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[deliverable/binutils-gdb.git] / bfd / elf32-arm.c
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252b5132 1/* 32-bit ELF support for ARM
6f2750fe 2 Copyright (C) 1998-2016 Free Software Foundation, Inc.
252b5132
RH		 3
4 This file is part of BFD, the Binary File Descriptor library.
5
6 This program is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
cd123cb7 8 the Free Software Foundation; either version 3 of the License, or
252b5132
RH		 9 (at your option) any later version.
10
11 This program is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
15
16 You should have received a copy of the GNU General Public License
17 along with this program; if not, write to the Free Software
cd123cb7
NC		 18 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
19 MA 02110-1301, USA. */
252b5132 20
6e6718a3 21#include "sysdep.h"
2468f9c9
PB		 22#include <limits.h>
23
3db64b00 24#include "bfd.h"
6034aab8 25#include "bfd_stdint.h"
00a97672 26#include "libiberty.h"
7f266840
DJ		 27#include "libbfd.h"
28#include "elf-bfd.h"
b38cadfb 29#include "elf-nacl.h"
00a97672 30#include "elf-vxworks.h"
ee065d83 31#include "elf/arm.h"
7f266840 32
00a97672
RS		 33/* Return the relocation section associated with NAME. HTAB is the
34 bfd's elf32_arm_link_hash_entry. */
35#define RELOC_SECTION(HTAB, NAME) \
36 ((HTAB)->use_rel ? ".rel" NAME : ".rela" NAME)
37
38/* Return size of a relocation entry. HTAB is the bfd's
39 elf32_arm_link_hash_entry. */
40#define RELOC_SIZE(HTAB) \
41 ((HTAB)->use_rel \
42 ? sizeof (Elf32_External_Rel) \
43 : sizeof (Elf32_External_Rela))
44
45/* Return function to swap relocations in. HTAB is the bfd's
46 elf32_arm_link_hash_entry. */
47#define SWAP_RELOC_IN(HTAB) \
48 ((HTAB)->use_rel \
49 ? bfd_elf32_swap_reloc_in \
50 : bfd_elf32_swap_reloca_in)
51
52/* Return function to swap relocations out. HTAB is the bfd's
53 elf32_arm_link_hash_entry. */
54#define SWAP_RELOC_OUT(HTAB) \
55 ((HTAB)->use_rel \
56 ? bfd_elf32_swap_reloc_out \
57 : bfd_elf32_swap_reloca_out)
58
7f266840
DJ		 59#define elf_info_to_howto 0
60#define elf_info_to_howto_rel elf32_arm_info_to_howto
61
62#define ARM_ELF_ABI_VERSION 0
63#define ARM_ELF_OS_ABI_VERSION ELFOSABI_ARM
64
79f08007
YZ		 65/* The Adjusted Place, as defined by AAELF. */
66#define Pa(X) ((X) & 0xfffffffc)
67
3e6b1042
DJ		 68static bfd_boolean elf32_arm_write_section (bfd *output_bfd,
69 struct bfd_link_info *link_info,
70 asection *sec,
71 bfd_byte *contents);
72
7f266840
DJ		 73/* Note: code such as elf32_arm_reloc_type_lookup expect to use e.g.
74 R_ARM_PC24 as an index into this, and find the R_ARM_PC24 HOWTO
75 in that slot. */
76
c19d1205 77static reloc_howto_type elf32_arm_howto_table_1[] =
7f266840 78{
8029a119 79 /* No relocation. */
7f266840
DJ		 80 HOWTO (R_ARM_NONE, /* type */
81 0, /* rightshift */
6346d5ca 82 3, /* size (0 = byte, 1 = short, 2 = long) */
7f266840
DJ		 83 0, /* bitsize */
84 FALSE, /* pc_relative */
85 0, /* bitpos */
86 complain_overflow_dont,/* complain_on_overflow */
87 bfd_elf_generic_reloc, /* special_function */
88 "R_ARM_NONE", /* name */
89 FALSE, /* partial_inplace */
90 0, /* src_mask */
91 0, /* dst_mask */
92 FALSE), /* pcrel_offset */
93
94 HOWTO (R_ARM_PC24, /* type */
95 2, /* rightshift */
96 2, /* size (0 = byte, 1 = short, 2 = long) */
97 24, /* bitsize */
98 TRUE, /* pc_relative */
99 0, /* bitpos */
100 complain_overflow_signed,/* complain_on_overflow */
101 bfd_elf_generic_reloc, /* special_function */
102 "R_ARM_PC24", /* name */
103 FALSE, /* partial_inplace */
104 0x00ffffff, /* src_mask */
105 0x00ffffff, /* dst_mask */
106 TRUE), /* pcrel_offset */
107
108 /* 32 bit absolute */
109 HOWTO (R_ARM_ABS32, /* type */
110 0, /* rightshift */
111 2, /* size (0 = byte, 1 = short, 2 = long) */
112 32, /* bitsize */
113 FALSE, /* pc_relative */
114 0, /* bitpos */
115 complain_overflow_bitfield,/* complain_on_overflow */
116 bfd_elf_generic_reloc, /* special_function */
117 "R_ARM_ABS32", /* name */
118 FALSE, /* partial_inplace */
119 0xffffffff, /* src_mask */
120 0xffffffff, /* dst_mask */
121 FALSE), /* pcrel_offset */
122
123 /* standard 32bit pc-relative reloc */
124 HOWTO (R_ARM_REL32, /* type */
125 0, /* rightshift */
126 2, /* size (0 = byte, 1 = short, 2 = long) */
127 32, /* bitsize */
128 TRUE, /* pc_relative */
129 0, /* bitpos */
130 complain_overflow_bitfield,/* complain_on_overflow */
131 bfd_elf_generic_reloc, /* special_function */
132 "R_ARM_REL32", /* name */
133 FALSE, /* partial_inplace */
134 0xffffffff, /* src_mask */
135 0xffffffff, /* dst_mask */
136 TRUE), /* pcrel_offset */
137
c19d1205 138 /* 8 bit absolute - R_ARM_LDR_PC_G0 in AAELF */
4962c51a 139 HOWTO (R_ARM_LDR_PC_G0, /* type */
7f266840
DJ		 140 0, /* rightshift */
141 0, /* size (0 = byte, 1 = short, 2 = long) */
4962c51a
MS		 142 32, /* bitsize */
143 TRUE, /* pc_relative */
7f266840 144 0, /* bitpos */
4962c51a 145 complain_overflow_dont,/* complain_on_overflow */
7f266840 146 bfd_elf_generic_reloc, /* special_function */
4962c51a 147 "R_ARM_LDR_PC_G0", /* name */
7f266840 148 FALSE, /* partial_inplace */
4962c51a
MS		 149 0xffffffff, /* src_mask */
150 0xffffffff, /* dst_mask */
151 TRUE), /* pcrel_offset */
7f266840
DJ		 152
153 /* 16 bit absolute */
154 HOWTO (R_ARM_ABS16, /* type */
155 0, /* rightshift */
156 1, /* size (0 = byte, 1 = short, 2 = long) */
157 16, /* bitsize */
158 FALSE, /* pc_relative */
159 0, /* bitpos */
160 complain_overflow_bitfield,/* complain_on_overflow */
161 bfd_elf_generic_reloc, /* special_function */
162 "R_ARM_ABS16", /* name */
163 FALSE, /* partial_inplace */
164 0x0000ffff, /* src_mask */
165 0x0000ffff, /* dst_mask */
166 FALSE), /* pcrel_offset */
167
168 /* 12 bit absolute */
169 HOWTO (R_ARM_ABS12, /* type */
170 0, /* rightshift */
171 2, /* size (0 = byte, 1 = short, 2 = long) */
172 12, /* bitsize */
173 FALSE, /* pc_relative */
174 0, /* bitpos */
175 complain_overflow_bitfield,/* complain_on_overflow */
176 bfd_elf_generic_reloc, /* special_function */
177 "R_ARM_ABS12", /* name */
178 FALSE, /* partial_inplace */
00a97672
RS		 179 0x00000fff, /* src_mask */
180 0x00000fff, /* dst_mask */
7f266840
DJ		 181 FALSE), /* pcrel_offset */
182
183 HOWTO (R_ARM_THM_ABS5, /* type */
184 6, /* rightshift */
185 1, /* size (0 = byte, 1 = short, 2 = long) */
186 5, /* bitsize */
187 FALSE, /* pc_relative */
188 0, /* bitpos */
189 complain_overflow_bitfield,/* complain_on_overflow */
190 bfd_elf_generic_reloc, /* special_function */
191 "R_ARM_THM_ABS5", /* name */
192 FALSE, /* partial_inplace */
193 0x000007e0, /* src_mask */
194 0x000007e0, /* dst_mask */
195 FALSE), /* pcrel_offset */
196
197 /* 8 bit absolute */
198 HOWTO (R_ARM_ABS8, /* type */
199 0, /* rightshift */
200 0, /* size (0 = byte, 1 = short, 2 = long) */
201 8, /* bitsize */
202 FALSE, /* pc_relative */
203 0, /* bitpos */
204 complain_overflow_bitfield,/* complain_on_overflow */
205 bfd_elf_generic_reloc, /* special_function */
206 "R_ARM_ABS8", /* name */
207 FALSE, /* partial_inplace */
208 0x000000ff, /* src_mask */
209 0x000000ff, /* dst_mask */
210 FALSE), /* pcrel_offset */
211
212 HOWTO (R_ARM_SBREL32, /* type */
213 0, /* rightshift */
214 2, /* size (0 = byte, 1 = short, 2 = long) */
215 32, /* bitsize */
216 FALSE, /* pc_relative */
217 0, /* bitpos */
218 complain_overflow_dont,/* complain_on_overflow */
219 bfd_elf_generic_reloc, /* special_function */
220 "R_ARM_SBREL32", /* name */
221 FALSE, /* partial_inplace */
222 0xffffffff, /* src_mask */
223 0xffffffff, /* dst_mask */
224 FALSE), /* pcrel_offset */
225
c19d1205 226 HOWTO (R_ARM_THM_CALL, /* type */
7f266840
DJ		 227 1, /* rightshift */
228 2, /* size (0 = byte, 1 = short, 2 = long) */
f6ebfac0 229 24, /* bitsize */
7f266840
DJ		 230 TRUE, /* pc_relative */
231 0, /* bitpos */
232 complain_overflow_signed,/* complain_on_overflow */
233 bfd_elf_generic_reloc, /* special_function */
c19d1205 234 "R_ARM_THM_CALL", /* name */
7f266840 235 FALSE, /* partial_inplace */
7f6ab9f8
AM		 236 0x07ff2fff, /* src_mask */
237 0x07ff2fff, /* dst_mask */
7f266840
DJ		 238 TRUE), /* pcrel_offset */
239
240 HOWTO (R_ARM_THM_PC8, /* type */
241 1, /* rightshift */
242 1, /* size (0 = byte, 1 = short, 2 = long) */
243 8, /* bitsize */
244 TRUE, /* pc_relative */
245 0, /* bitpos */
246 complain_overflow_signed,/* complain_on_overflow */
247 bfd_elf_generic_reloc, /* special_function */
248 "R_ARM_THM_PC8", /* name */
249 FALSE, /* partial_inplace */
250 0x000000ff, /* src_mask */
251 0x000000ff, /* dst_mask */
252 TRUE), /* pcrel_offset */
253
c19d1205 254 HOWTO (R_ARM_BREL_ADJ, /* type */
7f266840
DJ		 255 1, /* rightshift */
256 1, /* size (0 = byte, 1 = short, 2 = long) */
c19d1205
ZW		 257 32, /* bitsize */
258 FALSE, /* pc_relative */
7f266840
DJ		 259 0, /* bitpos */
260 complain_overflow_signed,/* complain_on_overflow */
261 bfd_elf_generic_reloc, /* special_function */
c19d1205 262 "R_ARM_BREL_ADJ", /* name */
7f266840 263 FALSE, /* partial_inplace */
c19d1205
ZW		 264 0xffffffff, /* src_mask */
265 0xffffffff, /* dst_mask */
266 FALSE), /* pcrel_offset */
7f266840 267
0855e32b 268 HOWTO (R_ARM_TLS_DESC, /* type */
7f266840 269 0, /* rightshift */
0855e32b
NS		 270 2, /* size (0 = byte, 1 = short, 2 = long) */
271 32, /* bitsize */
7f266840
DJ		 272 FALSE, /* pc_relative */
273 0, /* bitpos */
0855e32b 274 complain_overflow_bitfield,/* complain_on_overflow */
7f266840 275 bfd_elf_generic_reloc, /* special_function */
0855e32b 276 "R_ARM_TLS_DESC", /* name */
7f266840 277 FALSE, /* partial_inplace */
0855e32b
NS		 278 0xffffffff, /* src_mask */
279 0xffffffff, /* dst_mask */
7f266840
DJ		 280 FALSE), /* pcrel_offset */
281
282 HOWTO (R_ARM_THM_SWI8, /* type */
283 0, /* rightshift */
284 0, /* size (0 = byte, 1 = short, 2 = long) */
285 0, /* bitsize */
286 FALSE, /* pc_relative */
287 0, /* bitpos */
288 complain_overflow_signed,/* complain_on_overflow */
289 bfd_elf_generic_reloc, /* special_function */
290 "R_ARM_SWI8", /* name */
291 FALSE, /* partial_inplace */
292 0x00000000, /* src_mask */
293 0x00000000, /* dst_mask */
294 FALSE), /* pcrel_offset */
295
296 /* BLX instruction for the ARM. */
297 HOWTO (R_ARM_XPC25, /* type */
298 2, /* rightshift */
299 2, /* size (0 = byte, 1 = short, 2 = long) */
7f6ab9f8 300 24, /* bitsize */
7f266840
DJ		 301 TRUE, /* pc_relative */
302 0, /* bitpos */
303 complain_overflow_signed,/* complain_on_overflow */
304 bfd_elf_generic_reloc, /* special_function */
305 "R_ARM_XPC25", /* name */
306 FALSE, /* partial_inplace */
307 0x00ffffff, /* src_mask */
308 0x00ffffff, /* dst_mask */
309 TRUE), /* pcrel_offset */
310
311 /* BLX instruction for the Thumb. */
312 HOWTO (R_ARM_THM_XPC22, /* type */
313 2, /* rightshift */
314 2, /* size (0 = byte, 1 = short, 2 = long) */
7f6ab9f8 315 24, /* bitsize */
7f266840
DJ		 316 TRUE, /* pc_relative */
317 0, /* bitpos */
318 complain_overflow_signed,/* complain_on_overflow */
319 bfd_elf_generic_reloc, /* special_function */
320 "R_ARM_THM_XPC22", /* name */
321 FALSE, /* partial_inplace */
7f6ab9f8
AM		 322 0x07ff2fff, /* src_mask */
323 0x07ff2fff, /* dst_mask */
7f266840
DJ		 324 TRUE), /* pcrel_offset */
325
ba93b8ac 326 /* Dynamic TLS relocations. */
7f266840 327
ba93b8ac 328 HOWTO (R_ARM_TLS_DTPMOD32, /* type */
99059e56
RM		 329 0, /* rightshift */
330 2, /* size (0 = byte, 1 = short, 2 = long) */
331 32, /* bitsize */
332 FALSE, /* pc_relative */
333 0, /* bitpos */
334 complain_overflow_bitfield,/* complain_on_overflow */
335 bfd_elf_generic_reloc, /* special_function */
336 "R_ARM_TLS_DTPMOD32", /* name */
337 TRUE, /* partial_inplace */
338 0xffffffff, /* src_mask */
339 0xffffffff, /* dst_mask */
340 FALSE), /* pcrel_offset */
7f266840 341
ba93b8ac 342 HOWTO (R_ARM_TLS_DTPOFF32, /* type */
99059e56
RM		 343 0, /* rightshift */
344 2, /* size (0 = byte, 1 = short, 2 = long) */
345 32, /* bitsize */
346 FALSE, /* pc_relative */
347 0, /* bitpos */
348 complain_overflow_bitfield,/* complain_on_overflow */
349 bfd_elf_generic_reloc, /* special_function */
350 "R_ARM_TLS_DTPOFF32", /* name */
351 TRUE, /* partial_inplace */
352 0xffffffff, /* src_mask */
353 0xffffffff, /* dst_mask */
354 FALSE), /* pcrel_offset */
7f266840 355
ba93b8ac 356 HOWTO (R_ARM_TLS_TPOFF32, /* type */
99059e56
RM		 357 0, /* rightshift */
358 2, /* size (0 = byte, 1 = short, 2 = long) */
359 32, /* bitsize */
360 FALSE, /* pc_relative */
361 0, /* bitpos */
362 complain_overflow_bitfield,/* complain_on_overflow */
363 bfd_elf_generic_reloc, /* special_function */
364 "R_ARM_TLS_TPOFF32", /* name */
365 TRUE, /* partial_inplace */
366 0xffffffff, /* src_mask */
367 0xffffffff, /* dst_mask */
368 FALSE), /* pcrel_offset */
7f266840
DJ		 369
370 /* Relocs used in ARM Linux */
371
372 HOWTO (R_ARM_COPY, /* type */
99059e56
RM		 373 0, /* rightshift */
374 2, /* size (0 = byte, 1 = short, 2 = long) */
375 32, /* bitsize */
376 FALSE, /* pc_relative */
377 0, /* bitpos */
378 complain_overflow_bitfield,/* complain_on_overflow */
379 bfd_elf_generic_reloc, /* special_function */
380 "R_ARM_COPY", /* name */
381 TRUE, /* partial_inplace */
382 0xffffffff, /* src_mask */
383 0xffffffff, /* dst_mask */
384 FALSE), /* pcrel_offset */
7f266840
DJ		 385
386 HOWTO (R_ARM_GLOB_DAT, /* type */
99059e56
RM		 387 0, /* rightshift */
388 2, /* size (0 = byte, 1 = short, 2 = long) */
389 32, /* bitsize */
390 FALSE, /* pc_relative */
391 0, /* bitpos */
392 complain_overflow_bitfield,/* complain_on_overflow */
393 bfd_elf_generic_reloc, /* special_function */
394 "R_ARM_GLOB_DAT", /* name */
395 TRUE, /* partial_inplace */
396 0xffffffff, /* src_mask */
397 0xffffffff, /* dst_mask */
398 FALSE), /* pcrel_offset */
7f266840
DJ		 399
400 HOWTO (R_ARM_JUMP_SLOT, /* type */
99059e56
RM		 401 0, /* rightshift */
402 2, /* size (0 = byte, 1 = short, 2 = long) */
403 32, /* bitsize */
404 FALSE, /* pc_relative */
405 0, /* bitpos */
406 complain_overflow_bitfield,/* complain_on_overflow */
407 bfd_elf_generic_reloc, /* special_function */
408 "R_ARM_JUMP_SLOT", /* name */
409 TRUE, /* partial_inplace */
410 0xffffffff, /* src_mask */
411 0xffffffff, /* dst_mask */
412 FALSE), /* pcrel_offset */
7f266840
DJ		 413
414 HOWTO (R_ARM_RELATIVE, /* type */
99059e56
RM		 415 0, /* rightshift */
416 2, /* size (0 = byte, 1 = short, 2 = long) */
417 32, /* bitsize */
418 FALSE, /* pc_relative */
419 0, /* bitpos */
420 complain_overflow_bitfield,/* complain_on_overflow */
421 bfd_elf_generic_reloc, /* special_function */
422 "R_ARM_RELATIVE", /* name */
423 TRUE, /* partial_inplace */
424 0xffffffff, /* src_mask */
425 0xffffffff, /* dst_mask */
426 FALSE), /* pcrel_offset */
7f266840 427
c19d1205 428 HOWTO (R_ARM_GOTOFF32, /* type */
99059e56
RM		 429 0, /* rightshift */
430 2, /* size (0 = byte, 1 = short, 2 = long) */
431 32, /* bitsize */
432 FALSE, /* pc_relative */
433 0, /* bitpos */
434 complain_overflow_bitfield,/* complain_on_overflow */
435 bfd_elf_generic_reloc, /* special_function */
436 "R_ARM_GOTOFF32", /* name */
437 TRUE, /* partial_inplace */
438 0xffffffff, /* src_mask */
439 0xffffffff, /* dst_mask */
440 FALSE), /* pcrel_offset */
7f266840
DJ		 441
442 HOWTO (R_ARM_GOTPC, /* type */
99059e56
RM		 443 0, /* rightshift */
444 2, /* size (0 = byte, 1 = short, 2 = long) */
445 32, /* bitsize */
446 TRUE, /* pc_relative */
447 0, /* bitpos */
448 complain_overflow_bitfield,/* complain_on_overflow */
449 bfd_elf_generic_reloc, /* special_function */
450 "R_ARM_GOTPC", /* name */
451 TRUE, /* partial_inplace */
452 0xffffffff, /* src_mask */
453 0xffffffff, /* dst_mask */
454 TRUE), /* pcrel_offset */
7f266840
DJ		 455
456 HOWTO (R_ARM_GOT32, /* type */
99059e56
RM		 457 0, /* rightshift */
458 2, /* size (0 = byte, 1 = short, 2 = long) */
459 32, /* bitsize */
460 FALSE, /* pc_relative */
461 0, /* bitpos */
462 complain_overflow_bitfield,/* complain_on_overflow */
463 bfd_elf_generic_reloc, /* special_function */
464 "R_ARM_GOT32", /* name */
465 TRUE, /* partial_inplace */
466 0xffffffff, /* src_mask */
467 0xffffffff, /* dst_mask */
468 FALSE), /* pcrel_offset */
7f266840
DJ		 469
470 HOWTO (R_ARM_PLT32, /* type */
99059e56
RM		 471 2, /* rightshift */
472 2, /* size (0 = byte, 1 = short, 2 = long) */
473 24, /* bitsize */
474 TRUE, /* pc_relative */
475 0, /* bitpos */
476 complain_overflow_bitfield,/* complain_on_overflow */
477 bfd_elf_generic_reloc, /* special_function */
478 "R_ARM_PLT32", /* name */
479 FALSE, /* partial_inplace */
480 0x00ffffff, /* src_mask */
481 0x00ffffff, /* dst_mask */
482 TRUE), /* pcrel_offset */
7f266840
DJ		 483
484 HOWTO (R_ARM_CALL, /* type */
485 2, /* rightshift */
486 2, /* size (0 = byte, 1 = short, 2 = long) */
487 24, /* bitsize */
488 TRUE, /* pc_relative */
489 0, /* bitpos */
490 complain_overflow_signed,/* complain_on_overflow */
491 bfd_elf_generic_reloc, /* special_function */
492 "R_ARM_CALL", /* name */
493 FALSE, /* partial_inplace */
494 0x00ffffff, /* src_mask */
495 0x00ffffff, /* dst_mask */
496 TRUE), /* pcrel_offset */
497
498 HOWTO (R_ARM_JUMP24, /* type */
499 2, /* rightshift */
500 2, /* size (0 = byte, 1 = short, 2 = long) */
501 24, /* bitsize */
502 TRUE, /* pc_relative */
503 0, /* bitpos */
504 complain_overflow_signed,/* complain_on_overflow */
505 bfd_elf_generic_reloc, /* special_function */
506 "R_ARM_JUMP24", /* name */
507 FALSE, /* partial_inplace */
508 0x00ffffff, /* src_mask */
509 0x00ffffff, /* dst_mask */
510 TRUE), /* pcrel_offset */
511
c19d1205
ZW		 512 HOWTO (R_ARM_THM_JUMP24, /* type */
513 1, /* rightshift */
514 2, /* size (0 = byte, 1 = short, 2 = long) */
515 24, /* bitsize */
516 TRUE, /* pc_relative */
7f266840 517 0, /* bitpos */
c19d1205 518 complain_overflow_signed,/* complain_on_overflow */
7f266840 519 bfd_elf_generic_reloc, /* special_function */
c19d1205 520 "R_ARM_THM_JUMP24", /* name */
7f266840 521 FALSE, /* partial_inplace */
c19d1205
ZW		 522 0x07ff2fff, /* src_mask */
523 0x07ff2fff, /* dst_mask */
524 TRUE), /* pcrel_offset */
7f266840 525
c19d1205 526 HOWTO (R_ARM_BASE_ABS, /* type */
7f266840 527 0, /* rightshift */
c19d1205
ZW		 528 2, /* size (0 = byte, 1 = short, 2 = long) */
529 32, /* bitsize */
7f266840
DJ		 530 FALSE, /* pc_relative */
531 0, /* bitpos */
532 complain_overflow_dont,/* complain_on_overflow */
533 bfd_elf_generic_reloc, /* special_function */
c19d1205 534 "R_ARM_BASE_ABS", /* name */
7f266840 535 FALSE, /* partial_inplace */
c19d1205
ZW		 536 0xffffffff, /* src_mask */
537 0xffffffff, /* dst_mask */
7f266840
DJ		 538 FALSE), /* pcrel_offset */
539
540 HOWTO (R_ARM_ALU_PCREL7_0, /* type */
541 0, /* rightshift */
542 2, /* size (0 = byte, 1 = short, 2 = long) */
543 12, /* bitsize */
544 TRUE, /* pc_relative */
545 0, /* bitpos */
546 complain_overflow_dont,/* complain_on_overflow */
547 bfd_elf_generic_reloc, /* special_function */
548 "R_ARM_ALU_PCREL_7_0", /* name */
549 FALSE, /* partial_inplace */
550 0x00000fff, /* src_mask */
551 0x00000fff, /* dst_mask */
552 TRUE), /* pcrel_offset */
553
554 HOWTO (R_ARM_ALU_PCREL15_8, /* type */
555 0, /* rightshift */
556 2, /* size (0 = byte, 1 = short, 2 = long) */
557 12, /* bitsize */
558 TRUE, /* pc_relative */
559 8, /* bitpos */
560 complain_overflow_dont,/* complain_on_overflow */
561 bfd_elf_generic_reloc, /* special_function */
562 "R_ARM_ALU_PCREL_15_8",/* name */
563 FALSE, /* partial_inplace */
564 0x00000fff, /* src_mask */
565 0x00000fff, /* dst_mask */
566 TRUE), /* pcrel_offset */
567
568 HOWTO (R_ARM_ALU_PCREL23_15, /* type */
569 0, /* rightshift */
570 2, /* size (0 = byte, 1 = short, 2 = long) */
571 12, /* bitsize */
572 TRUE, /* pc_relative */
573 16, /* bitpos */
574 complain_overflow_dont,/* complain_on_overflow */
575 bfd_elf_generic_reloc, /* special_function */
576 "R_ARM_ALU_PCREL_23_15",/* name */
577 FALSE, /* partial_inplace */
578 0x00000fff, /* src_mask */
579 0x00000fff, /* dst_mask */
580 TRUE), /* pcrel_offset */
581
582 HOWTO (R_ARM_LDR_SBREL_11_0, /* type */
583 0, /* rightshift */
584 2, /* size (0 = byte, 1 = short, 2 = long) */
585 12, /* bitsize */
586 FALSE, /* pc_relative */
587 0, /* bitpos */
588 complain_overflow_dont,/* complain_on_overflow */
589 bfd_elf_generic_reloc, /* special_function */
590 "R_ARM_LDR_SBREL_11_0",/* name */
591 FALSE, /* partial_inplace */
592 0x00000fff, /* src_mask */
593 0x00000fff, /* dst_mask */
594 FALSE), /* pcrel_offset */
595
596 HOWTO (R_ARM_ALU_SBREL_19_12, /* type */
597 0, /* rightshift */
598 2, /* size (0 = byte, 1 = short, 2 = long) */
599 8, /* bitsize */
600 FALSE, /* pc_relative */
601 12, /* bitpos */
602 complain_overflow_dont,/* complain_on_overflow */
603 bfd_elf_generic_reloc, /* special_function */
604 "R_ARM_ALU_SBREL_19_12",/* name */
605 FALSE, /* partial_inplace */
606 0x000ff000, /* src_mask */
607 0x000ff000, /* dst_mask */
608 FALSE), /* pcrel_offset */
609
610 HOWTO (R_ARM_ALU_SBREL_27_20, /* type */
611 0, /* rightshift */
612 2, /* size (0 = byte, 1 = short, 2 = long) */
613 8, /* bitsize */
614 FALSE, /* pc_relative */
615 20, /* bitpos */
616 complain_overflow_dont,/* complain_on_overflow */
617 bfd_elf_generic_reloc, /* special_function */
618 "R_ARM_ALU_SBREL_27_20",/* name */
619 FALSE, /* partial_inplace */
620 0x0ff00000, /* src_mask */
621 0x0ff00000, /* dst_mask */
622 FALSE), /* pcrel_offset */
623
624 HOWTO (R_ARM_TARGET1, /* type */
625 0, /* rightshift */
626 2, /* size (0 = byte, 1 = short, 2 = long) */
627 32, /* bitsize */
628 FALSE, /* pc_relative */
629 0, /* bitpos */
630 complain_overflow_dont,/* complain_on_overflow */
631 bfd_elf_generic_reloc, /* special_function */
632 "R_ARM_TARGET1", /* name */
633 FALSE, /* partial_inplace */
634 0xffffffff, /* src_mask */
635 0xffffffff, /* dst_mask */
636 FALSE), /* pcrel_offset */
637
638 HOWTO (R_ARM_ROSEGREL32, /* type */
639 0, /* rightshift */
640 2, /* size (0 = byte, 1 = short, 2 = long) */
641 32, /* bitsize */
642 FALSE, /* pc_relative */
643 0, /* bitpos */
644 complain_overflow_dont,/* complain_on_overflow */
645 bfd_elf_generic_reloc, /* special_function */
646 "R_ARM_ROSEGREL32", /* name */
647 FALSE, /* partial_inplace */
648 0xffffffff, /* src_mask */
649 0xffffffff, /* dst_mask */
650 FALSE), /* pcrel_offset */
651
652 HOWTO (R_ARM_V4BX, /* type */
653 0, /* rightshift */
654 2, /* size (0 = byte, 1 = short, 2 = long) */
655 32, /* bitsize */
656 FALSE, /* pc_relative */
657 0, /* bitpos */
658 complain_overflow_dont,/* complain_on_overflow */
659 bfd_elf_generic_reloc, /* special_function */
660 "R_ARM_V4BX", /* name */
661 FALSE, /* partial_inplace */
662 0xffffffff, /* src_mask */
663 0xffffffff, /* dst_mask */
664 FALSE), /* pcrel_offset */
665
666 HOWTO (R_ARM_TARGET2, /* type */
667 0, /* rightshift */
668 2, /* size (0 = byte, 1 = short, 2 = long) */
669 32, /* bitsize */
670 FALSE, /* pc_relative */
671 0, /* bitpos */
672 complain_overflow_signed,/* complain_on_overflow */
673 bfd_elf_generic_reloc, /* special_function */
674 "R_ARM_TARGET2", /* name */
675 FALSE, /* partial_inplace */
676 0xffffffff, /* src_mask */
677 0xffffffff, /* dst_mask */
678 TRUE), /* pcrel_offset */
679
680 HOWTO (R_ARM_PREL31, /* type */
681 0, /* rightshift */
682 2, /* size (0 = byte, 1 = short, 2 = long) */
683 31, /* bitsize */
684 TRUE, /* pc_relative */
685 0, /* bitpos */
686 complain_overflow_signed,/* complain_on_overflow */
687 bfd_elf_generic_reloc, /* special_function */
688 "R_ARM_PREL31", /* name */
689 FALSE, /* partial_inplace */
690 0x7fffffff, /* src_mask */
691 0x7fffffff, /* dst_mask */
692 TRUE), /* pcrel_offset */
c19d1205
ZW		 693
694 HOWTO (R_ARM_MOVW_ABS_NC, /* type */
695 0, /* rightshift */
696 2, /* size (0 = byte, 1 = short, 2 = long) */
697 16, /* bitsize */
698 FALSE, /* pc_relative */
699 0, /* bitpos */
700 complain_overflow_dont,/* complain_on_overflow */
701 bfd_elf_generic_reloc, /* special_function */
702 "R_ARM_MOVW_ABS_NC", /* name */
703 FALSE, /* partial_inplace */
39623e12
PB		 704 0x000f0fff, /* src_mask */
705 0x000f0fff, /* dst_mask */
c19d1205
ZW		 706 FALSE), /* pcrel_offset */
707
708 HOWTO (R_ARM_MOVT_ABS, /* type */
709 0, /* rightshift */
710 2, /* size (0 = byte, 1 = short, 2 = long) */
711 16, /* bitsize */
712 FALSE, /* pc_relative */
713 0, /* bitpos */
714 complain_overflow_bitfield,/* complain_on_overflow */
715 bfd_elf_generic_reloc, /* special_function */
716 "R_ARM_MOVT_ABS", /* name */
717 FALSE, /* partial_inplace */
39623e12
PB		 718 0x000f0fff, /* src_mask */
719 0x000f0fff, /* dst_mask */
c19d1205
ZW		 720 FALSE), /* pcrel_offset */
721
722 HOWTO (R_ARM_MOVW_PREL_NC, /* type */
723 0, /* rightshift */
724 2, /* size (0 = byte, 1 = short, 2 = long) */
725 16, /* bitsize */
726 TRUE, /* pc_relative */
727 0, /* bitpos */
728 complain_overflow_dont,/* complain_on_overflow */
729 bfd_elf_generic_reloc, /* special_function */
730 "R_ARM_MOVW_PREL_NC", /* name */
731 FALSE, /* partial_inplace */
39623e12
PB		 732 0x000f0fff, /* src_mask */
733 0x000f0fff, /* dst_mask */
c19d1205
ZW		 734 TRUE), /* pcrel_offset */
735
736 HOWTO (R_ARM_MOVT_PREL, /* type */
737 0, /* rightshift */
738 2, /* size (0 = byte, 1 = short, 2 = long) */
739 16, /* bitsize */
740 TRUE, /* pc_relative */
741 0, /* bitpos */
742 complain_overflow_bitfield,/* complain_on_overflow */
743 bfd_elf_generic_reloc, /* special_function */
744 "R_ARM_MOVT_PREL", /* name */
745 FALSE, /* partial_inplace */
39623e12
PB		 746 0x000f0fff, /* src_mask */
747 0x000f0fff, /* dst_mask */
c19d1205
ZW		 748 TRUE), /* pcrel_offset */
749
750 HOWTO (R_ARM_THM_MOVW_ABS_NC, /* type */
751 0, /* rightshift */
752 2, /* size (0 = byte, 1 = short, 2 = long) */
753 16, /* bitsize */
754 FALSE, /* pc_relative */
755 0, /* bitpos */
756 complain_overflow_dont,/* complain_on_overflow */
757 bfd_elf_generic_reloc, /* special_function */
758 "R_ARM_THM_MOVW_ABS_NC",/* name */
759 FALSE, /* partial_inplace */
760 0x040f70ff, /* src_mask */
761 0x040f70ff, /* dst_mask */
762 FALSE), /* pcrel_offset */
763
764 HOWTO (R_ARM_THM_MOVT_ABS, /* type */
765 0, /* rightshift */
766 2, /* size (0 = byte, 1 = short, 2 = long) */
767 16, /* bitsize */
768 FALSE, /* pc_relative */
769 0, /* bitpos */
770 complain_overflow_bitfield,/* complain_on_overflow */
771 bfd_elf_generic_reloc, /* special_function */
772 "R_ARM_THM_MOVT_ABS", /* name */
773 FALSE, /* partial_inplace */
774 0x040f70ff, /* src_mask */
775 0x040f70ff, /* dst_mask */
776 FALSE), /* pcrel_offset */
777
778 HOWTO (R_ARM_THM_MOVW_PREL_NC,/* type */
779 0, /* rightshift */
780 2, /* size (0 = byte, 1 = short, 2 = long) */
781 16, /* bitsize */
782 TRUE, /* pc_relative */
783 0, /* bitpos */
784 complain_overflow_dont,/* complain_on_overflow */
785 bfd_elf_generic_reloc, /* special_function */
786 "R_ARM_THM_MOVW_PREL_NC",/* name */
787 FALSE, /* partial_inplace */
788 0x040f70ff, /* src_mask */
789 0x040f70ff, /* dst_mask */
790 TRUE), /* pcrel_offset */
791
792 HOWTO (R_ARM_THM_MOVT_PREL, /* type */
793 0, /* rightshift */
794 2, /* size (0 = byte, 1 = short, 2 = long) */
795 16, /* bitsize */
796 TRUE, /* pc_relative */
797 0, /* bitpos */
798 complain_overflow_bitfield,/* complain_on_overflow */
799 bfd_elf_generic_reloc, /* special_function */
800 "R_ARM_THM_MOVT_PREL", /* name */
801 FALSE, /* partial_inplace */
802 0x040f70ff, /* src_mask */
803 0x040f70ff, /* dst_mask */
804 TRUE), /* pcrel_offset */
805
806 HOWTO (R_ARM_THM_JUMP19, /* type */
807 1, /* rightshift */
808 2, /* size (0 = byte, 1 = short, 2 = long) */
809 19, /* bitsize */
810 TRUE, /* pc_relative */
811 0, /* bitpos */
812 complain_overflow_signed,/* complain_on_overflow */
813 bfd_elf_generic_reloc, /* special_function */
814 "R_ARM_THM_JUMP19", /* name */
815 FALSE, /* partial_inplace */
816 0x043f2fff, /* src_mask */
817 0x043f2fff, /* dst_mask */
818 TRUE), /* pcrel_offset */
819
820 HOWTO (R_ARM_THM_JUMP6, /* type */
821 1, /* rightshift */
822 1, /* size (0 = byte, 1 = short, 2 = long) */
823 6, /* bitsize */
824 TRUE, /* pc_relative */
825 0, /* bitpos */
826 complain_overflow_unsigned,/* complain_on_overflow */
827 bfd_elf_generic_reloc, /* special_function */
828 "R_ARM_THM_JUMP6", /* name */
829 FALSE, /* partial_inplace */
830 0x02f8, /* src_mask */
831 0x02f8, /* dst_mask */
832 TRUE), /* pcrel_offset */
833
834 /* These are declared as 13-bit signed relocations because we can
835 address -4095 .. 4095(base) by altering ADDW to SUBW or vice
836 versa. */
837 HOWTO (R_ARM_THM_ALU_PREL_11_0,/* type */
838 0, /* rightshift */
839 2, /* size (0 = byte, 1 = short, 2 = long) */
840 13, /* bitsize */
841 TRUE, /* pc_relative */
842 0, /* bitpos */
2cab6cc3 843 complain_overflow_dont,/* complain_on_overflow */
c19d1205
ZW		 844 bfd_elf_generic_reloc, /* special_function */
845 "R_ARM_THM_ALU_PREL_11_0",/* name */
846 FALSE, /* partial_inplace */
2cab6cc3
MS		 847 0xffffffff, /* src_mask */
848 0xffffffff, /* dst_mask */
c19d1205
ZW		 849 TRUE), /* pcrel_offset */
850
851 HOWTO (R_ARM_THM_PC12, /* type */
852 0, /* rightshift */
853 2, /* size (0 = byte, 1 = short, 2 = long) */
854 13, /* bitsize */
855 TRUE, /* pc_relative */
856 0, /* bitpos */
2cab6cc3 857 complain_overflow_dont,/* complain_on_overflow */
c19d1205
ZW		 858 bfd_elf_generic_reloc, /* special_function */
859 "R_ARM_THM_PC12", /* name */
860 FALSE, /* partial_inplace */
2cab6cc3
MS		 861 0xffffffff, /* src_mask */
862 0xffffffff, /* dst_mask */
c19d1205
ZW		 863 TRUE), /* pcrel_offset */
864
865 HOWTO (R_ARM_ABS32_NOI, /* type */
866 0, /* rightshift */
867 2, /* size (0 = byte, 1 = short, 2 = long) */
868 32, /* bitsize */
869 FALSE, /* pc_relative */
870 0, /* bitpos */
871 complain_overflow_dont,/* complain_on_overflow */
872 bfd_elf_generic_reloc, /* special_function */
873 "R_ARM_ABS32_NOI", /* name */
874 FALSE, /* partial_inplace */
875 0xffffffff, /* src_mask */
876 0xffffffff, /* dst_mask */
877 FALSE), /* pcrel_offset */
878
879 HOWTO (R_ARM_REL32_NOI, /* type */
880 0, /* rightshift */
881 2, /* size (0 = byte, 1 = short, 2 = long) */
882 32, /* bitsize */
883 TRUE, /* pc_relative */
884 0, /* bitpos */
885 complain_overflow_dont,/* complain_on_overflow */
886 bfd_elf_generic_reloc, /* special_function */
887 "R_ARM_REL32_NOI", /* name */
888 FALSE, /* partial_inplace */
889 0xffffffff, /* src_mask */
890 0xffffffff, /* dst_mask */
891 FALSE), /* pcrel_offset */
7f266840 892
4962c51a
MS		 893 /* Group relocations. */
894
895 HOWTO (R_ARM_ALU_PC_G0_NC, /* type */
896 0, /* rightshift */
897 2, /* size (0 = byte, 1 = short, 2 = long) */
898 32, /* bitsize */
899 TRUE, /* pc_relative */
900 0, /* bitpos */
901 complain_overflow_dont,/* complain_on_overflow */
902 bfd_elf_generic_reloc, /* special_function */
903 "R_ARM_ALU_PC_G0_NC", /* name */
904 FALSE, /* partial_inplace */
905 0xffffffff, /* src_mask */
906 0xffffffff, /* dst_mask */
907 TRUE), /* pcrel_offset */
908
909 HOWTO (R_ARM_ALU_PC_G0, /* type */
910 0, /* rightshift */
911 2, /* size (0 = byte, 1 = short, 2 = long) */
912 32, /* bitsize */
913 TRUE, /* pc_relative */
914 0, /* bitpos */
915 complain_overflow_dont,/* complain_on_overflow */
916 bfd_elf_generic_reloc, /* special_function */
917 "R_ARM_ALU_PC_G0", /* name */
918 FALSE, /* partial_inplace */
919 0xffffffff, /* src_mask */
920 0xffffffff, /* dst_mask */
921 TRUE), /* pcrel_offset */
922
923 HOWTO (R_ARM_ALU_PC_G1_NC, /* type */
924 0, /* rightshift */
925 2, /* size (0 = byte, 1 = short, 2 = long) */
926 32, /* bitsize */
927 TRUE, /* pc_relative */
928 0, /* bitpos */
929 complain_overflow_dont,/* complain_on_overflow */
930 bfd_elf_generic_reloc, /* special_function */
931 "R_ARM_ALU_PC_G1_NC", /* name */
932 FALSE, /* partial_inplace */
933 0xffffffff, /* src_mask */
934 0xffffffff, /* dst_mask */
935 TRUE), /* pcrel_offset */
936
937 HOWTO (R_ARM_ALU_PC_G1, /* type */
938 0, /* rightshift */
939 2, /* size (0 = byte, 1 = short, 2 = long) */
940 32, /* bitsize */
941 TRUE, /* pc_relative */
942 0, /* bitpos */
943 complain_overflow_dont,/* complain_on_overflow */
944 bfd_elf_generic_reloc, /* special_function */
945 "R_ARM_ALU_PC_G1", /* name */
946 FALSE, /* partial_inplace */
947 0xffffffff, /* src_mask */
948 0xffffffff, /* dst_mask */
949 TRUE), /* pcrel_offset */
950
951 HOWTO (R_ARM_ALU_PC_G2, /* type */
952 0, /* rightshift */
953 2, /* size (0 = byte, 1 = short, 2 = long) */
954 32, /* bitsize */
955 TRUE, /* pc_relative */
956 0, /* bitpos */
957 complain_overflow_dont,/* complain_on_overflow */
958 bfd_elf_generic_reloc, /* special_function */
959 "R_ARM_ALU_PC_G2", /* name */
960 FALSE, /* partial_inplace */
961 0xffffffff, /* src_mask */
962 0xffffffff, /* dst_mask */
963 TRUE), /* pcrel_offset */
964
965 HOWTO (R_ARM_LDR_PC_G1, /* type */
966 0, /* rightshift */
967 2, /* size (0 = byte, 1 = short, 2 = long) */
968 32, /* bitsize */
969 TRUE, /* pc_relative */
970 0, /* bitpos */
971 complain_overflow_dont,/* complain_on_overflow */
972 bfd_elf_generic_reloc, /* special_function */
973 "R_ARM_LDR_PC_G1", /* name */
974 FALSE, /* partial_inplace */
975 0xffffffff, /* src_mask */
976 0xffffffff, /* dst_mask */
977 TRUE), /* pcrel_offset */
978
979 HOWTO (R_ARM_LDR_PC_G2, /* type */
980 0, /* rightshift */
981 2, /* size (0 = byte, 1 = short, 2 = long) */
982 32, /* bitsize */
983 TRUE, /* pc_relative */
984 0, /* bitpos */
985 complain_overflow_dont,/* complain_on_overflow */
986 bfd_elf_generic_reloc, /* special_function */
987 "R_ARM_LDR_PC_G2", /* name */
988 FALSE, /* partial_inplace */
989 0xffffffff, /* src_mask */
990 0xffffffff, /* dst_mask */
991 TRUE), /* pcrel_offset */
992
993 HOWTO (R_ARM_LDRS_PC_G0, /* type */
994 0, /* rightshift */
995 2, /* size (0 = byte, 1 = short, 2 = long) */
996 32, /* bitsize */
997 TRUE, /* pc_relative */
998 0, /* bitpos */
999 complain_overflow_dont,/* complain_on_overflow */
1000 bfd_elf_generic_reloc, /* special_function */
1001 "R_ARM_LDRS_PC_G0", /* name */
1002 FALSE, /* partial_inplace */
1003 0xffffffff, /* src_mask */
1004 0xffffffff, /* dst_mask */
1005 TRUE), /* pcrel_offset */
1006
1007 HOWTO (R_ARM_LDRS_PC_G1, /* type */
1008 0, /* rightshift */
1009 2, /* size (0 = byte, 1 = short, 2 = long) */
1010 32, /* bitsize */
1011 TRUE, /* pc_relative */
1012 0, /* bitpos */
1013 complain_overflow_dont,/* complain_on_overflow */
1014 bfd_elf_generic_reloc, /* special_function */
1015 "R_ARM_LDRS_PC_G1", /* name */
1016 FALSE, /* partial_inplace */
1017 0xffffffff, /* src_mask */
1018 0xffffffff, /* dst_mask */
1019 TRUE), /* pcrel_offset */
1020
1021 HOWTO (R_ARM_LDRS_PC_G2, /* type */
1022 0, /* rightshift */
1023 2, /* size (0 = byte, 1 = short, 2 = long) */
1024 32, /* bitsize */
1025 TRUE, /* pc_relative */
1026 0, /* bitpos */
1027 complain_overflow_dont,/* complain_on_overflow */
1028 bfd_elf_generic_reloc, /* special_function */
1029 "R_ARM_LDRS_PC_G2", /* name */
1030 FALSE, /* partial_inplace */
1031 0xffffffff, /* src_mask */
1032 0xffffffff, /* dst_mask */
1033 TRUE), /* pcrel_offset */
1034
1035 HOWTO (R_ARM_LDC_PC_G0, /* type */
1036 0, /* rightshift */
1037 2, /* size (0 = byte, 1 = short, 2 = long) */
1038 32, /* bitsize */
1039 TRUE, /* pc_relative */
1040 0, /* bitpos */
1041 complain_overflow_dont,/* complain_on_overflow */
1042 bfd_elf_generic_reloc, /* special_function */
1043 "R_ARM_LDC_PC_G0", /* name */
1044 FALSE, /* partial_inplace */
1045 0xffffffff, /* src_mask */
1046 0xffffffff, /* dst_mask */
1047 TRUE), /* pcrel_offset */
1048
1049 HOWTO (R_ARM_LDC_PC_G1, /* type */
1050 0, /* rightshift */
1051 2, /* size (0 = byte, 1 = short, 2 = long) */
1052 32, /* bitsize */
1053 TRUE, /* pc_relative */
1054 0, /* bitpos */
1055 complain_overflow_dont,/* complain_on_overflow */
1056 bfd_elf_generic_reloc, /* special_function */
1057 "R_ARM_LDC_PC_G1", /* name */
1058 FALSE, /* partial_inplace */
1059 0xffffffff, /* src_mask */
1060 0xffffffff, /* dst_mask */
1061 TRUE), /* pcrel_offset */
1062
1063 HOWTO (R_ARM_LDC_PC_G2, /* type */
1064 0, /* rightshift */
1065 2, /* size (0 = byte, 1 = short, 2 = long) */
1066 32, /* bitsize */
1067 TRUE, /* pc_relative */
1068 0, /* bitpos */
1069 complain_overflow_dont,/* complain_on_overflow */
1070 bfd_elf_generic_reloc, /* special_function */
1071 "R_ARM_LDC_PC_G2", /* name */
1072 FALSE, /* partial_inplace */
1073 0xffffffff, /* src_mask */
1074 0xffffffff, /* dst_mask */
1075 TRUE), /* pcrel_offset */
1076
1077 HOWTO (R_ARM_ALU_SB_G0_NC, /* type */
1078 0, /* rightshift */
1079 2, /* size (0 = byte, 1 = short, 2 = long) */
1080 32, /* bitsize */
1081 TRUE, /* pc_relative */
1082 0, /* bitpos */
1083 complain_overflow_dont,/* complain_on_overflow */
1084 bfd_elf_generic_reloc, /* special_function */
1085 "R_ARM_ALU_SB_G0_NC", /* name */
1086 FALSE, /* partial_inplace */
1087 0xffffffff, /* src_mask */
1088 0xffffffff, /* dst_mask */
1089 TRUE), /* pcrel_offset */
1090
1091 HOWTO (R_ARM_ALU_SB_G0, /* type */
1092 0, /* rightshift */
1093 2, /* size (0 = byte, 1 = short, 2 = long) */
1094 32, /* bitsize */
1095 TRUE, /* pc_relative */
1096 0, /* bitpos */
1097 complain_overflow_dont,/* complain_on_overflow */
1098 bfd_elf_generic_reloc, /* special_function */
1099 "R_ARM_ALU_SB_G0", /* name */
1100 FALSE, /* partial_inplace */
1101 0xffffffff, /* src_mask */
1102 0xffffffff, /* dst_mask */
1103 TRUE), /* pcrel_offset */
1104
1105 HOWTO (R_ARM_ALU_SB_G1_NC, /* type */
1106 0, /* rightshift */
1107 2, /* size (0 = byte, 1 = short, 2 = long) */
1108 32, /* bitsize */
1109 TRUE, /* pc_relative */
1110 0, /* bitpos */
1111 complain_overflow_dont,/* complain_on_overflow */
1112 bfd_elf_generic_reloc, /* special_function */
1113 "R_ARM_ALU_SB_G1_NC", /* name */
1114 FALSE, /* partial_inplace */
1115 0xffffffff, /* src_mask */
1116 0xffffffff, /* dst_mask */
1117 TRUE), /* pcrel_offset */
1118
1119 HOWTO (R_ARM_ALU_SB_G1, /* type */
1120 0, /* rightshift */
1121 2, /* size (0 = byte, 1 = short, 2 = long) */
1122 32, /* bitsize */
1123 TRUE, /* pc_relative */
1124 0, /* bitpos */
1125 complain_overflow_dont,/* complain_on_overflow */
1126 bfd_elf_generic_reloc, /* special_function */
1127 "R_ARM_ALU_SB_G1", /* name */
1128 FALSE, /* partial_inplace */
1129 0xffffffff, /* src_mask */
1130 0xffffffff, /* dst_mask */
1131 TRUE), /* pcrel_offset */
1132
1133 HOWTO (R_ARM_ALU_SB_G2, /* type */
1134 0, /* rightshift */
1135 2, /* size (0 = byte, 1 = short, 2 = long) */
1136 32, /* bitsize */
1137 TRUE, /* pc_relative */
1138 0, /* bitpos */
1139 complain_overflow_dont,/* complain_on_overflow */
1140 bfd_elf_generic_reloc, /* special_function */
1141 "R_ARM_ALU_SB_G2", /* name */
1142 FALSE, /* partial_inplace */
1143 0xffffffff, /* src_mask */
1144 0xffffffff, /* dst_mask */
1145 TRUE), /* pcrel_offset */
1146
1147 HOWTO (R_ARM_LDR_SB_G0, /* type */
1148 0, /* rightshift */
1149 2, /* size (0 = byte, 1 = short, 2 = long) */
1150 32, /* bitsize */
1151 TRUE, /* pc_relative */
1152 0, /* bitpos */
1153 complain_overflow_dont,/* complain_on_overflow */
1154 bfd_elf_generic_reloc, /* special_function */
1155 "R_ARM_LDR_SB_G0", /* name */
1156 FALSE, /* partial_inplace */
1157 0xffffffff, /* src_mask */
1158 0xffffffff, /* dst_mask */
1159 TRUE), /* pcrel_offset */
1160
1161 HOWTO (R_ARM_LDR_SB_G1, /* type */
1162 0, /* rightshift */
1163 2, /* size (0 = byte, 1 = short, 2 = long) */
1164 32, /* bitsize */
1165 TRUE, /* pc_relative */
1166 0, /* bitpos */
1167 complain_overflow_dont,/* complain_on_overflow */
1168 bfd_elf_generic_reloc, /* special_function */
1169 "R_ARM_LDR_SB_G1", /* name */
1170 FALSE, /* partial_inplace */
1171 0xffffffff, /* src_mask */
1172 0xffffffff, /* dst_mask */
1173 TRUE), /* pcrel_offset */
1174
1175 HOWTO (R_ARM_LDR_SB_G2, /* type */
1176 0, /* rightshift */
1177 2, /* size (0 = byte, 1 = short, 2 = long) */
1178 32, /* bitsize */
1179 TRUE, /* pc_relative */
1180 0, /* bitpos */
1181 complain_overflow_dont,/* complain_on_overflow */
1182 bfd_elf_generic_reloc, /* special_function */
1183 "R_ARM_LDR_SB_G2", /* name */
1184 FALSE, /* partial_inplace */
1185 0xffffffff, /* src_mask */
1186 0xffffffff, /* dst_mask */
1187 TRUE), /* pcrel_offset */
1188
1189 HOWTO (R_ARM_LDRS_SB_G0, /* type */
1190 0, /* rightshift */
1191 2, /* size (0 = byte, 1 = short, 2 = long) */
1192 32, /* bitsize */
1193 TRUE, /* pc_relative */
1194 0, /* bitpos */
1195 complain_overflow_dont,/* complain_on_overflow */
1196 bfd_elf_generic_reloc, /* special_function */
1197 "R_ARM_LDRS_SB_G0", /* name */
1198 FALSE, /* partial_inplace */
1199 0xffffffff, /* src_mask */
1200 0xffffffff, /* dst_mask */
1201 TRUE), /* pcrel_offset */
1202
1203 HOWTO (R_ARM_LDRS_SB_G1, /* type */
1204 0, /* rightshift */
1205 2, /* size (0 = byte, 1 = short, 2 = long) */
1206 32, /* bitsize */
1207 TRUE, /* pc_relative */
1208 0, /* bitpos */
1209 complain_overflow_dont,/* complain_on_overflow */
1210 bfd_elf_generic_reloc, /* special_function */
1211 "R_ARM_LDRS_SB_G1", /* name */
1212 FALSE, /* partial_inplace */
1213 0xffffffff, /* src_mask */
1214 0xffffffff, /* dst_mask */
1215 TRUE), /* pcrel_offset */
1216
1217 HOWTO (R_ARM_LDRS_SB_G2, /* type */
1218 0, /* rightshift */
1219 2, /* size (0 = byte, 1 = short, 2 = long) */
1220 32, /* bitsize */
1221 TRUE, /* pc_relative */
1222 0, /* bitpos */
1223 complain_overflow_dont,/* complain_on_overflow */
1224 bfd_elf_generic_reloc, /* special_function */
1225 "R_ARM_LDRS_SB_G2", /* name */
1226 FALSE, /* partial_inplace */
1227 0xffffffff, /* src_mask */
1228 0xffffffff, /* dst_mask */
1229 TRUE), /* pcrel_offset */
1230
1231 HOWTO (R_ARM_LDC_SB_G0, /* type */
1232 0, /* rightshift */
1233 2, /* size (0 = byte, 1 = short, 2 = long) */
1234 32, /* bitsize */
1235 TRUE, /* pc_relative */
1236 0, /* bitpos */
1237 complain_overflow_dont,/* complain_on_overflow */
1238 bfd_elf_generic_reloc, /* special_function */
1239 "R_ARM_LDC_SB_G0", /* name */
1240 FALSE, /* partial_inplace */
1241 0xffffffff, /* src_mask */
1242 0xffffffff, /* dst_mask */
1243 TRUE), /* pcrel_offset */
1244
1245 HOWTO (R_ARM_LDC_SB_G1, /* type */
1246 0, /* rightshift */
1247 2, /* size (0 = byte, 1 = short, 2 = long) */
1248 32, /* bitsize */
1249 TRUE, /* pc_relative */
1250 0, /* bitpos */
1251 complain_overflow_dont,/* complain_on_overflow */
1252 bfd_elf_generic_reloc, /* special_function */
1253 "R_ARM_LDC_SB_G1", /* name */
1254 FALSE, /* partial_inplace */
1255 0xffffffff, /* src_mask */
1256 0xffffffff, /* dst_mask */
1257 TRUE), /* pcrel_offset */
1258
1259 HOWTO (R_ARM_LDC_SB_G2, /* type */
1260 0, /* rightshift */
1261 2, /* size (0 = byte, 1 = short, 2 = long) */
1262 32, /* bitsize */
1263 TRUE, /* pc_relative */
1264 0, /* bitpos */
1265 complain_overflow_dont,/* complain_on_overflow */
1266 bfd_elf_generic_reloc, /* special_function */
1267 "R_ARM_LDC_SB_G2", /* name */
1268 FALSE, /* partial_inplace */
1269 0xffffffff, /* src_mask */
1270 0xffffffff, /* dst_mask */
1271 TRUE), /* pcrel_offset */
1272
1273 /* End of group relocations. */
c19d1205 1274
c19d1205
ZW		 1275 HOWTO (R_ARM_MOVW_BREL_NC, /* type */
1276 0, /* rightshift */
1277 2, /* size (0 = byte, 1 = short, 2 = long) */
1278 16, /* bitsize */
1279 FALSE, /* pc_relative */
1280 0, /* bitpos */
1281 complain_overflow_dont,/* complain_on_overflow */
1282 bfd_elf_generic_reloc, /* special_function */
1283 "R_ARM_MOVW_BREL_NC", /* name */
1284 FALSE, /* partial_inplace */
1285 0x0000ffff, /* src_mask */
1286 0x0000ffff, /* dst_mask */
1287 FALSE), /* pcrel_offset */
1288
1289 HOWTO (R_ARM_MOVT_BREL, /* type */
1290 0, /* rightshift */
1291 2, /* size (0 = byte, 1 = short, 2 = long) */
1292 16, /* bitsize */
1293 FALSE, /* pc_relative */
1294 0, /* bitpos */
1295 complain_overflow_bitfield,/* complain_on_overflow */
1296 bfd_elf_generic_reloc, /* special_function */
1297 "R_ARM_MOVT_BREL", /* name */
1298 FALSE, /* partial_inplace */
1299 0x0000ffff, /* src_mask */
1300 0x0000ffff, /* dst_mask */
1301 FALSE), /* pcrel_offset */
1302
1303 HOWTO (R_ARM_MOVW_BREL, /* type */
1304 0, /* rightshift */
1305 2, /* size (0 = byte, 1 = short, 2 = long) */
1306 16, /* bitsize */
1307 FALSE, /* pc_relative */
1308 0, /* bitpos */
1309 complain_overflow_dont,/* complain_on_overflow */
1310 bfd_elf_generic_reloc, /* special_function */
1311 "R_ARM_MOVW_BREL", /* name */
1312 FALSE, /* partial_inplace */
1313 0x0000ffff, /* src_mask */
1314 0x0000ffff, /* dst_mask */
1315 FALSE), /* pcrel_offset */
1316
1317 HOWTO (R_ARM_THM_MOVW_BREL_NC,/* type */
1318 0, /* rightshift */
1319 2, /* size (0 = byte, 1 = short, 2 = long) */
1320 16, /* bitsize */
1321 FALSE, /* pc_relative */
1322 0, /* bitpos */
1323 complain_overflow_dont,/* complain_on_overflow */
1324 bfd_elf_generic_reloc, /* special_function */
1325 "R_ARM_THM_MOVW_BREL_NC",/* name */
1326 FALSE, /* partial_inplace */
1327 0x040f70ff, /* src_mask */
1328 0x040f70ff, /* dst_mask */
1329 FALSE), /* pcrel_offset */
1330
1331 HOWTO (R_ARM_THM_MOVT_BREL, /* type */
1332 0, /* rightshift */
1333 2, /* size (0 = byte, 1 = short, 2 = long) */
1334 16, /* bitsize */
1335 FALSE, /* pc_relative */
1336 0, /* bitpos */
1337 complain_overflow_bitfield,/* complain_on_overflow */
1338 bfd_elf_generic_reloc, /* special_function */
1339 "R_ARM_THM_MOVT_BREL", /* name */
1340 FALSE, /* partial_inplace */
1341 0x040f70ff, /* src_mask */
1342 0x040f70ff, /* dst_mask */
1343 FALSE), /* pcrel_offset */
1344
1345 HOWTO (R_ARM_THM_MOVW_BREL, /* type */
1346 0, /* rightshift */
1347 2, /* size (0 = byte, 1 = short, 2 = long) */
1348 16, /* bitsize */
1349 FALSE, /* pc_relative */
1350 0, /* bitpos */
1351 complain_overflow_dont,/* complain_on_overflow */
1352 bfd_elf_generic_reloc, /* special_function */
1353 "R_ARM_THM_MOVW_BREL", /* name */
1354 FALSE, /* partial_inplace */
1355 0x040f70ff, /* src_mask */
1356 0x040f70ff, /* dst_mask */
1357 FALSE), /* pcrel_offset */
1358
0855e32b
NS		 1359 HOWTO (R_ARM_TLS_GOTDESC, /* type */
1360 0, /* rightshift */
1361 2, /* size (0 = byte, 1 = short, 2 = long) */
1362 32, /* bitsize */
1363 FALSE, /* pc_relative */
1364 0, /* bitpos */
1365 complain_overflow_bitfield,/* complain_on_overflow */
1366 NULL, /* special_function */
1367 "R_ARM_TLS_GOTDESC", /* name */
1368 TRUE, /* partial_inplace */
1369 0xffffffff, /* src_mask */
1370 0xffffffff, /* dst_mask */
1371 FALSE), /* pcrel_offset */
1372
1373 HOWTO (R_ARM_TLS_CALL, /* type */
1374 0, /* rightshift */
1375 2, /* size (0 = byte, 1 = short, 2 = long) */
1376 24, /* bitsize */
1377 FALSE, /* pc_relative */
1378 0, /* bitpos */
1379 complain_overflow_dont,/* complain_on_overflow */
1380 bfd_elf_generic_reloc, /* special_function */
1381 "R_ARM_TLS_CALL", /* name */
1382 FALSE, /* partial_inplace */
1383 0x00ffffff, /* src_mask */
1384 0x00ffffff, /* dst_mask */
1385 FALSE), /* pcrel_offset */
1386
1387 HOWTO (R_ARM_TLS_DESCSEQ, /* type */
1388 0, /* rightshift */
1389 2, /* size (0 = byte, 1 = short, 2 = long) */
1390 0, /* bitsize */
1391 FALSE, /* pc_relative */
1392 0, /* bitpos */
1393 complain_overflow_bitfield,/* complain_on_overflow */
1394 bfd_elf_generic_reloc, /* special_function */
1395 "R_ARM_TLS_DESCSEQ", /* name */
1396 FALSE, /* partial_inplace */
1397 0x00000000, /* src_mask */
1398 0x00000000, /* dst_mask */
1399 FALSE), /* pcrel_offset */
1400
1401 HOWTO (R_ARM_THM_TLS_CALL, /* type */
1402 0, /* rightshift */
1403 2, /* size (0 = byte, 1 = short, 2 = long) */
1404 24, /* bitsize */
1405 FALSE, /* pc_relative */
1406 0, /* bitpos */
1407 complain_overflow_dont,/* complain_on_overflow */
1408 bfd_elf_generic_reloc, /* special_function */
1409 "R_ARM_THM_TLS_CALL", /* name */
1410 FALSE, /* partial_inplace */
1411 0x07ff07ff, /* src_mask */
1412 0x07ff07ff, /* dst_mask */
1413 FALSE), /* pcrel_offset */
c19d1205
ZW		 1414
1415 HOWTO (R_ARM_PLT32_ABS, /* type */
1416 0, /* rightshift */
1417 2, /* size (0 = byte, 1 = short, 2 = long) */
1418 32, /* bitsize */
1419 FALSE, /* pc_relative */
1420 0, /* bitpos */
1421 complain_overflow_dont,/* complain_on_overflow */
1422 bfd_elf_generic_reloc, /* special_function */
1423 "R_ARM_PLT32_ABS", /* name */
1424 FALSE, /* partial_inplace */
1425 0xffffffff, /* src_mask */
1426 0xffffffff, /* dst_mask */
1427 FALSE), /* pcrel_offset */
1428
1429 HOWTO (R_ARM_GOT_ABS, /* type */
1430 0, /* rightshift */
1431 2, /* size (0 = byte, 1 = short, 2 = long) */
1432 32, /* bitsize */
1433 FALSE, /* pc_relative */
1434 0, /* bitpos */
1435 complain_overflow_dont,/* complain_on_overflow */
1436 bfd_elf_generic_reloc, /* special_function */
1437 "R_ARM_GOT_ABS", /* name */
1438 FALSE, /* partial_inplace */
1439 0xffffffff, /* src_mask */
1440 0xffffffff, /* dst_mask */
1441 FALSE), /* pcrel_offset */
1442
1443 HOWTO (R_ARM_GOT_PREL, /* type */
1444 0, /* rightshift */
1445 2, /* size (0 = byte, 1 = short, 2 = long) */
1446 32, /* bitsize */
1447 TRUE, /* pc_relative */
1448 0, /* bitpos */
1449 complain_overflow_dont, /* complain_on_overflow */
1450 bfd_elf_generic_reloc, /* special_function */
1451 "R_ARM_GOT_PREL", /* name */
1452 FALSE, /* partial_inplace */
1453 0xffffffff, /* src_mask */
1454 0xffffffff, /* dst_mask */
1455 TRUE), /* pcrel_offset */
1456
1457 HOWTO (R_ARM_GOT_BREL12, /* type */
1458 0, /* rightshift */
1459 2, /* size (0 = byte, 1 = short, 2 = long) */
1460 12, /* bitsize */
1461 FALSE, /* pc_relative */
1462 0, /* bitpos */
1463 complain_overflow_bitfield,/* complain_on_overflow */
1464 bfd_elf_generic_reloc, /* special_function */
1465 "R_ARM_GOT_BREL12", /* name */
1466 FALSE, /* partial_inplace */
1467 0x00000fff, /* src_mask */
1468 0x00000fff, /* dst_mask */
1469 FALSE), /* pcrel_offset */
1470
1471 HOWTO (R_ARM_GOTOFF12, /* type */
1472 0, /* rightshift */
1473 2, /* size (0 = byte, 1 = short, 2 = long) */
1474 12, /* bitsize */
1475 FALSE, /* pc_relative */
1476 0, /* bitpos */
1477 complain_overflow_bitfield,/* complain_on_overflow */
1478 bfd_elf_generic_reloc, /* special_function */
1479 "R_ARM_GOTOFF12", /* name */
1480 FALSE, /* partial_inplace */
1481 0x00000fff, /* src_mask */
1482 0x00000fff, /* dst_mask */
1483 FALSE), /* pcrel_offset */
1484
1485 EMPTY_HOWTO (R_ARM_GOTRELAX), /* reserved for future GOT-load optimizations */
1486
1487 /* GNU extension to record C++ vtable member usage */
1488 HOWTO (R_ARM_GNU_VTENTRY, /* type */
99059e56
RM		 1489 0, /* rightshift */
1490 2, /* size (0 = byte, 1 = short, 2 = long) */
1491 0, /* bitsize */
1492 FALSE, /* pc_relative */
1493 0, /* bitpos */
1494 complain_overflow_dont, /* complain_on_overflow */
1495 _bfd_elf_rel_vtable_reloc_fn, /* special_function */
1496 "R_ARM_GNU_VTENTRY", /* name */
1497 FALSE, /* partial_inplace */
1498 0, /* src_mask */
1499 0, /* dst_mask */
1500 FALSE), /* pcrel_offset */
c19d1205
ZW		 1501
1502 /* GNU extension to record C++ vtable hierarchy */
1503 HOWTO (R_ARM_GNU_VTINHERIT, /* type */
99059e56
RM		 1504 0, /* rightshift */
1505 2, /* size (0 = byte, 1 = short, 2 = long) */
1506 0, /* bitsize */
1507 FALSE, /* pc_relative */
1508 0, /* bitpos */
1509 complain_overflow_dont, /* complain_on_overflow */
1510 NULL, /* special_function */
1511 "R_ARM_GNU_VTINHERIT", /* name */
1512 FALSE, /* partial_inplace */
1513 0, /* src_mask */
1514 0, /* dst_mask */
1515 FALSE), /* pcrel_offset */
c19d1205
ZW		 1516
1517 HOWTO (R_ARM_THM_JUMP11, /* type */
1518 1, /* rightshift */
1519 1, /* size (0 = byte, 1 = short, 2 = long) */
1520 11, /* bitsize */
1521 TRUE, /* pc_relative */
1522 0, /* bitpos */
1523 complain_overflow_signed, /* complain_on_overflow */
1524 bfd_elf_generic_reloc, /* special_function */
1525 "R_ARM_THM_JUMP11", /* name */
1526 FALSE, /* partial_inplace */
1527 0x000007ff, /* src_mask */
1528 0x000007ff, /* dst_mask */
1529 TRUE), /* pcrel_offset */
1530
1531 HOWTO (R_ARM_THM_JUMP8, /* type */
1532 1, /* rightshift */
1533 1, /* size (0 = byte, 1 = short, 2 = long) */
1534 8, /* bitsize */
1535 TRUE, /* pc_relative */
1536 0, /* bitpos */
1537 complain_overflow_signed, /* complain_on_overflow */
1538 bfd_elf_generic_reloc, /* special_function */
1539 "R_ARM_THM_JUMP8", /* name */
1540 FALSE, /* partial_inplace */
1541 0x000000ff, /* src_mask */
1542 0x000000ff, /* dst_mask */
1543 TRUE), /* pcrel_offset */
ba93b8ac 1544
c19d1205
ZW		 1545 /* TLS relocations */
1546 HOWTO (R_ARM_TLS_GD32, /* type */
99059e56
RM		 1547 0, /* rightshift */
1548 2, /* size (0 = byte, 1 = short, 2 = long) */
1549 32, /* bitsize */
1550 FALSE, /* pc_relative */
1551 0, /* bitpos */
1552 complain_overflow_bitfield,/* complain_on_overflow */
1553 NULL, /* special_function */
1554 "R_ARM_TLS_GD32", /* name */
1555 TRUE, /* partial_inplace */
1556 0xffffffff, /* src_mask */
1557 0xffffffff, /* dst_mask */
1558 FALSE), /* pcrel_offset */
ba93b8ac 1559
ba93b8ac 1560 HOWTO (R_ARM_TLS_LDM32, /* type */
99059e56
RM		 1561 0, /* rightshift */
1562 2, /* size (0 = byte, 1 = short, 2 = long) */
1563 32, /* bitsize */
1564 FALSE, /* pc_relative */
1565 0, /* bitpos */
1566 complain_overflow_bitfield,/* complain_on_overflow */
1567 bfd_elf_generic_reloc, /* special_function */
1568 "R_ARM_TLS_LDM32", /* name */
1569 TRUE, /* partial_inplace */
1570 0xffffffff, /* src_mask */
1571 0xffffffff, /* dst_mask */
1572 FALSE), /* pcrel_offset */
ba93b8ac 1573
c19d1205 1574 HOWTO (R_ARM_TLS_LDO32, /* type */
99059e56
RM		 1575 0, /* rightshift */
1576 2, /* size (0 = byte, 1 = short, 2 = long) */
1577 32, /* bitsize */
1578 FALSE, /* pc_relative */
1579 0, /* bitpos */
1580 complain_overflow_bitfield,/* complain_on_overflow */
1581 bfd_elf_generic_reloc, /* special_function */
1582 "R_ARM_TLS_LDO32", /* name */
1583 TRUE, /* partial_inplace */
1584 0xffffffff, /* src_mask */
1585 0xffffffff, /* dst_mask */
1586 FALSE), /* pcrel_offset */
ba93b8ac 1587
ba93b8ac 1588 HOWTO (R_ARM_TLS_IE32, /* type */
99059e56
RM		 1589 0, /* rightshift */
1590 2, /* size (0 = byte, 1 = short, 2 = long) */
1591 32, /* bitsize */
1592 FALSE, /* pc_relative */
1593 0, /* bitpos */
1594 complain_overflow_bitfield,/* complain_on_overflow */
1595 NULL, /* special_function */
1596 "R_ARM_TLS_IE32", /* name */
1597 TRUE, /* partial_inplace */
1598 0xffffffff, /* src_mask */
1599 0xffffffff, /* dst_mask */
1600 FALSE), /* pcrel_offset */
7f266840 1601
c19d1205 1602 HOWTO (R_ARM_TLS_LE32, /* type */
99059e56
RM		 1603 0, /* rightshift */
1604 2, /* size (0 = byte, 1 = short, 2 = long) */
1605 32, /* bitsize */
1606 FALSE, /* pc_relative */
1607 0, /* bitpos */
1608 complain_overflow_bitfield,/* complain_on_overflow */
75c11999 1609 NULL, /* special_function */
99059e56
RM		 1610 "R_ARM_TLS_LE32", /* name */
1611 TRUE, /* partial_inplace */
1612 0xffffffff, /* src_mask */
1613 0xffffffff, /* dst_mask */
1614 FALSE), /* pcrel_offset */
7f266840 1615
c19d1205
ZW		 1616 HOWTO (R_ARM_TLS_LDO12, /* type */
1617 0, /* rightshift */
1618 2, /* size (0 = byte, 1 = short, 2 = long) */
1619 12, /* bitsize */
1620 FALSE, /* pc_relative */
7f266840 1621 0, /* bitpos */
c19d1205 1622 complain_overflow_bitfield,/* complain_on_overflow */
7f266840 1623 bfd_elf_generic_reloc, /* special_function */
c19d1205 1624 "R_ARM_TLS_LDO12", /* name */
7f266840 1625 FALSE, /* partial_inplace */
c19d1205
ZW		 1626 0x00000fff, /* src_mask */
1627 0x00000fff, /* dst_mask */
1628 FALSE), /* pcrel_offset */
7f266840 1629
c19d1205
ZW		 1630 HOWTO (R_ARM_TLS_LE12, /* type */
1631 0, /* rightshift */
1632 2, /* size (0 = byte, 1 = short, 2 = long) */
1633 12, /* bitsize */
1634 FALSE, /* pc_relative */
7f266840 1635 0, /* bitpos */
c19d1205 1636 complain_overflow_bitfield,/* complain_on_overflow */
7f266840 1637 bfd_elf_generic_reloc, /* special_function */
c19d1205 1638 "R_ARM_TLS_LE12", /* name */
7f266840 1639 FALSE, /* partial_inplace */
c19d1205
ZW		 1640 0x00000fff, /* src_mask */
1641 0x00000fff, /* dst_mask */
1642 FALSE), /* pcrel_offset */
7f266840 1643
c19d1205 1644 HOWTO (R_ARM_TLS_IE12GP, /* type */
7f266840
DJ		 1645 0, /* rightshift */
1646 2, /* size (0 = byte, 1 = short, 2 = long) */
c19d1205
ZW		 1647 12, /* bitsize */
1648 FALSE, /* pc_relative */
7f266840 1649 0, /* bitpos */
c19d1205 1650 complain_overflow_bitfield,/* complain_on_overflow */
7f266840 1651 bfd_elf_generic_reloc, /* special_function */
c19d1205 1652 "R_ARM_TLS_IE12GP", /* name */
7f266840 1653 FALSE, /* partial_inplace */
c19d1205
ZW		 1654 0x00000fff, /* src_mask */
1655 0x00000fff, /* dst_mask */
1656 FALSE), /* pcrel_offset */
0855e32b 1657
34e77a92 1658 /* 112-127 private relocations. */
0855e32b
NS		 1659 EMPTY_HOWTO (112),
1660 EMPTY_HOWTO (113),
1661 EMPTY_HOWTO (114),
1662 EMPTY_HOWTO (115),
1663 EMPTY_HOWTO (116),
1664 EMPTY_HOWTO (117),
1665 EMPTY_HOWTO (118),
1666 EMPTY_HOWTO (119),
1667 EMPTY_HOWTO (120),
1668 EMPTY_HOWTO (121),
1669 EMPTY_HOWTO (122),
1670 EMPTY_HOWTO (123),
1671 EMPTY_HOWTO (124),
1672 EMPTY_HOWTO (125),
1673 EMPTY_HOWTO (126),
1674 EMPTY_HOWTO (127),
34e77a92
RS		 1675
1676 /* R_ARM_ME_TOO, obsolete. */
0855e32b
NS		 1677 EMPTY_HOWTO (128),
1678
1679 HOWTO (R_ARM_THM_TLS_DESCSEQ, /* type */
1680 0, /* rightshift */
1681 1, /* size (0 = byte, 1 = short, 2 = long) */
1682 0, /* bitsize */
1683 FALSE, /* pc_relative */
1684 0, /* bitpos */
1685 complain_overflow_bitfield,/* complain_on_overflow */
1686 bfd_elf_generic_reloc, /* special_function */
1687 "R_ARM_THM_TLS_DESCSEQ",/* name */
1688 FALSE, /* partial_inplace */
1689 0x00000000, /* src_mask */
1690 0x00000000, /* dst_mask */
1691 FALSE), /* pcrel_offset */
72d98d16
MG		 1692 EMPTY_HOWTO (130),
1693 EMPTY_HOWTO (131),
1694 HOWTO (R_ARM_THM_ALU_ABS_G0_NC,/* type. */
1695 0, /* rightshift. */
1696 1, /* size (0 = byte, 1 = short, 2 = long). */
1697 16, /* bitsize. */
1698 FALSE, /* pc_relative. */
1699 0, /* bitpos. */
1700 complain_overflow_bitfield,/* complain_on_overflow. */
1701 bfd_elf_generic_reloc, /* special_function. */
1702 "R_ARM_THM_ALU_ABS_G0_NC",/* name. */
1703 FALSE, /* partial_inplace. */
1704 0x00000000, /* src_mask. */
1705 0x00000000, /* dst_mask. */
1706 FALSE), /* pcrel_offset. */
1707 HOWTO (R_ARM_THM_ALU_ABS_G1_NC,/* type. */
1708 0, /* rightshift. */
1709 1, /* size (0 = byte, 1 = short, 2 = long). */
1710 16, /* bitsize. */
1711 FALSE, /* pc_relative. */
1712 0, /* bitpos. */
1713 complain_overflow_bitfield,/* complain_on_overflow. */
1714 bfd_elf_generic_reloc, /* special_function. */
1715 "R_ARM_THM_ALU_ABS_G1_NC",/* name. */
1716 FALSE, /* partial_inplace. */
1717 0x00000000, /* src_mask. */
1718 0x00000000, /* dst_mask. */
1719 FALSE), /* pcrel_offset. */
1720 HOWTO (R_ARM_THM_ALU_ABS_G2_NC,/* type. */
1721 0, /* rightshift. */
1722 1, /* size (0 = byte, 1 = short, 2 = long). */
1723 16, /* bitsize. */
1724 FALSE, /* pc_relative. */
1725 0, /* bitpos. */
1726 complain_overflow_bitfield,/* complain_on_overflow. */
1727 bfd_elf_generic_reloc, /* special_function. */
1728 "R_ARM_THM_ALU_ABS_G2_NC",/* name. */
1729 FALSE, /* partial_inplace. */
1730 0x00000000, /* src_mask. */
1731 0x00000000, /* dst_mask. */
1732 FALSE), /* pcrel_offset. */
1733 HOWTO (R_ARM_THM_ALU_ABS_G3_NC,/* type. */
1734 0, /* rightshift. */
1735 1, /* size (0 = byte, 1 = short, 2 = long). */
1736 16, /* bitsize. */
1737 FALSE, /* pc_relative. */
1738 0, /* bitpos. */
1739 complain_overflow_bitfield,/* complain_on_overflow. */
1740 bfd_elf_generic_reloc, /* special_function. */
1741 "R_ARM_THM_ALU_ABS_G3_NC",/* name. */
1742 FALSE, /* partial_inplace. */
1743 0x00000000, /* src_mask. */
1744 0x00000000, /* dst_mask. */
1745 FALSE), /* pcrel_offset. */
c19d1205
ZW		 1746};
1747
34e77a92
RS		 1748/* 160 onwards: */
1749static reloc_howto_type elf32_arm_howto_table_2[1] =
1750{
1751 HOWTO (R_ARM_IRELATIVE, /* type */
99059e56
RM		 1752 0, /* rightshift */
1753 2, /* size (0 = byte, 1 = short, 2 = long) */
1754 32, /* bitsize */
1755 FALSE, /* pc_relative */
1756 0, /* bitpos */
1757 complain_overflow_bitfield,/* complain_on_overflow */
1758 bfd_elf_generic_reloc, /* special_function */
1759 "R_ARM_IRELATIVE", /* name */
1760 TRUE, /* partial_inplace */
1761 0xffffffff, /* src_mask */
1762 0xffffffff, /* dst_mask */
1763 FALSE) /* pcrel_offset */
34e77a92 1764};
c19d1205 1765
34e77a92
RS		 1766/* 249-255 extended, currently unused, relocations: */
1767static reloc_howto_type elf32_arm_howto_table_3[4] =
7f266840
DJ		 1768{
1769 HOWTO (R_ARM_RREL32, /* type */
1770 0, /* rightshift */
1771 0, /* size (0 = byte, 1 = short, 2 = long) */
1772 0, /* bitsize */
1773 FALSE, /* pc_relative */
1774 0, /* bitpos */
1775 complain_overflow_dont,/* complain_on_overflow */
1776 bfd_elf_generic_reloc, /* special_function */
1777 "R_ARM_RREL32", /* name */
1778 FALSE, /* partial_inplace */
1779 0, /* src_mask */
1780 0, /* dst_mask */
1781 FALSE), /* pcrel_offset */
1782
1783 HOWTO (R_ARM_RABS32, /* type */
1784 0, /* rightshift */
1785 0, /* size (0 = byte, 1 = short, 2 = long) */
1786 0, /* bitsize */
1787 FALSE, /* pc_relative */
1788 0, /* bitpos */
1789 complain_overflow_dont,/* complain_on_overflow */
1790 bfd_elf_generic_reloc, /* special_function */
1791 "R_ARM_RABS32", /* name */
1792 FALSE, /* partial_inplace */
1793 0, /* src_mask */
1794 0, /* dst_mask */
1795 FALSE), /* pcrel_offset */
1796
1797 HOWTO (R_ARM_RPC24, /* type */
1798 0, /* rightshift */
1799 0, /* size (0 = byte, 1 = short, 2 = long) */
1800 0, /* bitsize */
1801 FALSE, /* pc_relative */
1802 0, /* bitpos */
1803 complain_overflow_dont,/* complain_on_overflow */
1804 bfd_elf_generic_reloc, /* special_function */
1805 "R_ARM_RPC24", /* name */
1806 FALSE, /* partial_inplace */
1807 0, /* src_mask */
1808 0, /* dst_mask */
1809 FALSE), /* pcrel_offset */
1810
1811 HOWTO (R_ARM_RBASE, /* type */
1812 0, /* rightshift */
1813 0, /* size (0 = byte, 1 = short, 2 = long) */
1814 0, /* bitsize */
1815 FALSE, /* pc_relative */
1816 0, /* bitpos */
1817 complain_overflow_dont,/* complain_on_overflow */
1818 bfd_elf_generic_reloc, /* special_function */
1819 "R_ARM_RBASE", /* name */
1820 FALSE, /* partial_inplace */
1821 0, /* src_mask */
1822 0, /* dst_mask */
1823 FALSE) /* pcrel_offset */
1824};
1825
1826static reloc_howto_type *
1827elf32_arm_howto_from_type (unsigned int r_type)
1828{
906e58ca 1829 if (r_type < ARRAY_SIZE (elf32_arm_howto_table_1))
c19d1205 1830 return &elf32_arm_howto_table_1[r_type];
ba93b8ac 1831
34e77a92
RS		 1832 if (r_type == R_ARM_IRELATIVE)
1833 return &elf32_arm_howto_table_2[r_type - R_ARM_IRELATIVE];
1834
c19d1205 1835 if (r_type >= R_ARM_RREL32
34e77a92
RS		 1836 && r_type < R_ARM_RREL32 + ARRAY_SIZE (elf32_arm_howto_table_3))
1837 return &elf32_arm_howto_table_3[r_type - R_ARM_RREL32];
7f266840 1838
c19d1205 1839 return NULL;
7f266840
DJ		 1840}
1841
1842static void
1843elf32_arm_info_to_howto (bfd * abfd ATTRIBUTE_UNUSED, arelent * bfd_reloc,
1844 Elf_Internal_Rela * elf_reloc)
1845{
1846 unsigned int r_type;
1847
1848 r_type = ELF32_R_TYPE (elf_reloc->r_info);
1849 bfd_reloc->howto = elf32_arm_howto_from_type (r_type);
1850}
1851
1852struct elf32_arm_reloc_map
1853 {
1854 bfd_reloc_code_real_type bfd_reloc_val;
1855 unsigned char elf_reloc_val;
1856 };
1857
1858/* All entries in this list must also be present in elf32_arm_howto_table. */
1859static const struct elf32_arm_reloc_map elf32_arm_reloc_map[] =
1860 {
1861 {BFD_RELOC_NONE, R_ARM_NONE},
1862 {BFD_RELOC_ARM_PCREL_BRANCH, R_ARM_PC24},
39b41c9c
PB		 1863 {BFD_RELOC_ARM_PCREL_CALL, R_ARM_CALL},
1864 {BFD_RELOC_ARM_PCREL_JUMP, R_ARM_JUMP24},
7f266840
DJ		 1865 {BFD_RELOC_ARM_PCREL_BLX, R_ARM_XPC25},
1866 {BFD_RELOC_THUMB_PCREL_BLX, R_ARM_THM_XPC22},
1867 {BFD_RELOC_32, R_ARM_ABS32},
1868 {BFD_RELOC_32_PCREL, R_ARM_REL32},
1869 {BFD_RELOC_8, R_ARM_ABS8},
1870 {BFD_RELOC_16, R_ARM_ABS16},
1871 {BFD_RELOC_ARM_OFFSET_IMM, R_ARM_ABS12},
1872 {BFD_RELOC_ARM_THUMB_OFFSET, R_ARM_THM_ABS5},
c19d1205
ZW		 1873 {BFD_RELOC_THUMB_PCREL_BRANCH25, R_ARM_THM_JUMP24},
1874 {BFD_RELOC_THUMB_PCREL_BRANCH23, R_ARM_THM_CALL},
1875 {BFD_RELOC_THUMB_PCREL_BRANCH12, R_ARM_THM_JUMP11},
1876 {BFD_RELOC_THUMB_PCREL_BRANCH20, R_ARM_THM_JUMP19},
1877 {BFD_RELOC_THUMB_PCREL_BRANCH9, R_ARM_THM_JUMP8},
1878 {BFD_RELOC_THUMB_PCREL_BRANCH7, R_ARM_THM_JUMP6},
7f266840
DJ		 1879 {BFD_RELOC_ARM_GLOB_DAT, R_ARM_GLOB_DAT},
1880 {BFD_RELOC_ARM_JUMP_SLOT, R_ARM_JUMP_SLOT},
1881 {BFD_RELOC_ARM_RELATIVE, R_ARM_RELATIVE},
c19d1205 1882 {BFD_RELOC_ARM_GOTOFF, R_ARM_GOTOFF32},
7f266840 1883 {BFD_RELOC_ARM_GOTPC, R_ARM_GOTPC},
b43420e6 1884 {BFD_RELOC_ARM_GOT_PREL, R_ARM_GOT_PREL},
7f266840
DJ		 1885 {BFD_RELOC_ARM_GOT32, R_ARM_GOT32},
1886 {BFD_RELOC_ARM_PLT32, R_ARM_PLT32},
1887 {BFD_RELOC_ARM_TARGET1, R_ARM_TARGET1},
1888 {BFD_RELOC_ARM_ROSEGREL32, R_ARM_ROSEGREL32},
1889 {BFD_RELOC_ARM_SBREL32, R_ARM_SBREL32},
1890 {BFD_RELOC_ARM_PREL31, R_ARM_PREL31},
ba93b8ac
DJ		 1891 {BFD_RELOC_ARM_TARGET2, R_ARM_TARGET2},
1892 {BFD_RELOC_ARM_PLT32, R_ARM_PLT32},
0855e32b
NS		 1893 {BFD_RELOC_ARM_TLS_GOTDESC, R_ARM_TLS_GOTDESC},
1894 {BFD_RELOC_ARM_TLS_CALL, R_ARM_TLS_CALL},
1895 {BFD_RELOC_ARM_THM_TLS_CALL, R_ARM_THM_TLS_CALL},
1896 {BFD_RELOC_ARM_TLS_DESCSEQ, R_ARM_TLS_DESCSEQ},
1897 {BFD_RELOC_ARM_THM_TLS_DESCSEQ, R_ARM_THM_TLS_DESCSEQ},
1898 {BFD_RELOC_ARM_TLS_DESC, R_ARM_TLS_DESC},
ba93b8ac
DJ		 1899 {BFD_RELOC_ARM_TLS_GD32, R_ARM_TLS_GD32},
1900 {BFD_RELOC_ARM_TLS_LDO32, R_ARM_TLS_LDO32},
1901 {BFD_RELOC_ARM_TLS_LDM32, R_ARM_TLS_LDM32},
1902 {BFD_RELOC_ARM_TLS_DTPMOD32, R_ARM_TLS_DTPMOD32},
1903 {BFD_RELOC_ARM_TLS_DTPOFF32, R_ARM_TLS_DTPOFF32},
1904 {BFD_RELOC_ARM_TLS_TPOFF32, R_ARM_TLS_TPOFF32},
1905 {BFD_RELOC_ARM_TLS_IE32, R_ARM_TLS_IE32},
1906 {BFD_RELOC_ARM_TLS_LE32, R_ARM_TLS_LE32},
34e77a92 1907 {BFD_RELOC_ARM_IRELATIVE, R_ARM_IRELATIVE},
c19d1205
ZW		 1908 {BFD_RELOC_VTABLE_INHERIT, R_ARM_GNU_VTINHERIT},
1909 {BFD_RELOC_VTABLE_ENTRY, R_ARM_GNU_VTENTRY},
b6895b4f
PB		 1910 {BFD_RELOC_ARM_MOVW, R_ARM_MOVW_ABS_NC},
1911 {BFD_RELOC_ARM_MOVT, R_ARM_MOVT_ABS},
1912 {BFD_RELOC_ARM_MOVW_PCREL, R_ARM_MOVW_PREL_NC},
1913 {BFD_RELOC_ARM_MOVT_PCREL, R_ARM_MOVT_PREL},
1914 {BFD_RELOC_ARM_THUMB_MOVW, R_ARM_THM_MOVW_ABS_NC},
1915 {BFD_RELOC_ARM_THUMB_MOVT, R_ARM_THM_MOVT_ABS},
1916 {BFD_RELOC_ARM_THUMB_MOVW_PCREL, R_ARM_THM_MOVW_PREL_NC},
1917 {BFD_RELOC_ARM_THUMB_MOVT_PCREL, R_ARM_THM_MOVT_PREL},
4962c51a
MS		 1918 {BFD_RELOC_ARM_ALU_PC_G0_NC, R_ARM_ALU_PC_G0_NC},
1919 {BFD_RELOC_ARM_ALU_PC_G0, R_ARM_ALU_PC_G0},
1920 {BFD_RELOC_ARM_ALU_PC_G1_NC, R_ARM_ALU_PC_G1_NC},
1921 {BFD_RELOC_ARM_ALU_PC_G1, R_ARM_ALU_PC_G1},
1922 {BFD_RELOC_ARM_ALU_PC_G2, R_ARM_ALU_PC_G2},
1923 {BFD_RELOC_ARM_LDR_PC_G0, R_ARM_LDR_PC_G0},
1924 {BFD_RELOC_ARM_LDR_PC_G1, R_ARM_LDR_PC_G1},
1925 {BFD_RELOC_ARM_LDR_PC_G2, R_ARM_LDR_PC_G2},
1926 {BFD_RELOC_ARM_LDRS_PC_G0, R_ARM_LDRS_PC_G0},
1927 {BFD_RELOC_ARM_LDRS_PC_G1, R_ARM_LDRS_PC_G1},
1928 {BFD_RELOC_ARM_LDRS_PC_G2, R_ARM_LDRS_PC_G2},
1929 {BFD_RELOC_ARM_LDC_PC_G0, R_ARM_LDC_PC_G0},
1930 {BFD_RELOC_ARM_LDC_PC_G1, R_ARM_LDC_PC_G1},
1931 {BFD_RELOC_ARM_LDC_PC_G2, R_ARM_LDC_PC_G2},
1932 {BFD_RELOC_ARM_ALU_SB_G0_NC, R_ARM_ALU_SB_G0_NC},
1933 {BFD_RELOC_ARM_ALU_SB_G0, R_ARM_ALU_SB_G0},
1934 {BFD_RELOC_ARM_ALU_SB_G1_NC, R_ARM_ALU_SB_G1_NC},
1935 {BFD_RELOC_ARM_ALU_SB_G1, R_ARM_ALU_SB_G1},
1936 {BFD_RELOC_ARM_ALU_SB_G2, R_ARM_ALU_SB_G2},
1937 {BFD_RELOC_ARM_LDR_SB_G0, R_ARM_LDR_SB_G0},
1938 {BFD_RELOC_ARM_LDR_SB_G1, R_ARM_LDR_SB_G1},
1939 {BFD_RELOC_ARM_LDR_SB_G2, R_ARM_LDR_SB_G2},
1940 {BFD_RELOC_ARM_LDRS_SB_G0, R_ARM_LDRS_SB_G0},
1941 {BFD_RELOC_ARM_LDRS_SB_G1, R_ARM_LDRS_SB_G1},
1942 {BFD_RELOC_ARM_LDRS_SB_G2, R_ARM_LDRS_SB_G2},
1943 {BFD_RELOC_ARM_LDC_SB_G0, R_ARM_LDC_SB_G0},
1944 {BFD_RELOC_ARM_LDC_SB_G1, R_ARM_LDC_SB_G1},
845b51d6 1945 {BFD_RELOC_ARM_LDC_SB_G2, R_ARM_LDC_SB_G2},
72d98d16
MG		 1946 {BFD_RELOC_ARM_V4BX, R_ARM_V4BX},
1947 {BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC, R_ARM_THM_ALU_ABS_G3_NC},
1948 {BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC, R_ARM_THM_ALU_ABS_G2_NC},
1949 {BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC, R_ARM_THM_ALU_ABS_G1_NC},
1950 {BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC, R_ARM_THM_ALU_ABS_G0_NC}
7f266840
DJ		 1951 };
1952
1953static reloc_howto_type *
f1c71a59
ZW		 1954elf32_arm_reloc_type_lookup (bfd *abfd ATTRIBUTE_UNUSED,
1955 bfd_reloc_code_real_type code)
7f266840
DJ		 1956{
1957 unsigned int i;
8029a119 1958
906e58ca 1959 for (i = 0; i < ARRAY_SIZE (elf32_arm_reloc_map); i ++)
c19d1205
ZW		 1960 if (elf32_arm_reloc_map[i].bfd_reloc_val == code)
1961 return elf32_arm_howto_from_type (elf32_arm_reloc_map[i].elf_reloc_val);
7f266840 1962
c19d1205 1963 return NULL;
7f266840
DJ		 1964}
1965
157090f7
AM		 1966static reloc_howto_type *
1967elf32_arm_reloc_name_lookup (bfd *abfd ATTRIBUTE_UNUSED,
1968 const char *r_name)
1969{
1970 unsigned int i;
1971
906e58ca 1972 for (i = 0; i < ARRAY_SIZE (elf32_arm_howto_table_1); i++)
157090f7
AM		 1973 if (elf32_arm_howto_table_1[i].name != NULL
1974 && strcasecmp (elf32_arm_howto_table_1[i].name, r_name) == 0)
1975 return &elf32_arm_howto_table_1[i];
1976
906e58ca 1977 for (i = 0; i < ARRAY_SIZE (elf32_arm_howto_table_2); i++)
157090f7
AM		 1978 if (elf32_arm_howto_table_2[i].name != NULL
1979 && strcasecmp (elf32_arm_howto_table_2[i].name, r_name) == 0)
1980 return &elf32_arm_howto_table_2[i];
1981
34e77a92
RS		 1982 for (i = 0; i < ARRAY_SIZE (elf32_arm_howto_table_3); i++)
1983 if (elf32_arm_howto_table_3[i].name != NULL
1984 && strcasecmp (elf32_arm_howto_table_3[i].name, r_name) == 0)
1985 return &elf32_arm_howto_table_3[i];
1986
157090f7
AM		 1987 return NULL;
1988}
1989
906e58ca
NC		 1990/* Support for core dump NOTE sections. */
1991
7f266840 1992static bfd_boolean
f1c71a59 1993elf32_arm_nabi_grok_prstatus (bfd *abfd, Elf_Internal_Note *note)
7f266840
DJ		 1994{
1995 int offset;
1996 size_t size;
1997
1998 switch (note->descsz)
1999 {
2000 default:
2001 return FALSE;
2002
8029a119 2003 case 148: /* Linux/ARM 32-bit. */
7f266840 2004 /* pr_cursig */
228e534f 2005 elf_tdata (abfd)->core->signal = bfd_get_16 (abfd, note->descdata + 12);
7f266840
DJ		 2006
2007 /* pr_pid */
228e534f 2008 elf_tdata (abfd)->core->lwpid = bfd_get_32 (abfd, note->descdata + 24);
7f266840
DJ		 2009
2010 /* pr_reg */
2011 offset = 72;
2012 size = 72;
2013
2014 break;
2015 }
2016
2017 /* Make a ".reg/999" section. */
2018 return _bfd_elfcore_make_pseudosection (abfd, ".reg",
2019 size, note->descpos + offset);
2020}
2021
2022static bfd_boolean
f1c71a59 2023elf32_arm_nabi_grok_psinfo (bfd *abfd, Elf_Internal_Note *note)
7f266840
DJ		 2024{
2025 switch (note->descsz)
2026 {
2027 default:
2028 return FALSE;
2029
8029a119 2030 case 124: /* Linux/ARM elf_prpsinfo. */
228e534f 2031 elf_tdata (abfd)->core->pid
4395ee08 2032 = bfd_get_32 (abfd, note->descdata + 12);
228e534f 2033 elf_tdata (abfd)->core->program
7f266840 2034 = _bfd_elfcore_strndup (abfd, note->descdata + 28, 16);
228e534f 2035 elf_tdata (abfd)->core->command
7f266840
DJ		 2036 = _bfd_elfcore_strndup (abfd, note->descdata + 44, 80);
2037 }
2038
2039 /* Note that for some reason, a spurious space is tacked
2040 onto the end of the args in some (at least one anyway)
2041 implementations, so strip it off if it exists. */
7f266840 2042 {
228e534f 2043 char *command = elf_tdata (abfd)->core->command;
7f266840
DJ		 2044 int n = strlen (command);
2045
2046 if (0 < n && command[n - 1] == ' ')
2047 command[n - 1] = '\0';
2048 }
2049
2050 return TRUE;
2051}
2052
1f20dca5
UW		 2053static char *
2054elf32_arm_nabi_write_core_note (bfd *abfd, char *buf, int *bufsiz,
2055 int note_type, ...)
2056{
2057 switch (note_type)
2058 {
2059 default:
2060 return NULL;
2061
2062 case NT_PRPSINFO:
2063 {
2064 char data[124];
2065 va_list ap;
2066
2067 va_start (ap, note_type);
2068 memset (data, 0, sizeof (data));
2069 strncpy (data + 28, va_arg (ap, const char *), 16);
2070 strncpy (data + 44, va_arg (ap, const char *), 80);
2071 va_end (ap);
2072
2073 return elfcore_write_note (abfd, buf, bufsiz,
2074 "CORE", note_type, data, sizeof (data));
2075 }
2076
2077 case NT_PRSTATUS:
2078 {
2079 char data[148];
2080 va_list ap;
2081 long pid;
2082 int cursig;
2083 const void *greg;
2084
2085 va_start (ap, note_type);
2086 memset (data, 0, sizeof (data));
2087 pid = va_arg (ap, long);
2088 bfd_put_32 (abfd, pid, data + 24);
2089 cursig = va_arg (ap, int);
2090 bfd_put_16 (abfd, cursig, data + 12);
2091 greg = va_arg (ap, const void *);
2092 memcpy (data + 72, greg, 72);
2093 va_end (ap);
2094
2095 return elfcore_write_note (abfd, buf, bufsiz,
2096 "CORE", note_type, data, sizeof (data));
2097 }
2098 }
2099}
2100
6d00b590 2101#define TARGET_LITTLE_SYM arm_elf32_le_vec
7f266840 2102#define TARGET_LITTLE_NAME "elf32-littlearm"
6d00b590 2103#define TARGET_BIG_SYM arm_elf32_be_vec
7f266840
DJ		 2104#define TARGET_BIG_NAME "elf32-bigarm"
2105
2106#define elf_backend_grok_prstatus elf32_arm_nabi_grok_prstatus
2107#define elf_backend_grok_psinfo elf32_arm_nabi_grok_psinfo
1f20dca5 2108#define elf_backend_write_core_note elf32_arm_nabi_write_core_note
7f266840 2109
252b5132
RH		 2110typedef unsigned long int insn32;
2111typedef unsigned short int insn16;
2112
3a4a14e9
PB		 2113/* In lieu of proper flags, assume all EABIv4 or later objects are
2114 interworkable. */
57e8b36a 2115#define INTERWORK_FLAG(abfd) \
3a4a14e9 2116 (EF_ARM_EABI_VERSION (elf_elfheader (abfd)->e_flags) >= EF_ARM_EABI_VER4 \
3e6b1042
DJ		 2117 || (elf_elfheader (abfd)->e_flags & EF_ARM_INTERWORK) \
2118 || ((abfd)->flags & BFD_LINKER_CREATED))
9b485d32 2119
252b5132
RH		 2120/* The linker script knows the section names for placement.
2121 The entry_names are used to do simple name mangling on the stubs.
2122 Given a function name, and its type, the stub can be found. The
9b485d32 2123 name can be changed. The only requirement is the %s be present. */
252b5132
RH		 2124#define THUMB2ARM_GLUE_SECTION_NAME ".glue_7t"
2125#define THUMB2ARM_GLUE_ENTRY_NAME "__%s_from_thumb"
2126
2127#define ARM2THUMB_GLUE_SECTION_NAME ".glue_7"
2128#define ARM2THUMB_GLUE_ENTRY_NAME "__%s_from_arm"
2129
c7b8f16e
JB		 2130#define VFP11_ERRATUM_VENEER_SECTION_NAME ".vfp11_veneer"
2131#define VFP11_ERRATUM_VENEER_ENTRY_NAME "__vfp11_veneer_%x"
2132
a504d23a
LA		 2133#define STM32L4XX_ERRATUM_VENEER_SECTION_NAME ".text.stm32l4xx_veneer"
2134#define STM32L4XX_ERRATUM_VENEER_ENTRY_NAME "__stm32l4xx_veneer_%x"
2135
845b51d6
PB		 2136#define ARM_BX_GLUE_SECTION_NAME ".v4_bx"
2137#define ARM_BX_GLUE_ENTRY_NAME "__bx_r%d"
2138
7413f23f
DJ		 2139#define STUB_ENTRY_NAME "__%s_veneer"
2140
4ba2ef8f
TP		 2141#define CMSE_PREFIX "__acle_se_"
2142
252b5132
RH		 2143/* The name of the dynamic interpreter. This is put in the .interp
2144 section. */
2145#define ELF_DYNAMIC_INTERPRETER "/usr/lib/ld.so.1"
2146
0855e32b 2147static const unsigned long tls_trampoline [] =
b38cadfb
NC		 2148{
2149 0xe08e0000, /* add r0, lr, r0 */
2150 0xe5901004, /* ldr r1, [r0,#4] */
2151 0xe12fff11, /* bx r1 */
2152};
0855e32b
NS		 2153
2154static const unsigned long dl_tlsdesc_lazy_trampoline [] =
b38cadfb
NC		 2155{
2156 0xe52d2004, /* push {r2} */
2157 0xe59f200c, /* ldr r2, [pc, #3f - . - 8] */
2158 0xe59f100c, /* ldr r1, [pc, #4f - . - 8] */
2159 0xe79f2002, /* 1: ldr r2, [pc, r2] */
2160 0xe081100f, /* 2: add r1, pc */
2161 0xe12fff12, /* bx r2 */
2162 0x00000014, /* 3: .word _GLOBAL_OFFSET_TABLE_ - 1b - 8
99059e56 2163 + dl_tlsdesc_lazy_resolver(GOT) */
b38cadfb
NC		 2164 0x00000018, /* 4: .word _GLOBAL_OFFSET_TABLE_ - 2b - 8 */
2165};
0855e32b 2166
5e681ec4
PB		 2167#ifdef FOUR_WORD_PLT
2168
252b5132
RH		 2169/* The first entry in a procedure linkage table looks like
2170 this. It is set up so that any shared library function that is
59f2c4e7 2171 called before the relocation has been set up calls the dynamic
9b485d32 2172 linker first. */
e5a52504 2173static const bfd_vma elf32_arm_plt0_entry [] =
b38cadfb
NC		 2174{
2175 0xe52de004, /* str lr, [sp, #-4]! */
2176 0xe59fe010, /* ldr lr, [pc, #16] */
2177 0xe08fe00e, /* add lr, pc, lr */
2178 0xe5bef008, /* ldr pc, [lr, #8]! */
2179};
5e681ec4
PB		 2180
2181/* Subsequent entries in a procedure linkage table look like
2182 this. */
e5a52504 2183static const bfd_vma elf32_arm_plt_entry [] =
b38cadfb
NC		 2184{
2185 0xe28fc600, /* add ip, pc, #NN */
2186 0xe28cca00, /* add ip, ip, #NN */
2187 0xe5bcf000, /* ldr pc, [ip, #NN]! */
2188 0x00000000, /* unused */
2189};
5e681ec4 2190
eed94f8f 2191#else /* not FOUR_WORD_PLT */
5e681ec4 2192
5e681ec4
PB		 2193/* The first entry in a procedure linkage table looks like
2194 this. It is set up so that any shared library function that is
2195 called before the relocation has been set up calls the dynamic
2196 linker first. */
e5a52504 2197static const bfd_vma elf32_arm_plt0_entry [] =
b38cadfb
NC		 2198{
2199 0xe52de004, /* str lr, [sp, #-4]! */
2200 0xe59fe004, /* ldr lr, [pc, #4] */
2201 0xe08fe00e, /* add lr, pc, lr */
2202 0xe5bef008, /* ldr pc, [lr, #8]! */
2203 0x00000000, /* &GOT[0] - . */
2204};
252b5132 2205
1db37fe6
YG		 2206/* By default subsequent entries in a procedure linkage table look like
2207 this. Offsets that don't fit into 28 bits will cause link error. */
2208static const bfd_vma elf32_arm_plt_entry_short [] =
b38cadfb
NC		 2209{
2210 0xe28fc600, /* add ip, pc, #0xNN00000 */
2211 0xe28cca00, /* add ip, ip, #0xNN000 */
2212 0xe5bcf000, /* ldr pc, [ip, #0xNNN]! */
2213};
5e681ec4 2214
1db37fe6
YG		 2215/* When explicitly asked, we'll use this "long" entry format
2216 which can cope with arbitrary displacements. */
2217static const bfd_vma elf32_arm_plt_entry_long [] =
2218{
2219 0xe28fc200, /* add ip, pc, #0xN0000000 */
2220 0xe28cc600, /* add ip, ip, #0xNN00000 */
2221 0xe28cca00, /* add ip, ip, #0xNN000 */
2222 0xe5bcf000, /* ldr pc, [ip, #0xNNN]! */
2223};
2224
2225static bfd_boolean elf32_arm_use_long_plt_entry = FALSE;
2226
eed94f8f
NC		 2227#endif /* not FOUR_WORD_PLT */
2228
2229/* The first entry in a procedure linkage table looks like this.
2230 It is set up so that any shared library function that is called before the
2231 relocation has been set up calls the dynamic linker first. */
2232static const bfd_vma elf32_thumb2_plt0_entry [] =
2233{
2234 /* NOTE: As this is a mixture of 16-bit and 32-bit instructions,
2235 an instruction maybe encoded to one or two array elements. */
2236 0xf8dfb500, /* push {lr} */
2237 0x44fee008, /* ldr.w lr, [pc, #8] */
469a3493 2238 /* add lr, pc */
eed94f8f
NC		 2239 0xff08f85e, /* ldr.w pc, [lr, #8]! */
2240 0x00000000, /* &GOT[0] - . */
2241};
2242
2243/* Subsequent entries in a procedure linkage table for thumb only target
2244 look like this. */
2245static const bfd_vma elf32_thumb2_plt_entry [] =
2246{
2247 /* NOTE: As this is a mixture of 16-bit and 32-bit instructions,
2248 an instruction maybe encoded to one or two array elements. */
2249 0x0c00f240, /* movw ip, #0xNNNN */
2250 0x0c00f2c0, /* movt ip, #0xNNNN */
2251 0xf8dc44fc, /* add ip, pc */
2252 0xbf00f000 /* ldr.w pc, [ip] */
469a3493 2253 /* nop */
eed94f8f 2254};
252b5132 2255
00a97672
RS		 2256/* The format of the first entry in the procedure linkage table
2257 for a VxWorks executable. */
2258static const bfd_vma elf32_arm_vxworks_exec_plt0_entry[] =
b38cadfb
NC		 2259{
2260 0xe52dc008, /* str ip,[sp,#-8]! */
2261 0xe59fc000, /* ldr ip,[pc] */
2262 0xe59cf008, /* ldr pc,[ip,#8] */
2263 0x00000000, /* .long _GLOBAL_OFFSET_TABLE_ */
2264};
00a97672
RS		 2265
2266/* The format of subsequent entries in a VxWorks executable. */
2267static const bfd_vma elf32_arm_vxworks_exec_plt_entry[] =
b38cadfb
NC		 2268{
2269 0xe59fc000, /* ldr ip,[pc] */
2270 0xe59cf000, /* ldr pc,[ip] */
2271 0x00000000, /* .long @got */
2272 0xe59fc000, /* ldr ip,[pc] */
2273 0xea000000, /* b _PLT */
2274 0x00000000, /* .long @pltindex*sizeof(Elf32_Rela) */
2275};
00a97672
RS		 2276
2277/* The format of entries in a VxWorks shared library. */
2278static const bfd_vma elf32_arm_vxworks_shared_plt_entry[] =
b38cadfb
NC		 2279{
2280 0xe59fc000, /* ldr ip,[pc] */
2281 0xe79cf009, /* ldr pc,[ip,r9] */
2282 0x00000000, /* .long @got */
2283 0xe59fc000, /* ldr ip,[pc] */
2284 0xe599f008, /* ldr pc,[r9,#8] */
2285 0x00000000, /* .long @pltindex*sizeof(Elf32_Rela) */
2286};
00a97672 2287
b7693d02
DJ		 2288/* An initial stub used if the PLT entry is referenced from Thumb code. */
2289#define PLT_THUMB_STUB_SIZE 4
2290static const bfd_vma elf32_arm_plt_thumb_stub [] =
b38cadfb
NC		 2291{
2292 0x4778, /* bx pc */
2293 0x46c0 /* nop */
2294};
b7693d02 2295
e5a52504
MM		 2296/* The entries in a PLT when using a DLL-based target with multiple
2297 address spaces. */
906e58ca 2298static const bfd_vma elf32_arm_symbian_plt_entry [] =
b38cadfb
NC		 2299{
2300 0xe51ff004, /* ldr pc, [pc, #-4] */
2301 0x00000000, /* dcd R_ARM_GLOB_DAT(X) */
2302};
2303
2304/* The first entry in a procedure linkage table looks like
2305 this. It is set up so that any shared library function that is
2306 called before the relocation has been set up calls the dynamic
2307 linker first. */
2308static const bfd_vma elf32_arm_nacl_plt0_entry [] =
2309{
2310 /* First bundle: */
2311 0xe300c000, /* movw ip, #:lower16:&GOT[2]-.+8 */
2312 0xe340c000, /* movt ip, #:upper16:&GOT[2]-.+8 */
2313 0xe08cc00f, /* add ip, ip, pc */
2314 0xe52dc008, /* str ip, [sp, #-8]! */
2315 /* Second bundle: */
edccdf7c
RM		 2316 0xe3ccc103, /* bic ip, ip, #0xc0000000 */
2317 0xe59cc000, /* ldr ip, [ip] */
b38cadfb 2318 0xe3ccc13f, /* bic ip, ip, #0xc000000f */
edccdf7c 2319 0xe12fff1c, /* bx ip */
b38cadfb 2320 /* Third bundle: */
edccdf7c
RM		 2321 0xe320f000, /* nop */
2322 0xe320f000, /* nop */
2323 0xe320f000, /* nop */
b38cadfb
NC		 2324 /* .Lplt_tail: */
2325 0xe50dc004, /* str ip, [sp, #-4] */
2326 /* Fourth bundle: */
edccdf7c
RM		 2327 0xe3ccc103, /* bic ip, ip, #0xc0000000 */
2328 0xe59cc000, /* ldr ip, [ip] */
b38cadfb 2329 0xe3ccc13f, /* bic ip, ip, #0xc000000f */
edccdf7c 2330 0xe12fff1c, /* bx ip */
b38cadfb
NC		 2331};
2332#define ARM_NACL_PLT_TAIL_OFFSET (11 * 4)
2333
2334/* Subsequent entries in a procedure linkage table look like this. */
2335static const bfd_vma elf32_arm_nacl_plt_entry [] =
2336{
2337 0xe300c000, /* movw ip, #:lower16:&GOT[n]-.+8 */
2338 0xe340c000, /* movt ip, #:upper16:&GOT[n]-.+8 */
2339 0xe08cc00f, /* add ip, ip, pc */
2340 0xea000000, /* b .Lplt_tail */
2341};
e5a52504 2342
906e58ca
NC		 2343#define ARM_MAX_FWD_BRANCH_OFFSET ((((1 << 23) - 1) << 2) + 8)
2344#define ARM_MAX_BWD_BRANCH_OFFSET ((-((1 << 23) << 2)) + 8)
2345#define THM_MAX_FWD_BRANCH_OFFSET ((1 << 22) -2 + 4)
2346#define THM_MAX_BWD_BRANCH_OFFSET (-(1 << 22) + 4)
2347#define THM2_MAX_FWD_BRANCH_OFFSET (((1 << 24) - 2) + 4)
2348#define THM2_MAX_BWD_BRANCH_OFFSET (-(1 << 24) + 4)
c5423981
TG		 2349#define THM2_MAX_FWD_COND_BRANCH_OFFSET (((1 << 20) -2) + 4)
2350#define THM2_MAX_BWD_COND_BRANCH_OFFSET (-(1 << 20) + 4)
906e58ca 2351
461a49ca 2352enum stub_insn_type
b38cadfb
NC		 2353{
2354 THUMB16_TYPE = 1,
2355 THUMB32_TYPE,
2356 ARM_TYPE,
2357 DATA_TYPE
2358};
461a49ca 2359
48229727
JB		 2360#define THUMB16_INSN(X) {(X), THUMB16_TYPE, R_ARM_NONE, 0}
2361/* A bit of a hack. A Thumb conditional branch, in which the proper condition
2362 is inserted in arm_build_one_stub(). */
2363#define THUMB16_BCOND_INSN(X) {(X), THUMB16_TYPE, R_ARM_NONE, 1}
2364#define THUMB32_INSN(X) {(X), THUMB32_TYPE, R_ARM_NONE, 0}
d5a67c02
AV		 2365#define THUMB32_MOVT(X) {(X), THUMB32_TYPE, R_ARM_THM_MOVT_ABS, 0}
2366#define THUMB32_MOVW(X) {(X), THUMB32_TYPE, R_ARM_THM_MOVW_ABS_NC, 0}
48229727
JB		 2367#define THUMB32_B_INSN(X, Z) {(X), THUMB32_TYPE, R_ARM_THM_JUMP24, (Z)}
2368#define ARM_INSN(X) {(X), ARM_TYPE, R_ARM_NONE, 0}
2369#define ARM_REL_INSN(X, Z) {(X), ARM_TYPE, R_ARM_JUMP24, (Z)}
2370#define DATA_WORD(X,Y,Z) {(X), DATA_TYPE, (Y), (Z)}
461a49ca
DJ		 2371
2372typedef struct
2373{
b38cadfb
NC		 2374 bfd_vma data;
2375 enum stub_insn_type type;
2376 unsigned int r_type;
2377 int reloc_addend;
461a49ca
DJ		 2378} insn_sequence;
2379
fea2b4d6
CL		 2380/* Arm/Thumb -> Arm/Thumb long branch stub. On V5T and above, use blx
2381 to reach the stub if necessary. */
461a49ca 2382static const insn_sequence elf32_arm_stub_long_branch_any_any[] =
b38cadfb
NC		 2383{
2384 ARM_INSN (0xe51ff004), /* ldr pc, [pc, #-4] */
2385 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(X) */
2386};
906e58ca 2387
fea2b4d6
CL		 2388/* V4T Arm -> Thumb long branch stub. Used on V4T where blx is not
2389 available. */
461a49ca 2390static const insn_sequence elf32_arm_stub_long_branch_v4t_arm_thumb[] =
b38cadfb
NC		 2391{
2392 ARM_INSN (0xe59fc000), /* ldr ip, [pc, #0] */
2393 ARM_INSN (0xe12fff1c), /* bx ip */
2394 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(X) */
2395};
906e58ca 2396
d3626fb0 2397/* Thumb -> Thumb long branch stub. Used on M-profile architectures. */
461a49ca 2398static const insn_sequence elf32_arm_stub_long_branch_thumb_only[] =
b38cadfb
NC		 2399{
2400 THUMB16_INSN (0xb401), /* push {r0} */
2401 THUMB16_INSN (0x4802), /* ldr r0, [pc, #8] */
2402 THUMB16_INSN (0x4684), /* mov ip, r0 */
2403 THUMB16_INSN (0xbc01), /* pop {r0} */
2404 THUMB16_INSN (0x4760), /* bx ip */
2405 THUMB16_INSN (0xbf00), /* nop */
2406 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(X) */
2407};
906e58ca 2408
80c135e5
TP		 2409/* Thumb -> Thumb long branch stub in thumb2 encoding. Used on armv7. */
2410static const insn_sequence elf32_arm_stub_long_branch_thumb2_only[] =
2411{
2412 THUMB32_INSN (0xf85ff000), /* ldr.w pc, [pc, #-0] */
2413 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(x) */
2414};
2415
d5a67c02
AV		 2416/* Thumb -> Thumb long branch stub. Used for PureCode sections on Thumb2
2417 M-profile architectures. */
2418static const insn_sequence elf32_arm_stub_long_branch_thumb2_only_pure[] =
2419{
2420 THUMB32_MOVW (0xf2400c00), /* mov.w ip, R_ARM_MOVW_ABS_NC */
2421 THUMB32_MOVT (0xf2c00c00), /* movt ip, R_ARM_MOVT_ABS << 16 */
2422 THUMB16_INSN (0x4760), /* bx ip */
2423};
2424
d3626fb0
CL		 2425/* V4T Thumb -> Thumb long branch stub. Using the stack is not
2426 allowed. */
2427static const insn_sequence elf32_arm_stub_long_branch_v4t_thumb_thumb[] =
b38cadfb
NC		 2428{
2429 THUMB16_INSN (0x4778), /* bx pc */
2430 THUMB16_INSN (0x46c0), /* nop */
2431 ARM_INSN (0xe59fc000), /* ldr ip, [pc, #0] */
2432 ARM_INSN (0xe12fff1c), /* bx ip */
2433 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(X) */
2434};
d3626fb0 2435
fea2b4d6
CL		 2436/* V4T Thumb -> ARM long branch stub. Used on V4T where blx is not
2437 available. */
461a49ca 2438static const insn_sequence elf32_arm_stub_long_branch_v4t_thumb_arm[] =
b38cadfb
NC		 2439{
2440 THUMB16_INSN (0x4778), /* bx pc */
2441 THUMB16_INSN (0x46c0), /* nop */
2442 ARM_INSN (0xe51ff004), /* ldr pc, [pc, #-4] */
2443 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(X) */
2444};
906e58ca 2445
fea2b4d6
CL		 2446/* V4T Thumb -> ARM short branch stub. Shorter variant of the above
2447 one, when the destination is close enough. */
461a49ca 2448static const insn_sequence elf32_arm_stub_short_branch_v4t_thumb_arm[] =
b38cadfb
NC		 2449{
2450 THUMB16_INSN (0x4778), /* bx pc */
2451 THUMB16_INSN (0x46c0), /* nop */
2452 ARM_REL_INSN (0xea000000, -8), /* b (X-8) */
2453};
c820be07 2454
cf3eccff 2455/* ARM/Thumb -> ARM long branch stub, PIC. On V5T and above, use
fea2b4d6 2456 blx to reach the stub if necessary. */
cf3eccff 2457static const insn_sequence elf32_arm_stub_long_branch_any_arm_pic[] =
b38cadfb
NC		 2458{
2459 ARM_INSN (0xe59fc000), /* ldr ip, [pc] */
2460 ARM_INSN (0xe08ff00c), /* add pc, pc, ip */
2461 DATA_WORD (0, R_ARM_REL32, -4), /* dcd R_ARM_REL32(X-4) */
2462};
906e58ca 2463
cf3eccff
DJ		 2464/* ARM/Thumb -> Thumb long branch stub, PIC. On V5T and above, use
2465 blx to reach the stub if necessary. We can not add into pc;
2466 it is not guaranteed to mode switch (different in ARMv6 and
2467 ARMv7). */
2468static const insn_sequence elf32_arm_stub_long_branch_any_thumb_pic[] =
b38cadfb
NC		 2469{
2470 ARM_INSN (0xe59fc004), /* ldr ip, [pc, #4] */
2471 ARM_INSN (0xe08fc00c), /* add ip, pc, ip */
2472 ARM_INSN (0xe12fff1c), /* bx ip */
2473 DATA_WORD (0, R_ARM_REL32, 0), /* dcd R_ARM_REL32(X) */
2474};
cf3eccff 2475
ebe24dd4
CL		 2476/* V4T ARM -> ARM long branch stub, PIC. */
2477static const insn_sequence elf32_arm_stub_long_branch_v4t_arm_thumb_pic[] =
b38cadfb
NC		 2478{
2479 ARM_INSN (0xe59fc004), /* ldr ip, [pc, #4] */
2480 ARM_INSN (0xe08fc00c), /* add ip, pc, ip */
2481 ARM_INSN (0xe12fff1c), /* bx ip */
2482 DATA_WORD (0, R_ARM_REL32, 0), /* dcd R_ARM_REL32(X) */
2483};
ebe24dd4
CL		 2484
2485/* V4T Thumb -> ARM long branch stub, PIC. */
2486static const insn_sequence elf32_arm_stub_long_branch_v4t_thumb_arm_pic[] =
b38cadfb
NC		 2487{
2488 THUMB16_INSN (0x4778), /* bx pc */
2489 THUMB16_INSN (0x46c0), /* nop */
2490 ARM_INSN (0xe59fc000), /* ldr ip, [pc, #0] */
2491 ARM_INSN (0xe08cf00f), /* add pc, ip, pc */
2492 DATA_WORD (0, R_ARM_REL32, -4), /* dcd R_ARM_REL32(X) */
2493};
ebe24dd4 2494
d3626fb0
CL		 2495/* Thumb -> Thumb long branch stub, PIC. Used on M-profile
2496 architectures. */
ebe24dd4 2497static const insn_sequence elf32_arm_stub_long_branch_thumb_only_pic[] =
b38cadfb
NC		 2498{
2499 THUMB16_INSN (0xb401), /* push {r0} */
2500 THUMB16_INSN (0x4802), /* ldr r0, [pc, #8] */
2501 THUMB16_INSN (0x46fc), /* mov ip, pc */
2502 THUMB16_INSN (0x4484), /* add ip, r0 */
2503 THUMB16_INSN (0xbc01), /* pop {r0} */
2504 THUMB16_INSN (0x4760), /* bx ip */
2505 DATA_WORD (0, R_ARM_REL32, 4), /* dcd R_ARM_REL32(X) */
2506};
ebe24dd4 2507
d3626fb0
CL		 2508/* V4T Thumb -> Thumb long branch stub, PIC. Using the stack is not
2509 allowed. */
2510static const insn_sequence elf32_arm_stub_long_branch_v4t_thumb_thumb_pic[] =
b38cadfb
NC		 2511{
2512 THUMB16_INSN (0x4778), /* bx pc */
2513 THUMB16_INSN (0x46c0), /* nop */
2514 ARM_INSN (0xe59fc004), /* ldr ip, [pc, #4] */
2515 ARM_INSN (0xe08fc00c), /* add ip, pc, ip */
2516 ARM_INSN (0xe12fff1c), /* bx ip */
2517 DATA_WORD (0, R_ARM_REL32, 0), /* dcd R_ARM_REL32(X) */
2518};
d3626fb0 2519
0855e32b
NS		 2520/* Thumb2/ARM -> TLS trampoline. Lowest common denominator, which is a
2521 long PIC stub. We can use r1 as a scratch -- and cannot use ip. */
2522static const insn_sequence elf32_arm_stub_long_branch_any_tls_pic[] =
2523{
b38cadfb
NC		 2524 ARM_INSN (0xe59f1000), /* ldr r1, [pc] */
2525 ARM_INSN (0xe08ff001), /* add pc, pc, r1 */
2526 DATA_WORD (0, R_ARM_REL32, -4), /* dcd R_ARM_REL32(X-4) */
0855e32b
NS		 2527};
2528
2529/* V4T Thumb -> TLS trampoline. lowest common denominator, which is a
2530 long PIC stub. We can use r1 as a scratch -- and cannot use ip. */
2531static const insn_sequence elf32_arm_stub_long_branch_v4t_thumb_tls_pic[] =
2532{
b38cadfb
NC		 2533 THUMB16_INSN (0x4778), /* bx pc */
2534 THUMB16_INSN (0x46c0), /* nop */
2535 ARM_INSN (0xe59f1000), /* ldr r1, [pc, #0] */
2536 ARM_INSN (0xe081f00f), /* add pc, r1, pc */
2537 DATA_WORD (0, R_ARM_REL32, -4), /* dcd R_ARM_REL32(X) */
0855e32b
NS		 2538};
2539
7a89b94e
NC		 2540/* NaCl ARM -> ARM long branch stub. */
2541static const insn_sequence elf32_arm_stub_long_branch_arm_nacl[] =
2542{
2543 ARM_INSN (0xe59fc00c), /* ldr ip, [pc, #12] */
2544 ARM_INSN (0xe3ccc13f), /* bic ip, ip, #0xc000000f */
2545 ARM_INSN (0xe12fff1c), /* bx ip */
2546 ARM_INSN (0xe320f000), /* nop */
2547 ARM_INSN (0xe125be70), /* bkpt 0x5be0 */
2548 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(X) */
2549 DATA_WORD (0, R_ARM_NONE, 0), /* .word 0 */
2550 DATA_WORD (0, R_ARM_NONE, 0), /* .word 0 */
2551};
2552
2553/* NaCl ARM -> ARM long branch stub, PIC. */
2554static const insn_sequence elf32_arm_stub_long_branch_arm_nacl_pic[] =
2555{
2556 ARM_INSN (0xe59fc00c), /* ldr ip, [pc, #12] */
2557 ARM_INSN (0xe08cc00f), /* add ip, ip, pc */
2558 ARM_INSN (0xe3ccc13f), /* bic ip, ip, #0xc000000f */
2559 ARM_INSN (0xe12fff1c), /* bx ip */
2560 ARM_INSN (0xe125be70), /* bkpt 0x5be0 */
2561 DATA_WORD (0, R_ARM_REL32, 8), /* dcd R_ARM_REL32(X+8) */
2562 DATA_WORD (0, R_ARM_NONE, 0), /* .word 0 */
2563 DATA_WORD (0, R_ARM_NONE, 0), /* .word 0 */
2564};
2565
4ba2ef8f
TP		 2566/* Stub used for transition to secure state (aka SG veneer). */
2567static const insn_sequence elf32_arm_stub_cmse_branch_thumb_only[] =
2568{
2569 THUMB32_INSN (0xe97fe97f), /* sg. */
2570 THUMB32_B_INSN (0xf000b800, -4), /* b.w original_branch_dest. */
2571};
2572
7a89b94e 2573
48229727
JB		 2574/* Cortex-A8 erratum-workaround stubs. */
2575
2576/* Stub used for conditional branches (which may be beyond +/-1MB away, so we
2577 can't use a conditional branch to reach this stub). */
2578
2579static const insn_sequence elf32_arm_stub_a8_veneer_b_cond[] =
b38cadfb
NC		 2580{
2581 THUMB16_BCOND_INSN (0xd001), /* b<cond>.n true. */
2582 THUMB32_B_INSN (0xf000b800, -4), /* b.w insn_after_original_branch. */
2583 THUMB32_B_INSN (0xf000b800, -4) /* true: b.w original_branch_dest. */
2584};
48229727
JB		 2585
2586/* Stub used for b.w and bl.w instructions. */
2587
2588static const insn_sequence elf32_arm_stub_a8_veneer_b[] =
b38cadfb
NC		 2589{
2590 THUMB32_B_INSN (0xf000b800, -4) /* b.w original_branch_dest. */
2591};
48229727
JB		 2592
2593static const insn_sequence elf32_arm_stub_a8_veneer_bl[] =
b38cadfb
NC		 2594{
2595 THUMB32_B_INSN (0xf000b800, -4) /* b.w original_branch_dest. */
2596};
48229727
JB		 2597
2598/* Stub used for Thumb-2 blx.w instructions. We modified the original blx.w
2599 instruction (which switches to ARM mode) to point to this stub. Jump to the
2600 real destination using an ARM-mode branch. */
2601
2602static const insn_sequence elf32_arm_stub_a8_veneer_blx[] =
b38cadfb
NC		 2603{
2604 ARM_REL_INSN (0xea000000, -8) /* b original_branch_dest. */
2605};
48229727 2606
9553db3c
NC		 2607/* For each section group there can be a specially created linker section
2608 to hold the stubs for that group. The name of the stub section is based
2609 upon the name of another section within that group with the suffix below
2610 applied.
2611
2612 PR 13049: STUB_SUFFIX used to be ".stub", but this allowed the user to
2613 create what appeared to be a linker stub section when it actually
2614 contained user code/data. For example, consider this fragment:
b38cadfb 2615
9553db3c
NC		 2616 const char * stubborn_problems[] = { "np" };
2617
2618 If this is compiled with "-fPIC -fdata-sections" then gcc produces a
2619 section called:
2620
2621 .data.rel.local.stubborn_problems
2622
2623 This then causes problems in arm32_arm_build_stubs() as it triggers:
2624
2625 // Ignore non-stub sections.
2626 if (!strstr (stub_sec->name, STUB_SUFFIX))
2627 continue;
2628
2629 And so the section would be ignored instead of being processed. Hence
2630 the change in definition of STUB_SUFFIX to a name that cannot be a valid
2631 C identifier. */
2632#define STUB_SUFFIX ".__stub"
906e58ca 2633
738a79f6
CL		 2634/* One entry per long/short branch stub defined above. */
2635#define DEF_STUBS \
2636 DEF_STUB(long_branch_any_any) \
2637 DEF_STUB(long_branch_v4t_arm_thumb) \
2638 DEF_STUB(long_branch_thumb_only) \
2639 DEF_STUB(long_branch_v4t_thumb_thumb) \
2640 DEF_STUB(long_branch_v4t_thumb_arm) \
2641 DEF_STUB(short_branch_v4t_thumb_arm) \
2642 DEF_STUB(long_branch_any_arm_pic) \
2643 DEF_STUB(long_branch_any_thumb_pic) \
2644 DEF_STUB(long_branch_v4t_thumb_thumb_pic) \
2645 DEF_STUB(long_branch_v4t_arm_thumb_pic) \
2646 DEF_STUB(long_branch_v4t_thumb_arm_pic) \
48229727 2647 DEF_STUB(long_branch_thumb_only_pic) \
0855e32b
NS		 2648 DEF_STUB(long_branch_any_tls_pic) \
2649 DEF_STUB(long_branch_v4t_thumb_tls_pic) \
7a89b94e
NC		 2650 DEF_STUB(long_branch_arm_nacl) \
2651 DEF_STUB(long_branch_arm_nacl_pic) \
4ba2ef8f 2652 DEF_STUB(cmse_branch_thumb_only) \
48229727
JB		 2653 DEF_STUB(a8_veneer_b_cond) \
2654 DEF_STUB(a8_veneer_b) \
2655 DEF_STUB(a8_veneer_bl) \
80c135e5
TP		 2656 DEF_STUB(a8_veneer_blx) \
2657 DEF_STUB(long_branch_thumb2_only) \
d5a67c02 2658 DEF_STUB(long_branch_thumb2_only_pure)
738a79f6
CL		 2659
2660#define DEF_STUB(x) arm_stub_##x,
b38cadfb
NC		 2661enum elf32_arm_stub_type
2662{
906e58ca 2663 arm_stub_none,
738a79f6 2664 DEF_STUBS
4f4faa4d 2665 max_stub_type
738a79f6
CL		 2666};
2667#undef DEF_STUB
2668
8d9d9490
TP		 2669/* Note the first a8_veneer type. */
2670const unsigned arm_stub_a8_veneer_lwm = arm_stub_a8_veneer_b_cond;
2671
738a79f6
CL		 2672typedef struct
2673{
d3ce72d0 2674 const insn_sequence* template_sequence;
738a79f6
CL		 2675 int template_size;
2676} stub_def;
2677
2678#define DEF_STUB(x) {elf32_arm_stub_##x, ARRAY_SIZE(elf32_arm_stub_##x)},
b38cadfb
NC		 2679static const stub_def stub_definitions[] =
2680{
738a79f6
CL		 2681 {NULL, 0},
2682 DEF_STUBS
906e58ca
NC		 2683};
2684
2685struct elf32_arm_stub_hash_entry
2686{
2687 /* Base hash table entry structure. */
2688 struct bfd_hash_entry root;
2689
2690 /* The stub section. */
2691 asection *stub_sec;
2692
2693 /* Offset within stub_sec of the beginning of this stub. */
2694 bfd_vma stub_offset;
2695
2696 /* Given the symbol's value and its section we can determine its final
2697 value when building the stubs (so the stub knows where to jump). */
2698 bfd_vma target_value;
2699 asection *target_section;
2700
8d9d9490
TP		 2701 /* Same as above but for the source of the branch to the stub. Used for
2702 Cortex-A8 erratum workaround to patch it to branch to the stub. As
2703 such, source section does not need to be recorded since Cortex-A8 erratum
2704 workaround stubs are only generated when both source and target are in the
2705 same section. */
2706 bfd_vma source_value;
48229727
JB		 2707
2708 /* The instruction which caused this stub to be generated (only valid for
2709 Cortex-A8 erratum workaround stubs at present). */
2710 unsigned long orig_insn;
2711
461a49ca 2712 /* The stub type. */
906e58ca 2713 enum elf32_arm_stub_type stub_type;
461a49ca
DJ		 2714 /* Its encoding size in bytes. */
2715 int stub_size;
2716 /* Its template. */
2717 const insn_sequence *stub_template;
2718 /* The size of the template (number of entries). */
2719 int stub_template_size;
906e58ca
NC		 2720
2721 /* The symbol table entry, if any, that this was derived from. */
2722 struct elf32_arm_link_hash_entry *h;
2723
35fc36a8
RS		 2724 /* Type of branch. */
2725 enum arm_st_branch_type branch_type;
906e58ca
NC		 2726
2727 /* Where this stub is being called from, or, in the case of combined
2728 stub sections, the first input section in the group. */
2729 asection *id_sec;
7413f23f
DJ		 2730
2731 /* The name for the local symbol at the start of this stub. The
2732 stub name in the hash table has to be unique; this does not, so
2733 it can be friendlier. */
2734 char *output_name;
906e58ca
NC		 2735};
2736
e489d0ae
PB		 2737/* Used to build a map of a section. This is required for mixed-endian
2738 code/data. */
2739
2740typedef struct elf32_elf_section_map
2741{
2742 bfd_vma vma;
2743 char type;
2744}
2745elf32_arm_section_map;
2746
c7b8f16e
JB		 2747/* Information about a VFP11 erratum veneer, or a branch to such a veneer. */
2748
2749typedef enum
2750{
2751 VFP11_ERRATUM_BRANCH_TO_ARM_VENEER,
2752 VFP11_ERRATUM_BRANCH_TO_THUMB_VENEER,
2753 VFP11_ERRATUM_ARM_VENEER,
2754 VFP11_ERRATUM_THUMB_VENEER
2755}
2756elf32_vfp11_erratum_type;
2757
2758typedef struct elf32_vfp11_erratum_list
2759{
2760 struct elf32_vfp11_erratum_list *next;
2761 bfd_vma vma;
2762 union
2763 {
2764 struct
2765 {
2766 struct elf32_vfp11_erratum_list *veneer;
2767 unsigned int vfp_insn;
2768 } b;
2769 struct
2770 {
2771 struct elf32_vfp11_erratum_list *branch;
2772 unsigned int id;
2773 } v;
2774 } u;
2775 elf32_vfp11_erratum_type type;
2776}
2777elf32_vfp11_erratum_list;
2778
a504d23a
LA		 2779/* Information about a STM32L4XX erratum veneer, or a branch to such a
2780 veneer. */
2781typedef enum
2782{
2783 STM32L4XX_ERRATUM_BRANCH_TO_VENEER,
2784 STM32L4XX_ERRATUM_VENEER
2785}
2786elf32_stm32l4xx_erratum_type;
2787
2788typedef struct elf32_stm32l4xx_erratum_list
2789{
2790 struct elf32_stm32l4xx_erratum_list *next;
2791 bfd_vma vma;
2792 union
2793 {
2794 struct
2795 {
2796 struct elf32_stm32l4xx_erratum_list *veneer;
2797 unsigned int insn;
2798 } b;
2799 struct
2800 {
2801 struct elf32_stm32l4xx_erratum_list *branch;
2802 unsigned int id;
2803 } v;
2804 } u;
2805 elf32_stm32l4xx_erratum_type type;
2806}
2807elf32_stm32l4xx_erratum_list;
2808
2468f9c9
PB		 2809typedef enum
2810{
2811 DELETE_EXIDX_ENTRY,
2812 INSERT_EXIDX_CANTUNWIND_AT_END
2813}
2814arm_unwind_edit_type;
2815
2816/* A (sorted) list of edits to apply to an unwind table. */
2817typedef struct arm_unwind_table_edit
2818{
2819 arm_unwind_edit_type type;
2820 /* Note: we sometimes want to insert an unwind entry corresponding to a
2821 section different from the one we're currently writing out, so record the
2822 (text) section this edit relates to here. */
2823 asection *linked_section;
2824 unsigned int index;
2825 struct arm_unwind_table_edit *next;
2826}
2827arm_unwind_table_edit;
2828
8e3de13a 2829typedef struct _arm_elf_section_data
e489d0ae 2830{
2468f9c9 2831 /* Information about mapping symbols. */
e489d0ae 2832 struct bfd_elf_section_data elf;
8e3de13a 2833 unsigned int mapcount;
c7b8f16e 2834 unsigned int mapsize;
e489d0ae 2835 elf32_arm_section_map *map;
2468f9c9 2836 /* Information about CPU errata. */
c7b8f16e
JB		 2837 unsigned int erratumcount;
2838 elf32_vfp11_erratum_list *erratumlist;
a504d23a
LA		 2839 unsigned int stm32l4xx_erratumcount;
2840 elf32_stm32l4xx_erratum_list *stm32l4xx_erratumlist;
491d01d3 2841 unsigned int additional_reloc_count;
2468f9c9
PB		 2842 /* Information about unwind tables. */
2843 union
2844 {
2845 /* Unwind info attached to a text section. */
2846 struct
2847 {
2848 asection *arm_exidx_sec;
2849 } text;
2850
2851 /* Unwind info attached to an .ARM.exidx section. */
2852 struct
2853 {
2854 arm_unwind_table_edit *unwind_edit_list;
2855 arm_unwind_table_edit *unwind_edit_tail;
2856 } exidx;
2857 } u;
8e3de13a
NC		 2858}
2859_arm_elf_section_data;
e489d0ae
PB		 2860
2861#define elf32_arm_section_data(sec) \
8e3de13a 2862 ((_arm_elf_section_data *) elf_section_data (sec))
e489d0ae 2863
48229727
JB		 2864/* A fix which might be required for Cortex-A8 Thumb-2 branch/TLB erratum.
2865 These fixes are subject to a relaxation procedure (in elf32_arm_size_stubs),
2866 so may be created multiple times: we use an array of these entries whilst
2867 relaxing which we can refresh easily, then create stubs for each potentially
2868 erratum-triggering instruction once we've settled on a solution. */
2869
b38cadfb
NC		 2870struct a8_erratum_fix
2871{
48229727
JB		 2872 bfd *input_bfd;
2873 asection *section;
2874 bfd_vma offset;
8d9d9490 2875 bfd_vma target_offset;
48229727
JB		 2876 unsigned long orig_insn;
2877 char *stub_name;
2878 enum elf32_arm_stub_type stub_type;
35fc36a8 2879 enum arm_st_branch_type branch_type;
48229727
JB		 2880};
2881
2882/* A table of relocs applied to branches which might trigger Cortex-A8
2883 erratum. */
2884
b38cadfb
NC		 2885struct a8_erratum_reloc
2886{
48229727
JB		 2887 bfd_vma from;
2888 bfd_vma destination;
92750f34
DJ		 2889 struct elf32_arm_link_hash_entry *hash;
2890 const char *sym_name;
48229727 2891 unsigned int r_type;
35fc36a8 2892 enum arm_st_branch_type branch_type;
48229727
JB		 2893 bfd_boolean non_a8_stub;
2894};
2895
ba93b8ac
DJ		 2896/* The size of the thread control block. */
2897#define TCB_SIZE 8
2898
34e77a92
RS		 2899/* ARM-specific information about a PLT entry, over and above the usual
2900 gotplt_union. */
b38cadfb
NC		 2901struct arm_plt_info
2902{
34e77a92
RS		 2903 /* We reference count Thumb references to a PLT entry separately,
2904 so that we can emit the Thumb trampoline only if needed. */
2905 bfd_signed_vma thumb_refcount;
2906
2907 /* Some references from Thumb code may be eliminated by BL->BLX
2908 conversion, so record them separately. */
2909 bfd_signed_vma maybe_thumb_refcount;
2910
2911 /* How many of the recorded PLT accesses were from non-call relocations.
2912 This information is useful when deciding whether anything takes the
2913 address of an STT_GNU_IFUNC PLT. A value of 0 means that all
2914 non-call references to the function should resolve directly to the
2915 real runtime target. */
2916 unsigned int noncall_refcount;
2917
2918 /* Since PLT entries have variable size if the Thumb prologue is
2919 used, we need to record the index into .got.plt instead of
2920 recomputing it from the PLT offset. */
2921 bfd_signed_vma got_offset;
2922};
2923
2924/* Information about an .iplt entry for a local STT_GNU_IFUNC symbol. */
b38cadfb
NC		 2925struct arm_local_iplt_info
2926{
34e77a92
RS		 2927 /* The information that is usually found in the generic ELF part of
2928 the hash table entry. */
2929 union gotplt_union root;
2930
2931 /* The information that is usually found in the ARM-specific part of
2932 the hash table entry. */
2933 struct arm_plt_info arm;
2934
2935 /* A list of all potential dynamic relocations against this symbol. */
2936 struct elf_dyn_relocs *dyn_relocs;
2937};
2938
0ffa91dd 2939struct elf_arm_obj_tdata
ba93b8ac
DJ		 2940{
2941 struct elf_obj_tdata root;
2942
2943 /* tls_type for each local got entry. */
2944 char *local_got_tls_type;
ee065d83 2945
0855e32b
NS		 2946 /* GOTPLT entries for TLS descriptors. */
2947 bfd_vma *local_tlsdesc_gotent;
2948
34e77a92
RS		 2949 /* Information for local symbols that need entries in .iplt. */
2950 struct arm_local_iplt_info **local_iplt;
2951
bf21ed78
MS		 2952 /* Zero to warn when linking objects with incompatible enum sizes. */
2953 int no_enum_size_warning;
a9dc9481
JM		 2954
2955 /* Zero to warn when linking objects with incompatible wchar_t sizes. */
2956 int no_wchar_size_warning;
ba93b8ac
DJ		 2957};
2958
0ffa91dd
NC		 2959#define elf_arm_tdata(bfd) \
2960 ((struct elf_arm_obj_tdata *) (bfd)->tdata.any)
ba93b8ac 2961
0ffa91dd
NC		 2962#define elf32_arm_local_got_tls_type(bfd) \
2963 (elf_arm_tdata (bfd)->local_got_tls_type)
2964
0855e32b
NS		 2965#define elf32_arm_local_tlsdesc_gotent(bfd) \
2966 (elf_arm_tdata (bfd)->local_tlsdesc_gotent)
2967
34e77a92
RS		 2968#define elf32_arm_local_iplt(bfd) \
2969 (elf_arm_tdata (bfd)->local_iplt)
2970
0ffa91dd
NC		 2971#define is_arm_elf(bfd) \
2972 (bfd_get_flavour (bfd) == bfd_target_elf_flavour \
2973 && elf_tdata (bfd) != NULL \
4dfe6ac6 2974 && elf_object_id (bfd) == ARM_ELF_DATA)
ba93b8ac
DJ		 2975
2976static bfd_boolean
2977elf32_arm_mkobject (bfd *abfd)
2978{
0ffa91dd 2979 return bfd_elf_allocate_object (abfd, sizeof (struct elf_arm_obj_tdata),
4dfe6ac6 2980 ARM_ELF_DATA);
ba93b8ac
DJ		 2981}
2982
ba93b8ac
DJ		 2983#define elf32_arm_hash_entry(ent) ((struct elf32_arm_link_hash_entry *)(ent))
2984
ba96a88f 2985/* Arm ELF linker hash entry. */
252b5132 2986struct elf32_arm_link_hash_entry
b38cadfb
NC		 2987{
2988 struct elf_link_hash_entry root;
252b5132 2989
b38cadfb
NC		 2990 /* Track dynamic relocs copied for this symbol. */
2991 struct elf_dyn_relocs *dyn_relocs;
b7693d02 2992
b38cadfb
NC		 2993 /* ARM-specific PLT information. */
2994 struct arm_plt_info plt;
ba93b8ac
DJ		 2995
2996#define GOT_UNKNOWN 0
2997#define GOT_NORMAL 1
2998#define GOT_TLS_GD 2
2999#define GOT_TLS_IE 4
0855e32b
NS		 3000#define GOT_TLS_GDESC 8
3001#define GOT_TLS_GD_ANY_P(type) ((type & GOT_TLS_GD) || (type & GOT_TLS_GDESC))
b38cadfb 3002 unsigned int tls_type : 8;
34e77a92 3003
b38cadfb
NC		 3004 /* True if the symbol's PLT entry is in .iplt rather than .plt. */
3005 unsigned int is_iplt : 1;
34e77a92 3006
b38cadfb 3007 unsigned int unused : 23;
a4fd1a8e 3008
b38cadfb
NC		 3009 /* Offset of the GOTPLT entry reserved for the TLS descriptor,
3010 starting at the end of the jump table. */
3011 bfd_vma tlsdesc_got;
0855e32b 3012
b38cadfb
NC		 3013 /* The symbol marking the real symbol location for exported thumb
3014 symbols with Arm stubs. */
3015 struct elf_link_hash_entry *export_glue;
906e58ca 3016
b38cadfb 3017 /* A pointer to the most recently used stub hash entry against this
8029a119 3018 symbol. */
b38cadfb
NC		 3019 struct elf32_arm_stub_hash_entry *stub_cache;
3020};
252b5132 3021
252b5132 3022/* Traverse an arm ELF linker hash table. */
252b5132
RH		 3023#define elf32_arm_link_hash_traverse(table, func, info) \
3024 (elf_link_hash_traverse \
3025 (&(table)->root, \
b7693d02 3026 (bfd_boolean (*) (struct elf_link_hash_entry *, void *)) (func), \
252b5132
RH		 3027 (info)))
3028
3029/* Get the ARM elf linker hash table from a link_info structure. */
3030#define elf32_arm_hash_table(info) \
4dfe6ac6
NC		 3031 (elf_hash_table_id ((struct elf_link_hash_table *) ((info)->hash)) \
3032 == ARM_ELF_DATA ? ((struct elf32_arm_link_hash_table *) ((info)->hash)) : NULL)
252b5132 3033
906e58ca
NC		 3034#define arm_stub_hash_lookup(table, string, create, copy) \
3035 ((struct elf32_arm_stub_hash_entry *) \
3036 bfd_hash_lookup ((table), (string), (create), (copy)))
3037
21d799b5
NC		 3038/* Array to keep track of which stub sections have been created, and
3039 information on stub grouping. */
3040struct map_stub
3041{
3042 /* This is the section to which stubs in the group will be
3043 attached. */
3044 asection *link_sec;
3045 /* The stub section. */
3046 asection *stub_sec;
3047};
3048
0855e32b
NS		 3049#define elf32_arm_compute_jump_table_size(htab) \
3050 ((htab)->next_tls_desc_index * 4)
3051
9b485d32 3052/* ARM ELF linker hash table. */
252b5132 3053struct elf32_arm_link_hash_table
906e58ca
NC		 3054{
3055 /* The main hash table. */
3056 struct elf_link_hash_table root;
252b5132 3057
906e58ca
NC		 3058 /* The size in bytes of the section containing the Thumb-to-ARM glue. */
3059 bfd_size_type thumb_glue_size;
252b5132 3060
906e58ca
NC		 3061 /* The size in bytes of the section containing the ARM-to-Thumb glue. */
3062 bfd_size_type arm_glue_size;
252b5132 3063
906e58ca
NC		 3064 /* The size in bytes of section containing the ARMv4 BX veneers. */
3065 bfd_size_type bx_glue_size;
845b51d6 3066
906e58ca
NC		 3067 /* Offsets of ARMv4 BX veneers. Bit1 set if present, and Bit0 set when
3068 veneer has been populated. */
3069 bfd_vma bx_glue_offset[15];
845b51d6 3070
906e58ca
NC		 3071 /* The size in bytes of the section containing glue for VFP11 erratum
3072 veneers. */
3073 bfd_size_type vfp11_erratum_glue_size;
c7b8f16e 3074
a504d23a
LA		 3075 /* The size in bytes of the section containing glue for STM32L4XX erratum
3076 veneers. */
3077 bfd_size_type stm32l4xx_erratum_glue_size;
3078
48229727
JB		 3079 /* A table of fix locations for Cortex-A8 Thumb-2 branch/TLB erratum. This
3080 holds Cortex-A8 erratum fix locations between elf32_arm_size_stubs() and
3081 elf32_arm_write_section(). */
3082 struct a8_erratum_fix *a8_erratum_fixes;
3083 unsigned int num_a8_erratum_fixes;
3084
906e58ca
NC		 3085 /* An arbitrary input BFD chosen to hold the glue sections. */
3086 bfd * bfd_of_glue_owner;
ba96a88f 3087
906e58ca
NC		 3088 /* Nonzero to output a BE8 image. */
3089 int byteswap_code;
e489d0ae 3090
906e58ca
NC		 3091 /* Zero if R_ARM_TARGET1 means R_ARM_ABS32.
3092 Nonzero if R_ARM_TARGET1 means R_ARM_REL32. */
3093 int target1_is_rel;
9c504268 3094
906e58ca
NC		 3095 /* The relocation to use for R_ARM_TARGET2 relocations. */
3096 int target2_reloc;
eb043451 3097
906e58ca
NC		 3098 /* 0 = Ignore R_ARM_V4BX.
3099 1 = Convert BX to MOV PC.
3100 2 = Generate v4 interworing stubs. */
3101 int fix_v4bx;
319850b4 3102
48229727
JB		 3103 /* Whether we should fix the Cortex-A8 Thumb-2 branch/TLB erratum. */
3104 int fix_cortex_a8;
3105
2de70689
MGD		 3106 /* Whether we should fix the ARM1176 BLX immediate issue. */
3107 int fix_arm1176;
3108
906e58ca
NC		 3109 /* Nonzero if the ARM/Thumb BLX instructions are available for use. */
3110 int use_blx;
33bfe774 3111
906e58ca
NC		 3112 /* What sort of code sequences we should look for which may trigger the
3113 VFP11 denorm erratum. */
3114 bfd_arm_vfp11_fix vfp11_fix;
c7b8f16e 3115
906e58ca
NC		 3116 /* Global counter for the number of fixes we have emitted. */
3117 int num_vfp11_fixes;
c7b8f16e 3118
a504d23a
LA		 3119 /* What sort of code sequences we should look for which may trigger the
3120 STM32L4XX erratum. */
3121 bfd_arm_stm32l4xx_fix stm32l4xx_fix;
3122
3123 /* Global counter for the number of fixes we have emitted. */
3124 int num_stm32l4xx_fixes;
3125
906e58ca
NC		 3126 /* Nonzero to force PIC branch veneers. */
3127 int pic_veneer;
27e55c4d 3128
906e58ca
NC		 3129 /* The number of bytes in the initial entry in the PLT. */
3130 bfd_size_type plt_header_size;
e5a52504 3131
906e58ca
NC		 3132 /* The number of bytes in the subsequent PLT etries. */
3133 bfd_size_type plt_entry_size;
e5a52504 3134
906e58ca
NC		 3135 /* True if the target system is VxWorks. */
3136 int vxworks_p;
00a97672 3137
906e58ca
NC		 3138 /* True if the target system is Symbian OS. */
3139 int symbian_p;
e5a52504 3140
b38cadfb
NC		 3141 /* True if the target system is Native Client. */
3142 int nacl_p;
3143
906e58ca
NC		 3144 /* True if the target uses REL relocations. */
3145 int use_rel;
4e7fd91e 3146
54ddd295
TP		 3147 /* Nonzero if import library must be a secure gateway import library
3148 as per ARMv8-M Security Extensions. */
3149 int cmse_implib;
3150
0955507f
TP		 3151 /* The import library whose symbols' address must remain stable in
3152 the import library generated. */
3153 bfd *in_implib_bfd;
3154
0855e32b
NS		 3155 /* The index of the next unused R_ARM_TLS_DESC slot in .rel.plt. */
3156 bfd_vma next_tls_desc_index;
3157
3158 /* How many R_ARM_TLS_DESC relocations were generated so far. */
3159 bfd_vma num_tls_desc;
3160
906e58ca 3161 /* Short-cuts to get to dynamic linker sections. */
906e58ca
NC		 3162 asection *sdynbss;
3163 asection *srelbss;
5e681ec4 3164
906e58ca
NC		 3165 /* The (unloaded but important) VxWorks .rela.plt.unloaded section. */
3166 asection *srelplt2;
00a97672 3167
0855e32b
NS		 3168 /* The offset into splt of the PLT entry for the TLS descriptor
3169 resolver. Special values are 0, if not necessary (or not found
3170 to be necessary yet), and -1 if needed but not determined
3171 yet. */
3172 bfd_vma dt_tlsdesc_plt;
3173
3174 /* The offset into sgot of the GOT entry used by the PLT entry
3175 above. */
b38cadfb 3176 bfd_vma dt_tlsdesc_got;
0855e32b
NS		 3177
3178 /* Offset in .plt section of tls_arm_trampoline. */
3179 bfd_vma tls_trampoline;
3180
906e58ca
NC		 3181 /* Data for R_ARM_TLS_LDM32 relocations. */
3182 union
3183 {
3184 bfd_signed_vma refcount;
3185 bfd_vma offset;
3186 } tls_ldm_got;
b7693d02 3187
87d72d41
AM		 3188 /* Small local sym cache. */
3189 struct sym_cache sym_cache;
906e58ca
NC		 3190
3191 /* For convenience in allocate_dynrelocs. */
3192 bfd * obfd;
3193
0855e32b
NS		 3194 /* The amount of space used by the reserved portion of the sgotplt
3195 section, plus whatever space is used by the jump slots. */
3196 bfd_vma sgotplt_jump_table_size;
3197
906e58ca
NC		 3198 /* The stub hash table. */
3199 struct bfd_hash_table stub_hash_table;
3200
3201 /* Linker stub bfd. */
3202 bfd *stub_bfd;
3203
3204 /* Linker call-backs. */
6bde4c52
TP		 3205 asection * (*add_stub_section) (const char *, asection *, asection *,
3206 unsigned int);
906e58ca
NC		 3207 void (*layout_sections_again) (void);
3208
3209 /* Array to keep track of which stub sections have been created, and
3210 information on stub grouping. */
21d799b5 3211 struct map_stub *stub_group;
906e58ca 3212
4ba2ef8f
TP		 3213 /* Input stub section holding secure gateway veneers. */
3214 asection *cmse_stub_sec;
3215
0955507f
TP		 3216 /* Offset in cmse_stub_sec where new SG veneers (not in input import library)
3217 start to be allocated. */
3218 bfd_vma new_cmse_stub_offset;
3219
fe33d2fa 3220 /* Number of elements in stub_group. */
7292b3ac 3221 unsigned int top_id;
fe33d2fa 3222
906e58ca
NC		 3223 /* Assorted information used by elf32_arm_size_stubs. */
3224 unsigned int bfd_count;
7292b3ac 3225 unsigned int top_index;
906e58ca
NC		 3226 asection **input_list;
3227};
252b5132 3228
a504d23a
LA		 3229static inline int
3230ctz (unsigned int mask)
3231{
3232#if GCC_VERSION >= 3004
3233 return __builtin_ctz (mask);
3234#else
3235 unsigned int i;
3236
3237 for (i = 0; i < 8 * sizeof (mask); i++)
3238 {
3239 if (mask & 0x1)
3240 break;
3241 mask = (mask >> 1);
3242 }
3243 return i;
3244#endif
3245}
3246
3247static inline int
b25e998d 3248elf32_arm_popcount (unsigned int mask)
a504d23a
LA		 3249{
3250#if GCC_VERSION >= 3004
3251 return __builtin_popcount (mask);
3252#else
b25e998d
CG		 3253 unsigned int i;
3254 int sum = 0;
a504d23a
LA		 3255
3256 for (i = 0; i < 8 * sizeof (mask); i++)
3257 {
3258 if (mask & 0x1)
3259 sum++;
3260 mask = (mask >> 1);
3261 }
3262 return sum;
3263#endif
3264}
3265
780a67af
NC		 3266/* Create an entry in an ARM ELF linker hash table. */
3267
3268static struct bfd_hash_entry *
57e8b36a 3269elf32_arm_link_hash_newfunc (struct bfd_hash_entry * entry,
99059e56
RM		 3270 struct bfd_hash_table * table,
3271 const char * string)
780a67af
NC		 3272{
3273 struct elf32_arm_link_hash_entry * ret =
3274 (struct elf32_arm_link_hash_entry *) entry;
3275
3276 /* Allocate the structure if it has not already been allocated by a
3277 subclass. */
906e58ca 3278 if (ret == NULL)
21d799b5 3279 ret = (struct elf32_arm_link_hash_entry *)
99059e56 3280 bfd_hash_allocate (table, sizeof (struct elf32_arm_link_hash_entry));
57e8b36a 3281 if (ret == NULL)
780a67af
NC		 3282 return (struct bfd_hash_entry *) ret;
3283
3284 /* Call the allocation method of the superclass. */
3285 ret = ((struct elf32_arm_link_hash_entry *)
3286 _bfd_elf_link_hash_newfunc ((struct bfd_hash_entry *) ret,
3287 table, string));
57e8b36a 3288 if (ret != NULL)
b7693d02 3289 {
0bdcacaf 3290 ret->dyn_relocs = NULL;
ba93b8ac 3291 ret->tls_type = GOT_UNKNOWN;
0855e32b 3292 ret->tlsdesc_got = (bfd_vma) -1;
34e77a92
RS		 3293 ret->plt.thumb_refcount = 0;
3294 ret->plt.maybe_thumb_refcount = 0;
3295 ret->plt.noncall_refcount = 0;
3296 ret->plt.got_offset = -1;
3297 ret->is_iplt = FALSE;
a4fd1a8e 3298 ret->export_glue = NULL;
906e58ca
NC		 3299
3300 ret->stub_cache = NULL;
b7693d02 3301 }
780a67af
NC		 3302
3303 return (struct bfd_hash_entry *) ret;
3304}
3305
34e77a92
RS		 3306/* Ensure that we have allocated bookkeeping structures for ABFD's local
3307 symbols. */
3308
3309static bfd_boolean
3310elf32_arm_allocate_local_sym_info (bfd *abfd)
3311{
3312 if (elf_local_got_refcounts (abfd) == NULL)
3313 {
3314 bfd_size_type num_syms;
3315 bfd_size_type size;
3316 char *data;
3317
3318 num_syms = elf_tdata (abfd)->symtab_hdr.sh_info;
3319 size = num_syms * (sizeof (bfd_signed_vma)
3320 + sizeof (struct arm_local_iplt_info *)
3321 + sizeof (bfd_vma)
3322 + sizeof (char));
3323 data = bfd_zalloc (abfd, size);
3324 if (data == NULL)
3325 return FALSE;
3326
3327 elf_local_got_refcounts (abfd) = (bfd_signed_vma *) data;
3328 data += num_syms * sizeof (bfd_signed_vma);
3329
3330 elf32_arm_local_iplt (abfd) = (struct arm_local_iplt_info **) data;
3331 data += num_syms * sizeof (struct arm_local_iplt_info *);
3332
3333 elf32_arm_local_tlsdesc_gotent (abfd) = (bfd_vma *) data;
3334 data += num_syms * sizeof (bfd_vma);
3335
3336 elf32_arm_local_got_tls_type (abfd) = data;
3337 }
3338 return TRUE;
3339}
3340
3341/* Return the .iplt information for local symbol R_SYMNDX, which belongs
3342 to input bfd ABFD. Create the information if it doesn't already exist.
3343 Return null if an allocation fails. */
3344
3345static struct arm_local_iplt_info *
3346elf32_arm_create_local_iplt (bfd *abfd, unsigned long r_symndx)
3347{
3348 struct arm_local_iplt_info **ptr;
3349
3350 if (!elf32_arm_allocate_local_sym_info (abfd))
3351 return NULL;
3352
3353 BFD_ASSERT (r_symndx < elf_tdata (abfd)->symtab_hdr.sh_info);
3354 ptr = &elf32_arm_local_iplt (abfd)[r_symndx];
3355 if (*ptr == NULL)
3356 *ptr = bfd_zalloc (abfd, sizeof (**ptr));
3357 return *ptr;
3358}
3359
3360/* Try to obtain PLT information for the symbol with index R_SYMNDX
3361 in ABFD's symbol table. If the symbol is global, H points to its
3362 hash table entry, otherwise H is null.
3363
3364 Return true if the symbol does have PLT information. When returning
3365 true, point *ROOT_PLT at the target-independent reference count/offset
3366 union and *ARM_PLT at the ARM-specific information. */
3367
3368static bfd_boolean
4ba2ef8f
TP		 3369elf32_arm_get_plt_info (bfd *abfd, struct elf32_arm_link_hash_table *globals,
3370 struct elf32_arm_link_hash_entry *h,
34e77a92
RS		 3371 unsigned long r_symndx, union gotplt_union **root_plt,
3372 struct arm_plt_info **arm_plt)
3373{
3374 struct arm_local_iplt_info *local_iplt;
3375
4ba2ef8f
TP		 3376 if (globals->root.splt == NULL && globals->root.iplt == NULL)
3377 return FALSE;
3378
34e77a92
RS		 3379 if (h != NULL)
3380 {
3381 *root_plt = &h->root.plt;
3382 *arm_plt = &h->plt;
3383 return TRUE;
3384 }
3385
3386 if (elf32_arm_local_iplt (abfd) == NULL)
3387 return FALSE;
3388
3389 local_iplt = elf32_arm_local_iplt (abfd)[r_symndx];
3390 if (local_iplt == NULL)
3391 return FALSE;
3392
3393 *root_plt = &local_iplt->root;
3394 *arm_plt = &local_iplt->arm;
3395 return TRUE;
3396}
3397
3398/* Return true if the PLT described by ARM_PLT requires a Thumb stub
3399 before it. */
3400
3401static bfd_boolean
3402elf32_arm_plt_needs_thumb_stub_p (struct bfd_link_info *info,
3403 struct arm_plt_info *arm_plt)
3404{
3405 struct elf32_arm_link_hash_table *htab;
3406
3407 htab = elf32_arm_hash_table (info);
3408 return (arm_plt->thumb_refcount != 0
3409 || (!htab->use_blx && arm_plt->maybe_thumb_refcount != 0));
3410}
3411
3412/* Return a pointer to the head of the dynamic reloc list that should
3413 be used for local symbol ISYM, which is symbol number R_SYMNDX in
3414 ABFD's symbol table. Return null if an error occurs. */
3415
3416static struct elf_dyn_relocs **
3417elf32_arm_get_local_dynreloc_list (bfd *abfd, unsigned long r_symndx,
3418 Elf_Internal_Sym *isym)
3419{
3420 if (ELF32_ST_TYPE (isym->st_info) == STT_GNU_IFUNC)
3421 {
3422 struct arm_local_iplt_info *local_iplt;
3423
3424 local_iplt = elf32_arm_create_local_iplt (abfd, r_symndx);
3425 if (local_iplt == NULL)
3426 return NULL;
3427 return &local_iplt->dyn_relocs;
3428 }
3429 else
3430 {
3431 /* Track dynamic relocs needed for local syms too.
3432 We really need local syms available to do this
3433 easily. Oh well. */
3434 asection *s;
3435 void *vpp;
3436
3437 s = bfd_section_from_elf_index (abfd, isym->st_shndx);
3438 if (s == NULL)
3439 abort ();
3440
3441 vpp = &elf_section_data (s)->local_dynrel;
3442 return (struct elf_dyn_relocs **) vpp;
3443 }
3444}
3445
906e58ca
NC		 3446/* Initialize an entry in the stub hash table. */
3447
3448static struct bfd_hash_entry *
3449stub_hash_newfunc (struct bfd_hash_entry *entry,
3450 struct bfd_hash_table *table,
3451 const char *string)
3452{
3453 /* Allocate the structure if it has not already been allocated by a
3454 subclass. */
3455 if (entry == NULL)
3456 {
21d799b5 3457 entry = (struct bfd_hash_entry *)
99059e56 3458 bfd_hash_allocate (table, sizeof (struct elf32_arm_stub_hash_entry));
906e58ca
NC		 3459 if (entry == NULL)
3460 return entry;
3461 }
3462
3463 /* Call the allocation method of the superclass. */
3464 entry = bfd_hash_newfunc (entry, table, string);
3465 if (entry != NULL)
3466 {
3467 struct elf32_arm_stub_hash_entry *eh;
3468
3469 /* Initialize the local fields. */
3470 eh = (struct elf32_arm_stub_hash_entry *) entry;
3471 eh->stub_sec = NULL;
0955507f 3472 eh->stub_offset = (bfd_vma) -1;
8d9d9490 3473 eh->source_value = 0;
906e58ca
NC		 3474 eh->target_value = 0;
3475 eh->target_section = NULL;
cedfb179 3476 eh->orig_insn = 0;
906e58ca 3477 eh->stub_type = arm_stub_none;
461a49ca
DJ		 3478 eh->stub_size = 0;
3479 eh->stub_template = NULL;
0955507f 3480 eh->stub_template_size = -1;
906e58ca
NC		 3481 eh->h = NULL;
3482 eh->id_sec = NULL;
d8d2f433 3483 eh->output_name = NULL;
906e58ca
NC		 3484 }
3485
3486 return entry;
3487}
3488
00a97672 3489/* Create .got, .gotplt, and .rel(a).got sections in DYNOBJ, and set up
5e681ec4
PB		 3490 shortcuts to them in our hash table. */
3491
3492static bfd_boolean
57e8b36a 3493create_got_section (bfd *dynobj, struct bfd_link_info *info)
5e681ec4
PB		 3494{
3495 struct elf32_arm_link_hash_table *htab;
3496
e5a52504 3497 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 3498 if (htab == NULL)
3499 return FALSE;
3500
e5a52504
MM		 3501 /* BPABI objects never have a GOT, or associated sections. */
3502 if (htab->symbian_p)
3503 return TRUE;
3504
5e681ec4
PB		 3505 if (! _bfd_elf_create_got_section (dynobj, info))
3506 return FALSE;
3507
5e681ec4
PB		 3508 return TRUE;
3509}
3510
34e77a92
RS		 3511/* Create the .iplt, .rel(a).iplt and .igot.plt sections. */
3512
3513static bfd_boolean
3514create_ifunc_sections (struct bfd_link_info *info)
3515{
3516 struct elf32_arm_link_hash_table *htab;
3517 const struct elf_backend_data *bed;
3518 bfd *dynobj;
3519 asection *s;
3520 flagword flags;
b38cadfb 3521
34e77a92
RS		 3522 htab = elf32_arm_hash_table (info);
3523 dynobj = htab->root.dynobj;
3524 bed = get_elf_backend_data (dynobj);
3525 flags = bed->dynamic_sec_flags;
3526
3527 if (htab->root.iplt == NULL)
3528 {
3d4d4302
AM		 3529 s = bfd_make_section_anyway_with_flags (dynobj, ".iplt",
3530 flags | SEC_READONLY | SEC_CODE);
34e77a92 3531 if (s == NULL
a0f49396 3532 || !bfd_set_section_alignment (dynobj, s, bed->plt_alignment))
34e77a92
RS		 3533 return FALSE;
3534 htab->root.iplt = s;
3535 }
3536
3537 if (htab->root.irelplt == NULL)
3538 {
3d4d4302
AM		 3539 s = bfd_make_section_anyway_with_flags (dynobj,
3540 RELOC_SECTION (htab, ".iplt"),
3541 flags | SEC_READONLY);
34e77a92 3542 if (s == NULL
a0f49396 3543 || !bfd_set_section_alignment (dynobj, s, bed->s->log_file_align))
34e77a92
RS		 3544 return FALSE;
3545 htab->root.irelplt = s;
3546 }
3547
3548 if (htab->root.igotplt == NULL)
3549 {
3d4d4302 3550 s = bfd_make_section_anyway_with_flags (dynobj, ".igot.plt", flags);
34e77a92
RS		 3551 if (s == NULL
3552 || !bfd_set_section_alignment (dynobj, s, bed->s->log_file_align))
3553 return FALSE;
3554 htab->root.igotplt = s;
3555 }
3556 return TRUE;
3557}
3558
eed94f8f
NC		 3559/* Determine if we're dealing with a Thumb only architecture. */
3560
3561static bfd_boolean
3562using_thumb_only (struct elf32_arm_link_hash_table *globals)
3563{
2fd158eb
TP		 3564 int arch;
3565 int profile = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC,
3566 Tag_CPU_arch_profile);
eed94f8f 3567
2fd158eb
TP		 3568 if (profile)
3569 return profile == 'M';
eed94f8f 3570
2fd158eb 3571 arch = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC, Tag_CPU_arch);
eed94f8f 3572
60a019a0
TP		 3573 /* Force return logic to be reviewed for each new architecture. */
3574 BFD_ASSERT (arch <= TAG_CPU_ARCH_V8
3575 || arch == TAG_CPU_ARCH_V8M_BASE
3576 || arch == TAG_CPU_ARCH_V8M_MAIN);
3577
2fd158eb
TP		 3578 if (arch == TAG_CPU_ARCH_V6_M
3579 || arch == TAG_CPU_ARCH_V6S_M
3580 || arch == TAG_CPU_ARCH_V7E_M
3581 || arch == TAG_CPU_ARCH_V8M_BASE
3582 || arch == TAG_CPU_ARCH_V8M_MAIN)
3583 return TRUE;
eed94f8f 3584
2fd158eb 3585 return FALSE;
eed94f8f
NC		 3586}
3587
3588/* Determine if we're dealing with a Thumb-2 object. */
3589
3590static bfd_boolean
3591using_thumb2 (struct elf32_arm_link_hash_table *globals)
3592{
60a019a0
TP		 3593 int arch;
3594 int thumb_isa = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC,
3595 Tag_THUMB_ISA_use);
3596
3597 if (thumb_isa)
3598 return thumb_isa == 2;
3599
3600 arch = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC, Tag_CPU_arch);
3601
3602 /* Force return logic to be reviewed for each new architecture. */
3603 BFD_ASSERT (arch <= TAG_CPU_ARCH_V8
3604 || arch == TAG_CPU_ARCH_V8M_BASE
3605 || arch == TAG_CPU_ARCH_V8M_MAIN);
3606
3607 return (arch == TAG_CPU_ARCH_V6T2
3608 || arch == TAG_CPU_ARCH_V7
3609 || arch == TAG_CPU_ARCH_V7E_M
3610 || arch == TAG_CPU_ARCH_V8
3611 || arch == TAG_CPU_ARCH_V8M_MAIN);
eed94f8f
NC		 3612}
3613
5e866f5a
TP		 3614/* Determine whether Thumb-2 BL instruction is available. */
3615
3616static bfd_boolean
3617using_thumb2_bl (struct elf32_arm_link_hash_table *globals)
3618{
3619 int arch =
3620 bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC, Tag_CPU_arch);
3621
3622 /* Force return logic to be reviewed for each new architecture. */
3623 BFD_ASSERT (arch <= TAG_CPU_ARCH_V8
3624 || arch == TAG_CPU_ARCH_V8M_BASE
3625 || arch == TAG_CPU_ARCH_V8M_MAIN);
3626
3627 /* Architecture was introduced after ARMv6T2 (eg. ARMv6-M). */
3628 return (arch == TAG_CPU_ARCH_V6T2
3629 || arch >= TAG_CPU_ARCH_V7);
3630}
3631
00a97672
RS		 3632/* Create .plt, .rel(a).plt, .got, .got.plt, .rel(a).got, .dynbss, and
3633 .rel(a).bss sections in DYNOBJ, and set up shortcuts to them in our
5e681ec4
PB		 3634 hash table. */
3635
3636static bfd_boolean
57e8b36a 3637elf32_arm_create_dynamic_sections (bfd *dynobj, struct bfd_link_info *info)
5e681ec4
PB		 3638{
3639 struct elf32_arm_link_hash_table *htab;
3640
3641 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 3642 if (htab == NULL)
3643 return FALSE;
3644
362d30a1 3645 if (!htab->root.sgot && !create_got_section (dynobj, info))
5e681ec4
PB		 3646 return FALSE;
3647
3648 if (!_bfd_elf_create_dynamic_sections (dynobj, info))
3649 return FALSE;
3650
3d4d4302 3651 htab->sdynbss = bfd_get_linker_section (dynobj, ".dynbss");
0e1862bb 3652 if (!bfd_link_pic (info))
3d4d4302
AM		 3653 htab->srelbss = bfd_get_linker_section (dynobj,
3654 RELOC_SECTION (htab, ".bss"));
00a97672
RS		 3655
3656 if (htab->vxworks_p)
3657 {
3658 if (!elf_vxworks_create_dynamic_sections (dynobj, info, &htab->srelplt2))
3659 return FALSE;
3660
0e1862bb 3661 if (bfd_link_pic (info))
00a97672
RS		 3662 {
3663 htab->plt_header_size = 0;
3664 htab->plt_entry_size
3665 = 4 * ARRAY_SIZE (elf32_arm_vxworks_shared_plt_entry);
3666 }
3667 else
3668 {
3669 htab->plt_header_size
3670 = 4 * ARRAY_SIZE (elf32_arm_vxworks_exec_plt0_entry);
3671 htab->plt_entry_size
3672 = 4 * ARRAY_SIZE (elf32_arm_vxworks_exec_plt_entry);
3673 }
aebf9be7
NC		 3674
3675 if (elf_elfheader (dynobj))
3676 elf_elfheader (dynobj)->e_ident[EI_CLASS] = ELFCLASS32;
00a97672 3677 }
eed94f8f
NC		 3678 else
3679 {
3680 /* PR ld/16017
3681 Test for thumb only architectures. Note - we cannot just call
3682 using_thumb_only() as the attributes in the output bfd have not been
3683 initialised at this point, so instead we use the input bfd. */
3684 bfd * saved_obfd = htab->obfd;
3685
3686 htab->obfd = dynobj;
3687 if (using_thumb_only (htab))
3688 {
3689 htab->plt_header_size = 4 * ARRAY_SIZE (elf32_thumb2_plt0_entry);
3690 htab->plt_entry_size = 4 * ARRAY_SIZE (elf32_thumb2_plt_entry);
3691 }
3692 htab->obfd = saved_obfd;
3693 }
5e681ec4 3694
362d30a1
RS		 3695 if (!htab->root.splt
3696 || !htab->root.srelplt
e5a52504 3697 || !htab->sdynbss
0e1862bb 3698 || (!bfd_link_pic (info) && !htab->srelbss))
5e681ec4
PB		 3699 abort ();
3700
3701 return TRUE;
3702}
3703
906e58ca
NC		 3704/* Copy the extra info we tack onto an elf_link_hash_entry. */
3705
3706static void
3707elf32_arm_copy_indirect_symbol (struct bfd_link_info *info,
3708 struct elf_link_hash_entry *dir,
3709 struct elf_link_hash_entry *ind)
3710{
3711 struct elf32_arm_link_hash_entry *edir, *eind;
3712
3713 edir = (struct elf32_arm_link_hash_entry *) dir;
3714 eind = (struct elf32_arm_link_hash_entry *) ind;
3715
0bdcacaf 3716 if (eind->dyn_relocs != NULL)
906e58ca 3717 {
0bdcacaf 3718 if (edir->dyn_relocs != NULL)
906e58ca 3719 {
0bdcacaf
RS		 3720 struct elf_dyn_relocs **pp;
3721 struct elf_dyn_relocs *p;
906e58ca
NC		 3722
3723 /* Add reloc counts against the indirect sym to the direct sym
3724 list. Merge any entries against the same section. */
0bdcacaf 3725 for (pp = &eind->dyn_relocs; (p = *pp) != NULL; )
906e58ca 3726 {
0bdcacaf 3727 struct elf_dyn_relocs *q;
906e58ca 3728
0bdcacaf
RS		 3729 for (q = edir->dyn_relocs; q != NULL; q = q->next)
3730 if (q->sec == p->sec)
906e58ca
NC		 3731 {
3732 q->pc_count += p->pc_count;
3733 q->count += p->count;
3734 *pp = p->next;
3735 break;
3736 }
3737 if (q == NULL)
3738 pp = &p->next;
3739 }
0bdcacaf 3740 *pp = edir->dyn_relocs;
906e58ca
NC		 3741 }
3742
0bdcacaf
RS		 3743 edir->dyn_relocs = eind->dyn_relocs;
3744 eind->dyn_relocs = NULL;
906e58ca
NC		 3745 }
3746
3747 if (ind->root.type == bfd_link_hash_indirect)
3748 {
3749 /* Copy over PLT info. */
34e77a92
RS		 3750 edir->plt.thumb_refcount += eind->plt.thumb_refcount;
3751 eind->plt.thumb_refcount = 0;
3752 edir->plt.maybe_thumb_refcount += eind->plt.maybe_thumb_refcount;
3753 eind->plt.maybe_thumb_refcount = 0;
3754 edir->plt.noncall_refcount += eind->plt.noncall_refcount;
3755 eind->plt.noncall_refcount = 0;
3756
3757 /* We should only allocate a function to .iplt once the final
3758 symbol information is known. */
3759 BFD_ASSERT (!eind->is_iplt);
906e58ca
NC		 3760
3761 if (dir->got.refcount <= 0)
3762 {
3763 edir->tls_type = eind->tls_type;
3764 eind->tls_type = GOT_UNKNOWN;
3765 }
3766 }
3767
3768 _bfd_elf_link_hash_copy_indirect (info, dir, ind);
3769}
3770
68faa637
AM		 3771/* Destroy an ARM elf linker hash table. */
3772
3773static void
d495ab0d 3774elf32_arm_link_hash_table_free (bfd *obfd)
68faa637
AM		 3775{
3776 struct elf32_arm_link_hash_table *ret
d495ab0d 3777 = (struct elf32_arm_link_hash_table *) obfd->link.hash;
68faa637
AM		 3778
3779 bfd_hash_table_free (&ret->stub_hash_table);
d495ab0d 3780 _bfd_elf_link_hash_table_free (obfd);
68faa637
AM		 3781}
3782
906e58ca
NC		 3783/* Create an ARM elf linker hash table. */
3784
3785static struct bfd_link_hash_table *
3786elf32_arm_link_hash_table_create (bfd *abfd)
3787{
3788 struct elf32_arm_link_hash_table *ret;
3789 bfd_size_type amt = sizeof (struct elf32_arm_link_hash_table);
3790
7bf52ea2 3791 ret = (struct elf32_arm_link_hash_table *) bfd_zmalloc (amt);
906e58ca
NC		 3792 if (ret == NULL)
3793 return NULL;
3794
3795 if (!_bfd_elf_link_hash_table_init (& ret->root, abfd,
3796 elf32_arm_link_hash_newfunc,
4dfe6ac6
NC		 3797 sizeof (struct elf32_arm_link_hash_entry),
3798 ARM_ELF_DATA))
906e58ca
NC		 3799 {
3800 free (ret);
3801 return NULL;
3802 }
3803
906e58ca 3804 ret->vfp11_fix = BFD_ARM_VFP11_FIX_NONE;
a504d23a 3805 ret->stm32l4xx_fix = BFD_ARM_STM32L4XX_FIX_NONE;
906e58ca
NC		 3806#ifdef FOUR_WORD_PLT
3807 ret->plt_header_size = 16;
3808 ret->plt_entry_size = 16;
3809#else
3810 ret->plt_header_size = 20;
1db37fe6 3811 ret->plt_entry_size = elf32_arm_use_long_plt_entry ? 16 : 12;
906e58ca 3812#endif
906e58ca 3813 ret->use_rel = 1;
906e58ca 3814 ret->obfd = abfd;
906e58ca
NC		 3815
3816 if (!bfd_hash_table_init (&ret->stub_hash_table, stub_hash_newfunc,
3817 sizeof (struct elf32_arm_stub_hash_entry)))
3818 {
d495ab0d 3819 _bfd_elf_link_hash_table_free (abfd);
906e58ca
NC		 3820 return NULL;
3821 }
d495ab0d 3822 ret->root.root.hash_table_free = elf32_arm_link_hash_table_free;
906e58ca
NC		 3823
3824 return &ret->root.root;
3825}
3826
cd1dac3d
DG		 3827/* Determine what kind of NOPs are available. */
3828
3829static bfd_boolean
3830arch_has_arm_nop (struct elf32_arm_link_hash_table *globals)
3831{
3832 const int arch = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC,
3833 Tag_CPU_arch);
cd1dac3d 3834
60a019a0
TP		 3835 /* Force return logic to be reviewed for each new architecture. */
3836 BFD_ASSERT (arch <= TAG_CPU_ARCH_V8
3837 || arch == TAG_CPU_ARCH_V8M_BASE
3838 || arch == TAG_CPU_ARCH_V8M_MAIN);
3839
3840 return (arch == TAG_CPU_ARCH_V6T2
3841 || arch == TAG_CPU_ARCH_V6K
3842 || arch == TAG_CPU_ARCH_V7
3843 || arch == TAG_CPU_ARCH_V8);
cd1dac3d
DG		 3844}
3845
f4ac8484
DJ		 3846static bfd_boolean
3847arm_stub_is_thumb (enum elf32_arm_stub_type stub_type)
3848{
3849 switch (stub_type)
3850 {
fea2b4d6 3851 case arm_stub_long_branch_thumb_only:
80c135e5 3852 case arm_stub_long_branch_thumb2_only:
d5a67c02 3853 case arm_stub_long_branch_thumb2_only_pure:
fea2b4d6
CL		 3854 case arm_stub_long_branch_v4t_thumb_arm:
3855 case arm_stub_short_branch_v4t_thumb_arm:
ebe24dd4 3856 case arm_stub_long_branch_v4t_thumb_arm_pic:
12352d3f 3857 case arm_stub_long_branch_v4t_thumb_tls_pic:
ebe24dd4 3858 case arm_stub_long_branch_thumb_only_pic:
4ba2ef8f 3859 case arm_stub_cmse_branch_thumb_only:
f4ac8484
DJ		 3860 return TRUE;
3861 case arm_stub_none:
3862 BFD_FAIL ();
3863 return FALSE;
3864 break;
3865 default:
3866 return FALSE;
3867 }
3868}
3869
906e58ca
NC		 3870/* Determine the type of stub needed, if any, for a call. */
3871
3872static enum elf32_arm_stub_type
3873arm_type_of_stub (struct bfd_link_info *info,
3874 asection *input_sec,
3875 const Elf_Internal_Rela *rel,
34e77a92 3876 unsigned char st_type,
35fc36a8 3877 enum arm_st_branch_type *actual_branch_type,
906e58ca 3878 struct elf32_arm_link_hash_entry *hash,
c820be07
NC		 3879 bfd_vma destination,
3880 asection *sym_sec,
3881 bfd *input_bfd,
3882 const char *name)
906e58ca
NC		 3883{
3884 bfd_vma location;
3885 bfd_signed_vma branch_offset;
3886 unsigned int r_type;
3887 struct elf32_arm_link_hash_table * globals;
5e866f5a 3888 bfd_boolean thumb2, thumb2_bl, thumb_only;
906e58ca 3889 enum elf32_arm_stub_type stub_type = arm_stub_none;
5fa9e92f 3890 int use_plt = 0;
35fc36a8 3891 enum arm_st_branch_type branch_type = *actual_branch_type;
34e77a92
RS		 3892 union gotplt_union *root_plt;
3893 struct arm_plt_info *arm_plt;
d5a67c02
AV		 3894 int arch;
3895 int thumb2_movw;
906e58ca 3896
35fc36a8 3897 if (branch_type == ST_BRANCH_LONG)
da5938a2
NC		 3898 return stub_type;
3899
906e58ca 3900 globals = elf32_arm_hash_table (info);
4dfe6ac6
NC		 3901 if (globals == NULL)
3902 return stub_type;
906e58ca
NC		 3903
3904 thumb_only = using_thumb_only (globals);
906e58ca 3905 thumb2 = using_thumb2 (globals);
5e866f5a 3906 thumb2_bl = using_thumb2_bl (globals);
906e58ca 3907
d5a67c02
AV		 3908 arch = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC, Tag_CPU_arch);
3909
3910 /* True for architectures that implement the thumb2 movw instruction. */
3911 thumb2_movw = thumb2 || (arch == TAG_CPU_ARCH_V8M_BASE);
3912
906e58ca
NC		 3913 /* Determine where the call point is. */
3914 location = (input_sec->output_offset
3915 + input_sec->output_section->vma
3916 + rel->r_offset);
3917
906e58ca
NC		 3918 r_type = ELF32_R_TYPE (rel->r_info);
3919
39f21624
NC		 3920 /* ST_BRANCH_TO_ARM is nonsense to thumb-only targets when we
3921 are considering a function call relocation. */
c5423981
TG		 3922 if (thumb_only && (r_type == R_ARM_THM_CALL || r_type == R_ARM_THM_JUMP24
3923 || r_type == R_ARM_THM_JUMP19)
39f21624
NC		 3924 && branch_type == ST_BRANCH_TO_ARM)
3925 branch_type = ST_BRANCH_TO_THUMB;
3926
34e77a92
RS		 3927 /* For TLS call relocs, it is the caller's responsibility to provide
3928 the address of the appropriate trampoline. */
3929 if (r_type != R_ARM_TLS_CALL
3930 && r_type != R_ARM_THM_TLS_CALL
4ba2ef8f
TP		 3931 && elf32_arm_get_plt_info (input_bfd, globals, hash,
3932 ELF32_R_SYM (rel->r_info), &root_plt,
3933 &arm_plt)
34e77a92 3934 && root_plt->offset != (bfd_vma) -1)
5fa9e92f 3935 {
34e77a92 3936 asection *splt;
fe33d2fa 3937
34e77a92
RS		 3938 if (hash == NULL || hash->is_iplt)
3939 splt = globals->root.iplt;
3940 else
3941 splt = globals->root.splt;
3942 if (splt != NULL)
b38cadfb 3943 {
34e77a92
RS		 3944 use_plt = 1;
3945
3946 /* Note when dealing with PLT entries: the main PLT stub is in
3947 ARM mode, so if the branch is in Thumb mode, another
3948 Thumb->ARM stub will be inserted later just before the ARM
2df2751d
CL		 3949 PLT stub. If a long branch stub is needed, we'll add a
3950 Thumb->Arm one and branch directly to the ARM PLT entry.
3951 Here, we have to check if a pre-PLT Thumb->ARM stub
3952 is needed and if it will be close enough. */
34e77a92
RS		 3953
3954 destination = (splt->output_section->vma
3955 + splt->output_offset
3956 + root_plt->offset);
3957 st_type = STT_FUNC;
2df2751d
CL		 3958
3959 /* Thumb branch/call to PLT: it can become a branch to ARM
3960 or to Thumb. We must perform the same checks and
3961 corrections as in elf32_arm_final_link_relocate. */
3962 if ((r_type == R_ARM_THM_CALL)
3963 || (r_type == R_ARM_THM_JUMP24))
3964 {
3965 if (globals->use_blx
3966 && r_type == R_ARM_THM_CALL
3967 && !thumb_only)
3968 {
3969 /* If the Thumb BLX instruction is available, convert
3970 the BL to a BLX instruction to call the ARM-mode
3971 PLT entry. */
3972 branch_type = ST_BRANCH_TO_ARM;
3973 }
3974 else
3975 {
3976 if (!thumb_only)
3977 /* Target the Thumb stub before the ARM PLT entry. */
3978 destination -= PLT_THUMB_STUB_SIZE;
3979 branch_type = ST_BRANCH_TO_THUMB;
3980 }
3981 }
3982 else
3983 {
3984 branch_type = ST_BRANCH_TO_ARM;
3985 }
34e77a92 3986 }
5fa9e92f 3987 }
34e77a92
RS		 3988 /* Calls to STT_GNU_IFUNC symbols should go through a PLT. */
3989 BFD_ASSERT (st_type != STT_GNU_IFUNC);
906e58ca 3990
fe33d2fa
CL		 3991 branch_offset = (bfd_signed_vma)(destination - location);
3992
0855e32b 3993 if (r_type == R_ARM_THM_CALL || r_type == R_ARM_THM_JUMP24
c5423981 3994 || r_type == R_ARM_THM_TLS_CALL || r_type == R_ARM_THM_JUMP19)
906e58ca 3995 {
5fa9e92f
CL		 3996 /* Handle cases where:
3997 - this call goes too far (different Thumb/Thumb2 max
99059e56 3998 distance)
155d87d7 3999 - it's a Thumb->Arm call and blx is not available, or it's a
99059e56
RM		 4000 Thumb->Arm branch (not bl). A stub is needed in this case,
4001 but only if this call is not through a PLT entry. Indeed,
695344c0 4002 PLT stubs handle mode switching already. */
5e866f5a 4003 if ((!thumb2_bl
906e58ca
NC		 4004 && (branch_offset > THM_MAX_FWD_BRANCH_OFFSET
4005 || (branch_offset < THM_MAX_BWD_BRANCH_OFFSET)))
5e866f5a 4006 || (thumb2_bl
906e58ca
NC		 4007 && (branch_offset > THM2_MAX_FWD_BRANCH_OFFSET
4008 || (branch_offset < THM2_MAX_BWD_BRANCH_OFFSET)))
c5423981
TG		 4009 || (thumb2
4010 && (branch_offset > THM2_MAX_FWD_COND_BRANCH_OFFSET
4011 || (branch_offset < THM2_MAX_BWD_COND_BRANCH_OFFSET))
4012 && (r_type == R_ARM_THM_JUMP19))
35fc36a8 4013 || (branch_type == ST_BRANCH_TO_ARM
0855e32b
NS		 4014 && (((r_type == R_ARM_THM_CALL
4015 || r_type == R_ARM_THM_TLS_CALL) && !globals->use_blx)
c5423981
TG		 4016 || (r_type == R_ARM_THM_JUMP24)
4017 || (r_type == R_ARM_THM_JUMP19))
5fa9e92f 4018 && !use_plt))
906e58ca 4019 {
2df2751d
CL		 4020 /* If we need to insert a Thumb-Thumb long branch stub to a
4021 PLT, use one that branches directly to the ARM PLT
4022 stub. If we pretended we'd use the pre-PLT Thumb->ARM
4023 stub, undo this now. */
695344c0
NC		 4024 if ((branch_type == ST_BRANCH_TO_THUMB) && use_plt && !thumb_only)
4025 {
4026 branch_type = ST_BRANCH_TO_ARM;
4027 branch_offset += PLT_THUMB_STUB_SIZE;
4028 }
2df2751d 4029
35fc36a8 4030 if (branch_type == ST_BRANCH_TO_THUMB)
906e58ca
NC		 4031 {
4032 /* Thumb to thumb. */
4033 if (!thumb_only)
4034 {
d5a67c02 4035 if (input_sec->flags & SEC_ELF_PURECODE)
695344c0
NC		 4036 _bfd_error_handler (_("\
4037%B(%A): warning: long branch veneers used in section with SHF_ARM_PURECODE section \
4038attribute is only supported for M-profile targets that implement the movw instruction."),
4039 input_sec);
d5a67c02 4040
0e1862bb 4041 stub_type = (bfd_link_pic (info) | globals->pic_veneer)
c2b4a39d 4042 /* PIC stubs. */
155d87d7 4043 ? ((globals->use_blx
9553db3c 4044 && (r_type == R_ARM_THM_CALL))
155d87d7
CL		 4045 /* V5T and above. Stub starts with ARM code, so
4046 we must be able to switch mode before
4047 reaching it, which is only possible for 'bl'
4048 (ie R_ARM_THM_CALL relocation). */
cf3eccff 4049 ? arm_stub_long_branch_any_thumb_pic
ebe24dd4 4050 /* On V4T, use Thumb code only. */
d3626fb0 4051 : arm_stub_long_branch_v4t_thumb_thumb_pic)
c2b4a39d
CL		 4052
4053 /* non-PIC stubs. */
155d87d7 4054 : ((globals->use_blx
9553db3c 4055 && (r_type == R_ARM_THM_CALL))
c2b4a39d
CL		 4056 /* V5T and above. */
4057 ? arm_stub_long_branch_any_any
4058 /* V4T. */
d3626fb0 4059 : arm_stub_long_branch_v4t_thumb_thumb);
906e58ca
NC		 4060 }
4061 else
4062 {
d5a67c02
AV		 4063 if (thumb2_movw && (input_sec->flags & SEC_ELF_PURECODE))
4064 stub_type = arm_stub_long_branch_thumb2_only_pure;
4065 else
4066 {
4067 if (input_sec->flags & SEC_ELF_PURECODE)
695344c0
NC		 4068 _bfd_error_handler (_("\
4069%B(%A): warning: long branch veneers used in section with SHF_ARM_PURECODE section \
4070attribute is only supported for M-profile targets that implement the movw instruction."),
4071 input_sec);
d5a67c02
AV		 4072
4073 stub_type = (bfd_link_pic (info) | globals->pic_veneer)
4074 /* PIC stub. */
4075 ? arm_stub_long_branch_thumb_only_pic
4076 /* non-PIC stub. */
4077 : (thumb2 ? arm_stub_long_branch_thumb2_only
4078 : arm_stub_long_branch_thumb_only);
4079 }
906e58ca
NC		 4080 }
4081 }
4082 else
4083 {
d5a67c02 4084 if (input_sec->flags & SEC_ELF_PURECODE)
4eca0228
AM		 4085 _bfd_error_handler (_("%B(%s): warning: long branch "
4086 " veneers used in section with "
4087 "SHF_ARM_PURECODE section "
4088 "attribute is only supported"
4089 " for M-profile targets that "
4090 "implement the movw "
4091 "instruction."));
d5a67c02 4092
906e58ca 4093 /* Thumb to arm. */
c820be07
NC		 4094 if (sym_sec != NULL
4095 && sym_sec->owner != NULL
4096 && !INTERWORK_FLAG (sym_sec->owner))
4097 {
4eca0228 4098 _bfd_error_handler
c820be07
NC		 4099 (_("%B(%s): warning: interworking not enabled.\n"
4100 " first occurrence: %B: Thumb call to ARM"),
4101 sym_sec->owner, input_bfd, name);
4102 }
4103
0855e32b 4104 stub_type =
0e1862bb 4105 (bfd_link_pic (info) | globals->pic_veneer)
c2b4a39d 4106 /* PIC stubs. */
0855e32b 4107 ? (r_type == R_ARM_THM_TLS_CALL
6a631e86 4108 /* TLS PIC stubs. */
0855e32b
NS		 4109 ? (globals->use_blx ? arm_stub_long_branch_any_tls_pic
4110 : arm_stub_long_branch_v4t_thumb_tls_pic)
4111 : ((globals->use_blx && r_type == R_ARM_THM_CALL)
4112 /* V5T PIC and above. */
4113 ? arm_stub_long_branch_any_arm_pic
4114 /* V4T PIC stub. */
4115 : arm_stub_long_branch_v4t_thumb_arm_pic))
c2b4a39d
CL		 4116
4117 /* non-PIC stubs. */
0855e32b 4118 : ((globals->use_blx && r_type == R_ARM_THM_CALL)
c2b4a39d
CL		 4119 /* V5T and above. */
4120 ? arm_stub_long_branch_any_any
4121 /* V4T. */
4122 : arm_stub_long_branch_v4t_thumb_arm);
c820be07
NC		 4123
4124 /* Handle v4t short branches. */
fea2b4d6 4125 if ((stub_type == arm_stub_long_branch_v4t_thumb_arm)
c820be07
NC		 4126 && (branch_offset <= THM_MAX_FWD_BRANCH_OFFSET)
4127 && (branch_offset >= THM_MAX_BWD_BRANCH_OFFSET))
fea2b4d6 4128 stub_type = arm_stub_short_branch_v4t_thumb_arm;
906e58ca
NC		 4129 }
4130 }
4131 }
fe33d2fa
CL		 4132 else if (r_type == R_ARM_CALL
4133 || r_type == R_ARM_JUMP24
0855e32b
NS		 4134 || r_type == R_ARM_PLT32
4135 || r_type == R_ARM_TLS_CALL)
906e58ca 4136 {
d5a67c02 4137 if (input_sec->flags & SEC_ELF_PURECODE)
4eca0228
AM		 4138 _bfd_error_handler (_("%B(%s): warning: long branch "
4139 " veneers used in section with "
4140 "SHF_ARM_PURECODE section "
4141 "attribute is only supported"
4142 " for M-profile targets that "
4143 "implement the movw "
4144 "instruction."));
35fc36a8 4145 if (branch_type == ST_BRANCH_TO_THUMB)
906e58ca
NC		 4146 {
4147 /* Arm to thumb. */
c820be07
NC		 4148
4149 if (sym_sec != NULL
4150 && sym_sec->owner != NULL
4151 && !INTERWORK_FLAG (sym_sec->owner))
4152 {
4eca0228 4153 _bfd_error_handler
c820be07 4154 (_("%B(%s): warning: interworking not enabled.\n"
c2b4a39d 4155 " first occurrence: %B: ARM call to Thumb"),
c820be07
NC		 4156 sym_sec->owner, input_bfd, name);
4157 }
4158
4159 /* We have an extra 2-bytes reach because of
4160 the mode change (bit 24 (H) of BLX encoding). */
4116d8d7
PB		 4161 if (branch_offset > (ARM_MAX_FWD_BRANCH_OFFSET + 2)
4162 || (branch_offset < ARM_MAX_BWD_BRANCH_OFFSET)
0855e32b 4163 || (r_type == R_ARM_CALL && !globals->use_blx)
4116d8d7
PB		 4164 || (r_type == R_ARM_JUMP24)
4165 || (r_type == R_ARM_PLT32))
906e58ca 4166 {
0e1862bb 4167 stub_type = (bfd_link_pic (info) | globals->pic_veneer)
c2b4a39d 4168 /* PIC stubs. */
ebe24dd4
CL		 4169 ? ((globals->use_blx)
4170 /* V5T and above. */
4171 ? arm_stub_long_branch_any_thumb_pic
4172 /* V4T stub. */
4173 : arm_stub_long_branch_v4t_arm_thumb_pic)
4174
c2b4a39d
CL		 4175 /* non-PIC stubs. */
4176 : ((globals->use_blx)
4177 /* V5T and above. */
4178 ? arm_stub_long_branch_any_any
4179 /* V4T. */
4180 : arm_stub_long_branch_v4t_arm_thumb);
906e58ca
NC		 4181 }
4182 }
4183 else
4184 {
4185 /* Arm to arm. */
4186 if (branch_offset > ARM_MAX_FWD_BRANCH_OFFSET
4187 || (branch_offset < ARM_MAX_BWD_BRANCH_OFFSET))
4188 {
0855e32b 4189 stub_type =
0e1862bb 4190 (bfd_link_pic (info) | globals->pic_veneer)
c2b4a39d 4191 /* PIC stubs. */
0855e32b 4192 ? (r_type == R_ARM_TLS_CALL
6a631e86 4193 /* TLS PIC Stub. */
0855e32b 4194 ? arm_stub_long_branch_any_tls_pic
7a89b94e
NC		 4195 : (globals->nacl_p
4196 ? arm_stub_long_branch_arm_nacl_pic
4197 : arm_stub_long_branch_any_arm_pic))
c2b4a39d 4198 /* non-PIC stubs. */
7a89b94e
NC		 4199 : (globals->nacl_p
4200 ? arm_stub_long_branch_arm_nacl
4201 : arm_stub_long_branch_any_any);
906e58ca
NC		 4202 }
4203 }
4204 }
4205
fe33d2fa
CL		 4206 /* If a stub is needed, record the actual destination type. */
4207 if (stub_type != arm_stub_none)
35fc36a8 4208 *actual_branch_type = branch_type;
fe33d2fa 4209
906e58ca
NC		 4210 return stub_type;
4211}
4212
4213/* Build a name for an entry in the stub hash table. */
4214
4215static char *
4216elf32_arm_stub_name (const asection *input_section,
4217 const asection *sym_sec,
4218 const struct elf32_arm_link_hash_entry *hash,
fe33d2fa
CL		 4219 const Elf_Internal_Rela *rel,
4220 enum elf32_arm_stub_type stub_type)
906e58ca
NC		 4221{
4222 char *stub_name;
4223 bfd_size_type len;
4224
4225 if (hash)
4226 {
fe33d2fa 4227 len = 8 + 1 + strlen (hash->root.root.root.string) + 1 + 8 + 1 + 2 + 1;
21d799b5 4228 stub_name = (char *) bfd_malloc (len);
906e58ca 4229 if (stub_name != NULL)
fe33d2fa 4230 sprintf (stub_name, "%08x_%s+%x_%d",
906e58ca
NC		 4231 input_section->id & 0xffffffff,
4232 hash->root.root.root.string,
fe33d2fa
CL		 4233 (int) rel->r_addend & 0xffffffff,
4234 (int) stub_type);
906e58ca
NC		 4235 }
4236 else
4237 {
fe33d2fa 4238 len = 8 + 1 + 8 + 1 + 8 + 1 + 8 + 1 + 2 + 1;
21d799b5 4239 stub_name = (char *) bfd_malloc (len);
906e58ca 4240 if (stub_name != NULL)
fe33d2fa 4241 sprintf (stub_name, "%08x_%x:%x+%x_%d",
906e58ca
NC		 4242 input_section->id & 0xffffffff,
4243 sym_sec->id & 0xffffffff,
0855e32b
NS		 4244 ELF32_R_TYPE (rel->r_info) == R_ARM_TLS_CALL
4245 || ELF32_R_TYPE (rel->r_info) == R_ARM_THM_TLS_CALL
4246 ? 0 : (int) ELF32_R_SYM (rel->r_info) & 0xffffffff,
fe33d2fa
CL		 4247 (int) rel->r_addend & 0xffffffff,
4248 (int) stub_type);
906e58ca
NC		 4249 }
4250
4251 return stub_name;
4252}
4253
4254/* Look up an entry in the stub hash. Stub entries are cached because
4255 creating the stub name takes a bit of time. */
4256
4257static struct elf32_arm_stub_hash_entry *
4258elf32_arm_get_stub_entry (const asection *input_section,
4259 const asection *sym_sec,
4260 struct elf_link_hash_entry *hash,
4261 const Elf_Internal_Rela *rel,
fe33d2fa
CL		 4262 struct elf32_arm_link_hash_table *htab,
4263 enum elf32_arm_stub_type stub_type)
906e58ca
NC		 4264{
4265 struct elf32_arm_stub_hash_entry *stub_entry;
4266 struct elf32_arm_link_hash_entry *h = (struct elf32_arm_link_hash_entry *) hash;
4267 const asection *id_sec;
4268
4269 if ((input_section->flags & SEC_CODE) == 0)
4270 return NULL;
4271
4272 /* If this input section is part of a group of sections sharing one
4273 stub section, then use the id of the first section in the group.
4274 Stub names need to include a section id, as there may well be
4275 more than one stub used to reach say, printf, and we need to
4276 distinguish between them. */
c2abbbeb 4277 BFD_ASSERT (input_section->id <= htab->top_id);
906e58ca
NC		 4278 id_sec = htab->stub_group[input_section->id].link_sec;
4279
4280 if (h != NULL && h->stub_cache != NULL
4281 && h->stub_cache->h == h
fe33d2fa
CL		 4282 && h->stub_cache->id_sec == id_sec
4283 && h->stub_cache->stub_type == stub_type)
906e58ca
NC		 4284 {
4285 stub_entry = h->stub_cache;
4286 }
4287 else
4288 {
4289 char *stub_name;
4290
fe33d2fa 4291 stub_name = elf32_arm_stub_name (id_sec, sym_sec, h, rel, stub_type);
906e58ca
NC		 4292 if (stub_name == NULL)
4293 return NULL;
4294
4295 stub_entry = arm_stub_hash_lookup (&htab->stub_hash_table,
4296 stub_name, FALSE, FALSE);
4297 if (h != NULL)
4298 h->stub_cache = stub_entry;
4299
4300 free (stub_name);
4301 }
4302
4303 return stub_entry;
4304}
4305
daa4adae
TP		 4306/* Whether veneers of type STUB_TYPE require to be in a dedicated output
4307 section. */
4308
4309static bfd_boolean
4310arm_dedicated_stub_output_section_required (enum elf32_arm_stub_type stub_type)
4311{
4312 if (stub_type >= max_stub_type)
4313 abort (); /* Should be unreachable. */
4314
4ba2ef8f
TP		 4315 switch (stub_type)
4316 {
4317 case arm_stub_cmse_branch_thumb_only:
4318 return TRUE;
4319
4320 default:
4321 return FALSE;
4322 }
4323
4324 abort (); /* Should be unreachable. */
daa4adae
TP		 4325}
4326
4327/* Required alignment (as a power of 2) for the dedicated section holding
4328 veneers of type STUB_TYPE, or 0 if veneers of this type are interspersed
4329 with input sections. */
4330
4331static int
4332arm_dedicated_stub_output_section_required_alignment
4333 (enum elf32_arm_stub_type stub_type)
4334{
4335 if (stub_type >= max_stub_type)
4336 abort (); /* Should be unreachable. */
4337
4ba2ef8f
TP		 4338 switch (stub_type)
4339 {
4340 /* Vectors of Secure Gateway veneers must be aligned on 32byte
4341 boundary. */
4342 case arm_stub_cmse_branch_thumb_only:
4343 return 5;
4344
4345 default:
4346 BFD_ASSERT (!arm_dedicated_stub_output_section_required (stub_type));
4347 return 0;
4348 }
4349
4350 abort (); /* Should be unreachable. */
daa4adae
TP		 4351}
4352
4353/* Name of the dedicated output section to put veneers of type STUB_TYPE, or
4354 NULL if veneers of this type are interspersed with input sections. */
4355
4356static const char *
4357arm_dedicated_stub_output_section_name (enum elf32_arm_stub_type stub_type)
4358{
4359 if (stub_type >= max_stub_type)
4360 abort (); /* Should be unreachable. */
4361
4ba2ef8f
TP		 4362 switch (stub_type)
4363 {
4364 case arm_stub_cmse_branch_thumb_only:
4365 return ".gnu.sgstubs";
4366
4367 default:
4368 BFD_ASSERT (!arm_dedicated_stub_output_section_required (stub_type));
4369 return NULL;
4370 }
4371
4372 abort (); /* Should be unreachable. */
daa4adae
TP		 4373}
4374
4375/* If veneers of type STUB_TYPE should go in a dedicated output section,
4376 returns the address of the hash table field in HTAB holding a pointer to the
4377 corresponding input section. Otherwise, returns NULL. */
4378
4379static asection **
4ba2ef8f
TP		 4380arm_dedicated_stub_input_section_ptr (struct elf32_arm_link_hash_table *htab,
4381 enum elf32_arm_stub_type stub_type)
daa4adae
TP		 4382{
4383 if (stub_type >= max_stub_type)
4384 abort (); /* Should be unreachable. */
4385
4ba2ef8f
TP		 4386 switch (stub_type)
4387 {
4388 case arm_stub_cmse_branch_thumb_only:
4389 return &htab->cmse_stub_sec;
4390
4391 default:
4392 BFD_ASSERT (!arm_dedicated_stub_output_section_required (stub_type));
4393 return NULL;
4394 }
4395
4396 abort (); /* Should be unreachable. */
daa4adae
TP		 4397}
4398
4399/* Find or create a stub section to contain a stub of type STUB_TYPE. SECTION
4400 is the section that branch into veneer and can be NULL if stub should go in
4401 a dedicated output section. Returns a pointer to the stub section, and the
4402 section to which the stub section will be attached (in *LINK_SEC_P).
48229727 4403 LINK_SEC_P may be NULL. */
906e58ca 4404
48229727
JB		 4405static asection *
4406elf32_arm_create_or_find_stub_sec (asection **link_sec_p, asection *section,
daa4adae
TP		 4407 struct elf32_arm_link_hash_table *htab,
4408 enum elf32_arm_stub_type stub_type)
906e58ca 4409{
daa4adae
TP		 4410 asection *link_sec, *out_sec, **stub_sec_p;
4411 const char *stub_sec_prefix;
4412 bfd_boolean dedicated_output_section =
4413 arm_dedicated_stub_output_section_required (stub_type);
4414 int align;
906e58ca 4415
daa4adae 4416 if (dedicated_output_section)
906e58ca 4417 {
daa4adae
TP		 4418 bfd *output_bfd = htab->obfd;
4419 const char *out_sec_name =
4420 arm_dedicated_stub_output_section_name (stub_type);
4421 link_sec = NULL;
4422 stub_sec_p = arm_dedicated_stub_input_section_ptr (htab, stub_type);
4423 stub_sec_prefix = out_sec_name;
4424 align = arm_dedicated_stub_output_section_required_alignment (stub_type);
4425 out_sec = bfd_get_section_by_name (output_bfd, out_sec_name);
4426 if (out_sec == NULL)
906e58ca 4427 {
4eca0228
AM		 4428 _bfd_error_handler (_("No address assigned to the veneers output "
4429 "section %s"), out_sec_name);
daa4adae 4430 return NULL;
906e58ca 4431 }
daa4adae
TP		 4432 }
4433 else
4434 {
c2abbbeb 4435 BFD_ASSERT (section->id <= htab->top_id);
daa4adae
TP		 4436 link_sec = htab->stub_group[section->id].link_sec;
4437 BFD_ASSERT (link_sec != NULL);
4438 stub_sec_p = &htab->stub_group[section->id].stub_sec;
4439 if (*stub_sec_p == NULL)
4440 stub_sec_p = &htab->stub_group[link_sec->id].stub_sec;
4441 stub_sec_prefix = link_sec->name;
4442 out_sec = link_sec->output_section;
4443 align = htab->nacl_p ? 4 : 3;
906e58ca 4444 }
b38cadfb 4445
daa4adae
TP		 4446 if (*stub_sec_p == NULL)
4447 {
4448 size_t namelen;
4449 bfd_size_type len;
4450 char *s_name;
4451
4452 namelen = strlen (stub_sec_prefix);
4453 len = namelen + sizeof (STUB_SUFFIX);
4454 s_name = (char *) bfd_alloc (htab->stub_bfd, len);
4455 if (s_name == NULL)
4456 return NULL;
4457
4458 memcpy (s_name, stub_sec_prefix, namelen);
4459 memcpy (s_name + namelen, STUB_SUFFIX, sizeof (STUB_SUFFIX));
4460 *stub_sec_p = (*htab->add_stub_section) (s_name, out_sec, link_sec,
4461 align);
4462 if (*stub_sec_p == NULL)
4463 return NULL;
4464
4465 out_sec->flags |= SEC_ALLOC | SEC_LOAD | SEC_READONLY | SEC_CODE
4466 | SEC_HAS_CONTENTS | SEC_RELOC | SEC_IN_MEMORY
4467 | SEC_KEEP;
4468 }
4469
4470 if (!dedicated_output_section)
4471 htab->stub_group[section->id].stub_sec = *stub_sec_p;
4472
48229727
JB		 4473 if (link_sec_p)
4474 *link_sec_p = link_sec;
b38cadfb 4475
daa4adae 4476 return *stub_sec_p;
48229727
JB		 4477}
4478
4479/* Add a new stub entry to the stub hash. Not all fields of the new
4480 stub entry are initialised. */
4481
4482static struct elf32_arm_stub_hash_entry *
daa4adae
TP		 4483elf32_arm_add_stub (const char *stub_name, asection *section,
4484 struct elf32_arm_link_hash_table *htab,
4485 enum elf32_arm_stub_type stub_type)
48229727
JB		 4486{
4487 asection *link_sec;
4488 asection *stub_sec;
4489 struct elf32_arm_stub_hash_entry *stub_entry;
4490
daa4adae
TP		 4491 stub_sec = elf32_arm_create_or_find_stub_sec (&link_sec, section, htab,
4492 stub_type);
48229727
JB		 4493 if (stub_sec == NULL)
4494 return NULL;
906e58ca
NC		 4495
4496 /* Enter this entry into the linker stub hash table. */
4497 stub_entry = arm_stub_hash_lookup (&htab->stub_hash_table, stub_name,
4498 TRUE, FALSE);
4499 if (stub_entry == NULL)
4500 {
6bde4c52
TP		 4501 if (section == NULL)
4502 section = stub_sec;
4eca0228
AM		 4503 _bfd_error_handler (_("%s: cannot create stub entry %s"),
4504 section->owner, stub_name);
906e58ca
NC		 4505 return NULL;
4506 }
4507
4508 stub_entry->stub_sec = stub_sec;
0955507f 4509 stub_entry->stub_offset = (bfd_vma) -1;
906e58ca
NC		 4510 stub_entry->id_sec = link_sec;
4511
906e58ca
NC		 4512 return stub_entry;
4513}
4514
4515/* Store an Arm insn into an output section not processed by
4516 elf32_arm_write_section. */
4517
4518static void
8029a119
NC		 4519put_arm_insn (struct elf32_arm_link_hash_table * htab,
4520 bfd * output_bfd, bfd_vma val, void * ptr)
906e58ca
NC		 4521{
4522 if (htab->byteswap_code != bfd_little_endian (output_bfd))
4523 bfd_putl32 (val, ptr);
4524 else
4525 bfd_putb32 (val, ptr);
4526}
4527
4528/* Store a 16-bit Thumb insn into an output section not processed by
4529 elf32_arm_write_section. */
4530
4531static void
8029a119
NC		 4532put_thumb_insn (struct elf32_arm_link_hash_table * htab,
4533 bfd * output_bfd, bfd_vma val, void * ptr)
906e58ca
NC		 4534{
4535 if (htab->byteswap_code != bfd_little_endian (output_bfd))
4536 bfd_putl16 (val, ptr);
4537 else
4538 bfd_putb16 (val, ptr);
4539}
4540
a504d23a
LA		 4541/* Store a Thumb2 insn into an output section not processed by
4542 elf32_arm_write_section. */
4543
4544static void
4545put_thumb2_insn (struct elf32_arm_link_hash_table * htab,
b98e6871 4546 bfd * output_bfd, bfd_vma val, bfd_byte * ptr)
a504d23a
LA		 4547{
4548 /* T2 instructions are 16-bit streamed. */
4549 if (htab->byteswap_code != bfd_little_endian (output_bfd))
4550 {
4551 bfd_putl16 ((val >> 16) & 0xffff, ptr);
4552 bfd_putl16 ((val & 0xffff), ptr + 2);
4553 }
4554 else
4555 {
4556 bfd_putb16 ((val >> 16) & 0xffff, ptr);
4557 bfd_putb16 ((val & 0xffff), ptr + 2);
4558 }
4559}
4560
0855e32b
NS		 4561/* If it's possible to change R_TYPE to a more efficient access
4562 model, return the new reloc type. */
4563
4564static unsigned
b38cadfb 4565elf32_arm_tls_transition (struct bfd_link_info *info, int r_type,
0855e32b
NS		 4566 struct elf_link_hash_entry *h)
4567{
4568 int is_local = (h == NULL);
4569
0e1862bb
L		 4570 if (bfd_link_pic (info)
4571 || (h && h->root.type == bfd_link_hash_undefweak))
0855e32b
NS		 4572 return r_type;
4573
b38cadfb 4574 /* We do not support relaxations for Old TLS models. */
0855e32b
NS		 4575 switch (r_type)
4576 {
4577 case R_ARM_TLS_GOTDESC:
4578 case R_ARM_TLS_CALL:
4579 case R_ARM_THM_TLS_CALL:
4580 case R_ARM_TLS_DESCSEQ:
4581 case R_ARM_THM_TLS_DESCSEQ:
4582 return is_local ? R_ARM_TLS_LE32 : R_ARM_TLS_IE32;
4583 }
4584
4585 return r_type;
4586}
4587
48229727
JB		 4588static bfd_reloc_status_type elf32_arm_final_link_relocate
4589 (reloc_howto_type *, bfd *, bfd *, asection *, bfd_byte *,
4590 Elf_Internal_Rela *, bfd_vma, struct bfd_link_info *, asection *,
34e77a92
RS		 4591 const char *, unsigned char, enum arm_st_branch_type,
4592 struct elf_link_hash_entry *, bfd_boolean *, char **);
48229727 4593
4563a860
JB		 4594static unsigned int
4595arm_stub_required_alignment (enum elf32_arm_stub_type stub_type)
4596{
4597 switch (stub_type)
4598 {
4599 case arm_stub_a8_veneer_b_cond:
4600 case arm_stub_a8_veneer_b:
4601 case arm_stub_a8_veneer_bl:
4602 return 2;
4603
4604 case arm_stub_long_branch_any_any:
4605 case arm_stub_long_branch_v4t_arm_thumb:
4606 case arm_stub_long_branch_thumb_only:
80c135e5 4607 case arm_stub_long_branch_thumb2_only:
d5a67c02 4608 case arm_stub_long_branch_thumb2_only_pure:
4563a860
JB		 4609 case arm_stub_long_branch_v4t_thumb_thumb:
4610 case arm_stub_long_branch_v4t_thumb_arm:
4611 case arm_stub_short_branch_v4t_thumb_arm:
4612 case arm_stub_long_branch_any_arm_pic:
4613 case arm_stub_long_branch_any_thumb_pic:
4614 case arm_stub_long_branch_v4t_thumb_thumb_pic:
4615 case arm_stub_long_branch_v4t_arm_thumb_pic:
4616 case arm_stub_long_branch_v4t_thumb_arm_pic:
4617 case arm_stub_long_branch_thumb_only_pic:
0855e32b
NS		 4618 case arm_stub_long_branch_any_tls_pic:
4619 case arm_stub_long_branch_v4t_thumb_tls_pic:
4ba2ef8f 4620 case arm_stub_cmse_branch_thumb_only:
4563a860
JB		 4621 case arm_stub_a8_veneer_blx:
4622 return 4;
b38cadfb 4623
7a89b94e
NC		 4624 case arm_stub_long_branch_arm_nacl:
4625 case arm_stub_long_branch_arm_nacl_pic:
4626 return 16;
4627
4563a860
JB		 4628 default:
4629 abort (); /* Should be unreachable. */
4630 }
4631}
4632
4f4faa4d
TP		 4633/* Returns whether stubs of type STUB_TYPE take over the symbol they are
4634 veneering (TRUE) or have their own symbol (FALSE). */
4635
4636static bfd_boolean
4637arm_stub_sym_claimed (enum elf32_arm_stub_type stub_type)
4638{
4639 if (stub_type >= max_stub_type)
4640 abort (); /* Should be unreachable. */
4641
4ba2ef8f
TP		 4642 switch (stub_type)
4643 {
4644 case arm_stub_cmse_branch_thumb_only:
4645 return TRUE;
4646
4647 default:
4648 return FALSE;
4649 }
4650
4651 abort (); /* Should be unreachable. */
4f4faa4d
TP		 4652}
4653
d7c5bd02
TP		 4654/* Returns the padding needed for the dedicated section used stubs of type
4655 STUB_TYPE. */
4656
4657static int
4658arm_dedicated_stub_section_padding (enum elf32_arm_stub_type stub_type)
4659{
4660 if (stub_type >= max_stub_type)
4661 abort (); /* Should be unreachable. */
4662
4ba2ef8f
TP		 4663 switch (stub_type)
4664 {
4665 case arm_stub_cmse_branch_thumb_only:
4666 return 32;
4667
4668 default:
4669 return 0;
4670 }
4671
4672 abort (); /* Should be unreachable. */
d7c5bd02
TP		 4673}
4674
0955507f
TP		 4675/* If veneers of type STUB_TYPE should go in a dedicated output section,
4676 returns the address of the hash table field in HTAB holding the offset at
4677 which new veneers should be layed out in the stub section. */
4678
4679static bfd_vma*
4680arm_new_stubs_start_offset_ptr (struct elf32_arm_link_hash_table *htab,
4681 enum elf32_arm_stub_type stub_type)
4682{
4683 switch (stub_type)
4684 {
4685 case arm_stub_cmse_branch_thumb_only:
4686 return &htab->new_cmse_stub_offset;
4687
4688 default:
4689 BFD_ASSERT (!arm_dedicated_stub_output_section_required (stub_type));
4690 return NULL;
4691 }
4692}
4693
906e58ca
NC		 4694static bfd_boolean
4695arm_build_one_stub (struct bfd_hash_entry *gen_entry,
4696 void * in_arg)
4697{
7a89b94e 4698#define MAXRELOCS 3
0955507f 4699 bfd_boolean removed_sg_veneer;
906e58ca 4700 struct elf32_arm_stub_hash_entry *stub_entry;
4dfe6ac6 4701 struct elf32_arm_link_hash_table *globals;
906e58ca 4702 struct bfd_link_info *info;
906e58ca
NC		 4703 asection *stub_sec;
4704 bfd *stub_bfd;
906e58ca
NC		 4705 bfd_byte *loc;
4706 bfd_vma sym_value;
4707 int template_size;
4708 int size;
d3ce72d0 4709 const insn_sequence *template_sequence;
906e58ca 4710 int i;
48229727
JB		 4711 int stub_reloc_idx[MAXRELOCS] = {-1, -1};
4712 int stub_reloc_offset[MAXRELOCS] = {0, 0};
4713 int nrelocs = 0;
0955507f 4714 int just_allocated = 0;
906e58ca
NC		 4715
4716 /* Massage our args to the form they really have. */
4717 stub_entry = (struct elf32_arm_stub_hash_entry *) gen_entry;
4718 info = (struct bfd_link_info *) in_arg;
4719
4720 globals = elf32_arm_hash_table (info);
4dfe6ac6
NC		 4721 if (globals == NULL)
4722 return FALSE;
906e58ca 4723
906e58ca
NC		 4724 stub_sec = stub_entry->stub_sec;
4725
4dfe6ac6 4726 if ((globals->fix_cortex_a8 < 0)
4563a860
JB		 4727 != (arm_stub_required_alignment (stub_entry->stub_type) == 2))
4728 /* We have to do less-strictly-aligned fixes last. */
eb7c4339 4729 return TRUE;
fe33d2fa 4730
0955507f
TP		 4731 /* Assign a slot at the end of section if none assigned yet. */
4732 if (stub_entry->stub_offset == (bfd_vma) -1)
4733 {
4734 stub_entry->stub_offset = stub_sec->size;
4735 just_allocated = 1;
4736 }
906e58ca
NC		 4737 loc = stub_sec->contents + stub_entry->stub_offset;
4738
4739 stub_bfd = stub_sec->owner;
4740
906e58ca
NC		 4741 /* This is the address of the stub destination. */
4742 sym_value = (stub_entry->target_value
4743 + stub_entry->target_section->output_offset
4744 + stub_entry->target_section->output_section->vma);
4745
d3ce72d0 4746 template_sequence = stub_entry->stub_template;
461a49ca 4747 template_size = stub_entry->stub_template_size;
906e58ca
NC		 4748
4749 size = 0;
461a49ca 4750 for (i = 0; i < template_size; i++)
906e58ca 4751 {
d3ce72d0 4752 switch (template_sequence[i].type)
461a49ca
DJ		 4753 {
4754 case THUMB16_TYPE:
48229727 4755 {
d3ce72d0
NC		 4756 bfd_vma data = (bfd_vma) template_sequence[i].data;
4757 if (template_sequence[i].reloc_addend != 0)
48229727 4758 {
99059e56
RM		 4759 /* We've borrowed the reloc_addend field to mean we should
4760 insert a condition code into this (Thumb-1 branch)
4761 instruction. See THUMB16_BCOND_INSN. */
4762 BFD_ASSERT ((data & 0xff00) == 0xd000);
4763 data |= ((stub_entry->orig_insn >> 22) & 0xf) << 8;
48229727 4764 }
fe33d2fa 4765 bfd_put_16 (stub_bfd, data, loc + size);
48229727
JB		 4766 size += 2;
4767 }
461a49ca 4768 break;
906e58ca 4769
48229727 4770 case THUMB32_TYPE:
fe33d2fa
CL		 4771 bfd_put_16 (stub_bfd,
4772 (template_sequence[i].data >> 16) & 0xffff,
4773 loc + size);
4774 bfd_put_16 (stub_bfd, template_sequence[i].data & 0xffff,
4775 loc + size + 2);
99059e56
RM		 4776 if (template_sequence[i].r_type != R_ARM_NONE)
4777 {
4778 stub_reloc_idx[nrelocs] = i;
4779 stub_reloc_offset[nrelocs++] = size;
4780 }
4781 size += 4;
4782 break;
48229727 4783
461a49ca 4784 case ARM_TYPE:
fe33d2fa
CL		 4785 bfd_put_32 (stub_bfd, template_sequence[i].data,
4786 loc + size);
461a49ca
DJ		 4787 /* Handle cases where the target is encoded within the
4788 instruction. */
d3ce72d0 4789 if (template_sequence[i].r_type == R_ARM_JUMP24)
461a49ca 4790 {
48229727
JB		 4791 stub_reloc_idx[nrelocs] = i;
4792 stub_reloc_offset[nrelocs++] = size;
461a49ca
DJ		 4793 }
4794 size += 4;
4795 break;
4796
4797 case DATA_TYPE:
d3ce72d0 4798 bfd_put_32 (stub_bfd, template_sequence[i].data, loc + size);
48229727
JB		 4799 stub_reloc_idx[nrelocs] = i;
4800 stub_reloc_offset[nrelocs++] = size;
461a49ca
DJ		 4801 size += 4;
4802 break;
4803
4804 default:
4805 BFD_FAIL ();
4806 return FALSE;
4807 }
906e58ca 4808 }
461a49ca 4809
0955507f
TP		 4810 if (just_allocated)
4811 stub_sec->size += size;
906e58ca 4812
461a49ca
DJ		 4813 /* Stub size has already been computed in arm_size_one_stub. Check
4814 consistency. */
4815 BFD_ASSERT (size == stub_entry->stub_size);
4816
906e58ca 4817 /* Destination is Thumb. Force bit 0 to 1 to reflect this. */
35fc36a8 4818 if (stub_entry->branch_type == ST_BRANCH_TO_THUMB)
906e58ca
NC		 4819 sym_value |= 1;
4820
0955507f
TP		 4821 /* Assume non empty slots have at least one and at most MAXRELOCS entries
4822 to relocate in each stub. */
4823 removed_sg_veneer =
4824 (size == 0 && stub_entry->stub_type == arm_stub_cmse_branch_thumb_only);
4825 BFD_ASSERT (removed_sg_veneer || (nrelocs != 0 && nrelocs <= MAXRELOCS));
c820be07 4826
48229727 4827 for (i = 0; i < nrelocs; i++)
8d9d9490
TP		 4828 {
4829 Elf_Internal_Rela rel;
4830 bfd_boolean unresolved_reloc;
4831 char *error_message;
4832 bfd_vma points_to =
4833 sym_value + template_sequence[stub_reloc_idx[i]].reloc_addend;
4834
4835 rel.r_offset = stub_entry->stub_offset + stub_reloc_offset[i];
4836 rel.r_info = ELF32_R_INFO (0,
4837 template_sequence[stub_reloc_idx[i]].r_type);
4838 rel.r_addend = 0;
4839
4840 if (stub_entry->stub_type == arm_stub_a8_veneer_b_cond && i == 0)
4841 /* The first relocation in the elf32_arm_stub_a8_veneer_b_cond[]
4842 template should refer back to the instruction after the original
4843 branch. We use target_section as Cortex-A8 erratum workaround stubs
4844 are only generated when both source and target are in the same
4845 section. */
4846 points_to = stub_entry->target_section->output_section->vma
4847 + stub_entry->target_section->output_offset
4848 + stub_entry->source_value;
4849
4850 elf32_arm_final_link_relocate (elf32_arm_howto_from_type
4851 (template_sequence[stub_reloc_idx[i]].r_type),
4852 stub_bfd, info->output_bfd, stub_sec, stub_sec->contents, &rel,
4853 points_to, info, stub_entry->target_section, "", STT_FUNC,
4854 stub_entry->branch_type,
4855 (struct elf_link_hash_entry *) stub_entry->h, &unresolved_reloc,
4856 &error_message);
4857 }
906e58ca
NC		 4858
4859 return TRUE;
48229727 4860#undef MAXRELOCS
906e58ca
NC		 4861}
4862
48229727
JB		 4863/* Calculate the template, template size and instruction size for a stub.
4864 Return value is the instruction size. */
906e58ca 4865
48229727
JB		 4866static unsigned int
4867find_stub_size_and_template (enum elf32_arm_stub_type stub_type,
4868 const insn_sequence **stub_template,
4869 int *stub_template_size)
906e58ca 4870{
d3ce72d0 4871 const insn_sequence *template_sequence = NULL;
48229727
JB		 4872 int template_size = 0, i;
4873 unsigned int size;
906e58ca 4874
d3ce72d0 4875 template_sequence = stub_definitions[stub_type].template_sequence;
2a229407
AM		 4876 if (stub_template)
4877 *stub_template = template_sequence;
4878
48229727 4879 template_size = stub_definitions[stub_type].template_size;
2a229407
AM		 4880 if (stub_template_size)
4881 *stub_template_size = template_size;
906e58ca
NC		 4882
4883 size = 0;
461a49ca
DJ		 4884 for (i = 0; i < template_size; i++)
4885 {
d3ce72d0 4886 switch (template_sequence[i].type)
461a49ca
DJ		 4887 {
4888 case THUMB16_TYPE:
4889 size += 2;
4890 break;
4891
4892 case ARM_TYPE:
48229727 4893 case THUMB32_TYPE:
461a49ca
DJ		 4894 case DATA_TYPE:
4895 size += 4;
4896 break;
4897
4898 default:
4899 BFD_FAIL ();
2a229407 4900 return 0;
461a49ca
DJ		 4901 }
4902 }
4903
48229727
JB		 4904 return size;
4905}
4906
4907/* As above, but don't actually build the stub. Just bump offset so
4908 we know stub section sizes. */
4909
4910static bfd_boolean
4911arm_size_one_stub (struct bfd_hash_entry *gen_entry,
c7e2358a 4912 void *in_arg ATTRIBUTE_UNUSED)
48229727
JB		 4913{
4914 struct elf32_arm_stub_hash_entry *stub_entry;
d3ce72d0 4915 const insn_sequence *template_sequence;
48229727
JB		 4916 int template_size, size;
4917
4918 /* Massage our args to the form they really have. */
4919 stub_entry = (struct elf32_arm_stub_hash_entry *) gen_entry;
48229727
JB		 4920
4921 BFD_ASSERT((stub_entry->stub_type > arm_stub_none)
4922 && stub_entry->stub_type < ARRAY_SIZE(stub_definitions));
4923
d3ce72d0 4924 size = find_stub_size_and_template (stub_entry->stub_type, &template_sequence,
48229727
JB		 4925 &template_size);
4926
0955507f
TP		 4927 /* Initialized to -1. Null size indicates an empty slot full of zeros. */
4928 if (stub_entry->stub_template_size)
4929 {
4930 stub_entry->stub_size = size;
4931 stub_entry->stub_template = template_sequence;
4932 stub_entry->stub_template_size = template_size;
4933 }
4934
4935 /* Already accounted for. */
4936 if (stub_entry->stub_offset != (bfd_vma) -1)
4937 return TRUE;
461a49ca 4938
906e58ca
NC		 4939 size = (size + 7) & ~7;
4940 stub_entry->stub_sec->size += size;
461a49ca 4941
906e58ca
NC		 4942 return TRUE;
4943}
4944
4945/* External entry points for sizing and building linker stubs. */
4946
4947/* Set up various things so that we can make a list of input sections
4948 for each output section included in the link. Returns -1 on error,
4949 0 when no stubs will be needed, and 1 on success. */
4950
4951int
4952elf32_arm_setup_section_lists (bfd *output_bfd,
4953 struct bfd_link_info *info)
4954{
4955 bfd *input_bfd;
4956 unsigned int bfd_count;
7292b3ac 4957 unsigned int top_id, top_index;
906e58ca
NC		 4958 asection *section;
4959 asection **input_list, **list;
4960 bfd_size_type amt;
4961 struct elf32_arm_link_hash_table *htab = elf32_arm_hash_table (info);
4962
4dfe6ac6
NC		 4963 if (htab == NULL)
4964 return 0;
906e58ca
NC		 4965 if (! is_elf_hash_table (htab))
4966 return 0;
4967
4968 /* Count the number of input BFDs and find the top input section id. */
4969 for (input_bfd = info->input_bfds, bfd_count = 0, top_id = 0;
4970 input_bfd != NULL;
c72f2fb2 4971 input_bfd = input_bfd->link.next)
906e58ca
NC		 4972 {
4973 bfd_count += 1;
4974 for (section = input_bfd->sections;
4975 section != NULL;
4976 section = section->next)
4977 {
4978 if (top_id < section->id)
4979 top_id = section->id;
4980 }
4981 }
4982 htab->bfd_count = bfd_count;
4983
4984 amt = sizeof (struct map_stub) * (top_id + 1);
21d799b5 4985 htab->stub_group = (struct map_stub *) bfd_zmalloc (amt);
906e58ca
NC		 4986 if (htab->stub_group == NULL)
4987 return -1;
fe33d2fa 4988 htab->top_id = top_id;
906e58ca
NC		 4989
4990 /* We can't use output_bfd->section_count here to find the top output
4991 section index as some sections may have been removed, and
4992 _bfd_strip_section_from_output doesn't renumber the indices. */
4993 for (section = output_bfd->sections, top_index = 0;
4994 section != NULL;
4995 section = section->next)
4996 {
4997 if (top_index < section->index)
4998 top_index = section->index;
4999 }
5000
5001 htab->top_index = top_index;
5002 amt = sizeof (asection *) * (top_index + 1);
21d799b5 5003 input_list = (asection **) bfd_malloc (amt);
906e58ca
NC		 5004 htab->input_list = input_list;
5005 if (input_list == NULL)
5006 return -1;
5007
5008 /* For sections we aren't interested in, mark their entries with a
5009 value we can check later. */
5010 list = input_list + top_index;
5011 do
5012 *list = bfd_abs_section_ptr;
5013 while (list-- != input_list);
5014
5015 for (section = output_bfd->sections;
5016 section != NULL;
5017 section = section->next)
5018 {
5019 if ((section->flags & SEC_CODE) != 0)
5020 input_list[section->index] = NULL;
5021 }
5022
5023 return 1;
5024}
5025
5026/* The linker repeatedly calls this function for each input section,
5027 in the order that input sections are linked into output sections.
5028 Build lists of input sections to determine groupings between which
5029 we may insert linker stubs. */
5030
5031void
5032elf32_arm_next_input_section (struct bfd_link_info *info,
5033 asection *isec)
5034{
5035 struct elf32_arm_link_hash_table *htab = elf32_arm_hash_table (info);
5036
4dfe6ac6
NC		 5037 if (htab == NULL)
5038 return;
5039
906e58ca
NC		 5040 if (isec->output_section->index <= htab->top_index)
5041 {
5042 asection **list = htab->input_list + isec->output_section->index;
5043
a7470592 5044 if (*list != bfd_abs_section_ptr && (isec->flags & SEC_CODE) != 0)
906e58ca
NC		 5045 {
5046 /* Steal the link_sec pointer for our list. */
5047#define PREV_SEC(sec) (htab->stub_group[(sec)->id].link_sec)
5048 /* This happens to make the list in reverse order,
07d72278 5049 which we reverse later. */
906e58ca
NC		 5050 PREV_SEC (isec) = *list;
5051 *list = isec;
5052 }
5053 }
5054}
5055
5056/* See whether we can group stub sections together. Grouping stub
5057 sections may result in fewer stubs. More importantly, we need to
07d72278 5058 put all .init* and .fini* stubs at the end of the .init or
906e58ca
NC		 5059 .fini output sections respectively, because glibc splits the
5060 _init and _fini functions into multiple parts. Putting a stub in
5061 the middle of a function is not a good idea. */
5062
5063static void
5064group_sections (struct elf32_arm_link_hash_table *htab,
5065 bfd_size_type stub_group_size,
07d72278 5066 bfd_boolean stubs_always_after_branch)
906e58ca 5067{
07d72278 5068 asection **list = htab->input_list;
906e58ca
NC		 5069
5070 do
5071 {
5072 asection *tail = *list;
07d72278 5073 asection *head;
906e58ca
NC		 5074
5075 if (tail == bfd_abs_section_ptr)
5076 continue;
5077
07d72278
DJ		 5078 /* Reverse the list: we must avoid placing stubs at the
5079 beginning of the section because the beginning of the text
5080 section may be required for an interrupt vector in bare metal
5081 code. */
5082#define NEXT_SEC PREV_SEC
e780aef2
CL		 5083 head = NULL;
5084 while (tail != NULL)
99059e56
RM		 5085 {
5086 /* Pop from tail. */
5087 asection *item = tail;
5088 tail = PREV_SEC (item);
e780aef2 5089
99059e56
RM		 5090 /* Push on head. */
5091 NEXT_SEC (item) = head;
5092 head = item;
5093 }
07d72278
DJ		 5094
5095 while (head != NULL)
906e58ca
NC		 5096 {
5097 asection *curr;
07d72278 5098 asection *next;
e780aef2
CL		 5099 bfd_vma stub_group_start = head->output_offset;
5100 bfd_vma end_of_next;
906e58ca 5101
07d72278 5102 curr = head;
e780aef2 5103 while (NEXT_SEC (curr) != NULL)
8cd931b7 5104 {
e780aef2
CL		 5105 next = NEXT_SEC (curr);
5106 end_of_next = next->output_offset + next->size;
5107 if (end_of_next - stub_group_start >= stub_group_size)
5108 /* End of NEXT is too far from start, so stop. */
8cd931b7 5109 break;
e780aef2
CL		 5110 /* Add NEXT to the group. */
5111 curr = next;
8cd931b7 5112 }
906e58ca 5113
07d72278 5114 /* OK, the size from the start to the start of CURR is less
906e58ca 5115 than stub_group_size and thus can be handled by one stub
07d72278 5116 section. (Or the head section is itself larger than
906e58ca
NC		 5117 stub_group_size, in which case we may be toast.)
5118 We should really be keeping track of the total size of
5119 stubs added here, as stubs contribute to the final output
7fb9f789 5120 section size. */
906e58ca
NC		 5121 do
5122 {
07d72278 5123 next = NEXT_SEC (head);
906e58ca 5124 /* Set up this stub group. */
07d72278 5125 htab->stub_group[head->id].link_sec = curr;
906e58ca 5126 }
07d72278 5127 while (head != curr && (head = next) != NULL);
906e58ca
NC		 5128
5129 /* But wait, there's more! Input sections up to stub_group_size
07d72278
DJ		 5130 bytes after the stub section can be handled by it too. */
5131 if (!stubs_always_after_branch)
906e58ca 5132 {
e780aef2
CL		 5133 stub_group_start = curr->output_offset + curr->size;
5134
8cd931b7 5135 while (next != NULL)
906e58ca 5136 {
e780aef2
CL		 5137 end_of_next = next->output_offset + next->size;
5138 if (end_of_next - stub_group_start >= stub_group_size)
5139 /* End of NEXT is too far from stubs, so stop. */
8cd931b7 5140 break;
e780aef2 5141 /* Add NEXT to the stub group. */
07d72278
DJ		 5142 head = next;
5143 next = NEXT_SEC (head);
5144 htab->stub_group[head->id].link_sec = curr;
906e58ca
NC		 5145 }
5146 }
07d72278 5147 head = next;
906e58ca
NC		 5148 }
5149 }
07d72278 5150 while (list++ != htab->input_list + htab->top_index);
906e58ca
NC		 5151
5152 free (htab->input_list);
5153#undef PREV_SEC
07d72278 5154#undef NEXT_SEC
906e58ca
NC		 5155}
5156
48229727
JB		 5157/* Comparison function for sorting/searching relocations relating to Cortex-A8
5158 erratum fix. */
5159
5160static int
5161a8_reloc_compare (const void *a, const void *b)
5162{
21d799b5
NC		 5163 const struct a8_erratum_reloc *ra = (const struct a8_erratum_reloc *) a;
5164 const struct a8_erratum_reloc *rb = (const struct a8_erratum_reloc *) b;
48229727
JB		 5165
5166 if (ra->from < rb->from)
5167 return -1;
5168 else if (ra->from > rb->from)
5169 return 1;
5170 else
5171 return 0;
5172}
5173
5174static struct elf_link_hash_entry *find_thumb_glue (struct bfd_link_info *,
5175 const char *, char **);
5176
5177/* Helper function to scan code for sequences which might trigger the Cortex-A8
5178 branch/TLB erratum. Fill in the table described by A8_FIXES_P,
81694485 5179 NUM_A8_FIXES_P, A8_FIX_TABLE_SIZE_P. Returns true if an error occurs, false
48229727
JB		 5180 otherwise. */
5181
81694485
NC		 5182static bfd_boolean
5183cortex_a8_erratum_scan (bfd *input_bfd,
5184 struct bfd_link_info *info,
48229727
JB		 5185 struct a8_erratum_fix **a8_fixes_p,
5186 unsigned int *num_a8_fixes_p,
5187 unsigned int *a8_fix_table_size_p,
5188 struct a8_erratum_reloc *a8_relocs,
eb7c4339
NS		 5189 unsigned int num_a8_relocs,
5190 unsigned prev_num_a8_fixes,
5191 bfd_boolean *stub_changed_p)
48229727
JB		 5192{
5193 asection *section;
5194 struct elf32_arm_link_hash_table *htab = elf32_arm_hash_table (info);
5195 struct a8_erratum_fix *a8_fixes = *a8_fixes_p;
5196 unsigned int num_a8_fixes = *num_a8_fixes_p;
5197 unsigned int a8_fix_table_size = *a8_fix_table_size_p;
5198
4dfe6ac6
NC		 5199 if (htab == NULL)
5200 return FALSE;
5201
48229727
JB		 5202 for (section = input_bfd->sections;
5203 section != NULL;
5204 section = section->next)
5205 {
5206 bfd_byte *contents = NULL;
5207 struct _arm_elf_section_data *sec_data;
5208 unsigned int span;
5209 bfd_vma base_vma;
5210
5211 if (elf_section_type (section) != SHT_PROGBITS
99059e56
RM		 5212 || (elf_section_flags (section) & SHF_EXECINSTR) == 0
5213 || (section->flags & SEC_EXCLUDE) != 0
5214 || (section->sec_info_type == SEC_INFO_TYPE_JUST_SYMS)
5215 || (section->output_section == bfd_abs_section_ptr))
5216 continue;
48229727
JB		 5217
5218 base_vma = section->output_section->vma + section->output_offset;
5219
5220 if (elf_section_data (section)->this_hdr.contents != NULL)
99059e56 5221 contents = elf_section_data (section)->this_hdr.contents;
48229727 5222 else if (! bfd_malloc_and_get_section (input_bfd, section, &contents))
99059e56 5223 return TRUE;
48229727
JB		 5224
5225 sec_data = elf32_arm_section_data (section);
5226
5227 for (span = 0; span < sec_data->mapcount; span++)
99059e56
RM		 5228 {
5229 unsigned int span_start = sec_data->map[span].vma;
5230 unsigned int span_end = (span == sec_data->mapcount - 1)
5231 ? section->size : sec_data->map[span + 1].vma;
5232 unsigned int i;
5233 char span_type = sec_data->map[span].type;
5234 bfd_boolean last_was_32bit = FALSE, last_was_branch = FALSE;
5235
5236 if (span_type != 't')
5237 continue;
5238
5239 /* Span is entirely within a single 4KB region: skip scanning. */
5240 if (((base_vma + span_start) & ~0xfff)
48229727 5241 == ((base_vma + span_end) & ~0xfff))
99059e56
RM		 5242 continue;
5243
5244 /* Scan for 32-bit Thumb-2 branches which span two 4K regions, where:
5245
5246 * The opcode is BLX.W, BL.W, B.W, Bcc.W
5247 * The branch target is in the same 4KB region as the
5248 first half of the branch.
5249 * The instruction before the branch is a 32-bit
5250 length non-branch instruction. */
5251 for (i = span_start; i < span_end;)
5252 {
5253 unsigned int insn = bfd_getl16 (&contents[i]);
5254 bfd_boolean insn_32bit = FALSE, is_blx = FALSE, is_b = FALSE;
48229727
JB		 5255 bfd_boolean is_bl = FALSE, is_bcc = FALSE, is_32bit_branch;
5256
99059e56
RM		 5257 if ((insn & 0xe000) == 0xe000 && (insn & 0x1800) != 0x0000)
5258 insn_32bit = TRUE;
48229727
JB		 5259
5260 if (insn_32bit)
99059e56
RM		 5261 {
5262 /* Load the rest of the insn (in manual-friendly order). */
5263 insn = (insn << 16) | bfd_getl16 (&contents[i + 2]);
5264
5265 /* Encoding T4: B<c>.W. */
5266 is_b = (insn & 0xf800d000) == 0xf0009000;
5267 /* Encoding T1: BL<c>.W. */
5268 is_bl = (insn & 0xf800d000) == 0xf000d000;
5269 /* Encoding T2: BLX<c>.W. */
5270 is_blx = (insn & 0xf800d000) == 0xf000c000;
48229727
JB		 5271 /* Encoding T3: B<c>.W (not permitted in IT block). */
5272 is_bcc = (insn & 0xf800d000) == 0xf0008000
5273 && (insn & 0x07f00000) != 0x03800000;
5274 }
5275
5276 is_32bit_branch = is_b || is_bl || is_blx || is_bcc;
fe33d2fa 5277
99059e56 5278 if (((base_vma + i) & 0xfff) == 0xffe
81694485
NC		 5279 && insn_32bit
5280 && is_32bit_branch
5281 && last_was_32bit
5282 && ! last_was_branch)
99059e56
RM		 5283 {
5284 bfd_signed_vma offset = 0;
5285 bfd_boolean force_target_arm = FALSE;
48229727 5286 bfd_boolean force_target_thumb = FALSE;
99059e56
RM		 5287 bfd_vma target;
5288 enum elf32_arm_stub_type stub_type = arm_stub_none;
5289 struct a8_erratum_reloc key, *found;
5290 bfd_boolean use_plt = FALSE;
48229727 5291
99059e56
RM		 5292 key.from = base_vma + i;
5293 found = (struct a8_erratum_reloc *)
5294 bsearch (&key, a8_relocs, num_a8_relocs,
5295 sizeof (struct a8_erratum_reloc),
5296 &a8_reloc_compare);
48229727
JB		 5297
5298 if (found)
5299 {
5300 char *error_message = NULL;
5301 struct elf_link_hash_entry *entry;
5302
5303 /* We don't care about the error returned from this
99059e56 5304 function, only if there is glue or not. */
48229727
JB		 5305 entry = find_thumb_glue (info, found->sym_name,
5306 &error_message);
5307
5308 if (entry)
5309 found->non_a8_stub = TRUE;
5310
92750f34 5311 /* Keep a simpler condition, for the sake of clarity. */
362d30a1 5312 if (htab->root.splt != NULL && found->hash != NULL
92750f34
DJ		 5313 && found->hash->root.plt.offset != (bfd_vma) -1)
5314 use_plt = TRUE;
5315
5316 if (found->r_type == R_ARM_THM_CALL)
5317 {
35fc36a8
RS		 5318 if (found->branch_type == ST_BRANCH_TO_ARM
5319 || use_plt)
92750f34
DJ		 5320 force_target_arm = TRUE;
5321 else
5322 force_target_thumb = TRUE;
5323 }
48229727
JB		 5324 }
5325
99059e56 5326 /* Check if we have an offending branch instruction. */
48229727
JB		 5327
5328 if (found && found->non_a8_stub)
5329 /* We've already made a stub for this instruction, e.g.
5330 it's a long branch or a Thumb->ARM stub. Assume that
5331 stub will suffice to work around the A8 erratum (see
5332 setting of always_after_branch above). */
5333 ;
99059e56
RM		 5334 else if (is_bcc)
5335 {
5336 offset = (insn & 0x7ff) << 1;
5337 offset |= (insn & 0x3f0000) >> 4;
5338 offset |= (insn & 0x2000) ? 0x40000 : 0;
5339 offset |= (insn & 0x800) ? 0x80000 : 0;
5340 offset |= (insn & 0x4000000) ? 0x100000 : 0;
5341 if (offset & 0x100000)
5342 offset |= ~ ((bfd_signed_vma) 0xfffff);
5343 stub_type = arm_stub_a8_veneer_b_cond;
5344 }
5345 else if (is_b || is_bl || is_blx)
5346 {
5347 int s = (insn & 0x4000000) != 0;
5348 int j1 = (insn & 0x2000) != 0;
5349 int j2 = (insn & 0x800) != 0;
5350 int i1 = !(j1 ^ s);
5351 int i2 = !(j2 ^ s);
5352
5353 offset = (insn & 0x7ff) << 1;
5354 offset |= (insn & 0x3ff0000) >> 4;
5355 offset |= i2 << 22;
5356 offset |= i1 << 23;
5357 offset |= s << 24;
5358 if (offset & 0x1000000)
5359 offset |= ~ ((bfd_signed_vma) 0xffffff);
5360
5361 if (is_blx)
5362 offset &= ~ ((bfd_signed_vma) 3);
5363
5364 stub_type = is_blx ? arm_stub_a8_veneer_blx :
5365 is_bl ? arm_stub_a8_veneer_bl : arm_stub_a8_veneer_b;
5366 }
5367
5368 if (stub_type != arm_stub_none)
5369 {
5370 bfd_vma pc_for_insn = base_vma + i + 4;
48229727
JB		 5371
5372 /* The original instruction is a BL, but the target is
99059e56 5373 an ARM instruction. If we were not making a stub,
48229727
JB		 5374 the BL would have been converted to a BLX. Use the
5375 BLX stub instead in that case. */
5376 if (htab->use_blx && force_target_arm
5377 && stub_type == arm_stub_a8_veneer_bl)
5378 {
5379 stub_type = arm_stub_a8_veneer_blx;
5380 is_blx = TRUE;
5381 is_bl = FALSE;
5382 }
5383 /* Conversely, if the original instruction was
5384 BLX but the target is Thumb mode, use the BL
5385 stub. */
5386 else if (force_target_thumb
5387 && stub_type == arm_stub_a8_veneer_blx)
5388 {
5389 stub_type = arm_stub_a8_veneer_bl;
5390 is_blx = FALSE;
5391 is_bl = TRUE;
5392 }
5393
99059e56
RM		 5394 if (is_blx)
5395 pc_for_insn &= ~ ((bfd_vma) 3);
48229727 5396
99059e56
RM		 5397 /* If we found a relocation, use the proper destination,
5398 not the offset in the (unrelocated) instruction.
48229727
JB		 5399 Note this is always done if we switched the stub type
5400 above. */
99059e56
RM		 5401 if (found)
5402 offset =
81694485 5403 (bfd_signed_vma) (found->destination - pc_for_insn);
48229727 5404
99059e56
RM		 5405 /* If the stub will use a Thumb-mode branch to a
5406 PLT target, redirect it to the preceding Thumb
5407 entry point. */
5408 if (stub_type != arm_stub_a8_veneer_blx && use_plt)
5409 offset -= PLT_THUMB_STUB_SIZE;
7d24e6a6 5410
99059e56 5411 target = pc_for_insn + offset;
48229727 5412
99059e56
RM		 5413 /* The BLX stub is ARM-mode code. Adjust the offset to
5414 take the different PC value (+8 instead of +4) into
48229727 5415 account. */
99059e56
RM		 5416 if (stub_type == arm_stub_a8_veneer_blx)
5417 offset += 4;
5418
5419 if (((base_vma + i) & ~0xfff) == (target & ~0xfff))
5420 {
5421 char *stub_name = NULL;
5422
5423 if (num_a8_fixes == a8_fix_table_size)
5424 {
5425 a8_fix_table_size *= 2;
5426 a8_fixes = (struct a8_erratum_fix *)
5427 bfd_realloc (a8_fixes,
5428 sizeof (struct a8_erratum_fix)
5429 * a8_fix_table_size);
5430 }
48229727 5431
eb7c4339
NS		 5432 if (num_a8_fixes < prev_num_a8_fixes)
5433 {
5434 /* If we're doing a subsequent scan,
5435 check if we've found the same fix as
5436 before, and try and reuse the stub
5437 name. */
5438 stub_name = a8_fixes[num_a8_fixes].stub_name;
5439 if ((a8_fixes[num_a8_fixes].section != section)
5440 || (a8_fixes[num_a8_fixes].offset != i))
5441 {
5442 free (stub_name);
5443 stub_name = NULL;
5444 *stub_changed_p = TRUE;
5445 }
5446 }
5447
5448 if (!stub_name)
5449 {
21d799b5 5450 stub_name = (char *) bfd_malloc (8 + 1 + 8 + 1);
eb7c4339
NS		 5451 if (stub_name != NULL)
5452 sprintf (stub_name, "%x:%x", section->id, i);
5453 }
48229727 5454
99059e56
RM		 5455 a8_fixes[num_a8_fixes].input_bfd = input_bfd;
5456 a8_fixes[num_a8_fixes].section = section;
5457 a8_fixes[num_a8_fixes].offset = i;
8d9d9490
TP		 5458 a8_fixes[num_a8_fixes].target_offset =
5459 target - base_vma;
99059e56
RM		 5460 a8_fixes[num_a8_fixes].orig_insn = insn;
5461 a8_fixes[num_a8_fixes].stub_name = stub_name;
5462 a8_fixes[num_a8_fixes].stub_type = stub_type;
5463 a8_fixes[num_a8_fixes].branch_type =
35fc36a8 5464 is_blx ? ST_BRANCH_TO_ARM : ST_BRANCH_TO_THUMB;
48229727 5465
99059e56
RM		 5466 num_a8_fixes++;
5467 }
5468 }
5469 }
48229727 5470
99059e56
RM		 5471 i += insn_32bit ? 4 : 2;
5472 last_was_32bit = insn_32bit;
48229727 5473 last_was_branch = is_32bit_branch;
99059e56
RM		 5474 }
5475 }
48229727
JB		 5476
5477 if (elf_section_data (section)->this_hdr.contents == NULL)
99059e56 5478 free (contents);
48229727 5479 }
fe33d2fa 5480
48229727
JB		 5481 *a8_fixes_p = a8_fixes;
5482 *num_a8_fixes_p = num_a8_fixes;
5483 *a8_fix_table_size_p = a8_fix_table_size;
fe33d2fa 5484
81694485 5485 return FALSE;
48229727
JB		 5486}
5487
b715f643
TP		 5488/* Create or update a stub entry depending on whether the stub can already be
5489 found in HTAB. The stub is identified by:
5490 - its type STUB_TYPE
5491 - its source branch (note that several can share the same stub) whose
5492 section and relocation (if any) are given by SECTION and IRELA
5493 respectively
5494 - its target symbol whose input section, hash, name, value and branch type
5495 are given in SYM_SEC, HASH, SYM_NAME, SYM_VALUE and BRANCH_TYPE
5496 respectively
5497
5498 If found, the value of the stub's target symbol is updated from SYM_VALUE
5499 and *NEW_STUB is set to FALSE. Otherwise, *NEW_STUB is set to
5500 TRUE and the stub entry is initialized.
5501
0955507f
TP		 5502 Returns the stub that was created or updated, or NULL if an error
5503 occurred. */
b715f643 5504
0955507f 5505static struct elf32_arm_stub_hash_entry *
b715f643
TP		 5506elf32_arm_create_stub (struct elf32_arm_link_hash_table *htab,
5507 enum elf32_arm_stub_type stub_type, asection *section,
5508 Elf_Internal_Rela *irela, asection *sym_sec,
5509 struct elf32_arm_link_hash_entry *hash, char *sym_name,
5510 bfd_vma sym_value, enum arm_st_branch_type branch_type,
5511 bfd_boolean *new_stub)
5512{
5513 const asection *id_sec;
5514 char *stub_name;
5515 struct elf32_arm_stub_hash_entry *stub_entry;
5516 unsigned int r_type;
4f4faa4d 5517 bfd_boolean sym_claimed = arm_stub_sym_claimed (stub_type);
b715f643
TP		 5518
5519 BFD_ASSERT (stub_type != arm_stub_none);
5520 *new_stub = FALSE;
5521
4f4faa4d
TP		 5522 if (sym_claimed)
5523 stub_name = sym_name;
5524 else
5525 {
5526 BFD_ASSERT (irela);
5527 BFD_ASSERT (section);
c2abbbeb 5528 BFD_ASSERT (section->id <= htab->top_id);
b715f643 5529
4f4faa4d
TP		 5530 /* Support for grouping stub sections. */
5531 id_sec = htab->stub_group[section->id].link_sec;
b715f643 5532
4f4faa4d
TP		 5533 /* Get the name of this stub. */
5534 stub_name = elf32_arm_stub_name (id_sec, sym_sec, hash, irela,
5535 stub_type);
5536 if (!stub_name)
0955507f 5537 return NULL;
4f4faa4d 5538 }
b715f643
TP		 5539
5540 stub_entry = arm_stub_hash_lookup (&htab->stub_hash_table, stub_name, FALSE,
5541 FALSE);
5542 /* The proper stub has already been created, just update its value. */
5543 if (stub_entry != NULL)
5544 {
4f4faa4d
TP		 5545 if (!sym_claimed)
5546 free (stub_name);
b715f643 5547 stub_entry->target_value = sym_value;
0955507f 5548 return stub_entry;
b715f643
TP		 5549 }
5550
daa4adae 5551 stub_entry = elf32_arm_add_stub (stub_name, section, htab, stub_type);
b715f643
TP		 5552 if (stub_entry == NULL)
5553 {
4f4faa4d
TP		 5554 if (!sym_claimed)
5555 free (stub_name);
0955507f 5556 return NULL;
b715f643
TP		 5557 }
5558
5559 stub_entry->target_value = sym_value;
5560 stub_entry->target_section = sym_sec;
5561 stub_entry->stub_type = stub_type;
5562 stub_entry->h = hash;
5563 stub_entry->branch_type = branch_type;
5564
4f4faa4d
TP		 5565 if (sym_claimed)
5566 stub_entry->output_name = sym_name;
5567 else
b715f643 5568 {
4f4faa4d
TP		 5569 if (sym_name == NULL)
5570 sym_name = "unnamed";
5571 stub_entry->output_name = (char *)
5572 bfd_alloc (htab->stub_bfd, sizeof (THUMB2ARM_GLUE_ENTRY_NAME)
5573 + strlen (sym_name));
5574 if (stub_entry->output_name == NULL)
5575 {
5576 free (stub_name);
0955507f 5577 return NULL;
4f4faa4d 5578 }
b715f643 5579
4f4faa4d
TP		 5580 /* For historical reasons, use the existing names for ARM-to-Thumb and
5581 Thumb-to-ARM stubs. */
5582 r_type = ELF32_R_TYPE (irela->r_info);
5583 if ((r_type == (unsigned int) R_ARM_THM_CALL
5584 || r_type == (unsigned int) R_ARM_THM_JUMP24
5585 || r_type == (unsigned int) R_ARM_THM_JUMP19)
5586 && branch_type == ST_BRANCH_TO_ARM)
5587 sprintf (stub_entry->output_name, THUMB2ARM_GLUE_ENTRY_NAME, sym_name);
5588 else if ((r_type == (unsigned int) R_ARM_CALL
5589 || r_type == (unsigned int) R_ARM_JUMP24)
5590 && branch_type == ST_BRANCH_TO_THUMB)
5591 sprintf (stub_entry->output_name, ARM2THUMB_GLUE_ENTRY_NAME, sym_name);
5592 else
5593 sprintf (stub_entry->output_name, STUB_ENTRY_NAME, sym_name);
5594 }
b715f643
TP		 5595
5596 *new_stub = TRUE;
0955507f 5597 return stub_entry;
b715f643
TP		 5598}
5599
4ba2ef8f
TP		 5600/* Scan symbols in INPUT_BFD to identify secure entry functions needing a
5601 gateway veneer to transition from non secure to secure state and create them
5602 accordingly.
5603
5604 "ARMv8-M Security Extensions: Requirements on Development Tools" document
5605 defines the conditions that govern Secure Gateway veneer creation for a
5606 given symbol <SYM> as follows:
5607 - it has function type
5608 - it has non local binding
5609 - a symbol named __acle_se_<SYM> (called special symbol) exists with the
5610 same type, binding and value as <SYM> (called normal symbol).
5611 An entry function can handle secure state transition itself in which case
5612 its special symbol would have a different value from the normal symbol.
5613
5614 OUT_ATTR gives the output attributes, SYM_HASHES the symbol index to hash
5615 entry mapping while HTAB gives the name to hash entry mapping.
0955507f
TP		 5616 *CMSE_STUB_CREATED is increased by the number of secure gateway veneer
5617 created.
4ba2ef8f 5618
0955507f 5619 The return value gives whether a stub failed to be allocated. */
4ba2ef8f
TP		 5620
5621static bfd_boolean
5622cmse_scan (bfd *input_bfd, struct elf32_arm_link_hash_table *htab,
5623 obj_attribute *out_attr, struct elf_link_hash_entry **sym_hashes,
0955507f 5624 int *cmse_stub_created)
4ba2ef8f
TP		 5625{
5626 const struct elf_backend_data *bed;
5627 Elf_Internal_Shdr *symtab_hdr;
5628 unsigned i, j, sym_count, ext_start;
5629 Elf_Internal_Sym *cmse_sym, *local_syms;
5630 struct elf32_arm_link_hash_entry *hash, *cmse_hash = NULL;
5631 enum arm_st_branch_type branch_type;
5632 char *sym_name, *lsym_name;
5633 bfd_vma sym_value;
5634 asection *section;
0955507f
TP		 5635 struct elf32_arm_stub_hash_entry *stub_entry;
5636 bfd_boolean is_v8m, new_stub, cmse_invalid, ret = TRUE;
4ba2ef8f
TP		 5637
5638 bed = get_elf_backend_data (input_bfd);
5639 symtab_hdr = &elf_tdata (input_bfd)->symtab_hdr;
5640 sym_count = symtab_hdr->sh_size / bed->s->sizeof_sym;
5641 ext_start = symtab_hdr->sh_info;
5642 is_v8m = (out_attr[Tag_CPU_arch].i >= TAG_CPU_ARCH_V8M_BASE
5643 && out_attr[Tag_CPU_arch_profile].i == 'M');
5644
5645 local_syms = (Elf_Internal_Sym *) symtab_hdr->contents;
5646 if (local_syms == NULL)
5647 local_syms = bfd_elf_get_elf_syms (input_bfd, symtab_hdr,
5648 symtab_hdr->sh_info, 0, NULL, NULL,
5649 NULL);
5650 if (symtab_hdr->sh_info && local_syms == NULL)
5651 return FALSE;
5652
5653 /* Scan symbols. */
5654 for (i = 0; i < sym_count; i++)
5655 {
5656 cmse_invalid = FALSE;
5657
5658 if (i < ext_start)
5659 {
5660 cmse_sym = &local_syms[i];
5661 /* Not a special symbol. */
5662 if (!ARM_GET_SYM_CMSE_SPCL (cmse_sym->st_target_internal))
5663 continue;
5664 sym_name = bfd_elf_string_from_elf_section (input_bfd,
5665 symtab_hdr->sh_link,
5666 cmse_sym->st_name);
5667 /* Special symbol with local binding. */
5668 cmse_invalid = TRUE;
5669 }
5670 else
5671 {
5672 cmse_hash = elf32_arm_hash_entry (sym_hashes[i - ext_start]);
5673 sym_name = (char *) cmse_hash->root.root.root.string;
5674
5675 /* Not a special symbol. */
5676 if (!ARM_GET_SYM_CMSE_SPCL (cmse_hash->root.target_internal))
5677 continue;
5678
5679 /* Special symbol has incorrect binding or type. */
5680 if ((cmse_hash->root.root.type != bfd_link_hash_defined
5681 && cmse_hash->root.root.type != bfd_link_hash_defweak)
5682 || cmse_hash->root.type != STT_FUNC)
5683 cmse_invalid = TRUE;
5684 }
5685
5686 if (!is_v8m)
5687 {
4eca0228
AM		 5688 _bfd_error_handler (_("%B: Special symbol `%s' only allowed for "
5689 "ARMv8-M architecture or later."),
5690 input_bfd, sym_name);
4ba2ef8f
TP		 5691 is_v8m = TRUE; /* Avoid multiple warning. */
5692 ret = FALSE;
5693 }
5694
5695 if (cmse_invalid)
5696 {
4eca0228
AM		 5697 _bfd_error_handler (_("%B: invalid special symbol `%s'."),
5698 input_bfd, sym_name);
5699 _bfd_error_handler (_("It must be a global or weak function "
5700 "symbol."));
4ba2ef8f
TP		 5701 ret = FALSE;
5702 if (i < ext_start)
5703 continue;
5704 }
5705
5706 sym_name += strlen (CMSE_PREFIX);
5707 hash = (struct elf32_arm_link_hash_entry *)
5708 elf_link_hash_lookup (&(htab)->root, sym_name, FALSE, FALSE, TRUE);
5709
5710 /* No associated normal symbol or it is neither global nor weak. */
5711 if (!hash
5712 || (hash->root.root.type != bfd_link_hash_defined
5713 && hash->root.root.type != bfd_link_hash_defweak)
5714 || hash->root.type != STT_FUNC)
5715 {
5716 /* Initialize here to avoid warning about use of possibly
5717 uninitialized variable. */
5718 j = 0;
5719
5720 if (!hash)
5721 {
5722 /* Searching for a normal symbol with local binding. */
5723 for (; j < ext_start; j++)
5724 {
5725 lsym_name =
5726 bfd_elf_string_from_elf_section (input_bfd,
5727 symtab_hdr->sh_link,
5728 local_syms[j].st_name);
5729 if (!strcmp (sym_name, lsym_name))
5730 break;
5731 }
5732 }
5733
5734 if (hash || j < ext_start)
5735 {
4eca0228 5736 _bfd_error_handler
4ba2ef8f 5737 (_("%B: invalid standard symbol `%s'."), input_bfd, sym_name);
4eca0228 5738 _bfd_error_handler
4ba2ef8f
TP		 5739 (_("It must be a global or weak function symbol."));
5740 }
5741 else
4eca0228 5742 _bfd_error_handler
4ba2ef8f
TP		 5743 (_("%B: absent standard symbol `%s'."), input_bfd, sym_name);
5744 ret = FALSE;
5745 if (!hash)
5746 continue;
5747 }
5748
5749 sym_value = hash->root.root.u.def.value;
5750 section = hash->root.root.u.def.section;
5751
5752 if (cmse_hash->root.root.u.def.section != section)
5753 {
4eca0228 5754 _bfd_error_handler
4ba2ef8f
TP		 5755 (_("%B: `%s' and its special symbol are in different sections."),
5756 input_bfd, sym_name);
5757 ret = FALSE;
5758 }
5759 if (cmse_hash->root.root.u.def.value != sym_value)
5760 continue; /* Ignore: could be an entry function starting with SG. */
5761
5762 /* If this section is a link-once section that will be discarded, then
5763 don't create any stubs. */
5764 if (section->output_section == NULL)
5765 {
4eca0228 5766 _bfd_error_handler
4ba2ef8f
TP		 5767 (_("%B: entry function `%s' not output."), input_bfd, sym_name);
5768 continue;
5769 }
5770
5771 if (hash->root.size == 0)
5772 {
4eca0228 5773 _bfd_error_handler
4ba2ef8f
TP		 5774 (_("%B: entry function `%s' is empty."), input_bfd, sym_name);
5775 ret = FALSE;
5776 }
5777
5778 if (!ret)
5779 continue;
5780 branch_type = ARM_GET_SYM_BRANCH_TYPE (hash->root.target_internal);
0955507f 5781 stub_entry
4ba2ef8f
TP		 5782 = elf32_arm_create_stub (htab, arm_stub_cmse_branch_thumb_only,
5783 NULL, NULL, section, hash, sym_name,
5784 sym_value, branch_type, &new_stub);
5785
0955507f 5786 if (stub_entry == NULL)
4ba2ef8f
TP		 5787 ret = FALSE;
5788 else
5789 {
5790 BFD_ASSERT (new_stub);
0955507f 5791 (*cmse_stub_created)++;
4ba2ef8f
TP		 5792 }
5793 }
5794
5795 if (!symtab_hdr->contents)
5796 free (local_syms);
5797 return ret;
5798}
5799
0955507f
TP		 5800/* Return TRUE iff a symbol identified by its linker HASH entry is a secure
5801 code entry function, ie can be called from non secure code without using a
5802 veneer. */
5803
5804static bfd_boolean
5805cmse_entry_fct_p (struct elf32_arm_link_hash_entry *hash)
5806{
42484486 5807 bfd_byte contents[4];
0955507f
TP		 5808 uint32_t first_insn;
5809 asection *section;
5810 file_ptr offset;
5811 bfd *abfd;
5812
5813 /* Defined symbol of function type. */
5814 if (hash->root.root.type != bfd_link_hash_defined
5815 && hash->root.root.type != bfd_link_hash_defweak)
5816 return FALSE;
5817 if (hash->root.type != STT_FUNC)
5818 return FALSE;
5819
5820 /* Read first instruction. */
5821 section = hash->root.root.u.def.section;
5822 abfd = section->owner;
5823 offset = hash->root.root.u.def.value - section->vma;
42484486
TP		 5824 if (!bfd_get_section_contents (abfd, section, contents, offset,
5825 sizeof (contents)))
0955507f
TP		 5826 return FALSE;
5827
42484486
TP		 5828 first_insn = bfd_get_32 (abfd, contents);
5829
5830 /* Starts by SG instruction. */
0955507f
TP		 5831 return first_insn == 0xe97fe97f;
5832}
5833
5834/* Output the name (in symbol table) of the veneer GEN_ENTRY if it is a new
5835 secure gateway veneers (ie. the veneers was not in the input import library)
5836 and there is no output import library (GEN_INFO->out_implib_bfd is NULL. */
5837
5838static bfd_boolean
5839arm_list_new_cmse_stub (struct bfd_hash_entry *gen_entry, void *gen_info)
5840{
5841 struct elf32_arm_stub_hash_entry *stub_entry;
5842 struct bfd_link_info *info;
5843
5844 /* Massage our args to the form they really have. */
5845 stub_entry = (struct elf32_arm_stub_hash_entry *) gen_entry;
5846 info = (struct bfd_link_info *) gen_info;
5847
5848 if (info->out_implib_bfd)
5849 return TRUE;
5850
5851 if (stub_entry->stub_type != arm_stub_cmse_branch_thumb_only)
5852 return TRUE;
5853
5854 if (stub_entry->stub_offset == (bfd_vma) -1)
4eca0228 5855 _bfd_error_handler (" %s", stub_entry->output_name);
0955507f
TP		 5856
5857 return TRUE;
5858}
5859
5860/* Set offset of each secure gateway veneers so that its address remain
5861 identical to the one in the input import library referred by
5862 HTAB->in_implib_bfd. A warning is issued for veneers that disappeared
5863 (present in input import library but absent from the executable being
5864 linked) or if new veneers appeared and there is no output import library
5865 (INFO->out_implib_bfd is NULL and *CMSE_STUB_CREATED is bigger than the
5866 number of secure gateway veneers found in the input import library.
5867
5868 The function returns whether an error occurred. If no error occurred,
5869 *CMSE_STUB_CREATED gives the number of SG veneers created by both cmse_scan
5870 and this function and HTAB->new_cmse_stub_offset is set to the biggest
5871 veneer observed set for new veneers to be layed out after. */
5872
5873static bfd_boolean
5874set_cmse_veneer_addr_from_implib (struct bfd_link_info *info,
5875 struct elf32_arm_link_hash_table *htab,
5876 int *cmse_stub_created)
5877{
5878 long symsize;
5879 char *sym_name;
5880 flagword flags;
5881 long i, symcount;
5882 bfd *in_implib_bfd;
5883 asection *stub_out_sec;
5884 bfd_boolean ret = TRUE;
5885 Elf_Internal_Sym *intsym;
5886 const char *out_sec_name;
5887 bfd_size_type cmse_stub_size;
5888 asymbol **sympp = NULL, *sym;
5889 struct elf32_arm_link_hash_entry *hash;
5890 const insn_sequence *cmse_stub_template;
5891 struct elf32_arm_stub_hash_entry *stub_entry;
5892 int cmse_stub_template_size, new_cmse_stubs_created = *cmse_stub_created;
5893 bfd_vma veneer_value, stub_offset, next_cmse_stub_offset;
5894 bfd_vma cmse_stub_array_start = (bfd_vma) -1, cmse_stub_sec_vma = 0;
5895
5896 /* No input secure gateway import library. */
5897 if (!htab->in_implib_bfd)
5898 return TRUE;
5899
5900 in_implib_bfd = htab->in_implib_bfd;
5901 if (!htab->cmse_implib)
5902 {
4eca0228
AM		 5903 _bfd_error_handler (_("%B: --in-implib only supported for Secure "
5904 "Gateway import libraries."), in_implib_bfd);
0955507f
TP		 5905 return FALSE;
5906 }
5907
5908 /* Get symbol table size. */
5909 symsize = bfd_get_symtab_upper_bound (in_implib_bfd);
5910 if (symsize < 0)
5911 return FALSE;
5912
5913 /* Read in the input secure gateway import library's symbol table. */
5914 sympp = (asymbol **) xmalloc (symsize);
5915 symcount = bfd_canonicalize_symtab (in_implib_bfd, sympp);
5916 if (symcount < 0)
5917 {
5918 ret = FALSE;
5919 goto free_sym_buf;
5920 }
5921
5922 htab->new_cmse_stub_offset = 0;
5923 cmse_stub_size =
5924 find_stub_size_and_template (arm_stub_cmse_branch_thumb_only,
5925 &cmse_stub_template,
5926 &cmse_stub_template_size);
5927 out_sec_name =
5928 arm_dedicated_stub_output_section_name (arm_stub_cmse_branch_thumb_only);
5929 stub_out_sec =
5930 bfd_get_section_by_name (htab->obfd, out_sec_name);
5931 if (stub_out_sec != NULL)
5932 cmse_stub_sec_vma = stub_out_sec->vma;
5933
5934 /* Set addresses of veneers mentionned in input secure gateway import
5935 library's symbol table. */
5936 for (i = 0; i < symcount; i++)
5937 {
5938 sym = sympp[i];
5939 flags = sym->flags;
5940 sym_name = (char *) bfd_asymbol_name (sym);
5941 intsym = &((elf_symbol_type *) sym)->internal_elf_sym;
5942
5943 if (sym->section != bfd_abs_section_ptr
5944 || !(flags & (BSF_GLOBAL | BSF_WEAK))
5945 || (flags & BSF_FUNCTION) != BSF_FUNCTION
5946 || (ARM_GET_SYM_BRANCH_TYPE (intsym->st_target_internal)
5947 != ST_BRANCH_TO_THUMB))
5948 {
4eca0228
AM		 5949 _bfd_error_handler (_("%B: invalid import library entry: `%s'."),
5950 in_implib_bfd, sym_name);
5951 _bfd_error_handler (_("Symbol should be absolute, global and "
5952 "refer to Thumb functions."));
0955507f
TP		 5953 ret = FALSE;
5954 continue;
5955 }
5956
5957 veneer_value = bfd_asymbol_value (sym);
5958 stub_offset = veneer_value - cmse_stub_sec_vma;
5959 stub_entry = arm_stub_hash_lookup (&htab->stub_hash_table, sym_name,
5960 FALSE, FALSE);
5961 hash = (struct elf32_arm_link_hash_entry *)
5962 elf_link_hash_lookup (&(htab)->root, sym_name, FALSE, FALSE, TRUE);
5963
5964 /* Stub entry should have been created by cmse_scan or the symbol be of
5965 a secure function callable from non secure code. */
5966 if (!stub_entry && !hash)
5967 {
5968 bfd_boolean new_stub;
5969
4eca0228 5970 _bfd_error_handler
0955507f
TP		 5971 (_("Entry function `%s' disappeared from secure code."), sym_name);
5972 hash = (struct elf32_arm_link_hash_entry *)
5973 elf_link_hash_lookup (&(htab)->root, sym_name, TRUE, TRUE, TRUE);
5974 stub_entry
5975 = elf32_arm_create_stub (htab, arm_stub_cmse_branch_thumb_only,
5976 NULL, NULL, bfd_abs_section_ptr, hash,
5977 sym_name, veneer_value,
5978 ST_BRANCH_TO_THUMB, &new_stub);
5979 if (stub_entry == NULL)
5980 ret = FALSE;
5981 else
5982 {
5983 BFD_ASSERT (new_stub);
5984 new_cmse_stubs_created++;
5985 (*cmse_stub_created)++;
5986 }
5987 stub_entry->stub_template_size = stub_entry->stub_size = 0;
5988 stub_entry->stub_offset = stub_offset;
5989 }
5990 /* Symbol found is not callable from non secure code. */
5991 else if (!stub_entry)
5992 {
5993 if (!cmse_entry_fct_p (hash))
5994 {
4eca0228
AM		 5995 _bfd_error_handler (_("`%s' refers to a non entry function."),
5996 sym_name);
0955507f
TP		 5997 ret = FALSE;
5998 }
5999 continue;
6000 }
6001 else
6002 {
6003 /* Only stubs for SG veneers should have been created. */
6004 BFD_ASSERT (stub_entry->stub_type == arm_stub_cmse_branch_thumb_only);
6005
6006 /* Check visibility hasn't changed. */
6007 if (!!(flags & BSF_GLOBAL)
6008 != (hash->root.root.type == bfd_link_hash_defined))
4eca0228 6009 _bfd_error_handler
0955507f
TP		 6010 (_("%B: visibility of symbol `%s' has changed."), in_implib_bfd,
6011 sym_name);
6012
6013 stub_entry->stub_offset = stub_offset;
6014 }
6015
6016 /* Size should match that of a SG veneer. */
6017 if (intsym->st_size != cmse_stub_size)
6018 {
4eca0228
AM		 6019 _bfd_error_handler (_("%B: incorrect size for symbol `%s'."),
6020 in_implib_bfd, sym_name);
0955507f
TP		 6021 ret = FALSE;
6022 }
6023
6024 /* Previous veneer address is before current SG veneer section. */
6025 if (veneer_value < cmse_stub_sec_vma)
6026 {
6027 /* Avoid offset underflow. */
6028 if (stub_entry)
6029 stub_entry->stub_offset = 0;
6030 stub_offset = 0;
6031 ret = FALSE;
6032 }
6033
6034 /* Complain if stub offset not a multiple of stub size. */
6035 if (stub_offset % cmse_stub_size)
6036 {
4eca0228 6037 _bfd_error_handler
0955507f
TP		 6038 (_("Offset of veneer for entry function `%s' not a multiple of "
6039 "its size."), sym_name);
6040 ret = FALSE;
6041 }
6042
6043 if (!ret)
6044 continue;
6045
6046 new_cmse_stubs_created--;
6047 if (veneer_value < cmse_stub_array_start)
6048 cmse_stub_array_start = veneer_value;
6049 next_cmse_stub_offset = stub_offset + ((cmse_stub_size + 7) & ~7);
6050 if (next_cmse_stub_offset > htab->new_cmse_stub_offset)
6051 htab->new_cmse_stub_offset = next_cmse_stub_offset;
6052 }
6053
6054 if (!info->out_implib_bfd && new_cmse_stubs_created != 0)
6055 {
6056 BFD_ASSERT (new_cmse_stubs_created > 0);
4eca0228 6057 _bfd_error_handler
0955507f
TP		 6058 (_("new entry function(s) introduced but no output import library "
6059 "specified:"));
6060 bfd_hash_traverse (&htab->stub_hash_table, arm_list_new_cmse_stub, info);
6061 }
6062
6063 if (cmse_stub_array_start != cmse_stub_sec_vma)
6064 {
4eca0228 6065 _bfd_error_handler
0955507f
TP		 6066 (_("Start address of `%s' is different from previous link."),
6067 out_sec_name);
6068 ret = FALSE;
6069 }
6070
6071free_sym_buf:
6072 free (sympp);
6073 return ret;
6074}
6075
906e58ca
NC		 6076/* Determine and set the size of the stub section for a final link.
6077
6078 The basic idea here is to examine all the relocations looking for
6079 PC-relative calls to a target that is unreachable with a "bl"
6080 instruction. */
6081
6082bfd_boolean
6083elf32_arm_size_stubs (bfd *output_bfd,
6084 bfd *stub_bfd,
6085 struct bfd_link_info *info,
6086 bfd_signed_vma group_size,
7a89b94e 6087 asection * (*add_stub_section) (const char *, asection *,
6bde4c52 6088 asection *,
7a89b94e 6089 unsigned int),
906e58ca
NC		 6090 void (*layout_sections_again) (void))
6091{
0955507f 6092 bfd_boolean ret = TRUE;
4ba2ef8f 6093 obj_attribute *out_attr;
0955507f 6094 int cmse_stub_created = 0;
906e58ca 6095 bfd_size_type stub_group_size;
4ba2ef8f 6096 bfd_boolean m_profile, stubs_always_after_branch, first_veneer_scan = TRUE;
906e58ca 6097 struct elf32_arm_link_hash_table *htab = elf32_arm_hash_table (info);
48229727 6098 struct a8_erratum_fix *a8_fixes = NULL;
eb7c4339 6099 unsigned int num_a8_fixes = 0, a8_fix_table_size = 10;
48229727
JB		 6100 struct a8_erratum_reloc *a8_relocs = NULL;
6101 unsigned int num_a8_relocs = 0, a8_reloc_table_size = 10, i;
6102
4dfe6ac6
NC		 6103 if (htab == NULL)
6104 return FALSE;
6105
48229727
JB		 6106 if (htab->fix_cortex_a8)
6107 {
21d799b5 6108 a8_fixes = (struct a8_erratum_fix *)
99059e56 6109 bfd_zmalloc (sizeof (struct a8_erratum_fix) * a8_fix_table_size);
21d799b5 6110 a8_relocs = (struct a8_erratum_reloc *)
99059e56 6111 bfd_zmalloc (sizeof (struct a8_erratum_reloc) * a8_reloc_table_size);
48229727 6112 }
906e58ca
NC		 6113
6114 /* Propagate mach to stub bfd, because it may not have been
6115 finalized when we created stub_bfd. */
6116 bfd_set_arch_mach (stub_bfd, bfd_get_arch (output_bfd),
6117 bfd_get_mach (output_bfd));
6118
6119 /* Stash our params away. */
6120 htab->stub_bfd = stub_bfd;
6121 htab->add_stub_section = add_stub_section;
6122 htab->layout_sections_again = layout_sections_again;
07d72278 6123 stubs_always_after_branch = group_size < 0;
48229727 6124
4ba2ef8f
TP		 6125 out_attr = elf_known_obj_attributes_proc (output_bfd);
6126 m_profile = out_attr[Tag_CPU_arch_profile].i == 'M';
0955507f 6127
48229727
JB		 6128 /* The Cortex-A8 erratum fix depends on stubs not being in the same 4K page
6129 as the first half of a 32-bit branch straddling two 4K pages. This is a
6130 crude way of enforcing that. */
6131 if (htab->fix_cortex_a8)
6132 stubs_always_after_branch = 1;
6133
906e58ca
NC		 6134 if (group_size < 0)
6135 stub_group_size = -group_size;
6136 else
6137 stub_group_size = group_size;
6138
6139 if (stub_group_size == 1)
6140 {
6141 /* Default values. */
6142 /* Thumb branch range is +-4MB has to be used as the default
6143 maximum size (a given section can contain both ARM and Thumb
6144 code, so the worst case has to be taken into account).
6145
6146 This value is 24K less than that, which allows for 2025
6147 12-byte stubs. If we exceed that, then we will fail to link.
6148 The user will have to relink with an explicit group size
6149 option. */
6150 stub_group_size = 4170000;
6151 }
6152
07d72278 6153 group_sections (htab, stub_group_size, stubs_always_after_branch);
906e58ca 6154
3ae046cc
NS		 6155 /* If we're applying the cortex A8 fix, we need to determine the
6156 program header size now, because we cannot change it later --
6157 that could alter section placements. Notice the A8 erratum fix
6158 ends up requiring the section addresses to remain unchanged
6159 modulo the page size. That's something we cannot represent
6160 inside BFD, and we don't want to force the section alignment to
6161 be the page size. */
6162 if (htab->fix_cortex_a8)
6163 (*htab->layout_sections_again) ();
6164
906e58ca
NC		 6165 while (1)
6166 {
6167 bfd *input_bfd;
6168 unsigned int bfd_indx;
6169 asection *stub_sec;
d7c5bd02 6170 enum elf32_arm_stub_type stub_type;
eb7c4339
NS		 6171 bfd_boolean stub_changed = FALSE;
6172 unsigned prev_num_a8_fixes = num_a8_fixes;
906e58ca 6173
48229727 6174 num_a8_fixes = 0;
906e58ca
NC		 6175 for (input_bfd = info->input_bfds, bfd_indx = 0;
6176 input_bfd != NULL;
c72f2fb2 6177 input_bfd = input_bfd->link.next, bfd_indx++)
906e58ca
NC		 6178 {
6179 Elf_Internal_Shdr *symtab_hdr;
6180 asection *section;
6181 Elf_Internal_Sym *local_syms = NULL;
6182
99059e56
RM		 6183 if (!is_arm_elf (input_bfd))
6184 continue;
adbcc655 6185
48229727
JB		 6186 num_a8_relocs = 0;
6187
906e58ca
NC		 6188 /* We'll need the symbol table in a second. */
6189 symtab_hdr = &elf_tdata (input_bfd)->symtab_hdr;
6190 if (symtab_hdr->sh_info == 0)
6191 continue;
6192
4ba2ef8f
TP		 6193 /* Limit scan of symbols to object file whose profile is
6194 Microcontroller to not hinder performance in the general case. */
6195 if (m_profile && first_veneer_scan)
6196 {
6197 struct elf_link_hash_entry **sym_hashes;
6198
6199 sym_hashes = elf_sym_hashes (input_bfd);
6200 if (!cmse_scan (input_bfd, htab, out_attr, sym_hashes,
0955507f 6201 &cmse_stub_created))
4ba2ef8f 6202 goto error_ret_free_local;
0955507f
TP		 6203
6204 if (cmse_stub_created != 0)
6205 stub_changed = TRUE;
4ba2ef8f
TP		 6206 }
6207
906e58ca
NC		 6208 /* Walk over each section attached to the input bfd. */
6209 for (section = input_bfd->sections;
6210 section != NULL;
6211 section = section->next)
6212 {
6213 Elf_Internal_Rela *internal_relocs, *irelaend, *irela;
6214
6215 /* If there aren't any relocs, then there's nothing more
6216 to do. */
6217 if ((section->flags & SEC_RELOC) == 0
6218 || section->reloc_count == 0
6219 || (section->flags & SEC_CODE) == 0)
6220 continue;
6221
6222 /* If this section is a link-once section that will be
6223 discarded, then don't create any stubs. */
6224 if (section->output_section == NULL
6225 || section->output_section->owner != output_bfd)
6226 continue;
6227
6228 /* Get the relocs. */
6229 internal_relocs
6230 = _bfd_elf_link_read_relocs (input_bfd, section, NULL,
6231 NULL, info->keep_memory);
6232 if (internal_relocs == NULL)
6233 goto error_ret_free_local;
6234
6235 /* Now examine each relocation. */
6236 irela = internal_relocs;
6237 irelaend = irela + section->reloc_count;
6238 for (; irela < irelaend; irela++)
6239 {
6240 unsigned int r_type, r_indx;
906e58ca
NC		 6241 asection *sym_sec;
6242 bfd_vma sym_value;
6243 bfd_vma destination;
6244 struct elf32_arm_link_hash_entry *hash;
7413f23f 6245 const char *sym_name;
34e77a92 6246 unsigned char st_type;
35fc36a8 6247 enum arm_st_branch_type branch_type;
48229727 6248 bfd_boolean created_stub = FALSE;
906e58ca
NC		 6249
6250 r_type = ELF32_R_TYPE (irela->r_info);
6251 r_indx = ELF32_R_SYM (irela->r_info);
6252
6253 if (r_type >= (unsigned int) R_ARM_max)
6254 {
6255 bfd_set_error (bfd_error_bad_value);
6256 error_ret_free_internal:
6257 if (elf_section_data (section)->relocs == NULL)
6258 free (internal_relocs);
15dd01b1
TP		 6259 /* Fall through. */
6260 error_ret_free_local:
6261 if (local_syms != NULL
6262 && (symtab_hdr->contents
6263 != (unsigned char *) local_syms))
6264 free (local_syms);
6265 return FALSE;
906e58ca 6266 }
b38cadfb 6267
0855e32b
NS		 6268 hash = NULL;
6269 if (r_indx >= symtab_hdr->sh_info)
6270 hash = elf32_arm_hash_entry
6271 (elf_sym_hashes (input_bfd)
6272 [r_indx - symtab_hdr->sh_info]);
b38cadfb 6273
0855e32b
NS		 6274 /* Only look for stubs on branch instructions, or
6275 non-relaxed TLSCALL */
906e58ca 6276 if ((r_type != (unsigned int) R_ARM_CALL)
155d87d7
CL		 6277 && (r_type != (unsigned int) R_ARM_THM_CALL)
6278 && (r_type != (unsigned int) R_ARM_JUMP24)
48229727
JB		 6279 && (r_type != (unsigned int) R_ARM_THM_JUMP19)
6280 && (r_type != (unsigned int) R_ARM_THM_XPC22)
155d87d7 6281 && (r_type != (unsigned int) R_ARM_THM_JUMP24)
0855e32b
NS		 6282 && (r_type != (unsigned int) R_ARM_PLT32)
6283 && !((r_type == (unsigned int) R_ARM_TLS_CALL
6284 || r_type == (unsigned int) R_ARM_THM_TLS_CALL)
6285 && r_type == elf32_arm_tls_transition
6286 (info, r_type, &hash->root)
6287 && ((hash ? hash->tls_type
6288 : (elf32_arm_local_got_tls_type
6289 (input_bfd)[r_indx]))
6290 & GOT_TLS_GDESC) != 0))
906e58ca
NC		 6291 continue;
6292
6293 /* Now determine the call target, its name, value,
6294 section. */
6295 sym_sec = NULL;
6296 sym_value = 0;
6297 destination = 0;
7413f23f 6298 sym_name = NULL;
b38cadfb 6299
0855e32b
NS		 6300 if (r_type == (unsigned int) R_ARM_TLS_CALL
6301 || r_type == (unsigned int) R_ARM_THM_TLS_CALL)
6302 {
6303 /* A non-relaxed TLS call. The target is the
6304 plt-resident trampoline and nothing to do
6305 with the symbol. */
6306 BFD_ASSERT (htab->tls_trampoline > 0);
6307 sym_sec = htab->root.splt;
6308 sym_value = htab->tls_trampoline;
6309 hash = 0;
34e77a92 6310 st_type = STT_FUNC;
35fc36a8 6311 branch_type = ST_BRANCH_TO_ARM;
0855e32b
NS		 6312 }
6313 else if (!hash)
906e58ca
NC		 6314 {
6315 /* It's a local symbol. */
6316 Elf_Internal_Sym *sym;
906e58ca
NC		 6317
6318 if (local_syms == NULL)
6319 {
6320 local_syms
6321 = (Elf_Internal_Sym *) symtab_hdr->contents;
6322 if (local_syms == NULL)
6323 local_syms
6324 = bfd_elf_get_elf_syms (input_bfd, symtab_hdr,
6325 symtab_hdr->sh_info, 0,
6326 NULL, NULL, NULL);
6327 if (local_syms == NULL)
6328 goto error_ret_free_internal;
6329 }
6330
6331 sym = local_syms + r_indx;
f6d250ce
TS		 6332 if (sym->st_shndx == SHN_UNDEF)
6333 sym_sec = bfd_und_section_ptr;
6334 else if (sym->st_shndx == SHN_ABS)
6335 sym_sec = bfd_abs_section_ptr;
6336 else if (sym->st_shndx == SHN_COMMON)
6337 sym_sec = bfd_com_section_ptr;
6338 else
6339 sym_sec =
6340 bfd_section_from_elf_index (input_bfd, sym->st_shndx);
6341
ffcb4889
NS		 6342 if (!sym_sec)
6343 /* This is an undefined symbol. It can never
6a631e86 6344 be resolved. */
ffcb4889 6345 continue;
fe33d2fa 6346
906e58ca
NC		 6347 if (ELF_ST_TYPE (sym->st_info) != STT_SECTION)
6348 sym_value = sym->st_value;
6349 destination = (sym_value + irela->r_addend
6350 + sym_sec->output_offset
6351 + sym_sec->output_section->vma);
34e77a92 6352 st_type = ELF_ST_TYPE (sym->st_info);
39d911fc
TP		 6353 branch_type =
6354 ARM_GET_SYM_BRANCH_TYPE (sym->st_target_internal);
7413f23f
DJ		 6355 sym_name
6356 = bfd_elf_string_from_elf_section (input_bfd,
6357 symtab_hdr->sh_link,
6358 sym->st_name);
906e58ca
NC		 6359 }
6360 else
6361 {
6362 /* It's an external symbol. */
906e58ca
NC		 6363 while (hash->root.root.type == bfd_link_hash_indirect
6364 || hash->root.root.type == bfd_link_hash_warning)
6365 hash = ((struct elf32_arm_link_hash_entry *)
6366 hash->root.root.u.i.link);
6367
6368 if (hash->root.root.type == bfd_link_hash_defined
6369 || hash->root.root.type == bfd_link_hash_defweak)
6370 {
6371 sym_sec = hash->root.root.u.def.section;
6372 sym_value = hash->root.root.u.def.value;
022f8312
CL		 6373
6374 struct elf32_arm_link_hash_table *globals =
6375 elf32_arm_hash_table (info);
6376
6377 /* For a destination in a shared library,
6378 use the PLT stub as target address to
6379 decide whether a branch stub is
6380 needed. */
4dfe6ac6 6381 if (globals != NULL
362d30a1 6382 && globals->root.splt != NULL
4dfe6ac6 6383 && hash != NULL
022f8312
CL		 6384 && hash->root.plt.offset != (bfd_vma) -1)
6385 {
362d30a1 6386 sym_sec = globals->root.splt;
022f8312
CL		 6387 sym_value = hash->root.plt.offset;
6388 if (sym_sec->output_section != NULL)
6389 destination = (sym_value
6390 + sym_sec->output_offset
6391 + sym_sec->output_section->vma);
6392 }
6393 else if (sym_sec->output_section != NULL)
906e58ca
NC		 6394 destination = (sym_value + irela->r_addend
6395 + sym_sec->output_offset
6396 + sym_sec->output_section->vma);
6397 }
69c5861e
CL		 6398 else if ((hash->root.root.type == bfd_link_hash_undefined)
6399 || (hash->root.root.type == bfd_link_hash_undefweak))
6400 {
6401 /* For a shared library, use the PLT stub as
6402 target address to decide whether a long
6403 branch stub is needed.
6404 For absolute code, they cannot be handled. */
6405 struct elf32_arm_link_hash_table *globals =
6406 elf32_arm_hash_table (info);
6407
4dfe6ac6 6408 if (globals != NULL
362d30a1 6409 && globals->root.splt != NULL
4dfe6ac6 6410 && hash != NULL
69c5861e
CL		 6411 && hash->root.plt.offset != (bfd_vma) -1)
6412 {
362d30a1 6413 sym_sec = globals->root.splt;
69c5861e
CL		 6414 sym_value = hash->root.plt.offset;
6415 if (sym_sec->output_section != NULL)
6416 destination = (sym_value
6417 + sym_sec->output_offset
6418 + sym_sec->output_section->vma);
6419 }
6420 else
6421 continue;
6422 }
906e58ca
NC		 6423 else
6424 {
6425 bfd_set_error (bfd_error_bad_value);
6426 goto error_ret_free_internal;
6427 }
34e77a92 6428 st_type = hash->root.type;
39d911fc
TP		 6429 branch_type =
6430 ARM_GET_SYM_BRANCH_TYPE (hash->root.target_internal);
7413f23f 6431 sym_name = hash->root.root.root.string;
906e58ca
NC		 6432 }
6433
48229727 6434 do
7413f23f 6435 {
b715f643 6436 bfd_boolean new_stub;
0955507f 6437 struct elf32_arm_stub_hash_entry *stub_entry;
b715f643 6438
48229727
JB		 6439 /* Determine what (if any) linker stub is needed. */
6440 stub_type = arm_type_of_stub (info, section, irela,
34e77a92
RS		 6441 st_type, &branch_type,
6442 hash, destination, sym_sec,
48229727
JB		 6443 input_bfd, sym_name);
6444 if (stub_type == arm_stub_none)
6445 break;
6446
48229727
JB		 6447 /* We've either created a stub for this reloc already,
6448 or we are about to. */
0955507f 6449 stub_entry =
b715f643
TP		 6450 elf32_arm_create_stub (htab, stub_type, section, irela,
6451 sym_sec, hash,
6452 (char *) sym_name, sym_value,
6453 branch_type, &new_stub);
7413f23f 6454
0955507f 6455 created_stub = stub_entry != NULL;
b715f643
TP		 6456 if (!created_stub)
6457 goto error_ret_free_internal;
6458 else if (!new_stub)
6459 break;
99059e56 6460 else
b715f643 6461 stub_changed = TRUE;
99059e56
RM		 6462 }
6463 while (0);
6464
6465 /* Look for relocations which might trigger Cortex-A8
6466 erratum. */
6467 if (htab->fix_cortex_a8
6468 && (r_type == (unsigned int) R_ARM_THM_JUMP24
6469 || r_type == (unsigned int) R_ARM_THM_JUMP19
6470 || r_type == (unsigned int) R_ARM_THM_CALL
6471 || r_type == (unsigned int) R_ARM_THM_XPC22))
6472 {
6473 bfd_vma from = section->output_section->vma
6474 + section->output_offset
6475 + irela->r_offset;
6476
6477 if ((from & 0xfff) == 0xffe)
6478 {
6479 /* Found a candidate. Note we haven't checked the
6480 destination is within 4K here: if we do so (and
6481 don't create an entry in a8_relocs) we can't tell
6482 that a branch should have been relocated when
6483 scanning later. */
6484 if (num_a8_relocs == a8_reloc_table_size)
6485 {
6486 a8_reloc_table_size *= 2;
6487 a8_relocs = (struct a8_erratum_reloc *)
6488 bfd_realloc (a8_relocs,
6489 sizeof (struct a8_erratum_reloc)
6490 * a8_reloc_table_size);
6491 }
6492
6493 a8_relocs[num_a8_relocs].from = from;
6494 a8_relocs[num_a8_relocs].destination = destination;
6495 a8_relocs[num_a8_relocs].r_type = r_type;
6496 a8_relocs[num_a8_relocs].branch_type = branch_type;
6497 a8_relocs[num_a8_relocs].sym_name = sym_name;
6498 a8_relocs[num_a8_relocs].non_a8_stub = created_stub;
6499 a8_relocs[num_a8_relocs].hash = hash;
6500
6501 num_a8_relocs++;
6502 }
6503 }
906e58ca
NC		 6504 }
6505
99059e56
RM		 6506 /* We're done with the internal relocs, free them. */
6507 if (elf_section_data (section)->relocs == NULL)
6508 free (internal_relocs);
6509 }
48229727 6510
99059e56 6511 if (htab->fix_cortex_a8)
48229727 6512 {
99059e56
RM		 6513 /* Sort relocs which might apply to Cortex-A8 erratum. */
6514 qsort (a8_relocs, num_a8_relocs,
eb7c4339 6515 sizeof (struct a8_erratum_reloc),
99059e56 6516 &a8_reloc_compare);
48229727 6517
99059e56
RM		 6518 /* Scan for branches which might trigger Cortex-A8 erratum. */
6519 if (cortex_a8_erratum_scan (input_bfd, info, &a8_fixes,
48229727 6520 &num_a8_fixes, &a8_fix_table_size,
eb7c4339
NS		 6521 a8_relocs, num_a8_relocs,
6522 prev_num_a8_fixes, &stub_changed)
6523 != 0)
48229727 6524 goto error_ret_free_local;
5e681ec4 6525 }
7f991970
AM		 6526
6527 if (local_syms != NULL
6528 && symtab_hdr->contents != (unsigned char *) local_syms)
6529 {
6530 if (!info->keep_memory)
6531 free (local_syms);
6532 else
6533 symtab_hdr->contents = (unsigned char *) local_syms;
6534 }
5e681ec4
PB		 6535 }
6536
0955507f
TP		 6537 if (first_veneer_scan
6538 && !set_cmse_veneer_addr_from_implib (info, htab,
6539 &cmse_stub_created))
6540 ret = FALSE;
6541
eb7c4339 6542 if (prev_num_a8_fixes != num_a8_fixes)
99059e56 6543 stub_changed = TRUE;
48229727 6544
906e58ca
NC		 6545 if (!stub_changed)
6546 break;
5e681ec4 6547
906e58ca
NC		 6548 /* OK, we've added some stubs. Find out the new size of the
6549 stub sections. */
6550 for (stub_sec = htab->stub_bfd->sections;
6551 stub_sec != NULL;
6552 stub_sec = stub_sec->next)
3e6b1042
DJ		 6553 {
6554 /* Ignore non-stub sections. */
6555 if (!strstr (stub_sec->name, STUB_SUFFIX))
6556 continue;
6557
6558 stub_sec->size = 0;
6559 }
b34b2d70 6560
0955507f
TP		 6561 /* Add new SG veneers after those already in the input import
6562 library. */
6563 for (stub_type = arm_stub_none + 1; stub_type < max_stub_type;
6564 stub_type++)
6565 {
6566 bfd_vma *start_offset_p;
6567 asection **stub_sec_p;
6568
6569 start_offset_p = arm_new_stubs_start_offset_ptr (htab, stub_type);
6570 stub_sec_p = arm_dedicated_stub_input_section_ptr (htab, stub_type);
6571 if (start_offset_p == NULL)
6572 continue;
6573
6574 BFD_ASSERT (stub_sec_p != NULL);
6575 if (*stub_sec_p != NULL)
6576 (*stub_sec_p)->size = *start_offset_p;
6577 }
6578
d7c5bd02 6579 /* Compute stub section size, considering padding. */
906e58ca 6580 bfd_hash_traverse (&htab->stub_hash_table, arm_size_one_stub, htab);
d7c5bd02
TP		 6581 for (stub_type = arm_stub_none + 1; stub_type < max_stub_type;
6582 stub_type++)
6583 {
6584 int size, padding;
6585 asection **stub_sec_p;
6586
6587 padding = arm_dedicated_stub_section_padding (stub_type);
6588 stub_sec_p = arm_dedicated_stub_input_section_ptr (htab, stub_type);
6589 /* Skip if no stub input section or no stub section padding
6590 required. */
6591 if ((stub_sec_p != NULL && *stub_sec_p == NULL) || padding == 0)
6592 continue;
6593 /* Stub section padding required but no dedicated section. */
6594 BFD_ASSERT (stub_sec_p);
6595
6596 size = (*stub_sec_p)->size;
6597 size = (size + padding - 1) & ~(padding - 1);
6598 (*stub_sec_p)->size = size;
6599 }
906e58ca 6600
48229727
JB		 6601 /* Add Cortex-A8 erratum veneers to stub section sizes too. */
6602 if (htab->fix_cortex_a8)
99059e56
RM		 6603 for (i = 0; i < num_a8_fixes; i++)
6604 {
48229727 6605 stub_sec = elf32_arm_create_or_find_stub_sec (NULL,
daa4adae 6606 a8_fixes[i].section, htab, a8_fixes[i].stub_type);
48229727
JB		 6607
6608 if (stub_sec == NULL)
7f991970 6609 return FALSE;
48229727 6610
99059e56
RM		 6611 stub_sec->size
6612 += find_stub_size_and_template (a8_fixes[i].stub_type, NULL,
6613 NULL);
6614 }
48229727
JB		 6615
6616
906e58ca
NC		 6617 /* Ask the linker to do its stuff. */
6618 (*htab->layout_sections_again) ();
4ba2ef8f 6619 first_veneer_scan = FALSE;
ba93b8ac
DJ		 6620 }
6621
48229727
JB		 6622 /* Add stubs for Cortex-A8 erratum fixes now. */
6623 if (htab->fix_cortex_a8)
6624 {
6625 for (i = 0; i < num_a8_fixes; i++)
99059e56
RM		 6626 {
6627 struct elf32_arm_stub_hash_entry *stub_entry;
6628 char *stub_name = a8_fixes[i].stub_name;
6629 asection *section = a8_fixes[i].section;
6630 unsigned int section_id = a8_fixes[i].section->id;
6631 asection *link_sec = htab->stub_group[section_id].link_sec;
6632 asection *stub_sec = htab->stub_group[section_id].stub_sec;
6633 const insn_sequence *template_sequence;
6634 int template_size, size = 0;
6635
6636 stub_entry = arm_stub_hash_lookup (&htab->stub_hash_table, stub_name,
6637 TRUE, FALSE);
6638 if (stub_entry == NULL)
6639 {
4eca0228
AM		 6640 _bfd_error_handler (_("%s: cannot create stub entry %s"),
6641 section->owner, stub_name);
99059e56
RM		 6642 return FALSE;
6643 }
6644
6645 stub_entry->stub_sec = stub_sec;
0955507f 6646 stub_entry->stub_offset = (bfd_vma) -1;
99059e56
RM		 6647 stub_entry->id_sec = link_sec;
6648 stub_entry->stub_type = a8_fixes[i].stub_type;
8d9d9490 6649 stub_entry->source_value = a8_fixes[i].offset;
99059e56 6650 stub_entry->target_section = a8_fixes[i].section;
8d9d9490 6651 stub_entry->target_value = a8_fixes[i].target_offset;
99059e56 6652 stub_entry->orig_insn = a8_fixes[i].orig_insn;
35fc36a8 6653 stub_entry->branch_type = a8_fixes[i].branch_type;
48229727 6654
99059e56
RM		 6655 size = find_stub_size_and_template (a8_fixes[i].stub_type,
6656 &template_sequence,
6657 &template_size);
48229727 6658
99059e56
RM		 6659 stub_entry->stub_size = size;
6660 stub_entry->stub_template = template_sequence;
6661 stub_entry->stub_template_size = template_size;
6662 }
48229727
JB		 6663
6664 /* Stash the Cortex-A8 erratum fix array for use later in
99059e56 6665 elf32_arm_write_section(). */
48229727
JB		 6666 htab->a8_erratum_fixes = a8_fixes;
6667 htab->num_a8_erratum_fixes = num_a8_fixes;
6668 }
6669 else
6670 {
6671 htab->a8_erratum_fixes = NULL;
6672 htab->num_a8_erratum_fixes = 0;
6673 }
0955507f 6674 return ret;
5e681ec4
PB		 6675}
6676
906e58ca
NC		 6677/* Build all the stubs associated with the current output file. The
6678 stubs are kept in a hash table attached to the main linker hash
6679 table. We also set up the .plt entries for statically linked PIC
6680 functions here. This function is called via arm_elf_finish in the
6681 linker. */
252b5132 6682
906e58ca
NC		 6683bfd_boolean
6684elf32_arm_build_stubs (struct bfd_link_info *info)
252b5132 6685{
906e58ca
NC		 6686 asection *stub_sec;
6687 struct bfd_hash_table *table;
0955507f 6688 enum elf32_arm_stub_type stub_type;
906e58ca 6689 struct elf32_arm_link_hash_table *htab;
252b5132 6690
906e58ca 6691 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 6692 if (htab == NULL)
6693 return FALSE;
252b5132 6694
906e58ca
NC		 6695 for (stub_sec = htab->stub_bfd->sections;
6696 stub_sec != NULL;
6697 stub_sec = stub_sec->next)
252b5132 6698 {
906e58ca
NC		 6699 bfd_size_type size;
6700
8029a119 6701 /* Ignore non-stub sections. */
906e58ca
NC		 6702 if (!strstr (stub_sec->name, STUB_SUFFIX))
6703 continue;
6704
d7c5bd02 6705 /* Allocate memory to hold the linker stubs. Zeroing the stub sections
0955507f
TP		 6706 must at least be done for stub section requiring padding and for SG
6707 veneers to ensure that a non secure code branching to a removed SG
6708 veneer causes an error. */
906e58ca 6709 size = stub_sec->size;
21d799b5 6710 stub_sec->contents = (unsigned char *) bfd_zalloc (htab->stub_bfd, size);
906e58ca
NC		 6711 if (stub_sec->contents == NULL && size != 0)
6712 return FALSE;
0955507f 6713
906e58ca 6714 stub_sec->size = 0;
252b5132
RH		 6715 }
6716
0955507f
TP		 6717 /* Add new SG veneers after those already in the input import library. */
6718 for (stub_type = arm_stub_none + 1; stub_type < max_stub_type; stub_type++)
6719 {
6720 bfd_vma *start_offset_p;
6721 asection **stub_sec_p;
6722
6723 start_offset_p = arm_new_stubs_start_offset_ptr (htab, stub_type);
6724 stub_sec_p = arm_dedicated_stub_input_section_ptr (htab, stub_type);
6725 if (start_offset_p == NULL)
6726 continue;
6727
6728 BFD_ASSERT (stub_sec_p != NULL);
6729 if (*stub_sec_p != NULL)
6730 (*stub_sec_p)->size = *start_offset_p;
6731 }
6732
906e58ca
NC		 6733 /* Build the stubs as directed by the stub hash table. */
6734 table = &htab->stub_hash_table;
6735 bfd_hash_traverse (table, arm_build_one_stub, info);
eb7c4339
NS		 6736 if (htab->fix_cortex_a8)
6737 {
6738 /* Place the cortex a8 stubs last. */
6739 htab->fix_cortex_a8 = -1;
6740 bfd_hash_traverse (table, arm_build_one_stub, info);
6741 }
252b5132 6742
906e58ca 6743 return TRUE;
252b5132
RH		 6744}
6745
9b485d32
NC		 6746/* Locate the Thumb encoded calling stub for NAME. */
6747
252b5132 6748static struct elf_link_hash_entry *
57e8b36a
NC		 6749find_thumb_glue (struct bfd_link_info *link_info,
6750 const char *name,
f2a9dd69 6751 char **error_message)
252b5132
RH		 6752{
6753 char *tmp_name;
6754 struct elf_link_hash_entry *hash;
6755 struct elf32_arm_link_hash_table *hash_table;
6756
6757 /* We need a pointer to the armelf specific hash table. */
6758 hash_table = elf32_arm_hash_table (link_info);
4dfe6ac6
NC		 6759 if (hash_table == NULL)
6760 return NULL;
252b5132 6761
21d799b5 6762 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen (name)
99059e56 6763 + strlen (THUMB2ARM_GLUE_ENTRY_NAME) + 1);
252b5132
RH		 6764
6765 BFD_ASSERT (tmp_name);
6766
6767 sprintf (tmp_name, THUMB2ARM_GLUE_ENTRY_NAME, name);
6768
6769 hash = elf_link_hash_lookup
b34976b6 6770 (&(hash_table)->root, tmp_name, FALSE, FALSE, TRUE);
252b5132 6771
b1657152
AM		 6772 if (hash == NULL
6773 && asprintf (error_message, _("unable to find THUMB glue '%s' for '%s'"),
6774 tmp_name, name) == -1)
6775 *error_message = (char *) bfd_errmsg (bfd_error_system_call);
252b5132
RH		 6776
6777 free (tmp_name);
6778
6779 return hash;
6780}
6781
9b485d32
NC		 6782/* Locate the ARM encoded calling stub for NAME. */
6783
252b5132 6784static struct elf_link_hash_entry *
57e8b36a
NC		 6785find_arm_glue (struct bfd_link_info *link_info,
6786 const char *name,
f2a9dd69 6787 char **error_message)
252b5132
RH		 6788{
6789 char *tmp_name;
6790 struct elf_link_hash_entry *myh;
6791 struct elf32_arm_link_hash_table *hash_table;
6792
6793 /* We need a pointer to the elfarm specific hash table. */
6794 hash_table = elf32_arm_hash_table (link_info);
4dfe6ac6
NC		 6795 if (hash_table == NULL)
6796 return NULL;
252b5132 6797
21d799b5 6798 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen (name)
99059e56 6799 + strlen (ARM2THUMB_GLUE_ENTRY_NAME) + 1);
252b5132
RH		 6800
6801 BFD_ASSERT (tmp_name);
6802
6803 sprintf (tmp_name, ARM2THUMB_GLUE_ENTRY_NAME, name);
6804
6805 myh = elf_link_hash_lookup
b34976b6 6806 (&(hash_table)->root, tmp_name, FALSE, FALSE, TRUE);
252b5132 6807
b1657152
AM		 6808 if (myh == NULL
6809 && asprintf (error_message, _("unable to find ARM glue '%s' for '%s'"),
6810 tmp_name, name) == -1)
6811 *error_message = (char *) bfd_errmsg (bfd_error_system_call);
252b5132
RH		 6812
6813 free (tmp_name);
6814
6815 return myh;
6816}
6817
8f6277f5 6818/* ARM->Thumb glue (static images):
252b5132
RH		 6819
6820 .arm
6821 __func_from_arm:
6822 ldr r12, __func_addr
6823 bx r12
6824 __func_addr:
906e58ca 6825 .word func @ behave as if you saw a ARM_32 reloc.
252b5132 6826
26079076
PB		 6827 (v5t static images)
6828 .arm
6829 __func_from_arm:
6830 ldr pc, __func_addr
6831 __func_addr:
906e58ca 6832 .word func @ behave as if you saw a ARM_32 reloc.
26079076 6833
8f6277f5
PB		 6834 (relocatable images)
6835 .arm
6836 __func_from_arm:
6837 ldr r12, __func_offset
6838 add r12, r12, pc
6839 bx r12
6840 __func_offset:
8029a119 6841 .word func - . */
8f6277f5
PB		 6842
6843#define ARM2THUMB_STATIC_GLUE_SIZE 12
252b5132
RH		 6844static const insn32 a2t1_ldr_insn = 0xe59fc000;
6845static const insn32 a2t2_bx_r12_insn = 0xe12fff1c;
6846static const insn32 a2t3_func_addr_insn = 0x00000001;
6847
26079076
PB		 6848#define ARM2THUMB_V5_STATIC_GLUE_SIZE 8
6849static const insn32 a2t1v5_ldr_insn = 0xe51ff004;
6850static const insn32 a2t2v5_func_addr_insn = 0x00000001;
6851
8f6277f5
PB		 6852#define ARM2THUMB_PIC_GLUE_SIZE 16
6853static const insn32 a2t1p_ldr_insn = 0xe59fc004;
6854static const insn32 a2t2p_add_pc_insn = 0xe08cc00f;
6855static const insn32 a2t3p_bx_r12_insn = 0xe12fff1c;
6856
9b485d32 6857/* Thumb->ARM: Thumb->(non-interworking aware) ARM
252b5132 6858
8029a119
NC		 6859 .thumb .thumb
6860 .align 2 .align 2
6861 __func_from_thumb: __func_from_thumb:
6862 bx pc push {r6, lr}
6863 nop ldr r6, __func_addr
6864 .arm mov lr, pc
6865 b func bx r6
99059e56
RM		 6866 .arm
6867 ;; back_to_thumb
6868 ldmia r13! {r6, lr}
6869 bx lr
6870 __func_addr:
6871 .word func */
252b5132
RH		 6872
6873#define THUMB2ARM_GLUE_SIZE 8
6874static const insn16 t2a1_bx_pc_insn = 0x4778;
6875static const insn16 t2a2_noop_insn = 0x46c0;
6876static const insn32 t2a3_b_insn = 0xea000000;
6877
c7b8f16e 6878#define VFP11_ERRATUM_VENEER_SIZE 8
a504d23a
LA		 6879#define STM32L4XX_ERRATUM_LDM_VENEER_SIZE 16
6880#define STM32L4XX_ERRATUM_VLDM_VENEER_SIZE 24
c7b8f16e 6881
845b51d6
PB		 6882#define ARM_BX_VENEER_SIZE 12
6883static const insn32 armbx1_tst_insn = 0xe3100001;
6884static const insn32 armbx2_moveq_insn = 0x01a0f000;
6885static const insn32 armbx3_bx_insn = 0xe12fff10;
6886
7e392df6 6887#ifndef ELFARM_NABI_C_INCLUDED
8029a119
NC		 6888static void
6889arm_allocate_glue_section_space (bfd * abfd, bfd_size_type size, const char * name)
252b5132
RH		 6890{
6891 asection * s;
8029a119 6892 bfd_byte * contents;
252b5132 6893
8029a119 6894 if (size == 0)
3e6b1042
DJ		 6895 {
6896 /* Do not include empty glue sections in the output. */
6897 if (abfd != NULL)
6898 {
3d4d4302 6899 s = bfd_get_linker_section (abfd, name);
3e6b1042
DJ		 6900 if (s != NULL)
6901 s->flags |= SEC_EXCLUDE;
6902 }
6903 return;
6904 }
252b5132 6905
8029a119 6906 BFD_ASSERT (abfd != NULL);
252b5132 6907
3d4d4302 6908 s = bfd_get_linker_section (abfd, name);
8029a119 6909 BFD_ASSERT (s != NULL);
252b5132 6910
21d799b5 6911 contents = (bfd_byte *) bfd_alloc (abfd, size);
252b5132 6912
8029a119
NC		 6913 BFD_ASSERT (s->size == size);
6914 s->contents = contents;
6915}
906e58ca 6916
8029a119
NC		 6917bfd_boolean
6918bfd_elf32_arm_allocate_interworking_sections (struct bfd_link_info * info)
6919{
6920 struct elf32_arm_link_hash_table * globals;
906e58ca 6921
8029a119
NC		 6922 globals = elf32_arm_hash_table (info);
6923 BFD_ASSERT (globals != NULL);
906e58ca 6924
8029a119
NC		 6925 arm_allocate_glue_section_space (globals->bfd_of_glue_owner,
6926 globals->arm_glue_size,
6927 ARM2THUMB_GLUE_SECTION_NAME);
906e58ca 6928
8029a119
NC		 6929 arm_allocate_glue_section_space (globals->bfd_of_glue_owner,
6930 globals->thumb_glue_size,
6931 THUMB2ARM_GLUE_SECTION_NAME);
252b5132 6932
8029a119
NC		 6933 arm_allocate_glue_section_space (globals->bfd_of_glue_owner,
6934 globals->vfp11_erratum_glue_size,
6935 VFP11_ERRATUM_VENEER_SECTION_NAME);
845b51d6 6936
a504d23a
LA		 6937 arm_allocate_glue_section_space (globals->bfd_of_glue_owner,
6938 globals->stm32l4xx_erratum_glue_size,
6939 STM32L4XX_ERRATUM_VENEER_SECTION_NAME);
6940
8029a119
NC		 6941 arm_allocate_glue_section_space (globals->bfd_of_glue_owner,
6942 globals->bx_glue_size,
845b51d6
PB		 6943 ARM_BX_GLUE_SECTION_NAME);
6944
b34976b6 6945 return TRUE;
252b5132
RH		 6946}
6947
a4fd1a8e 6948/* Allocate space and symbols for calling a Thumb function from Arm mode.
906e58ca
NC		 6949 returns the symbol identifying the stub. */
6950
a4fd1a8e 6951static struct elf_link_hash_entry *
57e8b36a
NC		 6952record_arm_to_thumb_glue (struct bfd_link_info * link_info,
6953 struct elf_link_hash_entry * h)
252b5132
RH		 6954{
6955 const char * name = h->root.root.string;
63b0f745 6956 asection * s;
252b5132
RH		 6957 char * tmp_name;
6958 struct elf_link_hash_entry * myh;
14a793b2 6959 struct bfd_link_hash_entry * bh;
252b5132 6960 struct elf32_arm_link_hash_table * globals;
dc810e39 6961 bfd_vma val;
2f475487 6962 bfd_size_type size;
252b5132
RH		 6963
6964 globals = elf32_arm_hash_table (link_info);
252b5132
RH		 6965 BFD_ASSERT (globals != NULL);
6966 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
6967
3d4d4302 6968 s = bfd_get_linker_section
252b5132
RH		 6969 (globals->bfd_of_glue_owner, ARM2THUMB_GLUE_SECTION_NAME);
6970
252b5132
RH		 6971 BFD_ASSERT (s != NULL);
6972
21d799b5 6973 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen (name)
99059e56 6974 + strlen (ARM2THUMB_GLUE_ENTRY_NAME) + 1);
252b5132
RH		 6975
6976 BFD_ASSERT (tmp_name);
6977
6978 sprintf (tmp_name, ARM2THUMB_GLUE_ENTRY_NAME, name);
6979
6980 myh = elf_link_hash_lookup
b34976b6 6981 (&(globals)->root, tmp_name, FALSE, FALSE, TRUE);
252b5132
RH		 6982
6983 if (myh != NULL)
6984 {
9b485d32 6985 /* We've already seen this guy. */
252b5132 6986 free (tmp_name);
a4fd1a8e 6987 return myh;
252b5132
RH		 6988 }
6989
57e8b36a
NC		 6990 /* The only trick here is using hash_table->arm_glue_size as the value.
6991 Even though the section isn't allocated yet, this is where we will be
3dccd7b7
DJ		 6992 putting it. The +1 on the value marks that the stub has not been
6993 output yet - not that it is a Thumb function. */
14a793b2 6994 bh = NULL;
dc810e39
AM		 6995 val = globals->arm_glue_size + 1;
6996 _bfd_generic_link_add_one_symbol (link_info, globals->bfd_of_glue_owner,
6997 tmp_name, BSF_GLOBAL, s, val,
b34976b6 6998 NULL, TRUE, FALSE, &bh);
252b5132 6999
b7693d02
DJ		 7000 myh = (struct elf_link_hash_entry *) bh;
7001 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
7002 myh->forced_local = 1;
7003
252b5132
RH		 7004 free (tmp_name);
7005
0e1862bb
L		 7006 if (bfd_link_pic (link_info)
7007 || globals->root.is_relocatable_executable
27e55c4d 7008 || globals->pic_veneer)
2f475487 7009 size = ARM2THUMB_PIC_GLUE_SIZE;
26079076
PB		 7010 else if (globals->use_blx)
7011 size = ARM2THUMB_V5_STATIC_GLUE_SIZE;
8f6277f5 7012 else
2f475487
AM		 7013 size = ARM2THUMB_STATIC_GLUE_SIZE;
7014
7015 s->size += size;
7016 globals->arm_glue_size += size;
252b5132 7017
a4fd1a8e 7018 return myh;
252b5132
RH		 7019}
7020
845b51d6
PB		 7021/* Allocate space for ARMv4 BX veneers. */
7022
7023static void
7024record_arm_bx_glue (struct bfd_link_info * link_info, int reg)
7025{
7026 asection * s;
7027 struct elf32_arm_link_hash_table *globals;
7028 char *tmp_name;
7029 struct elf_link_hash_entry *myh;
7030 struct bfd_link_hash_entry *bh;
7031 bfd_vma val;
7032
7033 /* BX PC does not need a veneer. */
7034 if (reg == 15)
7035 return;
7036
7037 globals = elf32_arm_hash_table (link_info);
845b51d6
PB		 7038 BFD_ASSERT (globals != NULL);
7039 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
7040
7041 /* Check if this veneer has already been allocated. */
7042 if (globals->bx_glue_offset[reg])
7043 return;
7044
3d4d4302 7045 s = bfd_get_linker_section
845b51d6
PB		 7046 (globals->bfd_of_glue_owner, ARM_BX_GLUE_SECTION_NAME);
7047
7048 BFD_ASSERT (s != NULL);
7049
7050 /* Add symbol for veneer. */
21d799b5
NC		 7051 tmp_name = (char *)
7052 bfd_malloc ((bfd_size_type) strlen (ARM_BX_GLUE_ENTRY_NAME) + 1);
906e58ca 7053
845b51d6 7054 BFD_ASSERT (tmp_name);
906e58ca 7055
845b51d6 7056 sprintf (tmp_name, ARM_BX_GLUE_ENTRY_NAME, reg);
906e58ca 7057
845b51d6
PB		 7058 myh = elf_link_hash_lookup
7059 (&(globals)->root, tmp_name, FALSE, FALSE, FALSE);
906e58ca 7060
845b51d6 7061 BFD_ASSERT (myh == NULL);
906e58ca 7062
845b51d6
PB		 7063 bh = NULL;
7064 val = globals->bx_glue_size;
7065 _bfd_generic_link_add_one_symbol (link_info, globals->bfd_of_glue_owner,
99059e56
RM		 7066 tmp_name, BSF_FUNCTION | BSF_LOCAL, s, val,
7067 NULL, TRUE, FALSE, &bh);
845b51d6
PB		 7068
7069 myh = (struct elf_link_hash_entry *) bh;
7070 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
7071 myh->forced_local = 1;
7072
7073 s->size += ARM_BX_VENEER_SIZE;
7074 globals->bx_glue_offset[reg] = globals->bx_glue_size | 2;
7075 globals->bx_glue_size += ARM_BX_VENEER_SIZE;
7076}
7077
7078
c7b8f16e
JB		 7079/* Add an entry to the code/data map for section SEC. */
7080
7081static void
7082elf32_arm_section_map_add (asection *sec, char type, bfd_vma vma)
7083{
7084 struct _arm_elf_section_data *sec_data = elf32_arm_section_data (sec);
7085 unsigned int newidx;
906e58ca 7086
c7b8f16e
JB		 7087 if (sec_data->map == NULL)
7088 {
21d799b5 7089 sec_data->map = (elf32_arm_section_map *)
99059e56 7090 bfd_malloc (sizeof (elf32_arm_section_map));
c7b8f16e
JB		 7091 sec_data->mapcount = 0;
7092 sec_data->mapsize = 1;
7093 }
906e58ca 7094
c7b8f16e 7095 newidx = sec_data->mapcount++;
906e58ca 7096
c7b8f16e
JB		 7097 if (sec_data->mapcount > sec_data->mapsize)
7098 {
7099 sec_data->mapsize *= 2;
21d799b5 7100 sec_data->map = (elf32_arm_section_map *)
99059e56
RM		 7101 bfd_realloc_or_free (sec_data->map, sec_data->mapsize
7102 * sizeof (elf32_arm_section_map));
515ef31d
NC		 7103 }
7104
7105 if (sec_data->map)
7106 {
7107 sec_data->map[newidx].vma = vma;
7108 sec_data->map[newidx].type = type;
c7b8f16e 7109 }
c7b8f16e
JB		 7110}
7111
7112
7113/* Record information about a VFP11 denorm-erratum veneer. Only ARM-mode
7114 veneers are handled for now. */
7115
7116static bfd_vma
7117record_vfp11_erratum_veneer (struct bfd_link_info *link_info,
99059e56
RM		 7118 elf32_vfp11_erratum_list *branch,
7119 bfd *branch_bfd,
7120 asection *branch_sec,
7121 unsigned int offset)
c7b8f16e
JB		 7122{
7123 asection *s;
7124 struct elf32_arm_link_hash_table *hash_table;
7125 char *tmp_name;
7126 struct elf_link_hash_entry *myh;
7127 struct bfd_link_hash_entry *bh;
7128 bfd_vma val;
7129 struct _arm_elf_section_data *sec_data;
c7b8f16e 7130 elf32_vfp11_erratum_list *newerr;
906e58ca 7131
c7b8f16e 7132 hash_table = elf32_arm_hash_table (link_info);
c7b8f16e
JB		 7133 BFD_ASSERT (hash_table != NULL);
7134 BFD_ASSERT (hash_table->bfd_of_glue_owner != NULL);
906e58ca 7135
3d4d4302 7136 s = bfd_get_linker_section
c7b8f16e 7137 (hash_table->bfd_of_glue_owner, VFP11_ERRATUM_VENEER_SECTION_NAME);
906e58ca 7138
c7b8f16e 7139 sec_data = elf32_arm_section_data (s);
906e58ca 7140
c7b8f16e 7141 BFD_ASSERT (s != NULL);
906e58ca 7142
21d799b5 7143 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen
99059e56 7144 (VFP11_ERRATUM_VENEER_ENTRY_NAME) + 10);
906e58ca 7145
c7b8f16e 7146 BFD_ASSERT (tmp_name);
906e58ca 7147
c7b8f16e
JB		 7148 sprintf (tmp_name, VFP11_ERRATUM_VENEER_ENTRY_NAME,
7149 hash_table->num_vfp11_fixes);
906e58ca 7150
c7b8f16e
JB		 7151 myh = elf_link_hash_lookup
7152 (&(hash_table)->root, tmp_name, FALSE, FALSE, FALSE);
906e58ca 7153
c7b8f16e 7154 BFD_ASSERT (myh == NULL);
906e58ca 7155
c7b8f16e
JB		 7156 bh = NULL;
7157 val = hash_table->vfp11_erratum_glue_size;
7158 _bfd_generic_link_add_one_symbol (link_info, hash_table->bfd_of_glue_owner,
99059e56
RM		 7159 tmp_name, BSF_FUNCTION | BSF_LOCAL, s, val,
7160 NULL, TRUE, FALSE, &bh);
c7b8f16e
JB		 7161
7162 myh = (struct elf_link_hash_entry *) bh;
7163 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
7164 myh->forced_local = 1;
7165
7166 /* Link veneer back to calling location. */
c7e2358a 7167 sec_data->erratumcount += 1;
21d799b5
NC		 7168 newerr = (elf32_vfp11_erratum_list *)
7169 bfd_zmalloc (sizeof (elf32_vfp11_erratum_list));
906e58ca 7170
c7b8f16e
JB		 7171 newerr->type = VFP11_ERRATUM_ARM_VENEER;
7172 newerr->vma = -1;
7173 newerr->u.v.branch = branch;
7174 newerr->u.v.id = hash_table->num_vfp11_fixes;
7175 branch->u.b.veneer = newerr;
7176
7177 newerr->next = sec_data->erratumlist;
7178 sec_data->erratumlist = newerr;
7179
7180 /* A symbol for the return from the veneer. */
7181 sprintf (tmp_name, VFP11_ERRATUM_VENEER_ENTRY_NAME "_r",
7182 hash_table->num_vfp11_fixes);
7183
7184 myh = elf_link_hash_lookup
7185 (&(hash_table)->root, tmp_name, FALSE, FALSE, FALSE);
906e58ca 7186
c7b8f16e
JB		 7187 if (myh != NULL)
7188 abort ();
7189
7190 bh = NULL;
7191 val = offset + 4;
7192 _bfd_generic_link_add_one_symbol (link_info, branch_bfd, tmp_name, BSF_LOCAL,
7193 branch_sec, val, NULL, TRUE, FALSE, &bh);
906e58ca 7194
c7b8f16e
JB		 7195 myh = (struct elf_link_hash_entry *) bh;
7196 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
7197 myh->forced_local = 1;
7198
7199 free (tmp_name);
906e58ca 7200
c7b8f16e
JB		 7201 /* Generate a mapping symbol for the veneer section, and explicitly add an
7202 entry for that symbol to the code/data map for the section. */
7203 if (hash_table->vfp11_erratum_glue_size == 0)
7204 {
7205 bh = NULL;
7206 /* FIXME: Creates an ARM symbol. Thumb mode will need attention if it
99059e56 7207 ever requires this erratum fix. */
c7b8f16e
JB		 7208 _bfd_generic_link_add_one_symbol (link_info,
7209 hash_table->bfd_of_glue_owner, "$a",
7210 BSF_LOCAL, s, 0, NULL,
99059e56 7211 TRUE, FALSE, &bh);
c7b8f16e
JB		 7212
7213 myh = (struct elf_link_hash_entry *) bh;
7214 myh->type = ELF_ST_INFO (STB_LOCAL, STT_NOTYPE);
7215 myh->forced_local = 1;
906e58ca 7216
c7b8f16e 7217 /* The elf32_arm_init_maps function only cares about symbols from input
99059e56
RM		 7218 BFDs. We must make a note of this generated mapping symbol
7219 ourselves so that code byteswapping works properly in
7220 elf32_arm_write_section. */
c7b8f16e
JB		 7221 elf32_arm_section_map_add (s, 'a', 0);
7222 }
906e58ca 7223
c7b8f16e
JB		 7224 s->size += VFP11_ERRATUM_VENEER_SIZE;
7225 hash_table->vfp11_erratum_glue_size += VFP11_ERRATUM_VENEER_SIZE;
7226 hash_table->num_vfp11_fixes++;
906e58ca 7227
c7b8f16e
JB		 7228 /* The offset of the veneer. */
7229 return val;
7230}
7231
a504d23a
LA		 7232/* Record information about a STM32L4XX STM erratum veneer. Only THUMB-mode
7233 veneers need to be handled because used only in Cortex-M. */
7234
7235static bfd_vma
7236record_stm32l4xx_erratum_veneer (struct bfd_link_info *link_info,
7237 elf32_stm32l4xx_erratum_list *branch,
7238 bfd *branch_bfd,
7239 asection *branch_sec,
7240 unsigned int offset,
7241 bfd_size_type veneer_size)
7242{
7243 asection *s;
7244 struct elf32_arm_link_hash_table *hash_table;
7245 char *tmp_name;
7246 struct elf_link_hash_entry *myh;
7247 struct bfd_link_hash_entry *bh;
7248 bfd_vma val;
7249 struct _arm_elf_section_data *sec_data;
7250 elf32_stm32l4xx_erratum_list *newerr;
7251
7252 hash_table = elf32_arm_hash_table (link_info);
7253 BFD_ASSERT (hash_table != NULL);
7254 BFD_ASSERT (hash_table->bfd_of_glue_owner != NULL);
7255
7256 s = bfd_get_linker_section
7257 (hash_table->bfd_of_glue_owner, STM32L4XX_ERRATUM_VENEER_SECTION_NAME);
7258
7259 BFD_ASSERT (s != NULL);
7260
7261 sec_data = elf32_arm_section_data (s);
7262
7263 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen
7264 (STM32L4XX_ERRATUM_VENEER_ENTRY_NAME) + 10);
7265
7266 BFD_ASSERT (tmp_name);
7267
7268 sprintf (tmp_name, STM32L4XX_ERRATUM_VENEER_ENTRY_NAME,
7269 hash_table->num_stm32l4xx_fixes);
7270
7271 myh = elf_link_hash_lookup
7272 (&(hash_table)->root, tmp_name, FALSE, FALSE, FALSE);
7273
7274 BFD_ASSERT (myh == NULL);
7275
7276 bh = NULL;
7277 val = hash_table->stm32l4xx_erratum_glue_size;
7278 _bfd_generic_link_add_one_symbol (link_info, hash_table->bfd_of_glue_owner,
7279 tmp_name, BSF_FUNCTION | BSF_LOCAL, s, val,
7280 NULL, TRUE, FALSE, &bh);
7281
7282 myh = (struct elf_link_hash_entry *) bh;
7283 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
7284 myh->forced_local = 1;
7285
7286 /* Link veneer back to calling location. */
7287 sec_data->stm32l4xx_erratumcount += 1;
7288 newerr = (elf32_stm32l4xx_erratum_list *)
7289 bfd_zmalloc (sizeof (elf32_stm32l4xx_erratum_list));
7290
7291 newerr->type = STM32L4XX_ERRATUM_VENEER;
7292 newerr->vma = -1;
7293 newerr->u.v.branch = branch;
7294 newerr->u.v.id = hash_table->num_stm32l4xx_fixes;
7295 branch->u.b.veneer = newerr;
7296
7297 newerr->next = sec_data->stm32l4xx_erratumlist;
7298 sec_data->stm32l4xx_erratumlist = newerr;
7299
7300 /* A symbol for the return from the veneer. */
7301 sprintf (tmp_name, STM32L4XX_ERRATUM_VENEER_ENTRY_NAME "_r",
7302 hash_table->num_stm32l4xx_fixes);
7303
7304 myh = elf_link_hash_lookup
7305 (&(hash_table)->root, tmp_name, FALSE, FALSE, FALSE);
7306
7307 if (myh != NULL)
7308 abort ();
7309
7310 bh = NULL;
7311 val = offset + 4;
7312 _bfd_generic_link_add_one_symbol (link_info, branch_bfd, tmp_name, BSF_LOCAL,
7313 branch_sec, val, NULL, TRUE, FALSE, &bh);
7314
7315 myh = (struct elf_link_hash_entry *) bh;
7316 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
7317 myh->forced_local = 1;
7318
7319 free (tmp_name);
7320
7321 /* Generate a mapping symbol for the veneer section, and explicitly add an
7322 entry for that symbol to the code/data map for the section. */
7323 if (hash_table->stm32l4xx_erratum_glue_size == 0)
7324 {
7325 bh = NULL;
7326 /* Creates a THUMB symbol since there is no other choice. */
7327 _bfd_generic_link_add_one_symbol (link_info,
7328 hash_table->bfd_of_glue_owner, "$t",
7329 BSF_LOCAL, s, 0, NULL,
7330 TRUE, FALSE, &bh);
7331
7332 myh = (struct elf_link_hash_entry *) bh;
7333 myh->type = ELF_ST_INFO (STB_LOCAL, STT_NOTYPE);
7334 myh->forced_local = 1;
7335
7336 /* The elf32_arm_init_maps function only cares about symbols from input
7337 BFDs. We must make a note of this generated mapping symbol
7338 ourselves so that code byteswapping works properly in
7339 elf32_arm_write_section. */
7340 elf32_arm_section_map_add (s, 't', 0);
7341 }
7342
7343 s->size += veneer_size;
7344 hash_table->stm32l4xx_erratum_glue_size += veneer_size;
7345 hash_table->num_stm32l4xx_fixes++;
7346
7347 /* The offset of the veneer. */
7348 return val;
7349}
7350
8029a119 7351#define ARM_GLUE_SECTION_FLAGS \
3e6b1042
DJ		 7352 (SEC_ALLOC | SEC_LOAD | SEC_HAS_CONTENTS | SEC_IN_MEMORY | SEC_CODE \
7353 | SEC_READONLY | SEC_LINKER_CREATED)
8029a119
NC		 7354
7355/* Create a fake section for use by the ARM backend of the linker. */
7356
7357static bfd_boolean
7358arm_make_glue_section (bfd * abfd, const char * name)
7359{
7360 asection * sec;
7361
3d4d4302 7362 sec = bfd_get_linker_section (abfd, name);
8029a119
NC		 7363 if (sec != NULL)
7364 /* Already made. */
7365 return TRUE;
7366
3d4d4302 7367 sec = bfd_make_section_anyway_with_flags (abfd, name, ARM_GLUE_SECTION_FLAGS);
8029a119
NC		 7368
7369 if (sec == NULL
7370 || !bfd_set_section_alignment (abfd, sec, 2))
7371 return FALSE;
7372
7373 /* Set the gc mark to prevent the section from being removed by garbage
7374 collection, despite the fact that no relocs refer to this section. */
7375 sec->gc_mark = 1;
7376
7377 return TRUE;
7378}
7379
1db37fe6
YG		 7380/* Set size of .plt entries. This function is called from the
7381 linker scripts in ld/emultempl/{armelf}.em. */
7382
7383void
7384bfd_elf32_arm_use_long_plt (void)
7385{
7386 elf32_arm_use_long_plt_entry = TRUE;
7387}
7388
8afb0e02
NC		 7389/* Add the glue sections to ABFD. This function is called from the
7390 linker scripts in ld/emultempl/{armelf}.em. */
9b485d32 7391
b34976b6 7392bfd_boolean
57e8b36a
NC		 7393bfd_elf32_arm_add_glue_sections_to_bfd (bfd *abfd,
7394 struct bfd_link_info *info)
252b5132 7395{
a504d23a
LA		 7396 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (info);
7397 bfd_boolean dostm32l4xx = globals
7398 && globals->stm32l4xx_fix != BFD_ARM_STM32L4XX_FIX_NONE;
7399 bfd_boolean addglue;
7400
8afb0e02
NC		 7401 /* If we are only performing a partial
7402 link do not bother adding the glue. */
0e1862bb 7403 if (bfd_link_relocatable (info))
b34976b6 7404 return TRUE;
252b5132 7405
a504d23a 7406 addglue = arm_make_glue_section (abfd, ARM2THUMB_GLUE_SECTION_NAME)
8029a119
NC		 7407 && arm_make_glue_section (abfd, THUMB2ARM_GLUE_SECTION_NAME)
7408 && arm_make_glue_section (abfd, VFP11_ERRATUM_VENEER_SECTION_NAME)
7409 && arm_make_glue_section (abfd, ARM_BX_GLUE_SECTION_NAME);
a504d23a
LA		 7410
7411 if (!dostm32l4xx)
7412 return addglue;
7413
7414 return addglue
7415 && arm_make_glue_section (abfd, STM32L4XX_ERRATUM_VENEER_SECTION_NAME);
8afb0e02
NC		 7416}
7417
daa4adae
TP		 7418/* Mark output sections of veneers needing a dedicated one with SEC_KEEP. This
7419 ensures they are not marked for deletion by
7420 strip_excluded_output_sections () when veneers are going to be created
7421 later. Not doing so would trigger assert on empty section size in
7422 lang_size_sections_1 (). */
7423
7424void
7425bfd_elf32_arm_keep_private_stub_output_sections (struct bfd_link_info *info)
7426{
7427 enum elf32_arm_stub_type stub_type;
7428
7429 /* If we are only performing a partial
7430 link do not bother adding the glue. */
7431 if (bfd_link_relocatable (info))
7432 return;
7433
7434 for (stub_type = arm_stub_none + 1; stub_type < max_stub_type; stub_type++)
7435 {
7436 asection *out_sec;
7437 const char *out_sec_name;
7438
7439 if (!arm_dedicated_stub_output_section_required (stub_type))
7440 continue;
7441
7442 out_sec_name = arm_dedicated_stub_output_section_name (stub_type);
7443 out_sec = bfd_get_section_by_name (info->output_bfd, out_sec_name);
7444 if (out_sec != NULL)
7445 out_sec->flags |= SEC_KEEP;
7446 }
7447}
7448
8afb0e02
NC		 7449/* Select a BFD to be used to hold the sections used by the glue code.
7450 This function is called from the linker scripts in ld/emultempl/
8029a119 7451 {armelf/pe}.em. */
8afb0e02 7452
b34976b6 7453bfd_boolean
57e8b36a 7454bfd_elf32_arm_get_bfd_for_interworking (bfd *abfd, struct bfd_link_info *info)
8afb0e02
NC		 7455{
7456 struct elf32_arm_link_hash_table *globals;
7457
7458 /* If we are only performing a partial link
7459 do not bother getting a bfd to hold the glue. */
0e1862bb 7460 if (bfd_link_relocatable (info))
b34976b6 7461 return TRUE;
8afb0e02 7462
b7693d02
DJ		 7463 /* Make sure we don't attach the glue sections to a dynamic object. */
7464 BFD_ASSERT (!(abfd->flags & DYNAMIC));
7465
8afb0e02 7466 globals = elf32_arm_hash_table (info);
8afb0e02
NC		 7467 BFD_ASSERT (globals != NULL);
7468
7469 if (globals->bfd_of_glue_owner != NULL)
b34976b6 7470 return TRUE;
8afb0e02 7471
252b5132
RH		 7472 /* Save the bfd for later use. */
7473 globals->bfd_of_glue_owner = abfd;
cedb70c5 7474
b34976b6 7475 return TRUE;
252b5132
RH		 7476}
7477
906e58ca
NC		 7478static void
7479check_use_blx (struct elf32_arm_link_hash_table *globals)
39b41c9c 7480{
2de70689
MGD		 7481 int cpu_arch;
7482
b38cadfb 7483 cpu_arch = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC,
2de70689
MGD		 7484 Tag_CPU_arch);
7485
7486 if (globals->fix_arm1176)
7487 {
7488 if (cpu_arch == TAG_CPU_ARCH_V6T2 || cpu_arch > TAG_CPU_ARCH_V6K)
7489 globals->use_blx = 1;
7490 }
7491 else
7492 {
7493 if (cpu_arch > TAG_CPU_ARCH_V4T)
7494 globals->use_blx = 1;
7495 }
39b41c9c
PB		 7496}
7497
b34976b6 7498bfd_boolean
57e8b36a 7499bfd_elf32_arm_process_before_allocation (bfd *abfd,
d504ffc8 7500 struct bfd_link_info *link_info)
252b5132
RH		 7501{
7502 Elf_Internal_Shdr *symtab_hdr;
6cdc0ccc 7503 Elf_Internal_Rela *internal_relocs = NULL;
252b5132
RH		 7504 Elf_Internal_Rela *irel, *irelend;
7505 bfd_byte *contents = NULL;
252b5132
RH		 7506
7507 asection *sec;
7508 struct elf32_arm_link_hash_table *globals;
7509
7510 /* If we are only performing a partial link do not bother
7511 to construct any glue. */
0e1862bb 7512 if (bfd_link_relocatable (link_info))
b34976b6 7513 return TRUE;
252b5132 7514
39ce1a6a
NC		 7515 /* Here we have a bfd that is to be included on the link. We have a
7516 hook to do reloc rummaging, before section sizes are nailed down. */
252b5132 7517 globals = elf32_arm_hash_table (link_info);
252b5132 7518 BFD_ASSERT (globals != NULL);
39ce1a6a
NC		 7519
7520 check_use_blx (globals);
252b5132 7521
d504ffc8 7522 if (globals->byteswap_code && !bfd_big_endian (abfd))
e489d0ae 7523 {
d003868e
AM		 7524 _bfd_error_handler (_("%B: BE8 images only valid in big-endian mode."),
7525 abfd);
e489d0ae
PB		 7526 return FALSE;
7527 }
f21f3fe0 7528
39ce1a6a
NC		 7529 /* PR 5398: If we have not decided to include any loadable sections in
7530 the output then we will not have a glue owner bfd. This is OK, it
7531 just means that there is nothing else for us to do here. */
7532 if (globals->bfd_of_glue_owner == NULL)
7533 return TRUE;
7534
252b5132
RH		 7535 /* Rummage around all the relocs and map the glue vectors. */
7536 sec = abfd->sections;
7537
7538 if (sec == NULL)
b34976b6 7539 return TRUE;
252b5132
RH		 7540
7541 for (; sec != NULL; sec = sec->next)
7542 {
7543 if (sec->reloc_count == 0)
7544 continue;
7545
2f475487
AM		 7546 if ((sec->flags & SEC_EXCLUDE) != 0)
7547 continue;
7548
0ffa91dd 7549 symtab_hdr = & elf_symtab_hdr (abfd);
252b5132 7550
9b485d32 7551 /* Load the relocs. */
6cdc0ccc 7552 internal_relocs
906e58ca 7553 = _bfd_elf_link_read_relocs (abfd, sec, NULL, NULL, FALSE);
252b5132 7554
6cdc0ccc
AM		 7555 if (internal_relocs == NULL)
7556 goto error_return;
252b5132 7557
6cdc0ccc
AM		 7558 irelend = internal_relocs + sec->reloc_count;
7559 for (irel = internal_relocs; irel < irelend; irel++)
252b5132
RH		 7560 {
7561 long r_type;
7562 unsigned long r_index;
252b5132
RH		 7563
7564 struct elf_link_hash_entry *h;
7565
7566 r_type = ELF32_R_TYPE (irel->r_info);
7567 r_index = ELF32_R_SYM (irel->r_info);
7568
9b485d32 7569 /* These are the only relocation types we care about. */
ba96a88f 7570 if ( r_type != R_ARM_PC24
845b51d6 7571 && (r_type != R_ARM_V4BX || globals->fix_v4bx < 2))
252b5132
RH		 7572 continue;
7573
7574 /* Get the section contents if we haven't done so already. */
7575 if (contents == NULL)
7576 {
7577 /* Get cached copy if it exists. */
7578 if (elf_section_data (sec)->this_hdr.contents != NULL)
7579 contents = elf_section_data (sec)->this_hdr.contents;
7580 else
7581 {
7582 /* Go get them off disk. */
57e8b36a 7583 if (! bfd_malloc_and_get_section (abfd, sec, &contents))
252b5132
RH		 7584 goto error_return;
7585 }
7586 }
7587
845b51d6
PB		 7588 if (r_type == R_ARM_V4BX)
7589 {
7590 int reg;
7591
7592 reg = bfd_get_32 (abfd, contents + irel->r_offset) & 0xf;
7593 record_arm_bx_glue (link_info, reg);
7594 continue;
7595 }
7596
a7c10850 7597 /* If the relocation is not against a symbol it cannot concern us. */
252b5132
RH		 7598 h = NULL;
7599
9b485d32 7600 /* We don't care about local symbols. */
252b5132
RH		 7601 if (r_index < symtab_hdr->sh_info)
7602 continue;
7603
9b485d32 7604 /* This is an external symbol. */
252b5132
RH		 7605 r_index -= symtab_hdr->sh_info;
7606 h = (struct elf_link_hash_entry *)
7607 elf_sym_hashes (abfd)[r_index];
7608
7609 /* If the relocation is against a static symbol it must be within
7610 the current section and so cannot be a cross ARM/Thumb relocation. */
7611 if (h == NULL)
7612 continue;
7613
d504ffc8
DJ		 7614 /* If the call will go through a PLT entry then we do not need
7615 glue. */
362d30a1 7616 if (globals->root.splt != NULL && h->plt.offset != (bfd_vma) -1)
b7693d02
DJ		 7617 continue;
7618
252b5132
RH		 7619 switch (r_type)
7620 {
7621 case R_ARM_PC24:
7622 /* This one is a call from arm code. We need to look up
99059e56
RM		 7623 the target of the call. If it is a thumb target, we
7624 insert glue. */
39d911fc
TP		 7625 if (ARM_GET_SYM_BRANCH_TYPE (h->target_internal)
7626 == ST_BRANCH_TO_THUMB)
252b5132
RH		 7627 record_arm_to_thumb_glue (link_info, h);
7628 break;
7629
252b5132 7630 default:
c6596c5e 7631 abort ();
252b5132
RH		 7632 }
7633 }
6cdc0ccc
AM		 7634
7635 if (contents != NULL
7636 && elf_section_data (sec)->this_hdr.contents != contents)
7637 free (contents);
7638 contents = NULL;
7639
7640 if (internal_relocs != NULL
7641 && elf_section_data (sec)->relocs != internal_relocs)
7642 free (internal_relocs);
7643 internal_relocs = NULL;
252b5132
RH		 7644 }
7645
b34976b6 7646 return TRUE;
9a5aca8c 7647
252b5132 7648error_return:
6cdc0ccc
AM		 7649 if (contents != NULL
7650 && elf_section_data (sec)->this_hdr.contents != contents)
7651 free (contents);
7652 if (internal_relocs != NULL
7653 && elf_section_data (sec)->relocs != internal_relocs)
7654 free (internal_relocs);
9a5aca8c 7655
b34976b6 7656 return FALSE;
252b5132 7657}
7e392df6 7658#endif
252b5132 7659
eb043451 7660
c7b8f16e
JB		 7661/* Initialise maps of ARM/Thumb/data for input BFDs. */
7662
7663void
7664bfd_elf32_arm_init_maps (bfd *abfd)
7665{
7666 Elf_Internal_Sym *isymbuf;
7667 Elf_Internal_Shdr *hdr;
7668 unsigned int i, localsyms;
7669
af1f4419
NC		 7670 /* PR 7093: Make sure that we are dealing with an arm elf binary. */
7671 if (! is_arm_elf (abfd))
7672 return;
7673
c7b8f16e
JB		 7674 if ((abfd->flags & DYNAMIC) != 0)
7675 return;
7676
0ffa91dd 7677 hdr = & elf_symtab_hdr (abfd);
c7b8f16e
JB		 7678 localsyms = hdr->sh_info;
7679
7680 /* Obtain a buffer full of symbols for this BFD. The hdr->sh_info field
7681 should contain the number of local symbols, which should come before any
7682 global symbols. Mapping symbols are always local. */
7683 isymbuf = bfd_elf_get_elf_syms (abfd, hdr, localsyms, 0, NULL, NULL,
7684 NULL);
7685
7686 /* No internal symbols read? Skip this BFD. */
7687 if (isymbuf == NULL)
7688 return;
7689
7690 for (i = 0; i < localsyms; i++)
7691 {
7692 Elf_Internal_Sym *isym = &isymbuf[i];
7693 asection *sec = bfd_section_from_elf_index (abfd, isym->st_shndx);
7694 const char *name;
906e58ca 7695
c7b8f16e 7696 if (sec != NULL
99059e56
RM		 7697 && ELF_ST_BIND (isym->st_info) == STB_LOCAL)
7698 {
7699 name = bfd_elf_string_from_elf_section (abfd,
7700 hdr->sh_link, isym->st_name);
906e58ca 7701
99059e56 7702 if (bfd_is_arm_special_symbol_name (name,
c7b8f16e 7703 BFD_ARM_SPECIAL_SYM_TYPE_MAP))
99059e56
RM		 7704 elf32_arm_section_map_add (sec, name[1], isym->st_value);
7705 }
c7b8f16e
JB		 7706 }
7707}
7708
7709
48229727
JB		 7710/* Auto-select enabling of Cortex-A8 erratum fix if the user didn't explicitly
7711 say what they wanted. */
7712
7713void
7714bfd_elf32_arm_set_cortex_a8_fix (bfd *obfd, struct bfd_link_info *link_info)
7715{
7716 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (link_info);
7717 obj_attribute *out_attr = elf_known_obj_attributes_proc (obfd);
7718
4dfe6ac6
NC		 7719 if (globals == NULL)
7720 return;
7721
48229727
JB		 7722 if (globals->fix_cortex_a8 == -1)
7723 {
7724 /* Turn on Cortex-A8 erratum workaround for ARMv7-A. */
7725 if (out_attr[Tag_CPU_arch].i == TAG_CPU_ARCH_V7
7726 && (out_attr[Tag_CPU_arch_profile].i == 'A'
7727 || out_attr[Tag_CPU_arch_profile].i == 0))
7728 globals->fix_cortex_a8 = 1;
7729 else
7730 globals->fix_cortex_a8 = 0;
7731 }
7732}
7733
7734
c7b8f16e
JB		 7735void
7736bfd_elf32_arm_set_vfp11_fix (bfd *obfd, struct bfd_link_info *link_info)
7737{
7738 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (link_info);
104d59d1 7739 obj_attribute *out_attr = elf_known_obj_attributes_proc (obfd);
906e58ca 7740
4dfe6ac6
NC		 7741 if (globals == NULL)
7742 return;
c7b8f16e
JB		 7743 /* We assume that ARMv7+ does not need the VFP11 denorm erratum fix. */
7744 if (out_attr[Tag_CPU_arch].i >= TAG_CPU_ARCH_V7)
7745 {
7746 switch (globals->vfp11_fix)
99059e56
RM		 7747 {
7748 case BFD_ARM_VFP11_FIX_DEFAULT:
7749 case BFD_ARM_VFP11_FIX_NONE:
7750 globals->vfp11_fix = BFD_ARM_VFP11_FIX_NONE;
7751 break;
7752
7753 default:
7754 /* Give a warning, but do as the user requests anyway. */
4eca0228 7755 _bfd_error_handler (_("%B: warning: selected VFP11 erratum "
99059e56
RM		 7756 "workaround is not necessary for target architecture"), obfd);
7757 }
c7b8f16e
JB		 7758 }
7759 else if (globals->vfp11_fix == BFD_ARM_VFP11_FIX_DEFAULT)
7760 /* For earlier architectures, we might need the workaround, but do not
7761 enable it by default. If users is running with broken hardware, they
7762 must enable the erratum fix explicitly. */
7763 globals->vfp11_fix = BFD_ARM_VFP11_FIX_NONE;
7764}
7765
a504d23a
LA		 7766void
7767bfd_elf32_arm_set_stm32l4xx_fix (bfd *obfd, struct bfd_link_info *link_info)
7768{
7769 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (link_info);
7770 obj_attribute *out_attr = elf_known_obj_attributes_proc (obfd);
7771
7772 if (globals == NULL)
7773 return;
7774
7775 /* We assume only Cortex-M4 may require the fix. */
7776 if (out_attr[Tag_CPU_arch].i != TAG_CPU_ARCH_V7E_M
7777 || out_attr[Tag_CPU_arch_profile].i != 'M')
7778 {
7779 if (globals->stm32l4xx_fix != BFD_ARM_STM32L4XX_FIX_NONE)
7780 /* Give a warning, but do as the user requests anyway. */
4eca0228 7781 _bfd_error_handler
a504d23a
LA		 7782 (_("%B: warning: selected STM32L4XX erratum "
7783 "workaround is not necessary for target architecture"), obfd);
7784 }
7785}
c7b8f16e 7786
906e58ca
NC		 7787enum bfd_arm_vfp11_pipe
7788{
c7b8f16e
JB		 7789 VFP11_FMAC,
7790 VFP11_LS,
7791 VFP11_DS,
7792 VFP11_BAD
7793};
7794
7795/* Return a VFP register number. This is encoded as RX:X for single-precision
7796 registers, or X:RX for double-precision registers, where RX is the group of
7797 four bits in the instruction encoding and X is the single extension bit.
7798 RX and X fields are specified using their lowest (starting) bit. The return
7799 value is:
7800
7801 0...31: single-precision registers s0...s31
7802 32...63: double-precision registers d0...d31.
906e58ca 7803
c7b8f16e
JB		 7804 Although X should be zero for VFP11 (encoding d0...d15 only), we might
7805 encounter VFP3 instructions, so we allow the full range for DP registers. */
906e58ca 7806
c7b8f16e
JB		 7807static unsigned int
7808bfd_arm_vfp11_regno (unsigned int insn, bfd_boolean is_double, unsigned int rx,
99059e56 7809 unsigned int x)
c7b8f16e
JB		 7810{
7811 if (is_double)
7812 return (((insn >> rx) & 0xf) | (((insn >> x) & 1) << 4)) + 32;
7813 else
7814 return (((insn >> rx) & 0xf) << 1) | ((insn >> x) & 1);
7815}
7816
7817/* Set bits in *WMASK according to a register number REG as encoded by
7818 bfd_arm_vfp11_regno(). Ignore d16-d31. */
7819
7820static void
7821bfd_arm_vfp11_write_mask (unsigned int *wmask, unsigned int reg)
7822{
7823 if (reg < 32)
7824 *wmask |= 1 << reg;
7825 else if (reg < 48)
7826 *wmask |= 3 << ((reg - 32) * 2);
7827}
7828
7829/* Return TRUE if WMASK overwrites anything in REGS. */
7830
7831static bfd_boolean
7832bfd_arm_vfp11_antidependency (unsigned int wmask, int *regs, int numregs)
7833{
7834 int i;
906e58ca 7835
c7b8f16e
JB		 7836 for (i = 0; i < numregs; i++)
7837 {
7838 unsigned int reg = regs[i];
7839
7840 if (reg < 32 && (wmask & (1 << reg)) != 0)
99059e56 7841 return TRUE;
906e58ca 7842
c7b8f16e
JB		 7843 reg -= 32;
7844
7845 if (reg >= 16)
99059e56 7846 continue;
906e58ca 7847
c7b8f16e 7848 if ((wmask & (3 << (reg * 2))) != 0)
99059e56 7849 return TRUE;
c7b8f16e 7850 }
906e58ca 7851
c7b8f16e
JB		 7852 return FALSE;
7853}
7854
7855/* In this function, we're interested in two things: finding input registers
7856 for VFP data-processing instructions, and finding the set of registers which
7857 arbitrary VFP instructions may write to. We use a 32-bit unsigned int to
7858 hold the written set, so FLDM etc. are easy to deal with (we're only
7859 interested in 32 SP registers or 16 dp registers, due to the VFP version
7860 implemented by the chip in question). DP registers are marked by setting
7861 both SP registers in the write mask). */
7862
7863static enum bfd_arm_vfp11_pipe
7864bfd_arm_vfp11_insn_decode (unsigned int insn, unsigned int *destmask, int *regs,
99059e56 7865 int *numregs)
c7b8f16e 7866{
91d6fa6a 7867 enum bfd_arm_vfp11_pipe vpipe = VFP11_BAD;
c7b8f16e
JB		 7868 bfd_boolean is_double = ((insn & 0xf00) == 0xb00) ? 1 : 0;
7869
7870 if ((insn & 0x0f000e10) == 0x0e000a00) /* A data-processing insn. */
7871 {
7872 unsigned int pqrs;
7873 unsigned int fd = bfd_arm_vfp11_regno (insn, is_double, 12, 22);
7874 unsigned int fm = bfd_arm_vfp11_regno (insn, is_double, 0, 5);
7875
7876 pqrs = ((insn & 0x00800000) >> 20)
99059e56
RM		 7877 | ((insn & 0x00300000) >> 19)
7878 | ((insn & 0x00000040) >> 6);
c7b8f16e
JB		 7879
7880 switch (pqrs)
99059e56
RM		 7881 {
7882 case 0: /* fmac[sd]. */
7883 case 1: /* fnmac[sd]. */
7884 case 2: /* fmsc[sd]. */
7885 case 3: /* fnmsc[sd]. */
7886 vpipe = VFP11_FMAC;
7887 bfd_arm_vfp11_write_mask (destmask, fd);
7888 regs[0] = fd;
7889 regs[1] = bfd_arm_vfp11_regno (insn, is_double, 16, 7); /* Fn. */
7890 regs[2] = fm;
7891 *numregs = 3;
7892 break;
7893
7894 case 4: /* fmul[sd]. */
7895 case 5: /* fnmul[sd]. */
7896 case 6: /* fadd[sd]. */
7897 case 7: /* fsub[sd]. */
7898 vpipe = VFP11_FMAC;
7899 goto vfp_binop;
7900
7901 case 8: /* fdiv[sd]. */
7902 vpipe = VFP11_DS;
7903 vfp_binop:
7904 bfd_arm_vfp11_write_mask (destmask, fd);
7905 regs[0] = bfd_arm_vfp11_regno (insn, is_double, 16, 7); /* Fn. */
7906 regs[1] = fm;
7907 *numregs = 2;
7908 break;
7909
7910 case 15: /* extended opcode. */
7911 {
7912 unsigned int extn = ((insn >> 15) & 0x1e)
7913 | ((insn >> 7) & 1);
7914
7915 switch (extn)
7916 {
7917 case 0: /* fcpy[sd]. */
7918 case 1: /* fabs[sd]. */
7919 case 2: /* fneg[sd]. */
7920 case 8: /* fcmp[sd]. */
7921 case 9: /* fcmpe[sd]. */
7922 case 10: /* fcmpz[sd]. */
7923 case 11: /* fcmpez[sd]. */
7924 case 16: /* fuito[sd]. */
7925 case 17: /* fsito[sd]. */
7926 case 24: /* ftoui[sd]. */
7927 case 25: /* ftouiz[sd]. */
7928 case 26: /* ftosi[sd]. */
7929 case 27: /* ftosiz[sd]. */
7930 /* These instructions will not bounce due to underflow. */
7931 *numregs = 0;
7932 vpipe = VFP11_FMAC;
7933 break;
7934
7935 case 3: /* fsqrt[sd]. */
7936 /* fsqrt cannot underflow, but it can (perhaps) overwrite
7937 registers to cause the erratum in previous instructions. */
7938 bfd_arm_vfp11_write_mask (destmask, fd);
7939 vpipe = VFP11_DS;
7940 break;
7941
7942 case 15: /* fcvt{ds,sd}. */
7943 {
7944 int rnum = 0;
7945
7946 bfd_arm_vfp11_write_mask (destmask, fd);
c7b8f16e
JB		 7947
7948 /* Only FCVTSD can underflow. */
99059e56
RM		 7949 if ((insn & 0x100) != 0)
7950 regs[rnum++] = fm;
c7b8f16e 7951
99059e56 7952 *numregs = rnum;
c7b8f16e 7953
99059e56
RM		 7954 vpipe = VFP11_FMAC;
7955 }
7956 break;
c7b8f16e 7957
99059e56
RM		 7958 default:
7959 return VFP11_BAD;
7960 }
7961 }
7962 break;
c7b8f16e 7963
99059e56
RM		 7964 default:
7965 return VFP11_BAD;
7966 }
c7b8f16e
JB		 7967 }
7968 /* Two-register transfer. */
7969 else if ((insn & 0x0fe00ed0) == 0x0c400a10)
7970 {
7971 unsigned int fm = bfd_arm_vfp11_regno (insn, is_double, 0, 5);
906e58ca 7972
c7b8f16e
JB		 7973 if ((insn & 0x100000) == 0)
7974 {
99059e56
RM		 7975 if (is_double)
7976 bfd_arm_vfp11_write_mask (destmask, fm);
7977 else
7978 {
7979 bfd_arm_vfp11_write_mask (destmask, fm);
7980 bfd_arm_vfp11_write_mask (destmask, fm + 1);
7981 }
c7b8f16e
JB		 7982 }
7983
91d6fa6a 7984 vpipe = VFP11_LS;
c7b8f16e
JB		 7985 }
7986 else if ((insn & 0x0e100e00) == 0x0c100a00) /* A load insn. */
7987 {
7988 int fd = bfd_arm_vfp11_regno (insn, is_double, 12, 22);
7989 unsigned int puw = ((insn >> 21) & 0x1) | (((insn >> 23) & 3) << 1);
906e58ca 7990
c7b8f16e 7991 switch (puw)
99059e56
RM		 7992 {
7993 case 0: /* Two-reg transfer. We should catch these above. */
7994 abort ();
906e58ca 7995
99059e56
RM		 7996 case 2: /* fldm[sdx]. */
7997 case 3:
7998 case 5:
7999 {
8000 unsigned int i, offset = insn & 0xff;
c7b8f16e 8001
99059e56
RM		 8002 if (is_double)
8003 offset >>= 1;
c7b8f16e 8004
99059e56
RM		 8005 for (i = fd; i < fd + offset; i++)
8006 bfd_arm_vfp11_write_mask (destmask, i);
8007 }
8008 break;
906e58ca 8009
99059e56
RM		 8010 case 4: /* fld[sd]. */
8011 case 6:
8012 bfd_arm_vfp11_write_mask (destmask, fd);
8013 break;
906e58ca 8014
99059e56
RM		 8015 default:
8016 return VFP11_BAD;
8017 }
c7b8f16e 8018
91d6fa6a 8019 vpipe = VFP11_LS;
c7b8f16e
JB		 8020 }
8021 /* Single-register transfer. Note L==0. */
8022 else if ((insn & 0x0f100e10) == 0x0e000a10)
8023 {
8024 unsigned int opcode = (insn >> 21) & 7;
8025 unsigned int fn = bfd_arm_vfp11_regno (insn, is_double, 16, 7);
8026
8027 switch (opcode)
99059e56
RM		 8028 {
8029 case 0: /* fmsr/fmdlr. */
8030 case 1: /* fmdhr. */
8031 /* Mark fmdhr and fmdlr as writing to the whole of the DP
8032 destination register. I don't know if this is exactly right,
8033 but it is the conservative choice. */
8034 bfd_arm_vfp11_write_mask (destmask, fn);
8035 break;
8036
8037 case 7: /* fmxr. */
8038 break;
8039 }
c7b8f16e 8040
91d6fa6a 8041 vpipe = VFP11_LS;
c7b8f16e
JB		 8042 }
8043
91d6fa6a 8044 return vpipe;
c7b8f16e
JB		 8045}
8046
8047
8048static int elf32_arm_compare_mapping (const void * a, const void * b);
8049
8050
8051/* Look for potentially-troublesome code sequences which might trigger the
8052 VFP11 denormal/antidependency erratum. See, e.g., the ARM1136 errata sheet
8053 (available from ARM) for details of the erratum. A short version is
8054 described in ld.texinfo. */
8055
8056bfd_boolean
8057bfd_elf32_arm_vfp11_erratum_scan (bfd *abfd, struct bfd_link_info *link_info)
8058{
8059 asection *sec;
8060 bfd_byte *contents = NULL;
8061 int state = 0;
8062 int regs[3], numregs = 0;
8063 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (link_info);
8064 int use_vector = (globals->vfp11_fix == BFD_ARM_VFP11_FIX_VECTOR);
906e58ca 8065
4dfe6ac6
NC		 8066 if (globals == NULL)
8067 return FALSE;
8068
c7b8f16e
JB		 8069 /* We use a simple FSM to match troublesome VFP11 instruction sequences.
8070 The states transition as follows:
906e58ca 8071
c7b8f16e 8072 0 -> 1 (vector) or 0 -> 2 (scalar)
99059e56
RM		 8073 A VFP FMAC-pipeline instruction has been seen. Fill
8074 regs[0]..regs[numregs-1] with its input operands. Remember this
8075 instruction in 'first_fmac'.
c7b8f16e
JB		 8076
8077 1 -> 2
99059e56
RM		 8078 Any instruction, except for a VFP instruction which overwrites
8079 regs[*].
906e58ca 8080
c7b8f16e
JB		 8081 1 -> 3 [ -> 0 ] or
8082 2 -> 3 [ -> 0 ]
99059e56
RM		 8083 A VFP instruction has been seen which overwrites any of regs[*].
8084 We must make a veneer! Reset state to 0 before examining next
8085 instruction.
906e58ca 8086
c7b8f16e 8087 2 -> 0
99059e56
RM		 8088 If we fail to match anything in state 2, reset to state 0 and reset
8089 the instruction pointer to the instruction after 'first_fmac'.
c7b8f16e
JB		 8090
8091 If the VFP11 vector mode is in use, there must be at least two unrelated
8092 instructions between anti-dependent VFP11 instructions to properly avoid
906e58ca 8093 triggering the erratum, hence the use of the extra state 1. */
c7b8f16e
JB		 8094
8095 /* If we are only performing a partial link do not bother
8096 to construct any glue. */
0e1862bb 8097 if (bfd_link_relocatable (link_info))
c7b8f16e
JB		 8098 return TRUE;
8099
0ffa91dd
NC		 8100 /* Skip if this bfd does not correspond to an ELF image. */
8101 if (! is_arm_elf (abfd))
8102 return TRUE;
906e58ca 8103
c7b8f16e
JB		 8104 /* We should have chosen a fix type by the time we get here. */
8105 BFD_ASSERT (globals->vfp11_fix != BFD_ARM_VFP11_FIX_DEFAULT);
8106
8107 if (globals->vfp11_fix == BFD_ARM_VFP11_FIX_NONE)
8108 return TRUE;
2e6030b9 8109
33a7ffc2
JM		 8110 /* Skip this BFD if it corresponds to an executable or dynamic object. */
8111 if ((abfd->flags & (EXEC_P | DYNAMIC)) != 0)
8112 return TRUE;
8113
c7b8f16e
JB		 8114 for (sec = abfd->sections; sec != NULL; sec = sec->next)
8115 {
8116 unsigned int i, span, first_fmac = 0, veneer_of_insn = 0;
8117 struct _arm_elf_section_data *sec_data;
8118
8119 /* If we don't have executable progbits, we're not interested in this
99059e56 8120 section. Also skip if section is to be excluded. */
c7b8f16e 8121 if (elf_section_type (sec) != SHT_PROGBITS
99059e56
RM		 8122 || (elf_section_flags (sec) & SHF_EXECINSTR) == 0
8123 || (sec->flags & SEC_EXCLUDE) != 0
dbaa2011 8124 || sec->sec_info_type == SEC_INFO_TYPE_JUST_SYMS
33a7ffc2 8125 || sec->output_section == bfd_abs_section_ptr
99059e56
RM		 8126 || strcmp (sec->name, VFP11_ERRATUM_VENEER_SECTION_NAME) == 0)
8127 continue;
c7b8f16e
JB		 8128
8129 sec_data = elf32_arm_section_data (sec);
906e58ca 8130
c7b8f16e 8131 if (sec_data->mapcount == 0)
99059e56 8132 continue;
906e58ca 8133
c7b8f16e
JB		 8134 if (elf_section_data (sec)->this_hdr.contents != NULL)
8135 contents = elf_section_data (sec)->this_hdr.contents;
8136 else if (! bfd_malloc_and_get_section (abfd, sec, &contents))
8137 goto error_return;
8138
8139 qsort (sec_data->map, sec_data->mapcount, sizeof (elf32_arm_section_map),
8140 elf32_arm_compare_mapping);
8141
8142 for (span = 0; span < sec_data->mapcount; span++)
99059e56
RM		 8143 {
8144 unsigned int span_start = sec_data->map[span].vma;
8145 unsigned int span_end = (span == sec_data->mapcount - 1)
c7b8f16e 8146 ? sec->size : sec_data->map[span + 1].vma;
99059e56
RM		 8147 char span_type = sec_data->map[span].type;
8148
8149 /* FIXME: Only ARM mode is supported at present. We may need to
8150 support Thumb-2 mode also at some point. */
8151 if (span_type != 'a')
8152 continue;
8153
8154 for (i = span_start; i < span_end;)
8155 {
8156 unsigned int next_i = i + 4;
8157 unsigned int insn = bfd_big_endian (abfd)
8158 ? (contents[i] << 24)
8159 | (contents[i + 1] << 16)
8160 | (contents[i + 2] << 8)
8161 | contents[i + 3]
8162 : (contents[i + 3] << 24)
8163 | (contents[i + 2] << 16)
8164 | (contents[i + 1] << 8)
8165 | contents[i];
8166 unsigned int writemask = 0;
8167 enum bfd_arm_vfp11_pipe vpipe;
8168
8169 switch (state)
8170 {
8171 case 0:
8172 vpipe = bfd_arm_vfp11_insn_decode (insn, &writemask, regs,
8173 &numregs);
8174 /* I'm assuming the VFP11 erratum can trigger with denorm
8175 operands on either the FMAC or the DS pipeline. This might
8176 lead to slightly overenthusiastic veneer insertion. */
8177 if (vpipe == VFP11_FMAC || vpipe == VFP11_DS)
8178 {
8179 state = use_vector ? 1 : 2;
8180 first_fmac = i;
8181 veneer_of_insn = insn;
8182 }
8183 break;
8184
8185 case 1:
8186 {
8187 int other_regs[3], other_numregs;
8188 vpipe = bfd_arm_vfp11_insn_decode (insn, &writemask,
c7b8f16e 8189 other_regs,
99059e56
RM		 8190 &other_numregs);
8191 if (vpipe != VFP11_BAD
8192 && bfd_arm_vfp11_antidependency (writemask, regs,
c7b8f16e 8193 numregs))
99059e56
RM		 8194 state = 3;
8195 else
8196 state = 2;
8197 }
8198 break;
8199
8200 case 2:
8201 {
8202 int other_regs[3], other_numregs;
8203 vpipe = bfd_arm_vfp11_insn_decode (insn, &writemask,
c7b8f16e 8204 other_regs,
99059e56
RM		 8205 &other_numregs);
8206 if (vpipe != VFP11_BAD
8207 && bfd_arm_vfp11_antidependency (writemask, regs,
c7b8f16e 8208 numregs))
99059e56
RM		 8209 state = 3;
8210 else
8211 {
8212 state = 0;
8213 next_i = first_fmac + 4;
8214 }
8215 }
8216 break;
8217
8218 case 3:
8219 abort (); /* Should be unreachable. */
8220 }
8221
8222 if (state == 3)
8223 {
8224 elf32_vfp11_erratum_list *newerr =(elf32_vfp11_erratum_list *)
8225 bfd_zmalloc (sizeof (elf32_vfp11_erratum_list));
8226
8227 elf32_arm_section_data (sec)->erratumcount += 1;
8228
8229 newerr->u.b.vfp_insn = veneer_of_insn;
8230
8231 switch (span_type)
8232 {
8233 case 'a':
8234 newerr->type = VFP11_ERRATUM_BRANCH_TO_ARM_VENEER;
8235 break;
8236
8237 default:
8238 abort ();
8239 }
8240
8241 record_vfp11_erratum_veneer (link_info, newerr, abfd, sec,
c7b8f16e
JB		 8242 first_fmac);
8243
99059e56 8244 newerr->vma = -1;
c7b8f16e 8245
99059e56
RM		 8246 newerr->next = sec_data->erratumlist;
8247 sec_data->erratumlist = newerr;
c7b8f16e 8248
99059e56
RM		 8249 state = 0;
8250 }
c7b8f16e 8251
99059e56
RM		 8252 i = next_i;
8253 }
8254 }
906e58ca 8255
c7b8f16e 8256 if (contents != NULL
99059e56
RM		 8257 && elf_section_data (sec)->this_hdr.contents != contents)
8258 free (contents);
c7b8f16e
JB		 8259 contents = NULL;
8260 }
8261
8262 return TRUE;
8263
8264error_return:
8265 if (contents != NULL
8266 && elf_section_data (sec)->this_hdr.contents != contents)
8267 free (contents);
906e58ca 8268
c7b8f16e
JB		 8269 return FALSE;
8270}
8271
8272/* Find virtual-memory addresses for VFP11 erratum veneers and return locations
8273 after sections have been laid out, using specially-named symbols. */
8274
8275void
8276bfd_elf32_arm_vfp11_fix_veneer_locations (bfd *abfd,
8277 struct bfd_link_info *link_info)
8278{
8279 asection *sec;
8280 struct elf32_arm_link_hash_table *globals;
8281 char *tmp_name;
906e58ca 8282
0e1862bb 8283 if (bfd_link_relocatable (link_info))
c7b8f16e 8284 return;
2e6030b9
MS		 8285
8286 /* Skip if this bfd does not correspond to an ELF image. */
0ffa91dd 8287 if (! is_arm_elf (abfd))
2e6030b9
MS		 8288 return;
8289
c7b8f16e 8290 globals = elf32_arm_hash_table (link_info);
4dfe6ac6
NC		 8291 if (globals == NULL)
8292 return;
906e58ca 8293
21d799b5 8294 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen
99059e56 8295 (VFP11_ERRATUM_VENEER_ENTRY_NAME) + 10);
c7b8f16e
JB		 8296
8297 for (sec = abfd->sections; sec != NULL; sec = sec->next)
8298 {
8299 struct _arm_elf_section_data *sec_data = elf32_arm_section_data (sec);
8300 elf32_vfp11_erratum_list *errnode = sec_data->erratumlist;
906e58ca 8301
c7b8f16e 8302 for (; errnode != NULL; errnode = errnode->next)
99059e56
RM		 8303 {
8304 struct elf_link_hash_entry *myh;
8305 bfd_vma vma;
8306
8307 switch (errnode->type)
8308 {
8309 case VFP11_ERRATUM_BRANCH_TO_ARM_VENEER:
8310 case VFP11_ERRATUM_BRANCH_TO_THUMB_VENEER:
8311 /* Find veneer symbol. */
8312 sprintf (tmp_name, VFP11_ERRATUM_VENEER_ENTRY_NAME,
c7b8f16e
JB		 8313 errnode->u.b.veneer->u.v.id);
8314
99059e56
RM		 8315 myh = elf_link_hash_lookup
8316 (&(globals)->root, tmp_name, FALSE, FALSE, TRUE);
c7b8f16e 8317
a504d23a 8318 if (myh == NULL)
4eca0228
AM		 8319 _bfd_error_handler (_("%B: unable to find VFP11 veneer "
8320 "`%s'"), abfd, tmp_name);
a504d23a
LA		 8321
8322 vma = myh->root.u.def.section->output_section->vma
8323 + myh->root.u.def.section->output_offset
8324 + myh->root.u.def.value;
8325
8326 errnode->u.b.veneer->vma = vma;
8327 break;
8328
8329 case VFP11_ERRATUM_ARM_VENEER:
8330 case VFP11_ERRATUM_THUMB_VENEER:
8331 /* Find return location. */
8332 sprintf (tmp_name, VFP11_ERRATUM_VENEER_ENTRY_NAME "_r",
8333 errnode->u.v.id);
8334
8335 myh = elf_link_hash_lookup
8336 (&(globals)->root, tmp_name, FALSE, FALSE, TRUE);
8337
8338 if (myh == NULL)
4eca0228
AM		 8339 _bfd_error_handler (_("%B: unable to find VFP11 veneer "
8340 "`%s'"), abfd, tmp_name);
a504d23a
LA		 8341
8342 vma = myh->root.u.def.section->output_section->vma
8343 + myh->root.u.def.section->output_offset
8344 + myh->root.u.def.value;
8345
8346 errnode->u.v.branch->vma = vma;
8347 break;
8348
8349 default:
8350 abort ();
8351 }
8352 }
8353 }
8354
8355 free (tmp_name);
8356}
8357
8358/* Find virtual-memory addresses for STM32L4XX erratum veneers and
8359 return locations after sections have been laid out, using
8360 specially-named symbols. */
8361
8362void
8363bfd_elf32_arm_stm32l4xx_fix_veneer_locations (bfd *abfd,
8364 struct bfd_link_info *link_info)
8365{
8366 asection *sec;
8367 struct elf32_arm_link_hash_table *globals;
8368 char *tmp_name;
8369
8370 if (bfd_link_relocatable (link_info))
8371 return;
8372
8373 /* Skip if this bfd does not correspond to an ELF image. */
8374 if (! is_arm_elf (abfd))
8375 return;
8376
8377 globals = elf32_arm_hash_table (link_info);
8378 if (globals == NULL)
8379 return;
8380
8381 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen
8382 (STM32L4XX_ERRATUM_VENEER_ENTRY_NAME) + 10);
8383
8384 for (sec = abfd->sections; sec != NULL; sec = sec->next)
8385 {
8386 struct _arm_elf_section_data *sec_data = elf32_arm_section_data (sec);
8387 elf32_stm32l4xx_erratum_list *errnode = sec_data->stm32l4xx_erratumlist;
8388
8389 for (; errnode != NULL; errnode = errnode->next)
8390 {
8391 struct elf_link_hash_entry *myh;
8392 bfd_vma vma;
8393
8394 switch (errnode->type)
8395 {
8396 case STM32L4XX_ERRATUM_BRANCH_TO_VENEER:
8397 /* Find veneer symbol. */
8398 sprintf (tmp_name, STM32L4XX_ERRATUM_VENEER_ENTRY_NAME,
8399 errnode->u.b.veneer->u.v.id);
8400
8401 myh = elf_link_hash_lookup
8402 (&(globals)->root, tmp_name, FALSE, FALSE, TRUE);
8403
8404 if (myh == NULL)
4eca0228
AM		 8405 _bfd_error_handler (_("%B: unable to find STM32L4XX veneer "
8406 "`%s'"), abfd, tmp_name);
a504d23a
LA		 8407
8408 vma = myh->root.u.def.section->output_section->vma
8409 + myh->root.u.def.section->output_offset
8410 + myh->root.u.def.value;
8411
8412 errnode->u.b.veneer->vma = vma;
8413 break;
8414
8415 case STM32L4XX_ERRATUM_VENEER:
8416 /* Find return location. */
8417 sprintf (tmp_name, STM32L4XX_ERRATUM_VENEER_ENTRY_NAME "_r",
8418 errnode->u.v.id);
8419
8420 myh = elf_link_hash_lookup
8421 (&(globals)->root, tmp_name, FALSE, FALSE, TRUE);
8422
8423 if (myh == NULL)
4eca0228
AM		 8424 _bfd_error_handler (_("%B: unable to find STM32L4XX veneer "
8425 "`%s'"), abfd, tmp_name);
a504d23a
LA		 8426
8427 vma = myh->root.u.def.section->output_section->vma
8428 + myh->root.u.def.section->output_offset
8429 + myh->root.u.def.value;
8430
8431 errnode->u.v.branch->vma = vma;
8432 break;
8433
8434 default:
8435 abort ();
8436 }
8437 }
8438 }
8439
8440 free (tmp_name);
8441}
8442
8443static inline bfd_boolean
8444is_thumb2_ldmia (const insn32 insn)
8445{
8446 /* Encoding T2: LDM<c>.W <Rn>{!},<registers>
8447 1110 - 1000 - 10W1 - rrrr - PM (0) l - llll - llll - llll. */
8448 return (insn & 0xffd02000) == 0xe8900000;
8449}
8450
8451static inline bfd_boolean
8452is_thumb2_ldmdb (const insn32 insn)
8453{
8454 /* Encoding T1: LDMDB<c> <Rn>{!},<registers>
8455 1110 - 1001 - 00W1 - rrrr - PM (0) l - llll - llll - llll. */
8456 return (insn & 0xffd02000) == 0xe9100000;
8457}
8458
8459static inline bfd_boolean
8460is_thumb2_vldm (const insn32 insn)
8461{
8462 /* A6.5 Extension register load or store instruction
8463 A7.7.229
9239bbd3
CM		 8464 We look for SP 32-bit and DP 64-bit registers.
8465 Encoding T1 VLDM{mode}<c> <Rn>{!}, <list>
8466 <list> is consecutive 64-bit registers
8467 1110 - 110P - UDW1 - rrrr - vvvv - 1011 - iiii - iiii
a504d23a
LA		 8468 Encoding T2 VLDM{mode}<c> <Rn>{!}, <list>
8469 <list> is consecutive 32-bit registers
8470 1110 - 110P - UDW1 - rrrr - vvvv - 1010 - iiii - iiii
8471 if P==0 && U==1 && W==1 && Rn=1101 VPOP
8472 if PUW=010 || PUW=011 || PUW=101 VLDM. */
8473 return
9239bbd3
CM		 8474 (((insn & 0xfe100f00) == 0xec100b00) ||
8475 ((insn & 0xfe100f00) == 0xec100a00))
a504d23a
LA		 8476 && /* (IA without !). */
8477 (((((insn << 7) >> 28) & 0xd) == 0x4)
9239bbd3 8478 /* (IA with !), includes VPOP (when reg number is SP). */
a504d23a
LA		 8479 || ((((insn << 7) >> 28) & 0xd) == 0x5)
8480 /* (DB with !). */
8481 || ((((insn << 7) >> 28) & 0xd) == 0x9));
8482}
8483
8484/* STM STM32L4XX erratum : This function assumes that it receives an LDM or
8485 VLDM opcode and:
8486 - computes the number and the mode of memory accesses
8487 - decides if the replacement should be done:
8488 . replaces only if > 8-word accesses
8489 . or (testing purposes only) replaces all accesses. */
8490
8491static bfd_boolean
8492stm32l4xx_need_create_replacing_stub (const insn32 insn,
8493 bfd_arm_stm32l4xx_fix stm32l4xx_fix)
8494{
9239bbd3 8495 int nb_words = 0;
a504d23a
LA		 8496
8497 /* The field encoding the register list is the same for both LDMIA
8498 and LDMDB encodings. */
8499 if (is_thumb2_ldmia (insn) || is_thumb2_ldmdb (insn))
b25e998d 8500 nb_words = elf32_arm_popcount (insn & 0x0000ffff);
a504d23a 8501 else if (is_thumb2_vldm (insn))
9239bbd3 8502 nb_words = (insn & 0xff);
a504d23a
LA		 8503
8504 /* DEFAULT mode accounts for the real bug condition situation,
8505 ALL mode inserts stubs for each LDM/VLDM instruction (testing). */
8506 return
9239bbd3 8507 (stm32l4xx_fix == BFD_ARM_STM32L4XX_FIX_DEFAULT) ? nb_words > 8 :
a504d23a
LA		 8508 (stm32l4xx_fix == BFD_ARM_STM32L4XX_FIX_ALL) ? TRUE : FALSE;
8509}
8510
8511/* Look for potentially-troublesome code sequences which might trigger
8512 the STM STM32L4XX erratum. */
8513
8514bfd_boolean
8515bfd_elf32_arm_stm32l4xx_erratum_scan (bfd *abfd,
8516 struct bfd_link_info *link_info)
8517{
8518 asection *sec;
8519 bfd_byte *contents = NULL;
8520 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (link_info);
8521
8522 if (globals == NULL)
8523 return FALSE;
8524
8525 /* If we are only performing a partial link do not bother
8526 to construct any glue. */
8527 if (bfd_link_relocatable (link_info))
8528 return TRUE;
8529
8530 /* Skip if this bfd does not correspond to an ELF image. */
8531 if (! is_arm_elf (abfd))
8532 return TRUE;
8533
8534 if (globals->stm32l4xx_fix == BFD_ARM_STM32L4XX_FIX_NONE)
8535 return TRUE;
8536
8537 /* Skip this BFD if it corresponds to an executable or dynamic object. */
8538 if ((abfd->flags & (EXEC_P | DYNAMIC)) != 0)
8539 return TRUE;
8540
8541 for (sec = abfd->sections; sec != NULL; sec = sec->next)
8542 {
8543 unsigned int i, span;
8544 struct _arm_elf_section_data *sec_data;
8545
8546 /* If we don't have executable progbits, we're not interested in this
8547 section. Also skip if section is to be excluded. */
8548 if (elf_section_type (sec) != SHT_PROGBITS
8549 || (elf_section_flags (sec) & SHF_EXECINSTR) == 0
8550 || (sec->flags & SEC_EXCLUDE) != 0
8551 || sec->sec_info_type == SEC_INFO_TYPE_JUST_SYMS
8552 || sec->output_section == bfd_abs_section_ptr
8553 || strcmp (sec->name, STM32L4XX_ERRATUM_VENEER_SECTION_NAME) == 0)
8554 continue;
8555
8556 sec_data = elf32_arm_section_data (sec);
c7b8f16e 8557
a504d23a
LA		 8558 if (sec_data->mapcount == 0)
8559 continue;
c7b8f16e 8560
a504d23a
LA		 8561 if (elf_section_data (sec)->this_hdr.contents != NULL)
8562 contents = elf_section_data (sec)->this_hdr.contents;
8563 else if (! bfd_malloc_and_get_section (abfd, sec, &contents))
8564 goto error_return;
c7b8f16e 8565
a504d23a
LA		 8566 qsort (sec_data->map, sec_data->mapcount, sizeof (elf32_arm_section_map),
8567 elf32_arm_compare_mapping);
c7b8f16e 8568
a504d23a
LA		 8569 for (span = 0; span < sec_data->mapcount; span++)
8570 {
8571 unsigned int span_start = sec_data->map[span].vma;
8572 unsigned int span_end = (span == sec_data->mapcount - 1)
8573 ? sec->size : sec_data->map[span + 1].vma;
8574 char span_type = sec_data->map[span].type;
8575 int itblock_current_pos = 0;
c7b8f16e 8576
a504d23a
LA		 8577 /* Only Thumb2 mode need be supported with this CM4 specific
8578 code, we should not encounter any arm mode eg span_type
8579 != 'a'. */
8580 if (span_type != 't')
8581 continue;
c7b8f16e 8582
a504d23a
LA		 8583 for (i = span_start; i < span_end;)
8584 {
8585 unsigned int insn = bfd_get_16 (abfd, &contents[i]);
8586 bfd_boolean insn_32bit = FALSE;
8587 bfd_boolean is_ldm = FALSE;
8588 bfd_boolean is_vldm = FALSE;
8589 bfd_boolean is_not_last_in_it_block = FALSE;
8590
8591 /* The first 16-bits of all 32-bit thumb2 instructions start
8592 with opcode[15..13]=0b111 and the encoded op1 can be anything
8593 except opcode[12..11]!=0b00.
8594 See 32-bit Thumb instruction encoding. */
8595 if ((insn & 0xe000) == 0xe000 && (insn & 0x1800) != 0x0000)
8596 insn_32bit = TRUE;
c7b8f16e 8597
a504d23a
LA		 8598 /* Compute the predicate that tells if the instruction
8599 is concerned by the IT block
8600 - Creates an error if there is a ldm that is not
8601 last in the IT block thus cannot be replaced
8602 - Otherwise we can create a branch at the end of the
8603 IT block, it will be controlled naturally by IT
8604 with the proper pseudo-predicate
8605 - So the only interesting predicate is the one that
8606 tells that we are not on the last item of an IT
8607 block. */
8608 if (itblock_current_pos != 0)
8609 is_not_last_in_it_block = !!--itblock_current_pos;
906e58ca 8610
a504d23a
LA		 8611 if (insn_32bit)
8612 {
8613 /* Load the rest of the insn (in manual-friendly order). */
8614 insn = (insn << 16) | bfd_get_16 (abfd, &contents[i + 2]);
8615 is_ldm = is_thumb2_ldmia (insn) || is_thumb2_ldmdb (insn);
8616 is_vldm = is_thumb2_vldm (insn);
8617
8618 /* Veneers are created for (v)ldm depending on
8619 option flags and memory accesses conditions; but
8620 if the instruction is not the last instruction of
8621 an IT block, we cannot create a jump there, so we
8622 bail out. */
5025eb7c
AO		 8623 if ((is_ldm || is_vldm)
8624 && stm32l4xx_need_create_replacing_stub
a504d23a
LA		 8625 (insn, globals->stm32l4xx_fix))
8626 {
8627 if (is_not_last_in_it_block)
8628 {
4eca0228 8629 _bfd_error_handler
a504d23a 8630 /* Note - overlong line used here to allow for translation. */
695344c0 8631 /* xgettext:c-format */
a504d23a
LA		 8632 (_("\
8633%B(%A+0x%lx): error: multiple load detected in non-last IT block instruction : STM32L4XX veneer cannot be generated.\n"
8634 "Use gcc option -mrestrict-it to generate only one instruction per IT block.\n"),
695344c0 8635 abfd, sec, (long) i);
a504d23a
LA		 8636 }
8637 else
8638 {
8639 elf32_stm32l4xx_erratum_list *newerr =
8640 (elf32_stm32l4xx_erratum_list *)
8641 bfd_zmalloc
8642 (sizeof (elf32_stm32l4xx_erratum_list));
8643
8644 elf32_arm_section_data (sec)
8645 ->stm32l4xx_erratumcount += 1;
8646 newerr->u.b.insn = insn;
8647 /* We create only thumb branches. */
8648 newerr->type =
8649 STM32L4XX_ERRATUM_BRANCH_TO_VENEER;
8650 record_stm32l4xx_erratum_veneer
8651 (link_info, newerr, abfd, sec,
8652 i,
8653 is_ldm ?
8654 STM32L4XX_ERRATUM_LDM_VENEER_SIZE:
8655 STM32L4XX_ERRATUM_VLDM_VENEER_SIZE);
8656 newerr->vma = -1;
8657 newerr->next = sec_data->stm32l4xx_erratumlist;
8658 sec_data->stm32l4xx_erratumlist = newerr;
8659 }
8660 }
8661 }
8662 else
8663 {
8664 /* A7.7.37 IT p208
8665 IT blocks are only encoded in T1
8666 Encoding T1: IT{x{y{z}}} <firstcond>
8667 1 0 1 1 - 1 1 1 1 - firstcond - mask
8668 if mask = '0000' then see 'related encodings'
8669 We don't deal with UNPREDICTABLE, just ignore these.
8670 There can be no nested IT blocks so an IT block
8671 is naturally a new one for which it is worth
8672 computing its size. */
5025eb7c
AO		 8673 bfd_boolean is_newitblock = ((insn & 0xff00) == 0xbf00)
8674 && ((insn & 0x000f) != 0x0000);
a504d23a
LA		 8675 /* If we have a new IT block we compute its size. */
8676 if (is_newitblock)
8677 {
8678 /* Compute the number of instructions controlled
8679 by the IT block, it will be used to decide
8680 whether we are inside an IT block or not. */
8681 unsigned int mask = insn & 0x000f;
8682 itblock_current_pos = 4 - ctz (mask);
8683 }
8684 }
8685
8686 i += insn_32bit ? 4 : 2;
99059e56
RM		 8687 }
8688 }
a504d23a
LA		 8689
8690 if (contents != NULL
8691 && elf_section_data (sec)->this_hdr.contents != contents)
8692 free (contents);
8693 contents = NULL;
c7b8f16e 8694 }
906e58ca 8695
a504d23a
LA		 8696 return TRUE;
8697
8698error_return:
8699 if (contents != NULL
8700 && elf_section_data (sec)->this_hdr.contents != contents)
8701 free (contents);
c7b8f16e 8702
a504d23a
LA		 8703 return FALSE;
8704}
c7b8f16e 8705
eb043451
PB		 8706/* Set target relocation values needed during linking. */
8707
8708void
68c39892 8709bfd_elf32_arm_set_target_params (struct bfd *output_bfd,
bf21ed78 8710 struct bfd_link_info *link_info,
68c39892 8711 struct elf32_arm_params *params)
eb043451
PB		 8712{
8713 struct elf32_arm_link_hash_table *globals;
8714
8715 globals = elf32_arm_hash_table (link_info);
4dfe6ac6
NC		 8716 if (globals == NULL)
8717 return;
eb043451 8718
68c39892
TP		 8719 globals->target1_is_rel = params->target1_is_rel;
8720 if (strcmp (params->target2_type, "rel") == 0)
eb043451 8721 globals->target2_reloc = R_ARM_REL32;
68c39892 8722 else if (strcmp (params->target2_type, "abs") == 0)
eeac373a 8723 globals->target2_reloc = R_ARM_ABS32;
68c39892 8724 else if (strcmp (params->target2_type, "got-rel") == 0)
eb043451
PB		 8725 globals->target2_reloc = R_ARM_GOT_PREL;
8726 else
8727 {
8728 _bfd_error_handler (_("Invalid TARGET2 relocation type '%s'."),
68c39892 8729 params->target2_type);
eb043451 8730 }
68c39892
TP		 8731 globals->fix_v4bx = params->fix_v4bx;
8732 globals->use_blx |= params->use_blx;
8733 globals->vfp11_fix = params->vfp11_denorm_fix;
8734 globals->stm32l4xx_fix = params->stm32l4xx_fix;
8735 globals->pic_veneer = params->pic_veneer;
8736 globals->fix_cortex_a8 = params->fix_cortex_a8;
8737 globals->fix_arm1176 = params->fix_arm1176;
8738 globals->cmse_implib = params->cmse_implib;
8739 globals->in_implib_bfd = params->in_implib_bfd;
bf21ed78 8740
0ffa91dd 8741 BFD_ASSERT (is_arm_elf (output_bfd));
68c39892
TP		 8742 elf_arm_tdata (output_bfd)->no_enum_size_warning
8743 = params->no_enum_size_warning;
8744 elf_arm_tdata (output_bfd)->no_wchar_size_warning
8745 = params->no_wchar_size_warning;
eb043451 8746}
eb043451 8747
12a0a0fd 8748/* Replace the target offset of a Thumb bl or b.w instruction. */
252b5132 8749
12a0a0fd
PB		 8750static void
8751insert_thumb_branch (bfd *abfd, long int offset, bfd_byte *insn)
8752{
8753 bfd_vma upper;
8754 bfd_vma lower;
8755 int reloc_sign;
8756
8757 BFD_ASSERT ((offset & 1) == 0);
8758
8759 upper = bfd_get_16 (abfd, insn);
8760 lower = bfd_get_16 (abfd, insn + 2);
8761 reloc_sign = (offset < 0) ? 1 : 0;
8762 upper = (upper & ~(bfd_vma) 0x7ff)
8763 | ((offset >> 12) & 0x3ff)
8764 | (reloc_sign << 10);
906e58ca 8765 lower = (lower & ~(bfd_vma) 0x2fff)
12a0a0fd
PB		 8766 | (((!((offset >> 23) & 1)) ^ reloc_sign) << 13)
8767 | (((!((offset >> 22) & 1)) ^ reloc_sign) << 11)
8768 | ((offset >> 1) & 0x7ff);
8769 bfd_put_16 (abfd, upper, insn);
8770 bfd_put_16 (abfd, lower, insn + 2);
252b5132
RH		 8771}
8772
9b485d32
NC		 8773/* Thumb code calling an ARM function. */
8774
252b5132 8775static int
57e8b36a
NC		 8776elf32_thumb_to_arm_stub (struct bfd_link_info * info,
8777 const char * name,
8778 bfd * input_bfd,
8779 bfd * output_bfd,
8780 asection * input_section,
8781 bfd_byte * hit_data,
8782 asection * sym_sec,
8783 bfd_vma offset,
8784 bfd_signed_vma addend,
f2a9dd69
DJ		 8785 bfd_vma val,
8786 char **error_message)
252b5132 8787{
bcbdc74c 8788 asection * s = 0;
dc810e39 8789 bfd_vma my_offset;
252b5132 8790 long int ret_offset;
bcbdc74c
NC		 8791 struct elf_link_hash_entry * myh;
8792 struct elf32_arm_link_hash_table * globals;
252b5132 8793
f2a9dd69 8794 myh = find_thumb_glue (info, name, error_message);
252b5132 8795 if (myh == NULL)
b34976b6 8796 return FALSE;
252b5132
RH		 8797
8798 globals = elf32_arm_hash_table (info);
252b5132
RH		 8799 BFD_ASSERT (globals != NULL);
8800 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
8801
8802 my_offset = myh->root.u.def.value;
8803
3d4d4302
AM		 8804 s = bfd_get_linker_section (globals->bfd_of_glue_owner,
8805 THUMB2ARM_GLUE_SECTION_NAME);
252b5132
RH		 8806
8807 BFD_ASSERT (s != NULL);
8808 BFD_ASSERT (s->contents != NULL);
8809 BFD_ASSERT (s->output_section != NULL);
8810
8811 if ((my_offset & 0x01) == 0x01)
8812 {
8813 if (sym_sec != NULL
8814 && sym_sec->owner != NULL
8815 && !INTERWORK_FLAG (sym_sec->owner))
8816 {
4eca0228 8817 _bfd_error_handler
d003868e 8818 (_("%B(%s): warning: interworking not enabled.\n"
3aaeb7d3 8819 " first occurrence: %B: Thumb call to ARM"),
d003868e 8820 sym_sec->owner, input_bfd, name);
252b5132 8821
b34976b6 8822 return FALSE;
252b5132
RH		 8823 }
8824
8825 --my_offset;
8826 myh->root.u.def.value = my_offset;
8827
52ab56c2
PB		 8828 put_thumb_insn (globals, output_bfd, (bfd_vma) t2a1_bx_pc_insn,
8829 s->contents + my_offset);
252b5132 8830
52ab56c2
PB		 8831 put_thumb_insn (globals, output_bfd, (bfd_vma) t2a2_noop_insn,
8832 s->contents + my_offset + 2);
252b5132
RH		 8833
8834 ret_offset =
9b485d32
NC		 8835 /* Address of destination of the stub. */
8836 ((bfd_signed_vma) val)
252b5132 8837 - ((bfd_signed_vma)
57e8b36a
NC		 8838 /* Offset from the start of the current section
8839 to the start of the stubs. */
9b485d32
NC		 8840 (s->output_offset
8841 /* Offset of the start of this stub from the start of the stubs. */
8842 + my_offset
8843 /* Address of the start of the current section. */
8844 + s->output_section->vma)
8845 /* The branch instruction is 4 bytes into the stub. */
8846 + 4
8847 /* ARM branches work from the pc of the instruction + 8. */
8848 + 8);
252b5132 8849
52ab56c2
PB		 8850 put_arm_insn (globals, output_bfd,
8851 (bfd_vma) t2a3_b_insn | ((ret_offset >> 2) & 0x00FFFFFF),
8852 s->contents + my_offset + 4);
252b5132
RH		 8853 }
8854
8855 BFD_ASSERT (my_offset <= globals->thumb_glue_size);
8856
427bfd90
NC		 8857 /* Now go back and fix up the original BL insn to point to here. */
8858 ret_offset =
8859 /* Address of where the stub is located. */
8860 (s->output_section->vma + s->output_offset + my_offset)
8861 /* Address of where the BL is located. */
57e8b36a
NC		 8862 - (input_section->output_section->vma + input_section->output_offset
8863 + offset)
427bfd90
NC		 8864 /* Addend in the relocation. */
8865 - addend
8866 /* Biassing for PC-relative addressing. */
8867 - 8;
252b5132 8868
12a0a0fd 8869 insert_thumb_branch (input_bfd, ret_offset, hit_data - input_section->vma);
252b5132 8870
b34976b6 8871 return TRUE;
252b5132
RH		 8872}
8873
a4fd1a8e 8874/* Populate an Arm to Thumb stub. Returns the stub symbol. */
9b485d32 8875
a4fd1a8e
PB		 8876static struct elf_link_hash_entry *
8877elf32_arm_create_thumb_stub (struct bfd_link_info * info,
8878 const char * name,
8879 bfd * input_bfd,
8880 bfd * output_bfd,
8881 asection * sym_sec,
8882 bfd_vma val,
8029a119
NC		 8883 asection * s,
8884 char ** error_message)
252b5132 8885{
dc810e39 8886 bfd_vma my_offset;
252b5132 8887 long int ret_offset;
bcbdc74c
NC		 8888 struct elf_link_hash_entry * myh;
8889 struct elf32_arm_link_hash_table * globals;
252b5132 8890
f2a9dd69 8891 myh = find_arm_glue (info, name, error_message);
252b5132 8892 if (myh == NULL)
a4fd1a8e 8893 return NULL;
252b5132
RH		 8894
8895 globals = elf32_arm_hash_table (info);
252b5132
RH		 8896 BFD_ASSERT (globals != NULL);
8897 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
8898
8899 my_offset = myh->root.u.def.value;
252b5132
RH		 8900
8901 if ((my_offset & 0x01) == 0x01)
8902 {
8903 if (sym_sec != NULL
8904 && sym_sec->owner != NULL
8905 && !INTERWORK_FLAG (sym_sec->owner))
8906 {
4eca0228 8907 _bfd_error_handler
d003868e
AM		 8908 (_("%B(%s): warning: interworking not enabled.\n"
8909 " first occurrence: %B: arm call to thumb"),
8910 sym_sec->owner, input_bfd, name);
252b5132 8911 }
9b485d32 8912
252b5132
RH		 8913 --my_offset;
8914 myh->root.u.def.value = my_offset;
8915
0e1862bb
L		 8916 if (bfd_link_pic (info)
8917 || globals->root.is_relocatable_executable
27e55c4d 8918 || globals->pic_veneer)
8f6277f5
PB		 8919 {
8920 /* For relocatable objects we can't use absolute addresses,
8921 so construct the address from a relative offset. */
8922 /* TODO: If the offset is small it's probably worth
8923 constructing the address with adds. */
52ab56c2
PB		 8924 put_arm_insn (globals, output_bfd, (bfd_vma) a2t1p_ldr_insn,
8925 s->contents + my_offset);
8926 put_arm_insn (globals, output_bfd, (bfd_vma) a2t2p_add_pc_insn,
8927 s->contents + my_offset + 4);
8928 put_arm_insn (globals, output_bfd, (bfd_vma) a2t3p_bx_r12_insn,
8929 s->contents + my_offset + 8);
8f6277f5
PB		 8930 /* Adjust the offset by 4 for the position of the add,
8931 and 8 for the pipeline offset. */
8932 ret_offset = (val - (s->output_offset
8933 + s->output_section->vma
8934 + my_offset + 12))
8935 | 1;
8936 bfd_put_32 (output_bfd, ret_offset,
8937 s->contents + my_offset + 12);
8938 }
26079076
PB		 8939 else if (globals->use_blx)
8940 {
8941 put_arm_insn (globals, output_bfd, (bfd_vma) a2t1v5_ldr_insn,
8942 s->contents + my_offset);
8943
8944 /* It's a thumb address. Add the low order bit. */
8945 bfd_put_32 (output_bfd, val | a2t2v5_func_addr_insn,
8946 s->contents + my_offset + 4);
8947 }
8f6277f5
PB		 8948 else
8949 {
52ab56c2
PB		 8950 put_arm_insn (globals, output_bfd, (bfd_vma) a2t1_ldr_insn,
8951 s->contents + my_offset);
252b5132 8952
52ab56c2
PB		 8953 put_arm_insn (globals, output_bfd, (bfd_vma) a2t2_bx_r12_insn,
8954 s->contents + my_offset + 4);
252b5132 8955
8f6277f5
PB		 8956 /* It's a thumb address. Add the low order bit. */
8957 bfd_put_32 (output_bfd, val | a2t3_func_addr_insn,
8958 s->contents + my_offset + 8);
8029a119
NC		 8959
8960 my_offset += 12;
8f6277f5 8961 }
252b5132
RH		 8962 }
8963
8964 BFD_ASSERT (my_offset <= globals->arm_glue_size);
8965
a4fd1a8e
PB		 8966 return myh;
8967}
8968
8969/* Arm code calling a Thumb function. */
8970
8971static int
8972elf32_arm_to_thumb_stub (struct bfd_link_info * info,
8973 const char * name,
8974 bfd * input_bfd,
8975 bfd * output_bfd,
8976 asection * input_section,
8977 bfd_byte * hit_data,
8978 asection * sym_sec,
8979 bfd_vma offset,
8980 bfd_signed_vma addend,
f2a9dd69
DJ		 8981 bfd_vma val,
8982 char **error_message)
a4fd1a8e
PB		 8983{
8984 unsigned long int tmp;
8985 bfd_vma my_offset;
8986 asection * s;
8987 long int ret_offset;
8988 struct elf_link_hash_entry * myh;
8989 struct elf32_arm_link_hash_table * globals;
8990
8991 globals = elf32_arm_hash_table (info);
a4fd1a8e
PB		 8992 BFD_ASSERT (globals != NULL);
8993 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
8994
3d4d4302
AM		 8995 s = bfd_get_linker_section (globals->bfd_of_glue_owner,
8996 ARM2THUMB_GLUE_SECTION_NAME);
a4fd1a8e
PB		 8997 BFD_ASSERT (s != NULL);
8998 BFD_ASSERT (s->contents != NULL);
8999 BFD_ASSERT (s->output_section != NULL);
9000
9001 myh = elf32_arm_create_thumb_stub (info, name, input_bfd, output_bfd,
f2a9dd69 9002 sym_sec, val, s, error_message);
a4fd1a8e
PB		 9003 if (!myh)
9004 return FALSE;
9005
9006 my_offset = myh->root.u.def.value;
252b5132
RH		 9007 tmp = bfd_get_32 (input_bfd, hit_data);
9008 tmp = tmp & 0xFF000000;
9009
9b485d32 9010 /* Somehow these are both 4 too far, so subtract 8. */
dc810e39
AM		 9011 ret_offset = (s->output_offset
9012 + my_offset
9013 + s->output_section->vma
9014 - (input_section->output_offset
9015 + input_section->output_section->vma
9016 + offset + addend)
9017 - 8);
9a5aca8c 9018
252b5132
RH		 9019 tmp = tmp | ((ret_offset >> 2) & 0x00FFFFFF);
9020
dc810e39 9021 bfd_put_32 (output_bfd, (bfd_vma) tmp, hit_data - input_section->vma);
252b5132 9022
b34976b6 9023 return TRUE;
252b5132
RH		 9024}
9025
a4fd1a8e
PB		 9026/* Populate Arm stub for an exported Thumb function. */
9027
9028static bfd_boolean
9029elf32_arm_to_thumb_export_stub (struct elf_link_hash_entry *h, void * inf)
9030{
9031 struct bfd_link_info * info = (struct bfd_link_info *) inf;
9032 asection * s;
9033 struct elf_link_hash_entry * myh;
9034 struct elf32_arm_link_hash_entry *eh;
9035 struct elf32_arm_link_hash_table * globals;
9036 asection *sec;
9037 bfd_vma val;
f2a9dd69 9038 char *error_message;
a4fd1a8e 9039
906e58ca 9040 eh = elf32_arm_hash_entry (h);
a4fd1a8e
PB		 9041 /* Allocate stubs for exported Thumb functions on v4t. */
9042 if (eh->export_glue == NULL)
9043 return TRUE;
9044
9045 globals = elf32_arm_hash_table (info);
a4fd1a8e
PB		 9046 BFD_ASSERT (globals != NULL);
9047 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
9048
3d4d4302
AM		 9049 s = bfd_get_linker_section (globals->bfd_of_glue_owner,
9050 ARM2THUMB_GLUE_SECTION_NAME);
a4fd1a8e
PB		 9051 BFD_ASSERT (s != NULL);
9052 BFD_ASSERT (s->contents != NULL);
9053 BFD_ASSERT (s->output_section != NULL);
9054
9055 sec = eh->export_glue->root.u.def.section;
0eaedd0e
PB		 9056
9057 BFD_ASSERT (sec->output_section != NULL);
9058
a4fd1a8e
PB		 9059 val = eh->export_glue->root.u.def.value + sec->output_offset
9060 + sec->output_section->vma;
8029a119 9061
a4fd1a8e
PB		 9062 myh = elf32_arm_create_thumb_stub (info, h->root.root.string,
9063 h->root.u.def.section->owner,
f2a9dd69
DJ		 9064 globals->obfd, sec, val, s,
9065 &error_message);
a4fd1a8e
PB		 9066 BFD_ASSERT (myh);
9067 return TRUE;
9068}
9069
845b51d6
PB		 9070/* Populate ARMv4 BX veneers. Returns the absolute adress of the veneer. */
9071
9072static bfd_vma
9073elf32_arm_bx_glue (struct bfd_link_info * info, int reg)
9074{
9075 bfd_byte *p;
9076 bfd_vma glue_addr;
9077 asection *s;
9078 struct elf32_arm_link_hash_table *globals;
9079
9080 globals = elf32_arm_hash_table (info);
845b51d6
PB		 9081 BFD_ASSERT (globals != NULL);
9082 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
9083
3d4d4302
AM		 9084 s = bfd_get_linker_section (globals->bfd_of_glue_owner,
9085 ARM_BX_GLUE_SECTION_NAME);
845b51d6
PB		 9086 BFD_ASSERT (s != NULL);
9087 BFD_ASSERT (s->contents != NULL);
9088 BFD_ASSERT (s->output_section != NULL);
9089
9090 BFD_ASSERT (globals->bx_glue_offset[reg] & 2);
9091
9092 glue_addr = globals->bx_glue_offset[reg] & ~(bfd_vma)3;
9093
9094 if ((globals->bx_glue_offset[reg] & 1) == 0)
9095 {
9096 p = s->contents + glue_addr;
9097 bfd_put_32 (globals->obfd, armbx1_tst_insn + (reg << 16), p);
9098 bfd_put_32 (globals->obfd, armbx2_moveq_insn + reg, p + 4);
9099 bfd_put_32 (globals->obfd, armbx3_bx_insn + reg, p + 8);
9100 globals->bx_glue_offset[reg] |= 1;
9101 }
9102
9103 return glue_addr + s->output_section->vma + s->output_offset;
9104}
9105
a4fd1a8e
PB		 9106/* Generate Arm stubs for exported Thumb symbols. */
9107static void
906e58ca 9108elf32_arm_begin_write_processing (bfd *abfd ATTRIBUTE_UNUSED,
a4fd1a8e
PB		 9109 struct bfd_link_info *link_info)
9110{
9111 struct elf32_arm_link_hash_table * globals;
9112
8029a119
NC		 9113 if (link_info == NULL)
9114 /* Ignore this if we are not called by the ELF backend linker. */
a4fd1a8e
PB		 9115 return;
9116
9117 globals = elf32_arm_hash_table (link_info);
4dfe6ac6
NC		 9118 if (globals == NULL)
9119 return;
9120
84c08195
PB		 9121 /* If blx is available then exported Thumb symbols are OK and there is
9122 nothing to do. */
a4fd1a8e
PB		 9123 if (globals->use_blx)
9124 return;
9125
9126 elf_link_hash_traverse (&globals->root, elf32_arm_to_thumb_export_stub,
9127 link_info);
9128}
9129
47beaa6a
RS		 9130/* Reserve space for COUNT dynamic relocations in relocation selection
9131 SRELOC. */
9132
9133static void
9134elf32_arm_allocate_dynrelocs (struct bfd_link_info *info, asection *sreloc,
9135 bfd_size_type count)
9136{
9137 struct elf32_arm_link_hash_table *htab;
9138
9139 htab = elf32_arm_hash_table (info);
9140 BFD_ASSERT (htab->root.dynamic_sections_created);
9141 if (sreloc == NULL)
9142 abort ();
9143 sreloc->size += RELOC_SIZE (htab) * count;
9144}
9145
34e77a92
RS		 9146/* Reserve space for COUNT R_ARM_IRELATIVE relocations. If the link is
9147 dynamic, the relocations should go in SRELOC, otherwise they should
9148 go in the special .rel.iplt section. */
9149
9150static void
9151elf32_arm_allocate_irelocs (struct bfd_link_info *info, asection *sreloc,
9152 bfd_size_type count)
9153{
9154 struct elf32_arm_link_hash_table *htab;
9155
9156 htab = elf32_arm_hash_table (info);
9157 if (!htab->root.dynamic_sections_created)
9158 htab->root.irelplt->size += RELOC_SIZE (htab) * count;
9159 else
9160 {
9161 BFD_ASSERT (sreloc != NULL);
9162 sreloc->size += RELOC_SIZE (htab) * count;
9163 }
9164}
9165
47beaa6a
RS		 9166/* Add relocation REL to the end of relocation section SRELOC. */
9167
9168static void
9169elf32_arm_add_dynreloc (bfd *output_bfd, struct bfd_link_info *info,
9170 asection *sreloc, Elf_Internal_Rela *rel)
9171{
9172 bfd_byte *loc;
9173 struct elf32_arm_link_hash_table *htab;
9174
9175 htab = elf32_arm_hash_table (info);
34e77a92
RS		 9176 if (!htab->root.dynamic_sections_created
9177 && ELF32_R_TYPE (rel->r_info) == R_ARM_IRELATIVE)
9178 sreloc = htab->root.irelplt;
47beaa6a
RS		 9179 if (sreloc == NULL)
9180 abort ();
9181 loc = sreloc->contents;
9182 loc += sreloc->reloc_count++ * RELOC_SIZE (htab);
9183 if (sreloc->reloc_count * RELOC_SIZE (htab) > sreloc->size)
9184 abort ();
9185 SWAP_RELOC_OUT (htab) (output_bfd, rel, loc);
9186}
9187
34e77a92
RS		 9188/* Allocate room for a PLT entry described by ROOT_PLT and ARM_PLT.
9189 IS_IPLT_ENTRY says whether the entry belongs to .iplt rather than
9190 to .plt. */
9191
9192static void
9193elf32_arm_allocate_plt_entry (struct bfd_link_info *info,
9194 bfd_boolean is_iplt_entry,
9195 union gotplt_union *root_plt,
9196 struct arm_plt_info *arm_plt)
9197{
9198 struct elf32_arm_link_hash_table *htab;
9199 asection *splt;
9200 asection *sgotplt;
9201
9202 htab = elf32_arm_hash_table (info);
9203
9204 if (is_iplt_entry)
9205 {
9206 splt = htab->root.iplt;
9207 sgotplt = htab->root.igotplt;
9208
99059e56
RM		 9209 /* NaCl uses a special first entry in .iplt too. */
9210 if (htab->nacl_p && splt->size == 0)
9211 splt->size += htab->plt_header_size;
9212
34e77a92
RS		 9213 /* Allocate room for an R_ARM_IRELATIVE relocation in .rel.iplt. */
9214 elf32_arm_allocate_irelocs (info, htab->root.irelplt, 1);
9215 }
9216 else
9217 {
9218 splt = htab->root.splt;
9219 sgotplt = htab->root.sgotplt;
9220
9221 /* Allocate room for an R_JUMP_SLOT relocation in .rel.plt. */
9222 elf32_arm_allocate_dynrelocs (info, htab->root.srelplt, 1);
9223
9224 /* If this is the first .plt entry, make room for the special
9225 first entry. */
9226 if (splt->size == 0)
9227 splt->size += htab->plt_header_size;
9f19ab6d
WN		 9228
9229 htab->next_tls_desc_index++;
34e77a92
RS		 9230 }
9231
9232 /* Allocate the PLT entry itself, including any leading Thumb stub. */
9233 if (elf32_arm_plt_needs_thumb_stub_p (info, arm_plt))
9234 splt->size += PLT_THUMB_STUB_SIZE;
9235 root_plt->offset = splt->size;
9236 splt->size += htab->plt_entry_size;
9237
9238 if (!htab->symbian_p)
9239 {
9240 /* We also need to make an entry in the .got.plt section, which
9241 will be placed in the .got section by the linker script. */
9f19ab6d
WN		 9242 if (is_iplt_entry)
9243 arm_plt->got_offset = sgotplt->size;
9244 else
9245 arm_plt->got_offset = sgotplt->size - 8 * htab->num_tls_desc;
34e77a92
RS		 9246 sgotplt->size += 4;
9247 }
9248}
9249
b38cadfb
NC		 9250static bfd_vma
9251arm_movw_immediate (bfd_vma value)
9252{
9253 return (value & 0x00000fff) | ((value & 0x0000f000) << 4);
9254}
9255
9256static bfd_vma
9257arm_movt_immediate (bfd_vma value)
9258{
9259 return ((value & 0x0fff0000) >> 16) | ((value & 0xf0000000) >> 12);
9260}
9261
34e77a92
RS		 9262/* Fill in a PLT entry and its associated GOT slot. If DYNINDX == -1,
9263 the entry lives in .iplt and resolves to (*SYM_VALUE)().
9264 Otherwise, DYNINDX is the index of the symbol in the dynamic
9265 symbol table and SYM_VALUE is undefined.
9266
9267 ROOT_PLT points to the offset of the PLT entry from the start of its
9268 section (.iplt or .plt). ARM_PLT points to the symbol's ARM-specific
57460bcf 9269 bookkeeping information.
34e77a92 9270
57460bcf
NC		 9271 Returns FALSE if there was a problem. */
9272
9273static bfd_boolean
34e77a92
RS		 9274elf32_arm_populate_plt_entry (bfd *output_bfd, struct bfd_link_info *info,
9275 union gotplt_union *root_plt,
9276 struct arm_plt_info *arm_plt,
9277 int dynindx, bfd_vma sym_value)
9278{
9279 struct elf32_arm_link_hash_table *htab;
9280 asection *sgot;
9281 asection *splt;
9282 asection *srel;
9283 bfd_byte *loc;
9284 bfd_vma plt_index;
9285 Elf_Internal_Rela rel;
9286 bfd_vma plt_header_size;
9287 bfd_vma got_header_size;
9288
9289 htab = elf32_arm_hash_table (info);
9290
9291 /* Pick the appropriate sections and sizes. */
9292 if (dynindx == -1)
9293 {
9294 splt = htab->root.iplt;
9295 sgot = htab->root.igotplt;
9296 srel = htab->root.irelplt;
9297
9298 /* There are no reserved entries in .igot.plt, and no special
9299 first entry in .iplt. */
9300 got_header_size = 0;
9301 plt_header_size = 0;
9302 }
9303 else
9304 {
9305 splt = htab->root.splt;
9306 sgot = htab->root.sgotplt;
9307 srel = htab->root.srelplt;
9308
9309 got_header_size = get_elf_backend_data (output_bfd)->got_header_size;
9310 plt_header_size = htab->plt_header_size;
9311 }
9312 BFD_ASSERT (splt != NULL && srel != NULL);
9313
9314 /* Fill in the entry in the procedure linkage table. */
9315 if (htab->symbian_p)
9316 {
9317 BFD_ASSERT (dynindx >= 0);
9318 put_arm_insn (htab, output_bfd,
9319 elf32_arm_symbian_plt_entry[0],
9320 splt->contents + root_plt->offset);
9321 bfd_put_32 (output_bfd,
9322 elf32_arm_symbian_plt_entry[1],
9323 splt->contents + root_plt->offset + 4);
9324
9325 /* Fill in the entry in the .rel.plt section. */
9326 rel.r_offset = (splt->output_section->vma
9327 + splt->output_offset
9328 + root_plt->offset + 4);
9329 rel.r_info = ELF32_R_INFO (dynindx, R_ARM_GLOB_DAT);
9330
9331 /* Get the index in the procedure linkage table which
9332 corresponds to this symbol. This is the index of this symbol
9333 in all the symbols for which we are making plt entries. The
9334 first entry in the procedure linkage table is reserved. */
9335 plt_index = ((root_plt->offset - plt_header_size)
9336 / htab->plt_entry_size);
9337 }
9338 else
9339 {
9340 bfd_vma got_offset, got_address, plt_address;
9341 bfd_vma got_displacement, initial_got_entry;
9342 bfd_byte * ptr;
9343
9344 BFD_ASSERT (sgot != NULL);
9345
9346 /* Get the offset into the .(i)got.plt table of the entry that
9347 corresponds to this function. */
9348 got_offset = (arm_plt->got_offset & -2);
9349
9350 /* Get the index in the procedure linkage table which
9351 corresponds to this symbol. This is the index of this symbol
9352 in all the symbols for which we are making plt entries.
9353 After the reserved .got.plt entries, all symbols appear in
9354 the same order as in .plt. */
9355 plt_index = (got_offset - got_header_size) / 4;
9356
9357 /* Calculate the address of the GOT entry. */
9358 got_address = (sgot->output_section->vma
9359 + sgot->output_offset
9360 + got_offset);
9361
9362 /* ...and the address of the PLT entry. */
9363 plt_address = (splt->output_section->vma
9364 + splt->output_offset
9365 + root_plt->offset);
9366
9367 ptr = splt->contents + root_plt->offset;
0e1862bb 9368 if (htab->vxworks_p && bfd_link_pic (info))
34e77a92
RS		 9369 {
9370 unsigned int i;
9371 bfd_vma val;
9372
9373 for (i = 0; i != htab->plt_entry_size / 4; i++, ptr += 4)
9374 {
9375 val = elf32_arm_vxworks_shared_plt_entry[i];
9376 if (i == 2)
9377 val |= got_address - sgot->output_section->vma;
9378 if (i == 5)
9379 val |= plt_index * RELOC_SIZE (htab);
9380 if (i == 2 || i == 5)
9381 bfd_put_32 (output_bfd, val, ptr);
9382 else
9383 put_arm_insn (htab, output_bfd, val, ptr);
9384 }
9385 }
9386 else if (htab->vxworks_p)
9387 {
9388 unsigned int i;
9389 bfd_vma val;
9390
9391 for (i = 0; i != htab->plt_entry_size / 4; i++, ptr += 4)
9392 {
9393 val = elf32_arm_vxworks_exec_plt_entry[i];
9394 if (i == 2)
9395 val |= got_address;
9396 if (i == 4)
9397 val |= 0xffffff & -((root_plt->offset + i * 4 + 8) >> 2);
9398 if (i == 5)
9399 val |= plt_index * RELOC_SIZE (htab);
9400 if (i == 2 || i == 5)
9401 bfd_put_32 (output_bfd, val, ptr);
9402 else
9403 put_arm_insn (htab, output_bfd, val, ptr);
9404 }
9405
9406 loc = (htab->srelplt2->contents
9407 + (plt_index * 2 + 1) * RELOC_SIZE (htab));
9408
9409 /* Create the .rela.plt.unloaded R_ARM_ABS32 relocation
9410 referencing the GOT for this PLT entry. */
9411 rel.r_offset = plt_address + 8;
9412 rel.r_info = ELF32_R_INFO (htab->root.hgot->indx, R_ARM_ABS32);
9413 rel.r_addend = got_offset;
9414 SWAP_RELOC_OUT (htab) (output_bfd, &rel, loc);
9415 loc += RELOC_SIZE (htab);
9416
9417 /* Create the R_ARM_ABS32 relocation referencing the
9418 beginning of the PLT for this GOT entry. */
9419 rel.r_offset = got_address;
9420 rel.r_info = ELF32_R_INFO (htab->root.hplt->indx, R_ARM_ABS32);
9421 rel.r_addend = 0;
9422 SWAP_RELOC_OUT (htab) (output_bfd, &rel, loc);
9423 }
b38cadfb
NC		 9424 else if (htab->nacl_p)
9425 {
9426 /* Calculate the displacement between the PLT slot and the
9427 common tail that's part of the special initial PLT slot. */
6034aab8 9428 int32_t tail_displacement
b38cadfb
NC		 9429 = ((splt->output_section->vma + splt->output_offset
9430 + ARM_NACL_PLT_TAIL_OFFSET)
9431 - (plt_address + htab->plt_entry_size + 4));
9432 BFD_ASSERT ((tail_displacement & 3) == 0);
9433 tail_displacement >>= 2;
9434
9435 BFD_ASSERT ((tail_displacement & 0xff000000) == 0
9436 || (-tail_displacement & 0xff000000) == 0);
9437
9438 /* Calculate the displacement between the PLT slot and the entry
9439 in the GOT. The offset accounts for the value produced by
9440 adding to pc in the penultimate instruction of the PLT stub. */
6034aab8 9441 got_displacement = (got_address
99059e56 9442 - (plt_address + htab->plt_entry_size));
b38cadfb
NC		 9443
9444 /* NaCl does not support interworking at all. */
9445 BFD_ASSERT (!elf32_arm_plt_needs_thumb_stub_p (info, arm_plt));
9446
9447 put_arm_insn (htab, output_bfd,
9448 elf32_arm_nacl_plt_entry[0]
9449 | arm_movw_immediate (got_displacement),
9450 ptr + 0);
9451 put_arm_insn (htab, output_bfd,
9452 elf32_arm_nacl_plt_entry[1]
9453 | arm_movt_immediate (got_displacement),
9454 ptr + 4);
9455 put_arm_insn (htab, output_bfd,
9456 elf32_arm_nacl_plt_entry[2],
9457 ptr + 8);
9458 put_arm_insn (htab, output_bfd,
9459 elf32_arm_nacl_plt_entry[3]
9460 | (tail_displacement & 0x00ffffff),
9461 ptr + 12);
9462 }
57460bcf
NC		 9463 else if (using_thumb_only (htab))
9464 {
eed94f8f 9465 /* PR ld/16017: Generate thumb only PLT entries. */
469a3493 9466 if (!using_thumb2 (htab))
eed94f8f
NC		 9467 {
9468 /* FIXME: We ought to be able to generate thumb-1 PLT
9469 instructions... */
9470 _bfd_error_handler (_("%B: Warning: thumb-1 mode PLT generation not currently supported"),
9471 output_bfd);
9472 return FALSE;
9473 }
57460bcf 9474
eed94f8f
NC		 9475 /* Calculate the displacement between the PLT slot and the entry in
9476 the GOT. The 12-byte offset accounts for the value produced by
9477 adding to pc in the 3rd instruction of the PLT stub. */
9478 got_displacement = got_address - (plt_address + 12);
9479
9480 /* As we are using 32 bit instructions we have to use 'put_arm_insn'
9481 instead of 'put_thumb_insn'. */
9482 put_arm_insn (htab, output_bfd,
9483 elf32_thumb2_plt_entry[0]
9484 | ((got_displacement & 0x000000ff) << 16)
9485 | ((got_displacement & 0x00000700) << 20)
9486 | ((got_displacement & 0x00000800) >> 1)
9487 | ((got_displacement & 0x0000f000) >> 12),
9488 ptr + 0);
9489 put_arm_insn (htab, output_bfd,
9490 elf32_thumb2_plt_entry[1]
9491 | ((got_displacement & 0x00ff0000) )
9492 | ((got_displacement & 0x07000000) << 4)
9493 | ((got_displacement & 0x08000000) >> 17)
9494 | ((got_displacement & 0xf0000000) >> 28),
9495 ptr + 4);
9496 put_arm_insn (htab, output_bfd,
9497 elf32_thumb2_plt_entry[2],
9498 ptr + 8);
9499 put_arm_insn (htab, output_bfd,
9500 elf32_thumb2_plt_entry[3],
9501 ptr + 12);
57460bcf 9502 }
34e77a92
RS		 9503 else
9504 {
9505 /* Calculate the displacement between the PLT slot and the
9506 entry in the GOT. The eight-byte offset accounts for the
9507 value produced by adding to pc in the first instruction
9508 of the PLT stub. */
9509 got_displacement = got_address - (plt_address + 8);
9510
34e77a92
RS		 9511 if (elf32_arm_plt_needs_thumb_stub_p (info, arm_plt))
9512 {
9513 put_thumb_insn (htab, output_bfd,
9514 elf32_arm_plt_thumb_stub[0], ptr - 4);
9515 put_thumb_insn (htab, output_bfd,
9516 elf32_arm_plt_thumb_stub[1], ptr - 2);
9517 }
9518
1db37fe6
YG		 9519 if (!elf32_arm_use_long_plt_entry)
9520 {
9521 BFD_ASSERT ((got_displacement & 0xf0000000) == 0);
9522
9523 put_arm_insn (htab, output_bfd,
9524 elf32_arm_plt_entry_short[0]
9525 | ((got_displacement & 0x0ff00000) >> 20),
9526 ptr + 0);
9527 put_arm_insn (htab, output_bfd,
9528 elf32_arm_plt_entry_short[1]
9529 | ((got_displacement & 0x000ff000) >> 12),
9530 ptr+ 4);
9531 put_arm_insn (htab, output_bfd,
9532 elf32_arm_plt_entry_short[2]
9533 | (got_displacement & 0x00000fff),
9534 ptr + 8);
34e77a92 9535#ifdef FOUR_WORD_PLT
1db37fe6 9536 bfd_put_32 (output_bfd, elf32_arm_plt_entry_short[3], ptr + 12);
34e77a92 9537#endif
1db37fe6
YG		 9538 }
9539 else
9540 {
9541 put_arm_insn (htab, output_bfd,
9542 elf32_arm_plt_entry_long[0]
9543 | ((got_displacement & 0xf0000000) >> 28),
9544 ptr + 0);
9545 put_arm_insn (htab, output_bfd,
9546 elf32_arm_plt_entry_long[1]
9547 | ((got_displacement & 0x0ff00000) >> 20),
9548 ptr + 4);
9549 put_arm_insn (htab, output_bfd,
9550 elf32_arm_plt_entry_long[2]
9551 | ((got_displacement & 0x000ff000) >> 12),
9552 ptr+ 8);
9553 put_arm_insn (htab, output_bfd,
9554 elf32_arm_plt_entry_long[3]
9555 | (got_displacement & 0x00000fff),
9556 ptr + 12);
9557 }
34e77a92
RS		 9558 }
9559
9560 /* Fill in the entry in the .rel(a).(i)plt section. */
9561 rel.r_offset = got_address;
9562 rel.r_addend = 0;
9563 if (dynindx == -1)
9564 {
9565 /* .igot.plt entries use IRELATIVE relocations against SYM_VALUE.
9566 The dynamic linker or static executable then calls SYM_VALUE
9567 to determine the correct run-time value of the .igot.plt entry. */
9568 rel.r_info = ELF32_R_INFO (0, R_ARM_IRELATIVE);
9569 initial_got_entry = sym_value;
9570 }
9571 else
9572 {
9573 rel.r_info = ELF32_R_INFO (dynindx, R_ARM_JUMP_SLOT);
9574 initial_got_entry = (splt->output_section->vma
9575 + splt->output_offset);
9576 }
9577
9578 /* Fill in the entry in the global offset table. */
9579 bfd_put_32 (output_bfd, initial_got_entry,
9580 sgot->contents + got_offset);
9581 }
9582
aba8c3de
WN		 9583 if (dynindx == -1)
9584 elf32_arm_add_dynreloc (output_bfd, info, srel, &rel);
9585 else
9586 {
9587 loc = srel->contents + plt_index * RELOC_SIZE (htab);
9588 SWAP_RELOC_OUT (htab) (output_bfd, &rel, loc);
9589 }
57460bcf
NC		 9590
9591 return TRUE;
34e77a92
RS		 9592}
9593
eb043451
PB		 9594/* Some relocations map to different relocations depending on the
9595 target. Return the real relocation. */
8029a119 9596
eb043451
PB		 9597static int
9598arm_real_reloc_type (struct elf32_arm_link_hash_table * globals,
9599 int r_type)
9600{
9601 switch (r_type)
9602 {
9603 case R_ARM_TARGET1:
9604 if (globals->target1_is_rel)
9605 return R_ARM_REL32;
9606 else
9607 return R_ARM_ABS32;
9608
9609 case R_ARM_TARGET2:
9610 return globals->target2_reloc;
9611
9612 default:
9613 return r_type;
9614 }
9615}
eb043451 9616
ba93b8ac
DJ		 9617/* Return the base VMA address which should be subtracted from real addresses
9618 when resolving @dtpoff relocation.
9619 This is PT_TLS segment p_vaddr. */
9620
9621static bfd_vma
9622dtpoff_base (struct bfd_link_info *info)
9623{
9624 /* If tls_sec is NULL, we should have signalled an error already. */
9625 if (elf_hash_table (info)->tls_sec == NULL)
9626 return 0;
9627 return elf_hash_table (info)->tls_sec->vma;
9628}
9629
9630/* Return the relocation value for @tpoff relocation
9631 if STT_TLS virtual address is ADDRESS. */
9632
9633static bfd_vma
9634tpoff (struct bfd_link_info *info, bfd_vma address)
9635{
9636 struct elf_link_hash_table *htab = elf_hash_table (info);
9637 bfd_vma base;
9638
9639 /* If tls_sec is NULL, we should have signalled an error already. */
9640 if (htab->tls_sec == NULL)
9641 return 0;
9642 base = align_power ((bfd_vma) TCB_SIZE, htab->tls_sec->alignment_power);
9643 return address - htab->tls_sec->vma + base;
9644}
9645
00a97672
RS		 9646/* Perform an R_ARM_ABS12 relocation on the field pointed to by DATA.
9647 VALUE is the relocation value. */
9648
9649static bfd_reloc_status_type
9650elf32_arm_abs12_reloc (bfd *abfd, void *data, bfd_vma value)
9651{
9652 if (value > 0xfff)
9653 return bfd_reloc_overflow;
9654
9655 value |= bfd_get_32 (abfd, data) & 0xfffff000;
9656 bfd_put_32 (abfd, value, data);
9657 return bfd_reloc_ok;
9658}
9659
0855e32b
NS		 9660/* Handle TLS relaxations. Relaxing is possible for symbols that use
9661 R_ARM_GOTDESC, R_ARM_{,THM_}TLS_CALL or
9662 R_ARM_{,THM_}TLS_DESCSEQ relocations, during a static link.
9663
9664 Return bfd_reloc_ok if we're done, bfd_reloc_continue if the caller
9665 is to then call final_link_relocate. Return other values in the
62672b10
NS		 9666 case of error.
9667
9668 FIXME:When --emit-relocs is in effect, we'll emit relocs describing
9669 the pre-relaxed code. It would be nice if the relocs were updated
9670 to match the optimization. */
0855e32b 9671
b38cadfb 9672static bfd_reloc_status_type
0855e32b 9673elf32_arm_tls_relax (struct elf32_arm_link_hash_table *globals,
b38cadfb 9674 bfd *input_bfd, asection *input_sec, bfd_byte *contents,
0855e32b
NS		 9675 Elf_Internal_Rela *rel, unsigned long is_local)
9676{
9677 unsigned long insn;
b38cadfb 9678
0855e32b
NS		 9679 switch (ELF32_R_TYPE (rel->r_info))
9680 {
9681 default:
9682 return bfd_reloc_notsupported;
b38cadfb 9683
0855e32b
NS		 9684 case R_ARM_TLS_GOTDESC:
9685 if (is_local)
9686 insn = 0;
9687 else
9688 {
9689 insn = bfd_get_32 (input_bfd, contents + rel->r_offset);
9690 if (insn & 1)
9691 insn -= 5; /* THUMB */
9692 else
9693 insn -= 8; /* ARM */
9694 }
9695 bfd_put_32 (input_bfd, insn, contents + rel->r_offset);
9696 return bfd_reloc_continue;
9697
9698 case R_ARM_THM_TLS_DESCSEQ:
9699 /* Thumb insn. */
9700 insn = bfd_get_16 (input_bfd, contents + rel->r_offset);
9701 if ((insn & 0xff78) == 0x4478) /* add rx, pc */
9702 {
9703 if (is_local)
9704 /* nop */
9705 bfd_put_16 (input_bfd, 0x46c0, contents + rel->r_offset);
9706 }
9707 else if ((insn & 0xffc0) == 0x6840) /* ldr rx,[ry,#4] */
9708 {
9709 if (is_local)
9710 /* nop */
9711 bfd_put_16 (input_bfd, 0x46c0, contents + rel->r_offset);
9712 else
9713 /* ldr rx,[ry] */
9714 bfd_put_16 (input_bfd, insn & 0xf83f, contents + rel->r_offset);
9715 }
9716 else if ((insn & 0xff87) == 0x4780) /* blx rx */
9717 {
9718 if (is_local)
9719 /* nop */
9720 bfd_put_16 (input_bfd, 0x46c0, contents + rel->r_offset);
9721 else
9722 /* mov r0, rx */
9723 bfd_put_16 (input_bfd, 0x4600 | (insn & 0x78),
9724 contents + rel->r_offset);
9725 }
9726 else
9727 {
9728 if ((insn & 0xf000) == 0xf000 || (insn & 0xf800) == 0xe800)
9729 /* It's a 32 bit instruction, fetch the rest of it for
9730 error generation. */
9731 insn = (insn << 16)
9732 | bfd_get_16 (input_bfd, contents + rel->r_offset + 2);
4eca0228 9733 _bfd_error_handler
695344c0
NC		 9734 /* xgettext:c-format */
9735 (_("%B(%A+0x%lx): unexpected Thumb instruction '0x%x' in TLS trampoline"),
0855e32b
NS		 9736 input_bfd, input_sec, (unsigned long)rel->r_offset, insn);
9737 return bfd_reloc_notsupported;
9738 }
9739 break;
b38cadfb 9740
0855e32b
NS		 9741 case R_ARM_TLS_DESCSEQ:
9742 /* arm insn. */
9743 insn = bfd_get_32 (input_bfd, contents + rel->r_offset);
9744 if ((insn & 0xffff0ff0) == 0xe08f0000) /* add rx,pc,ry */
9745 {
9746 if (is_local)
9747 /* mov rx, ry */
9748 bfd_put_32 (input_bfd, 0xe1a00000 | (insn & 0xffff),
9749 contents + rel->r_offset);
9750 }
9751 else if ((insn & 0xfff00fff) == 0xe5900004) /* ldr rx,[ry,#4]*/
9752 {
9753 if (is_local)
9754 /* nop */
9755 bfd_put_32 (input_bfd, 0xe1a00000, contents + rel->r_offset);
9756 else
9757 /* ldr rx,[ry] */
9758 bfd_put_32 (input_bfd, insn & 0xfffff000,
9759 contents + rel->r_offset);
9760 }
9761 else if ((insn & 0xfffffff0) == 0xe12fff30) /* blx rx */
9762 {
9763 if (is_local)
9764 /* nop */
9765 bfd_put_32 (input_bfd, 0xe1a00000, contents + rel->r_offset);
9766 else
9767 /* mov r0, rx */
9768 bfd_put_32 (input_bfd, 0xe1a00000 | (insn & 0xf),
9769 contents + rel->r_offset);
9770 }
9771 else
9772 {
4eca0228 9773 _bfd_error_handler
695344c0
NC		 9774 /* xgettext:c-format */
9775 (_("%B(%A+0x%lx): unexpected ARM instruction '0x%x' in TLS trampoline"),
0855e32b
NS		 9776 input_bfd, input_sec, (unsigned long)rel->r_offset, insn);
9777 return bfd_reloc_notsupported;
9778 }
9779 break;
9780
9781 case R_ARM_TLS_CALL:
9782 /* GD->IE relaxation, turn the instruction into 'nop' or
9783 'ldr r0, [pc,r0]' */
9784 insn = is_local ? 0xe1a00000 : 0xe79f0000;
9785 bfd_put_32 (input_bfd, insn, contents + rel->r_offset);
9786 break;
b38cadfb 9787
0855e32b 9788 case R_ARM_THM_TLS_CALL:
6a631e86 9789 /* GD->IE relaxation. */
0855e32b
NS		 9790 if (!is_local)
9791 /* add r0,pc; ldr r0, [r0] */
9792 insn = 0x44786800;
60a019a0 9793 else if (using_thumb2 (globals))
0855e32b
NS		 9794 /* nop.w */
9795 insn = 0xf3af8000;
9796 else
9797 /* nop; nop */
9798 insn = 0xbf00bf00;
b38cadfb 9799
0855e32b
NS		 9800 bfd_put_16 (input_bfd, insn >> 16, contents + rel->r_offset);
9801 bfd_put_16 (input_bfd, insn & 0xffff, contents + rel->r_offset + 2);
9802 break;
9803 }
9804 return bfd_reloc_ok;
9805}
9806
4962c51a
MS		 9807/* For a given value of n, calculate the value of G_n as required to
9808 deal with group relocations. We return it in the form of an
9809 encoded constant-and-rotation, together with the final residual. If n is
9810 specified as less than zero, then final_residual is filled with the
9811 input value and no further action is performed. */
9812
9813static bfd_vma
9814calculate_group_reloc_mask (bfd_vma value, int n, bfd_vma *final_residual)
9815{
9816 int current_n;
9817 bfd_vma g_n;
9818 bfd_vma encoded_g_n = 0;
9819 bfd_vma residual = value; /* Also known as Y_n. */
9820
9821 for (current_n = 0; current_n <= n; current_n++)
9822 {
9823 int shift;
9824
9825 /* Calculate which part of the value to mask. */
9826 if (residual == 0)
99059e56 9827 shift = 0;
4962c51a 9828 else
99059e56
RM		 9829 {
9830 int msb;
9831
9832 /* Determine the most significant bit in the residual and
9833 align the resulting value to a 2-bit boundary. */
9834 for (msb = 30; msb >= 0; msb -= 2)
9835 if (residual & (3 << msb))
9836 break;
9837
9838 /* The desired shift is now (msb - 6), or zero, whichever
9839 is the greater. */
9840 shift = msb - 6;
9841 if (shift < 0)
9842 shift = 0;
9843 }
4962c51a
MS		 9844
9845 /* Calculate g_n in 32-bit as well as encoded constant+rotation form. */
9846 g_n = residual & (0xff << shift);
9847 encoded_g_n = (g_n >> shift)
99059e56 9848 | ((g_n <= 0xff ? 0 : (32 - shift) / 2) << 8);
4962c51a
MS		 9849
9850 /* Calculate the residual for the next time around. */
9851 residual &= ~g_n;
9852 }
9853
9854 *final_residual = residual;
9855
9856 return encoded_g_n;
9857}
9858
9859/* Given an ARM instruction, determine whether it is an ADD or a SUB.
9860 Returns 1 if it is an ADD, -1 if it is a SUB, and 0 otherwise. */
906e58ca 9861
4962c51a 9862static int
906e58ca 9863identify_add_or_sub (bfd_vma insn)
4962c51a
MS		 9864{
9865 int opcode = insn & 0x1e00000;
9866
9867 if (opcode == 1 << 23) /* ADD */
9868 return 1;
9869
9870 if (opcode == 1 << 22) /* SUB */
9871 return -1;
9872
9873 return 0;
9874}
9875
252b5132 9876/* Perform a relocation as part of a final link. */
9b485d32 9877
252b5132 9878static bfd_reloc_status_type
57e8b36a
NC		 9879elf32_arm_final_link_relocate (reloc_howto_type * howto,
9880 bfd * input_bfd,
9881 bfd * output_bfd,
9882 asection * input_section,
9883 bfd_byte * contents,
9884 Elf_Internal_Rela * rel,
9885 bfd_vma value,
9886 struct bfd_link_info * info,
9887 asection * sym_sec,
9888 const char * sym_name,
34e77a92
RS		 9889 unsigned char st_type,
9890 enum arm_st_branch_type branch_type,
0945cdfd 9891 struct elf_link_hash_entry * h,
f2a9dd69 9892 bfd_boolean * unresolved_reloc_p,
8029a119 9893 char ** error_message)
252b5132
RH		 9894{
9895 unsigned long r_type = howto->type;
9896 unsigned long r_symndx;
9897 bfd_byte * hit_data = contents + rel->r_offset;
252b5132 9898 bfd_vma * local_got_offsets;
0855e32b 9899 bfd_vma * local_tlsdesc_gotents;
34e77a92
RS		 9900 asection * sgot;
9901 asection * splt;
252b5132 9902 asection * sreloc = NULL;
362d30a1 9903 asection * srelgot;
252b5132 9904 bfd_vma addend;
ba96a88f 9905 bfd_signed_vma signed_addend;
34e77a92
RS		 9906 unsigned char dynreloc_st_type;
9907 bfd_vma dynreloc_value;
ba96a88f 9908 struct elf32_arm_link_hash_table * globals;
34e77a92
RS		 9909 struct elf32_arm_link_hash_entry *eh;
9910 union gotplt_union *root_plt;
9911 struct arm_plt_info *arm_plt;
9912 bfd_vma plt_offset;
9913 bfd_vma gotplt_offset;
9914 bfd_boolean has_iplt_entry;
f21f3fe0 9915
9c504268 9916 globals = elf32_arm_hash_table (info);
4dfe6ac6
NC		 9917 if (globals == NULL)
9918 return bfd_reloc_notsupported;
9c504268 9919
0ffa91dd
NC		 9920 BFD_ASSERT (is_arm_elf (input_bfd));
9921
9922 /* Some relocation types map to different relocations depending on the
9c504268 9923 target. We pick the right one here. */
eb043451 9924 r_type = arm_real_reloc_type (globals, r_type);
0855e32b
NS		 9925
9926 /* It is possible to have linker relaxations on some TLS access
9927 models. Update our information here. */
9928 r_type = elf32_arm_tls_transition (info, r_type, h);
9929
eb043451
PB		 9930 if (r_type != howto->type)
9931 howto = elf32_arm_howto_from_type (r_type);
9c504268 9932
34e77a92 9933 eh = (struct elf32_arm_link_hash_entry *) h;
362d30a1 9934 sgot = globals->root.sgot;
252b5132 9935 local_got_offsets = elf_local_got_offsets (input_bfd);
0855e32b
NS		 9936 local_tlsdesc_gotents = elf32_arm_local_tlsdesc_gotent (input_bfd);
9937
34e77a92
RS		 9938 if (globals->root.dynamic_sections_created)
9939 srelgot = globals->root.srelgot;
9940 else
9941 srelgot = NULL;
9942
252b5132
RH		 9943 r_symndx = ELF32_R_SYM (rel->r_info);
9944
4e7fd91e 9945 if (globals->use_rel)
ba96a88f 9946 {
4e7fd91e
PB		 9947 addend = bfd_get_32 (input_bfd, hit_data) & howto->src_mask;
9948
9949 if (addend & ((howto->src_mask + 1) >> 1))
9950 {
9951 signed_addend = -1;
9952 signed_addend &= ~ howto->src_mask;
9953 signed_addend |= addend;
9954 }
9955 else
9956 signed_addend = addend;
ba96a88f
NC		 9957 }
9958 else
4e7fd91e 9959 addend = signed_addend = rel->r_addend;
f21f3fe0 9960
39f21624
NC		 9961 /* ST_BRANCH_TO_ARM is nonsense to thumb-only targets when we
9962 are resolving a function call relocation. */
9963 if (using_thumb_only (globals)
9964 && (r_type == R_ARM_THM_CALL
9965 || r_type == R_ARM_THM_JUMP24)
9966 && branch_type == ST_BRANCH_TO_ARM)
9967 branch_type = ST_BRANCH_TO_THUMB;
9968
34e77a92
RS		 9969 /* Record the symbol information that should be used in dynamic
9970 relocations. */
9971 dynreloc_st_type = st_type;
9972 dynreloc_value = value;
9973 if (branch_type == ST_BRANCH_TO_THUMB)
9974 dynreloc_value |= 1;
9975
9976 /* Find out whether the symbol has a PLT. Set ST_VALUE, BRANCH_TYPE and
9977 VALUE appropriately for relocations that we resolve at link time. */
9978 has_iplt_entry = FALSE;
4ba2ef8f
TP		 9979 if (elf32_arm_get_plt_info (input_bfd, globals, eh, r_symndx, &root_plt,
9980 &arm_plt)
34e77a92
RS		 9981 && root_plt->offset != (bfd_vma) -1)
9982 {
9983 plt_offset = root_plt->offset;
9984 gotplt_offset = arm_plt->got_offset;
9985
9986 if (h == NULL || eh->is_iplt)
9987 {
9988 has_iplt_entry = TRUE;
9989 splt = globals->root.iplt;
9990
9991 /* Populate .iplt entries here, because not all of them will
9992 be seen by finish_dynamic_symbol. The lower bit is set if
9993 we have already populated the entry. */
9994 if (plt_offset & 1)
9995 plt_offset--;
9996 else
9997 {
57460bcf
NC		 9998 if (elf32_arm_populate_plt_entry (output_bfd, info, root_plt, arm_plt,
9999 -1, dynreloc_value))
10000 root_plt->offset |= 1;
10001 else
10002 return bfd_reloc_notsupported;
34e77a92
RS		 10003 }
10004
10005 /* Static relocations always resolve to the .iplt entry. */
10006 st_type = STT_FUNC;
10007 value = (splt->output_section->vma
10008 + splt->output_offset
10009 + plt_offset);
10010 branch_type = ST_BRANCH_TO_ARM;
10011
10012 /* If there are non-call relocations that resolve to the .iplt
10013 entry, then all dynamic ones must too. */
10014 if (arm_plt->noncall_refcount != 0)
10015 {
10016 dynreloc_st_type = st_type;
10017 dynreloc_value = value;
10018 }
10019 }
10020 else
10021 /* We populate the .plt entry in finish_dynamic_symbol. */
10022 splt = globals->root.splt;
10023 }
10024 else
10025 {
10026 splt = NULL;
10027 plt_offset = (bfd_vma) -1;
10028 gotplt_offset = (bfd_vma) -1;
10029 }
10030
252b5132
RH		 10031 switch (r_type)
10032 {
10033 case R_ARM_NONE:
28a094c2
DJ		 10034 /* We don't need to find a value for this symbol. It's just a
10035 marker. */
10036 *unresolved_reloc_p = FALSE;
252b5132
RH		 10037 return bfd_reloc_ok;
10038
00a97672
RS		 10039 case R_ARM_ABS12:
10040 if (!globals->vxworks_p)
10041 return elf32_arm_abs12_reloc (input_bfd, hit_data, value + addend);
1a0670f3 10042 /* Fall through. */
00a97672 10043
252b5132
RH		 10044 case R_ARM_PC24:
10045 case R_ARM_ABS32:
bb224fc3 10046 case R_ARM_ABS32_NOI:
252b5132 10047 case R_ARM_REL32:
bb224fc3 10048 case R_ARM_REL32_NOI:
5b5bb741
PB		 10049 case R_ARM_CALL:
10050 case R_ARM_JUMP24:
dfc5f959 10051 case R_ARM_XPC25:
eb043451 10052 case R_ARM_PREL31:
7359ea65 10053 case R_ARM_PLT32:
7359ea65
DJ		 10054 /* Handle relocations which should use the PLT entry. ABS32/REL32
10055 will use the symbol's value, which may point to a PLT entry, but we
10056 don't need to handle that here. If we created a PLT entry, all
5fa9e92f
CL		 10057 branches in this object should go to it, except if the PLT is too
10058 far away, in which case a long branch stub should be inserted. */
bb224fc3 10059 if ((r_type != R_ARM_ABS32 && r_type != R_ARM_REL32
99059e56 10060 && r_type != R_ARM_ABS32_NOI && r_type != R_ARM_REL32_NOI
155d87d7
CL		 10061 && r_type != R_ARM_CALL
10062 && r_type != R_ARM_JUMP24
10063 && r_type != R_ARM_PLT32)
34e77a92 10064 && plt_offset != (bfd_vma) -1)
7359ea65 10065 {
34e77a92
RS		 10066 /* If we've created a .plt section, and assigned a PLT entry
10067 to this function, it must either be a STT_GNU_IFUNC reference
10068 or not be known to bind locally. In other cases, we should
10069 have cleared the PLT entry by now. */
10070 BFD_ASSERT (has_iplt_entry || !SYMBOL_CALLS_LOCAL (info, h));
7359ea65
DJ		 10071
10072 value = (splt->output_section->vma
10073 + splt->output_offset
34e77a92 10074 + plt_offset);
0945cdfd 10075 *unresolved_reloc_p = FALSE;
7359ea65
DJ		 10076 return _bfd_final_link_relocate (howto, input_bfd, input_section,
10077 contents, rel->r_offset, value,
00a97672 10078 rel->r_addend);
7359ea65
DJ		 10079 }
10080
67687978
PB		 10081 /* When generating a shared object or relocatable executable, these
10082 relocations are copied into the output file to be resolved at
10083 run time. */
0e1862bb
L		 10084 if ((bfd_link_pic (info)
10085 || globals->root.is_relocatable_executable)
7359ea65 10086 && (input_section->flags & SEC_ALLOC)
4dfe6ac6 10087 && !(globals->vxworks_p
3348747a
NS		 10088 && strcmp (input_section->output_section->name,
10089 ".tls_vars") == 0)
bb224fc3 10090 && ((r_type != R_ARM_REL32 && r_type != R_ARM_REL32_NOI)
ee06dc07 10091 || !SYMBOL_CALLS_LOCAL (info, h))
ca6b5f82
AM		 10092 && !(input_bfd == globals->stub_bfd
10093 && strstr (input_section->name, STUB_SUFFIX))
7359ea65
DJ		 10094 && (h == NULL
10095 || ELF_ST_VISIBILITY (h->other) == STV_DEFAULT
10096 || h->root.type != bfd_link_hash_undefweak)
10097 && r_type != R_ARM_PC24
5b5bb741
PB		 10098 && r_type != R_ARM_CALL
10099 && r_type != R_ARM_JUMP24
ee06dc07 10100 && r_type != R_ARM_PREL31
7359ea65 10101 && r_type != R_ARM_PLT32)
252b5132 10102 {
947216bf 10103 Elf_Internal_Rela outrel;
b34976b6 10104 bfd_boolean skip, relocate;
f21f3fe0 10105
52db4ec2
JW		 10106 if ((r_type == R_ARM_REL32 || r_type == R_ARM_REL32_NOI)
10107 && !h->def_regular)
10108 {
10109 char *v = _("shared object");
10110
0e1862bb 10111 if (bfd_link_executable (info))
52db4ec2
JW		 10112 v = _("PIE executable");
10113
4eca0228 10114 _bfd_error_handler
52db4ec2
JW		 10115 (_("%B: relocation %s against external or undefined symbol `%s'"
10116 " can not be used when making a %s; recompile with -fPIC"), input_bfd,
10117 elf32_arm_howto_table_1[r_type].name, h->root.root.string, v);
10118 return bfd_reloc_notsupported;
10119 }
10120
0945cdfd
DJ		 10121 *unresolved_reloc_p = FALSE;
10122
34e77a92 10123 if (sreloc == NULL && globals->root.dynamic_sections_created)
252b5132 10124 {
83bac4b0
NC		 10125 sreloc = _bfd_elf_get_dynamic_reloc_section (input_bfd, input_section,
10126 ! globals->use_rel);
f21f3fe0 10127
83bac4b0 10128 if (sreloc == NULL)
252b5132 10129 return bfd_reloc_notsupported;
252b5132 10130 }
f21f3fe0 10131
b34976b6
AM		 10132 skip = FALSE;
10133 relocate = FALSE;
f21f3fe0 10134
00a97672 10135 outrel.r_addend = addend;
c629eae0
JJ		 10136 outrel.r_offset =
10137 _bfd_elf_section_offset (output_bfd, info, input_section,
10138 rel->r_offset);
10139 if (outrel.r_offset == (bfd_vma) -1)
b34976b6 10140 skip = TRUE;
0bb2d96a 10141 else if (outrel.r_offset == (bfd_vma) -2)
b34976b6 10142 skip = TRUE, relocate = TRUE;
252b5132
RH		 10143 outrel.r_offset += (input_section->output_section->vma
10144 + input_section->output_offset);
f21f3fe0 10145
252b5132 10146 if (skip)
0bb2d96a 10147 memset (&outrel, 0, sizeof outrel);
5e681ec4
PB		 10148 else if (h != NULL
10149 && h->dynindx != -1
0e1862bb 10150 && (!bfd_link_pic (info)
1dcb9720
JW		 10151 || !(bfd_link_pie (info)
10152 || SYMBOLIC_BIND (info, h))
f5385ebf 10153 || !h->def_regular))
5e681ec4 10154 outrel.r_info = ELF32_R_INFO (h->dynindx, r_type);
252b5132
RH		 10155 else
10156 {
a16385dc
MM		 10157 int symbol;
10158
5e681ec4 10159 /* This symbol is local, or marked to become local. */
34e77a92 10160 BFD_ASSERT (r_type == R_ARM_ABS32 || r_type == R_ARM_ABS32_NOI);
a16385dc 10161 if (globals->symbian_p)
6366ff1e 10162 {
74541ad4
AM		 10163 asection *osec;
10164
6366ff1e
MM		 10165 /* On Symbian OS, the data segment and text segement
10166 can be relocated independently. Therefore, we
10167 must indicate the segment to which this
10168 relocation is relative. The BPABI allows us to
10169 use any symbol in the right segment; we just use
10170 the section symbol as it is convenient. (We
10171 cannot use the symbol given by "h" directly as it
74541ad4
AM		 10172 will not appear in the dynamic symbol table.)
10173
10174 Note that the dynamic linker ignores the section
10175 symbol value, so we don't subtract osec->vma
10176 from the emitted reloc addend. */
10dbd1f3 10177 if (sym_sec)
74541ad4 10178 osec = sym_sec->output_section;
10dbd1f3 10179 else
74541ad4
AM		 10180 osec = input_section->output_section;
10181 symbol = elf_section_data (osec)->dynindx;
10182 if (symbol == 0)
10183 {
10184 struct elf_link_hash_table *htab = elf_hash_table (info);
10185
10186 if ((osec->flags & SEC_READONLY) == 0
10187 && htab->data_index_section != NULL)
10188 osec = htab->data_index_section;
10189 else
10190 osec = htab->text_index_section;
10191 symbol = elf_section_data (osec)->dynindx;
10192 }
6366ff1e
MM		 10193 BFD_ASSERT (symbol != 0);
10194 }
a16385dc
MM		 10195 else
10196 /* On SVR4-ish systems, the dynamic loader cannot
10197 relocate the text and data segments independently,
10198 so the symbol does not matter. */
10199 symbol = 0;
34e77a92
RS		 10200 if (dynreloc_st_type == STT_GNU_IFUNC)
10201 /* We have an STT_GNU_IFUNC symbol that doesn't resolve
10202 to the .iplt entry. Instead, every non-call reference
10203 must use an R_ARM_IRELATIVE relocation to obtain the
10204 correct run-time address. */
10205 outrel.r_info = ELF32_R_INFO (symbol, R_ARM_IRELATIVE);
10206 else
10207 outrel.r_info = ELF32_R_INFO (symbol, R_ARM_RELATIVE);
00a97672
RS		 10208 if (globals->use_rel)
10209 relocate = TRUE;
10210 else
34e77a92 10211 outrel.r_addend += dynreloc_value;
252b5132 10212 }
f21f3fe0 10213
47beaa6a 10214 elf32_arm_add_dynreloc (output_bfd, info, sreloc, &outrel);
9a5aca8c 10215
f21f3fe0 10216 /* If this reloc is against an external symbol, we do not want to
252b5132 10217 fiddle with the addend. Otherwise, we need to include the symbol
9b485d32 10218 value so that it becomes an addend for the dynamic reloc. */
252b5132
RH		 10219 if (! relocate)
10220 return bfd_reloc_ok;
9a5aca8c 10221
f21f3fe0 10222 return _bfd_final_link_relocate (howto, input_bfd, input_section,
34e77a92
RS		 10223 contents, rel->r_offset,
10224 dynreloc_value, (bfd_vma) 0);
252b5132
RH		 10225 }
10226 else switch (r_type)
10227 {
00a97672
RS		 10228 case R_ARM_ABS12:
10229 return elf32_arm_abs12_reloc (input_bfd, hit_data, value + addend);
10230
dfc5f959 10231 case R_ARM_XPC25: /* Arm BLX instruction. */
5b5bb741
PB		 10232 case R_ARM_CALL:
10233 case R_ARM_JUMP24:
8029a119 10234 case R_ARM_PC24: /* Arm B/BL instruction. */
7359ea65 10235 case R_ARM_PLT32:
906e58ca 10236 {
906e58ca
NC		 10237 struct elf32_arm_stub_hash_entry *stub_entry = NULL;
10238
dfc5f959 10239 if (r_type == R_ARM_XPC25)
252b5132 10240 {
dfc5f959
NC		 10241 /* Check for Arm calling Arm function. */
10242 /* FIXME: Should we translate the instruction into a BL
10243 instruction instead ? */
35fc36a8 10244 if (branch_type != ST_BRANCH_TO_THUMB)
4eca0228 10245 _bfd_error_handler
d003868e
AM		 10246 (_("\%B: Warning: Arm BLX instruction targets Arm function '%s'."),
10247 input_bfd,
10248 h ? h->root.root.string : "(local)");
dfc5f959 10249 }
155d87d7 10250 else if (r_type == R_ARM_PC24)
dfc5f959
NC		 10251 {
10252 /* Check for Arm calling Thumb function. */
35fc36a8 10253 if (branch_type == ST_BRANCH_TO_THUMB)
dfc5f959 10254 {
f2a9dd69
DJ		 10255 if (elf32_arm_to_thumb_stub (info, sym_name, input_bfd,
10256 output_bfd, input_section,
10257 hit_data, sym_sec, rel->r_offset,
10258 signed_addend, value,
10259 error_message))
10260 return bfd_reloc_ok;
10261 else
10262 return bfd_reloc_dangerous;
dfc5f959 10263 }
252b5132 10264 }
ba96a88f 10265
906e58ca 10266 /* Check if a stub has to be inserted because the
8029a119 10267 destination is too far or we are changing mode. */
155d87d7
CL		 10268 if ( r_type == R_ARM_CALL
10269 || r_type == R_ARM_JUMP24
10270 || r_type == R_ARM_PLT32)
906e58ca 10271 {
fe33d2fa
CL		 10272 enum elf32_arm_stub_type stub_type = arm_stub_none;
10273 struct elf32_arm_link_hash_entry *hash;
10274
10275 hash = (struct elf32_arm_link_hash_entry *) h;
10276 stub_type = arm_type_of_stub (info, input_section, rel,
34e77a92
RS		 10277 st_type, &branch_type,
10278 hash, value, sym_sec,
fe33d2fa 10279 input_bfd, sym_name);
5fa9e92f 10280
fe33d2fa 10281 if (stub_type != arm_stub_none)
906e58ca
NC		 10282 {
10283 /* The target is out of reach, so redirect the
10284 branch to the local stub for this function. */
906e58ca
NC		 10285 stub_entry = elf32_arm_get_stub_entry (input_section,
10286 sym_sec, h,
fe33d2fa
CL		 10287 rel, globals,
10288 stub_type);
9cd3e4e5
NC		 10289 {
10290 if (stub_entry != NULL)
10291 value = (stub_entry->stub_offset
10292 + stub_entry->stub_sec->output_offset
10293 + stub_entry->stub_sec->output_section->vma);
10294
10295 if (plt_offset != (bfd_vma) -1)
10296 *unresolved_reloc_p = FALSE;
10297 }
906e58ca 10298 }
fe33d2fa
CL		 10299 else
10300 {
10301 /* If the call goes through a PLT entry, make sure to
10302 check distance to the right destination address. */
34e77a92 10303 if (plt_offset != (bfd_vma) -1)
fe33d2fa
CL		 10304 {
10305 value = (splt->output_section->vma
10306 + splt->output_offset
34e77a92 10307 + plt_offset);
fe33d2fa
CL		 10308 *unresolved_reloc_p = FALSE;
10309 /* The PLT entry is in ARM mode, regardless of the
10310 target function. */
35fc36a8 10311 branch_type = ST_BRANCH_TO_ARM;
fe33d2fa
CL		 10312 }
10313 }
906e58ca
NC		 10314 }
10315
dea514f5
PB		 10316 /* The ARM ELF ABI says that this reloc is computed as: S - P + A
10317 where:
10318 S is the address of the symbol in the relocation.
10319 P is address of the instruction being relocated.
10320 A is the addend (extracted from the instruction) in bytes.
10321
10322 S is held in 'value'.
10323 P is the base address of the section containing the
10324 instruction plus the offset of the reloc into that
10325 section, ie:
10326 (input_section->output_section->vma +
10327 input_section->output_offset +
10328 rel->r_offset).
10329 A is the addend, converted into bytes, ie:
10330 (signed_addend * 4)
10331
10332 Note: None of these operations have knowledge of the pipeline
10333 size of the processor, thus it is up to the assembler to
10334 encode this information into the addend. */
10335 value -= (input_section->output_section->vma
10336 + input_section->output_offset);
10337 value -= rel->r_offset;
4e7fd91e
PB		 10338 if (globals->use_rel)
10339 value += (signed_addend << howto->size);
10340 else
10341 /* RELA addends do not have to be adjusted by howto->size. */
10342 value += signed_addend;
23080146 10343
dcb5e6e6
NC		 10344 signed_addend = value;
10345 signed_addend >>= howto->rightshift;
9a5aca8c 10346
5ab79981 10347 /* A branch to an undefined weak symbol is turned into a jump to
ffcb4889 10348 the next instruction unless a PLT entry will be created.
77b4f08f 10349 Do the same for local undefined symbols (but not for STN_UNDEF).
cd1dac3d
DG		 10350 The jump to the next instruction is optimized as a NOP depending
10351 on the architecture. */
ffcb4889 10352 if (h ? (h->root.type == bfd_link_hash_undefweak
34e77a92 10353 && plt_offset == (bfd_vma) -1)
77b4f08f 10354 : r_symndx != STN_UNDEF && bfd_is_und_section (sym_sec))
5ab79981 10355 {
cd1dac3d
DG		 10356 value = (bfd_get_32 (input_bfd, hit_data) & 0xf0000000);
10357
10358 if (arch_has_arm_nop (globals))
10359 value |= 0x0320f000;
10360 else
10361 value |= 0x01a00000; /* Using pre-UAL nop: mov r0, r0. */
5ab79981
PB		 10362 }
10363 else
59f2c4e7 10364 {
9b485d32 10365 /* Perform a signed range check. */
dcb5e6e6 10366 if ( signed_addend > ((bfd_signed_vma) (howto->dst_mask >> 1))
59f2c4e7
NC		 10367 || signed_addend < - ((bfd_signed_vma) ((howto->dst_mask + 1) >> 1)))
10368 return bfd_reloc_overflow;
9a5aca8c 10369
5ab79981 10370 addend = (value & 2);
39b41c9c 10371
5ab79981
PB		 10372 value = (signed_addend & howto->dst_mask)
10373 | (bfd_get_32 (input_bfd, hit_data) & (~ howto->dst_mask));
39b41c9c 10374
5ab79981
PB		 10375 if (r_type == R_ARM_CALL)
10376 {
155d87d7 10377 /* Set the H bit in the BLX instruction. */
35fc36a8 10378 if (branch_type == ST_BRANCH_TO_THUMB)
155d87d7
CL		 10379 {
10380 if (addend)
10381 value |= (1 << 24);
10382 else
10383 value &= ~(bfd_vma)(1 << 24);
10384 }
10385
5ab79981 10386 /* Select the correct instruction (BL or BLX). */
906e58ca 10387 /* Only if we are not handling a BL to a stub. In this
8029a119 10388 case, mode switching is performed by the stub. */
35fc36a8 10389 if (branch_type == ST_BRANCH_TO_THUMB && !stub_entry)
5ab79981 10390 value |= (1 << 28);
63e1a0fc 10391 else if (stub_entry || branch_type != ST_BRANCH_UNKNOWN)
5ab79981
PB		 10392 {
10393 value &= ~(bfd_vma)(1 << 28);
10394 value |= (1 << 24);
10395 }
39b41c9c
PB		 10396 }
10397 }
906e58ca 10398 }
252b5132 10399 break;
f21f3fe0 10400
252b5132
RH		 10401 case R_ARM_ABS32:
10402 value += addend;
35fc36a8 10403 if (branch_type == ST_BRANCH_TO_THUMB)
252b5132
RH		 10404 value |= 1;
10405 break;
f21f3fe0 10406
bb224fc3
MS		 10407 case R_ARM_ABS32_NOI:
10408 value += addend;
10409 break;
10410
252b5132 10411 case R_ARM_REL32:
a8bc6c78 10412 value += addend;
35fc36a8 10413 if (branch_type == ST_BRANCH_TO_THUMB)
a8bc6c78 10414 value |= 1;
252b5132 10415 value -= (input_section->output_section->vma
62efb346 10416 + input_section->output_offset + rel->r_offset);
252b5132 10417 break;
eb043451 10418
bb224fc3
MS		 10419 case R_ARM_REL32_NOI:
10420 value += addend;
10421 value -= (input_section->output_section->vma
10422 + input_section->output_offset + rel->r_offset);
10423 break;
10424
eb043451
PB		 10425 case R_ARM_PREL31:
10426 value -= (input_section->output_section->vma
10427 + input_section->output_offset + rel->r_offset);
10428 value += signed_addend;
10429 if (! h || h->root.type != bfd_link_hash_undefweak)
10430 {
8029a119 10431 /* Check for overflow. */
eb043451
PB		 10432 if ((value ^ (value >> 1)) & (1 << 30))
10433 return bfd_reloc_overflow;
10434 }
10435 value &= 0x7fffffff;
10436 value |= (bfd_get_32 (input_bfd, hit_data) & 0x80000000);
35fc36a8 10437 if (branch_type == ST_BRANCH_TO_THUMB)
eb043451
PB		 10438 value |= 1;
10439 break;
252b5132 10440 }
f21f3fe0 10441
252b5132
RH		 10442 bfd_put_32 (input_bfd, value, hit_data);
10443 return bfd_reloc_ok;
10444
10445 case R_ARM_ABS8:
fd0fd00c
MJ		 10446 /* PR 16202: Refectch the addend using the correct size. */
10447 if (globals->use_rel)
10448 addend = bfd_get_8 (input_bfd, hit_data);
252b5132 10449 value += addend;
4e67d4ca
DG		 10450
10451 /* There is no way to tell whether the user intended to use a signed or
10452 unsigned addend. When checking for overflow we accept either,
10453 as specified by the AAELF. */
10454 if ((long) value > 0xff || (long) value < -0x80)
252b5132
RH		 10455 return bfd_reloc_overflow;
10456
10457 bfd_put_8 (input_bfd, value, hit_data);
10458 return bfd_reloc_ok;
10459
10460 case R_ARM_ABS16:
fd0fd00c
MJ		 10461 /* PR 16202: Refectch the addend using the correct size. */
10462 if (globals->use_rel)
10463 addend = bfd_get_16 (input_bfd, hit_data);
252b5132
RH		 10464 value += addend;
10465
4e67d4ca
DG		 10466 /* See comment for R_ARM_ABS8. */
10467 if ((long) value > 0xffff || (long) value < -0x8000)
252b5132
RH		 10468 return bfd_reloc_overflow;
10469
10470 bfd_put_16 (input_bfd, value, hit_data);
10471 return bfd_reloc_ok;
10472
252b5132 10473 case R_ARM_THM_ABS5:
9b485d32 10474 /* Support ldr and str instructions for the thumb. */
4e7fd91e
PB		 10475 if (globals->use_rel)
10476 {
10477 /* Need to refetch addend. */
10478 addend = bfd_get_16 (input_bfd, hit_data) & howto->src_mask;
10479 /* ??? Need to determine shift amount from operand size. */
10480 addend >>= howto->rightshift;
10481 }
252b5132
RH		 10482 value += addend;
10483
10484 /* ??? Isn't value unsigned? */
10485 if ((long) value > 0x1f || (long) value < -0x10)
10486 return bfd_reloc_overflow;
10487
10488 /* ??? Value needs to be properly shifted into place first. */
10489 value |= bfd_get_16 (input_bfd, hit_data) & 0xf83f;
10490 bfd_put_16 (input_bfd, value, hit_data);
10491 return bfd_reloc_ok;
10492
2cab6cc3
MS		 10493 case R_ARM_THM_ALU_PREL_11_0:
10494 /* Corresponds to: addw.w reg, pc, #offset (and similarly for subw). */
10495 {
10496 bfd_vma insn;
10497 bfd_signed_vma relocation;
10498
10499 insn = (bfd_get_16 (input_bfd, hit_data) << 16)
99059e56 10500 | bfd_get_16 (input_bfd, hit_data + 2);
2cab6cc3 10501
99059e56
RM		 10502 if (globals->use_rel)
10503 {
10504 signed_addend = (insn & 0xff) | ((insn & 0x7000) >> 4)
10505 | ((insn & (1 << 26)) >> 15);
10506 if (insn & 0xf00000)
10507 signed_addend = -signed_addend;
10508 }
2cab6cc3
MS		 10509
10510 relocation = value + signed_addend;
79f08007 10511 relocation -= Pa (input_section->output_section->vma
99059e56
RM		 10512 + input_section->output_offset
10513 + rel->r_offset);
2cab6cc3 10514
b6518b38 10515 value = relocation;
2cab6cc3 10516
99059e56
RM		 10517 if (value >= 0x1000)
10518 return bfd_reloc_overflow;
2cab6cc3
MS		 10519
10520 insn = (insn & 0xfb0f8f00) | (value & 0xff)
99059e56
RM		 10521 | ((value & 0x700) << 4)
10522 | ((value & 0x800) << 15);
10523 if (relocation < 0)
10524 insn |= 0xa00000;
2cab6cc3
MS		 10525
10526 bfd_put_16 (input_bfd, insn >> 16, hit_data);
10527 bfd_put_16 (input_bfd, insn & 0xffff, hit_data + 2);
10528
99059e56 10529 return bfd_reloc_ok;
2cab6cc3
MS		 10530 }
10531
e1ec24c6
NC		 10532 case R_ARM_THM_PC8:
10533 /* PR 10073: This reloc is not generated by the GNU toolchain,
10534 but it is supported for compatibility with third party libraries
10535 generated by other compilers, specifically the ARM/IAR. */
10536 {
10537 bfd_vma insn;
10538 bfd_signed_vma relocation;
10539
10540 insn = bfd_get_16 (input_bfd, hit_data);
10541
99059e56 10542 if (globals->use_rel)
79f08007 10543 addend = ((((insn & 0x00ff) << 2) + 4) & 0x3ff) -4;
e1ec24c6
NC		 10544
10545 relocation = value + addend;
79f08007 10546 relocation -= Pa (input_section->output_section->vma
99059e56
RM		 10547 + input_section->output_offset
10548 + rel->r_offset);
e1ec24c6 10549
b6518b38 10550 value = relocation;
e1ec24c6
NC		 10551
10552 /* We do not check for overflow of this reloc. Although strictly
10553 speaking this is incorrect, it appears to be necessary in order
10554 to work with IAR generated relocs. Since GCC and GAS do not
10555 generate R_ARM_THM_PC8 relocs, the lack of a check should not be
10556 a problem for them. */
10557 value &= 0x3fc;
10558
10559 insn = (insn & 0xff00) | (value >> 2);
10560
10561 bfd_put_16 (input_bfd, insn, hit_data);
10562
99059e56 10563 return bfd_reloc_ok;
e1ec24c6
NC		 10564 }
10565
2cab6cc3
MS		 10566 case R_ARM_THM_PC12:
10567 /* Corresponds to: ldr.w reg, [pc, #offset]. */
10568 {
10569 bfd_vma insn;
10570 bfd_signed_vma relocation;
10571
10572 insn = (bfd_get_16 (input_bfd, hit_data) << 16)
99059e56 10573 | bfd_get_16 (input_bfd, hit_data + 2);
2cab6cc3 10574
99059e56
RM		 10575 if (globals->use_rel)
10576 {
10577 signed_addend = insn & 0xfff;
10578 if (!(insn & (1 << 23)))
10579 signed_addend = -signed_addend;
10580 }
2cab6cc3
MS		 10581
10582 relocation = value + signed_addend;
79f08007 10583 relocation -= Pa (input_section->output_section->vma
99059e56
RM		 10584 + input_section->output_offset
10585 + rel->r_offset);
2cab6cc3 10586
b6518b38 10587 value = relocation;
2cab6cc3 10588
99059e56
RM		 10589 if (value >= 0x1000)
10590 return bfd_reloc_overflow;
2cab6cc3
MS		 10591
10592 insn = (insn & 0xff7ff000) | value;
99059e56
RM		 10593 if (relocation >= 0)
10594 insn |= (1 << 23);
2cab6cc3
MS		 10595
10596 bfd_put_16 (input_bfd, insn >> 16, hit_data);
10597 bfd_put_16 (input_bfd, insn & 0xffff, hit_data + 2);
10598
99059e56 10599 return bfd_reloc_ok;
2cab6cc3
MS		 10600 }
10601
dfc5f959 10602 case R_ARM_THM_XPC22:
c19d1205 10603 case R_ARM_THM_CALL:
bd97cb95 10604 case R_ARM_THM_JUMP24:
dfc5f959 10605 /* Thumb BL (branch long instruction). */
252b5132 10606 {
b34976b6 10607 bfd_vma relocation;
99059e56 10608 bfd_vma reloc_sign;
b34976b6
AM		 10609 bfd_boolean overflow = FALSE;
10610 bfd_vma upper_insn = bfd_get_16 (input_bfd, hit_data);
10611 bfd_vma lower_insn = bfd_get_16 (input_bfd, hit_data + 2);
e95de063
MS		 10612 bfd_signed_vma reloc_signed_max;
10613 bfd_signed_vma reloc_signed_min;
b34976b6 10614 bfd_vma check;
252b5132 10615 bfd_signed_vma signed_check;
e95de063 10616 int bitsize;
cd1dac3d 10617 const int thumb2 = using_thumb2 (globals);
5e866f5a 10618 const int thumb2_bl = using_thumb2_bl (globals);
252b5132 10619
5ab79981 10620 /* A branch to an undefined weak symbol is turned into a jump to
cd1dac3d
DG		 10621 the next instruction unless a PLT entry will be created.
10622 The jump to the next instruction is optimized as a NOP.W for
10623 Thumb-2 enabled architectures. */
19540007 10624 if (h && h->root.type == bfd_link_hash_undefweak
34e77a92 10625 && plt_offset == (bfd_vma) -1)
5ab79981 10626 {
60a019a0 10627 if (thumb2)
cd1dac3d
DG		 10628 {
10629 bfd_put_16 (input_bfd, 0xf3af, hit_data);
10630 bfd_put_16 (input_bfd, 0x8000, hit_data + 2);
10631 }
10632 else
10633 {
10634 bfd_put_16 (input_bfd, 0xe000, hit_data);
10635 bfd_put_16 (input_bfd, 0xbf00, hit_data + 2);
10636 }
5ab79981
PB		 10637 return bfd_reloc_ok;
10638 }
10639
e95de063 10640 /* Fetch the addend. We use the Thumb-2 encoding (backwards compatible
99059e56 10641 with Thumb-1) involving the J1 and J2 bits. */
4e7fd91e
PB		 10642 if (globals->use_rel)
10643 {
99059e56
RM		 10644 bfd_vma s = (upper_insn & (1 << 10)) >> 10;
10645 bfd_vma upper = upper_insn & 0x3ff;
10646 bfd_vma lower = lower_insn & 0x7ff;
e95de063
MS		 10647 bfd_vma j1 = (lower_insn & (1 << 13)) >> 13;
10648 bfd_vma j2 = (lower_insn & (1 << 11)) >> 11;
99059e56
RM		 10649 bfd_vma i1 = j1 ^ s ? 0 : 1;
10650 bfd_vma i2 = j2 ^ s ? 0 : 1;
e95de063 10651
99059e56
RM		 10652 addend = (i1 << 23) | (i2 << 22) | (upper << 12) | (lower << 1);
10653 /* Sign extend. */
10654 addend = (addend | ((s ? 0 : 1) << 24)) - (1 << 24);
e95de063 10655
4e7fd91e
PB		 10656 signed_addend = addend;
10657 }
cb1afa5c 10658
dfc5f959
NC		 10659 if (r_type == R_ARM_THM_XPC22)
10660 {
10661 /* Check for Thumb to Thumb call. */
10662 /* FIXME: Should we translate the instruction into a BL
10663 instruction instead ? */
35fc36a8 10664 if (branch_type == ST_BRANCH_TO_THUMB)
4eca0228 10665 _bfd_error_handler
d003868e
AM		 10666 (_("%B: Warning: Thumb BLX instruction targets thumb function '%s'."),
10667 input_bfd,
10668 h ? h->root.root.string : "(local)");
dfc5f959
NC		 10669 }
10670 else
252b5132 10671 {
dfc5f959
NC		 10672 /* If it is not a call to Thumb, assume call to Arm.
10673 If it is a call relative to a section name, then it is not a
b7693d02
DJ		 10674 function call at all, but rather a long jump. Calls through
10675 the PLT do not require stubs. */
34e77a92 10676 if (branch_type == ST_BRANCH_TO_ARM && plt_offset == (bfd_vma) -1)
dfc5f959 10677 {
bd97cb95 10678 if (globals->use_blx && r_type == R_ARM_THM_CALL)
39b41c9c
PB		 10679 {
10680 /* Convert BL to BLX. */
10681 lower_insn = (lower_insn & ~0x1000) | 0x0800;
10682 }
155d87d7
CL		 10683 else if (( r_type != R_ARM_THM_CALL)
10684 && (r_type != R_ARM_THM_JUMP24))
8029a119
NC		 10685 {
10686 if (elf32_thumb_to_arm_stub
10687 (info, sym_name, input_bfd, output_bfd, input_section,
10688 hit_data, sym_sec, rel->r_offset, signed_addend, value,
10689 error_message))
10690 return bfd_reloc_ok;
10691 else
10692 return bfd_reloc_dangerous;
10693 }
da5938a2 10694 }
35fc36a8
RS		 10695 else if (branch_type == ST_BRANCH_TO_THUMB
10696 && globals->use_blx
bd97cb95 10697 && r_type == R_ARM_THM_CALL)
39b41c9c
PB		 10698 {
10699 /* Make sure this is a BL. */
10700 lower_insn |= 0x1800;
10701 }
252b5132 10702 }
f21f3fe0 10703
fe33d2fa 10704 enum elf32_arm_stub_type stub_type = arm_stub_none;
155d87d7 10705 if (r_type == R_ARM_THM_CALL || r_type == R_ARM_THM_JUMP24)
906e58ca
NC		 10706 {
10707 /* Check if a stub has to be inserted because the destination
8029a119 10708 is too far. */
fe33d2fa
CL		 10709 struct elf32_arm_stub_hash_entry *stub_entry;
10710 struct elf32_arm_link_hash_entry *hash;
10711
10712 hash = (struct elf32_arm_link_hash_entry *) h;
10713
10714 stub_type = arm_type_of_stub (info, input_section, rel,
34e77a92
RS		 10715 st_type, &branch_type,
10716 hash, value, sym_sec,
fe33d2fa
CL		 10717 input_bfd, sym_name);
10718
10719 if (stub_type != arm_stub_none)
906e58ca
NC		 10720 {
10721 /* The target is out of reach or we are changing modes, so
10722 redirect the branch to the local stub for this
10723 function. */
10724 stub_entry = elf32_arm_get_stub_entry (input_section,
10725 sym_sec, h,
fe33d2fa
CL		 10726 rel, globals,
10727 stub_type);
906e58ca 10728 if (stub_entry != NULL)
9cd3e4e5
NC		 10729 {
10730 value = (stub_entry->stub_offset
10731 + stub_entry->stub_sec->output_offset
10732 + stub_entry->stub_sec->output_section->vma);
10733
10734 if (plt_offset != (bfd_vma) -1)
10735 *unresolved_reloc_p = FALSE;
10736 }
906e58ca 10737
f4ac8484 10738 /* If this call becomes a call to Arm, force BLX. */
155d87d7 10739 if (globals->use_blx && (r_type == R_ARM_THM_CALL))
f4ac8484
DJ		 10740 {
10741 if ((stub_entry
10742 && !arm_stub_is_thumb (stub_entry->stub_type))
35fc36a8 10743 || branch_type != ST_BRANCH_TO_THUMB)
f4ac8484
DJ		 10744 lower_insn = (lower_insn & ~0x1000) | 0x0800;
10745 }
906e58ca
NC		 10746 }
10747 }
10748
fe33d2fa 10749 /* Handle calls via the PLT. */
34e77a92 10750 if (stub_type == arm_stub_none && plt_offset != (bfd_vma) -1)
fe33d2fa
CL		 10751 {
10752 value = (splt->output_section->vma
10753 + splt->output_offset
34e77a92 10754 + plt_offset);
fe33d2fa 10755
eed94f8f
NC		 10756 if (globals->use_blx
10757 && r_type == R_ARM_THM_CALL
10758 && ! using_thumb_only (globals))
fe33d2fa
CL		 10759 {
10760 /* If the Thumb BLX instruction is available, convert
10761 the BL to a BLX instruction to call the ARM-mode
10762 PLT entry. */
10763 lower_insn = (lower_insn & ~0x1000) | 0x0800;
35fc36a8 10764 branch_type = ST_BRANCH_TO_ARM;
fe33d2fa
CL		 10765 }
10766 else
10767 {
eed94f8f
NC		 10768 if (! using_thumb_only (globals))
10769 /* Target the Thumb stub before the ARM PLT entry. */
10770 value -= PLT_THUMB_STUB_SIZE;
35fc36a8 10771 branch_type = ST_BRANCH_TO_THUMB;
fe33d2fa
CL		 10772 }
10773 *unresolved_reloc_p = FALSE;
10774 }
10775
ba96a88f 10776 relocation = value + signed_addend;
f21f3fe0 10777
252b5132 10778 relocation -= (input_section->output_section->vma
ba96a88f
NC		 10779 + input_section->output_offset
10780 + rel->r_offset);
9a5aca8c 10781
252b5132
RH		 10782 check = relocation >> howto->rightshift;
10783
10784 /* If this is a signed value, the rightshift just dropped
10785 leading 1 bits (assuming twos complement). */
10786 if ((bfd_signed_vma) relocation >= 0)
10787 signed_check = check;
10788 else
10789 signed_check = check | ~((bfd_vma) -1 >> howto->rightshift);
10790
e95de063
MS		 10791 /* Calculate the permissable maximum and minimum values for
10792 this relocation according to whether we're relocating for
10793 Thumb-2 or not. */
10794 bitsize = howto->bitsize;
5e866f5a 10795 if (!thumb2_bl)
e95de063 10796 bitsize -= 2;
f6ebfac0 10797 reloc_signed_max = (1 << (bitsize - 1)) - 1;
e95de063
MS		 10798 reloc_signed_min = ~reloc_signed_max;
10799
252b5132 10800 /* Assumes two's complement. */
ba96a88f 10801 if (signed_check > reloc_signed_max || signed_check < reloc_signed_min)
b34976b6 10802 overflow = TRUE;
252b5132 10803
bd97cb95 10804 if ((lower_insn & 0x5000) == 0x4000)
c62e1cc3
NC		 10805 /* For a BLX instruction, make sure that the relocation is rounded up
10806 to a word boundary. This follows the semantics of the instruction
10807 which specifies that bit 1 of the target address will come from bit
10808 1 of the base address. */
10809 relocation = (relocation + 2) & ~ 3;
cb1afa5c 10810
e95de063
MS		 10811 /* Put RELOCATION back into the insn. Assumes two's complement.
10812 We use the Thumb-2 encoding, which is safe even if dealing with
10813 a Thumb-1 instruction by virtue of our overflow check above. */
99059e56 10814 reloc_sign = (signed_check < 0) ? 1 : 0;
e95de063 10815 upper_insn = (upper_insn & ~(bfd_vma) 0x7ff)
99059e56
RM		 10816 | ((relocation >> 12) & 0x3ff)
10817 | (reloc_sign << 10);
906e58ca 10818 lower_insn = (lower_insn & ~(bfd_vma) 0x2fff)
99059e56
RM		 10819 | (((!((relocation >> 23) & 1)) ^ reloc_sign) << 13)
10820 | (((!((relocation >> 22) & 1)) ^ reloc_sign) << 11)
10821 | ((relocation >> 1) & 0x7ff);
c62e1cc3 10822
252b5132
RH		 10823 /* Put the relocated value back in the object file: */
10824 bfd_put_16 (input_bfd, upper_insn, hit_data);
10825 bfd_put_16 (input_bfd, lower_insn, hit_data + 2);
10826
10827 return (overflow ? bfd_reloc_overflow : bfd_reloc_ok);
10828 }
10829 break;
10830
c19d1205
ZW		 10831 case R_ARM_THM_JUMP19:
10832 /* Thumb32 conditional branch instruction. */
10833 {
10834 bfd_vma relocation;
10835 bfd_boolean overflow = FALSE;
10836 bfd_vma upper_insn = bfd_get_16 (input_bfd, hit_data);
10837 bfd_vma lower_insn = bfd_get_16 (input_bfd, hit_data + 2);
a00a1f35
MS		 10838 bfd_signed_vma reloc_signed_max = 0xffffe;
10839 bfd_signed_vma reloc_signed_min = -0x100000;
c19d1205 10840 bfd_signed_vma signed_check;
c5423981
TG		 10841 enum elf32_arm_stub_type stub_type = arm_stub_none;
10842 struct elf32_arm_stub_hash_entry *stub_entry;
10843 struct elf32_arm_link_hash_entry *hash;
c19d1205
ZW		 10844
10845 /* Need to refetch the addend, reconstruct the top three bits,
10846 and squish the two 11 bit pieces together. */
10847 if (globals->use_rel)
10848 {
10849 bfd_vma S = (upper_insn & 0x0400) >> 10;
a00a1f35 10850 bfd_vma upper = (upper_insn & 0x003f);
c19d1205
ZW		 10851 bfd_vma J1 = (lower_insn & 0x2000) >> 13;
10852 bfd_vma J2 = (lower_insn & 0x0800) >> 11;
10853 bfd_vma lower = (lower_insn & 0x07ff);
10854
a00a1f35
MS		 10855 upper |= J1 << 6;
10856 upper |= J2 << 7;
10857 upper |= (!S) << 8;
c19d1205
ZW		 10858 upper -= 0x0100; /* Sign extend. */
10859
10860 addend = (upper << 12) | (lower << 1);
10861 signed_addend = addend;
10862 }
10863
bd97cb95 10864 /* Handle calls via the PLT. */
34e77a92 10865 if (plt_offset != (bfd_vma) -1)
bd97cb95
DJ		 10866 {
10867 value = (splt->output_section->vma
10868 + splt->output_offset
34e77a92 10869 + plt_offset);
bd97cb95
DJ		 10870 /* Target the Thumb stub before the ARM PLT entry. */
10871 value -= PLT_THUMB_STUB_SIZE;
10872 *unresolved_reloc_p = FALSE;
10873 }
10874
c5423981
TG		 10875 hash = (struct elf32_arm_link_hash_entry *)h;
10876
10877 stub_type = arm_type_of_stub (info, input_section, rel,
10878 st_type, &branch_type,
10879 hash, value, sym_sec,
10880 input_bfd, sym_name);
10881 if (stub_type != arm_stub_none)
10882 {
10883 stub_entry = elf32_arm_get_stub_entry (input_section,
10884 sym_sec, h,
10885 rel, globals,
10886 stub_type);
10887 if (stub_entry != NULL)
10888 {
10889 value = (stub_entry->stub_offset
10890 + stub_entry->stub_sec->output_offset
10891 + stub_entry->stub_sec->output_section->vma);
10892 }
10893 }
c19d1205 10894
99059e56 10895 relocation = value + signed_addend;
c19d1205
ZW		 10896 relocation -= (input_section->output_section->vma
10897 + input_section->output_offset
10898 + rel->r_offset);
a00a1f35 10899 signed_check = (bfd_signed_vma) relocation;
c19d1205 10900
c19d1205
ZW		 10901 if (signed_check > reloc_signed_max || signed_check < reloc_signed_min)
10902 overflow = TRUE;
10903
10904 /* Put RELOCATION back into the insn. */
10905 {
10906 bfd_vma S = (relocation & 0x00100000) >> 20;
10907 bfd_vma J2 = (relocation & 0x00080000) >> 19;
10908 bfd_vma J1 = (relocation & 0x00040000) >> 18;
10909 bfd_vma hi = (relocation & 0x0003f000) >> 12;
10910 bfd_vma lo = (relocation & 0x00000ffe) >> 1;
10911
a00a1f35 10912 upper_insn = (upper_insn & 0xfbc0) | (S << 10) | hi;
c19d1205
ZW		 10913 lower_insn = (lower_insn & 0xd000) | (J1 << 13) | (J2 << 11) | lo;
10914 }
10915
10916 /* Put the relocated value back in the object file: */
10917 bfd_put_16 (input_bfd, upper_insn, hit_data);
10918 bfd_put_16 (input_bfd, lower_insn, hit_data + 2);
10919
10920 return (overflow ? bfd_reloc_overflow : bfd_reloc_ok);
10921 }
10922
10923 case R_ARM_THM_JUMP11:
10924 case R_ARM_THM_JUMP8:
10925 case R_ARM_THM_JUMP6:
51c5503b
NC		 10926 /* Thumb B (branch) instruction). */
10927 {
6cf9e9fe 10928 bfd_signed_vma relocation;
51c5503b
NC		 10929 bfd_signed_vma reloc_signed_max = (1 << (howto->bitsize - 1)) - 1;
10930 bfd_signed_vma reloc_signed_min = ~ reloc_signed_max;
51c5503b
NC		 10931 bfd_signed_vma signed_check;
10932
c19d1205
ZW		 10933 /* CZB cannot jump backward. */
10934 if (r_type == R_ARM_THM_JUMP6)
10935 reloc_signed_min = 0;
10936
4e7fd91e 10937 if (globals->use_rel)
6cf9e9fe 10938 {
4e7fd91e
PB		 10939 /* Need to refetch addend. */
10940 addend = bfd_get_16 (input_bfd, hit_data) & howto->src_mask;
10941 if (addend & ((howto->src_mask + 1) >> 1))
10942 {
10943 signed_addend = -1;
10944 signed_addend &= ~ howto->src_mask;
10945 signed_addend |= addend;
10946 }
10947 else
10948 signed_addend = addend;
10949 /* The value in the insn has been right shifted. We need to
10950 undo this, so that we can perform the address calculation
10951 in terms of bytes. */
10952 signed_addend <<= howto->rightshift;
6cf9e9fe 10953 }
6cf9e9fe 10954 relocation = value + signed_addend;
51c5503b
NC		 10955
10956 relocation -= (input_section->output_section->vma
10957 + input_section->output_offset
10958 + rel->r_offset);
10959
6cf9e9fe
NC		 10960 relocation >>= howto->rightshift;
10961 signed_check = relocation;
c19d1205
ZW		 10962
10963 if (r_type == R_ARM_THM_JUMP6)
10964 relocation = ((relocation & 0x0020) << 4) | ((relocation & 0x001f) << 3);
10965 else
10966 relocation &= howto->dst_mask;
51c5503b 10967 relocation |= (bfd_get_16 (input_bfd, hit_data) & (~ howto->dst_mask));
cedb70c5 10968
51c5503b
NC		 10969 bfd_put_16 (input_bfd, relocation, hit_data);
10970
10971 /* Assumes two's complement. */
10972 if (signed_check > reloc_signed_max || signed_check < reloc_signed_min)
10973 return bfd_reloc_overflow;
10974
10975 return bfd_reloc_ok;
10976 }
cedb70c5 10977
8375c36b
PB		 10978 case R_ARM_ALU_PCREL7_0:
10979 case R_ARM_ALU_PCREL15_8:
10980 case R_ARM_ALU_PCREL23_15:
10981 {
10982 bfd_vma insn;
10983 bfd_vma relocation;
10984
10985 insn = bfd_get_32 (input_bfd, hit_data);
4e7fd91e
PB		 10986 if (globals->use_rel)
10987 {
10988 /* Extract the addend. */
10989 addend = (insn & 0xff) << ((insn & 0xf00) >> 7);
10990 signed_addend = addend;
10991 }
8375c36b
PB		 10992 relocation = value + signed_addend;
10993
10994 relocation -= (input_section->output_section->vma
10995 + input_section->output_offset
10996 + rel->r_offset);
10997 insn = (insn & ~0xfff)
10998 | ((howto->bitpos << 7) & 0xf00)
10999 | ((relocation >> howto->bitpos) & 0xff);
11000 bfd_put_32 (input_bfd, value, hit_data);
11001 }
11002 return bfd_reloc_ok;
11003
252b5132
RH		 11004 case R_ARM_GNU_VTINHERIT:
11005 case R_ARM_GNU_VTENTRY:
11006 return bfd_reloc_ok;
11007
c19d1205 11008 case R_ARM_GOTOFF32:
252b5132 11009 /* Relocation is relative to the start of the
99059e56 11010 global offset table. */
252b5132
RH		 11011
11012 BFD_ASSERT (sgot != NULL);
11013 if (sgot == NULL)
99059e56 11014 return bfd_reloc_notsupported;
9a5aca8c 11015
cedb70c5 11016 /* If we are addressing a Thumb function, we need to adjust the
ee29b9fb
RE		 11017 address by one, so that attempts to call the function pointer will
11018 correctly interpret it as Thumb code. */
35fc36a8 11019 if (branch_type == ST_BRANCH_TO_THUMB)
ee29b9fb
RE		 11020 value += 1;
11021
252b5132 11022 /* Note that sgot->output_offset is not involved in this
99059e56
RM		 11023 calculation. We always want the start of .got. If we
11024 define _GLOBAL_OFFSET_TABLE in a different way, as is
11025 permitted by the ABI, we might have to change this
11026 calculation. */
252b5132 11027 value -= sgot->output_section->vma;
f21f3fe0 11028 return _bfd_final_link_relocate (howto, input_bfd, input_section,
99e4ae17 11029 contents, rel->r_offset, value,
00a97672 11030 rel->r_addend);
252b5132
RH		 11031
11032 case R_ARM_GOTPC:
a7c10850 11033 /* Use global offset table as symbol value. */
252b5132 11034 BFD_ASSERT (sgot != NULL);
f21f3fe0 11035
252b5132 11036 if (sgot == NULL)
99059e56 11037 return bfd_reloc_notsupported;
252b5132 11038
0945cdfd 11039 *unresolved_reloc_p = FALSE;
252b5132 11040 value = sgot->output_section->vma;
f21f3fe0 11041 return _bfd_final_link_relocate (howto, input_bfd, input_section,
99e4ae17 11042 contents, rel->r_offset, value,
00a97672 11043 rel->r_addend);
f21f3fe0 11044
252b5132 11045 case R_ARM_GOT32:
eb043451 11046 case R_ARM_GOT_PREL:
252b5132 11047 /* Relocation is to the entry for this symbol in the
99059e56 11048 global offset table. */
252b5132
RH		 11049 if (sgot == NULL)
11050 return bfd_reloc_notsupported;
f21f3fe0 11051
34e77a92
RS		 11052 if (dynreloc_st_type == STT_GNU_IFUNC
11053 && plt_offset != (bfd_vma) -1
11054 && (h == NULL || SYMBOL_REFERENCES_LOCAL (info, h)))
11055 {
11056 /* We have a relocation against a locally-binding STT_GNU_IFUNC
11057 symbol, and the relocation resolves directly to the runtime
11058 target rather than to the .iplt entry. This means that any
11059 .got entry would be the same value as the .igot.plt entry,
11060 so there's no point creating both. */
11061 sgot = globals->root.igotplt;
11062 value = sgot->output_offset + gotplt_offset;
11063 }
11064 else if (h != NULL)
252b5132
RH		 11065 {
11066 bfd_vma off;
f21f3fe0 11067
252b5132
RH		 11068 off = h->got.offset;
11069 BFD_ASSERT (off != (bfd_vma) -1);
b436d854 11070 if ((off & 1) != 0)
252b5132 11071 {
b436d854
RS		 11072 /* We have already processsed one GOT relocation against
11073 this symbol. */
11074 off &= ~1;
11075 if (globals->root.dynamic_sections_created
11076 && !SYMBOL_REFERENCES_LOCAL (info, h))
11077 *unresolved_reloc_p = FALSE;
11078 }
11079 else
11080 {
11081 Elf_Internal_Rela outrel;
11082
6f820c85 11083 if (h->dynindx != -1 && !SYMBOL_REFERENCES_LOCAL (info, h))
b436d854
RS		 11084 {
11085 /* If the symbol doesn't resolve locally in a static
11086 object, we have an undefined reference. If the
11087 symbol doesn't resolve locally in a dynamic object,
11088 it should be resolved by the dynamic linker. */
11089 if (globals->root.dynamic_sections_created)
11090 {
11091 outrel.r_info = ELF32_R_INFO (h->dynindx, R_ARM_GLOB_DAT);
11092 *unresolved_reloc_p = FALSE;
11093 }
11094 else
11095 outrel.r_info = 0;
11096 outrel.r_addend = 0;
11097 }
252b5132
RH		 11098 else
11099 {
34e77a92 11100 if (dynreloc_st_type == STT_GNU_IFUNC)
99059e56 11101 outrel.r_info = ELF32_R_INFO (0, R_ARM_IRELATIVE);
5025eb7c
AO		 11102 else if (bfd_link_pic (info)
11103 && (ELF_ST_VISIBILITY (h->other) == STV_DEFAULT
11104 || h->root.type != bfd_link_hash_undefweak))
99059e56
RM		 11105 outrel.r_info = ELF32_R_INFO (0, R_ARM_RELATIVE);
11106 else
11107 outrel.r_info = 0;
34e77a92 11108 outrel.r_addend = dynreloc_value;
b436d854 11109 }
ee29b9fb 11110
b436d854
RS		 11111 /* The GOT entry is initialized to zero by default.
11112 See if we should install a different value. */
11113 if (outrel.r_addend != 0
11114 && (outrel.r_info == 0 || globals->use_rel))
11115 {
11116 bfd_put_32 (output_bfd, outrel.r_addend,
11117 sgot->contents + off);
11118 outrel.r_addend = 0;
252b5132 11119 }
f21f3fe0 11120
b436d854
RS		 11121 if (outrel.r_info != 0)
11122 {
11123 outrel.r_offset = (sgot->output_section->vma
11124 + sgot->output_offset
11125 + off);
11126 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
11127 }
11128 h->got.offset |= 1;
11129 }
252b5132
RH		 11130 value = sgot->output_offset + off;
11131 }
11132 else
11133 {
11134 bfd_vma off;
f21f3fe0 11135
5025eb7c
AO		 11136 BFD_ASSERT (local_got_offsets != NULL
11137 && local_got_offsets[r_symndx] != (bfd_vma) -1);
f21f3fe0 11138
252b5132 11139 off = local_got_offsets[r_symndx];
f21f3fe0 11140
252b5132
RH		 11141 /* The offset must always be a multiple of 4. We use the
11142 least significant bit to record whether we have already
9b485d32 11143 generated the necessary reloc. */
252b5132
RH		 11144 if ((off & 1) != 0)
11145 off &= ~1;
11146 else
11147 {
00a97672 11148 if (globals->use_rel)
34e77a92 11149 bfd_put_32 (output_bfd, dynreloc_value, sgot->contents + off);
f21f3fe0 11150
0e1862bb 11151 if (bfd_link_pic (info) || dynreloc_st_type == STT_GNU_IFUNC)
252b5132 11152 {
947216bf 11153 Elf_Internal_Rela outrel;
f21f3fe0 11154
34e77a92 11155 outrel.r_addend = addend + dynreloc_value;
252b5132 11156 outrel.r_offset = (sgot->output_section->vma
f21f3fe0 11157 + sgot->output_offset
252b5132 11158 + off);
34e77a92 11159 if (dynreloc_st_type == STT_GNU_IFUNC)
99059e56 11160 outrel.r_info = ELF32_R_INFO (0, R_ARM_IRELATIVE);
34e77a92
RS		 11161 else
11162 outrel.r_info = ELF32_R_INFO (0, R_ARM_RELATIVE);
47beaa6a 11163 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
252b5132 11164 }
f21f3fe0 11165
252b5132
RH		 11166 local_got_offsets[r_symndx] |= 1;
11167 }
f21f3fe0 11168
252b5132
RH		 11169 value = sgot->output_offset + off;
11170 }
eb043451
PB		 11171 if (r_type != R_ARM_GOT32)
11172 value += sgot->output_section->vma;
9a5aca8c 11173
f21f3fe0 11174 return _bfd_final_link_relocate (howto, input_bfd, input_section,
99e4ae17 11175 contents, rel->r_offset, value,
00a97672 11176 rel->r_addend);
f21f3fe0 11177
ba93b8ac
DJ		 11178 case R_ARM_TLS_LDO32:
11179 value = value - dtpoff_base (info);
11180
11181 return _bfd_final_link_relocate (howto, input_bfd, input_section,
00a97672
RS		 11182 contents, rel->r_offset, value,
11183 rel->r_addend);
ba93b8ac
DJ		 11184
11185 case R_ARM_TLS_LDM32:
11186 {
11187 bfd_vma off;
11188
362d30a1 11189 if (sgot == NULL)
ba93b8ac
DJ		 11190 abort ();
11191
11192 off = globals->tls_ldm_got.offset;
11193
11194 if ((off & 1) != 0)
11195 off &= ~1;
11196 else
11197 {
11198 /* If we don't know the module number, create a relocation
11199 for it. */
0e1862bb 11200 if (bfd_link_pic (info))
ba93b8ac
DJ		 11201 {
11202 Elf_Internal_Rela outrel;
ba93b8ac 11203
362d30a1 11204 if (srelgot == NULL)
ba93b8ac
DJ		 11205 abort ();
11206
00a97672 11207 outrel.r_addend = 0;
362d30a1
RS		 11208 outrel.r_offset = (sgot->output_section->vma
11209 + sgot->output_offset + off);
ba93b8ac
DJ		 11210 outrel.r_info = ELF32_R_INFO (0, R_ARM_TLS_DTPMOD32);
11211
00a97672
RS		 11212 if (globals->use_rel)
11213 bfd_put_32 (output_bfd, outrel.r_addend,
362d30a1 11214 sgot->contents + off);
ba93b8ac 11215
47beaa6a 11216 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
ba93b8ac
DJ		 11217 }
11218 else
362d30a1 11219 bfd_put_32 (output_bfd, 1, sgot->contents + off);
ba93b8ac
DJ		 11220
11221 globals->tls_ldm_got.offset |= 1;
11222 }
11223
362d30a1 11224 value = sgot->output_section->vma + sgot->output_offset + off
ba93b8ac
DJ		 11225 - (input_section->output_section->vma + input_section->output_offset + rel->r_offset);
11226
11227 return _bfd_final_link_relocate (howto, input_bfd, input_section,
11228 contents, rel->r_offset, value,
00a97672 11229 rel->r_addend);
ba93b8ac
DJ		 11230 }
11231
0855e32b
NS		 11232 case R_ARM_TLS_CALL:
11233 case R_ARM_THM_TLS_CALL:
ba93b8ac
DJ		 11234 case R_ARM_TLS_GD32:
11235 case R_ARM_TLS_IE32:
0855e32b
NS		 11236 case R_ARM_TLS_GOTDESC:
11237 case R_ARM_TLS_DESCSEQ:
11238 case R_ARM_THM_TLS_DESCSEQ:
ba93b8ac 11239 {
0855e32b
NS		 11240 bfd_vma off, offplt;
11241 int indx = 0;
ba93b8ac
DJ		 11242 char tls_type;
11243
0855e32b 11244 BFD_ASSERT (sgot != NULL);
ba93b8ac 11245
ba93b8ac
DJ		 11246 if (h != NULL)
11247 {
11248 bfd_boolean dyn;
11249 dyn = globals->root.dynamic_sections_created;
0e1862bb
L		 11250 if (WILL_CALL_FINISH_DYNAMIC_SYMBOL (dyn,
11251 bfd_link_pic (info),
11252 h)
11253 && (!bfd_link_pic (info)
ba93b8ac
DJ		 11254 || !SYMBOL_REFERENCES_LOCAL (info, h)))
11255 {
11256 *unresolved_reloc_p = FALSE;
11257 indx = h->dynindx;
11258 }
11259 off = h->got.offset;
0855e32b 11260 offplt = elf32_arm_hash_entry (h)->tlsdesc_got;
ba93b8ac
DJ		 11261 tls_type = ((struct elf32_arm_link_hash_entry *) h)->tls_type;
11262 }
11263 else
11264 {
0855e32b 11265 BFD_ASSERT (local_got_offsets != NULL);
ba93b8ac 11266 off = local_got_offsets[r_symndx];
0855e32b 11267 offplt = local_tlsdesc_gotents[r_symndx];
ba93b8ac
DJ		 11268 tls_type = elf32_arm_local_got_tls_type (input_bfd)[r_symndx];
11269 }
11270
0855e32b 11271 /* Linker relaxations happens from one of the
b38cadfb 11272 R_ARM_{GOTDESC,CALL,DESCSEQ} relocations to IE or LE. */
0855e32b 11273 if (ELF32_R_TYPE(rel->r_info) != r_type)
b38cadfb 11274 tls_type = GOT_TLS_IE;
0855e32b
NS		 11275
11276 BFD_ASSERT (tls_type != GOT_UNKNOWN);
ba93b8ac
DJ		 11277
11278 if ((off & 1) != 0)
11279 off &= ~1;
11280 else
11281 {
11282 bfd_boolean need_relocs = FALSE;
11283 Elf_Internal_Rela outrel;
ba93b8ac
DJ		 11284 int cur_off = off;
11285
11286 /* The GOT entries have not been initialized yet. Do it
11287 now, and emit any relocations. If both an IE GOT and a
11288 GD GOT are necessary, we emit the GD first. */
11289
0e1862bb 11290 if ((bfd_link_pic (info) || indx != 0)
ba93b8ac
DJ		 11291 && (h == NULL
11292 || ELF_ST_VISIBILITY (h->other) == STV_DEFAULT
11293 || h->root.type != bfd_link_hash_undefweak))
11294 {
11295 need_relocs = TRUE;
0855e32b 11296 BFD_ASSERT (srelgot != NULL);
ba93b8ac
DJ		 11297 }
11298
0855e32b
NS		 11299 if (tls_type & GOT_TLS_GDESC)
11300 {
47beaa6a
RS		 11301 bfd_byte *loc;
11302
0855e32b
NS		 11303 /* We should have relaxed, unless this is an undefined
11304 weak symbol. */
11305 BFD_ASSERT ((h && (h->root.type == bfd_link_hash_undefweak))
0e1862bb 11306 || bfd_link_pic (info));
0855e32b 11307 BFD_ASSERT (globals->sgotplt_jump_table_size + offplt + 8
99059e56 11308 <= globals->root.sgotplt->size);
0855e32b
NS		 11309
11310 outrel.r_addend = 0;
11311 outrel.r_offset = (globals->root.sgotplt->output_section->vma
11312 + globals->root.sgotplt->output_offset
11313 + offplt
11314 + globals->sgotplt_jump_table_size);
b38cadfb 11315
0855e32b
NS		 11316 outrel.r_info = ELF32_R_INFO (indx, R_ARM_TLS_DESC);
11317 sreloc = globals->root.srelplt;
11318 loc = sreloc->contents;
11319 loc += globals->next_tls_desc_index++ * RELOC_SIZE (globals);
11320 BFD_ASSERT (loc + RELOC_SIZE (globals)
99059e56 11321 <= sreloc->contents + sreloc->size);
0855e32b
NS		 11322
11323 SWAP_RELOC_OUT (globals) (output_bfd, &outrel, loc);
11324
11325 /* For globals, the first word in the relocation gets
11326 the relocation index and the top bit set, or zero,
11327 if we're binding now. For locals, it gets the
11328 symbol's offset in the tls section. */
99059e56 11329 bfd_put_32 (output_bfd,
0855e32b
NS		 11330 !h ? value - elf_hash_table (info)->tls_sec->vma
11331 : info->flags & DF_BIND_NOW ? 0
11332 : 0x80000000 | ELF32_R_SYM (outrel.r_info),
b38cadfb
NC		 11333 globals->root.sgotplt->contents + offplt
11334 + globals->sgotplt_jump_table_size);
11335
0855e32b 11336 /* Second word in the relocation is always zero. */
99059e56 11337 bfd_put_32 (output_bfd, 0,
b38cadfb
NC		 11338 globals->root.sgotplt->contents + offplt
11339 + globals->sgotplt_jump_table_size + 4);
0855e32b 11340 }
ba93b8ac
DJ		 11341 if (tls_type & GOT_TLS_GD)
11342 {
11343 if (need_relocs)
11344 {
00a97672 11345 outrel.r_addend = 0;
362d30a1
RS		 11346 outrel.r_offset = (sgot->output_section->vma
11347 + sgot->output_offset
00a97672 11348 + cur_off);
ba93b8ac 11349 outrel.r_info = ELF32_R_INFO (indx, R_ARM_TLS_DTPMOD32);
ba93b8ac 11350
00a97672
RS		 11351 if (globals->use_rel)
11352 bfd_put_32 (output_bfd, outrel.r_addend,
362d30a1 11353 sgot->contents + cur_off);
00a97672 11354
47beaa6a 11355 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
ba93b8ac
DJ		 11356
11357 if (indx == 0)
11358 bfd_put_32 (output_bfd, value - dtpoff_base (info),
362d30a1 11359 sgot->contents + cur_off + 4);
ba93b8ac
DJ		 11360 else
11361 {
00a97672 11362 outrel.r_addend = 0;
ba93b8ac
DJ		 11363 outrel.r_info = ELF32_R_INFO (indx,
11364 R_ARM_TLS_DTPOFF32);
11365 outrel.r_offset += 4;
00a97672
RS		 11366
11367 if (globals->use_rel)
11368 bfd_put_32 (output_bfd, outrel.r_addend,
362d30a1 11369 sgot->contents + cur_off + 4);
00a97672 11370
47beaa6a
RS		 11371 elf32_arm_add_dynreloc (output_bfd, info,
11372 srelgot, &outrel);
ba93b8ac
DJ		 11373 }
11374 }
11375 else
11376 {
11377 /* If we are not emitting relocations for a
11378 general dynamic reference, then we must be in a
11379 static link or an executable link with the
11380 symbol binding locally. Mark it as belonging
11381 to module 1, the executable. */
11382 bfd_put_32 (output_bfd, 1,
362d30a1 11383 sgot->contents + cur_off);
ba93b8ac 11384 bfd_put_32 (output_bfd, value - dtpoff_base (info),
362d30a1 11385 sgot->contents + cur_off + 4);
ba93b8ac
DJ		 11386 }
11387
11388 cur_off += 8;
11389 }
11390
11391 if (tls_type & GOT_TLS_IE)
11392 {
11393 if (need_relocs)
11394 {
00a97672
RS		 11395 if (indx == 0)
11396 outrel.r_addend = value - dtpoff_base (info);
11397 else
11398 outrel.r_addend = 0;
362d30a1
RS		 11399 outrel.r_offset = (sgot->output_section->vma
11400 + sgot->output_offset
ba93b8ac
DJ		 11401 + cur_off);
11402 outrel.r_info = ELF32_R_INFO (indx, R_ARM_TLS_TPOFF32);
11403
00a97672
RS		 11404 if (globals->use_rel)
11405 bfd_put_32 (output_bfd, outrel.r_addend,
362d30a1 11406 sgot->contents + cur_off);
ba93b8ac 11407
47beaa6a 11408 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
ba93b8ac
DJ		 11409 }
11410 else
11411 bfd_put_32 (output_bfd, tpoff (info, value),
362d30a1 11412 sgot->contents + cur_off);
ba93b8ac
DJ		 11413 cur_off += 4;
11414 }
11415
11416 if (h != NULL)
11417 h->got.offset |= 1;
11418 else
11419 local_got_offsets[r_symndx] |= 1;
11420 }
11421
11422 if ((tls_type & GOT_TLS_GD) && r_type != R_ARM_TLS_GD32)
11423 off += 8;
0855e32b
NS		 11424 else if (tls_type & GOT_TLS_GDESC)
11425 off = offplt;
11426
11427 if (ELF32_R_TYPE(rel->r_info) == R_ARM_TLS_CALL
11428 || ELF32_R_TYPE(rel->r_info) == R_ARM_THM_TLS_CALL)
11429 {
11430 bfd_signed_vma offset;
12352d3f
PB		 11431 /* TLS stubs are arm mode. The original symbol is a
11432 data object, so branch_type is bogus. */
11433 branch_type = ST_BRANCH_TO_ARM;
0855e32b 11434 enum elf32_arm_stub_type stub_type
34e77a92
RS		 11435 = arm_type_of_stub (info, input_section, rel,
11436 st_type, &branch_type,
0855e32b
NS		 11437 (struct elf32_arm_link_hash_entry *)h,
11438 globals->tls_trampoline, globals->root.splt,
11439 input_bfd, sym_name);
11440
11441 if (stub_type != arm_stub_none)
11442 {
11443 struct elf32_arm_stub_hash_entry *stub_entry
11444 = elf32_arm_get_stub_entry
11445 (input_section, globals->root.splt, 0, rel,
11446 globals, stub_type);
11447 offset = (stub_entry->stub_offset
11448 + stub_entry->stub_sec->output_offset
11449 + stub_entry->stub_sec->output_section->vma);
11450 }
11451 else
11452 offset = (globals->root.splt->output_section->vma
11453 + globals->root.splt->output_offset
11454 + globals->tls_trampoline);
11455
11456 if (ELF32_R_TYPE(rel->r_info) == R_ARM_TLS_CALL)
11457 {
11458 unsigned long inst;
b38cadfb
NC		 11459
11460 offset -= (input_section->output_section->vma
11461 + input_section->output_offset
11462 + rel->r_offset + 8);
0855e32b
NS		 11463
11464 inst = offset >> 2;
11465 inst &= 0x00ffffff;
11466 value = inst | (globals->use_blx ? 0xfa000000 : 0xeb000000);
11467 }
11468 else
11469 {
11470 /* Thumb blx encodes the offset in a complicated
11471 fashion. */
11472 unsigned upper_insn, lower_insn;
11473 unsigned neg;
11474
b38cadfb
NC		 11475 offset -= (input_section->output_section->vma
11476 + input_section->output_offset
0855e32b 11477 + rel->r_offset + 4);
b38cadfb 11478
12352d3f
PB		 11479 if (stub_type != arm_stub_none
11480 && arm_stub_is_thumb (stub_type))
11481 {
11482 lower_insn = 0xd000;
11483 }
11484 else
11485 {
11486 lower_insn = 0xc000;
6a631e86 11487 /* Round up the offset to a word boundary. */
12352d3f
PB		 11488 offset = (offset + 2) & ~2;
11489 }
11490
0855e32b
NS		 11491 neg = offset < 0;
11492 upper_insn = (0xf000
11493 | ((offset >> 12) & 0x3ff)
11494 | (neg << 10));
12352d3f 11495 lower_insn |= (((!((offset >> 23) & 1)) ^ neg) << 13)
0855e32b 11496 | (((!((offset >> 22) & 1)) ^ neg) << 11)
12352d3f 11497 | ((offset >> 1) & 0x7ff);
0855e32b
NS		 11498 bfd_put_16 (input_bfd, upper_insn, hit_data);
11499 bfd_put_16 (input_bfd, lower_insn, hit_data + 2);
11500 return bfd_reloc_ok;
11501 }
11502 }
11503 /* These relocations needs special care, as besides the fact
11504 they point somewhere in .gotplt, the addend must be
11505 adjusted accordingly depending on the type of instruction
6a631e86 11506 we refer to. */
0855e32b
NS		 11507 else if ((r_type == R_ARM_TLS_GOTDESC) && (tls_type & GOT_TLS_GDESC))
11508 {
11509 unsigned long data, insn;
11510 unsigned thumb;
b38cadfb 11511
0855e32b
NS		 11512 data = bfd_get_32 (input_bfd, hit_data);
11513 thumb = data & 1;
11514 data &= ~1u;
b38cadfb 11515
0855e32b
NS		 11516 if (thumb)
11517 {
11518 insn = bfd_get_16 (input_bfd, contents + rel->r_offset - data);
11519 if ((insn & 0xf000) == 0xf000 || (insn & 0xf800) == 0xe800)
11520 insn = (insn << 16)
11521 | bfd_get_16 (input_bfd,
11522 contents + rel->r_offset - data + 2);
11523 if ((insn & 0xf800c000) == 0xf000c000)
11524 /* bl/blx */
11525 value = -6;
11526 else if ((insn & 0xffffff00) == 0x4400)
11527 /* add */
11528 value = -5;
11529 else
11530 {
4eca0228 11531 _bfd_error_handler
695344c0
NC		 11532 /* xgettext:c-format */
11533 (_("%B(%A+0x%lx): unexpected Thumb instruction '0x%x' referenced by TLS_GOTDESC"),
0855e32b
NS		 11534 input_bfd, input_section,
11535 (unsigned long)rel->r_offset, insn);
11536 return bfd_reloc_notsupported;
11537 }
11538 }
11539 else
11540 {
11541 insn = bfd_get_32 (input_bfd, contents + rel->r_offset - data);
11542
11543 switch (insn >> 24)
11544 {
11545 case 0xeb: /* bl */
11546 case 0xfa: /* blx */
11547 value = -4;
11548 break;
11549
11550 case 0xe0: /* add */
11551 value = -8;
11552 break;
b38cadfb 11553
0855e32b 11554 default:
4eca0228 11555 _bfd_error_handler
695344c0
NC		 11556 /* xgettext:c-format */
11557 (_("%B(%A+0x%lx): unexpected ARM instruction '0x%x' referenced by TLS_GOTDESC"),
0855e32b
NS		 11558 input_bfd, input_section,
11559 (unsigned long)rel->r_offset, insn);
11560 return bfd_reloc_notsupported;
11561 }
11562 }
b38cadfb 11563
0855e32b
NS		 11564 value += ((globals->root.sgotplt->output_section->vma
11565 + globals->root.sgotplt->output_offset + off)
11566 - (input_section->output_section->vma
11567 + input_section->output_offset
11568 + rel->r_offset)
11569 + globals->sgotplt_jump_table_size);
11570 }
11571 else
11572 value = ((globals->root.sgot->output_section->vma
11573 + globals->root.sgot->output_offset + off)
11574 - (input_section->output_section->vma
11575 + input_section->output_offset + rel->r_offset));
ba93b8ac
DJ		 11576
11577 return _bfd_final_link_relocate (howto, input_bfd, input_section,
11578 contents, rel->r_offset, value,
00a97672 11579 rel->r_addend);
ba93b8ac
DJ		 11580 }
11581
11582 case R_ARM_TLS_LE32:
3cbc1e5e 11583 if (bfd_link_dll (info))
ba93b8ac 11584 {
4eca0228 11585 _bfd_error_handler
695344c0 11586 /* xgettext:c-format */
ba93b8ac
DJ		 11587 (_("%B(%A+0x%lx): R_ARM_TLS_LE32 relocation not permitted in shared object"),
11588 input_bfd, input_section,
11589 (long) rel->r_offset, howto->name);
46691134 11590 return bfd_reloc_notsupported;
ba93b8ac
DJ		 11591 }
11592 else
11593 value = tpoff (info, value);
906e58ca 11594
ba93b8ac 11595 return _bfd_final_link_relocate (howto, input_bfd, input_section,
00a97672
RS		 11596 contents, rel->r_offset, value,
11597 rel->r_addend);
ba93b8ac 11598
319850b4
JB		 11599 case R_ARM_V4BX:
11600 if (globals->fix_v4bx)
845b51d6
PB		 11601 {
11602 bfd_vma insn = bfd_get_32 (input_bfd, hit_data);
319850b4 11603
845b51d6
PB		 11604 /* Ensure that we have a BX instruction. */
11605 BFD_ASSERT ((insn & 0x0ffffff0) == 0x012fff10);
319850b4 11606
845b51d6
PB		 11607 if (globals->fix_v4bx == 2 && (insn & 0xf) != 0xf)
11608 {
11609 /* Branch to veneer. */
11610 bfd_vma glue_addr;
11611 glue_addr = elf32_arm_bx_glue (info, insn & 0xf);
11612 glue_addr -= input_section->output_section->vma
11613 + input_section->output_offset
11614 + rel->r_offset + 8;
11615 insn = (insn & 0xf0000000) | 0x0a000000
11616 | ((glue_addr >> 2) & 0x00ffffff);
11617 }
11618 else
11619 {
11620 /* Preserve Rm (lowest four bits) and the condition code
11621 (highest four bits). Other bits encode MOV PC,Rm. */
11622 insn = (insn & 0xf000000f) | 0x01a0f000;
11623 }
319850b4 11624
845b51d6
PB		 11625 bfd_put_32 (input_bfd, insn, hit_data);
11626 }
319850b4
JB		 11627 return bfd_reloc_ok;
11628
b6895b4f
PB		 11629 case R_ARM_MOVW_ABS_NC:
11630 case R_ARM_MOVT_ABS:
11631 case R_ARM_MOVW_PREL_NC:
11632 case R_ARM_MOVT_PREL:
92f5d02b
MS		 11633 /* Until we properly support segment-base-relative addressing then
11634 we assume the segment base to be zero, as for the group relocations.
11635 Thus R_ARM_MOVW_BREL_NC has the same semantics as R_ARM_MOVW_ABS_NC
11636 and R_ARM_MOVT_BREL has the same semantics as R_ARM_MOVT_ABS. */
11637 case R_ARM_MOVW_BREL_NC:
11638 case R_ARM_MOVW_BREL:
11639 case R_ARM_MOVT_BREL:
b6895b4f
PB		 11640 {
11641 bfd_vma insn = bfd_get_32 (input_bfd, hit_data);
11642
11643 if (globals->use_rel)
11644 {
11645 addend = ((insn >> 4) & 0xf000) | (insn & 0xfff);
39623e12 11646 signed_addend = (addend ^ 0x8000) - 0x8000;
b6895b4f 11647 }
92f5d02b 11648
b6895b4f 11649 value += signed_addend;
b6895b4f
PB		 11650
11651 if (r_type == R_ARM_MOVW_PREL_NC || r_type == R_ARM_MOVT_PREL)
11652 value -= (input_section->output_section->vma
11653 + input_section->output_offset + rel->r_offset);
11654
92f5d02b 11655 if (r_type == R_ARM_MOVW_BREL && value >= 0x10000)
99059e56 11656 return bfd_reloc_overflow;
92f5d02b 11657
35fc36a8 11658 if (branch_type == ST_BRANCH_TO_THUMB)
92f5d02b
MS		 11659 value |= 1;
11660
11661 if (r_type == R_ARM_MOVT_ABS || r_type == R_ARM_MOVT_PREL
99059e56 11662 || r_type == R_ARM_MOVT_BREL)
b6895b4f
PB		 11663 value >>= 16;
11664
11665 insn &= 0xfff0f000;
11666 insn |= value & 0xfff;
11667 insn |= (value & 0xf000) << 4;
11668 bfd_put_32 (input_bfd, insn, hit_data);
11669 }
11670 return bfd_reloc_ok;
11671
11672 case R_ARM_THM_MOVW_ABS_NC:
11673 case R_ARM_THM_MOVT_ABS:
11674 case R_ARM_THM_MOVW_PREL_NC:
11675 case R_ARM_THM_MOVT_PREL:
92f5d02b
MS		 11676 /* Until we properly support segment-base-relative addressing then
11677 we assume the segment base to be zero, as for the above relocations.
11678 Thus R_ARM_THM_MOVW_BREL_NC has the same semantics as
11679 R_ARM_THM_MOVW_ABS_NC and R_ARM_THM_MOVT_BREL has the same semantics
11680 as R_ARM_THM_MOVT_ABS. */
11681 case R_ARM_THM_MOVW_BREL_NC:
11682 case R_ARM_THM_MOVW_BREL:
11683 case R_ARM_THM_MOVT_BREL:
b6895b4f
PB		 11684 {
11685 bfd_vma insn;
906e58ca 11686
b6895b4f
PB		 11687 insn = bfd_get_16 (input_bfd, hit_data) << 16;
11688 insn |= bfd_get_16 (input_bfd, hit_data + 2);
11689
11690 if (globals->use_rel)
11691 {
11692 addend = ((insn >> 4) & 0xf000)
11693 | ((insn >> 15) & 0x0800)
11694 | ((insn >> 4) & 0x0700)
11695 | (insn & 0x00ff);
39623e12 11696 signed_addend = (addend ^ 0x8000) - 0x8000;
b6895b4f 11697 }
92f5d02b 11698
b6895b4f 11699 value += signed_addend;
b6895b4f
PB		 11700
11701 if (r_type == R_ARM_THM_MOVW_PREL_NC || r_type == R_ARM_THM_MOVT_PREL)
11702 value -= (input_section->output_section->vma
11703 + input_section->output_offset + rel->r_offset);
11704
92f5d02b 11705 if (r_type == R_ARM_THM_MOVW_BREL && value >= 0x10000)
99059e56 11706 return bfd_reloc_overflow;
92f5d02b 11707
35fc36a8 11708 if (branch_type == ST_BRANCH_TO_THUMB)
92f5d02b
MS		 11709 value |= 1;
11710
11711 if (r_type == R_ARM_THM_MOVT_ABS || r_type == R_ARM_THM_MOVT_PREL
99059e56 11712 || r_type == R_ARM_THM_MOVT_BREL)
b6895b4f
PB		 11713 value >>= 16;
11714
11715 insn &= 0xfbf08f00;
11716 insn |= (value & 0xf000) << 4;
11717 insn |= (value & 0x0800) << 15;
11718 insn |= (value & 0x0700) << 4;
11719 insn |= (value & 0x00ff);
11720
11721 bfd_put_16 (input_bfd, insn >> 16, hit_data);
11722 bfd_put_16 (input_bfd, insn & 0xffff, hit_data + 2);
11723 }
11724 return bfd_reloc_ok;
11725
4962c51a
MS		 11726 case R_ARM_ALU_PC_G0_NC:
11727 case R_ARM_ALU_PC_G1_NC:
11728 case R_ARM_ALU_PC_G0:
11729 case R_ARM_ALU_PC_G1:
11730 case R_ARM_ALU_PC_G2:
11731 case R_ARM_ALU_SB_G0_NC:
11732 case R_ARM_ALU_SB_G1_NC:
11733 case R_ARM_ALU_SB_G0:
11734 case R_ARM_ALU_SB_G1:
11735 case R_ARM_ALU_SB_G2:
11736 {
11737 bfd_vma insn = bfd_get_32 (input_bfd, hit_data);
99059e56 11738 bfd_vma pc = input_section->output_section->vma
4962c51a 11739 + input_section->output_offset + rel->r_offset;
31a91d61 11740 /* sb is the origin of the *segment* containing the symbol. */
62c34db3 11741 bfd_vma sb = sym_sec ? sym_sec->output_section->vma : 0;
99059e56
RM		 11742 bfd_vma residual;
11743 bfd_vma g_n;
4962c51a 11744 bfd_signed_vma signed_value;
99059e56
RM		 11745 int group = 0;
11746
11747 /* Determine which group of bits to select. */
11748 switch (r_type)
11749 {
11750 case R_ARM_ALU_PC_G0_NC:
11751 case R_ARM_ALU_PC_G0:
11752 case R_ARM_ALU_SB_G0_NC:
11753 case R_ARM_ALU_SB_G0:
11754 group = 0;
11755 break;
11756
11757 case R_ARM_ALU_PC_G1_NC:
11758 case R_ARM_ALU_PC_G1:
11759 case R_ARM_ALU_SB_G1_NC:
11760 case R_ARM_ALU_SB_G1:
11761 group = 1;
11762 break;
11763
11764 case R_ARM_ALU_PC_G2:
11765 case R_ARM_ALU_SB_G2:
11766 group = 2;
11767 break;
11768
11769 default:
11770 abort ();
11771 }
11772
11773 /* If REL, extract the addend from the insn. If RELA, it will
11774 have already been fetched for us. */
4962c51a 11775 if (globals->use_rel)
99059e56
RM		 11776 {
11777 int negative;
11778 bfd_vma constant = insn & 0xff;
11779 bfd_vma rotation = (insn & 0xf00) >> 8;
11780
11781 if (rotation == 0)
11782 signed_addend = constant;
11783 else
11784 {
11785 /* Compensate for the fact that in the instruction, the
11786 rotation is stored in multiples of 2 bits. */
11787 rotation *= 2;
11788
11789 /* Rotate "constant" right by "rotation" bits. */
11790 signed_addend = (constant >> rotation) |
11791 (constant << (8 * sizeof (bfd_vma) - rotation));
11792 }
11793
11794 /* Determine if the instruction is an ADD or a SUB.
11795 (For REL, this determines the sign of the addend.) */
11796 negative = identify_add_or_sub (insn);
11797 if (negative == 0)
11798 {
4eca0228 11799 _bfd_error_handler
695344c0 11800 /* xgettext:c-format */
99059e56
RM		 11801 (_("%B(%A+0x%lx): Only ADD or SUB instructions are allowed for ALU group relocations"),
11802 input_bfd, input_section,
11803 (long) rel->r_offset, howto->name);
11804 return bfd_reloc_overflow;
11805 }
11806
11807 signed_addend *= negative;
11808 }
4962c51a
MS		 11809
11810 /* Compute the value (X) to go in the place. */
99059e56
RM		 11811 if (r_type == R_ARM_ALU_PC_G0_NC
11812 || r_type == R_ARM_ALU_PC_G1_NC
11813 || r_type == R_ARM_ALU_PC_G0
11814 || r_type == R_ARM_ALU_PC_G1
11815 || r_type == R_ARM_ALU_PC_G2)
11816 /* PC relative. */
11817 signed_value = value - pc + signed_addend;
11818 else
11819 /* Section base relative. */
11820 signed_value = value - sb + signed_addend;
11821
11822 /* If the target symbol is a Thumb function, then set the
11823 Thumb bit in the address. */
35fc36a8 11824 if (branch_type == ST_BRANCH_TO_THUMB)
4962c51a
MS		 11825 signed_value |= 1;
11826
99059e56
RM		 11827 /* Calculate the value of the relevant G_n, in encoded
11828 constant-with-rotation format. */
b6518b38
NC		 11829 g_n = calculate_group_reloc_mask (signed_value < 0 ? - signed_value : signed_value,
11830 group, &residual);
99059e56
RM		 11831
11832 /* Check for overflow if required. */
11833 if ((r_type == R_ARM_ALU_PC_G0
11834 || r_type == R_ARM_ALU_PC_G1
11835 || r_type == R_ARM_ALU_PC_G2
11836 || r_type == R_ARM_ALU_SB_G0
11837 || r_type == R_ARM_ALU_SB_G1
11838 || r_type == R_ARM_ALU_SB_G2) && residual != 0)
11839 {
4eca0228 11840 _bfd_error_handler
695344c0 11841 /* xgettext:c-format */
99059e56
RM		 11842 (_("%B(%A+0x%lx): Overflow whilst splitting 0x%lx for group relocation %s"),
11843 input_bfd, input_section,
b6518b38
NC		 11844 (long) rel->r_offset, signed_value < 0 ? - signed_value : signed_value,
11845 howto->name);
99059e56
RM		 11846 return bfd_reloc_overflow;
11847 }
11848
11849 /* Mask out the value and the ADD/SUB part of the opcode; take care
11850 not to destroy the S bit. */
11851 insn &= 0xff1ff000;
11852
11853 /* Set the opcode according to whether the value to go in the
11854 place is negative. */
11855 if (signed_value < 0)
11856 insn |= 1 << 22;
11857 else
11858 insn |= 1 << 23;
11859
11860 /* Encode the offset. */
11861 insn |= g_n;
4962c51a
MS		 11862
11863 bfd_put_32 (input_bfd, insn, hit_data);
11864 }
11865 return bfd_reloc_ok;
11866
11867 case R_ARM_LDR_PC_G0:
11868 case R_ARM_LDR_PC_G1:
11869 case R_ARM_LDR_PC_G2:
11870 case R_ARM_LDR_SB_G0:
11871 case R_ARM_LDR_SB_G1:
11872 case R_ARM_LDR_SB_G2:
11873 {
11874 bfd_vma insn = bfd_get_32 (input_bfd, hit_data);
99059e56 11875 bfd_vma pc = input_section->output_section->vma
4962c51a 11876 + input_section->output_offset + rel->r_offset;
31a91d61 11877 /* sb is the origin of the *segment* containing the symbol. */
62c34db3 11878 bfd_vma sb = sym_sec ? sym_sec->output_section->vma : 0;
99059e56 11879 bfd_vma residual;
4962c51a 11880 bfd_signed_vma signed_value;
99059e56
RM		 11881 int group = 0;
11882
11883 /* Determine which groups of bits to calculate. */
11884 switch (r_type)
11885 {
11886 case R_ARM_LDR_PC_G0:
11887 case R_ARM_LDR_SB_G0:
11888 group = 0;
11889 break;
11890
11891 case R_ARM_LDR_PC_G1:
11892 case R_ARM_LDR_SB_G1:
11893 group = 1;
11894 break;
11895
11896 case R_ARM_LDR_PC_G2:
11897 case R_ARM_LDR_SB_G2:
11898 group = 2;
11899 break;
11900
11901 default:
11902 abort ();
11903 }
11904
11905 /* If REL, extract the addend from the insn. If RELA, it will
11906 have already been fetched for us. */
4962c51a 11907 if (globals->use_rel)
99059e56
RM		 11908 {
11909 int negative = (insn & (1 << 23)) ? 1 : -1;
11910 signed_addend = negative * (insn & 0xfff);
11911 }
4962c51a
MS		 11912
11913 /* Compute the value (X) to go in the place. */
99059e56
RM		 11914 if (r_type == R_ARM_LDR_PC_G0
11915 || r_type == R_ARM_LDR_PC_G1
11916 || r_type == R_ARM_LDR_PC_G2)
11917 /* PC relative. */
11918 signed_value = value - pc + signed_addend;
11919 else
11920 /* Section base relative. */
11921 signed_value = value - sb + signed_addend;
11922
11923 /* Calculate the value of the relevant G_{n-1} to obtain
11924 the residual at that stage. */
b6518b38
NC		 11925 calculate_group_reloc_mask (signed_value < 0 ? - signed_value : signed_value,
11926 group - 1, &residual);
99059e56
RM		 11927
11928 /* Check for overflow. */
11929 if (residual >= 0x1000)
11930 {
4eca0228 11931 _bfd_error_handler
695344c0 11932 /* xgettext:c-format */
99059e56 11933 (_("%B(%A+0x%lx): Overflow whilst splitting 0x%lx for group relocation %s"),
b6518b38
NC		 11934 input_bfd, input_section,
11935 (long) rel->r_offset, labs (signed_value), howto->name);
99059e56
RM		 11936 return bfd_reloc_overflow;
11937 }
11938
11939 /* Mask out the value and U bit. */
11940 insn &= 0xff7ff000;
11941
11942 /* Set the U bit if the value to go in the place is non-negative. */
11943 if (signed_value >= 0)
11944 insn |= 1 << 23;
11945
11946 /* Encode the offset. */
11947 insn |= residual;
4962c51a
MS		 11948
11949 bfd_put_32 (input_bfd, insn, hit_data);
11950 }
11951 return bfd_reloc_ok;
11952
11953 case R_ARM_LDRS_PC_G0:
11954 case R_ARM_LDRS_PC_G1:
11955 case R_ARM_LDRS_PC_G2:
11956 case R_ARM_LDRS_SB_G0:
11957 case R_ARM_LDRS_SB_G1:
11958 case R_ARM_LDRS_SB_G2:
11959 {
11960 bfd_vma insn = bfd_get_32 (input_bfd, hit_data);
99059e56 11961 bfd_vma pc = input_section->output_section->vma
4962c51a 11962 + input_section->output_offset + rel->r_offset;
31a91d61 11963 /* sb is the origin of the *segment* containing the symbol. */
62c34db3 11964 bfd_vma sb = sym_sec ? sym_sec->output_section->vma : 0;
99059e56 11965 bfd_vma residual;
4962c51a 11966 bfd_signed_vma signed_value;
99059e56
RM		 11967 int group = 0;
11968
11969 /* Determine which groups of bits to calculate. */
11970 switch (r_type)
11971 {
11972 case R_ARM_LDRS_PC_G0:
11973 case R_ARM_LDRS_SB_G0:
11974 group = 0;
11975 break;
11976
11977 case R_ARM_LDRS_PC_G1:
11978 case R_ARM_LDRS_SB_G1:
11979 group = 1;
11980 break;
11981
11982 case R_ARM_LDRS_PC_G2:
11983 case R_ARM_LDRS_SB_G2:
11984 group = 2;
11985 break;
11986
11987 default:
11988 abort ();
11989 }
11990
11991 /* If REL, extract the addend from the insn. If RELA, it will
11992 have already been fetched for us. */
4962c51a 11993 if (globals->use_rel)
99059e56
RM		 11994 {
11995 int negative = (insn & (1 << 23)) ? 1 : -1;
11996 signed_addend = negative * (((insn & 0xf00) >> 4) + (insn & 0xf));
11997 }
4962c51a
MS		 11998
11999 /* Compute the value (X) to go in the place. */
99059e56
RM		 12000 if (r_type == R_ARM_LDRS_PC_G0
12001 || r_type == R_ARM_LDRS_PC_G1
12002 || r_type == R_ARM_LDRS_PC_G2)
12003 /* PC relative. */
12004 signed_value = value - pc + signed_addend;
12005 else
12006 /* Section base relative. */
12007 signed_value = value - sb + signed_addend;
12008
12009 /* Calculate the value of the relevant G_{n-1} to obtain
12010 the residual at that stage. */
b6518b38
NC		 12011 calculate_group_reloc_mask (signed_value < 0 ? - signed_value : signed_value,
12012 group - 1, &residual);
99059e56
RM		 12013
12014 /* Check for overflow. */
12015 if (residual >= 0x100)
12016 {
4eca0228 12017 _bfd_error_handler
695344c0 12018 /* xgettext:c-format */
99059e56 12019 (_("%B(%A+0x%lx): Overflow whilst splitting 0x%lx for group relocation %s"),
b6518b38
NC		 12020 input_bfd, input_section,
12021 (long) rel->r_offset, labs (signed_value), howto->name);
99059e56
RM		 12022 return bfd_reloc_overflow;
12023 }
12024
12025 /* Mask out the value and U bit. */
12026 insn &= 0xff7ff0f0;
12027
12028 /* Set the U bit if the value to go in the place is non-negative. */
12029 if (signed_value >= 0)
12030 insn |= 1 << 23;
12031
12032 /* Encode the offset. */
12033 insn |= ((residual & 0xf0) << 4) | (residual & 0xf);
4962c51a
MS		 12034
12035 bfd_put_32 (input_bfd, insn, hit_data);
12036 }
12037 return bfd_reloc_ok;
12038
12039 case R_ARM_LDC_PC_G0:
12040 case R_ARM_LDC_PC_G1:
12041 case R_ARM_LDC_PC_G2:
12042 case R_ARM_LDC_SB_G0:
12043 case R_ARM_LDC_SB_G1:
12044 case R_ARM_LDC_SB_G2:
12045 {
12046 bfd_vma insn = bfd_get_32 (input_bfd, hit_data);
99059e56 12047 bfd_vma pc = input_section->output_section->vma
4962c51a 12048 + input_section->output_offset + rel->r_offset;
31a91d61 12049 /* sb is the origin of the *segment* containing the symbol. */
62c34db3 12050 bfd_vma sb = sym_sec ? sym_sec->output_section->vma : 0;
99059e56 12051 bfd_vma residual;
4962c51a 12052 bfd_signed_vma signed_value;
99059e56
RM		 12053 int group = 0;
12054
12055 /* Determine which groups of bits to calculate. */
12056 switch (r_type)
12057 {
12058 case R_ARM_LDC_PC_G0:
12059 case R_ARM_LDC_SB_G0:
12060 group = 0;
12061 break;
12062
12063 case R_ARM_LDC_PC_G1:
12064 case R_ARM_LDC_SB_G1:
12065 group = 1;
12066 break;
12067
12068 case R_ARM_LDC_PC_G2:
12069 case R_ARM_LDC_SB_G2:
12070 group = 2;
12071 break;
12072
12073 default:
12074 abort ();
12075 }
12076
12077 /* If REL, extract the addend from the insn. If RELA, it will
12078 have already been fetched for us. */
4962c51a 12079 if (globals->use_rel)
99059e56
RM		 12080 {
12081 int negative = (insn & (1 << 23)) ? 1 : -1;
12082 signed_addend = negative * ((insn & 0xff) << 2);
12083 }
4962c51a
MS		 12084
12085 /* Compute the value (X) to go in the place. */
99059e56
RM		 12086 if (r_type == R_ARM_LDC_PC_G0
12087 || r_type == R_ARM_LDC_PC_G1
12088 || r_type == R_ARM_LDC_PC_G2)
12089 /* PC relative. */
12090 signed_value = value - pc + signed_addend;
12091 else
12092 /* Section base relative. */
12093 signed_value = value - sb + signed_addend;
12094
12095 /* Calculate the value of the relevant G_{n-1} to obtain
12096 the residual at that stage. */
b6518b38
NC		 12097 calculate_group_reloc_mask (signed_value < 0 ? - signed_value : signed_value,
12098 group - 1, &residual);
99059e56
RM		 12099
12100 /* Check for overflow. (The absolute value to go in the place must be
12101 divisible by four and, after having been divided by four, must
12102 fit in eight bits.) */
12103 if ((residual & 0x3) != 0 || residual >= 0x400)
12104 {
4eca0228 12105 _bfd_error_handler
695344c0 12106 /* xgettext:c-format */
99059e56
RM		 12107 (_("%B(%A+0x%lx): Overflow whilst splitting 0x%lx for group relocation %s"),
12108 input_bfd, input_section,
b6518b38 12109 (long) rel->r_offset, labs (signed_value), howto->name);
99059e56
RM		 12110 return bfd_reloc_overflow;
12111 }
12112
12113 /* Mask out the value and U bit. */
12114 insn &= 0xff7fff00;
12115
12116 /* Set the U bit if the value to go in the place is non-negative. */
12117 if (signed_value >= 0)
12118 insn |= 1 << 23;
12119
12120 /* Encode the offset. */
12121 insn |= residual >> 2;
4962c51a
MS		 12122
12123 bfd_put_32 (input_bfd, insn, hit_data);
12124 }
12125 return bfd_reloc_ok;
12126
72d98d16
MG		 12127 case R_ARM_THM_ALU_ABS_G0_NC:
12128 case R_ARM_THM_ALU_ABS_G1_NC:
12129 case R_ARM_THM_ALU_ABS_G2_NC:
12130 case R_ARM_THM_ALU_ABS_G3_NC:
12131 {
12132 const int shift_array[4] = {0, 8, 16, 24};
12133 bfd_vma insn = bfd_get_16 (input_bfd, hit_data);
12134 bfd_vma addr = value;
12135 int shift = shift_array[r_type - R_ARM_THM_ALU_ABS_G0_NC];
12136
12137 /* Compute address. */
12138 if (globals->use_rel)
12139 signed_addend = insn & 0xff;
12140 addr += signed_addend;
12141 if (branch_type == ST_BRANCH_TO_THUMB)
12142 addr |= 1;
12143 /* Clean imm8 insn. */
12144 insn &= 0xff00;
12145 /* And update with correct part of address. */
12146 insn |= (addr >> shift) & 0xff;
12147 /* Update insn. */
12148 bfd_put_16 (input_bfd, insn, hit_data);
12149 }
12150
12151 *unresolved_reloc_p = FALSE;
12152 return bfd_reloc_ok;
12153
252b5132
RH		 12154 default:
12155 return bfd_reloc_notsupported;
12156 }
12157}
12158
98c1d4aa
NC		 12159/* Add INCREMENT to the reloc (of type HOWTO) at ADDRESS. */
12160static void
57e8b36a
NC		 12161arm_add_to_rel (bfd * abfd,
12162 bfd_byte * address,
12163 reloc_howto_type * howto,
12164 bfd_signed_vma increment)
98c1d4aa 12165{
98c1d4aa
NC		 12166 bfd_signed_vma addend;
12167
bd97cb95
DJ		 12168 if (howto->type == R_ARM_THM_CALL
12169 || howto->type == R_ARM_THM_JUMP24)
98c1d4aa 12170 {
9a5aca8c
AM		 12171 int upper_insn, lower_insn;
12172 int upper, lower;
98c1d4aa 12173
9a5aca8c
AM		 12174 upper_insn = bfd_get_16 (abfd, address);
12175 lower_insn = bfd_get_16 (abfd, address + 2);
12176 upper = upper_insn & 0x7ff;
12177 lower = lower_insn & 0x7ff;
12178
12179 addend = (upper << 12) | (lower << 1);
ddda4409 12180 addend += increment;
9a5aca8c 12181 addend >>= 1;
98c1d4aa 12182
9a5aca8c
AM		 12183 upper_insn = (upper_insn & 0xf800) | ((addend >> 11) & 0x7ff);
12184 lower_insn = (lower_insn & 0xf800) | (addend & 0x7ff);
12185
dc810e39
AM		 12186 bfd_put_16 (abfd, (bfd_vma) upper_insn, address);
12187 bfd_put_16 (abfd, (bfd_vma) lower_insn, address + 2);
9a5aca8c
AM		 12188 }
12189 else
12190 {
12191 bfd_vma contents;
12192
12193 contents = bfd_get_32 (abfd, address);
12194
12195 /* Get the (signed) value from the instruction. */
12196 addend = contents & howto->src_mask;
12197 if (addend & ((howto->src_mask + 1) >> 1))
12198 {
12199 bfd_signed_vma mask;
12200
12201 mask = -1;
12202 mask &= ~ howto->src_mask;
12203 addend |= mask;
12204 }
12205
12206 /* Add in the increment, (which is a byte value). */
12207 switch (howto->type)
12208 {
12209 default:
12210 addend += increment;
12211 break;
12212
12213 case R_ARM_PC24:
c6596c5e 12214 case R_ARM_PLT32:
5b5bb741
PB		 12215 case R_ARM_CALL:
12216 case R_ARM_JUMP24:
9a5aca8c 12217 addend <<= howto->size;
dc810e39 12218 addend += increment;
9a5aca8c
AM		 12219
12220 /* Should we check for overflow here ? */
12221
12222 /* Drop any undesired bits. */
12223 addend >>= howto->rightshift;
12224 break;
12225 }
12226
12227 contents = (contents & ~ howto->dst_mask) | (addend & howto->dst_mask);
12228
12229 bfd_put_32 (abfd, contents, address);
ddda4409 12230 }
98c1d4aa 12231}
252b5132 12232
ba93b8ac
DJ		 12233#define IS_ARM_TLS_RELOC(R_TYPE) \
12234 ((R_TYPE) == R_ARM_TLS_GD32 \
12235 || (R_TYPE) == R_ARM_TLS_LDO32 \
12236 || (R_TYPE) == R_ARM_TLS_LDM32 \
12237 || (R_TYPE) == R_ARM_TLS_DTPOFF32 \
12238 || (R_TYPE) == R_ARM_TLS_DTPMOD32 \
12239 || (R_TYPE) == R_ARM_TLS_TPOFF32 \
12240 || (R_TYPE) == R_ARM_TLS_LE32 \
0855e32b
NS		 12241 || (R_TYPE) == R_ARM_TLS_IE32 \
12242 || IS_ARM_TLS_GNU_RELOC (R_TYPE))
12243
12244/* Specific set of relocations for the gnu tls dialect. */
12245#define IS_ARM_TLS_GNU_RELOC(R_TYPE) \
12246 ((R_TYPE) == R_ARM_TLS_GOTDESC \
12247 || (R_TYPE) == R_ARM_TLS_CALL \
12248 || (R_TYPE) == R_ARM_THM_TLS_CALL \
12249 || (R_TYPE) == R_ARM_TLS_DESCSEQ \
12250 || (R_TYPE) == R_ARM_THM_TLS_DESCSEQ)
ba93b8ac 12251
252b5132 12252/* Relocate an ARM ELF section. */
906e58ca 12253
b34976b6 12254static bfd_boolean
57e8b36a
NC		 12255elf32_arm_relocate_section (bfd * output_bfd,
12256 struct bfd_link_info * info,
12257 bfd * input_bfd,
12258 asection * input_section,
12259 bfd_byte * contents,
12260 Elf_Internal_Rela * relocs,
12261 Elf_Internal_Sym * local_syms,
12262 asection ** local_sections)
252b5132 12263{
b34976b6
AM		 12264 Elf_Internal_Shdr *symtab_hdr;
12265 struct elf_link_hash_entry **sym_hashes;
12266 Elf_Internal_Rela *rel;
12267 Elf_Internal_Rela *relend;
12268 const char *name;
b32d3aa2 12269 struct elf32_arm_link_hash_table * globals;
252b5132 12270
4e7fd91e 12271 globals = elf32_arm_hash_table (info);
4dfe6ac6
NC		 12272 if (globals == NULL)
12273 return FALSE;
b491616a 12274
0ffa91dd 12275 symtab_hdr = & elf_symtab_hdr (input_bfd);
252b5132
RH		 12276 sym_hashes = elf_sym_hashes (input_bfd);
12277
12278 rel = relocs;
12279 relend = relocs + input_section->reloc_count;
12280 for (; rel < relend; rel++)
12281 {
ba96a88f
NC		 12282 int r_type;
12283 reloc_howto_type * howto;
12284 unsigned long r_symndx;
12285 Elf_Internal_Sym * sym;
12286 asection * sec;
252b5132 12287 struct elf_link_hash_entry * h;
ba96a88f
NC		 12288 bfd_vma relocation;
12289 bfd_reloc_status_type r;
12290 arelent bfd_reloc;
ba93b8ac 12291 char sym_type;
0945cdfd 12292 bfd_boolean unresolved_reloc = FALSE;
f2a9dd69 12293 char *error_message = NULL;
f21f3fe0 12294
252b5132 12295 r_symndx = ELF32_R_SYM (rel->r_info);
ba96a88f 12296 r_type = ELF32_R_TYPE (rel->r_info);
b32d3aa2 12297 r_type = arm_real_reloc_type (globals, r_type);
252b5132 12298
ba96a88f 12299 if ( r_type == R_ARM_GNU_VTENTRY
99059e56
RM		 12300 || r_type == R_ARM_GNU_VTINHERIT)
12301 continue;
252b5132 12302
b32d3aa2 12303 bfd_reloc.howto = elf32_arm_howto_from_type (r_type);
ba96a88f 12304 howto = bfd_reloc.howto;
252b5132 12305
252b5132
RH		 12306 h = NULL;
12307 sym = NULL;
12308 sec = NULL;
9b485d32 12309
252b5132
RH		 12310 if (r_symndx < symtab_hdr->sh_info)
12311 {
12312 sym = local_syms + r_symndx;
ba93b8ac 12313 sym_type = ELF32_ST_TYPE (sym->st_info);
252b5132 12314 sec = local_sections[r_symndx];
ffcb4889
NS		 12315
12316 /* An object file might have a reference to a local
12317 undefined symbol. This is a daft object file, but we
12318 should at least do something about it. V4BX & NONE
12319 relocations do not use the symbol and are explicitly
77b4f08f
TS		 12320 allowed to use the undefined symbol, so allow those.
12321 Likewise for relocations against STN_UNDEF. */
ffcb4889
NS		 12322 if (r_type != R_ARM_V4BX
12323 && r_type != R_ARM_NONE
77b4f08f 12324 && r_symndx != STN_UNDEF
ffcb4889
NS		 12325 && bfd_is_und_section (sec)
12326 && ELF_ST_BIND (sym->st_info) != STB_WEAK)
1a72702b
AM		 12327 (*info->callbacks->undefined_symbol)
12328 (info, bfd_elf_string_from_elf_section
12329 (input_bfd, symtab_hdr->sh_link, sym->st_name),
12330 input_bfd, input_section,
12331 rel->r_offset, TRUE);
b38cadfb 12332
4e7fd91e 12333 if (globals->use_rel)
f8df10f4 12334 {
4e7fd91e
PB		 12335 relocation = (sec->output_section->vma
12336 + sec->output_offset
12337 + sym->st_value);
0e1862bb 12338 if (!bfd_link_relocatable (info)
ab96bf03
AM		 12339 && (sec->flags & SEC_MERGE)
12340 && ELF_ST_TYPE (sym->st_info) == STT_SECTION)
f8df10f4 12341 {
4e7fd91e
PB		 12342 asection *msec;
12343 bfd_vma addend, value;
12344
39623e12 12345 switch (r_type)
4e7fd91e 12346 {
39623e12
PB		 12347 case R_ARM_MOVW_ABS_NC:
12348 case R_ARM_MOVT_ABS:
12349 value = bfd_get_32 (input_bfd, contents + rel->r_offset);
12350 addend = ((value & 0xf0000) >> 4) | (value & 0xfff);
12351 addend = (addend ^ 0x8000) - 0x8000;
12352 break;
f8df10f4 12353
39623e12
PB		 12354 case R_ARM_THM_MOVW_ABS_NC:
12355 case R_ARM_THM_MOVT_ABS:
12356 value = bfd_get_16 (input_bfd, contents + rel->r_offset)
12357 << 16;
12358 value |= bfd_get_16 (input_bfd,
12359 contents + rel->r_offset + 2);
12360 addend = ((value & 0xf7000) >> 4) | (value & 0xff)
12361 | ((value & 0x04000000) >> 15);
12362 addend = (addend ^ 0x8000) - 0x8000;
12363 break;
f8df10f4 12364
39623e12
PB		 12365 default:
12366 if (howto->rightshift
12367 || (howto->src_mask & (howto->src_mask + 1)))
12368 {
4eca0228 12369 _bfd_error_handler
695344c0 12370 /* xgettext:c-format */
39623e12
PB		 12371 (_("%B(%A+0x%lx): %s relocation against SEC_MERGE section"),
12372 input_bfd, input_section,
12373 (long) rel->r_offset, howto->name);
12374 return FALSE;
12375 }
12376
12377 value = bfd_get_32 (input_bfd, contents + rel->r_offset);
12378
12379 /* Get the (signed) value from the instruction. */
12380 addend = value & howto->src_mask;
12381 if (addend & ((howto->src_mask + 1) >> 1))
12382 {
12383 bfd_signed_vma mask;
12384
12385 mask = -1;
12386 mask &= ~ howto->src_mask;
12387 addend |= mask;
12388 }
12389 break;
4e7fd91e 12390 }
39623e12 12391
4e7fd91e
PB		 12392 msec = sec;
12393 addend =
12394 _bfd_elf_rel_local_sym (output_bfd, sym, &msec, addend)
12395 - relocation;
12396 addend += msec->output_section->vma + msec->output_offset;
39623e12 12397
cc643b88 12398 /* Cases here must match those in the preceding
39623e12
PB		 12399 switch statement. */
12400 switch (r_type)
12401 {
12402 case R_ARM_MOVW_ABS_NC:
12403 case R_ARM_MOVT_ABS:
12404 value = (value & 0xfff0f000) | ((addend & 0xf000) << 4)
12405 | (addend & 0xfff);
12406 bfd_put_32 (input_bfd, value, contents + rel->r_offset);
12407 break;
12408
12409 case R_ARM_THM_MOVW_ABS_NC:
12410 case R_ARM_THM_MOVT_ABS:
12411 value = (value & 0xfbf08f00) | ((addend & 0xf700) << 4)
12412 | (addend & 0xff) | ((addend & 0x0800) << 15);
12413 bfd_put_16 (input_bfd, value >> 16,
12414 contents + rel->r_offset);
12415 bfd_put_16 (input_bfd, value,
12416 contents + rel->r_offset + 2);
12417 break;
12418
12419 default:
12420 value = (value & ~ howto->dst_mask)
12421 | (addend & howto->dst_mask);
12422 bfd_put_32 (input_bfd, value, contents + rel->r_offset);
12423 break;
12424 }
f8df10f4 12425 }
f8df10f4 12426 }
4e7fd91e
PB		 12427 else
12428 relocation = _bfd_elf_rela_local_sym (output_bfd, sym, &sec, rel);
252b5132
RH		 12429 }
12430 else
12431 {
62d887d4 12432 bfd_boolean warned, ignored;
560e09e9 12433
b2a8e766
AM		 12434 RELOC_FOR_GLOBAL_SYMBOL (info, input_bfd, input_section, rel,
12435 r_symndx, symtab_hdr, sym_hashes,
12436 h, sec, relocation,
62d887d4 12437 unresolved_reloc, warned, ignored);
ba93b8ac
DJ		 12438
12439 sym_type = h->type;
252b5132
RH		 12440 }
12441
dbaa2011 12442 if (sec != NULL && discarded_section (sec))
e4067dbb 12443 RELOC_AGAINST_DISCARDED_SECTION (info, input_bfd, input_section,
545fd46b 12444 rel, 1, relend, howto, 0, contents);
ab96bf03 12445
0e1862bb 12446 if (bfd_link_relocatable (info))
ab96bf03
AM		 12447 {
12448 /* This is a relocatable link. We don't have to change
12449 anything, unless the reloc is against a section symbol,
12450 in which case we have to adjust according to where the
12451 section symbol winds up in the output section. */
12452 if (sym != NULL && ELF_ST_TYPE (sym->st_info) == STT_SECTION)
12453 {
12454 if (globals->use_rel)
12455 arm_add_to_rel (input_bfd, contents + rel->r_offset,
12456 howto, (bfd_signed_vma) sec->output_offset);
12457 else
12458 rel->r_addend += sec->output_offset;
12459 }
12460 continue;
12461 }
12462
252b5132
RH		 12463 if (h != NULL)
12464 name = h->root.root.string;
12465 else
12466 {
12467 name = (bfd_elf_string_from_elf_section
12468 (input_bfd, symtab_hdr->sh_link, sym->st_name));
12469 if (name == NULL || *name == '\0')
12470 name = bfd_section_name (input_bfd, sec);
12471 }
f21f3fe0 12472
cf35638d 12473 if (r_symndx != STN_UNDEF
ba93b8ac
DJ		 12474 && r_type != R_ARM_NONE
12475 && (h == NULL
12476 || h->root.type == bfd_link_hash_defined
12477 || h->root.type == bfd_link_hash_defweak)
12478 && IS_ARM_TLS_RELOC (r_type) != (sym_type == STT_TLS))
12479 {
4eca0228 12480 _bfd_error_handler
ba93b8ac 12481 ((sym_type == STT_TLS
695344c0 12482 /* xgettext:c-format */
ba93b8ac 12483 ? _("%B(%A+0x%lx): %s used with TLS symbol %s")
695344c0 12484 /* xgettext:c-format */
ba93b8ac
DJ		 12485 : _("%B(%A+0x%lx): %s used with non-TLS symbol %s")),
12486 input_bfd,
12487 input_section,
12488 (long) rel->r_offset,
12489 howto->name,
12490 name);
12491 }
12492
0855e32b 12493 /* We call elf32_arm_final_link_relocate unless we're completely
99059e56
RM		 12494 done, i.e., the relaxation produced the final output we want,
12495 and we won't let anybody mess with it. Also, we have to do
12496 addend adjustments in case of a R_ARM_TLS_GOTDESC relocation
6a631e86 12497 both in relaxed and non-relaxed cases. */
39d911fc
TP		 12498 if ((elf32_arm_tls_transition (info, r_type, h) != (unsigned)r_type)
12499 || (IS_ARM_TLS_GNU_RELOC (r_type)
12500 && !((h ? elf32_arm_hash_entry (h)->tls_type :
12501 elf32_arm_local_got_tls_type (input_bfd)[r_symndx])
12502 & GOT_TLS_GDESC)))
12503 {
12504 r = elf32_arm_tls_relax (globals, input_bfd, input_section,
12505 contents, rel, h == NULL);
12506 /* This may have been marked unresolved because it came from
12507 a shared library. But we've just dealt with that. */
12508 unresolved_reloc = 0;
12509 }
12510 else
12511 r = bfd_reloc_continue;
b38cadfb 12512
39d911fc
TP		 12513 if (r == bfd_reloc_continue)
12514 {
12515 unsigned char branch_type =
12516 h ? ARM_GET_SYM_BRANCH_TYPE (h->target_internal)
12517 : ARM_GET_SYM_BRANCH_TYPE (sym->st_target_internal);
12518
12519 r = elf32_arm_final_link_relocate (howto, input_bfd, output_bfd,
12520 input_section, contents, rel,
12521 relocation, info, sec, name,
12522 sym_type, branch_type, h,
12523 &unresolved_reloc,
12524 &error_message);
12525 }
0945cdfd
DJ		 12526
12527 /* Dynamic relocs are not propagated for SEC_DEBUGGING sections
12528 because such sections are not SEC_ALLOC and thus ld.so will
12529 not process them. */
12530 if (unresolved_reloc
99059e56
RM		 12531 && !((input_section->flags & SEC_DEBUGGING) != 0
12532 && h->def_dynamic)
1d5316ab
AM		 12533 && _bfd_elf_section_offset (output_bfd, info, input_section,
12534 rel->r_offset) != (bfd_vma) -1)
0945cdfd 12535 {
4eca0228 12536 _bfd_error_handler
695344c0 12537 /* xgettext:c-format */
843fe662
L		 12538 (_("%B(%A+0x%lx): unresolvable %s relocation against symbol `%s'"),
12539 input_bfd,
12540 input_section,
12541 (long) rel->r_offset,
12542 howto->name,
12543 h->root.root.string);
0945cdfd
DJ		 12544 return FALSE;
12545 }
252b5132
RH		 12546
12547 if (r != bfd_reloc_ok)
12548 {
252b5132
RH		 12549 switch (r)
12550 {
12551 case bfd_reloc_overflow:
cf919dfd
PB		 12552 /* If the overflowing reloc was to an undefined symbol,
12553 we have already printed one error message and there
12554 is no point complaining again. */
1a72702b
AM		 12555 if (!h || h->root.type != bfd_link_hash_undefined)
12556 (*info->callbacks->reloc_overflow)
12557 (info, (h ? &h->root : NULL), name, howto->name,
12558 (bfd_vma) 0, input_bfd, input_section, rel->r_offset);
252b5132
RH		 12559 break;
12560
12561 case bfd_reloc_undefined:
1a72702b
AM		 12562 (*info->callbacks->undefined_symbol)
12563 (info, name, input_bfd, input_section, rel->r_offset, TRUE);
252b5132
RH		 12564 break;
12565
12566 case bfd_reloc_outofrange:
f2a9dd69 12567 error_message = _("out of range");
252b5132
RH		 12568 goto common_error;
12569
12570 case bfd_reloc_notsupported:
f2a9dd69 12571 error_message = _("unsupported relocation");
252b5132
RH		 12572 goto common_error;
12573
12574 case bfd_reloc_dangerous:
f2a9dd69 12575 /* error_message should already be set. */
252b5132
RH		 12576 goto common_error;
12577
12578 default:
f2a9dd69 12579 error_message = _("unknown error");
8029a119 12580 /* Fall through. */
252b5132
RH		 12581
12582 common_error:
f2a9dd69 12583 BFD_ASSERT (error_message != NULL);
1a72702b
AM		 12584 (*info->callbacks->reloc_dangerous)
12585 (info, error_message, input_bfd, input_section, rel->r_offset);
252b5132
RH		 12586 break;
12587 }
12588 }
12589 }
12590
b34976b6 12591 return TRUE;
252b5132
RH		 12592}
12593
91d6fa6a 12594/* Add a new unwind edit to the list described by HEAD, TAIL. If TINDEX is zero,
2468f9c9 12595 adds the edit to the start of the list. (The list must be built in order of
91d6fa6a 12596 ascending TINDEX: the function's callers are primarily responsible for
2468f9c9
PB		 12597 maintaining that condition). */
12598
12599static void
12600add_unwind_table_edit (arm_unwind_table_edit **head,
12601 arm_unwind_table_edit **tail,
12602 arm_unwind_edit_type type,
12603 asection *linked_section,
91d6fa6a 12604 unsigned int tindex)
2468f9c9 12605{
21d799b5
NC		 12606 arm_unwind_table_edit *new_edit = (arm_unwind_table_edit *)
12607 xmalloc (sizeof (arm_unwind_table_edit));
b38cadfb 12608
2468f9c9
PB		 12609 new_edit->type = type;
12610 new_edit->linked_section = linked_section;
91d6fa6a 12611 new_edit->index = tindex;
b38cadfb 12612
91d6fa6a 12613 if (tindex > 0)
2468f9c9
PB		 12614 {
12615 new_edit->next = NULL;
12616
12617 if (*tail)
12618 (*tail)->next = new_edit;
12619
12620 (*tail) = new_edit;
12621
12622 if (!*head)
12623 (*head) = new_edit;
12624 }
12625 else
12626 {
12627 new_edit->next = *head;
12628
12629 if (!*tail)
12630 *tail = new_edit;
12631
12632 *head = new_edit;
12633 }
12634}
12635
12636static _arm_elf_section_data *get_arm_elf_section_data (asection *);
12637
12638/* Increase the size of EXIDX_SEC by ADJUST bytes. ADJUST mau be negative. */
12639static void
12640adjust_exidx_size(asection *exidx_sec, int adjust)
12641{
12642 asection *out_sec;
12643
12644 if (!exidx_sec->rawsize)
12645 exidx_sec->rawsize = exidx_sec->size;
12646
12647 bfd_set_section_size (exidx_sec->owner, exidx_sec, exidx_sec->size + adjust);
12648 out_sec = exidx_sec->output_section;
12649 /* Adjust size of output section. */
12650 bfd_set_section_size (out_sec->owner, out_sec, out_sec->size +adjust);
12651}
12652
12653/* Insert an EXIDX_CANTUNWIND marker at the end of a section. */
12654static void
12655insert_cantunwind_after(asection *text_sec, asection *exidx_sec)
12656{
12657 struct _arm_elf_section_data *exidx_arm_data;
12658
12659 exidx_arm_data = get_arm_elf_section_data (exidx_sec);
12660 add_unwind_table_edit (
12661 &exidx_arm_data->u.exidx.unwind_edit_list,
12662 &exidx_arm_data->u.exidx.unwind_edit_tail,
12663 INSERT_EXIDX_CANTUNWIND_AT_END, text_sec, UINT_MAX);
12664
491d01d3
YU		 12665 exidx_arm_data->additional_reloc_count++;
12666
2468f9c9
PB		 12667 adjust_exidx_size(exidx_sec, 8);
12668}
12669
12670/* Scan .ARM.exidx tables, and create a list describing edits which should be
12671 made to those tables, such that:
b38cadfb 12672
2468f9c9
PB		 12673 1. Regions without unwind data are marked with EXIDX_CANTUNWIND entries.
12674 2. Duplicate entries are merged together (EXIDX_CANTUNWIND, or unwind
99059e56 12675 codes which have been inlined into the index).
2468f9c9 12676
85fdf906
AH		 12677 If MERGE_EXIDX_ENTRIES is false, duplicate entries are not merged.
12678
2468f9c9 12679 The edits are applied when the tables are written
b38cadfb 12680 (in elf32_arm_write_section). */
2468f9c9
PB		 12681
12682bfd_boolean
12683elf32_arm_fix_exidx_coverage (asection **text_section_order,
12684 unsigned int num_text_sections,
85fdf906
AH		 12685 struct bfd_link_info *info,
12686 bfd_boolean merge_exidx_entries)
2468f9c9
PB		 12687{
12688 bfd *inp;
12689 unsigned int last_second_word = 0, i;
12690 asection *last_exidx_sec = NULL;
12691 asection *last_text_sec = NULL;
12692 int last_unwind_type = -1;
12693
12694 /* Walk over all EXIDX sections, and create backlinks from the corrsponding
12695 text sections. */
c72f2fb2 12696 for (inp = info->input_bfds; inp != NULL; inp = inp->link.next)
2468f9c9
PB		 12697 {
12698 asection *sec;
b38cadfb 12699
2468f9c9 12700 for (sec = inp->sections; sec != NULL; sec = sec->next)
99059e56 12701 {
2468f9c9
PB		 12702 struct bfd_elf_section_data *elf_sec = elf_section_data (sec);
12703 Elf_Internal_Shdr *hdr = &elf_sec->this_hdr;
b38cadfb 12704
dec9d5df 12705 if (!hdr || hdr->sh_type != SHT_ARM_EXIDX)
2468f9c9 12706 continue;
b38cadfb 12707
2468f9c9
PB		 12708 if (elf_sec->linked_to)
12709 {
12710 Elf_Internal_Shdr *linked_hdr
99059e56 12711 = &elf_section_data (elf_sec->linked_to)->this_hdr;
2468f9c9 12712 struct _arm_elf_section_data *linked_sec_arm_data
99059e56 12713 = get_arm_elf_section_data (linked_hdr->bfd_section);
2468f9c9
PB		 12714
12715 if (linked_sec_arm_data == NULL)
99059e56 12716 continue;
2468f9c9
PB		 12717
12718 /* Link this .ARM.exidx section back from the text section it
99059e56 12719 describes. */
2468f9c9
PB		 12720 linked_sec_arm_data->u.text.arm_exidx_sec = sec;
12721 }
12722 }
12723 }
12724
12725 /* Walk all text sections in order of increasing VMA. Eilminate duplicate
12726 index table entries (EXIDX_CANTUNWIND and inlined unwind opcodes),
91d6fa6a 12727 and add EXIDX_CANTUNWIND entries for sections with no unwind table data. */
2468f9c9
PB		 12728
12729 for (i = 0; i < num_text_sections; i++)
12730 {
12731 asection *sec = text_section_order[i];
12732 asection *exidx_sec;
12733 struct _arm_elf_section_data *arm_data = get_arm_elf_section_data (sec);
12734 struct _arm_elf_section_data *exidx_arm_data;
12735 bfd_byte *contents = NULL;
12736 int deleted_exidx_bytes = 0;
12737 bfd_vma j;
12738 arm_unwind_table_edit *unwind_edit_head = NULL;
12739 arm_unwind_table_edit *unwind_edit_tail = NULL;
12740 Elf_Internal_Shdr *hdr;
12741 bfd *ibfd;
12742
12743 if (arm_data == NULL)
99059e56 12744 continue;
2468f9c9
PB		 12745
12746 exidx_sec = arm_data->u.text.arm_exidx_sec;
12747 if (exidx_sec == NULL)
12748 {
12749 /* Section has no unwind data. */
12750 if (last_unwind_type == 0 || !last_exidx_sec)
12751 continue;
12752
12753 /* Ignore zero sized sections. */
12754 if (sec->size == 0)
12755 continue;
12756
12757 insert_cantunwind_after(last_text_sec, last_exidx_sec);
12758 last_unwind_type = 0;
12759 continue;
12760 }
12761
22a8f80e
PB		 12762 /* Skip /DISCARD/ sections. */
12763 if (bfd_is_abs_section (exidx_sec->output_section))
12764 continue;
12765
2468f9c9
PB		 12766 hdr = &elf_section_data (exidx_sec)->this_hdr;
12767 if (hdr->sh_type != SHT_ARM_EXIDX)
99059e56 12768 continue;
b38cadfb 12769
2468f9c9
PB		 12770 exidx_arm_data = get_arm_elf_section_data (exidx_sec);
12771 if (exidx_arm_data == NULL)
99059e56 12772 continue;
b38cadfb 12773
2468f9c9 12774 ibfd = exidx_sec->owner;
b38cadfb 12775
2468f9c9
PB		 12776 if (hdr->contents != NULL)
12777 contents = hdr->contents;
12778 else if (! bfd_malloc_and_get_section (ibfd, exidx_sec, &contents))
12779 /* An error? */
12780 continue;
12781
ac06903d
YU		 12782 if (last_unwind_type > 0)
12783 {
12784 unsigned int first_word = bfd_get_32 (ibfd, contents);
12785 /* Add cantunwind if first unwind item does not match section
12786 start. */
12787 if (first_word != sec->vma)
12788 {
12789 insert_cantunwind_after (last_text_sec, last_exidx_sec);
12790 last_unwind_type = 0;
12791 }
12792 }
12793
2468f9c9
PB		 12794 for (j = 0; j < hdr->sh_size; j += 8)
12795 {
12796 unsigned int second_word = bfd_get_32 (ibfd, contents + j + 4);
12797 int unwind_type;
12798 int elide = 0;
12799
12800 /* An EXIDX_CANTUNWIND entry. */
12801 if (second_word == 1)
12802 {
12803 if (last_unwind_type == 0)
12804 elide = 1;
12805 unwind_type = 0;
12806 }
12807 /* Inlined unwinding data. Merge if equal to previous. */
12808 else if ((second_word & 0x80000000) != 0)
12809 {
85fdf906
AH		 12810 if (merge_exidx_entries
12811 && last_second_word == second_word && last_unwind_type == 1)
2468f9c9
PB		 12812 elide = 1;
12813 unwind_type = 1;
12814 last_second_word = second_word;
12815 }
12816 /* Normal table entry. In theory we could merge these too,
12817 but duplicate entries are likely to be much less common. */
12818 else
12819 unwind_type = 2;
12820
491d01d3 12821 if (elide && !bfd_link_relocatable (info))
2468f9c9
PB		 12822 {
12823 add_unwind_table_edit (&unwind_edit_head, &unwind_edit_tail,
12824 DELETE_EXIDX_ENTRY, NULL, j / 8);
12825
12826 deleted_exidx_bytes += 8;
12827 }
12828
12829 last_unwind_type = unwind_type;
12830 }
12831
12832 /* Free contents if we allocated it ourselves. */
12833 if (contents != hdr->contents)
99059e56 12834 free (contents);
2468f9c9
PB		 12835
12836 /* Record edits to be applied later (in elf32_arm_write_section). */
12837 exidx_arm_data->u.exidx.unwind_edit_list = unwind_edit_head;
12838 exidx_arm_data->u.exidx.unwind_edit_tail = unwind_edit_tail;
b38cadfb 12839
2468f9c9
PB		 12840 if (deleted_exidx_bytes > 0)
12841 adjust_exidx_size(exidx_sec, -deleted_exidx_bytes);
12842
12843 last_exidx_sec = exidx_sec;
12844 last_text_sec = sec;
12845 }
12846
12847 /* Add terminating CANTUNWIND entry. */
491d01d3
YU		 12848 if (!bfd_link_relocatable (info) && last_exidx_sec
12849 && last_unwind_type != 0)
2468f9c9
PB		 12850 insert_cantunwind_after(last_text_sec, last_exidx_sec);
12851
12852 return TRUE;
12853}
12854
3e6b1042
DJ		 12855static bfd_boolean
12856elf32_arm_output_glue_section (struct bfd_link_info *info, bfd *obfd,
12857 bfd *ibfd, const char *name)
12858{
12859 asection *sec, *osec;
12860
3d4d4302 12861 sec = bfd_get_linker_section (ibfd, name);
3e6b1042
DJ		 12862 if (sec == NULL || (sec->flags & SEC_EXCLUDE) != 0)
12863 return TRUE;
12864
12865 osec = sec->output_section;
12866 if (elf32_arm_write_section (obfd, info, sec, sec->contents))
12867 return TRUE;
12868
12869 if (! bfd_set_section_contents (obfd, osec, sec->contents,
12870 sec->output_offset, sec->size))
12871 return FALSE;
12872
12873 return TRUE;
12874}
12875
12876static bfd_boolean
12877elf32_arm_final_link (bfd *abfd, struct bfd_link_info *info)
12878{
12879 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (info);
fe33d2fa 12880 asection *sec, *osec;
3e6b1042 12881
4dfe6ac6
NC		 12882 if (globals == NULL)
12883 return FALSE;
12884
3e6b1042
DJ		 12885 /* Invoke the regular ELF backend linker to do all the work. */
12886 if (!bfd_elf_final_link (abfd, info))
12887 return FALSE;
12888
fe33d2fa
CL		 12889 /* Process stub sections (eg BE8 encoding, ...). */
12890 struct elf32_arm_link_hash_table *htab = elf32_arm_hash_table (info);
7292b3ac 12891 unsigned int i;
cdb21a0a
NS		 12892 for (i=0; i<htab->top_id; i++)
12893 {
12894 sec = htab->stub_group[i].stub_sec;
12895 /* Only process it once, in its link_sec slot. */
12896 if (sec && i == htab->stub_group[i].link_sec->id)
12897 {
12898 osec = sec->output_section;
12899 elf32_arm_write_section (abfd, info, sec, sec->contents);
12900 if (! bfd_set_section_contents (abfd, osec, sec->contents,
12901 sec->output_offset, sec->size))
12902 return FALSE;
12903 }
fe33d2fa 12904 }
fe33d2fa 12905
3e6b1042
DJ		 12906 /* Write out any glue sections now that we have created all the
12907 stubs. */
12908 if (globals->bfd_of_glue_owner != NULL)
12909 {
12910 if (! elf32_arm_output_glue_section (info, abfd,
12911 globals->bfd_of_glue_owner,
12912 ARM2THUMB_GLUE_SECTION_NAME))
12913 return FALSE;
12914
12915 if (! elf32_arm_output_glue_section (info, abfd,
12916 globals->bfd_of_glue_owner,
12917 THUMB2ARM_GLUE_SECTION_NAME))
12918 return FALSE;
12919
12920 if (! elf32_arm_output_glue_section (info, abfd,
12921 globals->bfd_of_glue_owner,
12922 VFP11_ERRATUM_VENEER_SECTION_NAME))
12923 return FALSE;
12924
a504d23a
LA		 12925 if (! elf32_arm_output_glue_section (info, abfd,
12926 globals->bfd_of_glue_owner,
12927 STM32L4XX_ERRATUM_VENEER_SECTION_NAME))
12928 return FALSE;
12929
3e6b1042
DJ		 12930 if (! elf32_arm_output_glue_section (info, abfd,
12931 globals->bfd_of_glue_owner,
12932 ARM_BX_GLUE_SECTION_NAME))
12933 return FALSE;
12934 }
12935
12936 return TRUE;
12937}
12938
5968a7b8
NC		 12939/* Return a best guess for the machine number based on the attributes. */
12940
12941static unsigned int
12942bfd_arm_get_mach_from_attributes (bfd * abfd)
12943{
12944 int arch = bfd_elf_get_obj_attr_int (abfd, OBJ_ATTR_PROC, Tag_CPU_arch);
12945
12946 switch (arch)
12947 {
12948 case TAG_CPU_ARCH_V4: return bfd_mach_arm_4;
12949 case TAG_CPU_ARCH_V4T: return bfd_mach_arm_4T;
12950 case TAG_CPU_ARCH_V5T: return bfd_mach_arm_5T;
12951
12952 case TAG_CPU_ARCH_V5TE:
12953 {
12954 char * name;
12955
12956 BFD_ASSERT (Tag_CPU_name < NUM_KNOWN_OBJ_ATTRIBUTES);
12957 name = elf_known_obj_attributes (abfd) [OBJ_ATTR_PROC][Tag_CPU_name].s;
12958
12959 if (name)
12960 {
12961 if (strcmp (name, "IWMMXT2") == 0)
12962 return bfd_mach_arm_iWMMXt2;
12963
12964 if (strcmp (name, "IWMMXT") == 0)
6034aab8 12965 return bfd_mach_arm_iWMMXt;
088ca6c1
NC		 12966
12967 if (strcmp (name, "XSCALE") == 0)
12968 {
12969 int wmmx;
12970
12971 BFD_ASSERT (Tag_WMMX_arch < NUM_KNOWN_OBJ_ATTRIBUTES);
12972 wmmx = elf_known_obj_attributes (abfd) [OBJ_ATTR_PROC][Tag_WMMX_arch].i;
12973 switch (wmmx)
12974 {
12975 case 1: return bfd_mach_arm_iWMMXt;
12976 case 2: return bfd_mach_arm_iWMMXt2;
12977 default: return bfd_mach_arm_XScale;
12978 }
12979 }
5968a7b8
NC		 12980 }
12981
12982 return bfd_mach_arm_5TE;
12983 }
12984
12985 default:
12986 return bfd_mach_arm_unknown;
12987 }
12988}
12989
c178919b
NC		 12990/* Set the right machine number. */
12991
12992static bfd_boolean
57e8b36a 12993elf32_arm_object_p (bfd *abfd)
c178919b 12994{
5a6c6817 12995 unsigned int mach;
57e8b36a 12996
5a6c6817 12997 mach = bfd_arm_get_mach_from_notes (abfd, ARM_NOTE_SECTION);
c178919b 12998
5968a7b8
NC		 12999 if (mach == bfd_mach_arm_unknown)
13000 {
13001 if (elf_elfheader (abfd)->e_flags & EF_ARM_MAVERICK_FLOAT)
13002 mach = bfd_mach_arm_ep9312;
13003 else
13004 mach = bfd_arm_get_mach_from_attributes (abfd);
13005 }
c178919b 13006
5968a7b8 13007 bfd_default_set_arch_mach (abfd, bfd_arch_arm, mach);
c178919b
NC		 13008 return TRUE;
13009}
13010
fc830a83 13011/* Function to keep ARM specific flags in the ELF header. */
3c9458e9 13012
b34976b6 13013static bfd_boolean
57e8b36a 13014elf32_arm_set_private_flags (bfd *abfd, flagword flags)
252b5132
RH		 13015{
13016 if (elf_flags_init (abfd)
13017 && elf_elfheader (abfd)->e_flags != flags)
13018 {
fc830a83
NC		 13019 if (EF_ARM_EABI_VERSION (flags) == EF_ARM_EABI_UNKNOWN)
13020 {
fd2ec330 13021 if (flags & EF_ARM_INTERWORK)
4eca0228 13022 _bfd_error_handler
d003868e
AM		 13023 (_("Warning: Not setting interworking flag of %B since it has already been specified as non-interworking"),
13024 abfd);
fc830a83 13025 else
d003868e
AM		 13026 _bfd_error_handler
13027 (_("Warning: Clearing the interworking flag of %B due to outside request"),
13028 abfd);
fc830a83 13029 }
252b5132
RH		 13030 }
13031 else
13032 {
13033 elf_elfheader (abfd)->e_flags = flags;
b34976b6 13034 elf_flags_init (abfd) = TRUE;
252b5132
RH		 13035 }
13036
b34976b6 13037 return TRUE;
252b5132
RH		 13038}
13039
fc830a83 13040/* Copy backend specific data from one object module to another. */
9b485d32 13041
b34976b6 13042static bfd_boolean
57e8b36a 13043elf32_arm_copy_private_bfd_data (bfd *ibfd, bfd *obfd)
252b5132
RH		 13044{
13045 flagword in_flags;
13046 flagword out_flags;
13047
0ffa91dd 13048 if (! is_arm_elf (ibfd) || ! is_arm_elf (obfd))
b34976b6 13049 return TRUE;
252b5132 13050
fc830a83 13051 in_flags = elf_elfheader (ibfd)->e_flags;
252b5132
RH		 13052 out_flags = elf_elfheader (obfd)->e_flags;
13053
fc830a83
NC		 13054 if (elf_flags_init (obfd)
13055 && EF_ARM_EABI_VERSION (out_flags) == EF_ARM_EABI_UNKNOWN
13056 && in_flags != out_flags)
252b5132 13057 {
252b5132 13058 /* Cannot mix APCS26 and APCS32 code. */
fd2ec330 13059 if ((in_flags & EF_ARM_APCS_26) != (out_flags & EF_ARM_APCS_26))
b34976b6 13060 return FALSE;
252b5132
RH		 13061
13062 /* Cannot mix float APCS and non-float APCS code. */
fd2ec330 13063 if ((in_flags & EF_ARM_APCS_FLOAT) != (out_flags & EF_ARM_APCS_FLOAT))
b34976b6 13064 return FALSE;
252b5132
RH		 13065
13066 /* If the src and dest have different interworking flags
99059e56 13067 then turn off the interworking bit. */
fd2ec330 13068 if ((in_flags & EF_ARM_INTERWORK) != (out_flags & EF_ARM_INTERWORK))
252b5132 13069 {
fd2ec330 13070 if (out_flags & EF_ARM_INTERWORK)
d003868e
AM		 13071 _bfd_error_handler
13072 (_("Warning: Clearing the interworking flag of %B because non-interworking code in %B has been linked with it"),
13073 obfd, ibfd);
252b5132 13074
fd2ec330 13075 in_flags &= ~EF_ARM_INTERWORK;
252b5132 13076 }
1006ba19
PB		 13077
13078 /* Likewise for PIC, though don't warn for this case. */
fd2ec330
PB		 13079 if ((in_flags & EF_ARM_PIC) != (out_flags & EF_ARM_PIC))
13080 in_flags &= ~EF_ARM_PIC;
252b5132
RH		 13081 }
13082
13083 elf_elfheader (obfd)->e_flags = in_flags;
b34976b6 13084 elf_flags_init (obfd) = TRUE;
252b5132 13085
e2349352 13086 return _bfd_elf_copy_private_bfd_data (ibfd, obfd);
ee065d83
PB		 13087}
13088
13089/* Values for Tag_ABI_PCS_R9_use. */
13090enum
13091{
13092 AEABI_R9_V6,
13093 AEABI_R9_SB,
13094 AEABI_R9_TLS,
13095 AEABI_R9_unused
13096};
13097
13098/* Values for Tag_ABI_PCS_RW_data. */
13099enum
13100{
13101 AEABI_PCS_RW_data_absolute,
13102 AEABI_PCS_RW_data_PCrel,
13103 AEABI_PCS_RW_data_SBrel,
13104 AEABI_PCS_RW_data_unused
13105};
13106
13107/* Values for Tag_ABI_enum_size. */
13108enum
13109{
13110 AEABI_enum_unused,
13111 AEABI_enum_short,
13112 AEABI_enum_wide,
13113 AEABI_enum_forced_wide
13114};
13115
104d59d1
JM		 13116/* Determine whether an object attribute tag takes an integer, a
13117 string or both. */
906e58ca 13118
104d59d1
JM		 13119static int
13120elf32_arm_obj_attrs_arg_type (int tag)
13121{
13122 if (tag == Tag_compatibility)
3483fe2e 13123 return ATTR_TYPE_FLAG_INT_VAL | ATTR_TYPE_FLAG_STR_VAL;
2d0bb761 13124 else if (tag == Tag_nodefaults)
3483fe2e
AS		 13125 return ATTR_TYPE_FLAG_INT_VAL | ATTR_TYPE_FLAG_NO_DEFAULT;
13126 else if (tag == Tag_CPU_raw_name || tag == Tag_CPU_name)
13127 return ATTR_TYPE_FLAG_STR_VAL;
104d59d1 13128 else if (tag < 32)
3483fe2e 13129 return ATTR_TYPE_FLAG_INT_VAL;
104d59d1 13130 else
3483fe2e 13131 return (tag & 1) != 0 ? ATTR_TYPE_FLAG_STR_VAL : ATTR_TYPE_FLAG_INT_VAL;
104d59d1
JM		 13132}
13133
5aa6ff7c
AS		 13134/* The ABI defines that Tag_conformance should be emitted first, and that
13135 Tag_nodefaults should be second (if either is defined). This sets those
13136 two positions, and bumps up the position of all the remaining tags to
13137 compensate. */
13138static int
13139elf32_arm_obj_attrs_order (int num)
13140{
3de4a297 13141 if (num == LEAST_KNOWN_OBJ_ATTRIBUTE)
5aa6ff7c 13142 return Tag_conformance;
3de4a297 13143 if (num == LEAST_KNOWN_OBJ_ATTRIBUTE + 1)
5aa6ff7c
AS		 13144 return Tag_nodefaults;
13145 if ((num - 2) < Tag_nodefaults)
13146 return num - 2;
13147 if ((num - 1) < Tag_conformance)
13148 return num - 1;
13149 return num;
13150}
13151
e8b36cd1
JM		 13152/* Attribute numbers >=64 (mod 128) can be safely ignored. */
13153static bfd_boolean
13154elf32_arm_obj_attrs_handle_unknown (bfd *abfd, int tag)
13155{
13156 if ((tag & 127) < 64)
13157 {
13158 _bfd_error_handler
13159 (_("%B: Unknown mandatory EABI object attribute %d"),
13160 abfd, tag);
13161 bfd_set_error (bfd_error_bad_value);
13162 return FALSE;
13163 }
13164 else
13165 {
13166 _bfd_error_handler
13167 (_("Warning: %B: Unknown EABI object attribute %d"),
13168 abfd, tag);
13169 return TRUE;
13170 }
13171}
13172
91e22acd
AS		 13173/* Read the architecture from the Tag_also_compatible_with attribute, if any.
13174 Returns -1 if no architecture could be read. */
13175
13176static int
13177get_secondary_compatible_arch (bfd *abfd)
13178{
13179 obj_attribute *attr =
13180 &elf_known_obj_attributes_proc (abfd)[Tag_also_compatible_with];
13181
13182 /* Note: the tag and its argument below are uleb128 values, though
13183 currently-defined values fit in one byte for each. */
13184 if (attr->s
13185 && attr->s[0] == Tag_CPU_arch
13186 && (attr->s[1] & 128) != 128
13187 && attr->s[2] == 0)
13188 return attr->s[1];
13189
13190 /* This tag is "safely ignorable", so don't complain if it looks funny. */
13191 return -1;
13192}
13193
13194/* Set, or unset, the architecture of the Tag_also_compatible_with attribute.
13195 The tag is removed if ARCH is -1. */
13196
8e79c3df 13197static void
91e22acd 13198set_secondary_compatible_arch (bfd *abfd, int arch)
8e79c3df 13199{
91e22acd
AS		 13200 obj_attribute *attr =
13201 &elf_known_obj_attributes_proc (abfd)[Tag_also_compatible_with];
8e79c3df 13202
91e22acd
AS		 13203 if (arch == -1)
13204 {
13205 attr->s = NULL;
13206 return;
8e79c3df 13207 }
91e22acd
AS		 13208
13209 /* Note: the tag and its argument below are uleb128 values, though
13210 currently-defined values fit in one byte for each. */
13211 if (!attr->s)
21d799b5 13212 attr->s = (char *) bfd_alloc (abfd, 3);
91e22acd
AS		 13213 attr->s[0] = Tag_CPU_arch;
13214 attr->s[1] = arch;
13215 attr->s[2] = '\0';
8e79c3df
CM		 13216}
13217
91e22acd
AS		 13218/* Combine two values for Tag_CPU_arch, taking secondary compatibility tags
13219 into account. */
13220
13221static int
13222tag_cpu_arch_combine (bfd *ibfd, int oldtag, int *secondary_compat_out,
13223 int newtag, int secondary_compat)
8e79c3df 13224{
91e22acd
AS		 13225#define T(X) TAG_CPU_ARCH_##X
13226 int tagl, tagh, result;
13227 const int v6t2[] =
13228 {
13229 T(V6T2), /* PRE_V4. */
13230 T(V6T2), /* V4. */
13231 T(V6T2), /* V4T. */
13232 T(V6T2), /* V5T. */
13233 T(V6T2), /* V5TE. */
13234 T(V6T2), /* V5TEJ. */
13235 T(V6T2), /* V6. */
13236 T(V7), /* V6KZ. */
13237 T(V6T2) /* V6T2. */
13238 };
13239 const int v6k[] =
13240 {
13241 T(V6K), /* PRE_V4. */
13242 T(V6K), /* V4. */
13243 T(V6K), /* V4T. */
13244 T(V6K), /* V5T. */
13245 T(V6K), /* V5TE. */
13246 T(V6K), /* V5TEJ. */
13247 T(V6K), /* V6. */
13248 T(V6KZ), /* V6KZ. */
13249 T(V7), /* V6T2. */
13250 T(V6K) /* V6K. */
13251 };
13252 const int v7[] =
13253 {
13254 T(V7), /* PRE_V4. */
13255 T(V7), /* V4. */
13256 T(V7), /* V4T. */
13257 T(V7), /* V5T. */
13258 T(V7), /* V5TE. */
13259 T(V7), /* V5TEJ. */
13260 T(V7), /* V6. */
13261 T(V7), /* V6KZ. */
13262 T(V7), /* V6T2. */
13263 T(V7), /* V6K. */
13264 T(V7) /* V7. */
13265 };
13266 const int v6_m[] =
13267 {
13268 -1, /* PRE_V4. */
13269 -1, /* V4. */
13270 T(V6K), /* V4T. */
13271 T(V6K), /* V5T. */
13272 T(V6K), /* V5TE. */
13273 T(V6K), /* V5TEJ. */
13274 T(V6K), /* V6. */
13275 T(V6KZ), /* V6KZ. */
13276 T(V7), /* V6T2. */
13277 T(V6K), /* V6K. */
13278 T(V7), /* V7. */
13279 T(V6_M) /* V6_M. */
13280 };
13281 const int v6s_m[] =
13282 {
13283 -1, /* PRE_V4. */
13284 -1, /* V4. */
13285 T(V6K), /* V4T. */
13286 T(V6K), /* V5T. */
13287 T(V6K), /* V5TE. */
13288 T(V6K), /* V5TEJ. */
13289 T(V6K), /* V6. */
13290 T(V6KZ), /* V6KZ. */
13291 T(V7), /* V6T2. */
13292 T(V6K), /* V6K. */
13293 T(V7), /* V7. */
13294 T(V6S_M), /* V6_M. */
13295 T(V6S_M) /* V6S_M. */
13296 };
9e3c6df6
PB		 13297 const int v7e_m[] =
13298 {
13299 -1, /* PRE_V4. */
13300 -1, /* V4. */
13301 T(V7E_M), /* V4T. */
13302 T(V7E_M), /* V5T. */
13303 T(V7E_M), /* V5TE. */
13304 T(V7E_M), /* V5TEJ. */
13305 T(V7E_M), /* V6. */
13306 T(V7E_M), /* V6KZ. */
13307 T(V7E_M), /* V6T2. */
13308 T(V7E_M), /* V6K. */
13309 T(V7E_M), /* V7. */
13310 T(V7E_M), /* V6_M. */
13311 T(V7E_M), /* V6S_M. */
13312 T(V7E_M) /* V7E_M. */
13313 };
bca38921
MGD		 13314 const int v8[] =
13315 {
13316 T(V8), /* PRE_V4. */
13317 T(V8), /* V4. */
13318 T(V8), /* V4T. */
13319 T(V8), /* V5T. */
13320 T(V8), /* V5TE. */
13321 T(V8), /* V5TEJ. */
13322 T(V8), /* V6. */
13323 T(V8), /* V6KZ. */
13324 T(V8), /* V6T2. */
13325 T(V8), /* V6K. */
13326 T(V8), /* V7. */
13327 T(V8), /* V6_M. */
13328 T(V8), /* V6S_M. */
13329 T(V8), /* V7E_M. */
13330 T(V8) /* V8. */
13331 };
2fd158eb
TP		 13332 const int v8m_baseline[] =
13333 {
13334 -1, /* PRE_V4. */
13335 -1, /* V4. */
13336 -1, /* V4T. */
13337 -1, /* V5T. */
13338 -1, /* V5TE. */
13339 -1, /* V5TEJ. */
13340 -1, /* V6. */
13341 -1, /* V6KZ. */
13342 -1, /* V6T2. */
13343 -1, /* V6K. */
13344 -1, /* V7. */
13345 T(V8M_BASE), /* V6_M. */
13346 T(V8M_BASE), /* V6S_M. */
13347 -1, /* V7E_M. */
13348 -1, /* V8. */
13349 -1,
13350 T(V8M_BASE) /* V8-M BASELINE. */
13351 };
13352 const int v8m_mainline[] =
13353 {
13354 -1, /* PRE_V4. */
13355 -1, /* V4. */
13356 -1, /* V4T. */
13357 -1, /* V5T. */
13358 -1, /* V5TE. */
13359 -1, /* V5TEJ. */
13360 -1, /* V6. */
13361 -1, /* V6KZ. */
13362 -1, /* V6T2. */
13363 -1, /* V6K. */
13364 T(V8M_MAIN), /* V7. */
13365 T(V8M_MAIN), /* V6_M. */
13366 T(V8M_MAIN), /* V6S_M. */
13367 T(V8M_MAIN), /* V7E_M. */
13368 -1, /* V8. */
13369 -1,
13370 T(V8M_MAIN), /* V8-M BASELINE. */
13371 T(V8M_MAIN) /* V8-M MAINLINE. */
13372 };
91e22acd
AS		 13373 const int v4t_plus_v6_m[] =
13374 {
13375 -1, /* PRE_V4. */
13376 -1, /* V4. */
13377 T(V4T), /* V4T. */
13378 T(V5T), /* V5T. */
13379 T(V5TE), /* V5TE. */
13380 T(V5TEJ), /* V5TEJ. */
13381 T(V6), /* V6. */
13382 T(V6KZ), /* V6KZ. */
13383 T(V6T2), /* V6T2. */
13384 T(V6K), /* V6K. */
13385 T(V7), /* V7. */
13386 T(V6_M), /* V6_M. */
13387 T(V6S_M), /* V6S_M. */
9e3c6df6 13388 T(V7E_M), /* V7E_M. */
bca38921 13389 T(V8), /* V8. */
4ed7ed8d 13390 -1, /* Unused. */
2fd158eb
TP		 13391 T(V8M_BASE), /* V8-M BASELINE. */
13392 T(V8M_MAIN), /* V8-M MAINLINE. */
91e22acd
AS		 13393 T(V4T_PLUS_V6_M) /* V4T plus V6_M. */
13394 };
13395 const int *comb[] =
13396 {
13397 v6t2,
13398 v6k,
13399 v7,
13400 v6_m,
13401 v6s_m,
9e3c6df6 13402 v7e_m,
bca38921 13403 v8,
4ed7ed8d 13404 NULL,
2fd158eb
TP		 13405 v8m_baseline,
13406 v8m_mainline,
91e22acd
AS		 13407 /* Pseudo-architecture. */
13408 v4t_plus_v6_m
13409 };
13410
13411 /* Check we've not got a higher architecture than we know about. */
13412
9e3c6df6 13413 if (oldtag > MAX_TAG_CPU_ARCH || newtag > MAX_TAG_CPU_ARCH)
91e22acd 13414 {
3895f852 13415 _bfd_error_handler (_("error: %B: Unknown CPU architecture"), ibfd);
91e22acd
AS		 13416 return -1;
13417 }
13418
13419 /* Override old tag if we have a Tag_also_compatible_with on the output. */
13420
13421 if ((oldtag == T(V6_M) && *secondary_compat_out == T(V4T))
13422 || (oldtag == T(V4T) && *secondary_compat_out == T(V6_M)))
13423 oldtag = T(V4T_PLUS_V6_M);
13424
13425 /* And override the new tag if we have a Tag_also_compatible_with on the
13426 input. */
13427
13428 if ((newtag == T(V6_M) && secondary_compat == T(V4T))
13429 || (newtag == T(V4T) && secondary_compat == T(V6_M)))
13430 newtag = T(V4T_PLUS_V6_M);
13431
13432 tagl = (oldtag < newtag) ? oldtag : newtag;
13433 result = tagh = (oldtag > newtag) ? oldtag : newtag;
13434
13435 /* Architectures before V6KZ add features monotonically. */
13436 if (tagh <= TAG_CPU_ARCH_V6KZ)
13437 return result;
13438
4ed7ed8d 13439 result = comb[tagh - T(V6T2)] ? comb[tagh - T(V6T2)][tagl] : -1;
91e22acd
AS		 13440
13441 /* Use Tag_CPU_arch == V4T and Tag_also_compatible_with (Tag_CPU_arch V6_M)
13442 as the canonical version. */
13443 if (result == T(V4T_PLUS_V6_M))
13444 {
13445 result = T(V4T);
13446 *secondary_compat_out = T(V6_M);
13447 }
13448 else
13449 *secondary_compat_out = -1;
13450
13451 if (result == -1)
13452 {
3895f852 13453 _bfd_error_handler (_("error: %B: Conflicting CPU architectures %d/%d"),
91e22acd
AS		 13454 ibfd, oldtag, newtag);
13455 return -1;
13456 }
13457
13458 return result;
13459#undef T
8e79c3df
CM		 13460}
13461
ac56ee8f
MGD		 13462/* Query attributes object to see if integer divide instructions may be
13463 present in an object. */
13464static bfd_boolean
13465elf32_arm_attributes_accept_div (const obj_attribute *attr)
13466{
13467 int arch = attr[Tag_CPU_arch].i;
13468 int profile = attr[Tag_CPU_arch_profile].i;
13469
13470 switch (attr[Tag_DIV_use].i)
13471 {
13472 case 0:
13473 /* Integer divide allowed if instruction contained in archetecture. */
13474 if (arch == TAG_CPU_ARCH_V7 && (profile == 'R' || profile == 'M'))
13475 return TRUE;
13476 else if (arch >= TAG_CPU_ARCH_V7E_M)
13477 return TRUE;
13478 else
13479 return FALSE;
13480
13481 case 1:
13482 /* Integer divide explicitly prohibited. */
13483 return FALSE;
13484
13485 default:
13486 /* Unrecognised case - treat as allowing divide everywhere. */
13487 case 2:
13488 /* Integer divide allowed in ARM state. */
13489 return TRUE;
13490 }
13491}
13492
13493/* Query attributes object to see if integer divide instructions are
13494 forbidden to be in the object. This is not the inverse of
13495 elf32_arm_attributes_accept_div. */
13496static bfd_boolean
13497elf32_arm_attributes_forbid_div (const obj_attribute *attr)
13498{
13499 return attr[Tag_DIV_use].i == 1;
13500}
13501
ee065d83
PB		 13502/* Merge EABI object attributes from IBFD into OBFD. Raise an error if there
13503 are conflicting attributes. */
906e58ca 13504
ee065d83 13505static bfd_boolean
50e03d47 13506elf32_arm_merge_eabi_attributes (bfd *ibfd, struct bfd_link_info *info)
ee065d83 13507{
50e03d47 13508 bfd *obfd = info->output_bfd;
104d59d1
JM		 13509 obj_attribute *in_attr;
13510 obj_attribute *out_attr;
ee065d83
PB		 13511 /* Some tags have 0 = don't care, 1 = strong requirement,
13512 2 = weak requirement. */
91e22acd 13513 static const int order_021[3] = {0, 2, 1};
ee065d83 13514 int i;
91e22acd 13515 bfd_boolean result = TRUE;
9274e9de 13516 const char *sec_name = get_elf_backend_data (ibfd)->obj_attrs_section;
ee065d83 13517
3e6b1042
DJ		 13518 /* Skip the linker stubs file. This preserves previous behavior
13519 of accepting unknown attributes in the first input file - but
13520 is that a bug? */
13521 if (ibfd->flags & BFD_LINKER_CREATED)
13522 return TRUE;
13523
9274e9de
TG		 13524 /* Skip any input that hasn't attribute section.
13525 This enables to link object files without attribute section with
13526 any others. */
13527 if (bfd_get_section_by_name (ibfd, sec_name) == NULL)
13528 return TRUE;
13529
104d59d1 13530 if (!elf_known_obj_attributes_proc (obfd)[0].i)
ee065d83
PB		 13531 {
13532 /* This is the first object. Copy the attributes. */
104d59d1 13533 _bfd_elf_copy_obj_attributes (ibfd, obfd);
004ae526 13534
cd21e546
MGD		 13535 out_attr = elf_known_obj_attributes_proc (obfd);
13536
004ae526
PB		 13537 /* Use the Tag_null value to indicate the attributes have been
13538 initialized. */
cd21e546 13539 out_attr[0].i = 1;
004ae526 13540
cd21e546
MGD		 13541 /* We do not output objects with Tag_MPextension_use_legacy - we move
13542 the attribute's value to Tag_MPextension_use. */
13543 if (out_attr[Tag_MPextension_use_legacy].i != 0)
13544 {
13545 if (out_attr[Tag_MPextension_use].i != 0
13546 && out_attr[Tag_MPextension_use_legacy].i
99059e56 13547 != out_attr[Tag_MPextension_use].i)
cd21e546
MGD		 13548 {
13549 _bfd_error_handler
13550 (_("Error: %B has both the current and legacy "
13551 "Tag_MPextension_use attributes"), ibfd);
13552 result = FALSE;
13553 }
13554
13555 out_attr[Tag_MPextension_use] =
13556 out_attr[Tag_MPextension_use_legacy];
13557 out_attr[Tag_MPextension_use_legacy].type = 0;
13558 out_attr[Tag_MPextension_use_legacy].i = 0;
13559 }
13560
13561 return result;
ee065d83
PB		 13562 }
13563
104d59d1
JM		 13564 in_attr = elf_known_obj_attributes_proc (ibfd);
13565 out_attr = elf_known_obj_attributes_proc (obfd);
ee065d83
PB		 13566 /* This needs to happen before Tag_ABI_FP_number_model is merged. */
13567 if (in_attr[Tag_ABI_VFP_args].i != out_attr[Tag_ABI_VFP_args].i)
13568 {
5c294fee
TG		 13569 /* Ignore mismatches if the object doesn't use floating point or is
13570 floating point ABI independent. */
13571 if (out_attr[Tag_ABI_FP_number_model].i == AEABI_FP_number_model_none
13572 || (in_attr[Tag_ABI_FP_number_model].i != AEABI_FP_number_model_none
13573 && out_attr[Tag_ABI_VFP_args].i == AEABI_VFP_args_compatible))
ee065d83 13574 out_attr[Tag_ABI_VFP_args].i = in_attr[Tag_ABI_VFP_args].i;
5c294fee
TG		 13575 else if (in_attr[Tag_ABI_FP_number_model].i != AEABI_FP_number_model_none
13576 && in_attr[Tag_ABI_VFP_args].i != AEABI_VFP_args_compatible)
ee065d83
PB		 13577 {
13578 _bfd_error_handler
3895f852 13579 (_("error: %B uses VFP register arguments, %B does not"),
deddc40b
NS		 13580 in_attr[Tag_ABI_VFP_args].i ? ibfd : obfd,
13581 in_attr[Tag_ABI_VFP_args].i ? obfd : ibfd);
91e22acd 13582 result = FALSE;
ee065d83
PB		 13583 }
13584 }
13585
3de4a297 13586 for (i = LEAST_KNOWN_OBJ_ATTRIBUTE; i < NUM_KNOWN_OBJ_ATTRIBUTES; i++)
ee065d83
PB		 13587 {
13588 /* Merge this attribute with existing attributes. */
13589 switch (i)
13590 {
13591 case Tag_CPU_raw_name:
13592 case Tag_CPU_name:
6a631e86 13593 /* These are merged after Tag_CPU_arch. */
ee065d83
PB		 13594 break;
13595
13596 case Tag_ABI_optimization_goals:
13597 case Tag_ABI_FP_optimization_goals:
13598 /* Use the first value seen. */
13599 break;
13600
13601 case Tag_CPU_arch:
91e22acd
AS		 13602 {
13603 int secondary_compat = -1, secondary_compat_out = -1;
13604 unsigned int saved_out_attr = out_attr[i].i;
70e99720
TG		 13605 int arch_attr;
13606 static const char *name_table[] =
13607 {
91e22acd
AS		 13608 /* These aren't real CPU names, but we can't guess
13609 that from the architecture version alone. */
13610 "Pre v4",
13611 "ARM v4",
13612 "ARM v4T",
13613 "ARM v5T",
13614 "ARM v5TE",
13615 "ARM v5TEJ",
13616 "ARM v6",
13617 "ARM v6KZ",
13618 "ARM v6T2",
13619 "ARM v6K",
13620 "ARM v7",
13621 "ARM v6-M",
bca38921 13622 "ARM v6S-M",
2fd158eb
TP		 13623 "ARM v8",
13624 "",
13625 "ARM v8-M.baseline",
13626 "ARM v8-M.mainline",
91e22acd
AS		 13627 };
13628
13629 /* Merge Tag_CPU_arch and Tag_also_compatible_with. */
13630 secondary_compat = get_secondary_compatible_arch (ibfd);
13631 secondary_compat_out = get_secondary_compatible_arch (obfd);
70e99720
TG		 13632 arch_attr = tag_cpu_arch_combine (ibfd, out_attr[i].i,
13633 &secondary_compat_out,
13634 in_attr[i].i,
13635 secondary_compat);
13636
13637 /* Return with error if failed to merge. */
13638 if (arch_attr == -1)
13639 return FALSE;
13640
13641 out_attr[i].i = arch_attr;
13642
91e22acd
AS		 13643 set_secondary_compatible_arch (obfd, secondary_compat_out);
13644
13645 /* Merge Tag_CPU_name and Tag_CPU_raw_name. */
13646 if (out_attr[i].i == saved_out_attr)
13647 ; /* Leave the names alone. */
13648 else if (out_attr[i].i == in_attr[i].i)
13649 {
13650 /* The output architecture has been changed to match the
13651 input architecture. Use the input names. */
13652 out_attr[Tag_CPU_name].s = in_attr[Tag_CPU_name].s
13653 ? _bfd_elf_attr_strdup (obfd, in_attr[Tag_CPU_name].s)
13654 : NULL;
13655 out_attr[Tag_CPU_raw_name].s = in_attr[Tag_CPU_raw_name].s
13656 ? _bfd_elf_attr_strdup (obfd, in_attr[Tag_CPU_raw_name].s)
13657 : NULL;
13658 }
13659 else
13660 {
13661 out_attr[Tag_CPU_name].s = NULL;
13662 out_attr[Tag_CPU_raw_name].s = NULL;
13663 }
13664
13665 /* If we still don't have a value for Tag_CPU_name,
13666 make one up now. Tag_CPU_raw_name remains blank. */
13667 if (out_attr[Tag_CPU_name].s == NULL
13668 && out_attr[i].i < ARRAY_SIZE (name_table))
13669 out_attr[Tag_CPU_name].s =
13670 _bfd_elf_attr_strdup (obfd, name_table[out_attr[i].i]);
13671 }
13672 break;
13673
ee065d83
PB		 13674 case Tag_ARM_ISA_use:
13675 case Tag_THUMB_ISA_use:
ee065d83 13676 case Tag_WMMX_arch:
91e22acd
AS		 13677 case Tag_Advanced_SIMD_arch:
13678 /* ??? Do Advanced_SIMD (NEON) and WMMX conflict? */
ee065d83 13679 case Tag_ABI_FP_rounding:
ee065d83
PB		 13680 case Tag_ABI_FP_exceptions:
13681 case Tag_ABI_FP_user_exceptions:
13682 case Tag_ABI_FP_number_model:
75375b3e 13683 case Tag_FP_HP_extension:
91e22acd
AS		 13684 case Tag_CPU_unaligned_access:
13685 case Tag_T2EE_use:
91e22acd 13686 case Tag_MPextension_use:
ee065d83
PB		 13687 /* Use the largest value specified. */
13688 if (in_attr[i].i > out_attr[i].i)
13689 out_attr[i].i = in_attr[i].i;
13690 break;
13691
75375b3e 13692 case Tag_ABI_align_preserved:
91e22acd
AS		 13693 case Tag_ABI_PCS_RO_data:
13694 /* Use the smallest value specified. */
13695 if (in_attr[i].i < out_attr[i].i)
13696 out_attr[i].i = in_attr[i].i;
13697 break;
13698
75375b3e 13699 case Tag_ABI_align_needed:
91e22acd 13700 if ((in_attr[i].i > 0 || out_attr[i].i > 0)
75375b3e
MGD		 13701 && (in_attr[Tag_ABI_align_preserved].i == 0
13702 || out_attr[Tag_ABI_align_preserved].i == 0))
ee065d83 13703 {
91e22acd
AS		 13704 /* This error message should be enabled once all non-conformant
13705 binaries in the toolchain have had the attributes set
13706 properly.
ee065d83 13707 _bfd_error_handler
3895f852 13708 (_("error: %B: 8-byte data alignment conflicts with %B"),
91e22acd
AS		 13709 obfd, ibfd);
13710 result = FALSE; */
ee065d83 13711 }
91e22acd
AS		 13712 /* Fall through. */
13713 case Tag_ABI_FP_denormal:
13714 case Tag_ABI_PCS_GOT_use:
13715 /* Use the "greatest" from the sequence 0, 2, 1, or the largest
13716 value if greater than 2 (for future-proofing). */
13717 if ((in_attr[i].i > 2 && in_attr[i].i > out_attr[i].i)
13718 || (in_attr[i].i <= 2 && out_attr[i].i <= 2
13719 && order_021[in_attr[i].i] > order_021[out_attr[i].i]))
ee065d83
PB		 13720 out_attr[i].i = in_attr[i].i;
13721 break;
91e22acd 13722
75375b3e
MGD		 13723 case Tag_Virtualization_use:
13724 /* The virtualization tag effectively stores two bits of
13725 information: the intended use of TrustZone (in bit 0), and the
13726 intended use of Virtualization (in bit 1). */
13727 if (out_attr[i].i == 0)
13728 out_attr[i].i = in_attr[i].i;
13729 else if (in_attr[i].i != 0
13730 && in_attr[i].i != out_attr[i].i)
13731 {
13732 if (in_attr[i].i <= 3 && out_attr[i].i <= 3)
13733 out_attr[i].i = 3;
13734 else
13735 {
13736 _bfd_error_handler
13737 (_("error: %B: unable to merge virtualization attributes "
13738 "with %B"),
13739 obfd, ibfd);
13740 result = FALSE;
13741 }
13742 }
13743 break;
91e22acd
AS		 13744
13745 case Tag_CPU_arch_profile:
13746 if (out_attr[i].i != in_attr[i].i)
13747 {
13748 /* 0 will merge with anything.
13749 'A' and 'S' merge to 'A'.
13750 'R' and 'S' merge to 'R'.
99059e56 13751 'M' and 'A|R|S' is an error. */
91e22acd
AS		 13752 if (out_attr[i].i == 0
13753 || (out_attr[i].i == 'S'
13754 && (in_attr[i].i == 'A' || in_attr[i].i == 'R')))
13755 out_attr[i].i = in_attr[i].i;
13756 else if (in_attr[i].i == 0
13757 || (in_attr[i].i == 'S'
13758 && (out_attr[i].i == 'A' || out_attr[i].i == 'R')))
6a631e86 13759 ; /* Do nothing. */
91e22acd
AS		 13760 else
13761 {
13762 _bfd_error_handler
3895f852 13763 (_("error: %B: Conflicting architecture profiles %c/%c"),
91e22acd
AS		 13764 ibfd,
13765 in_attr[i].i ? in_attr[i].i : '0',
13766 out_attr[i].i ? out_attr[i].i : '0');
13767 result = FALSE;
13768 }
13769 }
13770 break;
15afaa63
TP		 13771
13772 case Tag_DSP_extension:
13773 /* No need to change output value if any of:
13774 - pre (<=) ARMv5T input architecture (do not have DSP)
13775 - M input profile not ARMv7E-M and do not have DSP. */
13776 if (in_attr[Tag_CPU_arch].i <= 3
13777 || (in_attr[Tag_CPU_arch_profile].i == 'M'
13778 && in_attr[Tag_CPU_arch].i != 13
13779 && in_attr[i].i == 0))
13780 ; /* Do nothing. */
13781 /* Output value should be 0 if DSP part of architecture, ie.
13782 - post (>=) ARMv5te architecture output
13783 - A, R or S profile output or ARMv7E-M output architecture. */
13784 else if (out_attr[Tag_CPU_arch].i >= 4
13785 && (out_attr[Tag_CPU_arch_profile].i == 'A'
13786 || out_attr[Tag_CPU_arch_profile].i == 'R'
13787 || out_attr[Tag_CPU_arch_profile].i == 'S'
13788 || out_attr[Tag_CPU_arch].i == 13))
13789 out_attr[i].i = 0;
13790 /* Otherwise, DSP instructions are added and not part of output
13791 architecture. */
13792 else
13793 out_attr[i].i = 1;
13794 break;
13795
75375b3e 13796 case Tag_FP_arch:
62f3b8c8 13797 {
4547cb56
NC		 13798 /* Tag_ABI_HardFP_use is handled along with Tag_FP_arch since
13799 the meaning of Tag_ABI_HardFP_use depends on Tag_FP_arch
13800 when it's 0. It might mean absence of FP hardware if
99654aaf 13801 Tag_FP_arch is zero. */
4547cb56 13802
a715796b 13803#define VFP_VERSION_COUNT 9
62f3b8c8
PB		 13804 static const struct
13805 {
13806 int ver;
13807 int regs;
bca38921 13808 } vfp_versions[VFP_VERSION_COUNT] =
62f3b8c8
PB		 13809 {
13810 {0, 0},
13811 {1, 16},
13812 {2, 16},
13813 {3, 32},
13814 {3, 16},
13815 {4, 32},
bca38921 13816 {4, 16},
a715796b
TG		 13817 {8, 32},
13818 {8, 16}
62f3b8c8
PB		 13819 };
13820 int ver;
13821 int regs;
13822 int newval;
13823
4547cb56
NC		 13824 /* If the output has no requirement about FP hardware,
13825 follow the requirement of the input. */
13826 if (out_attr[i].i == 0)
13827 {
13828 BFD_ASSERT (out_attr[Tag_ABI_HardFP_use].i == 0);
13829 out_attr[i].i = in_attr[i].i;
13830 out_attr[Tag_ABI_HardFP_use].i
13831 = in_attr[Tag_ABI_HardFP_use].i;
13832 break;
13833 }
13834 /* If the input has no requirement about FP hardware, do
13835 nothing. */
13836 else if (in_attr[i].i == 0)
13837 {
13838 BFD_ASSERT (in_attr[Tag_ABI_HardFP_use].i == 0);
13839 break;
13840 }
13841
13842 /* Both the input and the output have nonzero Tag_FP_arch.
99654aaf 13843 So Tag_ABI_HardFP_use is implied by Tag_FP_arch when it's zero. */
4547cb56
NC		 13844
13845 /* If both the input and the output have zero Tag_ABI_HardFP_use,
13846 do nothing. */
13847 if (in_attr[Tag_ABI_HardFP_use].i == 0
13848 && out_attr[Tag_ABI_HardFP_use].i == 0)
13849 ;
13850 /* If the input and the output have different Tag_ABI_HardFP_use,
99654aaf 13851 the combination of them is 0 (implied by Tag_FP_arch). */
4547cb56
NC		 13852 else if (in_attr[Tag_ABI_HardFP_use].i
13853 != out_attr[Tag_ABI_HardFP_use].i)
99654aaf 13854 out_attr[Tag_ABI_HardFP_use].i = 0;
4547cb56
NC		 13855
13856 /* Now we can handle Tag_FP_arch. */
13857
bca38921
MGD		 13858 /* Values of VFP_VERSION_COUNT or more aren't defined, so just
13859 pick the biggest. */
13860 if (in_attr[i].i >= VFP_VERSION_COUNT
13861 && in_attr[i].i > out_attr[i].i)
62f3b8c8
PB		 13862 {
13863 out_attr[i] = in_attr[i];
13864 break;
13865 }
13866 /* The output uses the superset of input features
13867 (ISA version) and registers. */
13868 ver = vfp_versions[in_attr[i].i].ver;
13869 if (ver < vfp_versions[out_attr[i].i].ver)
13870 ver = vfp_versions[out_attr[i].i].ver;
13871 regs = vfp_versions[in_attr[i].i].regs;
13872 if (regs < vfp_versions[out_attr[i].i].regs)
13873 regs = vfp_versions[out_attr[i].i].regs;
13874 /* This assumes all possible supersets are also a valid
99059e56 13875 options. */
bca38921 13876 for (newval = VFP_VERSION_COUNT - 1; newval > 0; newval--)
62f3b8c8
PB		 13877 {
13878 if (regs == vfp_versions[newval].regs
13879 && ver == vfp_versions[newval].ver)
13880 break;
13881 }
13882 out_attr[i].i = newval;
13883 }
b1cc4aeb 13884 break;
ee065d83
PB		 13885 case Tag_PCS_config:
13886 if (out_attr[i].i == 0)
13887 out_attr[i].i = in_attr[i].i;
b6009aca 13888 else if (in_attr[i].i != 0 && out_attr[i].i != in_attr[i].i)
ee065d83
PB		 13889 {
13890 /* It's sometimes ok to mix different configs, so this is only
99059e56 13891 a warning. */
ee065d83
PB		 13892 _bfd_error_handler
13893 (_("Warning: %B: Conflicting platform configuration"), ibfd);
13894 }
13895 break;
13896 case Tag_ABI_PCS_R9_use:
004ae526
PB		 13897 if (in_attr[i].i != out_attr[i].i
13898 && out_attr[i].i != AEABI_R9_unused
ee065d83
PB		 13899 && in_attr[i].i != AEABI_R9_unused)
13900 {
13901 _bfd_error_handler
3895f852 13902 (_("error: %B: Conflicting use of R9"), ibfd);
91e22acd 13903 result = FALSE;
ee065d83
PB		 13904 }
13905 if (out_attr[i].i == AEABI_R9_unused)
13906 out_attr[i].i = in_attr[i].i;
13907 break;
13908 case Tag_ABI_PCS_RW_data:
13909 if (in_attr[i].i == AEABI_PCS_RW_data_SBrel
13910 && out_attr[Tag_ABI_PCS_R9_use].i != AEABI_R9_SB
13911 && out_attr[Tag_ABI_PCS_R9_use].i != AEABI_R9_unused)
13912 {
13913 _bfd_error_handler
3895f852 13914 (_("error: %B: SB relative addressing conflicts with use of R9"),
ee065d83 13915 ibfd);
91e22acd 13916 result = FALSE;
ee065d83
PB		 13917 }
13918 /* Use the smallest value specified. */
13919 if (in_attr[i].i < out_attr[i].i)
13920 out_attr[i].i = in_attr[i].i;
13921 break;
ee065d83 13922 case Tag_ABI_PCS_wchar_t:
a9dc9481
JM		 13923 if (out_attr[i].i && in_attr[i].i && out_attr[i].i != in_attr[i].i
13924 && !elf_arm_tdata (obfd)->no_wchar_size_warning)
ee065d83
PB		 13925 {
13926 _bfd_error_handler
a9dc9481
JM		 13927 (_("warning: %B uses %u-byte wchar_t yet the output is to use %u-byte wchar_t; use of wchar_t values across objects may fail"),
13928 ibfd, in_attr[i].i, out_attr[i].i);
ee065d83 13929 }
a9dc9481 13930 else if (in_attr[i].i && !out_attr[i].i)
ee065d83
PB		 13931 out_attr[i].i = in_attr[i].i;
13932 break;
ee065d83
PB		 13933 case Tag_ABI_enum_size:
13934 if (in_attr[i].i != AEABI_enum_unused)
13935 {
13936 if (out_attr[i].i == AEABI_enum_unused
13937 || out_attr[i].i == AEABI_enum_forced_wide)
13938 {
13939 /* The existing object is compatible with anything.
13940 Use whatever requirements the new object has. */
13941 out_attr[i].i = in_attr[i].i;
13942 }
13943 else if (in_attr[i].i != AEABI_enum_forced_wide
bf21ed78 13944 && out_attr[i].i != in_attr[i].i
0ffa91dd 13945 && !elf_arm_tdata (obfd)->no_enum_size_warning)
ee065d83 13946 {
91e22acd 13947 static const char *aeabi_enum_names[] =
bf21ed78 13948 { "", "variable-size", "32-bit", "" };
91e22acd
AS		 13949 const char *in_name =
13950 in_attr[i].i < ARRAY_SIZE(aeabi_enum_names)
13951 ? aeabi_enum_names[in_attr[i].i]
13952 : "<unknown>";
13953 const char *out_name =
13954 out_attr[i].i < ARRAY_SIZE(aeabi_enum_names)
13955 ? aeabi_enum_names[out_attr[i].i]
13956 : "<unknown>";
ee065d83 13957 _bfd_error_handler
bf21ed78 13958 (_("warning: %B uses %s enums yet the output is to use %s enums; use of enum values across objects may fail"),
91e22acd 13959 ibfd, in_name, out_name);
ee065d83
PB		 13960 }
13961 }
13962 break;
13963 case Tag_ABI_VFP_args:
13964 /* Aready done. */
13965 break;
13966 case Tag_ABI_WMMX_args:
13967 if (in_attr[i].i != out_attr[i].i)
13968 {
13969 _bfd_error_handler
3895f852 13970 (_("error: %B uses iWMMXt register arguments, %B does not"),
ee065d83 13971 ibfd, obfd);
91e22acd 13972 result = FALSE;
ee065d83
PB		 13973 }
13974 break;
7b86a9fa
AS		 13975 case Tag_compatibility:
13976 /* Merged in target-independent code. */
13977 break;
91e22acd 13978 case Tag_ABI_HardFP_use:
4547cb56 13979 /* This is handled along with Tag_FP_arch. */
91e22acd
AS		 13980 break;
13981 case Tag_ABI_FP_16bit_format:
13982 if (in_attr[i].i != 0 && out_attr[i].i != 0)
13983 {
13984 if (in_attr[i].i != out_attr[i].i)
13985 {
13986 _bfd_error_handler
3895f852 13987 (_("error: fp16 format mismatch between %B and %B"),
91e22acd
AS		 13988 ibfd, obfd);
13989 result = FALSE;
13990 }
13991 }
13992 if (in_attr[i].i != 0)
13993 out_attr[i].i = in_attr[i].i;
13994 break;
7b86a9fa 13995
cd21e546 13996 case Tag_DIV_use:
ac56ee8f
MGD		 13997 /* A value of zero on input means that the divide instruction may
13998 be used if available in the base architecture as specified via
13999 Tag_CPU_arch and Tag_CPU_arch_profile. A value of 1 means that
14000 the user did not want divide instructions. A value of 2
14001 explicitly means that divide instructions were allowed in ARM
14002 and Thumb state. */
14003 if (in_attr[i].i == out_attr[i].i)
14004 /* Do nothing. */ ;
14005 else if (elf32_arm_attributes_forbid_div (in_attr)
14006 && !elf32_arm_attributes_accept_div (out_attr))
14007 out_attr[i].i = 1;
14008 else if (elf32_arm_attributes_forbid_div (out_attr)
14009 && elf32_arm_attributes_accept_div (in_attr))
14010 out_attr[i].i = in_attr[i].i;
14011 else if (in_attr[i].i == 2)
14012 out_attr[i].i = in_attr[i].i;
cd21e546
MGD		 14013 break;
14014
14015 case Tag_MPextension_use_legacy:
14016 /* We don't output objects with Tag_MPextension_use_legacy - we
14017 move the value to Tag_MPextension_use. */
14018 if (in_attr[i].i != 0 && in_attr[Tag_MPextension_use].i != 0)
14019 {
14020 if (in_attr[Tag_MPextension_use].i != in_attr[i].i)
14021 {
14022 _bfd_error_handler
14023 (_("%B has has both the current and legacy "
b38cadfb 14024 "Tag_MPextension_use attributes"),
cd21e546
MGD		 14025 ibfd);
14026 result = FALSE;
14027 }
14028 }
14029
14030 if (in_attr[i].i > out_attr[Tag_MPextension_use].i)
14031 out_attr[Tag_MPextension_use] = in_attr[i];
14032
14033 break;
14034
91e22acd 14035 case Tag_nodefaults:
2d0bb761
AS		 14036 /* This tag is set if it exists, but the value is unused (and is
14037 typically zero). We don't actually need to do anything here -
14038 the merge happens automatically when the type flags are merged
14039 below. */
91e22acd
AS		 14040 break;
14041 case Tag_also_compatible_with:
14042 /* Already done in Tag_CPU_arch. */
14043 break;
14044 case Tag_conformance:
14045 /* Keep the attribute if it matches. Throw it away otherwise.
14046 No attribute means no claim to conform. */
14047 if (!in_attr[i].s || !out_attr[i].s
14048 || strcmp (in_attr[i].s, out_attr[i].s) != 0)
14049 out_attr[i].s = NULL;
14050 break;
3cfad14c 14051
91e22acd 14052 default:
e8b36cd1
JM		 14053 result
14054 = result && _bfd_elf_merge_unknown_attribute_low (ibfd, obfd, i);
91e22acd
AS		 14055 }
14056
14057 /* If out_attr was copied from in_attr then it won't have a type yet. */
14058 if (in_attr[i].type && !out_attr[i].type)
14059 out_attr[i].type = in_attr[i].type;
ee065d83
PB		 14060 }
14061
104d59d1 14062 /* Merge Tag_compatibility attributes and any common GNU ones. */
50e03d47 14063 if (!_bfd_elf_merge_object_attributes (ibfd, info))
5488d830 14064 return FALSE;
ee065d83 14065
104d59d1 14066 /* Check for any attributes not known on ARM. */
e8b36cd1 14067 result &= _bfd_elf_merge_unknown_attribute_list (ibfd, obfd);
91e22acd 14068
91e22acd 14069 return result;
252b5132
RH		 14070}
14071
3a4a14e9
PB		 14072
14073/* Return TRUE if the two EABI versions are incompatible. */
14074
14075static bfd_boolean
14076elf32_arm_versions_compatible (unsigned iver, unsigned over)
14077{
14078 /* v4 and v5 are the same spec before and after it was released,
14079 so allow mixing them. */
14080 if ((iver == EF_ARM_EABI_VER4 && over == EF_ARM_EABI_VER5)
14081 || (iver == EF_ARM_EABI_VER5 && over == EF_ARM_EABI_VER4))
14082 return TRUE;
14083
14084 return (iver == over);
14085}
14086
252b5132
RH		 14087/* Merge backend specific data from an object file to the output
14088 object file when linking. */
9b485d32 14089
b34976b6 14090static bfd_boolean
50e03d47 14091elf32_arm_merge_private_bfd_data (bfd *, struct bfd_link_info *);
252b5132 14092
9b485d32
NC		 14093/* Display the flags field. */
14094
b34976b6 14095static bfd_boolean
57e8b36a 14096elf32_arm_print_private_bfd_data (bfd *abfd, void * ptr)
252b5132 14097{
fc830a83
NC		 14098 FILE * file = (FILE *) ptr;
14099 unsigned long flags;
252b5132
RH		 14100
14101 BFD_ASSERT (abfd != NULL && ptr != NULL);
14102
14103 /* Print normal ELF private data. */
14104 _bfd_elf_print_private_bfd_data (abfd, ptr);
14105
fc830a83 14106 flags = elf_elfheader (abfd)->e_flags;
9b485d32
NC		 14107 /* Ignore init flag - it may not be set, despite the flags field
14108 containing valid data. */
252b5132 14109
9b485d32 14110 fprintf (file, _("private flags = %lx:"), elf_elfheader (abfd)->e_flags);
252b5132 14111
fc830a83
NC		 14112 switch (EF_ARM_EABI_VERSION (flags))
14113 {
14114 case EF_ARM_EABI_UNKNOWN:
4cc11e76 14115 /* The following flag bits are GNU extensions and not part of the
fc830a83
NC		 14116 official ARM ELF extended ABI. Hence they are only decoded if
14117 the EABI version is not set. */
fd2ec330 14118 if (flags & EF_ARM_INTERWORK)
9b485d32 14119 fprintf (file, _(" [interworking enabled]"));
9a5aca8c 14120
fd2ec330 14121 if (flags & EF_ARM_APCS_26)
6c571f00 14122 fprintf (file, " [APCS-26]");
fc830a83 14123 else
6c571f00 14124 fprintf (file, " [APCS-32]");
9a5aca8c 14125
96a846ea
RE		 14126 if (flags & EF_ARM_VFP_FLOAT)
14127 fprintf (file, _(" [VFP float format]"));
fde78edd
NC		 14128 else if (flags & EF_ARM_MAVERICK_FLOAT)
14129 fprintf (file, _(" [Maverick float format]"));
96a846ea
RE		 14130 else
14131 fprintf (file, _(" [FPA float format]"));
14132
fd2ec330 14133 if (flags & EF_ARM_APCS_FLOAT)
9b485d32 14134 fprintf (file, _(" [floats passed in float registers]"));
9a5aca8c 14135
fd2ec330 14136 if (flags & EF_ARM_PIC)
9b485d32 14137 fprintf (file, _(" [position independent]"));
fc830a83 14138
fd2ec330 14139 if (flags & EF_ARM_NEW_ABI)
9b485d32 14140 fprintf (file, _(" [new ABI]"));
9a5aca8c 14141
fd2ec330 14142 if (flags & EF_ARM_OLD_ABI)
9b485d32 14143 fprintf (file, _(" [old ABI]"));
9a5aca8c 14144
fd2ec330 14145 if (flags & EF_ARM_SOFT_FLOAT)
9b485d32 14146 fprintf (file, _(" [software FP]"));
9a5aca8c 14147
96a846ea
RE		 14148 flags &= ~(EF_ARM_INTERWORK | EF_ARM_APCS_26 | EF_ARM_APCS_FLOAT
14149 | EF_ARM_PIC | EF_ARM_NEW_ABI | EF_ARM_OLD_ABI
fde78edd
NC		 14150 | EF_ARM_SOFT_FLOAT | EF_ARM_VFP_FLOAT
14151 | EF_ARM_MAVERICK_FLOAT);
fc830a83 14152 break;
9a5aca8c 14153
fc830a83 14154 case EF_ARM_EABI_VER1:
9b485d32 14155 fprintf (file, _(" [Version1 EABI]"));
9a5aca8c 14156
fc830a83 14157 if (flags & EF_ARM_SYMSARESORTED)
9b485d32 14158 fprintf (file, _(" [sorted symbol table]"));
fc830a83 14159 else
9b485d32 14160 fprintf (file, _(" [unsorted symbol table]"));
9a5aca8c 14161
fc830a83
NC		 14162 flags &= ~ EF_ARM_SYMSARESORTED;
14163 break;
9a5aca8c 14164
fd2ec330
PB		 14165 case EF_ARM_EABI_VER2:
14166 fprintf (file, _(" [Version2 EABI]"));
14167
14168 if (flags & EF_ARM_SYMSARESORTED)
14169 fprintf (file, _(" [sorted symbol table]"));
14170 else
14171 fprintf (file, _(" [unsorted symbol table]"));
14172
14173 if (flags & EF_ARM_DYNSYMSUSESEGIDX)
14174 fprintf (file, _(" [dynamic symbols use segment index]"));
14175
14176 if (flags & EF_ARM_MAPSYMSFIRST)
14177 fprintf (file, _(" [mapping symbols precede others]"));
14178
99e4ae17 14179 flags &= ~(EF_ARM_SYMSARESORTED | EF_ARM_DYNSYMSUSESEGIDX
fd2ec330
PB		 14180 | EF_ARM_MAPSYMSFIRST);
14181 break;
14182
d507cf36
PB		 14183 case EF_ARM_EABI_VER3:
14184 fprintf (file, _(" [Version3 EABI]"));
8cb51566
PB		 14185 break;
14186
14187 case EF_ARM_EABI_VER4:
14188 fprintf (file, _(" [Version4 EABI]"));
3a4a14e9 14189 goto eabi;
d507cf36 14190
3a4a14e9
PB		 14191 case EF_ARM_EABI_VER5:
14192 fprintf (file, _(" [Version5 EABI]"));
3bfcb652
NC		 14193
14194 if (flags & EF_ARM_ABI_FLOAT_SOFT)
14195 fprintf (file, _(" [soft-float ABI]"));
14196
14197 if (flags & EF_ARM_ABI_FLOAT_HARD)
14198 fprintf (file, _(" [hard-float ABI]"));
14199
14200 flags &= ~(EF_ARM_ABI_FLOAT_SOFT | EF_ARM_ABI_FLOAT_HARD);
14201
3a4a14e9 14202 eabi:
d507cf36
PB		 14203 if (flags & EF_ARM_BE8)
14204 fprintf (file, _(" [BE8]"));
14205
14206 if (flags & EF_ARM_LE8)
14207 fprintf (file, _(" [LE8]"));
14208
14209 flags &= ~(EF_ARM_LE8 | EF_ARM_BE8);
14210 break;
14211
fc830a83 14212 default:
9b485d32 14213 fprintf (file, _(" <EABI version unrecognised>"));
fc830a83
NC		 14214 break;
14215 }
252b5132 14216
fc830a83 14217 flags &= ~ EF_ARM_EABIMASK;
252b5132 14218
fc830a83 14219 if (flags & EF_ARM_RELEXEC)
9b485d32 14220 fprintf (file, _(" [relocatable executable]"));
252b5132 14221
a5721edd 14222 flags &= ~EF_ARM_RELEXEC;
fc830a83
NC		 14223
14224 if (flags)
9b485d32 14225 fprintf (file, _("<Unrecognised flag bits set>"));
9a5aca8c 14226
252b5132
RH		 14227 fputc ('\n', file);
14228
b34976b6 14229 return TRUE;
252b5132
RH		 14230}
14231
14232static int
57e8b36a 14233elf32_arm_get_symbol_type (Elf_Internal_Sym * elf_sym, int type)
252b5132 14234{
2f0ca46a
NC		 14235 switch (ELF_ST_TYPE (elf_sym->st_info))
14236 {
14237 case STT_ARM_TFUNC:
14238 return ELF_ST_TYPE (elf_sym->st_info);
ce855c42 14239
2f0ca46a
NC		 14240 case STT_ARM_16BIT:
14241 /* If the symbol is not an object, return the STT_ARM_16BIT flag.
14242 This allows us to distinguish between data used by Thumb instructions
14243 and non-data (which is probably code) inside Thumb regions of an
14244 executable. */
1a0eb693 14245 if (type != STT_OBJECT && type != STT_TLS)
2f0ca46a
NC		 14246 return ELF_ST_TYPE (elf_sym->st_info);
14247 break;
9a5aca8c 14248
ce855c42
NC		 14249 default:
14250 break;
2f0ca46a
NC		 14251 }
14252
14253 return type;
252b5132 14254}
f21f3fe0 14255
252b5132 14256static asection *
07adf181
AM		 14257elf32_arm_gc_mark_hook (asection *sec,
14258 struct bfd_link_info *info,
14259 Elf_Internal_Rela *rel,
14260 struct elf_link_hash_entry *h,
14261 Elf_Internal_Sym *sym)
252b5132
RH		 14262{
14263 if (h != NULL)
07adf181 14264 switch (ELF32_R_TYPE (rel->r_info))
252b5132
RH		 14265 {
14266 case R_ARM_GNU_VTINHERIT:
14267 case R_ARM_GNU_VTENTRY:
07adf181
AM		 14268 return NULL;
14269 }
9ad5cbcf 14270
07adf181 14271 return _bfd_elf_gc_mark_hook (sec, info, rel, h, sym);
252b5132
RH		 14272}
14273
780a67af
NC		 14274/* Update the got entry reference counts for the section being removed. */
14275
b34976b6 14276static bfd_boolean
ba93b8ac
DJ		 14277elf32_arm_gc_sweep_hook (bfd * abfd,
14278 struct bfd_link_info * info,
14279 asection * sec,
14280 const Elf_Internal_Rela * relocs)
252b5132 14281{
5e681ec4
PB		 14282 Elf_Internal_Shdr *symtab_hdr;
14283 struct elf_link_hash_entry **sym_hashes;
14284 bfd_signed_vma *local_got_refcounts;
14285 const Elf_Internal_Rela *rel, *relend;
eb043451
PB		 14286 struct elf32_arm_link_hash_table * globals;
14287
0e1862bb 14288 if (bfd_link_relocatable (info))
7dda2462
TG		 14289 return TRUE;
14290
eb043451 14291 globals = elf32_arm_hash_table (info);
4dfe6ac6
NC		 14292 if (globals == NULL)
14293 return FALSE;
5e681ec4
PB		 14294
14295 elf_section_data (sec)->local_dynrel = NULL;
14296
0ffa91dd 14297 symtab_hdr = & elf_symtab_hdr (abfd);
5e681ec4
PB		 14298 sym_hashes = elf_sym_hashes (abfd);
14299 local_got_refcounts = elf_local_got_refcounts (abfd);
14300
906e58ca 14301 check_use_blx (globals);
bd97cb95 14302
5e681ec4
PB		 14303 relend = relocs + sec->reloc_count;
14304 for (rel = relocs; rel < relend; rel++)
eb043451 14305 {
3eb128b2
AM		 14306 unsigned long r_symndx;
14307 struct elf_link_hash_entry *h = NULL;
f6e32f6d 14308 struct elf32_arm_link_hash_entry *eh;
eb043451 14309 int r_type;
34e77a92 14310 bfd_boolean call_reloc_p;
f6e32f6d
RS		 14311 bfd_boolean may_become_dynamic_p;
14312 bfd_boolean may_need_local_target_p;
34e77a92
RS		 14313 union gotplt_union *root_plt;
14314 struct arm_plt_info *arm_plt;
5e681ec4 14315
3eb128b2
AM		 14316 r_symndx = ELF32_R_SYM (rel->r_info);
14317 if (r_symndx >= symtab_hdr->sh_info)
14318 {
14319 h = sym_hashes[r_symndx - symtab_hdr->sh_info];
14320 while (h->root.type == bfd_link_hash_indirect
14321 || h->root.type == bfd_link_hash_warning)
14322 h = (struct elf_link_hash_entry *) h->root.u.i.link;
14323 }
f6e32f6d
RS		 14324 eh = (struct elf32_arm_link_hash_entry *) h;
14325
34e77a92 14326 call_reloc_p = FALSE;
f6e32f6d
RS		 14327 may_become_dynamic_p = FALSE;
14328 may_need_local_target_p = FALSE;
3eb128b2 14329
eb043451 14330 r_type = ELF32_R_TYPE (rel->r_info);
eb043451 14331 r_type = arm_real_reloc_type (globals, r_type);
eb043451
PB		 14332 switch (r_type)
14333 {
14334 case R_ARM_GOT32:
eb043451 14335 case R_ARM_GOT_PREL:
ba93b8ac
DJ		 14336 case R_ARM_TLS_GD32:
14337 case R_ARM_TLS_IE32:
3eb128b2 14338 if (h != NULL)
eb043451 14339 {
eb043451
PB		 14340 if (h->got.refcount > 0)
14341 h->got.refcount -= 1;
14342 }
14343 else if (local_got_refcounts != NULL)
14344 {
14345 if (local_got_refcounts[r_symndx] > 0)
14346 local_got_refcounts[r_symndx] -= 1;
14347 }
14348 break;
14349
ba93b8ac 14350 case R_ARM_TLS_LDM32:
4dfe6ac6 14351 globals->tls_ldm_got.refcount -= 1;
ba93b8ac
DJ		 14352 break;
14353
eb043451
PB		 14354 case R_ARM_PC24:
14355 case R_ARM_PLT32:
5b5bb741
PB		 14356 case R_ARM_CALL:
14357 case R_ARM_JUMP24:
eb043451 14358 case R_ARM_PREL31:
c19d1205 14359 case R_ARM_THM_CALL:
bd97cb95
DJ		 14360 case R_ARM_THM_JUMP24:
14361 case R_ARM_THM_JUMP19:
34e77a92 14362 call_reloc_p = TRUE;
f6e32f6d
RS		 14363 may_need_local_target_p = TRUE;
14364 break;
14365
14366 case R_ARM_ABS12:
14367 if (!globals->vxworks_p)
14368 {
14369 may_need_local_target_p = TRUE;
14370 break;
14371 }
14372 /* Fall through. */
14373 case R_ARM_ABS32:
14374 case R_ARM_ABS32_NOI:
14375 case R_ARM_REL32:
14376 case R_ARM_REL32_NOI:
b6895b4f
PB		 14377 case R_ARM_MOVW_ABS_NC:
14378 case R_ARM_MOVT_ABS:
14379 case R_ARM_MOVW_PREL_NC:
14380 case R_ARM_MOVT_PREL:
14381 case R_ARM_THM_MOVW_ABS_NC:
14382 case R_ARM_THM_MOVT_ABS:
14383 case R_ARM_THM_MOVW_PREL_NC:
14384 case R_ARM_THM_MOVT_PREL:
b7693d02 14385 /* Should the interworking branches be here also? */
0e1862bb 14386 if ((bfd_link_pic (info) || globals->root.is_relocatable_executable)
34e77a92
RS		 14387 && (sec->flags & SEC_ALLOC) != 0)
14388 {
14389 if (h == NULL
469a3493 14390 && elf32_arm_howto_from_type (r_type)->pc_relative)
34e77a92
RS		 14391 {
14392 call_reloc_p = TRUE;
14393 may_need_local_target_p = TRUE;
14394 }
14395 else
14396 may_become_dynamic_p = TRUE;
14397 }
f6e32f6d
RS		 14398 else
14399 may_need_local_target_p = TRUE;
14400 break;
b7693d02 14401
f6e32f6d
RS		 14402 default:
14403 break;
14404 }
5e681ec4 14405
34e77a92 14406 if (may_need_local_target_p
4ba2ef8f
TP		 14407 && elf32_arm_get_plt_info (abfd, globals, eh, r_symndx, &root_plt,
14408 &arm_plt))
f6e32f6d 14409 {
27586251
HPN		 14410 /* If PLT refcount book-keeping is wrong and too low, we'll
14411 see a zero value (going to -1) for the root PLT reference
14412 count. */
14413 if (root_plt->refcount >= 0)
14414 {
14415 BFD_ASSERT (root_plt->refcount != 0);
14416 root_plt->refcount -= 1;
14417 }
14418 else
14419 /* A value of -1 means the symbol has become local, forced
14420 or seeing a hidden definition. Any other negative value
14421 is an error. */
14422 BFD_ASSERT (root_plt->refcount == -1);
34e77a92
RS		 14423
14424 if (!call_reloc_p)
14425 arm_plt->noncall_refcount--;
5e681ec4 14426
f6e32f6d 14427 if (r_type == R_ARM_THM_CALL)
34e77a92 14428 arm_plt->maybe_thumb_refcount--;
bd97cb95 14429
f6e32f6d
RS		 14430 if (r_type == R_ARM_THM_JUMP24
14431 || r_type == R_ARM_THM_JUMP19)
34e77a92 14432 arm_plt->thumb_refcount--;
f6e32f6d 14433 }
5e681ec4 14434
34e77a92 14435 if (may_become_dynamic_p)
f6e32f6d
RS		 14436 {
14437 struct elf_dyn_relocs **pp;
14438 struct elf_dyn_relocs *p;
5e681ec4 14439
34e77a92 14440 if (h != NULL)
9c489990 14441 pp = &(eh->dyn_relocs);
34e77a92
RS		 14442 else
14443 {
14444 Elf_Internal_Sym *isym;
14445
14446 isym = bfd_sym_from_r_symndx (&globals->sym_cache,
14447 abfd, r_symndx);
14448 if (isym == NULL)
14449 return FALSE;
14450 pp = elf32_arm_get_local_dynreloc_list (abfd, r_symndx, isym);
14451 if (pp == NULL)
14452 return FALSE;
14453 }
9c489990 14454 for (; (p = *pp) != NULL; pp = &p->next)
f6e32f6d
RS		 14455 if (p->sec == sec)
14456 {
14457 /* Everything must go for SEC. */
14458 *pp = p->next;
14459 break;
14460 }
eb043451
PB		 14461 }
14462 }
5e681ec4 14463
b34976b6 14464 return TRUE;
252b5132
RH		 14465}
14466
780a67af
NC		 14467/* Look through the relocs for a section during the first phase. */
14468
b34976b6 14469static bfd_boolean
57e8b36a
NC		 14470elf32_arm_check_relocs (bfd *abfd, struct bfd_link_info *info,
14471 asection *sec, const Elf_Internal_Rela *relocs)
252b5132 14472{
b34976b6
AM		 14473 Elf_Internal_Shdr *symtab_hdr;
14474 struct elf_link_hash_entry **sym_hashes;
b34976b6
AM		 14475 const Elf_Internal_Rela *rel;
14476 const Elf_Internal_Rela *rel_end;
14477 bfd *dynobj;
5e681ec4 14478 asection *sreloc;
5e681ec4 14479 struct elf32_arm_link_hash_table *htab;
f6e32f6d
RS		 14480 bfd_boolean call_reloc_p;
14481 bfd_boolean may_become_dynamic_p;
14482 bfd_boolean may_need_local_target_p;
ce98a316 14483 unsigned long nsyms;
9a5aca8c 14484
0e1862bb 14485 if (bfd_link_relocatable (info))
b34976b6 14486 return TRUE;
9a5aca8c 14487
0ffa91dd
NC		 14488 BFD_ASSERT (is_arm_elf (abfd));
14489
5e681ec4 14490 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 14491 if (htab == NULL)
14492 return FALSE;
14493
5e681ec4 14494 sreloc = NULL;
9a5aca8c 14495
67687978
PB		 14496 /* Create dynamic sections for relocatable executables so that we can
14497 copy relocations. */
14498 if (htab->root.is_relocatable_executable
14499 && ! htab->root.dynamic_sections_created)
14500 {
14501 if (! _bfd_elf_link_create_dynamic_sections (abfd, info))
14502 return FALSE;
14503 }
14504
cbc704f3
RS		 14505 if (htab->root.dynobj == NULL)
14506 htab->root.dynobj = abfd;
34e77a92
RS		 14507 if (!create_ifunc_sections (info))
14508 return FALSE;
cbc704f3
RS		 14509
14510 dynobj = htab->root.dynobj;
14511
0ffa91dd 14512 symtab_hdr = & elf_symtab_hdr (abfd);
252b5132 14513 sym_hashes = elf_sym_hashes (abfd);
ce98a316 14514 nsyms = NUM_SHDR_ENTRIES (symtab_hdr);
b38cadfb 14515
252b5132
RH		 14516 rel_end = relocs + sec->reloc_count;
14517 for (rel = relocs; rel < rel_end; rel++)
14518 {
34e77a92 14519 Elf_Internal_Sym *isym;
252b5132 14520 struct elf_link_hash_entry *h;
b7693d02 14521 struct elf32_arm_link_hash_entry *eh;
252b5132 14522 unsigned long r_symndx;
eb043451 14523 int r_type;
9a5aca8c 14524
252b5132 14525 r_symndx = ELF32_R_SYM (rel->r_info);
eb043451 14526 r_type = ELF32_R_TYPE (rel->r_info);
eb043451 14527 r_type = arm_real_reloc_type (htab, r_type);
ba93b8ac 14528
ce98a316
NC		 14529 if (r_symndx >= nsyms
14530 /* PR 9934: It is possible to have relocations that do not
14531 refer to symbols, thus it is also possible to have an
14532 object file containing relocations but no symbol table. */
cf35638d 14533 && (r_symndx > STN_UNDEF || nsyms > 0))
ba93b8ac 14534 {
4eca0228
AM		 14535 _bfd_error_handler (_("%B: bad symbol index: %d"), abfd,
14536 r_symndx);
ba93b8ac
DJ		 14537 return FALSE;
14538 }
14539
34e77a92
RS		 14540 h = NULL;
14541 isym = NULL;
14542 if (nsyms > 0)
973a3492 14543 {
34e77a92
RS		 14544 if (r_symndx < symtab_hdr->sh_info)
14545 {
14546 /* A local symbol. */
14547 isym = bfd_sym_from_r_symndx (&htab->sym_cache,
14548 abfd, r_symndx);
14549 if (isym == NULL)
14550 return FALSE;
14551 }
14552 else
14553 {
14554 h = sym_hashes[r_symndx - symtab_hdr->sh_info];
14555 while (h->root.type == bfd_link_hash_indirect
14556 || h->root.type == bfd_link_hash_warning)
14557 h = (struct elf_link_hash_entry *) h->root.u.i.link;
81fbe831
AM		 14558
14559 /* PR15323, ref flags aren't set for references in the
14560 same object. */
14561 h->root.non_ir_ref = 1;
34e77a92 14562 }
973a3492 14563 }
9a5aca8c 14564
b7693d02
DJ		 14565 eh = (struct elf32_arm_link_hash_entry *) h;
14566
f6e32f6d
RS		 14567 call_reloc_p = FALSE;
14568 may_become_dynamic_p = FALSE;
14569 may_need_local_target_p = FALSE;
14570
0855e32b
NS		 14571 /* Could be done earlier, if h were already available. */
14572 r_type = elf32_arm_tls_transition (info, r_type, h);
eb043451 14573 switch (r_type)
99059e56 14574 {
5e681ec4 14575 case R_ARM_GOT32:
eb043451 14576 case R_ARM_GOT_PREL:
ba93b8ac
DJ		 14577 case R_ARM_TLS_GD32:
14578 case R_ARM_TLS_IE32:
0855e32b
NS		 14579 case R_ARM_TLS_GOTDESC:
14580 case R_ARM_TLS_DESCSEQ:
14581 case R_ARM_THM_TLS_DESCSEQ:
14582 case R_ARM_TLS_CALL:
14583 case R_ARM_THM_TLS_CALL:
5e681ec4 14584 /* This symbol requires a global offset table entry. */
ba93b8ac
DJ		 14585 {
14586 int tls_type, old_tls_type;
5e681ec4 14587
ba93b8ac
DJ		 14588 switch (r_type)
14589 {
14590 case R_ARM_TLS_GD32: tls_type = GOT_TLS_GD; break;
b38cadfb 14591
ba93b8ac 14592 case R_ARM_TLS_IE32: tls_type = GOT_TLS_IE; break;
b38cadfb 14593
0855e32b
NS		 14594 case R_ARM_TLS_GOTDESC:
14595 case R_ARM_TLS_CALL: case R_ARM_THM_TLS_CALL:
14596 case R_ARM_TLS_DESCSEQ: case R_ARM_THM_TLS_DESCSEQ:
14597 tls_type = GOT_TLS_GDESC; break;
b38cadfb 14598
ba93b8ac
DJ		 14599 default: tls_type = GOT_NORMAL; break;
14600 }
252b5132 14601
0e1862bb 14602 if (!bfd_link_executable (info) && (tls_type & GOT_TLS_IE))
eea6dad2
KM		 14603 info->flags |= DF_STATIC_TLS;
14604
ba93b8ac
DJ		 14605 if (h != NULL)
14606 {
14607 h->got.refcount++;
14608 old_tls_type = elf32_arm_hash_entry (h)->tls_type;
14609 }
14610 else
14611 {
ba93b8ac 14612 /* This is a global offset table entry for a local symbol. */
34e77a92
RS		 14613 if (!elf32_arm_allocate_local_sym_info (abfd))
14614 return FALSE;
14615 elf_local_got_refcounts (abfd)[r_symndx] += 1;
ba93b8ac
DJ		 14616 old_tls_type = elf32_arm_local_got_tls_type (abfd) [r_symndx];
14617 }
14618
0855e32b 14619 /* If a variable is accessed with both tls methods, two
99059e56 14620 slots may be created. */
0855e32b
NS		 14621 if (GOT_TLS_GD_ANY_P (old_tls_type)
14622 && GOT_TLS_GD_ANY_P (tls_type))
14623 tls_type |= old_tls_type;
14624
14625 /* We will already have issued an error message if there
14626 is a TLS/non-TLS mismatch, based on the symbol
14627 type. So just combine any TLS types needed. */
ba93b8ac
DJ		 14628 if (old_tls_type != GOT_UNKNOWN && old_tls_type != GOT_NORMAL
14629 && tls_type != GOT_NORMAL)
14630 tls_type |= old_tls_type;
14631
0855e32b 14632 /* If the symbol is accessed in both IE and GDESC
99059e56
RM		 14633 method, we're able to relax. Turn off the GDESC flag,
14634 without messing up with any other kind of tls types
6a631e86 14635 that may be involved. */
0855e32b
NS		 14636 if ((tls_type & GOT_TLS_IE) && (tls_type & GOT_TLS_GDESC))
14637 tls_type &= ~GOT_TLS_GDESC;
14638
ba93b8ac
DJ		 14639 if (old_tls_type != tls_type)
14640 {
14641 if (h != NULL)
14642 elf32_arm_hash_entry (h)->tls_type = tls_type;
14643 else
14644 elf32_arm_local_got_tls_type (abfd) [r_symndx] = tls_type;
14645 }
14646 }
8029a119 14647 /* Fall through. */
ba93b8ac
DJ		 14648
14649 case R_ARM_TLS_LDM32:
14650 if (r_type == R_ARM_TLS_LDM32)
14651 htab->tls_ldm_got.refcount++;
8029a119 14652 /* Fall through. */
252b5132 14653
c19d1205 14654 case R_ARM_GOTOFF32:
5e681ec4 14655 case R_ARM_GOTPC:
cbc704f3
RS		 14656 if (htab->root.sgot == NULL
14657 && !create_got_section (htab->root.dynobj, info))
14658 return FALSE;
252b5132
RH		 14659 break;
14660
252b5132 14661 case R_ARM_PC24:
7359ea65 14662 case R_ARM_PLT32:
5b5bb741
PB		 14663 case R_ARM_CALL:
14664 case R_ARM_JUMP24:
eb043451 14665 case R_ARM_PREL31:
c19d1205 14666 case R_ARM_THM_CALL:
bd97cb95
DJ		 14667 case R_ARM_THM_JUMP24:
14668 case R_ARM_THM_JUMP19:
f6e32f6d
RS		 14669 call_reloc_p = TRUE;
14670 may_need_local_target_p = TRUE;
14671 break;
14672
14673 case R_ARM_ABS12:
14674 /* VxWorks uses dynamic R_ARM_ABS12 relocations for
14675 ldr __GOTT_INDEX__ offsets. */
14676 if (!htab->vxworks_p)
14677 {
14678 may_need_local_target_p = TRUE;
14679 break;
14680 }
aebf9be7 14681 else goto jump_over;
9eaff861 14682
f6e32f6d 14683 /* Fall through. */
39623e12 14684
96c23d59
JM		 14685 case R_ARM_MOVW_ABS_NC:
14686 case R_ARM_MOVT_ABS:
14687 case R_ARM_THM_MOVW_ABS_NC:
14688 case R_ARM_THM_MOVT_ABS:
0e1862bb 14689 if (bfd_link_pic (info))
96c23d59 14690 {
4eca0228 14691 _bfd_error_handler
96c23d59
JM		 14692 (_("%B: relocation %s against `%s' can not be used when making a shared object; recompile with -fPIC"),
14693 abfd, elf32_arm_howto_table_1[r_type].name,
14694 (h) ? h->root.root.string : "a local symbol");
14695 bfd_set_error (bfd_error_bad_value);
14696 return FALSE;
14697 }
14698
14699 /* Fall through. */
39623e12
PB		 14700 case R_ARM_ABS32:
14701 case R_ARM_ABS32_NOI:
aebf9be7 14702 jump_over:
0e1862bb 14703 if (h != NULL && bfd_link_executable (info))
97323ad1
WN		 14704 {
14705 h->pointer_equality_needed = 1;
14706 }
14707 /* Fall through. */
39623e12
PB		 14708 case R_ARM_REL32:
14709 case R_ARM_REL32_NOI:
b6895b4f
PB		 14710 case R_ARM_MOVW_PREL_NC:
14711 case R_ARM_MOVT_PREL:
b6895b4f
PB		 14712 case R_ARM_THM_MOVW_PREL_NC:
14713 case R_ARM_THM_MOVT_PREL:
39623e12 14714
b7693d02 14715 /* Should the interworking branches be listed here? */
0e1862bb 14716 if ((bfd_link_pic (info) || htab->root.is_relocatable_executable)
34e77a92
RS		 14717 && (sec->flags & SEC_ALLOC) != 0)
14718 {
14719 if (h == NULL
469a3493 14720 && elf32_arm_howto_from_type (r_type)->pc_relative)
34e77a92
RS		 14721 {
14722 /* In shared libraries and relocatable executables,
14723 we treat local relative references as calls;
14724 see the related SYMBOL_CALLS_LOCAL code in
14725 allocate_dynrelocs. */
14726 call_reloc_p = TRUE;
14727 may_need_local_target_p = TRUE;
14728 }
14729 else
14730 /* We are creating a shared library or relocatable
14731 executable, and this is a reloc against a global symbol,
14732 or a non-PC-relative reloc against a local symbol.
14733 We may need to copy the reloc into the output. */
14734 may_become_dynamic_p = TRUE;
14735 }
f6e32f6d
RS		 14736 else
14737 may_need_local_target_p = TRUE;
252b5132
RH		 14738 break;
14739
99059e56
RM		 14740 /* This relocation describes the C++ object vtable hierarchy.
14741 Reconstruct it for later use during GC. */
14742 case R_ARM_GNU_VTINHERIT:
14743 if (!bfd_elf_gc_record_vtinherit (abfd, sec, h, rel->r_offset))
14744 return FALSE;
14745 break;
14746
14747 /* This relocation describes which C++ vtable entries are actually
14748 used. Record for later use during GC. */
14749 case R_ARM_GNU_VTENTRY:
14750 BFD_ASSERT (h != NULL);
14751 if (h != NULL
14752 && !bfd_elf_gc_record_vtentry (abfd, sec, h, rel->r_offset))
14753 return FALSE;
14754 break;
14755 }
f6e32f6d
RS		 14756
14757 if (h != NULL)
14758 {
14759 if (call_reloc_p)
14760 /* We may need a .plt entry if the function this reloc
14761 refers to is in a different object, regardless of the
14762 symbol's type. We can't tell for sure yet, because
14763 something later might force the symbol local. */
14764 h->needs_plt = 1;
14765 else if (may_need_local_target_p)
14766 /* If this reloc is in a read-only section, we might
14767 need a copy reloc. We can't check reliably at this
14768 stage whether the section is read-only, as input
14769 sections have not yet been mapped to output sections.
14770 Tentatively set the flag for now, and correct in
14771 adjust_dynamic_symbol. */
14772 h->non_got_ref = 1;
14773 }
14774
34e77a92
RS		 14775 if (may_need_local_target_p
14776 && (h != NULL || ELF32_ST_TYPE (isym->st_info) == STT_GNU_IFUNC))
f6e32f6d 14777 {
34e77a92
RS		 14778 union gotplt_union *root_plt;
14779 struct arm_plt_info *arm_plt;
14780 struct arm_local_iplt_info *local_iplt;
14781
14782 if (h != NULL)
14783 {
14784 root_plt = &h->plt;
14785 arm_plt = &eh->plt;
14786 }
14787 else
14788 {
14789 local_iplt = elf32_arm_create_local_iplt (abfd, r_symndx);
14790 if (local_iplt == NULL)
14791 return FALSE;
14792 root_plt = &local_iplt->root;
14793 arm_plt = &local_iplt->arm;
14794 }
14795
f6e32f6d
RS		 14796 /* If the symbol is a function that doesn't bind locally,
14797 this relocation will need a PLT entry. */
a8c887dd
NC		 14798 if (root_plt->refcount != -1)
14799 root_plt->refcount += 1;
34e77a92
RS		 14800
14801 if (!call_reloc_p)
14802 arm_plt->noncall_refcount++;
f6e32f6d
RS		 14803
14804 /* It's too early to use htab->use_blx here, so we have to
14805 record possible blx references separately from
14806 relocs that definitely need a thumb stub. */
14807
14808 if (r_type == R_ARM_THM_CALL)
34e77a92 14809 arm_plt->maybe_thumb_refcount += 1;
f6e32f6d
RS		 14810
14811 if (r_type == R_ARM_THM_JUMP24
14812 || r_type == R_ARM_THM_JUMP19)
34e77a92 14813 arm_plt->thumb_refcount += 1;
f6e32f6d
RS		 14814 }
14815
14816 if (may_become_dynamic_p)
14817 {
14818 struct elf_dyn_relocs *p, **head;
14819
14820 /* Create a reloc section in dynobj. */
14821 if (sreloc == NULL)
14822 {
14823 sreloc = _bfd_elf_make_dynamic_reloc_section
14824 (sec, dynobj, 2, abfd, ! htab->use_rel);
14825
14826 if (sreloc == NULL)
14827 return FALSE;
14828
14829 /* BPABI objects never have dynamic relocations mapped. */
14830 if (htab->symbian_p)
14831 {
14832 flagword flags;
14833
14834 flags = bfd_get_section_flags (dynobj, sreloc);
14835 flags &= ~(SEC_LOAD | SEC_ALLOC);
14836 bfd_set_section_flags (dynobj, sreloc, flags);
14837 }
14838 }
14839
14840 /* If this is a global symbol, count the number of
14841 relocations we need for this symbol. */
14842 if (h != NULL)
14843 head = &((struct elf32_arm_link_hash_entry *) h)->dyn_relocs;
14844 else
14845 {
34e77a92
RS		 14846 head = elf32_arm_get_local_dynreloc_list (abfd, r_symndx, isym);
14847 if (head == NULL)
f6e32f6d 14848 return FALSE;
f6e32f6d
RS		 14849 }
14850
14851 p = *head;
14852 if (p == NULL || p->sec != sec)
14853 {
14854 bfd_size_type amt = sizeof *p;
14855
14856 p = (struct elf_dyn_relocs *) bfd_alloc (htab->root.dynobj, amt);
14857 if (p == NULL)
14858 return FALSE;
14859 p->next = *head;
14860 *head = p;
14861 p->sec = sec;
14862 p->count = 0;
14863 p->pc_count = 0;
14864 }
14865
469a3493 14866 if (elf32_arm_howto_from_type (r_type)->pc_relative)
f6e32f6d
RS		 14867 p->pc_count += 1;
14868 p->count += 1;
14869 }
252b5132 14870 }
f21f3fe0 14871
b34976b6 14872 return TRUE;
252b5132
RH		 14873}
14874
9eaff861
AO		 14875static void
14876elf32_arm_update_relocs (asection *o,
14877 struct bfd_elf_section_reloc_data *reldata)
14878{
14879 void (*swap_in) (bfd *, const bfd_byte *, Elf_Internal_Rela *);
14880 void (*swap_out) (bfd *, const Elf_Internal_Rela *, bfd_byte *);
14881 const struct elf_backend_data *bed;
14882 _arm_elf_section_data *eado;
14883 struct bfd_link_order *p;
14884 bfd_byte *erela_head, *erela;
14885 Elf_Internal_Rela *irela_head, *irela;
14886 Elf_Internal_Shdr *rel_hdr;
14887 bfd *abfd;
14888 unsigned int count;
14889
14890 eado = get_arm_elf_section_data (o);
14891
14892 if (!eado || eado->elf.this_hdr.sh_type != SHT_ARM_EXIDX)
14893 return;
14894
14895 abfd = o->owner;
14896 bed = get_elf_backend_data (abfd);
14897 rel_hdr = reldata->hdr;
14898
14899 if (rel_hdr->sh_entsize == bed->s->sizeof_rel)
14900 {
14901 swap_in = bed->s->swap_reloc_in;
14902 swap_out = bed->s->swap_reloc_out;
14903 }
14904 else if (rel_hdr->sh_entsize == bed->s->sizeof_rela)
14905 {
14906 swap_in = bed->s->swap_reloca_in;
14907 swap_out = bed->s->swap_reloca_out;
14908 }
14909 else
14910 abort ();
14911
14912 erela_head = rel_hdr->contents;
14913 irela_head = (Elf_Internal_Rela *) bfd_zmalloc
14914 ((NUM_SHDR_ENTRIES (rel_hdr) + 1) * sizeof (*irela_head));
14915
14916 erela = erela_head;
14917 irela = irela_head;
14918 count = 0;
14919
14920 for (p = o->map_head.link_order; p; p = p->next)
14921 {
14922 if (p->type == bfd_section_reloc_link_order
14923 || p->type == bfd_symbol_reloc_link_order)
14924 {
14925 (*swap_in) (abfd, erela, irela);
14926 erela += rel_hdr->sh_entsize;
14927 irela++;
14928 count++;
14929 }
14930 else if (p->type == bfd_indirect_link_order)
14931 {
14932 struct bfd_elf_section_reloc_data *input_reldata;
14933 arm_unwind_table_edit *edit_list, *edit_tail;
14934 _arm_elf_section_data *eadi;
14935 bfd_size_type j;
14936 bfd_vma offset;
14937 asection *i;
14938
14939 i = p->u.indirect.section;
14940
14941 eadi = get_arm_elf_section_data (i);
14942 edit_list = eadi->u.exidx.unwind_edit_list;
14943 edit_tail = eadi->u.exidx.unwind_edit_tail;
14944 offset = o->vma + i->output_offset;
14945
14946 if (eadi->elf.rel.hdr &&
14947 eadi->elf.rel.hdr->sh_entsize == rel_hdr->sh_entsize)
14948 input_reldata = &eadi->elf.rel;
14949 else if (eadi->elf.rela.hdr &&
14950 eadi->elf.rela.hdr->sh_entsize == rel_hdr->sh_entsize)
14951 input_reldata = &eadi->elf.rela;
14952 else
14953 abort ();
14954
14955 if (edit_list)
14956 {
14957 for (j = 0; j < NUM_SHDR_ENTRIES (input_reldata->hdr); j++)
14958 {
14959 arm_unwind_table_edit *edit_node, *edit_next;
14960 bfd_vma bias;
c48182bf 14961 bfd_vma reloc_index;
9eaff861
AO		 14962
14963 (*swap_in) (abfd, erela, irela);
c48182bf 14964 reloc_index = (irela->r_offset - offset) / 8;
9eaff861
AO		 14965
14966 bias = 0;
14967 edit_node = edit_list;
14968 for (edit_next = edit_list;
c48182bf 14969 edit_next && edit_next->index <= reloc_index;
9eaff861
AO		 14970 edit_next = edit_node->next)
14971 {
14972 bias++;
14973 edit_node = edit_next;
14974 }
14975
14976 if (edit_node->type != DELETE_EXIDX_ENTRY
c48182bf 14977 || edit_node->index != reloc_index)
9eaff861
AO		 14978 {
14979 irela->r_offset -= bias * 8;
14980 irela++;
14981 count++;
14982 }
14983
14984 erela += rel_hdr->sh_entsize;
14985 }
14986
14987 if (edit_tail->type == INSERT_EXIDX_CANTUNWIND_AT_END)
14988 {
14989 /* New relocation entity. */
14990 asection *text_sec = edit_tail->linked_section;
14991 asection *text_out = text_sec->output_section;
14992 bfd_vma exidx_offset = offset + i->size - 8;
14993
14994 irela->r_addend = 0;
14995 irela->r_offset = exidx_offset;
14996 irela->r_info = ELF32_R_INFO
14997 (text_out->target_index, R_ARM_PREL31);
14998 irela++;
14999 count++;
15000 }
15001 }
15002 else
15003 {
15004 for (j = 0; j < NUM_SHDR_ENTRIES (input_reldata->hdr); j++)
15005 {
15006 (*swap_in) (abfd, erela, irela);
15007 erela += rel_hdr->sh_entsize;
15008 irela++;
15009 }
15010
15011 count += NUM_SHDR_ENTRIES (input_reldata->hdr);
15012 }
15013 }
15014 }
15015
15016 reldata->count = count;
15017 rel_hdr->sh_size = count * rel_hdr->sh_entsize;
15018
15019 erela = erela_head;
15020 irela = irela_head;
15021 while (count > 0)
15022 {
15023 (*swap_out) (abfd, irela, erela);
15024 erela += rel_hdr->sh_entsize;
15025 irela++;
15026 count--;
15027 }
15028
15029 free (irela_head);
15030
15031 /* Hashes are no longer valid. */
15032 free (reldata->hashes);
15033 reldata->hashes = NULL;
15034}
15035
6a5bb875 15036/* Unwinding tables are not referenced directly. This pass marks them as
4ba2ef8f
TP		 15037 required if the corresponding code section is marked. Similarly, ARMv8-M
15038 secure entry functions can only be referenced by SG veneers which are
15039 created after the GC process. They need to be marked in case they reside in
15040 their own section (as would be the case if code was compiled with
15041 -ffunction-sections). */
6a5bb875
PB		 15042
15043static bfd_boolean
906e58ca
NC		 15044elf32_arm_gc_mark_extra_sections (struct bfd_link_info *info,
15045 elf_gc_mark_hook_fn gc_mark_hook)
6a5bb875
PB		 15046{
15047 bfd *sub;
15048 Elf_Internal_Shdr **elf_shdrp;
4ba2ef8f
TP		 15049 asection *cmse_sec;
15050 obj_attribute *out_attr;
15051 Elf_Internal_Shdr *symtab_hdr;
15052 unsigned i, sym_count, ext_start;
15053 const struct elf_backend_data *bed;
15054 struct elf_link_hash_entry **sym_hashes;
15055 struct elf32_arm_link_hash_entry *cmse_hash;
15056 bfd_boolean again, is_v8m, first_bfd_browse = TRUE;
6a5bb875 15057
7f6ab9f8
AM		 15058 _bfd_elf_gc_mark_extra_sections (info, gc_mark_hook);
15059
4ba2ef8f
TP		 15060 out_attr = elf_known_obj_attributes_proc (info->output_bfd);
15061 is_v8m = out_attr[Tag_CPU_arch].i >= TAG_CPU_ARCH_V8M_BASE
15062 && out_attr[Tag_CPU_arch_profile].i == 'M';
15063
6a5bb875
PB		 15064 /* Marking EH data may cause additional code sections to be marked,
15065 requiring multiple passes. */
15066 again = TRUE;
15067 while (again)
15068 {
15069 again = FALSE;
c72f2fb2 15070 for (sub = info->input_bfds; sub != NULL; sub = sub->link.next)
6a5bb875
PB		 15071 {
15072 asection *o;
15073
0ffa91dd 15074 if (! is_arm_elf (sub))
6a5bb875
PB		 15075 continue;
15076
15077 elf_shdrp = elf_elfsections (sub);
15078 for (o = sub->sections; o != NULL; o = o->next)
15079 {
15080 Elf_Internal_Shdr *hdr;
0ffa91dd 15081
6a5bb875 15082 hdr = &elf_section_data (o)->this_hdr;
4fbb74a6
AM		 15083 if (hdr->sh_type == SHT_ARM_EXIDX
15084 && hdr->sh_link
15085 && hdr->sh_link < elf_numsections (sub)
6a5bb875
PB		 15086 && !o->gc_mark
15087 && elf_shdrp[hdr->sh_link]->bfd_section->gc_mark)
15088 {
15089 again = TRUE;
15090 if (!_bfd_elf_gc_mark (info, o, gc_mark_hook))
15091 return FALSE;
15092 }
15093 }
4ba2ef8f
TP		 15094
15095 /* Mark section holding ARMv8-M secure entry functions. We mark all
15096 of them so no need for a second browsing. */
15097 if (is_v8m && first_bfd_browse)
15098 {
15099 sym_hashes = elf_sym_hashes (sub);
15100 bed = get_elf_backend_data (sub);
15101 symtab_hdr = &elf_tdata (sub)->symtab_hdr;
15102 sym_count = symtab_hdr->sh_size / bed->s->sizeof_sym;
15103 ext_start = symtab_hdr->sh_info;
15104
15105 /* Scan symbols. */
15106 for (i = ext_start; i < sym_count; i++)
15107 {
15108 cmse_hash = elf32_arm_hash_entry (sym_hashes[i - ext_start]);
15109
15110 /* Assume it is a special symbol. If not, cmse_scan will
15111 warn about it and user can do something about it. */
15112 if (ARM_GET_SYM_CMSE_SPCL (cmse_hash->root.target_internal))
15113 {
15114 cmse_sec = cmse_hash->root.root.u.def.section;
5025eb7c
AO		 15115 if (!cmse_sec->gc_mark
15116 && !_bfd_elf_gc_mark (info, cmse_sec, gc_mark_hook))
4ba2ef8f
TP		 15117 return FALSE;
15118 }
15119 }
15120 }
6a5bb875 15121 }
4ba2ef8f 15122 first_bfd_browse = FALSE;
6a5bb875
PB		 15123 }
15124
15125 return TRUE;
15126}
15127
3c9458e9
NC		 15128/* Treat mapping symbols as special target symbols. */
15129
15130static bfd_boolean
15131elf32_arm_is_target_special_symbol (bfd * abfd ATTRIBUTE_UNUSED, asymbol * sym)
15132{
b0796911
PB		 15133 return bfd_is_arm_special_symbol_name (sym->name,
15134 BFD_ARM_SPECIAL_SYM_TYPE_ANY);
3c9458e9
NC		 15135}
15136
0367ecfb
NC		 15137/* This is a copy of elf_find_function() from elf.c except that
15138 ARM mapping symbols are ignored when looking for function names
15139 and STT_ARM_TFUNC is considered to a function type. */
252b5132 15140
0367ecfb
NC		 15141static bfd_boolean
15142arm_elf_find_function (bfd * abfd ATTRIBUTE_UNUSED,
0367ecfb 15143 asymbol ** symbols,
fb167eb2 15144 asection * section,
0367ecfb
NC		 15145 bfd_vma offset,
15146 const char ** filename_ptr,
15147 const char ** functionname_ptr)
15148{
15149 const char * filename = NULL;
15150 asymbol * func = NULL;
15151 bfd_vma low_func = 0;
15152 asymbol ** p;
252b5132
RH		 15153
15154 for (p = symbols; *p != NULL; p++)
15155 {
15156 elf_symbol_type *q;
15157
15158 q = (elf_symbol_type *) *p;
15159
252b5132
RH		 15160 switch (ELF_ST_TYPE (q->internal_elf_sym.st_info))
15161 {
15162 default:
15163 break;
15164 case STT_FILE:
15165 filename = bfd_asymbol_name (&q->symbol);
15166 break;
252b5132
RH		 15167 case STT_FUNC:
15168 case STT_ARM_TFUNC:
9d2da7ca 15169 case STT_NOTYPE:
b0796911 15170 /* Skip mapping symbols. */
0367ecfb 15171 if ((q->symbol.flags & BSF_LOCAL)
b0796911
PB		 15172 && bfd_is_arm_special_symbol_name (q->symbol.name,
15173 BFD_ARM_SPECIAL_SYM_TYPE_ANY))
0367ecfb
NC		 15174 continue;
15175 /* Fall through. */
6b40fcba 15176 if (bfd_get_section (&q->symbol) == section
252b5132
RH		 15177 && q->symbol.value >= low_func
15178 && q->symbol.value <= offset)
15179 {
15180 func = (asymbol *) q;
15181 low_func = q->symbol.value;
15182 }
15183 break;
15184 }
15185 }
15186
15187 if (func == NULL)
b34976b6 15188 return FALSE;
252b5132 15189
0367ecfb
NC		 15190 if (filename_ptr)
15191 *filename_ptr = filename;
15192 if (functionname_ptr)
15193 *functionname_ptr = bfd_asymbol_name (func);
15194
15195 return TRUE;
906e58ca 15196}
0367ecfb
NC		 15197
15198
15199/* Find the nearest line to a particular section and offset, for error
15200 reporting. This code is a duplicate of the code in elf.c, except
15201 that it uses arm_elf_find_function. */
15202
15203static bfd_boolean
15204elf32_arm_find_nearest_line (bfd * abfd,
0367ecfb 15205 asymbol ** symbols,
fb167eb2 15206 asection * section,
0367ecfb
NC		 15207 bfd_vma offset,
15208 const char ** filename_ptr,
15209 const char ** functionname_ptr,
fb167eb2
AM		 15210 unsigned int * line_ptr,
15211 unsigned int * discriminator_ptr)
0367ecfb
NC		 15212{
15213 bfd_boolean found = FALSE;
15214
fb167eb2 15215 if (_bfd_dwarf2_find_nearest_line (abfd, symbols, NULL, section, offset,
0367ecfb 15216 filename_ptr, functionname_ptr,
fb167eb2
AM		 15217 line_ptr, discriminator_ptr,
15218 dwarf_debug_sections, 0,
0367ecfb
NC		 15219 & elf_tdata (abfd)->dwarf2_find_line_info))
15220 {
15221 if (!*functionname_ptr)
fb167eb2 15222 arm_elf_find_function (abfd, symbols, section, offset,
0367ecfb
NC		 15223 *filename_ptr ? NULL : filename_ptr,
15224 functionname_ptr);
f21f3fe0 15225
0367ecfb
NC		 15226 return TRUE;
15227 }
15228
fb167eb2
AM		 15229 /* Skip _bfd_dwarf1_find_nearest_line since no known ARM toolchain
15230 uses DWARF1. */
15231
0367ecfb
NC		 15232 if (! _bfd_stab_section_find_nearest_line (abfd, symbols, section, offset,
15233 & found, filename_ptr,
15234 functionname_ptr, line_ptr,
15235 & elf_tdata (abfd)->line_info))
15236 return FALSE;
15237
15238 if (found && (*functionname_ptr || *line_ptr))
15239 return TRUE;
15240
15241 if (symbols == NULL)
15242 return FALSE;
15243
fb167eb2 15244 if (! arm_elf_find_function (abfd, symbols, section, offset,
0367ecfb
NC		 15245 filename_ptr, functionname_ptr))
15246 return FALSE;
15247
15248 *line_ptr = 0;
b34976b6 15249 return TRUE;
252b5132
RH		 15250}
15251
4ab527b0
FF		 15252static bfd_boolean
15253elf32_arm_find_inliner_info (bfd * abfd,
15254 const char ** filename_ptr,
15255 const char ** functionname_ptr,
15256 unsigned int * line_ptr)
15257{
15258 bfd_boolean found;
15259 found = _bfd_dwarf2_find_inliner_info (abfd, filename_ptr,
15260 functionname_ptr, line_ptr,
15261 & elf_tdata (abfd)->dwarf2_find_line_info);
15262 return found;
15263}
15264
252b5132
RH		 15265/* Adjust a symbol defined by a dynamic object and referenced by a
15266 regular object. The current definition is in some section of the
15267 dynamic object, but we're not including those sections. We have to
15268 change the definition to something the rest of the link can
15269 understand. */
15270
b34976b6 15271static bfd_boolean
57e8b36a
NC		 15272elf32_arm_adjust_dynamic_symbol (struct bfd_link_info * info,
15273 struct elf_link_hash_entry * h)
252b5132
RH		 15274{
15275 bfd * dynobj;
15276 asection * s;
b7693d02 15277 struct elf32_arm_link_hash_entry * eh;
67687978 15278 struct elf32_arm_link_hash_table *globals;
252b5132 15279
67687978 15280 globals = elf32_arm_hash_table (info);
4dfe6ac6
NC		 15281 if (globals == NULL)
15282 return FALSE;
15283
252b5132
RH		 15284 dynobj = elf_hash_table (info)->dynobj;
15285
15286 /* Make sure we know what is going on here. */
15287 BFD_ASSERT (dynobj != NULL
f5385ebf 15288 && (h->needs_plt
34e77a92 15289 || h->type == STT_GNU_IFUNC
f6e332e6 15290 || h->u.weakdef != NULL
f5385ebf
AM		 15291 || (h->def_dynamic
15292 && h->ref_regular
15293 && !h->def_regular)));
252b5132 15294
b7693d02
DJ		 15295 eh = (struct elf32_arm_link_hash_entry *) h;
15296
252b5132
RH		 15297 /* If this is a function, put it in the procedure linkage table. We
15298 will fill in the contents of the procedure linkage table later,
15299 when we know the address of the .got section. */
34e77a92 15300 if (h->type == STT_FUNC || h->type == STT_GNU_IFUNC || h->needs_plt)
252b5132 15301 {
34e77a92
RS		 15302 /* Calls to STT_GNU_IFUNC symbols always use a PLT, even if the
15303 symbol binds locally. */
5e681ec4 15304 if (h->plt.refcount <= 0
34e77a92
RS		 15305 || (h->type != STT_GNU_IFUNC
15306 && (SYMBOL_CALLS_LOCAL (info, h)
15307 || (ELF_ST_VISIBILITY (h->other) != STV_DEFAULT
15308 && h->root.type == bfd_link_hash_undefweak))))
252b5132
RH		 15309 {
15310 /* This case can occur if we saw a PLT32 reloc in an input
5e681ec4
PB		 15311 file, but the symbol was never referred to by a dynamic
15312 object, or if all references were garbage collected. In
15313 such a case, we don't actually need to build a procedure
15314 linkage table, and we can just do a PC24 reloc instead. */
15315 h->plt.offset = (bfd_vma) -1;
34e77a92
RS		 15316 eh->plt.thumb_refcount = 0;
15317 eh->plt.maybe_thumb_refcount = 0;
15318 eh->plt.noncall_refcount = 0;
f5385ebf 15319 h->needs_plt = 0;
252b5132
RH		 15320 }
15321
b34976b6 15322 return TRUE;
252b5132 15323 }
5e681ec4 15324 else
b7693d02
DJ		 15325 {
15326 /* It's possible that we incorrectly decided a .plt reloc was
15327 needed for an R_ARM_PC24 or similar reloc to a non-function sym
15328 in check_relocs. We can't decide accurately between function
15329 and non-function syms in check-relocs; Objects loaded later in
15330 the link may change h->type. So fix it now. */
15331 h->plt.offset = (bfd_vma) -1;
34e77a92
RS		 15332 eh->plt.thumb_refcount = 0;
15333 eh->plt.maybe_thumb_refcount = 0;
15334 eh->plt.noncall_refcount = 0;
b7693d02 15335 }
252b5132
RH		 15336
15337 /* If this is a weak symbol, and there is a real definition, the
15338 processor independent code will have arranged for us to see the
15339 real definition first, and we can just use the same value. */
f6e332e6 15340 if (h->u.weakdef != NULL)
252b5132 15341 {
f6e332e6
AM		 15342 BFD_ASSERT (h->u.weakdef->root.type == bfd_link_hash_defined
15343 || h->u.weakdef->root.type == bfd_link_hash_defweak);
15344 h->root.u.def.section = h->u.weakdef->root.u.def.section;
15345 h->root.u.def.value = h->u.weakdef->root.u.def.value;
b34976b6 15346 return TRUE;
252b5132
RH		 15347 }
15348
ba93b8ac
DJ		 15349 /* If there are no non-GOT references, we do not need a copy
15350 relocation. */
15351 if (!h->non_got_ref)
15352 return TRUE;
15353
252b5132
RH		 15354 /* This is a reference to a symbol defined by a dynamic object which
15355 is not a function. */
15356
15357 /* If we are creating a shared library, we must presume that the
15358 only references to the symbol are via the global offset table.
15359 For such cases we need not do anything here; the relocations will
67687978
PB		 15360 be handled correctly by relocate_section. Relocatable executables
15361 can reference data in shared objects directly, so we don't need to
15362 do anything here. */
0e1862bb 15363 if (bfd_link_pic (info) || globals->root.is_relocatable_executable)
b34976b6 15364 return TRUE;
252b5132
RH		 15365
15366 /* We must allocate the symbol in our .dynbss section, which will
15367 become part of the .bss section of the executable. There will be
15368 an entry for this symbol in the .dynsym section. The dynamic
15369 object will contain position independent code, so all references
15370 from the dynamic object to this symbol will go through the global
15371 offset table. The dynamic linker will use the .dynsym entry to
15372 determine the address it must put in the global offset table, so
15373 both the dynamic object and the regular object will refer to the
15374 same memory location for the variable. */
3d4d4302 15375 s = bfd_get_linker_section (dynobj, ".dynbss");
252b5132
RH		 15376 BFD_ASSERT (s != NULL);
15377
5522f910
NC		 15378 /* If allowed, we must generate a R_ARM_COPY reloc to tell the dynamic
15379 linker to copy the initial value out of the dynamic object and into
15380 the runtime process image. We need to remember the offset into the
00a97672 15381 .rel(a).bss section we are going to use. */
5522f910
NC		 15382 if (info->nocopyreloc == 0
15383 && (h->root.u.def.section->flags & SEC_ALLOC) != 0
5522f910 15384 && h->size != 0)
252b5132
RH		 15385 {
15386 asection *srel;
15387
3d4d4302 15388 srel = bfd_get_linker_section (dynobj, RELOC_SECTION (globals, ".bss"));
47beaa6a 15389 elf32_arm_allocate_dynrelocs (info, srel, 1);
f5385ebf 15390 h->needs_copy = 1;
252b5132
RH		 15391 }
15392
6cabe1ea 15393 return _bfd_elf_adjust_dynamic_copy (info, h, s);
252b5132
RH		 15394}
15395
5e681ec4
PB		 15396/* Allocate space in .plt, .got and associated reloc sections for
15397 dynamic relocs. */
15398
15399static bfd_boolean
47beaa6a 15400allocate_dynrelocs_for_symbol (struct elf_link_hash_entry *h, void * inf)
5e681ec4
PB		 15401{
15402 struct bfd_link_info *info;
15403 struct elf32_arm_link_hash_table *htab;
15404 struct elf32_arm_link_hash_entry *eh;
0bdcacaf 15405 struct elf_dyn_relocs *p;
5e681ec4
PB		 15406
15407 if (h->root.type == bfd_link_hash_indirect)
15408 return TRUE;
15409
e6a6bb22
AM		 15410 eh = (struct elf32_arm_link_hash_entry *) h;
15411
5e681ec4
PB		 15412 info = (struct bfd_link_info *) inf;
15413 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 15414 if (htab == NULL)
15415 return FALSE;
5e681ec4 15416
34e77a92 15417 if ((htab->root.dynamic_sections_created || h->type == STT_GNU_IFUNC)
5e681ec4
PB		 15418 && h->plt.refcount > 0)
15419 {
15420 /* Make sure this symbol is output as a dynamic symbol.
15421 Undefined weak syms won't yet be marked as dynamic. */
15422 if (h->dynindx == -1
f5385ebf 15423 && !h->forced_local)
5e681ec4 15424 {
c152c796 15425 if (! bfd_elf_link_record_dynamic_symbol (info, h))
5e681ec4
PB		 15426 return FALSE;
15427 }
15428
34e77a92
RS		 15429 /* If the call in the PLT entry binds locally, the associated
15430 GOT entry should use an R_ARM_IRELATIVE relocation instead of
15431 the usual R_ARM_JUMP_SLOT. Put it in the .iplt section rather
15432 than the .plt section. */
15433 if (h->type == STT_GNU_IFUNC && SYMBOL_CALLS_LOCAL (info, h))
15434 {
15435 eh->is_iplt = 1;
15436 if (eh->plt.noncall_refcount == 0
15437 && SYMBOL_REFERENCES_LOCAL (info, h))
15438 /* All non-call references can be resolved directly.
15439 This means that they can (and in some cases, must)
15440 resolve directly to the run-time target, rather than
15441 to the PLT. That in turns means that any .got entry
15442 would be equal to the .igot.plt entry, so there's
15443 no point having both. */
15444 h->got.refcount = 0;
15445 }
15446
0e1862bb 15447 if (bfd_link_pic (info)
34e77a92 15448 || eh->is_iplt
7359ea65 15449 || WILL_CALL_FINISH_DYNAMIC_SYMBOL (1, 0, h))
5e681ec4 15450 {
34e77a92 15451 elf32_arm_allocate_plt_entry (info, eh->is_iplt, &h->plt, &eh->plt);
b7693d02 15452
5e681ec4
PB		 15453 /* If this symbol is not defined in a regular file, and we are
15454 not generating a shared library, then set the symbol to this
15455 location in the .plt. This is required to make function
15456 pointers compare as equal between the normal executable and
15457 the shared library. */
0e1862bb 15458 if (! bfd_link_pic (info)
f5385ebf 15459 && !h->def_regular)
5e681ec4 15460 {
34e77a92 15461 h->root.u.def.section = htab->root.splt;
5e681ec4 15462 h->root.u.def.value = h->plt.offset;
5e681ec4 15463
67d74e43
DJ		 15464 /* Make sure the function is not marked as Thumb, in case
15465 it is the target of an ABS32 relocation, which will
15466 point to the PLT entry. */
39d911fc 15467 ARM_SET_SYM_BRANCH_TYPE (h->target_internal, ST_BRANCH_TO_ARM);
67d74e43 15468 }
022f8312 15469
00a97672
RS		 15470 /* VxWorks executables have a second set of relocations for
15471 each PLT entry. They go in a separate relocation section,
15472 which is processed by the kernel loader. */
0e1862bb 15473 if (htab->vxworks_p && !bfd_link_pic (info))
00a97672
RS		 15474 {
15475 /* There is a relocation for the initial PLT entry:
15476 an R_ARM_32 relocation for _GLOBAL_OFFSET_TABLE_. */
15477 if (h->plt.offset == htab->plt_header_size)
47beaa6a 15478 elf32_arm_allocate_dynrelocs (info, htab->srelplt2, 1);
00a97672
RS		 15479
15480 /* There are two extra relocations for each subsequent
15481 PLT entry: an R_ARM_32 relocation for the GOT entry,
15482 and an R_ARM_32 relocation for the PLT entry. */
47beaa6a 15483 elf32_arm_allocate_dynrelocs (info, htab->srelplt2, 2);
00a97672 15484 }
5e681ec4
PB		 15485 }
15486 else
15487 {
15488 h->plt.offset = (bfd_vma) -1;
f5385ebf 15489 h->needs_plt = 0;
5e681ec4
PB		 15490 }
15491 }
15492 else
15493 {
15494 h->plt.offset = (bfd_vma) -1;
f5385ebf 15495 h->needs_plt = 0;
5e681ec4
PB		 15496 }
15497
0855e32b
NS		 15498 eh = (struct elf32_arm_link_hash_entry *) h;
15499 eh->tlsdesc_got = (bfd_vma) -1;
15500
5e681ec4
PB		 15501 if (h->got.refcount > 0)
15502 {
15503 asection *s;
15504 bfd_boolean dyn;
ba93b8ac
DJ		 15505 int tls_type = elf32_arm_hash_entry (h)->tls_type;
15506 int indx;
5e681ec4
PB		 15507
15508 /* Make sure this symbol is output as a dynamic symbol.
15509 Undefined weak syms won't yet be marked as dynamic. */
15510 if (h->dynindx == -1
f5385ebf 15511 && !h->forced_local)
5e681ec4 15512 {
c152c796 15513 if (! bfd_elf_link_record_dynamic_symbol (info, h))
5e681ec4
PB		 15514 return FALSE;
15515 }
15516
e5a52504
MM		 15517 if (!htab->symbian_p)
15518 {
362d30a1 15519 s = htab->root.sgot;
e5a52504 15520 h->got.offset = s->size;
ba93b8ac
DJ		 15521
15522 if (tls_type == GOT_UNKNOWN)
15523 abort ();
15524
15525 if (tls_type == GOT_NORMAL)
15526 /* Non-TLS symbols need one GOT slot. */
15527 s->size += 4;
15528 else
15529 {
99059e56
RM		 15530 if (tls_type & GOT_TLS_GDESC)
15531 {
0855e32b 15532 /* R_ARM_TLS_DESC needs 2 GOT slots. */
99059e56 15533 eh->tlsdesc_got
0855e32b
NS		 15534 = (htab->root.sgotplt->size
15535 - elf32_arm_compute_jump_table_size (htab));
99059e56
RM		 15536 htab->root.sgotplt->size += 8;
15537 h->got.offset = (bfd_vma) -2;
34e77a92 15538 /* plt.got_offset needs to know there's a TLS_DESC
0855e32b 15539 reloc in the middle of .got.plt. */
99059e56
RM		 15540 htab->num_tls_desc++;
15541 }
0855e32b 15542
ba93b8ac 15543 if (tls_type & GOT_TLS_GD)
0855e32b
NS		 15544 {
15545 /* R_ARM_TLS_GD32 needs 2 consecutive GOT slots. If
15546 the symbol is both GD and GDESC, got.offset may
15547 have been overwritten. */
15548 h->got.offset = s->size;
15549 s->size += 8;
15550 }
15551
ba93b8ac
DJ		 15552 if (tls_type & GOT_TLS_IE)
15553 /* R_ARM_TLS_IE32 needs one GOT slot. */
15554 s->size += 4;
15555 }
15556
e5a52504 15557 dyn = htab->root.dynamic_sections_created;
ba93b8ac
DJ		 15558
15559 indx = 0;
0e1862bb
L		 15560 if (WILL_CALL_FINISH_DYNAMIC_SYMBOL (dyn,
15561 bfd_link_pic (info),
15562 h)
15563 && (!bfd_link_pic (info)
ba93b8ac
DJ		 15564 || !SYMBOL_REFERENCES_LOCAL (info, h)))
15565 indx = h->dynindx;
15566
15567 if (tls_type != GOT_NORMAL
0e1862bb 15568 && (bfd_link_pic (info) || indx != 0)
ba93b8ac
DJ		 15569 && (ELF_ST_VISIBILITY (h->other) == STV_DEFAULT
15570 || h->root.type != bfd_link_hash_undefweak))
15571 {
15572 if (tls_type & GOT_TLS_IE)
47beaa6a 15573 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
ba93b8ac
DJ		 15574
15575 if (tls_type & GOT_TLS_GD)
47beaa6a 15576 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
ba93b8ac 15577
b38cadfb 15578 if (tls_type & GOT_TLS_GDESC)
0855e32b 15579 {
47beaa6a 15580 elf32_arm_allocate_dynrelocs (info, htab->root.srelplt, 1);
0855e32b
NS		 15581 /* GDESC needs a trampoline to jump to. */
15582 htab->tls_trampoline = -1;
15583 }
15584
15585 /* Only GD needs it. GDESC just emits one relocation per
15586 2 entries. */
b38cadfb 15587 if ((tls_type & GOT_TLS_GD) && indx != 0)
47beaa6a 15588 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
ba93b8ac 15589 }
6f820c85 15590 else if (indx != -1 && !SYMBOL_REFERENCES_LOCAL (info, h))
b436d854
RS		 15591 {
15592 if (htab->root.dynamic_sections_created)
15593 /* Reserve room for the GOT entry's R_ARM_GLOB_DAT relocation. */
15594 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
15595 }
34e77a92
RS		 15596 else if (h->type == STT_GNU_IFUNC
15597 && eh->plt.noncall_refcount == 0)
15598 /* No non-call references resolve the STT_GNU_IFUNC's PLT entry;
15599 they all resolve dynamically instead. Reserve room for the
15600 GOT entry's R_ARM_IRELATIVE relocation. */
15601 elf32_arm_allocate_irelocs (info, htab->root.srelgot, 1);
0e1862bb
L		 15602 else if (bfd_link_pic (info)
15603 && (ELF_ST_VISIBILITY (h->other) == STV_DEFAULT
15604 || h->root.type != bfd_link_hash_undefweak))
b436d854 15605 /* Reserve room for the GOT entry's R_ARM_RELATIVE relocation. */
47beaa6a 15606 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
e5a52504 15607 }
5e681ec4
PB		 15608 }
15609 else
15610 h->got.offset = (bfd_vma) -1;
15611
a4fd1a8e
PB		 15612 /* Allocate stubs for exported Thumb functions on v4t. */
15613 if (!htab->use_blx && h->dynindx != -1
0eaedd0e 15614 && h->def_regular
39d911fc 15615 && ARM_GET_SYM_BRANCH_TYPE (h->target_internal) == ST_BRANCH_TO_THUMB
a4fd1a8e
PB		 15616 && ELF_ST_VISIBILITY (h->other) == STV_DEFAULT)
15617 {
15618 struct elf_link_hash_entry * th;
15619 struct bfd_link_hash_entry * bh;
15620 struct elf_link_hash_entry * myh;
15621 char name[1024];
15622 asection *s;
15623 bh = NULL;
15624 /* Create a new symbol to regist the real location of the function. */
15625 s = h->root.u.def.section;
906e58ca 15626 sprintf (name, "__real_%s", h->root.root.string);
a4fd1a8e
PB		 15627 _bfd_generic_link_add_one_symbol (info, s->owner,
15628 name, BSF_GLOBAL, s,
15629 h->root.u.def.value,
15630 NULL, TRUE, FALSE, &bh);
15631
15632 myh = (struct elf_link_hash_entry *) bh;
35fc36a8 15633 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
a4fd1a8e 15634 myh->forced_local = 1;
39d911fc 15635 ARM_SET_SYM_BRANCH_TYPE (myh->target_internal, ST_BRANCH_TO_THUMB);
a4fd1a8e
PB		 15636 eh->export_glue = myh;
15637 th = record_arm_to_thumb_glue (info, h);
15638 /* Point the symbol at the stub. */
15639 h->type = ELF_ST_INFO (ELF_ST_BIND (h->type), STT_FUNC);
39d911fc 15640 ARM_SET_SYM_BRANCH_TYPE (h->target_internal, ST_BRANCH_TO_ARM);
a4fd1a8e
PB		 15641 h->root.u.def.section = th->root.u.def.section;
15642 h->root.u.def.value = th->root.u.def.value & ~1;
15643 }
15644
0bdcacaf 15645 if (eh->dyn_relocs == NULL)
5e681ec4
PB		 15646 return TRUE;
15647
15648 /* In the shared -Bsymbolic case, discard space allocated for
15649 dynamic pc-relative relocs against symbols which turn out to be
15650 defined in regular objects. For the normal shared case, discard
15651 space for pc-relative relocs that have become local due to symbol
15652 visibility changes. */
15653
0e1862bb 15654 if (bfd_link_pic (info) || htab->root.is_relocatable_executable)
5e681ec4 15655 {
469a3493
RM		 15656 /* Relocs that use pc_count are PC-relative forms, which will appear
15657 on something like ".long foo - ." or "movw REG, foo - .". We want
15658 calls to protected symbols to resolve directly to the function
15659 rather than going via the plt. If people want function pointer
15660 comparisons to work as expected then they should avoid writing
15661 assembly like ".long foo - .". */
ba93b8ac
DJ		 15662 if (SYMBOL_CALLS_LOCAL (info, h))
15663 {
0bdcacaf 15664 struct elf_dyn_relocs **pp;
ba93b8ac 15665
0bdcacaf 15666 for (pp = &eh->dyn_relocs; (p = *pp) != NULL; )
ba93b8ac
DJ		 15667 {
15668 p->count -= p->pc_count;
15669 p->pc_count = 0;
15670 if (p->count == 0)
15671 *pp = p->next;
15672 else
15673 pp = &p->next;
15674 }
15675 }
15676
4dfe6ac6 15677 if (htab->vxworks_p)
3348747a 15678 {
0bdcacaf 15679 struct elf_dyn_relocs **pp;
3348747a 15680
0bdcacaf 15681 for (pp = &eh->dyn_relocs; (p = *pp) != NULL; )
3348747a 15682 {
0bdcacaf 15683 if (strcmp (p->sec->output_section->name, ".tls_vars") == 0)
3348747a
NS		 15684 *pp = p->next;
15685 else
15686 pp = &p->next;
15687 }
15688 }
15689
ba93b8ac 15690 /* Also discard relocs on undefined weak syms with non-default
99059e56 15691 visibility. */
0bdcacaf 15692 if (eh->dyn_relocs != NULL
5e681ec4 15693 && h->root.type == bfd_link_hash_undefweak)
22d606e9
AM		 15694 {
15695 if (ELF_ST_VISIBILITY (h->other) != STV_DEFAULT)
0bdcacaf 15696 eh->dyn_relocs = NULL;
22d606e9
AM		 15697
15698 /* Make sure undefined weak symbols are output as a dynamic
15699 symbol in PIEs. */
15700 else if (h->dynindx == -1
15701 && !h->forced_local)
15702 {
15703 if (! bfd_elf_link_record_dynamic_symbol (info, h))
15704 return FALSE;
15705 }
15706 }
15707
67687978
PB		 15708 else if (htab->root.is_relocatable_executable && h->dynindx == -1
15709 && h->root.type == bfd_link_hash_new)
15710 {
15711 /* Output absolute symbols so that we can create relocations
15712 against them. For normal symbols we output a relocation
15713 against the section that contains them. */
15714 if (! bfd_elf_link_record_dynamic_symbol (info, h))
15715 return FALSE;
15716 }
15717
5e681ec4
PB		 15718 }
15719 else
15720 {
15721 /* For the non-shared case, discard space for relocs against
15722 symbols which turn out to need copy relocs or are not
15723 dynamic. */
15724
f5385ebf
AM		 15725 if (!h->non_got_ref
15726 && ((h->def_dynamic
15727 && !h->def_regular)
5e681ec4
PB		 15728 || (htab->root.dynamic_sections_created
15729 && (h->root.type == bfd_link_hash_undefweak
15730 || h->root.type == bfd_link_hash_undefined))))
15731 {
15732 /* Make sure this symbol is output as a dynamic symbol.
15733 Undefined weak syms won't yet be marked as dynamic. */
15734 if (h->dynindx == -1
f5385ebf 15735 && !h->forced_local)
5e681ec4 15736 {
c152c796 15737 if (! bfd_elf_link_record_dynamic_symbol (info, h))
5e681ec4
PB		 15738 return FALSE;
15739 }
15740
15741 /* If that succeeded, we know we'll be keeping all the
15742 relocs. */
15743 if (h->dynindx != -1)
15744 goto keep;
15745 }
15746
0bdcacaf 15747 eh->dyn_relocs = NULL;
5e681ec4
PB		 15748
15749 keep: ;
15750 }
15751
15752 /* Finally, allocate space. */
0bdcacaf 15753 for (p = eh->dyn_relocs; p != NULL; p = p->next)
5e681ec4 15754 {
0bdcacaf 15755 asection *sreloc = elf_section_data (p->sec)->sreloc;
34e77a92
RS		 15756 if (h->type == STT_GNU_IFUNC
15757 && eh->plt.noncall_refcount == 0
15758 && SYMBOL_REFERENCES_LOCAL (info, h))
15759 elf32_arm_allocate_irelocs (info, sreloc, p->count);
15760 else
15761 elf32_arm_allocate_dynrelocs (info, sreloc, p->count);
5e681ec4
PB		 15762 }
15763
15764 return TRUE;
15765}
15766
08d1f311
DJ		 15767/* Find any dynamic relocs that apply to read-only sections. */
15768
15769static bfd_boolean
8029a119 15770elf32_arm_readonly_dynrelocs (struct elf_link_hash_entry * h, void * inf)
08d1f311 15771{
8029a119 15772 struct elf32_arm_link_hash_entry * eh;
0bdcacaf 15773 struct elf_dyn_relocs * p;
08d1f311 15774
08d1f311 15775 eh = (struct elf32_arm_link_hash_entry *) h;
0bdcacaf 15776 for (p = eh->dyn_relocs; p != NULL; p = p->next)
08d1f311 15777 {
0bdcacaf 15778 asection *s = p->sec;
08d1f311
DJ		 15779
15780 if (s != NULL && (s->flags & SEC_READONLY) != 0)
15781 {
15782 struct bfd_link_info *info = (struct bfd_link_info *) inf;
15783
15784 info->flags |= DF_TEXTREL;
15785
15786 /* Not an error, just cut short the traversal. */
15787 return FALSE;
15788 }
15789 }
15790 return TRUE;
15791}
15792
d504ffc8
DJ		 15793void
15794bfd_elf32_arm_set_byteswap_code (struct bfd_link_info *info,
15795 int byteswap_code)
15796{
15797 struct elf32_arm_link_hash_table *globals;
15798
15799 globals = elf32_arm_hash_table (info);
4dfe6ac6
NC		 15800 if (globals == NULL)
15801 return;
15802
d504ffc8
DJ		 15803 globals->byteswap_code = byteswap_code;
15804}
15805
252b5132
RH		 15806/* Set the sizes of the dynamic sections. */
15807
b34976b6 15808static bfd_boolean
57e8b36a
NC		 15809elf32_arm_size_dynamic_sections (bfd * output_bfd ATTRIBUTE_UNUSED,
15810 struct bfd_link_info * info)
252b5132
RH		 15811{
15812 bfd * dynobj;
15813 asection * s;
b34976b6
AM		 15814 bfd_boolean plt;
15815 bfd_boolean relocs;
5e681ec4
PB		 15816 bfd *ibfd;
15817 struct elf32_arm_link_hash_table *htab;
252b5132 15818
5e681ec4 15819 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 15820 if (htab == NULL)
15821 return FALSE;
15822
252b5132
RH		 15823 dynobj = elf_hash_table (info)->dynobj;
15824 BFD_ASSERT (dynobj != NULL);
39b41c9c 15825 check_use_blx (htab);
252b5132
RH		 15826
15827 if (elf_hash_table (info)->dynamic_sections_created)
15828 {
15829 /* Set the contents of the .interp section to the interpreter. */
9b8b325a 15830 if (bfd_link_executable (info) && !info->nointerp)
252b5132 15831 {
3d4d4302 15832 s = bfd_get_linker_section (dynobj, ".interp");
252b5132 15833 BFD_ASSERT (s != NULL);
eea6121a 15834 s->size = sizeof ELF_DYNAMIC_INTERPRETER;
252b5132
RH		 15835 s->contents = (unsigned char *) ELF_DYNAMIC_INTERPRETER;
15836 }
15837 }
5e681ec4
PB		 15838
15839 /* Set up .got offsets for local syms, and space for local dynamic
15840 relocs. */
c72f2fb2 15841 for (ibfd = info->input_bfds; ibfd != NULL; ibfd = ibfd->link.next)
252b5132 15842 {
5e681ec4
PB		 15843 bfd_signed_vma *local_got;
15844 bfd_signed_vma *end_local_got;
34e77a92 15845 struct arm_local_iplt_info **local_iplt_ptr, *local_iplt;
5e681ec4 15846 char *local_tls_type;
0855e32b 15847 bfd_vma *local_tlsdesc_gotent;
5e681ec4
PB		 15848 bfd_size_type locsymcount;
15849 Elf_Internal_Shdr *symtab_hdr;
15850 asection *srel;
4dfe6ac6 15851 bfd_boolean is_vxworks = htab->vxworks_p;
34e77a92 15852 unsigned int symndx;
5e681ec4 15853
0ffa91dd 15854 if (! is_arm_elf (ibfd))
5e681ec4
PB		 15855 continue;
15856
15857 for (s = ibfd->sections; s != NULL; s = s->next)
15858 {
0bdcacaf 15859 struct elf_dyn_relocs *p;
5e681ec4 15860
0bdcacaf 15861 for (p = (struct elf_dyn_relocs *)
99059e56 15862 elf_section_data (s)->local_dynrel; p != NULL; p = p->next)
5e681ec4 15863 {
0bdcacaf
RS		 15864 if (!bfd_is_abs_section (p->sec)
15865 && bfd_is_abs_section (p->sec->output_section))
5e681ec4
PB		 15866 {
15867 /* Input section has been discarded, either because
15868 it is a copy of a linkonce section or due to
15869 linker script /DISCARD/, so we'll be discarding
15870 the relocs too. */
15871 }
3348747a 15872 else if (is_vxworks
0bdcacaf 15873 && strcmp (p->sec->output_section->name,
3348747a
NS		 15874 ".tls_vars") == 0)
15875 {
15876 /* Relocations in vxworks .tls_vars sections are
15877 handled specially by the loader. */
15878 }
5e681ec4
PB		 15879 else if (p->count != 0)
15880 {
0bdcacaf 15881 srel = elf_section_data (p->sec)->sreloc;
47beaa6a 15882 elf32_arm_allocate_dynrelocs (info, srel, p->count);
0bdcacaf 15883 if ((p->sec->output_section->flags & SEC_READONLY) != 0)
5e681ec4
PB		 15884 info->flags |= DF_TEXTREL;
15885 }
15886 }
15887 }
15888
15889 local_got = elf_local_got_refcounts (ibfd);
15890 if (!local_got)
15891 continue;
15892
0ffa91dd 15893 symtab_hdr = & elf_symtab_hdr (ibfd);
5e681ec4
PB		 15894 locsymcount = symtab_hdr->sh_info;
15895 end_local_got = local_got + locsymcount;
34e77a92 15896 local_iplt_ptr = elf32_arm_local_iplt (ibfd);
ba93b8ac 15897 local_tls_type = elf32_arm_local_got_tls_type (ibfd);
0855e32b 15898 local_tlsdesc_gotent = elf32_arm_local_tlsdesc_gotent (ibfd);
34e77a92 15899 symndx = 0;
362d30a1
RS		 15900 s = htab->root.sgot;
15901 srel = htab->root.srelgot;
0855e32b 15902 for (; local_got < end_local_got;
34e77a92
RS		 15903 ++local_got, ++local_iplt_ptr, ++local_tls_type,
15904 ++local_tlsdesc_gotent, ++symndx)
5e681ec4 15905 {
0855e32b 15906 *local_tlsdesc_gotent = (bfd_vma) -1;
34e77a92
RS		 15907 local_iplt = *local_iplt_ptr;
15908 if (local_iplt != NULL)
15909 {
15910 struct elf_dyn_relocs *p;
15911
15912 if (local_iplt->root.refcount > 0)
15913 {
15914 elf32_arm_allocate_plt_entry (info, TRUE,
15915 &local_iplt->root,
15916 &local_iplt->arm);
15917 if (local_iplt->arm.noncall_refcount == 0)
15918 /* All references to the PLT are calls, so all
15919 non-call references can resolve directly to the
15920 run-time target. This means that the .got entry
15921 would be the same as the .igot.plt entry, so there's
15922 no point creating both. */
15923 *local_got = 0;
15924 }
15925 else
15926 {
15927 BFD_ASSERT (local_iplt->arm.noncall_refcount == 0);
15928 local_iplt->root.offset = (bfd_vma) -1;
15929 }
15930
15931 for (p = local_iplt->dyn_relocs; p != NULL; p = p->next)
15932 {
15933 asection *psrel;
15934
15935 psrel = elf_section_data (p->sec)->sreloc;
15936 if (local_iplt->arm.noncall_refcount == 0)
15937 elf32_arm_allocate_irelocs (info, psrel, p->count);
15938 else
15939 elf32_arm_allocate_dynrelocs (info, psrel, p->count);
15940 }
15941 }
5e681ec4
PB		 15942 if (*local_got > 0)
15943 {
34e77a92
RS		 15944 Elf_Internal_Sym *isym;
15945
eea6121a 15946 *local_got = s->size;
ba93b8ac
DJ		 15947 if (*local_tls_type & GOT_TLS_GD)
15948 /* TLS_GD relocs need an 8-byte structure in the GOT. */
15949 s->size += 8;
0855e32b
NS		 15950 if (*local_tls_type & GOT_TLS_GDESC)
15951 {
15952 *local_tlsdesc_gotent = htab->root.sgotplt->size
15953 - elf32_arm_compute_jump_table_size (htab);
15954 htab->root.sgotplt->size += 8;
15955 *local_got = (bfd_vma) -2;
34e77a92 15956 /* plt.got_offset needs to know there's a TLS_DESC
0855e32b 15957 reloc in the middle of .got.plt. */
99059e56 15958 htab->num_tls_desc++;
0855e32b 15959 }
ba93b8ac
DJ		 15960 if (*local_tls_type & GOT_TLS_IE)
15961 s->size += 4;
ba93b8ac 15962
0855e32b
NS		 15963 if (*local_tls_type & GOT_NORMAL)
15964 {
15965 /* If the symbol is both GD and GDESC, *local_got
15966 may have been overwritten. */
15967 *local_got = s->size;
15968 s->size += 4;
15969 }
15970
34e77a92
RS		 15971 isym = bfd_sym_from_r_symndx (&htab->sym_cache, ibfd, symndx);
15972 if (isym == NULL)
15973 return FALSE;
15974
15975 /* If all references to an STT_GNU_IFUNC PLT are calls,
15976 then all non-call references, including this GOT entry,
15977 resolve directly to the run-time target. */
15978 if (ELF32_ST_TYPE (isym->st_info) == STT_GNU_IFUNC
15979 && (local_iplt == NULL
15980 || local_iplt->arm.noncall_refcount == 0))
15981 elf32_arm_allocate_irelocs (info, srel, 1);
0e1862bb 15982 else if (bfd_link_pic (info) || output_bfd->flags & DYNAMIC)
0855e32b 15983 {
0e1862bb 15984 if ((bfd_link_pic (info) && !(*local_tls_type & GOT_TLS_GDESC))
3064e1ff
JB		 15985 || *local_tls_type & GOT_TLS_GD)
15986 elf32_arm_allocate_dynrelocs (info, srel, 1);
99059e56 15987
0e1862bb 15988 if (bfd_link_pic (info) && *local_tls_type & GOT_TLS_GDESC)
3064e1ff
JB		 15989 {
15990 elf32_arm_allocate_dynrelocs (info,
15991 htab->root.srelplt, 1);
15992 htab->tls_trampoline = -1;
15993 }
0855e32b 15994 }
5e681ec4
PB		 15995 }
15996 else
15997 *local_got = (bfd_vma) -1;
15998 }
252b5132
RH		 15999 }
16000
ba93b8ac
DJ		 16001 if (htab->tls_ldm_got.refcount > 0)
16002 {
16003 /* Allocate two GOT entries and one dynamic relocation (if necessary)
16004 for R_ARM_TLS_LDM32 relocations. */
362d30a1
RS		 16005 htab->tls_ldm_got.offset = htab->root.sgot->size;
16006 htab->root.sgot->size += 8;
0e1862bb 16007 if (bfd_link_pic (info))
47beaa6a 16008 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
ba93b8ac
DJ		 16009 }
16010 else
16011 htab->tls_ldm_got.offset = -1;
16012
5e681ec4
PB		 16013 /* Allocate global sym .plt and .got entries, and space for global
16014 sym dynamic relocs. */
47beaa6a 16015 elf_link_hash_traverse (& htab->root, allocate_dynrelocs_for_symbol, info);
252b5132 16016
d504ffc8 16017 /* Here we rummage through the found bfds to collect glue information. */
c72f2fb2 16018 for (ibfd = info->input_bfds; ibfd != NULL; ibfd = ibfd->link.next)
c7b8f16e 16019 {
0ffa91dd 16020 if (! is_arm_elf (ibfd))
e44a2c9c
AM		 16021 continue;
16022
c7b8f16e
JB		 16023 /* Initialise mapping tables for code/data. */
16024 bfd_elf32_arm_init_maps (ibfd);
906e58ca 16025
c7b8f16e 16026 if (!bfd_elf32_arm_process_before_allocation (ibfd, info)
a504d23a
LA		 16027 || !bfd_elf32_arm_vfp11_erratum_scan (ibfd, info)
16028 || !bfd_elf32_arm_stm32l4xx_erratum_scan (ibfd, info))
99059e56 16029 _bfd_error_handler (_("Errors encountered processing file %s"),
c7b8f16e
JB		 16030 ibfd->filename);
16031 }
d504ffc8 16032
3e6b1042
DJ		 16033 /* Allocate space for the glue sections now that we've sized them. */
16034 bfd_elf32_arm_allocate_interworking_sections (info);
16035
0855e32b
NS		 16036 /* For every jump slot reserved in the sgotplt, reloc_count is
16037 incremented. However, when we reserve space for TLS descriptors,
16038 it's not incremented, so in order to compute the space reserved
16039 for them, it suffices to multiply the reloc count by the jump
16040 slot size. */
16041 if (htab->root.srelplt)
16042 htab->sgotplt_jump_table_size = elf32_arm_compute_jump_table_size(htab);
16043
16044 if (htab->tls_trampoline)
16045 {
16046 if (htab->root.splt->size == 0)
16047 htab->root.splt->size += htab->plt_header_size;
b38cadfb 16048
0855e32b
NS		 16049 htab->tls_trampoline = htab->root.splt->size;
16050 htab->root.splt->size += htab->plt_entry_size;
b38cadfb 16051
0855e32b 16052 /* If we're not using lazy TLS relocations, don't generate the
99059e56 16053 PLT and GOT entries they require. */
0855e32b
NS		 16054 if (!(info->flags & DF_BIND_NOW))
16055 {
16056 htab->dt_tlsdesc_got = htab->root.sgot->size;
16057 htab->root.sgot->size += 4;
16058
16059 htab->dt_tlsdesc_plt = htab->root.splt->size;
16060 htab->root.splt->size += 4 * ARRAY_SIZE (dl_tlsdesc_lazy_trampoline);
16061 }
16062 }
16063
252b5132
RH		 16064 /* The check_relocs and adjust_dynamic_symbol entry points have
16065 determined the sizes of the various dynamic sections. Allocate
16066 memory for them. */
b34976b6
AM		 16067 plt = FALSE;
16068 relocs = FALSE;
252b5132
RH		 16069 for (s = dynobj->sections; s != NULL; s = s->next)
16070 {
16071 const char * name;
252b5132
RH		 16072
16073 if ((s->flags & SEC_LINKER_CREATED) == 0)
16074 continue;
16075
16076 /* It's OK to base decisions on the section name, because none
16077 of the dynobj section names depend upon the input files. */
16078 name = bfd_get_section_name (dynobj, s);
16079
34e77a92 16080 if (s == htab->root.splt)
252b5132 16081 {
c456f082
AM		 16082 /* Remember whether there is a PLT. */
16083 plt = s->size != 0;
252b5132 16084 }
0112cd26 16085 else if (CONST_STRNEQ (name, ".rel"))
252b5132 16086 {
c456f082 16087 if (s->size != 0)
252b5132 16088 {
252b5132 16089 /* Remember whether there are any reloc sections other
00a97672 16090 than .rel(a).plt and .rela.plt.unloaded. */
362d30a1 16091 if (s != htab->root.srelplt && s != htab->srelplt2)
b34976b6 16092 relocs = TRUE;
252b5132
RH		 16093
16094 /* We use the reloc_count field as a counter if we need
16095 to copy relocs into the output file. */
16096 s->reloc_count = 0;
16097 }
16098 }
34e77a92
RS		 16099 else if (s != htab->root.sgot
16100 && s != htab->root.sgotplt
16101 && s != htab->root.iplt
16102 && s != htab->root.igotplt
16103 && s != htab->sdynbss)
252b5132
RH		 16104 {
16105 /* It's not one of our sections, so don't allocate space. */
16106 continue;
16107 }
16108
c456f082 16109 if (s->size == 0)
252b5132 16110 {
c456f082 16111 /* If we don't need this section, strip it from the
00a97672
RS		 16112 output file. This is mostly to handle .rel(a).bss and
16113 .rel(a).plt. We must create both sections in
c456f082
AM		 16114 create_dynamic_sections, because they must be created
16115 before the linker maps input sections to output
16116 sections. The linker does that before
16117 adjust_dynamic_symbol is called, and it is that
16118 function which decides whether anything needs to go
16119 into these sections. */
8423293d 16120 s->flags |= SEC_EXCLUDE;
252b5132
RH		 16121 continue;
16122 }
16123
c456f082
AM		 16124 if ((s->flags & SEC_HAS_CONTENTS) == 0)
16125 continue;
16126
252b5132 16127 /* Allocate memory for the section contents. */
21d799b5 16128 s->contents = (unsigned char *) bfd_zalloc (dynobj, s->size);
c456f082 16129 if (s->contents == NULL)
b34976b6 16130 return FALSE;
252b5132
RH		 16131 }
16132
16133 if (elf_hash_table (info)->dynamic_sections_created)
16134 {
16135 /* Add some entries to the .dynamic section. We fill in the
16136 values later, in elf32_arm_finish_dynamic_sections, but we
16137 must add the entries now so that we get the correct size for
16138 the .dynamic section. The DT_DEBUG entry is filled in by the
16139 dynamic linker and used by the debugger. */
dc810e39 16140#define add_dynamic_entry(TAG, VAL) \
5a580b3a 16141 _bfd_elf_add_dynamic_entry (info, TAG, VAL)
dc810e39 16142
0e1862bb 16143 if (bfd_link_executable (info))
252b5132 16144 {
dc810e39 16145 if (!add_dynamic_entry (DT_DEBUG, 0))
b34976b6 16146 return FALSE;
252b5132
RH		 16147 }
16148
16149 if (plt)
16150 {
dc810e39
AM		 16151 if ( !add_dynamic_entry (DT_PLTGOT, 0)
16152 || !add_dynamic_entry (DT_PLTRELSZ, 0)
00a97672
RS		 16153 || !add_dynamic_entry (DT_PLTREL,
16154 htab->use_rel ? DT_REL : DT_RELA)
dc810e39 16155 || !add_dynamic_entry (DT_JMPREL, 0))
b34976b6 16156 return FALSE;
0855e32b 16157
5025eb7c
AO		 16158 if (htab->dt_tlsdesc_plt
16159 && (!add_dynamic_entry (DT_TLSDESC_PLT,0)
16160 || !add_dynamic_entry (DT_TLSDESC_GOT,0)))
b38cadfb 16161 return FALSE;
252b5132
RH		 16162 }
16163
16164 if (relocs)
16165 {
00a97672
RS		 16166 if (htab->use_rel)
16167 {
16168 if (!add_dynamic_entry (DT_REL, 0)
16169 || !add_dynamic_entry (DT_RELSZ, 0)
16170 || !add_dynamic_entry (DT_RELENT, RELOC_SIZE (htab)))
16171 return FALSE;
16172 }
16173 else
16174 {
16175 if (!add_dynamic_entry (DT_RELA, 0)
16176 || !add_dynamic_entry (DT_RELASZ, 0)
16177 || !add_dynamic_entry (DT_RELAENT, RELOC_SIZE (htab)))
16178 return FALSE;
16179 }
252b5132
RH		 16180 }
16181
08d1f311
DJ		 16182 /* If any dynamic relocs apply to a read-only section,
16183 then we need a DT_TEXTREL entry. */
16184 if ((info->flags & DF_TEXTREL) == 0)
8029a119
NC		 16185 elf_link_hash_traverse (& htab->root, elf32_arm_readonly_dynrelocs,
16186 info);
08d1f311 16187
99e4ae17 16188 if ((info->flags & DF_TEXTREL) != 0)
252b5132 16189 {
dc810e39 16190 if (!add_dynamic_entry (DT_TEXTREL, 0))
b34976b6 16191 return FALSE;
252b5132 16192 }
7a2b07ff
NS		 16193 if (htab->vxworks_p
16194 && !elf_vxworks_add_dynamic_entries (output_bfd, info))
16195 return FALSE;
252b5132 16196 }
8532796c 16197#undef add_dynamic_entry
252b5132 16198
b34976b6 16199 return TRUE;
252b5132
RH		 16200}
16201
0855e32b
NS		 16202/* Size sections even though they're not dynamic. We use it to setup
16203 _TLS_MODULE_BASE_, if needed. */
16204
16205static bfd_boolean
16206elf32_arm_always_size_sections (bfd *output_bfd,
99059e56 16207 struct bfd_link_info *info)
0855e32b
NS		 16208{
16209 asection *tls_sec;
16210
0e1862bb 16211 if (bfd_link_relocatable (info))
0855e32b
NS		 16212 return TRUE;
16213
16214 tls_sec = elf_hash_table (info)->tls_sec;
16215
16216 if (tls_sec)
16217 {
16218 struct elf_link_hash_entry *tlsbase;
16219
16220 tlsbase = elf_link_hash_lookup
16221 (elf_hash_table (info), "_TLS_MODULE_BASE_", TRUE, TRUE, FALSE);
16222
16223 if (tlsbase)
99059e56
RM		 16224 {
16225 struct bfd_link_hash_entry *bh = NULL;
0855e32b 16226 const struct elf_backend_data *bed
99059e56 16227 = get_elf_backend_data (output_bfd);
0855e32b 16228
99059e56 16229 if (!(_bfd_generic_link_add_one_symbol
0855e32b
NS		 16230 (info, output_bfd, "_TLS_MODULE_BASE_", BSF_LOCAL,
16231 tls_sec, 0, NULL, FALSE,
16232 bed->collect, &bh)))
16233 return FALSE;
b38cadfb 16234
99059e56
RM		 16235 tlsbase->type = STT_TLS;
16236 tlsbase = (struct elf_link_hash_entry *)bh;
16237 tlsbase->def_regular = 1;
16238 tlsbase->other = STV_HIDDEN;
16239 (*bed->elf_backend_hide_symbol) (info, tlsbase, TRUE);
0855e32b
NS		 16240 }
16241 }
16242 return TRUE;
16243}
16244
252b5132
RH		 16245/* Finish up dynamic symbol handling. We set the contents of various
16246 dynamic sections here. */
16247
b34976b6 16248static bfd_boolean
906e58ca
NC		 16249elf32_arm_finish_dynamic_symbol (bfd * output_bfd,
16250 struct bfd_link_info * info,
16251 struct elf_link_hash_entry * h,
16252 Elf_Internal_Sym * sym)
252b5132 16253{
e5a52504 16254 struct elf32_arm_link_hash_table *htab;
b7693d02 16255 struct elf32_arm_link_hash_entry *eh;
252b5132 16256
e5a52504 16257 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 16258 if (htab == NULL)
16259 return FALSE;
16260
b7693d02 16261 eh = (struct elf32_arm_link_hash_entry *) h;
252b5132
RH		 16262
16263 if (h->plt.offset != (bfd_vma) -1)
16264 {
34e77a92 16265 if (!eh->is_iplt)
e5a52504 16266 {
34e77a92 16267 BFD_ASSERT (h->dynindx != -1);
57460bcf
NC		 16268 if (! elf32_arm_populate_plt_entry (output_bfd, info, &h->plt, &eh->plt,
16269 h->dynindx, 0))
16270 return FALSE;
e5a52504 16271 }
57e8b36a 16272
f5385ebf 16273 if (!h->def_regular)
252b5132
RH		 16274 {
16275 /* Mark the symbol as undefined, rather than as defined in
3a635617 16276 the .plt section. */
252b5132 16277 sym->st_shndx = SHN_UNDEF;
3a635617 16278 /* If the symbol is weak we need to clear the value.
d982ba73
PB		 16279 Otherwise, the PLT entry would provide a definition for
16280 the symbol even if the symbol wasn't defined anywhere,
3a635617
WN		 16281 and so the symbol would never be NULL. Leave the value if
16282 there were any relocations where pointer equality matters
16283 (this is a clue for the dynamic linker, to make function
16284 pointer comparisons work between an application and shared
16285 library). */
97323ad1 16286 if (!h->ref_regular_nonweak || !h->pointer_equality_needed)
d982ba73 16287 sym->st_value = 0;
252b5132 16288 }
34e77a92
RS		 16289 else if (eh->is_iplt && eh->plt.noncall_refcount != 0)
16290 {
16291 /* At least one non-call relocation references this .iplt entry,
16292 so the .iplt entry is the function's canonical address. */
16293 sym->st_info = ELF_ST_INFO (ELF_ST_BIND (sym->st_info), STT_FUNC);
39d911fc 16294 ARM_SET_SYM_BRANCH_TYPE (sym->st_target_internal, ST_BRANCH_TO_ARM);
34e77a92
RS		 16295 sym->st_shndx = (_bfd_elf_section_from_bfd_section
16296 (output_bfd, htab->root.iplt->output_section));
16297 sym->st_value = (h->plt.offset
16298 + htab->root.iplt->output_section->vma
16299 + htab->root.iplt->output_offset);
16300 }
252b5132
RH		 16301 }
16302
f5385ebf 16303 if (h->needs_copy)
252b5132
RH		 16304 {
16305 asection * s;
947216bf 16306 Elf_Internal_Rela rel;
252b5132
RH		 16307
16308 /* This symbol needs a copy reloc. Set it up. */
252b5132
RH		 16309 BFD_ASSERT (h->dynindx != -1
16310 && (h->root.type == bfd_link_hash_defined
16311 || h->root.type == bfd_link_hash_defweak));
16312
362d30a1 16313 s = htab->srelbss;
252b5132
RH		 16314 BFD_ASSERT (s != NULL);
16315
00a97672 16316 rel.r_addend = 0;
252b5132
RH		 16317 rel.r_offset = (h->root.u.def.value
16318 + h->root.u.def.section->output_section->vma
16319 + h->root.u.def.section->output_offset);
16320 rel.r_info = ELF32_R_INFO (h->dynindx, R_ARM_COPY);
47beaa6a 16321 elf32_arm_add_dynreloc (output_bfd, info, s, &rel);
252b5132
RH		 16322 }
16323
00a97672
RS		 16324 /* Mark _DYNAMIC and _GLOBAL_OFFSET_TABLE_ as absolute. On VxWorks,
16325 the _GLOBAL_OFFSET_TABLE_ symbol is not absolute: it is relative
16326 to the ".got" section. */
9637f6ef 16327 if (h == htab->root.hdynamic
00a97672 16328 || (!htab->vxworks_p && h == htab->root.hgot))
252b5132
RH		 16329 sym->st_shndx = SHN_ABS;
16330
b34976b6 16331 return TRUE;
252b5132
RH		 16332}
16333
0855e32b
NS		 16334static void
16335arm_put_trampoline (struct elf32_arm_link_hash_table *htab, bfd *output_bfd,
16336 void *contents,
16337 const unsigned long *template, unsigned count)
16338{
16339 unsigned ix;
b38cadfb 16340
0855e32b
NS		 16341 for (ix = 0; ix != count; ix++)
16342 {
16343 unsigned long insn = template[ix];
16344
16345 /* Emit mov pc,rx if bx is not permitted. */
16346 if (htab->fix_v4bx == 1 && (insn & 0x0ffffff0) == 0x012fff10)
16347 insn = (insn & 0xf000000f) | 0x01a0f000;
16348 put_arm_insn (htab, output_bfd, insn, (char *)contents + ix*4);
16349 }
16350}
16351
99059e56
RM		 16352/* Install the special first PLT entry for elf32-arm-nacl. Unlike
16353 other variants, NaCl needs this entry in a static executable's
16354 .iplt too. When we're handling that case, GOT_DISPLACEMENT is
16355 zero. For .iplt really only the last bundle is useful, and .iplt
16356 could have a shorter first entry, with each individual PLT entry's
16357 relative branch calculated differently so it targets the last
16358 bundle instead of the instruction before it (labelled .Lplt_tail
16359 above). But it's simpler to keep the size and layout of PLT0
16360 consistent with the dynamic case, at the cost of some dead code at
16361 the start of .iplt and the one dead store to the stack at the start
16362 of .Lplt_tail. */
16363static void
16364arm_nacl_put_plt0 (struct elf32_arm_link_hash_table *htab, bfd *output_bfd,
16365 asection *plt, bfd_vma got_displacement)
16366{
16367 unsigned int i;
16368
16369 put_arm_insn (htab, output_bfd,
16370 elf32_arm_nacl_plt0_entry[0]
16371 | arm_movw_immediate (got_displacement),
16372 plt->contents + 0);
16373 put_arm_insn (htab, output_bfd,
16374 elf32_arm_nacl_plt0_entry[1]
16375 | arm_movt_immediate (got_displacement),
16376 plt->contents + 4);
16377
16378 for (i = 2; i < ARRAY_SIZE (elf32_arm_nacl_plt0_entry); ++i)
16379 put_arm_insn (htab, output_bfd,
16380 elf32_arm_nacl_plt0_entry[i],
16381 plt->contents + (i * 4));
16382}
16383
252b5132
RH		 16384/* Finish up the dynamic sections. */
16385
b34976b6 16386static bfd_boolean
57e8b36a 16387elf32_arm_finish_dynamic_sections (bfd * output_bfd, struct bfd_link_info * info)
252b5132
RH		 16388{
16389 bfd * dynobj;
16390 asection * sgot;
16391 asection * sdyn;
4dfe6ac6
NC		 16392 struct elf32_arm_link_hash_table *htab;
16393
16394 htab = elf32_arm_hash_table (info);
16395 if (htab == NULL)
16396 return FALSE;
252b5132
RH		 16397
16398 dynobj = elf_hash_table (info)->dynobj;
16399
362d30a1 16400 sgot = htab->root.sgotplt;
894891db
NC		 16401 /* A broken linker script might have discarded the dynamic sections.
16402 Catch this here so that we do not seg-fault later on. */
16403 if (sgot != NULL && bfd_is_abs_section (sgot->output_section))
16404 return FALSE;
3d4d4302 16405 sdyn = bfd_get_linker_section (dynobj, ".dynamic");
252b5132
RH		 16406
16407 if (elf_hash_table (info)->dynamic_sections_created)
16408 {
16409 asection *splt;
16410 Elf32_External_Dyn *dyncon, *dynconend;
16411
362d30a1 16412 splt = htab->root.splt;
24a1ba0f 16413 BFD_ASSERT (splt != NULL && sdyn != NULL);
cbc704f3 16414 BFD_ASSERT (htab->symbian_p || sgot != NULL);
252b5132
RH		 16415
16416 dyncon = (Elf32_External_Dyn *) sdyn->contents;
eea6121a 16417 dynconend = (Elf32_External_Dyn *) (sdyn->contents + sdyn->size);
9b485d32 16418
252b5132
RH		 16419 for (; dyncon < dynconend; dyncon++)
16420 {
16421 Elf_Internal_Dyn dyn;
16422 const char * name;
16423 asection * s;
16424
16425 bfd_elf32_swap_dyn_in (dynobj, dyncon, &dyn);
16426
16427 switch (dyn.d_tag)
16428 {
229fcec5
MM		 16429 unsigned int type;
16430
252b5132 16431 default:
7a2b07ff
NS		 16432 if (htab->vxworks_p
16433 && elf_vxworks_finish_dynamic_entry (output_bfd, &dyn))
16434 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
252b5132
RH		 16435 break;
16436
229fcec5
MM		 16437 case DT_HASH:
16438 name = ".hash";
16439 goto get_vma_if_bpabi;
16440 case DT_STRTAB:
16441 name = ".dynstr";
16442 goto get_vma_if_bpabi;
16443 case DT_SYMTAB:
16444 name = ".dynsym";
16445 goto get_vma_if_bpabi;
c0042f5d
MM		 16446 case DT_VERSYM:
16447 name = ".gnu.version";
16448 goto get_vma_if_bpabi;
16449 case DT_VERDEF:
16450 name = ".gnu.version_d";
16451 goto get_vma_if_bpabi;
16452 case DT_VERNEED:
16453 name = ".gnu.version_r";
16454 goto get_vma_if_bpabi;
16455
252b5132 16456 case DT_PLTGOT:
4ade44b7 16457 name = htab->symbian_p ? ".got" : ".got.plt";
252b5132
RH		 16458 goto get_vma;
16459 case DT_JMPREL:
00a97672 16460 name = RELOC_SECTION (htab, ".plt");
252b5132 16461 get_vma:
4ade44b7 16462 s = bfd_get_linker_section (dynobj, name);
05456594
NC		 16463 if (s == NULL)
16464 {
4eca0228 16465 _bfd_error_handler
4ade44b7 16466 (_("could not find section %s"), name);
05456594
NC		 16467 bfd_set_error (bfd_error_invalid_operation);
16468 return FALSE;
16469 }
229fcec5 16470 if (!htab->symbian_p)
4ade44b7 16471 dyn.d_un.d_ptr = s->output_section->vma + s->output_offset;
229fcec5
MM		 16472 else
16473 /* In the BPABI, tags in the PT_DYNAMIC section point
16474 at the file offset, not the memory address, for the
16475 convenience of the post linker. */
4ade44b7 16476 dyn.d_un.d_ptr = s->output_section->filepos + s->output_offset;
252b5132
RH		 16477 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
16478 break;
16479
229fcec5
MM		 16480 get_vma_if_bpabi:
16481 if (htab->symbian_p)
16482 goto get_vma;
16483 break;
16484
252b5132 16485 case DT_PLTRELSZ:
362d30a1 16486 s = htab->root.srelplt;
252b5132 16487 BFD_ASSERT (s != NULL);
eea6121a 16488 dyn.d_un.d_val = s->size;
252b5132
RH		 16489 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
16490 break;
906e58ca 16491
252b5132 16492 case DT_RELSZ:
00a97672 16493 case DT_RELASZ:
229fcec5
MM		 16494 case DT_REL:
16495 case DT_RELA:
229fcec5
MM		 16496 /* In the BPABI, the DT_REL tag must point at the file
16497 offset, not the VMA, of the first relocation
16498 section. So, we use code similar to that in
16499 elflink.c, but do not check for SHF_ALLOC on the
64f52338
AM		 16500 relocation section, since relocation sections are
16501 never allocated under the BPABI. PLT relocs are also
16502 included. */
229fcec5
MM		 16503 if (htab->symbian_p)
16504 {
16505 unsigned int i;
16506 type = ((dyn.d_tag == DT_REL || dyn.d_tag == DT_RELSZ)
16507 ? SHT_REL : SHT_RELA);
16508 dyn.d_un.d_val = 0;
16509 for (i = 1; i < elf_numsections (output_bfd); i++)
16510 {
906e58ca 16511 Elf_Internal_Shdr *hdr
229fcec5
MM		 16512 = elf_elfsections (output_bfd)[i];
16513 if (hdr->sh_type == type)
16514 {
906e58ca 16515 if (dyn.d_tag == DT_RELSZ
229fcec5
MM		 16516 || dyn.d_tag == DT_RELASZ)
16517 dyn.d_un.d_val += hdr->sh_size;
de52dba4
AM		 16518 else if ((ufile_ptr) hdr->sh_offset
16519 <= dyn.d_un.d_val - 1)
229fcec5
MM		 16520 dyn.d_un.d_val = hdr->sh_offset;
16521 }
16522 }
16523 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
16524 }
252b5132 16525 break;
88f7bcd5 16526
0855e32b 16527 case DT_TLSDESC_PLT:
99059e56 16528 s = htab->root.splt;
0855e32b
NS		 16529 dyn.d_un.d_ptr = (s->output_section->vma + s->output_offset
16530 + htab->dt_tlsdesc_plt);
16531 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
16532 break;
16533
16534 case DT_TLSDESC_GOT:
99059e56 16535 s = htab->root.sgot;
0855e32b 16536 dyn.d_un.d_ptr = (s->output_section->vma + s->output_offset
99059e56 16537 + htab->dt_tlsdesc_got);
0855e32b
NS		 16538 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
16539 break;
16540
88f7bcd5
NC		 16541 /* Set the bottom bit of DT_INIT/FINI if the
16542 corresponding function is Thumb. */
16543 case DT_INIT:
16544 name = info->init_function;
16545 goto get_sym;
16546 case DT_FINI:
16547 name = info->fini_function;
16548 get_sym:
16549 /* If it wasn't set by elf_bfd_final_link
4cc11e76 16550 then there is nothing to adjust. */
88f7bcd5
NC		 16551 if (dyn.d_un.d_val != 0)
16552 {
16553 struct elf_link_hash_entry * eh;
16554
16555 eh = elf_link_hash_lookup (elf_hash_table (info), name,
b34976b6 16556 FALSE, FALSE, TRUE);
39d911fc
TP		 16557 if (eh != NULL
16558 && ARM_GET_SYM_BRANCH_TYPE (eh->target_internal)
16559 == ST_BRANCH_TO_THUMB)
88f7bcd5
NC		 16560 {
16561 dyn.d_un.d_val |= 1;
b34976b6 16562 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
88f7bcd5
NC		 16563 }
16564 }
16565 break;
252b5132
RH		 16566 }
16567 }
16568
24a1ba0f 16569 /* Fill in the first entry in the procedure linkage table. */
4dfe6ac6 16570 if (splt->size > 0 && htab->plt_header_size)
f7a74f8c 16571 {
00a97672
RS		 16572 const bfd_vma *plt0_entry;
16573 bfd_vma got_address, plt_address, got_displacement;
16574
16575 /* Calculate the addresses of the GOT and PLT. */
16576 got_address = sgot->output_section->vma + sgot->output_offset;
16577 plt_address = splt->output_section->vma + splt->output_offset;
16578
16579 if (htab->vxworks_p)
16580 {
16581 /* The VxWorks GOT is relocated by the dynamic linker.
16582 Therefore, we must emit relocations rather than simply
16583 computing the values now. */
16584 Elf_Internal_Rela rel;
16585
16586 plt0_entry = elf32_arm_vxworks_exec_plt0_entry;
52ab56c2
PB		 16587 put_arm_insn (htab, output_bfd, plt0_entry[0],
16588 splt->contents + 0);
16589 put_arm_insn (htab, output_bfd, plt0_entry[1],
16590 splt->contents + 4);
16591 put_arm_insn (htab, output_bfd, plt0_entry[2],
16592 splt->contents + 8);
00a97672
RS		 16593 bfd_put_32 (output_bfd, got_address, splt->contents + 12);
16594
8029a119 16595 /* Generate a relocation for _GLOBAL_OFFSET_TABLE_. */
00a97672
RS		 16596 rel.r_offset = plt_address + 12;
16597 rel.r_info = ELF32_R_INFO (htab->root.hgot->indx, R_ARM_ABS32);
16598 rel.r_addend = 0;
16599 SWAP_RELOC_OUT (htab) (output_bfd, &rel,
16600 htab->srelplt2->contents);
16601 }
b38cadfb 16602 else if (htab->nacl_p)
99059e56
RM		 16603 arm_nacl_put_plt0 (htab, output_bfd, splt,
16604 got_address + 8 - (plt_address + 16));
eed94f8f
NC		 16605 else if (using_thumb_only (htab))
16606 {
16607 got_displacement = got_address - (plt_address + 12);
16608
16609 plt0_entry = elf32_thumb2_plt0_entry;
16610 put_arm_insn (htab, output_bfd, plt0_entry[0],
16611 splt->contents + 0);
16612 put_arm_insn (htab, output_bfd, plt0_entry[1],
16613 splt->contents + 4);
16614 put_arm_insn (htab, output_bfd, plt0_entry[2],
16615 splt->contents + 8);
16616
16617 bfd_put_32 (output_bfd, got_displacement, splt->contents + 12);
16618 }
00a97672
RS		 16619 else
16620 {
16621 got_displacement = got_address - (plt_address + 16);
16622
16623 plt0_entry = elf32_arm_plt0_entry;
52ab56c2
PB		 16624 put_arm_insn (htab, output_bfd, plt0_entry[0],
16625 splt->contents + 0);
16626 put_arm_insn (htab, output_bfd, plt0_entry[1],
16627 splt->contents + 4);
16628 put_arm_insn (htab, output_bfd, plt0_entry[2],
16629 splt->contents + 8);
16630 put_arm_insn (htab, output_bfd, plt0_entry[3],
16631 splt->contents + 12);
5e681ec4 16632
5e681ec4 16633#ifdef FOUR_WORD_PLT
00a97672
RS		 16634 /* The displacement value goes in the otherwise-unused
16635 last word of the second entry. */
16636 bfd_put_32 (output_bfd, got_displacement, splt->contents + 28);
5e681ec4 16637#else
00a97672 16638 bfd_put_32 (output_bfd, got_displacement, splt->contents + 16);
5e681ec4 16639#endif
00a97672 16640 }
f7a74f8c 16641 }
252b5132
RH		 16642
16643 /* UnixWare sets the entsize of .plt to 4, although that doesn't
16644 really seem like the right value. */
74541ad4
AM		 16645 if (splt->output_section->owner == output_bfd)
16646 elf_section_data (splt->output_section)->this_hdr.sh_entsize = 4;
00a97672 16647
0855e32b
NS		 16648 if (htab->dt_tlsdesc_plt)
16649 {
16650 bfd_vma got_address
16651 = sgot->output_section->vma + sgot->output_offset;
16652 bfd_vma gotplt_address = (htab->root.sgot->output_section->vma
16653 + htab->root.sgot->output_offset);
16654 bfd_vma plt_address
16655 = splt->output_section->vma + splt->output_offset;
16656
b38cadfb 16657 arm_put_trampoline (htab, output_bfd,
0855e32b
NS		 16658 splt->contents + htab->dt_tlsdesc_plt,
16659 dl_tlsdesc_lazy_trampoline, 6);
16660
16661 bfd_put_32 (output_bfd,
16662 gotplt_address + htab->dt_tlsdesc_got
16663 - (plt_address + htab->dt_tlsdesc_plt)
16664 - dl_tlsdesc_lazy_trampoline[6],
16665 splt->contents + htab->dt_tlsdesc_plt + 24);
16666 bfd_put_32 (output_bfd,
16667 got_address - (plt_address + htab->dt_tlsdesc_plt)
16668 - dl_tlsdesc_lazy_trampoline[7],
16669 splt->contents + htab->dt_tlsdesc_plt + 24 + 4);
16670 }
16671
16672 if (htab->tls_trampoline)
16673 {
b38cadfb 16674 arm_put_trampoline (htab, output_bfd,
0855e32b
NS		 16675 splt->contents + htab->tls_trampoline,
16676 tls_trampoline, 3);
16677#ifdef FOUR_WORD_PLT
16678 bfd_put_32 (output_bfd, 0x00000000,
16679 splt->contents + htab->tls_trampoline + 12);
b38cadfb 16680#endif
0855e32b
NS		 16681 }
16682
0e1862bb
L		 16683 if (htab->vxworks_p
16684 && !bfd_link_pic (info)
16685 && htab->root.splt->size > 0)
00a97672
RS		 16686 {
16687 /* Correct the .rel(a).plt.unloaded relocations. They will have
16688 incorrect symbol indexes. */
16689 int num_plts;
eed62c48 16690 unsigned char *p;
00a97672 16691
362d30a1 16692 num_plts = ((htab->root.splt->size - htab->plt_header_size)
00a97672
RS		 16693 / htab->plt_entry_size);
16694 p = htab->srelplt2->contents + RELOC_SIZE (htab);
16695
16696 for (; num_plts; num_plts--)
16697 {
16698 Elf_Internal_Rela rel;
16699
16700 SWAP_RELOC_IN (htab) (output_bfd, p, &rel);
16701 rel.r_info = ELF32_R_INFO (htab->root.hgot->indx, R_ARM_ABS32);
16702 SWAP_RELOC_OUT (htab) (output_bfd, &rel, p);
16703 p += RELOC_SIZE (htab);
16704
16705 SWAP_RELOC_IN (htab) (output_bfd, p, &rel);
16706 rel.r_info = ELF32_R_INFO (htab->root.hplt->indx, R_ARM_ABS32);
16707 SWAP_RELOC_OUT (htab) (output_bfd, &rel, p);
16708 p += RELOC_SIZE (htab);
16709 }
16710 }
252b5132
RH		 16711 }
16712
99059e56
RM		 16713 if (htab->nacl_p && htab->root.iplt != NULL && htab->root.iplt->size > 0)
16714 /* NaCl uses a special first entry in .iplt too. */
16715 arm_nacl_put_plt0 (htab, output_bfd, htab->root.iplt, 0);
16716
252b5132 16717 /* Fill in the first three entries in the global offset table. */
229fcec5 16718 if (sgot)
252b5132 16719 {
229fcec5
MM		 16720 if (sgot->size > 0)
16721 {
16722 if (sdyn == NULL)
16723 bfd_put_32 (output_bfd, (bfd_vma) 0, sgot->contents);
16724 else
16725 bfd_put_32 (output_bfd,
16726 sdyn->output_section->vma + sdyn->output_offset,
16727 sgot->contents);
16728 bfd_put_32 (output_bfd, (bfd_vma) 0, sgot->contents + 4);
16729 bfd_put_32 (output_bfd, (bfd_vma) 0, sgot->contents + 8);
16730 }
252b5132 16731
229fcec5
MM		 16732 elf_section_data (sgot->output_section)->this_hdr.sh_entsize = 4;
16733 }
252b5132 16734
b34976b6 16735 return TRUE;
252b5132
RH		 16736}
16737
ba96a88f 16738static void
57e8b36a 16739elf32_arm_post_process_headers (bfd * abfd, struct bfd_link_info * link_info ATTRIBUTE_UNUSED)
ba96a88f 16740{
9b485d32 16741 Elf_Internal_Ehdr * i_ehdrp; /* ELF file header, internal form. */
e489d0ae 16742 struct elf32_arm_link_hash_table *globals;
ac4c9b04 16743 struct elf_segment_map *m;
ba96a88f
NC		 16744
16745 i_ehdrp = elf_elfheader (abfd);
16746
94a3258f
PB		 16747 if (EF_ARM_EABI_VERSION (i_ehdrp->e_flags) == EF_ARM_EABI_UNKNOWN)
16748 i_ehdrp->e_ident[EI_OSABI] = ELFOSABI_ARM;
16749 else
7394f108 16750 _bfd_elf_post_process_headers (abfd, link_info);
ba96a88f 16751 i_ehdrp->e_ident[EI_ABIVERSION] = ARM_ELF_ABI_VERSION;
e489d0ae 16752
93204d3a
PB		 16753 if (link_info)
16754 {
16755 globals = elf32_arm_hash_table (link_info);
4dfe6ac6 16756 if (globals != NULL && globals->byteswap_code)
93204d3a
PB		 16757 i_ehdrp->e_flags |= EF_ARM_BE8;
16758 }
3bfcb652
NC		 16759
16760 if (EF_ARM_EABI_VERSION (i_ehdrp->e_flags) == EF_ARM_EABI_VER5
16761 && ((i_ehdrp->e_type == ET_DYN) || (i_ehdrp->e_type == ET_EXEC)))
16762 {
16763 int abi = bfd_elf_get_obj_attr_int (abfd, OBJ_ATTR_PROC, Tag_ABI_VFP_args);
5c294fee 16764 if (abi == AEABI_VFP_args_vfp)
3bfcb652
NC		 16765 i_ehdrp->e_flags |= EF_ARM_ABI_FLOAT_HARD;
16766 else
16767 i_ehdrp->e_flags |= EF_ARM_ABI_FLOAT_SOFT;
16768 }
ac4c9b04
MG		 16769
16770 /* Scan segment to set p_flags attribute if it contains only sections with
f0728ee3 16771 SHF_ARM_PURECODE flag. */
ac4c9b04
MG		 16772 for (m = elf_seg_map (abfd); m != NULL; m = m->next)
16773 {
16774 unsigned int j;
16775
16776 if (m->count == 0)
16777 continue;
16778 for (j = 0; j < m->count; j++)
16779 {
f0728ee3 16780 if (!(elf_section_flags (m->sections[j]) & SHF_ARM_PURECODE))
ac4c9b04
MG		 16781 break;
16782 }
16783 if (j == m->count)
16784 {
16785 m->p_flags = PF_X;
16786 m->p_flags_valid = 1;
16787 }
16788 }
ba96a88f
NC		 16789}
16790
99e4ae17 16791static enum elf_reloc_type_class
7e612e98
AM		 16792elf32_arm_reloc_type_class (const struct bfd_link_info *info ATTRIBUTE_UNUSED,
16793 const asection *rel_sec ATTRIBUTE_UNUSED,
16794 const Elf_Internal_Rela *rela)
99e4ae17 16795{
f51e552e 16796 switch ((int) ELF32_R_TYPE (rela->r_info))
99e4ae17
AJ		 16797 {
16798 case R_ARM_RELATIVE:
16799 return reloc_class_relative;
16800 case R_ARM_JUMP_SLOT:
16801 return reloc_class_plt;
16802 case R_ARM_COPY:
16803 return reloc_class_copy;
109575d7
JW		 16804 case R_ARM_IRELATIVE:
16805 return reloc_class_ifunc;
99e4ae17
AJ		 16806 default:
16807 return reloc_class_normal;
16808 }
16809}
16810
e489d0ae 16811static void
57e8b36a 16812elf32_arm_final_write_processing (bfd *abfd, bfd_boolean linker ATTRIBUTE_UNUSED)
e16bb312 16813{
5a6c6817 16814 bfd_arm_update_notes (abfd, ARM_NOTE_SECTION);
e16bb312
NC		 16815}
16816
40a18ebd
NC		 16817/* Return TRUE if this is an unwinding table entry. */
16818
16819static bfd_boolean
16820is_arm_elf_unwind_section_name (bfd * abfd ATTRIBUTE_UNUSED, const char * name)
16821{
0112cd26
NC		 16822 return (CONST_STRNEQ (name, ELF_STRING_ARM_unwind)
16823 || CONST_STRNEQ (name, ELF_STRING_ARM_unwind_once));
40a18ebd
NC		 16824}
16825
16826
16827/* Set the type and flags for an ARM section. We do this by
16828 the section name, which is a hack, but ought to work. */
16829
16830static bfd_boolean
16831elf32_arm_fake_sections (bfd * abfd, Elf_Internal_Shdr * hdr, asection * sec)
16832{
16833 const char * name;
16834
16835 name = bfd_get_section_name (abfd, sec);
16836
16837 if (is_arm_elf_unwind_section_name (abfd, name))
16838 {
16839 hdr->sh_type = SHT_ARM_EXIDX;
16840 hdr->sh_flags |= SHF_LINK_ORDER;
16841 }
ac4c9b04 16842
f0728ee3
AV		 16843 if (sec->flags & SEC_ELF_PURECODE)
16844 hdr->sh_flags |= SHF_ARM_PURECODE;
ac4c9b04 16845
40a18ebd
NC		 16846 return TRUE;
16847}
16848
6dc132d9
L		 16849/* Handle an ARM specific section when reading an object file. This is
16850 called when bfd_section_from_shdr finds a section with an unknown
16851 type. */
40a18ebd
NC		 16852
16853static bfd_boolean
16854elf32_arm_section_from_shdr (bfd *abfd,
16855 Elf_Internal_Shdr * hdr,
6dc132d9
L		 16856 const char *name,
16857 int shindex)
40a18ebd
NC		 16858{
16859 /* There ought to be a place to keep ELF backend specific flags, but
16860 at the moment there isn't one. We just keep track of the
16861 sections by their name, instead. Fortunately, the ABI gives
16862 names for all the ARM specific sections, so we will probably get
16863 away with this. */
16864 switch (hdr->sh_type)
16865 {
16866 case SHT_ARM_EXIDX:
0951f019
RE		 16867 case SHT_ARM_PREEMPTMAP:
16868 case SHT_ARM_ATTRIBUTES:
40a18ebd
NC		 16869 break;
16870
16871 default:
16872 return FALSE;
16873 }
16874
6dc132d9 16875 if (! _bfd_elf_make_section_from_shdr (abfd, hdr, name, shindex))
40a18ebd
NC		 16876 return FALSE;
16877
16878 return TRUE;
16879}
e489d0ae 16880
44444f50
NC		 16881static _arm_elf_section_data *
16882get_arm_elf_section_data (asection * sec)
16883{
47b2e99c
JZ		 16884 if (sec && sec->owner && is_arm_elf (sec->owner))
16885 return elf32_arm_section_data (sec);
44444f50
NC		 16886 else
16887 return NULL;
8e3de13a
NC		 16888}
16889
4e617b1e
PB		 16890typedef struct
16891{
57402f1e 16892 void *flaginfo;
4e617b1e 16893 struct bfd_link_info *info;
91a5743d
PB		 16894 asection *sec;
16895 int sec_shndx;
6e0b88f1
AM		 16896 int (*func) (void *, const char *, Elf_Internal_Sym *,
16897 asection *, struct elf_link_hash_entry *);
4e617b1e
PB		 16898} output_arch_syminfo;
16899
16900enum map_symbol_type
16901{
16902 ARM_MAP_ARM,
16903 ARM_MAP_THUMB,
16904 ARM_MAP_DATA
16905};
16906
16907
7413f23f 16908/* Output a single mapping symbol. */
4e617b1e
PB		 16909
16910static bfd_boolean
7413f23f
DJ		 16911elf32_arm_output_map_sym (output_arch_syminfo *osi,
16912 enum map_symbol_type type,
16913 bfd_vma offset)
4e617b1e
PB		 16914{
16915 static const char *names[3] = {"$a", "$t", "$d"};
4e617b1e
PB		 16916 Elf_Internal_Sym sym;
16917
91a5743d
PB		 16918 sym.st_value = osi->sec->output_section->vma
16919 + osi->sec->output_offset
16920 + offset;
4e617b1e
PB		 16921 sym.st_size = 0;
16922 sym.st_other = 0;
16923 sym.st_info = ELF_ST_INFO (STB_LOCAL, STT_NOTYPE);
91a5743d 16924 sym.st_shndx = osi->sec_shndx;
35fc36a8 16925 sym.st_target_internal = 0;
fe33d2fa 16926 elf32_arm_section_map_add (osi->sec, names[type][1], offset);
57402f1e 16927 return osi->func (osi->flaginfo, names[type], &sym, osi->sec, NULL) == 1;
4e617b1e
PB		 16928}
16929
34e77a92
RS		 16930/* Output mapping symbols for the PLT entry described by ROOT_PLT and ARM_PLT.
16931 IS_IPLT_ENTRY_P says whether the PLT is in .iplt rather than .plt. */
4e617b1e
PB		 16932
16933static bfd_boolean
34e77a92
RS		 16934elf32_arm_output_plt_map_1 (output_arch_syminfo *osi,
16935 bfd_boolean is_iplt_entry_p,
16936 union gotplt_union *root_plt,
16937 struct arm_plt_info *arm_plt)
4e617b1e 16938{
4e617b1e 16939 struct elf32_arm_link_hash_table *htab;
34e77a92 16940 bfd_vma addr, plt_header_size;
4e617b1e 16941
34e77a92 16942 if (root_plt->offset == (bfd_vma) -1)
4e617b1e
PB		 16943 return TRUE;
16944
4dfe6ac6
NC		 16945 htab = elf32_arm_hash_table (osi->info);
16946 if (htab == NULL)
16947 return FALSE;
16948
34e77a92
RS		 16949 if (is_iplt_entry_p)
16950 {
16951 osi->sec = htab->root.iplt;
16952 plt_header_size = 0;
16953 }
16954 else
16955 {
16956 osi->sec = htab->root.splt;
16957 plt_header_size = htab->plt_header_size;
16958 }
16959 osi->sec_shndx = (_bfd_elf_section_from_bfd_section
16960 (osi->info->output_bfd, osi->sec->output_section));
16961
16962 addr = root_plt->offset & -2;
4e617b1e
PB		 16963 if (htab->symbian_p)
16964 {
7413f23f 16965 if (!elf32_arm_output_map_sym (osi, ARM_MAP_ARM, addr))
4e617b1e 16966 return FALSE;
7413f23f 16967 if (!elf32_arm_output_map_sym (osi, ARM_MAP_DATA, addr + 4))
4e617b1e
PB		 16968 return FALSE;
16969 }
16970 else if (htab->vxworks_p)
16971 {
7413f23f 16972 if (!elf32_arm_output_map_sym (osi, ARM_MAP_ARM, addr))
4e617b1e 16973 return FALSE;
7413f23f 16974 if (!elf32_arm_output_map_sym (osi, ARM_MAP_DATA, addr + 8))
4e617b1e 16975 return FALSE;
7413f23f 16976 if (!elf32_arm_output_map_sym (osi, ARM_MAP_ARM, addr + 12))
4e617b1e 16977 return FALSE;
7413f23f 16978 if (!elf32_arm_output_map_sym (osi, ARM_MAP_DATA, addr + 20))
4e617b1e
PB		 16979 return FALSE;
16980 }
b38cadfb
NC		 16981 else if (htab->nacl_p)
16982 {
16983 if (!elf32_arm_output_map_sym (osi, ARM_MAP_ARM, addr))
16984 return FALSE;
16985 }
eed94f8f
NC		 16986 else if (using_thumb_only (htab))
16987 {
16988 if (!elf32_arm_output_map_sym (osi, ARM_MAP_THUMB, addr))
16989 return FALSE;
6a631e86 16990 }
4e617b1e
PB		 16991 else
16992 {
34e77a92 16993 bfd_boolean thumb_stub_p;
bd97cb95 16994
34e77a92
RS		 16995 thumb_stub_p = elf32_arm_plt_needs_thumb_stub_p (osi->info, arm_plt);
16996 if (thumb_stub_p)
4e617b1e 16997 {
7413f23f 16998 if (!elf32_arm_output_map_sym (osi, ARM_MAP_THUMB, addr - 4))
4e617b1e
PB		 16999 return FALSE;
17000 }
17001#ifdef FOUR_WORD_PLT
7413f23f 17002 if (!elf32_arm_output_map_sym (osi, ARM_MAP_ARM, addr))
4e617b1e 17003 return FALSE;
7413f23f 17004 if (!elf32_arm_output_map_sym (osi, ARM_MAP_DATA, addr + 12))
4e617b1e
PB		 17005 return FALSE;
17006#else
906e58ca 17007 /* A three-word PLT with no Thumb thunk contains only Arm code,
4e617b1e
PB		 17008 so only need to output a mapping symbol for the first PLT entry and
17009 entries with thumb thunks. */
34e77a92 17010 if (thumb_stub_p || addr == plt_header_size)
4e617b1e 17011 {
7413f23f 17012 if (!elf32_arm_output_map_sym (osi, ARM_MAP_ARM, addr))
4e617b1e
PB		 17013 return FALSE;
17014 }
17015#endif
17016 }
17017
17018 return TRUE;
17019}
17020
34e77a92
RS		 17021/* Output mapping symbols for PLT entries associated with H. */
17022
17023static bfd_boolean
17024elf32_arm_output_plt_map (struct elf_link_hash_entry *h, void *inf)
17025{
17026 output_arch_syminfo *osi = (output_arch_syminfo *) inf;
17027 struct elf32_arm_link_hash_entry *eh;
17028
17029 if (h->root.type == bfd_link_hash_indirect)
17030 return TRUE;
17031
17032 if (h->root.type == bfd_link_hash_warning)
17033 /* When warning symbols are created, they **replace** the "real"
17034 entry in the hash table, thus we never get to see the real
17035 symbol in a hash traversal. So look at it now. */
17036 h = (struct elf_link_hash_entry *) h->root.u.i.link;
17037
17038 eh = (struct elf32_arm_link_hash_entry *) h;
17039 return elf32_arm_output_plt_map_1 (osi, SYMBOL_CALLS_LOCAL (osi->info, h),
17040 &h->plt, &eh->plt);
17041}
17042
4f4faa4d
TP		 17043/* Bind a veneered symbol to its veneer identified by its hash entry
17044 STUB_ENTRY. The veneered location thus loose its symbol. */
17045
17046static void
17047arm_stub_claim_sym (struct elf32_arm_stub_hash_entry *stub_entry)
17048{
17049 struct elf32_arm_link_hash_entry *hash = stub_entry->h;
17050
17051 BFD_ASSERT (hash);
17052 hash->root.root.u.def.section = stub_entry->stub_sec;
17053 hash->root.root.u.def.value = stub_entry->stub_offset;
17054 hash->root.size = stub_entry->stub_size;
17055}
17056
7413f23f
DJ		 17057/* Output a single local symbol for a generated stub. */
17058
17059static bfd_boolean
17060elf32_arm_output_stub_sym (output_arch_syminfo *osi, const char *name,
17061 bfd_vma offset, bfd_vma size)
17062{
7413f23f
DJ		 17063 Elf_Internal_Sym sym;
17064
7413f23f
DJ		 17065 sym.st_value = osi->sec->output_section->vma
17066 + osi->sec->output_offset
17067 + offset;
17068 sym.st_size = size;
17069 sym.st_other = 0;
17070 sym.st_info = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
17071 sym.st_shndx = osi->sec_shndx;
35fc36a8 17072 sym.st_target_internal = 0;
57402f1e 17073 return osi->func (osi->flaginfo, name, &sym, osi->sec, NULL) == 1;
7413f23f 17074}
4e617b1e 17075
da5938a2 17076static bfd_boolean
8029a119
NC		 17077arm_map_one_stub (struct bfd_hash_entry * gen_entry,
17078 void * in_arg)
da5938a2
NC		 17079{
17080 struct elf32_arm_stub_hash_entry *stub_entry;
da5938a2
NC		 17081 asection *stub_sec;
17082 bfd_vma addr;
7413f23f 17083 char *stub_name;
9a008db3 17084 output_arch_syminfo *osi;
d3ce72d0 17085 const insn_sequence *template_sequence;
461a49ca
DJ		 17086 enum stub_insn_type prev_type;
17087 int size;
17088 int i;
17089 enum map_symbol_type sym_type;
da5938a2
NC		 17090
17091 /* Massage our args to the form they really have. */
17092 stub_entry = (struct elf32_arm_stub_hash_entry *) gen_entry;
9a008db3 17093 osi = (output_arch_syminfo *) in_arg;
da5938a2 17094
da5938a2
NC		 17095 stub_sec = stub_entry->stub_sec;
17096
17097 /* Ensure this stub is attached to the current section being
7413f23f 17098 processed. */
da5938a2
NC		 17099 if (stub_sec != osi->sec)
17100 return TRUE;
17101
7413f23f 17102 addr = (bfd_vma) stub_entry->stub_offset;
d3ce72d0 17103 template_sequence = stub_entry->stub_template;
4f4faa4d
TP		 17104
17105 if (arm_stub_sym_claimed (stub_entry->stub_type))
17106 arm_stub_claim_sym (stub_entry);
17107 else
7413f23f 17108 {
4f4faa4d
TP		 17109 stub_name = stub_entry->output_name;
17110 switch (template_sequence[0].type)
17111 {
17112 case ARM_TYPE:
17113 if (!elf32_arm_output_stub_sym (osi, stub_name, addr,
17114 stub_entry->stub_size))
17115 return FALSE;
17116 break;
17117 case THUMB16_TYPE:
17118 case THUMB32_TYPE:
17119 if (!elf32_arm_output_stub_sym (osi, stub_name, addr | 1,
17120 stub_entry->stub_size))
17121 return FALSE;
17122 break;
17123 default:
17124 BFD_FAIL ();
17125 return 0;
17126 }
7413f23f 17127 }
da5938a2 17128
461a49ca
DJ		 17129 prev_type = DATA_TYPE;
17130 size = 0;
17131 for (i = 0; i < stub_entry->stub_template_size; i++)
17132 {
d3ce72d0 17133 switch (template_sequence[i].type)
461a49ca
DJ		 17134 {
17135 case ARM_TYPE:
17136 sym_type = ARM_MAP_ARM;
17137 break;
17138
17139 case THUMB16_TYPE:
48229727 17140 case THUMB32_TYPE:
461a49ca
DJ		 17141 sym_type = ARM_MAP_THUMB;
17142 break;
17143
17144 case DATA_TYPE:
17145 sym_type = ARM_MAP_DATA;
17146 break;
17147
17148 default:
17149 BFD_FAIL ();
4e31c731 17150 return FALSE;
461a49ca
DJ		 17151 }
17152
d3ce72d0 17153 if (template_sequence[i].type != prev_type)
461a49ca 17154 {
d3ce72d0 17155 prev_type = template_sequence[i].type;
461a49ca
DJ		 17156 if (!elf32_arm_output_map_sym (osi, sym_type, addr + size))
17157 return FALSE;
17158 }
17159
d3ce72d0 17160 switch (template_sequence[i].type)
461a49ca
DJ		 17161 {
17162 case ARM_TYPE:
48229727 17163 case THUMB32_TYPE:
461a49ca
DJ		 17164 size += 4;
17165 break;
17166
17167 case THUMB16_TYPE:
17168 size += 2;
17169 break;
17170
17171 case DATA_TYPE:
17172 size += 4;
17173 break;
17174
17175 default:
17176 BFD_FAIL ();
4e31c731 17177 return FALSE;
461a49ca
DJ		 17178 }
17179 }
17180
da5938a2
NC		 17181 return TRUE;
17182}
17183
33811162
DG		 17184/* Output mapping symbols for linker generated sections,
17185 and for those data-only sections that do not have a
17186 $d. */
4e617b1e
PB		 17187
17188static bfd_boolean
17189elf32_arm_output_arch_local_syms (bfd *output_bfd,
906e58ca 17190 struct bfd_link_info *info,
57402f1e 17191 void *flaginfo,
6e0b88f1
AM		 17192 int (*func) (void *, const char *,
17193 Elf_Internal_Sym *,
17194 asection *,
17195 struct elf_link_hash_entry *))
4e617b1e
PB		 17196{
17197 output_arch_syminfo osi;
17198 struct elf32_arm_link_hash_table *htab;
91a5743d
PB		 17199 bfd_vma offset;
17200 bfd_size_type size;
33811162 17201 bfd *input_bfd;
4e617b1e
PB		 17202
17203 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 17204 if (htab == NULL)
17205 return FALSE;
17206
906e58ca 17207 check_use_blx (htab);
91a5743d 17208
57402f1e 17209 osi.flaginfo = flaginfo;
4e617b1e
PB		 17210 osi.info = info;
17211 osi.func = func;
906e58ca 17212
33811162
DG		 17213 /* Add a $d mapping symbol to data-only sections that
17214 don't have any mapping symbol. This may result in (harmless) redundant
17215 mapping symbols. */
17216 for (input_bfd = info->input_bfds;
17217 input_bfd != NULL;
c72f2fb2 17218 input_bfd = input_bfd->link.next)
33811162
DG		 17219 {
17220 if ((input_bfd->flags & (BFD_LINKER_CREATED | HAS_SYMS)) == HAS_SYMS)
17221 for (osi.sec = input_bfd->sections;
17222 osi.sec != NULL;
17223 osi.sec = osi.sec->next)
17224 {
17225 if (osi.sec->output_section != NULL
f7dd8c79
DJ		 17226 && ((osi.sec->output_section->flags & (SEC_ALLOC | SEC_CODE))
17227 != 0)
33811162
DG		 17228 && (osi.sec->flags & (SEC_HAS_CONTENTS | SEC_LINKER_CREATED))
17229 == SEC_HAS_CONTENTS
17230 && get_arm_elf_section_data (osi.sec) != NULL
501abfe0 17231 && get_arm_elf_section_data (osi.sec)->mapcount == 0
7d500b83
CL		 17232 && osi.sec->size > 0
17233 && (osi.sec->flags & SEC_EXCLUDE) == 0)
33811162
DG		 17234 {
17235 osi.sec_shndx = _bfd_elf_section_from_bfd_section
17236 (output_bfd, osi.sec->output_section);
17237 if (osi.sec_shndx != (int)SHN_BAD)
17238 elf32_arm_output_map_sym (&osi, ARM_MAP_DATA, 0);
17239 }
17240 }
17241 }
17242
91a5743d
PB		 17243 /* ARM->Thumb glue. */
17244 if (htab->arm_glue_size > 0)
17245 {
3d4d4302
AM		 17246 osi.sec = bfd_get_linker_section (htab->bfd_of_glue_owner,
17247 ARM2THUMB_GLUE_SECTION_NAME);
91a5743d
PB		 17248
17249 osi.sec_shndx = _bfd_elf_section_from_bfd_section
17250 (output_bfd, osi.sec->output_section);
0e1862bb 17251 if (bfd_link_pic (info) || htab->root.is_relocatable_executable
91a5743d
PB		 17252 || htab->pic_veneer)
17253 size = ARM2THUMB_PIC_GLUE_SIZE;
17254 else if (htab->use_blx)
17255 size = ARM2THUMB_V5_STATIC_GLUE_SIZE;
17256 else
17257 size = ARM2THUMB_STATIC_GLUE_SIZE;
4e617b1e 17258
91a5743d
PB		 17259 for (offset = 0; offset < htab->arm_glue_size; offset += size)
17260 {
7413f23f
DJ		 17261 elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, offset);
17262 elf32_arm_output_map_sym (&osi, ARM_MAP_DATA, offset + size - 4);
91a5743d
PB		 17263 }
17264 }
17265
17266 /* Thumb->ARM glue. */
17267 if (htab->thumb_glue_size > 0)
17268 {
3d4d4302
AM		 17269 osi.sec = bfd_get_linker_section (htab->bfd_of_glue_owner,
17270 THUMB2ARM_GLUE_SECTION_NAME);
91a5743d
PB		 17271
17272 osi.sec_shndx = _bfd_elf_section_from_bfd_section
17273 (output_bfd, osi.sec->output_section);
17274 size = THUMB2ARM_GLUE_SIZE;
17275
17276 for (offset = 0; offset < htab->thumb_glue_size; offset += size)
17277 {
7413f23f
DJ		 17278 elf32_arm_output_map_sym (&osi, ARM_MAP_THUMB, offset);
17279 elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, offset + 4);
91a5743d
PB		 17280 }
17281 }
17282
845b51d6
PB		 17283 /* ARMv4 BX veneers. */
17284 if (htab->bx_glue_size > 0)
17285 {
3d4d4302
AM		 17286 osi.sec = bfd_get_linker_section (htab->bfd_of_glue_owner,
17287 ARM_BX_GLUE_SECTION_NAME);
845b51d6
PB		 17288
17289 osi.sec_shndx = _bfd_elf_section_from_bfd_section
17290 (output_bfd, osi.sec->output_section);
17291
7413f23f 17292 elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, 0);
845b51d6
PB		 17293 }
17294
8029a119
NC		 17295 /* Long calls stubs. */
17296 if (htab->stub_bfd && htab->stub_bfd->sections)
17297 {
da5938a2 17298 asection* stub_sec;
8029a119 17299
da5938a2
NC		 17300 for (stub_sec = htab->stub_bfd->sections;
17301 stub_sec != NULL;
8029a119
NC		 17302 stub_sec = stub_sec->next)
17303 {
17304 /* Ignore non-stub sections. */
17305 if (!strstr (stub_sec->name, STUB_SUFFIX))
17306 continue;
da5938a2 17307
8029a119 17308 osi.sec = stub_sec;
da5938a2 17309
8029a119
NC		 17310 osi.sec_shndx = _bfd_elf_section_from_bfd_section
17311 (output_bfd, osi.sec->output_section);
da5938a2 17312
8029a119
NC		 17313 bfd_hash_traverse (&htab->stub_hash_table, arm_map_one_stub, &osi);
17314 }
17315 }
da5938a2 17316
91a5743d 17317 /* Finally, output mapping symbols for the PLT. */
34e77a92 17318 if (htab->root.splt && htab->root.splt->size > 0)
4e617b1e 17319 {
34e77a92
RS		 17320 osi.sec = htab->root.splt;
17321 osi.sec_shndx = (_bfd_elf_section_from_bfd_section
17322 (output_bfd, osi.sec->output_section));
17323
17324 /* Output mapping symbols for the plt header. SymbianOS does not have a
17325 plt header. */
17326 if (htab->vxworks_p)
17327 {
17328 /* VxWorks shared libraries have no PLT header. */
0e1862bb 17329 if (!bfd_link_pic (info))
34e77a92
RS		 17330 {
17331 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, 0))
17332 return FALSE;
17333 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_DATA, 12))
17334 return FALSE;
17335 }
17336 }
b38cadfb
NC		 17337 else if (htab->nacl_p)
17338 {
17339 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, 0))
17340 return FALSE;
17341 }
eed94f8f
NC		 17342 else if (using_thumb_only (htab))
17343 {
17344 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_THUMB, 0))
17345 return FALSE;
17346 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_DATA, 12))
17347 return FALSE;
17348 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_THUMB, 16))
17349 return FALSE;
17350 }
34e77a92 17351 else if (!htab->symbian_p)
4e617b1e 17352 {
7413f23f 17353 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, 0))
4e617b1e 17354 return FALSE;
34e77a92
RS		 17355#ifndef FOUR_WORD_PLT
17356 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_DATA, 16))
4e617b1e 17357 return FALSE;
34e77a92 17358#endif
4e617b1e
PB		 17359 }
17360 }
99059e56
RM		 17361 if (htab->nacl_p && htab->root.iplt && htab->root.iplt->size > 0)
17362 {
17363 /* NaCl uses a special first entry in .iplt too. */
17364 osi.sec = htab->root.iplt;
17365 osi.sec_shndx = (_bfd_elf_section_from_bfd_section
17366 (output_bfd, osi.sec->output_section));
17367 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, 0))
17368 return FALSE;
17369 }
34e77a92
RS		 17370 if ((htab->root.splt && htab->root.splt->size > 0)
17371 || (htab->root.iplt && htab->root.iplt->size > 0))
4e617b1e 17372 {
34e77a92
RS		 17373 elf_link_hash_traverse (&htab->root, elf32_arm_output_plt_map, &osi);
17374 for (input_bfd = info->input_bfds;
17375 input_bfd != NULL;
c72f2fb2 17376 input_bfd = input_bfd->link.next)
34e77a92
RS		 17377 {
17378 struct arm_local_iplt_info **local_iplt;
17379 unsigned int i, num_syms;
4e617b1e 17380
34e77a92
RS		 17381 local_iplt = elf32_arm_local_iplt (input_bfd);
17382 if (local_iplt != NULL)
17383 {
17384 num_syms = elf_symtab_hdr (input_bfd).sh_info;
17385 for (i = 0; i < num_syms; i++)
17386 if (local_iplt[i] != NULL
17387 && !elf32_arm_output_plt_map_1 (&osi, TRUE,
17388 &local_iplt[i]->root,
17389 &local_iplt[i]->arm))
17390 return FALSE;
17391 }
17392 }
17393 }
0855e32b
NS		 17394 if (htab->dt_tlsdesc_plt != 0)
17395 {
17396 /* Mapping symbols for the lazy tls trampoline. */
17397 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, htab->dt_tlsdesc_plt))
17398 return FALSE;
b38cadfb 17399
0855e32b
NS		 17400 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_DATA,
17401 htab->dt_tlsdesc_plt + 24))
17402 return FALSE;
17403 }
17404 if (htab->tls_trampoline != 0)
17405 {
17406 /* Mapping symbols for the tls trampoline. */
17407 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, htab->tls_trampoline))
17408 return FALSE;
17409#ifdef FOUR_WORD_PLT
17410 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_DATA,
17411 htab->tls_trampoline + 12))
17412 return FALSE;
b38cadfb 17413#endif
0855e32b 17414 }
b38cadfb 17415
4e617b1e
PB		 17416 return TRUE;
17417}
17418
54ddd295
TP		 17419/* Filter normal symbols of CMSE entry functions of ABFD to include in
17420 the import library. All SYMCOUNT symbols of ABFD can be examined
17421 from their pointers in SYMS. Pointers of symbols to keep should be
17422 stored continuously at the beginning of that array.
17423
17424 Returns the number of symbols to keep. */
17425
17426static unsigned int
17427elf32_arm_filter_cmse_symbols (bfd *abfd ATTRIBUTE_UNUSED,
17428 struct bfd_link_info *info,
17429 asymbol **syms, long symcount)
17430{
17431 size_t maxnamelen;
17432 char *cmse_name;
17433 long src_count, dst_count = 0;
17434 struct elf32_arm_link_hash_table *htab;
17435
17436 htab = elf32_arm_hash_table (info);
17437 if (!htab->stub_bfd || !htab->stub_bfd->sections)
17438 symcount = 0;
17439
17440 maxnamelen = 128;
17441 cmse_name = (char *) bfd_malloc (maxnamelen);
17442 for (src_count = 0; src_count < symcount; src_count++)
17443 {
17444 struct elf32_arm_link_hash_entry *cmse_hash;
17445 asymbol *sym;
17446 flagword flags;
17447 char *name;
17448 size_t namelen;
17449
17450 sym = syms[src_count];
17451 flags = sym->flags;
17452 name = (char *) bfd_asymbol_name (sym);
17453
17454 if ((flags & BSF_FUNCTION) != BSF_FUNCTION)
17455 continue;
17456 if (!(flags & (BSF_GLOBAL | BSF_WEAK)))
17457 continue;
17458
17459 namelen = strlen (name) + sizeof (CMSE_PREFIX) + 1;
17460 if (namelen > maxnamelen)
17461 {
17462 cmse_name = (char *)
17463 bfd_realloc (cmse_name, namelen);
17464 maxnamelen = namelen;
17465 }
17466 snprintf (cmse_name, maxnamelen, "%s%s", CMSE_PREFIX, name);
17467 cmse_hash = (struct elf32_arm_link_hash_entry *)
17468 elf_link_hash_lookup (&(htab)->root, cmse_name, FALSE, FALSE, TRUE);
17469
17470 if (!cmse_hash
17471 || (cmse_hash->root.root.type != bfd_link_hash_defined
17472 && cmse_hash->root.root.type != bfd_link_hash_defweak)
17473 || cmse_hash->root.type != STT_FUNC)
17474 continue;
17475
17476 if (!ARM_GET_SYM_CMSE_SPCL (cmse_hash->root.target_internal))
17477 continue;
17478
17479 syms[dst_count++] = sym;
17480 }
17481 free (cmse_name);
17482
17483 syms[dst_count] = NULL;
17484
17485 return dst_count;
17486}
17487
17488/* Filter symbols of ABFD to include in the import library. All
17489 SYMCOUNT symbols of ABFD can be examined from their pointers in
17490 SYMS. Pointers of symbols to keep should be stored continuously at
17491 the beginning of that array.
17492
17493 Returns the number of symbols to keep. */
17494
17495static unsigned int
17496elf32_arm_filter_implib_symbols (bfd *abfd ATTRIBUTE_UNUSED,
17497 struct bfd_link_info *info,
17498 asymbol **syms, long symcount)
17499{
17500 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (info);
17501
17502 if (globals->cmse_implib)
17503 return elf32_arm_filter_cmse_symbols (abfd, info, syms, symcount);
17504 else
17505 return _bfd_elf_filter_global_symbols (abfd, info, syms, symcount);
17506}
17507
e489d0ae
PB		 17508/* Allocate target specific section data. */
17509
17510static bfd_boolean
17511elf32_arm_new_section_hook (bfd *abfd, asection *sec)
17512{
f592407e
AM		 17513 if (!sec->used_by_bfd)
17514 {
17515 _arm_elf_section_data *sdata;
17516 bfd_size_type amt = sizeof (*sdata);
e489d0ae 17517
21d799b5 17518 sdata = (_arm_elf_section_data *) bfd_zalloc (abfd, amt);
f592407e
AM		 17519 if (sdata == NULL)
17520 return FALSE;
17521 sec->used_by_bfd = sdata;
17522 }
e489d0ae
PB		 17523
17524 return _bfd_elf_new_section_hook (abfd, sec);
17525}
17526
17527
17528/* Used to order a list of mapping symbols by address. */
17529
17530static int
17531elf32_arm_compare_mapping (const void * a, const void * b)
17532{
7f6a71ff
JM		 17533 const elf32_arm_section_map *amap = (const elf32_arm_section_map *) a;
17534 const elf32_arm_section_map *bmap = (const elf32_arm_section_map *) b;
17535
17536 if (amap->vma > bmap->vma)
17537 return 1;
17538 else if (amap->vma < bmap->vma)
17539 return -1;
17540 else if (amap->type > bmap->type)
17541 /* Ensure results do not depend on the host qsort for objects with
17542 multiple mapping symbols at the same address by sorting on type
17543 after vma. */
17544 return 1;
17545 else if (amap->type < bmap->type)
17546 return -1;
17547 else
17548 return 0;
e489d0ae
PB		 17549}
17550
2468f9c9
PB		 17551/* Add OFFSET to lower 31 bits of ADDR, leaving other bits unmodified. */
17552
17553static unsigned long
17554offset_prel31 (unsigned long addr, bfd_vma offset)
17555{
17556 return (addr & ~0x7ffffffful) | ((addr + offset) & 0x7ffffffful);
17557}
17558
17559/* Copy an .ARM.exidx table entry, adding OFFSET to (applied) PREL31
17560 relocations. */
17561
17562static void
17563copy_exidx_entry (bfd *output_bfd, bfd_byte *to, bfd_byte *from, bfd_vma offset)
17564{
17565 unsigned long first_word = bfd_get_32 (output_bfd, from);
17566 unsigned long second_word = bfd_get_32 (output_bfd, from + 4);
b38cadfb 17567
2468f9c9
PB		 17568 /* High bit of first word is supposed to be zero. */
17569 if ((first_word & 0x80000000ul) == 0)
17570 first_word = offset_prel31 (first_word, offset);
b38cadfb 17571
2468f9c9
PB		 17572 /* If the high bit of the first word is clear, and the bit pattern is not 0x1
17573 (EXIDX_CANTUNWIND), this is an offset to an .ARM.extab entry. */
17574 if ((second_word != 0x1) && ((second_word & 0x80000000ul) == 0))
17575 second_word = offset_prel31 (second_word, offset);
b38cadfb 17576
2468f9c9
PB		 17577 bfd_put_32 (output_bfd, first_word, to);
17578 bfd_put_32 (output_bfd, second_word, to + 4);
17579}
e489d0ae 17580
48229727
JB		 17581/* Data for make_branch_to_a8_stub(). */
17582
b38cadfb
NC		 17583struct a8_branch_to_stub_data
17584{
48229727
JB		 17585 asection *writing_section;
17586 bfd_byte *contents;
17587};
17588
17589
17590/* Helper to insert branches to Cortex-A8 erratum stubs in the right
17591 places for a particular section. */
17592
17593static bfd_boolean
17594make_branch_to_a8_stub (struct bfd_hash_entry *gen_entry,
99059e56 17595 void *in_arg)
48229727
JB		 17596{
17597 struct elf32_arm_stub_hash_entry *stub_entry;
17598 struct a8_branch_to_stub_data *data;
17599 bfd_byte *contents;
17600 unsigned long branch_insn;
17601 bfd_vma veneered_insn_loc, veneer_entry_loc;
17602 bfd_signed_vma branch_offset;
17603 bfd *abfd;
8d9d9490 17604 unsigned int loc;
48229727
JB		 17605
17606 stub_entry = (struct elf32_arm_stub_hash_entry *) gen_entry;
17607 data = (struct a8_branch_to_stub_data *) in_arg;
17608
17609 if (stub_entry->target_section != data->writing_section
4563a860 17610 || stub_entry->stub_type < arm_stub_a8_veneer_lwm)
48229727
JB		 17611 return TRUE;
17612
17613 contents = data->contents;
17614
8d9d9490
TP		 17615 /* We use target_section as Cortex-A8 erratum workaround stubs are only
17616 generated when both source and target are in the same section. */
48229727
JB		 17617 veneered_insn_loc = stub_entry->target_section->output_section->vma
17618 + stub_entry->target_section->output_offset
8d9d9490 17619 + stub_entry->source_value;
48229727
JB		 17620
17621 veneer_entry_loc = stub_entry->stub_sec->output_section->vma
17622 + stub_entry->stub_sec->output_offset
17623 + stub_entry->stub_offset;
17624
17625 if (stub_entry->stub_type == arm_stub_a8_veneer_blx)
17626 veneered_insn_loc &= ~3u;
17627
17628 branch_offset = veneer_entry_loc - veneered_insn_loc - 4;
17629
17630 abfd = stub_entry->target_section->owner;
8d9d9490 17631 loc = stub_entry->source_value;
48229727
JB		 17632
17633 /* We attempt to avoid this condition by setting stubs_always_after_branch
17634 in elf32_arm_size_stubs if we've enabled the Cortex-A8 erratum workaround.
17635 This check is just to be on the safe side... */
17636 if ((veneered_insn_loc & ~0xfff) == (veneer_entry_loc & ~0xfff))
17637 {
4eca0228
AM		 17638 _bfd_error_handler (_("%B: error: Cortex-A8 erratum stub is "
17639 "allocated in unsafe location"), abfd);
48229727
JB		 17640 return FALSE;
17641 }
17642
17643 switch (stub_entry->stub_type)
17644 {
17645 case arm_stub_a8_veneer_b:
17646 case arm_stub_a8_veneer_b_cond:
17647 branch_insn = 0xf0009000;
17648 goto jump24;
17649
17650 case arm_stub_a8_veneer_blx:
17651 branch_insn = 0xf000e800;
17652 goto jump24;
17653
17654 case arm_stub_a8_veneer_bl:
17655 {
17656 unsigned int i1, j1, i2, j2, s;
17657
17658 branch_insn = 0xf000d000;
17659
17660 jump24:
17661 if (branch_offset < -16777216 || branch_offset > 16777214)
17662 {
17663 /* There's not much we can do apart from complain if this
17664 happens. */
4eca0228
AM		 17665 _bfd_error_handler (_("%B: error: Cortex-A8 erratum stub out "
17666 "of range (input file too large)"), abfd);
48229727
JB		 17667 return FALSE;
17668 }
17669
17670 /* i1 = not(j1 eor s), so:
17671 not i1 = j1 eor s
17672 j1 = (not i1) eor s. */
17673
17674 branch_insn |= (branch_offset >> 1) & 0x7ff;
17675 branch_insn |= ((branch_offset >> 12) & 0x3ff) << 16;
17676 i2 = (branch_offset >> 22) & 1;
17677 i1 = (branch_offset >> 23) & 1;
17678 s = (branch_offset >> 24) & 1;
17679 j1 = (!i1) ^ s;
17680 j2 = (!i2) ^ s;
17681 branch_insn |= j2 << 11;
17682 branch_insn |= j1 << 13;
17683 branch_insn |= s << 26;
17684 }
17685 break;
17686
17687 default:
17688 BFD_FAIL ();
17689 return FALSE;
17690 }
17691
8d9d9490
TP		 17692 bfd_put_16 (abfd, (branch_insn >> 16) & 0xffff, &contents[loc]);
17693 bfd_put_16 (abfd, branch_insn & 0xffff, &contents[loc + 2]);
48229727
JB		 17694
17695 return TRUE;
17696}
17697
a504d23a
LA		 17698/* Beginning of stm32l4xx work-around. */
17699
17700/* Functions encoding instructions necessary for the emission of the
17701 fix-stm32l4xx-629360.
17702 Encoding is extracted from the
17703 ARM (C) Architecture Reference Manual
17704 ARMv7-A and ARMv7-R edition
17705 ARM DDI 0406C.b (ID072512). */
17706
17707static inline bfd_vma
82188b29 17708create_instruction_branch_absolute (int branch_offset)
a504d23a
LA		 17709{
17710 /* A8.8.18 B (A8-334)
17711 B target_address (Encoding T4). */
17712 /* 1111 - 0Sii - iiii - iiii - 10J1 - Jiii - iiii - iiii. */
17713 /* jump offset is: S:I1:I2:imm10:imm11:0. */
17714 /* with : I1 = NOT (J1 EOR S) I2 = NOT (J2 EOR S). */
17715
a504d23a
LA		 17716 int s = ((branch_offset & 0x1000000) >> 24);
17717 int j1 = s ^ !((branch_offset & 0x800000) >> 23);
17718 int j2 = s ^ !((branch_offset & 0x400000) >> 22);
17719
17720 if (branch_offset < -(1 << 24) || branch_offset >= (1 << 24))
17721 BFD_ASSERT (0 && "Error: branch out of range. Cannot create branch.");
17722
17723 bfd_vma patched_inst = 0xf0009000
17724 | s << 26 /* S. */
17725 | (((unsigned long) (branch_offset) >> 12) & 0x3ff) << 16 /* imm10. */
17726 | j1 << 13 /* J1. */
17727 | j2 << 11 /* J2. */
17728 | (((unsigned long) (branch_offset) >> 1) & 0x7ff); /* imm11. */
17729
17730 return patched_inst;
17731}
17732
17733static inline bfd_vma
17734create_instruction_ldmia (int base_reg, int wback, int reg_mask)
17735{
17736 /* A8.8.57 LDM/LDMIA/LDMFD (A8-396)
17737 LDMIA Rn!, {Ra, Rb, Rc, ...} (Encoding T2). */
17738 bfd_vma patched_inst = 0xe8900000
17739 | (/*W=*/wback << 21)
17740 | (base_reg << 16)
17741 | (reg_mask & 0x0000ffff);
17742
17743 return patched_inst;
17744}
17745
17746static inline bfd_vma
17747create_instruction_ldmdb (int base_reg, int wback, int reg_mask)
17748{
17749 /* A8.8.60 LDMDB/LDMEA (A8-402)
17750 LDMDB Rn!, {Ra, Rb, Rc, ...} (Encoding T1). */
17751 bfd_vma patched_inst = 0xe9100000
17752 | (/*W=*/wback << 21)
17753 | (base_reg << 16)
17754 | (reg_mask & 0x0000ffff);
17755
17756 return patched_inst;
17757}
17758
17759static inline bfd_vma
17760create_instruction_mov (int target_reg, int source_reg)
17761{
17762 /* A8.8.103 MOV (register) (A8-486)
17763 MOV Rd, Rm (Encoding T1). */
17764 bfd_vma patched_inst = 0x4600
17765 | (target_reg & 0x7)
17766 | ((target_reg & 0x8) >> 3) << 7
17767 | (source_reg << 3);
17768
17769 return patched_inst;
17770}
17771
17772static inline bfd_vma
17773create_instruction_sub (int target_reg, int source_reg, int value)
17774{
17775 /* A8.8.221 SUB (immediate) (A8-708)
17776 SUB Rd, Rn, #value (Encoding T3). */
17777 bfd_vma patched_inst = 0xf1a00000
17778 | (target_reg << 8)
17779 | (source_reg << 16)
17780 | (/*S=*/0 << 20)
17781 | ((value & 0x800) >> 11) << 26
17782 | ((value & 0x700) >> 8) << 12
17783 | (value & 0x0ff);
17784
17785 return patched_inst;
17786}
17787
17788static inline bfd_vma
9239bbd3 17789create_instruction_vldmia (int base_reg, int is_dp, int wback, int num_words,
a504d23a
LA		 17790 int first_reg)
17791{
17792 /* A8.8.332 VLDM (A8-922)
9239bbd3
CM		 17793 VLMD{MODE} Rn{!}, {list} (Encoding T1 or T2). */
17794 bfd_vma patched_inst = (is_dp ? 0xec900b00 : 0xec900a00)
a504d23a
LA		 17795 | (/*W=*/wback << 21)
17796 | (base_reg << 16)
9239bbd3
CM		 17797 | (num_words & 0x000000ff)
17798 | (((unsigned)first_reg >> 1) & 0x0000000f) << 12
a504d23a
LA		 17799 | (first_reg & 0x00000001) << 22;
17800
17801 return patched_inst;
17802}
17803
17804static inline bfd_vma
9239bbd3
CM		 17805create_instruction_vldmdb (int base_reg, int is_dp, int num_words,
17806 int first_reg)
a504d23a
LA		 17807{
17808 /* A8.8.332 VLDM (A8-922)
9239bbd3
CM		 17809 VLMD{MODE} Rn!, {} (Encoding T1 or T2). */
17810 bfd_vma patched_inst = (is_dp ? 0xed300b00 : 0xed300a00)
a504d23a 17811 | (base_reg << 16)
9239bbd3
CM		 17812 | (num_words & 0x000000ff)
17813 | (((unsigned)first_reg >>1 ) & 0x0000000f) << 12
a504d23a
LA		 17814 | (first_reg & 0x00000001) << 22;
17815
17816 return patched_inst;
17817}
17818
17819static inline bfd_vma
17820create_instruction_udf_w (int value)
17821{
17822 /* A8.8.247 UDF (A8-758)
17823 Undefined (Encoding T2). */
17824 bfd_vma patched_inst = 0xf7f0a000
17825 | (value & 0x00000fff)
17826 | (value & 0x000f0000) << 16;
17827
17828 return patched_inst;
17829}
17830
17831static inline bfd_vma
17832create_instruction_udf (int value)
17833{
17834 /* A8.8.247 UDF (A8-758)
17835 Undefined (Encoding T1). */
17836 bfd_vma patched_inst = 0xde00
17837 | (value & 0xff);
17838
17839 return patched_inst;
17840}
17841
17842/* Functions writing an instruction in memory, returning the next
17843 memory position to write to. */
17844
17845static inline bfd_byte *
17846push_thumb2_insn32 (struct elf32_arm_link_hash_table * htab,
17847 bfd * output_bfd, bfd_byte *pt, insn32 insn)
17848{
17849 put_thumb2_insn (htab, output_bfd, insn, pt);
17850 return pt + 4;
17851}
17852
17853static inline bfd_byte *
17854push_thumb2_insn16 (struct elf32_arm_link_hash_table * htab,
17855 bfd * output_bfd, bfd_byte *pt, insn32 insn)
17856{
17857 put_thumb_insn (htab, output_bfd, insn, pt);
17858 return pt + 2;
17859}
17860
17861/* Function filling up a region in memory with T1 and T2 UDFs taking
17862 care of alignment. */
17863
17864static bfd_byte *
17865stm32l4xx_fill_stub_udf (struct elf32_arm_link_hash_table * htab,
17866 bfd * output_bfd,
17867 const bfd_byte * const base_stub_contents,
17868 bfd_byte * const from_stub_contents,
17869 const bfd_byte * const end_stub_contents)
17870{
17871 bfd_byte *current_stub_contents = from_stub_contents;
17872
17873 /* Fill the remaining of the stub with deterministic contents : UDF
17874 instructions.
17875 Check if realignment is needed on modulo 4 frontier using T1, to
17876 further use T2. */
17877 if ((current_stub_contents < end_stub_contents)
17878 && !((current_stub_contents - base_stub_contents) % 2)
17879 && ((current_stub_contents - base_stub_contents) % 4))
17880 current_stub_contents =
17881 push_thumb2_insn16 (htab, output_bfd, current_stub_contents,
17882 create_instruction_udf (0));
17883
17884 for (; current_stub_contents < end_stub_contents;)
17885 current_stub_contents =
17886 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
17887 create_instruction_udf_w (0));
17888
17889 return current_stub_contents;
17890}
17891
17892/* Functions writing the stream of instructions equivalent to the
17893 derived sequence for ldmia, ldmdb, vldm respectively. */
17894
17895static void
17896stm32l4xx_create_replacing_stub_ldmia (struct elf32_arm_link_hash_table * htab,
17897 bfd * output_bfd,
17898 const insn32 initial_insn,
17899 const bfd_byte *const initial_insn_addr,
17900 bfd_byte *const base_stub_contents)
17901{
17902 int wback = (initial_insn & 0x00200000) >> 21;
17903 int ri, rn = (initial_insn & 0x000F0000) >> 16;
17904 int insn_all_registers = initial_insn & 0x0000ffff;
17905 int insn_low_registers, insn_high_registers;
17906 int usable_register_mask;
b25e998d 17907 int nb_registers = elf32_arm_popcount (insn_all_registers);
a504d23a
LA		 17908 int restore_pc = (insn_all_registers & (1 << 15)) ? 1 : 0;
17909 int restore_rn = (insn_all_registers & (1 << rn)) ? 1 : 0;
17910 bfd_byte *current_stub_contents = base_stub_contents;
17911
17912 BFD_ASSERT (is_thumb2_ldmia (initial_insn));
17913
17914 /* In BFD_ARM_STM32L4XX_FIX_ALL mode we may have to deal with
17915 smaller than 8 registers load sequences that do not cause the
17916 hardware issue. */
17917 if (nb_registers <= 8)
17918 {
17919 /* UNTOUCHED : LDMIA Rn{!}, {R-all-register-list}. */
17920 current_stub_contents =
17921 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
17922 initial_insn);
17923
17924 /* B initial_insn_addr+4. */
17925 if (!restore_pc)
17926 current_stub_contents =
17927 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
17928 create_instruction_branch_absolute
82188b29 17929 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 17930
17931 /* Fill the remaining of the stub with deterministic contents. */
17932 current_stub_contents =
17933 stm32l4xx_fill_stub_udf (htab, output_bfd,
17934 base_stub_contents, current_stub_contents,
17935 base_stub_contents +
17936 STM32L4XX_ERRATUM_LDM_VENEER_SIZE);
17937
17938 return;
17939 }
17940
17941 /* - reg_list[13] == 0. */
17942 BFD_ASSERT ((insn_all_registers & (1 << 13))==0);
17943
17944 /* - reg_list[14] & reg_list[15] != 1. */
17945 BFD_ASSERT ((insn_all_registers & 0xC000) != 0xC000);
17946
17947 /* - if (wback==1) reg_list[rn] == 0. */
17948 BFD_ASSERT (!wback || !restore_rn);
17949
17950 /* - nb_registers > 8. */
b25e998d 17951 BFD_ASSERT (elf32_arm_popcount (insn_all_registers) > 8);
a504d23a
LA		 17952
17953 /* At this point, LDMxx initial insn loads between 9 and 14 registers. */
17954
17955 /* In the following algorithm, we split this wide LDM using 2 LDM insns:
17956 - One with the 7 lowest registers (register mask 0x007F)
17957 This LDM will finally contain between 2 and 7 registers
17958 - One with the 7 highest registers (register mask 0xDF80)
17959 This ldm will finally contain between 2 and 7 registers. */
17960 insn_low_registers = insn_all_registers & 0x007F;
17961 insn_high_registers = insn_all_registers & 0xDF80;
17962
17963 /* A spare register may be needed during this veneer to temporarily
17964 handle the base register. This register will be restored with the
17965 last LDM operation.
17966 The usable register may be any general purpose register (that
17967 excludes PC, SP, LR : register mask is 0x1FFF). */
17968 usable_register_mask = 0x1FFF;
17969
17970 /* Generate the stub function. */
17971 if (wback)
17972 {
17973 /* LDMIA Rn!, {R-low-register-list} : (Encoding T2). */
17974 current_stub_contents =
17975 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
17976 create_instruction_ldmia
17977 (rn, /*wback=*/1, insn_low_registers));
17978
17979 /* LDMIA Rn!, {R-high-register-list} : (Encoding T2). */
17980 current_stub_contents =
17981 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
17982 create_instruction_ldmia
17983 (rn, /*wback=*/1, insn_high_registers));
17984 if (!restore_pc)
17985 {
17986 /* B initial_insn_addr+4. */
17987 current_stub_contents =
17988 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
17989 create_instruction_branch_absolute
82188b29 17990 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 17991 }
17992 }
17993 else /* if (!wback). */
17994 {
17995 ri = rn;
17996
17997 /* If Rn is not part of the high-register-list, move it there. */
17998 if (!(insn_high_registers & (1 << rn)))
17999 {
18000 /* Choose a Ri in the high-register-list that will be restored. */
18001 ri = ctz (insn_high_registers & usable_register_mask & ~(1 << rn));
18002
18003 /* MOV Ri, Rn. */
18004 current_stub_contents =
18005 push_thumb2_insn16 (htab, output_bfd, current_stub_contents,
18006 create_instruction_mov (ri, rn));
18007 }
18008
18009 /* LDMIA Ri!, {R-low-register-list} : (Encoding T2). */
18010 current_stub_contents =
18011 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18012 create_instruction_ldmia
18013 (ri, /*wback=*/1, insn_low_registers));
18014
18015 /* LDMIA Ri, {R-high-register-list} : (Encoding T2). */
18016 current_stub_contents =
18017 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18018 create_instruction_ldmia
18019 (ri, /*wback=*/0, insn_high_registers));
18020
18021 if (!restore_pc)
18022 {
18023 /* B initial_insn_addr+4. */
18024 current_stub_contents =
18025 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18026 create_instruction_branch_absolute
82188b29 18027 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 18028 }
18029 }
18030
18031 /* Fill the remaining of the stub with deterministic contents. */
18032 current_stub_contents =
18033 stm32l4xx_fill_stub_udf (htab, output_bfd,
18034 base_stub_contents, current_stub_contents,
18035 base_stub_contents +
18036 STM32L4XX_ERRATUM_LDM_VENEER_SIZE);
18037}
18038
18039static void
18040stm32l4xx_create_replacing_stub_ldmdb (struct elf32_arm_link_hash_table * htab,
18041 bfd * output_bfd,
18042 const insn32 initial_insn,
18043 const bfd_byte *const initial_insn_addr,
18044 bfd_byte *const base_stub_contents)
18045{
18046 int wback = (initial_insn & 0x00200000) >> 21;
18047 int ri, rn = (initial_insn & 0x000f0000) >> 16;
18048 int insn_all_registers = initial_insn & 0x0000ffff;
18049 int insn_low_registers, insn_high_registers;
18050 int usable_register_mask;
18051 int restore_pc = (insn_all_registers & (1 << 15)) ? 1 : 0;
18052 int restore_rn = (insn_all_registers & (1 << rn)) ? 1 : 0;
b25e998d 18053 int nb_registers = elf32_arm_popcount (insn_all_registers);
a504d23a
LA		 18054 bfd_byte *current_stub_contents = base_stub_contents;
18055
18056 BFD_ASSERT (is_thumb2_ldmdb (initial_insn));
18057
18058 /* In BFD_ARM_STM32L4XX_FIX_ALL mode we may have to deal with
18059 smaller than 8 registers load sequences that do not cause the
18060 hardware issue. */
18061 if (nb_registers <= 8)
18062 {
18063 /* UNTOUCHED : LDMIA Rn{!}, {R-all-register-list}. */
18064 current_stub_contents =
18065 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18066 initial_insn);
18067
18068 /* B initial_insn_addr+4. */
18069 current_stub_contents =
18070 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18071 create_instruction_branch_absolute
82188b29 18072 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 18073
18074 /* Fill the remaining of the stub with deterministic contents. */
18075 current_stub_contents =
18076 stm32l4xx_fill_stub_udf (htab, output_bfd,
18077 base_stub_contents, current_stub_contents,
18078 base_stub_contents +
18079 STM32L4XX_ERRATUM_LDM_VENEER_SIZE);
18080
18081 return;
18082 }
18083
18084 /* - reg_list[13] == 0. */
18085 BFD_ASSERT ((insn_all_registers & (1 << 13)) == 0);
18086
18087 /* - reg_list[14] & reg_list[15] != 1. */
18088 BFD_ASSERT ((insn_all_registers & 0xC000) != 0xC000);
18089
18090 /* - if (wback==1) reg_list[rn] == 0. */
18091 BFD_ASSERT (!wback || !restore_rn);
18092
18093 /* - nb_registers > 8. */
b25e998d 18094 BFD_ASSERT (elf32_arm_popcount (insn_all_registers) > 8);
a504d23a
LA		 18095
18096 /* At this point, LDMxx initial insn loads between 9 and 14 registers. */
18097
18098 /* In the following algorithm, we split this wide LDM using 2 LDM insn:
18099 - One with the 7 lowest registers (register mask 0x007F)
18100 This LDM will finally contain between 2 and 7 registers
18101 - One with the 7 highest registers (register mask 0xDF80)
18102 This ldm will finally contain between 2 and 7 registers. */
18103 insn_low_registers = insn_all_registers & 0x007F;
18104 insn_high_registers = insn_all_registers & 0xDF80;
18105
18106 /* A spare register may be needed during this veneer to temporarily
18107 handle the base register. This register will be restored with
18108 the last LDM operation.
18109 The usable register may be any general purpose register (that excludes
18110 PC, SP, LR : register mask is 0x1FFF). */
18111 usable_register_mask = 0x1FFF;
18112
18113 /* Generate the stub function. */
18114 if (!wback && !restore_pc && !restore_rn)
18115 {
18116 /* Choose a Ri in the low-register-list that will be restored. */
18117 ri = ctz (insn_low_registers & usable_register_mask & ~(1 << rn));
18118
18119 /* MOV Ri, Rn. */
18120 current_stub_contents =
18121 push_thumb2_insn16 (htab, output_bfd, current_stub_contents,
18122 create_instruction_mov (ri, rn));
18123
18124 /* LDMDB Ri!, {R-high-register-list}. */
18125 current_stub_contents =
18126 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18127 create_instruction_ldmdb
18128 (ri, /*wback=*/1, insn_high_registers));
18129
18130 /* LDMDB Ri, {R-low-register-list}. */
18131 current_stub_contents =
18132 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18133 create_instruction_ldmdb
18134 (ri, /*wback=*/0, insn_low_registers));
18135
18136 /* B initial_insn_addr+4. */
18137 current_stub_contents =
18138 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18139 create_instruction_branch_absolute
82188b29 18140 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 18141 }
18142 else if (wback && !restore_pc && !restore_rn)
18143 {
18144 /* LDMDB Rn!, {R-high-register-list}. */
18145 current_stub_contents =
18146 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18147 create_instruction_ldmdb
18148 (rn, /*wback=*/1, insn_high_registers));
18149
18150 /* LDMDB Rn!, {R-low-register-list}. */
18151 current_stub_contents =
18152 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18153 create_instruction_ldmdb
18154 (rn, /*wback=*/1, insn_low_registers));
18155
18156 /* B initial_insn_addr+4. */
18157 current_stub_contents =
18158 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18159 create_instruction_branch_absolute
82188b29 18160 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 18161 }
18162 else if (!wback && restore_pc && !restore_rn)
18163 {
18164 /* Choose a Ri in the high-register-list that will be restored. */
18165 ri = ctz (insn_high_registers & usable_register_mask & ~(1 << rn));
18166
18167 /* SUB Ri, Rn, #(4*nb_registers). */
18168 current_stub_contents =
18169 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18170 create_instruction_sub (ri, rn, (4 * nb_registers)));
18171
18172 /* LDMIA Ri!, {R-low-register-list}. */
18173 current_stub_contents =
18174 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18175 create_instruction_ldmia
18176 (ri, /*wback=*/1, insn_low_registers));
18177
18178 /* LDMIA Ri, {R-high-register-list}. */
18179 current_stub_contents =
18180 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18181 create_instruction_ldmia
18182 (ri, /*wback=*/0, insn_high_registers));
18183 }
18184 else if (wback && restore_pc && !restore_rn)
18185 {
18186 /* Choose a Ri in the high-register-list that will be restored. */
18187 ri = ctz (insn_high_registers & usable_register_mask & ~(1 << rn));
18188
18189 /* SUB Rn, Rn, #(4*nb_registers) */
18190 current_stub_contents =
18191 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18192 create_instruction_sub (rn, rn, (4 * nb_registers)));
18193
18194 /* MOV Ri, Rn. */
18195 current_stub_contents =
18196 push_thumb2_insn16 (htab, output_bfd, current_stub_contents,
18197 create_instruction_mov (ri, rn));
18198
18199 /* LDMIA Ri!, {R-low-register-list}. */
18200 current_stub_contents =
18201 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18202 create_instruction_ldmia
18203 (ri, /*wback=*/1, insn_low_registers));
18204
18205 /* LDMIA Ri, {R-high-register-list}. */
18206 current_stub_contents =
18207 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18208 create_instruction_ldmia
18209 (ri, /*wback=*/0, insn_high_registers));
18210 }
18211 else if (!wback && !restore_pc && restore_rn)
18212 {
18213 ri = rn;
18214 if (!(insn_low_registers & (1 << rn)))
18215 {
18216 /* Choose a Ri in the low-register-list that will be restored. */
18217 ri = ctz (insn_low_registers & usable_register_mask & ~(1 << rn));
18218
18219 /* MOV Ri, Rn. */
18220 current_stub_contents =
18221 push_thumb2_insn16 (htab, output_bfd, current_stub_contents,
18222 create_instruction_mov (ri, rn));
18223 }
18224
18225 /* LDMDB Ri!, {R-high-register-list}. */
18226 current_stub_contents =
18227 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18228 create_instruction_ldmdb
18229 (ri, /*wback=*/1, insn_high_registers));
18230
18231 /* LDMDB Ri, {R-low-register-list}. */
18232 current_stub_contents =
18233 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18234 create_instruction_ldmdb
18235 (ri, /*wback=*/0, insn_low_registers));
18236
18237 /* B initial_insn_addr+4. */
18238 current_stub_contents =
18239 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18240 create_instruction_branch_absolute
82188b29 18241 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 18242 }
18243 else if (!wback && restore_pc && restore_rn)
18244 {
18245 ri = rn;
18246 if (!(insn_high_registers & (1 << rn)))
18247 {
18248 /* Choose a Ri in the high-register-list that will be restored. */
18249 ri = ctz (insn_high_registers & usable_register_mask & ~(1 << rn));
18250 }
18251
18252 /* SUB Ri, Rn, #(4*nb_registers). */
18253 current_stub_contents =
18254 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18255 create_instruction_sub (ri, rn, (4 * nb_registers)));
18256
18257 /* LDMIA Ri!, {R-low-register-list}. */
18258 current_stub_contents =
18259 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18260 create_instruction_ldmia
18261 (ri, /*wback=*/1, insn_low_registers));
18262
18263 /* LDMIA Ri, {R-high-register-list}. */
18264 current_stub_contents =
18265 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18266 create_instruction_ldmia
18267 (ri, /*wback=*/0, insn_high_registers));
18268 }
18269 else if (wback && restore_rn)
18270 {
18271 /* The assembler should not have accepted to encode this. */
18272 BFD_ASSERT (0 && "Cannot patch an instruction that has an "
18273 "undefined behavior.\n");
18274 }
18275
18276 /* Fill the remaining of the stub with deterministic contents. */
18277 current_stub_contents =
18278 stm32l4xx_fill_stub_udf (htab, output_bfd,
18279 base_stub_contents, current_stub_contents,
18280 base_stub_contents +
18281 STM32L4XX_ERRATUM_LDM_VENEER_SIZE);
18282
18283}
18284
18285static void
18286stm32l4xx_create_replacing_stub_vldm (struct elf32_arm_link_hash_table * htab,
18287 bfd * output_bfd,
18288 const insn32 initial_insn,
18289 const bfd_byte *const initial_insn_addr,
18290 bfd_byte *const base_stub_contents)
18291{
9239bbd3 18292 int num_words = ((unsigned int) initial_insn << 24) >> 24;
a504d23a
LA		 18293 bfd_byte *current_stub_contents = base_stub_contents;
18294
18295 BFD_ASSERT (is_thumb2_vldm (initial_insn));
18296
18297 /* In BFD_ARM_STM32L4XX_FIX_ALL mode we may have to deal with
9239bbd3 18298 smaller than 8 words load sequences that do not cause the
a504d23a 18299 hardware issue. */
9239bbd3 18300 if (num_words <= 8)
a504d23a
LA		 18301 {
18302 /* Untouched instruction. */
18303 current_stub_contents =
18304 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18305 initial_insn);
18306
18307 /* B initial_insn_addr+4. */
18308 current_stub_contents =
18309 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18310 create_instruction_branch_absolute
82188b29 18311 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 18312 }
18313 else
18314 {
9eaff861 18315 bfd_boolean is_dp = /* DP encoding. */
9239bbd3 18316 (initial_insn & 0xfe100f00) == 0xec100b00;
a504d23a
LA		 18317 bfd_boolean is_ia_nobang = /* (IA without !). */
18318 (((initial_insn << 7) >> 28) & 0xd) == 0x4;
18319 bfd_boolean is_ia_bang = /* (IA with !) - includes VPOP. */
18320 (((initial_insn << 7) >> 28) & 0xd) == 0x5;
18321 bfd_boolean is_db_bang = /* (DB with !). */
18322 (((initial_insn << 7) >> 28) & 0xd) == 0x9;
9239bbd3 18323 int base_reg = ((unsigned int) initial_insn << 12) >> 28;
a504d23a 18324 /* d = UInt (Vd:D);. */
9239bbd3 18325 int first_reg = ((((unsigned int) initial_insn << 16) >> 28) << 1)
a504d23a
LA		 18326 | (((unsigned int)initial_insn << 9) >> 31);
18327
9239bbd3
CM		 18328 /* Compute the number of 8-words chunks needed to split. */
18329 int chunks = (num_words % 8) ? (num_words / 8 + 1) : (num_words / 8);
a504d23a
LA		 18330 int chunk;
18331
18332 /* The test coverage has been done assuming the following
18333 hypothesis that exactly one of the previous is_ predicates is
18334 true. */
9239bbd3
CM		 18335 BFD_ASSERT ( (is_ia_nobang ^ is_ia_bang ^ is_db_bang)
18336 && !(is_ia_nobang & is_ia_bang & is_db_bang));
a504d23a 18337
9239bbd3 18338 /* We treat the cutting of the words in one pass for all
a504d23a
LA		 18339 cases, then we emit the adjustments:
18340
18341 vldm rx, {...}
18342 -> vldm rx!, {8_words_or_less} for each needed 8_word
18343 -> sub rx, rx, #size (list)
18344
18345 vldm rx!, {...}
18346 -> vldm rx!, {8_words_or_less} for each needed 8_word
18347 This also handles vpop instruction (when rx is sp)
18348
18349 vldmd rx!, {...}
18350 -> vldmb rx!, {8_words_or_less} for each needed 8_word. */
9239bbd3 18351 for (chunk = 0; chunk < chunks; ++chunk)
a504d23a 18352 {
9239bbd3
CM		 18353 bfd_vma new_insn = 0;
18354
a504d23a
LA		 18355 if (is_ia_nobang || is_ia_bang)
18356 {
9239bbd3
CM		 18357 new_insn = create_instruction_vldmia
18358 (base_reg,
18359 is_dp,
18360 /*wback= . */1,
18361 chunks - (chunk + 1) ?
18362 8 : num_words - chunk * 8,
18363 first_reg + chunk * 8);
a504d23a
LA		 18364 }
18365 else if (is_db_bang)
18366 {
9239bbd3
CM		 18367 new_insn = create_instruction_vldmdb
18368 (base_reg,
18369 is_dp,
18370 chunks - (chunk + 1) ?
18371 8 : num_words - chunk * 8,
18372 first_reg + chunk * 8);
a504d23a 18373 }
9239bbd3
CM		 18374
18375 if (new_insn)
18376 current_stub_contents =
18377 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18378 new_insn);
a504d23a
LA		 18379 }
18380
18381 /* Only this case requires the base register compensation
18382 subtract. */
18383 if (is_ia_nobang)
18384 {
18385 current_stub_contents =
18386 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18387 create_instruction_sub
9239bbd3 18388 (base_reg, base_reg, 4*num_words));
a504d23a
LA		 18389 }
18390
18391 /* B initial_insn_addr+4. */
18392 current_stub_contents =
18393 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18394 create_instruction_branch_absolute
82188b29 18395 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 18396 }
18397
18398 /* Fill the remaining of the stub with deterministic contents. */
18399 current_stub_contents =
18400 stm32l4xx_fill_stub_udf (htab, output_bfd,
18401 base_stub_contents, current_stub_contents,
18402 base_stub_contents +
18403 STM32L4XX_ERRATUM_VLDM_VENEER_SIZE);
18404}
18405
18406static void
18407stm32l4xx_create_replacing_stub (struct elf32_arm_link_hash_table * htab,
18408 bfd * output_bfd,
18409 const insn32 wrong_insn,
18410 const bfd_byte *const wrong_insn_addr,
18411 bfd_byte *const stub_contents)
18412{
18413 if (is_thumb2_ldmia (wrong_insn))
18414 stm32l4xx_create_replacing_stub_ldmia (htab, output_bfd,
18415 wrong_insn, wrong_insn_addr,
18416 stub_contents);
18417 else if (is_thumb2_ldmdb (wrong_insn))
18418 stm32l4xx_create_replacing_stub_ldmdb (htab, output_bfd,
18419 wrong_insn, wrong_insn_addr,
18420 stub_contents);
18421 else if (is_thumb2_vldm (wrong_insn))
18422 stm32l4xx_create_replacing_stub_vldm (htab, output_bfd,
18423 wrong_insn, wrong_insn_addr,
18424 stub_contents);
18425}
18426
18427/* End of stm32l4xx work-around. */
18428
18429
e489d0ae
PB		 18430/* Do code byteswapping. Return FALSE afterwards so that the section is
18431 written out as normal. */
18432
18433static bfd_boolean
c7b8f16e 18434elf32_arm_write_section (bfd *output_bfd,
8029a119
NC		 18435 struct bfd_link_info *link_info,
18436 asection *sec,
e489d0ae
PB		 18437 bfd_byte *contents)
18438{
48229727 18439 unsigned int mapcount, errcount;
8e3de13a 18440 _arm_elf_section_data *arm_data;
c7b8f16e 18441 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (link_info);
e489d0ae 18442 elf32_arm_section_map *map;
c7b8f16e 18443 elf32_vfp11_erratum_list *errnode;
a504d23a 18444 elf32_stm32l4xx_erratum_list *stm32l4xx_errnode;
e489d0ae
PB		 18445 bfd_vma ptr;
18446 bfd_vma end;
c7b8f16e 18447 bfd_vma offset = sec->output_section->vma + sec->output_offset;
e489d0ae 18448 bfd_byte tmp;
48229727 18449 unsigned int i;
57e8b36a 18450
4dfe6ac6
NC		 18451 if (globals == NULL)
18452 return FALSE;
18453
8e3de13a
NC		 18454 /* If this section has not been allocated an _arm_elf_section_data
18455 structure then we cannot record anything. */
18456 arm_data = get_arm_elf_section_data (sec);
18457 if (arm_data == NULL)
18458 return FALSE;
18459
18460 mapcount = arm_data->mapcount;
18461 map = arm_data->map;
c7b8f16e
JB		 18462 errcount = arm_data->erratumcount;
18463
18464 if (errcount != 0)
18465 {
18466 unsigned int endianflip = bfd_big_endian (output_bfd) ? 3 : 0;
18467
18468 for (errnode = arm_data->erratumlist; errnode != 0;
99059e56
RM		 18469 errnode = errnode->next)
18470 {
18471 bfd_vma target = errnode->vma - offset;
18472
18473 switch (errnode->type)
18474 {
18475 case VFP11_ERRATUM_BRANCH_TO_ARM_VENEER:
18476 {
18477 bfd_vma branch_to_veneer;
18478 /* Original condition code of instruction, plus bit mask for
18479 ARM B instruction. */
18480 unsigned int insn = (errnode->u.b.vfp_insn & 0xf0000000)
18481 | 0x0a000000;
c7b8f16e
JB		 18482
18483 /* The instruction is before the label. */
91d6fa6a 18484 target -= 4;
c7b8f16e
JB		 18485
18486 /* Above offset included in -4 below. */
18487 branch_to_veneer = errnode->u.b.veneer->vma
99059e56 18488 - errnode->vma - 4;
c7b8f16e
JB		 18489
18490 if ((signed) branch_to_veneer < -(1 << 25)
18491 || (signed) branch_to_veneer >= (1 << 25))
4eca0228
AM		 18492 _bfd_error_handler (_("%B: error: VFP11 veneer out of "
18493 "range"), output_bfd);
c7b8f16e 18494
99059e56
RM		 18495 insn |= (branch_to_veneer >> 2) & 0xffffff;
18496 contents[endianflip ^ target] = insn & 0xff;
18497 contents[endianflip ^ (target + 1)] = (insn >> 8) & 0xff;
18498 contents[endianflip ^ (target + 2)] = (insn >> 16) & 0xff;
18499 contents[endianflip ^ (target + 3)] = (insn >> 24) & 0xff;
18500 }
18501 break;
c7b8f16e
JB		 18502
18503 case VFP11_ERRATUM_ARM_VENEER:
99059e56
RM		 18504 {
18505 bfd_vma branch_from_veneer;
18506 unsigned int insn;
c7b8f16e 18507
99059e56
RM		 18508 /* Take size of veneer into account. */
18509 branch_from_veneer = errnode->u.v.branch->vma
18510 - errnode->vma - 12;
c7b8f16e
JB		 18511
18512 if ((signed) branch_from_veneer < -(1 << 25)
18513 || (signed) branch_from_veneer >= (1 << 25))
4eca0228
AM		 18514 _bfd_error_handler (_("%B: error: VFP11 veneer out of "
18515 "range"), output_bfd);
c7b8f16e 18516
99059e56
RM		 18517 /* Original instruction. */
18518 insn = errnode->u.v.branch->u.b.vfp_insn;
18519 contents[endianflip ^ target] = insn & 0xff;
18520 contents[endianflip ^ (target + 1)] = (insn >> 8) & 0xff;
18521 contents[endianflip ^ (target + 2)] = (insn >> 16) & 0xff;
18522 contents[endianflip ^ (target + 3)] = (insn >> 24) & 0xff;
18523
18524 /* Branch back to insn after original insn. */
18525 insn = 0xea000000 | ((branch_from_veneer >> 2) & 0xffffff);
18526 contents[endianflip ^ (target + 4)] = insn & 0xff;
18527 contents[endianflip ^ (target + 5)] = (insn >> 8) & 0xff;
18528 contents[endianflip ^ (target + 6)] = (insn >> 16) & 0xff;
18529 contents[endianflip ^ (target + 7)] = (insn >> 24) & 0xff;
18530 }
18531 break;
c7b8f16e 18532
99059e56
RM		 18533 default:
18534 abort ();
18535 }
18536 }
c7b8f16e 18537 }
e489d0ae 18538
a504d23a
LA		 18539 if (arm_data->stm32l4xx_erratumcount != 0)
18540 {
18541 for (stm32l4xx_errnode = arm_data->stm32l4xx_erratumlist;
18542 stm32l4xx_errnode != 0;
18543 stm32l4xx_errnode = stm32l4xx_errnode->next)
18544 {
18545 bfd_vma target = stm32l4xx_errnode->vma - offset;
18546
18547 switch (stm32l4xx_errnode->type)
18548 {
18549 case STM32L4XX_ERRATUM_BRANCH_TO_VENEER:
18550 {
18551 unsigned int insn;
18552 bfd_vma branch_to_veneer =
18553 stm32l4xx_errnode->u.b.veneer->vma - stm32l4xx_errnode->vma;
18554
18555 if ((signed) branch_to_veneer < -(1 << 24)
18556 || (signed) branch_to_veneer >= (1 << 24))
18557 {
18558 bfd_vma out_of_range =
18559 ((signed) branch_to_veneer < -(1 << 24)) ?
18560 - branch_to_veneer - (1 << 24) :
18561 ((signed) branch_to_veneer >= (1 << 24)) ?
18562 branch_to_veneer - (1 << 24) : 0;
18563
4eca0228 18564 _bfd_error_handler
a504d23a 18565 (_("%B(%#x): error: Cannot create STM32L4XX veneer. "
eee926f2 18566 "Jump out of range by %ld bytes. "
a504d23a
LA		 18567 "Cannot encode branch instruction. "),
18568 output_bfd,
eee926f2 18569 (long) (stm32l4xx_errnode->vma - 4),
a504d23a
LA		 18570 out_of_range);
18571 continue;
18572 }
18573
18574 insn = create_instruction_branch_absolute
82188b29 18575 (stm32l4xx_errnode->u.b.veneer->vma - stm32l4xx_errnode->vma);
a504d23a
LA		 18576
18577 /* The instruction is before the label. */
18578 target -= 4;
18579
18580 put_thumb2_insn (globals, output_bfd,
18581 (bfd_vma) insn, contents + target);
18582 }
18583 break;
18584
18585 case STM32L4XX_ERRATUM_VENEER:
18586 {
82188b29
NC		 18587 bfd_byte * veneer;
18588 bfd_byte * veneer_r;
a504d23a
LA		 18589 unsigned int insn;
18590
82188b29
NC		 18591 veneer = contents + target;
18592 veneer_r = veneer
18593 + stm32l4xx_errnode->u.b.veneer->vma
18594 - stm32l4xx_errnode->vma - 4;
a504d23a
LA		 18595
18596 if ((signed) (veneer_r - veneer -
18597 STM32L4XX_ERRATUM_VLDM_VENEER_SIZE >
18598 STM32L4XX_ERRATUM_LDM_VENEER_SIZE ?
18599 STM32L4XX_ERRATUM_VLDM_VENEER_SIZE :
18600 STM32L4XX_ERRATUM_LDM_VENEER_SIZE) < -(1 << 24)
18601 || (signed) (veneer_r - veneer) >= (1 << 24))
18602 {
4eca0228
AM		 18603 _bfd_error_handler (_("%B: error: Cannot create STM32L4XX "
18604 "veneer."), output_bfd);
a504d23a
LA		 18605 continue;
18606 }
18607
18608 /* Original instruction. */
18609 insn = stm32l4xx_errnode->u.v.branch->u.b.insn;
18610
18611 stm32l4xx_create_replacing_stub
18612 (globals, output_bfd, insn, (void*)veneer_r, (void*)veneer);
18613 }
18614 break;
18615
18616 default:
18617 abort ();
18618 }
18619 }
18620 }
18621
2468f9c9
PB		 18622 if (arm_data->elf.this_hdr.sh_type == SHT_ARM_EXIDX)
18623 {
18624 arm_unwind_table_edit *edit_node
99059e56 18625 = arm_data->u.exidx.unwind_edit_list;
2468f9c9 18626 /* Now, sec->size is the size of the section we will write. The original
99059e56 18627 size (before we merged duplicate entries and inserted EXIDX_CANTUNWIND
2468f9c9
PB		 18628 markers) was sec->rawsize. (This isn't the case if we perform no
18629 edits, then rawsize will be zero and we should use size). */
21d799b5 18630 bfd_byte *edited_contents = (bfd_byte *) bfd_malloc (sec->size);
2468f9c9
PB		 18631 unsigned int input_size = sec->rawsize ? sec->rawsize : sec->size;
18632 unsigned int in_index, out_index;
18633 bfd_vma add_to_offsets = 0;
18634
18635 for (in_index = 0, out_index = 0; in_index * 8 < input_size || edit_node;)
99059e56 18636 {
2468f9c9
PB		 18637 if (edit_node)
18638 {
18639 unsigned int edit_index = edit_node->index;
b38cadfb 18640
2468f9c9 18641 if (in_index < edit_index && in_index * 8 < input_size)
99059e56 18642 {
2468f9c9
PB		 18643 copy_exidx_entry (output_bfd, edited_contents + out_index * 8,
18644 contents + in_index * 8, add_to_offsets);
18645 out_index++;
18646 in_index++;
18647 }
18648 else if (in_index == edit_index
18649 || (in_index * 8 >= input_size
18650 && edit_index == UINT_MAX))
99059e56 18651 {
2468f9c9
PB		 18652 switch (edit_node->type)
18653 {
18654 case DELETE_EXIDX_ENTRY:
18655 in_index++;
18656 add_to_offsets += 8;
18657 break;
b38cadfb 18658
2468f9c9
PB		 18659 case INSERT_EXIDX_CANTUNWIND_AT_END:
18660 {
99059e56 18661 asection *text_sec = edit_node->linked_section;
2468f9c9
PB		 18662 bfd_vma text_offset = text_sec->output_section->vma
18663 + text_sec->output_offset
18664 + text_sec->size;
18665 bfd_vma exidx_offset = offset + out_index * 8;
99059e56 18666 unsigned long prel31_offset;
2468f9c9
PB		 18667
18668 /* Note: this is meant to be equivalent to an
18669 R_ARM_PREL31 relocation. These synthetic
18670 EXIDX_CANTUNWIND markers are not relocated by the
18671 usual BFD method. */
18672 prel31_offset = (text_offset - exidx_offset)
18673 & 0x7ffffffful;
491d01d3
YU		 18674 if (bfd_link_relocatable (link_info))
18675 {
18676 /* Here relocation for new EXIDX_CANTUNWIND is
18677 created, so there is no need to
18678 adjust offset by hand. */
18679 prel31_offset = text_sec->output_offset
18680 + text_sec->size;
491d01d3 18681 }
2468f9c9
PB		 18682
18683 /* First address we can't unwind. */
18684 bfd_put_32 (output_bfd, prel31_offset,
18685 &edited_contents[out_index * 8]);
18686
18687 /* Code for EXIDX_CANTUNWIND. */
18688 bfd_put_32 (output_bfd, 0x1,
18689 &edited_contents[out_index * 8 + 4]);
18690
18691 out_index++;
18692 add_to_offsets -= 8;
18693 }
18694 break;
18695 }
b38cadfb 18696
2468f9c9
PB		 18697 edit_node = edit_node->next;
18698 }
18699 }
18700 else
18701 {
18702 /* No more edits, copy remaining entries verbatim. */
18703 copy_exidx_entry (output_bfd, edited_contents + out_index * 8,
18704 contents + in_index * 8, add_to_offsets);
18705 out_index++;
18706 in_index++;
18707 }
18708 }
18709
18710 if (!(sec->flags & SEC_EXCLUDE) && !(sec->flags & SEC_NEVER_LOAD))
18711 bfd_set_section_contents (output_bfd, sec->output_section,
18712 edited_contents,
18713 (file_ptr) sec->output_offset, sec->size);
18714
18715 return TRUE;
18716 }
18717
48229727
JB		 18718 /* Fix code to point to Cortex-A8 erratum stubs. */
18719 if (globals->fix_cortex_a8)
18720 {
18721 struct a8_branch_to_stub_data data;
18722
18723 data.writing_section = sec;
18724 data.contents = contents;
18725
a504d23a
LA		 18726 bfd_hash_traverse (& globals->stub_hash_table, make_branch_to_a8_stub,
18727 & data);
48229727
JB		 18728 }
18729
e489d0ae
PB		 18730 if (mapcount == 0)
18731 return FALSE;
18732
c7b8f16e 18733 if (globals->byteswap_code)
e489d0ae 18734 {
c7b8f16e 18735 qsort (map, mapcount, sizeof (* map), elf32_arm_compare_mapping);
57e8b36a 18736
c7b8f16e
JB		 18737 ptr = map[0].vma;
18738 for (i = 0; i < mapcount; i++)
99059e56
RM		 18739 {
18740 if (i == mapcount - 1)
c7b8f16e 18741 end = sec->size;
99059e56
RM		 18742 else
18743 end = map[i + 1].vma;
e489d0ae 18744
99059e56 18745 switch (map[i].type)
e489d0ae 18746 {
c7b8f16e
JB		 18747 case 'a':
18748 /* Byte swap code words. */
18749 while (ptr + 3 < end)
99059e56
RM		 18750 {
18751 tmp = contents[ptr];
18752 contents[ptr] = contents[ptr + 3];
18753 contents[ptr + 3] = tmp;
18754 tmp = contents[ptr + 1];
18755 contents[ptr + 1] = contents[ptr + 2];
18756 contents[ptr + 2] = tmp;
18757 ptr += 4;
18758 }
c7b8f16e 18759 break;
e489d0ae 18760
c7b8f16e
JB		 18761 case 't':
18762 /* Byte swap code halfwords. */
18763 while (ptr + 1 < end)
99059e56
RM		 18764 {
18765 tmp = contents[ptr];
18766 contents[ptr] = contents[ptr + 1];
18767 contents[ptr + 1] = tmp;
18768 ptr += 2;
18769 }
c7b8f16e
JB		 18770 break;
18771
18772 case 'd':
18773 /* Leave data alone. */
18774 break;
18775 }
99059e56
RM		 18776 ptr = end;
18777 }
e489d0ae 18778 }
8e3de13a 18779
93204d3a 18780 free (map);
47b2e99c 18781 arm_data->mapcount = -1;
c7b8f16e 18782 arm_data->mapsize = 0;
8e3de13a 18783 arm_data->map = NULL;
8e3de13a 18784
e489d0ae
PB		 18785 return FALSE;
18786}
18787
0beaef2b
PB		 18788/* Mangle thumb function symbols as we read them in. */
18789
8384fb8f 18790static bfd_boolean
0beaef2b
PB		 18791elf32_arm_swap_symbol_in (bfd * abfd,
18792 const void *psrc,
18793 const void *pshn,
18794 Elf_Internal_Sym *dst)
18795{
4ba2ef8f
TP		 18796 Elf_Internal_Shdr *symtab_hdr;
18797 const char *name = NULL;
18798
8384fb8f
AM		 18799 if (!bfd_elf32_swap_symbol_in (abfd, psrc, pshn, dst))
18800 return FALSE;
39d911fc 18801 dst->st_target_internal = 0;
0beaef2b
PB		 18802
18803 /* New EABI objects mark thumb function symbols by setting the low bit of
35fc36a8 18804 the address. */
63e1a0fc
PB		 18805 if (ELF_ST_TYPE (dst->st_info) == STT_FUNC
18806 || ELF_ST_TYPE (dst->st_info) == STT_GNU_IFUNC)
0beaef2b 18807 {
63e1a0fc
PB		 18808 if (dst->st_value & 1)
18809 {
18810 dst->st_value &= ~(bfd_vma) 1;
39d911fc
TP		 18811 ARM_SET_SYM_BRANCH_TYPE (dst->st_target_internal,
18812 ST_BRANCH_TO_THUMB);
63e1a0fc
PB		 18813 }
18814 else
39d911fc 18815 ARM_SET_SYM_BRANCH_TYPE (dst->st_target_internal, ST_BRANCH_TO_ARM);
35fc36a8
RS		 18816 }
18817 else if (ELF_ST_TYPE (dst->st_info) == STT_ARM_TFUNC)
18818 {
18819 dst->st_info = ELF_ST_INFO (ELF_ST_BIND (dst->st_info), STT_FUNC);
39d911fc 18820 ARM_SET_SYM_BRANCH_TYPE (dst->st_target_internal, ST_BRANCH_TO_THUMB);
0beaef2b 18821 }
35fc36a8 18822 else if (ELF_ST_TYPE (dst->st_info) == STT_SECTION)
39d911fc 18823 ARM_SET_SYM_BRANCH_TYPE (dst->st_target_internal, ST_BRANCH_LONG);
35fc36a8 18824 else
39d911fc 18825 ARM_SET_SYM_BRANCH_TYPE (dst->st_target_internal, ST_BRANCH_UNKNOWN);
35fc36a8 18826
4ba2ef8f
TP		 18827 /* Mark CMSE special symbols. */
18828 symtab_hdr = & elf_symtab_hdr (abfd);
18829 if (symtab_hdr->sh_size)
18830 name = bfd_elf_sym_name (abfd, symtab_hdr, dst, NULL);
18831 if (name && CONST_STRNEQ (name, CMSE_PREFIX))
18832 ARM_SET_SYM_CMSE_SPCL (dst->st_target_internal);
18833
8384fb8f 18834 return TRUE;
0beaef2b
PB		 18835}
18836
18837
18838/* Mangle thumb function symbols as we write them out. */
18839
18840static void
18841elf32_arm_swap_symbol_out (bfd *abfd,
18842 const Elf_Internal_Sym *src,
18843 void *cdst,
18844 void *shndx)
18845{
18846 Elf_Internal_Sym newsym;
18847
18848 /* We convert STT_ARM_TFUNC symbols into STT_FUNC with the low bit
18849 of the address set, as per the new EABI. We do this unconditionally
18850 because objcopy does not set the elf header flags until after
18851 it writes out the symbol table. */
39d911fc 18852 if (ARM_GET_SYM_BRANCH_TYPE (src->st_target_internal) == ST_BRANCH_TO_THUMB)
0beaef2b
PB		 18853 {
18854 newsym = *src;
34e77a92
RS		 18855 if (ELF_ST_TYPE (src->st_info) != STT_GNU_IFUNC)
18856 newsym.st_info = ELF_ST_INFO (ELF_ST_BIND (src->st_info), STT_FUNC);
0fa3dcad 18857 if (newsym.st_shndx != SHN_UNDEF)
99059e56
RM		 18858 {
18859 /* Do this only for defined symbols. At link type, the static
18860 linker will simulate the work of dynamic linker of resolving
18861 symbols and will carry over the thumbness of found symbols to
18862 the output symbol table. It's not clear how it happens, but
18863 the thumbness of undefined symbols can well be different at
18864 runtime, and writing '1' for them will be confusing for users
18865 and possibly for dynamic linker itself.
18866 */
18867 newsym.st_value |= 1;
18868 }
906e58ca 18869
0beaef2b
PB		 18870 src = &newsym;
18871 }
18872 bfd_elf32_swap_symbol_out (abfd, src, cdst, shndx);
18873}
18874
b294bdf8
MM		 18875/* Add the PT_ARM_EXIDX program header. */
18876
18877static bfd_boolean
906e58ca 18878elf32_arm_modify_segment_map (bfd *abfd,
b294bdf8
MM		 18879 struct bfd_link_info *info ATTRIBUTE_UNUSED)
18880{
18881 struct elf_segment_map *m;
18882 asection *sec;
18883
18884 sec = bfd_get_section_by_name (abfd, ".ARM.exidx");
18885 if (sec != NULL && (sec->flags & SEC_LOAD) != 0)
18886 {
18887 /* If there is already a PT_ARM_EXIDX header, then we do not
18888 want to add another one. This situation arises when running
18889 "strip"; the input binary already has the header. */
12bd6957 18890 m = elf_seg_map (abfd);
b294bdf8
MM		 18891 while (m && m->p_type != PT_ARM_EXIDX)
18892 m = m->next;
18893 if (!m)
18894 {
21d799b5 18895 m = (struct elf_segment_map *)
99059e56 18896 bfd_zalloc (abfd, sizeof (struct elf_segment_map));
b294bdf8
MM		 18897 if (m == NULL)
18898 return FALSE;
18899 m->p_type = PT_ARM_EXIDX;
18900 m->count = 1;
18901 m->sections[0] = sec;
18902
12bd6957
AM		 18903 m->next = elf_seg_map (abfd);
18904 elf_seg_map (abfd) = m;
b294bdf8
MM		 18905 }
18906 }
18907
18908 return TRUE;
18909}
18910
18911/* We may add a PT_ARM_EXIDX program header. */
18912
18913static int
a6b96beb
AM		 18914elf32_arm_additional_program_headers (bfd *abfd,
18915 struct bfd_link_info *info ATTRIBUTE_UNUSED)
b294bdf8
MM		 18916{
18917 asection *sec;
18918
18919 sec = bfd_get_section_by_name (abfd, ".ARM.exidx");
18920 if (sec != NULL && (sec->flags & SEC_LOAD) != 0)
18921 return 1;
18922 else
18923 return 0;
18924}
18925
34e77a92
RS		 18926/* Hook called by the linker routine which adds symbols from an object
18927 file. */
18928
18929static bfd_boolean
18930elf32_arm_add_symbol_hook (bfd *abfd, struct bfd_link_info *info,
18931 Elf_Internal_Sym *sym, const char **namep,
18932 flagword *flagsp, asection **secp, bfd_vma *valp)
18933{
a43942db 18934 if (ELF_ST_TYPE (sym->st_info) == STT_GNU_IFUNC
f1885d1e
AM		 18935 && (abfd->flags & DYNAMIC) == 0
18936 && bfd_get_flavour (info->output_bfd) == bfd_target_elf_flavour)
a43942db 18937 elf_tdata (info->output_bfd)->has_gnu_symbols |= elf_gnu_symbol_ifunc;
34e77a92 18938
c792917c
NC		 18939 if (elf32_arm_hash_table (info) == NULL)
18940 return FALSE;
18941
34e77a92
RS		 18942 if (elf32_arm_hash_table (info)->vxworks_p
18943 && !elf_vxworks_add_symbol_hook (abfd, info, sym, namep,
18944 flagsp, secp, valp))
18945 return FALSE;
18946
18947 return TRUE;
18948}
18949
0beaef2b 18950/* We use this to override swap_symbol_in and swap_symbol_out. */
906e58ca
NC		 18951const struct elf_size_info elf32_arm_size_info =
18952{
0beaef2b
PB		 18953 sizeof (Elf32_External_Ehdr),
18954 sizeof (Elf32_External_Phdr),
18955 sizeof (Elf32_External_Shdr),
18956 sizeof (Elf32_External_Rel),
18957 sizeof (Elf32_External_Rela),
18958 sizeof (Elf32_External_Sym),
18959 sizeof (Elf32_External_Dyn),
18960 sizeof (Elf_External_Note),
18961 4,
18962 1,
18963 32, 2,
18964 ELFCLASS32, EV_CURRENT,
18965 bfd_elf32_write_out_phdrs,
18966 bfd_elf32_write_shdrs_and_ehdr,
1489a3a0 18967 bfd_elf32_checksum_contents,
0beaef2b
PB		 18968 bfd_elf32_write_relocs,
18969 elf32_arm_swap_symbol_in,
18970 elf32_arm_swap_symbol_out,
18971 bfd_elf32_slurp_reloc_table,
18972 bfd_elf32_slurp_symbol_table,
18973 bfd_elf32_swap_dyn_in,
18974 bfd_elf32_swap_dyn_out,
18975 bfd_elf32_swap_reloc_in,
18976 bfd_elf32_swap_reloc_out,
18977 bfd_elf32_swap_reloca_in,
18978 bfd_elf32_swap_reloca_out
18979};
18980
685e70ae
VK		 18981static bfd_vma
18982read_code32 (const bfd *abfd, const bfd_byte *addr)
18983{
18984 /* V7 BE8 code is always little endian. */
18985 if ((elf_elfheader (abfd)->e_flags & EF_ARM_BE8) != 0)
18986 return bfd_getl32 (addr);
18987
18988 return bfd_get_32 (abfd, addr);
18989}
18990
18991static bfd_vma
18992read_code16 (const bfd *abfd, const bfd_byte *addr)
18993{
18994 /* V7 BE8 code is always little endian. */
18995 if ((elf_elfheader (abfd)->e_flags & EF_ARM_BE8) != 0)
18996 return bfd_getl16 (addr);
18997
18998 return bfd_get_16 (abfd, addr);
18999}
19000
6a631e86
YG		 19001/* Return size of plt0 entry starting at ADDR
19002 or (bfd_vma) -1 if size can not be determined. */
19003
19004static bfd_vma
19005elf32_arm_plt0_size (const bfd *abfd, const bfd_byte *addr)
19006{
19007 bfd_vma first_word;
19008 bfd_vma plt0_size;
19009
685e70ae 19010 first_word = read_code32 (abfd, addr);
6a631e86
YG		 19011
19012 if (first_word == elf32_arm_plt0_entry[0])
19013 plt0_size = 4 * ARRAY_SIZE (elf32_arm_plt0_entry);
19014 else if (first_word == elf32_thumb2_plt0_entry[0])
19015 plt0_size = 4 * ARRAY_SIZE (elf32_thumb2_plt0_entry);
19016 else
19017 /* We don't yet handle this PLT format. */
19018 return (bfd_vma) -1;
19019
19020 return plt0_size;
19021}
19022
19023/* Return size of plt entry starting at offset OFFSET
19024 of plt section located at address START
19025 or (bfd_vma) -1 if size can not be determined. */
19026
19027static bfd_vma
19028elf32_arm_plt_size (const bfd *abfd, const bfd_byte *start, bfd_vma offset)
19029{
19030 bfd_vma first_insn;
19031 bfd_vma plt_size = 0;
19032 const bfd_byte *addr = start + offset;
19033
19034 /* PLT entry size if fixed on Thumb-only platforms. */
685e70ae 19035 if (read_code32 (abfd, start) == elf32_thumb2_plt0_entry[0])
6a631e86
YG		 19036 return 4 * ARRAY_SIZE (elf32_thumb2_plt_entry);
19037
19038 /* Respect Thumb stub if necessary. */
685e70ae 19039 if (read_code16 (abfd, addr) == elf32_arm_plt_thumb_stub[0])
6a631e86
YG		 19040 {
19041 plt_size += 2 * ARRAY_SIZE(elf32_arm_plt_thumb_stub);
19042 }
19043
19044 /* Strip immediate from first add. */
685e70ae 19045 first_insn = read_code32 (abfd, addr + plt_size) & 0xffffff00;
6a631e86
YG		 19046
19047#ifdef FOUR_WORD_PLT
19048 if (first_insn == elf32_arm_plt_entry[0])
19049 plt_size += 4 * ARRAY_SIZE (elf32_arm_plt_entry);
19050#else
19051 if (first_insn == elf32_arm_plt_entry_long[0])
19052 plt_size += 4 * ARRAY_SIZE (elf32_arm_plt_entry_long);
19053 else if (first_insn == elf32_arm_plt_entry_short[0])
19054 plt_size += 4 * ARRAY_SIZE (elf32_arm_plt_entry_short);
19055#endif
19056 else
19057 /* We don't yet handle this PLT format. */
19058 return (bfd_vma) -1;
19059
19060 return plt_size;
19061}
19062
19063/* Implementation is shamelessly borrowed from _bfd_elf_get_synthetic_symtab. */
19064
19065static long
19066elf32_arm_get_synthetic_symtab (bfd *abfd,
19067 long symcount ATTRIBUTE_UNUSED,
19068 asymbol **syms ATTRIBUTE_UNUSED,
19069 long dynsymcount,
19070 asymbol **dynsyms,
19071 asymbol **ret)
19072{
19073 asection *relplt;
19074 asymbol *s;
19075 arelent *p;
19076 long count, i, n;
19077 size_t size;
19078 Elf_Internal_Shdr *hdr;
19079 char *names;
19080 asection *plt;
19081 bfd_vma offset;
19082 bfd_byte *data;
19083
19084 *ret = NULL;
19085
19086 if ((abfd->flags & (DYNAMIC | EXEC_P)) == 0)
19087 return 0;
19088
19089 if (dynsymcount <= 0)
19090 return 0;
19091
19092 relplt = bfd_get_section_by_name (abfd, ".rel.plt");
19093 if (relplt == NULL)
19094 return 0;
19095
19096 hdr = &elf_section_data (relplt)->this_hdr;
19097 if (hdr->sh_link != elf_dynsymtab (abfd)
19098 || (hdr->sh_type != SHT_REL && hdr->sh_type != SHT_RELA))
19099 return 0;
19100
19101 plt = bfd_get_section_by_name (abfd, ".plt");
19102 if (plt == NULL)
19103 return 0;
19104
19105 if (!elf32_arm_size_info.slurp_reloc_table (abfd, relplt, dynsyms, TRUE))
19106 return -1;
19107
19108 data = plt->contents;
19109 if (data == NULL)
19110 {
19111 if (!bfd_get_full_section_contents(abfd, (asection *) plt, &data) || data == NULL)
19112 return -1;
19113 bfd_cache_section_contents((asection *) plt, data);
19114 }
19115
19116 count = relplt->size / hdr->sh_entsize;
19117 size = count * sizeof (asymbol);
19118 p = relplt->relocation;
19119 for (i = 0; i < count; i++, p += elf32_arm_size_info.int_rels_per_ext_rel)
19120 {
19121 size += strlen ((*p->sym_ptr_ptr)->name) + sizeof ("@plt");
19122 if (p->addend != 0)
19123 size += sizeof ("+0x") - 1 + 8;
19124 }
19125
19126 s = *ret = (asymbol *) bfd_malloc (size);
19127 if (s == NULL)
19128 return -1;
19129
19130 offset = elf32_arm_plt0_size (abfd, data);
19131 if (offset == (bfd_vma) -1)
19132 return -1;
19133
19134 names = (char *) (s + count);
19135 p = relplt->relocation;
19136 n = 0;
19137 for (i = 0; i < count; i++, p += elf32_arm_size_info.int_rels_per_ext_rel)
19138 {
19139 size_t len;
19140
19141 bfd_vma plt_size = elf32_arm_plt_size (abfd, data, offset);
19142 if (plt_size == (bfd_vma) -1)
19143 break;
19144
19145 *s = **p->sym_ptr_ptr;
19146 /* Undefined syms won't have BSF_LOCAL or BSF_GLOBAL set. Since
19147 we are defining a symbol, ensure one of them is set. */
19148 if ((s->flags & BSF_LOCAL) == 0)
19149 s->flags |= BSF_GLOBAL;
19150 s->flags |= BSF_SYNTHETIC;
19151 s->section = plt;
19152 s->value = offset;
19153 s->name = names;
19154 s->udata.p = NULL;
19155 len = strlen ((*p->sym_ptr_ptr)->name);
19156 memcpy (names, (*p->sym_ptr_ptr)->name, len);
19157 names += len;
19158 if (p->addend != 0)
19159 {
19160 char buf[30], *a;
19161
19162 memcpy (names, "+0x", sizeof ("+0x") - 1);
19163 names += sizeof ("+0x") - 1;
19164 bfd_sprintf_vma (abfd, buf, p->addend);
19165 for (a = buf; *a == '0'; ++a)
19166 ;
19167 len = strlen (a);
19168 memcpy (names, a, len);
19169 names += len;
19170 }
19171 memcpy (names, "@plt", sizeof ("@plt"));
19172 names += sizeof ("@plt");
19173 ++s, ++n;
19174 offset += plt_size;
19175 }
19176
19177 return n;
19178}
19179
ac4c9b04
MG		 19180static bfd_boolean
19181elf32_arm_section_flags (flagword *flags, const Elf_Internal_Shdr * hdr)
19182{
f0728ee3
AV		 19183 if (hdr->sh_flags & SHF_ARM_PURECODE)
19184 *flags |= SEC_ELF_PURECODE;
ac4c9b04
MG		 19185 return TRUE;
19186}
19187
19188static flagword
19189elf32_arm_lookup_section_flags (char *flag_name)
19190{
f0728ee3
AV		 19191 if (!strcmp (flag_name, "SHF_ARM_PURECODE"))
19192 return SHF_ARM_PURECODE;
ac4c9b04
MG		 19193
19194 return SEC_NO_FLAGS;
19195}
19196
491d01d3
YU		 19197static unsigned int
19198elf32_arm_count_additional_relocs (asection *sec)
19199{
19200 struct _arm_elf_section_data *arm_data;
19201 arm_data = get_arm_elf_section_data (sec);
5025eb7c 19202
6342be70 19203 return arm_data == NULL ? 0 : arm_data->additional_reloc_count;
491d01d3
YU		 19204}
19205
5522f910 19206/* Called to set the sh_flags, sh_link and sh_info fields of OSECTION which
9eaff861 19207 has a type >= SHT_LOOS. Returns TRUE if these fields were initialised
5522f910
NC		 19208 FALSE otherwise. ISECTION is the best guess matching section from the
19209 input bfd IBFD, but it might be NULL. */
19210
19211static bfd_boolean
19212elf32_arm_copy_special_section_fields (const bfd *ibfd ATTRIBUTE_UNUSED,
19213 bfd *obfd ATTRIBUTE_UNUSED,
19214 const Elf_Internal_Shdr *isection ATTRIBUTE_UNUSED,
19215 Elf_Internal_Shdr *osection)
19216{
19217 switch (osection->sh_type)
19218 {
19219 case SHT_ARM_EXIDX:
19220 {
19221 Elf_Internal_Shdr **oheaders = elf_elfsections (obfd);
19222 Elf_Internal_Shdr **iheaders = elf_elfsections (ibfd);
19223 unsigned i = 0;
19224
19225 osection->sh_flags = SHF_ALLOC | SHF_LINK_ORDER;
19226 osection->sh_info = 0;
19227
19228 /* The sh_link field must be set to the text section associated with
19229 this index section. Unfortunately the ARM EHABI does not specify
19230 exactly how to determine this association. Our caller does try
19231 to match up OSECTION with its corresponding input section however
19232 so that is a good first guess. */
19233 if (isection != NULL
19234 && osection->bfd_section != NULL
19235 && isection->bfd_section != NULL
19236 && isection->bfd_section->output_section != NULL
19237 && isection->bfd_section->output_section == osection->bfd_section
19238 && iheaders != NULL
19239 && isection->sh_link > 0
19240 && isection->sh_link < elf_numsections (ibfd)
19241 && iheaders[isection->sh_link]->bfd_section != NULL
19242 && iheaders[isection->sh_link]->bfd_section->output_section != NULL
19243 )
19244 {
19245 for (i = elf_numsections (obfd); i-- > 0;)
19246 if (oheaders[i]->bfd_section
19247 == iheaders[isection->sh_link]->bfd_section->output_section)
19248 break;
19249 }
9eaff861 19250
5522f910
NC		 19251 if (i == 0)
19252 {
19253 /* Failing that we have to find a matching section ourselves. If
19254 we had the output section name available we could compare that
19255 with input section names. Unfortunately we don't. So instead
19256 we use a simple heuristic and look for the nearest executable
19257 section before this one. */
19258 for (i = elf_numsections (obfd); i-- > 0;)
19259 if (oheaders[i] == osection)
19260 break;
19261 if (i == 0)
19262 break;
19263
19264 while (i-- > 0)
19265 if (oheaders[i]->sh_type == SHT_PROGBITS
19266 && (oheaders[i]->sh_flags & (SHF_ALLOC | SHF_EXECINSTR))
19267 == (SHF_ALLOC | SHF_EXECINSTR))
19268 break;
19269 }
19270
19271 if (i)
19272 {
19273 osection->sh_link = i;
19274 /* If the text section was part of a group
19275 then the index section should be too. */
19276 if (oheaders[i]->sh_flags & SHF_GROUP)
19277 osection->sh_flags |= SHF_GROUP;
19278 return TRUE;
19279 }
19280 }
19281 break;
19282
19283 case SHT_ARM_PREEMPTMAP:
19284 osection->sh_flags = SHF_ALLOC;
19285 break;
19286
19287 case SHT_ARM_ATTRIBUTES:
19288 case SHT_ARM_DEBUGOVERLAY:
19289 case SHT_ARM_OVERLAYSECTION:
19290 default:
19291 break;
19292 }
19293
19294 return FALSE;
19295}
19296
d691934d
NC		 19297/* Returns TRUE if NAME is an ARM mapping symbol.
19298 Traditionally the symbols $a, $d and $t have been used.
19299 The ARM ELF standard also defines $x (for A64 code). It also allows a
19300 period initiated suffix to be added to the symbol: "$[adtx]\.[:sym_char]+".
19301 Other tools might also produce $b (Thumb BL), $f, $p, $m and $v, but we do
19302 not support them here. $t.x indicates the start of ThumbEE instructions. */
19303
19304static bfd_boolean
19305is_arm_mapping_symbol (const char * name)
19306{
19307 return name != NULL /* Paranoia. */
19308 && name[0] == '$' /* Note: if objcopy --prefix-symbols has been used then
19309 the mapping symbols could have acquired a prefix.
19310 We do not support this here, since such symbols no
19311 longer conform to the ARM ELF ABI. */
19312 && (name[1] == 'a' || name[1] == 'd' || name[1] == 't' || name[1] == 'x')
19313 && (name[2] == 0 || name[2] == '.');
19314 /* FIXME: Strictly speaking the symbol is only a valid mapping symbol if
19315 any characters that follow the period are legal characters for the body
19316 of a symbol's name. For now we just assume that this is the case. */
19317}
19318
fca2a38f
NC		 19319/* Make sure that mapping symbols in object files are not removed via the
19320 "strip --strip-unneeded" tool. These symbols are needed in order to
19321 correctly generate interworking veneers, and for byte swapping code
19322 regions. Once an object file has been linked, it is safe to remove the
19323 symbols as they will no longer be needed. */
19324
19325static void
19326elf32_arm_backend_symbol_processing (bfd *abfd, asymbol *sym)
19327{
19328 if (((abfd->flags & (EXEC_P | DYNAMIC)) == 0)
fca2a38f 19329 && sym->section != bfd_abs_section_ptr
d691934d 19330 && is_arm_mapping_symbol (sym->name))
fca2a38f
NC		 19331 sym->flags |= BSF_KEEP;
19332}
19333
5522f910
NC		 19334#undef elf_backend_copy_special_section_fields
19335#define elf_backend_copy_special_section_fields elf32_arm_copy_special_section_fields
19336
252b5132 19337#define ELF_ARCH bfd_arch_arm
ae95ffa6 19338#define ELF_TARGET_ID ARM_ELF_DATA
252b5132 19339#define ELF_MACHINE_CODE EM_ARM
d0facd1b
NC		 19340#ifdef __QNXTARGET__
19341#define ELF_MAXPAGESIZE 0x1000
19342#else
7572ca89 19343#define ELF_MAXPAGESIZE 0x10000
d0facd1b 19344#endif
b1342370 19345#define ELF_MINPAGESIZE 0x1000
24718e3b 19346#define ELF_COMMONPAGESIZE 0x1000
252b5132 19347
ba93b8ac
DJ		 19348#define bfd_elf32_mkobject elf32_arm_mkobject
19349
99e4ae17
AJ		 19350#define bfd_elf32_bfd_copy_private_bfd_data elf32_arm_copy_private_bfd_data
19351#define bfd_elf32_bfd_merge_private_bfd_data elf32_arm_merge_private_bfd_data
252b5132
RH		 19352#define bfd_elf32_bfd_set_private_flags elf32_arm_set_private_flags
19353#define bfd_elf32_bfd_print_private_bfd_data elf32_arm_print_private_bfd_data
19354#define bfd_elf32_bfd_link_hash_table_create elf32_arm_link_hash_table_create
dc810e39 19355#define bfd_elf32_bfd_reloc_type_lookup elf32_arm_reloc_type_lookup
b38cadfb 19356#define bfd_elf32_bfd_reloc_name_lookup elf32_arm_reloc_name_lookup
252b5132 19357#define bfd_elf32_find_nearest_line elf32_arm_find_nearest_line
4ab527b0 19358#define bfd_elf32_find_inliner_info elf32_arm_find_inliner_info
e489d0ae 19359#define bfd_elf32_new_section_hook elf32_arm_new_section_hook
3c9458e9 19360#define bfd_elf32_bfd_is_target_special_symbol elf32_arm_is_target_special_symbol
3e6b1042 19361#define bfd_elf32_bfd_final_link elf32_arm_final_link
6a631e86 19362#define bfd_elf32_get_synthetic_symtab elf32_arm_get_synthetic_symtab
252b5132
RH		 19363
19364#define elf_backend_get_symbol_type elf32_arm_get_symbol_type
19365#define elf_backend_gc_mark_hook elf32_arm_gc_mark_hook
6a5bb875 19366#define elf_backend_gc_mark_extra_sections elf32_arm_gc_mark_extra_sections
252b5132
RH		 19367#define elf_backend_gc_sweep_hook elf32_arm_gc_sweep_hook
19368#define elf_backend_check_relocs elf32_arm_check_relocs
9eaff861 19369#define elf_backend_update_relocs elf32_arm_update_relocs
dc810e39 19370#define elf_backend_relocate_section elf32_arm_relocate_section
e489d0ae 19371#define elf_backend_write_section elf32_arm_write_section
252b5132 19372#define elf_backend_adjust_dynamic_symbol elf32_arm_adjust_dynamic_symbol
5e681ec4 19373#define elf_backend_create_dynamic_sections elf32_arm_create_dynamic_sections
252b5132
RH		 19374#define elf_backend_finish_dynamic_symbol elf32_arm_finish_dynamic_symbol
19375#define elf_backend_finish_dynamic_sections elf32_arm_finish_dynamic_sections
19376#define elf_backend_size_dynamic_sections elf32_arm_size_dynamic_sections
0855e32b 19377#define elf_backend_always_size_sections elf32_arm_always_size_sections
74541ad4 19378#define elf_backend_init_index_section _bfd_elf_init_2_index_sections
ba96a88f 19379#define elf_backend_post_process_headers elf32_arm_post_process_headers
99e4ae17 19380#define elf_backend_reloc_type_class elf32_arm_reloc_type_class
c178919b 19381#define elf_backend_object_p elf32_arm_object_p
40a18ebd
NC		 19382#define elf_backend_fake_sections elf32_arm_fake_sections
19383#define elf_backend_section_from_shdr elf32_arm_section_from_shdr
e16bb312 19384#define elf_backend_final_write_processing elf32_arm_final_write_processing
5e681ec4 19385#define elf_backend_copy_indirect_symbol elf32_arm_copy_indirect_symbol
0beaef2b 19386#define elf_backend_size_info elf32_arm_size_info
b294bdf8 19387#define elf_backend_modify_segment_map elf32_arm_modify_segment_map
906e58ca
NC		 19388#define elf_backend_additional_program_headers elf32_arm_additional_program_headers
19389#define elf_backend_output_arch_local_syms elf32_arm_output_arch_local_syms
54ddd295 19390#define elf_backend_filter_implib_symbols elf32_arm_filter_implib_symbols
906e58ca 19391#define elf_backend_begin_write_processing elf32_arm_begin_write_processing
34e77a92 19392#define elf_backend_add_symbol_hook elf32_arm_add_symbol_hook
491d01d3 19393#define elf_backend_count_additional_relocs elf32_arm_count_additional_relocs
fca2a38f 19394#define elf_backend_symbol_processing elf32_arm_backend_symbol_processing
906e58ca
NC		 19395
19396#define elf_backend_can_refcount 1
19397#define elf_backend_can_gc_sections 1
19398#define elf_backend_plt_readonly 1
19399#define elf_backend_want_got_plt 1
19400#define elf_backend_want_plt_sym 0
19401#define elf_backend_may_use_rel_p 1
19402#define elf_backend_may_use_rela_p 0
4e7fd91e 19403#define elf_backend_default_use_rela_p 0
64f52338 19404#define elf_backend_dtrel_excludes_plt 1
252b5132 19405
04f7c78d 19406#define elf_backend_got_header_size 12
b68a20d6 19407#define elf_backend_extern_protected_data 1
04f7c78d 19408
906e58ca
NC		 19409#undef elf_backend_obj_attrs_vendor
19410#define elf_backend_obj_attrs_vendor "aeabi"
19411#undef elf_backend_obj_attrs_section
19412#define elf_backend_obj_attrs_section ".ARM.attributes"
19413#undef elf_backend_obj_attrs_arg_type
19414#define elf_backend_obj_attrs_arg_type elf32_arm_obj_attrs_arg_type
19415#undef elf_backend_obj_attrs_section_type
104d59d1 19416#define elf_backend_obj_attrs_section_type SHT_ARM_ATTRIBUTES
b38cadfb
NC		 19417#define elf_backend_obj_attrs_order elf32_arm_obj_attrs_order
19418#define elf_backend_obj_attrs_handle_unknown elf32_arm_obj_attrs_handle_unknown
104d59d1 19419
5025eb7c 19420#undef elf_backend_section_flags
ac4c9b04 19421#define elf_backend_section_flags elf32_arm_section_flags
5025eb7c 19422#undef elf_backend_lookup_section_flags_hook
ac4c9b04
MG		 19423#define elf_backend_lookup_section_flags_hook elf32_arm_lookup_section_flags
19424
252b5132 19425#include "elf32-target.h"
7f266840 19426
b38cadfb
NC		 19427/* Native Client targets. */
19428
19429#undef TARGET_LITTLE_SYM
6d00b590 19430#define TARGET_LITTLE_SYM arm_elf32_nacl_le_vec
b38cadfb
NC		 19431#undef TARGET_LITTLE_NAME
19432#define TARGET_LITTLE_NAME "elf32-littlearm-nacl"
19433#undef TARGET_BIG_SYM
6d00b590 19434#define TARGET_BIG_SYM arm_elf32_nacl_be_vec
b38cadfb
NC		 19435#undef TARGET_BIG_NAME
19436#define TARGET_BIG_NAME "elf32-bigarm-nacl"
19437
19438/* Like elf32_arm_link_hash_table_create -- but overrides
19439 appropriately for NaCl. */
19440
19441static struct bfd_link_hash_table *
19442elf32_arm_nacl_link_hash_table_create (bfd *abfd)
19443{
19444 struct bfd_link_hash_table *ret;
19445
19446 ret = elf32_arm_link_hash_table_create (abfd);
19447 if (ret)
19448 {
19449 struct elf32_arm_link_hash_table *htab
19450 = (struct elf32_arm_link_hash_table *) ret;
19451
19452 htab->nacl_p = 1;
19453
19454 htab->plt_header_size = 4 * ARRAY_SIZE (elf32_arm_nacl_plt0_entry);
19455 htab->plt_entry_size = 4 * ARRAY_SIZE (elf32_arm_nacl_plt_entry);
19456 }
19457 return ret;
19458}
19459
19460/* Since NaCl doesn't use the ARM-specific unwind format, we don't
19461 really need to use elf32_arm_modify_segment_map. But we do it
19462 anyway just to reduce gratuitous differences with the stock ARM backend. */
19463
19464static bfd_boolean
19465elf32_arm_nacl_modify_segment_map (bfd *abfd, struct bfd_link_info *info)
19466{
19467 return (elf32_arm_modify_segment_map (abfd, info)
19468 && nacl_modify_segment_map (abfd, info));
19469}
19470
887badb3
RM		 19471static void
19472elf32_arm_nacl_final_write_processing (bfd *abfd, bfd_boolean linker)
19473{
19474 elf32_arm_final_write_processing (abfd, linker);
19475 nacl_final_write_processing (abfd, linker);
19476}
19477
6a631e86
YG		 19478static bfd_vma
19479elf32_arm_nacl_plt_sym_val (bfd_vma i, const asection *plt,
19480 const arelent *rel ATTRIBUTE_UNUSED)
19481{
19482 return plt->vma
19483 + 4 * (ARRAY_SIZE (elf32_arm_nacl_plt0_entry) +
19484 i * ARRAY_SIZE (elf32_arm_nacl_plt_entry));
19485}
887badb3 19486
b38cadfb 19487#undef elf32_bed
6a631e86 19488#define elf32_bed elf32_arm_nacl_bed
b38cadfb
NC		 19489#undef bfd_elf32_bfd_link_hash_table_create
19490#define bfd_elf32_bfd_link_hash_table_create \
19491 elf32_arm_nacl_link_hash_table_create
19492#undef elf_backend_plt_alignment
6a631e86 19493#define elf_backend_plt_alignment 4
b38cadfb
NC		 19494#undef elf_backend_modify_segment_map
19495#define elf_backend_modify_segment_map elf32_arm_nacl_modify_segment_map
19496#undef elf_backend_modify_program_headers
19497#define elf_backend_modify_program_headers nacl_modify_program_headers
887badb3
RM		 19498#undef elf_backend_final_write_processing
19499#define elf_backend_final_write_processing elf32_arm_nacl_final_write_processing
6a631e86
YG		 19500#undef bfd_elf32_get_synthetic_symtab
19501#undef elf_backend_plt_sym_val
19502#define elf_backend_plt_sym_val elf32_arm_nacl_plt_sym_val
5522f910 19503#undef elf_backend_copy_special_section_fields
b38cadfb 19504
887badb3
RM		 19505#undef ELF_MINPAGESIZE
19506#undef ELF_COMMONPAGESIZE
19507
b38cadfb
NC		 19508
19509#include "elf32-target.h"
19510
19511/* Reset to defaults. */
19512#undef elf_backend_plt_alignment
19513#undef elf_backend_modify_segment_map
19514#define elf_backend_modify_segment_map elf32_arm_modify_segment_map
19515#undef elf_backend_modify_program_headers
887badb3
RM		 19516#undef elf_backend_final_write_processing
19517#define elf_backend_final_write_processing elf32_arm_final_write_processing
19518#undef ELF_MINPAGESIZE
19519#define ELF_MINPAGESIZE 0x1000
19520#undef ELF_COMMONPAGESIZE
19521#define ELF_COMMONPAGESIZE 0x1000
19522
b38cadfb 19523
906e58ca 19524/* VxWorks Targets. */
4e7fd91e 19525
906e58ca 19526#undef TARGET_LITTLE_SYM
6d00b590 19527#define TARGET_LITTLE_SYM arm_elf32_vxworks_le_vec
906e58ca 19528#undef TARGET_LITTLE_NAME
4e7fd91e 19529#define TARGET_LITTLE_NAME "elf32-littlearm-vxworks"
906e58ca 19530#undef TARGET_BIG_SYM
6d00b590 19531#define TARGET_BIG_SYM arm_elf32_vxworks_be_vec
906e58ca 19532#undef TARGET_BIG_NAME
4e7fd91e
PB		 19533#define TARGET_BIG_NAME "elf32-bigarm-vxworks"
19534
19535/* Like elf32_arm_link_hash_table_create -- but overrides
19536 appropriately for VxWorks. */
906e58ca 19537
4e7fd91e
PB		 19538static struct bfd_link_hash_table *
19539elf32_arm_vxworks_link_hash_table_create (bfd *abfd)
19540{
19541 struct bfd_link_hash_table *ret;
19542
19543 ret = elf32_arm_link_hash_table_create (abfd);
19544 if (ret)
19545 {
19546 struct elf32_arm_link_hash_table *htab
00a97672 19547 = (struct elf32_arm_link_hash_table *) ret;
4e7fd91e 19548 htab->use_rel = 0;
00a97672 19549 htab->vxworks_p = 1;
4e7fd91e
PB		 19550 }
19551 return ret;
906e58ca 19552}
4e7fd91e 19553
00a97672
RS		 19554static void
19555elf32_arm_vxworks_final_write_processing (bfd *abfd, bfd_boolean linker)
19556{
19557 elf32_arm_final_write_processing (abfd, linker);
19558 elf_vxworks_final_write_processing (abfd, linker);
19559}
19560
906e58ca 19561#undef elf32_bed
4e7fd91e
PB		 19562#define elf32_bed elf32_arm_vxworks_bed
19563
906e58ca
NC		 19564#undef bfd_elf32_bfd_link_hash_table_create
19565#define bfd_elf32_bfd_link_hash_table_create elf32_arm_vxworks_link_hash_table_create
906e58ca
NC		 19566#undef elf_backend_final_write_processing
19567#define elf_backend_final_write_processing elf32_arm_vxworks_final_write_processing
19568#undef elf_backend_emit_relocs
9eaff861 19569#define elf_backend_emit_relocs elf_vxworks_emit_relocs
4e7fd91e 19570
906e58ca 19571#undef elf_backend_may_use_rel_p
00a97672 19572#define elf_backend_may_use_rel_p 0
906e58ca 19573#undef elf_backend_may_use_rela_p
00a97672 19574#define elf_backend_may_use_rela_p 1
906e58ca 19575#undef elf_backend_default_use_rela_p
00a97672 19576#define elf_backend_default_use_rela_p 1
906e58ca 19577#undef elf_backend_want_plt_sym
00a97672 19578#define elf_backend_want_plt_sym 1
906e58ca 19579#undef ELF_MAXPAGESIZE
00a97672 19580#define ELF_MAXPAGESIZE 0x1000
4e7fd91e
PB		 19581
19582#include "elf32-target.h"
19583
19584
21d799b5
NC		 19585/* Merge backend specific data from an object file to the output
19586 object file when linking. */
19587
19588static bfd_boolean
50e03d47 19589elf32_arm_merge_private_bfd_data (bfd *ibfd, struct bfd_link_info *info)
21d799b5 19590{
50e03d47 19591 bfd *obfd = info->output_bfd;
21d799b5
NC		 19592 flagword out_flags;
19593 flagword in_flags;
19594 bfd_boolean flags_compatible = TRUE;
19595 asection *sec;
19596
cc643b88 19597 /* Check if we have the same endianness. */
50e03d47 19598 if (! _bfd_generic_verify_endian_match (ibfd, info))
21d799b5
NC		 19599 return FALSE;
19600
19601 if (! is_arm_elf (ibfd) || ! is_arm_elf (obfd))
19602 return TRUE;
19603
50e03d47 19604 if (!elf32_arm_merge_eabi_attributes (ibfd, info))
21d799b5
NC		 19605 return FALSE;
19606
19607 /* The input BFD must have had its flags initialised. */
19608 /* The following seems bogus to me -- The flags are initialized in
19609 the assembler but I don't think an elf_flags_init field is
19610 written into the object. */
19611 /* BFD_ASSERT (elf_flags_init (ibfd)); */
19612
19613 in_flags = elf_elfheader (ibfd)->e_flags;
19614 out_flags = elf_elfheader (obfd)->e_flags;
19615
19616 /* In theory there is no reason why we couldn't handle this. However
19617 in practice it isn't even close to working and there is no real
19618 reason to want it. */
19619 if (EF_ARM_EABI_VERSION (in_flags) >= EF_ARM_EABI_VER4
19620 && !(ibfd->flags & DYNAMIC)
19621 && (in_flags & EF_ARM_BE8))
19622 {
19623 _bfd_error_handler (_("error: %B is already in final BE8 format"),
19624 ibfd);
19625 return FALSE;
19626 }
19627
19628 if (!elf_flags_init (obfd))
19629 {
19630 /* If the input is the default architecture and had the default
19631 flags then do not bother setting the flags for the output
19632 architecture, instead allow future merges to do this. If no
19633 future merges ever set these flags then they will retain their
99059e56
RM		 19634 uninitialised values, which surprise surprise, correspond
19635 to the default values. */
21d799b5
NC		 19636 if (bfd_get_arch_info (ibfd)->the_default
19637 && elf_elfheader (ibfd)->e_flags == 0)
19638 return TRUE;
19639
19640 elf_flags_init (obfd) = TRUE;
19641 elf_elfheader (obfd)->e_flags = in_flags;
19642
19643 if (bfd_get_arch (obfd) == bfd_get_arch (ibfd)
19644 && bfd_get_arch_info (obfd)->the_default)
19645 return bfd_set_arch_mach (obfd, bfd_get_arch (ibfd), bfd_get_mach (ibfd));
19646
19647 return TRUE;
19648 }
19649
19650 /* Determine what should happen if the input ARM architecture
19651 does not match the output ARM architecture. */
19652 if (! bfd_arm_merge_machines (ibfd, obfd))
19653 return FALSE;
19654
19655 /* Identical flags must be compatible. */
19656 if (in_flags == out_flags)
19657 return TRUE;
19658
19659 /* Check to see if the input BFD actually contains any sections. If
19660 not, its flags may not have been initialised either, but it
19661 cannot actually cause any incompatiblity. Do not short-circuit
19662 dynamic objects; their section list may be emptied by
19663 elf_link_add_object_symbols.
19664
19665 Also check to see if there are no code sections in the input.
19666 In this case there is no need to check for code specific flags.
19667 XXX - do we need to worry about floating-point format compatability
19668 in data sections ? */
19669 if (!(ibfd->flags & DYNAMIC))
19670 {
19671 bfd_boolean null_input_bfd = TRUE;
19672 bfd_boolean only_data_sections = TRUE;
19673
19674 for (sec = ibfd->sections; sec != NULL; sec = sec->next)
19675 {
19676 /* Ignore synthetic glue sections. */
19677 if (strcmp (sec->name, ".glue_7")
19678 && strcmp (sec->name, ".glue_7t"))
19679 {
19680 if ((bfd_get_section_flags (ibfd, sec)
19681 & (SEC_LOAD | SEC_CODE | SEC_HAS_CONTENTS))
19682 == (SEC_LOAD | SEC_CODE | SEC_HAS_CONTENTS))
99059e56 19683 only_data_sections = FALSE;
21d799b5
NC		 19684
19685 null_input_bfd = FALSE;
19686 break;
19687 }
19688 }
19689
19690 if (null_input_bfd || only_data_sections)
19691 return TRUE;
19692 }
19693
19694 /* Complain about various flag mismatches. */
19695 if (!elf32_arm_versions_compatible (EF_ARM_EABI_VERSION (in_flags),
19696 EF_ARM_EABI_VERSION (out_flags)))
19697 {
19698 _bfd_error_handler
19699 (_("error: Source object %B has EABI version %d, but target %B has EABI version %d"),
19700 ibfd, obfd,
19701 (in_flags & EF_ARM_EABIMASK) >> 24,
19702 (out_flags & EF_ARM_EABIMASK) >> 24);
19703 return FALSE;
19704 }
19705
19706 /* Not sure what needs to be checked for EABI versions >= 1. */
19707 /* VxWorks libraries do not use these flags. */
19708 if (get_elf_backend_data (obfd) != &elf32_arm_vxworks_bed
19709 && get_elf_backend_data (ibfd) != &elf32_arm_vxworks_bed
19710 && EF_ARM_EABI_VERSION (in_flags) == EF_ARM_EABI_UNKNOWN)
19711 {
19712 if ((in_flags & EF_ARM_APCS_26) != (out_flags & EF_ARM_APCS_26))
19713 {
19714 _bfd_error_handler
19715 (_("error: %B is compiled for APCS-%d, whereas target %B uses APCS-%d"),
19716 ibfd, obfd,
19717 in_flags & EF_ARM_APCS_26 ? 26 : 32,
19718 out_flags & EF_ARM_APCS_26 ? 26 : 32);
19719 flags_compatible = FALSE;
19720 }
19721
19722 if ((in_flags & EF_ARM_APCS_FLOAT) != (out_flags & EF_ARM_APCS_FLOAT))
19723 {
19724 if (in_flags & EF_ARM_APCS_FLOAT)
19725 _bfd_error_handler
19726 (_("error: %B passes floats in float registers, whereas %B passes them in integer registers"),
19727 ibfd, obfd);
19728 else
19729 _bfd_error_handler
19730 (_("error: %B passes floats in integer registers, whereas %B passes them in float registers"),
19731 ibfd, obfd);
19732
19733 flags_compatible = FALSE;
19734 }
19735
19736 if ((in_flags & EF_ARM_VFP_FLOAT) != (out_flags & EF_ARM_VFP_FLOAT))
19737 {
19738 if (in_flags & EF_ARM_VFP_FLOAT)
19739 _bfd_error_handler
19740 (_("error: %B uses VFP instructions, whereas %B does not"),
19741 ibfd, obfd);
19742 else
19743 _bfd_error_handler
19744 (_("error: %B uses FPA instructions, whereas %B does not"),
19745 ibfd, obfd);
19746
19747 flags_compatible = FALSE;
19748 }
19749
19750 if ((in_flags & EF_ARM_MAVERICK_FLOAT) != (out_flags & EF_ARM_MAVERICK_FLOAT))
19751 {
19752 if (in_flags & EF_ARM_MAVERICK_FLOAT)
19753 _bfd_error_handler
19754 (_("error: %B uses Maverick instructions, whereas %B does not"),
19755 ibfd, obfd);
19756 else
19757 _bfd_error_handler
19758 (_("error: %B does not use Maverick instructions, whereas %B does"),
19759 ibfd, obfd);
19760
19761 flags_compatible = FALSE;
19762 }
19763
19764#ifdef EF_ARM_SOFT_FLOAT
19765 if ((in_flags & EF_ARM_SOFT_FLOAT) != (out_flags & EF_ARM_SOFT_FLOAT))
19766 {
19767 /* We can allow interworking between code that is VFP format
19768 layout, and uses either soft float or integer regs for
19769 passing floating point arguments and results. We already
19770 know that the APCS_FLOAT flags match; similarly for VFP
19771 flags. */
19772 if ((in_flags & EF_ARM_APCS_FLOAT) != 0
19773 || (in_flags & EF_ARM_VFP_FLOAT) == 0)
19774 {
19775 if (in_flags & EF_ARM_SOFT_FLOAT)
19776 _bfd_error_handler
19777 (_("error: %B uses software FP, whereas %B uses hardware FP"),
19778 ibfd, obfd);
19779 else
19780 _bfd_error_handler
19781 (_("error: %B uses hardware FP, whereas %B uses software FP"),
19782 ibfd, obfd);
19783
19784 flags_compatible = FALSE;
19785 }
19786 }
19787#endif
19788
19789 /* Interworking mismatch is only a warning. */
19790 if ((in_flags & EF_ARM_INTERWORK) != (out_flags & EF_ARM_INTERWORK))
19791 {
19792 if (in_flags & EF_ARM_INTERWORK)
19793 {
19794 _bfd_error_handler
19795 (_("Warning: %B supports interworking, whereas %B does not"),
19796 ibfd, obfd);
19797 }
19798 else
19799 {
19800 _bfd_error_handler
19801 (_("Warning: %B does not support interworking, whereas %B does"),
19802 ibfd, obfd);
19803 }
19804 }
19805 }
19806
19807 return flags_compatible;
19808}
19809
19810
906e58ca 19811/* Symbian OS Targets. */
7f266840 19812
906e58ca 19813#undef TARGET_LITTLE_SYM
6d00b590 19814#define TARGET_LITTLE_SYM arm_elf32_symbian_le_vec
906e58ca 19815#undef TARGET_LITTLE_NAME
7f266840 19816#define TARGET_LITTLE_NAME "elf32-littlearm-symbian"
906e58ca 19817#undef TARGET_BIG_SYM
6d00b590 19818#define TARGET_BIG_SYM arm_elf32_symbian_be_vec
906e58ca 19819#undef TARGET_BIG_NAME
7f266840
DJ		 19820#define TARGET_BIG_NAME "elf32-bigarm-symbian"
19821
19822/* Like elf32_arm_link_hash_table_create -- but overrides
19823 appropriately for Symbian OS. */
906e58ca 19824
7f266840
DJ		 19825static struct bfd_link_hash_table *
19826elf32_arm_symbian_link_hash_table_create (bfd *abfd)
19827{
19828 struct bfd_link_hash_table *ret;
19829
19830 ret = elf32_arm_link_hash_table_create (abfd);
19831 if (ret)
19832 {
19833 struct elf32_arm_link_hash_table *htab
19834 = (struct elf32_arm_link_hash_table *)ret;
19835 /* There is no PLT header for Symbian OS. */
19836 htab->plt_header_size = 0;
95720a86
DJ		 19837 /* The PLT entries are each one instruction and one word. */
19838 htab->plt_entry_size = 4 * ARRAY_SIZE (elf32_arm_symbian_plt_entry);
7f266840 19839 htab->symbian_p = 1;
33bfe774
JB		 19840 /* Symbian uses armv5t or above, so use_blx is always true. */
19841 htab->use_blx = 1;
67687978 19842 htab->root.is_relocatable_executable = 1;
7f266840
DJ		 19843 }
19844 return ret;
906e58ca 19845}
7f266840 19846
b35d266b 19847static const struct bfd_elf_special_section
551b43fd 19848elf32_arm_symbian_special_sections[] =
7f266840 19849{
5cd3778d
MM		 19850 /* In a BPABI executable, the dynamic linking sections do not go in
19851 the loadable read-only segment. The post-linker may wish to
19852 refer to these sections, but they are not part of the final
19853 program image. */
0112cd26
NC		 19854 { STRING_COMMA_LEN (".dynamic"), 0, SHT_DYNAMIC, 0 },
19855 { STRING_COMMA_LEN (".dynstr"), 0, SHT_STRTAB, 0 },
19856 { STRING_COMMA_LEN (".dynsym"), 0, SHT_DYNSYM, 0 },
19857 { STRING_COMMA_LEN (".got"), 0, SHT_PROGBITS, 0 },
19858 { STRING_COMMA_LEN (".hash"), 0, SHT_HASH, 0 },
5cd3778d
MM		 19859 /* These sections do not need to be writable as the SymbianOS
19860 postlinker will arrange things so that no dynamic relocation is
19861 required. */
0112cd26
NC		 19862 { STRING_COMMA_LEN (".init_array"), 0, SHT_INIT_ARRAY, SHF_ALLOC },
19863 { STRING_COMMA_LEN (".fini_array"), 0, SHT_FINI_ARRAY, SHF_ALLOC },
19864 { STRING_COMMA_LEN (".preinit_array"), 0, SHT_PREINIT_ARRAY, SHF_ALLOC },
19865 { NULL, 0, 0, 0, 0 }
7f266840
DJ		 19866};
19867
c3c76620 19868static void
906e58ca 19869elf32_arm_symbian_begin_write_processing (bfd *abfd,
a4fd1a8e 19870 struct bfd_link_info *link_info)
c3c76620
MM		 19871{
19872 /* BPABI objects are never loaded directly by an OS kernel; they are
19873 processed by a postlinker first, into an OS-specific format. If
19874 the D_PAGED bit is set on the file, BFD will align segments on
19875 page boundaries, so that an OS can directly map the file. With
19876 BPABI objects, that just results in wasted space. In addition,
19877 because we clear the D_PAGED bit, map_sections_to_segments will
19878 recognize that the program headers should not be mapped into any
19879 loadable segment. */
19880 abfd->flags &= ~D_PAGED;
906e58ca 19881 elf32_arm_begin_write_processing (abfd, link_info);
c3c76620 19882}
7f266840
DJ		 19883
19884static bfd_boolean
906e58ca 19885elf32_arm_symbian_modify_segment_map (bfd *abfd,
b294bdf8 19886 struct bfd_link_info *info)
7f266840
DJ		 19887{
19888 struct elf_segment_map *m;
19889 asection *dynsec;
19890
7f266840
DJ		 19891 /* BPABI shared libraries and executables should have a PT_DYNAMIC
19892 segment. However, because the .dynamic section is not marked
19893 with SEC_LOAD, the generic ELF code will not create such a
19894 segment. */
19895 dynsec = bfd_get_section_by_name (abfd, ".dynamic");
19896 if (dynsec)
19897 {
12bd6957 19898 for (m = elf_seg_map (abfd); m != NULL; m = m->next)
8ded5a0f
AM		 19899 if (m->p_type == PT_DYNAMIC)
19900 break;
19901
19902 if (m == NULL)
19903 {
19904 m = _bfd_elf_make_dynamic_segment (abfd, dynsec);
12bd6957
AM		 19905 m->next = elf_seg_map (abfd);
19906 elf_seg_map (abfd) = m;
8ded5a0f 19907 }
7f266840
DJ		 19908 }
19909
b294bdf8
MM		 19910 /* Also call the generic arm routine. */
19911 return elf32_arm_modify_segment_map (abfd, info);
7f266840
DJ		 19912}
19913
95720a86
DJ		 19914/* Return address for Ith PLT stub in section PLT, for relocation REL
19915 or (bfd_vma) -1 if it should not be included. */
19916
19917static bfd_vma
19918elf32_arm_symbian_plt_sym_val (bfd_vma i, const asection *plt,
19919 const arelent *rel ATTRIBUTE_UNUSED)
19920{
19921 return plt->vma + 4 * ARRAY_SIZE (elf32_arm_symbian_plt_entry) * i;
19922}
19923
8029a119 19924#undef elf32_bed
7f266840
DJ		 19925#define elf32_bed elf32_arm_symbian_bed
19926
19927/* The dynamic sections are not allocated on SymbianOS; the postlinker
19928 will process them and then discard them. */
906e58ca 19929#undef ELF_DYNAMIC_SEC_FLAGS
7f266840
DJ		 19930#define ELF_DYNAMIC_SEC_FLAGS \
19931 (SEC_HAS_CONTENTS | SEC_IN_MEMORY | SEC_LINKER_CREATED)
19932
9eaff861 19933#undef elf_backend_emit_relocs
c3c76620 19934
906e58ca
NC		 19935#undef bfd_elf32_bfd_link_hash_table_create
19936#define bfd_elf32_bfd_link_hash_table_create elf32_arm_symbian_link_hash_table_create
19937#undef elf_backend_special_sections
19938#define elf_backend_special_sections elf32_arm_symbian_special_sections
19939#undef elf_backend_begin_write_processing
19940#define elf_backend_begin_write_processing elf32_arm_symbian_begin_write_processing
19941#undef elf_backend_final_write_processing
19942#define elf_backend_final_write_processing elf32_arm_final_write_processing
19943
19944#undef elf_backend_modify_segment_map
7f266840
DJ		 19945#define elf_backend_modify_segment_map elf32_arm_symbian_modify_segment_map
19946
19947/* There is no .got section for BPABI objects, and hence no header. */
906e58ca 19948#undef elf_backend_got_header_size
7f266840
DJ		 19949#define elf_backend_got_header_size 0
19950
19951/* Similarly, there is no .got.plt section. */
906e58ca 19952#undef elf_backend_want_got_plt
7f266840
DJ		 19953#define elf_backend_want_got_plt 0
19954
906e58ca 19955#undef elf_backend_plt_sym_val
95720a86
DJ		 19956#define elf_backend_plt_sym_val elf32_arm_symbian_plt_sym_val
19957
906e58ca 19958#undef elf_backend_may_use_rel_p
00a97672 19959#define elf_backend_may_use_rel_p 1
906e58ca 19960#undef elf_backend_may_use_rela_p
00a97672 19961#define elf_backend_may_use_rela_p 0
906e58ca 19962#undef elf_backend_default_use_rela_p
00a97672 19963#define elf_backend_default_use_rela_p 0
906e58ca 19964#undef elf_backend_want_plt_sym
00a97672 19965#define elf_backend_want_plt_sym 0
64f52338
AM		 19966#undef elf_backend_dtrel_excludes_plt
19967#define elf_backend_dtrel_excludes_plt 0
906e58ca 19968#undef ELF_MAXPAGESIZE
00a97672 19969#define ELF_MAXPAGESIZE 0x8000
4e7fd91e 19970
7f266840 19971#include "elf32-target.h"
GDB Binutils - Deliverables
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