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Fix regression introduced in "break *<EXPR>" by explicit location patches.
[deliverable/binutils-gdb.git] / bfd / elf32-arm.c
CommitLineData
252b5132 1/* 32-bit ELF support for ARM
6f2750fe 2 Copyright (C) 1998-2016 Free Software Foundation, Inc.
252b5132
RH		 3
4 This file is part of BFD, the Binary File Descriptor library.
5
6 This program is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
cd123cb7 8 the Free Software Foundation; either version 3 of the License, or
252b5132
RH		 9 (at your option) any later version.
10
11 This program is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
15
16 You should have received a copy of the GNU General Public License
17 along with this program; if not, write to the Free Software
cd123cb7
NC		 18 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
19 MA 02110-1301, USA. */
252b5132 20
6e6718a3 21#include "sysdep.h"
2468f9c9
PB		 22#include <limits.h>
23
3db64b00 24#include "bfd.h"
6034aab8 25#include "bfd_stdint.h"
00a97672 26#include "libiberty.h"
7f266840
DJ		 27#include "libbfd.h"
28#include "elf-bfd.h"
b38cadfb 29#include "elf-nacl.h"
00a97672 30#include "elf-vxworks.h"
ee065d83 31#include "elf/arm.h"
7f266840 32
00a97672
RS		 33/* Return the relocation section associated with NAME. HTAB is the
34 bfd's elf32_arm_link_hash_entry. */
35#define RELOC_SECTION(HTAB, NAME) \
36 ((HTAB)->use_rel ? ".rel" NAME : ".rela" NAME)
37
38/* Return size of a relocation entry. HTAB is the bfd's
39 elf32_arm_link_hash_entry. */
40#define RELOC_SIZE(HTAB) \
41 ((HTAB)->use_rel \
42 ? sizeof (Elf32_External_Rel) \
43 : sizeof (Elf32_External_Rela))
44
45/* Return function to swap relocations in. HTAB is the bfd's
46 elf32_arm_link_hash_entry. */
47#define SWAP_RELOC_IN(HTAB) \
48 ((HTAB)->use_rel \
49 ? bfd_elf32_swap_reloc_in \
50 : bfd_elf32_swap_reloca_in)
51
52/* Return function to swap relocations out. HTAB is the bfd's
53 elf32_arm_link_hash_entry. */
54#define SWAP_RELOC_OUT(HTAB) \
55 ((HTAB)->use_rel \
56 ? bfd_elf32_swap_reloc_out \
57 : bfd_elf32_swap_reloca_out)
58
7f266840
DJ		 59#define elf_info_to_howto 0
60#define elf_info_to_howto_rel elf32_arm_info_to_howto
61
62#define ARM_ELF_ABI_VERSION 0
63#define ARM_ELF_OS_ABI_VERSION ELFOSABI_ARM
64
79f08007
YZ		 65/* The Adjusted Place, as defined by AAELF. */
66#define Pa(X) ((X) & 0xfffffffc)
67
3e6b1042
DJ		 68static bfd_boolean elf32_arm_write_section (bfd *output_bfd,
69 struct bfd_link_info *link_info,
70 asection *sec,
71 bfd_byte *contents);
72
7f266840
DJ		 73/* Note: code such as elf32_arm_reloc_type_lookup expect to use e.g.
74 R_ARM_PC24 as an index into this, and find the R_ARM_PC24 HOWTO
75 in that slot. */
76
c19d1205 77static reloc_howto_type elf32_arm_howto_table_1[] =
7f266840 78{
8029a119 79 /* No relocation. */
7f266840
DJ		 80 HOWTO (R_ARM_NONE, /* type */
81 0, /* rightshift */
6346d5ca 82 3, /* size (0 = byte, 1 = short, 2 = long) */
7f266840
DJ		 83 0, /* bitsize */
84 FALSE, /* pc_relative */
85 0, /* bitpos */
86 complain_overflow_dont,/* complain_on_overflow */
87 bfd_elf_generic_reloc, /* special_function */
88 "R_ARM_NONE", /* name */
89 FALSE, /* partial_inplace */
90 0, /* src_mask */
91 0, /* dst_mask */
92 FALSE), /* pcrel_offset */
93
94 HOWTO (R_ARM_PC24, /* type */
95 2, /* rightshift */
96 2, /* size (0 = byte, 1 = short, 2 = long) */
97 24, /* bitsize */
98 TRUE, /* pc_relative */
99 0, /* bitpos */
100 complain_overflow_signed,/* complain_on_overflow */
101 bfd_elf_generic_reloc, /* special_function */
102 "R_ARM_PC24", /* name */
103 FALSE, /* partial_inplace */
104 0x00ffffff, /* src_mask */
105 0x00ffffff, /* dst_mask */
106 TRUE), /* pcrel_offset */
107
108 /* 32 bit absolute */
109 HOWTO (R_ARM_ABS32, /* type */
110 0, /* rightshift */
111 2, /* size (0 = byte, 1 = short, 2 = long) */
112 32, /* bitsize */
113 FALSE, /* pc_relative */
114 0, /* bitpos */
115 complain_overflow_bitfield,/* complain_on_overflow */
116 bfd_elf_generic_reloc, /* special_function */
117 "R_ARM_ABS32", /* name */
118 FALSE, /* partial_inplace */
119 0xffffffff, /* src_mask */
120 0xffffffff, /* dst_mask */
121 FALSE), /* pcrel_offset */
122
123 /* standard 32bit pc-relative reloc */
124 HOWTO (R_ARM_REL32, /* type */
125 0, /* rightshift */
126 2, /* size (0 = byte, 1 = short, 2 = long) */
127 32, /* bitsize */
128 TRUE, /* pc_relative */
129 0, /* bitpos */
130 complain_overflow_bitfield,/* complain_on_overflow */
131 bfd_elf_generic_reloc, /* special_function */
132 "R_ARM_REL32", /* name */
133 FALSE, /* partial_inplace */
134 0xffffffff, /* src_mask */
135 0xffffffff, /* dst_mask */
136 TRUE), /* pcrel_offset */
137
c19d1205 138 /* 8 bit absolute - R_ARM_LDR_PC_G0 in AAELF */
4962c51a 139 HOWTO (R_ARM_LDR_PC_G0, /* type */
7f266840
DJ		 140 0, /* rightshift */
141 0, /* size (0 = byte, 1 = short, 2 = long) */
4962c51a
MS		 142 32, /* bitsize */
143 TRUE, /* pc_relative */
7f266840 144 0, /* bitpos */
4962c51a 145 complain_overflow_dont,/* complain_on_overflow */
7f266840 146 bfd_elf_generic_reloc, /* special_function */
4962c51a 147 "R_ARM_LDR_PC_G0", /* name */
7f266840 148 FALSE, /* partial_inplace */
4962c51a
MS		 149 0xffffffff, /* src_mask */
150 0xffffffff, /* dst_mask */
151 TRUE), /* pcrel_offset */
7f266840
DJ		 152
153 /* 16 bit absolute */
154 HOWTO (R_ARM_ABS16, /* type */
155 0, /* rightshift */
156 1, /* size (0 = byte, 1 = short, 2 = long) */
157 16, /* bitsize */
158 FALSE, /* pc_relative */
159 0, /* bitpos */
160 complain_overflow_bitfield,/* complain_on_overflow */
161 bfd_elf_generic_reloc, /* special_function */
162 "R_ARM_ABS16", /* name */
163 FALSE, /* partial_inplace */
164 0x0000ffff, /* src_mask */
165 0x0000ffff, /* dst_mask */
166 FALSE), /* pcrel_offset */
167
168 /* 12 bit absolute */
169 HOWTO (R_ARM_ABS12, /* type */
170 0, /* rightshift */
171 2, /* size (0 = byte, 1 = short, 2 = long) */
172 12, /* bitsize */
173 FALSE, /* pc_relative */
174 0, /* bitpos */
175 complain_overflow_bitfield,/* complain_on_overflow */
176 bfd_elf_generic_reloc, /* special_function */
177 "R_ARM_ABS12", /* name */
178 FALSE, /* partial_inplace */
00a97672
RS		 179 0x00000fff, /* src_mask */
180 0x00000fff, /* dst_mask */
7f266840
DJ		 181 FALSE), /* pcrel_offset */
182
183 HOWTO (R_ARM_THM_ABS5, /* type */
184 6, /* rightshift */
185 1, /* size (0 = byte, 1 = short, 2 = long) */
186 5, /* bitsize */
187 FALSE, /* pc_relative */
188 0, /* bitpos */
189 complain_overflow_bitfield,/* complain_on_overflow */
190 bfd_elf_generic_reloc, /* special_function */
191 "R_ARM_THM_ABS5", /* name */
192 FALSE, /* partial_inplace */
193 0x000007e0, /* src_mask */
194 0x000007e0, /* dst_mask */
195 FALSE), /* pcrel_offset */
196
197 /* 8 bit absolute */
198 HOWTO (R_ARM_ABS8, /* type */
199 0, /* rightshift */
200 0, /* size (0 = byte, 1 = short, 2 = long) */
201 8, /* bitsize */
202 FALSE, /* pc_relative */
203 0, /* bitpos */
204 complain_overflow_bitfield,/* complain_on_overflow */
205 bfd_elf_generic_reloc, /* special_function */
206 "R_ARM_ABS8", /* name */
207 FALSE, /* partial_inplace */
208 0x000000ff, /* src_mask */
209 0x000000ff, /* dst_mask */
210 FALSE), /* pcrel_offset */
211
212 HOWTO (R_ARM_SBREL32, /* type */
213 0, /* rightshift */
214 2, /* size (0 = byte, 1 = short, 2 = long) */
215 32, /* bitsize */
216 FALSE, /* pc_relative */
217 0, /* bitpos */
218 complain_overflow_dont,/* complain_on_overflow */
219 bfd_elf_generic_reloc, /* special_function */
220 "R_ARM_SBREL32", /* name */
221 FALSE, /* partial_inplace */
222 0xffffffff, /* src_mask */
223 0xffffffff, /* dst_mask */
224 FALSE), /* pcrel_offset */
225
c19d1205 226 HOWTO (R_ARM_THM_CALL, /* type */
7f266840
DJ		 227 1, /* rightshift */
228 2, /* size (0 = byte, 1 = short, 2 = long) */
f6ebfac0 229 24, /* bitsize */
7f266840
DJ		 230 TRUE, /* pc_relative */
231 0, /* bitpos */
232 complain_overflow_signed,/* complain_on_overflow */
233 bfd_elf_generic_reloc, /* special_function */
c19d1205 234 "R_ARM_THM_CALL", /* name */
7f266840 235 FALSE, /* partial_inplace */
7f6ab9f8
AM		 236 0x07ff2fff, /* src_mask */
237 0x07ff2fff, /* dst_mask */
7f266840
DJ		 238 TRUE), /* pcrel_offset */
239
240 HOWTO (R_ARM_THM_PC8, /* type */
241 1, /* rightshift */
242 1, /* size (0 = byte, 1 = short, 2 = long) */
243 8, /* bitsize */
244 TRUE, /* pc_relative */
245 0, /* bitpos */
246 complain_overflow_signed,/* complain_on_overflow */
247 bfd_elf_generic_reloc, /* special_function */
248 "R_ARM_THM_PC8", /* name */
249 FALSE, /* partial_inplace */
250 0x000000ff, /* src_mask */
251 0x000000ff, /* dst_mask */
252 TRUE), /* pcrel_offset */
253
c19d1205 254 HOWTO (R_ARM_BREL_ADJ, /* type */
7f266840
DJ		 255 1, /* rightshift */
256 1, /* size (0 = byte, 1 = short, 2 = long) */
c19d1205
ZW		 257 32, /* bitsize */
258 FALSE, /* pc_relative */
7f266840
DJ		 259 0, /* bitpos */
260 complain_overflow_signed,/* complain_on_overflow */
261 bfd_elf_generic_reloc, /* special_function */
c19d1205 262 "R_ARM_BREL_ADJ", /* name */
7f266840 263 FALSE, /* partial_inplace */
c19d1205
ZW		 264 0xffffffff, /* src_mask */
265 0xffffffff, /* dst_mask */
266 FALSE), /* pcrel_offset */
7f266840 267
0855e32b 268 HOWTO (R_ARM_TLS_DESC, /* type */
7f266840 269 0, /* rightshift */
0855e32b
NS		 270 2, /* size (0 = byte, 1 = short, 2 = long) */
271 32, /* bitsize */
7f266840
DJ		 272 FALSE, /* pc_relative */
273 0, /* bitpos */
0855e32b 274 complain_overflow_bitfield,/* complain_on_overflow */
7f266840 275 bfd_elf_generic_reloc, /* special_function */
0855e32b 276 "R_ARM_TLS_DESC", /* name */
7f266840 277 FALSE, /* partial_inplace */
0855e32b
NS		 278 0xffffffff, /* src_mask */
279 0xffffffff, /* dst_mask */
7f266840
DJ		 280 FALSE), /* pcrel_offset */
281
282 HOWTO (R_ARM_THM_SWI8, /* type */
283 0, /* rightshift */
284 0, /* size (0 = byte, 1 = short, 2 = long) */
285 0, /* bitsize */
286 FALSE, /* pc_relative */
287 0, /* bitpos */
288 complain_overflow_signed,/* complain_on_overflow */
289 bfd_elf_generic_reloc, /* special_function */
290 "R_ARM_SWI8", /* name */
291 FALSE, /* partial_inplace */
292 0x00000000, /* src_mask */
293 0x00000000, /* dst_mask */
294 FALSE), /* pcrel_offset */
295
296 /* BLX instruction for the ARM. */
297 HOWTO (R_ARM_XPC25, /* type */
298 2, /* rightshift */
299 2, /* size (0 = byte, 1 = short, 2 = long) */
7f6ab9f8 300 24, /* bitsize */
7f266840
DJ		 301 TRUE, /* pc_relative */
302 0, /* bitpos */
303 complain_overflow_signed,/* complain_on_overflow */
304 bfd_elf_generic_reloc, /* special_function */
305 "R_ARM_XPC25", /* name */
306 FALSE, /* partial_inplace */
307 0x00ffffff, /* src_mask */
308 0x00ffffff, /* dst_mask */
309 TRUE), /* pcrel_offset */
310
311 /* BLX instruction for the Thumb. */
312 HOWTO (R_ARM_THM_XPC22, /* type */
313 2, /* rightshift */
314 2, /* size (0 = byte, 1 = short, 2 = long) */
7f6ab9f8 315 24, /* bitsize */
7f266840
DJ		 316 TRUE, /* pc_relative */
317 0, /* bitpos */
318 complain_overflow_signed,/* complain_on_overflow */
319 bfd_elf_generic_reloc, /* special_function */
320 "R_ARM_THM_XPC22", /* name */
321 FALSE, /* partial_inplace */
7f6ab9f8
AM		 322 0x07ff2fff, /* src_mask */
323 0x07ff2fff, /* dst_mask */
7f266840
DJ		 324 TRUE), /* pcrel_offset */
325
ba93b8ac 326 /* Dynamic TLS relocations. */
7f266840 327
ba93b8ac 328 HOWTO (R_ARM_TLS_DTPMOD32, /* type */
99059e56
RM		 329 0, /* rightshift */
330 2, /* size (0 = byte, 1 = short, 2 = long) */
331 32, /* bitsize */
332 FALSE, /* pc_relative */
333 0, /* bitpos */
334 complain_overflow_bitfield,/* complain_on_overflow */
335 bfd_elf_generic_reloc, /* special_function */
336 "R_ARM_TLS_DTPMOD32", /* name */
337 TRUE, /* partial_inplace */
338 0xffffffff, /* src_mask */
339 0xffffffff, /* dst_mask */
340 FALSE), /* pcrel_offset */
7f266840 341
ba93b8ac 342 HOWTO (R_ARM_TLS_DTPOFF32, /* type */
99059e56
RM		 343 0, /* rightshift */
344 2, /* size (0 = byte, 1 = short, 2 = long) */
345 32, /* bitsize */
346 FALSE, /* pc_relative */
347 0, /* bitpos */
348 complain_overflow_bitfield,/* complain_on_overflow */
349 bfd_elf_generic_reloc, /* special_function */
350 "R_ARM_TLS_DTPOFF32", /* name */
351 TRUE, /* partial_inplace */
352 0xffffffff, /* src_mask */
353 0xffffffff, /* dst_mask */
354 FALSE), /* pcrel_offset */
7f266840 355
ba93b8ac 356 HOWTO (R_ARM_TLS_TPOFF32, /* type */
99059e56
RM		 357 0, /* rightshift */
358 2, /* size (0 = byte, 1 = short, 2 = long) */
359 32, /* bitsize */
360 FALSE, /* pc_relative */
361 0, /* bitpos */
362 complain_overflow_bitfield,/* complain_on_overflow */
363 bfd_elf_generic_reloc, /* special_function */
364 "R_ARM_TLS_TPOFF32", /* name */
365 TRUE, /* partial_inplace */
366 0xffffffff, /* src_mask */
367 0xffffffff, /* dst_mask */
368 FALSE), /* pcrel_offset */
7f266840
DJ		 369
370 /* Relocs used in ARM Linux */
371
372 HOWTO (R_ARM_COPY, /* type */
99059e56
RM		 373 0, /* rightshift */
374 2, /* size (0 = byte, 1 = short, 2 = long) */
375 32, /* bitsize */
376 FALSE, /* pc_relative */
377 0, /* bitpos */
378 complain_overflow_bitfield,/* complain_on_overflow */
379 bfd_elf_generic_reloc, /* special_function */
380 "R_ARM_COPY", /* name */
381 TRUE, /* partial_inplace */
382 0xffffffff, /* src_mask */
383 0xffffffff, /* dst_mask */
384 FALSE), /* pcrel_offset */
7f266840
DJ		 385
386 HOWTO (R_ARM_GLOB_DAT, /* type */
99059e56
RM		 387 0, /* rightshift */
388 2, /* size (0 = byte, 1 = short, 2 = long) */
389 32, /* bitsize */
390 FALSE, /* pc_relative */
391 0, /* bitpos */
392 complain_overflow_bitfield,/* complain_on_overflow */
393 bfd_elf_generic_reloc, /* special_function */
394 "R_ARM_GLOB_DAT", /* name */
395 TRUE, /* partial_inplace */
396 0xffffffff, /* src_mask */
397 0xffffffff, /* dst_mask */
398 FALSE), /* pcrel_offset */
7f266840
DJ		 399
400 HOWTO (R_ARM_JUMP_SLOT, /* type */
99059e56
RM		 401 0, /* rightshift */
402 2, /* size (0 = byte, 1 = short, 2 = long) */
403 32, /* bitsize */
404 FALSE, /* pc_relative */
405 0, /* bitpos */
406 complain_overflow_bitfield,/* complain_on_overflow */
407 bfd_elf_generic_reloc, /* special_function */
408 "R_ARM_JUMP_SLOT", /* name */
409 TRUE, /* partial_inplace */
410 0xffffffff, /* src_mask */
411 0xffffffff, /* dst_mask */
412 FALSE), /* pcrel_offset */
7f266840
DJ		 413
414 HOWTO (R_ARM_RELATIVE, /* type */
99059e56
RM		 415 0, /* rightshift */
416 2, /* size (0 = byte, 1 = short, 2 = long) */
417 32, /* bitsize */
418 FALSE, /* pc_relative */
419 0, /* bitpos */
420 complain_overflow_bitfield,/* complain_on_overflow */
421 bfd_elf_generic_reloc, /* special_function */
422 "R_ARM_RELATIVE", /* name */
423 TRUE, /* partial_inplace */
424 0xffffffff, /* src_mask */
425 0xffffffff, /* dst_mask */
426 FALSE), /* pcrel_offset */
7f266840 427
c19d1205 428 HOWTO (R_ARM_GOTOFF32, /* type */
99059e56
RM		 429 0, /* rightshift */
430 2, /* size (0 = byte, 1 = short, 2 = long) */
431 32, /* bitsize */
432 FALSE, /* pc_relative */
433 0, /* bitpos */
434 complain_overflow_bitfield,/* complain_on_overflow */
435 bfd_elf_generic_reloc, /* special_function */
436 "R_ARM_GOTOFF32", /* name */
437 TRUE, /* partial_inplace */
438 0xffffffff, /* src_mask */
439 0xffffffff, /* dst_mask */
440 FALSE), /* pcrel_offset */
7f266840
DJ		 441
442 HOWTO (R_ARM_GOTPC, /* type */
99059e56
RM		 443 0, /* rightshift */
444 2, /* size (0 = byte, 1 = short, 2 = long) */
445 32, /* bitsize */
446 TRUE, /* pc_relative */
447 0, /* bitpos */
448 complain_overflow_bitfield,/* complain_on_overflow */
449 bfd_elf_generic_reloc, /* special_function */
450 "R_ARM_GOTPC", /* name */
451 TRUE, /* partial_inplace */
452 0xffffffff, /* src_mask */
453 0xffffffff, /* dst_mask */
454 TRUE), /* pcrel_offset */
7f266840
DJ		 455
456 HOWTO (R_ARM_GOT32, /* type */
99059e56
RM		 457 0, /* rightshift */
458 2, /* size (0 = byte, 1 = short, 2 = long) */
459 32, /* bitsize */
460 FALSE, /* pc_relative */
461 0, /* bitpos */
462 complain_overflow_bitfield,/* complain_on_overflow */
463 bfd_elf_generic_reloc, /* special_function */
464 "R_ARM_GOT32", /* name */
465 TRUE, /* partial_inplace */
466 0xffffffff, /* src_mask */
467 0xffffffff, /* dst_mask */
468 FALSE), /* pcrel_offset */
7f266840
DJ		 469
470 HOWTO (R_ARM_PLT32, /* type */
99059e56
RM		 471 2, /* rightshift */
472 2, /* size (0 = byte, 1 = short, 2 = long) */
473 24, /* bitsize */
474 TRUE, /* pc_relative */
475 0, /* bitpos */
476 complain_overflow_bitfield,/* complain_on_overflow */
477 bfd_elf_generic_reloc, /* special_function */
478 "R_ARM_PLT32", /* name */
479 FALSE, /* partial_inplace */
480 0x00ffffff, /* src_mask */
481 0x00ffffff, /* dst_mask */
482 TRUE), /* pcrel_offset */
7f266840
DJ		 483
484 HOWTO (R_ARM_CALL, /* type */
485 2, /* rightshift */
486 2, /* size (0 = byte, 1 = short, 2 = long) */
487 24, /* bitsize */
488 TRUE, /* pc_relative */
489 0, /* bitpos */
490 complain_overflow_signed,/* complain_on_overflow */
491 bfd_elf_generic_reloc, /* special_function */
492 "R_ARM_CALL", /* name */
493 FALSE, /* partial_inplace */
494 0x00ffffff, /* src_mask */
495 0x00ffffff, /* dst_mask */
496 TRUE), /* pcrel_offset */
497
498 HOWTO (R_ARM_JUMP24, /* type */
499 2, /* rightshift */
500 2, /* size (0 = byte, 1 = short, 2 = long) */
501 24, /* bitsize */
502 TRUE, /* pc_relative */
503 0, /* bitpos */
504 complain_overflow_signed,/* complain_on_overflow */
505 bfd_elf_generic_reloc, /* special_function */
506 "R_ARM_JUMP24", /* name */
507 FALSE, /* partial_inplace */
508 0x00ffffff, /* src_mask */
509 0x00ffffff, /* dst_mask */
510 TRUE), /* pcrel_offset */
511
c19d1205
ZW		 512 HOWTO (R_ARM_THM_JUMP24, /* type */
513 1, /* rightshift */
514 2, /* size (0 = byte, 1 = short, 2 = long) */
515 24, /* bitsize */
516 TRUE, /* pc_relative */
7f266840 517 0, /* bitpos */
c19d1205 518 complain_overflow_signed,/* complain_on_overflow */
7f266840 519 bfd_elf_generic_reloc, /* special_function */
c19d1205 520 "R_ARM_THM_JUMP24", /* name */
7f266840 521 FALSE, /* partial_inplace */
c19d1205
ZW		 522 0x07ff2fff, /* src_mask */
523 0x07ff2fff, /* dst_mask */
524 TRUE), /* pcrel_offset */
7f266840 525
c19d1205 526 HOWTO (R_ARM_BASE_ABS, /* type */
7f266840 527 0, /* rightshift */
c19d1205
ZW		 528 2, /* size (0 = byte, 1 = short, 2 = long) */
529 32, /* bitsize */
7f266840
DJ		 530 FALSE, /* pc_relative */
531 0, /* bitpos */
532 complain_overflow_dont,/* complain_on_overflow */
533 bfd_elf_generic_reloc, /* special_function */
c19d1205 534 "R_ARM_BASE_ABS", /* name */
7f266840 535 FALSE, /* partial_inplace */
c19d1205
ZW		 536 0xffffffff, /* src_mask */
537 0xffffffff, /* dst_mask */
7f266840
DJ		 538 FALSE), /* pcrel_offset */
539
540 HOWTO (R_ARM_ALU_PCREL7_0, /* type */
541 0, /* rightshift */
542 2, /* size (0 = byte, 1 = short, 2 = long) */
543 12, /* bitsize */
544 TRUE, /* pc_relative */
545 0, /* bitpos */
546 complain_overflow_dont,/* complain_on_overflow */
547 bfd_elf_generic_reloc, /* special_function */
548 "R_ARM_ALU_PCREL_7_0", /* name */
549 FALSE, /* partial_inplace */
550 0x00000fff, /* src_mask */
551 0x00000fff, /* dst_mask */
552 TRUE), /* pcrel_offset */
553
554 HOWTO (R_ARM_ALU_PCREL15_8, /* type */
555 0, /* rightshift */
556 2, /* size (0 = byte, 1 = short, 2 = long) */
557 12, /* bitsize */
558 TRUE, /* pc_relative */
559 8, /* bitpos */
560 complain_overflow_dont,/* complain_on_overflow */
561 bfd_elf_generic_reloc, /* special_function */
562 "R_ARM_ALU_PCREL_15_8",/* name */
563 FALSE, /* partial_inplace */
564 0x00000fff, /* src_mask */
565 0x00000fff, /* dst_mask */
566 TRUE), /* pcrel_offset */
567
568 HOWTO (R_ARM_ALU_PCREL23_15, /* type */
569 0, /* rightshift */
570 2, /* size (0 = byte, 1 = short, 2 = long) */
571 12, /* bitsize */
572 TRUE, /* pc_relative */
573 16, /* bitpos */
574 complain_overflow_dont,/* complain_on_overflow */
575 bfd_elf_generic_reloc, /* special_function */
576 "R_ARM_ALU_PCREL_23_15",/* name */
577 FALSE, /* partial_inplace */
578 0x00000fff, /* src_mask */
579 0x00000fff, /* dst_mask */
580 TRUE), /* pcrel_offset */
581
582 HOWTO (R_ARM_LDR_SBREL_11_0, /* type */
583 0, /* rightshift */
584 2, /* size (0 = byte, 1 = short, 2 = long) */
585 12, /* bitsize */
586 FALSE, /* pc_relative */
587 0, /* bitpos */
588 complain_overflow_dont,/* complain_on_overflow */
589 bfd_elf_generic_reloc, /* special_function */
590 "R_ARM_LDR_SBREL_11_0",/* name */
591 FALSE, /* partial_inplace */
592 0x00000fff, /* src_mask */
593 0x00000fff, /* dst_mask */
594 FALSE), /* pcrel_offset */
595
596 HOWTO (R_ARM_ALU_SBREL_19_12, /* type */
597 0, /* rightshift */
598 2, /* size (0 = byte, 1 = short, 2 = long) */
599 8, /* bitsize */
600 FALSE, /* pc_relative */
601 12, /* bitpos */
602 complain_overflow_dont,/* complain_on_overflow */
603 bfd_elf_generic_reloc, /* special_function */
604 "R_ARM_ALU_SBREL_19_12",/* name */
605 FALSE, /* partial_inplace */
606 0x000ff000, /* src_mask */
607 0x000ff000, /* dst_mask */
608 FALSE), /* pcrel_offset */
609
610 HOWTO (R_ARM_ALU_SBREL_27_20, /* type */
611 0, /* rightshift */
612 2, /* size (0 = byte, 1 = short, 2 = long) */
613 8, /* bitsize */
614 FALSE, /* pc_relative */
615 20, /* bitpos */
616 complain_overflow_dont,/* complain_on_overflow */
617 bfd_elf_generic_reloc, /* special_function */
618 "R_ARM_ALU_SBREL_27_20",/* name */
619 FALSE, /* partial_inplace */
620 0x0ff00000, /* src_mask */
621 0x0ff00000, /* dst_mask */
622 FALSE), /* pcrel_offset */
623
624 HOWTO (R_ARM_TARGET1, /* type */
625 0, /* rightshift */
626 2, /* size (0 = byte, 1 = short, 2 = long) */
627 32, /* bitsize */
628 FALSE, /* pc_relative */
629 0, /* bitpos */
630 complain_overflow_dont,/* complain_on_overflow */
631 bfd_elf_generic_reloc, /* special_function */
632 "R_ARM_TARGET1", /* name */
633 FALSE, /* partial_inplace */
634 0xffffffff, /* src_mask */
635 0xffffffff, /* dst_mask */
636 FALSE), /* pcrel_offset */
637
638 HOWTO (R_ARM_ROSEGREL32, /* type */
639 0, /* rightshift */
640 2, /* size (0 = byte, 1 = short, 2 = long) */
641 32, /* bitsize */
642 FALSE, /* pc_relative */
643 0, /* bitpos */
644 complain_overflow_dont,/* complain_on_overflow */
645 bfd_elf_generic_reloc, /* special_function */
646 "R_ARM_ROSEGREL32", /* name */
647 FALSE, /* partial_inplace */
648 0xffffffff, /* src_mask */
649 0xffffffff, /* dst_mask */
650 FALSE), /* pcrel_offset */
651
652 HOWTO (R_ARM_V4BX, /* type */
653 0, /* rightshift */
654 2, /* size (0 = byte, 1 = short, 2 = long) */
655 32, /* bitsize */
656 FALSE, /* pc_relative */
657 0, /* bitpos */
658 complain_overflow_dont,/* complain_on_overflow */
659 bfd_elf_generic_reloc, /* special_function */
660 "R_ARM_V4BX", /* name */
661 FALSE, /* partial_inplace */
662 0xffffffff, /* src_mask */
663 0xffffffff, /* dst_mask */
664 FALSE), /* pcrel_offset */
665
666 HOWTO (R_ARM_TARGET2, /* type */
667 0, /* rightshift */
668 2, /* size (0 = byte, 1 = short, 2 = long) */
669 32, /* bitsize */
670 FALSE, /* pc_relative */
671 0, /* bitpos */
672 complain_overflow_signed,/* complain_on_overflow */
673 bfd_elf_generic_reloc, /* special_function */
674 "R_ARM_TARGET2", /* name */
675 FALSE, /* partial_inplace */
676 0xffffffff, /* src_mask */
677 0xffffffff, /* dst_mask */
678 TRUE), /* pcrel_offset */
679
680 HOWTO (R_ARM_PREL31, /* type */
681 0, /* rightshift */
682 2, /* size (0 = byte, 1 = short, 2 = long) */
683 31, /* bitsize */
684 TRUE, /* pc_relative */
685 0, /* bitpos */
686 complain_overflow_signed,/* complain_on_overflow */
687 bfd_elf_generic_reloc, /* special_function */
688 "R_ARM_PREL31", /* name */
689 FALSE, /* partial_inplace */
690 0x7fffffff, /* src_mask */
691 0x7fffffff, /* dst_mask */
692 TRUE), /* pcrel_offset */
c19d1205
ZW		 693
694 HOWTO (R_ARM_MOVW_ABS_NC, /* type */
695 0, /* rightshift */
696 2, /* size (0 = byte, 1 = short, 2 = long) */
697 16, /* bitsize */
698 FALSE, /* pc_relative */
699 0, /* bitpos */
700 complain_overflow_dont,/* complain_on_overflow */
701 bfd_elf_generic_reloc, /* special_function */
702 "R_ARM_MOVW_ABS_NC", /* name */
703 FALSE, /* partial_inplace */
39623e12
PB		 704 0x000f0fff, /* src_mask */
705 0x000f0fff, /* dst_mask */
c19d1205
ZW		 706 FALSE), /* pcrel_offset */
707
708 HOWTO (R_ARM_MOVT_ABS, /* type */
709 0, /* rightshift */
710 2, /* size (0 = byte, 1 = short, 2 = long) */
711 16, /* bitsize */
712 FALSE, /* pc_relative */
713 0, /* bitpos */
714 complain_overflow_bitfield,/* complain_on_overflow */
715 bfd_elf_generic_reloc, /* special_function */
716 "R_ARM_MOVT_ABS", /* name */
717 FALSE, /* partial_inplace */
39623e12
PB		 718 0x000f0fff, /* src_mask */
719 0x000f0fff, /* dst_mask */
c19d1205
ZW		 720 FALSE), /* pcrel_offset */
721
722 HOWTO (R_ARM_MOVW_PREL_NC, /* type */
723 0, /* rightshift */
724 2, /* size (0 = byte, 1 = short, 2 = long) */
725 16, /* bitsize */
726 TRUE, /* pc_relative */
727 0, /* bitpos */
728 complain_overflow_dont,/* complain_on_overflow */
729 bfd_elf_generic_reloc, /* special_function */
730 "R_ARM_MOVW_PREL_NC", /* name */
731 FALSE, /* partial_inplace */
39623e12
PB		 732 0x000f0fff, /* src_mask */
733 0x000f0fff, /* dst_mask */
c19d1205
ZW		 734 TRUE), /* pcrel_offset */
735
736 HOWTO (R_ARM_MOVT_PREL, /* type */
737 0, /* rightshift */
738 2, /* size (0 = byte, 1 = short, 2 = long) */
739 16, /* bitsize */
740 TRUE, /* pc_relative */
741 0, /* bitpos */
742 complain_overflow_bitfield,/* complain_on_overflow */
743 bfd_elf_generic_reloc, /* special_function */
744 "R_ARM_MOVT_PREL", /* name */
745 FALSE, /* partial_inplace */
39623e12
PB		 746 0x000f0fff, /* src_mask */
747 0x000f0fff, /* dst_mask */
c19d1205
ZW		 748 TRUE), /* pcrel_offset */
749
750 HOWTO (R_ARM_THM_MOVW_ABS_NC, /* type */
751 0, /* rightshift */
752 2, /* size (0 = byte, 1 = short, 2 = long) */
753 16, /* bitsize */
754 FALSE, /* pc_relative */
755 0, /* bitpos */
756 complain_overflow_dont,/* complain_on_overflow */
757 bfd_elf_generic_reloc, /* special_function */
758 "R_ARM_THM_MOVW_ABS_NC",/* name */
759 FALSE, /* partial_inplace */
760 0x040f70ff, /* src_mask */
761 0x040f70ff, /* dst_mask */
762 FALSE), /* pcrel_offset */
763
764 HOWTO (R_ARM_THM_MOVT_ABS, /* type */
765 0, /* rightshift */
766 2, /* size (0 = byte, 1 = short, 2 = long) */
767 16, /* bitsize */
768 FALSE, /* pc_relative */
769 0, /* bitpos */
770 complain_overflow_bitfield,/* complain_on_overflow */
771 bfd_elf_generic_reloc, /* special_function */
772 "R_ARM_THM_MOVT_ABS", /* name */
773 FALSE, /* partial_inplace */
774 0x040f70ff, /* src_mask */
775 0x040f70ff, /* dst_mask */
776 FALSE), /* pcrel_offset */
777
778 HOWTO (R_ARM_THM_MOVW_PREL_NC,/* type */
779 0, /* rightshift */
780 2, /* size (0 = byte, 1 = short, 2 = long) */
781 16, /* bitsize */
782 TRUE, /* pc_relative */
783 0, /* bitpos */
784 complain_overflow_dont,/* complain_on_overflow */
785 bfd_elf_generic_reloc, /* special_function */
786 "R_ARM_THM_MOVW_PREL_NC",/* name */
787 FALSE, /* partial_inplace */
788 0x040f70ff, /* src_mask */
789 0x040f70ff, /* dst_mask */
790 TRUE), /* pcrel_offset */
791
792 HOWTO (R_ARM_THM_MOVT_PREL, /* type */
793 0, /* rightshift */
794 2, /* size (0 = byte, 1 = short, 2 = long) */
795 16, /* bitsize */
796 TRUE, /* pc_relative */
797 0, /* bitpos */
798 complain_overflow_bitfield,/* complain_on_overflow */
799 bfd_elf_generic_reloc, /* special_function */
800 "R_ARM_THM_MOVT_PREL", /* name */
801 FALSE, /* partial_inplace */
802 0x040f70ff, /* src_mask */
803 0x040f70ff, /* dst_mask */
804 TRUE), /* pcrel_offset */
805
806 HOWTO (R_ARM_THM_JUMP19, /* type */
807 1, /* rightshift */
808 2, /* size (0 = byte, 1 = short, 2 = long) */
809 19, /* bitsize */
810 TRUE, /* pc_relative */
811 0, /* bitpos */
812 complain_overflow_signed,/* complain_on_overflow */
813 bfd_elf_generic_reloc, /* special_function */
814 "R_ARM_THM_JUMP19", /* name */
815 FALSE, /* partial_inplace */
816 0x043f2fff, /* src_mask */
817 0x043f2fff, /* dst_mask */
818 TRUE), /* pcrel_offset */
819
820 HOWTO (R_ARM_THM_JUMP6, /* type */
821 1, /* rightshift */
822 1, /* size (0 = byte, 1 = short, 2 = long) */
823 6, /* bitsize */
824 TRUE, /* pc_relative */
825 0, /* bitpos */
826 complain_overflow_unsigned,/* complain_on_overflow */
827 bfd_elf_generic_reloc, /* special_function */
828 "R_ARM_THM_JUMP6", /* name */
829 FALSE, /* partial_inplace */
830 0x02f8, /* src_mask */
831 0x02f8, /* dst_mask */
832 TRUE), /* pcrel_offset */
833
834 /* These are declared as 13-bit signed relocations because we can
835 address -4095 .. 4095(base) by altering ADDW to SUBW or vice
836 versa. */
837 HOWTO (R_ARM_THM_ALU_PREL_11_0,/* type */
838 0, /* rightshift */
839 2, /* size (0 = byte, 1 = short, 2 = long) */
840 13, /* bitsize */
841 TRUE, /* pc_relative */
842 0, /* bitpos */
2cab6cc3 843 complain_overflow_dont,/* complain_on_overflow */
c19d1205
ZW		 844 bfd_elf_generic_reloc, /* special_function */
845 "R_ARM_THM_ALU_PREL_11_0",/* name */
846 FALSE, /* partial_inplace */
2cab6cc3
MS		 847 0xffffffff, /* src_mask */
848 0xffffffff, /* dst_mask */
c19d1205
ZW		 849 TRUE), /* pcrel_offset */
850
851 HOWTO (R_ARM_THM_PC12, /* type */
852 0, /* rightshift */
853 2, /* size (0 = byte, 1 = short, 2 = long) */
854 13, /* bitsize */
855 TRUE, /* pc_relative */
856 0, /* bitpos */
2cab6cc3 857 complain_overflow_dont,/* complain_on_overflow */
c19d1205
ZW		 858 bfd_elf_generic_reloc, /* special_function */
859 "R_ARM_THM_PC12", /* name */
860 FALSE, /* partial_inplace */
2cab6cc3
MS		 861 0xffffffff, /* src_mask */
862 0xffffffff, /* dst_mask */
c19d1205
ZW		 863 TRUE), /* pcrel_offset */
864
865 HOWTO (R_ARM_ABS32_NOI, /* type */
866 0, /* rightshift */
867 2, /* size (0 = byte, 1 = short, 2 = long) */
868 32, /* bitsize */
869 FALSE, /* pc_relative */
870 0, /* bitpos */
871 complain_overflow_dont,/* complain_on_overflow */
872 bfd_elf_generic_reloc, /* special_function */
873 "R_ARM_ABS32_NOI", /* name */
874 FALSE, /* partial_inplace */
875 0xffffffff, /* src_mask */
876 0xffffffff, /* dst_mask */
877 FALSE), /* pcrel_offset */
878
879 HOWTO (R_ARM_REL32_NOI, /* type */
880 0, /* rightshift */
881 2, /* size (0 = byte, 1 = short, 2 = long) */
882 32, /* bitsize */
883 TRUE, /* pc_relative */
884 0, /* bitpos */
885 complain_overflow_dont,/* complain_on_overflow */
886 bfd_elf_generic_reloc, /* special_function */
887 "R_ARM_REL32_NOI", /* name */
888 FALSE, /* partial_inplace */
889 0xffffffff, /* src_mask */
890 0xffffffff, /* dst_mask */
891 FALSE), /* pcrel_offset */
7f266840 892
4962c51a
MS		 893 /* Group relocations. */
894
895 HOWTO (R_ARM_ALU_PC_G0_NC, /* type */
896 0, /* rightshift */
897 2, /* size (0 = byte, 1 = short, 2 = long) */
898 32, /* bitsize */
899 TRUE, /* pc_relative */
900 0, /* bitpos */
901 complain_overflow_dont,/* complain_on_overflow */
902 bfd_elf_generic_reloc, /* special_function */
903 "R_ARM_ALU_PC_G0_NC", /* name */
904 FALSE, /* partial_inplace */
905 0xffffffff, /* src_mask */
906 0xffffffff, /* dst_mask */
907 TRUE), /* pcrel_offset */
908
909 HOWTO (R_ARM_ALU_PC_G0, /* type */
910 0, /* rightshift */
911 2, /* size (0 = byte, 1 = short, 2 = long) */
912 32, /* bitsize */
913 TRUE, /* pc_relative */
914 0, /* bitpos */
915 complain_overflow_dont,/* complain_on_overflow */
916 bfd_elf_generic_reloc, /* special_function */
917 "R_ARM_ALU_PC_G0", /* name */
918 FALSE, /* partial_inplace */
919 0xffffffff, /* src_mask */
920 0xffffffff, /* dst_mask */
921 TRUE), /* pcrel_offset */
922
923 HOWTO (R_ARM_ALU_PC_G1_NC, /* type */
924 0, /* rightshift */
925 2, /* size (0 = byte, 1 = short, 2 = long) */
926 32, /* bitsize */
927 TRUE, /* pc_relative */
928 0, /* bitpos */
929 complain_overflow_dont,/* complain_on_overflow */
930 bfd_elf_generic_reloc, /* special_function */
931 "R_ARM_ALU_PC_G1_NC", /* name */
932 FALSE, /* partial_inplace */
933 0xffffffff, /* src_mask */
934 0xffffffff, /* dst_mask */
935 TRUE), /* pcrel_offset */
936
937 HOWTO (R_ARM_ALU_PC_G1, /* type */
938 0, /* rightshift */
939 2, /* size (0 = byte, 1 = short, 2 = long) */
940 32, /* bitsize */
941 TRUE, /* pc_relative */
942 0, /* bitpos */
943 complain_overflow_dont,/* complain_on_overflow */
944 bfd_elf_generic_reloc, /* special_function */
945 "R_ARM_ALU_PC_G1", /* name */
946 FALSE, /* partial_inplace */
947 0xffffffff, /* src_mask */
948 0xffffffff, /* dst_mask */
949 TRUE), /* pcrel_offset */
950
951 HOWTO (R_ARM_ALU_PC_G2, /* type */
952 0, /* rightshift */
953 2, /* size (0 = byte, 1 = short, 2 = long) */
954 32, /* bitsize */
955 TRUE, /* pc_relative */
956 0, /* bitpos */
957 complain_overflow_dont,/* complain_on_overflow */
958 bfd_elf_generic_reloc, /* special_function */
959 "R_ARM_ALU_PC_G2", /* name */
960 FALSE, /* partial_inplace */
961 0xffffffff, /* src_mask */
962 0xffffffff, /* dst_mask */
963 TRUE), /* pcrel_offset */
964
965 HOWTO (R_ARM_LDR_PC_G1, /* type */
966 0, /* rightshift */
967 2, /* size (0 = byte, 1 = short, 2 = long) */
968 32, /* bitsize */
969 TRUE, /* pc_relative */
970 0, /* bitpos */
971 complain_overflow_dont,/* complain_on_overflow */
972 bfd_elf_generic_reloc, /* special_function */
973 "R_ARM_LDR_PC_G1", /* name */
974 FALSE, /* partial_inplace */
975 0xffffffff, /* src_mask */
976 0xffffffff, /* dst_mask */
977 TRUE), /* pcrel_offset */
978
979 HOWTO (R_ARM_LDR_PC_G2, /* type */
980 0, /* rightshift */
981 2, /* size (0 = byte, 1 = short, 2 = long) */
982 32, /* bitsize */
983 TRUE, /* pc_relative */
984 0, /* bitpos */
985 complain_overflow_dont,/* complain_on_overflow */
986 bfd_elf_generic_reloc, /* special_function */
987 "R_ARM_LDR_PC_G2", /* name */
988 FALSE, /* partial_inplace */
989 0xffffffff, /* src_mask */
990 0xffffffff, /* dst_mask */
991 TRUE), /* pcrel_offset */
992
993 HOWTO (R_ARM_LDRS_PC_G0, /* type */
994 0, /* rightshift */
995 2, /* size (0 = byte, 1 = short, 2 = long) */
996 32, /* bitsize */
997 TRUE, /* pc_relative */
998 0, /* bitpos */
999 complain_overflow_dont,/* complain_on_overflow */
1000 bfd_elf_generic_reloc, /* special_function */
1001 "R_ARM_LDRS_PC_G0", /* name */
1002 FALSE, /* partial_inplace */
1003 0xffffffff, /* src_mask */
1004 0xffffffff, /* dst_mask */
1005 TRUE), /* pcrel_offset */
1006
1007 HOWTO (R_ARM_LDRS_PC_G1, /* type */
1008 0, /* rightshift */
1009 2, /* size (0 = byte, 1 = short, 2 = long) */
1010 32, /* bitsize */
1011 TRUE, /* pc_relative */
1012 0, /* bitpos */
1013 complain_overflow_dont,/* complain_on_overflow */
1014 bfd_elf_generic_reloc, /* special_function */
1015 "R_ARM_LDRS_PC_G1", /* name */
1016 FALSE, /* partial_inplace */
1017 0xffffffff, /* src_mask */
1018 0xffffffff, /* dst_mask */
1019 TRUE), /* pcrel_offset */
1020
1021 HOWTO (R_ARM_LDRS_PC_G2, /* type */
1022 0, /* rightshift */
1023 2, /* size (0 = byte, 1 = short, 2 = long) */
1024 32, /* bitsize */
1025 TRUE, /* pc_relative */
1026 0, /* bitpos */
1027 complain_overflow_dont,/* complain_on_overflow */
1028 bfd_elf_generic_reloc, /* special_function */
1029 "R_ARM_LDRS_PC_G2", /* name */
1030 FALSE, /* partial_inplace */
1031 0xffffffff, /* src_mask */
1032 0xffffffff, /* dst_mask */
1033 TRUE), /* pcrel_offset */
1034
1035 HOWTO (R_ARM_LDC_PC_G0, /* type */
1036 0, /* rightshift */
1037 2, /* size (0 = byte, 1 = short, 2 = long) */
1038 32, /* bitsize */
1039 TRUE, /* pc_relative */
1040 0, /* bitpos */
1041 complain_overflow_dont,/* complain_on_overflow */
1042 bfd_elf_generic_reloc, /* special_function */
1043 "R_ARM_LDC_PC_G0", /* name */
1044 FALSE, /* partial_inplace */
1045 0xffffffff, /* src_mask */
1046 0xffffffff, /* dst_mask */
1047 TRUE), /* pcrel_offset */
1048
1049 HOWTO (R_ARM_LDC_PC_G1, /* type */
1050 0, /* rightshift */
1051 2, /* size (0 = byte, 1 = short, 2 = long) */
1052 32, /* bitsize */
1053 TRUE, /* pc_relative */
1054 0, /* bitpos */
1055 complain_overflow_dont,/* complain_on_overflow */
1056 bfd_elf_generic_reloc, /* special_function */
1057 "R_ARM_LDC_PC_G1", /* name */
1058 FALSE, /* partial_inplace */
1059 0xffffffff, /* src_mask */
1060 0xffffffff, /* dst_mask */
1061 TRUE), /* pcrel_offset */
1062
1063 HOWTO (R_ARM_LDC_PC_G2, /* type */
1064 0, /* rightshift */
1065 2, /* size (0 = byte, 1 = short, 2 = long) */
1066 32, /* bitsize */
1067 TRUE, /* pc_relative */
1068 0, /* bitpos */
1069 complain_overflow_dont,/* complain_on_overflow */
1070 bfd_elf_generic_reloc, /* special_function */
1071 "R_ARM_LDC_PC_G2", /* name */
1072 FALSE, /* partial_inplace */
1073 0xffffffff, /* src_mask */
1074 0xffffffff, /* dst_mask */
1075 TRUE), /* pcrel_offset */
1076
1077 HOWTO (R_ARM_ALU_SB_G0_NC, /* type */
1078 0, /* rightshift */
1079 2, /* size (0 = byte, 1 = short, 2 = long) */
1080 32, /* bitsize */
1081 TRUE, /* pc_relative */
1082 0, /* bitpos */
1083 complain_overflow_dont,/* complain_on_overflow */
1084 bfd_elf_generic_reloc, /* special_function */
1085 "R_ARM_ALU_SB_G0_NC", /* name */
1086 FALSE, /* partial_inplace */
1087 0xffffffff, /* src_mask */
1088 0xffffffff, /* dst_mask */
1089 TRUE), /* pcrel_offset */
1090
1091 HOWTO (R_ARM_ALU_SB_G0, /* type */
1092 0, /* rightshift */
1093 2, /* size (0 = byte, 1 = short, 2 = long) */
1094 32, /* bitsize */
1095 TRUE, /* pc_relative */
1096 0, /* bitpos */
1097 complain_overflow_dont,/* complain_on_overflow */
1098 bfd_elf_generic_reloc, /* special_function */
1099 "R_ARM_ALU_SB_G0", /* name */
1100 FALSE, /* partial_inplace */
1101 0xffffffff, /* src_mask */
1102 0xffffffff, /* dst_mask */
1103 TRUE), /* pcrel_offset */
1104
1105 HOWTO (R_ARM_ALU_SB_G1_NC, /* type */
1106 0, /* rightshift */
1107 2, /* size (0 = byte, 1 = short, 2 = long) */
1108 32, /* bitsize */
1109 TRUE, /* pc_relative */
1110 0, /* bitpos */
1111 complain_overflow_dont,/* complain_on_overflow */
1112 bfd_elf_generic_reloc, /* special_function */
1113 "R_ARM_ALU_SB_G1_NC", /* name */
1114 FALSE, /* partial_inplace */
1115 0xffffffff, /* src_mask */
1116 0xffffffff, /* dst_mask */
1117 TRUE), /* pcrel_offset */
1118
1119 HOWTO (R_ARM_ALU_SB_G1, /* type */
1120 0, /* rightshift */
1121 2, /* size (0 = byte, 1 = short, 2 = long) */
1122 32, /* bitsize */
1123 TRUE, /* pc_relative */
1124 0, /* bitpos */
1125 complain_overflow_dont,/* complain_on_overflow */
1126 bfd_elf_generic_reloc, /* special_function */
1127 "R_ARM_ALU_SB_G1", /* name */
1128 FALSE, /* partial_inplace */
1129 0xffffffff, /* src_mask */
1130 0xffffffff, /* dst_mask */
1131 TRUE), /* pcrel_offset */
1132
1133 HOWTO (R_ARM_ALU_SB_G2, /* type */
1134 0, /* rightshift */
1135 2, /* size (0 = byte, 1 = short, 2 = long) */
1136 32, /* bitsize */
1137 TRUE, /* pc_relative */
1138 0, /* bitpos */
1139 complain_overflow_dont,/* complain_on_overflow */
1140 bfd_elf_generic_reloc, /* special_function */
1141 "R_ARM_ALU_SB_G2", /* name */
1142 FALSE, /* partial_inplace */
1143 0xffffffff, /* src_mask */
1144 0xffffffff, /* dst_mask */
1145 TRUE), /* pcrel_offset */
1146
1147 HOWTO (R_ARM_LDR_SB_G0, /* type */
1148 0, /* rightshift */
1149 2, /* size (0 = byte, 1 = short, 2 = long) */
1150 32, /* bitsize */
1151 TRUE, /* pc_relative */
1152 0, /* bitpos */
1153 complain_overflow_dont,/* complain_on_overflow */
1154 bfd_elf_generic_reloc, /* special_function */
1155 "R_ARM_LDR_SB_G0", /* name */
1156 FALSE, /* partial_inplace */
1157 0xffffffff, /* src_mask */
1158 0xffffffff, /* dst_mask */
1159 TRUE), /* pcrel_offset */
1160
1161 HOWTO (R_ARM_LDR_SB_G1, /* type */
1162 0, /* rightshift */
1163 2, /* size (0 = byte, 1 = short, 2 = long) */
1164 32, /* bitsize */
1165 TRUE, /* pc_relative */
1166 0, /* bitpos */
1167 complain_overflow_dont,/* complain_on_overflow */
1168 bfd_elf_generic_reloc, /* special_function */
1169 "R_ARM_LDR_SB_G1", /* name */
1170 FALSE, /* partial_inplace */
1171 0xffffffff, /* src_mask */
1172 0xffffffff, /* dst_mask */
1173 TRUE), /* pcrel_offset */
1174
1175 HOWTO (R_ARM_LDR_SB_G2, /* type */
1176 0, /* rightshift */
1177 2, /* size (0 = byte, 1 = short, 2 = long) */
1178 32, /* bitsize */
1179 TRUE, /* pc_relative */
1180 0, /* bitpos */
1181 complain_overflow_dont,/* complain_on_overflow */
1182 bfd_elf_generic_reloc, /* special_function */
1183 "R_ARM_LDR_SB_G2", /* name */
1184 FALSE, /* partial_inplace */
1185 0xffffffff, /* src_mask */
1186 0xffffffff, /* dst_mask */
1187 TRUE), /* pcrel_offset */
1188
1189 HOWTO (R_ARM_LDRS_SB_G0, /* type */
1190 0, /* rightshift */
1191 2, /* size (0 = byte, 1 = short, 2 = long) */
1192 32, /* bitsize */
1193 TRUE, /* pc_relative */
1194 0, /* bitpos */
1195 complain_overflow_dont,/* complain_on_overflow */
1196 bfd_elf_generic_reloc, /* special_function */
1197 "R_ARM_LDRS_SB_G0", /* name */
1198 FALSE, /* partial_inplace */
1199 0xffffffff, /* src_mask */
1200 0xffffffff, /* dst_mask */
1201 TRUE), /* pcrel_offset */
1202
1203 HOWTO (R_ARM_LDRS_SB_G1, /* type */
1204 0, /* rightshift */
1205 2, /* size (0 = byte, 1 = short, 2 = long) */
1206 32, /* bitsize */
1207 TRUE, /* pc_relative */
1208 0, /* bitpos */
1209 complain_overflow_dont,/* complain_on_overflow */
1210 bfd_elf_generic_reloc, /* special_function */
1211 "R_ARM_LDRS_SB_G1", /* name */
1212 FALSE, /* partial_inplace */
1213 0xffffffff, /* src_mask */
1214 0xffffffff, /* dst_mask */
1215 TRUE), /* pcrel_offset */
1216
1217 HOWTO (R_ARM_LDRS_SB_G2, /* type */
1218 0, /* rightshift */
1219 2, /* size (0 = byte, 1 = short, 2 = long) */
1220 32, /* bitsize */
1221 TRUE, /* pc_relative */
1222 0, /* bitpos */
1223 complain_overflow_dont,/* complain_on_overflow */
1224 bfd_elf_generic_reloc, /* special_function */
1225 "R_ARM_LDRS_SB_G2", /* name */
1226 FALSE, /* partial_inplace */
1227 0xffffffff, /* src_mask */
1228 0xffffffff, /* dst_mask */
1229 TRUE), /* pcrel_offset */
1230
1231 HOWTO (R_ARM_LDC_SB_G0, /* type */
1232 0, /* rightshift */
1233 2, /* size (0 = byte, 1 = short, 2 = long) */
1234 32, /* bitsize */
1235 TRUE, /* pc_relative */
1236 0, /* bitpos */
1237 complain_overflow_dont,/* complain_on_overflow */
1238 bfd_elf_generic_reloc, /* special_function */
1239 "R_ARM_LDC_SB_G0", /* name */
1240 FALSE, /* partial_inplace */
1241 0xffffffff, /* src_mask */
1242 0xffffffff, /* dst_mask */
1243 TRUE), /* pcrel_offset */
1244
1245 HOWTO (R_ARM_LDC_SB_G1, /* type */
1246 0, /* rightshift */
1247 2, /* size (0 = byte, 1 = short, 2 = long) */
1248 32, /* bitsize */
1249 TRUE, /* pc_relative */
1250 0, /* bitpos */
1251 complain_overflow_dont,/* complain_on_overflow */
1252 bfd_elf_generic_reloc, /* special_function */
1253 "R_ARM_LDC_SB_G1", /* name */
1254 FALSE, /* partial_inplace */
1255 0xffffffff, /* src_mask */
1256 0xffffffff, /* dst_mask */
1257 TRUE), /* pcrel_offset */
1258
1259 HOWTO (R_ARM_LDC_SB_G2, /* type */
1260 0, /* rightshift */
1261 2, /* size (0 = byte, 1 = short, 2 = long) */
1262 32, /* bitsize */
1263 TRUE, /* pc_relative */
1264 0, /* bitpos */
1265 complain_overflow_dont,/* complain_on_overflow */
1266 bfd_elf_generic_reloc, /* special_function */
1267 "R_ARM_LDC_SB_G2", /* name */
1268 FALSE, /* partial_inplace */
1269 0xffffffff, /* src_mask */
1270 0xffffffff, /* dst_mask */
1271 TRUE), /* pcrel_offset */
1272
1273 /* End of group relocations. */
c19d1205 1274
c19d1205
ZW		 1275 HOWTO (R_ARM_MOVW_BREL_NC, /* type */
1276 0, /* rightshift */
1277 2, /* size (0 = byte, 1 = short, 2 = long) */
1278 16, /* bitsize */
1279 FALSE, /* pc_relative */
1280 0, /* bitpos */
1281 complain_overflow_dont,/* complain_on_overflow */
1282 bfd_elf_generic_reloc, /* special_function */
1283 "R_ARM_MOVW_BREL_NC", /* name */
1284 FALSE, /* partial_inplace */
1285 0x0000ffff, /* src_mask */
1286 0x0000ffff, /* dst_mask */
1287 FALSE), /* pcrel_offset */
1288
1289 HOWTO (R_ARM_MOVT_BREL, /* type */
1290 0, /* rightshift */
1291 2, /* size (0 = byte, 1 = short, 2 = long) */
1292 16, /* bitsize */
1293 FALSE, /* pc_relative */
1294 0, /* bitpos */
1295 complain_overflow_bitfield,/* complain_on_overflow */
1296 bfd_elf_generic_reloc, /* special_function */
1297 "R_ARM_MOVT_BREL", /* name */
1298 FALSE, /* partial_inplace */
1299 0x0000ffff, /* src_mask */
1300 0x0000ffff, /* dst_mask */
1301 FALSE), /* pcrel_offset */
1302
1303 HOWTO (R_ARM_MOVW_BREL, /* type */
1304 0, /* rightshift */
1305 2, /* size (0 = byte, 1 = short, 2 = long) */
1306 16, /* bitsize */
1307 FALSE, /* pc_relative */
1308 0, /* bitpos */
1309 complain_overflow_dont,/* complain_on_overflow */
1310 bfd_elf_generic_reloc, /* special_function */
1311 "R_ARM_MOVW_BREL", /* name */
1312 FALSE, /* partial_inplace */
1313 0x0000ffff, /* src_mask */
1314 0x0000ffff, /* dst_mask */
1315 FALSE), /* pcrel_offset */
1316
1317 HOWTO (R_ARM_THM_MOVW_BREL_NC,/* type */
1318 0, /* rightshift */
1319 2, /* size (0 = byte, 1 = short, 2 = long) */
1320 16, /* bitsize */
1321 FALSE, /* pc_relative */
1322 0, /* bitpos */
1323 complain_overflow_dont,/* complain_on_overflow */
1324 bfd_elf_generic_reloc, /* special_function */
1325 "R_ARM_THM_MOVW_BREL_NC",/* name */
1326 FALSE, /* partial_inplace */
1327 0x040f70ff, /* src_mask */
1328 0x040f70ff, /* dst_mask */
1329 FALSE), /* pcrel_offset */
1330
1331 HOWTO (R_ARM_THM_MOVT_BREL, /* type */
1332 0, /* rightshift */
1333 2, /* size (0 = byte, 1 = short, 2 = long) */
1334 16, /* bitsize */
1335 FALSE, /* pc_relative */
1336 0, /* bitpos */
1337 complain_overflow_bitfield,/* complain_on_overflow */
1338 bfd_elf_generic_reloc, /* special_function */
1339 "R_ARM_THM_MOVT_BREL", /* name */
1340 FALSE, /* partial_inplace */
1341 0x040f70ff, /* src_mask */
1342 0x040f70ff, /* dst_mask */
1343 FALSE), /* pcrel_offset */
1344
1345 HOWTO (R_ARM_THM_MOVW_BREL, /* type */
1346 0, /* rightshift */
1347 2, /* size (0 = byte, 1 = short, 2 = long) */
1348 16, /* bitsize */
1349 FALSE, /* pc_relative */
1350 0, /* bitpos */
1351 complain_overflow_dont,/* complain_on_overflow */
1352 bfd_elf_generic_reloc, /* special_function */
1353 "R_ARM_THM_MOVW_BREL", /* name */
1354 FALSE, /* partial_inplace */
1355 0x040f70ff, /* src_mask */
1356 0x040f70ff, /* dst_mask */
1357 FALSE), /* pcrel_offset */
1358
0855e32b
NS		 1359 HOWTO (R_ARM_TLS_GOTDESC, /* type */
1360 0, /* rightshift */
1361 2, /* size (0 = byte, 1 = short, 2 = long) */
1362 32, /* bitsize */
1363 FALSE, /* pc_relative */
1364 0, /* bitpos */
1365 complain_overflow_bitfield,/* complain_on_overflow */
1366 NULL, /* special_function */
1367 "R_ARM_TLS_GOTDESC", /* name */
1368 TRUE, /* partial_inplace */
1369 0xffffffff, /* src_mask */
1370 0xffffffff, /* dst_mask */
1371 FALSE), /* pcrel_offset */
1372
1373 HOWTO (R_ARM_TLS_CALL, /* type */
1374 0, /* rightshift */
1375 2, /* size (0 = byte, 1 = short, 2 = long) */
1376 24, /* bitsize */
1377 FALSE, /* pc_relative */
1378 0, /* bitpos */
1379 complain_overflow_dont,/* complain_on_overflow */
1380 bfd_elf_generic_reloc, /* special_function */
1381 "R_ARM_TLS_CALL", /* name */
1382 FALSE, /* partial_inplace */
1383 0x00ffffff, /* src_mask */
1384 0x00ffffff, /* dst_mask */
1385 FALSE), /* pcrel_offset */
1386
1387 HOWTO (R_ARM_TLS_DESCSEQ, /* type */
1388 0, /* rightshift */
1389 2, /* size (0 = byte, 1 = short, 2 = long) */
1390 0, /* bitsize */
1391 FALSE, /* pc_relative */
1392 0, /* bitpos */
1393 complain_overflow_bitfield,/* complain_on_overflow */
1394 bfd_elf_generic_reloc, /* special_function */
1395 "R_ARM_TLS_DESCSEQ", /* name */
1396 FALSE, /* partial_inplace */
1397 0x00000000, /* src_mask */
1398 0x00000000, /* dst_mask */
1399 FALSE), /* pcrel_offset */
1400
1401 HOWTO (R_ARM_THM_TLS_CALL, /* type */
1402 0, /* rightshift */
1403 2, /* size (0 = byte, 1 = short, 2 = long) */
1404 24, /* bitsize */
1405 FALSE, /* pc_relative */
1406 0, /* bitpos */
1407 complain_overflow_dont,/* complain_on_overflow */
1408 bfd_elf_generic_reloc, /* special_function */
1409 "R_ARM_THM_TLS_CALL", /* name */
1410 FALSE, /* partial_inplace */
1411 0x07ff07ff, /* src_mask */
1412 0x07ff07ff, /* dst_mask */
1413 FALSE), /* pcrel_offset */
c19d1205
ZW		 1414
1415 HOWTO (R_ARM_PLT32_ABS, /* type */
1416 0, /* rightshift */
1417 2, /* size (0 = byte, 1 = short, 2 = long) */
1418 32, /* bitsize */
1419 FALSE, /* pc_relative */
1420 0, /* bitpos */
1421 complain_overflow_dont,/* complain_on_overflow */
1422 bfd_elf_generic_reloc, /* special_function */
1423 "R_ARM_PLT32_ABS", /* name */
1424 FALSE, /* partial_inplace */
1425 0xffffffff, /* src_mask */
1426 0xffffffff, /* dst_mask */
1427 FALSE), /* pcrel_offset */
1428
1429 HOWTO (R_ARM_GOT_ABS, /* type */
1430 0, /* rightshift */
1431 2, /* size (0 = byte, 1 = short, 2 = long) */
1432 32, /* bitsize */
1433 FALSE, /* pc_relative */
1434 0, /* bitpos */
1435 complain_overflow_dont,/* complain_on_overflow */
1436 bfd_elf_generic_reloc, /* special_function */
1437 "R_ARM_GOT_ABS", /* name */
1438 FALSE, /* partial_inplace */
1439 0xffffffff, /* src_mask */
1440 0xffffffff, /* dst_mask */
1441 FALSE), /* pcrel_offset */
1442
1443 HOWTO (R_ARM_GOT_PREL, /* type */
1444 0, /* rightshift */
1445 2, /* size (0 = byte, 1 = short, 2 = long) */
1446 32, /* bitsize */
1447 TRUE, /* pc_relative */
1448 0, /* bitpos */
1449 complain_overflow_dont, /* complain_on_overflow */
1450 bfd_elf_generic_reloc, /* special_function */
1451 "R_ARM_GOT_PREL", /* name */
1452 FALSE, /* partial_inplace */
1453 0xffffffff, /* src_mask */
1454 0xffffffff, /* dst_mask */
1455 TRUE), /* pcrel_offset */
1456
1457 HOWTO (R_ARM_GOT_BREL12, /* type */
1458 0, /* rightshift */
1459 2, /* size (0 = byte, 1 = short, 2 = long) */
1460 12, /* bitsize */
1461 FALSE, /* pc_relative */
1462 0, /* bitpos */
1463 complain_overflow_bitfield,/* complain_on_overflow */
1464 bfd_elf_generic_reloc, /* special_function */
1465 "R_ARM_GOT_BREL12", /* name */
1466 FALSE, /* partial_inplace */
1467 0x00000fff, /* src_mask */
1468 0x00000fff, /* dst_mask */
1469 FALSE), /* pcrel_offset */
1470
1471 HOWTO (R_ARM_GOTOFF12, /* type */
1472 0, /* rightshift */
1473 2, /* size (0 = byte, 1 = short, 2 = long) */
1474 12, /* bitsize */
1475 FALSE, /* pc_relative */
1476 0, /* bitpos */
1477 complain_overflow_bitfield,/* complain_on_overflow */
1478 bfd_elf_generic_reloc, /* special_function */
1479 "R_ARM_GOTOFF12", /* name */
1480 FALSE, /* partial_inplace */
1481 0x00000fff, /* src_mask */
1482 0x00000fff, /* dst_mask */
1483 FALSE), /* pcrel_offset */
1484
1485 EMPTY_HOWTO (R_ARM_GOTRELAX), /* reserved for future GOT-load optimizations */
1486
1487 /* GNU extension to record C++ vtable member usage */
1488 HOWTO (R_ARM_GNU_VTENTRY, /* type */
99059e56
RM		 1489 0, /* rightshift */
1490 2, /* size (0 = byte, 1 = short, 2 = long) */
1491 0, /* bitsize */
1492 FALSE, /* pc_relative */
1493 0, /* bitpos */
1494 complain_overflow_dont, /* complain_on_overflow */
1495 _bfd_elf_rel_vtable_reloc_fn, /* special_function */
1496 "R_ARM_GNU_VTENTRY", /* name */
1497 FALSE, /* partial_inplace */
1498 0, /* src_mask */
1499 0, /* dst_mask */
1500 FALSE), /* pcrel_offset */
c19d1205
ZW		 1501
1502 /* GNU extension to record C++ vtable hierarchy */
1503 HOWTO (R_ARM_GNU_VTINHERIT, /* type */
99059e56
RM		 1504 0, /* rightshift */
1505 2, /* size (0 = byte, 1 = short, 2 = long) */
1506 0, /* bitsize */
1507 FALSE, /* pc_relative */
1508 0, /* bitpos */
1509 complain_overflow_dont, /* complain_on_overflow */
1510 NULL, /* special_function */
1511 "R_ARM_GNU_VTINHERIT", /* name */
1512 FALSE, /* partial_inplace */
1513 0, /* src_mask */
1514 0, /* dst_mask */
1515 FALSE), /* pcrel_offset */
c19d1205
ZW		 1516
1517 HOWTO (R_ARM_THM_JUMP11, /* type */
1518 1, /* rightshift */
1519 1, /* size (0 = byte, 1 = short, 2 = long) */
1520 11, /* bitsize */
1521 TRUE, /* pc_relative */
1522 0, /* bitpos */
1523 complain_overflow_signed, /* complain_on_overflow */
1524 bfd_elf_generic_reloc, /* special_function */
1525 "R_ARM_THM_JUMP11", /* name */
1526 FALSE, /* partial_inplace */
1527 0x000007ff, /* src_mask */
1528 0x000007ff, /* dst_mask */
1529 TRUE), /* pcrel_offset */
1530
1531 HOWTO (R_ARM_THM_JUMP8, /* type */
1532 1, /* rightshift */
1533 1, /* size (0 = byte, 1 = short, 2 = long) */
1534 8, /* bitsize */
1535 TRUE, /* pc_relative */
1536 0, /* bitpos */
1537 complain_overflow_signed, /* complain_on_overflow */
1538 bfd_elf_generic_reloc, /* special_function */
1539 "R_ARM_THM_JUMP8", /* name */
1540 FALSE, /* partial_inplace */
1541 0x000000ff, /* src_mask */
1542 0x000000ff, /* dst_mask */
1543 TRUE), /* pcrel_offset */
ba93b8ac 1544
c19d1205
ZW		 1545 /* TLS relocations */
1546 HOWTO (R_ARM_TLS_GD32, /* type */
99059e56
RM		 1547 0, /* rightshift */
1548 2, /* size (0 = byte, 1 = short, 2 = long) */
1549 32, /* bitsize */
1550 FALSE, /* pc_relative */
1551 0, /* bitpos */
1552 complain_overflow_bitfield,/* complain_on_overflow */
1553 NULL, /* special_function */
1554 "R_ARM_TLS_GD32", /* name */
1555 TRUE, /* partial_inplace */
1556 0xffffffff, /* src_mask */
1557 0xffffffff, /* dst_mask */
1558 FALSE), /* pcrel_offset */
ba93b8ac 1559
ba93b8ac 1560 HOWTO (R_ARM_TLS_LDM32, /* type */
99059e56
RM		 1561 0, /* rightshift */
1562 2, /* size (0 = byte, 1 = short, 2 = long) */
1563 32, /* bitsize */
1564 FALSE, /* pc_relative */
1565 0, /* bitpos */
1566 complain_overflow_bitfield,/* complain_on_overflow */
1567 bfd_elf_generic_reloc, /* special_function */
1568 "R_ARM_TLS_LDM32", /* name */
1569 TRUE, /* partial_inplace */
1570 0xffffffff, /* src_mask */
1571 0xffffffff, /* dst_mask */
1572 FALSE), /* pcrel_offset */
ba93b8ac 1573
c19d1205 1574 HOWTO (R_ARM_TLS_LDO32, /* type */
99059e56
RM		 1575 0, /* rightshift */
1576 2, /* size (0 = byte, 1 = short, 2 = long) */
1577 32, /* bitsize */
1578 FALSE, /* pc_relative */
1579 0, /* bitpos */
1580 complain_overflow_bitfield,/* complain_on_overflow */
1581 bfd_elf_generic_reloc, /* special_function */
1582 "R_ARM_TLS_LDO32", /* name */
1583 TRUE, /* partial_inplace */
1584 0xffffffff, /* src_mask */
1585 0xffffffff, /* dst_mask */
1586 FALSE), /* pcrel_offset */
ba93b8ac 1587
ba93b8ac 1588 HOWTO (R_ARM_TLS_IE32, /* type */
99059e56
RM		 1589 0, /* rightshift */
1590 2, /* size (0 = byte, 1 = short, 2 = long) */
1591 32, /* bitsize */
1592 FALSE, /* pc_relative */
1593 0, /* bitpos */
1594 complain_overflow_bitfield,/* complain_on_overflow */
1595 NULL, /* special_function */
1596 "R_ARM_TLS_IE32", /* name */
1597 TRUE, /* partial_inplace */
1598 0xffffffff, /* src_mask */
1599 0xffffffff, /* dst_mask */
1600 FALSE), /* pcrel_offset */
7f266840 1601
c19d1205 1602 HOWTO (R_ARM_TLS_LE32, /* type */
99059e56
RM		 1603 0, /* rightshift */
1604 2, /* size (0 = byte, 1 = short, 2 = long) */
1605 32, /* bitsize */
1606 FALSE, /* pc_relative */
1607 0, /* bitpos */
1608 complain_overflow_bitfield,/* complain_on_overflow */
75c11999 1609 NULL, /* special_function */
99059e56
RM		 1610 "R_ARM_TLS_LE32", /* name */
1611 TRUE, /* partial_inplace */
1612 0xffffffff, /* src_mask */
1613 0xffffffff, /* dst_mask */
1614 FALSE), /* pcrel_offset */
7f266840 1615
c19d1205
ZW		 1616 HOWTO (R_ARM_TLS_LDO12, /* type */
1617 0, /* rightshift */
1618 2, /* size (0 = byte, 1 = short, 2 = long) */
1619 12, /* bitsize */
1620 FALSE, /* pc_relative */
7f266840 1621 0, /* bitpos */
c19d1205 1622 complain_overflow_bitfield,/* complain_on_overflow */
7f266840 1623 bfd_elf_generic_reloc, /* special_function */
c19d1205 1624 "R_ARM_TLS_LDO12", /* name */
7f266840 1625 FALSE, /* partial_inplace */
c19d1205
ZW		 1626 0x00000fff, /* src_mask */
1627 0x00000fff, /* dst_mask */
1628 FALSE), /* pcrel_offset */
7f266840 1629
c19d1205
ZW		 1630 HOWTO (R_ARM_TLS_LE12, /* type */
1631 0, /* rightshift */
1632 2, /* size (0 = byte, 1 = short, 2 = long) */
1633 12, /* bitsize */
1634 FALSE, /* pc_relative */
7f266840 1635 0, /* bitpos */
c19d1205 1636 complain_overflow_bitfield,/* complain_on_overflow */
7f266840 1637 bfd_elf_generic_reloc, /* special_function */
c19d1205 1638 "R_ARM_TLS_LE12", /* name */
7f266840 1639 FALSE, /* partial_inplace */
c19d1205
ZW		 1640 0x00000fff, /* src_mask */
1641 0x00000fff, /* dst_mask */
1642 FALSE), /* pcrel_offset */
7f266840 1643
c19d1205 1644 HOWTO (R_ARM_TLS_IE12GP, /* type */
7f266840
DJ		 1645 0, /* rightshift */
1646 2, /* size (0 = byte, 1 = short, 2 = long) */
c19d1205
ZW		 1647 12, /* bitsize */
1648 FALSE, /* pc_relative */
7f266840 1649 0, /* bitpos */
c19d1205 1650 complain_overflow_bitfield,/* complain_on_overflow */
7f266840 1651 bfd_elf_generic_reloc, /* special_function */
c19d1205 1652 "R_ARM_TLS_IE12GP", /* name */
7f266840 1653 FALSE, /* partial_inplace */
c19d1205
ZW		 1654 0x00000fff, /* src_mask */
1655 0x00000fff, /* dst_mask */
1656 FALSE), /* pcrel_offset */
0855e32b 1657
34e77a92 1658 /* 112-127 private relocations. */
0855e32b
NS		 1659 EMPTY_HOWTO (112),
1660 EMPTY_HOWTO (113),
1661 EMPTY_HOWTO (114),
1662 EMPTY_HOWTO (115),
1663 EMPTY_HOWTO (116),
1664 EMPTY_HOWTO (117),
1665 EMPTY_HOWTO (118),
1666 EMPTY_HOWTO (119),
1667 EMPTY_HOWTO (120),
1668 EMPTY_HOWTO (121),
1669 EMPTY_HOWTO (122),
1670 EMPTY_HOWTO (123),
1671 EMPTY_HOWTO (124),
1672 EMPTY_HOWTO (125),
1673 EMPTY_HOWTO (126),
1674 EMPTY_HOWTO (127),
34e77a92
RS		 1675
1676 /* R_ARM_ME_TOO, obsolete. */
0855e32b
NS		 1677 EMPTY_HOWTO (128),
1678
1679 HOWTO (R_ARM_THM_TLS_DESCSEQ, /* type */
1680 0, /* rightshift */
1681 1, /* size (0 = byte, 1 = short, 2 = long) */
1682 0, /* bitsize */
1683 FALSE, /* pc_relative */
1684 0, /* bitpos */
1685 complain_overflow_bitfield,/* complain_on_overflow */
1686 bfd_elf_generic_reloc, /* special_function */
1687 "R_ARM_THM_TLS_DESCSEQ",/* name */
1688 FALSE, /* partial_inplace */
1689 0x00000000, /* src_mask */
1690 0x00000000, /* dst_mask */
1691 FALSE), /* pcrel_offset */
72d98d16
MG		 1692 EMPTY_HOWTO (130),
1693 EMPTY_HOWTO (131),
1694 HOWTO (R_ARM_THM_ALU_ABS_G0_NC,/* type. */
1695 0, /* rightshift. */
1696 1, /* size (0 = byte, 1 = short, 2 = long). */
1697 16, /* bitsize. */
1698 FALSE, /* pc_relative. */
1699 0, /* bitpos. */
1700 complain_overflow_bitfield,/* complain_on_overflow. */
1701 bfd_elf_generic_reloc, /* special_function. */
1702 "R_ARM_THM_ALU_ABS_G0_NC",/* name. */
1703 FALSE, /* partial_inplace. */
1704 0x00000000, /* src_mask. */
1705 0x00000000, /* dst_mask. */
1706 FALSE), /* pcrel_offset. */
1707 HOWTO (R_ARM_THM_ALU_ABS_G1_NC,/* type. */
1708 0, /* rightshift. */
1709 1, /* size (0 = byte, 1 = short, 2 = long). */
1710 16, /* bitsize. */
1711 FALSE, /* pc_relative. */
1712 0, /* bitpos. */
1713 complain_overflow_bitfield,/* complain_on_overflow. */
1714 bfd_elf_generic_reloc, /* special_function. */
1715 "R_ARM_THM_ALU_ABS_G1_NC",/* name. */
1716 FALSE, /* partial_inplace. */
1717 0x00000000, /* src_mask. */
1718 0x00000000, /* dst_mask. */
1719 FALSE), /* pcrel_offset. */
1720 HOWTO (R_ARM_THM_ALU_ABS_G2_NC,/* type. */
1721 0, /* rightshift. */
1722 1, /* size (0 = byte, 1 = short, 2 = long). */
1723 16, /* bitsize. */
1724 FALSE, /* pc_relative. */
1725 0, /* bitpos. */
1726 complain_overflow_bitfield,/* complain_on_overflow. */
1727 bfd_elf_generic_reloc, /* special_function. */
1728 "R_ARM_THM_ALU_ABS_G2_NC",/* name. */
1729 FALSE, /* partial_inplace. */
1730 0x00000000, /* src_mask. */
1731 0x00000000, /* dst_mask. */
1732 FALSE), /* pcrel_offset. */
1733 HOWTO (R_ARM_THM_ALU_ABS_G3_NC,/* type. */
1734 0, /* rightshift. */
1735 1, /* size (0 = byte, 1 = short, 2 = long). */
1736 16, /* bitsize. */
1737 FALSE, /* pc_relative. */
1738 0, /* bitpos. */
1739 complain_overflow_bitfield,/* complain_on_overflow. */
1740 bfd_elf_generic_reloc, /* special_function. */
1741 "R_ARM_THM_ALU_ABS_G3_NC",/* name. */
1742 FALSE, /* partial_inplace. */
1743 0x00000000, /* src_mask. */
1744 0x00000000, /* dst_mask. */
1745 FALSE), /* pcrel_offset. */
c19d1205
ZW		 1746};
1747
34e77a92
RS		 1748/* 160 onwards: */
1749static reloc_howto_type elf32_arm_howto_table_2[1] =
1750{
1751 HOWTO (R_ARM_IRELATIVE, /* type */
99059e56
RM		 1752 0, /* rightshift */
1753 2, /* size (0 = byte, 1 = short, 2 = long) */
1754 32, /* bitsize */
1755 FALSE, /* pc_relative */
1756 0, /* bitpos */
1757 complain_overflow_bitfield,/* complain_on_overflow */
1758 bfd_elf_generic_reloc, /* special_function */
1759 "R_ARM_IRELATIVE", /* name */
1760 TRUE, /* partial_inplace */
1761 0xffffffff, /* src_mask */
1762 0xffffffff, /* dst_mask */
1763 FALSE) /* pcrel_offset */
34e77a92 1764};
c19d1205 1765
34e77a92
RS		 1766/* 249-255 extended, currently unused, relocations: */
1767static reloc_howto_type elf32_arm_howto_table_3[4] =
7f266840
DJ		 1768{
1769 HOWTO (R_ARM_RREL32, /* type */
1770 0, /* rightshift */
1771 0, /* size (0 = byte, 1 = short, 2 = long) */
1772 0, /* bitsize */
1773 FALSE, /* pc_relative */
1774 0, /* bitpos */
1775 complain_overflow_dont,/* complain_on_overflow */
1776 bfd_elf_generic_reloc, /* special_function */
1777 "R_ARM_RREL32", /* name */
1778 FALSE, /* partial_inplace */
1779 0, /* src_mask */
1780 0, /* dst_mask */
1781 FALSE), /* pcrel_offset */
1782
1783 HOWTO (R_ARM_RABS32, /* type */
1784 0, /* rightshift */
1785 0, /* size (0 = byte, 1 = short, 2 = long) */
1786 0, /* bitsize */
1787 FALSE, /* pc_relative */
1788 0, /* bitpos */
1789 complain_overflow_dont,/* complain_on_overflow */
1790 bfd_elf_generic_reloc, /* special_function */
1791 "R_ARM_RABS32", /* name */
1792 FALSE, /* partial_inplace */
1793 0, /* src_mask */
1794 0, /* dst_mask */
1795 FALSE), /* pcrel_offset */
1796
1797 HOWTO (R_ARM_RPC24, /* type */
1798 0, /* rightshift */
1799 0, /* size (0 = byte, 1 = short, 2 = long) */
1800 0, /* bitsize */
1801 FALSE, /* pc_relative */
1802 0, /* bitpos */
1803 complain_overflow_dont,/* complain_on_overflow */
1804 bfd_elf_generic_reloc, /* special_function */
1805 "R_ARM_RPC24", /* name */
1806 FALSE, /* partial_inplace */
1807 0, /* src_mask */
1808 0, /* dst_mask */
1809 FALSE), /* pcrel_offset */
1810
1811 HOWTO (R_ARM_RBASE, /* type */
1812 0, /* rightshift */
1813 0, /* size (0 = byte, 1 = short, 2 = long) */
1814 0, /* bitsize */
1815 FALSE, /* pc_relative */
1816 0, /* bitpos */
1817 complain_overflow_dont,/* complain_on_overflow */
1818 bfd_elf_generic_reloc, /* special_function */
1819 "R_ARM_RBASE", /* name */
1820 FALSE, /* partial_inplace */
1821 0, /* src_mask */
1822 0, /* dst_mask */
1823 FALSE) /* pcrel_offset */
1824};
1825
1826static reloc_howto_type *
1827elf32_arm_howto_from_type (unsigned int r_type)
1828{
906e58ca 1829 if (r_type < ARRAY_SIZE (elf32_arm_howto_table_1))
c19d1205 1830 return &elf32_arm_howto_table_1[r_type];
ba93b8ac 1831
34e77a92
RS		 1832 if (r_type == R_ARM_IRELATIVE)
1833 return &elf32_arm_howto_table_2[r_type - R_ARM_IRELATIVE];
1834
c19d1205 1835 if (r_type >= R_ARM_RREL32
34e77a92
RS		 1836 && r_type < R_ARM_RREL32 + ARRAY_SIZE (elf32_arm_howto_table_3))
1837 return &elf32_arm_howto_table_3[r_type - R_ARM_RREL32];
7f266840 1838
c19d1205 1839 return NULL;
7f266840
DJ		 1840}
1841
1842static void
1843elf32_arm_info_to_howto (bfd * abfd ATTRIBUTE_UNUSED, arelent * bfd_reloc,
1844 Elf_Internal_Rela * elf_reloc)
1845{
1846 unsigned int r_type;
1847
1848 r_type = ELF32_R_TYPE (elf_reloc->r_info);
1849 bfd_reloc->howto = elf32_arm_howto_from_type (r_type);
1850}
1851
1852struct elf32_arm_reloc_map
1853 {
1854 bfd_reloc_code_real_type bfd_reloc_val;
1855 unsigned char elf_reloc_val;
1856 };
1857
1858/* All entries in this list must also be present in elf32_arm_howto_table. */
1859static const struct elf32_arm_reloc_map elf32_arm_reloc_map[] =
1860 {
1861 {BFD_RELOC_NONE, R_ARM_NONE},
1862 {BFD_RELOC_ARM_PCREL_BRANCH, R_ARM_PC24},
39b41c9c
PB		 1863 {BFD_RELOC_ARM_PCREL_CALL, R_ARM_CALL},
1864 {BFD_RELOC_ARM_PCREL_JUMP, R_ARM_JUMP24},
7f266840
DJ		 1865 {BFD_RELOC_ARM_PCREL_BLX, R_ARM_XPC25},
1866 {BFD_RELOC_THUMB_PCREL_BLX, R_ARM_THM_XPC22},
1867 {BFD_RELOC_32, R_ARM_ABS32},
1868 {BFD_RELOC_32_PCREL, R_ARM_REL32},
1869 {BFD_RELOC_8, R_ARM_ABS8},
1870 {BFD_RELOC_16, R_ARM_ABS16},
1871 {BFD_RELOC_ARM_OFFSET_IMM, R_ARM_ABS12},
1872 {BFD_RELOC_ARM_THUMB_OFFSET, R_ARM_THM_ABS5},
c19d1205
ZW		 1873 {BFD_RELOC_THUMB_PCREL_BRANCH25, R_ARM_THM_JUMP24},
1874 {BFD_RELOC_THUMB_PCREL_BRANCH23, R_ARM_THM_CALL},
1875 {BFD_RELOC_THUMB_PCREL_BRANCH12, R_ARM_THM_JUMP11},
1876 {BFD_RELOC_THUMB_PCREL_BRANCH20, R_ARM_THM_JUMP19},
1877 {BFD_RELOC_THUMB_PCREL_BRANCH9, R_ARM_THM_JUMP8},
1878 {BFD_RELOC_THUMB_PCREL_BRANCH7, R_ARM_THM_JUMP6},
7f266840
DJ		 1879 {BFD_RELOC_ARM_GLOB_DAT, R_ARM_GLOB_DAT},
1880 {BFD_RELOC_ARM_JUMP_SLOT, R_ARM_JUMP_SLOT},
1881 {BFD_RELOC_ARM_RELATIVE, R_ARM_RELATIVE},
c19d1205 1882 {BFD_RELOC_ARM_GOTOFF, R_ARM_GOTOFF32},
7f266840 1883 {BFD_RELOC_ARM_GOTPC, R_ARM_GOTPC},
b43420e6 1884 {BFD_RELOC_ARM_GOT_PREL, R_ARM_GOT_PREL},
7f266840
DJ		 1885 {BFD_RELOC_ARM_GOT32, R_ARM_GOT32},
1886 {BFD_RELOC_ARM_PLT32, R_ARM_PLT32},
1887 {BFD_RELOC_ARM_TARGET1, R_ARM_TARGET1},
1888 {BFD_RELOC_ARM_ROSEGREL32, R_ARM_ROSEGREL32},
1889 {BFD_RELOC_ARM_SBREL32, R_ARM_SBREL32},
1890 {BFD_RELOC_ARM_PREL31, R_ARM_PREL31},
ba93b8ac
DJ		 1891 {BFD_RELOC_ARM_TARGET2, R_ARM_TARGET2},
1892 {BFD_RELOC_ARM_PLT32, R_ARM_PLT32},
0855e32b
NS		 1893 {BFD_RELOC_ARM_TLS_GOTDESC, R_ARM_TLS_GOTDESC},
1894 {BFD_RELOC_ARM_TLS_CALL, R_ARM_TLS_CALL},
1895 {BFD_RELOC_ARM_THM_TLS_CALL, R_ARM_THM_TLS_CALL},
1896 {BFD_RELOC_ARM_TLS_DESCSEQ, R_ARM_TLS_DESCSEQ},
1897 {BFD_RELOC_ARM_THM_TLS_DESCSEQ, R_ARM_THM_TLS_DESCSEQ},
1898 {BFD_RELOC_ARM_TLS_DESC, R_ARM_TLS_DESC},
ba93b8ac
DJ		 1899 {BFD_RELOC_ARM_TLS_GD32, R_ARM_TLS_GD32},
1900 {BFD_RELOC_ARM_TLS_LDO32, R_ARM_TLS_LDO32},
1901 {BFD_RELOC_ARM_TLS_LDM32, R_ARM_TLS_LDM32},
1902 {BFD_RELOC_ARM_TLS_DTPMOD32, R_ARM_TLS_DTPMOD32},
1903 {BFD_RELOC_ARM_TLS_DTPOFF32, R_ARM_TLS_DTPOFF32},
1904 {BFD_RELOC_ARM_TLS_TPOFF32, R_ARM_TLS_TPOFF32},
1905 {BFD_RELOC_ARM_TLS_IE32, R_ARM_TLS_IE32},
1906 {BFD_RELOC_ARM_TLS_LE32, R_ARM_TLS_LE32},
34e77a92 1907 {BFD_RELOC_ARM_IRELATIVE, R_ARM_IRELATIVE},
c19d1205
ZW		 1908 {BFD_RELOC_VTABLE_INHERIT, R_ARM_GNU_VTINHERIT},
1909 {BFD_RELOC_VTABLE_ENTRY, R_ARM_GNU_VTENTRY},
b6895b4f
PB		 1910 {BFD_RELOC_ARM_MOVW, R_ARM_MOVW_ABS_NC},
1911 {BFD_RELOC_ARM_MOVT, R_ARM_MOVT_ABS},
1912 {BFD_RELOC_ARM_MOVW_PCREL, R_ARM_MOVW_PREL_NC},
1913 {BFD_RELOC_ARM_MOVT_PCREL, R_ARM_MOVT_PREL},
1914 {BFD_RELOC_ARM_THUMB_MOVW, R_ARM_THM_MOVW_ABS_NC},
1915 {BFD_RELOC_ARM_THUMB_MOVT, R_ARM_THM_MOVT_ABS},
1916 {BFD_RELOC_ARM_THUMB_MOVW_PCREL, R_ARM_THM_MOVW_PREL_NC},
1917 {BFD_RELOC_ARM_THUMB_MOVT_PCREL, R_ARM_THM_MOVT_PREL},
4962c51a
MS		 1918 {BFD_RELOC_ARM_ALU_PC_G0_NC, R_ARM_ALU_PC_G0_NC},
1919 {BFD_RELOC_ARM_ALU_PC_G0, R_ARM_ALU_PC_G0},
1920 {BFD_RELOC_ARM_ALU_PC_G1_NC, R_ARM_ALU_PC_G1_NC},
1921 {BFD_RELOC_ARM_ALU_PC_G1, R_ARM_ALU_PC_G1},
1922 {BFD_RELOC_ARM_ALU_PC_G2, R_ARM_ALU_PC_G2},
1923 {BFD_RELOC_ARM_LDR_PC_G0, R_ARM_LDR_PC_G0},
1924 {BFD_RELOC_ARM_LDR_PC_G1, R_ARM_LDR_PC_G1},
1925 {BFD_RELOC_ARM_LDR_PC_G2, R_ARM_LDR_PC_G2},
1926 {BFD_RELOC_ARM_LDRS_PC_G0, R_ARM_LDRS_PC_G0},
1927 {BFD_RELOC_ARM_LDRS_PC_G1, R_ARM_LDRS_PC_G1},
1928 {BFD_RELOC_ARM_LDRS_PC_G2, R_ARM_LDRS_PC_G2},
1929 {BFD_RELOC_ARM_LDC_PC_G0, R_ARM_LDC_PC_G0},
1930 {BFD_RELOC_ARM_LDC_PC_G1, R_ARM_LDC_PC_G1},
1931 {BFD_RELOC_ARM_LDC_PC_G2, R_ARM_LDC_PC_G2},
1932 {BFD_RELOC_ARM_ALU_SB_G0_NC, R_ARM_ALU_SB_G0_NC},
1933 {BFD_RELOC_ARM_ALU_SB_G0, R_ARM_ALU_SB_G0},
1934 {BFD_RELOC_ARM_ALU_SB_G1_NC, R_ARM_ALU_SB_G1_NC},
1935 {BFD_RELOC_ARM_ALU_SB_G1, R_ARM_ALU_SB_G1},
1936 {BFD_RELOC_ARM_ALU_SB_G2, R_ARM_ALU_SB_G2},
1937 {BFD_RELOC_ARM_LDR_SB_G0, R_ARM_LDR_SB_G0},
1938 {BFD_RELOC_ARM_LDR_SB_G1, R_ARM_LDR_SB_G1},
1939 {BFD_RELOC_ARM_LDR_SB_G2, R_ARM_LDR_SB_G2},
1940 {BFD_RELOC_ARM_LDRS_SB_G0, R_ARM_LDRS_SB_G0},
1941 {BFD_RELOC_ARM_LDRS_SB_G1, R_ARM_LDRS_SB_G1},
1942 {BFD_RELOC_ARM_LDRS_SB_G2, R_ARM_LDRS_SB_G2},
1943 {BFD_RELOC_ARM_LDC_SB_G0, R_ARM_LDC_SB_G0},
1944 {BFD_RELOC_ARM_LDC_SB_G1, R_ARM_LDC_SB_G1},
845b51d6 1945 {BFD_RELOC_ARM_LDC_SB_G2, R_ARM_LDC_SB_G2},
72d98d16
MG		 1946 {BFD_RELOC_ARM_V4BX, R_ARM_V4BX},
1947 {BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC, R_ARM_THM_ALU_ABS_G3_NC},
1948 {BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC, R_ARM_THM_ALU_ABS_G2_NC},
1949 {BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC, R_ARM_THM_ALU_ABS_G1_NC},
1950 {BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC, R_ARM_THM_ALU_ABS_G0_NC}
7f266840
DJ		 1951 };
1952
1953static reloc_howto_type *
f1c71a59
ZW		 1954elf32_arm_reloc_type_lookup (bfd *abfd ATTRIBUTE_UNUSED,
1955 bfd_reloc_code_real_type code)
7f266840
DJ		 1956{
1957 unsigned int i;
8029a119 1958
906e58ca 1959 for (i = 0; i < ARRAY_SIZE (elf32_arm_reloc_map); i ++)
c19d1205
ZW		 1960 if (elf32_arm_reloc_map[i].bfd_reloc_val == code)
1961 return elf32_arm_howto_from_type (elf32_arm_reloc_map[i].elf_reloc_val);
7f266840 1962
c19d1205 1963 return NULL;
7f266840
DJ		 1964}
1965
157090f7
AM		 1966static reloc_howto_type *
1967elf32_arm_reloc_name_lookup (bfd *abfd ATTRIBUTE_UNUSED,
1968 const char *r_name)
1969{
1970 unsigned int i;
1971
906e58ca 1972 for (i = 0; i < ARRAY_SIZE (elf32_arm_howto_table_1); i++)
157090f7
AM		 1973 if (elf32_arm_howto_table_1[i].name != NULL
1974 && strcasecmp (elf32_arm_howto_table_1[i].name, r_name) == 0)
1975 return &elf32_arm_howto_table_1[i];
1976
906e58ca 1977 for (i = 0; i < ARRAY_SIZE (elf32_arm_howto_table_2); i++)
157090f7
AM		 1978 if (elf32_arm_howto_table_2[i].name != NULL
1979 && strcasecmp (elf32_arm_howto_table_2[i].name, r_name) == 0)
1980 return &elf32_arm_howto_table_2[i];
1981
34e77a92
RS		 1982 for (i = 0; i < ARRAY_SIZE (elf32_arm_howto_table_3); i++)
1983 if (elf32_arm_howto_table_3[i].name != NULL
1984 && strcasecmp (elf32_arm_howto_table_3[i].name, r_name) == 0)
1985 return &elf32_arm_howto_table_3[i];
1986
157090f7
AM		 1987 return NULL;
1988}
1989
906e58ca
NC		 1990/* Support for core dump NOTE sections. */
1991
7f266840 1992static bfd_boolean
f1c71a59 1993elf32_arm_nabi_grok_prstatus (bfd *abfd, Elf_Internal_Note *note)
7f266840
DJ		 1994{
1995 int offset;
1996 size_t size;
1997
1998 switch (note->descsz)
1999 {
2000 default:
2001 return FALSE;
2002
8029a119 2003 case 148: /* Linux/ARM 32-bit. */
7f266840 2004 /* pr_cursig */
228e534f 2005 elf_tdata (abfd)->core->signal = bfd_get_16 (abfd, note->descdata + 12);
7f266840
DJ		 2006
2007 /* pr_pid */
228e534f 2008 elf_tdata (abfd)->core->lwpid = bfd_get_32 (abfd, note->descdata + 24);
7f266840
DJ		 2009
2010 /* pr_reg */
2011 offset = 72;
2012 size = 72;
2013
2014 break;
2015 }
2016
2017 /* Make a ".reg/999" section. */
2018 return _bfd_elfcore_make_pseudosection (abfd, ".reg",
2019 size, note->descpos + offset);
2020}
2021
2022static bfd_boolean
f1c71a59 2023elf32_arm_nabi_grok_psinfo (bfd *abfd, Elf_Internal_Note *note)
7f266840
DJ		 2024{
2025 switch (note->descsz)
2026 {
2027 default:
2028 return FALSE;
2029
8029a119 2030 case 124: /* Linux/ARM elf_prpsinfo. */
228e534f 2031 elf_tdata (abfd)->core->pid
4395ee08 2032 = bfd_get_32 (abfd, note->descdata + 12);
228e534f 2033 elf_tdata (abfd)->core->program
7f266840 2034 = _bfd_elfcore_strndup (abfd, note->descdata + 28, 16);
228e534f 2035 elf_tdata (abfd)->core->command
7f266840
DJ		 2036 = _bfd_elfcore_strndup (abfd, note->descdata + 44, 80);
2037 }
2038
2039 /* Note that for some reason, a spurious space is tacked
2040 onto the end of the args in some (at least one anyway)
2041 implementations, so strip it off if it exists. */
7f266840 2042 {
228e534f 2043 char *command = elf_tdata (abfd)->core->command;
7f266840
DJ		 2044 int n = strlen (command);
2045
2046 if (0 < n && command[n - 1] == ' ')
2047 command[n - 1] = '\0';
2048 }
2049
2050 return TRUE;
2051}
2052
1f20dca5
UW		 2053static char *
2054elf32_arm_nabi_write_core_note (bfd *abfd, char *buf, int *bufsiz,
2055 int note_type, ...)
2056{
2057 switch (note_type)
2058 {
2059 default:
2060 return NULL;
2061
2062 case NT_PRPSINFO:
2063 {
2064 char data[124];
2065 va_list ap;
2066
2067 va_start (ap, note_type);
2068 memset (data, 0, sizeof (data));
2069 strncpy (data + 28, va_arg (ap, const char *), 16);
2070 strncpy (data + 44, va_arg (ap, const char *), 80);
2071 va_end (ap);
2072
2073 return elfcore_write_note (abfd, buf, bufsiz,
2074 "CORE", note_type, data, sizeof (data));
2075 }
2076
2077 case NT_PRSTATUS:
2078 {
2079 char data[148];
2080 va_list ap;
2081 long pid;
2082 int cursig;
2083 const void *greg;
2084
2085 va_start (ap, note_type);
2086 memset (data, 0, sizeof (data));
2087 pid = va_arg (ap, long);
2088 bfd_put_32 (abfd, pid, data + 24);
2089 cursig = va_arg (ap, int);
2090 bfd_put_16 (abfd, cursig, data + 12);
2091 greg = va_arg (ap, const void *);
2092 memcpy (data + 72, greg, 72);
2093 va_end (ap);
2094
2095 return elfcore_write_note (abfd, buf, bufsiz,
2096 "CORE", note_type, data, sizeof (data));
2097 }
2098 }
2099}
2100
6d00b590 2101#define TARGET_LITTLE_SYM arm_elf32_le_vec
7f266840 2102#define TARGET_LITTLE_NAME "elf32-littlearm"
6d00b590 2103#define TARGET_BIG_SYM arm_elf32_be_vec
7f266840
DJ		 2104#define TARGET_BIG_NAME "elf32-bigarm"
2105
2106#define elf_backend_grok_prstatus elf32_arm_nabi_grok_prstatus
2107#define elf_backend_grok_psinfo elf32_arm_nabi_grok_psinfo
1f20dca5 2108#define elf_backend_write_core_note elf32_arm_nabi_write_core_note
7f266840 2109
252b5132
RH		 2110typedef unsigned long int insn32;
2111typedef unsigned short int insn16;
2112
3a4a14e9
PB		 2113/* In lieu of proper flags, assume all EABIv4 or later objects are
2114 interworkable. */
57e8b36a 2115#define INTERWORK_FLAG(abfd) \
3a4a14e9 2116 (EF_ARM_EABI_VERSION (elf_elfheader (abfd)->e_flags) >= EF_ARM_EABI_VER4 \
3e6b1042
DJ		 2117 || (elf_elfheader (abfd)->e_flags & EF_ARM_INTERWORK) \
2118 || ((abfd)->flags & BFD_LINKER_CREATED))
9b485d32 2119
252b5132
RH		 2120/* The linker script knows the section names for placement.
2121 The entry_names are used to do simple name mangling on the stubs.
2122 Given a function name, and its type, the stub can be found. The
9b485d32 2123 name can be changed. The only requirement is the %s be present. */
252b5132
RH		 2124#define THUMB2ARM_GLUE_SECTION_NAME ".glue_7t"
2125#define THUMB2ARM_GLUE_ENTRY_NAME "__%s_from_thumb"
2126
2127#define ARM2THUMB_GLUE_SECTION_NAME ".glue_7"
2128#define ARM2THUMB_GLUE_ENTRY_NAME "__%s_from_arm"
2129
c7b8f16e
JB		 2130#define VFP11_ERRATUM_VENEER_SECTION_NAME ".vfp11_veneer"
2131#define VFP11_ERRATUM_VENEER_ENTRY_NAME "__vfp11_veneer_%x"
2132
a504d23a
LA		 2133#define STM32L4XX_ERRATUM_VENEER_SECTION_NAME ".text.stm32l4xx_veneer"
2134#define STM32L4XX_ERRATUM_VENEER_ENTRY_NAME "__stm32l4xx_veneer_%x"
2135
845b51d6
PB		 2136#define ARM_BX_GLUE_SECTION_NAME ".v4_bx"
2137#define ARM_BX_GLUE_ENTRY_NAME "__bx_r%d"
2138
7413f23f
DJ		 2139#define STUB_ENTRY_NAME "__%s_veneer"
2140
252b5132
RH		 2141/* The name of the dynamic interpreter. This is put in the .interp
2142 section. */
2143#define ELF_DYNAMIC_INTERPRETER "/usr/lib/ld.so.1"
2144
0855e32b 2145static const unsigned long tls_trampoline [] =
b38cadfb
NC		 2146{
2147 0xe08e0000, /* add r0, lr, r0 */
2148 0xe5901004, /* ldr r1, [r0,#4] */
2149 0xe12fff11, /* bx r1 */
2150};
0855e32b
NS		 2151
2152static const unsigned long dl_tlsdesc_lazy_trampoline [] =
b38cadfb
NC		 2153{
2154 0xe52d2004, /* push {r2} */
2155 0xe59f200c, /* ldr r2, [pc, #3f - . - 8] */
2156 0xe59f100c, /* ldr r1, [pc, #4f - . - 8] */
2157 0xe79f2002, /* 1: ldr r2, [pc, r2] */
2158 0xe081100f, /* 2: add r1, pc */
2159 0xe12fff12, /* bx r2 */
2160 0x00000014, /* 3: .word _GLOBAL_OFFSET_TABLE_ - 1b - 8
99059e56 2161 + dl_tlsdesc_lazy_resolver(GOT) */
b38cadfb
NC		 2162 0x00000018, /* 4: .word _GLOBAL_OFFSET_TABLE_ - 2b - 8 */
2163};
0855e32b 2164
5e681ec4
PB		 2165#ifdef FOUR_WORD_PLT
2166
252b5132
RH		 2167/* The first entry in a procedure linkage table looks like
2168 this. It is set up so that any shared library function that is
59f2c4e7 2169 called before the relocation has been set up calls the dynamic
9b485d32 2170 linker first. */
e5a52504 2171static const bfd_vma elf32_arm_plt0_entry [] =
b38cadfb
NC		 2172{
2173 0xe52de004, /* str lr, [sp, #-4]! */
2174 0xe59fe010, /* ldr lr, [pc, #16] */
2175 0xe08fe00e, /* add lr, pc, lr */
2176 0xe5bef008, /* ldr pc, [lr, #8]! */
2177};
5e681ec4
PB		 2178
2179/* Subsequent entries in a procedure linkage table look like
2180 this. */
e5a52504 2181static const bfd_vma elf32_arm_plt_entry [] =
b38cadfb
NC		 2182{
2183 0xe28fc600, /* add ip, pc, #NN */
2184 0xe28cca00, /* add ip, ip, #NN */
2185 0xe5bcf000, /* ldr pc, [ip, #NN]! */
2186 0x00000000, /* unused */
2187};
5e681ec4 2188
eed94f8f 2189#else /* not FOUR_WORD_PLT */
5e681ec4 2190
5e681ec4
PB		 2191/* The first entry in a procedure linkage table looks like
2192 this. It is set up so that any shared library function that is
2193 called before the relocation has been set up calls the dynamic
2194 linker first. */
e5a52504 2195static const bfd_vma elf32_arm_plt0_entry [] =
b38cadfb
NC		 2196{
2197 0xe52de004, /* str lr, [sp, #-4]! */
2198 0xe59fe004, /* ldr lr, [pc, #4] */
2199 0xe08fe00e, /* add lr, pc, lr */
2200 0xe5bef008, /* ldr pc, [lr, #8]! */
2201 0x00000000, /* &GOT[0] - . */
2202};
252b5132 2203
1db37fe6
YG		 2204/* By default subsequent entries in a procedure linkage table look like
2205 this. Offsets that don't fit into 28 bits will cause link error. */
2206static const bfd_vma elf32_arm_plt_entry_short [] =
b38cadfb
NC		 2207{
2208 0xe28fc600, /* add ip, pc, #0xNN00000 */
2209 0xe28cca00, /* add ip, ip, #0xNN000 */
2210 0xe5bcf000, /* ldr pc, [ip, #0xNNN]! */
2211};
5e681ec4 2212
1db37fe6
YG		 2213/* When explicitly asked, we'll use this "long" entry format
2214 which can cope with arbitrary displacements. */
2215static const bfd_vma elf32_arm_plt_entry_long [] =
2216{
2217 0xe28fc200, /* add ip, pc, #0xN0000000 */
2218 0xe28cc600, /* add ip, ip, #0xNN00000 */
2219 0xe28cca00, /* add ip, ip, #0xNN000 */
2220 0xe5bcf000, /* ldr pc, [ip, #0xNNN]! */
2221};
2222
2223static bfd_boolean elf32_arm_use_long_plt_entry = FALSE;
2224
eed94f8f
NC		 2225#endif /* not FOUR_WORD_PLT */
2226
2227/* The first entry in a procedure linkage table looks like this.
2228 It is set up so that any shared library function that is called before the
2229 relocation has been set up calls the dynamic linker first. */
2230static const bfd_vma elf32_thumb2_plt0_entry [] =
2231{
2232 /* NOTE: As this is a mixture of 16-bit and 32-bit instructions,
2233 an instruction maybe encoded to one or two array elements. */
2234 0xf8dfb500, /* push {lr} */
2235 0x44fee008, /* ldr.w lr, [pc, #8] */
469a3493 2236 /* add lr, pc */
eed94f8f
NC		 2237 0xff08f85e, /* ldr.w pc, [lr, #8]! */
2238 0x00000000, /* &GOT[0] - . */
2239};
2240
2241/* Subsequent entries in a procedure linkage table for thumb only target
2242 look like this. */
2243static const bfd_vma elf32_thumb2_plt_entry [] =
2244{
2245 /* NOTE: As this is a mixture of 16-bit and 32-bit instructions,
2246 an instruction maybe encoded to one or two array elements. */
2247 0x0c00f240, /* movw ip, #0xNNNN */
2248 0x0c00f2c0, /* movt ip, #0xNNNN */
2249 0xf8dc44fc, /* add ip, pc */
2250 0xbf00f000 /* ldr.w pc, [ip] */
469a3493 2251 /* nop */
eed94f8f 2252};
252b5132 2253
00a97672
RS		 2254/* The format of the first entry in the procedure linkage table
2255 for a VxWorks executable. */
2256static const bfd_vma elf32_arm_vxworks_exec_plt0_entry[] =
b38cadfb
NC		 2257{
2258 0xe52dc008, /* str ip,[sp,#-8]! */
2259 0xe59fc000, /* ldr ip,[pc] */
2260 0xe59cf008, /* ldr pc,[ip,#8] */
2261 0x00000000, /* .long _GLOBAL_OFFSET_TABLE_ */
2262};
00a97672
RS		 2263
2264/* The format of subsequent entries in a VxWorks executable. */
2265static const bfd_vma elf32_arm_vxworks_exec_plt_entry[] =
b38cadfb
NC		 2266{
2267 0xe59fc000, /* ldr ip,[pc] */
2268 0xe59cf000, /* ldr pc,[ip] */
2269 0x00000000, /* .long @got */
2270 0xe59fc000, /* ldr ip,[pc] */
2271 0xea000000, /* b _PLT */
2272 0x00000000, /* .long @pltindex*sizeof(Elf32_Rela) */
2273};
00a97672
RS		 2274
2275/* The format of entries in a VxWorks shared library. */
2276static const bfd_vma elf32_arm_vxworks_shared_plt_entry[] =
b38cadfb
NC		 2277{
2278 0xe59fc000, /* ldr ip,[pc] */
2279 0xe79cf009, /* ldr pc,[ip,r9] */
2280 0x00000000, /* .long @got */
2281 0xe59fc000, /* ldr ip,[pc] */
2282 0xe599f008, /* ldr pc,[r9,#8] */
2283 0x00000000, /* .long @pltindex*sizeof(Elf32_Rela) */
2284};
00a97672 2285
b7693d02
DJ		 2286/* An initial stub used if the PLT entry is referenced from Thumb code. */
2287#define PLT_THUMB_STUB_SIZE 4
2288static const bfd_vma elf32_arm_plt_thumb_stub [] =
b38cadfb
NC		 2289{
2290 0x4778, /* bx pc */
2291 0x46c0 /* nop */
2292};
b7693d02 2293
e5a52504
MM		 2294/* The entries in a PLT when using a DLL-based target with multiple
2295 address spaces. */
906e58ca 2296static const bfd_vma elf32_arm_symbian_plt_entry [] =
b38cadfb
NC		 2297{
2298 0xe51ff004, /* ldr pc, [pc, #-4] */
2299 0x00000000, /* dcd R_ARM_GLOB_DAT(X) */
2300};
2301
2302/* The first entry in a procedure linkage table looks like
2303 this. It is set up so that any shared library function that is
2304 called before the relocation has been set up calls the dynamic
2305 linker first. */
2306static const bfd_vma elf32_arm_nacl_plt0_entry [] =
2307{
2308 /* First bundle: */
2309 0xe300c000, /* movw ip, #:lower16:&GOT[2]-.+8 */
2310 0xe340c000, /* movt ip, #:upper16:&GOT[2]-.+8 */
2311 0xe08cc00f, /* add ip, ip, pc */
2312 0xe52dc008, /* str ip, [sp, #-8]! */
2313 /* Second bundle: */
edccdf7c
RM		 2314 0xe3ccc103, /* bic ip, ip, #0xc0000000 */
2315 0xe59cc000, /* ldr ip, [ip] */
b38cadfb 2316 0xe3ccc13f, /* bic ip, ip, #0xc000000f */
edccdf7c 2317 0xe12fff1c, /* bx ip */
b38cadfb 2318 /* Third bundle: */
edccdf7c
RM		 2319 0xe320f000, /* nop */
2320 0xe320f000, /* nop */
2321 0xe320f000, /* nop */
b38cadfb
NC		 2322 /* .Lplt_tail: */
2323 0xe50dc004, /* str ip, [sp, #-4] */
2324 /* Fourth bundle: */
edccdf7c
RM		 2325 0xe3ccc103, /* bic ip, ip, #0xc0000000 */
2326 0xe59cc000, /* ldr ip, [ip] */
b38cadfb 2327 0xe3ccc13f, /* bic ip, ip, #0xc000000f */
edccdf7c 2328 0xe12fff1c, /* bx ip */
b38cadfb
NC		 2329};
2330#define ARM_NACL_PLT_TAIL_OFFSET (11 * 4)
2331
2332/* Subsequent entries in a procedure linkage table look like this. */
2333static const bfd_vma elf32_arm_nacl_plt_entry [] =
2334{
2335 0xe300c000, /* movw ip, #:lower16:&GOT[n]-.+8 */
2336 0xe340c000, /* movt ip, #:upper16:&GOT[n]-.+8 */
2337 0xe08cc00f, /* add ip, ip, pc */
2338 0xea000000, /* b .Lplt_tail */
2339};
e5a52504 2340
906e58ca
NC		 2341#define ARM_MAX_FWD_BRANCH_OFFSET ((((1 << 23) - 1) << 2) + 8)
2342#define ARM_MAX_BWD_BRANCH_OFFSET ((-((1 << 23) << 2)) + 8)
2343#define THM_MAX_FWD_BRANCH_OFFSET ((1 << 22) -2 + 4)
2344#define THM_MAX_BWD_BRANCH_OFFSET (-(1 << 22) + 4)
2345#define THM2_MAX_FWD_BRANCH_OFFSET (((1 << 24) - 2) + 4)
2346#define THM2_MAX_BWD_BRANCH_OFFSET (-(1 << 24) + 4)
c5423981
TG		 2347#define THM2_MAX_FWD_COND_BRANCH_OFFSET (((1 << 20) -2) + 4)
2348#define THM2_MAX_BWD_COND_BRANCH_OFFSET (-(1 << 20) + 4)
906e58ca 2349
461a49ca 2350enum stub_insn_type
b38cadfb
NC		 2351{
2352 THUMB16_TYPE = 1,
2353 THUMB32_TYPE,
2354 ARM_TYPE,
2355 DATA_TYPE
2356};
461a49ca 2357
48229727
JB		 2358#define THUMB16_INSN(X) {(X), THUMB16_TYPE, R_ARM_NONE, 0}
2359/* A bit of a hack. A Thumb conditional branch, in which the proper condition
2360 is inserted in arm_build_one_stub(). */
2361#define THUMB16_BCOND_INSN(X) {(X), THUMB16_TYPE, R_ARM_NONE, 1}
2362#define THUMB32_INSN(X) {(X), THUMB32_TYPE, R_ARM_NONE, 0}
2363#define THUMB32_B_INSN(X, Z) {(X), THUMB32_TYPE, R_ARM_THM_JUMP24, (Z)}
2364#define ARM_INSN(X) {(X), ARM_TYPE, R_ARM_NONE, 0}
2365#define ARM_REL_INSN(X, Z) {(X), ARM_TYPE, R_ARM_JUMP24, (Z)}
2366#define DATA_WORD(X,Y,Z) {(X), DATA_TYPE, (Y), (Z)}
461a49ca
DJ		 2367
2368typedef struct
2369{
b38cadfb
NC		 2370 bfd_vma data;
2371 enum stub_insn_type type;
2372 unsigned int r_type;
2373 int reloc_addend;
461a49ca
DJ		 2374} insn_sequence;
2375
fea2b4d6
CL		 2376/* Arm/Thumb -> Arm/Thumb long branch stub. On V5T and above, use blx
2377 to reach the stub if necessary. */
461a49ca 2378static const insn_sequence elf32_arm_stub_long_branch_any_any[] =
b38cadfb
NC		 2379{
2380 ARM_INSN (0xe51ff004), /* ldr pc, [pc, #-4] */
2381 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(X) */
2382};
906e58ca 2383
fea2b4d6
CL		 2384/* V4T Arm -> Thumb long branch stub. Used on V4T where blx is not
2385 available. */
461a49ca 2386static const insn_sequence elf32_arm_stub_long_branch_v4t_arm_thumb[] =
b38cadfb
NC		 2387{
2388 ARM_INSN (0xe59fc000), /* ldr ip, [pc, #0] */
2389 ARM_INSN (0xe12fff1c), /* bx ip */
2390 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(X) */
2391};
906e58ca 2392
d3626fb0 2393/* Thumb -> Thumb long branch stub. Used on M-profile architectures. */
461a49ca 2394static const insn_sequence elf32_arm_stub_long_branch_thumb_only[] =
b38cadfb
NC		 2395{
2396 THUMB16_INSN (0xb401), /* push {r0} */
2397 THUMB16_INSN (0x4802), /* ldr r0, [pc, #8] */
2398 THUMB16_INSN (0x4684), /* mov ip, r0 */
2399 THUMB16_INSN (0xbc01), /* pop {r0} */
2400 THUMB16_INSN (0x4760), /* bx ip */
2401 THUMB16_INSN (0xbf00), /* nop */
2402 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(X) */
2403};
906e58ca 2404
d3626fb0
CL		 2405/* V4T Thumb -> Thumb long branch stub. Using the stack is not
2406 allowed. */
2407static const insn_sequence elf32_arm_stub_long_branch_v4t_thumb_thumb[] =
b38cadfb
NC		 2408{
2409 THUMB16_INSN (0x4778), /* bx pc */
2410 THUMB16_INSN (0x46c0), /* nop */
2411 ARM_INSN (0xe59fc000), /* ldr ip, [pc, #0] */
2412 ARM_INSN (0xe12fff1c), /* bx ip */
2413 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(X) */
2414};
d3626fb0 2415
fea2b4d6
CL		 2416/* V4T Thumb -> ARM long branch stub. Used on V4T where blx is not
2417 available. */
461a49ca 2418static const insn_sequence elf32_arm_stub_long_branch_v4t_thumb_arm[] =
b38cadfb
NC		 2419{
2420 THUMB16_INSN (0x4778), /* bx pc */
2421 THUMB16_INSN (0x46c0), /* nop */
2422 ARM_INSN (0xe51ff004), /* ldr pc, [pc, #-4] */
2423 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(X) */
2424};
906e58ca 2425
fea2b4d6
CL		 2426/* V4T Thumb -> ARM short branch stub. Shorter variant of the above
2427 one, when the destination is close enough. */
461a49ca 2428static const insn_sequence elf32_arm_stub_short_branch_v4t_thumb_arm[] =
b38cadfb
NC		 2429{
2430 THUMB16_INSN (0x4778), /* bx pc */
2431 THUMB16_INSN (0x46c0), /* nop */
2432 ARM_REL_INSN (0xea000000, -8), /* b (X-8) */
2433};
c820be07 2434
cf3eccff 2435/* ARM/Thumb -> ARM long branch stub, PIC. On V5T and above, use
fea2b4d6 2436 blx to reach the stub if necessary. */
cf3eccff 2437static const insn_sequence elf32_arm_stub_long_branch_any_arm_pic[] =
b38cadfb
NC		 2438{
2439 ARM_INSN (0xe59fc000), /* ldr ip, [pc] */
2440 ARM_INSN (0xe08ff00c), /* add pc, pc, ip */
2441 DATA_WORD (0, R_ARM_REL32, -4), /* dcd R_ARM_REL32(X-4) */
2442};
906e58ca 2443
cf3eccff
DJ		 2444/* ARM/Thumb -> Thumb long branch stub, PIC. On V5T and above, use
2445 blx to reach the stub if necessary. We can not add into pc;
2446 it is not guaranteed to mode switch (different in ARMv6 and
2447 ARMv7). */
2448static const insn_sequence elf32_arm_stub_long_branch_any_thumb_pic[] =
b38cadfb
NC		 2449{
2450 ARM_INSN (0xe59fc004), /* ldr ip, [pc, #4] */
2451 ARM_INSN (0xe08fc00c), /* add ip, pc, ip */
2452 ARM_INSN (0xe12fff1c), /* bx ip */
2453 DATA_WORD (0, R_ARM_REL32, 0), /* dcd R_ARM_REL32(X) */
2454};
cf3eccff 2455
ebe24dd4
CL		 2456/* V4T ARM -> ARM long branch stub, PIC. */
2457static const insn_sequence elf32_arm_stub_long_branch_v4t_arm_thumb_pic[] =
b38cadfb
NC		 2458{
2459 ARM_INSN (0xe59fc004), /* ldr ip, [pc, #4] */
2460 ARM_INSN (0xe08fc00c), /* add ip, pc, ip */
2461 ARM_INSN (0xe12fff1c), /* bx ip */
2462 DATA_WORD (0, R_ARM_REL32, 0), /* dcd R_ARM_REL32(X) */
2463};
ebe24dd4
CL		 2464
2465/* V4T Thumb -> ARM long branch stub, PIC. */
2466static const insn_sequence elf32_arm_stub_long_branch_v4t_thumb_arm_pic[] =
b38cadfb
NC		 2467{
2468 THUMB16_INSN (0x4778), /* bx pc */
2469 THUMB16_INSN (0x46c0), /* nop */
2470 ARM_INSN (0xe59fc000), /* ldr ip, [pc, #0] */
2471 ARM_INSN (0xe08cf00f), /* add pc, ip, pc */
2472 DATA_WORD (0, R_ARM_REL32, -4), /* dcd R_ARM_REL32(X) */
2473};
ebe24dd4 2474
d3626fb0
CL		 2475/* Thumb -> Thumb long branch stub, PIC. Used on M-profile
2476 architectures. */
ebe24dd4 2477static const insn_sequence elf32_arm_stub_long_branch_thumb_only_pic[] =
b38cadfb
NC		 2478{
2479 THUMB16_INSN (0xb401), /* push {r0} */
2480 THUMB16_INSN (0x4802), /* ldr r0, [pc, #8] */
2481 THUMB16_INSN (0x46fc), /* mov ip, pc */
2482 THUMB16_INSN (0x4484), /* add ip, r0 */
2483 THUMB16_INSN (0xbc01), /* pop {r0} */
2484 THUMB16_INSN (0x4760), /* bx ip */
2485 DATA_WORD (0, R_ARM_REL32, 4), /* dcd R_ARM_REL32(X) */
2486};
ebe24dd4 2487
d3626fb0
CL		 2488/* V4T Thumb -> Thumb long branch stub, PIC. Using the stack is not
2489 allowed. */
2490static const insn_sequence elf32_arm_stub_long_branch_v4t_thumb_thumb_pic[] =
b38cadfb
NC		 2491{
2492 THUMB16_INSN (0x4778), /* bx pc */
2493 THUMB16_INSN (0x46c0), /* nop */
2494 ARM_INSN (0xe59fc004), /* ldr ip, [pc, #4] */
2495 ARM_INSN (0xe08fc00c), /* add ip, pc, ip */
2496 ARM_INSN (0xe12fff1c), /* bx ip */
2497 DATA_WORD (0, R_ARM_REL32, 0), /* dcd R_ARM_REL32(X) */
2498};
d3626fb0 2499
0855e32b
NS		 2500/* Thumb2/ARM -> TLS trampoline. Lowest common denominator, which is a
2501 long PIC stub. We can use r1 as a scratch -- and cannot use ip. */
2502static const insn_sequence elf32_arm_stub_long_branch_any_tls_pic[] =
2503{
b38cadfb
NC		 2504 ARM_INSN (0xe59f1000), /* ldr r1, [pc] */
2505 ARM_INSN (0xe08ff001), /* add pc, pc, r1 */
2506 DATA_WORD (0, R_ARM_REL32, -4), /* dcd R_ARM_REL32(X-4) */
0855e32b
NS		 2507};
2508
2509/* V4T Thumb -> TLS trampoline. lowest common denominator, which is a
2510 long PIC stub. We can use r1 as a scratch -- and cannot use ip. */
2511static const insn_sequence elf32_arm_stub_long_branch_v4t_thumb_tls_pic[] =
2512{
b38cadfb
NC		 2513 THUMB16_INSN (0x4778), /* bx pc */
2514 THUMB16_INSN (0x46c0), /* nop */
2515 ARM_INSN (0xe59f1000), /* ldr r1, [pc, #0] */
2516 ARM_INSN (0xe081f00f), /* add pc, r1, pc */
2517 DATA_WORD (0, R_ARM_REL32, -4), /* dcd R_ARM_REL32(X) */
0855e32b
NS		 2518};
2519
7a89b94e
NC		 2520/* NaCl ARM -> ARM long branch stub. */
2521static const insn_sequence elf32_arm_stub_long_branch_arm_nacl[] =
2522{
2523 ARM_INSN (0xe59fc00c), /* ldr ip, [pc, #12] */
2524 ARM_INSN (0xe3ccc13f), /* bic ip, ip, #0xc000000f */
2525 ARM_INSN (0xe12fff1c), /* bx ip */
2526 ARM_INSN (0xe320f000), /* nop */
2527 ARM_INSN (0xe125be70), /* bkpt 0x5be0 */
2528 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(X) */
2529 DATA_WORD (0, R_ARM_NONE, 0), /* .word 0 */
2530 DATA_WORD (0, R_ARM_NONE, 0), /* .word 0 */
2531};
2532
2533/* NaCl ARM -> ARM long branch stub, PIC. */
2534static const insn_sequence elf32_arm_stub_long_branch_arm_nacl_pic[] =
2535{
2536 ARM_INSN (0xe59fc00c), /* ldr ip, [pc, #12] */
2537 ARM_INSN (0xe08cc00f), /* add ip, ip, pc */
2538 ARM_INSN (0xe3ccc13f), /* bic ip, ip, #0xc000000f */
2539 ARM_INSN (0xe12fff1c), /* bx ip */
2540 ARM_INSN (0xe125be70), /* bkpt 0x5be0 */
2541 DATA_WORD (0, R_ARM_REL32, 8), /* dcd R_ARM_REL32(X+8) */
2542 DATA_WORD (0, R_ARM_NONE, 0), /* .word 0 */
2543 DATA_WORD (0, R_ARM_NONE, 0), /* .word 0 */
2544};
2545
2546
48229727
JB		 2547/* Cortex-A8 erratum-workaround stubs. */
2548
2549/* Stub used for conditional branches (which may be beyond +/-1MB away, so we
2550 can't use a conditional branch to reach this stub). */
2551
2552static const insn_sequence elf32_arm_stub_a8_veneer_b_cond[] =
b38cadfb
NC		 2553{
2554 THUMB16_BCOND_INSN (0xd001), /* b<cond>.n true. */
2555 THUMB32_B_INSN (0xf000b800, -4), /* b.w insn_after_original_branch. */
2556 THUMB32_B_INSN (0xf000b800, -4) /* true: b.w original_branch_dest. */
2557};
48229727
JB		 2558
2559/* Stub used for b.w and bl.w instructions. */
2560
2561static const insn_sequence elf32_arm_stub_a8_veneer_b[] =
b38cadfb
NC		 2562{
2563 THUMB32_B_INSN (0xf000b800, -4) /* b.w original_branch_dest. */
2564};
48229727
JB		 2565
2566static const insn_sequence elf32_arm_stub_a8_veneer_bl[] =
b38cadfb
NC		 2567{
2568 THUMB32_B_INSN (0xf000b800, -4) /* b.w original_branch_dest. */
2569};
48229727
JB		 2570
2571/* Stub used for Thumb-2 blx.w instructions. We modified the original blx.w
2572 instruction (which switches to ARM mode) to point to this stub. Jump to the
2573 real destination using an ARM-mode branch. */
2574
2575static const insn_sequence elf32_arm_stub_a8_veneer_blx[] =
b38cadfb
NC		 2576{
2577 ARM_REL_INSN (0xea000000, -8) /* b original_branch_dest. */
2578};
48229727 2579
9553db3c
NC		 2580/* For each section group there can be a specially created linker section
2581 to hold the stubs for that group. The name of the stub section is based
2582 upon the name of another section within that group with the suffix below
2583 applied.
2584
2585 PR 13049: STUB_SUFFIX used to be ".stub", but this allowed the user to
2586 create what appeared to be a linker stub section when it actually
2587 contained user code/data. For example, consider this fragment:
b38cadfb 2588
9553db3c
NC		 2589 const char * stubborn_problems[] = { "np" };
2590
2591 If this is compiled with "-fPIC -fdata-sections" then gcc produces a
2592 section called:
2593
2594 .data.rel.local.stubborn_problems
2595
2596 This then causes problems in arm32_arm_build_stubs() as it triggers:
2597
2598 // Ignore non-stub sections.
2599 if (!strstr (stub_sec->name, STUB_SUFFIX))
2600 continue;
2601
2602 And so the section would be ignored instead of being processed. Hence
2603 the change in definition of STUB_SUFFIX to a name that cannot be a valid
2604 C identifier. */
2605#define STUB_SUFFIX ".__stub"
906e58ca 2606
738a79f6
CL		 2607/* One entry per long/short branch stub defined above. */
2608#define DEF_STUBS \
2609 DEF_STUB(long_branch_any_any) \
2610 DEF_STUB(long_branch_v4t_arm_thumb) \
2611 DEF_STUB(long_branch_thumb_only) \
2612 DEF_STUB(long_branch_v4t_thumb_thumb) \
2613 DEF_STUB(long_branch_v4t_thumb_arm) \
2614 DEF_STUB(short_branch_v4t_thumb_arm) \
2615 DEF_STUB(long_branch_any_arm_pic) \
2616 DEF_STUB(long_branch_any_thumb_pic) \
2617 DEF_STUB(long_branch_v4t_thumb_thumb_pic) \
2618 DEF_STUB(long_branch_v4t_arm_thumb_pic) \
2619 DEF_STUB(long_branch_v4t_thumb_arm_pic) \
48229727 2620 DEF_STUB(long_branch_thumb_only_pic) \
0855e32b
NS		 2621 DEF_STUB(long_branch_any_tls_pic) \
2622 DEF_STUB(long_branch_v4t_thumb_tls_pic) \
7a89b94e
NC		 2623 DEF_STUB(long_branch_arm_nacl) \
2624 DEF_STUB(long_branch_arm_nacl_pic) \
48229727
JB		 2625 DEF_STUB(a8_veneer_b_cond) \
2626 DEF_STUB(a8_veneer_b) \
2627 DEF_STUB(a8_veneer_bl) \
2628 DEF_STUB(a8_veneer_blx)
738a79f6
CL		 2629
2630#define DEF_STUB(x) arm_stub_##x,
b38cadfb
NC		 2631enum elf32_arm_stub_type
2632{
906e58ca 2633 arm_stub_none,
738a79f6 2634 DEF_STUBS
6a631e86 2635 /* Note the first a8_veneer type. */
eb7c4339 2636 arm_stub_a8_veneer_lwm = arm_stub_a8_veneer_b_cond
738a79f6
CL		 2637};
2638#undef DEF_STUB
2639
2640typedef struct
2641{
d3ce72d0 2642 const insn_sequence* template_sequence;
738a79f6
CL		 2643 int template_size;
2644} stub_def;
2645
2646#define DEF_STUB(x) {elf32_arm_stub_##x, ARRAY_SIZE(elf32_arm_stub_##x)},
b38cadfb
NC		 2647static const stub_def stub_definitions[] =
2648{
738a79f6
CL		 2649 {NULL, 0},
2650 DEF_STUBS
906e58ca
NC		 2651};
2652
2653struct elf32_arm_stub_hash_entry
2654{
2655 /* Base hash table entry structure. */
2656 struct bfd_hash_entry root;
2657
2658 /* The stub section. */
2659 asection *stub_sec;
2660
2661 /* Offset within stub_sec of the beginning of this stub. */
2662 bfd_vma stub_offset;
2663
2664 /* Given the symbol's value and its section we can determine its final
2665 value when building the stubs (so the stub knows where to jump). */
2666 bfd_vma target_value;
2667 asection *target_section;
2668
48229727
JB		 2669 /* Offset to apply to relocation referencing target_value. */
2670 bfd_vma target_addend;
2671
2672 /* The instruction which caused this stub to be generated (only valid for
2673 Cortex-A8 erratum workaround stubs at present). */
2674 unsigned long orig_insn;
2675
461a49ca 2676 /* The stub type. */
906e58ca 2677 enum elf32_arm_stub_type stub_type;
461a49ca
DJ		 2678 /* Its encoding size in bytes. */
2679 int stub_size;
2680 /* Its template. */
2681 const insn_sequence *stub_template;
2682 /* The size of the template (number of entries). */
2683 int stub_template_size;
906e58ca
NC		 2684
2685 /* The symbol table entry, if any, that this was derived from. */
2686 struct elf32_arm_link_hash_entry *h;
2687
35fc36a8
RS		 2688 /* Type of branch. */
2689 enum arm_st_branch_type branch_type;
906e58ca
NC		 2690
2691 /* Where this stub is being called from, or, in the case of combined
2692 stub sections, the first input section in the group. */
2693 asection *id_sec;
7413f23f
DJ		 2694
2695 /* The name for the local symbol at the start of this stub. The
2696 stub name in the hash table has to be unique; this does not, so
2697 it can be friendlier. */
2698 char *output_name;
906e58ca
NC		 2699};
2700
e489d0ae
PB		 2701/* Used to build a map of a section. This is required for mixed-endian
2702 code/data. */
2703
2704typedef struct elf32_elf_section_map
2705{
2706 bfd_vma vma;
2707 char type;
2708}
2709elf32_arm_section_map;
2710
c7b8f16e
JB		 2711/* Information about a VFP11 erratum veneer, or a branch to such a veneer. */
2712
2713typedef enum
2714{
2715 VFP11_ERRATUM_BRANCH_TO_ARM_VENEER,
2716 VFP11_ERRATUM_BRANCH_TO_THUMB_VENEER,
2717 VFP11_ERRATUM_ARM_VENEER,
2718 VFP11_ERRATUM_THUMB_VENEER
2719}
2720elf32_vfp11_erratum_type;
2721
2722typedef struct elf32_vfp11_erratum_list
2723{
2724 struct elf32_vfp11_erratum_list *next;
2725 bfd_vma vma;
2726 union
2727 {
2728 struct
2729 {
2730 struct elf32_vfp11_erratum_list *veneer;
2731 unsigned int vfp_insn;
2732 } b;
2733 struct
2734 {
2735 struct elf32_vfp11_erratum_list *branch;
2736 unsigned int id;
2737 } v;
2738 } u;
2739 elf32_vfp11_erratum_type type;
2740}
2741elf32_vfp11_erratum_list;
2742
a504d23a
LA		 2743/* Information about a STM32L4XX erratum veneer, or a branch to such a
2744 veneer. */
2745typedef enum
2746{
2747 STM32L4XX_ERRATUM_BRANCH_TO_VENEER,
2748 STM32L4XX_ERRATUM_VENEER
2749}
2750elf32_stm32l4xx_erratum_type;
2751
2752typedef struct elf32_stm32l4xx_erratum_list
2753{
2754 struct elf32_stm32l4xx_erratum_list *next;
2755 bfd_vma vma;
2756 union
2757 {
2758 struct
2759 {
2760 struct elf32_stm32l4xx_erratum_list *veneer;
2761 unsigned int insn;
2762 } b;
2763 struct
2764 {
2765 struct elf32_stm32l4xx_erratum_list *branch;
2766 unsigned int id;
2767 } v;
2768 } u;
2769 elf32_stm32l4xx_erratum_type type;
2770}
2771elf32_stm32l4xx_erratum_list;
2772
2468f9c9
PB		 2773typedef enum
2774{
2775 DELETE_EXIDX_ENTRY,
2776 INSERT_EXIDX_CANTUNWIND_AT_END
2777}
2778arm_unwind_edit_type;
2779
2780/* A (sorted) list of edits to apply to an unwind table. */
2781typedef struct arm_unwind_table_edit
2782{
2783 arm_unwind_edit_type type;
2784 /* Note: we sometimes want to insert an unwind entry corresponding to a
2785 section different from the one we're currently writing out, so record the
2786 (text) section this edit relates to here. */
2787 asection *linked_section;
2788 unsigned int index;
2789 struct arm_unwind_table_edit *next;
2790}
2791arm_unwind_table_edit;
2792
8e3de13a 2793typedef struct _arm_elf_section_data
e489d0ae 2794{
2468f9c9 2795 /* Information about mapping symbols. */
e489d0ae 2796 struct bfd_elf_section_data elf;
8e3de13a 2797 unsigned int mapcount;
c7b8f16e 2798 unsigned int mapsize;
e489d0ae 2799 elf32_arm_section_map *map;
2468f9c9 2800 /* Information about CPU errata. */
c7b8f16e
JB		 2801 unsigned int erratumcount;
2802 elf32_vfp11_erratum_list *erratumlist;
a504d23a
LA		 2803 unsigned int stm32l4xx_erratumcount;
2804 elf32_stm32l4xx_erratum_list *stm32l4xx_erratumlist;
491d01d3 2805 unsigned int additional_reloc_count;
2468f9c9
PB		 2806 /* Information about unwind tables. */
2807 union
2808 {
2809 /* Unwind info attached to a text section. */
2810 struct
2811 {
2812 asection *arm_exidx_sec;
2813 } text;
2814
2815 /* Unwind info attached to an .ARM.exidx section. */
2816 struct
2817 {
2818 arm_unwind_table_edit *unwind_edit_list;
2819 arm_unwind_table_edit *unwind_edit_tail;
2820 } exidx;
2821 } u;
8e3de13a
NC		 2822}
2823_arm_elf_section_data;
e489d0ae
PB		 2824
2825#define elf32_arm_section_data(sec) \
8e3de13a 2826 ((_arm_elf_section_data *) elf_section_data (sec))
e489d0ae 2827
48229727
JB		 2828/* A fix which might be required for Cortex-A8 Thumb-2 branch/TLB erratum.
2829 These fixes are subject to a relaxation procedure (in elf32_arm_size_stubs),
2830 so may be created multiple times: we use an array of these entries whilst
2831 relaxing which we can refresh easily, then create stubs for each potentially
2832 erratum-triggering instruction once we've settled on a solution. */
2833
b38cadfb
NC		 2834struct a8_erratum_fix
2835{
48229727
JB		 2836 bfd *input_bfd;
2837 asection *section;
2838 bfd_vma offset;
2839 bfd_vma addend;
2840 unsigned long orig_insn;
2841 char *stub_name;
2842 enum elf32_arm_stub_type stub_type;
35fc36a8 2843 enum arm_st_branch_type branch_type;
48229727
JB		 2844};
2845
2846/* A table of relocs applied to branches which might trigger Cortex-A8
2847 erratum. */
2848
b38cadfb
NC		 2849struct a8_erratum_reloc
2850{
48229727
JB		 2851 bfd_vma from;
2852 bfd_vma destination;
92750f34
DJ		 2853 struct elf32_arm_link_hash_entry *hash;
2854 const char *sym_name;
48229727 2855 unsigned int r_type;
35fc36a8 2856 enum arm_st_branch_type branch_type;
48229727
JB		 2857 bfd_boolean non_a8_stub;
2858};
2859
ba93b8ac
DJ		 2860/* The size of the thread control block. */
2861#define TCB_SIZE 8
2862
34e77a92
RS		 2863/* ARM-specific information about a PLT entry, over and above the usual
2864 gotplt_union. */
b38cadfb
NC		 2865struct arm_plt_info
2866{
34e77a92
RS		 2867 /* We reference count Thumb references to a PLT entry separately,
2868 so that we can emit the Thumb trampoline only if needed. */
2869 bfd_signed_vma thumb_refcount;
2870
2871 /* Some references from Thumb code may be eliminated by BL->BLX
2872 conversion, so record them separately. */
2873 bfd_signed_vma maybe_thumb_refcount;
2874
2875 /* How many of the recorded PLT accesses were from non-call relocations.
2876 This information is useful when deciding whether anything takes the
2877 address of an STT_GNU_IFUNC PLT. A value of 0 means that all
2878 non-call references to the function should resolve directly to the
2879 real runtime target. */
2880 unsigned int noncall_refcount;
2881
2882 /* Since PLT entries have variable size if the Thumb prologue is
2883 used, we need to record the index into .got.plt instead of
2884 recomputing it from the PLT offset. */
2885 bfd_signed_vma got_offset;
2886};
2887
2888/* Information about an .iplt entry for a local STT_GNU_IFUNC symbol. */
b38cadfb
NC		 2889struct arm_local_iplt_info
2890{
34e77a92
RS		 2891 /* The information that is usually found in the generic ELF part of
2892 the hash table entry. */
2893 union gotplt_union root;
2894
2895 /* The information that is usually found in the ARM-specific part of
2896 the hash table entry. */
2897 struct arm_plt_info arm;
2898
2899 /* A list of all potential dynamic relocations against this symbol. */
2900 struct elf_dyn_relocs *dyn_relocs;
2901};
2902
0ffa91dd 2903struct elf_arm_obj_tdata
ba93b8ac
DJ		 2904{
2905 struct elf_obj_tdata root;
2906
2907 /* tls_type for each local got entry. */
2908 char *local_got_tls_type;
ee065d83 2909
0855e32b
NS		 2910 /* GOTPLT entries for TLS descriptors. */
2911 bfd_vma *local_tlsdesc_gotent;
2912
34e77a92
RS		 2913 /* Information for local symbols that need entries in .iplt. */
2914 struct arm_local_iplt_info **local_iplt;
2915
bf21ed78
MS		 2916 /* Zero to warn when linking objects with incompatible enum sizes. */
2917 int no_enum_size_warning;
a9dc9481
JM		 2918
2919 /* Zero to warn when linking objects with incompatible wchar_t sizes. */
2920 int no_wchar_size_warning;
ba93b8ac
DJ		 2921};
2922
0ffa91dd
NC		 2923#define elf_arm_tdata(bfd) \
2924 ((struct elf_arm_obj_tdata *) (bfd)->tdata.any)
ba93b8ac 2925
0ffa91dd
NC		 2926#define elf32_arm_local_got_tls_type(bfd) \
2927 (elf_arm_tdata (bfd)->local_got_tls_type)
2928
0855e32b
NS		 2929#define elf32_arm_local_tlsdesc_gotent(bfd) \
2930 (elf_arm_tdata (bfd)->local_tlsdesc_gotent)
2931
34e77a92
RS		 2932#define elf32_arm_local_iplt(bfd) \
2933 (elf_arm_tdata (bfd)->local_iplt)
2934
0ffa91dd
NC		 2935#define is_arm_elf(bfd) \
2936 (bfd_get_flavour (bfd) == bfd_target_elf_flavour \
2937 && elf_tdata (bfd) != NULL \
4dfe6ac6 2938 && elf_object_id (bfd) == ARM_ELF_DATA)
ba93b8ac
DJ		 2939
2940static bfd_boolean
2941elf32_arm_mkobject (bfd *abfd)
2942{
0ffa91dd 2943 return bfd_elf_allocate_object (abfd, sizeof (struct elf_arm_obj_tdata),
4dfe6ac6 2944 ARM_ELF_DATA);
ba93b8ac
DJ		 2945}
2946
ba93b8ac
DJ		 2947#define elf32_arm_hash_entry(ent) ((struct elf32_arm_link_hash_entry *)(ent))
2948
ba96a88f 2949/* Arm ELF linker hash entry. */
252b5132 2950struct elf32_arm_link_hash_entry
b38cadfb
NC		 2951{
2952 struct elf_link_hash_entry root;
252b5132 2953
b38cadfb
NC		 2954 /* Track dynamic relocs copied for this symbol. */
2955 struct elf_dyn_relocs *dyn_relocs;
b7693d02 2956
b38cadfb
NC		 2957 /* ARM-specific PLT information. */
2958 struct arm_plt_info plt;
ba93b8ac
DJ		 2959
2960#define GOT_UNKNOWN 0
2961#define GOT_NORMAL 1
2962#define GOT_TLS_GD 2
2963#define GOT_TLS_IE 4
0855e32b
NS		 2964#define GOT_TLS_GDESC 8
2965#define GOT_TLS_GD_ANY_P(type) ((type & GOT_TLS_GD) || (type & GOT_TLS_GDESC))
b38cadfb 2966 unsigned int tls_type : 8;
34e77a92 2967
b38cadfb
NC		 2968 /* True if the symbol's PLT entry is in .iplt rather than .plt. */
2969 unsigned int is_iplt : 1;
34e77a92 2970
b38cadfb 2971 unsigned int unused : 23;
a4fd1a8e 2972
b38cadfb
NC		 2973 /* Offset of the GOTPLT entry reserved for the TLS descriptor,
2974 starting at the end of the jump table. */
2975 bfd_vma tlsdesc_got;
0855e32b 2976
b38cadfb
NC		 2977 /* The symbol marking the real symbol location for exported thumb
2978 symbols with Arm stubs. */
2979 struct elf_link_hash_entry *export_glue;
906e58ca 2980
b38cadfb 2981 /* A pointer to the most recently used stub hash entry against this
8029a119 2982 symbol. */
b38cadfb
NC		 2983 struct elf32_arm_stub_hash_entry *stub_cache;
2984};
252b5132 2985
252b5132 2986/* Traverse an arm ELF linker hash table. */
252b5132
RH		 2987#define elf32_arm_link_hash_traverse(table, func, info) \
2988 (elf_link_hash_traverse \
2989 (&(table)->root, \
b7693d02 2990 (bfd_boolean (*) (struct elf_link_hash_entry *, void *)) (func), \
252b5132
RH		 2991 (info)))
2992
2993/* Get the ARM elf linker hash table from a link_info structure. */
2994#define elf32_arm_hash_table(info) \
4dfe6ac6
NC		 2995 (elf_hash_table_id ((struct elf_link_hash_table *) ((info)->hash)) \
2996 == ARM_ELF_DATA ? ((struct elf32_arm_link_hash_table *) ((info)->hash)) : NULL)
252b5132 2997
906e58ca
NC		 2998#define arm_stub_hash_lookup(table, string, create, copy) \
2999 ((struct elf32_arm_stub_hash_entry *) \
3000 bfd_hash_lookup ((table), (string), (create), (copy)))
3001
21d799b5
NC		 3002/* Array to keep track of which stub sections have been created, and
3003 information on stub grouping. */
3004struct map_stub
3005{
3006 /* This is the section to which stubs in the group will be
3007 attached. */
3008 asection *link_sec;
3009 /* The stub section. */
3010 asection *stub_sec;
3011};
3012
0855e32b
NS		 3013#define elf32_arm_compute_jump_table_size(htab) \
3014 ((htab)->next_tls_desc_index * 4)
3015
9b485d32 3016/* ARM ELF linker hash table. */
252b5132 3017struct elf32_arm_link_hash_table
906e58ca
NC		 3018{
3019 /* The main hash table. */
3020 struct elf_link_hash_table root;
252b5132 3021
906e58ca
NC		 3022 /* The size in bytes of the section containing the Thumb-to-ARM glue. */
3023 bfd_size_type thumb_glue_size;
252b5132 3024
906e58ca
NC		 3025 /* The size in bytes of the section containing the ARM-to-Thumb glue. */
3026 bfd_size_type arm_glue_size;
252b5132 3027
906e58ca
NC		 3028 /* The size in bytes of section containing the ARMv4 BX veneers. */
3029 bfd_size_type bx_glue_size;
845b51d6 3030
906e58ca
NC		 3031 /* Offsets of ARMv4 BX veneers. Bit1 set if present, and Bit0 set when
3032 veneer has been populated. */
3033 bfd_vma bx_glue_offset[15];
845b51d6 3034
906e58ca
NC		 3035 /* The size in bytes of the section containing glue for VFP11 erratum
3036 veneers. */
3037 bfd_size_type vfp11_erratum_glue_size;
c7b8f16e 3038
a504d23a
LA		 3039 /* The size in bytes of the section containing glue for STM32L4XX erratum
3040 veneers. */
3041 bfd_size_type stm32l4xx_erratum_glue_size;
3042
48229727
JB		 3043 /* A table of fix locations for Cortex-A8 Thumb-2 branch/TLB erratum. This
3044 holds Cortex-A8 erratum fix locations between elf32_arm_size_stubs() and
3045 elf32_arm_write_section(). */
3046 struct a8_erratum_fix *a8_erratum_fixes;
3047 unsigned int num_a8_erratum_fixes;
3048
906e58ca
NC		 3049 /* An arbitrary input BFD chosen to hold the glue sections. */
3050 bfd * bfd_of_glue_owner;
ba96a88f 3051
906e58ca
NC		 3052 /* Nonzero to output a BE8 image. */
3053 int byteswap_code;
e489d0ae 3054
906e58ca
NC		 3055 /* Zero if R_ARM_TARGET1 means R_ARM_ABS32.
3056 Nonzero if R_ARM_TARGET1 means R_ARM_REL32. */
3057 int target1_is_rel;
9c504268 3058
906e58ca
NC		 3059 /* The relocation to use for R_ARM_TARGET2 relocations. */
3060 int target2_reloc;
eb043451 3061
906e58ca
NC		 3062 /* 0 = Ignore R_ARM_V4BX.
3063 1 = Convert BX to MOV PC.
3064 2 = Generate v4 interworing stubs. */
3065 int fix_v4bx;
319850b4 3066
48229727
JB		 3067 /* Whether we should fix the Cortex-A8 Thumb-2 branch/TLB erratum. */
3068 int fix_cortex_a8;
3069
2de70689
MGD		 3070 /* Whether we should fix the ARM1176 BLX immediate issue. */
3071 int fix_arm1176;
3072
906e58ca
NC		 3073 /* Nonzero if the ARM/Thumb BLX instructions are available for use. */
3074 int use_blx;
33bfe774 3075
906e58ca
NC		 3076 /* What sort of code sequences we should look for which may trigger the
3077 VFP11 denorm erratum. */
3078 bfd_arm_vfp11_fix vfp11_fix;
c7b8f16e 3079
906e58ca
NC		 3080 /* Global counter for the number of fixes we have emitted. */
3081 int num_vfp11_fixes;
c7b8f16e 3082
a504d23a
LA		 3083 /* What sort of code sequences we should look for which may trigger the
3084 STM32L4XX erratum. */
3085 bfd_arm_stm32l4xx_fix stm32l4xx_fix;
3086
3087 /* Global counter for the number of fixes we have emitted. */
3088 int num_stm32l4xx_fixes;
3089
906e58ca
NC		 3090 /* Nonzero to force PIC branch veneers. */
3091 int pic_veneer;
27e55c4d 3092
906e58ca
NC		 3093 /* The number of bytes in the initial entry in the PLT. */
3094 bfd_size_type plt_header_size;
e5a52504 3095
906e58ca
NC		 3096 /* The number of bytes in the subsequent PLT etries. */
3097 bfd_size_type plt_entry_size;
e5a52504 3098
906e58ca
NC		 3099 /* True if the target system is VxWorks. */
3100 int vxworks_p;
00a97672 3101
906e58ca
NC		 3102 /* True if the target system is Symbian OS. */
3103 int symbian_p;
e5a52504 3104
b38cadfb
NC		 3105 /* True if the target system is Native Client. */
3106 int nacl_p;
3107
906e58ca
NC		 3108 /* True if the target uses REL relocations. */
3109 int use_rel;
4e7fd91e 3110
0855e32b
NS		 3111 /* The index of the next unused R_ARM_TLS_DESC slot in .rel.plt. */
3112 bfd_vma next_tls_desc_index;
3113
3114 /* How many R_ARM_TLS_DESC relocations were generated so far. */
3115 bfd_vma num_tls_desc;
3116
906e58ca 3117 /* Short-cuts to get to dynamic linker sections. */
906e58ca
NC		 3118 asection *sdynbss;
3119 asection *srelbss;
5e681ec4 3120
906e58ca
NC		 3121 /* The (unloaded but important) VxWorks .rela.plt.unloaded section. */
3122 asection *srelplt2;
00a97672 3123
0855e32b
NS		 3124 /* The offset into splt of the PLT entry for the TLS descriptor
3125 resolver. Special values are 0, if not necessary (or not found
3126 to be necessary yet), and -1 if needed but not determined
3127 yet. */
3128 bfd_vma dt_tlsdesc_plt;
3129
3130 /* The offset into sgot of the GOT entry used by the PLT entry
3131 above. */
b38cadfb 3132 bfd_vma dt_tlsdesc_got;
0855e32b
NS		 3133
3134 /* Offset in .plt section of tls_arm_trampoline. */
3135 bfd_vma tls_trampoline;
3136
906e58ca
NC		 3137 /* Data for R_ARM_TLS_LDM32 relocations. */
3138 union
3139 {
3140 bfd_signed_vma refcount;
3141 bfd_vma offset;
3142 } tls_ldm_got;
b7693d02 3143
87d72d41
AM		 3144 /* Small local sym cache. */
3145 struct sym_cache sym_cache;
906e58ca
NC		 3146
3147 /* For convenience in allocate_dynrelocs. */
3148 bfd * obfd;
3149
0855e32b
NS		 3150 /* The amount of space used by the reserved portion of the sgotplt
3151 section, plus whatever space is used by the jump slots. */
3152 bfd_vma sgotplt_jump_table_size;
3153
906e58ca
NC		 3154 /* The stub hash table. */
3155 struct bfd_hash_table stub_hash_table;
3156
3157 /* Linker stub bfd. */
3158 bfd *stub_bfd;
3159
3160 /* Linker call-backs. */
7a89b94e 3161 asection * (*add_stub_section) (const char *, asection *, unsigned int);
906e58ca
NC		 3162 void (*layout_sections_again) (void);
3163
3164 /* Array to keep track of which stub sections have been created, and
3165 information on stub grouping. */
21d799b5 3166 struct map_stub *stub_group;
906e58ca 3167
fe33d2fa 3168 /* Number of elements in stub_group. */
7292b3ac 3169 unsigned int top_id;
fe33d2fa 3170
906e58ca
NC		 3171 /* Assorted information used by elf32_arm_size_stubs. */
3172 unsigned int bfd_count;
7292b3ac 3173 unsigned int top_index;
906e58ca
NC		 3174 asection **input_list;
3175};
252b5132 3176
a504d23a
LA		 3177static inline int
3178ctz (unsigned int mask)
3179{
3180#if GCC_VERSION >= 3004
3181 return __builtin_ctz (mask);
3182#else
3183 unsigned int i;
3184
3185 for (i = 0; i < 8 * sizeof (mask); i++)
3186 {
3187 if (mask & 0x1)
3188 break;
3189 mask = (mask >> 1);
3190 }
3191 return i;
3192#endif
3193}
3194
3195static inline int
3196popcount (unsigned int mask)
3197{
3198#if GCC_VERSION >= 3004
3199 return __builtin_popcount (mask);
3200#else
3201 unsigned int i, sum = 0;
3202
3203 for (i = 0; i < 8 * sizeof (mask); i++)
3204 {
3205 if (mask & 0x1)
3206 sum++;
3207 mask = (mask >> 1);
3208 }
3209 return sum;
3210#endif
3211}
3212
780a67af
NC		 3213/* Create an entry in an ARM ELF linker hash table. */
3214
3215static struct bfd_hash_entry *
57e8b36a 3216elf32_arm_link_hash_newfunc (struct bfd_hash_entry * entry,
99059e56
RM		 3217 struct bfd_hash_table * table,
3218 const char * string)
780a67af
NC		 3219{
3220 struct elf32_arm_link_hash_entry * ret =
3221 (struct elf32_arm_link_hash_entry *) entry;
3222
3223 /* Allocate the structure if it has not already been allocated by a
3224 subclass. */
906e58ca 3225 if (ret == NULL)
21d799b5 3226 ret = (struct elf32_arm_link_hash_entry *)
99059e56 3227 bfd_hash_allocate (table, sizeof (struct elf32_arm_link_hash_entry));
57e8b36a 3228 if (ret == NULL)
780a67af
NC		 3229 return (struct bfd_hash_entry *) ret;
3230
3231 /* Call the allocation method of the superclass. */
3232 ret = ((struct elf32_arm_link_hash_entry *)
3233 _bfd_elf_link_hash_newfunc ((struct bfd_hash_entry *) ret,
3234 table, string));
57e8b36a 3235 if (ret != NULL)
b7693d02 3236 {
0bdcacaf 3237 ret->dyn_relocs = NULL;
ba93b8ac 3238 ret->tls_type = GOT_UNKNOWN;
0855e32b 3239 ret->tlsdesc_got = (bfd_vma) -1;
34e77a92
RS		 3240 ret->plt.thumb_refcount = 0;
3241 ret->plt.maybe_thumb_refcount = 0;
3242 ret->plt.noncall_refcount = 0;
3243 ret->plt.got_offset = -1;
3244 ret->is_iplt = FALSE;
a4fd1a8e 3245 ret->export_glue = NULL;
906e58ca
NC		 3246
3247 ret->stub_cache = NULL;
b7693d02 3248 }
780a67af
NC		 3249
3250 return (struct bfd_hash_entry *) ret;
3251}
3252
34e77a92
RS		 3253/* Ensure that we have allocated bookkeeping structures for ABFD's local
3254 symbols. */
3255
3256static bfd_boolean
3257elf32_arm_allocate_local_sym_info (bfd *abfd)
3258{
3259 if (elf_local_got_refcounts (abfd) == NULL)
3260 {
3261 bfd_size_type num_syms;
3262 bfd_size_type size;
3263 char *data;
3264
3265 num_syms = elf_tdata (abfd)->symtab_hdr.sh_info;
3266 size = num_syms * (sizeof (bfd_signed_vma)
3267 + sizeof (struct arm_local_iplt_info *)
3268 + sizeof (bfd_vma)
3269 + sizeof (char));
3270 data = bfd_zalloc (abfd, size);
3271 if (data == NULL)
3272 return FALSE;
3273
3274 elf_local_got_refcounts (abfd) = (bfd_signed_vma *) data;
3275 data += num_syms * sizeof (bfd_signed_vma);
3276
3277 elf32_arm_local_iplt (abfd) = (struct arm_local_iplt_info **) data;
3278 data += num_syms * sizeof (struct arm_local_iplt_info *);
3279
3280 elf32_arm_local_tlsdesc_gotent (abfd) = (bfd_vma *) data;
3281 data += num_syms * sizeof (bfd_vma);
3282
3283 elf32_arm_local_got_tls_type (abfd) = data;
3284 }
3285 return TRUE;
3286}
3287
3288/* Return the .iplt information for local symbol R_SYMNDX, which belongs
3289 to input bfd ABFD. Create the information if it doesn't already exist.
3290 Return null if an allocation fails. */
3291
3292static struct arm_local_iplt_info *
3293elf32_arm_create_local_iplt (bfd *abfd, unsigned long r_symndx)
3294{
3295 struct arm_local_iplt_info **ptr;
3296
3297 if (!elf32_arm_allocate_local_sym_info (abfd))
3298 return NULL;
3299
3300 BFD_ASSERT (r_symndx < elf_tdata (abfd)->symtab_hdr.sh_info);
3301 ptr = &elf32_arm_local_iplt (abfd)[r_symndx];
3302 if (*ptr == NULL)
3303 *ptr = bfd_zalloc (abfd, sizeof (**ptr));
3304 return *ptr;
3305}
3306
3307/* Try to obtain PLT information for the symbol with index R_SYMNDX
3308 in ABFD's symbol table. If the symbol is global, H points to its
3309 hash table entry, otherwise H is null.
3310
3311 Return true if the symbol does have PLT information. When returning
3312 true, point *ROOT_PLT at the target-independent reference count/offset
3313 union and *ARM_PLT at the ARM-specific information. */
3314
3315static bfd_boolean
3316elf32_arm_get_plt_info (bfd *abfd, struct elf32_arm_link_hash_entry *h,
3317 unsigned long r_symndx, union gotplt_union **root_plt,
3318 struct arm_plt_info **arm_plt)
3319{
3320 struct arm_local_iplt_info *local_iplt;
3321
3322 if (h != NULL)
3323 {
3324 *root_plt = &h->root.plt;
3325 *arm_plt = &h->plt;
3326 return TRUE;
3327 }
3328
3329 if (elf32_arm_local_iplt (abfd) == NULL)
3330 return FALSE;
3331
3332 local_iplt = elf32_arm_local_iplt (abfd)[r_symndx];
3333 if (local_iplt == NULL)
3334 return FALSE;
3335
3336 *root_plt = &local_iplt->root;
3337 *arm_plt = &local_iplt->arm;
3338 return TRUE;
3339}
3340
3341/* Return true if the PLT described by ARM_PLT requires a Thumb stub
3342 before it. */
3343
3344static bfd_boolean
3345elf32_arm_plt_needs_thumb_stub_p (struct bfd_link_info *info,
3346 struct arm_plt_info *arm_plt)
3347{
3348 struct elf32_arm_link_hash_table *htab;
3349
3350 htab = elf32_arm_hash_table (info);
3351 return (arm_plt->thumb_refcount != 0
3352 || (!htab->use_blx && arm_plt->maybe_thumb_refcount != 0));
3353}
3354
3355/* Return a pointer to the head of the dynamic reloc list that should
3356 be used for local symbol ISYM, which is symbol number R_SYMNDX in
3357 ABFD's symbol table. Return null if an error occurs. */
3358
3359static struct elf_dyn_relocs **
3360elf32_arm_get_local_dynreloc_list (bfd *abfd, unsigned long r_symndx,
3361 Elf_Internal_Sym *isym)
3362{
3363 if (ELF32_ST_TYPE (isym->st_info) == STT_GNU_IFUNC)
3364 {
3365 struct arm_local_iplt_info *local_iplt;
3366
3367 local_iplt = elf32_arm_create_local_iplt (abfd, r_symndx);
3368 if (local_iplt == NULL)
3369 return NULL;
3370 return &local_iplt->dyn_relocs;
3371 }
3372 else
3373 {
3374 /* Track dynamic relocs needed for local syms too.
3375 We really need local syms available to do this
3376 easily. Oh well. */
3377 asection *s;
3378 void *vpp;
3379
3380 s = bfd_section_from_elf_index (abfd, isym->st_shndx);
3381 if (s == NULL)
3382 abort ();
3383
3384 vpp = &elf_section_data (s)->local_dynrel;
3385 return (struct elf_dyn_relocs **) vpp;
3386 }
3387}
3388
906e58ca
NC		 3389/* Initialize an entry in the stub hash table. */
3390
3391static struct bfd_hash_entry *
3392stub_hash_newfunc (struct bfd_hash_entry *entry,
3393 struct bfd_hash_table *table,
3394 const char *string)
3395{
3396 /* Allocate the structure if it has not already been allocated by a
3397 subclass. */
3398 if (entry == NULL)
3399 {
21d799b5 3400 entry = (struct bfd_hash_entry *)
99059e56 3401 bfd_hash_allocate (table, sizeof (struct elf32_arm_stub_hash_entry));
906e58ca
NC		 3402 if (entry == NULL)
3403 return entry;
3404 }
3405
3406 /* Call the allocation method of the superclass. */
3407 entry = bfd_hash_newfunc (entry, table, string);
3408 if (entry != NULL)
3409 {
3410 struct elf32_arm_stub_hash_entry *eh;
3411
3412 /* Initialize the local fields. */
3413 eh = (struct elf32_arm_stub_hash_entry *) entry;
3414 eh->stub_sec = NULL;
3415 eh->stub_offset = 0;
3416 eh->target_value = 0;
3417 eh->target_section = NULL;
cedfb179
DK		 3418 eh->target_addend = 0;
3419 eh->orig_insn = 0;
906e58ca 3420 eh->stub_type = arm_stub_none;
461a49ca
DJ		 3421 eh->stub_size = 0;
3422 eh->stub_template = NULL;
3423 eh->stub_template_size = 0;
906e58ca
NC		 3424 eh->h = NULL;
3425 eh->id_sec = NULL;
d8d2f433 3426 eh->output_name = NULL;
906e58ca
NC		 3427 }
3428
3429 return entry;
3430}
3431
00a97672 3432/* Create .got, .gotplt, and .rel(a).got sections in DYNOBJ, and set up
5e681ec4
PB		 3433 shortcuts to them in our hash table. */
3434
3435static bfd_boolean
57e8b36a 3436create_got_section (bfd *dynobj, struct bfd_link_info *info)
5e681ec4
PB		 3437{
3438 struct elf32_arm_link_hash_table *htab;
3439
e5a52504 3440 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 3441 if (htab == NULL)
3442 return FALSE;
3443
e5a52504
MM		 3444 /* BPABI objects never have a GOT, or associated sections. */
3445 if (htab->symbian_p)
3446 return TRUE;
3447
5e681ec4
PB		 3448 if (! _bfd_elf_create_got_section (dynobj, info))
3449 return FALSE;
3450
5e681ec4
PB		 3451 return TRUE;
3452}
3453
34e77a92
RS		 3454/* Create the .iplt, .rel(a).iplt and .igot.plt sections. */
3455
3456static bfd_boolean
3457create_ifunc_sections (struct bfd_link_info *info)
3458{
3459 struct elf32_arm_link_hash_table *htab;
3460 const struct elf_backend_data *bed;
3461 bfd *dynobj;
3462 asection *s;
3463 flagword flags;
b38cadfb 3464
34e77a92
RS		 3465 htab = elf32_arm_hash_table (info);
3466 dynobj = htab->root.dynobj;
3467 bed = get_elf_backend_data (dynobj);
3468 flags = bed->dynamic_sec_flags;
3469
3470 if (htab->root.iplt == NULL)
3471 {
3d4d4302
AM		 3472 s = bfd_make_section_anyway_with_flags (dynobj, ".iplt",
3473 flags | SEC_READONLY | SEC_CODE);
34e77a92 3474 if (s == NULL
a0f49396 3475 || !bfd_set_section_alignment (dynobj, s, bed->plt_alignment))
34e77a92
RS		 3476 return FALSE;
3477 htab->root.iplt = s;
3478 }
3479
3480 if (htab->root.irelplt == NULL)
3481 {
3d4d4302
AM		 3482 s = bfd_make_section_anyway_with_flags (dynobj,
3483 RELOC_SECTION (htab, ".iplt"),
3484 flags | SEC_READONLY);
34e77a92 3485 if (s == NULL
a0f49396 3486 || !bfd_set_section_alignment (dynobj, s, bed->s->log_file_align))
34e77a92
RS		 3487 return FALSE;
3488 htab->root.irelplt = s;
3489 }
3490
3491 if (htab->root.igotplt == NULL)
3492 {
3d4d4302 3493 s = bfd_make_section_anyway_with_flags (dynobj, ".igot.plt", flags);
34e77a92
RS		 3494 if (s == NULL
3495 || !bfd_set_section_alignment (dynobj, s, bed->s->log_file_align))
3496 return FALSE;
3497 htab->root.igotplt = s;
3498 }
3499 return TRUE;
3500}
3501
eed94f8f
NC		 3502/* Determine if we're dealing with a Thumb only architecture. */
3503
3504static bfd_boolean
3505using_thumb_only (struct elf32_arm_link_hash_table *globals)
3506{
2fd158eb
TP		 3507 int arch;
3508 int profile = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC,
3509 Tag_CPU_arch_profile);
eed94f8f 3510
2fd158eb
TP		 3511 if (profile)
3512 return profile == 'M';
eed94f8f 3513
2fd158eb 3514 arch = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC, Tag_CPU_arch);
eed94f8f 3515
2fd158eb
TP		 3516 if (arch == TAG_CPU_ARCH_V6_M
3517 || arch == TAG_CPU_ARCH_V6S_M
3518 || arch == TAG_CPU_ARCH_V7E_M
3519 || arch == TAG_CPU_ARCH_V8M_BASE
3520 || arch == TAG_CPU_ARCH_V8M_MAIN)
3521 return TRUE;
eed94f8f 3522
2fd158eb 3523 return FALSE;
eed94f8f
NC		 3524}
3525
3526/* Determine if we're dealing with a Thumb-2 object. */
3527
3528static bfd_boolean
3529using_thumb2 (struct elf32_arm_link_hash_table *globals)
3530{
3531 int arch = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC,
3532 Tag_CPU_arch);
3533 return arch == TAG_CPU_ARCH_V6T2 || arch >= TAG_CPU_ARCH_V7;
3534}
3535
00a97672
RS		 3536/* Create .plt, .rel(a).plt, .got, .got.plt, .rel(a).got, .dynbss, and
3537 .rel(a).bss sections in DYNOBJ, and set up shortcuts to them in our
5e681ec4
PB		 3538 hash table. */
3539
3540static bfd_boolean
57e8b36a 3541elf32_arm_create_dynamic_sections (bfd *dynobj, struct bfd_link_info *info)
5e681ec4
PB		 3542{
3543 struct elf32_arm_link_hash_table *htab;
3544
3545 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 3546 if (htab == NULL)
3547 return FALSE;
3548
362d30a1 3549 if (!htab->root.sgot && !create_got_section (dynobj, info))
5e681ec4
PB		 3550 return FALSE;
3551
3552 if (!_bfd_elf_create_dynamic_sections (dynobj, info))
3553 return FALSE;
3554
3d4d4302 3555 htab->sdynbss = bfd_get_linker_section (dynobj, ".dynbss");
0e1862bb 3556 if (!bfd_link_pic (info))
3d4d4302
AM		 3557 htab->srelbss = bfd_get_linker_section (dynobj,
3558 RELOC_SECTION (htab, ".bss"));
00a97672
RS		 3559
3560 if (htab->vxworks_p)
3561 {
3562 if (!elf_vxworks_create_dynamic_sections (dynobj, info, &htab->srelplt2))
3563 return FALSE;
3564
0e1862bb 3565 if (bfd_link_pic (info))
00a97672
RS		 3566 {
3567 htab->plt_header_size = 0;
3568 htab->plt_entry_size
3569 = 4 * ARRAY_SIZE (elf32_arm_vxworks_shared_plt_entry);
3570 }
3571 else
3572 {
3573 htab->plt_header_size
3574 = 4 * ARRAY_SIZE (elf32_arm_vxworks_exec_plt0_entry);
3575 htab->plt_entry_size
3576 = 4 * ARRAY_SIZE (elf32_arm_vxworks_exec_plt_entry);
3577 }
3578 }
eed94f8f
NC		 3579 else
3580 {
3581 /* PR ld/16017
3582 Test for thumb only architectures. Note - we cannot just call
3583 using_thumb_only() as the attributes in the output bfd have not been
3584 initialised at this point, so instead we use the input bfd. */
3585 bfd * saved_obfd = htab->obfd;
3586
3587 htab->obfd = dynobj;
3588 if (using_thumb_only (htab))
3589 {
3590 htab->plt_header_size = 4 * ARRAY_SIZE (elf32_thumb2_plt0_entry);
3591 htab->plt_entry_size = 4 * ARRAY_SIZE (elf32_thumb2_plt_entry);
3592 }
3593 htab->obfd = saved_obfd;
3594 }
5e681ec4 3595
362d30a1
RS		 3596 if (!htab->root.splt
3597 || !htab->root.srelplt
e5a52504 3598 || !htab->sdynbss
0e1862bb 3599 || (!bfd_link_pic (info) && !htab->srelbss))
5e681ec4
PB		 3600 abort ();
3601
3602 return TRUE;
3603}
3604
906e58ca
NC		 3605/* Copy the extra info we tack onto an elf_link_hash_entry. */
3606
3607static void
3608elf32_arm_copy_indirect_symbol (struct bfd_link_info *info,
3609 struct elf_link_hash_entry *dir,
3610 struct elf_link_hash_entry *ind)
3611{
3612 struct elf32_arm_link_hash_entry *edir, *eind;
3613
3614 edir = (struct elf32_arm_link_hash_entry *) dir;
3615 eind = (struct elf32_arm_link_hash_entry *) ind;
3616
0bdcacaf 3617 if (eind->dyn_relocs != NULL)
906e58ca 3618 {
0bdcacaf 3619 if (edir->dyn_relocs != NULL)
906e58ca 3620 {
0bdcacaf
RS		 3621 struct elf_dyn_relocs **pp;
3622 struct elf_dyn_relocs *p;
906e58ca
NC		 3623
3624 /* Add reloc counts against the indirect sym to the direct sym
3625 list. Merge any entries against the same section. */
0bdcacaf 3626 for (pp = &eind->dyn_relocs; (p = *pp) != NULL; )
906e58ca 3627 {
0bdcacaf 3628 struct elf_dyn_relocs *q;
906e58ca 3629
0bdcacaf
RS		 3630 for (q = edir->dyn_relocs; q != NULL; q = q->next)
3631 if (q->sec == p->sec)
906e58ca
NC		 3632 {
3633 q->pc_count += p->pc_count;
3634 q->count += p->count;
3635 *pp = p->next;
3636 break;
3637 }
3638 if (q == NULL)
3639 pp = &p->next;
3640 }
0bdcacaf 3641 *pp = edir->dyn_relocs;
906e58ca
NC		 3642 }
3643
0bdcacaf
RS		 3644 edir->dyn_relocs = eind->dyn_relocs;
3645 eind->dyn_relocs = NULL;
906e58ca
NC		 3646 }
3647
3648 if (ind->root.type == bfd_link_hash_indirect)
3649 {
3650 /* Copy over PLT info. */
34e77a92
RS		 3651 edir->plt.thumb_refcount += eind->plt.thumb_refcount;
3652 eind->plt.thumb_refcount = 0;
3653 edir->plt.maybe_thumb_refcount += eind->plt.maybe_thumb_refcount;
3654 eind->plt.maybe_thumb_refcount = 0;
3655 edir->plt.noncall_refcount += eind->plt.noncall_refcount;
3656 eind->plt.noncall_refcount = 0;
3657
3658 /* We should only allocate a function to .iplt once the final
3659 symbol information is known. */
3660 BFD_ASSERT (!eind->is_iplt);
906e58ca
NC		 3661
3662 if (dir->got.refcount <= 0)
3663 {
3664 edir->tls_type = eind->tls_type;
3665 eind->tls_type = GOT_UNKNOWN;
3666 }
3667 }
3668
3669 _bfd_elf_link_hash_copy_indirect (info, dir, ind);
3670}
3671
68faa637
AM		 3672/* Destroy an ARM elf linker hash table. */
3673
3674static void
d495ab0d 3675elf32_arm_link_hash_table_free (bfd *obfd)
68faa637
AM		 3676{
3677 struct elf32_arm_link_hash_table *ret
d495ab0d 3678 = (struct elf32_arm_link_hash_table *) obfd->link.hash;
68faa637
AM		 3679
3680 bfd_hash_table_free (&ret->stub_hash_table);
d495ab0d 3681 _bfd_elf_link_hash_table_free (obfd);
68faa637
AM		 3682}
3683
906e58ca
NC		 3684/* Create an ARM elf linker hash table. */
3685
3686static struct bfd_link_hash_table *
3687elf32_arm_link_hash_table_create (bfd *abfd)
3688{
3689 struct elf32_arm_link_hash_table *ret;
3690 bfd_size_type amt = sizeof (struct elf32_arm_link_hash_table);
3691
7bf52ea2 3692 ret = (struct elf32_arm_link_hash_table *) bfd_zmalloc (amt);
906e58ca
NC		 3693 if (ret == NULL)
3694 return NULL;
3695
3696 if (!_bfd_elf_link_hash_table_init (& ret->root, abfd,
3697 elf32_arm_link_hash_newfunc,
4dfe6ac6
NC		 3698 sizeof (struct elf32_arm_link_hash_entry),
3699 ARM_ELF_DATA))
906e58ca
NC		 3700 {
3701 free (ret);
3702 return NULL;
3703 }
3704
906e58ca 3705 ret->vfp11_fix = BFD_ARM_VFP11_FIX_NONE;
a504d23a 3706 ret->stm32l4xx_fix = BFD_ARM_STM32L4XX_FIX_NONE;
906e58ca
NC		 3707#ifdef FOUR_WORD_PLT
3708 ret->plt_header_size = 16;
3709 ret->plt_entry_size = 16;
3710#else
3711 ret->plt_header_size = 20;
1db37fe6 3712 ret->plt_entry_size = elf32_arm_use_long_plt_entry ? 16 : 12;
906e58ca 3713#endif
906e58ca 3714 ret->use_rel = 1;
906e58ca 3715 ret->obfd = abfd;
906e58ca
NC		 3716
3717 if (!bfd_hash_table_init (&ret->stub_hash_table, stub_hash_newfunc,
3718 sizeof (struct elf32_arm_stub_hash_entry)))
3719 {
d495ab0d 3720 _bfd_elf_link_hash_table_free (abfd);
906e58ca
NC		 3721 return NULL;
3722 }
d495ab0d 3723 ret->root.root.hash_table_free = elf32_arm_link_hash_table_free;
906e58ca
NC		 3724
3725 return &ret->root.root;
3726}
3727
cd1dac3d
DG		 3728/* Determine what kind of NOPs are available. */
3729
3730static bfd_boolean
3731arch_has_arm_nop (struct elf32_arm_link_hash_table *globals)
3732{
3733 const int arch = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC,
3734 Tag_CPU_arch);
3735 return arch == TAG_CPU_ARCH_V6T2
3736 || arch == TAG_CPU_ARCH_V6K
9e3c6df6
PB		 3737 || arch == TAG_CPU_ARCH_V7
3738 || arch == TAG_CPU_ARCH_V7E_M;
cd1dac3d
DG		 3739}
3740
3741static bfd_boolean
3742arch_has_thumb2_nop (struct elf32_arm_link_hash_table *globals)
3743{
3744 const int arch = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC,
3745 Tag_CPU_arch);
9e3c6df6
PB		 3746 return (arch == TAG_CPU_ARCH_V6T2 || arch == TAG_CPU_ARCH_V7
3747 || arch == TAG_CPU_ARCH_V7E_M);
cd1dac3d
DG		 3748}
3749
f4ac8484
DJ		 3750static bfd_boolean
3751arm_stub_is_thumb (enum elf32_arm_stub_type stub_type)
3752{
3753 switch (stub_type)
3754 {
fea2b4d6
CL		 3755 case arm_stub_long_branch_thumb_only:
3756 case arm_stub_long_branch_v4t_thumb_arm:
3757 case arm_stub_short_branch_v4t_thumb_arm:
ebe24dd4 3758 case arm_stub_long_branch_v4t_thumb_arm_pic:
12352d3f 3759 case arm_stub_long_branch_v4t_thumb_tls_pic:
ebe24dd4 3760 case arm_stub_long_branch_thumb_only_pic:
f4ac8484
DJ		 3761 return TRUE;
3762 case arm_stub_none:
3763 BFD_FAIL ();
3764 return FALSE;
3765 break;
3766 default:
3767 return FALSE;
3768 }
3769}
3770
906e58ca
NC		 3771/* Determine the type of stub needed, if any, for a call. */
3772
3773static enum elf32_arm_stub_type
3774arm_type_of_stub (struct bfd_link_info *info,
3775 asection *input_sec,
3776 const Elf_Internal_Rela *rel,
34e77a92 3777 unsigned char st_type,
35fc36a8 3778 enum arm_st_branch_type *actual_branch_type,
906e58ca 3779 struct elf32_arm_link_hash_entry *hash,
c820be07
NC		 3780 bfd_vma destination,
3781 asection *sym_sec,
3782 bfd *input_bfd,
3783 const char *name)
906e58ca
NC		 3784{
3785 bfd_vma location;
3786 bfd_signed_vma branch_offset;
3787 unsigned int r_type;
3788 struct elf32_arm_link_hash_table * globals;
3789 int thumb2;
3790 int thumb_only;
3791 enum elf32_arm_stub_type stub_type = arm_stub_none;
5fa9e92f 3792 int use_plt = 0;
35fc36a8 3793 enum arm_st_branch_type branch_type = *actual_branch_type;
34e77a92
RS		 3794 union gotplt_union *root_plt;
3795 struct arm_plt_info *arm_plt;
906e58ca 3796
35fc36a8 3797 if (branch_type == ST_BRANCH_LONG)
da5938a2
NC		 3798 return stub_type;
3799
906e58ca 3800 globals = elf32_arm_hash_table (info);
4dfe6ac6
NC		 3801 if (globals == NULL)
3802 return stub_type;
906e58ca
NC		 3803
3804 thumb_only = using_thumb_only (globals);
3805
3806 thumb2 = using_thumb2 (globals);
3807
3808 /* Determine where the call point is. */
3809 location = (input_sec->output_offset
3810 + input_sec->output_section->vma
3811 + rel->r_offset);
3812
906e58ca
NC		 3813 r_type = ELF32_R_TYPE (rel->r_info);
3814
39f21624
NC		 3815 /* ST_BRANCH_TO_ARM is nonsense to thumb-only targets when we
3816 are considering a function call relocation. */
c5423981
TG		 3817 if (thumb_only && (r_type == R_ARM_THM_CALL || r_type == R_ARM_THM_JUMP24
3818 || r_type == R_ARM_THM_JUMP19)
39f21624
NC		 3819 && branch_type == ST_BRANCH_TO_ARM)
3820 branch_type = ST_BRANCH_TO_THUMB;
3821
34e77a92
RS		 3822 /* For TLS call relocs, it is the caller's responsibility to provide
3823 the address of the appropriate trampoline. */
3824 if (r_type != R_ARM_TLS_CALL
3825 && r_type != R_ARM_THM_TLS_CALL
3826 && elf32_arm_get_plt_info (input_bfd, hash, ELF32_R_SYM (rel->r_info),
3827 &root_plt, &arm_plt)
3828 && root_plt->offset != (bfd_vma) -1)
5fa9e92f 3829 {
34e77a92 3830 asection *splt;
fe33d2fa 3831
34e77a92
RS		 3832 if (hash == NULL || hash->is_iplt)
3833 splt = globals->root.iplt;
3834 else
3835 splt = globals->root.splt;
3836 if (splt != NULL)
b38cadfb 3837 {
34e77a92
RS		 3838 use_plt = 1;
3839
3840 /* Note when dealing with PLT entries: the main PLT stub is in
3841 ARM mode, so if the branch is in Thumb mode, another
3842 Thumb->ARM stub will be inserted later just before the ARM
3843 PLT stub. We don't take this extra distance into account
3844 here, because if a long branch stub is needed, we'll add a
3845 Thumb->Arm one and branch directly to the ARM PLT entry
3846 because it avoids spreading offset corrections in several
3847 places. */
3848
3849 destination = (splt->output_section->vma
3850 + splt->output_offset
3851 + root_plt->offset);
3852 st_type = STT_FUNC;
3853 branch_type = ST_BRANCH_TO_ARM;
3854 }
5fa9e92f 3855 }
34e77a92
RS		 3856 /* Calls to STT_GNU_IFUNC symbols should go through a PLT. */
3857 BFD_ASSERT (st_type != STT_GNU_IFUNC);
906e58ca 3858
fe33d2fa
CL		 3859 branch_offset = (bfd_signed_vma)(destination - location);
3860
0855e32b 3861 if (r_type == R_ARM_THM_CALL || r_type == R_ARM_THM_JUMP24
c5423981 3862 || r_type == R_ARM_THM_TLS_CALL || r_type == R_ARM_THM_JUMP19)
906e58ca 3863 {
5fa9e92f
CL		 3864 /* Handle cases where:
3865 - this call goes too far (different Thumb/Thumb2 max
99059e56 3866 distance)
155d87d7 3867 - it's a Thumb->Arm call and blx is not available, or it's a
99059e56
RM		 3868 Thumb->Arm branch (not bl). A stub is needed in this case,
3869 but only if this call is not through a PLT entry. Indeed,
3870 PLT stubs handle mode switching already.
5fa9e92f 3871 */
906e58ca
NC		 3872 if ((!thumb2
3873 && (branch_offset > THM_MAX_FWD_BRANCH_OFFSET
3874 || (branch_offset < THM_MAX_BWD_BRANCH_OFFSET)))
3875 || (thumb2
3876 && (branch_offset > THM2_MAX_FWD_BRANCH_OFFSET
3877 || (branch_offset < THM2_MAX_BWD_BRANCH_OFFSET)))
c5423981
TG		 3878 || (thumb2
3879 && (branch_offset > THM2_MAX_FWD_COND_BRANCH_OFFSET
3880 || (branch_offset < THM2_MAX_BWD_COND_BRANCH_OFFSET))
3881 && (r_type == R_ARM_THM_JUMP19))
35fc36a8 3882 || (branch_type == ST_BRANCH_TO_ARM
0855e32b
NS		 3883 && (((r_type == R_ARM_THM_CALL
3884 || r_type == R_ARM_THM_TLS_CALL) && !globals->use_blx)
c5423981
TG		 3885 || (r_type == R_ARM_THM_JUMP24)
3886 || (r_type == R_ARM_THM_JUMP19))
5fa9e92f 3887 && !use_plt))
906e58ca 3888 {
35fc36a8 3889 if (branch_type == ST_BRANCH_TO_THUMB)
906e58ca
NC		 3890 {
3891 /* Thumb to thumb. */
3892 if (!thumb_only)
3893 {
0e1862bb 3894 stub_type = (bfd_link_pic (info) | globals->pic_veneer)
c2b4a39d 3895 /* PIC stubs. */
155d87d7 3896 ? ((globals->use_blx
9553db3c 3897 && (r_type == R_ARM_THM_CALL))
155d87d7
CL		 3898 /* V5T and above. Stub starts with ARM code, so
3899 we must be able to switch mode before
3900 reaching it, which is only possible for 'bl'
3901 (ie R_ARM_THM_CALL relocation). */
cf3eccff 3902 ? arm_stub_long_branch_any_thumb_pic
ebe24dd4 3903 /* On V4T, use Thumb code only. */
d3626fb0 3904 : arm_stub_long_branch_v4t_thumb_thumb_pic)
c2b4a39d
CL		 3905
3906 /* non-PIC stubs. */
155d87d7 3907 : ((globals->use_blx
9553db3c 3908 && (r_type == R_ARM_THM_CALL))
c2b4a39d
CL		 3909 /* V5T and above. */
3910 ? arm_stub_long_branch_any_any
3911 /* V4T. */
d3626fb0 3912 : arm_stub_long_branch_v4t_thumb_thumb);
906e58ca
NC		 3913 }
3914 else
3915 {
0e1862bb 3916 stub_type = (bfd_link_pic (info) | globals->pic_veneer)
ebe24dd4
CL		 3917 /* PIC stub. */
3918 ? arm_stub_long_branch_thumb_only_pic
c2b4a39d
CL		 3919 /* non-PIC stub. */
3920 : arm_stub_long_branch_thumb_only;
906e58ca
NC		 3921 }
3922 }
3923 else
3924 {
3925 /* Thumb to arm. */
c820be07
NC		 3926 if (sym_sec != NULL
3927 && sym_sec->owner != NULL
3928 && !INTERWORK_FLAG (sym_sec->owner))
3929 {
3930 (*_bfd_error_handler)
3931 (_("%B(%s): warning: interworking not enabled.\n"
3932 " first occurrence: %B: Thumb call to ARM"),
3933 sym_sec->owner, input_bfd, name);
3934 }
3935
0855e32b 3936 stub_type =
0e1862bb 3937 (bfd_link_pic (info) | globals->pic_veneer)
c2b4a39d 3938 /* PIC stubs. */
0855e32b 3939 ? (r_type == R_ARM_THM_TLS_CALL
6a631e86 3940 /* TLS PIC stubs. */
0855e32b
NS		 3941 ? (globals->use_blx ? arm_stub_long_branch_any_tls_pic
3942 : arm_stub_long_branch_v4t_thumb_tls_pic)
3943 : ((globals->use_blx && r_type == R_ARM_THM_CALL)
3944 /* V5T PIC and above. */
3945 ? arm_stub_long_branch_any_arm_pic
3946 /* V4T PIC stub. */
3947 : arm_stub_long_branch_v4t_thumb_arm_pic))
c2b4a39d
CL		 3948
3949 /* non-PIC stubs. */
0855e32b 3950 : ((globals->use_blx && r_type == R_ARM_THM_CALL)
c2b4a39d
CL		 3951 /* V5T and above. */
3952 ? arm_stub_long_branch_any_any
3953 /* V4T. */
3954 : arm_stub_long_branch_v4t_thumb_arm);
c820be07
NC		 3955
3956 /* Handle v4t short branches. */
fea2b4d6 3957 if ((stub_type == arm_stub_long_branch_v4t_thumb_arm)
c820be07
NC		 3958 && (branch_offset <= THM_MAX_FWD_BRANCH_OFFSET)
3959 && (branch_offset >= THM_MAX_BWD_BRANCH_OFFSET))
fea2b4d6 3960 stub_type = arm_stub_short_branch_v4t_thumb_arm;
906e58ca
NC		 3961 }
3962 }
3963 }
fe33d2fa
CL		 3964 else if (r_type == R_ARM_CALL
3965 || r_type == R_ARM_JUMP24
0855e32b
NS		 3966 || r_type == R_ARM_PLT32
3967 || r_type == R_ARM_TLS_CALL)
906e58ca 3968 {
35fc36a8 3969 if (branch_type == ST_BRANCH_TO_THUMB)
906e58ca
NC		 3970 {
3971 /* Arm to thumb. */
c820be07
NC		 3972
3973 if (sym_sec != NULL
3974 && sym_sec->owner != NULL
3975 && !INTERWORK_FLAG (sym_sec->owner))
3976 {
3977 (*_bfd_error_handler)
3978 (_("%B(%s): warning: interworking not enabled.\n"
c2b4a39d 3979 " first occurrence: %B: ARM call to Thumb"),
c820be07
NC		 3980 sym_sec->owner, input_bfd, name);
3981 }
3982
3983 /* We have an extra 2-bytes reach because of
3984 the mode change (bit 24 (H) of BLX encoding). */
4116d8d7
PB		 3985 if (branch_offset > (ARM_MAX_FWD_BRANCH_OFFSET + 2)
3986 || (branch_offset < ARM_MAX_BWD_BRANCH_OFFSET)
0855e32b 3987 || (r_type == R_ARM_CALL && !globals->use_blx)
4116d8d7
PB		 3988 || (r_type == R_ARM_JUMP24)
3989 || (r_type == R_ARM_PLT32))
906e58ca 3990 {
0e1862bb 3991 stub_type = (bfd_link_pic (info) | globals->pic_veneer)
c2b4a39d 3992 /* PIC stubs. */
ebe24dd4
CL		 3993 ? ((globals->use_blx)
3994 /* V5T and above. */
3995 ? arm_stub_long_branch_any_thumb_pic
3996 /* V4T stub. */
3997 : arm_stub_long_branch_v4t_arm_thumb_pic)
3998
c2b4a39d
CL		 3999 /* non-PIC stubs. */
4000 : ((globals->use_blx)
4001 /* V5T and above. */
4002 ? arm_stub_long_branch_any_any
4003 /* V4T. */
4004 : arm_stub_long_branch_v4t_arm_thumb);
906e58ca
NC		 4005 }
4006 }
4007 else
4008 {
4009 /* Arm to arm. */
4010 if (branch_offset > ARM_MAX_FWD_BRANCH_OFFSET
4011 || (branch_offset < ARM_MAX_BWD_BRANCH_OFFSET))
4012 {
0855e32b 4013 stub_type =
0e1862bb 4014 (bfd_link_pic (info) | globals->pic_veneer)
c2b4a39d 4015 /* PIC stubs. */
0855e32b 4016 ? (r_type == R_ARM_TLS_CALL
6a631e86 4017 /* TLS PIC Stub. */
0855e32b 4018 ? arm_stub_long_branch_any_tls_pic
7a89b94e
NC		 4019 : (globals->nacl_p
4020 ? arm_stub_long_branch_arm_nacl_pic
4021 : arm_stub_long_branch_any_arm_pic))
c2b4a39d 4022 /* non-PIC stubs. */
7a89b94e
NC		 4023 : (globals->nacl_p
4024 ? arm_stub_long_branch_arm_nacl
4025 : arm_stub_long_branch_any_any);
906e58ca
NC		 4026 }
4027 }
4028 }
4029
fe33d2fa
CL		 4030 /* If a stub is needed, record the actual destination type. */
4031 if (stub_type != arm_stub_none)
35fc36a8 4032 *actual_branch_type = branch_type;
fe33d2fa 4033
906e58ca
NC		 4034 return stub_type;
4035}
4036
4037/* Build a name for an entry in the stub hash table. */
4038
4039static char *
4040elf32_arm_stub_name (const asection *input_section,
4041 const asection *sym_sec,
4042 const struct elf32_arm_link_hash_entry *hash,
fe33d2fa
CL		 4043 const Elf_Internal_Rela *rel,
4044 enum elf32_arm_stub_type stub_type)
906e58ca
NC		 4045{
4046 char *stub_name;
4047 bfd_size_type len;
4048
4049 if (hash)
4050 {
fe33d2fa 4051 len = 8 + 1 + strlen (hash->root.root.root.string) + 1 + 8 + 1 + 2 + 1;
21d799b5 4052 stub_name = (char *) bfd_malloc (len);
906e58ca 4053 if (stub_name != NULL)
fe33d2fa 4054 sprintf (stub_name, "%08x_%s+%x_%d",
906e58ca
NC		 4055 input_section->id & 0xffffffff,
4056 hash->root.root.root.string,
fe33d2fa
CL		 4057 (int) rel->r_addend & 0xffffffff,
4058 (int) stub_type);
906e58ca
NC		 4059 }
4060 else
4061 {
fe33d2fa 4062 len = 8 + 1 + 8 + 1 + 8 + 1 + 8 + 1 + 2 + 1;
21d799b5 4063 stub_name = (char *) bfd_malloc (len);
906e58ca 4064 if (stub_name != NULL)
fe33d2fa 4065 sprintf (stub_name, "%08x_%x:%x+%x_%d",
906e58ca
NC		 4066 input_section->id & 0xffffffff,
4067 sym_sec->id & 0xffffffff,
0855e32b
NS		 4068 ELF32_R_TYPE (rel->r_info) == R_ARM_TLS_CALL
4069 || ELF32_R_TYPE (rel->r_info) == R_ARM_THM_TLS_CALL
4070 ? 0 : (int) ELF32_R_SYM (rel->r_info) & 0xffffffff,
fe33d2fa
CL		 4071 (int) rel->r_addend & 0xffffffff,
4072 (int) stub_type);
906e58ca
NC		 4073 }
4074
4075 return stub_name;
4076}
4077
4078/* Look up an entry in the stub hash. Stub entries are cached because
4079 creating the stub name takes a bit of time. */
4080
4081static struct elf32_arm_stub_hash_entry *
4082elf32_arm_get_stub_entry (const asection *input_section,
4083 const asection *sym_sec,
4084 struct elf_link_hash_entry *hash,
4085 const Elf_Internal_Rela *rel,
fe33d2fa
CL		 4086 struct elf32_arm_link_hash_table *htab,
4087 enum elf32_arm_stub_type stub_type)
906e58ca
NC		 4088{
4089 struct elf32_arm_stub_hash_entry *stub_entry;
4090 struct elf32_arm_link_hash_entry *h = (struct elf32_arm_link_hash_entry *) hash;
4091 const asection *id_sec;
4092
4093 if ((input_section->flags & SEC_CODE) == 0)
4094 return NULL;
4095
4096 /* If this input section is part of a group of sections sharing one
4097 stub section, then use the id of the first section in the group.
4098 Stub names need to include a section id, as there may well be
4099 more than one stub used to reach say, printf, and we need to
4100 distinguish between them. */
4101 id_sec = htab->stub_group[input_section->id].link_sec;
4102
4103 if (h != NULL && h->stub_cache != NULL
4104 && h->stub_cache->h == h
fe33d2fa
CL		 4105 && h->stub_cache->id_sec == id_sec
4106 && h->stub_cache->stub_type == stub_type)
906e58ca
NC		 4107 {
4108 stub_entry = h->stub_cache;
4109 }
4110 else
4111 {
4112 char *stub_name;
4113
fe33d2fa 4114 stub_name = elf32_arm_stub_name (id_sec, sym_sec, h, rel, stub_type);
906e58ca
NC		 4115 if (stub_name == NULL)
4116 return NULL;
4117
4118 stub_entry = arm_stub_hash_lookup (&htab->stub_hash_table,
4119 stub_name, FALSE, FALSE);
4120 if (h != NULL)
4121 h->stub_cache = stub_entry;
4122
4123 free (stub_name);
4124 }
4125
4126 return stub_entry;
4127}
4128
48229727 4129/* Find or create a stub section. Returns a pointer to the stub section, and
b38cadfb 4130 the section to which the stub section will be attached (in *LINK_SEC_P).
48229727 4131 LINK_SEC_P may be NULL. */
906e58ca 4132
48229727
JB		 4133static asection *
4134elf32_arm_create_or_find_stub_sec (asection **link_sec_p, asection *section,
4135 struct elf32_arm_link_hash_table *htab)
906e58ca
NC		 4136{
4137 asection *link_sec;
4138 asection *stub_sec;
906e58ca
NC		 4139
4140 link_sec = htab->stub_group[section->id].link_sec;
9553db3c 4141 BFD_ASSERT (link_sec != NULL);
906e58ca 4142 stub_sec = htab->stub_group[section->id].stub_sec;
9553db3c 4143
906e58ca
NC		 4144 if (stub_sec == NULL)
4145 {
4146 stub_sec = htab->stub_group[link_sec->id].stub_sec;
4147 if (stub_sec == NULL)
4148 {
4149 size_t namelen;
4150 bfd_size_type len;
4151 char *s_name;
4152
4153 namelen = strlen (link_sec->name);
4154 len = namelen + sizeof (STUB_SUFFIX);
21d799b5 4155 s_name = (char *) bfd_alloc (htab->stub_bfd, len);
906e58ca
NC		 4156 if (s_name == NULL)
4157 return NULL;
4158
4159 memcpy (s_name, link_sec->name, namelen);
4160 memcpy (s_name + namelen, STUB_SUFFIX, sizeof (STUB_SUFFIX));
7a89b94e
NC		 4161 stub_sec = (*htab->add_stub_section) (s_name, link_sec,
4162 htab->nacl_p ? 4 : 3);
906e58ca
NC		 4163 if (stub_sec == NULL)
4164 return NULL;
4165 htab->stub_group[link_sec->id].stub_sec = stub_sec;
4166 }
4167 htab->stub_group[section->id].stub_sec = stub_sec;
4168 }
b38cadfb 4169
48229727
JB		 4170 if (link_sec_p)
4171 *link_sec_p = link_sec;
b38cadfb 4172
48229727
JB		 4173 return stub_sec;
4174}
4175
4176/* Add a new stub entry to the stub hash. Not all fields of the new
4177 stub entry are initialised. */
4178
4179static struct elf32_arm_stub_hash_entry *
4180elf32_arm_add_stub (const char *stub_name,
4181 asection *section,
4182 struct elf32_arm_link_hash_table *htab)
4183{
4184 asection *link_sec;
4185 asection *stub_sec;
4186 struct elf32_arm_stub_hash_entry *stub_entry;
4187
4188 stub_sec = elf32_arm_create_or_find_stub_sec (&link_sec, section, htab);
4189 if (stub_sec == NULL)
4190 return NULL;
906e58ca
NC		 4191
4192 /* Enter this entry into the linker stub hash table. */
4193 stub_entry = arm_stub_hash_lookup (&htab->stub_hash_table, stub_name,
4194 TRUE, FALSE);
4195 if (stub_entry == NULL)
4196 {
4197 (*_bfd_error_handler) (_("%s: cannot create stub entry %s"),
4198 section->owner,
4199 stub_name);
4200 return NULL;
4201 }
4202
4203 stub_entry->stub_sec = stub_sec;
4204 stub_entry->stub_offset = 0;
4205 stub_entry->id_sec = link_sec;
4206
906e58ca
NC		 4207 return stub_entry;
4208}
4209
4210/* Store an Arm insn into an output section not processed by
4211 elf32_arm_write_section. */
4212
4213static void
8029a119
NC		 4214put_arm_insn (struct elf32_arm_link_hash_table * htab,
4215 bfd * output_bfd, bfd_vma val, void * ptr)
906e58ca
NC		 4216{
4217 if (htab->byteswap_code != bfd_little_endian (output_bfd))
4218 bfd_putl32 (val, ptr);
4219 else
4220 bfd_putb32 (val, ptr);
4221}
4222
4223/* Store a 16-bit Thumb insn into an output section not processed by
4224 elf32_arm_write_section. */
4225
4226static void
8029a119
NC		 4227put_thumb_insn (struct elf32_arm_link_hash_table * htab,
4228 bfd * output_bfd, bfd_vma val, void * ptr)
906e58ca
NC		 4229{
4230 if (htab->byteswap_code != bfd_little_endian (output_bfd))
4231 bfd_putl16 (val, ptr);
4232 else
4233 bfd_putb16 (val, ptr);
4234}
4235
a504d23a
LA		 4236/* Store a Thumb2 insn into an output section not processed by
4237 elf32_arm_write_section. */
4238
4239static void
4240put_thumb2_insn (struct elf32_arm_link_hash_table * htab,
4241 bfd * output_bfd, bfd_vma val, void * ptr)
4242{
4243 /* T2 instructions are 16-bit streamed. */
4244 if (htab->byteswap_code != bfd_little_endian (output_bfd))
4245 {
4246 bfd_putl16 ((val >> 16) & 0xffff, ptr);
4247 bfd_putl16 ((val & 0xffff), ptr + 2);
4248 }
4249 else
4250 {
4251 bfd_putb16 ((val >> 16) & 0xffff, ptr);
4252 bfd_putb16 ((val & 0xffff), ptr + 2);
4253 }
4254}
4255
0855e32b
NS		 4256/* If it's possible to change R_TYPE to a more efficient access
4257 model, return the new reloc type. */
4258
4259static unsigned
b38cadfb 4260elf32_arm_tls_transition (struct bfd_link_info *info, int r_type,
0855e32b
NS		 4261 struct elf_link_hash_entry *h)
4262{
4263 int is_local = (h == NULL);
4264
0e1862bb
L		 4265 if (bfd_link_pic (info)
4266 || (h && h->root.type == bfd_link_hash_undefweak))
0855e32b
NS		 4267 return r_type;
4268
b38cadfb 4269 /* We do not support relaxations for Old TLS models. */
0855e32b
NS		 4270 switch (r_type)
4271 {
4272 case R_ARM_TLS_GOTDESC:
4273 case R_ARM_TLS_CALL:
4274 case R_ARM_THM_TLS_CALL:
4275 case R_ARM_TLS_DESCSEQ:
4276 case R_ARM_THM_TLS_DESCSEQ:
4277 return is_local ? R_ARM_TLS_LE32 : R_ARM_TLS_IE32;
4278 }
4279
4280 return r_type;
4281}
4282
48229727
JB		 4283static bfd_reloc_status_type elf32_arm_final_link_relocate
4284 (reloc_howto_type *, bfd *, bfd *, asection *, bfd_byte *,
4285 Elf_Internal_Rela *, bfd_vma, struct bfd_link_info *, asection *,
34e77a92
RS		 4286 const char *, unsigned char, enum arm_st_branch_type,
4287 struct elf_link_hash_entry *, bfd_boolean *, char **);
48229727 4288
4563a860
JB		 4289static unsigned int
4290arm_stub_required_alignment (enum elf32_arm_stub_type stub_type)
4291{
4292 switch (stub_type)
4293 {
4294 case arm_stub_a8_veneer_b_cond:
4295 case arm_stub_a8_veneer_b:
4296 case arm_stub_a8_veneer_bl:
4297 return 2;
4298
4299 case arm_stub_long_branch_any_any:
4300 case arm_stub_long_branch_v4t_arm_thumb:
4301 case arm_stub_long_branch_thumb_only:
4302 case arm_stub_long_branch_v4t_thumb_thumb:
4303 case arm_stub_long_branch_v4t_thumb_arm:
4304 case arm_stub_short_branch_v4t_thumb_arm:
4305 case arm_stub_long_branch_any_arm_pic:
4306 case arm_stub_long_branch_any_thumb_pic:
4307 case arm_stub_long_branch_v4t_thumb_thumb_pic:
4308 case arm_stub_long_branch_v4t_arm_thumb_pic:
4309 case arm_stub_long_branch_v4t_thumb_arm_pic:
4310 case arm_stub_long_branch_thumb_only_pic:
0855e32b
NS		 4311 case arm_stub_long_branch_any_tls_pic:
4312 case arm_stub_long_branch_v4t_thumb_tls_pic:
4563a860
JB		 4313 case arm_stub_a8_veneer_blx:
4314 return 4;
b38cadfb 4315
7a89b94e
NC		 4316 case arm_stub_long_branch_arm_nacl:
4317 case arm_stub_long_branch_arm_nacl_pic:
4318 return 16;
4319
4563a860
JB		 4320 default:
4321 abort (); /* Should be unreachable. */
4322 }
4323}
4324
906e58ca
NC		 4325static bfd_boolean
4326arm_build_one_stub (struct bfd_hash_entry *gen_entry,
4327 void * in_arg)
4328{
7a89b94e 4329#define MAXRELOCS 3
906e58ca 4330 struct elf32_arm_stub_hash_entry *stub_entry;
4dfe6ac6 4331 struct elf32_arm_link_hash_table *globals;
906e58ca 4332 struct bfd_link_info *info;
906e58ca
NC		 4333 asection *stub_sec;
4334 bfd *stub_bfd;
906e58ca
NC		 4335 bfd_byte *loc;
4336 bfd_vma sym_value;
4337 int template_size;
4338 int size;
d3ce72d0 4339 const insn_sequence *template_sequence;
906e58ca 4340 int i;
48229727
JB		 4341 int stub_reloc_idx[MAXRELOCS] = {-1, -1};
4342 int stub_reloc_offset[MAXRELOCS] = {0, 0};
4343 int nrelocs = 0;
906e58ca
NC		 4344
4345 /* Massage our args to the form they really have. */
4346 stub_entry = (struct elf32_arm_stub_hash_entry *) gen_entry;
4347 info = (struct bfd_link_info *) in_arg;
4348
4349 globals = elf32_arm_hash_table (info);
4dfe6ac6
NC		 4350 if (globals == NULL)
4351 return FALSE;
906e58ca 4352
906e58ca
NC		 4353 stub_sec = stub_entry->stub_sec;
4354
4dfe6ac6 4355 if ((globals->fix_cortex_a8 < 0)
4563a860
JB		 4356 != (arm_stub_required_alignment (stub_entry->stub_type) == 2))
4357 /* We have to do less-strictly-aligned fixes last. */
eb7c4339 4358 return TRUE;
fe33d2fa 4359
906e58ca
NC		 4360 /* Make a note of the offset within the stubs for this entry. */
4361 stub_entry->stub_offset = stub_sec->size;
4362 loc = stub_sec->contents + stub_entry->stub_offset;
4363
4364 stub_bfd = stub_sec->owner;
4365
906e58ca
NC		 4366 /* This is the address of the stub destination. */
4367 sym_value = (stub_entry->target_value
4368 + stub_entry->target_section->output_offset
4369 + stub_entry->target_section->output_section->vma);
4370
d3ce72d0 4371 template_sequence = stub_entry->stub_template;
461a49ca 4372 template_size = stub_entry->stub_template_size;
906e58ca
NC		 4373
4374 size = 0;
461a49ca 4375 for (i = 0; i < template_size; i++)
906e58ca 4376 {
d3ce72d0 4377 switch (template_sequence[i].type)
461a49ca
DJ		 4378 {
4379 case THUMB16_TYPE:
48229727 4380 {
d3ce72d0
NC		 4381 bfd_vma data = (bfd_vma) template_sequence[i].data;
4382 if (template_sequence[i].reloc_addend != 0)
48229727 4383 {
99059e56
RM		 4384 /* We've borrowed the reloc_addend field to mean we should
4385 insert a condition code into this (Thumb-1 branch)
4386 instruction. See THUMB16_BCOND_INSN. */
4387 BFD_ASSERT ((data & 0xff00) == 0xd000);
4388 data |= ((stub_entry->orig_insn >> 22) & 0xf) << 8;
48229727 4389 }
fe33d2fa 4390 bfd_put_16 (stub_bfd, data, loc + size);
48229727
JB		 4391 size += 2;
4392 }
461a49ca 4393 break;
906e58ca 4394
48229727 4395 case THUMB32_TYPE:
fe33d2fa
CL		 4396 bfd_put_16 (stub_bfd,
4397 (template_sequence[i].data >> 16) & 0xffff,
4398 loc + size);
4399 bfd_put_16 (stub_bfd, template_sequence[i].data & 0xffff,
4400 loc + size + 2);
99059e56
RM		 4401 if (template_sequence[i].r_type != R_ARM_NONE)
4402 {
4403 stub_reloc_idx[nrelocs] = i;
4404 stub_reloc_offset[nrelocs++] = size;
4405 }
4406 size += 4;
4407 break;
48229727 4408
461a49ca 4409 case ARM_TYPE:
fe33d2fa
CL		 4410 bfd_put_32 (stub_bfd, template_sequence[i].data,
4411 loc + size);
461a49ca
DJ		 4412 /* Handle cases where the target is encoded within the
4413 instruction. */
d3ce72d0 4414 if (template_sequence[i].r_type == R_ARM_JUMP24)
461a49ca 4415 {
48229727
JB		 4416 stub_reloc_idx[nrelocs] = i;
4417 stub_reloc_offset[nrelocs++] = size;
461a49ca
DJ		 4418 }
4419 size += 4;
4420 break;
4421
4422 case DATA_TYPE:
d3ce72d0 4423 bfd_put_32 (stub_bfd, template_sequence[i].data, loc + size);
48229727
JB		 4424 stub_reloc_idx[nrelocs] = i;
4425 stub_reloc_offset[nrelocs++] = size;
461a49ca
DJ		 4426 size += 4;
4427 break;
4428
4429 default:
4430 BFD_FAIL ();
4431 return FALSE;
4432 }
906e58ca 4433 }
461a49ca 4434
906e58ca
NC		 4435 stub_sec->size += size;
4436
461a49ca
DJ		 4437 /* Stub size has already been computed in arm_size_one_stub. Check
4438 consistency. */
4439 BFD_ASSERT (size == stub_entry->stub_size);
4440
906e58ca 4441 /* Destination is Thumb. Force bit 0 to 1 to reflect this. */
35fc36a8 4442 if (stub_entry->branch_type == ST_BRANCH_TO_THUMB)
906e58ca
NC		 4443 sym_value |= 1;
4444
48229727
JB		 4445 /* Assume there is at least one and at most MAXRELOCS entries to relocate
4446 in each stub. */
4447 BFD_ASSERT (nrelocs != 0 && nrelocs <= MAXRELOCS);
c820be07 4448
48229727 4449 for (i = 0; i < nrelocs; i++)
d3ce72d0
NC		 4450 if (template_sequence[stub_reloc_idx[i]].r_type == R_ARM_THM_JUMP24
4451 || template_sequence[stub_reloc_idx[i]].r_type == R_ARM_THM_JUMP19
4452 || template_sequence[stub_reloc_idx[i]].r_type == R_ARM_THM_CALL
4453 || template_sequence[stub_reloc_idx[i]].r_type == R_ARM_THM_XPC22)
48229727
JB		 4454 {
4455 Elf_Internal_Rela rel;
4456 bfd_boolean unresolved_reloc;
4457 char *error_message;
35fc36a8
RS		 4458 enum arm_st_branch_type branch_type
4459 = (template_sequence[stub_reloc_idx[i]].r_type != R_ARM_THM_XPC22
4460 ? ST_BRANCH_TO_THUMB : ST_BRANCH_TO_ARM);
48229727
JB		 4461 bfd_vma points_to = sym_value + stub_entry->target_addend;
4462
4463 rel.r_offset = stub_entry->stub_offset + stub_reloc_offset[i];
d3ce72d0 4464 rel.r_info = ELF32_R_INFO (0,
99059e56 4465 template_sequence[stub_reloc_idx[i]].r_type);
d3ce72d0 4466 rel.r_addend = template_sequence[stub_reloc_idx[i]].reloc_addend;
48229727
JB		 4467
4468 if (stub_entry->stub_type == arm_stub_a8_veneer_b_cond && i == 0)
4469 /* The first relocation in the elf32_arm_stub_a8_veneer_b_cond[]
4470 template should refer back to the instruction after the original
4471 branch. */
4472 points_to = sym_value;
4473
33c6a8fc
JB		 4474 /* There may be unintended consequences if this is not true. */
4475 BFD_ASSERT (stub_entry->h == NULL);
4476
48229727
JB		 4477 /* Note: _bfd_final_link_relocate doesn't handle these relocations
4478 properly. We should probably use this function unconditionally,
4479 rather than only for certain relocations listed in the enclosing
4480 conditional, for the sake of consistency. */
4481 elf32_arm_final_link_relocate (elf32_arm_howto_from_type
d3ce72d0 4482 (template_sequence[stub_reloc_idx[i]].r_type),
48229727 4483 stub_bfd, info->output_bfd, stub_sec, stub_sec->contents, &rel,
34e77a92
RS		 4484 points_to, info, stub_entry->target_section, "", STT_FUNC,
4485 branch_type, (struct elf_link_hash_entry *) stub_entry->h,
4486 &unresolved_reloc, &error_message);
48229727
JB		 4487 }
4488 else
4489 {
fe33d2fa
CL		 4490 Elf_Internal_Rela rel;
4491 bfd_boolean unresolved_reloc;
4492 char *error_message;
4493 bfd_vma points_to = sym_value + stub_entry->target_addend
4494 + template_sequence[stub_reloc_idx[i]].reloc_addend;
4495
4496 rel.r_offset = stub_entry->stub_offset + stub_reloc_offset[i];
4497 rel.r_info = ELF32_R_INFO (0,
99059e56 4498 template_sequence[stub_reloc_idx[i]].r_type);
fe33d2fa
CL		 4499 rel.r_addend = 0;
4500
4501 elf32_arm_final_link_relocate (elf32_arm_howto_from_type
4502 (template_sequence[stub_reloc_idx[i]].r_type),
4503 stub_bfd, info->output_bfd, stub_sec, stub_sec->contents, &rel,
34e77a92 4504 points_to, info, stub_entry->target_section, "", STT_FUNC,
35fc36a8 4505 stub_entry->branch_type,
fe33d2fa
CL		 4506 (struct elf_link_hash_entry *) stub_entry->h, &unresolved_reloc,
4507 &error_message);
48229727 4508 }
906e58ca
NC		 4509
4510 return TRUE;
48229727 4511#undef MAXRELOCS
906e58ca
NC		 4512}
4513
48229727
JB		 4514/* Calculate the template, template size and instruction size for a stub.
4515 Return value is the instruction size. */
906e58ca 4516
48229727
JB		 4517static unsigned int
4518find_stub_size_and_template (enum elf32_arm_stub_type stub_type,
4519 const insn_sequence **stub_template,
4520 int *stub_template_size)
906e58ca 4521{
d3ce72d0 4522 const insn_sequence *template_sequence = NULL;
48229727
JB		 4523 int template_size = 0, i;
4524 unsigned int size;
906e58ca 4525
d3ce72d0 4526 template_sequence = stub_definitions[stub_type].template_sequence;
2a229407
AM		 4527 if (stub_template)
4528 *stub_template = template_sequence;
4529
48229727 4530 template_size = stub_definitions[stub_type].template_size;
2a229407
AM		 4531 if (stub_template_size)
4532 *stub_template_size = template_size;
906e58ca
NC		 4533
4534 size = 0;
461a49ca
DJ		 4535 for (i = 0; i < template_size; i++)
4536 {
d3ce72d0 4537 switch (template_sequence[i].type)
461a49ca
DJ		 4538 {
4539 case THUMB16_TYPE:
4540 size += 2;
4541 break;
4542
4543 case ARM_TYPE:
48229727 4544 case THUMB32_TYPE:
461a49ca
DJ		 4545 case DATA_TYPE:
4546 size += 4;
4547 break;
4548
4549 default:
4550 BFD_FAIL ();
2a229407 4551 return 0;
461a49ca
DJ		 4552 }
4553 }
4554
48229727
JB		 4555 return size;
4556}
4557
4558/* As above, but don't actually build the stub. Just bump offset so
4559 we know stub section sizes. */
4560
4561static bfd_boolean
4562arm_size_one_stub (struct bfd_hash_entry *gen_entry,
c7e2358a 4563 void *in_arg ATTRIBUTE_UNUSED)
48229727
JB		 4564{
4565 struct elf32_arm_stub_hash_entry *stub_entry;
d3ce72d0 4566 const insn_sequence *template_sequence;
48229727
JB		 4567 int template_size, size;
4568
4569 /* Massage our args to the form they really have. */
4570 stub_entry = (struct elf32_arm_stub_hash_entry *) gen_entry;
48229727
JB		 4571
4572 BFD_ASSERT((stub_entry->stub_type > arm_stub_none)
4573 && stub_entry->stub_type < ARRAY_SIZE(stub_definitions));
4574
d3ce72d0 4575 size = find_stub_size_and_template (stub_entry->stub_type, &template_sequence,
48229727
JB		 4576 &template_size);
4577
461a49ca 4578 stub_entry->stub_size = size;
d3ce72d0 4579 stub_entry->stub_template = template_sequence;
461a49ca
DJ		 4580 stub_entry->stub_template_size = template_size;
4581
906e58ca
NC		 4582 size = (size + 7) & ~7;
4583 stub_entry->stub_sec->size += size;
461a49ca 4584
906e58ca
NC		 4585 return TRUE;
4586}
4587
4588/* External entry points for sizing and building linker stubs. */
4589
4590/* Set up various things so that we can make a list of input sections
4591 for each output section included in the link. Returns -1 on error,
4592 0 when no stubs will be needed, and 1 on success. */
4593
4594int
4595elf32_arm_setup_section_lists (bfd *output_bfd,
4596 struct bfd_link_info *info)
4597{
4598 bfd *input_bfd;
4599 unsigned int bfd_count;
7292b3ac 4600 unsigned int top_id, top_index;
906e58ca
NC		 4601 asection *section;
4602 asection **input_list, **list;
4603 bfd_size_type amt;
4604 struct elf32_arm_link_hash_table *htab = elf32_arm_hash_table (info);
4605
4dfe6ac6
NC		 4606 if (htab == NULL)
4607 return 0;
906e58ca
NC		 4608 if (! is_elf_hash_table (htab))
4609 return 0;
4610
4611 /* Count the number of input BFDs and find the top input section id. */
4612 for (input_bfd = info->input_bfds, bfd_count = 0, top_id = 0;
4613 input_bfd != NULL;
c72f2fb2 4614 input_bfd = input_bfd->link.next)
906e58ca
NC		 4615 {
4616 bfd_count += 1;
4617 for (section = input_bfd->sections;
4618 section != NULL;
4619 section = section->next)
4620 {
4621 if (top_id < section->id)
4622 top_id = section->id;
4623 }
4624 }
4625 htab->bfd_count = bfd_count;
4626
4627 amt = sizeof (struct map_stub) * (top_id + 1);
21d799b5 4628 htab->stub_group = (struct map_stub *) bfd_zmalloc (amt);
906e58ca
NC		 4629 if (htab->stub_group == NULL)
4630 return -1;
fe33d2fa 4631 htab->top_id = top_id;
906e58ca
NC		 4632
4633 /* We can't use output_bfd->section_count here to find the top output
4634 section index as some sections may have been removed, and
4635 _bfd_strip_section_from_output doesn't renumber the indices. */
4636 for (section = output_bfd->sections, top_index = 0;
4637 section != NULL;
4638 section = section->next)
4639 {
4640 if (top_index < section->index)
4641 top_index = section->index;
4642 }
4643
4644 htab->top_index = top_index;
4645 amt = sizeof (asection *) * (top_index + 1);
21d799b5 4646 input_list = (asection **) bfd_malloc (amt);
906e58ca
NC		 4647 htab->input_list = input_list;
4648 if (input_list == NULL)
4649 return -1;
4650
4651 /* For sections we aren't interested in, mark their entries with a
4652 value we can check later. */
4653 list = input_list + top_index;
4654 do
4655 *list = bfd_abs_section_ptr;
4656 while (list-- != input_list);
4657
4658 for (section = output_bfd->sections;
4659 section != NULL;
4660 section = section->next)
4661 {
4662 if ((section->flags & SEC_CODE) != 0)
4663 input_list[section->index] = NULL;
4664 }
4665
4666 return 1;
4667}
4668
4669/* The linker repeatedly calls this function for each input section,
4670 in the order that input sections are linked into output sections.
4671 Build lists of input sections to determine groupings between which
4672 we may insert linker stubs. */
4673
4674void
4675elf32_arm_next_input_section (struct bfd_link_info *info,
4676 asection *isec)
4677{
4678 struct elf32_arm_link_hash_table *htab = elf32_arm_hash_table (info);
4679
4dfe6ac6
NC		 4680 if (htab == NULL)
4681 return;
4682
906e58ca
NC		 4683 if (isec->output_section->index <= htab->top_index)
4684 {
4685 asection **list = htab->input_list + isec->output_section->index;
4686
a7470592 4687 if (*list != bfd_abs_section_ptr && (isec->flags & SEC_CODE) != 0)
906e58ca
NC		 4688 {
4689 /* Steal the link_sec pointer for our list. */
4690#define PREV_SEC(sec) (htab->stub_group[(sec)->id].link_sec)
4691 /* This happens to make the list in reverse order,
07d72278 4692 which we reverse later. */
906e58ca
NC		 4693 PREV_SEC (isec) = *list;
4694 *list = isec;
4695 }
4696 }
4697}
4698
4699/* See whether we can group stub sections together. Grouping stub
4700 sections may result in fewer stubs. More importantly, we need to
07d72278 4701 put all .init* and .fini* stubs at the end of the .init or
906e58ca
NC		 4702 .fini output sections respectively, because glibc splits the
4703 _init and _fini functions into multiple parts. Putting a stub in
4704 the middle of a function is not a good idea. */
4705
4706static void
4707group_sections (struct elf32_arm_link_hash_table *htab,
4708 bfd_size_type stub_group_size,
07d72278 4709 bfd_boolean stubs_always_after_branch)
906e58ca 4710{
07d72278 4711 asection **list = htab->input_list;
906e58ca
NC		 4712
4713 do
4714 {
4715 asection *tail = *list;
07d72278 4716 asection *head;
906e58ca
NC		 4717
4718 if (tail == bfd_abs_section_ptr)
4719 continue;
4720
07d72278
DJ		 4721 /* Reverse the list: we must avoid placing stubs at the
4722 beginning of the section because the beginning of the text
4723 section may be required for an interrupt vector in bare metal
4724 code. */
4725#define NEXT_SEC PREV_SEC
e780aef2
CL		 4726 head = NULL;
4727 while (tail != NULL)
99059e56
RM		 4728 {
4729 /* Pop from tail. */
4730 asection *item = tail;
4731 tail = PREV_SEC (item);
e780aef2 4732
99059e56
RM		 4733 /* Push on head. */
4734 NEXT_SEC (item) = head;
4735 head = item;
4736 }
07d72278
DJ		 4737
4738 while (head != NULL)
906e58ca
NC		 4739 {
4740 asection *curr;
07d72278 4741 asection *next;
e780aef2
CL		 4742 bfd_vma stub_group_start = head->output_offset;
4743 bfd_vma end_of_next;
906e58ca 4744
07d72278 4745 curr = head;
e780aef2 4746 while (NEXT_SEC (curr) != NULL)
8cd931b7 4747 {
e780aef2
CL		 4748 next = NEXT_SEC (curr);
4749 end_of_next = next->output_offset + next->size;
4750 if (end_of_next - stub_group_start >= stub_group_size)
4751 /* End of NEXT is too far from start, so stop. */
8cd931b7 4752 break;
e780aef2
CL		 4753 /* Add NEXT to the group. */
4754 curr = next;
8cd931b7 4755 }
906e58ca 4756
07d72278 4757 /* OK, the size from the start to the start of CURR is less
906e58ca 4758 than stub_group_size and thus can be handled by one stub
07d72278 4759 section. (Or the head section is itself larger than
906e58ca
NC		 4760 stub_group_size, in which case we may be toast.)
4761 We should really be keeping track of the total size of
4762 stubs added here, as stubs contribute to the final output
7fb9f789 4763 section size. */
906e58ca
NC		 4764 do
4765 {
07d72278 4766 next = NEXT_SEC (head);
906e58ca 4767 /* Set up this stub group. */
07d72278 4768 htab->stub_group[head->id].link_sec = curr;
906e58ca 4769 }
07d72278 4770 while (head != curr && (head = next) != NULL);
906e58ca
NC		 4771
4772 /* But wait, there's more! Input sections up to stub_group_size
07d72278
DJ		 4773 bytes after the stub section can be handled by it too. */
4774 if (!stubs_always_after_branch)
906e58ca 4775 {
e780aef2
CL		 4776 stub_group_start = curr->output_offset + curr->size;
4777
8cd931b7 4778 while (next != NULL)
906e58ca 4779 {
e780aef2
CL		 4780 end_of_next = next->output_offset + next->size;
4781 if (end_of_next - stub_group_start >= stub_group_size)
4782 /* End of NEXT is too far from stubs, so stop. */
8cd931b7 4783 break;
e780aef2 4784 /* Add NEXT to the stub group. */
07d72278
DJ		 4785 head = next;
4786 next = NEXT_SEC (head);
4787 htab->stub_group[head->id].link_sec = curr;
906e58ca
NC		 4788 }
4789 }
07d72278 4790 head = next;
906e58ca
NC		 4791 }
4792 }
07d72278 4793 while (list++ != htab->input_list + htab->top_index);
906e58ca
NC		 4794
4795 free (htab->input_list);
4796#undef PREV_SEC
07d72278 4797#undef NEXT_SEC
906e58ca
NC		 4798}
4799
48229727
JB		 4800/* Comparison function for sorting/searching relocations relating to Cortex-A8
4801 erratum fix. */
4802
4803static int
4804a8_reloc_compare (const void *a, const void *b)
4805{
21d799b5
NC		 4806 const struct a8_erratum_reloc *ra = (const struct a8_erratum_reloc *) a;
4807 const struct a8_erratum_reloc *rb = (const struct a8_erratum_reloc *) b;
48229727
JB		 4808
4809 if (ra->from < rb->from)
4810 return -1;
4811 else if (ra->from > rb->from)
4812 return 1;
4813 else
4814 return 0;
4815}
4816
4817static struct elf_link_hash_entry *find_thumb_glue (struct bfd_link_info *,
4818 const char *, char **);
4819
4820/* Helper function to scan code for sequences which might trigger the Cortex-A8
4821 branch/TLB erratum. Fill in the table described by A8_FIXES_P,
81694485 4822 NUM_A8_FIXES_P, A8_FIX_TABLE_SIZE_P. Returns true if an error occurs, false
48229727
JB		 4823 otherwise. */
4824
81694485
NC		 4825static bfd_boolean
4826cortex_a8_erratum_scan (bfd *input_bfd,
4827 struct bfd_link_info *info,
48229727
JB		 4828 struct a8_erratum_fix **a8_fixes_p,
4829 unsigned int *num_a8_fixes_p,
4830 unsigned int *a8_fix_table_size_p,
4831 struct a8_erratum_reloc *a8_relocs,
eb7c4339
NS		 4832 unsigned int num_a8_relocs,
4833 unsigned prev_num_a8_fixes,
4834 bfd_boolean *stub_changed_p)
48229727
JB		 4835{
4836 asection *section;
4837 struct elf32_arm_link_hash_table *htab = elf32_arm_hash_table (info);
4838 struct a8_erratum_fix *a8_fixes = *a8_fixes_p;
4839 unsigned int num_a8_fixes = *num_a8_fixes_p;
4840 unsigned int a8_fix_table_size = *a8_fix_table_size_p;
4841
4dfe6ac6
NC		 4842 if (htab == NULL)
4843 return FALSE;
4844
48229727
JB		 4845 for (section = input_bfd->sections;
4846 section != NULL;
4847 section = section->next)
4848 {
4849 bfd_byte *contents = NULL;
4850 struct _arm_elf_section_data *sec_data;
4851 unsigned int span;
4852 bfd_vma base_vma;
4853
4854 if (elf_section_type (section) != SHT_PROGBITS
99059e56
RM		 4855 || (elf_section_flags (section) & SHF_EXECINSTR) == 0
4856 || (section->flags & SEC_EXCLUDE) != 0
4857 || (section->sec_info_type == SEC_INFO_TYPE_JUST_SYMS)
4858 || (section->output_section == bfd_abs_section_ptr))
4859 continue;
48229727
JB		 4860
4861 base_vma = section->output_section->vma + section->output_offset;
4862
4863 if (elf_section_data (section)->this_hdr.contents != NULL)
99059e56 4864 contents = elf_section_data (section)->this_hdr.contents;
48229727 4865 else if (! bfd_malloc_and_get_section (input_bfd, section, &contents))
99059e56 4866 return TRUE;
48229727
JB		 4867
4868 sec_data = elf32_arm_section_data (section);
4869
4870 for (span = 0; span < sec_data->mapcount; span++)
99059e56
RM		 4871 {
4872 unsigned int span_start = sec_data->map[span].vma;
4873 unsigned int span_end = (span == sec_data->mapcount - 1)
4874 ? section->size : sec_data->map[span + 1].vma;
4875 unsigned int i;
4876 char span_type = sec_data->map[span].type;
4877 bfd_boolean last_was_32bit = FALSE, last_was_branch = FALSE;
4878
4879 if (span_type != 't')
4880 continue;
4881
4882 /* Span is entirely within a single 4KB region: skip scanning. */
4883 if (((base_vma + span_start) & ~0xfff)
48229727 4884 == ((base_vma + span_end) & ~0xfff))
99059e56
RM		 4885 continue;
4886
4887 /* Scan for 32-bit Thumb-2 branches which span two 4K regions, where:
4888
4889 * The opcode is BLX.W, BL.W, B.W, Bcc.W
4890 * The branch target is in the same 4KB region as the
4891 first half of the branch.
4892 * The instruction before the branch is a 32-bit
4893 length non-branch instruction. */
4894 for (i = span_start; i < span_end;)
4895 {
4896 unsigned int insn = bfd_getl16 (&contents[i]);
4897 bfd_boolean insn_32bit = FALSE, is_blx = FALSE, is_b = FALSE;
48229727
JB		 4898 bfd_boolean is_bl = FALSE, is_bcc = FALSE, is_32bit_branch;
4899
99059e56
RM		 4900 if ((insn & 0xe000) == 0xe000 && (insn & 0x1800) != 0x0000)
4901 insn_32bit = TRUE;
48229727
JB		 4902
4903 if (insn_32bit)
99059e56
RM		 4904 {
4905 /* Load the rest of the insn (in manual-friendly order). */
4906 insn = (insn << 16) | bfd_getl16 (&contents[i + 2]);
4907
4908 /* Encoding T4: B<c>.W. */
4909 is_b = (insn & 0xf800d000) == 0xf0009000;
4910 /* Encoding T1: BL<c>.W. */
4911 is_bl = (insn & 0xf800d000) == 0xf000d000;
4912 /* Encoding T2: BLX<c>.W. */
4913 is_blx = (insn & 0xf800d000) == 0xf000c000;
48229727
JB		 4914 /* Encoding T3: B<c>.W (not permitted in IT block). */
4915 is_bcc = (insn & 0xf800d000) == 0xf0008000
4916 && (insn & 0x07f00000) != 0x03800000;
4917 }
4918
4919 is_32bit_branch = is_b || is_bl || is_blx || is_bcc;
fe33d2fa 4920
99059e56 4921 if (((base_vma + i) & 0xfff) == 0xffe
81694485
NC		 4922 && insn_32bit
4923 && is_32bit_branch
4924 && last_was_32bit
4925 && ! last_was_branch)
99059e56
RM		 4926 {
4927 bfd_signed_vma offset = 0;
4928 bfd_boolean force_target_arm = FALSE;
48229727 4929 bfd_boolean force_target_thumb = FALSE;
99059e56
RM		 4930 bfd_vma target;
4931 enum elf32_arm_stub_type stub_type = arm_stub_none;
4932 struct a8_erratum_reloc key, *found;
4933 bfd_boolean use_plt = FALSE;
48229727 4934
99059e56
RM		 4935 key.from = base_vma + i;
4936 found = (struct a8_erratum_reloc *)
4937 bsearch (&key, a8_relocs, num_a8_relocs,
4938 sizeof (struct a8_erratum_reloc),
4939 &a8_reloc_compare);
48229727
JB		 4940
4941 if (found)
4942 {
4943 char *error_message = NULL;
4944 struct elf_link_hash_entry *entry;
4945
4946 /* We don't care about the error returned from this
99059e56 4947 function, only if there is glue or not. */
48229727
JB		 4948 entry = find_thumb_glue (info, found->sym_name,
4949 &error_message);
4950
4951 if (entry)
4952 found->non_a8_stub = TRUE;
4953
92750f34 4954 /* Keep a simpler condition, for the sake of clarity. */
362d30a1 4955 if (htab->root.splt != NULL && found->hash != NULL
92750f34
DJ		 4956 && found->hash->root.plt.offset != (bfd_vma) -1)
4957 use_plt = TRUE;
4958
4959 if (found->r_type == R_ARM_THM_CALL)
4960 {
35fc36a8
RS		 4961 if (found->branch_type == ST_BRANCH_TO_ARM
4962 || use_plt)
92750f34
DJ		 4963 force_target_arm = TRUE;
4964 else
4965 force_target_thumb = TRUE;
4966 }
48229727
JB		 4967 }
4968
99059e56 4969 /* Check if we have an offending branch instruction. */
48229727
JB		 4970
4971 if (found && found->non_a8_stub)
4972 /* We've already made a stub for this instruction, e.g.
4973 it's a long branch or a Thumb->ARM stub. Assume that
4974 stub will suffice to work around the A8 erratum (see
4975 setting of always_after_branch above). */
4976 ;
99059e56
RM		 4977 else if (is_bcc)
4978 {
4979 offset = (insn & 0x7ff) << 1;
4980 offset |= (insn & 0x3f0000) >> 4;
4981 offset |= (insn & 0x2000) ? 0x40000 : 0;
4982 offset |= (insn & 0x800) ? 0x80000 : 0;
4983 offset |= (insn & 0x4000000) ? 0x100000 : 0;
4984 if (offset & 0x100000)
4985 offset |= ~ ((bfd_signed_vma) 0xfffff);
4986 stub_type = arm_stub_a8_veneer_b_cond;
4987 }
4988 else if (is_b || is_bl || is_blx)
4989 {
4990 int s = (insn & 0x4000000) != 0;
4991 int j1 = (insn & 0x2000) != 0;
4992 int j2 = (insn & 0x800) != 0;
4993 int i1 = !(j1 ^ s);
4994 int i2 = !(j2 ^ s);
4995
4996 offset = (insn & 0x7ff) << 1;
4997 offset |= (insn & 0x3ff0000) >> 4;
4998 offset |= i2 << 22;
4999 offset |= i1 << 23;
5000 offset |= s << 24;
5001 if (offset & 0x1000000)
5002 offset |= ~ ((bfd_signed_vma) 0xffffff);
5003
5004 if (is_blx)
5005 offset &= ~ ((bfd_signed_vma) 3);
5006
5007 stub_type = is_blx ? arm_stub_a8_veneer_blx :
5008 is_bl ? arm_stub_a8_veneer_bl : arm_stub_a8_veneer_b;
5009 }
5010
5011 if (stub_type != arm_stub_none)
5012 {
5013 bfd_vma pc_for_insn = base_vma + i + 4;
48229727
JB		 5014
5015 /* The original instruction is a BL, but the target is
99059e56 5016 an ARM instruction. If we were not making a stub,
48229727
JB		 5017 the BL would have been converted to a BLX. Use the
5018 BLX stub instead in that case. */
5019 if (htab->use_blx && force_target_arm
5020 && stub_type == arm_stub_a8_veneer_bl)
5021 {
5022 stub_type = arm_stub_a8_veneer_blx;
5023 is_blx = TRUE;
5024 is_bl = FALSE;
5025 }
5026 /* Conversely, if the original instruction was
5027 BLX but the target is Thumb mode, use the BL
5028 stub. */
5029 else if (force_target_thumb
5030 && stub_type == arm_stub_a8_veneer_blx)
5031 {
5032 stub_type = arm_stub_a8_veneer_bl;
5033 is_blx = FALSE;
5034 is_bl = TRUE;
5035 }
5036
99059e56
RM		 5037 if (is_blx)
5038 pc_for_insn &= ~ ((bfd_vma) 3);
48229727 5039
99059e56
RM		 5040 /* If we found a relocation, use the proper destination,
5041 not the offset in the (unrelocated) instruction.
48229727
JB		 5042 Note this is always done if we switched the stub type
5043 above. */
99059e56
RM		 5044 if (found)
5045 offset =
81694485 5046 (bfd_signed_vma) (found->destination - pc_for_insn);
48229727 5047
99059e56
RM		 5048 /* If the stub will use a Thumb-mode branch to a
5049 PLT target, redirect it to the preceding Thumb
5050 entry point. */
5051 if (stub_type != arm_stub_a8_veneer_blx && use_plt)
5052 offset -= PLT_THUMB_STUB_SIZE;
7d24e6a6 5053
99059e56 5054 target = pc_for_insn + offset;
48229727 5055
99059e56
RM		 5056 /* The BLX stub is ARM-mode code. Adjust the offset to
5057 take the different PC value (+8 instead of +4) into
48229727 5058 account. */
99059e56
RM		 5059 if (stub_type == arm_stub_a8_veneer_blx)
5060 offset += 4;
5061
5062 if (((base_vma + i) & ~0xfff) == (target & ~0xfff))
5063 {
5064 char *stub_name = NULL;
5065
5066 if (num_a8_fixes == a8_fix_table_size)
5067 {
5068 a8_fix_table_size *= 2;
5069 a8_fixes = (struct a8_erratum_fix *)
5070 bfd_realloc (a8_fixes,
5071 sizeof (struct a8_erratum_fix)
5072 * a8_fix_table_size);
5073 }
48229727 5074
eb7c4339
NS		 5075 if (num_a8_fixes < prev_num_a8_fixes)
5076 {
5077 /* If we're doing a subsequent scan,
5078 check if we've found the same fix as
5079 before, and try and reuse the stub
5080 name. */
5081 stub_name = a8_fixes[num_a8_fixes].stub_name;
5082 if ((a8_fixes[num_a8_fixes].section != section)
5083 || (a8_fixes[num_a8_fixes].offset != i))
5084 {
5085 free (stub_name);
5086 stub_name = NULL;
5087 *stub_changed_p = TRUE;
5088 }
5089 }
5090
5091 if (!stub_name)
5092 {
21d799b5 5093 stub_name = (char *) bfd_malloc (8 + 1 + 8 + 1);
eb7c4339
NS		 5094 if (stub_name != NULL)
5095 sprintf (stub_name, "%x:%x", section->id, i);
5096 }
48229727 5097
99059e56
RM		 5098 a8_fixes[num_a8_fixes].input_bfd = input_bfd;
5099 a8_fixes[num_a8_fixes].section = section;
5100 a8_fixes[num_a8_fixes].offset = i;
5101 a8_fixes[num_a8_fixes].addend = offset;
5102 a8_fixes[num_a8_fixes].orig_insn = insn;
5103 a8_fixes[num_a8_fixes].stub_name = stub_name;
5104 a8_fixes[num_a8_fixes].stub_type = stub_type;
5105 a8_fixes[num_a8_fixes].branch_type =
35fc36a8 5106 is_blx ? ST_BRANCH_TO_ARM : ST_BRANCH_TO_THUMB;
48229727 5107
99059e56
RM		 5108 num_a8_fixes++;
5109 }
5110 }
5111 }
48229727 5112
99059e56
RM		 5113 i += insn_32bit ? 4 : 2;
5114 last_was_32bit = insn_32bit;
48229727 5115 last_was_branch = is_32bit_branch;
99059e56
RM		 5116 }
5117 }
48229727
JB		 5118
5119 if (elf_section_data (section)->this_hdr.contents == NULL)
99059e56 5120 free (contents);
48229727 5121 }
fe33d2fa 5122
48229727
JB		 5123 *a8_fixes_p = a8_fixes;
5124 *num_a8_fixes_p = num_a8_fixes;
5125 *a8_fix_table_size_p = a8_fix_table_size;
fe33d2fa 5126
81694485 5127 return FALSE;
48229727
JB		 5128}
5129
906e58ca
NC		 5130/* Determine and set the size of the stub section for a final link.
5131
5132 The basic idea here is to examine all the relocations looking for
5133 PC-relative calls to a target that is unreachable with a "bl"
5134 instruction. */
5135
5136bfd_boolean
5137elf32_arm_size_stubs (bfd *output_bfd,
5138 bfd *stub_bfd,
5139 struct bfd_link_info *info,
5140 bfd_signed_vma group_size,
7a89b94e
NC		 5141 asection * (*add_stub_section) (const char *, asection *,
5142 unsigned int),
906e58ca
NC		 5143 void (*layout_sections_again) (void))
5144{
5145 bfd_size_type stub_group_size;
07d72278 5146 bfd_boolean stubs_always_after_branch;
906e58ca 5147 struct elf32_arm_link_hash_table *htab = elf32_arm_hash_table (info);
48229727 5148 struct a8_erratum_fix *a8_fixes = NULL;
eb7c4339 5149 unsigned int num_a8_fixes = 0, a8_fix_table_size = 10;
48229727
JB		 5150 struct a8_erratum_reloc *a8_relocs = NULL;
5151 unsigned int num_a8_relocs = 0, a8_reloc_table_size = 10, i;
5152
4dfe6ac6
NC		 5153 if (htab == NULL)
5154 return FALSE;
5155
48229727
JB		 5156 if (htab->fix_cortex_a8)
5157 {
21d799b5 5158 a8_fixes = (struct a8_erratum_fix *)
99059e56 5159 bfd_zmalloc (sizeof (struct a8_erratum_fix) * a8_fix_table_size);
21d799b5 5160 a8_relocs = (struct a8_erratum_reloc *)
99059e56 5161 bfd_zmalloc (sizeof (struct a8_erratum_reloc) * a8_reloc_table_size);
48229727 5162 }
906e58ca
NC		 5163
5164 /* Propagate mach to stub bfd, because it may not have been
5165 finalized when we created stub_bfd. */
5166 bfd_set_arch_mach (stub_bfd, bfd_get_arch (output_bfd),
5167 bfd_get_mach (output_bfd));
5168
5169 /* Stash our params away. */
5170 htab->stub_bfd = stub_bfd;
5171 htab->add_stub_section = add_stub_section;
5172 htab->layout_sections_again = layout_sections_again;
07d72278 5173 stubs_always_after_branch = group_size < 0;
48229727
JB		 5174
5175 /* The Cortex-A8 erratum fix depends on stubs not being in the same 4K page
5176 as the first half of a 32-bit branch straddling two 4K pages. This is a
5177 crude way of enforcing that. */
5178 if (htab->fix_cortex_a8)
5179 stubs_always_after_branch = 1;
5180
906e58ca
NC		 5181 if (group_size < 0)
5182 stub_group_size = -group_size;
5183 else
5184 stub_group_size = group_size;
5185
5186 if (stub_group_size == 1)
5187 {
5188 /* Default values. */
5189 /* Thumb branch range is +-4MB has to be used as the default
5190 maximum size (a given section can contain both ARM and Thumb
5191 code, so the worst case has to be taken into account).
5192
5193 This value is 24K less than that, which allows for 2025
5194 12-byte stubs. If we exceed that, then we will fail to link.
5195 The user will have to relink with an explicit group size
5196 option. */
5197 stub_group_size = 4170000;
5198 }
5199
07d72278 5200 group_sections (htab, stub_group_size, stubs_always_after_branch);
906e58ca 5201
3ae046cc
NS		 5202 /* If we're applying the cortex A8 fix, we need to determine the
5203 program header size now, because we cannot change it later --
5204 that could alter section placements. Notice the A8 erratum fix
5205 ends up requiring the section addresses to remain unchanged
5206 modulo the page size. That's something we cannot represent
5207 inside BFD, and we don't want to force the section alignment to
5208 be the page size. */
5209 if (htab->fix_cortex_a8)
5210 (*htab->layout_sections_again) ();
5211
906e58ca
NC		 5212 while (1)
5213 {
5214 bfd *input_bfd;
5215 unsigned int bfd_indx;
5216 asection *stub_sec;
eb7c4339
NS		 5217 bfd_boolean stub_changed = FALSE;
5218 unsigned prev_num_a8_fixes = num_a8_fixes;
906e58ca 5219
48229727 5220 num_a8_fixes = 0;
906e58ca
NC		 5221 for (input_bfd = info->input_bfds, bfd_indx = 0;
5222 input_bfd != NULL;
c72f2fb2 5223 input_bfd = input_bfd->link.next, bfd_indx++)
906e58ca
NC		 5224 {
5225 Elf_Internal_Shdr *symtab_hdr;
5226 asection *section;
5227 Elf_Internal_Sym *local_syms = NULL;
5228
99059e56
RM		 5229 if (!is_arm_elf (input_bfd))
5230 continue;
adbcc655 5231
48229727
JB		 5232 num_a8_relocs = 0;
5233
906e58ca
NC		 5234 /* We'll need the symbol table in a second. */
5235 symtab_hdr = &elf_tdata (input_bfd)->symtab_hdr;
5236 if (symtab_hdr->sh_info == 0)
5237 continue;
5238
5239 /* Walk over each section attached to the input bfd. */
5240 for (section = input_bfd->sections;
5241 section != NULL;
5242 section = section->next)
5243 {
5244 Elf_Internal_Rela *internal_relocs, *irelaend, *irela;
5245
5246 /* If there aren't any relocs, then there's nothing more
5247 to do. */
5248 if ((section->flags & SEC_RELOC) == 0
5249 || section->reloc_count == 0
5250 || (section->flags & SEC_CODE) == 0)
5251 continue;
5252
5253 /* If this section is a link-once section that will be
5254 discarded, then don't create any stubs. */
5255 if (section->output_section == NULL
5256 || section->output_section->owner != output_bfd)
5257 continue;
5258
5259 /* Get the relocs. */
5260 internal_relocs
5261 = _bfd_elf_link_read_relocs (input_bfd, section, NULL,
5262 NULL, info->keep_memory);
5263 if (internal_relocs == NULL)
5264 goto error_ret_free_local;
5265
5266 /* Now examine each relocation. */
5267 irela = internal_relocs;
5268 irelaend = irela + section->reloc_count;
5269 for (; irela < irelaend; irela++)
5270 {
5271 unsigned int r_type, r_indx;
5272 enum elf32_arm_stub_type stub_type;
5273 struct elf32_arm_stub_hash_entry *stub_entry;
5274 asection *sym_sec;
5275 bfd_vma sym_value;
5276 bfd_vma destination;
5277 struct elf32_arm_link_hash_entry *hash;
7413f23f 5278 const char *sym_name;
906e58ca
NC		 5279 char *stub_name;
5280 const asection *id_sec;
34e77a92 5281 unsigned char st_type;
35fc36a8 5282 enum arm_st_branch_type branch_type;
48229727 5283 bfd_boolean created_stub = FALSE;
906e58ca
NC		 5284
5285 r_type = ELF32_R_TYPE (irela->r_info);
5286 r_indx = ELF32_R_SYM (irela->r_info);
5287
5288 if (r_type >= (unsigned int) R_ARM_max)
5289 {
5290 bfd_set_error (bfd_error_bad_value);
5291 error_ret_free_internal:
5292 if (elf_section_data (section)->relocs == NULL)
5293 free (internal_relocs);
5294 goto error_ret_free_local;
5295 }
b38cadfb 5296
0855e32b
NS		 5297 hash = NULL;
5298 if (r_indx >= symtab_hdr->sh_info)
5299 hash = elf32_arm_hash_entry
5300 (elf_sym_hashes (input_bfd)
5301 [r_indx - symtab_hdr->sh_info]);
b38cadfb 5302
0855e32b
NS		 5303 /* Only look for stubs on branch instructions, or
5304 non-relaxed TLSCALL */
906e58ca 5305 if ((r_type != (unsigned int) R_ARM_CALL)
155d87d7
CL		 5306 && (r_type != (unsigned int) R_ARM_THM_CALL)
5307 && (r_type != (unsigned int) R_ARM_JUMP24)
48229727
JB		 5308 && (r_type != (unsigned int) R_ARM_THM_JUMP19)
5309 && (r_type != (unsigned int) R_ARM_THM_XPC22)
155d87d7 5310 && (r_type != (unsigned int) R_ARM_THM_JUMP24)
0855e32b
NS		 5311 && (r_type != (unsigned int) R_ARM_PLT32)
5312 && !((r_type == (unsigned int) R_ARM_TLS_CALL
5313 || r_type == (unsigned int) R_ARM_THM_TLS_CALL)
5314 && r_type == elf32_arm_tls_transition
5315 (info, r_type, &hash->root)
5316 && ((hash ? hash->tls_type
5317 : (elf32_arm_local_got_tls_type
5318 (input_bfd)[r_indx]))
5319 & GOT_TLS_GDESC) != 0))
906e58ca
NC		 5320 continue;
5321
5322 /* Now determine the call target, its name, value,
5323 section. */
5324 sym_sec = NULL;
5325 sym_value = 0;
5326 destination = 0;
7413f23f 5327 sym_name = NULL;
b38cadfb 5328
0855e32b
NS		 5329 if (r_type == (unsigned int) R_ARM_TLS_CALL
5330 || r_type == (unsigned int) R_ARM_THM_TLS_CALL)
5331 {
5332 /* A non-relaxed TLS call. The target is the
5333 plt-resident trampoline and nothing to do
5334 with the symbol. */
5335 BFD_ASSERT (htab->tls_trampoline > 0);
5336 sym_sec = htab->root.splt;
5337 sym_value = htab->tls_trampoline;
5338 hash = 0;
34e77a92 5339 st_type = STT_FUNC;
35fc36a8 5340 branch_type = ST_BRANCH_TO_ARM;
0855e32b
NS		 5341 }
5342 else if (!hash)
906e58ca
NC		 5343 {
5344 /* It's a local symbol. */
5345 Elf_Internal_Sym *sym;
906e58ca
NC		 5346
5347 if (local_syms == NULL)
5348 {
5349 local_syms
5350 = (Elf_Internal_Sym *) symtab_hdr->contents;
5351 if (local_syms == NULL)
5352 local_syms
5353 = bfd_elf_get_elf_syms (input_bfd, symtab_hdr,
5354 symtab_hdr->sh_info, 0,
5355 NULL, NULL, NULL);
5356 if (local_syms == NULL)
5357 goto error_ret_free_internal;
5358 }
5359
5360 sym = local_syms + r_indx;
f6d250ce
TS		 5361 if (sym->st_shndx == SHN_UNDEF)
5362 sym_sec = bfd_und_section_ptr;
5363 else if (sym->st_shndx == SHN_ABS)
5364 sym_sec = bfd_abs_section_ptr;
5365 else if (sym->st_shndx == SHN_COMMON)
5366 sym_sec = bfd_com_section_ptr;
5367 else
5368 sym_sec =
5369 bfd_section_from_elf_index (input_bfd, sym->st_shndx);
5370
ffcb4889
NS		 5371 if (!sym_sec)
5372 /* This is an undefined symbol. It can never
6a631e86 5373 be resolved. */
ffcb4889 5374 continue;
fe33d2fa 5375
906e58ca
NC		 5376 if (ELF_ST_TYPE (sym->st_info) != STT_SECTION)
5377 sym_value = sym->st_value;
5378 destination = (sym_value + irela->r_addend
5379 + sym_sec->output_offset
5380 + sym_sec->output_section->vma);
34e77a92 5381 st_type = ELF_ST_TYPE (sym->st_info);
35fc36a8 5382 branch_type = ARM_SYM_BRANCH_TYPE (sym);
7413f23f
DJ		 5383 sym_name
5384 = bfd_elf_string_from_elf_section (input_bfd,
5385 symtab_hdr->sh_link,
5386 sym->st_name);
906e58ca
NC		 5387 }
5388 else
5389 {
5390 /* It's an external symbol. */
906e58ca
NC		 5391 while (hash->root.root.type == bfd_link_hash_indirect
5392 || hash->root.root.type == bfd_link_hash_warning)
5393 hash = ((struct elf32_arm_link_hash_entry *)
5394 hash->root.root.u.i.link);
5395
5396 if (hash->root.root.type == bfd_link_hash_defined
5397 || hash->root.root.type == bfd_link_hash_defweak)
5398 {
5399 sym_sec = hash->root.root.u.def.section;
5400 sym_value = hash->root.root.u.def.value;
022f8312
CL		 5401
5402 struct elf32_arm_link_hash_table *globals =
5403 elf32_arm_hash_table (info);
5404
5405 /* For a destination in a shared library,
5406 use the PLT stub as target address to
5407 decide whether a branch stub is
5408 needed. */
4dfe6ac6 5409 if (globals != NULL
362d30a1 5410 && globals->root.splt != NULL
4dfe6ac6 5411 && hash != NULL
022f8312
CL		 5412 && hash->root.plt.offset != (bfd_vma) -1)
5413 {
362d30a1 5414 sym_sec = globals->root.splt;
022f8312
CL		 5415 sym_value = hash->root.plt.offset;
5416 if (sym_sec->output_section != NULL)
5417 destination = (sym_value
5418 + sym_sec->output_offset
5419 + sym_sec->output_section->vma);
5420 }
5421 else if (sym_sec->output_section != NULL)
906e58ca
NC		 5422 destination = (sym_value + irela->r_addend
5423 + sym_sec->output_offset
5424 + sym_sec->output_section->vma);
5425 }
69c5861e
CL		 5426 else if ((hash->root.root.type == bfd_link_hash_undefined)
5427 || (hash->root.root.type == bfd_link_hash_undefweak))
5428 {
5429 /* For a shared library, use the PLT stub as
5430 target address to decide whether a long
5431 branch stub is needed.
5432 For absolute code, they cannot be handled. */
5433 struct elf32_arm_link_hash_table *globals =
5434 elf32_arm_hash_table (info);
5435
4dfe6ac6 5436 if (globals != NULL
362d30a1 5437 && globals->root.splt != NULL
4dfe6ac6 5438 && hash != NULL
69c5861e
CL		 5439 && hash->root.plt.offset != (bfd_vma) -1)
5440 {
362d30a1 5441 sym_sec = globals->root.splt;
69c5861e
CL		 5442 sym_value = hash->root.plt.offset;
5443 if (sym_sec->output_section != NULL)
5444 destination = (sym_value
5445 + sym_sec->output_offset
5446 + sym_sec->output_section->vma);
5447 }
5448 else
5449 continue;
5450 }
906e58ca
NC		 5451 else
5452 {
5453 bfd_set_error (bfd_error_bad_value);
5454 goto error_ret_free_internal;
5455 }
34e77a92 5456 st_type = hash->root.type;
35fc36a8 5457 branch_type = hash->root.target_internal;
7413f23f 5458 sym_name = hash->root.root.root.string;
906e58ca
NC		 5459 }
5460
48229727 5461 do
7413f23f 5462 {
48229727
JB		 5463 /* Determine what (if any) linker stub is needed. */
5464 stub_type = arm_type_of_stub (info, section, irela,
34e77a92
RS		 5465 st_type, &branch_type,
5466 hash, destination, sym_sec,
48229727
JB		 5467 input_bfd, sym_name);
5468 if (stub_type == arm_stub_none)
5469 break;
5470
5471 /* Support for grouping stub sections. */
5472 id_sec = htab->stub_group[section->id].link_sec;
5473
5474 /* Get the name of this stub. */
5475 stub_name = elf32_arm_stub_name (id_sec, sym_sec, hash,
fe33d2fa 5476 irela, stub_type);
48229727
JB		 5477 if (!stub_name)
5478 goto error_ret_free_internal;
5479
5480 /* We've either created a stub for this reloc already,
5481 or we are about to. */
5482 created_stub = TRUE;
5483
5484 stub_entry = arm_stub_hash_lookup
5485 (&htab->stub_hash_table, stub_name,
5486 FALSE, FALSE);
5487 if (stub_entry != NULL)
5488 {
5489 /* The proper stub has already been created. */
5490 free (stub_name);
eb7c4339 5491 stub_entry->target_value = sym_value;
48229727
JB		 5492 break;
5493 }
7413f23f 5494
48229727
JB		 5495 stub_entry = elf32_arm_add_stub (stub_name, section,
5496 htab);
5497 if (stub_entry == NULL)
5498 {
5499 free (stub_name);
5500 goto error_ret_free_internal;
5501 }
7413f23f 5502
99059e56
RM		 5503 stub_entry->target_value = sym_value;
5504 stub_entry->target_section = sym_sec;
5505 stub_entry->stub_type = stub_type;
5506 stub_entry->h = hash;
5507 stub_entry->branch_type = branch_type;
5508
5509 if (sym_name == NULL)
5510 sym_name = "unnamed";
5511 stub_entry->output_name = (char *)
5512 bfd_alloc (htab->stub_bfd,
5513 sizeof (THUMB2ARM_GLUE_ENTRY_NAME)
5514 + strlen (sym_name));
5515 if (stub_entry->output_name == NULL)
5516 {
5517 free (stub_name);
5518 goto error_ret_free_internal;
5519 }
5520
5521 /* For historical reasons, use the existing names for
5522 ARM-to-Thumb and Thumb-to-ARM stubs. */
5523 if ((r_type == (unsigned int) R_ARM_THM_CALL
c5423981
TG		 5524 || r_type == (unsigned int) R_ARM_THM_JUMP24
5525 || r_type == (unsigned int) R_ARM_THM_JUMP19)
35fc36a8 5526 && branch_type == ST_BRANCH_TO_ARM)
99059e56
RM		 5527 sprintf (stub_entry->output_name,
5528 THUMB2ARM_GLUE_ENTRY_NAME, sym_name);
5529 else if ((r_type == (unsigned int) R_ARM_CALL
35fc36a8
RS		 5530 || r_type == (unsigned int) R_ARM_JUMP24)
5531 && branch_type == ST_BRANCH_TO_THUMB)
99059e56
RM		 5532 sprintf (stub_entry->output_name,
5533 ARM2THUMB_GLUE_ENTRY_NAME, sym_name);
5534 else
5535 sprintf (stub_entry->output_name, STUB_ENTRY_NAME,
5536 sym_name);
5537
5538 stub_changed = TRUE;
5539 }
5540 while (0);
5541
5542 /* Look for relocations which might trigger Cortex-A8
5543 erratum. */
5544 if (htab->fix_cortex_a8
5545 && (r_type == (unsigned int) R_ARM_THM_JUMP24
5546 || r_type == (unsigned int) R_ARM_THM_JUMP19
5547 || r_type == (unsigned int) R_ARM_THM_CALL
5548 || r_type == (unsigned int) R_ARM_THM_XPC22))
5549 {
5550 bfd_vma from = section->output_section->vma
5551 + section->output_offset
5552 + irela->r_offset;
5553
5554 if ((from & 0xfff) == 0xffe)
5555 {
5556 /* Found a candidate. Note we haven't checked the
5557 destination is within 4K here: if we do so (and
5558 don't create an entry in a8_relocs) we can't tell
5559 that a branch should have been relocated when
5560 scanning later. */
5561 if (num_a8_relocs == a8_reloc_table_size)
5562 {
5563 a8_reloc_table_size *= 2;
5564 a8_relocs = (struct a8_erratum_reloc *)
5565 bfd_realloc (a8_relocs,
5566 sizeof (struct a8_erratum_reloc)
5567 * a8_reloc_table_size);
5568 }
5569
5570 a8_relocs[num_a8_relocs].from = from;
5571 a8_relocs[num_a8_relocs].destination = destination;
5572 a8_relocs[num_a8_relocs].r_type = r_type;
5573 a8_relocs[num_a8_relocs].branch_type = branch_type;
5574 a8_relocs[num_a8_relocs].sym_name = sym_name;
5575 a8_relocs[num_a8_relocs].non_a8_stub = created_stub;
5576 a8_relocs[num_a8_relocs].hash = hash;
5577
5578 num_a8_relocs++;
5579 }
5580 }
906e58ca
NC		 5581 }
5582
99059e56
RM		 5583 /* We're done with the internal relocs, free them. */
5584 if (elf_section_data (section)->relocs == NULL)
5585 free (internal_relocs);
5586 }
48229727 5587
99059e56 5588 if (htab->fix_cortex_a8)
48229727 5589 {
99059e56
RM		 5590 /* Sort relocs which might apply to Cortex-A8 erratum. */
5591 qsort (a8_relocs, num_a8_relocs,
eb7c4339 5592 sizeof (struct a8_erratum_reloc),
99059e56 5593 &a8_reloc_compare);
48229727 5594
99059e56
RM		 5595 /* Scan for branches which might trigger Cortex-A8 erratum. */
5596 if (cortex_a8_erratum_scan (input_bfd, info, &a8_fixes,
48229727 5597 &num_a8_fixes, &a8_fix_table_size,
eb7c4339
NS		 5598 a8_relocs, num_a8_relocs,
5599 prev_num_a8_fixes, &stub_changed)
5600 != 0)
48229727 5601 goto error_ret_free_local;
5e681ec4 5602 }
5e681ec4
PB		 5603 }
5604
eb7c4339 5605 if (prev_num_a8_fixes != num_a8_fixes)
99059e56 5606 stub_changed = TRUE;
48229727 5607
906e58ca
NC		 5608 if (!stub_changed)
5609 break;
5e681ec4 5610
906e58ca
NC		 5611 /* OK, we've added some stubs. Find out the new size of the
5612 stub sections. */
5613 for (stub_sec = htab->stub_bfd->sections;
5614 stub_sec != NULL;
5615 stub_sec = stub_sec->next)
3e6b1042
DJ		 5616 {
5617 /* Ignore non-stub sections. */
5618 if (!strstr (stub_sec->name, STUB_SUFFIX))
5619 continue;
5620
5621 stub_sec->size = 0;
5622 }
b34b2d70 5623
906e58ca
NC		 5624 bfd_hash_traverse (&htab->stub_hash_table, arm_size_one_stub, htab);
5625
48229727
JB		 5626 /* Add Cortex-A8 erratum veneers to stub section sizes too. */
5627 if (htab->fix_cortex_a8)
99059e56
RM		 5628 for (i = 0; i < num_a8_fixes; i++)
5629 {
48229727
JB		 5630 stub_sec = elf32_arm_create_or_find_stub_sec (NULL,
5631 a8_fixes[i].section, htab);
5632
5633 if (stub_sec == NULL)
5634 goto error_ret_free_local;
5635
99059e56
RM		 5636 stub_sec->size
5637 += find_stub_size_and_template (a8_fixes[i].stub_type, NULL,
5638 NULL);
5639 }
48229727
JB		 5640
5641
906e58ca
NC		 5642 /* Ask the linker to do its stuff. */
5643 (*htab->layout_sections_again) ();
ba93b8ac
DJ		 5644 }
5645
48229727
JB		 5646 /* Add stubs for Cortex-A8 erratum fixes now. */
5647 if (htab->fix_cortex_a8)
5648 {
5649 for (i = 0; i < num_a8_fixes; i++)
99059e56
RM		 5650 {
5651 struct elf32_arm_stub_hash_entry *stub_entry;
5652 char *stub_name = a8_fixes[i].stub_name;
5653 asection *section = a8_fixes[i].section;
5654 unsigned int section_id = a8_fixes[i].section->id;
5655 asection *link_sec = htab->stub_group[section_id].link_sec;
5656 asection *stub_sec = htab->stub_group[section_id].stub_sec;
5657 const insn_sequence *template_sequence;
5658 int template_size, size = 0;
5659
5660 stub_entry = arm_stub_hash_lookup (&htab->stub_hash_table, stub_name,
5661 TRUE, FALSE);
5662 if (stub_entry == NULL)
5663 {
5664 (*_bfd_error_handler) (_("%s: cannot create stub entry %s"),
5665 section->owner,
5666 stub_name);
5667 return FALSE;
5668 }
5669
5670 stub_entry->stub_sec = stub_sec;
5671 stub_entry->stub_offset = 0;
5672 stub_entry->id_sec = link_sec;
5673 stub_entry->stub_type = a8_fixes[i].stub_type;
5674 stub_entry->target_section = a8_fixes[i].section;
5675 stub_entry->target_value = a8_fixes[i].offset;
5676 stub_entry->target_addend = a8_fixes[i].addend;
5677 stub_entry->orig_insn = a8_fixes[i].orig_insn;
35fc36a8 5678 stub_entry->branch_type = a8_fixes[i].branch_type;
48229727 5679
99059e56
RM		 5680 size = find_stub_size_and_template (a8_fixes[i].stub_type,
5681 &template_sequence,
5682 &template_size);
48229727 5683
99059e56
RM		 5684 stub_entry->stub_size = size;
5685 stub_entry->stub_template = template_sequence;
5686 stub_entry->stub_template_size = template_size;
5687 }
48229727
JB		 5688
5689 /* Stash the Cortex-A8 erratum fix array for use later in
99059e56 5690 elf32_arm_write_section(). */
48229727
JB		 5691 htab->a8_erratum_fixes = a8_fixes;
5692 htab->num_a8_erratum_fixes = num_a8_fixes;
5693 }
5694 else
5695 {
5696 htab->a8_erratum_fixes = NULL;
5697 htab->num_a8_erratum_fixes = 0;
5698 }
906e58ca
NC		 5699 return TRUE;
5700
5701 error_ret_free_local:
5702 return FALSE;
5e681ec4
PB		 5703}
5704
906e58ca
NC		 5705/* Build all the stubs associated with the current output file. The
5706 stubs are kept in a hash table attached to the main linker hash
5707 table. We also set up the .plt entries for statically linked PIC
5708 functions here. This function is called via arm_elf_finish in the
5709 linker. */
252b5132 5710
906e58ca
NC		 5711bfd_boolean
5712elf32_arm_build_stubs (struct bfd_link_info *info)
252b5132 5713{
906e58ca
NC		 5714 asection *stub_sec;
5715 struct bfd_hash_table *table;
5716 struct elf32_arm_link_hash_table *htab;
252b5132 5717
906e58ca 5718 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 5719 if (htab == NULL)
5720 return FALSE;
252b5132 5721
906e58ca
NC		 5722 for (stub_sec = htab->stub_bfd->sections;
5723 stub_sec != NULL;
5724 stub_sec = stub_sec->next)
252b5132 5725 {
906e58ca
NC		 5726 bfd_size_type size;
5727
8029a119 5728 /* Ignore non-stub sections. */
906e58ca
NC		 5729 if (!strstr (stub_sec->name, STUB_SUFFIX))
5730 continue;
5731
5732 /* Allocate memory to hold the linker stubs. */
5733 size = stub_sec->size;
21d799b5 5734 stub_sec->contents = (unsigned char *) bfd_zalloc (htab->stub_bfd, size);
906e58ca
NC		 5735 if (stub_sec->contents == NULL && size != 0)
5736 return FALSE;
5737 stub_sec->size = 0;
252b5132
RH		 5738 }
5739
906e58ca
NC		 5740 /* Build the stubs as directed by the stub hash table. */
5741 table = &htab->stub_hash_table;
5742 bfd_hash_traverse (table, arm_build_one_stub, info);
eb7c4339
NS		 5743 if (htab->fix_cortex_a8)
5744 {
5745 /* Place the cortex a8 stubs last. */
5746 htab->fix_cortex_a8 = -1;
5747 bfd_hash_traverse (table, arm_build_one_stub, info);
5748 }
252b5132 5749
906e58ca 5750 return TRUE;
252b5132
RH		 5751}
5752
9b485d32
NC		 5753/* Locate the Thumb encoded calling stub for NAME. */
5754
252b5132 5755static struct elf_link_hash_entry *
57e8b36a
NC		 5756find_thumb_glue (struct bfd_link_info *link_info,
5757 const char *name,
f2a9dd69 5758 char **error_message)
252b5132
RH		 5759{
5760 char *tmp_name;
5761 struct elf_link_hash_entry *hash;
5762 struct elf32_arm_link_hash_table *hash_table;
5763
5764 /* We need a pointer to the armelf specific hash table. */
5765 hash_table = elf32_arm_hash_table (link_info);
4dfe6ac6
NC		 5766 if (hash_table == NULL)
5767 return NULL;
252b5132 5768
21d799b5 5769 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen (name)
99059e56 5770 + strlen (THUMB2ARM_GLUE_ENTRY_NAME) + 1);
252b5132
RH		 5771
5772 BFD_ASSERT (tmp_name);
5773
5774 sprintf (tmp_name, THUMB2ARM_GLUE_ENTRY_NAME, name);
5775
5776 hash = elf_link_hash_lookup
b34976b6 5777 (&(hash_table)->root, tmp_name, FALSE, FALSE, TRUE);
252b5132 5778
b1657152
AM		 5779 if (hash == NULL
5780 && asprintf (error_message, _("unable to find THUMB glue '%s' for '%s'"),
5781 tmp_name, name) == -1)
5782 *error_message = (char *) bfd_errmsg (bfd_error_system_call);
252b5132
RH		 5783
5784 free (tmp_name);
5785
5786 return hash;
5787}
5788
9b485d32
NC		 5789/* Locate the ARM encoded calling stub for NAME. */
5790
252b5132 5791static struct elf_link_hash_entry *
57e8b36a
NC		 5792find_arm_glue (struct bfd_link_info *link_info,
5793 const char *name,
f2a9dd69 5794 char **error_message)
252b5132
RH		 5795{
5796 char *tmp_name;
5797 struct elf_link_hash_entry *myh;
5798 struct elf32_arm_link_hash_table *hash_table;
5799
5800 /* We need a pointer to the elfarm specific hash table. */
5801 hash_table = elf32_arm_hash_table (link_info);
4dfe6ac6
NC		 5802 if (hash_table == NULL)
5803 return NULL;
252b5132 5804
21d799b5 5805 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen (name)
99059e56 5806 + strlen (ARM2THUMB_GLUE_ENTRY_NAME) + 1);
252b5132
RH		 5807
5808 BFD_ASSERT (tmp_name);
5809
5810 sprintf (tmp_name, ARM2THUMB_GLUE_ENTRY_NAME, name);
5811
5812 myh = elf_link_hash_lookup
b34976b6 5813 (&(hash_table)->root, tmp_name, FALSE, FALSE, TRUE);
252b5132 5814
b1657152
AM		 5815 if (myh == NULL
5816 && asprintf (error_message, _("unable to find ARM glue '%s' for '%s'"),
5817 tmp_name, name) == -1)
5818 *error_message = (char *) bfd_errmsg (bfd_error_system_call);
252b5132
RH		 5819
5820 free (tmp_name);
5821
5822 return myh;
5823}
5824
8f6277f5 5825/* ARM->Thumb glue (static images):
252b5132
RH		 5826
5827 .arm
5828 __func_from_arm:
5829 ldr r12, __func_addr
5830 bx r12
5831 __func_addr:
906e58ca 5832 .word func @ behave as if you saw a ARM_32 reloc.
252b5132 5833
26079076
PB		 5834 (v5t static images)
5835 .arm
5836 __func_from_arm:
5837 ldr pc, __func_addr
5838 __func_addr:
906e58ca 5839 .word func @ behave as if you saw a ARM_32 reloc.
26079076 5840
8f6277f5
PB		 5841 (relocatable images)
5842 .arm
5843 __func_from_arm:
5844 ldr r12, __func_offset
5845 add r12, r12, pc
5846 bx r12
5847 __func_offset:
8029a119 5848 .word func - . */
8f6277f5
PB		 5849
5850#define ARM2THUMB_STATIC_GLUE_SIZE 12
252b5132
RH		 5851static const insn32 a2t1_ldr_insn = 0xe59fc000;
5852static const insn32 a2t2_bx_r12_insn = 0xe12fff1c;
5853static const insn32 a2t3_func_addr_insn = 0x00000001;
5854
26079076
PB		 5855#define ARM2THUMB_V5_STATIC_GLUE_SIZE 8
5856static const insn32 a2t1v5_ldr_insn = 0xe51ff004;
5857static const insn32 a2t2v5_func_addr_insn = 0x00000001;
5858
8f6277f5
PB		 5859#define ARM2THUMB_PIC_GLUE_SIZE 16
5860static const insn32 a2t1p_ldr_insn = 0xe59fc004;
5861static const insn32 a2t2p_add_pc_insn = 0xe08cc00f;
5862static const insn32 a2t3p_bx_r12_insn = 0xe12fff1c;
5863
9b485d32 5864/* Thumb->ARM: Thumb->(non-interworking aware) ARM
252b5132 5865
8029a119
NC		 5866 .thumb .thumb
5867 .align 2 .align 2
5868 __func_from_thumb: __func_from_thumb:
5869 bx pc push {r6, lr}
5870 nop ldr r6, __func_addr
5871 .arm mov lr, pc
5872 b func bx r6
99059e56
RM		 5873 .arm
5874 ;; back_to_thumb
5875 ldmia r13! {r6, lr}
5876 bx lr
5877 __func_addr:
5878 .word func */
252b5132
RH		 5879
5880#define THUMB2ARM_GLUE_SIZE 8
5881static const insn16 t2a1_bx_pc_insn = 0x4778;
5882static const insn16 t2a2_noop_insn = 0x46c0;
5883static const insn32 t2a3_b_insn = 0xea000000;
5884
c7b8f16e 5885#define VFP11_ERRATUM_VENEER_SIZE 8
a504d23a
LA		 5886#define STM32L4XX_ERRATUM_LDM_VENEER_SIZE 16
5887#define STM32L4XX_ERRATUM_VLDM_VENEER_SIZE 24
c7b8f16e 5888
845b51d6
PB		 5889#define ARM_BX_VENEER_SIZE 12
5890static const insn32 armbx1_tst_insn = 0xe3100001;
5891static const insn32 armbx2_moveq_insn = 0x01a0f000;
5892static const insn32 armbx3_bx_insn = 0xe12fff10;
5893
7e392df6 5894#ifndef ELFARM_NABI_C_INCLUDED
8029a119
NC		 5895static void
5896arm_allocate_glue_section_space (bfd * abfd, bfd_size_type size, const char * name)
252b5132
RH		 5897{
5898 asection * s;
8029a119 5899 bfd_byte * contents;
252b5132 5900
8029a119 5901 if (size == 0)
3e6b1042
DJ		 5902 {
5903 /* Do not include empty glue sections in the output. */
5904 if (abfd != NULL)
5905 {
3d4d4302 5906 s = bfd_get_linker_section (abfd, name);
3e6b1042
DJ		 5907 if (s != NULL)
5908 s->flags |= SEC_EXCLUDE;
5909 }
5910 return;
5911 }
252b5132 5912
8029a119 5913 BFD_ASSERT (abfd != NULL);
252b5132 5914
3d4d4302 5915 s = bfd_get_linker_section (abfd, name);
8029a119 5916 BFD_ASSERT (s != NULL);
252b5132 5917
21d799b5 5918 contents = (bfd_byte *) bfd_alloc (abfd, size);
252b5132 5919
8029a119
NC		 5920 BFD_ASSERT (s->size == size);
5921 s->contents = contents;
5922}
906e58ca 5923
8029a119
NC		 5924bfd_boolean
5925bfd_elf32_arm_allocate_interworking_sections (struct bfd_link_info * info)
5926{
5927 struct elf32_arm_link_hash_table * globals;
906e58ca 5928
8029a119
NC		 5929 globals = elf32_arm_hash_table (info);
5930 BFD_ASSERT (globals != NULL);
906e58ca 5931
8029a119
NC		 5932 arm_allocate_glue_section_space (globals->bfd_of_glue_owner,
5933 globals->arm_glue_size,
5934 ARM2THUMB_GLUE_SECTION_NAME);
906e58ca 5935
8029a119
NC		 5936 arm_allocate_glue_section_space (globals->bfd_of_glue_owner,
5937 globals->thumb_glue_size,
5938 THUMB2ARM_GLUE_SECTION_NAME);
252b5132 5939
8029a119
NC		 5940 arm_allocate_glue_section_space (globals->bfd_of_glue_owner,
5941 globals->vfp11_erratum_glue_size,
5942 VFP11_ERRATUM_VENEER_SECTION_NAME);
845b51d6 5943
a504d23a
LA		 5944 arm_allocate_glue_section_space (globals->bfd_of_glue_owner,
5945 globals->stm32l4xx_erratum_glue_size,
5946 STM32L4XX_ERRATUM_VENEER_SECTION_NAME);
5947
8029a119
NC		 5948 arm_allocate_glue_section_space (globals->bfd_of_glue_owner,
5949 globals->bx_glue_size,
845b51d6
PB		 5950 ARM_BX_GLUE_SECTION_NAME);
5951
b34976b6 5952 return TRUE;
252b5132
RH		 5953}
5954
a4fd1a8e 5955/* Allocate space and symbols for calling a Thumb function from Arm mode.
906e58ca
NC		 5956 returns the symbol identifying the stub. */
5957
a4fd1a8e 5958static struct elf_link_hash_entry *
57e8b36a
NC		 5959record_arm_to_thumb_glue (struct bfd_link_info * link_info,
5960 struct elf_link_hash_entry * h)
252b5132
RH		 5961{
5962 const char * name = h->root.root.string;
63b0f745 5963 asection * s;
252b5132
RH		 5964 char * tmp_name;
5965 struct elf_link_hash_entry * myh;
14a793b2 5966 struct bfd_link_hash_entry * bh;
252b5132 5967 struct elf32_arm_link_hash_table * globals;
dc810e39 5968 bfd_vma val;
2f475487 5969 bfd_size_type size;
252b5132
RH		 5970
5971 globals = elf32_arm_hash_table (link_info);
252b5132
RH		 5972 BFD_ASSERT (globals != NULL);
5973 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
5974
3d4d4302 5975 s = bfd_get_linker_section
252b5132
RH		 5976 (globals->bfd_of_glue_owner, ARM2THUMB_GLUE_SECTION_NAME);
5977
252b5132
RH		 5978 BFD_ASSERT (s != NULL);
5979
21d799b5 5980 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen (name)
99059e56 5981 + strlen (ARM2THUMB_GLUE_ENTRY_NAME) + 1);
252b5132
RH		 5982
5983 BFD_ASSERT (tmp_name);
5984
5985 sprintf (tmp_name, ARM2THUMB_GLUE_ENTRY_NAME, name);
5986
5987 myh = elf_link_hash_lookup
b34976b6 5988 (&(globals)->root, tmp_name, FALSE, FALSE, TRUE);
252b5132
RH		 5989
5990 if (myh != NULL)
5991 {
9b485d32 5992 /* We've already seen this guy. */
252b5132 5993 free (tmp_name);
a4fd1a8e 5994 return myh;
252b5132
RH		 5995 }
5996
57e8b36a
NC		 5997 /* The only trick here is using hash_table->arm_glue_size as the value.
5998 Even though the section isn't allocated yet, this is where we will be
3dccd7b7
DJ		 5999 putting it. The +1 on the value marks that the stub has not been
6000 output yet - not that it is a Thumb function. */
14a793b2 6001 bh = NULL;
dc810e39
AM		 6002 val = globals->arm_glue_size + 1;
6003 _bfd_generic_link_add_one_symbol (link_info, globals->bfd_of_glue_owner,
6004 tmp_name, BSF_GLOBAL, s, val,
b34976b6 6005 NULL, TRUE, FALSE, &bh);
252b5132 6006
b7693d02
DJ		 6007 myh = (struct elf_link_hash_entry *) bh;
6008 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
6009 myh->forced_local = 1;
6010
252b5132
RH		 6011 free (tmp_name);
6012
0e1862bb
L		 6013 if (bfd_link_pic (link_info)
6014 || globals->root.is_relocatable_executable
27e55c4d 6015 || globals->pic_veneer)
2f475487 6016 size = ARM2THUMB_PIC_GLUE_SIZE;
26079076
PB		 6017 else if (globals->use_blx)
6018 size = ARM2THUMB_V5_STATIC_GLUE_SIZE;
8f6277f5 6019 else
2f475487
AM		 6020 size = ARM2THUMB_STATIC_GLUE_SIZE;
6021
6022 s->size += size;
6023 globals->arm_glue_size += size;
252b5132 6024
a4fd1a8e 6025 return myh;
252b5132
RH		 6026}
6027
845b51d6
PB		 6028/* Allocate space for ARMv4 BX veneers. */
6029
6030static void
6031record_arm_bx_glue (struct bfd_link_info * link_info, int reg)
6032{
6033 asection * s;
6034 struct elf32_arm_link_hash_table *globals;
6035 char *tmp_name;
6036 struct elf_link_hash_entry *myh;
6037 struct bfd_link_hash_entry *bh;
6038 bfd_vma val;
6039
6040 /* BX PC does not need a veneer. */
6041 if (reg == 15)
6042 return;
6043
6044 globals = elf32_arm_hash_table (link_info);
845b51d6
PB		 6045 BFD_ASSERT (globals != NULL);
6046 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
6047
6048 /* Check if this veneer has already been allocated. */
6049 if (globals->bx_glue_offset[reg])
6050 return;
6051
3d4d4302 6052 s = bfd_get_linker_section
845b51d6
PB		 6053 (globals->bfd_of_glue_owner, ARM_BX_GLUE_SECTION_NAME);
6054
6055 BFD_ASSERT (s != NULL);
6056
6057 /* Add symbol for veneer. */
21d799b5
NC		 6058 tmp_name = (char *)
6059 bfd_malloc ((bfd_size_type) strlen (ARM_BX_GLUE_ENTRY_NAME) + 1);
906e58ca 6060
845b51d6 6061 BFD_ASSERT (tmp_name);
906e58ca 6062
845b51d6 6063 sprintf (tmp_name, ARM_BX_GLUE_ENTRY_NAME, reg);
906e58ca 6064
845b51d6
PB		 6065 myh = elf_link_hash_lookup
6066 (&(globals)->root, tmp_name, FALSE, FALSE, FALSE);
906e58ca 6067
845b51d6 6068 BFD_ASSERT (myh == NULL);
906e58ca 6069
845b51d6
PB		 6070 bh = NULL;
6071 val = globals->bx_glue_size;
6072 _bfd_generic_link_add_one_symbol (link_info, globals->bfd_of_glue_owner,
99059e56
RM		 6073 tmp_name, BSF_FUNCTION | BSF_LOCAL, s, val,
6074 NULL, TRUE, FALSE, &bh);
845b51d6
PB		 6075
6076 myh = (struct elf_link_hash_entry *) bh;
6077 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
6078 myh->forced_local = 1;
6079
6080 s->size += ARM_BX_VENEER_SIZE;
6081 globals->bx_glue_offset[reg] = globals->bx_glue_size | 2;
6082 globals->bx_glue_size += ARM_BX_VENEER_SIZE;
6083}
6084
6085
c7b8f16e
JB		 6086/* Add an entry to the code/data map for section SEC. */
6087
6088static void
6089elf32_arm_section_map_add (asection *sec, char type, bfd_vma vma)
6090{
6091 struct _arm_elf_section_data *sec_data = elf32_arm_section_data (sec);
6092 unsigned int newidx;
906e58ca 6093
c7b8f16e
JB		 6094 if (sec_data->map == NULL)
6095 {
21d799b5 6096 sec_data->map = (elf32_arm_section_map *)
99059e56 6097 bfd_malloc (sizeof (elf32_arm_section_map));
c7b8f16e
JB		 6098 sec_data->mapcount = 0;
6099 sec_data->mapsize = 1;
6100 }
906e58ca 6101
c7b8f16e 6102 newidx = sec_data->mapcount++;
906e58ca 6103
c7b8f16e
JB		 6104 if (sec_data->mapcount > sec_data->mapsize)
6105 {
6106 sec_data->mapsize *= 2;
21d799b5 6107 sec_data->map = (elf32_arm_section_map *)
99059e56
RM		 6108 bfd_realloc_or_free (sec_data->map, sec_data->mapsize
6109 * sizeof (elf32_arm_section_map));
515ef31d
NC		 6110 }
6111
6112 if (sec_data->map)
6113 {
6114 sec_data->map[newidx].vma = vma;
6115 sec_data->map[newidx].type = type;
c7b8f16e 6116 }
c7b8f16e
JB		 6117}
6118
6119
6120/* Record information about a VFP11 denorm-erratum veneer. Only ARM-mode
6121 veneers are handled for now. */
6122
6123static bfd_vma
6124record_vfp11_erratum_veneer (struct bfd_link_info *link_info,
99059e56
RM		 6125 elf32_vfp11_erratum_list *branch,
6126 bfd *branch_bfd,
6127 asection *branch_sec,
6128 unsigned int offset)
c7b8f16e
JB		 6129{
6130 asection *s;
6131 struct elf32_arm_link_hash_table *hash_table;
6132 char *tmp_name;
6133 struct elf_link_hash_entry *myh;
6134 struct bfd_link_hash_entry *bh;
6135 bfd_vma val;
6136 struct _arm_elf_section_data *sec_data;
c7b8f16e 6137 elf32_vfp11_erratum_list *newerr;
906e58ca 6138
c7b8f16e 6139 hash_table = elf32_arm_hash_table (link_info);
c7b8f16e
JB		 6140 BFD_ASSERT (hash_table != NULL);
6141 BFD_ASSERT (hash_table->bfd_of_glue_owner != NULL);
906e58ca 6142
3d4d4302 6143 s = bfd_get_linker_section
c7b8f16e 6144 (hash_table->bfd_of_glue_owner, VFP11_ERRATUM_VENEER_SECTION_NAME);
906e58ca 6145
c7b8f16e 6146 sec_data = elf32_arm_section_data (s);
906e58ca 6147
c7b8f16e 6148 BFD_ASSERT (s != NULL);
906e58ca 6149
21d799b5 6150 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen
99059e56 6151 (VFP11_ERRATUM_VENEER_ENTRY_NAME) + 10);
906e58ca 6152
c7b8f16e 6153 BFD_ASSERT (tmp_name);
906e58ca 6154
c7b8f16e
JB		 6155 sprintf (tmp_name, VFP11_ERRATUM_VENEER_ENTRY_NAME,
6156 hash_table->num_vfp11_fixes);
906e58ca 6157
c7b8f16e
JB		 6158 myh = elf_link_hash_lookup
6159 (&(hash_table)->root, tmp_name, FALSE, FALSE, FALSE);
906e58ca 6160
c7b8f16e 6161 BFD_ASSERT (myh == NULL);
906e58ca 6162
c7b8f16e
JB		 6163 bh = NULL;
6164 val = hash_table->vfp11_erratum_glue_size;
6165 _bfd_generic_link_add_one_symbol (link_info, hash_table->bfd_of_glue_owner,
99059e56
RM		 6166 tmp_name, BSF_FUNCTION | BSF_LOCAL, s, val,
6167 NULL, TRUE, FALSE, &bh);
c7b8f16e
JB		 6168
6169 myh = (struct elf_link_hash_entry *) bh;
6170 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
6171 myh->forced_local = 1;
6172
6173 /* Link veneer back to calling location. */
c7e2358a 6174 sec_data->erratumcount += 1;
21d799b5
NC		 6175 newerr = (elf32_vfp11_erratum_list *)
6176 bfd_zmalloc (sizeof (elf32_vfp11_erratum_list));
906e58ca 6177
c7b8f16e
JB		 6178 newerr->type = VFP11_ERRATUM_ARM_VENEER;
6179 newerr->vma = -1;
6180 newerr->u.v.branch = branch;
6181 newerr->u.v.id = hash_table->num_vfp11_fixes;
6182 branch->u.b.veneer = newerr;
6183
6184 newerr->next = sec_data->erratumlist;
6185 sec_data->erratumlist = newerr;
6186
6187 /* A symbol for the return from the veneer. */
6188 sprintf (tmp_name, VFP11_ERRATUM_VENEER_ENTRY_NAME "_r",
6189 hash_table->num_vfp11_fixes);
6190
6191 myh = elf_link_hash_lookup
6192 (&(hash_table)->root, tmp_name, FALSE, FALSE, FALSE);
906e58ca 6193
c7b8f16e
JB		 6194 if (myh != NULL)
6195 abort ();
6196
6197 bh = NULL;
6198 val = offset + 4;
6199 _bfd_generic_link_add_one_symbol (link_info, branch_bfd, tmp_name, BSF_LOCAL,
6200 branch_sec, val, NULL, TRUE, FALSE, &bh);
906e58ca 6201
c7b8f16e
JB		 6202 myh = (struct elf_link_hash_entry *) bh;
6203 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
6204 myh->forced_local = 1;
6205
6206 free (tmp_name);
906e58ca 6207
c7b8f16e
JB		 6208 /* Generate a mapping symbol for the veneer section, and explicitly add an
6209 entry for that symbol to the code/data map for the section. */
6210 if (hash_table->vfp11_erratum_glue_size == 0)
6211 {
6212 bh = NULL;
6213 /* FIXME: Creates an ARM symbol. Thumb mode will need attention if it
99059e56 6214 ever requires this erratum fix. */
c7b8f16e
JB		 6215 _bfd_generic_link_add_one_symbol (link_info,
6216 hash_table->bfd_of_glue_owner, "$a",
6217 BSF_LOCAL, s, 0, NULL,
99059e56 6218 TRUE, FALSE, &bh);
c7b8f16e
JB		 6219
6220 myh = (struct elf_link_hash_entry *) bh;
6221 myh->type = ELF_ST_INFO (STB_LOCAL, STT_NOTYPE);
6222 myh->forced_local = 1;
906e58ca 6223
c7b8f16e 6224 /* The elf32_arm_init_maps function only cares about symbols from input
99059e56
RM		 6225 BFDs. We must make a note of this generated mapping symbol
6226 ourselves so that code byteswapping works properly in
6227 elf32_arm_write_section. */
c7b8f16e
JB		 6228 elf32_arm_section_map_add (s, 'a', 0);
6229 }
906e58ca 6230
c7b8f16e
JB		 6231 s->size += VFP11_ERRATUM_VENEER_SIZE;
6232 hash_table->vfp11_erratum_glue_size += VFP11_ERRATUM_VENEER_SIZE;
6233 hash_table->num_vfp11_fixes++;
906e58ca 6234
c7b8f16e
JB		 6235 /* The offset of the veneer. */
6236 return val;
6237}
6238
a504d23a
LA		 6239/* Record information about a STM32L4XX STM erratum veneer. Only THUMB-mode
6240 veneers need to be handled because used only in Cortex-M. */
6241
6242static bfd_vma
6243record_stm32l4xx_erratum_veneer (struct bfd_link_info *link_info,
6244 elf32_stm32l4xx_erratum_list *branch,
6245 bfd *branch_bfd,
6246 asection *branch_sec,
6247 unsigned int offset,
6248 bfd_size_type veneer_size)
6249{
6250 asection *s;
6251 struct elf32_arm_link_hash_table *hash_table;
6252 char *tmp_name;
6253 struct elf_link_hash_entry *myh;
6254 struct bfd_link_hash_entry *bh;
6255 bfd_vma val;
6256 struct _arm_elf_section_data *sec_data;
6257 elf32_stm32l4xx_erratum_list *newerr;
6258
6259 hash_table = elf32_arm_hash_table (link_info);
6260 BFD_ASSERT (hash_table != NULL);
6261 BFD_ASSERT (hash_table->bfd_of_glue_owner != NULL);
6262
6263 s = bfd_get_linker_section
6264 (hash_table->bfd_of_glue_owner, STM32L4XX_ERRATUM_VENEER_SECTION_NAME);
6265
6266 BFD_ASSERT (s != NULL);
6267
6268 sec_data = elf32_arm_section_data (s);
6269
6270 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen
6271 (STM32L4XX_ERRATUM_VENEER_ENTRY_NAME) + 10);
6272
6273 BFD_ASSERT (tmp_name);
6274
6275 sprintf (tmp_name, STM32L4XX_ERRATUM_VENEER_ENTRY_NAME,
6276 hash_table->num_stm32l4xx_fixes);
6277
6278 myh = elf_link_hash_lookup
6279 (&(hash_table)->root, tmp_name, FALSE, FALSE, FALSE);
6280
6281 BFD_ASSERT (myh == NULL);
6282
6283 bh = NULL;
6284 val = hash_table->stm32l4xx_erratum_glue_size;
6285 _bfd_generic_link_add_one_symbol (link_info, hash_table->bfd_of_glue_owner,
6286 tmp_name, BSF_FUNCTION | BSF_LOCAL, s, val,
6287 NULL, TRUE, FALSE, &bh);
6288
6289 myh = (struct elf_link_hash_entry *) bh;
6290 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
6291 myh->forced_local = 1;
6292
6293 /* Link veneer back to calling location. */
6294 sec_data->stm32l4xx_erratumcount += 1;
6295 newerr = (elf32_stm32l4xx_erratum_list *)
6296 bfd_zmalloc (sizeof (elf32_stm32l4xx_erratum_list));
6297
6298 newerr->type = STM32L4XX_ERRATUM_VENEER;
6299 newerr->vma = -1;
6300 newerr->u.v.branch = branch;
6301 newerr->u.v.id = hash_table->num_stm32l4xx_fixes;
6302 branch->u.b.veneer = newerr;
6303
6304 newerr->next = sec_data->stm32l4xx_erratumlist;
6305 sec_data->stm32l4xx_erratumlist = newerr;
6306
6307 /* A symbol for the return from the veneer. */
6308 sprintf (tmp_name, STM32L4XX_ERRATUM_VENEER_ENTRY_NAME "_r",
6309 hash_table->num_stm32l4xx_fixes);
6310
6311 myh = elf_link_hash_lookup
6312 (&(hash_table)->root, tmp_name, FALSE, FALSE, FALSE);
6313
6314 if (myh != NULL)
6315 abort ();
6316
6317 bh = NULL;
6318 val = offset + 4;
6319 _bfd_generic_link_add_one_symbol (link_info, branch_bfd, tmp_name, BSF_LOCAL,
6320 branch_sec, val, NULL, TRUE, FALSE, &bh);
6321
6322 myh = (struct elf_link_hash_entry *) bh;
6323 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
6324 myh->forced_local = 1;
6325
6326 free (tmp_name);
6327
6328 /* Generate a mapping symbol for the veneer section, and explicitly add an
6329 entry for that symbol to the code/data map for the section. */
6330 if (hash_table->stm32l4xx_erratum_glue_size == 0)
6331 {
6332 bh = NULL;
6333 /* Creates a THUMB symbol since there is no other choice. */
6334 _bfd_generic_link_add_one_symbol (link_info,
6335 hash_table->bfd_of_glue_owner, "$t",
6336 BSF_LOCAL, s, 0, NULL,
6337 TRUE, FALSE, &bh);
6338
6339 myh = (struct elf_link_hash_entry *) bh;
6340 myh->type = ELF_ST_INFO (STB_LOCAL, STT_NOTYPE);
6341 myh->forced_local = 1;
6342
6343 /* The elf32_arm_init_maps function only cares about symbols from input
6344 BFDs. We must make a note of this generated mapping symbol
6345 ourselves so that code byteswapping works properly in
6346 elf32_arm_write_section. */
6347 elf32_arm_section_map_add (s, 't', 0);
6348 }
6349
6350 s->size += veneer_size;
6351 hash_table->stm32l4xx_erratum_glue_size += veneer_size;
6352 hash_table->num_stm32l4xx_fixes++;
6353
6354 /* The offset of the veneer. */
6355 return val;
6356}
6357
8029a119 6358#define ARM_GLUE_SECTION_FLAGS \
3e6b1042
DJ		 6359 (SEC_ALLOC | SEC_LOAD | SEC_HAS_CONTENTS | SEC_IN_MEMORY | SEC_CODE \
6360 | SEC_READONLY | SEC_LINKER_CREATED)
8029a119
NC		 6361
6362/* Create a fake section for use by the ARM backend of the linker. */
6363
6364static bfd_boolean
6365arm_make_glue_section (bfd * abfd, const char * name)
6366{
6367 asection * sec;
6368
3d4d4302 6369 sec = bfd_get_linker_section (abfd, name);
8029a119
NC		 6370 if (sec != NULL)
6371 /* Already made. */
6372 return TRUE;
6373
3d4d4302 6374 sec = bfd_make_section_anyway_with_flags (abfd, name, ARM_GLUE_SECTION_FLAGS);
8029a119
NC		 6375
6376 if (sec == NULL
6377 || !bfd_set_section_alignment (abfd, sec, 2))
6378 return FALSE;
6379
6380 /* Set the gc mark to prevent the section from being removed by garbage
6381 collection, despite the fact that no relocs refer to this section. */
6382 sec->gc_mark = 1;
6383
6384 return TRUE;
6385}
6386
1db37fe6
YG		 6387/* Set size of .plt entries. This function is called from the
6388 linker scripts in ld/emultempl/{armelf}.em. */
6389
6390void
6391bfd_elf32_arm_use_long_plt (void)
6392{
6393 elf32_arm_use_long_plt_entry = TRUE;
6394}
6395
8afb0e02
NC		 6396/* Add the glue sections to ABFD. This function is called from the
6397 linker scripts in ld/emultempl/{armelf}.em. */
9b485d32 6398
b34976b6 6399bfd_boolean
57e8b36a
NC		 6400bfd_elf32_arm_add_glue_sections_to_bfd (bfd *abfd,
6401 struct bfd_link_info *info)
252b5132 6402{
a504d23a
LA		 6403 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (info);
6404 bfd_boolean dostm32l4xx = globals
6405 && globals->stm32l4xx_fix != BFD_ARM_STM32L4XX_FIX_NONE;
6406 bfd_boolean addglue;
6407
8afb0e02
NC		 6408 /* If we are only performing a partial
6409 link do not bother adding the glue. */
0e1862bb 6410 if (bfd_link_relocatable (info))
b34976b6 6411 return TRUE;
252b5132 6412
a504d23a 6413 addglue = arm_make_glue_section (abfd, ARM2THUMB_GLUE_SECTION_NAME)
8029a119
NC		 6414 && arm_make_glue_section (abfd, THUMB2ARM_GLUE_SECTION_NAME)
6415 && arm_make_glue_section (abfd, VFP11_ERRATUM_VENEER_SECTION_NAME)
6416 && arm_make_glue_section (abfd, ARM_BX_GLUE_SECTION_NAME);
a504d23a
LA		 6417
6418 if (!dostm32l4xx)
6419 return addglue;
6420
6421 return addglue
6422 && arm_make_glue_section (abfd, STM32L4XX_ERRATUM_VENEER_SECTION_NAME);
8afb0e02
NC		 6423}
6424
6425/* Select a BFD to be used to hold the sections used by the glue code.
6426 This function is called from the linker scripts in ld/emultempl/
8029a119 6427 {armelf/pe}.em. */
8afb0e02 6428
b34976b6 6429bfd_boolean
57e8b36a 6430bfd_elf32_arm_get_bfd_for_interworking (bfd *abfd, struct bfd_link_info *info)
8afb0e02
NC		 6431{
6432 struct elf32_arm_link_hash_table *globals;
6433
6434 /* If we are only performing a partial link
6435 do not bother getting a bfd to hold the glue. */
0e1862bb 6436 if (bfd_link_relocatable (info))
b34976b6 6437 return TRUE;
8afb0e02 6438
b7693d02
DJ		 6439 /* Make sure we don't attach the glue sections to a dynamic object. */
6440 BFD_ASSERT (!(abfd->flags & DYNAMIC));
6441
8afb0e02 6442 globals = elf32_arm_hash_table (info);
8afb0e02
NC		 6443 BFD_ASSERT (globals != NULL);
6444
6445 if (globals->bfd_of_glue_owner != NULL)
b34976b6 6446 return TRUE;
8afb0e02 6447
252b5132
RH		 6448 /* Save the bfd for later use. */
6449 globals->bfd_of_glue_owner = abfd;
cedb70c5 6450
b34976b6 6451 return TRUE;
252b5132
RH		 6452}
6453
906e58ca
NC		 6454static void
6455check_use_blx (struct elf32_arm_link_hash_table *globals)
39b41c9c 6456{
2de70689
MGD		 6457 int cpu_arch;
6458
b38cadfb 6459 cpu_arch = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC,
2de70689
MGD		 6460 Tag_CPU_arch);
6461
6462 if (globals->fix_arm1176)
6463 {
6464 if (cpu_arch == TAG_CPU_ARCH_V6T2 || cpu_arch > TAG_CPU_ARCH_V6K)
6465 globals->use_blx = 1;
6466 }
6467 else
6468 {
6469 if (cpu_arch > TAG_CPU_ARCH_V4T)
6470 globals->use_blx = 1;
6471 }
39b41c9c
PB		 6472}
6473
b34976b6 6474bfd_boolean
57e8b36a 6475bfd_elf32_arm_process_before_allocation (bfd *abfd,
d504ffc8 6476 struct bfd_link_info *link_info)
252b5132
RH		 6477{
6478 Elf_Internal_Shdr *symtab_hdr;
6cdc0ccc 6479 Elf_Internal_Rela *internal_relocs = NULL;
252b5132
RH		 6480 Elf_Internal_Rela *irel, *irelend;
6481 bfd_byte *contents = NULL;
252b5132
RH		 6482
6483 asection *sec;
6484 struct elf32_arm_link_hash_table *globals;
6485
6486 /* If we are only performing a partial link do not bother
6487 to construct any glue. */
0e1862bb 6488 if (bfd_link_relocatable (link_info))
b34976b6 6489 return TRUE;
252b5132 6490
39ce1a6a
NC		 6491 /* Here we have a bfd that is to be included on the link. We have a
6492 hook to do reloc rummaging, before section sizes are nailed down. */
252b5132 6493 globals = elf32_arm_hash_table (link_info);
252b5132 6494 BFD_ASSERT (globals != NULL);
39ce1a6a
NC		 6495
6496 check_use_blx (globals);
252b5132 6497
d504ffc8 6498 if (globals->byteswap_code && !bfd_big_endian (abfd))
e489d0ae 6499 {
d003868e
AM		 6500 _bfd_error_handler (_("%B: BE8 images only valid in big-endian mode."),
6501 abfd);
e489d0ae
PB		 6502 return FALSE;
6503 }
f21f3fe0 6504
39ce1a6a
NC		 6505 /* PR 5398: If we have not decided to include any loadable sections in
6506 the output then we will not have a glue owner bfd. This is OK, it
6507 just means that there is nothing else for us to do here. */
6508 if (globals->bfd_of_glue_owner == NULL)
6509 return TRUE;
6510
252b5132
RH		 6511 /* Rummage around all the relocs and map the glue vectors. */
6512 sec = abfd->sections;
6513
6514 if (sec == NULL)
b34976b6 6515 return TRUE;
252b5132
RH		 6516
6517 for (; sec != NULL; sec = sec->next)
6518 {
6519 if (sec->reloc_count == 0)
6520 continue;
6521
2f475487
AM		 6522 if ((sec->flags & SEC_EXCLUDE) != 0)
6523 continue;
6524
0ffa91dd 6525 symtab_hdr = & elf_symtab_hdr (abfd);
252b5132 6526
9b485d32 6527 /* Load the relocs. */
6cdc0ccc 6528 internal_relocs
906e58ca 6529 = _bfd_elf_link_read_relocs (abfd, sec, NULL, NULL, FALSE);
252b5132 6530
6cdc0ccc
AM		 6531 if (internal_relocs == NULL)
6532 goto error_return;
252b5132 6533
6cdc0ccc
AM		 6534 irelend = internal_relocs + sec->reloc_count;
6535 for (irel = internal_relocs; irel < irelend; irel++)
252b5132
RH		 6536 {
6537 long r_type;
6538 unsigned long r_index;
252b5132
RH		 6539
6540 struct elf_link_hash_entry *h;
6541
6542 r_type = ELF32_R_TYPE (irel->r_info);
6543 r_index = ELF32_R_SYM (irel->r_info);
6544
9b485d32 6545 /* These are the only relocation types we care about. */
ba96a88f 6546 if ( r_type != R_ARM_PC24
845b51d6 6547 && (r_type != R_ARM_V4BX || globals->fix_v4bx < 2))
252b5132
RH		 6548 continue;
6549
6550 /* Get the section contents if we haven't done so already. */
6551 if (contents == NULL)
6552 {
6553 /* Get cached copy if it exists. */
6554 if (elf_section_data (sec)->this_hdr.contents != NULL)
6555 contents = elf_section_data (sec)->this_hdr.contents;
6556 else
6557 {
6558 /* Go get them off disk. */
57e8b36a 6559 if (! bfd_malloc_and_get_section (abfd, sec, &contents))
252b5132
RH		 6560 goto error_return;
6561 }
6562 }
6563
845b51d6
PB		 6564 if (r_type == R_ARM_V4BX)
6565 {
6566 int reg;
6567
6568 reg = bfd_get_32 (abfd, contents + irel->r_offset) & 0xf;
6569 record_arm_bx_glue (link_info, reg);
6570 continue;
6571 }
6572
a7c10850 6573 /* If the relocation is not against a symbol it cannot concern us. */
252b5132
RH		 6574 h = NULL;
6575
9b485d32 6576 /* We don't care about local symbols. */
252b5132
RH		 6577 if (r_index < symtab_hdr->sh_info)
6578 continue;
6579
9b485d32 6580 /* This is an external symbol. */
252b5132
RH		 6581 r_index -= symtab_hdr->sh_info;
6582 h = (struct elf_link_hash_entry *)
6583 elf_sym_hashes (abfd)[r_index];
6584
6585 /* If the relocation is against a static symbol it must be within
6586 the current section and so cannot be a cross ARM/Thumb relocation. */
6587 if (h == NULL)
6588 continue;
6589
d504ffc8
DJ		 6590 /* If the call will go through a PLT entry then we do not need
6591 glue. */
362d30a1 6592 if (globals->root.splt != NULL && h->plt.offset != (bfd_vma) -1)
b7693d02
DJ		 6593 continue;
6594
252b5132
RH		 6595 switch (r_type)
6596 {
6597 case R_ARM_PC24:
6598 /* This one is a call from arm code. We need to look up
99059e56
RM		 6599 the target of the call. If it is a thumb target, we
6600 insert glue. */
35fc36a8 6601 if (h->target_internal == ST_BRANCH_TO_THUMB)
252b5132
RH		 6602 record_arm_to_thumb_glue (link_info, h);
6603 break;
6604
252b5132 6605 default:
c6596c5e 6606 abort ();
252b5132
RH		 6607 }
6608 }
6cdc0ccc
AM		 6609
6610 if (contents != NULL
6611 && elf_section_data (sec)->this_hdr.contents != contents)
6612 free (contents);
6613 contents = NULL;
6614
6615 if (internal_relocs != NULL
6616 && elf_section_data (sec)->relocs != internal_relocs)
6617 free (internal_relocs);
6618 internal_relocs = NULL;
252b5132
RH		 6619 }
6620
b34976b6 6621 return TRUE;
9a5aca8c 6622
252b5132 6623error_return:
6cdc0ccc
AM		 6624 if (contents != NULL
6625 && elf_section_data (sec)->this_hdr.contents != contents)
6626 free (contents);
6627 if (internal_relocs != NULL
6628 && elf_section_data (sec)->relocs != internal_relocs)
6629 free (internal_relocs);
9a5aca8c 6630
b34976b6 6631 return FALSE;
252b5132 6632}
7e392df6 6633#endif
252b5132 6634
eb043451 6635
c7b8f16e
JB		 6636/* Initialise maps of ARM/Thumb/data for input BFDs. */
6637
6638void
6639bfd_elf32_arm_init_maps (bfd *abfd)
6640{
6641 Elf_Internal_Sym *isymbuf;
6642 Elf_Internal_Shdr *hdr;
6643 unsigned int i, localsyms;
6644
af1f4419
NC		 6645 /* PR 7093: Make sure that we are dealing with an arm elf binary. */
6646 if (! is_arm_elf (abfd))
6647 return;
6648
c7b8f16e
JB		 6649 if ((abfd->flags & DYNAMIC) != 0)
6650 return;
6651
0ffa91dd 6652 hdr = & elf_symtab_hdr (abfd);
c7b8f16e
JB		 6653 localsyms = hdr->sh_info;
6654
6655 /* Obtain a buffer full of symbols for this BFD. The hdr->sh_info field
6656 should contain the number of local symbols, which should come before any
6657 global symbols. Mapping symbols are always local. */
6658 isymbuf = bfd_elf_get_elf_syms (abfd, hdr, localsyms, 0, NULL, NULL,
6659 NULL);
6660
6661 /* No internal symbols read? Skip this BFD. */
6662 if (isymbuf == NULL)
6663 return;
6664
6665 for (i = 0; i < localsyms; i++)
6666 {
6667 Elf_Internal_Sym *isym = &isymbuf[i];
6668 asection *sec = bfd_section_from_elf_index (abfd, isym->st_shndx);
6669 const char *name;
906e58ca 6670
c7b8f16e 6671 if (sec != NULL
99059e56
RM		 6672 && ELF_ST_BIND (isym->st_info) == STB_LOCAL)
6673 {
6674 name = bfd_elf_string_from_elf_section (abfd,
6675 hdr->sh_link, isym->st_name);
906e58ca 6676
99059e56 6677 if (bfd_is_arm_special_symbol_name (name,
c7b8f16e 6678 BFD_ARM_SPECIAL_SYM_TYPE_MAP))
99059e56
RM		 6679 elf32_arm_section_map_add (sec, name[1], isym->st_value);
6680 }
c7b8f16e
JB		 6681 }
6682}
6683
6684
48229727
JB		 6685/* Auto-select enabling of Cortex-A8 erratum fix if the user didn't explicitly
6686 say what they wanted. */
6687
6688void
6689bfd_elf32_arm_set_cortex_a8_fix (bfd *obfd, struct bfd_link_info *link_info)
6690{
6691 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (link_info);
6692 obj_attribute *out_attr = elf_known_obj_attributes_proc (obfd);
6693
4dfe6ac6
NC		 6694 if (globals == NULL)
6695 return;
6696
48229727
JB		 6697 if (globals->fix_cortex_a8 == -1)
6698 {
6699 /* Turn on Cortex-A8 erratum workaround for ARMv7-A. */
6700 if (out_attr[Tag_CPU_arch].i == TAG_CPU_ARCH_V7
6701 && (out_attr[Tag_CPU_arch_profile].i == 'A'
6702 || out_attr[Tag_CPU_arch_profile].i == 0))
6703 globals->fix_cortex_a8 = 1;
6704 else
6705 globals->fix_cortex_a8 = 0;
6706 }
6707}
6708
6709
c7b8f16e
JB		 6710void
6711bfd_elf32_arm_set_vfp11_fix (bfd *obfd, struct bfd_link_info *link_info)
6712{
6713 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (link_info);
104d59d1 6714 obj_attribute *out_attr = elf_known_obj_attributes_proc (obfd);
906e58ca 6715
4dfe6ac6
NC		 6716 if (globals == NULL)
6717 return;
c7b8f16e
JB		 6718 /* We assume that ARMv7+ does not need the VFP11 denorm erratum fix. */
6719 if (out_attr[Tag_CPU_arch].i >= TAG_CPU_ARCH_V7)
6720 {
6721 switch (globals->vfp11_fix)
99059e56
RM		 6722 {
6723 case BFD_ARM_VFP11_FIX_DEFAULT:
6724 case BFD_ARM_VFP11_FIX_NONE:
6725 globals->vfp11_fix = BFD_ARM_VFP11_FIX_NONE;
6726 break;
6727
6728 default:
6729 /* Give a warning, but do as the user requests anyway. */
6730 (*_bfd_error_handler) (_("%B: warning: selected VFP11 erratum "
6731 "workaround is not necessary for target architecture"), obfd);
6732 }
c7b8f16e
JB		 6733 }
6734 else if (globals->vfp11_fix == BFD_ARM_VFP11_FIX_DEFAULT)
6735 /* For earlier architectures, we might need the workaround, but do not
6736 enable it by default. If users is running with broken hardware, they
6737 must enable the erratum fix explicitly. */
6738 globals->vfp11_fix = BFD_ARM_VFP11_FIX_NONE;
6739}
6740
a504d23a
LA		 6741void
6742bfd_elf32_arm_set_stm32l4xx_fix (bfd *obfd, struct bfd_link_info *link_info)
6743{
6744 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (link_info);
6745 obj_attribute *out_attr = elf_known_obj_attributes_proc (obfd);
6746
6747 if (globals == NULL)
6748 return;
6749
6750 /* We assume only Cortex-M4 may require the fix. */
6751 if (out_attr[Tag_CPU_arch].i != TAG_CPU_ARCH_V7E_M
6752 || out_attr[Tag_CPU_arch_profile].i != 'M')
6753 {
6754 if (globals->stm32l4xx_fix != BFD_ARM_STM32L4XX_FIX_NONE)
6755 /* Give a warning, but do as the user requests anyway. */
6756 (*_bfd_error_handler)
6757 (_("%B: warning: selected STM32L4XX erratum "
6758 "workaround is not necessary for target architecture"), obfd);
6759 }
6760}
c7b8f16e 6761
906e58ca
NC		 6762enum bfd_arm_vfp11_pipe
6763{
c7b8f16e
JB		 6764 VFP11_FMAC,
6765 VFP11_LS,
6766 VFP11_DS,
6767 VFP11_BAD
6768};
6769
6770/* Return a VFP register number. This is encoded as RX:X for single-precision
6771 registers, or X:RX for double-precision registers, where RX is the group of
6772 four bits in the instruction encoding and X is the single extension bit.
6773 RX and X fields are specified using their lowest (starting) bit. The return
6774 value is:
6775
6776 0...31: single-precision registers s0...s31
6777 32...63: double-precision registers d0...d31.
906e58ca 6778
c7b8f16e
JB		 6779 Although X should be zero for VFP11 (encoding d0...d15 only), we might
6780 encounter VFP3 instructions, so we allow the full range for DP registers. */
906e58ca 6781
c7b8f16e
JB		 6782static unsigned int
6783bfd_arm_vfp11_regno (unsigned int insn, bfd_boolean is_double, unsigned int rx,
99059e56 6784 unsigned int x)
c7b8f16e
JB		 6785{
6786 if (is_double)
6787 return (((insn >> rx) & 0xf) | (((insn >> x) & 1) << 4)) + 32;
6788 else
6789 return (((insn >> rx) & 0xf) << 1) | ((insn >> x) & 1);
6790}
6791
6792/* Set bits in *WMASK according to a register number REG as encoded by
6793 bfd_arm_vfp11_regno(). Ignore d16-d31. */
6794
6795static void
6796bfd_arm_vfp11_write_mask (unsigned int *wmask, unsigned int reg)
6797{
6798 if (reg < 32)
6799 *wmask |= 1 << reg;
6800 else if (reg < 48)
6801 *wmask |= 3 << ((reg - 32) * 2);
6802}
6803
6804/* Return TRUE if WMASK overwrites anything in REGS. */
6805
6806static bfd_boolean
6807bfd_arm_vfp11_antidependency (unsigned int wmask, int *regs, int numregs)
6808{
6809 int i;
906e58ca 6810
c7b8f16e
JB		 6811 for (i = 0; i < numregs; i++)
6812 {
6813 unsigned int reg = regs[i];
6814
6815 if (reg < 32 && (wmask & (1 << reg)) != 0)
99059e56 6816 return TRUE;
906e58ca 6817
c7b8f16e
JB		 6818 reg -= 32;
6819
6820 if (reg >= 16)
99059e56 6821 continue;
906e58ca 6822
c7b8f16e 6823 if ((wmask & (3 << (reg * 2))) != 0)
99059e56 6824 return TRUE;
c7b8f16e 6825 }
906e58ca 6826
c7b8f16e
JB		 6827 return FALSE;
6828}
6829
6830/* In this function, we're interested in two things: finding input registers
6831 for VFP data-processing instructions, and finding the set of registers which
6832 arbitrary VFP instructions may write to. We use a 32-bit unsigned int to
6833 hold the written set, so FLDM etc. are easy to deal with (we're only
6834 interested in 32 SP registers or 16 dp registers, due to the VFP version
6835 implemented by the chip in question). DP registers are marked by setting
6836 both SP registers in the write mask). */
6837
6838static enum bfd_arm_vfp11_pipe
6839bfd_arm_vfp11_insn_decode (unsigned int insn, unsigned int *destmask, int *regs,
99059e56 6840 int *numregs)
c7b8f16e 6841{
91d6fa6a 6842 enum bfd_arm_vfp11_pipe vpipe = VFP11_BAD;
c7b8f16e
JB		 6843 bfd_boolean is_double = ((insn & 0xf00) == 0xb00) ? 1 : 0;
6844
6845 if ((insn & 0x0f000e10) == 0x0e000a00) /* A data-processing insn. */
6846 {
6847 unsigned int pqrs;
6848 unsigned int fd = bfd_arm_vfp11_regno (insn, is_double, 12, 22);
6849 unsigned int fm = bfd_arm_vfp11_regno (insn, is_double, 0, 5);
6850
6851 pqrs = ((insn & 0x00800000) >> 20)
99059e56
RM		 6852 | ((insn & 0x00300000) >> 19)
6853 | ((insn & 0x00000040) >> 6);
c7b8f16e
JB		 6854
6855 switch (pqrs)
99059e56
RM		 6856 {
6857 case 0: /* fmac[sd]. */
6858 case 1: /* fnmac[sd]. */
6859 case 2: /* fmsc[sd]. */
6860 case 3: /* fnmsc[sd]. */
6861 vpipe = VFP11_FMAC;
6862 bfd_arm_vfp11_write_mask (destmask, fd);
6863 regs[0] = fd;
6864 regs[1] = bfd_arm_vfp11_regno (insn, is_double, 16, 7); /* Fn. */
6865 regs[2] = fm;
6866 *numregs = 3;
6867 break;
6868
6869 case 4: /* fmul[sd]. */
6870 case 5: /* fnmul[sd]. */
6871 case 6: /* fadd[sd]. */
6872 case 7: /* fsub[sd]. */
6873 vpipe = VFP11_FMAC;
6874 goto vfp_binop;
6875
6876 case 8: /* fdiv[sd]. */
6877 vpipe = VFP11_DS;
6878 vfp_binop:
6879 bfd_arm_vfp11_write_mask (destmask, fd);
6880 regs[0] = bfd_arm_vfp11_regno (insn, is_double, 16, 7); /* Fn. */
6881 regs[1] = fm;
6882 *numregs = 2;
6883 break;
6884
6885 case 15: /* extended opcode. */
6886 {
6887 unsigned int extn = ((insn >> 15) & 0x1e)
6888 | ((insn >> 7) & 1);
6889
6890 switch (extn)
6891 {
6892 case 0: /* fcpy[sd]. */
6893 case 1: /* fabs[sd]. */
6894 case 2: /* fneg[sd]. */
6895 case 8: /* fcmp[sd]. */
6896 case 9: /* fcmpe[sd]. */
6897 case 10: /* fcmpz[sd]. */
6898 case 11: /* fcmpez[sd]. */
6899 case 16: /* fuito[sd]. */
6900 case 17: /* fsito[sd]. */
6901 case 24: /* ftoui[sd]. */
6902 case 25: /* ftouiz[sd]. */
6903 case 26: /* ftosi[sd]. */
6904 case 27: /* ftosiz[sd]. */
6905 /* These instructions will not bounce due to underflow. */
6906 *numregs = 0;
6907 vpipe = VFP11_FMAC;
6908 break;
6909
6910 case 3: /* fsqrt[sd]. */
6911 /* fsqrt cannot underflow, but it can (perhaps) overwrite
6912 registers to cause the erratum in previous instructions. */
6913 bfd_arm_vfp11_write_mask (destmask, fd);
6914 vpipe = VFP11_DS;
6915 break;
6916
6917 case 15: /* fcvt{ds,sd}. */
6918 {
6919 int rnum = 0;
6920
6921 bfd_arm_vfp11_write_mask (destmask, fd);
c7b8f16e
JB		 6922
6923 /* Only FCVTSD can underflow. */
99059e56
RM		 6924 if ((insn & 0x100) != 0)
6925 regs[rnum++] = fm;
c7b8f16e 6926
99059e56 6927 *numregs = rnum;
c7b8f16e 6928
99059e56
RM		 6929 vpipe = VFP11_FMAC;
6930 }
6931 break;
c7b8f16e 6932
99059e56
RM		 6933 default:
6934 return VFP11_BAD;
6935 }
6936 }
6937 break;
c7b8f16e 6938
99059e56
RM		 6939 default:
6940 return VFP11_BAD;
6941 }
c7b8f16e
JB		 6942 }
6943 /* Two-register transfer. */
6944 else if ((insn & 0x0fe00ed0) == 0x0c400a10)
6945 {
6946 unsigned int fm = bfd_arm_vfp11_regno (insn, is_double, 0, 5);
906e58ca 6947
c7b8f16e
JB		 6948 if ((insn & 0x100000) == 0)
6949 {
99059e56
RM		 6950 if (is_double)
6951 bfd_arm_vfp11_write_mask (destmask, fm);
6952 else
6953 {
6954 bfd_arm_vfp11_write_mask (destmask, fm);
6955 bfd_arm_vfp11_write_mask (destmask, fm + 1);
6956 }
c7b8f16e
JB		 6957 }
6958
91d6fa6a 6959 vpipe = VFP11_LS;
c7b8f16e
JB		 6960 }
6961 else if ((insn & 0x0e100e00) == 0x0c100a00) /* A load insn. */
6962 {
6963 int fd = bfd_arm_vfp11_regno (insn, is_double, 12, 22);
6964 unsigned int puw = ((insn >> 21) & 0x1) | (((insn >> 23) & 3) << 1);
906e58ca 6965
c7b8f16e 6966 switch (puw)
99059e56
RM		 6967 {
6968 case 0: /* Two-reg transfer. We should catch these above. */
6969 abort ();
906e58ca 6970
99059e56
RM		 6971 case 2: /* fldm[sdx]. */
6972 case 3:
6973 case 5:
6974 {
6975 unsigned int i, offset = insn & 0xff;
c7b8f16e 6976
99059e56
RM		 6977 if (is_double)
6978 offset >>= 1;
c7b8f16e 6979
99059e56
RM		 6980 for (i = fd; i < fd + offset; i++)
6981 bfd_arm_vfp11_write_mask (destmask, i);
6982 }
6983 break;
906e58ca 6984
99059e56
RM		 6985 case 4: /* fld[sd]. */
6986 case 6:
6987 bfd_arm_vfp11_write_mask (destmask, fd);
6988 break;
906e58ca 6989
99059e56
RM		 6990 default:
6991 return VFP11_BAD;
6992 }
c7b8f16e 6993
91d6fa6a 6994 vpipe = VFP11_LS;
c7b8f16e
JB		 6995 }
6996 /* Single-register transfer. Note L==0. */
6997 else if ((insn & 0x0f100e10) == 0x0e000a10)
6998 {
6999 unsigned int opcode = (insn >> 21) & 7;
7000 unsigned int fn = bfd_arm_vfp11_regno (insn, is_double, 16, 7);
7001
7002 switch (opcode)
99059e56
RM		 7003 {
7004 case 0: /* fmsr/fmdlr. */
7005 case 1: /* fmdhr. */
7006 /* Mark fmdhr and fmdlr as writing to the whole of the DP
7007 destination register. I don't know if this is exactly right,
7008 but it is the conservative choice. */
7009 bfd_arm_vfp11_write_mask (destmask, fn);
7010 break;
7011
7012 case 7: /* fmxr. */
7013 break;
7014 }
c7b8f16e 7015
91d6fa6a 7016 vpipe = VFP11_LS;
c7b8f16e
JB		 7017 }
7018
91d6fa6a 7019 return vpipe;
c7b8f16e
JB		 7020}
7021
7022
7023static int elf32_arm_compare_mapping (const void * a, const void * b);
7024
7025
7026/* Look for potentially-troublesome code sequences which might trigger the
7027 VFP11 denormal/antidependency erratum. See, e.g., the ARM1136 errata sheet
7028 (available from ARM) for details of the erratum. A short version is
7029 described in ld.texinfo. */
7030
7031bfd_boolean
7032bfd_elf32_arm_vfp11_erratum_scan (bfd *abfd, struct bfd_link_info *link_info)
7033{
7034 asection *sec;
7035 bfd_byte *contents = NULL;
7036 int state = 0;
7037 int regs[3], numregs = 0;
7038 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (link_info);
7039 int use_vector = (globals->vfp11_fix == BFD_ARM_VFP11_FIX_VECTOR);
906e58ca 7040
4dfe6ac6
NC		 7041 if (globals == NULL)
7042 return FALSE;
7043
c7b8f16e
JB		 7044 /* We use a simple FSM to match troublesome VFP11 instruction sequences.
7045 The states transition as follows:
906e58ca 7046
c7b8f16e 7047 0 -> 1 (vector) or 0 -> 2 (scalar)
99059e56
RM		 7048 A VFP FMAC-pipeline instruction has been seen. Fill
7049 regs[0]..regs[numregs-1] with its input operands. Remember this
7050 instruction in 'first_fmac'.
c7b8f16e
JB		 7051
7052 1 -> 2
99059e56
RM		 7053 Any instruction, except for a VFP instruction which overwrites
7054 regs[*].
906e58ca 7055
c7b8f16e
JB		 7056 1 -> 3 [ -> 0 ] or
7057 2 -> 3 [ -> 0 ]
99059e56
RM		 7058 A VFP instruction has been seen which overwrites any of regs[*].
7059 We must make a veneer! Reset state to 0 before examining next
7060 instruction.
906e58ca 7061
c7b8f16e 7062 2 -> 0
99059e56
RM		 7063 If we fail to match anything in state 2, reset to state 0 and reset
7064 the instruction pointer to the instruction after 'first_fmac'.
c7b8f16e
JB		 7065
7066 If the VFP11 vector mode is in use, there must be at least two unrelated
7067 instructions between anti-dependent VFP11 instructions to properly avoid
906e58ca 7068 triggering the erratum, hence the use of the extra state 1. */
c7b8f16e
JB		 7069
7070 /* If we are only performing a partial link do not bother
7071 to construct any glue. */
0e1862bb 7072 if (bfd_link_relocatable (link_info))
c7b8f16e
JB		 7073 return TRUE;
7074
0ffa91dd
NC		 7075 /* Skip if this bfd does not correspond to an ELF image. */
7076 if (! is_arm_elf (abfd))
7077 return TRUE;
906e58ca 7078
c7b8f16e
JB		 7079 /* We should have chosen a fix type by the time we get here. */
7080 BFD_ASSERT (globals->vfp11_fix != BFD_ARM_VFP11_FIX_DEFAULT);
7081
7082 if (globals->vfp11_fix == BFD_ARM_VFP11_FIX_NONE)
7083 return TRUE;
2e6030b9 7084
33a7ffc2
JM		 7085 /* Skip this BFD if it corresponds to an executable or dynamic object. */
7086 if ((abfd->flags & (EXEC_P | DYNAMIC)) != 0)
7087 return TRUE;
7088
c7b8f16e
JB		 7089 for (sec = abfd->sections; sec != NULL; sec = sec->next)
7090 {
7091 unsigned int i, span, first_fmac = 0, veneer_of_insn = 0;
7092 struct _arm_elf_section_data *sec_data;
7093
7094 /* If we don't have executable progbits, we're not interested in this
99059e56 7095 section. Also skip if section is to be excluded. */
c7b8f16e 7096 if (elf_section_type (sec) != SHT_PROGBITS
99059e56
RM		 7097 || (elf_section_flags (sec) & SHF_EXECINSTR) == 0
7098 || (sec->flags & SEC_EXCLUDE) != 0
dbaa2011 7099 || sec->sec_info_type == SEC_INFO_TYPE_JUST_SYMS
33a7ffc2 7100 || sec->output_section == bfd_abs_section_ptr
99059e56
RM		 7101 || strcmp (sec->name, VFP11_ERRATUM_VENEER_SECTION_NAME) == 0)
7102 continue;
c7b8f16e
JB		 7103
7104 sec_data = elf32_arm_section_data (sec);
906e58ca 7105
c7b8f16e 7106 if (sec_data->mapcount == 0)
99059e56 7107 continue;
906e58ca 7108
c7b8f16e
JB		 7109 if (elf_section_data (sec)->this_hdr.contents != NULL)
7110 contents = elf_section_data (sec)->this_hdr.contents;
7111 else if (! bfd_malloc_and_get_section (abfd, sec, &contents))
7112 goto error_return;
7113
7114 qsort (sec_data->map, sec_data->mapcount, sizeof (elf32_arm_section_map),
7115 elf32_arm_compare_mapping);
7116
7117 for (span = 0; span < sec_data->mapcount; span++)
99059e56
RM		 7118 {
7119 unsigned int span_start = sec_data->map[span].vma;
7120 unsigned int span_end = (span == sec_data->mapcount - 1)
c7b8f16e 7121 ? sec->size : sec_data->map[span + 1].vma;
99059e56
RM		 7122 char span_type = sec_data->map[span].type;
7123
7124 /* FIXME: Only ARM mode is supported at present. We may need to
7125 support Thumb-2 mode also at some point. */
7126 if (span_type != 'a')
7127 continue;
7128
7129 for (i = span_start; i < span_end;)
7130 {
7131 unsigned int next_i = i + 4;
7132 unsigned int insn = bfd_big_endian (abfd)
7133 ? (contents[i] << 24)
7134 | (contents[i + 1] << 16)
7135 | (contents[i + 2] << 8)
7136 | contents[i + 3]
7137 : (contents[i + 3] << 24)
7138 | (contents[i + 2] << 16)
7139 | (contents[i + 1] << 8)
7140 | contents[i];
7141 unsigned int writemask = 0;
7142 enum bfd_arm_vfp11_pipe vpipe;
7143
7144 switch (state)
7145 {
7146 case 0:
7147 vpipe = bfd_arm_vfp11_insn_decode (insn, &writemask, regs,
7148 &numregs);
7149 /* I'm assuming the VFP11 erratum can trigger with denorm
7150 operands on either the FMAC or the DS pipeline. This might
7151 lead to slightly overenthusiastic veneer insertion. */
7152 if (vpipe == VFP11_FMAC || vpipe == VFP11_DS)
7153 {
7154 state = use_vector ? 1 : 2;
7155 first_fmac = i;
7156 veneer_of_insn = insn;
7157 }
7158 break;
7159
7160 case 1:
7161 {
7162 int other_regs[3], other_numregs;
7163 vpipe = bfd_arm_vfp11_insn_decode (insn, &writemask,
c7b8f16e 7164 other_regs,
99059e56
RM		 7165 &other_numregs);
7166 if (vpipe != VFP11_BAD
7167 && bfd_arm_vfp11_antidependency (writemask, regs,
c7b8f16e 7168 numregs))
99059e56
RM		 7169 state = 3;
7170 else
7171 state = 2;
7172 }
7173 break;
7174
7175 case 2:
7176 {
7177 int other_regs[3], other_numregs;
7178 vpipe = bfd_arm_vfp11_insn_decode (insn, &writemask,
c7b8f16e 7179 other_regs,
99059e56
RM		 7180 &other_numregs);
7181 if (vpipe != VFP11_BAD
7182 && bfd_arm_vfp11_antidependency (writemask, regs,
c7b8f16e 7183 numregs))
99059e56
RM		 7184 state = 3;
7185 else
7186 {
7187 state = 0;
7188 next_i = first_fmac + 4;
7189 }
7190 }
7191 break;
7192
7193 case 3:
7194 abort (); /* Should be unreachable. */
7195 }
7196
7197 if (state == 3)
7198 {
7199 elf32_vfp11_erratum_list *newerr =(elf32_vfp11_erratum_list *)
7200 bfd_zmalloc (sizeof (elf32_vfp11_erratum_list));
7201
7202 elf32_arm_section_data (sec)->erratumcount += 1;
7203
7204 newerr->u.b.vfp_insn = veneer_of_insn;
7205
7206 switch (span_type)
7207 {
7208 case 'a':
7209 newerr->type = VFP11_ERRATUM_BRANCH_TO_ARM_VENEER;
7210 break;
7211
7212 default:
7213 abort ();
7214 }
7215
7216 record_vfp11_erratum_veneer (link_info, newerr, abfd, sec,
c7b8f16e
JB		 7217 first_fmac);
7218
99059e56 7219 newerr->vma = -1;
c7b8f16e 7220
99059e56
RM		 7221 newerr->next = sec_data->erratumlist;
7222 sec_data->erratumlist = newerr;
c7b8f16e 7223
99059e56
RM		 7224 state = 0;
7225 }
c7b8f16e 7226
99059e56
RM		 7227 i = next_i;
7228 }
7229 }
906e58ca 7230
c7b8f16e 7231 if (contents != NULL
99059e56
RM		 7232 && elf_section_data (sec)->this_hdr.contents != contents)
7233 free (contents);
c7b8f16e
JB		 7234 contents = NULL;
7235 }
7236
7237 return TRUE;
7238
7239error_return:
7240 if (contents != NULL
7241 && elf_section_data (sec)->this_hdr.contents != contents)
7242 free (contents);
906e58ca 7243
c7b8f16e
JB		 7244 return FALSE;
7245}
7246
7247/* Find virtual-memory addresses for VFP11 erratum veneers and return locations
7248 after sections have been laid out, using specially-named symbols. */
7249
7250void
7251bfd_elf32_arm_vfp11_fix_veneer_locations (bfd *abfd,
7252 struct bfd_link_info *link_info)
7253{
7254 asection *sec;
7255 struct elf32_arm_link_hash_table *globals;
7256 char *tmp_name;
906e58ca 7257
0e1862bb 7258 if (bfd_link_relocatable (link_info))
c7b8f16e 7259 return;
2e6030b9
MS		 7260
7261 /* Skip if this bfd does not correspond to an ELF image. */
0ffa91dd 7262 if (! is_arm_elf (abfd))
2e6030b9
MS		 7263 return;
7264
c7b8f16e 7265 globals = elf32_arm_hash_table (link_info);
4dfe6ac6
NC		 7266 if (globals == NULL)
7267 return;
906e58ca 7268
21d799b5 7269 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen
99059e56 7270 (VFP11_ERRATUM_VENEER_ENTRY_NAME) + 10);
c7b8f16e
JB		 7271
7272 for (sec = abfd->sections; sec != NULL; sec = sec->next)
7273 {
7274 struct _arm_elf_section_data *sec_data = elf32_arm_section_data (sec);
7275 elf32_vfp11_erratum_list *errnode = sec_data->erratumlist;
906e58ca 7276
c7b8f16e 7277 for (; errnode != NULL; errnode = errnode->next)
99059e56
RM		 7278 {
7279 struct elf_link_hash_entry *myh;
7280 bfd_vma vma;
7281
7282 switch (errnode->type)
7283 {
7284 case VFP11_ERRATUM_BRANCH_TO_ARM_VENEER:
7285 case VFP11_ERRATUM_BRANCH_TO_THUMB_VENEER:
7286 /* Find veneer symbol. */
7287 sprintf (tmp_name, VFP11_ERRATUM_VENEER_ENTRY_NAME,
c7b8f16e
JB		 7288 errnode->u.b.veneer->u.v.id);
7289
99059e56
RM		 7290 myh = elf_link_hash_lookup
7291 (&(globals)->root, tmp_name, FALSE, FALSE, TRUE);
c7b8f16e 7292
a504d23a
LA		 7293 if (myh == NULL)
7294 (*_bfd_error_handler) (_("%B: unable to find VFP11 veneer "
7295 "`%s'"), abfd, tmp_name);
7296
7297 vma = myh->root.u.def.section->output_section->vma
7298 + myh->root.u.def.section->output_offset
7299 + myh->root.u.def.value;
7300
7301 errnode->u.b.veneer->vma = vma;
7302 break;
7303
7304 case VFP11_ERRATUM_ARM_VENEER:
7305 case VFP11_ERRATUM_THUMB_VENEER:
7306 /* Find return location. */
7307 sprintf (tmp_name, VFP11_ERRATUM_VENEER_ENTRY_NAME "_r",
7308 errnode->u.v.id);
7309
7310 myh = elf_link_hash_lookup
7311 (&(globals)->root, tmp_name, FALSE, FALSE, TRUE);
7312
7313 if (myh == NULL)
7314 (*_bfd_error_handler) (_("%B: unable to find VFP11 veneer "
7315 "`%s'"), abfd, tmp_name);
7316
7317 vma = myh->root.u.def.section->output_section->vma
7318 + myh->root.u.def.section->output_offset
7319 + myh->root.u.def.value;
7320
7321 errnode->u.v.branch->vma = vma;
7322 break;
7323
7324 default:
7325 abort ();
7326 }
7327 }
7328 }
7329
7330 free (tmp_name);
7331}
7332
7333/* Find virtual-memory addresses for STM32L4XX erratum veneers and
7334 return locations after sections have been laid out, using
7335 specially-named symbols. */
7336
7337void
7338bfd_elf32_arm_stm32l4xx_fix_veneer_locations (bfd *abfd,
7339 struct bfd_link_info *link_info)
7340{
7341 asection *sec;
7342 struct elf32_arm_link_hash_table *globals;
7343 char *tmp_name;
7344
7345 if (bfd_link_relocatable (link_info))
7346 return;
7347
7348 /* Skip if this bfd does not correspond to an ELF image. */
7349 if (! is_arm_elf (abfd))
7350 return;
7351
7352 globals = elf32_arm_hash_table (link_info);
7353 if (globals == NULL)
7354 return;
7355
7356 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen
7357 (STM32L4XX_ERRATUM_VENEER_ENTRY_NAME) + 10);
7358
7359 for (sec = abfd->sections; sec != NULL; sec = sec->next)
7360 {
7361 struct _arm_elf_section_data *sec_data = elf32_arm_section_data (sec);
7362 elf32_stm32l4xx_erratum_list *errnode = sec_data->stm32l4xx_erratumlist;
7363
7364 for (; errnode != NULL; errnode = errnode->next)
7365 {
7366 struct elf_link_hash_entry *myh;
7367 bfd_vma vma;
7368
7369 switch (errnode->type)
7370 {
7371 case STM32L4XX_ERRATUM_BRANCH_TO_VENEER:
7372 /* Find veneer symbol. */
7373 sprintf (tmp_name, STM32L4XX_ERRATUM_VENEER_ENTRY_NAME,
7374 errnode->u.b.veneer->u.v.id);
7375
7376 myh = elf_link_hash_lookup
7377 (&(globals)->root, tmp_name, FALSE, FALSE, TRUE);
7378
7379 if (myh == NULL)
7380 (*_bfd_error_handler) (_("%B: unable to find STM32L4XX veneer "
7381 "`%s'"), abfd, tmp_name);
7382
7383 vma = myh->root.u.def.section->output_section->vma
7384 + myh->root.u.def.section->output_offset
7385 + myh->root.u.def.value;
7386
7387 errnode->u.b.veneer->vma = vma;
7388 break;
7389
7390 case STM32L4XX_ERRATUM_VENEER:
7391 /* Find return location. */
7392 sprintf (tmp_name, STM32L4XX_ERRATUM_VENEER_ENTRY_NAME "_r",
7393 errnode->u.v.id);
7394
7395 myh = elf_link_hash_lookup
7396 (&(globals)->root, tmp_name, FALSE, FALSE, TRUE);
7397
7398 if (myh == NULL)
7399 (*_bfd_error_handler) (_("%B: unable to find STM32L4XX veneer "
7400 "`%s'"), abfd, tmp_name);
7401
7402 vma = myh->root.u.def.section->output_section->vma
7403 + myh->root.u.def.section->output_offset
7404 + myh->root.u.def.value;
7405
7406 errnode->u.v.branch->vma = vma;
7407 break;
7408
7409 default:
7410 abort ();
7411 }
7412 }
7413 }
7414
7415 free (tmp_name);
7416}
7417
7418static inline bfd_boolean
7419is_thumb2_ldmia (const insn32 insn)
7420{
7421 /* Encoding T2: LDM<c>.W <Rn>{!},<registers>
7422 1110 - 1000 - 10W1 - rrrr - PM (0) l - llll - llll - llll. */
7423 return (insn & 0xffd02000) == 0xe8900000;
7424}
7425
7426static inline bfd_boolean
7427is_thumb2_ldmdb (const insn32 insn)
7428{
7429 /* Encoding T1: LDMDB<c> <Rn>{!},<registers>
7430 1110 - 1001 - 00W1 - rrrr - PM (0) l - llll - llll - llll. */
7431 return (insn & 0xffd02000) == 0xe9100000;
7432}
7433
7434static inline bfd_boolean
7435is_thumb2_vldm (const insn32 insn)
7436{
7437 /* A6.5 Extension register load or store instruction
7438 A7.7.229
7439 We look only for the 32-bit registers case since the DP (64-bit
7440 registers) are not supported for STM32L4XX
7441 Encoding T2 VLDM{mode}<c> <Rn>{!}, <list>
7442 <list> is consecutive 32-bit registers
7443 1110 - 110P - UDW1 - rrrr - vvvv - 1010 - iiii - iiii
7444 if P==0 && U==1 && W==1 && Rn=1101 VPOP
7445 if PUW=010 || PUW=011 || PUW=101 VLDM. */
7446 return
7447 ((insn & 0xfe100f00) == 0xec100a00)
7448 && /* (IA without !). */
7449 (((((insn << 7) >> 28) & 0xd) == 0x4)
7450 /* (IA with !), includes VPOP (when reg number is SP). */
7451 || ((((insn << 7) >> 28) & 0xd) == 0x5)
7452 /* (DB with !). */
7453 || ((((insn << 7) >> 28) & 0xd) == 0x9));
7454}
7455
7456/* STM STM32L4XX erratum : This function assumes that it receives an LDM or
7457 VLDM opcode and:
7458 - computes the number and the mode of memory accesses
7459 - decides if the replacement should be done:
7460 . replaces only if > 8-word accesses
7461 . or (testing purposes only) replaces all accesses. */
7462
7463static bfd_boolean
7464stm32l4xx_need_create_replacing_stub (const insn32 insn,
7465 bfd_arm_stm32l4xx_fix stm32l4xx_fix)
7466{
7467 int nb_regs = 0;
7468
7469 /* The field encoding the register list is the same for both LDMIA
7470 and LDMDB encodings. */
7471 if (is_thumb2_ldmia (insn) || is_thumb2_ldmdb (insn))
7472 nb_regs = popcount (insn & 0x0000ffff);
7473 else if (is_thumb2_vldm (insn))
7474 nb_regs = (insn & 0xff);
7475
7476 /* DEFAULT mode accounts for the real bug condition situation,
7477 ALL mode inserts stubs for each LDM/VLDM instruction (testing). */
7478 return
7479 (stm32l4xx_fix == BFD_ARM_STM32L4XX_FIX_DEFAULT) ? nb_regs > 8 :
7480 (stm32l4xx_fix == BFD_ARM_STM32L4XX_FIX_ALL) ? TRUE : FALSE;
7481}
7482
7483/* Look for potentially-troublesome code sequences which might trigger
7484 the STM STM32L4XX erratum. */
7485
7486bfd_boolean
7487bfd_elf32_arm_stm32l4xx_erratum_scan (bfd *abfd,
7488 struct bfd_link_info *link_info)
7489{
7490 asection *sec;
7491 bfd_byte *contents = NULL;
7492 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (link_info);
7493
7494 if (globals == NULL)
7495 return FALSE;
7496
7497 /* If we are only performing a partial link do not bother
7498 to construct any glue. */
7499 if (bfd_link_relocatable (link_info))
7500 return TRUE;
7501
7502 /* Skip if this bfd does not correspond to an ELF image. */
7503 if (! is_arm_elf (abfd))
7504 return TRUE;
7505
7506 if (globals->stm32l4xx_fix == BFD_ARM_STM32L4XX_FIX_NONE)
7507 return TRUE;
7508
7509 /* Skip this BFD if it corresponds to an executable or dynamic object. */
7510 if ((abfd->flags & (EXEC_P | DYNAMIC)) != 0)
7511 return TRUE;
7512
7513 for (sec = abfd->sections; sec != NULL; sec = sec->next)
7514 {
7515 unsigned int i, span;
7516 struct _arm_elf_section_data *sec_data;
7517
7518 /* If we don't have executable progbits, we're not interested in this
7519 section. Also skip if section is to be excluded. */
7520 if (elf_section_type (sec) != SHT_PROGBITS
7521 || (elf_section_flags (sec) & SHF_EXECINSTR) == 0
7522 || (sec->flags & SEC_EXCLUDE) != 0
7523 || sec->sec_info_type == SEC_INFO_TYPE_JUST_SYMS
7524 || sec->output_section == bfd_abs_section_ptr
7525 || strcmp (sec->name, STM32L4XX_ERRATUM_VENEER_SECTION_NAME) == 0)
7526 continue;
7527
7528 sec_data = elf32_arm_section_data (sec);
c7b8f16e 7529
a504d23a
LA		 7530 if (sec_data->mapcount == 0)
7531 continue;
c7b8f16e 7532
a504d23a
LA		 7533 if (elf_section_data (sec)->this_hdr.contents != NULL)
7534 contents = elf_section_data (sec)->this_hdr.contents;
7535 else if (! bfd_malloc_and_get_section (abfd, sec, &contents))
7536 goto error_return;
c7b8f16e 7537
a504d23a
LA		 7538 qsort (sec_data->map, sec_data->mapcount, sizeof (elf32_arm_section_map),
7539 elf32_arm_compare_mapping);
c7b8f16e 7540
a504d23a
LA		 7541 for (span = 0; span < sec_data->mapcount; span++)
7542 {
7543 unsigned int span_start = sec_data->map[span].vma;
7544 unsigned int span_end = (span == sec_data->mapcount - 1)
7545 ? sec->size : sec_data->map[span + 1].vma;
7546 char span_type = sec_data->map[span].type;
7547 int itblock_current_pos = 0;
c7b8f16e 7548
a504d23a
LA		 7549 /* Only Thumb2 mode need be supported with this CM4 specific
7550 code, we should not encounter any arm mode eg span_type
7551 != 'a'. */
7552 if (span_type != 't')
7553 continue;
c7b8f16e 7554
a504d23a
LA		 7555 for (i = span_start; i < span_end;)
7556 {
7557 unsigned int insn = bfd_get_16 (abfd, &contents[i]);
7558 bfd_boolean insn_32bit = FALSE;
7559 bfd_boolean is_ldm = FALSE;
7560 bfd_boolean is_vldm = FALSE;
7561 bfd_boolean is_not_last_in_it_block = FALSE;
7562
7563 /* The first 16-bits of all 32-bit thumb2 instructions start
7564 with opcode[15..13]=0b111 and the encoded op1 can be anything
7565 except opcode[12..11]!=0b00.
7566 See 32-bit Thumb instruction encoding. */
7567 if ((insn & 0xe000) == 0xe000 && (insn & 0x1800) != 0x0000)
7568 insn_32bit = TRUE;
c7b8f16e 7569
a504d23a
LA		 7570 /* Compute the predicate that tells if the instruction
7571 is concerned by the IT block
7572 - Creates an error if there is a ldm that is not
7573 last in the IT block thus cannot be replaced
7574 - Otherwise we can create a branch at the end of the
7575 IT block, it will be controlled naturally by IT
7576 with the proper pseudo-predicate
7577 - So the only interesting predicate is the one that
7578 tells that we are not on the last item of an IT
7579 block. */
7580 if (itblock_current_pos != 0)
7581 is_not_last_in_it_block = !!--itblock_current_pos;
906e58ca 7582
a504d23a
LA		 7583 if (insn_32bit)
7584 {
7585 /* Load the rest of the insn (in manual-friendly order). */
7586 insn = (insn << 16) | bfd_get_16 (abfd, &contents[i + 2]);
7587 is_ldm = is_thumb2_ldmia (insn) || is_thumb2_ldmdb (insn);
7588 is_vldm = is_thumb2_vldm (insn);
7589
7590 /* Veneers are created for (v)ldm depending on
7591 option flags and memory accesses conditions; but
7592 if the instruction is not the last instruction of
7593 an IT block, we cannot create a jump there, so we
7594 bail out. */
7595 if ((is_ldm || is_vldm) &&
7596 stm32l4xx_need_create_replacing_stub
7597 (insn, globals->stm32l4xx_fix))
7598 {
7599 if (is_not_last_in_it_block)
7600 {
7601 (*_bfd_error_handler)
7602 /* Note - overlong line used here to allow for translation. */
7603 (_("\
7604%B(%A+0x%lx): error: multiple load detected in non-last IT block instruction : STM32L4XX veneer cannot be generated.\n"
7605 "Use gcc option -mrestrict-it to generate only one instruction per IT block.\n"),
7606 abfd, sec, (long)i);
7607 }
7608 else
7609 {
7610 elf32_stm32l4xx_erratum_list *newerr =
7611 (elf32_stm32l4xx_erratum_list *)
7612 bfd_zmalloc
7613 (sizeof (elf32_stm32l4xx_erratum_list));
7614
7615 elf32_arm_section_data (sec)
7616 ->stm32l4xx_erratumcount += 1;
7617 newerr->u.b.insn = insn;
7618 /* We create only thumb branches. */
7619 newerr->type =
7620 STM32L4XX_ERRATUM_BRANCH_TO_VENEER;
7621 record_stm32l4xx_erratum_veneer
7622 (link_info, newerr, abfd, sec,
7623 i,
7624 is_ldm ?
7625 STM32L4XX_ERRATUM_LDM_VENEER_SIZE:
7626 STM32L4XX_ERRATUM_VLDM_VENEER_SIZE);
7627 newerr->vma = -1;
7628 newerr->next = sec_data->stm32l4xx_erratumlist;
7629 sec_data->stm32l4xx_erratumlist = newerr;
7630 }
7631 }
7632 }
7633 else
7634 {
7635 /* A7.7.37 IT p208
7636 IT blocks are only encoded in T1
7637 Encoding T1: IT{x{y{z}}} <firstcond>
7638 1 0 1 1 - 1 1 1 1 - firstcond - mask
7639 if mask = '0000' then see 'related encodings'
7640 We don't deal with UNPREDICTABLE, just ignore these.
7641 There can be no nested IT blocks so an IT block
7642 is naturally a new one for which it is worth
7643 computing its size. */
7644 bfd_boolean is_newitblock = ((insn & 0xff00) == 0xbf00) &&
7645 ((insn & 0x000f) != 0x0000);
7646 /* If we have a new IT block we compute its size. */
7647 if (is_newitblock)
7648 {
7649 /* Compute the number of instructions controlled
7650 by the IT block, it will be used to decide
7651 whether we are inside an IT block or not. */
7652 unsigned int mask = insn & 0x000f;
7653 itblock_current_pos = 4 - ctz (mask);
7654 }
7655 }
7656
7657 i += insn_32bit ? 4 : 2;
99059e56
RM		 7658 }
7659 }
a504d23a
LA		 7660
7661 if (contents != NULL
7662 && elf_section_data (sec)->this_hdr.contents != contents)
7663 free (contents);
7664 contents = NULL;
c7b8f16e 7665 }
906e58ca 7666
a504d23a
LA		 7667 return TRUE;
7668
7669error_return:
7670 if (contents != NULL
7671 && elf_section_data (sec)->this_hdr.contents != contents)
7672 free (contents);
c7b8f16e 7673
a504d23a
LA		 7674 return FALSE;
7675}
c7b8f16e 7676
eb043451
PB		 7677/* Set target relocation values needed during linking. */
7678
7679void
bf21ed78
MS		 7680bfd_elf32_arm_set_target_relocs (struct bfd *output_bfd,
7681 struct bfd_link_info *link_info,
eb043451 7682 int target1_is_rel,
319850b4 7683 char * target2_type,
99059e56 7684 int fix_v4bx,
c7b8f16e 7685 int use_blx,
99059e56 7686 bfd_arm_vfp11_fix vfp11_fix,
a504d23a 7687 bfd_arm_stm32l4xx_fix stm32l4xx_fix,
a9dc9481 7688 int no_enum_warn, int no_wchar_warn,
2de70689
MGD		 7689 int pic_veneer, int fix_cortex_a8,
7690 int fix_arm1176)
eb043451
PB		 7691{
7692 struct elf32_arm_link_hash_table *globals;
7693
7694 globals = elf32_arm_hash_table (link_info);
4dfe6ac6
NC		 7695 if (globals == NULL)
7696 return;
eb043451
PB		 7697
7698 globals->target1_is_rel = target1_is_rel;
7699 if (strcmp (target2_type, "rel") == 0)
7700 globals->target2_reloc = R_ARM_REL32;
eeac373a
PB		 7701 else if (strcmp (target2_type, "abs") == 0)
7702 globals->target2_reloc = R_ARM_ABS32;
eb043451
PB		 7703 else if (strcmp (target2_type, "got-rel") == 0)
7704 globals->target2_reloc = R_ARM_GOT_PREL;
7705 else
7706 {
7707 _bfd_error_handler (_("Invalid TARGET2 relocation type '%s'."),
7708 target2_type);
7709 }
319850b4 7710 globals->fix_v4bx = fix_v4bx;
33bfe774 7711 globals->use_blx |= use_blx;
c7b8f16e 7712 globals->vfp11_fix = vfp11_fix;
a504d23a 7713 globals->stm32l4xx_fix = stm32l4xx_fix;
27e55c4d 7714 globals->pic_veneer = pic_veneer;
48229727 7715 globals->fix_cortex_a8 = fix_cortex_a8;
2de70689 7716 globals->fix_arm1176 = fix_arm1176;
bf21ed78 7717
0ffa91dd
NC		 7718 BFD_ASSERT (is_arm_elf (output_bfd));
7719 elf_arm_tdata (output_bfd)->no_enum_size_warning = no_enum_warn;
a9dc9481 7720 elf_arm_tdata (output_bfd)->no_wchar_size_warning = no_wchar_warn;
eb043451 7721}
eb043451 7722
12a0a0fd 7723/* Replace the target offset of a Thumb bl or b.w instruction. */
252b5132 7724
12a0a0fd
PB		 7725static void
7726insert_thumb_branch (bfd *abfd, long int offset, bfd_byte *insn)
7727{
7728 bfd_vma upper;
7729 bfd_vma lower;
7730 int reloc_sign;
7731
7732 BFD_ASSERT ((offset & 1) == 0);
7733
7734 upper = bfd_get_16 (abfd, insn);
7735 lower = bfd_get_16 (abfd, insn + 2);
7736 reloc_sign = (offset < 0) ? 1 : 0;
7737 upper = (upper & ~(bfd_vma) 0x7ff)
7738 | ((offset >> 12) & 0x3ff)
7739 | (reloc_sign << 10);
906e58ca 7740 lower = (lower & ~(bfd_vma) 0x2fff)
12a0a0fd
PB		 7741 | (((!((offset >> 23) & 1)) ^ reloc_sign) << 13)
7742 | (((!((offset >> 22) & 1)) ^ reloc_sign) << 11)
7743 | ((offset >> 1) & 0x7ff);
7744 bfd_put_16 (abfd, upper, insn);
7745 bfd_put_16 (abfd, lower, insn + 2);
252b5132
RH		 7746}
7747
9b485d32
NC		 7748/* Thumb code calling an ARM function. */
7749
252b5132 7750static int
57e8b36a
NC		 7751elf32_thumb_to_arm_stub (struct bfd_link_info * info,
7752 const char * name,
7753 bfd * input_bfd,
7754 bfd * output_bfd,
7755 asection * input_section,
7756 bfd_byte * hit_data,
7757 asection * sym_sec,
7758 bfd_vma offset,
7759 bfd_signed_vma addend,
f2a9dd69
DJ		 7760 bfd_vma val,
7761 char **error_message)
252b5132 7762{
bcbdc74c 7763 asection * s = 0;
dc810e39 7764 bfd_vma my_offset;
252b5132 7765 long int ret_offset;
bcbdc74c
NC		 7766 struct elf_link_hash_entry * myh;
7767 struct elf32_arm_link_hash_table * globals;
252b5132 7768
f2a9dd69 7769 myh = find_thumb_glue (info, name, error_message);
252b5132 7770 if (myh == NULL)
b34976b6 7771 return FALSE;
252b5132
RH		 7772
7773 globals = elf32_arm_hash_table (info);
252b5132
RH		 7774 BFD_ASSERT (globals != NULL);
7775 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
7776
7777 my_offset = myh->root.u.def.value;
7778
3d4d4302
AM		 7779 s = bfd_get_linker_section (globals->bfd_of_glue_owner,
7780 THUMB2ARM_GLUE_SECTION_NAME);
252b5132
RH		 7781
7782 BFD_ASSERT (s != NULL);
7783 BFD_ASSERT (s->contents != NULL);
7784 BFD_ASSERT (s->output_section != NULL);
7785
7786 if ((my_offset & 0x01) == 0x01)
7787 {
7788 if (sym_sec != NULL
7789 && sym_sec->owner != NULL
7790 && !INTERWORK_FLAG (sym_sec->owner))
7791 {
8f615d07 7792 (*_bfd_error_handler)
d003868e 7793 (_("%B(%s): warning: interworking not enabled.\n"
3aaeb7d3 7794 " first occurrence: %B: Thumb call to ARM"),
d003868e 7795 sym_sec->owner, input_bfd, name);
252b5132 7796
b34976b6 7797 return FALSE;
252b5132
RH		 7798 }
7799
7800 --my_offset;
7801 myh->root.u.def.value = my_offset;
7802
52ab56c2
PB		 7803 put_thumb_insn (globals, output_bfd, (bfd_vma) t2a1_bx_pc_insn,
7804 s->contents + my_offset);
252b5132 7805
52ab56c2
PB		 7806 put_thumb_insn (globals, output_bfd, (bfd_vma) t2a2_noop_insn,
7807 s->contents + my_offset + 2);
252b5132
RH		 7808
7809 ret_offset =
9b485d32
NC		 7810 /* Address of destination of the stub. */
7811 ((bfd_signed_vma) val)
252b5132 7812 - ((bfd_signed_vma)
57e8b36a
NC		 7813 /* Offset from the start of the current section
7814 to the start of the stubs. */
9b485d32
NC		 7815 (s->output_offset
7816 /* Offset of the start of this stub from the start of the stubs. */
7817 + my_offset
7818 /* Address of the start of the current section. */
7819 + s->output_section->vma)
7820 /* The branch instruction is 4 bytes into the stub. */
7821 + 4
7822 /* ARM branches work from the pc of the instruction + 8. */
7823 + 8);
252b5132 7824
52ab56c2
PB		 7825 put_arm_insn (globals, output_bfd,
7826 (bfd_vma) t2a3_b_insn | ((ret_offset >> 2) & 0x00FFFFFF),
7827 s->contents + my_offset + 4);
252b5132
RH		 7828 }
7829
7830 BFD_ASSERT (my_offset <= globals->thumb_glue_size);
7831
427bfd90
NC		 7832 /* Now go back and fix up the original BL insn to point to here. */
7833 ret_offset =
7834 /* Address of where the stub is located. */
7835 (s->output_section->vma + s->output_offset + my_offset)
7836 /* Address of where the BL is located. */
57e8b36a
NC		 7837 - (input_section->output_section->vma + input_section->output_offset
7838 + offset)
427bfd90
NC		 7839 /* Addend in the relocation. */
7840 - addend
7841 /* Biassing for PC-relative addressing. */
7842 - 8;
252b5132 7843
12a0a0fd 7844 insert_thumb_branch (input_bfd, ret_offset, hit_data - input_section->vma);
252b5132 7845
b34976b6 7846 return TRUE;
252b5132
RH		 7847}
7848
a4fd1a8e 7849/* Populate an Arm to Thumb stub. Returns the stub symbol. */
9b485d32 7850
a4fd1a8e
PB		 7851static struct elf_link_hash_entry *
7852elf32_arm_create_thumb_stub (struct bfd_link_info * info,
7853 const char * name,
7854 bfd * input_bfd,
7855 bfd * output_bfd,
7856 asection * sym_sec,
7857 bfd_vma val,
8029a119
NC		 7858 asection * s,
7859 char ** error_message)
252b5132 7860{
dc810e39 7861 bfd_vma my_offset;
252b5132 7862 long int ret_offset;
bcbdc74c
NC		 7863 struct elf_link_hash_entry * myh;
7864 struct elf32_arm_link_hash_table * globals;
252b5132 7865
f2a9dd69 7866 myh = find_arm_glue (info, name, error_message);
252b5132 7867 if (myh == NULL)
a4fd1a8e 7868 return NULL;
252b5132
RH		 7869
7870 globals = elf32_arm_hash_table (info);
252b5132
RH		 7871 BFD_ASSERT (globals != NULL);
7872 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
7873
7874 my_offset = myh->root.u.def.value;
252b5132
RH		 7875
7876 if ((my_offset & 0x01) == 0x01)
7877 {
7878 if (sym_sec != NULL
7879 && sym_sec->owner != NULL
7880 && !INTERWORK_FLAG (sym_sec->owner))
7881 {
8f615d07 7882 (*_bfd_error_handler)
d003868e
AM		 7883 (_("%B(%s): warning: interworking not enabled.\n"
7884 " first occurrence: %B: arm call to thumb"),
7885 sym_sec->owner, input_bfd, name);
252b5132 7886 }
9b485d32 7887
252b5132
RH		 7888 --my_offset;
7889 myh->root.u.def.value = my_offset;
7890
0e1862bb
L		 7891 if (bfd_link_pic (info)
7892 || globals->root.is_relocatable_executable
27e55c4d 7893 || globals->pic_veneer)
8f6277f5
PB		 7894 {
7895 /* For relocatable objects we can't use absolute addresses,
7896 so construct the address from a relative offset. */
7897 /* TODO: If the offset is small it's probably worth
7898 constructing the address with adds. */
52ab56c2
PB		 7899 put_arm_insn (globals, output_bfd, (bfd_vma) a2t1p_ldr_insn,
7900 s->contents + my_offset);
7901 put_arm_insn (globals, output_bfd, (bfd_vma) a2t2p_add_pc_insn,
7902 s->contents + my_offset + 4);
7903 put_arm_insn (globals, output_bfd, (bfd_vma) a2t3p_bx_r12_insn,
7904 s->contents + my_offset + 8);
8f6277f5
PB		 7905 /* Adjust the offset by 4 for the position of the add,
7906 and 8 for the pipeline offset. */
7907 ret_offset = (val - (s->output_offset
7908 + s->output_section->vma
7909 + my_offset + 12))
7910 | 1;
7911 bfd_put_32 (output_bfd, ret_offset,
7912 s->contents + my_offset + 12);
7913 }
26079076
PB		 7914 else if (globals->use_blx)
7915 {
7916 put_arm_insn (globals, output_bfd, (bfd_vma) a2t1v5_ldr_insn,
7917 s->contents + my_offset);
7918
7919 /* It's a thumb address. Add the low order bit. */
7920 bfd_put_32 (output_bfd, val | a2t2v5_func_addr_insn,
7921 s->contents + my_offset + 4);
7922 }
8f6277f5
PB		 7923 else
7924 {
52ab56c2
PB		 7925 put_arm_insn (globals, output_bfd, (bfd_vma) a2t1_ldr_insn,
7926 s->contents + my_offset);
252b5132 7927
52ab56c2
PB		 7928 put_arm_insn (globals, output_bfd, (bfd_vma) a2t2_bx_r12_insn,
7929 s->contents + my_offset + 4);
252b5132 7930
8f6277f5
PB		 7931 /* It's a thumb address. Add the low order bit. */
7932 bfd_put_32 (output_bfd, val | a2t3_func_addr_insn,
7933 s->contents + my_offset + 8);
8029a119
NC		 7934
7935 my_offset += 12;
8f6277f5 7936 }
252b5132
RH		 7937 }
7938
7939 BFD_ASSERT (my_offset <= globals->arm_glue_size);
7940
a4fd1a8e
PB		 7941 return myh;
7942}
7943
7944/* Arm code calling a Thumb function. */
7945
7946static int
7947elf32_arm_to_thumb_stub (struct bfd_link_info * info,
7948 const char * name,
7949 bfd * input_bfd,
7950 bfd * output_bfd,
7951 asection * input_section,
7952 bfd_byte * hit_data,
7953 asection * sym_sec,
7954 bfd_vma offset,
7955 bfd_signed_vma addend,
f2a9dd69
DJ		 7956 bfd_vma val,
7957 char **error_message)
a4fd1a8e
PB		 7958{
7959 unsigned long int tmp;
7960 bfd_vma my_offset;
7961 asection * s;
7962 long int ret_offset;
7963 struct elf_link_hash_entry * myh;
7964 struct elf32_arm_link_hash_table * globals;
7965
7966 globals = elf32_arm_hash_table (info);
a4fd1a8e
PB		 7967 BFD_ASSERT (globals != NULL);
7968 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
7969
3d4d4302
AM		 7970 s = bfd_get_linker_section (globals->bfd_of_glue_owner,
7971 ARM2THUMB_GLUE_SECTION_NAME);
a4fd1a8e
PB		 7972 BFD_ASSERT (s != NULL);
7973 BFD_ASSERT (s->contents != NULL);
7974 BFD_ASSERT (s->output_section != NULL);
7975
7976 myh = elf32_arm_create_thumb_stub (info, name, input_bfd, output_bfd,
f2a9dd69 7977 sym_sec, val, s, error_message);
a4fd1a8e
PB		 7978 if (!myh)
7979 return FALSE;
7980
7981 my_offset = myh->root.u.def.value;
252b5132
RH		 7982 tmp = bfd_get_32 (input_bfd, hit_data);
7983 tmp = tmp & 0xFF000000;
7984
9b485d32 7985 /* Somehow these are both 4 too far, so subtract 8. */
dc810e39
AM		 7986 ret_offset = (s->output_offset
7987 + my_offset
7988 + s->output_section->vma
7989 - (input_section->output_offset
7990 + input_section->output_section->vma
7991 + offset + addend)
7992 - 8);
9a5aca8c 7993
252b5132
RH		 7994 tmp = tmp | ((ret_offset >> 2) & 0x00FFFFFF);
7995
dc810e39 7996 bfd_put_32 (output_bfd, (bfd_vma) tmp, hit_data - input_section->vma);
252b5132 7997
b34976b6 7998 return TRUE;
252b5132
RH		 7999}
8000
a4fd1a8e
PB		 8001/* Populate Arm stub for an exported Thumb function. */
8002
8003static bfd_boolean
8004elf32_arm_to_thumb_export_stub (struct elf_link_hash_entry *h, void * inf)
8005{
8006 struct bfd_link_info * info = (struct bfd_link_info *) inf;
8007 asection * s;
8008 struct elf_link_hash_entry * myh;
8009 struct elf32_arm_link_hash_entry *eh;
8010 struct elf32_arm_link_hash_table * globals;
8011 asection *sec;
8012 bfd_vma val;
f2a9dd69 8013 char *error_message;
a4fd1a8e 8014
906e58ca 8015 eh = elf32_arm_hash_entry (h);
a4fd1a8e
PB		 8016 /* Allocate stubs for exported Thumb functions on v4t. */
8017 if (eh->export_glue == NULL)
8018 return TRUE;
8019
8020 globals = elf32_arm_hash_table (info);
a4fd1a8e
PB		 8021 BFD_ASSERT (globals != NULL);
8022 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
8023
3d4d4302
AM		 8024 s = bfd_get_linker_section (globals->bfd_of_glue_owner,
8025 ARM2THUMB_GLUE_SECTION_NAME);
a4fd1a8e
PB		 8026 BFD_ASSERT (s != NULL);
8027 BFD_ASSERT (s->contents != NULL);
8028 BFD_ASSERT (s->output_section != NULL);
8029
8030 sec = eh->export_glue->root.u.def.section;
0eaedd0e
PB		 8031
8032 BFD_ASSERT (sec->output_section != NULL);
8033
a4fd1a8e
PB		 8034 val = eh->export_glue->root.u.def.value + sec->output_offset
8035 + sec->output_section->vma;
8029a119 8036
a4fd1a8e
PB		 8037 myh = elf32_arm_create_thumb_stub (info, h->root.root.string,
8038 h->root.u.def.section->owner,
f2a9dd69
DJ		 8039 globals->obfd, sec, val, s,
8040 &error_message);
a4fd1a8e
PB		 8041 BFD_ASSERT (myh);
8042 return TRUE;
8043}
8044
845b51d6
PB		 8045/* Populate ARMv4 BX veneers. Returns the absolute adress of the veneer. */
8046
8047static bfd_vma
8048elf32_arm_bx_glue (struct bfd_link_info * info, int reg)
8049{
8050 bfd_byte *p;
8051 bfd_vma glue_addr;
8052 asection *s;
8053 struct elf32_arm_link_hash_table *globals;
8054
8055 globals = elf32_arm_hash_table (info);
845b51d6
PB		 8056 BFD_ASSERT (globals != NULL);
8057 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
8058
3d4d4302
AM		 8059 s = bfd_get_linker_section (globals->bfd_of_glue_owner,
8060 ARM_BX_GLUE_SECTION_NAME);
845b51d6
PB		 8061 BFD_ASSERT (s != NULL);
8062 BFD_ASSERT (s->contents != NULL);
8063 BFD_ASSERT (s->output_section != NULL);
8064
8065 BFD_ASSERT (globals->bx_glue_offset[reg] & 2);
8066
8067 glue_addr = globals->bx_glue_offset[reg] & ~(bfd_vma)3;
8068
8069 if ((globals->bx_glue_offset[reg] & 1) == 0)
8070 {
8071 p = s->contents + glue_addr;
8072 bfd_put_32 (globals->obfd, armbx1_tst_insn + (reg << 16), p);
8073 bfd_put_32 (globals->obfd, armbx2_moveq_insn + reg, p + 4);
8074 bfd_put_32 (globals->obfd, armbx3_bx_insn + reg, p + 8);
8075 globals->bx_glue_offset[reg] |= 1;
8076 }
8077
8078 return glue_addr + s->output_section->vma + s->output_offset;
8079}
8080
a4fd1a8e
PB		 8081/* Generate Arm stubs for exported Thumb symbols. */
8082static void
906e58ca 8083elf32_arm_begin_write_processing (bfd *abfd ATTRIBUTE_UNUSED,
a4fd1a8e
PB		 8084 struct bfd_link_info *link_info)
8085{
8086 struct elf32_arm_link_hash_table * globals;
8087
8029a119
NC		 8088 if (link_info == NULL)
8089 /* Ignore this if we are not called by the ELF backend linker. */
a4fd1a8e
PB		 8090 return;
8091
8092 globals = elf32_arm_hash_table (link_info);
4dfe6ac6
NC		 8093 if (globals == NULL)
8094 return;
8095
84c08195
PB		 8096 /* If blx is available then exported Thumb symbols are OK and there is
8097 nothing to do. */
a4fd1a8e
PB		 8098 if (globals->use_blx)
8099 return;
8100
8101 elf_link_hash_traverse (&globals->root, elf32_arm_to_thumb_export_stub,
8102 link_info);
8103}
8104
47beaa6a
RS		 8105/* Reserve space for COUNT dynamic relocations in relocation selection
8106 SRELOC. */
8107
8108static void
8109elf32_arm_allocate_dynrelocs (struct bfd_link_info *info, asection *sreloc,
8110 bfd_size_type count)
8111{
8112 struct elf32_arm_link_hash_table *htab;
8113
8114 htab = elf32_arm_hash_table (info);
8115 BFD_ASSERT (htab->root.dynamic_sections_created);
8116 if (sreloc == NULL)
8117 abort ();
8118 sreloc->size += RELOC_SIZE (htab) * count;
8119}
8120
34e77a92
RS		 8121/* Reserve space for COUNT R_ARM_IRELATIVE relocations. If the link is
8122 dynamic, the relocations should go in SRELOC, otherwise they should
8123 go in the special .rel.iplt section. */
8124
8125static void
8126elf32_arm_allocate_irelocs (struct bfd_link_info *info, asection *sreloc,
8127 bfd_size_type count)
8128{
8129 struct elf32_arm_link_hash_table *htab;
8130
8131 htab = elf32_arm_hash_table (info);
8132 if (!htab->root.dynamic_sections_created)
8133 htab->root.irelplt->size += RELOC_SIZE (htab) * count;
8134 else
8135 {
8136 BFD_ASSERT (sreloc != NULL);
8137 sreloc->size += RELOC_SIZE (htab) * count;
8138 }
8139}
8140
47beaa6a
RS		 8141/* Add relocation REL to the end of relocation section SRELOC. */
8142
8143static void
8144elf32_arm_add_dynreloc (bfd *output_bfd, struct bfd_link_info *info,
8145 asection *sreloc, Elf_Internal_Rela *rel)
8146{
8147 bfd_byte *loc;
8148 struct elf32_arm_link_hash_table *htab;
8149
8150 htab = elf32_arm_hash_table (info);
34e77a92
RS		 8151 if (!htab->root.dynamic_sections_created
8152 && ELF32_R_TYPE (rel->r_info) == R_ARM_IRELATIVE)
8153 sreloc = htab->root.irelplt;
47beaa6a
RS		 8154 if (sreloc == NULL)
8155 abort ();
8156 loc = sreloc->contents;
8157 loc += sreloc->reloc_count++ * RELOC_SIZE (htab);
8158 if (sreloc->reloc_count * RELOC_SIZE (htab) > sreloc->size)
8159 abort ();
8160 SWAP_RELOC_OUT (htab) (output_bfd, rel, loc);
8161}
8162
34e77a92
RS		 8163/* Allocate room for a PLT entry described by ROOT_PLT and ARM_PLT.
8164 IS_IPLT_ENTRY says whether the entry belongs to .iplt rather than
8165 to .plt. */
8166
8167static void
8168elf32_arm_allocate_plt_entry (struct bfd_link_info *info,
8169 bfd_boolean is_iplt_entry,
8170 union gotplt_union *root_plt,
8171 struct arm_plt_info *arm_plt)
8172{
8173 struct elf32_arm_link_hash_table *htab;
8174 asection *splt;
8175 asection *sgotplt;
8176
8177 htab = elf32_arm_hash_table (info);
8178
8179 if (is_iplt_entry)
8180 {
8181 splt = htab->root.iplt;
8182 sgotplt = htab->root.igotplt;
8183
99059e56
RM		 8184 /* NaCl uses a special first entry in .iplt too. */
8185 if (htab->nacl_p && splt->size == 0)
8186 splt->size += htab->plt_header_size;
8187
34e77a92
RS		 8188 /* Allocate room for an R_ARM_IRELATIVE relocation in .rel.iplt. */
8189 elf32_arm_allocate_irelocs (info, htab->root.irelplt, 1);
8190 }
8191 else
8192 {
8193 splt = htab->root.splt;
8194 sgotplt = htab->root.sgotplt;
8195
8196 /* Allocate room for an R_JUMP_SLOT relocation in .rel.plt. */
8197 elf32_arm_allocate_dynrelocs (info, htab->root.srelplt, 1);
8198
8199 /* If this is the first .plt entry, make room for the special
8200 first entry. */
8201 if (splt->size == 0)
8202 splt->size += htab->plt_header_size;
9f19ab6d
WN		 8203
8204 htab->next_tls_desc_index++;
34e77a92
RS		 8205 }
8206
8207 /* Allocate the PLT entry itself, including any leading Thumb stub. */
8208 if (elf32_arm_plt_needs_thumb_stub_p (info, arm_plt))
8209 splt->size += PLT_THUMB_STUB_SIZE;
8210 root_plt->offset = splt->size;
8211 splt->size += htab->plt_entry_size;
8212
8213 if (!htab->symbian_p)
8214 {
8215 /* We also need to make an entry in the .got.plt section, which
8216 will be placed in the .got section by the linker script. */
9f19ab6d
WN		 8217 if (is_iplt_entry)
8218 arm_plt->got_offset = sgotplt->size;
8219 else
8220 arm_plt->got_offset = sgotplt->size - 8 * htab->num_tls_desc;
34e77a92
RS		 8221 sgotplt->size += 4;
8222 }
8223}
8224
b38cadfb
NC		 8225static bfd_vma
8226arm_movw_immediate (bfd_vma value)
8227{
8228 return (value & 0x00000fff) | ((value & 0x0000f000) << 4);
8229}
8230
8231static bfd_vma
8232arm_movt_immediate (bfd_vma value)
8233{
8234 return ((value & 0x0fff0000) >> 16) | ((value & 0xf0000000) >> 12);
8235}
8236
34e77a92
RS		 8237/* Fill in a PLT entry and its associated GOT slot. If DYNINDX == -1,
8238 the entry lives in .iplt and resolves to (*SYM_VALUE)().
8239 Otherwise, DYNINDX is the index of the symbol in the dynamic
8240 symbol table and SYM_VALUE is undefined.
8241
8242 ROOT_PLT points to the offset of the PLT entry from the start of its
8243 section (.iplt or .plt). ARM_PLT points to the symbol's ARM-specific
57460bcf 8244 bookkeeping information.
34e77a92 8245
57460bcf
NC		 8246 Returns FALSE if there was a problem. */
8247
8248static bfd_boolean
34e77a92
RS		 8249elf32_arm_populate_plt_entry (bfd *output_bfd, struct bfd_link_info *info,
8250 union gotplt_union *root_plt,
8251 struct arm_plt_info *arm_plt,
8252 int dynindx, bfd_vma sym_value)
8253{
8254 struct elf32_arm_link_hash_table *htab;
8255 asection *sgot;
8256 asection *splt;
8257 asection *srel;
8258 bfd_byte *loc;
8259 bfd_vma plt_index;
8260 Elf_Internal_Rela rel;
8261 bfd_vma plt_header_size;
8262 bfd_vma got_header_size;
8263
8264 htab = elf32_arm_hash_table (info);
8265
8266 /* Pick the appropriate sections and sizes. */
8267 if (dynindx == -1)
8268 {
8269 splt = htab->root.iplt;
8270 sgot = htab->root.igotplt;
8271 srel = htab->root.irelplt;
8272
8273 /* There are no reserved entries in .igot.plt, and no special
8274 first entry in .iplt. */
8275 got_header_size = 0;
8276 plt_header_size = 0;
8277 }
8278 else
8279 {
8280 splt = htab->root.splt;
8281 sgot = htab->root.sgotplt;
8282 srel = htab->root.srelplt;
8283
8284 got_header_size = get_elf_backend_data (output_bfd)->got_header_size;
8285 plt_header_size = htab->plt_header_size;
8286 }
8287 BFD_ASSERT (splt != NULL && srel != NULL);
8288
8289 /* Fill in the entry in the procedure linkage table. */
8290 if (htab->symbian_p)
8291 {
8292 BFD_ASSERT (dynindx >= 0);
8293 put_arm_insn (htab, output_bfd,
8294 elf32_arm_symbian_plt_entry[0],
8295 splt->contents + root_plt->offset);
8296 bfd_put_32 (output_bfd,
8297 elf32_arm_symbian_plt_entry[1],
8298 splt->contents + root_plt->offset + 4);
8299
8300 /* Fill in the entry in the .rel.plt section. */
8301 rel.r_offset = (splt->output_section->vma
8302 + splt->output_offset
8303 + root_plt->offset + 4);
8304 rel.r_info = ELF32_R_INFO (dynindx, R_ARM_GLOB_DAT);
8305
8306 /* Get the index in the procedure linkage table which
8307 corresponds to this symbol. This is the index of this symbol
8308 in all the symbols for which we are making plt entries. The
8309 first entry in the procedure linkage table is reserved. */
8310 plt_index = ((root_plt->offset - plt_header_size)
8311 / htab->plt_entry_size);
8312 }
8313 else
8314 {
8315 bfd_vma got_offset, got_address, plt_address;
8316 bfd_vma got_displacement, initial_got_entry;
8317 bfd_byte * ptr;
8318
8319 BFD_ASSERT (sgot != NULL);
8320
8321 /* Get the offset into the .(i)got.plt table of the entry that
8322 corresponds to this function. */
8323 got_offset = (arm_plt->got_offset & -2);
8324
8325 /* Get the index in the procedure linkage table which
8326 corresponds to this symbol. This is the index of this symbol
8327 in all the symbols for which we are making plt entries.
8328 After the reserved .got.plt entries, all symbols appear in
8329 the same order as in .plt. */
8330 plt_index = (got_offset - got_header_size) / 4;
8331
8332 /* Calculate the address of the GOT entry. */
8333 got_address = (sgot->output_section->vma
8334 + sgot->output_offset
8335 + got_offset);
8336
8337 /* ...and the address of the PLT entry. */
8338 plt_address = (splt->output_section->vma
8339 + splt->output_offset
8340 + root_plt->offset);
8341
8342 ptr = splt->contents + root_plt->offset;
0e1862bb 8343 if (htab->vxworks_p && bfd_link_pic (info))
34e77a92
RS		 8344 {
8345 unsigned int i;
8346 bfd_vma val;
8347
8348 for (i = 0; i != htab->plt_entry_size / 4; i++, ptr += 4)
8349 {
8350 val = elf32_arm_vxworks_shared_plt_entry[i];
8351 if (i == 2)
8352 val |= got_address - sgot->output_section->vma;
8353 if (i == 5)
8354 val |= plt_index * RELOC_SIZE (htab);
8355 if (i == 2 || i == 5)
8356 bfd_put_32 (output_bfd, val, ptr);
8357 else
8358 put_arm_insn (htab, output_bfd, val, ptr);
8359 }
8360 }
8361 else if (htab->vxworks_p)
8362 {
8363 unsigned int i;
8364 bfd_vma val;
8365
8366 for (i = 0; i != htab->plt_entry_size / 4; i++, ptr += 4)
8367 {
8368 val = elf32_arm_vxworks_exec_plt_entry[i];
8369 if (i == 2)
8370 val |= got_address;
8371 if (i == 4)
8372 val |= 0xffffff & -((root_plt->offset + i * 4 + 8) >> 2);
8373 if (i == 5)
8374 val |= plt_index * RELOC_SIZE (htab);
8375 if (i == 2 || i == 5)
8376 bfd_put_32 (output_bfd, val, ptr);
8377 else
8378 put_arm_insn (htab, output_bfd, val, ptr);
8379 }
8380
8381 loc = (htab->srelplt2->contents
8382 + (plt_index * 2 + 1) * RELOC_SIZE (htab));
8383
8384 /* Create the .rela.plt.unloaded R_ARM_ABS32 relocation
8385 referencing the GOT for this PLT entry. */
8386 rel.r_offset = plt_address + 8;
8387 rel.r_info = ELF32_R_INFO (htab->root.hgot->indx, R_ARM_ABS32);
8388 rel.r_addend = got_offset;
8389 SWAP_RELOC_OUT (htab) (output_bfd, &rel, loc);
8390 loc += RELOC_SIZE (htab);
8391
8392 /* Create the R_ARM_ABS32 relocation referencing the
8393 beginning of the PLT for this GOT entry. */
8394 rel.r_offset = got_address;
8395 rel.r_info = ELF32_R_INFO (htab->root.hplt->indx, R_ARM_ABS32);
8396 rel.r_addend = 0;
8397 SWAP_RELOC_OUT (htab) (output_bfd, &rel, loc);
8398 }
b38cadfb
NC		 8399 else if (htab->nacl_p)
8400 {
8401 /* Calculate the displacement between the PLT slot and the
8402 common tail that's part of the special initial PLT slot. */
6034aab8 8403 int32_t tail_displacement
b38cadfb
NC		 8404 = ((splt->output_section->vma + splt->output_offset
8405 + ARM_NACL_PLT_TAIL_OFFSET)
8406 - (plt_address + htab->plt_entry_size + 4));
8407 BFD_ASSERT ((tail_displacement & 3) == 0);
8408 tail_displacement >>= 2;
8409
8410 BFD_ASSERT ((tail_displacement & 0xff000000) == 0
8411 || (-tail_displacement & 0xff000000) == 0);
8412
8413 /* Calculate the displacement between the PLT slot and the entry
8414 in the GOT. The offset accounts for the value produced by
8415 adding to pc in the penultimate instruction of the PLT stub. */
6034aab8 8416 got_displacement = (got_address
99059e56 8417 - (plt_address + htab->plt_entry_size));
b38cadfb
NC		 8418
8419 /* NaCl does not support interworking at all. */
8420 BFD_ASSERT (!elf32_arm_plt_needs_thumb_stub_p (info, arm_plt));
8421
8422 put_arm_insn (htab, output_bfd,
8423 elf32_arm_nacl_plt_entry[0]
8424 | arm_movw_immediate (got_displacement),
8425 ptr + 0);
8426 put_arm_insn (htab, output_bfd,
8427 elf32_arm_nacl_plt_entry[1]
8428 | arm_movt_immediate (got_displacement),
8429 ptr + 4);
8430 put_arm_insn (htab, output_bfd,
8431 elf32_arm_nacl_plt_entry[2],
8432 ptr + 8);
8433 put_arm_insn (htab, output_bfd,
8434 elf32_arm_nacl_plt_entry[3]
8435 | (tail_displacement & 0x00ffffff),
8436 ptr + 12);
8437 }
57460bcf
NC		 8438 else if (using_thumb_only (htab))
8439 {
eed94f8f 8440 /* PR ld/16017: Generate thumb only PLT entries. */
469a3493 8441 if (!using_thumb2 (htab))
eed94f8f
NC		 8442 {
8443 /* FIXME: We ought to be able to generate thumb-1 PLT
8444 instructions... */
8445 _bfd_error_handler (_("%B: Warning: thumb-1 mode PLT generation not currently supported"),
8446 output_bfd);
8447 return FALSE;
8448 }
57460bcf 8449
eed94f8f
NC		 8450 /* Calculate the displacement between the PLT slot and the entry in
8451 the GOT. The 12-byte offset accounts for the value produced by
8452 adding to pc in the 3rd instruction of the PLT stub. */
8453 got_displacement = got_address - (plt_address + 12);
8454
8455 /* As we are using 32 bit instructions we have to use 'put_arm_insn'
8456 instead of 'put_thumb_insn'. */
8457 put_arm_insn (htab, output_bfd,
8458 elf32_thumb2_plt_entry[0]
8459 | ((got_displacement & 0x000000ff) << 16)
8460 | ((got_displacement & 0x00000700) << 20)
8461 | ((got_displacement & 0x00000800) >> 1)
8462 | ((got_displacement & 0x0000f000) >> 12),
8463 ptr + 0);
8464 put_arm_insn (htab, output_bfd,
8465 elf32_thumb2_plt_entry[1]
8466 | ((got_displacement & 0x00ff0000) )
8467 | ((got_displacement & 0x07000000) << 4)
8468 | ((got_displacement & 0x08000000) >> 17)
8469 | ((got_displacement & 0xf0000000) >> 28),
8470 ptr + 4);
8471 put_arm_insn (htab, output_bfd,
8472 elf32_thumb2_plt_entry[2],
8473 ptr + 8);
8474 put_arm_insn (htab, output_bfd,
8475 elf32_thumb2_plt_entry[3],
8476 ptr + 12);
57460bcf 8477 }
34e77a92
RS		 8478 else
8479 {
8480 /* Calculate the displacement between the PLT slot and the
8481 entry in the GOT. The eight-byte offset accounts for the
8482 value produced by adding to pc in the first instruction
8483 of the PLT stub. */
8484 got_displacement = got_address - (plt_address + 8);
8485
34e77a92
RS		 8486 if (elf32_arm_plt_needs_thumb_stub_p (info, arm_plt))
8487 {
8488 put_thumb_insn (htab, output_bfd,
8489 elf32_arm_plt_thumb_stub[0], ptr - 4);
8490 put_thumb_insn (htab, output_bfd,
8491 elf32_arm_plt_thumb_stub[1], ptr - 2);
8492 }
8493
1db37fe6
YG		 8494 if (!elf32_arm_use_long_plt_entry)
8495 {
8496 BFD_ASSERT ((got_displacement & 0xf0000000) == 0);
8497
8498 put_arm_insn (htab, output_bfd,
8499 elf32_arm_plt_entry_short[0]
8500 | ((got_displacement & 0x0ff00000) >> 20),
8501 ptr + 0);
8502 put_arm_insn (htab, output_bfd,
8503 elf32_arm_plt_entry_short[1]
8504 | ((got_displacement & 0x000ff000) >> 12),
8505 ptr+ 4);
8506 put_arm_insn (htab, output_bfd,
8507 elf32_arm_plt_entry_short[2]
8508 | (got_displacement & 0x00000fff),
8509 ptr + 8);
34e77a92 8510#ifdef FOUR_WORD_PLT
1db37fe6 8511 bfd_put_32 (output_bfd, elf32_arm_plt_entry_short[3], ptr + 12);
34e77a92 8512#endif
1db37fe6
YG		 8513 }
8514 else
8515 {
8516 put_arm_insn (htab, output_bfd,
8517 elf32_arm_plt_entry_long[0]
8518 | ((got_displacement & 0xf0000000) >> 28),
8519 ptr + 0);
8520 put_arm_insn (htab, output_bfd,
8521 elf32_arm_plt_entry_long[1]
8522 | ((got_displacement & 0x0ff00000) >> 20),
8523 ptr + 4);
8524 put_arm_insn (htab, output_bfd,
8525 elf32_arm_plt_entry_long[2]
8526 | ((got_displacement & 0x000ff000) >> 12),
8527 ptr+ 8);
8528 put_arm_insn (htab, output_bfd,
8529 elf32_arm_plt_entry_long[3]
8530 | (got_displacement & 0x00000fff),
8531 ptr + 12);
8532 }
34e77a92
RS		 8533 }
8534
8535 /* Fill in the entry in the .rel(a).(i)plt section. */
8536 rel.r_offset = got_address;
8537 rel.r_addend = 0;
8538 if (dynindx == -1)
8539 {
8540 /* .igot.plt entries use IRELATIVE relocations against SYM_VALUE.
8541 The dynamic linker or static executable then calls SYM_VALUE
8542 to determine the correct run-time value of the .igot.plt entry. */
8543 rel.r_info = ELF32_R_INFO (0, R_ARM_IRELATIVE);
8544 initial_got_entry = sym_value;
8545 }
8546 else
8547 {
8548 rel.r_info = ELF32_R_INFO (dynindx, R_ARM_JUMP_SLOT);
8549 initial_got_entry = (splt->output_section->vma
8550 + splt->output_offset);
8551 }
8552
8553 /* Fill in the entry in the global offset table. */
8554 bfd_put_32 (output_bfd, initial_got_entry,
8555 sgot->contents + got_offset);
8556 }
8557
aba8c3de
WN		 8558 if (dynindx == -1)
8559 elf32_arm_add_dynreloc (output_bfd, info, srel, &rel);
8560 else
8561 {
8562 loc = srel->contents + plt_index * RELOC_SIZE (htab);
8563 SWAP_RELOC_OUT (htab) (output_bfd, &rel, loc);
8564 }
57460bcf
NC		 8565
8566 return TRUE;
34e77a92
RS		 8567}
8568
eb043451
PB		 8569/* Some relocations map to different relocations depending on the
8570 target. Return the real relocation. */
8029a119 8571
eb043451
PB		 8572static int
8573arm_real_reloc_type (struct elf32_arm_link_hash_table * globals,
8574 int r_type)
8575{
8576 switch (r_type)
8577 {
8578 case R_ARM_TARGET1:
8579 if (globals->target1_is_rel)
8580 return R_ARM_REL32;
8581 else
8582 return R_ARM_ABS32;
8583
8584 case R_ARM_TARGET2:
8585 return globals->target2_reloc;
8586
8587 default:
8588 return r_type;
8589 }
8590}
eb043451 8591
ba93b8ac
DJ		 8592/* Return the base VMA address which should be subtracted from real addresses
8593 when resolving @dtpoff relocation.
8594 This is PT_TLS segment p_vaddr. */
8595
8596static bfd_vma
8597dtpoff_base (struct bfd_link_info *info)
8598{
8599 /* If tls_sec is NULL, we should have signalled an error already. */
8600 if (elf_hash_table (info)->tls_sec == NULL)
8601 return 0;
8602 return elf_hash_table (info)->tls_sec->vma;
8603}
8604
8605/* Return the relocation value for @tpoff relocation
8606 if STT_TLS virtual address is ADDRESS. */
8607
8608static bfd_vma
8609tpoff (struct bfd_link_info *info, bfd_vma address)
8610{
8611 struct elf_link_hash_table *htab = elf_hash_table (info);
8612 bfd_vma base;
8613
8614 /* If tls_sec is NULL, we should have signalled an error already. */
8615 if (htab->tls_sec == NULL)
8616 return 0;
8617 base = align_power ((bfd_vma) TCB_SIZE, htab->tls_sec->alignment_power);
8618 return address - htab->tls_sec->vma + base;
8619}
8620
00a97672
RS		 8621/* Perform an R_ARM_ABS12 relocation on the field pointed to by DATA.
8622 VALUE is the relocation value. */
8623
8624static bfd_reloc_status_type
8625elf32_arm_abs12_reloc (bfd *abfd, void *data, bfd_vma value)
8626{
8627 if (value > 0xfff)
8628 return bfd_reloc_overflow;
8629
8630 value |= bfd_get_32 (abfd, data) & 0xfffff000;
8631 bfd_put_32 (abfd, value, data);
8632 return bfd_reloc_ok;
8633}
8634
0855e32b
NS		 8635/* Handle TLS relaxations. Relaxing is possible for symbols that use
8636 R_ARM_GOTDESC, R_ARM_{,THM_}TLS_CALL or
8637 R_ARM_{,THM_}TLS_DESCSEQ relocations, during a static link.
8638
8639 Return bfd_reloc_ok if we're done, bfd_reloc_continue if the caller
8640 is to then call final_link_relocate. Return other values in the
62672b10
NS		 8641 case of error.
8642
8643 FIXME:When --emit-relocs is in effect, we'll emit relocs describing
8644 the pre-relaxed code. It would be nice if the relocs were updated
8645 to match the optimization. */
0855e32b 8646
b38cadfb 8647static bfd_reloc_status_type
0855e32b 8648elf32_arm_tls_relax (struct elf32_arm_link_hash_table *globals,
b38cadfb 8649 bfd *input_bfd, asection *input_sec, bfd_byte *contents,
0855e32b
NS		 8650 Elf_Internal_Rela *rel, unsigned long is_local)
8651{
8652 unsigned long insn;
b38cadfb 8653
0855e32b
NS		 8654 switch (ELF32_R_TYPE (rel->r_info))
8655 {
8656 default:
8657 return bfd_reloc_notsupported;
b38cadfb 8658
0855e32b
NS		 8659 case R_ARM_TLS_GOTDESC:
8660 if (is_local)
8661 insn = 0;
8662 else
8663 {
8664 insn = bfd_get_32 (input_bfd, contents + rel->r_offset);
8665 if (insn & 1)
8666 insn -= 5; /* THUMB */
8667 else
8668 insn -= 8; /* ARM */
8669 }
8670 bfd_put_32 (input_bfd, insn, contents + rel->r_offset);
8671 return bfd_reloc_continue;
8672
8673 case R_ARM_THM_TLS_DESCSEQ:
8674 /* Thumb insn. */
8675 insn = bfd_get_16 (input_bfd, contents + rel->r_offset);
8676 if ((insn & 0xff78) == 0x4478) /* add rx, pc */
8677 {
8678 if (is_local)
8679 /* nop */
8680 bfd_put_16 (input_bfd, 0x46c0, contents + rel->r_offset);
8681 }
8682 else if ((insn & 0xffc0) == 0x6840) /* ldr rx,[ry,#4] */
8683 {
8684 if (is_local)
8685 /* nop */
8686 bfd_put_16 (input_bfd, 0x46c0, contents + rel->r_offset);
8687 else
8688 /* ldr rx,[ry] */
8689 bfd_put_16 (input_bfd, insn & 0xf83f, contents + rel->r_offset);
8690 }
8691 else if ((insn & 0xff87) == 0x4780) /* blx rx */
8692 {
8693 if (is_local)
8694 /* nop */
8695 bfd_put_16 (input_bfd, 0x46c0, contents + rel->r_offset);
8696 else
8697 /* mov r0, rx */
8698 bfd_put_16 (input_bfd, 0x4600 | (insn & 0x78),
8699 contents + rel->r_offset);
8700 }
8701 else
8702 {
8703 if ((insn & 0xf000) == 0xf000 || (insn & 0xf800) == 0xe800)
8704 /* It's a 32 bit instruction, fetch the rest of it for
8705 error generation. */
8706 insn = (insn << 16)
8707 | bfd_get_16 (input_bfd, contents + rel->r_offset + 2);
8708 (*_bfd_error_handler)
8709 (_("%B(%A+0x%lx):unexpected Thumb instruction '0x%x' in TLS trampoline"),
8710 input_bfd, input_sec, (unsigned long)rel->r_offset, insn);
8711 return bfd_reloc_notsupported;
8712 }
8713 break;
b38cadfb 8714
0855e32b
NS		 8715 case R_ARM_TLS_DESCSEQ:
8716 /* arm insn. */
8717 insn = bfd_get_32 (input_bfd, contents + rel->r_offset);
8718 if ((insn & 0xffff0ff0) == 0xe08f0000) /* add rx,pc,ry */
8719 {
8720 if (is_local)
8721 /* mov rx, ry */
8722 bfd_put_32 (input_bfd, 0xe1a00000 | (insn & 0xffff),
8723 contents + rel->r_offset);
8724 }
8725 else if ((insn & 0xfff00fff) == 0xe5900004) /* ldr rx,[ry,#4]*/
8726 {
8727 if (is_local)
8728 /* nop */
8729 bfd_put_32 (input_bfd, 0xe1a00000, contents + rel->r_offset);
8730 else
8731 /* ldr rx,[ry] */
8732 bfd_put_32 (input_bfd, insn & 0xfffff000,
8733 contents + rel->r_offset);
8734 }
8735 else if ((insn & 0xfffffff0) == 0xe12fff30) /* blx rx */
8736 {
8737 if (is_local)
8738 /* nop */
8739 bfd_put_32 (input_bfd, 0xe1a00000, contents + rel->r_offset);
8740 else
8741 /* mov r0, rx */
8742 bfd_put_32 (input_bfd, 0xe1a00000 | (insn & 0xf),
8743 contents + rel->r_offset);
8744 }
8745 else
8746 {
8747 (*_bfd_error_handler)
8748 (_("%B(%A+0x%lx):unexpected ARM instruction '0x%x' in TLS trampoline"),
8749 input_bfd, input_sec, (unsigned long)rel->r_offset, insn);
8750 return bfd_reloc_notsupported;
8751 }
8752 break;
8753
8754 case R_ARM_TLS_CALL:
8755 /* GD->IE relaxation, turn the instruction into 'nop' or
8756 'ldr r0, [pc,r0]' */
8757 insn = is_local ? 0xe1a00000 : 0xe79f0000;
8758 bfd_put_32 (input_bfd, insn, contents + rel->r_offset);
8759 break;
b38cadfb 8760
0855e32b 8761 case R_ARM_THM_TLS_CALL:
6a631e86 8762 /* GD->IE relaxation. */
0855e32b
NS		 8763 if (!is_local)
8764 /* add r0,pc; ldr r0, [r0] */
8765 insn = 0x44786800;
8766 else if (arch_has_thumb2_nop (globals))
8767 /* nop.w */
8768 insn = 0xf3af8000;
8769 else
8770 /* nop; nop */
8771 insn = 0xbf00bf00;
b38cadfb 8772
0855e32b
NS		 8773 bfd_put_16 (input_bfd, insn >> 16, contents + rel->r_offset);
8774 bfd_put_16 (input_bfd, insn & 0xffff, contents + rel->r_offset + 2);
8775 break;
8776 }
8777 return bfd_reloc_ok;
8778}
8779
4962c51a
MS		 8780/* For a given value of n, calculate the value of G_n as required to
8781 deal with group relocations. We return it in the form of an
8782 encoded constant-and-rotation, together with the final residual. If n is
8783 specified as less than zero, then final_residual is filled with the
8784 input value and no further action is performed. */
8785
8786static bfd_vma
8787calculate_group_reloc_mask (bfd_vma value, int n, bfd_vma *final_residual)
8788{
8789 int current_n;
8790 bfd_vma g_n;
8791 bfd_vma encoded_g_n = 0;
8792 bfd_vma residual = value; /* Also known as Y_n. */
8793
8794 for (current_n = 0; current_n <= n; current_n++)
8795 {
8796 int shift;
8797
8798 /* Calculate which part of the value to mask. */
8799 if (residual == 0)
99059e56 8800 shift = 0;
4962c51a 8801 else
99059e56
RM		 8802 {
8803 int msb;
8804
8805 /* Determine the most significant bit in the residual and
8806 align the resulting value to a 2-bit boundary. */
8807 for (msb = 30; msb >= 0; msb -= 2)
8808 if (residual & (3 << msb))
8809 break;
8810
8811 /* The desired shift is now (msb - 6), or zero, whichever
8812 is the greater. */
8813 shift = msb - 6;
8814 if (shift < 0)
8815 shift = 0;
8816 }
4962c51a
MS		 8817
8818 /* Calculate g_n in 32-bit as well as encoded constant+rotation form. */
8819 g_n = residual & (0xff << shift);
8820 encoded_g_n = (g_n >> shift)
99059e56 8821 | ((g_n <= 0xff ? 0 : (32 - shift) / 2) << 8);
4962c51a
MS		 8822
8823 /* Calculate the residual for the next time around. */
8824 residual &= ~g_n;
8825 }
8826
8827 *final_residual = residual;
8828
8829 return encoded_g_n;
8830}
8831
8832/* Given an ARM instruction, determine whether it is an ADD or a SUB.
8833 Returns 1 if it is an ADD, -1 if it is a SUB, and 0 otherwise. */
906e58ca 8834
4962c51a 8835static int
906e58ca 8836identify_add_or_sub (bfd_vma insn)
4962c51a
MS		 8837{
8838 int opcode = insn & 0x1e00000;
8839
8840 if (opcode == 1 << 23) /* ADD */
8841 return 1;
8842
8843 if (opcode == 1 << 22) /* SUB */
8844 return -1;
8845
8846 return 0;
8847}
8848
252b5132 8849/* Perform a relocation as part of a final link. */
9b485d32 8850
252b5132 8851static bfd_reloc_status_type
57e8b36a
NC		 8852elf32_arm_final_link_relocate (reloc_howto_type * howto,
8853 bfd * input_bfd,
8854 bfd * output_bfd,
8855 asection * input_section,
8856 bfd_byte * contents,
8857 Elf_Internal_Rela * rel,
8858 bfd_vma value,
8859 struct bfd_link_info * info,
8860 asection * sym_sec,
8861 const char * sym_name,
34e77a92
RS		 8862 unsigned char st_type,
8863 enum arm_st_branch_type branch_type,
0945cdfd 8864 struct elf_link_hash_entry * h,
f2a9dd69 8865 bfd_boolean * unresolved_reloc_p,
8029a119 8866 char ** error_message)
252b5132
RH		 8867{
8868 unsigned long r_type = howto->type;
8869 unsigned long r_symndx;
8870 bfd_byte * hit_data = contents + rel->r_offset;
252b5132 8871 bfd_vma * local_got_offsets;
0855e32b 8872 bfd_vma * local_tlsdesc_gotents;
34e77a92
RS		 8873 asection * sgot;
8874 asection * splt;
252b5132 8875 asection * sreloc = NULL;
362d30a1 8876 asection * srelgot;
252b5132 8877 bfd_vma addend;
ba96a88f 8878 bfd_signed_vma signed_addend;
34e77a92
RS		 8879 unsigned char dynreloc_st_type;
8880 bfd_vma dynreloc_value;
ba96a88f 8881 struct elf32_arm_link_hash_table * globals;
34e77a92
RS		 8882 struct elf32_arm_link_hash_entry *eh;
8883 union gotplt_union *root_plt;
8884 struct arm_plt_info *arm_plt;
8885 bfd_vma plt_offset;
8886 bfd_vma gotplt_offset;
8887 bfd_boolean has_iplt_entry;
f21f3fe0 8888
9c504268 8889 globals = elf32_arm_hash_table (info);
4dfe6ac6
NC		 8890 if (globals == NULL)
8891 return bfd_reloc_notsupported;
9c504268 8892
0ffa91dd
NC		 8893 BFD_ASSERT (is_arm_elf (input_bfd));
8894
8895 /* Some relocation types map to different relocations depending on the
9c504268 8896 target. We pick the right one here. */
eb043451 8897 r_type = arm_real_reloc_type (globals, r_type);
0855e32b
NS		 8898
8899 /* It is possible to have linker relaxations on some TLS access
8900 models. Update our information here. */
8901 r_type = elf32_arm_tls_transition (info, r_type, h);
8902
eb043451
PB		 8903 if (r_type != howto->type)
8904 howto = elf32_arm_howto_from_type (r_type);
9c504268 8905
34e77a92 8906 eh = (struct elf32_arm_link_hash_entry *) h;
362d30a1 8907 sgot = globals->root.sgot;
252b5132 8908 local_got_offsets = elf_local_got_offsets (input_bfd);
0855e32b
NS		 8909 local_tlsdesc_gotents = elf32_arm_local_tlsdesc_gotent (input_bfd);
8910
34e77a92
RS		 8911 if (globals->root.dynamic_sections_created)
8912 srelgot = globals->root.srelgot;
8913 else
8914 srelgot = NULL;
8915
252b5132
RH		 8916 r_symndx = ELF32_R_SYM (rel->r_info);
8917
4e7fd91e 8918 if (globals->use_rel)
ba96a88f 8919 {
4e7fd91e
PB		 8920 addend = bfd_get_32 (input_bfd, hit_data) & howto->src_mask;
8921
8922 if (addend & ((howto->src_mask + 1) >> 1))
8923 {
8924 signed_addend = -1;
8925 signed_addend &= ~ howto->src_mask;
8926 signed_addend |= addend;
8927 }
8928 else
8929 signed_addend = addend;
ba96a88f
NC		 8930 }
8931 else
4e7fd91e 8932 addend = signed_addend = rel->r_addend;
f21f3fe0 8933
39f21624
NC		 8934 /* ST_BRANCH_TO_ARM is nonsense to thumb-only targets when we
8935 are resolving a function call relocation. */
8936 if (using_thumb_only (globals)
8937 && (r_type == R_ARM_THM_CALL
8938 || r_type == R_ARM_THM_JUMP24)
8939 && branch_type == ST_BRANCH_TO_ARM)
8940 branch_type = ST_BRANCH_TO_THUMB;
8941
34e77a92
RS		 8942 /* Record the symbol information that should be used in dynamic
8943 relocations. */
8944 dynreloc_st_type = st_type;
8945 dynreloc_value = value;
8946 if (branch_type == ST_BRANCH_TO_THUMB)
8947 dynreloc_value |= 1;
8948
8949 /* Find out whether the symbol has a PLT. Set ST_VALUE, BRANCH_TYPE and
8950 VALUE appropriately for relocations that we resolve at link time. */
8951 has_iplt_entry = FALSE;
8952 if (elf32_arm_get_plt_info (input_bfd, eh, r_symndx, &root_plt, &arm_plt)
8953 && root_plt->offset != (bfd_vma) -1)
8954 {
8955 plt_offset = root_plt->offset;
8956 gotplt_offset = arm_plt->got_offset;
8957
8958 if (h == NULL || eh->is_iplt)
8959 {
8960 has_iplt_entry = TRUE;
8961 splt = globals->root.iplt;
8962
8963 /* Populate .iplt entries here, because not all of them will
8964 be seen by finish_dynamic_symbol. The lower bit is set if
8965 we have already populated the entry. */
8966 if (plt_offset & 1)
8967 plt_offset--;
8968 else
8969 {
57460bcf
NC		 8970 if (elf32_arm_populate_plt_entry (output_bfd, info, root_plt, arm_plt,
8971 -1, dynreloc_value))
8972 root_plt->offset |= 1;
8973 else
8974 return bfd_reloc_notsupported;
34e77a92
RS		 8975 }
8976
8977 /* Static relocations always resolve to the .iplt entry. */
8978 st_type = STT_FUNC;
8979 value = (splt->output_section->vma
8980 + splt->output_offset
8981 + plt_offset);
8982 branch_type = ST_BRANCH_TO_ARM;
8983
8984 /* If there are non-call relocations that resolve to the .iplt
8985 entry, then all dynamic ones must too. */
8986 if (arm_plt->noncall_refcount != 0)
8987 {
8988 dynreloc_st_type = st_type;
8989 dynreloc_value = value;
8990 }
8991 }
8992 else
8993 /* We populate the .plt entry in finish_dynamic_symbol. */
8994 splt = globals->root.splt;
8995 }
8996 else
8997 {
8998 splt = NULL;
8999 plt_offset = (bfd_vma) -1;
9000 gotplt_offset = (bfd_vma) -1;
9001 }
9002
252b5132
RH		 9003 switch (r_type)
9004 {
9005 case R_ARM_NONE:
28a094c2
DJ		 9006 /* We don't need to find a value for this symbol. It's just a
9007 marker. */
9008 *unresolved_reloc_p = FALSE;
252b5132
RH		 9009 return bfd_reloc_ok;
9010
00a97672
RS		 9011 case R_ARM_ABS12:
9012 if (!globals->vxworks_p)
9013 return elf32_arm_abs12_reloc (input_bfd, hit_data, value + addend);
9014
252b5132
RH		 9015 case R_ARM_PC24:
9016 case R_ARM_ABS32:
bb224fc3 9017 case R_ARM_ABS32_NOI:
252b5132 9018 case R_ARM_REL32:
bb224fc3 9019 case R_ARM_REL32_NOI:
5b5bb741
PB		 9020 case R_ARM_CALL:
9021 case R_ARM_JUMP24:
dfc5f959 9022 case R_ARM_XPC25:
eb043451 9023 case R_ARM_PREL31:
7359ea65 9024 case R_ARM_PLT32:
7359ea65
DJ		 9025 /* Handle relocations which should use the PLT entry. ABS32/REL32
9026 will use the symbol's value, which may point to a PLT entry, but we
9027 don't need to handle that here. If we created a PLT entry, all
5fa9e92f
CL		 9028 branches in this object should go to it, except if the PLT is too
9029 far away, in which case a long branch stub should be inserted. */
bb224fc3 9030 if ((r_type != R_ARM_ABS32 && r_type != R_ARM_REL32
99059e56 9031 && r_type != R_ARM_ABS32_NOI && r_type != R_ARM_REL32_NOI
155d87d7
CL		 9032 && r_type != R_ARM_CALL
9033 && r_type != R_ARM_JUMP24
9034 && r_type != R_ARM_PLT32)
34e77a92 9035 && plt_offset != (bfd_vma) -1)
7359ea65 9036 {
34e77a92
RS		 9037 /* If we've created a .plt section, and assigned a PLT entry
9038 to this function, it must either be a STT_GNU_IFUNC reference
9039 or not be known to bind locally. In other cases, we should
9040 have cleared the PLT entry by now. */
9041 BFD_ASSERT (has_iplt_entry || !SYMBOL_CALLS_LOCAL (info, h));
7359ea65
DJ		 9042
9043 value = (splt->output_section->vma
9044 + splt->output_offset
34e77a92 9045 + plt_offset);
0945cdfd 9046 *unresolved_reloc_p = FALSE;
7359ea65
DJ		 9047 return _bfd_final_link_relocate (howto, input_bfd, input_section,
9048 contents, rel->r_offset, value,
00a97672 9049 rel->r_addend);
7359ea65
DJ		 9050 }
9051
67687978
PB		 9052 /* When generating a shared object or relocatable executable, these
9053 relocations are copied into the output file to be resolved at
9054 run time. */
0e1862bb
L		 9055 if ((bfd_link_pic (info)
9056 || globals->root.is_relocatable_executable)
7359ea65 9057 && (input_section->flags & SEC_ALLOC)
4dfe6ac6 9058 && !(globals->vxworks_p
3348747a
NS		 9059 && strcmp (input_section->output_section->name,
9060 ".tls_vars") == 0)
bb224fc3 9061 && ((r_type != R_ARM_REL32 && r_type != R_ARM_REL32_NOI)
ee06dc07 9062 || !SYMBOL_CALLS_LOCAL (info, h))
ca6b5f82
AM		 9063 && !(input_bfd == globals->stub_bfd
9064 && strstr (input_section->name, STUB_SUFFIX))
7359ea65
DJ		 9065 && (h == NULL
9066 || ELF_ST_VISIBILITY (h->other) == STV_DEFAULT
9067 || h->root.type != bfd_link_hash_undefweak)
9068 && r_type != R_ARM_PC24
5b5bb741
PB		 9069 && r_type != R_ARM_CALL
9070 && r_type != R_ARM_JUMP24
ee06dc07 9071 && r_type != R_ARM_PREL31
7359ea65 9072 && r_type != R_ARM_PLT32)
252b5132 9073 {
947216bf 9074 Elf_Internal_Rela outrel;
b34976b6 9075 bfd_boolean skip, relocate;
f21f3fe0 9076
52db4ec2
JW		 9077 if ((r_type == R_ARM_REL32 || r_type == R_ARM_REL32_NOI)
9078 && !h->def_regular)
9079 {
9080 char *v = _("shared object");
9081
0e1862bb 9082 if (bfd_link_executable (info))
52db4ec2
JW		 9083 v = _("PIE executable");
9084
9085 (*_bfd_error_handler)
9086 (_("%B: relocation %s against external or undefined symbol `%s'"
9087 " can not be used when making a %s; recompile with -fPIC"), input_bfd,
9088 elf32_arm_howto_table_1[r_type].name, h->root.root.string, v);
9089 return bfd_reloc_notsupported;
9090 }
9091
0945cdfd
DJ		 9092 *unresolved_reloc_p = FALSE;
9093
34e77a92 9094 if (sreloc == NULL && globals->root.dynamic_sections_created)
252b5132 9095 {
83bac4b0
NC		 9096 sreloc = _bfd_elf_get_dynamic_reloc_section (input_bfd, input_section,
9097 ! globals->use_rel);
f21f3fe0 9098
83bac4b0 9099 if (sreloc == NULL)
252b5132 9100 return bfd_reloc_notsupported;
252b5132 9101 }
f21f3fe0 9102
b34976b6
AM		 9103 skip = FALSE;
9104 relocate = FALSE;
f21f3fe0 9105
00a97672 9106 outrel.r_addend = addend;
c629eae0
JJ		 9107 outrel.r_offset =
9108 _bfd_elf_section_offset (output_bfd, info, input_section,
9109 rel->r_offset);
9110 if (outrel.r_offset == (bfd_vma) -1)
b34976b6 9111 skip = TRUE;
0bb2d96a 9112 else if (outrel.r_offset == (bfd_vma) -2)
b34976b6 9113 skip = TRUE, relocate = TRUE;
252b5132
RH		 9114 outrel.r_offset += (input_section->output_section->vma
9115 + input_section->output_offset);
f21f3fe0 9116
252b5132 9117 if (skip)
0bb2d96a 9118 memset (&outrel, 0, sizeof outrel);
5e681ec4
PB		 9119 else if (h != NULL
9120 && h->dynindx != -1
0e1862bb 9121 && (!bfd_link_pic (info)
a496fbc8 9122 || !SYMBOLIC_BIND (info, h)
f5385ebf 9123 || !h->def_regular))
5e681ec4 9124 outrel.r_info = ELF32_R_INFO (h->dynindx, r_type);
252b5132
RH		 9125 else
9126 {
a16385dc
MM		 9127 int symbol;
9128
5e681ec4 9129 /* This symbol is local, or marked to become local. */
34e77a92 9130 BFD_ASSERT (r_type == R_ARM_ABS32 || r_type == R_ARM_ABS32_NOI);
a16385dc 9131 if (globals->symbian_p)
6366ff1e 9132 {
74541ad4
AM		 9133 asection *osec;
9134
6366ff1e
MM		 9135 /* On Symbian OS, the data segment and text segement
9136 can be relocated independently. Therefore, we
9137 must indicate the segment to which this
9138 relocation is relative. The BPABI allows us to
9139 use any symbol in the right segment; we just use
9140 the section symbol as it is convenient. (We
9141 cannot use the symbol given by "h" directly as it
74541ad4
AM		 9142 will not appear in the dynamic symbol table.)
9143
9144 Note that the dynamic linker ignores the section
9145 symbol value, so we don't subtract osec->vma
9146 from the emitted reloc addend. */
10dbd1f3 9147 if (sym_sec)
74541ad4 9148 osec = sym_sec->output_section;
10dbd1f3 9149 else
74541ad4
AM		 9150 osec = input_section->output_section;
9151 symbol = elf_section_data (osec)->dynindx;
9152 if (symbol == 0)
9153 {
9154 struct elf_link_hash_table *htab = elf_hash_table (info);
9155
9156 if ((osec->flags & SEC_READONLY) == 0
9157 && htab->data_index_section != NULL)
9158 osec = htab->data_index_section;
9159 else
9160 osec = htab->text_index_section;
9161 symbol = elf_section_data (osec)->dynindx;
9162 }
6366ff1e
MM		 9163 BFD_ASSERT (symbol != 0);
9164 }
a16385dc
MM		 9165 else
9166 /* On SVR4-ish systems, the dynamic loader cannot
9167 relocate the text and data segments independently,
9168 so the symbol does not matter. */
9169 symbol = 0;
34e77a92
RS		 9170 if (dynreloc_st_type == STT_GNU_IFUNC)
9171 /* We have an STT_GNU_IFUNC symbol that doesn't resolve
9172 to the .iplt entry. Instead, every non-call reference
9173 must use an R_ARM_IRELATIVE relocation to obtain the
9174 correct run-time address. */
9175 outrel.r_info = ELF32_R_INFO (symbol, R_ARM_IRELATIVE);
9176 else
9177 outrel.r_info = ELF32_R_INFO (symbol, R_ARM_RELATIVE);
00a97672
RS		 9178 if (globals->use_rel)
9179 relocate = TRUE;
9180 else
34e77a92 9181 outrel.r_addend += dynreloc_value;
252b5132 9182 }
f21f3fe0 9183
47beaa6a 9184 elf32_arm_add_dynreloc (output_bfd, info, sreloc, &outrel);
9a5aca8c 9185
f21f3fe0 9186 /* If this reloc is against an external symbol, we do not want to
252b5132 9187 fiddle with the addend. Otherwise, we need to include the symbol
9b485d32 9188 value so that it becomes an addend for the dynamic reloc. */
252b5132
RH		 9189 if (! relocate)
9190 return bfd_reloc_ok;
9a5aca8c 9191
f21f3fe0 9192 return _bfd_final_link_relocate (howto, input_bfd, input_section,
34e77a92
RS		 9193 contents, rel->r_offset,
9194 dynreloc_value, (bfd_vma) 0);
252b5132
RH		 9195 }
9196 else switch (r_type)
9197 {
00a97672
RS		 9198 case R_ARM_ABS12:
9199 return elf32_arm_abs12_reloc (input_bfd, hit_data, value + addend);
9200
dfc5f959 9201 case R_ARM_XPC25: /* Arm BLX instruction. */
5b5bb741
PB		 9202 case R_ARM_CALL:
9203 case R_ARM_JUMP24:
8029a119 9204 case R_ARM_PC24: /* Arm B/BL instruction. */
7359ea65 9205 case R_ARM_PLT32:
906e58ca 9206 {
906e58ca
NC		 9207 struct elf32_arm_stub_hash_entry *stub_entry = NULL;
9208
dfc5f959 9209 if (r_type == R_ARM_XPC25)
252b5132 9210 {
dfc5f959
NC		 9211 /* Check for Arm calling Arm function. */
9212 /* FIXME: Should we translate the instruction into a BL
9213 instruction instead ? */
35fc36a8 9214 if (branch_type != ST_BRANCH_TO_THUMB)
d003868e
AM		 9215 (*_bfd_error_handler)
9216 (_("\%B: Warning: Arm BLX instruction targets Arm function '%s'."),
9217 input_bfd,
9218 h ? h->root.root.string : "(local)");
dfc5f959 9219 }
155d87d7 9220 else if (r_type == R_ARM_PC24)
dfc5f959
NC		 9221 {
9222 /* Check for Arm calling Thumb function. */
35fc36a8 9223 if (branch_type == ST_BRANCH_TO_THUMB)
dfc5f959 9224 {
f2a9dd69
DJ		 9225 if (elf32_arm_to_thumb_stub (info, sym_name, input_bfd,
9226 output_bfd, input_section,
9227 hit_data, sym_sec, rel->r_offset,
9228 signed_addend, value,
9229 error_message))
9230 return bfd_reloc_ok;
9231 else
9232 return bfd_reloc_dangerous;
dfc5f959 9233 }
252b5132 9234 }
ba96a88f 9235
906e58ca 9236 /* Check if a stub has to be inserted because the
8029a119 9237 destination is too far or we are changing mode. */
155d87d7
CL		 9238 if ( r_type == R_ARM_CALL
9239 || r_type == R_ARM_JUMP24
9240 || r_type == R_ARM_PLT32)
906e58ca 9241 {
fe33d2fa
CL		 9242 enum elf32_arm_stub_type stub_type = arm_stub_none;
9243 struct elf32_arm_link_hash_entry *hash;
9244
9245 hash = (struct elf32_arm_link_hash_entry *) h;
9246 stub_type = arm_type_of_stub (info, input_section, rel,
34e77a92
RS		 9247 st_type, &branch_type,
9248 hash, value, sym_sec,
fe33d2fa 9249 input_bfd, sym_name);
5fa9e92f 9250
fe33d2fa 9251 if (stub_type != arm_stub_none)
906e58ca
NC		 9252 {
9253 /* The target is out of reach, so redirect the
9254 branch to the local stub for this function. */
906e58ca
NC		 9255 stub_entry = elf32_arm_get_stub_entry (input_section,
9256 sym_sec, h,
fe33d2fa
CL		 9257 rel, globals,
9258 stub_type);
9cd3e4e5
NC		 9259 {
9260 if (stub_entry != NULL)
9261 value = (stub_entry->stub_offset
9262 + stub_entry->stub_sec->output_offset
9263 + stub_entry->stub_sec->output_section->vma);
9264
9265 if (plt_offset != (bfd_vma) -1)
9266 *unresolved_reloc_p = FALSE;
9267 }
906e58ca 9268 }
fe33d2fa
CL		 9269 else
9270 {
9271 /* If the call goes through a PLT entry, make sure to
9272 check distance to the right destination address. */
34e77a92 9273 if (plt_offset != (bfd_vma) -1)
fe33d2fa
CL		 9274 {
9275 value = (splt->output_section->vma
9276 + splt->output_offset
34e77a92 9277 + plt_offset);
fe33d2fa
CL		 9278 *unresolved_reloc_p = FALSE;
9279 /* The PLT entry is in ARM mode, regardless of the
9280 target function. */
35fc36a8 9281 branch_type = ST_BRANCH_TO_ARM;
fe33d2fa
CL		 9282 }
9283 }
906e58ca
NC		 9284 }
9285
dea514f5
PB		 9286 /* The ARM ELF ABI says that this reloc is computed as: S - P + A
9287 where:
9288 S is the address of the symbol in the relocation.
9289 P is address of the instruction being relocated.
9290 A is the addend (extracted from the instruction) in bytes.
9291
9292 S is held in 'value'.
9293 P is the base address of the section containing the
9294 instruction plus the offset of the reloc into that
9295 section, ie:
9296 (input_section->output_section->vma +
9297 input_section->output_offset +
9298 rel->r_offset).
9299 A is the addend, converted into bytes, ie:
9300 (signed_addend * 4)
9301
9302 Note: None of these operations have knowledge of the pipeline
9303 size of the processor, thus it is up to the assembler to
9304 encode this information into the addend. */
9305 value -= (input_section->output_section->vma
9306 + input_section->output_offset);
9307 value -= rel->r_offset;
4e7fd91e
PB		 9308 if (globals->use_rel)
9309 value += (signed_addend << howto->size);
9310 else
9311 /* RELA addends do not have to be adjusted by howto->size. */
9312 value += signed_addend;
23080146 9313
dcb5e6e6
NC		 9314 signed_addend = value;
9315 signed_addend >>= howto->rightshift;
9a5aca8c 9316
5ab79981 9317 /* A branch to an undefined weak symbol is turned into a jump to
ffcb4889 9318 the next instruction unless a PLT entry will be created.
77b4f08f 9319 Do the same for local undefined symbols (but not for STN_UNDEF).
cd1dac3d
DG		 9320 The jump to the next instruction is optimized as a NOP depending
9321 on the architecture. */
ffcb4889 9322 if (h ? (h->root.type == bfd_link_hash_undefweak
34e77a92 9323 && plt_offset == (bfd_vma) -1)
77b4f08f 9324 : r_symndx != STN_UNDEF && bfd_is_und_section (sym_sec))
5ab79981 9325 {
cd1dac3d
DG		 9326 value = (bfd_get_32 (input_bfd, hit_data) & 0xf0000000);
9327
9328 if (arch_has_arm_nop (globals))
9329 value |= 0x0320f000;
9330 else
9331 value |= 0x01a00000; /* Using pre-UAL nop: mov r0, r0. */
5ab79981
PB		 9332 }
9333 else
59f2c4e7 9334 {
9b485d32 9335 /* Perform a signed range check. */
dcb5e6e6 9336 if ( signed_addend > ((bfd_signed_vma) (howto->dst_mask >> 1))
59f2c4e7
NC		 9337 || signed_addend < - ((bfd_signed_vma) ((howto->dst_mask + 1) >> 1)))
9338 return bfd_reloc_overflow;
9a5aca8c 9339
5ab79981 9340 addend = (value & 2);
39b41c9c 9341
5ab79981
PB		 9342 value = (signed_addend & howto->dst_mask)
9343 | (bfd_get_32 (input_bfd, hit_data) & (~ howto->dst_mask));
39b41c9c 9344
5ab79981
PB		 9345 if (r_type == R_ARM_CALL)
9346 {
155d87d7 9347 /* Set the H bit in the BLX instruction. */
35fc36a8 9348 if (branch_type == ST_BRANCH_TO_THUMB)
155d87d7
CL		 9349 {
9350 if (addend)
9351 value |= (1 << 24);
9352 else
9353 value &= ~(bfd_vma)(1 << 24);
9354 }
9355
5ab79981 9356 /* Select the correct instruction (BL or BLX). */
906e58ca 9357 /* Only if we are not handling a BL to a stub. In this
8029a119 9358 case, mode switching is performed by the stub. */
35fc36a8 9359 if (branch_type == ST_BRANCH_TO_THUMB && !stub_entry)
5ab79981 9360 value |= (1 << 28);
63e1a0fc 9361 else if (stub_entry || branch_type != ST_BRANCH_UNKNOWN)
5ab79981
PB		 9362 {
9363 value &= ~(bfd_vma)(1 << 28);
9364 value |= (1 << 24);
9365 }
39b41c9c
PB		 9366 }
9367 }
906e58ca 9368 }
252b5132 9369 break;
f21f3fe0 9370
252b5132
RH		 9371 case R_ARM_ABS32:
9372 value += addend;
35fc36a8 9373 if (branch_type == ST_BRANCH_TO_THUMB)
252b5132
RH		 9374 value |= 1;
9375 break;
f21f3fe0 9376
bb224fc3
MS		 9377 case R_ARM_ABS32_NOI:
9378 value += addend;
9379 break;
9380
252b5132 9381 case R_ARM_REL32:
a8bc6c78 9382 value += addend;
35fc36a8 9383 if (branch_type == ST_BRANCH_TO_THUMB)
a8bc6c78 9384 value |= 1;
252b5132 9385 value -= (input_section->output_section->vma
62efb346 9386 + input_section->output_offset + rel->r_offset);
252b5132 9387 break;
eb043451 9388
bb224fc3
MS		 9389 case R_ARM_REL32_NOI:
9390 value += addend;
9391 value -= (input_section->output_section->vma
9392 + input_section->output_offset + rel->r_offset);
9393 break;
9394
eb043451
PB		 9395 case R_ARM_PREL31:
9396 value -= (input_section->output_section->vma
9397 + input_section->output_offset + rel->r_offset);
9398 value += signed_addend;
9399 if (! h || h->root.type != bfd_link_hash_undefweak)
9400 {
8029a119 9401 /* Check for overflow. */
eb043451
PB		 9402 if ((value ^ (value >> 1)) & (1 << 30))
9403 return bfd_reloc_overflow;
9404 }
9405 value &= 0x7fffffff;
9406 value |= (bfd_get_32 (input_bfd, hit_data) & 0x80000000);
35fc36a8 9407 if (branch_type == ST_BRANCH_TO_THUMB)
eb043451
PB		 9408 value |= 1;
9409 break;
252b5132 9410 }
f21f3fe0 9411
252b5132
RH		 9412 bfd_put_32 (input_bfd, value, hit_data);
9413 return bfd_reloc_ok;
9414
9415 case R_ARM_ABS8:
fd0fd00c
MJ		 9416 /* PR 16202: Refectch the addend using the correct size. */
9417 if (globals->use_rel)
9418 addend = bfd_get_8 (input_bfd, hit_data);
252b5132 9419 value += addend;
4e67d4ca
DG		 9420
9421 /* There is no way to tell whether the user intended to use a signed or
9422 unsigned addend. When checking for overflow we accept either,
9423 as specified by the AAELF. */
9424 if ((long) value > 0xff || (long) value < -0x80)
252b5132
RH		 9425 return bfd_reloc_overflow;
9426
9427 bfd_put_8 (input_bfd, value, hit_data);
9428 return bfd_reloc_ok;
9429
9430 case R_ARM_ABS16:
fd0fd00c
MJ		 9431 /* PR 16202: Refectch the addend using the correct size. */
9432 if (globals->use_rel)
9433 addend = bfd_get_16 (input_bfd, hit_data);
252b5132
RH		 9434 value += addend;
9435
4e67d4ca
DG		 9436 /* See comment for R_ARM_ABS8. */
9437 if ((long) value > 0xffff || (long) value < -0x8000)
252b5132
RH		 9438 return bfd_reloc_overflow;
9439
9440 bfd_put_16 (input_bfd, value, hit_data);
9441 return bfd_reloc_ok;
9442
252b5132 9443 case R_ARM_THM_ABS5:
9b485d32 9444 /* Support ldr and str instructions for the thumb. */
4e7fd91e
PB		 9445 if (globals->use_rel)
9446 {
9447 /* Need to refetch addend. */
9448 addend = bfd_get_16 (input_bfd, hit_data) & howto->src_mask;
9449 /* ??? Need to determine shift amount from operand size. */
9450 addend >>= howto->rightshift;
9451 }
252b5132
RH		 9452 value += addend;
9453
9454 /* ??? Isn't value unsigned? */
9455 if ((long) value > 0x1f || (long) value < -0x10)
9456 return bfd_reloc_overflow;
9457
9458 /* ??? Value needs to be properly shifted into place first. */
9459 value |= bfd_get_16 (input_bfd, hit_data) & 0xf83f;
9460 bfd_put_16 (input_bfd, value, hit_data);
9461 return bfd_reloc_ok;
9462
2cab6cc3
MS		 9463 case R_ARM_THM_ALU_PREL_11_0:
9464 /* Corresponds to: addw.w reg, pc, #offset (and similarly for subw). */
9465 {
9466 bfd_vma insn;
9467 bfd_signed_vma relocation;
9468
9469 insn = (bfd_get_16 (input_bfd, hit_data) << 16)
99059e56 9470 | bfd_get_16 (input_bfd, hit_data + 2);
2cab6cc3 9471
99059e56
RM		 9472 if (globals->use_rel)
9473 {
9474 signed_addend = (insn & 0xff) | ((insn & 0x7000) >> 4)
9475 | ((insn & (1 << 26)) >> 15);
9476 if (insn & 0xf00000)
9477 signed_addend = -signed_addend;
9478 }
2cab6cc3
MS		 9479
9480 relocation = value + signed_addend;
79f08007 9481 relocation -= Pa (input_section->output_section->vma
99059e56
RM		 9482 + input_section->output_offset
9483 + rel->r_offset);
2cab6cc3 9484
b6518b38 9485 value = relocation;
2cab6cc3 9486
99059e56
RM		 9487 if (value >= 0x1000)
9488 return bfd_reloc_overflow;
2cab6cc3
MS		 9489
9490 insn = (insn & 0xfb0f8f00) | (value & 0xff)
99059e56
RM		 9491 | ((value & 0x700) << 4)
9492 | ((value & 0x800) << 15);
9493 if (relocation < 0)
9494 insn |= 0xa00000;
2cab6cc3
MS		 9495
9496 bfd_put_16 (input_bfd, insn >> 16, hit_data);
9497 bfd_put_16 (input_bfd, insn & 0xffff, hit_data + 2);
9498
99059e56 9499 return bfd_reloc_ok;
2cab6cc3
MS		 9500 }
9501
e1ec24c6
NC		 9502 case R_ARM_THM_PC8:
9503 /* PR 10073: This reloc is not generated by the GNU toolchain,
9504 but it is supported for compatibility with third party libraries
9505 generated by other compilers, specifically the ARM/IAR. */
9506 {
9507 bfd_vma insn;
9508 bfd_signed_vma relocation;
9509
9510 insn = bfd_get_16 (input_bfd, hit_data);
9511
99059e56 9512 if (globals->use_rel)
79f08007 9513 addend = ((((insn & 0x00ff) << 2) + 4) & 0x3ff) -4;
e1ec24c6
NC		 9514
9515 relocation = value + addend;
79f08007 9516 relocation -= Pa (input_section->output_section->vma
99059e56
RM		 9517 + input_section->output_offset
9518 + rel->r_offset);
e1ec24c6 9519
b6518b38 9520 value = relocation;
e1ec24c6
NC		 9521
9522 /* We do not check for overflow of this reloc. Although strictly
9523 speaking this is incorrect, it appears to be necessary in order
9524 to work with IAR generated relocs. Since GCC and GAS do not
9525 generate R_ARM_THM_PC8 relocs, the lack of a check should not be
9526 a problem for them. */
9527 value &= 0x3fc;
9528
9529 insn = (insn & 0xff00) | (value >> 2);
9530
9531 bfd_put_16 (input_bfd, insn, hit_data);
9532
99059e56 9533 return bfd_reloc_ok;
e1ec24c6
NC		 9534 }
9535
2cab6cc3
MS		 9536 case R_ARM_THM_PC12:
9537 /* Corresponds to: ldr.w reg, [pc, #offset]. */
9538 {
9539 bfd_vma insn;
9540 bfd_signed_vma relocation;
9541
9542 insn = (bfd_get_16 (input_bfd, hit_data) << 16)
99059e56 9543 | bfd_get_16 (input_bfd, hit_data + 2);
2cab6cc3 9544
99059e56
RM		 9545 if (globals->use_rel)
9546 {
9547 signed_addend = insn & 0xfff;
9548 if (!(insn & (1 << 23)))
9549 signed_addend = -signed_addend;
9550 }
2cab6cc3
MS		 9551
9552 relocation = value + signed_addend;
79f08007 9553 relocation -= Pa (input_section->output_section->vma
99059e56
RM		 9554 + input_section->output_offset
9555 + rel->r_offset);
2cab6cc3 9556
b6518b38 9557 value = relocation;
2cab6cc3 9558
99059e56
RM		 9559 if (value >= 0x1000)
9560 return bfd_reloc_overflow;
2cab6cc3
MS		 9561
9562 insn = (insn & 0xff7ff000) | value;
99059e56
RM		 9563 if (relocation >= 0)
9564 insn |= (1 << 23);
2cab6cc3
MS		 9565
9566 bfd_put_16 (input_bfd, insn >> 16, hit_data);
9567 bfd_put_16 (input_bfd, insn & 0xffff, hit_data + 2);
9568
99059e56 9569 return bfd_reloc_ok;
2cab6cc3
MS		 9570 }
9571
dfc5f959 9572 case R_ARM_THM_XPC22:
c19d1205 9573 case R_ARM_THM_CALL:
bd97cb95 9574 case R_ARM_THM_JUMP24:
dfc5f959 9575 /* Thumb BL (branch long instruction). */
252b5132 9576 {
b34976b6 9577 bfd_vma relocation;
99059e56 9578 bfd_vma reloc_sign;
b34976b6
AM		 9579 bfd_boolean overflow = FALSE;
9580 bfd_vma upper_insn = bfd_get_16 (input_bfd, hit_data);
9581 bfd_vma lower_insn = bfd_get_16 (input_bfd, hit_data + 2);
e95de063
MS		 9582 bfd_signed_vma reloc_signed_max;
9583 bfd_signed_vma reloc_signed_min;
b34976b6 9584 bfd_vma check;
252b5132 9585 bfd_signed_vma signed_check;
e95de063 9586 int bitsize;
cd1dac3d 9587 const int thumb2 = using_thumb2 (globals);
252b5132 9588
5ab79981 9589 /* A branch to an undefined weak symbol is turned into a jump to
cd1dac3d
DG		 9590 the next instruction unless a PLT entry will be created.
9591 The jump to the next instruction is optimized as a NOP.W for
9592 Thumb-2 enabled architectures. */
19540007 9593 if (h && h->root.type == bfd_link_hash_undefweak
34e77a92 9594 && plt_offset == (bfd_vma) -1)
5ab79981 9595 {
cd1dac3d
DG		 9596 if (arch_has_thumb2_nop (globals))
9597 {
9598 bfd_put_16 (input_bfd, 0xf3af, hit_data);
9599 bfd_put_16 (input_bfd, 0x8000, hit_data + 2);
9600 }
9601 else
9602 {
9603 bfd_put_16 (input_bfd, 0xe000, hit_data);
9604 bfd_put_16 (input_bfd, 0xbf00, hit_data + 2);
9605 }
5ab79981
PB		 9606 return bfd_reloc_ok;
9607 }
9608
e95de063 9609 /* Fetch the addend. We use the Thumb-2 encoding (backwards compatible
99059e56 9610 with Thumb-1) involving the J1 and J2 bits. */
4e7fd91e
PB		 9611 if (globals->use_rel)
9612 {
99059e56
RM		 9613 bfd_vma s = (upper_insn & (1 << 10)) >> 10;
9614 bfd_vma upper = upper_insn & 0x3ff;
9615 bfd_vma lower = lower_insn & 0x7ff;
e95de063
MS		 9616 bfd_vma j1 = (lower_insn & (1 << 13)) >> 13;
9617 bfd_vma j2 = (lower_insn & (1 << 11)) >> 11;
99059e56
RM		 9618 bfd_vma i1 = j1 ^ s ? 0 : 1;
9619 bfd_vma i2 = j2 ^ s ? 0 : 1;
e95de063 9620
99059e56
RM		 9621 addend = (i1 << 23) | (i2 << 22) | (upper << 12) | (lower << 1);
9622 /* Sign extend. */
9623 addend = (addend | ((s ? 0 : 1) << 24)) - (1 << 24);
e95de063 9624
4e7fd91e
PB		 9625 signed_addend = addend;
9626 }
cb1afa5c 9627
dfc5f959
NC		 9628 if (r_type == R_ARM_THM_XPC22)
9629 {
9630 /* Check for Thumb to Thumb call. */
9631 /* FIXME: Should we translate the instruction into a BL
9632 instruction instead ? */
35fc36a8 9633 if (branch_type == ST_BRANCH_TO_THUMB)
d003868e
AM		 9634 (*_bfd_error_handler)
9635 (_("%B: Warning: Thumb BLX instruction targets thumb function '%s'."),
9636 input_bfd,
9637 h ? h->root.root.string : "(local)");
dfc5f959
NC		 9638 }
9639 else
252b5132 9640 {
dfc5f959
NC		 9641 /* If it is not a call to Thumb, assume call to Arm.
9642 If it is a call relative to a section name, then it is not a
b7693d02
DJ		 9643 function call at all, but rather a long jump. Calls through
9644 the PLT do not require stubs. */
34e77a92 9645 if (branch_type == ST_BRANCH_TO_ARM && plt_offset == (bfd_vma) -1)
dfc5f959 9646 {
bd97cb95 9647 if (globals->use_blx && r_type == R_ARM_THM_CALL)
39b41c9c
PB		 9648 {
9649 /* Convert BL to BLX. */
9650 lower_insn = (lower_insn & ~0x1000) | 0x0800;
9651 }
155d87d7
CL		 9652 else if (( r_type != R_ARM_THM_CALL)
9653 && (r_type != R_ARM_THM_JUMP24))
8029a119
NC		 9654 {
9655 if (elf32_thumb_to_arm_stub
9656 (info, sym_name, input_bfd, output_bfd, input_section,
9657 hit_data, sym_sec, rel->r_offset, signed_addend, value,
9658 error_message))
9659 return bfd_reloc_ok;
9660 else
9661 return bfd_reloc_dangerous;
9662 }
da5938a2 9663 }
35fc36a8
RS		 9664 else if (branch_type == ST_BRANCH_TO_THUMB
9665 && globals->use_blx
bd97cb95 9666 && r_type == R_ARM_THM_CALL)
39b41c9c
PB		 9667 {
9668 /* Make sure this is a BL. */
9669 lower_insn |= 0x1800;
9670 }
252b5132 9671 }
f21f3fe0 9672
fe33d2fa 9673 enum elf32_arm_stub_type stub_type = arm_stub_none;
155d87d7 9674 if (r_type == R_ARM_THM_CALL || r_type == R_ARM_THM_JUMP24)
906e58ca
NC		 9675 {
9676 /* Check if a stub has to be inserted because the destination
8029a119 9677 is too far. */
fe33d2fa
CL		 9678 struct elf32_arm_stub_hash_entry *stub_entry;
9679 struct elf32_arm_link_hash_entry *hash;
9680
9681 hash = (struct elf32_arm_link_hash_entry *) h;
9682
9683 stub_type = arm_type_of_stub (info, input_section, rel,
34e77a92
RS		 9684 st_type, &branch_type,
9685 hash, value, sym_sec,
fe33d2fa
CL		 9686 input_bfd, sym_name);
9687
9688 if (stub_type != arm_stub_none)
906e58ca
NC		 9689 {
9690 /* The target is out of reach or we are changing modes, so
9691 redirect the branch to the local stub for this
9692 function. */
9693 stub_entry = elf32_arm_get_stub_entry (input_section,
9694 sym_sec, h,
fe33d2fa
CL		 9695 rel, globals,
9696 stub_type);
906e58ca 9697 if (stub_entry != NULL)
9cd3e4e5
NC		 9698 {
9699 value = (stub_entry->stub_offset
9700 + stub_entry->stub_sec->output_offset
9701 + stub_entry->stub_sec->output_section->vma);
9702
9703 if (plt_offset != (bfd_vma) -1)
9704 *unresolved_reloc_p = FALSE;
9705 }
906e58ca 9706
f4ac8484 9707 /* If this call becomes a call to Arm, force BLX. */
155d87d7 9708 if (globals->use_blx && (r_type == R_ARM_THM_CALL))
f4ac8484
DJ		 9709 {
9710 if ((stub_entry
9711 && !arm_stub_is_thumb (stub_entry->stub_type))
35fc36a8 9712 || branch_type != ST_BRANCH_TO_THUMB)
f4ac8484
DJ		 9713 lower_insn = (lower_insn & ~0x1000) | 0x0800;
9714 }
906e58ca
NC		 9715 }
9716 }
9717
fe33d2fa 9718 /* Handle calls via the PLT. */
34e77a92 9719 if (stub_type == arm_stub_none && plt_offset != (bfd_vma) -1)
fe33d2fa
CL		 9720 {
9721 value = (splt->output_section->vma
9722 + splt->output_offset
34e77a92 9723 + plt_offset);
fe33d2fa 9724
eed94f8f
NC		 9725 if (globals->use_blx
9726 && r_type == R_ARM_THM_CALL
9727 && ! using_thumb_only (globals))
fe33d2fa
CL		 9728 {
9729 /* If the Thumb BLX instruction is available, convert
9730 the BL to a BLX instruction to call the ARM-mode
9731 PLT entry. */
9732 lower_insn = (lower_insn & ~0x1000) | 0x0800;
35fc36a8 9733 branch_type = ST_BRANCH_TO_ARM;
fe33d2fa
CL		 9734 }
9735 else
9736 {
eed94f8f
NC		 9737 if (! using_thumb_only (globals))
9738 /* Target the Thumb stub before the ARM PLT entry. */
9739 value -= PLT_THUMB_STUB_SIZE;
35fc36a8 9740 branch_type = ST_BRANCH_TO_THUMB;
fe33d2fa
CL		 9741 }
9742 *unresolved_reloc_p = FALSE;
9743 }
9744
ba96a88f 9745 relocation = value + signed_addend;
f21f3fe0 9746
252b5132 9747 relocation -= (input_section->output_section->vma
ba96a88f
NC		 9748 + input_section->output_offset
9749 + rel->r_offset);
9a5aca8c 9750
252b5132
RH		 9751 check = relocation >> howto->rightshift;
9752
9753 /* If this is a signed value, the rightshift just dropped
9754 leading 1 bits (assuming twos complement). */
9755 if ((bfd_signed_vma) relocation >= 0)
9756 signed_check = check;
9757 else
9758 signed_check = check | ~((bfd_vma) -1 >> howto->rightshift);
9759
e95de063
MS		 9760 /* Calculate the permissable maximum and minimum values for
9761 this relocation according to whether we're relocating for
9762 Thumb-2 or not. */
9763 bitsize = howto->bitsize;
9764 if (!thumb2)
9765 bitsize -= 2;
f6ebfac0 9766 reloc_signed_max = (1 << (bitsize - 1)) - 1;
e95de063
MS		 9767 reloc_signed_min = ~reloc_signed_max;
9768
252b5132 9769 /* Assumes two's complement. */
ba96a88f 9770 if (signed_check > reloc_signed_max || signed_check < reloc_signed_min)
b34976b6 9771 overflow = TRUE;
252b5132 9772
bd97cb95 9773 if ((lower_insn & 0x5000) == 0x4000)
c62e1cc3
NC		 9774 /* For a BLX instruction, make sure that the relocation is rounded up
9775 to a word boundary. This follows the semantics of the instruction
9776 which specifies that bit 1 of the target address will come from bit
9777 1 of the base address. */
9778 relocation = (relocation + 2) & ~ 3;
cb1afa5c 9779
e95de063
MS		 9780 /* Put RELOCATION back into the insn. Assumes two's complement.
9781 We use the Thumb-2 encoding, which is safe even if dealing with
9782 a Thumb-1 instruction by virtue of our overflow check above. */
99059e56 9783 reloc_sign = (signed_check < 0) ? 1 : 0;
e95de063 9784 upper_insn = (upper_insn & ~(bfd_vma) 0x7ff)
99059e56
RM		 9785 | ((relocation >> 12) & 0x3ff)
9786 | (reloc_sign << 10);
906e58ca 9787 lower_insn = (lower_insn & ~(bfd_vma) 0x2fff)
99059e56
RM		 9788 | (((!((relocation >> 23) & 1)) ^ reloc_sign) << 13)
9789 | (((!((relocation >> 22) & 1)) ^ reloc_sign) << 11)
9790 | ((relocation >> 1) & 0x7ff);
c62e1cc3 9791
252b5132
RH		 9792 /* Put the relocated value back in the object file: */
9793 bfd_put_16 (input_bfd, upper_insn, hit_data);
9794 bfd_put_16 (input_bfd, lower_insn, hit_data + 2);
9795
9796 return (overflow ? bfd_reloc_overflow : bfd_reloc_ok);
9797 }
9798 break;
9799
c19d1205
ZW		 9800 case R_ARM_THM_JUMP19:
9801 /* Thumb32 conditional branch instruction. */
9802 {
9803 bfd_vma relocation;
9804 bfd_boolean overflow = FALSE;
9805 bfd_vma upper_insn = bfd_get_16 (input_bfd, hit_data);
9806 bfd_vma lower_insn = bfd_get_16 (input_bfd, hit_data + 2);
a00a1f35
MS		 9807 bfd_signed_vma reloc_signed_max = 0xffffe;
9808 bfd_signed_vma reloc_signed_min = -0x100000;
c19d1205 9809 bfd_signed_vma signed_check;
c5423981
TG		 9810 enum elf32_arm_stub_type stub_type = arm_stub_none;
9811 struct elf32_arm_stub_hash_entry *stub_entry;
9812 struct elf32_arm_link_hash_entry *hash;
c19d1205
ZW		 9813
9814 /* Need to refetch the addend, reconstruct the top three bits,
9815 and squish the two 11 bit pieces together. */
9816 if (globals->use_rel)
9817 {
9818 bfd_vma S = (upper_insn & 0x0400) >> 10;
a00a1f35 9819 bfd_vma upper = (upper_insn & 0x003f);
c19d1205
ZW		 9820 bfd_vma J1 = (lower_insn & 0x2000) >> 13;
9821 bfd_vma J2 = (lower_insn & 0x0800) >> 11;
9822 bfd_vma lower = (lower_insn & 0x07ff);
9823
a00a1f35
MS		 9824 upper |= J1 << 6;
9825 upper |= J2 << 7;
9826 upper |= (!S) << 8;
c19d1205
ZW		 9827 upper -= 0x0100; /* Sign extend. */
9828
9829 addend = (upper << 12) | (lower << 1);
9830 signed_addend = addend;
9831 }
9832
bd97cb95 9833 /* Handle calls via the PLT. */
34e77a92 9834 if (plt_offset != (bfd_vma) -1)
bd97cb95
DJ		 9835 {
9836 value = (splt->output_section->vma
9837 + splt->output_offset
34e77a92 9838 + plt_offset);
bd97cb95
DJ		 9839 /* Target the Thumb stub before the ARM PLT entry. */
9840 value -= PLT_THUMB_STUB_SIZE;
9841 *unresolved_reloc_p = FALSE;
9842 }
9843
c5423981
TG		 9844 hash = (struct elf32_arm_link_hash_entry *)h;
9845
9846 stub_type = arm_type_of_stub (info, input_section, rel,
9847 st_type, &branch_type,
9848 hash, value, sym_sec,
9849 input_bfd, sym_name);
9850 if (stub_type != arm_stub_none)
9851 {
9852 stub_entry = elf32_arm_get_stub_entry (input_section,
9853 sym_sec, h,
9854 rel, globals,
9855 stub_type);
9856 if (stub_entry != NULL)
9857 {
9858 value = (stub_entry->stub_offset
9859 + stub_entry->stub_sec->output_offset
9860 + stub_entry->stub_sec->output_section->vma);
9861 }
9862 }
c19d1205 9863
99059e56 9864 relocation = value + signed_addend;
c19d1205
ZW		 9865 relocation -= (input_section->output_section->vma
9866 + input_section->output_offset
9867 + rel->r_offset);
a00a1f35 9868 signed_check = (bfd_signed_vma) relocation;
c19d1205 9869
c19d1205
ZW		 9870 if (signed_check > reloc_signed_max || signed_check < reloc_signed_min)
9871 overflow = TRUE;
9872
9873 /* Put RELOCATION back into the insn. */
9874 {
9875 bfd_vma S = (relocation & 0x00100000) >> 20;
9876 bfd_vma J2 = (relocation & 0x00080000) >> 19;
9877 bfd_vma J1 = (relocation & 0x00040000) >> 18;
9878 bfd_vma hi = (relocation & 0x0003f000) >> 12;
9879 bfd_vma lo = (relocation & 0x00000ffe) >> 1;
9880
a00a1f35 9881 upper_insn = (upper_insn & 0xfbc0) | (S << 10) | hi;
c19d1205
ZW		 9882 lower_insn = (lower_insn & 0xd000) | (J1 << 13) | (J2 << 11) | lo;
9883 }
9884
9885 /* Put the relocated value back in the object file: */
9886 bfd_put_16 (input_bfd, upper_insn, hit_data);
9887 bfd_put_16 (input_bfd, lower_insn, hit_data + 2);
9888
9889 return (overflow ? bfd_reloc_overflow : bfd_reloc_ok);
9890 }
9891
9892 case R_ARM_THM_JUMP11:
9893 case R_ARM_THM_JUMP8:
9894 case R_ARM_THM_JUMP6:
51c5503b
NC		 9895 /* Thumb B (branch) instruction). */
9896 {
6cf9e9fe 9897 bfd_signed_vma relocation;
51c5503b
NC		 9898 bfd_signed_vma reloc_signed_max = (1 << (howto->bitsize - 1)) - 1;
9899 bfd_signed_vma reloc_signed_min = ~ reloc_signed_max;
51c5503b
NC		 9900 bfd_signed_vma signed_check;
9901
c19d1205
ZW		 9902 /* CZB cannot jump backward. */
9903 if (r_type == R_ARM_THM_JUMP6)
9904 reloc_signed_min = 0;
9905
4e7fd91e 9906 if (globals->use_rel)
6cf9e9fe 9907 {
4e7fd91e
PB		 9908 /* Need to refetch addend. */
9909 addend = bfd_get_16 (input_bfd, hit_data) & howto->src_mask;
9910 if (addend & ((howto->src_mask + 1) >> 1))
9911 {
9912 signed_addend = -1;
9913 signed_addend &= ~ howto->src_mask;
9914 signed_addend |= addend;
9915 }
9916 else
9917 signed_addend = addend;
9918 /* The value in the insn has been right shifted. We need to
9919 undo this, so that we can perform the address calculation
9920 in terms of bytes. */
9921 signed_addend <<= howto->rightshift;
6cf9e9fe 9922 }
6cf9e9fe 9923 relocation = value + signed_addend;
51c5503b
NC		 9924
9925 relocation -= (input_section->output_section->vma
9926 + input_section->output_offset
9927 + rel->r_offset);
9928
6cf9e9fe
NC		 9929 relocation >>= howto->rightshift;
9930 signed_check = relocation;
c19d1205
ZW		 9931
9932 if (r_type == R_ARM_THM_JUMP6)
9933 relocation = ((relocation & 0x0020) << 4) | ((relocation & 0x001f) << 3);
9934 else
9935 relocation &= howto->dst_mask;
51c5503b 9936 relocation |= (bfd_get_16 (input_bfd, hit_data) & (~ howto->dst_mask));
cedb70c5 9937
51c5503b
NC		 9938 bfd_put_16 (input_bfd, relocation, hit_data);
9939
9940 /* Assumes two's complement. */
9941 if (signed_check > reloc_signed_max || signed_check < reloc_signed_min)
9942 return bfd_reloc_overflow;
9943
9944 return bfd_reloc_ok;
9945 }
cedb70c5 9946
8375c36b
PB		 9947 case R_ARM_ALU_PCREL7_0:
9948 case R_ARM_ALU_PCREL15_8:
9949 case R_ARM_ALU_PCREL23_15:
9950 {
9951 bfd_vma insn;
9952 bfd_vma relocation;
9953
9954 insn = bfd_get_32 (input_bfd, hit_data);
4e7fd91e
PB		 9955 if (globals->use_rel)
9956 {
9957 /* Extract the addend. */
9958 addend = (insn & 0xff) << ((insn & 0xf00) >> 7);
9959 signed_addend = addend;
9960 }
8375c36b
PB		 9961 relocation = value + signed_addend;
9962
9963 relocation -= (input_section->output_section->vma
9964 + input_section->output_offset
9965 + rel->r_offset);
9966 insn = (insn & ~0xfff)
9967 | ((howto->bitpos << 7) & 0xf00)
9968 | ((relocation >> howto->bitpos) & 0xff);
9969 bfd_put_32 (input_bfd, value, hit_data);
9970 }
9971 return bfd_reloc_ok;
9972
252b5132
RH		 9973 case R_ARM_GNU_VTINHERIT:
9974 case R_ARM_GNU_VTENTRY:
9975 return bfd_reloc_ok;
9976
c19d1205 9977 case R_ARM_GOTOFF32:
252b5132 9978 /* Relocation is relative to the start of the
99059e56 9979 global offset table. */
252b5132
RH		 9980
9981 BFD_ASSERT (sgot != NULL);
9982 if (sgot == NULL)
99059e56 9983 return bfd_reloc_notsupported;
9a5aca8c 9984
cedb70c5 9985 /* If we are addressing a Thumb function, we need to adjust the
ee29b9fb
RE		 9986 address by one, so that attempts to call the function pointer will
9987 correctly interpret it as Thumb code. */
35fc36a8 9988 if (branch_type == ST_BRANCH_TO_THUMB)
ee29b9fb
RE		 9989 value += 1;
9990
252b5132 9991 /* Note that sgot->output_offset is not involved in this
99059e56
RM		 9992 calculation. We always want the start of .got. If we
9993 define _GLOBAL_OFFSET_TABLE in a different way, as is
9994 permitted by the ABI, we might have to change this
9995 calculation. */
252b5132 9996 value -= sgot->output_section->vma;
f21f3fe0 9997 return _bfd_final_link_relocate (howto, input_bfd, input_section,
99e4ae17 9998 contents, rel->r_offset, value,
00a97672 9999 rel->r_addend);
252b5132
RH		 10000
10001 case R_ARM_GOTPC:
a7c10850 10002 /* Use global offset table as symbol value. */
252b5132 10003 BFD_ASSERT (sgot != NULL);
f21f3fe0 10004
252b5132 10005 if (sgot == NULL)
99059e56 10006 return bfd_reloc_notsupported;
252b5132 10007
0945cdfd 10008 *unresolved_reloc_p = FALSE;
252b5132 10009 value = sgot->output_section->vma;
f21f3fe0 10010 return _bfd_final_link_relocate (howto, input_bfd, input_section,
99e4ae17 10011 contents, rel->r_offset, value,
00a97672 10012 rel->r_addend);
f21f3fe0 10013
252b5132 10014 case R_ARM_GOT32:
eb043451 10015 case R_ARM_GOT_PREL:
252b5132 10016 /* Relocation is to the entry for this symbol in the
99059e56 10017 global offset table. */
252b5132
RH		 10018 if (sgot == NULL)
10019 return bfd_reloc_notsupported;
f21f3fe0 10020
34e77a92
RS		 10021 if (dynreloc_st_type == STT_GNU_IFUNC
10022 && plt_offset != (bfd_vma) -1
10023 && (h == NULL || SYMBOL_REFERENCES_LOCAL (info, h)))
10024 {
10025 /* We have a relocation against a locally-binding STT_GNU_IFUNC
10026 symbol, and the relocation resolves directly to the runtime
10027 target rather than to the .iplt entry. This means that any
10028 .got entry would be the same value as the .igot.plt entry,
10029 so there's no point creating both. */
10030 sgot = globals->root.igotplt;
10031 value = sgot->output_offset + gotplt_offset;
10032 }
10033 else if (h != NULL)
252b5132
RH		 10034 {
10035 bfd_vma off;
f21f3fe0 10036
252b5132
RH		 10037 off = h->got.offset;
10038 BFD_ASSERT (off != (bfd_vma) -1);
b436d854 10039 if ((off & 1) != 0)
252b5132 10040 {
b436d854
RS		 10041 /* We have already processsed one GOT relocation against
10042 this symbol. */
10043 off &= ~1;
10044 if (globals->root.dynamic_sections_created
10045 && !SYMBOL_REFERENCES_LOCAL (info, h))
10046 *unresolved_reloc_p = FALSE;
10047 }
10048 else
10049 {
10050 Elf_Internal_Rela outrel;
10051
6f820c85 10052 if (h->dynindx != -1 && !SYMBOL_REFERENCES_LOCAL (info, h))
b436d854
RS		 10053 {
10054 /* If the symbol doesn't resolve locally in a static
10055 object, we have an undefined reference. If the
10056 symbol doesn't resolve locally in a dynamic object,
10057 it should be resolved by the dynamic linker. */
10058 if (globals->root.dynamic_sections_created)
10059 {
10060 outrel.r_info = ELF32_R_INFO (h->dynindx, R_ARM_GLOB_DAT);
10061 *unresolved_reloc_p = FALSE;
10062 }
10063 else
10064 outrel.r_info = 0;
10065 outrel.r_addend = 0;
10066 }
252b5132
RH		 10067 else
10068 {
34e77a92 10069 if (dynreloc_st_type == STT_GNU_IFUNC)
99059e56 10070 outrel.r_info = ELF32_R_INFO (0, R_ARM_IRELATIVE);
0e1862bb 10071 else if (bfd_link_pic (info) &&
31943882
WN		 10072 (ELF_ST_VISIBILITY (h->other) == STV_DEFAULT
10073 || h->root.type != bfd_link_hash_undefweak))
99059e56
RM		 10074 outrel.r_info = ELF32_R_INFO (0, R_ARM_RELATIVE);
10075 else
10076 outrel.r_info = 0;
34e77a92 10077 outrel.r_addend = dynreloc_value;
b436d854 10078 }
ee29b9fb 10079
b436d854
RS		 10080 /* The GOT entry is initialized to zero by default.
10081 See if we should install a different value. */
10082 if (outrel.r_addend != 0
10083 && (outrel.r_info == 0 || globals->use_rel))
10084 {
10085 bfd_put_32 (output_bfd, outrel.r_addend,
10086 sgot->contents + off);
10087 outrel.r_addend = 0;
252b5132 10088 }
f21f3fe0 10089
b436d854
RS		 10090 if (outrel.r_info != 0)
10091 {
10092 outrel.r_offset = (sgot->output_section->vma
10093 + sgot->output_offset
10094 + off);
10095 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
10096 }
10097 h->got.offset |= 1;
10098 }
252b5132
RH		 10099 value = sgot->output_offset + off;
10100 }
10101 else
10102 {
10103 bfd_vma off;
f21f3fe0 10104
252b5132
RH		 10105 BFD_ASSERT (local_got_offsets != NULL &&
10106 local_got_offsets[r_symndx] != (bfd_vma) -1);
f21f3fe0 10107
252b5132 10108 off = local_got_offsets[r_symndx];
f21f3fe0 10109
252b5132
RH		 10110 /* The offset must always be a multiple of 4. We use the
10111 least significant bit to record whether we have already
9b485d32 10112 generated the necessary reloc. */
252b5132
RH		 10113 if ((off & 1) != 0)
10114 off &= ~1;
10115 else
10116 {
00a97672 10117 if (globals->use_rel)
34e77a92 10118 bfd_put_32 (output_bfd, dynreloc_value, sgot->contents + off);
f21f3fe0 10119
0e1862bb 10120 if (bfd_link_pic (info) || dynreloc_st_type == STT_GNU_IFUNC)
252b5132 10121 {
947216bf 10122 Elf_Internal_Rela outrel;
f21f3fe0 10123
34e77a92 10124 outrel.r_addend = addend + dynreloc_value;
252b5132 10125 outrel.r_offset = (sgot->output_section->vma
f21f3fe0 10126 + sgot->output_offset
252b5132 10127 + off);
34e77a92 10128 if (dynreloc_st_type == STT_GNU_IFUNC)
99059e56 10129 outrel.r_info = ELF32_R_INFO (0, R_ARM_IRELATIVE);
34e77a92
RS		 10130 else
10131 outrel.r_info = ELF32_R_INFO (0, R_ARM_RELATIVE);
47beaa6a 10132 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
252b5132 10133 }
f21f3fe0 10134
252b5132
RH		 10135 local_got_offsets[r_symndx] |= 1;
10136 }
f21f3fe0 10137
252b5132
RH		 10138 value = sgot->output_offset + off;
10139 }
eb043451
PB		 10140 if (r_type != R_ARM_GOT32)
10141 value += sgot->output_section->vma;
9a5aca8c 10142
f21f3fe0 10143 return _bfd_final_link_relocate (howto, input_bfd, input_section,
99e4ae17 10144 contents, rel->r_offset, value,
00a97672 10145 rel->r_addend);
f21f3fe0 10146
ba93b8ac
DJ		 10147 case R_ARM_TLS_LDO32:
10148 value = value - dtpoff_base (info);
10149
10150 return _bfd_final_link_relocate (howto, input_bfd, input_section,
00a97672
RS		 10151 contents, rel->r_offset, value,
10152 rel->r_addend);
ba93b8ac
DJ		 10153
10154 case R_ARM_TLS_LDM32:
10155 {
10156 bfd_vma off;
10157
362d30a1 10158 if (sgot == NULL)
ba93b8ac
DJ		 10159 abort ();
10160
10161 off = globals->tls_ldm_got.offset;
10162
10163 if ((off & 1) != 0)
10164 off &= ~1;
10165 else
10166 {
10167 /* If we don't know the module number, create a relocation
10168 for it. */
0e1862bb 10169 if (bfd_link_pic (info))
ba93b8ac
DJ		 10170 {
10171 Elf_Internal_Rela outrel;
ba93b8ac 10172
362d30a1 10173 if (srelgot == NULL)
ba93b8ac
DJ		 10174 abort ();
10175
00a97672 10176 outrel.r_addend = 0;
362d30a1
RS		 10177 outrel.r_offset = (sgot->output_section->vma
10178 + sgot->output_offset + off);
ba93b8ac
DJ		 10179 outrel.r_info = ELF32_R_INFO (0, R_ARM_TLS_DTPMOD32);
10180
00a97672
RS		 10181 if (globals->use_rel)
10182 bfd_put_32 (output_bfd, outrel.r_addend,
362d30a1 10183 sgot->contents + off);
ba93b8ac 10184
47beaa6a 10185 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
ba93b8ac
DJ		 10186 }
10187 else
362d30a1 10188 bfd_put_32 (output_bfd, 1, sgot->contents + off);
ba93b8ac
DJ		 10189
10190 globals->tls_ldm_got.offset |= 1;
10191 }
10192
362d30a1 10193 value = sgot->output_section->vma + sgot->output_offset + off
ba93b8ac
DJ		 10194 - (input_section->output_section->vma + input_section->output_offset + rel->r_offset);
10195
10196 return _bfd_final_link_relocate (howto, input_bfd, input_section,
10197 contents, rel->r_offset, value,
00a97672 10198 rel->r_addend);
ba93b8ac
DJ		 10199 }
10200
0855e32b
NS		 10201 case R_ARM_TLS_CALL:
10202 case R_ARM_THM_TLS_CALL:
ba93b8ac
DJ		 10203 case R_ARM_TLS_GD32:
10204 case R_ARM_TLS_IE32:
0855e32b
NS		 10205 case R_ARM_TLS_GOTDESC:
10206 case R_ARM_TLS_DESCSEQ:
10207 case R_ARM_THM_TLS_DESCSEQ:
ba93b8ac 10208 {
0855e32b
NS		 10209 bfd_vma off, offplt;
10210 int indx = 0;
ba93b8ac
DJ		 10211 char tls_type;
10212
0855e32b 10213 BFD_ASSERT (sgot != NULL);
ba93b8ac 10214
ba93b8ac
DJ		 10215 if (h != NULL)
10216 {
10217 bfd_boolean dyn;
10218 dyn = globals->root.dynamic_sections_created;
0e1862bb
L		 10219 if (WILL_CALL_FINISH_DYNAMIC_SYMBOL (dyn,
10220 bfd_link_pic (info),
10221 h)
10222 && (!bfd_link_pic (info)
ba93b8ac
DJ		 10223 || !SYMBOL_REFERENCES_LOCAL (info, h)))
10224 {
10225 *unresolved_reloc_p = FALSE;
10226 indx = h->dynindx;
10227 }
10228 off = h->got.offset;
0855e32b 10229 offplt = elf32_arm_hash_entry (h)->tlsdesc_got;
ba93b8ac
DJ		 10230 tls_type = ((struct elf32_arm_link_hash_entry *) h)->tls_type;
10231 }
10232 else
10233 {
0855e32b 10234 BFD_ASSERT (local_got_offsets != NULL);
ba93b8ac 10235 off = local_got_offsets[r_symndx];
0855e32b 10236 offplt = local_tlsdesc_gotents[r_symndx];
ba93b8ac
DJ		 10237 tls_type = elf32_arm_local_got_tls_type (input_bfd)[r_symndx];
10238 }
10239
0855e32b 10240 /* Linker relaxations happens from one of the
b38cadfb 10241 R_ARM_{GOTDESC,CALL,DESCSEQ} relocations to IE or LE. */
0855e32b 10242 if (ELF32_R_TYPE(rel->r_info) != r_type)
b38cadfb 10243 tls_type = GOT_TLS_IE;
0855e32b
NS		 10244
10245 BFD_ASSERT (tls_type != GOT_UNKNOWN);
ba93b8ac
DJ		 10246
10247 if ((off & 1) != 0)
10248 off &= ~1;
10249 else
10250 {
10251 bfd_boolean need_relocs = FALSE;
10252 Elf_Internal_Rela outrel;
ba93b8ac
DJ		 10253 int cur_off = off;
10254
10255 /* The GOT entries have not been initialized yet. Do it
10256 now, and emit any relocations. If both an IE GOT and a
10257 GD GOT are necessary, we emit the GD first. */
10258
0e1862bb 10259 if ((bfd_link_pic (info) || indx != 0)
ba93b8ac
DJ		 10260 && (h == NULL
10261 || ELF_ST_VISIBILITY (h->other) == STV_DEFAULT
10262 || h->root.type != bfd_link_hash_undefweak))
10263 {
10264 need_relocs = TRUE;
0855e32b 10265 BFD_ASSERT (srelgot != NULL);
ba93b8ac
DJ		 10266 }
10267
0855e32b
NS		 10268 if (tls_type & GOT_TLS_GDESC)
10269 {
47beaa6a
RS		 10270 bfd_byte *loc;
10271
0855e32b
NS		 10272 /* We should have relaxed, unless this is an undefined
10273 weak symbol. */
10274 BFD_ASSERT ((h && (h->root.type == bfd_link_hash_undefweak))
0e1862bb 10275 || bfd_link_pic (info));
0855e32b 10276 BFD_ASSERT (globals->sgotplt_jump_table_size + offplt + 8
99059e56 10277 <= globals->root.sgotplt->size);
0855e32b
NS		 10278
10279 outrel.r_addend = 0;
10280 outrel.r_offset = (globals->root.sgotplt->output_section->vma
10281 + globals->root.sgotplt->output_offset
10282 + offplt
10283 + globals->sgotplt_jump_table_size);
b38cadfb 10284
0855e32b
NS		 10285 outrel.r_info = ELF32_R_INFO (indx, R_ARM_TLS_DESC);
10286 sreloc = globals->root.srelplt;
10287 loc = sreloc->contents;
10288 loc += globals->next_tls_desc_index++ * RELOC_SIZE (globals);
10289 BFD_ASSERT (loc + RELOC_SIZE (globals)
99059e56 10290 <= sreloc->contents + sreloc->size);
0855e32b
NS		 10291
10292 SWAP_RELOC_OUT (globals) (output_bfd, &outrel, loc);
10293
10294 /* For globals, the first word in the relocation gets
10295 the relocation index and the top bit set, or zero,
10296 if we're binding now. For locals, it gets the
10297 symbol's offset in the tls section. */
99059e56 10298 bfd_put_32 (output_bfd,
0855e32b
NS		 10299 !h ? value - elf_hash_table (info)->tls_sec->vma
10300 : info->flags & DF_BIND_NOW ? 0
10301 : 0x80000000 | ELF32_R_SYM (outrel.r_info),
b38cadfb
NC		 10302 globals->root.sgotplt->contents + offplt
10303 + globals->sgotplt_jump_table_size);
10304
0855e32b 10305 /* Second word in the relocation is always zero. */
99059e56 10306 bfd_put_32 (output_bfd, 0,
b38cadfb
NC		 10307 globals->root.sgotplt->contents + offplt
10308 + globals->sgotplt_jump_table_size + 4);
0855e32b 10309 }
ba93b8ac
DJ		 10310 if (tls_type & GOT_TLS_GD)
10311 {
10312 if (need_relocs)
10313 {
00a97672 10314 outrel.r_addend = 0;
362d30a1
RS		 10315 outrel.r_offset = (sgot->output_section->vma
10316 + sgot->output_offset
00a97672 10317 + cur_off);
ba93b8ac 10318 outrel.r_info = ELF32_R_INFO (indx, R_ARM_TLS_DTPMOD32);
ba93b8ac 10319
00a97672
RS		 10320 if (globals->use_rel)
10321 bfd_put_32 (output_bfd, outrel.r_addend,
362d30a1 10322 sgot->contents + cur_off);
00a97672 10323
47beaa6a 10324 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
ba93b8ac
DJ		 10325
10326 if (indx == 0)
10327 bfd_put_32 (output_bfd, value - dtpoff_base (info),
362d30a1 10328 sgot->contents + cur_off + 4);
ba93b8ac
DJ		 10329 else
10330 {
00a97672 10331 outrel.r_addend = 0;
ba93b8ac
DJ		 10332 outrel.r_info = ELF32_R_INFO (indx,
10333 R_ARM_TLS_DTPOFF32);
10334 outrel.r_offset += 4;
00a97672
RS		 10335
10336 if (globals->use_rel)
10337 bfd_put_32 (output_bfd, outrel.r_addend,
362d30a1 10338 sgot->contents + cur_off + 4);
00a97672 10339
47beaa6a
RS		 10340 elf32_arm_add_dynreloc (output_bfd, info,
10341 srelgot, &outrel);
ba93b8ac
DJ		 10342 }
10343 }
10344 else
10345 {
10346 /* If we are not emitting relocations for a
10347 general dynamic reference, then we must be in a
10348 static link or an executable link with the
10349 symbol binding locally. Mark it as belonging
10350 to module 1, the executable. */
10351 bfd_put_32 (output_bfd, 1,
362d30a1 10352 sgot->contents + cur_off);
ba93b8ac 10353 bfd_put_32 (output_bfd, value - dtpoff_base (info),
362d30a1 10354 sgot->contents + cur_off + 4);
ba93b8ac
DJ		 10355 }
10356
10357 cur_off += 8;
10358 }
10359
10360 if (tls_type & GOT_TLS_IE)
10361 {
10362 if (need_relocs)
10363 {
00a97672
RS		 10364 if (indx == 0)
10365 outrel.r_addend = value - dtpoff_base (info);
10366 else
10367 outrel.r_addend = 0;
362d30a1
RS		 10368 outrel.r_offset = (sgot->output_section->vma
10369 + sgot->output_offset
ba93b8ac
DJ		 10370 + cur_off);
10371 outrel.r_info = ELF32_R_INFO (indx, R_ARM_TLS_TPOFF32);
10372
00a97672
RS		 10373 if (globals->use_rel)
10374 bfd_put_32 (output_bfd, outrel.r_addend,
362d30a1 10375 sgot->contents + cur_off);
ba93b8ac 10376
47beaa6a 10377 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
ba93b8ac
DJ		 10378 }
10379 else
10380 bfd_put_32 (output_bfd, tpoff (info, value),
362d30a1 10381 sgot->contents + cur_off);
ba93b8ac
DJ		 10382 cur_off += 4;
10383 }
10384
10385 if (h != NULL)
10386 h->got.offset |= 1;
10387 else
10388 local_got_offsets[r_symndx] |= 1;
10389 }
10390
10391 if ((tls_type & GOT_TLS_GD) && r_type != R_ARM_TLS_GD32)
10392 off += 8;
0855e32b
NS		 10393 else if (tls_type & GOT_TLS_GDESC)
10394 off = offplt;
10395
10396 if (ELF32_R_TYPE(rel->r_info) == R_ARM_TLS_CALL
10397 || ELF32_R_TYPE(rel->r_info) == R_ARM_THM_TLS_CALL)
10398 {
10399 bfd_signed_vma offset;
12352d3f
PB		 10400 /* TLS stubs are arm mode. The original symbol is a
10401 data object, so branch_type is bogus. */
10402 branch_type = ST_BRANCH_TO_ARM;
0855e32b 10403 enum elf32_arm_stub_type stub_type
34e77a92
RS		 10404 = arm_type_of_stub (info, input_section, rel,
10405 st_type, &branch_type,
0855e32b
NS		 10406 (struct elf32_arm_link_hash_entry *)h,
10407 globals->tls_trampoline, globals->root.splt,
10408 input_bfd, sym_name);
10409
10410 if (stub_type != arm_stub_none)
10411 {
10412 struct elf32_arm_stub_hash_entry *stub_entry
10413 = elf32_arm_get_stub_entry
10414 (input_section, globals->root.splt, 0, rel,
10415 globals, stub_type);
10416 offset = (stub_entry->stub_offset
10417 + stub_entry->stub_sec->output_offset
10418 + stub_entry->stub_sec->output_section->vma);
10419 }
10420 else
10421 offset = (globals->root.splt->output_section->vma
10422 + globals->root.splt->output_offset
10423 + globals->tls_trampoline);
10424
10425 if (ELF32_R_TYPE(rel->r_info) == R_ARM_TLS_CALL)
10426 {
10427 unsigned long inst;
b38cadfb
NC		 10428
10429 offset -= (input_section->output_section->vma
10430 + input_section->output_offset
10431 + rel->r_offset + 8);
0855e32b
NS		 10432
10433 inst = offset >> 2;
10434 inst &= 0x00ffffff;
10435 value = inst | (globals->use_blx ? 0xfa000000 : 0xeb000000);
10436 }
10437 else
10438 {
10439 /* Thumb blx encodes the offset in a complicated
10440 fashion. */
10441 unsigned upper_insn, lower_insn;
10442 unsigned neg;
10443
b38cadfb
NC		 10444 offset -= (input_section->output_section->vma
10445 + input_section->output_offset
0855e32b 10446 + rel->r_offset + 4);
b38cadfb 10447
12352d3f
PB		 10448 if (stub_type != arm_stub_none
10449 && arm_stub_is_thumb (stub_type))
10450 {
10451 lower_insn = 0xd000;
10452 }
10453 else
10454 {
10455 lower_insn = 0xc000;
6a631e86 10456 /* Round up the offset to a word boundary. */
12352d3f
PB		 10457 offset = (offset + 2) & ~2;
10458 }
10459
0855e32b
NS		 10460 neg = offset < 0;
10461 upper_insn = (0xf000
10462 | ((offset >> 12) & 0x3ff)
10463 | (neg << 10));
12352d3f 10464 lower_insn |= (((!((offset >> 23) & 1)) ^ neg) << 13)
0855e32b 10465 | (((!((offset >> 22) & 1)) ^ neg) << 11)
12352d3f 10466 | ((offset >> 1) & 0x7ff);
0855e32b
NS		 10467 bfd_put_16 (input_bfd, upper_insn, hit_data);
10468 bfd_put_16 (input_bfd, lower_insn, hit_data + 2);
10469 return bfd_reloc_ok;
10470 }
10471 }
10472 /* These relocations needs special care, as besides the fact
10473 they point somewhere in .gotplt, the addend must be
10474 adjusted accordingly depending on the type of instruction
6a631e86 10475 we refer to. */
0855e32b
NS		 10476 else if ((r_type == R_ARM_TLS_GOTDESC) && (tls_type & GOT_TLS_GDESC))
10477 {
10478 unsigned long data, insn;
10479 unsigned thumb;
b38cadfb 10480
0855e32b
NS		 10481 data = bfd_get_32 (input_bfd, hit_data);
10482 thumb = data & 1;
10483 data &= ~1u;
b38cadfb 10484
0855e32b
NS		 10485 if (thumb)
10486 {
10487 insn = bfd_get_16 (input_bfd, contents + rel->r_offset - data);
10488 if ((insn & 0xf000) == 0xf000 || (insn & 0xf800) == 0xe800)
10489 insn = (insn << 16)
10490 | bfd_get_16 (input_bfd,
10491 contents + rel->r_offset - data + 2);
10492 if ((insn & 0xf800c000) == 0xf000c000)
10493 /* bl/blx */
10494 value = -6;
10495 else if ((insn & 0xffffff00) == 0x4400)
10496 /* add */
10497 value = -5;
10498 else
10499 {
10500 (*_bfd_error_handler)
10501 (_("%B(%A+0x%lx):unexpected Thumb instruction '0x%x' referenced by TLS_GOTDESC"),
10502 input_bfd, input_section,
10503 (unsigned long)rel->r_offset, insn);
10504 return bfd_reloc_notsupported;
10505 }
10506 }
10507 else
10508 {
10509 insn = bfd_get_32 (input_bfd, contents + rel->r_offset - data);
10510
10511 switch (insn >> 24)
10512 {
10513 case 0xeb: /* bl */
10514 case 0xfa: /* blx */
10515 value = -4;
10516 break;
10517
10518 case 0xe0: /* add */
10519 value = -8;
10520 break;
b38cadfb 10521
0855e32b
NS		 10522 default:
10523 (*_bfd_error_handler)
10524 (_("%B(%A+0x%lx):unexpected ARM instruction '0x%x' referenced by TLS_GOTDESC"),
10525 input_bfd, input_section,
10526 (unsigned long)rel->r_offset, insn);
10527 return bfd_reloc_notsupported;
10528 }
10529 }
b38cadfb 10530
0855e32b
NS		 10531 value += ((globals->root.sgotplt->output_section->vma
10532 + globals->root.sgotplt->output_offset + off)
10533 - (input_section->output_section->vma
10534 + input_section->output_offset
10535 + rel->r_offset)
10536 + globals->sgotplt_jump_table_size);
10537 }
10538 else
10539 value = ((globals->root.sgot->output_section->vma
10540 + globals->root.sgot->output_offset + off)
10541 - (input_section->output_section->vma
10542 + input_section->output_offset + rel->r_offset));
ba93b8ac
DJ		 10543
10544 return _bfd_final_link_relocate (howto, input_bfd, input_section,
10545 contents, rel->r_offset, value,
00a97672 10546 rel->r_addend);
ba93b8ac
DJ		 10547 }
10548
10549 case R_ARM_TLS_LE32:
3cbc1e5e 10550 if (bfd_link_dll (info))
ba93b8ac
DJ		 10551 {
10552 (*_bfd_error_handler)
10553 (_("%B(%A+0x%lx): R_ARM_TLS_LE32 relocation not permitted in shared object"),
10554 input_bfd, input_section,
10555 (long) rel->r_offset, howto->name);
46691134 10556 return bfd_reloc_notsupported;
ba93b8ac
DJ		 10557 }
10558 else
10559 value = tpoff (info, value);
906e58ca 10560
ba93b8ac 10561 return _bfd_final_link_relocate (howto, input_bfd, input_section,
00a97672
RS		 10562 contents, rel->r_offset, value,
10563 rel->r_addend);
ba93b8ac 10564
319850b4
JB		 10565 case R_ARM_V4BX:
10566 if (globals->fix_v4bx)
845b51d6
PB		 10567 {
10568 bfd_vma insn = bfd_get_32 (input_bfd, hit_data);
319850b4 10569
845b51d6
PB		 10570 /* Ensure that we have a BX instruction. */
10571 BFD_ASSERT ((insn & 0x0ffffff0) == 0x012fff10);
319850b4 10572
845b51d6
PB		 10573 if (globals->fix_v4bx == 2 && (insn & 0xf) != 0xf)
10574 {
10575 /* Branch to veneer. */
10576 bfd_vma glue_addr;
10577 glue_addr = elf32_arm_bx_glue (info, insn & 0xf);
10578 glue_addr -= input_section->output_section->vma
10579 + input_section->output_offset
10580 + rel->r_offset + 8;
10581 insn = (insn & 0xf0000000) | 0x0a000000
10582 | ((glue_addr >> 2) & 0x00ffffff);
10583 }
10584 else
10585 {
10586 /* Preserve Rm (lowest four bits) and the condition code
10587 (highest four bits). Other bits encode MOV PC,Rm. */
10588 insn = (insn & 0xf000000f) | 0x01a0f000;
10589 }
319850b4 10590
845b51d6
PB		 10591 bfd_put_32 (input_bfd, insn, hit_data);
10592 }
319850b4
JB		 10593 return bfd_reloc_ok;
10594
b6895b4f
PB		 10595 case R_ARM_MOVW_ABS_NC:
10596 case R_ARM_MOVT_ABS:
10597 case R_ARM_MOVW_PREL_NC:
10598 case R_ARM_MOVT_PREL:
92f5d02b
MS		 10599 /* Until we properly support segment-base-relative addressing then
10600 we assume the segment base to be zero, as for the group relocations.
10601 Thus R_ARM_MOVW_BREL_NC has the same semantics as R_ARM_MOVW_ABS_NC
10602 and R_ARM_MOVT_BREL has the same semantics as R_ARM_MOVT_ABS. */
10603 case R_ARM_MOVW_BREL_NC:
10604 case R_ARM_MOVW_BREL:
10605 case R_ARM_MOVT_BREL:
b6895b4f
PB		 10606 {
10607 bfd_vma insn = bfd_get_32 (input_bfd, hit_data);
10608
10609 if (globals->use_rel)
10610 {
10611 addend = ((insn >> 4) & 0xf000) | (insn & 0xfff);
39623e12 10612 signed_addend = (addend ^ 0x8000) - 0x8000;
b6895b4f 10613 }
92f5d02b 10614
b6895b4f 10615 value += signed_addend;
b6895b4f
PB		 10616
10617 if (r_type == R_ARM_MOVW_PREL_NC || r_type == R_ARM_MOVT_PREL)
10618 value -= (input_section->output_section->vma
10619 + input_section->output_offset + rel->r_offset);
10620
92f5d02b 10621 if (r_type == R_ARM_MOVW_BREL && value >= 0x10000)
99059e56 10622 return bfd_reloc_overflow;
92f5d02b 10623
35fc36a8 10624 if (branch_type == ST_BRANCH_TO_THUMB)
92f5d02b
MS		 10625 value |= 1;
10626
10627 if (r_type == R_ARM_MOVT_ABS || r_type == R_ARM_MOVT_PREL
99059e56 10628 || r_type == R_ARM_MOVT_BREL)
b6895b4f
PB		 10629 value >>= 16;
10630
10631 insn &= 0xfff0f000;
10632 insn |= value & 0xfff;
10633 insn |= (value & 0xf000) << 4;
10634 bfd_put_32 (input_bfd, insn, hit_data);
10635 }
10636 return bfd_reloc_ok;
10637
10638 case R_ARM_THM_MOVW_ABS_NC:
10639 case R_ARM_THM_MOVT_ABS:
10640 case R_ARM_THM_MOVW_PREL_NC:
10641 case R_ARM_THM_MOVT_PREL:
92f5d02b
MS		 10642 /* Until we properly support segment-base-relative addressing then
10643 we assume the segment base to be zero, as for the above relocations.
10644 Thus R_ARM_THM_MOVW_BREL_NC has the same semantics as
10645 R_ARM_THM_MOVW_ABS_NC and R_ARM_THM_MOVT_BREL has the same semantics
10646 as R_ARM_THM_MOVT_ABS. */
10647 case R_ARM_THM_MOVW_BREL_NC:
10648 case R_ARM_THM_MOVW_BREL:
10649 case R_ARM_THM_MOVT_BREL:
b6895b4f
PB		 10650 {
10651 bfd_vma insn;
906e58ca 10652
b6895b4f
PB		 10653 insn = bfd_get_16 (input_bfd, hit_data) << 16;
10654 insn |= bfd_get_16 (input_bfd, hit_data + 2);
10655
10656 if (globals->use_rel)
10657 {
10658 addend = ((insn >> 4) & 0xf000)
10659 | ((insn >> 15) & 0x0800)
10660 | ((insn >> 4) & 0x0700)
10661 | (insn & 0x00ff);
39623e12 10662 signed_addend = (addend ^ 0x8000) - 0x8000;
b6895b4f 10663 }
92f5d02b 10664
b6895b4f 10665 value += signed_addend;
b6895b4f
PB		 10666
10667 if (r_type == R_ARM_THM_MOVW_PREL_NC || r_type == R_ARM_THM_MOVT_PREL)
10668 value -= (input_section->output_section->vma
10669 + input_section->output_offset + rel->r_offset);
10670
92f5d02b 10671 if (r_type == R_ARM_THM_MOVW_BREL && value >= 0x10000)
99059e56 10672 return bfd_reloc_overflow;
92f5d02b 10673
35fc36a8 10674 if (branch_type == ST_BRANCH_TO_THUMB)
92f5d02b
MS		 10675 value |= 1;
10676
10677 if (r_type == R_ARM_THM_MOVT_ABS || r_type == R_ARM_THM_MOVT_PREL
99059e56 10678 || r_type == R_ARM_THM_MOVT_BREL)
b6895b4f
PB		 10679 value >>= 16;
10680
10681 insn &= 0xfbf08f00;
10682 insn |= (value & 0xf000) << 4;
10683 insn |= (value & 0x0800) << 15;
10684 insn |= (value & 0x0700) << 4;
10685 insn |= (value & 0x00ff);
10686
10687 bfd_put_16 (input_bfd, insn >> 16, hit_data);
10688 bfd_put_16 (input_bfd, insn & 0xffff, hit_data + 2);
10689 }
10690 return bfd_reloc_ok;
10691
4962c51a
MS		 10692 case R_ARM_ALU_PC_G0_NC:
10693 case R_ARM_ALU_PC_G1_NC:
10694 case R_ARM_ALU_PC_G0:
10695 case R_ARM_ALU_PC_G1:
10696 case R_ARM_ALU_PC_G2:
10697 case R_ARM_ALU_SB_G0_NC:
10698 case R_ARM_ALU_SB_G1_NC:
10699 case R_ARM_ALU_SB_G0:
10700 case R_ARM_ALU_SB_G1:
10701 case R_ARM_ALU_SB_G2:
10702 {
10703 bfd_vma insn = bfd_get_32 (input_bfd, hit_data);
99059e56 10704 bfd_vma pc = input_section->output_section->vma
4962c51a 10705 + input_section->output_offset + rel->r_offset;
31a91d61 10706 /* sb is the origin of the *segment* containing the symbol. */
62c34db3 10707 bfd_vma sb = sym_sec ? sym_sec->output_section->vma : 0;
99059e56
RM		 10708 bfd_vma residual;
10709 bfd_vma g_n;
4962c51a 10710 bfd_signed_vma signed_value;
99059e56
RM		 10711 int group = 0;
10712
10713 /* Determine which group of bits to select. */
10714 switch (r_type)
10715 {
10716 case R_ARM_ALU_PC_G0_NC:
10717 case R_ARM_ALU_PC_G0:
10718 case R_ARM_ALU_SB_G0_NC:
10719 case R_ARM_ALU_SB_G0:
10720 group = 0;
10721 break;
10722
10723 case R_ARM_ALU_PC_G1_NC:
10724 case R_ARM_ALU_PC_G1:
10725 case R_ARM_ALU_SB_G1_NC:
10726 case R_ARM_ALU_SB_G1:
10727 group = 1;
10728 break;
10729
10730 case R_ARM_ALU_PC_G2:
10731 case R_ARM_ALU_SB_G2:
10732 group = 2;
10733 break;
10734
10735 default:
10736 abort ();
10737 }
10738
10739 /* If REL, extract the addend from the insn. If RELA, it will
10740 have already been fetched for us. */
4962c51a 10741 if (globals->use_rel)
99059e56
RM		 10742 {
10743 int negative;
10744 bfd_vma constant = insn & 0xff;
10745 bfd_vma rotation = (insn & 0xf00) >> 8;
10746
10747 if (rotation == 0)
10748 signed_addend = constant;
10749 else
10750 {
10751 /* Compensate for the fact that in the instruction, the
10752 rotation is stored in multiples of 2 bits. */
10753 rotation *= 2;
10754
10755 /* Rotate "constant" right by "rotation" bits. */
10756 signed_addend = (constant >> rotation) |
10757 (constant << (8 * sizeof (bfd_vma) - rotation));
10758 }
10759
10760 /* Determine if the instruction is an ADD or a SUB.
10761 (For REL, this determines the sign of the addend.) */
10762 negative = identify_add_or_sub (insn);
10763 if (negative == 0)
10764 {
10765 (*_bfd_error_handler)
10766 (_("%B(%A+0x%lx): Only ADD or SUB instructions are allowed for ALU group relocations"),
10767 input_bfd, input_section,
10768 (long) rel->r_offset, howto->name);
10769 return bfd_reloc_overflow;
10770 }
10771
10772 signed_addend *= negative;
10773 }
4962c51a
MS		 10774
10775 /* Compute the value (X) to go in the place. */
99059e56
RM		 10776 if (r_type == R_ARM_ALU_PC_G0_NC
10777 || r_type == R_ARM_ALU_PC_G1_NC
10778 || r_type == R_ARM_ALU_PC_G0
10779 || r_type == R_ARM_ALU_PC_G1
10780 || r_type == R_ARM_ALU_PC_G2)
10781 /* PC relative. */
10782 signed_value = value - pc + signed_addend;
10783 else
10784 /* Section base relative. */
10785 signed_value = value - sb + signed_addend;
10786
10787 /* If the target symbol is a Thumb function, then set the
10788 Thumb bit in the address. */
35fc36a8 10789 if (branch_type == ST_BRANCH_TO_THUMB)
4962c51a
MS		 10790 signed_value |= 1;
10791
99059e56
RM		 10792 /* Calculate the value of the relevant G_n, in encoded
10793 constant-with-rotation format. */
b6518b38
NC		 10794 g_n = calculate_group_reloc_mask (signed_value < 0 ? - signed_value : signed_value,
10795 group, &residual);
99059e56
RM		 10796
10797 /* Check for overflow if required. */
10798 if ((r_type == R_ARM_ALU_PC_G0
10799 || r_type == R_ARM_ALU_PC_G1
10800 || r_type == R_ARM_ALU_PC_G2
10801 || r_type == R_ARM_ALU_SB_G0
10802 || r_type == R_ARM_ALU_SB_G1
10803 || r_type == R_ARM_ALU_SB_G2) && residual != 0)
10804 {
10805 (*_bfd_error_handler)
10806 (_("%B(%A+0x%lx): Overflow whilst splitting 0x%lx for group relocation %s"),
10807 input_bfd, input_section,
b6518b38
NC		 10808 (long) rel->r_offset, signed_value < 0 ? - signed_value : signed_value,
10809 howto->name);
99059e56
RM		 10810 return bfd_reloc_overflow;
10811 }
10812
10813 /* Mask out the value and the ADD/SUB part of the opcode; take care
10814 not to destroy the S bit. */
10815 insn &= 0xff1ff000;
10816
10817 /* Set the opcode according to whether the value to go in the
10818 place is negative. */
10819 if (signed_value < 0)
10820 insn |= 1 << 22;
10821 else
10822 insn |= 1 << 23;
10823
10824 /* Encode the offset. */
10825 insn |= g_n;
4962c51a
MS		 10826
10827 bfd_put_32 (input_bfd, insn, hit_data);
10828 }
10829 return bfd_reloc_ok;
10830
10831 case R_ARM_LDR_PC_G0:
10832 case R_ARM_LDR_PC_G1:
10833 case R_ARM_LDR_PC_G2:
10834 case R_ARM_LDR_SB_G0:
10835 case R_ARM_LDR_SB_G1:
10836 case R_ARM_LDR_SB_G2:
10837 {
10838 bfd_vma insn = bfd_get_32 (input_bfd, hit_data);
99059e56 10839 bfd_vma pc = input_section->output_section->vma
4962c51a 10840 + input_section->output_offset + rel->r_offset;
31a91d61 10841 /* sb is the origin of the *segment* containing the symbol. */
62c34db3 10842 bfd_vma sb = sym_sec ? sym_sec->output_section->vma : 0;
99059e56 10843 bfd_vma residual;
4962c51a 10844 bfd_signed_vma signed_value;
99059e56
RM		 10845 int group = 0;
10846
10847 /* Determine which groups of bits to calculate. */
10848 switch (r_type)
10849 {
10850 case R_ARM_LDR_PC_G0:
10851 case R_ARM_LDR_SB_G0:
10852 group = 0;
10853 break;
10854
10855 case R_ARM_LDR_PC_G1:
10856 case R_ARM_LDR_SB_G1:
10857 group = 1;
10858 break;
10859
10860 case R_ARM_LDR_PC_G2:
10861 case R_ARM_LDR_SB_G2:
10862 group = 2;
10863 break;
10864
10865 default:
10866 abort ();
10867 }
10868
10869 /* If REL, extract the addend from the insn. If RELA, it will
10870 have already been fetched for us. */
4962c51a 10871 if (globals->use_rel)
99059e56
RM		 10872 {
10873 int negative = (insn & (1 << 23)) ? 1 : -1;
10874 signed_addend = negative * (insn & 0xfff);
10875 }
4962c51a
MS		 10876
10877 /* Compute the value (X) to go in the place. */
99059e56
RM		 10878 if (r_type == R_ARM_LDR_PC_G0
10879 || r_type == R_ARM_LDR_PC_G1
10880 || r_type == R_ARM_LDR_PC_G2)
10881 /* PC relative. */
10882 signed_value = value - pc + signed_addend;
10883 else
10884 /* Section base relative. */
10885 signed_value = value - sb + signed_addend;
10886
10887 /* Calculate the value of the relevant G_{n-1} to obtain
10888 the residual at that stage. */
b6518b38
NC		 10889 calculate_group_reloc_mask (signed_value < 0 ? - signed_value : signed_value,
10890 group - 1, &residual);
99059e56
RM		 10891
10892 /* Check for overflow. */
10893 if (residual >= 0x1000)
10894 {
10895 (*_bfd_error_handler)
10896 (_("%B(%A+0x%lx): Overflow whilst splitting 0x%lx for group relocation %s"),
b6518b38
NC		 10897 input_bfd, input_section,
10898 (long) rel->r_offset, labs (signed_value), howto->name);
99059e56
RM		 10899 return bfd_reloc_overflow;
10900 }
10901
10902 /* Mask out the value and U bit. */
10903 insn &= 0xff7ff000;
10904
10905 /* Set the U bit if the value to go in the place is non-negative. */
10906 if (signed_value >= 0)
10907 insn |= 1 << 23;
10908
10909 /* Encode the offset. */
10910 insn |= residual;
4962c51a
MS		 10911
10912 bfd_put_32 (input_bfd, insn, hit_data);
10913 }
10914 return bfd_reloc_ok;
10915
10916 case R_ARM_LDRS_PC_G0:
10917 case R_ARM_LDRS_PC_G1:
10918 case R_ARM_LDRS_PC_G2:
10919 case R_ARM_LDRS_SB_G0:
10920 case R_ARM_LDRS_SB_G1:
10921 case R_ARM_LDRS_SB_G2:
10922 {
10923 bfd_vma insn = bfd_get_32 (input_bfd, hit_data);
99059e56 10924 bfd_vma pc = input_section->output_section->vma
4962c51a 10925 + input_section->output_offset + rel->r_offset;
31a91d61 10926 /* sb is the origin of the *segment* containing the symbol. */
62c34db3 10927 bfd_vma sb = sym_sec ? sym_sec->output_section->vma : 0;
99059e56 10928 bfd_vma residual;
4962c51a 10929 bfd_signed_vma signed_value;
99059e56
RM		 10930 int group = 0;
10931
10932 /* Determine which groups of bits to calculate. */
10933 switch (r_type)
10934 {
10935 case R_ARM_LDRS_PC_G0:
10936 case R_ARM_LDRS_SB_G0:
10937 group = 0;
10938 break;
10939
10940 case R_ARM_LDRS_PC_G1:
10941 case R_ARM_LDRS_SB_G1:
10942 group = 1;
10943 break;
10944
10945 case R_ARM_LDRS_PC_G2:
10946 case R_ARM_LDRS_SB_G2:
10947 group = 2;
10948 break;
10949
10950 default:
10951 abort ();
10952 }
10953
10954 /* If REL, extract the addend from the insn. If RELA, it will
10955 have already been fetched for us. */
4962c51a 10956 if (globals->use_rel)
99059e56
RM		 10957 {
10958 int negative = (insn & (1 << 23)) ? 1 : -1;
10959 signed_addend = negative * (((insn & 0xf00) >> 4) + (insn & 0xf));
10960 }
4962c51a
MS		 10961
10962 /* Compute the value (X) to go in the place. */
99059e56
RM		 10963 if (r_type == R_ARM_LDRS_PC_G0
10964 || r_type == R_ARM_LDRS_PC_G1
10965 || r_type == R_ARM_LDRS_PC_G2)
10966 /* PC relative. */
10967 signed_value = value - pc + signed_addend;
10968 else
10969 /* Section base relative. */
10970 signed_value = value - sb + signed_addend;
10971
10972 /* Calculate the value of the relevant G_{n-1} to obtain
10973 the residual at that stage. */
b6518b38
NC		 10974 calculate_group_reloc_mask (signed_value < 0 ? - signed_value : signed_value,
10975 group - 1, &residual);
99059e56
RM		 10976
10977 /* Check for overflow. */
10978 if (residual >= 0x100)
10979 {
10980 (*_bfd_error_handler)
10981 (_("%B(%A+0x%lx): Overflow whilst splitting 0x%lx for group relocation %s"),
b6518b38
NC		 10982 input_bfd, input_section,
10983 (long) rel->r_offset, labs (signed_value), howto->name);
99059e56
RM		 10984 return bfd_reloc_overflow;
10985 }
10986
10987 /* Mask out the value and U bit. */
10988 insn &= 0xff7ff0f0;
10989
10990 /* Set the U bit if the value to go in the place is non-negative. */
10991 if (signed_value >= 0)
10992 insn |= 1 << 23;
10993
10994 /* Encode the offset. */
10995 insn |= ((residual & 0xf0) << 4) | (residual & 0xf);
4962c51a
MS		 10996
10997 bfd_put_32 (input_bfd, insn, hit_data);
10998 }
10999 return bfd_reloc_ok;
11000
11001 case R_ARM_LDC_PC_G0:
11002 case R_ARM_LDC_PC_G1:
11003 case R_ARM_LDC_PC_G2:
11004 case R_ARM_LDC_SB_G0:
11005 case R_ARM_LDC_SB_G1:
11006 case R_ARM_LDC_SB_G2:
11007 {
11008 bfd_vma insn = bfd_get_32 (input_bfd, hit_data);
99059e56 11009 bfd_vma pc = input_section->output_section->vma
4962c51a 11010 + input_section->output_offset + rel->r_offset;
31a91d61 11011 /* sb is the origin of the *segment* containing the symbol. */
62c34db3 11012 bfd_vma sb = sym_sec ? sym_sec->output_section->vma : 0;
99059e56 11013 bfd_vma residual;
4962c51a 11014 bfd_signed_vma signed_value;
99059e56
RM		 11015 int group = 0;
11016
11017 /* Determine which groups of bits to calculate. */
11018 switch (r_type)
11019 {
11020 case R_ARM_LDC_PC_G0:
11021 case R_ARM_LDC_SB_G0:
11022 group = 0;
11023 break;
11024
11025 case R_ARM_LDC_PC_G1:
11026 case R_ARM_LDC_SB_G1:
11027 group = 1;
11028 break;
11029
11030 case R_ARM_LDC_PC_G2:
11031 case R_ARM_LDC_SB_G2:
11032 group = 2;
11033 break;
11034
11035 default:
11036 abort ();
11037 }
11038
11039 /* If REL, extract the addend from the insn. If RELA, it will
11040 have already been fetched for us. */
4962c51a 11041 if (globals->use_rel)
99059e56
RM		 11042 {
11043 int negative = (insn & (1 << 23)) ? 1 : -1;
11044 signed_addend = negative * ((insn & 0xff) << 2);
11045 }
4962c51a
MS		 11046
11047 /* Compute the value (X) to go in the place. */
99059e56
RM		 11048 if (r_type == R_ARM_LDC_PC_G0
11049 || r_type == R_ARM_LDC_PC_G1
11050 || r_type == R_ARM_LDC_PC_G2)
11051 /* PC relative. */
11052 signed_value = value - pc + signed_addend;
11053 else
11054 /* Section base relative. */
11055 signed_value = value - sb + signed_addend;
11056
11057 /* Calculate the value of the relevant G_{n-1} to obtain
11058 the residual at that stage. */
b6518b38
NC		 11059 calculate_group_reloc_mask (signed_value < 0 ? - signed_value : signed_value,
11060 group - 1, &residual);
99059e56
RM		 11061
11062 /* Check for overflow. (The absolute value to go in the place must be
11063 divisible by four and, after having been divided by four, must
11064 fit in eight bits.) */
11065 if ((residual & 0x3) != 0 || residual >= 0x400)
11066 {
11067 (*_bfd_error_handler)
11068 (_("%B(%A+0x%lx): Overflow whilst splitting 0x%lx for group relocation %s"),
11069 input_bfd, input_section,
b6518b38 11070 (long) rel->r_offset, labs (signed_value), howto->name);
99059e56
RM		 11071 return bfd_reloc_overflow;
11072 }
11073
11074 /* Mask out the value and U bit. */
11075 insn &= 0xff7fff00;
11076
11077 /* Set the U bit if the value to go in the place is non-negative. */
11078 if (signed_value >= 0)
11079 insn |= 1 << 23;
11080
11081 /* Encode the offset. */
11082 insn |= residual >> 2;
4962c51a
MS		 11083
11084 bfd_put_32 (input_bfd, insn, hit_data);
11085 }
11086 return bfd_reloc_ok;
11087
72d98d16
MG		 11088 case R_ARM_THM_ALU_ABS_G0_NC:
11089 case R_ARM_THM_ALU_ABS_G1_NC:
11090 case R_ARM_THM_ALU_ABS_G2_NC:
11091 case R_ARM_THM_ALU_ABS_G3_NC:
11092 {
11093 const int shift_array[4] = {0, 8, 16, 24};
11094 bfd_vma insn = bfd_get_16 (input_bfd, hit_data);
11095 bfd_vma addr = value;
11096 int shift = shift_array[r_type - R_ARM_THM_ALU_ABS_G0_NC];
11097
11098 /* Compute address. */
11099 if (globals->use_rel)
11100 signed_addend = insn & 0xff;
11101 addr += signed_addend;
11102 if (branch_type == ST_BRANCH_TO_THUMB)
11103 addr |= 1;
11104 /* Clean imm8 insn. */
11105 insn &= 0xff00;
11106 /* And update with correct part of address. */
11107 insn |= (addr >> shift) & 0xff;
11108 /* Update insn. */
11109 bfd_put_16 (input_bfd, insn, hit_data);
11110 }
11111
11112 *unresolved_reloc_p = FALSE;
11113 return bfd_reloc_ok;
11114
252b5132
RH		 11115 default:
11116 return bfd_reloc_notsupported;
11117 }
11118}
11119
98c1d4aa
NC		 11120/* Add INCREMENT to the reloc (of type HOWTO) at ADDRESS. */
11121static void
57e8b36a
NC		 11122arm_add_to_rel (bfd * abfd,
11123 bfd_byte * address,
11124 reloc_howto_type * howto,
11125 bfd_signed_vma increment)
98c1d4aa 11126{
98c1d4aa
NC		 11127 bfd_signed_vma addend;
11128
bd97cb95
DJ		 11129 if (howto->type == R_ARM_THM_CALL
11130 || howto->type == R_ARM_THM_JUMP24)
98c1d4aa 11131 {
9a5aca8c
AM		 11132 int upper_insn, lower_insn;
11133 int upper, lower;
98c1d4aa 11134
9a5aca8c
AM		 11135 upper_insn = bfd_get_16 (abfd, address);
11136 lower_insn = bfd_get_16 (abfd, address + 2);
11137 upper = upper_insn & 0x7ff;
11138 lower = lower_insn & 0x7ff;
11139
11140 addend = (upper << 12) | (lower << 1);
ddda4409 11141 addend += increment;
9a5aca8c 11142 addend >>= 1;
98c1d4aa 11143
9a5aca8c
AM		 11144 upper_insn = (upper_insn & 0xf800) | ((addend >> 11) & 0x7ff);
11145 lower_insn = (lower_insn & 0xf800) | (addend & 0x7ff);
11146
dc810e39
AM		 11147 bfd_put_16 (abfd, (bfd_vma) upper_insn, address);
11148 bfd_put_16 (abfd, (bfd_vma) lower_insn, address + 2);
9a5aca8c
AM		 11149 }
11150 else
11151 {
11152 bfd_vma contents;
11153
11154 contents = bfd_get_32 (abfd, address);
11155
11156 /* Get the (signed) value from the instruction. */
11157 addend = contents & howto->src_mask;
11158 if (addend & ((howto->src_mask + 1) >> 1))
11159 {
11160 bfd_signed_vma mask;
11161
11162 mask = -1;
11163 mask &= ~ howto->src_mask;
11164 addend |= mask;
11165 }
11166
11167 /* Add in the increment, (which is a byte value). */
11168 switch (howto->type)
11169 {
11170 default:
11171 addend += increment;
11172 break;
11173
11174 case R_ARM_PC24:
c6596c5e 11175 case R_ARM_PLT32:
5b5bb741
PB		 11176 case R_ARM_CALL:
11177 case R_ARM_JUMP24:
9a5aca8c 11178 addend <<= howto->size;
dc810e39 11179 addend += increment;
9a5aca8c
AM		 11180
11181 /* Should we check for overflow here ? */
11182
11183 /* Drop any undesired bits. */
11184 addend >>= howto->rightshift;
11185 break;
11186 }
11187
11188 contents = (contents & ~ howto->dst_mask) | (addend & howto->dst_mask);
11189
11190 bfd_put_32 (abfd, contents, address);
ddda4409 11191 }
98c1d4aa 11192}
252b5132 11193
ba93b8ac
DJ		 11194#define IS_ARM_TLS_RELOC(R_TYPE) \
11195 ((R_TYPE) == R_ARM_TLS_GD32 \
11196 || (R_TYPE) == R_ARM_TLS_LDO32 \
11197 || (R_TYPE) == R_ARM_TLS_LDM32 \
11198 || (R_TYPE) == R_ARM_TLS_DTPOFF32 \
11199 || (R_TYPE) == R_ARM_TLS_DTPMOD32 \
11200 || (R_TYPE) == R_ARM_TLS_TPOFF32 \
11201 || (R_TYPE) == R_ARM_TLS_LE32 \
0855e32b
NS		 11202 || (R_TYPE) == R_ARM_TLS_IE32 \
11203 || IS_ARM_TLS_GNU_RELOC (R_TYPE))
11204
11205/* Specific set of relocations for the gnu tls dialect. */
11206#define IS_ARM_TLS_GNU_RELOC(R_TYPE) \
11207 ((R_TYPE) == R_ARM_TLS_GOTDESC \
11208 || (R_TYPE) == R_ARM_TLS_CALL \
11209 || (R_TYPE) == R_ARM_THM_TLS_CALL \
11210 || (R_TYPE) == R_ARM_TLS_DESCSEQ \
11211 || (R_TYPE) == R_ARM_THM_TLS_DESCSEQ)
ba93b8ac 11212
252b5132 11213/* Relocate an ARM ELF section. */
906e58ca 11214
b34976b6 11215static bfd_boolean
57e8b36a
NC		 11216elf32_arm_relocate_section (bfd * output_bfd,
11217 struct bfd_link_info * info,
11218 bfd * input_bfd,
11219 asection * input_section,
11220 bfd_byte * contents,
11221 Elf_Internal_Rela * relocs,
11222 Elf_Internal_Sym * local_syms,
11223 asection ** local_sections)
252b5132 11224{
b34976b6
AM		 11225 Elf_Internal_Shdr *symtab_hdr;
11226 struct elf_link_hash_entry **sym_hashes;
11227 Elf_Internal_Rela *rel;
11228 Elf_Internal_Rela *relend;
11229 const char *name;
b32d3aa2 11230 struct elf32_arm_link_hash_table * globals;
252b5132 11231
4e7fd91e 11232 globals = elf32_arm_hash_table (info);
4dfe6ac6
NC		 11233 if (globals == NULL)
11234 return FALSE;
b491616a 11235
0ffa91dd 11236 symtab_hdr = & elf_symtab_hdr (input_bfd);
252b5132
RH		 11237 sym_hashes = elf_sym_hashes (input_bfd);
11238
11239 rel = relocs;
11240 relend = relocs + input_section->reloc_count;
11241 for (; rel < relend; rel++)
11242 {
ba96a88f
NC		 11243 int r_type;
11244 reloc_howto_type * howto;
11245 unsigned long r_symndx;
11246 Elf_Internal_Sym * sym;
11247 asection * sec;
252b5132 11248 struct elf_link_hash_entry * h;
ba96a88f
NC		 11249 bfd_vma relocation;
11250 bfd_reloc_status_type r;
11251 arelent bfd_reloc;
ba93b8ac 11252 char sym_type;
0945cdfd 11253 bfd_boolean unresolved_reloc = FALSE;
f2a9dd69 11254 char *error_message = NULL;
f21f3fe0 11255
252b5132 11256 r_symndx = ELF32_R_SYM (rel->r_info);
ba96a88f 11257 r_type = ELF32_R_TYPE (rel->r_info);
b32d3aa2 11258 r_type = arm_real_reloc_type (globals, r_type);
252b5132 11259
ba96a88f 11260 if ( r_type == R_ARM_GNU_VTENTRY
99059e56
RM		 11261 || r_type == R_ARM_GNU_VTINHERIT)
11262 continue;
252b5132 11263
b32d3aa2 11264 bfd_reloc.howto = elf32_arm_howto_from_type (r_type);
ba96a88f 11265 howto = bfd_reloc.howto;
252b5132 11266
252b5132
RH		 11267 h = NULL;
11268 sym = NULL;
11269 sec = NULL;
9b485d32 11270
252b5132
RH		 11271 if (r_symndx < symtab_hdr->sh_info)
11272 {
11273 sym = local_syms + r_symndx;
ba93b8ac 11274 sym_type = ELF32_ST_TYPE (sym->st_info);
252b5132 11275 sec = local_sections[r_symndx];
ffcb4889
NS		 11276
11277 /* An object file might have a reference to a local
11278 undefined symbol. This is a daft object file, but we
11279 should at least do something about it. V4BX & NONE
11280 relocations do not use the symbol and are explicitly
77b4f08f
TS		 11281 allowed to use the undefined symbol, so allow those.
11282 Likewise for relocations against STN_UNDEF. */
ffcb4889
NS		 11283 if (r_type != R_ARM_V4BX
11284 && r_type != R_ARM_NONE
77b4f08f 11285 && r_symndx != STN_UNDEF
ffcb4889
NS		 11286 && bfd_is_und_section (sec)
11287 && ELF_ST_BIND (sym->st_info) != STB_WEAK)
11288 {
11289 if (!info->callbacks->undefined_symbol
11290 (info, bfd_elf_string_from_elf_section
11291 (input_bfd, symtab_hdr->sh_link, sym->st_name),
11292 input_bfd, input_section,
11293 rel->r_offset, TRUE))
11294 return FALSE;
11295 }
b38cadfb 11296
4e7fd91e 11297 if (globals->use_rel)
f8df10f4 11298 {
4e7fd91e
PB		 11299 relocation = (sec->output_section->vma
11300 + sec->output_offset
11301 + sym->st_value);
0e1862bb 11302 if (!bfd_link_relocatable (info)
ab96bf03
AM		 11303 && (sec->flags & SEC_MERGE)
11304 && ELF_ST_TYPE (sym->st_info) == STT_SECTION)
f8df10f4 11305 {
4e7fd91e
PB		 11306 asection *msec;
11307 bfd_vma addend, value;
11308
39623e12 11309 switch (r_type)
4e7fd91e 11310 {
39623e12
PB		 11311 case R_ARM_MOVW_ABS_NC:
11312 case R_ARM_MOVT_ABS:
11313 value = bfd_get_32 (input_bfd, contents + rel->r_offset);
11314 addend = ((value & 0xf0000) >> 4) | (value & 0xfff);
11315 addend = (addend ^ 0x8000) - 0x8000;
11316 break;
f8df10f4 11317
39623e12
PB		 11318 case R_ARM_THM_MOVW_ABS_NC:
11319 case R_ARM_THM_MOVT_ABS:
11320 value = bfd_get_16 (input_bfd, contents + rel->r_offset)
11321 << 16;
11322 value |= bfd_get_16 (input_bfd,
11323 contents + rel->r_offset + 2);
11324 addend = ((value & 0xf7000) >> 4) | (value & 0xff)
11325 | ((value & 0x04000000) >> 15);
11326 addend = (addend ^ 0x8000) - 0x8000;
11327 break;
f8df10f4 11328
39623e12
PB		 11329 default:
11330 if (howto->rightshift
11331 || (howto->src_mask & (howto->src_mask + 1)))
11332 {
11333 (*_bfd_error_handler)
11334 (_("%B(%A+0x%lx): %s relocation against SEC_MERGE section"),
11335 input_bfd, input_section,
11336 (long) rel->r_offset, howto->name);
11337 return FALSE;
11338 }
11339
11340 value = bfd_get_32 (input_bfd, contents + rel->r_offset);
11341
11342 /* Get the (signed) value from the instruction. */
11343 addend = value & howto->src_mask;
11344 if (addend & ((howto->src_mask + 1) >> 1))
11345 {
11346 bfd_signed_vma mask;
11347
11348 mask = -1;
11349 mask &= ~ howto->src_mask;
11350 addend |= mask;
11351 }
11352 break;
4e7fd91e 11353 }
39623e12 11354
4e7fd91e
PB		 11355 msec = sec;
11356 addend =
11357 _bfd_elf_rel_local_sym (output_bfd, sym, &msec, addend)
11358 - relocation;
11359 addend += msec->output_section->vma + msec->output_offset;
39623e12 11360
cc643b88 11361 /* Cases here must match those in the preceding
39623e12
PB		 11362 switch statement. */
11363 switch (r_type)
11364 {
11365 case R_ARM_MOVW_ABS_NC:
11366 case R_ARM_MOVT_ABS:
11367 value = (value & 0xfff0f000) | ((addend & 0xf000) << 4)
11368 | (addend & 0xfff);
11369 bfd_put_32 (input_bfd, value, contents + rel->r_offset);
11370 break;
11371
11372 case R_ARM_THM_MOVW_ABS_NC:
11373 case R_ARM_THM_MOVT_ABS:
11374 value = (value & 0xfbf08f00) | ((addend & 0xf700) << 4)
11375 | (addend & 0xff) | ((addend & 0x0800) << 15);
11376 bfd_put_16 (input_bfd, value >> 16,
11377 contents + rel->r_offset);
11378 bfd_put_16 (input_bfd, value,
11379 contents + rel->r_offset + 2);
11380 break;
11381
11382 default:
11383 value = (value & ~ howto->dst_mask)
11384 | (addend & howto->dst_mask);
11385 bfd_put_32 (input_bfd, value, contents + rel->r_offset);
11386 break;
11387 }
f8df10f4 11388 }
f8df10f4 11389 }
4e7fd91e
PB		 11390 else
11391 relocation = _bfd_elf_rela_local_sym (output_bfd, sym, &sec, rel);
252b5132
RH		 11392 }
11393 else
11394 {
62d887d4 11395 bfd_boolean warned, ignored;
560e09e9 11396
b2a8e766
AM		 11397 RELOC_FOR_GLOBAL_SYMBOL (info, input_bfd, input_section, rel,
11398 r_symndx, symtab_hdr, sym_hashes,
11399 h, sec, relocation,
62d887d4 11400 unresolved_reloc, warned, ignored);
ba93b8ac
DJ		 11401
11402 sym_type = h->type;
252b5132
RH		 11403 }
11404
dbaa2011 11405 if (sec != NULL && discarded_section (sec))
e4067dbb 11406 RELOC_AGAINST_DISCARDED_SECTION (info, input_bfd, input_section,
545fd46b 11407 rel, 1, relend, howto, 0, contents);
ab96bf03 11408
0e1862bb 11409 if (bfd_link_relocatable (info))
ab96bf03
AM		 11410 {
11411 /* This is a relocatable link. We don't have to change
11412 anything, unless the reloc is against a section symbol,
11413 in which case we have to adjust according to where the
11414 section symbol winds up in the output section. */
11415 if (sym != NULL && ELF_ST_TYPE (sym->st_info) == STT_SECTION)
11416 {
11417 if (globals->use_rel)
11418 arm_add_to_rel (input_bfd, contents + rel->r_offset,
11419 howto, (bfd_signed_vma) sec->output_offset);
11420 else
11421 rel->r_addend += sec->output_offset;
11422 }
11423 continue;
11424 }
11425
252b5132
RH		 11426 if (h != NULL)
11427 name = h->root.root.string;
11428 else
11429 {
11430 name = (bfd_elf_string_from_elf_section
11431 (input_bfd, symtab_hdr->sh_link, sym->st_name));
11432 if (name == NULL || *name == '\0')
11433 name = bfd_section_name (input_bfd, sec);
11434 }
f21f3fe0 11435
cf35638d 11436 if (r_symndx != STN_UNDEF
ba93b8ac
DJ		 11437 && r_type != R_ARM_NONE
11438 && (h == NULL
11439 || h->root.type == bfd_link_hash_defined
11440 || h->root.type == bfd_link_hash_defweak)
11441 && IS_ARM_TLS_RELOC (r_type) != (sym_type == STT_TLS))
11442 {
11443 (*_bfd_error_handler)
11444 ((sym_type == STT_TLS
11445 ? _("%B(%A+0x%lx): %s used with TLS symbol %s")
11446 : _("%B(%A+0x%lx): %s used with non-TLS symbol %s")),
11447 input_bfd,
11448 input_section,
11449 (long) rel->r_offset,
11450 howto->name,
11451 name);
11452 }
11453
0855e32b 11454 /* We call elf32_arm_final_link_relocate unless we're completely
99059e56
RM		 11455 done, i.e., the relaxation produced the final output we want,
11456 and we won't let anybody mess with it. Also, we have to do
11457 addend adjustments in case of a R_ARM_TLS_GOTDESC relocation
6a631e86 11458 both in relaxed and non-relaxed cases. */
0855e32b
NS		 11459 if ((elf32_arm_tls_transition (info, r_type, h) != (unsigned)r_type)
11460 || (IS_ARM_TLS_GNU_RELOC (r_type)
b38cadfb 11461 && !((h ? elf32_arm_hash_entry (h)->tls_type :
0855e32b
NS		 11462 elf32_arm_local_got_tls_type (input_bfd)[r_symndx])
11463 & GOT_TLS_GDESC)))
11464 {
11465 r = elf32_arm_tls_relax (globals, input_bfd, input_section,
11466 contents, rel, h == NULL);
11467 /* This may have been marked unresolved because it came from
11468 a shared library. But we've just dealt with that. */
11469 unresolved_reloc = 0;
11470 }
11471 else
11472 r = bfd_reloc_continue;
b38cadfb 11473
0855e32b
NS		 11474 if (r == bfd_reloc_continue)
11475 r = elf32_arm_final_link_relocate (howto, input_bfd, output_bfd,
11476 input_section, contents, rel,
34e77a92 11477 relocation, info, sec, name, sym_type,
35fc36a8
RS		 11478 (h ? h->target_internal
11479 : ARM_SYM_BRANCH_TYPE (sym)), h,
0855e32b 11480 &unresolved_reloc, &error_message);
0945cdfd
DJ		 11481
11482 /* Dynamic relocs are not propagated for SEC_DEBUGGING sections
11483 because such sections are not SEC_ALLOC and thus ld.so will
11484 not process them. */
11485 if (unresolved_reloc
99059e56
RM		 11486 && !((input_section->flags & SEC_DEBUGGING) != 0
11487 && h->def_dynamic)
1d5316ab
AM		 11488 && _bfd_elf_section_offset (output_bfd, info, input_section,
11489 rel->r_offset) != (bfd_vma) -1)
0945cdfd
DJ		 11490 {
11491 (*_bfd_error_handler)
843fe662
L		 11492 (_("%B(%A+0x%lx): unresolvable %s relocation against symbol `%s'"),
11493 input_bfd,
11494 input_section,
11495 (long) rel->r_offset,
11496 howto->name,
11497 h->root.root.string);
0945cdfd
DJ		 11498 return FALSE;
11499 }
252b5132
RH		 11500
11501 if (r != bfd_reloc_ok)
11502 {
252b5132
RH		 11503 switch (r)
11504 {
11505 case bfd_reloc_overflow:
cf919dfd
PB		 11506 /* If the overflowing reloc was to an undefined symbol,
11507 we have already printed one error message and there
11508 is no point complaining again. */
11509 if ((! h ||
11510 h->root.type != bfd_link_hash_undefined)
11511 && (!((*info->callbacks->reloc_overflow)
dfeffb9f
L		 11512 (info, (h ? &h->root : NULL), name, howto->name,
11513 (bfd_vma) 0, input_bfd, input_section,
11514 rel->r_offset))))
b34976b6 11515 return FALSE;
252b5132
RH		 11516 break;
11517
11518 case bfd_reloc_undefined:
11519 if (!((*info->callbacks->undefined_symbol)
11520 (info, name, input_bfd, input_section,
b34976b6
AM		 11521 rel->r_offset, TRUE)))
11522 return FALSE;
252b5132
RH		 11523 break;
11524
11525 case bfd_reloc_outofrange:
f2a9dd69 11526 error_message = _("out of range");
252b5132
RH		 11527 goto common_error;
11528
11529 case bfd_reloc_notsupported:
f2a9dd69 11530 error_message = _("unsupported relocation");
252b5132
RH		 11531 goto common_error;
11532
11533 case bfd_reloc_dangerous:
f2a9dd69 11534 /* error_message should already be set. */
252b5132
RH		 11535 goto common_error;
11536
11537 default:
f2a9dd69 11538 error_message = _("unknown error");
8029a119 11539 /* Fall through. */
252b5132
RH		 11540
11541 common_error:
f2a9dd69
DJ		 11542 BFD_ASSERT (error_message != NULL);
11543 if (!((*info->callbacks->reloc_dangerous)
11544 (info, error_message, input_bfd, input_section,
252b5132 11545 rel->r_offset)))
b34976b6 11546 return FALSE;
252b5132
RH		 11547 break;
11548 }
11549 }
11550 }
11551
b34976b6 11552 return TRUE;
252b5132
RH		 11553}
11554
91d6fa6a 11555/* Add a new unwind edit to the list described by HEAD, TAIL. If TINDEX is zero,
2468f9c9 11556 adds the edit to the start of the list. (The list must be built in order of
91d6fa6a 11557 ascending TINDEX: the function's callers are primarily responsible for
2468f9c9
PB		 11558 maintaining that condition). */
11559
11560static void
11561add_unwind_table_edit (arm_unwind_table_edit **head,
11562 arm_unwind_table_edit **tail,
11563 arm_unwind_edit_type type,
11564 asection *linked_section,
91d6fa6a 11565 unsigned int tindex)
2468f9c9 11566{
21d799b5
NC		 11567 arm_unwind_table_edit *new_edit = (arm_unwind_table_edit *)
11568 xmalloc (sizeof (arm_unwind_table_edit));
b38cadfb 11569
2468f9c9
PB		 11570 new_edit->type = type;
11571 new_edit->linked_section = linked_section;
91d6fa6a 11572 new_edit->index = tindex;
b38cadfb 11573
91d6fa6a 11574 if (tindex > 0)
2468f9c9
PB		 11575 {
11576 new_edit->next = NULL;
11577
11578 if (*tail)
11579 (*tail)->next = new_edit;
11580
11581 (*tail) = new_edit;
11582
11583 if (!*head)
11584 (*head) = new_edit;
11585 }
11586 else
11587 {
11588 new_edit->next = *head;
11589
11590 if (!*tail)
11591 *tail = new_edit;
11592
11593 *head = new_edit;
11594 }
11595}
11596
11597static _arm_elf_section_data *get_arm_elf_section_data (asection *);
11598
11599/* Increase the size of EXIDX_SEC by ADJUST bytes. ADJUST mau be negative. */
11600static void
11601adjust_exidx_size(asection *exidx_sec, int adjust)
11602{
11603 asection *out_sec;
11604
11605 if (!exidx_sec->rawsize)
11606 exidx_sec->rawsize = exidx_sec->size;
11607
11608 bfd_set_section_size (exidx_sec->owner, exidx_sec, exidx_sec->size + adjust);
11609 out_sec = exidx_sec->output_section;
11610 /* Adjust size of output section. */
11611 bfd_set_section_size (out_sec->owner, out_sec, out_sec->size +adjust);
11612}
11613
11614/* Insert an EXIDX_CANTUNWIND marker at the end of a section. */
11615static void
11616insert_cantunwind_after(asection *text_sec, asection *exidx_sec)
11617{
11618 struct _arm_elf_section_data *exidx_arm_data;
11619
11620 exidx_arm_data = get_arm_elf_section_data (exidx_sec);
11621 add_unwind_table_edit (
11622 &exidx_arm_data->u.exidx.unwind_edit_list,
11623 &exidx_arm_data->u.exidx.unwind_edit_tail,
11624 INSERT_EXIDX_CANTUNWIND_AT_END, text_sec, UINT_MAX);
11625
491d01d3
YU		 11626 exidx_arm_data->additional_reloc_count++;
11627
2468f9c9
PB		 11628 adjust_exidx_size(exidx_sec, 8);
11629}
11630
11631/* Scan .ARM.exidx tables, and create a list describing edits which should be
11632 made to those tables, such that:
b38cadfb 11633
2468f9c9
PB		 11634 1. Regions without unwind data are marked with EXIDX_CANTUNWIND entries.
11635 2. Duplicate entries are merged together (EXIDX_CANTUNWIND, or unwind
99059e56 11636 codes which have been inlined into the index).
2468f9c9 11637
85fdf906
AH		 11638 If MERGE_EXIDX_ENTRIES is false, duplicate entries are not merged.
11639
2468f9c9 11640 The edits are applied when the tables are written
b38cadfb 11641 (in elf32_arm_write_section). */
2468f9c9
PB		 11642
11643bfd_boolean
11644elf32_arm_fix_exidx_coverage (asection **text_section_order,
11645 unsigned int num_text_sections,
85fdf906
AH		 11646 struct bfd_link_info *info,
11647 bfd_boolean merge_exidx_entries)
2468f9c9
PB		 11648{
11649 bfd *inp;
11650 unsigned int last_second_word = 0, i;
11651 asection *last_exidx_sec = NULL;
11652 asection *last_text_sec = NULL;
11653 int last_unwind_type = -1;
11654
11655 /* Walk over all EXIDX sections, and create backlinks from the corrsponding
11656 text sections. */
c72f2fb2 11657 for (inp = info->input_bfds; inp != NULL; inp = inp->link.next)
2468f9c9
PB		 11658 {
11659 asection *sec;
b38cadfb 11660
2468f9c9 11661 for (sec = inp->sections; sec != NULL; sec = sec->next)
99059e56 11662 {
2468f9c9
PB		 11663 struct bfd_elf_section_data *elf_sec = elf_section_data (sec);
11664 Elf_Internal_Shdr *hdr = &elf_sec->this_hdr;
b38cadfb 11665
dec9d5df 11666 if (!hdr || hdr->sh_type != SHT_ARM_EXIDX)
2468f9c9 11667 continue;
b38cadfb 11668
2468f9c9
PB		 11669 if (elf_sec->linked_to)
11670 {
11671 Elf_Internal_Shdr *linked_hdr
99059e56 11672 = &elf_section_data (elf_sec->linked_to)->this_hdr;
2468f9c9 11673 struct _arm_elf_section_data *linked_sec_arm_data
99059e56 11674 = get_arm_elf_section_data (linked_hdr->bfd_section);
2468f9c9
PB		 11675
11676 if (linked_sec_arm_data == NULL)
99059e56 11677 continue;
2468f9c9
PB		 11678
11679 /* Link this .ARM.exidx section back from the text section it
99059e56 11680 describes. */
2468f9c9
PB		 11681 linked_sec_arm_data->u.text.arm_exidx_sec = sec;
11682 }
11683 }
11684 }
11685
11686 /* Walk all text sections in order of increasing VMA. Eilminate duplicate
11687 index table entries (EXIDX_CANTUNWIND and inlined unwind opcodes),
91d6fa6a 11688 and add EXIDX_CANTUNWIND entries for sections with no unwind table data. */
2468f9c9
PB		 11689
11690 for (i = 0; i < num_text_sections; i++)
11691 {
11692 asection *sec = text_section_order[i];
11693 asection *exidx_sec;
11694 struct _arm_elf_section_data *arm_data = get_arm_elf_section_data (sec);
11695 struct _arm_elf_section_data *exidx_arm_data;
11696 bfd_byte *contents = NULL;
11697 int deleted_exidx_bytes = 0;
11698 bfd_vma j;
11699 arm_unwind_table_edit *unwind_edit_head = NULL;
11700 arm_unwind_table_edit *unwind_edit_tail = NULL;
11701 Elf_Internal_Shdr *hdr;
11702 bfd *ibfd;
11703
11704 if (arm_data == NULL)
99059e56 11705 continue;
2468f9c9
PB		 11706
11707 exidx_sec = arm_data->u.text.arm_exidx_sec;
11708 if (exidx_sec == NULL)
11709 {
11710 /* Section has no unwind data. */
11711 if (last_unwind_type == 0 || !last_exidx_sec)
11712 continue;
11713
11714 /* Ignore zero sized sections. */
11715 if (sec->size == 0)
11716 continue;
11717
11718 insert_cantunwind_after(last_text_sec, last_exidx_sec);
11719 last_unwind_type = 0;
11720 continue;
11721 }
11722
22a8f80e
PB		 11723 /* Skip /DISCARD/ sections. */
11724 if (bfd_is_abs_section (exidx_sec->output_section))
11725 continue;
11726
2468f9c9
PB		 11727 hdr = &elf_section_data (exidx_sec)->this_hdr;
11728 if (hdr->sh_type != SHT_ARM_EXIDX)
99059e56 11729 continue;
b38cadfb 11730
2468f9c9
PB		 11731 exidx_arm_data = get_arm_elf_section_data (exidx_sec);
11732 if (exidx_arm_data == NULL)
99059e56 11733 continue;
b38cadfb 11734
2468f9c9 11735 ibfd = exidx_sec->owner;
b38cadfb 11736
2468f9c9
PB		 11737 if (hdr->contents != NULL)
11738 contents = hdr->contents;
11739 else if (! bfd_malloc_and_get_section (ibfd, exidx_sec, &contents))
11740 /* An error? */
11741 continue;
11742
ac06903d
YU		 11743 if (last_unwind_type > 0)
11744 {
11745 unsigned int first_word = bfd_get_32 (ibfd, contents);
11746 /* Add cantunwind if first unwind item does not match section
11747 start. */
11748 if (first_word != sec->vma)
11749 {
11750 insert_cantunwind_after (last_text_sec, last_exidx_sec);
11751 last_unwind_type = 0;
11752 }
11753 }
11754
2468f9c9
PB		 11755 for (j = 0; j < hdr->sh_size; j += 8)
11756 {
11757 unsigned int second_word = bfd_get_32 (ibfd, contents + j + 4);
11758 int unwind_type;
11759 int elide = 0;
11760
11761 /* An EXIDX_CANTUNWIND entry. */
11762 if (second_word == 1)
11763 {
11764 if (last_unwind_type == 0)
11765 elide = 1;
11766 unwind_type = 0;
11767 }
11768 /* Inlined unwinding data. Merge if equal to previous. */
11769 else if ((second_word & 0x80000000) != 0)
11770 {
85fdf906
AH		 11771 if (merge_exidx_entries
11772 && last_second_word == second_word && last_unwind_type == 1)
2468f9c9
PB		 11773 elide = 1;
11774 unwind_type = 1;
11775 last_second_word = second_word;
11776 }
11777 /* Normal table entry. In theory we could merge these too,
11778 but duplicate entries are likely to be much less common. */
11779 else
11780 unwind_type = 2;
11781
491d01d3 11782 if (elide && !bfd_link_relocatable (info))
2468f9c9
PB		 11783 {
11784 add_unwind_table_edit (&unwind_edit_head, &unwind_edit_tail,
11785 DELETE_EXIDX_ENTRY, NULL, j / 8);
11786
11787 deleted_exidx_bytes += 8;
11788 }
11789
11790 last_unwind_type = unwind_type;
11791 }
11792
11793 /* Free contents if we allocated it ourselves. */
11794 if (contents != hdr->contents)
99059e56 11795 free (contents);
2468f9c9
PB		 11796
11797 /* Record edits to be applied later (in elf32_arm_write_section). */
11798 exidx_arm_data->u.exidx.unwind_edit_list = unwind_edit_head;
11799 exidx_arm_data->u.exidx.unwind_edit_tail = unwind_edit_tail;
b38cadfb 11800
2468f9c9
PB		 11801 if (deleted_exidx_bytes > 0)
11802 adjust_exidx_size(exidx_sec, -deleted_exidx_bytes);
11803
11804 last_exidx_sec = exidx_sec;
11805 last_text_sec = sec;
11806 }
11807
11808 /* Add terminating CANTUNWIND entry. */
491d01d3
YU		 11809 if (!bfd_link_relocatable (info) && last_exidx_sec
11810 && last_unwind_type != 0)
2468f9c9
PB		 11811 insert_cantunwind_after(last_text_sec, last_exidx_sec);
11812
11813 return TRUE;
11814}
11815
3e6b1042
DJ		 11816static bfd_boolean
11817elf32_arm_output_glue_section (struct bfd_link_info *info, bfd *obfd,
11818 bfd *ibfd, const char *name)
11819{
11820 asection *sec, *osec;
11821
3d4d4302 11822 sec = bfd_get_linker_section (ibfd, name);
3e6b1042
DJ		 11823 if (sec == NULL || (sec->flags & SEC_EXCLUDE) != 0)
11824 return TRUE;
11825
11826 osec = sec->output_section;
11827 if (elf32_arm_write_section (obfd, info, sec, sec->contents))
11828 return TRUE;
11829
11830 if (! bfd_set_section_contents (obfd, osec, sec->contents,
11831 sec->output_offset, sec->size))
11832 return FALSE;
11833
11834 return TRUE;
11835}
11836
11837static bfd_boolean
11838elf32_arm_final_link (bfd *abfd, struct bfd_link_info *info)
11839{
11840 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (info);
fe33d2fa 11841 asection *sec, *osec;
3e6b1042 11842
4dfe6ac6
NC		 11843 if (globals == NULL)
11844 return FALSE;
11845
3e6b1042
DJ		 11846 /* Invoke the regular ELF backend linker to do all the work. */
11847 if (!bfd_elf_final_link (abfd, info))
11848 return FALSE;
11849
fe33d2fa
CL		 11850 /* Process stub sections (eg BE8 encoding, ...). */
11851 struct elf32_arm_link_hash_table *htab = elf32_arm_hash_table (info);
7292b3ac 11852 unsigned int i;
cdb21a0a
NS		 11853 for (i=0; i<htab->top_id; i++)
11854 {
11855 sec = htab->stub_group[i].stub_sec;
11856 /* Only process it once, in its link_sec slot. */
11857 if (sec && i == htab->stub_group[i].link_sec->id)
11858 {
11859 osec = sec->output_section;
11860 elf32_arm_write_section (abfd, info, sec, sec->contents);
11861 if (! bfd_set_section_contents (abfd, osec, sec->contents,
11862 sec->output_offset, sec->size))
11863 return FALSE;
11864 }
fe33d2fa 11865 }
fe33d2fa 11866
3e6b1042
DJ		 11867 /* Write out any glue sections now that we have created all the
11868 stubs. */
11869 if (globals->bfd_of_glue_owner != NULL)
11870 {
11871 if (! elf32_arm_output_glue_section (info, abfd,
11872 globals->bfd_of_glue_owner,
11873 ARM2THUMB_GLUE_SECTION_NAME))
11874 return FALSE;
11875
11876 if (! elf32_arm_output_glue_section (info, abfd,
11877 globals->bfd_of_glue_owner,
11878 THUMB2ARM_GLUE_SECTION_NAME))
11879 return FALSE;
11880
11881 if (! elf32_arm_output_glue_section (info, abfd,
11882 globals->bfd_of_glue_owner,
11883 VFP11_ERRATUM_VENEER_SECTION_NAME))
11884 return FALSE;
11885
a504d23a
LA		 11886 if (! elf32_arm_output_glue_section (info, abfd,
11887 globals->bfd_of_glue_owner,
11888 STM32L4XX_ERRATUM_VENEER_SECTION_NAME))
11889 return FALSE;
11890
3e6b1042
DJ		 11891 if (! elf32_arm_output_glue_section (info, abfd,
11892 globals->bfd_of_glue_owner,
11893 ARM_BX_GLUE_SECTION_NAME))
11894 return FALSE;
11895 }
11896
11897 return TRUE;
11898}
11899
5968a7b8
NC		 11900/* Return a best guess for the machine number based on the attributes. */
11901
11902static unsigned int
11903bfd_arm_get_mach_from_attributes (bfd * abfd)
11904{
11905 int arch = bfd_elf_get_obj_attr_int (abfd, OBJ_ATTR_PROC, Tag_CPU_arch);
11906
11907 switch (arch)
11908 {
11909 case TAG_CPU_ARCH_V4: return bfd_mach_arm_4;
11910 case TAG_CPU_ARCH_V4T: return bfd_mach_arm_4T;
11911 case TAG_CPU_ARCH_V5T: return bfd_mach_arm_5T;
11912
11913 case TAG_CPU_ARCH_V5TE:
11914 {
11915 char * name;
11916
11917 BFD_ASSERT (Tag_CPU_name < NUM_KNOWN_OBJ_ATTRIBUTES);
11918 name = elf_known_obj_attributes (abfd) [OBJ_ATTR_PROC][Tag_CPU_name].s;
11919
11920 if (name)
11921 {
11922 if (strcmp (name, "IWMMXT2") == 0)
11923 return bfd_mach_arm_iWMMXt2;
11924
11925 if (strcmp (name, "IWMMXT") == 0)
6034aab8 11926 return bfd_mach_arm_iWMMXt;
088ca6c1
NC		 11927
11928 if (strcmp (name, "XSCALE") == 0)
11929 {
11930 int wmmx;
11931
11932 BFD_ASSERT (Tag_WMMX_arch < NUM_KNOWN_OBJ_ATTRIBUTES);
11933 wmmx = elf_known_obj_attributes (abfd) [OBJ_ATTR_PROC][Tag_WMMX_arch].i;
11934 switch (wmmx)
11935 {
11936 case 1: return bfd_mach_arm_iWMMXt;
11937 case 2: return bfd_mach_arm_iWMMXt2;
11938 default: return bfd_mach_arm_XScale;
11939 }
11940 }
5968a7b8
NC		 11941 }
11942
11943 return bfd_mach_arm_5TE;
11944 }
11945
11946 default:
11947 return bfd_mach_arm_unknown;
11948 }
11949}
11950
c178919b
NC		 11951/* Set the right machine number. */
11952
11953static bfd_boolean
57e8b36a 11954elf32_arm_object_p (bfd *abfd)
c178919b 11955{
5a6c6817 11956 unsigned int mach;
57e8b36a 11957
5a6c6817 11958 mach = bfd_arm_get_mach_from_notes (abfd, ARM_NOTE_SECTION);
c178919b 11959
5968a7b8
NC		 11960 if (mach == bfd_mach_arm_unknown)
11961 {
11962 if (elf_elfheader (abfd)->e_flags & EF_ARM_MAVERICK_FLOAT)
11963 mach = bfd_mach_arm_ep9312;
11964 else
11965 mach = bfd_arm_get_mach_from_attributes (abfd);
11966 }
c178919b 11967
5968a7b8 11968 bfd_default_set_arch_mach (abfd, bfd_arch_arm, mach);
c178919b
NC		 11969 return TRUE;
11970}
11971
fc830a83 11972/* Function to keep ARM specific flags in the ELF header. */
3c9458e9 11973
b34976b6 11974static bfd_boolean
57e8b36a 11975elf32_arm_set_private_flags (bfd *abfd, flagword flags)
252b5132
RH		 11976{
11977 if (elf_flags_init (abfd)
11978 && elf_elfheader (abfd)->e_flags != flags)
11979 {
fc830a83
NC		 11980 if (EF_ARM_EABI_VERSION (flags) == EF_ARM_EABI_UNKNOWN)
11981 {
fd2ec330 11982 if (flags & EF_ARM_INTERWORK)
d003868e
AM		 11983 (*_bfd_error_handler)
11984 (_("Warning: Not setting interworking flag of %B since it has already been specified as non-interworking"),
11985 abfd);
fc830a83 11986 else
d003868e
AM		 11987 _bfd_error_handler
11988 (_("Warning: Clearing the interworking flag of %B due to outside request"),
11989 abfd);
fc830a83 11990 }
252b5132
RH		 11991 }
11992 else
11993 {
11994 elf_elfheader (abfd)->e_flags = flags;
b34976b6 11995 elf_flags_init (abfd) = TRUE;
252b5132
RH		 11996 }
11997
b34976b6 11998 return TRUE;
252b5132
RH		 11999}
12000
fc830a83 12001/* Copy backend specific data from one object module to another. */
9b485d32 12002
b34976b6 12003static bfd_boolean
57e8b36a 12004elf32_arm_copy_private_bfd_data (bfd *ibfd, bfd *obfd)
252b5132
RH		 12005{
12006 flagword in_flags;
12007 flagword out_flags;
12008
0ffa91dd 12009 if (! is_arm_elf (ibfd) || ! is_arm_elf (obfd))
b34976b6 12010 return TRUE;
252b5132 12011
fc830a83 12012 in_flags = elf_elfheader (ibfd)->e_flags;
252b5132
RH		 12013 out_flags = elf_elfheader (obfd)->e_flags;
12014
fc830a83
NC		 12015 if (elf_flags_init (obfd)
12016 && EF_ARM_EABI_VERSION (out_flags) == EF_ARM_EABI_UNKNOWN
12017 && in_flags != out_flags)
252b5132 12018 {
252b5132 12019 /* Cannot mix APCS26 and APCS32 code. */
fd2ec330 12020 if ((in_flags & EF_ARM_APCS_26) != (out_flags & EF_ARM_APCS_26))
b34976b6 12021 return FALSE;
252b5132
RH		 12022
12023 /* Cannot mix float APCS and non-float APCS code. */
fd2ec330 12024 if ((in_flags & EF_ARM_APCS_FLOAT) != (out_flags & EF_ARM_APCS_FLOAT))
b34976b6 12025 return FALSE;
252b5132
RH		 12026
12027 /* If the src and dest have different interworking flags
99059e56 12028 then turn off the interworking bit. */
fd2ec330 12029 if ((in_flags & EF_ARM_INTERWORK) != (out_flags & EF_ARM_INTERWORK))
252b5132 12030 {
fd2ec330 12031 if (out_flags & EF_ARM_INTERWORK)
d003868e
AM		 12032 _bfd_error_handler
12033 (_("Warning: Clearing the interworking flag of %B because non-interworking code in %B has been linked with it"),
12034 obfd, ibfd);
252b5132 12035
fd2ec330 12036 in_flags &= ~EF_ARM_INTERWORK;
252b5132 12037 }
1006ba19
PB		 12038
12039 /* Likewise for PIC, though don't warn for this case. */
fd2ec330
PB		 12040 if ((in_flags & EF_ARM_PIC) != (out_flags & EF_ARM_PIC))
12041 in_flags &= ~EF_ARM_PIC;
252b5132
RH		 12042 }
12043
12044 elf_elfheader (obfd)->e_flags = in_flags;
b34976b6 12045 elf_flags_init (obfd) = TRUE;
252b5132 12046
e2349352 12047 return _bfd_elf_copy_private_bfd_data (ibfd, obfd);
ee065d83
PB		 12048}
12049
12050/* Values for Tag_ABI_PCS_R9_use. */
12051enum
12052{
12053 AEABI_R9_V6,
12054 AEABI_R9_SB,
12055 AEABI_R9_TLS,
12056 AEABI_R9_unused
12057};
12058
12059/* Values for Tag_ABI_PCS_RW_data. */
12060enum
12061{
12062 AEABI_PCS_RW_data_absolute,
12063 AEABI_PCS_RW_data_PCrel,
12064 AEABI_PCS_RW_data_SBrel,
12065 AEABI_PCS_RW_data_unused
12066};
12067
12068/* Values for Tag_ABI_enum_size. */
12069enum
12070{
12071 AEABI_enum_unused,
12072 AEABI_enum_short,
12073 AEABI_enum_wide,
12074 AEABI_enum_forced_wide
12075};
12076
104d59d1
JM		 12077/* Determine whether an object attribute tag takes an integer, a
12078 string or both. */
906e58ca 12079
104d59d1
JM		 12080static int
12081elf32_arm_obj_attrs_arg_type (int tag)
12082{
12083 if (tag == Tag_compatibility)
3483fe2e 12084 return ATTR_TYPE_FLAG_INT_VAL | ATTR_TYPE_FLAG_STR_VAL;
2d0bb761 12085 else if (tag == Tag_nodefaults)
3483fe2e
AS		 12086 return ATTR_TYPE_FLAG_INT_VAL | ATTR_TYPE_FLAG_NO_DEFAULT;
12087 else if (tag == Tag_CPU_raw_name || tag == Tag_CPU_name)
12088 return ATTR_TYPE_FLAG_STR_VAL;
104d59d1 12089 else if (tag < 32)
3483fe2e 12090 return ATTR_TYPE_FLAG_INT_VAL;
104d59d1 12091 else
3483fe2e 12092 return (tag & 1) != 0 ? ATTR_TYPE_FLAG_STR_VAL : ATTR_TYPE_FLAG_INT_VAL;
104d59d1
JM		 12093}
12094
5aa6ff7c
AS		 12095/* The ABI defines that Tag_conformance should be emitted first, and that
12096 Tag_nodefaults should be second (if either is defined). This sets those
12097 two positions, and bumps up the position of all the remaining tags to
12098 compensate. */
12099static int
12100elf32_arm_obj_attrs_order (int num)
12101{
3de4a297 12102 if (num == LEAST_KNOWN_OBJ_ATTRIBUTE)
5aa6ff7c 12103 return Tag_conformance;
3de4a297 12104 if (num == LEAST_KNOWN_OBJ_ATTRIBUTE + 1)
5aa6ff7c
AS		 12105 return Tag_nodefaults;
12106 if ((num - 2) < Tag_nodefaults)
12107 return num - 2;
12108 if ((num - 1) < Tag_conformance)
12109 return num - 1;
12110 return num;
12111}
12112
e8b36cd1
JM		 12113/* Attribute numbers >=64 (mod 128) can be safely ignored. */
12114static bfd_boolean
12115elf32_arm_obj_attrs_handle_unknown (bfd *abfd, int tag)
12116{
12117 if ((tag & 127) < 64)
12118 {
12119 _bfd_error_handler
12120 (_("%B: Unknown mandatory EABI object attribute %d"),
12121 abfd, tag);
12122 bfd_set_error (bfd_error_bad_value);
12123 return FALSE;
12124 }
12125 else
12126 {
12127 _bfd_error_handler
12128 (_("Warning: %B: Unknown EABI object attribute %d"),
12129 abfd, tag);
12130 return TRUE;
12131 }
12132}
12133
91e22acd
AS		 12134/* Read the architecture from the Tag_also_compatible_with attribute, if any.
12135 Returns -1 if no architecture could be read. */
12136
12137static int
12138get_secondary_compatible_arch (bfd *abfd)
12139{
12140 obj_attribute *attr =
12141 &elf_known_obj_attributes_proc (abfd)[Tag_also_compatible_with];
12142
12143 /* Note: the tag and its argument below are uleb128 values, though
12144 currently-defined values fit in one byte for each. */
12145 if (attr->s
12146 && attr->s[0] == Tag_CPU_arch
12147 && (attr->s[1] & 128) != 128
12148 && attr->s[2] == 0)
12149 return attr->s[1];
12150
12151 /* This tag is "safely ignorable", so don't complain if it looks funny. */
12152 return -1;
12153}
12154
12155/* Set, or unset, the architecture of the Tag_also_compatible_with attribute.
12156 The tag is removed if ARCH is -1. */
12157
8e79c3df 12158static void
91e22acd 12159set_secondary_compatible_arch (bfd *abfd, int arch)
8e79c3df 12160{
91e22acd
AS		 12161 obj_attribute *attr =
12162 &elf_known_obj_attributes_proc (abfd)[Tag_also_compatible_with];
8e79c3df 12163
91e22acd
AS		 12164 if (arch == -1)
12165 {
12166 attr->s = NULL;
12167 return;
8e79c3df 12168 }
91e22acd
AS		 12169
12170 /* Note: the tag and its argument below are uleb128 values, though
12171 currently-defined values fit in one byte for each. */
12172 if (!attr->s)
21d799b5 12173 attr->s = (char *) bfd_alloc (abfd, 3);
91e22acd
AS		 12174 attr->s[0] = Tag_CPU_arch;
12175 attr->s[1] = arch;
12176 attr->s[2] = '\0';
8e79c3df
CM		 12177}
12178
91e22acd
AS		 12179/* Combine two values for Tag_CPU_arch, taking secondary compatibility tags
12180 into account. */
12181
12182static int
12183tag_cpu_arch_combine (bfd *ibfd, int oldtag, int *secondary_compat_out,
12184 int newtag, int secondary_compat)
8e79c3df 12185{
91e22acd
AS		 12186#define T(X) TAG_CPU_ARCH_##X
12187 int tagl, tagh, result;
12188 const int v6t2[] =
12189 {
12190 T(V6T2), /* PRE_V4. */
12191 T(V6T2), /* V4. */
12192 T(V6T2), /* V4T. */
12193 T(V6T2), /* V5T. */
12194 T(V6T2), /* V5TE. */
12195 T(V6T2), /* V5TEJ. */
12196 T(V6T2), /* V6. */
12197 T(V7), /* V6KZ. */
12198 T(V6T2) /* V6T2. */
12199 };
12200 const int v6k[] =
12201 {
12202 T(V6K), /* PRE_V4. */
12203 T(V6K), /* V4. */
12204 T(V6K), /* V4T. */
12205 T(V6K), /* V5T. */
12206 T(V6K), /* V5TE. */
12207 T(V6K), /* V5TEJ. */
12208 T(V6K), /* V6. */
12209 T(V6KZ), /* V6KZ. */
12210 T(V7), /* V6T2. */
12211 T(V6K) /* V6K. */
12212 };
12213 const int v7[] =
12214 {
12215 T(V7), /* PRE_V4. */
12216 T(V7), /* V4. */
12217 T(V7), /* V4T. */
12218 T(V7), /* V5T. */
12219 T(V7), /* V5TE. */
12220 T(V7), /* V5TEJ. */
12221 T(V7), /* V6. */
12222 T(V7), /* V6KZ. */
12223 T(V7), /* V6T2. */
12224 T(V7), /* V6K. */
12225 T(V7) /* V7. */
12226 };
12227 const int v6_m[] =
12228 {
12229 -1, /* PRE_V4. */
12230 -1, /* V4. */
12231 T(V6K), /* V4T. */
12232 T(V6K), /* V5T. */
12233 T(V6K), /* V5TE. */
12234 T(V6K), /* V5TEJ. */
12235 T(V6K), /* V6. */
12236 T(V6KZ), /* V6KZ. */
12237 T(V7), /* V6T2. */
12238 T(V6K), /* V6K. */
12239 T(V7), /* V7. */
12240 T(V6_M) /* V6_M. */
12241 };
12242 const int v6s_m[] =
12243 {
12244 -1, /* PRE_V4. */
12245 -1, /* V4. */
12246 T(V6K), /* V4T. */
12247 T(V6K), /* V5T. */
12248 T(V6K), /* V5TE. */
12249 T(V6K), /* V5TEJ. */
12250 T(V6K), /* V6. */
12251 T(V6KZ), /* V6KZ. */
12252 T(V7), /* V6T2. */
12253 T(V6K), /* V6K. */
12254 T(V7), /* V7. */
12255 T(V6S_M), /* V6_M. */
12256 T(V6S_M) /* V6S_M. */
12257 };
9e3c6df6
PB		 12258 const int v7e_m[] =
12259 {
12260 -1, /* PRE_V4. */
12261 -1, /* V4. */
12262 T(V7E_M), /* V4T. */
12263 T(V7E_M), /* V5T. */
12264 T(V7E_M), /* V5TE. */
12265 T(V7E_M), /* V5TEJ. */
12266 T(V7E_M), /* V6. */
12267 T(V7E_M), /* V6KZ. */
12268 T(V7E_M), /* V6T2. */
12269 T(V7E_M), /* V6K. */
12270 T(V7E_M), /* V7. */
12271 T(V7E_M), /* V6_M. */
12272 T(V7E_M), /* V6S_M. */
12273 T(V7E_M) /* V7E_M. */
12274 };
bca38921
MGD		 12275 const int v8[] =
12276 {
12277 T(V8), /* PRE_V4. */
12278 T(V8), /* V4. */
12279 T(V8), /* V4T. */
12280 T(V8), /* V5T. */
12281 T(V8), /* V5TE. */
12282 T(V8), /* V5TEJ. */
12283 T(V8), /* V6. */
12284 T(V8), /* V6KZ. */
12285 T(V8), /* V6T2. */
12286 T(V8), /* V6K. */
12287 T(V8), /* V7. */
12288 T(V8), /* V6_M. */
12289 T(V8), /* V6S_M. */
12290 T(V8), /* V7E_M. */
12291 T(V8) /* V8. */
12292 };
2fd158eb
TP		 12293 const int v8m_baseline[] =
12294 {
12295 -1, /* PRE_V4. */
12296 -1, /* V4. */
12297 -1, /* V4T. */
12298 -1, /* V5T. */
12299 -1, /* V5TE. */
12300 -1, /* V5TEJ. */
12301 -1, /* V6. */
12302 -1, /* V6KZ. */
12303 -1, /* V6T2. */
12304 -1, /* V6K. */
12305 -1, /* V7. */
12306 T(V8M_BASE), /* V6_M. */
12307 T(V8M_BASE), /* V6S_M. */
12308 -1, /* V7E_M. */
12309 -1, /* V8. */
12310 -1,
12311 T(V8M_BASE) /* V8-M BASELINE. */
12312 };
12313 const int v8m_mainline[] =
12314 {
12315 -1, /* PRE_V4. */
12316 -1, /* V4. */
12317 -1, /* V4T. */
12318 -1, /* V5T. */
12319 -1, /* V5TE. */
12320 -1, /* V5TEJ. */
12321 -1, /* V6. */
12322 -1, /* V6KZ. */
12323 -1, /* V6T2. */
12324 -1, /* V6K. */
12325 T(V8M_MAIN), /* V7. */
12326 T(V8M_MAIN), /* V6_M. */
12327 T(V8M_MAIN), /* V6S_M. */
12328 T(V8M_MAIN), /* V7E_M. */
12329 -1, /* V8. */
12330 -1,
12331 T(V8M_MAIN), /* V8-M BASELINE. */
12332 T(V8M_MAIN) /* V8-M MAINLINE. */
12333 };
91e22acd
AS		 12334 const int v4t_plus_v6_m[] =
12335 {
12336 -1, /* PRE_V4. */
12337 -1, /* V4. */
12338 T(V4T), /* V4T. */
12339 T(V5T), /* V5T. */
12340 T(V5TE), /* V5TE. */
12341 T(V5TEJ), /* V5TEJ. */
12342 T(V6), /* V6. */
12343 T(V6KZ), /* V6KZ. */
12344 T(V6T2), /* V6T2. */
12345 T(V6K), /* V6K. */
12346 T(V7), /* V7. */
12347 T(V6_M), /* V6_M. */
12348 T(V6S_M), /* V6S_M. */
9e3c6df6 12349 T(V7E_M), /* V7E_M. */
bca38921 12350 T(V8), /* V8. */
4ed7ed8d 12351 -1, /* Unused. */
2fd158eb
TP		 12352 T(V8M_BASE), /* V8-M BASELINE. */
12353 T(V8M_MAIN), /* V8-M MAINLINE. */
91e22acd
AS		 12354 T(V4T_PLUS_V6_M) /* V4T plus V6_M. */
12355 };
12356 const int *comb[] =
12357 {
12358 v6t2,
12359 v6k,
12360 v7,
12361 v6_m,
12362 v6s_m,
9e3c6df6 12363 v7e_m,
bca38921 12364 v8,
4ed7ed8d 12365 NULL,
2fd158eb
TP		 12366 v8m_baseline,
12367 v8m_mainline,
91e22acd
AS		 12368 /* Pseudo-architecture. */
12369 v4t_plus_v6_m
12370 };
12371
12372 /* Check we've not got a higher architecture than we know about. */
12373
9e3c6df6 12374 if (oldtag > MAX_TAG_CPU_ARCH || newtag > MAX_TAG_CPU_ARCH)
91e22acd 12375 {
3895f852 12376 _bfd_error_handler (_("error: %B: Unknown CPU architecture"), ibfd);
91e22acd
AS		 12377 return -1;
12378 }
12379
12380 /* Override old tag if we have a Tag_also_compatible_with on the output. */
12381
12382 if ((oldtag == T(V6_M) && *secondary_compat_out == T(V4T))
12383 || (oldtag == T(V4T) && *secondary_compat_out == T(V6_M)))
12384 oldtag = T(V4T_PLUS_V6_M);
12385
12386 /* And override the new tag if we have a Tag_also_compatible_with on the
12387 input. */
12388
12389 if ((newtag == T(V6_M) && secondary_compat == T(V4T))
12390 || (newtag == T(V4T) && secondary_compat == T(V6_M)))
12391 newtag = T(V4T_PLUS_V6_M);
12392
12393 tagl = (oldtag < newtag) ? oldtag : newtag;
12394 result = tagh = (oldtag > newtag) ? oldtag : newtag;
12395
12396 /* Architectures before V6KZ add features monotonically. */
12397 if (tagh <= TAG_CPU_ARCH_V6KZ)
12398 return result;
12399
4ed7ed8d 12400 result = comb[tagh - T(V6T2)] ? comb[tagh - T(V6T2)][tagl] : -1;
91e22acd
AS		 12401
12402 /* Use Tag_CPU_arch == V4T and Tag_also_compatible_with (Tag_CPU_arch V6_M)
12403 as the canonical version. */
12404 if (result == T(V4T_PLUS_V6_M))
12405 {
12406 result = T(V4T);
12407 *secondary_compat_out = T(V6_M);
12408 }
12409 else
12410 *secondary_compat_out = -1;
12411
12412 if (result == -1)
12413 {
3895f852 12414 _bfd_error_handler (_("error: %B: Conflicting CPU architectures %d/%d"),
91e22acd
AS		 12415 ibfd, oldtag, newtag);
12416 return -1;
12417 }
12418
12419 return result;
12420#undef T
8e79c3df
CM		 12421}
12422
ac56ee8f
MGD		 12423/* Query attributes object to see if integer divide instructions may be
12424 present in an object. */
12425static bfd_boolean
12426elf32_arm_attributes_accept_div (const obj_attribute *attr)
12427{
12428 int arch = attr[Tag_CPU_arch].i;
12429 int profile = attr[Tag_CPU_arch_profile].i;
12430
12431 switch (attr[Tag_DIV_use].i)
12432 {
12433 case 0:
12434 /* Integer divide allowed if instruction contained in archetecture. */
12435 if (arch == TAG_CPU_ARCH_V7 && (profile == 'R' || profile == 'M'))
12436 return TRUE;
12437 else if (arch >= TAG_CPU_ARCH_V7E_M)
12438 return TRUE;
12439 else
12440 return FALSE;
12441
12442 case 1:
12443 /* Integer divide explicitly prohibited. */
12444 return FALSE;
12445
12446 default:
12447 /* Unrecognised case - treat as allowing divide everywhere. */
12448 case 2:
12449 /* Integer divide allowed in ARM state. */
12450 return TRUE;
12451 }
12452}
12453
12454/* Query attributes object to see if integer divide instructions are
12455 forbidden to be in the object. This is not the inverse of
12456 elf32_arm_attributes_accept_div. */
12457static bfd_boolean
12458elf32_arm_attributes_forbid_div (const obj_attribute *attr)
12459{
12460 return attr[Tag_DIV_use].i == 1;
12461}
12462
ee065d83
PB		 12463/* Merge EABI object attributes from IBFD into OBFD. Raise an error if there
12464 are conflicting attributes. */
906e58ca 12465
ee065d83
PB		 12466static bfd_boolean
12467elf32_arm_merge_eabi_attributes (bfd *ibfd, bfd *obfd)
12468{
104d59d1
JM		 12469 obj_attribute *in_attr;
12470 obj_attribute *out_attr;
ee065d83
PB		 12471 /* Some tags have 0 = don't care, 1 = strong requirement,
12472 2 = weak requirement. */
91e22acd 12473 static const int order_021[3] = {0, 2, 1};
ee065d83 12474 int i;
91e22acd 12475 bfd_boolean result = TRUE;
9274e9de 12476 const char *sec_name = get_elf_backend_data (ibfd)->obj_attrs_section;
ee065d83 12477
3e6b1042
DJ		 12478 /* Skip the linker stubs file. This preserves previous behavior
12479 of accepting unknown attributes in the first input file - but
12480 is that a bug? */
12481 if (ibfd->flags & BFD_LINKER_CREATED)
12482 return TRUE;
12483
9274e9de
TG		 12484 /* Skip any input that hasn't attribute section.
12485 This enables to link object files without attribute section with
12486 any others. */
12487 if (bfd_get_section_by_name (ibfd, sec_name) == NULL)
12488 return TRUE;
12489
104d59d1 12490 if (!elf_known_obj_attributes_proc (obfd)[0].i)
ee065d83
PB		 12491 {
12492 /* This is the first object. Copy the attributes. */
104d59d1 12493 _bfd_elf_copy_obj_attributes (ibfd, obfd);
004ae526 12494
cd21e546
MGD		 12495 out_attr = elf_known_obj_attributes_proc (obfd);
12496
004ae526
PB		 12497 /* Use the Tag_null value to indicate the attributes have been
12498 initialized. */
cd21e546 12499 out_attr[0].i = 1;
004ae526 12500
cd21e546
MGD		 12501 /* We do not output objects with Tag_MPextension_use_legacy - we move
12502 the attribute's value to Tag_MPextension_use. */
12503 if (out_attr[Tag_MPextension_use_legacy].i != 0)
12504 {
12505 if (out_attr[Tag_MPextension_use].i != 0
12506 && out_attr[Tag_MPextension_use_legacy].i
99059e56 12507 != out_attr[Tag_MPextension_use].i)
cd21e546
MGD		 12508 {
12509 _bfd_error_handler
12510 (_("Error: %B has both the current and legacy "
12511 "Tag_MPextension_use attributes"), ibfd);
12512 result = FALSE;
12513 }
12514
12515 out_attr[Tag_MPextension_use] =
12516 out_attr[Tag_MPextension_use_legacy];
12517 out_attr[Tag_MPextension_use_legacy].type = 0;
12518 out_attr[Tag_MPextension_use_legacy].i = 0;
12519 }
12520
12521 return result;
ee065d83
PB		 12522 }
12523
104d59d1
JM		 12524 in_attr = elf_known_obj_attributes_proc (ibfd);
12525 out_attr = elf_known_obj_attributes_proc (obfd);
ee065d83
PB		 12526 /* This needs to happen before Tag_ABI_FP_number_model is merged. */
12527 if (in_attr[Tag_ABI_VFP_args].i != out_attr[Tag_ABI_VFP_args].i)
12528 {
5c294fee
TG		 12529 /* Ignore mismatches if the object doesn't use floating point or is
12530 floating point ABI independent. */
12531 if (out_attr[Tag_ABI_FP_number_model].i == AEABI_FP_number_model_none
12532 || (in_attr[Tag_ABI_FP_number_model].i != AEABI_FP_number_model_none
12533 && out_attr[Tag_ABI_VFP_args].i == AEABI_VFP_args_compatible))
ee065d83 12534 out_attr[Tag_ABI_VFP_args].i = in_attr[Tag_ABI_VFP_args].i;
5c294fee
TG		 12535 else if (in_attr[Tag_ABI_FP_number_model].i != AEABI_FP_number_model_none
12536 && in_attr[Tag_ABI_VFP_args].i != AEABI_VFP_args_compatible)
ee065d83
PB		 12537 {
12538 _bfd_error_handler
3895f852 12539 (_("error: %B uses VFP register arguments, %B does not"),
deddc40b
NS		 12540 in_attr[Tag_ABI_VFP_args].i ? ibfd : obfd,
12541 in_attr[Tag_ABI_VFP_args].i ? obfd : ibfd);
91e22acd 12542 result = FALSE;
ee065d83
PB		 12543 }
12544 }
12545
3de4a297 12546 for (i = LEAST_KNOWN_OBJ_ATTRIBUTE; i < NUM_KNOWN_OBJ_ATTRIBUTES; i++)
ee065d83
PB		 12547 {
12548 /* Merge this attribute with existing attributes. */
12549 switch (i)
12550 {
12551 case Tag_CPU_raw_name:
12552 case Tag_CPU_name:
6a631e86 12553 /* These are merged after Tag_CPU_arch. */
ee065d83
PB		 12554 break;
12555
12556 case Tag_ABI_optimization_goals:
12557 case Tag_ABI_FP_optimization_goals:
12558 /* Use the first value seen. */
12559 break;
12560
12561 case Tag_CPU_arch:
91e22acd
AS		 12562 {
12563 int secondary_compat = -1, secondary_compat_out = -1;
12564 unsigned int saved_out_attr = out_attr[i].i;
70e99720
TG		 12565 int arch_attr;
12566 static const char *name_table[] =
12567 {
91e22acd
AS		 12568 /* These aren't real CPU names, but we can't guess
12569 that from the architecture version alone. */
12570 "Pre v4",
12571 "ARM v4",
12572 "ARM v4T",
12573 "ARM v5T",
12574 "ARM v5TE",
12575 "ARM v5TEJ",
12576 "ARM v6",
12577 "ARM v6KZ",
12578 "ARM v6T2",
12579 "ARM v6K",
12580 "ARM v7",
12581 "ARM v6-M",
bca38921 12582 "ARM v6S-M",
2fd158eb
TP		 12583 "ARM v8",
12584 "",
12585 "ARM v8-M.baseline",
12586 "ARM v8-M.mainline",
91e22acd
AS		 12587 };
12588
12589 /* Merge Tag_CPU_arch and Tag_also_compatible_with. */
12590 secondary_compat = get_secondary_compatible_arch (ibfd);
12591 secondary_compat_out = get_secondary_compatible_arch (obfd);
70e99720
TG		 12592 arch_attr = tag_cpu_arch_combine (ibfd, out_attr[i].i,
12593 &secondary_compat_out,
12594 in_attr[i].i,
12595 secondary_compat);
12596
12597 /* Return with error if failed to merge. */
12598 if (arch_attr == -1)
12599 return FALSE;
12600
12601 out_attr[i].i = arch_attr;
12602
91e22acd
AS		 12603 set_secondary_compatible_arch (obfd, secondary_compat_out);
12604
12605 /* Merge Tag_CPU_name and Tag_CPU_raw_name. */
12606 if (out_attr[i].i == saved_out_attr)
12607 ; /* Leave the names alone. */
12608 else if (out_attr[i].i == in_attr[i].i)
12609 {
12610 /* The output architecture has been changed to match the
12611 input architecture. Use the input names. */
12612 out_attr[Tag_CPU_name].s = in_attr[Tag_CPU_name].s
12613 ? _bfd_elf_attr_strdup (obfd, in_attr[Tag_CPU_name].s)
12614 : NULL;
12615 out_attr[Tag_CPU_raw_name].s = in_attr[Tag_CPU_raw_name].s
12616 ? _bfd_elf_attr_strdup (obfd, in_attr[Tag_CPU_raw_name].s)
12617 : NULL;
12618 }
12619 else
12620 {
12621 out_attr[Tag_CPU_name].s = NULL;
12622 out_attr[Tag_CPU_raw_name].s = NULL;
12623 }
12624
12625 /* If we still don't have a value for Tag_CPU_name,
12626 make one up now. Tag_CPU_raw_name remains blank. */
12627 if (out_attr[Tag_CPU_name].s == NULL
12628 && out_attr[i].i < ARRAY_SIZE (name_table))
12629 out_attr[Tag_CPU_name].s =
12630 _bfd_elf_attr_strdup (obfd, name_table[out_attr[i].i]);
12631 }
12632 break;
12633
ee065d83
PB		 12634 case Tag_ARM_ISA_use:
12635 case Tag_THUMB_ISA_use:
ee065d83 12636 case Tag_WMMX_arch:
91e22acd
AS		 12637 case Tag_Advanced_SIMD_arch:
12638 /* ??? Do Advanced_SIMD (NEON) and WMMX conflict? */
ee065d83 12639 case Tag_ABI_FP_rounding:
ee065d83
PB		 12640 case Tag_ABI_FP_exceptions:
12641 case Tag_ABI_FP_user_exceptions:
12642 case Tag_ABI_FP_number_model:
75375b3e 12643 case Tag_FP_HP_extension:
91e22acd
AS		 12644 case Tag_CPU_unaligned_access:
12645 case Tag_T2EE_use:
91e22acd 12646 case Tag_MPextension_use:
ee065d83
PB		 12647 /* Use the largest value specified. */
12648 if (in_attr[i].i > out_attr[i].i)
12649 out_attr[i].i = in_attr[i].i;
12650 break;
12651
75375b3e 12652 case Tag_ABI_align_preserved:
91e22acd
AS		 12653 case Tag_ABI_PCS_RO_data:
12654 /* Use the smallest value specified. */
12655 if (in_attr[i].i < out_attr[i].i)
12656 out_attr[i].i = in_attr[i].i;
12657 break;
12658
75375b3e 12659 case Tag_ABI_align_needed:
91e22acd 12660 if ((in_attr[i].i > 0 || out_attr[i].i > 0)
75375b3e
MGD		 12661 && (in_attr[Tag_ABI_align_preserved].i == 0
12662 || out_attr[Tag_ABI_align_preserved].i == 0))
ee065d83 12663 {
91e22acd
AS		 12664 /* This error message should be enabled once all non-conformant
12665 binaries in the toolchain have had the attributes set
12666 properly.
ee065d83 12667 _bfd_error_handler
3895f852 12668 (_("error: %B: 8-byte data alignment conflicts with %B"),
91e22acd
AS		 12669 obfd, ibfd);
12670 result = FALSE; */
ee065d83 12671 }
91e22acd
AS		 12672 /* Fall through. */
12673 case Tag_ABI_FP_denormal:
12674 case Tag_ABI_PCS_GOT_use:
12675 /* Use the "greatest" from the sequence 0, 2, 1, or the largest
12676 value if greater than 2 (for future-proofing). */
12677 if ((in_attr[i].i > 2 && in_attr[i].i > out_attr[i].i)
12678 || (in_attr[i].i <= 2 && out_attr[i].i <= 2
12679 && order_021[in_attr[i].i] > order_021[out_attr[i].i]))
ee065d83
PB		 12680 out_attr[i].i = in_attr[i].i;
12681 break;
91e22acd 12682
75375b3e
MGD		 12683 case Tag_Virtualization_use:
12684 /* The virtualization tag effectively stores two bits of
12685 information: the intended use of TrustZone (in bit 0), and the
12686 intended use of Virtualization (in bit 1). */
12687 if (out_attr[i].i == 0)
12688 out_attr[i].i = in_attr[i].i;
12689 else if (in_attr[i].i != 0
12690 && in_attr[i].i != out_attr[i].i)
12691 {
12692 if (in_attr[i].i <= 3 && out_attr[i].i <= 3)
12693 out_attr[i].i = 3;
12694 else
12695 {
12696 _bfd_error_handler
12697 (_("error: %B: unable to merge virtualization attributes "
12698 "with %B"),
12699 obfd, ibfd);
12700 result = FALSE;
12701 }
12702 }
12703 break;
91e22acd
AS		 12704
12705 case Tag_CPU_arch_profile:
12706 if (out_attr[i].i != in_attr[i].i)
12707 {
12708 /* 0 will merge with anything.
12709 'A' and 'S' merge to 'A'.
12710 'R' and 'S' merge to 'R'.
99059e56 12711 'M' and 'A|R|S' is an error. */
91e22acd
AS		 12712 if (out_attr[i].i == 0
12713 || (out_attr[i].i == 'S'
12714 && (in_attr[i].i == 'A' || in_attr[i].i == 'R')))
12715 out_attr[i].i = in_attr[i].i;
12716 else if (in_attr[i].i == 0
12717 || (in_attr[i].i == 'S'
12718 && (out_attr[i].i == 'A' || out_attr[i].i == 'R')))
6a631e86 12719 ; /* Do nothing. */
91e22acd
AS		 12720 else
12721 {
12722 _bfd_error_handler
3895f852 12723 (_("error: %B: Conflicting architecture profiles %c/%c"),
91e22acd
AS		 12724 ibfd,
12725 in_attr[i].i ? in_attr[i].i : '0',
12726 out_attr[i].i ? out_attr[i].i : '0');
12727 result = FALSE;
12728 }
12729 }
12730 break;
75375b3e 12731 case Tag_FP_arch:
62f3b8c8 12732 {
4547cb56
NC		 12733 /* Tag_ABI_HardFP_use is handled along with Tag_FP_arch since
12734 the meaning of Tag_ABI_HardFP_use depends on Tag_FP_arch
12735 when it's 0. It might mean absence of FP hardware if
99654aaf 12736 Tag_FP_arch is zero. */
4547cb56 12737
a715796b 12738#define VFP_VERSION_COUNT 9
62f3b8c8
PB		 12739 static const struct
12740 {
12741 int ver;
12742 int regs;
bca38921 12743 } vfp_versions[VFP_VERSION_COUNT] =
62f3b8c8
PB		 12744 {
12745 {0, 0},
12746 {1, 16},
12747 {2, 16},
12748 {3, 32},
12749 {3, 16},
12750 {4, 32},
bca38921 12751 {4, 16},
a715796b
TG		 12752 {8, 32},
12753 {8, 16}
62f3b8c8
PB		 12754 };
12755 int ver;
12756 int regs;
12757 int newval;
12758
4547cb56
NC		 12759 /* If the output has no requirement about FP hardware,
12760 follow the requirement of the input. */
12761 if (out_attr[i].i == 0)
12762 {
12763 BFD_ASSERT (out_attr[Tag_ABI_HardFP_use].i == 0);
12764 out_attr[i].i = in_attr[i].i;
12765 out_attr[Tag_ABI_HardFP_use].i
12766 = in_attr[Tag_ABI_HardFP_use].i;
12767 break;
12768 }
12769 /* If the input has no requirement about FP hardware, do
12770 nothing. */
12771 else if (in_attr[i].i == 0)
12772 {
12773 BFD_ASSERT (in_attr[Tag_ABI_HardFP_use].i == 0);
12774 break;
12775 }
12776
12777 /* Both the input and the output have nonzero Tag_FP_arch.
99654aaf 12778 So Tag_ABI_HardFP_use is implied by Tag_FP_arch when it's zero. */
4547cb56
NC		 12779
12780 /* If both the input and the output have zero Tag_ABI_HardFP_use,
12781 do nothing. */
12782 if (in_attr[Tag_ABI_HardFP_use].i == 0
12783 && out_attr[Tag_ABI_HardFP_use].i == 0)
12784 ;
12785 /* If the input and the output have different Tag_ABI_HardFP_use,
99654aaf 12786 the combination of them is 0 (implied by Tag_FP_arch). */
4547cb56
NC		 12787 else if (in_attr[Tag_ABI_HardFP_use].i
12788 != out_attr[Tag_ABI_HardFP_use].i)
99654aaf 12789 out_attr[Tag_ABI_HardFP_use].i = 0;
4547cb56
NC		 12790
12791 /* Now we can handle Tag_FP_arch. */
12792
bca38921
MGD		 12793 /* Values of VFP_VERSION_COUNT or more aren't defined, so just
12794 pick the biggest. */
12795 if (in_attr[i].i >= VFP_VERSION_COUNT
12796 && in_attr[i].i > out_attr[i].i)
62f3b8c8
PB		 12797 {
12798 out_attr[i] = in_attr[i];
12799 break;
12800 }
12801 /* The output uses the superset of input features
12802 (ISA version) and registers. */
12803 ver = vfp_versions[in_attr[i].i].ver;
12804 if (ver < vfp_versions[out_attr[i].i].ver)
12805 ver = vfp_versions[out_attr[i].i].ver;
12806 regs = vfp_versions[in_attr[i].i].regs;
12807 if (regs < vfp_versions[out_attr[i].i].regs)
12808 regs = vfp_versions[out_attr[i].i].regs;
12809 /* This assumes all possible supersets are also a valid
99059e56 12810 options. */
bca38921 12811 for (newval = VFP_VERSION_COUNT - 1; newval > 0; newval--)
62f3b8c8
PB		 12812 {
12813 if (regs == vfp_versions[newval].regs
12814 && ver == vfp_versions[newval].ver)
12815 break;
12816 }
12817 out_attr[i].i = newval;
12818 }
b1cc4aeb 12819 break;
ee065d83
PB		 12820 case Tag_PCS_config:
12821 if (out_attr[i].i == 0)
12822 out_attr[i].i = in_attr[i].i;
b6009aca 12823 else if (in_attr[i].i != 0 && out_attr[i].i != in_attr[i].i)
ee065d83
PB		 12824 {
12825 /* It's sometimes ok to mix different configs, so this is only
99059e56 12826 a warning. */
ee065d83
PB		 12827 _bfd_error_handler
12828 (_("Warning: %B: Conflicting platform configuration"), ibfd);
12829 }
12830 break;
12831 case Tag_ABI_PCS_R9_use:
004ae526
PB		 12832 if (in_attr[i].i != out_attr[i].i
12833 && out_attr[i].i != AEABI_R9_unused
ee065d83
PB		 12834 && in_attr[i].i != AEABI_R9_unused)
12835 {
12836 _bfd_error_handler
3895f852 12837 (_("error: %B: Conflicting use of R9"), ibfd);
91e22acd 12838 result = FALSE;
ee065d83
PB		 12839 }
12840 if (out_attr[i].i == AEABI_R9_unused)
12841 out_attr[i].i = in_attr[i].i;
12842 break;
12843 case Tag_ABI_PCS_RW_data:
12844 if (in_attr[i].i == AEABI_PCS_RW_data_SBrel
12845 && out_attr[Tag_ABI_PCS_R9_use].i != AEABI_R9_SB
12846 && out_attr[Tag_ABI_PCS_R9_use].i != AEABI_R9_unused)
12847 {
12848 _bfd_error_handler
3895f852 12849 (_("error: %B: SB relative addressing conflicts with use of R9"),
ee065d83 12850 ibfd);
91e22acd 12851 result = FALSE;
ee065d83
PB		 12852 }
12853 /* Use the smallest value specified. */
12854 if (in_attr[i].i < out_attr[i].i)
12855 out_attr[i].i = in_attr[i].i;
12856 break;
ee065d83 12857 case Tag_ABI_PCS_wchar_t:
a9dc9481
JM		 12858 if (out_attr[i].i && in_attr[i].i && out_attr[i].i != in_attr[i].i
12859 && !elf_arm_tdata (obfd)->no_wchar_size_warning)
ee065d83
PB		 12860 {
12861 _bfd_error_handler
a9dc9481
JM		 12862 (_("warning: %B uses %u-byte wchar_t yet the output is to use %u-byte wchar_t; use of wchar_t values across objects may fail"),
12863 ibfd, in_attr[i].i, out_attr[i].i);
ee065d83 12864 }
a9dc9481 12865 else if (in_attr[i].i && !out_attr[i].i)
ee065d83
PB		 12866 out_attr[i].i = in_attr[i].i;
12867 break;
ee065d83
PB		 12868 case Tag_ABI_enum_size:
12869 if (in_attr[i].i != AEABI_enum_unused)
12870 {
12871 if (out_attr[i].i == AEABI_enum_unused
12872 || out_attr[i].i == AEABI_enum_forced_wide)
12873 {
12874 /* The existing object is compatible with anything.
12875 Use whatever requirements the new object has. */
12876 out_attr[i].i = in_attr[i].i;
12877 }
12878 else if (in_attr[i].i != AEABI_enum_forced_wide
bf21ed78 12879 && out_attr[i].i != in_attr[i].i
0ffa91dd 12880 && !elf_arm_tdata (obfd)->no_enum_size_warning)
ee065d83 12881 {
91e22acd 12882 static const char *aeabi_enum_names[] =
bf21ed78 12883 { "", "variable-size", "32-bit", "" };
91e22acd
AS		 12884 const char *in_name =
12885 in_attr[i].i < ARRAY_SIZE(aeabi_enum_names)
12886 ? aeabi_enum_names[in_attr[i].i]
12887 : "<unknown>";
12888 const char *out_name =
12889 out_attr[i].i < ARRAY_SIZE(aeabi_enum_names)
12890 ? aeabi_enum_names[out_attr[i].i]
12891 : "<unknown>";
ee065d83 12892 _bfd_error_handler
bf21ed78 12893 (_("warning: %B uses %s enums yet the output is to use %s enums; use of enum values across objects may fail"),
91e22acd 12894 ibfd, in_name, out_name);
ee065d83
PB		 12895 }
12896 }
12897 break;
12898 case Tag_ABI_VFP_args:
12899 /* Aready done. */
12900 break;
12901 case Tag_ABI_WMMX_args:
12902 if (in_attr[i].i != out_attr[i].i)
12903 {
12904 _bfd_error_handler
3895f852 12905 (_("error: %B uses iWMMXt register arguments, %B does not"),
ee065d83 12906 ibfd, obfd);
91e22acd 12907 result = FALSE;
ee065d83
PB		 12908 }
12909 break;
7b86a9fa
AS		 12910 case Tag_compatibility:
12911 /* Merged in target-independent code. */
12912 break;
91e22acd 12913 case Tag_ABI_HardFP_use:
4547cb56 12914 /* This is handled along with Tag_FP_arch. */
91e22acd
AS		 12915 break;
12916 case Tag_ABI_FP_16bit_format:
12917 if (in_attr[i].i != 0 && out_attr[i].i != 0)
12918 {
12919 if (in_attr[i].i != out_attr[i].i)
12920 {
12921 _bfd_error_handler
3895f852 12922 (_("error: fp16 format mismatch between %B and %B"),
91e22acd
AS		 12923 ibfd, obfd);
12924 result = FALSE;
12925 }
12926 }
12927 if (in_attr[i].i != 0)
12928 out_attr[i].i = in_attr[i].i;
12929 break;
7b86a9fa 12930
cd21e546 12931 case Tag_DIV_use:
ac56ee8f
MGD		 12932 /* A value of zero on input means that the divide instruction may
12933 be used if available in the base architecture as specified via
12934 Tag_CPU_arch and Tag_CPU_arch_profile. A value of 1 means that
12935 the user did not want divide instructions. A value of 2
12936 explicitly means that divide instructions were allowed in ARM
12937 and Thumb state. */
12938 if (in_attr[i].i == out_attr[i].i)
12939 /* Do nothing. */ ;
12940 else if (elf32_arm_attributes_forbid_div (in_attr)
12941 && !elf32_arm_attributes_accept_div (out_attr))
12942 out_attr[i].i = 1;
12943 else if (elf32_arm_attributes_forbid_div (out_attr)
12944 && elf32_arm_attributes_accept_div (in_attr))
12945 out_attr[i].i = in_attr[i].i;
12946 else if (in_attr[i].i == 2)
12947 out_attr[i].i = in_attr[i].i;
cd21e546
MGD		 12948 break;
12949
12950 case Tag_MPextension_use_legacy:
12951 /* We don't output objects with Tag_MPextension_use_legacy - we
12952 move the value to Tag_MPextension_use. */
12953 if (in_attr[i].i != 0 && in_attr[Tag_MPextension_use].i != 0)
12954 {
12955 if (in_attr[Tag_MPextension_use].i != in_attr[i].i)
12956 {
12957 _bfd_error_handler
12958 (_("%B has has both the current and legacy "
b38cadfb 12959 "Tag_MPextension_use attributes"),
cd21e546
MGD		 12960 ibfd);
12961 result = FALSE;
12962 }
12963 }
12964
12965 if (in_attr[i].i > out_attr[Tag_MPextension_use].i)
12966 out_attr[Tag_MPextension_use] = in_attr[i];
12967
12968 break;
12969
91e22acd 12970 case Tag_nodefaults:
2d0bb761
AS		 12971 /* This tag is set if it exists, but the value is unused (and is
12972 typically zero). We don't actually need to do anything here -
12973 the merge happens automatically when the type flags are merged
12974 below. */
91e22acd
AS		 12975 break;
12976 case Tag_also_compatible_with:
12977 /* Already done in Tag_CPU_arch. */
12978 break;
12979 case Tag_conformance:
12980 /* Keep the attribute if it matches. Throw it away otherwise.
12981 No attribute means no claim to conform. */
12982 if (!in_attr[i].s || !out_attr[i].s
12983 || strcmp (in_attr[i].s, out_attr[i].s) != 0)
12984 out_attr[i].s = NULL;
12985 break;
3cfad14c 12986
91e22acd 12987 default:
e8b36cd1
JM		 12988 result
12989 = result && _bfd_elf_merge_unknown_attribute_low (ibfd, obfd, i);
91e22acd
AS		 12990 }
12991
12992 /* If out_attr was copied from in_attr then it won't have a type yet. */
12993 if (in_attr[i].type && !out_attr[i].type)
12994 out_attr[i].type = in_attr[i].type;
ee065d83
PB		 12995 }
12996
104d59d1 12997 /* Merge Tag_compatibility attributes and any common GNU ones. */
5488d830
MGD		 12998 if (!_bfd_elf_merge_object_attributes (ibfd, obfd))
12999 return FALSE;
ee065d83 13000
104d59d1 13001 /* Check for any attributes not known on ARM. */
e8b36cd1 13002 result &= _bfd_elf_merge_unknown_attribute_list (ibfd, obfd);
91e22acd 13003
91e22acd 13004 return result;
252b5132
RH		 13005}
13006
3a4a14e9
PB		 13007
13008/* Return TRUE if the two EABI versions are incompatible. */
13009
13010static bfd_boolean
13011elf32_arm_versions_compatible (unsigned iver, unsigned over)
13012{
13013 /* v4 and v5 are the same spec before and after it was released,
13014 so allow mixing them. */
13015 if ((iver == EF_ARM_EABI_VER4 && over == EF_ARM_EABI_VER5)
13016 || (iver == EF_ARM_EABI_VER5 && over == EF_ARM_EABI_VER4))
13017 return TRUE;
13018
13019 return (iver == over);
13020}
13021
252b5132
RH		 13022/* Merge backend specific data from an object file to the output
13023 object file when linking. */
9b485d32 13024
b34976b6 13025static bfd_boolean
21d799b5 13026elf32_arm_merge_private_bfd_data (bfd * ibfd, bfd * obfd);
252b5132 13027
9b485d32
NC		 13028/* Display the flags field. */
13029
b34976b6 13030static bfd_boolean
57e8b36a 13031elf32_arm_print_private_bfd_data (bfd *abfd, void * ptr)
252b5132 13032{
fc830a83
NC		 13033 FILE * file = (FILE *) ptr;
13034 unsigned long flags;
252b5132
RH		 13035
13036 BFD_ASSERT (abfd != NULL && ptr != NULL);
13037
13038 /* Print normal ELF private data. */
13039 _bfd_elf_print_private_bfd_data (abfd, ptr);
13040
fc830a83 13041 flags = elf_elfheader (abfd)->e_flags;
9b485d32
NC		 13042 /* Ignore init flag - it may not be set, despite the flags field
13043 containing valid data. */
252b5132
RH		 13044
13045 /* xgettext:c-format */
9b485d32 13046 fprintf (file, _("private flags = %lx:"), elf_elfheader (abfd)->e_flags);
252b5132 13047
fc830a83
NC		 13048 switch (EF_ARM_EABI_VERSION (flags))
13049 {
13050 case EF_ARM_EABI_UNKNOWN:
4cc11e76 13051 /* The following flag bits are GNU extensions and not part of the
fc830a83
NC		 13052 official ARM ELF extended ABI. Hence they are only decoded if
13053 the EABI version is not set. */
fd2ec330 13054 if (flags & EF_ARM_INTERWORK)
9b485d32 13055 fprintf (file, _(" [interworking enabled]"));
9a5aca8c 13056
fd2ec330 13057 if (flags & EF_ARM_APCS_26)
6c571f00 13058 fprintf (file, " [APCS-26]");
fc830a83 13059 else
6c571f00 13060 fprintf (file, " [APCS-32]");
9a5aca8c 13061
96a846ea
RE		 13062 if (flags & EF_ARM_VFP_FLOAT)
13063 fprintf (file, _(" [VFP float format]"));
fde78edd
NC		 13064 else if (flags & EF_ARM_MAVERICK_FLOAT)
13065 fprintf (file, _(" [Maverick float format]"));
96a846ea
RE		 13066 else
13067 fprintf (file, _(" [FPA float format]"));
13068
fd2ec330 13069 if (flags & EF_ARM_APCS_FLOAT)
9b485d32 13070 fprintf (file, _(" [floats passed in float registers]"));
9a5aca8c 13071
fd2ec330 13072 if (flags & EF_ARM_PIC)
9b485d32 13073 fprintf (file, _(" [position independent]"));
fc830a83 13074
fd2ec330 13075 if (flags & EF_ARM_NEW_ABI)
9b485d32 13076 fprintf (file, _(" [new ABI]"));
9a5aca8c 13077
fd2ec330 13078 if (flags & EF_ARM_OLD_ABI)
9b485d32 13079 fprintf (file, _(" [old ABI]"));
9a5aca8c 13080
fd2ec330 13081 if (flags & EF_ARM_SOFT_FLOAT)
9b485d32 13082 fprintf (file, _(" [software FP]"));
9a5aca8c 13083
96a846ea
RE		 13084 flags &= ~(EF_ARM_INTERWORK | EF_ARM_APCS_26 | EF_ARM_APCS_FLOAT
13085 | EF_ARM_PIC | EF_ARM_NEW_ABI | EF_ARM_OLD_ABI
fde78edd
NC		 13086 | EF_ARM_SOFT_FLOAT | EF_ARM_VFP_FLOAT
13087 | EF_ARM_MAVERICK_FLOAT);
fc830a83 13088 break;
9a5aca8c 13089
fc830a83 13090 case EF_ARM_EABI_VER1:
9b485d32 13091 fprintf (file, _(" [Version1 EABI]"));
9a5aca8c 13092
fc830a83 13093 if (flags & EF_ARM_SYMSARESORTED)
9b485d32 13094 fprintf (file, _(" [sorted symbol table]"));
fc830a83 13095 else
9b485d32 13096 fprintf (file, _(" [unsorted symbol table]"));
9a5aca8c 13097
fc830a83
NC		 13098 flags &= ~ EF_ARM_SYMSARESORTED;
13099 break;
9a5aca8c 13100
fd2ec330
PB		 13101 case EF_ARM_EABI_VER2:
13102 fprintf (file, _(" [Version2 EABI]"));
13103
13104 if (flags & EF_ARM_SYMSARESORTED)
13105 fprintf (file, _(" [sorted symbol table]"));
13106 else
13107 fprintf (file, _(" [unsorted symbol table]"));
13108
13109 if (flags & EF_ARM_DYNSYMSUSESEGIDX)
13110 fprintf (file, _(" [dynamic symbols use segment index]"));
13111
13112 if (flags & EF_ARM_MAPSYMSFIRST)
13113 fprintf (file, _(" [mapping symbols precede others]"));
13114
99e4ae17 13115 flags &= ~(EF_ARM_SYMSARESORTED | EF_ARM_DYNSYMSUSESEGIDX
fd2ec330
PB		 13116 | EF_ARM_MAPSYMSFIRST);
13117 break;
13118
d507cf36
PB		 13119 case EF_ARM_EABI_VER3:
13120 fprintf (file, _(" [Version3 EABI]"));
8cb51566
PB		 13121 break;
13122
13123 case EF_ARM_EABI_VER4:
13124 fprintf (file, _(" [Version4 EABI]"));
3a4a14e9 13125 goto eabi;
d507cf36 13126
3a4a14e9
PB		 13127 case EF_ARM_EABI_VER5:
13128 fprintf (file, _(" [Version5 EABI]"));
3bfcb652
NC		 13129
13130 if (flags & EF_ARM_ABI_FLOAT_SOFT)
13131 fprintf (file, _(" [soft-float ABI]"));
13132
13133 if (flags & EF_ARM_ABI_FLOAT_HARD)
13134 fprintf (file, _(" [hard-float ABI]"));
13135
13136 flags &= ~(EF_ARM_ABI_FLOAT_SOFT | EF_ARM_ABI_FLOAT_HARD);
13137
3a4a14e9 13138 eabi:
d507cf36
PB		 13139 if (flags & EF_ARM_BE8)
13140 fprintf (file, _(" [BE8]"));
13141
13142 if (flags & EF_ARM_LE8)
13143 fprintf (file, _(" [LE8]"));
13144
13145 flags &= ~(EF_ARM_LE8 | EF_ARM_BE8);
13146 break;
13147
fc830a83 13148 default:
9b485d32 13149 fprintf (file, _(" <EABI version unrecognised>"));
fc830a83
NC		 13150 break;
13151 }
252b5132 13152
fc830a83 13153 flags &= ~ EF_ARM_EABIMASK;
252b5132 13154
fc830a83 13155 if (flags & EF_ARM_RELEXEC)
9b485d32 13156 fprintf (file, _(" [relocatable executable]"));
252b5132 13157
a5721edd 13158 flags &= ~EF_ARM_RELEXEC;
fc830a83
NC		 13159
13160 if (flags)
9b485d32 13161 fprintf (file, _("<Unrecognised flag bits set>"));
9a5aca8c 13162
252b5132
RH		 13163 fputc ('\n', file);
13164
b34976b6 13165 return TRUE;
252b5132
RH		 13166}
13167
13168static int
57e8b36a 13169elf32_arm_get_symbol_type (Elf_Internal_Sym * elf_sym, int type)
252b5132 13170{
2f0ca46a
NC		 13171 switch (ELF_ST_TYPE (elf_sym->st_info))
13172 {
13173 case STT_ARM_TFUNC:
13174 return ELF_ST_TYPE (elf_sym->st_info);
ce855c42 13175
2f0ca46a
NC		 13176 case STT_ARM_16BIT:
13177 /* If the symbol is not an object, return the STT_ARM_16BIT flag.
13178 This allows us to distinguish between data used by Thumb instructions
13179 and non-data (which is probably code) inside Thumb regions of an
13180 executable. */
1a0eb693 13181 if (type != STT_OBJECT && type != STT_TLS)
2f0ca46a
NC		 13182 return ELF_ST_TYPE (elf_sym->st_info);
13183 break;
9a5aca8c 13184
ce855c42
NC		 13185 default:
13186 break;
2f0ca46a
NC		 13187 }
13188
13189 return type;
252b5132 13190}
f21f3fe0 13191
252b5132 13192static asection *
07adf181
AM		 13193elf32_arm_gc_mark_hook (asection *sec,
13194 struct bfd_link_info *info,
13195 Elf_Internal_Rela *rel,
13196 struct elf_link_hash_entry *h,
13197 Elf_Internal_Sym *sym)
252b5132
RH		 13198{
13199 if (h != NULL)
07adf181 13200 switch (ELF32_R_TYPE (rel->r_info))
252b5132
RH		 13201 {
13202 case R_ARM_GNU_VTINHERIT:
13203 case R_ARM_GNU_VTENTRY:
07adf181
AM		 13204 return NULL;
13205 }
9ad5cbcf 13206
07adf181 13207 return _bfd_elf_gc_mark_hook (sec, info, rel, h, sym);
252b5132
RH		 13208}
13209
780a67af
NC		 13210/* Update the got entry reference counts for the section being removed. */
13211
b34976b6 13212static bfd_boolean
ba93b8ac
DJ		 13213elf32_arm_gc_sweep_hook (bfd * abfd,
13214 struct bfd_link_info * info,
13215 asection * sec,
13216 const Elf_Internal_Rela * relocs)
252b5132 13217{
5e681ec4
PB		 13218 Elf_Internal_Shdr *symtab_hdr;
13219 struct elf_link_hash_entry **sym_hashes;
13220 bfd_signed_vma *local_got_refcounts;
13221 const Elf_Internal_Rela *rel, *relend;
eb043451
PB		 13222 struct elf32_arm_link_hash_table * globals;
13223
0e1862bb 13224 if (bfd_link_relocatable (info))
7dda2462
TG		 13225 return TRUE;
13226
eb043451 13227 globals = elf32_arm_hash_table (info);
4dfe6ac6
NC		 13228 if (globals == NULL)
13229 return FALSE;
5e681ec4
PB		 13230
13231 elf_section_data (sec)->local_dynrel = NULL;
13232
0ffa91dd 13233 symtab_hdr = & elf_symtab_hdr (abfd);
5e681ec4
PB		 13234 sym_hashes = elf_sym_hashes (abfd);
13235 local_got_refcounts = elf_local_got_refcounts (abfd);
13236
906e58ca 13237 check_use_blx (globals);
bd97cb95 13238
5e681ec4
PB		 13239 relend = relocs + sec->reloc_count;
13240 for (rel = relocs; rel < relend; rel++)
eb043451 13241 {
3eb128b2
AM		 13242 unsigned long r_symndx;
13243 struct elf_link_hash_entry *h = NULL;
f6e32f6d 13244 struct elf32_arm_link_hash_entry *eh;
eb043451 13245 int r_type;
34e77a92 13246 bfd_boolean call_reloc_p;
f6e32f6d
RS		 13247 bfd_boolean may_become_dynamic_p;
13248 bfd_boolean may_need_local_target_p;
34e77a92
RS		 13249 union gotplt_union *root_plt;
13250 struct arm_plt_info *arm_plt;
5e681ec4 13251
3eb128b2
AM		 13252 r_symndx = ELF32_R_SYM (rel->r_info);
13253 if (r_symndx >= symtab_hdr->sh_info)
13254 {
13255 h = sym_hashes[r_symndx - symtab_hdr->sh_info];
13256 while (h->root.type == bfd_link_hash_indirect
13257 || h->root.type == bfd_link_hash_warning)
13258 h = (struct elf_link_hash_entry *) h->root.u.i.link;
13259 }
f6e32f6d
RS		 13260 eh = (struct elf32_arm_link_hash_entry *) h;
13261
34e77a92 13262 call_reloc_p = FALSE;
f6e32f6d
RS		 13263 may_become_dynamic_p = FALSE;
13264 may_need_local_target_p = FALSE;
3eb128b2 13265
eb043451 13266 r_type = ELF32_R_TYPE (rel->r_info);
eb043451 13267 r_type = arm_real_reloc_type (globals, r_type);
eb043451
PB		 13268 switch (r_type)
13269 {
13270 case R_ARM_GOT32:
eb043451 13271 case R_ARM_GOT_PREL:
ba93b8ac
DJ		 13272 case R_ARM_TLS_GD32:
13273 case R_ARM_TLS_IE32:
3eb128b2 13274 if (h != NULL)
eb043451 13275 {
eb043451
PB		 13276 if (h->got.refcount > 0)
13277 h->got.refcount -= 1;
13278 }
13279 else if (local_got_refcounts != NULL)
13280 {
13281 if (local_got_refcounts[r_symndx] > 0)
13282 local_got_refcounts[r_symndx] -= 1;
13283 }
13284 break;
13285
ba93b8ac 13286 case R_ARM_TLS_LDM32:
4dfe6ac6 13287 globals->tls_ldm_got.refcount -= 1;
ba93b8ac
DJ		 13288 break;
13289
eb043451
PB		 13290 case R_ARM_PC24:
13291 case R_ARM_PLT32:
5b5bb741
PB		 13292 case R_ARM_CALL:
13293 case R_ARM_JUMP24:
eb043451 13294 case R_ARM_PREL31:
c19d1205 13295 case R_ARM_THM_CALL:
bd97cb95
DJ		 13296 case R_ARM_THM_JUMP24:
13297 case R_ARM_THM_JUMP19:
34e77a92 13298 call_reloc_p = TRUE;
f6e32f6d
RS		 13299 may_need_local_target_p = TRUE;
13300 break;
13301
13302 case R_ARM_ABS12:
13303 if (!globals->vxworks_p)
13304 {
13305 may_need_local_target_p = TRUE;
13306 break;
13307 }
13308 /* Fall through. */
13309 case R_ARM_ABS32:
13310 case R_ARM_ABS32_NOI:
13311 case R_ARM_REL32:
13312 case R_ARM_REL32_NOI:
b6895b4f
PB		 13313 case R_ARM_MOVW_ABS_NC:
13314 case R_ARM_MOVT_ABS:
13315 case R_ARM_MOVW_PREL_NC:
13316 case R_ARM_MOVT_PREL:
13317 case R_ARM_THM_MOVW_ABS_NC:
13318 case R_ARM_THM_MOVT_ABS:
13319 case R_ARM_THM_MOVW_PREL_NC:
13320 case R_ARM_THM_MOVT_PREL:
b7693d02 13321 /* Should the interworking branches be here also? */
0e1862bb 13322 if ((bfd_link_pic (info) || globals->root.is_relocatable_executable)
34e77a92
RS		 13323 && (sec->flags & SEC_ALLOC) != 0)
13324 {
13325 if (h == NULL
469a3493 13326 && elf32_arm_howto_from_type (r_type)->pc_relative)
34e77a92
RS		 13327 {
13328 call_reloc_p = TRUE;
13329 may_need_local_target_p = TRUE;
13330 }
13331 else
13332 may_become_dynamic_p = TRUE;
13333 }
f6e32f6d
RS		 13334 else
13335 may_need_local_target_p = TRUE;
13336 break;
b7693d02 13337
f6e32f6d
RS		 13338 default:
13339 break;
13340 }
5e681ec4 13341
34e77a92
RS		 13342 if (may_need_local_target_p
13343 && elf32_arm_get_plt_info (abfd, eh, r_symndx, &root_plt, &arm_plt))
f6e32f6d 13344 {
27586251
HPN		 13345 /* If PLT refcount book-keeping is wrong and too low, we'll
13346 see a zero value (going to -1) for the root PLT reference
13347 count. */
13348 if (root_plt->refcount >= 0)
13349 {
13350 BFD_ASSERT (root_plt->refcount != 0);
13351 root_plt->refcount -= 1;
13352 }
13353 else
13354 /* A value of -1 means the symbol has become local, forced
13355 or seeing a hidden definition. Any other negative value
13356 is an error. */
13357 BFD_ASSERT (root_plt->refcount == -1);
34e77a92
RS		 13358
13359 if (!call_reloc_p)
13360 arm_plt->noncall_refcount--;
5e681ec4 13361
f6e32f6d 13362 if (r_type == R_ARM_THM_CALL)
34e77a92 13363 arm_plt->maybe_thumb_refcount--;
bd97cb95 13364
f6e32f6d
RS		 13365 if (r_type == R_ARM_THM_JUMP24
13366 || r_type == R_ARM_THM_JUMP19)
34e77a92 13367 arm_plt->thumb_refcount--;
f6e32f6d 13368 }
5e681ec4 13369
34e77a92 13370 if (may_become_dynamic_p)
f6e32f6d
RS		 13371 {
13372 struct elf_dyn_relocs **pp;
13373 struct elf_dyn_relocs *p;
5e681ec4 13374
34e77a92 13375 if (h != NULL)
9c489990 13376 pp = &(eh->dyn_relocs);
34e77a92
RS		 13377 else
13378 {
13379 Elf_Internal_Sym *isym;
13380
13381 isym = bfd_sym_from_r_symndx (&globals->sym_cache,
13382 abfd, r_symndx);
13383 if (isym == NULL)
13384 return FALSE;
13385 pp = elf32_arm_get_local_dynreloc_list (abfd, r_symndx, isym);
13386 if (pp == NULL)
13387 return FALSE;
13388 }
9c489990 13389 for (; (p = *pp) != NULL; pp = &p->next)
f6e32f6d
RS		 13390 if (p->sec == sec)
13391 {
13392 /* Everything must go for SEC. */
13393 *pp = p->next;
13394 break;
13395 }
eb043451
PB		 13396 }
13397 }
5e681ec4 13398
b34976b6 13399 return TRUE;
252b5132
RH		 13400}
13401
780a67af
NC		 13402/* Look through the relocs for a section during the first phase. */
13403
b34976b6 13404static bfd_boolean
57e8b36a
NC		 13405elf32_arm_check_relocs (bfd *abfd, struct bfd_link_info *info,
13406 asection *sec, const Elf_Internal_Rela *relocs)
252b5132 13407{
b34976b6
AM		 13408 Elf_Internal_Shdr *symtab_hdr;
13409 struct elf_link_hash_entry **sym_hashes;
b34976b6
AM		 13410 const Elf_Internal_Rela *rel;
13411 const Elf_Internal_Rela *rel_end;
13412 bfd *dynobj;
5e681ec4 13413 asection *sreloc;
5e681ec4 13414 struct elf32_arm_link_hash_table *htab;
f6e32f6d
RS		 13415 bfd_boolean call_reloc_p;
13416 bfd_boolean may_become_dynamic_p;
13417 bfd_boolean may_need_local_target_p;
ce98a316 13418 unsigned long nsyms;
9a5aca8c 13419
0e1862bb 13420 if (bfd_link_relocatable (info))
b34976b6 13421 return TRUE;
9a5aca8c 13422
0ffa91dd
NC		 13423 BFD_ASSERT (is_arm_elf (abfd));
13424
5e681ec4 13425 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 13426 if (htab == NULL)
13427 return FALSE;
13428
5e681ec4 13429 sreloc = NULL;
9a5aca8c 13430
67687978
PB		 13431 /* Create dynamic sections for relocatable executables so that we can
13432 copy relocations. */
13433 if (htab->root.is_relocatable_executable
13434 && ! htab->root.dynamic_sections_created)
13435 {
13436 if (! _bfd_elf_link_create_dynamic_sections (abfd, info))
13437 return FALSE;
13438 }
13439
cbc704f3
RS		 13440 if (htab->root.dynobj == NULL)
13441 htab->root.dynobj = abfd;
34e77a92
RS		 13442 if (!create_ifunc_sections (info))
13443 return FALSE;
cbc704f3
RS		 13444
13445 dynobj = htab->root.dynobj;
13446
0ffa91dd 13447 symtab_hdr = & elf_symtab_hdr (abfd);
252b5132 13448 sym_hashes = elf_sym_hashes (abfd);
ce98a316 13449 nsyms = NUM_SHDR_ENTRIES (symtab_hdr);
b38cadfb 13450
252b5132
RH		 13451 rel_end = relocs + sec->reloc_count;
13452 for (rel = relocs; rel < rel_end; rel++)
13453 {
34e77a92 13454 Elf_Internal_Sym *isym;
252b5132 13455 struct elf_link_hash_entry *h;
b7693d02 13456 struct elf32_arm_link_hash_entry *eh;
252b5132 13457 unsigned long r_symndx;
eb043451 13458 int r_type;
9a5aca8c 13459
252b5132 13460 r_symndx = ELF32_R_SYM (rel->r_info);
eb043451 13461 r_type = ELF32_R_TYPE (rel->r_info);
eb043451 13462 r_type = arm_real_reloc_type (htab, r_type);
ba93b8ac 13463
ce98a316
NC		 13464 if (r_symndx >= nsyms
13465 /* PR 9934: It is possible to have relocations that do not
13466 refer to symbols, thus it is also possible to have an
13467 object file containing relocations but no symbol table. */
cf35638d 13468 && (r_symndx > STN_UNDEF || nsyms > 0))
ba93b8ac
DJ		 13469 {
13470 (*_bfd_error_handler) (_("%B: bad symbol index: %d"), abfd,
ce98a316 13471 r_symndx);
ba93b8ac
DJ		 13472 return FALSE;
13473 }
13474
34e77a92
RS		 13475 h = NULL;
13476 isym = NULL;
13477 if (nsyms > 0)
973a3492 13478 {
34e77a92
RS		 13479 if (r_symndx < symtab_hdr->sh_info)
13480 {
13481 /* A local symbol. */
13482 isym = bfd_sym_from_r_symndx (&htab->sym_cache,
13483 abfd, r_symndx);
13484 if (isym == NULL)
13485 return FALSE;
13486 }
13487 else
13488 {
13489 h = sym_hashes[r_symndx - symtab_hdr->sh_info];
13490 while (h->root.type == bfd_link_hash_indirect
13491 || h->root.type == bfd_link_hash_warning)
13492 h = (struct elf_link_hash_entry *) h->root.u.i.link;
81fbe831
AM		 13493
13494 /* PR15323, ref flags aren't set for references in the
13495 same object. */
13496 h->root.non_ir_ref = 1;
34e77a92 13497 }
973a3492 13498 }
9a5aca8c 13499
b7693d02
DJ		 13500 eh = (struct elf32_arm_link_hash_entry *) h;
13501
f6e32f6d
RS		 13502 call_reloc_p = FALSE;
13503 may_become_dynamic_p = FALSE;
13504 may_need_local_target_p = FALSE;
13505
0855e32b
NS		 13506 /* Could be done earlier, if h were already available. */
13507 r_type = elf32_arm_tls_transition (info, r_type, h);
eb043451 13508 switch (r_type)
99059e56 13509 {
5e681ec4 13510 case R_ARM_GOT32:
eb043451 13511 case R_ARM_GOT_PREL:
ba93b8ac
DJ		 13512 case R_ARM_TLS_GD32:
13513 case R_ARM_TLS_IE32:
0855e32b
NS		 13514 case R_ARM_TLS_GOTDESC:
13515 case R_ARM_TLS_DESCSEQ:
13516 case R_ARM_THM_TLS_DESCSEQ:
13517 case R_ARM_TLS_CALL:
13518 case R_ARM_THM_TLS_CALL:
5e681ec4 13519 /* This symbol requires a global offset table entry. */
ba93b8ac
DJ		 13520 {
13521 int tls_type, old_tls_type;
5e681ec4 13522
ba93b8ac
DJ		 13523 switch (r_type)
13524 {
13525 case R_ARM_TLS_GD32: tls_type = GOT_TLS_GD; break;
b38cadfb 13526
ba93b8ac 13527 case R_ARM_TLS_IE32: tls_type = GOT_TLS_IE; break;
b38cadfb 13528
0855e32b
NS		 13529 case R_ARM_TLS_GOTDESC:
13530 case R_ARM_TLS_CALL: case R_ARM_THM_TLS_CALL:
13531 case R_ARM_TLS_DESCSEQ: case R_ARM_THM_TLS_DESCSEQ:
13532 tls_type = GOT_TLS_GDESC; break;
b38cadfb 13533
ba93b8ac
DJ		 13534 default: tls_type = GOT_NORMAL; break;
13535 }
252b5132 13536
0e1862bb 13537 if (!bfd_link_executable (info) && (tls_type & GOT_TLS_IE))
eea6dad2
KM		 13538 info->flags |= DF_STATIC_TLS;
13539
ba93b8ac
DJ		 13540 if (h != NULL)
13541 {
13542 h->got.refcount++;
13543 old_tls_type = elf32_arm_hash_entry (h)->tls_type;
13544 }
13545 else
13546 {
ba93b8ac 13547 /* This is a global offset table entry for a local symbol. */
34e77a92
RS		 13548 if (!elf32_arm_allocate_local_sym_info (abfd))
13549 return FALSE;
13550 elf_local_got_refcounts (abfd)[r_symndx] += 1;
ba93b8ac
DJ		 13551 old_tls_type = elf32_arm_local_got_tls_type (abfd) [r_symndx];
13552 }
13553
0855e32b 13554 /* If a variable is accessed with both tls methods, two
99059e56 13555 slots may be created. */
0855e32b
NS		 13556 if (GOT_TLS_GD_ANY_P (old_tls_type)
13557 && GOT_TLS_GD_ANY_P (tls_type))
13558 tls_type |= old_tls_type;
13559
13560 /* We will already have issued an error message if there
13561 is a TLS/non-TLS mismatch, based on the symbol
13562 type. So just combine any TLS types needed. */
ba93b8ac
DJ		 13563 if (old_tls_type != GOT_UNKNOWN && old_tls_type != GOT_NORMAL
13564 && tls_type != GOT_NORMAL)
13565 tls_type |= old_tls_type;
13566
0855e32b 13567 /* If the symbol is accessed in both IE and GDESC
99059e56
RM		 13568 method, we're able to relax. Turn off the GDESC flag,
13569 without messing up with any other kind of tls types
6a631e86 13570 that may be involved. */
0855e32b
NS		 13571 if ((tls_type & GOT_TLS_IE) && (tls_type & GOT_TLS_GDESC))
13572 tls_type &= ~GOT_TLS_GDESC;
13573
ba93b8ac
DJ		 13574 if (old_tls_type != tls_type)
13575 {
13576 if (h != NULL)
13577 elf32_arm_hash_entry (h)->tls_type = tls_type;
13578 else
13579 elf32_arm_local_got_tls_type (abfd) [r_symndx] = tls_type;
13580 }
13581 }
8029a119 13582 /* Fall through. */
ba93b8ac
DJ		 13583
13584 case R_ARM_TLS_LDM32:
13585 if (r_type == R_ARM_TLS_LDM32)
13586 htab->tls_ldm_got.refcount++;
8029a119 13587 /* Fall through. */
252b5132 13588
c19d1205 13589 case R_ARM_GOTOFF32:
5e681ec4 13590 case R_ARM_GOTPC:
cbc704f3
RS		 13591 if (htab->root.sgot == NULL
13592 && !create_got_section (htab->root.dynobj, info))
13593 return FALSE;
252b5132
RH		 13594 break;
13595
252b5132 13596 case R_ARM_PC24:
7359ea65 13597 case R_ARM_PLT32:
5b5bb741
PB		 13598 case R_ARM_CALL:
13599 case R_ARM_JUMP24:
eb043451 13600 case R_ARM_PREL31:
c19d1205 13601 case R_ARM_THM_CALL:
bd97cb95
DJ		 13602 case R_ARM_THM_JUMP24:
13603 case R_ARM_THM_JUMP19:
f6e32f6d
RS		 13604 call_reloc_p = TRUE;
13605 may_need_local_target_p = TRUE;
13606 break;
13607
13608 case R_ARM_ABS12:
13609 /* VxWorks uses dynamic R_ARM_ABS12 relocations for
13610 ldr __GOTT_INDEX__ offsets. */
13611 if (!htab->vxworks_p)
13612 {
13613 may_need_local_target_p = TRUE;
13614 break;
13615 }
13616 /* Fall through. */
39623e12 13617
96c23d59
JM		 13618 case R_ARM_MOVW_ABS_NC:
13619 case R_ARM_MOVT_ABS:
13620 case R_ARM_THM_MOVW_ABS_NC:
13621 case R_ARM_THM_MOVT_ABS:
0e1862bb 13622 if (bfd_link_pic (info))
96c23d59
JM		 13623 {
13624 (*_bfd_error_handler)
13625 (_("%B: relocation %s against `%s' can not be used when making a shared object; recompile with -fPIC"),
13626 abfd, elf32_arm_howto_table_1[r_type].name,
13627 (h) ? h->root.root.string : "a local symbol");
13628 bfd_set_error (bfd_error_bad_value);
13629 return FALSE;
13630 }
13631
13632 /* Fall through. */
39623e12
PB		 13633 case R_ARM_ABS32:
13634 case R_ARM_ABS32_NOI:
0e1862bb 13635 if (h != NULL && bfd_link_executable (info))
97323ad1
WN		 13636 {
13637 h->pointer_equality_needed = 1;
13638 }
13639 /* Fall through. */
39623e12
PB		 13640 case R_ARM_REL32:
13641 case R_ARM_REL32_NOI:
b6895b4f
PB		 13642 case R_ARM_MOVW_PREL_NC:
13643 case R_ARM_MOVT_PREL:
b6895b4f
PB		 13644 case R_ARM_THM_MOVW_PREL_NC:
13645 case R_ARM_THM_MOVT_PREL:
39623e12 13646
b7693d02 13647 /* Should the interworking branches be listed here? */
0e1862bb 13648 if ((bfd_link_pic (info) || htab->root.is_relocatable_executable)
34e77a92
RS		 13649 && (sec->flags & SEC_ALLOC) != 0)
13650 {
13651 if (h == NULL
469a3493 13652 && elf32_arm_howto_from_type (r_type)->pc_relative)
34e77a92
RS		 13653 {
13654 /* In shared libraries and relocatable executables,
13655 we treat local relative references as calls;
13656 see the related SYMBOL_CALLS_LOCAL code in
13657 allocate_dynrelocs. */
13658 call_reloc_p = TRUE;
13659 may_need_local_target_p = TRUE;
13660 }
13661 else
13662 /* We are creating a shared library or relocatable
13663 executable, and this is a reloc against a global symbol,
13664 or a non-PC-relative reloc against a local symbol.
13665 We may need to copy the reloc into the output. */
13666 may_become_dynamic_p = TRUE;
13667 }
f6e32f6d
RS		 13668 else
13669 may_need_local_target_p = TRUE;
252b5132
RH		 13670 break;
13671
99059e56
RM		 13672 /* This relocation describes the C++ object vtable hierarchy.
13673 Reconstruct it for later use during GC. */
13674 case R_ARM_GNU_VTINHERIT:
13675 if (!bfd_elf_gc_record_vtinherit (abfd, sec, h, rel->r_offset))
13676 return FALSE;
13677 break;
13678
13679 /* This relocation describes which C++ vtable entries are actually
13680 used. Record for later use during GC. */
13681 case R_ARM_GNU_VTENTRY:
13682 BFD_ASSERT (h != NULL);
13683 if (h != NULL
13684 && !bfd_elf_gc_record_vtentry (abfd, sec, h, rel->r_offset))
13685 return FALSE;
13686 break;
13687 }
f6e32f6d
RS		 13688
13689 if (h != NULL)
13690 {
13691 if (call_reloc_p)
13692 /* We may need a .plt entry if the function this reloc
13693 refers to is in a different object, regardless of the
13694 symbol's type. We can't tell for sure yet, because
13695 something later might force the symbol local. */
13696 h->needs_plt = 1;
13697 else if (may_need_local_target_p)
13698 /* If this reloc is in a read-only section, we might
13699 need a copy reloc. We can't check reliably at this
13700 stage whether the section is read-only, as input
13701 sections have not yet been mapped to output sections.
13702 Tentatively set the flag for now, and correct in
13703 adjust_dynamic_symbol. */
13704 h->non_got_ref = 1;
13705 }
13706
34e77a92
RS		 13707 if (may_need_local_target_p
13708 && (h != NULL || ELF32_ST_TYPE (isym->st_info) == STT_GNU_IFUNC))
f6e32f6d 13709 {
34e77a92
RS		 13710 union gotplt_union *root_plt;
13711 struct arm_plt_info *arm_plt;
13712 struct arm_local_iplt_info *local_iplt;
13713
13714 if (h != NULL)
13715 {
13716 root_plt = &h->plt;
13717 arm_plt = &eh->plt;
13718 }
13719 else
13720 {
13721 local_iplt = elf32_arm_create_local_iplt (abfd, r_symndx);
13722 if (local_iplt == NULL)
13723 return FALSE;
13724 root_plt = &local_iplt->root;
13725 arm_plt = &local_iplt->arm;
13726 }
13727
f6e32f6d
RS		 13728 /* If the symbol is a function that doesn't bind locally,
13729 this relocation will need a PLT entry. */
a8c887dd
NC		 13730 if (root_plt->refcount != -1)
13731 root_plt->refcount += 1;
34e77a92
RS		 13732
13733 if (!call_reloc_p)
13734 arm_plt->noncall_refcount++;
f6e32f6d
RS		 13735
13736 /* It's too early to use htab->use_blx here, so we have to
13737 record possible blx references separately from
13738 relocs that definitely need a thumb stub. */
13739
13740 if (r_type == R_ARM_THM_CALL)
34e77a92 13741 arm_plt->maybe_thumb_refcount += 1;
f6e32f6d
RS		 13742
13743 if (r_type == R_ARM_THM_JUMP24
13744 || r_type == R_ARM_THM_JUMP19)
34e77a92 13745 arm_plt->thumb_refcount += 1;
f6e32f6d
RS		 13746 }
13747
13748 if (may_become_dynamic_p)
13749 {
13750 struct elf_dyn_relocs *p, **head;
13751
13752 /* Create a reloc section in dynobj. */
13753 if (sreloc == NULL)
13754 {
13755 sreloc = _bfd_elf_make_dynamic_reloc_section
13756 (sec, dynobj, 2, abfd, ! htab->use_rel);
13757
13758 if (sreloc == NULL)
13759 return FALSE;
13760
13761 /* BPABI objects never have dynamic relocations mapped. */
13762 if (htab->symbian_p)
13763 {
13764 flagword flags;
13765
13766 flags = bfd_get_section_flags (dynobj, sreloc);
13767 flags &= ~(SEC_LOAD | SEC_ALLOC);
13768 bfd_set_section_flags (dynobj, sreloc, flags);
13769 }
13770 }
13771
13772 /* If this is a global symbol, count the number of
13773 relocations we need for this symbol. */
13774 if (h != NULL)
13775 head = &((struct elf32_arm_link_hash_entry *) h)->dyn_relocs;
13776 else
13777 {
34e77a92
RS		 13778 head = elf32_arm_get_local_dynreloc_list (abfd, r_symndx, isym);
13779 if (head == NULL)
f6e32f6d 13780 return FALSE;
f6e32f6d
RS		 13781 }
13782
13783 p = *head;
13784 if (p == NULL || p->sec != sec)
13785 {
13786 bfd_size_type amt = sizeof *p;
13787
13788 p = (struct elf_dyn_relocs *) bfd_alloc (htab->root.dynobj, amt);
13789 if (p == NULL)
13790 return FALSE;
13791 p->next = *head;
13792 *head = p;
13793 p->sec = sec;
13794 p->count = 0;
13795 p->pc_count = 0;
13796 }
13797
469a3493 13798 if (elf32_arm_howto_from_type (r_type)->pc_relative)
f6e32f6d
RS		 13799 p->pc_count += 1;
13800 p->count += 1;
13801 }
252b5132 13802 }
f21f3fe0 13803
b34976b6 13804 return TRUE;
252b5132
RH		 13805}
13806
6a5bb875
PB		 13807/* Unwinding tables are not referenced directly. This pass marks them as
13808 required if the corresponding code section is marked. */
13809
13810static bfd_boolean
906e58ca
NC		 13811elf32_arm_gc_mark_extra_sections (struct bfd_link_info *info,
13812 elf_gc_mark_hook_fn gc_mark_hook)
6a5bb875
PB		 13813{
13814 bfd *sub;
13815 Elf_Internal_Shdr **elf_shdrp;
13816 bfd_boolean again;
13817
7f6ab9f8
AM		 13818 _bfd_elf_gc_mark_extra_sections (info, gc_mark_hook);
13819
6a5bb875
PB		 13820 /* Marking EH data may cause additional code sections to be marked,
13821 requiring multiple passes. */
13822 again = TRUE;
13823 while (again)
13824 {
13825 again = FALSE;
c72f2fb2 13826 for (sub = info->input_bfds; sub != NULL; sub = sub->link.next)
6a5bb875
PB		 13827 {
13828 asection *o;
13829
0ffa91dd 13830 if (! is_arm_elf (sub))
6a5bb875
PB		 13831 continue;
13832
13833 elf_shdrp = elf_elfsections (sub);
13834 for (o = sub->sections; o != NULL; o = o->next)
13835 {
13836 Elf_Internal_Shdr *hdr;
0ffa91dd 13837
6a5bb875 13838 hdr = &elf_section_data (o)->this_hdr;
4fbb74a6
AM		 13839 if (hdr->sh_type == SHT_ARM_EXIDX
13840 && hdr->sh_link
13841 && hdr->sh_link < elf_numsections (sub)
6a5bb875
PB		 13842 && !o->gc_mark
13843 && elf_shdrp[hdr->sh_link]->bfd_section->gc_mark)
13844 {
13845 again = TRUE;
13846 if (!_bfd_elf_gc_mark (info, o, gc_mark_hook))
13847 return FALSE;
13848 }
13849 }
13850 }
13851 }
13852
13853 return TRUE;
13854}
13855
3c9458e9
NC		 13856/* Treat mapping symbols as special target symbols. */
13857
13858static bfd_boolean
13859elf32_arm_is_target_special_symbol (bfd * abfd ATTRIBUTE_UNUSED, asymbol * sym)
13860{
b0796911
PB		 13861 return bfd_is_arm_special_symbol_name (sym->name,
13862 BFD_ARM_SPECIAL_SYM_TYPE_ANY);
3c9458e9
NC		 13863}
13864
0367ecfb
NC		 13865/* This is a copy of elf_find_function() from elf.c except that
13866 ARM mapping symbols are ignored when looking for function names
13867 and STT_ARM_TFUNC is considered to a function type. */
252b5132 13868
0367ecfb
NC		 13869static bfd_boolean
13870arm_elf_find_function (bfd * abfd ATTRIBUTE_UNUSED,
0367ecfb 13871 asymbol ** symbols,
fb167eb2 13872 asection * section,
0367ecfb
NC		 13873 bfd_vma offset,
13874 const char ** filename_ptr,
13875 const char ** functionname_ptr)
13876{
13877 const char * filename = NULL;
13878 asymbol * func = NULL;
13879 bfd_vma low_func = 0;
13880 asymbol ** p;
252b5132
RH		 13881
13882 for (p = symbols; *p != NULL; p++)
13883 {
13884 elf_symbol_type *q;
13885
13886 q = (elf_symbol_type *) *p;
13887
252b5132
RH		 13888 switch (ELF_ST_TYPE (q->internal_elf_sym.st_info))
13889 {
13890 default:
13891 break;
13892 case STT_FILE:
13893 filename = bfd_asymbol_name (&q->symbol);
13894 break;
252b5132
RH		 13895 case STT_FUNC:
13896 case STT_ARM_TFUNC:
9d2da7ca 13897 case STT_NOTYPE:
b0796911 13898 /* Skip mapping symbols. */
0367ecfb 13899 if ((q->symbol.flags & BSF_LOCAL)
b0796911
PB		 13900 && bfd_is_arm_special_symbol_name (q->symbol.name,
13901 BFD_ARM_SPECIAL_SYM_TYPE_ANY))
0367ecfb
NC		 13902 continue;
13903 /* Fall through. */
6b40fcba 13904 if (bfd_get_section (&q->symbol) == section
252b5132
RH		 13905 && q->symbol.value >= low_func
13906 && q->symbol.value <= offset)
13907 {
13908 func = (asymbol *) q;
13909 low_func = q->symbol.value;
13910 }
13911 break;
13912 }
13913 }
13914
13915 if (func == NULL)
b34976b6 13916 return FALSE;
252b5132 13917
0367ecfb
NC		 13918 if (filename_ptr)
13919 *filename_ptr = filename;
13920 if (functionname_ptr)
13921 *functionname_ptr = bfd_asymbol_name (func);
13922
13923 return TRUE;
906e58ca 13924}
0367ecfb
NC		 13925
13926
13927/* Find the nearest line to a particular section and offset, for error
13928 reporting. This code is a duplicate of the code in elf.c, except
13929 that it uses arm_elf_find_function. */
13930
13931static bfd_boolean
13932elf32_arm_find_nearest_line (bfd * abfd,
0367ecfb 13933 asymbol ** symbols,
fb167eb2 13934 asection * section,
0367ecfb
NC		 13935 bfd_vma offset,
13936 const char ** filename_ptr,
13937 const char ** functionname_ptr,
fb167eb2
AM		 13938 unsigned int * line_ptr,
13939 unsigned int * discriminator_ptr)
0367ecfb
NC		 13940{
13941 bfd_boolean found = FALSE;
13942
fb167eb2 13943 if (_bfd_dwarf2_find_nearest_line (abfd, symbols, NULL, section, offset,
0367ecfb 13944 filename_ptr, functionname_ptr,
fb167eb2
AM		 13945 line_ptr, discriminator_ptr,
13946 dwarf_debug_sections, 0,
0367ecfb
NC		 13947 & elf_tdata (abfd)->dwarf2_find_line_info))
13948 {
13949 if (!*functionname_ptr)
fb167eb2 13950 arm_elf_find_function (abfd, symbols, section, offset,
0367ecfb
NC		 13951 *filename_ptr ? NULL : filename_ptr,
13952 functionname_ptr);
f21f3fe0 13953
0367ecfb
NC		 13954 return TRUE;
13955 }
13956
fb167eb2
AM		 13957 /* Skip _bfd_dwarf1_find_nearest_line since no known ARM toolchain
13958 uses DWARF1. */
13959
0367ecfb
NC		 13960 if (! _bfd_stab_section_find_nearest_line (abfd, symbols, section, offset,
13961 & found, filename_ptr,
13962 functionname_ptr, line_ptr,
13963 & elf_tdata (abfd)->line_info))
13964 return FALSE;
13965
13966 if (found && (*functionname_ptr || *line_ptr))
13967 return TRUE;
13968
13969 if (symbols == NULL)
13970 return FALSE;
13971
fb167eb2 13972 if (! arm_elf_find_function (abfd, symbols, section, offset,
0367ecfb
NC		 13973 filename_ptr, functionname_ptr))
13974 return FALSE;
13975
13976 *line_ptr = 0;
b34976b6 13977 return TRUE;
252b5132
RH		 13978}
13979
4ab527b0
FF		 13980static bfd_boolean
13981elf32_arm_find_inliner_info (bfd * abfd,
13982 const char ** filename_ptr,
13983 const char ** functionname_ptr,
13984 unsigned int * line_ptr)
13985{
13986 bfd_boolean found;
13987 found = _bfd_dwarf2_find_inliner_info (abfd, filename_ptr,
13988 functionname_ptr, line_ptr,
13989 & elf_tdata (abfd)->dwarf2_find_line_info);
13990 return found;
13991}
13992
252b5132
RH		 13993/* Adjust a symbol defined by a dynamic object and referenced by a
13994 regular object. The current definition is in some section of the
13995 dynamic object, but we're not including those sections. We have to
13996 change the definition to something the rest of the link can
13997 understand. */
13998
b34976b6 13999static bfd_boolean
57e8b36a
NC		 14000elf32_arm_adjust_dynamic_symbol (struct bfd_link_info * info,
14001 struct elf_link_hash_entry * h)
252b5132
RH		 14002{
14003 bfd * dynobj;
14004 asection * s;
b7693d02 14005 struct elf32_arm_link_hash_entry * eh;
67687978 14006 struct elf32_arm_link_hash_table *globals;
252b5132 14007
67687978 14008 globals = elf32_arm_hash_table (info);
4dfe6ac6
NC		 14009 if (globals == NULL)
14010 return FALSE;
14011
252b5132
RH		 14012 dynobj = elf_hash_table (info)->dynobj;
14013
14014 /* Make sure we know what is going on here. */
14015 BFD_ASSERT (dynobj != NULL
f5385ebf 14016 && (h->needs_plt
34e77a92 14017 || h->type == STT_GNU_IFUNC
f6e332e6 14018 || h->u.weakdef != NULL
f5385ebf
AM		 14019 || (h->def_dynamic
14020 && h->ref_regular
14021 && !h->def_regular)));
252b5132 14022
b7693d02
DJ		 14023 eh = (struct elf32_arm_link_hash_entry *) h;
14024
252b5132
RH		 14025 /* If this is a function, put it in the procedure linkage table. We
14026 will fill in the contents of the procedure linkage table later,
14027 when we know the address of the .got section. */
34e77a92 14028 if (h->type == STT_FUNC || h->type == STT_GNU_IFUNC || h->needs_plt)
252b5132 14029 {
34e77a92
RS		 14030 /* Calls to STT_GNU_IFUNC symbols always use a PLT, even if the
14031 symbol binds locally. */
5e681ec4 14032 if (h->plt.refcount <= 0
34e77a92
RS		 14033 || (h->type != STT_GNU_IFUNC
14034 && (SYMBOL_CALLS_LOCAL (info, h)
14035 || (ELF_ST_VISIBILITY (h->other) != STV_DEFAULT
14036 && h->root.type == bfd_link_hash_undefweak))))
252b5132
RH		 14037 {
14038 /* This case can occur if we saw a PLT32 reloc in an input
5e681ec4
PB		 14039 file, but the symbol was never referred to by a dynamic
14040 object, or if all references were garbage collected. In
14041 such a case, we don't actually need to build a procedure
14042 linkage table, and we can just do a PC24 reloc instead. */
14043 h->plt.offset = (bfd_vma) -1;
34e77a92
RS		 14044 eh->plt.thumb_refcount = 0;
14045 eh->plt.maybe_thumb_refcount = 0;
14046 eh->plt.noncall_refcount = 0;
f5385ebf 14047 h->needs_plt = 0;
252b5132
RH		 14048 }
14049
b34976b6 14050 return TRUE;
252b5132 14051 }
5e681ec4 14052 else
b7693d02
DJ		 14053 {
14054 /* It's possible that we incorrectly decided a .plt reloc was
14055 needed for an R_ARM_PC24 or similar reloc to a non-function sym
14056 in check_relocs. We can't decide accurately between function
14057 and non-function syms in check-relocs; Objects loaded later in
14058 the link may change h->type. So fix it now. */
14059 h->plt.offset = (bfd_vma) -1;
34e77a92
RS		 14060 eh->plt.thumb_refcount = 0;
14061 eh->plt.maybe_thumb_refcount = 0;
14062 eh->plt.noncall_refcount = 0;
b7693d02 14063 }
252b5132
RH		 14064
14065 /* If this is a weak symbol, and there is a real definition, the
14066 processor independent code will have arranged for us to see the
14067 real definition first, and we can just use the same value. */
f6e332e6 14068 if (h->u.weakdef != NULL)
252b5132 14069 {
f6e332e6
AM		 14070 BFD_ASSERT (h->u.weakdef->root.type == bfd_link_hash_defined
14071 || h->u.weakdef->root.type == bfd_link_hash_defweak);
14072 h->root.u.def.section = h->u.weakdef->root.u.def.section;
14073 h->root.u.def.value = h->u.weakdef->root.u.def.value;
b34976b6 14074 return TRUE;
252b5132
RH		 14075 }
14076
ba93b8ac
DJ		 14077 /* If there are no non-GOT references, we do not need a copy
14078 relocation. */
14079 if (!h->non_got_ref)
14080 return TRUE;
14081
252b5132
RH		 14082 /* This is a reference to a symbol defined by a dynamic object which
14083 is not a function. */
14084
14085 /* If we are creating a shared library, we must presume that the
14086 only references to the symbol are via the global offset table.
14087 For such cases we need not do anything here; the relocations will
67687978
PB		 14088 be handled correctly by relocate_section. Relocatable executables
14089 can reference data in shared objects directly, so we don't need to
14090 do anything here. */
0e1862bb 14091 if (bfd_link_pic (info) || globals->root.is_relocatable_executable)
b34976b6 14092 return TRUE;
252b5132
RH		 14093
14094 /* We must allocate the symbol in our .dynbss section, which will
14095 become part of the .bss section of the executable. There will be
14096 an entry for this symbol in the .dynsym section. The dynamic
14097 object will contain position independent code, so all references
14098 from the dynamic object to this symbol will go through the global
14099 offset table. The dynamic linker will use the .dynsym entry to
14100 determine the address it must put in the global offset table, so
14101 both the dynamic object and the regular object will refer to the
14102 same memory location for the variable. */
3d4d4302 14103 s = bfd_get_linker_section (dynobj, ".dynbss");
252b5132
RH		 14104 BFD_ASSERT (s != NULL);
14105
14106 /* We must generate a R_ARM_COPY reloc to tell the dynamic linker to
14107 copy the initial value out of the dynamic object and into the
14108 runtime process image. We need to remember the offset into the
00a97672 14109 .rel(a).bss section we are going to use. */
1d7e9d18 14110 if ((h->root.u.def.section->flags & SEC_ALLOC) != 0 && h->size != 0)
252b5132
RH		 14111 {
14112 asection *srel;
14113
3d4d4302 14114 srel = bfd_get_linker_section (dynobj, RELOC_SECTION (globals, ".bss"));
47beaa6a 14115 elf32_arm_allocate_dynrelocs (info, srel, 1);
f5385ebf 14116 h->needs_copy = 1;
252b5132
RH		 14117 }
14118
6cabe1ea 14119 return _bfd_elf_adjust_dynamic_copy (info, h, s);
252b5132
RH		 14120}
14121
5e681ec4
PB		 14122/* Allocate space in .plt, .got and associated reloc sections for
14123 dynamic relocs. */
14124
14125static bfd_boolean
47beaa6a 14126allocate_dynrelocs_for_symbol (struct elf_link_hash_entry *h, void * inf)
5e681ec4
PB		 14127{
14128 struct bfd_link_info *info;
14129 struct elf32_arm_link_hash_table *htab;
14130 struct elf32_arm_link_hash_entry *eh;
0bdcacaf 14131 struct elf_dyn_relocs *p;
5e681ec4
PB		 14132
14133 if (h->root.type == bfd_link_hash_indirect)
14134 return TRUE;
14135
e6a6bb22
AM		 14136 eh = (struct elf32_arm_link_hash_entry *) h;
14137
5e681ec4
PB		 14138 info = (struct bfd_link_info *) inf;
14139 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 14140 if (htab == NULL)
14141 return FALSE;
5e681ec4 14142
34e77a92 14143 if ((htab->root.dynamic_sections_created || h->type == STT_GNU_IFUNC)
5e681ec4
PB		 14144 && h->plt.refcount > 0)
14145 {
14146 /* Make sure this symbol is output as a dynamic symbol.
14147 Undefined weak syms won't yet be marked as dynamic. */
14148 if (h->dynindx == -1
f5385ebf 14149 && !h->forced_local)
5e681ec4 14150 {
c152c796 14151 if (! bfd_elf_link_record_dynamic_symbol (info, h))
5e681ec4
PB		 14152 return FALSE;
14153 }
14154
34e77a92
RS		 14155 /* If the call in the PLT entry binds locally, the associated
14156 GOT entry should use an R_ARM_IRELATIVE relocation instead of
14157 the usual R_ARM_JUMP_SLOT. Put it in the .iplt section rather
14158 than the .plt section. */
14159 if (h->type == STT_GNU_IFUNC && SYMBOL_CALLS_LOCAL (info, h))
14160 {
14161 eh->is_iplt = 1;
14162 if (eh->plt.noncall_refcount == 0
14163 && SYMBOL_REFERENCES_LOCAL (info, h))
14164 /* All non-call references can be resolved directly.
14165 This means that they can (and in some cases, must)
14166 resolve directly to the run-time target, rather than
14167 to the PLT. That in turns means that any .got entry
14168 would be equal to the .igot.plt entry, so there's
14169 no point having both. */
14170 h->got.refcount = 0;
14171 }
14172
0e1862bb 14173 if (bfd_link_pic (info)
34e77a92 14174 || eh->is_iplt
7359ea65 14175 || WILL_CALL_FINISH_DYNAMIC_SYMBOL (1, 0, h))
5e681ec4 14176 {
34e77a92 14177 elf32_arm_allocate_plt_entry (info, eh->is_iplt, &h->plt, &eh->plt);
b7693d02 14178
5e681ec4
PB		 14179 /* If this symbol is not defined in a regular file, and we are
14180 not generating a shared library, then set the symbol to this
14181 location in the .plt. This is required to make function
14182 pointers compare as equal between the normal executable and
14183 the shared library. */
0e1862bb 14184 if (! bfd_link_pic (info)
f5385ebf 14185 && !h->def_regular)
5e681ec4 14186 {
34e77a92 14187 h->root.u.def.section = htab->root.splt;
5e681ec4 14188 h->root.u.def.value = h->plt.offset;
5e681ec4 14189
67d74e43
DJ		 14190 /* Make sure the function is not marked as Thumb, in case
14191 it is the target of an ABS32 relocation, which will
14192 point to the PLT entry. */
35fc36a8 14193 h->target_internal = ST_BRANCH_TO_ARM;
67d74e43 14194 }
022f8312 14195
00a97672
RS		 14196 /* VxWorks executables have a second set of relocations for
14197 each PLT entry. They go in a separate relocation section,
14198 which is processed by the kernel loader. */
0e1862bb 14199 if (htab->vxworks_p && !bfd_link_pic (info))
00a97672
RS		 14200 {
14201 /* There is a relocation for the initial PLT entry:
14202 an R_ARM_32 relocation for _GLOBAL_OFFSET_TABLE_. */
14203 if (h->plt.offset == htab->plt_header_size)
47beaa6a 14204 elf32_arm_allocate_dynrelocs (info, htab->srelplt2, 1);
00a97672
RS		 14205
14206 /* There are two extra relocations for each subsequent
14207 PLT entry: an R_ARM_32 relocation for the GOT entry,
14208 and an R_ARM_32 relocation for the PLT entry. */
47beaa6a 14209 elf32_arm_allocate_dynrelocs (info, htab->srelplt2, 2);
00a97672 14210 }
5e681ec4
PB		 14211 }
14212 else
14213 {
14214 h->plt.offset = (bfd_vma) -1;
f5385ebf 14215 h->needs_plt = 0;
5e681ec4
PB		 14216 }
14217 }
14218 else
14219 {
14220 h->plt.offset = (bfd_vma) -1;
f5385ebf 14221 h->needs_plt = 0;
5e681ec4
PB		 14222 }
14223
0855e32b
NS		 14224 eh = (struct elf32_arm_link_hash_entry *) h;
14225 eh->tlsdesc_got = (bfd_vma) -1;
14226
5e681ec4
PB		 14227 if (h->got.refcount > 0)
14228 {
14229 asection *s;
14230 bfd_boolean dyn;
ba93b8ac
DJ		 14231 int tls_type = elf32_arm_hash_entry (h)->tls_type;
14232 int indx;
5e681ec4
PB		 14233
14234 /* Make sure this symbol is output as a dynamic symbol.
14235 Undefined weak syms won't yet be marked as dynamic. */
14236 if (h->dynindx == -1
f5385ebf 14237 && !h->forced_local)
5e681ec4 14238 {
c152c796 14239 if (! bfd_elf_link_record_dynamic_symbol (info, h))
5e681ec4
PB		 14240 return FALSE;
14241 }
14242
e5a52504
MM		 14243 if (!htab->symbian_p)
14244 {
362d30a1 14245 s = htab->root.sgot;
e5a52504 14246 h->got.offset = s->size;
ba93b8ac
DJ		 14247
14248 if (tls_type == GOT_UNKNOWN)
14249 abort ();
14250
14251 if (tls_type == GOT_NORMAL)
14252 /* Non-TLS symbols need one GOT slot. */
14253 s->size += 4;
14254 else
14255 {
99059e56
RM		 14256 if (tls_type & GOT_TLS_GDESC)
14257 {
0855e32b 14258 /* R_ARM_TLS_DESC needs 2 GOT slots. */
99059e56 14259 eh->tlsdesc_got
0855e32b
NS		 14260 = (htab->root.sgotplt->size
14261 - elf32_arm_compute_jump_table_size (htab));
99059e56
RM		 14262 htab->root.sgotplt->size += 8;
14263 h->got.offset = (bfd_vma) -2;
34e77a92 14264 /* plt.got_offset needs to know there's a TLS_DESC
0855e32b 14265 reloc in the middle of .got.plt. */
99059e56
RM		 14266 htab->num_tls_desc++;
14267 }
0855e32b 14268
ba93b8ac 14269 if (tls_type & GOT_TLS_GD)
0855e32b
NS		 14270 {
14271 /* R_ARM_TLS_GD32 needs 2 consecutive GOT slots. If
14272 the symbol is both GD and GDESC, got.offset may
14273 have been overwritten. */
14274 h->got.offset = s->size;
14275 s->size += 8;
14276 }
14277
ba93b8ac
DJ		 14278 if (tls_type & GOT_TLS_IE)
14279 /* R_ARM_TLS_IE32 needs one GOT slot. */
14280 s->size += 4;
14281 }
14282
e5a52504 14283 dyn = htab->root.dynamic_sections_created;
ba93b8ac
DJ		 14284
14285 indx = 0;
0e1862bb
L		 14286 if (WILL_CALL_FINISH_DYNAMIC_SYMBOL (dyn,
14287 bfd_link_pic (info),
14288 h)
14289 && (!bfd_link_pic (info)
ba93b8ac
DJ		 14290 || !SYMBOL_REFERENCES_LOCAL (info, h)))
14291 indx = h->dynindx;
14292
14293 if (tls_type != GOT_NORMAL
0e1862bb 14294 && (bfd_link_pic (info) || indx != 0)
ba93b8ac
DJ		 14295 && (ELF_ST_VISIBILITY (h->other) == STV_DEFAULT
14296 || h->root.type != bfd_link_hash_undefweak))
14297 {
14298 if (tls_type & GOT_TLS_IE)
47beaa6a 14299 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
ba93b8ac
DJ		 14300
14301 if (tls_type & GOT_TLS_GD)
47beaa6a 14302 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
ba93b8ac 14303
b38cadfb 14304 if (tls_type & GOT_TLS_GDESC)
0855e32b 14305 {
47beaa6a 14306 elf32_arm_allocate_dynrelocs (info, htab->root.srelplt, 1);
0855e32b
NS		 14307 /* GDESC needs a trampoline to jump to. */
14308 htab->tls_trampoline = -1;
14309 }
14310
14311 /* Only GD needs it. GDESC just emits one relocation per
14312 2 entries. */
b38cadfb 14313 if ((tls_type & GOT_TLS_GD) && indx != 0)
47beaa6a 14314 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
ba93b8ac 14315 }
6f820c85 14316 else if (indx != -1 && !SYMBOL_REFERENCES_LOCAL (info, h))
b436d854
RS		 14317 {
14318 if (htab->root.dynamic_sections_created)
14319 /* Reserve room for the GOT entry's R_ARM_GLOB_DAT relocation. */
14320 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
14321 }
34e77a92
RS		 14322 else if (h->type == STT_GNU_IFUNC
14323 && eh->plt.noncall_refcount == 0)
14324 /* No non-call references resolve the STT_GNU_IFUNC's PLT entry;
14325 they all resolve dynamically instead. Reserve room for the
14326 GOT entry's R_ARM_IRELATIVE relocation. */
14327 elf32_arm_allocate_irelocs (info, htab->root.srelgot, 1);
0e1862bb
L		 14328 else if (bfd_link_pic (info)
14329 && (ELF_ST_VISIBILITY (h->other) == STV_DEFAULT
14330 || h->root.type != bfd_link_hash_undefweak))
b436d854 14331 /* Reserve room for the GOT entry's R_ARM_RELATIVE relocation. */
47beaa6a 14332 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
e5a52504 14333 }
5e681ec4
PB		 14334 }
14335 else
14336 h->got.offset = (bfd_vma) -1;
14337
a4fd1a8e
PB		 14338 /* Allocate stubs for exported Thumb functions on v4t. */
14339 if (!htab->use_blx && h->dynindx != -1
0eaedd0e 14340 && h->def_regular
35fc36a8 14341 && h->target_internal == ST_BRANCH_TO_THUMB
a4fd1a8e
PB		 14342 && ELF_ST_VISIBILITY (h->other) == STV_DEFAULT)
14343 {
14344 struct elf_link_hash_entry * th;
14345 struct bfd_link_hash_entry * bh;
14346 struct elf_link_hash_entry * myh;
14347 char name[1024];
14348 asection *s;
14349 bh = NULL;
14350 /* Create a new symbol to regist the real location of the function. */
14351 s = h->root.u.def.section;
906e58ca 14352 sprintf (name, "__real_%s", h->root.root.string);
a4fd1a8e
PB		 14353 _bfd_generic_link_add_one_symbol (info, s->owner,
14354 name, BSF_GLOBAL, s,
14355 h->root.u.def.value,
14356 NULL, TRUE, FALSE, &bh);
14357
14358 myh = (struct elf_link_hash_entry *) bh;
35fc36a8 14359 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
a4fd1a8e 14360 myh->forced_local = 1;
35fc36a8 14361 myh->target_internal = ST_BRANCH_TO_THUMB;
a4fd1a8e
PB		 14362 eh->export_glue = myh;
14363 th = record_arm_to_thumb_glue (info, h);
14364 /* Point the symbol at the stub. */
14365 h->type = ELF_ST_INFO (ELF_ST_BIND (h->type), STT_FUNC);
35fc36a8 14366 h->target_internal = ST_BRANCH_TO_ARM;
a4fd1a8e
PB		 14367 h->root.u.def.section = th->root.u.def.section;
14368 h->root.u.def.value = th->root.u.def.value & ~1;
14369 }
14370
0bdcacaf 14371 if (eh->dyn_relocs == NULL)
5e681ec4
PB		 14372 return TRUE;
14373
14374 /* In the shared -Bsymbolic case, discard space allocated for
14375 dynamic pc-relative relocs against symbols which turn out to be
14376 defined in regular objects. For the normal shared case, discard
14377 space for pc-relative relocs that have become local due to symbol
14378 visibility changes. */
14379
0e1862bb 14380 if (bfd_link_pic (info) || htab->root.is_relocatable_executable)
5e681ec4 14381 {
469a3493
RM		 14382 /* Relocs that use pc_count are PC-relative forms, which will appear
14383 on something like ".long foo - ." or "movw REG, foo - .". We want
14384 calls to protected symbols to resolve directly to the function
14385 rather than going via the plt. If people want function pointer
14386 comparisons to work as expected then they should avoid writing
14387 assembly like ".long foo - .". */
ba93b8ac
DJ		 14388 if (SYMBOL_CALLS_LOCAL (info, h))
14389 {
0bdcacaf 14390 struct elf_dyn_relocs **pp;
ba93b8ac 14391
0bdcacaf 14392 for (pp = &eh->dyn_relocs; (p = *pp) != NULL; )
ba93b8ac
DJ		 14393 {
14394 p->count -= p->pc_count;
14395 p->pc_count = 0;
14396 if (p->count == 0)
14397 *pp = p->next;
14398 else
14399 pp = &p->next;
14400 }
14401 }
14402
4dfe6ac6 14403 if (htab->vxworks_p)
3348747a 14404 {
0bdcacaf 14405 struct elf_dyn_relocs **pp;
3348747a 14406
0bdcacaf 14407 for (pp = &eh->dyn_relocs; (p = *pp) != NULL; )
3348747a 14408 {
0bdcacaf 14409 if (strcmp (p->sec->output_section->name, ".tls_vars") == 0)
3348747a
NS		 14410 *pp = p->next;
14411 else
14412 pp = &p->next;
14413 }
14414 }
14415
ba93b8ac 14416 /* Also discard relocs on undefined weak syms with non-default
99059e56 14417 visibility. */
0bdcacaf 14418 if (eh->dyn_relocs != NULL
5e681ec4 14419 && h->root.type == bfd_link_hash_undefweak)
22d606e9
AM		 14420 {
14421 if (ELF_ST_VISIBILITY (h->other) != STV_DEFAULT)
0bdcacaf 14422 eh->dyn_relocs = NULL;
22d606e9
AM		 14423
14424 /* Make sure undefined weak symbols are output as a dynamic
14425 symbol in PIEs. */
14426 else if (h->dynindx == -1
14427 && !h->forced_local)
14428 {
14429 if (! bfd_elf_link_record_dynamic_symbol (info, h))
14430 return FALSE;
14431 }
14432 }
14433
67687978
PB		 14434 else if (htab->root.is_relocatable_executable && h->dynindx == -1
14435 && h->root.type == bfd_link_hash_new)
14436 {
14437 /* Output absolute symbols so that we can create relocations
14438 against them. For normal symbols we output a relocation
14439 against the section that contains them. */
14440 if (! bfd_elf_link_record_dynamic_symbol (info, h))
14441 return FALSE;
14442 }
14443
5e681ec4
PB		 14444 }
14445 else
14446 {
14447 /* For the non-shared case, discard space for relocs against
14448 symbols which turn out to need copy relocs or are not
14449 dynamic. */
14450
f5385ebf
AM		 14451 if (!h->non_got_ref
14452 && ((h->def_dynamic
14453 && !h->def_regular)
5e681ec4
PB		 14454 || (htab->root.dynamic_sections_created
14455 && (h->root.type == bfd_link_hash_undefweak
14456 || h->root.type == bfd_link_hash_undefined))))
14457 {
14458 /* Make sure this symbol is output as a dynamic symbol.
14459 Undefined weak syms won't yet be marked as dynamic. */
14460 if (h->dynindx == -1
f5385ebf 14461 && !h->forced_local)
5e681ec4 14462 {
c152c796 14463 if (! bfd_elf_link_record_dynamic_symbol (info, h))
5e681ec4
PB		 14464 return FALSE;
14465 }
14466
14467 /* If that succeeded, we know we'll be keeping all the
14468 relocs. */
14469 if (h->dynindx != -1)
14470 goto keep;
14471 }
14472
0bdcacaf 14473 eh->dyn_relocs = NULL;
5e681ec4
PB		 14474
14475 keep: ;
14476 }
14477
14478 /* Finally, allocate space. */
0bdcacaf 14479 for (p = eh->dyn_relocs; p != NULL; p = p->next)
5e681ec4 14480 {
0bdcacaf 14481 asection *sreloc = elf_section_data (p->sec)->sreloc;
34e77a92
RS		 14482 if (h->type == STT_GNU_IFUNC
14483 && eh->plt.noncall_refcount == 0
14484 && SYMBOL_REFERENCES_LOCAL (info, h))
14485 elf32_arm_allocate_irelocs (info, sreloc, p->count);
14486 else
14487 elf32_arm_allocate_dynrelocs (info, sreloc, p->count);
5e681ec4
PB		 14488 }
14489
14490 return TRUE;
14491}
14492
08d1f311
DJ		 14493/* Find any dynamic relocs that apply to read-only sections. */
14494
14495static bfd_boolean
8029a119 14496elf32_arm_readonly_dynrelocs (struct elf_link_hash_entry * h, void * inf)
08d1f311 14497{
8029a119 14498 struct elf32_arm_link_hash_entry * eh;
0bdcacaf 14499 struct elf_dyn_relocs * p;
08d1f311 14500
08d1f311 14501 eh = (struct elf32_arm_link_hash_entry *) h;
0bdcacaf 14502 for (p = eh->dyn_relocs; p != NULL; p = p->next)
08d1f311 14503 {
0bdcacaf 14504 asection *s = p->sec;
08d1f311
DJ		 14505
14506 if (s != NULL && (s->flags & SEC_READONLY) != 0)
14507 {
14508 struct bfd_link_info *info = (struct bfd_link_info *) inf;
14509
14510 info->flags |= DF_TEXTREL;
14511
14512 /* Not an error, just cut short the traversal. */
14513 return FALSE;
14514 }
14515 }
14516 return TRUE;
14517}
14518
d504ffc8
DJ		 14519void
14520bfd_elf32_arm_set_byteswap_code (struct bfd_link_info *info,
14521 int byteswap_code)
14522{
14523 struct elf32_arm_link_hash_table *globals;
14524
14525 globals = elf32_arm_hash_table (info);
4dfe6ac6
NC		 14526 if (globals == NULL)
14527 return;
14528
d504ffc8
DJ		 14529 globals->byteswap_code = byteswap_code;
14530}
14531
252b5132
RH		 14532/* Set the sizes of the dynamic sections. */
14533
b34976b6 14534static bfd_boolean
57e8b36a
NC		 14535elf32_arm_size_dynamic_sections (bfd * output_bfd ATTRIBUTE_UNUSED,
14536 struct bfd_link_info * info)
252b5132
RH		 14537{
14538 bfd * dynobj;
14539 asection * s;
b34976b6
AM		 14540 bfd_boolean plt;
14541 bfd_boolean relocs;
5e681ec4
PB		 14542 bfd *ibfd;
14543 struct elf32_arm_link_hash_table *htab;
252b5132 14544
5e681ec4 14545 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 14546 if (htab == NULL)
14547 return FALSE;
14548
252b5132
RH		 14549 dynobj = elf_hash_table (info)->dynobj;
14550 BFD_ASSERT (dynobj != NULL);
39b41c9c 14551 check_use_blx (htab);
252b5132
RH		 14552
14553 if (elf_hash_table (info)->dynamic_sections_created)
14554 {
14555 /* Set the contents of the .interp section to the interpreter. */
9b8b325a 14556 if (bfd_link_executable (info) && !info->nointerp)
252b5132 14557 {
3d4d4302 14558 s = bfd_get_linker_section (dynobj, ".interp");
252b5132 14559 BFD_ASSERT (s != NULL);
eea6121a 14560 s->size = sizeof ELF_DYNAMIC_INTERPRETER;
252b5132
RH		 14561 s->contents = (unsigned char *) ELF_DYNAMIC_INTERPRETER;
14562 }
14563 }
5e681ec4
PB		 14564
14565 /* Set up .got offsets for local syms, and space for local dynamic
14566 relocs. */
c72f2fb2 14567 for (ibfd = info->input_bfds; ibfd != NULL; ibfd = ibfd->link.next)
252b5132 14568 {
5e681ec4
PB		 14569 bfd_signed_vma *local_got;
14570 bfd_signed_vma *end_local_got;
34e77a92 14571 struct arm_local_iplt_info **local_iplt_ptr, *local_iplt;
5e681ec4 14572 char *local_tls_type;
0855e32b 14573 bfd_vma *local_tlsdesc_gotent;
5e681ec4
PB		 14574 bfd_size_type locsymcount;
14575 Elf_Internal_Shdr *symtab_hdr;
14576 asection *srel;
4dfe6ac6 14577 bfd_boolean is_vxworks = htab->vxworks_p;
34e77a92 14578 unsigned int symndx;
5e681ec4 14579
0ffa91dd 14580 if (! is_arm_elf (ibfd))
5e681ec4
PB		 14581 continue;
14582
14583 for (s = ibfd->sections; s != NULL; s = s->next)
14584 {
0bdcacaf 14585 struct elf_dyn_relocs *p;
5e681ec4 14586
0bdcacaf 14587 for (p = (struct elf_dyn_relocs *)
99059e56 14588 elf_section_data (s)->local_dynrel; p != NULL; p = p->next)
5e681ec4 14589 {
0bdcacaf
RS		 14590 if (!bfd_is_abs_section (p->sec)
14591 && bfd_is_abs_section (p->sec->output_section))
5e681ec4
PB		 14592 {
14593 /* Input section has been discarded, either because
14594 it is a copy of a linkonce section or due to
14595 linker script /DISCARD/, so we'll be discarding
14596 the relocs too. */
14597 }
3348747a 14598 else if (is_vxworks
0bdcacaf 14599 && strcmp (p->sec->output_section->name,
3348747a
NS		 14600 ".tls_vars") == 0)
14601 {
14602 /* Relocations in vxworks .tls_vars sections are
14603 handled specially by the loader. */
14604 }
5e681ec4
PB		 14605 else if (p->count != 0)
14606 {
0bdcacaf 14607 srel = elf_section_data (p->sec)->sreloc;
47beaa6a 14608 elf32_arm_allocate_dynrelocs (info, srel, p->count);
0bdcacaf 14609 if ((p->sec->output_section->flags & SEC_READONLY) != 0)
5e681ec4
PB		 14610 info->flags |= DF_TEXTREL;
14611 }
14612 }
14613 }
14614
14615 local_got = elf_local_got_refcounts (ibfd);
14616 if (!local_got)
14617 continue;
14618
0ffa91dd 14619 symtab_hdr = & elf_symtab_hdr (ibfd);
5e681ec4
PB		 14620 locsymcount = symtab_hdr->sh_info;
14621 end_local_got = local_got + locsymcount;
34e77a92 14622 local_iplt_ptr = elf32_arm_local_iplt (ibfd);
ba93b8ac 14623 local_tls_type = elf32_arm_local_got_tls_type (ibfd);
0855e32b 14624 local_tlsdesc_gotent = elf32_arm_local_tlsdesc_gotent (ibfd);
34e77a92 14625 symndx = 0;
362d30a1
RS		 14626 s = htab->root.sgot;
14627 srel = htab->root.srelgot;
0855e32b 14628 for (; local_got < end_local_got;
34e77a92
RS		 14629 ++local_got, ++local_iplt_ptr, ++local_tls_type,
14630 ++local_tlsdesc_gotent, ++symndx)
5e681ec4 14631 {
0855e32b 14632 *local_tlsdesc_gotent = (bfd_vma) -1;
34e77a92
RS		 14633 local_iplt = *local_iplt_ptr;
14634 if (local_iplt != NULL)
14635 {
14636 struct elf_dyn_relocs *p;
14637
14638 if (local_iplt->root.refcount > 0)
14639 {
14640 elf32_arm_allocate_plt_entry (info, TRUE,
14641 &local_iplt->root,
14642 &local_iplt->arm);
14643 if (local_iplt->arm.noncall_refcount == 0)
14644 /* All references to the PLT are calls, so all
14645 non-call references can resolve directly to the
14646 run-time target. This means that the .got entry
14647 would be the same as the .igot.plt entry, so there's
14648 no point creating both. */
14649 *local_got = 0;
14650 }
14651 else
14652 {
14653 BFD_ASSERT (local_iplt->arm.noncall_refcount == 0);
14654 local_iplt->root.offset = (bfd_vma) -1;
14655 }
14656
14657 for (p = local_iplt->dyn_relocs; p != NULL; p = p->next)
14658 {
14659 asection *psrel;
14660
14661 psrel = elf_section_data (p->sec)->sreloc;
14662 if (local_iplt->arm.noncall_refcount == 0)
14663 elf32_arm_allocate_irelocs (info, psrel, p->count);
14664 else
14665 elf32_arm_allocate_dynrelocs (info, psrel, p->count);
14666 }
14667 }
5e681ec4
PB		 14668 if (*local_got > 0)
14669 {
34e77a92
RS		 14670 Elf_Internal_Sym *isym;
14671
eea6121a 14672 *local_got = s->size;
ba93b8ac
DJ		 14673 if (*local_tls_type & GOT_TLS_GD)
14674 /* TLS_GD relocs need an 8-byte structure in the GOT. */
14675 s->size += 8;
0855e32b
NS		 14676 if (*local_tls_type & GOT_TLS_GDESC)
14677 {
14678 *local_tlsdesc_gotent = htab->root.sgotplt->size
14679 - elf32_arm_compute_jump_table_size (htab);
14680 htab->root.sgotplt->size += 8;
14681 *local_got = (bfd_vma) -2;
34e77a92 14682 /* plt.got_offset needs to know there's a TLS_DESC
0855e32b 14683 reloc in the middle of .got.plt. */
99059e56 14684 htab->num_tls_desc++;
0855e32b 14685 }
ba93b8ac
DJ		 14686 if (*local_tls_type & GOT_TLS_IE)
14687 s->size += 4;
ba93b8ac 14688
0855e32b
NS		 14689 if (*local_tls_type & GOT_NORMAL)
14690 {
14691 /* If the symbol is both GD and GDESC, *local_got
14692 may have been overwritten. */
14693 *local_got = s->size;
14694 s->size += 4;
14695 }
14696
34e77a92
RS		 14697 isym = bfd_sym_from_r_symndx (&htab->sym_cache, ibfd, symndx);
14698 if (isym == NULL)
14699 return FALSE;
14700
14701 /* If all references to an STT_GNU_IFUNC PLT are calls,
14702 then all non-call references, including this GOT entry,
14703 resolve directly to the run-time target. */
14704 if (ELF32_ST_TYPE (isym->st_info) == STT_GNU_IFUNC
14705 && (local_iplt == NULL
14706 || local_iplt->arm.noncall_refcount == 0))
14707 elf32_arm_allocate_irelocs (info, srel, 1);
0e1862bb 14708 else if (bfd_link_pic (info) || output_bfd->flags & DYNAMIC)
0855e32b 14709 {
0e1862bb 14710 if ((bfd_link_pic (info) && !(*local_tls_type & GOT_TLS_GDESC))
3064e1ff
JB		 14711 || *local_tls_type & GOT_TLS_GD)
14712 elf32_arm_allocate_dynrelocs (info, srel, 1);
99059e56 14713
0e1862bb 14714 if (bfd_link_pic (info) && *local_tls_type & GOT_TLS_GDESC)
3064e1ff
JB		 14715 {
14716 elf32_arm_allocate_dynrelocs (info,
14717 htab->root.srelplt, 1);
14718 htab->tls_trampoline = -1;
14719 }
0855e32b 14720 }
5e681ec4
PB		 14721 }
14722 else
14723 *local_got = (bfd_vma) -1;
14724 }
252b5132
RH		 14725 }
14726
ba93b8ac
DJ		 14727 if (htab->tls_ldm_got.refcount > 0)
14728 {
14729 /* Allocate two GOT entries and one dynamic relocation (if necessary)
14730 for R_ARM_TLS_LDM32 relocations. */
362d30a1
RS		 14731 htab->tls_ldm_got.offset = htab->root.sgot->size;
14732 htab->root.sgot->size += 8;
0e1862bb 14733 if (bfd_link_pic (info))
47beaa6a 14734 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
ba93b8ac
DJ		 14735 }
14736 else
14737 htab->tls_ldm_got.offset = -1;
14738
5e681ec4
PB		 14739 /* Allocate global sym .plt and .got entries, and space for global
14740 sym dynamic relocs. */
47beaa6a 14741 elf_link_hash_traverse (& htab->root, allocate_dynrelocs_for_symbol, info);
252b5132 14742
d504ffc8 14743 /* Here we rummage through the found bfds to collect glue information. */
c72f2fb2 14744 for (ibfd = info->input_bfds; ibfd != NULL; ibfd = ibfd->link.next)
c7b8f16e 14745 {
0ffa91dd 14746 if (! is_arm_elf (ibfd))
e44a2c9c
AM		 14747 continue;
14748
c7b8f16e
JB		 14749 /* Initialise mapping tables for code/data. */
14750 bfd_elf32_arm_init_maps (ibfd);
906e58ca 14751
c7b8f16e 14752 if (!bfd_elf32_arm_process_before_allocation (ibfd, info)
a504d23a
LA		 14753 || !bfd_elf32_arm_vfp11_erratum_scan (ibfd, info)
14754 || !bfd_elf32_arm_stm32l4xx_erratum_scan (ibfd, info))
99059e56
RM		 14755 /* xgettext:c-format */
14756 _bfd_error_handler (_("Errors encountered processing file %s"),
c7b8f16e
JB		 14757 ibfd->filename);
14758 }
d504ffc8 14759
3e6b1042
DJ		 14760 /* Allocate space for the glue sections now that we've sized them. */
14761 bfd_elf32_arm_allocate_interworking_sections (info);
14762
0855e32b
NS		 14763 /* For every jump slot reserved in the sgotplt, reloc_count is
14764 incremented. However, when we reserve space for TLS descriptors,
14765 it's not incremented, so in order to compute the space reserved
14766 for them, it suffices to multiply the reloc count by the jump
14767 slot size. */
14768 if (htab->root.srelplt)
14769 htab->sgotplt_jump_table_size = elf32_arm_compute_jump_table_size(htab);
14770
14771 if (htab->tls_trampoline)
14772 {
14773 if (htab->root.splt->size == 0)
14774 htab->root.splt->size += htab->plt_header_size;
b38cadfb 14775
0855e32b
NS		 14776 htab->tls_trampoline = htab->root.splt->size;
14777 htab->root.splt->size += htab->plt_entry_size;
b38cadfb 14778
0855e32b 14779 /* If we're not using lazy TLS relocations, don't generate the
99059e56 14780 PLT and GOT entries they require. */
0855e32b
NS		 14781 if (!(info->flags & DF_BIND_NOW))
14782 {
14783 htab->dt_tlsdesc_got = htab->root.sgot->size;
14784 htab->root.sgot->size += 4;
14785
14786 htab->dt_tlsdesc_plt = htab->root.splt->size;
14787 htab->root.splt->size += 4 * ARRAY_SIZE (dl_tlsdesc_lazy_trampoline);
14788 }
14789 }
14790
252b5132
RH		 14791 /* The check_relocs and adjust_dynamic_symbol entry points have
14792 determined the sizes of the various dynamic sections. Allocate
14793 memory for them. */
b34976b6
AM		 14794 plt = FALSE;
14795 relocs = FALSE;
252b5132
RH		 14796 for (s = dynobj->sections; s != NULL; s = s->next)
14797 {
14798 const char * name;
252b5132
RH		 14799
14800 if ((s->flags & SEC_LINKER_CREATED) == 0)
14801 continue;
14802
14803 /* It's OK to base decisions on the section name, because none
14804 of the dynobj section names depend upon the input files. */
14805 name = bfd_get_section_name (dynobj, s);
14806
34e77a92 14807 if (s == htab->root.splt)
252b5132 14808 {
c456f082
AM		 14809 /* Remember whether there is a PLT. */
14810 plt = s->size != 0;
252b5132 14811 }
0112cd26 14812 else if (CONST_STRNEQ (name, ".rel"))
252b5132 14813 {
c456f082 14814 if (s->size != 0)
252b5132 14815 {
252b5132 14816 /* Remember whether there are any reloc sections other
00a97672 14817 than .rel(a).plt and .rela.plt.unloaded. */
362d30a1 14818 if (s != htab->root.srelplt && s != htab->srelplt2)
b34976b6 14819 relocs = TRUE;
252b5132
RH		 14820
14821 /* We use the reloc_count field as a counter if we need
14822 to copy relocs into the output file. */
14823 s->reloc_count = 0;
14824 }
14825 }
34e77a92
RS		 14826 else if (s != htab->root.sgot
14827 && s != htab->root.sgotplt
14828 && s != htab->root.iplt
14829 && s != htab->root.igotplt
14830 && s != htab->sdynbss)
252b5132
RH		 14831 {
14832 /* It's not one of our sections, so don't allocate space. */
14833 continue;
14834 }
14835
c456f082 14836 if (s->size == 0)
252b5132 14837 {
c456f082 14838 /* If we don't need this section, strip it from the
00a97672
RS		 14839 output file. This is mostly to handle .rel(a).bss and
14840 .rel(a).plt. We must create both sections in
c456f082
AM		 14841 create_dynamic_sections, because they must be created
14842 before the linker maps input sections to output
14843 sections. The linker does that before
14844 adjust_dynamic_symbol is called, and it is that
14845 function which decides whether anything needs to go
14846 into these sections. */
8423293d 14847 s->flags |= SEC_EXCLUDE;
252b5132
RH		 14848 continue;
14849 }
14850
c456f082
AM		 14851 if ((s->flags & SEC_HAS_CONTENTS) == 0)
14852 continue;
14853
252b5132 14854 /* Allocate memory for the section contents. */
21d799b5 14855 s->contents = (unsigned char *) bfd_zalloc (dynobj, s->size);
c456f082 14856 if (s->contents == NULL)
b34976b6 14857 return FALSE;
252b5132
RH		 14858 }
14859
14860 if (elf_hash_table (info)->dynamic_sections_created)
14861 {
14862 /* Add some entries to the .dynamic section. We fill in the
14863 values later, in elf32_arm_finish_dynamic_sections, but we
14864 must add the entries now so that we get the correct size for
14865 the .dynamic section. The DT_DEBUG entry is filled in by the
14866 dynamic linker and used by the debugger. */
dc810e39 14867#define add_dynamic_entry(TAG, VAL) \
5a580b3a 14868 _bfd_elf_add_dynamic_entry (info, TAG, VAL)
dc810e39 14869
0e1862bb 14870 if (bfd_link_executable (info))
252b5132 14871 {
dc810e39 14872 if (!add_dynamic_entry (DT_DEBUG, 0))
b34976b6 14873 return FALSE;
252b5132
RH		 14874 }
14875
14876 if (plt)
14877 {
dc810e39
AM		 14878 if ( !add_dynamic_entry (DT_PLTGOT, 0)
14879 || !add_dynamic_entry (DT_PLTRELSZ, 0)
00a97672
RS		 14880 || !add_dynamic_entry (DT_PLTREL,
14881 htab->use_rel ? DT_REL : DT_RELA)
dc810e39 14882 || !add_dynamic_entry (DT_JMPREL, 0))
b34976b6 14883 return FALSE;
0855e32b
NS		 14884
14885 if (htab->dt_tlsdesc_plt &&
b38cadfb 14886 (!add_dynamic_entry (DT_TLSDESC_PLT,0)
0855e32b 14887 || !add_dynamic_entry (DT_TLSDESC_GOT,0)))
b38cadfb 14888 return FALSE;
252b5132
RH		 14889 }
14890
14891 if (relocs)
14892 {
00a97672
RS		 14893 if (htab->use_rel)
14894 {
14895 if (!add_dynamic_entry (DT_REL, 0)
14896 || !add_dynamic_entry (DT_RELSZ, 0)
14897 || !add_dynamic_entry (DT_RELENT, RELOC_SIZE (htab)))
14898 return FALSE;
14899 }
14900 else
14901 {
14902 if (!add_dynamic_entry (DT_RELA, 0)
14903 || !add_dynamic_entry (DT_RELASZ, 0)
14904 || !add_dynamic_entry (DT_RELAENT, RELOC_SIZE (htab)))
14905 return FALSE;
14906 }
252b5132
RH		 14907 }
14908
08d1f311
DJ		 14909 /* If any dynamic relocs apply to a read-only section,
14910 then we need a DT_TEXTREL entry. */
14911 if ((info->flags & DF_TEXTREL) == 0)
8029a119
NC		 14912 elf_link_hash_traverse (& htab->root, elf32_arm_readonly_dynrelocs,
14913 info);
08d1f311 14914
99e4ae17 14915 if ((info->flags & DF_TEXTREL) != 0)
252b5132 14916 {
dc810e39 14917 if (!add_dynamic_entry (DT_TEXTREL, 0))
b34976b6 14918 return FALSE;
252b5132 14919 }
7a2b07ff
NS		 14920 if (htab->vxworks_p
14921 && !elf_vxworks_add_dynamic_entries (output_bfd, info))
14922 return FALSE;
252b5132 14923 }
8532796c 14924#undef add_dynamic_entry
252b5132 14925
b34976b6 14926 return TRUE;
252b5132
RH		 14927}
14928
0855e32b
NS		 14929/* Size sections even though they're not dynamic. We use it to setup
14930 _TLS_MODULE_BASE_, if needed. */
14931
14932static bfd_boolean
14933elf32_arm_always_size_sections (bfd *output_bfd,
99059e56 14934 struct bfd_link_info *info)
0855e32b
NS		 14935{
14936 asection *tls_sec;
14937
0e1862bb 14938 if (bfd_link_relocatable (info))
0855e32b
NS		 14939 return TRUE;
14940
14941 tls_sec = elf_hash_table (info)->tls_sec;
14942
14943 if (tls_sec)
14944 {
14945 struct elf_link_hash_entry *tlsbase;
14946
14947 tlsbase = elf_link_hash_lookup
14948 (elf_hash_table (info), "_TLS_MODULE_BASE_", TRUE, TRUE, FALSE);
14949
14950 if (tlsbase)
99059e56
RM		 14951 {
14952 struct bfd_link_hash_entry *bh = NULL;
0855e32b 14953 const struct elf_backend_data *bed
99059e56 14954 = get_elf_backend_data (output_bfd);
0855e32b 14955
99059e56 14956 if (!(_bfd_generic_link_add_one_symbol
0855e32b
NS		 14957 (info, output_bfd, "_TLS_MODULE_BASE_", BSF_LOCAL,
14958 tls_sec, 0, NULL, FALSE,
14959 bed->collect, &bh)))
14960 return FALSE;
b38cadfb 14961
99059e56
RM		 14962 tlsbase->type = STT_TLS;
14963 tlsbase = (struct elf_link_hash_entry *)bh;
14964 tlsbase->def_regular = 1;
14965 tlsbase->other = STV_HIDDEN;
14966 (*bed->elf_backend_hide_symbol) (info, tlsbase, TRUE);
0855e32b
NS		 14967 }
14968 }
14969 return TRUE;
14970}
14971
252b5132
RH		 14972/* Finish up dynamic symbol handling. We set the contents of various
14973 dynamic sections here. */
14974
b34976b6 14975static bfd_boolean
906e58ca
NC		 14976elf32_arm_finish_dynamic_symbol (bfd * output_bfd,
14977 struct bfd_link_info * info,
14978 struct elf_link_hash_entry * h,
14979 Elf_Internal_Sym * sym)
252b5132 14980{
e5a52504 14981 struct elf32_arm_link_hash_table *htab;
b7693d02 14982 struct elf32_arm_link_hash_entry *eh;
252b5132 14983
e5a52504 14984 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 14985 if (htab == NULL)
14986 return FALSE;
14987
b7693d02 14988 eh = (struct elf32_arm_link_hash_entry *) h;
252b5132
RH		 14989
14990 if (h->plt.offset != (bfd_vma) -1)
14991 {
34e77a92 14992 if (!eh->is_iplt)
e5a52504 14993 {
34e77a92 14994 BFD_ASSERT (h->dynindx != -1);
57460bcf
NC		 14995 if (! elf32_arm_populate_plt_entry (output_bfd, info, &h->plt, &eh->plt,
14996 h->dynindx, 0))
14997 return FALSE;
e5a52504 14998 }
57e8b36a 14999
f5385ebf 15000 if (!h->def_regular)
252b5132
RH		 15001 {
15002 /* Mark the symbol as undefined, rather than as defined in
3a635617 15003 the .plt section. */
252b5132 15004 sym->st_shndx = SHN_UNDEF;
3a635617 15005 /* If the symbol is weak we need to clear the value.
d982ba73
PB		 15006 Otherwise, the PLT entry would provide a definition for
15007 the symbol even if the symbol wasn't defined anywhere,
3a635617
WN		 15008 and so the symbol would never be NULL. Leave the value if
15009 there were any relocations where pointer equality matters
15010 (this is a clue for the dynamic linker, to make function
15011 pointer comparisons work between an application and shared
15012 library). */
97323ad1 15013 if (!h->ref_regular_nonweak || !h->pointer_equality_needed)
d982ba73 15014 sym->st_value = 0;
252b5132 15015 }
34e77a92
RS		 15016 else if (eh->is_iplt && eh->plt.noncall_refcount != 0)
15017 {
15018 /* At least one non-call relocation references this .iplt entry,
15019 so the .iplt entry is the function's canonical address. */
15020 sym->st_info = ELF_ST_INFO (ELF_ST_BIND (sym->st_info), STT_FUNC);
15021 sym->st_target_internal = ST_BRANCH_TO_ARM;
15022 sym->st_shndx = (_bfd_elf_section_from_bfd_section
15023 (output_bfd, htab->root.iplt->output_section));
15024 sym->st_value = (h->plt.offset
15025 + htab->root.iplt->output_section->vma
15026 + htab->root.iplt->output_offset);
15027 }
252b5132
RH		 15028 }
15029
f5385ebf 15030 if (h->needs_copy)
252b5132
RH		 15031 {
15032 asection * s;
947216bf 15033 Elf_Internal_Rela rel;
252b5132
RH		 15034
15035 /* This symbol needs a copy reloc. Set it up. */
252b5132
RH		 15036 BFD_ASSERT (h->dynindx != -1
15037 && (h->root.type == bfd_link_hash_defined
15038 || h->root.type == bfd_link_hash_defweak));
15039
362d30a1 15040 s = htab->srelbss;
252b5132
RH		 15041 BFD_ASSERT (s != NULL);
15042
00a97672 15043 rel.r_addend = 0;
252b5132
RH		 15044 rel.r_offset = (h->root.u.def.value
15045 + h->root.u.def.section->output_section->vma
15046 + h->root.u.def.section->output_offset);
15047 rel.r_info = ELF32_R_INFO (h->dynindx, R_ARM_COPY);
47beaa6a 15048 elf32_arm_add_dynreloc (output_bfd, info, s, &rel);
252b5132
RH		 15049 }
15050
00a97672
RS		 15051 /* Mark _DYNAMIC and _GLOBAL_OFFSET_TABLE_ as absolute. On VxWorks,
15052 the _GLOBAL_OFFSET_TABLE_ symbol is not absolute: it is relative
15053 to the ".got" section. */
9637f6ef 15054 if (h == htab->root.hdynamic
00a97672 15055 || (!htab->vxworks_p && h == htab->root.hgot))
252b5132
RH		 15056 sym->st_shndx = SHN_ABS;
15057
b34976b6 15058 return TRUE;
252b5132
RH		 15059}
15060
0855e32b
NS		 15061static void
15062arm_put_trampoline (struct elf32_arm_link_hash_table *htab, bfd *output_bfd,
15063 void *contents,
15064 const unsigned long *template, unsigned count)
15065{
15066 unsigned ix;
b38cadfb 15067
0855e32b
NS		 15068 for (ix = 0; ix != count; ix++)
15069 {
15070 unsigned long insn = template[ix];
15071
15072 /* Emit mov pc,rx if bx is not permitted. */
15073 if (htab->fix_v4bx == 1 && (insn & 0x0ffffff0) == 0x012fff10)
15074 insn = (insn & 0xf000000f) | 0x01a0f000;
15075 put_arm_insn (htab, output_bfd, insn, (char *)contents + ix*4);
15076 }
15077}
15078
99059e56
RM		 15079/* Install the special first PLT entry for elf32-arm-nacl. Unlike
15080 other variants, NaCl needs this entry in a static executable's
15081 .iplt too. When we're handling that case, GOT_DISPLACEMENT is
15082 zero. For .iplt really only the last bundle is useful, and .iplt
15083 could have a shorter first entry, with each individual PLT entry's
15084 relative branch calculated differently so it targets the last
15085 bundle instead of the instruction before it (labelled .Lplt_tail
15086 above). But it's simpler to keep the size and layout of PLT0
15087 consistent with the dynamic case, at the cost of some dead code at
15088 the start of .iplt and the one dead store to the stack at the start
15089 of .Lplt_tail. */
15090static void
15091arm_nacl_put_plt0 (struct elf32_arm_link_hash_table *htab, bfd *output_bfd,
15092 asection *plt, bfd_vma got_displacement)
15093{
15094 unsigned int i;
15095
15096 put_arm_insn (htab, output_bfd,
15097 elf32_arm_nacl_plt0_entry[0]
15098 | arm_movw_immediate (got_displacement),
15099 plt->contents + 0);
15100 put_arm_insn (htab, output_bfd,
15101 elf32_arm_nacl_plt0_entry[1]
15102 | arm_movt_immediate (got_displacement),
15103 plt->contents + 4);
15104
15105 for (i = 2; i < ARRAY_SIZE (elf32_arm_nacl_plt0_entry); ++i)
15106 put_arm_insn (htab, output_bfd,
15107 elf32_arm_nacl_plt0_entry[i],
15108 plt->contents + (i * 4));
15109}
15110
252b5132
RH		 15111/* Finish up the dynamic sections. */
15112
b34976b6 15113static bfd_boolean
57e8b36a 15114elf32_arm_finish_dynamic_sections (bfd * output_bfd, struct bfd_link_info * info)
252b5132
RH		 15115{
15116 bfd * dynobj;
15117 asection * sgot;
15118 asection * sdyn;
4dfe6ac6
NC		 15119 struct elf32_arm_link_hash_table *htab;
15120
15121 htab = elf32_arm_hash_table (info);
15122 if (htab == NULL)
15123 return FALSE;
252b5132
RH		 15124
15125 dynobj = elf_hash_table (info)->dynobj;
15126
362d30a1 15127 sgot = htab->root.sgotplt;
894891db
NC		 15128 /* A broken linker script might have discarded the dynamic sections.
15129 Catch this here so that we do not seg-fault later on. */
15130 if (sgot != NULL && bfd_is_abs_section (sgot->output_section))
15131 return FALSE;
3d4d4302 15132 sdyn = bfd_get_linker_section (dynobj, ".dynamic");
252b5132
RH		 15133
15134 if (elf_hash_table (info)->dynamic_sections_created)
15135 {
15136 asection *splt;
15137 Elf32_External_Dyn *dyncon, *dynconend;
15138
362d30a1 15139 splt = htab->root.splt;
24a1ba0f 15140 BFD_ASSERT (splt != NULL && sdyn != NULL);
cbc704f3 15141 BFD_ASSERT (htab->symbian_p || sgot != NULL);
252b5132
RH		 15142
15143 dyncon = (Elf32_External_Dyn *) sdyn->contents;
eea6121a 15144 dynconend = (Elf32_External_Dyn *) (sdyn->contents + sdyn->size);
9b485d32 15145
252b5132
RH		 15146 for (; dyncon < dynconend; dyncon++)
15147 {
15148 Elf_Internal_Dyn dyn;
15149 const char * name;
15150 asection * s;
15151
15152 bfd_elf32_swap_dyn_in (dynobj, dyncon, &dyn);
15153
15154 switch (dyn.d_tag)
15155 {
229fcec5
MM		 15156 unsigned int type;
15157
252b5132 15158 default:
7a2b07ff
NS		 15159 if (htab->vxworks_p
15160 && elf_vxworks_finish_dynamic_entry (output_bfd, &dyn))
15161 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
252b5132
RH		 15162 break;
15163
229fcec5
MM		 15164 case DT_HASH:
15165 name = ".hash";
15166 goto get_vma_if_bpabi;
15167 case DT_STRTAB:
15168 name = ".dynstr";
15169 goto get_vma_if_bpabi;
15170 case DT_SYMTAB:
15171 name = ".dynsym";
15172 goto get_vma_if_bpabi;
c0042f5d
MM		 15173 case DT_VERSYM:
15174 name = ".gnu.version";
15175 goto get_vma_if_bpabi;
15176 case DT_VERDEF:
15177 name = ".gnu.version_d";
15178 goto get_vma_if_bpabi;
15179 case DT_VERNEED:
15180 name = ".gnu.version_r";
15181 goto get_vma_if_bpabi;
15182
252b5132
RH		 15183 case DT_PLTGOT:
15184 name = ".got";
15185 goto get_vma;
15186 case DT_JMPREL:
00a97672 15187 name = RELOC_SECTION (htab, ".plt");
252b5132
RH		 15188 get_vma:
15189 s = bfd_get_section_by_name (output_bfd, name);
05456594
NC		 15190 if (s == NULL)
15191 {
15192 /* PR ld/14397: Issue an error message if a required section is missing. */
15193 (*_bfd_error_handler)
15194 (_("error: required section '%s' not found in the linker script"), name);
15195 bfd_set_error (bfd_error_invalid_operation);
15196 return FALSE;
15197 }
229fcec5
MM		 15198 if (!htab->symbian_p)
15199 dyn.d_un.d_ptr = s->vma;
15200 else
15201 /* In the BPABI, tags in the PT_DYNAMIC section point
15202 at the file offset, not the memory address, for the
15203 convenience of the post linker. */
15204 dyn.d_un.d_ptr = s->filepos;
252b5132
RH		 15205 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
15206 break;
15207
229fcec5
MM		 15208 get_vma_if_bpabi:
15209 if (htab->symbian_p)
15210 goto get_vma;
15211 break;
15212
252b5132 15213 case DT_PLTRELSZ:
362d30a1 15214 s = htab->root.srelplt;
252b5132 15215 BFD_ASSERT (s != NULL);
eea6121a 15216 dyn.d_un.d_val = s->size;
252b5132
RH		 15217 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
15218 break;
906e58ca 15219
252b5132 15220 case DT_RELSZ:
00a97672 15221 case DT_RELASZ:
229fcec5
MM		 15222 if (!htab->symbian_p)
15223 {
15224 /* My reading of the SVR4 ABI indicates that the
15225 procedure linkage table relocs (DT_JMPREL) should be
15226 included in the overall relocs (DT_REL). This is
15227 what Solaris does. However, UnixWare can not handle
15228 that case. Therefore, we override the DT_RELSZ entry
15229 here to make it not include the JMPREL relocs. Since
00a97672 15230 the linker script arranges for .rel(a).plt to follow all
229fcec5
MM		 15231 other relocation sections, we don't have to worry
15232 about changing the DT_REL entry. */
362d30a1 15233 s = htab->root.srelplt;
229fcec5
MM		 15234 if (s != NULL)
15235 dyn.d_un.d_val -= s->size;
15236 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
15237 break;
15238 }
8029a119 15239 /* Fall through. */
229fcec5
MM		 15240
15241 case DT_REL:
15242 case DT_RELA:
229fcec5
MM		 15243 /* In the BPABI, the DT_REL tag must point at the file
15244 offset, not the VMA, of the first relocation
15245 section. So, we use code similar to that in
15246 elflink.c, but do not check for SHF_ALLOC on the
15247 relcoation section, since relocations sections are
15248 never allocated under the BPABI. The comments above
15249 about Unixware notwithstanding, we include all of the
15250 relocations here. */
15251 if (htab->symbian_p)
15252 {
15253 unsigned int i;
15254 type = ((dyn.d_tag == DT_REL || dyn.d_tag == DT_RELSZ)
15255 ? SHT_REL : SHT_RELA);
15256 dyn.d_un.d_val = 0;
15257 for (i = 1; i < elf_numsections (output_bfd); i++)
15258 {
906e58ca 15259 Elf_Internal_Shdr *hdr
229fcec5
MM		 15260 = elf_elfsections (output_bfd)[i];
15261 if (hdr->sh_type == type)
15262 {
906e58ca 15263 if (dyn.d_tag == DT_RELSZ
229fcec5
MM		 15264 || dyn.d_tag == DT_RELASZ)
15265 dyn.d_un.d_val += hdr->sh_size;
de52dba4
AM		 15266 else if ((ufile_ptr) hdr->sh_offset
15267 <= dyn.d_un.d_val - 1)
229fcec5
MM		 15268 dyn.d_un.d_val = hdr->sh_offset;
15269 }
15270 }
15271 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
15272 }
252b5132 15273 break;
88f7bcd5 15274
0855e32b 15275 case DT_TLSDESC_PLT:
99059e56 15276 s = htab->root.splt;
0855e32b
NS		 15277 dyn.d_un.d_ptr = (s->output_section->vma + s->output_offset
15278 + htab->dt_tlsdesc_plt);
15279 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
15280 break;
15281
15282 case DT_TLSDESC_GOT:
99059e56 15283 s = htab->root.sgot;
0855e32b 15284 dyn.d_un.d_ptr = (s->output_section->vma + s->output_offset
99059e56 15285 + htab->dt_tlsdesc_got);
0855e32b
NS		 15286 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
15287 break;
15288
88f7bcd5
NC		 15289 /* Set the bottom bit of DT_INIT/FINI if the
15290 corresponding function is Thumb. */
15291 case DT_INIT:
15292 name = info->init_function;
15293 goto get_sym;
15294 case DT_FINI:
15295 name = info->fini_function;
15296 get_sym:
15297 /* If it wasn't set by elf_bfd_final_link
4cc11e76 15298 then there is nothing to adjust. */
88f7bcd5
NC		 15299 if (dyn.d_un.d_val != 0)
15300 {
15301 struct elf_link_hash_entry * eh;
15302
15303 eh = elf_link_hash_lookup (elf_hash_table (info), name,
b34976b6 15304 FALSE, FALSE, TRUE);
35fc36a8 15305 if (eh != NULL && eh->target_internal == ST_BRANCH_TO_THUMB)
88f7bcd5
NC		 15306 {
15307 dyn.d_un.d_val |= 1;
b34976b6 15308 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
88f7bcd5
NC		 15309 }
15310 }
15311 break;
252b5132
RH		 15312 }
15313 }
15314
24a1ba0f 15315 /* Fill in the first entry in the procedure linkage table. */
4dfe6ac6 15316 if (splt->size > 0 && htab->plt_header_size)
f7a74f8c 15317 {
00a97672
RS		 15318 const bfd_vma *plt0_entry;
15319 bfd_vma got_address, plt_address, got_displacement;
15320
15321 /* Calculate the addresses of the GOT and PLT. */
15322 got_address = sgot->output_section->vma + sgot->output_offset;
15323 plt_address = splt->output_section->vma + splt->output_offset;
15324
15325 if (htab->vxworks_p)
15326 {
15327 /* The VxWorks GOT is relocated by the dynamic linker.
15328 Therefore, we must emit relocations rather than simply
15329 computing the values now. */
15330 Elf_Internal_Rela rel;
15331
15332 plt0_entry = elf32_arm_vxworks_exec_plt0_entry;
52ab56c2
PB		 15333 put_arm_insn (htab, output_bfd, plt0_entry[0],
15334 splt->contents + 0);
15335 put_arm_insn (htab, output_bfd, plt0_entry[1],
15336 splt->contents + 4);
15337 put_arm_insn (htab, output_bfd, plt0_entry[2],
15338 splt->contents + 8);
00a97672
RS		 15339 bfd_put_32 (output_bfd, got_address, splt->contents + 12);
15340
8029a119 15341 /* Generate a relocation for _GLOBAL_OFFSET_TABLE_. */
00a97672
RS		 15342 rel.r_offset = plt_address + 12;
15343 rel.r_info = ELF32_R_INFO (htab->root.hgot->indx, R_ARM_ABS32);
15344 rel.r_addend = 0;
15345 SWAP_RELOC_OUT (htab) (output_bfd, &rel,
15346 htab->srelplt2->contents);
15347 }
b38cadfb 15348 else if (htab->nacl_p)
99059e56
RM		 15349 arm_nacl_put_plt0 (htab, output_bfd, splt,
15350 got_address + 8 - (plt_address + 16));
eed94f8f
NC		 15351 else if (using_thumb_only (htab))
15352 {
15353 got_displacement = got_address - (plt_address + 12);
15354
15355 plt0_entry = elf32_thumb2_plt0_entry;
15356 put_arm_insn (htab, output_bfd, plt0_entry[0],
15357 splt->contents + 0);
15358 put_arm_insn (htab, output_bfd, plt0_entry[1],
15359 splt->contents + 4);
15360 put_arm_insn (htab, output_bfd, plt0_entry[2],
15361 splt->contents + 8);
15362
15363 bfd_put_32 (output_bfd, got_displacement, splt->contents + 12);
15364 }
00a97672
RS		 15365 else
15366 {
15367 got_displacement = got_address - (plt_address + 16);
15368
15369 plt0_entry = elf32_arm_plt0_entry;
52ab56c2
PB		 15370 put_arm_insn (htab, output_bfd, plt0_entry[0],
15371 splt->contents + 0);
15372 put_arm_insn (htab, output_bfd, plt0_entry[1],
15373 splt->contents + 4);
15374 put_arm_insn (htab, output_bfd, plt0_entry[2],
15375 splt->contents + 8);
15376 put_arm_insn (htab, output_bfd, plt0_entry[3],
15377 splt->contents + 12);
5e681ec4 15378
5e681ec4 15379#ifdef FOUR_WORD_PLT
00a97672
RS		 15380 /* The displacement value goes in the otherwise-unused
15381 last word of the second entry. */
15382 bfd_put_32 (output_bfd, got_displacement, splt->contents + 28);
5e681ec4 15383#else
00a97672 15384 bfd_put_32 (output_bfd, got_displacement, splt->contents + 16);
5e681ec4 15385#endif
00a97672 15386 }
f7a74f8c 15387 }
252b5132
RH		 15388
15389 /* UnixWare sets the entsize of .plt to 4, although that doesn't
15390 really seem like the right value. */
74541ad4
AM		 15391 if (splt->output_section->owner == output_bfd)
15392 elf_section_data (splt->output_section)->this_hdr.sh_entsize = 4;
00a97672 15393
0855e32b
NS		 15394 if (htab->dt_tlsdesc_plt)
15395 {
15396 bfd_vma got_address
15397 = sgot->output_section->vma + sgot->output_offset;
15398 bfd_vma gotplt_address = (htab->root.sgot->output_section->vma
15399 + htab->root.sgot->output_offset);
15400 bfd_vma plt_address
15401 = splt->output_section->vma + splt->output_offset;
15402
b38cadfb 15403 arm_put_trampoline (htab, output_bfd,
0855e32b
NS		 15404 splt->contents + htab->dt_tlsdesc_plt,
15405 dl_tlsdesc_lazy_trampoline, 6);
15406
15407 bfd_put_32 (output_bfd,
15408 gotplt_address + htab->dt_tlsdesc_got
15409 - (plt_address + htab->dt_tlsdesc_plt)
15410 - dl_tlsdesc_lazy_trampoline[6],
15411 splt->contents + htab->dt_tlsdesc_plt + 24);
15412 bfd_put_32 (output_bfd,
15413 got_address - (plt_address + htab->dt_tlsdesc_plt)
15414 - dl_tlsdesc_lazy_trampoline[7],
15415 splt->contents + htab->dt_tlsdesc_plt + 24 + 4);
15416 }
15417
15418 if (htab->tls_trampoline)
15419 {
b38cadfb 15420 arm_put_trampoline (htab, output_bfd,
0855e32b
NS		 15421 splt->contents + htab->tls_trampoline,
15422 tls_trampoline, 3);
15423#ifdef FOUR_WORD_PLT
15424 bfd_put_32 (output_bfd, 0x00000000,
15425 splt->contents + htab->tls_trampoline + 12);
b38cadfb 15426#endif
0855e32b
NS		 15427 }
15428
0e1862bb
L		 15429 if (htab->vxworks_p
15430 && !bfd_link_pic (info)
15431 && htab->root.splt->size > 0)
00a97672
RS		 15432 {
15433 /* Correct the .rel(a).plt.unloaded relocations. They will have
15434 incorrect symbol indexes. */
15435 int num_plts;
eed62c48 15436 unsigned char *p;
00a97672 15437
362d30a1 15438 num_plts = ((htab->root.splt->size - htab->plt_header_size)
00a97672
RS		 15439 / htab->plt_entry_size);
15440 p = htab->srelplt2->contents + RELOC_SIZE (htab);
15441
15442 for (; num_plts; num_plts--)
15443 {
15444 Elf_Internal_Rela rel;
15445
15446 SWAP_RELOC_IN (htab) (output_bfd, p, &rel);
15447 rel.r_info = ELF32_R_INFO (htab->root.hgot->indx, R_ARM_ABS32);
15448 SWAP_RELOC_OUT (htab) (output_bfd, &rel, p);
15449 p += RELOC_SIZE (htab);
15450
15451 SWAP_RELOC_IN (htab) (output_bfd, p, &rel);
15452 rel.r_info = ELF32_R_INFO (htab->root.hplt->indx, R_ARM_ABS32);
15453 SWAP_RELOC_OUT (htab) (output_bfd, &rel, p);
15454 p += RELOC_SIZE (htab);
15455 }
15456 }
252b5132
RH		 15457 }
15458
99059e56
RM		 15459 if (htab->nacl_p && htab->root.iplt != NULL && htab->root.iplt->size > 0)
15460 /* NaCl uses a special first entry in .iplt too. */
15461 arm_nacl_put_plt0 (htab, output_bfd, htab->root.iplt, 0);
15462
252b5132 15463 /* Fill in the first three entries in the global offset table. */
229fcec5 15464 if (sgot)
252b5132 15465 {
229fcec5
MM		 15466 if (sgot->size > 0)
15467 {
15468 if (sdyn == NULL)
15469 bfd_put_32 (output_bfd, (bfd_vma) 0, sgot->contents);
15470 else
15471 bfd_put_32 (output_bfd,
15472 sdyn->output_section->vma + sdyn->output_offset,
15473 sgot->contents);
15474 bfd_put_32 (output_bfd, (bfd_vma) 0, sgot->contents + 4);
15475 bfd_put_32 (output_bfd, (bfd_vma) 0, sgot->contents + 8);
15476 }
252b5132 15477
229fcec5
MM		 15478 elf_section_data (sgot->output_section)->this_hdr.sh_entsize = 4;
15479 }
252b5132 15480
b34976b6 15481 return TRUE;
252b5132
RH		 15482}
15483
ba96a88f 15484static void
57e8b36a 15485elf32_arm_post_process_headers (bfd * abfd, struct bfd_link_info * link_info ATTRIBUTE_UNUSED)
ba96a88f 15486{
9b485d32 15487 Elf_Internal_Ehdr * i_ehdrp; /* ELF file header, internal form. */
e489d0ae 15488 struct elf32_arm_link_hash_table *globals;
ac4c9b04 15489 struct elf_segment_map *m;
ba96a88f
NC		 15490
15491 i_ehdrp = elf_elfheader (abfd);
15492
94a3258f
PB		 15493 if (EF_ARM_EABI_VERSION (i_ehdrp->e_flags) == EF_ARM_EABI_UNKNOWN)
15494 i_ehdrp->e_ident[EI_OSABI] = ELFOSABI_ARM;
15495 else
7394f108 15496 _bfd_elf_post_process_headers (abfd, link_info);
ba96a88f 15497 i_ehdrp->e_ident[EI_ABIVERSION] = ARM_ELF_ABI_VERSION;
e489d0ae 15498
93204d3a
PB		 15499 if (link_info)
15500 {
15501 globals = elf32_arm_hash_table (link_info);
4dfe6ac6 15502 if (globals != NULL && globals->byteswap_code)
93204d3a
PB		 15503 i_ehdrp->e_flags |= EF_ARM_BE8;
15504 }
3bfcb652
NC		 15505
15506 if (EF_ARM_EABI_VERSION (i_ehdrp->e_flags) == EF_ARM_EABI_VER5
15507 && ((i_ehdrp->e_type == ET_DYN) || (i_ehdrp->e_type == ET_EXEC)))
15508 {
15509 int abi = bfd_elf_get_obj_attr_int (abfd, OBJ_ATTR_PROC, Tag_ABI_VFP_args);
5c294fee 15510 if (abi == AEABI_VFP_args_vfp)
3bfcb652
NC		 15511 i_ehdrp->e_flags |= EF_ARM_ABI_FLOAT_HARD;
15512 else
15513 i_ehdrp->e_flags |= EF_ARM_ABI_FLOAT_SOFT;
15514 }
ac4c9b04
MG		 15515
15516 /* Scan segment to set p_flags attribute if it contains only sections with
15517 SHF_ARM_NOREAD flag. */
15518 for (m = elf_seg_map (abfd); m != NULL; m = m->next)
15519 {
15520 unsigned int j;
15521
15522 if (m->count == 0)
15523 continue;
15524 for (j = 0; j < m->count; j++)
15525 {
15526 if (!(elf_section_flags (m->sections[j]) & SHF_ARM_NOREAD))
15527 break;
15528 }
15529 if (j == m->count)
15530 {
15531 m->p_flags = PF_X;
15532 m->p_flags_valid = 1;
15533 }
15534 }
ba96a88f
NC		 15535}
15536
99e4ae17 15537static enum elf_reloc_type_class
7e612e98
AM		 15538elf32_arm_reloc_type_class (const struct bfd_link_info *info ATTRIBUTE_UNUSED,
15539 const asection *rel_sec ATTRIBUTE_UNUSED,
15540 const Elf_Internal_Rela *rela)
99e4ae17 15541{
f51e552e 15542 switch ((int) ELF32_R_TYPE (rela->r_info))
99e4ae17
AJ		 15543 {
15544 case R_ARM_RELATIVE:
15545 return reloc_class_relative;
15546 case R_ARM_JUMP_SLOT:
15547 return reloc_class_plt;
15548 case R_ARM_COPY:
15549 return reloc_class_copy;
109575d7
JW		 15550 case R_ARM_IRELATIVE:
15551 return reloc_class_ifunc;
99e4ae17
AJ		 15552 default:
15553 return reloc_class_normal;
15554 }
15555}
15556
e489d0ae 15557static void
57e8b36a 15558elf32_arm_final_write_processing (bfd *abfd, bfd_boolean linker ATTRIBUTE_UNUSED)
e16bb312 15559{
5a6c6817 15560 bfd_arm_update_notes (abfd, ARM_NOTE_SECTION);
e16bb312
NC		 15561}
15562
40a18ebd
NC		 15563/* Return TRUE if this is an unwinding table entry. */
15564
15565static bfd_boolean
15566is_arm_elf_unwind_section_name (bfd * abfd ATTRIBUTE_UNUSED, const char * name)
15567{
0112cd26
NC		 15568 return (CONST_STRNEQ (name, ELF_STRING_ARM_unwind)
15569 || CONST_STRNEQ (name, ELF_STRING_ARM_unwind_once));
40a18ebd
NC		 15570}
15571
15572
15573/* Set the type and flags for an ARM section. We do this by
15574 the section name, which is a hack, but ought to work. */
15575
15576static bfd_boolean
15577elf32_arm_fake_sections (bfd * abfd, Elf_Internal_Shdr * hdr, asection * sec)
15578{
15579 const char * name;
15580
15581 name = bfd_get_section_name (abfd, sec);
15582
15583 if (is_arm_elf_unwind_section_name (abfd, name))
15584 {
15585 hdr->sh_type = SHT_ARM_EXIDX;
15586 hdr->sh_flags |= SHF_LINK_ORDER;
15587 }
ac4c9b04
MG		 15588
15589 if (sec->flags & SEC_ELF_NOREAD)
15590 hdr->sh_flags |= SHF_ARM_NOREAD;
15591
40a18ebd
NC		 15592 return TRUE;
15593}
15594
6dc132d9
L		 15595/* Handle an ARM specific section when reading an object file. This is
15596 called when bfd_section_from_shdr finds a section with an unknown
15597 type. */
40a18ebd
NC		 15598
15599static bfd_boolean
15600elf32_arm_section_from_shdr (bfd *abfd,
15601 Elf_Internal_Shdr * hdr,
6dc132d9
L		 15602 const char *name,
15603 int shindex)
40a18ebd
NC		 15604{
15605 /* There ought to be a place to keep ELF backend specific flags, but
15606 at the moment there isn't one. We just keep track of the
15607 sections by their name, instead. Fortunately, the ABI gives
15608 names for all the ARM specific sections, so we will probably get
15609 away with this. */
15610 switch (hdr->sh_type)
15611 {
15612 case SHT_ARM_EXIDX:
0951f019
RE		 15613 case SHT_ARM_PREEMPTMAP:
15614 case SHT_ARM_ATTRIBUTES:
40a18ebd
NC		 15615 break;
15616
15617 default:
15618 return FALSE;
15619 }
15620
6dc132d9 15621 if (! _bfd_elf_make_section_from_shdr (abfd, hdr, name, shindex))
40a18ebd
NC		 15622 return FALSE;
15623
15624 return TRUE;
15625}
e489d0ae 15626
44444f50
NC		 15627static _arm_elf_section_data *
15628get_arm_elf_section_data (asection * sec)
15629{
47b2e99c
JZ		 15630 if (sec && sec->owner && is_arm_elf (sec->owner))
15631 return elf32_arm_section_data (sec);
44444f50
NC		 15632 else
15633 return NULL;
8e3de13a
NC		 15634}
15635
4e617b1e
PB		 15636typedef struct
15637{
57402f1e 15638 void *flaginfo;
4e617b1e 15639 struct bfd_link_info *info;
91a5743d
PB		 15640 asection *sec;
15641 int sec_shndx;
6e0b88f1
AM		 15642 int (*func) (void *, const char *, Elf_Internal_Sym *,
15643 asection *, struct elf_link_hash_entry *);
4e617b1e
PB		 15644} output_arch_syminfo;
15645
15646enum map_symbol_type
15647{
15648 ARM_MAP_ARM,
15649 ARM_MAP_THUMB,
15650 ARM_MAP_DATA
15651};
15652
15653
7413f23f 15654/* Output a single mapping symbol. */
4e617b1e
PB		 15655
15656static bfd_boolean
7413f23f
DJ		 15657elf32_arm_output_map_sym (output_arch_syminfo *osi,
15658 enum map_symbol_type type,
15659 bfd_vma offset)
4e617b1e
PB		 15660{
15661 static const char *names[3] = {"$a", "$t", "$d"};
4e617b1e
PB		 15662 Elf_Internal_Sym sym;
15663
91a5743d
PB		 15664 sym.st_value = osi->sec->output_section->vma
15665 + osi->sec->output_offset
15666 + offset;
4e617b1e
PB		 15667 sym.st_size = 0;
15668 sym.st_other = 0;
15669 sym.st_info = ELF_ST_INFO (STB_LOCAL, STT_NOTYPE);
91a5743d 15670 sym.st_shndx = osi->sec_shndx;
35fc36a8 15671 sym.st_target_internal = 0;
fe33d2fa 15672 elf32_arm_section_map_add (osi->sec, names[type][1], offset);
57402f1e 15673 return osi->func (osi->flaginfo, names[type], &sym, osi->sec, NULL) == 1;
4e617b1e
PB		 15674}
15675
34e77a92
RS		 15676/* Output mapping symbols for the PLT entry described by ROOT_PLT and ARM_PLT.
15677 IS_IPLT_ENTRY_P says whether the PLT is in .iplt rather than .plt. */
4e617b1e
PB		 15678
15679static bfd_boolean
34e77a92
RS		 15680elf32_arm_output_plt_map_1 (output_arch_syminfo *osi,
15681 bfd_boolean is_iplt_entry_p,
15682 union gotplt_union *root_plt,
15683 struct arm_plt_info *arm_plt)
4e617b1e 15684{
4e617b1e 15685 struct elf32_arm_link_hash_table *htab;
34e77a92 15686 bfd_vma addr, plt_header_size;
4e617b1e 15687
34e77a92 15688 if (root_plt->offset == (bfd_vma) -1)
4e617b1e
PB		 15689 return TRUE;
15690
4dfe6ac6
NC		 15691 htab = elf32_arm_hash_table (osi->info);
15692 if (htab == NULL)
15693 return FALSE;
15694
34e77a92
RS		 15695 if (is_iplt_entry_p)
15696 {
15697 osi->sec = htab->root.iplt;
15698 plt_header_size = 0;
15699 }
15700 else
15701 {
15702 osi->sec = htab->root.splt;
15703 plt_header_size = htab->plt_header_size;
15704 }
15705 osi->sec_shndx = (_bfd_elf_section_from_bfd_section
15706 (osi->info->output_bfd, osi->sec->output_section));
15707
15708 addr = root_plt->offset & -2;
4e617b1e
PB		 15709 if (htab->symbian_p)
15710 {
7413f23f 15711 if (!elf32_arm_output_map_sym (osi, ARM_MAP_ARM, addr))
4e617b1e 15712 return FALSE;
7413f23f 15713 if (!elf32_arm_output_map_sym (osi, ARM_MAP_DATA, addr + 4))
4e617b1e
PB		 15714 return FALSE;
15715 }
15716 else if (htab->vxworks_p)
15717 {
7413f23f 15718 if (!elf32_arm_output_map_sym (osi, ARM_MAP_ARM, addr))
4e617b1e 15719 return FALSE;
7413f23f 15720 if (!elf32_arm_output_map_sym (osi, ARM_MAP_DATA, addr + 8))
4e617b1e 15721 return FALSE;
7413f23f 15722 if (!elf32_arm_output_map_sym (osi, ARM_MAP_ARM, addr + 12))
4e617b1e 15723 return FALSE;
7413f23f 15724 if (!elf32_arm_output_map_sym (osi, ARM_MAP_DATA, addr + 20))
4e617b1e
PB		 15725 return FALSE;
15726 }
b38cadfb
NC		 15727 else if (htab->nacl_p)
15728 {
15729 if (!elf32_arm_output_map_sym (osi, ARM_MAP_ARM, addr))
15730 return FALSE;
15731 }
eed94f8f
NC		 15732 else if (using_thumb_only (htab))
15733 {
15734 if (!elf32_arm_output_map_sym (osi, ARM_MAP_THUMB, addr))
15735 return FALSE;
6a631e86 15736 }
4e617b1e
PB		 15737 else
15738 {
34e77a92 15739 bfd_boolean thumb_stub_p;
bd97cb95 15740
34e77a92
RS		 15741 thumb_stub_p = elf32_arm_plt_needs_thumb_stub_p (osi->info, arm_plt);
15742 if (thumb_stub_p)
4e617b1e 15743 {
7413f23f 15744 if (!elf32_arm_output_map_sym (osi, ARM_MAP_THUMB, addr - 4))
4e617b1e
PB		 15745 return FALSE;
15746 }
15747#ifdef FOUR_WORD_PLT
7413f23f 15748 if (!elf32_arm_output_map_sym (osi, ARM_MAP_ARM, addr))
4e617b1e 15749 return FALSE;
7413f23f 15750 if (!elf32_arm_output_map_sym (osi, ARM_MAP_DATA, addr + 12))
4e617b1e
PB		 15751 return FALSE;
15752#else
906e58ca 15753 /* A three-word PLT with no Thumb thunk contains only Arm code,
4e617b1e
PB		 15754 so only need to output a mapping symbol for the first PLT entry and
15755 entries with thumb thunks. */
34e77a92 15756 if (thumb_stub_p || addr == plt_header_size)
4e617b1e 15757 {
7413f23f 15758 if (!elf32_arm_output_map_sym (osi, ARM_MAP_ARM, addr))
4e617b1e
PB		 15759 return FALSE;
15760 }
15761#endif
15762 }
15763
15764 return TRUE;
15765}
15766
34e77a92
RS		 15767/* Output mapping symbols for PLT entries associated with H. */
15768
15769static bfd_boolean
15770elf32_arm_output_plt_map (struct elf_link_hash_entry *h, void *inf)
15771{
15772 output_arch_syminfo *osi = (output_arch_syminfo *) inf;
15773 struct elf32_arm_link_hash_entry *eh;
15774
15775 if (h->root.type == bfd_link_hash_indirect)
15776 return TRUE;
15777
15778 if (h->root.type == bfd_link_hash_warning)
15779 /* When warning symbols are created, they **replace** the "real"
15780 entry in the hash table, thus we never get to see the real
15781 symbol in a hash traversal. So look at it now. */
15782 h = (struct elf_link_hash_entry *) h->root.u.i.link;
15783
15784 eh = (struct elf32_arm_link_hash_entry *) h;
15785 return elf32_arm_output_plt_map_1 (osi, SYMBOL_CALLS_LOCAL (osi->info, h),
15786 &h->plt, &eh->plt);
15787}
15788
7413f23f
DJ		 15789/* Output a single local symbol for a generated stub. */
15790
15791static bfd_boolean
15792elf32_arm_output_stub_sym (output_arch_syminfo *osi, const char *name,
15793 bfd_vma offset, bfd_vma size)
15794{
7413f23f
DJ		 15795 Elf_Internal_Sym sym;
15796
7413f23f
DJ		 15797 sym.st_value = osi->sec->output_section->vma
15798 + osi->sec->output_offset
15799 + offset;
15800 sym.st_size = size;
15801 sym.st_other = 0;
15802 sym.st_info = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
15803 sym.st_shndx = osi->sec_shndx;
35fc36a8 15804 sym.st_target_internal = 0;
57402f1e 15805 return osi->func (osi->flaginfo, name, &sym, osi->sec, NULL) == 1;
7413f23f 15806}
4e617b1e 15807
da5938a2 15808static bfd_boolean
8029a119
NC		 15809arm_map_one_stub (struct bfd_hash_entry * gen_entry,
15810 void * in_arg)
da5938a2
NC		 15811{
15812 struct elf32_arm_stub_hash_entry *stub_entry;
da5938a2
NC		 15813 asection *stub_sec;
15814 bfd_vma addr;
7413f23f 15815 char *stub_name;
9a008db3 15816 output_arch_syminfo *osi;
d3ce72d0 15817 const insn_sequence *template_sequence;
461a49ca
DJ		 15818 enum stub_insn_type prev_type;
15819 int size;
15820 int i;
15821 enum map_symbol_type sym_type;
da5938a2
NC		 15822
15823 /* Massage our args to the form they really have. */
15824 stub_entry = (struct elf32_arm_stub_hash_entry *) gen_entry;
9a008db3 15825 osi = (output_arch_syminfo *) in_arg;
da5938a2 15826
da5938a2
NC		 15827 stub_sec = stub_entry->stub_sec;
15828
15829 /* Ensure this stub is attached to the current section being
7413f23f 15830 processed. */
da5938a2
NC		 15831 if (stub_sec != osi->sec)
15832 return TRUE;
15833
7413f23f
DJ		 15834 addr = (bfd_vma) stub_entry->stub_offset;
15835 stub_name = stub_entry->output_name;
da5938a2 15836
d3ce72d0
NC		 15837 template_sequence = stub_entry->stub_template;
15838 switch (template_sequence[0].type)
7413f23f 15839 {
461a49ca
DJ		 15840 case ARM_TYPE:
15841 if (!elf32_arm_output_stub_sym (osi, stub_name, addr, stub_entry->stub_size))
da5938a2
NC		 15842 return FALSE;
15843 break;
461a49ca 15844 case THUMB16_TYPE:
48229727 15845 case THUMB32_TYPE:
461a49ca
DJ		 15846 if (!elf32_arm_output_stub_sym (osi, stub_name, addr | 1,
15847 stub_entry->stub_size))
da5938a2
NC		 15848 return FALSE;
15849 break;
15850 default:
15851 BFD_FAIL ();
48229727 15852 return 0;
7413f23f 15853 }
da5938a2 15854
461a49ca
DJ		 15855 prev_type = DATA_TYPE;
15856 size = 0;
15857 for (i = 0; i < stub_entry->stub_template_size; i++)
15858 {
d3ce72d0 15859 switch (template_sequence[i].type)
461a49ca
DJ		 15860 {
15861 case ARM_TYPE:
15862 sym_type = ARM_MAP_ARM;
15863 break;
15864
15865 case THUMB16_TYPE:
48229727 15866 case THUMB32_TYPE:
461a49ca
DJ		 15867 sym_type = ARM_MAP_THUMB;
15868 break;
15869
15870 case DATA_TYPE:
15871 sym_type = ARM_MAP_DATA;
15872 break;
15873
15874 default:
15875 BFD_FAIL ();
4e31c731 15876 return FALSE;
461a49ca
DJ		 15877 }
15878
d3ce72d0 15879 if (template_sequence[i].type != prev_type)
461a49ca 15880 {
d3ce72d0 15881 prev_type = template_sequence[i].type;
461a49ca
DJ		 15882 if (!elf32_arm_output_map_sym (osi, sym_type, addr + size))
15883 return FALSE;
15884 }
15885
d3ce72d0 15886 switch (template_sequence[i].type)
461a49ca
DJ		 15887 {
15888 case ARM_TYPE:
48229727 15889 case THUMB32_TYPE:
461a49ca
DJ		 15890 size += 4;
15891 break;
15892
15893 case THUMB16_TYPE:
15894 size += 2;
15895 break;
15896
15897 case DATA_TYPE:
15898 size += 4;
15899 break;
15900
15901 default:
15902 BFD_FAIL ();
4e31c731 15903 return FALSE;
461a49ca
DJ		 15904 }
15905 }
15906
da5938a2
NC		 15907 return TRUE;
15908}
15909
33811162
DG		 15910/* Output mapping symbols for linker generated sections,
15911 and for those data-only sections that do not have a
15912 $d. */
4e617b1e
PB		 15913
15914static bfd_boolean
15915elf32_arm_output_arch_local_syms (bfd *output_bfd,
906e58ca 15916 struct bfd_link_info *info,
57402f1e 15917 void *flaginfo,
6e0b88f1
AM		 15918 int (*func) (void *, const char *,
15919 Elf_Internal_Sym *,
15920 asection *,
15921 struct elf_link_hash_entry *))
4e617b1e
PB		 15922{
15923 output_arch_syminfo osi;
15924 struct elf32_arm_link_hash_table *htab;
91a5743d
PB		 15925 bfd_vma offset;
15926 bfd_size_type size;
33811162 15927 bfd *input_bfd;
4e617b1e
PB		 15928
15929 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 15930 if (htab == NULL)
15931 return FALSE;
15932
906e58ca 15933 check_use_blx (htab);
91a5743d 15934
57402f1e 15935 osi.flaginfo = flaginfo;
4e617b1e
PB		 15936 osi.info = info;
15937 osi.func = func;
906e58ca 15938
33811162
DG		 15939 /* Add a $d mapping symbol to data-only sections that
15940 don't have any mapping symbol. This may result in (harmless) redundant
15941 mapping symbols. */
15942 for (input_bfd = info->input_bfds;
15943 input_bfd != NULL;
c72f2fb2 15944 input_bfd = input_bfd->link.next)
33811162
DG		 15945 {
15946 if ((input_bfd->flags & (BFD_LINKER_CREATED | HAS_SYMS)) == HAS_SYMS)
15947 for (osi.sec = input_bfd->sections;
15948 osi.sec != NULL;
15949 osi.sec = osi.sec->next)
15950 {
15951 if (osi.sec->output_section != NULL
f7dd8c79
DJ		 15952 && ((osi.sec->output_section->flags & (SEC_ALLOC | SEC_CODE))
15953 != 0)
33811162
DG		 15954 && (osi.sec->flags & (SEC_HAS_CONTENTS | SEC_LINKER_CREATED))
15955 == SEC_HAS_CONTENTS
15956 && get_arm_elf_section_data (osi.sec) != NULL
501abfe0 15957 && get_arm_elf_section_data (osi.sec)->mapcount == 0
7d500b83
CL		 15958 && osi.sec->size > 0
15959 && (osi.sec->flags & SEC_EXCLUDE) == 0)
33811162
DG		 15960 {
15961 osi.sec_shndx = _bfd_elf_section_from_bfd_section
15962 (output_bfd, osi.sec->output_section);
15963 if (osi.sec_shndx != (int)SHN_BAD)
15964 elf32_arm_output_map_sym (&osi, ARM_MAP_DATA, 0);
15965 }
15966 }
15967 }
15968
91a5743d
PB		 15969 /* ARM->Thumb glue. */
15970 if (htab->arm_glue_size > 0)
15971 {
3d4d4302
AM		 15972 osi.sec = bfd_get_linker_section (htab->bfd_of_glue_owner,
15973 ARM2THUMB_GLUE_SECTION_NAME);
91a5743d
PB		 15974
15975 osi.sec_shndx = _bfd_elf_section_from_bfd_section
15976 (output_bfd, osi.sec->output_section);
0e1862bb 15977 if (bfd_link_pic (info) || htab->root.is_relocatable_executable
91a5743d
PB		 15978 || htab->pic_veneer)
15979 size = ARM2THUMB_PIC_GLUE_SIZE;
15980 else if (htab->use_blx)
15981 size = ARM2THUMB_V5_STATIC_GLUE_SIZE;
15982 else
15983 size = ARM2THUMB_STATIC_GLUE_SIZE;
4e617b1e 15984
91a5743d
PB		 15985 for (offset = 0; offset < htab->arm_glue_size; offset += size)
15986 {
7413f23f
DJ		 15987 elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, offset);
15988 elf32_arm_output_map_sym (&osi, ARM_MAP_DATA, offset + size - 4);
91a5743d
PB		 15989 }
15990 }
15991
15992 /* Thumb->ARM glue. */
15993 if (htab->thumb_glue_size > 0)
15994 {
3d4d4302
AM		 15995 osi.sec = bfd_get_linker_section (htab->bfd_of_glue_owner,
15996 THUMB2ARM_GLUE_SECTION_NAME);
91a5743d
PB		 15997
15998 osi.sec_shndx = _bfd_elf_section_from_bfd_section
15999 (output_bfd, osi.sec->output_section);
16000 size = THUMB2ARM_GLUE_SIZE;
16001
16002 for (offset = 0; offset < htab->thumb_glue_size; offset += size)
16003 {
7413f23f
DJ		 16004 elf32_arm_output_map_sym (&osi, ARM_MAP_THUMB, offset);
16005 elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, offset + 4);
91a5743d
PB		 16006 }
16007 }
16008
845b51d6
PB		 16009 /* ARMv4 BX veneers. */
16010 if (htab->bx_glue_size > 0)
16011 {
3d4d4302
AM		 16012 osi.sec = bfd_get_linker_section (htab->bfd_of_glue_owner,
16013 ARM_BX_GLUE_SECTION_NAME);
845b51d6
PB		 16014
16015 osi.sec_shndx = _bfd_elf_section_from_bfd_section
16016 (output_bfd, osi.sec->output_section);
16017
7413f23f 16018 elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, 0);
845b51d6
PB		 16019 }
16020
8029a119
NC		 16021 /* Long calls stubs. */
16022 if (htab->stub_bfd && htab->stub_bfd->sections)
16023 {
da5938a2 16024 asection* stub_sec;
8029a119 16025
da5938a2
NC		 16026 for (stub_sec = htab->stub_bfd->sections;
16027 stub_sec != NULL;
8029a119
NC		 16028 stub_sec = stub_sec->next)
16029 {
16030 /* Ignore non-stub sections. */
16031 if (!strstr (stub_sec->name, STUB_SUFFIX))
16032 continue;
da5938a2 16033
8029a119 16034 osi.sec = stub_sec;
da5938a2 16035
8029a119
NC		 16036 osi.sec_shndx = _bfd_elf_section_from_bfd_section
16037 (output_bfd, osi.sec->output_section);
da5938a2 16038
8029a119
NC		 16039 bfd_hash_traverse (&htab->stub_hash_table, arm_map_one_stub, &osi);
16040 }
16041 }
da5938a2 16042
91a5743d 16043 /* Finally, output mapping symbols for the PLT. */
34e77a92 16044 if (htab->root.splt && htab->root.splt->size > 0)
4e617b1e 16045 {
34e77a92
RS		 16046 osi.sec = htab->root.splt;
16047 osi.sec_shndx = (_bfd_elf_section_from_bfd_section
16048 (output_bfd, osi.sec->output_section));
16049
16050 /* Output mapping symbols for the plt header. SymbianOS does not have a
16051 plt header. */
16052 if (htab->vxworks_p)
16053 {
16054 /* VxWorks shared libraries have no PLT header. */
0e1862bb 16055 if (!bfd_link_pic (info))
34e77a92
RS		 16056 {
16057 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, 0))
16058 return FALSE;
16059 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_DATA, 12))
16060 return FALSE;
16061 }
16062 }
b38cadfb
NC		 16063 else if (htab->nacl_p)
16064 {
16065 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, 0))
16066 return FALSE;
16067 }
eed94f8f
NC		 16068 else if (using_thumb_only (htab))
16069 {
16070 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_THUMB, 0))
16071 return FALSE;
16072 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_DATA, 12))
16073 return FALSE;
16074 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_THUMB, 16))
16075 return FALSE;
16076 }
34e77a92 16077 else if (!htab->symbian_p)
4e617b1e 16078 {
7413f23f 16079 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, 0))
4e617b1e 16080 return FALSE;
34e77a92
RS		 16081#ifndef FOUR_WORD_PLT
16082 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_DATA, 16))
4e617b1e 16083 return FALSE;
34e77a92 16084#endif
4e617b1e
PB		 16085 }
16086 }
99059e56
RM		 16087 if (htab->nacl_p && htab->root.iplt && htab->root.iplt->size > 0)
16088 {
16089 /* NaCl uses a special first entry in .iplt too. */
16090 osi.sec = htab->root.iplt;
16091 osi.sec_shndx = (_bfd_elf_section_from_bfd_section
16092 (output_bfd, osi.sec->output_section));
16093 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, 0))
16094 return FALSE;
16095 }
34e77a92
RS		 16096 if ((htab->root.splt && htab->root.splt->size > 0)
16097 || (htab->root.iplt && htab->root.iplt->size > 0))
4e617b1e 16098 {
34e77a92
RS		 16099 elf_link_hash_traverse (&htab->root, elf32_arm_output_plt_map, &osi);
16100 for (input_bfd = info->input_bfds;
16101 input_bfd != NULL;
c72f2fb2 16102 input_bfd = input_bfd->link.next)
34e77a92
RS		 16103 {
16104 struct arm_local_iplt_info **local_iplt;
16105 unsigned int i, num_syms;
4e617b1e 16106
34e77a92
RS		 16107 local_iplt = elf32_arm_local_iplt (input_bfd);
16108 if (local_iplt != NULL)
16109 {
16110 num_syms = elf_symtab_hdr (input_bfd).sh_info;
16111 for (i = 0; i < num_syms; i++)
16112 if (local_iplt[i] != NULL
16113 && !elf32_arm_output_plt_map_1 (&osi, TRUE,
16114 &local_iplt[i]->root,
16115 &local_iplt[i]->arm))
16116 return FALSE;
16117 }
16118 }
16119 }
0855e32b
NS		 16120 if (htab->dt_tlsdesc_plt != 0)
16121 {
16122 /* Mapping symbols for the lazy tls trampoline. */
16123 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, htab->dt_tlsdesc_plt))
16124 return FALSE;
b38cadfb 16125
0855e32b
NS		 16126 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_DATA,
16127 htab->dt_tlsdesc_plt + 24))
16128 return FALSE;
16129 }
16130 if (htab->tls_trampoline != 0)
16131 {
16132 /* Mapping symbols for the tls trampoline. */
16133 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, htab->tls_trampoline))
16134 return FALSE;
16135#ifdef FOUR_WORD_PLT
16136 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_DATA,
16137 htab->tls_trampoline + 12))
16138 return FALSE;
b38cadfb 16139#endif
0855e32b 16140 }
b38cadfb 16141
4e617b1e
PB		 16142 return TRUE;
16143}
16144
e489d0ae
PB		 16145/* Allocate target specific section data. */
16146
16147static bfd_boolean
16148elf32_arm_new_section_hook (bfd *abfd, asection *sec)
16149{
f592407e
AM		 16150 if (!sec->used_by_bfd)
16151 {
16152 _arm_elf_section_data *sdata;
16153 bfd_size_type amt = sizeof (*sdata);
e489d0ae 16154
21d799b5 16155 sdata = (_arm_elf_section_data *) bfd_zalloc (abfd, amt);
f592407e
AM		 16156 if (sdata == NULL)
16157 return FALSE;
16158 sec->used_by_bfd = sdata;
16159 }
e489d0ae
PB		 16160
16161 return _bfd_elf_new_section_hook (abfd, sec);
16162}
16163
16164
16165/* Used to order a list of mapping symbols by address. */
16166
16167static int
16168elf32_arm_compare_mapping (const void * a, const void * b)
16169{
7f6a71ff
JM		 16170 const elf32_arm_section_map *amap = (const elf32_arm_section_map *) a;
16171 const elf32_arm_section_map *bmap = (const elf32_arm_section_map *) b;
16172
16173 if (amap->vma > bmap->vma)
16174 return 1;
16175 else if (amap->vma < bmap->vma)
16176 return -1;
16177 else if (amap->type > bmap->type)
16178 /* Ensure results do not depend on the host qsort for objects with
16179 multiple mapping symbols at the same address by sorting on type
16180 after vma. */
16181 return 1;
16182 else if (amap->type < bmap->type)
16183 return -1;
16184 else
16185 return 0;
e489d0ae
PB		 16186}
16187
2468f9c9
PB		 16188/* Add OFFSET to lower 31 bits of ADDR, leaving other bits unmodified. */
16189
16190static unsigned long
16191offset_prel31 (unsigned long addr, bfd_vma offset)
16192{
16193 return (addr & ~0x7ffffffful) | ((addr + offset) & 0x7ffffffful);
16194}
16195
16196/* Copy an .ARM.exidx table entry, adding OFFSET to (applied) PREL31
16197 relocations. */
16198
16199static void
16200copy_exidx_entry (bfd *output_bfd, bfd_byte *to, bfd_byte *from, bfd_vma offset)
16201{
16202 unsigned long first_word = bfd_get_32 (output_bfd, from);
16203 unsigned long second_word = bfd_get_32 (output_bfd, from + 4);
b38cadfb 16204
2468f9c9
PB		 16205 /* High bit of first word is supposed to be zero. */
16206 if ((first_word & 0x80000000ul) == 0)
16207 first_word = offset_prel31 (first_word, offset);
b38cadfb 16208
2468f9c9
PB		 16209 /* If the high bit of the first word is clear, and the bit pattern is not 0x1
16210 (EXIDX_CANTUNWIND), this is an offset to an .ARM.extab entry. */
16211 if ((second_word != 0x1) && ((second_word & 0x80000000ul) == 0))
16212 second_word = offset_prel31 (second_word, offset);
b38cadfb 16213
2468f9c9
PB		 16214 bfd_put_32 (output_bfd, first_word, to);
16215 bfd_put_32 (output_bfd, second_word, to + 4);
16216}
e489d0ae 16217
48229727
JB		 16218/* Data for make_branch_to_a8_stub(). */
16219
b38cadfb
NC		 16220struct a8_branch_to_stub_data
16221{
48229727
JB		 16222 asection *writing_section;
16223 bfd_byte *contents;
16224};
16225
16226
16227/* Helper to insert branches to Cortex-A8 erratum stubs in the right
16228 places for a particular section. */
16229
16230static bfd_boolean
16231make_branch_to_a8_stub (struct bfd_hash_entry *gen_entry,
99059e56 16232 void *in_arg)
48229727
JB		 16233{
16234 struct elf32_arm_stub_hash_entry *stub_entry;
16235 struct a8_branch_to_stub_data *data;
16236 bfd_byte *contents;
16237 unsigned long branch_insn;
16238 bfd_vma veneered_insn_loc, veneer_entry_loc;
16239 bfd_signed_vma branch_offset;
16240 bfd *abfd;
91d6fa6a 16241 unsigned int target;
48229727
JB		 16242
16243 stub_entry = (struct elf32_arm_stub_hash_entry *) gen_entry;
16244 data = (struct a8_branch_to_stub_data *) in_arg;
16245
16246 if (stub_entry->target_section != data->writing_section
4563a860 16247 || stub_entry->stub_type < arm_stub_a8_veneer_lwm)
48229727
JB		 16248 return TRUE;
16249
16250 contents = data->contents;
16251
16252 veneered_insn_loc = stub_entry->target_section->output_section->vma
16253 + stub_entry->target_section->output_offset
16254 + stub_entry->target_value;
16255
16256 veneer_entry_loc = stub_entry->stub_sec->output_section->vma
16257 + stub_entry->stub_sec->output_offset
16258 + stub_entry->stub_offset;
16259
16260 if (stub_entry->stub_type == arm_stub_a8_veneer_blx)
16261 veneered_insn_loc &= ~3u;
16262
16263 branch_offset = veneer_entry_loc - veneered_insn_loc - 4;
16264
16265 abfd = stub_entry->target_section->owner;
91d6fa6a 16266 target = stub_entry->target_value;
48229727
JB		 16267
16268 /* We attempt to avoid this condition by setting stubs_always_after_branch
16269 in elf32_arm_size_stubs if we've enabled the Cortex-A8 erratum workaround.
16270 This check is just to be on the safe side... */
16271 if ((veneered_insn_loc & ~0xfff) == (veneer_entry_loc & ~0xfff))
16272 {
16273 (*_bfd_error_handler) (_("%B: error: Cortex-A8 erratum stub is "
16274 "allocated in unsafe location"), abfd);
16275 return FALSE;
16276 }
16277
16278 switch (stub_entry->stub_type)
16279 {
16280 case arm_stub_a8_veneer_b:
16281 case arm_stub_a8_veneer_b_cond:
16282 branch_insn = 0xf0009000;
16283 goto jump24;
16284
16285 case arm_stub_a8_veneer_blx:
16286 branch_insn = 0xf000e800;
16287 goto jump24;
16288
16289 case arm_stub_a8_veneer_bl:
16290 {
16291 unsigned int i1, j1, i2, j2, s;
16292
16293 branch_insn = 0xf000d000;
16294
16295 jump24:
16296 if (branch_offset < -16777216 || branch_offset > 16777214)
16297 {
16298 /* There's not much we can do apart from complain if this
16299 happens. */
16300 (*_bfd_error_handler) (_("%B: error: Cortex-A8 erratum stub out "
16301 "of range (input file too large)"), abfd);
16302 return FALSE;
16303 }
16304
16305 /* i1 = not(j1 eor s), so:
16306 not i1 = j1 eor s
16307 j1 = (not i1) eor s. */
16308
16309 branch_insn |= (branch_offset >> 1) & 0x7ff;
16310 branch_insn |= ((branch_offset >> 12) & 0x3ff) << 16;
16311 i2 = (branch_offset >> 22) & 1;
16312 i1 = (branch_offset >> 23) & 1;
16313 s = (branch_offset >> 24) & 1;
16314 j1 = (!i1) ^ s;
16315 j2 = (!i2) ^ s;
16316 branch_insn |= j2 << 11;
16317 branch_insn |= j1 << 13;
16318 branch_insn |= s << 26;
16319 }
16320 break;
16321
16322 default:
16323 BFD_FAIL ();
16324 return FALSE;
16325 }
16326
91d6fa6a
NC		 16327 bfd_put_16 (abfd, (branch_insn >> 16) & 0xffff, &contents[target]);
16328 bfd_put_16 (abfd, branch_insn & 0xffff, &contents[target + 2]);
48229727
JB		 16329
16330 return TRUE;
16331}
16332
a504d23a
LA		 16333/* Beginning of stm32l4xx work-around. */
16334
16335/* Functions encoding instructions necessary for the emission of the
16336 fix-stm32l4xx-629360.
16337 Encoding is extracted from the
16338 ARM (C) Architecture Reference Manual
16339 ARMv7-A and ARMv7-R edition
16340 ARM DDI 0406C.b (ID072512). */
16341
16342static inline bfd_vma
82188b29 16343create_instruction_branch_absolute (int branch_offset)
a504d23a
LA		 16344{
16345 /* A8.8.18 B (A8-334)
16346 B target_address (Encoding T4). */
16347 /* 1111 - 0Sii - iiii - iiii - 10J1 - Jiii - iiii - iiii. */
16348 /* jump offset is: S:I1:I2:imm10:imm11:0. */
16349 /* with : I1 = NOT (J1 EOR S) I2 = NOT (J2 EOR S). */
16350
a504d23a
LA		 16351 int s = ((branch_offset & 0x1000000) >> 24);
16352 int j1 = s ^ !((branch_offset & 0x800000) >> 23);
16353 int j2 = s ^ !((branch_offset & 0x400000) >> 22);
16354
16355 if (branch_offset < -(1 << 24) || branch_offset >= (1 << 24))
16356 BFD_ASSERT (0 && "Error: branch out of range. Cannot create branch.");
16357
16358 bfd_vma patched_inst = 0xf0009000
16359 | s << 26 /* S. */
16360 | (((unsigned long) (branch_offset) >> 12) & 0x3ff) << 16 /* imm10. */
16361 | j1 << 13 /* J1. */
16362 | j2 << 11 /* J2. */
16363 | (((unsigned long) (branch_offset) >> 1) & 0x7ff); /* imm11. */
16364
16365 return patched_inst;
16366}
16367
16368static inline bfd_vma
16369create_instruction_ldmia (int base_reg, int wback, int reg_mask)
16370{
16371 /* A8.8.57 LDM/LDMIA/LDMFD (A8-396)
16372 LDMIA Rn!, {Ra, Rb, Rc, ...} (Encoding T2). */
16373 bfd_vma patched_inst = 0xe8900000
16374 | (/*W=*/wback << 21)
16375 | (base_reg << 16)
16376 | (reg_mask & 0x0000ffff);
16377
16378 return patched_inst;
16379}
16380
16381static inline bfd_vma
16382create_instruction_ldmdb (int base_reg, int wback, int reg_mask)
16383{
16384 /* A8.8.60 LDMDB/LDMEA (A8-402)
16385 LDMDB Rn!, {Ra, Rb, Rc, ...} (Encoding T1). */
16386 bfd_vma patched_inst = 0xe9100000
16387 | (/*W=*/wback << 21)
16388 | (base_reg << 16)
16389 | (reg_mask & 0x0000ffff);
16390
16391 return patched_inst;
16392}
16393
16394static inline bfd_vma
16395create_instruction_mov (int target_reg, int source_reg)
16396{
16397 /* A8.8.103 MOV (register) (A8-486)
16398 MOV Rd, Rm (Encoding T1). */
16399 bfd_vma patched_inst = 0x4600
16400 | (target_reg & 0x7)
16401 | ((target_reg & 0x8) >> 3) << 7
16402 | (source_reg << 3);
16403
16404 return patched_inst;
16405}
16406
16407static inline bfd_vma
16408create_instruction_sub (int target_reg, int source_reg, int value)
16409{
16410 /* A8.8.221 SUB (immediate) (A8-708)
16411 SUB Rd, Rn, #value (Encoding T3). */
16412 bfd_vma patched_inst = 0xf1a00000
16413 | (target_reg << 8)
16414 | (source_reg << 16)
16415 | (/*S=*/0 << 20)
16416 | ((value & 0x800) >> 11) << 26
16417 | ((value & 0x700) >> 8) << 12
16418 | (value & 0x0ff);
16419
16420 return patched_inst;
16421}
16422
16423static inline bfd_vma
16424create_instruction_vldmia (int base_reg, int wback, int num_regs,
16425 int first_reg)
16426{
16427 /* A8.8.332 VLDM (A8-922)
16428 VLMD{MODE} Rn{!}, {list} (Encoding T2). */
16429 bfd_vma patched_inst = 0xec900a00
16430 | (/*W=*/wback << 21)
16431 | (base_reg << 16)
16432 | (num_regs & 0x000000ff)
16433 | (((unsigned)first_reg>>1) & 0x0000000f) << 12
16434 | (first_reg & 0x00000001) << 22;
16435
16436 return patched_inst;
16437}
16438
16439static inline bfd_vma
16440create_instruction_vldmdb (int base_reg, int num_regs, int first_reg)
16441{
16442 /* A8.8.332 VLDM (A8-922)
16443 VLMD{MODE} Rn!, {} (Encoding T2). */
16444 bfd_vma patched_inst = 0xed300a00
16445 | (base_reg << 16)
16446 | (num_regs & 0x000000ff)
16447 | (((unsigned)first_reg>>1) & 0x0000000f) << 12
16448 | (first_reg & 0x00000001) << 22;
16449
16450 return patched_inst;
16451}
16452
16453static inline bfd_vma
16454create_instruction_udf_w (int value)
16455{
16456 /* A8.8.247 UDF (A8-758)
16457 Undefined (Encoding T2). */
16458 bfd_vma patched_inst = 0xf7f0a000
16459 | (value & 0x00000fff)
16460 | (value & 0x000f0000) << 16;
16461
16462 return patched_inst;
16463}
16464
16465static inline bfd_vma
16466create_instruction_udf (int value)
16467{
16468 /* A8.8.247 UDF (A8-758)
16469 Undefined (Encoding T1). */
16470 bfd_vma patched_inst = 0xde00
16471 | (value & 0xff);
16472
16473 return patched_inst;
16474}
16475
16476/* Functions writing an instruction in memory, returning the next
16477 memory position to write to. */
16478
16479static inline bfd_byte *
16480push_thumb2_insn32 (struct elf32_arm_link_hash_table * htab,
16481 bfd * output_bfd, bfd_byte *pt, insn32 insn)
16482{
16483 put_thumb2_insn (htab, output_bfd, insn, pt);
16484 return pt + 4;
16485}
16486
16487static inline bfd_byte *
16488push_thumb2_insn16 (struct elf32_arm_link_hash_table * htab,
16489 bfd * output_bfd, bfd_byte *pt, insn32 insn)
16490{
16491 put_thumb_insn (htab, output_bfd, insn, pt);
16492 return pt + 2;
16493}
16494
16495/* Function filling up a region in memory with T1 and T2 UDFs taking
16496 care of alignment. */
16497
16498static bfd_byte *
16499stm32l4xx_fill_stub_udf (struct elf32_arm_link_hash_table * htab,
16500 bfd * output_bfd,
16501 const bfd_byte * const base_stub_contents,
16502 bfd_byte * const from_stub_contents,
16503 const bfd_byte * const end_stub_contents)
16504{
16505 bfd_byte *current_stub_contents = from_stub_contents;
16506
16507 /* Fill the remaining of the stub with deterministic contents : UDF
16508 instructions.
16509 Check if realignment is needed on modulo 4 frontier using T1, to
16510 further use T2. */
16511 if ((current_stub_contents < end_stub_contents)
16512 && !((current_stub_contents - base_stub_contents) % 2)
16513 && ((current_stub_contents - base_stub_contents) % 4))
16514 current_stub_contents =
16515 push_thumb2_insn16 (htab, output_bfd, current_stub_contents,
16516 create_instruction_udf (0));
16517
16518 for (; current_stub_contents < end_stub_contents;)
16519 current_stub_contents =
16520 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
16521 create_instruction_udf_w (0));
16522
16523 return current_stub_contents;
16524}
16525
16526/* Functions writing the stream of instructions equivalent to the
16527 derived sequence for ldmia, ldmdb, vldm respectively. */
16528
16529static void
16530stm32l4xx_create_replacing_stub_ldmia (struct elf32_arm_link_hash_table * htab,
16531 bfd * output_bfd,
16532 const insn32 initial_insn,
16533 const bfd_byte *const initial_insn_addr,
16534 bfd_byte *const base_stub_contents)
16535{
16536 int wback = (initial_insn & 0x00200000) >> 21;
16537 int ri, rn = (initial_insn & 0x000F0000) >> 16;
16538 int insn_all_registers = initial_insn & 0x0000ffff;
16539 int insn_low_registers, insn_high_registers;
16540 int usable_register_mask;
16541 int nb_registers = popcount (insn_all_registers);
16542 int restore_pc = (insn_all_registers & (1 << 15)) ? 1 : 0;
16543 int restore_rn = (insn_all_registers & (1 << rn)) ? 1 : 0;
16544 bfd_byte *current_stub_contents = base_stub_contents;
16545
16546 BFD_ASSERT (is_thumb2_ldmia (initial_insn));
16547
16548 /* In BFD_ARM_STM32L4XX_FIX_ALL mode we may have to deal with
16549 smaller than 8 registers load sequences that do not cause the
16550 hardware issue. */
16551 if (nb_registers <= 8)
16552 {
16553 /* UNTOUCHED : LDMIA Rn{!}, {R-all-register-list}. */
16554 current_stub_contents =
16555 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
16556 initial_insn);
16557
16558 /* B initial_insn_addr+4. */
16559 if (!restore_pc)
16560 current_stub_contents =
16561 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
16562 create_instruction_branch_absolute
82188b29
NC		 16563 (initial_insn_addr - current_stub_contents));
16564
a504d23a
LA		 16565
16566 /* Fill the remaining of the stub with deterministic contents. */
16567 current_stub_contents =
16568 stm32l4xx_fill_stub_udf (htab, output_bfd,
16569 base_stub_contents, current_stub_contents,
16570 base_stub_contents +
16571 STM32L4XX_ERRATUM_LDM_VENEER_SIZE);
16572
16573 return;
16574 }
16575
16576 /* - reg_list[13] == 0. */
16577 BFD_ASSERT ((insn_all_registers & (1 << 13))==0);
16578
16579 /* - reg_list[14] & reg_list[15] != 1. */
16580 BFD_ASSERT ((insn_all_registers & 0xC000) != 0xC000);
16581
16582 /* - if (wback==1) reg_list[rn] == 0. */
16583 BFD_ASSERT (!wback || !restore_rn);
16584
16585 /* - nb_registers > 8. */
16586 BFD_ASSERT (popcount (insn_all_registers) > 8);
16587
16588 /* At this point, LDMxx initial insn loads between 9 and 14 registers. */
16589
16590 /* In the following algorithm, we split this wide LDM using 2 LDM insns:
16591 - One with the 7 lowest registers (register mask 0x007F)
16592 This LDM will finally contain between 2 and 7 registers
16593 - One with the 7 highest registers (register mask 0xDF80)
16594 This ldm will finally contain between 2 and 7 registers. */
16595 insn_low_registers = insn_all_registers & 0x007F;
16596 insn_high_registers = insn_all_registers & 0xDF80;
16597
16598 /* A spare register may be needed during this veneer to temporarily
16599 handle the base register. This register will be restored with the
16600 last LDM operation.
16601 The usable register may be any general purpose register (that
16602 excludes PC, SP, LR : register mask is 0x1FFF). */
16603 usable_register_mask = 0x1FFF;
16604
16605 /* Generate the stub function. */
16606 if (wback)
16607 {
16608 /* LDMIA Rn!, {R-low-register-list} : (Encoding T2). */
16609 current_stub_contents =
16610 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
16611 create_instruction_ldmia
16612 (rn, /*wback=*/1, insn_low_registers));
16613
16614 /* LDMIA Rn!, {R-high-register-list} : (Encoding T2). */
16615 current_stub_contents =
16616 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
16617 create_instruction_ldmia
16618 (rn, /*wback=*/1, insn_high_registers));
16619 if (!restore_pc)
16620 {
16621 /* B initial_insn_addr+4. */
16622 current_stub_contents =
16623 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
16624 create_instruction_branch_absolute
82188b29 16625 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 16626 }
16627 }
16628 else /* if (!wback). */
16629 {
16630 ri = rn;
16631
16632 /* If Rn is not part of the high-register-list, move it there. */
16633 if (!(insn_high_registers & (1 << rn)))
16634 {
16635 /* Choose a Ri in the high-register-list that will be restored. */
16636 ri = ctz (insn_high_registers & usable_register_mask & ~(1 << rn));
16637
16638 /* MOV Ri, Rn. */
16639 current_stub_contents =
16640 push_thumb2_insn16 (htab, output_bfd, current_stub_contents,
16641 create_instruction_mov (ri, rn));
16642 }
16643
16644 /* LDMIA Ri!, {R-low-register-list} : (Encoding T2). */
16645 current_stub_contents =
16646 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
16647 create_instruction_ldmia
16648 (ri, /*wback=*/1, insn_low_registers));
16649
16650 /* LDMIA Ri, {R-high-register-list} : (Encoding T2). */
16651 current_stub_contents =
16652 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
16653 create_instruction_ldmia
16654 (ri, /*wback=*/0, insn_high_registers));
16655
16656 if (!restore_pc)
16657 {
16658 /* B initial_insn_addr+4. */
16659 current_stub_contents =
16660 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
16661 create_instruction_branch_absolute
82188b29 16662 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 16663 }
16664 }
16665
16666 /* Fill the remaining of the stub with deterministic contents. */
16667 current_stub_contents =
16668 stm32l4xx_fill_stub_udf (htab, output_bfd,
16669 base_stub_contents, current_stub_contents,
16670 base_stub_contents +
16671 STM32L4XX_ERRATUM_LDM_VENEER_SIZE);
16672}
16673
16674static void
16675stm32l4xx_create_replacing_stub_ldmdb (struct elf32_arm_link_hash_table * htab,
16676 bfd * output_bfd,
16677 const insn32 initial_insn,
16678 const bfd_byte *const initial_insn_addr,
16679 bfd_byte *const base_stub_contents)
16680{
16681 int wback = (initial_insn & 0x00200000) >> 21;
16682 int ri, rn = (initial_insn & 0x000f0000) >> 16;
16683 int insn_all_registers = initial_insn & 0x0000ffff;
16684 int insn_low_registers, insn_high_registers;
16685 int usable_register_mask;
16686 int restore_pc = (insn_all_registers & (1 << 15)) ? 1 : 0;
16687 int restore_rn = (insn_all_registers & (1 << rn)) ? 1 : 0;
16688 int nb_registers = popcount (insn_all_registers);
16689 bfd_byte *current_stub_contents = base_stub_contents;
16690
16691 BFD_ASSERT (is_thumb2_ldmdb (initial_insn));
16692
16693 /* In BFD_ARM_STM32L4XX_FIX_ALL mode we may have to deal with
16694 smaller than 8 registers load sequences that do not cause the
16695 hardware issue. */
16696 if (nb_registers <= 8)
16697 {
16698 /* UNTOUCHED : LDMIA Rn{!}, {R-all-register-list}. */
16699 current_stub_contents =
16700 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
16701 initial_insn);
16702
16703 /* B initial_insn_addr+4. */
16704 current_stub_contents =
16705 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
16706 create_instruction_branch_absolute
82188b29 16707 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 16708
16709 /* Fill the remaining of the stub with deterministic contents. */
16710 current_stub_contents =
16711 stm32l4xx_fill_stub_udf (htab, output_bfd,
16712 base_stub_contents, current_stub_contents,
16713 base_stub_contents +
16714 STM32L4XX_ERRATUM_LDM_VENEER_SIZE);
16715
16716 return;
16717 }
16718
16719 /* - reg_list[13] == 0. */
16720 BFD_ASSERT ((insn_all_registers & (1 << 13)) == 0);
16721
16722 /* - reg_list[14] & reg_list[15] != 1. */
16723 BFD_ASSERT ((insn_all_registers & 0xC000) != 0xC000);
16724
16725 /* - if (wback==1) reg_list[rn] == 0. */
16726 BFD_ASSERT (!wback || !restore_rn);
16727
16728 /* - nb_registers > 8. */
16729 BFD_ASSERT (popcount (insn_all_registers) > 8);
16730
16731 /* At this point, LDMxx initial insn loads between 9 and 14 registers. */
16732
16733 /* In the following algorithm, we split this wide LDM using 2 LDM insn:
16734 - One with the 7 lowest registers (register mask 0x007F)
16735 This LDM will finally contain between 2 and 7 registers
16736 - One with the 7 highest registers (register mask 0xDF80)
16737 This ldm will finally contain between 2 and 7 registers. */
16738 insn_low_registers = insn_all_registers & 0x007F;
16739 insn_high_registers = insn_all_registers & 0xDF80;
16740
16741 /* A spare register may be needed during this veneer to temporarily
16742 handle the base register. This register will be restored with
16743 the last LDM operation.
16744 The usable register may be any general purpose register (that excludes
16745 PC, SP, LR : register mask is 0x1FFF). */
16746 usable_register_mask = 0x1FFF;
16747
16748 /* Generate the stub function. */
16749 if (!wback && !restore_pc && !restore_rn)
16750 {
16751 /* Choose a Ri in the low-register-list that will be restored. */
16752 ri = ctz (insn_low_registers & usable_register_mask & ~(1 << rn));
16753
16754 /* MOV Ri, Rn. */
16755 current_stub_contents =
16756 push_thumb2_insn16 (htab, output_bfd, current_stub_contents,
16757 create_instruction_mov (ri, rn));
16758
16759 /* LDMDB Ri!, {R-high-register-list}. */
16760 current_stub_contents =
16761 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
16762 create_instruction_ldmdb
16763 (ri, /*wback=*/1, insn_high_registers));
16764
16765 /* LDMDB Ri, {R-low-register-list}. */
16766 current_stub_contents =
16767 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
16768 create_instruction_ldmdb
16769 (ri, /*wback=*/0, insn_low_registers));
16770
16771 /* B initial_insn_addr+4. */
16772 current_stub_contents =
16773 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
16774 create_instruction_branch_absolute
82188b29 16775 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 16776 }
16777 else if (wback && !restore_pc && !restore_rn)
16778 {
16779 /* LDMDB Rn!, {R-high-register-list}. */
16780 current_stub_contents =
16781 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
16782 create_instruction_ldmdb
16783 (rn, /*wback=*/1, insn_high_registers));
16784
16785 /* LDMDB Rn!, {R-low-register-list}. */
16786 current_stub_contents =
16787 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
16788 create_instruction_ldmdb
16789 (rn, /*wback=*/1, insn_low_registers));
16790
16791 /* B initial_insn_addr+4. */
16792 current_stub_contents =
16793 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
16794 create_instruction_branch_absolute
82188b29 16795 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 16796 }
16797 else if (!wback && restore_pc && !restore_rn)
16798 {
16799 /* Choose a Ri in the high-register-list that will be restored. */
16800 ri = ctz (insn_high_registers & usable_register_mask & ~(1 << rn));
16801
16802 /* SUB Ri, Rn, #(4*nb_registers). */
16803 current_stub_contents =
16804 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
16805 create_instruction_sub (ri, rn, (4 * nb_registers)));
16806
16807 /* LDMIA Ri!, {R-low-register-list}. */
16808 current_stub_contents =
16809 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
16810 create_instruction_ldmia
16811 (ri, /*wback=*/1, insn_low_registers));
16812
16813 /* LDMIA Ri, {R-high-register-list}. */
16814 current_stub_contents =
16815 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
16816 create_instruction_ldmia
16817 (ri, /*wback=*/0, insn_high_registers));
16818 }
16819 else if (wback && restore_pc && !restore_rn)
16820 {
16821 /* Choose a Ri in the high-register-list that will be restored. */
16822 ri = ctz (insn_high_registers & usable_register_mask & ~(1 << rn));
16823
16824 /* SUB Rn, Rn, #(4*nb_registers) */
16825 current_stub_contents =
16826 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
16827 create_instruction_sub (rn, rn, (4 * nb_registers)));
16828
16829 /* MOV Ri, Rn. */
16830 current_stub_contents =
16831 push_thumb2_insn16 (htab, output_bfd, current_stub_contents,
16832 create_instruction_mov (ri, rn));
16833
16834 /* LDMIA Ri!, {R-low-register-list}. */
16835 current_stub_contents =
16836 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
16837 create_instruction_ldmia
16838 (ri, /*wback=*/1, insn_low_registers));
16839
16840 /* LDMIA Ri, {R-high-register-list}. */
16841 current_stub_contents =
16842 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
16843 create_instruction_ldmia
16844 (ri, /*wback=*/0, insn_high_registers));
16845 }
16846 else if (!wback && !restore_pc && restore_rn)
16847 {
16848 ri = rn;
16849 if (!(insn_low_registers & (1 << rn)))
16850 {
16851 /* Choose a Ri in the low-register-list that will be restored. */
16852 ri = ctz (insn_low_registers & usable_register_mask & ~(1 << rn));
16853
16854 /* MOV Ri, Rn. */
16855 current_stub_contents =
16856 push_thumb2_insn16 (htab, output_bfd, current_stub_contents,
16857 create_instruction_mov (ri, rn));
16858 }
16859
16860 /* LDMDB Ri!, {R-high-register-list}. */
16861 current_stub_contents =
16862 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
16863 create_instruction_ldmdb
16864 (ri, /*wback=*/1, insn_high_registers));
16865
16866 /* LDMDB Ri, {R-low-register-list}. */
16867 current_stub_contents =
16868 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
16869 create_instruction_ldmdb
16870 (ri, /*wback=*/0, insn_low_registers));
16871
16872 /* B initial_insn_addr+4. */
16873 current_stub_contents =
16874 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
16875 create_instruction_branch_absolute
82188b29 16876 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 16877 }
16878 else if (!wback && restore_pc && restore_rn)
16879 {
16880 ri = rn;
16881 if (!(insn_high_registers & (1 << rn)))
16882 {
16883 /* Choose a Ri in the high-register-list that will be restored. */
16884 ri = ctz (insn_high_registers & usable_register_mask & ~(1 << rn));
16885 }
16886
16887 /* SUB Ri, Rn, #(4*nb_registers). */
16888 current_stub_contents =
16889 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
16890 create_instruction_sub (ri, rn, (4 * nb_registers)));
16891
16892 /* LDMIA Ri!, {R-low-register-list}. */
16893 current_stub_contents =
16894 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
16895 create_instruction_ldmia
16896 (ri, /*wback=*/1, insn_low_registers));
16897
16898 /* LDMIA Ri, {R-high-register-list}. */
16899 current_stub_contents =
16900 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
16901 create_instruction_ldmia
16902 (ri, /*wback=*/0, insn_high_registers));
16903 }
16904 else if (wback && restore_rn)
16905 {
16906 /* The assembler should not have accepted to encode this. */
16907 BFD_ASSERT (0 && "Cannot patch an instruction that has an "
16908 "undefined behavior.\n");
16909 }
16910
16911 /* Fill the remaining of the stub with deterministic contents. */
16912 current_stub_contents =
16913 stm32l4xx_fill_stub_udf (htab, output_bfd,
16914 base_stub_contents, current_stub_contents,
16915 base_stub_contents +
16916 STM32L4XX_ERRATUM_LDM_VENEER_SIZE);
16917
16918}
16919
16920static void
16921stm32l4xx_create_replacing_stub_vldm (struct elf32_arm_link_hash_table * htab,
16922 bfd * output_bfd,
16923 const insn32 initial_insn,
16924 const bfd_byte *const initial_insn_addr,
16925 bfd_byte *const base_stub_contents)
16926{
16927 int num_regs = ((unsigned int)initial_insn << 24) >> 24;
16928 bfd_byte *current_stub_contents = base_stub_contents;
16929
16930 BFD_ASSERT (is_thumb2_vldm (initial_insn));
16931
16932 /* In BFD_ARM_STM32L4XX_FIX_ALL mode we may have to deal with
16933 smaller than 8 registers load sequences that do not cause the
16934 hardware issue. */
16935 if (num_regs <= 8)
16936 {
16937 /* Untouched instruction. */
16938 current_stub_contents =
16939 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
16940 initial_insn);
16941
16942 /* B initial_insn_addr+4. */
16943 current_stub_contents =
16944 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
16945 create_instruction_branch_absolute
82188b29 16946 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 16947 }
16948 else
16949 {
16950 bfd_boolean is_ia_nobang = /* (IA without !). */
16951 (((initial_insn << 7) >> 28) & 0xd) == 0x4;
16952 bfd_boolean is_ia_bang = /* (IA with !) - includes VPOP. */
16953 (((initial_insn << 7) >> 28) & 0xd) == 0x5;
16954 bfd_boolean is_db_bang = /* (DB with !). */
16955 (((initial_insn << 7) >> 28) & 0xd) == 0x9;
16956 int base_reg = ((unsigned int)initial_insn << 12) >> 28;
16957 /* d = UInt (Vd:D);. */
16958 int first_reg = ((((unsigned int)initial_insn << 16) >> 28) << 1)
16959 | (((unsigned int)initial_insn << 9) >> 31);
16960
16961 /* Compute the number of 8-register chunks needed to split. */
16962 int chunks = (num_regs%8) ? (num_regs/8 + 1) : (num_regs/8);
16963 int chunk;
16964
16965 /* The test coverage has been done assuming the following
16966 hypothesis that exactly one of the previous is_ predicates is
16967 true. */
16968 BFD_ASSERT ((is_ia_nobang ^ is_ia_bang ^ is_db_bang) &&
16969 !(is_ia_nobang & is_ia_bang & is_db_bang));
16970
16971 /* We treat the cutting of the register in one pass for all
16972 cases, then we emit the adjustments:
16973
16974 vldm rx, {...}
16975 -> vldm rx!, {8_words_or_less} for each needed 8_word
16976 -> sub rx, rx, #size (list)
16977
16978 vldm rx!, {...}
16979 -> vldm rx!, {8_words_or_less} for each needed 8_word
16980 This also handles vpop instruction (when rx is sp)
16981
16982 vldmd rx!, {...}
16983 -> vldmb rx!, {8_words_or_less} for each needed 8_word. */
16984 for (chunk = 0; chunk<chunks; ++chunk)
16985 {
16986 if (is_ia_nobang || is_ia_bang)
16987 {
16988 current_stub_contents =
16989 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
16990 create_instruction_vldmia
16991 (base_reg,
16992 /*wback= . */1,
16993 chunks - (chunk + 1) ?
16994 8 : num_regs - chunk * 8,
16995 first_reg + chunk * 8));
16996 }
16997 else if (is_db_bang)
16998 {
16999 current_stub_contents =
17000 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
17001 create_instruction_vldmdb
17002 (base_reg,
17003 chunks - (chunk + 1) ?
17004 8 : num_regs - chunk * 8,
17005 first_reg + chunk * 8));
17006 }
17007 }
17008
17009 /* Only this case requires the base register compensation
17010 subtract. */
17011 if (is_ia_nobang)
17012 {
17013 current_stub_contents =
17014 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
17015 create_instruction_sub
17016 (base_reg, base_reg, 4*num_regs));
17017 }
17018
17019 /* B initial_insn_addr+4. */
17020 current_stub_contents =
17021 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
17022 create_instruction_branch_absolute
82188b29 17023 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 17024 }
17025
17026 /* Fill the remaining of the stub with deterministic contents. */
17027 current_stub_contents =
17028 stm32l4xx_fill_stub_udf (htab, output_bfd,
17029 base_stub_contents, current_stub_contents,
17030 base_stub_contents +
17031 STM32L4XX_ERRATUM_VLDM_VENEER_SIZE);
17032}
17033
17034static void
17035stm32l4xx_create_replacing_stub (struct elf32_arm_link_hash_table * htab,
17036 bfd * output_bfd,
17037 const insn32 wrong_insn,
17038 const bfd_byte *const wrong_insn_addr,
17039 bfd_byte *const stub_contents)
17040{
17041 if (is_thumb2_ldmia (wrong_insn))
17042 stm32l4xx_create_replacing_stub_ldmia (htab, output_bfd,
17043 wrong_insn, wrong_insn_addr,
17044 stub_contents);
17045 else if (is_thumb2_ldmdb (wrong_insn))
17046 stm32l4xx_create_replacing_stub_ldmdb (htab, output_bfd,
17047 wrong_insn, wrong_insn_addr,
17048 stub_contents);
17049 else if (is_thumb2_vldm (wrong_insn))
17050 stm32l4xx_create_replacing_stub_vldm (htab, output_bfd,
17051 wrong_insn, wrong_insn_addr,
17052 stub_contents);
17053}
17054
17055/* End of stm32l4xx work-around. */
17056
17057
491d01d3
YU		 17058static void
17059elf32_arm_add_relocation (bfd *output_bfd, struct bfd_link_info *info,
17060 asection *output_sec, Elf_Internal_Rela *rel)
17061{
17062 BFD_ASSERT (output_sec && rel);
17063 struct bfd_elf_section_reloc_data *output_reldata;
17064 struct elf32_arm_link_hash_table *htab;
17065 struct bfd_elf_section_data *oesd = elf_section_data (output_sec);
17066 Elf_Internal_Shdr *rel_hdr;
17067
17068
17069 if (oesd->rel.hdr)
17070 {
17071 rel_hdr = oesd->rel.hdr;
17072 output_reldata = &(oesd->rel);
17073 }
17074 else if (oesd->rela.hdr)
17075 {
17076 rel_hdr = oesd->rela.hdr;
17077 output_reldata = &(oesd->rela);
17078 }
17079 else
17080 {
17081 abort ();
17082 }
17083
17084 bfd_byte *erel = rel_hdr->contents;
17085 erel += output_reldata->count * rel_hdr->sh_entsize;
17086 htab = elf32_arm_hash_table (info);
17087 SWAP_RELOC_OUT (htab) (output_bfd, rel, erel);
17088 output_reldata->count++;
17089}
17090
e489d0ae
PB		 17091/* Do code byteswapping. Return FALSE afterwards so that the section is
17092 written out as normal. */
17093
17094static bfd_boolean
c7b8f16e 17095elf32_arm_write_section (bfd *output_bfd,
8029a119
NC		 17096 struct bfd_link_info *link_info,
17097 asection *sec,
e489d0ae
PB		 17098 bfd_byte *contents)
17099{
48229727 17100 unsigned int mapcount, errcount;
8e3de13a 17101 _arm_elf_section_data *arm_data;
c7b8f16e 17102 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (link_info);
e489d0ae 17103 elf32_arm_section_map *map;
c7b8f16e 17104 elf32_vfp11_erratum_list *errnode;
a504d23a 17105 elf32_stm32l4xx_erratum_list *stm32l4xx_errnode;
e489d0ae
PB		 17106 bfd_vma ptr;
17107 bfd_vma end;
c7b8f16e 17108 bfd_vma offset = sec->output_section->vma + sec->output_offset;
e489d0ae 17109 bfd_byte tmp;
48229727 17110 unsigned int i;
57e8b36a 17111
4dfe6ac6
NC		 17112 if (globals == NULL)
17113 return FALSE;
17114
8e3de13a
NC		 17115 /* If this section has not been allocated an _arm_elf_section_data
17116 structure then we cannot record anything. */
17117 arm_data = get_arm_elf_section_data (sec);
17118 if (arm_data == NULL)
17119 return FALSE;
17120
17121 mapcount = arm_data->mapcount;
17122 map = arm_data->map;
c7b8f16e
JB		 17123 errcount = arm_data->erratumcount;
17124
17125 if (errcount != 0)
17126 {
17127 unsigned int endianflip = bfd_big_endian (output_bfd) ? 3 : 0;
17128
17129 for (errnode = arm_data->erratumlist; errnode != 0;
99059e56
RM		 17130 errnode = errnode->next)
17131 {
17132 bfd_vma target = errnode->vma - offset;
17133
17134 switch (errnode->type)
17135 {
17136 case VFP11_ERRATUM_BRANCH_TO_ARM_VENEER:
17137 {
17138 bfd_vma branch_to_veneer;
17139 /* Original condition code of instruction, plus bit mask for
17140 ARM B instruction. */
17141 unsigned int insn = (errnode->u.b.vfp_insn & 0xf0000000)
17142 | 0x0a000000;
c7b8f16e
JB		 17143
17144 /* The instruction is before the label. */
91d6fa6a 17145 target -= 4;
c7b8f16e
JB		 17146
17147 /* Above offset included in -4 below. */
17148 branch_to_veneer = errnode->u.b.veneer->vma
99059e56 17149 - errnode->vma - 4;
c7b8f16e
JB		 17150
17151 if ((signed) branch_to_veneer < -(1 << 25)
17152 || (signed) branch_to_veneer >= (1 << 25))
17153 (*_bfd_error_handler) (_("%B: error: VFP11 veneer out of "
17154 "range"), output_bfd);
17155
99059e56
RM		 17156 insn |= (branch_to_veneer >> 2) & 0xffffff;
17157 contents[endianflip ^ target] = insn & 0xff;
17158 contents[endianflip ^ (target + 1)] = (insn >> 8) & 0xff;
17159 contents[endianflip ^ (target + 2)] = (insn >> 16) & 0xff;
17160 contents[endianflip ^ (target + 3)] = (insn >> 24) & 0xff;
17161 }
17162 break;
c7b8f16e
JB		 17163
17164 case VFP11_ERRATUM_ARM_VENEER:
99059e56
RM		 17165 {
17166 bfd_vma branch_from_veneer;
17167 unsigned int insn;
c7b8f16e 17168
99059e56
RM		 17169 /* Take size of veneer into account. */
17170 branch_from_veneer = errnode->u.v.branch->vma
17171 - errnode->vma - 12;
c7b8f16e
JB		 17172
17173 if ((signed) branch_from_veneer < -(1 << 25)
17174 || (signed) branch_from_veneer >= (1 << 25))
17175 (*_bfd_error_handler) (_("%B: error: VFP11 veneer out of "
17176 "range"), output_bfd);
17177
99059e56
RM		 17178 /* Original instruction. */
17179 insn = errnode->u.v.branch->u.b.vfp_insn;
17180 contents[endianflip ^ target] = insn & 0xff;
17181 contents[endianflip ^ (target + 1)] = (insn >> 8) & 0xff;
17182 contents[endianflip ^ (target + 2)] = (insn >> 16) & 0xff;
17183 contents[endianflip ^ (target + 3)] = (insn >> 24) & 0xff;
17184
17185 /* Branch back to insn after original insn. */
17186 insn = 0xea000000 | ((branch_from_veneer >> 2) & 0xffffff);
17187 contents[endianflip ^ (target + 4)] = insn & 0xff;
17188 contents[endianflip ^ (target + 5)] = (insn >> 8) & 0xff;
17189 contents[endianflip ^ (target + 6)] = (insn >> 16) & 0xff;
17190 contents[endianflip ^ (target + 7)] = (insn >> 24) & 0xff;
17191 }
17192 break;
c7b8f16e 17193
99059e56
RM		 17194 default:
17195 abort ();
17196 }
17197 }
c7b8f16e 17198 }
e489d0ae 17199
a504d23a
LA		 17200 if (arm_data->stm32l4xx_erratumcount != 0)
17201 {
17202 for (stm32l4xx_errnode = arm_data->stm32l4xx_erratumlist;
17203 stm32l4xx_errnode != 0;
17204 stm32l4xx_errnode = stm32l4xx_errnode->next)
17205 {
17206 bfd_vma target = stm32l4xx_errnode->vma - offset;
17207
17208 switch (stm32l4xx_errnode->type)
17209 {
17210 case STM32L4XX_ERRATUM_BRANCH_TO_VENEER:
17211 {
17212 unsigned int insn;
17213 bfd_vma branch_to_veneer =
17214 stm32l4xx_errnode->u.b.veneer->vma - stm32l4xx_errnode->vma;
17215
17216 if ((signed) branch_to_veneer < -(1 << 24)
17217 || (signed) branch_to_veneer >= (1 << 24))
17218 {
17219 bfd_vma out_of_range =
17220 ((signed) branch_to_veneer < -(1 << 24)) ?
17221 - branch_to_veneer - (1 << 24) :
17222 ((signed) branch_to_veneer >= (1 << 24)) ?
17223 branch_to_veneer - (1 << 24) : 0;
17224
17225 (*_bfd_error_handler)
17226 (_("%B(%#x): error: Cannot create STM32L4XX veneer. "
eee926f2 17227 "Jump out of range by %ld bytes. "
a504d23a
LA		 17228 "Cannot encode branch instruction. "),
17229 output_bfd,
eee926f2 17230 (long) (stm32l4xx_errnode->vma - 4),
a504d23a
LA		 17231 out_of_range);
17232 continue;
17233 }
17234
17235 insn = create_instruction_branch_absolute
82188b29 17236 (stm32l4xx_errnode->u.b.veneer->vma - stm32l4xx_errnode->vma);
a504d23a
LA		 17237
17238 /* The instruction is before the label. */
17239 target -= 4;
17240
17241 put_thumb2_insn (globals, output_bfd,
17242 (bfd_vma) insn, contents + target);
17243 }
17244 break;
17245
17246 case STM32L4XX_ERRATUM_VENEER:
17247 {
82188b29
NC		 17248 bfd_byte * veneer;
17249 bfd_byte * veneer_r;
a504d23a
LA		 17250 unsigned int insn;
17251
82188b29
NC		 17252 veneer = contents + target;
17253 veneer_r = veneer
17254 + stm32l4xx_errnode->u.b.veneer->vma
17255 - stm32l4xx_errnode->vma - 4;
a504d23a
LA		 17256
17257 if ((signed) (veneer_r - veneer -
17258 STM32L4XX_ERRATUM_VLDM_VENEER_SIZE >
17259 STM32L4XX_ERRATUM_LDM_VENEER_SIZE ?
17260 STM32L4XX_ERRATUM_VLDM_VENEER_SIZE :
17261 STM32L4XX_ERRATUM_LDM_VENEER_SIZE) < -(1 << 24)
17262 || (signed) (veneer_r - veneer) >= (1 << 24))
17263 {
17264 (*_bfd_error_handler) (_("%B: error: Cannot create STM32L4XX "
17265 "veneer."), output_bfd);
17266 continue;
17267 }
17268
17269 /* Original instruction. */
17270 insn = stm32l4xx_errnode->u.v.branch->u.b.insn;
17271
17272 stm32l4xx_create_replacing_stub
17273 (globals, output_bfd, insn, (void*)veneer_r, (void*)veneer);
17274 }
17275 break;
17276
17277 default:
17278 abort ();
17279 }
17280 }
17281 }
17282
2468f9c9
PB		 17283 if (arm_data->elf.this_hdr.sh_type == SHT_ARM_EXIDX)
17284 {
17285 arm_unwind_table_edit *edit_node
99059e56 17286 = arm_data->u.exidx.unwind_edit_list;
2468f9c9 17287 /* Now, sec->size is the size of the section we will write. The original
99059e56 17288 size (before we merged duplicate entries and inserted EXIDX_CANTUNWIND
2468f9c9
PB		 17289 markers) was sec->rawsize. (This isn't the case if we perform no
17290 edits, then rawsize will be zero and we should use size). */
21d799b5 17291 bfd_byte *edited_contents = (bfd_byte *) bfd_malloc (sec->size);
2468f9c9
PB		 17292 unsigned int input_size = sec->rawsize ? sec->rawsize : sec->size;
17293 unsigned int in_index, out_index;
17294 bfd_vma add_to_offsets = 0;
17295
17296 for (in_index = 0, out_index = 0; in_index * 8 < input_size || edit_node;)
99059e56 17297 {
2468f9c9
PB		 17298 if (edit_node)
17299 {
17300 unsigned int edit_index = edit_node->index;
b38cadfb 17301
2468f9c9 17302 if (in_index < edit_index && in_index * 8 < input_size)
99059e56 17303 {
2468f9c9
PB		 17304 copy_exidx_entry (output_bfd, edited_contents + out_index * 8,
17305 contents + in_index * 8, add_to_offsets);
17306 out_index++;
17307 in_index++;
17308 }
17309 else if (in_index == edit_index
17310 || (in_index * 8 >= input_size
17311 && edit_index == UINT_MAX))
99059e56 17312 {
2468f9c9
PB		 17313 switch (edit_node->type)
17314 {
17315 case DELETE_EXIDX_ENTRY:
17316 in_index++;
17317 add_to_offsets += 8;
17318 break;
b38cadfb 17319
2468f9c9
PB		 17320 case INSERT_EXIDX_CANTUNWIND_AT_END:
17321 {
99059e56 17322 asection *text_sec = edit_node->linked_section;
2468f9c9
PB		 17323 bfd_vma text_offset = text_sec->output_section->vma
17324 + text_sec->output_offset
17325 + text_sec->size;
17326 bfd_vma exidx_offset = offset + out_index * 8;
99059e56 17327 unsigned long prel31_offset;
2468f9c9
PB		 17328
17329 /* Note: this is meant to be equivalent to an
17330 R_ARM_PREL31 relocation. These synthetic
17331 EXIDX_CANTUNWIND markers are not relocated by the
17332 usual BFD method. */
17333 prel31_offset = (text_offset - exidx_offset)
17334 & 0x7ffffffful;
491d01d3
YU		 17335 if (bfd_link_relocatable (link_info))
17336 {
17337 /* Here relocation for new EXIDX_CANTUNWIND is
17338 created, so there is no need to
17339 adjust offset by hand. */
17340 prel31_offset = text_sec->output_offset
17341 + text_sec->size;
17342
17343 /* New relocation entity. */
17344 asection *text_out = text_sec->output_section;
17345 Elf_Internal_Rela rel;
17346 rel.r_addend = 0;
17347 rel.r_offset = exidx_offset;
17348 rel.r_info = ELF32_R_INFO (text_out->target_index,
17349 R_ARM_PREL31);
17350
17351 elf32_arm_add_relocation (output_bfd, link_info,
17352 sec->output_section,
17353 &rel);
17354 }
2468f9c9
PB		 17355
17356 /* First address we can't unwind. */
17357 bfd_put_32 (output_bfd, prel31_offset,
17358 &edited_contents[out_index * 8]);
17359
17360 /* Code for EXIDX_CANTUNWIND. */
17361 bfd_put_32 (output_bfd, 0x1,
17362 &edited_contents[out_index * 8 + 4]);
17363
17364 out_index++;
17365 add_to_offsets -= 8;
17366 }
17367 break;
17368 }
b38cadfb 17369
2468f9c9
PB		 17370 edit_node = edit_node->next;
17371 }
17372 }
17373 else
17374 {
17375 /* No more edits, copy remaining entries verbatim. */
17376 copy_exidx_entry (output_bfd, edited_contents + out_index * 8,
17377 contents + in_index * 8, add_to_offsets);
17378 out_index++;
17379 in_index++;
17380 }
17381 }
17382
17383 if (!(sec->flags & SEC_EXCLUDE) && !(sec->flags & SEC_NEVER_LOAD))
17384 bfd_set_section_contents (output_bfd, sec->output_section,
17385 edited_contents,
17386 (file_ptr) sec->output_offset, sec->size);
17387
17388 return TRUE;
17389 }
17390
48229727
JB		 17391 /* Fix code to point to Cortex-A8 erratum stubs. */
17392 if (globals->fix_cortex_a8)
17393 {
17394 struct a8_branch_to_stub_data data;
17395
17396 data.writing_section = sec;
17397 data.contents = contents;
17398
a504d23a
LA		 17399 bfd_hash_traverse (& globals->stub_hash_table, make_branch_to_a8_stub,
17400 & data);
48229727
JB		 17401 }
17402
e489d0ae
PB		 17403 if (mapcount == 0)
17404 return FALSE;
17405
c7b8f16e 17406 if (globals->byteswap_code)
e489d0ae 17407 {
c7b8f16e 17408 qsort (map, mapcount, sizeof (* map), elf32_arm_compare_mapping);
57e8b36a 17409
c7b8f16e
JB		 17410 ptr = map[0].vma;
17411 for (i = 0; i < mapcount; i++)
99059e56
RM		 17412 {
17413 if (i == mapcount - 1)
c7b8f16e 17414 end = sec->size;
99059e56
RM		 17415 else
17416 end = map[i + 1].vma;
e489d0ae 17417
99059e56 17418 switch (map[i].type)
e489d0ae 17419 {
c7b8f16e
JB		 17420 case 'a':
17421 /* Byte swap code words. */
17422 while (ptr + 3 < end)
99059e56
RM		 17423 {
17424 tmp = contents[ptr];
17425 contents[ptr] = contents[ptr + 3];
17426 contents[ptr + 3] = tmp;
17427 tmp = contents[ptr + 1];
17428 contents[ptr + 1] = contents[ptr + 2];
17429 contents[ptr + 2] = tmp;
17430 ptr += 4;
17431 }
c7b8f16e 17432 break;
e489d0ae 17433
c7b8f16e
JB		 17434 case 't':
17435 /* Byte swap code halfwords. */
17436 while (ptr + 1 < end)
99059e56
RM		 17437 {
17438 tmp = contents[ptr];
17439 contents[ptr] = contents[ptr + 1];
17440 contents[ptr + 1] = tmp;
17441 ptr += 2;
17442 }
c7b8f16e
JB		 17443 break;
17444
17445 case 'd':
17446 /* Leave data alone. */
17447 break;
17448 }
99059e56
RM		 17449 ptr = end;
17450 }
e489d0ae 17451 }
8e3de13a 17452
93204d3a 17453 free (map);
47b2e99c 17454 arm_data->mapcount = -1;
c7b8f16e 17455 arm_data->mapsize = 0;
8e3de13a 17456 arm_data->map = NULL;
8e3de13a 17457
e489d0ae
PB		 17458 return FALSE;
17459}
17460
0beaef2b
PB		 17461/* Mangle thumb function symbols as we read them in. */
17462
8384fb8f 17463static bfd_boolean
0beaef2b
PB		 17464elf32_arm_swap_symbol_in (bfd * abfd,
17465 const void *psrc,
17466 const void *pshn,
17467 Elf_Internal_Sym *dst)
17468{
8384fb8f
AM		 17469 if (!bfd_elf32_swap_symbol_in (abfd, psrc, pshn, dst))
17470 return FALSE;
0beaef2b
PB		 17471
17472 /* New EABI objects mark thumb function symbols by setting the low bit of
35fc36a8 17473 the address. */
63e1a0fc
PB		 17474 if (ELF_ST_TYPE (dst->st_info) == STT_FUNC
17475 || ELF_ST_TYPE (dst->st_info) == STT_GNU_IFUNC)
0beaef2b 17476 {
63e1a0fc
PB		 17477 if (dst->st_value & 1)
17478 {
17479 dst->st_value &= ~(bfd_vma) 1;
17480 dst->st_target_internal = ST_BRANCH_TO_THUMB;
17481 }
17482 else
17483 dst->st_target_internal = ST_BRANCH_TO_ARM;
35fc36a8
RS		 17484 }
17485 else if (ELF_ST_TYPE (dst->st_info) == STT_ARM_TFUNC)
17486 {
17487 dst->st_info = ELF_ST_INFO (ELF_ST_BIND (dst->st_info), STT_FUNC);
17488 dst->st_target_internal = ST_BRANCH_TO_THUMB;
0beaef2b 17489 }
35fc36a8
RS		 17490 else if (ELF_ST_TYPE (dst->st_info) == STT_SECTION)
17491 dst->st_target_internal = ST_BRANCH_LONG;
17492 else
63e1a0fc 17493 dst->st_target_internal = ST_BRANCH_UNKNOWN;
35fc36a8 17494
8384fb8f 17495 return TRUE;
0beaef2b
PB		 17496}
17497
17498
17499/* Mangle thumb function symbols as we write them out. */
17500
17501static void
17502elf32_arm_swap_symbol_out (bfd *abfd,
17503 const Elf_Internal_Sym *src,
17504 void *cdst,
17505 void *shndx)
17506{
17507 Elf_Internal_Sym newsym;
17508
17509 /* We convert STT_ARM_TFUNC symbols into STT_FUNC with the low bit
17510 of the address set, as per the new EABI. We do this unconditionally
17511 because objcopy does not set the elf header flags until after
17512 it writes out the symbol table. */
35fc36a8 17513 if (src->st_target_internal == ST_BRANCH_TO_THUMB)
0beaef2b
PB		 17514 {
17515 newsym = *src;
34e77a92
RS		 17516 if (ELF_ST_TYPE (src->st_info) != STT_GNU_IFUNC)
17517 newsym.st_info = ELF_ST_INFO (ELF_ST_BIND (src->st_info), STT_FUNC);
0fa3dcad 17518 if (newsym.st_shndx != SHN_UNDEF)
99059e56
RM		 17519 {
17520 /* Do this only for defined symbols. At link type, the static
17521 linker will simulate the work of dynamic linker of resolving
17522 symbols and will carry over the thumbness of found symbols to
17523 the output symbol table. It's not clear how it happens, but
17524 the thumbness of undefined symbols can well be different at
17525 runtime, and writing '1' for them will be confusing for users
17526 and possibly for dynamic linker itself.
17527 */
17528 newsym.st_value |= 1;
17529 }
906e58ca 17530
0beaef2b
PB		 17531 src = &newsym;
17532 }
17533 bfd_elf32_swap_symbol_out (abfd, src, cdst, shndx);
17534}
17535
b294bdf8
MM		 17536/* Add the PT_ARM_EXIDX program header. */
17537
17538static bfd_boolean
906e58ca 17539elf32_arm_modify_segment_map (bfd *abfd,
b294bdf8
MM		 17540 struct bfd_link_info *info ATTRIBUTE_UNUSED)
17541{
17542 struct elf_segment_map *m;
17543 asection *sec;
17544
17545 sec = bfd_get_section_by_name (abfd, ".ARM.exidx");
17546 if (sec != NULL && (sec->flags & SEC_LOAD) != 0)
17547 {
17548 /* If there is already a PT_ARM_EXIDX header, then we do not
17549 want to add another one. This situation arises when running
17550 "strip"; the input binary already has the header. */
12bd6957 17551 m = elf_seg_map (abfd);
b294bdf8
MM		 17552 while (m && m->p_type != PT_ARM_EXIDX)
17553 m = m->next;
17554 if (!m)
17555 {
21d799b5 17556 m = (struct elf_segment_map *)
99059e56 17557 bfd_zalloc (abfd, sizeof (struct elf_segment_map));
b294bdf8
MM		 17558 if (m == NULL)
17559 return FALSE;
17560 m->p_type = PT_ARM_EXIDX;
17561 m->count = 1;
17562 m->sections[0] = sec;
17563
12bd6957
AM		 17564 m->next = elf_seg_map (abfd);
17565 elf_seg_map (abfd) = m;
b294bdf8
MM		 17566 }
17567 }
17568
17569 return TRUE;
17570}
17571
17572/* We may add a PT_ARM_EXIDX program header. */
17573
17574static int
a6b96beb
AM		 17575elf32_arm_additional_program_headers (bfd *abfd,
17576 struct bfd_link_info *info ATTRIBUTE_UNUSED)
b294bdf8
MM		 17577{
17578 asection *sec;
17579
17580 sec = bfd_get_section_by_name (abfd, ".ARM.exidx");
17581 if (sec != NULL && (sec->flags & SEC_LOAD) != 0)
17582 return 1;
17583 else
17584 return 0;
17585}
17586
34e77a92
RS		 17587/* Hook called by the linker routine which adds symbols from an object
17588 file. */
17589
17590static bfd_boolean
17591elf32_arm_add_symbol_hook (bfd *abfd, struct bfd_link_info *info,
17592 Elf_Internal_Sym *sym, const char **namep,
17593 flagword *flagsp, asection **secp, bfd_vma *valp)
17594{
f1885d1e
AM		 17595 if ((ELF_ST_TYPE (sym->st_info) == STT_GNU_IFUNC
17596 || ELF_ST_BIND (sym->st_info) == STB_GNU_UNIQUE)
17597 && (abfd->flags & DYNAMIC) == 0
17598 && bfd_get_flavour (info->output_bfd) == bfd_target_elf_flavour)
13a2df29 17599 elf_tdata (info->output_bfd)->has_gnu_symbols = elf_gnu_symbol_any;
34e77a92 17600
c792917c
NC		 17601 if (elf32_arm_hash_table (info) == NULL)
17602 return FALSE;
17603
34e77a92
RS		 17604 if (elf32_arm_hash_table (info)->vxworks_p
17605 && !elf_vxworks_add_symbol_hook (abfd, info, sym, namep,
17606 flagsp, secp, valp))
17607 return FALSE;
17608
17609 return TRUE;
17610}
17611
0beaef2b 17612/* We use this to override swap_symbol_in and swap_symbol_out. */
906e58ca
NC		 17613const struct elf_size_info elf32_arm_size_info =
17614{
0beaef2b
PB		 17615 sizeof (Elf32_External_Ehdr),
17616 sizeof (Elf32_External_Phdr),
17617 sizeof (Elf32_External_Shdr),
17618 sizeof (Elf32_External_Rel),
17619 sizeof (Elf32_External_Rela),
17620 sizeof (Elf32_External_Sym),
17621 sizeof (Elf32_External_Dyn),
17622 sizeof (Elf_External_Note),
17623 4,
17624 1,
17625 32, 2,
17626 ELFCLASS32, EV_CURRENT,
17627 bfd_elf32_write_out_phdrs,
17628 bfd_elf32_write_shdrs_and_ehdr,
1489a3a0 17629 bfd_elf32_checksum_contents,
0beaef2b
PB		 17630 bfd_elf32_write_relocs,
17631 elf32_arm_swap_symbol_in,
17632 elf32_arm_swap_symbol_out,
17633 bfd_elf32_slurp_reloc_table,
17634 bfd_elf32_slurp_symbol_table,
17635 bfd_elf32_swap_dyn_in,
17636 bfd_elf32_swap_dyn_out,
17637 bfd_elf32_swap_reloc_in,
17638 bfd_elf32_swap_reloc_out,
17639 bfd_elf32_swap_reloca_in,
17640 bfd_elf32_swap_reloca_out
17641};
17642
685e70ae
VK		 17643static bfd_vma
17644read_code32 (const bfd *abfd, const bfd_byte *addr)
17645{
17646 /* V7 BE8 code is always little endian. */
17647 if ((elf_elfheader (abfd)->e_flags & EF_ARM_BE8) != 0)
17648 return bfd_getl32 (addr);
17649
17650 return bfd_get_32 (abfd, addr);
17651}
17652
17653static bfd_vma
17654read_code16 (const bfd *abfd, const bfd_byte *addr)
17655{
17656 /* V7 BE8 code is always little endian. */
17657 if ((elf_elfheader (abfd)->e_flags & EF_ARM_BE8) != 0)
17658 return bfd_getl16 (addr);
17659
17660 return bfd_get_16 (abfd, addr);
17661}
17662
6a631e86
YG		 17663/* Return size of plt0 entry starting at ADDR
17664 or (bfd_vma) -1 if size can not be determined. */
17665
17666static bfd_vma
17667elf32_arm_plt0_size (const bfd *abfd, const bfd_byte *addr)
17668{
17669 bfd_vma first_word;
17670 bfd_vma plt0_size;
17671
685e70ae 17672 first_word = read_code32 (abfd, addr);
6a631e86
YG		 17673
17674 if (first_word == elf32_arm_plt0_entry[0])
17675 plt0_size = 4 * ARRAY_SIZE (elf32_arm_plt0_entry);
17676 else if (first_word == elf32_thumb2_plt0_entry[0])
17677 plt0_size = 4 * ARRAY_SIZE (elf32_thumb2_plt0_entry);
17678 else
17679 /* We don't yet handle this PLT format. */
17680 return (bfd_vma) -1;
17681
17682 return plt0_size;
17683}
17684
17685/* Return size of plt entry starting at offset OFFSET
17686 of plt section located at address START
17687 or (bfd_vma) -1 if size can not be determined. */
17688
17689static bfd_vma
17690elf32_arm_plt_size (const bfd *abfd, const bfd_byte *start, bfd_vma offset)
17691{
17692 bfd_vma first_insn;
17693 bfd_vma plt_size = 0;
17694 const bfd_byte *addr = start + offset;
17695
17696 /* PLT entry size if fixed on Thumb-only platforms. */
685e70ae 17697 if (read_code32 (abfd, start) == elf32_thumb2_plt0_entry[0])
6a631e86
YG		 17698 return 4 * ARRAY_SIZE (elf32_thumb2_plt_entry);
17699
17700 /* Respect Thumb stub if necessary. */
685e70ae 17701 if (read_code16 (abfd, addr) == elf32_arm_plt_thumb_stub[0])
6a631e86
YG		 17702 {
17703 plt_size += 2 * ARRAY_SIZE(elf32_arm_plt_thumb_stub);
17704 }
17705
17706 /* Strip immediate from first add. */
685e70ae 17707 first_insn = read_code32 (abfd, addr + plt_size) & 0xffffff00;
6a631e86
YG		 17708
17709#ifdef FOUR_WORD_PLT
17710 if (first_insn == elf32_arm_plt_entry[0])
17711 plt_size += 4 * ARRAY_SIZE (elf32_arm_plt_entry);
17712#else
17713 if (first_insn == elf32_arm_plt_entry_long[0])
17714 plt_size += 4 * ARRAY_SIZE (elf32_arm_plt_entry_long);
17715 else if (first_insn == elf32_arm_plt_entry_short[0])
17716 plt_size += 4 * ARRAY_SIZE (elf32_arm_plt_entry_short);
17717#endif
17718 else
17719 /* We don't yet handle this PLT format. */
17720 return (bfd_vma) -1;
17721
17722 return plt_size;
17723}
17724
17725/* Implementation is shamelessly borrowed from _bfd_elf_get_synthetic_symtab. */
17726
17727static long
17728elf32_arm_get_synthetic_symtab (bfd *abfd,
17729 long symcount ATTRIBUTE_UNUSED,
17730 asymbol **syms ATTRIBUTE_UNUSED,
17731 long dynsymcount,
17732 asymbol **dynsyms,
17733 asymbol **ret)
17734{
17735 asection *relplt;
17736 asymbol *s;
17737 arelent *p;
17738 long count, i, n;
17739 size_t size;
17740 Elf_Internal_Shdr *hdr;
17741 char *names;
17742 asection *plt;
17743 bfd_vma offset;
17744 bfd_byte *data;
17745
17746 *ret = NULL;
17747
17748 if ((abfd->flags & (DYNAMIC | EXEC_P)) == 0)
17749 return 0;
17750
17751 if (dynsymcount <= 0)
17752 return 0;
17753
17754 relplt = bfd_get_section_by_name (abfd, ".rel.plt");
17755 if (relplt == NULL)
17756 return 0;
17757
17758 hdr = &elf_section_data (relplt)->this_hdr;
17759 if (hdr->sh_link != elf_dynsymtab (abfd)
17760 || (hdr->sh_type != SHT_REL && hdr->sh_type != SHT_RELA))
17761 return 0;
17762
17763 plt = bfd_get_section_by_name (abfd, ".plt");
17764 if (plt == NULL)
17765 return 0;
17766
17767 if (!elf32_arm_size_info.slurp_reloc_table (abfd, relplt, dynsyms, TRUE))
17768 return -1;
17769
17770 data = plt->contents;
17771 if (data == NULL)
17772 {
17773 if (!bfd_get_full_section_contents(abfd, (asection *) plt, &data) || data == NULL)
17774 return -1;
17775 bfd_cache_section_contents((asection *) plt, data);
17776 }
17777
17778 count = relplt->size / hdr->sh_entsize;
17779 size = count * sizeof (asymbol);
17780 p = relplt->relocation;
17781 for (i = 0; i < count; i++, p += elf32_arm_size_info.int_rels_per_ext_rel)
17782 {
17783 size += strlen ((*p->sym_ptr_ptr)->name) + sizeof ("@plt");
17784 if (p->addend != 0)
17785 size += sizeof ("+0x") - 1 + 8;
17786 }
17787
17788 s = *ret = (asymbol *) bfd_malloc (size);
17789 if (s == NULL)
17790 return -1;
17791
17792 offset = elf32_arm_plt0_size (abfd, data);
17793 if (offset == (bfd_vma) -1)
17794 return -1;
17795
17796 names = (char *) (s + count);
17797 p = relplt->relocation;
17798 n = 0;
17799 for (i = 0; i < count; i++, p += elf32_arm_size_info.int_rels_per_ext_rel)
17800 {
17801 size_t len;
17802
17803 bfd_vma plt_size = elf32_arm_plt_size (abfd, data, offset);
17804 if (plt_size == (bfd_vma) -1)
17805 break;
17806
17807 *s = **p->sym_ptr_ptr;
17808 /* Undefined syms won't have BSF_LOCAL or BSF_GLOBAL set. Since
17809 we are defining a symbol, ensure one of them is set. */
17810 if ((s->flags & BSF_LOCAL) == 0)
17811 s->flags |= BSF_GLOBAL;
17812 s->flags |= BSF_SYNTHETIC;
17813 s->section = plt;
17814 s->value = offset;
17815 s->name = names;
17816 s->udata.p = NULL;
17817 len = strlen ((*p->sym_ptr_ptr)->name);
17818 memcpy (names, (*p->sym_ptr_ptr)->name, len);
17819 names += len;
17820 if (p->addend != 0)
17821 {
17822 char buf[30], *a;
17823
17824 memcpy (names, "+0x", sizeof ("+0x") - 1);
17825 names += sizeof ("+0x") - 1;
17826 bfd_sprintf_vma (abfd, buf, p->addend);
17827 for (a = buf; *a == '0'; ++a)
17828 ;
17829 len = strlen (a);
17830 memcpy (names, a, len);
17831 names += len;
17832 }
17833 memcpy (names, "@plt", sizeof ("@plt"));
17834 names += sizeof ("@plt");
17835 ++s, ++n;
17836 offset += plt_size;
17837 }
17838
17839 return n;
17840}
17841
ac4c9b04
MG		 17842static bfd_boolean
17843elf32_arm_section_flags (flagword *flags, const Elf_Internal_Shdr * hdr)
17844{
17845 if (hdr->sh_flags & SHF_ARM_NOREAD)
17846 *flags |= SEC_ELF_NOREAD;
17847 return TRUE;
17848}
17849
17850static flagword
17851elf32_arm_lookup_section_flags (char *flag_name)
17852{
17853 if (!strcmp (flag_name, "SHF_ARM_NOREAD"))
17854 return SHF_ARM_NOREAD;
17855
17856 return SEC_NO_FLAGS;
17857}
17858
491d01d3
YU		 17859static unsigned int
17860elf32_arm_count_additional_relocs (asection *sec)
17861{
17862 struct _arm_elf_section_data *arm_data;
17863 arm_data = get_arm_elf_section_data (sec);
17864 return arm_data->additional_reloc_count;
17865}
17866
252b5132 17867#define ELF_ARCH bfd_arch_arm
ae95ffa6 17868#define ELF_TARGET_ID ARM_ELF_DATA
252b5132 17869#define ELF_MACHINE_CODE EM_ARM
d0facd1b
NC		 17870#ifdef __QNXTARGET__
17871#define ELF_MAXPAGESIZE 0x1000
17872#else
7572ca89 17873#define ELF_MAXPAGESIZE 0x10000
d0facd1b 17874#endif
b1342370 17875#define ELF_MINPAGESIZE 0x1000
24718e3b 17876#define ELF_COMMONPAGESIZE 0x1000
252b5132 17877
ba93b8ac
DJ		 17878#define bfd_elf32_mkobject elf32_arm_mkobject
17879
99e4ae17
AJ		 17880#define bfd_elf32_bfd_copy_private_bfd_data elf32_arm_copy_private_bfd_data
17881#define bfd_elf32_bfd_merge_private_bfd_data elf32_arm_merge_private_bfd_data
252b5132
RH		 17882#define bfd_elf32_bfd_set_private_flags elf32_arm_set_private_flags
17883#define bfd_elf32_bfd_print_private_bfd_data elf32_arm_print_private_bfd_data
17884#define bfd_elf32_bfd_link_hash_table_create elf32_arm_link_hash_table_create
dc810e39 17885#define bfd_elf32_bfd_reloc_type_lookup elf32_arm_reloc_type_lookup
b38cadfb 17886#define bfd_elf32_bfd_reloc_name_lookup elf32_arm_reloc_name_lookup
252b5132 17887#define bfd_elf32_find_nearest_line elf32_arm_find_nearest_line
4ab527b0 17888#define bfd_elf32_find_inliner_info elf32_arm_find_inliner_info
e489d0ae 17889#define bfd_elf32_new_section_hook elf32_arm_new_section_hook
3c9458e9 17890#define bfd_elf32_bfd_is_target_special_symbol elf32_arm_is_target_special_symbol
3e6b1042 17891#define bfd_elf32_bfd_final_link elf32_arm_final_link
6a631e86 17892#define bfd_elf32_get_synthetic_symtab elf32_arm_get_synthetic_symtab
252b5132
RH		 17893
17894#define elf_backend_get_symbol_type elf32_arm_get_symbol_type
17895#define elf_backend_gc_mark_hook elf32_arm_gc_mark_hook
6a5bb875 17896#define elf_backend_gc_mark_extra_sections elf32_arm_gc_mark_extra_sections
252b5132
RH		 17897#define elf_backend_gc_sweep_hook elf32_arm_gc_sweep_hook
17898#define elf_backend_check_relocs elf32_arm_check_relocs
dc810e39 17899#define elf_backend_relocate_section elf32_arm_relocate_section
e489d0ae 17900#define elf_backend_write_section elf32_arm_write_section
252b5132 17901#define elf_backend_adjust_dynamic_symbol elf32_arm_adjust_dynamic_symbol
5e681ec4 17902#define elf_backend_create_dynamic_sections elf32_arm_create_dynamic_sections
252b5132
RH		 17903#define elf_backend_finish_dynamic_symbol elf32_arm_finish_dynamic_symbol
17904#define elf_backend_finish_dynamic_sections elf32_arm_finish_dynamic_sections
17905#define elf_backend_size_dynamic_sections elf32_arm_size_dynamic_sections
0855e32b 17906#define elf_backend_always_size_sections elf32_arm_always_size_sections
74541ad4 17907#define elf_backend_init_index_section _bfd_elf_init_2_index_sections
ba96a88f 17908#define elf_backend_post_process_headers elf32_arm_post_process_headers
99e4ae17 17909#define elf_backend_reloc_type_class elf32_arm_reloc_type_class
c178919b 17910#define elf_backend_object_p elf32_arm_object_p
40a18ebd
NC		 17911#define elf_backend_fake_sections elf32_arm_fake_sections
17912#define elf_backend_section_from_shdr elf32_arm_section_from_shdr
e16bb312 17913#define elf_backend_final_write_processing elf32_arm_final_write_processing
5e681ec4 17914#define elf_backend_copy_indirect_symbol elf32_arm_copy_indirect_symbol
0beaef2b 17915#define elf_backend_size_info elf32_arm_size_info
b294bdf8 17916#define elf_backend_modify_segment_map elf32_arm_modify_segment_map
906e58ca
NC		 17917#define elf_backend_additional_program_headers elf32_arm_additional_program_headers
17918#define elf_backend_output_arch_local_syms elf32_arm_output_arch_local_syms
17919#define elf_backend_begin_write_processing elf32_arm_begin_write_processing
34e77a92 17920#define elf_backend_add_symbol_hook elf32_arm_add_symbol_hook
491d01d3 17921#define elf_backend_count_additional_relocs elf32_arm_count_additional_relocs
906e58ca
NC		 17922
17923#define elf_backend_can_refcount 1
17924#define elf_backend_can_gc_sections 1
17925#define elf_backend_plt_readonly 1
17926#define elf_backend_want_got_plt 1
17927#define elf_backend_want_plt_sym 0
17928#define elf_backend_may_use_rel_p 1
17929#define elf_backend_may_use_rela_p 0
4e7fd91e 17930#define elf_backend_default_use_rela_p 0
252b5132 17931
04f7c78d 17932#define elf_backend_got_header_size 12
b68a20d6 17933#define elf_backend_extern_protected_data 1
04f7c78d 17934
906e58ca
NC		 17935#undef elf_backend_obj_attrs_vendor
17936#define elf_backend_obj_attrs_vendor "aeabi"
17937#undef elf_backend_obj_attrs_section
17938#define elf_backend_obj_attrs_section ".ARM.attributes"
17939#undef elf_backend_obj_attrs_arg_type
17940#define elf_backend_obj_attrs_arg_type elf32_arm_obj_attrs_arg_type
17941#undef elf_backend_obj_attrs_section_type
104d59d1 17942#define elf_backend_obj_attrs_section_type SHT_ARM_ATTRIBUTES
b38cadfb
NC		 17943#define elf_backend_obj_attrs_order elf32_arm_obj_attrs_order
17944#define elf_backend_obj_attrs_handle_unknown elf32_arm_obj_attrs_handle_unknown
104d59d1 17945
ac4c9b04
MG		 17946#undef elf_backend_section_flags
17947#define elf_backend_section_flags elf32_arm_section_flags
17948#undef elf_backend_lookup_section_flags_hook
17949#define elf_backend_lookup_section_flags_hook elf32_arm_lookup_section_flags
17950
252b5132 17951#include "elf32-target.h"
7f266840 17952
b38cadfb
NC		 17953/* Native Client targets. */
17954
17955#undef TARGET_LITTLE_SYM
6d00b590 17956#define TARGET_LITTLE_SYM arm_elf32_nacl_le_vec
b38cadfb
NC		 17957#undef TARGET_LITTLE_NAME
17958#define TARGET_LITTLE_NAME "elf32-littlearm-nacl"
17959#undef TARGET_BIG_SYM
6d00b590 17960#define TARGET_BIG_SYM arm_elf32_nacl_be_vec
b38cadfb
NC		 17961#undef TARGET_BIG_NAME
17962#define TARGET_BIG_NAME "elf32-bigarm-nacl"
17963
17964/* Like elf32_arm_link_hash_table_create -- but overrides
17965 appropriately for NaCl. */
17966
17967static struct bfd_link_hash_table *
17968elf32_arm_nacl_link_hash_table_create (bfd *abfd)
17969{
17970 struct bfd_link_hash_table *ret;
17971
17972 ret = elf32_arm_link_hash_table_create (abfd);
17973 if (ret)
17974 {
17975 struct elf32_arm_link_hash_table *htab
17976 = (struct elf32_arm_link_hash_table *) ret;
17977
17978 htab->nacl_p = 1;
17979
17980 htab->plt_header_size = 4 * ARRAY_SIZE (elf32_arm_nacl_plt0_entry);
17981 htab->plt_entry_size = 4 * ARRAY_SIZE (elf32_arm_nacl_plt_entry);
17982 }
17983 return ret;
17984}
17985
17986/* Since NaCl doesn't use the ARM-specific unwind format, we don't
17987 really need to use elf32_arm_modify_segment_map. But we do it
17988 anyway just to reduce gratuitous differences with the stock ARM backend. */
17989
17990static bfd_boolean
17991elf32_arm_nacl_modify_segment_map (bfd *abfd, struct bfd_link_info *info)
17992{
17993 return (elf32_arm_modify_segment_map (abfd, info)
17994 && nacl_modify_segment_map (abfd, info));
17995}
17996
887badb3
RM		 17997static void
17998elf32_arm_nacl_final_write_processing (bfd *abfd, bfd_boolean linker)
17999{
18000 elf32_arm_final_write_processing (abfd, linker);
18001 nacl_final_write_processing (abfd, linker);
18002}
18003
6a631e86
YG		 18004static bfd_vma
18005elf32_arm_nacl_plt_sym_val (bfd_vma i, const asection *plt,
18006 const arelent *rel ATTRIBUTE_UNUSED)
18007{
18008 return plt->vma
18009 + 4 * (ARRAY_SIZE (elf32_arm_nacl_plt0_entry) +
18010 i * ARRAY_SIZE (elf32_arm_nacl_plt_entry));
18011}
887badb3 18012
b38cadfb 18013#undef elf32_bed
6a631e86 18014#define elf32_bed elf32_arm_nacl_bed
b38cadfb
NC		 18015#undef bfd_elf32_bfd_link_hash_table_create
18016#define bfd_elf32_bfd_link_hash_table_create \
18017 elf32_arm_nacl_link_hash_table_create
18018#undef elf_backend_plt_alignment
6a631e86 18019#define elf_backend_plt_alignment 4
b38cadfb
NC		 18020#undef elf_backend_modify_segment_map
18021#define elf_backend_modify_segment_map elf32_arm_nacl_modify_segment_map
18022#undef elf_backend_modify_program_headers
18023#define elf_backend_modify_program_headers nacl_modify_program_headers
887badb3
RM		 18024#undef elf_backend_final_write_processing
18025#define elf_backend_final_write_processing elf32_arm_nacl_final_write_processing
6a631e86
YG		 18026#undef bfd_elf32_get_synthetic_symtab
18027#undef elf_backend_plt_sym_val
18028#define elf_backend_plt_sym_val elf32_arm_nacl_plt_sym_val
b38cadfb 18029
887badb3
RM		 18030#undef ELF_MINPAGESIZE
18031#undef ELF_COMMONPAGESIZE
18032
b38cadfb
NC		 18033
18034#include "elf32-target.h"
18035
18036/* Reset to defaults. */
18037#undef elf_backend_plt_alignment
18038#undef elf_backend_modify_segment_map
18039#define elf_backend_modify_segment_map elf32_arm_modify_segment_map
18040#undef elf_backend_modify_program_headers
887badb3
RM		 18041#undef elf_backend_final_write_processing
18042#define elf_backend_final_write_processing elf32_arm_final_write_processing
18043#undef ELF_MINPAGESIZE
18044#define ELF_MINPAGESIZE 0x1000
18045#undef ELF_COMMONPAGESIZE
18046#define ELF_COMMONPAGESIZE 0x1000
18047
b38cadfb 18048
906e58ca 18049/* VxWorks Targets. */
4e7fd91e 18050
906e58ca 18051#undef TARGET_LITTLE_SYM
6d00b590 18052#define TARGET_LITTLE_SYM arm_elf32_vxworks_le_vec
906e58ca 18053#undef TARGET_LITTLE_NAME
4e7fd91e 18054#define TARGET_LITTLE_NAME "elf32-littlearm-vxworks"
906e58ca 18055#undef TARGET_BIG_SYM
6d00b590 18056#define TARGET_BIG_SYM arm_elf32_vxworks_be_vec
906e58ca 18057#undef TARGET_BIG_NAME
4e7fd91e
PB		 18058#define TARGET_BIG_NAME "elf32-bigarm-vxworks"
18059
18060/* Like elf32_arm_link_hash_table_create -- but overrides
18061 appropriately for VxWorks. */
906e58ca 18062
4e7fd91e
PB		 18063static struct bfd_link_hash_table *
18064elf32_arm_vxworks_link_hash_table_create (bfd *abfd)
18065{
18066 struct bfd_link_hash_table *ret;
18067
18068 ret = elf32_arm_link_hash_table_create (abfd);
18069 if (ret)
18070 {
18071 struct elf32_arm_link_hash_table *htab
00a97672 18072 = (struct elf32_arm_link_hash_table *) ret;
4e7fd91e 18073 htab->use_rel = 0;
00a97672 18074 htab->vxworks_p = 1;
4e7fd91e
PB		 18075 }
18076 return ret;
906e58ca 18077}
4e7fd91e 18078
00a97672
RS		 18079static void
18080elf32_arm_vxworks_final_write_processing (bfd *abfd, bfd_boolean linker)
18081{
18082 elf32_arm_final_write_processing (abfd, linker);
18083 elf_vxworks_final_write_processing (abfd, linker);
18084}
18085
906e58ca 18086#undef elf32_bed
4e7fd91e
PB		 18087#define elf32_bed elf32_arm_vxworks_bed
18088
906e58ca
NC		 18089#undef bfd_elf32_bfd_link_hash_table_create
18090#define bfd_elf32_bfd_link_hash_table_create elf32_arm_vxworks_link_hash_table_create
906e58ca
NC		 18091#undef elf_backend_final_write_processing
18092#define elf_backend_final_write_processing elf32_arm_vxworks_final_write_processing
18093#undef elf_backend_emit_relocs
18094#define elf_backend_emit_relocs elf_vxworks_emit_relocs
4e7fd91e 18095
906e58ca 18096#undef elf_backend_may_use_rel_p
00a97672 18097#define elf_backend_may_use_rel_p 0
906e58ca 18098#undef elf_backend_may_use_rela_p
00a97672 18099#define elf_backend_may_use_rela_p 1
906e58ca 18100#undef elf_backend_default_use_rela_p
00a97672 18101#define elf_backend_default_use_rela_p 1
906e58ca 18102#undef elf_backend_want_plt_sym
00a97672 18103#define elf_backend_want_plt_sym 1
906e58ca 18104#undef ELF_MAXPAGESIZE
00a97672 18105#define ELF_MAXPAGESIZE 0x1000
4e7fd91e
PB		 18106
18107#include "elf32-target.h"
18108
18109
21d799b5
NC		 18110/* Merge backend specific data from an object file to the output
18111 object file when linking. */
18112
18113static bfd_boolean
18114elf32_arm_merge_private_bfd_data (bfd * ibfd, bfd * obfd)
18115{
18116 flagword out_flags;
18117 flagword in_flags;
18118 bfd_boolean flags_compatible = TRUE;
18119 asection *sec;
18120
cc643b88 18121 /* Check if we have the same endianness. */
21d799b5
NC		 18122 if (! _bfd_generic_verify_endian_match (ibfd, obfd))
18123 return FALSE;
18124
18125 if (! is_arm_elf (ibfd) || ! is_arm_elf (obfd))
18126 return TRUE;
18127
18128 if (!elf32_arm_merge_eabi_attributes (ibfd, obfd))
18129 return FALSE;
18130
18131 /* The input BFD must have had its flags initialised. */
18132 /* The following seems bogus to me -- The flags are initialized in
18133 the assembler but I don't think an elf_flags_init field is
18134 written into the object. */
18135 /* BFD_ASSERT (elf_flags_init (ibfd)); */
18136
18137 in_flags = elf_elfheader (ibfd)->e_flags;
18138 out_flags = elf_elfheader (obfd)->e_flags;
18139
18140 /* In theory there is no reason why we couldn't handle this. However
18141 in practice it isn't even close to working and there is no real
18142 reason to want it. */
18143 if (EF_ARM_EABI_VERSION (in_flags) >= EF_ARM_EABI_VER4
18144 && !(ibfd->flags & DYNAMIC)
18145 && (in_flags & EF_ARM_BE8))
18146 {
18147 _bfd_error_handler (_("error: %B is already in final BE8 format"),
18148 ibfd);
18149 return FALSE;
18150 }
18151
18152 if (!elf_flags_init (obfd))
18153 {
18154 /* If the input is the default architecture and had the default
18155 flags then do not bother setting the flags for the output
18156 architecture, instead allow future merges to do this. If no
18157 future merges ever set these flags then they will retain their
99059e56
RM		 18158 uninitialised values, which surprise surprise, correspond
18159 to the default values. */
21d799b5
NC		 18160 if (bfd_get_arch_info (ibfd)->the_default
18161 && elf_elfheader (ibfd)->e_flags == 0)
18162 return TRUE;
18163
18164 elf_flags_init (obfd) = TRUE;
18165 elf_elfheader (obfd)->e_flags = in_flags;
18166
18167 if (bfd_get_arch (obfd) == bfd_get_arch (ibfd)
18168 && bfd_get_arch_info (obfd)->the_default)
18169 return bfd_set_arch_mach (obfd, bfd_get_arch (ibfd), bfd_get_mach (ibfd));
18170
18171 return TRUE;
18172 }
18173
18174 /* Determine what should happen if the input ARM architecture
18175 does not match the output ARM architecture. */
18176 if (! bfd_arm_merge_machines (ibfd, obfd))
18177 return FALSE;
18178
18179 /* Identical flags must be compatible. */
18180 if (in_flags == out_flags)
18181 return TRUE;
18182
18183 /* Check to see if the input BFD actually contains any sections. If
18184 not, its flags may not have been initialised either, but it
18185 cannot actually cause any incompatiblity. Do not short-circuit
18186 dynamic objects; their section list may be emptied by
18187 elf_link_add_object_symbols.
18188
18189 Also check to see if there are no code sections in the input.
18190 In this case there is no need to check for code specific flags.
18191 XXX - do we need to worry about floating-point format compatability
18192 in data sections ? */
18193 if (!(ibfd->flags & DYNAMIC))
18194 {
18195 bfd_boolean null_input_bfd = TRUE;
18196 bfd_boolean only_data_sections = TRUE;
18197
18198 for (sec = ibfd->sections; sec != NULL; sec = sec->next)
18199 {
18200 /* Ignore synthetic glue sections. */
18201 if (strcmp (sec->name, ".glue_7")
18202 && strcmp (sec->name, ".glue_7t"))
18203 {
18204 if ((bfd_get_section_flags (ibfd, sec)
18205 & (SEC_LOAD | SEC_CODE | SEC_HAS_CONTENTS))
18206 == (SEC_LOAD | SEC_CODE | SEC_HAS_CONTENTS))
99059e56 18207 only_data_sections = FALSE;
21d799b5
NC		 18208
18209 null_input_bfd = FALSE;
18210 break;
18211 }
18212 }
18213
18214 if (null_input_bfd || only_data_sections)
18215 return TRUE;
18216 }
18217
18218 /* Complain about various flag mismatches. */
18219 if (!elf32_arm_versions_compatible (EF_ARM_EABI_VERSION (in_flags),
18220 EF_ARM_EABI_VERSION (out_flags)))
18221 {
18222 _bfd_error_handler
18223 (_("error: Source object %B has EABI version %d, but target %B has EABI version %d"),
18224 ibfd, obfd,
18225 (in_flags & EF_ARM_EABIMASK) >> 24,
18226 (out_flags & EF_ARM_EABIMASK) >> 24);
18227 return FALSE;
18228 }
18229
18230 /* Not sure what needs to be checked for EABI versions >= 1. */
18231 /* VxWorks libraries do not use these flags. */
18232 if (get_elf_backend_data (obfd) != &elf32_arm_vxworks_bed
18233 && get_elf_backend_data (ibfd) != &elf32_arm_vxworks_bed
18234 && EF_ARM_EABI_VERSION (in_flags) == EF_ARM_EABI_UNKNOWN)
18235 {
18236 if ((in_flags & EF_ARM_APCS_26) != (out_flags & EF_ARM_APCS_26))
18237 {
18238 _bfd_error_handler
18239 (_("error: %B is compiled for APCS-%d, whereas target %B uses APCS-%d"),
18240 ibfd, obfd,
18241 in_flags & EF_ARM_APCS_26 ? 26 : 32,
18242 out_flags & EF_ARM_APCS_26 ? 26 : 32);
18243 flags_compatible = FALSE;
18244 }
18245
18246 if ((in_flags & EF_ARM_APCS_FLOAT) != (out_flags & EF_ARM_APCS_FLOAT))
18247 {
18248 if (in_flags & EF_ARM_APCS_FLOAT)
18249 _bfd_error_handler
18250 (_("error: %B passes floats in float registers, whereas %B passes them in integer registers"),
18251 ibfd, obfd);
18252 else
18253 _bfd_error_handler
18254 (_("error: %B passes floats in integer registers, whereas %B passes them in float registers"),
18255 ibfd, obfd);
18256
18257 flags_compatible = FALSE;
18258 }
18259
18260 if ((in_flags & EF_ARM_VFP_FLOAT) != (out_flags & EF_ARM_VFP_FLOAT))
18261 {
18262 if (in_flags & EF_ARM_VFP_FLOAT)
18263 _bfd_error_handler
18264 (_("error: %B uses VFP instructions, whereas %B does not"),
18265 ibfd, obfd);
18266 else
18267 _bfd_error_handler
18268 (_("error: %B uses FPA instructions, whereas %B does not"),
18269 ibfd, obfd);
18270
18271 flags_compatible = FALSE;
18272 }
18273
18274 if ((in_flags & EF_ARM_MAVERICK_FLOAT) != (out_flags & EF_ARM_MAVERICK_FLOAT))
18275 {
18276 if (in_flags & EF_ARM_MAVERICK_FLOAT)
18277 _bfd_error_handler
18278 (_("error: %B uses Maverick instructions, whereas %B does not"),
18279 ibfd, obfd);
18280 else
18281 _bfd_error_handler
18282 (_("error: %B does not use Maverick instructions, whereas %B does"),
18283 ibfd, obfd);
18284
18285 flags_compatible = FALSE;
18286 }
18287
18288#ifdef EF_ARM_SOFT_FLOAT
18289 if ((in_flags & EF_ARM_SOFT_FLOAT) != (out_flags & EF_ARM_SOFT_FLOAT))
18290 {
18291 /* We can allow interworking between code that is VFP format
18292 layout, and uses either soft float or integer regs for
18293 passing floating point arguments and results. We already
18294 know that the APCS_FLOAT flags match; similarly for VFP
18295 flags. */
18296 if ((in_flags & EF_ARM_APCS_FLOAT) != 0
18297 || (in_flags & EF_ARM_VFP_FLOAT) == 0)
18298 {
18299 if (in_flags & EF_ARM_SOFT_FLOAT)
18300 _bfd_error_handler
18301 (_("error: %B uses software FP, whereas %B uses hardware FP"),
18302 ibfd, obfd);
18303 else
18304 _bfd_error_handler
18305 (_("error: %B uses hardware FP, whereas %B uses software FP"),
18306 ibfd, obfd);
18307
18308 flags_compatible = FALSE;
18309 }
18310 }
18311#endif
18312
18313 /* Interworking mismatch is only a warning. */
18314 if ((in_flags & EF_ARM_INTERWORK) != (out_flags & EF_ARM_INTERWORK))
18315 {
18316 if (in_flags & EF_ARM_INTERWORK)
18317 {
18318 _bfd_error_handler
18319 (_("Warning: %B supports interworking, whereas %B does not"),
18320 ibfd, obfd);
18321 }
18322 else
18323 {
18324 _bfd_error_handler
18325 (_("Warning: %B does not support interworking, whereas %B does"),
18326 ibfd, obfd);
18327 }
18328 }
18329 }
18330
18331 return flags_compatible;
18332}
18333
18334
906e58ca 18335/* Symbian OS Targets. */
7f266840 18336
906e58ca 18337#undef TARGET_LITTLE_SYM
6d00b590 18338#define TARGET_LITTLE_SYM arm_elf32_symbian_le_vec
906e58ca 18339#undef TARGET_LITTLE_NAME
7f266840 18340#define TARGET_LITTLE_NAME "elf32-littlearm-symbian"
906e58ca 18341#undef TARGET_BIG_SYM
6d00b590 18342#define TARGET_BIG_SYM arm_elf32_symbian_be_vec
906e58ca 18343#undef TARGET_BIG_NAME
7f266840
DJ		 18344#define TARGET_BIG_NAME "elf32-bigarm-symbian"
18345
18346/* Like elf32_arm_link_hash_table_create -- but overrides
18347 appropriately for Symbian OS. */
906e58ca 18348
7f266840
DJ		 18349static struct bfd_link_hash_table *
18350elf32_arm_symbian_link_hash_table_create (bfd *abfd)
18351{
18352 struct bfd_link_hash_table *ret;
18353
18354 ret = elf32_arm_link_hash_table_create (abfd);
18355 if (ret)
18356 {
18357 struct elf32_arm_link_hash_table *htab
18358 = (struct elf32_arm_link_hash_table *)ret;
18359 /* There is no PLT header for Symbian OS. */
18360 htab->plt_header_size = 0;
95720a86
DJ		 18361 /* The PLT entries are each one instruction and one word. */
18362 htab->plt_entry_size = 4 * ARRAY_SIZE (elf32_arm_symbian_plt_entry);
7f266840 18363 htab->symbian_p = 1;
33bfe774
JB		 18364 /* Symbian uses armv5t or above, so use_blx is always true. */
18365 htab->use_blx = 1;
67687978 18366 htab->root.is_relocatable_executable = 1;
7f266840
DJ		 18367 }
18368 return ret;
906e58ca 18369}
7f266840 18370
b35d266b 18371static const struct bfd_elf_special_section
551b43fd 18372elf32_arm_symbian_special_sections[] =
7f266840 18373{
5cd3778d
MM		 18374 /* In a BPABI executable, the dynamic linking sections do not go in
18375 the loadable read-only segment. The post-linker may wish to
18376 refer to these sections, but they are not part of the final
18377 program image. */
0112cd26
NC		 18378 { STRING_COMMA_LEN (".dynamic"), 0, SHT_DYNAMIC, 0 },
18379 { STRING_COMMA_LEN (".dynstr"), 0, SHT_STRTAB, 0 },
18380 { STRING_COMMA_LEN (".dynsym"), 0, SHT_DYNSYM, 0 },
18381 { STRING_COMMA_LEN (".got"), 0, SHT_PROGBITS, 0 },
18382 { STRING_COMMA_LEN (".hash"), 0, SHT_HASH, 0 },
5cd3778d
MM		 18383 /* These sections do not need to be writable as the SymbianOS
18384 postlinker will arrange things so that no dynamic relocation is
18385 required. */
0112cd26
NC		 18386 { STRING_COMMA_LEN (".init_array"), 0, SHT_INIT_ARRAY, SHF_ALLOC },
18387 { STRING_COMMA_LEN (".fini_array"), 0, SHT_FINI_ARRAY, SHF_ALLOC },
18388 { STRING_COMMA_LEN (".preinit_array"), 0, SHT_PREINIT_ARRAY, SHF_ALLOC },
18389 { NULL, 0, 0, 0, 0 }
7f266840
DJ		 18390};
18391
c3c76620 18392static void
906e58ca 18393elf32_arm_symbian_begin_write_processing (bfd *abfd,
a4fd1a8e 18394 struct bfd_link_info *link_info)
c3c76620
MM		 18395{
18396 /* BPABI objects are never loaded directly by an OS kernel; they are
18397 processed by a postlinker first, into an OS-specific format. If
18398 the D_PAGED bit is set on the file, BFD will align segments on
18399 page boundaries, so that an OS can directly map the file. With
18400 BPABI objects, that just results in wasted space. In addition,
18401 because we clear the D_PAGED bit, map_sections_to_segments will
18402 recognize that the program headers should not be mapped into any
18403 loadable segment. */
18404 abfd->flags &= ~D_PAGED;
906e58ca 18405 elf32_arm_begin_write_processing (abfd, link_info);
c3c76620 18406}
7f266840
DJ		 18407
18408static bfd_boolean
906e58ca 18409elf32_arm_symbian_modify_segment_map (bfd *abfd,
b294bdf8 18410 struct bfd_link_info *info)
7f266840
DJ		 18411{
18412 struct elf_segment_map *m;
18413 asection *dynsec;
18414
7f266840
DJ		 18415 /* BPABI shared libraries and executables should have a PT_DYNAMIC
18416 segment. However, because the .dynamic section is not marked
18417 with SEC_LOAD, the generic ELF code will not create such a
18418 segment. */
18419 dynsec = bfd_get_section_by_name (abfd, ".dynamic");
18420 if (dynsec)
18421 {
12bd6957 18422 for (m = elf_seg_map (abfd); m != NULL; m = m->next)
8ded5a0f
AM		 18423 if (m->p_type == PT_DYNAMIC)
18424 break;
18425
18426 if (m == NULL)
18427 {
18428 m = _bfd_elf_make_dynamic_segment (abfd, dynsec);
12bd6957
AM		 18429 m->next = elf_seg_map (abfd);
18430 elf_seg_map (abfd) = m;
8ded5a0f 18431 }
7f266840
DJ		 18432 }
18433
b294bdf8
MM		 18434 /* Also call the generic arm routine. */
18435 return elf32_arm_modify_segment_map (abfd, info);
7f266840
DJ		 18436}
18437
95720a86
DJ		 18438/* Return address for Ith PLT stub in section PLT, for relocation REL
18439 or (bfd_vma) -1 if it should not be included. */
18440
18441static bfd_vma
18442elf32_arm_symbian_plt_sym_val (bfd_vma i, const asection *plt,
18443 const arelent *rel ATTRIBUTE_UNUSED)
18444{
18445 return plt->vma + 4 * ARRAY_SIZE (elf32_arm_symbian_plt_entry) * i;
18446}
18447
18448
8029a119 18449#undef elf32_bed
7f266840
DJ		 18450#define elf32_bed elf32_arm_symbian_bed
18451
18452/* The dynamic sections are not allocated on SymbianOS; the postlinker
18453 will process them and then discard them. */
906e58ca 18454#undef ELF_DYNAMIC_SEC_FLAGS
7f266840
DJ		 18455#define ELF_DYNAMIC_SEC_FLAGS \
18456 (SEC_HAS_CONTENTS | SEC_IN_MEMORY | SEC_LINKER_CREATED)
18457
00a97672 18458#undef elf_backend_emit_relocs
c3c76620 18459
906e58ca
NC		 18460#undef bfd_elf32_bfd_link_hash_table_create
18461#define bfd_elf32_bfd_link_hash_table_create elf32_arm_symbian_link_hash_table_create
18462#undef elf_backend_special_sections
18463#define elf_backend_special_sections elf32_arm_symbian_special_sections
18464#undef elf_backend_begin_write_processing
18465#define elf_backend_begin_write_processing elf32_arm_symbian_begin_write_processing
18466#undef elf_backend_final_write_processing
18467#define elf_backend_final_write_processing elf32_arm_final_write_processing
18468
18469#undef elf_backend_modify_segment_map
7f266840
DJ		 18470#define elf_backend_modify_segment_map elf32_arm_symbian_modify_segment_map
18471
18472/* There is no .got section for BPABI objects, and hence no header. */
906e58ca 18473#undef elf_backend_got_header_size
7f266840
DJ		 18474#define elf_backend_got_header_size 0
18475
18476/* Similarly, there is no .got.plt section. */
906e58ca 18477#undef elf_backend_want_got_plt
7f266840
DJ		 18478#define elf_backend_want_got_plt 0
18479
906e58ca 18480#undef elf_backend_plt_sym_val
95720a86
DJ		 18481#define elf_backend_plt_sym_val elf32_arm_symbian_plt_sym_val
18482
906e58ca 18483#undef elf_backend_may_use_rel_p
00a97672 18484#define elf_backend_may_use_rel_p 1
906e58ca 18485#undef elf_backend_may_use_rela_p
00a97672 18486#define elf_backend_may_use_rela_p 0
906e58ca 18487#undef elf_backend_default_use_rela_p
00a97672 18488#define elf_backend_default_use_rela_p 0
906e58ca 18489#undef elf_backend_want_plt_sym
00a97672 18490#define elf_backend_want_plt_sym 0
906e58ca 18491#undef ELF_MAXPAGESIZE
00a97672 18492#define ELF_MAXPAGESIZE 0x8000
4e7fd91e 18493
7f266840 18494#include "elf32-target.h"
GDB Binutils - Deliverables
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