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Remove syntactic sugar
[deliverable/binutils-gdb.git] / bfd / elf32-arm.c
CommitLineData
252b5132 1/* 32-bit ELF support for ARM
6f2750fe 2 Copyright (C) 1998-2016 Free Software Foundation, Inc.
252b5132
RH		 3
4 This file is part of BFD, the Binary File Descriptor library.
5
6 This program is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
cd123cb7 8 the Free Software Foundation; either version 3 of the License, or
252b5132
RH		 9 (at your option) any later version.
10
11 This program is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
15
16 You should have received a copy of the GNU General Public License
17 along with this program; if not, write to the Free Software
cd123cb7
NC		 18 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
19 MA 02110-1301, USA. */
252b5132 20
6e6718a3 21#include "sysdep.h"
2468f9c9
PB		 22#include <limits.h>
23
3db64b00 24#include "bfd.h"
6034aab8 25#include "bfd_stdint.h"
00a97672 26#include "libiberty.h"
7f266840
DJ		 27#include "libbfd.h"
28#include "elf-bfd.h"
b38cadfb 29#include "elf-nacl.h"
00a97672 30#include "elf-vxworks.h"
ee065d83 31#include "elf/arm.h"
7f266840 32
00a97672
RS		 33/* Return the relocation section associated with NAME. HTAB is the
34 bfd's elf32_arm_link_hash_entry. */
35#define RELOC_SECTION(HTAB, NAME) \
36 ((HTAB)->use_rel ? ".rel" NAME : ".rela" NAME)
37
38/* Return size of a relocation entry. HTAB is the bfd's
39 elf32_arm_link_hash_entry. */
40#define RELOC_SIZE(HTAB) \
41 ((HTAB)->use_rel \
42 ? sizeof (Elf32_External_Rel) \
43 : sizeof (Elf32_External_Rela))
44
45/* Return function to swap relocations in. HTAB is the bfd's
46 elf32_arm_link_hash_entry. */
47#define SWAP_RELOC_IN(HTAB) \
48 ((HTAB)->use_rel \
49 ? bfd_elf32_swap_reloc_in \
50 : bfd_elf32_swap_reloca_in)
51
52/* Return function to swap relocations out. HTAB is the bfd's
53 elf32_arm_link_hash_entry. */
54#define SWAP_RELOC_OUT(HTAB) \
55 ((HTAB)->use_rel \
56 ? bfd_elf32_swap_reloc_out \
57 : bfd_elf32_swap_reloca_out)
58
7f266840
DJ		 59#define elf_info_to_howto 0
60#define elf_info_to_howto_rel elf32_arm_info_to_howto
61
62#define ARM_ELF_ABI_VERSION 0
63#define ARM_ELF_OS_ABI_VERSION ELFOSABI_ARM
64
79f08007
YZ		 65/* The Adjusted Place, as defined by AAELF. */
66#define Pa(X) ((X) & 0xfffffffc)
67
3e6b1042
DJ		 68static bfd_boolean elf32_arm_write_section (bfd *output_bfd,
69 struct bfd_link_info *link_info,
70 asection *sec,
71 bfd_byte *contents);
72
7f266840
DJ		 73/* Note: code such as elf32_arm_reloc_type_lookup expect to use e.g.
74 R_ARM_PC24 as an index into this, and find the R_ARM_PC24 HOWTO
75 in that slot. */
76
c19d1205 77static reloc_howto_type elf32_arm_howto_table_1[] =
7f266840 78{
8029a119 79 /* No relocation. */
7f266840
DJ		 80 HOWTO (R_ARM_NONE, /* type */
81 0, /* rightshift */
6346d5ca 82 3, /* size (0 = byte, 1 = short, 2 = long) */
7f266840
DJ		 83 0, /* bitsize */
84 FALSE, /* pc_relative */
85 0, /* bitpos */
86 complain_overflow_dont,/* complain_on_overflow */
87 bfd_elf_generic_reloc, /* special_function */
88 "R_ARM_NONE", /* name */
89 FALSE, /* partial_inplace */
90 0, /* src_mask */
91 0, /* dst_mask */
92 FALSE), /* pcrel_offset */
93
94 HOWTO (R_ARM_PC24, /* type */
95 2, /* rightshift */
96 2, /* size (0 = byte, 1 = short, 2 = long) */
97 24, /* bitsize */
98 TRUE, /* pc_relative */
99 0, /* bitpos */
100 complain_overflow_signed,/* complain_on_overflow */
101 bfd_elf_generic_reloc, /* special_function */
102 "R_ARM_PC24", /* name */
103 FALSE, /* partial_inplace */
104 0x00ffffff, /* src_mask */
105 0x00ffffff, /* dst_mask */
106 TRUE), /* pcrel_offset */
107
108 /* 32 bit absolute */
109 HOWTO (R_ARM_ABS32, /* type */
110 0, /* rightshift */
111 2, /* size (0 = byte, 1 = short, 2 = long) */
112 32, /* bitsize */
113 FALSE, /* pc_relative */
114 0, /* bitpos */
115 complain_overflow_bitfield,/* complain_on_overflow */
116 bfd_elf_generic_reloc, /* special_function */
117 "R_ARM_ABS32", /* name */
118 FALSE, /* partial_inplace */
119 0xffffffff, /* src_mask */
120 0xffffffff, /* dst_mask */
121 FALSE), /* pcrel_offset */
122
123 /* standard 32bit pc-relative reloc */
124 HOWTO (R_ARM_REL32, /* type */
125 0, /* rightshift */
126 2, /* size (0 = byte, 1 = short, 2 = long) */
127 32, /* bitsize */
128 TRUE, /* pc_relative */
129 0, /* bitpos */
130 complain_overflow_bitfield,/* complain_on_overflow */
131 bfd_elf_generic_reloc, /* special_function */
132 "R_ARM_REL32", /* name */
133 FALSE, /* partial_inplace */
134 0xffffffff, /* src_mask */
135 0xffffffff, /* dst_mask */
136 TRUE), /* pcrel_offset */
137
c19d1205 138 /* 8 bit absolute - R_ARM_LDR_PC_G0 in AAELF */
4962c51a 139 HOWTO (R_ARM_LDR_PC_G0, /* type */
7f266840
DJ		 140 0, /* rightshift */
141 0, /* size (0 = byte, 1 = short, 2 = long) */
4962c51a
MS		 142 32, /* bitsize */
143 TRUE, /* pc_relative */
7f266840 144 0, /* bitpos */
4962c51a 145 complain_overflow_dont,/* complain_on_overflow */
7f266840 146 bfd_elf_generic_reloc, /* special_function */
4962c51a 147 "R_ARM_LDR_PC_G0", /* name */
7f266840 148 FALSE, /* partial_inplace */
4962c51a
MS		 149 0xffffffff, /* src_mask */
150 0xffffffff, /* dst_mask */
151 TRUE), /* pcrel_offset */
7f266840
DJ		 152
153 /* 16 bit absolute */
154 HOWTO (R_ARM_ABS16, /* type */
155 0, /* rightshift */
156 1, /* size (0 = byte, 1 = short, 2 = long) */
157 16, /* bitsize */
158 FALSE, /* pc_relative */
159 0, /* bitpos */
160 complain_overflow_bitfield,/* complain_on_overflow */
161 bfd_elf_generic_reloc, /* special_function */
162 "R_ARM_ABS16", /* name */
163 FALSE, /* partial_inplace */
164 0x0000ffff, /* src_mask */
165 0x0000ffff, /* dst_mask */
166 FALSE), /* pcrel_offset */
167
168 /* 12 bit absolute */
169 HOWTO (R_ARM_ABS12, /* type */
170 0, /* rightshift */
171 2, /* size (0 = byte, 1 = short, 2 = long) */
172 12, /* bitsize */
173 FALSE, /* pc_relative */
174 0, /* bitpos */
175 complain_overflow_bitfield,/* complain_on_overflow */
176 bfd_elf_generic_reloc, /* special_function */
177 "R_ARM_ABS12", /* name */
178 FALSE, /* partial_inplace */
00a97672
RS		 179 0x00000fff, /* src_mask */
180 0x00000fff, /* dst_mask */
7f266840
DJ		 181 FALSE), /* pcrel_offset */
182
183 HOWTO (R_ARM_THM_ABS5, /* type */
184 6, /* rightshift */
185 1, /* size (0 = byte, 1 = short, 2 = long) */
186 5, /* bitsize */
187 FALSE, /* pc_relative */
188 0, /* bitpos */
189 complain_overflow_bitfield,/* complain_on_overflow */
190 bfd_elf_generic_reloc, /* special_function */
191 "R_ARM_THM_ABS5", /* name */
192 FALSE, /* partial_inplace */
193 0x000007e0, /* src_mask */
194 0x000007e0, /* dst_mask */
195 FALSE), /* pcrel_offset */
196
197 /* 8 bit absolute */
198 HOWTO (R_ARM_ABS8, /* type */
199 0, /* rightshift */
200 0, /* size (0 = byte, 1 = short, 2 = long) */
201 8, /* bitsize */
202 FALSE, /* pc_relative */
203 0, /* bitpos */
204 complain_overflow_bitfield,/* complain_on_overflow */
205 bfd_elf_generic_reloc, /* special_function */
206 "R_ARM_ABS8", /* name */
207 FALSE, /* partial_inplace */
208 0x000000ff, /* src_mask */
209 0x000000ff, /* dst_mask */
210 FALSE), /* pcrel_offset */
211
212 HOWTO (R_ARM_SBREL32, /* type */
213 0, /* rightshift */
214 2, /* size (0 = byte, 1 = short, 2 = long) */
215 32, /* bitsize */
216 FALSE, /* pc_relative */
217 0, /* bitpos */
218 complain_overflow_dont,/* complain_on_overflow */
219 bfd_elf_generic_reloc, /* special_function */
220 "R_ARM_SBREL32", /* name */
221 FALSE, /* partial_inplace */
222 0xffffffff, /* src_mask */
223 0xffffffff, /* dst_mask */
224 FALSE), /* pcrel_offset */
225
c19d1205 226 HOWTO (R_ARM_THM_CALL, /* type */
7f266840
DJ		 227 1, /* rightshift */
228 2, /* size (0 = byte, 1 = short, 2 = long) */
f6ebfac0 229 24, /* bitsize */
7f266840
DJ		 230 TRUE, /* pc_relative */
231 0, /* bitpos */
232 complain_overflow_signed,/* complain_on_overflow */
233 bfd_elf_generic_reloc, /* special_function */
c19d1205 234 "R_ARM_THM_CALL", /* name */
7f266840 235 FALSE, /* partial_inplace */
7f6ab9f8
AM		 236 0x07ff2fff, /* src_mask */
237 0x07ff2fff, /* dst_mask */
7f266840
DJ		 238 TRUE), /* pcrel_offset */
239
240 HOWTO (R_ARM_THM_PC8, /* type */
241 1, /* rightshift */
242 1, /* size (0 = byte, 1 = short, 2 = long) */
243 8, /* bitsize */
244 TRUE, /* pc_relative */
245 0, /* bitpos */
246 complain_overflow_signed,/* complain_on_overflow */
247 bfd_elf_generic_reloc, /* special_function */
248 "R_ARM_THM_PC8", /* name */
249 FALSE, /* partial_inplace */
250 0x000000ff, /* src_mask */
251 0x000000ff, /* dst_mask */
252 TRUE), /* pcrel_offset */
253
c19d1205 254 HOWTO (R_ARM_BREL_ADJ, /* type */
7f266840
DJ		 255 1, /* rightshift */
256 1, /* size (0 = byte, 1 = short, 2 = long) */
c19d1205
ZW		 257 32, /* bitsize */
258 FALSE, /* pc_relative */
7f266840
DJ		 259 0, /* bitpos */
260 complain_overflow_signed,/* complain_on_overflow */
261 bfd_elf_generic_reloc, /* special_function */
c19d1205 262 "R_ARM_BREL_ADJ", /* name */
7f266840 263 FALSE, /* partial_inplace */
c19d1205
ZW		 264 0xffffffff, /* src_mask */
265 0xffffffff, /* dst_mask */
266 FALSE), /* pcrel_offset */
7f266840 267
0855e32b 268 HOWTO (R_ARM_TLS_DESC, /* type */
7f266840 269 0, /* rightshift */
0855e32b
NS		 270 2, /* size (0 = byte, 1 = short, 2 = long) */
271 32, /* bitsize */
7f266840
DJ		 272 FALSE, /* pc_relative */
273 0, /* bitpos */
0855e32b 274 complain_overflow_bitfield,/* complain_on_overflow */
7f266840 275 bfd_elf_generic_reloc, /* special_function */
0855e32b 276 "R_ARM_TLS_DESC", /* name */
7f266840 277 FALSE, /* partial_inplace */
0855e32b
NS		 278 0xffffffff, /* src_mask */
279 0xffffffff, /* dst_mask */
7f266840
DJ		 280 FALSE), /* pcrel_offset */
281
282 HOWTO (R_ARM_THM_SWI8, /* type */
283 0, /* rightshift */
284 0, /* size (0 = byte, 1 = short, 2 = long) */
285 0, /* bitsize */
286 FALSE, /* pc_relative */
287 0, /* bitpos */
288 complain_overflow_signed,/* complain_on_overflow */
289 bfd_elf_generic_reloc, /* special_function */
290 "R_ARM_SWI8", /* name */
291 FALSE, /* partial_inplace */
292 0x00000000, /* src_mask */
293 0x00000000, /* dst_mask */
294 FALSE), /* pcrel_offset */
295
296 /* BLX instruction for the ARM. */
297 HOWTO (R_ARM_XPC25, /* type */
298 2, /* rightshift */
299 2, /* size (0 = byte, 1 = short, 2 = long) */
7f6ab9f8 300 24, /* bitsize */
7f266840
DJ		 301 TRUE, /* pc_relative */
302 0, /* bitpos */
303 complain_overflow_signed,/* complain_on_overflow */
304 bfd_elf_generic_reloc, /* special_function */
305 "R_ARM_XPC25", /* name */
306 FALSE, /* partial_inplace */
307 0x00ffffff, /* src_mask */
308 0x00ffffff, /* dst_mask */
309 TRUE), /* pcrel_offset */
310
311 /* BLX instruction for the Thumb. */
312 HOWTO (R_ARM_THM_XPC22, /* type */
313 2, /* rightshift */
314 2, /* size (0 = byte, 1 = short, 2 = long) */
7f6ab9f8 315 24, /* bitsize */
7f266840
DJ		 316 TRUE, /* pc_relative */
317 0, /* bitpos */
318 complain_overflow_signed,/* complain_on_overflow */
319 bfd_elf_generic_reloc, /* special_function */
320 "R_ARM_THM_XPC22", /* name */
321 FALSE, /* partial_inplace */
7f6ab9f8
AM		 322 0x07ff2fff, /* src_mask */
323 0x07ff2fff, /* dst_mask */
7f266840
DJ		 324 TRUE), /* pcrel_offset */
325
ba93b8ac 326 /* Dynamic TLS relocations. */
7f266840 327
ba93b8ac 328 HOWTO (R_ARM_TLS_DTPMOD32, /* type */
99059e56
RM		 329 0, /* rightshift */
330 2, /* size (0 = byte, 1 = short, 2 = long) */
331 32, /* bitsize */
332 FALSE, /* pc_relative */
333 0, /* bitpos */
334 complain_overflow_bitfield,/* complain_on_overflow */
335 bfd_elf_generic_reloc, /* special_function */
336 "R_ARM_TLS_DTPMOD32", /* name */
337 TRUE, /* partial_inplace */
338 0xffffffff, /* src_mask */
339 0xffffffff, /* dst_mask */
340 FALSE), /* pcrel_offset */
7f266840 341
ba93b8ac 342 HOWTO (R_ARM_TLS_DTPOFF32, /* type */
99059e56
RM		 343 0, /* rightshift */
344 2, /* size (0 = byte, 1 = short, 2 = long) */
345 32, /* bitsize */
346 FALSE, /* pc_relative */
347 0, /* bitpos */
348 complain_overflow_bitfield,/* complain_on_overflow */
349 bfd_elf_generic_reloc, /* special_function */
350 "R_ARM_TLS_DTPOFF32", /* name */
351 TRUE, /* partial_inplace */
352 0xffffffff, /* src_mask */
353 0xffffffff, /* dst_mask */
354 FALSE), /* pcrel_offset */
7f266840 355
ba93b8ac 356 HOWTO (R_ARM_TLS_TPOFF32, /* type */
99059e56
RM		 357 0, /* rightshift */
358 2, /* size (0 = byte, 1 = short, 2 = long) */
359 32, /* bitsize */
360 FALSE, /* pc_relative */
361 0, /* bitpos */
362 complain_overflow_bitfield,/* complain_on_overflow */
363 bfd_elf_generic_reloc, /* special_function */
364 "R_ARM_TLS_TPOFF32", /* name */
365 TRUE, /* partial_inplace */
366 0xffffffff, /* src_mask */
367 0xffffffff, /* dst_mask */
368 FALSE), /* pcrel_offset */
7f266840
DJ		 369
370 /* Relocs used in ARM Linux */
371
372 HOWTO (R_ARM_COPY, /* type */
99059e56
RM		 373 0, /* rightshift */
374 2, /* size (0 = byte, 1 = short, 2 = long) */
375 32, /* bitsize */
376 FALSE, /* pc_relative */
377 0, /* bitpos */
378 complain_overflow_bitfield,/* complain_on_overflow */
379 bfd_elf_generic_reloc, /* special_function */
380 "R_ARM_COPY", /* name */
381 TRUE, /* partial_inplace */
382 0xffffffff, /* src_mask */
383 0xffffffff, /* dst_mask */
384 FALSE), /* pcrel_offset */
7f266840
DJ		 385
386 HOWTO (R_ARM_GLOB_DAT, /* type */
99059e56
RM		 387 0, /* rightshift */
388 2, /* size (0 = byte, 1 = short, 2 = long) */
389 32, /* bitsize */
390 FALSE, /* pc_relative */
391 0, /* bitpos */
392 complain_overflow_bitfield,/* complain_on_overflow */
393 bfd_elf_generic_reloc, /* special_function */
394 "R_ARM_GLOB_DAT", /* name */
395 TRUE, /* partial_inplace */
396 0xffffffff, /* src_mask */
397 0xffffffff, /* dst_mask */
398 FALSE), /* pcrel_offset */
7f266840
DJ		 399
400 HOWTO (R_ARM_JUMP_SLOT, /* type */
99059e56
RM		 401 0, /* rightshift */
402 2, /* size (0 = byte, 1 = short, 2 = long) */
403 32, /* bitsize */
404 FALSE, /* pc_relative */
405 0, /* bitpos */
406 complain_overflow_bitfield,/* complain_on_overflow */
407 bfd_elf_generic_reloc, /* special_function */
408 "R_ARM_JUMP_SLOT", /* name */
409 TRUE, /* partial_inplace */
410 0xffffffff, /* src_mask */
411 0xffffffff, /* dst_mask */
412 FALSE), /* pcrel_offset */
7f266840
DJ		 413
414 HOWTO (R_ARM_RELATIVE, /* type */
99059e56
RM		 415 0, /* rightshift */
416 2, /* size (0 = byte, 1 = short, 2 = long) */
417 32, /* bitsize */
418 FALSE, /* pc_relative */
419 0, /* bitpos */
420 complain_overflow_bitfield,/* complain_on_overflow */
421 bfd_elf_generic_reloc, /* special_function */
422 "R_ARM_RELATIVE", /* name */
423 TRUE, /* partial_inplace */
424 0xffffffff, /* src_mask */
425 0xffffffff, /* dst_mask */
426 FALSE), /* pcrel_offset */
7f266840 427
c19d1205 428 HOWTO (R_ARM_GOTOFF32, /* type */
99059e56
RM		 429 0, /* rightshift */
430 2, /* size (0 = byte, 1 = short, 2 = long) */
431 32, /* bitsize */
432 FALSE, /* pc_relative */
433 0, /* bitpos */
434 complain_overflow_bitfield,/* complain_on_overflow */
435 bfd_elf_generic_reloc, /* special_function */
436 "R_ARM_GOTOFF32", /* name */
437 TRUE, /* partial_inplace */
438 0xffffffff, /* src_mask */
439 0xffffffff, /* dst_mask */
440 FALSE), /* pcrel_offset */
7f266840
DJ		 441
442 HOWTO (R_ARM_GOTPC, /* type */
99059e56
RM		 443 0, /* rightshift */
444 2, /* size (0 = byte, 1 = short, 2 = long) */
445 32, /* bitsize */
446 TRUE, /* pc_relative */
447 0, /* bitpos */
448 complain_overflow_bitfield,/* complain_on_overflow */
449 bfd_elf_generic_reloc, /* special_function */
450 "R_ARM_GOTPC", /* name */
451 TRUE, /* partial_inplace */
452 0xffffffff, /* src_mask */
453 0xffffffff, /* dst_mask */
454 TRUE), /* pcrel_offset */
7f266840
DJ		 455
456 HOWTO (R_ARM_GOT32, /* type */
99059e56
RM		 457 0, /* rightshift */
458 2, /* size (0 = byte, 1 = short, 2 = long) */
459 32, /* bitsize */
460 FALSE, /* pc_relative */
461 0, /* bitpos */
462 complain_overflow_bitfield,/* complain_on_overflow */
463 bfd_elf_generic_reloc, /* special_function */
464 "R_ARM_GOT32", /* name */
465 TRUE, /* partial_inplace */
466 0xffffffff, /* src_mask */
467 0xffffffff, /* dst_mask */
468 FALSE), /* pcrel_offset */
7f266840
DJ		 469
470 HOWTO (R_ARM_PLT32, /* type */
99059e56
RM		 471 2, /* rightshift */
472 2, /* size (0 = byte, 1 = short, 2 = long) */
473 24, /* bitsize */
474 TRUE, /* pc_relative */
475 0, /* bitpos */
476 complain_overflow_bitfield,/* complain_on_overflow */
477 bfd_elf_generic_reloc, /* special_function */
478 "R_ARM_PLT32", /* name */
479 FALSE, /* partial_inplace */
480 0x00ffffff, /* src_mask */
481 0x00ffffff, /* dst_mask */
482 TRUE), /* pcrel_offset */
7f266840
DJ		 483
484 HOWTO (R_ARM_CALL, /* type */
485 2, /* rightshift */
486 2, /* size (0 = byte, 1 = short, 2 = long) */
487 24, /* bitsize */
488 TRUE, /* pc_relative */
489 0, /* bitpos */
490 complain_overflow_signed,/* complain_on_overflow */
491 bfd_elf_generic_reloc, /* special_function */
492 "R_ARM_CALL", /* name */
493 FALSE, /* partial_inplace */
494 0x00ffffff, /* src_mask */
495 0x00ffffff, /* dst_mask */
496 TRUE), /* pcrel_offset */
497
498 HOWTO (R_ARM_JUMP24, /* type */
499 2, /* rightshift */
500 2, /* size (0 = byte, 1 = short, 2 = long) */
501 24, /* bitsize */
502 TRUE, /* pc_relative */
503 0, /* bitpos */
504 complain_overflow_signed,/* complain_on_overflow */
505 bfd_elf_generic_reloc, /* special_function */
506 "R_ARM_JUMP24", /* name */
507 FALSE, /* partial_inplace */
508 0x00ffffff, /* src_mask */
509 0x00ffffff, /* dst_mask */
510 TRUE), /* pcrel_offset */
511
c19d1205
ZW		 512 HOWTO (R_ARM_THM_JUMP24, /* type */
513 1, /* rightshift */
514 2, /* size (0 = byte, 1 = short, 2 = long) */
515 24, /* bitsize */
516 TRUE, /* pc_relative */
7f266840 517 0, /* bitpos */
c19d1205 518 complain_overflow_signed,/* complain_on_overflow */
7f266840 519 bfd_elf_generic_reloc, /* special_function */
c19d1205 520 "R_ARM_THM_JUMP24", /* name */
7f266840 521 FALSE, /* partial_inplace */
c19d1205
ZW		 522 0x07ff2fff, /* src_mask */
523 0x07ff2fff, /* dst_mask */
524 TRUE), /* pcrel_offset */
7f266840 525
c19d1205 526 HOWTO (R_ARM_BASE_ABS, /* type */
7f266840 527 0, /* rightshift */
c19d1205
ZW		 528 2, /* size (0 = byte, 1 = short, 2 = long) */
529 32, /* bitsize */
7f266840
DJ		 530 FALSE, /* pc_relative */
531 0, /* bitpos */
532 complain_overflow_dont,/* complain_on_overflow */
533 bfd_elf_generic_reloc, /* special_function */
c19d1205 534 "R_ARM_BASE_ABS", /* name */
7f266840 535 FALSE, /* partial_inplace */
c19d1205
ZW		 536 0xffffffff, /* src_mask */
537 0xffffffff, /* dst_mask */
7f266840
DJ		 538 FALSE), /* pcrel_offset */
539
540 HOWTO (R_ARM_ALU_PCREL7_0, /* type */
541 0, /* rightshift */
542 2, /* size (0 = byte, 1 = short, 2 = long) */
543 12, /* bitsize */
544 TRUE, /* pc_relative */
545 0, /* bitpos */
546 complain_overflow_dont,/* complain_on_overflow */
547 bfd_elf_generic_reloc, /* special_function */
548 "R_ARM_ALU_PCREL_7_0", /* name */
549 FALSE, /* partial_inplace */
550 0x00000fff, /* src_mask */
551 0x00000fff, /* dst_mask */
552 TRUE), /* pcrel_offset */
553
554 HOWTO (R_ARM_ALU_PCREL15_8, /* type */
555 0, /* rightshift */
556 2, /* size (0 = byte, 1 = short, 2 = long) */
557 12, /* bitsize */
558 TRUE, /* pc_relative */
559 8, /* bitpos */
560 complain_overflow_dont,/* complain_on_overflow */
561 bfd_elf_generic_reloc, /* special_function */
562 "R_ARM_ALU_PCREL_15_8",/* name */
563 FALSE, /* partial_inplace */
564 0x00000fff, /* src_mask */
565 0x00000fff, /* dst_mask */
566 TRUE), /* pcrel_offset */
567
568 HOWTO (R_ARM_ALU_PCREL23_15, /* type */
569 0, /* rightshift */
570 2, /* size (0 = byte, 1 = short, 2 = long) */
571 12, /* bitsize */
572 TRUE, /* pc_relative */
573 16, /* bitpos */
574 complain_overflow_dont,/* complain_on_overflow */
575 bfd_elf_generic_reloc, /* special_function */
576 "R_ARM_ALU_PCREL_23_15",/* name */
577 FALSE, /* partial_inplace */
578 0x00000fff, /* src_mask */
579 0x00000fff, /* dst_mask */
580 TRUE), /* pcrel_offset */
581
582 HOWTO (R_ARM_LDR_SBREL_11_0, /* type */
583 0, /* rightshift */
584 2, /* size (0 = byte, 1 = short, 2 = long) */
585 12, /* bitsize */
586 FALSE, /* pc_relative */
587 0, /* bitpos */
588 complain_overflow_dont,/* complain_on_overflow */
589 bfd_elf_generic_reloc, /* special_function */
590 "R_ARM_LDR_SBREL_11_0",/* name */
591 FALSE, /* partial_inplace */
592 0x00000fff, /* src_mask */
593 0x00000fff, /* dst_mask */
594 FALSE), /* pcrel_offset */
595
596 HOWTO (R_ARM_ALU_SBREL_19_12, /* type */
597 0, /* rightshift */
598 2, /* size (0 = byte, 1 = short, 2 = long) */
599 8, /* bitsize */
600 FALSE, /* pc_relative */
601 12, /* bitpos */
602 complain_overflow_dont,/* complain_on_overflow */
603 bfd_elf_generic_reloc, /* special_function */
604 "R_ARM_ALU_SBREL_19_12",/* name */
605 FALSE, /* partial_inplace */
606 0x000ff000, /* src_mask */
607 0x000ff000, /* dst_mask */
608 FALSE), /* pcrel_offset */
609
610 HOWTO (R_ARM_ALU_SBREL_27_20, /* type */
611 0, /* rightshift */
612 2, /* size (0 = byte, 1 = short, 2 = long) */
613 8, /* bitsize */
614 FALSE, /* pc_relative */
615 20, /* bitpos */
616 complain_overflow_dont,/* complain_on_overflow */
617 bfd_elf_generic_reloc, /* special_function */
618 "R_ARM_ALU_SBREL_27_20",/* name */
619 FALSE, /* partial_inplace */
620 0x0ff00000, /* src_mask */
621 0x0ff00000, /* dst_mask */
622 FALSE), /* pcrel_offset */
623
624 HOWTO (R_ARM_TARGET1, /* type */
625 0, /* rightshift */
626 2, /* size (0 = byte, 1 = short, 2 = long) */
627 32, /* bitsize */
628 FALSE, /* pc_relative */
629 0, /* bitpos */
630 complain_overflow_dont,/* complain_on_overflow */
631 bfd_elf_generic_reloc, /* special_function */
632 "R_ARM_TARGET1", /* name */
633 FALSE, /* partial_inplace */
634 0xffffffff, /* src_mask */
635 0xffffffff, /* dst_mask */
636 FALSE), /* pcrel_offset */
637
638 HOWTO (R_ARM_ROSEGREL32, /* type */
639 0, /* rightshift */
640 2, /* size (0 = byte, 1 = short, 2 = long) */
641 32, /* bitsize */
642 FALSE, /* pc_relative */
643 0, /* bitpos */
644 complain_overflow_dont,/* complain_on_overflow */
645 bfd_elf_generic_reloc, /* special_function */
646 "R_ARM_ROSEGREL32", /* name */
647 FALSE, /* partial_inplace */
648 0xffffffff, /* src_mask */
649 0xffffffff, /* dst_mask */
650 FALSE), /* pcrel_offset */
651
652 HOWTO (R_ARM_V4BX, /* type */
653 0, /* rightshift */
654 2, /* size (0 = byte, 1 = short, 2 = long) */
655 32, /* bitsize */
656 FALSE, /* pc_relative */
657 0, /* bitpos */
658 complain_overflow_dont,/* complain_on_overflow */
659 bfd_elf_generic_reloc, /* special_function */
660 "R_ARM_V4BX", /* name */
661 FALSE, /* partial_inplace */
662 0xffffffff, /* src_mask */
663 0xffffffff, /* dst_mask */
664 FALSE), /* pcrel_offset */
665
666 HOWTO (R_ARM_TARGET2, /* type */
667 0, /* rightshift */
668 2, /* size (0 = byte, 1 = short, 2 = long) */
669 32, /* bitsize */
670 FALSE, /* pc_relative */
671 0, /* bitpos */
672 complain_overflow_signed,/* complain_on_overflow */
673 bfd_elf_generic_reloc, /* special_function */
674 "R_ARM_TARGET2", /* name */
675 FALSE, /* partial_inplace */
676 0xffffffff, /* src_mask */
677 0xffffffff, /* dst_mask */
678 TRUE), /* pcrel_offset */
679
680 HOWTO (R_ARM_PREL31, /* type */
681 0, /* rightshift */
682 2, /* size (0 = byte, 1 = short, 2 = long) */
683 31, /* bitsize */
684 TRUE, /* pc_relative */
685 0, /* bitpos */
686 complain_overflow_signed,/* complain_on_overflow */
687 bfd_elf_generic_reloc, /* special_function */
688 "R_ARM_PREL31", /* name */
689 FALSE, /* partial_inplace */
690 0x7fffffff, /* src_mask */
691 0x7fffffff, /* dst_mask */
692 TRUE), /* pcrel_offset */
c19d1205
ZW		 693
694 HOWTO (R_ARM_MOVW_ABS_NC, /* type */
695 0, /* rightshift */
696 2, /* size (0 = byte, 1 = short, 2 = long) */
697 16, /* bitsize */
698 FALSE, /* pc_relative */
699 0, /* bitpos */
700 complain_overflow_dont,/* complain_on_overflow */
701 bfd_elf_generic_reloc, /* special_function */
702 "R_ARM_MOVW_ABS_NC", /* name */
703 FALSE, /* partial_inplace */
39623e12
PB		 704 0x000f0fff, /* src_mask */
705 0x000f0fff, /* dst_mask */
c19d1205
ZW		 706 FALSE), /* pcrel_offset */
707
708 HOWTO (R_ARM_MOVT_ABS, /* type */
709 0, /* rightshift */
710 2, /* size (0 = byte, 1 = short, 2 = long) */
711 16, /* bitsize */
712 FALSE, /* pc_relative */
713 0, /* bitpos */
714 complain_overflow_bitfield,/* complain_on_overflow */
715 bfd_elf_generic_reloc, /* special_function */
716 "R_ARM_MOVT_ABS", /* name */
717 FALSE, /* partial_inplace */
39623e12
PB		 718 0x000f0fff, /* src_mask */
719 0x000f0fff, /* dst_mask */
c19d1205
ZW		 720 FALSE), /* pcrel_offset */
721
722 HOWTO (R_ARM_MOVW_PREL_NC, /* type */
723 0, /* rightshift */
724 2, /* size (0 = byte, 1 = short, 2 = long) */
725 16, /* bitsize */
726 TRUE, /* pc_relative */
727 0, /* bitpos */
728 complain_overflow_dont,/* complain_on_overflow */
729 bfd_elf_generic_reloc, /* special_function */
730 "R_ARM_MOVW_PREL_NC", /* name */
731 FALSE, /* partial_inplace */
39623e12
PB		 732 0x000f0fff, /* src_mask */
733 0x000f0fff, /* dst_mask */
c19d1205
ZW		 734 TRUE), /* pcrel_offset */
735
736 HOWTO (R_ARM_MOVT_PREL, /* type */
737 0, /* rightshift */
738 2, /* size (0 = byte, 1 = short, 2 = long) */
739 16, /* bitsize */
740 TRUE, /* pc_relative */
741 0, /* bitpos */
742 complain_overflow_bitfield,/* complain_on_overflow */
743 bfd_elf_generic_reloc, /* special_function */
744 "R_ARM_MOVT_PREL", /* name */
745 FALSE, /* partial_inplace */
39623e12
PB		 746 0x000f0fff, /* src_mask */
747 0x000f0fff, /* dst_mask */
c19d1205
ZW		 748 TRUE), /* pcrel_offset */
749
750 HOWTO (R_ARM_THM_MOVW_ABS_NC, /* type */
751 0, /* rightshift */
752 2, /* size (0 = byte, 1 = short, 2 = long) */
753 16, /* bitsize */
754 FALSE, /* pc_relative */
755 0, /* bitpos */
756 complain_overflow_dont,/* complain_on_overflow */
757 bfd_elf_generic_reloc, /* special_function */
758 "R_ARM_THM_MOVW_ABS_NC",/* name */
759 FALSE, /* partial_inplace */
760 0x040f70ff, /* src_mask */
761 0x040f70ff, /* dst_mask */
762 FALSE), /* pcrel_offset */
763
764 HOWTO (R_ARM_THM_MOVT_ABS, /* type */
765 0, /* rightshift */
766 2, /* size (0 = byte, 1 = short, 2 = long) */
767 16, /* bitsize */
768 FALSE, /* pc_relative */
769 0, /* bitpos */
770 complain_overflow_bitfield,/* complain_on_overflow */
771 bfd_elf_generic_reloc, /* special_function */
772 "R_ARM_THM_MOVT_ABS", /* name */
773 FALSE, /* partial_inplace */
774 0x040f70ff, /* src_mask */
775 0x040f70ff, /* dst_mask */
776 FALSE), /* pcrel_offset */
777
778 HOWTO (R_ARM_THM_MOVW_PREL_NC,/* type */
779 0, /* rightshift */
780 2, /* size (0 = byte, 1 = short, 2 = long) */
781 16, /* bitsize */
782 TRUE, /* pc_relative */
783 0, /* bitpos */
784 complain_overflow_dont,/* complain_on_overflow */
785 bfd_elf_generic_reloc, /* special_function */
786 "R_ARM_THM_MOVW_PREL_NC",/* name */
787 FALSE, /* partial_inplace */
788 0x040f70ff, /* src_mask */
789 0x040f70ff, /* dst_mask */
790 TRUE), /* pcrel_offset */
791
792 HOWTO (R_ARM_THM_MOVT_PREL, /* type */
793 0, /* rightshift */
794 2, /* size (0 = byte, 1 = short, 2 = long) */
795 16, /* bitsize */
796 TRUE, /* pc_relative */
797 0, /* bitpos */
798 complain_overflow_bitfield,/* complain_on_overflow */
799 bfd_elf_generic_reloc, /* special_function */
800 "R_ARM_THM_MOVT_PREL", /* name */
801 FALSE, /* partial_inplace */
802 0x040f70ff, /* src_mask */
803 0x040f70ff, /* dst_mask */
804 TRUE), /* pcrel_offset */
805
806 HOWTO (R_ARM_THM_JUMP19, /* type */
807 1, /* rightshift */
808 2, /* size (0 = byte, 1 = short, 2 = long) */
809 19, /* bitsize */
810 TRUE, /* pc_relative */
811 0, /* bitpos */
812 complain_overflow_signed,/* complain_on_overflow */
813 bfd_elf_generic_reloc, /* special_function */
814 "R_ARM_THM_JUMP19", /* name */
815 FALSE, /* partial_inplace */
816 0x043f2fff, /* src_mask */
817 0x043f2fff, /* dst_mask */
818 TRUE), /* pcrel_offset */
819
820 HOWTO (R_ARM_THM_JUMP6, /* type */
821 1, /* rightshift */
822 1, /* size (0 = byte, 1 = short, 2 = long) */
823 6, /* bitsize */
824 TRUE, /* pc_relative */
825 0, /* bitpos */
826 complain_overflow_unsigned,/* complain_on_overflow */
827 bfd_elf_generic_reloc, /* special_function */
828 "R_ARM_THM_JUMP6", /* name */
829 FALSE, /* partial_inplace */
830 0x02f8, /* src_mask */
831 0x02f8, /* dst_mask */
832 TRUE), /* pcrel_offset */
833
834 /* These are declared as 13-bit signed relocations because we can
835 address -4095 .. 4095(base) by altering ADDW to SUBW or vice
836 versa. */
837 HOWTO (R_ARM_THM_ALU_PREL_11_0,/* type */
838 0, /* rightshift */
839 2, /* size (0 = byte, 1 = short, 2 = long) */
840 13, /* bitsize */
841 TRUE, /* pc_relative */
842 0, /* bitpos */
2cab6cc3 843 complain_overflow_dont,/* complain_on_overflow */
c19d1205
ZW		 844 bfd_elf_generic_reloc, /* special_function */
845 "R_ARM_THM_ALU_PREL_11_0",/* name */
846 FALSE, /* partial_inplace */
2cab6cc3
MS		 847 0xffffffff, /* src_mask */
848 0xffffffff, /* dst_mask */
c19d1205
ZW		 849 TRUE), /* pcrel_offset */
850
851 HOWTO (R_ARM_THM_PC12, /* type */
852 0, /* rightshift */
853 2, /* size (0 = byte, 1 = short, 2 = long) */
854 13, /* bitsize */
855 TRUE, /* pc_relative */
856 0, /* bitpos */
2cab6cc3 857 complain_overflow_dont,/* complain_on_overflow */
c19d1205
ZW		 858 bfd_elf_generic_reloc, /* special_function */
859 "R_ARM_THM_PC12", /* name */
860 FALSE, /* partial_inplace */
2cab6cc3
MS		 861 0xffffffff, /* src_mask */
862 0xffffffff, /* dst_mask */
c19d1205
ZW		 863 TRUE), /* pcrel_offset */
864
865 HOWTO (R_ARM_ABS32_NOI, /* type */
866 0, /* rightshift */
867 2, /* size (0 = byte, 1 = short, 2 = long) */
868 32, /* bitsize */
869 FALSE, /* pc_relative */
870 0, /* bitpos */
871 complain_overflow_dont,/* complain_on_overflow */
872 bfd_elf_generic_reloc, /* special_function */
873 "R_ARM_ABS32_NOI", /* name */
874 FALSE, /* partial_inplace */
875 0xffffffff, /* src_mask */
876 0xffffffff, /* dst_mask */
877 FALSE), /* pcrel_offset */
878
879 HOWTO (R_ARM_REL32_NOI, /* type */
880 0, /* rightshift */
881 2, /* size (0 = byte, 1 = short, 2 = long) */
882 32, /* bitsize */
883 TRUE, /* pc_relative */
884 0, /* bitpos */
885 complain_overflow_dont,/* complain_on_overflow */
886 bfd_elf_generic_reloc, /* special_function */
887 "R_ARM_REL32_NOI", /* name */
888 FALSE, /* partial_inplace */
889 0xffffffff, /* src_mask */
890 0xffffffff, /* dst_mask */
891 FALSE), /* pcrel_offset */
7f266840 892
4962c51a
MS		 893 /* Group relocations. */
894
895 HOWTO (R_ARM_ALU_PC_G0_NC, /* type */
896 0, /* rightshift */
897 2, /* size (0 = byte, 1 = short, 2 = long) */
898 32, /* bitsize */
899 TRUE, /* pc_relative */
900 0, /* bitpos */
901 complain_overflow_dont,/* complain_on_overflow */
902 bfd_elf_generic_reloc, /* special_function */
903 "R_ARM_ALU_PC_G0_NC", /* name */
904 FALSE, /* partial_inplace */
905 0xffffffff, /* src_mask */
906 0xffffffff, /* dst_mask */
907 TRUE), /* pcrel_offset */
908
909 HOWTO (R_ARM_ALU_PC_G0, /* type */
910 0, /* rightshift */
911 2, /* size (0 = byte, 1 = short, 2 = long) */
912 32, /* bitsize */
913 TRUE, /* pc_relative */
914 0, /* bitpos */
915 complain_overflow_dont,/* complain_on_overflow */
916 bfd_elf_generic_reloc, /* special_function */
917 "R_ARM_ALU_PC_G0", /* name */
918 FALSE, /* partial_inplace */
919 0xffffffff, /* src_mask */
920 0xffffffff, /* dst_mask */
921 TRUE), /* pcrel_offset */
922
923 HOWTO (R_ARM_ALU_PC_G1_NC, /* type */
924 0, /* rightshift */
925 2, /* size (0 = byte, 1 = short, 2 = long) */
926 32, /* bitsize */
927 TRUE, /* pc_relative */
928 0, /* bitpos */
929 complain_overflow_dont,/* complain_on_overflow */
930 bfd_elf_generic_reloc, /* special_function */
931 "R_ARM_ALU_PC_G1_NC", /* name */
932 FALSE, /* partial_inplace */
933 0xffffffff, /* src_mask */
934 0xffffffff, /* dst_mask */
935 TRUE), /* pcrel_offset */
936
937 HOWTO (R_ARM_ALU_PC_G1, /* type */
938 0, /* rightshift */
939 2, /* size (0 = byte, 1 = short, 2 = long) */
940 32, /* bitsize */
941 TRUE, /* pc_relative */
942 0, /* bitpos */
943 complain_overflow_dont,/* complain_on_overflow */
944 bfd_elf_generic_reloc, /* special_function */
945 "R_ARM_ALU_PC_G1", /* name */
946 FALSE, /* partial_inplace */
947 0xffffffff, /* src_mask */
948 0xffffffff, /* dst_mask */
949 TRUE), /* pcrel_offset */
950
951 HOWTO (R_ARM_ALU_PC_G2, /* type */
952 0, /* rightshift */
953 2, /* size (0 = byte, 1 = short, 2 = long) */
954 32, /* bitsize */
955 TRUE, /* pc_relative */
956 0, /* bitpos */
957 complain_overflow_dont,/* complain_on_overflow */
958 bfd_elf_generic_reloc, /* special_function */
959 "R_ARM_ALU_PC_G2", /* name */
960 FALSE, /* partial_inplace */
961 0xffffffff, /* src_mask */
962 0xffffffff, /* dst_mask */
963 TRUE), /* pcrel_offset */
964
965 HOWTO (R_ARM_LDR_PC_G1, /* type */
966 0, /* rightshift */
967 2, /* size (0 = byte, 1 = short, 2 = long) */
968 32, /* bitsize */
969 TRUE, /* pc_relative */
970 0, /* bitpos */
971 complain_overflow_dont,/* complain_on_overflow */
972 bfd_elf_generic_reloc, /* special_function */
973 "R_ARM_LDR_PC_G1", /* name */
974 FALSE, /* partial_inplace */
975 0xffffffff, /* src_mask */
976 0xffffffff, /* dst_mask */
977 TRUE), /* pcrel_offset */
978
979 HOWTO (R_ARM_LDR_PC_G2, /* type */
980 0, /* rightshift */
981 2, /* size (0 = byte, 1 = short, 2 = long) */
982 32, /* bitsize */
983 TRUE, /* pc_relative */
984 0, /* bitpos */
985 complain_overflow_dont,/* complain_on_overflow */
986 bfd_elf_generic_reloc, /* special_function */
987 "R_ARM_LDR_PC_G2", /* name */
988 FALSE, /* partial_inplace */
989 0xffffffff, /* src_mask */
990 0xffffffff, /* dst_mask */
991 TRUE), /* pcrel_offset */
992
993 HOWTO (R_ARM_LDRS_PC_G0, /* type */
994 0, /* rightshift */
995 2, /* size (0 = byte, 1 = short, 2 = long) */
996 32, /* bitsize */
997 TRUE, /* pc_relative */
998 0, /* bitpos */
999 complain_overflow_dont,/* complain_on_overflow */
1000 bfd_elf_generic_reloc, /* special_function */
1001 "R_ARM_LDRS_PC_G0", /* name */
1002 FALSE, /* partial_inplace */
1003 0xffffffff, /* src_mask */
1004 0xffffffff, /* dst_mask */
1005 TRUE), /* pcrel_offset */
1006
1007 HOWTO (R_ARM_LDRS_PC_G1, /* type */
1008 0, /* rightshift */
1009 2, /* size (0 = byte, 1 = short, 2 = long) */
1010 32, /* bitsize */
1011 TRUE, /* pc_relative */
1012 0, /* bitpos */
1013 complain_overflow_dont,/* complain_on_overflow */
1014 bfd_elf_generic_reloc, /* special_function */
1015 "R_ARM_LDRS_PC_G1", /* name */
1016 FALSE, /* partial_inplace */
1017 0xffffffff, /* src_mask */
1018 0xffffffff, /* dst_mask */
1019 TRUE), /* pcrel_offset */
1020
1021 HOWTO (R_ARM_LDRS_PC_G2, /* type */
1022 0, /* rightshift */
1023 2, /* size (0 = byte, 1 = short, 2 = long) */
1024 32, /* bitsize */
1025 TRUE, /* pc_relative */
1026 0, /* bitpos */
1027 complain_overflow_dont,/* complain_on_overflow */
1028 bfd_elf_generic_reloc, /* special_function */
1029 "R_ARM_LDRS_PC_G2", /* name */
1030 FALSE, /* partial_inplace */
1031 0xffffffff, /* src_mask */
1032 0xffffffff, /* dst_mask */
1033 TRUE), /* pcrel_offset */
1034
1035 HOWTO (R_ARM_LDC_PC_G0, /* type */
1036 0, /* rightshift */
1037 2, /* size (0 = byte, 1 = short, 2 = long) */
1038 32, /* bitsize */
1039 TRUE, /* pc_relative */
1040 0, /* bitpos */
1041 complain_overflow_dont,/* complain_on_overflow */
1042 bfd_elf_generic_reloc, /* special_function */
1043 "R_ARM_LDC_PC_G0", /* name */
1044 FALSE, /* partial_inplace */
1045 0xffffffff, /* src_mask */
1046 0xffffffff, /* dst_mask */
1047 TRUE), /* pcrel_offset */
1048
1049 HOWTO (R_ARM_LDC_PC_G1, /* type */
1050 0, /* rightshift */
1051 2, /* size (0 = byte, 1 = short, 2 = long) */
1052 32, /* bitsize */
1053 TRUE, /* pc_relative */
1054 0, /* bitpos */
1055 complain_overflow_dont,/* complain_on_overflow */
1056 bfd_elf_generic_reloc, /* special_function */
1057 "R_ARM_LDC_PC_G1", /* name */
1058 FALSE, /* partial_inplace */
1059 0xffffffff, /* src_mask */
1060 0xffffffff, /* dst_mask */
1061 TRUE), /* pcrel_offset */
1062
1063 HOWTO (R_ARM_LDC_PC_G2, /* type */
1064 0, /* rightshift */
1065 2, /* size (0 = byte, 1 = short, 2 = long) */
1066 32, /* bitsize */
1067 TRUE, /* pc_relative */
1068 0, /* bitpos */
1069 complain_overflow_dont,/* complain_on_overflow */
1070 bfd_elf_generic_reloc, /* special_function */
1071 "R_ARM_LDC_PC_G2", /* name */
1072 FALSE, /* partial_inplace */
1073 0xffffffff, /* src_mask */
1074 0xffffffff, /* dst_mask */
1075 TRUE), /* pcrel_offset */
1076
1077 HOWTO (R_ARM_ALU_SB_G0_NC, /* type */
1078 0, /* rightshift */
1079 2, /* size (0 = byte, 1 = short, 2 = long) */
1080 32, /* bitsize */
1081 TRUE, /* pc_relative */
1082 0, /* bitpos */
1083 complain_overflow_dont,/* complain_on_overflow */
1084 bfd_elf_generic_reloc, /* special_function */
1085 "R_ARM_ALU_SB_G0_NC", /* name */
1086 FALSE, /* partial_inplace */
1087 0xffffffff, /* src_mask */
1088 0xffffffff, /* dst_mask */
1089 TRUE), /* pcrel_offset */
1090
1091 HOWTO (R_ARM_ALU_SB_G0, /* type */
1092 0, /* rightshift */
1093 2, /* size (0 = byte, 1 = short, 2 = long) */
1094 32, /* bitsize */
1095 TRUE, /* pc_relative */
1096 0, /* bitpos */
1097 complain_overflow_dont,/* complain_on_overflow */
1098 bfd_elf_generic_reloc, /* special_function */
1099 "R_ARM_ALU_SB_G0", /* name */
1100 FALSE, /* partial_inplace */
1101 0xffffffff, /* src_mask */
1102 0xffffffff, /* dst_mask */
1103 TRUE), /* pcrel_offset */
1104
1105 HOWTO (R_ARM_ALU_SB_G1_NC, /* type */
1106 0, /* rightshift */
1107 2, /* size (0 = byte, 1 = short, 2 = long) */
1108 32, /* bitsize */
1109 TRUE, /* pc_relative */
1110 0, /* bitpos */
1111 complain_overflow_dont,/* complain_on_overflow */
1112 bfd_elf_generic_reloc, /* special_function */
1113 "R_ARM_ALU_SB_G1_NC", /* name */
1114 FALSE, /* partial_inplace */
1115 0xffffffff, /* src_mask */
1116 0xffffffff, /* dst_mask */
1117 TRUE), /* pcrel_offset */
1118
1119 HOWTO (R_ARM_ALU_SB_G1, /* type */
1120 0, /* rightshift */
1121 2, /* size (0 = byte, 1 = short, 2 = long) */
1122 32, /* bitsize */
1123 TRUE, /* pc_relative */
1124 0, /* bitpos */
1125 complain_overflow_dont,/* complain_on_overflow */
1126 bfd_elf_generic_reloc, /* special_function */
1127 "R_ARM_ALU_SB_G1", /* name */
1128 FALSE, /* partial_inplace */
1129 0xffffffff, /* src_mask */
1130 0xffffffff, /* dst_mask */
1131 TRUE), /* pcrel_offset */
1132
1133 HOWTO (R_ARM_ALU_SB_G2, /* type */
1134 0, /* rightshift */
1135 2, /* size (0 = byte, 1 = short, 2 = long) */
1136 32, /* bitsize */
1137 TRUE, /* pc_relative */
1138 0, /* bitpos */
1139 complain_overflow_dont,/* complain_on_overflow */
1140 bfd_elf_generic_reloc, /* special_function */
1141 "R_ARM_ALU_SB_G2", /* name */
1142 FALSE, /* partial_inplace */
1143 0xffffffff, /* src_mask */
1144 0xffffffff, /* dst_mask */
1145 TRUE), /* pcrel_offset */
1146
1147 HOWTO (R_ARM_LDR_SB_G0, /* type */
1148 0, /* rightshift */
1149 2, /* size (0 = byte, 1 = short, 2 = long) */
1150 32, /* bitsize */
1151 TRUE, /* pc_relative */
1152 0, /* bitpos */
1153 complain_overflow_dont,/* complain_on_overflow */
1154 bfd_elf_generic_reloc, /* special_function */
1155 "R_ARM_LDR_SB_G0", /* name */
1156 FALSE, /* partial_inplace */
1157 0xffffffff, /* src_mask */
1158 0xffffffff, /* dst_mask */
1159 TRUE), /* pcrel_offset */
1160
1161 HOWTO (R_ARM_LDR_SB_G1, /* type */
1162 0, /* rightshift */
1163 2, /* size (0 = byte, 1 = short, 2 = long) */
1164 32, /* bitsize */
1165 TRUE, /* pc_relative */
1166 0, /* bitpos */
1167 complain_overflow_dont,/* complain_on_overflow */
1168 bfd_elf_generic_reloc, /* special_function */
1169 "R_ARM_LDR_SB_G1", /* name */
1170 FALSE, /* partial_inplace */
1171 0xffffffff, /* src_mask */
1172 0xffffffff, /* dst_mask */
1173 TRUE), /* pcrel_offset */
1174
1175 HOWTO (R_ARM_LDR_SB_G2, /* type */
1176 0, /* rightshift */
1177 2, /* size (0 = byte, 1 = short, 2 = long) */
1178 32, /* bitsize */
1179 TRUE, /* pc_relative */
1180 0, /* bitpos */
1181 complain_overflow_dont,/* complain_on_overflow */
1182 bfd_elf_generic_reloc, /* special_function */
1183 "R_ARM_LDR_SB_G2", /* name */
1184 FALSE, /* partial_inplace */
1185 0xffffffff, /* src_mask */
1186 0xffffffff, /* dst_mask */
1187 TRUE), /* pcrel_offset */
1188
1189 HOWTO (R_ARM_LDRS_SB_G0, /* type */
1190 0, /* rightshift */
1191 2, /* size (0 = byte, 1 = short, 2 = long) */
1192 32, /* bitsize */
1193 TRUE, /* pc_relative */
1194 0, /* bitpos */
1195 complain_overflow_dont,/* complain_on_overflow */
1196 bfd_elf_generic_reloc, /* special_function */
1197 "R_ARM_LDRS_SB_G0", /* name */
1198 FALSE, /* partial_inplace */
1199 0xffffffff, /* src_mask */
1200 0xffffffff, /* dst_mask */
1201 TRUE), /* pcrel_offset */
1202
1203 HOWTO (R_ARM_LDRS_SB_G1, /* type */
1204 0, /* rightshift */
1205 2, /* size (0 = byte, 1 = short, 2 = long) */
1206 32, /* bitsize */
1207 TRUE, /* pc_relative */
1208 0, /* bitpos */
1209 complain_overflow_dont,/* complain_on_overflow */
1210 bfd_elf_generic_reloc, /* special_function */
1211 "R_ARM_LDRS_SB_G1", /* name */
1212 FALSE, /* partial_inplace */
1213 0xffffffff, /* src_mask */
1214 0xffffffff, /* dst_mask */
1215 TRUE), /* pcrel_offset */
1216
1217 HOWTO (R_ARM_LDRS_SB_G2, /* type */
1218 0, /* rightshift */
1219 2, /* size (0 = byte, 1 = short, 2 = long) */
1220 32, /* bitsize */
1221 TRUE, /* pc_relative */
1222 0, /* bitpos */
1223 complain_overflow_dont,/* complain_on_overflow */
1224 bfd_elf_generic_reloc, /* special_function */
1225 "R_ARM_LDRS_SB_G2", /* name */
1226 FALSE, /* partial_inplace */
1227 0xffffffff, /* src_mask */
1228 0xffffffff, /* dst_mask */
1229 TRUE), /* pcrel_offset */
1230
1231 HOWTO (R_ARM_LDC_SB_G0, /* type */
1232 0, /* rightshift */
1233 2, /* size (0 = byte, 1 = short, 2 = long) */
1234 32, /* bitsize */
1235 TRUE, /* pc_relative */
1236 0, /* bitpos */
1237 complain_overflow_dont,/* complain_on_overflow */
1238 bfd_elf_generic_reloc, /* special_function */
1239 "R_ARM_LDC_SB_G0", /* name */
1240 FALSE, /* partial_inplace */
1241 0xffffffff, /* src_mask */
1242 0xffffffff, /* dst_mask */
1243 TRUE), /* pcrel_offset */
1244
1245 HOWTO (R_ARM_LDC_SB_G1, /* type */
1246 0, /* rightshift */
1247 2, /* size (0 = byte, 1 = short, 2 = long) */
1248 32, /* bitsize */
1249 TRUE, /* pc_relative */
1250 0, /* bitpos */
1251 complain_overflow_dont,/* complain_on_overflow */
1252 bfd_elf_generic_reloc, /* special_function */
1253 "R_ARM_LDC_SB_G1", /* name */
1254 FALSE, /* partial_inplace */
1255 0xffffffff, /* src_mask */
1256 0xffffffff, /* dst_mask */
1257 TRUE), /* pcrel_offset */
1258
1259 HOWTO (R_ARM_LDC_SB_G2, /* type */
1260 0, /* rightshift */
1261 2, /* size (0 = byte, 1 = short, 2 = long) */
1262 32, /* bitsize */
1263 TRUE, /* pc_relative */
1264 0, /* bitpos */
1265 complain_overflow_dont,/* complain_on_overflow */
1266 bfd_elf_generic_reloc, /* special_function */
1267 "R_ARM_LDC_SB_G2", /* name */
1268 FALSE, /* partial_inplace */
1269 0xffffffff, /* src_mask */
1270 0xffffffff, /* dst_mask */
1271 TRUE), /* pcrel_offset */
1272
1273 /* End of group relocations. */
c19d1205 1274
c19d1205
ZW		 1275 HOWTO (R_ARM_MOVW_BREL_NC, /* type */
1276 0, /* rightshift */
1277 2, /* size (0 = byte, 1 = short, 2 = long) */
1278 16, /* bitsize */
1279 FALSE, /* pc_relative */
1280 0, /* bitpos */
1281 complain_overflow_dont,/* complain_on_overflow */
1282 bfd_elf_generic_reloc, /* special_function */
1283 "R_ARM_MOVW_BREL_NC", /* name */
1284 FALSE, /* partial_inplace */
1285 0x0000ffff, /* src_mask */
1286 0x0000ffff, /* dst_mask */
1287 FALSE), /* pcrel_offset */
1288
1289 HOWTO (R_ARM_MOVT_BREL, /* type */
1290 0, /* rightshift */
1291 2, /* size (0 = byte, 1 = short, 2 = long) */
1292 16, /* bitsize */
1293 FALSE, /* pc_relative */
1294 0, /* bitpos */
1295 complain_overflow_bitfield,/* complain_on_overflow */
1296 bfd_elf_generic_reloc, /* special_function */
1297 "R_ARM_MOVT_BREL", /* name */
1298 FALSE, /* partial_inplace */
1299 0x0000ffff, /* src_mask */
1300 0x0000ffff, /* dst_mask */
1301 FALSE), /* pcrel_offset */
1302
1303 HOWTO (R_ARM_MOVW_BREL, /* type */
1304 0, /* rightshift */
1305 2, /* size (0 = byte, 1 = short, 2 = long) */
1306 16, /* bitsize */
1307 FALSE, /* pc_relative */
1308 0, /* bitpos */
1309 complain_overflow_dont,/* complain_on_overflow */
1310 bfd_elf_generic_reloc, /* special_function */
1311 "R_ARM_MOVW_BREL", /* name */
1312 FALSE, /* partial_inplace */
1313 0x0000ffff, /* src_mask */
1314 0x0000ffff, /* dst_mask */
1315 FALSE), /* pcrel_offset */
1316
1317 HOWTO (R_ARM_THM_MOVW_BREL_NC,/* type */
1318 0, /* rightshift */
1319 2, /* size (0 = byte, 1 = short, 2 = long) */
1320 16, /* bitsize */
1321 FALSE, /* pc_relative */
1322 0, /* bitpos */
1323 complain_overflow_dont,/* complain_on_overflow */
1324 bfd_elf_generic_reloc, /* special_function */
1325 "R_ARM_THM_MOVW_BREL_NC",/* name */
1326 FALSE, /* partial_inplace */
1327 0x040f70ff, /* src_mask */
1328 0x040f70ff, /* dst_mask */
1329 FALSE), /* pcrel_offset */
1330
1331 HOWTO (R_ARM_THM_MOVT_BREL, /* type */
1332 0, /* rightshift */
1333 2, /* size (0 = byte, 1 = short, 2 = long) */
1334 16, /* bitsize */
1335 FALSE, /* pc_relative */
1336 0, /* bitpos */
1337 complain_overflow_bitfield,/* complain_on_overflow */
1338 bfd_elf_generic_reloc, /* special_function */
1339 "R_ARM_THM_MOVT_BREL", /* name */
1340 FALSE, /* partial_inplace */
1341 0x040f70ff, /* src_mask */
1342 0x040f70ff, /* dst_mask */
1343 FALSE), /* pcrel_offset */
1344
1345 HOWTO (R_ARM_THM_MOVW_BREL, /* type */
1346 0, /* rightshift */
1347 2, /* size (0 = byte, 1 = short, 2 = long) */
1348 16, /* bitsize */
1349 FALSE, /* pc_relative */
1350 0, /* bitpos */
1351 complain_overflow_dont,/* complain_on_overflow */
1352 bfd_elf_generic_reloc, /* special_function */
1353 "R_ARM_THM_MOVW_BREL", /* name */
1354 FALSE, /* partial_inplace */
1355 0x040f70ff, /* src_mask */
1356 0x040f70ff, /* dst_mask */
1357 FALSE), /* pcrel_offset */
1358
0855e32b
NS		 1359 HOWTO (R_ARM_TLS_GOTDESC, /* type */
1360 0, /* rightshift */
1361 2, /* size (0 = byte, 1 = short, 2 = long) */
1362 32, /* bitsize */
1363 FALSE, /* pc_relative */
1364 0, /* bitpos */
1365 complain_overflow_bitfield,/* complain_on_overflow */
1366 NULL, /* special_function */
1367 "R_ARM_TLS_GOTDESC", /* name */
1368 TRUE, /* partial_inplace */
1369 0xffffffff, /* src_mask */
1370 0xffffffff, /* dst_mask */
1371 FALSE), /* pcrel_offset */
1372
1373 HOWTO (R_ARM_TLS_CALL, /* type */
1374 0, /* rightshift */
1375 2, /* size (0 = byte, 1 = short, 2 = long) */
1376 24, /* bitsize */
1377 FALSE, /* pc_relative */
1378 0, /* bitpos */
1379 complain_overflow_dont,/* complain_on_overflow */
1380 bfd_elf_generic_reloc, /* special_function */
1381 "R_ARM_TLS_CALL", /* name */
1382 FALSE, /* partial_inplace */
1383 0x00ffffff, /* src_mask */
1384 0x00ffffff, /* dst_mask */
1385 FALSE), /* pcrel_offset */
1386
1387 HOWTO (R_ARM_TLS_DESCSEQ, /* type */
1388 0, /* rightshift */
1389 2, /* size (0 = byte, 1 = short, 2 = long) */
1390 0, /* bitsize */
1391 FALSE, /* pc_relative */
1392 0, /* bitpos */
1393 complain_overflow_bitfield,/* complain_on_overflow */
1394 bfd_elf_generic_reloc, /* special_function */
1395 "R_ARM_TLS_DESCSEQ", /* name */
1396 FALSE, /* partial_inplace */
1397 0x00000000, /* src_mask */
1398 0x00000000, /* dst_mask */
1399 FALSE), /* pcrel_offset */
1400
1401 HOWTO (R_ARM_THM_TLS_CALL, /* type */
1402 0, /* rightshift */
1403 2, /* size (0 = byte, 1 = short, 2 = long) */
1404 24, /* bitsize */
1405 FALSE, /* pc_relative */
1406 0, /* bitpos */
1407 complain_overflow_dont,/* complain_on_overflow */
1408 bfd_elf_generic_reloc, /* special_function */
1409 "R_ARM_THM_TLS_CALL", /* name */
1410 FALSE, /* partial_inplace */
1411 0x07ff07ff, /* src_mask */
1412 0x07ff07ff, /* dst_mask */
1413 FALSE), /* pcrel_offset */
c19d1205
ZW		 1414
1415 HOWTO (R_ARM_PLT32_ABS, /* type */
1416 0, /* rightshift */
1417 2, /* size (0 = byte, 1 = short, 2 = long) */
1418 32, /* bitsize */
1419 FALSE, /* pc_relative */
1420 0, /* bitpos */
1421 complain_overflow_dont,/* complain_on_overflow */
1422 bfd_elf_generic_reloc, /* special_function */
1423 "R_ARM_PLT32_ABS", /* name */
1424 FALSE, /* partial_inplace */
1425 0xffffffff, /* src_mask */
1426 0xffffffff, /* dst_mask */
1427 FALSE), /* pcrel_offset */
1428
1429 HOWTO (R_ARM_GOT_ABS, /* type */
1430 0, /* rightshift */
1431 2, /* size (0 = byte, 1 = short, 2 = long) */
1432 32, /* bitsize */
1433 FALSE, /* pc_relative */
1434 0, /* bitpos */
1435 complain_overflow_dont,/* complain_on_overflow */
1436 bfd_elf_generic_reloc, /* special_function */
1437 "R_ARM_GOT_ABS", /* name */
1438 FALSE, /* partial_inplace */
1439 0xffffffff, /* src_mask */
1440 0xffffffff, /* dst_mask */
1441 FALSE), /* pcrel_offset */
1442
1443 HOWTO (R_ARM_GOT_PREL, /* type */
1444 0, /* rightshift */
1445 2, /* size (0 = byte, 1 = short, 2 = long) */
1446 32, /* bitsize */
1447 TRUE, /* pc_relative */
1448 0, /* bitpos */
1449 complain_overflow_dont, /* complain_on_overflow */
1450 bfd_elf_generic_reloc, /* special_function */
1451 "R_ARM_GOT_PREL", /* name */
1452 FALSE, /* partial_inplace */
1453 0xffffffff, /* src_mask */
1454 0xffffffff, /* dst_mask */
1455 TRUE), /* pcrel_offset */
1456
1457 HOWTO (R_ARM_GOT_BREL12, /* type */
1458 0, /* rightshift */
1459 2, /* size (0 = byte, 1 = short, 2 = long) */
1460 12, /* bitsize */
1461 FALSE, /* pc_relative */
1462 0, /* bitpos */
1463 complain_overflow_bitfield,/* complain_on_overflow */
1464 bfd_elf_generic_reloc, /* special_function */
1465 "R_ARM_GOT_BREL12", /* name */
1466 FALSE, /* partial_inplace */
1467 0x00000fff, /* src_mask */
1468 0x00000fff, /* dst_mask */
1469 FALSE), /* pcrel_offset */
1470
1471 HOWTO (R_ARM_GOTOFF12, /* type */
1472 0, /* rightshift */
1473 2, /* size (0 = byte, 1 = short, 2 = long) */
1474 12, /* bitsize */
1475 FALSE, /* pc_relative */
1476 0, /* bitpos */
1477 complain_overflow_bitfield,/* complain_on_overflow */
1478 bfd_elf_generic_reloc, /* special_function */
1479 "R_ARM_GOTOFF12", /* name */
1480 FALSE, /* partial_inplace */
1481 0x00000fff, /* src_mask */
1482 0x00000fff, /* dst_mask */
1483 FALSE), /* pcrel_offset */
1484
1485 EMPTY_HOWTO (R_ARM_GOTRELAX), /* reserved for future GOT-load optimizations */
1486
1487 /* GNU extension to record C++ vtable member usage */
1488 HOWTO (R_ARM_GNU_VTENTRY, /* type */
99059e56
RM		 1489 0, /* rightshift */
1490 2, /* size (0 = byte, 1 = short, 2 = long) */
1491 0, /* bitsize */
1492 FALSE, /* pc_relative */
1493 0, /* bitpos */
1494 complain_overflow_dont, /* complain_on_overflow */
1495 _bfd_elf_rel_vtable_reloc_fn, /* special_function */
1496 "R_ARM_GNU_VTENTRY", /* name */
1497 FALSE, /* partial_inplace */
1498 0, /* src_mask */
1499 0, /* dst_mask */
1500 FALSE), /* pcrel_offset */
c19d1205
ZW		 1501
1502 /* GNU extension to record C++ vtable hierarchy */
1503 HOWTO (R_ARM_GNU_VTINHERIT, /* type */
99059e56
RM		 1504 0, /* rightshift */
1505 2, /* size (0 = byte, 1 = short, 2 = long) */
1506 0, /* bitsize */
1507 FALSE, /* pc_relative */
1508 0, /* bitpos */
1509 complain_overflow_dont, /* complain_on_overflow */
1510 NULL, /* special_function */
1511 "R_ARM_GNU_VTINHERIT", /* name */
1512 FALSE, /* partial_inplace */
1513 0, /* src_mask */
1514 0, /* dst_mask */
1515 FALSE), /* pcrel_offset */
c19d1205
ZW		 1516
1517 HOWTO (R_ARM_THM_JUMP11, /* type */
1518 1, /* rightshift */
1519 1, /* size (0 = byte, 1 = short, 2 = long) */
1520 11, /* bitsize */
1521 TRUE, /* pc_relative */
1522 0, /* bitpos */
1523 complain_overflow_signed, /* complain_on_overflow */
1524 bfd_elf_generic_reloc, /* special_function */
1525 "R_ARM_THM_JUMP11", /* name */
1526 FALSE, /* partial_inplace */
1527 0x000007ff, /* src_mask */
1528 0x000007ff, /* dst_mask */
1529 TRUE), /* pcrel_offset */
1530
1531 HOWTO (R_ARM_THM_JUMP8, /* type */
1532 1, /* rightshift */
1533 1, /* size (0 = byte, 1 = short, 2 = long) */
1534 8, /* bitsize */
1535 TRUE, /* pc_relative */
1536 0, /* bitpos */
1537 complain_overflow_signed, /* complain_on_overflow */
1538 bfd_elf_generic_reloc, /* special_function */
1539 "R_ARM_THM_JUMP8", /* name */
1540 FALSE, /* partial_inplace */
1541 0x000000ff, /* src_mask */
1542 0x000000ff, /* dst_mask */
1543 TRUE), /* pcrel_offset */
ba93b8ac 1544
c19d1205
ZW		 1545 /* TLS relocations */
1546 HOWTO (R_ARM_TLS_GD32, /* type */
99059e56
RM		 1547 0, /* rightshift */
1548 2, /* size (0 = byte, 1 = short, 2 = long) */
1549 32, /* bitsize */
1550 FALSE, /* pc_relative */
1551 0, /* bitpos */
1552 complain_overflow_bitfield,/* complain_on_overflow */
1553 NULL, /* special_function */
1554 "R_ARM_TLS_GD32", /* name */
1555 TRUE, /* partial_inplace */
1556 0xffffffff, /* src_mask */
1557 0xffffffff, /* dst_mask */
1558 FALSE), /* pcrel_offset */
ba93b8ac 1559
ba93b8ac 1560 HOWTO (R_ARM_TLS_LDM32, /* type */
99059e56
RM		 1561 0, /* rightshift */
1562 2, /* size (0 = byte, 1 = short, 2 = long) */
1563 32, /* bitsize */
1564 FALSE, /* pc_relative */
1565 0, /* bitpos */
1566 complain_overflow_bitfield,/* complain_on_overflow */
1567 bfd_elf_generic_reloc, /* special_function */
1568 "R_ARM_TLS_LDM32", /* name */
1569 TRUE, /* partial_inplace */
1570 0xffffffff, /* src_mask */
1571 0xffffffff, /* dst_mask */
1572 FALSE), /* pcrel_offset */
ba93b8ac 1573
c19d1205 1574 HOWTO (R_ARM_TLS_LDO32, /* type */
99059e56
RM		 1575 0, /* rightshift */
1576 2, /* size (0 = byte, 1 = short, 2 = long) */
1577 32, /* bitsize */
1578 FALSE, /* pc_relative */
1579 0, /* bitpos */
1580 complain_overflow_bitfield,/* complain_on_overflow */
1581 bfd_elf_generic_reloc, /* special_function */
1582 "R_ARM_TLS_LDO32", /* name */
1583 TRUE, /* partial_inplace */
1584 0xffffffff, /* src_mask */
1585 0xffffffff, /* dst_mask */
1586 FALSE), /* pcrel_offset */
ba93b8ac 1587
ba93b8ac 1588 HOWTO (R_ARM_TLS_IE32, /* type */
99059e56
RM		 1589 0, /* rightshift */
1590 2, /* size (0 = byte, 1 = short, 2 = long) */
1591 32, /* bitsize */
1592 FALSE, /* pc_relative */
1593 0, /* bitpos */
1594 complain_overflow_bitfield,/* complain_on_overflow */
1595 NULL, /* special_function */
1596 "R_ARM_TLS_IE32", /* name */
1597 TRUE, /* partial_inplace */
1598 0xffffffff, /* src_mask */
1599 0xffffffff, /* dst_mask */
1600 FALSE), /* pcrel_offset */
7f266840 1601
c19d1205 1602 HOWTO (R_ARM_TLS_LE32, /* type */
99059e56
RM		 1603 0, /* rightshift */
1604 2, /* size (0 = byte, 1 = short, 2 = long) */
1605 32, /* bitsize */
1606 FALSE, /* pc_relative */
1607 0, /* bitpos */
1608 complain_overflow_bitfield,/* complain_on_overflow */
75c11999 1609 NULL, /* special_function */
99059e56
RM		 1610 "R_ARM_TLS_LE32", /* name */
1611 TRUE, /* partial_inplace */
1612 0xffffffff, /* src_mask */
1613 0xffffffff, /* dst_mask */
1614 FALSE), /* pcrel_offset */
7f266840 1615
c19d1205
ZW		 1616 HOWTO (R_ARM_TLS_LDO12, /* type */
1617 0, /* rightshift */
1618 2, /* size (0 = byte, 1 = short, 2 = long) */
1619 12, /* bitsize */
1620 FALSE, /* pc_relative */
7f266840 1621 0, /* bitpos */
c19d1205 1622 complain_overflow_bitfield,/* complain_on_overflow */
7f266840 1623 bfd_elf_generic_reloc, /* special_function */
c19d1205 1624 "R_ARM_TLS_LDO12", /* name */
7f266840 1625 FALSE, /* partial_inplace */
c19d1205
ZW		 1626 0x00000fff, /* src_mask */
1627 0x00000fff, /* dst_mask */
1628 FALSE), /* pcrel_offset */
7f266840 1629
c19d1205
ZW		 1630 HOWTO (R_ARM_TLS_LE12, /* type */
1631 0, /* rightshift */
1632 2, /* size (0 = byte, 1 = short, 2 = long) */
1633 12, /* bitsize */
1634 FALSE, /* pc_relative */
7f266840 1635 0, /* bitpos */
c19d1205 1636 complain_overflow_bitfield,/* complain_on_overflow */
7f266840 1637 bfd_elf_generic_reloc, /* special_function */
c19d1205 1638 "R_ARM_TLS_LE12", /* name */
7f266840 1639 FALSE, /* partial_inplace */
c19d1205
ZW		 1640 0x00000fff, /* src_mask */
1641 0x00000fff, /* dst_mask */
1642 FALSE), /* pcrel_offset */
7f266840 1643
c19d1205 1644 HOWTO (R_ARM_TLS_IE12GP, /* type */
7f266840
DJ		 1645 0, /* rightshift */
1646 2, /* size (0 = byte, 1 = short, 2 = long) */
c19d1205
ZW		 1647 12, /* bitsize */
1648 FALSE, /* pc_relative */
7f266840 1649 0, /* bitpos */
c19d1205 1650 complain_overflow_bitfield,/* complain_on_overflow */
7f266840 1651 bfd_elf_generic_reloc, /* special_function */
c19d1205 1652 "R_ARM_TLS_IE12GP", /* name */
7f266840 1653 FALSE, /* partial_inplace */
c19d1205
ZW		 1654 0x00000fff, /* src_mask */
1655 0x00000fff, /* dst_mask */
1656 FALSE), /* pcrel_offset */
0855e32b 1657
34e77a92 1658 /* 112-127 private relocations. */
0855e32b
NS		 1659 EMPTY_HOWTO (112),
1660 EMPTY_HOWTO (113),
1661 EMPTY_HOWTO (114),
1662 EMPTY_HOWTO (115),
1663 EMPTY_HOWTO (116),
1664 EMPTY_HOWTO (117),
1665 EMPTY_HOWTO (118),
1666 EMPTY_HOWTO (119),
1667 EMPTY_HOWTO (120),
1668 EMPTY_HOWTO (121),
1669 EMPTY_HOWTO (122),
1670 EMPTY_HOWTO (123),
1671 EMPTY_HOWTO (124),
1672 EMPTY_HOWTO (125),
1673 EMPTY_HOWTO (126),
1674 EMPTY_HOWTO (127),
34e77a92
RS		 1675
1676 /* R_ARM_ME_TOO, obsolete. */
0855e32b
NS		 1677 EMPTY_HOWTO (128),
1678
1679 HOWTO (R_ARM_THM_TLS_DESCSEQ, /* type */
1680 0, /* rightshift */
1681 1, /* size (0 = byte, 1 = short, 2 = long) */
1682 0, /* bitsize */
1683 FALSE, /* pc_relative */
1684 0, /* bitpos */
1685 complain_overflow_bitfield,/* complain_on_overflow */
1686 bfd_elf_generic_reloc, /* special_function */
1687 "R_ARM_THM_TLS_DESCSEQ",/* name */
1688 FALSE, /* partial_inplace */
1689 0x00000000, /* src_mask */
1690 0x00000000, /* dst_mask */
1691 FALSE), /* pcrel_offset */
72d98d16
MG		 1692 EMPTY_HOWTO (130),
1693 EMPTY_HOWTO (131),
1694 HOWTO (R_ARM_THM_ALU_ABS_G0_NC,/* type. */
1695 0, /* rightshift. */
1696 1, /* size (0 = byte, 1 = short, 2 = long). */
1697 16, /* bitsize. */
1698 FALSE, /* pc_relative. */
1699 0, /* bitpos. */
1700 complain_overflow_bitfield,/* complain_on_overflow. */
1701 bfd_elf_generic_reloc, /* special_function. */
1702 "R_ARM_THM_ALU_ABS_G0_NC",/* name. */
1703 FALSE, /* partial_inplace. */
1704 0x00000000, /* src_mask. */
1705 0x00000000, /* dst_mask. */
1706 FALSE), /* pcrel_offset. */
1707 HOWTO (R_ARM_THM_ALU_ABS_G1_NC,/* type. */
1708 0, /* rightshift. */
1709 1, /* size (0 = byte, 1 = short, 2 = long). */
1710 16, /* bitsize. */
1711 FALSE, /* pc_relative. */
1712 0, /* bitpos. */
1713 complain_overflow_bitfield,/* complain_on_overflow. */
1714 bfd_elf_generic_reloc, /* special_function. */
1715 "R_ARM_THM_ALU_ABS_G1_NC",/* name. */
1716 FALSE, /* partial_inplace. */
1717 0x00000000, /* src_mask. */
1718 0x00000000, /* dst_mask. */
1719 FALSE), /* pcrel_offset. */
1720 HOWTO (R_ARM_THM_ALU_ABS_G2_NC,/* type. */
1721 0, /* rightshift. */
1722 1, /* size (0 = byte, 1 = short, 2 = long). */
1723 16, /* bitsize. */
1724 FALSE, /* pc_relative. */
1725 0, /* bitpos. */
1726 complain_overflow_bitfield,/* complain_on_overflow. */
1727 bfd_elf_generic_reloc, /* special_function. */
1728 "R_ARM_THM_ALU_ABS_G2_NC",/* name. */
1729 FALSE, /* partial_inplace. */
1730 0x00000000, /* src_mask. */
1731 0x00000000, /* dst_mask. */
1732 FALSE), /* pcrel_offset. */
1733 HOWTO (R_ARM_THM_ALU_ABS_G3_NC,/* type. */
1734 0, /* rightshift. */
1735 1, /* size (0 = byte, 1 = short, 2 = long). */
1736 16, /* bitsize. */
1737 FALSE, /* pc_relative. */
1738 0, /* bitpos. */
1739 complain_overflow_bitfield,/* complain_on_overflow. */
1740 bfd_elf_generic_reloc, /* special_function. */
1741 "R_ARM_THM_ALU_ABS_G3_NC",/* name. */
1742 FALSE, /* partial_inplace. */
1743 0x00000000, /* src_mask. */
1744 0x00000000, /* dst_mask. */
1745 FALSE), /* pcrel_offset. */
c19d1205
ZW		 1746};
1747
34e77a92
RS		 1748/* 160 onwards: */
1749static reloc_howto_type elf32_arm_howto_table_2[1] =
1750{
1751 HOWTO (R_ARM_IRELATIVE, /* type */
99059e56
RM		 1752 0, /* rightshift */
1753 2, /* size (0 = byte, 1 = short, 2 = long) */
1754 32, /* bitsize */
1755 FALSE, /* pc_relative */
1756 0, /* bitpos */
1757 complain_overflow_bitfield,/* complain_on_overflow */
1758 bfd_elf_generic_reloc, /* special_function */
1759 "R_ARM_IRELATIVE", /* name */
1760 TRUE, /* partial_inplace */
1761 0xffffffff, /* src_mask */
1762 0xffffffff, /* dst_mask */
1763 FALSE) /* pcrel_offset */
34e77a92 1764};
c19d1205 1765
34e77a92
RS		 1766/* 249-255 extended, currently unused, relocations: */
1767static reloc_howto_type elf32_arm_howto_table_3[4] =
7f266840
DJ		 1768{
1769 HOWTO (R_ARM_RREL32, /* type */
1770 0, /* rightshift */
1771 0, /* size (0 = byte, 1 = short, 2 = long) */
1772 0, /* bitsize */
1773 FALSE, /* pc_relative */
1774 0, /* bitpos */
1775 complain_overflow_dont,/* complain_on_overflow */
1776 bfd_elf_generic_reloc, /* special_function */
1777 "R_ARM_RREL32", /* name */
1778 FALSE, /* partial_inplace */
1779 0, /* src_mask */
1780 0, /* dst_mask */
1781 FALSE), /* pcrel_offset */
1782
1783 HOWTO (R_ARM_RABS32, /* type */
1784 0, /* rightshift */
1785 0, /* size (0 = byte, 1 = short, 2 = long) */
1786 0, /* bitsize */
1787 FALSE, /* pc_relative */
1788 0, /* bitpos */
1789 complain_overflow_dont,/* complain_on_overflow */
1790 bfd_elf_generic_reloc, /* special_function */
1791 "R_ARM_RABS32", /* name */
1792 FALSE, /* partial_inplace */
1793 0, /* src_mask */
1794 0, /* dst_mask */
1795 FALSE), /* pcrel_offset */
1796
1797 HOWTO (R_ARM_RPC24, /* type */
1798 0, /* rightshift */
1799 0, /* size (0 = byte, 1 = short, 2 = long) */
1800 0, /* bitsize */
1801 FALSE, /* pc_relative */
1802 0, /* bitpos */
1803 complain_overflow_dont,/* complain_on_overflow */
1804 bfd_elf_generic_reloc, /* special_function */
1805 "R_ARM_RPC24", /* name */
1806 FALSE, /* partial_inplace */
1807 0, /* src_mask */
1808 0, /* dst_mask */
1809 FALSE), /* pcrel_offset */
1810
1811 HOWTO (R_ARM_RBASE, /* type */
1812 0, /* rightshift */
1813 0, /* size (0 = byte, 1 = short, 2 = long) */
1814 0, /* bitsize */
1815 FALSE, /* pc_relative */
1816 0, /* bitpos */
1817 complain_overflow_dont,/* complain_on_overflow */
1818 bfd_elf_generic_reloc, /* special_function */
1819 "R_ARM_RBASE", /* name */
1820 FALSE, /* partial_inplace */
1821 0, /* src_mask */
1822 0, /* dst_mask */
1823 FALSE) /* pcrel_offset */
1824};
1825
1826static reloc_howto_type *
1827elf32_arm_howto_from_type (unsigned int r_type)
1828{
906e58ca 1829 if (r_type < ARRAY_SIZE (elf32_arm_howto_table_1))
c19d1205 1830 return &elf32_arm_howto_table_1[r_type];
ba93b8ac 1831
34e77a92
RS		 1832 if (r_type == R_ARM_IRELATIVE)
1833 return &elf32_arm_howto_table_2[r_type - R_ARM_IRELATIVE];
1834
c19d1205 1835 if (r_type >= R_ARM_RREL32
34e77a92
RS		 1836 && r_type < R_ARM_RREL32 + ARRAY_SIZE (elf32_arm_howto_table_3))
1837 return &elf32_arm_howto_table_3[r_type - R_ARM_RREL32];
7f266840 1838
c19d1205 1839 return NULL;
7f266840
DJ		 1840}
1841
1842static void
1843elf32_arm_info_to_howto (bfd * abfd ATTRIBUTE_UNUSED, arelent * bfd_reloc,
1844 Elf_Internal_Rela * elf_reloc)
1845{
1846 unsigned int r_type;
1847
1848 r_type = ELF32_R_TYPE (elf_reloc->r_info);
1849 bfd_reloc->howto = elf32_arm_howto_from_type (r_type);
1850}
1851
1852struct elf32_arm_reloc_map
1853 {
1854 bfd_reloc_code_real_type bfd_reloc_val;
1855 unsigned char elf_reloc_val;
1856 };
1857
1858/* All entries in this list must also be present in elf32_arm_howto_table. */
1859static const struct elf32_arm_reloc_map elf32_arm_reloc_map[] =
1860 {
1861 {BFD_RELOC_NONE, R_ARM_NONE},
1862 {BFD_RELOC_ARM_PCREL_BRANCH, R_ARM_PC24},
39b41c9c
PB		 1863 {BFD_RELOC_ARM_PCREL_CALL, R_ARM_CALL},
1864 {BFD_RELOC_ARM_PCREL_JUMP, R_ARM_JUMP24},
7f266840
DJ		 1865 {BFD_RELOC_ARM_PCREL_BLX, R_ARM_XPC25},
1866 {BFD_RELOC_THUMB_PCREL_BLX, R_ARM_THM_XPC22},
1867 {BFD_RELOC_32, R_ARM_ABS32},
1868 {BFD_RELOC_32_PCREL, R_ARM_REL32},
1869 {BFD_RELOC_8, R_ARM_ABS8},
1870 {BFD_RELOC_16, R_ARM_ABS16},
1871 {BFD_RELOC_ARM_OFFSET_IMM, R_ARM_ABS12},
1872 {BFD_RELOC_ARM_THUMB_OFFSET, R_ARM_THM_ABS5},
c19d1205
ZW		 1873 {BFD_RELOC_THUMB_PCREL_BRANCH25, R_ARM_THM_JUMP24},
1874 {BFD_RELOC_THUMB_PCREL_BRANCH23, R_ARM_THM_CALL},
1875 {BFD_RELOC_THUMB_PCREL_BRANCH12, R_ARM_THM_JUMP11},
1876 {BFD_RELOC_THUMB_PCREL_BRANCH20, R_ARM_THM_JUMP19},
1877 {BFD_RELOC_THUMB_PCREL_BRANCH9, R_ARM_THM_JUMP8},
1878 {BFD_RELOC_THUMB_PCREL_BRANCH7, R_ARM_THM_JUMP6},
7f266840
DJ		 1879 {BFD_RELOC_ARM_GLOB_DAT, R_ARM_GLOB_DAT},
1880 {BFD_RELOC_ARM_JUMP_SLOT, R_ARM_JUMP_SLOT},
1881 {BFD_RELOC_ARM_RELATIVE, R_ARM_RELATIVE},
c19d1205 1882 {BFD_RELOC_ARM_GOTOFF, R_ARM_GOTOFF32},
7f266840 1883 {BFD_RELOC_ARM_GOTPC, R_ARM_GOTPC},
b43420e6 1884 {BFD_RELOC_ARM_GOT_PREL, R_ARM_GOT_PREL},
7f266840
DJ		 1885 {BFD_RELOC_ARM_GOT32, R_ARM_GOT32},
1886 {BFD_RELOC_ARM_PLT32, R_ARM_PLT32},
1887 {BFD_RELOC_ARM_TARGET1, R_ARM_TARGET1},
1888 {BFD_RELOC_ARM_ROSEGREL32, R_ARM_ROSEGREL32},
1889 {BFD_RELOC_ARM_SBREL32, R_ARM_SBREL32},
1890 {BFD_RELOC_ARM_PREL31, R_ARM_PREL31},
ba93b8ac
DJ		 1891 {BFD_RELOC_ARM_TARGET2, R_ARM_TARGET2},
1892 {BFD_RELOC_ARM_PLT32, R_ARM_PLT32},
0855e32b
NS		 1893 {BFD_RELOC_ARM_TLS_GOTDESC, R_ARM_TLS_GOTDESC},
1894 {BFD_RELOC_ARM_TLS_CALL, R_ARM_TLS_CALL},
1895 {BFD_RELOC_ARM_THM_TLS_CALL, R_ARM_THM_TLS_CALL},
1896 {BFD_RELOC_ARM_TLS_DESCSEQ, R_ARM_TLS_DESCSEQ},
1897 {BFD_RELOC_ARM_THM_TLS_DESCSEQ, R_ARM_THM_TLS_DESCSEQ},
1898 {BFD_RELOC_ARM_TLS_DESC, R_ARM_TLS_DESC},
ba93b8ac
DJ		 1899 {BFD_RELOC_ARM_TLS_GD32, R_ARM_TLS_GD32},
1900 {BFD_RELOC_ARM_TLS_LDO32, R_ARM_TLS_LDO32},
1901 {BFD_RELOC_ARM_TLS_LDM32, R_ARM_TLS_LDM32},
1902 {BFD_RELOC_ARM_TLS_DTPMOD32, R_ARM_TLS_DTPMOD32},
1903 {BFD_RELOC_ARM_TLS_DTPOFF32, R_ARM_TLS_DTPOFF32},
1904 {BFD_RELOC_ARM_TLS_TPOFF32, R_ARM_TLS_TPOFF32},
1905 {BFD_RELOC_ARM_TLS_IE32, R_ARM_TLS_IE32},
1906 {BFD_RELOC_ARM_TLS_LE32, R_ARM_TLS_LE32},
34e77a92 1907 {BFD_RELOC_ARM_IRELATIVE, R_ARM_IRELATIVE},
c19d1205
ZW		 1908 {BFD_RELOC_VTABLE_INHERIT, R_ARM_GNU_VTINHERIT},
1909 {BFD_RELOC_VTABLE_ENTRY, R_ARM_GNU_VTENTRY},
b6895b4f
PB		 1910 {BFD_RELOC_ARM_MOVW, R_ARM_MOVW_ABS_NC},
1911 {BFD_RELOC_ARM_MOVT, R_ARM_MOVT_ABS},
1912 {BFD_RELOC_ARM_MOVW_PCREL, R_ARM_MOVW_PREL_NC},
1913 {BFD_RELOC_ARM_MOVT_PCREL, R_ARM_MOVT_PREL},
1914 {BFD_RELOC_ARM_THUMB_MOVW, R_ARM_THM_MOVW_ABS_NC},
1915 {BFD_RELOC_ARM_THUMB_MOVT, R_ARM_THM_MOVT_ABS},
1916 {BFD_RELOC_ARM_THUMB_MOVW_PCREL, R_ARM_THM_MOVW_PREL_NC},
1917 {BFD_RELOC_ARM_THUMB_MOVT_PCREL, R_ARM_THM_MOVT_PREL},
4962c51a
MS		 1918 {BFD_RELOC_ARM_ALU_PC_G0_NC, R_ARM_ALU_PC_G0_NC},
1919 {BFD_RELOC_ARM_ALU_PC_G0, R_ARM_ALU_PC_G0},
1920 {BFD_RELOC_ARM_ALU_PC_G1_NC, R_ARM_ALU_PC_G1_NC},
1921 {BFD_RELOC_ARM_ALU_PC_G1, R_ARM_ALU_PC_G1},
1922 {BFD_RELOC_ARM_ALU_PC_G2, R_ARM_ALU_PC_G2},
1923 {BFD_RELOC_ARM_LDR_PC_G0, R_ARM_LDR_PC_G0},
1924 {BFD_RELOC_ARM_LDR_PC_G1, R_ARM_LDR_PC_G1},
1925 {BFD_RELOC_ARM_LDR_PC_G2, R_ARM_LDR_PC_G2},
1926 {BFD_RELOC_ARM_LDRS_PC_G0, R_ARM_LDRS_PC_G0},
1927 {BFD_RELOC_ARM_LDRS_PC_G1, R_ARM_LDRS_PC_G1},
1928 {BFD_RELOC_ARM_LDRS_PC_G2, R_ARM_LDRS_PC_G2},
1929 {BFD_RELOC_ARM_LDC_PC_G0, R_ARM_LDC_PC_G0},
1930 {BFD_RELOC_ARM_LDC_PC_G1, R_ARM_LDC_PC_G1},
1931 {BFD_RELOC_ARM_LDC_PC_G2, R_ARM_LDC_PC_G2},
1932 {BFD_RELOC_ARM_ALU_SB_G0_NC, R_ARM_ALU_SB_G0_NC},
1933 {BFD_RELOC_ARM_ALU_SB_G0, R_ARM_ALU_SB_G0},
1934 {BFD_RELOC_ARM_ALU_SB_G1_NC, R_ARM_ALU_SB_G1_NC},
1935 {BFD_RELOC_ARM_ALU_SB_G1, R_ARM_ALU_SB_G1},
1936 {BFD_RELOC_ARM_ALU_SB_G2, R_ARM_ALU_SB_G2},
1937 {BFD_RELOC_ARM_LDR_SB_G0, R_ARM_LDR_SB_G0},
1938 {BFD_RELOC_ARM_LDR_SB_G1, R_ARM_LDR_SB_G1},
1939 {BFD_RELOC_ARM_LDR_SB_G2, R_ARM_LDR_SB_G2},
1940 {BFD_RELOC_ARM_LDRS_SB_G0, R_ARM_LDRS_SB_G0},
1941 {BFD_RELOC_ARM_LDRS_SB_G1, R_ARM_LDRS_SB_G1},
1942 {BFD_RELOC_ARM_LDRS_SB_G2, R_ARM_LDRS_SB_G2},
1943 {BFD_RELOC_ARM_LDC_SB_G0, R_ARM_LDC_SB_G0},
1944 {BFD_RELOC_ARM_LDC_SB_G1, R_ARM_LDC_SB_G1},
845b51d6 1945 {BFD_RELOC_ARM_LDC_SB_G2, R_ARM_LDC_SB_G2},
72d98d16
MG		 1946 {BFD_RELOC_ARM_V4BX, R_ARM_V4BX},
1947 {BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC, R_ARM_THM_ALU_ABS_G3_NC},
1948 {BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC, R_ARM_THM_ALU_ABS_G2_NC},
1949 {BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC, R_ARM_THM_ALU_ABS_G1_NC},
1950 {BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC, R_ARM_THM_ALU_ABS_G0_NC}
7f266840
DJ		 1951 };
1952
1953static reloc_howto_type *
f1c71a59
ZW		 1954elf32_arm_reloc_type_lookup (bfd *abfd ATTRIBUTE_UNUSED,
1955 bfd_reloc_code_real_type code)
7f266840
DJ		 1956{
1957 unsigned int i;
8029a119 1958
906e58ca 1959 for (i = 0; i < ARRAY_SIZE (elf32_arm_reloc_map); i ++)
c19d1205
ZW		 1960 if (elf32_arm_reloc_map[i].bfd_reloc_val == code)
1961 return elf32_arm_howto_from_type (elf32_arm_reloc_map[i].elf_reloc_val);
7f266840 1962
c19d1205 1963 return NULL;
7f266840
DJ		 1964}
1965
157090f7
AM		 1966static reloc_howto_type *
1967elf32_arm_reloc_name_lookup (bfd *abfd ATTRIBUTE_UNUSED,
1968 const char *r_name)
1969{
1970 unsigned int i;
1971
906e58ca 1972 for (i = 0; i < ARRAY_SIZE (elf32_arm_howto_table_1); i++)
157090f7
AM		 1973 if (elf32_arm_howto_table_1[i].name != NULL
1974 && strcasecmp (elf32_arm_howto_table_1[i].name, r_name) == 0)
1975 return &elf32_arm_howto_table_1[i];
1976
906e58ca 1977 for (i = 0; i < ARRAY_SIZE (elf32_arm_howto_table_2); i++)
157090f7
AM		 1978 if (elf32_arm_howto_table_2[i].name != NULL
1979 && strcasecmp (elf32_arm_howto_table_2[i].name, r_name) == 0)
1980 return &elf32_arm_howto_table_2[i];
1981
34e77a92
RS		 1982 for (i = 0; i < ARRAY_SIZE (elf32_arm_howto_table_3); i++)
1983 if (elf32_arm_howto_table_3[i].name != NULL
1984 && strcasecmp (elf32_arm_howto_table_3[i].name, r_name) == 0)
1985 return &elf32_arm_howto_table_3[i];
1986
157090f7
AM		 1987 return NULL;
1988}
1989
906e58ca
NC		 1990/* Support for core dump NOTE sections. */
1991
7f266840 1992static bfd_boolean
f1c71a59 1993elf32_arm_nabi_grok_prstatus (bfd *abfd, Elf_Internal_Note *note)
7f266840
DJ		 1994{
1995 int offset;
1996 size_t size;
1997
1998 switch (note->descsz)
1999 {
2000 default:
2001 return FALSE;
2002
8029a119 2003 case 148: /* Linux/ARM 32-bit. */
7f266840 2004 /* pr_cursig */
228e534f 2005 elf_tdata (abfd)->core->signal = bfd_get_16 (abfd, note->descdata + 12);
7f266840
DJ		 2006
2007 /* pr_pid */
228e534f 2008 elf_tdata (abfd)->core->lwpid = bfd_get_32 (abfd, note->descdata + 24);
7f266840
DJ		 2009
2010 /* pr_reg */
2011 offset = 72;
2012 size = 72;
2013
2014 break;
2015 }
2016
2017 /* Make a ".reg/999" section. */
2018 return _bfd_elfcore_make_pseudosection (abfd, ".reg",
2019 size, note->descpos + offset);
2020}
2021
2022static bfd_boolean
f1c71a59 2023elf32_arm_nabi_grok_psinfo (bfd *abfd, Elf_Internal_Note *note)
7f266840
DJ		 2024{
2025 switch (note->descsz)
2026 {
2027 default:
2028 return FALSE;
2029
8029a119 2030 case 124: /* Linux/ARM elf_prpsinfo. */
228e534f 2031 elf_tdata (abfd)->core->pid
4395ee08 2032 = bfd_get_32 (abfd, note->descdata + 12);
228e534f 2033 elf_tdata (abfd)->core->program
7f266840 2034 = _bfd_elfcore_strndup (abfd, note->descdata + 28, 16);
228e534f 2035 elf_tdata (abfd)->core->command
7f266840
DJ		 2036 = _bfd_elfcore_strndup (abfd, note->descdata + 44, 80);
2037 }
2038
2039 /* Note that for some reason, a spurious space is tacked
2040 onto the end of the args in some (at least one anyway)
2041 implementations, so strip it off if it exists. */
7f266840 2042 {
228e534f 2043 char *command = elf_tdata (abfd)->core->command;
7f266840
DJ		 2044 int n = strlen (command);
2045
2046 if (0 < n && command[n - 1] == ' ')
2047 command[n - 1] = '\0';
2048 }
2049
2050 return TRUE;
2051}
2052
1f20dca5
UW		 2053static char *
2054elf32_arm_nabi_write_core_note (bfd *abfd, char *buf, int *bufsiz,
2055 int note_type, ...)
2056{
2057 switch (note_type)
2058 {
2059 default:
2060 return NULL;
2061
2062 case NT_PRPSINFO:
2063 {
2064 char data[124];
2065 va_list ap;
2066
2067 va_start (ap, note_type);
2068 memset (data, 0, sizeof (data));
2069 strncpy (data + 28, va_arg (ap, const char *), 16);
2070 strncpy (data + 44, va_arg (ap, const char *), 80);
2071 va_end (ap);
2072
2073 return elfcore_write_note (abfd, buf, bufsiz,
2074 "CORE", note_type, data, sizeof (data));
2075 }
2076
2077 case NT_PRSTATUS:
2078 {
2079 char data[148];
2080 va_list ap;
2081 long pid;
2082 int cursig;
2083 const void *greg;
2084
2085 va_start (ap, note_type);
2086 memset (data, 0, sizeof (data));
2087 pid = va_arg (ap, long);
2088 bfd_put_32 (abfd, pid, data + 24);
2089 cursig = va_arg (ap, int);
2090 bfd_put_16 (abfd, cursig, data + 12);
2091 greg = va_arg (ap, const void *);
2092 memcpy (data + 72, greg, 72);
2093 va_end (ap);
2094
2095 return elfcore_write_note (abfd, buf, bufsiz,
2096 "CORE", note_type, data, sizeof (data));
2097 }
2098 }
2099}
2100
6d00b590 2101#define TARGET_LITTLE_SYM arm_elf32_le_vec
7f266840 2102#define TARGET_LITTLE_NAME "elf32-littlearm"
6d00b590 2103#define TARGET_BIG_SYM arm_elf32_be_vec
7f266840
DJ		 2104#define TARGET_BIG_NAME "elf32-bigarm"
2105
2106#define elf_backend_grok_prstatus elf32_arm_nabi_grok_prstatus
2107#define elf_backend_grok_psinfo elf32_arm_nabi_grok_psinfo
1f20dca5 2108#define elf_backend_write_core_note elf32_arm_nabi_write_core_note
7f266840 2109
252b5132
RH		 2110typedef unsigned long int insn32;
2111typedef unsigned short int insn16;
2112
3a4a14e9
PB		 2113/* In lieu of proper flags, assume all EABIv4 or later objects are
2114 interworkable. */
57e8b36a 2115#define INTERWORK_FLAG(abfd) \
3a4a14e9 2116 (EF_ARM_EABI_VERSION (elf_elfheader (abfd)->e_flags) >= EF_ARM_EABI_VER4 \
3e6b1042
DJ		 2117 || (elf_elfheader (abfd)->e_flags & EF_ARM_INTERWORK) \
2118 || ((abfd)->flags & BFD_LINKER_CREATED))
9b485d32 2119
252b5132
RH		 2120/* The linker script knows the section names for placement.
2121 The entry_names are used to do simple name mangling on the stubs.
2122 Given a function name, and its type, the stub can be found. The
9b485d32 2123 name can be changed. The only requirement is the %s be present. */
252b5132
RH		 2124#define THUMB2ARM_GLUE_SECTION_NAME ".glue_7t"
2125#define THUMB2ARM_GLUE_ENTRY_NAME "__%s_from_thumb"
2126
2127#define ARM2THUMB_GLUE_SECTION_NAME ".glue_7"
2128#define ARM2THUMB_GLUE_ENTRY_NAME "__%s_from_arm"
2129
c7b8f16e
JB		 2130#define VFP11_ERRATUM_VENEER_SECTION_NAME ".vfp11_veneer"
2131#define VFP11_ERRATUM_VENEER_ENTRY_NAME "__vfp11_veneer_%x"
2132
a504d23a
LA		 2133#define STM32L4XX_ERRATUM_VENEER_SECTION_NAME ".text.stm32l4xx_veneer"
2134#define STM32L4XX_ERRATUM_VENEER_ENTRY_NAME "__stm32l4xx_veneer_%x"
2135
845b51d6
PB		 2136#define ARM_BX_GLUE_SECTION_NAME ".v4_bx"
2137#define ARM_BX_GLUE_ENTRY_NAME "__bx_r%d"
2138
7413f23f
DJ		 2139#define STUB_ENTRY_NAME "__%s_veneer"
2140
4ba2ef8f
TP		 2141#define CMSE_PREFIX "__acle_se_"
2142
252b5132
RH		 2143/* The name of the dynamic interpreter. This is put in the .interp
2144 section. */
2145#define ELF_DYNAMIC_INTERPRETER "/usr/lib/ld.so.1"
2146
0855e32b 2147static const unsigned long tls_trampoline [] =
b38cadfb
NC		 2148{
2149 0xe08e0000, /* add r0, lr, r0 */
2150 0xe5901004, /* ldr r1, [r0,#4] */
2151 0xe12fff11, /* bx r1 */
2152};
0855e32b
NS		 2153
2154static const unsigned long dl_tlsdesc_lazy_trampoline [] =
b38cadfb
NC		 2155{
2156 0xe52d2004, /* push {r2} */
2157 0xe59f200c, /* ldr r2, [pc, #3f - . - 8] */
2158 0xe59f100c, /* ldr r1, [pc, #4f - . - 8] */
2159 0xe79f2002, /* 1: ldr r2, [pc, r2] */
2160 0xe081100f, /* 2: add r1, pc */
2161 0xe12fff12, /* bx r2 */
2162 0x00000014, /* 3: .word _GLOBAL_OFFSET_TABLE_ - 1b - 8
99059e56 2163 + dl_tlsdesc_lazy_resolver(GOT) */
b38cadfb
NC		 2164 0x00000018, /* 4: .word _GLOBAL_OFFSET_TABLE_ - 2b - 8 */
2165};
0855e32b 2166
5e681ec4
PB		 2167#ifdef FOUR_WORD_PLT
2168
252b5132
RH		 2169/* The first entry in a procedure linkage table looks like
2170 this. It is set up so that any shared library function that is
59f2c4e7 2171 called before the relocation has been set up calls the dynamic
9b485d32 2172 linker first. */
e5a52504 2173static const bfd_vma elf32_arm_plt0_entry [] =
b38cadfb
NC		 2174{
2175 0xe52de004, /* str lr, [sp, #-4]! */
2176 0xe59fe010, /* ldr lr, [pc, #16] */
2177 0xe08fe00e, /* add lr, pc, lr */
2178 0xe5bef008, /* ldr pc, [lr, #8]! */
2179};
5e681ec4
PB		 2180
2181/* Subsequent entries in a procedure linkage table look like
2182 this. */
e5a52504 2183static const bfd_vma elf32_arm_plt_entry [] =
b38cadfb
NC		 2184{
2185 0xe28fc600, /* add ip, pc, #NN */
2186 0xe28cca00, /* add ip, ip, #NN */
2187 0xe5bcf000, /* ldr pc, [ip, #NN]! */
2188 0x00000000, /* unused */
2189};
5e681ec4 2190
eed94f8f 2191#else /* not FOUR_WORD_PLT */
5e681ec4 2192
5e681ec4
PB		 2193/* The first entry in a procedure linkage table looks like
2194 this. It is set up so that any shared library function that is
2195 called before the relocation has been set up calls the dynamic
2196 linker first. */
e5a52504 2197static const bfd_vma elf32_arm_plt0_entry [] =
b38cadfb
NC		 2198{
2199 0xe52de004, /* str lr, [sp, #-4]! */
2200 0xe59fe004, /* ldr lr, [pc, #4] */
2201 0xe08fe00e, /* add lr, pc, lr */
2202 0xe5bef008, /* ldr pc, [lr, #8]! */
2203 0x00000000, /* &GOT[0] - . */
2204};
252b5132 2205
1db37fe6
YG		 2206/* By default subsequent entries in a procedure linkage table look like
2207 this. Offsets that don't fit into 28 bits will cause link error. */
2208static const bfd_vma elf32_arm_plt_entry_short [] =
b38cadfb
NC		 2209{
2210 0xe28fc600, /* add ip, pc, #0xNN00000 */
2211 0xe28cca00, /* add ip, ip, #0xNN000 */
2212 0xe5bcf000, /* ldr pc, [ip, #0xNNN]! */
2213};
5e681ec4 2214
1db37fe6
YG		 2215/* When explicitly asked, we'll use this "long" entry format
2216 which can cope with arbitrary displacements. */
2217static const bfd_vma elf32_arm_plt_entry_long [] =
2218{
2219 0xe28fc200, /* add ip, pc, #0xN0000000 */
2220 0xe28cc600, /* add ip, ip, #0xNN00000 */
2221 0xe28cca00, /* add ip, ip, #0xNN000 */
2222 0xe5bcf000, /* ldr pc, [ip, #0xNNN]! */
2223};
2224
2225static bfd_boolean elf32_arm_use_long_plt_entry = FALSE;
2226
eed94f8f
NC		 2227#endif /* not FOUR_WORD_PLT */
2228
2229/* The first entry in a procedure linkage table looks like this.
2230 It is set up so that any shared library function that is called before the
2231 relocation has been set up calls the dynamic linker first. */
2232static const bfd_vma elf32_thumb2_plt0_entry [] =
2233{
2234 /* NOTE: As this is a mixture of 16-bit and 32-bit instructions,
2235 an instruction maybe encoded to one or two array elements. */
2236 0xf8dfb500, /* push {lr} */
2237 0x44fee008, /* ldr.w lr, [pc, #8] */
469a3493 2238 /* add lr, pc */
eed94f8f
NC		 2239 0xff08f85e, /* ldr.w pc, [lr, #8]! */
2240 0x00000000, /* &GOT[0] - . */
2241};
2242
2243/* Subsequent entries in a procedure linkage table for thumb only target
2244 look like this. */
2245static const bfd_vma elf32_thumb2_plt_entry [] =
2246{
2247 /* NOTE: As this is a mixture of 16-bit and 32-bit instructions,
2248 an instruction maybe encoded to one or two array elements. */
2249 0x0c00f240, /* movw ip, #0xNNNN */
2250 0x0c00f2c0, /* movt ip, #0xNNNN */
2251 0xf8dc44fc, /* add ip, pc */
2252 0xbf00f000 /* ldr.w pc, [ip] */
469a3493 2253 /* nop */
eed94f8f 2254};
252b5132 2255
00a97672
RS		 2256/* The format of the first entry in the procedure linkage table
2257 for a VxWorks executable. */
2258static const bfd_vma elf32_arm_vxworks_exec_plt0_entry[] =
b38cadfb
NC		 2259{
2260 0xe52dc008, /* str ip,[sp,#-8]! */
2261 0xe59fc000, /* ldr ip,[pc] */
2262 0xe59cf008, /* ldr pc,[ip,#8] */
2263 0x00000000, /* .long _GLOBAL_OFFSET_TABLE_ */
2264};
00a97672
RS		 2265
2266/* The format of subsequent entries in a VxWorks executable. */
2267static const bfd_vma elf32_arm_vxworks_exec_plt_entry[] =
b38cadfb
NC		 2268{
2269 0xe59fc000, /* ldr ip,[pc] */
2270 0xe59cf000, /* ldr pc,[ip] */
2271 0x00000000, /* .long @got */
2272 0xe59fc000, /* ldr ip,[pc] */
2273 0xea000000, /* b _PLT */
2274 0x00000000, /* .long @pltindex*sizeof(Elf32_Rela) */
2275};
00a97672
RS		 2276
2277/* The format of entries in a VxWorks shared library. */
2278static const bfd_vma elf32_arm_vxworks_shared_plt_entry[] =
b38cadfb
NC		 2279{
2280 0xe59fc000, /* ldr ip,[pc] */
2281 0xe79cf009, /* ldr pc,[ip,r9] */
2282 0x00000000, /* .long @got */
2283 0xe59fc000, /* ldr ip,[pc] */
2284 0xe599f008, /* ldr pc,[r9,#8] */
2285 0x00000000, /* .long @pltindex*sizeof(Elf32_Rela) */
2286};
00a97672 2287
b7693d02
DJ		 2288/* An initial stub used if the PLT entry is referenced from Thumb code. */
2289#define PLT_THUMB_STUB_SIZE 4
2290static const bfd_vma elf32_arm_plt_thumb_stub [] =
b38cadfb
NC		 2291{
2292 0x4778, /* bx pc */
2293 0x46c0 /* nop */
2294};
b7693d02 2295
e5a52504
MM		 2296/* The entries in a PLT when using a DLL-based target with multiple
2297 address spaces. */
906e58ca 2298static const bfd_vma elf32_arm_symbian_plt_entry [] =
b38cadfb
NC		 2299{
2300 0xe51ff004, /* ldr pc, [pc, #-4] */
2301 0x00000000, /* dcd R_ARM_GLOB_DAT(X) */
2302};
2303
2304/* The first entry in a procedure linkage table looks like
2305 this. It is set up so that any shared library function that is
2306 called before the relocation has been set up calls the dynamic
2307 linker first. */
2308static const bfd_vma elf32_arm_nacl_plt0_entry [] =
2309{
2310 /* First bundle: */
2311 0xe300c000, /* movw ip, #:lower16:&GOT[2]-.+8 */
2312 0xe340c000, /* movt ip, #:upper16:&GOT[2]-.+8 */
2313 0xe08cc00f, /* add ip, ip, pc */
2314 0xe52dc008, /* str ip, [sp, #-8]! */
2315 /* Second bundle: */
edccdf7c
RM		 2316 0xe3ccc103, /* bic ip, ip, #0xc0000000 */
2317 0xe59cc000, /* ldr ip, [ip] */
b38cadfb 2318 0xe3ccc13f, /* bic ip, ip, #0xc000000f */
edccdf7c 2319 0xe12fff1c, /* bx ip */
b38cadfb 2320 /* Third bundle: */
edccdf7c
RM		 2321 0xe320f000, /* nop */
2322 0xe320f000, /* nop */
2323 0xe320f000, /* nop */
b38cadfb
NC		 2324 /* .Lplt_tail: */
2325 0xe50dc004, /* str ip, [sp, #-4] */
2326 /* Fourth bundle: */
edccdf7c
RM		 2327 0xe3ccc103, /* bic ip, ip, #0xc0000000 */
2328 0xe59cc000, /* ldr ip, [ip] */
b38cadfb 2329 0xe3ccc13f, /* bic ip, ip, #0xc000000f */
edccdf7c 2330 0xe12fff1c, /* bx ip */
b38cadfb
NC		 2331};
2332#define ARM_NACL_PLT_TAIL_OFFSET (11 * 4)
2333
2334/* Subsequent entries in a procedure linkage table look like this. */
2335static const bfd_vma elf32_arm_nacl_plt_entry [] =
2336{
2337 0xe300c000, /* movw ip, #:lower16:&GOT[n]-.+8 */
2338 0xe340c000, /* movt ip, #:upper16:&GOT[n]-.+8 */
2339 0xe08cc00f, /* add ip, ip, pc */
2340 0xea000000, /* b .Lplt_tail */
2341};
e5a52504 2342
906e58ca
NC		 2343#define ARM_MAX_FWD_BRANCH_OFFSET ((((1 << 23) - 1) << 2) + 8)
2344#define ARM_MAX_BWD_BRANCH_OFFSET ((-((1 << 23) << 2)) + 8)
2345#define THM_MAX_FWD_BRANCH_OFFSET ((1 << 22) -2 + 4)
2346#define THM_MAX_BWD_BRANCH_OFFSET (-(1 << 22) + 4)
2347#define THM2_MAX_FWD_BRANCH_OFFSET (((1 << 24) - 2) + 4)
2348#define THM2_MAX_BWD_BRANCH_OFFSET (-(1 << 24) + 4)
c5423981
TG		 2349#define THM2_MAX_FWD_COND_BRANCH_OFFSET (((1 << 20) -2) + 4)
2350#define THM2_MAX_BWD_COND_BRANCH_OFFSET (-(1 << 20) + 4)
906e58ca 2351
461a49ca 2352enum stub_insn_type
b38cadfb
NC		 2353{
2354 THUMB16_TYPE = 1,
2355 THUMB32_TYPE,
2356 ARM_TYPE,
2357 DATA_TYPE
2358};
461a49ca 2359
48229727
JB		 2360#define THUMB16_INSN(X) {(X), THUMB16_TYPE, R_ARM_NONE, 0}
2361/* A bit of a hack. A Thumb conditional branch, in which the proper condition
2362 is inserted in arm_build_one_stub(). */
2363#define THUMB16_BCOND_INSN(X) {(X), THUMB16_TYPE, R_ARM_NONE, 1}
2364#define THUMB32_INSN(X) {(X), THUMB32_TYPE, R_ARM_NONE, 0}
d5a67c02
AV		 2365#define THUMB32_MOVT(X) {(X), THUMB32_TYPE, R_ARM_THM_MOVT_ABS, 0}
2366#define THUMB32_MOVW(X) {(X), THUMB32_TYPE, R_ARM_THM_MOVW_ABS_NC, 0}
48229727
JB		 2367#define THUMB32_B_INSN(X, Z) {(X), THUMB32_TYPE, R_ARM_THM_JUMP24, (Z)}
2368#define ARM_INSN(X) {(X), ARM_TYPE, R_ARM_NONE, 0}
2369#define ARM_REL_INSN(X, Z) {(X), ARM_TYPE, R_ARM_JUMP24, (Z)}
2370#define DATA_WORD(X,Y,Z) {(X), DATA_TYPE, (Y), (Z)}
461a49ca
DJ		 2371
2372typedef struct
2373{
b38cadfb
NC		 2374 bfd_vma data;
2375 enum stub_insn_type type;
2376 unsigned int r_type;
2377 int reloc_addend;
461a49ca
DJ		 2378} insn_sequence;
2379
fea2b4d6
CL		 2380/* Arm/Thumb -> Arm/Thumb long branch stub. On V5T and above, use blx
2381 to reach the stub if necessary. */
461a49ca 2382static const insn_sequence elf32_arm_stub_long_branch_any_any[] =
b38cadfb
NC		 2383{
2384 ARM_INSN (0xe51ff004), /* ldr pc, [pc, #-4] */
2385 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(X) */
2386};
906e58ca 2387
fea2b4d6
CL		 2388/* V4T Arm -> Thumb long branch stub. Used on V4T where blx is not
2389 available. */
461a49ca 2390static const insn_sequence elf32_arm_stub_long_branch_v4t_arm_thumb[] =
b38cadfb
NC		 2391{
2392 ARM_INSN (0xe59fc000), /* ldr ip, [pc, #0] */
2393 ARM_INSN (0xe12fff1c), /* bx ip */
2394 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(X) */
2395};
906e58ca 2396
d3626fb0 2397/* Thumb -> Thumb long branch stub. Used on M-profile architectures. */
461a49ca 2398static const insn_sequence elf32_arm_stub_long_branch_thumb_only[] =
b38cadfb
NC		 2399{
2400 THUMB16_INSN (0xb401), /* push {r0} */
2401 THUMB16_INSN (0x4802), /* ldr r0, [pc, #8] */
2402 THUMB16_INSN (0x4684), /* mov ip, r0 */
2403 THUMB16_INSN (0xbc01), /* pop {r0} */
2404 THUMB16_INSN (0x4760), /* bx ip */
2405 THUMB16_INSN (0xbf00), /* nop */
2406 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(X) */
2407};
906e58ca 2408
80c135e5
TP		 2409/* Thumb -> Thumb long branch stub in thumb2 encoding. Used on armv7. */
2410static const insn_sequence elf32_arm_stub_long_branch_thumb2_only[] =
2411{
2412 THUMB32_INSN (0xf85ff000), /* ldr.w pc, [pc, #-0] */
2413 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(x) */
2414};
2415
d5a67c02
AV		 2416/* Thumb -> Thumb long branch stub. Used for PureCode sections on Thumb2
2417 M-profile architectures. */
2418static const insn_sequence elf32_arm_stub_long_branch_thumb2_only_pure[] =
2419{
2420 THUMB32_MOVW (0xf2400c00), /* mov.w ip, R_ARM_MOVW_ABS_NC */
2421 THUMB32_MOVT (0xf2c00c00), /* movt ip, R_ARM_MOVT_ABS << 16 */
2422 THUMB16_INSN (0x4760), /* bx ip */
2423};
2424
d3626fb0
CL		 2425/* V4T Thumb -> Thumb long branch stub. Using the stack is not
2426 allowed. */
2427static const insn_sequence elf32_arm_stub_long_branch_v4t_thumb_thumb[] =
b38cadfb
NC		 2428{
2429 THUMB16_INSN (0x4778), /* bx pc */
2430 THUMB16_INSN (0x46c0), /* nop */
2431 ARM_INSN (0xe59fc000), /* ldr ip, [pc, #0] */
2432 ARM_INSN (0xe12fff1c), /* bx ip */
2433 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(X) */
2434};
d3626fb0 2435
fea2b4d6
CL		 2436/* V4T Thumb -> ARM long branch stub. Used on V4T where blx is not
2437 available. */
461a49ca 2438static const insn_sequence elf32_arm_stub_long_branch_v4t_thumb_arm[] =
b38cadfb
NC		 2439{
2440 THUMB16_INSN (0x4778), /* bx pc */
2441 THUMB16_INSN (0x46c0), /* nop */
2442 ARM_INSN (0xe51ff004), /* ldr pc, [pc, #-4] */
2443 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(X) */
2444};
906e58ca 2445
fea2b4d6
CL		 2446/* V4T Thumb -> ARM short branch stub. Shorter variant of the above
2447 one, when the destination is close enough. */
461a49ca 2448static const insn_sequence elf32_arm_stub_short_branch_v4t_thumb_arm[] =
b38cadfb
NC		 2449{
2450 THUMB16_INSN (0x4778), /* bx pc */
2451 THUMB16_INSN (0x46c0), /* nop */
2452 ARM_REL_INSN (0xea000000, -8), /* b (X-8) */
2453};
c820be07 2454
cf3eccff 2455/* ARM/Thumb -> ARM long branch stub, PIC. On V5T and above, use
fea2b4d6 2456 blx to reach the stub if necessary. */
cf3eccff 2457static const insn_sequence elf32_arm_stub_long_branch_any_arm_pic[] =
b38cadfb
NC		 2458{
2459 ARM_INSN (0xe59fc000), /* ldr ip, [pc] */
2460 ARM_INSN (0xe08ff00c), /* add pc, pc, ip */
2461 DATA_WORD (0, R_ARM_REL32, -4), /* dcd R_ARM_REL32(X-4) */
2462};
906e58ca 2463
cf3eccff
DJ		 2464/* ARM/Thumb -> Thumb long branch stub, PIC. On V5T and above, use
2465 blx to reach the stub if necessary. We can not add into pc;
2466 it is not guaranteed to mode switch (different in ARMv6 and
2467 ARMv7). */
2468static const insn_sequence elf32_arm_stub_long_branch_any_thumb_pic[] =
b38cadfb
NC		 2469{
2470 ARM_INSN (0xe59fc004), /* ldr ip, [pc, #4] */
2471 ARM_INSN (0xe08fc00c), /* add ip, pc, ip */
2472 ARM_INSN (0xe12fff1c), /* bx ip */
2473 DATA_WORD (0, R_ARM_REL32, 0), /* dcd R_ARM_REL32(X) */
2474};
cf3eccff 2475
ebe24dd4
CL		 2476/* V4T ARM -> ARM long branch stub, PIC. */
2477static const insn_sequence elf32_arm_stub_long_branch_v4t_arm_thumb_pic[] =
b38cadfb
NC		 2478{
2479 ARM_INSN (0xe59fc004), /* ldr ip, [pc, #4] */
2480 ARM_INSN (0xe08fc00c), /* add ip, pc, ip */
2481 ARM_INSN (0xe12fff1c), /* bx ip */
2482 DATA_WORD (0, R_ARM_REL32, 0), /* dcd R_ARM_REL32(X) */
2483};
ebe24dd4
CL		 2484
2485/* V4T Thumb -> ARM long branch stub, PIC. */
2486static const insn_sequence elf32_arm_stub_long_branch_v4t_thumb_arm_pic[] =
b38cadfb
NC		 2487{
2488 THUMB16_INSN (0x4778), /* bx pc */
2489 THUMB16_INSN (0x46c0), /* nop */
2490 ARM_INSN (0xe59fc000), /* ldr ip, [pc, #0] */
2491 ARM_INSN (0xe08cf00f), /* add pc, ip, pc */
2492 DATA_WORD (0, R_ARM_REL32, -4), /* dcd R_ARM_REL32(X) */
2493};
ebe24dd4 2494
d3626fb0
CL		 2495/* Thumb -> Thumb long branch stub, PIC. Used on M-profile
2496 architectures. */
ebe24dd4 2497static const insn_sequence elf32_arm_stub_long_branch_thumb_only_pic[] =
b38cadfb
NC		 2498{
2499 THUMB16_INSN (0xb401), /* push {r0} */
2500 THUMB16_INSN (0x4802), /* ldr r0, [pc, #8] */
2501 THUMB16_INSN (0x46fc), /* mov ip, pc */
2502 THUMB16_INSN (0x4484), /* add ip, r0 */
2503 THUMB16_INSN (0xbc01), /* pop {r0} */
2504 THUMB16_INSN (0x4760), /* bx ip */
2505 DATA_WORD (0, R_ARM_REL32, 4), /* dcd R_ARM_REL32(X) */
2506};
ebe24dd4 2507
d3626fb0
CL		 2508/* V4T Thumb -> Thumb long branch stub, PIC. Using the stack is not
2509 allowed. */
2510static const insn_sequence elf32_arm_stub_long_branch_v4t_thumb_thumb_pic[] =
b38cadfb
NC		 2511{
2512 THUMB16_INSN (0x4778), /* bx pc */
2513 THUMB16_INSN (0x46c0), /* nop */
2514 ARM_INSN (0xe59fc004), /* ldr ip, [pc, #4] */
2515 ARM_INSN (0xe08fc00c), /* add ip, pc, ip */
2516 ARM_INSN (0xe12fff1c), /* bx ip */
2517 DATA_WORD (0, R_ARM_REL32, 0), /* dcd R_ARM_REL32(X) */
2518};
d3626fb0 2519
0855e32b
NS		 2520/* Thumb2/ARM -> TLS trampoline. Lowest common denominator, which is a
2521 long PIC stub. We can use r1 as a scratch -- and cannot use ip. */
2522static const insn_sequence elf32_arm_stub_long_branch_any_tls_pic[] =
2523{
b38cadfb
NC		 2524 ARM_INSN (0xe59f1000), /* ldr r1, [pc] */
2525 ARM_INSN (0xe08ff001), /* add pc, pc, r1 */
2526 DATA_WORD (0, R_ARM_REL32, -4), /* dcd R_ARM_REL32(X-4) */
0855e32b
NS		 2527};
2528
2529/* V4T Thumb -> TLS trampoline. lowest common denominator, which is a
2530 long PIC stub. We can use r1 as a scratch -- and cannot use ip. */
2531static const insn_sequence elf32_arm_stub_long_branch_v4t_thumb_tls_pic[] =
2532{
b38cadfb
NC		 2533 THUMB16_INSN (0x4778), /* bx pc */
2534 THUMB16_INSN (0x46c0), /* nop */
2535 ARM_INSN (0xe59f1000), /* ldr r1, [pc, #0] */
2536 ARM_INSN (0xe081f00f), /* add pc, r1, pc */
2537 DATA_WORD (0, R_ARM_REL32, -4), /* dcd R_ARM_REL32(X) */
0855e32b
NS		 2538};
2539
7a89b94e
NC		 2540/* NaCl ARM -> ARM long branch stub. */
2541static const insn_sequence elf32_arm_stub_long_branch_arm_nacl[] =
2542{
2543 ARM_INSN (0xe59fc00c), /* ldr ip, [pc, #12] */
2544 ARM_INSN (0xe3ccc13f), /* bic ip, ip, #0xc000000f */
2545 ARM_INSN (0xe12fff1c), /* bx ip */
2546 ARM_INSN (0xe320f000), /* nop */
2547 ARM_INSN (0xe125be70), /* bkpt 0x5be0 */
2548 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(X) */
2549 DATA_WORD (0, R_ARM_NONE, 0), /* .word 0 */
2550 DATA_WORD (0, R_ARM_NONE, 0), /* .word 0 */
2551};
2552
2553/* NaCl ARM -> ARM long branch stub, PIC. */
2554static const insn_sequence elf32_arm_stub_long_branch_arm_nacl_pic[] =
2555{
2556 ARM_INSN (0xe59fc00c), /* ldr ip, [pc, #12] */
2557 ARM_INSN (0xe08cc00f), /* add ip, ip, pc */
2558 ARM_INSN (0xe3ccc13f), /* bic ip, ip, #0xc000000f */
2559 ARM_INSN (0xe12fff1c), /* bx ip */
2560 ARM_INSN (0xe125be70), /* bkpt 0x5be0 */
2561 DATA_WORD (0, R_ARM_REL32, 8), /* dcd R_ARM_REL32(X+8) */
2562 DATA_WORD (0, R_ARM_NONE, 0), /* .word 0 */
2563 DATA_WORD (0, R_ARM_NONE, 0), /* .word 0 */
2564};
2565
4ba2ef8f
TP		 2566/* Stub used for transition to secure state (aka SG veneer). */
2567static const insn_sequence elf32_arm_stub_cmse_branch_thumb_only[] =
2568{
2569 THUMB32_INSN (0xe97fe97f), /* sg. */
2570 THUMB32_B_INSN (0xf000b800, -4), /* b.w original_branch_dest. */
2571};
2572
7a89b94e 2573
48229727
JB		 2574/* Cortex-A8 erratum-workaround stubs. */
2575
2576/* Stub used for conditional branches (which may be beyond +/-1MB away, so we
2577 can't use a conditional branch to reach this stub). */
2578
2579static const insn_sequence elf32_arm_stub_a8_veneer_b_cond[] =
b38cadfb
NC		 2580{
2581 THUMB16_BCOND_INSN (0xd001), /* b<cond>.n true. */
2582 THUMB32_B_INSN (0xf000b800, -4), /* b.w insn_after_original_branch. */
2583 THUMB32_B_INSN (0xf000b800, -4) /* true: b.w original_branch_dest. */
2584};
48229727
JB		 2585
2586/* Stub used for b.w and bl.w instructions. */
2587
2588static const insn_sequence elf32_arm_stub_a8_veneer_b[] =
b38cadfb
NC		 2589{
2590 THUMB32_B_INSN (0xf000b800, -4) /* b.w original_branch_dest. */
2591};
48229727
JB		 2592
2593static const insn_sequence elf32_arm_stub_a8_veneer_bl[] =
b38cadfb
NC		 2594{
2595 THUMB32_B_INSN (0xf000b800, -4) /* b.w original_branch_dest. */
2596};
48229727
JB		 2597
2598/* Stub used for Thumb-2 blx.w instructions. We modified the original blx.w
2599 instruction (which switches to ARM mode) to point to this stub. Jump to the
2600 real destination using an ARM-mode branch. */
2601
2602static const insn_sequence elf32_arm_stub_a8_veneer_blx[] =
b38cadfb
NC		 2603{
2604 ARM_REL_INSN (0xea000000, -8) /* b original_branch_dest. */
2605};
48229727 2606
9553db3c
NC		 2607/* For each section group there can be a specially created linker section
2608 to hold the stubs for that group. The name of the stub section is based
2609 upon the name of another section within that group with the suffix below
2610 applied.
2611
2612 PR 13049: STUB_SUFFIX used to be ".stub", but this allowed the user to
2613 create what appeared to be a linker stub section when it actually
2614 contained user code/data. For example, consider this fragment:
b38cadfb 2615
9553db3c
NC		 2616 const char * stubborn_problems[] = { "np" };
2617
2618 If this is compiled with "-fPIC -fdata-sections" then gcc produces a
2619 section called:
2620
2621 .data.rel.local.stubborn_problems
2622
2623 This then causes problems in arm32_arm_build_stubs() as it triggers:
2624
2625 // Ignore non-stub sections.
2626 if (!strstr (stub_sec->name, STUB_SUFFIX))
2627 continue;
2628
2629 And so the section would be ignored instead of being processed. Hence
2630 the change in definition of STUB_SUFFIX to a name that cannot be a valid
2631 C identifier. */
2632#define STUB_SUFFIX ".__stub"
906e58ca 2633
738a79f6
CL		 2634/* One entry per long/short branch stub defined above. */
2635#define DEF_STUBS \
2636 DEF_STUB(long_branch_any_any) \
2637 DEF_STUB(long_branch_v4t_arm_thumb) \
2638 DEF_STUB(long_branch_thumb_only) \
2639 DEF_STUB(long_branch_v4t_thumb_thumb) \
2640 DEF_STUB(long_branch_v4t_thumb_arm) \
2641 DEF_STUB(short_branch_v4t_thumb_arm) \
2642 DEF_STUB(long_branch_any_arm_pic) \
2643 DEF_STUB(long_branch_any_thumb_pic) \
2644 DEF_STUB(long_branch_v4t_thumb_thumb_pic) \
2645 DEF_STUB(long_branch_v4t_arm_thumb_pic) \
2646 DEF_STUB(long_branch_v4t_thumb_arm_pic) \
48229727 2647 DEF_STUB(long_branch_thumb_only_pic) \
0855e32b
NS		 2648 DEF_STUB(long_branch_any_tls_pic) \
2649 DEF_STUB(long_branch_v4t_thumb_tls_pic) \
7a89b94e
NC		 2650 DEF_STUB(long_branch_arm_nacl) \
2651 DEF_STUB(long_branch_arm_nacl_pic) \
4ba2ef8f 2652 DEF_STUB(cmse_branch_thumb_only) \
48229727
JB		 2653 DEF_STUB(a8_veneer_b_cond) \
2654 DEF_STUB(a8_veneer_b) \
2655 DEF_STUB(a8_veneer_bl) \
80c135e5
TP		 2656 DEF_STUB(a8_veneer_blx) \
2657 DEF_STUB(long_branch_thumb2_only) \
d5a67c02 2658 DEF_STUB(long_branch_thumb2_only_pure)
738a79f6
CL		 2659
2660#define DEF_STUB(x) arm_stub_##x,
b38cadfb
NC		 2661enum elf32_arm_stub_type
2662{
906e58ca 2663 arm_stub_none,
738a79f6 2664 DEF_STUBS
4f4faa4d 2665 max_stub_type
738a79f6
CL		 2666};
2667#undef DEF_STUB
2668
8d9d9490
TP		 2669/* Note the first a8_veneer type. */
2670const unsigned arm_stub_a8_veneer_lwm = arm_stub_a8_veneer_b_cond;
2671
738a79f6
CL		 2672typedef struct
2673{
d3ce72d0 2674 const insn_sequence* template_sequence;
738a79f6
CL		 2675 int template_size;
2676} stub_def;
2677
2678#define DEF_STUB(x) {elf32_arm_stub_##x, ARRAY_SIZE(elf32_arm_stub_##x)},
b38cadfb
NC		 2679static const stub_def stub_definitions[] =
2680{
738a79f6
CL		 2681 {NULL, 0},
2682 DEF_STUBS
906e58ca
NC		 2683};
2684
2685struct elf32_arm_stub_hash_entry
2686{
2687 /* Base hash table entry structure. */
2688 struct bfd_hash_entry root;
2689
2690 /* The stub section. */
2691 asection *stub_sec;
2692
2693 /* Offset within stub_sec of the beginning of this stub. */
2694 bfd_vma stub_offset;
2695
2696 /* Given the symbol's value and its section we can determine its final
2697 value when building the stubs (so the stub knows where to jump). */
2698 bfd_vma target_value;
2699 asection *target_section;
2700
8d9d9490
TP		 2701 /* Same as above but for the source of the branch to the stub. Used for
2702 Cortex-A8 erratum workaround to patch it to branch to the stub. As
2703 such, source section does not need to be recorded since Cortex-A8 erratum
2704 workaround stubs are only generated when both source and target are in the
2705 same section. */
2706 bfd_vma source_value;
48229727
JB		 2707
2708 /* The instruction which caused this stub to be generated (only valid for
2709 Cortex-A8 erratum workaround stubs at present). */
2710 unsigned long orig_insn;
2711
461a49ca 2712 /* The stub type. */
906e58ca 2713 enum elf32_arm_stub_type stub_type;
461a49ca
DJ		 2714 /* Its encoding size in bytes. */
2715 int stub_size;
2716 /* Its template. */
2717 const insn_sequence *stub_template;
2718 /* The size of the template (number of entries). */
2719 int stub_template_size;
906e58ca
NC		 2720
2721 /* The symbol table entry, if any, that this was derived from. */
2722 struct elf32_arm_link_hash_entry *h;
2723
35fc36a8
RS		 2724 /* Type of branch. */
2725 enum arm_st_branch_type branch_type;
906e58ca
NC		 2726
2727 /* Where this stub is being called from, or, in the case of combined
2728 stub sections, the first input section in the group. */
2729 asection *id_sec;
7413f23f
DJ		 2730
2731 /* The name for the local symbol at the start of this stub. The
2732 stub name in the hash table has to be unique; this does not, so
2733 it can be friendlier. */
2734 char *output_name;
906e58ca
NC		 2735};
2736
e489d0ae
PB		 2737/* Used to build a map of a section. This is required for mixed-endian
2738 code/data. */
2739
2740typedef struct elf32_elf_section_map
2741{
2742 bfd_vma vma;
2743 char type;
2744}
2745elf32_arm_section_map;
2746
c7b8f16e
JB		 2747/* Information about a VFP11 erratum veneer, or a branch to such a veneer. */
2748
2749typedef enum
2750{
2751 VFP11_ERRATUM_BRANCH_TO_ARM_VENEER,
2752 VFP11_ERRATUM_BRANCH_TO_THUMB_VENEER,
2753 VFP11_ERRATUM_ARM_VENEER,
2754 VFP11_ERRATUM_THUMB_VENEER
2755}
2756elf32_vfp11_erratum_type;
2757
2758typedef struct elf32_vfp11_erratum_list
2759{
2760 struct elf32_vfp11_erratum_list *next;
2761 bfd_vma vma;
2762 union
2763 {
2764 struct
2765 {
2766 struct elf32_vfp11_erratum_list *veneer;
2767 unsigned int vfp_insn;
2768 } b;
2769 struct
2770 {
2771 struct elf32_vfp11_erratum_list *branch;
2772 unsigned int id;
2773 } v;
2774 } u;
2775 elf32_vfp11_erratum_type type;
2776}
2777elf32_vfp11_erratum_list;
2778
a504d23a
LA		 2779/* Information about a STM32L4XX erratum veneer, or a branch to such a
2780 veneer. */
2781typedef enum
2782{
2783 STM32L4XX_ERRATUM_BRANCH_TO_VENEER,
2784 STM32L4XX_ERRATUM_VENEER
2785}
2786elf32_stm32l4xx_erratum_type;
2787
2788typedef struct elf32_stm32l4xx_erratum_list
2789{
2790 struct elf32_stm32l4xx_erratum_list *next;
2791 bfd_vma vma;
2792 union
2793 {
2794 struct
2795 {
2796 struct elf32_stm32l4xx_erratum_list *veneer;
2797 unsigned int insn;
2798 } b;
2799 struct
2800 {
2801 struct elf32_stm32l4xx_erratum_list *branch;
2802 unsigned int id;
2803 } v;
2804 } u;
2805 elf32_stm32l4xx_erratum_type type;
2806}
2807elf32_stm32l4xx_erratum_list;
2808
2468f9c9
PB		 2809typedef enum
2810{
2811 DELETE_EXIDX_ENTRY,
2812 INSERT_EXIDX_CANTUNWIND_AT_END
2813}
2814arm_unwind_edit_type;
2815
2816/* A (sorted) list of edits to apply to an unwind table. */
2817typedef struct arm_unwind_table_edit
2818{
2819 arm_unwind_edit_type type;
2820 /* Note: we sometimes want to insert an unwind entry corresponding to a
2821 section different from the one we're currently writing out, so record the
2822 (text) section this edit relates to here. */
2823 asection *linked_section;
2824 unsigned int index;
2825 struct arm_unwind_table_edit *next;
2826}
2827arm_unwind_table_edit;
2828
8e3de13a 2829typedef struct _arm_elf_section_data
e489d0ae 2830{
2468f9c9 2831 /* Information about mapping symbols. */
e489d0ae 2832 struct bfd_elf_section_data elf;
8e3de13a 2833 unsigned int mapcount;
c7b8f16e 2834 unsigned int mapsize;
e489d0ae 2835 elf32_arm_section_map *map;
2468f9c9 2836 /* Information about CPU errata. */
c7b8f16e
JB		 2837 unsigned int erratumcount;
2838 elf32_vfp11_erratum_list *erratumlist;
a504d23a
LA		 2839 unsigned int stm32l4xx_erratumcount;
2840 elf32_stm32l4xx_erratum_list *stm32l4xx_erratumlist;
491d01d3 2841 unsigned int additional_reloc_count;
2468f9c9
PB		 2842 /* Information about unwind tables. */
2843 union
2844 {
2845 /* Unwind info attached to a text section. */
2846 struct
2847 {
2848 asection *arm_exidx_sec;
2849 } text;
2850
2851 /* Unwind info attached to an .ARM.exidx section. */
2852 struct
2853 {
2854 arm_unwind_table_edit *unwind_edit_list;
2855 arm_unwind_table_edit *unwind_edit_tail;
2856 } exidx;
2857 } u;
8e3de13a
NC		 2858}
2859_arm_elf_section_data;
e489d0ae
PB		 2860
2861#define elf32_arm_section_data(sec) \
8e3de13a 2862 ((_arm_elf_section_data *) elf_section_data (sec))
e489d0ae 2863
48229727
JB		 2864/* A fix which might be required for Cortex-A8 Thumb-2 branch/TLB erratum.
2865 These fixes are subject to a relaxation procedure (in elf32_arm_size_stubs),
2866 so may be created multiple times: we use an array of these entries whilst
2867 relaxing which we can refresh easily, then create stubs for each potentially
2868 erratum-triggering instruction once we've settled on a solution. */
2869
b38cadfb
NC		 2870struct a8_erratum_fix
2871{
48229727
JB		 2872 bfd *input_bfd;
2873 asection *section;
2874 bfd_vma offset;
8d9d9490 2875 bfd_vma target_offset;
48229727
JB		 2876 unsigned long orig_insn;
2877 char *stub_name;
2878 enum elf32_arm_stub_type stub_type;
35fc36a8 2879 enum arm_st_branch_type branch_type;
48229727
JB		 2880};
2881
2882/* A table of relocs applied to branches which might trigger Cortex-A8
2883 erratum. */
2884
b38cadfb
NC		 2885struct a8_erratum_reloc
2886{
48229727
JB		 2887 bfd_vma from;
2888 bfd_vma destination;
92750f34
DJ		 2889 struct elf32_arm_link_hash_entry *hash;
2890 const char *sym_name;
48229727 2891 unsigned int r_type;
35fc36a8 2892 enum arm_st_branch_type branch_type;
48229727
JB		 2893 bfd_boolean non_a8_stub;
2894};
2895
ba93b8ac
DJ		 2896/* The size of the thread control block. */
2897#define TCB_SIZE 8
2898
34e77a92
RS		 2899/* ARM-specific information about a PLT entry, over and above the usual
2900 gotplt_union. */
b38cadfb
NC		 2901struct arm_plt_info
2902{
34e77a92
RS		 2903 /* We reference count Thumb references to a PLT entry separately,
2904 so that we can emit the Thumb trampoline only if needed. */
2905 bfd_signed_vma thumb_refcount;
2906
2907 /* Some references from Thumb code may be eliminated by BL->BLX
2908 conversion, so record them separately. */
2909 bfd_signed_vma maybe_thumb_refcount;
2910
2911 /* How many of the recorded PLT accesses were from non-call relocations.
2912 This information is useful when deciding whether anything takes the
2913 address of an STT_GNU_IFUNC PLT. A value of 0 means that all
2914 non-call references to the function should resolve directly to the
2915 real runtime target. */
2916 unsigned int noncall_refcount;
2917
2918 /* Since PLT entries have variable size if the Thumb prologue is
2919 used, we need to record the index into .got.plt instead of
2920 recomputing it from the PLT offset. */
2921 bfd_signed_vma got_offset;
2922};
2923
2924/* Information about an .iplt entry for a local STT_GNU_IFUNC symbol. */
b38cadfb
NC		 2925struct arm_local_iplt_info
2926{
34e77a92
RS		 2927 /* The information that is usually found in the generic ELF part of
2928 the hash table entry. */
2929 union gotplt_union root;
2930
2931 /* The information that is usually found in the ARM-specific part of
2932 the hash table entry. */
2933 struct arm_plt_info arm;
2934
2935 /* A list of all potential dynamic relocations against this symbol. */
2936 struct elf_dyn_relocs *dyn_relocs;
2937};
2938
0ffa91dd 2939struct elf_arm_obj_tdata
ba93b8ac
DJ		 2940{
2941 struct elf_obj_tdata root;
2942
2943 /* tls_type for each local got entry. */
2944 char *local_got_tls_type;
ee065d83 2945
0855e32b
NS		 2946 /* GOTPLT entries for TLS descriptors. */
2947 bfd_vma *local_tlsdesc_gotent;
2948
34e77a92
RS		 2949 /* Information for local symbols that need entries in .iplt. */
2950 struct arm_local_iplt_info **local_iplt;
2951
bf21ed78
MS		 2952 /* Zero to warn when linking objects with incompatible enum sizes. */
2953 int no_enum_size_warning;
a9dc9481
JM		 2954
2955 /* Zero to warn when linking objects with incompatible wchar_t sizes. */
2956 int no_wchar_size_warning;
ba93b8ac
DJ		 2957};
2958
0ffa91dd
NC		 2959#define elf_arm_tdata(bfd) \
2960 ((struct elf_arm_obj_tdata *) (bfd)->tdata.any)
ba93b8ac 2961
0ffa91dd
NC		 2962#define elf32_arm_local_got_tls_type(bfd) \
2963 (elf_arm_tdata (bfd)->local_got_tls_type)
2964
0855e32b
NS		 2965#define elf32_arm_local_tlsdesc_gotent(bfd) \
2966 (elf_arm_tdata (bfd)->local_tlsdesc_gotent)
2967
34e77a92
RS		 2968#define elf32_arm_local_iplt(bfd) \
2969 (elf_arm_tdata (bfd)->local_iplt)
2970
0ffa91dd
NC		 2971#define is_arm_elf(bfd) \
2972 (bfd_get_flavour (bfd) == bfd_target_elf_flavour \
2973 && elf_tdata (bfd) != NULL \
4dfe6ac6 2974 && elf_object_id (bfd) == ARM_ELF_DATA)
ba93b8ac
DJ		 2975
2976static bfd_boolean
2977elf32_arm_mkobject (bfd *abfd)
2978{
0ffa91dd 2979 return bfd_elf_allocate_object (abfd, sizeof (struct elf_arm_obj_tdata),
4dfe6ac6 2980 ARM_ELF_DATA);
ba93b8ac
DJ		 2981}
2982
ba93b8ac
DJ		 2983#define elf32_arm_hash_entry(ent) ((struct elf32_arm_link_hash_entry *)(ent))
2984
ba96a88f 2985/* Arm ELF linker hash entry. */
252b5132 2986struct elf32_arm_link_hash_entry
b38cadfb
NC		 2987{
2988 struct elf_link_hash_entry root;
252b5132 2989
b38cadfb
NC		 2990 /* Track dynamic relocs copied for this symbol. */
2991 struct elf_dyn_relocs *dyn_relocs;
b7693d02 2992
b38cadfb
NC		 2993 /* ARM-specific PLT information. */
2994 struct arm_plt_info plt;
ba93b8ac
DJ		 2995
2996#define GOT_UNKNOWN 0
2997#define GOT_NORMAL 1
2998#define GOT_TLS_GD 2
2999#define GOT_TLS_IE 4
0855e32b
NS		 3000#define GOT_TLS_GDESC 8
3001#define GOT_TLS_GD_ANY_P(type) ((type & GOT_TLS_GD) || (type & GOT_TLS_GDESC))
b38cadfb 3002 unsigned int tls_type : 8;
34e77a92 3003
b38cadfb
NC		 3004 /* True if the symbol's PLT entry is in .iplt rather than .plt. */
3005 unsigned int is_iplt : 1;
34e77a92 3006
b38cadfb 3007 unsigned int unused : 23;
a4fd1a8e 3008
b38cadfb
NC		 3009 /* Offset of the GOTPLT entry reserved for the TLS descriptor,
3010 starting at the end of the jump table. */
3011 bfd_vma tlsdesc_got;
0855e32b 3012
b38cadfb
NC		 3013 /* The symbol marking the real symbol location for exported thumb
3014 symbols with Arm stubs. */
3015 struct elf_link_hash_entry *export_glue;
906e58ca 3016
b38cadfb 3017 /* A pointer to the most recently used stub hash entry against this
8029a119 3018 symbol. */
b38cadfb
NC		 3019 struct elf32_arm_stub_hash_entry *stub_cache;
3020};
252b5132 3021
252b5132 3022/* Traverse an arm ELF linker hash table. */
252b5132
RH		 3023#define elf32_arm_link_hash_traverse(table, func, info) \
3024 (elf_link_hash_traverse \
3025 (&(table)->root, \
b7693d02 3026 (bfd_boolean (*) (struct elf_link_hash_entry *, void *)) (func), \
252b5132
RH		 3027 (info)))
3028
3029/* Get the ARM elf linker hash table from a link_info structure. */
3030#define elf32_arm_hash_table(info) \
4dfe6ac6
NC		 3031 (elf_hash_table_id ((struct elf_link_hash_table *) ((info)->hash)) \
3032 == ARM_ELF_DATA ? ((struct elf32_arm_link_hash_table *) ((info)->hash)) : NULL)
252b5132 3033
906e58ca
NC		 3034#define arm_stub_hash_lookup(table, string, create, copy) \
3035 ((struct elf32_arm_stub_hash_entry *) \
3036 bfd_hash_lookup ((table), (string), (create), (copy)))
3037
21d799b5
NC		 3038/* Array to keep track of which stub sections have been created, and
3039 information on stub grouping. */
3040struct map_stub
3041{
3042 /* This is the section to which stubs in the group will be
3043 attached. */
3044 asection *link_sec;
3045 /* The stub section. */
3046 asection *stub_sec;
3047};
3048
0855e32b
NS		 3049#define elf32_arm_compute_jump_table_size(htab) \
3050 ((htab)->next_tls_desc_index * 4)
3051
9b485d32 3052/* ARM ELF linker hash table. */
252b5132 3053struct elf32_arm_link_hash_table
906e58ca
NC		 3054{
3055 /* The main hash table. */
3056 struct elf_link_hash_table root;
252b5132 3057
906e58ca
NC		 3058 /* The size in bytes of the section containing the Thumb-to-ARM glue. */
3059 bfd_size_type thumb_glue_size;
252b5132 3060
906e58ca
NC		 3061 /* The size in bytes of the section containing the ARM-to-Thumb glue. */
3062 bfd_size_type arm_glue_size;
252b5132 3063
906e58ca
NC		 3064 /* The size in bytes of section containing the ARMv4 BX veneers. */
3065 bfd_size_type bx_glue_size;
845b51d6 3066
906e58ca
NC		 3067 /* Offsets of ARMv4 BX veneers. Bit1 set if present, and Bit0 set when
3068 veneer has been populated. */
3069 bfd_vma bx_glue_offset[15];
845b51d6 3070
906e58ca
NC		 3071 /* The size in bytes of the section containing glue for VFP11 erratum
3072 veneers. */
3073 bfd_size_type vfp11_erratum_glue_size;
c7b8f16e 3074
a504d23a
LA		 3075 /* The size in bytes of the section containing glue for STM32L4XX erratum
3076 veneers. */
3077 bfd_size_type stm32l4xx_erratum_glue_size;
3078
48229727
JB		 3079 /* A table of fix locations for Cortex-A8 Thumb-2 branch/TLB erratum. This
3080 holds Cortex-A8 erratum fix locations between elf32_arm_size_stubs() and
3081 elf32_arm_write_section(). */
3082 struct a8_erratum_fix *a8_erratum_fixes;
3083 unsigned int num_a8_erratum_fixes;
3084
906e58ca
NC		 3085 /* An arbitrary input BFD chosen to hold the glue sections. */
3086 bfd * bfd_of_glue_owner;
ba96a88f 3087
906e58ca
NC		 3088 /* Nonzero to output a BE8 image. */
3089 int byteswap_code;
e489d0ae 3090
906e58ca
NC		 3091 /* Zero if R_ARM_TARGET1 means R_ARM_ABS32.
3092 Nonzero if R_ARM_TARGET1 means R_ARM_REL32. */
3093 int target1_is_rel;
9c504268 3094
906e58ca
NC		 3095 /* The relocation to use for R_ARM_TARGET2 relocations. */
3096 int target2_reloc;
eb043451 3097
906e58ca
NC		 3098 /* 0 = Ignore R_ARM_V4BX.
3099 1 = Convert BX to MOV PC.
3100 2 = Generate v4 interworing stubs. */
3101 int fix_v4bx;
319850b4 3102
48229727
JB		 3103 /* Whether we should fix the Cortex-A8 Thumb-2 branch/TLB erratum. */
3104 int fix_cortex_a8;
3105
2de70689
MGD		 3106 /* Whether we should fix the ARM1176 BLX immediate issue. */
3107 int fix_arm1176;
3108
906e58ca
NC		 3109 /* Nonzero if the ARM/Thumb BLX instructions are available for use. */
3110 int use_blx;
33bfe774 3111
906e58ca
NC		 3112 /* What sort of code sequences we should look for which may trigger the
3113 VFP11 denorm erratum. */
3114 bfd_arm_vfp11_fix vfp11_fix;
c7b8f16e 3115
906e58ca
NC		 3116 /* Global counter for the number of fixes we have emitted. */
3117 int num_vfp11_fixes;
c7b8f16e 3118
a504d23a
LA		 3119 /* What sort of code sequences we should look for which may trigger the
3120 STM32L4XX erratum. */
3121 bfd_arm_stm32l4xx_fix stm32l4xx_fix;
3122
3123 /* Global counter for the number of fixes we have emitted. */
3124 int num_stm32l4xx_fixes;
3125
906e58ca
NC		 3126 /* Nonzero to force PIC branch veneers. */
3127 int pic_veneer;
27e55c4d 3128
906e58ca
NC		 3129 /* The number of bytes in the initial entry in the PLT. */
3130 bfd_size_type plt_header_size;
e5a52504 3131
906e58ca
NC		 3132 /* The number of bytes in the subsequent PLT etries. */
3133 bfd_size_type plt_entry_size;
e5a52504 3134
906e58ca
NC		 3135 /* True if the target system is VxWorks. */
3136 int vxworks_p;
00a97672 3137
906e58ca
NC		 3138 /* True if the target system is Symbian OS. */
3139 int symbian_p;
e5a52504 3140
b38cadfb
NC		 3141 /* True if the target system is Native Client. */
3142 int nacl_p;
3143
906e58ca
NC		 3144 /* True if the target uses REL relocations. */
3145 int use_rel;
4e7fd91e 3146
54ddd295
TP		 3147 /* Nonzero if import library must be a secure gateway import library
3148 as per ARMv8-M Security Extensions. */
3149 int cmse_implib;
3150
0955507f
TP		 3151 /* The import library whose symbols' address must remain stable in
3152 the import library generated. */
3153 bfd *in_implib_bfd;
3154
0855e32b
NS		 3155 /* The index of the next unused R_ARM_TLS_DESC slot in .rel.plt. */
3156 bfd_vma next_tls_desc_index;
3157
3158 /* How many R_ARM_TLS_DESC relocations were generated so far. */
3159 bfd_vma num_tls_desc;
3160
906e58ca 3161 /* Short-cuts to get to dynamic linker sections. */
906e58ca
NC		 3162 asection *sdynbss;
3163 asection *srelbss;
5e681ec4 3164
906e58ca
NC		 3165 /* The (unloaded but important) VxWorks .rela.plt.unloaded section. */
3166 asection *srelplt2;
00a97672 3167
0855e32b
NS		 3168 /* The offset into splt of the PLT entry for the TLS descriptor
3169 resolver. Special values are 0, if not necessary (or not found
3170 to be necessary yet), and -1 if needed but not determined
3171 yet. */
3172 bfd_vma dt_tlsdesc_plt;
3173
3174 /* The offset into sgot of the GOT entry used by the PLT entry
3175 above. */
b38cadfb 3176 bfd_vma dt_tlsdesc_got;
0855e32b
NS		 3177
3178 /* Offset in .plt section of tls_arm_trampoline. */
3179 bfd_vma tls_trampoline;
3180
906e58ca
NC		 3181 /* Data for R_ARM_TLS_LDM32 relocations. */
3182 union
3183 {
3184 bfd_signed_vma refcount;
3185 bfd_vma offset;
3186 } tls_ldm_got;
b7693d02 3187
87d72d41
AM		 3188 /* Small local sym cache. */
3189 struct sym_cache sym_cache;
906e58ca
NC		 3190
3191 /* For convenience in allocate_dynrelocs. */
3192 bfd * obfd;
3193
0855e32b
NS		 3194 /* The amount of space used by the reserved portion of the sgotplt
3195 section, plus whatever space is used by the jump slots. */
3196 bfd_vma sgotplt_jump_table_size;
3197
906e58ca
NC		 3198 /* The stub hash table. */
3199 struct bfd_hash_table stub_hash_table;
3200
3201 /* Linker stub bfd. */
3202 bfd *stub_bfd;
3203
3204 /* Linker call-backs. */
6bde4c52
TP		 3205 asection * (*add_stub_section) (const char *, asection *, asection *,
3206 unsigned int);
906e58ca
NC		 3207 void (*layout_sections_again) (void);
3208
3209 /* Array to keep track of which stub sections have been created, and
3210 information on stub grouping. */
21d799b5 3211 struct map_stub *stub_group;
906e58ca 3212
4ba2ef8f
TP		 3213 /* Input stub section holding secure gateway veneers. */
3214 asection *cmse_stub_sec;
3215
0955507f
TP		 3216 /* Offset in cmse_stub_sec where new SG veneers (not in input import library)
3217 start to be allocated. */
3218 bfd_vma new_cmse_stub_offset;
3219
fe33d2fa 3220 /* Number of elements in stub_group. */
7292b3ac 3221 unsigned int top_id;
fe33d2fa 3222
906e58ca
NC		 3223 /* Assorted information used by elf32_arm_size_stubs. */
3224 unsigned int bfd_count;
7292b3ac 3225 unsigned int top_index;
906e58ca
NC		 3226 asection **input_list;
3227};
252b5132 3228
a504d23a
LA		 3229static inline int
3230ctz (unsigned int mask)
3231{
3232#if GCC_VERSION >= 3004
3233 return __builtin_ctz (mask);
3234#else
3235 unsigned int i;
3236
3237 for (i = 0; i < 8 * sizeof (mask); i++)
3238 {
3239 if (mask & 0x1)
3240 break;
3241 mask = (mask >> 1);
3242 }
3243 return i;
3244#endif
3245}
3246
3247static inline int
3248popcount (unsigned int mask)
3249{
3250#if GCC_VERSION >= 3004
3251 return __builtin_popcount (mask);
3252#else
3253 unsigned int i, sum = 0;
3254
3255 for (i = 0; i < 8 * sizeof (mask); i++)
3256 {
3257 if (mask & 0x1)
3258 sum++;
3259 mask = (mask >> 1);
3260 }
3261 return sum;
3262#endif
3263}
3264
780a67af
NC		 3265/* Create an entry in an ARM ELF linker hash table. */
3266
3267static struct bfd_hash_entry *
57e8b36a 3268elf32_arm_link_hash_newfunc (struct bfd_hash_entry * entry,
99059e56
RM		 3269 struct bfd_hash_table * table,
3270 const char * string)
780a67af
NC		 3271{
3272 struct elf32_arm_link_hash_entry * ret =
3273 (struct elf32_arm_link_hash_entry *) entry;
3274
3275 /* Allocate the structure if it has not already been allocated by a
3276 subclass. */
906e58ca 3277 if (ret == NULL)
21d799b5 3278 ret = (struct elf32_arm_link_hash_entry *)
99059e56 3279 bfd_hash_allocate (table, sizeof (struct elf32_arm_link_hash_entry));
57e8b36a 3280 if (ret == NULL)
780a67af
NC		 3281 return (struct bfd_hash_entry *) ret;
3282
3283 /* Call the allocation method of the superclass. */
3284 ret = ((struct elf32_arm_link_hash_entry *)
3285 _bfd_elf_link_hash_newfunc ((struct bfd_hash_entry *) ret,
3286 table, string));
57e8b36a 3287 if (ret != NULL)
b7693d02 3288 {
0bdcacaf 3289 ret->dyn_relocs = NULL;
ba93b8ac 3290 ret->tls_type = GOT_UNKNOWN;
0855e32b 3291 ret->tlsdesc_got = (bfd_vma) -1;
34e77a92
RS		 3292 ret->plt.thumb_refcount = 0;
3293 ret->plt.maybe_thumb_refcount = 0;
3294 ret->plt.noncall_refcount = 0;
3295 ret->plt.got_offset = -1;
3296 ret->is_iplt = FALSE;
a4fd1a8e 3297 ret->export_glue = NULL;
906e58ca
NC		 3298
3299 ret->stub_cache = NULL;
b7693d02 3300 }
780a67af
NC		 3301
3302 return (struct bfd_hash_entry *) ret;
3303}
3304
34e77a92
RS		 3305/* Ensure that we have allocated bookkeeping structures for ABFD's local
3306 symbols. */
3307
3308static bfd_boolean
3309elf32_arm_allocate_local_sym_info (bfd *abfd)
3310{
3311 if (elf_local_got_refcounts (abfd) == NULL)
3312 {
3313 bfd_size_type num_syms;
3314 bfd_size_type size;
3315 char *data;
3316
3317 num_syms = elf_tdata (abfd)->symtab_hdr.sh_info;
3318 size = num_syms * (sizeof (bfd_signed_vma)
3319 + sizeof (struct arm_local_iplt_info *)
3320 + sizeof (bfd_vma)
3321 + sizeof (char));
3322 data = bfd_zalloc (abfd, size);
3323 if (data == NULL)
3324 return FALSE;
3325
3326 elf_local_got_refcounts (abfd) = (bfd_signed_vma *) data;
3327 data += num_syms * sizeof (bfd_signed_vma);
3328
3329 elf32_arm_local_iplt (abfd) = (struct arm_local_iplt_info **) data;
3330 data += num_syms * sizeof (struct arm_local_iplt_info *);
3331
3332 elf32_arm_local_tlsdesc_gotent (abfd) = (bfd_vma *) data;
3333 data += num_syms * sizeof (bfd_vma);
3334
3335 elf32_arm_local_got_tls_type (abfd) = data;
3336 }
3337 return TRUE;
3338}
3339
3340/* Return the .iplt information for local symbol R_SYMNDX, which belongs
3341 to input bfd ABFD. Create the information if it doesn't already exist.
3342 Return null if an allocation fails. */
3343
3344static struct arm_local_iplt_info *
3345elf32_arm_create_local_iplt (bfd *abfd, unsigned long r_symndx)
3346{
3347 struct arm_local_iplt_info **ptr;
3348
3349 if (!elf32_arm_allocate_local_sym_info (abfd))
3350 return NULL;
3351
3352 BFD_ASSERT (r_symndx < elf_tdata (abfd)->symtab_hdr.sh_info);
3353 ptr = &elf32_arm_local_iplt (abfd)[r_symndx];
3354 if (*ptr == NULL)
3355 *ptr = bfd_zalloc (abfd, sizeof (**ptr));
3356 return *ptr;
3357}
3358
3359/* Try to obtain PLT information for the symbol with index R_SYMNDX
3360 in ABFD's symbol table. If the symbol is global, H points to its
3361 hash table entry, otherwise H is null.
3362
3363 Return true if the symbol does have PLT information. When returning
3364 true, point *ROOT_PLT at the target-independent reference count/offset
3365 union and *ARM_PLT at the ARM-specific information. */
3366
3367static bfd_boolean
4ba2ef8f
TP		 3368elf32_arm_get_plt_info (bfd *abfd, struct elf32_arm_link_hash_table *globals,
3369 struct elf32_arm_link_hash_entry *h,
34e77a92
RS		 3370 unsigned long r_symndx, union gotplt_union **root_plt,
3371 struct arm_plt_info **arm_plt)
3372{
3373 struct arm_local_iplt_info *local_iplt;
3374
4ba2ef8f
TP		 3375 if (globals->root.splt == NULL && globals->root.iplt == NULL)
3376 return FALSE;
3377
34e77a92
RS		 3378 if (h != NULL)
3379 {
3380 *root_plt = &h->root.plt;
3381 *arm_plt = &h->plt;
3382 return TRUE;
3383 }
3384
3385 if (elf32_arm_local_iplt (abfd) == NULL)
3386 return FALSE;
3387
3388 local_iplt = elf32_arm_local_iplt (abfd)[r_symndx];
3389 if (local_iplt == NULL)
3390 return FALSE;
3391
3392 *root_plt = &local_iplt->root;
3393 *arm_plt = &local_iplt->arm;
3394 return TRUE;
3395}
3396
3397/* Return true if the PLT described by ARM_PLT requires a Thumb stub
3398 before it. */
3399
3400static bfd_boolean
3401elf32_arm_plt_needs_thumb_stub_p (struct bfd_link_info *info,
3402 struct arm_plt_info *arm_plt)
3403{
3404 struct elf32_arm_link_hash_table *htab;
3405
3406 htab = elf32_arm_hash_table (info);
3407 return (arm_plt->thumb_refcount != 0
3408 || (!htab->use_blx && arm_plt->maybe_thumb_refcount != 0));
3409}
3410
3411/* Return a pointer to the head of the dynamic reloc list that should
3412 be used for local symbol ISYM, which is symbol number R_SYMNDX in
3413 ABFD's symbol table. Return null if an error occurs. */
3414
3415static struct elf_dyn_relocs **
3416elf32_arm_get_local_dynreloc_list (bfd *abfd, unsigned long r_symndx,
3417 Elf_Internal_Sym *isym)
3418{
3419 if (ELF32_ST_TYPE (isym->st_info) == STT_GNU_IFUNC)
3420 {
3421 struct arm_local_iplt_info *local_iplt;
3422
3423 local_iplt = elf32_arm_create_local_iplt (abfd, r_symndx);
3424 if (local_iplt == NULL)
3425 return NULL;
3426 return &local_iplt->dyn_relocs;
3427 }
3428 else
3429 {
3430 /* Track dynamic relocs needed for local syms too.
3431 We really need local syms available to do this
3432 easily. Oh well. */
3433 asection *s;
3434 void *vpp;
3435
3436 s = bfd_section_from_elf_index (abfd, isym->st_shndx);
3437 if (s == NULL)
3438 abort ();
3439
3440 vpp = &elf_section_data (s)->local_dynrel;
3441 return (struct elf_dyn_relocs **) vpp;
3442 }
3443}
3444
906e58ca
NC		 3445/* Initialize an entry in the stub hash table. */
3446
3447static struct bfd_hash_entry *
3448stub_hash_newfunc (struct bfd_hash_entry *entry,
3449 struct bfd_hash_table *table,
3450 const char *string)
3451{
3452 /* Allocate the structure if it has not already been allocated by a
3453 subclass. */
3454 if (entry == NULL)
3455 {
21d799b5 3456 entry = (struct bfd_hash_entry *)
99059e56 3457 bfd_hash_allocate (table, sizeof (struct elf32_arm_stub_hash_entry));
906e58ca
NC		 3458 if (entry == NULL)
3459 return entry;
3460 }
3461
3462 /* Call the allocation method of the superclass. */
3463 entry = bfd_hash_newfunc (entry, table, string);
3464 if (entry != NULL)
3465 {
3466 struct elf32_arm_stub_hash_entry *eh;
3467
3468 /* Initialize the local fields. */
3469 eh = (struct elf32_arm_stub_hash_entry *) entry;
3470 eh->stub_sec = NULL;
0955507f 3471 eh->stub_offset = (bfd_vma) -1;
8d9d9490 3472 eh->source_value = 0;
906e58ca
NC		 3473 eh->target_value = 0;
3474 eh->target_section = NULL;
cedfb179 3475 eh->orig_insn = 0;
906e58ca 3476 eh->stub_type = arm_stub_none;
461a49ca
DJ		 3477 eh->stub_size = 0;
3478 eh->stub_template = NULL;
0955507f 3479 eh->stub_template_size = -1;
906e58ca
NC		 3480 eh->h = NULL;
3481 eh->id_sec = NULL;
d8d2f433 3482 eh->output_name = NULL;
906e58ca
NC		 3483 }
3484
3485 return entry;
3486}
3487
00a97672 3488/* Create .got, .gotplt, and .rel(a).got sections in DYNOBJ, and set up
5e681ec4
PB		 3489 shortcuts to them in our hash table. */
3490
3491static bfd_boolean
57e8b36a 3492create_got_section (bfd *dynobj, struct bfd_link_info *info)
5e681ec4
PB		 3493{
3494 struct elf32_arm_link_hash_table *htab;
3495
e5a52504 3496 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 3497 if (htab == NULL)
3498 return FALSE;
3499
e5a52504
MM		 3500 /* BPABI objects never have a GOT, or associated sections. */
3501 if (htab->symbian_p)
3502 return TRUE;
3503
5e681ec4
PB		 3504 if (! _bfd_elf_create_got_section (dynobj, info))
3505 return FALSE;
3506
5e681ec4
PB		 3507 return TRUE;
3508}
3509
34e77a92
RS		 3510/* Create the .iplt, .rel(a).iplt and .igot.plt sections. */
3511
3512static bfd_boolean
3513create_ifunc_sections (struct bfd_link_info *info)
3514{
3515 struct elf32_arm_link_hash_table *htab;
3516 const struct elf_backend_data *bed;
3517 bfd *dynobj;
3518 asection *s;
3519 flagword flags;
b38cadfb 3520
34e77a92
RS		 3521 htab = elf32_arm_hash_table (info);
3522 dynobj = htab->root.dynobj;
3523 bed = get_elf_backend_data (dynobj);
3524 flags = bed->dynamic_sec_flags;
3525
3526 if (htab->root.iplt == NULL)
3527 {
3d4d4302
AM		 3528 s = bfd_make_section_anyway_with_flags (dynobj, ".iplt",
3529 flags | SEC_READONLY | SEC_CODE);
34e77a92 3530 if (s == NULL
a0f49396 3531 || !bfd_set_section_alignment (dynobj, s, bed->plt_alignment))
34e77a92
RS		 3532 return FALSE;
3533 htab->root.iplt = s;
3534 }
3535
3536 if (htab->root.irelplt == NULL)
3537 {
3d4d4302
AM		 3538 s = bfd_make_section_anyway_with_flags (dynobj,
3539 RELOC_SECTION (htab, ".iplt"),
3540 flags | SEC_READONLY);
34e77a92 3541 if (s == NULL
a0f49396 3542 || !bfd_set_section_alignment (dynobj, s, bed->s->log_file_align))
34e77a92
RS		 3543 return FALSE;
3544 htab->root.irelplt = s;
3545 }
3546
3547 if (htab->root.igotplt == NULL)
3548 {
3d4d4302 3549 s = bfd_make_section_anyway_with_flags (dynobj, ".igot.plt", flags);
34e77a92
RS		 3550 if (s == NULL
3551 || !bfd_set_section_alignment (dynobj, s, bed->s->log_file_align))
3552 return FALSE;
3553 htab->root.igotplt = s;
3554 }
3555 return TRUE;
3556}
3557
eed94f8f
NC		 3558/* Determine if we're dealing with a Thumb only architecture. */
3559
3560static bfd_boolean
3561using_thumb_only (struct elf32_arm_link_hash_table *globals)
3562{
2fd158eb
TP		 3563 int arch;
3564 int profile = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC,
3565 Tag_CPU_arch_profile);
eed94f8f 3566
2fd158eb
TP		 3567 if (profile)
3568 return profile == 'M';
eed94f8f 3569
2fd158eb 3570 arch = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC, Tag_CPU_arch);
eed94f8f 3571
60a019a0
TP		 3572 /* Force return logic to be reviewed for each new architecture. */
3573 BFD_ASSERT (arch <= TAG_CPU_ARCH_V8
3574 || arch == TAG_CPU_ARCH_V8M_BASE
3575 || arch == TAG_CPU_ARCH_V8M_MAIN);
3576
2fd158eb
TP		 3577 if (arch == TAG_CPU_ARCH_V6_M
3578 || arch == TAG_CPU_ARCH_V6S_M
3579 || arch == TAG_CPU_ARCH_V7E_M
3580 || arch == TAG_CPU_ARCH_V8M_BASE
3581 || arch == TAG_CPU_ARCH_V8M_MAIN)
3582 return TRUE;
eed94f8f 3583
2fd158eb 3584 return FALSE;
eed94f8f
NC		 3585}
3586
3587/* Determine if we're dealing with a Thumb-2 object. */
3588
3589static bfd_boolean
3590using_thumb2 (struct elf32_arm_link_hash_table *globals)
3591{
60a019a0
TP		 3592 int arch;
3593 int thumb_isa = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC,
3594 Tag_THUMB_ISA_use);
3595
3596 if (thumb_isa)
3597 return thumb_isa == 2;
3598
3599 arch = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC, Tag_CPU_arch);
3600
3601 /* Force return logic to be reviewed for each new architecture. */
3602 BFD_ASSERT (arch <= TAG_CPU_ARCH_V8
3603 || arch == TAG_CPU_ARCH_V8M_BASE
3604 || arch == TAG_CPU_ARCH_V8M_MAIN);
3605
3606 return (arch == TAG_CPU_ARCH_V6T2
3607 || arch == TAG_CPU_ARCH_V7
3608 || arch == TAG_CPU_ARCH_V7E_M
3609 || arch == TAG_CPU_ARCH_V8
3610 || arch == TAG_CPU_ARCH_V8M_MAIN);
eed94f8f
NC		 3611}
3612
5e866f5a
TP		 3613/* Determine whether Thumb-2 BL instruction is available. */
3614
3615static bfd_boolean
3616using_thumb2_bl (struct elf32_arm_link_hash_table *globals)
3617{
3618 int arch =
3619 bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC, Tag_CPU_arch);
3620
3621 /* Force return logic to be reviewed for each new architecture. */
3622 BFD_ASSERT (arch <= TAG_CPU_ARCH_V8
3623 || arch == TAG_CPU_ARCH_V8M_BASE
3624 || arch == TAG_CPU_ARCH_V8M_MAIN);
3625
3626 /* Architecture was introduced after ARMv6T2 (eg. ARMv6-M). */
3627 return (arch == TAG_CPU_ARCH_V6T2
3628 || arch >= TAG_CPU_ARCH_V7);
3629}
3630
00a97672
RS		 3631/* Create .plt, .rel(a).plt, .got, .got.plt, .rel(a).got, .dynbss, and
3632 .rel(a).bss sections in DYNOBJ, and set up shortcuts to them in our
5e681ec4
PB		 3633 hash table. */
3634
3635static bfd_boolean
57e8b36a 3636elf32_arm_create_dynamic_sections (bfd *dynobj, struct bfd_link_info *info)
5e681ec4
PB		 3637{
3638 struct elf32_arm_link_hash_table *htab;
3639
3640 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 3641 if (htab == NULL)
3642 return FALSE;
3643
362d30a1 3644 if (!htab->root.sgot && !create_got_section (dynobj, info))
5e681ec4
PB		 3645 return FALSE;
3646
3647 if (!_bfd_elf_create_dynamic_sections (dynobj, info))
3648 return FALSE;
3649
3d4d4302 3650 htab->sdynbss = bfd_get_linker_section (dynobj, ".dynbss");
0e1862bb 3651 if (!bfd_link_pic (info))
3d4d4302
AM		 3652 htab->srelbss = bfd_get_linker_section (dynobj,
3653 RELOC_SECTION (htab, ".bss"));
00a97672
RS		 3654
3655 if (htab->vxworks_p)
3656 {
3657 if (!elf_vxworks_create_dynamic_sections (dynobj, info, &htab->srelplt2))
3658 return FALSE;
3659
0e1862bb 3660 if (bfd_link_pic (info))
00a97672
RS		 3661 {
3662 htab->plt_header_size = 0;
3663 htab->plt_entry_size
3664 = 4 * ARRAY_SIZE (elf32_arm_vxworks_shared_plt_entry);
3665 }
3666 else
3667 {
3668 htab->plt_header_size
3669 = 4 * ARRAY_SIZE (elf32_arm_vxworks_exec_plt0_entry);
3670 htab->plt_entry_size
3671 = 4 * ARRAY_SIZE (elf32_arm_vxworks_exec_plt_entry);
3672 }
aebf9be7
NC		 3673
3674 if (elf_elfheader (dynobj))
3675 elf_elfheader (dynobj)->e_ident[EI_CLASS] = ELFCLASS32;
00a97672 3676 }
eed94f8f
NC		 3677 else
3678 {
3679 /* PR ld/16017
3680 Test for thumb only architectures. Note - we cannot just call
3681 using_thumb_only() as the attributes in the output bfd have not been
3682 initialised at this point, so instead we use the input bfd. */
3683 bfd * saved_obfd = htab->obfd;
3684
3685 htab->obfd = dynobj;
3686 if (using_thumb_only (htab))
3687 {
3688 htab->plt_header_size = 4 * ARRAY_SIZE (elf32_thumb2_plt0_entry);
3689 htab->plt_entry_size = 4 * ARRAY_SIZE (elf32_thumb2_plt_entry);
3690 }
3691 htab->obfd = saved_obfd;
3692 }
5e681ec4 3693
362d30a1
RS		 3694 if (!htab->root.splt
3695 || !htab->root.srelplt
e5a52504 3696 || !htab->sdynbss
0e1862bb 3697 || (!bfd_link_pic (info) && !htab->srelbss))
5e681ec4
PB		 3698 abort ();
3699
3700 return TRUE;
3701}
3702
906e58ca
NC		 3703/* Copy the extra info we tack onto an elf_link_hash_entry. */
3704
3705static void
3706elf32_arm_copy_indirect_symbol (struct bfd_link_info *info,
3707 struct elf_link_hash_entry *dir,
3708 struct elf_link_hash_entry *ind)
3709{
3710 struct elf32_arm_link_hash_entry *edir, *eind;
3711
3712 edir = (struct elf32_arm_link_hash_entry *) dir;
3713 eind = (struct elf32_arm_link_hash_entry *) ind;
3714
0bdcacaf 3715 if (eind->dyn_relocs != NULL)
906e58ca 3716 {
0bdcacaf 3717 if (edir->dyn_relocs != NULL)
906e58ca 3718 {
0bdcacaf
RS		 3719 struct elf_dyn_relocs **pp;
3720 struct elf_dyn_relocs *p;
906e58ca
NC		 3721
3722 /* Add reloc counts against the indirect sym to the direct sym
3723 list. Merge any entries against the same section. */
0bdcacaf 3724 for (pp = &eind->dyn_relocs; (p = *pp) != NULL; )
906e58ca 3725 {
0bdcacaf 3726 struct elf_dyn_relocs *q;
906e58ca 3727
0bdcacaf
RS		 3728 for (q = edir->dyn_relocs; q != NULL; q = q->next)
3729 if (q->sec == p->sec)
906e58ca
NC		 3730 {
3731 q->pc_count += p->pc_count;
3732 q->count += p->count;
3733 *pp = p->next;
3734 break;
3735 }
3736 if (q == NULL)
3737 pp = &p->next;
3738 }
0bdcacaf 3739 *pp = edir->dyn_relocs;
906e58ca
NC		 3740 }
3741
0bdcacaf
RS		 3742 edir->dyn_relocs = eind->dyn_relocs;
3743 eind->dyn_relocs = NULL;
906e58ca
NC		 3744 }
3745
3746 if (ind->root.type == bfd_link_hash_indirect)
3747 {
3748 /* Copy over PLT info. */
34e77a92
RS		 3749 edir->plt.thumb_refcount += eind->plt.thumb_refcount;
3750 eind->plt.thumb_refcount = 0;
3751 edir->plt.maybe_thumb_refcount += eind->plt.maybe_thumb_refcount;
3752 eind->plt.maybe_thumb_refcount = 0;
3753 edir->plt.noncall_refcount += eind->plt.noncall_refcount;
3754 eind->plt.noncall_refcount = 0;
3755
3756 /* We should only allocate a function to .iplt once the final
3757 symbol information is known. */
3758 BFD_ASSERT (!eind->is_iplt);
906e58ca
NC		 3759
3760 if (dir->got.refcount <= 0)
3761 {
3762 edir->tls_type = eind->tls_type;
3763 eind->tls_type = GOT_UNKNOWN;
3764 }
3765 }
3766
3767 _bfd_elf_link_hash_copy_indirect (info, dir, ind);
3768}
3769
68faa637
AM		 3770/* Destroy an ARM elf linker hash table. */
3771
3772static void
d495ab0d 3773elf32_arm_link_hash_table_free (bfd *obfd)
68faa637
AM		 3774{
3775 struct elf32_arm_link_hash_table *ret
d495ab0d 3776 = (struct elf32_arm_link_hash_table *) obfd->link.hash;
68faa637
AM		 3777
3778 bfd_hash_table_free (&ret->stub_hash_table);
d495ab0d 3779 _bfd_elf_link_hash_table_free (obfd);
68faa637
AM		 3780}
3781
906e58ca
NC		 3782/* Create an ARM elf linker hash table. */
3783
3784static struct bfd_link_hash_table *
3785elf32_arm_link_hash_table_create (bfd *abfd)
3786{
3787 struct elf32_arm_link_hash_table *ret;
3788 bfd_size_type amt = sizeof (struct elf32_arm_link_hash_table);
3789
7bf52ea2 3790 ret = (struct elf32_arm_link_hash_table *) bfd_zmalloc (amt);
906e58ca
NC		 3791 if (ret == NULL)
3792 return NULL;
3793
3794 if (!_bfd_elf_link_hash_table_init (& ret->root, abfd,
3795 elf32_arm_link_hash_newfunc,
4dfe6ac6
NC		 3796 sizeof (struct elf32_arm_link_hash_entry),
3797 ARM_ELF_DATA))
906e58ca
NC		 3798 {
3799 free (ret);
3800 return NULL;
3801 }
3802
906e58ca 3803 ret->vfp11_fix = BFD_ARM_VFP11_FIX_NONE;
a504d23a 3804 ret->stm32l4xx_fix = BFD_ARM_STM32L4XX_FIX_NONE;
906e58ca
NC		 3805#ifdef FOUR_WORD_PLT
3806 ret->plt_header_size = 16;
3807 ret->plt_entry_size = 16;
3808#else
3809 ret->plt_header_size = 20;
1db37fe6 3810 ret->plt_entry_size = elf32_arm_use_long_plt_entry ? 16 : 12;
906e58ca 3811#endif
906e58ca 3812 ret->use_rel = 1;
906e58ca 3813 ret->obfd = abfd;
906e58ca
NC		 3814
3815 if (!bfd_hash_table_init (&ret->stub_hash_table, stub_hash_newfunc,
3816 sizeof (struct elf32_arm_stub_hash_entry)))
3817 {
d495ab0d 3818 _bfd_elf_link_hash_table_free (abfd);
906e58ca
NC		 3819 return NULL;
3820 }
d495ab0d 3821 ret->root.root.hash_table_free = elf32_arm_link_hash_table_free;
906e58ca
NC		 3822
3823 return &ret->root.root;
3824}
3825
cd1dac3d
DG		 3826/* Determine what kind of NOPs are available. */
3827
3828static bfd_boolean
3829arch_has_arm_nop (struct elf32_arm_link_hash_table *globals)
3830{
3831 const int arch = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC,
3832 Tag_CPU_arch);
cd1dac3d 3833
60a019a0
TP		 3834 /* Force return logic to be reviewed for each new architecture. */
3835 BFD_ASSERT (arch <= TAG_CPU_ARCH_V8
3836 || arch == TAG_CPU_ARCH_V8M_BASE
3837 || arch == TAG_CPU_ARCH_V8M_MAIN);
3838
3839 return (arch == TAG_CPU_ARCH_V6T2
3840 || arch == TAG_CPU_ARCH_V6K
3841 || arch == TAG_CPU_ARCH_V7
3842 || arch == TAG_CPU_ARCH_V8);
cd1dac3d
DG		 3843}
3844
f4ac8484
DJ		 3845static bfd_boolean
3846arm_stub_is_thumb (enum elf32_arm_stub_type stub_type)
3847{
3848 switch (stub_type)
3849 {
fea2b4d6 3850 case arm_stub_long_branch_thumb_only:
80c135e5 3851 case arm_stub_long_branch_thumb2_only:
d5a67c02 3852 case arm_stub_long_branch_thumb2_only_pure:
fea2b4d6
CL		 3853 case arm_stub_long_branch_v4t_thumb_arm:
3854 case arm_stub_short_branch_v4t_thumb_arm:
ebe24dd4 3855 case arm_stub_long_branch_v4t_thumb_arm_pic:
12352d3f 3856 case arm_stub_long_branch_v4t_thumb_tls_pic:
ebe24dd4 3857 case arm_stub_long_branch_thumb_only_pic:
4ba2ef8f 3858 case arm_stub_cmse_branch_thumb_only:
f4ac8484
DJ		 3859 return TRUE;
3860 case arm_stub_none:
3861 BFD_FAIL ();
3862 return FALSE;
3863 break;
3864 default:
3865 return FALSE;
3866 }
3867}
3868
906e58ca
NC		 3869/* Determine the type of stub needed, if any, for a call. */
3870
3871static enum elf32_arm_stub_type
3872arm_type_of_stub (struct bfd_link_info *info,
3873 asection *input_sec,
3874 const Elf_Internal_Rela *rel,
34e77a92 3875 unsigned char st_type,
35fc36a8 3876 enum arm_st_branch_type *actual_branch_type,
906e58ca 3877 struct elf32_arm_link_hash_entry *hash,
c820be07
NC		 3878 bfd_vma destination,
3879 asection *sym_sec,
3880 bfd *input_bfd,
3881 const char *name)
906e58ca
NC		 3882{
3883 bfd_vma location;
3884 bfd_signed_vma branch_offset;
3885 unsigned int r_type;
3886 struct elf32_arm_link_hash_table * globals;
5e866f5a 3887 bfd_boolean thumb2, thumb2_bl, thumb_only;
906e58ca 3888 enum elf32_arm_stub_type stub_type = arm_stub_none;
5fa9e92f 3889 int use_plt = 0;
35fc36a8 3890 enum arm_st_branch_type branch_type = *actual_branch_type;
34e77a92
RS		 3891 union gotplt_union *root_plt;
3892 struct arm_plt_info *arm_plt;
d5a67c02
AV		 3893 int arch;
3894 int thumb2_movw;
906e58ca 3895
35fc36a8 3896 if (branch_type == ST_BRANCH_LONG)
da5938a2
NC		 3897 return stub_type;
3898
906e58ca 3899 globals = elf32_arm_hash_table (info);
4dfe6ac6
NC		 3900 if (globals == NULL)
3901 return stub_type;
906e58ca
NC		 3902
3903 thumb_only = using_thumb_only (globals);
906e58ca 3904 thumb2 = using_thumb2 (globals);
5e866f5a 3905 thumb2_bl = using_thumb2_bl (globals);
906e58ca 3906
d5a67c02
AV		 3907 arch = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC, Tag_CPU_arch);
3908
3909 /* True for architectures that implement the thumb2 movw instruction. */
3910 thumb2_movw = thumb2 || (arch == TAG_CPU_ARCH_V8M_BASE);
3911
906e58ca
NC		 3912 /* Determine where the call point is. */
3913 location = (input_sec->output_offset
3914 + input_sec->output_section->vma
3915 + rel->r_offset);
3916
906e58ca
NC		 3917 r_type = ELF32_R_TYPE (rel->r_info);
3918
39f21624
NC		 3919 /* ST_BRANCH_TO_ARM is nonsense to thumb-only targets when we
3920 are considering a function call relocation. */
c5423981
TG		 3921 if (thumb_only && (r_type == R_ARM_THM_CALL || r_type == R_ARM_THM_JUMP24
3922 || r_type == R_ARM_THM_JUMP19)
39f21624
NC		 3923 && branch_type == ST_BRANCH_TO_ARM)
3924 branch_type = ST_BRANCH_TO_THUMB;
3925
34e77a92
RS		 3926 /* For TLS call relocs, it is the caller's responsibility to provide
3927 the address of the appropriate trampoline. */
3928 if (r_type != R_ARM_TLS_CALL
3929 && r_type != R_ARM_THM_TLS_CALL
4ba2ef8f
TP		 3930 && elf32_arm_get_plt_info (input_bfd, globals, hash,
3931 ELF32_R_SYM (rel->r_info), &root_plt,
3932 &arm_plt)
34e77a92 3933 && root_plt->offset != (bfd_vma) -1)
5fa9e92f 3934 {
34e77a92 3935 asection *splt;
fe33d2fa 3936
34e77a92
RS		 3937 if (hash == NULL || hash->is_iplt)
3938 splt = globals->root.iplt;
3939 else
3940 splt = globals->root.splt;
3941 if (splt != NULL)
b38cadfb 3942 {
34e77a92
RS		 3943 use_plt = 1;
3944
3945 /* Note when dealing with PLT entries: the main PLT stub is in
3946 ARM mode, so if the branch is in Thumb mode, another
3947 Thumb->ARM stub will be inserted later just before the ARM
2df2751d
CL		 3948 PLT stub. If a long branch stub is needed, we'll add a
3949 Thumb->Arm one and branch directly to the ARM PLT entry.
3950 Here, we have to check if a pre-PLT Thumb->ARM stub
3951 is needed and if it will be close enough. */
34e77a92
RS		 3952
3953 destination = (splt->output_section->vma
3954 + splt->output_offset
3955 + root_plt->offset);
3956 st_type = STT_FUNC;
2df2751d
CL		 3957
3958 /* Thumb branch/call to PLT: it can become a branch to ARM
3959 or to Thumb. We must perform the same checks and
3960 corrections as in elf32_arm_final_link_relocate. */
3961 if ((r_type == R_ARM_THM_CALL)
3962 || (r_type == R_ARM_THM_JUMP24))
3963 {
3964 if (globals->use_blx
3965 && r_type == R_ARM_THM_CALL
3966 && !thumb_only)
3967 {
3968 /* If the Thumb BLX instruction is available, convert
3969 the BL to a BLX instruction to call the ARM-mode
3970 PLT entry. */
3971 branch_type = ST_BRANCH_TO_ARM;
3972 }
3973 else
3974 {
3975 if (!thumb_only)
3976 /* Target the Thumb stub before the ARM PLT entry. */
3977 destination -= PLT_THUMB_STUB_SIZE;
3978 branch_type = ST_BRANCH_TO_THUMB;
3979 }
3980 }
3981 else
3982 {
3983 branch_type = ST_BRANCH_TO_ARM;
3984 }
34e77a92 3985 }
5fa9e92f 3986 }
34e77a92
RS		 3987 /* Calls to STT_GNU_IFUNC symbols should go through a PLT. */
3988 BFD_ASSERT (st_type != STT_GNU_IFUNC);
906e58ca 3989
fe33d2fa
CL		 3990 branch_offset = (bfd_signed_vma)(destination - location);
3991
0855e32b 3992 if (r_type == R_ARM_THM_CALL || r_type == R_ARM_THM_JUMP24
c5423981 3993 || r_type == R_ARM_THM_TLS_CALL || r_type == R_ARM_THM_JUMP19)
906e58ca 3994 {
5fa9e92f
CL		 3995 /* Handle cases where:
3996 - this call goes too far (different Thumb/Thumb2 max
99059e56 3997 distance)
155d87d7 3998 - it's a Thumb->Arm call and blx is not available, or it's a
99059e56
RM		 3999 Thumb->Arm branch (not bl). A stub is needed in this case,
4000 but only if this call is not through a PLT entry. Indeed,
4001 PLT stubs handle mode switching already.
5fa9e92f 4002 */
5e866f5a 4003 if ((!thumb2_bl
906e58ca
NC		 4004 && (branch_offset > THM_MAX_FWD_BRANCH_OFFSET
4005 || (branch_offset < THM_MAX_BWD_BRANCH_OFFSET)))
5e866f5a 4006 || (thumb2_bl
906e58ca
NC		 4007 && (branch_offset > THM2_MAX_FWD_BRANCH_OFFSET
4008 || (branch_offset < THM2_MAX_BWD_BRANCH_OFFSET)))
c5423981
TG		 4009 || (thumb2
4010 && (branch_offset > THM2_MAX_FWD_COND_BRANCH_OFFSET
4011 || (branch_offset < THM2_MAX_BWD_COND_BRANCH_OFFSET))
4012 && (r_type == R_ARM_THM_JUMP19))
35fc36a8 4013 || (branch_type == ST_BRANCH_TO_ARM
0855e32b
NS		 4014 && (((r_type == R_ARM_THM_CALL
4015 || r_type == R_ARM_THM_TLS_CALL) && !globals->use_blx)
c5423981
TG		 4016 || (r_type == R_ARM_THM_JUMP24)
4017 || (r_type == R_ARM_THM_JUMP19))
5fa9e92f 4018 && !use_plt))
906e58ca 4019 {
2df2751d
CL		 4020 /* If we need to insert a Thumb-Thumb long branch stub to a
4021 PLT, use one that branches directly to the ARM PLT
4022 stub. If we pretended we'd use the pre-PLT Thumb->ARM
4023 stub, undo this now. */
4024 if ((branch_type == ST_BRANCH_TO_THUMB) && use_plt && !thumb_only) {
4025 branch_type = ST_BRANCH_TO_ARM;
4026 branch_offset += PLT_THUMB_STUB_SIZE;
4027 }
4028
35fc36a8 4029 if (branch_type == ST_BRANCH_TO_THUMB)
906e58ca
NC		 4030 {
4031 /* Thumb to thumb. */
4032 if (!thumb_only)
4033 {
d5a67c02 4034 if (input_sec->flags & SEC_ELF_PURECODE)
4eca0228
AM		 4035 _bfd_error_handler (_("%B(%s): warning: long branch "
4036 " veneers used in section with "
4037 "SHF_ARM_PURECODE section "
4038 "attribute is only supported"
4039 " for M-profile targets that "
4040 "implement the movw "
4041 "instruction."));
d5a67c02 4042
0e1862bb 4043 stub_type = (bfd_link_pic (info) | globals->pic_veneer)
c2b4a39d 4044 /* PIC stubs. */
155d87d7 4045 ? ((globals->use_blx
9553db3c 4046 && (r_type == R_ARM_THM_CALL))
155d87d7
CL		 4047 /* V5T and above. Stub starts with ARM code, so
4048 we must be able to switch mode before
4049 reaching it, which is only possible for 'bl'
4050 (ie R_ARM_THM_CALL relocation). */
cf3eccff 4051 ? arm_stub_long_branch_any_thumb_pic
ebe24dd4 4052 /* On V4T, use Thumb code only. */
d3626fb0 4053 : arm_stub_long_branch_v4t_thumb_thumb_pic)
c2b4a39d
CL		 4054
4055 /* non-PIC stubs. */
155d87d7 4056 : ((globals->use_blx
9553db3c 4057 && (r_type == R_ARM_THM_CALL))
c2b4a39d
CL		 4058 /* V5T and above. */
4059 ? arm_stub_long_branch_any_any
4060 /* V4T. */
d3626fb0 4061 : arm_stub_long_branch_v4t_thumb_thumb);
906e58ca
NC		 4062 }
4063 else
4064 {
d5a67c02
AV		 4065 if (thumb2_movw && (input_sec->flags & SEC_ELF_PURECODE))
4066 stub_type = arm_stub_long_branch_thumb2_only_pure;
4067 else
4068 {
4069 if (input_sec->flags & SEC_ELF_PURECODE)
4eca0228
AM		 4070 _bfd_error_handler (_("%B(%s): warning: long branch "
4071 " veneers used in section with "
4072 "SHF_ARM_PURECODE section "
4073 "attribute is only supported"
4074 " for M-profile targets that "
4075 "implement the movw "
4076 "instruction."));
d5a67c02
AV		 4077
4078 stub_type = (bfd_link_pic (info) | globals->pic_veneer)
4079 /* PIC stub. */
4080 ? arm_stub_long_branch_thumb_only_pic
4081 /* non-PIC stub. */
4082 : (thumb2 ? arm_stub_long_branch_thumb2_only
4083 : arm_stub_long_branch_thumb_only);
4084 }
906e58ca
NC		 4085 }
4086 }
4087 else
4088 {
d5a67c02 4089 if (input_sec->flags & SEC_ELF_PURECODE)
4eca0228
AM		 4090 _bfd_error_handler (_("%B(%s): warning: long branch "
4091 " veneers used in section with "
4092 "SHF_ARM_PURECODE section "
4093 "attribute is only supported"
4094 " for M-profile targets that "
4095 "implement the movw "
4096 "instruction."));
d5a67c02 4097
906e58ca 4098 /* Thumb to arm. */
c820be07
NC		 4099 if (sym_sec != NULL
4100 && sym_sec->owner != NULL
4101 && !INTERWORK_FLAG (sym_sec->owner))
4102 {
4eca0228 4103 _bfd_error_handler
c820be07
NC		 4104 (_("%B(%s): warning: interworking not enabled.\n"
4105 " first occurrence: %B: Thumb call to ARM"),
4106 sym_sec->owner, input_bfd, name);
4107 }
4108
0855e32b 4109 stub_type =
0e1862bb 4110 (bfd_link_pic (info) | globals->pic_veneer)
c2b4a39d 4111 /* PIC stubs. */
0855e32b 4112 ? (r_type == R_ARM_THM_TLS_CALL
6a631e86 4113 /* TLS PIC stubs. */
0855e32b
NS		 4114 ? (globals->use_blx ? arm_stub_long_branch_any_tls_pic
4115 : arm_stub_long_branch_v4t_thumb_tls_pic)
4116 : ((globals->use_blx && r_type == R_ARM_THM_CALL)
4117 /* V5T PIC and above. */
4118 ? arm_stub_long_branch_any_arm_pic
4119 /* V4T PIC stub. */
4120 : arm_stub_long_branch_v4t_thumb_arm_pic))
c2b4a39d
CL		 4121
4122 /* non-PIC stubs. */
0855e32b 4123 : ((globals->use_blx && r_type == R_ARM_THM_CALL)
c2b4a39d
CL		 4124 /* V5T and above. */
4125 ? arm_stub_long_branch_any_any
4126 /* V4T. */
4127 : arm_stub_long_branch_v4t_thumb_arm);
c820be07
NC		 4128
4129 /* Handle v4t short branches. */
fea2b4d6 4130 if ((stub_type == arm_stub_long_branch_v4t_thumb_arm)
c820be07
NC		 4131 && (branch_offset <= THM_MAX_FWD_BRANCH_OFFSET)
4132 && (branch_offset >= THM_MAX_BWD_BRANCH_OFFSET))
fea2b4d6 4133 stub_type = arm_stub_short_branch_v4t_thumb_arm;
906e58ca
NC		 4134 }
4135 }
4136 }
fe33d2fa
CL		 4137 else if (r_type == R_ARM_CALL
4138 || r_type == R_ARM_JUMP24
0855e32b
NS		 4139 || r_type == R_ARM_PLT32
4140 || r_type == R_ARM_TLS_CALL)
906e58ca 4141 {
d5a67c02 4142 if (input_sec->flags & SEC_ELF_PURECODE)
4eca0228
AM		 4143 _bfd_error_handler (_("%B(%s): warning: long branch "
4144 " veneers used in section with "
4145 "SHF_ARM_PURECODE section "
4146 "attribute is only supported"
4147 " for M-profile targets that "
4148 "implement the movw "
4149 "instruction."));
35fc36a8 4150 if (branch_type == ST_BRANCH_TO_THUMB)
906e58ca
NC		 4151 {
4152 /* Arm to thumb. */
c820be07
NC		 4153
4154 if (sym_sec != NULL
4155 && sym_sec->owner != NULL
4156 && !INTERWORK_FLAG (sym_sec->owner))
4157 {
4eca0228 4158 _bfd_error_handler
c820be07 4159 (_("%B(%s): warning: interworking not enabled.\n"
c2b4a39d 4160 " first occurrence: %B: ARM call to Thumb"),
c820be07
NC		 4161 sym_sec->owner, input_bfd, name);
4162 }
4163
4164 /* We have an extra 2-bytes reach because of
4165 the mode change (bit 24 (H) of BLX encoding). */
4116d8d7
PB		 4166 if (branch_offset > (ARM_MAX_FWD_BRANCH_OFFSET + 2)
4167 || (branch_offset < ARM_MAX_BWD_BRANCH_OFFSET)
0855e32b 4168 || (r_type == R_ARM_CALL && !globals->use_blx)
4116d8d7
PB		 4169 || (r_type == R_ARM_JUMP24)
4170 || (r_type == R_ARM_PLT32))
906e58ca 4171 {
0e1862bb 4172 stub_type = (bfd_link_pic (info) | globals->pic_veneer)
c2b4a39d 4173 /* PIC stubs. */
ebe24dd4
CL		 4174 ? ((globals->use_blx)
4175 /* V5T and above. */
4176 ? arm_stub_long_branch_any_thumb_pic
4177 /* V4T stub. */
4178 : arm_stub_long_branch_v4t_arm_thumb_pic)
4179
c2b4a39d
CL		 4180 /* non-PIC stubs. */
4181 : ((globals->use_blx)
4182 /* V5T and above. */
4183 ? arm_stub_long_branch_any_any
4184 /* V4T. */
4185 : arm_stub_long_branch_v4t_arm_thumb);
906e58ca
NC		 4186 }
4187 }
4188 else
4189 {
4190 /* Arm to arm. */
4191 if (branch_offset > ARM_MAX_FWD_BRANCH_OFFSET
4192 || (branch_offset < ARM_MAX_BWD_BRANCH_OFFSET))
4193 {
0855e32b 4194 stub_type =
0e1862bb 4195 (bfd_link_pic (info) | globals->pic_veneer)
c2b4a39d 4196 /* PIC stubs. */
0855e32b 4197 ? (r_type == R_ARM_TLS_CALL
6a631e86 4198 /* TLS PIC Stub. */
0855e32b 4199 ? arm_stub_long_branch_any_tls_pic
7a89b94e
NC		 4200 : (globals->nacl_p
4201 ? arm_stub_long_branch_arm_nacl_pic
4202 : arm_stub_long_branch_any_arm_pic))
c2b4a39d 4203 /* non-PIC stubs. */
7a89b94e
NC		 4204 : (globals->nacl_p
4205 ? arm_stub_long_branch_arm_nacl
4206 : arm_stub_long_branch_any_any);
906e58ca
NC		 4207 }
4208 }
4209 }
4210
fe33d2fa
CL		 4211 /* If a stub is needed, record the actual destination type. */
4212 if (stub_type != arm_stub_none)
35fc36a8 4213 *actual_branch_type = branch_type;
fe33d2fa 4214
906e58ca
NC		 4215 return stub_type;
4216}
4217
4218/* Build a name for an entry in the stub hash table. */
4219
4220static char *
4221elf32_arm_stub_name (const asection *input_section,
4222 const asection *sym_sec,
4223 const struct elf32_arm_link_hash_entry *hash,
fe33d2fa
CL		 4224 const Elf_Internal_Rela *rel,
4225 enum elf32_arm_stub_type stub_type)
906e58ca
NC		 4226{
4227 char *stub_name;
4228 bfd_size_type len;
4229
4230 if (hash)
4231 {
fe33d2fa 4232 len = 8 + 1 + strlen (hash->root.root.root.string) + 1 + 8 + 1 + 2 + 1;
21d799b5 4233 stub_name = (char *) bfd_malloc (len);
906e58ca 4234 if (stub_name != NULL)
fe33d2fa 4235 sprintf (stub_name, "%08x_%s+%x_%d",
906e58ca
NC		 4236 input_section->id & 0xffffffff,
4237 hash->root.root.root.string,
fe33d2fa
CL		 4238 (int) rel->r_addend & 0xffffffff,
4239 (int) stub_type);
906e58ca
NC		 4240 }
4241 else
4242 {
fe33d2fa 4243 len = 8 + 1 + 8 + 1 + 8 + 1 + 8 + 1 + 2 + 1;
21d799b5 4244 stub_name = (char *) bfd_malloc (len);
906e58ca 4245 if (stub_name != NULL)
fe33d2fa 4246 sprintf (stub_name, "%08x_%x:%x+%x_%d",
906e58ca
NC		 4247 input_section->id & 0xffffffff,
4248 sym_sec->id & 0xffffffff,
0855e32b
NS		 4249 ELF32_R_TYPE (rel->r_info) == R_ARM_TLS_CALL
4250 || ELF32_R_TYPE (rel->r_info) == R_ARM_THM_TLS_CALL
4251 ? 0 : (int) ELF32_R_SYM (rel->r_info) & 0xffffffff,
fe33d2fa
CL		 4252 (int) rel->r_addend & 0xffffffff,
4253 (int) stub_type);
906e58ca
NC		 4254 }
4255
4256 return stub_name;
4257}
4258
4259/* Look up an entry in the stub hash. Stub entries are cached because
4260 creating the stub name takes a bit of time. */
4261
4262static struct elf32_arm_stub_hash_entry *
4263elf32_arm_get_stub_entry (const asection *input_section,
4264 const asection *sym_sec,
4265 struct elf_link_hash_entry *hash,
4266 const Elf_Internal_Rela *rel,
fe33d2fa
CL		 4267 struct elf32_arm_link_hash_table *htab,
4268 enum elf32_arm_stub_type stub_type)
906e58ca
NC		 4269{
4270 struct elf32_arm_stub_hash_entry *stub_entry;
4271 struct elf32_arm_link_hash_entry *h = (struct elf32_arm_link_hash_entry *) hash;
4272 const asection *id_sec;
4273
4274 if ((input_section->flags & SEC_CODE) == 0)
4275 return NULL;
4276
4277 /* If this input section is part of a group of sections sharing one
4278 stub section, then use the id of the first section in the group.
4279 Stub names need to include a section id, as there may well be
4280 more than one stub used to reach say, printf, and we need to
4281 distinguish between them. */
c2abbbeb 4282 BFD_ASSERT (input_section->id <= htab->top_id);
906e58ca
NC		 4283 id_sec = htab->stub_group[input_section->id].link_sec;
4284
4285 if (h != NULL && h->stub_cache != NULL
4286 && h->stub_cache->h == h
fe33d2fa
CL		 4287 && h->stub_cache->id_sec == id_sec
4288 && h->stub_cache->stub_type == stub_type)
906e58ca
NC		 4289 {
4290 stub_entry = h->stub_cache;
4291 }
4292 else
4293 {
4294 char *stub_name;
4295
fe33d2fa 4296 stub_name = elf32_arm_stub_name (id_sec, sym_sec, h, rel, stub_type);
906e58ca
NC		 4297 if (stub_name == NULL)
4298 return NULL;
4299
4300 stub_entry = arm_stub_hash_lookup (&htab->stub_hash_table,
4301 stub_name, FALSE, FALSE);
4302 if (h != NULL)
4303 h->stub_cache = stub_entry;
4304
4305 free (stub_name);
4306 }
4307
4308 return stub_entry;
4309}
4310
daa4adae
TP		 4311/* Whether veneers of type STUB_TYPE require to be in a dedicated output
4312 section. */
4313
4314static bfd_boolean
4315arm_dedicated_stub_output_section_required (enum elf32_arm_stub_type stub_type)
4316{
4317 if (stub_type >= max_stub_type)
4318 abort (); /* Should be unreachable. */
4319
4ba2ef8f
TP		 4320 switch (stub_type)
4321 {
4322 case arm_stub_cmse_branch_thumb_only:
4323 return TRUE;
4324
4325 default:
4326 return FALSE;
4327 }
4328
4329 abort (); /* Should be unreachable. */
daa4adae
TP		 4330}
4331
4332/* Required alignment (as a power of 2) for the dedicated section holding
4333 veneers of type STUB_TYPE, or 0 if veneers of this type are interspersed
4334 with input sections. */
4335
4336static int
4337arm_dedicated_stub_output_section_required_alignment
4338 (enum elf32_arm_stub_type stub_type)
4339{
4340 if (stub_type >= max_stub_type)
4341 abort (); /* Should be unreachable. */
4342
4ba2ef8f
TP		 4343 switch (stub_type)
4344 {
4345 /* Vectors of Secure Gateway veneers must be aligned on 32byte
4346 boundary. */
4347 case arm_stub_cmse_branch_thumb_only:
4348 return 5;
4349
4350 default:
4351 BFD_ASSERT (!arm_dedicated_stub_output_section_required (stub_type));
4352 return 0;
4353 }
4354
4355 abort (); /* Should be unreachable. */
daa4adae
TP		 4356}
4357
4358/* Name of the dedicated output section to put veneers of type STUB_TYPE, or
4359 NULL if veneers of this type are interspersed with input sections. */
4360
4361static const char *
4362arm_dedicated_stub_output_section_name (enum elf32_arm_stub_type stub_type)
4363{
4364 if (stub_type >= max_stub_type)
4365 abort (); /* Should be unreachable. */
4366
4ba2ef8f
TP		 4367 switch (stub_type)
4368 {
4369 case arm_stub_cmse_branch_thumb_only:
4370 return ".gnu.sgstubs";
4371
4372 default:
4373 BFD_ASSERT (!arm_dedicated_stub_output_section_required (stub_type));
4374 return NULL;
4375 }
4376
4377 abort (); /* Should be unreachable. */
daa4adae
TP		 4378}
4379
4380/* If veneers of type STUB_TYPE should go in a dedicated output section,
4381 returns the address of the hash table field in HTAB holding a pointer to the
4382 corresponding input section. Otherwise, returns NULL. */
4383
4384static asection **
4ba2ef8f
TP		 4385arm_dedicated_stub_input_section_ptr (struct elf32_arm_link_hash_table *htab,
4386 enum elf32_arm_stub_type stub_type)
daa4adae
TP		 4387{
4388 if (stub_type >= max_stub_type)
4389 abort (); /* Should be unreachable. */
4390
4ba2ef8f
TP		 4391 switch (stub_type)
4392 {
4393 case arm_stub_cmse_branch_thumb_only:
4394 return &htab->cmse_stub_sec;
4395
4396 default:
4397 BFD_ASSERT (!arm_dedicated_stub_output_section_required (stub_type));
4398 return NULL;
4399 }
4400
4401 abort (); /* Should be unreachable. */
daa4adae
TP		 4402}
4403
4404/* Find or create a stub section to contain a stub of type STUB_TYPE. SECTION
4405 is the section that branch into veneer and can be NULL if stub should go in
4406 a dedicated output section. Returns a pointer to the stub section, and the
4407 section to which the stub section will be attached (in *LINK_SEC_P).
48229727 4408 LINK_SEC_P may be NULL. */
906e58ca 4409
48229727
JB		 4410static asection *
4411elf32_arm_create_or_find_stub_sec (asection **link_sec_p, asection *section,
daa4adae
TP		 4412 struct elf32_arm_link_hash_table *htab,
4413 enum elf32_arm_stub_type stub_type)
906e58ca 4414{
daa4adae
TP		 4415 asection *link_sec, *out_sec, **stub_sec_p;
4416 const char *stub_sec_prefix;
4417 bfd_boolean dedicated_output_section =
4418 arm_dedicated_stub_output_section_required (stub_type);
4419 int align;
906e58ca 4420
daa4adae 4421 if (dedicated_output_section)
906e58ca 4422 {
daa4adae
TP		 4423 bfd *output_bfd = htab->obfd;
4424 const char *out_sec_name =
4425 arm_dedicated_stub_output_section_name (stub_type);
4426 link_sec = NULL;
4427 stub_sec_p = arm_dedicated_stub_input_section_ptr (htab, stub_type);
4428 stub_sec_prefix = out_sec_name;
4429 align = arm_dedicated_stub_output_section_required_alignment (stub_type);
4430 out_sec = bfd_get_section_by_name (output_bfd, out_sec_name);
4431 if (out_sec == NULL)
906e58ca 4432 {
4eca0228
AM		 4433 _bfd_error_handler (_("No address assigned to the veneers output "
4434 "section %s"), out_sec_name);
daa4adae 4435 return NULL;
906e58ca 4436 }
daa4adae
TP		 4437 }
4438 else
4439 {
c2abbbeb 4440 BFD_ASSERT (section->id <= htab->top_id);
daa4adae
TP		 4441 link_sec = htab->stub_group[section->id].link_sec;
4442 BFD_ASSERT (link_sec != NULL);
4443 stub_sec_p = &htab->stub_group[section->id].stub_sec;
4444 if (*stub_sec_p == NULL)
4445 stub_sec_p = &htab->stub_group[link_sec->id].stub_sec;
4446 stub_sec_prefix = link_sec->name;
4447 out_sec = link_sec->output_section;
4448 align = htab->nacl_p ? 4 : 3;
906e58ca 4449 }
b38cadfb 4450
daa4adae
TP		 4451 if (*stub_sec_p == NULL)
4452 {
4453 size_t namelen;
4454 bfd_size_type len;
4455 char *s_name;
4456
4457 namelen = strlen (stub_sec_prefix);
4458 len = namelen + sizeof (STUB_SUFFIX);
4459 s_name = (char *) bfd_alloc (htab->stub_bfd, len);
4460 if (s_name == NULL)
4461 return NULL;
4462
4463 memcpy (s_name, stub_sec_prefix, namelen);
4464 memcpy (s_name + namelen, STUB_SUFFIX, sizeof (STUB_SUFFIX));
4465 *stub_sec_p = (*htab->add_stub_section) (s_name, out_sec, link_sec,
4466 align);
4467 if (*stub_sec_p == NULL)
4468 return NULL;
4469
4470 out_sec->flags |= SEC_ALLOC | SEC_LOAD | SEC_READONLY | SEC_CODE
4471 | SEC_HAS_CONTENTS | SEC_RELOC | SEC_IN_MEMORY
4472 | SEC_KEEP;
4473 }
4474
4475 if (!dedicated_output_section)
4476 htab->stub_group[section->id].stub_sec = *stub_sec_p;
4477
48229727
JB		 4478 if (link_sec_p)
4479 *link_sec_p = link_sec;
b38cadfb 4480
daa4adae 4481 return *stub_sec_p;
48229727
JB		 4482}
4483
4484/* Add a new stub entry to the stub hash. Not all fields of the new
4485 stub entry are initialised. */
4486
4487static struct elf32_arm_stub_hash_entry *
daa4adae
TP		 4488elf32_arm_add_stub (const char *stub_name, asection *section,
4489 struct elf32_arm_link_hash_table *htab,
4490 enum elf32_arm_stub_type stub_type)
48229727
JB		 4491{
4492 asection *link_sec;
4493 asection *stub_sec;
4494 struct elf32_arm_stub_hash_entry *stub_entry;
4495
daa4adae
TP		 4496 stub_sec = elf32_arm_create_or_find_stub_sec (&link_sec, section, htab,
4497 stub_type);
48229727
JB		 4498 if (stub_sec == NULL)
4499 return NULL;
906e58ca
NC		 4500
4501 /* Enter this entry into the linker stub hash table. */
4502 stub_entry = arm_stub_hash_lookup (&htab->stub_hash_table, stub_name,
4503 TRUE, FALSE);
4504 if (stub_entry == NULL)
4505 {
6bde4c52
TP		 4506 if (section == NULL)
4507 section = stub_sec;
4eca0228
AM		 4508 _bfd_error_handler (_("%s: cannot create stub entry %s"),
4509 section->owner, stub_name);
906e58ca
NC		 4510 return NULL;
4511 }
4512
4513 stub_entry->stub_sec = stub_sec;
0955507f 4514 stub_entry->stub_offset = (bfd_vma) -1;
906e58ca
NC		 4515 stub_entry->id_sec = link_sec;
4516
906e58ca
NC		 4517 return stub_entry;
4518}
4519
4520/* Store an Arm insn into an output section not processed by
4521 elf32_arm_write_section. */
4522
4523static void
8029a119
NC		 4524put_arm_insn (struct elf32_arm_link_hash_table * htab,
4525 bfd * output_bfd, bfd_vma val, void * ptr)
906e58ca
NC		 4526{
4527 if (htab->byteswap_code != bfd_little_endian (output_bfd))
4528 bfd_putl32 (val, ptr);
4529 else
4530 bfd_putb32 (val, ptr);
4531}
4532
4533/* Store a 16-bit Thumb insn into an output section not processed by
4534 elf32_arm_write_section. */
4535
4536static void
8029a119
NC		 4537put_thumb_insn (struct elf32_arm_link_hash_table * htab,
4538 bfd * output_bfd, bfd_vma val, void * ptr)
906e58ca
NC		 4539{
4540 if (htab->byteswap_code != bfd_little_endian (output_bfd))
4541 bfd_putl16 (val, ptr);
4542 else
4543 bfd_putb16 (val, ptr);
4544}
4545
a504d23a
LA		 4546/* Store a Thumb2 insn into an output section not processed by
4547 elf32_arm_write_section. */
4548
4549static void
4550put_thumb2_insn (struct elf32_arm_link_hash_table * htab,
b98e6871 4551 bfd * output_bfd, bfd_vma val, bfd_byte * ptr)
a504d23a
LA		 4552{
4553 /* T2 instructions are 16-bit streamed. */
4554 if (htab->byteswap_code != bfd_little_endian (output_bfd))
4555 {
4556 bfd_putl16 ((val >> 16) & 0xffff, ptr);
4557 bfd_putl16 ((val & 0xffff), ptr + 2);
4558 }
4559 else
4560 {
4561 bfd_putb16 ((val >> 16) & 0xffff, ptr);
4562 bfd_putb16 ((val & 0xffff), ptr + 2);
4563 }
4564}
4565
0855e32b
NS		 4566/* If it's possible to change R_TYPE to a more efficient access
4567 model, return the new reloc type. */
4568
4569static unsigned
b38cadfb 4570elf32_arm_tls_transition (struct bfd_link_info *info, int r_type,
0855e32b
NS		 4571 struct elf_link_hash_entry *h)
4572{
4573 int is_local = (h == NULL);
4574
0e1862bb
L		 4575 if (bfd_link_pic (info)
4576 || (h && h->root.type == bfd_link_hash_undefweak))
0855e32b
NS		 4577 return r_type;
4578
b38cadfb 4579 /* We do not support relaxations for Old TLS models. */
0855e32b
NS		 4580 switch (r_type)
4581 {
4582 case R_ARM_TLS_GOTDESC:
4583 case R_ARM_TLS_CALL:
4584 case R_ARM_THM_TLS_CALL:
4585 case R_ARM_TLS_DESCSEQ:
4586 case R_ARM_THM_TLS_DESCSEQ:
4587 return is_local ? R_ARM_TLS_LE32 : R_ARM_TLS_IE32;
4588 }
4589
4590 return r_type;
4591}
4592
48229727
JB		 4593static bfd_reloc_status_type elf32_arm_final_link_relocate
4594 (reloc_howto_type *, bfd *, bfd *, asection *, bfd_byte *,
4595 Elf_Internal_Rela *, bfd_vma, struct bfd_link_info *, asection *,
34e77a92
RS		 4596 const char *, unsigned char, enum arm_st_branch_type,
4597 struct elf_link_hash_entry *, bfd_boolean *, char **);
48229727 4598
4563a860
JB		 4599static unsigned int
4600arm_stub_required_alignment (enum elf32_arm_stub_type stub_type)
4601{
4602 switch (stub_type)
4603 {
4604 case arm_stub_a8_veneer_b_cond:
4605 case arm_stub_a8_veneer_b:
4606 case arm_stub_a8_veneer_bl:
4607 return 2;
4608
4609 case arm_stub_long_branch_any_any:
4610 case arm_stub_long_branch_v4t_arm_thumb:
4611 case arm_stub_long_branch_thumb_only:
80c135e5 4612 case arm_stub_long_branch_thumb2_only:
d5a67c02 4613 case arm_stub_long_branch_thumb2_only_pure:
4563a860
JB		 4614 case arm_stub_long_branch_v4t_thumb_thumb:
4615 case arm_stub_long_branch_v4t_thumb_arm:
4616 case arm_stub_short_branch_v4t_thumb_arm:
4617 case arm_stub_long_branch_any_arm_pic:
4618 case arm_stub_long_branch_any_thumb_pic:
4619 case arm_stub_long_branch_v4t_thumb_thumb_pic:
4620 case arm_stub_long_branch_v4t_arm_thumb_pic:
4621 case arm_stub_long_branch_v4t_thumb_arm_pic:
4622 case arm_stub_long_branch_thumb_only_pic:
0855e32b
NS		 4623 case arm_stub_long_branch_any_tls_pic:
4624 case arm_stub_long_branch_v4t_thumb_tls_pic:
4ba2ef8f 4625 case arm_stub_cmse_branch_thumb_only:
4563a860
JB		 4626 case arm_stub_a8_veneer_blx:
4627 return 4;
b38cadfb 4628
7a89b94e
NC		 4629 case arm_stub_long_branch_arm_nacl:
4630 case arm_stub_long_branch_arm_nacl_pic:
4631 return 16;
4632
4563a860
JB		 4633 default:
4634 abort (); /* Should be unreachable. */
4635 }
4636}
4637
4f4faa4d
TP		 4638/* Returns whether stubs of type STUB_TYPE take over the symbol they are
4639 veneering (TRUE) or have their own symbol (FALSE). */
4640
4641static bfd_boolean
4642arm_stub_sym_claimed (enum elf32_arm_stub_type stub_type)
4643{
4644 if (stub_type >= max_stub_type)
4645 abort (); /* Should be unreachable. */
4646
4ba2ef8f
TP		 4647 switch (stub_type)
4648 {
4649 case arm_stub_cmse_branch_thumb_only:
4650 return TRUE;
4651
4652 default:
4653 return FALSE;
4654 }
4655
4656 abort (); /* Should be unreachable. */
4f4faa4d
TP		 4657}
4658
d7c5bd02
TP		 4659/* Returns the padding needed for the dedicated section used stubs of type
4660 STUB_TYPE. */
4661
4662static int
4663arm_dedicated_stub_section_padding (enum elf32_arm_stub_type stub_type)
4664{
4665 if (stub_type >= max_stub_type)
4666 abort (); /* Should be unreachable. */
4667
4ba2ef8f
TP		 4668 switch (stub_type)
4669 {
4670 case arm_stub_cmse_branch_thumb_only:
4671 return 32;
4672
4673 default:
4674 return 0;
4675 }
4676
4677 abort (); /* Should be unreachable. */
d7c5bd02
TP		 4678}
4679
0955507f
TP		 4680/* If veneers of type STUB_TYPE should go in a dedicated output section,
4681 returns the address of the hash table field in HTAB holding the offset at
4682 which new veneers should be layed out in the stub section. */
4683
4684static bfd_vma*
4685arm_new_stubs_start_offset_ptr (struct elf32_arm_link_hash_table *htab,
4686 enum elf32_arm_stub_type stub_type)
4687{
4688 switch (stub_type)
4689 {
4690 case arm_stub_cmse_branch_thumb_only:
4691 return &htab->new_cmse_stub_offset;
4692
4693 default:
4694 BFD_ASSERT (!arm_dedicated_stub_output_section_required (stub_type));
4695 return NULL;
4696 }
4697}
4698
906e58ca
NC		 4699static bfd_boolean
4700arm_build_one_stub (struct bfd_hash_entry *gen_entry,
4701 void * in_arg)
4702{
7a89b94e 4703#define MAXRELOCS 3
0955507f 4704 bfd_boolean removed_sg_veneer;
906e58ca 4705 struct elf32_arm_stub_hash_entry *stub_entry;
4dfe6ac6 4706 struct elf32_arm_link_hash_table *globals;
906e58ca 4707 struct bfd_link_info *info;
906e58ca
NC		 4708 asection *stub_sec;
4709 bfd *stub_bfd;
906e58ca
NC		 4710 bfd_byte *loc;
4711 bfd_vma sym_value;
4712 int template_size;
4713 int size;
d3ce72d0 4714 const insn_sequence *template_sequence;
906e58ca 4715 int i;
48229727
JB		 4716 int stub_reloc_idx[MAXRELOCS] = {-1, -1};
4717 int stub_reloc_offset[MAXRELOCS] = {0, 0};
4718 int nrelocs = 0;
0955507f 4719 int just_allocated = 0;
906e58ca
NC		 4720
4721 /* Massage our args to the form they really have. */
4722 stub_entry = (struct elf32_arm_stub_hash_entry *) gen_entry;
4723 info = (struct bfd_link_info *) in_arg;
4724
4725 globals = elf32_arm_hash_table (info);
4dfe6ac6
NC		 4726 if (globals == NULL)
4727 return FALSE;
906e58ca 4728
906e58ca
NC		 4729 stub_sec = stub_entry->stub_sec;
4730
4dfe6ac6 4731 if ((globals->fix_cortex_a8 < 0)
4563a860
JB		 4732 != (arm_stub_required_alignment (stub_entry->stub_type) == 2))
4733 /* We have to do less-strictly-aligned fixes last. */
eb7c4339 4734 return TRUE;
fe33d2fa 4735
0955507f
TP		 4736 /* Assign a slot at the end of section if none assigned yet. */
4737 if (stub_entry->stub_offset == (bfd_vma) -1)
4738 {
4739 stub_entry->stub_offset = stub_sec->size;
4740 just_allocated = 1;
4741 }
906e58ca
NC		 4742 loc = stub_sec->contents + stub_entry->stub_offset;
4743
4744 stub_bfd = stub_sec->owner;
4745
906e58ca
NC		 4746 /* This is the address of the stub destination. */
4747 sym_value = (stub_entry->target_value
4748 + stub_entry->target_section->output_offset
4749 + stub_entry->target_section->output_section->vma);
4750
d3ce72d0 4751 template_sequence = stub_entry->stub_template;
461a49ca 4752 template_size = stub_entry->stub_template_size;
906e58ca
NC		 4753
4754 size = 0;
461a49ca 4755 for (i = 0; i < template_size; i++)
906e58ca 4756 {
d3ce72d0 4757 switch (template_sequence[i].type)
461a49ca
DJ		 4758 {
4759 case THUMB16_TYPE:
48229727 4760 {
d3ce72d0
NC		 4761 bfd_vma data = (bfd_vma) template_sequence[i].data;
4762 if (template_sequence[i].reloc_addend != 0)
48229727 4763 {
99059e56
RM		 4764 /* We've borrowed the reloc_addend field to mean we should
4765 insert a condition code into this (Thumb-1 branch)
4766 instruction. See THUMB16_BCOND_INSN. */
4767 BFD_ASSERT ((data & 0xff00) == 0xd000);
4768 data |= ((stub_entry->orig_insn >> 22) & 0xf) << 8;
48229727 4769 }
fe33d2fa 4770 bfd_put_16 (stub_bfd, data, loc + size);
48229727
JB		 4771 size += 2;
4772 }
461a49ca 4773 break;
906e58ca 4774
48229727 4775 case THUMB32_TYPE:
fe33d2fa
CL		 4776 bfd_put_16 (stub_bfd,
4777 (template_sequence[i].data >> 16) & 0xffff,
4778 loc + size);
4779 bfd_put_16 (stub_bfd, template_sequence[i].data & 0xffff,
4780 loc + size + 2);
99059e56
RM		 4781 if (template_sequence[i].r_type != R_ARM_NONE)
4782 {
4783 stub_reloc_idx[nrelocs] = i;
4784 stub_reloc_offset[nrelocs++] = size;
4785 }
4786 size += 4;
4787 break;
48229727 4788
461a49ca 4789 case ARM_TYPE:
fe33d2fa
CL		 4790 bfd_put_32 (stub_bfd, template_sequence[i].data,
4791 loc + size);
461a49ca
DJ		 4792 /* Handle cases where the target is encoded within the
4793 instruction. */
d3ce72d0 4794 if (template_sequence[i].r_type == R_ARM_JUMP24)
461a49ca 4795 {
48229727
JB		 4796 stub_reloc_idx[nrelocs] = i;
4797 stub_reloc_offset[nrelocs++] = size;
461a49ca
DJ		 4798 }
4799 size += 4;
4800 break;
4801
4802 case DATA_TYPE:
d3ce72d0 4803 bfd_put_32 (stub_bfd, template_sequence[i].data, loc + size);
48229727
JB		 4804 stub_reloc_idx[nrelocs] = i;
4805 stub_reloc_offset[nrelocs++] = size;
461a49ca
DJ		 4806 size += 4;
4807 break;
4808
4809 default:
4810 BFD_FAIL ();
4811 return FALSE;
4812 }
906e58ca 4813 }
461a49ca 4814
0955507f
TP		 4815 if (just_allocated)
4816 stub_sec->size += size;
906e58ca 4817
461a49ca
DJ		 4818 /* Stub size has already been computed in arm_size_one_stub. Check
4819 consistency. */
4820 BFD_ASSERT (size == stub_entry->stub_size);
4821
906e58ca 4822 /* Destination is Thumb. Force bit 0 to 1 to reflect this. */
35fc36a8 4823 if (stub_entry->branch_type == ST_BRANCH_TO_THUMB)
906e58ca
NC		 4824 sym_value |= 1;
4825
0955507f
TP		 4826 /* Assume non empty slots have at least one and at most MAXRELOCS entries
4827 to relocate in each stub. */
4828 removed_sg_veneer =
4829 (size == 0 && stub_entry->stub_type == arm_stub_cmse_branch_thumb_only);
4830 BFD_ASSERT (removed_sg_veneer || (nrelocs != 0 && nrelocs <= MAXRELOCS));
c820be07 4831
48229727 4832 for (i = 0; i < nrelocs; i++)
8d9d9490
TP		 4833 {
4834 Elf_Internal_Rela rel;
4835 bfd_boolean unresolved_reloc;
4836 char *error_message;
4837 bfd_vma points_to =
4838 sym_value + template_sequence[stub_reloc_idx[i]].reloc_addend;
4839
4840 rel.r_offset = stub_entry->stub_offset + stub_reloc_offset[i];
4841 rel.r_info = ELF32_R_INFO (0,
4842 template_sequence[stub_reloc_idx[i]].r_type);
4843 rel.r_addend = 0;
4844
4845 if (stub_entry->stub_type == arm_stub_a8_veneer_b_cond && i == 0)
4846 /* The first relocation in the elf32_arm_stub_a8_veneer_b_cond[]
4847 template should refer back to the instruction after the original
4848 branch. We use target_section as Cortex-A8 erratum workaround stubs
4849 are only generated when both source and target are in the same
4850 section. */
4851 points_to = stub_entry->target_section->output_section->vma
4852 + stub_entry->target_section->output_offset
4853 + stub_entry->source_value;
4854
4855 elf32_arm_final_link_relocate (elf32_arm_howto_from_type
4856 (template_sequence[stub_reloc_idx[i]].r_type),
4857 stub_bfd, info->output_bfd, stub_sec, stub_sec->contents, &rel,
4858 points_to, info, stub_entry->target_section, "", STT_FUNC,
4859 stub_entry->branch_type,
4860 (struct elf_link_hash_entry *) stub_entry->h, &unresolved_reloc,
4861 &error_message);
4862 }
906e58ca
NC		 4863
4864 return TRUE;
48229727 4865#undef MAXRELOCS
906e58ca
NC		 4866}
4867
48229727
JB		 4868/* Calculate the template, template size and instruction size for a stub.
4869 Return value is the instruction size. */
906e58ca 4870
48229727
JB		 4871static unsigned int
4872find_stub_size_and_template (enum elf32_arm_stub_type stub_type,
4873 const insn_sequence **stub_template,
4874 int *stub_template_size)
906e58ca 4875{
d3ce72d0 4876 const insn_sequence *template_sequence = NULL;
48229727
JB		 4877 int template_size = 0, i;
4878 unsigned int size;
906e58ca 4879
d3ce72d0 4880 template_sequence = stub_definitions[stub_type].template_sequence;
2a229407
AM		 4881 if (stub_template)
4882 *stub_template = template_sequence;
4883
48229727 4884 template_size = stub_definitions[stub_type].template_size;
2a229407
AM		 4885 if (stub_template_size)
4886 *stub_template_size = template_size;
906e58ca
NC		 4887
4888 size = 0;
461a49ca
DJ		 4889 for (i = 0; i < template_size; i++)
4890 {
d3ce72d0 4891 switch (template_sequence[i].type)
461a49ca
DJ		 4892 {
4893 case THUMB16_TYPE:
4894 size += 2;
4895 break;
4896
4897 case ARM_TYPE:
48229727 4898 case THUMB32_TYPE:
461a49ca
DJ		 4899 case DATA_TYPE:
4900 size += 4;
4901 break;
4902
4903 default:
4904 BFD_FAIL ();
2a229407 4905 return 0;
461a49ca
DJ		 4906 }
4907 }
4908
48229727
JB		 4909 return size;
4910}
4911
4912/* As above, but don't actually build the stub. Just bump offset so
4913 we know stub section sizes. */
4914
4915static bfd_boolean
4916arm_size_one_stub (struct bfd_hash_entry *gen_entry,
c7e2358a 4917 void *in_arg ATTRIBUTE_UNUSED)
48229727
JB		 4918{
4919 struct elf32_arm_stub_hash_entry *stub_entry;
d3ce72d0 4920 const insn_sequence *template_sequence;
48229727
JB		 4921 int template_size, size;
4922
4923 /* Massage our args to the form they really have. */
4924 stub_entry = (struct elf32_arm_stub_hash_entry *) gen_entry;
48229727
JB		 4925
4926 BFD_ASSERT((stub_entry->stub_type > arm_stub_none)
4927 && stub_entry->stub_type < ARRAY_SIZE(stub_definitions));
4928
d3ce72d0 4929 size = find_stub_size_and_template (stub_entry->stub_type, &template_sequence,
48229727
JB		 4930 &template_size);
4931
0955507f
TP		 4932 /* Initialized to -1. Null size indicates an empty slot full of zeros. */
4933 if (stub_entry->stub_template_size)
4934 {
4935 stub_entry->stub_size = size;
4936 stub_entry->stub_template = template_sequence;
4937 stub_entry->stub_template_size = template_size;
4938 }
4939
4940 /* Already accounted for. */
4941 if (stub_entry->stub_offset != (bfd_vma) -1)
4942 return TRUE;
461a49ca 4943
906e58ca
NC		 4944 size = (size + 7) & ~7;
4945 stub_entry->stub_sec->size += size;
461a49ca 4946
906e58ca
NC		 4947 return TRUE;
4948}
4949
4950/* External entry points for sizing and building linker stubs. */
4951
4952/* Set up various things so that we can make a list of input sections
4953 for each output section included in the link. Returns -1 on error,
4954 0 when no stubs will be needed, and 1 on success. */
4955
4956int
4957elf32_arm_setup_section_lists (bfd *output_bfd,
4958 struct bfd_link_info *info)
4959{
4960 bfd *input_bfd;
4961 unsigned int bfd_count;
7292b3ac 4962 unsigned int top_id, top_index;
906e58ca
NC		 4963 asection *section;
4964 asection **input_list, **list;
4965 bfd_size_type amt;
4966 struct elf32_arm_link_hash_table *htab = elf32_arm_hash_table (info);
4967
4dfe6ac6
NC		 4968 if (htab == NULL)
4969 return 0;
906e58ca
NC		 4970 if (! is_elf_hash_table (htab))
4971 return 0;
4972
4973 /* Count the number of input BFDs and find the top input section id. */
4974 for (input_bfd = info->input_bfds, bfd_count = 0, top_id = 0;
4975 input_bfd != NULL;
c72f2fb2 4976 input_bfd = input_bfd->link.next)
906e58ca
NC		 4977 {
4978 bfd_count += 1;
4979 for (section = input_bfd->sections;
4980 section != NULL;
4981 section = section->next)
4982 {
4983 if (top_id < section->id)
4984 top_id = section->id;
4985 }
4986 }
4987 htab->bfd_count = bfd_count;
4988
4989 amt = sizeof (struct map_stub) * (top_id + 1);
21d799b5 4990 htab->stub_group = (struct map_stub *) bfd_zmalloc (amt);
906e58ca
NC		 4991 if (htab->stub_group == NULL)
4992 return -1;
fe33d2fa 4993 htab->top_id = top_id;
906e58ca
NC		 4994
4995 /* We can't use output_bfd->section_count here to find the top output
4996 section index as some sections may have been removed, and
4997 _bfd_strip_section_from_output doesn't renumber the indices. */
4998 for (section = output_bfd->sections, top_index = 0;
4999 section != NULL;
5000 section = section->next)
5001 {
5002 if (top_index < section->index)
5003 top_index = section->index;
5004 }
5005
5006 htab->top_index = top_index;
5007 amt = sizeof (asection *) * (top_index + 1);
21d799b5 5008 input_list = (asection **) bfd_malloc (amt);
906e58ca
NC		 5009 htab->input_list = input_list;
5010 if (input_list == NULL)
5011 return -1;
5012
5013 /* For sections we aren't interested in, mark their entries with a
5014 value we can check later. */
5015 list = input_list + top_index;
5016 do
5017 *list = bfd_abs_section_ptr;
5018 while (list-- != input_list);
5019
5020 for (section = output_bfd->sections;
5021 section != NULL;
5022 section = section->next)
5023 {
5024 if ((section->flags & SEC_CODE) != 0)
5025 input_list[section->index] = NULL;
5026 }
5027
5028 return 1;
5029}
5030
5031/* The linker repeatedly calls this function for each input section,
5032 in the order that input sections are linked into output sections.
5033 Build lists of input sections to determine groupings between which
5034 we may insert linker stubs. */
5035
5036void
5037elf32_arm_next_input_section (struct bfd_link_info *info,
5038 asection *isec)
5039{
5040 struct elf32_arm_link_hash_table *htab = elf32_arm_hash_table (info);
5041
4dfe6ac6
NC		 5042 if (htab == NULL)
5043 return;
5044
906e58ca
NC		 5045 if (isec->output_section->index <= htab->top_index)
5046 {
5047 asection **list = htab->input_list + isec->output_section->index;
5048
a7470592 5049 if (*list != bfd_abs_section_ptr && (isec->flags & SEC_CODE) != 0)
906e58ca
NC		 5050 {
5051 /* Steal the link_sec pointer for our list. */
5052#define PREV_SEC(sec) (htab->stub_group[(sec)->id].link_sec)
5053 /* This happens to make the list in reverse order,
07d72278 5054 which we reverse later. */
906e58ca
NC		 5055 PREV_SEC (isec) = *list;
5056 *list = isec;
5057 }
5058 }
5059}
5060
5061/* See whether we can group stub sections together. Grouping stub
5062 sections may result in fewer stubs. More importantly, we need to
07d72278 5063 put all .init* and .fini* stubs at the end of the .init or
906e58ca
NC		 5064 .fini output sections respectively, because glibc splits the
5065 _init and _fini functions into multiple parts. Putting a stub in
5066 the middle of a function is not a good idea. */
5067
5068static void
5069group_sections (struct elf32_arm_link_hash_table *htab,
5070 bfd_size_type stub_group_size,
07d72278 5071 bfd_boolean stubs_always_after_branch)
906e58ca 5072{
07d72278 5073 asection **list = htab->input_list;
906e58ca
NC		 5074
5075 do
5076 {
5077 asection *tail = *list;
07d72278 5078 asection *head;
906e58ca
NC		 5079
5080 if (tail == bfd_abs_section_ptr)
5081 continue;
5082
07d72278
DJ		 5083 /* Reverse the list: we must avoid placing stubs at the
5084 beginning of the section because the beginning of the text
5085 section may be required for an interrupt vector in bare metal
5086 code. */
5087#define NEXT_SEC PREV_SEC
e780aef2
CL		 5088 head = NULL;
5089 while (tail != NULL)
99059e56
RM		 5090 {
5091 /* Pop from tail. */
5092 asection *item = tail;
5093 tail = PREV_SEC (item);
e780aef2 5094
99059e56
RM		 5095 /* Push on head. */
5096 NEXT_SEC (item) = head;
5097 head = item;
5098 }
07d72278
DJ		 5099
5100 while (head != NULL)
906e58ca
NC		 5101 {
5102 asection *curr;
07d72278 5103 asection *next;
e780aef2
CL		 5104 bfd_vma stub_group_start = head->output_offset;
5105 bfd_vma end_of_next;
906e58ca 5106
07d72278 5107 curr = head;
e780aef2 5108 while (NEXT_SEC (curr) != NULL)
8cd931b7 5109 {
e780aef2
CL		 5110 next = NEXT_SEC (curr);
5111 end_of_next = next->output_offset + next->size;
5112 if (end_of_next - stub_group_start >= stub_group_size)
5113 /* End of NEXT is too far from start, so stop. */
8cd931b7 5114 break;
e780aef2
CL		 5115 /* Add NEXT to the group. */
5116 curr = next;
8cd931b7 5117 }
906e58ca 5118
07d72278 5119 /* OK, the size from the start to the start of CURR is less
906e58ca 5120 than stub_group_size and thus can be handled by one stub
07d72278 5121 section. (Or the head section is itself larger than
906e58ca
NC		 5122 stub_group_size, in which case we may be toast.)
5123 We should really be keeping track of the total size of
5124 stubs added here, as stubs contribute to the final output
7fb9f789 5125 section size. */
906e58ca
NC		 5126 do
5127 {
07d72278 5128 next = NEXT_SEC (head);
906e58ca 5129 /* Set up this stub group. */
07d72278 5130 htab->stub_group[head->id].link_sec = curr;
906e58ca 5131 }
07d72278 5132 while (head != curr && (head = next) != NULL);
906e58ca
NC		 5133
5134 /* But wait, there's more! Input sections up to stub_group_size
07d72278
DJ		 5135 bytes after the stub section can be handled by it too. */
5136 if (!stubs_always_after_branch)
906e58ca 5137 {
e780aef2
CL		 5138 stub_group_start = curr->output_offset + curr->size;
5139
8cd931b7 5140 while (next != NULL)
906e58ca 5141 {
e780aef2
CL		 5142 end_of_next = next->output_offset + next->size;
5143 if (end_of_next - stub_group_start >= stub_group_size)
5144 /* End of NEXT is too far from stubs, so stop. */
8cd931b7 5145 break;
e780aef2 5146 /* Add NEXT to the stub group. */
07d72278
DJ		 5147 head = next;
5148 next = NEXT_SEC (head);
5149 htab->stub_group[head->id].link_sec = curr;
906e58ca
NC		 5150 }
5151 }
07d72278 5152 head = next;
906e58ca
NC		 5153 }
5154 }
07d72278 5155 while (list++ != htab->input_list + htab->top_index);
906e58ca
NC		 5156
5157 free (htab->input_list);
5158#undef PREV_SEC
07d72278 5159#undef NEXT_SEC
906e58ca
NC		 5160}
5161
48229727
JB		 5162/* Comparison function for sorting/searching relocations relating to Cortex-A8
5163 erratum fix. */
5164
5165static int
5166a8_reloc_compare (const void *a, const void *b)
5167{
21d799b5
NC		 5168 const struct a8_erratum_reloc *ra = (const struct a8_erratum_reloc *) a;
5169 const struct a8_erratum_reloc *rb = (const struct a8_erratum_reloc *) b;
48229727
JB		 5170
5171 if (ra->from < rb->from)
5172 return -1;
5173 else if (ra->from > rb->from)
5174 return 1;
5175 else
5176 return 0;
5177}
5178
5179static struct elf_link_hash_entry *find_thumb_glue (struct bfd_link_info *,
5180 const char *, char **);
5181
5182/* Helper function to scan code for sequences which might trigger the Cortex-A8
5183 branch/TLB erratum. Fill in the table described by A8_FIXES_P,
81694485 5184 NUM_A8_FIXES_P, A8_FIX_TABLE_SIZE_P. Returns true if an error occurs, false
48229727
JB		 5185 otherwise. */
5186
81694485
NC		 5187static bfd_boolean
5188cortex_a8_erratum_scan (bfd *input_bfd,
5189 struct bfd_link_info *info,
48229727
JB		 5190 struct a8_erratum_fix **a8_fixes_p,
5191 unsigned int *num_a8_fixes_p,
5192 unsigned int *a8_fix_table_size_p,
5193 struct a8_erratum_reloc *a8_relocs,
eb7c4339
NS		 5194 unsigned int num_a8_relocs,
5195 unsigned prev_num_a8_fixes,
5196 bfd_boolean *stub_changed_p)
48229727
JB		 5197{
5198 asection *section;
5199 struct elf32_arm_link_hash_table *htab = elf32_arm_hash_table (info);
5200 struct a8_erratum_fix *a8_fixes = *a8_fixes_p;
5201 unsigned int num_a8_fixes = *num_a8_fixes_p;
5202 unsigned int a8_fix_table_size = *a8_fix_table_size_p;
5203
4dfe6ac6
NC		 5204 if (htab == NULL)
5205 return FALSE;
5206
48229727
JB		 5207 for (section = input_bfd->sections;
5208 section != NULL;
5209 section = section->next)
5210 {
5211 bfd_byte *contents = NULL;
5212 struct _arm_elf_section_data *sec_data;
5213 unsigned int span;
5214 bfd_vma base_vma;
5215
5216 if (elf_section_type (section) != SHT_PROGBITS
99059e56
RM		 5217 || (elf_section_flags (section) & SHF_EXECINSTR) == 0
5218 || (section->flags & SEC_EXCLUDE) != 0
5219 || (section->sec_info_type == SEC_INFO_TYPE_JUST_SYMS)
5220 || (section->output_section == bfd_abs_section_ptr))
5221 continue;
48229727
JB		 5222
5223 base_vma = section->output_section->vma + section->output_offset;
5224
5225 if (elf_section_data (section)->this_hdr.contents != NULL)
99059e56 5226 contents = elf_section_data (section)->this_hdr.contents;
48229727 5227 else if (! bfd_malloc_and_get_section (input_bfd, section, &contents))
99059e56 5228 return TRUE;
48229727
JB		 5229
5230 sec_data = elf32_arm_section_data (section);
5231
5232 for (span = 0; span < sec_data->mapcount; span++)
99059e56
RM		 5233 {
5234 unsigned int span_start = sec_data->map[span].vma;
5235 unsigned int span_end = (span == sec_data->mapcount - 1)
5236 ? section->size : sec_data->map[span + 1].vma;
5237 unsigned int i;
5238 char span_type = sec_data->map[span].type;
5239 bfd_boolean last_was_32bit = FALSE, last_was_branch = FALSE;
5240
5241 if (span_type != 't')
5242 continue;
5243
5244 /* Span is entirely within a single 4KB region: skip scanning. */
5245 if (((base_vma + span_start) & ~0xfff)
48229727 5246 == ((base_vma + span_end) & ~0xfff))
99059e56
RM		 5247 continue;
5248
5249 /* Scan for 32-bit Thumb-2 branches which span two 4K regions, where:
5250
5251 * The opcode is BLX.W, BL.W, B.W, Bcc.W
5252 * The branch target is in the same 4KB region as the
5253 first half of the branch.
5254 * The instruction before the branch is a 32-bit
5255 length non-branch instruction. */
5256 for (i = span_start; i < span_end;)
5257 {
5258 unsigned int insn = bfd_getl16 (&contents[i]);
5259 bfd_boolean insn_32bit = FALSE, is_blx = FALSE, is_b = FALSE;
48229727
JB		 5260 bfd_boolean is_bl = FALSE, is_bcc = FALSE, is_32bit_branch;
5261
99059e56
RM		 5262 if ((insn & 0xe000) == 0xe000 && (insn & 0x1800) != 0x0000)
5263 insn_32bit = TRUE;
48229727
JB		 5264
5265 if (insn_32bit)
99059e56
RM		 5266 {
5267 /* Load the rest of the insn (in manual-friendly order). */
5268 insn = (insn << 16) | bfd_getl16 (&contents[i + 2]);
5269
5270 /* Encoding T4: B<c>.W. */
5271 is_b = (insn & 0xf800d000) == 0xf0009000;
5272 /* Encoding T1: BL<c>.W. */
5273 is_bl = (insn & 0xf800d000) == 0xf000d000;
5274 /* Encoding T2: BLX<c>.W. */
5275 is_blx = (insn & 0xf800d000) == 0xf000c000;
48229727
JB		 5276 /* Encoding T3: B<c>.W (not permitted in IT block). */
5277 is_bcc = (insn & 0xf800d000) == 0xf0008000
5278 && (insn & 0x07f00000) != 0x03800000;
5279 }
5280
5281 is_32bit_branch = is_b || is_bl || is_blx || is_bcc;
fe33d2fa 5282
99059e56 5283 if (((base_vma + i) & 0xfff) == 0xffe
81694485
NC		 5284 && insn_32bit
5285 && is_32bit_branch
5286 && last_was_32bit
5287 && ! last_was_branch)
99059e56
RM		 5288 {
5289 bfd_signed_vma offset = 0;
5290 bfd_boolean force_target_arm = FALSE;
48229727 5291 bfd_boolean force_target_thumb = FALSE;
99059e56
RM		 5292 bfd_vma target;
5293 enum elf32_arm_stub_type stub_type = arm_stub_none;
5294 struct a8_erratum_reloc key, *found;
5295 bfd_boolean use_plt = FALSE;
48229727 5296
99059e56
RM		 5297 key.from = base_vma + i;
5298 found = (struct a8_erratum_reloc *)
5299 bsearch (&key, a8_relocs, num_a8_relocs,
5300 sizeof (struct a8_erratum_reloc),
5301 &a8_reloc_compare);
48229727
JB		 5302
5303 if (found)
5304 {
5305 char *error_message = NULL;
5306 struct elf_link_hash_entry *entry;
5307
5308 /* We don't care about the error returned from this
99059e56 5309 function, only if there is glue or not. */
48229727
JB		 5310 entry = find_thumb_glue (info, found->sym_name,
5311 &error_message);
5312
5313 if (entry)
5314 found->non_a8_stub = TRUE;
5315
92750f34 5316 /* Keep a simpler condition, for the sake of clarity. */
362d30a1 5317 if (htab->root.splt != NULL && found->hash != NULL
92750f34
DJ		 5318 && found->hash->root.plt.offset != (bfd_vma) -1)
5319 use_plt = TRUE;
5320
5321 if (found->r_type == R_ARM_THM_CALL)
5322 {
35fc36a8
RS		 5323 if (found->branch_type == ST_BRANCH_TO_ARM
5324 || use_plt)
92750f34
DJ		 5325 force_target_arm = TRUE;
5326 else
5327 force_target_thumb = TRUE;
5328 }
48229727
JB		 5329 }
5330
99059e56 5331 /* Check if we have an offending branch instruction. */
48229727
JB		 5332
5333 if (found && found->non_a8_stub)
5334 /* We've already made a stub for this instruction, e.g.
5335 it's a long branch or a Thumb->ARM stub. Assume that
5336 stub will suffice to work around the A8 erratum (see
5337 setting of always_after_branch above). */
5338 ;
99059e56
RM		 5339 else if (is_bcc)
5340 {
5341 offset = (insn & 0x7ff) << 1;
5342 offset |= (insn & 0x3f0000) >> 4;
5343 offset |= (insn & 0x2000) ? 0x40000 : 0;
5344 offset |= (insn & 0x800) ? 0x80000 : 0;
5345 offset |= (insn & 0x4000000) ? 0x100000 : 0;
5346 if (offset & 0x100000)
5347 offset |= ~ ((bfd_signed_vma) 0xfffff);
5348 stub_type = arm_stub_a8_veneer_b_cond;
5349 }
5350 else if (is_b || is_bl || is_blx)
5351 {
5352 int s = (insn & 0x4000000) != 0;
5353 int j1 = (insn & 0x2000) != 0;
5354 int j2 = (insn & 0x800) != 0;
5355 int i1 = !(j1 ^ s);
5356 int i2 = !(j2 ^ s);
5357
5358 offset = (insn & 0x7ff) << 1;
5359 offset |= (insn & 0x3ff0000) >> 4;
5360 offset |= i2 << 22;
5361 offset |= i1 << 23;
5362 offset |= s << 24;
5363 if (offset & 0x1000000)
5364 offset |= ~ ((bfd_signed_vma) 0xffffff);
5365
5366 if (is_blx)
5367 offset &= ~ ((bfd_signed_vma) 3);
5368
5369 stub_type = is_blx ? arm_stub_a8_veneer_blx :
5370 is_bl ? arm_stub_a8_veneer_bl : arm_stub_a8_veneer_b;
5371 }
5372
5373 if (stub_type != arm_stub_none)
5374 {
5375 bfd_vma pc_for_insn = base_vma + i + 4;
48229727
JB		 5376
5377 /* The original instruction is a BL, but the target is
99059e56 5378 an ARM instruction. If we were not making a stub,
48229727
JB		 5379 the BL would have been converted to a BLX. Use the
5380 BLX stub instead in that case. */
5381 if (htab->use_blx && force_target_arm
5382 && stub_type == arm_stub_a8_veneer_bl)
5383 {
5384 stub_type = arm_stub_a8_veneer_blx;
5385 is_blx = TRUE;
5386 is_bl = FALSE;
5387 }
5388 /* Conversely, if the original instruction was
5389 BLX but the target is Thumb mode, use the BL
5390 stub. */
5391 else if (force_target_thumb
5392 && stub_type == arm_stub_a8_veneer_blx)
5393 {
5394 stub_type = arm_stub_a8_veneer_bl;
5395 is_blx = FALSE;
5396 is_bl = TRUE;
5397 }
5398
99059e56
RM		 5399 if (is_blx)
5400 pc_for_insn &= ~ ((bfd_vma) 3);
48229727 5401
99059e56
RM		 5402 /* If we found a relocation, use the proper destination,
5403 not the offset in the (unrelocated) instruction.
48229727
JB		 5404 Note this is always done if we switched the stub type
5405 above. */
99059e56
RM		 5406 if (found)
5407 offset =
81694485 5408 (bfd_signed_vma) (found->destination - pc_for_insn);
48229727 5409
99059e56
RM		 5410 /* If the stub will use a Thumb-mode branch to a
5411 PLT target, redirect it to the preceding Thumb
5412 entry point. */
5413 if (stub_type != arm_stub_a8_veneer_blx && use_plt)
5414 offset -= PLT_THUMB_STUB_SIZE;
7d24e6a6 5415
99059e56 5416 target = pc_for_insn + offset;
48229727 5417
99059e56
RM		 5418 /* The BLX stub is ARM-mode code. Adjust the offset to
5419 take the different PC value (+8 instead of +4) into
48229727 5420 account. */
99059e56
RM		 5421 if (stub_type == arm_stub_a8_veneer_blx)
5422 offset += 4;
5423
5424 if (((base_vma + i) & ~0xfff) == (target & ~0xfff))
5425 {
5426 char *stub_name = NULL;
5427
5428 if (num_a8_fixes == a8_fix_table_size)
5429 {
5430 a8_fix_table_size *= 2;
5431 a8_fixes = (struct a8_erratum_fix *)
5432 bfd_realloc (a8_fixes,
5433 sizeof (struct a8_erratum_fix)
5434 * a8_fix_table_size);
5435 }
48229727 5436
eb7c4339
NS		 5437 if (num_a8_fixes < prev_num_a8_fixes)
5438 {
5439 /* If we're doing a subsequent scan,
5440 check if we've found the same fix as
5441 before, and try and reuse the stub
5442 name. */
5443 stub_name = a8_fixes[num_a8_fixes].stub_name;
5444 if ((a8_fixes[num_a8_fixes].section != section)
5445 || (a8_fixes[num_a8_fixes].offset != i))
5446 {
5447 free (stub_name);
5448 stub_name = NULL;
5449 *stub_changed_p = TRUE;
5450 }
5451 }
5452
5453 if (!stub_name)
5454 {
21d799b5 5455 stub_name = (char *) bfd_malloc (8 + 1 + 8 + 1);
eb7c4339
NS		 5456 if (stub_name != NULL)
5457 sprintf (stub_name, "%x:%x", section->id, i);
5458 }
48229727 5459
99059e56
RM		 5460 a8_fixes[num_a8_fixes].input_bfd = input_bfd;
5461 a8_fixes[num_a8_fixes].section = section;
5462 a8_fixes[num_a8_fixes].offset = i;
8d9d9490
TP		 5463 a8_fixes[num_a8_fixes].target_offset =
5464 target - base_vma;
99059e56
RM		 5465 a8_fixes[num_a8_fixes].orig_insn = insn;
5466 a8_fixes[num_a8_fixes].stub_name = stub_name;
5467 a8_fixes[num_a8_fixes].stub_type = stub_type;
5468 a8_fixes[num_a8_fixes].branch_type =
35fc36a8 5469 is_blx ? ST_BRANCH_TO_ARM : ST_BRANCH_TO_THUMB;
48229727 5470
99059e56
RM		 5471 num_a8_fixes++;
5472 }
5473 }
5474 }
48229727 5475
99059e56
RM		 5476 i += insn_32bit ? 4 : 2;
5477 last_was_32bit = insn_32bit;
48229727 5478 last_was_branch = is_32bit_branch;
99059e56
RM		 5479 }
5480 }
48229727
JB		 5481
5482 if (elf_section_data (section)->this_hdr.contents == NULL)
99059e56 5483 free (contents);
48229727 5484 }
fe33d2fa 5485
48229727
JB		 5486 *a8_fixes_p = a8_fixes;
5487 *num_a8_fixes_p = num_a8_fixes;
5488 *a8_fix_table_size_p = a8_fix_table_size;
fe33d2fa 5489
81694485 5490 return FALSE;
48229727
JB		 5491}
5492
b715f643
TP		 5493/* Create or update a stub entry depending on whether the stub can already be
5494 found in HTAB. The stub is identified by:
5495 - its type STUB_TYPE
5496 - its source branch (note that several can share the same stub) whose
5497 section and relocation (if any) are given by SECTION and IRELA
5498 respectively
5499 - its target symbol whose input section, hash, name, value and branch type
5500 are given in SYM_SEC, HASH, SYM_NAME, SYM_VALUE and BRANCH_TYPE
5501 respectively
5502
5503 If found, the value of the stub's target symbol is updated from SYM_VALUE
5504 and *NEW_STUB is set to FALSE. Otherwise, *NEW_STUB is set to
5505 TRUE and the stub entry is initialized.
5506
0955507f
TP		 5507 Returns the stub that was created or updated, or NULL if an error
5508 occurred. */
b715f643 5509
0955507f 5510static struct elf32_arm_stub_hash_entry *
b715f643
TP		 5511elf32_arm_create_stub (struct elf32_arm_link_hash_table *htab,
5512 enum elf32_arm_stub_type stub_type, asection *section,
5513 Elf_Internal_Rela *irela, asection *sym_sec,
5514 struct elf32_arm_link_hash_entry *hash, char *sym_name,
5515 bfd_vma sym_value, enum arm_st_branch_type branch_type,
5516 bfd_boolean *new_stub)
5517{
5518 const asection *id_sec;
5519 char *stub_name;
5520 struct elf32_arm_stub_hash_entry *stub_entry;
5521 unsigned int r_type;
4f4faa4d 5522 bfd_boolean sym_claimed = arm_stub_sym_claimed (stub_type);
b715f643
TP		 5523
5524 BFD_ASSERT (stub_type != arm_stub_none);
5525 *new_stub = FALSE;
5526
4f4faa4d
TP		 5527 if (sym_claimed)
5528 stub_name = sym_name;
5529 else
5530 {
5531 BFD_ASSERT (irela);
5532 BFD_ASSERT (section);
c2abbbeb 5533 BFD_ASSERT (section->id <= htab->top_id);
b715f643 5534
4f4faa4d
TP		 5535 /* Support for grouping stub sections. */
5536 id_sec = htab->stub_group[section->id].link_sec;
b715f643 5537
4f4faa4d
TP		 5538 /* Get the name of this stub. */
5539 stub_name = elf32_arm_stub_name (id_sec, sym_sec, hash, irela,
5540 stub_type);
5541 if (!stub_name)
0955507f 5542 return NULL;
4f4faa4d 5543 }
b715f643
TP		 5544
5545 stub_entry = arm_stub_hash_lookup (&htab->stub_hash_table, stub_name, FALSE,
5546 FALSE);
5547 /* The proper stub has already been created, just update its value. */
5548 if (stub_entry != NULL)
5549 {
4f4faa4d
TP		 5550 if (!sym_claimed)
5551 free (stub_name);
b715f643 5552 stub_entry->target_value = sym_value;
0955507f 5553 return stub_entry;
b715f643
TP		 5554 }
5555
daa4adae 5556 stub_entry = elf32_arm_add_stub (stub_name, section, htab, stub_type);
b715f643
TP		 5557 if (stub_entry == NULL)
5558 {
4f4faa4d
TP		 5559 if (!sym_claimed)
5560 free (stub_name);
0955507f 5561 return NULL;
b715f643
TP		 5562 }
5563
5564 stub_entry->target_value = sym_value;
5565 stub_entry->target_section = sym_sec;
5566 stub_entry->stub_type = stub_type;
5567 stub_entry->h = hash;
5568 stub_entry->branch_type = branch_type;
5569
4f4faa4d
TP		 5570 if (sym_claimed)
5571 stub_entry->output_name = sym_name;
5572 else
b715f643 5573 {
4f4faa4d
TP		 5574 if (sym_name == NULL)
5575 sym_name = "unnamed";
5576 stub_entry->output_name = (char *)
5577 bfd_alloc (htab->stub_bfd, sizeof (THUMB2ARM_GLUE_ENTRY_NAME)
5578 + strlen (sym_name));
5579 if (stub_entry->output_name == NULL)
5580 {
5581 free (stub_name);
0955507f 5582 return NULL;
4f4faa4d 5583 }
b715f643 5584
4f4faa4d
TP		 5585 /* For historical reasons, use the existing names for ARM-to-Thumb and
5586 Thumb-to-ARM stubs. */
5587 r_type = ELF32_R_TYPE (irela->r_info);
5588 if ((r_type == (unsigned int) R_ARM_THM_CALL
5589 || r_type == (unsigned int) R_ARM_THM_JUMP24
5590 || r_type == (unsigned int) R_ARM_THM_JUMP19)
5591 && branch_type == ST_BRANCH_TO_ARM)
5592 sprintf (stub_entry->output_name, THUMB2ARM_GLUE_ENTRY_NAME, sym_name);
5593 else if ((r_type == (unsigned int) R_ARM_CALL
5594 || r_type == (unsigned int) R_ARM_JUMP24)
5595 && branch_type == ST_BRANCH_TO_THUMB)
5596 sprintf (stub_entry->output_name, ARM2THUMB_GLUE_ENTRY_NAME, sym_name);
5597 else
5598 sprintf (stub_entry->output_name, STUB_ENTRY_NAME, sym_name);
5599 }
b715f643
TP		 5600
5601 *new_stub = TRUE;
0955507f 5602 return stub_entry;
b715f643
TP		 5603}
5604
4ba2ef8f
TP		 5605/* Scan symbols in INPUT_BFD to identify secure entry functions needing a
5606 gateway veneer to transition from non secure to secure state and create them
5607 accordingly.
5608
5609 "ARMv8-M Security Extensions: Requirements on Development Tools" document
5610 defines the conditions that govern Secure Gateway veneer creation for a
5611 given symbol <SYM> as follows:
5612 - it has function type
5613 - it has non local binding
5614 - a symbol named __acle_se_<SYM> (called special symbol) exists with the
5615 same type, binding and value as <SYM> (called normal symbol).
5616 An entry function can handle secure state transition itself in which case
5617 its special symbol would have a different value from the normal symbol.
5618
5619 OUT_ATTR gives the output attributes, SYM_HASHES the symbol index to hash
5620 entry mapping while HTAB gives the name to hash entry mapping.
0955507f
TP		 5621 *CMSE_STUB_CREATED is increased by the number of secure gateway veneer
5622 created.
4ba2ef8f 5623
0955507f 5624 The return value gives whether a stub failed to be allocated. */
4ba2ef8f
TP		 5625
5626static bfd_boolean
5627cmse_scan (bfd *input_bfd, struct elf32_arm_link_hash_table *htab,
5628 obj_attribute *out_attr, struct elf_link_hash_entry **sym_hashes,
0955507f 5629 int *cmse_stub_created)
4ba2ef8f
TP		 5630{
5631 const struct elf_backend_data *bed;
5632 Elf_Internal_Shdr *symtab_hdr;
5633 unsigned i, j, sym_count, ext_start;
5634 Elf_Internal_Sym *cmse_sym, *local_syms;
5635 struct elf32_arm_link_hash_entry *hash, *cmse_hash = NULL;
5636 enum arm_st_branch_type branch_type;
5637 char *sym_name, *lsym_name;
5638 bfd_vma sym_value;
5639 asection *section;
0955507f
TP		 5640 struct elf32_arm_stub_hash_entry *stub_entry;
5641 bfd_boolean is_v8m, new_stub, cmse_invalid, ret = TRUE;
4ba2ef8f
TP		 5642
5643 bed = get_elf_backend_data (input_bfd);
5644 symtab_hdr = &elf_tdata (input_bfd)->symtab_hdr;
5645 sym_count = symtab_hdr->sh_size / bed->s->sizeof_sym;
5646 ext_start = symtab_hdr->sh_info;
5647 is_v8m = (out_attr[Tag_CPU_arch].i >= TAG_CPU_ARCH_V8M_BASE
5648 && out_attr[Tag_CPU_arch_profile].i == 'M');
5649
5650 local_syms = (Elf_Internal_Sym *) symtab_hdr->contents;
5651 if (local_syms == NULL)
5652 local_syms = bfd_elf_get_elf_syms (input_bfd, symtab_hdr,
5653 symtab_hdr->sh_info, 0, NULL, NULL,
5654 NULL);
5655 if (symtab_hdr->sh_info && local_syms == NULL)
5656 return FALSE;
5657
5658 /* Scan symbols. */
5659 for (i = 0; i < sym_count; i++)
5660 {
5661 cmse_invalid = FALSE;
5662
5663 if (i < ext_start)
5664 {
5665 cmse_sym = &local_syms[i];
5666 /* Not a special symbol. */
5667 if (!ARM_GET_SYM_CMSE_SPCL (cmse_sym->st_target_internal))
5668 continue;
5669 sym_name = bfd_elf_string_from_elf_section (input_bfd,
5670 symtab_hdr->sh_link,
5671 cmse_sym->st_name);
5672 /* Special symbol with local binding. */
5673 cmse_invalid = TRUE;
5674 }
5675 else
5676 {
5677 cmse_hash = elf32_arm_hash_entry (sym_hashes[i - ext_start]);
5678 sym_name = (char *) cmse_hash->root.root.root.string;
5679
5680 /* Not a special symbol. */
5681 if (!ARM_GET_SYM_CMSE_SPCL (cmse_hash->root.target_internal))
5682 continue;
5683
5684 /* Special symbol has incorrect binding or type. */
5685 if ((cmse_hash->root.root.type != bfd_link_hash_defined
5686 && cmse_hash->root.root.type != bfd_link_hash_defweak)
5687 || cmse_hash->root.type != STT_FUNC)
5688 cmse_invalid = TRUE;
5689 }
5690
5691 if (!is_v8m)
5692 {
4eca0228
AM		 5693 _bfd_error_handler (_("%B: Special symbol `%s' only allowed for "
5694 "ARMv8-M architecture or later."),
5695 input_bfd, sym_name);
4ba2ef8f
TP		 5696 is_v8m = TRUE; /* Avoid multiple warning. */
5697 ret = FALSE;
5698 }
5699
5700 if (cmse_invalid)
5701 {
4eca0228
AM		 5702 _bfd_error_handler (_("%B: invalid special symbol `%s'."),
5703 input_bfd, sym_name);
5704 _bfd_error_handler (_("It must be a global or weak function "
5705 "symbol."));
4ba2ef8f
TP		 5706 ret = FALSE;
5707 if (i < ext_start)
5708 continue;
5709 }
5710
5711 sym_name += strlen (CMSE_PREFIX);
5712 hash = (struct elf32_arm_link_hash_entry *)
5713 elf_link_hash_lookup (&(htab)->root, sym_name, FALSE, FALSE, TRUE);
5714
5715 /* No associated normal symbol or it is neither global nor weak. */
5716 if (!hash
5717 || (hash->root.root.type != bfd_link_hash_defined
5718 && hash->root.root.type != bfd_link_hash_defweak)
5719 || hash->root.type != STT_FUNC)
5720 {
5721 /* Initialize here to avoid warning about use of possibly
5722 uninitialized variable. */
5723 j = 0;
5724
5725 if (!hash)
5726 {
5727 /* Searching for a normal symbol with local binding. */
5728 for (; j < ext_start; j++)
5729 {
5730 lsym_name =
5731 bfd_elf_string_from_elf_section (input_bfd,
5732 symtab_hdr->sh_link,
5733 local_syms[j].st_name);
5734 if (!strcmp (sym_name, lsym_name))
5735 break;
5736 }
5737 }
5738
5739 if (hash || j < ext_start)
5740 {
4eca0228 5741 _bfd_error_handler
4ba2ef8f 5742 (_("%B: invalid standard symbol `%s'."), input_bfd, sym_name);
4eca0228 5743 _bfd_error_handler
4ba2ef8f
TP		 5744 (_("It must be a global or weak function symbol."));
5745 }
5746 else
4eca0228 5747 _bfd_error_handler
4ba2ef8f
TP		 5748 (_("%B: absent standard symbol `%s'."), input_bfd, sym_name);
5749 ret = FALSE;
5750 if (!hash)
5751 continue;
5752 }
5753
5754 sym_value = hash->root.root.u.def.value;
5755 section = hash->root.root.u.def.section;
5756
5757 if (cmse_hash->root.root.u.def.section != section)
5758 {
4eca0228 5759 _bfd_error_handler
4ba2ef8f
TP		 5760 (_("%B: `%s' and its special symbol are in different sections."),
5761 input_bfd, sym_name);
5762 ret = FALSE;
5763 }
5764 if (cmse_hash->root.root.u.def.value != sym_value)
5765 continue; /* Ignore: could be an entry function starting with SG. */
5766
5767 /* If this section is a link-once section that will be discarded, then
5768 don't create any stubs. */
5769 if (section->output_section == NULL)
5770 {
4eca0228 5771 _bfd_error_handler
4ba2ef8f
TP		 5772 (_("%B: entry function `%s' not output."), input_bfd, sym_name);
5773 continue;
5774 }
5775
5776 if (hash->root.size == 0)
5777 {
4eca0228 5778 _bfd_error_handler
4ba2ef8f
TP		 5779 (_("%B: entry function `%s' is empty."), input_bfd, sym_name);
5780 ret = FALSE;
5781 }
5782
5783 if (!ret)
5784 continue;
5785 branch_type = ARM_GET_SYM_BRANCH_TYPE (hash->root.target_internal);
0955507f 5786 stub_entry
4ba2ef8f
TP		 5787 = elf32_arm_create_stub (htab, arm_stub_cmse_branch_thumb_only,
5788 NULL, NULL, section, hash, sym_name,
5789 sym_value, branch_type, &new_stub);
5790
0955507f 5791 if (stub_entry == NULL)
4ba2ef8f
TP		 5792 ret = FALSE;
5793 else
5794 {
5795 BFD_ASSERT (new_stub);
0955507f 5796 (*cmse_stub_created)++;
4ba2ef8f
TP		 5797 }
5798 }
5799
5800 if (!symtab_hdr->contents)
5801 free (local_syms);
5802 return ret;
5803}
5804
0955507f
TP		 5805/* Return TRUE iff a symbol identified by its linker HASH entry is a secure
5806 code entry function, ie can be called from non secure code without using a
5807 veneer. */
5808
5809static bfd_boolean
5810cmse_entry_fct_p (struct elf32_arm_link_hash_entry *hash)
5811{
42484486 5812 bfd_byte contents[4];
0955507f
TP		 5813 uint32_t first_insn;
5814 asection *section;
5815 file_ptr offset;
5816 bfd *abfd;
5817
5818 /* Defined symbol of function type. */
5819 if (hash->root.root.type != bfd_link_hash_defined
5820 && hash->root.root.type != bfd_link_hash_defweak)
5821 return FALSE;
5822 if (hash->root.type != STT_FUNC)
5823 return FALSE;
5824
5825 /* Read first instruction. */
5826 section = hash->root.root.u.def.section;
5827 abfd = section->owner;
5828 offset = hash->root.root.u.def.value - section->vma;
42484486
TP		 5829 if (!bfd_get_section_contents (abfd, section, contents, offset,
5830 sizeof (contents)))
0955507f
TP		 5831 return FALSE;
5832
42484486
TP		 5833 first_insn = bfd_get_32 (abfd, contents);
5834
5835 /* Starts by SG instruction. */
0955507f
TP		 5836 return first_insn == 0xe97fe97f;
5837}
5838
5839/* Output the name (in symbol table) of the veneer GEN_ENTRY if it is a new
5840 secure gateway veneers (ie. the veneers was not in the input import library)
5841 and there is no output import library (GEN_INFO->out_implib_bfd is NULL. */
5842
5843static bfd_boolean
5844arm_list_new_cmse_stub (struct bfd_hash_entry *gen_entry, void *gen_info)
5845{
5846 struct elf32_arm_stub_hash_entry *stub_entry;
5847 struct bfd_link_info *info;
5848
5849 /* Massage our args to the form they really have. */
5850 stub_entry = (struct elf32_arm_stub_hash_entry *) gen_entry;
5851 info = (struct bfd_link_info *) gen_info;
5852
5853 if (info->out_implib_bfd)
5854 return TRUE;
5855
5856 if (stub_entry->stub_type != arm_stub_cmse_branch_thumb_only)
5857 return TRUE;
5858
5859 if (stub_entry->stub_offset == (bfd_vma) -1)
4eca0228 5860 _bfd_error_handler (" %s", stub_entry->output_name);
0955507f
TP		 5861
5862 return TRUE;
5863}
5864
5865/* Set offset of each secure gateway veneers so that its address remain
5866 identical to the one in the input import library referred by
5867 HTAB->in_implib_bfd. A warning is issued for veneers that disappeared
5868 (present in input import library but absent from the executable being
5869 linked) or if new veneers appeared and there is no output import library
5870 (INFO->out_implib_bfd is NULL and *CMSE_STUB_CREATED is bigger than the
5871 number of secure gateway veneers found in the input import library.
5872
5873 The function returns whether an error occurred. If no error occurred,
5874 *CMSE_STUB_CREATED gives the number of SG veneers created by both cmse_scan
5875 and this function and HTAB->new_cmse_stub_offset is set to the biggest
5876 veneer observed set for new veneers to be layed out after. */
5877
5878static bfd_boolean
5879set_cmse_veneer_addr_from_implib (struct bfd_link_info *info,
5880 struct elf32_arm_link_hash_table *htab,
5881 int *cmse_stub_created)
5882{
5883 long symsize;
5884 char *sym_name;
5885 flagword flags;
5886 long i, symcount;
5887 bfd *in_implib_bfd;
5888 asection *stub_out_sec;
5889 bfd_boolean ret = TRUE;
5890 Elf_Internal_Sym *intsym;
5891 const char *out_sec_name;
5892 bfd_size_type cmse_stub_size;
5893 asymbol **sympp = NULL, *sym;
5894 struct elf32_arm_link_hash_entry *hash;
5895 const insn_sequence *cmse_stub_template;
5896 struct elf32_arm_stub_hash_entry *stub_entry;
5897 int cmse_stub_template_size, new_cmse_stubs_created = *cmse_stub_created;
5898 bfd_vma veneer_value, stub_offset, next_cmse_stub_offset;
5899 bfd_vma cmse_stub_array_start = (bfd_vma) -1, cmse_stub_sec_vma = 0;
5900
5901 /* No input secure gateway import library. */
5902 if (!htab->in_implib_bfd)
5903 return TRUE;
5904
5905 in_implib_bfd = htab->in_implib_bfd;
5906 if (!htab->cmse_implib)
5907 {
4eca0228
AM		 5908 _bfd_error_handler (_("%B: --in-implib only supported for Secure "
5909 "Gateway import libraries."), in_implib_bfd);
0955507f
TP		 5910 return FALSE;
5911 }
5912
5913 /* Get symbol table size. */
5914 symsize = bfd_get_symtab_upper_bound (in_implib_bfd);
5915 if (symsize < 0)
5916 return FALSE;
5917
5918 /* Read in the input secure gateway import library's symbol table. */
5919 sympp = (asymbol **) xmalloc (symsize);
5920 symcount = bfd_canonicalize_symtab (in_implib_bfd, sympp);
5921 if (symcount < 0)
5922 {
5923 ret = FALSE;
5924 goto free_sym_buf;
5925 }
5926
5927 htab->new_cmse_stub_offset = 0;
5928 cmse_stub_size =
5929 find_stub_size_and_template (arm_stub_cmse_branch_thumb_only,
5930 &cmse_stub_template,
5931 &cmse_stub_template_size);
5932 out_sec_name =
5933 arm_dedicated_stub_output_section_name (arm_stub_cmse_branch_thumb_only);
5934 stub_out_sec =
5935 bfd_get_section_by_name (htab->obfd, out_sec_name);
5936 if (stub_out_sec != NULL)
5937 cmse_stub_sec_vma = stub_out_sec->vma;
5938
5939 /* Set addresses of veneers mentionned in input secure gateway import
5940 library's symbol table. */
5941 for (i = 0; i < symcount; i++)
5942 {
5943 sym = sympp[i];
5944 flags = sym->flags;
5945 sym_name = (char *) bfd_asymbol_name (sym);
5946 intsym = &((elf_symbol_type *) sym)->internal_elf_sym;
5947
5948 if (sym->section != bfd_abs_section_ptr
5949 || !(flags & (BSF_GLOBAL | BSF_WEAK))
5950 || (flags & BSF_FUNCTION) != BSF_FUNCTION
5951 || (ARM_GET_SYM_BRANCH_TYPE (intsym->st_target_internal)
5952 != ST_BRANCH_TO_THUMB))
5953 {
4eca0228
AM		 5954 _bfd_error_handler (_("%B: invalid import library entry: `%s'."),
5955 in_implib_bfd, sym_name);
5956 _bfd_error_handler (_("Symbol should be absolute, global and "
5957 "refer to Thumb functions."));
0955507f
TP		 5958 ret = FALSE;
5959 continue;
5960 }
5961
5962 veneer_value = bfd_asymbol_value (sym);
5963 stub_offset = veneer_value - cmse_stub_sec_vma;
5964 stub_entry = arm_stub_hash_lookup (&htab->stub_hash_table, sym_name,
5965 FALSE, FALSE);
5966 hash = (struct elf32_arm_link_hash_entry *)
5967 elf_link_hash_lookup (&(htab)->root, sym_name, FALSE, FALSE, TRUE);
5968
5969 /* Stub entry should have been created by cmse_scan or the symbol be of
5970 a secure function callable from non secure code. */
5971 if (!stub_entry && !hash)
5972 {
5973 bfd_boolean new_stub;
5974
4eca0228 5975 _bfd_error_handler
0955507f
TP		 5976 (_("Entry function `%s' disappeared from secure code."), sym_name);
5977 hash = (struct elf32_arm_link_hash_entry *)
5978 elf_link_hash_lookup (&(htab)->root, sym_name, TRUE, TRUE, TRUE);
5979 stub_entry
5980 = elf32_arm_create_stub (htab, arm_stub_cmse_branch_thumb_only,
5981 NULL, NULL, bfd_abs_section_ptr, hash,
5982 sym_name, veneer_value,
5983 ST_BRANCH_TO_THUMB, &new_stub);
5984 if (stub_entry == NULL)
5985 ret = FALSE;
5986 else
5987 {
5988 BFD_ASSERT (new_stub);
5989 new_cmse_stubs_created++;
5990 (*cmse_stub_created)++;
5991 }
5992 stub_entry->stub_template_size = stub_entry->stub_size = 0;
5993 stub_entry->stub_offset = stub_offset;
5994 }
5995 /* Symbol found is not callable from non secure code. */
5996 else if (!stub_entry)
5997 {
5998 if (!cmse_entry_fct_p (hash))
5999 {
4eca0228
AM		 6000 _bfd_error_handler (_("`%s' refers to a non entry function."),
6001 sym_name);
0955507f
TP		 6002 ret = FALSE;
6003 }
6004 continue;
6005 }
6006 else
6007 {
6008 /* Only stubs for SG veneers should have been created. */
6009 BFD_ASSERT (stub_entry->stub_type == arm_stub_cmse_branch_thumb_only);
6010
6011 /* Check visibility hasn't changed. */
6012 if (!!(flags & BSF_GLOBAL)
6013 != (hash->root.root.type == bfd_link_hash_defined))
4eca0228 6014 _bfd_error_handler
0955507f
TP		 6015 (_("%B: visibility of symbol `%s' has changed."), in_implib_bfd,
6016 sym_name);
6017
6018 stub_entry->stub_offset = stub_offset;
6019 }
6020
6021 /* Size should match that of a SG veneer. */
6022 if (intsym->st_size != cmse_stub_size)
6023 {
4eca0228
AM		 6024 _bfd_error_handler (_("%B: incorrect size for symbol `%s'."),
6025 in_implib_bfd, sym_name);
0955507f
TP		 6026 ret = FALSE;
6027 }
6028
6029 /* Previous veneer address is before current SG veneer section. */
6030 if (veneer_value < cmse_stub_sec_vma)
6031 {
6032 /* Avoid offset underflow. */
6033 if (stub_entry)
6034 stub_entry->stub_offset = 0;
6035 stub_offset = 0;
6036 ret = FALSE;
6037 }
6038
6039 /* Complain if stub offset not a multiple of stub size. */
6040 if (stub_offset % cmse_stub_size)
6041 {
4eca0228 6042 _bfd_error_handler
0955507f
TP		 6043 (_("Offset of veneer for entry function `%s' not a multiple of "
6044 "its size."), sym_name);
6045 ret = FALSE;
6046 }
6047
6048 if (!ret)
6049 continue;
6050
6051 new_cmse_stubs_created--;
6052 if (veneer_value < cmse_stub_array_start)
6053 cmse_stub_array_start = veneer_value;
6054 next_cmse_stub_offset = stub_offset + ((cmse_stub_size + 7) & ~7);
6055 if (next_cmse_stub_offset > htab->new_cmse_stub_offset)
6056 htab->new_cmse_stub_offset = next_cmse_stub_offset;
6057 }
6058
6059 if (!info->out_implib_bfd && new_cmse_stubs_created != 0)
6060 {
6061 BFD_ASSERT (new_cmse_stubs_created > 0);
4eca0228 6062 _bfd_error_handler
0955507f
TP		 6063 (_("new entry function(s) introduced but no output import library "
6064 "specified:"));
6065 bfd_hash_traverse (&htab->stub_hash_table, arm_list_new_cmse_stub, info);
6066 }
6067
6068 if (cmse_stub_array_start != cmse_stub_sec_vma)
6069 {
4eca0228 6070 _bfd_error_handler
0955507f
TP		 6071 (_("Start address of `%s' is different from previous link."),
6072 out_sec_name);
6073 ret = FALSE;
6074 }
6075
6076free_sym_buf:
6077 free (sympp);
6078 return ret;
6079}
6080
906e58ca
NC		 6081/* Determine and set the size of the stub section for a final link.
6082
6083 The basic idea here is to examine all the relocations looking for
6084 PC-relative calls to a target that is unreachable with a "bl"
6085 instruction. */
6086
6087bfd_boolean
6088elf32_arm_size_stubs (bfd *output_bfd,
6089 bfd *stub_bfd,
6090 struct bfd_link_info *info,
6091 bfd_signed_vma group_size,
7a89b94e 6092 asection * (*add_stub_section) (const char *, asection *,
6bde4c52 6093 asection *,
7a89b94e 6094 unsigned int),
906e58ca
NC		 6095 void (*layout_sections_again) (void))
6096{
0955507f 6097 bfd_boolean ret = TRUE;
4ba2ef8f 6098 obj_attribute *out_attr;
0955507f 6099 int cmse_stub_created = 0;
906e58ca 6100 bfd_size_type stub_group_size;
4ba2ef8f 6101 bfd_boolean m_profile, stubs_always_after_branch, first_veneer_scan = TRUE;
906e58ca 6102 struct elf32_arm_link_hash_table *htab = elf32_arm_hash_table (info);
48229727 6103 struct a8_erratum_fix *a8_fixes = NULL;
eb7c4339 6104 unsigned int num_a8_fixes = 0, a8_fix_table_size = 10;
48229727
JB		 6105 struct a8_erratum_reloc *a8_relocs = NULL;
6106 unsigned int num_a8_relocs = 0, a8_reloc_table_size = 10, i;
6107
4dfe6ac6
NC		 6108 if (htab == NULL)
6109 return FALSE;
6110
48229727
JB		 6111 if (htab->fix_cortex_a8)
6112 {
21d799b5 6113 a8_fixes = (struct a8_erratum_fix *)
99059e56 6114 bfd_zmalloc (sizeof (struct a8_erratum_fix) * a8_fix_table_size);
21d799b5 6115 a8_relocs = (struct a8_erratum_reloc *)
99059e56 6116 bfd_zmalloc (sizeof (struct a8_erratum_reloc) * a8_reloc_table_size);
48229727 6117 }
906e58ca
NC		 6118
6119 /* Propagate mach to stub bfd, because it may not have been
6120 finalized when we created stub_bfd. */
6121 bfd_set_arch_mach (stub_bfd, bfd_get_arch (output_bfd),
6122 bfd_get_mach (output_bfd));
6123
6124 /* Stash our params away. */
6125 htab->stub_bfd = stub_bfd;
6126 htab->add_stub_section = add_stub_section;
6127 htab->layout_sections_again = layout_sections_again;
07d72278 6128 stubs_always_after_branch = group_size < 0;
48229727 6129
4ba2ef8f
TP		 6130 out_attr = elf_known_obj_attributes_proc (output_bfd);
6131 m_profile = out_attr[Tag_CPU_arch_profile].i == 'M';
0955507f 6132
48229727
JB		 6133 /* The Cortex-A8 erratum fix depends on stubs not being in the same 4K page
6134 as the first half of a 32-bit branch straddling two 4K pages. This is a
6135 crude way of enforcing that. */
6136 if (htab->fix_cortex_a8)
6137 stubs_always_after_branch = 1;
6138
906e58ca
NC		 6139 if (group_size < 0)
6140 stub_group_size = -group_size;
6141 else
6142 stub_group_size = group_size;
6143
6144 if (stub_group_size == 1)
6145 {
6146 /* Default values. */
6147 /* Thumb branch range is +-4MB has to be used as the default
6148 maximum size (a given section can contain both ARM and Thumb
6149 code, so the worst case has to be taken into account).
6150
6151 This value is 24K less than that, which allows for 2025
6152 12-byte stubs. If we exceed that, then we will fail to link.
6153 The user will have to relink with an explicit group size
6154 option. */
6155 stub_group_size = 4170000;
6156 }
6157
07d72278 6158 group_sections (htab, stub_group_size, stubs_always_after_branch);
906e58ca 6159
3ae046cc
NS		 6160 /* If we're applying the cortex A8 fix, we need to determine the
6161 program header size now, because we cannot change it later --
6162 that could alter section placements. Notice the A8 erratum fix
6163 ends up requiring the section addresses to remain unchanged
6164 modulo the page size. That's something we cannot represent
6165 inside BFD, and we don't want to force the section alignment to
6166 be the page size. */
6167 if (htab->fix_cortex_a8)
6168 (*htab->layout_sections_again) ();
6169
906e58ca
NC		 6170 while (1)
6171 {
6172 bfd *input_bfd;
6173 unsigned int bfd_indx;
6174 asection *stub_sec;
d7c5bd02 6175 enum elf32_arm_stub_type stub_type;
eb7c4339
NS		 6176 bfd_boolean stub_changed = FALSE;
6177 unsigned prev_num_a8_fixes = num_a8_fixes;
906e58ca 6178
48229727 6179 num_a8_fixes = 0;
906e58ca
NC		 6180 for (input_bfd = info->input_bfds, bfd_indx = 0;
6181 input_bfd != NULL;
c72f2fb2 6182 input_bfd = input_bfd->link.next, bfd_indx++)
906e58ca
NC		 6183 {
6184 Elf_Internal_Shdr *symtab_hdr;
6185 asection *section;
6186 Elf_Internal_Sym *local_syms = NULL;
6187
99059e56
RM		 6188 if (!is_arm_elf (input_bfd))
6189 continue;
adbcc655 6190
48229727
JB		 6191 num_a8_relocs = 0;
6192
906e58ca
NC		 6193 /* We'll need the symbol table in a second. */
6194 symtab_hdr = &elf_tdata (input_bfd)->symtab_hdr;
6195 if (symtab_hdr->sh_info == 0)
6196 continue;
6197
4ba2ef8f
TP		 6198 /* Limit scan of symbols to object file whose profile is
6199 Microcontroller to not hinder performance in the general case. */
6200 if (m_profile && first_veneer_scan)
6201 {
6202 struct elf_link_hash_entry **sym_hashes;
6203
6204 sym_hashes = elf_sym_hashes (input_bfd);
6205 if (!cmse_scan (input_bfd, htab, out_attr, sym_hashes,
0955507f 6206 &cmse_stub_created))
4ba2ef8f 6207 goto error_ret_free_local;
0955507f
TP		 6208
6209 if (cmse_stub_created != 0)
6210 stub_changed = TRUE;
4ba2ef8f
TP		 6211 }
6212
906e58ca
NC		 6213 /* Walk over each section attached to the input bfd. */
6214 for (section = input_bfd->sections;
6215 section != NULL;
6216 section = section->next)
6217 {
6218 Elf_Internal_Rela *internal_relocs, *irelaend, *irela;
6219
6220 /* If there aren't any relocs, then there's nothing more
6221 to do. */
6222 if ((section->flags & SEC_RELOC) == 0
6223 || section->reloc_count == 0
6224 || (section->flags & SEC_CODE) == 0)
6225 continue;
6226
6227 /* If this section is a link-once section that will be
6228 discarded, then don't create any stubs. */
6229 if (section->output_section == NULL
6230 || section->output_section->owner != output_bfd)
6231 continue;
6232
6233 /* Get the relocs. */
6234 internal_relocs
6235 = _bfd_elf_link_read_relocs (input_bfd, section, NULL,
6236 NULL, info->keep_memory);
6237 if (internal_relocs == NULL)
6238 goto error_ret_free_local;
6239
6240 /* Now examine each relocation. */
6241 irela = internal_relocs;
6242 irelaend = irela + section->reloc_count;
6243 for (; irela < irelaend; irela++)
6244 {
6245 unsigned int r_type, r_indx;
906e58ca
NC		 6246 asection *sym_sec;
6247 bfd_vma sym_value;
6248 bfd_vma destination;
6249 struct elf32_arm_link_hash_entry *hash;
7413f23f 6250 const char *sym_name;
34e77a92 6251 unsigned char st_type;
35fc36a8 6252 enum arm_st_branch_type branch_type;
48229727 6253 bfd_boolean created_stub = FALSE;
906e58ca
NC		 6254
6255 r_type = ELF32_R_TYPE (irela->r_info);
6256 r_indx = ELF32_R_SYM (irela->r_info);
6257
6258 if (r_type >= (unsigned int) R_ARM_max)
6259 {
6260 bfd_set_error (bfd_error_bad_value);
6261 error_ret_free_internal:
6262 if (elf_section_data (section)->relocs == NULL)
6263 free (internal_relocs);
15dd01b1
TP		 6264 /* Fall through. */
6265 error_ret_free_local:
6266 if (local_syms != NULL
6267 && (symtab_hdr->contents
6268 != (unsigned char *) local_syms))
6269 free (local_syms);
6270 return FALSE;
906e58ca 6271 }
b38cadfb 6272
0855e32b
NS		 6273 hash = NULL;
6274 if (r_indx >= symtab_hdr->sh_info)
6275 hash = elf32_arm_hash_entry
6276 (elf_sym_hashes (input_bfd)
6277 [r_indx - symtab_hdr->sh_info]);
b38cadfb 6278
0855e32b
NS		 6279 /* Only look for stubs on branch instructions, or
6280 non-relaxed TLSCALL */
906e58ca 6281 if ((r_type != (unsigned int) R_ARM_CALL)
155d87d7
CL		 6282 && (r_type != (unsigned int) R_ARM_THM_CALL)
6283 && (r_type != (unsigned int) R_ARM_JUMP24)
48229727
JB		 6284 && (r_type != (unsigned int) R_ARM_THM_JUMP19)
6285 && (r_type != (unsigned int) R_ARM_THM_XPC22)
155d87d7 6286 && (r_type != (unsigned int) R_ARM_THM_JUMP24)
0855e32b
NS		 6287 && (r_type != (unsigned int) R_ARM_PLT32)
6288 && !((r_type == (unsigned int) R_ARM_TLS_CALL
6289 || r_type == (unsigned int) R_ARM_THM_TLS_CALL)
6290 && r_type == elf32_arm_tls_transition
6291 (info, r_type, &hash->root)
6292 && ((hash ? hash->tls_type
6293 : (elf32_arm_local_got_tls_type
6294 (input_bfd)[r_indx]))
6295 & GOT_TLS_GDESC) != 0))
906e58ca
NC		 6296 continue;
6297
6298 /* Now determine the call target, its name, value,
6299 section. */
6300 sym_sec = NULL;
6301 sym_value = 0;
6302 destination = 0;
7413f23f 6303 sym_name = NULL;
b38cadfb 6304
0855e32b
NS		 6305 if (r_type == (unsigned int) R_ARM_TLS_CALL
6306 || r_type == (unsigned int) R_ARM_THM_TLS_CALL)
6307 {
6308 /* A non-relaxed TLS call. The target is the
6309 plt-resident trampoline and nothing to do
6310 with the symbol. */
6311 BFD_ASSERT (htab->tls_trampoline > 0);
6312 sym_sec = htab->root.splt;
6313 sym_value = htab->tls_trampoline;
6314 hash = 0;
34e77a92 6315 st_type = STT_FUNC;
35fc36a8 6316 branch_type = ST_BRANCH_TO_ARM;
0855e32b
NS		 6317 }
6318 else if (!hash)
906e58ca
NC		 6319 {
6320 /* It's a local symbol. */
6321 Elf_Internal_Sym *sym;
906e58ca
NC		 6322
6323 if (local_syms == NULL)
6324 {
6325 local_syms
6326 = (Elf_Internal_Sym *) symtab_hdr->contents;
6327 if (local_syms == NULL)
6328 local_syms
6329 = bfd_elf_get_elf_syms (input_bfd, symtab_hdr,
6330 symtab_hdr->sh_info, 0,
6331 NULL, NULL, NULL);
6332 if (local_syms == NULL)
6333 goto error_ret_free_internal;
6334 }
6335
6336 sym = local_syms + r_indx;
f6d250ce
TS		 6337 if (sym->st_shndx == SHN_UNDEF)
6338 sym_sec = bfd_und_section_ptr;
6339 else if (sym->st_shndx == SHN_ABS)
6340 sym_sec = bfd_abs_section_ptr;
6341 else if (sym->st_shndx == SHN_COMMON)
6342 sym_sec = bfd_com_section_ptr;
6343 else
6344 sym_sec =
6345 bfd_section_from_elf_index (input_bfd, sym->st_shndx);
6346
ffcb4889
NS		 6347 if (!sym_sec)
6348 /* This is an undefined symbol. It can never
6a631e86 6349 be resolved. */
ffcb4889 6350 continue;
fe33d2fa 6351
906e58ca
NC		 6352 if (ELF_ST_TYPE (sym->st_info) != STT_SECTION)
6353 sym_value = sym->st_value;
6354 destination = (sym_value + irela->r_addend
6355 + sym_sec->output_offset
6356 + sym_sec->output_section->vma);
34e77a92 6357 st_type = ELF_ST_TYPE (sym->st_info);
39d911fc
TP		 6358 branch_type =
6359 ARM_GET_SYM_BRANCH_TYPE (sym->st_target_internal);
7413f23f
DJ		 6360 sym_name
6361 = bfd_elf_string_from_elf_section (input_bfd,
6362 symtab_hdr->sh_link,
6363 sym->st_name);
906e58ca
NC		 6364 }
6365 else
6366 {
6367 /* It's an external symbol. */
906e58ca
NC		 6368 while (hash->root.root.type == bfd_link_hash_indirect
6369 || hash->root.root.type == bfd_link_hash_warning)
6370 hash = ((struct elf32_arm_link_hash_entry *)
6371 hash->root.root.u.i.link);
6372
6373 if (hash->root.root.type == bfd_link_hash_defined
6374 || hash->root.root.type == bfd_link_hash_defweak)
6375 {
6376 sym_sec = hash->root.root.u.def.section;
6377 sym_value = hash->root.root.u.def.value;
022f8312
CL		 6378
6379 struct elf32_arm_link_hash_table *globals =
6380 elf32_arm_hash_table (info);
6381
6382 /* For a destination in a shared library,
6383 use the PLT stub as target address to
6384 decide whether a branch stub is
6385 needed. */
4dfe6ac6 6386 if (globals != NULL
362d30a1 6387 && globals->root.splt != NULL
4dfe6ac6 6388 && hash != NULL
022f8312
CL		 6389 && hash->root.plt.offset != (bfd_vma) -1)
6390 {
362d30a1 6391 sym_sec = globals->root.splt;
022f8312
CL		 6392 sym_value = hash->root.plt.offset;
6393 if (sym_sec->output_section != NULL)
6394 destination = (sym_value
6395 + sym_sec->output_offset
6396 + sym_sec->output_section->vma);
6397 }
6398 else if (sym_sec->output_section != NULL)
906e58ca
NC		 6399 destination = (sym_value + irela->r_addend
6400 + sym_sec->output_offset
6401 + sym_sec->output_section->vma);
6402 }
69c5861e
CL		 6403 else if ((hash->root.root.type == bfd_link_hash_undefined)
6404 || (hash->root.root.type == bfd_link_hash_undefweak))
6405 {
6406 /* For a shared library, use the PLT stub as
6407 target address to decide whether a long
6408 branch stub is needed.
6409 For absolute code, they cannot be handled. */
6410 struct elf32_arm_link_hash_table *globals =
6411 elf32_arm_hash_table (info);
6412
4dfe6ac6 6413 if (globals != NULL
362d30a1 6414 && globals->root.splt != NULL
4dfe6ac6 6415 && hash != NULL
69c5861e
CL		 6416 && hash->root.plt.offset != (bfd_vma) -1)
6417 {
362d30a1 6418 sym_sec = globals->root.splt;
69c5861e
CL		 6419 sym_value = hash->root.plt.offset;
6420 if (sym_sec->output_section != NULL)
6421 destination = (sym_value
6422 + sym_sec->output_offset
6423 + sym_sec->output_section->vma);
6424 }
6425 else
6426 continue;
6427 }
906e58ca
NC		 6428 else
6429 {
6430 bfd_set_error (bfd_error_bad_value);
6431 goto error_ret_free_internal;
6432 }
34e77a92 6433 st_type = hash->root.type;
39d911fc
TP		 6434 branch_type =
6435 ARM_GET_SYM_BRANCH_TYPE (hash->root.target_internal);
7413f23f 6436 sym_name = hash->root.root.root.string;
906e58ca
NC		 6437 }
6438
48229727 6439 do
7413f23f 6440 {
b715f643 6441 bfd_boolean new_stub;
0955507f 6442 struct elf32_arm_stub_hash_entry *stub_entry;
b715f643 6443
48229727
JB		 6444 /* Determine what (if any) linker stub is needed. */
6445 stub_type = arm_type_of_stub (info, section, irela,
34e77a92
RS		 6446 st_type, &branch_type,
6447 hash, destination, sym_sec,
48229727
JB		 6448 input_bfd, sym_name);
6449 if (stub_type == arm_stub_none)
6450 break;
6451
48229727
JB		 6452 /* We've either created a stub for this reloc already,
6453 or we are about to. */
0955507f 6454 stub_entry =
b715f643
TP		 6455 elf32_arm_create_stub (htab, stub_type, section, irela,
6456 sym_sec, hash,
6457 (char *) sym_name, sym_value,
6458 branch_type, &new_stub);
7413f23f 6459
0955507f 6460 created_stub = stub_entry != NULL;
b715f643
TP		 6461 if (!created_stub)
6462 goto error_ret_free_internal;
6463 else if (!new_stub)
6464 break;
99059e56 6465 else
b715f643 6466 stub_changed = TRUE;
99059e56
RM		 6467 }
6468 while (0);
6469
6470 /* Look for relocations which might trigger Cortex-A8
6471 erratum. */
6472 if (htab->fix_cortex_a8
6473 && (r_type == (unsigned int) R_ARM_THM_JUMP24
6474 || r_type == (unsigned int) R_ARM_THM_JUMP19
6475 || r_type == (unsigned int) R_ARM_THM_CALL
6476 || r_type == (unsigned int) R_ARM_THM_XPC22))
6477 {
6478 bfd_vma from = section->output_section->vma
6479 + section->output_offset
6480 + irela->r_offset;
6481
6482 if ((from & 0xfff) == 0xffe)
6483 {
6484 /* Found a candidate. Note we haven't checked the
6485 destination is within 4K here: if we do so (and
6486 don't create an entry in a8_relocs) we can't tell
6487 that a branch should have been relocated when
6488 scanning later. */
6489 if (num_a8_relocs == a8_reloc_table_size)
6490 {
6491 a8_reloc_table_size *= 2;
6492 a8_relocs = (struct a8_erratum_reloc *)
6493 bfd_realloc (a8_relocs,
6494 sizeof (struct a8_erratum_reloc)
6495 * a8_reloc_table_size);
6496 }
6497
6498 a8_relocs[num_a8_relocs].from = from;
6499 a8_relocs[num_a8_relocs].destination = destination;
6500 a8_relocs[num_a8_relocs].r_type = r_type;
6501 a8_relocs[num_a8_relocs].branch_type = branch_type;
6502 a8_relocs[num_a8_relocs].sym_name = sym_name;
6503 a8_relocs[num_a8_relocs].non_a8_stub = created_stub;
6504 a8_relocs[num_a8_relocs].hash = hash;
6505
6506 num_a8_relocs++;
6507 }
6508 }
906e58ca
NC		 6509 }
6510
99059e56
RM		 6511 /* We're done with the internal relocs, free them. */
6512 if (elf_section_data (section)->relocs == NULL)
6513 free (internal_relocs);
6514 }
48229727 6515
99059e56 6516 if (htab->fix_cortex_a8)
48229727 6517 {
99059e56
RM		 6518 /* Sort relocs which might apply to Cortex-A8 erratum. */
6519 qsort (a8_relocs, num_a8_relocs,
eb7c4339 6520 sizeof (struct a8_erratum_reloc),
99059e56 6521 &a8_reloc_compare);
48229727 6522
99059e56
RM		 6523 /* Scan for branches which might trigger Cortex-A8 erratum. */
6524 if (cortex_a8_erratum_scan (input_bfd, info, &a8_fixes,
48229727 6525 &num_a8_fixes, &a8_fix_table_size,
eb7c4339
NS		 6526 a8_relocs, num_a8_relocs,
6527 prev_num_a8_fixes, &stub_changed)
6528 != 0)
48229727 6529 goto error_ret_free_local;
5e681ec4 6530 }
7f991970
AM		 6531
6532 if (local_syms != NULL
6533 && symtab_hdr->contents != (unsigned char *) local_syms)
6534 {
6535 if (!info->keep_memory)
6536 free (local_syms);
6537 else
6538 symtab_hdr->contents = (unsigned char *) local_syms;
6539 }
5e681ec4
PB		 6540 }
6541
0955507f
TP		 6542 if (first_veneer_scan
6543 && !set_cmse_veneer_addr_from_implib (info, htab,
6544 &cmse_stub_created))
6545 ret = FALSE;
6546
eb7c4339 6547 if (prev_num_a8_fixes != num_a8_fixes)
99059e56 6548 stub_changed = TRUE;
48229727 6549
906e58ca
NC		 6550 if (!stub_changed)
6551 break;
5e681ec4 6552
906e58ca
NC		 6553 /* OK, we've added some stubs. Find out the new size of the
6554 stub sections. */
6555 for (stub_sec = htab->stub_bfd->sections;
6556 stub_sec != NULL;
6557 stub_sec = stub_sec->next)
3e6b1042
DJ		 6558 {
6559 /* Ignore non-stub sections. */
6560 if (!strstr (stub_sec->name, STUB_SUFFIX))
6561 continue;
6562
6563 stub_sec->size = 0;
6564 }
b34b2d70 6565
0955507f
TP		 6566 /* Add new SG veneers after those already in the input import
6567 library. */
6568 for (stub_type = arm_stub_none + 1; stub_type < max_stub_type;
6569 stub_type++)
6570 {
6571 bfd_vma *start_offset_p;
6572 asection **stub_sec_p;
6573
6574 start_offset_p = arm_new_stubs_start_offset_ptr (htab, stub_type);
6575 stub_sec_p = arm_dedicated_stub_input_section_ptr (htab, stub_type);
6576 if (start_offset_p == NULL)
6577 continue;
6578
6579 BFD_ASSERT (stub_sec_p != NULL);
6580 if (*stub_sec_p != NULL)
6581 (*stub_sec_p)->size = *start_offset_p;
6582 }
6583
d7c5bd02 6584 /* Compute stub section size, considering padding. */
906e58ca 6585 bfd_hash_traverse (&htab->stub_hash_table, arm_size_one_stub, htab);
d7c5bd02
TP		 6586 for (stub_type = arm_stub_none + 1; stub_type < max_stub_type;
6587 stub_type++)
6588 {
6589 int size, padding;
6590 asection **stub_sec_p;
6591
6592 padding = arm_dedicated_stub_section_padding (stub_type);
6593 stub_sec_p = arm_dedicated_stub_input_section_ptr (htab, stub_type);
6594 /* Skip if no stub input section or no stub section padding
6595 required. */
6596 if ((stub_sec_p != NULL && *stub_sec_p == NULL) || padding == 0)
6597 continue;
6598 /* Stub section padding required but no dedicated section. */
6599 BFD_ASSERT (stub_sec_p);
6600
6601 size = (*stub_sec_p)->size;
6602 size = (size + padding - 1) & ~(padding - 1);
6603 (*stub_sec_p)->size = size;
6604 }
906e58ca 6605
48229727
JB		 6606 /* Add Cortex-A8 erratum veneers to stub section sizes too. */
6607 if (htab->fix_cortex_a8)
99059e56
RM		 6608 for (i = 0; i < num_a8_fixes; i++)
6609 {
48229727 6610 stub_sec = elf32_arm_create_or_find_stub_sec (NULL,
daa4adae 6611 a8_fixes[i].section, htab, a8_fixes[i].stub_type);
48229727
JB		 6612
6613 if (stub_sec == NULL)
7f991970 6614 return FALSE;
48229727 6615
99059e56
RM		 6616 stub_sec->size
6617 += find_stub_size_and_template (a8_fixes[i].stub_type, NULL,
6618 NULL);
6619 }
48229727
JB		 6620
6621
906e58ca
NC		 6622 /* Ask the linker to do its stuff. */
6623 (*htab->layout_sections_again) ();
4ba2ef8f 6624 first_veneer_scan = FALSE;
ba93b8ac
DJ		 6625 }
6626
48229727
JB		 6627 /* Add stubs for Cortex-A8 erratum fixes now. */
6628 if (htab->fix_cortex_a8)
6629 {
6630 for (i = 0; i < num_a8_fixes; i++)
99059e56
RM		 6631 {
6632 struct elf32_arm_stub_hash_entry *stub_entry;
6633 char *stub_name = a8_fixes[i].stub_name;
6634 asection *section = a8_fixes[i].section;
6635 unsigned int section_id = a8_fixes[i].section->id;
6636 asection *link_sec = htab->stub_group[section_id].link_sec;
6637 asection *stub_sec = htab->stub_group[section_id].stub_sec;
6638 const insn_sequence *template_sequence;
6639 int template_size, size = 0;
6640
6641 stub_entry = arm_stub_hash_lookup (&htab->stub_hash_table, stub_name,
6642 TRUE, FALSE);
6643 if (stub_entry == NULL)
6644 {
4eca0228
AM		 6645 _bfd_error_handler (_("%s: cannot create stub entry %s"),
6646 section->owner, stub_name);
99059e56
RM		 6647 return FALSE;
6648 }
6649
6650 stub_entry->stub_sec = stub_sec;
0955507f 6651 stub_entry->stub_offset = (bfd_vma) -1;
99059e56
RM		 6652 stub_entry->id_sec = link_sec;
6653 stub_entry->stub_type = a8_fixes[i].stub_type;
8d9d9490 6654 stub_entry->source_value = a8_fixes[i].offset;
99059e56 6655 stub_entry->target_section = a8_fixes[i].section;
8d9d9490 6656 stub_entry->target_value = a8_fixes[i].target_offset;
99059e56 6657 stub_entry->orig_insn = a8_fixes[i].orig_insn;
35fc36a8 6658 stub_entry->branch_type = a8_fixes[i].branch_type;
48229727 6659
99059e56
RM		 6660 size = find_stub_size_and_template (a8_fixes[i].stub_type,
6661 &template_sequence,
6662 &template_size);
48229727 6663
99059e56
RM		 6664 stub_entry->stub_size = size;
6665 stub_entry->stub_template = template_sequence;
6666 stub_entry->stub_template_size = template_size;
6667 }
48229727
JB		 6668
6669 /* Stash the Cortex-A8 erratum fix array for use later in
99059e56 6670 elf32_arm_write_section(). */
48229727
JB		 6671 htab->a8_erratum_fixes = a8_fixes;
6672 htab->num_a8_erratum_fixes = num_a8_fixes;
6673 }
6674 else
6675 {
6676 htab->a8_erratum_fixes = NULL;
6677 htab->num_a8_erratum_fixes = 0;
6678 }
0955507f 6679 return ret;
5e681ec4
PB		 6680}
6681
906e58ca
NC		 6682/* Build all the stubs associated with the current output file. The
6683 stubs are kept in a hash table attached to the main linker hash
6684 table. We also set up the .plt entries for statically linked PIC
6685 functions here. This function is called via arm_elf_finish in the
6686 linker. */
252b5132 6687
906e58ca
NC		 6688bfd_boolean
6689elf32_arm_build_stubs (struct bfd_link_info *info)
252b5132 6690{
906e58ca
NC		 6691 asection *stub_sec;
6692 struct bfd_hash_table *table;
0955507f 6693 enum elf32_arm_stub_type stub_type;
906e58ca 6694 struct elf32_arm_link_hash_table *htab;
252b5132 6695
906e58ca 6696 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 6697 if (htab == NULL)
6698 return FALSE;
252b5132 6699
906e58ca
NC		 6700 for (stub_sec = htab->stub_bfd->sections;
6701 stub_sec != NULL;
6702 stub_sec = stub_sec->next)
252b5132 6703 {
906e58ca
NC		 6704 bfd_size_type size;
6705
8029a119 6706 /* Ignore non-stub sections. */
906e58ca
NC		 6707 if (!strstr (stub_sec->name, STUB_SUFFIX))
6708 continue;
6709
d7c5bd02 6710 /* Allocate memory to hold the linker stubs. Zeroing the stub sections
0955507f
TP		 6711 must at least be done for stub section requiring padding and for SG
6712 veneers to ensure that a non secure code branching to a removed SG
6713 veneer causes an error. */
906e58ca 6714 size = stub_sec->size;
21d799b5 6715 stub_sec->contents = (unsigned char *) bfd_zalloc (htab->stub_bfd, size);
906e58ca
NC		 6716 if (stub_sec->contents == NULL && size != 0)
6717 return FALSE;
0955507f 6718
906e58ca 6719 stub_sec->size = 0;
252b5132
RH		 6720 }
6721
0955507f
TP		 6722 /* Add new SG veneers after those already in the input import library. */
6723 for (stub_type = arm_stub_none + 1; stub_type < max_stub_type; stub_type++)
6724 {
6725 bfd_vma *start_offset_p;
6726 asection **stub_sec_p;
6727
6728 start_offset_p = arm_new_stubs_start_offset_ptr (htab, stub_type);
6729 stub_sec_p = arm_dedicated_stub_input_section_ptr (htab, stub_type);
6730 if (start_offset_p == NULL)
6731 continue;
6732
6733 BFD_ASSERT (stub_sec_p != NULL);
6734 if (*stub_sec_p != NULL)
6735 (*stub_sec_p)->size = *start_offset_p;
6736 }
6737
906e58ca
NC		 6738 /* Build the stubs as directed by the stub hash table. */
6739 table = &htab->stub_hash_table;
6740 bfd_hash_traverse (table, arm_build_one_stub, info);
eb7c4339
NS		 6741 if (htab->fix_cortex_a8)
6742 {
6743 /* Place the cortex a8 stubs last. */
6744 htab->fix_cortex_a8 = -1;
6745 bfd_hash_traverse (table, arm_build_one_stub, info);
6746 }
252b5132 6747
906e58ca 6748 return TRUE;
252b5132
RH		 6749}
6750
9b485d32
NC		 6751/* Locate the Thumb encoded calling stub for NAME. */
6752
252b5132 6753static struct elf_link_hash_entry *
57e8b36a
NC		 6754find_thumb_glue (struct bfd_link_info *link_info,
6755 const char *name,
f2a9dd69 6756 char **error_message)
252b5132
RH		 6757{
6758 char *tmp_name;
6759 struct elf_link_hash_entry *hash;
6760 struct elf32_arm_link_hash_table *hash_table;
6761
6762 /* We need a pointer to the armelf specific hash table. */
6763 hash_table = elf32_arm_hash_table (link_info);
4dfe6ac6
NC		 6764 if (hash_table == NULL)
6765 return NULL;
252b5132 6766
21d799b5 6767 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen (name)
99059e56 6768 + strlen (THUMB2ARM_GLUE_ENTRY_NAME) + 1);
252b5132
RH		 6769
6770 BFD_ASSERT (tmp_name);
6771
6772 sprintf (tmp_name, THUMB2ARM_GLUE_ENTRY_NAME, name);
6773
6774 hash = elf_link_hash_lookup
b34976b6 6775 (&(hash_table)->root, tmp_name, FALSE, FALSE, TRUE);
252b5132 6776
b1657152
AM		 6777 if (hash == NULL
6778 && asprintf (error_message, _("unable to find THUMB glue '%s' for '%s'"),
6779 tmp_name, name) == -1)
6780 *error_message = (char *) bfd_errmsg (bfd_error_system_call);
252b5132
RH		 6781
6782 free (tmp_name);
6783
6784 return hash;
6785}
6786
9b485d32
NC		 6787/* Locate the ARM encoded calling stub for NAME. */
6788
252b5132 6789static struct elf_link_hash_entry *
57e8b36a
NC		 6790find_arm_glue (struct bfd_link_info *link_info,
6791 const char *name,
f2a9dd69 6792 char **error_message)
252b5132
RH		 6793{
6794 char *tmp_name;
6795 struct elf_link_hash_entry *myh;
6796 struct elf32_arm_link_hash_table *hash_table;
6797
6798 /* We need a pointer to the elfarm specific hash table. */
6799 hash_table = elf32_arm_hash_table (link_info);
4dfe6ac6
NC		 6800 if (hash_table == NULL)
6801 return NULL;
252b5132 6802
21d799b5 6803 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen (name)
99059e56 6804 + strlen (ARM2THUMB_GLUE_ENTRY_NAME) + 1);
252b5132
RH		 6805
6806 BFD_ASSERT (tmp_name);
6807
6808 sprintf (tmp_name, ARM2THUMB_GLUE_ENTRY_NAME, name);
6809
6810 myh = elf_link_hash_lookup
b34976b6 6811 (&(hash_table)->root, tmp_name, FALSE, FALSE, TRUE);
252b5132 6812
b1657152
AM		 6813 if (myh == NULL
6814 && asprintf (error_message, _("unable to find ARM glue '%s' for '%s'"),
6815 tmp_name, name) == -1)
6816 *error_message = (char *) bfd_errmsg (bfd_error_system_call);
252b5132
RH		 6817
6818 free (tmp_name);
6819
6820 return myh;
6821}
6822
8f6277f5 6823/* ARM->Thumb glue (static images):
252b5132
RH		 6824
6825 .arm
6826 __func_from_arm:
6827 ldr r12, __func_addr
6828 bx r12
6829 __func_addr:
906e58ca 6830 .word func @ behave as if you saw a ARM_32 reloc.
252b5132 6831
26079076
PB		 6832 (v5t static images)
6833 .arm
6834 __func_from_arm:
6835 ldr pc, __func_addr
6836 __func_addr:
906e58ca 6837 .word func @ behave as if you saw a ARM_32 reloc.
26079076 6838
8f6277f5
PB		 6839 (relocatable images)
6840 .arm
6841 __func_from_arm:
6842 ldr r12, __func_offset
6843 add r12, r12, pc
6844 bx r12
6845 __func_offset:
8029a119 6846 .word func - . */
8f6277f5
PB		 6847
6848#define ARM2THUMB_STATIC_GLUE_SIZE 12
252b5132
RH		 6849static const insn32 a2t1_ldr_insn = 0xe59fc000;
6850static const insn32 a2t2_bx_r12_insn = 0xe12fff1c;
6851static const insn32 a2t3_func_addr_insn = 0x00000001;
6852
26079076
PB		 6853#define ARM2THUMB_V5_STATIC_GLUE_SIZE 8
6854static const insn32 a2t1v5_ldr_insn = 0xe51ff004;
6855static const insn32 a2t2v5_func_addr_insn = 0x00000001;
6856
8f6277f5
PB		 6857#define ARM2THUMB_PIC_GLUE_SIZE 16
6858static const insn32 a2t1p_ldr_insn = 0xe59fc004;
6859static const insn32 a2t2p_add_pc_insn = 0xe08cc00f;
6860static const insn32 a2t3p_bx_r12_insn = 0xe12fff1c;
6861
9b485d32 6862/* Thumb->ARM: Thumb->(non-interworking aware) ARM
252b5132 6863
8029a119
NC		 6864 .thumb .thumb
6865 .align 2 .align 2
6866 __func_from_thumb: __func_from_thumb:
6867 bx pc push {r6, lr}
6868 nop ldr r6, __func_addr
6869 .arm mov lr, pc
6870 b func bx r6
99059e56
RM		 6871 .arm
6872 ;; back_to_thumb
6873 ldmia r13! {r6, lr}
6874 bx lr
6875 __func_addr:
6876 .word func */
252b5132
RH		 6877
6878#define THUMB2ARM_GLUE_SIZE 8
6879static const insn16 t2a1_bx_pc_insn = 0x4778;
6880static const insn16 t2a2_noop_insn = 0x46c0;
6881static const insn32 t2a3_b_insn = 0xea000000;
6882
c7b8f16e 6883#define VFP11_ERRATUM_VENEER_SIZE 8
a504d23a
LA		 6884#define STM32L4XX_ERRATUM_LDM_VENEER_SIZE 16
6885#define STM32L4XX_ERRATUM_VLDM_VENEER_SIZE 24
c7b8f16e 6886
845b51d6
PB		 6887#define ARM_BX_VENEER_SIZE 12
6888static const insn32 armbx1_tst_insn = 0xe3100001;
6889static const insn32 armbx2_moveq_insn = 0x01a0f000;
6890static const insn32 armbx3_bx_insn = 0xe12fff10;
6891
7e392df6 6892#ifndef ELFARM_NABI_C_INCLUDED
8029a119
NC		 6893static void
6894arm_allocate_glue_section_space (bfd * abfd, bfd_size_type size, const char * name)
252b5132
RH		 6895{
6896 asection * s;
8029a119 6897 bfd_byte * contents;
252b5132 6898
8029a119 6899 if (size == 0)
3e6b1042
DJ		 6900 {
6901 /* Do not include empty glue sections in the output. */
6902 if (abfd != NULL)
6903 {
3d4d4302 6904 s = bfd_get_linker_section (abfd, name);
3e6b1042
DJ		 6905 if (s != NULL)
6906 s->flags |= SEC_EXCLUDE;
6907 }
6908 return;
6909 }
252b5132 6910
8029a119 6911 BFD_ASSERT (abfd != NULL);
252b5132 6912
3d4d4302 6913 s = bfd_get_linker_section (abfd, name);
8029a119 6914 BFD_ASSERT (s != NULL);
252b5132 6915
21d799b5 6916 contents = (bfd_byte *) bfd_alloc (abfd, size);
252b5132 6917
8029a119
NC		 6918 BFD_ASSERT (s->size == size);
6919 s->contents = contents;
6920}
906e58ca 6921
8029a119
NC		 6922bfd_boolean
6923bfd_elf32_arm_allocate_interworking_sections (struct bfd_link_info * info)
6924{
6925 struct elf32_arm_link_hash_table * globals;
906e58ca 6926
8029a119
NC		 6927 globals = elf32_arm_hash_table (info);
6928 BFD_ASSERT (globals != NULL);
906e58ca 6929
8029a119
NC		 6930 arm_allocate_glue_section_space (globals->bfd_of_glue_owner,
6931 globals->arm_glue_size,
6932 ARM2THUMB_GLUE_SECTION_NAME);
906e58ca 6933
8029a119
NC		 6934 arm_allocate_glue_section_space (globals->bfd_of_glue_owner,
6935 globals->thumb_glue_size,
6936 THUMB2ARM_GLUE_SECTION_NAME);
252b5132 6937
8029a119
NC		 6938 arm_allocate_glue_section_space (globals->bfd_of_glue_owner,
6939 globals->vfp11_erratum_glue_size,
6940 VFP11_ERRATUM_VENEER_SECTION_NAME);
845b51d6 6941
a504d23a
LA		 6942 arm_allocate_glue_section_space (globals->bfd_of_glue_owner,
6943 globals->stm32l4xx_erratum_glue_size,
6944 STM32L4XX_ERRATUM_VENEER_SECTION_NAME);
6945
8029a119
NC		 6946 arm_allocate_glue_section_space (globals->bfd_of_glue_owner,
6947 globals->bx_glue_size,
845b51d6
PB		 6948 ARM_BX_GLUE_SECTION_NAME);
6949
b34976b6 6950 return TRUE;
252b5132
RH		 6951}
6952
a4fd1a8e 6953/* Allocate space and symbols for calling a Thumb function from Arm mode.
906e58ca
NC		 6954 returns the symbol identifying the stub. */
6955
a4fd1a8e 6956static struct elf_link_hash_entry *
57e8b36a
NC		 6957record_arm_to_thumb_glue (struct bfd_link_info * link_info,
6958 struct elf_link_hash_entry * h)
252b5132
RH		 6959{
6960 const char * name = h->root.root.string;
63b0f745 6961 asection * s;
252b5132
RH		 6962 char * tmp_name;
6963 struct elf_link_hash_entry * myh;
14a793b2 6964 struct bfd_link_hash_entry * bh;
252b5132 6965 struct elf32_arm_link_hash_table * globals;
dc810e39 6966 bfd_vma val;
2f475487 6967 bfd_size_type size;
252b5132
RH		 6968
6969 globals = elf32_arm_hash_table (link_info);
252b5132
RH		 6970 BFD_ASSERT (globals != NULL);
6971 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
6972
3d4d4302 6973 s = bfd_get_linker_section
252b5132
RH		 6974 (globals->bfd_of_glue_owner, ARM2THUMB_GLUE_SECTION_NAME);
6975
252b5132
RH		 6976 BFD_ASSERT (s != NULL);
6977
21d799b5 6978 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen (name)
99059e56 6979 + strlen (ARM2THUMB_GLUE_ENTRY_NAME) + 1);
252b5132
RH		 6980
6981 BFD_ASSERT (tmp_name);
6982
6983 sprintf (tmp_name, ARM2THUMB_GLUE_ENTRY_NAME, name);
6984
6985 myh = elf_link_hash_lookup
b34976b6 6986 (&(globals)->root, tmp_name, FALSE, FALSE, TRUE);
252b5132
RH		 6987
6988 if (myh != NULL)
6989 {
9b485d32 6990 /* We've already seen this guy. */
252b5132 6991 free (tmp_name);
a4fd1a8e 6992 return myh;
252b5132
RH		 6993 }
6994
57e8b36a
NC		 6995 /* The only trick here is using hash_table->arm_glue_size as the value.
6996 Even though the section isn't allocated yet, this is where we will be
3dccd7b7
DJ		 6997 putting it. The +1 on the value marks that the stub has not been
6998 output yet - not that it is a Thumb function. */
14a793b2 6999 bh = NULL;
dc810e39
AM		 7000 val = globals->arm_glue_size + 1;
7001 _bfd_generic_link_add_one_symbol (link_info, globals->bfd_of_glue_owner,
7002 tmp_name, BSF_GLOBAL, s, val,
b34976b6 7003 NULL, TRUE, FALSE, &bh);
252b5132 7004
b7693d02
DJ		 7005 myh = (struct elf_link_hash_entry *) bh;
7006 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
7007 myh->forced_local = 1;
7008
252b5132
RH		 7009 free (tmp_name);
7010
0e1862bb
L		 7011 if (bfd_link_pic (link_info)
7012 || globals->root.is_relocatable_executable
27e55c4d 7013 || globals->pic_veneer)
2f475487 7014 size = ARM2THUMB_PIC_GLUE_SIZE;
26079076
PB		 7015 else if (globals->use_blx)
7016 size = ARM2THUMB_V5_STATIC_GLUE_SIZE;
8f6277f5 7017 else
2f475487
AM		 7018 size = ARM2THUMB_STATIC_GLUE_SIZE;
7019
7020 s->size += size;
7021 globals->arm_glue_size += size;
252b5132 7022
a4fd1a8e 7023 return myh;
252b5132
RH		 7024}
7025
845b51d6
PB		 7026/* Allocate space for ARMv4 BX veneers. */
7027
7028static void
7029record_arm_bx_glue (struct bfd_link_info * link_info, int reg)
7030{
7031 asection * s;
7032 struct elf32_arm_link_hash_table *globals;
7033 char *tmp_name;
7034 struct elf_link_hash_entry *myh;
7035 struct bfd_link_hash_entry *bh;
7036 bfd_vma val;
7037
7038 /* BX PC does not need a veneer. */
7039 if (reg == 15)
7040 return;
7041
7042 globals = elf32_arm_hash_table (link_info);
845b51d6
PB		 7043 BFD_ASSERT (globals != NULL);
7044 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
7045
7046 /* Check if this veneer has already been allocated. */
7047 if (globals->bx_glue_offset[reg])
7048 return;
7049
3d4d4302 7050 s = bfd_get_linker_section
845b51d6
PB		 7051 (globals->bfd_of_glue_owner, ARM_BX_GLUE_SECTION_NAME);
7052
7053 BFD_ASSERT (s != NULL);
7054
7055 /* Add symbol for veneer. */
21d799b5
NC		 7056 tmp_name = (char *)
7057 bfd_malloc ((bfd_size_type) strlen (ARM_BX_GLUE_ENTRY_NAME) + 1);
906e58ca 7058
845b51d6 7059 BFD_ASSERT (tmp_name);
906e58ca 7060
845b51d6 7061 sprintf (tmp_name, ARM_BX_GLUE_ENTRY_NAME, reg);
906e58ca 7062
845b51d6
PB		 7063 myh = elf_link_hash_lookup
7064 (&(globals)->root, tmp_name, FALSE, FALSE, FALSE);
906e58ca 7065
845b51d6 7066 BFD_ASSERT (myh == NULL);
906e58ca 7067
845b51d6
PB		 7068 bh = NULL;
7069 val = globals->bx_glue_size;
7070 _bfd_generic_link_add_one_symbol (link_info, globals->bfd_of_glue_owner,
99059e56
RM		 7071 tmp_name, BSF_FUNCTION | BSF_LOCAL, s, val,
7072 NULL, TRUE, FALSE, &bh);
845b51d6
PB		 7073
7074 myh = (struct elf_link_hash_entry *) bh;
7075 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
7076 myh->forced_local = 1;
7077
7078 s->size += ARM_BX_VENEER_SIZE;
7079 globals->bx_glue_offset[reg] = globals->bx_glue_size | 2;
7080 globals->bx_glue_size += ARM_BX_VENEER_SIZE;
7081}
7082
7083
c7b8f16e
JB		 7084/* Add an entry to the code/data map for section SEC. */
7085
7086static void
7087elf32_arm_section_map_add (asection *sec, char type, bfd_vma vma)
7088{
7089 struct _arm_elf_section_data *sec_data = elf32_arm_section_data (sec);
7090 unsigned int newidx;
906e58ca 7091
c7b8f16e
JB		 7092 if (sec_data->map == NULL)
7093 {
21d799b5 7094 sec_data->map = (elf32_arm_section_map *)
99059e56 7095 bfd_malloc (sizeof (elf32_arm_section_map));
c7b8f16e
JB		 7096 sec_data->mapcount = 0;
7097 sec_data->mapsize = 1;
7098 }
906e58ca 7099
c7b8f16e 7100 newidx = sec_data->mapcount++;
906e58ca 7101
c7b8f16e
JB		 7102 if (sec_data->mapcount > sec_data->mapsize)
7103 {
7104 sec_data->mapsize *= 2;
21d799b5 7105 sec_data->map = (elf32_arm_section_map *)
99059e56
RM		 7106 bfd_realloc_or_free (sec_data->map, sec_data->mapsize
7107 * sizeof (elf32_arm_section_map));
515ef31d
NC		 7108 }
7109
7110 if (sec_data->map)
7111 {
7112 sec_data->map[newidx].vma = vma;
7113 sec_data->map[newidx].type = type;
c7b8f16e 7114 }
c7b8f16e
JB		 7115}
7116
7117
7118/* Record information about a VFP11 denorm-erratum veneer. Only ARM-mode
7119 veneers are handled for now. */
7120
7121static bfd_vma
7122record_vfp11_erratum_veneer (struct bfd_link_info *link_info,
99059e56
RM		 7123 elf32_vfp11_erratum_list *branch,
7124 bfd *branch_bfd,
7125 asection *branch_sec,
7126 unsigned int offset)
c7b8f16e
JB		 7127{
7128 asection *s;
7129 struct elf32_arm_link_hash_table *hash_table;
7130 char *tmp_name;
7131 struct elf_link_hash_entry *myh;
7132 struct bfd_link_hash_entry *bh;
7133 bfd_vma val;
7134 struct _arm_elf_section_data *sec_data;
c7b8f16e 7135 elf32_vfp11_erratum_list *newerr;
906e58ca 7136
c7b8f16e 7137 hash_table = elf32_arm_hash_table (link_info);
c7b8f16e
JB		 7138 BFD_ASSERT (hash_table != NULL);
7139 BFD_ASSERT (hash_table->bfd_of_glue_owner != NULL);
906e58ca 7140
3d4d4302 7141 s = bfd_get_linker_section
c7b8f16e 7142 (hash_table->bfd_of_glue_owner, VFP11_ERRATUM_VENEER_SECTION_NAME);
906e58ca 7143
c7b8f16e 7144 sec_data = elf32_arm_section_data (s);
906e58ca 7145
c7b8f16e 7146 BFD_ASSERT (s != NULL);
906e58ca 7147
21d799b5 7148 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen
99059e56 7149 (VFP11_ERRATUM_VENEER_ENTRY_NAME) + 10);
906e58ca 7150
c7b8f16e 7151 BFD_ASSERT (tmp_name);
906e58ca 7152
c7b8f16e
JB		 7153 sprintf (tmp_name, VFP11_ERRATUM_VENEER_ENTRY_NAME,
7154 hash_table->num_vfp11_fixes);
906e58ca 7155
c7b8f16e
JB		 7156 myh = elf_link_hash_lookup
7157 (&(hash_table)->root, tmp_name, FALSE, FALSE, FALSE);
906e58ca 7158
c7b8f16e 7159 BFD_ASSERT (myh == NULL);
906e58ca 7160
c7b8f16e
JB		 7161 bh = NULL;
7162 val = hash_table->vfp11_erratum_glue_size;
7163 _bfd_generic_link_add_one_symbol (link_info, hash_table->bfd_of_glue_owner,
99059e56
RM		 7164 tmp_name, BSF_FUNCTION | BSF_LOCAL, s, val,
7165 NULL, TRUE, FALSE, &bh);
c7b8f16e
JB		 7166
7167 myh = (struct elf_link_hash_entry *) bh;
7168 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
7169 myh->forced_local = 1;
7170
7171 /* Link veneer back to calling location. */
c7e2358a 7172 sec_data->erratumcount += 1;
21d799b5
NC		 7173 newerr = (elf32_vfp11_erratum_list *)
7174 bfd_zmalloc (sizeof (elf32_vfp11_erratum_list));
906e58ca 7175
c7b8f16e
JB		 7176 newerr->type = VFP11_ERRATUM_ARM_VENEER;
7177 newerr->vma = -1;
7178 newerr->u.v.branch = branch;
7179 newerr->u.v.id = hash_table->num_vfp11_fixes;
7180 branch->u.b.veneer = newerr;
7181
7182 newerr->next = sec_data->erratumlist;
7183 sec_data->erratumlist = newerr;
7184
7185 /* A symbol for the return from the veneer. */
7186 sprintf (tmp_name, VFP11_ERRATUM_VENEER_ENTRY_NAME "_r",
7187 hash_table->num_vfp11_fixes);
7188
7189 myh = elf_link_hash_lookup
7190 (&(hash_table)->root, tmp_name, FALSE, FALSE, FALSE);
906e58ca 7191
c7b8f16e
JB		 7192 if (myh != NULL)
7193 abort ();
7194
7195 bh = NULL;
7196 val = offset + 4;
7197 _bfd_generic_link_add_one_symbol (link_info, branch_bfd, tmp_name, BSF_LOCAL,
7198 branch_sec, val, NULL, TRUE, FALSE, &bh);
906e58ca 7199
c7b8f16e
JB		 7200 myh = (struct elf_link_hash_entry *) bh;
7201 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
7202 myh->forced_local = 1;
7203
7204 free (tmp_name);
906e58ca 7205
c7b8f16e
JB		 7206 /* Generate a mapping symbol for the veneer section, and explicitly add an
7207 entry for that symbol to the code/data map for the section. */
7208 if (hash_table->vfp11_erratum_glue_size == 0)
7209 {
7210 bh = NULL;
7211 /* FIXME: Creates an ARM symbol. Thumb mode will need attention if it
99059e56 7212 ever requires this erratum fix. */
c7b8f16e
JB		 7213 _bfd_generic_link_add_one_symbol (link_info,
7214 hash_table->bfd_of_glue_owner, "$a",
7215 BSF_LOCAL, s, 0, NULL,
99059e56 7216 TRUE, FALSE, &bh);
c7b8f16e
JB		 7217
7218 myh = (struct elf_link_hash_entry *) bh;
7219 myh->type = ELF_ST_INFO (STB_LOCAL, STT_NOTYPE);
7220 myh->forced_local = 1;
906e58ca 7221
c7b8f16e 7222 /* The elf32_arm_init_maps function only cares about symbols from input
99059e56
RM		 7223 BFDs. We must make a note of this generated mapping symbol
7224 ourselves so that code byteswapping works properly in
7225 elf32_arm_write_section. */
c7b8f16e
JB		 7226 elf32_arm_section_map_add (s, 'a', 0);
7227 }
906e58ca 7228
c7b8f16e
JB		 7229 s->size += VFP11_ERRATUM_VENEER_SIZE;
7230 hash_table->vfp11_erratum_glue_size += VFP11_ERRATUM_VENEER_SIZE;
7231 hash_table->num_vfp11_fixes++;
906e58ca 7232
c7b8f16e
JB		 7233 /* The offset of the veneer. */
7234 return val;
7235}
7236
a504d23a
LA		 7237/* Record information about a STM32L4XX STM erratum veneer. Only THUMB-mode
7238 veneers need to be handled because used only in Cortex-M. */
7239
7240static bfd_vma
7241record_stm32l4xx_erratum_veneer (struct bfd_link_info *link_info,
7242 elf32_stm32l4xx_erratum_list *branch,
7243 bfd *branch_bfd,
7244 asection *branch_sec,
7245 unsigned int offset,
7246 bfd_size_type veneer_size)
7247{
7248 asection *s;
7249 struct elf32_arm_link_hash_table *hash_table;
7250 char *tmp_name;
7251 struct elf_link_hash_entry *myh;
7252 struct bfd_link_hash_entry *bh;
7253 bfd_vma val;
7254 struct _arm_elf_section_data *sec_data;
7255 elf32_stm32l4xx_erratum_list *newerr;
7256
7257 hash_table = elf32_arm_hash_table (link_info);
7258 BFD_ASSERT (hash_table != NULL);
7259 BFD_ASSERT (hash_table->bfd_of_glue_owner != NULL);
7260
7261 s = bfd_get_linker_section
7262 (hash_table->bfd_of_glue_owner, STM32L4XX_ERRATUM_VENEER_SECTION_NAME);
7263
7264 BFD_ASSERT (s != NULL);
7265
7266 sec_data = elf32_arm_section_data (s);
7267
7268 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen
7269 (STM32L4XX_ERRATUM_VENEER_ENTRY_NAME) + 10);
7270
7271 BFD_ASSERT (tmp_name);
7272
7273 sprintf (tmp_name, STM32L4XX_ERRATUM_VENEER_ENTRY_NAME,
7274 hash_table->num_stm32l4xx_fixes);
7275
7276 myh = elf_link_hash_lookup
7277 (&(hash_table)->root, tmp_name, FALSE, FALSE, FALSE);
7278
7279 BFD_ASSERT (myh == NULL);
7280
7281 bh = NULL;
7282 val = hash_table->stm32l4xx_erratum_glue_size;
7283 _bfd_generic_link_add_one_symbol (link_info, hash_table->bfd_of_glue_owner,
7284 tmp_name, BSF_FUNCTION | BSF_LOCAL, s, val,
7285 NULL, TRUE, FALSE, &bh);
7286
7287 myh = (struct elf_link_hash_entry *) bh;
7288 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
7289 myh->forced_local = 1;
7290
7291 /* Link veneer back to calling location. */
7292 sec_data->stm32l4xx_erratumcount += 1;
7293 newerr = (elf32_stm32l4xx_erratum_list *)
7294 bfd_zmalloc (sizeof (elf32_stm32l4xx_erratum_list));
7295
7296 newerr->type = STM32L4XX_ERRATUM_VENEER;
7297 newerr->vma = -1;
7298 newerr->u.v.branch = branch;
7299 newerr->u.v.id = hash_table->num_stm32l4xx_fixes;
7300 branch->u.b.veneer = newerr;
7301
7302 newerr->next = sec_data->stm32l4xx_erratumlist;
7303 sec_data->stm32l4xx_erratumlist = newerr;
7304
7305 /* A symbol for the return from the veneer. */
7306 sprintf (tmp_name, STM32L4XX_ERRATUM_VENEER_ENTRY_NAME "_r",
7307 hash_table->num_stm32l4xx_fixes);
7308
7309 myh = elf_link_hash_lookup
7310 (&(hash_table)->root, tmp_name, FALSE, FALSE, FALSE);
7311
7312 if (myh != NULL)
7313 abort ();
7314
7315 bh = NULL;
7316 val = offset + 4;
7317 _bfd_generic_link_add_one_symbol (link_info, branch_bfd, tmp_name, BSF_LOCAL,
7318 branch_sec, val, NULL, TRUE, FALSE, &bh);
7319
7320 myh = (struct elf_link_hash_entry *) bh;
7321 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
7322 myh->forced_local = 1;
7323
7324 free (tmp_name);
7325
7326 /* Generate a mapping symbol for the veneer section, and explicitly add an
7327 entry for that symbol to the code/data map for the section. */
7328 if (hash_table->stm32l4xx_erratum_glue_size == 0)
7329 {
7330 bh = NULL;
7331 /* Creates a THUMB symbol since there is no other choice. */
7332 _bfd_generic_link_add_one_symbol (link_info,
7333 hash_table->bfd_of_glue_owner, "$t",
7334 BSF_LOCAL, s, 0, NULL,
7335 TRUE, FALSE, &bh);
7336
7337 myh = (struct elf_link_hash_entry *) bh;
7338 myh->type = ELF_ST_INFO (STB_LOCAL, STT_NOTYPE);
7339 myh->forced_local = 1;
7340
7341 /* The elf32_arm_init_maps function only cares about symbols from input
7342 BFDs. We must make a note of this generated mapping symbol
7343 ourselves so that code byteswapping works properly in
7344 elf32_arm_write_section. */
7345 elf32_arm_section_map_add (s, 't', 0);
7346 }
7347
7348 s->size += veneer_size;
7349 hash_table->stm32l4xx_erratum_glue_size += veneer_size;
7350 hash_table->num_stm32l4xx_fixes++;
7351
7352 /* The offset of the veneer. */
7353 return val;
7354}
7355
8029a119 7356#define ARM_GLUE_SECTION_FLAGS \
3e6b1042
DJ		 7357 (SEC_ALLOC | SEC_LOAD | SEC_HAS_CONTENTS | SEC_IN_MEMORY | SEC_CODE \
7358 | SEC_READONLY | SEC_LINKER_CREATED)
8029a119
NC		 7359
7360/* Create a fake section for use by the ARM backend of the linker. */
7361
7362static bfd_boolean
7363arm_make_glue_section (bfd * abfd, const char * name)
7364{
7365 asection * sec;
7366
3d4d4302 7367 sec = bfd_get_linker_section (abfd, name);
8029a119
NC		 7368 if (sec != NULL)
7369 /* Already made. */
7370 return TRUE;
7371
3d4d4302 7372 sec = bfd_make_section_anyway_with_flags (abfd, name, ARM_GLUE_SECTION_FLAGS);
8029a119
NC		 7373
7374 if (sec == NULL
7375 || !bfd_set_section_alignment (abfd, sec, 2))
7376 return FALSE;
7377
7378 /* Set the gc mark to prevent the section from being removed by garbage
7379 collection, despite the fact that no relocs refer to this section. */
7380 sec->gc_mark = 1;
7381
7382 return TRUE;
7383}
7384
1db37fe6
YG		 7385/* Set size of .plt entries. This function is called from the
7386 linker scripts in ld/emultempl/{armelf}.em. */
7387
7388void
7389bfd_elf32_arm_use_long_plt (void)
7390{
7391 elf32_arm_use_long_plt_entry = TRUE;
7392}
7393
8afb0e02
NC		 7394/* Add the glue sections to ABFD. This function is called from the
7395 linker scripts in ld/emultempl/{armelf}.em. */
9b485d32 7396
b34976b6 7397bfd_boolean
57e8b36a
NC		 7398bfd_elf32_arm_add_glue_sections_to_bfd (bfd *abfd,
7399 struct bfd_link_info *info)
252b5132 7400{
a504d23a
LA		 7401 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (info);
7402 bfd_boolean dostm32l4xx = globals
7403 && globals->stm32l4xx_fix != BFD_ARM_STM32L4XX_FIX_NONE;
7404 bfd_boolean addglue;
7405
8afb0e02
NC		 7406 /* If we are only performing a partial
7407 link do not bother adding the glue. */
0e1862bb 7408 if (bfd_link_relocatable (info))
b34976b6 7409 return TRUE;
252b5132 7410
a504d23a 7411 addglue = arm_make_glue_section (abfd, ARM2THUMB_GLUE_SECTION_NAME)
8029a119
NC		 7412 && arm_make_glue_section (abfd, THUMB2ARM_GLUE_SECTION_NAME)
7413 && arm_make_glue_section (abfd, VFP11_ERRATUM_VENEER_SECTION_NAME)
7414 && arm_make_glue_section (abfd, ARM_BX_GLUE_SECTION_NAME);
a504d23a
LA		 7415
7416 if (!dostm32l4xx)
7417 return addglue;
7418
7419 return addglue
7420 && arm_make_glue_section (abfd, STM32L4XX_ERRATUM_VENEER_SECTION_NAME);
8afb0e02
NC		 7421}
7422
daa4adae
TP		 7423/* Mark output sections of veneers needing a dedicated one with SEC_KEEP. This
7424 ensures they are not marked for deletion by
7425 strip_excluded_output_sections () when veneers are going to be created
7426 later. Not doing so would trigger assert on empty section size in
7427 lang_size_sections_1 (). */
7428
7429void
7430bfd_elf32_arm_keep_private_stub_output_sections (struct bfd_link_info *info)
7431{
7432 enum elf32_arm_stub_type stub_type;
7433
7434 /* If we are only performing a partial
7435 link do not bother adding the glue. */
7436 if (bfd_link_relocatable (info))
7437 return;
7438
7439 for (stub_type = arm_stub_none + 1; stub_type < max_stub_type; stub_type++)
7440 {
7441 asection *out_sec;
7442 const char *out_sec_name;
7443
7444 if (!arm_dedicated_stub_output_section_required (stub_type))
7445 continue;
7446
7447 out_sec_name = arm_dedicated_stub_output_section_name (stub_type);
7448 out_sec = bfd_get_section_by_name (info->output_bfd, out_sec_name);
7449 if (out_sec != NULL)
7450 out_sec->flags |= SEC_KEEP;
7451 }
7452}
7453
8afb0e02
NC		 7454/* Select a BFD to be used to hold the sections used by the glue code.
7455 This function is called from the linker scripts in ld/emultempl/
8029a119 7456 {armelf/pe}.em. */
8afb0e02 7457
b34976b6 7458bfd_boolean
57e8b36a 7459bfd_elf32_arm_get_bfd_for_interworking (bfd *abfd, struct bfd_link_info *info)
8afb0e02
NC		 7460{
7461 struct elf32_arm_link_hash_table *globals;
7462
7463 /* If we are only performing a partial link
7464 do not bother getting a bfd to hold the glue. */
0e1862bb 7465 if (bfd_link_relocatable (info))
b34976b6 7466 return TRUE;
8afb0e02 7467
b7693d02
DJ		 7468 /* Make sure we don't attach the glue sections to a dynamic object. */
7469 BFD_ASSERT (!(abfd->flags & DYNAMIC));
7470
8afb0e02 7471 globals = elf32_arm_hash_table (info);
8afb0e02
NC		 7472 BFD_ASSERT (globals != NULL);
7473
7474 if (globals->bfd_of_glue_owner != NULL)
b34976b6 7475 return TRUE;
8afb0e02 7476
252b5132
RH		 7477 /* Save the bfd for later use. */
7478 globals->bfd_of_glue_owner = abfd;
cedb70c5 7479
b34976b6 7480 return TRUE;
252b5132
RH		 7481}
7482
906e58ca
NC		 7483static void
7484check_use_blx (struct elf32_arm_link_hash_table *globals)
39b41c9c 7485{
2de70689
MGD		 7486 int cpu_arch;
7487
b38cadfb 7488 cpu_arch = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC,
2de70689
MGD		 7489 Tag_CPU_arch);
7490
7491 if (globals->fix_arm1176)
7492 {
7493 if (cpu_arch == TAG_CPU_ARCH_V6T2 || cpu_arch > TAG_CPU_ARCH_V6K)
7494 globals->use_blx = 1;
7495 }
7496 else
7497 {
7498 if (cpu_arch > TAG_CPU_ARCH_V4T)
7499 globals->use_blx = 1;
7500 }
39b41c9c
PB		 7501}
7502
b34976b6 7503bfd_boolean
57e8b36a 7504bfd_elf32_arm_process_before_allocation (bfd *abfd,
d504ffc8 7505 struct bfd_link_info *link_info)
252b5132
RH		 7506{
7507 Elf_Internal_Shdr *symtab_hdr;
6cdc0ccc 7508 Elf_Internal_Rela *internal_relocs = NULL;
252b5132
RH		 7509 Elf_Internal_Rela *irel, *irelend;
7510 bfd_byte *contents = NULL;
252b5132
RH		 7511
7512 asection *sec;
7513 struct elf32_arm_link_hash_table *globals;
7514
7515 /* If we are only performing a partial link do not bother
7516 to construct any glue. */
0e1862bb 7517 if (bfd_link_relocatable (link_info))
b34976b6 7518 return TRUE;
252b5132 7519
39ce1a6a
NC		 7520 /* Here we have a bfd that is to be included on the link. We have a
7521 hook to do reloc rummaging, before section sizes are nailed down. */
252b5132 7522 globals = elf32_arm_hash_table (link_info);
252b5132 7523 BFD_ASSERT (globals != NULL);
39ce1a6a
NC		 7524
7525 check_use_blx (globals);
252b5132 7526
d504ffc8 7527 if (globals->byteswap_code && !bfd_big_endian (abfd))
e489d0ae 7528 {
d003868e
AM		 7529 _bfd_error_handler (_("%B: BE8 images only valid in big-endian mode."),
7530 abfd);
e489d0ae
PB		 7531 return FALSE;
7532 }
f21f3fe0 7533
39ce1a6a
NC		 7534 /* PR 5398: If we have not decided to include any loadable sections in
7535 the output then we will not have a glue owner bfd. This is OK, it
7536 just means that there is nothing else for us to do here. */
7537 if (globals->bfd_of_glue_owner == NULL)
7538 return TRUE;
7539
252b5132
RH		 7540 /* Rummage around all the relocs and map the glue vectors. */
7541 sec = abfd->sections;
7542
7543 if (sec == NULL)
b34976b6 7544 return TRUE;
252b5132
RH		 7545
7546 for (; sec != NULL; sec = sec->next)
7547 {
7548 if (sec->reloc_count == 0)
7549 continue;
7550
2f475487
AM		 7551 if ((sec->flags & SEC_EXCLUDE) != 0)
7552 continue;
7553
0ffa91dd 7554 symtab_hdr = & elf_symtab_hdr (abfd);
252b5132 7555
9b485d32 7556 /* Load the relocs. */
6cdc0ccc 7557 internal_relocs
906e58ca 7558 = _bfd_elf_link_read_relocs (abfd, sec, NULL, NULL, FALSE);
252b5132 7559
6cdc0ccc
AM		 7560 if (internal_relocs == NULL)
7561 goto error_return;
252b5132 7562
6cdc0ccc
AM		 7563 irelend = internal_relocs + sec->reloc_count;
7564 for (irel = internal_relocs; irel < irelend; irel++)
252b5132
RH		 7565 {
7566 long r_type;
7567 unsigned long r_index;
252b5132
RH		 7568
7569 struct elf_link_hash_entry *h;
7570
7571 r_type = ELF32_R_TYPE (irel->r_info);
7572 r_index = ELF32_R_SYM (irel->r_info);
7573
9b485d32 7574 /* These are the only relocation types we care about. */
ba96a88f 7575 if ( r_type != R_ARM_PC24
845b51d6 7576 && (r_type != R_ARM_V4BX || globals->fix_v4bx < 2))
252b5132
RH		 7577 continue;
7578
7579 /* Get the section contents if we haven't done so already. */
7580 if (contents == NULL)
7581 {
7582 /* Get cached copy if it exists. */
7583 if (elf_section_data (sec)->this_hdr.contents != NULL)
7584 contents = elf_section_data (sec)->this_hdr.contents;
7585 else
7586 {
7587 /* Go get them off disk. */
57e8b36a 7588 if (! bfd_malloc_and_get_section (abfd, sec, &contents))
252b5132
RH		 7589 goto error_return;
7590 }
7591 }
7592
845b51d6
PB		 7593 if (r_type == R_ARM_V4BX)
7594 {
7595 int reg;
7596
7597 reg = bfd_get_32 (abfd, contents + irel->r_offset) & 0xf;
7598 record_arm_bx_glue (link_info, reg);
7599 continue;
7600 }
7601
a7c10850 7602 /* If the relocation is not against a symbol it cannot concern us. */
252b5132
RH		 7603 h = NULL;
7604
9b485d32 7605 /* We don't care about local symbols. */
252b5132
RH		 7606 if (r_index < symtab_hdr->sh_info)
7607 continue;
7608
9b485d32 7609 /* This is an external symbol. */
252b5132
RH		 7610 r_index -= symtab_hdr->sh_info;
7611 h = (struct elf_link_hash_entry *)
7612 elf_sym_hashes (abfd)[r_index];
7613
7614 /* If the relocation is against a static symbol it must be within
7615 the current section and so cannot be a cross ARM/Thumb relocation. */
7616 if (h == NULL)
7617 continue;
7618
d504ffc8
DJ		 7619 /* If the call will go through a PLT entry then we do not need
7620 glue. */
362d30a1 7621 if (globals->root.splt != NULL && h->plt.offset != (bfd_vma) -1)
b7693d02
DJ		 7622 continue;
7623
252b5132
RH		 7624 switch (r_type)
7625 {
7626 case R_ARM_PC24:
7627 /* This one is a call from arm code. We need to look up
99059e56
RM		 7628 the target of the call. If it is a thumb target, we
7629 insert glue. */
39d911fc
TP		 7630 if (ARM_GET_SYM_BRANCH_TYPE (h->target_internal)
7631 == ST_BRANCH_TO_THUMB)
252b5132
RH		 7632 record_arm_to_thumb_glue (link_info, h);
7633 break;
7634
252b5132 7635 default:
c6596c5e 7636 abort ();
252b5132
RH		 7637 }
7638 }
6cdc0ccc
AM		 7639
7640 if (contents != NULL
7641 && elf_section_data (sec)->this_hdr.contents != contents)
7642 free (contents);
7643 contents = NULL;
7644
7645 if (internal_relocs != NULL
7646 && elf_section_data (sec)->relocs != internal_relocs)
7647 free (internal_relocs);
7648 internal_relocs = NULL;
252b5132
RH		 7649 }
7650
b34976b6 7651 return TRUE;
9a5aca8c 7652
252b5132 7653error_return:
6cdc0ccc
AM		 7654 if (contents != NULL
7655 && elf_section_data (sec)->this_hdr.contents != contents)
7656 free (contents);
7657 if (internal_relocs != NULL
7658 && elf_section_data (sec)->relocs != internal_relocs)
7659 free (internal_relocs);
9a5aca8c 7660
b34976b6 7661 return FALSE;
252b5132 7662}
7e392df6 7663#endif
252b5132 7664
eb043451 7665
c7b8f16e
JB		 7666/* Initialise maps of ARM/Thumb/data for input BFDs. */
7667
7668void
7669bfd_elf32_arm_init_maps (bfd *abfd)
7670{
7671 Elf_Internal_Sym *isymbuf;
7672 Elf_Internal_Shdr *hdr;
7673 unsigned int i, localsyms;
7674
af1f4419
NC		 7675 /* PR 7093: Make sure that we are dealing with an arm elf binary. */
7676 if (! is_arm_elf (abfd))
7677 return;
7678
c7b8f16e
JB		 7679 if ((abfd->flags & DYNAMIC) != 0)
7680 return;
7681
0ffa91dd 7682 hdr = & elf_symtab_hdr (abfd);
c7b8f16e
JB		 7683 localsyms = hdr->sh_info;
7684
7685 /* Obtain a buffer full of symbols for this BFD. The hdr->sh_info field
7686 should contain the number of local symbols, which should come before any
7687 global symbols. Mapping symbols are always local. */
7688 isymbuf = bfd_elf_get_elf_syms (abfd, hdr, localsyms, 0, NULL, NULL,
7689 NULL);
7690
7691 /* No internal symbols read? Skip this BFD. */
7692 if (isymbuf == NULL)
7693 return;
7694
7695 for (i = 0; i < localsyms; i++)
7696 {
7697 Elf_Internal_Sym *isym = &isymbuf[i];
7698 asection *sec = bfd_section_from_elf_index (abfd, isym->st_shndx);
7699 const char *name;
906e58ca 7700
c7b8f16e 7701 if (sec != NULL
99059e56
RM		 7702 && ELF_ST_BIND (isym->st_info) == STB_LOCAL)
7703 {
7704 name = bfd_elf_string_from_elf_section (abfd,
7705 hdr->sh_link, isym->st_name);
906e58ca 7706
99059e56 7707 if (bfd_is_arm_special_symbol_name (name,
c7b8f16e 7708 BFD_ARM_SPECIAL_SYM_TYPE_MAP))
99059e56
RM		 7709 elf32_arm_section_map_add (sec, name[1], isym->st_value);
7710 }
c7b8f16e
JB		 7711 }
7712}
7713
7714
48229727
JB		 7715/* Auto-select enabling of Cortex-A8 erratum fix if the user didn't explicitly
7716 say what they wanted. */
7717
7718void
7719bfd_elf32_arm_set_cortex_a8_fix (bfd *obfd, struct bfd_link_info *link_info)
7720{
7721 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (link_info);
7722 obj_attribute *out_attr = elf_known_obj_attributes_proc (obfd);
7723
4dfe6ac6
NC		 7724 if (globals == NULL)
7725 return;
7726
48229727
JB		 7727 if (globals->fix_cortex_a8 == -1)
7728 {
7729 /* Turn on Cortex-A8 erratum workaround for ARMv7-A. */
7730 if (out_attr[Tag_CPU_arch].i == TAG_CPU_ARCH_V7
7731 && (out_attr[Tag_CPU_arch_profile].i == 'A'
7732 || out_attr[Tag_CPU_arch_profile].i == 0))
7733 globals->fix_cortex_a8 = 1;
7734 else
7735 globals->fix_cortex_a8 = 0;
7736 }
7737}
7738
7739
c7b8f16e
JB		 7740void
7741bfd_elf32_arm_set_vfp11_fix (bfd *obfd, struct bfd_link_info *link_info)
7742{
7743 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (link_info);
104d59d1 7744 obj_attribute *out_attr = elf_known_obj_attributes_proc (obfd);
906e58ca 7745
4dfe6ac6
NC		 7746 if (globals == NULL)
7747 return;
c7b8f16e
JB		 7748 /* We assume that ARMv7+ does not need the VFP11 denorm erratum fix. */
7749 if (out_attr[Tag_CPU_arch].i >= TAG_CPU_ARCH_V7)
7750 {
7751 switch (globals->vfp11_fix)
99059e56
RM		 7752 {
7753 case BFD_ARM_VFP11_FIX_DEFAULT:
7754 case BFD_ARM_VFP11_FIX_NONE:
7755 globals->vfp11_fix = BFD_ARM_VFP11_FIX_NONE;
7756 break;
7757
7758 default:
7759 /* Give a warning, but do as the user requests anyway. */
4eca0228 7760 _bfd_error_handler (_("%B: warning: selected VFP11 erratum "
99059e56
RM		 7761 "workaround is not necessary for target architecture"), obfd);
7762 }
c7b8f16e
JB		 7763 }
7764 else if (globals->vfp11_fix == BFD_ARM_VFP11_FIX_DEFAULT)
7765 /* For earlier architectures, we might need the workaround, but do not
7766 enable it by default. If users is running with broken hardware, they
7767 must enable the erratum fix explicitly. */
7768 globals->vfp11_fix = BFD_ARM_VFP11_FIX_NONE;
7769}
7770
a504d23a
LA		 7771void
7772bfd_elf32_arm_set_stm32l4xx_fix (bfd *obfd, struct bfd_link_info *link_info)
7773{
7774 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (link_info);
7775 obj_attribute *out_attr = elf_known_obj_attributes_proc (obfd);
7776
7777 if (globals == NULL)
7778 return;
7779
7780 /* We assume only Cortex-M4 may require the fix. */
7781 if (out_attr[Tag_CPU_arch].i != TAG_CPU_ARCH_V7E_M
7782 || out_attr[Tag_CPU_arch_profile].i != 'M')
7783 {
7784 if (globals->stm32l4xx_fix != BFD_ARM_STM32L4XX_FIX_NONE)
7785 /* Give a warning, but do as the user requests anyway. */
4eca0228 7786 _bfd_error_handler
a504d23a
LA		 7787 (_("%B: warning: selected STM32L4XX erratum "
7788 "workaround is not necessary for target architecture"), obfd);
7789 }
7790}
c7b8f16e 7791
906e58ca
NC		 7792enum bfd_arm_vfp11_pipe
7793{
c7b8f16e
JB		 7794 VFP11_FMAC,
7795 VFP11_LS,
7796 VFP11_DS,
7797 VFP11_BAD
7798};
7799
7800/* Return a VFP register number. This is encoded as RX:X for single-precision
7801 registers, or X:RX for double-precision registers, where RX is the group of
7802 four bits in the instruction encoding and X is the single extension bit.
7803 RX and X fields are specified using their lowest (starting) bit. The return
7804 value is:
7805
7806 0...31: single-precision registers s0...s31
7807 32...63: double-precision registers d0...d31.
906e58ca 7808
c7b8f16e
JB		 7809 Although X should be zero for VFP11 (encoding d0...d15 only), we might
7810 encounter VFP3 instructions, so we allow the full range for DP registers. */
906e58ca 7811
c7b8f16e
JB		 7812static unsigned int
7813bfd_arm_vfp11_regno (unsigned int insn, bfd_boolean is_double, unsigned int rx,
99059e56 7814 unsigned int x)
c7b8f16e
JB		 7815{
7816 if (is_double)
7817 return (((insn >> rx) & 0xf) | (((insn >> x) & 1) << 4)) + 32;
7818 else
7819 return (((insn >> rx) & 0xf) << 1) | ((insn >> x) & 1);
7820}
7821
7822/* Set bits in *WMASK according to a register number REG as encoded by
7823 bfd_arm_vfp11_regno(). Ignore d16-d31. */
7824
7825static void
7826bfd_arm_vfp11_write_mask (unsigned int *wmask, unsigned int reg)
7827{
7828 if (reg < 32)
7829 *wmask |= 1 << reg;
7830 else if (reg < 48)
7831 *wmask |= 3 << ((reg - 32) * 2);
7832}
7833
7834/* Return TRUE if WMASK overwrites anything in REGS. */
7835
7836static bfd_boolean
7837bfd_arm_vfp11_antidependency (unsigned int wmask, int *regs, int numregs)
7838{
7839 int i;
906e58ca 7840
c7b8f16e
JB		 7841 for (i = 0; i < numregs; i++)
7842 {
7843 unsigned int reg = regs[i];
7844
7845 if (reg < 32 && (wmask & (1 << reg)) != 0)
99059e56 7846 return TRUE;
906e58ca 7847
c7b8f16e
JB		 7848 reg -= 32;
7849
7850 if (reg >= 16)
99059e56 7851 continue;
906e58ca 7852
c7b8f16e 7853 if ((wmask & (3 << (reg * 2))) != 0)
99059e56 7854 return TRUE;
c7b8f16e 7855 }
906e58ca 7856
c7b8f16e
JB		 7857 return FALSE;
7858}
7859
7860/* In this function, we're interested in two things: finding input registers
7861 for VFP data-processing instructions, and finding the set of registers which
7862 arbitrary VFP instructions may write to. We use a 32-bit unsigned int to
7863 hold the written set, so FLDM etc. are easy to deal with (we're only
7864 interested in 32 SP registers or 16 dp registers, due to the VFP version
7865 implemented by the chip in question). DP registers are marked by setting
7866 both SP registers in the write mask). */
7867
7868static enum bfd_arm_vfp11_pipe
7869bfd_arm_vfp11_insn_decode (unsigned int insn, unsigned int *destmask, int *regs,
99059e56 7870 int *numregs)
c7b8f16e 7871{
91d6fa6a 7872 enum bfd_arm_vfp11_pipe vpipe = VFP11_BAD;
c7b8f16e
JB		 7873 bfd_boolean is_double = ((insn & 0xf00) == 0xb00) ? 1 : 0;
7874
7875 if ((insn & 0x0f000e10) == 0x0e000a00) /* A data-processing insn. */
7876 {
7877 unsigned int pqrs;
7878 unsigned int fd = bfd_arm_vfp11_regno (insn, is_double, 12, 22);
7879 unsigned int fm = bfd_arm_vfp11_regno (insn, is_double, 0, 5);
7880
7881 pqrs = ((insn & 0x00800000) >> 20)
99059e56
RM		 7882 | ((insn & 0x00300000) >> 19)
7883 | ((insn & 0x00000040) >> 6);
c7b8f16e
JB		 7884
7885 switch (pqrs)
99059e56
RM		 7886 {
7887 case 0: /* fmac[sd]. */
7888 case 1: /* fnmac[sd]. */
7889 case 2: /* fmsc[sd]. */
7890 case 3: /* fnmsc[sd]. */
7891 vpipe = VFP11_FMAC;
7892 bfd_arm_vfp11_write_mask (destmask, fd);
7893 regs[0] = fd;
7894 regs[1] = bfd_arm_vfp11_regno (insn, is_double, 16, 7); /* Fn. */
7895 regs[2] = fm;
7896 *numregs = 3;
7897 break;
7898
7899 case 4: /* fmul[sd]. */
7900 case 5: /* fnmul[sd]. */
7901 case 6: /* fadd[sd]. */
7902 case 7: /* fsub[sd]. */
7903 vpipe = VFP11_FMAC;
7904 goto vfp_binop;
7905
7906 case 8: /* fdiv[sd]. */
7907 vpipe = VFP11_DS;
7908 vfp_binop:
7909 bfd_arm_vfp11_write_mask (destmask, fd);
7910 regs[0] = bfd_arm_vfp11_regno (insn, is_double, 16, 7); /* Fn. */
7911 regs[1] = fm;
7912 *numregs = 2;
7913 break;
7914
7915 case 15: /* extended opcode. */
7916 {
7917 unsigned int extn = ((insn >> 15) & 0x1e)
7918 | ((insn >> 7) & 1);
7919
7920 switch (extn)
7921 {
7922 case 0: /* fcpy[sd]. */
7923 case 1: /* fabs[sd]. */
7924 case 2: /* fneg[sd]. */
7925 case 8: /* fcmp[sd]. */
7926 case 9: /* fcmpe[sd]. */
7927 case 10: /* fcmpz[sd]. */
7928 case 11: /* fcmpez[sd]. */
7929 case 16: /* fuito[sd]. */
7930 case 17: /* fsito[sd]. */
7931 case 24: /* ftoui[sd]. */
7932 case 25: /* ftouiz[sd]. */
7933 case 26: /* ftosi[sd]. */
7934 case 27: /* ftosiz[sd]. */
7935 /* These instructions will not bounce due to underflow. */
7936 *numregs = 0;
7937 vpipe = VFP11_FMAC;
7938 break;
7939
7940 case 3: /* fsqrt[sd]. */
7941 /* fsqrt cannot underflow, but it can (perhaps) overwrite
7942 registers to cause the erratum in previous instructions. */
7943 bfd_arm_vfp11_write_mask (destmask, fd);
7944 vpipe = VFP11_DS;
7945 break;
7946
7947 case 15: /* fcvt{ds,sd}. */
7948 {
7949 int rnum = 0;
7950
7951 bfd_arm_vfp11_write_mask (destmask, fd);
c7b8f16e
JB		 7952
7953 /* Only FCVTSD can underflow. */
99059e56
RM		 7954 if ((insn & 0x100) != 0)
7955 regs[rnum++] = fm;
c7b8f16e 7956
99059e56 7957 *numregs = rnum;
c7b8f16e 7958
99059e56
RM		 7959 vpipe = VFP11_FMAC;
7960 }
7961 break;
c7b8f16e 7962
99059e56
RM		 7963 default:
7964 return VFP11_BAD;
7965 }
7966 }
7967 break;
c7b8f16e 7968
99059e56
RM		 7969 default:
7970 return VFP11_BAD;
7971 }
c7b8f16e
JB		 7972 }
7973 /* Two-register transfer. */
7974 else if ((insn & 0x0fe00ed0) == 0x0c400a10)
7975 {
7976 unsigned int fm = bfd_arm_vfp11_regno (insn, is_double, 0, 5);
906e58ca 7977
c7b8f16e
JB		 7978 if ((insn & 0x100000) == 0)
7979 {
99059e56
RM		 7980 if (is_double)
7981 bfd_arm_vfp11_write_mask (destmask, fm);
7982 else
7983 {
7984 bfd_arm_vfp11_write_mask (destmask, fm);
7985 bfd_arm_vfp11_write_mask (destmask, fm + 1);
7986 }
c7b8f16e
JB		 7987 }
7988
91d6fa6a 7989 vpipe = VFP11_LS;
c7b8f16e
JB		 7990 }
7991 else if ((insn & 0x0e100e00) == 0x0c100a00) /* A load insn. */
7992 {
7993 int fd = bfd_arm_vfp11_regno (insn, is_double, 12, 22);
7994 unsigned int puw = ((insn >> 21) & 0x1) | (((insn >> 23) & 3) << 1);
906e58ca 7995
c7b8f16e 7996 switch (puw)
99059e56
RM		 7997 {
7998 case 0: /* Two-reg transfer. We should catch these above. */
7999 abort ();
906e58ca 8000
99059e56
RM		 8001 case 2: /* fldm[sdx]. */
8002 case 3:
8003 case 5:
8004 {
8005 unsigned int i, offset = insn & 0xff;
c7b8f16e 8006
99059e56
RM		 8007 if (is_double)
8008 offset >>= 1;
c7b8f16e 8009
99059e56
RM		 8010 for (i = fd; i < fd + offset; i++)
8011 bfd_arm_vfp11_write_mask (destmask, i);
8012 }
8013 break;
906e58ca 8014
99059e56
RM		 8015 case 4: /* fld[sd]. */
8016 case 6:
8017 bfd_arm_vfp11_write_mask (destmask, fd);
8018 break;
906e58ca 8019
99059e56
RM		 8020 default:
8021 return VFP11_BAD;
8022 }
c7b8f16e 8023
91d6fa6a 8024 vpipe = VFP11_LS;
c7b8f16e
JB		 8025 }
8026 /* Single-register transfer. Note L==0. */
8027 else if ((insn & 0x0f100e10) == 0x0e000a10)
8028 {
8029 unsigned int opcode = (insn >> 21) & 7;
8030 unsigned int fn = bfd_arm_vfp11_regno (insn, is_double, 16, 7);
8031
8032 switch (opcode)
99059e56
RM		 8033 {
8034 case 0: /* fmsr/fmdlr. */
8035 case 1: /* fmdhr. */
8036 /* Mark fmdhr and fmdlr as writing to the whole of the DP
8037 destination register. I don't know if this is exactly right,
8038 but it is the conservative choice. */
8039 bfd_arm_vfp11_write_mask (destmask, fn);
8040 break;
8041
8042 case 7: /* fmxr. */
8043 break;
8044 }
c7b8f16e 8045
91d6fa6a 8046 vpipe = VFP11_LS;
c7b8f16e
JB		 8047 }
8048
91d6fa6a 8049 return vpipe;
c7b8f16e
JB		 8050}
8051
8052
8053static int elf32_arm_compare_mapping (const void * a, const void * b);
8054
8055
8056/* Look for potentially-troublesome code sequences which might trigger the
8057 VFP11 denormal/antidependency erratum. See, e.g., the ARM1136 errata sheet
8058 (available from ARM) for details of the erratum. A short version is
8059 described in ld.texinfo. */
8060
8061bfd_boolean
8062bfd_elf32_arm_vfp11_erratum_scan (bfd *abfd, struct bfd_link_info *link_info)
8063{
8064 asection *sec;
8065 bfd_byte *contents = NULL;
8066 int state = 0;
8067 int regs[3], numregs = 0;
8068 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (link_info);
8069 int use_vector = (globals->vfp11_fix == BFD_ARM_VFP11_FIX_VECTOR);
906e58ca 8070
4dfe6ac6
NC		 8071 if (globals == NULL)
8072 return FALSE;
8073
c7b8f16e
JB		 8074 /* We use a simple FSM to match troublesome VFP11 instruction sequences.
8075 The states transition as follows:
906e58ca 8076
c7b8f16e 8077 0 -> 1 (vector) or 0 -> 2 (scalar)
99059e56
RM		 8078 A VFP FMAC-pipeline instruction has been seen. Fill
8079 regs[0]..regs[numregs-1] with its input operands. Remember this
8080 instruction in 'first_fmac'.
c7b8f16e
JB		 8081
8082 1 -> 2
99059e56
RM		 8083 Any instruction, except for a VFP instruction which overwrites
8084 regs[*].
906e58ca 8085
c7b8f16e
JB		 8086 1 -> 3 [ -> 0 ] or
8087 2 -> 3 [ -> 0 ]
99059e56
RM		 8088 A VFP instruction has been seen which overwrites any of regs[*].
8089 We must make a veneer! Reset state to 0 before examining next
8090 instruction.
906e58ca 8091
c7b8f16e 8092 2 -> 0
99059e56
RM		 8093 If we fail to match anything in state 2, reset to state 0 and reset
8094 the instruction pointer to the instruction after 'first_fmac'.
c7b8f16e
JB		 8095
8096 If the VFP11 vector mode is in use, there must be at least two unrelated
8097 instructions between anti-dependent VFP11 instructions to properly avoid
906e58ca 8098 triggering the erratum, hence the use of the extra state 1. */
c7b8f16e
JB		 8099
8100 /* If we are only performing a partial link do not bother
8101 to construct any glue. */
0e1862bb 8102 if (bfd_link_relocatable (link_info))
c7b8f16e
JB		 8103 return TRUE;
8104
0ffa91dd
NC		 8105 /* Skip if this bfd does not correspond to an ELF image. */
8106 if (! is_arm_elf (abfd))
8107 return TRUE;
906e58ca 8108
c7b8f16e
JB		 8109 /* We should have chosen a fix type by the time we get here. */
8110 BFD_ASSERT (globals->vfp11_fix != BFD_ARM_VFP11_FIX_DEFAULT);
8111
8112 if (globals->vfp11_fix == BFD_ARM_VFP11_FIX_NONE)
8113 return TRUE;
2e6030b9 8114
33a7ffc2
JM		 8115 /* Skip this BFD if it corresponds to an executable or dynamic object. */
8116 if ((abfd->flags & (EXEC_P | DYNAMIC)) != 0)
8117 return TRUE;
8118
c7b8f16e
JB		 8119 for (sec = abfd->sections; sec != NULL; sec = sec->next)
8120 {
8121 unsigned int i, span, first_fmac = 0, veneer_of_insn = 0;
8122 struct _arm_elf_section_data *sec_data;
8123
8124 /* If we don't have executable progbits, we're not interested in this
99059e56 8125 section. Also skip if section is to be excluded. */
c7b8f16e 8126 if (elf_section_type (sec) != SHT_PROGBITS
99059e56
RM		 8127 || (elf_section_flags (sec) & SHF_EXECINSTR) == 0
8128 || (sec->flags & SEC_EXCLUDE) != 0
dbaa2011 8129 || sec->sec_info_type == SEC_INFO_TYPE_JUST_SYMS
33a7ffc2 8130 || sec->output_section == bfd_abs_section_ptr
99059e56
RM		 8131 || strcmp (sec->name, VFP11_ERRATUM_VENEER_SECTION_NAME) == 0)
8132 continue;
c7b8f16e
JB		 8133
8134 sec_data = elf32_arm_section_data (sec);
906e58ca 8135
c7b8f16e 8136 if (sec_data->mapcount == 0)
99059e56 8137 continue;
906e58ca 8138
c7b8f16e
JB		 8139 if (elf_section_data (sec)->this_hdr.contents != NULL)
8140 contents = elf_section_data (sec)->this_hdr.contents;
8141 else if (! bfd_malloc_and_get_section (abfd, sec, &contents))
8142 goto error_return;
8143
8144 qsort (sec_data->map, sec_data->mapcount, sizeof (elf32_arm_section_map),
8145 elf32_arm_compare_mapping);
8146
8147 for (span = 0; span < sec_data->mapcount; span++)
99059e56
RM		 8148 {
8149 unsigned int span_start = sec_data->map[span].vma;
8150 unsigned int span_end = (span == sec_data->mapcount - 1)
c7b8f16e 8151 ? sec->size : sec_data->map[span + 1].vma;
99059e56
RM		 8152 char span_type = sec_data->map[span].type;
8153
8154 /* FIXME: Only ARM mode is supported at present. We may need to
8155 support Thumb-2 mode also at some point. */
8156 if (span_type != 'a')
8157 continue;
8158
8159 for (i = span_start; i < span_end;)
8160 {
8161 unsigned int next_i = i + 4;
8162 unsigned int insn = bfd_big_endian (abfd)
8163 ? (contents[i] << 24)
8164 | (contents[i + 1] << 16)
8165 | (contents[i + 2] << 8)
8166 | contents[i + 3]
8167 : (contents[i + 3] << 24)
8168 | (contents[i + 2] << 16)
8169 | (contents[i + 1] << 8)
8170 | contents[i];
8171 unsigned int writemask = 0;
8172 enum bfd_arm_vfp11_pipe vpipe;
8173
8174 switch (state)
8175 {
8176 case 0:
8177 vpipe = bfd_arm_vfp11_insn_decode (insn, &writemask, regs,
8178 &numregs);
8179 /* I'm assuming the VFP11 erratum can trigger with denorm
8180 operands on either the FMAC or the DS pipeline. This might
8181 lead to slightly overenthusiastic veneer insertion. */
8182 if (vpipe == VFP11_FMAC || vpipe == VFP11_DS)
8183 {
8184 state = use_vector ? 1 : 2;
8185 first_fmac = i;
8186 veneer_of_insn = insn;
8187 }
8188 break;
8189
8190 case 1:
8191 {
8192 int other_regs[3], other_numregs;
8193 vpipe = bfd_arm_vfp11_insn_decode (insn, &writemask,
c7b8f16e 8194 other_regs,
99059e56
RM		 8195 &other_numregs);
8196 if (vpipe != VFP11_BAD
8197 && bfd_arm_vfp11_antidependency (writemask, regs,
c7b8f16e 8198 numregs))
99059e56
RM		 8199 state = 3;
8200 else
8201 state = 2;
8202 }
8203 break;
8204
8205 case 2:
8206 {
8207 int other_regs[3], other_numregs;
8208 vpipe = bfd_arm_vfp11_insn_decode (insn, &writemask,
c7b8f16e 8209 other_regs,
99059e56
RM		 8210 &other_numregs);
8211 if (vpipe != VFP11_BAD
8212 && bfd_arm_vfp11_antidependency (writemask, regs,
c7b8f16e 8213 numregs))
99059e56
RM		 8214 state = 3;
8215 else
8216 {
8217 state = 0;
8218 next_i = first_fmac + 4;
8219 }
8220 }
8221 break;
8222
8223 case 3:
8224 abort (); /* Should be unreachable. */
8225 }
8226
8227 if (state == 3)
8228 {
8229 elf32_vfp11_erratum_list *newerr =(elf32_vfp11_erratum_list *)
8230 bfd_zmalloc (sizeof (elf32_vfp11_erratum_list));
8231
8232 elf32_arm_section_data (sec)->erratumcount += 1;
8233
8234 newerr->u.b.vfp_insn = veneer_of_insn;
8235
8236 switch (span_type)
8237 {
8238 case 'a':
8239 newerr->type = VFP11_ERRATUM_BRANCH_TO_ARM_VENEER;
8240 break;
8241
8242 default:
8243 abort ();
8244 }
8245
8246 record_vfp11_erratum_veneer (link_info, newerr, abfd, sec,
c7b8f16e
JB		 8247 first_fmac);
8248
99059e56 8249 newerr->vma = -1;
c7b8f16e 8250
99059e56
RM		 8251 newerr->next = sec_data->erratumlist;
8252 sec_data->erratumlist = newerr;
c7b8f16e 8253
99059e56
RM		 8254 state = 0;
8255 }
c7b8f16e 8256
99059e56
RM		 8257 i = next_i;
8258 }
8259 }
906e58ca 8260
c7b8f16e 8261 if (contents != NULL
99059e56
RM		 8262 && elf_section_data (sec)->this_hdr.contents != contents)
8263 free (contents);
c7b8f16e
JB		 8264 contents = NULL;
8265 }
8266
8267 return TRUE;
8268
8269error_return:
8270 if (contents != NULL
8271 && elf_section_data (sec)->this_hdr.contents != contents)
8272 free (contents);
906e58ca 8273
c7b8f16e
JB		 8274 return FALSE;
8275}
8276
8277/* Find virtual-memory addresses for VFP11 erratum veneers and return locations
8278 after sections have been laid out, using specially-named symbols. */
8279
8280void
8281bfd_elf32_arm_vfp11_fix_veneer_locations (bfd *abfd,
8282 struct bfd_link_info *link_info)
8283{
8284 asection *sec;
8285 struct elf32_arm_link_hash_table *globals;
8286 char *tmp_name;
906e58ca 8287
0e1862bb 8288 if (bfd_link_relocatable (link_info))
c7b8f16e 8289 return;
2e6030b9
MS		 8290
8291 /* Skip if this bfd does not correspond to an ELF image. */
0ffa91dd 8292 if (! is_arm_elf (abfd))
2e6030b9
MS		 8293 return;
8294
c7b8f16e 8295 globals = elf32_arm_hash_table (link_info);
4dfe6ac6
NC		 8296 if (globals == NULL)
8297 return;
906e58ca 8298
21d799b5 8299 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen
99059e56 8300 (VFP11_ERRATUM_VENEER_ENTRY_NAME) + 10);
c7b8f16e
JB		 8301
8302 for (sec = abfd->sections; sec != NULL; sec = sec->next)
8303 {
8304 struct _arm_elf_section_data *sec_data = elf32_arm_section_data (sec);
8305 elf32_vfp11_erratum_list *errnode = sec_data->erratumlist;
906e58ca 8306
c7b8f16e 8307 for (; errnode != NULL; errnode = errnode->next)
99059e56
RM		 8308 {
8309 struct elf_link_hash_entry *myh;
8310 bfd_vma vma;
8311
8312 switch (errnode->type)
8313 {
8314 case VFP11_ERRATUM_BRANCH_TO_ARM_VENEER:
8315 case VFP11_ERRATUM_BRANCH_TO_THUMB_VENEER:
8316 /* Find veneer symbol. */
8317 sprintf (tmp_name, VFP11_ERRATUM_VENEER_ENTRY_NAME,
c7b8f16e
JB		 8318 errnode->u.b.veneer->u.v.id);
8319
99059e56
RM		 8320 myh = elf_link_hash_lookup
8321 (&(globals)->root, tmp_name, FALSE, FALSE, TRUE);
c7b8f16e 8322
a504d23a 8323 if (myh == NULL)
4eca0228
AM		 8324 _bfd_error_handler (_("%B: unable to find VFP11 veneer "
8325 "`%s'"), abfd, tmp_name);
a504d23a
LA		 8326
8327 vma = myh->root.u.def.section->output_section->vma
8328 + myh->root.u.def.section->output_offset
8329 + myh->root.u.def.value;
8330
8331 errnode->u.b.veneer->vma = vma;
8332 break;
8333
8334 case VFP11_ERRATUM_ARM_VENEER:
8335 case VFP11_ERRATUM_THUMB_VENEER:
8336 /* Find return location. */
8337 sprintf (tmp_name, VFP11_ERRATUM_VENEER_ENTRY_NAME "_r",
8338 errnode->u.v.id);
8339
8340 myh = elf_link_hash_lookup
8341 (&(globals)->root, tmp_name, FALSE, FALSE, TRUE);
8342
8343 if (myh == NULL)
4eca0228
AM		 8344 _bfd_error_handler (_("%B: unable to find VFP11 veneer "
8345 "`%s'"), abfd, tmp_name);
a504d23a
LA		 8346
8347 vma = myh->root.u.def.section->output_section->vma
8348 + myh->root.u.def.section->output_offset
8349 + myh->root.u.def.value;
8350
8351 errnode->u.v.branch->vma = vma;
8352 break;
8353
8354 default:
8355 abort ();
8356 }
8357 }
8358 }
8359
8360 free (tmp_name);
8361}
8362
8363/* Find virtual-memory addresses for STM32L4XX erratum veneers and
8364 return locations after sections have been laid out, using
8365 specially-named symbols. */
8366
8367void
8368bfd_elf32_arm_stm32l4xx_fix_veneer_locations (bfd *abfd,
8369 struct bfd_link_info *link_info)
8370{
8371 asection *sec;
8372 struct elf32_arm_link_hash_table *globals;
8373 char *tmp_name;
8374
8375 if (bfd_link_relocatable (link_info))
8376 return;
8377
8378 /* Skip if this bfd does not correspond to an ELF image. */
8379 if (! is_arm_elf (abfd))
8380 return;
8381
8382 globals = elf32_arm_hash_table (link_info);
8383 if (globals == NULL)
8384 return;
8385
8386 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen
8387 (STM32L4XX_ERRATUM_VENEER_ENTRY_NAME) + 10);
8388
8389 for (sec = abfd->sections; sec != NULL; sec = sec->next)
8390 {
8391 struct _arm_elf_section_data *sec_data = elf32_arm_section_data (sec);
8392 elf32_stm32l4xx_erratum_list *errnode = sec_data->stm32l4xx_erratumlist;
8393
8394 for (; errnode != NULL; errnode = errnode->next)
8395 {
8396 struct elf_link_hash_entry *myh;
8397 bfd_vma vma;
8398
8399 switch (errnode->type)
8400 {
8401 case STM32L4XX_ERRATUM_BRANCH_TO_VENEER:
8402 /* Find veneer symbol. */
8403 sprintf (tmp_name, STM32L4XX_ERRATUM_VENEER_ENTRY_NAME,
8404 errnode->u.b.veneer->u.v.id);
8405
8406 myh = elf_link_hash_lookup
8407 (&(globals)->root, tmp_name, FALSE, FALSE, TRUE);
8408
8409 if (myh == NULL)
4eca0228
AM		 8410 _bfd_error_handler (_("%B: unable to find STM32L4XX veneer "
8411 "`%s'"), abfd, tmp_name);
a504d23a
LA		 8412
8413 vma = myh->root.u.def.section->output_section->vma
8414 + myh->root.u.def.section->output_offset
8415 + myh->root.u.def.value;
8416
8417 errnode->u.b.veneer->vma = vma;
8418 break;
8419
8420 case STM32L4XX_ERRATUM_VENEER:
8421 /* Find return location. */
8422 sprintf (tmp_name, STM32L4XX_ERRATUM_VENEER_ENTRY_NAME "_r",
8423 errnode->u.v.id);
8424
8425 myh = elf_link_hash_lookup
8426 (&(globals)->root, tmp_name, FALSE, FALSE, TRUE);
8427
8428 if (myh == NULL)
4eca0228
AM		 8429 _bfd_error_handler (_("%B: unable to find STM32L4XX veneer "
8430 "`%s'"), abfd, tmp_name);
a504d23a
LA		 8431
8432 vma = myh->root.u.def.section->output_section->vma
8433 + myh->root.u.def.section->output_offset
8434 + myh->root.u.def.value;
8435
8436 errnode->u.v.branch->vma = vma;
8437 break;
8438
8439 default:
8440 abort ();
8441 }
8442 }
8443 }
8444
8445 free (tmp_name);
8446}
8447
8448static inline bfd_boolean
8449is_thumb2_ldmia (const insn32 insn)
8450{
8451 /* Encoding T2: LDM<c>.W <Rn>{!},<registers>
8452 1110 - 1000 - 10W1 - rrrr - PM (0) l - llll - llll - llll. */
8453 return (insn & 0xffd02000) == 0xe8900000;
8454}
8455
8456static inline bfd_boolean
8457is_thumb2_ldmdb (const insn32 insn)
8458{
8459 /* Encoding T1: LDMDB<c> <Rn>{!},<registers>
8460 1110 - 1001 - 00W1 - rrrr - PM (0) l - llll - llll - llll. */
8461 return (insn & 0xffd02000) == 0xe9100000;
8462}
8463
8464static inline bfd_boolean
8465is_thumb2_vldm (const insn32 insn)
8466{
8467 /* A6.5 Extension register load or store instruction
8468 A7.7.229
9239bbd3
CM		 8469 We look for SP 32-bit and DP 64-bit registers.
8470 Encoding T1 VLDM{mode}<c> <Rn>{!}, <list>
8471 <list> is consecutive 64-bit registers
8472 1110 - 110P - UDW1 - rrrr - vvvv - 1011 - iiii - iiii
a504d23a
LA		 8473 Encoding T2 VLDM{mode}<c> <Rn>{!}, <list>
8474 <list> is consecutive 32-bit registers
8475 1110 - 110P - UDW1 - rrrr - vvvv - 1010 - iiii - iiii
8476 if P==0 && U==1 && W==1 && Rn=1101 VPOP
8477 if PUW=010 || PUW=011 || PUW=101 VLDM. */
8478 return
9239bbd3
CM		 8479 (((insn & 0xfe100f00) == 0xec100b00) ||
8480 ((insn & 0xfe100f00) == 0xec100a00))
a504d23a
LA		 8481 && /* (IA without !). */
8482 (((((insn << 7) >> 28) & 0xd) == 0x4)
9239bbd3 8483 /* (IA with !), includes VPOP (when reg number is SP). */
a504d23a
LA		 8484 || ((((insn << 7) >> 28) & 0xd) == 0x5)
8485 /* (DB with !). */
8486 || ((((insn << 7) >> 28) & 0xd) == 0x9));
8487}
8488
8489/* STM STM32L4XX erratum : This function assumes that it receives an LDM or
8490 VLDM opcode and:
8491 - computes the number and the mode of memory accesses
8492 - decides if the replacement should be done:
8493 . replaces only if > 8-word accesses
8494 . or (testing purposes only) replaces all accesses. */
8495
8496static bfd_boolean
8497stm32l4xx_need_create_replacing_stub (const insn32 insn,
8498 bfd_arm_stm32l4xx_fix stm32l4xx_fix)
8499{
9239bbd3 8500 int nb_words = 0;
a504d23a
LA		 8501
8502 /* The field encoding the register list is the same for both LDMIA
8503 and LDMDB encodings. */
8504 if (is_thumb2_ldmia (insn) || is_thumb2_ldmdb (insn))
9239bbd3 8505 nb_words = popcount (insn & 0x0000ffff);
a504d23a 8506 else if (is_thumb2_vldm (insn))
9239bbd3 8507 nb_words = (insn & 0xff);
a504d23a
LA		 8508
8509 /* DEFAULT mode accounts for the real bug condition situation,
8510 ALL mode inserts stubs for each LDM/VLDM instruction (testing). */
8511 return
9239bbd3 8512 (stm32l4xx_fix == BFD_ARM_STM32L4XX_FIX_DEFAULT) ? nb_words > 8 :
a504d23a
LA		 8513 (stm32l4xx_fix == BFD_ARM_STM32L4XX_FIX_ALL) ? TRUE : FALSE;
8514}
8515
8516/* Look for potentially-troublesome code sequences which might trigger
8517 the STM STM32L4XX erratum. */
8518
8519bfd_boolean
8520bfd_elf32_arm_stm32l4xx_erratum_scan (bfd *abfd,
8521 struct bfd_link_info *link_info)
8522{
8523 asection *sec;
8524 bfd_byte *contents = NULL;
8525 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (link_info);
8526
8527 if (globals == NULL)
8528 return FALSE;
8529
8530 /* If we are only performing a partial link do not bother
8531 to construct any glue. */
8532 if (bfd_link_relocatable (link_info))
8533 return TRUE;
8534
8535 /* Skip if this bfd does not correspond to an ELF image. */
8536 if (! is_arm_elf (abfd))
8537 return TRUE;
8538
8539 if (globals->stm32l4xx_fix == BFD_ARM_STM32L4XX_FIX_NONE)
8540 return TRUE;
8541
8542 /* Skip this BFD if it corresponds to an executable or dynamic object. */
8543 if ((abfd->flags & (EXEC_P | DYNAMIC)) != 0)
8544 return TRUE;
8545
8546 for (sec = abfd->sections; sec != NULL; sec = sec->next)
8547 {
8548 unsigned int i, span;
8549 struct _arm_elf_section_data *sec_data;
8550
8551 /* If we don't have executable progbits, we're not interested in this
8552 section. Also skip if section is to be excluded. */
8553 if (elf_section_type (sec) != SHT_PROGBITS
8554 || (elf_section_flags (sec) & SHF_EXECINSTR) == 0
8555 || (sec->flags & SEC_EXCLUDE) != 0
8556 || sec->sec_info_type == SEC_INFO_TYPE_JUST_SYMS
8557 || sec->output_section == bfd_abs_section_ptr
8558 || strcmp (sec->name, STM32L4XX_ERRATUM_VENEER_SECTION_NAME) == 0)
8559 continue;
8560
8561 sec_data = elf32_arm_section_data (sec);
c7b8f16e 8562
a504d23a
LA		 8563 if (sec_data->mapcount == 0)
8564 continue;
c7b8f16e 8565
a504d23a
LA		 8566 if (elf_section_data (sec)->this_hdr.contents != NULL)
8567 contents = elf_section_data (sec)->this_hdr.contents;
8568 else if (! bfd_malloc_and_get_section (abfd, sec, &contents))
8569 goto error_return;
c7b8f16e 8570
a504d23a
LA		 8571 qsort (sec_data->map, sec_data->mapcount, sizeof (elf32_arm_section_map),
8572 elf32_arm_compare_mapping);
c7b8f16e 8573
a504d23a
LA		 8574 for (span = 0; span < sec_data->mapcount; span++)
8575 {
8576 unsigned int span_start = sec_data->map[span].vma;
8577 unsigned int span_end = (span == sec_data->mapcount - 1)
8578 ? sec->size : sec_data->map[span + 1].vma;
8579 char span_type = sec_data->map[span].type;
8580 int itblock_current_pos = 0;
c7b8f16e 8581
a504d23a
LA		 8582 /* Only Thumb2 mode need be supported with this CM4 specific
8583 code, we should not encounter any arm mode eg span_type
8584 != 'a'. */
8585 if (span_type != 't')
8586 continue;
c7b8f16e 8587
a504d23a
LA		 8588 for (i = span_start; i < span_end;)
8589 {
8590 unsigned int insn = bfd_get_16 (abfd, &contents[i]);
8591 bfd_boolean insn_32bit = FALSE;
8592 bfd_boolean is_ldm = FALSE;
8593 bfd_boolean is_vldm = FALSE;
8594 bfd_boolean is_not_last_in_it_block = FALSE;
8595
8596 /* The first 16-bits of all 32-bit thumb2 instructions start
8597 with opcode[15..13]=0b111 and the encoded op1 can be anything
8598 except opcode[12..11]!=0b00.
8599 See 32-bit Thumb instruction encoding. */
8600 if ((insn & 0xe000) == 0xe000 && (insn & 0x1800) != 0x0000)
8601 insn_32bit = TRUE;
c7b8f16e 8602
a504d23a
LA		 8603 /* Compute the predicate that tells if the instruction
8604 is concerned by the IT block
8605 - Creates an error if there is a ldm that is not
8606 last in the IT block thus cannot be replaced
8607 - Otherwise we can create a branch at the end of the
8608 IT block, it will be controlled naturally by IT
8609 with the proper pseudo-predicate
8610 - So the only interesting predicate is the one that
8611 tells that we are not on the last item of an IT
8612 block. */
8613 if (itblock_current_pos != 0)
8614 is_not_last_in_it_block = !!--itblock_current_pos;
906e58ca 8615
a504d23a
LA		 8616 if (insn_32bit)
8617 {
8618 /* Load the rest of the insn (in manual-friendly order). */
8619 insn = (insn << 16) | bfd_get_16 (abfd, &contents[i + 2]);
8620 is_ldm = is_thumb2_ldmia (insn) || is_thumb2_ldmdb (insn);
8621 is_vldm = is_thumb2_vldm (insn);
8622
8623 /* Veneers are created for (v)ldm depending on
8624 option flags and memory accesses conditions; but
8625 if the instruction is not the last instruction of
8626 an IT block, we cannot create a jump there, so we
8627 bail out. */
5025eb7c
AO		 8628 if ((is_ldm || is_vldm)
8629 && stm32l4xx_need_create_replacing_stub
a504d23a
LA		 8630 (insn, globals->stm32l4xx_fix))
8631 {
8632 if (is_not_last_in_it_block)
8633 {
4eca0228 8634 _bfd_error_handler
a504d23a
LA		 8635 /* Note - overlong line used here to allow for translation. */
8636 (_("\
8637%B(%A+0x%lx): error: multiple load detected in non-last IT block instruction : STM32L4XX veneer cannot be generated.\n"
8638 "Use gcc option -mrestrict-it to generate only one instruction per IT block.\n"),
8639 abfd, sec, (long)i);
8640 }
8641 else
8642 {
8643 elf32_stm32l4xx_erratum_list *newerr =
8644 (elf32_stm32l4xx_erratum_list *)
8645 bfd_zmalloc
8646 (sizeof (elf32_stm32l4xx_erratum_list));
8647
8648 elf32_arm_section_data (sec)
8649 ->stm32l4xx_erratumcount += 1;
8650 newerr->u.b.insn = insn;
8651 /* We create only thumb branches. */
8652 newerr->type =
8653 STM32L4XX_ERRATUM_BRANCH_TO_VENEER;
8654 record_stm32l4xx_erratum_veneer
8655 (link_info, newerr, abfd, sec,
8656 i,
8657 is_ldm ?
8658 STM32L4XX_ERRATUM_LDM_VENEER_SIZE:
8659 STM32L4XX_ERRATUM_VLDM_VENEER_SIZE);
8660 newerr->vma = -1;
8661 newerr->next = sec_data->stm32l4xx_erratumlist;
8662 sec_data->stm32l4xx_erratumlist = newerr;
8663 }
8664 }
8665 }
8666 else
8667 {
8668 /* A7.7.37 IT p208
8669 IT blocks are only encoded in T1
8670 Encoding T1: IT{x{y{z}}} <firstcond>
8671 1 0 1 1 - 1 1 1 1 - firstcond - mask
8672 if mask = '0000' then see 'related encodings'
8673 We don't deal with UNPREDICTABLE, just ignore these.
8674 There can be no nested IT blocks so an IT block
8675 is naturally a new one for which it is worth
8676 computing its size. */
5025eb7c
AO		 8677 bfd_boolean is_newitblock = ((insn & 0xff00) == 0xbf00)
8678 && ((insn & 0x000f) != 0x0000);
a504d23a
LA		 8679 /* If we have a new IT block we compute its size. */
8680 if (is_newitblock)
8681 {
8682 /* Compute the number of instructions controlled
8683 by the IT block, it will be used to decide
8684 whether we are inside an IT block or not. */
8685 unsigned int mask = insn & 0x000f;
8686 itblock_current_pos = 4 - ctz (mask);
8687 }
8688 }
8689
8690 i += insn_32bit ? 4 : 2;
99059e56
RM		 8691 }
8692 }
a504d23a
LA		 8693
8694 if (contents != NULL
8695 && elf_section_data (sec)->this_hdr.contents != contents)
8696 free (contents);
8697 contents = NULL;
c7b8f16e 8698 }
906e58ca 8699
a504d23a
LA		 8700 return TRUE;
8701
8702error_return:
8703 if (contents != NULL
8704 && elf_section_data (sec)->this_hdr.contents != contents)
8705 free (contents);
c7b8f16e 8706
a504d23a
LA		 8707 return FALSE;
8708}
c7b8f16e 8709
eb043451
PB		 8710/* Set target relocation values needed during linking. */
8711
8712void
68c39892 8713bfd_elf32_arm_set_target_params (struct bfd *output_bfd,
bf21ed78 8714 struct bfd_link_info *link_info,
68c39892 8715 struct elf32_arm_params *params)
eb043451
PB		 8716{
8717 struct elf32_arm_link_hash_table *globals;
8718
8719 globals = elf32_arm_hash_table (link_info);
4dfe6ac6
NC		 8720 if (globals == NULL)
8721 return;
eb043451 8722
68c39892
TP		 8723 globals->target1_is_rel = params->target1_is_rel;
8724 if (strcmp (params->target2_type, "rel") == 0)
eb043451 8725 globals->target2_reloc = R_ARM_REL32;
68c39892 8726 else if (strcmp (params->target2_type, "abs") == 0)
eeac373a 8727 globals->target2_reloc = R_ARM_ABS32;
68c39892 8728 else if (strcmp (params->target2_type, "got-rel") == 0)
eb043451
PB		 8729 globals->target2_reloc = R_ARM_GOT_PREL;
8730 else
8731 {
8732 _bfd_error_handler (_("Invalid TARGET2 relocation type '%s'."),
68c39892 8733 params->target2_type);
eb043451 8734 }
68c39892
TP		 8735 globals->fix_v4bx = params->fix_v4bx;
8736 globals->use_blx |= params->use_blx;
8737 globals->vfp11_fix = params->vfp11_denorm_fix;
8738 globals->stm32l4xx_fix = params->stm32l4xx_fix;
8739 globals->pic_veneer = params->pic_veneer;
8740 globals->fix_cortex_a8 = params->fix_cortex_a8;
8741 globals->fix_arm1176 = params->fix_arm1176;
8742 globals->cmse_implib = params->cmse_implib;
8743 globals->in_implib_bfd = params->in_implib_bfd;
bf21ed78 8744
0ffa91dd 8745 BFD_ASSERT (is_arm_elf (output_bfd));
68c39892
TP		 8746 elf_arm_tdata (output_bfd)->no_enum_size_warning
8747 = params->no_enum_size_warning;
8748 elf_arm_tdata (output_bfd)->no_wchar_size_warning
8749 = params->no_wchar_size_warning;
eb043451 8750}
eb043451 8751
12a0a0fd 8752/* Replace the target offset of a Thumb bl or b.w instruction. */
252b5132 8753
12a0a0fd
PB		 8754static void
8755insert_thumb_branch (bfd *abfd, long int offset, bfd_byte *insn)
8756{
8757 bfd_vma upper;
8758 bfd_vma lower;
8759 int reloc_sign;
8760
8761 BFD_ASSERT ((offset & 1) == 0);
8762
8763 upper = bfd_get_16 (abfd, insn);
8764 lower = bfd_get_16 (abfd, insn + 2);
8765 reloc_sign = (offset < 0) ? 1 : 0;
8766 upper = (upper & ~(bfd_vma) 0x7ff)
8767 | ((offset >> 12) & 0x3ff)
8768 | (reloc_sign << 10);
906e58ca 8769 lower = (lower & ~(bfd_vma) 0x2fff)
12a0a0fd
PB		 8770 | (((!((offset >> 23) & 1)) ^ reloc_sign) << 13)
8771 | (((!((offset >> 22) & 1)) ^ reloc_sign) << 11)
8772 | ((offset >> 1) & 0x7ff);
8773 bfd_put_16 (abfd, upper, insn);
8774 bfd_put_16 (abfd, lower, insn + 2);
252b5132
RH		 8775}
8776
9b485d32
NC		 8777/* Thumb code calling an ARM function. */
8778
252b5132 8779static int
57e8b36a
NC		 8780elf32_thumb_to_arm_stub (struct bfd_link_info * info,
8781 const char * name,
8782 bfd * input_bfd,
8783 bfd * output_bfd,
8784 asection * input_section,
8785 bfd_byte * hit_data,
8786 asection * sym_sec,
8787 bfd_vma offset,
8788 bfd_signed_vma addend,
f2a9dd69
DJ		 8789 bfd_vma val,
8790 char **error_message)
252b5132 8791{
bcbdc74c 8792 asection * s = 0;
dc810e39 8793 bfd_vma my_offset;
252b5132 8794 long int ret_offset;
bcbdc74c
NC		 8795 struct elf_link_hash_entry * myh;
8796 struct elf32_arm_link_hash_table * globals;
252b5132 8797
f2a9dd69 8798 myh = find_thumb_glue (info, name, error_message);
252b5132 8799 if (myh == NULL)
b34976b6 8800 return FALSE;
252b5132
RH		 8801
8802 globals = elf32_arm_hash_table (info);
252b5132
RH		 8803 BFD_ASSERT (globals != NULL);
8804 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
8805
8806 my_offset = myh->root.u.def.value;
8807
3d4d4302
AM		 8808 s = bfd_get_linker_section (globals->bfd_of_glue_owner,
8809 THUMB2ARM_GLUE_SECTION_NAME);
252b5132
RH		 8810
8811 BFD_ASSERT (s != NULL);
8812 BFD_ASSERT (s->contents != NULL);
8813 BFD_ASSERT (s->output_section != NULL);
8814
8815 if ((my_offset & 0x01) == 0x01)
8816 {
8817 if (sym_sec != NULL
8818 && sym_sec->owner != NULL
8819 && !INTERWORK_FLAG (sym_sec->owner))
8820 {
4eca0228 8821 _bfd_error_handler
d003868e 8822 (_("%B(%s): warning: interworking not enabled.\n"
3aaeb7d3 8823 " first occurrence: %B: Thumb call to ARM"),
d003868e 8824 sym_sec->owner, input_bfd, name);
252b5132 8825
b34976b6 8826 return FALSE;
252b5132
RH		 8827 }
8828
8829 --my_offset;
8830 myh->root.u.def.value = my_offset;
8831
52ab56c2
PB		 8832 put_thumb_insn (globals, output_bfd, (bfd_vma) t2a1_bx_pc_insn,
8833 s->contents + my_offset);
252b5132 8834
52ab56c2
PB		 8835 put_thumb_insn (globals, output_bfd, (bfd_vma) t2a2_noop_insn,
8836 s->contents + my_offset + 2);
252b5132
RH		 8837
8838 ret_offset =
9b485d32
NC		 8839 /* Address of destination of the stub. */
8840 ((bfd_signed_vma) val)
252b5132 8841 - ((bfd_signed_vma)
57e8b36a
NC		 8842 /* Offset from the start of the current section
8843 to the start of the stubs. */
9b485d32
NC		 8844 (s->output_offset
8845 /* Offset of the start of this stub from the start of the stubs. */
8846 + my_offset
8847 /* Address of the start of the current section. */
8848 + s->output_section->vma)
8849 /* The branch instruction is 4 bytes into the stub. */
8850 + 4
8851 /* ARM branches work from the pc of the instruction + 8. */
8852 + 8);
252b5132 8853
52ab56c2
PB		 8854 put_arm_insn (globals, output_bfd,
8855 (bfd_vma) t2a3_b_insn | ((ret_offset >> 2) & 0x00FFFFFF),
8856 s->contents + my_offset + 4);
252b5132
RH		 8857 }
8858
8859 BFD_ASSERT (my_offset <= globals->thumb_glue_size);
8860
427bfd90
NC		 8861 /* Now go back and fix up the original BL insn to point to here. */
8862 ret_offset =
8863 /* Address of where the stub is located. */
8864 (s->output_section->vma + s->output_offset + my_offset)
8865 /* Address of where the BL is located. */
57e8b36a
NC		 8866 - (input_section->output_section->vma + input_section->output_offset
8867 + offset)
427bfd90
NC		 8868 /* Addend in the relocation. */
8869 - addend
8870 /* Biassing for PC-relative addressing. */
8871 - 8;
252b5132 8872
12a0a0fd 8873 insert_thumb_branch (input_bfd, ret_offset, hit_data - input_section->vma);
252b5132 8874
b34976b6 8875 return TRUE;
252b5132
RH		 8876}
8877
a4fd1a8e 8878/* Populate an Arm to Thumb stub. Returns the stub symbol. */
9b485d32 8879
a4fd1a8e
PB		 8880static struct elf_link_hash_entry *
8881elf32_arm_create_thumb_stub (struct bfd_link_info * info,
8882 const char * name,
8883 bfd * input_bfd,
8884 bfd * output_bfd,
8885 asection * sym_sec,
8886 bfd_vma val,
8029a119
NC		 8887 asection * s,
8888 char ** error_message)
252b5132 8889{
dc810e39 8890 bfd_vma my_offset;
252b5132 8891 long int ret_offset;
bcbdc74c
NC		 8892 struct elf_link_hash_entry * myh;
8893 struct elf32_arm_link_hash_table * globals;
252b5132 8894
f2a9dd69 8895 myh = find_arm_glue (info, name, error_message);
252b5132 8896 if (myh == NULL)
a4fd1a8e 8897 return NULL;
252b5132
RH		 8898
8899 globals = elf32_arm_hash_table (info);
252b5132
RH		 8900 BFD_ASSERT (globals != NULL);
8901 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
8902
8903 my_offset = myh->root.u.def.value;
252b5132
RH		 8904
8905 if ((my_offset & 0x01) == 0x01)
8906 {
8907 if (sym_sec != NULL
8908 && sym_sec->owner != NULL
8909 && !INTERWORK_FLAG (sym_sec->owner))
8910 {
4eca0228 8911 _bfd_error_handler
d003868e
AM		 8912 (_("%B(%s): warning: interworking not enabled.\n"
8913 " first occurrence: %B: arm call to thumb"),
8914 sym_sec->owner, input_bfd, name);
252b5132 8915 }
9b485d32 8916
252b5132
RH		 8917 --my_offset;
8918 myh->root.u.def.value = my_offset;
8919
0e1862bb
L		 8920 if (bfd_link_pic (info)
8921 || globals->root.is_relocatable_executable
27e55c4d 8922 || globals->pic_veneer)
8f6277f5
PB		 8923 {
8924 /* For relocatable objects we can't use absolute addresses,
8925 so construct the address from a relative offset. */
8926 /* TODO: If the offset is small it's probably worth
8927 constructing the address with adds. */
52ab56c2
PB		 8928 put_arm_insn (globals, output_bfd, (bfd_vma) a2t1p_ldr_insn,
8929 s->contents + my_offset);
8930 put_arm_insn (globals, output_bfd, (bfd_vma) a2t2p_add_pc_insn,
8931 s->contents + my_offset + 4);
8932 put_arm_insn (globals, output_bfd, (bfd_vma) a2t3p_bx_r12_insn,
8933 s->contents + my_offset + 8);
8f6277f5
PB		 8934 /* Adjust the offset by 4 for the position of the add,
8935 and 8 for the pipeline offset. */
8936 ret_offset = (val - (s->output_offset
8937 + s->output_section->vma
8938 + my_offset + 12))
8939 | 1;
8940 bfd_put_32 (output_bfd, ret_offset,
8941 s->contents + my_offset + 12);
8942 }
26079076
PB		 8943 else if (globals->use_blx)
8944 {
8945 put_arm_insn (globals, output_bfd, (bfd_vma) a2t1v5_ldr_insn,
8946 s->contents + my_offset);
8947
8948 /* It's a thumb address. Add the low order bit. */
8949 bfd_put_32 (output_bfd, val | a2t2v5_func_addr_insn,
8950 s->contents + my_offset + 4);
8951 }
8f6277f5
PB		 8952 else
8953 {
52ab56c2
PB		 8954 put_arm_insn (globals, output_bfd, (bfd_vma) a2t1_ldr_insn,
8955 s->contents + my_offset);
252b5132 8956
52ab56c2
PB		 8957 put_arm_insn (globals, output_bfd, (bfd_vma) a2t2_bx_r12_insn,
8958 s->contents + my_offset + 4);
252b5132 8959
8f6277f5
PB		 8960 /* It's a thumb address. Add the low order bit. */
8961 bfd_put_32 (output_bfd, val | a2t3_func_addr_insn,
8962 s->contents + my_offset + 8);
8029a119
NC		 8963
8964 my_offset += 12;
8f6277f5 8965 }
252b5132
RH		 8966 }
8967
8968 BFD_ASSERT (my_offset <= globals->arm_glue_size);
8969
a4fd1a8e
PB		 8970 return myh;
8971}
8972
8973/* Arm code calling a Thumb function. */
8974
8975static int
8976elf32_arm_to_thumb_stub (struct bfd_link_info * info,
8977 const char * name,
8978 bfd * input_bfd,
8979 bfd * output_bfd,
8980 asection * input_section,
8981 bfd_byte * hit_data,
8982 asection * sym_sec,
8983 bfd_vma offset,
8984 bfd_signed_vma addend,
f2a9dd69
DJ		 8985 bfd_vma val,
8986 char **error_message)
a4fd1a8e
PB		 8987{
8988 unsigned long int tmp;
8989 bfd_vma my_offset;
8990 asection * s;
8991 long int ret_offset;
8992 struct elf_link_hash_entry * myh;
8993 struct elf32_arm_link_hash_table * globals;
8994
8995 globals = elf32_arm_hash_table (info);
a4fd1a8e
PB		 8996 BFD_ASSERT (globals != NULL);
8997 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
8998
3d4d4302
AM		 8999 s = bfd_get_linker_section (globals->bfd_of_glue_owner,
9000 ARM2THUMB_GLUE_SECTION_NAME);
a4fd1a8e
PB		 9001 BFD_ASSERT (s != NULL);
9002 BFD_ASSERT (s->contents != NULL);
9003 BFD_ASSERT (s->output_section != NULL);
9004
9005 myh = elf32_arm_create_thumb_stub (info, name, input_bfd, output_bfd,
f2a9dd69 9006 sym_sec, val, s, error_message);
a4fd1a8e
PB		 9007 if (!myh)
9008 return FALSE;
9009
9010 my_offset = myh->root.u.def.value;
252b5132
RH		 9011 tmp = bfd_get_32 (input_bfd, hit_data);
9012 tmp = tmp & 0xFF000000;
9013
9b485d32 9014 /* Somehow these are both 4 too far, so subtract 8. */
dc810e39
AM		 9015 ret_offset = (s->output_offset
9016 + my_offset
9017 + s->output_section->vma
9018 - (input_section->output_offset
9019 + input_section->output_section->vma
9020 + offset + addend)
9021 - 8);
9a5aca8c 9022
252b5132
RH		 9023 tmp = tmp | ((ret_offset >> 2) & 0x00FFFFFF);
9024
dc810e39 9025 bfd_put_32 (output_bfd, (bfd_vma) tmp, hit_data - input_section->vma);
252b5132 9026
b34976b6 9027 return TRUE;
252b5132
RH		 9028}
9029
a4fd1a8e
PB		 9030/* Populate Arm stub for an exported Thumb function. */
9031
9032static bfd_boolean
9033elf32_arm_to_thumb_export_stub (struct elf_link_hash_entry *h, void * inf)
9034{
9035 struct bfd_link_info * info = (struct bfd_link_info *) inf;
9036 asection * s;
9037 struct elf_link_hash_entry * myh;
9038 struct elf32_arm_link_hash_entry *eh;
9039 struct elf32_arm_link_hash_table * globals;
9040 asection *sec;
9041 bfd_vma val;
f2a9dd69 9042 char *error_message;
a4fd1a8e 9043
906e58ca 9044 eh = elf32_arm_hash_entry (h);
a4fd1a8e
PB		 9045 /* Allocate stubs for exported Thumb functions on v4t. */
9046 if (eh->export_glue == NULL)
9047 return TRUE;
9048
9049 globals = elf32_arm_hash_table (info);
a4fd1a8e
PB		 9050 BFD_ASSERT (globals != NULL);
9051 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
9052
3d4d4302
AM		 9053 s = bfd_get_linker_section (globals->bfd_of_glue_owner,
9054 ARM2THUMB_GLUE_SECTION_NAME);
a4fd1a8e
PB		 9055 BFD_ASSERT (s != NULL);
9056 BFD_ASSERT (s->contents != NULL);
9057 BFD_ASSERT (s->output_section != NULL);
9058
9059 sec = eh->export_glue->root.u.def.section;
0eaedd0e
PB		 9060
9061 BFD_ASSERT (sec->output_section != NULL);
9062
a4fd1a8e
PB		 9063 val = eh->export_glue->root.u.def.value + sec->output_offset
9064 + sec->output_section->vma;
8029a119 9065
a4fd1a8e
PB		 9066 myh = elf32_arm_create_thumb_stub (info, h->root.root.string,
9067 h->root.u.def.section->owner,
f2a9dd69
DJ		 9068 globals->obfd, sec, val, s,
9069 &error_message);
a4fd1a8e
PB		 9070 BFD_ASSERT (myh);
9071 return TRUE;
9072}
9073
845b51d6
PB		 9074/* Populate ARMv4 BX veneers. Returns the absolute adress of the veneer. */
9075
9076static bfd_vma
9077elf32_arm_bx_glue (struct bfd_link_info * info, int reg)
9078{
9079 bfd_byte *p;
9080 bfd_vma glue_addr;
9081 asection *s;
9082 struct elf32_arm_link_hash_table *globals;
9083
9084 globals = elf32_arm_hash_table (info);
845b51d6
PB		 9085 BFD_ASSERT (globals != NULL);
9086 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
9087
3d4d4302
AM		 9088 s = bfd_get_linker_section (globals->bfd_of_glue_owner,
9089 ARM_BX_GLUE_SECTION_NAME);
845b51d6
PB		 9090 BFD_ASSERT (s != NULL);
9091 BFD_ASSERT (s->contents != NULL);
9092 BFD_ASSERT (s->output_section != NULL);
9093
9094 BFD_ASSERT (globals->bx_glue_offset[reg] & 2);
9095
9096 glue_addr = globals->bx_glue_offset[reg] & ~(bfd_vma)3;
9097
9098 if ((globals->bx_glue_offset[reg] & 1) == 0)
9099 {
9100 p = s->contents + glue_addr;
9101 bfd_put_32 (globals->obfd, armbx1_tst_insn + (reg << 16), p);
9102 bfd_put_32 (globals->obfd, armbx2_moveq_insn + reg, p + 4);
9103 bfd_put_32 (globals->obfd, armbx3_bx_insn + reg, p + 8);
9104 globals->bx_glue_offset[reg] |= 1;
9105 }
9106
9107 return glue_addr + s->output_section->vma + s->output_offset;
9108}
9109
a4fd1a8e
PB		 9110/* Generate Arm stubs for exported Thumb symbols. */
9111static void
906e58ca 9112elf32_arm_begin_write_processing (bfd *abfd ATTRIBUTE_UNUSED,
a4fd1a8e
PB		 9113 struct bfd_link_info *link_info)
9114{
9115 struct elf32_arm_link_hash_table * globals;
9116
8029a119
NC		 9117 if (link_info == NULL)
9118 /* Ignore this if we are not called by the ELF backend linker. */
a4fd1a8e
PB		 9119 return;
9120
9121 globals = elf32_arm_hash_table (link_info);
4dfe6ac6
NC		 9122 if (globals == NULL)
9123 return;
9124
84c08195
PB		 9125 /* If blx is available then exported Thumb symbols are OK and there is
9126 nothing to do. */
a4fd1a8e
PB		 9127 if (globals->use_blx)
9128 return;
9129
9130 elf_link_hash_traverse (&globals->root, elf32_arm_to_thumb_export_stub,
9131 link_info);
9132}
9133
47beaa6a
RS		 9134/* Reserve space for COUNT dynamic relocations in relocation selection
9135 SRELOC. */
9136
9137static void
9138elf32_arm_allocate_dynrelocs (struct bfd_link_info *info, asection *sreloc,
9139 bfd_size_type count)
9140{
9141 struct elf32_arm_link_hash_table *htab;
9142
9143 htab = elf32_arm_hash_table (info);
9144 BFD_ASSERT (htab->root.dynamic_sections_created);
9145 if (sreloc == NULL)
9146 abort ();
9147 sreloc->size += RELOC_SIZE (htab) * count;
9148}
9149
34e77a92
RS		 9150/* Reserve space for COUNT R_ARM_IRELATIVE relocations. If the link is
9151 dynamic, the relocations should go in SRELOC, otherwise they should
9152 go in the special .rel.iplt section. */
9153
9154static void
9155elf32_arm_allocate_irelocs (struct bfd_link_info *info, asection *sreloc,
9156 bfd_size_type count)
9157{
9158 struct elf32_arm_link_hash_table *htab;
9159
9160 htab = elf32_arm_hash_table (info);
9161 if (!htab->root.dynamic_sections_created)
9162 htab->root.irelplt->size += RELOC_SIZE (htab) * count;
9163 else
9164 {
9165 BFD_ASSERT (sreloc != NULL);
9166 sreloc->size += RELOC_SIZE (htab) * count;
9167 }
9168}
9169
47beaa6a
RS		 9170/* Add relocation REL to the end of relocation section SRELOC. */
9171
9172static void
9173elf32_arm_add_dynreloc (bfd *output_bfd, struct bfd_link_info *info,
9174 asection *sreloc, Elf_Internal_Rela *rel)
9175{
9176 bfd_byte *loc;
9177 struct elf32_arm_link_hash_table *htab;
9178
9179 htab = elf32_arm_hash_table (info);
34e77a92
RS		 9180 if (!htab->root.dynamic_sections_created
9181 && ELF32_R_TYPE (rel->r_info) == R_ARM_IRELATIVE)
9182 sreloc = htab->root.irelplt;
47beaa6a
RS		 9183 if (sreloc == NULL)
9184 abort ();
9185 loc = sreloc->contents;
9186 loc += sreloc->reloc_count++ * RELOC_SIZE (htab);
9187 if (sreloc->reloc_count * RELOC_SIZE (htab) > sreloc->size)
9188 abort ();
9189 SWAP_RELOC_OUT (htab) (output_bfd, rel, loc);
9190}
9191
34e77a92
RS		 9192/* Allocate room for a PLT entry described by ROOT_PLT and ARM_PLT.
9193 IS_IPLT_ENTRY says whether the entry belongs to .iplt rather than
9194 to .plt. */
9195
9196static void
9197elf32_arm_allocate_plt_entry (struct bfd_link_info *info,
9198 bfd_boolean is_iplt_entry,
9199 union gotplt_union *root_plt,
9200 struct arm_plt_info *arm_plt)
9201{
9202 struct elf32_arm_link_hash_table *htab;
9203 asection *splt;
9204 asection *sgotplt;
9205
9206 htab = elf32_arm_hash_table (info);
9207
9208 if (is_iplt_entry)
9209 {
9210 splt = htab->root.iplt;
9211 sgotplt = htab->root.igotplt;
9212
99059e56
RM		 9213 /* NaCl uses a special first entry in .iplt too. */
9214 if (htab->nacl_p && splt->size == 0)
9215 splt->size += htab->plt_header_size;
9216
34e77a92
RS		 9217 /* Allocate room for an R_ARM_IRELATIVE relocation in .rel.iplt. */
9218 elf32_arm_allocate_irelocs (info, htab->root.irelplt, 1);
9219 }
9220 else
9221 {
9222 splt = htab->root.splt;
9223 sgotplt = htab->root.sgotplt;
9224
9225 /* Allocate room for an R_JUMP_SLOT relocation in .rel.plt. */
9226 elf32_arm_allocate_dynrelocs (info, htab->root.srelplt, 1);
9227
9228 /* If this is the first .plt entry, make room for the special
9229 first entry. */
9230 if (splt->size == 0)
9231 splt->size += htab->plt_header_size;
9f19ab6d
WN		 9232
9233 htab->next_tls_desc_index++;
34e77a92
RS		 9234 }
9235
9236 /* Allocate the PLT entry itself, including any leading Thumb stub. */
9237 if (elf32_arm_plt_needs_thumb_stub_p (info, arm_plt))
9238 splt->size += PLT_THUMB_STUB_SIZE;
9239 root_plt->offset = splt->size;
9240 splt->size += htab->plt_entry_size;
9241
9242 if (!htab->symbian_p)
9243 {
9244 /* We also need to make an entry in the .got.plt section, which
9245 will be placed in the .got section by the linker script. */
9f19ab6d
WN		 9246 if (is_iplt_entry)
9247 arm_plt->got_offset = sgotplt->size;
9248 else
9249 arm_plt->got_offset = sgotplt->size - 8 * htab->num_tls_desc;
34e77a92
RS		 9250 sgotplt->size += 4;
9251 }
9252}
9253
b38cadfb
NC		 9254static bfd_vma
9255arm_movw_immediate (bfd_vma value)
9256{
9257 return (value & 0x00000fff) | ((value & 0x0000f000) << 4);
9258}
9259
9260static bfd_vma
9261arm_movt_immediate (bfd_vma value)
9262{
9263 return ((value & 0x0fff0000) >> 16) | ((value & 0xf0000000) >> 12);
9264}
9265
34e77a92
RS		 9266/* Fill in a PLT entry and its associated GOT slot. If DYNINDX == -1,
9267 the entry lives in .iplt and resolves to (*SYM_VALUE)().
9268 Otherwise, DYNINDX is the index of the symbol in the dynamic
9269 symbol table and SYM_VALUE is undefined.
9270
9271 ROOT_PLT points to the offset of the PLT entry from the start of its
9272 section (.iplt or .plt). ARM_PLT points to the symbol's ARM-specific
57460bcf 9273 bookkeeping information.
34e77a92 9274
57460bcf
NC		 9275 Returns FALSE if there was a problem. */
9276
9277static bfd_boolean
34e77a92
RS		 9278elf32_arm_populate_plt_entry (bfd *output_bfd, struct bfd_link_info *info,
9279 union gotplt_union *root_plt,
9280 struct arm_plt_info *arm_plt,
9281 int dynindx, bfd_vma sym_value)
9282{
9283 struct elf32_arm_link_hash_table *htab;
9284 asection *sgot;
9285 asection *splt;
9286 asection *srel;
9287 bfd_byte *loc;
9288 bfd_vma plt_index;
9289 Elf_Internal_Rela rel;
9290 bfd_vma plt_header_size;
9291 bfd_vma got_header_size;
9292
9293 htab = elf32_arm_hash_table (info);
9294
9295 /* Pick the appropriate sections and sizes. */
9296 if (dynindx == -1)
9297 {
9298 splt = htab->root.iplt;
9299 sgot = htab->root.igotplt;
9300 srel = htab->root.irelplt;
9301
9302 /* There are no reserved entries in .igot.plt, and no special
9303 first entry in .iplt. */
9304 got_header_size = 0;
9305 plt_header_size = 0;
9306 }
9307 else
9308 {
9309 splt = htab->root.splt;
9310 sgot = htab->root.sgotplt;
9311 srel = htab->root.srelplt;
9312
9313 got_header_size = get_elf_backend_data (output_bfd)->got_header_size;
9314 plt_header_size = htab->plt_header_size;
9315 }
9316 BFD_ASSERT (splt != NULL && srel != NULL);
9317
9318 /* Fill in the entry in the procedure linkage table. */
9319 if (htab->symbian_p)
9320 {
9321 BFD_ASSERT (dynindx >= 0);
9322 put_arm_insn (htab, output_bfd,
9323 elf32_arm_symbian_plt_entry[0],
9324 splt->contents + root_plt->offset);
9325 bfd_put_32 (output_bfd,
9326 elf32_arm_symbian_plt_entry[1],
9327 splt->contents + root_plt->offset + 4);
9328
9329 /* Fill in the entry in the .rel.plt section. */
9330 rel.r_offset = (splt->output_section->vma
9331 + splt->output_offset
9332 + root_plt->offset + 4);
9333 rel.r_info = ELF32_R_INFO (dynindx, R_ARM_GLOB_DAT);
9334
9335 /* Get the index in the procedure linkage table which
9336 corresponds to this symbol. This is the index of this symbol
9337 in all the symbols for which we are making plt entries. The
9338 first entry in the procedure linkage table is reserved. */
9339 plt_index = ((root_plt->offset - plt_header_size)
9340 / htab->plt_entry_size);
9341 }
9342 else
9343 {
9344 bfd_vma got_offset, got_address, plt_address;
9345 bfd_vma got_displacement, initial_got_entry;
9346 bfd_byte * ptr;
9347
9348 BFD_ASSERT (sgot != NULL);
9349
9350 /* Get the offset into the .(i)got.plt table of the entry that
9351 corresponds to this function. */
9352 got_offset = (arm_plt->got_offset & -2);
9353
9354 /* Get the index in the procedure linkage table which
9355 corresponds to this symbol. This is the index of this symbol
9356 in all the symbols for which we are making plt entries.
9357 After the reserved .got.plt entries, all symbols appear in
9358 the same order as in .plt. */
9359 plt_index = (got_offset - got_header_size) / 4;
9360
9361 /* Calculate the address of the GOT entry. */
9362 got_address = (sgot->output_section->vma
9363 + sgot->output_offset
9364 + got_offset);
9365
9366 /* ...and the address of the PLT entry. */
9367 plt_address = (splt->output_section->vma
9368 + splt->output_offset
9369 + root_plt->offset);
9370
9371 ptr = splt->contents + root_plt->offset;
0e1862bb 9372 if (htab->vxworks_p && bfd_link_pic (info))
34e77a92
RS		 9373 {
9374 unsigned int i;
9375 bfd_vma val;
9376
9377 for (i = 0; i != htab->plt_entry_size / 4; i++, ptr += 4)
9378 {
9379 val = elf32_arm_vxworks_shared_plt_entry[i];
9380 if (i == 2)
9381 val |= got_address - sgot->output_section->vma;
9382 if (i == 5)
9383 val |= plt_index * RELOC_SIZE (htab);
9384 if (i == 2 || i == 5)
9385 bfd_put_32 (output_bfd, val, ptr);
9386 else
9387 put_arm_insn (htab, output_bfd, val, ptr);
9388 }
9389 }
9390 else if (htab->vxworks_p)
9391 {
9392 unsigned int i;
9393 bfd_vma val;
9394
9395 for (i = 0; i != htab->plt_entry_size / 4; i++, ptr += 4)
9396 {
9397 val = elf32_arm_vxworks_exec_plt_entry[i];
9398 if (i == 2)
9399 val |= got_address;
9400 if (i == 4)
9401 val |= 0xffffff & -((root_plt->offset + i * 4 + 8) >> 2);
9402 if (i == 5)
9403 val |= plt_index * RELOC_SIZE (htab);
9404 if (i == 2 || i == 5)
9405 bfd_put_32 (output_bfd, val, ptr);
9406 else
9407 put_arm_insn (htab, output_bfd, val, ptr);
9408 }
9409
9410 loc = (htab->srelplt2->contents
9411 + (plt_index * 2 + 1) * RELOC_SIZE (htab));
9412
9413 /* Create the .rela.plt.unloaded R_ARM_ABS32 relocation
9414 referencing the GOT for this PLT entry. */
9415 rel.r_offset = plt_address + 8;
9416 rel.r_info = ELF32_R_INFO (htab->root.hgot->indx, R_ARM_ABS32);
9417 rel.r_addend = got_offset;
9418 SWAP_RELOC_OUT (htab) (output_bfd, &rel, loc);
9419 loc += RELOC_SIZE (htab);
9420
9421 /* Create the R_ARM_ABS32 relocation referencing the
9422 beginning of the PLT for this GOT entry. */
9423 rel.r_offset = got_address;
9424 rel.r_info = ELF32_R_INFO (htab->root.hplt->indx, R_ARM_ABS32);
9425 rel.r_addend = 0;
9426 SWAP_RELOC_OUT (htab) (output_bfd, &rel, loc);
9427 }
b38cadfb
NC		 9428 else if (htab->nacl_p)
9429 {
9430 /* Calculate the displacement between the PLT slot and the
9431 common tail that's part of the special initial PLT slot. */
6034aab8 9432 int32_t tail_displacement
b38cadfb
NC		 9433 = ((splt->output_section->vma + splt->output_offset
9434 + ARM_NACL_PLT_TAIL_OFFSET)
9435 - (plt_address + htab->plt_entry_size + 4));
9436 BFD_ASSERT ((tail_displacement & 3) == 0);
9437 tail_displacement >>= 2;
9438
9439 BFD_ASSERT ((tail_displacement & 0xff000000) == 0
9440 || (-tail_displacement & 0xff000000) == 0);
9441
9442 /* Calculate the displacement between the PLT slot and the entry
9443 in the GOT. The offset accounts for the value produced by
9444 adding to pc in the penultimate instruction of the PLT stub. */
6034aab8 9445 got_displacement = (got_address
99059e56 9446 - (plt_address + htab->plt_entry_size));
b38cadfb
NC		 9447
9448 /* NaCl does not support interworking at all. */
9449 BFD_ASSERT (!elf32_arm_plt_needs_thumb_stub_p (info, arm_plt));
9450
9451 put_arm_insn (htab, output_bfd,
9452 elf32_arm_nacl_plt_entry[0]
9453 | arm_movw_immediate (got_displacement),
9454 ptr + 0);
9455 put_arm_insn (htab, output_bfd,
9456 elf32_arm_nacl_plt_entry[1]
9457 | arm_movt_immediate (got_displacement),
9458 ptr + 4);
9459 put_arm_insn (htab, output_bfd,
9460 elf32_arm_nacl_plt_entry[2],
9461 ptr + 8);
9462 put_arm_insn (htab, output_bfd,
9463 elf32_arm_nacl_plt_entry[3]
9464 | (tail_displacement & 0x00ffffff),
9465 ptr + 12);
9466 }
57460bcf
NC		 9467 else if (using_thumb_only (htab))
9468 {
eed94f8f 9469 /* PR ld/16017: Generate thumb only PLT entries. */
469a3493 9470 if (!using_thumb2 (htab))
eed94f8f
NC		 9471 {
9472 /* FIXME: We ought to be able to generate thumb-1 PLT
9473 instructions... */
9474 _bfd_error_handler (_("%B: Warning: thumb-1 mode PLT generation not currently supported"),
9475 output_bfd);
9476 return FALSE;
9477 }
57460bcf 9478
eed94f8f
NC		 9479 /* Calculate the displacement between the PLT slot and the entry in
9480 the GOT. The 12-byte offset accounts for the value produced by
9481 adding to pc in the 3rd instruction of the PLT stub. */
9482 got_displacement = got_address - (plt_address + 12);
9483
9484 /* As we are using 32 bit instructions we have to use 'put_arm_insn'
9485 instead of 'put_thumb_insn'. */
9486 put_arm_insn (htab, output_bfd,
9487 elf32_thumb2_plt_entry[0]
9488 | ((got_displacement & 0x000000ff) << 16)
9489 | ((got_displacement & 0x00000700) << 20)
9490 | ((got_displacement & 0x00000800) >> 1)
9491 | ((got_displacement & 0x0000f000) >> 12),
9492 ptr + 0);
9493 put_arm_insn (htab, output_bfd,
9494 elf32_thumb2_plt_entry[1]
9495 | ((got_displacement & 0x00ff0000) )
9496 | ((got_displacement & 0x07000000) << 4)
9497 | ((got_displacement & 0x08000000) >> 17)
9498 | ((got_displacement & 0xf0000000) >> 28),
9499 ptr + 4);
9500 put_arm_insn (htab, output_bfd,
9501 elf32_thumb2_plt_entry[2],
9502 ptr + 8);
9503 put_arm_insn (htab, output_bfd,
9504 elf32_thumb2_plt_entry[3],
9505 ptr + 12);
57460bcf 9506 }
34e77a92
RS		 9507 else
9508 {
9509 /* Calculate the displacement between the PLT slot and the
9510 entry in the GOT. The eight-byte offset accounts for the
9511 value produced by adding to pc in the first instruction
9512 of the PLT stub. */
9513 got_displacement = got_address - (plt_address + 8);
9514
34e77a92
RS		 9515 if (elf32_arm_plt_needs_thumb_stub_p (info, arm_plt))
9516 {
9517 put_thumb_insn (htab, output_bfd,
9518 elf32_arm_plt_thumb_stub[0], ptr - 4);
9519 put_thumb_insn (htab, output_bfd,
9520 elf32_arm_plt_thumb_stub[1], ptr - 2);
9521 }
9522
1db37fe6
YG		 9523 if (!elf32_arm_use_long_plt_entry)
9524 {
9525 BFD_ASSERT ((got_displacement & 0xf0000000) == 0);
9526
9527 put_arm_insn (htab, output_bfd,
9528 elf32_arm_plt_entry_short[0]
9529 | ((got_displacement & 0x0ff00000) >> 20),
9530 ptr + 0);
9531 put_arm_insn (htab, output_bfd,
9532 elf32_arm_plt_entry_short[1]
9533 | ((got_displacement & 0x000ff000) >> 12),
9534 ptr+ 4);
9535 put_arm_insn (htab, output_bfd,
9536 elf32_arm_plt_entry_short[2]
9537 | (got_displacement & 0x00000fff),
9538 ptr + 8);
34e77a92 9539#ifdef FOUR_WORD_PLT
1db37fe6 9540 bfd_put_32 (output_bfd, elf32_arm_plt_entry_short[3], ptr + 12);
34e77a92 9541#endif
1db37fe6
YG		 9542 }
9543 else
9544 {
9545 put_arm_insn (htab, output_bfd,
9546 elf32_arm_plt_entry_long[0]
9547 | ((got_displacement & 0xf0000000) >> 28),
9548 ptr + 0);
9549 put_arm_insn (htab, output_bfd,
9550 elf32_arm_plt_entry_long[1]
9551 | ((got_displacement & 0x0ff00000) >> 20),
9552 ptr + 4);
9553 put_arm_insn (htab, output_bfd,
9554 elf32_arm_plt_entry_long[2]
9555 | ((got_displacement & 0x000ff000) >> 12),
9556 ptr+ 8);
9557 put_arm_insn (htab, output_bfd,
9558 elf32_arm_plt_entry_long[3]
9559 | (got_displacement & 0x00000fff),
9560 ptr + 12);
9561 }
34e77a92
RS		 9562 }
9563
9564 /* Fill in the entry in the .rel(a).(i)plt section. */
9565 rel.r_offset = got_address;
9566 rel.r_addend = 0;
9567 if (dynindx == -1)
9568 {
9569 /* .igot.plt entries use IRELATIVE relocations against SYM_VALUE.
9570 The dynamic linker or static executable then calls SYM_VALUE
9571 to determine the correct run-time value of the .igot.plt entry. */
9572 rel.r_info = ELF32_R_INFO (0, R_ARM_IRELATIVE);
9573 initial_got_entry = sym_value;
9574 }
9575 else
9576 {
9577 rel.r_info = ELF32_R_INFO (dynindx, R_ARM_JUMP_SLOT);
9578 initial_got_entry = (splt->output_section->vma
9579 + splt->output_offset);
9580 }
9581
9582 /* Fill in the entry in the global offset table. */
9583 bfd_put_32 (output_bfd, initial_got_entry,
9584 sgot->contents + got_offset);
9585 }
9586
aba8c3de
WN		 9587 if (dynindx == -1)
9588 elf32_arm_add_dynreloc (output_bfd, info, srel, &rel);
9589 else
9590 {
9591 loc = srel->contents + plt_index * RELOC_SIZE (htab);
9592 SWAP_RELOC_OUT (htab) (output_bfd, &rel, loc);
9593 }
57460bcf
NC		 9594
9595 return TRUE;
34e77a92
RS		 9596}
9597
eb043451
PB		 9598/* Some relocations map to different relocations depending on the
9599 target. Return the real relocation. */
8029a119 9600
eb043451
PB		 9601static int
9602arm_real_reloc_type (struct elf32_arm_link_hash_table * globals,
9603 int r_type)
9604{
9605 switch (r_type)
9606 {
9607 case R_ARM_TARGET1:
9608 if (globals->target1_is_rel)
9609 return R_ARM_REL32;
9610 else
9611 return R_ARM_ABS32;
9612
9613 case R_ARM_TARGET2:
9614 return globals->target2_reloc;
9615
9616 default:
9617 return r_type;
9618 }
9619}
eb043451 9620
ba93b8ac
DJ		 9621/* Return the base VMA address which should be subtracted from real addresses
9622 when resolving @dtpoff relocation.
9623 This is PT_TLS segment p_vaddr. */
9624
9625static bfd_vma
9626dtpoff_base (struct bfd_link_info *info)
9627{
9628 /* If tls_sec is NULL, we should have signalled an error already. */
9629 if (elf_hash_table (info)->tls_sec == NULL)
9630 return 0;
9631 return elf_hash_table (info)->tls_sec->vma;
9632}
9633
9634/* Return the relocation value for @tpoff relocation
9635 if STT_TLS virtual address is ADDRESS. */
9636
9637static bfd_vma
9638tpoff (struct bfd_link_info *info, bfd_vma address)
9639{
9640 struct elf_link_hash_table *htab = elf_hash_table (info);
9641 bfd_vma base;
9642
9643 /* If tls_sec is NULL, we should have signalled an error already. */
9644 if (htab->tls_sec == NULL)
9645 return 0;
9646 base = align_power ((bfd_vma) TCB_SIZE, htab->tls_sec->alignment_power);
9647 return address - htab->tls_sec->vma + base;
9648}
9649
00a97672
RS		 9650/* Perform an R_ARM_ABS12 relocation on the field pointed to by DATA.
9651 VALUE is the relocation value. */
9652
9653static bfd_reloc_status_type
9654elf32_arm_abs12_reloc (bfd *abfd, void *data, bfd_vma value)
9655{
9656 if (value > 0xfff)
9657 return bfd_reloc_overflow;
9658
9659 value |= bfd_get_32 (abfd, data) & 0xfffff000;
9660 bfd_put_32 (abfd, value, data);
9661 return bfd_reloc_ok;
9662}
9663
0855e32b
NS		 9664/* Handle TLS relaxations. Relaxing is possible for symbols that use
9665 R_ARM_GOTDESC, R_ARM_{,THM_}TLS_CALL or
9666 R_ARM_{,THM_}TLS_DESCSEQ relocations, during a static link.
9667
9668 Return bfd_reloc_ok if we're done, bfd_reloc_continue if the caller
9669 is to then call final_link_relocate. Return other values in the
62672b10
NS		 9670 case of error.
9671
9672 FIXME:When --emit-relocs is in effect, we'll emit relocs describing
9673 the pre-relaxed code. It would be nice if the relocs were updated
9674 to match the optimization. */
0855e32b 9675
b38cadfb 9676static bfd_reloc_status_type
0855e32b 9677elf32_arm_tls_relax (struct elf32_arm_link_hash_table *globals,
b38cadfb 9678 bfd *input_bfd, asection *input_sec, bfd_byte *contents,
0855e32b
NS		 9679 Elf_Internal_Rela *rel, unsigned long is_local)
9680{
9681 unsigned long insn;
b38cadfb 9682
0855e32b
NS		 9683 switch (ELF32_R_TYPE (rel->r_info))
9684 {
9685 default:
9686 return bfd_reloc_notsupported;
b38cadfb 9687
0855e32b
NS		 9688 case R_ARM_TLS_GOTDESC:
9689 if (is_local)
9690 insn = 0;
9691 else
9692 {
9693 insn = bfd_get_32 (input_bfd, contents + rel->r_offset);
9694 if (insn & 1)
9695 insn -= 5; /* THUMB */
9696 else
9697 insn -= 8; /* ARM */
9698 }
9699 bfd_put_32 (input_bfd, insn, contents + rel->r_offset);
9700 return bfd_reloc_continue;
9701
9702 case R_ARM_THM_TLS_DESCSEQ:
9703 /* Thumb insn. */
9704 insn = bfd_get_16 (input_bfd, contents + rel->r_offset);
9705 if ((insn & 0xff78) == 0x4478) /* add rx, pc */
9706 {
9707 if (is_local)
9708 /* nop */
9709 bfd_put_16 (input_bfd, 0x46c0, contents + rel->r_offset);
9710 }
9711 else if ((insn & 0xffc0) == 0x6840) /* ldr rx,[ry,#4] */
9712 {
9713 if (is_local)
9714 /* nop */
9715 bfd_put_16 (input_bfd, 0x46c0, contents + rel->r_offset);
9716 else
9717 /* ldr rx,[ry] */
9718 bfd_put_16 (input_bfd, insn & 0xf83f, contents + rel->r_offset);
9719 }
9720 else if ((insn & 0xff87) == 0x4780) /* blx rx */
9721 {
9722 if (is_local)
9723 /* nop */
9724 bfd_put_16 (input_bfd, 0x46c0, contents + rel->r_offset);
9725 else
9726 /* mov r0, rx */
9727 bfd_put_16 (input_bfd, 0x4600 | (insn & 0x78),
9728 contents + rel->r_offset);
9729 }
9730 else
9731 {
9732 if ((insn & 0xf000) == 0xf000 || (insn & 0xf800) == 0xe800)
9733 /* It's a 32 bit instruction, fetch the rest of it for
9734 error generation. */
9735 insn = (insn << 16)
9736 | bfd_get_16 (input_bfd, contents + rel->r_offset + 2);
4eca0228 9737 _bfd_error_handler
0855e32b
NS		 9738 (_("%B(%A+0x%lx):unexpected Thumb instruction '0x%x' in TLS trampoline"),
9739 input_bfd, input_sec, (unsigned long)rel->r_offset, insn);
9740 return bfd_reloc_notsupported;
9741 }
9742 break;
b38cadfb 9743
0855e32b
NS		 9744 case R_ARM_TLS_DESCSEQ:
9745 /* arm insn. */
9746 insn = bfd_get_32 (input_bfd, contents + rel->r_offset);
9747 if ((insn & 0xffff0ff0) == 0xe08f0000) /* add rx,pc,ry */
9748 {
9749 if (is_local)
9750 /* mov rx, ry */
9751 bfd_put_32 (input_bfd, 0xe1a00000 | (insn & 0xffff),
9752 contents + rel->r_offset);
9753 }
9754 else if ((insn & 0xfff00fff) == 0xe5900004) /* ldr rx,[ry,#4]*/
9755 {
9756 if (is_local)
9757 /* nop */
9758 bfd_put_32 (input_bfd, 0xe1a00000, contents + rel->r_offset);
9759 else
9760 /* ldr rx,[ry] */
9761 bfd_put_32 (input_bfd, insn & 0xfffff000,
9762 contents + rel->r_offset);
9763 }
9764 else if ((insn & 0xfffffff0) == 0xe12fff30) /* blx rx */
9765 {
9766 if (is_local)
9767 /* nop */
9768 bfd_put_32 (input_bfd, 0xe1a00000, contents + rel->r_offset);
9769 else
9770 /* mov r0, rx */
9771 bfd_put_32 (input_bfd, 0xe1a00000 | (insn & 0xf),
9772 contents + rel->r_offset);
9773 }
9774 else
9775 {
4eca0228 9776 _bfd_error_handler
0855e32b
NS		 9777 (_("%B(%A+0x%lx):unexpected ARM instruction '0x%x' in TLS trampoline"),
9778 input_bfd, input_sec, (unsigned long)rel->r_offset, insn);
9779 return bfd_reloc_notsupported;
9780 }
9781 break;
9782
9783 case R_ARM_TLS_CALL:
9784 /* GD->IE relaxation, turn the instruction into 'nop' or
9785 'ldr r0, [pc,r0]' */
9786 insn = is_local ? 0xe1a00000 : 0xe79f0000;
9787 bfd_put_32 (input_bfd, insn, contents + rel->r_offset);
9788 break;
b38cadfb 9789
0855e32b 9790 case R_ARM_THM_TLS_CALL:
6a631e86 9791 /* GD->IE relaxation. */
0855e32b
NS		 9792 if (!is_local)
9793 /* add r0,pc; ldr r0, [r0] */
9794 insn = 0x44786800;
60a019a0 9795 else if (using_thumb2 (globals))
0855e32b
NS		 9796 /* nop.w */
9797 insn = 0xf3af8000;
9798 else
9799 /* nop; nop */
9800 insn = 0xbf00bf00;
b38cadfb 9801
0855e32b
NS		 9802 bfd_put_16 (input_bfd, insn >> 16, contents + rel->r_offset);
9803 bfd_put_16 (input_bfd, insn & 0xffff, contents + rel->r_offset + 2);
9804 break;
9805 }
9806 return bfd_reloc_ok;
9807}
9808
4962c51a
MS		 9809/* For a given value of n, calculate the value of G_n as required to
9810 deal with group relocations. We return it in the form of an
9811 encoded constant-and-rotation, together with the final residual. If n is
9812 specified as less than zero, then final_residual is filled with the
9813 input value and no further action is performed. */
9814
9815static bfd_vma
9816calculate_group_reloc_mask (bfd_vma value, int n, bfd_vma *final_residual)
9817{
9818 int current_n;
9819 bfd_vma g_n;
9820 bfd_vma encoded_g_n = 0;
9821 bfd_vma residual = value; /* Also known as Y_n. */
9822
9823 for (current_n = 0; current_n <= n; current_n++)
9824 {
9825 int shift;
9826
9827 /* Calculate which part of the value to mask. */
9828 if (residual == 0)
99059e56 9829 shift = 0;
4962c51a 9830 else
99059e56
RM		 9831 {
9832 int msb;
9833
9834 /* Determine the most significant bit in the residual and
9835 align the resulting value to a 2-bit boundary. */
9836 for (msb = 30; msb >= 0; msb -= 2)
9837 if (residual & (3 << msb))
9838 break;
9839
9840 /* The desired shift is now (msb - 6), or zero, whichever
9841 is the greater. */
9842 shift = msb - 6;
9843 if (shift < 0)
9844 shift = 0;
9845 }
4962c51a
MS		 9846
9847 /* Calculate g_n in 32-bit as well as encoded constant+rotation form. */
9848 g_n = residual & (0xff << shift);
9849 encoded_g_n = (g_n >> shift)
99059e56 9850 | ((g_n <= 0xff ? 0 : (32 - shift) / 2) << 8);
4962c51a
MS		 9851
9852 /* Calculate the residual for the next time around. */
9853 residual &= ~g_n;
9854 }
9855
9856 *final_residual = residual;
9857
9858 return encoded_g_n;
9859}
9860
9861/* Given an ARM instruction, determine whether it is an ADD or a SUB.
9862 Returns 1 if it is an ADD, -1 if it is a SUB, and 0 otherwise. */
906e58ca 9863
4962c51a 9864static int
906e58ca 9865identify_add_or_sub (bfd_vma insn)
4962c51a
MS		 9866{
9867 int opcode = insn & 0x1e00000;
9868
9869 if (opcode == 1 << 23) /* ADD */
9870 return 1;
9871
9872 if (opcode == 1 << 22) /* SUB */
9873 return -1;
9874
9875 return 0;
9876}
9877
252b5132 9878/* Perform a relocation as part of a final link. */
9b485d32 9879
252b5132 9880static bfd_reloc_status_type
57e8b36a
NC		 9881elf32_arm_final_link_relocate (reloc_howto_type * howto,
9882 bfd * input_bfd,
9883 bfd * output_bfd,
9884 asection * input_section,
9885 bfd_byte * contents,
9886 Elf_Internal_Rela * rel,
9887 bfd_vma value,
9888 struct bfd_link_info * info,
9889 asection * sym_sec,
9890 const char * sym_name,
34e77a92
RS		 9891 unsigned char st_type,
9892 enum arm_st_branch_type branch_type,
0945cdfd 9893 struct elf_link_hash_entry * h,
f2a9dd69 9894 bfd_boolean * unresolved_reloc_p,
8029a119 9895 char ** error_message)
252b5132
RH		 9896{
9897 unsigned long r_type = howto->type;
9898 unsigned long r_symndx;
9899 bfd_byte * hit_data = contents + rel->r_offset;
252b5132 9900 bfd_vma * local_got_offsets;
0855e32b 9901 bfd_vma * local_tlsdesc_gotents;
34e77a92
RS		 9902 asection * sgot;
9903 asection * splt;
252b5132 9904 asection * sreloc = NULL;
362d30a1 9905 asection * srelgot;
252b5132 9906 bfd_vma addend;
ba96a88f 9907 bfd_signed_vma signed_addend;
34e77a92
RS		 9908 unsigned char dynreloc_st_type;
9909 bfd_vma dynreloc_value;
ba96a88f 9910 struct elf32_arm_link_hash_table * globals;
34e77a92
RS		 9911 struct elf32_arm_link_hash_entry *eh;
9912 union gotplt_union *root_plt;
9913 struct arm_plt_info *arm_plt;
9914 bfd_vma plt_offset;
9915 bfd_vma gotplt_offset;
9916 bfd_boolean has_iplt_entry;
f21f3fe0 9917
9c504268 9918 globals = elf32_arm_hash_table (info);
4dfe6ac6
NC		 9919 if (globals == NULL)
9920 return bfd_reloc_notsupported;
9c504268 9921
0ffa91dd
NC		 9922 BFD_ASSERT (is_arm_elf (input_bfd));
9923
9924 /* Some relocation types map to different relocations depending on the
9c504268 9925 target. We pick the right one here. */
eb043451 9926 r_type = arm_real_reloc_type (globals, r_type);
0855e32b
NS		 9927
9928 /* It is possible to have linker relaxations on some TLS access
9929 models. Update our information here. */
9930 r_type = elf32_arm_tls_transition (info, r_type, h);
9931
eb043451
PB		 9932 if (r_type != howto->type)
9933 howto = elf32_arm_howto_from_type (r_type);
9c504268 9934
34e77a92 9935 eh = (struct elf32_arm_link_hash_entry *) h;
362d30a1 9936 sgot = globals->root.sgot;
252b5132 9937 local_got_offsets = elf_local_got_offsets (input_bfd);
0855e32b
NS		 9938 local_tlsdesc_gotents = elf32_arm_local_tlsdesc_gotent (input_bfd);
9939
34e77a92
RS		 9940 if (globals->root.dynamic_sections_created)
9941 srelgot = globals->root.srelgot;
9942 else
9943 srelgot = NULL;
9944
252b5132
RH		 9945 r_symndx = ELF32_R_SYM (rel->r_info);
9946
4e7fd91e 9947 if (globals->use_rel)
ba96a88f 9948 {
4e7fd91e
PB		 9949 addend = bfd_get_32 (input_bfd, hit_data) & howto->src_mask;
9950
9951 if (addend & ((howto->src_mask + 1) >> 1))
9952 {
9953 signed_addend = -1;
9954 signed_addend &= ~ howto->src_mask;
9955 signed_addend |= addend;
9956 }
9957 else
9958 signed_addend = addend;
ba96a88f
NC		 9959 }
9960 else
4e7fd91e 9961 addend = signed_addend = rel->r_addend;
f21f3fe0 9962
39f21624
NC		 9963 /* ST_BRANCH_TO_ARM is nonsense to thumb-only targets when we
9964 are resolving a function call relocation. */
9965 if (using_thumb_only (globals)
9966 && (r_type == R_ARM_THM_CALL
9967 || r_type == R_ARM_THM_JUMP24)
9968 && branch_type == ST_BRANCH_TO_ARM)
9969 branch_type = ST_BRANCH_TO_THUMB;
9970
34e77a92
RS		 9971 /* Record the symbol information that should be used in dynamic
9972 relocations. */
9973 dynreloc_st_type = st_type;
9974 dynreloc_value = value;
9975 if (branch_type == ST_BRANCH_TO_THUMB)
9976 dynreloc_value |= 1;
9977
9978 /* Find out whether the symbol has a PLT. Set ST_VALUE, BRANCH_TYPE and
9979 VALUE appropriately for relocations that we resolve at link time. */
9980 has_iplt_entry = FALSE;
4ba2ef8f
TP		 9981 if (elf32_arm_get_plt_info (input_bfd, globals, eh, r_symndx, &root_plt,
9982 &arm_plt)
34e77a92
RS		 9983 && root_plt->offset != (bfd_vma) -1)
9984 {
9985 plt_offset = root_plt->offset;
9986 gotplt_offset = arm_plt->got_offset;
9987
9988 if (h == NULL || eh->is_iplt)
9989 {
9990 has_iplt_entry = TRUE;
9991 splt = globals->root.iplt;
9992
9993 /* Populate .iplt entries here, because not all of them will
9994 be seen by finish_dynamic_symbol. The lower bit is set if
9995 we have already populated the entry. */
9996 if (plt_offset & 1)
9997 plt_offset--;
9998 else
9999 {
57460bcf
NC		 10000 if (elf32_arm_populate_plt_entry (output_bfd, info, root_plt, arm_plt,
10001 -1, dynreloc_value))
10002 root_plt->offset |= 1;
10003 else
10004 return bfd_reloc_notsupported;
34e77a92
RS		 10005 }
10006
10007 /* Static relocations always resolve to the .iplt entry. */
10008 st_type = STT_FUNC;
10009 value = (splt->output_section->vma
10010 + splt->output_offset
10011 + plt_offset);
10012 branch_type = ST_BRANCH_TO_ARM;
10013
10014 /* If there are non-call relocations that resolve to the .iplt
10015 entry, then all dynamic ones must too. */
10016 if (arm_plt->noncall_refcount != 0)
10017 {
10018 dynreloc_st_type = st_type;
10019 dynreloc_value = value;
10020 }
10021 }
10022 else
10023 /* We populate the .plt entry in finish_dynamic_symbol. */
10024 splt = globals->root.splt;
10025 }
10026 else
10027 {
10028 splt = NULL;
10029 plt_offset = (bfd_vma) -1;
10030 gotplt_offset = (bfd_vma) -1;
10031 }
10032
252b5132
RH		 10033 switch (r_type)
10034 {
10035 case R_ARM_NONE:
28a094c2
DJ		 10036 /* We don't need to find a value for this symbol. It's just a
10037 marker. */
10038 *unresolved_reloc_p = FALSE;
252b5132
RH		 10039 return bfd_reloc_ok;
10040
00a97672
RS		 10041 case R_ARM_ABS12:
10042 if (!globals->vxworks_p)
10043 return elf32_arm_abs12_reloc (input_bfd, hit_data, value + addend);
10044
252b5132
RH		 10045 case R_ARM_PC24:
10046 case R_ARM_ABS32:
bb224fc3 10047 case R_ARM_ABS32_NOI:
252b5132 10048 case R_ARM_REL32:
bb224fc3 10049 case R_ARM_REL32_NOI:
5b5bb741
PB		 10050 case R_ARM_CALL:
10051 case R_ARM_JUMP24:
dfc5f959 10052 case R_ARM_XPC25:
eb043451 10053 case R_ARM_PREL31:
7359ea65 10054 case R_ARM_PLT32:
7359ea65
DJ		 10055 /* Handle relocations which should use the PLT entry. ABS32/REL32
10056 will use the symbol's value, which may point to a PLT entry, but we
10057 don't need to handle that here. If we created a PLT entry, all
5fa9e92f
CL		 10058 branches in this object should go to it, except if the PLT is too
10059 far away, in which case a long branch stub should be inserted. */
bb224fc3 10060 if ((r_type != R_ARM_ABS32 && r_type != R_ARM_REL32
99059e56 10061 && r_type != R_ARM_ABS32_NOI && r_type != R_ARM_REL32_NOI
155d87d7
CL		 10062 && r_type != R_ARM_CALL
10063 && r_type != R_ARM_JUMP24
10064 && r_type != R_ARM_PLT32)
34e77a92 10065 && plt_offset != (bfd_vma) -1)
7359ea65 10066 {
34e77a92
RS		 10067 /* If we've created a .plt section, and assigned a PLT entry
10068 to this function, it must either be a STT_GNU_IFUNC reference
10069 or not be known to bind locally. In other cases, we should
10070 have cleared the PLT entry by now. */
10071 BFD_ASSERT (has_iplt_entry || !SYMBOL_CALLS_LOCAL (info, h));
7359ea65
DJ		 10072
10073 value = (splt->output_section->vma
10074 + splt->output_offset
34e77a92 10075 + plt_offset);
0945cdfd 10076 *unresolved_reloc_p = FALSE;
7359ea65
DJ		 10077 return _bfd_final_link_relocate (howto, input_bfd, input_section,
10078 contents, rel->r_offset, value,
00a97672 10079 rel->r_addend);
7359ea65
DJ		 10080 }
10081
67687978
PB		 10082 /* When generating a shared object or relocatable executable, these
10083 relocations are copied into the output file to be resolved at
10084 run time. */
0e1862bb
L		 10085 if ((bfd_link_pic (info)
10086 || globals->root.is_relocatable_executable)
7359ea65 10087 && (input_section->flags & SEC_ALLOC)
4dfe6ac6 10088 && !(globals->vxworks_p
3348747a
NS		 10089 && strcmp (input_section->output_section->name,
10090 ".tls_vars") == 0)
bb224fc3 10091 && ((r_type != R_ARM_REL32 && r_type != R_ARM_REL32_NOI)
ee06dc07 10092 || !SYMBOL_CALLS_LOCAL (info, h))
ca6b5f82
AM		 10093 && !(input_bfd == globals->stub_bfd
10094 && strstr (input_section->name, STUB_SUFFIX))
7359ea65
DJ		 10095 && (h == NULL
10096 || ELF_ST_VISIBILITY (h->other) == STV_DEFAULT
10097 || h->root.type != bfd_link_hash_undefweak)
10098 && r_type != R_ARM_PC24
5b5bb741
PB		 10099 && r_type != R_ARM_CALL
10100 && r_type != R_ARM_JUMP24
ee06dc07 10101 && r_type != R_ARM_PREL31
7359ea65 10102 && r_type != R_ARM_PLT32)
252b5132 10103 {
947216bf 10104 Elf_Internal_Rela outrel;
b34976b6 10105 bfd_boolean skip, relocate;
f21f3fe0 10106
52db4ec2
JW		 10107 if ((r_type == R_ARM_REL32 || r_type == R_ARM_REL32_NOI)
10108 && !h->def_regular)
10109 {
10110 char *v = _("shared object");
10111
0e1862bb 10112 if (bfd_link_executable (info))
52db4ec2
JW		 10113 v = _("PIE executable");
10114
4eca0228 10115 _bfd_error_handler
52db4ec2
JW		 10116 (_("%B: relocation %s against external or undefined symbol `%s'"
10117 " can not be used when making a %s; recompile with -fPIC"), input_bfd,
10118 elf32_arm_howto_table_1[r_type].name, h->root.root.string, v);
10119 return bfd_reloc_notsupported;
10120 }
10121
0945cdfd
DJ		 10122 *unresolved_reloc_p = FALSE;
10123
34e77a92 10124 if (sreloc == NULL && globals->root.dynamic_sections_created)
252b5132 10125 {
83bac4b0
NC		 10126 sreloc = _bfd_elf_get_dynamic_reloc_section (input_bfd, input_section,
10127 ! globals->use_rel);
f21f3fe0 10128
83bac4b0 10129 if (sreloc == NULL)
252b5132 10130 return bfd_reloc_notsupported;
252b5132 10131 }
f21f3fe0 10132
b34976b6
AM		 10133 skip = FALSE;
10134 relocate = FALSE;
f21f3fe0 10135
00a97672 10136 outrel.r_addend = addend;
c629eae0
JJ		 10137 outrel.r_offset =
10138 _bfd_elf_section_offset (output_bfd, info, input_section,
10139 rel->r_offset);
10140 if (outrel.r_offset == (bfd_vma) -1)
b34976b6 10141 skip = TRUE;
0bb2d96a 10142 else if (outrel.r_offset == (bfd_vma) -2)
b34976b6 10143 skip = TRUE, relocate = TRUE;
252b5132
RH		 10144 outrel.r_offset += (input_section->output_section->vma
10145 + input_section->output_offset);
f21f3fe0 10146
252b5132 10147 if (skip)
0bb2d96a 10148 memset (&outrel, 0, sizeof outrel);
5e681ec4
PB		 10149 else if (h != NULL
10150 && h->dynindx != -1
0e1862bb 10151 && (!bfd_link_pic (info)
a496fbc8 10152 || !SYMBOLIC_BIND (info, h)
f5385ebf 10153 || !h->def_regular))
5e681ec4 10154 outrel.r_info = ELF32_R_INFO (h->dynindx, r_type);
252b5132
RH		 10155 else
10156 {
a16385dc
MM		 10157 int symbol;
10158
5e681ec4 10159 /* This symbol is local, or marked to become local. */
34e77a92 10160 BFD_ASSERT (r_type == R_ARM_ABS32 || r_type == R_ARM_ABS32_NOI);
a16385dc 10161 if (globals->symbian_p)
6366ff1e 10162 {
74541ad4
AM		 10163 asection *osec;
10164
6366ff1e
MM		 10165 /* On Symbian OS, the data segment and text segement
10166 can be relocated independently. Therefore, we
10167 must indicate the segment to which this
10168 relocation is relative. The BPABI allows us to
10169 use any symbol in the right segment; we just use
10170 the section symbol as it is convenient. (We
10171 cannot use the symbol given by "h" directly as it
74541ad4
AM		 10172 will not appear in the dynamic symbol table.)
10173
10174 Note that the dynamic linker ignores the section
10175 symbol value, so we don't subtract osec->vma
10176 from the emitted reloc addend. */
10dbd1f3 10177 if (sym_sec)
74541ad4 10178 osec = sym_sec->output_section;
10dbd1f3 10179 else
74541ad4
AM		 10180 osec = input_section->output_section;
10181 symbol = elf_section_data (osec)->dynindx;
10182 if (symbol == 0)
10183 {
10184 struct elf_link_hash_table *htab = elf_hash_table (info);
10185
10186 if ((osec->flags & SEC_READONLY) == 0
10187 && htab->data_index_section != NULL)
10188 osec = htab->data_index_section;
10189 else
10190 osec = htab->text_index_section;
10191 symbol = elf_section_data (osec)->dynindx;
10192 }
6366ff1e
MM		 10193 BFD_ASSERT (symbol != 0);
10194 }
a16385dc
MM		 10195 else
10196 /* On SVR4-ish systems, the dynamic loader cannot
10197 relocate the text and data segments independently,
10198 so the symbol does not matter. */
10199 symbol = 0;
34e77a92
RS		 10200 if (dynreloc_st_type == STT_GNU_IFUNC)
10201 /* We have an STT_GNU_IFUNC symbol that doesn't resolve
10202 to the .iplt entry. Instead, every non-call reference
10203 must use an R_ARM_IRELATIVE relocation to obtain the
10204 correct run-time address. */
10205 outrel.r_info = ELF32_R_INFO (symbol, R_ARM_IRELATIVE);
10206 else
10207 outrel.r_info = ELF32_R_INFO (symbol, R_ARM_RELATIVE);
00a97672
RS		 10208 if (globals->use_rel)
10209 relocate = TRUE;
10210 else
34e77a92 10211 outrel.r_addend += dynreloc_value;
252b5132 10212 }
f21f3fe0 10213
47beaa6a 10214 elf32_arm_add_dynreloc (output_bfd, info, sreloc, &outrel);
9a5aca8c 10215
f21f3fe0 10216 /* If this reloc is against an external symbol, we do not want to
252b5132 10217 fiddle with the addend. Otherwise, we need to include the symbol
9b485d32 10218 value so that it becomes an addend for the dynamic reloc. */
252b5132
RH		 10219 if (! relocate)
10220 return bfd_reloc_ok;
9a5aca8c 10221
f21f3fe0 10222 return _bfd_final_link_relocate (howto, input_bfd, input_section,
34e77a92
RS		 10223 contents, rel->r_offset,
10224 dynreloc_value, (bfd_vma) 0);
252b5132
RH		 10225 }
10226 else switch (r_type)
10227 {
00a97672
RS		 10228 case R_ARM_ABS12:
10229 return elf32_arm_abs12_reloc (input_bfd, hit_data, value + addend);
10230
dfc5f959 10231 case R_ARM_XPC25: /* Arm BLX instruction. */
5b5bb741
PB		 10232 case R_ARM_CALL:
10233 case R_ARM_JUMP24:
8029a119 10234 case R_ARM_PC24: /* Arm B/BL instruction. */
7359ea65 10235 case R_ARM_PLT32:
906e58ca 10236 {
906e58ca
NC		 10237 struct elf32_arm_stub_hash_entry *stub_entry = NULL;
10238
dfc5f959 10239 if (r_type == R_ARM_XPC25)
252b5132 10240 {
dfc5f959
NC		 10241 /* Check for Arm calling Arm function. */
10242 /* FIXME: Should we translate the instruction into a BL
10243 instruction instead ? */
35fc36a8 10244 if (branch_type != ST_BRANCH_TO_THUMB)
4eca0228 10245 _bfd_error_handler
d003868e
AM		 10246 (_("\%B: Warning: Arm BLX instruction targets Arm function '%s'."),
10247 input_bfd,
10248 h ? h->root.root.string : "(local)");
dfc5f959 10249 }
155d87d7 10250 else if (r_type == R_ARM_PC24)
dfc5f959
NC		 10251 {
10252 /* Check for Arm calling Thumb function. */
35fc36a8 10253 if (branch_type == ST_BRANCH_TO_THUMB)
dfc5f959 10254 {
f2a9dd69
DJ		 10255 if (elf32_arm_to_thumb_stub (info, sym_name, input_bfd,
10256 output_bfd, input_section,
10257 hit_data, sym_sec, rel->r_offset,
10258 signed_addend, value,
10259 error_message))
10260 return bfd_reloc_ok;
10261 else
10262 return bfd_reloc_dangerous;
dfc5f959 10263 }
252b5132 10264 }
ba96a88f 10265
906e58ca 10266 /* Check if a stub has to be inserted because the
8029a119 10267 destination is too far or we are changing mode. */
155d87d7
CL		 10268 if ( r_type == R_ARM_CALL
10269 || r_type == R_ARM_JUMP24
10270 || r_type == R_ARM_PLT32)
906e58ca 10271 {
fe33d2fa
CL		 10272 enum elf32_arm_stub_type stub_type = arm_stub_none;
10273 struct elf32_arm_link_hash_entry *hash;
10274
10275 hash = (struct elf32_arm_link_hash_entry *) h;
10276 stub_type = arm_type_of_stub (info, input_section, rel,
34e77a92
RS		 10277 st_type, &branch_type,
10278 hash, value, sym_sec,
fe33d2fa 10279 input_bfd, sym_name);
5fa9e92f 10280
fe33d2fa 10281 if (stub_type != arm_stub_none)
906e58ca
NC		 10282 {
10283 /* The target is out of reach, so redirect the
10284 branch to the local stub for this function. */
906e58ca
NC		 10285 stub_entry = elf32_arm_get_stub_entry (input_section,
10286 sym_sec, h,
fe33d2fa
CL		 10287 rel, globals,
10288 stub_type);
9cd3e4e5
NC		 10289 {
10290 if (stub_entry != NULL)
10291 value = (stub_entry->stub_offset
10292 + stub_entry->stub_sec->output_offset
10293 + stub_entry->stub_sec->output_section->vma);
10294
10295 if (plt_offset != (bfd_vma) -1)
10296 *unresolved_reloc_p = FALSE;
10297 }
906e58ca 10298 }
fe33d2fa
CL		 10299 else
10300 {
10301 /* If the call goes through a PLT entry, make sure to
10302 check distance to the right destination address. */
34e77a92 10303 if (plt_offset != (bfd_vma) -1)
fe33d2fa
CL		 10304 {
10305 value = (splt->output_section->vma
10306 + splt->output_offset
34e77a92 10307 + plt_offset);
fe33d2fa
CL		 10308 *unresolved_reloc_p = FALSE;
10309 /* The PLT entry is in ARM mode, regardless of the
10310 target function. */
35fc36a8 10311 branch_type = ST_BRANCH_TO_ARM;
fe33d2fa
CL		 10312 }
10313 }
906e58ca
NC		 10314 }
10315
dea514f5
PB		 10316 /* The ARM ELF ABI says that this reloc is computed as: S - P + A
10317 where:
10318 S is the address of the symbol in the relocation.
10319 P is address of the instruction being relocated.
10320 A is the addend (extracted from the instruction) in bytes.
10321
10322 S is held in 'value'.
10323 P is the base address of the section containing the
10324 instruction plus the offset of the reloc into that
10325 section, ie:
10326 (input_section->output_section->vma +
10327 input_section->output_offset +
10328 rel->r_offset).
10329 A is the addend, converted into bytes, ie:
10330 (signed_addend * 4)
10331
10332 Note: None of these operations have knowledge of the pipeline
10333 size of the processor, thus it is up to the assembler to
10334 encode this information into the addend. */
10335 value -= (input_section->output_section->vma
10336 + input_section->output_offset);
10337 value -= rel->r_offset;
4e7fd91e
PB		 10338 if (globals->use_rel)
10339 value += (signed_addend << howto->size);
10340 else
10341 /* RELA addends do not have to be adjusted by howto->size. */
10342 value += signed_addend;
23080146 10343
dcb5e6e6
NC		 10344 signed_addend = value;
10345 signed_addend >>= howto->rightshift;
9a5aca8c 10346
5ab79981 10347 /* A branch to an undefined weak symbol is turned into a jump to
ffcb4889 10348 the next instruction unless a PLT entry will be created.
77b4f08f 10349 Do the same for local undefined symbols (but not for STN_UNDEF).
cd1dac3d
DG		 10350 The jump to the next instruction is optimized as a NOP depending
10351 on the architecture. */
ffcb4889 10352 if (h ? (h->root.type == bfd_link_hash_undefweak
34e77a92 10353 && plt_offset == (bfd_vma) -1)
77b4f08f 10354 : r_symndx != STN_UNDEF && bfd_is_und_section (sym_sec))
5ab79981 10355 {
cd1dac3d
DG		 10356 value = (bfd_get_32 (input_bfd, hit_data) & 0xf0000000);
10357
10358 if (arch_has_arm_nop (globals))
10359 value |= 0x0320f000;
10360 else
10361 value |= 0x01a00000; /* Using pre-UAL nop: mov r0, r0. */
5ab79981
PB		 10362 }
10363 else
59f2c4e7 10364 {
9b485d32 10365 /* Perform a signed range check. */
dcb5e6e6 10366 if ( signed_addend > ((bfd_signed_vma) (howto->dst_mask >> 1))
59f2c4e7
NC		 10367 || signed_addend < - ((bfd_signed_vma) ((howto->dst_mask + 1) >> 1)))
10368 return bfd_reloc_overflow;
9a5aca8c 10369
5ab79981 10370 addend = (value & 2);
39b41c9c 10371
5ab79981
PB		 10372 value = (signed_addend & howto->dst_mask)
10373 | (bfd_get_32 (input_bfd, hit_data) & (~ howto->dst_mask));
39b41c9c 10374
5ab79981
PB		 10375 if (r_type == R_ARM_CALL)
10376 {
155d87d7 10377 /* Set the H bit in the BLX instruction. */
35fc36a8 10378 if (branch_type == ST_BRANCH_TO_THUMB)
155d87d7
CL		 10379 {
10380 if (addend)
10381 value |= (1 << 24);
10382 else
10383 value &= ~(bfd_vma)(1 << 24);
10384 }
10385
5ab79981 10386 /* Select the correct instruction (BL or BLX). */
906e58ca 10387 /* Only if we are not handling a BL to a stub. In this
8029a119 10388 case, mode switching is performed by the stub. */
35fc36a8 10389 if (branch_type == ST_BRANCH_TO_THUMB && !stub_entry)
5ab79981 10390 value |= (1 << 28);
63e1a0fc 10391 else if (stub_entry || branch_type != ST_BRANCH_UNKNOWN)
5ab79981
PB		 10392 {
10393 value &= ~(bfd_vma)(1 << 28);
10394 value |= (1 << 24);
10395 }
39b41c9c
PB		 10396 }
10397 }
906e58ca 10398 }
252b5132 10399 break;
f21f3fe0 10400
252b5132
RH		 10401 case R_ARM_ABS32:
10402 value += addend;
35fc36a8 10403 if (branch_type == ST_BRANCH_TO_THUMB)
252b5132
RH		 10404 value |= 1;
10405 break;
f21f3fe0 10406
bb224fc3
MS		 10407 case R_ARM_ABS32_NOI:
10408 value += addend;
10409 break;
10410
252b5132 10411 case R_ARM_REL32:
a8bc6c78 10412 value += addend;
35fc36a8 10413 if (branch_type == ST_BRANCH_TO_THUMB)
a8bc6c78 10414 value |= 1;
252b5132 10415 value -= (input_section->output_section->vma
62efb346 10416 + input_section->output_offset + rel->r_offset);
252b5132 10417 break;
eb043451 10418
bb224fc3
MS		 10419 case R_ARM_REL32_NOI:
10420 value += addend;
10421 value -= (input_section->output_section->vma
10422 + input_section->output_offset + rel->r_offset);
10423 break;
10424
eb043451
PB		 10425 case R_ARM_PREL31:
10426 value -= (input_section->output_section->vma
10427 + input_section->output_offset + rel->r_offset);
10428 value += signed_addend;
10429 if (! h || h->root.type != bfd_link_hash_undefweak)
10430 {
8029a119 10431 /* Check for overflow. */
eb043451
PB		 10432 if ((value ^ (value >> 1)) & (1 << 30))
10433 return bfd_reloc_overflow;
10434 }
10435 value &= 0x7fffffff;
10436 value |= (bfd_get_32 (input_bfd, hit_data) & 0x80000000);
35fc36a8 10437 if (branch_type == ST_BRANCH_TO_THUMB)
eb043451
PB		 10438 value |= 1;
10439 break;
252b5132 10440 }
f21f3fe0 10441
252b5132
RH		 10442 bfd_put_32 (input_bfd, value, hit_data);
10443 return bfd_reloc_ok;
10444
10445 case R_ARM_ABS8:
fd0fd00c
MJ		 10446 /* PR 16202: Refectch the addend using the correct size. */
10447 if (globals->use_rel)
10448 addend = bfd_get_8 (input_bfd, hit_data);
252b5132 10449 value += addend;
4e67d4ca
DG		 10450
10451 /* There is no way to tell whether the user intended to use a signed or
10452 unsigned addend. When checking for overflow we accept either,
10453 as specified by the AAELF. */
10454 if ((long) value > 0xff || (long) value < -0x80)
252b5132
RH		 10455 return bfd_reloc_overflow;
10456
10457 bfd_put_8 (input_bfd, value, hit_data);
10458 return bfd_reloc_ok;
10459
10460 case R_ARM_ABS16:
fd0fd00c
MJ		 10461 /* PR 16202: Refectch the addend using the correct size. */
10462 if (globals->use_rel)
10463 addend = bfd_get_16 (input_bfd, hit_data);
252b5132
RH		 10464 value += addend;
10465
4e67d4ca
DG		 10466 /* See comment for R_ARM_ABS8. */
10467 if ((long) value > 0xffff || (long) value < -0x8000)
252b5132
RH		 10468 return bfd_reloc_overflow;
10469
10470 bfd_put_16 (input_bfd, value, hit_data);
10471 return bfd_reloc_ok;
10472
252b5132 10473 case R_ARM_THM_ABS5:
9b485d32 10474 /* Support ldr and str instructions for the thumb. */
4e7fd91e
PB		 10475 if (globals->use_rel)
10476 {
10477 /* Need to refetch addend. */
10478 addend = bfd_get_16 (input_bfd, hit_data) & howto->src_mask;
10479 /* ??? Need to determine shift amount from operand size. */
10480 addend >>= howto->rightshift;
10481 }
252b5132
RH		 10482 value += addend;
10483
10484 /* ??? Isn't value unsigned? */
10485 if ((long) value > 0x1f || (long) value < -0x10)
10486 return bfd_reloc_overflow;
10487
10488 /* ??? Value needs to be properly shifted into place first. */
10489 value |= bfd_get_16 (input_bfd, hit_data) & 0xf83f;
10490 bfd_put_16 (input_bfd, value, hit_data);
10491 return bfd_reloc_ok;
10492
2cab6cc3
MS		 10493 case R_ARM_THM_ALU_PREL_11_0:
10494 /* Corresponds to: addw.w reg, pc, #offset (and similarly for subw). */
10495 {
10496 bfd_vma insn;
10497 bfd_signed_vma relocation;
10498
10499 insn = (bfd_get_16 (input_bfd, hit_data) << 16)
99059e56 10500 | bfd_get_16 (input_bfd, hit_data + 2);
2cab6cc3 10501
99059e56
RM		 10502 if (globals->use_rel)
10503 {
10504 signed_addend = (insn & 0xff) | ((insn & 0x7000) >> 4)
10505 | ((insn & (1 << 26)) >> 15);
10506 if (insn & 0xf00000)
10507 signed_addend = -signed_addend;
10508 }
2cab6cc3
MS		 10509
10510 relocation = value + signed_addend;
79f08007 10511 relocation -= Pa (input_section->output_section->vma
99059e56
RM		 10512 + input_section->output_offset
10513 + rel->r_offset);
2cab6cc3 10514
b6518b38 10515 value = relocation;
2cab6cc3 10516
99059e56
RM		 10517 if (value >= 0x1000)
10518 return bfd_reloc_overflow;
2cab6cc3
MS		 10519
10520 insn = (insn & 0xfb0f8f00) | (value & 0xff)
99059e56
RM		 10521 | ((value & 0x700) << 4)
10522 | ((value & 0x800) << 15);
10523 if (relocation < 0)
10524 insn |= 0xa00000;
2cab6cc3
MS		 10525
10526 bfd_put_16 (input_bfd, insn >> 16, hit_data);
10527 bfd_put_16 (input_bfd, insn & 0xffff, hit_data + 2);
10528
99059e56 10529 return bfd_reloc_ok;
2cab6cc3
MS		 10530 }
10531
e1ec24c6
NC		 10532 case R_ARM_THM_PC8:
10533 /* PR 10073: This reloc is not generated by the GNU toolchain,
10534 but it is supported for compatibility with third party libraries
10535 generated by other compilers, specifically the ARM/IAR. */
10536 {
10537 bfd_vma insn;
10538 bfd_signed_vma relocation;
10539
10540 insn = bfd_get_16 (input_bfd, hit_data);
10541
99059e56 10542 if (globals->use_rel)
79f08007 10543 addend = ((((insn & 0x00ff) << 2) + 4) & 0x3ff) -4;
e1ec24c6
NC		 10544
10545 relocation = value + addend;
79f08007 10546 relocation -= Pa (input_section->output_section->vma
99059e56
RM		 10547 + input_section->output_offset
10548 + rel->r_offset);
e1ec24c6 10549
b6518b38 10550 value = relocation;
e1ec24c6
NC		 10551
10552 /* We do not check for overflow of this reloc. Although strictly
10553 speaking this is incorrect, it appears to be necessary in order
10554 to work with IAR generated relocs. Since GCC and GAS do not
10555 generate R_ARM_THM_PC8 relocs, the lack of a check should not be
10556 a problem for them. */
10557 value &= 0x3fc;
10558
10559 insn = (insn & 0xff00) | (value >> 2);
10560
10561 bfd_put_16 (input_bfd, insn, hit_data);
10562
99059e56 10563 return bfd_reloc_ok;
e1ec24c6
NC		 10564 }
10565
2cab6cc3
MS		 10566 case R_ARM_THM_PC12:
10567 /* Corresponds to: ldr.w reg, [pc, #offset]. */
10568 {
10569 bfd_vma insn;
10570 bfd_signed_vma relocation;
10571
10572 insn = (bfd_get_16 (input_bfd, hit_data) << 16)
99059e56 10573 | bfd_get_16 (input_bfd, hit_data + 2);
2cab6cc3 10574
99059e56
RM		 10575 if (globals->use_rel)
10576 {
10577 signed_addend = insn & 0xfff;
10578 if (!(insn & (1 << 23)))
10579 signed_addend = -signed_addend;
10580 }
2cab6cc3
MS		 10581
10582 relocation = value + signed_addend;
79f08007 10583 relocation -= Pa (input_section->output_section->vma
99059e56
RM		 10584 + input_section->output_offset
10585 + rel->r_offset);
2cab6cc3 10586
b6518b38 10587 value = relocation;
2cab6cc3 10588
99059e56
RM		 10589 if (value >= 0x1000)
10590 return bfd_reloc_overflow;
2cab6cc3
MS		 10591
10592 insn = (insn & 0xff7ff000) | value;
99059e56
RM		 10593 if (relocation >= 0)
10594 insn |= (1 << 23);
2cab6cc3
MS		 10595
10596 bfd_put_16 (input_bfd, insn >> 16, hit_data);
10597 bfd_put_16 (input_bfd, insn & 0xffff, hit_data + 2);
10598
99059e56 10599 return bfd_reloc_ok;
2cab6cc3
MS		 10600 }
10601
dfc5f959 10602 case R_ARM_THM_XPC22:
c19d1205 10603 case R_ARM_THM_CALL:
bd97cb95 10604 case R_ARM_THM_JUMP24:
dfc5f959 10605 /* Thumb BL (branch long instruction). */
252b5132 10606 {
b34976b6 10607 bfd_vma relocation;
99059e56 10608 bfd_vma reloc_sign;
b34976b6
AM		 10609 bfd_boolean overflow = FALSE;
10610 bfd_vma upper_insn = bfd_get_16 (input_bfd, hit_data);
10611 bfd_vma lower_insn = bfd_get_16 (input_bfd, hit_data + 2);
e95de063
MS		 10612 bfd_signed_vma reloc_signed_max;
10613 bfd_signed_vma reloc_signed_min;
b34976b6 10614 bfd_vma check;
252b5132 10615 bfd_signed_vma signed_check;
e95de063 10616 int bitsize;
cd1dac3d 10617 const int thumb2 = using_thumb2 (globals);
5e866f5a 10618 const int thumb2_bl = using_thumb2_bl (globals);
252b5132 10619
5ab79981 10620 /* A branch to an undefined weak symbol is turned into a jump to
cd1dac3d
DG		 10621 the next instruction unless a PLT entry will be created.
10622 The jump to the next instruction is optimized as a NOP.W for
10623 Thumb-2 enabled architectures. */
19540007 10624 if (h && h->root.type == bfd_link_hash_undefweak
34e77a92 10625 && plt_offset == (bfd_vma) -1)
5ab79981 10626 {
60a019a0 10627 if (thumb2)
cd1dac3d
DG		 10628 {
10629 bfd_put_16 (input_bfd, 0xf3af, hit_data);
10630 bfd_put_16 (input_bfd, 0x8000, hit_data + 2);
10631 }
10632 else
10633 {
10634 bfd_put_16 (input_bfd, 0xe000, hit_data);
10635 bfd_put_16 (input_bfd, 0xbf00, hit_data + 2);
10636 }
5ab79981
PB		 10637 return bfd_reloc_ok;
10638 }
10639
e95de063 10640 /* Fetch the addend. We use the Thumb-2 encoding (backwards compatible
99059e56 10641 with Thumb-1) involving the J1 and J2 bits. */
4e7fd91e
PB		 10642 if (globals->use_rel)
10643 {
99059e56
RM		 10644 bfd_vma s = (upper_insn & (1 << 10)) >> 10;
10645 bfd_vma upper = upper_insn & 0x3ff;
10646 bfd_vma lower = lower_insn & 0x7ff;
e95de063
MS		 10647 bfd_vma j1 = (lower_insn & (1 << 13)) >> 13;
10648 bfd_vma j2 = (lower_insn & (1 << 11)) >> 11;
99059e56
RM		 10649 bfd_vma i1 = j1 ^ s ? 0 : 1;
10650 bfd_vma i2 = j2 ^ s ? 0 : 1;
e95de063 10651
99059e56
RM		 10652 addend = (i1 << 23) | (i2 << 22) | (upper << 12) | (lower << 1);
10653 /* Sign extend. */
10654 addend = (addend | ((s ? 0 : 1) << 24)) - (1 << 24);
e95de063 10655
4e7fd91e
PB		 10656 signed_addend = addend;
10657 }
cb1afa5c 10658
dfc5f959
NC		 10659 if (r_type == R_ARM_THM_XPC22)
10660 {
10661 /* Check for Thumb to Thumb call. */
10662 /* FIXME: Should we translate the instruction into a BL
10663 instruction instead ? */
35fc36a8 10664 if (branch_type == ST_BRANCH_TO_THUMB)
4eca0228 10665 _bfd_error_handler
d003868e
AM		 10666 (_("%B: Warning: Thumb BLX instruction targets thumb function '%s'."),
10667 input_bfd,
10668 h ? h->root.root.string : "(local)");
dfc5f959
NC		 10669 }
10670 else
252b5132 10671 {
dfc5f959
NC		 10672 /* If it is not a call to Thumb, assume call to Arm.
10673 If it is a call relative to a section name, then it is not a
b7693d02
DJ		 10674 function call at all, but rather a long jump. Calls through
10675 the PLT do not require stubs. */
34e77a92 10676 if (branch_type == ST_BRANCH_TO_ARM && plt_offset == (bfd_vma) -1)
dfc5f959 10677 {
bd97cb95 10678 if (globals->use_blx && r_type == R_ARM_THM_CALL)
39b41c9c
PB		 10679 {
10680 /* Convert BL to BLX. */
10681 lower_insn = (lower_insn & ~0x1000) | 0x0800;
10682 }
155d87d7
CL		 10683 else if (( r_type != R_ARM_THM_CALL)
10684 && (r_type != R_ARM_THM_JUMP24))
8029a119
NC		 10685 {
10686 if (elf32_thumb_to_arm_stub
10687 (info, sym_name, input_bfd, output_bfd, input_section,
10688 hit_data, sym_sec, rel->r_offset, signed_addend, value,
10689 error_message))
10690 return bfd_reloc_ok;
10691 else
10692 return bfd_reloc_dangerous;
10693 }
da5938a2 10694 }
35fc36a8
RS		 10695 else if (branch_type == ST_BRANCH_TO_THUMB
10696 && globals->use_blx
bd97cb95 10697 && r_type == R_ARM_THM_CALL)
39b41c9c
PB		 10698 {
10699 /* Make sure this is a BL. */
10700 lower_insn |= 0x1800;
10701 }
252b5132 10702 }
f21f3fe0 10703
fe33d2fa 10704 enum elf32_arm_stub_type stub_type = arm_stub_none;
155d87d7 10705 if (r_type == R_ARM_THM_CALL || r_type == R_ARM_THM_JUMP24)
906e58ca
NC		 10706 {
10707 /* Check if a stub has to be inserted because the destination
8029a119 10708 is too far. */
fe33d2fa
CL		 10709 struct elf32_arm_stub_hash_entry *stub_entry;
10710 struct elf32_arm_link_hash_entry *hash;
10711
10712 hash = (struct elf32_arm_link_hash_entry *) h;
10713
10714 stub_type = arm_type_of_stub (info, input_section, rel,
34e77a92
RS		 10715 st_type, &branch_type,
10716 hash, value, sym_sec,
fe33d2fa
CL		 10717 input_bfd, sym_name);
10718
10719 if (stub_type != arm_stub_none)
906e58ca
NC		 10720 {
10721 /* The target is out of reach or we are changing modes, so
10722 redirect the branch to the local stub for this
10723 function. */
10724 stub_entry = elf32_arm_get_stub_entry (input_section,
10725 sym_sec, h,
fe33d2fa
CL		 10726 rel, globals,
10727 stub_type);
906e58ca 10728 if (stub_entry != NULL)
9cd3e4e5
NC		 10729 {
10730 value = (stub_entry->stub_offset
10731 + stub_entry->stub_sec->output_offset
10732 + stub_entry->stub_sec->output_section->vma);
10733
10734 if (plt_offset != (bfd_vma) -1)
10735 *unresolved_reloc_p = FALSE;
10736 }
906e58ca 10737
f4ac8484 10738 /* If this call becomes a call to Arm, force BLX. */
155d87d7 10739 if (globals->use_blx && (r_type == R_ARM_THM_CALL))
f4ac8484
DJ		 10740 {
10741 if ((stub_entry
10742 && !arm_stub_is_thumb (stub_entry->stub_type))
35fc36a8 10743 || branch_type != ST_BRANCH_TO_THUMB)
f4ac8484
DJ		 10744 lower_insn = (lower_insn & ~0x1000) | 0x0800;
10745 }
906e58ca
NC		 10746 }
10747 }
10748
fe33d2fa 10749 /* Handle calls via the PLT. */
34e77a92 10750 if (stub_type == arm_stub_none && plt_offset != (bfd_vma) -1)
fe33d2fa
CL		 10751 {
10752 value = (splt->output_section->vma
10753 + splt->output_offset
34e77a92 10754 + plt_offset);
fe33d2fa 10755
eed94f8f
NC		 10756 if (globals->use_blx
10757 && r_type == R_ARM_THM_CALL
10758 && ! using_thumb_only (globals))
fe33d2fa
CL		 10759 {
10760 /* If the Thumb BLX instruction is available, convert
10761 the BL to a BLX instruction to call the ARM-mode
10762 PLT entry. */
10763 lower_insn = (lower_insn & ~0x1000) | 0x0800;
35fc36a8 10764 branch_type = ST_BRANCH_TO_ARM;
fe33d2fa
CL		 10765 }
10766 else
10767 {
eed94f8f
NC		 10768 if (! using_thumb_only (globals))
10769 /* Target the Thumb stub before the ARM PLT entry. */
10770 value -= PLT_THUMB_STUB_SIZE;
35fc36a8 10771 branch_type = ST_BRANCH_TO_THUMB;
fe33d2fa
CL		 10772 }
10773 *unresolved_reloc_p = FALSE;
10774 }
10775
ba96a88f 10776 relocation = value + signed_addend;
f21f3fe0 10777
252b5132 10778 relocation -= (input_section->output_section->vma
ba96a88f
NC		 10779 + input_section->output_offset
10780 + rel->r_offset);
9a5aca8c 10781
252b5132
RH		 10782 check = relocation >> howto->rightshift;
10783
10784 /* If this is a signed value, the rightshift just dropped
10785 leading 1 bits (assuming twos complement). */
10786 if ((bfd_signed_vma) relocation >= 0)
10787 signed_check = check;
10788 else
10789 signed_check = check | ~((bfd_vma) -1 >> howto->rightshift);
10790
e95de063
MS		 10791 /* Calculate the permissable maximum and minimum values for
10792 this relocation according to whether we're relocating for
10793 Thumb-2 or not. */
10794 bitsize = howto->bitsize;
5e866f5a 10795 if (!thumb2_bl)
e95de063 10796 bitsize -= 2;
f6ebfac0 10797 reloc_signed_max = (1 << (bitsize - 1)) - 1;
e95de063
MS		 10798 reloc_signed_min = ~reloc_signed_max;
10799
252b5132 10800 /* Assumes two's complement. */
ba96a88f 10801 if (signed_check > reloc_signed_max || signed_check < reloc_signed_min)
b34976b6 10802 overflow = TRUE;
252b5132 10803
bd97cb95 10804 if ((lower_insn & 0x5000) == 0x4000)
c62e1cc3
NC		 10805 /* For a BLX instruction, make sure that the relocation is rounded up
10806 to a word boundary. This follows the semantics of the instruction
10807 which specifies that bit 1 of the target address will come from bit
10808 1 of the base address. */
10809 relocation = (relocation + 2) & ~ 3;
cb1afa5c 10810
e95de063
MS		 10811 /* Put RELOCATION back into the insn. Assumes two's complement.
10812 We use the Thumb-2 encoding, which is safe even if dealing with
10813 a Thumb-1 instruction by virtue of our overflow check above. */
99059e56 10814 reloc_sign = (signed_check < 0) ? 1 : 0;
e95de063 10815 upper_insn = (upper_insn & ~(bfd_vma) 0x7ff)
99059e56
RM		 10816 | ((relocation >> 12) & 0x3ff)
10817 | (reloc_sign << 10);
906e58ca 10818 lower_insn = (lower_insn & ~(bfd_vma) 0x2fff)
99059e56
RM		 10819 | (((!((relocation >> 23) & 1)) ^ reloc_sign) << 13)
10820 | (((!((relocation >> 22) & 1)) ^ reloc_sign) << 11)
10821 | ((relocation >> 1) & 0x7ff);
c62e1cc3 10822
252b5132
RH		 10823 /* Put the relocated value back in the object file: */
10824 bfd_put_16 (input_bfd, upper_insn, hit_data);
10825 bfd_put_16 (input_bfd, lower_insn, hit_data + 2);
10826
10827 return (overflow ? bfd_reloc_overflow : bfd_reloc_ok);
10828 }
10829 break;
10830
c19d1205
ZW		 10831 case R_ARM_THM_JUMP19:
10832 /* Thumb32 conditional branch instruction. */
10833 {
10834 bfd_vma relocation;
10835 bfd_boolean overflow = FALSE;
10836 bfd_vma upper_insn = bfd_get_16 (input_bfd, hit_data);
10837 bfd_vma lower_insn = bfd_get_16 (input_bfd, hit_data + 2);
a00a1f35
MS		 10838 bfd_signed_vma reloc_signed_max = 0xffffe;
10839 bfd_signed_vma reloc_signed_min = -0x100000;
c19d1205 10840 bfd_signed_vma signed_check;
c5423981
TG		 10841 enum elf32_arm_stub_type stub_type = arm_stub_none;
10842 struct elf32_arm_stub_hash_entry *stub_entry;
10843 struct elf32_arm_link_hash_entry *hash;
c19d1205
ZW		 10844
10845 /* Need to refetch the addend, reconstruct the top three bits,
10846 and squish the two 11 bit pieces together. */
10847 if (globals->use_rel)
10848 {
10849 bfd_vma S = (upper_insn & 0x0400) >> 10;
a00a1f35 10850 bfd_vma upper = (upper_insn & 0x003f);
c19d1205
ZW		 10851 bfd_vma J1 = (lower_insn & 0x2000) >> 13;
10852 bfd_vma J2 = (lower_insn & 0x0800) >> 11;
10853 bfd_vma lower = (lower_insn & 0x07ff);
10854
a00a1f35
MS		 10855 upper |= J1 << 6;
10856 upper |= J2 << 7;
10857 upper |= (!S) << 8;
c19d1205
ZW		 10858 upper -= 0x0100; /* Sign extend. */
10859
10860 addend = (upper << 12) | (lower << 1);
10861 signed_addend = addend;
10862 }
10863
bd97cb95 10864 /* Handle calls via the PLT. */
34e77a92 10865 if (plt_offset != (bfd_vma) -1)
bd97cb95
DJ		 10866 {
10867 value = (splt->output_section->vma
10868 + splt->output_offset
34e77a92 10869 + plt_offset);
bd97cb95
DJ		 10870 /* Target the Thumb stub before the ARM PLT entry. */
10871 value -= PLT_THUMB_STUB_SIZE;
10872 *unresolved_reloc_p = FALSE;
10873 }
10874
c5423981
TG		 10875 hash = (struct elf32_arm_link_hash_entry *)h;
10876
10877 stub_type = arm_type_of_stub (info, input_section, rel,
10878 st_type, &branch_type,
10879 hash, value, sym_sec,
10880 input_bfd, sym_name);
10881 if (stub_type != arm_stub_none)
10882 {
10883 stub_entry = elf32_arm_get_stub_entry (input_section,
10884 sym_sec, h,
10885 rel, globals,
10886 stub_type);
10887 if (stub_entry != NULL)
10888 {
10889 value = (stub_entry->stub_offset
10890 + stub_entry->stub_sec->output_offset
10891 + stub_entry->stub_sec->output_section->vma);
10892 }
10893 }
c19d1205 10894
99059e56 10895 relocation = value + signed_addend;
c19d1205
ZW		 10896 relocation -= (input_section->output_section->vma
10897 + input_section->output_offset
10898 + rel->r_offset);
a00a1f35 10899 signed_check = (bfd_signed_vma) relocation;
c19d1205 10900
c19d1205
ZW		 10901 if (signed_check > reloc_signed_max || signed_check < reloc_signed_min)
10902 overflow = TRUE;
10903
10904 /* Put RELOCATION back into the insn. */
10905 {
10906 bfd_vma S = (relocation & 0x00100000) >> 20;
10907 bfd_vma J2 = (relocation & 0x00080000) >> 19;
10908 bfd_vma J1 = (relocation & 0x00040000) >> 18;
10909 bfd_vma hi = (relocation & 0x0003f000) >> 12;
10910 bfd_vma lo = (relocation & 0x00000ffe) >> 1;
10911
a00a1f35 10912 upper_insn = (upper_insn & 0xfbc0) | (S << 10) | hi;
c19d1205
ZW		 10913 lower_insn = (lower_insn & 0xd000) | (J1 << 13) | (J2 << 11) | lo;
10914 }
10915
10916 /* Put the relocated value back in the object file: */
10917 bfd_put_16 (input_bfd, upper_insn, hit_data);
10918 bfd_put_16 (input_bfd, lower_insn, hit_data + 2);
10919
10920 return (overflow ? bfd_reloc_overflow : bfd_reloc_ok);
10921 }
10922
10923 case R_ARM_THM_JUMP11:
10924 case R_ARM_THM_JUMP8:
10925 case R_ARM_THM_JUMP6:
51c5503b
NC		 10926 /* Thumb B (branch) instruction). */
10927 {
6cf9e9fe 10928 bfd_signed_vma relocation;
51c5503b
NC		 10929 bfd_signed_vma reloc_signed_max = (1 << (howto->bitsize - 1)) - 1;
10930 bfd_signed_vma reloc_signed_min = ~ reloc_signed_max;
51c5503b
NC		 10931 bfd_signed_vma signed_check;
10932
c19d1205
ZW		 10933 /* CZB cannot jump backward. */
10934 if (r_type == R_ARM_THM_JUMP6)
10935 reloc_signed_min = 0;
10936
4e7fd91e 10937 if (globals->use_rel)
6cf9e9fe 10938 {
4e7fd91e
PB		 10939 /* Need to refetch addend. */
10940 addend = bfd_get_16 (input_bfd, hit_data) & howto->src_mask;
10941 if (addend & ((howto->src_mask + 1) >> 1))
10942 {
10943 signed_addend = -1;
10944 signed_addend &= ~ howto->src_mask;
10945 signed_addend |= addend;
10946 }
10947 else
10948 signed_addend = addend;
10949 /* The value in the insn has been right shifted. We need to
10950 undo this, so that we can perform the address calculation
10951 in terms of bytes. */
10952 signed_addend <<= howto->rightshift;
6cf9e9fe 10953 }
6cf9e9fe 10954 relocation = value + signed_addend;
51c5503b
NC		 10955
10956 relocation -= (input_section->output_section->vma
10957 + input_section->output_offset
10958 + rel->r_offset);
10959
6cf9e9fe
NC		 10960 relocation >>= howto->rightshift;
10961 signed_check = relocation;
c19d1205
ZW		 10962
10963 if (r_type == R_ARM_THM_JUMP6)
10964 relocation = ((relocation & 0x0020) << 4) | ((relocation & 0x001f) << 3);
10965 else
10966 relocation &= howto->dst_mask;
51c5503b 10967 relocation |= (bfd_get_16 (input_bfd, hit_data) & (~ howto->dst_mask));
cedb70c5 10968
51c5503b
NC		 10969 bfd_put_16 (input_bfd, relocation, hit_data);
10970
10971 /* Assumes two's complement. */
10972 if (signed_check > reloc_signed_max || signed_check < reloc_signed_min)
10973 return bfd_reloc_overflow;
10974
10975 return bfd_reloc_ok;
10976 }
cedb70c5 10977
8375c36b
PB		 10978 case R_ARM_ALU_PCREL7_0:
10979 case R_ARM_ALU_PCREL15_8:
10980 case R_ARM_ALU_PCREL23_15:
10981 {
10982 bfd_vma insn;
10983 bfd_vma relocation;
10984
10985 insn = bfd_get_32 (input_bfd, hit_data);
4e7fd91e
PB		 10986 if (globals->use_rel)
10987 {
10988 /* Extract the addend. */
10989 addend = (insn & 0xff) << ((insn & 0xf00) >> 7);
10990 signed_addend = addend;
10991 }
8375c36b
PB		 10992 relocation = value + signed_addend;
10993
10994 relocation -= (input_section->output_section->vma
10995 + input_section->output_offset
10996 + rel->r_offset);
10997 insn = (insn & ~0xfff)
10998 | ((howto->bitpos << 7) & 0xf00)
10999 | ((relocation >> howto->bitpos) & 0xff);
11000 bfd_put_32 (input_bfd, value, hit_data);
11001 }
11002 return bfd_reloc_ok;
11003
252b5132
RH		 11004 case R_ARM_GNU_VTINHERIT:
11005 case R_ARM_GNU_VTENTRY:
11006 return bfd_reloc_ok;
11007
c19d1205 11008 case R_ARM_GOTOFF32:
252b5132 11009 /* Relocation is relative to the start of the
99059e56 11010 global offset table. */
252b5132
RH		 11011
11012 BFD_ASSERT (sgot != NULL);
11013 if (sgot == NULL)
99059e56 11014 return bfd_reloc_notsupported;
9a5aca8c 11015
cedb70c5 11016 /* If we are addressing a Thumb function, we need to adjust the
ee29b9fb
RE		 11017 address by one, so that attempts to call the function pointer will
11018 correctly interpret it as Thumb code. */
35fc36a8 11019 if (branch_type == ST_BRANCH_TO_THUMB)
ee29b9fb
RE		 11020 value += 1;
11021
252b5132 11022 /* Note that sgot->output_offset is not involved in this
99059e56
RM		 11023 calculation. We always want the start of .got. If we
11024 define _GLOBAL_OFFSET_TABLE in a different way, as is
11025 permitted by the ABI, we might have to change this
11026 calculation. */
252b5132 11027 value -= sgot->output_section->vma;
f21f3fe0 11028 return _bfd_final_link_relocate (howto, input_bfd, input_section,
99e4ae17 11029 contents, rel->r_offset, value,
00a97672 11030 rel->r_addend);
252b5132
RH		 11031
11032 case R_ARM_GOTPC:
a7c10850 11033 /* Use global offset table as symbol value. */
252b5132 11034 BFD_ASSERT (sgot != NULL);
f21f3fe0 11035
252b5132 11036 if (sgot == NULL)
99059e56 11037 return bfd_reloc_notsupported;
252b5132 11038
0945cdfd 11039 *unresolved_reloc_p = FALSE;
252b5132 11040 value = sgot->output_section->vma;
f21f3fe0 11041 return _bfd_final_link_relocate (howto, input_bfd, input_section,
99e4ae17 11042 contents, rel->r_offset, value,
00a97672 11043 rel->r_addend);
f21f3fe0 11044
252b5132 11045 case R_ARM_GOT32:
eb043451 11046 case R_ARM_GOT_PREL:
252b5132 11047 /* Relocation is to the entry for this symbol in the
99059e56 11048 global offset table. */
252b5132
RH		 11049 if (sgot == NULL)
11050 return bfd_reloc_notsupported;
f21f3fe0 11051
34e77a92
RS		 11052 if (dynreloc_st_type == STT_GNU_IFUNC
11053 && plt_offset != (bfd_vma) -1
11054 && (h == NULL || SYMBOL_REFERENCES_LOCAL (info, h)))
11055 {
11056 /* We have a relocation against a locally-binding STT_GNU_IFUNC
11057 symbol, and the relocation resolves directly to the runtime
11058 target rather than to the .iplt entry. This means that any
11059 .got entry would be the same value as the .igot.plt entry,
11060 so there's no point creating both. */
11061 sgot = globals->root.igotplt;
11062 value = sgot->output_offset + gotplt_offset;
11063 }
11064 else if (h != NULL)
252b5132
RH		 11065 {
11066 bfd_vma off;
f21f3fe0 11067
252b5132
RH		 11068 off = h->got.offset;
11069 BFD_ASSERT (off != (bfd_vma) -1);
b436d854 11070 if ((off & 1) != 0)
252b5132 11071 {
b436d854
RS		 11072 /* We have already processsed one GOT relocation against
11073 this symbol. */
11074 off &= ~1;
11075 if (globals->root.dynamic_sections_created
11076 && !SYMBOL_REFERENCES_LOCAL (info, h))
11077 *unresolved_reloc_p = FALSE;
11078 }
11079 else
11080 {
11081 Elf_Internal_Rela outrel;
11082
6f820c85 11083 if (h->dynindx != -1 && !SYMBOL_REFERENCES_LOCAL (info, h))
b436d854
RS		 11084 {
11085 /* If the symbol doesn't resolve locally in a static
11086 object, we have an undefined reference. If the
11087 symbol doesn't resolve locally in a dynamic object,
11088 it should be resolved by the dynamic linker. */
11089 if (globals->root.dynamic_sections_created)
11090 {
11091 outrel.r_info = ELF32_R_INFO (h->dynindx, R_ARM_GLOB_DAT);
11092 *unresolved_reloc_p = FALSE;
11093 }
11094 else
11095 outrel.r_info = 0;
11096 outrel.r_addend = 0;
11097 }
252b5132
RH		 11098 else
11099 {
34e77a92 11100 if (dynreloc_st_type == STT_GNU_IFUNC)
99059e56 11101 outrel.r_info = ELF32_R_INFO (0, R_ARM_IRELATIVE);
5025eb7c
AO		 11102 else if (bfd_link_pic (info)
11103 && (ELF_ST_VISIBILITY (h->other) == STV_DEFAULT
11104 || h->root.type != bfd_link_hash_undefweak))
99059e56
RM		 11105 outrel.r_info = ELF32_R_INFO (0, R_ARM_RELATIVE);
11106 else
11107 outrel.r_info = 0;
34e77a92 11108 outrel.r_addend = dynreloc_value;
b436d854 11109 }
ee29b9fb 11110
b436d854
RS		 11111 /* The GOT entry is initialized to zero by default.
11112 See if we should install a different value. */
11113 if (outrel.r_addend != 0
11114 && (outrel.r_info == 0 || globals->use_rel))
11115 {
11116 bfd_put_32 (output_bfd, outrel.r_addend,
11117 sgot->contents + off);
11118 outrel.r_addend = 0;
252b5132 11119 }
f21f3fe0 11120
b436d854
RS		 11121 if (outrel.r_info != 0)
11122 {
11123 outrel.r_offset = (sgot->output_section->vma
11124 + sgot->output_offset
11125 + off);
11126 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
11127 }
11128 h->got.offset |= 1;
11129 }
252b5132
RH		 11130 value = sgot->output_offset + off;
11131 }
11132 else
11133 {
11134 bfd_vma off;
f21f3fe0 11135
5025eb7c
AO		 11136 BFD_ASSERT (local_got_offsets != NULL
11137 && local_got_offsets[r_symndx] != (bfd_vma) -1);
f21f3fe0 11138
252b5132 11139 off = local_got_offsets[r_symndx];
f21f3fe0 11140
252b5132
RH		 11141 /* The offset must always be a multiple of 4. We use the
11142 least significant bit to record whether we have already
9b485d32 11143 generated the necessary reloc. */
252b5132
RH		 11144 if ((off & 1) != 0)
11145 off &= ~1;
11146 else
11147 {
00a97672 11148 if (globals->use_rel)
34e77a92 11149 bfd_put_32 (output_bfd, dynreloc_value, sgot->contents + off);
f21f3fe0 11150
0e1862bb 11151 if (bfd_link_pic (info) || dynreloc_st_type == STT_GNU_IFUNC)
252b5132 11152 {
947216bf 11153 Elf_Internal_Rela outrel;
f21f3fe0 11154
34e77a92 11155 outrel.r_addend = addend + dynreloc_value;
252b5132 11156 outrel.r_offset = (sgot->output_section->vma
f21f3fe0 11157 + sgot->output_offset
252b5132 11158 + off);
34e77a92 11159 if (dynreloc_st_type == STT_GNU_IFUNC)
99059e56 11160 outrel.r_info = ELF32_R_INFO (0, R_ARM_IRELATIVE);
34e77a92
RS		 11161 else
11162 outrel.r_info = ELF32_R_INFO (0, R_ARM_RELATIVE);
47beaa6a 11163 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
252b5132 11164 }
f21f3fe0 11165
252b5132
RH		 11166 local_got_offsets[r_symndx] |= 1;
11167 }
f21f3fe0 11168
252b5132
RH		 11169 value = sgot->output_offset + off;
11170 }
eb043451
PB		 11171 if (r_type != R_ARM_GOT32)
11172 value += sgot->output_section->vma;
9a5aca8c 11173
f21f3fe0 11174 return _bfd_final_link_relocate (howto, input_bfd, input_section,
99e4ae17 11175 contents, rel->r_offset, value,
00a97672 11176 rel->r_addend);
f21f3fe0 11177
ba93b8ac
DJ		 11178 case R_ARM_TLS_LDO32:
11179 value = value - dtpoff_base (info);
11180
11181 return _bfd_final_link_relocate (howto, input_bfd, input_section,
00a97672
RS		 11182 contents, rel->r_offset, value,
11183 rel->r_addend);
ba93b8ac
DJ		 11184
11185 case R_ARM_TLS_LDM32:
11186 {
11187 bfd_vma off;
11188
362d30a1 11189 if (sgot == NULL)
ba93b8ac
DJ		 11190 abort ();
11191
11192 off = globals->tls_ldm_got.offset;
11193
11194 if ((off & 1) != 0)
11195 off &= ~1;
11196 else
11197 {
11198 /* If we don't know the module number, create a relocation
11199 for it. */
0e1862bb 11200 if (bfd_link_pic (info))
ba93b8ac
DJ		 11201 {
11202 Elf_Internal_Rela outrel;
ba93b8ac 11203
362d30a1 11204 if (srelgot == NULL)
ba93b8ac
DJ		 11205 abort ();
11206
00a97672 11207 outrel.r_addend = 0;
362d30a1
RS		 11208 outrel.r_offset = (sgot->output_section->vma
11209 + sgot->output_offset + off);
ba93b8ac
DJ		 11210 outrel.r_info = ELF32_R_INFO (0, R_ARM_TLS_DTPMOD32);
11211
00a97672
RS		 11212 if (globals->use_rel)
11213 bfd_put_32 (output_bfd, outrel.r_addend,
362d30a1 11214 sgot->contents + off);
ba93b8ac 11215
47beaa6a 11216 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
ba93b8ac
DJ		 11217 }
11218 else
362d30a1 11219 bfd_put_32 (output_bfd, 1, sgot->contents + off);
ba93b8ac
DJ		 11220
11221 globals->tls_ldm_got.offset |= 1;
11222 }
11223
362d30a1 11224 value = sgot->output_section->vma + sgot->output_offset + off
ba93b8ac
DJ		 11225 - (input_section->output_section->vma + input_section->output_offset + rel->r_offset);
11226
11227 return _bfd_final_link_relocate (howto, input_bfd, input_section,
11228 contents, rel->r_offset, value,
00a97672 11229 rel->r_addend);
ba93b8ac
DJ		 11230 }
11231
0855e32b
NS		 11232 case R_ARM_TLS_CALL:
11233 case R_ARM_THM_TLS_CALL:
ba93b8ac
DJ		 11234 case R_ARM_TLS_GD32:
11235 case R_ARM_TLS_IE32:
0855e32b
NS		 11236 case R_ARM_TLS_GOTDESC:
11237 case R_ARM_TLS_DESCSEQ:
11238 case R_ARM_THM_TLS_DESCSEQ:
ba93b8ac 11239 {
0855e32b
NS		 11240 bfd_vma off, offplt;
11241 int indx = 0;
ba93b8ac
DJ		 11242 char tls_type;
11243
0855e32b 11244 BFD_ASSERT (sgot != NULL);
ba93b8ac 11245
ba93b8ac
DJ		 11246 if (h != NULL)
11247 {
11248 bfd_boolean dyn;
11249 dyn = globals->root.dynamic_sections_created;
0e1862bb
L		 11250 if (WILL_CALL_FINISH_DYNAMIC_SYMBOL (dyn,
11251 bfd_link_pic (info),
11252 h)
11253 && (!bfd_link_pic (info)
ba93b8ac
DJ		 11254 || !SYMBOL_REFERENCES_LOCAL (info, h)))
11255 {
11256 *unresolved_reloc_p = FALSE;
11257 indx = h->dynindx;
11258 }
11259 off = h->got.offset;
0855e32b 11260 offplt = elf32_arm_hash_entry (h)->tlsdesc_got;
ba93b8ac
DJ		 11261 tls_type = ((struct elf32_arm_link_hash_entry *) h)->tls_type;
11262 }
11263 else
11264 {
0855e32b 11265 BFD_ASSERT (local_got_offsets != NULL);
ba93b8ac 11266 off = local_got_offsets[r_symndx];
0855e32b 11267 offplt = local_tlsdesc_gotents[r_symndx];
ba93b8ac
DJ		 11268 tls_type = elf32_arm_local_got_tls_type (input_bfd)[r_symndx];
11269 }
11270
0855e32b 11271 /* Linker relaxations happens from one of the
b38cadfb 11272 R_ARM_{GOTDESC,CALL,DESCSEQ} relocations to IE or LE. */
0855e32b 11273 if (ELF32_R_TYPE(rel->r_info) != r_type)
b38cadfb 11274 tls_type = GOT_TLS_IE;
0855e32b
NS		 11275
11276 BFD_ASSERT (tls_type != GOT_UNKNOWN);
ba93b8ac
DJ		 11277
11278 if ((off & 1) != 0)
11279 off &= ~1;
11280 else
11281 {
11282 bfd_boolean need_relocs = FALSE;
11283 Elf_Internal_Rela outrel;
ba93b8ac
DJ		 11284 int cur_off = off;
11285
11286 /* The GOT entries have not been initialized yet. Do it
11287 now, and emit any relocations. If both an IE GOT and a
11288 GD GOT are necessary, we emit the GD first. */
11289
0e1862bb 11290 if ((bfd_link_pic (info) || indx != 0)
ba93b8ac
DJ		 11291 && (h == NULL
11292 || ELF_ST_VISIBILITY (h->other) == STV_DEFAULT
11293 || h->root.type != bfd_link_hash_undefweak))
11294 {
11295 need_relocs = TRUE;
0855e32b 11296 BFD_ASSERT (srelgot != NULL);
ba93b8ac
DJ		 11297 }
11298
0855e32b
NS		 11299 if (tls_type & GOT_TLS_GDESC)
11300 {
47beaa6a
RS		 11301 bfd_byte *loc;
11302
0855e32b
NS		 11303 /* We should have relaxed, unless this is an undefined
11304 weak symbol. */
11305 BFD_ASSERT ((h && (h->root.type == bfd_link_hash_undefweak))
0e1862bb 11306 || bfd_link_pic (info));
0855e32b 11307 BFD_ASSERT (globals->sgotplt_jump_table_size + offplt + 8
99059e56 11308 <= globals->root.sgotplt->size);
0855e32b
NS		 11309
11310 outrel.r_addend = 0;
11311 outrel.r_offset = (globals->root.sgotplt->output_section->vma
11312 + globals->root.sgotplt->output_offset
11313 + offplt
11314 + globals->sgotplt_jump_table_size);
b38cadfb 11315
0855e32b
NS		 11316 outrel.r_info = ELF32_R_INFO (indx, R_ARM_TLS_DESC);
11317 sreloc = globals->root.srelplt;
11318 loc = sreloc->contents;
11319 loc += globals->next_tls_desc_index++ * RELOC_SIZE (globals);
11320 BFD_ASSERT (loc + RELOC_SIZE (globals)
99059e56 11321 <= sreloc->contents + sreloc->size);
0855e32b
NS		 11322
11323 SWAP_RELOC_OUT (globals) (output_bfd, &outrel, loc);
11324
11325 /* For globals, the first word in the relocation gets
11326 the relocation index and the top bit set, or zero,
11327 if we're binding now. For locals, it gets the
11328 symbol's offset in the tls section. */
99059e56 11329 bfd_put_32 (output_bfd,
0855e32b
NS		 11330 !h ? value - elf_hash_table (info)->tls_sec->vma
11331 : info->flags & DF_BIND_NOW ? 0
11332 : 0x80000000 | ELF32_R_SYM (outrel.r_info),
b38cadfb
NC		 11333 globals->root.sgotplt->contents + offplt
11334 + globals->sgotplt_jump_table_size);
11335
0855e32b 11336 /* Second word in the relocation is always zero. */
99059e56 11337 bfd_put_32 (output_bfd, 0,
b38cadfb
NC		 11338 globals->root.sgotplt->contents + offplt
11339 + globals->sgotplt_jump_table_size + 4);
0855e32b 11340 }
ba93b8ac
DJ		 11341 if (tls_type & GOT_TLS_GD)
11342 {
11343 if (need_relocs)
11344 {
00a97672 11345 outrel.r_addend = 0;
362d30a1
RS		 11346 outrel.r_offset = (sgot->output_section->vma
11347 + sgot->output_offset
00a97672 11348 + cur_off);
ba93b8ac 11349 outrel.r_info = ELF32_R_INFO (indx, R_ARM_TLS_DTPMOD32);
ba93b8ac 11350
00a97672
RS		 11351 if (globals->use_rel)
11352 bfd_put_32 (output_bfd, outrel.r_addend,
362d30a1 11353 sgot->contents + cur_off);
00a97672 11354
47beaa6a 11355 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
ba93b8ac
DJ		 11356
11357 if (indx == 0)
11358 bfd_put_32 (output_bfd, value - dtpoff_base (info),
362d30a1 11359 sgot->contents + cur_off + 4);
ba93b8ac
DJ		 11360 else
11361 {
00a97672 11362 outrel.r_addend = 0;
ba93b8ac
DJ		 11363 outrel.r_info = ELF32_R_INFO (indx,
11364 R_ARM_TLS_DTPOFF32);
11365 outrel.r_offset += 4;
00a97672
RS		 11366
11367 if (globals->use_rel)
11368 bfd_put_32 (output_bfd, outrel.r_addend,
362d30a1 11369 sgot->contents + cur_off + 4);
00a97672 11370
47beaa6a
RS		 11371 elf32_arm_add_dynreloc (output_bfd, info,
11372 srelgot, &outrel);
ba93b8ac
DJ		 11373 }
11374 }
11375 else
11376 {
11377 /* If we are not emitting relocations for a
11378 general dynamic reference, then we must be in a
11379 static link or an executable link with the
11380 symbol binding locally. Mark it as belonging
11381 to module 1, the executable. */
11382 bfd_put_32 (output_bfd, 1,
362d30a1 11383 sgot->contents + cur_off);
ba93b8ac 11384 bfd_put_32 (output_bfd, value - dtpoff_base (info),
362d30a1 11385 sgot->contents + cur_off + 4);
ba93b8ac
DJ		 11386 }
11387
11388 cur_off += 8;
11389 }
11390
11391 if (tls_type & GOT_TLS_IE)
11392 {
11393 if (need_relocs)
11394 {
00a97672
RS		 11395 if (indx == 0)
11396 outrel.r_addend = value - dtpoff_base (info);
11397 else
11398 outrel.r_addend = 0;
362d30a1
RS		 11399 outrel.r_offset = (sgot->output_section->vma
11400 + sgot->output_offset
ba93b8ac
DJ		 11401 + cur_off);
11402 outrel.r_info = ELF32_R_INFO (indx, R_ARM_TLS_TPOFF32);
11403
00a97672
RS		 11404 if (globals->use_rel)
11405 bfd_put_32 (output_bfd, outrel.r_addend,
362d30a1 11406 sgot->contents + cur_off);
ba93b8ac 11407
47beaa6a 11408 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
ba93b8ac
DJ		 11409 }
11410 else
11411 bfd_put_32 (output_bfd, tpoff (info, value),
362d30a1 11412 sgot->contents + cur_off);
ba93b8ac
DJ		 11413 cur_off += 4;
11414 }
11415
11416 if (h != NULL)
11417 h->got.offset |= 1;
11418 else
11419 local_got_offsets[r_symndx] |= 1;
11420 }
11421
11422 if ((tls_type & GOT_TLS_GD) && r_type != R_ARM_TLS_GD32)
11423 off += 8;
0855e32b
NS		 11424 else if (tls_type & GOT_TLS_GDESC)
11425 off = offplt;
11426
11427 if (ELF32_R_TYPE(rel->r_info) == R_ARM_TLS_CALL
11428 || ELF32_R_TYPE(rel->r_info) == R_ARM_THM_TLS_CALL)
11429 {
11430 bfd_signed_vma offset;
12352d3f
PB		 11431 /* TLS stubs are arm mode. The original symbol is a
11432 data object, so branch_type is bogus. */
11433 branch_type = ST_BRANCH_TO_ARM;
0855e32b 11434 enum elf32_arm_stub_type stub_type
34e77a92
RS		 11435 = arm_type_of_stub (info, input_section, rel,
11436 st_type, &branch_type,
0855e32b
NS		 11437 (struct elf32_arm_link_hash_entry *)h,
11438 globals->tls_trampoline, globals->root.splt,
11439 input_bfd, sym_name);
11440
11441 if (stub_type != arm_stub_none)
11442 {
11443 struct elf32_arm_stub_hash_entry *stub_entry
11444 = elf32_arm_get_stub_entry
11445 (input_section, globals->root.splt, 0, rel,
11446 globals, stub_type);
11447 offset = (stub_entry->stub_offset
11448 + stub_entry->stub_sec->output_offset
11449 + stub_entry->stub_sec->output_section->vma);
11450 }
11451 else
11452 offset = (globals->root.splt->output_section->vma
11453 + globals->root.splt->output_offset
11454 + globals->tls_trampoline);
11455
11456 if (ELF32_R_TYPE(rel->r_info) == R_ARM_TLS_CALL)
11457 {
11458 unsigned long inst;
b38cadfb
NC		 11459
11460 offset -= (input_section->output_section->vma
11461 + input_section->output_offset
11462 + rel->r_offset + 8);
0855e32b
NS		 11463
11464 inst = offset >> 2;
11465 inst &= 0x00ffffff;
11466 value = inst | (globals->use_blx ? 0xfa000000 : 0xeb000000);
11467 }
11468 else
11469 {
11470 /* Thumb blx encodes the offset in a complicated
11471 fashion. */
11472 unsigned upper_insn, lower_insn;
11473 unsigned neg;
11474
b38cadfb
NC		 11475 offset -= (input_section->output_section->vma
11476 + input_section->output_offset
0855e32b 11477 + rel->r_offset + 4);
b38cadfb 11478
12352d3f
PB		 11479 if (stub_type != arm_stub_none
11480 && arm_stub_is_thumb (stub_type))
11481 {
11482 lower_insn = 0xd000;
11483 }
11484 else
11485 {
11486 lower_insn = 0xc000;
6a631e86 11487 /* Round up the offset to a word boundary. */
12352d3f
PB		 11488 offset = (offset + 2) & ~2;
11489 }
11490
0855e32b
NS		 11491 neg = offset < 0;
11492 upper_insn = (0xf000
11493 | ((offset >> 12) & 0x3ff)
11494 | (neg << 10));
12352d3f 11495 lower_insn |= (((!((offset >> 23) & 1)) ^ neg) << 13)
0855e32b 11496 | (((!((offset >> 22) & 1)) ^ neg) << 11)
12352d3f 11497 | ((offset >> 1) & 0x7ff);
0855e32b
NS		 11498 bfd_put_16 (input_bfd, upper_insn, hit_data);
11499 bfd_put_16 (input_bfd, lower_insn, hit_data + 2);
11500 return bfd_reloc_ok;
11501 }
11502 }
11503 /* These relocations needs special care, as besides the fact
11504 they point somewhere in .gotplt, the addend must be
11505 adjusted accordingly depending on the type of instruction
6a631e86 11506 we refer to. */
0855e32b
NS		 11507 else if ((r_type == R_ARM_TLS_GOTDESC) && (tls_type & GOT_TLS_GDESC))
11508 {
11509 unsigned long data, insn;
11510 unsigned thumb;
b38cadfb 11511
0855e32b
NS		 11512 data = bfd_get_32 (input_bfd, hit_data);
11513 thumb = data & 1;
11514 data &= ~1u;
b38cadfb 11515
0855e32b
NS		 11516 if (thumb)
11517 {
11518 insn = bfd_get_16 (input_bfd, contents + rel->r_offset - data);
11519 if ((insn & 0xf000) == 0xf000 || (insn & 0xf800) == 0xe800)
11520 insn = (insn << 16)
11521 | bfd_get_16 (input_bfd,
11522 contents + rel->r_offset - data + 2);
11523 if ((insn & 0xf800c000) == 0xf000c000)
11524 /* bl/blx */
11525 value = -6;
11526 else if ((insn & 0xffffff00) == 0x4400)
11527 /* add */
11528 value = -5;
11529 else
11530 {
4eca0228 11531 _bfd_error_handler
0855e32b
NS		 11532 (_("%B(%A+0x%lx):unexpected Thumb instruction '0x%x' referenced by TLS_GOTDESC"),
11533 input_bfd, input_section,
11534 (unsigned long)rel->r_offset, insn);
11535 return bfd_reloc_notsupported;
11536 }
11537 }
11538 else
11539 {
11540 insn = bfd_get_32 (input_bfd, contents + rel->r_offset - data);
11541
11542 switch (insn >> 24)
11543 {
11544 case 0xeb: /* bl */
11545 case 0xfa: /* blx */
11546 value = -4;
11547 break;
11548
11549 case 0xe0: /* add */
11550 value = -8;
11551 break;
b38cadfb 11552
0855e32b 11553 default:
4eca0228 11554 _bfd_error_handler
0855e32b
NS		 11555 (_("%B(%A+0x%lx):unexpected ARM instruction '0x%x' referenced by TLS_GOTDESC"),
11556 input_bfd, input_section,
11557 (unsigned long)rel->r_offset, insn);
11558 return bfd_reloc_notsupported;
11559 }
11560 }
b38cadfb 11561
0855e32b
NS		 11562 value += ((globals->root.sgotplt->output_section->vma
11563 + globals->root.sgotplt->output_offset + off)
11564 - (input_section->output_section->vma
11565 + input_section->output_offset
11566 + rel->r_offset)
11567 + globals->sgotplt_jump_table_size);
11568 }
11569 else
11570 value = ((globals->root.sgot->output_section->vma
11571 + globals->root.sgot->output_offset + off)
11572 - (input_section->output_section->vma
11573 + input_section->output_offset + rel->r_offset));
ba93b8ac
DJ		 11574
11575 return _bfd_final_link_relocate (howto, input_bfd, input_section,
11576 contents, rel->r_offset, value,
00a97672 11577 rel->r_addend);
ba93b8ac
DJ		 11578 }
11579
11580 case R_ARM_TLS_LE32:
3cbc1e5e 11581 if (bfd_link_dll (info))
ba93b8ac 11582 {
4eca0228 11583 _bfd_error_handler
ba93b8ac
DJ		 11584 (_("%B(%A+0x%lx): R_ARM_TLS_LE32 relocation not permitted in shared object"),
11585 input_bfd, input_section,
11586 (long) rel->r_offset, howto->name);
46691134 11587 return bfd_reloc_notsupported;
ba93b8ac
DJ		 11588 }
11589 else
11590 value = tpoff (info, value);
906e58ca 11591
ba93b8ac 11592 return _bfd_final_link_relocate (howto, input_bfd, input_section,
00a97672
RS		 11593 contents, rel->r_offset, value,
11594 rel->r_addend);
ba93b8ac 11595
319850b4
JB		 11596 case R_ARM_V4BX:
11597 if (globals->fix_v4bx)
845b51d6
PB		 11598 {
11599 bfd_vma insn = bfd_get_32 (input_bfd, hit_data);
319850b4 11600
845b51d6
PB		 11601 /* Ensure that we have a BX instruction. */
11602 BFD_ASSERT ((insn & 0x0ffffff0) == 0x012fff10);
319850b4 11603
845b51d6
PB		 11604 if (globals->fix_v4bx == 2 && (insn & 0xf) != 0xf)
11605 {
11606 /* Branch to veneer. */
11607 bfd_vma glue_addr;
11608 glue_addr = elf32_arm_bx_glue (info, insn & 0xf);
11609 glue_addr -= input_section->output_section->vma
11610 + input_section->output_offset
11611 + rel->r_offset + 8;
11612 insn = (insn & 0xf0000000) | 0x0a000000
11613 | ((glue_addr >> 2) & 0x00ffffff);
11614 }
11615 else
11616 {
11617 /* Preserve Rm (lowest four bits) and the condition code
11618 (highest four bits). Other bits encode MOV PC,Rm. */
11619 insn = (insn & 0xf000000f) | 0x01a0f000;
11620 }
319850b4 11621
845b51d6
PB		 11622 bfd_put_32 (input_bfd, insn, hit_data);
11623 }
319850b4
JB		 11624 return bfd_reloc_ok;
11625
b6895b4f
PB		 11626 case R_ARM_MOVW_ABS_NC:
11627 case R_ARM_MOVT_ABS:
11628 case R_ARM_MOVW_PREL_NC:
11629 case R_ARM_MOVT_PREL:
92f5d02b
MS		 11630 /* Until we properly support segment-base-relative addressing then
11631 we assume the segment base to be zero, as for the group relocations.
11632 Thus R_ARM_MOVW_BREL_NC has the same semantics as R_ARM_MOVW_ABS_NC
11633 and R_ARM_MOVT_BREL has the same semantics as R_ARM_MOVT_ABS. */
11634 case R_ARM_MOVW_BREL_NC:
11635 case R_ARM_MOVW_BREL:
11636 case R_ARM_MOVT_BREL:
b6895b4f
PB		 11637 {
11638 bfd_vma insn = bfd_get_32 (input_bfd, hit_data);
11639
11640 if (globals->use_rel)
11641 {
11642 addend = ((insn >> 4) & 0xf000) | (insn & 0xfff);
39623e12 11643 signed_addend = (addend ^ 0x8000) - 0x8000;
b6895b4f 11644 }
92f5d02b 11645
b6895b4f 11646 value += signed_addend;
b6895b4f
PB		 11647
11648 if (r_type == R_ARM_MOVW_PREL_NC || r_type == R_ARM_MOVT_PREL)
11649 value -= (input_section->output_section->vma
11650 + input_section->output_offset + rel->r_offset);
11651
92f5d02b 11652 if (r_type == R_ARM_MOVW_BREL && value >= 0x10000)
99059e56 11653 return bfd_reloc_overflow;
92f5d02b 11654
35fc36a8 11655 if (branch_type == ST_BRANCH_TO_THUMB)
92f5d02b
MS		 11656 value |= 1;
11657
11658 if (r_type == R_ARM_MOVT_ABS || r_type == R_ARM_MOVT_PREL
99059e56 11659 || r_type == R_ARM_MOVT_BREL)
b6895b4f
PB		 11660 value >>= 16;
11661
11662 insn &= 0xfff0f000;
11663 insn |= value & 0xfff;
11664 insn |= (value & 0xf000) << 4;
11665 bfd_put_32 (input_bfd, insn, hit_data);
11666 }
11667 return bfd_reloc_ok;
11668
11669 case R_ARM_THM_MOVW_ABS_NC:
11670 case R_ARM_THM_MOVT_ABS:
11671 case R_ARM_THM_MOVW_PREL_NC:
11672 case R_ARM_THM_MOVT_PREL:
92f5d02b
MS		 11673 /* Until we properly support segment-base-relative addressing then
11674 we assume the segment base to be zero, as for the above relocations.
11675 Thus R_ARM_THM_MOVW_BREL_NC has the same semantics as
11676 R_ARM_THM_MOVW_ABS_NC and R_ARM_THM_MOVT_BREL has the same semantics
11677 as R_ARM_THM_MOVT_ABS. */
11678 case R_ARM_THM_MOVW_BREL_NC:
11679 case R_ARM_THM_MOVW_BREL:
11680 case R_ARM_THM_MOVT_BREL:
b6895b4f
PB		 11681 {
11682 bfd_vma insn;
906e58ca 11683
b6895b4f
PB		 11684 insn = bfd_get_16 (input_bfd, hit_data) << 16;
11685 insn |= bfd_get_16 (input_bfd, hit_data + 2);
11686
11687 if (globals->use_rel)
11688 {
11689 addend = ((insn >> 4) & 0xf000)
11690 | ((insn >> 15) & 0x0800)
11691 | ((insn >> 4) & 0x0700)
11692 | (insn & 0x00ff);
39623e12 11693 signed_addend = (addend ^ 0x8000) - 0x8000;
b6895b4f 11694 }
92f5d02b 11695
b6895b4f 11696 value += signed_addend;
b6895b4f
PB		 11697
11698 if (r_type == R_ARM_THM_MOVW_PREL_NC || r_type == R_ARM_THM_MOVT_PREL)
11699 value -= (input_section->output_section->vma
11700 + input_section->output_offset + rel->r_offset);
11701
92f5d02b 11702 if (r_type == R_ARM_THM_MOVW_BREL && value >= 0x10000)
99059e56 11703 return bfd_reloc_overflow;
92f5d02b 11704
35fc36a8 11705 if (branch_type == ST_BRANCH_TO_THUMB)
92f5d02b
MS		 11706 value |= 1;
11707
11708 if (r_type == R_ARM_THM_MOVT_ABS || r_type == R_ARM_THM_MOVT_PREL
99059e56 11709 || r_type == R_ARM_THM_MOVT_BREL)
b6895b4f
PB		 11710 value >>= 16;
11711
11712 insn &= 0xfbf08f00;
11713 insn |= (value & 0xf000) << 4;
11714 insn |= (value & 0x0800) << 15;
11715 insn |= (value & 0x0700) << 4;
11716 insn |= (value & 0x00ff);
11717
11718 bfd_put_16 (input_bfd, insn >> 16, hit_data);
11719 bfd_put_16 (input_bfd, insn & 0xffff, hit_data + 2);
11720 }
11721 return bfd_reloc_ok;
11722
4962c51a
MS		 11723 case R_ARM_ALU_PC_G0_NC:
11724 case R_ARM_ALU_PC_G1_NC:
11725 case R_ARM_ALU_PC_G0:
11726 case R_ARM_ALU_PC_G1:
11727 case R_ARM_ALU_PC_G2:
11728 case R_ARM_ALU_SB_G0_NC:
11729 case R_ARM_ALU_SB_G1_NC:
11730 case R_ARM_ALU_SB_G0:
11731 case R_ARM_ALU_SB_G1:
11732 case R_ARM_ALU_SB_G2:
11733 {
11734 bfd_vma insn = bfd_get_32 (input_bfd, hit_data);
99059e56 11735 bfd_vma pc = input_section->output_section->vma
4962c51a 11736 + input_section->output_offset + rel->r_offset;
31a91d61 11737 /* sb is the origin of the *segment* containing the symbol. */
62c34db3 11738 bfd_vma sb = sym_sec ? sym_sec->output_section->vma : 0;
99059e56
RM		 11739 bfd_vma residual;
11740 bfd_vma g_n;
4962c51a 11741 bfd_signed_vma signed_value;
99059e56
RM		 11742 int group = 0;
11743
11744 /* Determine which group of bits to select. */
11745 switch (r_type)
11746 {
11747 case R_ARM_ALU_PC_G0_NC:
11748 case R_ARM_ALU_PC_G0:
11749 case R_ARM_ALU_SB_G0_NC:
11750 case R_ARM_ALU_SB_G0:
11751 group = 0;
11752 break;
11753
11754 case R_ARM_ALU_PC_G1_NC:
11755 case R_ARM_ALU_PC_G1:
11756 case R_ARM_ALU_SB_G1_NC:
11757 case R_ARM_ALU_SB_G1:
11758 group = 1;
11759 break;
11760
11761 case R_ARM_ALU_PC_G2:
11762 case R_ARM_ALU_SB_G2:
11763 group = 2;
11764 break;
11765
11766 default:
11767 abort ();
11768 }
11769
11770 /* If REL, extract the addend from the insn. If RELA, it will
11771 have already been fetched for us. */
4962c51a 11772 if (globals->use_rel)
99059e56
RM		 11773 {
11774 int negative;
11775 bfd_vma constant = insn & 0xff;
11776 bfd_vma rotation = (insn & 0xf00) >> 8;
11777
11778 if (rotation == 0)
11779 signed_addend = constant;
11780 else
11781 {
11782 /* Compensate for the fact that in the instruction, the
11783 rotation is stored in multiples of 2 bits. */
11784 rotation *= 2;
11785
11786 /* Rotate "constant" right by "rotation" bits. */
11787 signed_addend = (constant >> rotation) |
11788 (constant << (8 * sizeof (bfd_vma) - rotation));
11789 }
11790
11791 /* Determine if the instruction is an ADD or a SUB.
11792 (For REL, this determines the sign of the addend.) */
11793 negative = identify_add_or_sub (insn);
11794 if (negative == 0)
11795 {
4eca0228 11796 _bfd_error_handler
99059e56
RM		 11797 (_("%B(%A+0x%lx): Only ADD or SUB instructions are allowed for ALU group relocations"),
11798 input_bfd, input_section,
11799 (long) rel->r_offset, howto->name);
11800 return bfd_reloc_overflow;
11801 }
11802
11803 signed_addend *= negative;
11804 }
4962c51a
MS		 11805
11806 /* Compute the value (X) to go in the place. */
99059e56
RM		 11807 if (r_type == R_ARM_ALU_PC_G0_NC
11808 || r_type == R_ARM_ALU_PC_G1_NC
11809 || r_type == R_ARM_ALU_PC_G0
11810 || r_type == R_ARM_ALU_PC_G1
11811 || r_type == R_ARM_ALU_PC_G2)
11812 /* PC relative. */
11813 signed_value = value - pc + signed_addend;
11814 else
11815 /* Section base relative. */
11816 signed_value = value - sb + signed_addend;
11817
11818 /* If the target symbol is a Thumb function, then set the
11819 Thumb bit in the address. */
35fc36a8 11820 if (branch_type == ST_BRANCH_TO_THUMB)
4962c51a
MS		 11821 signed_value |= 1;
11822
99059e56
RM		 11823 /* Calculate the value of the relevant G_n, in encoded
11824 constant-with-rotation format. */
b6518b38
NC		 11825 g_n = calculate_group_reloc_mask (signed_value < 0 ? - signed_value : signed_value,
11826 group, &residual);
99059e56
RM		 11827
11828 /* Check for overflow if required. */
11829 if ((r_type == R_ARM_ALU_PC_G0
11830 || r_type == R_ARM_ALU_PC_G1
11831 || r_type == R_ARM_ALU_PC_G2
11832 || r_type == R_ARM_ALU_SB_G0
11833 || r_type == R_ARM_ALU_SB_G1
11834 || r_type == R_ARM_ALU_SB_G2) && residual != 0)
11835 {
4eca0228 11836 _bfd_error_handler
99059e56
RM		 11837 (_("%B(%A+0x%lx): Overflow whilst splitting 0x%lx for group relocation %s"),
11838 input_bfd, input_section,
b6518b38
NC		 11839 (long) rel->r_offset, signed_value < 0 ? - signed_value : signed_value,
11840 howto->name);
99059e56
RM		 11841 return bfd_reloc_overflow;
11842 }
11843
11844 /* Mask out the value and the ADD/SUB part of the opcode; take care
11845 not to destroy the S bit. */
11846 insn &= 0xff1ff000;
11847
11848 /* Set the opcode according to whether the value to go in the
11849 place is negative. */
11850 if (signed_value < 0)
11851 insn |= 1 << 22;
11852 else
11853 insn |= 1 << 23;
11854
11855 /* Encode the offset. */
11856 insn |= g_n;
4962c51a
MS		 11857
11858 bfd_put_32 (input_bfd, insn, hit_data);
11859 }
11860 return bfd_reloc_ok;
11861
11862 case R_ARM_LDR_PC_G0:
11863 case R_ARM_LDR_PC_G1:
11864 case R_ARM_LDR_PC_G2:
11865 case R_ARM_LDR_SB_G0:
11866 case R_ARM_LDR_SB_G1:
11867 case R_ARM_LDR_SB_G2:
11868 {
11869 bfd_vma insn = bfd_get_32 (input_bfd, hit_data);
99059e56 11870 bfd_vma pc = input_section->output_section->vma
4962c51a 11871 + input_section->output_offset + rel->r_offset;
31a91d61 11872 /* sb is the origin of the *segment* containing the symbol. */
62c34db3 11873 bfd_vma sb = sym_sec ? sym_sec->output_section->vma : 0;
99059e56 11874 bfd_vma residual;
4962c51a 11875 bfd_signed_vma signed_value;
99059e56
RM		 11876 int group = 0;
11877
11878 /* Determine which groups of bits to calculate. */
11879 switch (r_type)
11880 {
11881 case R_ARM_LDR_PC_G0:
11882 case R_ARM_LDR_SB_G0:
11883 group = 0;
11884 break;
11885
11886 case R_ARM_LDR_PC_G1:
11887 case R_ARM_LDR_SB_G1:
11888 group = 1;
11889 break;
11890
11891 case R_ARM_LDR_PC_G2:
11892 case R_ARM_LDR_SB_G2:
11893 group = 2;
11894 break;
11895
11896 default:
11897 abort ();
11898 }
11899
11900 /* If REL, extract the addend from the insn. If RELA, it will
11901 have already been fetched for us. */
4962c51a 11902 if (globals->use_rel)
99059e56
RM		 11903 {
11904 int negative = (insn & (1 << 23)) ? 1 : -1;
11905 signed_addend = negative * (insn & 0xfff);
11906 }
4962c51a
MS		 11907
11908 /* Compute the value (X) to go in the place. */
99059e56
RM		 11909 if (r_type == R_ARM_LDR_PC_G0
11910 || r_type == R_ARM_LDR_PC_G1
11911 || r_type == R_ARM_LDR_PC_G2)
11912 /* PC relative. */
11913 signed_value = value - pc + signed_addend;
11914 else
11915 /* Section base relative. */
11916 signed_value = value - sb + signed_addend;
11917
11918 /* Calculate the value of the relevant G_{n-1} to obtain
11919 the residual at that stage. */
b6518b38
NC		 11920 calculate_group_reloc_mask (signed_value < 0 ? - signed_value : signed_value,
11921 group - 1, &residual);
99059e56
RM		 11922
11923 /* Check for overflow. */
11924 if (residual >= 0x1000)
11925 {
4eca0228 11926 _bfd_error_handler
99059e56 11927 (_("%B(%A+0x%lx): Overflow whilst splitting 0x%lx for group relocation %s"),
b6518b38
NC		 11928 input_bfd, input_section,
11929 (long) rel->r_offset, labs (signed_value), howto->name);
99059e56
RM		 11930 return bfd_reloc_overflow;
11931 }
11932
11933 /* Mask out the value and U bit. */
11934 insn &= 0xff7ff000;
11935
11936 /* Set the U bit if the value to go in the place is non-negative. */
11937 if (signed_value >= 0)
11938 insn |= 1 << 23;
11939
11940 /* Encode the offset. */
11941 insn |= residual;
4962c51a
MS		 11942
11943 bfd_put_32 (input_bfd, insn, hit_data);
11944 }
11945 return bfd_reloc_ok;
11946
11947 case R_ARM_LDRS_PC_G0:
11948 case R_ARM_LDRS_PC_G1:
11949 case R_ARM_LDRS_PC_G2:
11950 case R_ARM_LDRS_SB_G0:
11951 case R_ARM_LDRS_SB_G1:
11952 case R_ARM_LDRS_SB_G2:
11953 {
11954 bfd_vma insn = bfd_get_32 (input_bfd, hit_data);
99059e56 11955 bfd_vma pc = input_section->output_section->vma
4962c51a 11956 + input_section->output_offset + rel->r_offset;
31a91d61 11957 /* sb is the origin of the *segment* containing the symbol. */
62c34db3 11958 bfd_vma sb = sym_sec ? sym_sec->output_section->vma : 0;
99059e56 11959 bfd_vma residual;
4962c51a 11960 bfd_signed_vma signed_value;
99059e56
RM		 11961 int group = 0;
11962
11963 /* Determine which groups of bits to calculate. */
11964 switch (r_type)
11965 {
11966 case R_ARM_LDRS_PC_G0:
11967 case R_ARM_LDRS_SB_G0:
11968 group = 0;
11969 break;
11970
11971 case R_ARM_LDRS_PC_G1:
11972 case R_ARM_LDRS_SB_G1:
11973 group = 1;
11974 break;
11975
11976 case R_ARM_LDRS_PC_G2:
11977 case R_ARM_LDRS_SB_G2:
11978 group = 2;
11979 break;
11980
11981 default:
11982 abort ();
11983 }
11984
11985 /* If REL, extract the addend from the insn. If RELA, it will
11986 have already been fetched for us. */
4962c51a 11987 if (globals->use_rel)
99059e56
RM		 11988 {
11989 int negative = (insn & (1 << 23)) ? 1 : -1;
11990 signed_addend = negative * (((insn & 0xf00) >> 4) + (insn & 0xf));
11991 }
4962c51a
MS		 11992
11993 /* Compute the value (X) to go in the place. */
99059e56
RM		 11994 if (r_type == R_ARM_LDRS_PC_G0
11995 || r_type == R_ARM_LDRS_PC_G1
11996 || r_type == R_ARM_LDRS_PC_G2)
11997 /* PC relative. */
11998 signed_value = value - pc + signed_addend;
11999 else
12000 /* Section base relative. */
12001 signed_value = value - sb + signed_addend;
12002
12003 /* Calculate the value of the relevant G_{n-1} to obtain
12004 the residual at that stage. */
b6518b38
NC		 12005 calculate_group_reloc_mask (signed_value < 0 ? - signed_value : signed_value,
12006 group - 1, &residual);
99059e56
RM		 12007
12008 /* Check for overflow. */
12009 if (residual >= 0x100)
12010 {
4eca0228 12011 _bfd_error_handler
99059e56 12012 (_("%B(%A+0x%lx): Overflow whilst splitting 0x%lx for group relocation %s"),
b6518b38
NC		 12013 input_bfd, input_section,
12014 (long) rel->r_offset, labs (signed_value), howto->name);
99059e56
RM		 12015 return bfd_reloc_overflow;
12016 }
12017
12018 /* Mask out the value and U bit. */
12019 insn &= 0xff7ff0f0;
12020
12021 /* Set the U bit if the value to go in the place is non-negative. */
12022 if (signed_value >= 0)
12023 insn |= 1 << 23;
12024
12025 /* Encode the offset. */
12026 insn |= ((residual & 0xf0) << 4) | (residual & 0xf);
4962c51a
MS		 12027
12028 bfd_put_32 (input_bfd, insn, hit_data);
12029 }
12030 return bfd_reloc_ok;
12031
12032 case R_ARM_LDC_PC_G0:
12033 case R_ARM_LDC_PC_G1:
12034 case R_ARM_LDC_PC_G2:
12035 case R_ARM_LDC_SB_G0:
12036 case R_ARM_LDC_SB_G1:
12037 case R_ARM_LDC_SB_G2:
12038 {
12039 bfd_vma insn = bfd_get_32 (input_bfd, hit_data);
99059e56 12040 bfd_vma pc = input_section->output_section->vma
4962c51a 12041 + input_section->output_offset + rel->r_offset;
31a91d61 12042 /* sb is the origin of the *segment* containing the symbol. */
62c34db3 12043 bfd_vma sb = sym_sec ? sym_sec->output_section->vma : 0;
99059e56 12044 bfd_vma residual;
4962c51a 12045 bfd_signed_vma signed_value;
99059e56
RM		 12046 int group = 0;
12047
12048 /* Determine which groups of bits to calculate. */
12049 switch (r_type)
12050 {
12051 case R_ARM_LDC_PC_G0:
12052 case R_ARM_LDC_SB_G0:
12053 group = 0;
12054 break;
12055
12056 case R_ARM_LDC_PC_G1:
12057 case R_ARM_LDC_SB_G1:
12058 group = 1;
12059 break;
12060
12061 case R_ARM_LDC_PC_G2:
12062 case R_ARM_LDC_SB_G2:
12063 group = 2;
12064 break;
12065
12066 default:
12067 abort ();
12068 }
12069
12070 /* If REL, extract the addend from the insn. If RELA, it will
12071 have already been fetched for us. */
4962c51a 12072 if (globals->use_rel)
99059e56
RM		 12073 {
12074 int negative = (insn & (1 << 23)) ? 1 : -1;
12075 signed_addend = negative * ((insn & 0xff) << 2);
12076 }
4962c51a
MS		 12077
12078 /* Compute the value (X) to go in the place. */
99059e56
RM		 12079 if (r_type == R_ARM_LDC_PC_G0
12080 || r_type == R_ARM_LDC_PC_G1
12081 || r_type == R_ARM_LDC_PC_G2)
12082 /* PC relative. */
12083 signed_value = value - pc + signed_addend;
12084 else
12085 /* Section base relative. */
12086 signed_value = value - sb + signed_addend;
12087
12088 /* Calculate the value of the relevant G_{n-1} to obtain
12089 the residual at that stage. */
b6518b38
NC		 12090 calculate_group_reloc_mask (signed_value < 0 ? - signed_value : signed_value,
12091 group - 1, &residual);
99059e56
RM		 12092
12093 /* Check for overflow. (The absolute value to go in the place must be
12094 divisible by four and, after having been divided by four, must
12095 fit in eight bits.) */
12096 if ((residual & 0x3) != 0 || residual >= 0x400)
12097 {
4eca0228 12098 _bfd_error_handler
99059e56
RM		 12099 (_("%B(%A+0x%lx): Overflow whilst splitting 0x%lx for group relocation %s"),
12100 input_bfd, input_section,
b6518b38 12101 (long) rel->r_offset, labs (signed_value), howto->name);
99059e56
RM		 12102 return bfd_reloc_overflow;
12103 }
12104
12105 /* Mask out the value and U bit. */
12106 insn &= 0xff7fff00;
12107
12108 /* Set the U bit if the value to go in the place is non-negative. */
12109 if (signed_value >= 0)
12110 insn |= 1 << 23;
12111
12112 /* Encode the offset. */
12113 insn |= residual >> 2;
4962c51a
MS		 12114
12115 bfd_put_32 (input_bfd, insn, hit_data);
12116 }
12117 return bfd_reloc_ok;
12118
72d98d16
MG		 12119 case R_ARM_THM_ALU_ABS_G0_NC:
12120 case R_ARM_THM_ALU_ABS_G1_NC:
12121 case R_ARM_THM_ALU_ABS_G2_NC:
12122 case R_ARM_THM_ALU_ABS_G3_NC:
12123 {
12124 const int shift_array[4] = {0, 8, 16, 24};
12125 bfd_vma insn = bfd_get_16 (input_bfd, hit_data);
12126 bfd_vma addr = value;
12127 int shift = shift_array[r_type - R_ARM_THM_ALU_ABS_G0_NC];
12128
12129 /* Compute address. */
12130 if (globals->use_rel)
12131 signed_addend = insn & 0xff;
12132 addr += signed_addend;
12133 if (branch_type == ST_BRANCH_TO_THUMB)
12134 addr |= 1;
12135 /* Clean imm8 insn. */
12136 insn &= 0xff00;
12137 /* And update with correct part of address. */
12138 insn |= (addr >> shift) & 0xff;
12139 /* Update insn. */
12140 bfd_put_16 (input_bfd, insn, hit_data);
12141 }
12142
12143 *unresolved_reloc_p = FALSE;
12144 return bfd_reloc_ok;
12145
252b5132
RH		 12146 default:
12147 return bfd_reloc_notsupported;
12148 }
12149}
12150
98c1d4aa
NC		 12151/* Add INCREMENT to the reloc (of type HOWTO) at ADDRESS. */
12152static void
57e8b36a
NC		 12153arm_add_to_rel (bfd * abfd,
12154 bfd_byte * address,
12155 reloc_howto_type * howto,
12156 bfd_signed_vma increment)
98c1d4aa 12157{
98c1d4aa
NC		 12158 bfd_signed_vma addend;
12159
bd97cb95
DJ		 12160 if (howto->type == R_ARM_THM_CALL
12161 || howto->type == R_ARM_THM_JUMP24)
98c1d4aa 12162 {
9a5aca8c
AM		 12163 int upper_insn, lower_insn;
12164 int upper, lower;
98c1d4aa 12165
9a5aca8c
AM		 12166 upper_insn = bfd_get_16 (abfd, address);
12167 lower_insn = bfd_get_16 (abfd, address + 2);
12168 upper = upper_insn & 0x7ff;
12169 lower = lower_insn & 0x7ff;
12170
12171 addend = (upper << 12) | (lower << 1);
ddda4409 12172 addend += increment;
9a5aca8c 12173 addend >>= 1;
98c1d4aa 12174
9a5aca8c
AM		 12175 upper_insn = (upper_insn & 0xf800) | ((addend >> 11) & 0x7ff);
12176 lower_insn = (lower_insn & 0xf800) | (addend & 0x7ff);
12177
dc810e39
AM		 12178 bfd_put_16 (abfd, (bfd_vma) upper_insn, address);
12179 bfd_put_16 (abfd, (bfd_vma) lower_insn, address + 2);
9a5aca8c
AM		 12180 }
12181 else
12182 {
12183 bfd_vma contents;
12184
12185 contents = bfd_get_32 (abfd, address);
12186
12187 /* Get the (signed) value from the instruction. */
12188 addend = contents & howto->src_mask;
12189 if (addend & ((howto->src_mask + 1) >> 1))
12190 {
12191 bfd_signed_vma mask;
12192
12193 mask = -1;
12194 mask &= ~ howto->src_mask;
12195 addend |= mask;
12196 }
12197
12198 /* Add in the increment, (which is a byte value). */
12199 switch (howto->type)
12200 {
12201 default:
12202 addend += increment;
12203 break;
12204
12205 case R_ARM_PC24:
c6596c5e 12206 case R_ARM_PLT32:
5b5bb741
PB		 12207 case R_ARM_CALL:
12208 case R_ARM_JUMP24:
9a5aca8c 12209 addend <<= howto->size;
dc810e39 12210 addend += increment;
9a5aca8c
AM		 12211
12212 /* Should we check for overflow here ? */
12213
12214 /* Drop any undesired bits. */
12215 addend >>= howto->rightshift;
12216 break;
12217 }
12218
12219 contents = (contents & ~ howto->dst_mask) | (addend & howto->dst_mask);
12220
12221 bfd_put_32 (abfd, contents, address);
ddda4409 12222 }
98c1d4aa 12223}
252b5132 12224
ba93b8ac
DJ		 12225#define IS_ARM_TLS_RELOC(R_TYPE) \
12226 ((R_TYPE) == R_ARM_TLS_GD32 \
12227 || (R_TYPE) == R_ARM_TLS_LDO32 \
12228 || (R_TYPE) == R_ARM_TLS_LDM32 \
12229 || (R_TYPE) == R_ARM_TLS_DTPOFF32 \
12230 || (R_TYPE) == R_ARM_TLS_DTPMOD32 \
12231 || (R_TYPE) == R_ARM_TLS_TPOFF32 \
12232 || (R_TYPE) == R_ARM_TLS_LE32 \
0855e32b
NS		 12233 || (R_TYPE) == R_ARM_TLS_IE32 \
12234 || IS_ARM_TLS_GNU_RELOC (R_TYPE))
12235
12236/* Specific set of relocations for the gnu tls dialect. */
12237#define IS_ARM_TLS_GNU_RELOC(R_TYPE) \
12238 ((R_TYPE) == R_ARM_TLS_GOTDESC \
12239 || (R_TYPE) == R_ARM_TLS_CALL \
12240 || (R_TYPE) == R_ARM_THM_TLS_CALL \
12241 || (R_TYPE) == R_ARM_TLS_DESCSEQ \
12242 || (R_TYPE) == R_ARM_THM_TLS_DESCSEQ)
ba93b8ac 12243
252b5132 12244/* Relocate an ARM ELF section. */
906e58ca 12245
b34976b6 12246static bfd_boolean
57e8b36a
NC		 12247elf32_arm_relocate_section (bfd * output_bfd,
12248 struct bfd_link_info * info,
12249 bfd * input_bfd,
12250 asection * input_section,
12251 bfd_byte * contents,
12252 Elf_Internal_Rela * relocs,
12253 Elf_Internal_Sym * local_syms,
12254 asection ** local_sections)
252b5132 12255{
b34976b6
AM		 12256 Elf_Internal_Shdr *symtab_hdr;
12257 struct elf_link_hash_entry **sym_hashes;
12258 Elf_Internal_Rela *rel;
12259 Elf_Internal_Rela *relend;
12260 const char *name;
b32d3aa2 12261 struct elf32_arm_link_hash_table * globals;
252b5132 12262
4e7fd91e 12263 globals = elf32_arm_hash_table (info);
4dfe6ac6
NC		 12264 if (globals == NULL)
12265 return FALSE;
b491616a 12266
0ffa91dd 12267 symtab_hdr = & elf_symtab_hdr (input_bfd);
252b5132
RH		 12268 sym_hashes = elf_sym_hashes (input_bfd);
12269
12270 rel = relocs;
12271 relend = relocs + input_section->reloc_count;
12272 for (; rel < relend; rel++)
12273 {
ba96a88f
NC		 12274 int r_type;
12275 reloc_howto_type * howto;
12276 unsigned long r_symndx;
12277 Elf_Internal_Sym * sym;
12278 asection * sec;
252b5132 12279 struct elf_link_hash_entry * h;
ba96a88f
NC		 12280 bfd_vma relocation;
12281 bfd_reloc_status_type r;
12282 arelent bfd_reloc;
ba93b8ac 12283 char sym_type;
0945cdfd 12284 bfd_boolean unresolved_reloc = FALSE;
f2a9dd69 12285 char *error_message = NULL;
f21f3fe0 12286
252b5132 12287 r_symndx = ELF32_R_SYM (rel->r_info);
ba96a88f 12288 r_type = ELF32_R_TYPE (rel->r_info);
b32d3aa2 12289 r_type = arm_real_reloc_type (globals, r_type);
252b5132 12290
ba96a88f 12291 if ( r_type == R_ARM_GNU_VTENTRY
99059e56
RM		 12292 || r_type == R_ARM_GNU_VTINHERIT)
12293 continue;
252b5132 12294
b32d3aa2 12295 bfd_reloc.howto = elf32_arm_howto_from_type (r_type);
ba96a88f 12296 howto = bfd_reloc.howto;
252b5132 12297
252b5132
RH		 12298 h = NULL;
12299 sym = NULL;
12300 sec = NULL;
9b485d32 12301
252b5132
RH		 12302 if (r_symndx < symtab_hdr->sh_info)
12303 {
12304 sym = local_syms + r_symndx;
ba93b8ac 12305 sym_type = ELF32_ST_TYPE (sym->st_info);
252b5132 12306 sec = local_sections[r_symndx];
ffcb4889
NS		 12307
12308 /* An object file might have a reference to a local
12309 undefined symbol. This is a daft object file, but we
12310 should at least do something about it. V4BX & NONE
12311 relocations do not use the symbol and are explicitly
77b4f08f
TS		 12312 allowed to use the undefined symbol, so allow those.
12313 Likewise for relocations against STN_UNDEF. */
ffcb4889
NS		 12314 if (r_type != R_ARM_V4BX
12315 && r_type != R_ARM_NONE
77b4f08f 12316 && r_symndx != STN_UNDEF
ffcb4889
NS		 12317 && bfd_is_und_section (sec)
12318 && ELF_ST_BIND (sym->st_info) != STB_WEAK)
1a72702b
AM		 12319 (*info->callbacks->undefined_symbol)
12320 (info, bfd_elf_string_from_elf_section
12321 (input_bfd, symtab_hdr->sh_link, sym->st_name),
12322 input_bfd, input_section,
12323 rel->r_offset, TRUE);
b38cadfb 12324
4e7fd91e 12325 if (globals->use_rel)
f8df10f4 12326 {
4e7fd91e
PB		 12327 relocation = (sec->output_section->vma
12328 + sec->output_offset
12329 + sym->st_value);
0e1862bb 12330 if (!bfd_link_relocatable (info)
ab96bf03
AM		 12331 && (sec->flags & SEC_MERGE)
12332 && ELF_ST_TYPE (sym->st_info) == STT_SECTION)
f8df10f4 12333 {
4e7fd91e
PB		 12334 asection *msec;
12335 bfd_vma addend, value;
12336
39623e12 12337 switch (r_type)
4e7fd91e 12338 {
39623e12
PB		 12339 case R_ARM_MOVW_ABS_NC:
12340 case R_ARM_MOVT_ABS:
12341 value = bfd_get_32 (input_bfd, contents + rel->r_offset);
12342 addend = ((value & 0xf0000) >> 4) | (value & 0xfff);
12343 addend = (addend ^ 0x8000) - 0x8000;
12344 break;
f8df10f4 12345
39623e12
PB		 12346 case R_ARM_THM_MOVW_ABS_NC:
12347 case R_ARM_THM_MOVT_ABS:
12348 value = bfd_get_16 (input_bfd, contents + rel->r_offset)
12349 << 16;
12350 value |= bfd_get_16 (input_bfd,
12351 contents + rel->r_offset + 2);
12352 addend = ((value & 0xf7000) >> 4) | (value & 0xff)
12353 | ((value & 0x04000000) >> 15);
12354 addend = (addend ^ 0x8000) - 0x8000;
12355 break;
f8df10f4 12356
39623e12
PB		 12357 default:
12358 if (howto->rightshift
12359 || (howto->src_mask & (howto->src_mask + 1)))
12360 {
4eca0228 12361 _bfd_error_handler
39623e12
PB		 12362 (_("%B(%A+0x%lx): %s relocation against SEC_MERGE section"),
12363 input_bfd, input_section,
12364 (long) rel->r_offset, howto->name);
12365 return FALSE;
12366 }
12367
12368 value = bfd_get_32 (input_bfd, contents + rel->r_offset);
12369
12370 /* Get the (signed) value from the instruction. */
12371 addend = value & howto->src_mask;
12372 if (addend & ((howto->src_mask + 1) >> 1))
12373 {
12374 bfd_signed_vma mask;
12375
12376 mask = -1;
12377 mask &= ~ howto->src_mask;
12378 addend |= mask;
12379 }
12380 break;
4e7fd91e 12381 }
39623e12 12382
4e7fd91e
PB		 12383 msec = sec;
12384 addend =
12385 _bfd_elf_rel_local_sym (output_bfd, sym, &msec, addend)
12386 - relocation;
12387 addend += msec->output_section->vma + msec->output_offset;
39623e12 12388
cc643b88 12389 /* Cases here must match those in the preceding
39623e12
PB		 12390 switch statement. */
12391 switch (r_type)
12392 {
12393 case R_ARM_MOVW_ABS_NC:
12394 case R_ARM_MOVT_ABS:
12395 value = (value & 0xfff0f000) | ((addend & 0xf000) << 4)
12396 | (addend & 0xfff);
12397 bfd_put_32 (input_bfd, value, contents + rel->r_offset);
12398 break;
12399
12400 case R_ARM_THM_MOVW_ABS_NC:
12401 case R_ARM_THM_MOVT_ABS:
12402 value = (value & 0xfbf08f00) | ((addend & 0xf700) << 4)
12403 | (addend & 0xff) | ((addend & 0x0800) << 15);
12404 bfd_put_16 (input_bfd, value >> 16,
12405 contents + rel->r_offset);
12406 bfd_put_16 (input_bfd, value,
12407 contents + rel->r_offset + 2);
12408 break;
12409
12410 default:
12411 value = (value & ~ howto->dst_mask)
12412 | (addend & howto->dst_mask);
12413 bfd_put_32 (input_bfd, value, contents + rel->r_offset);
12414 break;
12415 }
f8df10f4 12416 }
f8df10f4 12417 }
4e7fd91e
PB		 12418 else
12419 relocation = _bfd_elf_rela_local_sym (output_bfd, sym, &sec, rel);
252b5132
RH		 12420 }
12421 else
12422 {
62d887d4 12423 bfd_boolean warned, ignored;
560e09e9 12424
b2a8e766
AM		 12425 RELOC_FOR_GLOBAL_SYMBOL (info, input_bfd, input_section, rel,
12426 r_symndx, symtab_hdr, sym_hashes,
12427 h, sec, relocation,
62d887d4 12428 unresolved_reloc, warned, ignored);
ba93b8ac
DJ		 12429
12430 sym_type = h->type;
252b5132
RH		 12431 }
12432
dbaa2011 12433 if (sec != NULL && discarded_section (sec))
e4067dbb 12434 RELOC_AGAINST_DISCARDED_SECTION (info, input_bfd, input_section,
545fd46b 12435 rel, 1, relend, howto, 0, contents);
ab96bf03 12436
0e1862bb 12437 if (bfd_link_relocatable (info))
ab96bf03
AM		 12438 {
12439 /* This is a relocatable link. We don't have to change
12440 anything, unless the reloc is against a section symbol,
12441 in which case we have to adjust according to where the
12442 section symbol winds up in the output section. */
12443 if (sym != NULL && ELF_ST_TYPE (sym->st_info) == STT_SECTION)
12444 {
12445 if (globals->use_rel)
12446 arm_add_to_rel (input_bfd, contents + rel->r_offset,
12447 howto, (bfd_signed_vma) sec->output_offset);
12448 else
12449 rel->r_addend += sec->output_offset;
12450 }
12451 continue;
12452 }
12453
252b5132
RH		 12454 if (h != NULL)
12455 name = h->root.root.string;
12456 else
12457 {
12458 name = (bfd_elf_string_from_elf_section
12459 (input_bfd, symtab_hdr->sh_link, sym->st_name));
12460 if (name == NULL || *name == '\0')
12461 name = bfd_section_name (input_bfd, sec);
12462 }
f21f3fe0 12463
cf35638d 12464 if (r_symndx != STN_UNDEF
ba93b8ac
DJ		 12465 && r_type != R_ARM_NONE
12466 && (h == NULL
12467 || h->root.type == bfd_link_hash_defined
12468 || h->root.type == bfd_link_hash_defweak)
12469 && IS_ARM_TLS_RELOC (r_type) != (sym_type == STT_TLS))
12470 {
4eca0228 12471 _bfd_error_handler
ba93b8ac
DJ		 12472 ((sym_type == STT_TLS
12473 ? _("%B(%A+0x%lx): %s used with TLS symbol %s")
12474 : _("%B(%A+0x%lx): %s used with non-TLS symbol %s")),
12475 input_bfd,
12476 input_section,
12477 (long) rel->r_offset,
12478 howto->name,
12479 name);
12480 }
12481
0855e32b 12482 /* We call elf32_arm_final_link_relocate unless we're completely
99059e56
RM		 12483 done, i.e., the relaxation produced the final output we want,
12484 and we won't let anybody mess with it. Also, we have to do
12485 addend adjustments in case of a R_ARM_TLS_GOTDESC relocation
6a631e86 12486 both in relaxed and non-relaxed cases. */
39d911fc
TP		 12487 if ((elf32_arm_tls_transition (info, r_type, h) != (unsigned)r_type)
12488 || (IS_ARM_TLS_GNU_RELOC (r_type)
12489 && !((h ? elf32_arm_hash_entry (h)->tls_type :
12490 elf32_arm_local_got_tls_type (input_bfd)[r_symndx])
12491 & GOT_TLS_GDESC)))
12492 {
12493 r = elf32_arm_tls_relax (globals, input_bfd, input_section,
12494 contents, rel, h == NULL);
12495 /* This may have been marked unresolved because it came from
12496 a shared library. But we've just dealt with that. */
12497 unresolved_reloc = 0;
12498 }
12499 else
12500 r = bfd_reloc_continue;
b38cadfb 12501
39d911fc
TP		 12502 if (r == bfd_reloc_continue)
12503 {
12504 unsigned char branch_type =
12505 h ? ARM_GET_SYM_BRANCH_TYPE (h->target_internal)
12506 : ARM_GET_SYM_BRANCH_TYPE (sym->st_target_internal);
12507
12508 r = elf32_arm_final_link_relocate (howto, input_bfd, output_bfd,
12509 input_section, contents, rel,
12510 relocation, info, sec, name,
12511 sym_type, branch_type, h,
12512 &unresolved_reloc,
12513 &error_message);
12514 }
0945cdfd
DJ		 12515
12516 /* Dynamic relocs are not propagated for SEC_DEBUGGING sections
12517 because such sections are not SEC_ALLOC and thus ld.so will
12518 not process them. */
12519 if (unresolved_reloc
99059e56
RM		 12520 && !((input_section->flags & SEC_DEBUGGING) != 0
12521 && h->def_dynamic)
1d5316ab
AM		 12522 && _bfd_elf_section_offset (output_bfd, info, input_section,
12523 rel->r_offset) != (bfd_vma) -1)
0945cdfd 12524 {
4eca0228 12525 _bfd_error_handler
843fe662
L		 12526 (_("%B(%A+0x%lx): unresolvable %s relocation against symbol `%s'"),
12527 input_bfd,
12528 input_section,
12529 (long) rel->r_offset,
12530 howto->name,
12531 h->root.root.string);
0945cdfd
DJ		 12532 return FALSE;
12533 }
252b5132
RH		 12534
12535 if (r != bfd_reloc_ok)
12536 {
252b5132
RH		 12537 switch (r)
12538 {
12539 case bfd_reloc_overflow:
cf919dfd
PB		 12540 /* If the overflowing reloc was to an undefined symbol,
12541 we have already printed one error message and there
12542 is no point complaining again. */
1a72702b
AM		 12543 if (!h || h->root.type != bfd_link_hash_undefined)
12544 (*info->callbacks->reloc_overflow)
12545 (info, (h ? &h->root : NULL), name, howto->name,
12546 (bfd_vma) 0, input_bfd, input_section, rel->r_offset);
252b5132
RH		 12547 break;
12548
12549 case bfd_reloc_undefined:
1a72702b
AM		 12550 (*info->callbacks->undefined_symbol)
12551 (info, name, input_bfd, input_section, rel->r_offset, TRUE);
252b5132
RH		 12552 break;
12553
12554 case bfd_reloc_outofrange:
f2a9dd69 12555 error_message = _("out of range");
252b5132
RH		 12556 goto common_error;
12557
12558 case bfd_reloc_notsupported:
f2a9dd69 12559 error_message = _("unsupported relocation");
252b5132
RH		 12560 goto common_error;
12561
12562 case bfd_reloc_dangerous:
f2a9dd69 12563 /* error_message should already be set. */
252b5132
RH		 12564 goto common_error;
12565
12566 default:
f2a9dd69 12567 error_message = _("unknown error");
8029a119 12568 /* Fall through. */
252b5132
RH		 12569
12570 common_error:
f2a9dd69 12571 BFD_ASSERT (error_message != NULL);
1a72702b
AM		 12572 (*info->callbacks->reloc_dangerous)
12573 (info, error_message, input_bfd, input_section, rel->r_offset);
252b5132
RH		 12574 break;
12575 }
12576 }
12577 }
12578
b34976b6 12579 return TRUE;
252b5132
RH		 12580}
12581
91d6fa6a 12582/* Add a new unwind edit to the list described by HEAD, TAIL. If TINDEX is zero,
2468f9c9 12583 adds the edit to the start of the list. (The list must be built in order of
91d6fa6a 12584 ascending TINDEX: the function's callers are primarily responsible for
2468f9c9
PB		 12585 maintaining that condition). */
12586
12587static void
12588add_unwind_table_edit (arm_unwind_table_edit **head,
12589 arm_unwind_table_edit **tail,
12590 arm_unwind_edit_type type,
12591 asection *linked_section,
91d6fa6a 12592 unsigned int tindex)
2468f9c9 12593{
21d799b5
NC		 12594 arm_unwind_table_edit *new_edit = (arm_unwind_table_edit *)
12595 xmalloc (sizeof (arm_unwind_table_edit));
b38cadfb 12596
2468f9c9
PB		 12597 new_edit->type = type;
12598 new_edit->linked_section = linked_section;
91d6fa6a 12599 new_edit->index = tindex;
b38cadfb 12600
91d6fa6a 12601 if (tindex > 0)
2468f9c9
PB		 12602 {
12603 new_edit->next = NULL;
12604
12605 if (*tail)
12606 (*tail)->next = new_edit;
12607
12608 (*tail) = new_edit;
12609
12610 if (!*head)
12611 (*head) = new_edit;
12612 }
12613 else
12614 {
12615 new_edit->next = *head;
12616
12617 if (!*tail)
12618 *tail = new_edit;
12619
12620 *head = new_edit;
12621 }
12622}
12623
12624static _arm_elf_section_data *get_arm_elf_section_data (asection *);
12625
12626/* Increase the size of EXIDX_SEC by ADJUST bytes. ADJUST mau be negative. */
12627static void
12628adjust_exidx_size(asection *exidx_sec, int adjust)
12629{
12630 asection *out_sec;
12631
12632 if (!exidx_sec->rawsize)
12633 exidx_sec->rawsize = exidx_sec->size;
12634
12635 bfd_set_section_size (exidx_sec->owner, exidx_sec, exidx_sec->size + adjust);
12636 out_sec = exidx_sec->output_section;
12637 /* Adjust size of output section. */
12638 bfd_set_section_size (out_sec->owner, out_sec, out_sec->size +adjust);
12639}
12640
12641/* Insert an EXIDX_CANTUNWIND marker at the end of a section. */
12642static void
12643insert_cantunwind_after(asection *text_sec, asection *exidx_sec)
12644{
12645 struct _arm_elf_section_data *exidx_arm_data;
12646
12647 exidx_arm_data = get_arm_elf_section_data (exidx_sec);
12648 add_unwind_table_edit (
12649 &exidx_arm_data->u.exidx.unwind_edit_list,
12650 &exidx_arm_data->u.exidx.unwind_edit_tail,
12651 INSERT_EXIDX_CANTUNWIND_AT_END, text_sec, UINT_MAX);
12652
491d01d3
YU		 12653 exidx_arm_data->additional_reloc_count++;
12654
2468f9c9
PB		 12655 adjust_exidx_size(exidx_sec, 8);
12656}
12657
12658/* Scan .ARM.exidx tables, and create a list describing edits which should be
12659 made to those tables, such that:
b38cadfb 12660
2468f9c9
PB		 12661 1. Regions without unwind data are marked with EXIDX_CANTUNWIND entries.
12662 2. Duplicate entries are merged together (EXIDX_CANTUNWIND, or unwind
99059e56 12663 codes which have been inlined into the index).
2468f9c9 12664
85fdf906
AH		 12665 If MERGE_EXIDX_ENTRIES is false, duplicate entries are not merged.
12666
2468f9c9 12667 The edits are applied when the tables are written
b38cadfb 12668 (in elf32_arm_write_section). */
2468f9c9
PB		 12669
12670bfd_boolean
12671elf32_arm_fix_exidx_coverage (asection **text_section_order,
12672 unsigned int num_text_sections,
85fdf906
AH		 12673 struct bfd_link_info *info,
12674 bfd_boolean merge_exidx_entries)
2468f9c9
PB		 12675{
12676 bfd *inp;
12677 unsigned int last_second_word = 0, i;
12678 asection *last_exidx_sec = NULL;
12679 asection *last_text_sec = NULL;
12680 int last_unwind_type = -1;
12681
12682 /* Walk over all EXIDX sections, and create backlinks from the corrsponding
12683 text sections. */
c72f2fb2 12684 for (inp = info->input_bfds; inp != NULL; inp = inp->link.next)
2468f9c9
PB		 12685 {
12686 asection *sec;
b38cadfb 12687
2468f9c9 12688 for (sec = inp->sections; sec != NULL; sec = sec->next)
99059e56 12689 {
2468f9c9
PB		 12690 struct bfd_elf_section_data *elf_sec = elf_section_data (sec);
12691 Elf_Internal_Shdr *hdr = &elf_sec->this_hdr;
b38cadfb 12692
dec9d5df 12693 if (!hdr || hdr->sh_type != SHT_ARM_EXIDX)
2468f9c9 12694 continue;
b38cadfb 12695
2468f9c9
PB		 12696 if (elf_sec->linked_to)
12697 {
12698 Elf_Internal_Shdr *linked_hdr
99059e56 12699 = &elf_section_data (elf_sec->linked_to)->this_hdr;
2468f9c9 12700 struct _arm_elf_section_data *linked_sec_arm_data
99059e56 12701 = get_arm_elf_section_data (linked_hdr->bfd_section);
2468f9c9
PB		 12702
12703 if (linked_sec_arm_data == NULL)
99059e56 12704 continue;
2468f9c9
PB		 12705
12706 /* Link this .ARM.exidx section back from the text section it
99059e56 12707 describes. */
2468f9c9
PB		 12708 linked_sec_arm_data->u.text.arm_exidx_sec = sec;
12709 }
12710 }
12711 }
12712
12713 /* Walk all text sections in order of increasing VMA. Eilminate duplicate
12714 index table entries (EXIDX_CANTUNWIND and inlined unwind opcodes),
91d6fa6a 12715 and add EXIDX_CANTUNWIND entries for sections with no unwind table data. */
2468f9c9
PB		 12716
12717 for (i = 0; i < num_text_sections; i++)
12718 {
12719 asection *sec = text_section_order[i];
12720 asection *exidx_sec;
12721 struct _arm_elf_section_data *arm_data = get_arm_elf_section_data (sec);
12722 struct _arm_elf_section_data *exidx_arm_data;
12723 bfd_byte *contents = NULL;
12724 int deleted_exidx_bytes = 0;
12725 bfd_vma j;
12726 arm_unwind_table_edit *unwind_edit_head = NULL;
12727 arm_unwind_table_edit *unwind_edit_tail = NULL;
12728 Elf_Internal_Shdr *hdr;
12729 bfd *ibfd;
12730
12731 if (arm_data == NULL)
99059e56 12732 continue;
2468f9c9
PB		 12733
12734 exidx_sec = arm_data->u.text.arm_exidx_sec;
12735 if (exidx_sec == NULL)
12736 {
12737 /* Section has no unwind data. */
12738 if (last_unwind_type == 0 || !last_exidx_sec)
12739 continue;
12740
12741 /* Ignore zero sized sections. */
12742 if (sec->size == 0)
12743 continue;
12744
12745 insert_cantunwind_after(last_text_sec, last_exidx_sec);
12746 last_unwind_type = 0;
12747 continue;
12748 }
12749
22a8f80e
PB		 12750 /* Skip /DISCARD/ sections. */
12751 if (bfd_is_abs_section (exidx_sec->output_section))
12752 continue;
12753
2468f9c9
PB		 12754 hdr = &elf_section_data (exidx_sec)->this_hdr;
12755 if (hdr->sh_type != SHT_ARM_EXIDX)
99059e56 12756 continue;
b38cadfb 12757
2468f9c9
PB		 12758 exidx_arm_data = get_arm_elf_section_data (exidx_sec);
12759 if (exidx_arm_data == NULL)
99059e56 12760 continue;
b38cadfb 12761
2468f9c9 12762 ibfd = exidx_sec->owner;
b38cadfb 12763
2468f9c9
PB		 12764 if (hdr->contents != NULL)
12765 contents = hdr->contents;
12766 else if (! bfd_malloc_and_get_section (ibfd, exidx_sec, &contents))
12767 /* An error? */
12768 continue;
12769
ac06903d
YU		 12770 if (last_unwind_type > 0)
12771 {
12772 unsigned int first_word = bfd_get_32 (ibfd, contents);
12773 /* Add cantunwind if first unwind item does not match section
12774 start. */
12775 if (first_word != sec->vma)
12776 {
12777 insert_cantunwind_after (last_text_sec, last_exidx_sec);
12778 last_unwind_type = 0;
12779 }
12780 }
12781
2468f9c9
PB		 12782 for (j = 0; j < hdr->sh_size; j += 8)
12783 {
12784 unsigned int second_word = bfd_get_32 (ibfd, contents + j + 4);
12785 int unwind_type;
12786 int elide = 0;
12787
12788 /* An EXIDX_CANTUNWIND entry. */
12789 if (second_word == 1)
12790 {
12791 if (last_unwind_type == 0)
12792 elide = 1;
12793 unwind_type = 0;
12794 }
12795 /* Inlined unwinding data. Merge if equal to previous. */
12796 else if ((second_word & 0x80000000) != 0)
12797 {
85fdf906
AH		 12798 if (merge_exidx_entries
12799 && last_second_word == second_word && last_unwind_type == 1)
2468f9c9
PB		 12800 elide = 1;
12801 unwind_type = 1;
12802 last_second_word = second_word;
12803 }
12804 /* Normal table entry. In theory we could merge these too,
12805 but duplicate entries are likely to be much less common. */
12806 else
12807 unwind_type = 2;
12808
491d01d3 12809 if (elide && !bfd_link_relocatable (info))
2468f9c9
PB		 12810 {
12811 add_unwind_table_edit (&unwind_edit_head, &unwind_edit_tail,
12812 DELETE_EXIDX_ENTRY, NULL, j / 8);
12813
12814 deleted_exidx_bytes += 8;
12815 }
12816
12817 last_unwind_type = unwind_type;
12818 }
12819
12820 /* Free contents if we allocated it ourselves. */
12821 if (contents != hdr->contents)
99059e56 12822 free (contents);
2468f9c9
PB		 12823
12824 /* Record edits to be applied later (in elf32_arm_write_section). */
12825 exidx_arm_data->u.exidx.unwind_edit_list = unwind_edit_head;
12826 exidx_arm_data->u.exidx.unwind_edit_tail = unwind_edit_tail;
b38cadfb 12827
2468f9c9
PB		 12828 if (deleted_exidx_bytes > 0)
12829 adjust_exidx_size(exidx_sec, -deleted_exidx_bytes);
12830
12831 last_exidx_sec = exidx_sec;
12832 last_text_sec = sec;
12833 }
12834
12835 /* Add terminating CANTUNWIND entry. */
491d01d3
YU		 12836 if (!bfd_link_relocatable (info) && last_exidx_sec
12837 && last_unwind_type != 0)
2468f9c9
PB		 12838 insert_cantunwind_after(last_text_sec, last_exidx_sec);
12839
12840 return TRUE;
12841}
12842
3e6b1042
DJ		 12843static bfd_boolean
12844elf32_arm_output_glue_section (struct bfd_link_info *info, bfd *obfd,
12845 bfd *ibfd, const char *name)
12846{
12847 asection *sec, *osec;
12848
3d4d4302 12849 sec = bfd_get_linker_section (ibfd, name);
3e6b1042
DJ		 12850 if (sec == NULL || (sec->flags & SEC_EXCLUDE) != 0)
12851 return TRUE;
12852
12853 osec = sec->output_section;
12854 if (elf32_arm_write_section (obfd, info, sec, sec->contents))
12855 return TRUE;
12856
12857 if (! bfd_set_section_contents (obfd, osec, sec->contents,
12858 sec->output_offset, sec->size))
12859 return FALSE;
12860
12861 return TRUE;
12862}
12863
12864static bfd_boolean
12865elf32_arm_final_link (bfd *abfd, struct bfd_link_info *info)
12866{
12867 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (info);
fe33d2fa 12868 asection *sec, *osec;
3e6b1042 12869
4dfe6ac6
NC		 12870 if (globals == NULL)
12871 return FALSE;
12872
3e6b1042
DJ		 12873 /* Invoke the regular ELF backend linker to do all the work. */
12874 if (!bfd_elf_final_link (abfd, info))
12875 return FALSE;
12876
fe33d2fa
CL		 12877 /* Process stub sections (eg BE8 encoding, ...). */
12878 struct elf32_arm_link_hash_table *htab = elf32_arm_hash_table (info);
7292b3ac 12879 unsigned int i;
cdb21a0a
NS		 12880 for (i=0; i<htab->top_id; i++)
12881 {
12882 sec = htab->stub_group[i].stub_sec;
12883 /* Only process it once, in its link_sec slot. */
12884 if (sec && i == htab->stub_group[i].link_sec->id)
12885 {
12886 osec = sec->output_section;
12887 elf32_arm_write_section (abfd, info, sec, sec->contents);
12888 if (! bfd_set_section_contents (abfd, osec, sec->contents,
12889 sec->output_offset, sec->size))
12890 return FALSE;
12891 }
fe33d2fa 12892 }
fe33d2fa 12893
3e6b1042
DJ		 12894 /* Write out any glue sections now that we have created all the
12895 stubs. */
12896 if (globals->bfd_of_glue_owner != NULL)
12897 {
12898 if (! elf32_arm_output_glue_section (info, abfd,
12899 globals->bfd_of_glue_owner,
12900 ARM2THUMB_GLUE_SECTION_NAME))
12901 return FALSE;
12902
12903 if (! elf32_arm_output_glue_section (info, abfd,
12904 globals->bfd_of_glue_owner,
12905 THUMB2ARM_GLUE_SECTION_NAME))
12906 return FALSE;
12907
12908 if (! elf32_arm_output_glue_section (info, abfd,
12909 globals->bfd_of_glue_owner,
12910 VFP11_ERRATUM_VENEER_SECTION_NAME))
12911 return FALSE;
12912
a504d23a
LA		 12913 if (! elf32_arm_output_glue_section (info, abfd,
12914 globals->bfd_of_glue_owner,
12915 STM32L4XX_ERRATUM_VENEER_SECTION_NAME))
12916 return FALSE;
12917
3e6b1042
DJ		 12918 if (! elf32_arm_output_glue_section (info, abfd,
12919 globals->bfd_of_glue_owner,
12920 ARM_BX_GLUE_SECTION_NAME))
12921 return FALSE;
12922 }
12923
12924 return TRUE;
12925}
12926
5968a7b8
NC		 12927/* Return a best guess for the machine number based on the attributes. */
12928
12929static unsigned int
12930bfd_arm_get_mach_from_attributes (bfd * abfd)
12931{
12932 int arch = bfd_elf_get_obj_attr_int (abfd, OBJ_ATTR_PROC, Tag_CPU_arch);
12933
12934 switch (arch)
12935 {
12936 case TAG_CPU_ARCH_V4: return bfd_mach_arm_4;
12937 case TAG_CPU_ARCH_V4T: return bfd_mach_arm_4T;
12938 case TAG_CPU_ARCH_V5T: return bfd_mach_arm_5T;
12939
12940 case TAG_CPU_ARCH_V5TE:
12941 {
12942 char * name;
12943
12944 BFD_ASSERT (Tag_CPU_name < NUM_KNOWN_OBJ_ATTRIBUTES);
12945 name = elf_known_obj_attributes (abfd) [OBJ_ATTR_PROC][Tag_CPU_name].s;
12946
12947 if (name)
12948 {
12949 if (strcmp (name, "IWMMXT2") == 0)
12950 return bfd_mach_arm_iWMMXt2;
12951
12952 if (strcmp (name, "IWMMXT") == 0)
6034aab8 12953 return bfd_mach_arm_iWMMXt;
088ca6c1
NC		 12954
12955 if (strcmp (name, "XSCALE") == 0)
12956 {
12957 int wmmx;
12958
12959 BFD_ASSERT (Tag_WMMX_arch < NUM_KNOWN_OBJ_ATTRIBUTES);
12960 wmmx = elf_known_obj_attributes (abfd) [OBJ_ATTR_PROC][Tag_WMMX_arch].i;
12961 switch (wmmx)
12962 {
12963 case 1: return bfd_mach_arm_iWMMXt;
12964 case 2: return bfd_mach_arm_iWMMXt2;
12965 default: return bfd_mach_arm_XScale;
12966 }
12967 }
5968a7b8
NC		 12968 }
12969
12970 return bfd_mach_arm_5TE;
12971 }
12972
12973 default:
12974 return bfd_mach_arm_unknown;
12975 }
12976}
12977
c178919b
NC		 12978/* Set the right machine number. */
12979
12980static bfd_boolean
57e8b36a 12981elf32_arm_object_p (bfd *abfd)
c178919b 12982{
5a6c6817 12983 unsigned int mach;
57e8b36a 12984
5a6c6817 12985 mach = bfd_arm_get_mach_from_notes (abfd, ARM_NOTE_SECTION);
c178919b 12986
5968a7b8
NC		 12987 if (mach == bfd_mach_arm_unknown)
12988 {
12989 if (elf_elfheader (abfd)->e_flags & EF_ARM_MAVERICK_FLOAT)
12990 mach = bfd_mach_arm_ep9312;
12991 else
12992 mach = bfd_arm_get_mach_from_attributes (abfd);
12993 }
c178919b 12994
5968a7b8 12995 bfd_default_set_arch_mach (abfd, bfd_arch_arm, mach);
c178919b
NC		 12996 return TRUE;
12997}
12998
fc830a83 12999/* Function to keep ARM specific flags in the ELF header. */
3c9458e9 13000
b34976b6 13001static bfd_boolean
57e8b36a 13002elf32_arm_set_private_flags (bfd *abfd, flagword flags)
252b5132
RH		 13003{
13004 if (elf_flags_init (abfd)
13005 && elf_elfheader (abfd)->e_flags != flags)
13006 {
fc830a83
NC		 13007 if (EF_ARM_EABI_VERSION (flags) == EF_ARM_EABI_UNKNOWN)
13008 {
fd2ec330 13009 if (flags & EF_ARM_INTERWORK)
4eca0228 13010 _bfd_error_handler
d003868e
AM		 13011 (_("Warning: Not setting interworking flag of %B since it has already been specified as non-interworking"),
13012 abfd);
fc830a83 13013 else
d003868e
AM		 13014 _bfd_error_handler
13015 (_("Warning: Clearing the interworking flag of %B due to outside request"),
13016 abfd);
fc830a83 13017 }
252b5132
RH		 13018 }
13019 else
13020 {
13021 elf_elfheader (abfd)->e_flags = flags;
b34976b6 13022 elf_flags_init (abfd) = TRUE;
252b5132
RH		 13023 }
13024
b34976b6 13025 return TRUE;
252b5132
RH		 13026}
13027
fc830a83 13028/* Copy backend specific data from one object module to another. */
9b485d32 13029
b34976b6 13030static bfd_boolean
57e8b36a 13031elf32_arm_copy_private_bfd_data (bfd *ibfd, bfd *obfd)
252b5132
RH		 13032{
13033 flagword in_flags;
13034 flagword out_flags;
13035
0ffa91dd 13036 if (! is_arm_elf (ibfd) || ! is_arm_elf (obfd))
b34976b6 13037 return TRUE;
252b5132 13038
fc830a83 13039 in_flags = elf_elfheader (ibfd)->e_flags;
252b5132
RH		 13040 out_flags = elf_elfheader (obfd)->e_flags;
13041
fc830a83
NC		 13042 if (elf_flags_init (obfd)
13043 && EF_ARM_EABI_VERSION (out_flags) == EF_ARM_EABI_UNKNOWN
13044 && in_flags != out_flags)
252b5132 13045 {
252b5132 13046 /* Cannot mix APCS26 and APCS32 code. */
fd2ec330 13047 if ((in_flags & EF_ARM_APCS_26) != (out_flags & EF_ARM_APCS_26))
b34976b6 13048 return FALSE;
252b5132
RH		 13049
13050 /* Cannot mix float APCS and non-float APCS code. */
fd2ec330 13051 if ((in_flags & EF_ARM_APCS_FLOAT) != (out_flags & EF_ARM_APCS_FLOAT))
b34976b6 13052 return FALSE;
252b5132
RH		 13053
13054 /* If the src and dest have different interworking flags
99059e56 13055 then turn off the interworking bit. */
fd2ec330 13056 if ((in_flags & EF_ARM_INTERWORK) != (out_flags & EF_ARM_INTERWORK))
252b5132 13057 {
fd2ec330 13058 if (out_flags & EF_ARM_INTERWORK)
d003868e
AM		 13059 _bfd_error_handler
13060 (_("Warning: Clearing the interworking flag of %B because non-interworking code in %B has been linked with it"),
13061 obfd, ibfd);
252b5132 13062
fd2ec330 13063 in_flags &= ~EF_ARM_INTERWORK;
252b5132 13064 }
1006ba19
PB		 13065
13066 /* Likewise for PIC, though don't warn for this case. */
fd2ec330
PB		 13067 if ((in_flags & EF_ARM_PIC) != (out_flags & EF_ARM_PIC))
13068 in_flags &= ~EF_ARM_PIC;
252b5132
RH		 13069 }
13070
13071 elf_elfheader (obfd)->e_flags = in_flags;
b34976b6 13072 elf_flags_init (obfd) = TRUE;
252b5132 13073
e2349352 13074 return _bfd_elf_copy_private_bfd_data (ibfd, obfd);
ee065d83
PB		 13075}
13076
13077/* Values for Tag_ABI_PCS_R9_use. */
13078enum
13079{
13080 AEABI_R9_V6,
13081 AEABI_R9_SB,
13082 AEABI_R9_TLS,
13083 AEABI_R9_unused
13084};
13085
13086/* Values for Tag_ABI_PCS_RW_data. */
13087enum
13088{
13089 AEABI_PCS_RW_data_absolute,
13090 AEABI_PCS_RW_data_PCrel,
13091 AEABI_PCS_RW_data_SBrel,
13092 AEABI_PCS_RW_data_unused
13093};
13094
13095/* Values for Tag_ABI_enum_size. */
13096enum
13097{
13098 AEABI_enum_unused,
13099 AEABI_enum_short,
13100 AEABI_enum_wide,
13101 AEABI_enum_forced_wide
13102};
13103
104d59d1
JM		 13104/* Determine whether an object attribute tag takes an integer, a
13105 string or both. */
906e58ca 13106
104d59d1
JM		 13107static int
13108elf32_arm_obj_attrs_arg_type (int tag)
13109{
13110 if (tag == Tag_compatibility)
3483fe2e 13111 return ATTR_TYPE_FLAG_INT_VAL | ATTR_TYPE_FLAG_STR_VAL;
2d0bb761 13112 else if (tag == Tag_nodefaults)
3483fe2e
AS		 13113 return ATTR_TYPE_FLAG_INT_VAL | ATTR_TYPE_FLAG_NO_DEFAULT;
13114 else if (tag == Tag_CPU_raw_name || tag == Tag_CPU_name)
13115 return ATTR_TYPE_FLAG_STR_VAL;
104d59d1 13116 else if (tag < 32)
3483fe2e 13117 return ATTR_TYPE_FLAG_INT_VAL;
104d59d1 13118 else
3483fe2e 13119 return (tag & 1) != 0 ? ATTR_TYPE_FLAG_STR_VAL : ATTR_TYPE_FLAG_INT_VAL;
104d59d1
JM		 13120}
13121
5aa6ff7c
AS		 13122/* The ABI defines that Tag_conformance should be emitted first, and that
13123 Tag_nodefaults should be second (if either is defined). This sets those
13124 two positions, and bumps up the position of all the remaining tags to
13125 compensate. */
13126static int
13127elf32_arm_obj_attrs_order (int num)
13128{
3de4a297 13129 if (num == LEAST_KNOWN_OBJ_ATTRIBUTE)
5aa6ff7c 13130 return Tag_conformance;
3de4a297 13131 if (num == LEAST_KNOWN_OBJ_ATTRIBUTE + 1)
5aa6ff7c
AS		 13132 return Tag_nodefaults;
13133 if ((num - 2) < Tag_nodefaults)
13134 return num - 2;
13135 if ((num - 1) < Tag_conformance)
13136 return num - 1;
13137 return num;
13138}
13139
e8b36cd1
JM		 13140/* Attribute numbers >=64 (mod 128) can be safely ignored. */
13141static bfd_boolean
13142elf32_arm_obj_attrs_handle_unknown (bfd *abfd, int tag)
13143{
13144 if ((tag & 127) < 64)
13145 {
13146 _bfd_error_handler
13147 (_("%B: Unknown mandatory EABI object attribute %d"),
13148 abfd, tag);
13149 bfd_set_error (bfd_error_bad_value);
13150 return FALSE;
13151 }
13152 else
13153 {
13154 _bfd_error_handler
13155 (_("Warning: %B: Unknown EABI object attribute %d"),
13156 abfd, tag);
13157 return TRUE;
13158 }
13159}
13160
91e22acd
AS		 13161/* Read the architecture from the Tag_also_compatible_with attribute, if any.
13162 Returns -1 if no architecture could be read. */
13163
13164static int
13165get_secondary_compatible_arch (bfd *abfd)
13166{
13167 obj_attribute *attr =
13168 &elf_known_obj_attributes_proc (abfd)[Tag_also_compatible_with];
13169
13170 /* Note: the tag and its argument below are uleb128 values, though
13171 currently-defined values fit in one byte for each. */
13172 if (attr->s
13173 && attr->s[0] == Tag_CPU_arch
13174 && (attr->s[1] & 128) != 128
13175 && attr->s[2] == 0)
13176 return attr->s[1];
13177
13178 /* This tag is "safely ignorable", so don't complain if it looks funny. */
13179 return -1;
13180}
13181
13182/* Set, or unset, the architecture of the Tag_also_compatible_with attribute.
13183 The tag is removed if ARCH is -1. */
13184
8e79c3df 13185static void
91e22acd 13186set_secondary_compatible_arch (bfd *abfd, int arch)
8e79c3df 13187{
91e22acd
AS		 13188 obj_attribute *attr =
13189 &elf_known_obj_attributes_proc (abfd)[Tag_also_compatible_with];
8e79c3df 13190
91e22acd
AS		 13191 if (arch == -1)
13192 {
13193 attr->s = NULL;
13194 return;
8e79c3df 13195 }
91e22acd
AS		 13196
13197 /* Note: the tag and its argument below are uleb128 values, though
13198 currently-defined values fit in one byte for each. */
13199 if (!attr->s)
21d799b5 13200 attr->s = (char *) bfd_alloc (abfd, 3);
91e22acd
AS		 13201 attr->s[0] = Tag_CPU_arch;
13202 attr->s[1] = arch;
13203 attr->s[2] = '\0';
8e79c3df
CM		 13204}
13205
91e22acd
AS		 13206/* Combine two values for Tag_CPU_arch, taking secondary compatibility tags
13207 into account. */
13208
13209static int
13210tag_cpu_arch_combine (bfd *ibfd, int oldtag, int *secondary_compat_out,
13211 int newtag, int secondary_compat)
8e79c3df 13212{
91e22acd
AS		 13213#define T(X) TAG_CPU_ARCH_##X
13214 int tagl, tagh, result;
13215 const int v6t2[] =
13216 {
13217 T(V6T2), /* PRE_V4. */
13218 T(V6T2), /* V4. */
13219 T(V6T2), /* V4T. */
13220 T(V6T2), /* V5T. */
13221 T(V6T2), /* V5TE. */
13222 T(V6T2), /* V5TEJ. */
13223 T(V6T2), /* V6. */
13224 T(V7), /* V6KZ. */
13225 T(V6T2) /* V6T2. */
13226 };
13227 const int v6k[] =
13228 {
13229 T(V6K), /* PRE_V4. */
13230 T(V6K), /* V4. */
13231 T(V6K), /* V4T. */
13232 T(V6K), /* V5T. */
13233 T(V6K), /* V5TE. */
13234 T(V6K), /* V5TEJ. */
13235 T(V6K), /* V6. */
13236 T(V6KZ), /* V6KZ. */
13237 T(V7), /* V6T2. */
13238 T(V6K) /* V6K. */
13239 };
13240 const int v7[] =
13241 {
13242 T(V7), /* PRE_V4. */
13243 T(V7), /* V4. */
13244 T(V7), /* V4T. */
13245 T(V7), /* V5T. */
13246 T(V7), /* V5TE. */
13247 T(V7), /* V5TEJ. */
13248 T(V7), /* V6. */
13249 T(V7), /* V6KZ. */
13250 T(V7), /* V6T2. */
13251 T(V7), /* V6K. */
13252 T(V7) /* V7. */
13253 };
13254 const int v6_m[] =
13255 {
13256 -1, /* PRE_V4. */
13257 -1, /* V4. */
13258 T(V6K), /* V4T. */
13259 T(V6K), /* V5T. */
13260 T(V6K), /* V5TE. */
13261 T(V6K), /* V5TEJ. */
13262 T(V6K), /* V6. */
13263 T(V6KZ), /* V6KZ. */
13264 T(V7), /* V6T2. */
13265 T(V6K), /* V6K. */
13266 T(V7), /* V7. */
13267 T(V6_M) /* V6_M. */
13268 };
13269 const int v6s_m[] =
13270 {
13271 -1, /* PRE_V4. */
13272 -1, /* V4. */
13273 T(V6K), /* V4T. */
13274 T(V6K), /* V5T. */
13275 T(V6K), /* V5TE. */
13276 T(V6K), /* V5TEJ. */
13277 T(V6K), /* V6. */
13278 T(V6KZ), /* V6KZ. */
13279 T(V7), /* V6T2. */
13280 T(V6K), /* V6K. */
13281 T(V7), /* V7. */
13282 T(V6S_M), /* V6_M. */
13283 T(V6S_M) /* V6S_M. */
13284 };
9e3c6df6
PB		 13285 const int v7e_m[] =
13286 {
13287 -1, /* PRE_V4. */
13288 -1, /* V4. */
13289 T(V7E_M), /* V4T. */
13290 T(V7E_M), /* V5T. */
13291 T(V7E_M), /* V5TE. */
13292 T(V7E_M), /* V5TEJ. */
13293 T(V7E_M), /* V6. */
13294 T(V7E_M), /* V6KZ. */
13295 T(V7E_M), /* V6T2. */
13296 T(V7E_M), /* V6K. */
13297 T(V7E_M), /* V7. */
13298 T(V7E_M), /* V6_M. */
13299 T(V7E_M), /* V6S_M. */
13300 T(V7E_M) /* V7E_M. */
13301 };
bca38921
MGD		 13302 const int v8[] =
13303 {
13304 T(V8), /* PRE_V4. */
13305 T(V8), /* V4. */
13306 T(V8), /* V4T. */
13307 T(V8), /* V5T. */
13308 T(V8), /* V5TE. */
13309 T(V8), /* V5TEJ. */
13310 T(V8), /* V6. */
13311 T(V8), /* V6KZ. */
13312 T(V8), /* V6T2. */
13313 T(V8), /* V6K. */
13314 T(V8), /* V7. */
13315 T(V8), /* V6_M. */
13316 T(V8), /* V6S_M. */
13317 T(V8), /* V7E_M. */
13318 T(V8) /* V8. */
13319 };
2fd158eb
TP		 13320 const int v8m_baseline[] =
13321 {
13322 -1, /* PRE_V4. */
13323 -1, /* V4. */
13324 -1, /* V4T. */
13325 -1, /* V5T. */
13326 -1, /* V5TE. */
13327 -1, /* V5TEJ. */
13328 -1, /* V6. */
13329 -1, /* V6KZ. */
13330 -1, /* V6T2. */
13331 -1, /* V6K. */
13332 -1, /* V7. */
13333 T(V8M_BASE), /* V6_M. */
13334 T(V8M_BASE), /* V6S_M. */
13335 -1, /* V7E_M. */
13336 -1, /* V8. */
13337 -1,
13338 T(V8M_BASE) /* V8-M BASELINE. */
13339 };
13340 const int v8m_mainline[] =
13341 {
13342 -1, /* PRE_V4. */
13343 -1, /* V4. */
13344 -1, /* V4T. */
13345 -1, /* V5T. */
13346 -1, /* V5TE. */
13347 -1, /* V5TEJ. */
13348 -1, /* V6. */
13349 -1, /* V6KZ. */
13350 -1, /* V6T2. */
13351 -1, /* V6K. */
13352 T(V8M_MAIN), /* V7. */
13353 T(V8M_MAIN), /* V6_M. */
13354 T(V8M_MAIN), /* V6S_M. */
13355 T(V8M_MAIN), /* V7E_M. */
13356 -1, /* V8. */
13357 -1,
13358 T(V8M_MAIN), /* V8-M BASELINE. */
13359 T(V8M_MAIN) /* V8-M MAINLINE. */
13360 };
91e22acd
AS		 13361 const int v4t_plus_v6_m[] =
13362 {
13363 -1, /* PRE_V4. */
13364 -1, /* V4. */
13365 T(V4T), /* V4T. */
13366 T(V5T), /* V5T. */
13367 T(V5TE), /* V5TE. */
13368 T(V5TEJ), /* V5TEJ. */
13369 T(V6), /* V6. */
13370 T(V6KZ), /* V6KZ. */
13371 T(V6T2), /* V6T2. */
13372 T(V6K), /* V6K. */
13373 T(V7), /* V7. */
13374 T(V6_M), /* V6_M. */
13375 T(V6S_M), /* V6S_M. */
9e3c6df6 13376 T(V7E_M), /* V7E_M. */
bca38921 13377 T(V8), /* V8. */
4ed7ed8d 13378 -1, /* Unused. */
2fd158eb
TP		 13379 T(V8M_BASE), /* V8-M BASELINE. */
13380 T(V8M_MAIN), /* V8-M MAINLINE. */
91e22acd
AS		 13381 T(V4T_PLUS_V6_M) /* V4T plus V6_M. */
13382 };
13383 const int *comb[] =
13384 {
13385 v6t2,
13386 v6k,
13387 v7,
13388 v6_m,
13389 v6s_m,
9e3c6df6 13390 v7e_m,
bca38921 13391 v8,
4ed7ed8d 13392 NULL,
2fd158eb
TP		 13393 v8m_baseline,
13394 v8m_mainline,
91e22acd
AS		 13395 /* Pseudo-architecture. */
13396 v4t_plus_v6_m
13397 };
13398
13399 /* Check we've not got a higher architecture than we know about. */
13400
9e3c6df6 13401 if (oldtag > MAX_TAG_CPU_ARCH || newtag > MAX_TAG_CPU_ARCH)
91e22acd 13402 {
3895f852 13403 _bfd_error_handler (_("error: %B: Unknown CPU architecture"), ibfd);
91e22acd
AS		 13404 return -1;
13405 }
13406
13407 /* Override old tag if we have a Tag_also_compatible_with on the output. */
13408
13409 if ((oldtag == T(V6_M) && *secondary_compat_out == T(V4T))
13410 || (oldtag == T(V4T) && *secondary_compat_out == T(V6_M)))
13411 oldtag = T(V4T_PLUS_V6_M);
13412
13413 /* And override the new tag if we have a Tag_also_compatible_with on the
13414 input. */
13415
13416 if ((newtag == T(V6_M) && secondary_compat == T(V4T))
13417 || (newtag == T(V4T) && secondary_compat == T(V6_M)))
13418 newtag = T(V4T_PLUS_V6_M);
13419
13420 tagl = (oldtag < newtag) ? oldtag : newtag;
13421 result = tagh = (oldtag > newtag) ? oldtag : newtag;
13422
13423 /* Architectures before V6KZ add features monotonically. */
13424 if (tagh <= TAG_CPU_ARCH_V6KZ)
13425 return result;
13426
4ed7ed8d 13427 result = comb[tagh - T(V6T2)] ? comb[tagh - T(V6T2)][tagl] : -1;
91e22acd
AS		 13428
13429 /* Use Tag_CPU_arch == V4T and Tag_also_compatible_with (Tag_CPU_arch V6_M)
13430 as the canonical version. */
13431 if (result == T(V4T_PLUS_V6_M))
13432 {
13433 result = T(V4T);
13434 *secondary_compat_out = T(V6_M);
13435 }
13436 else
13437 *secondary_compat_out = -1;
13438
13439 if (result == -1)
13440 {
3895f852 13441 _bfd_error_handler (_("error: %B: Conflicting CPU architectures %d/%d"),
91e22acd
AS		 13442 ibfd, oldtag, newtag);
13443 return -1;
13444 }
13445
13446 return result;
13447#undef T
8e79c3df
CM		 13448}
13449
ac56ee8f
MGD		 13450/* Query attributes object to see if integer divide instructions may be
13451 present in an object. */
13452static bfd_boolean
13453elf32_arm_attributes_accept_div (const obj_attribute *attr)
13454{
13455 int arch = attr[Tag_CPU_arch].i;
13456 int profile = attr[Tag_CPU_arch_profile].i;
13457
13458 switch (attr[Tag_DIV_use].i)
13459 {
13460 case 0:
13461 /* Integer divide allowed if instruction contained in archetecture. */
13462 if (arch == TAG_CPU_ARCH_V7 && (profile == 'R' || profile == 'M'))
13463 return TRUE;
13464 else if (arch >= TAG_CPU_ARCH_V7E_M)
13465 return TRUE;
13466 else
13467 return FALSE;
13468
13469 case 1:
13470 /* Integer divide explicitly prohibited. */
13471 return FALSE;
13472
13473 default:
13474 /* Unrecognised case - treat as allowing divide everywhere. */
13475 case 2:
13476 /* Integer divide allowed in ARM state. */
13477 return TRUE;
13478 }
13479}
13480
13481/* Query attributes object to see if integer divide instructions are
13482 forbidden to be in the object. This is not the inverse of
13483 elf32_arm_attributes_accept_div. */
13484static bfd_boolean
13485elf32_arm_attributes_forbid_div (const obj_attribute *attr)
13486{
13487 return attr[Tag_DIV_use].i == 1;
13488}
13489
ee065d83
PB		 13490/* Merge EABI object attributes from IBFD into OBFD. Raise an error if there
13491 are conflicting attributes. */
906e58ca 13492
ee065d83
PB		 13493static bfd_boolean
13494elf32_arm_merge_eabi_attributes (bfd *ibfd, bfd *obfd)
13495{
104d59d1
JM		 13496 obj_attribute *in_attr;
13497 obj_attribute *out_attr;
ee065d83
PB		 13498 /* Some tags have 0 = don't care, 1 = strong requirement,
13499 2 = weak requirement. */
91e22acd 13500 static const int order_021[3] = {0, 2, 1};
ee065d83 13501 int i;
91e22acd 13502 bfd_boolean result = TRUE;
9274e9de 13503 const char *sec_name = get_elf_backend_data (ibfd)->obj_attrs_section;
ee065d83 13504
3e6b1042
DJ		 13505 /* Skip the linker stubs file. This preserves previous behavior
13506 of accepting unknown attributes in the first input file - but
13507 is that a bug? */
13508 if (ibfd->flags & BFD_LINKER_CREATED)
13509 return TRUE;
13510
9274e9de
TG		 13511 /* Skip any input that hasn't attribute section.
13512 This enables to link object files without attribute section with
13513 any others. */
13514 if (bfd_get_section_by_name (ibfd, sec_name) == NULL)
13515 return TRUE;
13516
104d59d1 13517 if (!elf_known_obj_attributes_proc (obfd)[0].i)
ee065d83
PB		 13518 {
13519 /* This is the first object. Copy the attributes. */
104d59d1 13520 _bfd_elf_copy_obj_attributes (ibfd, obfd);
004ae526 13521
cd21e546
MGD		 13522 out_attr = elf_known_obj_attributes_proc (obfd);
13523
004ae526
PB		 13524 /* Use the Tag_null value to indicate the attributes have been
13525 initialized. */
cd21e546 13526 out_attr[0].i = 1;
004ae526 13527
cd21e546
MGD		 13528 /* We do not output objects with Tag_MPextension_use_legacy - we move
13529 the attribute's value to Tag_MPextension_use. */
13530 if (out_attr[Tag_MPextension_use_legacy].i != 0)
13531 {
13532 if (out_attr[Tag_MPextension_use].i != 0
13533 && out_attr[Tag_MPextension_use_legacy].i
99059e56 13534 != out_attr[Tag_MPextension_use].i)
cd21e546
MGD		 13535 {
13536 _bfd_error_handler
13537 (_("Error: %B has both the current and legacy "
13538 "Tag_MPextension_use attributes"), ibfd);
13539 result = FALSE;
13540 }
13541
13542 out_attr[Tag_MPextension_use] =
13543 out_attr[Tag_MPextension_use_legacy];
13544 out_attr[Tag_MPextension_use_legacy].type = 0;
13545 out_attr[Tag_MPextension_use_legacy].i = 0;
13546 }
13547
13548 return result;
ee065d83
PB		 13549 }
13550
104d59d1
JM		 13551 in_attr = elf_known_obj_attributes_proc (ibfd);
13552 out_attr = elf_known_obj_attributes_proc (obfd);
ee065d83
PB		 13553 /* This needs to happen before Tag_ABI_FP_number_model is merged. */
13554 if (in_attr[Tag_ABI_VFP_args].i != out_attr[Tag_ABI_VFP_args].i)
13555 {
5c294fee
TG		 13556 /* Ignore mismatches if the object doesn't use floating point or is
13557 floating point ABI independent. */
13558 if (out_attr[Tag_ABI_FP_number_model].i == AEABI_FP_number_model_none
13559 || (in_attr[Tag_ABI_FP_number_model].i != AEABI_FP_number_model_none
13560 && out_attr[Tag_ABI_VFP_args].i == AEABI_VFP_args_compatible))
ee065d83 13561 out_attr[Tag_ABI_VFP_args].i = in_attr[Tag_ABI_VFP_args].i;
5c294fee
TG		 13562 else if (in_attr[Tag_ABI_FP_number_model].i != AEABI_FP_number_model_none
13563 && in_attr[Tag_ABI_VFP_args].i != AEABI_VFP_args_compatible)
ee065d83
PB		 13564 {
13565 _bfd_error_handler
3895f852 13566 (_("error: %B uses VFP register arguments, %B does not"),
deddc40b
NS		 13567 in_attr[Tag_ABI_VFP_args].i ? ibfd : obfd,
13568 in_attr[Tag_ABI_VFP_args].i ? obfd : ibfd);
91e22acd 13569 result = FALSE;
ee065d83
PB		 13570 }
13571 }
13572
3de4a297 13573 for (i = LEAST_KNOWN_OBJ_ATTRIBUTE; i < NUM_KNOWN_OBJ_ATTRIBUTES; i++)
ee065d83
PB		 13574 {
13575 /* Merge this attribute with existing attributes. */
13576 switch (i)
13577 {
13578 case Tag_CPU_raw_name:
13579 case Tag_CPU_name:
6a631e86 13580 /* These are merged after Tag_CPU_arch. */
ee065d83
PB		 13581 break;
13582
13583 case Tag_ABI_optimization_goals:
13584 case Tag_ABI_FP_optimization_goals:
13585 /* Use the first value seen. */
13586 break;
13587
13588 case Tag_CPU_arch:
91e22acd
AS		 13589 {
13590 int secondary_compat = -1, secondary_compat_out = -1;
13591 unsigned int saved_out_attr = out_attr[i].i;
70e99720
TG		 13592 int arch_attr;
13593 static const char *name_table[] =
13594 {
91e22acd
AS		 13595 /* These aren't real CPU names, but we can't guess
13596 that from the architecture version alone. */
13597 "Pre v4",
13598 "ARM v4",
13599 "ARM v4T",
13600 "ARM v5T",
13601 "ARM v5TE",
13602 "ARM v5TEJ",
13603 "ARM v6",
13604 "ARM v6KZ",
13605 "ARM v6T2",
13606 "ARM v6K",
13607 "ARM v7",
13608 "ARM v6-M",
bca38921 13609 "ARM v6S-M",
2fd158eb
TP		 13610 "ARM v8",
13611 "",
13612 "ARM v8-M.baseline",
13613 "ARM v8-M.mainline",
91e22acd
AS		 13614 };
13615
13616 /* Merge Tag_CPU_arch and Tag_also_compatible_with. */
13617 secondary_compat = get_secondary_compatible_arch (ibfd);
13618 secondary_compat_out = get_secondary_compatible_arch (obfd);
70e99720
TG		 13619 arch_attr = tag_cpu_arch_combine (ibfd, out_attr[i].i,
13620 &secondary_compat_out,
13621 in_attr[i].i,
13622 secondary_compat);
13623
13624 /* Return with error if failed to merge. */
13625 if (arch_attr == -1)
13626 return FALSE;
13627
13628 out_attr[i].i = arch_attr;
13629
91e22acd
AS		 13630 set_secondary_compatible_arch (obfd, secondary_compat_out);
13631
13632 /* Merge Tag_CPU_name and Tag_CPU_raw_name. */
13633 if (out_attr[i].i == saved_out_attr)
13634 ; /* Leave the names alone. */
13635 else if (out_attr[i].i == in_attr[i].i)
13636 {
13637 /* The output architecture has been changed to match the
13638 input architecture. Use the input names. */
13639 out_attr[Tag_CPU_name].s = in_attr[Tag_CPU_name].s
13640 ? _bfd_elf_attr_strdup (obfd, in_attr[Tag_CPU_name].s)
13641 : NULL;
13642 out_attr[Tag_CPU_raw_name].s = in_attr[Tag_CPU_raw_name].s
13643 ? _bfd_elf_attr_strdup (obfd, in_attr[Tag_CPU_raw_name].s)
13644 : NULL;
13645 }
13646 else
13647 {
13648 out_attr[Tag_CPU_name].s = NULL;
13649 out_attr[Tag_CPU_raw_name].s = NULL;
13650 }
13651
13652 /* If we still don't have a value for Tag_CPU_name,
13653 make one up now. Tag_CPU_raw_name remains blank. */
13654 if (out_attr[Tag_CPU_name].s == NULL
13655 && out_attr[i].i < ARRAY_SIZE (name_table))
13656 out_attr[Tag_CPU_name].s =
13657 _bfd_elf_attr_strdup (obfd, name_table[out_attr[i].i]);
13658 }
13659 break;
13660
ee065d83
PB		 13661 case Tag_ARM_ISA_use:
13662 case Tag_THUMB_ISA_use:
ee065d83 13663 case Tag_WMMX_arch:
91e22acd
AS		 13664 case Tag_Advanced_SIMD_arch:
13665 /* ??? Do Advanced_SIMD (NEON) and WMMX conflict? */
ee065d83 13666 case Tag_ABI_FP_rounding:
ee065d83
PB		 13667 case Tag_ABI_FP_exceptions:
13668 case Tag_ABI_FP_user_exceptions:
13669 case Tag_ABI_FP_number_model:
75375b3e 13670 case Tag_FP_HP_extension:
91e22acd
AS		 13671 case Tag_CPU_unaligned_access:
13672 case Tag_T2EE_use:
91e22acd 13673 case Tag_MPextension_use:
ee065d83
PB		 13674 /* Use the largest value specified. */
13675 if (in_attr[i].i > out_attr[i].i)
13676 out_attr[i].i = in_attr[i].i;
13677 break;
13678
75375b3e 13679 case Tag_ABI_align_preserved:
91e22acd
AS		 13680 case Tag_ABI_PCS_RO_data:
13681 /* Use the smallest value specified. */
13682 if (in_attr[i].i < out_attr[i].i)
13683 out_attr[i].i = in_attr[i].i;
13684 break;
13685
75375b3e 13686 case Tag_ABI_align_needed:
91e22acd 13687 if ((in_attr[i].i > 0 || out_attr[i].i > 0)
75375b3e
MGD		 13688 && (in_attr[Tag_ABI_align_preserved].i == 0
13689 || out_attr[Tag_ABI_align_preserved].i == 0))
ee065d83 13690 {
91e22acd
AS		 13691 /* This error message should be enabled once all non-conformant
13692 binaries in the toolchain have had the attributes set
13693 properly.
ee065d83 13694 _bfd_error_handler
3895f852 13695 (_("error: %B: 8-byte data alignment conflicts with %B"),
91e22acd
AS		 13696 obfd, ibfd);
13697 result = FALSE; */
ee065d83 13698 }
91e22acd
AS		 13699 /* Fall through. */
13700 case Tag_ABI_FP_denormal:
13701 case Tag_ABI_PCS_GOT_use:
13702 /* Use the "greatest" from the sequence 0, 2, 1, or the largest
13703 value if greater than 2 (for future-proofing). */
13704 if ((in_attr[i].i > 2 && in_attr[i].i > out_attr[i].i)
13705 || (in_attr[i].i <= 2 && out_attr[i].i <= 2
13706 && order_021[in_attr[i].i] > order_021[out_attr[i].i]))
ee065d83
PB		 13707 out_attr[i].i = in_attr[i].i;
13708 break;
91e22acd 13709
75375b3e
MGD		 13710 case Tag_Virtualization_use:
13711 /* The virtualization tag effectively stores two bits of
13712 information: the intended use of TrustZone (in bit 0), and the
13713 intended use of Virtualization (in bit 1). */
13714 if (out_attr[i].i == 0)
13715 out_attr[i].i = in_attr[i].i;
13716 else if (in_attr[i].i != 0
13717 && in_attr[i].i != out_attr[i].i)
13718 {
13719 if (in_attr[i].i <= 3 && out_attr[i].i <= 3)
13720 out_attr[i].i = 3;
13721 else
13722 {
13723 _bfd_error_handler
13724 (_("error: %B: unable to merge virtualization attributes "
13725 "with %B"),
13726 obfd, ibfd);
13727 result = FALSE;
13728 }
13729 }
13730 break;
91e22acd
AS		 13731
13732 case Tag_CPU_arch_profile:
13733 if (out_attr[i].i != in_attr[i].i)
13734 {
13735 /* 0 will merge with anything.
13736 'A' and 'S' merge to 'A'.
13737 'R' and 'S' merge to 'R'.
99059e56 13738 'M' and 'A|R|S' is an error. */
91e22acd
AS		 13739 if (out_attr[i].i == 0
13740 || (out_attr[i].i == 'S'
13741 && (in_attr[i].i == 'A' || in_attr[i].i == 'R')))
13742 out_attr[i].i = in_attr[i].i;
13743 else if (in_attr[i].i == 0
13744 || (in_attr[i].i == 'S'
13745 && (out_attr[i].i == 'A' || out_attr[i].i == 'R')))
6a631e86 13746 ; /* Do nothing. */
91e22acd
AS		 13747 else
13748 {
13749 _bfd_error_handler
3895f852 13750 (_("error: %B: Conflicting architecture profiles %c/%c"),
91e22acd
AS		 13751 ibfd,
13752 in_attr[i].i ? in_attr[i].i : '0',
13753 out_attr[i].i ? out_attr[i].i : '0');
13754 result = FALSE;
13755 }
13756 }
13757 break;
15afaa63
TP		 13758
13759 case Tag_DSP_extension:
13760 /* No need to change output value if any of:
13761 - pre (<=) ARMv5T input architecture (do not have DSP)
13762 - M input profile not ARMv7E-M and do not have DSP. */
13763 if (in_attr[Tag_CPU_arch].i <= 3
13764 || (in_attr[Tag_CPU_arch_profile].i == 'M'
13765 && in_attr[Tag_CPU_arch].i != 13
13766 && in_attr[i].i == 0))
13767 ; /* Do nothing. */
13768 /* Output value should be 0 if DSP part of architecture, ie.
13769 - post (>=) ARMv5te architecture output
13770 - A, R or S profile output or ARMv7E-M output architecture. */
13771 else if (out_attr[Tag_CPU_arch].i >= 4
13772 && (out_attr[Tag_CPU_arch_profile].i == 'A'
13773 || out_attr[Tag_CPU_arch_profile].i == 'R'
13774 || out_attr[Tag_CPU_arch_profile].i == 'S'
13775 || out_attr[Tag_CPU_arch].i == 13))
13776 out_attr[i].i = 0;
13777 /* Otherwise, DSP instructions are added and not part of output
13778 architecture. */
13779 else
13780 out_attr[i].i = 1;
13781 break;
13782
75375b3e 13783 case Tag_FP_arch:
62f3b8c8 13784 {
4547cb56
NC		 13785 /* Tag_ABI_HardFP_use is handled along with Tag_FP_arch since
13786 the meaning of Tag_ABI_HardFP_use depends on Tag_FP_arch
13787 when it's 0. It might mean absence of FP hardware if
99654aaf 13788 Tag_FP_arch is zero. */
4547cb56 13789
a715796b 13790#define VFP_VERSION_COUNT 9
62f3b8c8
PB		 13791 static const struct
13792 {
13793 int ver;
13794 int regs;
bca38921 13795 } vfp_versions[VFP_VERSION_COUNT] =
62f3b8c8
PB		 13796 {
13797 {0, 0},
13798 {1, 16},
13799 {2, 16},
13800 {3, 32},
13801 {3, 16},
13802 {4, 32},
bca38921 13803 {4, 16},
a715796b
TG		 13804 {8, 32},
13805 {8, 16}
62f3b8c8
PB		 13806 };
13807 int ver;
13808 int regs;
13809 int newval;
13810
4547cb56
NC		 13811 /* If the output has no requirement about FP hardware,
13812 follow the requirement of the input. */
13813 if (out_attr[i].i == 0)
13814 {
13815 BFD_ASSERT (out_attr[Tag_ABI_HardFP_use].i == 0);
13816 out_attr[i].i = in_attr[i].i;
13817 out_attr[Tag_ABI_HardFP_use].i
13818 = in_attr[Tag_ABI_HardFP_use].i;
13819 break;
13820 }
13821 /* If the input has no requirement about FP hardware, do
13822 nothing. */
13823 else if (in_attr[i].i == 0)
13824 {
13825 BFD_ASSERT (in_attr[Tag_ABI_HardFP_use].i == 0);
13826 break;
13827 }
13828
13829 /* Both the input and the output have nonzero Tag_FP_arch.
99654aaf 13830 So Tag_ABI_HardFP_use is implied by Tag_FP_arch when it's zero. */
4547cb56
NC		 13831
13832 /* If both the input and the output have zero Tag_ABI_HardFP_use,
13833 do nothing. */
13834 if (in_attr[Tag_ABI_HardFP_use].i == 0
13835 && out_attr[Tag_ABI_HardFP_use].i == 0)
13836 ;
13837 /* If the input and the output have different Tag_ABI_HardFP_use,
99654aaf 13838 the combination of them is 0 (implied by Tag_FP_arch). */
4547cb56
NC		 13839 else if (in_attr[Tag_ABI_HardFP_use].i
13840 != out_attr[Tag_ABI_HardFP_use].i)
99654aaf 13841 out_attr[Tag_ABI_HardFP_use].i = 0;
4547cb56
NC		 13842
13843 /* Now we can handle Tag_FP_arch. */
13844
bca38921
MGD		 13845 /* Values of VFP_VERSION_COUNT or more aren't defined, so just
13846 pick the biggest. */
13847 if (in_attr[i].i >= VFP_VERSION_COUNT
13848 && in_attr[i].i > out_attr[i].i)
62f3b8c8
PB		 13849 {
13850 out_attr[i] = in_attr[i];
13851 break;
13852 }
13853 /* The output uses the superset of input features
13854 (ISA version) and registers. */
13855 ver = vfp_versions[in_attr[i].i].ver;
13856 if (ver < vfp_versions[out_attr[i].i].ver)
13857 ver = vfp_versions[out_attr[i].i].ver;
13858 regs = vfp_versions[in_attr[i].i].regs;
13859 if (regs < vfp_versions[out_attr[i].i].regs)
13860 regs = vfp_versions[out_attr[i].i].regs;
13861 /* This assumes all possible supersets are also a valid
99059e56 13862 options. */
bca38921 13863 for (newval = VFP_VERSION_COUNT - 1; newval > 0; newval--)
62f3b8c8
PB		 13864 {
13865 if (regs == vfp_versions[newval].regs
13866 && ver == vfp_versions[newval].ver)
13867 break;
13868 }
13869 out_attr[i].i = newval;
13870 }
b1cc4aeb 13871 break;
ee065d83
PB		 13872 case Tag_PCS_config:
13873 if (out_attr[i].i == 0)
13874 out_attr[i].i = in_attr[i].i;
b6009aca 13875 else if (in_attr[i].i != 0 && out_attr[i].i != in_attr[i].i)
ee065d83
PB		 13876 {
13877 /* It's sometimes ok to mix different configs, so this is only
99059e56 13878 a warning. */
ee065d83
PB		 13879 _bfd_error_handler
13880 (_("Warning: %B: Conflicting platform configuration"), ibfd);
13881 }
13882 break;
13883 case Tag_ABI_PCS_R9_use:
004ae526
PB		 13884 if (in_attr[i].i != out_attr[i].i
13885 && out_attr[i].i != AEABI_R9_unused
ee065d83
PB		 13886 && in_attr[i].i != AEABI_R9_unused)
13887 {
13888 _bfd_error_handler
3895f852 13889 (_("error: %B: Conflicting use of R9"), ibfd);
91e22acd 13890 result = FALSE;
ee065d83
PB		 13891 }
13892 if (out_attr[i].i == AEABI_R9_unused)
13893 out_attr[i].i = in_attr[i].i;
13894 break;
13895 case Tag_ABI_PCS_RW_data:
13896 if (in_attr[i].i == AEABI_PCS_RW_data_SBrel
13897 && out_attr[Tag_ABI_PCS_R9_use].i != AEABI_R9_SB
13898 && out_attr[Tag_ABI_PCS_R9_use].i != AEABI_R9_unused)
13899 {
13900 _bfd_error_handler
3895f852 13901 (_("error: %B: SB relative addressing conflicts with use of R9"),
ee065d83 13902 ibfd);
91e22acd 13903 result = FALSE;
ee065d83
PB		 13904 }
13905 /* Use the smallest value specified. */
13906 if (in_attr[i].i < out_attr[i].i)
13907 out_attr[i].i = in_attr[i].i;
13908 break;
ee065d83 13909 case Tag_ABI_PCS_wchar_t:
a9dc9481
JM		 13910 if (out_attr[i].i && in_attr[i].i && out_attr[i].i != in_attr[i].i
13911 && !elf_arm_tdata (obfd)->no_wchar_size_warning)
ee065d83
PB		 13912 {
13913 _bfd_error_handler
a9dc9481
JM		 13914 (_("warning: %B uses %u-byte wchar_t yet the output is to use %u-byte wchar_t; use of wchar_t values across objects may fail"),
13915 ibfd, in_attr[i].i, out_attr[i].i);
ee065d83 13916 }
a9dc9481 13917 else if (in_attr[i].i && !out_attr[i].i)
ee065d83
PB		 13918 out_attr[i].i = in_attr[i].i;
13919 break;
ee065d83
PB		 13920 case Tag_ABI_enum_size:
13921 if (in_attr[i].i != AEABI_enum_unused)
13922 {
13923 if (out_attr[i].i == AEABI_enum_unused
13924 || out_attr[i].i == AEABI_enum_forced_wide)
13925 {
13926 /* The existing object is compatible with anything.
13927 Use whatever requirements the new object has. */
13928 out_attr[i].i = in_attr[i].i;
13929 }
13930 else if (in_attr[i].i != AEABI_enum_forced_wide
bf21ed78 13931 && out_attr[i].i != in_attr[i].i
0ffa91dd 13932 && !elf_arm_tdata (obfd)->no_enum_size_warning)
ee065d83 13933 {
91e22acd 13934 static const char *aeabi_enum_names[] =
bf21ed78 13935 { "", "variable-size", "32-bit", "" };
91e22acd
AS		 13936 const char *in_name =
13937 in_attr[i].i < ARRAY_SIZE(aeabi_enum_names)
13938 ? aeabi_enum_names[in_attr[i].i]
13939 : "<unknown>";
13940 const char *out_name =
13941 out_attr[i].i < ARRAY_SIZE(aeabi_enum_names)
13942 ? aeabi_enum_names[out_attr[i].i]
13943 : "<unknown>";
ee065d83 13944 _bfd_error_handler
bf21ed78 13945 (_("warning: %B uses %s enums yet the output is to use %s enums; use of enum values across objects may fail"),
91e22acd 13946 ibfd, in_name, out_name);
ee065d83
PB		 13947 }
13948 }
13949 break;
13950 case Tag_ABI_VFP_args:
13951 /* Aready done. */
13952 break;
13953 case Tag_ABI_WMMX_args:
13954 if (in_attr[i].i != out_attr[i].i)
13955 {
13956 _bfd_error_handler
3895f852 13957 (_("error: %B uses iWMMXt register arguments, %B does not"),
ee065d83 13958 ibfd, obfd);
91e22acd 13959 result = FALSE;
ee065d83
PB		 13960 }
13961 break;
7b86a9fa
AS		 13962 case Tag_compatibility:
13963 /* Merged in target-independent code. */
13964 break;
91e22acd 13965 case Tag_ABI_HardFP_use:
4547cb56 13966 /* This is handled along with Tag_FP_arch. */
91e22acd
AS		 13967 break;
13968 case Tag_ABI_FP_16bit_format:
13969 if (in_attr[i].i != 0 && out_attr[i].i != 0)
13970 {
13971 if (in_attr[i].i != out_attr[i].i)
13972 {
13973 _bfd_error_handler
3895f852 13974 (_("error: fp16 format mismatch between %B and %B"),
91e22acd
AS		 13975 ibfd, obfd);
13976 result = FALSE;
13977 }
13978 }
13979 if (in_attr[i].i != 0)
13980 out_attr[i].i = in_attr[i].i;
13981 break;
7b86a9fa 13982
cd21e546 13983 case Tag_DIV_use:
ac56ee8f
MGD		 13984 /* A value of zero on input means that the divide instruction may
13985 be used if available in the base architecture as specified via
13986 Tag_CPU_arch and Tag_CPU_arch_profile. A value of 1 means that
13987 the user did not want divide instructions. A value of 2
13988 explicitly means that divide instructions were allowed in ARM
13989 and Thumb state. */
13990 if (in_attr[i].i == out_attr[i].i)
13991 /* Do nothing. */ ;
13992 else if (elf32_arm_attributes_forbid_div (in_attr)
13993 && !elf32_arm_attributes_accept_div (out_attr))
13994 out_attr[i].i = 1;
13995 else if (elf32_arm_attributes_forbid_div (out_attr)
13996 && elf32_arm_attributes_accept_div (in_attr))
13997 out_attr[i].i = in_attr[i].i;
13998 else if (in_attr[i].i == 2)
13999 out_attr[i].i = in_attr[i].i;
cd21e546
MGD		 14000 break;
14001
14002 case Tag_MPextension_use_legacy:
14003 /* We don't output objects with Tag_MPextension_use_legacy - we
14004 move the value to Tag_MPextension_use. */
14005 if (in_attr[i].i != 0 && in_attr[Tag_MPextension_use].i != 0)
14006 {
14007 if (in_attr[Tag_MPextension_use].i != in_attr[i].i)
14008 {
14009 _bfd_error_handler
14010 (_("%B has has both the current and legacy "
b38cadfb 14011 "Tag_MPextension_use attributes"),
cd21e546
MGD		 14012 ibfd);
14013 result = FALSE;
14014 }
14015 }
14016
14017 if (in_attr[i].i > out_attr[Tag_MPextension_use].i)
14018 out_attr[Tag_MPextension_use] = in_attr[i];
14019
14020 break;
14021
91e22acd 14022 case Tag_nodefaults:
2d0bb761
AS		 14023 /* This tag is set if it exists, but the value is unused (and is
14024 typically zero). We don't actually need to do anything here -
14025 the merge happens automatically when the type flags are merged
14026 below. */
91e22acd
AS		 14027 break;
14028 case Tag_also_compatible_with:
14029 /* Already done in Tag_CPU_arch. */
14030 break;
14031 case Tag_conformance:
14032 /* Keep the attribute if it matches. Throw it away otherwise.
14033 No attribute means no claim to conform. */
14034 if (!in_attr[i].s || !out_attr[i].s
14035 || strcmp (in_attr[i].s, out_attr[i].s) != 0)
14036 out_attr[i].s = NULL;
14037 break;
3cfad14c 14038
91e22acd 14039 default:
e8b36cd1
JM		 14040 result
14041 = result && _bfd_elf_merge_unknown_attribute_low (ibfd, obfd, i);
91e22acd
AS		 14042 }
14043
14044 /* If out_attr was copied from in_attr then it won't have a type yet. */
14045 if (in_attr[i].type && !out_attr[i].type)
14046 out_attr[i].type = in_attr[i].type;
ee065d83
PB		 14047 }
14048
104d59d1 14049 /* Merge Tag_compatibility attributes and any common GNU ones. */
5488d830
MGD		 14050 if (!_bfd_elf_merge_object_attributes (ibfd, obfd))
14051 return FALSE;
ee065d83 14052
104d59d1 14053 /* Check for any attributes not known on ARM. */
e8b36cd1 14054 result &= _bfd_elf_merge_unknown_attribute_list (ibfd, obfd);
91e22acd 14055
91e22acd 14056 return result;
252b5132
RH		 14057}
14058
3a4a14e9
PB		 14059
14060/* Return TRUE if the two EABI versions are incompatible. */
14061
14062static bfd_boolean
14063elf32_arm_versions_compatible (unsigned iver, unsigned over)
14064{
14065 /* v4 and v5 are the same spec before and after it was released,
14066 so allow mixing them. */
14067 if ((iver == EF_ARM_EABI_VER4 && over == EF_ARM_EABI_VER5)
14068 || (iver == EF_ARM_EABI_VER5 && over == EF_ARM_EABI_VER4))
14069 return TRUE;
14070
14071 return (iver == over);
14072}
14073
252b5132
RH		 14074/* Merge backend specific data from an object file to the output
14075 object file when linking. */
9b485d32 14076
b34976b6 14077static bfd_boolean
21d799b5 14078elf32_arm_merge_private_bfd_data (bfd * ibfd, bfd * obfd);
252b5132 14079
9b485d32
NC		 14080/* Display the flags field. */
14081
b34976b6 14082static bfd_boolean
57e8b36a 14083elf32_arm_print_private_bfd_data (bfd *abfd, void * ptr)
252b5132 14084{
fc830a83
NC		 14085 FILE * file = (FILE *) ptr;
14086 unsigned long flags;
252b5132
RH		 14087
14088 BFD_ASSERT (abfd != NULL && ptr != NULL);
14089
14090 /* Print normal ELF private data. */
14091 _bfd_elf_print_private_bfd_data (abfd, ptr);
14092
fc830a83 14093 flags = elf_elfheader (abfd)->e_flags;
9b485d32
NC		 14094 /* Ignore init flag - it may not be set, despite the flags field
14095 containing valid data. */
252b5132
RH		 14096
14097 /* xgettext:c-format */
9b485d32 14098 fprintf (file, _("private flags = %lx:"), elf_elfheader (abfd)->e_flags);
252b5132 14099
fc830a83
NC		 14100 switch (EF_ARM_EABI_VERSION (flags))
14101 {
14102 case EF_ARM_EABI_UNKNOWN:
4cc11e76 14103 /* The following flag bits are GNU extensions and not part of the
fc830a83
NC		 14104 official ARM ELF extended ABI. Hence they are only decoded if
14105 the EABI version is not set. */
fd2ec330 14106 if (flags & EF_ARM_INTERWORK)
9b485d32 14107 fprintf (file, _(" [interworking enabled]"));
9a5aca8c 14108
fd2ec330 14109 if (flags & EF_ARM_APCS_26)
6c571f00 14110 fprintf (file, " [APCS-26]");
fc830a83 14111 else
6c571f00 14112 fprintf (file, " [APCS-32]");
9a5aca8c 14113
96a846ea
RE		 14114 if (flags & EF_ARM_VFP_FLOAT)
14115 fprintf (file, _(" [VFP float format]"));
fde78edd
NC		 14116 else if (flags & EF_ARM_MAVERICK_FLOAT)
14117 fprintf (file, _(" [Maverick float format]"));
96a846ea
RE		 14118 else
14119 fprintf (file, _(" [FPA float format]"));
14120
fd2ec330 14121 if (flags & EF_ARM_APCS_FLOAT)
9b485d32 14122 fprintf (file, _(" [floats passed in float registers]"));
9a5aca8c 14123
fd2ec330 14124 if (flags & EF_ARM_PIC)
9b485d32 14125 fprintf (file, _(" [position independent]"));
fc830a83 14126
fd2ec330 14127 if (flags & EF_ARM_NEW_ABI)
9b485d32 14128 fprintf (file, _(" [new ABI]"));
9a5aca8c 14129
fd2ec330 14130 if (flags & EF_ARM_OLD_ABI)
9b485d32 14131 fprintf (file, _(" [old ABI]"));
9a5aca8c 14132
fd2ec330 14133 if (flags & EF_ARM_SOFT_FLOAT)
9b485d32 14134 fprintf (file, _(" [software FP]"));
9a5aca8c 14135
96a846ea
RE		 14136 flags &= ~(EF_ARM_INTERWORK | EF_ARM_APCS_26 | EF_ARM_APCS_FLOAT
14137 | EF_ARM_PIC | EF_ARM_NEW_ABI | EF_ARM_OLD_ABI
fde78edd
NC		 14138 | EF_ARM_SOFT_FLOAT | EF_ARM_VFP_FLOAT
14139 | EF_ARM_MAVERICK_FLOAT);
fc830a83 14140 break;
9a5aca8c 14141
fc830a83 14142 case EF_ARM_EABI_VER1:
9b485d32 14143 fprintf (file, _(" [Version1 EABI]"));
9a5aca8c 14144
fc830a83 14145 if (flags & EF_ARM_SYMSARESORTED)
9b485d32 14146 fprintf (file, _(" [sorted symbol table]"));
fc830a83 14147 else
9b485d32 14148 fprintf (file, _(" [unsorted symbol table]"));
9a5aca8c 14149
fc830a83
NC		 14150 flags &= ~ EF_ARM_SYMSARESORTED;
14151 break;
9a5aca8c 14152
fd2ec330
PB		 14153 case EF_ARM_EABI_VER2:
14154 fprintf (file, _(" [Version2 EABI]"));
14155
14156 if (flags & EF_ARM_SYMSARESORTED)
14157 fprintf (file, _(" [sorted symbol table]"));
14158 else
14159 fprintf (file, _(" [unsorted symbol table]"));
14160
14161 if (flags & EF_ARM_DYNSYMSUSESEGIDX)
14162 fprintf (file, _(" [dynamic symbols use segment index]"));
14163
14164 if (flags & EF_ARM_MAPSYMSFIRST)
14165 fprintf (file, _(" [mapping symbols precede others]"));
14166
99e4ae17 14167 flags &= ~(EF_ARM_SYMSARESORTED | EF_ARM_DYNSYMSUSESEGIDX
fd2ec330
PB		 14168 | EF_ARM_MAPSYMSFIRST);
14169 break;
14170
d507cf36
PB		 14171 case EF_ARM_EABI_VER3:
14172 fprintf (file, _(" [Version3 EABI]"));
8cb51566
PB		 14173 break;
14174
14175 case EF_ARM_EABI_VER4:
14176 fprintf (file, _(" [Version4 EABI]"));
3a4a14e9 14177 goto eabi;
d507cf36 14178
3a4a14e9
PB		 14179 case EF_ARM_EABI_VER5:
14180 fprintf (file, _(" [Version5 EABI]"));
3bfcb652
NC		 14181
14182 if (flags & EF_ARM_ABI_FLOAT_SOFT)
14183 fprintf (file, _(" [soft-float ABI]"));
14184
14185 if (flags & EF_ARM_ABI_FLOAT_HARD)
14186 fprintf (file, _(" [hard-float ABI]"));
14187
14188 flags &= ~(EF_ARM_ABI_FLOAT_SOFT | EF_ARM_ABI_FLOAT_HARD);
14189
3a4a14e9 14190 eabi:
d507cf36
PB		 14191 if (flags & EF_ARM_BE8)
14192 fprintf (file, _(" [BE8]"));
14193
14194 if (flags & EF_ARM_LE8)
14195 fprintf (file, _(" [LE8]"));
14196
14197 flags &= ~(EF_ARM_LE8 | EF_ARM_BE8);
14198 break;
14199
fc830a83 14200 default:
9b485d32 14201 fprintf (file, _(" <EABI version unrecognised>"));
fc830a83
NC		 14202 break;
14203 }
252b5132 14204
fc830a83 14205 flags &= ~ EF_ARM_EABIMASK;
252b5132 14206
fc830a83 14207 if (flags & EF_ARM_RELEXEC)
9b485d32 14208 fprintf (file, _(" [relocatable executable]"));
252b5132 14209
a5721edd 14210 flags &= ~EF_ARM_RELEXEC;
fc830a83
NC		 14211
14212 if (flags)
9b485d32 14213 fprintf (file, _("<Unrecognised flag bits set>"));
9a5aca8c 14214
252b5132
RH		 14215 fputc ('\n', file);
14216
b34976b6 14217 return TRUE;
252b5132
RH		 14218}
14219
14220static int
57e8b36a 14221elf32_arm_get_symbol_type (Elf_Internal_Sym * elf_sym, int type)
252b5132 14222{
2f0ca46a
NC		 14223 switch (ELF_ST_TYPE (elf_sym->st_info))
14224 {
14225 case STT_ARM_TFUNC:
14226 return ELF_ST_TYPE (elf_sym->st_info);
ce855c42 14227
2f0ca46a
NC		 14228 case STT_ARM_16BIT:
14229 /* If the symbol is not an object, return the STT_ARM_16BIT flag.
14230 This allows us to distinguish between data used by Thumb instructions
14231 and non-data (which is probably code) inside Thumb regions of an
14232 executable. */
1a0eb693 14233 if (type != STT_OBJECT && type != STT_TLS)
2f0ca46a
NC		 14234 return ELF_ST_TYPE (elf_sym->st_info);
14235 break;
9a5aca8c 14236
ce855c42
NC		 14237 default:
14238 break;
2f0ca46a
NC		 14239 }
14240
14241 return type;
252b5132 14242}
f21f3fe0 14243
252b5132 14244static asection *
07adf181
AM		 14245elf32_arm_gc_mark_hook (asection *sec,
14246 struct bfd_link_info *info,
14247 Elf_Internal_Rela *rel,
14248 struct elf_link_hash_entry *h,
14249 Elf_Internal_Sym *sym)
252b5132
RH		 14250{
14251 if (h != NULL)
07adf181 14252 switch (ELF32_R_TYPE (rel->r_info))
252b5132
RH		 14253 {
14254 case R_ARM_GNU_VTINHERIT:
14255 case R_ARM_GNU_VTENTRY:
07adf181
AM		 14256 return NULL;
14257 }
9ad5cbcf 14258
07adf181 14259 return _bfd_elf_gc_mark_hook (sec, info, rel, h, sym);
252b5132
RH		 14260}
14261
780a67af
NC		 14262/* Update the got entry reference counts for the section being removed. */
14263
b34976b6 14264static bfd_boolean
ba93b8ac
DJ		 14265elf32_arm_gc_sweep_hook (bfd * abfd,
14266 struct bfd_link_info * info,
14267 asection * sec,
14268 const Elf_Internal_Rela * relocs)
252b5132 14269{
5e681ec4
PB		 14270 Elf_Internal_Shdr *symtab_hdr;
14271 struct elf_link_hash_entry **sym_hashes;
14272 bfd_signed_vma *local_got_refcounts;
14273 const Elf_Internal_Rela *rel, *relend;
eb043451
PB		 14274 struct elf32_arm_link_hash_table * globals;
14275
0e1862bb 14276 if (bfd_link_relocatable (info))
7dda2462
TG		 14277 return TRUE;
14278
eb043451 14279 globals = elf32_arm_hash_table (info);
4dfe6ac6
NC		 14280 if (globals == NULL)
14281 return FALSE;
5e681ec4
PB		 14282
14283 elf_section_data (sec)->local_dynrel = NULL;
14284
0ffa91dd 14285 symtab_hdr = & elf_symtab_hdr (abfd);
5e681ec4
PB		 14286 sym_hashes = elf_sym_hashes (abfd);
14287 local_got_refcounts = elf_local_got_refcounts (abfd);
14288
906e58ca 14289 check_use_blx (globals);
bd97cb95 14290
5e681ec4
PB		 14291 relend = relocs + sec->reloc_count;
14292 for (rel = relocs; rel < relend; rel++)
eb043451 14293 {
3eb128b2
AM		 14294 unsigned long r_symndx;
14295 struct elf_link_hash_entry *h = NULL;
f6e32f6d 14296 struct elf32_arm_link_hash_entry *eh;
eb043451 14297 int r_type;
34e77a92 14298 bfd_boolean call_reloc_p;
f6e32f6d
RS		 14299 bfd_boolean may_become_dynamic_p;
14300 bfd_boolean may_need_local_target_p;
34e77a92
RS		 14301 union gotplt_union *root_plt;
14302 struct arm_plt_info *arm_plt;
5e681ec4 14303
3eb128b2
AM		 14304 r_symndx = ELF32_R_SYM (rel->r_info);
14305 if (r_symndx >= symtab_hdr->sh_info)
14306 {
14307 h = sym_hashes[r_symndx - symtab_hdr->sh_info];
14308 while (h->root.type == bfd_link_hash_indirect
14309 || h->root.type == bfd_link_hash_warning)
14310 h = (struct elf_link_hash_entry *) h->root.u.i.link;
14311 }
f6e32f6d
RS		 14312 eh = (struct elf32_arm_link_hash_entry *) h;
14313
34e77a92 14314 call_reloc_p = FALSE;
f6e32f6d
RS		 14315 may_become_dynamic_p = FALSE;
14316 may_need_local_target_p = FALSE;
3eb128b2 14317
eb043451 14318 r_type = ELF32_R_TYPE (rel->r_info);
eb043451 14319 r_type = arm_real_reloc_type (globals, r_type);
eb043451
PB		 14320 switch (r_type)
14321 {
14322 case R_ARM_GOT32:
eb043451 14323 case R_ARM_GOT_PREL:
ba93b8ac
DJ		 14324 case R_ARM_TLS_GD32:
14325 case R_ARM_TLS_IE32:
3eb128b2 14326 if (h != NULL)
eb043451 14327 {
eb043451
PB		 14328 if (h->got.refcount > 0)
14329 h->got.refcount -= 1;
14330 }
14331 else if (local_got_refcounts != NULL)
14332 {
14333 if (local_got_refcounts[r_symndx] > 0)
14334 local_got_refcounts[r_symndx] -= 1;
14335 }
14336 break;
14337
ba93b8ac 14338 case R_ARM_TLS_LDM32:
4dfe6ac6 14339 globals->tls_ldm_got.refcount -= 1;
ba93b8ac
DJ		 14340 break;
14341
eb043451
PB		 14342 case R_ARM_PC24:
14343 case R_ARM_PLT32:
5b5bb741
PB		 14344 case R_ARM_CALL:
14345 case R_ARM_JUMP24:
eb043451 14346 case R_ARM_PREL31:
c19d1205 14347 case R_ARM_THM_CALL:
bd97cb95
DJ		 14348 case R_ARM_THM_JUMP24:
14349 case R_ARM_THM_JUMP19:
34e77a92 14350 call_reloc_p = TRUE;
f6e32f6d
RS		 14351 may_need_local_target_p = TRUE;
14352 break;
14353
14354 case R_ARM_ABS12:
14355 if (!globals->vxworks_p)
14356 {
14357 may_need_local_target_p = TRUE;
14358 break;
14359 }
14360 /* Fall through. */
14361 case R_ARM_ABS32:
14362 case R_ARM_ABS32_NOI:
14363 case R_ARM_REL32:
14364 case R_ARM_REL32_NOI:
b6895b4f
PB		 14365 case R_ARM_MOVW_ABS_NC:
14366 case R_ARM_MOVT_ABS:
14367 case R_ARM_MOVW_PREL_NC:
14368 case R_ARM_MOVT_PREL:
14369 case R_ARM_THM_MOVW_ABS_NC:
14370 case R_ARM_THM_MOVT_ABS:
14371 case R_ARM_THM_MOVW_PREL_NC:
14372 case R_ARM_THM_MOVT_PREL:
b7693d02 14373 /* Should the interworking branches be here also? */
0e1862bb 14374 if ((bfd_link_pic (info) || globals->root.is_relocatable_executable)
34e77a92
RS		 14375 && (sec->flags & SEC_ALLOC) != 0)
14376 {
14377 if (h == NULL
469a3493 14378 && elf32_arm_howto_from_type (r_type)->pc_relative)
34e77a92
RS		 14379 {
14380 call_reloc_p = TRUE;
14381 may_need_local_target_p = TRUE;
14382 }
14383 else
14384 may_become_dynamic_p = TRUE;
14385 }
f6e32f6d
RS		 14386 else
14387 may_need_local_target_p = TRUE;
14388 break;
b7693d02 14389
f6e32f6d
RS		 14390 default:
14391 break;
14392 }
5e681ec4 14393
34e77a92 14394 if (may_need_local_target_p
4ba2ef8f
TP		 14395 && elf32_arm_get_plt_info (abfd, globals, eh, r_symndx, &root_plt,
14396 &arm_plt))
f6e32f6d 14397 {
27586251
HPN		 14398 /* If PLT refcount book-keeping is wrong and too low, we'll
14399 see a zero value (going to -1) for the root PLT reference
14400 count. */
14401 if (root_plt->refcount >= 0)
14402 {
14403 BFD_ASSERT (root_plt->refcount != 0);
14404 root_plt->refcount -= 1;
14405 }
14406 else
14407 /* A value of -1 means the symbol has become local, forced
14408 or seeing a hidden definition. Any other negative value
14409 is an error. */
14410 BFD_ASSERT (root_plt->refcount == -1);
34e77a92
RS		 14411
14412 if (!call_reloc_p)
14413 arm_plt->noncall_refcount--;
5e681ec4 14414
f6e32f6d 14415 if (r_type == R_ARM_THM_CALL)
34e77a92 14416 arm_plt->maybe_thumb_refcount--;
bd97cb95 14417
f6e32f6d
RS		 14418 if (r_type == R_ARM_THM_JUMP24
14419 || r_type == R_ARM_THM_JUMP19)
34e77a92 14420 arm_plt->thumb_refcount--;
f6e32f6d 14421 }
5e681ec4 14422
34e77a92 14423 if (may_become_dynamic_p)
f6e32f6d
RS		 14424 {
14425 struct elf_dyn_relocs **pp;
14426 struct elf_dyn_relocs *p;
5e681ec4 14427
34e77a92 14428 if (h != NULL)
9c489990 14429 pp = &(eh->dyn_relocs);
34e77a92
RS		 14430 else
14431 {
14432 Elf_Internal_Sym *isym;
14433
14434 isym = bfd_sym_from_r_symndx (&globals->sym_cache,
14435 abfd, r_symndx);
14436 if (isym == NULL)
14437 return FALSE;
14438 pp = elf32_arm_get_local_dynreloc_list (abfd, r_symndx, isym);
14439 if (pp == NULL)
14440 return FALSE;
14441 }
9c489990 14442 for (; (p = *pp) != NULL; pp = &p->next)
f6e32f6d
RS		 14443 if (p->sec == sec)
14444 {
14445 /* Everything must go for SEC. */
14446 *pp = p->next;
14447 break;
14448 }
eb043451
PB		 14449 }
14450 }
5e681ec4 14451
b34976b6 14452 return TRUE;
252b5132
RH		 14453}
14454
780a67af
NC		 14455/* Look through the relocs for a section during the first phase. */
14456
b34976b6 14457static bfd_boolean
57e8b36a
NC		 14458elf32_arm_check_relocs (bfd *abfd, struct bfd_link_info *info,
14459 asection *sec, const Elf_Internal_Rela *relocs)
252b5132 14460{
b34976b6
AM		 14461 Elf_Internal_Shdr *symtab_hdr;
14462 struct elf_link_hash_entry **sym_hashes;
b34976b6
AM		 14463 const Elf_Internal_Rela *rel;
14464 const Elf_Internal_Rela *rel_end;
14465 bfd *dynobj;
5e681ec4 14466 asection *sreloc;
5e681ec4 14467 struct elf32_arm_link_hash_table *htab;
f6e32f6d
RS		 14468 bfd_boolean call_reloc_p;
14469 bfd_boolean may_become_dynamic_p;
14470 bfd_boolean may_need_local_target_p;
ce98a316 14471 unsigned long nsyms;
9a5aca8c 14472
0e1862bb 14473 if (bfd_link_relocatable (info))
b34976b6 14474 return TRUE;
9a5aca8c 14475
0ffa91dd
NC		 14476 BFD_ASSERT (is_arm_elf (abfd));
14477
5e681ec4 14478 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 14479 if (htab == NULL)
14480 return FALSE;
14481
5e681ec4 14482 sreloc = NULL;
9a5aca8c 14483
67687978
PB		 14484 /* Create dynamic sections for relocatable executables so that we can
14485 copy relocations. */
14486 if (htab->root.is_relocatable_executable
14487 && ! htab->root.dynamic_sections_created)
14488 {
14489 if (! _bfd_elf_link_create_dynamic_sections (abfd, info))
14490 return FALSE;
14491 }
14492
cbc704f3
RS		 14493 if (htab->root.dynobj == NULL)
14494 htab->root.dynobj = abfd;
34e77a92
RS		 14495 if (!create_ifunc_sections (info))
14496 return FALSE;
cbc704f3
RS		 14497
14498 dynobj = htab->root.dynobj;
14499
0ffa91dd 14500 symtab_hdr = & elf_symtab_hdr (abfd);
252b5132 14501 sym_hashes = elf_sym_hashes (abfd);
ce98a316 14502 nsyms = NUM_SHDR_ENTRIES (symtab_hdr);
b38cadfb 14503
252b5132
RH		 14504 rel_end = relocs + sec->reloc_count;
14505 for (rel = relocs; rel < rel_end; rel++)
14506 {
34e77a92 14507 Elf_Internal_Sym *isym;
252b5132 14508 struct elf_link_hash_entry *h;
b7693d02 14509 struct elf32_arm_link_hash_entry *eh;
252b5132 14510 unsigned long r_symndx;
eb043451 14511 int r_type;
9a5aca8c 14512
252b5132 14513 r_symndx = ELF32_R_SYM (rel->r_info);
eb043451 14514 r_type = ELF32_R_TYPE (rel->r_info);
eb043451 14515 r_type = arm_real_reloc_type (htab, r_type);
ba93b8ac 14516
ce98a316
NC		 14517 if (r_symndx >= nsyms
14518 /* PR 9934: It is possible to have relocations that do not
14519 refer to symbols, thus it is also possible to have an
14520 object file containing relocations but no symbol table. */
cf35638d 14521 && (r_symndx > STN_UNDEF || nsyms > 0))
ba93b8ac 14522 {
4eca0228
AM		 14523 _bfd_error_handler (_("%B: bad symbol index: %d"), abfd,
14524 r_symndx);
ba93b8ac
DJ		 14525 return FALSE;
14526 }
14527
34e77a92
RS		 14528 h = NULL;
14529 isym = NULL;
14530 if (nsyms > 0)
973a3492 14531 {
34e77a92
RS		 14532 if (r_symndx < symtab_hdr->sh_info)
14533 {
14534 /* A local symbol. */
14535 isym = bfd_sym_from_r_symndx (&htab->sym_cache,
14536 abfd, r_symndx);
14537 if (isym == NULL)
14538 return FALSE;
14539 }
14540 else
14541 {
14542 h = sym_hashes[r_symndx - symtab_hdr->sh_info];
14543 while (h->root.type == bfd_link_hash_indirect
14544 || h->root.type == bfd_link_hash_warning)
14545 h = (struct elf_link_hash_entry *) h->root.u.i.link;
81fbe831
AM		 14546
14547 /* PR15323, ref flags aren't set for references in the
14548 same object. */
14549 h->root.non_ir_ref = 1;
34e77a92 14550 }
973a3492 14551 }
9a5aca8c 14552
b7693d02
DJ		 14553 eh = (struct elf32_arm_link_hash_entry *) h;
14554
f6e32f6d
RS		 14555 call_reloc_p = FALSE;
14556 may_become_dynamic_p = FALSE;
14557 may_need_local_target_p = FALSE;
14558
0855e32b
NS		 14559 /* Could be done earlier, if h were already available. */
14560 r_type = elf32_arm_tls_transition (info, r_type, h);
eb043451 14561 switch (r_type)
99059e56 14562 {
5e681ec4 14563 case R_ARM_GOT32:
eb043451 14564 case R_ARM_GOT_PREL:
ba93b8ac
DJ		 14565 case R_ARM_TLS_GD32:
14566 case R_ARM_TLS_IE32:
0855e32b
NS		 14567 case R_ARM_TLS_GOTDESC:
14568 case R_ARM_TLS_DESCSEQ:
14569 case R_ARM_THM_TLS_DESCSEQ:
14570 case R_ARM_TLS_CALL:
14571 case R_ARM_THM_TLS_CALL:
5e681ec4 14572 /* This symbol requires a global offset table entry. */
ba93b8ac
DJ		 14573 {
14574 int tls_type, old_tls_type;
5e681ec4 14575
ba93b8ac
DJ		 14576 switch (r_type)
14577 {
14578 case R_ARM_TLS_GD32: tls_type = GOT_TLS_GD; break;
b38cadfb 14579
ba93b8ac 14580 case R_ARM_TLS_IE32: tls_type = GOT_TLS_IE; break;
b38cadfb 14581
0855e32b
NS		 14582 case R_ARM_TLS_GOTDESC:
14583 case R_ARM_TLS_CALL: case R_ARM_THM_TLS_CALL:
14584 case R_ARM_TLS_DESCSEQ: case R_ARM_THM_TLS_DESCSEQ:
14585 tls_type = GOT_TLS_GDESC; break;
b38cadfb 14586
ba93b8ac
DJ		 14587 default: tls_type = GOT_NORMAL; break;
14588 }
252b5132 14589
0e1862bb 14590 if (!bfd_link_executable (info) && (tls_type & GOT_TLS_IE))
eea6dad2
KM		 14591 info->flags |= DF_STATIC_TLS;
14592
ba93b8ac
DJ		 14593 if (h != NULL)
14594 {
14595 h->got.refcount++;
14596 old_tls_type = elf32_arm_hash_entry (h)->tls_type;
14597 }
14598 else
14599 {
ba93b8ac 14600 /* This is a global offset table entry for a local symbol. */
34e77a92
RS		 14601 if (!elf32_arm_allocate_local_sym_info (abfd))
14602 return FALSE;
14603 elf_local_got_refcounts (abfd)[r_symndx] += 1;
ba93b8ac
DJ		 14604 old_tls_type = elf32_arm_local_got_tls_type (abfd) [r_symndx];
14605 }
14606
0855e32b 14607 /* If a variable is accessed with both tls methods, two
99059e56 14608 slots may be created. */
0855e32b
NS		 14609 if (GOT_TLS_GD_ANY_P (old_tls_type)
14610 && GOT_TLS_GD_ANY_P (tls_type))
14611 tls_type |= old_tls_type;
14612
14613 /* We will already have issued an error message if there
14614 is a TLS/non-TLS mismatch, based on the symbol
14615 type. So just combine any TLS types needed. */
ba93b8ac
DJ		 14616 if (old_tls_type != GOT_UNKNOWN && old_tls_type != GOT_NORMAL
14617 && tls_type != GOT_NORMAL)
14618 tls_type |= old_tls_type;
14619
0855e32b 14620 /* If the symbol is accessed in both IE and GDESC
99059e56
RM		 14621 method, we're able to relax. Turn off the GDESC flag,
14622 without messing up with any other kind of tls types
6a631e86 14623 that may be involved. */
0855e32b
NS		 14624 if ((tls_type & GOT_TLS_IE) && (tls_type & GOT_TLS_GDESC))
14625 tls_type &= ~GOT_TLS_GDESC;
14626
ba93b8ac
DJ		 14627 if (old_tls_type != tls_type)
14628 {
14629 if (h != NULL)
14630 elf32_arm_hash_entry (h)->tls_type = tls_type;
14631 else
14632 elf32_arm_local_got_tls_type (abfd) [r_symndx] = tls_type;
14633 }
14634 }
8029a119 14635 /* Fall through. */
ba93b8ac
DJ		 14636
14637 case R_ARM_TLS_LDM32:
14638 if (r_type == R_ARM_TLS_LDM32)
14639 htab->tls_ldm_got.refcount++;
8029a119 14640 /* Fall through. */
252b5132 14641
c19d1205 14642 case R_ARM_GOTOFF32:
5e681ec4 14643 case R_ARM_GOTPC:
cbc704f3
RS		 14644 if (htab->root.sgot == NULL
14645 && !create_got_section (htab->root.dynobj, info))
14646 return FALSE;
252b5132
RH		 14647 break;
14648
252b5132 14649 case R_ARM_PC24:
7359ea65 14650 case R_ARM_PLT32:
5b5bb741
PB		 14651 case R_ARM_CALL:
14652 case R_ARM_JUMP24:
eb043451 14653 case R_ARM_PREL31:
c19d1205 14654 case R_ARM_THM_CALL:
bd97cb95
DJ		 14655 case R_ARM_THM_JUMP24:
14656 case R_ARM_THM_JUMP19:
f6e32f6d
RS		 14657 call_reloc_p = TRUE;
14658 may_need_local_target_p = TRUE;
14659 break;
14660
14661 case R_ARM_ABS12:
14662 /* VxWorks uses dynamic R_ARM_ABS12 relocations for
14663 ldr __GOTT_INDEX__ offsets. */
14664 if (!htab->vxworks_p)
14665 {
14666 may_need_local_target_p = TRUE;
14667 break;
14668 }
aebf9be7 14669 else goto jump_over;
9eaff861 14670
f6e32f6d 14671 /* Fall through. */
39623e12 14672
96c23d59
JM		 14673 case R_ARM_MOVW_ABS_NC:
14674 case R_ARM_MOVT_ABS:
14675 case R_ARM_THM_MOVW_ABS_NC:
14676 case R_ARM_THM_MOVT_ABS:
0e1862bb 14677 if (bfd_link_pic (info))
96c23d59 14678 {
4eca0228 14679 _bfd_error_handler
96c23d59
JM		 14680 (_("%B: relocation %s against `%s' can not be used when making a shared object; recompile with -fPIC"),
14681 abfd, elf32_arm_howto_table_1[r_type].name,
14682 (h) ? h->root.root.string : "a local symbol");
14683 bfd_set_error (bfd_error_bad_value);
14684 return FALSE;
14685 }
14686
14687 /* Fall through. */
39623e12
PB		 14688 case R_ARM_ABS32:
14689 case R_ARM_ABS32_NOI:
aebf9be7 14690 jump_over:
0e1862bb 14691 if (h != NULL && bfd_link_executable (info))
97323ad1
WN		 14692 {
14693 h->pointer_equality_needed = 1;
14694 }
14695 /* Fall through. */
39623e12
PB		 14696 case R_ARM_REL32:
14697 case R_ARM_REL32_NOI:
b6895b4f
PB		 14698 case R_ARM_MOVW_PREL_NC:
14699 case R_ARM_MOVT_PREL:
b6895b4f
PB		 14700 case R_ARM_THM_MOVW_PREL_NC:
14701 case R_ARM_THM_MOVT_PREL:
39623e12 14702
b7693d02 14703 /* Should the interworking branches be listed here? */
0e1862bb 14704 if ((bfd_link_pic (info) || htab->root.is_relocatable_executable)
34e77a92
RS		 14705 && (sec->flags & SEC_ALLOC) != 0)
14706 {
14707 if (h == NULL
469a3493 14708 && elf32_arm_howto_from_type (r_type)->pc_relative)
34e77a92
RS		 14709 {
14710 /* In shared libraries and relocatable executables,
14711 we treat local relative references as calls;
14712 see the related SYMBOL_CALLS_LOCAL code in
14713 allocate_dynrelocs. */
14714 call_reloc_p = TRUE;
14715 may_need_local_target_p = TRUE;
14716 }
14717 else
14718 /* We are creating a shared library or relocatable
14719 executable, and this is a reloc against a global symbol,
14720 or a non-PC-relative reloc against a local symbol.
14721 We may need to copy the reloc into the output. */
14722 may_become_dynamic_p = TRUE;
14723 }
f6e32f6d
RS		 14724 else
14725 may_need_local_target_p = TRUE;
252b5132
RH		 14726 break;
14727
99059e56
RM		 14728 /* This relocation describes the C++ object vtable hierarchy.
14729 Reconstruct it for later use during GC. */
14730 case R_ARM_GNU_VTINHERIT:
14731 if (!bfd_elf_gc_record_vtinherit (abfd, sec, h, rel->r_offset))
14732 return FALSE;
14733 break;
14734
14735 /* This relocation describes which C++ vtable entries are actually
14736 used. Record for later use during GC. */
14737 case R_ARM_GNU_VTENTRY:
14738 BFD_ASSERT (h != NULL);
14739 if (h != NULL
14740 && !bfd_elf_gc_record_vtentry (abfd, sec, h, rel->r_offset))
14741 return FALSE;
14742 break;
14743 }
f6e32f6d
RS		 14744
14745 if (h != NULL)
14746 {
14747 if (call_reloc_p)
14748 /* We may need a .plt entry if the function this reloc
14749 refers to is in a different object, regardless of the
14750 symbol's type. We can't tell for sure yet, because
14751 something later might force the symbol local. */
14752 h->needs_plt = 1;
14753 else if (may_need_local_target_p)
14754 /* If this reloc is in a read-only section, we might
14755 need a copy reloc. We can't check reliably at this
14756 stage whether the section is read-only, as input
14757 sections have not yet been mapped to output sections.
14758 Tentatively set the flag for now, and correct in
14759 adjust_dynamic_symbol. */
14760 h->non_got_ref = 1;
14761 }
14762
34e77a92
RS		 14763 if (may_need_local_target_p
14764 && (h != NULL || ELF32_ST_TYPE (isym->st_info) == STT_GNU_IFUNC))
f6e32f6d 14765 {
34e77a92
RS		 14766 union gotplt_union *root_plt;
14767 struct arm_plt_info *arm_plt;
14768 struct arm_local_iplt_info *local_iplt;
14769
14770 if (h != NULL)
14771 {
14772 root_plt = &h->plt;
14773 arm_plt = &eh->plt;
14774 }
14775 else
14776 {
14777 local_iplt = elf32_arm_create_local_iplt (abfd, r_symndx);
14778 if (local_iplt == NULL)
14779 return FALSE;
14780 root_plt = &local_iplt->root;
14781 arm_plt = &local_iplt->arm;
14782 }
14783
f6e32f6d
RS		 14784 /* If the symbol is a function that doesn't bind locally,
14785 this relocation will need a PLT entry. */
a8c887dd
NC		 14786 if (root_plt->refcount != -1)
14787 root_plt->refcount += 1;
34e77a92
RS		 14788
14789 if (!call_reloc_p)
14790 arm_plt->noncall_refcount++;
f6e32f6d
RS		 14791
14792 /* It's too early to use htab->use_blx here, so we have to
14793 record possible blx references separately from
14794 relocs that definitely need a thumb stub. */
14795
14796 if (r_type == R_ARM_THM_CALL)
34e77a92 14797 arm_plt->maybe_thumb_refcount += 1;
f6e32f6d
RS		 14798
14799 if (r_type == R_ARM_THM_JUMP24
14800 || r_type == R_ARM_THM_JUMP19)
34e77a92 14801 arm_plt->thumb_refcount += 1;
f6e32f6d
RS		 14802 }
14803
14804 if (may_become_dynamic_p)
14805 {
14806 struct elf_dyn_relocs *p, **head;
14807
14808 /* Create a reloc section in dynobj. */
14809 if (sreloc == NULL)
14810 {
14811 sreloc = _bfd_elf_make_dynamic_reloc_section
14812 (sec, dynobj, 2, abfd, ! htab->use_rel);
14813
14814 if (sreloc == NULL)
14815 return FALSE;
14816
14817 /* BPABI objects never have dynamic relocations mapped. */
14818 if (htab->symbian_p)
14819 {
14820 flagword flags;
14821
14822 flags = bfd_get_section_flags (dynobj, sreloc);
14823 flags &= ~(SEC_LOAD | SEC_ALLOC);
14824 bfd_set_section_flags (dynobj, sreloc, flags);
14825 }
14826 }
14827
14828 /* If this is a global symbol, count the number of
14829 relocations we need for this symbol. */
14830 if (h != NULL)
14831 head = &((struct elf32_arm_link_hash_entry *) h)->dyn_relocs;
14832 else
14833 {
34e77a92
RS		 14834 head = elf32_arm_get_local_dynreloc_list (abfd, r_symndx, isym);
14835 if (head == NULL)
f6e32f6d 14836 return FALSE;
f6e32f6d
RS		 14837 }
14838
14839 p = *head;
14840 if (p == NULL || p->sec != sec)
14841 {
14842 bfd_size_type amt = sizeof *p;
14843
14844 p = (struct elf_dyn_relocs *) bfd_alloc (htab->root.dynobj, amt);
14845 if (p == NULL)
14846 return FALSE;
14847 p->next = *head;
14848 *head = p;
14849 p->sec = sec;
14850 p->count = 0;
14851 p->pc_count = 0;
14852 }
14853
469a3493 14854 if (elf32_arm_howto_from_type (r_type)->pc_relative)
f6e32f6d
RS		 14855 p->pc_count += 1;
14856 p->count += 1;
14857 }
252b5132 14858 }
f21f3fe0 14859
b34976b6 14860 return TRUE;
252b5132
RH		 14861}
14862
9eaff861
AO		 14863static void
14864elf32_arm_update_relocs (asection *o,
14865 struct bfd_elf_section_reloc_data *reldata)
14866{
14867 void (*swap_in) (bfd *, const bfd_byte *, Elf_Internal_Rela *);
14868 void (*swap_out) (bfd *, const Elf_Internal_Rela *, bfd_byte *);
14869 const struct elf_backend_data *bed;
14870 _arm_elf_section_data *eado;
14871 struct bfd_link_order *p;
14872 bfd_byte *erela_head, *erela;
14873 Elf_Internal_Rela *irela_head, *irela;
14874 Elf_Internal_Shdr *rel_hdr;
14875 bfd *abfd;
14876 unsigned int count;
14877
14878 eado = get_arm_elf_section_data (o);
14879
14880 if (!eado || eado->elf.this_hdr.sh_type != SHT_ARM_EXIDX)
14881 return;
14882
14883 abfd = o->owner;
14884 bed = get_elf_backend_data (abfd);
14885 rel_hdr = reldata->hdr;
14886
14887 if (rel_hdr->sh_entsize == bed->s->sizeof_rel)
14888 {
14889 swap_in = bed->s->swap_reloc_in;
14890 swap_out = bed->s->swap_reloc_out;
14891 }
14892 else if (rel_hdr->sh_entsize == bed->s->sizeof_rela)
14893 {
14894 swap_in = bed->s->swap_reloca_in;
14895 swap_out = bed->s->swap_reloca_out;
14896 }
14897 else
14898 abort ();
14899
14900 erela_head = rel_hdr->contents;
14901 irela_head = (Elf_Internal_Rela *) bfd_zmalloc
14902 ((NUM_SHDR_ENTRIES (rel_hdr) + 1) * sizeof (*irela_head));
14903
14904 erela = erela_head;
14905 irela = irela_head;
14906 count = 0;
14907
14908 for (p = o->map_head.link_order; p; p = p->next)
14909 {
14910 if (p->type == bfd_section_reloc_link_order
14911 || p->type == bfd_symbol_reloc_link_order)
14912 {
14913 (*swap_in) (abfd, erela, irela);
14914 erela += rel_hdr->sh_entsize;
14915 irela++;
14916 count++;
14917 }
14918 else if (p->type == bfd_indirect_link_order)
14919 {
14920 struct bfd_elf_section_reloc_data *input_reldata;
14921 arm_unwind_table_edit *edit_list, *edit_tail;
14922 _arm_elf_section_data *eadi;
14923 bfd_size_type j;
14924 bfd_vma offset;
14925 asection *i;
14926
14927 i = p->u.indirect.section;
14928
14929 eadi = get_arm_elf_section_data (i);
14930 edit_list = eadi->u.exidx.unwind_edit_list;
14931 edit_tail = eadi->u.exidx.unwind_edit_tail;
14932 offset = o->vma + i->output_offset;
14933
14934 if (eadi->elf.rel.hdr &&
14935 eadi->elf.rel.hdr->sh_entsize == rel_hdr->sh_entsize)
14936 input_reldata = &eadi->elf.rel;
14937 else if (eadi->elf.rela.hdr &&
14938 eadi->elf.rela.hdr->sh_entsize == rel_hdr->sh_entsize)
14939 input_reldata = &eadi->elf.rela;
14940 else
14941 abort ();
14942
14943 if (edit_list)
14944 {
14945 for (j = 0; j < NUM_SHDR_ENTRIES (input_reldata->hdr); j++)
14946 {
14947 arm_unwind_table_edit *edit_node, *edit_next;
14948 bfd_vma bias;
14949 bfd_vma index;
14950
14951 (*swap_in) (abfd, erela, irela);
14952 index = (irela->r_offset - offset) / 8;
14953
14954 bias = 0;
14955 edit_node = edit_list;
14956 for (edit_next = edit_list;
14957 edit_next && edit_next->index <= index;
14958 edit_next = edit_node->next)
14959 {
14960 bias++;
14961 edit_node = edit_next;
14962 }
14963
14964 if (edit_node->type != DELETE_EXIDX_ENTRY
14965 || edit_node->index != index)
14966 {
14967 irela->r_offset -= bias * 8;
14968 irela++;
14969 count++;
14970 }
14971
14972 erela += rel_hdr->sh_entsize;
14973 }
14974
14975 if (edit_tail->type == INSERT_EXIDX_CANTUNWIND_AT_END)
14976 {
14977 /* New relocation entity. */
14978 asection *text_sec = edit_tail->linked_section;
14979 asection *text_out = text_sec->output_section;
14980 bfd_vma exidx_offset = offset + i->size - 8;
14981
14982 irela->r_addend = 0;
14983 irela->r_offset = exidx_offset;
14984 irela->r_info = ELF32_R_INFO
14985 (text_out->target_index, R_ARM_PREL31);
14986 irela++;
14987 count++;
14988 }
14989 }
14990 else
14991 {
14992 for (j = 0; j < NUM_SHDR_ENTRIES (input_reldata->hdr); j++)
14993 {
14994 (*swap_in) (abfd, erela, irela);
14995 erela += rel_hdr->sh_entsize;
14996 irela++;
14997 }
14998
14999 count += NUM_SHDR_ENTRIES (input_reldata->hdr);
15000 }
15001 }
15002 }
15003
15004 reldata->count = count;
15005 rel_hdr->sh_size = count * rel_hdr->sh_entsize;
15006
15007 erela = erela_head;
15008 irela = irela_head;
15009 while (count > 0)
15010 {
15011 (*swap_out) (abfd, irela, erela);
15012 erela += rel_hdr->sh_entsize;
15013 irela++;
15014 count--;
15015 }
15016
15017 free (irela_head);
15018
15019 /* Hashes are no longer valid. */
15020 free (reldata->hashes);
15021 reldata->hashes = NULL;
15022}
15023
6a5bb875 15024/* Unwinding tables are not referenced directly. This pass marks them as
4ba2ef8f
TP		 15025 required if the corresponding code section is marked. Similarly, ARMv8-M
15026 secure entry functions can only be referenced by SG veneers which are
15027 created after the GC process. They need to be marked in case they reside in
15028 their own section (as would be the case if code was compiled with
15029 -ffunction-sections). */
6a5bb875
PB		 15030
15031static bfd_boolean
906e58ca
NC		 15032elf32_arm_gc_mark_extra_sections (struct bfd_link_info *info,
15033 elf_gc_mark_hook_fn gc_mark_hook)
6a5bb875
PB		 15034{
15035 bfd *sub;
15036 Elf_Internal_Shdr **elf_shdrp;
4ba2ef8f
TP		 15037 asection *cmse_sec;
15038 obj_attribute *out_attr;
15039 Elf_Internal_Shdr *symtab_hdr;
15040 unsigned i, sym_count, ext_start;
15041 const struct elf_backend_data *bed;
15042 struct elf_link_hash_entry **sym_hashes;
15043 struct elf32_arm_link_hash_entry *cmse_hash;
15044 bfd_boolean again, is_v8m, first_bfd_browse = TRUE;
6a5bb875 15045
7f6ab9f8
AM		 15046 _bfd_elf_gc_mark_extra_sections (info, gc_mark_hook);
15047
4ba2ef8f
TP		 15048 out_attr = elf_known_obj_attributes_proc (info->output_bfd);
15049 is_v8m = out_attr[Tag_CPU_arch].i >= TAG_CPU_ARCH_V8M_BASE
15050 && out_attr[Tag_CPU_arch_profile].i == 'M';
15051
6a5bb875
PB		 15052 /* Marking EH data may cause additional code sections to be marked,
15053 requiring multiple passes. */
15054 again = TRUE;
15055 while (again)
15056 {
15057 again = FALSE;
c72f2fb2 15058 for (sub = info->input_bfds; sub != NULL; sub = sub->link.next)
6a5bb875
PB		 15059 {
15060 asection *o;
15061
0ffa91dd 15062 if (! is_arm_elf (sub))
6a5bb875
PB		 15063 continue;
15064
15065 elf_shdrp = elf_elfsections (sub);
15066 for (o = sub->sections; o != NULL; o = o->next)
15067 {
15068 Elf_Internal_Shdr *hdr;
0ffa91dd 15069
6a5bb875 15070 hdr = &elf_section_data (o)->this_hdr;
4fbb74a6
AM		 15071 if (hdr->sh_type == SHT_ARM_EXIDX
15072 && hdr->sh_link
15073 && hdr->sh_link < elf_numsections (sub)
6a5bb875
PB		 15074 && !o->gc_mark
15075 && elf_shdrp[hdr->sh_link]->bfd_section->gc_mark)
15076 {
15077 again = TRUE;
15078 if (!_bfd_elf_gc_mark (info, o, gc_mark_hook))
15079 return FALSE;
15080 }
15081 }
4ba2ef8f
TP		 15082
15083 /* Mark section holding ARMv8-M secure entry functions. We mark all
15084 of them so no need for a second browsing. */
15085 if (is_v8m && first_bfd_browse)
15086 {
15087 sym_hashes = elf_sym_hashes (sub);
15088 bed = get_elf_backend_data (sub);
15089 symtab_hdr = &elf_tdata (sub)->symtab_hdr;
15090 sym_count = symtab_hdr->sh_size / bed->s->sizeof_sym;
15091 ext_start = symtab_hdr->sh_info;
15092
15093 /* Scan symbols. */
15094 for (i = ext_start; i < sym_count; i++)
15095 {
15096 cmse_hash = elf32_arm_hash_entry (sym_hashes[i - ext_start]);
15097
15098 /* Assume it is a special symbol. If not, cmse_scan will
15099 warn about it and user can do something about it. */
15100 if (ARM_GET_SYM_CMSE_SPCL (cmse_hash->root.target_internal))
15101 {
15102 cmse_sec = cmse_hash->root.root.u.def.section;
5025eb7c
AO		 15103 if (!cmse_sec->gc_mark
15104 && !_bfd_elf_gc_mark (info, cmse_sec, gc_mark_hook))
4ba2ef8f
TP		 15105 return FALSE;
15106 }
15107 }
15108 }
6a5bb875 15109 }
4ba2ef8f 15110 first_bfd_browse = FALSE;
6a5bb875
PB		 15111 }
15112
15113 return TRUE;
15114}
15115
3c9458e9
NC		 15116/* Treat mapping symbols as special target symbols. */
15117
15118static bfd_boolean
15119elf32_arm_is_target_special_symbol (bfd * abfd ATTRIBUTE_UNUSED, asymbol * sym)
15120{
b0796911
PB		 15121 return bfd_is_arm_special_symbol_name (sym->name,
15122 BFD_ARM_SPECIAL_SYM_TYPE_ANY);
3c9458e9
NC		 15123}
15124
0367ecfb
NC		 15125/* This is a copy of elf_find_function() from elf.c except that
15126 ARM mapping symbols are ignored when looking for function names
15127 and STT_ARM_TFUNC is considered to a function type. */
252b5132 15128
0367ecfb
NC		 15129static bfd_boolean
15130arm_elf_find_function (bfd * abfd ATTRIBUTE_UNUSED,
0367ecfb 15131 asymbol ** symbols,
fb167eb2 15132 asection * section,
0367ecfb
NC		 15133 bfd_vma offset,
15134 const char ** filename_ptr,
15135 const char ** functionname_ptr)
15136{
15137 const char * filename = NULL;
15138 asymbol * func = NULL;
15139 bfd_vma low_func = 0;
15140 asymbol ** p;
252b5132
RH		 15141
15142 for (p = symbols; *p != NULL; p++)
15143 {
15144 elf_symbol_type *q;
15145
15146 q = (elf_symbol_type *) *p;
15147
252b5132
RH		 15148 switch (ELF_ST_TYPE (q->internal_elf_sym.st_info))
15149 {
15150 default:
15151 break;
15152 case STT_FILE:
15153 filename = bfd_asymbol_name (&q->symbol);
15154 break;
252b5132
RH		 15155 case STT_FUNC:
15156 case STT_ARM_TFUNC:
9d2da7ca 15157 case STT_NOTYPE:
b0796911 15158 /* Skip mapping symbols. */
0367ecfb 15159 if ((q->symbol.flags & BSF_LOCAL)
b0796911
PB		 15160 && bfd_is_arm_special_symbol_name (q->symbol.name,
15161 BFD_ARM_SPECIAL_SYM_TYPE_ANY))
0367ecfb
NC		 15162 continue;
15163 /* Fall through. */
6b40fcba 15164 if (bfd_get_section (&q->symbol) == section
252b5132
RH		 15165 && q->symbol.value >= low_func
15166 && q->symbol.value <= offset)
15167 {
15168 func = (asymbol *) q;
15169 low_func = q->symbol.value;
15170 }
15171 break;
15172 }
15173 }
15174
15175 if (func == NULL)
b34976b6 15176 return FALSE;
252b5132 15177
0367ecfb
NC		 15178 if (filename_ptr)
15179 *filename_ptr = filename;
15180 if (functionname_ptr)
15181 *functionname_ptr = bfd_asymbol_name (func);
15182
15183 return TRUE;
906e58ca 15184}
0367ecfb
NC		 15185
15186
15187/* Find the nearest line to a particular section and offset, for error
15188 reporting. This code is a duplicate of the code in elf.c, except
15189 that it uses arm_elf_find_function. */
15190
15191static bfd_boolean
15192elf32_arm_find_nearest_line (bfd * abfd,
0367ecfb 15193 asymbol ** symbols,
fb167eb2 15194 asection * section,
0367ecfb
NC		 15195 bfd_vma offset,
15196 const char ** filename_ptr,
15197 const char ** functionname_ptr,
fb167eb2
AM		 15198 unsigned int * line_ptr,
15199 unsigned int * discriminator_ptr)
0367ecfb
NC		 15200{
15201 bfd_boolean found = FALSE;
15202
fb167eb2 15203 if (_bfd_dwarf2_find_nearest_line (abfd, symbols, NULL, section, offset,
0367ecfb 15204 filename_ptr, functionname_ptr,
fb167eb2
AM		 15205 line_ptr, discriminator_ptr,
15206 dwarf_debug_sections, 0,
0367ecfb
NC		 15207 & elf_tdata (abfd)->dwarf2_find_line_info))
15208 {
15209 if (!*functionname_ptr)
fb167eb2 15210 arm_elf_find_function (abfd, symbols, section, offset,
0367ecfb
NC		 15211 *filename_ptr ? NULL : filename_ptr,
15212 functionname_ptr);
f21f3fe0 15213
0367ecfb
NC		 15214 return TRUE;
15215 }
15216
fb167eb2
AM		 15217 /* Skip _bfd_dwarf1_find_nearest_line since no known ARM toolchain
15218 uses DWARF1. */
15219
0367ecfb
NC		 15220 if (! _bfd_stab_section_find_nearest_line (abfd, symbols, section, offset,
15221 & found, filename_ptr,
15222 functionname_ptr, line_ptr,
15223 & elf_tdata (abfd)->line_info))
15224 return FALSE;
15225
15226 if (found && (*functionname_ptr || *line_ptr))
15227 return TRUE;
15228
15229 if (symbols == NULL)
15230 return FALSE;
15231
fb167eb2 15232 if (! arm_elf_find_function (abfd, symbols, section, offset,
0367ecfb
NC		 15233 filename_ptr, functionname_ptr))
15234 return FALSE;
15235
15236 *line_ptr = 0;
b34976b6 15237 return TRUE;
252b5132
RH		 15238}
15239
4ab527b0
FF		 15240static bfd_boolean
15241elf32_arm_find_inliner_info (bfd * abfd,
15242 const char ** filename_ptr,
15243 const char ** functionname_ptr,
15244 unsigned int * line_ptr)
15245{
15246 bfd_boolean found;
15247 found = _bfd_dwarf2_find_inliner_info (abfd, filename_ptr,
15248 functionname_ptr, line_ptr,
15249 & elf_tdata (abfd)->dwarf2_find_line_info);
15250 return found;
15251}
15252
252b5132
RH		 15253/* Adjust a symbol defined by a dynamic object and referenced by a
15254 regular object. The current definition is in some section of the
15255 dynamic object, but we're not including those sections. We have to
15256 change the definition to something the rest of the link can
15257 understand. */
15258
b34976b6 15259static bfd_boolean
57e8b36a
NC		 15260elf32_arm_adjust_dynamic_symbol (struct bfd_link_info * info,
15261 struct elf_link_hash_entry * h)
252b5132
RH		 15262{
15263 bfd * dynobj;
15264 asection * s;
b7693d02 15265 struct elf32_arm_link_hash_entry * eh;
67687978 15266 struct elf32_arm_link_hash_table *globals;
252b5132 15267
67687978 15268 globals = elf32_arm_hash_table (info);
4dfe6ac6
NC		 15269 if (globals == NULL)
15270 return FALSE;
15271
252b5132
RH		 15272 dynobj = elf_hash_table (info)->dynobj;
15273
15274 /* Make sure we know what is going on here. */
15275 BFD_ASSERT (dynobj != NULL
f5385ebf 15276 && (h->needs_plt
34e77a92 15277 || h->type == STT_GNU_IFUNC
f6e332e6 15278 || h->u.weakdef != NULL
f5385ebf
AM		 15279 || (h->def_dynamic
15280 && h->ref_regular
15281 && !h->def_regular)));
252b5132 15282
b7693d02
DJ		 15283 eh = (struct elf32_arm_link_hash_entry *) h;
15284
252b5132
RH		 15285 /* If this is a function, put it in the procedure linkage table. We
15286 will fill in the contents of the procedure linkage table later,
15287 when we know the address of the .got section. */
34e77a92 15288 if (h->type == STT_FUNC || h->type == STT_GNU_IFUNC || h->needs_plt)
252b5132 15289 {
34e77a92
RS		 15290 /* Calls to STT_GNU_IFUNC symbols always use a PLT, even if the
15291 symbol binds locally. */
5e681ec4 15292 if (h->plt.refcount <= 0
34e77a92
RS		 15293 || (h->type != STT_GNU_IFUNC
15294 && (SYMBOL_CALLS_LOCAL (info, h)
15295 || (ELF_ST_VISIBILITY (h->other) != STV_DEFAULT
15296 && h->root.type == bfd_link_hash_undefweak))))
252b5132
RH		 15297 {
15298 /* This case can occur if we saw a PLT32 reloc in an input
5e681ec4
PB		 15299 file, but the symbol was never referred to by a dynamic
15300 object, or if all references were garbage collected. In
15301 such a case, we don't actually need to build a procedure
15302 linkage table, and we can just do a PC24 reloc instead. */
15303 h->plt.offset = (bfd_vma) -1;
34e77a92
RS		 15304 eh->plt.thumb_refcount = 0;
15305 eh->plt.maybe_thumb_refcount = 0;
15306 eh->plt.noncall_refcount = 0;
f5385ebf 15307 h->needs_plt = 0;
252b5132
RH		 15308 }
15309
b34976b6 15310 return TRUE;
252b5132 15311 }
5e681ec4 15312 else
b7693d02
DJ		 15313 {
15314 /* It's possible that we incorrectly decided a .plt reloc was
15315 needed for an R_ARM_PC24 or similar reloc to a non-function sym
15316 in check_relocs. We can't decide accurately between function
15317 and non-function syms in check-relocs; Objects loaded later in
15318 the link may change h->type. So fix it now. */
15319 h->plt.offset = (bfd_vma) -1;
34e77a92
RS		 15320 eh->plt.thumb_refcount = 0;
15321 eh->plt.maybe_thumb_refcount = 0;
15322 eh->plt.noncall_refcount = 0;
b7693d02 15323 }
252b5132
RH		 15324
15325 /* If this is a weak symbol, and there is a real definition, the
15326 processor independent code will have arranged for us to see the
15327 real definition first, and we can just use the same value. */
f6e332e6 15328 if (h->u.weakdef != NULL)
252b5132 15329 {
f6e332e6
AM		 15330 BFD_ASSERT (h->u.weakdef->root.type == bfd_link_hash_defined
15331 || h->u.weakdef->root.type == bfd_link_hash_defweak);
15332 h->root.u.def.section = h->u.weakdef->root.u.def.section;
15333 h->root.u.def.value = h->u.weakdef->root.u.def.value;
b34976b6 15334 return TRUE;
252b5132
RH		 15335 }
15336
ba93b8ac
DJ		 15337 /* If there are no non-GOT references, we do not need a copy
15338 relocation. */
15339 if (!h->non_got_ref)
15340 return TRUE;
15341
252b5132
RH		 15342 /* This is a reference to a symbol defined by a dynamic object which
15343 is not a function. */
15344
15345 /* If we are creating a shared library, we must presume that the
15346 only references to the symbol are via the global offset table.
15347 For such cases we need not do anything here; the relocations will
67687978
PB		 15348 be handled correctly by relocate_section. Relocatable executables
15349 can reference data in shared objects directly, so we don't need to
15350 do anything here. */
0e1862bb 15351 if (bfd_link_pic (info) || globals->root.is_relocatable_executable)
b34976b6 15352 return TRUE;
252b5132
RH		 15353
15354 /* We must allocate the symbol in our .dynbss section, which will
15355 become part of the .bss section of the executable. There will be
15356 an entry for this symbol in the .dynsym section. The dynamic
15357 object will contain position independent code, so all references
15358 from the dynamic object to this symbol will go through the global
15359 offset table. The dynamic linker will use the .dynsym entry to
15360 determine the address it must put in the global offset table, so
15361 both the dynamic object and the regular object will refer to the
15362 same memory location for the variable. */
3d4d4302 15363 s = bfd_get_linker_section (dynobj, ".dynbss");
252b5132
RH		 15364 BFD_ASSERT (s != NULL);
15365
5522f910
NC		 15366 /* If allowed, we must generate a R_ARM_COPY reloc to tell the dynamic
15367 linker to copy the initial value out of the dynamic object and into
15368 the runtime process image. We need to remember the offset into the
00a97672 15369 .rel(a).bss section we are going to use. */
5522f910
NC		 15370 if (info->nocopyreloc == 0
15371 && (h->root.u.def.section->flags & SEC_ALLOC) != 0
5522f910 15372 && h->size != 0)
252b5132
RH		 15373 {
15374 asection *srel;
15375
3d4d4302 15376 srel = bfd_get_linker_section (dynobj, RELOC_SECTION (globals, ".bss"));
47beaa6a 15377 elf32_arm_allocate_dynrelocs (info, srel, 1);
f5385ebf 15378 h->needs_copy = 1;
252b5132
RH		 15379 }
15380
6cabe1ea 15381 return _bfd_elf_adjust_dynamic_copy (info, h, s);
252b5132
RH		 15382}
15383
5e681ec4
PB		 15384/* Allocate space in .plt, .got and associated reloc sections for
15385 dynamic relocs. */
15386
15387static bfd_boolean
47beaa6a 15388allocate_dynrelocs_for_symbol (struct elf_link_hash_entry *h, void * inf)
5e681ec4
PB		 15389{
15390 struct bfd_link_info *info;
15391 struct elf32_arm_link_hash_table *htab;
15392 struct elf32_arm_link_hash_entry *eh;
0bdcacaf 15393 struct elf_dyn_relocs *p;
5e681ec4
PB		 15394
15395 if (h->root.type == bfd_link_hash_indirect)
15396 return TRUE;
15397
e6a6bb22
AM		 15398 eh = (struct elf32_arm_link_hash_entry *) h;
15399
5e681ec4
PB		 15400 info = (struct bfd_link_info *) inf;
15401 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 15402 if (htab == NULL)
15403 return FALSE;
5e681ec4 15404
34e77a92 15405 if ((htab->root.dynamic_sections_created || h->type == STT_GNU_IFUNC)
5e681ec4
PB		 15406 && h->plt.refcount > 0)
15407 {
15408 /* Make sure this symbol is output as a dynamic symbol.
15409 Undefined weak syms won't yet be marked as dynamic. */
15410 if (h->dynindx == -1
f5385ebf 15411 && !h->forced_local)
5e681ec4 15412 {
c152c796 15413 if (! bfd_elf_link_record_dynamic_symbol (info, h))
5e681ec4
PB		 15414 return FALSE;
15415 }
15416
34e77a92
RS		 15417 /* If the call in the PLT entry binds locally, the associated
15418 GOT entry should use an R_ARM_IRELATIVE relocation instead of
15419 the usual R_ARM_JUMP_SLOT. Put it in the .iplt section rather
15420 than the .plt section. */
15421 if (h->type == STT_GNU_IFUNC && SYMBOL_CALLS_LOCAL (info, h))
15422 {
15423 eh->is_iplt = 1;
15424 if (eh->plt.noncall_refcount == 0
15425 && SYMBOL_REFERENCES_LOCAL (info, h))
15426 /* All non-call references can be resolved directly.
15427 This means that they can (and in some cases, must)
15428 resolve directly to the run-time target, rather than
15429 to the PLT. That in turns means that any .got entry
15430 would be equal to the .igot.plt entry, so there's
15431 no point having both. */
15432 h->got.refcount = 0;
15433 }
15434
0e1862bb 15435 if (bfd_link_pic (info)
34e77a92 15436 || eh->is_iplt
7359ea65 15437 || WILL_CALL_FINISH_DYNAMIC_SYMBOL (1, 0, h))
5e681ec4 15438 {
34e77a92 15439 elf32_arm_allocate_plt_entry (info, eh->is_iplt, &h->plt, &eh->plt);
b7693d02 15440
5e681ec4
PB		 15441 /* If this symbol is not defined in a regular file, and we are
15442 not generating a shared library, then set the symbol to this
15443 location in the .plt. This is required to make function
15444 pointers compare as equal between the normal executable and
15445 the shared library. */
0e1862bb 15446 if (! bfd_link_pic (info)
f5385ebf 15447 && !h->def_regular)
5e681ec4 15448 {
34e77a92 15449 h->root.u.def.section = htab->root.splt;
5e681ec4 15450 h->root.u.def.value = h->plt.offset;
5e681ec4 15451
67d74e43
DJ		 15452 /* Make sure the function is not marked as Thumb, in case
15453 it is the target of an ABS32 relocation, which will
15454 point to the PLT entry. */
39d911fc 15455 ARM_SET_SYM_BRANCH_TYPE (h->target_internal, ST_BRANCH_TO_ARM);
67d74e43 15456 }
022f8312 15457
00a97672
RS		 15458 /* VxWorks executables have a second set of relocations for
15459 each PLT entry. They go in a separate relocation section,
15460 which is processed by the kernel loader. */
0e1862bb 15461 if (htab->vxworks_p && !bfd_link_pic (info))
00a97672
RS		 15462 {
15463 /* There is a relocation for the initial PLT entry:
15464 an R_ARM_32 relocation for _GLOBAL_OFFSET_TABLE_. */
15465 if (h->plt.offset == htab->plt_header_size)
47beaa6a 15466 elf32_arm_allocate_dynrelocs (info, htab->srelplt2, 1);
00a97672
RS		 15467
15468 /* There are two extra relocations for each subsequent
15469 PLT entry: an R_ARM_32 relocation for the GOT entry,
15470 and an R_ARM_32 relocation for the PLT entry. */
47beaa6a 15471 elf32_arm_allocate_dynrelocs (info, htab->srelplt2, 2);
00a97672 15472 }
5e681ec4
PB		 15473 }
15474 else
15475 {
15476 h->plt.offset = (bfd_vma) -1;
f5385ebf 15477 h->needs_plt = 0;
5e681ec4
PB		 15478 }
15479 }
15480 else
15481 {
15482 h->plt.offset = (bfd_vma) -1;
f5385ebf 15483 h->needs_plt = 0;
5e681ec4
PB		 15484 }
15485
0855e32b
NS		 15486 eh = (struct elf32_arm_link_hash_entry *) h;
15487 eh->tlsdesc_got = (bfd_vma) -1;
15488
5e681ec4
PB		 15489 if (h->got.refcount > 0)
15490 {
15491 asection *s;
15492 bfd_boolean dyn;
ba93b8ac
DJ		 15493 int tls_type = elf32_arm_hash_entry (h)->tls_type;
15494 int indx;
5e681ec4
PB		 15495
15496 /* Make sure this symbol is output as a dynamic symbol.
15497 Undefined weak syms won't yet be marked as dynamic. */
15498 if (h->dynindx == -1
f5385ebf 15499 && !h->forced_local)
5e681ec4 15500 {
c152c796 15501 if (! bfd_elf_link_record_dynamic_symbol (info, h))
5e681ec4
PB		 15502 return FALSE;
15503 }
15504
e5a52504
MM		 15505 if (!htab->symbian_p)
15506 {
362d30a1 15507 s = htab->root.sgot;
e5a52504 15508 h->got.offset = s->size;
ba93b8ac
DJ		 15509
15510 if (tls_type == GOT_UNKNOWN)
15511 abort ();
15512
15513 if (tls_type == GOT_NORMAL)
15514 /* Non-TLS symbols need one GOT slot. */
15515 s->size += 4;
15516 else
15517 {
99059e56
RM		 15518 if (tls_type & GOT_TLS_GDESC)
15519 {
0855e32b 15520 /* R_ARM_TLS_DESC needs 2 GOT slots. */
99059e56 15521 eh->tlsdesc_got
0855e32b
NS		 15522 = (htab->root.sgotplt->size
15523 - elf32_arm_compute_jump_table_size (htab));
99059e56
RM		 15524 htab->root.sgotplt->size += 8;
15525 h->got.offset = (bfd_vma) -2;
34e77a92 15526 /* plt.got_offset needs to know there's a TLS_DESC
0855e32b 15527 reloc in the middle of .got.plt. */
99059e56
RM		 15528 htab->num_tls_desc++;
15529 }
0855e32b 15530
ba93b8ac 15531 if (tls_type & GOT_TLS_GD)
0855e32b
NS		 15532 {
15533 /* R_ARM_TLS_GD32 needs 2 consecutive GOT slots. If
15534 the symbol is both GD and GDESC, got.offset may
15535 have been overwritten. */
15536 h->got.offset = s->size;
15537 s->size += 8;
15538 }
15539
ba93b8ac
DJ		 15540 if (tls_type & GOT_TLS_IE)
15541 /* R_ARM_TLS_IE32 needs one GOT slot. */
15542 s->size += 4;
15543 }
15544
e5a52504 15545 dyn = htab->root.dynamic_sections_created;
ba93b8ac
DJ		 15546
15547 indx = 0;
0e1862bb
L		 15548 if (WILL_CALL_FINISH_DYNAMIC_SYMBOL (dyn,
15549 bfd_link_pic (info),
15550 h)
15551 && (!bfd_link_pic (info)
ba93b8ac
DJ		 15552 || !SYMBOL_REFERENCES_LOCAL (info, h)))
15553 indx = h->dynindx;
15554
15555 if (tls_type != GOT_NORMAL
0e1862bb 15556 && (bfd_link_pic (info) || indx != 0)
ba93b8ac
DJ		 15557 && (ELF_ST_VISIBILITY (h->other) == STV_DEFAULT
15558 || h->root.type != bfd_link_hash_undefweak))
15559 {
15560 if (tls_type & GOT_TLS_IE)
47beaa6a 15561 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
ba93b8ac
DJ		 15562
15563 if (tls_type & GOT_TLS_GD)
47beaa6a 15564 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
ba93b8ac 15565
b38cadfb 15566 if (tls_type & GOT_TLS_GDESC)
0855e32b 15567 {
47beaa6a 15568 elf32_arm_allocate_dynrelocs (info, htab->root.srelplt, 1);
0855e32b
NS		 15569 /* GDESC needs a trampoline to jump to. */
15570 htab->tls_trampoline = -1;
15571 }
15572
15573 /* Only GD needs it. GDESC just emits one relocation per
15574 2 entries. */
b38cadfb 15575 if ((tls_type & GOT_TLS_GD) && indx != 0)
47beaa6a 15576 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
ba93b8ac 15577 }
6f820c85 15578 else if (indx != -1 && !SYMBOL_REFERENCES_LOCAL (info, h))
b436d854
RS		 15579 {
15580 if (htab->root.dynamic_sections_created)
15581 /* Reserve room for the GOT entry's R_ARM_GLOB_DAT relocation. */
15582 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
15583 }
34e77a92
RS		 15584 else if (h->type == STT_GNU_IFUNC
15585 && eh->plt.noncall_refcount == 0)
15586 /* No non-call references resolve the STT_GNU_IFUNC's PLT entry;
15587 they all resolve dynamically instead. Reserve room for the
15588 GOT entry's R_ARM_IRELATIVE relocation. */
15589 elf32_arm_allocate_irelocs (info, htab->root.srelgot, 1);
0e1862bb
L		 15590 else if (bfd_link_pic (info)
15591 && (ELF_ST_VISIBILITY (h->other) == STV_DEFAULT
15592 || h->root.type != bfd_link_hash_undefweak))
b436d854 15593 /* Reserve room for the GOT entry's R_ARM_RELATIVE relocation. */
47beaa6a 15594 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
e5a52504 15595 }
5e681ec4
PB		 15596 }
15597 else
15598 h->got.offset = (bfd_vma) -1;
15599
a4fd1a8e
PB		 15600 /* Allocate stubs for exported Thumb functions on v4t. */
15601 if (!htab->use_blx && h->dynindx != -1
0eaedd0e 15602 && h->def_regular
39d911fc 15603 && ARM_GET_SYM_BRANCH_TYPE (h->target_internal) == ST_BRANCH_TO_THUMB
a4fd1a8e
PB		 15604 && ELF_ST_VISIBILITY (h->other) == STV_DEFAULT)
15605 {
15606 struct elf_link_hash_entry * th;
15607 struct bfd_link_hash_entry * bh;
15608 struct elf_link_hash_entry * myh;
15609 char name[1024];
15610 asection *s;
15611 bh = NULL;
15612 /* Create a new symbol to regist the real location of the function. */
15613 s = h->root.u.def.section;
906e58ca 15614 sprintf (name, "__real_%s", h->root.root.string);
a4fd1a8e
PB		 15615 _bfd_generic_link_add_one_symbol (info, s->owner,
15616 name, BSF_GLOBAL, s,
15617 h->root.u.def.value,
15618 NULL, TRUE, FALSE, &bh);
15619
15620 myh = (struct elf_link_hash_entry *) bh;
35fc36a8 15621 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
a4fd1a8e 15622 myh->forced_local = 1;
39d911fc 15623 ARM_SET_SYM_BRANCH_TYPE (myh->target_internal, ST_BRANCH_TO_THUMB);
a4fd1a8e
PB		 15624 eh->export_glue = myh;
15625 th = record_arm_to_thumb_glue (info, h);
15626 /* Point the symbol at the stub. */
15627 h->type = ELF_ST_INFO (ELF_ST_BIND (h->type), STT_FUNC);
39d911fc 15628 ARM_SET_SYM_BRANCH_TYPE (h->target_internal, ST_BRANCH_TO_ARM);
a4fd1a8e
PB		 15629 h->root.u.def.section = th->root.u.def.section;
15630 h->root.u.def.value = th->root.u.def.value & ~1;
15631 }
15632
0bdcacaf 15633 if (eh->dyn_relocs == NULL)
5e681ec4
PB		 15634 return TRUE;
15635
15636 /* In the shared -Bsymbolic case, discard space allocated for
15637 dynamic pc-relative relocs against symbols which turn out to be
15638 defined in regular objects. For the normal shared case, discard
15639 space for pc-relative relocs that have become local due to symbol
15640 visibility changes. */
15641
0e1862bb 15642 if (bfd_link_pic (info) || htab->root.is_relocatable_executable)
5e681ec4 15643 {
469a3493
RM		 15644 /* Relocs that use pc_count are PC-relative forms, which will appear
15645 on something like ".long foo - ." or "movw REG, foo - .". We want
15646 calls to protected symbols to resolve directly to the function
15647 rather than going via the plt. If people want function pointer
15648 comparisons to work as expected then they should avoid writing
15649 assembly like ".long foo - .". */
ba93b8ac
DJ		 15650 if (SYMBOL_CALLS_LOCAL (info, h))
15651 {
0bdcacaf 15652 struct elf_dyn_relocs **pp;
ba93b8ac 15653
0bdcacaf 15654 for (pp = &eh->dyn_relocs; (p = *pp) != NULL; )
ba93b8ac
DJ		 15655 {
15656 p->count -= p->pc_count;
15657 p->pc_count = 0;
15658 if (p->count == 0)
15659 *pp = p->next;
15660 else
15661 pp = &p->next;
15662 }
15663 }
15664
4dfe6ac6 15665 if (htab->vxworks_p)
3348747a 15666 {
0bdcacaf 15667 struct elf_dyn_relocs **pp;
3348747a 15668
0bdcacaf 15669 for (pp = &eh->dyn_relocs; (p = *pp) != NULL; )
3348747a 15670 {
0bdcacaf 15671 if (strcmp (p->sec->output_section->name, ".tls_vars") == 0)
3348747a
NS		 15672 *pp = p->next;
15673 else
15674 pp = &p->next;
15675 }
15676 }
15677
ba93b8ac 15678 /* Also discard relocs on undefined weak syms with non-default
99059e56 15679 visibility. */
0bdcacaf 15680 if (eh->dyn_relocs != NULL
5e681ec4 15681 && h->root.type == bfd_link_hash_undefweak)
22d606e9
AM		 15682 {
15683 if (ELF_ST_VISIBILITY (h->other) != STV_DEFAULT)
0bdcacaf 15684 eh->dyn_relocs = NULL;
22d606e9
AM		 15685
15686 /* Make sure undefined weak symbols are output as a dynamic
15687 symbol in PIEs. */
15688 else if (h->dynindx == -1
15689 && !h->forced_local)
15690 {
15691 if (! bfd_elf_link_record_dynamic_symbol (info, h))
15692 return FALSE;
15693 }
15694 }
15695
67687978
PB		 15696 else if (htab->root.is_relocatable_executable && h->dynindx == -1
15697 && h->root.type == bfd_link_hash_new)
15698 {
15699 /* Output absolute symbols so that we can create relocations
15700 against them. For normal symbols we output a relocation
15701 against the section that contains them. */
15702 if (! bfd_elf_link_record_dynamic_symbol (info, h))
15703 return FALSE;
15704 }
15705
5e681ec4
PB		 15706 }
15707 else
15708 {
15709 /* For the non-shared case, discard space for relocs against
15710 symbols which turn out to need copy relocs or are not
15711 dynamic. */
15712
f5385ebf
AM		 15713 if (!h->non_got_ref
15714 && ((h->def_dynamic
15715 && !h->def_regular)
5e681ec4
PB		 15716 || (htab->root.dynamic_sections_created
15717 && (h->root.type == bfd_link_hash_undefweak
15718 || h->root.type == bfd_link_hash_undefined))))
15719 {
15720 /* Make sure this symbol is output as a dynamic symbol.
15721 Undefined weak syms won't yet be marked as dynamic. */
15722 if (h->dynindx == -1
f5385ebf 15723 && !h->forced_local)
5e681ec4 15724 {
c152c796 15725 if (! bfd_elf_link_record_dynamic_symbol (info, h))
5e681ec4
PB		 15726 return FALSE;
15727 }
15728
15729 /* If that succeeded, we know we'll be keeping all the
15730 relocs. */
15731 if (h->dynindx != -1)
15732 goto keep;
15733 }
15734
0bdcacaf 15735 eh->dyn_relocs = NULL;
5e681ec4
PB		 15736
15737 keep: ;
15738 }
15739
15740 /* Finally, allocate space. */
0bdcacaf 15741 for (p = eh->dyn_relocs; p != NULL; p = p->next)
5e681ec4 15742 {
0bdcacaf 15743 asection *sreloc = elf_section_data (p->sec)->sreloc;
34e77a92
RS		 15744 if (h->type == STT_GNU_IFUNC
15745 && eh->plt.noncall_refcount == 0
15746 && SYMBOL_REFERENCES_LOCAL (info, h))
15747 elf32_arm_allocate_irelocs (info, sreloc, p->count);
15748 else
15749 elf32_arm_allocate_dynrelocs (info, sreloc, p->count);
5e681ec4
PB		 15750 }
15751
15752 return TRUE;
15753}
15754
08d1f311
DJ		 15755/* Find any dynamic relocs that apply to read-only sections. */
15756
15757static bfd_boolean
8029a119 15758elf32_arm_readonly_dynrelocs (struct elf_link_hash_entry * h, void * inf)
08d1f311 15759{
8029a119 15760 struct elf32_arm_link_hash_entry * eh;
0bdcacaf 15761 struct elf_dyn_relocs * p;
08d1f311 15762
08d1f311 15763 eh = (struct elf32_arm_link_hash_entry *) h;
0bdcacaf 15764 for (p = eh->dyn_relocs; p != NULL; p = p->next)
08d1f311 15765 {
0bdcacaf 15766 asection *s = p->sec;
08d1f311
DJ		 15767
15768 if (s != NULL && (s->flags & SEC_READONLY) != 0)
15769 {
15770 struct bfd_link_info *info = (struct bfd_link_info *) inf;
15771
15772 info->flags |= DF_TEXTREL;
15773
15774 /* Not an error, just cut short the traversal. */
15775 return FALSE;
15776 }
15777 }
15778 return TRUE;
15779}
15780
d504ffc8
DJ		 15781void
15782bfd_elf32_arm_set_byteswap_code (struct bfd_link_info *info,
15783 int byteswap_code)
15784{
15785 struct elf32_arm_link_hash_table *globals;
15786
15787 globals = elf32_arm_hash_table (info);
4dfe6ac6
NC		 15788 if (globals == NULL)
15789 return;
15790
d504ffc8
DJ		 15791 globals->byteswap_code = byteswap_code;
15792}
15793
252b5132
RH		 15794/* Set the sizes of the dynamic sections. */
15795
b34976b6 15796static bfd_boolean
57e8b36a
NC		 15797elf32_arm_size_dynamic_sections (bfd * output_bfd ATTRIBUTE_UNUSED,
15798 struct bfd_link_info * info)
252b5132
RH		 15799{
15800 bfd * dynobj;
15801 asection * s;
b34976b6
AM		 15802 bfd_boolean plt;
15803 bfd_boolean relocs;
5e681ec4
PB		 15804 bfd *ibfd;
15805 struct elf32_arm_link_hash_table *htab;
252b5132 15806
5e681ec4 15807 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 15808 if (htab == NULL)
15809 return FALSE;
15810
252b5132
RH		 15811 dynobj = elf_hash_table (info)->dynobj;
15812 BFD_ASSERT (dynobj != NULL);
39b41c9c 15813 check_use_blx (htab);
252b5132
RH		 15814
15815 if (elf_hash_table (info)->dynamic_sections_created)
15816 {
15817 /* Set the contents of the .interp section to the interpreter. */
9b8b325a 15818 if (bfd_link_executable (info) && !info->nointerp)
252b5132 15819 {
3d4d4302 15820 s = bfd_get_linker_section (dynobj, ".interp");
252b5132 15821 BFD_ASSERT (s != NULL);
eea6121a 15822 s->size = sizeof ELF_DYNAMIC_INTERPRETER;
252b5132
RH		 15823 s->contents = (unsigned char *) ELF_DYNAMIC_INTERPRETER;
15824 }
15825 }
5e681ec4
PB		 15826
15827 /* Set up .got offsets for local syms, and space for local dynamic
15828 relocs. */
c72f2fb2 15829 for (ibfd = info->input_bfds; ibfd != NULL; ibfd = ibfd->link.next)
252b5132 15830 {
5e681ec4
PB		 15831 bfd_signed_vma *local_got;
15832 bfd_signed_vma *end_local_got;
34e77a92 15833 struct arm_local_iplt_info **local_iplt_ptr, *local_iplt;
5e681ec4 15834 char *local_tls_type;
0855e32b 15835 bfd_vma *local_tlsdesc_gotent;
5e681ec4
PB		 15836 bfd_size_type locsymcount;
15837 Elf_Internal_Shdr *symtab_hdr;
15838 asection *srel;
4dfe6ac6 15839 bfd_boolean is_vxworks = htab->vxworks_p;
34e77a92 15840 unsigned int symndx;
5e681ec4 15841
0ffa91dd 15842 if (! is_arm_elf (ibfd))
5e681ec4
PB		 15843 continue;
15844
15845 for (s = ibfd->sections; s != NULL; s = s->next)
15846 {
0bdcacaf 15847 struct elf_dyn_relocs *p;
5e681ec4 15848
0bdcacaf 15849 for (p = (struct elf_dyn_relocs *)
99059e56 15850 elf_section_data (s)->local_dynrel; p != NULL; p = p->next)
5e681ec4 15851 {
0bdcacaf
RS		 15852 if (!bfd_is_abs_section (p->sec)
15853 && bfd_is_abs_section (p->sec->output_section))
5e681ec4
PB		 15854 {
15855 /* Input section has been discarded, either because
15856 it is a copy of a linkonce section or due to
15857 linker script /DISCARD/, so we'll be discarding
15858 the relocs too. */
15859 }
3348747a 15860 else if (is_vxworks
0bdcacaf 15861 && strcmp (p->sec->output_section->name,
3348747a
NS		 15862 ".tls_vars") == 0)
15863 {
15864 /* Relocations in vxworks .tls_vars sections are
15865 handled specially by the loader. */
15866 }
5e681ec4
PB		 15867 else if (p->count != 0)
15868 {
0bdcacaf 15869 srel = elf_section_data (p->sec)->sreloc;
47beaa6a 15870 elf32_arm_allocate_dynrelocs (info, srel, p->count);
0bdcacaf 15871 if ((p->sec->output_section->flags & SEC_READONLY) != 0)
5e681ec4
PB		 15872 info->flags |= DF_TEXTREL;
15873 }
15874 }
15875 }
15876
15877 local_got = elf_local_got_refcounts (ibfd);
15878 if (!local_got)
15879 continue;
15880
0ffa91dd 15881 symtab_hdr = & elf_symtab_hdr (ibfd);
5e681ec4
PB		 15882 locsymcount = symtab_hdr->sh_info;
15883 end_local_got = local_got + locsymcount;
34e77a92 15884 local_iplt_ptr = elf32_arm_local_iplt (ibfd);
ba93b8ac 15885 local_tls_type = elf32_arm_local_got_tls_type (ibfd);
0855e32b 15886 local_tlsdesc_gotent = elf32_arm_local_tlsdesc_gotent (ibfd);
34e77a92 15887 symndx = 0;
362d30a1
RS		 15888 s = htab->root.sgot;
15889 srel = htab->root.srelgot;
0855e32b 15890 for (; local_got < end_local_got;
34e77a92
RS		 15891 ++local_got, ++local_iplt_ptr, ++local_tls_type,
15892 ++local_tlsdesc_gotent, ++symndx)
5e681ec4 15893 {
0855e32b 15894 *local_tlsdesc_gotent = (bfd_vma) -1;
34e77a92
RS		 15895 local_iplt = *local_iplt_ptr;
15896 if (local_iplt != NULL)
15897 {
15898 struct elf_dyn_relocs *p;
15899
15900 if (local_iplt->root.refcount > 0)
15901 {
15902 elf32_arm_allocate_plt_entry (info, TRUE,
15903 &local_iplt->root,
15904 &local_iplt->arm);
15905 if (local_iplt->arm.noncall_refcount == 0)
15906 /* All references to the PLT are calls, so all
15907 non-call references can resolve directly to the
15908 run-time target. This means that the .got entry
15909 would be the same as the .igot.plt entry, so there's
15910 no point creating both. */
15911 *local_got = 0;
15912 }
15913 else
15914 {
15915 BFD_ASSERT (local_iplt->arm.noncall_refcount == 0);
15916 local_iplt->root.offset = (bfd_vma) -1;
15917 }
15918
15919 for (p = local_iplt->dyn_relocs; p != NULL; p = p->next)
15920 {
15921 asection *psrel;
15922
15923 psrel = elf_section_data (p->sec)->sreloc;
15924 if (local_iplt->arm.noncall_refcount == 0)
15925 elf32_arm_allocate_irelocs (info, psrel, p->count);
15926 else
15927 elf32_arm_allocate_dynrelocs (info, psrel, p->count);
15928 }
15929 }
5e681ec4
PB		 15930 if (*local_got > 0)
15931 {
34e77a92
RS		 15932 Elf_Internal_Sym *isym;
15933
eea6121a 15934 *local_got = s->size;
ba93b8ac
DJ		 15935 if (*local_tls_type & GOT_TLS_GD)
15936 /* TLS_GD relocs need an 8-byte structure in the GOT. */
15937 s->size += 8;
0855e32b
NS		 15938 if (*local_tls_type & GOT_TLS_GDESC)
15939 {
15940 *local_tlsdesc_gotent = htab->root.sgotplt->size
15941 - elf32_arm_compute_jump_table_size (htab);
15942 htab->root.sgotplt->size += 8;
15943 *local_got = (bfd_vma) -2;
34e77a92 15944 /* plt.got_offset needs to know there's a TLS_DESC
0855e32b 15945 reloc in the middle of .got.plt. */
99059e56 15946 htab->num_tls_desc++;
0855e32b 15947 }
ba93b8ac
DJ		 15948 if (*local_tls_type & GOT_TLS_IE)
15949 s->size += 4;
ba93b8ac 15950
0855e32b
NS		 15951 if (*local_tls_type & GOT_NORMAL)
15952 {
15953 /* If the symbol is both GD and GDESC, *local_got
15954 may have been overwritten. */
15955 *local_got = s->size;
15956 s->size += 4;
15957 }
15958
34e77a92
RS		 15959 isym = bfd_sym_from_r_symndx (&htab->sym_cache, ibfd, symndx);
15960 if (isym == NULL)
15961 return FALSE;
15962
15963 /* If all references to an STT_GNU_IFUNC PLT are calls,
15964 then all non-call references, including this GOT entry,
15965 resolve directly to the run-time target. */
15966 if (ELF32_ST_TYPE (isym->st_info) == STT_GNU_IFUNC
15967 && (local_iplt == NULL
15968 || local_iplt->arm.noncall_refcount == 0))
15969 elf32_arm_allocate_irelocs (info, srel, 1);
0e1862bb 15970 else if (bfd_link_pic (info) || output_bfd->flags & DYNAMIC)
0855e32b 15971 {
0e1862bb 15972 if ((bfd_link_pic (info) && !(*local_tls_type & GOT_TLS_GDESC))
3064e1ff
JB		 15973 || *local_tls_type & GOT_TLS_GD)
15974 elf32_arm_allocate_dynrelocs (info, srel, 1);
99059e56 15975
0e1862bb 15976 if (bfd_link_pic (info) && *local_tls_type & GOT_TLS_GDESC)
3064e1ff
JB		 15977 {
15978 elf32_arm_allocate_dynrelocs (info,
15979 htab->root.srelplt, 1);
15980 htab->tls_trampoline = -1;
15981 }
0855e32b 15982 }
5e681ec4
PB		 15983 }
15984 else
15985 *local_got = (bfd_vma) -1;
15986 }
252b5132
RH		 15987 }
15988
ba93b8ac
DJ		 15989 if (htab->tls_ldm_got.refcount > 0)
15990 {
15991 /* Allocate two GOT entries and one dynamic relocation (if necessary)
15992 for R_ARM_TLS_LDM32 relocations. */
362d30a1
RS		 15993 htab->tls_ldm_got.offset = htab->root.sgot->size;
15994 htab->root.sgot->size += 8;
0e1862bb 15995 if (bfd_link_pic (info))
47beaa6a 15996 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
ba93b8ac
DJ		 15997 }
15998 else
15999 htab->tls_ldm_got.offset = -1;
16000
5e681ec4
PB		 16001 /* Allocate global sym .plt and .got entries, and space for global
16002 sym dynamic relocs. */
47beaa6a 16003 elf_link_hash_traverse (& htab->root, allocate_dynrelocs_for_symbol, info);
252b5132 16004
d504ffc8 16005 /* Here we rummage through the found bfds to collect glue information. */
c72f2fb2 16006 for (ibfd = info->input_bfds; ibfd != NULL; ibfd = ibfd->link.next)
c7b8f16e 16007 {
0ffa91dd 16008 if (! is_arm_elf (ibfd))
e44a2c9c
AM		 16009 continue;
16010
c7b8f16e
JB		 16011 /* Initialise mapping tables for code/data. */
16012 bfd_elf32_arm_init_maps (ibfd);
906e58ca 16013
c7b8f16e 16014 if (!bfd_elf32_arm_process_before_allocation (ibfd, info)
a504d23a
LA		 16015 || !bfd_elf32_arm_vfp11_erratum_scan (ibfd, info)
16016 || !bfd_elf32_arm_stm32l4xx_erratum_scan (ibfd, info))
99059e56
RM		 16017 /* xgettext:c-format */
16018 _bfd_error_handler (_("Errors encountered processing file %s"),
c7b8f16e
JB		 16019 ibfd->filename);
16020 }
d504ffc8 16021
3e6b1042
DJ		 16022 /* Allocate space for the glue sections now that we've sized them. */
16023 bfd_elf32_arm_allocate_interworking_sections (info);
16024
0855e32b
NS		 16025 /* For every jump slot reserved in the sgotplt, reloc_count is
16026 incremented. However, when we reserve space for TLS descriptors,
16027 it's not incremented, so in order to compute the space reserved
16028 for them, it suffices to multiply the reloc count by the jump
16029 slot size. */
16030 if (htab->root.srelplt)
16031 htab->sgotplt_jump_table_size = elf32_arm_compute_jump_table_size(htab);
16032
16033 if (htab->tls_trampoline)
16034 {
16035 if (htab->root.splt->size == 0)
16036 htab->root.splt->size += htab->plt_header_size;
b38cadfb 16037
0855e32b
NS		 16038 htab->tls_trampoline = htab->root.splt->size;
16039 htab->root.splt->size += htab->plt_entry_size;
b38cadfb 16040
0855e32b 16041 /* If we're not using lazy TLS relocations, don't generate the
99059e56 16042 PLT and GOT entries they require. */
0855e32b
NS		 16043 if (!(info->flags & DF_BIND_NOW))
16044 {
16045 htab->dt_tlsdesc_got = htab->root.sgot->size;
16046 htab->root.sgot->size += 4;
16047
16048 htab->dt_tlsdesc_plt = htab->root.splt->size;
16049 htab->root.splt->size += 4 * ARRAY_SIZE (dl_tlsdesc_lazy_trampoline);
16050 }
16051 }
16052
252b5132
RH		 16053 /* The check_relocs and adjust_dynamic_symbol entry points have
16054 determined the sizes of the various dynamic sections. Allocate
16055 memory for them. */
b34976b6
AM		 16056 plt = FALSE;
16057 relocs = FALSE;
252b5132
RH		 16058 for (s = dynobj->sections; s != NULL; s = s->next)
16059 {
16060 const char * name;
252b5132
RH		 16061
16062 if ((s->flags & SEC_LINKER_CREATED) == 0)
16063 continue;
16064
16065 /* It's OK to base decisions on the section name, because none
16066 of the dynobj section names depend upon the input files. */
16067 name = bfd_get_section_name (dynobj, s);
16068
34e77a92 16069 if (s == htab->root.splt)
252b5132 16070 {
c456f082
AM		 16071 /* Remember whether there is a PLT. */
16072 plt = s->size != 0;
252b5132 16073 }
0112cd26 16074 else if (CONST_STRNEQ (name, ".rel"))
252b5132 16075 {
c456f082 16076 if (s->size != 0)
252b5132 16077 {
252b5132 16078 /* Remember whether there are any reloc sections other
00a97672 16079 than .rel(a).plt and .rela.plt.unloaded. */
362d30a1 16080 if (s != htab->root.srelplt && s != htab->srelplt2)
b34976b6 16081 relocs = TRUE;
252b5132
RH		 16082
16083 /* We use the reloc_count field as a counter if we need
16084 to copy relocs into the output file. */
16085 s->reloc_count = 0;
16086 }
16087 }
34e77a92
RS		 16088 else if (s != htab->root.sgot
16089 && s != htab->root.sgotplt
16090 && s != htab->root.iplt
16091 && s != htab->root.igotplt
16092 && s != htab->sdynbss)
252b5132
RH		 16093 {
16094 /* It's not one of our sections, so don't allocate space. */
16095 continue;
16096 }
16097
c456f082 16098 if (s->size == 0)
252b5132 16099 {
c456f082 16100 /* If we don't need this section, strip it from the
00a97672
RS		 16101 output file. This is mostly to handle .rel(a).bss and
16102 .rel(a).plt. We must create both sections in
c456f082
AM		 16103 create_dynamic_sections, because they must be created
16104 before the linker maps input sections to output
16105 sections. The linker does that before
16106 adjust_dynamic_symbol is called, and it is that
16107 function which decides whether anything needs to go
16108 into these sections. */
8423293d 16109 s->flags |= SEC_EXCLUDE;
252b5132
RH		 16110 continue;
16111 }
16112
c456f082
AM		 16113 if ((s->flags & SEC_HAS_CONTENTS) == 0)
16114 continue;
16115
252b5132 16116 /* Allocate memory for the section contents. */
21d799b5 16117 s->contents = (unsigned char *) bfd_zalloc (dynobj, s->size);
c456f082 16118 if (s->contents == NULL)
b34976b6 16119 return FALSE;
252b5132
RH		 16120 }
16121
16122 if (elf_hash_table (info)->dynamic_sections_created)
16123 {
16124 /* Add some entries to the .dynamic section. We fill in the
16125 values later, in elf32_arm_finish_dynamic_sections, but we
16126 must add the entries now so that we get the correct size for
16127 the .dynamic section. The DT_DEBUG entry is filled in by the
16128 dynamic linker and used by the debugger. */
dc810e39 16129#define add_dynamic_entry(TAG, VAL) \
5a580b3a 16130 _bfd_elf_add_dynamic_entry (info, TAG, VAL)
dc810e39 16131
0e1862bb 16132 if (bfd_link_executable (info))
252b5132 16133 {
dc810e39 16134 if (!add_dynamic_entry (DT_DEBUG, 0))
b34976b6 16135 return FALSE;
252b5132
RH		 16136 }
16137
16138 if (plt)
16139 {
dc810e39
AM		 16140 if ( !add_dynamic_entry (DT_PLTGOT, 0)
16141 || !add_dynamic_entry (DT_PLTRELSZ, 0)
00a97672
RS		 16142 || !add_dynamic_entry (DT_PLTREL,
16143 htab->use_rel ? DT_REL : DT_RELA)
dc810e39 16144 || !add_dynamic_entry (DT_JMPREL, 0))
b34976b6 16145 return FALSE;
0855e32b 16146
5025eb7c
AO		 16147 if (htab->dt_tlsdesc_plt
16148 && (!add_dynamic_entry (DT_TLSDESC_PLT,0)
16149 || !add_dynamic_entry (DT_TLSDESC_GOT,0)))
b38cadfb 16150 return FALSE;
252b5132
RH		 16151 }
16152
16153 if (relocs)
16154 {
00a97672
RS		 16155 if (htab->use_rel)
16156 {
16157 if (!add_dynamic_entry (DT_REL, 0)
16158 || !add_dynamic_entry (DT_RELSZ, 0)
16159 || !add_dynamic_entry (DT_RELENT, RELOC_SIZE (htab)))
16160 return FALSE;
16161 }
16162 else
16163 {
16164 if (!add_dynamic_entry (DT_RELA, 0)
16165 || !add_dynamic_entry (DT_RELASZ, 0)
16166 || !add_dynamic_entry (DT_RELAENT, RELOC_SIZE (htab)))
16167 return FALSE;
16168 }
252b5132
RH		 16169 }
16170
08d1f311
DJ		 16171 /* If any dynamic relocs apply to a read-only section,
16172 then we need a DT_TEXTREL entry. */
16173 if ((info->flags & DF_TEXTREL) == 0)
8029a119
NC		 16174 elf_link_hash_traverse (& htab->root, elf32_arm_readonly_dynrelocs,
16175 info);
08d1f311 16176
99e4ae17 16177 if ((info->flags & DF_TEXTREL) != 0)
252b5132 16178 {
dc810e39 16179 if (!add_dynamic_entry (DT_TEXTREL, 0))
b34976b6 16180 return FALSE;
252b5132 16181 }
7a2b07ff
NS		 16182 if (htab->vxworks_p
16183 && !elf_vxworks_add_dynamic_entries (output_bfd, info))
16184 return FALSE;
252b5132 16185 }
8532796c 16186#undef add_dynamic_entry
252b5132 16187
b34976b6 16188 return TRUE;
252b5132
RH		 16189}
16190
0855e32b
NS		 16191/* Size sections even though they're not dynamic. We use it to setup
16192 _TLS_MODULE_BASE_, if needed. */
16193
16194static bfd_boolean
16195elf32_arm_always_size_sections (bfd *output_bfd,
99059e56 16196 struct bfd_link_info *info)
0855e32b
NS		 16197{
16198 asection *tls_sec;
16199
0e1862bb 16200 if (bfd_link_relocatable (info))
0855e32b
NS		 16201 return TRUE;
16202
16203 tls_sec = elf_hash_table (info)->tls_sec;
16204
16205 if (tls_sec)
16206 {
16207 struct elf_link_hash_entry *tlsbase;
16208
16209 tlsbase = elf_link_hash_lookup
16210 (elf_hash_table (info), "_TLS_MODULE_BASE_", TRUE, TRUE, FALSE);
16211
16212 if (tlsbase)
99059e56
RM		 16213 {
16214 struct bfd_link_hash_entry *bh = NULL;
0855e32b 16215 const struct elf_backend_data *bed
99059e56 16216 = get_elf_backend_data (output_bfd);
0855e32b 16217
99059e56 16218 if (!(_bfd_generic_link_add_one_symbol
0855e32b
NS		 16219 (info, output_bfd, "_TLS_MODULE_BASE_", BSF_LOCAL,
16220 tls_sec, 0, NULL, FALSE,
16221 bed->collect, &bh)))
16222 return FALSE;
b38cadfb 16223
99059e56
RM		 16224 tlsbase->type = STT_TLS;
16225 tlsbase = (struct elf_link_hash_entry *)bh;
16226 tlsbase->def_regular = 1;
16227 tlsbase->other = STV_HIDDEN;
16228 (*bed->elf_backend_hide_symbol) (info, tlsbase, TRUE);
0855e32b
NS		 16229 }
16230 }
16231 return TRUE;
16232}
16233
252b5132
RH		 16234/* Finish up dynamic symbol handling. We set the contents of various
16235 dynamic sections here. */
16236
b34976b6 16237static bfd_boolean
906e58ca
NC		 16238elf32_arm_finish_dynamic_symbol (bfd * output_bfd,
16239 struct bfd_link_info * info,
16240 struct elf_link_hash_entry * h,
16241 Elf_Internal_Sym * sym)
252b5132 16242{
e5a52504 16243 struct elf32_arm_link_hash_table *htab;
b7693d02 16244 struct elf32_arm_link_hash_entry *eh;
252b5132 16245
e5a52504 16246 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 16247 if (htab == NULL)
16248 return FALSE;
16249
b7693d02 16250 eh = (struct elf32_arm_link_hash_entry *) h;
252b5132
RH		 16251
16252 if (h->plt.offset != (bfd_vma) -1)
16253 {
34e77a92 16254 if (!eh->is_iplt)
e5a52504 16255 {
34e77a92 16256 BFD_ASSERT (h->dynindx != -1);
57460bcf
NC		 16257 if (! elf32_arm_populate_plt_entry (output_bfd, info, &h->plt, &eh->plt,
16258 h->dynindx, 0))
16259 return FALSE;
e5a52504 16260 }
57e8b36a 16261
f5385ebf 16262 if (!h->def_regular)
252b5132
RH		 16263 {
16264 /* Mark the symbol as undefined, rather than as defined in
3a635617 16265 the .plt section. */
252b5132 16266 sym->st_shndx = SHN_UNDEF;
3a635617 16267 /* If the symbol is weak we need to clear the value.
d982ba73
PB		 16268 Otherwise, the PLT entry would provide a definition for
16269 the symbol even if the symbol wasn't defined anywhere,
3a635617
WN		 16270 and so the symbol would never be NULL. Leave the value if
16271 there were any relocations where pointer equality matters
16272 (this is a clue for the dynamic linker, to make function
16273 pointer comparisons work between an application and shared
16274 library). */
97323ad1 16275 if (!h->ref_regular_nonweak || !h->pointer_equality_needed)
d982ba73 16276 sym->st_value = 0;
252b5132 16277 }
34e77a92
RS		 16278 else if (eh->is_iplt && eh->plt.noncall_refcount != 0)
16279 {
16280 /* At least one non-call relocation references this .iplt entry,
16281 so the .iplt entry is the function's canonical address. */
16282 sym->st_info = ELF_ST_INFO (ELF_ST_BIND (sym->st_info), STT_FUNC);
39d911fc 16283 ARM_SET_SYM_BRANCH_TYPE (sym->st_target_internal, ST_BRANCH_TO_ARM);
34e77a92
RS		 16284 sym->st_shndx = (_bfd_elf_section_from_bfd_section
16285 (output_bfd, htab->root.iplt->output_section));
16286 sym->st_value = (h->plt.offset
16287 + htab->root.iplt->output_section->vma
16288 + htab->root.iplt->output_offset);
16289 }
252b5132
RH		 16290 }
16291
f5385ebf 16292 if (h->needs_copy)
252b5132
RH		 16293 {
16294 asection * s;
947216bf 16295 Elf_Internal_Rela rel;
252b5132
RH		 16296
16297 /* This symbol needs a copy reloc. Set it up. */
252b5132
RH		 16298 BFD_ASSERT (h->dynindx != -1
16299 && (h->root.type == bfd_link_hash_defined
16300 || h->root.type == bfd_link_hash_defweak));
16301
362d30a1 16302 s = htab->srelbss;
252b5132
RH		 16303 BFD_ASSERT (s != NULL);
16304
00a97672 16305 rel.r_addend = 0;
252b5132
RH		 16306 rel.r_offset = (h->root.u.def.value
16307 + h->root.u.def.section->output_section->vma
16308 + h->root.u.def.section->output_offset);
16309 rel.r_info = ELF32_R_INFO (h->dynindx, R_ARM_COPY);
47beaa6a 16310 elf32_arm_add_dynreloc (output_bfd, info, s, &rel);
252b5132
RH		 16311 }
16312
00a97672
RS		 16313 /* Mark _DYNAMIC and _GLOBAL_OFFSET_TABLE_ as absolute. On VxWorks,
16314 the _GLOBAL_OFFSET_TABLE_ symbol is not absolute: it is relative
16315 to the ".got" section. */
9637f6ef 16316 if (h == htab->root.hdynamic
00a97672 16317 || (!htab->vxworks_p && h == htab->root.hgot))
252b5132
RH		 16318 sym->st_shndx = SHN_ABS;
16319
b34976b6 16320 return TRUE;
252b5132
RH		 16321}
16322
0855e32b
NS		 16323static void
16324arm_put_trampoline (struct elf32_arm_link_hash_table *htab, bfd *output_bfd,
16325 void *contents,
16326 const unsigned long *template, unsigned count)
16327{
16328 unsigned ix;
b38cadfb 16329
0855e32b
NS		 16330 for (ix = 0; ix != count; ix++)
16331 {
16332 unsigned long insn = template[ix];
16333
16334 /* Emit mov pc,rx if bx is not permitted. */
16335 if (htab->fix_v4bx == 1 && (insn & 0x0ffffff0) == 0x012fff10)
16336 insn = (insn & 0xf000000f) | 0x01a0f000;
16337 put_arm_insn (htab, output_bfd, insn, (char *)contents + ix*4);
16338 }
16339}
16340
99059e56
RM		 16341/* Install the special first PLT entry for elf32-arm-nacl. Unlike
16342 other variants, NaCl needs this entry in a static executable's
16343 .iplt too. When we're handling that case, GOT_DISPLACEMENT is
16344 zero. For .iplt really only the last bundle is useful, and .iplt
16345 could have a shorter first entry, with each individual PLT entry's
16346 relative branch calculated differently so it targets the last
16347 bundle instead of the instruction before it (labelled .Lplt_tail
16348 above). But it's simpler to keep the size and layout of PLT0
16349 consistent with the dynamic case, at the cost of some dead code at
16350 the start of .iplt and the one dead store to the stack at the start
16351 of .Lplt_tail. */
16352static void
16353arm_nacl_put_plt0 (struct elf32_arm_link_hash_table *htab, bfd *output_bfd,
16354 asection *plt, bfd_vma got_displacement)
16355{
16356 unsigned int i;
16357
16358 put_arm_insn (htab, output_bfd,
16359 elf32_arm_nacl_plt0_entry[0]
16360 | arm_movw_immediate (got_displacement),
16361 plt->contents + 0);
16362 put_arm_insn (htab, output_bfd,
16363 elf32_arm_nacl_plt0_entry[1]
16364 | arm_movt_immediate (got_displacement),
16365 plt->contents + 4);
16366
16367 for (i = 2; i < ARRAY_SIZE (elf32_arm_nacl_plt0_entry); ++i)
16368 put_arm_insn (htab, output_bfd,
16369 elf32_arm_nacl_plt0_entry[i],
16370 plt->contents + (i * 4));
16371}
16372
252b5132
RH		 16373/* Finish up the dynamic sections. */
16374
b34976b6 16375static bfd_boolean
57e8b36a 16376elf32_arm_finish_dynamic_sections (bfd * output_bfd, struct bfd_link_info * info)
252b5132
RH		 16377{
16378 bfd * dynobj;
16379 asection * sgot;
16380 asection * sdyn;
4dfe6ac6
NC		 16381 struct elf32_arm_link_hash_table *htab;
16382
16383 htab = elf32_arm_hash_table (info);
16384 if (htab == NULL)
16385 return FALSE;
252b5132
RH		 16386
16387 dynobj = elf_hash_table (info)->dynobj;
16388
362d30a1 16389 sgot = htab->root.sgotplt;
894891db
NC		 16390 /* A broken linker script might have discarded the dynamic sections.
16391 Catch this here so that we do not seg-fault later on. */
16392 if (sgot != NULL && bfd_is_abs_section (sgot->output_section))
16393 return FALSE;
3d4d4302 16394 sdyn = bfd_get_linker_section (dynobj, ".dynamic");
252b5132
RH		 16395
16396 if (elf_hash_table (info)->dynamic_sections_created)
16397 {
16398 asection *splt;
16399 Elf32_External_Dyn *dyncon, *dynconend;
16400
362d30a1 16401 splt = htab->root.splt;
24a1ba0f 16402 BFD_ASSERT (splt != NULL && sdyn != NULL);
cbc704f3 16403 BFD_ASSERT (htab->symbian_p || sgot != NULL);
252b5132
RH		 16404
16405 dyncon = (Elf32_External_Dyn *) sdyn->contents;
eea6121a 16406 dynconend = (Elf32_External_Dyn *) (sdyn->contents + sdyn->size);
9b485d32 16407
252b5132
RH		 16408 for (; dyncon < dynconend; dyncon++)
16409 {
16410 Elf_Internal_Dyn dyn;
16411 const char * name;
16412 asection * s;
16413
16414 bfd_elf32_swap_dyn_in (dynobj, dyncon, &dyn);
16415
16416 switch (dyn.d_tag)
16417 {
229fcec5
MM		 16418 unsigned int type;
16419
252b5132 16420 default:
7a2b07ff
NS		 16421 if (htab->vxworks_p
16422 && elf_vxworks_finish_dynamic_entry (output_bfd, &dyn))
16423 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
252b5132
RH		 16424 break;
16425
229fcec5
MM		 16426 case DT_HASH:
16427 name = ".hash";
16428 goto get_vma_if_bpabi;
16429 case DT_STRTAB:
16430 name = ".dynstr";
16431 goto get_vma_if_bpabi;
16432 case DT_SYMTAB:
16433 name = ".dynsym";
16434 goto get_vma_if_bpabi;
c0042f5d
MM		 16435 case DT_VERSYM:
16436 name = ".gnu.version";
16437 goto get_vma_if_bpabi;
16438 case DT_VERDEF:
16439 name = ".gnu.version_d";
16440 goto get_vma_if_bpabi;
16441 case DT_VERNEED:
16442 name = ".gnu.version_r";
16443 goto get_vma_if_bpabi;
16444
252b5132 16445 case DT_PLTGOT:
4ade44b7 16446 name = htab->symbian_p ? ".got" : ".got.plt";
252b5132
RH		 16447 goto get_vma;
16448 case DT_JMPREL:
00a97672 16449 name = RELOC_SECTION (htab, ".plt");
252b5132 16450 get_vma:
4ade44b7 16451 s = bfd_get_linker_section (dynobj, name);
05456594
NC		 16452 if (s == NULL)
16453 {
4eca0228 16454 _bfd_error_handler
4ade44b7 16455 (_("could not find section %s"), name);
05456594
NC		 16456 bfd_set_error (bfd_error_invalid_operation);
16457 return FALSE;
16458 }
229fcec5 16459 if (!htab->symbian_p)
4ade44b7 16460 dyn.d_un.d_ptr = s->output_section->vma + s->output_offset;
229fcec5
MM		 16461 else
16462 /* In the BPABI, tags in the PT_DYNAMIC section point
16463 at the file offset, not the memory address, for the
16464 convenience of the post linker. */
4ade44b7 16465 dyn.d_un.d_ptr = s->output_section->filepos + s->output_offset;
252b5132
RH		 16466 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
16467 break;
16468
229fcec5
MM		 16469 get_vma_if_bpabi:
16470 if (htab->symbian_p)
16471 goto get_vma;
16472 break;
16473
252b5132 16474 case DT_PLTRELSZ:
362d30a1 16475 s = htab->root.srelplt;
252b5132 16476 BFD_ASSERT (s != NULL);
eea6121a 16477 dyn.d_un.d_val = s->size;
252b5132
RH		 16478 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
16479 break;
906e58ca 16480
252b5132 16481 case DT_RELSZ:
00a97672 16482 case DT_RELASZ:
229fcec5
MM		 16483 if (!htab->symbian_p)
16484 {
16485 /* My reading of the SVR4 ABI indicates that the
16486 procedure linkage table relocs (DT_JMPREL) should be
16487 included in the overall relocs (DT_REL). This is
16488 what Solaris does. However, UnixWare can not handle
16489 that case. Therefore, we override the DT_RELSZ entry
16490 here to make it not include the JMPREL relocs. Since
00a97672 16491 the linker script arranges for .rel(a).plt to follow all
229fcec5
MM		 16492 other relocation sections, we don't have to worry
16493 about changing the DT_REL entry. */
362d30a1 16494 s = htab->root.srelplt;
229fcec5
MM		 16495 if (s != NULL)
16496 dyn.d_un.d_val -= s->size;
16497 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
16498 break;
16499 }
8029a119 16500 /* Fall through. */
229fcec5
MM		 16501
16502 case DT_REL:
16503 case DT_RELA:
229fcec5
MM		 16504 /* In the BPABI, the DT_REL tag must point at the file
16505 offset, not the VMA, of the first relocation
16506 section. So, we use code similar to that in
16507 elflink.c, but do not check for SHF_ALLOC on the
16508 relcoation section, since relocations sections are
16509 never allocated under the BPABI. The comments above
16510 about Unixware notwithstanding, we include all of the
16511 relocations here. */
16512 if (htab->symbian_p)
16513 {
16514 unsigned int i;
16515 type = ((dyn.d_tag == DT_REL || dyn.d_tag == DT_RELSZ)
16516 ? SHT_REL : SHT_RELA);
16517 dyn.d_un.d_val = 0;
16518 for (i = 1; i < elf_numsections (output_bfd); i++)
16519 {
906e58ca 16520 Elf_Internal_Shdr *hdr
229fcec5
MM		 16521 = elf_elfsections (output_bfd)[i];
16522 if (hdr->sh_type == type)
16523 {
906e58ca 16524 if (dyn.d_tag == DT_RELSZ
229fcec5
MM		 16525 || dyn.d_tag == DT_RELASZ)
16526 dyn.d_un.d_val += hdr->sh_size;
de52dba4
AM		 16527 else if ((ufile_ptr) hdr->sh_offset
16528 <= dyn.d_un.d_val - 1)
229fcec5
MM		 16529 dyn.d_un.d_val = hdr->sh_offset;
16530 }
16531 }
16532 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
16533 }
252b5132 16534 break;
88f7bcd5 16535
0855e32b 16536 case DT_TLSDESC_PLT:
99059e56 16537 s = htab->root.splt;
0855e32b
NS		 16538 dyn.d_un.d_ptr = (s->output_section->vma + s->output_offset
16539 + htab->dt_tlsdesc_plt);
16540 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
16541 break;
16542
16543 case DT_TLSDESC_GOT:
99059e56 16544 s = htab->root.sgot;
0855e32b 16545 dyn.d_un.d_ptr = (s->output_section->vma + s->output_offset
99059e56 16546 + htab->dt_tlsdesc_got);
0855e32b
NS		 16547 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
16548 break;
16549
88f7bcd5
NC		 16550 /* Set the bottom bit of DT_INIT/FINI if the
16551 corresponding function is Thumb. */
16552 case DT_INIT:
16553 name = info->init_function;
16554 goto get_sym;
16555 case DT_FINI:
16556 name = info->fini_function;
16557 get_sym:
16558 /* If it wasn't set by elf_bfd_final_link
4cc11e76 16559 then there is nothing to adjust. */
88f7bcd5
NC		 16560 if (dyn.d_un.d_val != 0)
16561 {
16562 struct elf_link_hash_entry * eh;
16563
16564 eh = elf_link_hash_lookup (elf_hash_table (info), name,
b34976b6 16565 FALSE, FALSE, TRUE);
39d911fc
TP		 16566 if (eh != NULL
16567 && ARM_GET_SYM_BRANCH_TYPE (eh->target_internal)
16568 == ST_BRANCH_TO_THUMB)
88f7bcd5
NC		 16569 {
16570 dyn.d_un.d_val |= 1;
b34976b6 16571 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
88f7bcd5
NC		 16572 }
16573 }
16574 break;
252b5132
RH		 16575 }
16576 }
16577
24a1ba0f 16578 /* Fill in the first entry in the procedure linkage table. */
4dfe6ac6 16579 if (splt->size > 0 && htab->plt_header_size)
f7a74f8c 16580 {
00a97672
RS		 16581 const bfd_vma *plt0_entry;
16582 bfd_vma got_address, plt_address, got_displacement;
16583
16584 /* Calculate the addresses of the GOT and PLT. */
16585 got_address = sgot->output_section->vma + sgot->output_offset;
16586 plt_address = splt->output_section->vma + splt->output_offset;
16587
16588 if (htab->vxworks_p)
16589 {
16590 /* The VxWorks GOT is relocated by the dynamic linker.
16591 Therefore, we must emit relocations rather than simply
16592 computing the values now. */
16593 Elf_Internal_Rela rel;
16594
16595 plt0_entry = elf32_arm_vxworks_exec_plt0_entry;
52ab56c2
PB		 16596 put_arm_insn (htab, output_bfd, plt0_entry[0],
16597 splt->contents + 0);
16598 put_arm_insn (htab, output_bfd, plt0_entry[1],
16599 splt->contents + 4);
16600 put_arm_insn (htab, output_bfd, plt0_entry[2],
16601 splt->contents + 8);
00a97672
RS		 16602 bfd_put_32 (output_bfd, got_address, splt->contents + 12);
16603
8029a119 16604 /* Generate a relocation for _GLOBAL_OFFSET_TABLE_. */
00a97672
RS		 16605 rel.r_offset = plt_address + 12;
16606 rel.r_info = ELF32_R_INFO (htab->root.hgot->indx, R_ARM_ABS32);
16607 rel.r_addend = 0;
16608 SWAP_RELOC_OUT (htab) (output_bfd, &rel,
16609 htab->srelplt2->contents);
16610 }
b38cadfb 16611 else if (htab->nacl_p)
99059e56
RM		 16612 arm_nacl_put_plt0 (htab, output_bfd, splt,
16613 got_address + 8 - (plt_address + 16));
eed94f8f
NC		 16614 else if (using_thumb_only (htab))
16615 {
16616 got_displacement = got_address - (plt_address + 12);
16617
16618 plt0_entry = elf32_thumb2_plt0_entry;
16619 put_arm_insn (htab, output_bfd, plt0_entry[0],
16620 splt->contents + 0);
16621 put_arm_insn (htab, output_bfd, plt0_entry[1],
16622 splt->contents + 4);
16623 put_arm_insn (htab, output_bfd, plt0_entry[2],
16624 splt->contents + 8);
16625
16626 bfd_put_32 (output_bfd, got_displacement, splt->contents + 12);
16627 }
00a97672
RS		 16628 else
16629 {
16630 got_displacement = got_address - (plt_address + 16);
16631
16632 plt0_entry = elf32_arm_plt0_entry;
52ab56c2
PB		 16633 put_arm_insn (htab, output_bfd, plt0_entry[0],
16634 splt->contents + 0);
16635 put_arm_insn (htab, output_bfd, plt0_entry[1],
16636 splt->contents + 4);
16637 put_arm_insn (htab, output_bfd, plt0_entry[2],
16638 splt->contents + 8);
16639 put_arm_insn (htab, output_bfd, plt0_entry[3],
16640 splt->contents + 12);
5e681ec4 16641
5e681ec4 16642#ifdef FOUR_WORD_PLT
00a97672
RS		 16643 /* The displacement value goes in the otherwise-unused
16644 last word of the second entry. */
16645 bfd_put_32 (output_bfd, got_displacement, splt->contents + 28);
5e681ec4 16646#else
00a97672 16647 bfd_put_32 (output_bfd, got_displacement, splt->contents + 16);
5e681ec4 16648#endif
00a97672 16649 }
f7a74f8c 16650 }
252b5132
RH		 16651
16652 /* UnixWare sets the entsize of .plt to 4, although that doesn't
16653 really seem like the right value. */
74541ad4
AM		 16654 if (splt->output_section->owner == output_bfd)
16655 elf_section_data (splt->output_section)->this_hdr.sh_entsize = 4;
00a97672 16656
0855e32b
NS		 16657 if (htab->dt_tlsdesc_plt)
16658 {
16659 bfd_vma got_address
16660 = sgot->output_section->vma + sgot->output_offset;
16661 bfd_vma gotplt_address = (htab->root.sgot->output_section->vma
16662 + htab->root.sgot->output_offset);
16663 bfd_vma plt_address
16664 = splt->output_section->vma + splt->output_offset;
16665
b38cadfb 16666 arm_put_trampoline (htab, output_bfd,
0855e32b
NS		 16667 splt->contents + htab->dt_tlsdesc_plt,
16668 dl_tlsdesc_lazy_trampoline, 6);
16669
16670 bfd_put_32 (output_bfd,
16671 gotplt_address + htab->dt_tlsdesc_got
16672 - (plt_address + htab->dt_tlsdesc_plt)
16673 - dl_tlsdesc_lazy_trampoline[6],
16674 splt->contents + htab->dt_tlsdesc_plt + 24);
16675 bfd_put_32 (output_bfd,
16676 got_address - (plt_address + htab->dt_tlsdesc_plt)
16677 - dl_tlsdesc_lazy_trampoline[7],
16678 splt->contents + htab->dt_tlsdesc_plt + 24 + 4);
16679 }
16680
16681 if (htab->tls_trampoline)
16682 {
b38cadfb 16683 arm_put_trampoline (htab, output_bfd,
0855e32b
NS		 16684 splt->contents + htab->tls_trampoline,
16685 tls_trampoline, 3);
16686#ifdef FOUR_WORD_PLT
16687 bfd_put_32 (output_bfd, 0x00000000,
16688 splt->contents + htab->tls_trampoline + 12);
b38cadfb 16689#endif
0855e32b
NS		 16690 }
16691
0e1862bb
L		 16692 if (htab->vxworks_p
16693 && !bfd_link_pic (info)
16694 && htab->root.splt->size > 0)
00a97672
RS		 16695 {
16696 /* Correct the .rel(a).plt.unloaded relocations. They will have
16697 incorrect symbol indexes. */
16698 int num_plts;
eed62c48 16699 unsigned char *p;
00a97672 16700
362d30a1 16701 num_plts = ((htab->root.splt->size - htab->plt_header_size)
00a97672
RS		 16702 / htab->plt_entry_size);
16703 p = htab->srelplt2->contents + RELOC_SIZE (htab);
16704
16705 for (; num_plts; num_plts--)
16706 {
16707 Elf_Internal_Rela rel;
16708
16709 SWAP_RELOC_IN (htab) (output_bfd, p, &rel);
16710 rel.r_info = ELF32_R_INFO (htab->root.hgot->indx, R_ARM_ABS32);
16711 SWAP_RELOC_OUT (htab) (output_bfd, &rel, p);
16712 p += RELOC_SIZE (htab);
16713
16714 SWAP_RELOC_IN (htab) (output_bfd, p, &rel);
16715 rel.r_info = ELF32_R_INFO (htab->root.hplt->indx, R_ARM_ABS32);
16716 SWAP_RELOC_OUT (htab) (output_bfd, &rel, p);
16717 p += RELOC_SIZE (htab);
16718 }
16719 }
252b5132
RH		 16720 }
16721
99059e56
RM		 16722 if (htab->nacl_p && htab->root.iplt != NULL && htab->root.iplt->size > 0)
16723 /* NaCl uses a special first entry in .iplt too. */
16724 arm_nacl_put_plt0 (htab, output_bfd, htab->root.iplt, 0);
16725
252b5132 16726 /* Fill in the first three entries in the global offset table. */
229fcec5 16727 if (sgot)
252b5132 16728 {
229fcec5
MM		 16729 if (sgot->size > 0)
16730 {
16731 if (sdyn == NULL)
16732 bfd_put_32 (output_bfd, (bfd_vma) 0, sgot->contents);
16733 else
16734 bfd_put_32 (output_bfd,
16735 sdyn->output_section->vma + sdyn->output_offset,
16736 sgot->contents);
16737 bfd_put_32 (output_bfd, (bfd_vma) 0, sgot->contents + 4);
16738 bfd_put_32 (output_bfd, (bfd_vma) 0, sgot->contents + 8);
16739 }
252b5132 16740
229fcec5
MM		 16741 elf_section_data (sgot->output_section)->this_hdr.sh_entsize = 4;
16742 }
252b5132 16743
b34976b6 16744 return TRUE;
252b5132
RH		 16745}
16746
ba96a88f 16747static void
57e8b36a 16748elf32_arm_post_process_headers (bfd * abfd, struct bfd_link_info * link_info ATTRIBUTE_UNUSED)
ba96a88f 16749{
9b485d32 16750 Elf_Internal_Ehdr * i_ehdrp; /* ELF file header, internal form. */
e489d0ae 16751 struct elf32_arm_link_hash_table *globals;
ac4c9b04 16752 struct elf_segment_map *m;
ba96a88f
NC		 16753
16754 i_ehdrp = elf_elfheader (abfd);
16755
94a3258f
PB		 16756 if (EF_ARM_EABI_VERSION (i_ehdrp->e_flags) == EF_ARM_EABI_UNKNOWN)
16757 i_ehdrp->e_ident[EI_OSABI] = ELFOSABI_ARM;
16758 else
7394f108 16759 _bfd_elf_post_process_headers (abfd, link_info);
ba96a88f 16760 i_ehdrp->e_ident[EI_ABIVERSION] = ARM_ELF_ABI_VERSION;
e489d0ae 16761
93204d3a
PB		 16762 if (link_info)
16763 {
16764 globals = elf32_arm_hash_table (link_info);
4dfe6ac6 16765 if (globals != NULL && globals->byteswap_code)
93204d3a
PB		 16766 i_ehdrp->e_flags |= EF_ARM_BE8;
16767 }
3bfcb652
NC		 16768
16769 if (EF_ARM_EABI_VERSION (i_ehdrp->e_flags) == EF_ARM_EABI_VER5
16770 && ((i_ehdrp->e_type == ET_DYN) || (i_ehdrp->e_type == ET_EXEC)))
16771 {
16772 int abi = bfd_elf_get_obj_attr_int (abfd, OBJ_ATTR_PROC, Tag_ABI_VFP_args);
5c294fee 16773 if (abi == AEABI_VFP_args_vfp)
3bfcb652
NC		 16774 i_ehdrp->e_flags |= EF_ARM_ABI_FLOAT_HARD;
16775 else
16776 i_ehdrp->e_flags |= EF_ARM_ABI_FLOAT_SOFT;
16777 }
ac4c9b04
MG		 16778
16779 /* Scan segment to set p_flags attribute if it contains only sections with
f0728ee3 16780 SHF_ARM_PURECODE flag. */
ac4c9b04
MG		 16781 for (m = elf_seg_map (abfd); m != NULL; m = m->next)
16782 {
16783 unsigned int j;
16784
16785 if (m->count == 0)
16786 continue;
16787 for (j = 0; j < m->count; j++)
16788 {
f0728ee3 16789 if (!(elf_section_flags (m->sections[j]) & SHF_ARM_PURECODE))
ac4c9b04
MG		 16790 break;
16791 }
16792 if (j == m->count)
16793 {
16794 m->p_flags = PF_X;
16795 m->p_flags_valid = 1;
16796 }
16797 }
ba96a88f
NC		 16798}
16799
99e4ae17 16800static enum elf_reloc_type_class
7e612e98
AM		 16801elf32_arm_reloc_type_class (const struct bfd_link_info *info ATTRIBUTE_UNUSED,
16802 const asection *rel_sec ATTRIBUTE_UNUSED,
16803 const Elf_Internal_Rela *rela)
99e4ae17 16804{
f51e552e 16805 switch ((int) ELF32_R_TYPE (rela->r_info))
99e4ae17
AJ		 16806 {
16807 case R_ARM_RELATIVE:
16808 return reloc_class_relative;
16809 case R_ARM_JUMP_SLOT:
16810 return reloc_class_plt;
16811 case R_ARM_COPY:
16812 return reloc_class_copy;
109575d7
JW		 16813 case R_ARM_IRELATIVE:
16814 return reloc_class_ifunc;
99e4ae17
AJ		 16815 default:
16816 return reloc_class_normal;
16817 }
16818}
16819
e489d0ae 16820static void
57e8b36a 16821elf32_arm_final_write_processing (bfd *abfd, bfd_boolean linker ATTRIBUTE_UNUSED)
e16bb312 16822{
5a6c6817 16823 bfd_arm_update_notes (abfd, ARM_NOTE_SECTION);
e16bb312
NC		 16824}
16825
40a18ebd
NC		 16826/* Return TRUE if this is an unwinding table entry. */
16827
16828static bfd_boolean
16829is_arm_elf_unwind_section_name (bfd * abfd ATTRIBUTE_UNUSED, const char * name)
16830{
0112cd26
NC		 16831 return (CONST_STRNEQ (name, ELF_STRING_ARM_unwind)
16832 || CONST_STRNEQ (name, ELF_STRING_ARM_unwind_once));
40a18ebd
NC		 16833}
16834
16835
16836/* Set the type and flags for an ARM section. We do this by
16837 the section name, which is a hack, but ought to work. */
16838
16839static bfd_boolean
16840elf32_arm_fake_sections (bfd * abfd, Elf_Internal_Shdr * hdr, asection * sec)
16841{
16842 const char * name;
16843
16844 name = bfd_get_section_name (abfd, sec);
16845
16846 if (is_arm_elf_unwind_section_name (abfd, name))
16847 {
16848 hdr->sh_type = SHT_ARM_EXIDX;
16849 hdr->sh_flags |= SHF_LINK_ORDER;
16850 }
ac4c9b04 16851
f0728ee3
AV		 16852 if (sec->flags & SEC_ELF_PURECODE)
16853 hdr->sh_flags |= SHF_ARM_PURECODE;
ac4c9b04 16854
40a18ebd
NC		 16855 return TRUE;
16856}
16857
6dc132d9
L		 16858/* Handle an ARM specific section when reading an object file. This is
16859 called when bfd_section_from_shdr finds a section with an unknown
16860 type. */
40a18ebd
NC		 16861
16862static bfd_boolean
16863elf32_arm_section_from_shdr (bfd *abfd,
16864 Elf_Internal_Shdr * hdr,
6dc132d9
L		 16865 const char *name,
16866 int shindex)
40a18ebd
NC		 16867{
16868 /* There ought to be a place to keep ELF backend specific flags, but
16869 at the moment there isn't one. We just keep track of the
16870 sections by their name, instead. Fortunately, the ABI gives
16871 names for all the ARM specific sections, so we will probably get
16872 away with this. */
16873 switch (hdr->sh_type)
16874 {
16875 case SHT_ARM_EXIDX:
0951f019
RE		 16876 case SHT_ARM_PREEMPTMAP:
16877 case SHT_ARM_ATTRIBUTES:
40a18ebd
NC		 16878 break;
16879
16880 default:
16881 return FALSE;
16882 }
16883
6dc132d9 16884 if (! _bfd_elf_make_section_from_shdr (abfd, hdr, name, shindex))
40a18ebd
NC		 16885 return FALSE;
16886
16887 return TRUE;
16888}
e489d0ae 16889
44444f50
NC		 16890static _arm_elf_section_data *
16891get_arm_elf_section_data (asection * sec)
16892{
47b2e99c
JZ		 16893 if (sec && sec->owner && is_arm_elf (sec->owner))
16894 return elf32_arm_section_data (sec);
44444f50
NC		 16895 else
16896 return NULL;
8e3de13a
NC		 16897}
16898
4e617b1e
PB		 16899typedef struct
16900{
57402f1e 16901 void *flaginfo;
4e617b1e 16902 struct bfd_link_info *info;
91a5743d
PB		 16903 asection *sec;
16904 int sec_shndx;
6e0b88f1
AM		 16905 int (*func) (void *, const char *, Elf_Internal_Sym *,
16906 asection *, struct elf_link_hash_entry *);
4e617b1e
PB		 16907} output_arch_syminfo;
16908
16909enum map_symbol_type
16910{
16911 ARM_MAP_ARM,
16912 ARM_MAP_THUMB,
16913 ARM_MAP_DATA
16914};
16915
16916
7413f23f 16917/* Output a single mapping symbol. */
4e617b1e
PB		 16918
16919static bfd_boolean
7413f23f
DJ		 16920elf32_arm_output_map_sym (output_arch_syminfo *osi,
16921 enum map_symbol_type type,
16922 bfd_vma offset)
4e617b1e
PB		 16923{
16924 static const char *names[3] = {"$a", "$t", "$d"};
4e617b1e
PB		 16925 Elf_Internal_Sym sym;
16926
91a5743d
PB		 16927 sym.st_value = osi->sec->output_section->vma
16928 + osi->sec->output_offset
16929 + offset;
4e617b1e
PB		 16930 sym.st_size = 0;
16931 sym.st_other = 0;
16932 sym.st_info = ELF_ST_INFO (STB_LOCAL, STT_NOTYPE);
91a5743d 16933 sym.st_shndx = osi->sec_shndx;
35fc36a8 16934 sym.st_target_internal = 0;
fe33d2fa 16935 elf32_arm_section_map_add (osi->sec, names[type][1], offset);
57402f1e 16936 return osi->func (osi->flaginfo, names[type], &sym, osi->sec, NULL) == 1;
4e617b1e
PB		 16937}
16938
34e77a92
RS		 16939/* Output mapping symbols for the PLT entry described by ROOT_PLT and ARM_PLT.
16940 IS_IPLT_ENTRY_P says whether the PLT is in .iplt rather than .plt. */
4e617b1e
PB		 16941
16942static bfd_boolean
34e77a92
RS		 16943elf32_arm_output_plt_map_1 (output_arch_syminfo *osi,
16944 bfd_boolean is_iplt_entry_p,
16945 union gotplt_union *root_plt,
16946 struct arm_plt_info *arm_plt)
4e617b1e 16947{
4e617b1e 16948 struct elf32_arm_link_hash_table *htab;
34e77a92 16949 bfd_vma addr, plt_header_size;
4e617b1e 16950
34e77a92 16951 if (root_plt->offset == (bfd_vma) -1)
4e617b1e
PB		 16952 return TRUE;
16953
4dfe6ac6
NC		 16954 htab = elf32_arm_hash_table (osi->info);
16955 if (htab == NULL)
16956 return FALSE;
16957
34e77a92
RS		 16958 if (is_iplt_entry_p)
16959 {
16960 osi->sec = htab->root.iplt;
16961 plt_header_size = 0;
16962 }
16963 else
16964 {
16965 osi->sec = htab->root.splt;
16966 plt_header_size = htab->plt_header_size;
16967 }
16968 osi->sec_shndx = (_bfd_elf_section_from_bfd_section
16969 (osi->info->output_bfd, osi->sec->output_section));
16970
16971 addr = root_plt->offset & -2;
4e617b1e
PB		 16972 if (htab->symbian_p)
16973 {
7413f23f 16974 if (!elf32_arm_output_map_sym (osi, ARM_MAP_ARM, addr))
4e617b1e 16975 return FALSE;
7413f23f 16976 if (!elf32_arm_output_map_sym (osi, ARM_MAP_DATA, addr + 4))
4e617b1e
PB		 16977 return FALSE;
16978 }
16979 else if (htab->vxworks_p)
16980 {
7413f23f 16981 if (!elf32_arm_output_map_sym (osi, ARM_MAP_ARM, addr))
4e617b1e 16982 return FALSE;
7413f23f 16983 if (!elf32_arm_output_map_sym (osi, ARM_MAP_DATA, addr + 8))
4e617b1e 16984 return FALSE;
7413f23f 16985 if (!elf32_arm_output_map_sym (osi, ARM_MAP_ARM, addr + 12))
4e617b1e 16986 return FALSE;
7413f23f 16987 if (!elf32_arm_output_map_sym (osi, ARM_MAP_DATA, addr + 20))
4e617b1e
PB		 16988 return FALSE;
16989 }
b38cadfb
NC		 16990 else if (htab->nacl_p)
16991 {
16992 if (!elf32_arm_output_map_sym (osi, ARM_MAP_ARM, addr))
16993 return FALSE;
16994 }
eed94f8f
NC		 16995 else if (using_thumb_only (htab))
16996 {
16997 if (!elf32_arm_output_map_sym (osi, ARM_MAP_THUMB, addr))
16998 return FALSE;
6a631e86 16999 }
4e617b1e
PB		 17000 else
17001 {
34e77a92 17002 bfd_boolean thumb_stub_p;
bd97cb95 17003
34e77a92
RS		 17004 thumb_stub_p = elf32_arm_plt_needs_thumb_stub_p (osi->info, arm_plt);
17005 if (thumb_stub_p)
4e617b1e 17006 {
7413f23f 17007 if (!elf32_arm_output_map_sym (osi, ARM_MAP_THUMB, addr - 4))
4e617b1e
PB		 17008 return FALSE;
17009 }
17010#ifdef FOUR_WORD_PLT
7413f23f 17011 if (!elf32_arm_output_map_sym (osi, ARM_MAP_ARM, addr))
4e617b1e 17012 return FALSE;
7413f23f 17013 if (!elf32_arm_output_map_sym (osi, ARM_MAP_DATA, addr + 12))
4e617b1e
PB		 17014 return FALSE;
17015#else
906e58ca 17016 /* A three-word PLT with no Thumb thunk contains only Arm code,
4e617b1e
PB		 17017 so only need to output a mapping symbol for the first PLT entry and
17018 entries with thumb thunks. */
34e77a92 17019 if (thumb_stub_p || addr == plt_header_size)
4e617b1e 17020 {
7413f23f 17021 if (!elf32_arm_output_map_sym (osi, ARM_MAP_ARM, addr))
4e617b1e
PB		 17022 return FALSE;
17023 }
17024#endif
17025 }
17026
17027 return TRUE;
17028}
17029
34e77a92
RS		 17030/* Output mapping symbols for PLT entries associated with H. */
17031
17032static bfd_boolean
17033elf32_arm_output_plt_map (struct elf_link_hash_entry *h, void *inf)
17034{
17035 output_arch_syminfo *osi = (output_arch_syminfo *) inf;
17036 struct elf32_arm_link_hash_entry *eh;
17037
17038 if (h->root.type == bfd_link_hash_indirect)
17039 return TRUE;
17040
17041 if (h->root.type == bfd_link_hash_warning)
17042 /* When warning symbols are created, they **replace** the "real"
17043 entry in the hash table, thus we never get to see the real
17044 symbol in a hash traversal. So look at it now. */
17045 h = (struct elf_link_hash_entry *) h->root.u.i.link;
17046
17047 eh = (struct elf32_arm_link_hash_entry *) h;
17048 return elf32_arm_output_plt_map_1 (osi, SYMBOL_CALLS_LOCAL (osi->info, h),
17049 &h->plt, &eh->plt);
17050}
17051
4f4faa4d
TP		 17052/* Bind a veneered symbol to its veneer identified by its hash entry
17053 STUB_ENTRY. The veneered location thus loose its symbol. */
17054
17055static void
17056arm_stub_claim_sym (struct elf32_arm_stub_hash_entry *stub_entry)
17057{
17058 struct elf32_arm_link_hash_entry *hash = stub_entry->h;
17059
17060 BFD_ASSERT (hash);
17061 hash->root.root.u.def.section = stub_entry->stub_sec;
17062 hash->root.root.u.def.value = stub_entry->stub_offset;
17063 hash->root.size = stub_entry->stub_size;
17064}
17065
7413f23f
DJ		 17066/* Output a single local symbol for a generated stub. */
17067
17068static bfd_boolean
17069elf32_arm_output_stub_sym (output_arch_syminfo *osi, const char *name,
17070 bfd_vma offset, bfd_vma size)
17071{
7413f23f
DJ		 17072 Elf_Internal_Sym sym;
17073
7413f23f
DJ		 17074 sym.st_value = osi->sec->output_section->vma
17075 + osi->sec->output_offset
17076 + offset;
17077 sym.st_size = size;
17078 sym.st_other = 0;
17079 sym.st_info = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
17080 sym.st_shndx = osi->sec_shndx;
35fc36a8 17081 sym.st_target_internal = 0;
57402f1e 17082 return osi->func (osi->flaginfo, name, &sym, osi->sec, NULL) == 1;
7413f23f 17083}
4e617b1e 17084
da5938a2 17085static bfd_boolean
8029a119
NC		 17086arm_map_one_stub (struct bfd_hash_entry * gen_entry,
17087 void * in_arg)
da5938a2
NC		 17088{
17089 struct elf32_arm_stub_hash_entry *stub_entry;
da5938a2
NC		 17090 asection *stub_sec;
17091 bfd_vma addr;
7413f23f 17092 char *stub_name;
9a008db3 17093 output_arch_syminfo *osi;
d3ce72d0 17094 const insn_sequence *template_sequence;
461a49ca
DJ		 17095 enum stub_insn_type prev_type;
17096 int size;
17097 int i;
17098 enum map_symbol_type sym_type;
da5938a2
NC		 17099
17100 /* Massage our args to the form they really have. */
17101 stub_entry = (struct elf32_arm_stub_hash_entry *) gen_entry;
9a008db3 17102 osi = (output_arch_syminfo *) in_arg;
da5938a2 17103
da5938a2
NC		 17104 stub_sec = stub_entry->stub_sec;
17105
17106 /* Ensure this stub is attached to the current section being
7413f23f 17107 processed. */
da5938a2
NC		 17108 if (stub_sec != osi->sec)
17109 return TRUE;
17110
7413f23f 17111 addr = (bfd_vma) stub_entry->stub_offset;
d3ce72d0 17112 template_sequence = stub_entry->stub_template;
4f4faa4d
TP		 17113
17114 if (arm_stub_sym_claimed (stub_entry->stub_type))
17115 arm_stub_claim_sym (stub_entry);
17116 else
7413f23f 17117 {
4f4faa4d
TP		 17118 stub_name = stub_entry->output_name;
17119 switch (template_sequence[0].type)
17120 {
17121 case ARM_TYPE:
17122 if (!elf32_arm_output_stub_sym (osi, stub_name, addr,
17123 stub_entry->stub_size))
17124 return FALSE;
17125 break;
17126 case THUMB16_TYPE:
17127 case THUMB32_TYPE:
17128 if (!elf32_arm_output_stub_sym (osi, stub_name, addr | 1,
17129 stub_entry->stub_size))
17130 return FALSE;
17131 break;
17132 default:
17133 BFD_FAIL ();
17134 return 0;
17135 }
7413f23f 17136 }
da5938a2 17137
461a49ca
DJ		 17138 prev_type = DATA_TYPE;
17139 size = 0;
17140 for (i = 0; i < stub_entry->stub_template_size; i++)
17141 {
d3ce72d0 17142 switch (template_sequence[i].type)
461a49ca
DJ		 17143 {
17144 case ARM_TYPE:
17145 sym_type = ARM_MAP_ARM;
17146 break;
17147
17148 case THUMB16_TYPE:
48229727 17149 case THUMB32_TYPE:
461a49ca
DJ		 17150 sym_type = ARM_MAP_THUMB;
17151 break;
17152
17153 case DATA_TYPE:
17154 sym_type = ARM_MAP_DATA;
17155 break;
17156
17157 default:
17158 BFD_FAIL ();
4e31c731 17159 return FALSE;
461a49ca
DJ		 17160 }
17161
d3ce72d0 17162 if (template_sequence[i].type != prev_type)
461a49ca 17163 {
d3ce72d0 17164 prev_type = template_sequence[i].type;
461a49ca
DJ		 17165 if (!elf32_arm_output_map_sym (osi, sym_type, addr + size))
17166 return FALSE;
17167 }
17168
d3ce72d0 17169 switch (template_sequence[i].type)
461a49ca
DJ		 17170 {
17171 case ARM_TYPE:
48229727 17172 case THUMB32_TYPE:
461a49ca
DJ		 17173 size += 4;
17174 break;
17175
17176 case THUMB16_TYPE:
17177 size += 2;
17178 break;
17179
17180 case DATA_TYPE:
17181 size += 4;
17182 break;
17183
17184 default:
17185 BFD_FAIL ();
4e31c731 17186 return FALSE;
461a49ca
DJ		 17187 }
17188 }
17189
da5938a2
NC		 17190 return TRUE;
17191}
17192
33811162
DG		 17193/* Output mapping symbols for linker generated sections,
17194 and for those data-only sections that do not have a
17195 $d. */
4e617b1e
PB		 17196
17197static bfd_boolean
17198elf32_arm_output_arch_local_syms (bfd *output_bfd,
906e58ca 17199 struct bfd_link_info *info,
57402f1e 17200 void *flaginfo,
6e0b88f1
AM		 17201 int (*func) (void *, const char *,
17202 Elf_Internal_Sym *,
17203 asection *,
17204 struct elf_link_hash_entry *))
4e617b1e
PB		 17205{
17206 output_arch_syminfo osi;
17207 struct elf32_arm_link_hash_table *htab;
91a5743d
PB		 17208 bfd_vma offset;
17209 bfd_size_type size;
33811162 17210 bfd *input_bfd;
4e617b1e
PB		 17211
17212 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 17213 if (htab == NULL)
17214 return FALSE;
17215
906e58ca 17216 check_use_blx (htab);
91a5743d 17217
57402f1e 17218 osi.flaginfo = flaginfo;
4e617b1e
PB		 17219 osi.info = info;
17220 osi.func = func;
906e58ca 17221
33811162
DG		 17222 /* Add a $d mapping symbol to data-only sections that
17223 don't have any mapping symbol. This may result in (harmless) redundant
17224 mapping symbols. */
17225 for (input_bfd = info->input_bfds;
17226 input_bfd != NULL;
c72f2fb2 17227 input_bfd = input_bfd->link.next)
33811162
DG		 17228 {
17229 if ((input_bfd->flags & (BFD_LINKER_CREATED | HAS_SYMS)) == HAS_SYMS)
17230 for (osi.sec = input_bfd->sections;
17231 osi.sec != NULL;
17232 osi.sec = osi.sec->next)
17233 {
17234 if (osi.sec->output_section != NULL
f7dd8c79
DJ		 17235 && ((osi.sec->output_section->flags & (SEC_ALLOC | SEC_CODE))
17236 != 0)
33811162
DG		 17237 && (osi.sec->flags & (SEC_HAS_CONTENTS | SEC_LINKER_CREATED))
17238 == SEC_HAS_CONTENTS
17239 && get_arm_elf_section_data (osi.sec) != NULL
501abfe0 17240 && get_arm_elf_section_data (osi.sec)->mapcount == 0
7d500b83
CL		 17241 && osi.sec->size > 0
17242 && (osi.sec->flags & SEC_EXCLUDE) == 0)
33811162
DG		 17243 {
17244 osi.sec_shndx = _bfd_elf_section_from_bfd_section
17245 (output_bfd, osi.sec->output_section);
17246 if (osi.sec_shndx != (int)SHN_BAD)
17247 elf32_arm_output_map_sym (&osi, ARM_MAP_DATA, 0);
17248 }
17249 }
17250 }
17251
91a5743d
PB		 17252 /* ARM->Thumb glue. */
17253 if (htab->arm_glue_size > 0)
17254 {
3d4d4302
AM		 17255 osi.sec = bfd_get_linker_section (htab->bfd_of_glue_owner,
17256 ARM2THUMB_GLUE_SECTION_NAME);
91a5743d
PB		 17257
17258 osi.sec_shndx = _bfd_elf_section_from_bfd_section
17259 (output_bfd, osi.sec->output_section);
0e1862bb 17260 if (bfd_link_pic (info) || htab->root.is_relocatable_executable
91a5743d
PB		 17261 || htab->pic_veneer)
17262 size = ARM2THUMB_PIC_GLUE_SIZE;
17263 else if (htab->use_blx)
17264 size = ARM2THUMB_V5_STATIC_GLUE_SIZE;
17265 else
17266 size = ARM2THUMB_STATIC_GLUE_SIZE;
4e617b1e 17267
91a5743d
PB		 17268 for (offset = 0; offset < htab->arm_glue_size; offset += size)
17269 {
7413f23f
DJ		 17270 elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, offset);
17271 elf32_arm_output_map_sym (&osi, ARM_MAP_DATA, offset + size - 4);
91a5743d
PB		 17272 }
17273 }
17274
17275 /* Thumb->ARM glue. */
17276 if (htab->thumb_glue_size > 0)
17277 {
3d4d4302
AM		 17278 osi.sec = bfd_get_linker_section (htab->bfd_of_glue_owner,
17279 THUMB2ARM_GLUE_SECTION_NAME);
91a5743d
PB		 17280
17281 osi.sec_shndx = _bfd_elf_section_from_bfd_section
17282 (output_bfd, osi.sec->output_section);
17283 size = THUMB2ARM_GLUE_SIZE;
17284
17285 for (offset = 0; offset < htab->thumb_glue_size; offset += size)
17286 {
7413f23f
DJ		 17287 elf32_arm_output_map_sym (&osi, ARM_MAP_THUMB, offset);
17288 elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, offset + 4);
91a5743d
PB		 17289 }
17290 }
17291
845b51d6
PB		 17292 /* ARMv4 BX veneers. */
17293 if (htab->bx_glue_size > 0)
17294 {
3d4d4302
AM		 17295 osi.sec = bfd_get_linker_section (htab->bfd_of_glue_owner,
17296 ARM_BX_GLUE_SECTION_NAME);
845b51d6
PB		 17297
17298 osi.sec_shndx = _bfd_elf_section_from_bfd_section
17299 (output_bfd, osi.sec->output_section);
17300
7413f23f 17301 elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, 0);
845b51d6
PB		 17302 }
17303
8029a119
NC		 17304 /* Long calls stubs. */
17305 if (htab->stub_bfd && htab->stub_bfd->sections)
17306 {
da5938a2 17307 asection* stub_sec;
8029a119 17308
da5938a2
NC		 17309 for (stub_sec = htab->stub_bfd->sections;
17310 stub_sec != NULL;
8029a119
NC		 17311 stub_sec = stub_sec->next)
17312 {
17313 /* Ignore non-stub sections. */
17314 if (!strstr (stub_sec->name, STUB_SUFFIX))
17315 continue;
da5938a2 17316
8029a119 17317 osi.sec = stub_sec;
da5938a2 17318
8029a119
NC		 17319 osi.sec_shndx = _bfd_elf_section_from_bfd_section
17320 (output_bfd, osi.sec->output_section);
da5938a2 17321
8029a119
NC		 17322 bfd_hash_traverse (&htab->stub_hash_table, arm_map_one_stub, &osi);
17323 }
17324 }
da5938a2 17325
91a5743d 17326 /* Finally, output mapping symbols for the PLT. */
34e77a92 17327 if (htab->root.splt && htab->root.splt->size > 0)
4e617b1e 17328 {
34e77a92
RS		 17329 osi.sec = htab->root.splt;
17330 osi.sec_shndx = (_bfd_elf_section_from_bfd_section
17331 (output_bfd, osi.sec->output_section));
17332
17333 /* Output mapping symbols for the plt header. SymbianOS does not have a
17334 plt header. */
17335 if (htab->vxworks_p)
17336 {
17337 /* VxWorks shared libraries have no PLT header. */
0e1862bb 17338 if (!bfd_link_pic (info))
34e77a92
RS		 17339 {
17340 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, 0))
17341 return FALSE;
17342 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_DATA, 12))
17343 return FALSE;
17344 }
17345 }
b38cadfb
NC		 17346 else if (htab->nacl_p)
17347 {
17348 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, 0))
17349 return FALSE;
17350 }
eed94f8f
NC		 17351 else if (using_thumb_only (htab))
17352 {
17353 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_THUMB, 0))
17354 return FALSE;
17355 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_DATA, 12))
17356 return FALSE;
17357 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_THUMB, 16))
17358 return FALSE;
17359 }
34e77a92 17360 else if (!htab->symbian_p)
4e617b1e 17361 {
7413f23f 17362 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, 0))
4e617b1e 17363 return FALSE;
34e77a92
RS		 17364#ifndef FOUR_WORD_PLT
17365 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_DATA, 16))
4e617b1e 17366 return FALSE;
34e77a92 17367#endif
4e617b1e
PB		 17368 }
17369 }
99059e56
RM		 17370 if (htab->nacl_p && htab->root.iplt && htab->root.iplt->size > 0)
17371 {
17372 /* NaCl uses a special first entry in .iplt too. */
17373 osi.sec = htab->root.iplt;
17374 osi.sec_shndx = (_bfd_elf_section_from_bfd_section
17375 (output_bfd, osi.sec->output_section));
17376 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, 0))
17377 return FALSE;
17378 }
34e77a92
RS		 17379 if ((htab->root.splt && htab->root.splt->size > 0)
17380 || (htab->root.iplt && htab->root.iplt->size > 0))
4e617b1e 17381 {
34e77a92
RS		 17382 elf_link_hash_traverse (&htab->root, elf32_arm_output_plt_map, &osi);
17383 for (input_bfd = info->input_bfds;
17384 input_bfd != NULL;
c72f2fb2 17385 input_bfd = input_bfd->link.next)
34e77a92
RS		 17386 {
17387 struct arm_local_iplt_info **local_iplt;
17388 unsigned int i, num_syms;
4e617b1e 17389
34e77a92
RS		 17390 local_iplt = elf32_arm_local_iplt (input_bfd);
17391 if (local_iplt != NULL)
17392 {
17393 num_syms = elf_symtab_hdr (input_bfd).sh_info;
17394 for (i = 0; i < num_syms; i++)
17395 if (local_iplt[i] != NULL
17396 && !elf32_arm_output_plt_map_1 (&osi, TRUE,
17397 &local_iplt[i]->root,
17398 &local_iplt[i]->arm))
17399 return FALSE;
17400 }
17401 }
17402 }
0855e32b
NS		 17403 if (htab->dt_tlsdesc_plt != 0)
17404 {
17405 /* Mapping symbols for the lazy tls trampoline. */
17406 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, htab->dt_tlsdesc_plt))
17407 return FALSE;
b38cadfb 17408
0855e32b
NS		 17409 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_DATA,
17410 htab->dt_tlsdesc_plt + 24))
17411 return FALSE;
17412 }
17413 if (htab->tls_trampoline != 0)
17414 {
17415 /* Mapping symbols for the tls trampoline. */
17416 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, htab->tls_trampoline))
17417 return FALSE;
17418#ifdef FOUR_WORD_PLT
17419 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_DATA,
17420 htab->tls_trampoline + 12))
17421 return FALSE;
b38cadfb 17422#endif
0855e32b 17423 }
b38cadfb 17424
4e617b1e
PB		 17425 return TRUE;
17426}
17427
54ddd295
TP		 17428/* Filter normal symbols of CMSE entry functions of ABFD to include in
17429 the import library. All SYMCOUNT symbols of ABFD can be examined
17430 from their pointers in SYMS. Pointers of symbols to keep should be
17431 stored continuously at the beginning of that array.
17432
17433 Returns the number of symbols to keep. */
17434
17435static unsigned int
17436elf32_arm_filter_cmse_symbols (bfd *abfd ATTRIBUTE_UNUSED,
17437 struct bfd_link_info *info,
17438 asymbol **syms, long symcount)
17439{
17440 size_t maxnamelen;
17441 char *cmse_name;
17442 long src_count, dst_count = 0;
17443 struct elf32_arm_link_hash_table *htab;
17444
17445 htab = elf32_arm_hash_table (info);
17446 if (!htab->stub_bfd || !htab->stub_bfd->sections)
17447 symcount = 0;
17448
17449 maxnamelen = 128;
17450 cmse_name = (char *) bfd_malloc (maxnamelen);
17451 for (src_count = 0; src_count < symcount; src_count++)
17452 {
17453 struct elf32_arm_link_hash_entry *cmse_hash;
17454 asymbol *sym;
17455 flagword flags;
17456 char *name;
17457 size_t namelen;
17458
17459 sym = syms[src_count];
17460 flags = sym->flags;
17461 name = (char *) bfd_asymbol_name (sym);
17462
17463 if ((flags & BSF_FUNCTION) != BSF_FUNCTION)
17464 continue;
17465 if (!(flags & (BSF_GLOBAL | BSF_WEAK)))
17466 continue;
17467
17468 namelen = strlen (name) + sizeof (CMSE_PREFIX) + 1;
17469 if (namelen > maxnamelen)
17470 {
17471 cmse_name = (char *)
17472 bfd_realloc (cmse_name, namelen);
17473 maxnamelen = namelen;
17474 }
17475 snprintf (cmse_name, maxnamelen, "%s%s", CMSE_PREFIX, name);
17476 cmse_hash = (struct elf32_arm_link_hash_entry *)
17477 elf_link_hash_lookup (&(htab)->root, cmse_name, FALSE, FALSE, TRUE);
17478
17479 if (!cmse_hash
17480 || (cmse_hash->root.root.type != bfd_link_hash_defined
17481 && cmse_hash->root.root.type != bfd_link_hash_defweak)
17482 || cmse_hash->root.type != STT_FUNC)
17483 continue;
17484
17485 if (!ARM_GET_SYM_CMSE_SPCL (cmse_hash->root.target_internal))
17486 continue;
17487
17488 syms[dst_count++] = sym;
17489 }
17490 free (cmse_name);
17491
17492 syms[dst_count] = NULL;
17493
17494 return dst_count;
17495}
17496
17497/* Filter symbols of ABFD to include in the import library. All
17498 SYMCOUNT symbols of ABFD can be examined from their pointers in
17499 SYMS. Pointers of symbols to keep should be stored continuously at
17500 the beginning of that array.
17501
17502 Returns the number of symbols to keep. */
17503
17504static unsigned int
17505elf32_arm_filter_implib_symbols (bfd *abfd ATTRIBUTE_UNUSED,
17506 struct bfd_link_info *info,
17507 asymbol **syms, long symcount)
17508{
17509 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (info);
17510
17511 if (globals->cmse_implib)
17512 return elf32_arm_filter_cmse_symbols (abfd, info, syms, symcount);
17513 else
17514 return _bfd_elf_filter_global_symbols (abfd, info, syms, symcount);
17515}
17516
e489d0ae
PB		 17517/* Allocate target specific section data. */
17518
17519static bfd_boolean
17520elf32_arm_new_section_hook (bfd *abfd, asection *sec)
17521{
f592407e
AM		 17522 if (!sec->used_by_bfd)
17523 {
17524 _arm_elf_section_data *sdata;
17525 bfd_size_type amt = sizeof (*sdata);
e489d0ae 17526
21d799b5 17527 sdata = (_arm_elf_section_data *) bfd_zalloc (abfd, amt);
f592407e
AM		 17528 if (sdata == NULL)
17529 return FALSE;
17530 sec->used_by_bfd = sdata;
17531 }
e489d0ae
PB		 17532
17533 return _bfd_elf_new_section_hook (abfd, sec);
17534}
17535
17536
17537/* Used to order a list of mapping symbols by address. */
17538
17539static int
17540elf32_arm_compare_mapping (const void * a, const void * b)
17541{
7f6a71ff
JM		 17542 const elf32_arm_section_map *amap = (const elf32_arm_section_map *) a;
17543 const elf32_arm_section_map *bmap = (const elf32_arm_section_map *) b;
17544
17545 if (amap->vma > bmap->vma)
17546 return 1;
17547 else if (amap->vma < bmap->vma)
17548 return -1;
17549 else if (amap->type > bmap->type)
17550 /* Ensure results do not depend on the host qsort for objects with
17551 multiple mapping symbols at the same address by sorting on type
17552 after vma. */
17553 return 1;
17554 else if (amap->type < bmap->type)
17555 return -1;
17556 else
17557 return 0;
e489d0ae
PB		 17558}
17559
2468f9c9
PB		 17560/* Add OFFSET to lower 31 bits of ADDR, leaving other bits unmodified. */
17561
17562static unsigned long
17563offset_prel31 (unsigned long addr, bfd_vma offset)
17564{
17565 return (addr & ~0x7ffffffful) | ((addr + offset) & 0x7ffffffful);
17566}
17567
17568/* Copy an .ARM.exidx table entry, adding OFFSET to (applied) PREL31
17569 relocations. */
17570
17571static void
17572copy_exidx_entry (bfd *output_bfd, bfd_byte *to, bfd_byte *from, bfd_vma offset)
17573{
17574 unsigned long first_word = bfd_get_32 (output_bfd, from);
17575 unsigned long second_word = bfd_get_32 (output_bfd, from + 4);
b38cadfb 17576
2468f9c9
PB		 17577 /* High bit of first word is supposed to be zero. */
17578 if ((first_word & 0x80000000ul) == 0)
17579 first_word = offset_prel31 (first_word, offset);
b38cadfb 17580
2468f9c9
PB		 17581 /* If the high bit of the first word is clear, and the bit pattern is not 0x1
17582 (EXIDX_CANTUNWIND), this is an offset to an .ARM.extab entry. */
17583 if ((second_word != 0x1) && ((second_word & 0x80000000ul) == 0))
17584 second_word = offset_prel31 (second_word, offset);
b38cadfb 17585
2468f9c9
PB		 17586 bfd_put_32 (output_bfd, first_word, to);
17587 bfd_put_32 (output_bfd, second_word, to + 4);
17588}
e489d0ae 17589
48229727
JB		 17590/* Data for make_branch_to_a8_stub(). */
17591
b38cadfb
NC		 17592struct a8_branch_to_stub_data
17593{
48229727
JB		 17594 asection *writing_section;
17595 bfd_byte *contents;
17596};
17597
17598
17599/* Helper to insert branches to Cortex-A8 erratum stubs in the right
17600 places for a particular section. */
17601
17602static bfd_boolean
17603make_branch_to_a8_stub (struct bfd_hash_entry *gen_entry,
99059e56 17604 void *in_arg)
48229727
JB		 17605{
17606 struct elf32_arm_stub_hash_entry *stub_entry;
17607 struct a8_branch_to_stub_data *data;
17608 bfd_byte *contents;
17609 unsigned long branch_insn;
17610 bfd_vma veneered_insn_loc, veneer_entry_loc;
17611 bfd_signed_vma branch_offset;
17612 bfd *abfd;
8d9d9490 17613 unsigned int loc;
48229727
JB		 17614
17615 stub_entry = (struct elf32_arm_stub_hash_entry *) gen_entry;
17616 data = (struct a8_branch_to_stub_data *) in_arg;
17617
17618 if (stub_entry->target_section != data->writing_section
4563a860 17619 || stub_entry->stub_type < arm_stub_a8_veneer_lwm)
48229727
JB		 17620 return TRUE;
17621
17622 contents = data->contents;
17623
8d9d9490
TP		 17624 /* We use target_section as Cortex-A8 erratum workaround stubs are only
17625 generated when both source and target are in the same section. */
48229727
JB		 17626 veneered_insn_loc = stub_entry->target_section->output_section->vma
17627 + stub_entry->target_section->output_offset
8d9d9490 17628 + stub_entry->source_value;
48229727
JB		 17629
17630 veneer_entry_loc = stub_entry->stub_sec->output_section->vma
17631 + stub_entry->stub_sec->output_offset
17632 + stub_entry->stub_offset;
17633
17634 if (stub_entry->stub_type == arm_stub_a8_veneer_blx)
17635 veneered_insn_loc &= ~3u;
17636
17637 branch_offset = veneer_entry_loc - veneered_insn_loc - 4;
17638
17639 abfd = stub_entry->target_section->owner;
8d9d9490 17640 loc = stub_entry->source_value;
48229727
JB		 17641
17642 /* We attempt to avoid this condition by setting stubs_always_after_branch
17643 in elf32_arm_size_stubs if we've enabled the Cortex-A8 erratum workaround.
17644 This check is just to be on the safe side... */
17645 if ((veneered_insn_loc & ~0xfff) == (veneer_entry_loc & ~0xfff))
17646 {
4eca0228
AM		 17647 _bfd_error_handler (_("%B: error: Cortex-A8 erratum stub is "
17648 "allocated in unsafe location"), abfd);
48229727
JB		 17649 return FALSE;
17650 }
17651
17652 switch (stub_entry->stub_type)
17653 {
17654 case arm_stub_a8_veneer_b:
17655 case arm_stub_a8_veneer_b_cond:
17656 branch_insn = 0xf0009000;
17657 goto jump24;
17658
17659 case arm_stub_a8_veneer_blx:
17660 branch_insn = 0xf000e800;
17661 goto jump24;
17662
17663 case arm_stub_a8_veneer_bl:
17664 {
17665 unsigned int i1, j1, i2, j2, s;
17666
17667 branch_insn = 0xf000d000;
17668
17669 jump24:
17670 if (branch_offset < -16777216 || branch_offset > 16777214)
17671 {
17672 /* There's not much we can do apart from complain if this
17673 happens. */
4eca0228
AM		 17674 _bfd_error_handler (_("%B: error: Cortex-A8 erratum stub out "
17675 "of range (input file too large)"), abfd);
48229727
JB		 17676 return FALSE;
17677 }
17678
17679 /* i1 = not(j1 eor s), so:
17680 not i1 = j1 eor s
17681 j1 = (not i1) eor s. */
17682
17683 branch_insn |= (branch_offset >> 1) & 0x7ff;
17684 branch_insn |= ((branch_offset >> 12) & 0x3ff) << 16;
17685 i2 = (branch_offset >> 22) & 1;
17686 i1 = (branch_offset >> 23) & 1;
17687 s = (branch_offset >> 24) & 1;
17688 j1 = (!i1) ^ s;
17689 j2 = (!i2) ^ s;
17690 branch_insn |= j2 << 11;
17691 branch_insn |= j1 << 13;
17692 branch_insn |= s << 26;
17693 }
17694 break;
17695
17696 default:
17697 BFD_FAIL ();
17698 return FALSE;
17699 }
17700
8d9d9490
TP		 17701 bfd_put_16 (abfd, (branch_insn >> 16) & 0xffff, &contents[loc]);
17702 bfd_put_16 (abfd, branch_insn & 0xffff, &contents[loc + 2]);
48229727
JB		 17703
17704 return TRUE;
17705}
17706
a504d23a
LA		 17707/* Beginning of stm32l4xx work-around. */
17708
17709/* Functions encoding instructions necessary for the emission of the
17710 fix-stm32l4xx-629360.
17711 Encoding is extracted from the
17712 ARM (C) Architecture Reference Manual
17713 ARMv7-A and ARMv7-R edition
17714 ARM DDI 0406C.b (ID072512). */
17715
17716static inline bfd_vma
82188b29 17717create_instruction_branch_absolute (int branch_offset)
a504d23a
LA		 17718{
17719 /* A8.8.18 B (A8-334)
17720 B target_address (Encoding T4). */
17721 /* 1111 - 0Sii - iiii - iiii - 10J1 - Jiii - iiii - iiii. */
17722 /* jump offset is: S:I1:I2:imm10:imm11:0. */
17723 /* with : I1 = NOT (J1 EOR S) I2 = NOT (J2 EOR S). */
17724
a504d23a
LA		 17725 int s = ((branch_offset & 0x1000000) >> 24);
17726 int j1 = s ^ !((branch_offset & 0x800000) >> 23);
17727 int j2 = s ^ !((branch_offset & 0x400000) >> 22);
17728
17729 if (branch_offset < -(1 << 24) || branch_offset >= (1 << 24))
17730 BFD_ASSERT (0 && "Error: branch out of range. Cannot create branch.");
17731
17732 bfd_vma patched_inst = 0xf0009000
17733 | s << 26 /* S. */
17734 | (((unsigned long) (branch_offset) >> 12) & 0x3ff) << 16 /* imm10. */
17735 | j1 << 13 /* J1. */
17736 | j2 << 11 /* J2. */
17737 | (((unsigned long) (branch_offset) >> 1) & 0x7ff); /* imm11. */
17738
17739 return patched_inst;
17740}
17741
17742static inline bfd_vma
17743create_instruction_ldmia (int base_reg, int wback, int reg_mask)
17744{
17745 /* A8.8.57 LDM/LDMIA/LDMFD (A8-396)
17746 LDMIA Rn!, {Ra, Rb, Rc, ...} (Encoding T2). */
17747 bfd_vma patched_inst = 0xe8900000
17748 | (/*W=*/wback << 21)
17749 | (base_reg << 16)
17750 | (reg_mask & 0x0000ffff);
17751
17752 return patched_inst;
17753}
17754
17755static inline bfd_vma
17756create_instruction_ldmdb (int base_reg, int wback, int reg_mask)
17757{
17758 /* A8.8.60 LDMDB/LDMEA (A8-402)
17759 LDMDB Rn!, {Ra, Rb, Rc, ...} (Encoding T1). */
17760 bfd_vma patched_inst = 0xe9100000
17761 | (/*W=*/wback << 21)
17762 | (base_reg << 16)
17763 | (reg_mask & 0x0000ffff);
17764
17765 return patched_inst;
17766}
17767
17768static inline bfd_vma
17769create_instruction_mov (int target_reg, int source_reg)
17770{
17771 /* A8.8.103 MOV (register) (A8-486)
17772 MOV Rd, Rm (Encoding T1). */
17773 bfd_vma patched_inst = 0x4600
17774 | (target_reg & 0x7)
17775 | ((target_reg & 0x8) >> 3) << 7
17776 | (source_reg << 3);
17777
17778 return patched_inst;
17779}
17780
17781static inline bfd_vma
17782create_instruction_sub (int target_reg, int source_reg, int value)
17783{
17784 /* A8.8.221 SUB (immediate) (A8-708)
17785 SUB Rd, Rn, #value (Encoding T3). */
17786 bfd_vma patched_inst = 0xf1a00000
17787 | (target_reg << 8)
17788 | (source_reg << 16)
17789 | (/*S=*/0 << 20)
17790 | ((value & 0x800) >> 11) << 26
17791 | ((value & 0x700) >> 8) << 12
17792 | (value & 0x0ff);
17793
17794 return patched_inst;
17795}
17796
17797static inline bfd_vma
9239bbd3 17798create_instruction_vldmia (int base_reg, int is_dp, int wback, int num_words,
a504d23a
LA		 17799 int first_reg)
17800{
17801 /* A8.8.332 VLDM (A8-922)
9239bbd3
CM		 17802 VLMD{MODE} Rn{!}, {list} (Encoding T1 or T2). */
17803 bfd_vma patched_inst = (is_dp ? 0xec900b00 : 0xec900a00)
a504d23a
LA		 17804 | (/*W=*/wback << 21)
17805 | (base_reg << 16)
9239bbd3
CM		 17806 | (num_words & 0x000000ff)
17807 | (((unsigned)first_reg >> 1) & 0x0000000f) << 12
a504d23a
LA		 17808 | (first_reg & 0x00000001) << 22;
17809
17810 return patched_inst;
17811}
17812
17813static inline bfd_vma
9239bbd3
CM		 17814create_instruction_vldmdb (int base_reg, int is_dp, int num_words,
17815 int first_reg)
a504d23a
LA		 17816{
17817 /* A8.8.332 VLDM (A8-922)
9239bbd3
CM		 17818 VLMD{MODE} Rn!, {} (Encoding T1 or T2). */
17819 bfd_vma patched_inst = (is_dp ? 0xed300b00 : 0xed300a00)
a504d23a 17820 | (base_reg << 16)
9239bbd3
CM		 17821 | (num_words & 0x000000ff)
17822 | (((unsigned)first_reg >>1 ) & 0x0000000f) << 12
a504d23a
LA		 17823 | (first_reg & 0x00000001) << 22;
17824
17825 return patched_inst;
17826}
17827
17828static inline bfd_vma
17829create_instruction_udf_w (int value)
17830{
17831 /* A8.8.247 UDF (A8-758)
17832 Undefined (Encoding T2). */
17833 bfd_vma patched_inst = 0xf7f0a000
17834 | (value & 0x00000fff)
17835 | (value & 0x000f0000) << 16;
17836
17837 return patched_inst;
17838}
17839
17840static inline bfd_vma
17841create_instruction_udf (int value)
17842{
17843 /* A8.8.247 UDF (A8-758)
17844 Undefined (Encoding T1). */
17845 bfd_vma patched_inst = 0xde00
17846 | (value & 0xff);
17847
17848 return patched_inst;
17849}
17850
17851/* Functions writing an instruction in memory, returning the next
17852 memory position to write to. */
17853
17854static inline bfd_byte *
17855push_thumb2_insn32 (struct elf32_arm_link_hash_table * htab,
17856 bfd * output_bfd, bfd_byte *pt, insn32 insn)
17857{
17858 put_thumb2_insn (htab, output_bfd, insn, pt);
17859 return pt + 4;
17860}
17861
17862static inline bfd_byte *
17863push_thumb2_insn16 (struct elf32_arm_link_hash_table * htab,
17864 bfd * output_bfd, bfd_byte *pt, insn32 insn)
17865{
17866 put_thumb_insn (htab, output_bfd, insn, pt);
17867 return pt + 2;
17868}
17869
17870/* Function filling up a region in memory with T1 and T2 UDFs taking
17871 care of alignment. */
17872
17873static bfd_byte *
17874stm32l4xx_fill_stub_udf (struct elf32_arm_link_hash_table * htab,
17875 bfd * output_bfd,
17876 const bfd_byte * const base_stub_contents,
17877 bfd_byte * const from_stub_contents,
17878 const bfd_byte * const end_stub_contents)
17879{
17880 bfd_byte *current_stub_contents = from_stub_contents;
17881
17882 /* Fill the remaining of the stub with deterministic contents : UDF
17883 instructions.
17884 Check if realignment is needed on modulo 4 frontier using T1, to
17885 further use T2. */
17886 if ((current_stub_contents < end_stub_contents)
17887 && !((current_stub_contents - base_stub_contents) % 2)
17888 && ((current_stub_contents - base_stub_contents) % 4))
17889 current_stub_contents =
17890 push_thumb2_insn16 (htab, output_bfd, current_stub_contents,
17891 create_instruction_udf (0));
17892
17893 for (; current_stub_contents < end_stub_contents;)
17894 current_stub_contents =
17895 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
17896 create_instruction_udf_w (0));
17897
17898 return current_stub_contents;
17899}
17900
17901/* Functions writing the stream of instructions equivalent to the
17902 derived sequence for ldmia, ldmdb, vldm respectively. */
17903
17904static void
17905stm32l4xx_create_replacing_stub_ldmia (struct elf32_arm_link_hash_table * htab,
17906 bfd * output_bfd,
17907 const insn32 initial_insn,
17908 const bfd_byte *const initial_insn_addr,
17909 bfd_byte *const base_stub_contents)
17910{
17911 int wback = (initial_insn & 0x00200000) >> 21;
17912 int ri, rn = (initial_insn & 0x000F0000) >> 16;
17913 int insn_all_registers = initial_insn & 0x0000ffff;
17914 int insn_low_registers, insn_high_registers;
17915 int usable_register_mask;
17916 int nb_registers = popcount (insn_all_registers);
17917 int restore_pc = (insn_all_registers & (1 << 15)) ? 1 : 0;
17918 int restore_rn = (insn_all_registers & (1 << rn)) ? 1 : 0;
17919 bfd_byte *current_stub_contents = base_stub_contents;
17920
17921 BFD_ASSERT (is_thumb2_ldmia (initial_insn));
17922
17923 /* In BFD_ARM_STM32L4XX_FIX_ALL mode we may have to deal with
17924 smaller than 8 registers load sequences that do not cause the
17925 hardware issue. */
17926 if (nb_registers <= 8)
17927 {
17928 /* UNTOUCHED : LDMIA Rn{!}, {R-all-register-list}. */
17929 current_stub_contents =
17930 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
17931 initial_insn);
17932
17933 /* B initial_insn_addr+4. */
17934 if (!restore_pc)
17935 current_stub_contents =
17936 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
17937 create_instruction_branch_absolute
82188b29 17938 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 17939
17940 /* Fill the remaining of the stub with deterministic contents. */
17941 current_stub_contents =
17942 stm32l4xx_fill_stub_udf (htab, output_bfd,
17943 base_stub_contents, current_stub_contents,
17944 base_stub_contents +
17945 STM32L4XX_ERRATUM_LDM_VENEER_SIZE);
17946
17947 return;
17948 }
17949
17950 /* - reg_list[13] == 0. */
17951 BFD_ASSERT ((insn_all_registers & (1 << 13))==0);
17952
17953 /* - reg_list[14] & reg_list[15] != 1. */
17954 BFD_ASSERT ((insn_all_registers & 0xC000) != 0xC000);
17955
17956 /* - if (wback==1) reg_list[rn] == 0. */
17957 BFD_ASSERT (!wback || !restore_rn);
17958
17959 /* - nb_registers > 8. */
17960 BFD_ASSERT (popcount (insn_all_registers) > 8);
17961
17962 /* At this point, LDMxx initial insn loads between 9 and 14 registers. */
17963
17964 /* In the following algorithm, we split this wide LDM using 2 LDM insns:
17965 - One with the 7 lowest registers (register mask 0x007F)
17966 This LDM will finally contain between 2 and 7 registers
17967 - One with the 7 highest registers (register mask 0xDF80)
17968 This ldm will finally contain between 2 and 7 registers. */
17969 insn_low_registers = insn_all_registers & 0x007F;
17970 insn_high_registers = insn_all_registers & 0xDF80;
17971
17972 /* A spare register may be needed during this veneer to temporarily
17973 handle the base register. This register will be restored with the
17974 last LDM operation.
17975 The usable register may be any general purpose register (that
17976 excludes PC, SP, LR : register mask is 0x1FFF). */
17977 usable_register_mask = 0x1FFF;
17978
17979 /* Generate the stub function. */
17980 if (wback)
17981 {
17982 /* LDMIA Rn!, {R-low-register-list} : (Encoding T2). */
17983 current_stub_contents =
17984 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
17985 create_instruction_ldmia
17986 (rn, /*wback=*/1, insn_low_registers));
17987
17988 /* LDMIA Rn!, {R-high-register-list} : (Encoding T2). */
17989 current_stub_contents =
17990 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
17991 create_instruction_ldmia
17992 (rn, /*wback=*/1, insn_high_registers));
17993 if (!restore_pc)
17994 {
17995 /* B initial_insn_addr+4. */
17996 current_stub_contents =
17997 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
17998 create_instruction_branch_absolute
82188b29 17999 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 18000 }
18001 }
18002 else /* if (!wback). */
18003 {
18004 ri = rn;
18005
18006 /* If Rn is not part of the high-register-list, move it there. */
18007 if (!(insn_high_registers & (1 << rn)))
18008 {
18009 /* Choose a Ri in the high-register-list that will be restored. */
18010 ri = ctz (insn_high_registers & usable_register_mask & ~(1 << rn));
18011
18012 /* MOV Ri, Rn. */
18013 current_stub_contents =
18014 push_thumb2_insn16 (htab, output_bfd, current_stub_contents,
18015 create_instruction_mov (ri, rn));
18016 }
18017
18018 /* LDMIA Ri!, {R-low-register-list} : (Encoding T2). */
18019 current_stub_contents =
18020 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18021 create_instruction_ldmia
18022 (ri, /*wback=*/1, insn_low_registers));
18023
18024 /* LDMIA Ri, {R-high-register-list} : (Encoding T2). */
18025 current_stub_contents =
18026 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18027 create_instruction_ldmia
18028 (ri, /*wback=*/0, insn_high_registers));
18029
18030 if (!restore_pc)
18031 {
18032 /* B initial_insn_addr+4. */
18033 current_stub_contents =
18034 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18035 create_instruction_branch_absolute
82188b29 18036 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 18037 }
18038 }
18039
18040 /* Fill the remaining of the stub with deterministic contents. */
18041 current_stub_contents =
18042 stm32l4xx_fill_stub_udf (htab, output_bfd,
18043 base_stub_contents, current_stub_contents,
18044 base_stub_contents +
18045 STM32L4XX_ERRATUM_LDM_VENEER_SIZE);
18046}
18047
18048static void
18049stm32l4xx_create_replacing_stub_ldmdb (struct elf32_arm_link_hash_table * htab,
18050 bfd * output_bfd,
18051 const insn32 initial_insn,
18052 const bfd_byte *const initial_insn_addr,
18053 bfd_byte *const base_stub_contents)
18054{
18055 int wback = (initial_insn & 0x00200000) >> 21;
18056 int ri, rn = (initial_insn & 0x000f0000) >> 16;
18057 int insn_all_registers = initial_insn & 0x0000ffff;
18058 int insn_low_registers, insn_high_registers;
18059 int usable_register_mask;
18060 int restore_pc = (insn_all_registers & (1 << 15)) ? 1 : 0;
18061 int restore_rn = (insn_all_registers & (1 << rn)) ? 1 : 0;
18062 int nb_registers = popcount (insn_all_registers);
18063 bfd_byte *current_stub_contents = base_stub_contents;
18064
18065 BFD_ASSERT (is_thumb2_ldmdb (initial_insn));
18066
18067 /* In BFD_ARM_STM32L4XX_FIX_ALL mode we may have to deal with
18068 smaller than 8 registers load sequences that do not cause the
18069 hardware issue. */
18070 if (nb_registers <= 8)
18071 {
18072 /* UNTOUCHED : LDMIA Rn{!}, {R-all-register-list}. */
18073 current_stub_contents =
18074 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18075 initial_insn);
18076
18077 /* B initial_insn_addr+4. */
18078 current_stub_contents =
18079 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18080 create_instruction_branch_absolute
82188b29 18081 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 18082
18083 /* Fill the remaining of the stub with deterministic contents. */
18084 current_stub_contents =
18085 stm32l4xx_fill_stub_udf (htab, output_bfd,
18086 base_stub_contents, current_stub_contents,
18087 base_stub_contents +
18088 STM32L4XX_ERRATUM_LDM_VENEER_SIZE);
18089
18090 return;
18091 }
18092
18093 /* - reg_list[13] == 0. */
18094 BFD_ASSERT ((insn_all_registers & (1 << 13)) == 0);
18095
18096 /* - reg_list[14] & reg_list[15] != 1. */
18097 BFD_ASSERT ((insn_all_registers & 0xC000) != 0xC000);
18098
18099 /* - if (wback==1) reg_list[rn] == 0. */
18100 BFD_ASSERT (!wback || !restore_rn);
18101
18102 /* - nb_registers > 8. */
18103 BFD_ASSERT (popcount (insn_all_registers) > 8);
18104
18105 /* At this point, LDMxx initial insn loads between 9 and 14 registers. */
18106
18107 /* In the following algorithm, we split this wide LDM using 2 LDM insn:
18108 - One with the 7 lowest registers (register mask 0x007F)
18109 This LDM will finally contain between 2 and 7 registers
18110 - One with the 7 highest registers (register mask 0xDF80)
18111 This ldm will finally contain between 2 and 7 registers. */
18112 insn_low_registers = insn_all_registers & 0x007F;
18113 insn_high_registers = insn_all_registers & 0xDF80;
18114
18115 /* A spare register may be needed during this veneer to temporarily
18116 handle the base register. This register will be restored with
18117 the last LDM operation.
18118 The usable register may be any general purpose register (that excludes
18119 PC, SP, LR : register mask is 0x1FFF). */
18120 usable_register_mask = 0x1FFF;
18121
18122 /* Generate the stub function. */
18123 if (!wback && !restore_pc && !restore_rn)
18124 {
18125 /* Choose a Ri in the low-register-list that will be restored. */
18126 ri = ctz (insn_low_registers & usable_register_mask & ~(1 << rn));
18127
18128 /* MOV Ri, Rn. */
18129 current_stub_contents =
18130 push_thumb2_insn16 (htab, output_bfd, current_stub_contents,
18131 create_instruction_mov (ri, rn));
18132
18133 /* LDMDB Ri!, {R-high-register-list}. */
18134 current_stub_contents =
18135 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18136 create_instruction_ldmdb
18137 (ri, /*wback=*/1, insn_high_registers));
18138
18139 /* LDMDB Ri, {R-low-register-list}. */
18140 current_stub_contents =
18141 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18142 create_instruction_ldmdb
18143 (ri, /*wback=*/0, insn_low_registers));
18144
18145 /* B initial_insn_addr+4. */
18146 current_stub_contents =
18147 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18148 create_instruction_branch_absolute
82188b29 18149 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 18150 }
18151 else if (wback && !restore_pc && !restore_rn)
18152 {
18153 /* LDMDB Rn!, {R-high-register-list}. */
18154 current_stub_contents =
18155 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18156 create_instruction_ldmdb
18157 (rn, /*wback=*/1, insn_high_registers));
18158
18159 /* LDMDB Rn!, {R-low-register-list}. */
18160 current_stub_contents =
18161 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18162 create_instruction_ldmdb
18163 (rn, /*wback=*/1, insn_low_registers));
18164
18165 /* B initial_insn_addr+4. */
18166 current_stub_contents =
18167 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18168 create_instruction_branch_absolute
82188b29 18169 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 18170 }
18171 else if (!wback && restore_pc && !restore_rn)
18172 {
18173 /* Choose a Ri in the high-register-list that will be restored. */
18174 ri = ctz (insn_high_registers & usable_register_mask & ~(1 << rn));
18175
18176 /* SUB Ri, Rn, #(4*nb_registers). */
18177 current_stub_contents =
18178 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18179 create_instruction_sub (ri, rn, (4 * nb_registers)));
18180
18181 /* LDMIA Ri!, {R-low-register-list}. */
18182 current_stub_contents =
18183 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18184 create_instruction_ldmia
18185 (ri, /*wback=*/1, insn_low_registers));
18186
18187 /* LDMIA Ri, {R-high-register-list}. */
18188 current_stub_contents =
18189 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18190 create_instruction_ldmia
18191 (ri, /*wback=*/0, insn_high_registers));
18192 }
18193 else if (wback && restore_pc && !restore_rn)
18194 {
18195 /* Choose a Ri in the high-register-list that will be restored. */
18196 ri = ctz (insn_high_registers & usable_register_mask & ~(1 << rn));
18197
18198 /* SUB Rn, Rn, #(4*nb_registers) */
18199 current_stub_contents =
18200 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18201 create_instruction_sub (rn, rn, (4 * nb_registers)));
18202
18203 /* MOV Ri, Rn. */
18204 current_stub_contents =
18205 push_thumb2_insn16 (htab, output_bfd, current_stub_contents,
18206 create_instruction_mov (ri, rn));
18207
18208 /* LDMIA Ri!, {R-low-register-list}. */
18209 current_stub_contents =
18210 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18211 create_instruction_ldmia
18212 (ri, /*wback=*/1, insn_low_registers));
18213
18214 /* LDMIA Ri, {R-high-register-list}. */
18215 current_stub_contents =
18216 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18217 create_instruction_ldmia
18218 (ri, /*wback=*/0, insn_high_registers));
18219 }
18220 else if (!wback && !restore_pc && restore_rn)
18221 {
18222 ri = rn;
18223 if (!(insn_low_registers & (1 << rn)))
18224 {
18225 /* Choose a Ri in the low-register-list that will be restored. */
18226 ri = ctz (insn_low_registers & usable_register_mask & ~(1 << rn));
18227
18228 /* MOV Ri, Rn. */
18229 current_stub_contents =
18230 push_thumb2_insn16 (htab, output_bfd, current_stub_contents,
18231 create_instruction_mov (ri, rn));
18232 }
18233
18234 /* LDMDB Ri!, {R-high-register-list}. */
18235 current_stub_contents =
18236 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18237 create_instruction_ldmdb
18238 (ri, /*wback=*/1, insn_high_registers));
18239
18240 /* LDMDB Ri, {R-low-register-list}. */
18241 current_stub_contents =
18242 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18243 create_instruction_ldmdb
18244 (ri, /*wback=*/0, insn_low_registers));
18245
18246 /* B initial_insn_addr+4. */
18247 current_stub_contents =
18248 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18249 create_instruction_branch_absolute
82188b29 18250 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 18251 }
18252 else if (!wback && restore_pc && restore_rn)
18253 {
18254 ri = rn;
18255 if (!(insn_high_registers & (1 << rn)))
18256 {
18257 /* Choose a Ri in the high-register-list that will be restored. */
18258 ri = ctz (insn_high_registers & usable_register_mask & ~(1 << rn));
18259 }
18260
18261 /* SUB Ri, Rn, #(4*nb_registers). */
18262 current_stub_contents =
18263 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18264 create_instruction_sub (ri, rn, (4 * nb_registers)));
18265
18266 /* LDMIA Ri!, {R-low-register-list}. */
18267 current_stub_contents =
18268 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18269 create_instruction_ldmia
18270 (ri, /*wback=*/1, insn_low_registers));
18271
18272 /* LDMIA Ri, {R-high-register-list}. */
18273 current_stub_contents =
18274 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18275 create_instruction_ldmia
18276 (ri, /*wback=*/0, insn_high_registers));
18277 }
18278 else if (wback && restore_rn)
18279 {
18280 /* The assembler should not have accepted to encode this. */
18281 BFD_ASSERT (0 && "Cannot patch an instruction that has an "
18282 "undefined behavior.\n");
18283 }
18284
18285 /* Fill the remaining of the stub with deterministic contents. */
18286 current_stub_contents =
18287 stm32l4xx_fill_stub_udf (htab, output_bfd,
18288 base_stub_contents, current_stub_contents,
18289 base_stub_contents +
18290 STM32L4XX_ERRATUM_LDM_VENEER_SIZE);
18291
18292}
18293
18294static void
18295stm32l4xx_create_replacing_stub_vldm (struct elf32_arm_link_hash_table * htab,
18296 bfd * output_bfd,
18297 const insn32 initial_insn,
18298 const bfd_byte *const initial_insn_addr,
18299 bfd_byte *const base_stub_contents)
18300{
9239bbd3 18301 int num_words = ((unsigned int) initial_insn << 24) >> 24;
a504d23a
LA		 18302 bfd_byte *current_stub_contents = base_stub_contents;
18303
18304 BFD_ASSERT (is_thumb2_vldm (initial_insn));
18305
18306 /* In BFD_ARM_STM32L4XX_FIX_ALL mode we may have to deal with
9239bbd3 18307 smaller than 8 words load sequences that do not cause the
a504d23a 18308 hardware issue. */
9239bbd3 18309 if (num_words <= 8)
a504d23a
LA		 18310 {
18311 /* Untouched instruction. */
18312 current_stub_contents =
18313 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18314 initial_insn);
18315
18316 /* B initial_insn_addr+4. */
18317 current_stub_contents =
18318 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18319 create_instruction_branch_absolute
82188b29 18320 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 18321 }
18322 else
18323 {
9eaff861 18324 bfd_boolean is_dp = /* DP encoding. */
9239bbd3 18325 (initial_insn & 0xfe100f00) == 0xec100b00;
a504d23a
LA		 18326 bfd_boolean is_ia_nobang = /* (IA without !). */
18327 (((initial_insn << 7) >> 28) & 0xd) == 0x4;
18328 bfd_boolean is_ia_bang = /* (IA with !) - includes VPOP. */
18329 (((initial_insn << 7) >> 28) & 0xd) == 0x5;
18330 bfd_boolean is_db_bang = /* (DB with !). */
18331 (((initial_insn << 7) >> 28) & 0xd) == 0x9;
9239bbd3 18332 int base_reg = ((unsigned int) initial_insn << 12) >> 28;
a504d23a 18333 /* d = UInt (Vd:D);. */
9239bbd3 18334 int first_reg = ((((unsigned int) initial_insn << 16) >> 28) << 1)
a504d23a
LA		 18335 | (((unsigned int)initial_insn << 9) >> 31);
18336
9239bbd3
CM		 18337 /* Compute the number of 8-words chunks needed to split. */
18338 int chunks = (num_words % 8) ? (num_words / 8 + 1) : (num_words / 8);
a504d23a
LA		 18339 int chunk;
18340
18341 /* The test coverage has been done assuming the following
18342 hypothesis that exactly one of the previous is_ predicates is
18343 true. */
9239bbd3
CM		 18344 BFD_ASSERT ( (is_ia_nobang ^ is_ia_bang ^ is_db_bang)
18345 && !(is_ia_nobang & is_ia_bang & is_db_bang));
a504d23a 18346
9239bbd3 18347 /* We treat the cutting of the words in one pass for all
a504d23a
LA		 18348 cases, then we emit the adjustments:
18349
18350 vldm rx, {...}
18351 -> vldm rx!, {8_words_or_less} for each needed 8_word
18352 -> sub rx, rx, #size (list)
18353
18354 vldm rx!, {...}
18355 -> vldm rx!, {8_words_or_less} for each needed 8_word
18356 This also handles vpop instruction (when rx is sp)
18357
18358 vldmd rx!, {...}
18359 -> vldmb rx!, {8_words_or_less} for each needed 8_word. */
9239bbd3 18360 for (chunk = 0; chunk < chunks; ++chunk)
a504d23a 18361 {
9239bbd3
CM		 18362 bfd_vma new_insn = 0;
18363
a504d23a
LA		 18364 if (is_ia_nobang || is_ia_bang)
18365 {
9239bbd3
CM		 18366 new_insn = create_instruction_vldmia
18367 (base_reg,
18368 is_dp,
18369 /*wback= . */1,
18370 chunks - (chunk + 1) ?
18371 8 : num_words - chunk * 8,
18372 first_reg + chunk * 8);
a504d23a
LA		 18373 }
18374 else if (is_db_bang)
18375 {
9239bbd3
CM		 18376 new_insn = create_instruction_vldmdb
18377 (base_reg,
18378 is_dp,
18379 chunks - (chunk + 1) ?
18380 8 : num_words - chunk * 8,
18381 first_reg + chunk * 8);
a504d23a 18382 }
9239bbd3
CM		 18383
18384 if (new_insn)
18385 current_stub_contents =
18386 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18387 new_insn);
a504d23a
LA		 18388 }
18389
18390 /* Only this case requires the base register compensation
18391 subtract. */
18392 if (is_ia_nobang)
18393 {
18394 current_stub_contents =
18395 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18396 create_instruction_sub
9239bbd3 18397 (base_reg, base_reg, 4*num_words));
a504d23a
LA		 18398 }
18399
18400 /* B initial_insn_addr+4. */
18401 current_stub_contents =
18402 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18403 create_instruction_branch_absolute
82188b29 18404 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 18405 }
18406
18407 /* Fill the remaining of the stub with deterministic contents. */
18408 current_stub_contents =
18409 stm32l4xx_fill_stub_udf (htab, output_bfd,
18410 base_stub_contents, current_stub_contents,
18411 base_stub_contents +
18412 STM32L4XX_ERRATUM_VLDM_VENEER_SIZE);
18413}
18414
18415static void
18416stm32l4xx_create_replacing_stub (struct elf32_arm_link_hash_table * htab,
18417 bfd * output_bfd,
18418 const insn32 wrong_insn,
18419 const bfd_byte *const wrong_insn_addr,
18420 bfd_byte *const stub_contents)
18421{
18422 if (is_thumb2_ldmia (wrong_insn))
18423 stm32l4xx_create_replacing_stub_ldmia (htab, output_bfd,
18424 wrong_insn, wrong_insn_addr,
18425 stub_contents);
18426 else if (is_thumb2_ldmdb (wrong_insn))
18427 stm32l4xx_create_replacing_stub_ldmdb (htab, output_bfd,
18428 wrong_insn, wrong_insn_addr,
18429 stub_contents);
18430 else if (is_thumb2_vldm (wrong_insn))
18431 stm32l4xx_create_replacing_stub_vldm (htab, output_bfd,
18432 wrong_insn, wrong_insn_addr,
18433 stub_contents);
18434}
18435
18436/* End of stm32l4xx work-around. */
18437
18438
e489d0ae
PB		 18439/* Do code byteswapping. Return FALSE afterwards so that the section is
18440 written out as normal. */
18441
18442static bfd_boolean
c7b8f16e 18443elf32_arm_write_section (bfd *output_bfd,
8029a119
NC		 18444 struct bfd_link_info *link_info,
18445 asection *sec,
e489d0ae
PB		 18446 bfd_byte *contents)
18447{
48229727 18448 unsigned int mapcount, errcount;
8e3de13a 18449 _arm_elf_section_data *arm_data;
c7b8f16e 18450 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (link_info);
e489d0ae 18451 elf32_arm_section_map *map;
c7b8f16e 18452 elf32_vfp11_erratum_list *errnode;
a504d23a 18453 elf32_stm32l4xx_erratum_list *stm32l4xx_errnode;
e489d0ae
PB		 18454 bfd_vma ptr;
18455 bfd_vma end;
c7b8f16e 18456 bfd_vma offset = sec->output_section->vma + sec->output_offset;
e489d0ae 18457 bfd_byte tmp;
48229727 18458 unsigned int i;
57e8b36a 18459
4dfe6ac6
NC		 18460 if (globals == NULL)
18461 return FALSE;
18462
8e3de13a
NC		 18463 /* If this section has not been allocated an _arm_elf_section_data
18464 structure then we cannot record anything. */
18465 arm_data = get_arm_elf_section_data (sec);
18466 if (arm_data == NULL)
18467 return FALSE;
18468
18469 mapcount = arm_data->mapcount;
18470 map = arm_data->map;
c7b8f16e
JB		 18471 errcount = arm_data->erratumcount;
18472
18473 if (errcount != 0)
18474 {
18475 unsigned int endianflip = bfd_big_endian (output_bfd) ? 3 : 0;
18476
18477 for (errnode = arm_data->erratumlist; errnode != 0;
99059e56
RM		 18478 errnode = errnode->next)
18479 {
18480 bfd_vma target = errnode->vma - offset;
18481
18482 switch (errnode->type)
18483 {
18484 case VFP11_ERRATUM_BRANCH_TO_ARM_VENEER:
18485 {
18486 bfd_vma branch_to_veneer;
18487 /* Original condition code of instruction, plus bit mask for
18488 ARM B instruction. */
18489 unsigned int insn = (errnode->u.b.vfp_insn & 0xf0000000)
18490 | 0x0a000000;
c7b8f16e
JB		 18491
18492 /* The instruction is before the label. */
91d6fa6a 18493 target -= 4;
c7b8f16e
JB		 18494
18495 /* Above offset included in -4 below. */
18496 branch_to_veneer = errnode->u.b.veneer->vma
99059e56 18497 - errnode->vma - 4;
c7b8f16e
JB		 18498
18499 if ((signed) branch_to_veneer < -(1 << 25)
18500 || (signed) branch_to_veneer >= (1 << 25))
4eca0228
AM		 18501 _bfd_error_handler (_("%B: error: VFP11 veneer out of "
18502 "range"), output_bfd);
c7b8f16e 18503
99059e56
RM		 18504 insn |= (branch_to_veneer >> 2) & 0xffffff;
18505 contents[endianflip ^ target] = insn & 0xff;
18506 contents[endianflip ^ (target + 1)] = (insn >> 8) & 0xff;
18507 contents[endianflip ^ (target + 2)] = (insn >> 16) & 0xff;
18508 contents[endianflip ^ (target + 3)] = (insn >> 24) & 0xff;
18509 }
18510 break;
c7b8f16e
JB		 18511
18512 case VFP11_ERRATUM_ARM_VENEER:
99059e56
RM		 18513 {
18514 bfd_vma branch_from_veneer;
18515 unsigned int insn;
c7b8f16e 18516
99059e56
RM		 18517 /* Take size of veneer into account. */
18518 branch_from_veneer = errnode->u.v.branch->vma
18519 - errnode->vma - 12;
c7b8f16e
JB		 18520
18521 if ((signed) branch_from_veneer < -(1 << 25)
18522 || (signed) branch_from_veneer >= (1 << 25))
4eca0228
AM		 18523 _bfd_error_handler (_("%B: error: VFP11 veneer out of "
18524 "range"), output_bfd);
c7b8f16e 18525
99059e56
RM		 18526 /* Original instruction. */
18527 insn = errnode->u.v.branch->u.b.vfp_insn;
18528 contents[endianflip ^ target] = insn & 0xff;
18529 contents[endianflip ^ (target + 1)] = (insn >> 8) & 0xff;
18530 contents[endianflip ^ (target + 2)] = (insn >> 16) & 0xff;
18531 contents[endianflip ^ (target + 3)] = (insn >> 24) & 0xff;
18532
18533 /* Branch back to insn after original insn. */
18534 insn = 0xea000000 | ((branch_from_veneer >> 2) & 0xffffff);
18535 contents[endianflip ^ (target + 4)] = insn & 0xff;
18536 contents[endianflip ^ (target + 5)] = (insn >> 8) & 0xff;
18537 contents[endianflip ^ (target + 6)] = (insn >> 16) & 0xff;
18538 contents[endianflip ^ (target + 7)] = (insn >> 24) & 0xff;
18539 }
18540 break;
c7b8f16e 18541
99059e56
RM		 18542 default:
18543 abort ();
18544 }
18545 }
c7b8f16e 18546 }
e489d0ae 18547
a504d23a
LA		 18548 if (arm_data->stm32l4xx_erratumcount != 0)
18549 {
18550 for (stm32l4xx_errnode = arm_data->stm32l4xx_erratumlist;
18551 stm32l4xx_errnode != 0;
18552 stm32l4xx_errnode = stm32l4xx_errnode->next)
18553 {
18554 bfd_vma target = stm32l4xx_errnode->vma - offset;
18555
18556 switch (stm32l4xx_errnode->type)
18557 {
18558 case STM32L4XX_ERRATUM_BRANCH_TO_VENEER:
18559 {
18560 unsigned int insn;
18561 bfd_vma branch_to_veneer =
18562 stm32l4xx_errnode->u.b.veneer->vma - stm32l4xx_errnode->vma;
18563
18564 if ((signed) branch_to_veneer < -(1 << 24)
18565 || (signed) branch_to_veneer >= (1 << 24))
18566 {
18567 bfd_vma out_of_range =
18568 ((signed) branch_to_veneer < -(1 << 24)) ?
18569 - branch_to_veneer - (1 << 24) :
18570 ((signed) branch_to_veneer >= (1 << 24)) ?
18571 branch_to_veneer - (1 << 24) : 0;
18572
4eca0228 18573 _bfd_error_handler
a504d23a 18574 (_("%B(%#x): error: Cannot create STM32L4XX veneer. "
eee926f2 18575 "Jump out of range by %ld bytes. "
a504d23a
LA		 18576 "Cannot encode branch instruction. "),
18577 output_bfd,
eee926f2 18578 (long) (stm32l4xx_errnode->vma - 4),
a504d23a
LA		 18579 out_of_range);
18580 continue;
18581 }
18582
18583 insn = create_instruction_branch_absolute
82188b29 18584 (stm32l4xx_errnode->u.b.veneer->vma - stm32l4xx_errnode->vma);
a504d23a
LA		 18585
18586 /* The instruction is before the label. */
18587 target -= 4;
18588
18589 put_thumb2_insn (globals, output_bfd,
18590 (bfd_vma) insn, contents + target);
18591 }
18592 break;
18593
18594 case STM32L4XX_ERRATUM_VENEER:
18595 {
82188b29
NC		 18596 bfd_byte * veneer;
18597 bfd_byte * veneer_r;
a504d23a
LA		 18598 unsigned int insn;
18599
82188b29
NC		 18600 veneer = contents + target;
18601 veneer_r = veneer
18602 + stm32l4xx_errnode->u.b.veneer->vma
18603 - stm32l4xx_errnode->vma - 4;
a504d23a
LA		 18604
18605 if ((signed) (veneer_r - veneer -
18606 STM32L4XX_ERRATUM_VLDM_VENEER_SIZE >
18607 STM32L4XX_ERRATUM_LDM_VENEER_SIZE ?
18608 STM32L4XX_ERRATUM_VLDM_VENEER_SIZE :
18609 STM32L4XX_ERRATUM_LDM_VENEER_SIZE) < -(1 << 24)
18610 || (signed) (veneer_r - veneer) >= (1 << 24))
18611 {
4eca0228
AM		 18612 _bfd_error_handler (_("%B: error: Cannot create STM32L4XX "
18613 "veneer."), output_bfd);
a504d23a
LA		 18614 continue;
18615 }
18616
18617 /* Original instruction. */
18618 insn = stm32l4xx_errnode->u.v.branch->u.b.insn;
18619
18620 stm32l4xx_create_replacing_stub
18621 (globals, output_bfd, insn, (void*)veneer_r, (void*)veneer);
18622 }
18623 break;
18624
18625 default:
18626 abort ();
18627 }
18628 }
18629 }
18630
2468f9c9
PB		 18631 if (arm_data->elf.this_hdr.sh_type == SHT_ARM_EXIDX)
18632 {
18633 arm_unwind_table_edit *edit_node
99059e56 18634 = arm_data->u.exidx.unwind_edit_list;
2468f9c9 18635 /* Now, sec->size is the size of the section we will write. The original
99059e56 18636 size (before we merged duplicate entries and inserted EXIDX_CANTUNWIND
2468f9c9
PB		 18637 markers) was sec->rawsize. (This isn't the case if we perform no
18638 edits, then rawsize will be zero and we should use size). */
21d799b5 18639 bfd_byte *edited_contents = (bfd_byte *) bfd_malloc (sec->size);
2468f9c9
PB		 18640 unsigned int input_size = sec->rawsize ? sec->rawsize : sec->size;
18641 unsigned int in_index, out_index;
18642 bfd_vma add_to_offsets = 0;
18643
18644 for (in_index = 0, out_index = 0; in_index * 8 < input_size || edit_node;)
99059e56 18645 {
2468f9c9
PB		 18646 if (edit_node)
18647 {
18648 unsigned int edit_index = edit_node->index;
b38cadfb 18649
2468f9c9 18650 if (in_index < edit_index && in_index * 8 < input_size)
99059e56 18651 {
2468f9c9
PB		 18652 copy_exidx_entry (output_bfd, edited_contents + out_index * 8,
18653 contents + in_index * 8, add_to_offsets);
18654 out_index++;
18655 in_index++;
18656 }
18657 else if (in_index == edit_index
18658 || (in_index * 8 >= input_size
18659 && edit_index == UINT_MAX))
99059e56 18660 {
2468f9c9
PB		 18661 switch (edit_node->type)
18662 {
18663 case DELETE_EXIDX_ENTRY:
18664 in_index++;
18665 add_to_offsets += 8;
18666 break;
b38cadfb 18667
2468f9c9
PB		 18668 case INSERT_EXIDX_CANTUNWIND_AT_END:
18669 {
99059e56 18670 asection *text_sec = edit_node->linked_section;
2468f9c9
PB		 18671 bfd_vma text_offset = text_sec->output_section->vma
18672 + text_sec->output_offset
18673 + text_sec->size;
18674 bfd_vma exidx_offset = offset + out_index * 8;
99059e56 18675 unsigned long prel31_offset;
2468f9c9
PB		 18676
18677 /* Note: this is meant to be equivalent to an
18678 R_ARM_PREL31 relocation. These synthetic
18679 EXIDX_CANTUNWIND markers are not relocated by the
18680 usual BFD method. */
18681 prel31_offset = (text_offset - exidx_offset)
18682 & 0x7ffffffful;
491d01d3
YU		 18683 if (bfd_link_relocatable (link_info))
18684 {
18685 /* Here relocation for new EXIDX_CANTUNWIND is
18686 created, so there is no need to
18687 adjust offset by hand. */
18688 prel31_offset = text_sec->output_offset
18689 + text_sec->size;
491d01d3 18690 }
2468f9c9
PB		 18691
18692 /* First address we can't unwind. */
18693 bfd_put_32 (output_bfd, prel31_offset,
18694 &edited_contents[out_index * 8]);
18695
18696 /* Code for EXIDX_CANTUNWIND. */
18697 bfd_put_32 (output_bfd, 0x1,
18698 &edited_contents[out_index * 8 + 4]);
18699
18700 out_index++;
18701 add_to_offsets -= 8;
18702 }
18703 break;
18704 }
b38cadfb 18705
2468f9c9
PB		 18706 edit_node = edit_node->next;
18707 }
18708 }
18709 else
18710 {
18711 /* No more edits, copy remaining entries verbatim. */
18712 copy_exidx_entry (output_bfd, edited_contents + out_index * 8,
18713 contents + in_index * 8, add_to_offsets);
18714 out_index++;
18715 in_index++;
18716 }
18717 }
18718
18719 if (!(sec->flags & SEC_EXCLUDE) && !(sec->flags & SEC_NEVER_LOAD))
18720 bfd_set_section_contents (output_bfd, sec->output_section,
18721 edited_contents,
18722 (file_ptr) sec->output_offset, sec->size);
18723
18724 return TRUE;
18725 }
18726
48229727
JB		 18727 /* Fix code to point to Cortex-A8 erratum stubs. */
18728 if (globals->fix_cortex_a8)
18729 {
18730 struct a8_branch_to_stub_data data;
18731
18732 data.writing_section = sec;
18733 data.contents = contents;
18734
a504d23a
LA		 18735 bfd_hash_traverse (& globals->stub_hash_table, make_branch_to_a8_stub,
18736 & data);
48229727
JB		 18737 }
18738
e489d0ae
PB		 18739 if (mapcount == 0)
18740 return FALSE;
18741
c7b8f16e 18742 if (globals->byteswap_code)
e489d0ae 18743 {
c7b8f16e 18744 qsort (map, mapcount, sizeof (* map), elf32_arm_compare_mapping);
57e8b36a 18745
c7b8f16e
JB		 18746 ptr = map[0].vma;
18747 for (i = 0; i < mapcount; i++)
99059e56
RM		 18748 {
18749 if (i == mapcount - 1)
c7b8f16e 18750 end = sec->size;
99059e56
RM		 18751 else
18752 end = map[i + 1].vma;
e489d0ae 18753
99059e56 18754 switch (map[i].type)
e489d0ae 18755 {
c7b8f16e
JB		 18756 case 'a':
18757 /* Byte swap code words. */
18758 while (ptr + 3 < end)
99059e56
RM		 18759 {
18760 tmp = contents[ptr];
18761 contents[ptr] = contents[ptr + 3];
18762 contents[ptr + 3] = tmp;
18763 tmp = contents[ptr + 1];
18764 contents[ptr + 1] = contents[ptr + 2];
18765 contents[ptr + 2] = tmp;
18766 ptr += 4;
18767 }
c7b8f16e 18768 break;
e489d0ae 18769
c7b8f16e
JB		 18770 case 't':
18771 /* Byte swap code halfwords. */
18772 while (ptr + 1 < end)
99059e56
RM		 18773 {
18774 tmp = contents[ptr];
18775 contents[ptr] = contents[ptr + 1];
18776 contents[ptr + 1] = tmp;
18777 ptr += 2;
18778 }
c7b8f16e
JB		 18779 break;
18780
18781 case 'd':
18782 /* Leave data alone. */
18783 break;
18784 }
99059e56
RM		 18785 ptr = end;
18786 }
e489d0ae 18787 }
8e3de13a 18788
93204d3a 18789 free (map);
47b2e99c 18790 arm_data->mapcount = -1;
c7b8f16e 18791 arm_data->mapsize = 0;
8e3de13a 18792 arm_data->map = NULL;
8e3de13a 18793
e489d0ae
PB		 18794 return FALSE;
18795}
18796
0beaef2b
PB		 18797/* Mangle thumb function symbols as we read them in. */
18798
8384fb8f 18799static bfd_boolean
0beaef2b
PB		 18800elf32_arm_swap_symbol_in (bfd * abfd,
18801 const void *psrc,
18802 const void *pshn,
18803 Elf_Internal_Sym *dst)
18804{
4ba2ef8f
TP		 18805 Elf_Internal_Shdr *symtab_hdr;
18806 const char *name = NULL;
18807
8384fb8f
AM		 18808 if (!bfd_elf32_swap_symbol_in (abfd, psrc, pshn, dst))
18809 return FALSE;
39d911fc 18810 dst->st_target_internal = 0;
0beaef2b
PB		 18811
18812 /* New EABI objects mark thumb function symbols by setting the low bit of
35fc36a8 18813 the address. */
63e1a0fc
PB		 18814 if (ELF_ST_TYPE (dst->st_info) == STT_FUNC
18815 || ELF_ST_TYPE (dst->st_info) == STT_GNU_IFUNC)
0beaef2b 18816 {
63e1a0fc
PB		 18817 if (dst->st_value & 1)
18818 {
18819 dst->st_value &= ~(bfd_vma) 1;
39d911fc
TP		 18820 ARM_SET_SYM_BRANCH_TYPE (dst->st_target_internal,
18821 ST_BRANCH_TO_THUMB);
63e1a0fc
PB		 18822 }
18823 else
39d911fc 18824 ARM_SET_SYM_BRANCH_TYPE (dst->st_target_internal, ST_BRANCH_TO_ARM);
35fc36a8
RS		 18825 }
18826 else if (ELF_ST_TYPE (dst->st_info) == STT_ARM_TFUNC)
18827 {
18828 dst->st_info = ELF_ST_INFO (ELF_ST_BIND (dst->st_info), STT_FUNC);
39d911fc 18829 ARM_SET_SYM_BRANCH_TYPE (dst->st_target_internal, ST_BRANCH_TO_THUMB);
0beaef2b 18830 }
35fc36a8 18831 else if (ELF_ST_TYPE (dst->st_info) == STT_SECTION)
39d911fc 18832 ARM_SET_SYM_BRANCH_TYPE (dst->st_target_internal, ST_BRANCH_LONG);
35fc36a8 18833 else
39d911fc 18834 ARM_SET_SYM_BRANCH_TYPE (dst->st_target_internal, ST_BRANCH_UNKNOWN);
35fc36a8 18835
4ba2ef8f
TP		 18836 /* Mark CMSE special symbols. */
18837 symtab_hdr = & elf_symtab_hdr (abfd);
18838 if (symtab_hdr->sh_size)
18839 name = bfd_elf_sym_name (abfd, symtab_hdr, dst, NULL);
18840 if (name && CONST_STRNEQ (name, CMSE_PREFIX))
18841 ARM_SET_SYM_CMSE_SPCL (dst->st_target_internal);
18842
8384fb8f 18843 return TRUE;
0beaef2b
PB		 18844}
18845
18846
18847/* Mangle thumb function symbols as we write them out. */
18848
18849static void
18850elf32_arm_swap_symbol_out (bfd *abfd,
18851 const Elf_Internal_Sym *src,
18852 void *cdst,
18853 void *shndx)
18854{
18855 Elf_Internal_Sym newsym;
18856
18857 /* We convert STT_ARM_TFUNC symbols into STT_FUNC with the low bit
18858 of the address set, as per the new EABI. We do this unconditionally
18859 because objcopy does not set the elf header flags until after
18860 it writes out the symbol table. */
39d911fc 18861 if (ARM_GET_SYM_BRANCH_TYPE (src->st_target_internal) == ST_BRANCH_TO_THUMB)
0beaef2b
PB		 18862 {
18863 newsym = *src;
34e77a92
RS		 18864 if (ELF_ST_TYPE (src->st_info) != STT_GNU_IFUNC)
18865 newsym.st_info = ELF_ST_INFO (ELF_ST_BIND (src->st_info), STT_FUNC);
0fa3dcad 18866 if (newsym.st_shndx != SHN_UNDEF)
99059e56
RM		 18867 {
18868 /* Do this only for defined symbols. At link type, the static
18869 linker will simulate the work of dynamic linker of resolving
18870 symbols and will carry over the thumbness of found symbols to
18871 the output symbol table. It's not clear how it happens, but
18872 the thumbness of undefined symbols can well be different at
18873 runtime, and writing '1' for them will be confusing for users
18874 and possibly for dynamic linker itself.
18875 */
18876 newsym.st_value |= 1;
18877 }
906e58ca 18878
0beaef2b
PB		 18879 src = &newsym;
18880 }
18881 bfd_elf32_swap_symbol_out (abfd, src, cdst, shndx);
18882}
18883
b294bdf8
MM		 18884/* Add the PT_ARM_EXIDX program header. */
18885
18886static bfd_boolean
906e58ca 18887elf32_arm_modify_segment_map (bfd *abfd,
b294bdf8
MM		 18888 struct bfd_link_info *info ATTRIBUTE_UNUSED)
18889{
18890 struct elf_segment_map *m;
18891 asection *sec;
18892
18893 sec = bfd_get_section_by_name (abfd, ".ARM.exidx");
18894 if (sec != NULL && (sec->flags & SEC_LOAD) != 0)
18895 {
18896 /* If there is already a PT_ARM_EXIDX header, then we do not
18897 want to add another one. This situation arises when running
18898 "strip"; the input binary already has the header. */
12bd6957 18899 m = elf_seg_map (abfd);
b294bdf8
MM		 18900 while (m && m->p_type != PT_ARM_EXIDX)
18901 m = m->next;
18902 if (!m)
18903 {
21d799b5 18904 m = (struct elf_segment_map *)
99059e56 18905 bfd_zalloc (abfd, sizeof (struct elf_segment_map));
b294bdf8
MM		 18906 if (m == NULL)
18907 return FALSE;
18908 m->p_type = PT_ARM_EXIDX;
18909 m->count = 1;
18910 m->sections[0] = sec;
18911
12bd6957
AM		 18912 m->next = elf_seg_map (abfd);
18913 elf_seg_map (abfd) = m;
b294bdf8
MM		 18914 }
18915 }
18916
18917 return TRUE;
18918}
18919
18920/* We may add a PT_ARM_EXIDX program header. */
18921
18922static int
a6b96beb
AM		 18923elf32_arm_additional_program_headers (bfd *abfd,
18924 struct bfd_link_info *info ATTRIBUTE_UNUSED)
b294bdf8
MM		 18925{
18926 asection *sec;
18927
18928 sec = bfd_get_section_by_name (abfd, ".ARM.exidx");
18929 if (sec != NULL && (sec->flags & SEC_LOAD) != 0)
18930 return 1;
18931 else
18932 return 0;
18933}
18934
34e77a92
RS		 18935/* Hook called by the linker routine which adds symbols from an object
18936 file. */
18937
18938static bfd_boolean
18939elf32_arm_add_symbol_hook (bfd *abfd, struct bfd_link_info *info,
18940 Elf_Internal_Sym *sym, const char **namep,
18941 flagword *flagsp, asection **secp, bfd_vma *valp)
18942{
a43942db 18943 if (ELF_ST_TYPE (sym->st_info) == STT_GNU_IFUNC
f1885d1e
AM		 18944 && (abfd->flags & DYNAMIC) == 0
18945 && bfd_get_flavour (info->output_bfd) == bfd_target_elf_flavour)
a43942db 18946 elf_tdata (info->output_bfd)->has_gnu_symbols |= elf_gnu_symbol_ifunc;
34e77a92 18947
c792917c
NC		 18948 if (elf32_arm_hash_table (info) == NULL)
18949 return FALSE;
18950
34e77a92
RS		 18951 if (elf32_arm_hash_table (info)->vxworks_p
18952 && !elf_vxworks_add_symbol_hook (abfd, info, sym, namep,
18953 flagsp, secp, valp))
18954 return FALSE;
18955
18956 return TRUE;
18957}
18958
0beaef2b 18959/* We use this to override swap_symbol_in and swap_symbol_out. */
906e58ca
NC		 18960const struct elf_size_info elf32_arm_size_info =
18961{
0beaef2b
PB		 18962 sizeof (Elf32_External_Ehdr),
18963 sizeof (Elf32_External_Phdr),
18964 sizeof (Elf32_External_Shdr),
18965 sizeof (Elf32_External_Rel),
18966 sizeof (Elf32_External_Rela),
18967 sizeof (Elf32_External_Sym),
18968 sizeof (Elf32_External_Dyn),
18969 sizeof (Elf_External_Note),
18970 4,
18971 1,
18972 32, 2,
18973 ELFCLASS32, EV_CURRENT,
18974 bfd_elf32_write_out_phdrs,
18975 bfd_elf32_write_shdrs_and_ehdr,
1489a3a0 18976 bfd_elf32_checksum_contents,
0beaef2b
PB		 18977 bfd_elf32_write_relocs,
18978 elf32_arm_swap_symbol_in,
18979 elf32_arm_swap_symbol_out,
18980 bfd_elf32_slurp_reloc_table,
18981 bfd_elf32_slurp_symbol_table,
18982 bfd_elf32_swap_dyn_in,
18983 bfd_elf32_swap_dyn_out,
18984 bfd_elf32_swap_reloc_in,
18985 bfd_elf32_swap_reloc_out,
18986 bfd_elf32_swap_reloca_in,
18987 bfd_elf32_swap_reloca_out
18988};
18989
685e70ae
VK		 18990static bfd_vma
18991read_code32 (const bfd *abfd, const bfd_byte *addr)
18992{
18993 /* V7 BE8 code is always little endian. */
18994 if ((elf_elfheader (abfd)->e_flags & EF_ARM_BE8) != 0)
18995 return bfd_getl32 (addr);
18996
18997 return bfd_get_32 (abfd, addr);
18998}
18999
19000static bfd_vma
19001read_code16 (const bfd *abfd, const bfd_byte *addr)
19002{
19003 /* V7 BE8 code is always little endian. */
19004 if ((elf_elfheader (abfd)->e_flags & EF_ARM_BE8) != 0)
19005 return bfd_getl16 (addr);
19006
19007 return bfd_get_16 (abfd, addr);
19008}
19009
6a631e86
YG		 19010/* Return size of plt0 entry starting at ADDR
19011 or (bfd_vma) -1 if size can not be determined. */
19012
19013static bfd_vma
19014elf32_arm_plt0_size (const bfd *abfd, const bfd_byte *addr)
19015{
19016 bfd_vma first_word;
19017 bfd_vma plt0_size;
19018
685e70ae 19019 first_word = read_code32 (abfd, addr);
6a631e86
YG		 19020
19021 if (first_word == elf32_arm_plt0_entry[0])
19022 plt0_size = 4 * ARRAY_SIZE (elf32_arm_plt0_entry);
19023 else if (first_word == elf32_thumb2_plt0_entry[0])
19024 plt0_size = 4 * ARRAY_SIZE (elf32_thumb2_plt0_entry);
19025 else
19026 /* We don't yet handle this PLT format. */
19027 return (bfd_vma) -1;
19028
19029 return plt0_size;
19030}
19031
19032/* Return size of plt entry starting at offset OFFSET
19033 of plt section located at address START
19034 or (bfd_vma) -1 if size can not be determined. */
19035
19036static bfd_vma
19037elf32_arm_plt_size (const bfd *abfd, const bfd_byte *start, bfd_vma offset)
19038{
19039 bfd_vma first_insn;
19040 bfd_vma plt_size = 0;
19041 const bfd_byte *addr = start + offset;
19042
19043 /* PLT entry size if fixed on Thumb-only platforms. */
685e70ae 19044 if (read_code32 (abfd, start) == elf32_thumb2_plt0_entry[0])
6a631e86
YG		 19045 return 4 * ARRAY_SIZE (elf32_thumb2_plt_entry);
19046
19047 /* Respect Thumb stub if necessary. */
685e70ae 19048 if (read_code16 (abfd, addr) == elf32_arm_plt_thumb_stub[0])
6a631e86
YG		 19049 {
19050 plt_size += 2 * ARRAY_SIZE(elf32_arm_plt_thumb_stub);
19051 }
19052
19053 /* Strip immediate from first add. */
685e70ae 19054 first_insn = read_code32 (abfd, addr + plt_size) & 0xffffff00;
6a631e86
YG		 19055
19056#ifdef FOUR_WORD_PLT
19057 if (first_insn == elf32_arm_plt_entry[0])
19058 plt_size += 4 * ARRAY_SIZE (elf32_arm_plt_entry);
19059#else
19060 if (first_insn == elf32_arm_plt_entry_long[0])
19061 plt_size += 4 * ARRAY_SIZE (elf32_arm_plt_entry_long);
19062 else if (first_insn == elf32_arm_plt_entry_short[0])
19063 plt_size += 4 * ARRAY_SIZE (elf32_arm_plt_entry_short);
19064#endif
19065 else
19066 /* We don't yet handle this PLT format. */
19067 return (bfd_vma) -1;
19068
19069 return plt_size;
19070}
19071
19072/* Implementation is shamelessly borrowed from _bfd_elf_get_synthetic_symtab. */
19073
19074static long
19075elf32_arm_get_synthetic_symtab (bfd *abfd,
19076 long symcount ATTRIBUTE_UNUSED,
19077 asymbol **syms ATTRIBUTE_UNUSED,
19078 long dynsymcount,
19079 asymbol **dynsyms,
19080 asymbol **ret)
19081{
19082 asection *relplt;
19083 asymbol *s;
19084 arelent *p;
19085 long count, i, n;
19086 size_t size;
19087 Elf_Internal_Shdr *hdr;
19088 char *names;
19089 asection *plt;
19090 bfd_vma offset;
19091 bfd_byte *data;
19092
19093 *ret = NULL;
19094
19095 if ((abfd->flags & (DYNAMIC | EXEC_P)) == 0)
19096 return 0;
19097
19098 if (dynsymcount <= 0)
19099 return 0;
19100
19101 relplt = bfd_get_section_by_name (abfd, ".rel.plt");
19102 if (relplt == NULL)
19103 return 0;
19104
19105 hdr = &elf_section_data (relplt)->this_hdr;
19106 if (hdr->sh_link != elf_dynsymtab (abfd)
19107 || (hdr->sh_type != SHT_REL && hdr->sh_type != SHT_RELA))
19108 return 0;
19109
19110 plt = bfd_get_section_by_name (abfd, ".plt");
19111 if (plt == NULL)
19112 return 0;
19113
19114 if (!elf32_arm_size_info.slurp_reloc_table (abfd, relplt, dynsyms, TRUE))
19115 return -1;
19116
19117 data = plt->contents;
19118 if (data == NULL)
19119 {
19120 if (!bfd_get_full_section_contents(abfd, (asection *) plt, &data) || data == NULL)
19121 return -1;
19122 bfd_cache_section_contents((asection *) plt, data);
19123 }
19124
19125 count = relplt->size / hdr->sh_entsize;
19126 size = count * sizeof (asymbol);
19127 p = relplt->relocation;
19128 for (i = 0; i < count; i++, p += elf32_arm_size_info.int_rels_per_ext_rel)
19129 {
19130 size += strlen ((*p->sym_ptr_ptr)->name) + sizeof ("@plt");
19131 if (p->addend != 0)
19132 size += sizeof ("+0x") - 1 + 8;
19133 }
19134
19135 s = *ret = (asymbol *) bfd_malloc (size);
19136 if (s == NULL)
19137 return -1;
19138
19139 offset = elf32_arm_plt0_size (abfd, data);
19140 if (offset == (bfd_vma) -1)
19141 return -1;
19142
19143 names = (char *) (s + count);
19144 p = relplt->relocation;
19145 n = 0;
19146 for (i = 0; i < count; i++, p += elf32_arm_size_info.int_rels_per_ext_rel)
19147 {
19148 size_t len;
19149
19150 bfd_vma plt_size = elf32_arm_plt_size (abfd, data, offset);
19151 if (plt_size == (bfd_vma) -1)
19152 break;
19153
19154 *s = **p->sym_ptr_ptr;
19155 /* Undefined syms won't have BSF_LOCAL or BSF_GLOBAL set. Since
19156 we are defining a symbol, ensure one of them is set. */
19157 if ((s->flags & BSF_LOCAL) == 0)
19158 s->flags |= BSF_GLOBAL;
19159 s->flags |= BSF_SYNTHETIC;
19160 s->section = plt;
19161 s->value = offset;
19162 s->name = names;
19163 s->udata.p = NULL;
19164 len = strlen ((*p->sym_ptr_ptr)->name);
19165 memcpy (names, (*p->sym_ptr_ptr)->name, len);
19166 names += len;
19167 if (p->addend != 0)
19168 {
19169 char buf[30], *a;
19170
19171 memcpy (names, "+0x", sizeof ("+0x") - 1);
19172 names += sizeof ("+0x") - 1;
19173 bfd_sprintf_vma (abfd, buf, p->addend);
19174 for (a = buf; *a == '0'; ++a)
19175 ;
19176 len = strlen (a);
19177 memcpy (names, a, len);
19178 names += len;
19179 }
19180 memcpy (names, "@plt", sizeof ("@plt"));
19181 names += sizeof ("@plt");
19182 ++s, ++n;
19183 offset += plt_size;
19184 }
19185
19186 return n;
19187}
19188
ac4c9b04
MG		 19189static bfd_boolean
19190elf32_arm_section_flags (flagword *flags, const Elf_Internal_Shdr * hdr)
19191{
f0728ee3
AV		 19192 if (hdr->sh_flags & SHF_ARM_PURECODE)
19193 *flags |= SEC_ELF_PURECODE;
ac4c9b04
MG		 19194 return TRUE;
19195}
19196
19197static flagword
19198elf32_arm_lookup_section_flags (char *flag_name)
19199{
f0728ee3
AV		 19200 if (!strcmp (flag_name, "SHF_ARM_PURECODE"))
19201 return SHF_ARM_PURECODE;
ac4c9b04
MG		 19202
19203 return SEC_NO_FLAGS;
19204}
19205
491d01d3
YU		 19206static unsigned int
19207elf32_arm_count_additional_relocs (asection *sec)
19208{
19209 struct _arm_elf_section_data *arm_data;
19210 arm_data = get_arm_elf_section_data (sec);
5025eb7c 19211
6342be70 19212 return arm_data == NULL ? 0 : arm_data->additional_reloc_count;
491d01d3
YU		 19213}
19214
5522f910 19215/* Called to set the sh_flags, sh_link and sh_info fields of OSECTION which
9eaff861 19216 has a type >= SHT_LOOS. Returns TRUE if these fields were initialised
5522f910
NC		 19217 FALSE otherwise. ISECTION is the best guess matching section from the
19218 input bfd IBFD, but it might be NULL. */
19219
19220static bfd_boolean
19221elf32_arm_copy_special_section_fields (const bfd *ibfd ATTRIBUTE_UNUSED,
19222 bfd *obfd ATTRIBUTE_UNUSED,
19223 const Elf_Internal_Shdr *isection ATTRIBUTE_UNUSED,
19224 Elf_Internal_Shdr *osection)
19225{
19226 switch (osection->sh_type)
19227 {
19228 case SHT_ARM_EXIDX:
19229 {
19230 Elf_Internal_Shdr **oheaders = elf_elfsections (obfd);
19231 Elf_Internal_Shdr **iheaders = elf_elfsections (ibfd);
19232 unsigned i = 0;
19233
19234 osection->sh_flags = SHF_ALLOC | SHF_LINK_ORDER;
19235 osection->sh_info = 0;
19236
19237 /* The sh_link field must be set to the text section associated with
19238 this index section. Unfortunately the ARM EHABI does not specify
19239 exactly how to determine this association. Our caller does try
19240 to match up OSECTION with its corresponding input section however
19241 so that is a good first guess. */
19242 if (isection != NULL
19243 && osection->bfd_section != NULL
19244 && isection->bfd_section != NULL
19245 && isection->bfd_section->output_section != NULL
19246 && isection->bfd_section->output_section == osection->bfd_section
19247 && iheaders != NULL
19248 && isection->sh_link > 0
19249 && isection->sh_link < elf_numsections (ibfd)
19250 && iheaders[isection->sh_link]->bfd_section != NULL
19251 && iheaders[isection->sh_link]->bfd_section->output_section != NULL
19252 )
19253 {
19254 for (i = elf_numsections (obfd); i-- > 0;)
19255 if (oheaders[i]->bfd_section
19256 == iheaders[isection->sh_link]->bfd_section->output_section)
19257 break;
19258 }
9eaff861 19259
5522f910
NC		 19260 if (i == 0)
19261 {
19262 /* Failing that we have to find a matching section ourselves. If
19263 we had the output section name available we could compare that
19264 with input section names. Unfortunately we don't. So instead
19265 we use a simple heuristic and look for the nearest executable
19266 section before this one. */
19267 for (i = elf_numsections (obfd); i-- > 0;)
19268 if (oheaders[i] == osection)
19269 break;
19270 if (i == 0)
19271 break;
19272
19273 while (i-- > 0)
19274 if (oheaders[i]->sh_type == SHT_PROGBITS
19275 && (oheaders[i]->sh_flags & (SHF_ALLOC | SHF_EXECINSTR))
19276 == (SHF_ALLOC | SHF_EXECINSTR))
19277 break;
19278 }
19279
19280 if (i)
19281 {
19282 osection->sh_link = i;
19283 /* If the text section was part of a group
19284 then the index section should be too. */
19285 if (oheaders[i]->sh_flags & SHF_GROUP)
19286 osection->sh_flags |= SHF_GROUP;
19287 return TRUE;
19288 }
19289 }
19290 break;
19291
19292 case SHT_ARM_PREEMPTMAP:
19293 osection->sh_flags = SHF_ALLOC;
19294 break;
19295
19296 case SHT_ARM_ATTRIBUTES:
19297 case SHT_ARM_DEBUGOVERLAY:
19298 case SHT_ARM_OVERLAYSECTION:
19299 default:
19300 break;
19301 }
19302
19303 return FALSE;
19304}
19305
d691934d
NC		 19306/* Returns TRUE if NAME is an ARM mapping symbol.
19307 Traditionally the symbols $a, $d and $t have been used.
19308 The ARM ELF standard also defines $x (for A64 code). It also allows a
19309 period initiated suffix to be added to the symbol: "$[adtx]\.[:sym_char]+".
19310 Other tools might also produce $b (Thumb BL), $f, $p, $m and $v, but we do
19311 not support them here. $t.x indicates the start of ThumbEE instructions. */
19312
19313static bfd_boolean
19314is_arm_mapping_symbol (const char * name)
19315{
19316 return name != NULL /* Paranoia. */
19317 && name[0] == '$' /* Note: if objcopy --prefix-symbols has been used then
19318 the mapping symbols could have acquired a prefix.
19319 We do not support this here, since such symbols no
19320 longer conform to the ARM ELF ABI. */
19321 && (name[1] == 'a' || name[1] == 'd' || name[1] == 't' || name[1] == 'x')
19322 && (name[2] == 0 || name[2] == '.');
19323 /* FIXME: Strictly speaking the symbol is only a valid mapping symbol if
19324 any characters that follow the period are legal characters for the body
19325 of a symbol's name. For now we just assume that this is the case. */
19326}
19327
fca2a38f
NC		 19328/* Make sure that mapping symbols in object files are not removed via the
19329 "strip --strip-unneeded" tool. These symbols are needed in order to
19330 correctly generate interworking veneers, and for byte swapping code
19331 regions. Once an object file has been linked, it is safe to remove the
19332 symbols as they will no longer be needed. */
19333
19334static void
19335elf32_arm_backend_symbol_processing (bfd *abfd, asymbol *sym)
19336{
19337 if (((abfd->flags & (EXEC_P | DYNAMIC)) == 0)
fca2a38f 19338 && sym->section != bfd_abs_section_ptr
d691934d 19339 && is_arm_mapping_symbol (sym->name))
fca2a38f
NC		 19340 sym->flags |= BSF_KEEP;
19341}
19342
5522f910
NC		 19343#undef elf_backend_copy_special_section_fields
19344#define elf_backend_copy_special_section_fields elf32_arm_copy_special_section_fields
19345
252b5132 19346#define ELF_ARCH bfd_arch_arm
ae95ffa6 19347#define ELF_TARGET_ID ARM_ELF_DATA
252b5132 19348#define ELF_MACHINE_CODE EM_ARM
d0facd1b
NC		 19349#ifdef __QNXTARGET__
19350#define ELF_MAXPAGESIZE 0x1000
19351#else
7572ca89 19352#define ELF_MAXPAGESIZE 0x10000
d0facd1b 19353#endif
b1342370 19354#define ELF_MINPAGESIZE 0x1000
24718e3b 19355#define ELF_COMMONPAGESIZE 0x1000
252b5132 19356
ba93b8ac
DJ		 19357#define bfd_elf32_mkobject elf32_arm_mkobject
19358
99e4ae17
AJ		 19359#define bfd_elf32_bfd_copy_private_bfd_data elf32_arm_copy_private_bfd_data
19360#define bfd_elf32_bfd_merge_private_bfd_data elf32_arm_merge_private_bfd_data
252b5132
RH		 19361#define bfd_elf32_bfd_set_private_flags elf32_arm_set_private_flags
19362#define bfd_elf32_bfd_print_private_bfd_data elf32_arm_print_private_bfd_data
19363#define bfd_elf32_bfd_link_hash_table_create elf32_arm_link_hash_table_create
dc810e39 19364#define bfd_elf32_bfd_reloc_type_lookup elf32_arm_reloc_type_lookup
b38cadfb 19365#define bfd_elf32_bfd_reloc_name_lookup elf32_arm_reloc_name_lookup
252b5132 19366#define bfd_elf32_find_nearest_line elf32_arm_find_nearest_line
4ab527b0 19367#define bfd_elf32_find_inliner_info elf32_arm_find_inliner_info
e489d0ae 19368#define bfd_elf32_new_section_hook elf32_arm_new_section_hook
3c9458e9 19369#define bfd_elf32_bfd_is_target_special_symbol elf32_arm_is_target_special_symbol
3e6b1042 19370#define bfd_elf32_bfd_final_link elf32_arm_final_link
6a631e86 19371#define bfd_elf32_get_synthetic_symtab elf32_arm_get_synthetic_symtab
252b5132
RH		 19372
19373#define elf_backend_get_symbol_type elf32_arm_get_symbol_type
19374#define elf_backend_gc_mark_hook elf32_arm_gc_mark_hook
6a5bb875 19375#define elf_backend_gc_mark_extra_sections elf32_arm_gc_mark_extra_sections
252b5132
RH		 19376#define elf_backend_gc_sweep_hook elf32_arm_gc_sweep_hook
19377#define elf_backend_check_relocs elf32_arm_check_relocs
9eaff861 19378#define elf_backend_update_relocs elf32_arm_update_relocs
dc810e39 19379#define elf_backend_relocate_section elf32_arm_relocate_section
e489d0ae 19380#define elf_backend_write_section elf32_arm_write_section
252b5132 19381#define elf_backend_adjust_dynamic_symbol elf32_arm_adjust_dynamic_symbol
5e681ec4 19382#define elf_backend_create_dynamic_sections elf32_arm_create_dynamic_sections
252b5132
RH		 19383#define elf_backend_finish_dynamic_symbol elf32_arm_finish_dynamic_symbol
19384#define elf_backend_finish_dynamic_sections elf32_arm_finish_dynamic_sections
19385#define elf_backend_size_dynamic_sections elf32_arm_size_dynamic_sections
0855e32b 19386#define elf_backend_always_size_sections elf32_arm_always_size_sections
74541ad4 19387#define elf_backend_init_index_section _bfd_elf_init_2_index_sections
ba96a88f 19388#define elf_backend_post_process_headers elf32_arm_post_process_headers
99e4ae17 19389#define elf_backend_reloc_type_class elf32_arm_reloc_type_class
c178919b 19390#define elf_backend_object_p elf32_arm_object_p
40a18ebd
NC		 19391#define elf_backend_fake_sections elf32_arm_fake_sections
19392#define elf_backend_section_from_shdr elf32_arm_section_from_shdr
e16bb312 19393#define elf_backend_final_write_processing elf32_arm_final_write_processing
5e681ec4 19394#define elf_backend_copy_indirect_symbol elf32_arm_copy_indirect_symbol
0beaef2b 19395#define elf_backend_size_info elf32_arm_size_info
b294bdf8 19396#define elf_backend_modify_segment_map elf32_arm_modify_segment_map
906e58ca
NC		 19397#define elf_backend_additional_program_headers elf32_arm_additional_program_headers
19398#define elf_backend_output_arch_local_syms elf32_arm_output_arch_local_syms
54ddd295 19399#define elf_backend_filter_implib_symbols elf32_arm_filter_implib_symbols
906e58ca 19400#define elf_backend_begin_write_processing elf32_arm_begin_write_processing
34e77a92 19401#define elf_backend_add_symbol_hook elf32_arm_add_symbol_hook
491d01d3 19402#define elf_backend_count_additional_relocs elf32_arm_count_additional_relocs
fca2a38f 19403#define elf_backend_symbol_processing elf32_arm_backend_symbol_processing
906e58ca
NC		 19404
19405#define elf_backend_can_refcount 1
19406#define elf_backend_can_gc_sections 1
19407#define elf_backend_plt_readonly 1
19408#define elf_backend_want_got_plt 1
19409#define elf_backend_want_plt_sym 0
19410#define elf_backend_may_use_rel_p 1
19411#define elf_backend_may_use_rela_p 0
4e7fd91e 19412#define elf_backend_default_use_rela_p 0
252b5132 19413
04f7c78d 19414#define elf_backend_got_header_size 12
b68a20d6 19415#define elf_backend_extern_protected_data 1
04f7c78d 19416
906e58ca
NC		 19417#undef elf_backend_obj_attrs_vendor
19418#define elf_backend_obj_attrs_vendor "aeabi"
19419#undef elf_backend_obj_attrs_section
19420#define elf_backend_obj_attrs_section ".ARM.attributes"
19421#undef elf_backend_obj_attrs_arg_type
19422#define elf_backend_obj_attrs_arg_type elf32_arm_obj_attrs_arg_type
19423#undef elf_backend_obj_attrs_section_type
104d59d1 19424#define elf_backend_obj_attrs_section_type SHT_ARM_ATTRIBUTES
b38cadfb
NC		 19425#define elf_backend_obj_attrs_order elf32_arm_obj_attrs_order
19426#define elf_backend_obj_attrs_handle_unknown elf32_arm_obj_attrs_handle_unknown
104d59d1 19427
5025eb7c 19428#undef elf_backend_section_flags
ac4c9b04 19429#define elf_backend_section_flags elf32_arm_section_flags
5025eb7c 19430#undef elf_backend_lookup_section_flags_hook
ac4c9b04
MG		 19431#define elf_backend_lookup_section_flags_hook elf32_arm_lookup_section_flags
19432
252b5132 19433#include "elf32-target.h"
7f266840 19434
b38cadfb
NC		 19435/* Native Client targets. */
19436
19437#undef TARGET_LITTLE_SYM
6d00b590 19438#define TARGET_LITTLE_SYM arm_elf32_nacl_le_vec
b38cadfb
NC		 19439#undef TARGET_LITTLE_NAME
19440#define TARGET_LITTLE_NAME "elf32-littlearm-nacl"
19441#undef TARGET_BIG_SYM
6d00b590 19442#define TARGET_BIG_SYM arm_elf32_nacl_be_vec
b38cadfb
NC		 19443#undef TARGET_BIG_NAME
19444#define TARGET_BIG_NAME "elf32-bigarm-nacl"
19445
19446/* Like elf32_arm_link_hash_table_create -- but overrides
19447 appropriately for NaCl. */
19448
19449static struct bfd_link_hash_table *
19450elf32_arm_nacl_link_hash_table_create (bfd *abfd)
19451{
19452 struct bfd_link_hash_table *ret;
19453
19454 ret = elf32_arm_link_hash_table_create (abfd);
19455 if (ret)
19456 {
19457 struct elf32_arm_link_hash_table *htab
19458 = (struct elf32_arm_link_hash_table *) ret;
19459
19460 htab->nacl_p = 1;
19461
19462 htab->plt_header_size = 4 * ARRAY_SIZE (elf32_arm_nacl_plt0_entry);
19463 htab->plt_entry_size = 4 * ARRAY_SIZE (elf32_arm_nacl_plt_entry);
19464 }
19465 return ret;
19466}
19467
19468/* Since NaCl doesn't use the ARM-specific unwind format, we don't
19469 really need to use elf32_arm_modify_segment_map. But we do it
19470 anyway just to reduce gratuitous differences with the stock ARM backend. */
19471
19472static bfd_boolean
19473elf32_arm_nacl_modify_segment_map (bfd *abfd, struct bfd_link_info *info)
19474{
19475 return (elf32_arm_modify_segment_map (abfd, info)
19476 && nacl_modify_segment_map (abfd, info));
19477}
19478
887badb3
RM		 19479static void
19480elf32_arm_nacl_final_write_processing (bfd *abfd, bfd_boolean linker)
19481{
19482 elf32_arm_final_write_processing (abfd, linker);
19483 nacl_final_write_processing (abfd, linker);
19484}
19485
6a631e86
YG		 19486static bfd_vma
19487elf32_arm_nacl_plt_sym_val (bfd_vma i, const asection *plt,
19488 const arelent *rel ATTRIBUTE_UNUSED)
19489{
19490 return plt->vma
19491 + 4 * (ARRAY_SIZE (elf32_arm_nacl_plt0_entry) +
19492 i * ARRAY_SIZE (elf32_arm_nacl_plt_entry));
19493}
887badb3 19494
b38cadfb 19495#undef elf32_bed
6a631e86 19496#define elf32_bed elf32_arm_nacl_bed
b38cadfb
NC		 19497#undef bfd_elf32_bfd_link_hash_table_create
19498#define bfd_elf32_bfd_link_hash_table_create \
19499 elf32_arm_nacl_link_hash_table_create
19500#undef elf_backend_plt_alignment
6a631e86 19501#define elf_backend_plt_alignment 4
b38cadfb
NC		 19502#undef elf_backend_modify_segment_map
19503#define elf_backend_modify_segment_map elf32_arm_nacl_modify_segment_map
19504#undef elf_backend_modify_program_headers
19505#define elf_backend_modify_program_headers nacl_modify_program_headers
887badb3
RM		 19506#undef elf_backend_final_write_processing
19507#define elf_backend_final_write_processing elf32_arm_nacl_final_write_processing
6a631e86
YG		 19508#undef bfd_elf32_get_synthetic_symtab
19509#undef elf_backend_plt_sym_val
19510#define elf_backend_plt_sym_val elf32_arm_nacl_plt_sym_val
5522f910 19511#undef elf_backend_copy_special_section_fields
b38cadfb 19512
887badb3
RM		 19513#undef ELF_MINPAGESIZE
19514#undef ELF_COMMONPAGESIZE
19515
b38cadfb
NC		 19516
19517#include "elf32-target.h"
19518
19519/* Reset to defaults. */
19520#undef elf_backend_plt_alignment
19521#undef elf_backend_modify_segment_map
19522#define elf_backend_modify_segment_map elf32_arm_modify_segment_map
19523#undef elf_backend_modify_program_headers
887badb3
RM		 19524#undef elf_backend_final_write_processing
19525#define elf_backend_final_write_processing elf32_arm_final_write_processing
19526#undef ELF_MINPAGESIZE
19527#define ELF_MINPAGESIZE 0x1000
19528#undef ELF_COMMONPAGESIZE
19529#define ELF_COMMONPAGESIZE 0x1000
19530
b38cadfb 19531
906e58ca 19532/* VxWorks Targets. */
4e7fd91e 19533
906e58ca 19534#undef TARGET_LITTLE_SYM
6d00b590 19535#define TARGET_LITTLE_SYM arm_elf32_vxworks_le_vec
906e58ca 19536#undef TARGET_LITTLE_NAME
4e7fd91e 19537#define TARGET_LITTLE_NAME "elf32-littlearm-vxworks"
906e58ca 19538#undef TARGET_BIG_SYM
6d00b590 19539#define TARGET_BIG_SYM arm_elf32_vxworks_be_vec
906e58ca 19540#undef TARGET_BIG_NAME
4e7fd91e
PB		 19541#define TARGET_BIG_NAME "elf32-bigarm-vxworks"
19542
19543/* Like elf32_arm_link_hash_table_create -- but overrides
19544 appropriately for VxWorks. */
906e58ca 19545
4e7fd91e
PB		 19546static struct bfd_link_hash_table *
19547elf32_arm_vxworks_link_hash_table_create (bfd *abfd)
19548{
19549 struct bfd_link_hash_table *ret;
19550
19551 ret = elf32_arm_link_hash_table_create (abfd);
19552 if (ret)
19553 {
19554 struct elf32_arm_link_hash_table *htab
00a97672 19555 = (struct elf32_arm_link_hash_table *) ret;
4e7fd91e 19556 htab->use_rel = 0;
00a97672 19557 htab->vxworks_p = 1;
4e7fd91e
PB		 19558 }
19559 return ret;
906e58ca 19560}
4e7fd91e 19561
00a97672
RS		 19562static void
19563elf32_arm_vxworks_final_write_processing (bfd *abfd, bfd_boolean linker)
19564{
19565 elf32_arm_final_write_processing (abfd, linker);
19566 elf_vxworks_final_write_processing (abfd, linker);
19567}
19568
906e58ca 19569#undef elf32_bed
4e7fd91e
PB		 19570#define elf32_bed elf32_arm_vxworks_bed
19571
906e58ca
NC		 19572#undef bfd_elf32_bfd_link_hash_table_create
19573#define bfd_elf32_bfd_link_hash_table_create elf32_arm_vxworks_link_hash_table_create
906e58ca
NC		 19574#undef elf_backend_final_write_processing
19575#define elf_backend_final_write_processing elf32_arm_vxworks_final_write_processing
19576#undef elf_backend_emit_relocs
9eaff861 19577#define elf_backend_emit_relocs elf_vxworks_emit_relocs
4e7fd91e 19578
906e58ca 19579#undef elf_backend_may_use_rel_p
00a97672 19580#define elf_backend_may_use_rel_p 0
906e58ca 19581#undef elf_backend_may_use_rela_p
00a97672 19582#define elf_backend_may_use_rela_p 1
906e58ca 19583#undef elf_backend_default_use_rela_p
00a97672 19584#define elf_backend_default_use_rela_p 1
906e58ca 19585#undef elf_backend_want_plt_sym
00a97672 19586#define elf_backend_want_plt_sym 1
906e58ca 19587#undef ELF_MAXPAGESIZE
00a97672 19588#define ELF_MAXPAGESIZE 0x1000
4e7fd91e
PB		 19589
19590#include "elf32-target.h"
19591
19592
21d799b5
NC		 19593/* Merge backend specific data from an object file to the output
19594 object file when linking. */
19595
19596static bfd_boolean
19597elf32_arm_merge_private_bfd_data (bfd * ibfd, bfd * obfd)
19598{
19599 flagword out_flags;
19600 flagword in_flags;
19601 bfd_boolean flags_compatible = TRUE;
19602 asection *sec;
19603
cc643b88 19604 /* Check if we have the same endianness. */
21d799b5
NC		 19605 if (! _bfd_generic_verify_endian_match (ibfd, obfd))
19606 return FALSE;
19607
19608 if (! is_arm_elf (ibfd) || ! is_arm_elf (obfd))
19609 return TRUE;
19610
19611 if (!elf32_arm_merge_eabi_attributes (ibfd, obfd))
19612 return FALSE;
19613
19614 /* The input BFD must have had its flags initialised. */
19615 /* The following seems bogus to me -- The flags are initialized in
19616 the assembler but I don't think an elf_flags_init field is
19617 written into the object. */
19618 /* BFD_ASSERT (elf_flags_init (ibfd)); */
19619
19620 in_flags = elf_elfheader (ibfd)->e_flags;
19621 out_flags = elf_elfheader (obfd)->e_flags;
19622
19623 /* In theory there is no reason why we couldn't handle this. However
19624 in practice it isn't even close to working and there is no real
19625 reason to want it. */
19626 if (EF_ARM_EABI_VERSION (in_flags) >= EF_ARM_EABI_VER4
19627 && !(ibfd->flags & DYNAMIC)
19628 && (in_flags & EF_ARM_BE8))
19629 {
19630 _bfd_error_handler (_("error: %B is already in final BE8 format"),
19631 ibfd);
19632 return FALSE;
19633 }
19634
19635 if (!elf_flags_init (obfd))
19636 {
19637 /* If the input is the default architecture and had the default
19638 flags then do not bother setting the flags for the output
19639 architecture, instead allow future merges to do this. If no
19640 future merges ever set these flags then they will retain their
99059e56
RM		 19641 uninitialised values, which surprise surprise, correspond
19642 to the default values. */
21d799b5
NC		 19643 if (bfd_get_arch_info (ibfd)->the_default
19644 && elf_elfheader (ibfd)->e_flags == 0)
19645 return TRUE;
19646
19647 elf_flags_init (obfd) = TRUE;
19648 elf_elfheader (obfd)->e_flags = in_flags;
19649
19650 if (bfd_get_arch (obfd) == bfd_get_arch (ibfd)
19651 && bfd_get_arch_info (obfd)->the_default)
19652 return bfd_set_arch_mach (obfd, bfd_get_arch (ibfd), bfd_get_mach (ibfd));
19653
19654 return TRUE;
19655 }
19656
19657 /* Determine what should happen if the input ARM architecture
19658 does not match the output ARM architecture. */
19659 if (! bfd_arm_merge_machines (ibfd, obfd))
19660 return FALSE;
19661
19662 /* Identical flags must be compatible. */
19663 if (in_flags == out_flags)
19664 return TRUE;
19665
19666 /* Check to see if the input BFD actually contains any sections. If
19667 not, its flags may not have been initialised either, but it
19668 cannot actually cause any incompatiblity. Do not short-circuit
19669 dynamic objects; their section list may be emptied by
19670 elf_link_add_object_symbols.
19671
19672 Also check to see if there are no code sections in the input.
19673 In this case there is no need to check for code specific flags.
19674 XXX - do we need to worry about floating-point format compatability
19675 in data sections ? */
19676 if (!(ibfd->flags & DYNAMIC))
19677 {
19678 bfd_boolean null_input_bfd = TRUE;
19679 bfd_boolean only_data_sections = TRUE;
19680
19681 for (sec = ibfd->sections; sec != NULL; sec = sec->next)
19682 {
19683 /* Ignore synthetic glue sections. */
19684 if (strcmp (sec->name, ".glue_7")
19685 && strcmp (sec->name, ".glue_7t"))
19686 {
19687 if ((bfd_get_section_flags (ibfd, sec)
19688 & (SEC_LOAD | SEC_CODE | SEC_HAS_CONTENTS))
19689 == (SEC_LOAD | SEC_CODE | SEC_HAS_CONTENTS))
99059e56 19690 only_data_sections = FALSE;
21d799b5
NC		 19691
19692 null_input_bfd = FALSE;
19693 break;
19694 }
19695 }
19696
19697 if (null_input_bfd || only_data_sections)
19698 return TRUE;
19699 }
19700
19701 /* Complain about various flag mismatches. */
19702 if (!elf32_arm_versions_compatible (EF_ARM_EABI_VERSION (in_flags),
19703 EF_ARM_EABI_VERSION (out_flags)))
19704 {
19705 _bfd_error_handler
19706 (_("error: Source object %B has EABI version %d, but target %B has EABI version %d"),
19707 ibfd, obfd,
19708 (in_flags & EF_ARM_EABIMASK) >> 24,
19709 (out_flags & EF_ARM_EABIMASK) >> 24);
19710 return FALSE;
19711 }
19712
19713 /* Not sure what needs to be checked for EABI versions >= 1. */
19714 /* VxWorks libraries do not use these flags. */
19715 if (get_elf_backend_data (obfd) != &elf32_arm_vxworks_bed
19716 && get_elf_backend_data (ibfd) != &elf32_arm_vxworks_bed
19717 && EF_ARM_EABI_VERSION (in_flags) == EF_ARM_EABI_UNKNOWN)
19718 {
19719 if ((in_flags & EF_ARM_APCS_26) != (out_flags & EF_ARM_APCS_26))
19720 {
19721 _bfd_error_handler
19722 (_("error: %B is compiled for APCS-%d, whereas target %B uses APCS-%d"),
19723 ibfd, obfd,
19724 in_flags & EF_ARM_APCS_26 ? 26 : 32,
19725 out_flags & EF_ARM_APCS_26 ? 26 : 32);
19726 flags_compatible = FALSE;
19727 }
19728
19729 if ((in_flags & EF_ARM_APCS_FLOAT) != (out_flags & EF_ARM_APCS_FLOAT))
19730 {
19731 if (in_flags & EF_ARM_APCS_FLOAT)
19732 _bfd_error_handler
19733 (_("error: %B passes floats in float registers, whereas %B passes them in integer registers"),
19734 ibfd, obfd);
19735 else
19736 _bfd_error_handler
19737 (_("error: %B passes floats in integer registers, whereas %B passes them in float registers"),
19738 ibfd, obfd);
19739
19740 flags_compatible = FALSE;
19741 }
19742
19743 if ((in_flags & EF_ARM_VFP_FLOAT) != (out_flags & EF_ARM_VFP_FLOAT))
19744 {
19745 if (in_flags & EF_ARM_VFP_FLOAT)
19746 _bfd_error_handler
19747 (_("error: %B uses VFP instructions, whereas %B does not"),
19748 ibfd, obfd);
19749 else
19750 _bfd_error_handler
19751 (_("error: %B uses FPA instructions, whereas %B does not"),
19752 ibfd, obfd);
19753
19754 flags_compatible = FALSE;
19755 }
19756
19757 if ((in_flags & EF_ARM_MAVERICK_FLOAT) != (out_flags & EF_ARM_MAVERICK_FLOAT))
19758 {
19759 if (in_flags & EF_ARM_MAVERICK_FLOAT)
19760 _bfd_error_handler
19761 (_("error: %B uses Maverick instructions, whereas %B does not"),
19762 ibfd, obfd);
19763 else
19764 _bfd_error_handler
19765 (_("error: %B does not use Maverick instructions, whereas %B does"),
19766 ibfd, obfd);
19767
19768 flags_compatible = FALSE;
19769 }
19770
19771#ifdef EF_ARM_SOFT_FLOAT
19772 if ((in_flags & EF_ARM_SOFT_FLOAT) != (out_flags & EF_ARM_SOFT_FLOAT))
19773 {
19774 /* We can allow interworking between code that is VFP format
19775 layout, and uses either soft float or integer regs for
19776 passing floating point arguments and results. We already
19777 know that the APCS_FLOAT flags match; similarly for VFP
19778 flags. */
19779 if ((in_flags & EF_ARM_APCS_FLOAT) != 0
19780 || (in_flags & EF_ARM_VFP_FLOAT) == 0)
19781 {
19782 if (in_flags & EF_ARM_SOFT_FLOAT)
19783 _bfd_error_handler
19784 (_("error: %B uses software FP, whereas %B uses hardware FP"),
19785 ibfd, obfd);
19786 else
19787 _bfd_error_handler
19788 (_("error: %B uses hardware FP, whereas %B uses software FP"),
19789 ibfd, obfd);
19790
19791 flags_compatible = FALSE;
19792 }
19793 }
19794#endif
19795
19796 /* Interworking mismatch is only a warning. */
19797 if ((in_flags & EF_ARM_INTERWORK) != (out_flags & EF_ARM_INTERWORK))
19798 {
19799 if (in_flags & EF_ARM_INTERWORK)
19800 {
19801 _bfd_error_handler
19802 (_("Warning: %B supports interworking, whereas %B does not"),
19803 ibfd, obfd);
19804 }
19805 else
19806 {
19807 _bfd_error_handler
19808 (_("Warning: %B does not support interworking, whereas %B does"),
19809 ibfd, obfd);
19810 }
19811 }
19812 }
19813
19814 return flags_compatible;
19815}
19816
19817
906e58ca 19818/* Symbian OS Targets. */
7f266840 19819
906e58ca 19820#undef TARGET_LITTLE_SYM
6d00b590 19821#define TARGET_LITTLE_SYM arm_elf32_symbian_le_vec
906e58ca 19822#undef TARGET_LITTLE_NAME
7f266840 19823#define TARGET_LITTLE_NAME "elf32-littlearm-symbian"
906e58ca 19824#undef TARGET_BIG_SYM
6d00b590 19825#define TARGET_BIG_SYM arm_elf32_symbian_be_vec
906e58ca 19826#undef TARGET_BIG_NAME
7f266840
DJ		 19827#define TARGET_BIG_NAME "elf32-bigarm-symbian"
19828
19829/* Like elf32_arm_link_hash_table_create -- but overrides
19830 appropriately for Symbian OS. */
906e58ca 19831
7f266840
DJ		 19832static struct bfd_link_hash_table *
19833elf32_arm_symbian_link_hash_table_create (bfd *abfd)
19834{
19835 struct bfd_link_hash_table *ret;
19836
19837 ret = elf32_arm_link_hash_table_create (abfd);
19838 if (ret)
19839 {
19840 struct elf32_arm_link_hash_table *htab
19841 = (struct elf32_arm_link_hash_table *)ret;
19842 /* There is no PLT header for Symbian OS. */
19843 htab->plt_header_size = 0;
95720a86
DJ		 19844 /* The PLT entries are each one instruction and one word. */
19845 htab->plt_entry_size = 4 * ARRAY_SIZE (elf32_arm_symbian_plt_entry);
7f266840 19846 htab->symbian_p = 1;
33bfe774
JB		 19847 /* Symbian uses armv5t or above, so use_blx is always true. */
19848 htab->use_blx = 1;
67687978 19849 htab->root.is_relocatable_executable = 1;
7f266840
DJ		 19850 }
19851 return ret;
906e58ca 19852}
7f266840 19853
b35d266b 19854static const struct bfd_elf_special_section
551b43fd 19855elf32_arm_symbian_special_sections[] =
7f266840 19856{
5cd3778d
MM		 19857 /* In a BPABI executable, the dynamic linking sections do not go in
19858 the loadable read-only segment. The post-linker may wish to
19859 refer to these sections, but they are not part of the final
19860 program image. */
0112cd26
NC		 19861 { STRING_COMMA_LEN (".dynamic"), 0, SHT_DYNAMIC, 0 },
19862 { STRING_COMMA_LEN (".dynstr"), 0, SHT_STRTAB, 0 },
19863 { STRING_COMMA_LEN (".dynsym"), 0, SHT_DYNSYM, 0 },
19864 { STRING_COMMA_LEN (".got"), 0, SHT_PROGBITS, 0 },
19865 { STRING_COMMA_LEN (".hash"), 0, SHT_HASH, 0 },
5cd3778d
MM		 19866 /* These sections do not need to be writable as the SymbianOS
19867 postlinker will arrange things so that no dynamic relocation is
19868 required. */
0112cd26
NC		 19869 { STRING_COMMA_LEN (".init_array"), 0, SHT_INIT_ARRAY, SHF_ALLOC },
19870 { STRING_COMMA_LEN (".fini_array"), 0, SHT_FINI_ARRAY, SHF_ALLOC },
19871 { STRING_COMMA_LEN (".preinit_array"), 0, SHT_PREINIT_ARRAY, SHF_ALLOC },
19872 { NULL, 0, 0, 0, 0 }
7f266840
DJ		 19873};
19874
c3c76620 19875static void
906e58ca 19876elf32_arm_symbian_begin_write_processing (bfd *abfd,
a4fd1a8e 19877 struct bfd_link_info *link_info)
c3c76620
MM		 19878{
19879 /* BPABI objects are never loaded directly by an OS kernel; they are
19880 processed by a postlinker first, into an OS-specific format. If
19881 the D_PAGED bit is set on the file, BFD will align segments on
19882 page boundaries, so that an OS can directly map the file. With
19883 BPABI objects, that just results in wasted space. In addition,
19884 because we clear the D_PAGED bit, map_sections_to_segments will
19885 recognize that the program headers should not be mapped into any
19886 loadable segment. */
19887 abfd->flags &= ~D_PAGED;
906e58ca 19888 elf32_arm_begin_write_processing (abfd, link_info);
c3c76620 19889}
7f266840
DJ		 19890
19891static bfd_boolean
906e58ca 19892elf32_arm_symbian_modify_segment_map (bfd *abfd,
b294bdf8 19893 struct bfd_link_info *info)
7f266840
DJ		 19894{
19895 struct elf_segment_map *m;
19896 asection *dynsec;
19897
7f266840
DJ		 19898 /* BPABI shared libraries and executables should have a PT_DYNAMIC
19899 segment. However, because the .dynamic section is not marked
19900 with SEC_LOAD, the generic ELF code will not create such a
19901 segment. */
19902 dynsec = bfd_get_section_by_name (abfd, ".dynamic");
19903 if (dynsec)
19904 {
12bd6957 19905 for (m = elf_seg_map (abfd); m != NULL; m = m->next)
8ded5a0f
AM		 19906 if (m->p_type == PT_DYNAMIC)
19907 break;
19908
19909 if (m == NULL)
19910 {
19911 m = _bfd_elf_make_dynamic_segment (abfd, dynsec);
12bd6957
AM		 19912 m->next = elf_seg_map (abfd);
19913 elf_seg_map (abfd) = m;
8ded5a0f 19914 }
7f266840
DJ		 19915 }
19916
b294bdf8
MM		 19917 /* Also call the generic arm routine. */
19918 return elf32_arm_modify_segment_map (abfd, info);
7f266840
DJ		 19919}
19920
95720a86
DJ		 19921/* Return address for Ith PLT stub in section PLT, for relocation REL
19922 or (bfd_vma) -1 if it should not be included. */
19923
19924static bfd_vma
19925elf32_arm_symbian_plt_sym_val (bfd_vma i, const asection *plt,
19926 const arelent *rel ATTRIBUTE_UNUSED)
19927{
19928 return plt->vma + 4 * ARRAY_SIZE (elf32_arm_symbian_plt_entry) * i;
19929}
19930
8029a119 19931#undef elf32_bed
7f266840
DJ		 19932#define elf32_bed elf32_arm_symbian_bed
19933
19934/* The dynamic sections are not allocated on SymbianOS; the postlinker
19935 will process them and then discard them. */
906e58ca 19936#undef ELF_DYNAMIC_SEC_FLAGS
7f266840
DJ		 19937#define ELF_DYNAMIC_SEC_FLAGS \
19938 (SEC_HAS_CONTENTS | SEC_IN_MEMORY | SEC_LINKER_CREATED)
19939
9eaff861 19940#undef elf_backend_emit_relocs
c3c76620 19941
906e58ca
NC		 19942#undef bfd_elf32_bfd_link_hash_table_create
19943#define bfd_elf32_bfd_link_hash_table_create elf32_arm_symbian_link_hash_table_create
19944#undef elf_backend_special_sections
19945#define elf_backend_special_sections elf32_arm_symbian_special_sections
19946#undef elf_backend_begin_write_processing
19947#define elf_backend_begin_write_processing elf32_arm_symbian_begin_write_processing
19948#undef elf_backend_final_write_processing
19949#define elf_backend_final_write_processing elf32_arm_final_write_processing
19950
19951#undef elf_backend_modify_segment_map
7f266840
DJ		 19952#define elf_backend_modify_segment_map elf32_arm_symbian_modify_segment_map
19953
19954/* There is no .got section for BPABI objects, and hence no header. */
906e58ca 19955#undef elf_backend_got_header_size
7f266840
DJ		 19956#define elf_backend_got_header_size 0
19957
19958/* Similarly, there is no .got.plt section. */
906e58ca 19959#undef elf_backend_want_got_plt
7f266840
DJ		 19960#define elf_backend_want_got_plt 0
19961
906e58ca 19962#undef elf_backend_plt_sym_val
95720a86
DJ		 19963#define elf_backend_plt_sym_val elf32_arm_symbian_plt_sym_val
19964
906e58ca 19965#undef elf_backend_may_use_rel_p
00a97672 19966#define elf_backend_may_use_rel_p 1
906e58ca 19967#undef elf_backend_may_use_rela_p
00a97672 19968#define elf_backend_may_use_rela_p 0
906e58ca 19969#undef elf_backend_default_use_rela_p
00a97672 19970#define elf_backend_default_use_rela_p 0
906e58ca 19971#undef elf_backend_want_plt_sym
00a97672 19972#define elf_backend_want_plt_sym 0
906e58ca 19973#undef ELF_MAXPAGESIZE
00a97672 19974#define ELF_MAXPAGESIZE 0x8000
4e7fd91e 19975
7f266840 19976#include "elf32-target.h"
GDB Binutils - Deliverables
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