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[deliverable/binutils-gdb.git] / bfd / elf32-arm.c
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252b5132 1/* 32-bit ELF support for ARM
82704155 2 Copyright (C) 1998-2019 Free Software Foundation, Inc.
252b5132
RH		 3
4 This file is part of BFD, the Binary File Descriptor library.
5
6 This program is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
cd123cb7 8 the Free Software Foundation; either version 3 of the License, or
252b5132
RH		 9 (at your option) any later version.
10
11 This program is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
15
16 You should have received a copy of the GNU General Public License
17 along with this program; if not, write to the Free Software
cd123cb7
NC		 18 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
19 MA 02110-1301, USA. */
252b5132 20
6e6718a3 21#include "sysdep.h"
2468f9c9
PB		 22#include <limits.h>
23
3db64b00 24#include "bfd.h"
00a97672 25#include "libiberty.h"
7f266840
DJ		 26#include "libbfd.h"
27#include "elf-bfd.h"
b38cadfb 28#include "elf-nacl.h"
00a97672 29#include "elf-vxworks.h"
ee065d83 30#include "elf/arm.h"
7f266840 31
00a97672
RS		 32/* Return the relocation section associated with NAME. HTAB is the
33 bfd's elf32_arm_link_hash_entry. */
34#define RELOC_SECTION(HTAB, NAME) \
35 ((HTAB)->use_rel ? ".rel" NAME : ".rela" NAME)
36
37/* Return size of a relocation entry. HTAB is the bfd's
38 elf32_arm_link_hash_entry. */
39#define RELOC_SIZE(HTAB) \
40 ((HTAB)->use_rel \
41 ? sizeof (Elf32_External_Rel) \
42 : sizeof (Elf32_External_Rela))
43
44/* Return function to swap relocations in. HTAB is the bfd's
45 elf32_arm_link_hash_entry. */
46#define SWAP_RELOC_IN(HTAB) \
47 ((HTAB)->use_rel \
48 ? bfd_elf32_swap_reloc_in \
49 : bfd_elf32_swap_reloca_in)
50
51/* Return function to swap relocations out. HTAB is the bfd's
52 elf32_arm_link_hash_entry. */
53#define SWAP_RELOC_OUT(HTAB) \
54 ((HTAB)->use_rel \
55 ? bfd_elf32_swap_reloc_out \
56 : bfd_elf32_swap_reloca_out)
57
f3185997 58#define elf_info_to_howto NULL
07d6d2b8 59#define elf_info_to_howto_rel elf32_arm_info_to_howto
7f266840
DJ		 60
61#define ARM_ELF_ABI_VERSION 0
62#define ARM_ELF_OS_ABI_VERSION ELFOSABI_ARM
63
79f08007
YZ		 64/* The Adjusted Place, as defined by AAELF. */
65#define Pa(X) ((X) & 0xfffffffc)
66
3e6b1042
DJ		 67static bfd_boolean elf32_arm_write_section (bfd *output_bfd,
68 struct bfd_link_info *link_info,
69 asection *sec,
70 bfd_byte *contents);
71
7f266840
DJ		 72/* Note: code such as elf32_arm_reloc_type_lookup expect to use e.g.
73 R_ARM_PC24 as an index into this, and find the R_ARM_PC24 HOWTO
74 in that slot. */
75
c19d1205 76static reloc_howto_type elf32_arm_howto_table_1[] =
7f266840 77{
8029a119 78 /* No relocation. */
7f266840
DJ		 79 HOWTO (R_ARM_NONE, /* type */
80 0, /* rightshift */
6346d5ca 81 3, /* size (0 = byte, 1 = short, 2 = long) */
7f266840
DJ		 82 0, /* bitsize */
83 FALSE, /* pc_relative */
84 0, /* bitpos */
85 complain_overflow_dont,/* complain_on_overflow */
86 bfd_elf_generic_reloc, /* special_function */
87 "R_ARM_NONE", /* name */
88 FALSE, /* partial_inplace */
89 0, /* src_mask */
90 0, /* dst_mask */
91 FALSE), /* pcrel_offset */
92
93 HOWTO (R_ARM_PC24, /* type */
94 2, /* rightshift */
95 2, /* size (0 = byte, 1 = short, 2 = long) */
96 24, /* bitsize */
97 TRUE, /* pc_relative */
98 0, /* bitpos */
99 complain_overflow_signed,/* complain_on_overflow */
100 bfd_elf_generic_reloc, /* special_function */
101 "R_ARM_PC24", /* name */
102 FALSE, /* partial_inplace */
103 0x00ffffff, /* src_mask */
104 0x00ffffff, /* dst_mask */
105 TRUE), /* pcrel_offset */
106
107 /* 32 bit absolute */
108 HOWTO (R_ARM_ABS32, /* type */
109 0, /* rightshift */
110 2, /* size (0 = byte, 1 = short, 2 = long) */
111 32, /* bitsize */
112 FALSE, /* pc_relative */
113 0, /* bitpos */
114 complain_overflow_bitfield,/* complain_on_overflow */
115 bfd_elf_generic_reloc, /* special_function */
116 "R_ARM_ABS32", /* name */
117 FALSE, /* partial_inplace */
118 0xffffffff, /* src_mask */
119 0xffffffff, /* dst_mask */
120 FALSE), /* pcrel_offset */
121
122 /* standard 32bit pc-relative reloc */
123 HOWTO (R_ARM_REL32, /* type */
124 0, /* rightshift */
125 2, /* size (0 = byte, 1 = short, 2 = long) */
126 32, /* bitsize */
127 TRUE, /* pc_relative */
128 0, /* bitpos */
129 complain_overflow_bitfield,/* complain_on_overflow */
130 bfd_elf_generic_reloc, /* special_function */
131 "R_ARM_REL32", /* name */
132 FALSE, /* partial_inplace */
133 0xffffffff, /* src_mask */
134 0xffffffff, /* dst_mask */
135 TRUE), /* pcrel_offset */
136
c19d1205 137 /* 8 bit absolute - R_ARM_LDR_PC_G0 in AAELF */
4962c51a 138 HOWTO (R_ARM_LDR_PC_G0, /* type */
7f266840
DJ		 139 0, /* rightshift */
140 0, /* size (0 = byte, 1 = short, 2 = long) */
4962c51a
MS		 141 32, /* bitsize */
142 TRUE, /* pc_relative */
7f266840 143 0, /* bitpos */
4962c51a 144 complain_overflow_dont,/* complain_on_overflow */
7f266840 145 bfd_elf_generic_reloc, /* special_function */
4962c51a 146 "R_ARM_LDR_PC_G0", /* name */
7f266840 147 FALSE, /* partial_inplace */
4962c51a
MS		 148 0xffffffff, /* src_mask */
149 0xffffffff, /* dst_mask */
150 TRUE), /* pcrel_offset */
7f266840
DJ		 151
152 /* 16 bit absolute */
153 HOWTO (R_ARM_ABS16, /* type */
154 0, /* rightshift */
155 1, /* size (0 = byte, 1 = short, 2 = long) */
156 16, /* bitsize */
157 FALSE, /* pc_relative */
158 0, /* bitpos */
159 complain_overflow_bitfield,/* complain_on_overflow */
160 bfd_elf_generic_reloc, /* special_function */
161 "R_ARM_ABS16", /* name */
162 FALSE, /* partial_inplace */
163 0x0000ffff, /* src_mask */
164 0x0000ffff, /* dst_mask */
165 FALSE), /* pcrel_offset */
166
167 /* 12 bit absolute */
168 HOWTO (R_ARM_ABS12, /* type */
169 0, /* rightshift */
170 2, /* size (0 = byte, 1 = short, 2 = long) */
171 12, /* bitsize */
172 FALSE, /* pc_relative */
173 0, /* bitpos */
174 complain_overflow_bitfield,/* complain_on_overflow */
175 bfd_elf_generic_reloc, /* special_function */
176 "R_ARM_ABS12", /* name */
177 FALSE, /* partial_inplace */
00a97672
RS		 178 0x00000fff, /* src_mask */
179 0x00000fff, /* dst_mask */
7f266840
DJ		 180 FALSE), /* pcrel_offset */
181
182 HOWTO (R_ARM_THM_ABS5, /* type */
183 6, /* rightshift */
184 1, /* size (0 = byte, 1 = short, 2 = long) */
185 5, /* bitsize */
186 FALSE, /* pc_relative */
187 0, /* bitpos */
188 complain_overflow_bitfield,/* complain_on_overflow */
189 bfd_elf_generic_reloc, /* special_function */
190 "R_ARM_THM_ABS5", /* name */
191 FALSE, /* partial_inplace */
192 0x000007e0, /* src_mask */
193 0x000007e0, /* dst_mask */
194 FALSE), /* pcrel_offset */
195
196 /* 8 bit absolute */
197 HOWTO (R_ARM_ABS8, /* type */
198 0, /* rightshift */
199 0, /* size (0 = byte, 1 = short, 2 = long) */
200 8, /* bitsize */
201 FALSE, /* pc_relative */
202 0, /* bitpos */
203 complain_overflow_bitfield,/* complain_on_overflow */
204 bfd_elf_generic_reloc, /* special_function */
205 "R_ARM_ABS8", /* name */
206 FALSE, /* partial_inplace */
207 0x000000ff, /* src_mask */
208 0x000000ff, /* dst_mask */
209 FALSE), /* pcrel_offset */
210
211 HOWTO (R_ARM_SBREL32, /* type */
212 0, /* rightshift */
213 2, /* size (0 = byte, 1 = short, 2 = long) */
214 32, /* bitsize */
215 FALSE, /* pc_relative */
216 0, /* bitpos */
217 complain_overflow_dont,/* complain_on_overflow */
218 bfd_elf_generic_reloc, /* special_function */
219 "R_ARM_SBREL32", /* name */
220 FALSE, /* partial_inplace */
221 0xffffffff, /* src_mask */
222 0xffffffff, /* dst_mask */
223 FALSE), /* pcrel_offset */
224
c19d1205 225 HOWTO (R_ARM_THM_CALL, /* type */
7f266840
DJ		 226 1, /* rightshift */
227 2, /* size (0 = byte, 1 = short, 2 = long) */
f6ebfac0 228 24, /* bitsize */
7f266840
DJ		 229 TRUE, /* pc_relative */
230 0, /* bitpos */
231 complain_overflow_signed,/* complain_on_overflow */
232 bfd_elf_generic_reloc, /* special_function */
c19d1205 233 "R_ARM_THM_CALL", /* name */
7f266840 234 FALSE, /* partial_inplace */
7f6ab9f8
AM		 235 0x07ff2fff, /* src_mask */
236 0x07ff2fff, /* dst_mask */
7f266840
DJ		 237 TRUE), /* pcrel_offset */
238
07d6d2b8 239 HOWTO (R_ARM_THM_PC8, /* type */
7f266840
DJ		 240 1, /* rightshift */
241 1, /* size (0 = byte, 1 = short, 2 = long) */
242 8, /* bitsize */
243 TRUE, /* pc_relative */
244 0, /* bitpos */
245 complain_overflow_signed,/* complain_on_overflow */
246 bfd_elf_generic_reloc, /* special_function */
247 "R_ARM_THM_PC8", /* name */
248 FALSE, /* partial_inplace */
249 0x000000ff, /* src_mask */
250 0x000000ff, /* dst_mask */
251 TRUE), /* pcrel_offset */
252
c19d1205 253 HOWTO (R_ARM_BREL_ADJ, /* type */
7f266840
DJ		 254 1, /* rightshift */
255 1, /* size (0 = byte, 1 = short, 2 = long) */
c19d1205
ZW		 256 32, /* bitsize */
257 FALSE, /* pc_relative */
7f266840
DJ		 258 0, /* bitpos */
259 complain_overflow_signed,/* complain_on_overflow */
260 bfd_elf_generic_reloc, /* special_function */
c19d1205 261 "R_ARM_BREL_ADJ", /* name */
7f266840 262 FALSE, /* partial_inplace */
c19d1205
ZW		 263 0xffffffff, /* src_mask */
264 0xffffffff, /* dst_mask */
265 FALSE), /* pcrel_offset */
7f266840 266
0855e32b 267 HOWTO (R_ARM_TLS_DESC, /* type */
7f266840 268 0, /* rightshift */
0855e32b
NS		 269 2, /* size (0 = byte, 1 = short, 2 = long) */
270 32, /* bitsize */
7f266840
DJ		 271 FALSE, /* pc_relative */
272 0, /* bitpos */
0855e32b 273 complain_overflow_bitfield,/* complain_on_overflow */
7f266840 274 bfd_elf_generic_reloc, /* special_function */
0855e32b 275 "R_ARM_TLS_DESC", /* name */
7f266840 276 FALSE, /* partial_inplace */
0855e32b
NS		 277 0xffffffff, /* src_mask */
278 0xffffffff, /* dst_mask */
7f266840
DJ		 279 FALSE), /* pcrel_offset */
280
281 HOWTO (R_ARM_THM_SWI8, /* type */
282 0, /* rightshift */
283 0, /* size (0 = byte, 1 = short, 2 = long) */
284 0, /* bitsize */
285 FALSE, /* pc_relative */
286 0, /* bitpos */
287 complain_overflow_signed,/* complain_on_overflow */
288 bfd_elf_generic_reloc, /* special_function */
289 "R_ARM_SWI8", /* name */
290 FALSE, /* partial_inplace */
291 0x00000000, /* src_mask */
292 0x00000000, /* dst_mask */
293 FALSE), /* pcrel_offset */
294
295 /* BLX instruction for the ARM. */
296 HOWTO (R_ARM_XPC25, /* type */
297 2, /* rightshift */
298 2, /* size (0 = byte, 1 = short, 2 = long) */
7f6ab9f8 299 24, /* bitsize */
7f266840
DJ		 300 TRUE, /* pc_relative */
301 0, /* bitpos */
302 complain_overflow_signed,/* complain_on_overflow */
303 bfd_elf_generic_reloc, /* special_function */
304 "R_ARM_XPC25", /* name */
305 FALSE, /* partial_inplace */
306 0x00ffffff, /* src_mask */
307 0x00ffffff, /* dst_mask */
308 TRUE), /* pcrel_offset */
309
310 /* BLX instruction for the Thumb. */
311 HOWTO (R_ARM_THM_XPC22, /* type */
312 2, /* rightshift */
313 2, /* size (0 = byte, 1 = short, 2 = long) */
7f6ab9f8 314 24, /* bitsize */
7f266840
DJ		 315 TRUE, /* pc_relative */
316 0, /* bitpos */
317 complain_overflow_signed,/* complain_on_overflow */
318 bfd_elf_generic_reloc, /* special_function */
319 "R_ARM_THM_XPC22", /* name */
320 FALSE, /* partial_inplace */
7f6ab9f8
AM		 321 0x07ff2fff, /* src_mask */
322 0x07ff2fff, /* dst_mask */
7f266840
DJ		 323 TRUE), /* pcrel_offset */
324
ba93b8ac 325 /* Dynamic TLS relocations. */
7f266840 326
ba93b8ac 327 HOWTO (R_ARM_TLS_DTPMOD32, /* type */
07d6d2b8
AM		 328 0, /* rightshift */
329 2, /* size (0 = byte, 1 = short, 2 = long) */
330 32, /* bitsize */
331 FALSE, /* pc_relative */
332 0, /* bitpos */
99059e56
RM		 333 complain_overflow_bitfield,/* complain_on_overflow */
334 bfd_elf_generic_reloc, /* special_function */
335 "R_ARM_TLS_DTPMOD32", /* name */
336 TRUE, /* partial_inplace */
337 0xffffffff, /* src_mask */
338 0xffffffff, /* dst_mask */
07d6d2b8 339 FALSE), /* pcrel_offset */
7f266840 340
ba93b8ac 341 HOWTO (R_ARM_TLS_DTPOFF32, /* type */
07d6d2b8
AM		 342 0, /* rightshift */
343 2, /* size (0 = byte, 1 = short, 2 = long) */
344 32, /* bitsize */
345 FALSE, /* pc_relative */
346 0, /* bitpos */
99059e56
RM		 347 complain_overflow_bitfield,/* complain_on_overflow */
348 bfd_elf_generic_reloc, /* special_function */
349 "R_ARM_TLS_DTPOFF32", /* name */
350 TRUE, /* partial_inplace */
351 0xffffffff, /* src_mask */
352 0xffffffff, /* dst_mask */
07d6d2b8 353 FALSE), /* pcrel_offset */
7f266840 354
ba93b8ac 355 HOWTO (R_ARM_TLS_TPOFF32, /* type */
07d6d2b8
AM		 356 0, /* rightshift */
357 2, /* size (0 = byte, 1 = short, 2 = long) */
358 32, /* bitsize */
359 FALSE, /* pc_relative */
360 0, /* bitpos */
99059e56
RM		 361 complain_overflow_bitfield,/* complain_on_overflow */
362 bfd_elf_generic_reloc, /* special_function */
363 "R_ARM_TLS_TPOFF32", /* name */
364 TRUE, /* partial_inplace */
365 0xffffffff, /* src_mask */
366 0xffffffff, /* dst_mask */
07d6d2b8 367 FALSE), /* pcrel_offset */
7f266840
DJ		 368
369 /* Relocs used in ARM Linux */
370
371 HOWTO (R_ARM_COPY, /* type */
07d6d2b8
AM		 372 0, /* rightshift */
373 2, /* size (0 = byte, 1 = short, 2 = long) */
374 32, /* bitsize */
375 FALSE, /* pc_relative */
376 0, /* bitpos */
99059e56
RM		 377 complain_overflow_bitfield,/* complain_on_overflow */
378 bfd_elf_generic_reloc, /* special_function */
379 "R_ARM_COPY", /* name */
380 TRUE, /* partial_inplace */
381 0xffffffff, /* src_mask */
382 0xffffffff, /* dst_mask */
07d6d2b8 383 FALSE), /* pcrel_offset */
7f266840
DJ		 384
385 HOWTO (R_ARM_GLOB_DAT, /* type */
07d6d2b8
AM		 386 0, /* rightshift */
387 2, /* size (0 = byte, 1 = short, 2 = long) */
388 32, /* bitsize */
389 FALSE, /* pc_relative */
390 0, /* bitpos */
99059e56
RM		 391 complain_overflow_bitfield,/* complain_on_overflow */
392 bfd_elf_generic_reloc, /* special_function */
393 "R_ARM_GLOB_DAT", /* name */
394 TRUE, /* partial_inplace */
395 0xffffffff, /* src_mask */
396 0xffffffff, /* dst_mask */
07d6d2b8 397 FALSE), /* pcrel_offset */
7f266840
DJ		 398
399 HOWTO (R_ARM_JUMP_SLOT, /* type */
07d6d2b8
AM		 400 0, /* rightshift */
401 2, /* size (0 = byte, 1 = short, 2 = long) */
402 32, /* bitsize */
403 FALSE, /* pc_relative */
404 0, /* bitpos */
99059e56
RM		 405 complain_overflow_bitfield,/* complain_on_overflow */
406 bfd_elf_generic_reloc, /* special_function */
407 "R_ARM_JUMP_SLOT", /* name */
408 TRUE, /* partial_inplace */
409 0xffffffff, /* src_mask */
410 0xffffffff, /* dst_mask */
07d6d2b8 411 FALSE), /* pcrel_offset */
7f266840
DJ		 412
413 HOWTO (R_ARM_RELATIVE, /* type */
07d6d2b8
AM		 414 0, /* rightshift */
415 2, /* size (0 = byte, 1 = short, 2 = long) */
416 32, /* bitsize */
417 FALSE, /* pc_relative */
418 0, /* bitpos */
99059e56
RM		 419 complain_overflow_bitfield,/* complain_on_overflow */
420 bfd_elf_generic_reloc, /* special_function */
421 "R_ARM_RELATIVE", /* name */
422 TRUE, /* partial_inplace */
423 0xffffffff, /* src_mask */
424 0xffffffff, /* dst_mask */
07d6d2b8 425 FALSE), /* pcrel_offset */
7f266840 426
c19d1205 427 HOWTO (R_ARM_GOTOFF32, /* type */
07d6d2b8
AM		 428 0, /* rightshift */
429 2, /* size (0 = byte, 1 = short, 2 = long) */
430 32, /* bitsize */
431 FALSE, /* pc_relative */
432 0, /* bitpos */
99059e56
RM		 433 complain_overflow_bitfield,/* complain_on_overflow */
434 bfd_elf_generic_reloc, /* special_function */
435 "R_ARM_GOTOFF32", /* name */
436 TRUE, /* partial_inplace */
437 0xffffffff, /* src_mask */
438 0xffffffff, /* dst_mask */
07d6d2b8 439 FALSE), /* pcrel_offset */
7f266840
DJ		 440
441 HOWTO (R_ARM_GOTPC, /* type */
07d6d2b8
AM		 442 0, /* rightshift */
443 2, /* size (0 = byte, 1 = short, 2 = long) */
444 32, /* bitsize */
99059e56 445 TRUE, /* pc_relative */
07d6d2b8 446 0, /* bitpos */
99059e56
RM		 447 complain_overflow_bitfield,/* complain_on_overflow */
448 bfd_elf_generic_reloc, /* special_function */
449 "R_ARM_GOTPC", /* name */
450 TRUE, /* partial_inplace */
451 0xffffffff, /* src_mask */
452 0xffffffff, /* dst_mask */
453 TRUE), /* pcrel_offset */
7f266840
DJ		 454
455 HOWTO (R_ARM_GOT32, /* type */
07d6d2b8
AM		 456 0, /* rightshift */
457 2, /* size (0 = byte, 1 = short, 2 = long) */
458 32, /* bitsize */
99059e56 459 FALSE, /* pc_relative */
07d6d2b8 460 0, /* bitpos */
99059e56
RM		 461 complain_overflow_bitfield,/* complain_on_overflow */
462 bfd_elf_generic_reloc, /* special_function */
463 "R_ARM_GOT32", /* name */
464 TRUE, /* partial_inplace */
465 0xffffffff, /* src_mask */
466 0xffffffff, /* dst_mask */
467 FALSE), /* pcrel_offset */
7f266840
DJ		 468
469 HOWTO (R_ARM_PLT32, /* type */
07d6d2b8
AM		 470 2, /* rightshift */
471 2, /* size (0 = byte, 1 = short, 2 = long) */
472 24, /* bitsize */
99059e56 473 TRUE, /* pc_relative */
07d6d2b8 474 0, /* bitpos */
99059e56
RM		 475 complain_overflow_bitfield,/* complain_on_overflow */
476 bfd_elf_generic_reloc, /* special_function */
477 "R_ARM_PLT32", /* name */
478 FALSE, /* partial_inplace */
479 0x00ffffff, /* src_mask */
480 0x00ffffff, /* dst_mask */
481 TRUE), /* pcrel_offset */
7f266840
DJ		 482
483 HOWTO (R_ARM_CALL, /* type */
484 2, /* rightshift */
485 2, /* size (0 = byte, 1 = short, 2 = long) */
486 24, /* bitsize */
487 TRUE, /* pc_relative */
488 0, /* bitpos */
489 complain_overflow_signed,/* complain_on_overflow */
490 bfd_elf_generic_reloc, /* special_function */
491 "R_ARM_CALL", /* name */
492 FALSE, /* partial_inplace */
493 0x00ffffff, /* src_mask */
494 0x00ffffff, /* dst_mask */
495 TRUE), /* pcrel_offset */
496
497 HOWTO (R_ARM_JUMP24, /* type */
498 2, /* rightshift */
499 2, /* size (0 = byte, 1 = short, 2 = long) */
500 24, /* bitsize */
501 TRUE, /* pc_relative */
502 0, /* bitpos */
503 complain_overflow_signed,/* complain_on_overflow */
504 bfd_elf_generic_reloc, /* special_function */
505 "R_ARM_JUMP24", /* name */
506 FALSE, /* partial_inplace */
507 0x00ffffff, /* src_mask */
508 0x00ffffff, /* dst_mask */
509 TRUE), /* pcrel_offset */
510
c19d1205
ZW		 511 HOWTO (R_ARM_THM_JUMP24, /* type */
512 1, /* rightshift */
513 2, /* size (0 = byte, 1 = short, 2 = long) */
514 24, /* bitsize */
515 TRUE, /* pc_relative */
7f266840 516 0, /* bitpos */
c19d1205 517 complain_overflow_signed,/* complain_on_overflow */
7f266840 518 bfd_elf_generic_reloc, /* special_function */
c19d1205 519 "R_ARM_THM_JUMP24", /* name */
7f266840 520 FALSE, /* partial_inplace */
c19d1205
ZW		 521 0x07ff2fff, /* src_mask */
522 0x07ff2fff, /* dst_mask */
523 TRUE), /* pcrel_offset */
7f266840 524
c19d1205 525 HOWTO (R_ARM_BASE_ABS, /* type */
7f266840 526 0, /* rightshift */
c19d1205
ZW		 527 2, /* size (0 = byte, 1 = short, 2 = long) */
528 32, /* bitsize */
7f266840
DJ		 529 FALSE, /* pc_relative */
530 0, /* bitpos */
531 complain_overflow_dont,/* complain_on_overflow */
532 bfd_elf_generic_reloc, /* special_function */
c19d1205 533 "R_ARM_BASE_ABS", /* name */
7f266840 534 FALSE, /* partial_inplace */
c19d1205
ZW		 535 0xffffffff, /* src_mask */
536 0xffffffff, /* dst_mask */
7f266840
DJ		 537 FALSE), /* pcrel_offset */
538
539 HOWTO (R_ARM_ALU_PCREL7_0, /* type */
540 0, /* rightshift */
541 2, /* size (0 = byte, 1 = short, 2 = long) */
542 12, /* bitsize */
543 TRUE, /* pc_relative */
544 0, /* bitpos */
545 complain_overflow_dont,/* complain_on_overflow */
546 bfd_elf_generic_reloc, /* special_function */
547 "R_ARM_ALU_PCREL_7_0", /* name */
548 FALSE, /* partial_inplace */
549 0x00000fff, /* src_mask */
550 0x00000fff, /* dst_mask */
551 TRUE), /* pcrel_offset */
552
553 HOWTO (R_ARM_ALU_PCREL15_8, /* type */
554 0, /* rightshift */
555 2, /* size (0 = byte, 1 = short, 2 = long) */
556 12, /* bitsize */
557 TRUE, /* pc_relative */
558 8, /* bitpos */
559 complain_overflow_dont,/* complain_on_overflow */
560 bfd_elf_generic_reloc, /* special_function */
561 "R_ARM_ALU_PCREL_15_8",/* name */
562 FALSE, /* partial_inplace */
563 0x00000fff, /* src_mask */
564 0x00000fff, /* dst_mask */
565 TRUE), /* pcrel_offset */
566
567 HOWTO (R_ARM_ALU_PCREL23_15, /* type */
568 0, /* rightshift */
569 2, /* size (0 = byte, 1 = short, 2 = long) */
570 12, /* bitsize */
571 TRUE, /* pc_relative */
572 16, /* bitpos */
573 complain_overflow_dont,/* complain_on_overflow */
574 bfd_elf_generic_reloc, /* special_function */
575 "R_ARM_ALU_PCREL_23_15",/* name */
576 FALSE, /* partial_inplace */
577 0x00000fff, /* src_mask */
578 0x00000fff, /* dst_mask */
579 TRUE), /* pcrel_offset */
580
581 HOWTO (R_ARM_LDR_SBREL_11_0, /* type */
582 0, /* rightshift */
583 2, /* size (0 = byte, 1 = short, 2 = long) */
584 12, /* bitsize */
585 FALSE, /* pc_relative */
586 0, /* bitpos */
587 complain_overflow_dont,/* complain_on_overflow */
588 bfd_elf_generic_reloc, /* special_function */
589 "R_ARM_LDR_SBREL_11_0",/* name */
590 FALSE, /* partial_inplace */
591 0x00000fff, /* src_mask */
592 0x00000fff, /* dst_mask */
593 FALSE), /* pcrel_offset */
594
595 HOWTO (R_ARM_ALU_SBREL_19_12, /* type */
596 0, /* rightshift */
597 2, /* size (0 = byte, 1 = short, 2 = long) */
598 8, /* bitsize */
599 FALSE, /* pc_relative */
600 12, /* bitpos */
601 complain_overflow_dont,/* complain_on_overflow */
602 bfd_elf_generic_reloc, /* special_function */
603 "R_ARM_ALU_SBREL_19_12",/* name */
604 FALSE, /* partial_inplace */
605 0x000ff000, /* src_mask */
606 0x000ff000, /* dst_mask */
607 FALSE), /* pcrel_offset */
608
609 HOWTO (R_ARM_ALU_SBREL_27_20, /* type */
610 0, /* rightshift */
611 2, /* size (0 = byte, 1 = short, 2 = long) */
612 8, /* bitsize */
613 FALSE, /* pc_relative */
614 20, /* bitpos */
615 complain_overflow_dont,/* complain_on_overflow */
616 bfd_elf_generic_reloc, /* special_function */
617 "R_ARM_ALU_SBREL_27_20",/* name */
618 FALSE, /* partial_inplace */
619 0x0ff00000, /* src_mask */
620 0x0ff00000, /* dst_mask */
621 FALSE), /* pcrel_offset */
622
623 HOWTO (R_ARM_TARGET1, /* type */
624 0, /* rightshift */
625 2, /* size (0 = byte, 1 = short, 2 = long) */
626 32, /* bitsize */
627 FALSE, /* pc_relative */
628 0, /* bitpos */
629 complain_overflow_dont,/* complain_on_overflow */
630 bfd_elf_generic_reloc, /* special_function */
631 "R_ARM_TARGET1", /* name */
632 FALSE, /* partial_inplace */
633 0xffffffff, /* src_mask */
634 0xffffffff, /* dst_mask */
635 FALSE), /* pcrel_offset */
636
637 HOWTO (R_ARM_ROSEGREL32, /* type */
638 0, /* rightshift */
639 2, /* size (0 = byte, 1 = short, 2 = long) */
640 32, /* bitsize */
641 FALSE, /* pc_relative */
642 0, /* bitpos */
643 complain_overflow_dont,/* complain_on_overflow */
644 bfd_elf_generic_reloc, /* special_function */
645 "R_ARM_ROSEGREL32", /* name */
646 FALSE, /* partial_inplace */
647 0xffffffff, /* src_mask */
648 0xffffffff, /* dst_mask */
649 FALSE), /* pcrel_offset */
650
651 HOWTO (R_ARM_V4BX, /* type */
652 0, /* rightshift */
653 2, /* size (0 = byte, 1 = short, 2 = long) */
654 32, /* bitsize */
655 FALSE, /* pc_relative */
656 0, /* bitpos */
657 complain_overflow_dont,/* complain_on_overflow */
658 bfd_elf_generic_reloc, /* special_function */
659 "R_ARM_V4BX", /* name */
660 FALSE, /* partial_inplace */
661 0xffffffff, /* src_mask */
662 0xffffffff, /* dst_mask */
663 FALSE), /* pcrel_offset */
664
665 HOWTO (R_ARM_TARGET2, /* type */
666 0, /* rightshift */
667 2, /* size (0 = byte, 1 = short, 2 = long) */
668 32, /* bitsize */
669 FALSE, /* pc_relative */
670 0, /* bitpos */
671 complain_overflow_signed,/* complain_on_overflow */
672 bfd_elf_generic_reloc, /* special_function */
673 "R_ARM_TARGET2", /* name */
674 FALSE, /* partial_inplace */
675 0xffffffff, /* src_mask */
676 0xffffffff, /* dst_mask */
677 TRUE), /* pcrel_offset */
678
679 HOWTO (R_ARM_PREL31, /* type */
680 0, /* rightshift */
681 2, /* size (0 = byte, 1 = short, 2 = long) */
682 31, /* bitsize */
683 TRUE, /* pc_relative */
684 0, /* bitpos */
685 complain_overflow_signed,/* complain_on_overflow */
686 bfd_elf_generic_reloc, /* special_function */
687 "R_ARM_PREL31", /* name */
688 FALSE, /* partial_inplace */
689 0x7fffffff, /* src_mask */
690 0x7fffffff, /* dst_mask */
691 TRUE), /* pcrel_offset */
c19d1205
ZW		 692
693 HOWTO (R_ARM_MOVW_ABS_NC, /* type */
694 0, /* rightshift */
695 2, /* size (0 = byte, 1 = short, 2 = long) */
696 16, /* bitsize */
697 FALSE, /* pc_relative */
698 0, /* bitpos */
699 complain_overflow_dont,/* complain_on_overflow */
700 bfd_elf_generic_reloc, /* special_function */
701 "R_ARM_MOVW_ABS_NC", /* name */
702 FALSE, /* partial_inplace */
39623e12
PB		 703 0x000f0fff, /* src_mask */
704 0x000f0fff, /* dst_mask */
c19d1205
ZW		 705 FALSE), /* pcrel_offset */
706
707 HOWTO (R_ARM_MOVT_ABS, /* type */
708 0, /* rightshift */
709 2, /* size (0 = byte, 1 = short, 2 = long) */
710 16, /* bitsize */
711 FALSE, /* pc_relative */
712 0, /* bitpos */
713 complain_overflow_bitfield,/* complain_on_overflow */
714 bfd_elf_generic_reloc, /* special_function */
715 "R_ARM_MOVT_ABS", /* name */
716 FALSE, /* partial_inplace */
39623e12
PB		 717 0x000f0fff, /* src_mask */
718 0x000f0fff, /* dst_mask */
c19d1205
ZW		 719 FALSE), /* pcrel_offset */
720
721 HOWTO (R_ARM_MOVW_PREL_NC, /* type */
722 0, /* rightshift */
723 2, /* size (0 = byte, 1 = short, 2 = long) */
724 16, /* bitsize */
725 TRUE, /* pc_relative */
726 0, /* bitpos */
727 complain_overflow_dont,/* complain_on_overflow */
728 bfd_elf_generic_reloc, /* special_function */
729 "R_ARM_MOVW_PREL_NC", /* name */
730 FALSE, /* partial_inplace */
39623e12
PB		 731 0x000f0fff, /* src_mask */
732 0x000f0fff, /* dst_mask */
c19d1205
ZW		 733 TRUE), /* pcrel_offset */
734
735 HOWTO (R_ARM_MOVT_PREL, /* type */
736 0, /* rightshift */
737 2, /* size (0 = byte, 1 = short, 2 = long) */
738 16, /* bitsize */
739 TRUE, /* pc_relative */
740 0, /* bitpos */
741 complain_overflow_bitfield,/* complain_on_overflow */
742 bfd_elf_generic_reloc, /* special_function */
743 "R_ARM_MOVT_PREL", /* name */
744 FALSE, /* partial_inplace */
39623e12
PB		 745 0x000f0fff, /* src_mask */
746 0x000f0fff, /* dst_mask */
c19d1205
ZW		 747 TRUE), /* pcrel_offset */
748
749 HOWTO (R_ARM_THM_MOVW_ABS_NC, /* type */
750 0, /* rightshift */
751 2, /* size (0 = byte, 1 = short, 2 = long) */
752 16, /* bitsize */
753 FALSE, /* pc_relative */
754 0, /* bitpos */
755 complain_overflow_dont,/* complain_on_overflow */
756 bfd_elf_generic_reloc, /* special_function */
757 "R_ARM_THM_MOVW_ABS_NC",/* name */
758 FALSE, /* partial_inplace */
759 0x040f70ff, /* src_mask */
760 0x040f70ff, /* dst_mask */
761 FALSE), /* pcrel_offset */
762
763 HOWTO (R_ARM_THM_MOVT_ABS, /* type */
764 0, /* rightshift */
765 2, /* size (0 = byte, 1 = short, 2 = long) */
766 16, /* bitsize */
767 FALSE, /* pc_relative */
768 0, /* bitpos */
769 complain_overflow_bitfield,/* complain_on_overflow */
770 bfd_elf_generic_reloc, /* special_function */
771 "R_ARM_THM_MOVT_ABS", /* name */
772 FALSE, /* partial_inplace */
773 0x040f70ff, /* src_mask */
774 0x040f70ff, /* dst_mask */
775 FALSE), /* pcrel_offset */
776
777 HOWTO (R_ARM_THM_MOVW_PREL_NC,/* type */
778 0, /* rightshift */
779 2, /* size (0 = byte, 1 = short, 2 = long) */
780 16, /* bitsize */
781 TRUE, /* pc_relative */
782 0, /* bitpos */
783 complain_overflow_dont,/* complain_on_overflow */
784 bfd_elf_generic_reloc, /* special_function */
785 "R_ARM_THM_MOVW_PREL_NC",/* name */
786 FALSE, /* partial_inplace */
787 0x040f70ff, /* src_mask */
788 0x040f70ff, /* dst_mask */
789 TRUE), /* pcrel_offset */
790
791 HOWTO (R_ARM_THM_MOVT_PREL, /* type */
792 0, /* rightshift */
793 2, /* size (0 = byte, 1 = short, 2 = long) */
794 16, /* bitsize */
795 TRUE, /* pc_relative */
796 0, /* bitpos */
797 complain_overflow_bitfield,/* complain_on_overflow */
798 bfd_elf_generic_reloc, /* special_function */
799 "R_ARM_THM_MOVT_PREL", /* name */
800 FALSE, /* partial_inplace */
801 0x040f70ff, /* src_mask */
802 0x040f70ff, /* dst_mask */
803 TRUE), /* pcrel_offset */
804
805 HOWTO (R_ARM_THM_JUMP19, /* type */
806 1, /* rightshift */
807 2, /* size (0 = byte, 1 = short, 2 = long) */
808 19, /* bitsize */
809 TRUE, /* pc_relative */
810 0, /* bitpos */
811 complain_overflow_signed,/* complain_on_overflow */
812 bfd_elf_generic_reloc, /* special_function */
813 "R_ARM_THM_JUMP19", /* name */
814 FALSE, /* partial_inplace */
815 0x043f2fff, /* src_mask */
816 0x043f2fff, /* dst_mask */
817 TRUE), /* pcrel_offset */
818
819 HOWTO (R_ARM_THM_JUMP6, /* type */
820 1, /* rightshift */
821 1, /* size (0 = byte, 1 = short, 2 = long) */
822 6, /* bitsize */
823 TRUE, /* pc_relative */
824 0, /* bitpos */
825 complain_overflow_unsigned,/* complain_on_overflow */
826 bfd_elf_generic_reloc, /* special_function */
827 "R_ARM_THM_JUMP6", /* name */
828 FALSE, /* partial_inplace */
829 0x02f8, /* src_mask */
830 0x02f8, /* dst_mask */
831 TRUE), /* pcrel_offset */
832
833 /* These are declared as 13-bit signed relocations because we can
834 address -4095 .. 4095(base) by altering ADDW to SUBW or vice
835 versa. */
836 HOWTO (R_ARM_THM_ALU_PREL_11_0,/* type */
837 0, /* rightshift */
838 2, /* size (0 = byte, 1 = short, 2 = long) */
839 13, /* bitsize */
840 TRUE, /* pc_relative */
841 0, /* bitpos */
2cab6cc3 842 complain_overflow_dont,/* complain_on_overflow */
c19d1205
ZW		 843 bfd_elf_generic_reloc, /* special_function */
844 "R_ARM_THM_ALU_PREL_11_0",/* name */
845 FALSE, /* partial_inplace */
2cab6cc3
MS		 846 0xffffffff, /* src_mask */
847 0xffffffff, /* dst_mask */
c19d1205
ZW		 848 TRUE), /* pcrel_offset */
849
850 HOWTO (R_ARM_THM_PC12, /* type */
851 0, /* rightshift */
852 2, /* size (0 = byte, 1 = short, 2 = long) */
853 13, /* bitsize */
854 TRUE, /* pc_relative */
855 0, /* bitpos */
2cab6cc3 856 complain_overflow_dont,/* complain_on_overflow */
c19d1205
ZW		 857 bfd_elf_generic_reloc, /* special_function */
858 "R_ARM_THM_PC12", /* name */
859 FALSE, /* partial_inplace */
2cab6cc3
MS		 860 0xffffffff, /* src_mask */
861 0xffffffff, /* dst_mask */
c19d1205
ZW		 862 TRUE), /* pcrel_offset */
863
864 HOWTO (R_ARM_ABS32_NOI, /* type */
865 0, /* rightshift */
866 2, /* size (0 = byte, 1 = short, 2 = long) */
867 32, /* bitsize */
868 FALSE, /* pc_relative */
869 0, /* bitpos */
870 complain_overflow_dont,/* complain_on_overflow */
871 bfd_elf_generic_reloc, /* special_function */
872 "R_ARM_ABS32_NOI", /* name */
873 FALSE, /* partial_inplace */
874 0xffffffff, /* src_mask */
875 0xffffffff, /* dst_mask */
876 FALSE), /* pcrel_offset */
877
878 HOWTO (R_ARM_REL32_NOI, /* type */
879 0, /* rightshift */
880 2, /* size (0 = byte, 1 = short, 2 = long) */
881 32, /* bitsize */
882 TRUE, /* pc_relative */
883 0, /* bitpos */
884 complain_overflow_dont,/* complain_on_overflow */
885 bfd_elf_generic_reloc, /* special_function */
886 "R_ARM_REL32_NOI", /* name */
887 FALSE, /* partial_inplace */
888 0xffffffff, /* src_mask */
889 0xffffffff, /* dst_mask */
890 FALSE), /* pcrel_offset */
7f266840 891
4962c51a
MS		 892 /* Group relocations. */
893
894 HOWTO (R_ARM_ALU_PC_G0_NC, /* type */
895 0, /* rightshift */
896 2, /* size (0 = byte, 1 = short, 2 = long) */
897 32, /* bitsize */
898 TRUE, /* pc_relative */
899 0, /* bitpos */
900 complain_overflow_dont,/* complain_on_overflow */
901 bfd_elf_generic_reloc, /* special_function */
902 "R_ARM_ALU_PC_G0_NC", /* name */
903 FALSE, /* partial_inplace */
904 0xffffffff, /* src_mask */
905 0xffffffff, /* dst_mask */
906 TRUE), /* pcrel_offset */
907
07d6d2b8 908 HOWTO (R_ARM_ALU_PC_G0, /* type */
4962c51a
MS		 909 0, /* rightshift */
910 2, /* size (0 = byte, 1 = short, 2 = long) */
911 32, /* bitsize */
912 TRUE, /* pc_relative */
913 0, /* bitpos */
914 complain_overflow_dont,/* complain_on_overflow */
915 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 916 "R_ARM_ALU_PC_G0", /* name */
4962c51a
MS		 917 FALSE, /* partial_inplace */
918 0xffffffff, /* src_mask */
919 0xffffffff, /* dst_mask */
920 TRUE), /* pcrel_offset */
921
922 HOWTO (R_ARM_ALU_PC_G1_NC, /* type */
923 0, /* rightshift */
924 2, /* size (0 = byte, 1 = short, 2 = long) */
925 32, /* bitsize */
926 TRUE, /* pc_relative */
927 0, /* bitpos */
928 complain_overflow_dont,/* complain_on_overflow */
929 bfd_elf_generic_reloc, /* special_function */
930 "R_ARM_ALU_PC_G1_NC", /* name */
931 FALSE, /* partial_inplace */
932 0xffffffff, /* src_mask */
933 0xffffffff, /* dst_mask */
934 TRUE), /* pcrel_offset */
935
07d6d2b8 936 HOWTO (R_ARM_ALU_PC_G1, /* type */
4962c51a
MS		 937 0, /* rightshift */
938 2, /* size (0 = byte, 1 = short, 2 = long) */
939 32, /* bitsize */
940 TRUE, /* pc_relative */
941 0, /* bitpos */
942 complain_overflow_dont,/* complain_on_overflow */
943 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 944 "R_ARM_ALU_PC_G1", /* name */
4962c51a
MS		 945 FALSE, /* partial_inplace */
946 0xffffffff, /* src_mask */
947 0xffffffff, /* dst_mask */
948 TRUE), /* pcrel_offset */
949
07d6d2b8 950 HOWTO (R_ARM_ALU_PC_G2, /* type */
4962c51a
MS		 951 0, /* rightshift */
952 2, /* size (0 = byte, 1 = short, 2 = long) */
953 32, /* bitsize */
954 TRUE, /* pc_relative */
955 0, /* bitpos */
956 complain_overflow_dont,/* complain_on_overflow */
957 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 958 "R_ARM_ALU_PC_G2", /* name */
4962c51a
MS		 959 FALSE, /* partial_inplace */
960 0xffffffff, /* src_mask */
961 0xffffffff, /* dst_mask */
962 TRUE), /* pcrel_offset */
963
07d6d2b8 964 HOWTO (R_ARM_LDR_PC_G1, /* type */
4962c51a
MS		 965 0, /* rightshift */
966 2, /* size (0 = byte, 1 = short, 2 = long) */
967 32, /* bitsize */
968 TRUE, /* pc_relative */
969 0, /* bitpos */
970 complain_overflow_dont,/* complain_on_overflow */
971 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 972 "R_ARM_LDR_PC_G1", /* name */
4962c51a
MS		 973 FALSE, /* partial_inplace */
974 0xffffffff, /* src_mask */
975 0xffffffff, /* dst_mask */
976 TRUE), /* pcrel_offset */
977
07d6d2b8 978 HOWTO (R_ARM_LDR_PC_G2, /* type */
4962c51a
MS		 979 0, /* rightshift */
980 2, /* size (0 = byte, 1 = short, 2 = long) */
981 32, /* bitsize */
982 TRUE, /* pc_relative */
983 0, /* bitpos */
984 complain_overflow_dont,/* complain_on_overflow */
985 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 986 "R_ARM_LDR_PC_G2", /* name */
4962c51a
MS		 987 FALSE, /* partial_inplace */
988 0xffffffff, /* src_mask */
989 0xffffffff, /* dst_mask */
990 TRUE), /* pcrel_offset */
991
07d6d2b8 992 HOWTO (R_ARM_LDRS_PC_G0, /* type */
4962c51a
MS		 993 0, /* rightshift */
994 2, /* size (0 = byte, 1 = short, 2 = long) */
995 32, /* bitsize */
996 TRUE, /* pc_relative */
997 0, /* bitpos */
998 complain_overflow_dont,/* complain_on_overflow */
999 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1000 "R_ARM_LDRS_PC_G0", /* name */
4962c51a
MS		 1001 FALSE, /* partial_inplace */
1002 0xffffffff, /* src_mask */
1003 0xffffffff, /* dst_mask */
1004 TRUE), /* pcrel_offset */
1005
07d6d2b8 1006 HOWTO (R_ARM_LDRS_PC_G1, /* type */
4962c51a
MS		 1007 0, /* rightshift */
1008 2, /* size (0 = byte, 1 = short, 2 = long) */
1009 32, /* bitsize */
1010 TRUE, /* pc_relative */
1011 0, /* bitpos */
1012 complain_overflow_dont,/* complain_on_overflow */
1013 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1014 "R_ARM_LDRS_PC_G1", /* name */
4962c51a
MS		 1015 FALSE, /* partial_inplace */
1016 0xffffffff, /* src_mask */
1017 0xffffffff, /* dst_mask */
1018 TRUE), /* pcrel_offset */
1019
07d6d2b8 1020 HOWTO (R_ARM_LDRS_PC_G2, /* type */
4962c51a
MS		 1021 0, /* rightshift */
1022 2, /* size (0 = byte, 1 = short, 2 = long) */
1023 32, /* bitsize */
1024 TRUE, /* pc_relative */
1025 0, /* bitpos */
1026 complain_overflow_dont,/* complain_on_overflow */
1027 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1028 "R_ARM_LDRS_PC_G2", /* name */
4962c51a
MS		 1029 FALSE, /* partial_inplace */
1030 0xffffffff, /* src_mask */
1031 0xffffffff, /* dst_mask */
1032 TRUE), /* pcrel_offset */
1033
07d6d2b8 1034 HOWTO (R_ARM_LDC_PC_G0, /* type */
4962c51a
MS		 1035 0, /* rightshift */
1036 2, /* size (0 = byte, 1 = short, 2 = long) */
1037 32, /* bitsize */
1038 TRUE, /* pc_relative */
1039 0, /* bitpos */
1040 complain_overflow_dont,/* complain_on_overflow */
1041 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1042 "R_ARM_LDC_PC_G0", /* name */
4962c51a
MS		 1043 FALSE, /* partial_inplace */
1044 0xffffffff, /* src_mask */
1045 0xffffffff, /* dst_mask */
1046 TRUE), /* pcrel_offset */
1047
07d6d2b8 1048 HOWTO (R_ARM_LDC_PC_G1, /* type */
4962c51a
MS		 1049 0, /* rightshift */
1050 2, /* size (0 = byte, 1 = short, 2 = long) */
1051 32, /* bitsize */
1052 TRUE, /* pc_relative */
1053 0, /* bitpos */
1054 complain_overflow_dont,/* complain_on_overflow */
1055 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1056 "R_ARM_LDC_PC_G1", /* name */
4962c51a
MS		 1057 FALSE, /* partial_inplace */
1058 0xffffffff, /* src_mask */
1059 0xffffffff, /* dst_mask */
1060 TRUE), /* pcrel_offset */
1061
07d6d2b8 1062 HOWTO (R_ARM_LDC_PC_G2, /* type */
4962c51a
MS		 1063 0, /* rightshift */
1064 2, /* size (0 = byte, 1 = short, 2 = long) */
1065 32, /* bitsize */
1066 TRUE, /* pc_relative */
1067 0, /* bitpos */
1068 complain_overflow_dont,/* complain_on_overflow */
1069 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1070 "R_ARM_LDC_PC_G2", /* name */
4962c51a
MS		 1071 FALSE, /* partial_inplace */
1072 0xffffffff, /* src_mask */
1073 0xffffffff, /* dst_mask */
1074 TRUE), /* pcrel_offset */
1075
07d6d2b8 1076 HOWTO (R_ARM_ALU_SB_G0_NC, /* type */
4962c51a
MS		 1077 0, /* rightshift */
1078 2, /* size (0 = byte, 1 = short, 2 = long) */
1079 32, /* bitsize */
1080 TRUE, /* pc_relative */
1081 0, /* bitpos */
1082 complain_overflow_dont,/* complain_on_overflow */
1083 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1084 "R_ARM_ALU_SB_G0_NC", /* name */
4962c51a
MS		 1085 FALSE, /* partial_inplace */
1086 0xffffffff, /* src_mask */
1087 0xffffffff, /* dst_mask */
1088 TRUE), /* pcrel_offset */
1089
07d6d2b8 1090 HOWTO (R_ARM_ALU_SB_G0, /* type */
4962c51a
MS		 1091 0, /* rightshift */
1092 2, /* size (0 = byte, 1 = short, 2 = long) */
1093 32, /* bitsize */
1094 TRUE, /* pc_relative */
1095 0, /* bitpos */
1096 complain_overflow_dont,/* complain_on_overflow */
1097 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1098 "R_ARM_ALU_SB_G0", /* name */
4962c51a
MS		 1099 FALSE, /* partial_inplace */
1100 0xffffffff, /* src_mask */
1101 0xffffffff, /* dst_mask */
1102 TRUE), /* pcrel_offset */
1103
07d6d2b8 1104 HOWTO (R_ARM_ALU_SB_G1_NC, /* type */
4962c51a
MS		 1105 0, /* rightshift */
1106 2, /* size (0 = byte, 1 = short, 2 = long) */
1107 32, /* bitsize */
1108 TRUE, /* pc_relative */
1109 0, /* bitpos */
1110 complain_overflow_dont,/* complain_on_overflow */
1111 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1112 "R_ARM_ALU_SB_G1_NC", /* name */
4962c51a
MS		 1113 FALSE, /* partial_inplace */
1114 0xffffffff, /* src_mask */
1115 0xffffffff, /* dst_mask */
1116 TRUE), /* pcrel_offset */
1117
07d6d2b8 1118 HOWTO (R_ARM_ALU_SB_G1, /* type */
4962c51a
MS		 1119 0, /* rightshift */
1120 2, /* size (0 = byte, 1 = short, 2 = long) */
1121 32, /* bitsize */
1122 TRUE, /* pc_relative */
1123 0, /* bitpos */
1124 complain_overflow_dont,/* complain_on_overflow */
1125 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1126 "R_ARM_ALU_SB_G1", /* name */
4962c51a
MS		 1127 FALSE, /* partial_inplace */
1128 0xffffffff, /* src_mask */
1129 0xffffffff, /* dst_mask */
1130 TRUE), /* pcrel_offset */
1131
07d6d2b8 1132 HOWTO (R_ARM_ALU_SB_G2, /* type */
4962c51a
MS		 1133 0, /* rightshift */
1134 2, /* size (0 = byte, 1 = short, 2 = long) */
1135 32, /* bitsize */
1136 TRUE, /* pc_relative */
1137 0, /* bitpos */
1138 complain_overflow_dont,/* complain_on_overflow */
1139 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1140 "R_ARM_ALU_SB_G2", /* name */
4962c51a
MS		 1141 FALSE, /* partial_inplace */
1142 0xffffffff, /* src_mask */
1143 0xffffffff, /* dst_mask */
1144 TRUE), /* pcrel_offset */
1145
07d6d2b8 1146 HOWTO (R_ARM_LDR_SB_G0, /* type */
4962c51a
MS		 1147 0, /* rightshift */
1148 2, /* size (0 = byte, 1 = short, 2 = long) */
1149 32, /* bitsize */
1150 TRUE, /* pc_relative */
1151 0, /* bitpos */
1152 complain_overflow_dont,/* complain_on_overflow */
1153 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1154 "R_ARM_LDR_SB_G0", /* name */
4962c51a
MS		 1155 FALSE, /* partial_inplace */
1156 0xffffffff, /* src_mask */
1157 0xffffffff, /* dst_mask */
1158 TRUE), /* pcrel_offset */
1159
07d6d2b8 1160 HOWTO (R_ARM_LDR_SB_G1, /* type */
4962c51a
MS		 1161 0, /* rightshift */
1162 2, /* size (0 = byte, 1 = short, 2 = long) */
1163 32, /* bitsize */
1164 TRUE, /* pc_relative */
1165 0, /* bitpos */
1166 complain_overflow_dont,/* complain_on_overflow */
1167 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1168 "R_ARM_LDR_SB_G1", /* name */
4962c51a
MS		 1169 FALSE, /* partial_inplace */
1170 0xffffffff, /* src_mask */
1171 0xffffffff, /* dst_mask */
1172 TRUE), /* pcrel_offset */
1173
07d6d2b8 1174 HOWTO (R_ARM_LDR_SB_G2, /* type */
4962c51a
MS		 1175 0, /* rightshift */
1176 2, /* size (0 = byte, 1 = short, 2 = long) */
1177 32, /* bitsize */
1178 TRUE, /* pc_relative */
1179 0, /* bitpos */
1180 complain_overflow_dont,/* complain_on_overflow */
1181 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1182 "R_ARM_LDR_SB_G2", /* name */
4962c51a
MS		 1183 FALSE, /* partial_inplace */
1184 0xffffffff, /* src_mask */
1185 0xffffffff, /* dst_mask */
1186 TRUE), /* pcrel_offset */
1187
07d6d2b8 1188 HOWTO (R_ARM_LDRS_SB_G0, /* type */
4962c51a
MS		 1189 0, /* rightshift */
1190 2, /* size (0 = byte, 1 = short, 2 = long) */
1191 32, /* bitsize */
1192 TRUE, /* pc_relative */
1193 0, /* bitpos */
1194 complain_overflow_dont,/* complain_on_overflow */
1195 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1196 "R_ARM_LDRS_SB_G0", /* name */
4962c51a
MS		 1197 FALSE, /* partial_inplace */
1198 0xffffffff, /* src_mask */
1199 0xffffffff, /* dst_mask */
1200 TRUE), /* pcrel_offset */
1201
07d6d2b8 1202 HOWTO (R_ARM_LDRS_SB_G1, /* type */
4962c51a
MS		 1203 0, /* rightshift */
1204 2, /* size (0 = byte, 1 = short, 2 = long) */
1205 32, /* bitsize */
1206 TRUE, /* pc_relative */
1207 0, /* bitpos */
1208 complain_overflow_dont,/* complain_on_overflow */
1209 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1210 "R_ARM_LDRS_SB_G1", /* name */
4962c51a
MS		 1211 FALSE, /* partial_inplace */
1212 0xffffffff, /* src_mask */
1213 0xffffffff, /* dst_mask */
1214 TRUE), /* pcrel_offset */
1215
07d6d2b8 1216 HOWTO (R_ARM_LDRS_SB_G2, /* type */
4962c51a
MS		 1217 0, /* rightshift */
1218 2, /* size (0 = byte, 1 = short, 2 = long) */
1219 32, /* bitsize */
1220 TRUE, /* pc_relative */
1221 0, /* bitpos */
1222 complain_overflow_dont,/* complain_on_overflow */
1223 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1224 "R_ARM_LDRS_SB_G2", /* name */
4962c51a
MS		 1225 FALSE, /* partial_inplace */
1226 0xffffffff, /* src_mask */
1227 0xffffffff, /* dst_mask */
1228 TRUE), /* pcrel_offset */
1229
07d6d2b8 1230 HOWTO (R_ARM_LDC_SB_G0, /* type */
4962c51a
MS		 1231 0, /* rightshift */
1232 2, /* size (0 = byte, 1 = short, 2 = long) */
1233 32, /* bitsize */
1234 TRUE, /* pc_relative */
1235 0, /* bitpos */
1236 complain_overflow_dont,/* complain_on_overflow */
1237 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1238 "R_ARM_LDC_SB_G0", /* name */
4962c51a
MS		 1239 FALSE, /* partial_inplace */
1240 0xffffffff, /* src_mask */
1241 0xffffffff, /* dst_mask */
1242 TRUE), /* pcrel_offset */
1243
07d6d2b8 1244 HOWTO (R_ARM_LDC_SB_G1, /* type */
4962c51a
MS		 1245 0, /* rightshift */
1246 2, /* size (0 = byte, 1 = short, 2 = long) */
1247 32, /* bitsize */
1248 TRUE, /* pc_relative */
1249 0, /* bitpos */
1250 complain_overflow_dont,/* complain_on_overflow */
1251 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1252 "R_ARM_LDC_SB_G1", /* name */
4962c51a
MS		 1253 FALSE, /* partial_inplace */
1254 0xffffffff, /* src_mask */
1255 0xffffffff, /* dst_mask */
1256 TRUE), /* pcrel_offset */
1257
07d6d2b8 1258 HOWTO (R_ARM_LDC_SB_G2, /* type */
4962c51a
MS		 1259 0, /* rightshift */
1260 2, /* size (0 = byte, 1 = short, 2 = long) */
1261 32, /* bitsize */
1262 TRUE, /* pc_relative */
1263 0, /* bitpos */
1264 complain_overflow_dont,/* complain_on_overflow */
1265 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1266 "R_ARM_LDC_SB_G2", /* name */
4962c51a
MS		 1267 FALSE, /* partial_inplace */
1268 0xffffffff, /* src_mask */
1269 0xffffffff, /* dst_mask */
1270 TRUE), /* pcrel_offset */
1271
1272 /* End of group relocations. */
c19d1205 1273
c19d1205
ZW		 1274 HOWTO (R_ARM_MOVW_BREL_NC, /* type */
1275 0, /* rightshift */
1276 2, /* size (0 = byte, 1 = short, 2 = long) */
1277 16, /* bitsize */
1278 FALSE, /* pc_relative */
1279 0, /* bitpos */
1280 complain_overflow_dont,/* complain_on_overflow */
1281 bfd_elf_generic_reloc, /* special_function */
1282 "R_ARM_MOVW_BREL_NC", /* name */
1283 FALSE, /* partial_inplace */
1284 0x0000ffff, /* src_mask */
1285 0x0000ffff, /* dst_mask */
1286 FALSE), /* pcrel_offset */
1287
1288 HOWTO (R_ARM_MOVT_BREL, /* type */
1289 0, /* rightshift */
1290 2, /* size (0 = byte, 1 = short, 2 = long) */
1291 16, /* bitsize */
1292 FALSE, /* pc_relative */
1293 0, /* bitpos */
1294 complain_overflow_bitfield,/* complain_on_overflow */
1295 bfd_elf_generic_reloc, /* special_function */
1296 "R_ARM_MOVT_BREL", /* name */
1297 FALSE, /* partial_inplace */
1298 0x0000ffff, /* src_mask */
1299 0x0000ffff, /* dst_mask */
1300 FALSE), /* pcrel_offset */
1301
1302 HOWTO (R_ARM_MOVW_BREL, /* type */
1303 0, /* rightshift */
1304 2, /* size (0 = byte, 1 = short, 2 = long) */
1305 16, /* bitsize */
1306 FALSE, /* pc_relative */
1307 0, /* bitpos */
1308 complain_overflow_dont,/* complain_on_overflow */
1309 bfd_elf_generic_reloc, /* special_function */
1310 "R_ARM_MOVW_BREL", /* name */
1311 FALSE, /* partial_inplace */
1312 0x0000ffff, /* src_mask */
1313 0x0000ffff, /* dst_mask */
1314 FALSE), /* pcrel_offset */
1315
1316 HOWTO (R_ARM_THM_MOVW_BREL_NC,/* type */
1317 0, /* rightshift */
1318 2, /* size (0 = byte, 1 = short, 2 = long) */
1319 16, /* bitsize */
1320 FALSE, /* pc_relative */
1321 0, /* bitpos */
1322 complain_overflow_dont,/* complain_on_overflow */
1323 bfd_elf_generic_reloc, /* special_function */
1324 "R_ARM_THM_MOVW_BREL_NC",/* name */
1325 FALSE, /* partial_inplace */
1326 0x040f70ff, /* src_mask */
1327 0x040f70ff, /* dst_mask */
1328 FALSE), /* pcrel_offset */
1329
1330 HOWTO (R_ARM_THM_MOVT_BREL, /* type */
1331 0, /* rightshift */
1332 2, /* size (0 = byte, 1 = short, 2 = long) */
1333 16, /* bitsize */
1334 FALSE, /* pc_relative */
1335 0, /* bitpos */
1336 complain_overflow_bitfield,/* complain_on_overflow */
1337 bfd_elf_generic_reloc, /* special_function */
1338 "R_ARM_THM_MOVT_BREL", /* name */
1339 FALSE, /* partial_inplace */
1340 0x040f70ff, /* src_mask */
1341 0x040f70ff, /* dst_mask */
1342 FALSE), /* pcrel_offset */
1343
1344 HOWTO (R_ARM_THM_MOVW_BREL, /* type */
1345 0, /* rightshift */
1346 2, /* size (0 = byte, 1 = short, 2 = long) */
1347 16, /* bitsize */
1348 FALSE, /* pc_relative */
1349 0, /* bitpos */
1350 complain_overflow_dont,/* complain_on_overflow */
1351 bfd_elf_generic_reloc, /* special_function */
1352 "R_ARM_THM_MOVW_BREL", /* name */
1353 FALSE, /* partial_inplace */
1354 0x040f70ff, /* src_mask */
1355 0x040f70ff, /* dst_mask */
1356 FALSE), /* pcrel_offset */
1357
0855e32b
NS		 1358 HOWTO (R_ARM_TLS_GOTDESC, /* type */
1359 0, /* rightshift */
1360 2, /* size (0 = byte, 1 = short, 2 = long) */
1361 32, /* bitsize */
1362 FALSE, /* pc_relative */
1363 0, /* bitpos */
1364 complain_overflow_bitfield,/* complain_on_overflow */
1365 NULL, /* special_function */
1366 "R_ARM_TLS_GOTDESC", /* name */
1367 TRUE, /* partial_inplace */
1368 0xffffffff, /* src_mask */
1369 0xffffffff, /* dst_mask */
1370 FALSE), /* pcrel_offset */
1371
1372 HOWTO (R_ARM_TLS_CALL, /* type */
1373 0, /* rightshift */
1374 2, /* size (0 = byte, 1 = short, 2 = long) */
1375 24, /* bitsize */
1376 FALSE, /* pc_relative */
1377 0, /* bitpos */
1378 complain_overflow_dont,/* complain_on_overflow */
1379 bfd_elf_generic_reloc, /* special_function */
1380 "R_ARM_TLS_CALL", /* name */
1381 FALSE, /* partial_inplace */
1382 0x00ffffff, /* src_mask */
1383 0x00ffffff, /* dst_mask */
1384 FALSE), /* pcrel_offset */
1385
1386 HOWTO (R_ARM_TLS_DESCSEQ, /* type */
1387 0, /* rightshift */
1388 2, /* size (0 = byte, 1 = short, 2 = long) */
1389 0, /* bitsize */
1390 FALSE, /* pc_relative */
1391 0, /* bitpos */
1392 complain_overflow_bitfield,/* complain_on_overflow */
1393 bfd_elf_generic_reloc, /* special_function */
1394 "R_ARM_TLS_DESCSEQ", /* name */
1395 FALSE, /* partial_inplace */
1396 0x00000000, /* src_mask */
1397 0x00000000, /* dst_mask */
1398 FALSE), /* pcrel_offset */
1399
1400 HOWTO (R_ARM_THM_TLS_CALL, /* type */
1401 0, /* rightshift */
1402 2, /* size (0 = byte, 1 = short, 2 = long) */
1403 24, /* bitsize */
1404 FALSE, /* pc_relative */
1405 0, /* bitpos */
1406 complain_overflow_dont,/* complain_on_overflow */
1407 bfd_elf_generic_reloc, /* special_function */
1408 "R_ARM_THM_TLS_CALL", /* name */
1409 FALSE, /* partial_inplace */
1410 0x07ff07ff, /* src_mask */
1411 0x07ff07ff, /* dst_mask */
1412 FALSE), /* pcrel_offset */
c19d1205
ZW		 1413
1414 HOWTO (R_ARM_PLT32_ABS, /* type */
1415 0, /* rightshift */
1416 2, /* size (0 = byte, 1 = short, 2 = long) */
1417 32, /* bitsize */
1418 FALSE, /* pc_relative */
1419 0, /* bitpos */
1420 complain_overflow_dont,/* complain_on_overflow */
1421 bfd_elf_generic_reloc, /* special_function */
1422 "R_ARM_PLT32_ABS", /* name */
1423 FALSE, /* partial_inplace */
1424 0xffffffff, /* src_mask */
1425 0xffffffff, /* dst_mask */
1426 FALSE), /* pcrel_offset */
1427
1428 HOWTO (R_ARM_GOT_ABS, /* type */
1429 0, /* rightshift */
1430 2, /* size (0 = byte, 1 = short, 2 = long) */
1431 32, /* bitsize */
1432 FALSE, /* pc_relative */
1433 0, /* bitpos */
1434 complain_overflow_dont,/* complain_on_overflow */
1435 bfd_elf_generic_reloc, /* special_function */
1436 "R_ARM_GOT_ABS", /* name */
1437 FALSE, /* partial_inplace */
1438 0xffffffff, /* src_mask */
1439 0xffffffff, /* dst_mask */
1440 FALSE), /* pcrel_offset */
1441
1442 HOWTO (R_ARM_GOT_PREL, /* type */
1443 0, /* rightshift */
1444 2, /* size (0 = byte, 1 = short, 2 = long) */
1445 32, /* bitsize */
1446 TRUE, /* pc_relative */
1447 0, /* bitpos */
1448 complain_overflow_dont, /* complain_on_overflow */
1449 bfd_elf_generic_reloc, /* special_function */
1450 "R_ARM_GOT_PREL", /* name */
1451 FALSE, /* partial_inplace */
1452 0xffffffff, /* src_mask */
1453 0xffffffff, /* dst_mask */
1454 TRUE), /* pcrel_offset */
1455
1456 HOWTO (R_ARM_GOT_BREL12, /* type */
1457 0, /* rightshift */
1458 2, /* size (0 = byte, 1 = short, 2 = long) */
1459 12, /* bitsize */
1460 FALSE, /* pc_relative */
1461 0, /* bitpos */
1462 complain_overflow_bitfield,/* complain_on_overflow */
1463 bfd_elf_generic_reloc, /* special_function */
1464 "R_ARM_GOT_BREL12", /* name */
1465 FALSE, /* partial_inplace */
1466 0x00000fff, /* src_mask */
1467 0x00000fff, /* dst_mask */
1468 FALSE), /* pcrel_offset */
1469
1470 HOWTO (R_ARM_GOTOFF12, /* type */
1471 0, /* rightshift */
1472 2, /* size (0 = byte, 1 = short, 2 = long) */
1473 12, /* bitsize */
1474 FALSE, /* pc_relative */
1475 0, /* bitpos */
1476 complain_overflow_bitfield,/* complain_on_overflow */
1477 bfd_elf_generic_reloc, /* special_function */
1478 "R_ARM_GOTOFF12", /* name */
1479 FALSE, /* partial_inplace */
1480 0x00000fff, /* src_mask */
1481 0x00000fff, /* dst_mask */
1482 FALSE), /* pcrel_offset */
1483
07d6d2b8 1484 EMPTY_HOWTO (R_ARM_GOTRELAX), /* reserved for future GOT-load optimizations */
c19d1205
ZW		 1485
1486 /* GNU extension to record C++ vtable member usage */
07d6d2b8
AM		 1487 HOWTO (R_ARM_GNU_VTENTRY, /* type */
1488 0, /* rightshift */
1489 2, /* size (0 = byte, 1 = short, 2 = long) */
1490 0, /* bitsize */
1491 FALSE, /* pc_relative */
1492 0, /* bitpos */
99059e56 1493 complain_overflow_dont, /* complain_on_overflow */
07d6d2b8
AM		 1494 _bfd_elf_rel_vtable_reloc_fn, /* special_function */
1495 "R_ARM_GNU_VTENTRY", /* name */
1496 FALSE, /* partial_inplace */
1497 0, /* src_mask */
1498 0, /* dst_mask */
1499 FALSE), /* pcrel_offset */
c19d1205
ZW		 1500
1501 /* GNU extension to record C++ vtable hierarchy */
1502 HOWTO (R_ARM_GNU_VTINHERIT, /* type */
07d6d2b8
AM		 1503 0, /* rightshift */
1504 2, /* size (0 = byte, 1 = short, 2 = long) */
1505 0, /* bitsize */
1506 FALSE, /* pc_relative */
1507 0, /* bitpos */
99059e56 1508 complain_overflow_dont, /* complain_on_overflow */
07d6d2b8 1509 NULL, /* special_function */
99059e56 1510 "R_ARM_GNU_VTINHERIT", /* name */
07d6d2b8
AM		 1511 FALSE, /* partial_inplace */
1512 0, /* src_mask */
1513 0, /* dst_mask */
1514 FALSE), /* pcrel_offset */
c19d1205
ZW		 1515
1516 HOWTO (R_ARM_THM_JUMP11, /* type */
1517 1, /* rightshift */
1518 1, /* size (0 = byte, 1 = short, 2 = long) */
1519 11, /* bitsize */
1520 TRUE, /* pc_relative */
1521 0, /* bitpos */
1522 complain_overflow_signed, /* complain_on_overflow */
1523 bfd_elf_generic_reloc, /* special_function */
1524 "R_ARM_THM_JUMP11", /* name */
1525 FALSE, /* partial_inplace */
1526 0x000007ff, /* src_mask */
1527 0x000007ff, /* dst_mask */
1528 TRUE), /* pcrel_offset */
1529
1530 HOWTO (R_ARM_THM_JUMP8, /* type */
1531 1, /* rightshift */
1532 1, /* size (0 = byte, 1 = short, 2 = long) */
1533 8, /* bitsize */
1534 TRUE, /* pc_relative */
1535 0, /* bitpos */
1536 complain_overflow_signed, /* complain_on_overflow */
1537 bfd_elf_generic_reloc, /* special_function */
1538 "R_ARM_THM_JUMP8", /* name */
1539 FALSE, /* partial_inplace */
1540 0x000000ff, /* src_mask */
1541 0x000000ff, /* dst_mask */
1542 TRUE), /* pcrel_offset */
ba93b8ac 1543
c19d1205
ZW		 1544 /* TLS relocations */
1545 HOWTO (R_ARM_TLS_GD32, /* type */
07d6d2b8
AM		 1546 0, /* rightshift */
1547 2, /* size (0 = byte, 1 = short, 2 = long) */
1548 32, /* bitsize */
1549 FALSE, /* pc_relative */
1550 0, /* bitpos */
99059e56
RM		 1551 complain_overflow_bitfield,/* complain_on_overflow */
1552 NULL, /* special_function */
1553 "R_ARM_TLS_GD32", /* name */
1554 TRUE, /* partial_inplace */
1555 0xffffffff, /* src_mask */
1556 0xffffffff, /* dst_mask */
07d6d2b8 1557 FALSE), /* pcrel_offset */
ba93b8ac 1558
ba93b8ac 1559 HOWTO (R_ARM_TLS_LDM32, /* type */
07d6d2b8
AM		 1560 0, /* rightshift */
1561 2, /* size (0 = byte, 1 = short, 2 = long) */
1562 32, /* bitsize */
1563 FALSE, /* pc_relative */
1564 0, /* bitpos */
99059e56
RM		 1565 complain_overflow_bitfield,/* complain_on_overflow */
1566 bfd_elf_generic_reloc, /* special_function */
1567 "R_ARM_TLS_LDM32", /* name */
1568 TRUE, /* partial_inplace */
1569 0xffffffff, /* src_mask */
1570 0xffffffff, /* dst_mask */
07d6d2b8 1571 FALSE), /* pcrel_offset */
ba93b8ac 1572
c19d1205 1573 HOWTO (R_ARM_TLS_LDO32, /* type */
07d6d2b8
AM		 1574 0, /* rightshift */
1575 2, /* size (0 = byte, 1 = short, 2 = long) */
1576 32, /* bitsize */
1577 FALSE, /* pc_relative */
1578 0, /* bitpos */
99059e56
RM		 1579 complain_overflow_bitfield,/* complain_on_overflow */
1580 bfd_elf_generic_reloc, /* special_function */
1581 "R_ARM_TLS_LDO32", /* name */
1582 TRUE, /* partial_inplace */
1583 0xffffffff, /* src_mask */
1584 0xffffffff, /* dst_mask */
07d6d2b8 1585 FALSE), /* pcrel_offset */
ba93b8ac 1586
ba93b8ac 1587 HOWTO (R_ARM_TLS_IE32, /* type */
07d6d2b8
AM		 1588 0, /* rightshift */
1589 2, /* size (0 = byte, 1 = short, 2 = long) */
1590 32, /* bitsize */
1591 FALSE, /* pc_relative */
1592 0, /* bitpos */
99059e56
RM		 1593 complain_overflow_bitfield,/* complain_on_overflow */
1594 NULL, /* special_function */
1595 "R_ARM_TLS_IE32", /* name */
1596 TRUE, /* partial_inplace */
1597 0xffffffff, /* src_mask */
1598 0xffffffff, /* dst_mask */
07d6d2b8 1599 FALSE), /* pcrel_offset */
7f266840 1600
c19d1205 1601 HOWTO (R_ARM_TLS_LE32, /* type */
07d6d2b8
AM		 1602 0, /* rightshift */
1603 2, /* size (0 = byte, 1 = short, 2 = long) */
1604 32, /* bitsize */
1605 FALSE, /* pc_relative */
1606 0, /* bitpos */
99059e56 1607 complain_overflow_bitfield,/* complain_on_overflow */
07d6d2b8 1608 NULL, /* special_function */
99059e56
RM		 1609 "R_ARM_TLS_LE32", /* name */
1610 TRUE, /* partial_inplace */
1611 0xffffffff, /* src_mask */
1612 0xffffffff, /* dst_mask */
07d6d2b8 1613 FALSE), /* pcrel_offset */
7f266840 1614
c19d1205
ZW		 1615 HOWTO (R_ARM_TLS_LDO12, /* type */
1616 0, /* rightshift */
1617 2, /* size (0 = byte, 1 = short, 2 = long) */
1618 12, /* bitsize */
1619 FALSE, /* pc_relative */
7f266840 1620 0, /* bitpos */
c19d1205 1621 complain_overflow_bitfield,/* complain_on_overflow */
7f266840 1622 bfd_elf_generic_reloc, /* special_function */
c19d1205 1623 "R_ARM_TLS_LDO12", /* name */
7f266840 1624 FALSE, /* partial_inplace */
c19d1205
ZW		 1625 0x00000fff, /* src_mask */
1626 0x00000fff, /* dst_mask */
1627 FALSE), /* pcrel_offset */
7f266840 1628
c19d1205
ZW		 1629 HOWTO (R_ARM_TLS_LE12, /* type */
1630 0, /* rightshift */
1631 2, /* size (0 = byte, 1 = short, 2 = long) */
1632 12, /* bitsize */
1633 FALSE, /* pc_relative */
7f266840 1634 0, /* bitpos */
c19d1205 1635 complain_overflow_bitfield,/* complain_on_overflow */
7f266840 1636 bfd_elf_generic_reloc, /* special_function */
c19d1205 1637 "R_ARM_TLS_LE12", /* name */
7f266840 1638 FALSE, /* partial_inplace */
c19d1205
ZW		 1639 0x00000fff, /* src_mask */
1640 0x00000fff, /* dst_mask */
1641 FALSE), /* pcrel_offset */
7f266840 1642
c19d1205 1643 HOWTO (R_ARM_TLS_IE12GP, /* type */
7f266840
DJ		 1644 0, /* rightshift */
1645 2, /* size (0 = byte, 1 = short, 2 = long) */
c19d1205
ZW		 1646 12, /* bitsize */
1647 FALSE, /* pc_relative */
7f266840 1648 0, /* bitpos */
c19d1205 1649 complain_overflow_bitfield,/* complain_on_overflow */
7f266840 1650 bfd_elf_generic_reloc, /* special_function */
c19d1205 1651 "R_ARM_TLS_IE12GP", /* name */
7f266840 1652 FALSE, /* partial_inplace */
c19d1205
ZW		 1653 0x00000fff, /* src_mask */
1654 0x00000fff, /* dst_mask */
1655 FALSE), /* pcrel_offset */
0855e32b 1656
34e77a92 1657 /* 112-127 private relocations. */
0855e32b
NS		 1658 EMPTY_HOWTO (112),
1659 EMPTY_HOWTO (113),
1660 EMPTY_HOWTO (114),
1661 EMPTY_HOWTO (115),
1662 EMPTY_HOWTO (116),
1663 EMPTY_HOWTO (117),
1664 EMPTY_HOWTO (118),
1665 EMPTY_HOWTO (119),
1666 EMPTY_HOWTO (120),
1667 EMPTY_HOWTO (121),
1668 EMPTY_HOWTO (122),
1669 EMPTY_HOWTO (123),
1670 EMPTY_HOWTO (124),
1671 EMPTY_HOWTO (125),
1672 EMPTY_HOWTO (126),
1673 EMPTY_HOWTO (127),
34e77a92
RS		 1674
1675 /* R_ARM_ME_TOO, obsolete. */
0855e32b
NS		 1676 EMPTY_HOWTO (128),
1677
1678 HOWTO (R_ARM_THM_TLS_DESCSEQ, /* type */
1679 0, /* rightshift */
1680 1, /* size (0 = byte, 1 = short, 2 = long) */
1681 0, /* bitsize */
1682 FALSE, /* pc_relative */
1683 0, /* bitpos */
1684 complain_overflow_bitfield,/* complain_on_overflow */
1685 bfd_elf_generic_reloc, /* special_function */
1686 "R_ARM_THM_TLS_DESCSEQ",/* name */
1687 FALSE, /* partial_inplace */
1688 0x00000000, /* src_mask */
1689 0x00000000, /* dst_mask */
1690 FALSE), /* pcrel_offset */
72d98d16
MG		 1691 EMPTY_HOWTO (130),
1692 EMPTY_HOWTO (131),
1693 HOWTO (R_ARM_THM_ALU_ABS_G0_NC,/* type. */
1694 0, /* rightshift. */
1695 1, /* size (0 = byte, 1 = short, 2 = long). */
1696 16, /* bitsize. */
1697 FALSE, /* pc_relative. */
1698 0, /* bitpos. */
1699 complain_overflow_bitfield,/* complain_on_overflow. */
1700 bfd_elf_generic_reloc, /* special_function. */
1701 "R_ARM_THM_ALU_ABS_G0_NC",/* name. */
1702 FALSE, /* partial_inplace. */
1703 0x00000000, /* src_mask. */
1704 0x00000000, /* dst_mask. */
1705 FALSE), /* pcrel_offset. */
1706 HOWTO (R_ARM_THM_ALU_ABS_G1_NC,/* type. */
1707 0, /* rightshift. */
1708 1, /* size (0 = byte, 1 = short, 2 = long). */
1709 16, /* bitsize. */
1710 FALSE, /* pc_relative. */
1711 0, /* bitpos. */
1712 complain_overflow_bitfield,/* complain_on_overflow. */
1713 bfd_elf_generic_reloc, /* special_function. */
1714 "R_ARM_THM_ALU_ABS_G1_NC",/* name. */
1715 FALSE, /* partial_inplace. */
1716 0x00000000, /* src_mask. */
1717 0x00000000, /* dst_mask. */
1718 FALSE), /* pcrel_offset. */
1719 HOWTO (R_ARM_THM_ALU_ABS_G2_NC,/* type. */
1720 0, /* rightshift. */
1721 1, /* size (0 = byte, 1 = short, 2 = long). */
1722 16, /* bitsize. */
1723 FALSE, /* pc_relative. */
1724 0, /* bitpos. */
1725 complain_overflow_bitfield,/* complain_on_overflow. */
1726 bfd_elf_generic_reloc, /* special_function. */
1727 "R_ARM_THM_ALU_ABS_G2_NC",/* name. */
1728 FALSE, /* partial_inplace. */
1729 0x00000000, /* src_mask. */
1730 0x00000000, /* dst_mask. */
1731 FALSE), /* pcrel_offset. */
1732 HOWTO (R_ARM_THM_ALU_ABS_G3_NC,/* type. */
1733 0, /* rightshift. */
1734 1, /* size (0 = byte, 1 = short, 2 = long). */
1735 16, /* bitsize. */
1736 FALSE, /* pc_relative. */
1737 0, /* bitpos. */
1738 complain_overflow_bitfield,/* complain_on_overflow. */
1739 bfd_elf_generic_reloc, /* special_function. */
1740 "R_ARM_THM_ALU_ABS_G3_NC",/* name. */
1741 FALSE, /* partial_inplace. */
1742 0x00000000, /* src_mask. */
1743 0x00000000, /* dst_mask. */
1744 FALSE), /* pcrel_offset. */
e5d6e09e
AV		 1745 /* Relocations for Armv8.1-M Mainline. */
1746 HOWTO (R_ARM_THM_BF16, /* type. */
1747 0, /* rightshift. */
1748 1, /* size (0 = byte, 1 = short, 2 = long). */
1749 16, /* bitsize. */
1750 TRUE, /* pc_relative. */
1751 0, /* bitpos. */
1752 complain_overflow_dont,/* do not complain_on_overflow. */
1753 bfd_elf_generic_reloc, /* special_function. */
1754 "R_ARM_THM_BF16", /* name. */
1755 FALSE, /* partial_inplace. */
1756 0x001f0ffe, /* src_mask. */
1757 0x001f0ffe, /* dst_mask. */
1758 TRUE), /* pcrel_offset. */
1889da70
AV		 1759 HOWTO (R_ARM_THM_BF12, /* type. */
1760 0, /* rightshift. */
1761 1, /* size (0 = byte, 1 = short, 2 = long). */
1762 12, /* bitsize. */
1763 TRUE, /* pc_relative. */
1764 0, /* bitpos. */
1765 complain_overflow_dont,/* do not complain_on_overflow. */
1766 bfd_elf_generic_reloc, /* special_function. */
1767 "R_ARM_THM_BF12", /* name. */
1768 FALSE, /* partial_inplace. */
1769 0x00010ffe, /* src_mask. */
1770 0x00010ffe, /* dst_mask. */
1771 TRUE), /* pcrel_offset. */
1caf72a5
AV		 1772 HOWTO (R_ARM_THM_BF18, /* type. */
1773 0, /* rightshift. */
1774 1, /* size (0 = byte, 1 = short, 2 = long). */
1775 18, /* bitsize. */
1776 TRUE, /* pc_relative. */
1777 0, /* bitpos. */
1778 complain_overflow_dont,/* do not complain_on_overflow. */
1779 bfd_elf_generic_reloc, /* special_function. */
1780 "R_ARM_THM_BF18", /* name. */
1781 FALSE, /* partial_inplace. */
1782 0x007f0ffe, /* src_mask. */
1783 0x007f0ffe, /* dst_mask. */
1784 TRUE), /* pcrel_offset. */
c19d1205
ZW		 1785};
1786
34e77a92 1787/* 160 onwards: */
5c5a4843 1788static reloc_howto_type elf32_arm_howto_table_2[8] =
34e77a92
RS		 1789{
1790 HOWTO (R_ARM_IRELATIVE, /* type */
07d6d2b8
AM		 1791 0, /* rightshift */
1792 2, /* size (0 = byte, 1 = short, 2 = long) */
1793 32, /* bitsize */
1794 FALSE, /* pc_relative */
1795 0, /* bitpos */
99059e56
RM		 1796 complain_overflow_bitfield,/* complain_on_overflow */
1797 bfd_elf_generic_reloc, /* special_function */
1798 "R_ARM_IRELATIVE", /* name */
1799 TRUE, /* partial_inplace */
1800 0xffffffff, /* src_mask */
1801 0xffffffff, /* dst_mask */
188fd7ae
CL		 1802 FALSE), /* pcrel_offset */
1803 HOWTO (R_ARM_GOTFUNCDESC, /* type */
1804 0, /* rightshift */
1805 2, /* size (0 = byte, 1 = short, 2 = long) */
1806 32, /* bitsize */
1807 FALSE, /* pc_relative */
1808 0, /* bitpos */
1809 complain_overflow_bitfield,/* complain_on_overflow */
1810 bfd_elf_generic_reloc, /* special_function */
1811 "R_ARM_GOTFUNCDESC", /* name */
1812 FALSE, /* partial_inplace */
1813 0, /* src_mask */
1814 0xffffffff, /* dst_mask */
1815 FALSE), /* pcrel_offset */
1816 HOWTO (R_ARM_GOTOFFFUNCDESC, /* type */
1817 0, /* rightshift */
1818 2, /* size (0 = byte, 1 = short, 2 = long) */
1819 32, /* bitsize */
1820 FALSE, /* pc_relative */
1821 0, /* bitpos */
1822 complain_overflow_bitfield,/* complain_on_overflow */
1823 bfd_elf_generic_reloc, /* special_function */
1824 "R_ARM_GOTOFFFUNCDESC",/* name */
1825 FALSE, /* partial_inplace */
1826 0, /* src_mask */
1827 0xffffffff, /* dst_mask */
1828 FALSE), /* pcrel_offset */
1829 HOWTO (R_ARM_FUNCDESC, /* type */
1830 0, /* rightshift */
1831 2, /* size (0 = byte, 1 = short, 2 = long) */
1832 32, /* bitsize */
1833 FALSE, /* pc_relative */
1834 0, /* bitpos */
1835 complain_overflow_bitfield,/* complain_on_overflow */
1836 bfd_elf_generic_reloc, /* special_function */
1837 "R_ARM_FUNCDESC", /* name */
1838 FALSE, /* partial_inplace */
1839 0, /* src_mask */
1840 0xffffffff, /* dst_mask */
1841 FALSE), /* pcrel_offset */
1842 HOWTO (R_ARM_FUNCDESC_VALUE, /* type */
1843 0, /* rightshift */
1844 2, /* size (0 = byte, 1 = short, 2 = long) */
1845 64, /* bitsize */
1846 FALSE, /* pc_relative */
1847 0, /* bitpos */
1848 complain_overflow_bitfield,/* complain_on_overflow */
1849 bfd_elf_generic_reloc, /* special_function */
1850 "R_ARM_FUNCDESC_VALUE",/* name */
1851 FALSE, /* partial_inplace */
1852 0, /* src_mask */
1853 0xffffffff, /* dst_mask */
1854 FALSE), /* pcrel_offset */
5c5a4843
CL		 1855 HOWTO (R_ARM_TLS_GD32_FDPIC, /* type */
1856 0, /* rightshift */
1857 2, /* size (0 = byte, 1 = short, 2 = long) */
1858 32, /* bitsize */
1859 FALSE, /* pc_relative */
1860 0, /* bitpos */
1861 complain_overflow_bitfield,/* complain_on_overflow */
1862 bfd_elf_generic_reloc, /* special_function */
1863 "R_ARM_TLS_GD32_FDPIC",/* name */
1864 FALSE, /* partial_inplace */
1865 0, /* src_mask */
1866 0xffffffff, /* dst_mask */
1867 FALSE), /* pcrel_offset */
1868 HOWTO (R_ARM_TLS_LDM32_FDPIC, /* type */
1869 0, /* rightshift */
1870 2, /* size (0 = byte, 1 = short, 2 = long) */
1871 32, /* bitsize */
1872 FALSE, /* pc_relative */
1873 0, /* bitpos */
1874 complain_overflow_bitfield,/* complain_on_overflow */
1875 bfd_elf_generic_reloc, /* special_function */
1876 "R_ARM_TLS_LDM32_FDPIC",/* name */
1877 FALSE, /* partial_inplace */
1878 0, /* src_mask */
1879 0xffffffff, /* dst_mask */
1880 FALSE), /* pcrel_offset */
1881 HOWTO (R_ARM_TLS_IE32_FDPIC, /* type */
1882 0, /* rightshift */
1883 2, /* size (0 = byte, 1 = short, 2 = long) */
1884 32, /* bitsize */
1885 FALSE, /* pc_relative */
1886 0, /* bitpos */
1887 complain_overflow_bitfield,/* complain_on_overflow */
1888 bfd_elf_generic_reloc, /* special_function */
1889 "R_ARM_TLS_IE32_FDPIC",/* name */
1890 FALSE, /* partial_inplace */
1891 0, /* src_mask */
1892 0xffffffff, /* dst_mask */
1893 FALSE), /* pcrel_offset */
34e77a92 1894};
c19d1205 1895
34e77a92
RS		 1896/* 249-255 extended, currently unused, relocations: */
1897static reloc_howto_type elf32_arm_howto_table_3[4] =
7f266840
DJ		 1898{
1899 HOWTO (R_ARM_RREL32, /* type */
1900 0, /* rightshift */
1901 0, /* size (0 = byte, 1 = short, 2 = long) */
1902 0, /* bitsize */
1903 FALSE, /* pc_relative */
1904 0, /* bitpos */
1905 complain_overflow_dont,/* complain_on_overflow */
1906 bfd_elf_generic_reloc, /* special_function */
1907 "R_ARM_RREL32", /* name */
1908 FALSE, /* partial_inplace */
1909 0, /* src_mask */
1910 0, /* dst_mask */
1911 FALSE), /* pcrel_offset */
1912
1913 HOWTO (R_ARM_RABS32, /* type */
1914 0, /* rightshift */
1915 0, /* size (0 = byte, 1 = short, 2 = long) */
1916 0, /* bitsize */
1917 FALSE, /* pc_relative */
1918 0, /* bitpos */
1919 complain_overflow_dont,/* complain_on_overflow */
1920 bfd_elf_generic_reloc, /* special_function */
1921 "R_ARM_RABS32", /* name */
1922 FALSE, /* partial_inplace */
1923 0, /* src_mask */
1924 0, /* dst_mask */
1925 FALSE), /* pcrel_offset */
1926
1927 HOWTO (R_ARM_RPC24, /* type */
1928 0, /* rightshift */
1929 0, /* size (0 = byte, 1 = short, 2 = long) */
1930 0, /* bitsize */
1931 FALSE, /* pc_relative */
1932 0, /* bitpos */
1933 complain_overflow_dont,/* complain_on_overflow */
1934 bfd_elf_generic_reloc, /* special_function */
1935 "R_ARM_RPC24", /* name */
1936 FALSE, /* partial_inplace */
1937 0, /* src_mask */
1938 0, /* dst_mask */
1939 FALSE), /* pcrel_offset */
1940
1941 HOWTO (R_ARM_RBASE, /* type */
1942 0, /* rightshift */
1943 0, /* size (0 = byte, 1 = short, 2 = long) */
1944 0, /* bitsize */
1945 FALSE, /* pc_relative */
1946 0, /* bitpos */
1947 complain_overflow_dont,/* complain_on_overflow */
1948 bfd_elf_generic_reloc, /* special_function */
1949 "R_ARM_RBASE", /* name */
1950 FALSE, /* partial_inplace */
1951 0, /* src_mask */
1952 0, /* dst_mask */
1953 FALSE) /* pcrel_offset */
1954};
1955
1956static reloc_howto_type *
1957elf32_arm_howto_from_type (unsigned int r_type)
1958{
906e58ca 1959 if (r_type < ARRAY_SIZE (elf32_arm_howto_table_1))
c19d1205 1960 return &elf32_arm_howto_table_1[r_type];
ba93b8ac 1961
188fd7ae
CL		 1962 if (r_type >= R_ARM_IRELATIVE
1963 && r_type < R_ARM_IRELATIVE + ARRAY_SIZE (elf32_arm_howto_table_2))
34e77a92
RS		 1964 return &elf32_arm_howto_table_2[r_type - R_ARM_IRELATIVE];
1965
c19d1205 1966 if (r_type >= R_ARM_RREL32
34e77a92
RS		 1967 && r_type < R_ARM_RREL32 + ARRAY_SIZE (elf32_arm_howto_table_3))
1968 return &elf32_arm_howto_table_3[r_type - R_ARM_RREL32];
7f266840 1969
c19d1205 1970 return NULL;
7f266840
DJ		 1971}
1972
f3185997
NC		 1973static bfd_boolean
1974elf32_arm_info_to_howto (bfd * abfd, arelent * bfd_reloc,
7f266840
DJ		 1975 Elf_Internal_Rela * elf_reloc)
1976{
1977 unsigned int r_type;
1978
1979 r_type = ELF32_R_TYPE (elf_reloc->r_info);
f3185997
NC		 1980 if ((bfd_reloc->howto = elf32_arm_howto_from_type (r_type)) == NULL)
1981 {
1982 /* xgettext:c-format */
1983 _bfd_error_handler (_("%pB: unsupported relocation type %#x"),
1984 abfd, r_type);
1985 bfd_set_error (bfd_error_bad_value);
1986 return FALSE;
1987 }
1988 return TRUE;
7f266840
DJ		 1989}
1990
1991struct elf32_arm_reloc_map
1992 {
1993 bfd_reloc_code_real_type bfd_reloc_val;
07d6d2b8 1994 unsigned char elf_reloc_val;
7f266840
DJ		 1995 };
1996
1997/* All entries in this list must also be present in elf32_arm_howto_table. */
1998static const struct elf32_arm_reloc_map elf32_arm_reloc_map[] =
1999 {
07d6d2b8 2000 {BFD_RELOC_NONE, R_ARM_NONE},
7f266840 2001 {BFD_RELOC_ARM_PCREL_BRANCH, R_ARM_PC24},
39b41c9c
PB		 2002 {BFD_RELOC_ARM_PCREL_CALL, R_ARM_CALL},
2003 {BFD_RELOC_ARM_PCREL_JUMP, R_ARM_JUMP24},
07d6d2b8
AM		 2004 {BFD_RELOC_ARM_PCREL_BLX, R_ARM_XPC25},
2005 {BFD_RELOC_THUMB_PCREL_BLX, R_ARM_THM_XPC22},
2006 {BFD_RELOC_32, R_ARM_ABS32},
2007 {BFD_RELOC_32_PCREL, R_ARM_REL32},
2008 {BFD_RELOC_8, R_ARM_ABS8},
2009 {BFD_RELOC_16, R_ARM_ABS16},
2010 {BFD_RELOC_ARM_OFFSET_IMM, R_ARM_ABS12},
7f266840 2011 {BFD_RELOC_ARM_THUMB_OFFSET, R_ARM_THM_ABS5},
c19d1205
ZW		 2012 {BFD_RELOC_THUMB_PCREL_BRANCH25, R_ARM_THM_JUMP24},
2013 {BFD_RELOC_THUMB_PCREL_BRANCH23, R_ARM_THM_CALL},
2014 {BFD_RELOC_THUMB_PCREL_BRANCH12, R_ARM_THM_JUMP11},
2015 {BFD_RELOC_THUMB_PCREL_BRANCH20, R_ARM_THM_JUMP19},
2016 {BFD_RELOC_THUMB_PCREL_BRANCH9, R_ARM_THM_JUMP8},
2017 {BFD_RELOC_THUMB_PCREL_BRANCH7, R_ARM_THM_JUMP6},
07d6d2b8
AM		 2018 {BFD_RELOC_ARM_GLOB_DAT, R_ARM_GLOB_DAT},
2019 {BFD_RELOC_ARM_JUMP_SLOT, R_ARM_JUMP_SLOT},
2020 {BFD_RELOC_ARM_RELATIVE, R_ARM_RELATIVE},
2021 {BFD_RELOC_ARM_GOTOFF, R_ARM_GOTOFF32},
2022 {BFD_RELOC_ARM_GOTPC, R_ARM_GOTPC},
2023 {BFD_RELOC_ARM_GOT_PREL, R_ARM_GOT_PREL},
2024 {BFD_RELOC_ARM_GOT32, R_ARM_GOT32},
2025 {BFD_RELOC_ARM_PLT32, R_ARM_PLT32},
7f266840
DJ		 2026 {BFD_RELOC_ARM_TARGET1, R_ARM_TARGET1},
2027 {BFD_RELOC_ARM_ROSEGREL32, R_ARM_ROSEGREL32},
2028 {BFD_RELOC_ARM_SBREL32, R_ARM_SBREL32},
2029 {BFD_RELOC_ARM_PREL31, R_ARM_PREL31},
ba93b8ac 2030 {BFD_RELOC_ARM_TARGET2, R_ARM_TARGET2},
07d6d2b8
AM		 2031 {BFD_RELOC_ARM_PLT32, R_ARM_PLT32},
2032 {BFD_RELOC_ARM_TLS_GOTDESC, R_ARM_TLS_GOTDESC},
2033 {BFD_RELOC_ARM_TLS_CALL, R_ARM_TLS_CALL},
0855e32b 2034 {BFD_RELOC_ARM_THM_TLS_CALL, R_ARM_THM_TLS_CALL},
07d6d2b8 2035 {BFD_RELOC_ARM_TLS_DESCSEQ, R_ARM_TLS_DESCSEQ},
0855e32b 2036 {BFD_RELOC_ARM_THM_TLS_DESCSEQ, R_ARM_THM_TLS_DESCSEQ},
07d6d2b8 2037 {BFD_RELOC_ARM_TLS_DESC, R_ARM_TLS_DESC},
ba93b8ac
DJ		 2038 {BFD_RELOC_ARM_TLS_GD32, R_ARM_TLS_GD32},
2039 {BFD_RELOC_ARM_TLS_LDO32, R_ARM_TLS_LDO32},
2040 {BFD_RELOC_ARM_TLS_LDM32, R_ARM_TLS_LDM32},
2041 {BFD_RELOC_ARM_TLS_DTPMOD32, R_ARM_TLS_DTPMOD32},
2042 {BFD_RELOC_ARM_TLS_DTPOFF32, R_ARM_TLS_DTPOFF32},
07d6d2b8
AM		 2043 {BFD_RELOC_ARM_TLS_TPOFF32, R_ARM_TLS_TPOFF32},
2044 {BFD_RELOC_ARM_TLS_IE32, R_ARM_TLS_IE32},
2045 {BFD_RELOC_ARM_TLS_LE32, R_ARM_TLS_LE32},
2046 {BFD_RELOC_ARM_IRELATIVE, R_ARM_IRELATIVE},
188fd7ae
CL		 2047 {BFD_RELOC_ARM_GOTFUNCDESC, R_ARM_GOTFUNCDESC},
2048 {BFD_RELOC_ARM_GOTOFFFUNCDESC, R_ARM_GOTOFFFUNCDESC},
2049 {BFD_RELOC_ARM_FUNCDESC, R_ARM_FUNCDESC},
2050 {BFD_RELOC_ARM_FUNCDESC_VALUE, R_ARM_FUNCDESC_VALUE},
5c5a4843
CL		 2051 {BFD_RELOC_ARM_TLS_GD32_FDPIC, R_ARM_TLS_GD32_FDPIC},
2052 {BFD_RELOC_ARM_TLS_LDM32_FDPIC, R_ARM_TLS_LDM32_FDPIC},
2053 {BFD_RELOC_ARM_TLS_IE32_FDPIC, R_ARM_TLS_IE32_FDPIC},
c19d1205
ZW		 2054 {BFD_RELOC_VTABLE_INHERIT, R_ARM_GNU_VTINHERIT},
2055 {BFD_RELOC_VTABLE_ENTRY, R_ARM_GNU_VTENTRY},
b6895b4f
PB		 2056 {BFD_RELOC_ARM_MOVW, R_ARM_MOVW_ABS_NC},
2057 {BFD_RELOC_ARM_MOVT, R_ARM_MOVT_ABS},
2058 {BFD_RELOC_ARM_MOVW_PCREL, R_ARM_MOVW_PREL_NC},
2059 {BFD_RELOC_ARM_MOVT_PCREL, R_ARM_MOVT_PREL},
2060 {BFD_RELOC_ARM_THUMB_MOVW, R_ARM_THM_MOVW_ABS_NC},
2061 {BFD_RELOC_ARM_THUMB_MOVT, R_ARM_THM_MOVT_ABS},
2062 {BFD_RELOC_ARM_THUMB_MOVW_PCREL, R_ARM_THM_MOVW_PREL_NC},
2063 {BFD_RELOC_ARM_THUMB_MOVT_PCREL, R_ARM_THM_MOVT_PREL},
4962c51a
MS		 2064 {BFD_RELOC_ARM_ALU_PC_G0_NC, R_ARM_ALU_PC_G0_NC},
2065 {BFD_RELOC_ARM_ALU_PC_G0, R_ARM_ALU_PC_G0},
2066 {BFD_RELOC_ARM_ALU_PC_G1_NC, R_ARM_ALU_PC_G1_NC},
2067 {BFD_RELOC_ARM_ALU_PC_G1, R_ARM_ALU_PC_G1},
2068 {BFD_RELOC_ARM_ALU_PC_G2, R_ARM_ALU_PC_G2},
2069 {BFD_RELOC_ARM_LDR_PC_G0, R_ARM_LDR_PC_G0},
2070 {BFD_RELOC_ARM_LDR_PC_G1, R_ARM_LDR_PC_G1},
2071 {BFD_RELOC_ARM_LDR_PC_G2, R_ARM_LDR_PC_G2},
2072 {BFD_RELOC_ARM_LDRS_PC_G0, R_ARM_LDRS_PC_G0},
2073 {BFD_RELOC_ARM_LDRS_PC_G1, R_ARM_LDRS_PC_G1},
2074 {BFD_RELOC_ARM_LDRS_PC_G2, R_ARM_LDRS_PC_G2},
2075 {BFD_RELOC_ARM_LDC_PC_G0, R_ARM_LDC_PC_G0},
2076 {BFD_RELOC_ARM_LDC_PC_G1, R_ARM_LDC_PC_G1},
2077 {BFD_RELOC_ARM_LDC_PC_G2, R_ARM_LDC_PC_G2},
2078 {BFD_RELOC_ARM_ALU_SB_G0_NC, R_ARM_ALU_SB_G0_NC},
2079 {BFD_RELOC_ARM_ALU_SB_G0, R_ARM_ALU_SB_G0},
2080 {BFD_RELOC_ARM_ALU_SB_G1_NC, R_ARM_ALU_SB_G1_NC},
2081 {BFD_RELOC_ARM_ALU_SB_G1, R_ARM_ALU_SB_G1},
2082 {BFD_RELOC_ARM_ALU_SB_G2, R_ARM_ALU_SB_G2},
2083 {BFD_RELOC_ARM_LDR_SB_G0, R_ARM_LDR_SB_G0},
2084 {BFD_RELOC_ARM_LDR_SB_G1, R_ARM_LDR_SB_G1},
2085 {BFD_RELOC_ARM_LDR_SB_G2, R_ARM_LDR_SB_G2},
2086 {BFD_RELOC_ARM_LDRS_SB_G0, R_ARM_LDRS_SB_G0},
2087 {BFD_RELOC_ARM_LDRS_SB_G1, R_ARM_LDRS_SB_G1},
2088 {BFD_RELOC_ARM_LDRS_SB_G2, R_ARM_LDRS_SB_G2},
2089 {BFD_RELOC_ARM_LDC_SB_G0, R_ARM_LDC_SB_G0},
2090 {BFD_RELOC_ARM_LDC_SB_G1, R_ARM_LDC_SB_G1},
845b51d6 2091 {BFD_RELOC_ARM_LDC_SB_G2, R_ARM_LDC_SB_G2},
72d98d16
MG		 2092 {BFD_RELOC_ARM_V4BX, R_ARM_V4BX},
2093 {BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC, R_ARM_THM_ALU_ABS_G3_NC},
2094 {BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC, R_ARM_THM_ALU_ABS_G2_NC},
2095 {BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC, R_ARM_THM_ALU_ABS_G1_NC},
e5d6e09e 2096 {BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC, R_ARM_THM_ALU_ABS_G0_NC},
1caf72a5 2097 {BFD_RELOC_ARM_THUMB_BF17, R_ARM_THM_BF16},
1889da70 2098 {BFD_RELOC_ARM_THUMB_BF13, R_ARM_THM_BF12},
1caf72a5 2099 {BFD_RELOC_ARM_THUMB_BF19, R_ARM_THM_BF18}
7f266840
DJ		 2100 };
2101
2102static reloc_howto_type *
f1c71a59
ZW		 2103elf32_arm_reloc_type_lookup (bfd *abfd ATTRIBUTE_UNUSED,
2104 bfd_reloc_code_real_type code)
7f266840
DJ		 2105{
2106 unsigned int i;
8029a119 2107
906e58ca 2108 for (i = 0; i < ARRAY_SIZE (elf32_arm_reloc_map); i ++)
c19d1205
ZW		 2109 if (elf32_arm_reloc_map[i].bfd_reloc_val == code)
2110 return elf32_arm_howto_from_type (elf32_arm_reloc_map[i].elf_reloc_val);
7f266840 2111
c19d1205 2112 return NULL;
7f266840
DJ		 2113}
2114
157090f7
AM		 2115static reloc_howto_type *
2116elf32_arm_reloc_name_lookup (bfd *abfd ATTRIBUTE_UNUSED,
2117 const char *r_name)
2118{
2119 unsigned int i;
2120
906e58ca 2121 for (i = 0; i < ARRAY_SIZE (elf32_arm_howto_table_1); i++)
157090f7
AM		 2122 if (elf32_arm_howto_table_1[i].name != NULL
2123 && strcasecmp (elf32_arm_howto_table_1[i].name, r_name) == 0)
2124 return &elf32_arm_howto_table_1[i];
2125
906e58ca 2126 for (i = 0; i < ARRAY_SIZE (elf32_arm_howto_table_2); i++)
157090f7
AM		 2127 if (elf32_arm_howto_table_2[i].name != NULL
2128 && strcasecmp (elf32_arm_howto_table_2[i].name, r_name) == 0)
2129 return &elf32_arm_howto_table_2[i];
2130
34e77a92
RS		 2131 for (i = 0; i < ARRAY_SIZE (elf32_arm_howto_table_3); i++)
2132 if (elf32_arm_howto_table_3[i].name != NULL
2133 && strcasecmp (elf32_arm_howto_table_3[i].name, r_name) == 0)
2134 return &elf32_arm_howto_table_3[i];
2135
157090f7
AM		 2136 return NULL;
2137}
2138
906e58ca
NC		 2139/* Support for core dump NOTE sections. */
2140
7f266840 2141static bfd_boolean
f1c71a59 2142elf32_arm_nabi_grok_prstatus (bfd *abfd, Elf_Internal_Note *note)
7f266840
DJ		 2143{
2144 int offset;
2145 size_t size;
2146
2147 switch (note->descsz)
2148 {
2149 default:
2150 return FALSE;
2151
8029a119 2152 case 148: /* Linux/ARM 32-bit. */
7f266840 2153 /* pr_cursig */
228e534f 2154 elf_tdata (abfd)->core->signal = bfd_get_16 (abfd, note->descdata + 12);
7f266840
DJ		 2155
2156 /* pr_pid */
228e534f 2157 elf_tdata (abfd)->core->lwpid = bfd_get_32 (abfd, note->descdata + 24);
7f266840
DJ		 2158
2159 /* pr_reg */
2160 offset = 72;
2161 size = 72;
2162
2163 break;
2164 }
2165
2166 /* Make a ".reg/999" section. */
2167 return _bfd_elfcore_make_pseudosection (abfd, ".reg",
2168 size, note->descpos + offset);
2169}
2170
2171static bfd_boolean
f1c71a59 2172elf32_arm_nabi_grok_psinfo (bfd *abfd, Elf_Internal_Note *note)
7f266840
DJ		 2173{
2174 switch (note->descsz)
2175 {
2176 default:
2177 return FALSE;
2178
8029a119 2179 case 124: /* Linux/ARM elf_prpsinfo. */
228e534f 2180 elf_tdata (abfd)->core->pid
4395ee08 2181 = bfd_get_32 (abfd, note->descdata + 12);
228e534f 2182 elf_tdata (abfd)->core->program
7f266840 2183 = _bfd_elfcore_strndup (abfd, note->descdata + 28, 16);
228e534f 2184 elf_tdata (abfd)->core->command
7f266840
DJ		 2185 = _bfd_elfcore_strndup (abfd, note->descdata + 44, 80);
2186 }
2187
2188 /* Note that for some reason, a spurious space is tacked
2189 onto the end of the args in some (at least one anyway)
2190 implementations, so strip it off if it exists. */
7f266840 2191 {
228e534f 2192 char *command = elf_tdata (abfd)->core->command;
7f266840
DJ		 2193 int n = strlen (command);
2194
2195 if (0 < n && command[n - 1] == ' ')
2196 command[n - 1] = '\0';
2197 }
2198
2199 return TRUE;
2200}
2201
1f20dca5
UW		 2202static char *
2203elf32_arm_nabi_write_core_note (bfd *abfd, char *buf, int *bufsiz,
2204 int note_type, ...)
2205{
2206 switch (note_type)
2207 {
2208 default:
2209 return NULL;
2210
2211 case NT_PRPSINFO:
2212 {
602f1657 2213 char data[124] ATTRIBUTE_NONSTRING;
1f20dca5
UW		 2214 va_list ap;
2215
2216 va_start (ap, note_type);
2217 memset (data, 0, sizeof (data));
2218 strncpy (data + 28, va_arg (ap, const char *), 16);
be3e27bb 2219#if GCC_VERSION == 8000 || GCC_VERSION == 8001
95da9854 2220 DIAGNOSTIC_PUSH;
be3e27bb 2221 /* GCC 8.0 and 8.1 warn about 80 equals destination size with
95da9854
L		 2222 -Wstringop-truncation:
2223 https://gcc.gnu.org/bugzilla/show_bug.cgi?id=85643
2224 */
95da9854
L		 2225 DIAGNOSTIC_IGNORE_STRINGOP_TRUNCATION;
2226#endif
1f20dca5 2227 strncpy (data + 44, va_arg (ap, const char *), 80);
be3e27bb 2228#if GCC_VERSION == 8000 || GCC_VERSION == 8001
95da9854 2229 DIAGNOSTIC_POP;
fe75810f 2230#endif
1f20dca5
UW		 2231 va_end (ap);
2232
2233 return elfcore_write_note (abfd, buf, bufsiz,
2234 "CORE", note_type, data, sizeof (data));
2235 }
2236
2237 case NT_PRSTATUS:
2238 {
2239 char data[148];
2240 va_list ap;
2241 long pid;
2242 int cursig;
2243 const void *greg;
2244
2245 va_start (ap, note_type);
2246 memset (data, 0, sizeof (data));
2247 pid = va_arg (ap, long);
2248 bfd_put_32 (abfd, pid, data + 24);
2249 cursig = va_arg (ap, int);
2250 bfd_put_16 (abfd, cursig, data + 12);
2251 greg = va_arg (ap, const void *);
2252 memcpy (data + 72, greg, 72);
2253 va_end (ap);
2254
2255 return elfcore_write_note (abfd, buf, bufsiz,
2256 "CORE", note_type, data, sizeof (data));
2257 }
2258 }
2259}
2260
07d6d2b8
AM		 2261#define TARGET_LITTLE_SYM arm_elf32_le_vec
2262#define TARGET_LITTLE_NAME "elf32-littlearm"
2263#define TARGET_BIG_SYM arm_elf32_be_vec
2264#define TARGET_BIG_NAME "elf32-bigarm"
7f266840
DJ		 2265
2266#define elf_backend_grok_prstatus elf32_arm_nabi_grok_prstatus
2267#define elf_backend_grok_psinfo elf32_arm_nabi_grok_psinfo
1f20dca5 2268#define elf_backend_write_core_note elf32_arm_nabi_write_core_note
7f266840 2269
252b5132
RH		 2270typedef unsigned long int insn32;
2271typedef unsigned short int insn16;
2272
3a4a14e9
PB		 2273/* In lieu of proper flags, assume all EABIv4 or later objects are
2274 interworkable. */
57e8b36a 2275#define INTERWORK_FLAG(abfd) \
3a4a14e9 2276 (EF_ARM_EABI_VERSION (elf_elfheader (abfd)->e_flags) >= EF_ARM_EABI_VER4 \
3e6b1042
DJ		 2277 || (elf_elfheader (abfd)->e_flags & EF_ARM_INTERWORK) \
2278 || ((abfd)->flags & BFD_LINKER_CREATED))
9b485d32 2279
252b5132
RH		 2280/* The linker script knows the section names for placement.
2281 The entry_names are used to do simple name mangling on the stubs.
2282 Given a function name, and its type, the stub can be found. The
9b485d32 2283 name can be changed. The only requirement is the %s be present. */
252b5132
RH		 2284#define THUMB2ARM_GLUE_SECTION_NAME ".glue_7t"
2285#define THUMB2ARM_GLUE_ENTRY_NAME "__%s_from_thumb"
2286
2287#define ARM2THUMB_GLUE_SECTION_NAME ".glue_7"
2288#define ARM2THUMB_GLUE_ENTRY_NAME "__%s_from_arm"
2289
c7b8f16e
JB		 2290#define VFP11_ERRATUM_VENEER_SECTION_NAME ".vfp11_veneer"
2291#define VFP11_ERRATUM_VENEER_ENTRY_NAME "__vfp11_veneer_%x"
2292
a504d23a
LA		 2293#define STM32L4XX_ERRATUM_VENEER_SECTION_NAME ".text.stm32l4xx_veneer"
2294#define STM32L4XX_ERRATUM_VENEER_ENTRY_NAME "__stm32l4xx_veneer_%x"
2295
845b51d6
PB		 2296#define ARM_BX_GLUE_SECTION_NAME ".v4_bx"
2297#define ARM_BX_GLUE_ENTRY_NAME "__bx_r%d"
2298
7413f23f
DJ		 2299#define STUB_ENTRY_NAME "__%s_veneer"
2300
4ba2ef8f
TP		 2301#define CMSE_PREFIX "__acle_se_"
2302
4d83e8d9
CL		 2303#define CMSE_STUB_NAME ".gnu.sgstubs"
2304
252b5132
RH		 2305/* The name of the dynamic interpreter. This is put in the .interp
2306 section. */
2307#define ELF_DYNAMIC_INTERPRETER "/usr/lib/ld.so.1"
2308
cb10292c
CL		 2309/* FDPIC default stack size. */
2310#define DEFAULT_STACK_SIZE 0x8000
2311
0855e32b 2312static const unsigned long tls_trampoline [] =
b38cadfb
NC		 2313{
2314 0xe08e0000, /* add r0, lr, r0 */
2315 0xe5901004, /* ldr r1, [r0,#4] */
2316 0xe12fff11, /* bx r1 */
2317};
0855e32b
NS		 2318
2319static const unsigned long dl_tlsdesc_lazy_trampoline [] =
b38cadfb
NC		 2320{
2321 0xe52d2004, /* push {r2} */
2322 0xe59f200c, /* ldr r2, [pc, #3f - . - 8] */
2323 0xe59f100c, /* ldr r1, [pc, #4f - . - 8] */
2324 0xe79f2002, /* 1: ldr r2, [pc, r2] */
2325 0xe081100f, /* 2: add r1, pc */
2326 0xe12fff12, /* bx r2 */
2327 0x00000014, /* 3: .word _GLOBAL_OFFSET_TABLE_ - 1b - 8
99059e56 2328 + dl_tlsdesc_lazy_resolver(GOT) */
b38cadfb
NC		 2329 0x00000018, /* 4: .word _GLOBAL_OFFSET_TABLE_ - 2b - 8 */
2330};
0855e32b 2331
b4e87f2c
TC		 2332/* NOTE: [Thumb nop sequence]
2333 When adding code that transitions from Thumb to Arm the instruction that
2334 should be used for the alignment padding should be 0xe7fd (b .-2) instead of
2335 a nop for performance reasons. */
2336
7801f98f
CL		 2337/* ARM FDPIC PLT entry. */
2338/* The last 5 words contain PLT lazy fragment code and data. */
2339static const bfd_vma elf32_arm_fdpic_plt_entry [] =
2340 {
2341 0xe59fc008, /* ldr r12, .L1 */
2342 0xe08cc009, /* add r12, r12, r9 */
2343 0xe59c9004, /* ldr r9, [r12, #4] */
2344 0xe59cf000, /* ldr pc, [r12] */
2345 0x00000000, /* L1. .word foo(GOTOFFFUNCDESC) */
2346 0x00000000, /* L1. .word foo(funcdesc_value_reloc_offset) */
2347 0xe51fc00c, /* ldr r12, [pc, #-12] */
2348 0xe92d1000, /* push {r12} */
2349 0xe599c004, /* ldr r12, [r9, #4] */
2350 0xe599f000, /* ldr pc, [r9] */
2351 };
2352
59029f57
CL		 2353/* Thumb FDPIC PLT entry. */
2354/* The last 5 words contain PLT lazy fragment code and data. */
2355static const bfd_vma elf32_arm_fdpic_thumb_plt_entry [] =
2356 {
2357 0xc00cf8df, /* ldr.w r12, .L1 */
2358 0x0c09eb0c, /* add.w r12, r12, r9 */
2359 0x9004f8dc, /* ldr.w r9, [r12, #4] */
2360 0xf000f8dc, /* ldr.w pc, [r12] */
2361 0x00000000, /* .L1 .word foo(GOTOFFFUNCDESC) */
2362 0x00000000, /* .L2 .word foo(funcdesc_value_reloc_offset) */
2363 0xc008f85f, /* ldr.w r12, .L2 */
2364 0xcd04f84d, /* push {r12} */
2365 0xc004f8d9, /* ldr.w r12, [r9, #4] */
2366 0xf000f8d9, /* ldr.w pc, [r9] */
2367 };
2368
5e681ec4
PB		 2369#ifdef FOUR_WORD_PLT
2370
252b5132
RH		 2371/* The first entry in a procedure linkage table looks like
2372 this. It is set up so that any shared library function that is
59f2c4e7 2373 called before the relocation has been set up calls the dynamic
9b485d32 2374 linker first. */
e5a52504 2375static const bfd_vma elf32_arm_plt0_entry [] =
b38cadfb
NC		 2376{
2377 0xe52de004, /* str lr, [sp, #-4]! */
2378 0xe59fe010, /* ldr lr, [pc, #16] */
2379 0xe08fe00e, /* add lr, pc, lr */
2380 0xe5bef008, /* ldr pc, [lr, #8]! */
2381};
5e681ec4
PB		 2382
2383/* Subsequent entries in a procedure linkage table look like
2384 this. */
e5a52504 2385static const bfd_vma elf32_arm_plt_entry [] =
b38cadfb
NC		 2386{
2387 0xe28fc600, /* add ip, pc, #NN */
2388 0xe28cca00, /* add ip, ip, #NN */
2389 0xe5bcf000, /* ldr pc, [ip, #NN]! */
2390 0x00000000, /* unused */
2391};
5e681ec4 2392
eed94f8f 2393#else /* not FOUR_WORD_PLT */
5e681ec4 2394
5e681ec4
PB		 2395/* The first entry in a procedure linkage table looks like
2396 this. It is set up so that any shared library function that is
2397 called before the relocation has been set up calls the dynamic
2398 linker first. */
e5a52504 2399static const bfd_vma elf32_arm_plt0_entry [] =
b38cadfb 2400{
07d6d2b8
AM		 2401 0xe52de004, /* str lr, [sp, #-4]! */
2402 0xe59fe004, /* ldr lr, [pc, #4] */
2403 0xe08fe00e, /* add lr, pc, lr */
2404 0xe5bef008, /* ldr pc, [lr, #8]! */
2405 0x00000000, /* &GOT[0] - . */
b38cadfb 2406};
252b5132 2407
1db37fe6
YG		 2408/* By default subsequent entries in a procedure linkage table look like
2409 this. Offsets that don't fit into 28 bits will cause link error. */
2410static const bfd_vma elf32_arm_plt_entry_short [] =
b38cadfb
NC		 2411{
2412 0xe28fc600, /* add ip, pc, #0xNN00000 */
2413 0xe28cca00, /* add ip, ip, #0xNN000 */
2414 0xe5bcf000, /* ldr pc, [ip, #0xNNN]! */
2415};
5e681ec4 2416
1db37fe6
YG		 2417/* When explicitly asked, we'll use this "long" entry format
2418 which can cope with arbitrary displacements. */
2419static const bfd_vma elf32_arm_plt_entry_long [] =
2420{
07d6d2b8
AM		 2421 0xe28fc200, /* add ip, pc, #0xN0000000 */
2422 0xe28cc600, /* add ip, ip, #0xNN00000 */
1db37fe6
YG		 2423 0xe28cca00, /* add ip, ip, #0xNN000 */
2424 0xe5bcf000, /* ldr pc, [ip, #0xNNN]! */
2425};
2426
2427static bfd_boolean elf32_arm_use_long_plt_entry = FALSE;
2428
eed94f8f
NC		 2429#endif /* not FOUR_WORD_PLT */
2430
2431/* The first entry in a procedure linkage table looks like this.
2432 It is set up so that any shared library function that is called before the
2433 relocation has been set up calls the dynamic linker first. */
2434static const bfd_vma elf32_thumb2_plt0_entry [] =
2435{
2436 /* NOTE: As this is a mixture of 16-bit and 32-bit instructions,
2437 an instruction maybe encoded to one or two array elements. */
07d6d2b8
AM		 2438 0xf8dfb500, /* push {lr} */
2439 0x44fee008, /* ldr.w lr, [pc, #8] */
2440 /* add lr, pc */
eed94f8f 2441 0xff08f85e, /* ldr.w pc, [lr, #8]! */
07d6d2b8 2442 0x00000000, /* &GOT[0] - . */
eed94f8f
NC		 2443};
2444
2445/* Subsequent entries in a procedure linkage table for thumb only target
2446 look like this. */
2447static const bfd_vma elf32_thumb2_plt_entry [] =
2448{
2449 /* NOTE: As this is a mixture of 16-bit and 32-bit instructions,
2450 an instruction maybe encoded to one or two array elements. */
07d6d2b8
AM		 2451 0x0c00f240, /* movw ip, #0xNNNN */
2452 0x0c00f2c0, /* movt ip, #0xNNNN */
2453 0xf8dc44fc, /* add ip, pc */
b4e87f2c
TC		 2454 0xe7fdf000 /* ldr.w pc, [ip] */
2455 /* b .-2 */
eed94f8f 2456};
252b5132 2457
00a97672
RS		 2458/* The format of the first entry in the procedure linkage table
2459 for a VxWorks executable. */
2460static const bfd_vma elf32_arm_vxworks_exec_plt0_entry[] =
b38cadfb 2461{
07d6d2b8
AM		 2462 0xe52dc008, /* str ip,[sp,#-8]! */
2463 0xe59fc000, /* ldr ip,[pc] */
2464 0xe59cf008, /* ldr pc,[ip,#8] */
2465 0x00000000, /* .long _GLOBAL_OFFSET_TABLE_ */
b38cadfb 2466};
00a97672
RS		 2467
2468/* The format of subsequent entries in a VxWorks executable. */
2469static const bfd_vma elf32_arm_vxworks_exec_plt_entry[] =
b38cadfb 2470{
07d6d2b8
AM		 2471 0xe59fc000, /* ldr ip,[pc] */
2472 0xe59cf000, /* ldr pc,[ip] */
2473 0x00000000, /* .long @got */
2474 0xe59fc000, /* ldr ip,[pc] */
2475 0xea000000, /* b _PLT */
2476 0x00000000, /* .long @pltindex*sizeof(Elf32_Rela) */
b38cadfb 2477};
00a97672
RS		 2478
2479/* The format of entries in a VxWorks shared library. */
2480static const bfd_vma elf32_arm_vxworks_shared_plt_entry[] =
b38cadfb 2481{
07d6d2b8
AM		 2482 0xe59fc000, /* ldr ip,[pc] */
2483 0xe79cf009, /* ldr pc,[ip,r9] */
2484 0x00000000, /* .long @got */
2485 0xe59fc000, /* ldr ip,[pc] */
2486 0xe599f008, /* ldr pc,[r9,#8] */
2487 0x00000000, /* .long @pltindex*sizeof(Elf32_Rela) */
b38cadfb 2488};
00a97672 2489
b7693d02
DJ		 2490/* An initial stub used if the PLT entry is referenced from Thumb code. */
2491#define PLT_THUMB_STUB_SIZE 4
2492static const bfd_vma elf32_arm_plt_thumb_stub [] =
b38cadfb
NC		 2493{
2494 0x4778, /* bx pc */
b4e87f2c 2495 0xe7fd /* b .-2 */
b38cadfb 2496};
b7693d02 2497
e5a52504
MM		 2498/* The entries in a PLT when using a DLL-based target with multiple
2499 address spaces. */
906e58ca 2500static const bfd_vma elf32_arm_symbian_plt_entry [] =
b38cadfb 2501{
07d6d2b8
AM		 2502 0xe51ff004, /* ldr pc, [pc, #-4] */
2503 0x00000000, /* dcd R_ARM_GLOB_DAT(X) */
b38cadfb
NC		 2504};
2505
2506/* The first entry in a procedure linkage table looks like
2507 this. It is set up so that any shared library function that is
2508 called before the relocation has been set up calls the dynamic
2509 linker first. */
2510static const bfd_vma elf32_arm_nacl_plt0_entry [] =
2511{
2512 /* First bundle: */
2513 0xe300c000, /* movw ip, #:lower16:&GOT[2]-.+8 */
2514 0xe340c000, /* movt ip, #:upper16:&GOT[2]-.+8 */
2515 0xe08cc00f, /* add ip, ip, pc */
2516 0xe52dc008, /* str ip, [sp, #-8]! */
2517 /* Second bundle: */
edccdf7c
RM		 2518 0xe3ccc103, /* bic ip, ip, #0xc0000000 */
2519 0xe59cc000, /* ldr ip, [ip] */
b38cadfb 2520 0xe3ccc13f, /* bic ip, ip, #0xc000000f */
edccdf7c 2521 0xe12fff1c, /* bx ip */
b38cadfb 2522 /* Third bundle: */
edccdf7c
RM		 2523 0xe320f000, /* nop */
2524 0xe320f000, /* nop */
2525 0xe320f000, /* nop */
b38cadfb
NC		 2526 /* .Lplt_tail: */
2527 0xe50dc004, /* str ip, [sp, #-4] */
2528 /* Fourth bundle: */
edccdf7c
RM		 2529 0xe3ccc103, /* bic ip, ip, #0xc0000000 */
2530 0xe59cc000, /* ldr ip, [ip] */
b38cadfb 2531 0xe3ccc13f, /* bic ip, ip, #0xc000000f */
edccdf7c 2532 0xe12fff1c, /* bx ip */
b38cadfb
NC		 2533};
2534#define ARM_NACL_PLT_TAIL_OFFSET (11 * 4)
2535
2536/* Subsequent entries in a procedure linkage table look like this. */
2537static const bfd_vma elf32_arm_nacl_plt_entry [] =
2538{
2539 0xe300c000, /* movw ip, #:lower16:&GOT[n]-.+8 */
2540 0xe340c000, /* movt ip, #:upper16:&GOT[n]-.+8 */
2541 0xe08cc00f, /* add ip, ip, pc */
2542 0xea000000, /* b .Lplt_tail */
2543};
e5a52504 2544
906e58ca
NC		 2545#define ARM_MAX_FWD_BRANCH_OFFSET ((((1 << 23) - 1) << 2) + 8)
2546#define ARM_MAX_BWD_BRANCH_OFFSET ((-((1 << 23) << 2)) + 8)
2547#define THM_MAX_FWD_BRANCH_OFFSET ((1 << 22) -2 + 4)
2548#define THM_MAX_BWD_BRANCH_OFFSET (-(1 << 22) + 4)
2549#define THM2_MAX_FWD_BRANCH_OFFSET (((1 << 24) - 2) + 4)
2550#define THM2_MAX_BWD_BRANCH_OFFSET (-(1 << 24) + 4)
c5423981
TG		 2551#define THM2_MAX_FWD_COND_BRANCH_OFFSET (((1 << 20) -2) + 4)
2552#define THM2_MAX_BWD_COND_BRANCH_OFFSET (-(1 << 20) + 4)
906e58ca 2553
461a49ca 2554enum stub_insn_type
b38cadfb
NC		 2555{
2556 THUMB16_TYPE = 1,
2557 THUMB32_TYPE,
2558 ARM_TYPE,
2559 DATA_TYPE
2560};
461a49ca 2561
48229727
JB		 2562#define THUMB16_INSN(X) {(X), THUMB16_TYPE, R_ARM_NONE, 0}
2563/* A bit of a hack. A Thumb conditional branch, in which the proper condition
2564 is inserted in arm_build_one_stub(). */
2565#define THUMB16_BCOND_INSN(X) {(X), THUMB16_TYPE, R_ARM_NONE, 1}
2566#define THUMB32_INSN(X) {(X), THUMB32_TYPE, R_ARM_NONE, 0}
d5a67c02
AV		 2567#define THUMB32_MOVT(X) {(X), THUMB32_TYPE, R_ARM_THM_MOVT_ABS, 0}
2568#define THUMB32_MOVW(X) {(X), THUMB32_TYPE, R_ARM_THM_MOVW_ABS_NC, 0}
48229727
JB		 2569#define THUMB32_B_INSN(X, Z) {(X), THUMB32_TYPE, R_ARM_THM_JUMP24, (Z)}
2570#define ARM_INSN(X) {(X), ARM_TYPE, R_ARM_NONE, 0}
2571#define ARM_REL_INSN(X, Z) {(X), ARM_TYPE, R_ARM_JUMP24, (Z)}
2572#define DATA_WORD(X,Y,Z) {(X), DATA_TYPE, (Y), (Z)}
461a49ca
DJ		 2573
2574typedef struct
2575{
07d6d2b8 2576 bfd_vma data;
b38cadfb 2577 enum stub_insn_type type;
07d6d2b8
AM		 2578 unsigned int r_type;
2579 int reloc_addend;
461a49ca
DJ		 2580} insn_sequence;
2581
b4e87f2c
TC		 2582/* See note [Thumb nop sequence] when adding a veneer. */
2583
fea2b4d6
CL		 2584/* Arm/Thumb -> Arm/Thumb long branch stub. On V5T and above, use blx
2585 to reach the stub if necessary. */
461a49ca 2586static const insn_sequence elf32_arm_stub_long_branch_any_any[] =
b38cadfb 2587{
07d6d2b8 2588 ARM_INSN (0xe51ff004), /* ldr pc, [pc, #-4] */
b38cadfb
NC		 2589 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(X) */
2590};
906e58ca 2591
fea2b4d6
CL		 2592/* V4T Arm -> Thumb long branch stub. Used on V4T where blx is not
2593 available. */
461a49ca 2594static const insn_sequence elf32_arm_stub_long_branch_v4t_arm_thumb[] =
b38cadfb 2595{
07d6d2b8
AM		 2596 ARM_INSN (0xe59fc000), /* ldr ip, [pc, #0] */
2597 ARM_INSN (0xe12fff1c), /* bx ip */
b38cadfb
NC		 2598 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(X) */
2599};
906e58ca 2600
d3626fb0 2601/* Thumb -> Thumb long branch stub. Used on M-profile architectures. */
461a49ca 2602static const insn_sequence elf32_arm_stub_long_branch_thumb_only[] =
b38cadfb 2603{
07d6d2b8
AM		 2604 THUMB16_INSN (0xb401), /* push {r0} */
2605 THUMB16_INSN (0x4802), /* ldr r0, [pc, #8] */
2606 THUMB16_INSN (0x4684), /* mov ip, r0 */
2607 THUMB16_INSN (0xbc01), /* pop {r0} */
2608 THUMB16_INSN (0x4760), /* bx ip */
2609 THUMB16_INSN (0xbf00), /* nop */
b38cadfb
NC		 2610 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(X) */
2611};
906e58ca 2612
80c135e5
TP		 2613/* Thumb -> Thumb long branch stub in thumb2 encoding. Used on armv7. */
2614static const insn_sequence elf32_arm_stub_long_branch_thumb2_only[] =
2615{
07d6d2b8 2616 THUMB32_INSN (0xf85ff000), /* ldr.w pc, [pc, #-0] */
80c135e5
TP		 2617 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(x) */
2618};
2619
d5a67c02
AV		 2620/* Thumb -> Thumb long branch stub. Used for PureCode sections on Thumb2
2621 M-profile architectures. */
2622static const insn_sequence elf32_arm_stub_long_branch_thumb2_only_pure[] =
2623{
2624 THUMB32_MOVW (0xf2400c00), /* mov.w ip, R_ARM_MOVW_ABS_NC */
2625 THUMB32_MOVT (0xf2c00c00), /* movt ip, R_ARM_MOVT_ABS << 16 */
07d6d2b8 2626 THUMB16_INSN (0x4760), /* bx ip */
d5a67c02
AV		 2627};
2628
d3626fb0
CL		 2629/* V4T Thumb -> Thumb long branch stub. Using the stack is not
2630 allowed. */
2631static const insn_sequence elf32_arm_stub_long_branch_v4t_thumb_thumb[] =
b38cadfb 2632{
07d6d2b8 2633 THUMB16_INSN (0x4778), /* bx pc */
b4e87f2c 2634 THUMB16_INSN (0xe7fd), /* b .-2 */
07d6d2b8
AM		 2635 ARM_INSN (0xe59fc000), /* ldr ip, [pc, #0] */
2636 ARM_INSN (0xe12fff1c), /* bx ip */
b38cadfb
NC		 2637 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(X) */
2638};
d3626fb0 2639
fea2b4d6
CL		 2640/* V4T Thumb -> ARM long branch stub. Used on V4T where blx is not
2641 available. */
461a49ca 2642static const insn_sequence elf32_arm_stub_long_branch_v4t_thumb_arm[] =
b38cadfb 2643{
07d6d2b8 2644 THUMB16_INSN (0x4778), /* bx pc */
b4e87f2c 2645 THUMB16_INSN (0xe7fd), /* b .-2 */
07d6d2b8 2646 ARM_INSN (0xe51ff004), /* ldr pc, [pc, #-4] */
b38cadfb
NC		 2647 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(X) */
2648};
906e58ca 2649
fea2b4d6
CL		 2650/* V4T Thumb -> ARM short branch stub. Shorter variant of the above
2651 one, when the destination is close enough. */
461a49ca 2652static const insn_sequence elf32_arm_stub_short_branch_v4t_thumb_arm[] =
b38cadfb 2653{
07d6d2b8 2654 THUMB16_INSN (0x4778), /* bx pc */
b4e87f2c 2655 THUMB16_INSN (0xe7fd), /* b .-2 */
b38cadfb
NC		 2656 ARM_REL_INSN (0xea000000, -8), /* b (X-8) */
2657};
c820be07 2658
cf3eccff 2659/* ARM/Thumb -> ARM long branch stub, PIC. On V5T and above, use
fea2b4d6 2660 blx to reach the stub if necessary. */
cf3eccff 2661static const insn_sequence elf32_arm_stub_long_branch_any_arm_pic[] =
b38cadfb 2662{
07d6d2b8
AM		 2663 ARM_INSN (0xe59fc000), /* ldr ip, [pc] */
2664 ARM_INSN (0xe08ff00c), /* add pc, pc, ip */
b38cadfb
NC		 2665 DATA_WORD (0, R_ARM_REL32, -4), /* dcd R_ARM_REL32(X-4) */
2666};
906e58ca 2667
cf3eccff
DJ		 2668/* ARM/Thumb -> Thumb long branch stub, PIC. On V5T and above, use
2669 blx to reach the stub if necessary. We can not add into pc;
2670 it is not guaranteed to mode switch (different in ARMv6 and
2671 ARMv7). */
2672static const insn_sequence elf32_arm_stub_long_branch_any_thumb_pic[] =
b38cadfb 2673{
07d6d2b8
AM		 2674 ARM_INSN (0xe59fc004), /* ldr ip, [pc, #4] */
2675 ARM_INSN (0xe08fc00c), /* add ip, pc, ip */
2676 ARM_INSN (0xe12fff1c), /* bx ip */
b38cadfb
NC		 2677 DATA_WORD (0, R_ARM_REL32, 0), /* dcd R_ARM_REL32(X) */
2678};
cf3eccff 2679
ebe24dd4
CL		 2680/* V4T ARM -> ARM long branch stub, PIC. */
2681static const insn_sequence elf32_arm_stub_long_branch_v4t_arm_thumb_pic[] =
b38cadfb 2682{
07d6d2b8
AM		 2683 ARM_INSN (0xe59fc004), /* ldr ip, [pc, #4] */
2684 ARM_INSN (0xe08fc00c), /* add ip, pc, ip */
2685 ARM_INSN (0xe12fff1c), /* bx ip */
b38cadfb
NC		 2686 DATA_WORD (0, R_ARM_REL32, 0), /* dcd R_ARM_REL32(X) */
2687};
ebe24dd4
CL		 2688
2689/* V4T Thumb -> ARM long branch stub, PIC. */
2690static const insn_sequence elf32_arm_stub_long_branch_v4t_thumb_arm_pic[] =
b38cadfb 2691{
07d6d2b8 2692 THUMB16_INSN (0x4778), /* bx pc */
b4e87f2c 2693 THUMB16_INSN (0xe7fd), /* b .-2 */
07d6d2b8
AM		 2694 ARM_INSN (0xe59fc000), /* ldr ip, [pc, #0] */
2695 ARM_INSN (0xe08cf00f), /* add pc, ip, pc */
b38cadfb
NC		 2696 DATA_WORD (0, R_ARM_REL32, -4), /* dcd R_ARM_REL32(X) */
2697};
ebe24dd4 2698
d3626fb0
CL		 2699/* Thumb -> Thumb long branch stub, PIC. Used on M-profile
2700 architectures. */
ebe24dd4 2701static const insn_sequence elf32_arm_stub_long_branch_thumb_only_pic[] =
b38cadfb 2702{
07d6d2b8
AM		 2703 THUMB16_INSN (0xb401), /* push {r0} */
2704 THUMB16_INSN (0x4802), /* ldr r0, [pc, #8] */
2705 THUMB16_INSN (0x46fc), /* mov ip, pc */
2706 THUMB16_INSN (0x4484), /* add ip, r0 */
2707 THUMB16_INSN (0xbc01), /* pop {r0} */
2708 THUMB16_INSN (0x4760), /* bx ip */
b38cadfb
NC		 2709 DATA_WORD (0, R_ARM_REL32, 4), /* dcd R_ARM_REL32(X) */
2710};
ebe24dd4 2711
d3626fb0
CL		 2712/* V4T Thumb -> Thumb long branch stub, PIC. Using the stack is not
2713 allowed. */
2714static const insn_sequence elf32_arm_stub_long_branch_v4t_thumb_thumb_pic[] =
b38cadfb 2715{
07d6d2b8 2716 THUMB16_INSN (0x4778), /* bx pc */
b4e87f2c 2717 THUMB16_INSN (0xe7fd), /* b .-2 */
07d6d2b8
AM		 2718 ARM_INSN (0xe59fc004), /* ldr ip, [pc, #4] */
2719 ARM_INSN (0xe08fc00c), /* add ip, pc, ip */
2720 ARM_INSN (0xe12fff1c), /* bx ip */
b38cadfb
NC		 2721 DATA_WORD (0, R_ARM_REL32, 0), /* dcd R_ARM_REL32(X) */
2722};
d3626fb0 2723
0855e32b
NS		 2724/* Thumb2/ARM -> TLS trampoline. Lowest common denominator, which is a
2725 long PIC stub. We can use r1 as a scratch -- and cannot use ip. */
2726static const insn_sequence elf32_arm_stub_long_branch_any_tls_pic[] =
2727{
07d6d2b8
AM		 2728 ARM_INSN (0xe59f1000), /* ldr r1, [pc] */
2729 ARM_INSN (0xe08ff001), /* add pc, pc, r1 */
b38cadfb 2730 DATA_WORD (0, R_ARM_REL32, -4), /* dcd R_ARM_REL32(X-4) */
0855e32b
NS		 2731};
2732
2733/* V4T Thumb -> TLS trampoline. lowest common denominator, which is a
2734 long PIC stub. We can use r1 as a scratch -- and cannot use ip. */
2735static const insn_sequence elf32_arm_stub_long_branch_v4t_thumb_tls_pic[] =
2736{
07d6d2b8 2737 THUMB16_INSN (0x4778), /* bx pc */
b4e87f2c 2738 THUMB16_INSN (0xe7fd), /* b .-2 */
07d6d2b8
AM		 2739 ARM_INSN (0xe59f1000), /* ldr r1, [pc, #0] */
2740 ARM_INSN (0xe081f00f), /* add pc, r1, pc */
b38cadfb 2741 DATA_WORD (0, R_ARM_REL32, -4), /* dcd R_ARM_REL32(X) */
0855e32b
NS		 2742};
2743
7a89b94e
NC		 2744/* NaCl ARM -> ARM long branch stub. */
2745static const insn_sequence elf32_arm_stub_long_branch_arm_nacl[] =
2746{
2747 ARM_INSN (0xe59fc00c), /* ldr ip, [pc, #12] */
2748 ARM_INSN (0xe3ccc13f), /* bic ip, ip, #0xc000000f */
07d6d2b8
AM		 2749 ARM_INSN (0xe12fff1c), /* bx ip */
2750 ARM_INSN (0xe320f000), /* nop */
2751 ARM_INSN (0xe125be70), /* bkpt 0x5be0 */
2752 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(X) */
2753 DATA_WORD (0, R_ARM_NONE, 0), /* .word 0 */
2754 DATA_WORD (0, R_ARM_NONE, 0), /* .word 0 */
7a89b94e
NC		 2755};
2756
2757/* NaCl ARM -> ARM long branch stub, PIC. */
2758static const insn_sequence elf32_arm_stub_long_branch_arm_nacl_pic[] =
2759{
2760 ARM_INSN (0xe59fc00c), /* ldr ip, [pc, #12] */
07d6d2b8 2761 ARM_INSN (0xe08cc00f), /* add ip, ip, pc */
7a89b94e 2762 ARM_INSN (0xe3ccc13f), /* bic ip, ip, #0xc000000f */
07d6d2b8
AM		 2763 ARM_INSN (0xe12fff1c), /* bx ip */
2764 ARM_INSN (0xe125be70), /* bkpt 0x5be0 */
2765 DATA_WORD (0, R_ARM_REL32, 8), /* dcd R_ARM_REL32(X+8) */
2766 DATA_WORD (0, R_ARM_NONE, 0), /* .word 0 */
2767 DATA_WORD (0, R_ARM_NONE, 0), /* .word 0 */
7a89b94e
NC		 2768};
2769
4ba2ef8f
TP		 2770/* Stub used for transition to secure state (aka SG veneer). */
2771static const insn_sequence elf32_arm_stub_cmse_branch_thumb_only[] =
2772{
2773 THUMB32_INSN (0xe97fe97f), /* sg. */
2774 THUMB32_B_INSN (0xf000b800, -4), /* b.w original_branch_dest. */
2775};
2776
7a89b94e 2777
48229727
JB		 2778/* Cortex-A8 erratum-workaround stubs. */
2779
2780/* Stub used for conditional branches (which may be beyond +/-1MB away, so we
2781 can't use a conditional branch to reach this stub). */
2782
2783static const insn_sequence elf32_arm_stub_a8_veneer_b_cond[] =
b38cadfb 2784{
07d6d2b8 2785 THUMB16_BCOND_INSN (0xd001), /* b<cond>.n true. */
b38cadfb
NC		 2786 THUMB32_B_INSN (0xf000b800, -4), /* b.w insn_after_original_branch. */
2787 THUMB32_B_INSN (0xf000b800, -4) /* true: b.w original_branch_dest. */
2788};
48229727
JB		 2789
2790/* Stub used for b.w and bl.w instructions. */
2791
2792static const insn_sequence elf32_arm_stub_a8_veneer_b[] =
b38cadfb
NC		 2793{
2794 THUMB32_B_INSN (0xf000b800, -4) /* b.w original_branch_dest. */
2795};
48229727
JB		 2796
2797static const insn_sequence elf32_arm_stub_a8_veneer_bl[] =
b38cadfb
NC		 2798{
2799 THUMB32_B_INSN (0xf000b800, -4) /* b.w original_branch_dest. */
2800};
48229727
JB		 2801
2802/* Stub used for Thumb-2 blx.w instructions. We modified the original blx.w
2803 instruction (which switches to ARM mode) to point to this stub. Jump to the
2804 real destination using an ARM-mode branch. */
2805
2806static const insn_sequence elf32_arm_stub_a8_veneer_blx[] =
b38cadfb
NC		 2807{
2808 ARM_REL_INSN (0xea000000, -8) /* b original_branch_dest. */
2809};
48229727 2810
9553db3c
NC		 2811/* For each section group there can be a specially created linker section
2812 to hold the stubs for that group. The name of the stub section is based
2813 upon the name of another section within that group with the suffix below
2814 applied.
2815
2816 PR 13049: STUB_SUFFIX used to be ".stub", but this allowed the user to
2817 create what appeared to be a linker stub section when it actually
2818 contained user code/data. For example, consider this fragment:
b38cadfb 2819
9553db3c
NC		 2820 const char * stubborn_problems[] = { "np" };
2821
2822 If this is compiled with "-fPIC -fdata-sections" then gcc produces a
2823 section called:
2824
2825 .data.rel.local.stubborn_problems
2826
2827 This then causes problems in arm32_arm_build_stubs() as it triggers:
2828
2829 // Ignore non-stub sections.
2830 if (!strstr (stub_sec->name, STUB_SUFFIX))
2831 continue;
2832
2833 And so the section would be ignored instead of being processed. Hence
2834 the change in definition of STUB_SUFFIX to a name that cannot be a valid
2835 C identifier. */
2836#define STUB_SUFFIX ".__stub"
906e58ca 2837
738a79f6
CL		 2838/* One entry per long/short branch stub defined above. */
2839#define DEF_STUBS \
2840 DEF_STUB(long_branch_any_any) \
2841 DEF_STUB(long_branch_v4t_arm_thumb) \
2842 DEF_STUB(long_branch_thumb_only) \
2843 DEF_STUB(long_branch_v4t_thumb_thumb) \
2844 DEF_STUB(long_branch_v4t_thumb_arm) \
2845 DEF_STUB(short_branch_v4t_thumb_arm) \
2846 DEF_STUB(long_branch_any_arm_pic) \
2847 DEF_STUB(long_branch_any_thumb_pic) \
2848 DEF_STUB(long_branch_v4t_thumb_thumb_pic) \
2849 DEF_STUB(long_branch_v4t_arm_thumb_pic) \
2850 DEF_STUB(long_branch_v4t_thumb_arm_pic) \
48229727 2851 DEF_STUB(long_branch_thumb_only_pic) \
0855e32b
NS		 2852 DEF_STUB(long_branch_any_tls_pic) \
2853 DEF_STUB(long_branch_v4t_thumb_tls_pic) \
7a89b94e
NC		 2854 DEF_STUB(long_branch_arm_nacl) \
2855 DEF_STUB(long_branch_arm_nacl_pic) \
4ba2ef8f 2856 DEF_STUB(cmse_branch_thumb_only) \
48229727
JB		 2857 DEF_STUB(a8_veneer_b_cond) \
2858 DEF_STUB(a8_veneer_b) \
2859 DEF_STUB(a8_veneer_bl) \
80c135e5
TP		 2860 DEF_STUB(a8_veneer_blx) \
2861 DEF_STUB(long_branch_thumb2_only) \
d5a67c02 2862 DEF_STUB(long_branch_thumb2_only_pure)
738a79f6
CL		 2863
2864#define DEF_STUB(x) arm_stub_##x,
b38cadfb
NC		 2865enum elf32_arm_stub_type
2866{
906e58ca 2867 arm_stub_none,
738a79f6 2868 DEF_STUBS
4f4faa4d 2869 max_stub_type
738a79f6
CL		 2870};
2871#undef DEF_STUB
2872
8d9d9490
TP		 2873/* Note the first a8_veneer type. */
2874const unsigned arm_stub_a8_veneer_lwm = arm_stub_a8_veneer_b_cond;
2875
738a79f6
CL		 2876typedef struct
2877{
d3ce72d0 2878 const insn_sequence* template_sequence;
738a79f6
CL		 2879 int template_size;
2880} stub_def;
2881
2882#define DEF_STUB(x) {elf32_arm_stub_##x, ARRAY_SIZE(elf32_arm_stub_##x)},
b38cadfb
NC		 2883static const stub_def stub_definitions[] =
2884{
738a79f6
CL		 2885 {NULL, 0},
2886 DEF_STUBS
906e58ca
NC		 2887};
2888
2889struct elf32_arm_stub_hash_entry
2890{
2891 /* Base hash table entry structure. */
2892 struct bfd_hash_entry root;
2893
2894 /* The stub section. */
2895 asection *stub_sec;
2896
2897 /* Offset within stub_sec of the beginning of this stub. */
2898 bfd_vma stub_offset;
2899
2900 /* Given the symbol's value and its section we can determine its final
2901 value when building the stubs (so the stub knows where to jump). */
2902 bfd_vma target_value;
2903 asection *target_section;
2904
8d9d9490
TP		 2905 /* Same as above but for the source of the branch to the stub. Used for
2906 Cortex-A8 erratum workaround to patch it to branch to the stub. As
2907 such, source section does not need to be recorded since Cortex-A8 erratum
2908 workaround stubs are only generated when both source and target are in the
2909 same section. */
2910 bfd_vma source_value;
48229727
JB		 2911
2912 /* The instruction which caused this stub to be generated (only valid for
2913 Cortex-A8 erratum workaround stubs at present). */
2914 unsigned long orig_insn;
2915
461a49ca 2916 /* The stub type. */
906e58ca 2917 enum elf32_arm_stub_type stub_type;
461a49ca
DJ		 2918 /* Its encoding size in bytes. */
2919 int stub_size;
2920 /* Its template. */
2921 const insn_sequence *stub_template;
2922 /* The size of the template (number of entries). */
2923 int stub_template_size;
906e58ca
NC		 2924
2925 /* The symbol table entry, if any, that this was derived from. */
2926 struct elf32_arm_link_hash_entry *h;
2927
35fc36a8
RS		 2928 /* Type of branch. */
2929 enum arm_st_branch_type branch_type;
906e58ca
NC		 2930
2931 /* Where this stub is being called from, or, in the case of combined
2932 stub sections, the first input section in the group. */
2933 asection *id_sec;
7413f23f
DJ		 2934
2935 /* The name for the local symbol at the start of this stub. The
2936 stub name in the hash table has to be unique; this does not, so
2937 it can be friendlier. */
2938 char *output_name;
906e58ca
NC		 2939};
2940
e489d0ae
PB		 2941/* Used to build a map of a section. This is required for mixed-endian
2942 code/data. */
2943
2944typedef struct elf32_elf_section_map
2945{
2946 bfd_vma vma;
2947 char type;
2948}
2949elf32_arm_section_map;
2950
c7b8f16e
JB		 2951/* Information about a VFP11 erratum veneer, or a branch to such a veneer. */
2952
2953typedef enum
2954{
2955 VFP11_ERRATUM_BRANCH_TO_ARM_VENEER,
2956 VFP11_ERRATUM_BRANCH_TO_THUMB_VENEER,
2957 VFP11_ERRATUM_ARM_VENEER,
2958 VFP11_ERRATUM_THUMB_VENEER
2959}
2960elf32_vfp11_erratum_type;
2961
2962typedef struct elf32_vfp11_erratum_list
2963{
2964 struct elf32_vfp11_erratum_list *next;
2965 bfd_vma vma;
2966 union
2967 {
2968 struct
2969 {
2970 struct elf32_vfp11_erratum_list *veneer;
2971 unsigned int vfp_insn;
2972 } b;
2973 struct
2974 {
2975 struct elf32_vfp11_erratum_list *branch;
2976 unsigned int id;
2977 } v;
2978 } u;
2979 elf32_vfp11_erratum_type type;
2980}
2981elf32_vfp11_erratum_list;
2982
a504d23a
LA		 2983/* Information about a STM32L4XX erratum veneer, or a branch to such a
2984 veneer. */
2985typedef enum
2986{
2987 STM32L4XX_ERRATUM_BRANCH_TO_VENEER,
2988 STM32L4XX_ERRATUM_VENEER
2989}
2990elf32_stm32l4xx_erratum_type;
2991
2992typedef struct elf32_stm32l4xx_erratum_list
2993{
2994 struct elf32_stm32l4xx_erratum_list *next;
2995 bfd_vma vma;
2996 union
2997 {
2998 struct
2999 {
3000 struct elf32_stm32l4xx_erratum_list *veneer;
3001 unsigned int insn;
3002 } b;
3003 struct
3004 {
3005 struct elf32_stm32l4xx_erratum_list *branch;
3006 unsigned int id;
3007 } v;
3008 } u;
3009 elf32_stm32l4xx_erratum_type type;
3010}
3011elf32_stm32l4xx_erratum_list;
3012
2468f9c9
PB		 3013typedef enum
3014{
3015 DELETE_EXIDX_ENTRY,
3016 INSERT_EXIDX_CANTUNWIND_AT_END
3017}
3018arm_unwind_edit_type;
3019
3020/* A (sorted) list of edits to apply to an unwind table. */
3021typedef struct arm_unwind_table_edit
3022{
3023 arm_unwind_edit_type type;
3024 /* Note: we sometimes want to insert an unwind entry corresponding to a
3025 section different from the one we're currently writing out, so record the
3026 (text) section this edit relates to here. */
3027 asection *linked_section;
3028 unsigned int index;
3029 struct arm_unwind_table_edit *next;
3030}
3031arm_unwind_table_edit;
3032
8e3de13a 3033typedef struct _arm_elf_section_data
e489d0ae 3034{
2468f9c9 3035 /* Information about mapping symbols. */
e489d0ae 3036 struct bfd_elf_section_data elf;
8e3de13a 3037 unsigned int mapcount;
c7b8f16e 3038 unsigned int mapsize;
e489d0ae 3039 elf32_arm_section_map *map;
2468f9c9 3040 /* Information about CPU errata. */
c7b8f16e
JB		 3041 unsigned int erratumcount;
3042 elf32_vfp11_erratum_list *erratumlist;
a504d23a
LA		 3043 unsigned int stm32l4xx_erratumcount;
3044 elf32_stm32l4xx_erratum_list *stm32l4xx_erratumlist;
491d01d3 3045 unsigned int additional_reloc_count;
2468f9c9
PB		 3046 /* Information about unwind tables. */
3047 union
3048 {
3049 /* Unwind info attached to a text section. */
3050 struct
3051 {
3052 asection *arm_exidx_sec;
3053 } text;
3054
3055 /* Unwind info attached to an .ARM.exidx section. */
3056 struct
3057 {
3058 arm_unwind_table_edit *unwind_edit_list;
3059 arm_unwind_table_edit *unwind_edit_tail;
3060 } exidx;
3061 } u;
8e3de13a
NC		 3062}
3063_arm_elf_section_data;
e489d0ae
PB		 3064
3065#define elf32_arm_section_data(sec) \
8e3de13a 3066 ((_arm_elf_section_data *) elf_section_data (sec))
e489d0ae 3067
48229727
JB		 3068/* A fix which might be required for Cortex-A8 Thumb-2 branch/TLB erratum.
3069 These fixes are subject to a relaxation procedure (in elf32_arm_size_stubs),
3070 so may be created multiple times: we use an array of these entries whilst
3071 relaxing which we can refresh easily, then create stubs for each potentially
3072 erratum-triggering instruction once we've settled on a solution. */
3073
b38cadfb
NC		 3074struct a8_erratum_fix
3075{
48229727
JB		 3076 bfd *input_bfd;
3077 asection *section;
3078 bfd_vma offset;
8d9d9490 3079 bfd_vma target_offset;
48229727
JB		 3080 unsigned long orig_insn;
3081 char *stub_name;
3082 enum elf32_arm_stub_type stub_type;
35fc36a8 3083 enum arm_st_branch_type branch_type;
48229727
JB		 3084};
3085
3086/* A table of relocs applied to branches which might trigger Cortex-A8
3087 erratum. */
3088
b38cadfb
NC		 3089struct a8_erratum_reloc
3090{
48229727
JB		 3091 bfd_vma from;
3092 bfd_vma destination;
92750f34
DJ		 3093 struct elf32_arm_link_hash_entry *hash;
3094 const char *sym_name;
48229727 3095 unsigned int r_type;
35fc36a8 3096 enum arm_st_branch_type branch_type;
48229727
JB		 3097 bfd_boolean non_a8_stub;
3098};
3099
ba93b8ac
DJ		 3100/* The size of the thread control block. */
3101#define TCB_SIZE 8
3102
34e77a92
RS		 3103/* ARM-specific information about a PLT entry, over and above the usual
3104 gotplt_union. */
b38cadfb
NC		 3105struct arm_plt_info
3106{
34e77a92
RS		 3107 /* We reference count Thumb references to a PLT entry separately,
3108 so that we can emit the Thumb trampoline only if needed. */
3109 bfd_signed_vma thumb_refcount;
3110
3111 /* Some references from Thumb code may be eliminated by BL->BLX
3112 conversion, so record them separately. */
3113 bfd_signed_vma maybe_thumb_refcount;
3114
3115 /* How many of the recorded PLT accesses were from non-call relocations.
3116 This information is useful when deciding whether anything takes the
3117 address of an STT_GNU_IFUNC PLT. A value of 0 means that all
3118 non-call references to the function should resolve directly to the
3119 real runtime target. */
3120 unsigned int noncall_refcount;
3121
3122 /* Since PLT entries have variable size if the Thumb prologue is
3123 used, we need to record the index into .got.plt instead of
3124 recomputing it from the PLT offset. */
3125 bfd_signed_vma got_offset;
3126};
3127
3128/* Information about an .iplt entry for a local STT_GNU_IFUNC symbol. */
b38cadfb
NC		 3129struct arm_local_iplt_info
3130{
34e77a92
RS		 3131 /* The information that is usually found in the generic ELF part of
3132 the hash table entry. */
3133 union gotplt_union root;
3134
3135 /* The information that is usually found in the ARM-specific part of
3136 the hash table entry. */
3137 struct arm_plt_info arm;
3138
3139 /* A list of all potential dynamic relocations against this symbol. */
3140 struct elf_dyn_relocs *dyn_relocs;
3141};
3142
e8b09b87
CL		 3143/* Structure to handle FDPIC support for local functions. */
3144struct fdpic_local {
3145 unsigned int funcdesc_cnt;
3146 unsigned int gotofffuncdesc_cnt;
3147 int funcdesc_offset;
3148};
3149
0ffa91dd 3150struct elf_arm_obj_tdata
ba93b8ac
DJ		 3151{
3152 struct elf_obj_tdata root;
3153
3154 /* tls_type for each local got entry. */
3155 char *local_got_tls_type;
ee065d83 3156
0855e32b
NS		 3157 /* GOTPLT entries for TLS descriptors. */
3158 bfd_vma *local_tlsdesc_gotent;
3159
34e77a92
RS		 3160 /* Information for local symbols that need entries in .iplt. */
3161 struct arm_local_iplt_info **local_iplt;
3162
bf21ed78
MS		 3163 /* Zero to warn when linking objects with incompatible enum sizes. */
3164 int no_enum_size_warning;
a9dc9481
JM		 3165
3166 /* Zero to warn when linking objects with incompatible wchar_t sizes. */
3167 int no_wchar_size_warning;
e8b09b87
CL		 3168
3169 /* Maintains FDPIC counters and funcdesc info. */
3170 struct fdpic_local *local_fdpic_cnts;
ba93b8ac
DJ		 3171};
3172
0ffa91dd
NC		 3173#define elf_arm_tdata(bfd) \
3174 ((struct elf_arm_obj_tdata *) (bfd)->tdata.any)
ba93b8ac 3175
0ffa91dd
NC		 3176#define elf32_arm_local_got_tls_type(bfd) \
3177 (elf_arm_tdata (bfd)->local_got_tls_type)
3178
0855e32b
NS		 3179#define elf32_arm_local_tlsdesc_gotent(bfd) \
3180 (elf_arm_tdata (bfd)->local_tlsdesc_gotent)
3181
34e77a92
RS		 3182#define elf32_arm_local_iplt(bfd) \
3183 (elf_arm_tdata (bfd)->local_iplt)
3184
e8b09b87
CL		 3185#define elf32_arm_local_fdpic_cnts(bfd) \
3186 (elf_arm_tdata (bfd)->local_fdpic_cnts)
3187
0ffa91dd
NC		 3188#define is_arm_elf(bfd) \
3189 (bfd_get_flavour (bfd) == bfd_target_elf_flavour \
3190 && elf_tdata (bfd) != NULL \
4dfe6ac6 3191 && elf_object_id (bfd) == ARM_ELF_DATA)
ba93b8ac
DJ		 3192
3193static bfd_boolean
3194elf32_arm_mkobject (bfd *abfd)
3195{
0ffa91dd 3196 return bfd_elf_allocate_object (abfd, sizeof (struct elf_arm_obj_tdata),
4dfe6ac6 3197 ARM_ELF_DATA);
ba93b8ac
DJ		 3198}
3199
ba93b8ac
DJ		 3200#define elf32_arm_hash_entry(ent) ((struct elf32_arm_link_hash_entry *)(ent))
3201
e8b09b87
CL		 3202/* Structure to handle FDPIC support for extern functions. */
3203struct fdpic_global {
3204 unsigned int gotofffuncdesc_cnt;
3205 unsigned int gotfuncdesc_cnt;
3206 unsigned int funcdesc_cnt;
3207 int funcdesc_offset;
3208 int gotfuncdesc_offset;
3209};
3210
ba96a88f 3211/* Arm ELF linker hash entry. */
252b5132 3212struct elf32_arm_link_hash_entry
b38cadfb
NC		 3213{
3214 struct elf_link_hash_entry root;
252b5132 3215
b38cadfb
NC		 3216 /* Track dynamic relocs copied for this symbol. */
3217 struct elf_dyn_relocs *dyn_relocs;
b7693d02 3218
b38cadfb
NC		 3219 /* ARM-specific PLT information. */
3220 struct arm_plt_info plt;
ba93b8ac
DJ		 3221
3222#define GOT_UNKNOWN 0
3223#define GOT_NORMAL 1
3224#define GOT_TLS_GD 2
3225#define GOT_TLS_IE 4
0855e32b
NS		 3226#define GOT_TLS_GDESC 8
3227#define GOT_TLS_GD_ANY_P(type) ((type & GOT_TLS_GD) || (type & GOT_TLS_GDESC))
b38cadfb 3228 unsigned int tls_type : 8;
34e77a92 3229
b38cadfb
NC		 3230 /* True if the symbol's PLT entry is in .iplt rather than .plt. */
3231 unsigned int is_iplt : 1;
34e77a92 3232
b38cadfb 3233 unsigned int unused : 23;
a4fd1a8e 3234
b38cadfb
NC		 3235 /* Offset of the GOTPLT entry reserved for the TLS descriptor,
3236 starting at the end of the jump table. */
3237 bfd_vma tlsdesc_got;
0855e32b 3238
b38cadfb
NC		 3239 /* The symbol marking the real symbol location for exported thumb
3240 symbols with Arm stubs. */
3241 struct elf_link_hash_entry *export_glue;
906e58ca 3242
b38cadfb 3243 /* A pointer to the most recently used stub hash entry against this
8029a119 3244 symbol. */
b38cadfb 3245 struct elf32_arm_stub_hash_entry *stub_cache;
e8b09b87
CL		 3246
3247 /* Counter for FDPIC relocations against this symbol. */
3248 struct fdpic_global fdpic_cnts;
b38cadfb 3249};
252b5132 3250
252b5132 3251/* Traverse an arm ELF linker hash table. */
252b5132
RH		 3252#define elf32_arm_link_hash_traverse(table, func, info) \
3253 (elf_link_hash_traverse \
3254 (&(table)->root, \
b7693d02 3255 (bfd_boolean (*) (struct elf_link_hash_entry *, void *)) (func), \
252b5132
RH		 3256 (info)))
3257
3258/* Get the ARM elf linker hash table from a link_info structure. */
3259#define elf32_arm_hash_table(info) \
4dfe6ac6
NC		 3260 (elf_hash_table_id ((struct elf_link_hash_table *) ((info)->hash)) \
3261 == ARM_ELF_DATA ? ((struct elf32_arm_link_hash_table *) ((info)->hash)) : NULL)
252b5132 3262
906e58ca
NC		 3263#define arm_stub_hash_lookup(table, string, create, copy) \
3264 ((struct elf32_arm_stub_hash_entry *) \
3265 bfd_hash_lookup ((table), (string), (create), (copy)))
3266
21d799b5
NC		 3267/* Array to keep track of which stub sections have been created, and
3268 information on stub grouping. */
3269struct map_stub
3270{
3271 /* This is the section to which stubs in the group will be
3272 attached. */
3273 asection *link_sec;
3274 /* The stub section. */
3275 asection *stub_sec;
3276};
3277
0855e32b
NS		 3278#define elf32_arm_compute_jump_table_size(htab) \
3279 ((htab)->next_tls_desc_index * 4)
3280
9b485d32 3281/* ARM ELF linker hash table. */
252b5132 3282struct elf32_arm_link_hash_table
906e58ca
NC		 3283{
3284 /* The main hash table. */
3285 struct elf_link_hash_table root;
252b5132 3286
906e58ca
NC		 3287 /* The size in bytes of the section containing the Thumb-to-ARM glue. */
3288 bfd_size_type thumb_glue_size;
252b5132 3289
906e58ca
NC		 3290 /* The size in bytes of the section containing the ARM-to-Thumb glue. */
3291 bfd_size_type arm_glue_size;
252b5132 3292
906e58ca
NC		 3293 /* The size in bytes of section containing the ARMv4 BX veneers. */
3294 bfd_size_type bx_glue_size;
845b51d6 3295
906e58ca
NC		 3296 /* Offsets of ARMv4 BX veneers. Bit1 set if present, and Bit0 set when
3297 veneer has been populated. */
3298 bfd_vma bx_glue_offset[15];
845b51d6 3299
906e58ca
NC		 3300 /* The size in bytes of the section containing glue for VFP11 erratum
3301 veneers. */
3302 bfd_size_type vfp11_erratum_glue_size;
c7b8f16e 3303
a504d23a
LA		 3304 /* The size in bytes of the section containing glue for STM32L4XX erratum
3305 veneers. */
3306 bfd_size_type stm32l4xx_erratum_glue_size;
3307
48229727
JB		 3308 /* A table of fix locations for Cortex-A8 Thumb-2 branch/TLB erratum. This
3309 holds Cortex-A8 erratum fix locations between elf32_arm_size_stubs() and
3310 elf32_arm_write_section(). */
3311 struct a8_erratum_fix *a8_erratum_fixes;
3312 unsigned int num_a8_erratum_fixes;
3313
906e58ca
NC		 3314 /* An arbitrary input BFD chosen to hold the glue sections. */
3315 bfd * bfd_of_glue_owner;
ba96a88f 3316
906e58ca
NC		 3317 /* Nonzero to output a BE8 image. */
3318 int byteswap_code;
e489d0ae 3319
906e58ca
NC		 3320 /* Zero if R_ARM_TARGET1 means R_ARM_ABS32.
3321 Nonzero if R_ARM_TARGET1 means R_ARM_REL32. */
3322 int target1_is_rel;
9c504268 3323
906e58ca
NC		 3324 /* The relocation to use for R_ARM_TARGET2 relocations. */
3325 int target2_reloc;
eb043451 3326
906e58ca
NC		 3327 /* 0 = Ignore R_ARM_V4BX.
3328 1 = Convert BX to MOV PC.
3329 2 = Generate v4 interworing stubs. */
3330 int fix_v4bx;
319850b4 3331
48229727
JB		 3332 /* Whether we should fix the Cortex-A8 Thumb-2 branch/TLB erratum. */
3333 int fix_cortex_a8;
3334
2de70689
MGD		 3335 /* Whether we should fix the ARM1176 BLX immediate issue. */
3336 int fix_arm1176;
3337
906e58ca
NC		 3338 /* Nonzero if the ARM/Thumb BLX instructions are available for use. */
3339 int use_blx;
33bfe774 3340
906e58ca
NC		 3341 /* What sort of code sequences we should look for which may trigger the
3342 VFP11 denorm erratum. */
3343 bfd_arm_vfp11_fix vfp11_fix;
c7b8f16e 3344
906e58ca
NC		 3345 /* Global counter for the number of fixes we have emitted. */
3346 int num_vfp11_fixes;
c7b8f16e 3347
a504d23a
LA		 3348 /* What sort of code sequences we should look for which may trigger the
3349 STM32L4XX erratum. */
3350 bfd_arm_stm32l4xx_fix stm32l4xx_fix;
3351
3352 /* Global counter for the number of fixes we have emitted. */
3353 int num_stm32l4xx_fixes;
3354
906e58ca
NC		 3355 /* Nonzero to force PIC branch veneers. */
3356 int pic_veneer;
27e55c4d 3357
906e58ca
NC		 3358 /* The number of bytes in the initial entry in the PLT. */
3359 bfd_size_type plt_header_size;
e5a52504 3360
906e58ca
NC		 3361 /* The number of bytes in the subsequent PLT etries. */
3362 bfd_size_type plt_entry_size;
e5a52504 3363
906e58ca
NC		 3364 /* True if the target system is VxWorks. */
3365 int vxworks_p;
00a97672 3366
906e58ca
NC		 3367 /* True if the target system is Symbian OS. */
3368 int symbian_p;
e5a52504 3369
b38cadfb
NC		 3370 /* True if the target system is Native Client. */
3371 int nacl_p;
3372
906e58ca 3373 /* True if the target uses REL relocations. */
f3185997 3374 bfd_boolean use_rel;
4e7fd91e 3375
54ddd295
TP		 3376 /* Nonzero if import library must be a secure gateway import library
3377 as per ARMv8-M Security Extensions. */
3378 int cmse_implib;
3379
0955507f
TP		 3380 /* The import library whose symbols' address must remain stable in
3381 the import library generated. */
3382 bfd *in_implib_bfd;
3383
0855e32b
NS		 3384 /* The index of the next unused R_ARM_TLS_DESC slot in .rel.plt. */
3385 bfd_vma next_tls_desc_index;
3386
3387 /* How many R_ARM_TLS_DESC relocations were generated so far. */
3388 bfd_vma num_tls_desc;
3389
906e58ca
NC		 3390 /* The (unloaded but important) VxWorks .rela.plt.unloaded section. */
3391 asection *srelplt2;
00a97672 3392
0855e32b
NS		 3393 /* The offset into splt of the PLT entry for the TLS descriptor
3394 resolver. Special values are 0, if not necessary (or not found
3395 to be necessary yet), and -1 if needed but not determined
3396 yet. */
3397 bfd_vma dt_tlsdesc_plt;
3398
3399 /* The offset into sgot of the GOT entry used by the PLT entry
3400 above. */
b38cadfb 3401 bfd_vma dt_tlsdesc_got;
0855e32b
NS		 3402
3403 /* Offset in .plt section of tls_arm_trampoline. */
3404 bfd_vma tls_trampoline;
3405
5c5a4843 3406 /* Data for R_ARM_TLS_LDM32/R_ARM_TLS_LDM32_FDPIC relocations. */
906e58ca
NC		 3407 union
3408 {
3409 bfd_signed_vma refcount;
3410 bfd_vma offset;
3411 } tls_ldm_got;
b7693d02 3412
87d72d41
AM		 3413 /* Small local sym cache. */
3414 struct sym_cache sym_cache;
906e58ca
NC		 3415
3416 /* For convenience in allocate_dynrelocs. */
3417 bfd * obfd;
3418
0855e32b
NS		 3419 /* The amount of space used by the reserved portion of the sgotplt
3420 section, plus whatever space is used by the jump slots. */
3421 bfd_vma sgotplt_jump_table_size;
3422
906e58ca
NC		 3423 /* The stub hash table. */
3424 struct bfd_hash_table stub_hash_table;
3425
3426 /* Linker stub bfd. */
3427 bfd *stub_bfd;
3428
3429 /* Linker call-backs. */
6bde4c52
TP		 3430 asection * (*add_stub_section) (const char *, asection *, asection *,
3431 unsigned int);
906e58ca
NC		 3432 void (*layout_sections_again) (void);
3433
3434 /* Array to keep track of which stub sections have been created, and
3435 information on stub grouping. */
21d799b5 3436 struct map_stub *stub_group;
906e58ca 3437
4ba2ef8f
TP		 3438 /* Input stub section holding secure gateway veneers. */
3439 asection *cmse_stub_sec;
3440
0955507f
TP		 3441 /* Offset in cmse_stub_sec where new SG veneers (not in input import library)
3442 start to be allocated. */
3443 bfd_vma new_cmse_stub_offset;
3444
fe33d2fa 3445 /* Number of elements in stub_group. */
7292b3ac 3446 unsigned int top_id;
fe33d2fa 3447
906e58ca
NC		 3448 /* Assorted information used by elf32_arm_size_stubs. */
3449 unsigned int bfd_count;
7292b3ac 3450 unsigned int top_index;
906e58ca 3451 asection **input_list;
617a5ada
CL		 3452
3453 /* True if the target system uses FDPIC. */
3454 int fdpic_p;
e8b09b87
CL		 3455
3456 /* Fixup section. Used for FDPIC. */
3457 asection *srofixup;
906e58ca 3458};
252b5132 3459
e8b09b87
CL		 3460/* Add an FDPIC read-only fixup. */
3461static void
3462arm_elf_add_rofixup (bfd *output_bfd, asection *srofixup, bfd_vma offset)
3463{
3464 bfd_vma fixup_offset;
3465
3466 fixup_offset = srofixup->reloc_count++ * 4;
3467 BFD_ASSERT (fixup_offset < srofixup->size);
3468 bfd_put_32 (output_bfd, offset, srofixup->contents + fixup_offset);
3469}
3470
a504d23a
LA		 3471static inline int
3472ctz (unsigned int mask)
3473{
3474#if GCC_VERSION >= 3004
3475 return __builtin_ctz (mask);
3476#else
3477 unsigned int i;
3478
3479 for (i = 0; i < 8 * sizeof (mask); i++)
3480 {
3481 if (mask & 0x1)
3482 break;
3483 mask = (mask >> 1);
3484 }
3485 return i;
3486#endif
3487}
3488
3489static inline int
b25e998d 3490elf32_arm_popcount (unsigned int mask)
a504d23a
LA		 3491{
3492#if GCC_VERSION >= 3004
3493 return __builtin_popcount (mask);
3494#else
b25e998d
CG		 3495 unsigned int i;
3496 int sum = 0;
a504d23a
LA		 3497
3498 for (i = 0; i < 8 * sizeof (mask); i++)
3499 {
3500 if (mask & 0x1)
3501 sum++;
3502 mask = (mask >> 1);
3503 }
3504 return sum;
3505#endif
3506}
3507
e8b09b87
CL		 3508static void elf32_arm_add_dynreloc (bfd *output_bfd, struct bfd_link_info *info,
3509 asection *sreloc, Elf_Internal_Rela *rel);
3510
3511static void
3512arm_elf_fill_funcdesc(bfd *output_bfd,
3513 struct bfd_link_info *info,
3514 int *funcdesc_offset,
3515 int dynindx,
3516 int offset,
3517 bfd_vma addr,
3518 bfd_vma dynreloc_value,
3519 bfd_vma seg)
3520{
3521 if ((*funcdesc_offset & 1) == 0)
3522 {
3523 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (info);
3524 asection *sgot = globals->root.sgot;
3525
3526 if (bfd_link_pic(info))
3527 {
3528 asection *srelgot = globals->root.srelgot;
3529 Elf_Internal_Rela outrel;
3530
3531 outrel.r_info = ELF32_R_INFO (dynindx, R_ARM_FUNCDESC_VALUE);
3532 outrel.r_offset = sgot->output_section->vma + sgot->output_offset + offset;
3533 outrel.r_addend = 0;
3534
3535 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
3536 bfd_put_32 (output_bfd, addr, sgot->contents + offset);
3537 bfd_put_32 (output_bfd, seg, sgot->contents + offset + 4);
3538 }
3539 else
3540 {
3541 struct elf_link_hash_entry *hgot = globals->root.hgot;
3542 bfd_vma got_value = hgot->root.u.def.value
3543 + hgot->root.u.def.section->output_section->vma
3544 + hgot->root.u.def.section->output_offset;
3545
3546 arm_elf_add_rofixup(output_bfd, globals->srofixup,
3547 sgot->output_section->vma + sgot->output_offset
3548 + offset);
3549 arm_elf_add_rofixup(output_bfd, globals->srofixup,
3550 sgot->output_section->vma + sgot->output_offset
3551 + offset + 4);
3552 bfd_put_32 (output_bfd, dynreloc_value, sgot->contents + offset);
3553 bfd_put_32 (output_bfd, got_value, sgot->contents + offset + 4);
3554 }
3555 *funcdesc_offset |= 1;
3556 }
3557}
3558
780a67af
NC		 3559/* Create an entry in an ARM ELF linker hash table. */
3560
3561static struct bfd_hash_entry *
57e8b36a 3562elf32_arm_link_hash_newfunc (struct bfd_hash_entry * entry,
99059e56
RM		 3563 struct bfd_hash_table * table,
3564 const char * string)
780a67af
NC		 3565{
3566 struct elf32_arm_link_hash_entry * ret =
3567 (struct elf32_arm_link_hash_entry *) entry;
3568
3569 /* Allocate the structure if it has not already been allocated by a
3570 subclass. */
906e58ca 3571 if (ret == NULL)
21d799b5 3572 ret = (struct elf32_arm_link_hash_entry *)
99059e56 3573 bfd_hash_allocate (table, sizeof (struct elf32_arm_link_hash_entry));
57e8b36a 3574 if (ret == NULL)
780a67af
NC		 3575 return (struct bfd_hash_entry *) ret;
3576
3577 /* Call the allocation method of the superclass. */
3578 ret = ((struct elf32_arm_link_hash_entry *)
3579 _bfd_elf_link_hash_newfunc ((struct bfd_hash_entry *) ret,
3580 table, string));
57e8b36a 3581 if (ret != NULL)
b7693d02 3582 {
0bdcacaf 3583 ret->dyn_relocs = NULL;
ba93b8ac 3584 ret->tls_type = GOT_UNKNOWN;
0855e32b 3585 ret->tlsdesc_got = (bfd_vma) -1;
34e77a92
RS		 3586 ret->plt.thumb_refcount = 0;
3587 ret->plt.maybe_thumb_refcount = 0;
3588 ret->plt.noncall_refcount = 0;
3589 ret->plt.got_offset = -1;
3590 ret->is_iplt = FALSE;
a4fd1a8e 3591 ret->export_glue = NULL;
906e58ca
NC		 3592
3593 ret->stub_cache = NULL;
e8b09b87
CL		 3594
3595 ret->fdpic_cnts.gotofffuncdesc_cnt = 0;
3596 ret->fdpic_cnts.gotfuncdesc_cnt = 0;
3597 ret->fdpic_cnts.funcdesc_cnt = 0;
3598 ret->fdpic_cnts.funcdesc_offset = -1;
3599 ret->fdpic_cnts.gotfuncdesc_offset = -1;
b7693d02 3600 }
780a67af
NC		 3601
3602 return (struct bfd_hash_entry *) ret;
3603}
3604
34e77a92
RS		 3605/* Ensure that we have allocated bookkeeping structures for ABFD's local
3606 symbols. */
3607
3608static bfd_boolean
3609elf32_arm_allocate_local_sym_info (bfd *abfd)
3610{
3611 if (elf_local_got_refcounts (abfd) == NULL)
3612 {
3613 bfd_size_type num_syms;
3614 bfd_size_type size;
3615 char *data;
3616
3617 num_syms = elf_tdata (abfd)->symtab_hdr.sh_info;
3618 size = num_syms * (sizeof (bfd_signed_vma)
3619 + sizeof (struct arm_local_iplt_info *)
3620 + sizeof (bfd_vma)
e8b09b87
CL		 3621 + sizeof (char)
3622 + sizeof (struct fdpic_local));
34e77a92
RS		 3623 data = bfd_zalloc (abfd, size);
3624 if (data == NULL)
3625 return FALSE;
3626
e8b09b87
CL		 3627 elf32_arm_local_fdpic_cnts (abfd) = (struct fdpic_local *) data;
3628 data += num_syms * sizeof (struct fdpic_local);
3629
34e77a92
RS		 3630 elf_local_got_refcounts (abfd) = (bfd_signed_vma *) data;
3631 data += num_syms * sizeof (bfd_signed_vma);
3632
3633 elf32_arm_local_iplt (abfd) = (struct arm_local_iplt_info **) data;
3634 data += num_syms * sizeof (struct arm_local_iplt_info *);
3635
3636 elf32_arm_local_tlsdesc_gotent (abfd) = (bfd_vma *) data;
3637 data += num_syms * sizeof (bfd_vma);
3638
3639 elf32_arm_local_got_tls_type (abfd) = data;
3640 }
3641 return TRUE;
3642}
3643
3644/* Return the .iplt information for local symbol R_SYMNDX, which belongs
3645 to input bfd ABFD. Create the information if it doesn't already exist.
3646 Return null if an allocation fails. */
3647
3648static struct arm_local_iplt_info *
3649elf32_arm_create_local_iplt (bfd *abfd, unsigned long r_symndx)
3650{
3651 struct arm_local_iplt_info **ptr;
3652
3653 if (!elf32_arm_allocate_local_sym_info (abfd))
3654 return NULL;
3655
3656 BFD_ASSERT (r_symndx < elf_tdata (abfd)->symtab_hdr.sh_info);
3657 ptr = &elf32_arm_local_iplt (abfd)[r_symndx];
3658 if (*ptr == NULL)
3659 *ptr = bfd_zalloc (abfd, sizeof (**ptr));
3660 return *ptr;
3661}
3662
3663/* Try to obtain PLT information for the symbol with index R_SYMNDX
3664 in ABFD's symbol table. If the symbol is global, H points to its
3665 hash table entry, otherwise H is null.
3666
3667 Return true if the symbol does have PLT information. When returning
3668 true, point *ROOT_PLT at the target-independent reference count/offset
3669 union and *ARM_PLT at the ARM-specific information. */
3670
3671static bfd_boolean
4ba2ef8f
TP		 3672elf32_arm_get_plt_info (bfd *abfd, struct elf32_arm_link_hash_table *globals,
3673 struct elf32_arm_link_hash_entry *h,
34e77a92
RS		 3674 unsigned long r_symndx, union gotplt_union **root_plt,
3675 struct arm_plt_info **arm_plt)
3676{
3677 struct arm_local_iplt_info *local_iplt;
3678
4ba2ef8f
TP		 3679 if (globals->root.splt == NULL && globals->root.iplt == NULL)
3680 return FALSE;
3681
34e77a92
RS		 3682 if (h != NULL)
3683 {
3684 *root_plt = &h->root.plt;
3685 *arm_plt = &h->plt;
3686 return TRUE;
3687 }
3688
3689 if (elf32_arm_local_iplt (abfd) == NULL)
3690 return FALSE;
3691
3692 local_iplt = elf32_arm_local_iplt (abfd)[r_symndx];
3693 if (local_iplt == NULL)
3694 return FALSE;
3695
3696 *root_plt = &local_iplt->root;
3697 *arm_plt = &local_iplt->arm;
3698 return TRUE;
3699}
3700
59029f57
CL		 3701static bfd_boolean using_thumb_only (struct elf32_arm_link_hash_table *globals);
3702
34e77a92
RS		 3703/* Return true if the PLT described by ARM_PLT requires a Thumb stub
3704 before it. */
3705
3706static bfd_boolean
3707elf32_arm_plt_needs_thumb_stub_p (struct bfd_link_info *info,
3708 struct arm_plt_info *arm_plt)
3709{
3710 struct elf32_arm_link_hash_table *htab;
3711
3712 htab = elf32_arm_hash_table (info);
59029f57
CL		 3713
3714 return (!using_thumb_only(htab) && (arm_plt->thumb_refcount != 0
3715 || (!htab->use_blx && arm_plt->maybe_thumb_refcount != 0)));
34e77a92
RS		 3716}
3717
3718/* Return a pointer to the head of the dynamic reloc list that should
3719 be used for local symbol ISYM, which is symbol number R_SYMNDX in
3720 ABFD's symbol table. Return null if an error occurs. */
3721
3722static struct elf_dyn_relocs **
3723elf32_arm_get_local_dynreloc_list (bfd *abfd, unsigned long r_symndx,
3724 Elf_Internal_Sym *isym)
3725{
3726 if (ELF32_ST_TYPE (isym->st_info) == STT_GNU_IFUNC)
3727 {
3728 struct arm_local_iplt_info *local_iplt;
3729
3730 local_iplt = elf32_arm_create_local_iplt (abfd, r_symndx);
3731 if (local_iplt == NULL)
3732 return NULL;
3733 return &local_iplt->dyn_relocs;
3734 }
3735 else
3736 {
3737 /* Track dynamic relocs needed for local syms too.
3738 We really need local syms available to do this
3739 easily. Oh well. */
3740 asection *s;
3741 void *vpp;
3742
3743 s = bfd_section_from_elf_index (abfd, isym->st_shndx);
3744 if (s == NULL)
3745 abort ();
3746
3747 vpp = &elf_section_data (s)->local_dynrel;
3748 return (struct elf_dyn_relocs **) vpp;
3749 }
3750}
3751
906e58ca
NC		 3752/* Initialize an entry in the stub hash table. */
3753
3754static struct bfd_hash_entry *
3755stub_hash_newfunc (struct bfd_hash_entry *entry,
3756 struct bfd_hash_table *table,
3757 const char *string)
3758{
3759 /* Allocate the structure if it has not already been allocated by a
3760 subclass. */
3761 if (entry == NULL)
3762 {
21d799b5 3763 entry = (struct bfd_hash_entry *)
99059e56 3764 bfd_hash_allocate (table, sizeof (struct elf32_arm_stub_hash_entry));
906e58ca
NC		 3765 if (entry == NULL)
3766 return entry;
3767 }
3768
3769 /* Call the allocation method of the superclass. */
3770 entry = bfd_hash_newfunc (entry, table, string);
3771 if (entry != NULL)
3772 {
3773 struct elf32_arm_stub_hash_entry *eh;
3774
3775 /* Initialize the local fields. */
3776 eh = (struct elf32_arm_stub_hash_entry *) entry;
3777 eh->stub_sec = NULL;
0955507f 3778 eh->stub_offset = (bfd_vma) -1;
8d9d9490 3779 eh->source_value = 0;
906e58ca
NC		 3780 eh->target_value = 0;
3781 eh->target_section = NULL;
cedfb179 3782 eh->orig_insn = 0;
906e58ca 3783 eh->stub_type = arm_stub_none;
461a49ca
DJ		 3784 eh->stub_size = 0;
3785 eh->stub_template = NULL;
0955507f 3786 eh->stub_template_size = -1;
906e58ca
NC		 3787 eh->h = NULL;
3788 eh->id_sec = NULL;
d8d2f433 3789 eh->output_name = NULL;
906e58ca
NC		 3790 }
3791
3792 return entry;
3793}
3794
00a97672 3795/* Create .got, .gotplt, and .rel(a).got sections in DYNOBJ, and set up
5e681ec4
PB		 3796 shortcuts to them in our hash table. */
3797
3798static bfd_boolean
57e8b36a 3799create_got_section (bfd *dynobj, struct bfd_link_info *info)
5e681ec4
PB		 3800{
3801 struct elf32_arm_link_hash_table *htab;
3802
e5a52504 3803 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 3804 if (htab == NULL)
3805 return FALSE;
3806
e5a52504
MM		 3807 /* BPABI objects never have a GOT, or associated sections. */
3808 if (htab->symbian_p)
3809 return TRUE;
3810
5e681ec4
PB		 3811 if (! _bfd_elf_create_got_section (dynobj, info))
3812 return FALSE;
3813
e8b09b87
CL		 3814 /* Also create .rofixup. */
3815 if (htab->fdpic_p)
3816 {
3817 htab->srofixup = bfd_make_section_with_flags (dynobj, ".rofixup",
3818 (SEC_ALLOC | SEC_LOAD | SEC_HAS_CONTENTS
3819 | SEC_IN_MEMORY | SEC_LINKER_CREATED | SEC_READONLY));
3820 if (htab->srofixup == NULL || ! bfd_set_section_alignment (dynobj, htab->srofixup, 2))
3821 return FALSE;
3822 }
3823
5e681ec4
PB		 3824 return TRUE;
3825}
3826
34e77a92
RS		 3827/* Create the .iplt, .rel(a).iplt and .igot.plt sections. */
3828
3829static bfd_boolean
3830create_ifunc_sections (struct bfd_link_info *info)
3831{
3832 struct elf32_arm_link_hash_table *htab;
3833 const struct elf_backend_data *bed;
3834 bfd *dynobj;
3835 asection *s;
3836 flagword flags;
b38cadfb 3837
34e77a92
RS		 3838 htab = elf32_arm_hash_table (info);
3839 dynobj = htab->root.dynobj;
3840 bed = get_elf_backend_data (dynobj);
3841 flags = bed->dynamic_sec_flags;
3842
3843 if (htab->root.iplt == NULL)
3844 {
3d4d4302
AM		 3845 s = bfd_make_section_anyway_with_flags (dynobj, ".iplt",
3846 flags | SEC_READONLY | SEC_CODE);
34e77a92 3847 if (s == NULL
a0f49396 3848 || !bfd_set_section_alignment (dynobj, s, bed->plt_alignment))
34e77a92
RS		 3849 return FALSE;
3850 htab->root.iplt = s;
3851 }
3852
3853 if (htab->root.irelplt == NULL)
3854 {
3d4d4302
AM		 3855 s = bfd_make_section_anyway_with_flags (dynobj,
3856 RELOC_SECTION (htab, ".iplt"),
3857 flags | SEC_READONLY);
34e77a92 3858 if (s == NULL
a0f49396 3859 || !bfd_set_section_alignment (dynobj, s, bed->s->log_file_align))
34e77a92
RS		 3860 return FALSE;
3861 htab->root.irelplt = s;
3862 }
3863
3864 if (htab->root.igotplt == NULL)
3865 {
3d4d4302 3866 s = bfd_make_section_anyway_with_flags (dynobj, ".igot.plt", flags);
34e77a92
RS		 3867 if (s == NULL
3868 || !bfd_set_section_alignment (dynobj, s, bed->s->log_file_align))
3869 return FALSE;
3870 htab->root.igotplt = s;
3871 }
3872 return TRUE;
3873}
3874
eed94f8f
NC		 3875/* Determine if we're dealing with a Thumb only architecture. */
3876
3877static bfd_boolean
3878using_thumb_only (struct elf32_arm_link_hash_table *globals)
3879{
2fd158eb
TP		 3880 int arch;
3881 int profile = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC,
3882 Tag_CPU_arch_profile);
eed94f8f 3883
2fd158eb
TP		 3884 if (profile)
3885 return profile == 'M';
eed94f8f 3886
2fd158eb 3887 arch = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC, Tag_CPU_arch);
eed94f8f 3888
60a019a0 3889 /* Force return logic to be reviewed for each new architecture. */
031254f2 3890 BFD_ASSERT (arch <= TAG_CPU_ARCH_V8_1M_MAIN);
60a019a0 3891
2fd158eb
TP		 3892 if (arch == TAG_CPU_ARCH_V6_M
3893 || arch == TAG_CPU_ARCH_V6S_M
3894 || arch == TAG_CPU_ARCH_V7E_M
3895 || arch == TAG_CPU_ARCH_V8M_BASE
031254f2
AV		 3896 || arch == TAG_CPU_ARCH_V8M_MAIN
3897 || arch == TAG_CPU_ARCH_V8_1M_MAIN)
2fd158eb 3898 return TRUE;
eed94f8f 3899
2fd158eb 3900 return FALSE;
eed94f8f
NC		 3901}
3902
3903/* Determine if we're dealing with a Thumb-2 object. */
3904
3905static bfd_boolean
3906using_thumb2 (struct elf32_arm_link_hash_table *globals)
3907{
60a019a0
TP		 3908 int arch;
3909 int thumb_isa = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC,
3910 Tag_THUMB_ISA_use);
3911
3912 if (thumb_isa)
3913 return thumb_isa == 2;
3914
3915 arch = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC, Tag_CPU_arch);
3916
3917 /* Force return logic to be reviewed for each new architecture. */
031254f2 3918 BFD_ASSERT (arch <= TAG_CPU_ARCH_V8_1M_MAIN);
60a019a0
TP		 3919
3920 return (arch == TAG_CPU_ARCH_V6T2
3921 || arch == TAG_CPU_ARCH_V7
3922 || arch == TAG_CPU_ARCH_V7E_M
3923 || arch == TAG_CPU_ARCH_V8
bff0500d 3924 || arch == TAG_CPU_ARCH_V8R
031254f2
AV		 3925 || arch == TAG_CPU_ARCH_V8M_MAIN
3926 || arch == TAG_CPU_ARCH_V8_1M_MAIN);
eed94f8f
NC		 3927}
3928
5e866f5a
TP		 3929/* Determine whether Thumb-2 BL instruction is available. */
3930
3931static bfd_boolean
3932using_thumb2_bl (struct elf32_arm_link_hash_table *globals)
3933{
3934 int arch =
3935 bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC, Tag_CPU_arch);
3936
3937 /* Force return logic to be reviewed for each new architecture. */
031254f2 3938 BFD_ASSERT (arch <= TAG_CPU_ARCH_V8_1M_MAIN);
5e866f5a
TP		 3939
3940 /* Architecture was introduced after ARMv6T2 (eg. ARMv6-M). */
3941 return (arch == TAG_CPU_ARCH_V6T2
3942 || arch >= TAG_CPU_ARCH_V7);
3943}
3944
00a97672
RS		 3945/* Create .plt, .rel(a).plt, .got, .got.plt, .rel(a).got, .dynbss, and
3946 .rel(a).bss sections in DYNOBJ, and set up shortcuts to them in our
5e681ec4
PB		 3947 hash table. */
3948
3949static bfd_boolean
57e8b36a 3950elf32_arm_create_dynamic_sections (bfd *dynobj, struct bfd_link_info *info)
5e681ec4
PB		 3951{
3952 struct elf32_arm_link_hash_table *htab;
3953
3954 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 3955 if (htab == NULL)
3956 return FALSE;
3957
362d30a1 3958 if (!htab->root.sgot && !create_got_section (dynobj, info))
5e681ec4
PB		 3959 return FALSE;
3960
3961 if (!_bfd_elf_create_dynamic_sections (dynobj, info))
3962 return FALSE;
3963
00a97672
RS		 3964 if (htab->vxworks_p)
3965 {
3966 if (!elf_vxworks_create_dynamic_sections (dynobj, info, &htab->srelplt2))
3967 return FALSE;
3968
0e1862bb 3969 if (bfd_link_pic (info))
00a97672
RS		 3970 {
3971 htab->plt_header_size = 0;
3972 htab->plt_entry_size
3973 = 4 * ARRAY_SIZE (elf32_arm_vxworks_shared_plt_entry);
3974 }
3975 else
3976 {
3977 htab->plt_header_size
3978 = 4 * ARRAY_SIZE (elf32_arm_vxworks_exec_plt0_entry);
3979 htab->plt_entry_size
3980 = 4 * ARRAY_SIZE (elf32_arm_vxworks_exec_plt_entry);
3981 }
aebf9be7
NC		 3982
3983 if (elf_elfheader (dynobj))
3984 elf_elfheader (dynobj)->e_ident[EI_CLASS] = ELFCLASS32;
00a97672 3985 }
eed94f8f
NC		 3986 else
3987 {
3988 /* PR ld/16017
3989 Test for thumb only architectures. Note - we cannot just call
3990 using_thumb_only() as the attributes in the output bfd have not been
3991 initialised at this point, so instead we use the input bfd. */
3992 bfd * saved_obfd = htab->obfd;
3993
3994 htab->obfd = dynobj;
3995 if (using_thumb_only (htab))
3996 {
3997 htab->plt_header_size = 4 * ARRAY_SIZE (elf32_thumb2_plt0_entry);
3998 htab->plt_entry_size = 4 * ARRAY_SIZE (elf32_thumb2_plt_entry);
3999 }
4000 htab->obfd = saved_obfd;
4001 }
5e681ec4 4002
7801f98f
CL		 4003 if (htab->fdpic_p) {
4004 htab->plt_header_size = 0;
4005 if (info->flags & DF_BIND_NOW)
4006 htab->plt_entry_size = 4 * (ARRAY_SIZE(elf32_arm_fdpic_plt_entry) - 5);
4007 else
4008 htab->plt_entry_size = 4 * ARRAY_SIZE(elf32_arm_fdpic_plt_entry);
4009 }
4010
362d30a1
RS		 4011 if (!htab->root.splt
4012 || !htab->root.srelplt
9d19e4fd
AM		 4013 || !htab->root.sdynbss
4014 || (!bfd_link_pic (info) && !htab->root.srelbss))
5e681ec4
PB		 4015 abort ();
4016
4017 return TRUE;
4018}
4019
906e58ca
NC		 4020/* Copy the extra info we tack onto an elf_link_hash_entry. */
4021
4022static void
4023elf32_arm_copy_indirect_symbol (struct bfd_link_info *info,
4024 struct elf_link_hash_entry *dir,
4025 struct elf_link_hash_entry *ind)
4026{
4027 struct elf32_arm_link_hash_entry *edir, *eind;
4028
4029 edir = (struct elf32_arm_link_hash_entry *) dir;
4030 eind = (struct elf32_arm_link_hash_entry *) ind;
4031
0bdcacaf 4032 if (eind->dyn_relocs != NULL)
906e58ca 4033 {
0bdcacaf 4034 if (edir->dyn_relocs != NULL)
906e58ca 4035 {
0bdcacaf
RS		 4036 struct elf_dyn_relocs **pp;
4037 struct elf_dyn_relocs *p;
906e58ca
NC		 4038
4039 /* Add reloc counts against the indirect sym to the direct sym
4040 list. Merge any entries against the same section. */
0bdcacaf 4041 for (pp = &eind->dyn_relocs; (p = *pp) != NULL; )
906e58ca 4042 {
0bdcacaf 4043 struct elf_dyn_relocs *q;
906e58ca 4044
0bdcacaf
RS		 4045 for (q = edir->dyn_relocs; q != NULL; q = q->next)
4046 if (q->sec == p->sec)
906e58ca
NC		 4047 {
4048 q->pc_count += p->pc_count;
4049 q->count += p->count;
4050 *pp = p->next;
4051 break;
4052 }
4053 if (q == NULL)
4054 pp = &p->next;
4055 }
0bdcacaf 4056 *pp = edir->dyn_relocs;
906e58ca
NC		 4057 }
4058
0bdcacaf
RS		 4059 edir->dyn_relocs = eind->dyn_relocs;
4060 eind->dyn_relocs = NULL;
906e58ca
NC		 4061 }
4062
4063 if (ind->root.type == bfd_link_hash_indirect)
4064 {
4065 /* Copy over PLT info. */
34e77a92
RS		 4066 edir->plt.thumb_refcount += eind->plt.thumb_refcount;
4067 eind->plt.thumb_refcount = 0;
4068 edir->plt.maybe_thumb_refcount += eind->plt.maybe_thumb_refcount;
4069 eind->plt.maybe_thumb_refcount = 0;
4070 edir->plt.noncall_refcount += eind->plt.noncall_refcount;
4071 eind->plt.noncall_refcount = 0;
4072
e8b09b87
CL		 4073 /* Copy FDPIC counters. */
4074 edir->fdpic_cnts.gotofffuncdesc_cnt += eind->fdpic_cnts.gotofffuncdesc_cnt;
4075 edir->fdpic_cnts.gotfuncdesc_cnt += eind->fdpic_cnts.gotfuncdesc_cnt;
4076 edir->fdpic_cnts.funcdesc_cnt += eind->fdpic_cnts.funcdesc_cnt;
4077
34e77a92
RS		 4078 /* We should only allocate a function to .iplt once the final
4079 symbol information is known. */
4080 BFD_ASSERT (!eind->is_iplt);
906e58ca
NC		 4081
4082 if (dir->got.refcount <= 0)
4083 {
4084 edir->tls_type = eind->tls_type;
4085 eind->tls_type = GOT_UNKNOWN;
4086 }
4087 }
4088
4089 _bfd_elf_link_hash_copy_indirect (info, dir, ind);
4090}
4091
68faa637
AM		 4092/* Destroy an ARM elf linker hash table. */
4093
4094static void
d495ab0d 4095elf32_arm_link_hash_table_free (bfd *obfd)
68faa637
AM		 4096{
4097 struct elf32_arm_link_hash_table *ret
d495ab0d 4098 = (struct elf32_arm_link_hash_table *) obfd->link.hash;
68faa637
AM		 4099
4100 bfd_hash_table_free (&ret->stub_hash_table);
d495ab0d 4101 _bfd_elf_link_hash_table_free (obfd);
68faa637
AM		 4102}
4103
906e58ca
NC		 4104/* Create an ARM elf linker hash table. */
4105
4106static struct bfd_link_hash_table *
4107elf32_arm_link_hash_table_create (bfd *abfd)
4108{
4109 struct elf32_arm_link_hash_table *ret;
4110 bfd_size_type amt = sizeof (struct elf32_arm_link_hash_table);
4111
7bf52ea2 4112 ret = (struct elf32_arm_link_hash_table *) bfd_zmalloc (amt);
906e58ca
NC		 4113 if (ret == NULL)
4114 return NULL;
4115
4116 if (!_bfd_elf_link_hash_table_init (& ret->root, abfd,
4117 elf32_arm_link_hash_newfunc,
4dfe6ac6
NC		 4118 sizeof (struct elf32_arm_link_hash_entry),
4119 ARM_ELF_DATA))
906e58ca
NC		 4120 {
4121 free (ret);
4122 return NULL;
4123 }
4124
906e58ca 4125 ret->vfp11_fix = BFD_ARM_VFP11_FIX_NONE;
a504d23a 4126 ret->stm32l4xx_fix = BFD_ARM_STM32L4XX_FIX_NONE;
906e58ca
NC		 4127#ifdef FOUR_WORD_PLT
4128 ret->plt_header_size = 16;
4129 ret->plt_entry_size = 16;
4130#else
4131 ret->plt_header_size = 20;
1db37fe6 4132 ret->plt_entry_size = elf32_arm_use_long_plt_entry ? 16 : 12;
906e58ca 4133#endif
f3185997 4134 ret->use_rel = TRUE;
906e58ca 4135 ret->obfd = abfd;
617a5ada 4136 ret->fdpic_p = 0;
906e58ca
NC		 4137
4138 if (!bfd_hash_table_init (&ret->stub_hash_table, stub_hash_newfunc,
4139 sizeof (struct elf32_arm_stub_hash_entry)))
4140 {
d495ab0d 4141 _bfd_elf_link_hash_table_free (abfd);
906e58ca
NC		 4142 return NULL;
4143 }
d495ab0d 4144 ret->root.root.hash_table_free = elf32_arm_link_hash_table_free;
906e58ca
NC		 4145
4146 return &ret->root.root;
4147}
4148
cd1dac3d
DG		 4149/* Determine what kind of NOPs are available. */
4150
4151static bfd_boolean
4152arch_has_arm_nop (struct elf32_arm_link_hash_table *globals)
4153{
4154 const int arch = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC,
4155 Tag_CPU_arch);
cd1dac3d 4156
60a019a0 4157 /* Force return logic to be reviewed for each new architecture. */
031254f2 4158 BFD_ASSERT (arch <= TAG_CPU_ARCH_V8_1M_MAIN);
60a019a0
TP		 4159
4160 return (arch == TAG_CPU_ARCH_V6T2
4161 || arch == TAG_CPU_ARCH_V6K
4162 || arch == TAG_CPU_ARCH_V7
bff0500d
TP		 4163 || arch == TAG_CPU_ARCH_V8
4164 || arch == TAG_CPU_ARCH_V8R);
cd1dac3d
DG		 4165}
4166
f4ac8484
DJ		 4167static bfd_boolean
4168arm_stub_is_thumb (enum elf32_arm_stub_type stub_type)
4169{
4170 switch (stub_type)
4171 {
fea2b4d6 4172 case arm_stub_long_branch_thumb_only:
80c135e5 4173 case arm_stub_long_branch_thumb2_only:
d5a67c02 4174 case arm_stub_long_branch_thumb2_only_pure:
fea2b4d6
CL		 4175 case arm_stub_long_branch_v4t_thumb_arm:
4176 case arm_stub_short_branch_v4t_thumb_arm:
ebe24dd4 4177 case arm_stub_long_branch_v4t_thumb_arm_pic:
12352d3f 4178 case arm_stub_long_branch_v4t_thumb_tls_pic:
ebe24dd4 4179 case arm_stub_long_branch_thumb_only_pic:
4ba2ef8f 4180 case arm_stub_cmse_branch_thumb_only:
f4ac8484
DJ		 4181 return TRUE;
4182 case arm_stub_none:
4183 BFD_FAIL ();
4184 return FALSE;
4185 break;
4186 default:
4187 return FALSE;
4188 }
4189}
4190
906e58ca
NC		 4191/* Determine the type of stub needed, if any, for a call. */
4192
4193static enum elf32_arm_stub_type
4194arm_type_of_stub (struct bfd_link_info *info,
4195 asection *input_sec,
4196 const Elf_Internal_Rela *rel,
34e77a92 4197 unsigned char st_type,
35fc36a8 4198 enum arm_st_branch_type *actual_branch_type,
906e58ca 4199 struct elf32_arm_link_hash_entry *hash,
c820be07
NC		 4200 bfd_vma destination,
4201 asection *sym_sec,
4202 bfd *input_bfd,
4203 const char *name)
906e58ca
NC		 4204{
4205 bfd_vma location;
4206 bfd_signed_vma branch_offset;
4207 unsigned int r_type;
4208 struct elf32_arm_link_hash_table * globals;
5e866f5a 4209 bfd_boolean thumb2, thumb2_bl, thumb_only;
906e58ca 4210 enum elf32_arm_stub_type stub_type = arm_stub_none;
5fa9e92f 4211 int use_plt = 0;
35fc36a8 4212 enum arm_st_branch_type branch_type = *actual_branch_type;
34e77a92
RS		 4213 union gotplt_union *root_plt;
4214 struct arm_plt_info *arm_plt;
d5a67c02
AV		 4215 int arch;
4216 int thumb2_movw;
906e58ca 4217
35fc36a8 4218 if (branch_type == ST_BRANCH_LONG)
da5938a2
NC		 4219 return stub_type;
4220
906e58ca 4221 globals = elf32_arm_hash_table (info);
4dfe6ac6
NC		 4222 if (globals == NULL)
4223 return stub_type;
906e58ca
NC		 4224
4225 thumb_only = using_thumb_only (globals);
906e58ca 4226 thumb2 = using_thumb2 (globals);
5e866f5a 4227 thumb2_bl = using_thumb2_bl (globals);
906e58ca 4228
d5a67c02
AV		 4229 arch = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC, Tag_CPU_arch);
4230
4231 /* True for architectures that implement the thumb2 movw instruction. */
4232 thumb2_movw = thumb2 || (arch == TAG_CPU_ARCH_V8M_BASE);
4233
906e58ca
NC		 4234 /* Determine where the call point is. */
4235 location = (input_sec->output_offset
4236 + input_sec->output_section->vma
4237 + rel->r_offset);
4238
906e58ca
NC		 4239 r_type = ELF32_R_TYPE (rel->r_info);
4240
39f21624
NC		 4241 /* ST_BRANCH_TO_ARM is nonsense to thumb-only targets when we
4242 are considering a function call relocation. */
c5423981 4243 if (thumb_only && (r_type == R_ARM_THM_CALL || r_type == R_ARM_THM_JUMP24
07d6d2b8 4244 || r_type == R_ARM_THM_JUMP19)
39f21624
NC		 4245 && branch_type == ST_BRANCH_TO_ARM)
4246 branch_type = ST_BRANCH_TO_THUMB;
4247
34e77a92
RS		 4248 /* For TLS call relocs, it is the caller's responsibility to provide
4249 the address of the appropriate trampoline. */
4250 if (r_type != R_ARM_TLS_CALL
4251 && r_type != R_ARM_THM_TLS_CALL
4ba2ef8f
TP		 4252 && elf32_arm_get_plt_info (input_bfd, globals, hash,
4253 ELF32_R_SYM (rel->r_info), &root_plt,
4254 &arm_plt)
34e77a92 4255 && root_plt->offset != (bfd_vma) -1)
5fa9e92f 4256 {
34e77a92 4257 asection *splt;
fe33d2fa 4258
34e77a92
RS		 4259 if (hash == NULL || hash->is_iplt)
4260 splt = globals->root.iplt;
4261 else
4262 splt = globals->root.splt;
4263 if (splt != NULL)
b38cadfb 4264 {
34e77a92
RS		 4265 use_plt = 1;
4266
4267 /* Note when dealing with PLT entries: the main PLT stub is in
4268 ARM mode, so if the branch is in Thumb mode, another
4269 Thumb->ARM stub will be inserted later just before the ARM
2df2751d
CL		 4270 PLT stub. If a long branch stub is needed, we'll add a
4271 Thumb->Arm one and branch directly to the ARM PLT entry.
4272 Here, we have to check if a pre-PLT Thumb->ARM stub
4273 is needed and if it will be close enough. */
34e77a92
RS		 4274
4275 destination = (splt->output_section->vma
4276 + splt->output_offset
4277 + root_plt->offset);
4278 st_type = STT_FUNC;
2df2751d
CL		 4279
4280 /* Thumb branch/call to PLT: it can become a branch to ARM
4281 or to Thumb. We must perform the same checks and
4282 corrections as in elf32_arm_final_link_relocate. */
4283 if ((r_type == R_ARM_THM_CALL)
4284 || (r_type == R_ARM_THM_JUMP24))
4285 {
4286 if (globals->use_blx
4287 && r_type == R_ARM_THM_CALL
4288 && !thumb_only)
4289 {
4290 /* If the Thumb BLX instruction is available, convert
4291 the BL to a BLX instruction to call the ARM-mode
4292 PLT entry. */
4293 branch_type = ST_BRANCH_TO_ARM;
4294 }
4295 else
4296 {
4297 if (!thumb_only)
4298 /* Target the Thumb stub before the ARM PLT entry. */
4299 destination -= PLT_THUMB_STUB_SIZE;
4300 branch_type = ST_BRANCH_TO_THUMB;
4301 }
4302 }
4303 else
4304 {
4305 branch_type = ST_BRANCH_TO_ARM;
4306 }
34e77a92 4307 }
5fa9e92f 4308 }
34e77a92
RS		 4309 /* Calls to STT_GNU_IFUNC symbols should go through a PLT. */
4310 BFD_ASSERT (st_type != STT_GNU_IFUNC);
906e58ca 4311
fe33d2fa
CL		 4312 branch_offset = (bfd_signed_vma)(destination - location);
4313
0855e32b 4314 if (r_type == R_ARM_THM_CALL || r_type == R_ARM_THM_JUMP24
c5423981 4315 || r_type == R_ARM_THM_TLS_CALL || r_type == R_ARM_THM_JUMP19)
906e58ca 4316 {
5fa9e92f
CL		 4317 /* Handle cases where:
4318 - this call goes too far (different Thumb/Thumb2 max
99059e56 4319 distance)
155d87d7 4320 - it's a Thumb->Arm call and blx is not available, or it's a
99059e56
RM		 4321 Thumb->Arm branch (not bl). A stub is needed in this case,
4322 but only if this call is not through a PLT entry. Indeed,
695344c0 4323 PLT stubs handle mode switching already. */
5e866f5a 4324 if ((!thumb2_bl
906e58ca
NC		 4325 && (branch_offset > THM_MAX_FWD_BRANCH_OFFSET
4326 || (branch_offset < THM_MAX_BWD_BRANCH_OFFSET)))
5e866f5a 4327 || (thumb2_bl
906e58ca
NC		 4328 && (branch_offset > THM2_MAX_FWD_BRANCH_OFFSET
4329 || (branch_offset < THM2_MAX_BWD_BRANCH_OFFSET)))
c5423981
TG		 4330 || (thumb2
4331 && (branch_offset > THM2_MAX_FWD_COND_BRANCH_OFFSET
4332 || (branch_offset < THM2_MAX_BWD_COND_BRANCH_OFFSET))
4333 && (r_type == R_ARM_THM_JUMP19))
35fc36a8 4334 || (branch_type == ST_BRANCH_TO_ARM
0855e32b
NS		 4335 && (((r_type == R_ARM_THM_CALL
4336 || r_type == R_ARM_THM_TLS_CALL) && !globals->use_blx)
c5423981 4337 || (r_type == R_ARM_THM_JUMP24)
07d6d2b8 4338 || (r_type == R_ARM_THM_JUMP19))
5fa9e92f 4339 && !use_plt))
906e58ca 4340 {
2df2751d
CL		 4341 /* If we need to insert a Thumb-Thumb long branch stub to a
4342 PLT, use one that branches directly to the ARM PLT
4343 stub. If we pretended we'd use the pre-PLT Thumb->ARM
4344 stub, undo this now. */
695344c0
NC		 4345 if ((branch_type == ST_BRANCH_TO_THUMB) && use_plt && !thumb_only)
4346 {
4347 branch_type = ST_BRANCH_TO_ARM;
4348 branch_offset += PLT_THUMB_STUB_SIZE;
4349 }
2df2751d 4350
35fc36a8 4351 if (branch_type == ST_BRANCH_TO_THUMB)
906e58ca
NC		 4352 {
4353 /* Thumb to thumb. */
4354 if (!thumb_only)
4355 {
d5a67c02 4356 if (input_sec->flags & SEC_ELF_PURECODE)
10463f39 4357 _bfd_error_handler
871b3ab2 4358 (_("%pB(%pA): warning: long branch veneers used in"
10463f39
AM		 4359 " section with SHF_ARM_PURECODE section"
4360 " attribute is only supported for M-profile"
90b6238f 4361 " targets that implement the movw instruction"),
10463f39 4362 input_bfd, input_sec);
d5a67c02 4363
0e1862bb 4364 stub_type = (bfd_link_pic (info) | globals->pic_veneer)
c2b4a39d 4365 /* PIC stubs. */
155d87d7 4366 ? ((globals->use_blx
9553db3c 4367 && (r_type == R_ARM_THM_CALL))
155d87d7
CL		 4368 /* V5T and above. Stub starts with ARM code, so
4369 we must be able to switch mode before
4370 reaching it, which is only possible for 'bl'
4371 (ie R_ARM_THM_CALL relocation). */
cf3eccff 4372 ? arm_stub_long_branch_any_thumb_pic
ebe24dd4 4373 /* On V4T, use Thumb code only. */
d3626fb0 4374 : arm_stub_long_branch_v4t_thumb_thumb_pic)
c2b4a39d
CL		 4375
4376 /* non-PIC stubs. */
155d87d7 4377 : ((globals->use_blx
9553db3c 4378 && (r_type == R_ARM_THM_CALL))
c2b4a39d
CL		 4379 /* V5T and above. */
4380 ? arm_stub_long_branch_any_any
4381 /* V4T. */
d3626fb0 4382 : arm_stub_long_branch_v4t_thumb_thumb);
906e58ca
NC		 4383 }
4384 else
4385 {
d5a67c02
AV		 4386 if (thumb2_movw && (input_sec->flags & SEC_ELF_PURECODE))
4387 stub_type = arm_stub_long_branch_thumb2_only_pure;
4388 else
4389 {
4390 if (input_sec->flags & SEC_ELF_PURECODE)
10463f39 4391 _bfd_error_handler
871b3ab2 4392 (_("%pB(%pA): warning: long branch veneers used in"
10463f39
AM		 4393 " section with SHF_ARM_PURECODE section"
4394 " attribute is only supported for M-profile"
90b6238f 4395 " targets that implement the movw instruction"),
10463f39 4396 input_bfd, input_sec);
d5a67c02
AV		 4397
4398 stub_type = (bfd_link_pic (info) | globals->pic_veneer)
4399 /* PIC stub. */
4400 ? arm_stub_long_branch_thumb_only_pic
4401 /* non-PIC stub. */
4402 : (thumb2 ? arm_stub_long_branch_thumb2_only
4403 : arm_stub_long_branch_thumb_only);
4404 }
906e58ca
NC		 4405 }
4406 }
4407 else
4408 {
d5a67c02 4409 if (input_sec->flags & SEC_ELF_PURECODE)
10463f39 4410 _bfd_error_handler
871b3ab2 4411 (_("%pB(%pA): warning: long branch veneers used in"
10463f39
AM		 4412 " section with SHF_ARM_PURECODE section"
4413 " attribute is only supported" " for M-profile"
90b6238f 4414 " targets that implement the movw instruction"),
10463f39 4415 input_bfd, input_sec);
d5a67c02 4416
906e58ca 4417 /* Thumb to arm. */
c820be07
NC		 4418 if (sym_sec != NULL
4419 && sym_sec->owner != NULL
4420 && !INTERWORK_FLAG (sym_sec->owner))
4421 {
4eca0228 4422 _bfd_error_handler
90b6238f
AM		 4423 (_("%pB(%s): warning: interworking not enabled;"
4424 " first occurrence: %pB: %s call to %s"),
4425 sym_sec->owner, name, input_bfd, "Thumb", "ARM");
c820be07
NC		 4426 }
4427
0855e32b 4428 stub_type =
0e1862bb 4429 (bfd_link_pic (info) | globals->pic_veneer)
c2b4a39d 4430 /* PIC stubs. */
0855e32b 4431 ? (r_type == R_ARM_THM_TLS_CALL
6a631e86 4432 /* TLS PIC stubs. */
0855e32b
NS		 4433 ? (globals->use_blx ? arm_stub_long_branch_any_tls_pic
4434 : arm_stub_long_branch_v4t_thumb_tls_pic)
4435 : ((globals->use_blx && r_type == R_ARM_THM_CALL)
4436 /* V5T PIC and above. */
4437 ? arm_stub_long_branch_any_arm_pic
4438 /* V4T PIC stub. */
4439 : arm_stub_long_branch_v4t_thumb_arm_pic))
c2b4a39d
CL		 4440
4441 /* non-PIC stubs. */
0855e32b 4442 : ((globals->use_blx && r_type == R_ARM_THM_CALL)
c2b4a39d
CL		 4443 /* V5T and above. */
4444 ? arm_stub_long_branch_any_any
4445 /* V4T. */
4446 : arm_stub_long_branch_v4t_thumb_arm);
c820be07
NC		 4447
4448 /* Handle v4t short branches. */
fea2b4d6 4449 if ((stub_type == arm_stub_long_branch_v4t_thumb_arm)
c820be07
NC		 4450 && (branch_offset <= THM_MAX_FWD_BRANCH_OFFSET)
4451 && (branch_offset >= THM_MAX_BWD_BRANCH_OFFSET))
fea2b4d6 4452 stub_type = arm_stub_short_branch_v4t_thumb_arm;
906e58ca
NC		 4453 }
4454 }
4455 }
fe33d2fa
CL		 4456 else if (r_type == R_ARM_CALL
4457 || r_type == R_ARM_JUMP24
0855e32b
NS		 4458 || r_type == R_ARM_PLT32
4459 || r_type == R_ARM_TLS_CALL)
906e58ca 4460 {
d5a67c02 4461 if (input_sec->flags & SEC_ELF_PURECODE)
10463f39 4462 _bfd_error_handler
871b3ab2 4463 (_("%pB(%pA): warning: long branch veneers used in"
10463f39
AM		 4464 " section with SHF_ARM_PURECODE section"
4465 " attribute is only supported for M-profile"
90b6238f 4466 " targets that implement the movw instruction"),
10463f39 4467 input_bfd, input_sec);
35fc36a8 4468 if (branch_type == ST_BRANCH_TO_THUMB)
906e58ca
NC		 4469 {
4470 /* Arm to thumb. */
c820be07
NC		 4471
4472 if (sym_sec != NULL
4473 && sym_sec->owner != NULL
4474 && !INTERWORK_FLAG (sym_sec->owner))
4475 {
4eca0228 4476 _bfd_error_handler
90b6238f
AM		 4477 (_("%pB(%s): warning: interworking not enabled;"
4478 " first occurrence: %pB: %s call to %s"),
4479 sym_sec->owner, name, input_bfd, "ARM", "Thumb");
c820be07
NC		 4480 }
4481
4482 /* We have an extra 2-bytes reach because of
4483 the mode change (bit 24 (H) of BLX encoding). */
4116d8d7
PB		 4484 if (branch_offset > (ARM_MAX_FWD_BRANCH_OFFSET + 2)
4485 || (branch_offset < ARM_MAX_BWD_BRANCH_OFFSET)
0855e32b 4486 || (r_type == R_ARM_CALL && !globals->use_blx)
4116d8d7
PB		 4487 || (r_type == R_ARM_JUMP24)
4488 || (r_type == R_ARM_PLT32))
906e58ca 4489 {
0e1862bb 4490 stub_type = (bfd_link_pic (info) | globals->pic_veneer)
c2b4a39d 4491 /* PIC stubs. */
ebe24dd4
CL		 4492 ? ((globals->use_blx)
4493 /* V5T and above. */
4494 ? arm_stub_long_branch_any_thumb_pic
4495 /* V4T stub. */
4496 : arm_stub_long_branch_v4t_arm_thumb_pic)
4497
c2b4a39d
CL		 4498 /* non-PIC stubs. */
4499 : ((globals->use_blx)
4500 /* V5T and above. */
4501 ? arm_stub_long_branch_any_any
4502 /* V4T. */
4503 : arm_stub_long_branch_v4t_arm_thumb);
906e58ca
NC		 4504 }
4505 }
4506 else
4507 {
4508 /* Arm to arm. */
4509 if (branch_offset > ARM_MAX_FWD_BRANCH_OFFSET
4510 || (branch_offset < ARM_MAX_BWD_BRANCH_OFFSET))
4511 {
0855e32b 4512 stub_type =
0e1862bb 4513 (bfd_link_pic (info) | globals->pic_veneer)
c2b4a39d 4514 /* PIC stubs. */
0855e32b 4515 ? (r_type == R_ARM_TLS_CALL
6a631e86 4516 /* TLS PIC Stub. */
0855e32b 4517 ? arm_stub_long_branch_any_tls_pic
7a89b94e
NC		 4518 : (globals->nacl_p
4519 ? arm_stub_long_branch_arm_nacl_pic
4520 : arm_stub_long_branch_any_arm_pic))
c2b4a39d 4521 /* non-PIC stubs. */
7a89b94e
NC		 4522 : (globals->nacl_p
4523 ? arm_stub_long_branch_arm_nacl
4524 : arm_stub_long_branch_any_any);
906e58ca
NC		 4525 }
4526 }
4527 }
4528
fe33d2fa
CL		 4529 /* If a stub is needed, record the actual destination type. */
4530 if (stub_type != arm_stub_none)
35fc36a8 4531 *actual_branch_type = branch_type;
fe33d2fa 4532
906e58ca
NC		 4533 return stub_type;
4534}
4535
4536/* Build a name for an entry in the stub hash table. */
4537
4538static char *
4539elf32_arm_stub_name (const asection *input_section,
4540 const asection *sym_sec,
4541 const struct elf32_arm_link_hash_entry *hash,
fe33d2fa
CL		 4542 const Elf_Internal_Rela *rel,
4543 enum elf32_arm_stub_type stub_type)
906e58ca
NC		 4544{
4545 char *stub_name;
4546 bfd_size_type len;
4547
4548 if (hash)
4549 {
fe33d2fa 4550 len = 8 + 1 + strlen (hash->root.root.root.string) + 1 + 8 + 1 + 2 + 1;
21d799b5 4551 stub_name = (char *) bfd_malloc (len);
906e58ca 4552 if (stub_name != NULL)
fe33d2fa 4553 sprintf (stub_name, "%08x_%s+%x_%d",
906e58ca
NC		 4554 input_section->id & 0xffffffff,
4555 hash->root.root.root.string,
fe33d2fa
CL		 4556 (int) rel->r_addend & 0xffffffff,
4557 (int) stub_type);
906e58ca
NC		 4558 }
4559 else
4560 {
fe33d2fa 4561 len = 8 + 1 + 8 + 1 + 8 + 1 + 8 + 1 + 2 + 1;
21d799b5 4562 stub_name = (char *) bfd_malloc (len);
906e58ca 4563 if (stub_name != NULL)
fe33d2fa 4564 sprintf (stub_name, "%08x_%x:%x+%x_%d",
906e58ca
NC		 4565 input_section->id & 0xffffffff,
4566 sym_sec->id & 0xffffffff,
0855e32b
NS		 4567 ELF32_R_TYPE (rel->r_info) == R_ARM_TLS_CALL
4568 || ELF32_R_TYPE (rel->r_info) == R_ARM_THM_TLS_CALL
4569 ? 0 : (int) ELF32_R_SYM (rel->r_info) & 0xffffffff,
fe33d2fa
CL		 4570 (int) rel->r_addend & 0xffffffff,
4571 (int) stub_type);
906e58ca
NC		 4572 }
4573
4574 return stub_name;
4575}
4576
4577/* Look up an entry in the stub hash. Stub entries are cached because
4578 creating the stub name takes a bit of time. */
4579
4580static struct elf32_arm_stub_hash_entry *
4581elf32_arm_get_stub_entry (const asection *input_section,
4582 const asection *sym_sec,
4583 struct elf_link_hash_entry *hash,
4584 const Elf_Internal_Rela *rel,
fe33d2fa
CL		 4585 struct elf32_arm_link_hash_table *htab,
4586 enum elf32_arm_stub_type stub_type)
906e58ca
NC		 4587{
4588 struct elf32_arm_stub_hash_entry *stub_entry;
4589 struct elf32_arm_link_hash_entry *h = (struct elf32_arm_link_hash_entry *) hash;
4590 const asection *id_sec;
4591
4592 if ((input_section->flags & SEC_CODE) == 0)
4593 return NULL;
4594
4d83e8d9
CL		 4595 /* If the input section is the CMSE stubs one and it needs a long
4596 branch stub to reach it's final destination, give up with an
4597 error message: this is not supported. See PR ld/24709. */
4598 if (!strncmp (input_section->name, CMSE_STUB_NAME, strlen(CMSE_STUB_NAME)))
4599 {
4600 bfd *output_bfd = htab->obfd;
4601 asection *out_sec = bfd_get_section_by_name (output_bfd, CMSE_STUB_NAME);
4602
4603 _bfd_error_handler (_("ERROR: CMSE stub (%s section) too far "
4604 "(%#" PRIx64 ") from destination (%#" PRIx64 ")"),
4605 CMSE_STUB_NAME,
4606 (uint64_t)out_sec->output_section->vma
4607 + out_sec->output_offset,
4608 (uint64_t)sym_sec->output_section->vma
4609 + sym_sec->output_offset
4610 + h->root.root.u.def.value);
4611 /* Exit, rather than leave incompletely processed
4612 relocations. */
4613 xexit(1);
4614 }
4615
906e58ca
NC		 4616 /* If this input section is part of a group of sections sharing one
4617 stub section, then use the id of the first section in the group.
4618 Stub names need to include a section id, as there may well be
4619 more than one stub used to reach say, printf, and we need to
4620 distinguish between them. */
c2abbbeb 4621 BFD_ASSERT (input_section->id <= htab->top_id);
906e58ca
NC		 4622 id_sec = htab->stub_group[input_section->id].link_sec;
4623
4624 if (h != NULL && h->stub_cache != NULL
4625 && h->stub_cache->h == h
fe33d2fa
CL		 4626 && h->stub_cache->id_sec == id_sec
4627 && h->stub_cache->stub_type == stub_type)
906e58ca
NC		 4628 {
4629 stub_entry = h->stub_cache;
4630 }
4631 else
4632 {
4633 char *stub_name;
4634
fe33d2fa 4635 stub_name = elf32_arm_stub_name (id_sec, sym_sec, h, rel, stub_type);
906e58ca
NC		 4636 if (stub_name == NULL)
4637 return NULL;
4638
4639 stub_entry = arm_stub_hash_lookup (&htab->stub_hash_table,
4640 stub_name, FALSE, FALSE);
4641 if (h != NULL)
4642 h->stub_cache = stub_entry;
4643
4644 free (stub_name);
4645 }
4646
4647 return stub_entry;
4648}
4649
daa4adae
TP		 4650/* Whether veneers of type STUB_TYPE require to be in a dedicated output
4651 section. */
4652
4653static bfd_boolean
4654arm_dedicated_stub_output_section_required (enum elf32_arm_stub_type stub_type)
4655{
4656 if (stub_type >= max_stub_type)
4657 abort (); /* Should be unreachable. */
4658
4ba2ef8f
TP		 4659 switch (stub_type)
4660 {
4661 case arm_stub_cmse_branch_thumb_only:
4662 return TRUE;
4663
4664 default:
4665 return FALSE;
4666 }
4667
4668 abort (); /* Should be unreachable. */
daa4adae
TP		 4669}
4670
4671/* Required alignment (as a power of 2) for the dedicated section holding
4672 veneers of type STUB_TYPE, or 0 if veneers of this type are interspersed
4673 with input sections. */
4674
4675static int
4676arm_dedicated_stub_output_section_required_alignment
4677 (enum elf32_arm_stub_type stub_type)
4678{
4679 if (stub_type >= max_stub_type)
4680 abort (); /* Should be unreachable. */
4681
4ba2ef8f
TP		 4682 switch (stub_type)
4683 {
4684 /* Vectors of Secure Gateway veneers must be aligned on 32byte
4685 boundary. */
4686 case arm_stub_cmse_branch_thumb_only:
4687 return 5;
4688
4689 default:
4690 BFD_ASSERT (!arm_dedicated_stub_output_section_required (stub_type));
4691 return 0;
4692 }
4693
4694 abort (); /* Should be unreachable. */
daa4adae
TP		 4695}
4696
4697/* Name of the dedicated output section to put veneers of type STUB_TYPE, or
4698 NULL if veneers of this type are interspersed with input sections. */
4699
4700static const char *
4701arm_dedicated_stub_output_section_name (enum elf32_arm_stub_type stub_type)
4702{
4703 if (stub_type >= max_stub_type)
4704 abort (); /* Should be unreachable. */
4705
4ba2ef8f
TP		 4706 switch (stub_type)
4707 {
4708 case arm_stub_cmse_branch_thumb_only:
4d83e8d9 4709 return CMSE_STUB_NAME;
4ba2ef8f
TP		 4710
4711 default:
4712 BFD_ASSERT (!arm_dedicated_stub_output_section_required (stub_type));
4713 return NULL;
4714 }
4715
4716 abort (); /* Should be unreachable. */
daa4adae
TP		 4717}
4718
4719/* If veneers of type STUB_TYPE should go in a dedicated output section,
4720 returns the address of the hash table field in HTAB holding a pointer to the
4721 corresponding input section. Otherwise, returns NULL. */
4722
4723static asection **
4ba2ef8f
TP		 4724arm_dedicated_stub_input_section_ptr (struct elf32_arm_link_hash_table *htab,
4725 enum elf32_arm_stub_type stub_type)
daa4adae
TP		 4726{
4727 if (stub_type >= max_stub_type)
4728 abort (); /* Should be unreachable. */
4729
4ba2ef8f
TP		 4730 switch (stub_type)
4731 {
4732 case arm_stub_cmse_branch_thumb_only:
4733 return &htab->cmse_stub_sec;
4734
4735 default:
4736 BFD_ASSERT (!arm_dedicated_stub_output_section_required (stub_type));
4737 return NULL;
4738 }
4739
4740 abort (); /* Should be unreachable. */
daa4adae
TP		 4741}
4742
4743/* Find or create a stub section to contain a stub of type STUB_TYPE. SECTION
4744 is the section that branch into veneer and can be NULL if stub should go in
4745 a dedicated output section. Returns a pointer to the stub section, and the
4746 section to which the stub section will be attached (in *LINK_SEC_P).
48229727 4747 LINK_SEC_P may be NULL. */
906e58ca 4748
48229727
JB		 4749static asection *
4750elf32_arm_create_or_find_stub_sec (asection **link_sec_p, asection *section,
daa4adae
TP		 4751 struct elf32_arm_link_hash_table *htab,
4752 enum elf32_arm_stub_type stub_type)
906e58ca 4753{
daa4adae
TP		 4754 asection *link_sec, *out_sec, **stub_sec_p;
4755 const char *stub_sec_prefix;
4756 bfd_boolean dedicated_output_section =
4757 arm_dedicated_stub_output_section_required (stub_type);
4758 int align;
906e58ca 4759
daa4adae 4760 if (dedicated_output_section)
906e58ca 4761 {
daa4adae
TP		 4762 bfd *output_bfd = htab->obfd;
4763 const char *out_sec_name =
4764 arm_dedicated_stub_output_section_name (stub_type);
4765 link_sec = NULL;
4766 stub_sec_p = arm_dedicated_stub_input_section_ptr (htab, stub_type);
4767 stub_sec_prefix = out_sec_name;
4768 align = arm_dedicated_stub_output_section_required_alignment (stub_type);
4769 out_sec = bfd_get_section_by_name (output_bfd, out_sec_name);
4770 if (out_sec == NULL)
906e58ca 4771 {
90b6238f 4772 _bfd_error_handler (_("no address assigned to the veneers output "
4eca0228 4773 "section %s"), out_sec_name);
daa4adae 4774 return NULL;
906e58ca 4775 }
daa4adae
TP		 4776 }
4777 else
4778 {
c2abbbeb 4779 BFD_ASSERT (section->id <= htab->top_id);
daa4adae
TP		 4780 link_sec = htab->stub_group[section->id].link_sec;
4781 BFD_ASSERT (link_sec != NULL);
4782 stub_sec_p = &htab->stub_group[section->id].stub_sec;
4783 if (*stub_sec_p == NULL)
4784 stub_sec_p = &htab->stub_group[link_sec->id].stub_sec;
4785 stub_sec_prefix = link_sec->name;
4786 out_sec = link_sec->output_section;
4787 align = htab->nacl_p ? 4 : 3;
906e58ca 4788 }
b38cadfb 4789
daa4adae
TP		 4790 if (*stub_sec_p == NULL)
4791 {
4792 size_t namelen;
4793 bfd_size_type len;
4794 char *s_name;
4795
4796 namelen = strlen (stub_sec_prefix);
4797 len = namelen + sizeof (STUB_SUFFIX);
4798 s_name = (char *) bfd_alloc (htab->stub_bfd, len);
4799 if (s_name == NULL)
4800 return NULL;
4801
4802 memcpy (s_name, stub_sec_prefix, namelen);
4803 memcpy (s_name + namelen, STUB_SUFFIX, sizeof (STUB_SUFFIX));
4804 *stub_sec_p = (*htab->add_stub_section) (s_name, out_sec, link_sec,
4805 align);
4806 if (*stub_sec_p == NULL)
4807 return NULL;
4808
4809 out_sec->flags |= SEC_ALLOC | SEC_LOAD | SEC_READONLY | SEC_CODE
4810 | SEC_HAS_CONTENTS | SEC_RELOC | SEC_IN_MEMORY
4811 | SEC_KEEP;
4812 }
4813
4814 if (!dedicated_output_section)
4815 htab->stub_group[section->id].stub_sec = *stub_sec_p;
4816
48229727
JB		 4817 if (link_sec_p)
4818 *link_sec_p = link_sec;
b38cadfb 4819
daa4adae 4820 return *stub_sec_p;
48229727
JB		 4821}
4822
4823/* Add a new stub entry to the stub hash. Not all fields of the new
4824 stub entry are initialised. */
4825
4826static struct elf32_arm_stub_hash_entry *
daa4adae
TP		 4827elf32_arm_add_stub (const char *stub_name, asection *section,
4828 struct elf32_arm_link_hash_table *htab,
4829 enum elf32_arm_stub_type stub_type)
48229727
JB		 4830{
4831 asection *link_sec;
4832 asection *stub_sec;
4833 struct elf32_arm_stub_hash_entry *stub_entry;
4834
daa4adae
TP		 4835 stub_sec = elf32_arm_create_or_find_stub_sec (&link_sec, section, htab,
4836 stub_type);
48229727
JB		 4837 if (stub_sec == NULL)
4838 return NULL;
906e58ca
NC		 4839
4840 /* Enter this entry into the linker stub hash table. */
4841 stub_entry = arm_stub_hash_lookup (&htab->stub_hash_table, stub_name,
4842 TRUE, FALSE);
4843 if (stub_entry == NULL)
4844 {
6bde4c52
TP		 4845 if (section == NULL)
4846 section = stub_sec;
871b3ab2 4847 _bfd_error_handler (_("%pB: cannot create stub entry %s"),
4eca0228 4848 section->owner, stub_name);
906e58ca
NC		 4849 return NULL;
4850 }
4851
4852 stub_entry->stub_sec = stub_sec;
0955507f 4853 stub_entry->stub_offset = (bfd_vma) -1;
906e58ca
NC		 4854 stub_entry->id_sec = link_sec;
4855
906e58ca
NC		 4856 return stub_entry;
4857}
4858
4859/* Store an Arm insn into an output section not processed by
4860 elf32_arm_write_section. */
4861
4862static void
8029a119
NC		 4863put_arm_insn (struct elf32_arm_link_hash_table * htab,
4864 bfd * output_bfd, bfd_vma val, void * ptr)
906e58ca
NC		 4865{
4866 if (htab->byteswap_code != bfd_little_endian (output_bfd))
4867 bfd_putl32 (val, ptr);
4868 else
4869 bfd_putb32 (val, ptr);
4870}
4871
4872/* Store a 16-bit Thumb insn into an output section not processed by
4873 elf32_arm_write_section. */
4874
4875static void
8029a119
NC		 4876put_thumb_insn (struct elf32_arm_link_hash_table * htab,
4877 bfd * output_bfd, bfd_vma val, void * ptr)
906e58ca
NC		 4878{
4879 if (htab->byteswap_code != bfd_little_endian (output_bfd))
4880 bfd_putl16 (val, ptr);
4881 else
4882 bfd_putb16 (val, ptr);
4883}
4884
a504d23a
LA		 4885/* Store a Thumb2 insn into an output section not processed by
4886 elf32_arm_write_section. */
4887
4888static void
4889put_thumb2_insn (struct elf32_arm_link_hash_table * htab,
b98e6871 4890 bfd * output_bfd, bfd_vma val, bfd_byte * ptr)
a504d23a
LA		 4891{
4892 /* T2 instructions are 16-bit streamed. */
4893 if (htab->byteswap_code != bfd_little_endian (output_bfd))
4894 {
4895 bfd_putl16 ((val >> 16) & 0xffff, ptr);
4896 bfd_putl16 ((val & 0xffff), ptr + 2);
4897 }
4898 else
4899 {
4900 bfd_putb16 ((val >> 16) & 0xffff, ptr);
4901 bfd_putb16 ((val & 0xffff), ptr + 2);
4902 }
4903}
4904
0855e32b
NS		 4905/* If it's possible to change R_TYPE to a more efficient access
4906 model, return the new reloc type. */
4907
4908static unsigned
b38cadfb 4909elf32_arm_tls_transition (struct bfd_link_info *info, int r_type,
0855e32b
NS		 4910 struct elf_link_hash_entry *h)
4911{
4912 int is_local = (h == NULL);
4913
0e1862bb
L		 4914 if (bfd_link_pic (info)
4915 || (h && h->root.type == bfd_link_hash_undefweak))
0855e32b
NS		 4916 return r_type;
4917
b38cadfb 4918 /* We do not support relaxations for Old TLS models. */
0855e32b
NS		 4919 switch (r_type)
4920 {
4921 case R_ARM_TLS_GOTDESC:
4922 case R_ARM_TLS_CALL:
4923 case R_ARM_THM_TLS_CALL:
4924 case R_ARM_TLS_DESCSEQ:
4925 case R_ARM_THM_TLS_DESCSEQ:
4926 return is_local ? R_ARM_TLS_LE32 : R_ARM_TLS_IE32;
4927 }
4928
4929 return r_type;
4930}
4931
48229727
JB		 4932static bfd_reloc_status_type elf32_arm_final_link_relocate
4933 (reloc_howto_type *, bfd *, bfd *, asection *, bfd_byte *,
4934 Elf_Internal_Rela *, bfd_vma, struct bfd_link_info *, asection *,
34e77a92
RS		 4935 const char *, unsigned char, enum arm_st_branch_type,
4936 struct elf_link_hash_entry *, bfd_boolean *, char **);
48229727 4937
4563a860
JB		 4938static unsigned int
4939arm_stub_required_alignment (enum elf32_arm_stub_type stub_type)
4940{
4941 switch (stub_type)
4942 {
4943 case arm_stub_a8_veneer_b_cond:
4944 case arm_stub_a8_veneer_b:
4945 case arm_stub_a8_veneer_bl:
4946 return 2;
4947
4948 case arm_stub_long_branch_any_any:
4949 case arm_stub_long_branch_v4t_arm_thumb:
4950 case arm_stub_long_branch_thumb_only:
80c135e5 4951 case arm_stub_long_branch_thumb2_only:
d5a67c02 4952 case arm_stub_long_branch_thumb2_only_pure:
4563a860
JB		 4953 case arm_stub_long_branch_v4t_thumb_thumb:
4954 case arm_stub_long_branch_v4t_thumb_arm:
4955 case arm_stub_short_branch_v4t_thumb_arm:
4956 case arm_stub_long_branch_any_arm_pic:
4957 case arm_stub_long_branch_any_thumb_pic:
4958 case arm_stub_long_branch_v4t_thumb_thumb_pic:
4959 case arm_stub_long_branch_v4t_arm_thumb_pic:
4960 case arm_stub_long_branch_v4t_thumb_arm_pic:
4961 case arm_stub_long_branch_thumb_only_pic:
0855e32b
NS		 4962 case arm_stub_long_branch_any_tls_pic:
4963 case arm_stub_long_branch_v4t_thumb_tls_pic:
4ba2ef8f 4964 case arm_stub_cmse_branch_thumb_only:
4563a860
JB		 4965 case arm_stub_a8_veneer_blx:
4966 return 4;
b38cadfb 4967
7a89b94e
NC		 4968 case arm_stub_long_branch_arm_nacl:
4969 case arm_stub_long_branch_arm_nacl_pic:
4970 return 16;
4971
4563a860
JB		 4972 default:
4973 abort (); /* Should be unreachable. */
4974 }
4975}
4976
4f4faa4d
TP		 4977/* Returns whether stubs of type STUB_TYPE take over the symbol they are
4978 veneering (TRUE) or have their own symbol (FALSE). */
4979
4980static bfd_boolean
4981arm_stub_sym_claimed (enum elf32_arm_stub_type stub_type)
4982{
4983 if (stub_type >= max_stub_type)
4984 abort (); /* Should be unreachable. */
4985
4ba2ef8f
TP		 4986 switch (stub_type)
4987 {
4988 case arm_stub_cmse_branch_thumb_only:
4989 return TRUE;
4990
4991 default:
4992 return FALSE;
4993 }
4994
4995 abort (); /* Should be unreachable. */
4f4faa4d
TP		 4996}
4997
d7c5bd02
TP		 4998/* Returns the padding needed for the dedicated section used stubs of type
4999 STUB_TYPE. */
5000
5001static int
5002arm_dedicated_stub_section_padding (enum elf32_arm_stub_type stub_type)
5003{
5004 if (stub_type >= max_stub_type)
5005 abort (); /* Should be unreachable. */
5006
4ba2ef8f
TP		 5007 switch (stub_type)
5008 {
5009 case arm_stub_cmse_branch_thumb_only:
5010 return 32;
5011
5012 default:
5013 return 0;
5014 }
5015
5016 abort (); /* Should be unreachable. */
d7c5bd02
TP		 5017}
5018
0955507f
TP		 5019/* If veneers of type STUB_TYPE should go in a dedicated output section,
5020 returns the address of the hash table field in HTAB holding the offset at
5021 which new veneers should be layed out in the stub section. */
5022
5023static bfd_vma*
5024arm_new_stubs_start_offset_ptr (struct elf32_arm_link_hash_table *htab,
5025 enum elf32_arm_stub_type stub_type)
5026{
5027 switch (stub_type)
5028 {
5029 case arm_stub_cmse_branch_thumb_only:
5030 return &htab->new_cmse_stub_offset;
5031
5032 default:
5033 BFD_ASSERT (!arm_dedicated_stub_output_section_required (stub_type));
5034 return NULL;
5035 }
5036}
5037
906e58ca
NC		 5038static bfd_boolean
5039arm_build_one_stub (struct bfd_hash_entry *gen_entry,
5040 void * in_arg)
5041{
7a89b94e 5042#define MAXRELOCS 3
0955507f 5043 bfd_boolean removed_sg_veneer;
906e58ca 5044 struct elf32_arm_stub_hash_entry *stub_entry;
4dfe6ac6 5045 struct elf32_arm_link_hash_table *globals;
906e58ca 5046 struct bfd_link_info *info;
906e58ca
NC		 5047 asection *stub_sec;
5048 bfd *stub_bfd;
906e58ca
NC		 5049 bfd_byte *loc;
5050 bfd_vma sym_value;
5051 int template_size;
5052 int size;
d3ce72d0 5053 const insn_sequence *template_sequence;
906e58ca 5054 int i;
48229727
JB		 5055 int stub_reloc_idx[MAXRELOCS] = {-1, -1};
5056 int stub_reloc_offset[MAXRELOCS] = {0, 0};
5057 int nrelocs = 0;
0955507f 5058 int just_allocated = 0;
906e58ca
NC		 5059
5060 /* Massage our args to the form they really have. */
5061 stub_entry = (struct elf32_arm_stub_hash_entry *) gen_entry;
5062 info = (struct bfd_link_info *) in_arg;
5063
5064 globals = elf32_arm_hash_table (info);
4dfe6ac6
NC		 5065 if (globals == NULL)
5066 return FALSE;
906e58ca 5067
906e58ca
NC		 5068 stub_sec = stub_entry->stub_sec;
5069
4dfe6ac6 5070 if ((globals->fix_cortex_a8 < 0)
4563a860
JB		 5071 != (arm_stub_required_alignment (stub_entry->stub_type) == 2))
5072 /* We have to do less-strictly-aligned fixes last. */
eb7c4339 5073 return TRUE;
fe33d2fa 5074
0955507f
TP		 5075 /* Assign a slot at the end of section if none assigned yet. */
5076 if (stub_entry->stub_offset == (bfd_vma) -1)
5077 {
5078 stub_entry->stub_offset = stub_sec->size;
5079 just_allocated = 1;
5080 }
906e58ca
NC		 5081 loc = stub_sec->contents + stub_entry->stub_offset;
5082
5083 stub_bfd = stub_sec->owner;
5084
906e58ca
NC		 5085 /* This is the address of the stub destination. */
5086 sym_value = (stub_entry->target_value
5087 + stub_entry->target_section->output_offset
5088 + stub_entry->target_section->output_section->vma);
5089
d3ce72d0 5090 template_sequence = stub_entry->stub_template;
461a49ca 5091 template_size = stub_entry->stub_template_size;
906e58ca
NC		 5092
5093 size = 0;
461a49ca 5094 for (i = 0; i < template_size; i++)
906e58ca 5095 {
d3ce72d0 5096 switch (template_sequence[i].type)
461a49ca
DJ		 5097 {
5098 case THUMB16_TYPE:
48229727 5099 {
d3ce72d0
NC		 5100 bfd_vma data = (bfd_vma) template_sequence[i].data;
5101 if (template_sequence[i].reloc_addend != 0)
48229727 5102 {
99059e56
RM		 5103 /* We've borrowed the reloc_addend field to mean we should
5104 insert a condition code into this (Thumb-1 branch)
5105 instruction. See THUMB16_BCOND_INSN. */
5106 BFD_ASSERT ((data & 0xff00) == 0xd000);
5107 data |= ((stub_entry->orig_insn >> 22) & 0xf) << 8;
48229727 5108 }
fe33d2fa 5109 bfd_put_16 (stub_bfd, data, loc + size);
48229727
JB		 5110 size += 2;
5111 }
461a49ca 5112 break;
906e58ca 5113
48229727 5114 case THUMB32_TYPE:
fe33d2fa
CL		 5115 bfd_put_16 (stub_bfd,
5116 (template_sequence[i].data >> 16) & 0xffff,
5117 loc + size);
5118 bfd_put_16 (stub_bfd, template_sequence[i].data & 0xffff,
5119 loc + size + 2);
99059e56
RM		 5120 if (template_sequence[i].r_type != R_ARM_NONE)
5121 {
5122 stub_reloc_idx[nrelocs] = i;
5123 stub_reloc_offset[nrelocs++] = size;
5124 }
5125 size += 4;
5126 break;
48229727 5127
461a49ca 5128 case ARM_TYPE:
fe33d2fa
CL		 5129 bfd_put_32 (stub_bfd, template_sequence[i].data,
5130 loc + size);
461a49ca
DJ		 5131 /* Handle cases where the target is encoded within the
5132 instruction. */
d3ce72d0 5133 if (template_sequence[i].r_type == R_ARM_JUMP24)
461a49ca 5134 {
48229727
JB		 5135 stub_reloc_idx[nrelocs] = i;
5136 stub_reloc_offset[nrelocs++] = size;
461a49ca
DJ		 5137 }
5138 size += 4;
5139 break;
5140
5141 case DATA_TYPE:
d3ce72d0 5142 bfd_put_32 (stub_bfd, template_sequence[i].data, loc + size);
48229727
JB		 5143 stub_reloc_idx[nrelocs] = i;
5144 stub_reloc_offset[nrelocs++] = size;
461a49ca
DJ		 5145 size += 4;
5146 break;
5147
5148 default:
5149 BFD_FAIL ();
5150 return FALSE;
5151 }
906e58ca 5152 }
461a49ca 5153
0955507f
TP		 5154 if (just_allocated)
5155 stub_sec->size += size;
906e58ca 5156
461a49ca
DJ		 5157 /* Stub size has already been computed in arm_size_one_stub. Check
5158 consistency. */
5159 BFD_ASSERT (size == stub_entry->stub_size);
5160
906e58ca 5161 /* Destination is Thumb. Force bit 0 to 1 to reflect this. */
35fc36a8 5162 if (stub_entry->branch_type == ST_BRANCH_TO_THUMB)
906e58ca
NC		 5163 sym_value |= 1;
5164
0955507f
TP		 5165 /* Assume non empty slots have at least one and at most MAXRELOCS entries
5166 to relocate in each stub. */
5167 removed_sg_veneer =
5168 (size == 0 && stub_entry->stub_type == arm_stub_cmse_branch_thumb_only);
5169 BFD_ASSERT (removed_sg_veneer || (nrelocs != 0 && nrelocs <= MAXRELOCS));
c820be07 5170
48229727 5171 for (i = 0; i < nrelocs; i++)
8d9d9490
TP		 5172 {
5173 Elf_Internal_Rela rel;
5174 bfd_boolean unresolved_reloc;
5175 char *error_message;
5176 bfd_vma points_to =
5177 sym_value + template_sequence[stub_reloc_idx[i]].reloc_addend;
5178
5179 rel.r_offset = stub_entry->stub_offset + stub_reloc_offset[i];
5180 rel.r_info = ELF32_R_INFO (0,
5181 template_sequence[stub_reloc_idx[i]].r_type);
5182 rel.r_addend = 0;
5183
5184 if (stub_entry->stub_type == arm_stub_a8_veneer_b_cond && i == 0)
5185 /* The first relocation in the elf32_arm_stub_a8_veneer_b_cond[]
5186 template should refer back to the instruction after the original
5187 branch. We use target_section as Cortex-A8 erratum workaround stubs
5188 are only generated when both source and target are in the same
5189 section. */
5190 points_to = stub_entry->target_section->output_section->vma
5191 + stub_entry->target_section->output_offset
5192 + stub_entry->source_value;
5193
5194 elf32_arm_final_link_relocate (elf32_arm_howto_from_type
5195 (template_sequence[stub_reloc_idx[i]].r_type),
5196 stub_bfd, info->output_bfd, stub_sec, stub_sec->contents, &rel,
5197 points_to, info, stub_entry->target_section, "", STT_FUNC,
5198 stub_entry->branch_type,
5199 (struct elf_link_hash_entry *) stub_entry->h, &unresolved_reloc,
5200 &error_message);
5201 }
906e58ca
NC		 5202
5203 return TRUE;
48229727 5204#undef MAXRELOCS
906e58ca
NC		 5205}
5206
48229727
JB		 5207/* Calculate the template, template size and instruction size for a stub.
5208 Return value is the instruction size. */
906e58ca 5209
48229727
JB		 5210static unsigned int
5211find_stub_size_and_template (enum elf32_arm_stub_type stub_type,
5212 const insn_sequence **stub_template,
5213 int *stub_template_size)
906e58ca 5214{
d3ce72d0 5215 const insn_sequence *template_sequence = NULL;
48229727
JB		 5216 int template_size = 0, i;
5217 unsigned int size;
906e58ca 5218
d3ce72d0 5219 template_sequence = stub_definitions[stub_type].template_sequence;
2a229407
AM		 5220 if (stub_template)
5221 *stub_template = template_sequence;
5222
48229727 5223 template_size = stub_definitions[stub_type].template_size;
2a229407
AM		 5224 if (stub_template_size)
5225 *stub_template_size = template_size;
906e58ca
NC		 5226
5227 size = 0;
461a49ca
DJ		 5228 for (i = 0; i < template_size; i++)
5229 {
d3ce72d0 5230 switch (template_sequence[i].type)
461a49ca
DJ		 5231 {
5232 case THUMB16_TYPE:
5233 size += 2;
5234 break;
5235
5236 case ARM_TYPE:
48229727 5237 case THUMB32_TYPE:
461a49ca
DJ		 5238 case DATA_TYPE:
5239 size += 4;
5240 break;
5241
5242 default:
5243 BFD_FAIL ();
2a229407 5244 return 0;
461a49ca
DJ		 5245 }
5246 }
5247
48229727
JB		 5248 return size;
5249}
5250
5251/* As above, but don't actually build the stub. Just bump offset so
5252 we know stub section sizes. */
5253
5254static bfd_boolean
5255arm_size_one_stub (struct bfd_hash_entry *gen_entry,
c7e2358a 5256 void *in_arg ATTRIBUTE_UNUSED)
48229727
JB		 5257{
5258 struct elf32_arm_stub_hash_entry *stub_entry;
d3ce72d0 5259 const insn_sequence *template_sequence;
48229727
JB		 5260 int template_size, size;
5261
5262 /* Massage our args to the form they really have. */
5263 stub_entry = (struct elf32_arm_stub_hash_entry *) gen_entry;
48229727
JB		 5264
5265 BFD_ASSERT((stub_entry->stub_type > arm_stub_none)
5266 && stub_entry->stub_type < ARRAY_SIZE(stub_definitions));
5267
d3ce72d0 5268 size = find_stub_size_and_template (stub_entry->stub_type, &template_sequence,
48229727
JB		 5269 &template_size);
5270
0955507f
TP		 5271 /* Initialized to -1. Null size indicates an empty slot full of zeros. */
5272 if (stub_entry->stub_template_size)
5273 {
5274 stub_entry->stub_size = size;
5275 stub_entry->stub_template = template_sequence;
5276 stub_entry->stub_template_size = template_size;
5277 }
5278
5279 /* Already accounted for. */
5280 if (stub_entry->stub_offset != (bfd_vma) -1)
5281 return TRUE;
461a49ca 5282
906e58ca
NC		 5283 size = (size + 7) & ~7;
5284 stub_entry->stub_sec->size += size;
461a49ca 5285
906e58ca
NC		 5286 return TRUE;
5287}
5288
5289/* External entry points for sizing and building linker stubs. */
5290
5291/* Set up various things so that we can make a list of input sections
5292 for each output section included in the link. Returns -1 on error,
5293 0 when no stubs will be needed, and 1 on success. */
5294
5295int
5296elf32_arm_setup_section_lists (bfd *output_bfd,
5297 struct bfd_link_info *info)
5298{
5299 bfd *input_bfd;
5300 unsigned int bfd_count;
7292b3ac 5301 unsigned int top_id, top_index;
906e58ca
NC		 5302 asection *section;
5303 asection **input_list, **list;
5304 bfd_size_type amt;
5305 struct elf32_arm_link_hash_table *htab = elf32_arm_hash_table (info);
5306
4dfe6ac6
NC		 5307 if (htab == NULL)
5308 return 0;
906e58ca
NC		 5309 if (! is_elf_hash_table (htab))
5310 return 0;
5311
5312 /* Count the number of input BFDs and find the top input section id. */
5313 for (input_bfd = info->input_bfds, bfd_count = 0, top_id = 0;
5314 input_bfd != NULL;
c72f2fb2 5315 input_bfd = input_bfd->link.next)
906e58ca
NC		 5316 {
5317 bfd_count += 1;
5318 for (section = input_bfd->sections;
5319 section != NULL;
5320 section = section->next)
5321 {
5322 if (top_id < section->id)
5323 top_id = section->id;
5324 }
5325 }
5326 htab->bfd_count = bfd_count;
5327
5328 amt = sizeof (struct map_stub) * (top_id + 1);
21d799b5 5329 htab->stub_group = (struct map_stub *) bfd_zmalloc (amt);
906e58ca
NC		 5330 if (htab->stub_group == NULL)
5331 return -1;
fe33d2fa 5332 htab->top_id = top_id;
906e58ca
NC		 5333
5334 /* We can't use output_bfd->section_count here to find the top output
5335 section index as some sections may have been removed, and
5336 _bfd_strip_section_from_output doesn't renumber the indices. */
5337 for (section = output_bfd->sections, top_index = 0;
5338 section != NULL;
5339 section = section->next)
5340 {
5341 if (top_index < section->index)
5342 top_index = section->index;
5343 }
5344
5345 htab->top_index = top_index;
5346 amt = sizeof (asection *) * (top_index + 1);
21d799b5 5347 input_list = (asection **) bfd_malloc (amt);
906e58ca
NC		 5348 htab->input_list = input_list;
5349 if (input_list == NULL)
5350 return -1;
5351
5352 /* For sections we aren't interested in, mark their entries with a
5353 value we can check later. */
5354 list = input_list + top_index;
5355 do
5356 *list = bfd_abs_section_ptr;
5357 while (list-- != input_list);
5358
5359 for (section = output_bfd->sections;
5360 section != NULL;
5361 section = section->next)
5362 {
5363 if ((section->flags & SEC_CODE) != 0)
5364 input_list[section->index] = NULL;
5365 }
5366
5367 return 1;
5368}
5369
5370/* The linker repeatedly calls this function for each input section,
5371 in the order that input sections are linked into output sections.
5372 Build lists of input sections to determine groupings between which
5373 we may insert linker stubs. */
5374
5375void
5376elf32_arm_next_input_section (struct bfd_link_info *info,
5377 asection *isec)
5378{
5379 struct elf32_arm_link_hash_table *htab = elf32_arm_hash_table (info);
5380
4dfe6ac6
NC		 5381 if (htab == NULL)
5382 return;
5383
906e58ca
NC		 5384 if (isec->output_section->index <= htab->top_index)
5385 {
5386 asection **list = htab->input_list + isec->output_section->index;
5387
a7470592 5388 if (*list != bfd_abs_section_ptr && (isec->flags & SEC_CODE) != 0)
906e58ca
NC		 5389 {
5390 /* Steal the link_sec pointer for our list. */
5391#define PREV_SEC(sec) (htab->stub_group[(sec)->id].link_sec)
5392 /* This happens to make the list in reverse order,
07d72278 5393 which we reverse later. */
906e58ca
NC		 5394 PREV_SEC (isec) = *list;
5395 *list = isec;
5396 }
5397 }
5398}
5399
5400/* See whether we can group stub sections together. Grouping stub
5401 sections may result in fewer stubs. More importantly, we need to
07d72278 5402 put all .init* and .fini* stubs at the end of the .init or
906e58ca
NC		 5403 .fini output sections respectively, because glibc splits the
5404 _init and _fini functions into multiple parts. Putting a stub in
5405 the middle of a function is not a good idea. */
5406
5407static void
5408group_sections (struct elf32_arm_link_hash_table *htab,
5409 bfd_size_type stub_group_size,
07d72278 5410 bfd_boolean stubs_always_after_branch)
906e58ca 5411{
07d72278 5412 asection **list = htab->input_list;
906e58ca
NC		 5413
5414 do
5415 {
5416 asection *tail = *list;
07d72278 5417 asection *head;
906e58ca
NC		 5418
5419 if (tail == bfd_abs_section_ptr)
5420 continue;
5421
07d72278
DJ		 5422 /* Reverse the list: we must avoid placing stubs at the
5423 beginning of the section because the beginning of the text
5424 section may be required for an interrupt vector in bare metal
5425 code. */
5426#define NEXT_SEC PREV_SEC
e780aef2
CL		 5427 head = NULL;
5428 while (tail != NULL)
99059e56
RM		 5429 {
5430 /* Pop from tail. */
5431 asection *item = tail;
5432 tail = PREV_SEC (item);
e780aef2 5433
99059e56
RM		 5434 /* Push on head. */
5435 NEXT_SEC (item) = head;
5436 head = item;
5437 }
07d72278
DJ		 5438
5439 while (head != NULL)
906e58ca
NC		 5440 {
5441 asection *curr;
07d72278 5442 asection *next;
e780aef2
CL		 5443 bfd_vma stub_group_start = head->output_offset;
5444 bfd_vma end_of_next;
906e58ca 5445
07d72278 5446 curr = head;
e780aef2 5447 while (NEXT_SEC (curr) != NULL)
8cd931b7 5448 {
e780aef2
CL		 5449 next = NEXT_SEC (curr);
5450 end_of_next = next->output_offset + next->size;
5451 if (end_of_next - stub_group_start >= stub_group_size)
5452 /* End of NEXT is too far from start, so stop. */
8cd931b7 5453 break;
e780aef2
CL		 5454 /* Add NEXT to the group. */
5455 curr = next;
8cd931b7 5456 }
906e58ca 5457
07d72278 5458 /* OK, the size from the start to the start of CURR is less
906e58ca 5459 than stub_group_size and thus can be handled by one stub
07d72278 5460 section. (Or the head section is itself larger than
906e58ca
NC		 5461 stub_group_size, in which case we may be toast.)
5462 We should really be keeping track of the total size of
5463 stubs added here, as stubs contribute to the final output
7fb9f789 5464 section size. */
906e58ca
NC		 5465 do
5466 {
07d72278 5467 next = NEXT_SEC (head);
906e58ca 5468 /* Set up this stub group. */
07d72278 5469 htab->stub_group[head->id].link_sec = curr;
906e58ca 5470 }
07d72278 5471 while (head != curr && (head = next) != NULL);
906e58ca
NC		 5472
5473 /* But wait, there's more! Input sections up to stub_group_size
07d72278
DJ		 5474 bytes after the stub section can be handled by it too. */
5475 if (!stubs_always_after_branch)
906e58ca 5476 {
e780aef2
CL		 5477 stub_group_start = curr->output_offset + curr->size;
5478
8cd931b7 5479 while (next != NULL)
906e58ca 5480 {
e780aef2
CL		 5481 end_of_next = next->output_offset + next->size;
5482 if (end_of_next - stub_group_start >= stub_group_size)
5483 /* End of NEXT is too far from stubs, so stop. */
8cd931b7 5484 break;
e780aef2 5485 /* Add NEXT to the stub group. */
07d72278
DJ		 5486 head = next;
5487 next = NEXT_SEC (head);
5488 htab->stub_group[head->id].link_sec = curr;
906e58ca
NC		 5489 }
5490 }
07d72278 5491 head = next;
906e58ca
NC		 5492 }
5493 }
07d72278 5494 while (list++ != htab->input_list + htab->top_index);
906e58ca
NC		 5495
5496 free (htab->input_list);
5497#undef PREV_SEC
07d72278 5498#undef NEXT_SEC
906e58ca
NC		 5499}
5500
48229727
JB		 5501/* Comparison function for sorting/searching relocations relating to Cortex-A8
5502 erratum fix. */
5503
5504static int
5505a8_reloc_compare (const void *a, const void *b)
5506{
21d799b5
NC		 5507 const struct a8_erratum_reloc *ra = (const struct a8_erratum_reloc *) a;
5508 const struct a8_erratum_reloc *rb = (const struct a8_erratum_reloc *) b;
48229727
JB		 5509
5510 if (ra->from < rb->from)
5511 return -1;
5512 else if (ra->from > rb->from)
5513 return 1;
5514 else
5515 return 0;
5516}
5517
5518static struct elf_link_hash_entry *find_thumb_glue (struct bfd_link_info *,
5519 const char *, char **);
5520
5521/* Helper function to scan code for sequences which might trigger the Cortex-A8
5522 branch/TLB erratum. Fill in the table described by A8_FIXES_P,
81694485 5523 NUM_A8_FIXES_P, A8_FIX_TABLE_SIZE_P. Returns true if an error occurs, false
48229727
JB		 5524 otherwise. */
5525
81694485
NC		 5526static bfd_boolean
5527cortex_a8_erratum_scan (bfd *input_bfd,
5528 struct bfd_link_info *info,
48229727
JB		 5529 struct a8_erratum_fix **a8_fixes_p,
5530 unsigned int *num_a8_fixes_p,
5531 unsigned int *a8_fix_table_size_p,
5532 struct a8_erratum_reloc *a8_relocs,
eb7c4339
NS		 5533 unsigned int num_a8_relocs,
5534 unsigned prev_num_a8_fixes,
5535 bfd_boolean *stub_changed_p)
48229727
JB		 5536{
5537 asection *section;
5538 struct elf32_arm_link_hash_table *htab = elf32_arm_hash_table (info);
5539 struct a8_erratum_fix *a8_fixes = *a8_fixes_p;
5540 unsigned int num_a8_fixes = *num_a8_fixes_p;
5541 unsigned int a8_fix_table_size = *a8_fix_table_size_p;
5542
4dfe6ac6
NC		 5543 if (htab == NULL)
5544 return FALSE;
5545
48229727
JB		 5546 for (section = input_bfd->sections;
5547 section != NULL;
5548 section = section->next)
5549 {
5550 bfd_byte *contents = NULL;
5551 struct _arm_elf_section_data *sec_data;
5552 unsigned int span;
5553 bfd_vma base_vma;
5554
5555 if (elf_section_type (section) != SHT_PROGBITS
99059e56
RM		 5556 || (elf_section_flags (section) & SHF_EXECINSTR) == 0
5557 || (section->flags & SEC_EXCLUDE) != 0
5558 || (section->sec_info_type == SEC_INFO_TYPE_JUST_SYMS)
5559 || (section->output_section == bfd_abs_section_ptr))
5560 continue;
48229727
JB		 5561
5562 base_vma = section->output_section->vma + section->output_offset;
5563
5564 if (elf_section_data (section)->this_hdr.contents != NULL)
99059e56 5565 contents = elf_section_data (section)->this_hdr.contents;
48229727 5566 else if (! bfd_malloc_and_get_section (input_bfd, section, &contents))
99059e56 5567 return TRUE;
48229727
JB		 5568
5569 sec_data = elf32_arm_section_data (section);
5570
5571 for (span = 0; span < sec_data->mapcount; span++)
99059e56
RM		 5572 {
5573 unsigned int span_start = sec_data->map[span].vma;
5574 unsigned int span_end = (span == sec_data->mapcount - 1)
5575 ? section->size : sec_data->map[span + 1].vma;
5576 unsigned int i;
5577 char span_type = sec_data->map[span].type;
5578 bfd_boolean last_was_32bit = FALSE, last_was_branch = FALSE;
5579
5580 if (span_type != 't')
5581 continue;
5582
5583 /* Span is entirely within a single 4KB region: skip scanning. */
5584 if (((base_vma + span_start) & ~0xfff)
48229727 5585 == ((base_vma + span_end) & ~0xfff))
99059e56
RM		 5586 continue;
5587
5588 /* Scan for 32-bit Thumb-2 branches which span two 4K regions, where:
5589
5590 * The opcode is BLX.W, BL.W, B.W, Bcc.W
5591 * The branch target is in the same 4KB region as the
5592 first half of the branch.
5593 * The instruction before the branch is a 32-bit
5594 length non-branch instruction. */
5595 for (i = span_start; i < span_end;)
5596 {
5597 unsigned int insn = bfd_getl16 (&contents[i]);
5598 bfd_boolean insn_32bit = FALSE, is_blx = FALSE, is_b = FALSE;
48229727
JB		 5599 bfd_boolean is_bl = FALSE, is_bcc = FALSE, is_32bit_branch;
5600
99059e56
RM		 5601 if ((insn & 0xe000) == 0xe000 && (insn & 0x1800) != 0x0000)
5602 insn_32bit = TRUE;
48229727
JB		 5603
5604 if (insn_32bit)
99059e56
RM		 5605 {
5606 /* Load the rest of the insn (in manual-friendly order). */
5607 insn = (insn << 16) | bfd_getl16 (&contents[i + 2]);
5608
5609 /* Encoding T4: B<c>.W. */
5610 is_b = (insn & 0xf800d000) == 0xf0009000;
5611 /* Encoding T1: BL<c>.W. */
5612 is_bl = (insn & 0xf800d000) == 0xf000d000;
5613 /* Encoding T2: BLX<c>.W. */
5614 is_blx = (insn & 0xf800d000) == 0xf000c000;
48229727
JB		 5615 /* Encoding T3: B<c>.W (not permitted in IT block). */
5616 is_bcc = (insn & 0xf800d000) == 0xf0008000
5617 && (insn & 0x07f00000) != 0x03800000;
5618 }
5619
5620 is_32bit_branch = is_b || is_bl || is_blx || is_bcc;
fe33d2fa 5621
99059e56 5622 if (((base_vma + i) & 0xfff) == 0xffe
81694485
NC		 5623 && insn_32bit
5624 && is_32bit_branch
5625 && last_was_32bit
5626 && ! last_was_branch)
99059e56
RM		 5627 {
5628 bfd_signed_vma offset = 0;
5629 bfd_boolean force_target_arm = FALSE;
48229727 5630 bfd_boolean force_target_thumb = FALSE;
99059e56
RM		 5631 bfd_vma target;
5632 enum elf32_arm_stub_type stub_type = arm_stub_none;
5633 struct a8_erratum_reloc key, *found;
5634 bfd_boolean use_plt = FALSE;
48229727 5635
99059e56
RM		 5636 key.from = base_vma + i;
5637 found = (struct a8_erratum_reloc *)
5638 bsearch (&key, a8_relocs, num_a8_relocs,
5639 sizeof (struct a8_erratum_reloc),
5640 &a8_reloc_compare);
48229727
JB		 5641
5642 if (found)
5643 {
5644 char *error_message = NULL;
5645 struct elf_link_hash_entry *entry;
5646
5647 /* We don't care about the error returned from this
99059e56 5648 function, only if there is glue or not. */
48229727
JB		 5649 entry = find_thumb_glue (info, found->sym_name,
5650 &error_message);
5651
5652 if (entry)
5653 found->non_a8_stub = TRUE;
5654
92750f34 5655 /* Keep a simpler condition, for the sake of clarity. */
362d30a1 5656 if (htab->root.splt != NULL && found->hash != NULL
92750f34
DJ		 5657 && found->hash->root.plt.offset != (bfd_vma) -1)
5658 use_plt = TRUE;
5659
5660 if (found->r_type == R_ARM_THM_CALL)
5661 {
35fc36a8
RS		 5662 if (found->branch_type == ST_BRANCH_TO_ARM
5663 || use_plt)
92750f34
DJ		 5664 force_target_arm = TRUE;
5665 else
5666 force_target_thumb = TRUE;
5667 }
48229727
JB		 5668 }
5669
99059e56 5670 /* Check if we have an offending branch instruction. */
48229727
JB		 5671
5672 if (found && found->non_a8_stub)
5673 /* We've already made a stub for this instruction, e.g.
5674 it's a long branch or a Thumb->ARM stub. Assume that
5675 stub will suffice to work around the A8 erratum (see
5676 setting of always_after_branch above). */
5677 ;
99059e56
RM		 5678 else if (is_bcc)
5679 {
5680 offset = (insn & 0x7ff) << 1;
5681 offset |= (insn & 0x3f0000) >> 4;
5682 offset |= (insn & 0x2000) ? 0x40000 : 0;
5683 offset |= (insn & 0x800) ? 0x80000 : 0;
5684 offset |= (insn & 0x4000000) ? 0x100000 : 0;
5685 if (offset & 0x100000)
5686 offset |= ~ ((bfd_signed_vma) 0xfffff);
5687 stub_type = arm_stub_a8_veneer_b_cond;
5688 }
5689 else if (is_b || is_bl || is_blx)
5690 {
5691 int s = (insn & 0x4000000) != 0;
5692 int j1 = (insn & 0x2000) != 0;
5693 int j2 = (insn & 0x800) != 0;
5694 int i1 = !(j1 ^ s);
5695 int i2 = !(j2 ^ s);
5696
5697 offset = (insn & 0x7ff) << 1;
5698 offset |= (insn & 0x3ff0000) >> 4;
5699 offset |= i2 << 22;
5700 offset |= i1 << 23;
5701 offset |= s << 24;
5702 if (offset & 0x1000000)
5703 offset |= ~ ((bfd_signed_vma) 0xffffff);
5704
5705 if (is_blx)
5706 offset &= ~ ((bfd_signed_vma) 3);
5707
5708 stub_type = is_blx ? arm_stub_a8_veneer_blx :
5709 is_bl ? arm_stub_a8_veneer_bl : arm_stub_a8_veneer_b;
5710 }
5711
5712 if (stub_type != arm_stub_none)
5713 {
5714 bfd_vma pc_for_insn = base_vma + i + 4;
48229727
JB		 5715
5716 /* The original instruction is a BL, but the target is
99059e56 5717 an ARM instruction. If we were not making a stub,
48229727
JB		 5718 the BL would have been converted to a BLX. Use the
5719 BLX stub instead in that case. */
5720 if (htab->use_blx && force_target_arm
5721 && stub_type == arm_stub_a8_veneer_bl)
5722 {
5723 stub_type = arm_stub_a8_veneer_blx;
5724 is_blx = TRUE;
5725 is_bl = FALSE;
5726 }
5727 /* Conversely, if the original instruction was
5728 BLX but the target is Thumb mode, use the BL
5729 stub. */
5730 else if (force_target_thumb
5731 && stub_type == arm_stub_a8_veneer_blx)
5732 {
5733 stub_type = arm_stub_a8_veneer_bl;
5734 is_blx = FALSE;
5735 is_bl = TRUE;
5736 }
5737
99059e56
RM		 5738 if (is_blx)
5739 pc_for_insn &= ~ ((bfd_vma) 3);
48229727 5740
99059e56
RM		 5741 /* If we found a relocation, use the proper destination,
5742 not the offset in the (unrelocated) instruction.
48229727
JB		 5743 Note this is always done if we switched the stub type
5744 above. */
99059e56
RM		 5745 if (found)
5746 offset =
81694485 5747 (bfd_signed_vma) (found->destination - pc_for_insn);
48229727 5748
99059e56
RM		 5749 /* If the stub will use a Thumb-mode branch to a
5750 PLT target, redirect it to the preceding Thumb
5751 entry point. */
5752 if (stub_type != arm_stub_a8_veneer_blx && use_plt)
5753 offset -= PLT_THUMB_STUB_SIZE;
7d24e6a6 5754
99059e56 5755 target = pc_for_insn + offset;
48229727 5756
99059e56
RM		 5757 /* The BLX stub is ARM-mode code. Adjust the offset to
5758 take the different PC value (+8 instead of +4) into
48229727 5759 account. */
99059e56
RM		 5760 if (stub_type == arm_stub_a8_veneer_blx)
5761 offset += 4;
5762
5763 if (((base_vma + i) & ~0xfff) == (target & ~0xfff))
5764 {
5765 char *stub_name = NULL;
5766
5767 if (num_a8_fixes == a8_fix_table_size)
5768 {
5769 a8_fix_table_size *= 2;
5770 a8_fixes = (struct a8_erratum_fix *)
5771 bfd_realloc (a8_fixes,
5772 sizeof (struct a8_erratum_fix)
5773 * a8_fix_table_size);
5774 }
48229727 5775
eb7c4339
NS		 5776 if (num_a8_fixes < prev_num_a8_fixes)
5777 {
5778 /* If we're doing a subsequent scan,
5779 check if we've found the same fix as
5780 before, and try and reuse the stub
5781 name. */
5782 stub_name = a8_fixes[num_a8_fixes].stub_name;
5783 if ((a8_fixes[num_a8_fixes].section != section)
5784 || (a8_fixes[num_a8_fixes].offset != i))
5785 {
5786 free (stub_name);
5787 stub_name = NULL;
5788 *stub_changed_p = TRUE;
5789 }
5790 }
5791
5792 if (!stub_name)
5793 {
21d799b5 5794 stub_name = (char *) bfd_malloc (8 + 1 + 8 + 1);
eb7c4339
NS		 5795 if (stub_name != NULL)
5796 sprintf (stub_name, "%x:%x", section->id, i);
5797 }
48229727 5798
99059e56
RM		 5799 a8_fixes[num_a8_fixes].input_bfd = input_bfd;
5800 a8_fixes[num_a8_fixes].section = section;
5801 a8_fixes[num_a8_fixes].offset = i;
8d9d9490
TP		 5802 a8_fixes[num_a8_fixes].target_offset =
5803 target - base_vma;
99059e56
RM		 5804 a8_fixes[num_a8_fixes].orig_insn = insn;
5805 a8_fixes[num_a8_fixes].stub_name = stub_name;
5806 a8_fixes[num_a8_fixes].stub_type = stub_type;
5807 a8_fixes[num_a8_fixes].branch_type =
35fc36a8 5808 is_blx ? ST_BRANCH_TO_ARM : ST_BRANCH_TO_THUMB;
48229727 5809
99059e56
RM		 5810 num_a8_fixes++;
5811 }
5812 }
5813 }
48229727 5814
99059e56
RM		 5815 i += insn_32bit ? 4 : 2;
5816 last_was_32bit = insn_32bit;
48229727 5817 last_was_branch = is_32bit_branch;
99059e56
RM		 5818 }
5819 }
48229727
JB		 5820
5821 if (elf_section_data (section)->this_hdr.contents == NULL)
99059e56 5822 free (contents);
48229727 5823 }
fe33d2fa 5824
48229727
JB		 5825 *a8_fixes_p = a8_fixes;
5826 *num_a8_fixes_p = num_a8_fixes;
5827 *a8_fix_table_size_p = a8_fix_table_size;
fe33d2fa 5828
81694485 5829 return FALSE;
48229727
JB		 5830}
5831
b715f643
TP		 5832/* Create or update a stub entry depending on whether the stub can already be
5833 found in HTAB. The stub is identified by:
5834 - its type STUB_TYPE
5835 - its source branch (note that several can share the same stub) whose
5836 section and relocation (if any) are given by SECTION and IRELA
5837 respectively
5838 - its target symbol whose input section, hash, name, value and branch type
5839 are given in SYM_SEC, HASH, SYM_NAME, SYM_VALUE and BRANCH_TYPE
5840 respectively
5841
5842 If found, the value of the stub's target symbol is updated from SYM_VALUE
5843 and *NEW_STUB is set to FALSE. Otherwise, *NEW_STUB is set to
5844 TRUE and the stub entry is initialized.
5845
0955507f
TP		 5846 Returns the stub that was created or updated, or NULL if an error
5847 occurred. */
b715f643 5848
0955507f 5849static struct elf32_arm_stub_hash_entry *
b715f643
TP		 5850elf32_arm_create_stub (struct elf32_arm_link_hash_table *htab,
5851 enum elf32_arm_stub_type stub_type, asection *section,
5852 Elf_Internal_Rela *irela, asection *sym_sec,
5853 struct elf32_arm_link_hash_entry *hash, char *sym_name,
5854 bfd_vma sym_value, enum arm_st_branch_type branch_type,
5855 bfd_boolean *new_stub)
5856{
5857 const asection *id_sec;
5858 char *stub_name;
5859 struct elf32_arm_stub_hash_entry *stub_entry;
5860 unsigned int r_type;
4f4faa4d 5861 bfd_boolean sym_claimed = arm_stub_sym_claimed (stub_type);
b715f643
TP		 5862
5863 BFD_ASSERT (stub_type != arm_stub_none);
5864 *new_stub = FALSE;
5865
4f4faa4d
TP		 5866 if (sym_claimed)
5867 stub_name = sym_name;
5868 else
5869 {
5870 BFD_ASSERT (irela);
5871 BFD_ASSERT (section);
c2abbbeb 5872 BFD_ASSERT (section->id <= htab->top_id);
b715f643 5873
4f4faa4d
TP		 5874 /* Support for grouping stub sections. */
5875 id_sec = htab->stub_group[section->id].link_sec;
b715f643 5876
4f4faa4d
TP		 5877 /* Get the name of this stub. */
5878 stub_name = elf32_arm_stub_name (id_sec, sym_sec, hash, irela,
5879 stub_type);
5880 if (!stub_name)
0955507f 5881 return NULL;
4f4faa4d 5882 }
b715f643
TP		 5883
5884 stub_entry = arm_stub_hash_lookup (&htab->stub_hash_table, stub_name, FALSE,
5885 FALSE);
5886 /* The proper stub has already been created, just update its value. */
5887 if (stub_entry != NULL)
5888 {
4f4faa4d
TP		 5889 if (!sym_claimed)
5890 free (stub_name);
b715f643 5891 stub_entry->target_value = sym_value;
0955507f 5892 return stub_entry;
b715f643
TP		 5893 }
5894
daa4adae 5895 stub_entry = elf32_arm_add_stub (stub_name, section, htab, stub_type);
b715f643
TP		 5896 if (stub_entry == NULL)
5897 {
4f4faa4d
TP		 5898 if (!sym_claimed)
5899 free (stub_name);
0955507f 5900 return NULL;
b715f643
TP		 5901 }
5902
5903 stub_entry->target_value = sym_value;
5904 stub_entry->target_section = sym_sec;
5905 stub_entry->stub_type = stub_type;
5906 stub_entry->h = hash;
5907 stub_entry->branch_type = branch_type;
5908
4f4faa4d
TP		 5909 if (sym_claimed)
5910 stub_entry->output_name = sym_name;
5911 else
b715f643 5912 {
4f4faa4d
TP		 5913 if (sym_name == NULL)
5914 sym_name = "unnamed";
5915 stub_entry->output_name = (char *)
5916 bfd_alloc (htab->stub_bfd, sizeof (THUMB2ARM_GLUE_ENTRY_NAME)
5917 + strlen (sym_name));
5918 if (stub_entry->output_name == NULL)
5919 {
5920 free (stub_name);
0955507f 5921 return NULL;
4f4faa4d 5922 }
b715f643 5923
4f4faa4d
TP		 5924 /* For historical reasons, use the existing names for ARM-to-Thumb and
5925 Thumb-to-ARM stubs. */
5926 r_type = ELF32_R_TYPE (irela->r_info);
5927 if ((r_type == (unsigned int) R_ARM_THM_CALL
5928 || r_type == (unsigned int) R_ARM_THM_JUMP24
5929 || r_type == (unsigned int) R_ARM_THM_JUMP19)
5930 && branch_type == ST_BRANCH_TO_ARM)
5931 sprintf (stub_entry->output_name, THUMB2ARM_GLUE_ENTRY_NAME, sym_name);
5932 else if ((r_type == (unsigned int) R_ARM_CALL
5933 || r_type == (unsigned int) R_ARM_JUMP24)
5934 && branch_type == ST_BRANCH_TO_THUMB)
5935 sprintf (stub_entry->output_name, ARM2THUMB_GLUE_ENTRY_NAME, sym_name);
5936 else
5937 sprintf (stub_entry->output_name, STUB_ENTRY_NAME, sym_name);
5938 }
b715f643
TP		 5939
5940 *new_stub = TRUE;
0955507f 5941 return stub_entry;
b715f643
TP		 5942}
5943
4ba2ef8f
TP		 5944/* Scan symbols in INPUT_BFD to identify secure entry functions needing a
5945 gateway veneer to transition from non secure to secure state and create them
5946 accordingly.
5947
5948 "ARMv8-M Security Extensions: Requirements on Development Tools" document
5949 defines the conditions that govern Secure Gateway veneer creation for a
5950 given symbol <SYM> as follows:
5951 - it has function type
5952 - it has non local binding
5953 - a symbol named __acle_se_<SYM> (called special symbol) exists with the
5954 same type, binding and value as <SYM> (called normal symbol).
5955 An entry function can handle secure state transition itself in which case
5956 its special symbol would have a different value from the normal symbol.
5957
5958 OUT_ATTR gives the output attributes, SYM_HASHES the symbol index to hash
5959 entry mapping while HTAB gives the name to hash entry mapping.
0955507f
TP		 5960 *CMSE_STUB_CREATED is increased by the number of secure gateway veneer
5961 created.
4ba2ef8f 5962
0955507f 5963 The return value gives whether a stub failed to be allocated. */
4ba2ef8f
TP		 5964
5965static bfd_boolean
5966cmse_scan (bfd *input_bfd, struct elf32_arm_link_hash_table *htab,
5967 obj_attribute *out_attr, struct elf_link_hash_entry **sym_hashes,
0955507f 5968 int *cmse_stub_created)
4ba2ef8f
TP		 5969{
5970 const struct elf_backend_data *bed;
5971 Elf_Internal_Shdr *symtab_hdr;
5972 unsigned i, j, sym_count, ext_start;
5973 Elf_Internal_Sym *cmse_sym, *local_syms;
5974 struct elf32_arm_link_hash_entry *hash, *cmse_hash = NULL;
5975 enum arm_st_branch_type branch_type;
5976 char *sym_name, *lsym_name;
5977 bfd_vma sym_value;
5978 asection *section;
0955507f
TP		 5979 struct elf32_arm_stub_hash_entry *stub_entry;
5980 bfd_boolean is_v8m, new_stub, cmse_invalid, ret = TRUE;
4ba2ef8f
TP		 5981
5982 bed = get_elf_backend_data (input_bfd);
5983 symtab_hdr = &elf_tdata (input_bfd)->symtab_hdr;
5984 sym_count = symtab_hdr->sh_size / bed->s->sizeof_sym;
5985 ext_start = symtab_hdr->sh_info;
5986 is_v8m = (out_attr[Tag_CPU_arch].i >= TAG_CPU_ARCH_V8M_BASE
5987 && out_attr[Tag_CPU_arch_profile].i == 'M');
5988
5989 local_syms = (Elf_Internal_Sym *) symtab_hdr->contents;
5990 if (local_syms == NULL)
5991 local_syms = bfd_elf_get_elf_syms (input_bfd, symtab_hdr,
5992 symtab_hdr->sh_info, 0, NULL, NULL,
5993 NULL);
5994 if (symtab_hdr->sh_info && local_syms == NULL)
5995 return FALSE;
5996
5997 /* Scan symbols. */
5998 for (i = 0; i < sym_count; i++)
5999 {
6000 cmse_invalid = FALSE;
6001
6002 if (i < ext_start)
6003 {
6004 cmse_sym = &local_syms[i];
6005 /* Not a special symbol. */
6006 if (!ARM_GET_SYM_CMSE_SPCL (cmse_sym->st_target_internal))
6007 continue;
6008 sym_name = bfd_elf_string_from_elf_section (input_bfd,
6009 symtab_hdr->sh_link,
6010 cmse_sym->st_name);
6011 /* Special symbol with local binding. */
6012 cmse_invalid = TRUE;
6013 }
6014 else
6015 {
6016 cmse_hash = elf32_arm_hash_entry (sym_hashes[i - ext_start]);
6017 sym_name = (char *) cmse_hash->root.root.root.string;
6018
6019 /* Not a special symbol. */
6020 if (!ARM_GET_SYM_CMSE_SPCL (cmse_hash->root.target_internal))
6021 continue;
6022
6023 /* Special symbol has incorrect binding or type. */
6024 if ((cmse_hash->root.root.type != bfd_link_hash_defined
6025 && cmse_hash->root.root.type != bfd_link_hash_defweak)
6026 || cmse_hash->root.type != STT_FUNC)
6027 cmse_invalid = TRUE;
6028 }
6029
6030 if (!is_v8m)
6031 {
90b6238f
AM		 6032 _bfd_error_handler (_("%pB: special symbol `%s' only allowed for "
6033 "ARMv8-M architecture or later"),
4eca0228 6034 input_bfd, sym_name);
4ba2ef8f
TP		 6035 is_v8m = TRUE; /* Avoid multiple warning. */
6036 ret = FALSE;
6037 }
6038
6039 if (cmse_invalid)
6040 {
90b6238f
AM		 6041 _bfd_error_handler (_("%pB: invalid special symbol `%s'; it must be"
6042 " a global or weak function symbol"),
4eca0228 6043 input_bfd, sym_name);
4ba2ef8f
TP		 6044 ret = FALSE;
6045 if (i < ext_start)
6046 continue;
6047 }
6048
6049 sym_name += strlen (CMSE_PREFIX);
6050 hash = (struct elf32_arm_link_hash_entry *)
6051 elf_link_hash_lookup (&(htab)->root, sym_name, FALSE, FALSE, TRUE);
6052
6053 /* No associated normal symbol or it is neither global nor weak. */
6054 if (!hash
6055 || (hash->root.root.type != bfd_link_hash_defined
6056 && hash->root.root.type != bfd_link_hash_defweak)
6057 || hash->root.type != STT_FUNC)
6058 {
6059 /* Initialize here to avoid warning about use of possibly
6060 uninitialized variable. */
6061 j = 0;
6062
6063 if (!hash)
6064 {
6065 /* Searching for a normal symbol with local binding. */
6066 for (; j < ext_start; j++)
6067 {
6068 lsym_name =
6069 bfd_elf_string_from_elf_section (input_bfd,
6070 symtab_hdr->sh_link,
6071 local_syms[j].st_name);
6072 if (!strcmp (sym_name, lsym_name))
6073 break;
6074 }
6075 }
6076
6077 if (hash || j < ext_start)
6078 {
4eca0228 6079 _bfd_error_handler
90b6238f
AM		 6080 (_("%pB: invalid standard symbol `%s'; it must be "
6081 "a global or weak function symbol"),
6082 input_bfd, sym_name);
4ba2ef8f
TP		 6083 }
6084 else
4eca0228 6085 _bfd_error_handler
90b6238f 6086 (_("%pB: absent standard symbol `%s'"), input_bfd, sym_name);
4ba2ef8f
TP		 6087 ret = FALSE;
6088 if (!hash)
6089 continue;
6090 }
6091
6092 sym_value = hash->root.root.u.def.value;
6093 section = hash->root.root.u.def.section;
6094
6095 if (cmse_hash->root.root.u.def.section != section)
6096 {
4eca0228 6097 _bfd_error_handler
90b6238f 6098 (_("%pB: `%s' and its special symbol are in different sections"),
4ba2ef8f
TP		 6099 input_bfd, sym_name);
6100 ret = FALSE;
6101 }
6102 if (cmse_hash->root.root.u.def.value != sym_value)
6103 continue; /* Ignore: could be an entry function starting with SG. */
6104
6105 /* If this section is a link-once section that will be discarded, then
6106 don't create any stubs. */
6107 if (section->output_section == NULL)
6108 {
4eca0228 6109 _bfd_error_handler
90b6238f 6110 (_("%pB: entry function `%s' not output"), input_bfd, sym_name);
4ba2ef8f
TP		 6111 continue;
6112 }
6113
6114 if (hash->root.size == 0)
6115 {
4eca0228 6116 _bfd_error_handler
90b6238f 6117 (_("%pB: entry function `%s' is empty"), input_bfd, sym_name);
4ba2ef8f
TP		 6118 ret = FALSE;
6119 }
6120
6121 if (!ret)
6122 continue;
6123 branch_type = ARM_GET_SYM_BRANCH_TYPE (hash->root.target_internal);
0955507f 6124 stub_entry
4ba2ef8f
TP		 6125 = elf32_arm_create_stub (htab, arm_stub_cmse_branch_thumb_only,
6126 NULL, NULL, section, hash, sym_name,
6127 sym_value, branch_type, &new_stub);
6128
0955507f 6129 if (stub_entry == NULL)
4ba2ef8f
TP		 6130 ret = FALSE;
6131 else
6132 {
6133 BFD_ASSERT (new_stub);
0955507f 6134 (*cmse_stub_created)++;
4ba2ef8f
TP		 6135 }
6136 }
6137
6138 if (!symtab_hdr->contents)
6139 free (local_syms);
6140 return ret;
6141}
6142
0955507f
TP		 6143/* Return TRUE iff a symbol identified by its linker HASH entry is a secure
6144 code entry function, ie can be called from non secure code without using a
6145 veneer. */
6146
6147static bfd_boolean
6148cmse_entry_fct_p (struct elf32_arm_link_hash_entry *hash)
6149{
42484486 6150 bfd_byte contents[4];
0955507f
TP		 6151 uint32_t first_insn;
6152 asection *section;
6153 file_ptr offset;
6154 bfd *abfd;
6155
6156 /* Defined symbol of function type. */
6157 if (hash->root.root.type != bfd_link_hash_defined
6158 && hash->root.root.type != bfd_link_hash_defweak)
6159 return FALSE;
6160 if (hash->root.type != STT_FUNC)
6161 return FALSE;
6162
6163 /* Read first instruction. */
6164 section = hash->root.root.u.def.section;
6165 abfd = section->owner;
6166 offset = hash->root.root.u.def.value - section->vma;
42484486
TP		 6167 if (!bfd_get_section_contents (abfd, section, contents, offset,
6168 sizeof (contents)))
0955507f
TP		 6169 return FALSE;
6170
42484486
TP		 6171 first_insn = bfd_get_32 (abfd, contents);
6172
6173 /* Starts by SG instruction. */
0955507f
TP		 6174 return first_insn == 0xe97fe97f;
6175}
6176
6177/* Output the name (in symbol table) of the veneer GEN_ENTRY if it is a new
6178 secure gateway veneers (ie. the veneers was not in the input import library)
6179 and there is no output import library (GEN_INFO->out_implib_bfd is NULL. */
6180
6181static bfd_boolean
6182arm_list_new_cmse_stub (struct bfd_hash_entry *gen_entry, void *gen_info)
6183{
6184 struct elf32_arm_stub_hash_entry *stub_entry;
6185 struct bfd_link_info *info;
6186
6187 /* Massage our args to the form they really have. */
6188 stub_entry = (struct elf32_arm_stub_hash_entry *) gen_entry;
6189 info = (struct bfd_link_info *) gen_info;
6190
6191 if (info->out_implib_bfd)
6192 return TRUE;
6193
6194 if (stub_entry->stub_type != arm_stub_cmse_branch_thumb_only)
6195 return TRUE;
6196
6197 if (stub_entry->stub_offset == (bfd_vma) -1)
4eca0228 6198 _bfd_error_handler (" %s", stub_entry->output_name);
0955507f
TP		 6199
6200 return TRUE;
6201}
6202
6203/* Set offset of each secure gateway veneers so that its address remain
6204 identical to the one in the input import library referred by
6205 HTAB->in_implib_bfd. A warning is issued for veneers that disappeared
6206 (present in input import library but absent from the executable being
6207 linked) or if new veneers appeared and there is no output import library
6208 (INFO->out_implib_bfd is NULL and *CMSE_STUB_CREATED is bigger than the
6209 number of secure gateway veneers found in the input import library.
6210
6211 The function returns whether an error occurred. If no error occurred,
6212 *CMSE_STUB_CREATED gives the number of SG veneers created by both cmse_scan
6213 and this function and HTAB->new_cmse_stub_offset is set to the biggest
6214 veneer observed set for new veneers to be layed out after. */
6215
6216static bfd_boolean
6217set_cmse_veneer_addr_from_implib (struct bfd_link_info *info,
6218 struct elf32_arm_link_hash_table *htab,
6219 int *cmse_stub_created)
6220{
6221 long symsize;
6222 char *sym_name;
6223 flagword flags;
6224 long i, symcount;
6225 bfd *in_implib_bfd;
6226 asection *stub_out_sec;
6227 bfd_boolean ret = TRUE;
6228 Elf_Internal_Sym *intsym;
6229 const char *out_sec_name;
6230 bfd_size_type cmse_stub_size;
6231 asymbol **sympp = NULL, *sym;
6232 struct elf32_arm_link_hash_entry *hash;
6233 const insn_sequence *cmse_stub_template;
6234 struct elf32_arm_stub_hash_entry *stub_entry;
6235 int cmse_stub_template_size, new_cmse_stubs_created = *cmse_stub_created;
6236 bfd_vma veneer_value, stub_offset, next_cmse_stub_offset;
6237 bfd_vma cmse_stub_array_start = (bfd_vma) -1, cmse_stub_sec_vma = 0;
6238
6239 /* No input secure gateway import library. */
6240 if (!htab->in_implib_bfd)
6241 return TRUE;
6242
6243 in_implib_bfd = htab->in_implib_bfd;
6244 if (!htab->cmse_implib)
6245 {
871b3ab2 6246 _bfd_error_handler (_("%pB: --in-implib only supported for Secure "
90b6238f 6247 "Gateway import libraries"), in_implib_bfd);
0955507f
TP		 6248 return FALSE;
6249 }
6250
6251 /* Get symbol table size. */
6252 symsize = bfd_get_symtab_upper_bound (in_implib_bfd);
6253 if (symsize < 0)
6254 return FALSE;
6255
6256 /* Read in the input secure gateway import library's symbol table. */
6257 sympp = (asymbol **) xmalloc (symsize);
6258 symcount = bfd_canonicalize_symtab (in_implib_bfd, sympp);
6259 if (symcount < 0)
6260 {
6261 ret = FALSE;
6262 goto free_sym_buf;
6263 }
6264
6265 htab->new_cmse_stub_offset = 0;
6266 cmse_stub_size =
6267 find_stub_size_and_template (arm_stub_cmse_branch_thumb_only,
6268 &cmse_stub_template,
6269 &cmse_stub_template_size);
6270 out_sec_name =
6271 arm_dedicated_stub_output_section_name (arm_stub_cmse_branch_thumb_only);
6272 stub_out_sec =
6273 bfd_get_section_by_name (htab->obfd, out_sec_name);
6274 if (stub_out_sec != NULL)
6275 cmse_stub_sec_vma = stub_out_sec->vma;
6276
6277 /* Set addresses of veneers mentionned in input secure gateway import
6278 library's symbol table. */
6279 for (i = 0; i < symcount; i++)
6280 {
6281 sym = sympp[i];
6282 flags = sym->flags;
6283 sym_name = (char *) bfd_asymbol_name (sym);
6284 intsym = &((elf_symbol_type *) sym)->internal_elf_sym;
6285
6286 if (sym->section != bfd_abs_section_ptr
6287 || !(flags & (BSF_GLOBAL | BSF_WEAK))
6288 || (flags & BSF_FUNCTION) != BSF_FUNCTION
6289 || (ARM_GET_SYM_BRANCH_TYPE (intsym->st_target_internal)
6290 != ST_BRANCH_TO_THUMB))
6291 {
90b6238f
AM		 6292 _bfd_error_handler (_("%pB: invalid import library entry: `%s'; "
6293 "symbol should be absolute, global and "
6294 "refer to Thumb functions"),
4eca0228 6295 in_implib_bfd, sym_name);
0955507f
TP		 6296 ret = FALSE;
6297 continue;
6298 }
6299
6300 veneer_value = bfd_asymbol_value (sym);
6301 stub_offset = veneer_value - cmse_stub_sec_vma;
6302 stub_entry = arm_stub_hash_lookup (&htab->stub_hash_table, sym_name,
6303 FALSE, FALSE);
6304 hash = (struct elf32_arm_link_hash_entry *)
6305 elf_link_hash_lookup (&(htab)->root, sym_name, FALSE, FALSE, TRUE);
6306
6307 /* Stub entry should have been created by cmse_scan or the symbol be of
6308 a secure function callable from non secure code. */
6309 if (!stub_entry && !hash)
6310 {
6311 bfd_boolean new_stub;
6312
4eca0228 6313 _bfd_error_handler
90b6238f 6314 (_("entry function `%s' disappeared from secure code"), sym_name);
0955507f
TP		 6315 hash = (struct elf32_arm_link_hash_entry *)
6316 elf_link_hash_lookup (&(htab)->root, sym_name, TRUE, TRUE, TRUE);
6317 stub_entry
6318 = elf32_arm_create_stub (htab, arm_stub_cmse_branch_thumb_only,
6319 NULL, NULL, bfd_abs_section_ptr, hash,
6320 sym_name, veneer_value,
6321 ST_BRANCH_TO_THUMB, &new_stub);
6322 if (stub_entry == NULL)
6323 ret = FALSE;
6324 else
6325 {
6326 BFD_ASSERT (new_stub);
6327 new_cmse_stubs_created++;
6328 (*cmse_stub_created)++;
6329 }
6330 stub_entry->stub_template_size = stub_entry->stub_size = 0;
6331 stub_entry->stub_offset = stub_offset;
6332 }
6333 /* Symbol found is not callable from non secure code. */
6334 else if (!stub_entry)
6335 {
6336 if (!cmse_entry_fct_p (hash))
6337 {
90b6238f 6338 _bfd_error_handler (_("`%s' refers to a non entry function"),
4eca0228 6339 sym_name);
0955507f
TP		 6340 ret = FALSE;
6341 }
6342 continue;
6343 }
6344 else
6345 {
6346 /* Only stubs for SG veneers should have been created. */
6347 BFD_ASSERT (stub_entry->stub_type == arm_stub_cmse_branch_thumb_only);
6348
6349 /* Check visibility hasn't changed. */
6350 if (!!(flags & BSF_GLOBAL)
6351 != (hash->root.root.type == bfd_link_hash_defined))
4eca0228 6352 _bfd_error_handler
90b6238f 6353 (_("%pB: visibility of symbol `%s' has changed"), in_implib_bfd,
0955507f
TP		 6354 sym_name);
6355
6356 stub_entry->stub_offset = stub_offset;
6357 }
6358
6359 /* Size should match that of a SG veneer. */
6360 if (intsym->st_size != cmse_stub_size)
6361 {
90b6238f 6362 _bfd_error_handler (_("%pB: incorrect size for symbol `%s'"),
4eca0228 6363 in_implib_bfd, sym_name);
0955507f
TP		 6364 ret = FALSE;
6365 }
6366
6367 /* Previous veneer address is before current SG veneer section. */
6368 if (veneer_value < cmse_stub_sec_vma)
6369 {
6370 /* Avoid offset underflow. */
6371 if (stub_entry)
6372 stub_entry->stub_offset = 0;
6373 stub_offset = 0;
6374 ret = FALSE;
6375 }
6376
6377 /* Complain if stub offset not a multiple of stub size. */
6378 if (stub_offset % cmse_stub_size)
6379 {
4eca0228 6380 _bfd_error_handler
90b6238f
AM		 6381 (_("offset of veneer for entry function `%s' not a multiple of "
6382 "its size"), sym_name);
0955507f
TP		 6383 ret = FALSE;
6384 }
6385
6386 if (!ret)
6387 continue;
6388
6389 new_cmse_stubs_created--;
6390 if (veneer_value < cmse_stub_array_start)
6391 cmse_stub_array_start = veneer_value;
6392 next_cmse_stub_offset = stub_offset + ((cmse_stub_size + 7) & ~7);
6393 if (next_cmse_stub_offset > htab->new_cmse_stub_offset)
6394 htab->new_cmse_stub_offset = next_cmse_stub_offset;
6395 }
6396
6397 if (!info->out_implib_bfd && new_cmse_stubs_created != 0)
6398 {
6399 BFD_ASSERT (new_cmse_stubs_created > 0);
4eca0228 6400 _bfd_error_handler
0955507f
TP		 6401 (_("new entry function(s) introduced but no output import library "
6402 "specified:"));
6403 bfd_hash_traverse (&htab->stub_hash_table, arm_list_new_cmse_stub, info);
6404 }
6405
6406 if (cmse_stub_array_start != cmse_stub_sec_vma)
6407 {
4eca0228 6408 _bfd_error_handler
90b6238f 6409 (_("start address of `%s' is different from previous link"),
0955507f
TP		 6410 out_sec_name);
6411 ret = FALSE;
6412 }
6413
6414free_sym_buf:
6415 free (sympp);
6416 return ret;
6417}
6418
906e58ca
NC		 6419/* Determine and set the size of the stub section for a final link.
6420
6421 The basic idea here is to examine all the relocations looking for
6422 PC-relative calls to a target that is unreachable with a "bl"
6423 instruction. */
6424
6425bfd_boolean
6426elf32_arm_size_stubs (bfd *output_bfd,
6427 bfd *stub_bfd,
6428 struct bfd_link_info *info,
6429 bfd_signed_vma group_size,
7a89b94e 6430 asection * (*add_stub_section) (const char *, asection *,
6bde4c52 6431 asection *,
7a89b94e 6432 unsigned int),
906e58ca
NC		 6433 void (*layout_sections_again) (void))
6434{
0955507f 6435 bfd_boolean ret = TRUE;
4ba2ef8f 6436 obj_attribute *out_attr;
0955507f 6437 int cmse_stub_created = 0;
906e58ca 6438 bfd_size_type stub_group_size;
4ba2ef8f 6439 bfd_boolean m_profile, stubs_always_after_branch, first_veneer_scan = TRUE;
906e58ca 6440 struct elf32_arm_link_hash_table *htab = elf32_arm_hash_table (info);
48229727 6441 struct a8_erratum_fix *a8_fixes = NULL;
eb7c4339 6442 unsigned int num_a8_fixes = 0, a8_fix_table_size = 10;
48229727
JB		 6443 struct a8_erratum_reloc *a8_relocs = NULL;
6444 unsigned int num_a8_relocs = 0, a8_reloc_table_size = 10, i;
6445
4dfe6ac6
NC		 6446 if (htab == NULL)
6447 return FALSE;
6448
48229727
JB		 6449 if (htab->fix_cortex_a8)
6450 {
21d799b5 6451 a8_fixes = (struct a8_erratum_fix *)
99059e56 6452 bfd_zmalloc (sizeof (struct a8_erratum_fix) * a8_fix_table_size);
21d799b5 6453 a8_relocs = (struct a8_erratum_reloc *)
99059e56 6454 bfd_zmalloc (sizeof (struct a8_erratum_reloc) * a8_reloc_table_size);
48229727 6455 }
906e58ca
NC		 6456
6457 /* Propagate mach to stub bfd, because it may not have been
6458 finalized when we created stub_bfd. */
6459 bfd_set_arch_mach (stub_bfd, bfd_get_arch (output_bfd),
6460 bfd_get_mach (output_bfd));
6461
6462 /* Stash our params away. */
6463 htab->stub_bfd = stub_bfd;
6464 htab->add_stub_section = add_stub_section;
6465 htab->layout_sections_again = layout_sections_again;
07d72278 6466 stubs_always_after_branch = group_size < 0;
48229727 6467
4ba2ef8f
TP		 6468 out_attr = elf_known_obj_attributes_proc (output_bfd);
6469 m_profile = out_attr[Tag_CPU_arch_profile].i == 'M';
0955507f 6470
48229727
JB		 6471 /* The Cortex-A8 erratum fix depends on stubs not being in the same 4K page
6472 as the first half of a 32-bit branch straddling two 4K pages. This is a
6473 crude way of enforcing that. */
6474 if (htab->fix_cortex_a8)
6475 stubs_always_after_branch = 1;
6476
906e58ca
NC		 6477 if (group_size < 0)
6478 stub_group_size = -group_size;
6479 else
6480 stub_group_size = group_size;
6481
6482 if (stub_group_size == 1)
6483 {
6484 /* Default values. */
6485 /* Thumb branch range is +-4MB has to be used as the default
6486 maximum size (a given section can contain both ARM and Thumb
6487 code, so the worst case has to be taken into account).
6488
6489 This value is 24K less than that, which allows for 2025
6490 12-byte stubs. If we exceed that, then we will fail to link.
6491 The user will have to relink with an explicit group size
6492 option. */
6493 stub_group_size = 4170000;
6494 }
6495
07d72278 6496 group_sections (htab, stub_group_size, stubs_always_after_branch);
906e58ca 6497
3ae046cc
NS		 6498 /* If we're applying the cortex A8 fix, we need to determine the
6499 program header size now, because we cannot change it later --
6500 that could alter section placements. Notice the A8 erratum fix
6501 ends up requiring the section addresses to remain unchanged
6502 modulo the page size. That's something we cannot represent
6503 inside BFD, and we don't want to force the section alignment to
6504 be the page size. */
6505 if (htab->fix_cortex_a8)
6506 (*htab->layout_sections_again) ();
6507
906e58ca
NC		 6508 while (1)
6509 {
6510 bfd *input_bfd;
6511 unsigned int bfd_indx;
6512 asection *stub_sec;
d7c5bd02 6513 enum elf32_arm_stub_type stub_type;
eb7c4339
NS		 6514 bfd_boolean stub_changed = FALSE;
6515 unsigned prev_num_a8_fixes = num_a8_fixes;
906e58ca 6516
48229727 6517 num_a8_fixes = 0;
906e58ca
NC		 6518 for (input_bfd = info->input_bfds, bfd_indx = 0;
6519 input_bfd != NULL;
c72f2fb2 6520 input_bfd = input_bfd->link.next, bfd_indx++)
906e58ca
NC		 6521 {
6522 Elf_Internal_Shdr *symtab_hdr;
6523 asection *section;
6524 Elf_Internal_Sym *local_syms = NULL;
6525
8c246a60
AM		 6526 if (!is_arm_elf (input_bfd)
6527 || (elf_dyn_lib_class (input_bfd) & DYN_AS_NEEDED) != 0)
99059e56 6528 continue;
adbcc655 6529
48229727
JB		 6530 num_a8_relocs = 0;
6531
906e58ca
NC		 6532 /* We'll need the symbol table in a second. */
6533 symtab_hdr = &elf_tdata (input_bfd)->symtab_hdr;
6534 if (symtab_hdr->sh_info == 0)
6535 continue;
6536
4ba2ef8f
TP		 6537 /* Limit scan of symbols to object file whose profile is
6538 Microcontroller to not hinder performance in the general case. */
6539 if (m_profile && first_veneer_scan)
6540 {
6541 struct elf_link_hash_entry **sym_hashes;
6542
6543 sym_hashes = elf_sym_hashes (input_bfd);
6544 if (!cmse_scan (input_bfd, htab, out_attr, sym_hashes,
0955507f 6545 &cmse_stub_created))
4ba2ef8f 6546 goto error_ret_free_local;
0955507f
TP		 6547
6548 if (cmse_stub_created != 0)
6549 stub_changed = TRUE;
4ba2ef8f
TP		 6550 }
6551
906e58ca
NC		 6552 /* Walk over each section attached to the input bfd. */
6553 for (section = input_bfd->sections;
6554 section != NULL;
6555 section = section->next)
6556 {
6557 Elf_Internal_Rela *internal_relocs, *irelaend, *irela;
6558
6559 /* If there aren't any relocs, then there's nothing more
6560 to do. */
6561 if ((section->flags & SEC_RELOC) == 0
6562 || section->reloc_count == 0
6563 || (section->flags & SEC_CODE) == 0)
6564 continue;
6565
6566 /* If this section is a link-once section that will be
6567 discarded, then don't create any stubs. */
6568 if (section->output_section == NULL
6569 || section->output_section->owner != output_bfd)
6570 continue;
6571
6572 /* Get the relocs. */
6573 internal_relocs
6574 = _bfd_elf_link_read_relocs (input_bfd, section, NULL,
6575 NULL, info->keep_memory);
6576 if (internal_relocs == NULL)
6577 goto error_ret_free_local;
6578
6579 /* Now examine each relocation. */
6580 irela = internal_relocs;
6581 irelaend = irela + section->reloc_count;
6582 for (; irela < irelaend; irela++)
6583 {
6584 unsigned int r_type, r_indx;
906e58ca
NC		 6585 asection *sym_sec;
6586 bfd_vma sym_value;
6587 bfd_vma destination;
6588 struct elf32_arm_link_hash_entry *hash;
7413f23f 6589 const char *sym_name;
34e77a92 6590 unsigned char st_type;
35fc36a8 6591 enum arm_st_branch_type branch_type;
48229727 6592 bfd_boolean created_stub = FALSE;
906e58ca
NC		 6593
6594 r_type = ELF32_R_TYPE (irela->r_info);
6595 r_indx = ELF32_R_SYM (irela->r_info);
6596
6597 if (r_type >= (unsigned int) R_ARM_max)
6598 {
6599 bfd_set_error (bfd_error_bad_value);
6600 error_ret_free_internal:
6601 if (elf_section_data (section)->relocs == NULL)
6602 free (internal_relocs);
15dd01b1
TP		 6603 /* Fall through. */
6604 error_ret_free_local:
6605 if (local_syms != NULL
6606 && (symtab_hdr->contents
6607 != (unsigned char *) local_syms))
6608 free (local_syms);
6609 return FALSE;
906e58ca 6610 }
b38cadfb 6611
0855e32b
NS		 6612 hash = NULL;
6613 if (r_indx >= symtab_hdr->sh_info)
6614 hash = elf32_arm_hash_entry
6615 (elf_sym_hashes (input_bfd)
6616 [r_indx - symtab_hdr->sh_info]);
b38cadfb 6617
0855e32b
NS		 6618 /* Only look for stubs on branch instructions, or
6619 non-relaxed TLSCALL */
906e58ca 6620 if ((r_type != (unsigned int) R_ARM_CALL)
155d87d7
CL		 6621 && (r_type != (unsigned int) R_ARM_THM_CALL)
6622 && (r_type != (unsigned int) R_ARM_JUMP24)
48229727
JB		 6623 && (r_type != (unsigned int) R_ARM_THM_JUMP19)
6624 && (r_type != (unsigned int) R_ARM_THM_XPC22)
155d87d7 6625 && (r_type != (unsigned int) R_ARM_THM_JUMP24)
0855e32b
NS		 6626 && (r_type != (unsigned int) R_ARM_PLT32)
6627 && !((r_type == (unsigned int) R_ARM_TLS_CALL
6628 || r_type == (unsigned int) R_ARM_THM_TLS_CALL)
6629 && r_type == elf32_arm_tls_transition
6630 (info, r_type, &hash->root)
6631 && ((hash ? hash->tls_type
6632 : (elf32_arm_local_got_tls_type
6633 (input_bfd)[r_indx]))
6634 & GOT_TLS_GDESC) != 0))
906e58ca
NC		 6635 continue;
6636
6637 /* Now determine the call target, its name, value,
6638 section. */
6639 sym_sec = NULL;
6640 sym_value = 0;
6641 destination = 0;
7413f23f 6642 sym_name = NULL;
b38cadfb 6643
0855e32b
NS		 6644 if (r_type == (unsigned int) R_ARM_TLS_CALL
6645 || r_type == (unsigned int) R_ARM_THM_TLS_CALL)
6646 {
6647 /* A non-relaxed TLS call. The target is the
6648 plt-resident trampoline and nothing to do
6649 with the symbol. */
6650 BFD_ASSERT (htab->tls_trampoline > 0);
6651 sym_sec = htab->root.splt;
6652 sym_value = htab->tls_trampoline;
6653 hash = 0;
34e77a92 6654 st_type = STT_FUNC;
35fc36a8 6655 branch_type = ST_BRANCH_TO_ARM;
0855e32b
NS		 6656 }
6657 else if (!hash)
906e58ca
NC		 6658 {
6659 /* It's a local symbol. */
6660 Elf_Internal_Sym *sym;
906e58ca
NC		 6661
6662 if (local_syms == NULL)
6663 {
6664 local_syms
6665 = (Elf_Internal_Sym *) symtab_hdr->contents;
6666 if (local_syms == NULL)
6667 local_syms
6668 = bfd_elf_get_elf_syms (input_bfd, symtab_hdr,
6669 symtab_hdr->sh_info, 0,
6670 NULL, NULL, NULL);
6671 if (local_syms == NULL)
6672 goto error_ret_free_internal;
6673 }
6674
6675 sym = local_syms + r_indx;
f6d250ce
TS		 6676 if (sym->st_shndx == SHN_UNDEF)
6677 sym_sec = bfd_und_section_ptr;
6678 else if (sym->st_shndx == SHN_ABS)
6679 sym_sec = bfd_abs_section_ptr;
6680 else if (sym->st_shndx == SHN_COMMON)
6681 sym_sec = bfd_com_section_ptr;
6682 else
6683 sym_sec =
6684 bfd_section_from_elf_index (input_bfd, sym->st_shndx);
6685
ffcb4889
NS		 6686 if (!sym_sec)
6687 /* This is an undefined symbol. It can never
6a631e86 6688 be resolved. */
ffcb4889 6689 continue;
fe33d2fa 6690
906e58ca
NC		 6691 if (ELF_ST_TYPE (sym->st_info) != STT_SECTION)
6692 sym_value = sym->st_value;
6693 destination = (sym_value + irela->r_addend
6694 + sym_sec->output_offset
6695 + sym_sec->output_section->vma);
34e77a92 6696 st_type = ELF_ST_TYPE (sym->st_info);
39d911fc
TP		 6697 branch_type =
6698 ARM_GET_SYM_BRANCH_TYPE (sym->st_target_internal);
7413f23f
DJ		 6699 sym_name
6700 = bfd_elf_string_from_elf_section (input_bfd,
6701 symtab_hdr->sh_link,
6702 sym->st_name);
906e58ca
NC		 6703 }
6704 else
6705 {
6706 /* It's an external symbol. */
906e58ca
NC		 6707 while (hash->root.root.type == bfd_link_hash_indirect
6708 || hash->root.root.type == bfd_link_hash_warning)
6709 hash = ((struct elf32_arm_link_hash_entry *)
6710 hash->root.root.u.i.link);
6711
6712 if (hash->root.root.type == bfd_link_hash_defined
6713 || hash->root.root.type == bfd_link_hash_defweak)
6714 {
6715 sym_sec = hash->root.root.u.def.section;
6716 sym_value = hash->root.root.u.def.value;
022f8312
CL		 6717
6718 struct elf32_arm_link_hash_table *globals =
6719 elf32_arm_hash_table (info);
6720
6721 /* For a destination in a shared library,
6722 use the PLT stub as target address to
6723 decide whether a branch stub is
6724 needed. */
4dfe6ac6 6725 if (globals != NULL
362d30a1 6726 && globals->root.splt != NULL
4dfe6ac6 6727 && hash != NULL
022f8312
CL		 6728 && hash->root.plt.offset != (bfd_vma) -1)
6729 {
362d30a1 6730 sym_sec = globals->root.splt;
022f8312
CL		 6731 sym_value = hash->root.plt.offset;
6732 if (sym_sec->output_section != NULL)
6733 destination = (sym_value
6734 + sym_sec->output_offset
6735 + sym_sec->output_section->vma);
6736 }
6737 else if (sym_sec->output_section != NULL)
906e58ca
NC		 6738 destination = (sym_value + irela->r_addend
6739 + sym_sec->output_offset
6740 + sym_sec->output_section->vma);
6741 }
69c5861e
CL		 6742 else if ((hash->root.root.type == bfd_link_hash_undefined)
6743 || (hash->root.root.type == bfd_link_hash_undefweak))
6744 {
6745 /* For a shared library, use the PLT stub as
6746 target address to decide whether a long
6747 branch stub is needed.
6748 For absolute code, they cannot be handled. */
6749 struct elf32_arm_link_hash_table *globals =
6750 elf32_arm_hash_table (info);
6751
4dfe6ac6 6752 if (globals != NULL
362d30a1 6753 && globals->root.splt != NULL
4dfe6ac6 6754 && hash != NULL
69c5861e
CL		 6755 && hash->root.plt.offset != (bfd_vma) -1)
6756 {
362d30a1 6757 sym_sec = globals->root.splt;
69c5861e
CL		 6758 sym_value = hash->root.plt.offset;
6759 if (sym_sec->output_section != NULL)
6760 destination = (sym_value
6761 + sym_sec->output_offset
6762 + sym_sec->output_section->vma);
6763 }
6764 else
6765 continue;
6766 }
906e58ca
NC		 6767 else
6768 {
6769 bfd_set_error (bfd_error_bad_value);
6770 goto error_ret_free_internal;
6771 }
34e77a92 6772 st_type = hash->root.type;
39d911fc
TP		 6773 branch_type =
6774 ARM_GET_SYM_BRANCH_TYPE (hash->root.target_internal);
7413f23f 6775 sym_name = hash->root.root.root.string;
906e58ca
NC		 6776 }
6777
48229727 6778 do
7413f23f 6779 {
b715f643 6780 bfd_boolean new_stub;
0955507f 6781 struct elf32_arm_stub_hash_entry *stub_entry;
b715f643 6782
48229727
JB		 6783 /* Determine what (if any) linker stub is needed. */
6784 stub_type = arm_type_of_stub (info, section, irela,
34e77a92
RS		 6785 st_type, &branch_type,
6786 hash, destination, sym_sec,
48229727
JB		 6787 input_bfd, sym_name);
6788 if (stub_type == arm_stub_none)
6789 break;
6790
48229727
JB		 6791 /* We've either created a stub for this reloc already,
6792 or we are about to. */
0955507f 6793 stub_entry =
b715f643
TP		 6794 elf32_arm_create_stub (htab, stub_type, section, irela,
6795 sym_sec, hash,
6796 (char *) sym_name, sym_value,
6797 branch_type, &new_stub);
7413f23f 6798
0955507f 6799 created_stub = stub_entry != NULL;
b715f643
TP		 6800 if (!created_stub)
6801 goto error_ret_free_internal;
6802 else if (!new_stub)
6803 break;
99059e56 6804 else
b715f643 6805 stub_changed = TRUE;
99059e56
RM		 6806 }
6807 while (0);
6808
6809 /* Look for relocations which might trigger Cortex-A8
6810 erratum. */
6811 if (htab->fix_cortex_a8
6812 && (r_type == (unsigned int) R_ARM_THM_JUMP24
6813 || r_type == (unsigned int) R_ARM_THM_JUMP19
6814 || r_type == (unsigned int) R_ARM_THM_CALL
6815 || r_type == (unsigned int) R_ARM_THM_XPC22))
6816 {
6817 bfd_vma from = section->output_section->vma
6818 + section->output_offset
6819 + irela->r_offset;
6820
6821 if ((from & 0xfff) == 0xffe)
6822 {
6823 /* Found a candidate. Note we haven't checked the
6824 destination is within 4K here: if we do so (and
6825 don't create an entry in a8_relocs) we can't tell
6826 that a branch should have been relocated when
6827 scanning later. */
6828 if (num_a8_relocs == a8_reloc_table_size)
6829 {
6830 a8_reloc_table_size *= 2;
6831 a8_relocs = (struct a8_erratum_reloc *)
6832 bfd_realloc (a8_relocs,
6833 sizeof (struct a8_erratum_reloc)
6834 * a8_reloc_table_size);
6835 }
6836
6837 a8_relocs[num_a8_relocs].from = from;
6838 a8_relocs[num_a8_relocs].destination = destination;
6839 a8_relocs[num_a8_relocs].r_type = r_type;
6840 a8_relocs[num_a8_relocs].branch_type = branch_type;
6841 a8_relocs[num_a8_relocs].sym_name = sym_name;
6842 a8_relocs[num_a8_relocs].non_a8_stub = created_stub;
6843 a8_relocs[num_a8_relocs].hash = hash;
6844
6845 num_a8_relocs++;
6846 }
6847 }
906e58ca
NC		 6848 }
6849
99059e56
RM		 6850 /* We're done with the internal relocs, free them. */
6851 if (elf_section_data (section)->relocs == NULL)
6852 free (internal_relocs);
6853 }
48229727 6854
99059e56 6855 if (htab->fix_cortex_a8)
48229727 6856 {
99059e56
RM		 6857 /* Sort relocs which might apply to Cortex-A8 erratum. */
6858 qsort (a8_relocs, num_a8_relocs,
eb7c4339 6859 sizeof (struct a8_erratum_reloc),
99059e56 6860 &a8_reloc_compare);
48229727 6861
99059e56
RM		 6862 /* Scan for branches which might trigger Cortex-A8 erratum. */
6863 if (cortex_a8_erratum_scan (input_bfd, info, &a8_fixes,
48229727 6864 &num_a8_fixes, &a8_fix_table_size,
eb7c4339
NS		 6865 a8_relocs, num_a8_relocs,
6866 prev_num_a8_fixes, &stub_changed)
6867 != 0)
48229727 6868 goto error_ret_free_local;
5e681ec4 6869 }
7f991970
AM		 6870
6871 if (local_syms != NULL
6872 && symtab_hdr->contents != (unsigned char *) local_syms)
6873 {
6874 if (!info->keep_memory)
6875 free (local_syms);
6876 else
6877 symtab_hdr->contents = (unsigned char *) local_syms;
6878 }
5e681ec4
PB		 6879 }
6880
0955507f
TP		 6881 if (first_veneer_scan
6882 && !set_cmse_veneer_addr_from_implib (info, htab,
6883 &cmse_stub_created))
6884 ret = FALSE;
6885
eb7c4339 6886 if (prev_num_a8_fixes != num_a8_fixes)
99059e56 6887 stub_changed = TRUE;
48229727 6888
906e58ca
NC		 6889 if (!stub_changed)
6890 break;
5e681ec4 6891
906e58ca
NC		 6892 /* OK, we've added some stubs. Find out the new size of the
6893 stub sections. */
6894 for (stub_sec = htab->stub_bfd->sections;
6895 stub_sec != NULL;
6896 stub_sec = stub_sec->next)
3e6b1042
DJ		 6897 {
6898 /* Ignore non-stub sections. */
6899 if (!strstr (stub_sec->name, STUB_SUFFIX))
6900 continue;
6901
6902 stub_sec->size = 0;
6903 }
b34b2d70 6904
0955507f
TP		 6905 /* Add new SG veneers after those already in the input import
6906 library. */
6907 for (stub_type = arm_stub_none + 1; stub_type < max_stub_type;
6908 stub_type++)
6909 {
6910 bfd_vma *start_offset_p;
6911 asection **stub_sec_p;
6912
6913 start_offset_p = arm_new_stubs_start_offset_ptr (htab, stub_type);
6914 stub_sec_p = arm_dedicated_stub_input_section_ptr (htab, stub_type);
6915 if (start_offset_p == NULL)
6916 continue;
6917
6918 BFD_ASSERT (stub_sec_p != NULL);
6919 if (*stub_sec_p != NULL)
6920 (*stub_sec_p)->size = *start_offset_p;
6921 }
6922
d7c5bd02 6923 /* Compute stub section size, considering padding. */
906e58ca 6924 bfd_hash_traverse (&htab->stub_hash_table, arm_size_one_stub, htab);
d7c5bd02
TP		 6925 for (stub_type = arm_stub_none + 1; stub_type < max_stub_type;
6926 stub_type++)
6927 {
6928 int size, padding;
6929 asection **stub_sec_p;
6930
6931 padding = arm_dedicated_stub_section_padding (stub_type);
6932 stub_sec_p = arm_dedicated_stub_input_section_ptr (htab, stub_type);
6933 /* Skip if no stub input section or no stub section padding
6934 required. */
6935 if ((stub_sec_p != NULL && *stub_sec_p == NULL) || padding == 0)
6936 continue;
6937 /* Stub section padding required but no dedicated section. */
6938 BFD_ASSERT (stub_sec_p);
6939
6940 size = (*stub_sec_p)->size;
6941 size = (size + padding - 1) & ~(padding - 1);
6942 (*stub_sec_p)->size = size;
6943 }
906e58ca 6944
48229727
JB		 6945 /* Add Cortex-A8 erratum veneers to stub section sizes too. */
6946 if (htab->fix_cortex_a8)
99059e56
RM		 6947 for (i = 0; i < num_a8_fixes; i++)
6948 {
48229727 6949 stub_sec = elf32_arm_create_or_find_stub_sec (NULL,
daa4adae 6950 a8_fixes[i].section, htab, a8_fixes[i].stub_type);
48229727
JB		 6951
6952 if (stub_sec == NULL)
7f991970 6953 return FALSE;
48229727 6954
99059e56
RM		 6955 stub_sec->size
6956 += find_stub_size_and_template (a8_fixes[i].stub_type, NULL,
6957 NULL);
6958 }
48229727
JB		 6959
6960
906e58ca
NC		 6961 /* Ask the linker to do its stuff. */
6962 (*htab->layout_sections_again) ();
4ba2ef8f 6963 first_veneer_scan = FALSE;
ba93b8ac
DJ		 6964 }
6965
48229727
JB		 6966 /* Add stubs for Cortex-A8 erratum fixes now. */
6967 if (htab->fix_cortex_a8)
6968 {
6969 for (i = 0; i < num_a8_fixes; i++)
99059e56
RM		 6970 {
6971 struct elf32_arm_stub_hash_entry *stub_entry;
6972 char *stub_name = a8_fixes[i].stub_name;
6973 asection *section = a8_fixes[i].section;
6974 unsigned int section_id = a8_fixes[i].section->id;
6975 asection *link_sec = htab->stub_group[section_id].link_sec;
6976 asection *stub_sec = htab->stub_group[section_id].stub_sec;
6977 const insn_sequence *template_sequence;
6978 int template_size, size = 0;
6979
6980 stub_entry = arm_stub_hash_lookup (&htab->stub_hash_table, stub_name,
6981 TRUE, FALSE);
6982 if (stub_entry == NULL)
6983 {
871b3ab2 6984 _bfd_error_handler (_("%pB: cannot create stub entry %s"),
4eca0228 6985 section->owner, stub_name);
99059e56
RM		 6986 return FALSE;
6987 }
6988
6989 stub_entry->stub_sec = stub_sec;
0955507f 6990 stub_entry->stub_offset = (bfd_vma) -1;
99059e56
RM		 6991 stub_entry->id_sec = link_sec;
6992 stub_entry->stub_type = a8_fixes[i].stub_type;
8d9d9490 6993 stub_entry->source_value = a8_fixes[i].offset;
99059e56 6994 stub_entry->target_section = a8_fixes[i].section;
8d9d9490 6995 stub_entry->target_value = a8_fixes[i].target_offset;
99059e56 6996 stub_entry->orig_insn = a8_fixes[i].orig_insn;
35fc36a8 6997 stub_entry->branch_type = a8_fixes[i].branch_type;
48229727 6998
99059e56
RM		 6999 size = find_stub_size_and_template (a8_fixes[i].stub_type,
7000 &template_sequence,
7001 &template_size);
48229727 7002
99059e56
RM		 7003 stub_entry->stub_size = size;
7004 stub_entry->stub_template = template_sequence;
7005 stub_entry->stub_template_size = template_size;
7006 }
48229727
JB		 7007
7008 /* Stash the Cortex-A8 erratum fix array for use later in
99059e56 7009 elf32_arm_write_section(). */
48229727
JB		 7010 htab->a8_erratum_fixes = a8_fixes;
7011 htab->num_a8_erratum_fixes = num_a8_fixes;
7012 }
7013 else
7014 {
7015 htab->a8_erratum_fixes = NULL;
7016 htab->num_a8_erratum_fixes = 0;
7017 }
0955507f 7018 return ret;
5e681ec4
PB		 7019}
7020
906e58ca
NC		 7021/* Build all the stubs associated with the current output file. The
7022 stubs are kept in a hash table attached to the main linker hash
7023 table. We also set up the .plt entries for statically linked PIC
7024 functions here. This function is called via arm_elf_finish in the
7025 linker. */
252b5132 7026
906e58ca
NC		 7027bfd_boolean
7028elf32_arm_build_stubs (struct bfd_link_info *info)
252b5132 7029{
906e58ca
NC		 7030 asection *stub_sec;
7031 struct bfd_hash_table *table;
0955507f 7032 enum elf32_arm_stub_type stub_type;
906e58ca 7033 struct elf32_arm_link_hash_table *htab;
252b5132 7034
906e58ca 7035 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 7036 if (htab == NULL)
7037 return FALSE;
252b5132 7038
906e58ca
NC		 7039 for (stub_sec = htab->stub_bfd->sections;
7040 stub_sec != NULL;
7041 stub_sec = stub_sec->next)
252b5132 7042 {
906e58ca
NC		 7043 bfd_size_type size;
7044
8029a119 7045 /* Ignore non-stub sections. */
906e58ca
NC		 7046 if (!strstr (stub_sec->name, STUB_SUFFIX))
7047 continue;
7048
d7c5bd02 7049 /* Allocate memory to hold the linker stubs. Zeroing the stub sections
0955507f
TP		 7050 must at least be done for stub section requiring padding and for SG
7051 veneers to ensure that a non secure code branching to a removed SG
7052 veneer causes an error. */
906e58ca 7053 size = stub_sec->size;
21d799b5 7054 stub_sec->contents = (unsigned char *) bfd_zalloc (htab->stub_bfd, size);
906e58ca
NC		 7055 if (stub_sec->contents == NULL && size != 0)
7056 return FALSE;
0955507f 7057
906e58ca 7058 stub_sec->size = 0;
252b5132
RH		 7059 }
7060
0955507f
TP		 7061 /* Add new SG veneers after those already in the input import library. */
7062 for (stub_type = arm_stub_none + 1; stub_type < max_stub_type; stub_type++)
7063 {
7064 bfd_vma *start_offset_p;
7065 asection **stub_sec_p;
7066
7067 start_offset_p = arm_new_stubs_start_offset_ptr (htab, stub_type);
7068 stub_sec_p = arm_dedicated_stub_input_section_ptr (htab, stub_type);
7069 if (start_offset_p == NULL)
7070 continue;
7071
7072 BFD_ASSERT (stub_sec_p != NULL);
7073 if (*stub_sec_p != NULL)
7074 (*stub_sec_p)->size = *start_offset_p;
7075 }
7076
906e58ca
NC		 7077 /* Build the stubs as directed by the stub hash table. */
7078 table = &htab->stub_hash_table;
7079 bfd_hash_traverse (table, arm_build_one_stub, info);
eb7c4339
NS		 7080 if (htab->fix_cortex_a8)
7081 {
7082 /* Place the cortex a8 stubs last. */
7083 htab->fix_cortex_a8 = -1;
7084 bfd_hash_traverse (table, arm_build_one_stub, info);
7085 }
252b5132 7086
906e58ca 7087 return TRUE;
252b5132
RH		 7088}
7089
9b485d32
NC		 7090/* Locate the Thumb encoded calling stub for NAME. */
7091
252b5132 7092static struct elf_link_hash_entry *
57e8b36a
NC		 7093find_thumb_glue (struct bfd_link_info *link_info,
7094 const char *name,
f2a9dd69 7095 char **error_message)
252b5132
RH		 7096{
7097 char *tmp_name;
7098 struct elf_link_hash_entry *hash;
7099 struct elf32_arm_link_hash_table *hash_table;
7100
7101 /* We need a pointer to the armelf specific hash table. */
7102 hash_table = elf32_arm_hash_table (link_info);
4dfe6ac6
NC		 7103 if (hash_table == NULL)
7104 return NULL;
252b5132 7105
21d799b5 7106 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen (name)
99059e56 7107 + strlen (THUMB2ARM_GLUE_ENTRY_NAME) + 1);
252b5132
RH		 7108
7109 BFD_ASSERT (tmp_name);
7110
7111 sprintf (tmp_name, THUMB2ARM_GLUE_ENTRY_NAME, name);
7112
7113 hash = elf_link_hash_lookup
b34976b6 7114 (&(hash_table)->root, tmp_name, FALSE, FALSE, TRUE);
252b5132 7115
b1657152 7116 if (hash == NULL
90b6238f
AM		 7117 && asprintf (error_message, _("unable to find %s glue '%s' for '%s'"),
7118 "Thumb", tmp_name, name) == -1)
b1657152 7119 *error_message = (char *) bfd_errmsg (bfd_error_system_call);
252b5132
RH		 7120
7121 free (tmp_name);
7122
7123 return hash;
7124}
7125
9b485d32
NC		 7126/* Locate the ARM encoded calling stub for NAME. */
7127
252b5132 7128static struct elf_link_hash_entry *
57e8b36a
NC		 7129find_arm_glue (struct bfd_link_info *link_info,
7130 const char *name,
f2a9dd69 7131 char **error_message)
252b5132
RH		 7132{
7133 char *tmp_name;
7134 struct elf_link_hash_entry *myh;
7135 struct elf32_arm_link_hash_table *hash_table;
7136
7137 /* We need a pointer to the elfarm specific hash table. */
7138 hash_table = elf32_arm_hash_table (link_info);
4dfe6ac6
NC		 7139 if (hash_table == NULL)
7140 return NULL;
252b5132 7141
21d799b5 7142 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen (name)
99059e56 7143 + strlen (ARM2THUMB_GLUE_ENTRY_NAME) + 1);
252b5132
RH		 7144
7145 BFD_ASSERT (tmp_name);
7146
7147 sprintf (tmp_name, ARM2THUMB_GLUE_ENTRY_NAME, name);
7148
7149 myh = elf_link_hash_lookup
b34976b6 7150 (&(hash_table)->root, tmp_name, FALSE, FALSE, TRUE);
252b5132 7151
b1657152 7152 if (myh == NULL
90b6238f
AM		 7153 && asprintf (error_message, _("unable to find %s glue '%s' for '%s'"),
7154 "ARM", tmp_name, name) == -1)
b1657152 7155 *error_message = (char *) bfd_errmsg (bfd_error_system_call);
252b5132
RH		 7156
7157 free (tmp_name);
7158
7159 return myh;
7160}
7161
8f6277f5 7162/* ARM->Thumb glue (static images):
252b5132
RH		 7163
7164 .arm
7165 __func_from_arm:
7166 ldr r12, __func_addr
7167 bx r12
7168 __func_addr:
906e58ca 7169 .word func @ behave as if you saw a ARM_32 reloc.
252b5132 7170
26079076
PB		 7171 (v5t static images)
7172 .arm
7173 __func_from_arm:
7174 ldr pc, __func_addr
7175 __func_addr:
906e58ca 7176 .word func @ behave as if you saw a ARM_32 reloc.
26079076 7177
8f6277f5
PB		 7178 (relocatable images)
7179 .arm
7180 __func_from_arm:
7181 ldr r12, __func_offset
7182 add r12, r12, pc
7183 bx r12
7184 __func_offset:
8029a119 7185 .word func - . */
8f6277f5
PB		 7186
7187#define ARM2THUMB_STATIC_GLUE_SIZE 12
252b5132
RH		 7188static const insn32 a2t1_ldr_insn = 0xe59fc000;
7189static const insn32 a2t2_bx_r12_insn = 0xe12fff1c;
7190static const insn32 a2t3_func_addr_insn = 0x00000001;
7191
26079076
PB		 7192#define ARM2THUMB_V5_STATIC_GLUE_SIZE 8
7193static const insn32 a2t1v5_ldr_insn = 0xe51ff004;
7194static const insn32 a2t2v5_func_addr_insn = 0x00000001;
7195
8f6277f5
PB		 7196#define ARM2THUMB_PIC_GLUE_SIZE 16
7197static const insn32 a2t1p_ldr_insn = 0xe59fc004;
7198static const insn32 a2t2p_add_pc_insn = 0xe08cc00f;
7199static const insn32 a2t3p_bx_r12_insn = 0xe12fff1c;
7200
07d6d2b8 7201/* Thumb->ARM: Thumb->(non-interworking aware) ARM
252b5132 7202
07d6d2b8
AM		 7203 .thumb .thumb
7204 .align 2 .align 2
7205 __func_from_thumb: __func_from_thumb:
7206 bx pc push {r6, lr}
7207 nop ldr r6, __func_addr
7208 .arm mov lr, pc
7209 b func bx r6
99059e56
RM		 7210 .arm
7211 ;; back_to_thumb
7212 ldmia r13! {r6, lr}
7213 bx lr
7214 __func_addr:
07d6d2b8 7215 .word func */
252b5132
RH		 7216
7217#define THUMB2ARM_GLUE_SIZE 8
7218static const insn16 t2a1_bx_pc_insn = 0x4778;
7219static const insn16 t2a2_noop_insn = 0x46c0;
7220static const insn32 t2a3_b_insn = 0xea000000;
7221
c7b8f16e 7222#define VFP11_ERRATUM_VENEER_SIZE 8
a504d23a
LA		 7223#define STM32L4XX_ERRATUM_LDM_VENEER_SIZE 16
7224#define STM32L4XX_ERRATUM_VLDM_VENEER_SIZE 24
c7b8f16e 7225
845b51d6
PB		 7226#define ARM_BX_VENEER_SIZE 12
7227static const insn32 armbx1_tst_insn = 0xe3100001;
7228static const insn32 armbx2_moveq_insn = 0x01a0f000;
7229static const insn32 armbx3_bx_insn = 0xe12fff10;
7230
7e392df6 7231#ifndef ELFARM_NABI_C_INCLUDED
8029a119
NC		 7232static void
7233arm_allocate_glue_section_space (bfd * abfd, bfd_size_type size, const char * name)
252b5132
RH		 7234{
7235 asection * s;
8029a119 7236 bfd_byte * contents;
252b5132 7237
8029a119 7238 if (size == 0)
3e6b1042
DJ		 7239 {
7240 /* Do not include empty glue sections in the output. */
7241 if (abfd != NULL)
7242 {
3d4d4302 7243 s = bfd_get_linker_section (abfd, name);
3e6b1042
DJ		 7244 if (s != NULL)
7245 s->flags |= SEC_EXCLUDE;
7246 }
7247 return;
7248 }
252b5132 7249
8029a119 7250 BFD_ASSERT (abfd != NULL);
252b5132 7251
3d4d4302 7252 s = bfd_get_linker_section (abfd, name);
8029a119 7253 BFD_ASSERT (s != NULL);
252b5132 7254
b0f4fbf8 7255 contents = (bfd_byte *) bfd_zalloc (abfd, size);
252b5132 7256
8029a119
NC		 7257 BFD_ASSERT (s->size == size);
7258 s->contents = contents;
7259}
906e58ca 7260
8029a119
NC		 7261bfd_boolean
7262bfd_elf32_arm_allocate_interworking_sections (struct bfd_link_info * info)
7263{
7264 struct elf32_arm_link_hash_table * globals;
906e58ca 7265
8029a119
NC		 7266 globals = elf32_arm_hash_table (info);
7267 BFD_ASSERT (globals != NULL);
906e58ca 7268
8029a119
NC		 7269 arm_allocate_glue_section_space (globals->bfd_of_glue_owner,
7270 globals->arm_glue_size,
7271 ARM2THUMB_GLUE_SECTION_NAME);
906e58ca 7272
8029a119
NC		 7273 arm_allocate_glue_section_space (globals->bfd_of_glue_owner,
7274 globals->thumb_glue_size,
7275 THUMB2ARM_GLUE_SECTION_NAME);
252b5132 7276
8029a119
NC		 7277 arm_allocate_glue_section_space (globals->bfd_of_glue_owner,
7278 globals->vfp11_erratum_glue_size,
7279 VFP11_ERRATUM_VENEER_SECTION_NAME);
845b51d6 7280
a504d23a
LA		 7281 arm_allocate_glue_section_space (globals->bfd_of_glue_owner,
7282 globals->stm32l4xx_erratum_glue_size,
7283 STM32L4XX_ERRATUM_VENEER_SECTION_NAME);
7284
8029a119
NC		 7285 arm_allocate_glue_section_space (globals->bfd_of_glue_owner,
7286 globals->bx_glue_size,
845b51d6
PB		 7287 ARM_BX_GLUE_SECTION_NAME);
7288
b34976b6 7289 return TRUE;
252b5132
RH		 7290}
7291
a4fd1a8e 7292/* Allocate space and symbols for calling a Thumb function from Arm mode.
906e58ca
NC		 7293 returns the symbol identifying the stub. */
7294
a4fd1a8e 7295static struct elf_link_hash_entry *
57e8b36a
NC		 7296record_arm_to_thumb_glue (struct bfd_link_info * link_info,
7297 struct elf_link_hash_entry * h)
252b5132
RH		 7298{
7299 const char * name = h->root.root.string;
63b0f745 7300 asection * s;
252b5132
RH		 7301 char * tmp_name;
7302 struct elf_link_hash_entry * myh;
14a793b2 7303 struct bfd_link_hash_entry * bh;
252b5132 7304 struct elf32_arm_link_hash_table * globals;
dc810e39 7305 bfd_vma val;
2f475487 7306 bfd_size_type size;
252b5132
RH		 7307
7308 globals = elf32_arm_hash_table (link_info);
252b5132
RH		 7309 BFD_ASSERT (globals != NULL);
7310 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
7311
3d4d4302 7312 s = bfd_get_linker_section
252b5132
RH		 7313 (globals->bfd_of_glue_owner, ARM2THUMB_GLUE_SECTION_NAME);
7314
252b5132
RH		 7315 BFD_ASSERT (s != NULL);
7316
21d799b5 7317 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen (name)
99059e56 7318 + strlen (ARM2THUMB_GLUE_ENTRY_NAME) + 1);
252b5132
RH		 7319
7320 BFD_ASSERT (tmp_name);
7321
7322 sprintf (tmp_name, ARM2THUMB_GLUE_ENTRY_NAME, name);
7323
7324 myh = elf_link_hash_lookup
b34976b6 7325 (&(globals)->root, tmp_name, FALSE, FALSE, TRUE);
252b5132
RH		 7326
7327 if (myh != NULL)
7328 {
9b485d32 7329 /* We've already seen this guy. */
252b5132 7330 free (tmp_name);
a4fd1a8e 7331 return myh;
252b5132
RH		 7332 }
7333
57e8b36a
NC		 7334 /* The only trick here is using hash_table->arm_glue_size as the value.
7335 Even though the section isn't allocated yet, this is where we will be
3dccd7b7
DJ		 7336 putting it. The +1 on the value marks that the stub has not been
7337 output yet - not that it is a Thumb function. */
14a793b2 7338 bh = NULL;
dc810e39
AM		 7339 val = globals->arm_glue_size + 1;
7340 _bfd_generic_link_add_one_symbol (link_info, globals->bfd_of_glue_owner,
7341 tmp_name, BSF_GLOBAL, s, val,
b34976b6 7342 NULL, TRUE, FALSE, &bh);
252b5132 7343
b7693d02
DJ		 7344 myh = (struct elf_link_hash_entry *) bh;
7345 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
7346 myh->forced_local = 1;
7347
252b5132
RH		 7348 free (tmp_name);
7349
0e1862bb
L		 7350 if (bfd_link_pic (link_info)
7351 || globals->root.is_relocatable_executable
27e55c4d 7352 || globals->pic_veneer)
2f475487 7353 size = ARM2THUMB_PIC_GLUE_SIZE;
26079076
PB		 7354 else if (globals->use_blx)
7355 size = ARM2THUMB_V5_STATIC_GLUE_SIZE;
8f6277f5 7356 else
2f475487
AM		 7357 size = ARM2THUMB_STATIC_GLUE_SIZE;
7358
7359 s->size += size;
7360 globals->arm_glue_size += size;
252b5132 7361
a4fd1a8e 7362 return myh;
252b5132
RH		 7363}
7364
845b51d6
PB		 7365/* Allocate space for ARMv4 BX veneers. */
7366
7367static void
7368record_arm_bx_glue (struct bfd_link_info * link_info, int reg)
7369{
7370 asection * s;
7371 struct elf32_arm_link_hash_table *globals;
7372 char *tmp_name;
7373 struct elf_link_hash_entry *myh;
7374 struct bfd_link_hash_entry *bh;
7375 bfd_vma val;
7376
7377 /* BX PC does not need a veneer. */
7378 if (reg == 15)
7379 return;
7380
7381 globals = elf32_arm_hash_table (link_info);
845b51d6
PB		 7382 BFD_ASSERT (globals != NULL);
7383 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
7384
7385 /* Check if this veneer has already been allocated. */
7386 if (globals->bx_glue_offset[reg])
7387 return;
7388
3d4d4302 7389 s = bfd_get_linker_section
845b51d6
PB		 7390 (globals->bfd_of_glue_owner, ARM_BX_GLUE_SECTION_NAME);
7391
7392 BFD_ASSERT (s != NULL);
7393
7394 /* Add symbol for veneer. */
21d799b5
NC		 7395 tmp_name = (char *)
7396 bfd_malloc ((bfd_size_type) strlen (ARM_BX_GLUE_ENTRY_NAME) + 1);
906e58ca 7397
845b51d6 7398 BFD_ASSERT (tmp_name);
906e58ca 7399
845b51d6 7400 sprintf (tmp_name, ARM_BX_GLUE_ENTRY_NAME, reg);
906e58ca 7401
845b51d6
PB		 7402 myh = elf_link_hash_lookup
7403 (&(globals)->root, tmp_name, FALSE, FALSE, FALSE);
906e58ca 7404
845b51d6 7405 BFD_ASSERT (myh == NULL);
906e58ca 7406
845b51d6
PB		 7407 bh = NULL;
7408 val = globals->bx_glue_size;
7409 _bfd_generic_link_add_one_symbol (link_info, globals->bfd_of_glue_owner,
99059e56
RM		 7410 tmp_name, BSF_FUNCTION | BSF_LOCAL, s, val,
7411 NULL, TRUE, FALSE, &bh);
845b51d6
PB		 7412
7413 myh = (struct elf_link_hash_entry *) bh;
7414 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
7415 myh->forced_local = 1;
7416
7417 s->size += ARM_BX_VENEER_SIZE;
7418 globals->bx_glue_offset[reg] = globals->bx_glue_size | 2;
7419 globals->bx_glue_size += ARM_BX_VENEER_SIZE;
7420}
7421
7422
c7b8f16e
JB		 7423/* Add an entry to the code/data map for section SEC. */
7424
7425static void
7426elf32_arm_section_map_add (asection *sec, char type, bfd_vma vma)
7427{
7428 struct _arm_elf_section_data *sec_data = elf32_arm_section_data (sec);
7429 unsigned int newidx;
906e58ca 7430
c7b8f16e
JB		 7431 if (sec_data->map == NULL)
7432 {
21d799b5 7433 sec_data->map = (elf32_arm_section_map *)
99059e56 7434 bfd_malloc (sizeof (elf32_arm_section_map));
c7b8f16e
JB		 7435 sec_data->mapcount = 0;
7436 sec_data->mapsize = 1;
7437 }
906e58ca 7438
c7b8f16e 7439 newidx = sec_data->mapcount++;
906e58ca 7440
c7b8f16e
JB		 7441 if (sec_data->mapcount > sec_data->mapsize)
7442 {
7443 sec_data->mapsize *= 2;
21d799b5 7444 sec_data->map = (elf32_arm_section_map *)
99059e56
RM		 7445 bfd_realloc_or_free (sec_data->map, sec_data->mapsize
7446 * sizeof (elf32_arm_section_map));
515ef31d
NC		 7447 }
7448
7449 if (sec_data->map)
7450 {
7451 sec_data->map[newidx].vma = vma;
7452 sec_data->map[newidx].type = type;
c7b8f16e 7453 }
c7b8f16e
JB		 7454}
7455
7456
7457/* Record information about a VFP11 denorm-erratum veneer. Only ARM-mode
7458 veneers are handled for now. */
7459
7460static bfd_vma
7461record_vfp11_erratum_veneer (struct bfd_link_info *link_info,
99059e56
RM		 7462 elf32_vfp11_erratum_list *branch,
7463 bfd *branch_bfd,
7464 asection *branch_sec,
7465 unsigned int offset)
c7b8f16e
JB		 7466{
7467 asection *s;
7468 struct elf32_arm_link_hash_table *hash_table;
7469 char *tmp_name;
7470 struct elf_link_hash_entry *myh;
7471 struct bfd_link_hash_entry *bh;
7472 bfd_vma val;
7473 struct _arm_elf_section_data *sec_data;
c7b8f16e 7474 elf32_vfp11_erratum_list *newerr;
906e58ca 7475
c7b8f16e 7476 hash_table = elf32_arm_hash_table (link_info);
c7b8f16e
JB		 7477 BFD_ASSERT (hash_table != NULL);
7478 BFD_ASSERT (hash_table->bfd_of_glue_owner != NULL);
906e58ca 7479
3d4d4302 7480 s = bfd_get_linker_section
c7b8f16e 7481 (hash_table->bfd_of_glue_owner, VFP11_ERRATUM_VENEER_SECTION_NAME);
906e58ca 7482
c7b8f16e 7483 sec_data = elf32_arm_section_data (s);
906e58ca 7484
c7b8f16e 7485 BFD_ASSERT (s != NULL);
906e58ca 7486
21d799b5 7487 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen
99059e56 7488 (VFP11_ERRATUM_VENEER_ENTRY_NAME) + 10);
906e58ca 7489
c7b8f16e 7490 BFD_ASSERT (tmp_name);
906e58ca 7491
c7b8f16e
JB		 7492 sprintf (tmp_name, VFP11_ERRATUM_VENEER_ENTRY_NAME,
7493 hash_table->num_vfp11_fixes);
906e58ca 7494
c7b8f16e
JB		 7495 myh = elf_link_hash_lookup
7496 (&(hash_table)->root, tmp_name, FALSE, FALSE, FALSE);
906e58ca 7497
c7b8f16e 7498 BFD_ASSERT (myh == NULL);
906e58ca 7499
c7b8f16e
JB		 7500 bh = NULL;
7501 val = hash_table->vfp11_erratum_glue_size;
7502 _bfd_generic_link_add_one_symbol (link_info, hash_table->bfd_of_glue_owner,
99059e56
RM		 7503 tmp_name, BSF_FUNCTION | BSF_LOCAL, s, val,
7504 NULL, TRUE, FALSE, &bh);
c7b8f16e
JB		 7505
7506 myh = (struct elf_link_hash_entry *) bh;
7507 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
7508 myh->forced_local = 1;
7509
7510 /* Link veneer back to calling location. */
c7e2358a 7511 sec_data->erratumcount += 1;
21d799b5
NC		 7512 newerr = (elf32_vfp11_erratum_list *)
7513 bfd_zmalloc (sizeof (elf32_vfp11_erratum_list));
906e58ca 7514
c7b8f16e
JB		 7515 newerr->type = VFP11_ERRATUM_ARM_VENEER;
7516 newerr->vma = -1;
7517 newerr->u.v.branch = branch;
7518 newerr->u.v.id = hash_table->num_vfp11_fixes;
7519 branch->u.b.veneer = newerr;
7520
7521 newerr->next = sec_data->erratumlist;
7522 sec_data->erratumlist = newerr;
7523
7524 /* A symbol for the return from the veneer. */
7525 sprintf (tmp_name, VFP11_ERRATUM_VENEER_ENTRY_NAME "_r",
7526 hash_table->num_vfp11_fixes);
7527
7528 myh = elf_link_hash_lookup
7529 (&(hash_table)->root, tmp_name, FALSE, FALSE, FALSE);
906e58ca 7530
c7b8f16e
JB		 7531 if (myh != NULL)
7532 abort ();
7533
7534 bh = NULL;
7535 val = offset + 4;
7536 _bfd_generic_link_add_one_symbol (link_info, branch_bfd, tmp_name, BSF_LOCAL,
7537 branch_sec, val, NULL, TRUE, FALSE, &bh);
906e58ca 7538
c7b8f16e
JB		 7539 myh = (struct elf_link_hash_entry *) bh;
7540 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
7541 myh->forced_local = 1;
7542
7543 free (tmp_name);
906e58ca 7544
c7b8f16e
JB		 7545 /* Generate a mapping symbol for the veneer section, and explicitly add an
7546 entry for that symbol to the code/data map for the section. */
7547 if (hash_table->vfp11_erratum_glue_size == 0)
7548 {
7549 bh = NULL;
7550 /* FIXME: Creates an ARM symbol. Thumb mode will need attention if it
99059e56 7551 ever requires this erratum fix. */
c7b8f16e
JB		 7552 _bfd_generic_link_add_one_symbol (link_info,
7553 hash_table->bfd_of_glue_owner, "$a",
7554 BSF_LOCAL, s, 0, NULL,
99059e56 7555 TRUE, FALSE, &bh);
c7b8f16e
JB		 7556
7557 myh = (struct elf_link_hash_entry *) bh;
7558 myh->type = ELF_ST_INFO (STB_LOCAL, STT_NOTYPE);
7559 myh->forced_local = 1;
906e58ca 7560
c7b8f16e 7561 /* The elf32_arm_init_maps function only cares about symbols from input
99059e56
RM		 7562 BFDs. We must make a note of this generated mapping symbol
7563 ourselves so that code byteswapping works properly in
7564 elf32_arm_write_section. */
c7b8f16e
JB		 7565 elf32_arm_section_map_add (s, 'a', 0);
7566 }
906e58ca 7567
c7b8f16e
JB		 7568 s->size += VFP11_ERRATUM_VENEER_SIZE;
7569 hash_table->vfp11_erratum_glue_size += VFP11_ERRATUM_VENEER_SIZE;
7570 hash_table->num_vfp11_fixes++;
906e58ca 7571
c7b8f16e
JB		 7572 /* The offset of the veneer. */
7573 return val;
7574}
7575
a504d23a
LA		 7576/* Record information about a STM32L4XX STM erratum veneer. Only THUMB-mode
7577 veneers need to be handled because used only in Cortex-M. */
7578
7579static bfd_vma
7580record_stm32l4xx_erratum_veneer (struct bfd_link_info *link_info,
7581 elf32_stm32l4xx_erratum_list *branch,
7582 bfd *branch_bfd,
7583 asection *branch_sec,
7584 unsigned int offset,
7585 bfd_size_type veneer_size)
7586{
7587 asection *s;
7588 struct elf32_arm_link_hash_table *hash_table;
7589 char *tmp_name;
7590 struct elf_link_hash_entry *myh;
7591 struct bfd_link_hash_entry *bh;
7592 bfd_vma val;
7593 struct _arm_elf_section_data *sec_data;
7594 elf32_stm32l4xx_erratum_list *newerr;
7595
7596 hash_table = elf32_arm_hash_table (link_info);
7597 BFD_ASSERT (hash_table != NULL);
7598 BFD_ASSERT (hash_table->bfd_of_glue_owner != NULL);
7599
7600 s = bfd_get_linker_section
7601 (hash_table->bfd_of_glue_owner, STM32L4XX_ERRATUM_VENEER_SECTION_NAME);
7602
7603 BFD_ASSERT (s != NULL);
7604
7605 sec_data = elf32_arm_section_data (s);
7606
7607 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen
7608 (STM32L4XX_ERRATUM_VENEER_ENTRY_NAME) + 10);
7609
7610 BFD_ASSERT (tmp_name);
7611
7612 sprintf (tmp_name, STM32L4XX_ERRATUM_VENEER_ENTRY_NAME,
7613 hash_table->num_stm32l4xx_fixes);
7614
7615 myh = elf_link_hash_lookup
7616 (&(hash_table)->root, tmp_name, FALSE, FALSE, FALSE);
7617
7618 BFD_ASSERT (myh == NULL);
7619
7620 bh = NULL;
7621 val = hash_table->stm32l4xx_erratum_glue_size;
7622 _bfd_generic_link_add_one_symbol (link_info, hash_table->bfd_of_glue_owner,
7623 tmp_name, BSF_FUNCTION | BSF_LOCAL, s, val,
7624 NULL, TRUE, FALSE, &bh);
7625
7626 myh = (struct elf_link_hash_entry *) bh;
7627 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
7628 myh->forced_local = 1;
7629
7630 /* Link veneer back to calling location. */
7631 sec_data->stm32l4xx_erratumcount += 1;
7632 newerr = (elf32_stm32l4xx_erratum_list *)
7633 bfd_zmalloc (sizeof (elf32_stm32l4xx_erratum_list));
7634
7635 newerr->type = STM32L4XX_ERRATUM_VENEER;
7636 newerr->vma = -1;
7637 newerr->u.v.branch = branch;
7638 newerr->u.v.id = hash_table->num_stm32l4xx_fixes;
7639 branch->u.b.veneer = newerr;
7640
7641 newerr->next = sec_data->stm32l4xx_erratumlist;
7642 sec_data->stm32l4xx_erratumlist = newerr;
7643
7644 /* A symbol for the return from the veneer. */
7645 sprintf (tmp_name, STM32L4XX_ERRATUM_VENEER_ENTRY_NAME "_r",
7646 hash_table->num_stm32l4xx_fixes);
7647
7648 myh = elf_link_hash_lookup
7649 (&(hash_table)->root, tmp_name, FALSE, FALSE, FALSE);
7650
7651 if (myh != NULL)
7652 abort ();
7653
7654 bh = NULL;
7655 val = offset + 4;
7656 _bfd_generic_link_add_one_symbol (link_info, branch_bfd, tmp_name, BSF_LOCAL,
7657 branch_sec, val, NULL, TRUE, FALSE, &bh);
7658
7659 myh = (struct elf_link_hash_entry *) bh;
7660 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
7661 myh->forced_local = 1;
7662
7663 free (tmp_name);
7664
7665 /* Generate a mapping symbol for the veneer section, and explicitly add an
7666 entry for that symbol to the code/data map for the section. */
7667 if (hash_table->stm32l4xx_erratum_glue_size == 0)
7668 {
7669 bh = NULL;
7670 /* Creates a THUMB symbol since there is no other choice. */
7671 _bfd_generic_link_add_one_symbol (link_info,
7672 hash_table->bfd_of_glue_owner, "$t",
7673 BSF_LOCAL, s, 0, NULL,
7674 TRUE, FALSE, &bh);
7675
7676 myh = (struct elf_link_hash_entry *) bh;
7677 myh->type = ELF_ST_INFO (STB_LOCAL, STT_NOTYPE);
7678 myh->forced_local = 1;
7679
7680 /* The elf32_arm_init_maps function only cares about symbols from input
7681 BFDs. We must make a note of this generated mapping symbol
7682 ourselves so that code byteswapping works properly in
7683 elf32_arm_write_section. */
7684 elf32_arm_section_map_add (s, 't', 0);
7685 }
7686
7687 s->size += veneer_size;
7688 hash_table->stm32l4xx_erratum_glue_size += veneer_size;
7689 hash_table->num_stm32l4xx_fixes++;
7690
7691 /* The offset of the veneer. */
7692 return val;
7693}
7694
8029a119 7695#define ARM_GLUE_SECTION_FLAGS \
3e6b1042
DJ		 7696 (SEC_ALLOC | SEC_LOAD | SEC_HAS_CONTENTS | SEC_IN_MEMORY | SEC_CODE \
7697 | SEC_READONLY | SEC_LINKER_CREATED)
8029a119
NC		 7698
7699/* Create a fake section for use by the ARM backend of the linker. */
7700
7701static bfd_boolean
7702arm_make_glue_section (bfd * abfd, const char * name)
7703{
7704 asection * sec;
7705
3d4d4302 7706 sec = bfd_get_linker_section (abfd, name);
8029a119
NC		 7707 if (sec != NULL)
7708 /* Already made. */
7709 return TRUE;
7710
3d4d4302 7711 sec = bfd_make_section_anyway_with_flags (abfd, name, ARM_GLUE_SECTION_FLAGS);
8029a119
NC		 7712
7713 if (sec == NULL
7714 || !bfd_set_section_alignment (abfd, sec, 2))
7715 return FALSE;
7716
7717 /* Set the gc mark to prevent the section from being removed by garbage
7718 collection, despite the fact that no relocs refer to this section. */
7719 sec->gc_mark = 1;
7720
7721 return TRUE;
7722}
7723
1db37fe6
YG		 7724/* Set size of .plt entries. This function is called from the
7725 linker scripts in ld/emultempl/{armelf}.em. */
7726
7727void
7728bfd_elf32_arm_use_long_plt (void)
7729{
7730 elf32_arm_use_long_plt_entry = TRUE;
7731}
7732
8afb0e02
NC		 7733/* Add the glue sections to ABFD. This function is called from the
7734 linker scripts in ld/emultempl/{armelf}.em. */
9b485d32 7735
b34976b6 7736bfd_boolean
57e8b36a
NC		 7737bfd_elf32_arm_add_glue_sections_to_bfd (bfd *abfd,
7738 struct bfd_link_info *info)
252b5132 7739{
a504d23a
LA		 7740 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (info);
7741 bfd_boolean dostm32l4xx = globals
7742 && globals->stm32l4xx_fix != BFD_ARM_STM32L4XX_FIX_NONE;
7743 bfd_boolean addglue;
7744
8afb0e02
NC		 7745 /* If we are only performing a partial
7746 link do not bother adding the glue. */
0e1862bb 7747 if (bfd_link_relocatable (info))
b34976b6 7748 return TRUE;
252b5132 7749
a504d23a 7750 addglue = arm_make_glue_section (abfd, ARM2THUMB_GLUE_SECTION_NAME)
8029a119
NC		 7751 && arm_make_glue_section (abfd, THUMB2ARM_GLUE_SECTION_NAME)
7752 && arm_make_glue_section (abfd, VFP11_ERRATUM_VENEER_SECTION_NAME)
7753 && arm_make_glue_section (abfd, ARM_BX_GLUE_SECTION_NAME);
a504d23a
LA		 7754
7755 if (!dostm32l4xx)
7756 return addglue;
7757
7758 return addglue
7759 && arm_make_glue_section (abfd, STM32L4XX_ERRATUM_VENEER_SECTION_NAME);
8afb0e02
NC		 7760}
7761
daa4adae
TP		 7762/* Mark output sections of veneers needing a dedicated one with SEC_KEEP. This
7763 ensures they are not marked for deletion by
7764 strip_excluded_output_sections () when veneers are going to be created
7765 later. Not doing so would trigger assert on empty section size in
7766 lang_size_sections_1 (). */
7767
7768void
7769bfd_elf32_arm_keep_private_stub_output_sections (struct bfd_link_info *info)
7770{
7771 enum elf32_arm_stub_type stub_type;
7772
7773 /* If we are only performing a partial
7774 link do not bother adding the glue. */
7775 if (bfd_link_relocatable (info))
7776 return;
7777
7778 for (stub_type = arm_stub_none + 1; stub_type < max_stub_type; stub_type++)
7779 {
7780 asection *out_sec;
7781 const char *out_sec_name;
7782
7783 if (!arm_dedicated_stub_output_section_required (stub_type))
7784 continue;
7785
7786 out_sec_name = arm_dedicated_stub_output_section_name (stub_type);
7787 out_sec = bfd_get_section_by_name (info->output_bfd, out_sec_name);
7788 if (out_sec != NULL)
7789 out_sec->flags |= SEC_KEEP;
7790 }
7791}
7792
8afb0e02
NC		 7793/* Select a BFD to be used to hold the sections used by the glue code.
7794 This function is called from the linker scripts in ld/emultempl/
8029a119 7795 {armelf/pe}.em. */
8afb0e02 7796
b34976b6 7797bfd_boolean
57e8b36a 7798bfd_elf32_arm_get_bfd_for_interworking (bfd *abfd, struct bfd_link_info *info)
8afb0e02
NC		 7799{
7800 struct elf32_arm_link_hash_table *globals;
7801
7802 /* If we are only performing a partial link
7803 do not bother getting a bfd to hold the glue. */
0e1862bb 7804 if (bfd_link_relocatable (info))
b34976b6 7805 return TRUE;
8afb0e02 7806
b7693d02
DJ		 7807 /* Make sure we don't attach the glue sections to a dynamic object. */
7808 BFD_ASSERT (!(abfd->flags & DYNAMIC));
7809
8afb0e02 7810 globals = elf32_arm_hash_table (info);
8afb0e02
NC		 7811 BFD_ASSERT (globals != NULL);
7812
7813 if (globals->bfd_of_glue_owner != NULL)
b34976b6 7814 return TRUE;
8afb0e02 7815
252b5132
RH		 7816 /* Save the bfd for later use. */
7817 globals->bfd_of_glue_owner = abfd;
cedb70c5 7818
b34976b6 7819 return TRUE;
252b5132
RH		 7820}
7821
906e58ca
NC		 7822static void
7823check_use_blx (struct elf32_arm_link_hash_table *globals)
39b41c9c 7824{
2de70689
MGD		 7825 int cpu_arch;
7826
b38cadfb 7827 cpu_arch = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC,
2de70689
MGD		 7828 Tag_CPU_arch);
7829
7830 if (globals->fix_arm1176)
7831 {
7832 if (cpu_arch == TAG_CPU_ARCH_V6T2 || cpu_arch > TAG_CPU_ARCH_V6K)
7833 globals->use_blx = 1;
7834 }
7835 else
7836 {
7837 if (cpu_arch > TAG_CPU_ARCH_V4T)
7838 globals->use_blx = 1;
7839 }
39b41c9c
PB		 7840}
7841
b34976b6 7842bfd_boolean
57e8b36a 7843bfd_elf32_arm_process_before_allocation (bfd *abfd,
d504ffc8 7844 struct bfd_link_info *link_info)
252b5132
RH		 7845{
7846 Elf_Internal_Shdr *symtab_hdr;
6cdc0ccc 7847 Elf_Internal_Rela *internal_relocs = NULL;
252b5132
RH		 7848 Elf_Internal_Rela *irel, *irelend;
7849 bfd_byte *contents = NULL;
252b5132
RH		 7850
7851 asection *sec;
7852 struct elf32_arm_link_hash_table *globals;
7853
7854 /* If we are only performing a partial link do not bother
7855 to construct any glue. */
0e1862bb 7856 if (bfd_link_relocatable (link_info))
b34976b6 7857 return TRUE;
252b5132 7858
39ce1a6a
NC		 7859 /* Here we have a bfd that is to be included on the link. We have a
7860 hook to do reloc rummaging, before section sizes are nailed down. */
252b5132 7861 globals = elf32_arm_hash_table (link_info);
252b5132 7862 BFD_ASSERT (globals != NULL);
39ce1a6a
NC		 7863
7864 check_use_blx (globals);
252b5132 7865
d504ffc8 7866 if (globals->byteswap_code && !bfd_big_endian (abfd))
e489d0ae 7867 {
90b6238f 7868 _bfd_error_handler (_("%pB: BE8 images only valid in big-endian mode"),
d003868e 7869 abfd);
e489d0ae
PB		 7870 return FALSE;
7871 }
f21f3fe0 7872
39ce1a6a
NC		 7873 /* PR 5398: If we have not decided to include any loadable sections in
7874 the output then we will not have a glue owner bfd. This is OK, it
7875 just means that there is nothing else for us to do here. */
7876 if (globals->bfd_of_glue_owner == NULL)
7877 return TRUE;
7878
252b5132
RH		 7879 /* Rummage around all the relocs and map the glue vectors. */
7880 sec = abfd->sections;
7881
7882 if (sec == NULL)
b34976b6 7883 return TRUE;
252b5132
RH		 7884
7885 for (; sec != NULL; sec = sec->next)
7886 {
7887 if (sec->reloc_count == 0)
7888 continue;
7889
2f475487
AM		 7890 if ((sec->flags & SEC_EXCLUDE) != 0)
7891 continue;
7892
0ffa91dd 7893 symtab_hdr = & elf_symtab_hdr (abfd);
252b5132 7894
9b485d32 7895 /* Load the relocs. */
6cdc0ccc 7896 internal_relocs
906e58ca 7897 = _bfd_elf_link_read_relocs (abfd, sec, NULL, NULL, FALSE);
252b5132 7898
6cdc0ccc
AM		 7899 if (internal_relocs == NULL)
7900 goto error_return;
252b5132 7901
6cdc0ccc
AM		 7902 irelend = internal_relocs + sec->reloc_count;
7903 for (irel = internal_relocs; irel < irelend; irel++)
252b5132
RH		 7904 {
7905 long r_type;
7906 unsigned long r_index;
252b5132
RH		 7907
7908 struct elf_link_hash_entry *h;
7909
7910 r_type = ELF32_R_TYPE (irel->r_info);
7911 r_index = ELF32_R_SYM (irel->r_info);
7912
9b485d32 7913 /* These are the only relocation types we care about. */
ba96a88f 7914 if ( r_type != R_ARM_PC24
845b51d6 7915 && (r_type != R_ARM_V4BX || globals->fix_v4bx < 2))
252b5132
RH		 7916 continue;
7917
7918 /* Get the section contents if we haven't done so already. */
7919 if (contents == NULL)
7920 {
7921 /* Get cached copy if it exists. */
7922 if (elf_section_data (sec)->this_hdr.contents != NULL)
7923 contents = elf_section_data (sec)->this_hdr.contents;
7924 else
7925 {
7926 /* Go get them off disk. */
57e8b36a 7927 if (! bfd_malloc_and_get_section (abfd, sec, &contents))
252b5132
RH		 7928 goto error_return;
7929 }
7930 }
7931
845b51d6
PB		 7932 if (r_type == R_ARM_V4BX)
7933 {
7934 int reg;
7935
7936 reg = bfd_get_32 (abfd, contents + irel->r_offset) & 0xf;
7937 record_arm_bx_glue (link_info, reg);
7938 continue;
7939 }
7940
a7c10850 7941 /* If the relocation is not against a symbol it cannot concern us. */
252b5132
RH		 7942 h = NULL;
7943
9b485d32 7944 /* We don't care about local symbols. */
252b5132
RH		 7945 if (r_index < symtab_hdr->sh_info)
7946 continue;
7947
9b485d32 7948 /* This is an external symbol. */
252b5132
RH		 7949 r_index -= symtab_hdr->sh_info;
7950 h = (struct elf_link_hash_entry *)
7951 elf_sym_hashes (abfd)[r_index];
7952
7953 /* If the relocation is against a static symbol it must be within
7954 the current section and so cannot be a cross ARM/Thumb relocation. */
7955 if (h == NULL)
7956 continue;
7957
d504ffc8
DJ		 7958 /* If the call will go through a PLT entry then we do not need
7959 glue. */
362d30a1 7960 if (globals->root.splt != NULL && h->plt.offset != (bfd_vma) -1)
b7693d02
DJ		 7961 continue;
7962
252b5132
RH		 7963 switch (r_type)
7964 {
7965 case R_ARM_PC24:
7966 /* This one is a call from arm code. We need to look up
99059e56
RM		 7967 the target of the call. If it is a thumb target, we
7968 insert glue. */
39d911fc
TP		 7969 if (ARM_GET_SYM_BRANCH_TYPE (h->target_internal)
7970 == ST_BRANCH_TO_THUMB)
252b5132
RH		 7971 record_arm_to_thumb_glue (link_info, h);
7972 break;
7973
252b5132 7974 default:
c6596c5e 7975 abort ();
252b5132
RH		 7976 }
7977 }
6cdc0ccc
AM		 7978
7979 if (contents != NULL
7980 && elf_section_data (sec)->this_hdr.contents != contents)
7981 free (contents);
7982 contents = NULL;
7983
7984 if (internal_relocs != NULL
7985 && elf_section_data (sec)->relocs != internal_relocs)
7986 free (internal_relocs);
7987 internal_relocs = NULL;
252b5132
RH		 7988 }
7989
b34976b6 7990 return TRUE;
9a5aca8c 7991
252b5132 7992error_return:
6cdc0ccc
AM		 7993 if (contents != NULL
7994 && elf_section_data (sec)->this_hdr.contents != contents)
7995 free (contents);
7996 if (internal_relocs != NULL
7997 && elf_section_data (sec)->relocs != internal_relocs)
7998 free (internal_relocs);
9a5aca8c 7999
b34976b6 8000 return FALSE;
252b5132 8001}
7e392df6 8002#endif
252b5132 8003
eb043451 8004
c7b8f16e
JB		 8005/* Initialise maps of ARM/Thumb/data for input BFDs. */
8006
8007void
8008bfd_elf32_arm_init_maps (bfd *abfd)
8009{
8010 Elf_Internal_Sym *isymbuf;
8011 Elf_Internal_Shdr *hdr;
8012 unsigned int i, localsyms;
8013
af1f4419
NC		 8014 /* PR 7093: Make sure that we are dealing with an arm elf binary. */
8015 if (! is_arm_elf (abfd))
8016 return;
8017
c7b8f16e
JB		 8018 if ((abfd->flags & DYNAMIC) != 0)
8019 return;
8020
0ffa91dd 8021 hdr = & elf_symtab_hdr (abfd);
c7b8f16e
JB		 8022 localsyms = hdr->sh_info;
8023
8024 /* Obtain a buffer full of symbols for this BFD. The hdr->sh_info field
8025 should contain the number of local symbols, which should come before any
8026 global symbols. Mapping symbols are always local. */
8027 isymbuf = bfd_elf_get_elf_syms (abfd, hdr, localsyms, 0, NULL, NULL,
8028 NULL);
8029
8030 /* No internal symbols read? Skip this BFD. */
8031 if (isymbuf == NULL)
8032 return;
8033
8034 for (i = 0; i < localsyms; i++)
8035 {
8036 Elf_Internal_Sym *isym = &isymbuf[i];
8037 asection *sec = bfd_section_from_elf_index (abfd, isym->st_shndx);
8038 const char *name;
906e58ca 8039
c7b8f16e 8040 if (sec != NULL
99059e56
RM		 8041 && ELF_ST_BIND (isym->st_info) == STB_LOCAL)
8042 {
8043 name = bfd_elf_string_from_elf_section (abfd,
8044 hdr->sh_link, isym->st_name);
906e58ca 8045
99059e56 8046 if (bfd_is_arm_special_symbol_name (name,
c7b8f16e 8047 BFD_ARM_SPECIAL_SYM_TYPE_MAP))
99059e56
RM		 8048 elf32_arm_section_map_add (sec, name[1], isym->st_value);
8049 }
c7b8f16e
JB		 8050 }
8051}
8052
8053
48229727
JB		 8054/* Auto-select enabling of Cortex-A8 erratum fix if the user didn't explicitly
8055 say what they wanted. */
8056
8057void
8058bfd_elf32_arm_set_cortex_a8_fix (bfd *obfd, struct bfd_link_info *link_info)
8059{
8060 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (link_info);
8061 obj_attribute *out_attr = elf_known_obj_attributes_proc (obfd);
8062
4dfe6ac6
NC		 8063 if (globals == NULL)
8064 return;
8065
48229727
JB		 8066 if (globals->fix_cortex_a8 == -1)
8067 {
8068 /* Turn on Cortex-A8 erratum workaround for ARMv7-A. */
8069 if (out_attr[Tag_CPU_arch].i == TAG_CPU_ARCH_V7
8070 && (out_attr[Tag_CPU_arch_profile].i == 'A'
8071 || out_attr[Tag_CPU_arch_profile].i == 0))
8072 globals->fix_cortex_a8 = 1;
8073 else
8074 globals->fix_cortex_a8 = 0;
8075 }
8076}
8077
8078
c7b8f16e
JB		 8079void
8080bfd_elf32_arm_set_vfp11_fix (bfd *obfd, struct bfd_link_info *link_info)
8081{
8082 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (link_info);
104d59d1 8083 obj_attribute *out_attr = elf_known_obj_attributes_proc (obfd);
906e58ca 8084
4dfe6ac6
NC		 8085 if (globals == NULL)
8086 return;
c7b8f16e
JB		 8087 /* We assume that ARMv7+ does not need the VFP11 denorm erratum fix. */
8088 if (out_attr[Tag_CPU_arch].i >= TAG_CPU_ARCH_V7)
8089 {
8090 switch (globals->vfp11_fix)
99059e56
RM		 8091 {
8092 case BFD_ARM_VFP11_FIX_DEFAULT:
8093 case BFD_ARM_VFP11_FIX_NONE:
8094 globals->vfp11_fix = BFD_ARM_VFP11_FIX_NONE;
8095 break;
8096
8097 default:
8098 /* Give a warning, but do as the user requests anyway. */
871b3ab2 8099 _bfd_error_handler (_("%pB: warning: selected VFP11 erratum "
99059e56
RM		 8100 "workaround is not necessary for target architecture"), obfd);
8101 }
c7b8f16e
JB		 8102 }
8103 else if (globals->vfp11_fix == BFD_ARM_VFP11_FIX_DEFAULT)
8104 /* For earlier architectures, we might need the workaround, but do not
8105 enable it by default. If users is running with broken hardware, they
8106 must enable the erratum fix explicitly. */
8107 globals->vfp11_fix = BFD_ARM_VFP11_FIX_NONE;
8108}
8109
a504d23a
LA		 8110void
8111bfd_elf32_arm_set_stm32l4xx_fix (bfd *obfd, struct bfd_link_info *link_info)
8112{
8113 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (link_info);
8114 obj_attribute *out_attr = elf_known_obj_attributes_proc (obfd);
8115
8116 if (globals == NULL)
8117 return;
8118
8119 /* We assume only Cortex-M4 may require the fix. */
8120 if (out_attr[Tag_CPU_arch].i != TAG_CPU_ARCH_V7E_M
8121 || out_attr[Tag_CPU_arch_profile].i != 'M')
8122 {
8123 if (globals->stm32l4xx_fix != BFD_ARM_STM32L4XX_FIX_NONE)
8124 /* Give a warning, but do as the user requests anyway. */
4eca0228 8125 _bfd_error_handler
871b3ab2 8126 (_("%pB: warning: selected STM32L4XX erratum "
a504d23a
LA		 8127 "workaround is not necessary for target architecture"), obfd);
8128 }
8129}
c7b8f16e 8130
906e58ca
NC		 8131enum bfd_arm_vfp11_pipe
8132{
c7b8f16e
JB		 8133 VFP11_FMAC,
8134 VFP11_LS,
8135 VFP11_DS,
8136 VFP11_BAD
8137};
8138
8139/* Return a VFP register number. This is encoded as RX:X for single-precision
8140 registers, or X:RX for double-precision registers, where RX is the group of
8141 four bits in the instruction encoding and X is the single extension bit.
8142 RX and X fields are specified using their lowest (starting) bit. The return
8143 value is:
8144
8145 0...31: single-precision registers s0...s31
8146 32...63: double-precision registers d0...d31.
906e58ca 8147
c7b8f16e
JB		 8148 Although X should be zero for VFP11 (encoding d0...d15 only), we might
8149 encounter VFP3 instructions, so we allow the full range for DP registers. */
906e58ca 8150
c7b8f16e
JB		 8151static unsigned int
8152bfd_arm_vfp11_regno (unsigned int insn, bfd_boolean is_double, unsigned int rx,
99059e56 8153 unsigned int x)
c7b8f16e
JB		 8154{
8155 if (is_double)
8156 return (((insn >> rx) & 0xf) | (((insn >> x) & 1) << 4)) + 32;
8157 else
8158 return (((insn >> rx) & 0xf) << 1) | ((insn >> x) & 1);
8159}
8160
8161/* Set bits in *WMASK according to a register number REG as encoded by
8162 bfd_arm_vfp11_regno(). Ignore d16-d31. */
8163
8164static void
8165bfd_arm_vfp11_write_mask (unsigned int *wmask, unsigned int reg)
8166{
8167 if (reg < 32)
8168 *wmask |= 1 << reg;
8169 else if (reg < 48)
8170 *wmask |= 3 << ((reg - 32) * 2);
8171}
8172
8173/* Return TRUE if WMASK overwrites anything in REGS. */
8174
8175static bfd_boolean
8176bfd_arm_vfp11_antidependency (unsigned int wmask, int *regs, int numregs)
8177{
8178 int i;
906e58ca 8179
c7b8f16e
JB		 8180 for (i = 0; i < numregs; i++)
8181 {
8182 unsigned int reg = regs[i];
8183
8184 if (reg < 32 && (wmask & (1 << reg)) != 0)
99059e56 8185 return TRUE;
906e58ca 8186
c7b8f16e
JB		 8187 reg -= 32;
8188
8189 if (reg >= 16)
99059e56 8190 continue;
906e58ca 8191
c7b8f16e 8192 if ((wmask & (3 << (reg * 2))) != 0)
99059e56 8193 return TRUE;
c7b8f16e 8194 }
906e58ca 8195
c7b8f16e
JB		 8196 return FALSE;
8197}
8198
8199/* In this function, we're interested in two things: finding input registers
8200 for VFP data-processing instructions, and finding the set of registers which
8201 arbitrary VFP instructions may write to. We use a 32-bit unsigned int to
8202 hold the written set, so FLDM etc. are easy to deal with (we're only
8203 interested in 32 SP registers or 16 dp registers, due to the VFP version
8204 implemented by the chip in question). DP registers are marked by setting
8205 both SP registers in the write mask). */
8206
8207static enum bfd_arm_vfp11_pipe
8208bfd_arm_vfp11_insn_decode (unsigned int insn, unsigned int *destmask, int *regs,
99059e56 8209 int *numregs)
c7b8f16e 8210{
91d6fa6a 8211 enum bfd_arm_vfp11_pipe vpipe = VFP11_BAD;
c7b8f16e
JB		 8212 bfd_boolean is_double = ((insn & 0xf00) == 0xb00) ? 1 : 0;
8213
8214 if ((insn & 0x0f000e10) == 0x0e000a00) /* A data-processing insn. */
8215 {
8216 unsigned int pqrs;
8217 unsigned int fd = bfd_arm_vfp11_regno (insn, is_double, 12, 22);
8218 unsigned int fm = bfd_arm_vfp11_regno (insn, is_double, 0, 5);
8219
8220 pqrs = ((insn & 0x00800000) >> 20)
99059e56
RM		 8221 | ((insn & 0x00300000) >> 19)
8222 | ((insn & 0x00000040) >> 6);
c7b8f16e
JB		 8223
8224 switch (pqrs)
99059e56
RM		 8225 {
8226 case 0: /* fmac[sd]. */
8227 case 1: /* fnmac[sd]. */
8228 case 2: /* fmsc[sd]. */
8229 case 3: /* fnmsc[sd]. */
8230 vpipe = VFP11_FMAC;
8231 bfd_arm_vfp11_write_mask (destmask, fd);
8232 regs[0] = fd;
8233 regs[1] = bfd_arm_vfp11_regno (insn, is_double, 16, 7); /* Fn. */
8234 regs[2] = fm;
8235 *numregs = 3;
8236 break;
8237
8238 case 4: /* fmul[sd]. */
8239 case 5: /* fnmul[sd]. */
8240 case 6: /* fadd[sd]. */
8241 case 7: /* fsub[sd]. */
8242 vpipe = VFP11_FMAC;
8243 goto vfp_binop;
8244
8245 case 8: /* fdiv[sd]. */
8246 vpipe = VFP11_DS;
8247 vfp_binop:
8248 bfd_arm_vfp11_write_mask (destmask, fd);
8249 regs[0] = bfd_arm_vfp11_regno (insn, is_double, 16, 7); /* Fn. */
8250 regs[1] = fm;
8251 *numregs = 2;
8252 break;
8253
8254 case 15: /* extended opcode. */
8255 {
8256 unsigned int extn = ((insn >> 15) & 0x1e)
8257 | ((insn >> 7) & 1);
8258
8259 switch (extn)
8260 {
8261 case 0: /* fcpy[sd]. */
8262 case 1: /* fabs[sd]. */
8263 case 2: /* fneg[sd]. */
8264 case 8: /* fcmp[sd]. */
8265 case 9: /* fcmpe[sd]. */
8266 case 10: /* fcmpz[sd]. */
8267 case 11: /* fcmpez[sd]. */
8268 case 16: /* fuito[sd]. */
8269 case 17: /* fsito[sd]. */
8270 case 24: /* ftoui[sd]. */
8271 case 25: /* ftouiz[sd]. */
8272 case 26: /* ftosi[sd]. */
8273 case 27: /* ftosiz[sd]. */
8274 /* These instructions will not bounce due to underflow. */
8275 *numregs = 0;
8276 vpipe = VFP11_FMAC;
8277 break;
8278
8279 case 3: /* fsqrt[sd]. */
8280 /* fsqrt cannot underflow, but it can (perhaps) overwrite
8281 registers to cause the erratum in previous instructions. */
8282 bfd_arm_vfp11_write_mask (destmask, fd);
8283 vpipe = VFP11_DS;
8284 break;
8285
8286 case 15: /* fcvt{ds,sd}. */
8287 {
8288 int rnum = 0;
8289
8290 bfd_arm_vfp11_write_mask (destmask, fd);
c7b8f16e
JB		 8291
8292 /* Only FCVTSD can underflow. */
99059e56
RM		 8293 if ((insn & 0x100) != 0)
8294 regs[rnum++] = fm;
c7b8f16e 8295
99059e56 8296 *numregs = rnum;
c7b8f16e 8297
99059e56
RM		 8298 vpipe = VFP11_FMAC;
8299 }
8300 break;
c7b8f16e 8301
99059e56
RM		 8302 default:
8303 return VFP11_BAD;
8304 }
8305 }
8306 break;
c7b8f16e 8307
99059e56
RM		 8308 default:
8309 return VFP11_BAD;
8310 }
c7b8f16e
JB		 8311 }
8312 /* Two-register transfer. */
8313 else if ((insn & 0x0fe00ed0) == 0x0c400a10)
8314 {
8315 unsigned int fm = bfd_arm_vfp11_regno (insn, is_double, 0, 5);
906e58ca 8316
c7b8f16e
JB		 8317 if ((insn & 0x100000) == 0)
8318 {
99059e56
RM		 8319 if (is_double)
8320 bfd_arm_vfp11_write_mask (destmask, fm);
8321 else
8322 {
8323 bfd_arm_vfp11_write_mask (destmask, fm);
8324 bfd_arm_vfp11_write_mask (destmask, fm + 1);
8325 }
c7b8f16e
JB		 8326 }
8327
91d6fa6a 8328 vpipe = VFP11_LS;
c7b8f16e
JB		 8329 }
8330 else if ((insn & 0x0e100e00) == 0x0c100a00) /* A load insn. */
8331 {
8332 int fd = bfd_arm_vfp11_regno (insn, is_double, 12, 22);
8333 unsigned int puw = ((insn >> 21) & 0x1) | (((insn >> 23) & 3) << 1);
906e58ca 8334
c7b8f16e 8335 switch (puw)
99059e56
RM		 8336 {
8337 case 0: /* Two-reg transfer. We should catch these above. */
8338 abort ();
906e58ca 8339
99059e56
RM		 8340 case 2: /* fldm[sdx]. */
8341 case 3:
8342 case 5:
8343 {
8344 unsigned int i, offset = insn & 0xff;
c7b8f16e 8345
99059e56
RM		 8346 if (is_double)
8347 offset >>= 1;
c7b8f16e 8348
99059e56
RM		 8349 for (i = fd; i < fd + offset; i++)
8350 bfd_arm_vfp11_write_mask (destmask, i);
8351 }
8352 break;
906e58ca 8353
99059e56
RM		 8354 case 4: /* fld[sd]. */
8355 case 6:
8356 bfd_arm_vfp11_write_mask (destmask, fd);
8357 break;
906e58ca 8358
99059e56
RM		 8359 default:
8360 return VFP11_BAD;
8361 }
c7b8f16e 8362
91d6fa6a 8363 vpipe = VFP11_LS;
c7b8f16e
JB		 8364 }
8365 /* Single-register transfer. Note L==0. */
8366 else if ((insn & 0x0f100e10) == 0x0e000a10)
8367 {
8368 unsigned int opcode = (insn >> 21) & 7;
8369 unsigned int fn = bfd_arm_vfp11_regno (insn, is_double, 16, 7);
8370
8371 switch (opcode)
99059e56
RM		 8372 {
8373 case 0: /* fmsr/fmdlr. */
8374 case 1: /* fmdhr. */
8375 /* Mark fmdhr and fmdlr as writing to the whole of the DP
8376 destination register. I don't know if this is exactly right,
8377 but it is the conservative choice. */
8378 bfd_arm_vfp11_write_mask (destmask, fn);
8379 break;
8380
8381 case 7: /* fmxr. */
8382 break;
8383 }
c7b8f16e 8384
91d6fa6a 8385 vpipe = VFP11_LS;
c7b8f16e
JB		 8386 }
8387
91d6fa6a 8388 return vpipe;
c7b8f16e
JB		 8389}
8390
8391
8392static int elf32_arm_compare_mapping (const void * a, const void * b);
8393
8394
8395/* Look for potentially-troublesome code sequences which might trigger the
8396 VFP11 denormal/antidependency erratum. See, e.g., the ARM1136 errata sheet
8397 (available from ARM) for details of the erratum. A short version is
8398 described in ld.texinfo. */
8399
8400bfd_boolean
8401bfd_elf32_arm_vfp11_erratum_scan (bfd *abfd, struct bfd_link_info *link_info)
8402{
8403 asection *sec;
8404 bfd_byte *contents = NULL;
8405 int state = 0;
8406 int regs[3], numregs = 0;
8407 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (link_info);
8408 int use_vector = (globals->vfp11_fix == BFD_ARM_VFP11_FIX_VECTOR);
906e58ca 8409
4dfe6ac6
NC		 8410 if (globals == NULL)
8411 return FALSE;
8412
c7b8f16e
JB		 8413 /* We use a simple FSM to match troublesome VFP11 instruction sequences.
8414 The states transition as follows:
906e58ca 8415
c7b8f16e 8416 0 -> 1 (vector) or 0 -> 2 (scalar)
99059e56
RM		 8417 A VFP FMAC-pipeline instruction has been seen. Fill
8418 regs[0]..regs[numregs-1] with its input operands. Remember this
8419 instruction in 'first_fmac'.
c7b8f16e
JB		 8420
8421 1 -> 2
99059e56
RM		 8422 Any instruction, except for a VFP instruction which overwrites
8423 regs[*].
906e58ca 8424
c7b8f16e
JB		 8425 1 -> 3 [ -> 0 ] or
8426 2 -> 3 [ -> 0 ]
99059e56
RM		 8427 A VFP instruction has been seen which overwrites any of regs[*].
8428 We must make a veneer! Reset state to 0 before examining next
8429 instruction.
906e58ca 8430
c7b8f16e 8431 2 -> 0
99059e56
RM		 8432 If we fail to match anything in state 2, reset to state 0 and reset
8433 the instruction pointer to the instruction after 'first_fmac'.
c7b8f16e
JB		 8434
8435 If the VFP11 vector mode is in use, there must be at least two unrelated
8436 instructions between anti-dependent VFP11 instructions to properly avoid
906e58ca 8437 triggering the erratum, hence the use of the extra state 1. */
c7b8f16e
JB		 8438
8439 /* If we are only performing a partial link do not bother
8440 to construct any glue. */
0e1862bb 8441 if (bfd_link_relocatable (link_info))
c7b8f16e
JB		 8442 return TRUE;
8443
0ffa91dd
NC		 8444 /* Skip if this bfd does not correspond to an ELF image. */
8445 if (! is_arm_elf (abfd))
8446 return TRUE;
906e58ca 8447
c7b8f16e
JB		 8448 /* We should have chosen a fix type by the time we get here. */
8449 BFD_ASSERT (globals->vfp11_fix != BFD_ARM_VFP11_FIX_DEFAULT);
8450
8451 if (globals->vfp11_fix == BFD_ARM_VFP11_FIX_NONE)
8452 return TRUE;
2e6030b9 8453
33a7ffc2
JM		 8454 /* Skip this BFD if it corresponds to an executable or dynamic object. */
8455 if ((abfd->flags & (EXEC_P | DYNAMIC)) != 0)
8456 return TRUE;
8457
c7b8f16e
JB		 8458 for (sec = abfd->sections; sec != NULL; sec = sec->next)
8459 {
8460 unsigned int i, span, first_fmac = 0, veneer_of_insn = 0;
8461 struct _arm_elf_section_data *sec_data;
8462
8463 /* If we don't have executable progbits, we're not interested in this
99059e56 8464 section. Also skip if section is to be excluded. */
c7b8f16e 8465 if (elf_section_type (sec) != SHT_PROGBITS
99059e56
RM		 8466 || (elf_section_flags (sec) & SHF_EXECINSTR) == 0
8467 || (sec->flags & SEC_EXCLUDE) != 0
dbaa2011 8468 || sec->sec_info_type == SEC_INFO_TYPE_JUST_SYMS
33a7ffc2 8469 || sec->output_section == bfd_abs_section_ptr
99059e56
RM		 8470 || strcmp (sec->name, VFP11_ERRATUM_VENEER_SECTION_NAME) == 0)
8471 continue;
c7b8f16e
JB		 8472
8473 sec_data = elf32_arm_section_data (sec);
906e58ca 8474
c7b8f16e 8475 if (sec_data->mapcount == 0)
99059e56 8476 continue;
906e58ca 8477
c7b8f16e
JB		 8478 if (elf_section_data (sec)->this_hdr.contents != NULL)
8479 contents = elf_section_data (sec)->this_hdr.contents;
8480 else if (! bfd_malloc_and_get_section (abfd, sec, &contents))
8481 goto error_return;
8482
8483 qsort (sec_data->map, sec_data->mapcount, sizeof (elf32_arm_section_map),
8484 elf32_arm_compare_mapping);
8485
8486 for (span = 0; span < sec_data->mapcount; span++)
99059e56
RM		 8487 {
8488 unsigned int span_start = sec_data->map[span].vma;
8489 unsigned int span_end = (span == sec_data->mapcount - 1)
c7b8f16e 8490 ? sec->size : sec_data->map[span + 1].vma;
99059e56
RM		 8491 char span_type = sec_data->map[span].type;
8492
8493 /* FIXME: Only ARM mode is supported at present. We may need to
8494 support Thumb-2 mode also at some point. */
8495 if (span_type != 'a')
8496 continue;
8497
8498 for (i = span_start; i < span_end;)
8499 {
8500 unsigned int next_i = i + 4;
8501 unsigned int insn = bfd_big_endian (abfd)
8502 ? (contents[i] << 24)
8503 | (contents[i + 1] << 16)
8504 | (contents[i + 2] << 8)
8505 | contents[i + 3]
8506 : (contents[i + 3] << 24)
8507 | (contents[i + 2] << 16)
8508 | (contents[i + 1] << 8)
8509 | contents[i];
8510 unsigned int writemask = 0;
8511 enum bfd_arm_vfp11_pipe vpipe;
8512
8513 switch (state)
8514 {
8515 case 0:
8516 vpipe = bfd_arm_vfp11_insn_decode (insn, &writemask, regs,
8517 &numregs);
8518 /* I'm assuming the VFP11 erratum can trigger with denorm
8519 operands on either the FMAC or the DS pipeline. This might
8520 lead to slightly overenthusiastic veneer insertion. */
8521 if (vpipe == VFP11_FMAC || vpipe == VFP11_DS)
8522 {
8523 state = use_vector ? 1 : 2;
8524 first_fmac = i;
8525 veneer_of_insn = insn;
8526 }
8527 break;
8528
8529 case 1:
8530 {
8531 int other_regs[3], other_numregs;
8532 vpipe = bfd_arm_vfp11_insn_decode (insn, &writemask,
c7b8f16e 8533 other_regs,
99059e56
RM		 8534 &other_numregs);
8535 if (vpipe != VFP11_BAD
8536 && bfd_arm_vfp11_antidependency (writemask, regs,
c7b8f16e 8537 numregs))
99059e56
RM		 8538 state = 3;
8539 else
8540 state = 2;
8541 }
8542 break;
8543
8544 case 2:
8545 {
8546 int other_regs[3], other_numregs;
8547 vpipe = bfd_arm_vfp11_insn_decode (insn, &writemask,
c7b8f16e 8548 other_regs,
99059e56
RM		 8549 &other_numregs);
8550 if (vpipe != VFP11_BAD
8551 && bfd_arm_vfp11_antidependency (writemask, regs,
c7b8f16e 8552 numregs))
99059e56
RM		 8553 state = 3;
8554 else
8555 {
8556 state = 0;
8557 next_i = first_fmac + 4;
8558 }
8559 }
8560 break;
8561
8562 case 3:
8563 abort (); /* Should be unreachable. */
8564 }
8565
8566 if (state == 3)
8567 {
8568 elf32_vfp11_erratum_list *newerr =(elf32_vfp11_erratum_list *)
8569 bfd_zmalloc (sizeof (elf32_vfp11_erratum_list));
8570
8571 elf32_arm_section_data (sec)->erratumcount += 1;
8572
8573 newerr->u.b.vfp_insn = veneer_of_insn;
8574
8575 switch (span_type)
8576 {
8577 case 'a':
8578 newerr->type = VFP11_ERRATUM_BRANCH_TO_ARM_VENEER;
8579 break;
8580
8581 default:
8582 abort ();
8583 }
8584
8585 record_vfp11_erratum_veneer (link_info, newerr, abfd, sec,
c7b8f16e
JB		 8586 first_fmac);
8587
99059e56 8588 newerr->vma = -1;
c7b8f16e 8589
99059e56
RM		 8590 newerr->next = sec_data->erratumlist;
8591 sec_data->erratumlist = newerr;
c7b8f16e 8592
99059e56
RM		 8593 state = 0;
8594 }
c7b8f16e 8595
99059e56
RM		 8596 i = next_i;
8597 }
8598 }
906e58ca 8599
c7b8f16e 8600 if (contents != NULL
99059e56
RM		 8601 && elf_section_data (sec)->this_hdr.contents != contents)
8602 free (contents);
c7b8f16e
JB		 8603 contents = NULL;
8604 }
8605
8606 return TRUE;
8607
8608error_return:
8609 if (contents != NULL
8610 && elf_section_data (sec)->this_hdr.contents != contents)
8611 free (contents);
906e58ca 8612
c7b8f16e
JB		 8613 return FALSE;
8614}
8615
8616/* Find virtual-memory addresses for VFP11 erratum veneers and return locations
8617 after sections have been laid out, using specially-named symbols. */
8618
8619void
8620bfd_elf32_arm_vfp11_fix_veneer_locations (bfd *abfd,
8621 struct bfd_link_info *link_info)
8622{
8623 asection *sec;
8624 struct elf32_arm_link_hash_table *globals;
8625 char *tmp_name;
906e58ca 8626
0e1862bb 8627 if (bfd_link_relocatable (link_info))
c7b8f16e 8628 return;
2e6030b9
MS		 8629
8630 /* Skip if this bfd does not correspond to an ELF image. */
0ffa91dd 8631 if (! is_arm_elf (abfd))
2e6030b9
MS		 8632 return;
8633
c7b8f16e 8634 globals = elf32_arm_hash_table (link_info);
4dfe6ac6
NC		 8635 if (globals == NULL)
8636 return;
906e58ca 8637
21d799b5 8638 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen
99059e56 8639 (VFP11_ERRATUM_VENEER_ENTRY_NAME) + 10);
c7b8f16e
JB		 8640
8641 for (sec = abfd->sections; sec != NULL; sec = sec->next)
8642 {
8643 struct _arm_elf_section_data *sec_data = elf32_arm_section_data (sec);
8644 elf32_vfp11_erratum_list *errnode = sec_data->erratumlist;
906e58ca 8645
c7b8f16e 8646 for (; errnode != NULL; errnode = errnode->next)
99059e56
RM		 8647 {
8648 struct elf_link_hash_entry *myh;
8649 bfd_vma vma;
8650
8651 switch (errnode->type)
8652 {
8653 case VFP11_ERRATUM_BRANCH_TO_ARM_VENEER:
8654 case VFP11_ERRATUM_BRANCH_TO_THUMB_VENEER:
8655 /* Find veneer symbol. */
8656 sprintf (tmp_name, VFP11_ERRATUM_VENEER_ENTRY_NAME,
c7b8f16e
JB		 8657 errnode->u.b.veneer->u.v.id);
8658
99059e56
RM		 8659 myh = elf_link_hash_lookup
8660 (&(globals)->root, tmp_name, FALSE, FALSE, TRUE);
c7b8f16e 8661
a504d23a 8662 if (myh == NULL)
90b6238f
AM		 8663 _bfd_error_handler (_("%pB: unable to find %s veneer `%s'"),
8664 abfd, "VFP11", tmp_name);
a504d23a
LA		 8665
8666 vma = myh->root.u.def.section->output_section->vma
8667 + myh->root.u.def.section->output_offset
8668 + myh->root.u.def.value;
8669
8670 errnode->u.b.veneer->vma = vma;
8671 break;
8672
8673 case VFP11_ERRATUM_ARM_VENEER:
8674 case VFP11_ERRATUM_THUMB_VENEER:
8675 /* Find return location. */
8676 sprintf (tmp_name, VFP11_ERRATUM_VENEER_ENTRY_NAME "_r",
8677 errnode->u.v.id);
8678
8679 myh = elf_link_hash_lookup
8680 (&(globals)->root, tmp_name, FALSE, FALSE, TRUE);
8681
8682 if (myh == NULL)
90b6238f
AM		 8683 _bfd_error_handler (_("%pB: unable to find %s veneer `%s'"),
8684 abfd, "VFP11", tmp_name);
a504d23a
LA		 8685
8686 vma = myh->root.u.def.section->output_section->vma
8687 + myh->root.u.def.section->output_offset
8688 + myh->root.u.def.value;
8689
8690 errnode->u.v.branch->vma = vma;
8691 break;
8692
8693 default:
8694 abort ();
8695 }
8696 }
8697 }
8698
8699 free (tmp_name);
8700}
8701
8702/* Find virtual-memory addresses for STM32L4XX erratum veneers and
8703 return locations after sections have been laid out, using
8704 specially-named symbols. */
8705
8706void
8707bfd_elf32_arm_stm32l4xx_fix_veneer_locations (bfd *abfd,
8708 struct bfd_link_info *link_info)
8709{
8710 asection *sec;
8711 struct elf32_arm_link_hash_table *globals;
8712 char *tmp_name;
8713
8714 if (bfd_link_relocatable (link_info))
8715 return;
8716
8717 /* Skip if this bfd does not correspond to an ELF image. */
8718 if (! is_arm_elf (abfd))
8719 return;
8720
8721 globals = elf32_arm_hash_table (link_info);
8722 if (globals == NULL)
8723 return;
8724
8725 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen
8726 (STM32L4XX_ERRATUM_VENEER_ENTRY_NAME) + 10);
8727
8728 for (sec = abfd->sections; sec != NULL; sec = sec->next)
8729 {
8730 struct _arm_elf_section_data *sec_data = elf32_arm_section_data (sec);
8731 elf32_stm32l4xx_erratum_list *errnode = sec_data->stm32l4xx_erratumlist;
8732
8733 for (; errnode != NULL; errnode = errnode->next)
8734 {
8735 struct elf_link_hash_entry *myh;
8736 bfd_vma vma;
8737
8738 switch (errnode->type)
8739 {
8740 case STM32L4XX_ERRATUM_BRANCH_TO_VENEER:
8741 /* Find veneer symbol. */
8742 sprintf (tmp_name, STM32L4XX_ERRATUM_VENEER_ENTRY_NAME,
8743 errnode->u.b.veneer->u.v.id);
8744
8745 myh = elf_link_hash_lookup
8746 (&(globals)->root, tmp_name, FALSE, FALSE, TRUE);
8747
8748 if (myh == NULL)
90b6238f
AM		 8749 _bfd_error_handler (_("%pB: unable to find %s veneer `%s'"),
8750 abfd, "STM32L4XX", tmp_name);
a504d23a
LA		 8751
8752 vma = myh->root.u.def.section->output_section->vma
8753 + myh->root.u.def.section->output_offset
8754 + myh->root.u.def.value;
8755
8756 errnode->u.b.veneer->vma = vma;
8757 break;
8758
8759 case STM32L4XX_ERRATUM_VENEER:
8760 /* Find return location. */
8761 sprintf (tmp_name, STM32L4XX_ERRATUM_VENEER_ENTRY_NAME "_r",
8762 errnode->u.v.id);
8763
8764 myh = elf_link_hash_lookup
8765 (&(globals)->root, tmp_name, FALSE, FALSE, TRUE);
8766
8767 if (myh == NULL)
90b6238f
AM		 8768 _bfd_error_handler (_("%pB: unable to find %s veneer `%s'"),
8769 abfd, "STM32L4XX", tmp_name);
a504d23a
LA		 8770
8771 vma = myh->root.u.def.section->output_section->vma
8772 + myh->root.u.def.section->output_offset
8773 + myh->root.u.def.value;
8774
8775 errnode->u.v.branch->vma = vma;
8776 break;
8777
8778 default:
8779 abort ();
8780 }
8781 }
8782 }
8783
8784 free (tmp_name);
8785}
8786
8787static inline bfd_boolean
8788is_thumb2_ldmia (const insn32 insn)
8789{
8790 /* Encoding T2: LDM<c>.W <Rn>{!},<registers>
8791 1110 - 1000 - 10W1 - rrrr - PM (0) l - llll - llll - llll. */
8792 return (insn & 0xffd02000) == 0xe8900000;
8793}
8794
8795static inline bfd_boolean
8796is_thumb2_ldmdb (const insn32 insn)
8797{
8798 /* Encoding T1: LDMDB<c> <Rn>{!},<registers>
8799 1110 - 1001 - 00W1 - rrrr - PM (0) l - llll - llll - llll. */
8800 return (insn & 0xffd02000) == 0xe9100000;
8801}
8802
8803static inline bfd_boolean
8804is_thumb2_vldm (const insn32 insn)
8805{
8806 /* A6.5 Extension register load or store instruction
8807 A7.7.229
9239bbd3
CM		 8808 We look for SP 32-bit and DP 64-bit registers.
8809 Encoding T1 VLDM{mode}<c> <Rn>{!}, <list>
8810 <list> is consecutive 64-bit registers
8811 1110 - 110P - UDW1 - rrrr - vvvv - 1011 - iiii - iiii
a504d23a
LA		 8812 Encoding T2 VLDM{mode}<c> <Rn>{!}, <list>
8813 <list> is consecutive 32-bit registers
8814 1110 - 110P - UDW1 - rrrr - vvvv - 1010 - iiii - iiii
8815 if P==0 && U==1 && W==1 && Rn=1101 VPOP
8816 if PUW=010 || PUW=011 || PUW=101 VLDM. */
8817 return
9239bbd3
CM		 8818 (((insn & 0xfe100f00) == 0xec100b00) ||
8819 ((insn & 0xfe100f00) == 0xec100a00))
a504d23a
LA		 8820 && /* (IA without !). */
8821 (((((insn << 7) >> 28) & 0xd) == 0x4)
9239bbd3 8822 /* (IA with !), includes VPOP (when reg number is SP). */
a504d23a
LA		 8823 || ((((insn << 7) >> 28) & 0xd) == 0x5)
8824 /* (DB with !). */
8825 || ((((insn << 7) >> 28) & 0xd) == 0x9));
8826}
8827
8828/* STM STM32L4XX erratum : This function assumes that it receives an LDM or
8829 VLDM opcode and:
8830 - computes the number and the mode of memory accesses
8831 - decides if the replacement should be done:
8832 . replaces only if > 8-word accesses
8833 . or (testing purposes only) replaces all accesses. */
8834
8835static bfd_boolean
8836stm32l4xx_need_create_replacing_stub (const insn32 insn,
8837 bfd_arm_stm32l4xx_fix stm32l4xx_fix)
8838{
9239bbd3 8839 int nb_words = 0;
a504d23a
LA		 8840
8841 /* The field encoding the register list is the same for both LDMIA
8842 and LDMDB encodings. */
8843 if (is_thumb2_ldmia (insn) || is_thumb2_ldmdb (insn))
b25e998d 8844 nb_words = elf32_arm_popcount (insn & 0x0000ffff);
a504d23a 8845 else if (is_thumb2_vldm (insn))
9239bbd3 8846 nb_words = (insn & 0xff);
a504d23a
LA		 8847
8848 /* DEFAULT mode accounts for the real bug condition situation,
8849 ALL mode inserts stubs for each LDM/VLDM instruction (testing). */
8850 return
9239bbd3 8851 (stm32l4xx_fix == BFD_ARM_STM32L4XX_FIX_DEFAULT) ? nb_words > 8 :
a504d23a
LA		 8852 (stm32l4xx_fix == BFD_ARM_STM32L4XX_FIX_ALL) ? TRUE : FALSE;
8853}
8854
8855/* Look for potentially-troublesome code sequences which might trigger
8856 the STM STM32L4XX erratum. */
8857
8858bfd_boolean
8859bfd_elf32_arm_stm32l4xx_erratum_scan (bfd *abfd,
8860 struct bfd_link_info *link_info)
8861{
8862 asection *sec;
8863 bfd_byte *contents = NULL;
8864 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (link_info);
8865
8866 if (globals == NULL)
8867 return FALSE;
8868
8869 /* If we are only performing a partial link do not bother
8870 to construct any glue. */
8871 if (bfd_link_relocatable (link_info))
8872 return TRUE;
8873
8874 /* Skip if this bfd does not correspond to an ELF image. */
8875 if (! is_arm_elf (abfd))
8876 return TRUE;
8877
8878 if (globals->stm32l4xx_fix == BFD_ARM_STM32L4XX_FIX_NONE)
8879 return TRUE;
8880
8881 /* Skip this BFD if it corresponds to an executable or dynamic object. */
8882 if ((abfd->flags & (EXEC_P | DYNAMIC)) != 0)
8883 return TRUE;
8884
8885 for (sec = abfd->sections; sec != NULL; sec = sec->next)
8886 {
8887 unsigned int i, span;
8888 struct _arm_elf_section_data *sec_data;
8889
8890 /* If we don't have executable progbits, we're not interested in this
8891 section. Also skip if section is to be excluded. */
8892 if (elf_section_type (sec) != SHT_PROGBITS
8893 || (elf_section_flags (sec) & SHF_EXECINSTR) == 0
8894 || (sec->flags & SEC_EXCLUDE) != 0
8895 || sec->sec_info_type == SEC_INFO_TYPE_JUST_SYMS
8896 || sec->output_section == bfd_abs_section_ptr
8897 || strcmp (sec->name, STM32L4XX_ERRATUM_VENEER_SECTION_NAME) == 0)
8898 continue;
8899
8900 sec_data = elf32_arm_section_data (sec);
c7b8f16e 8901
a504d23a
LA		 8902 if (sec_data->mapcount == 0)
8903 continue;
c7b8f16e 8904
a504d23a
LA		 8905 if (elf_section_data (sec)->this_hdr.contents != NULL)
8906 contents = elf_section_data (sec)->this_hdr.contents;
8907 else if (! bfd_malloc_and_get_section (abfd, sec, &contents))
8908 goto error_return;
c7b8f16e 8909
a504d23a
LA		 8910 qsort (sec_data->map, sec_data->mapcount, sizeof (elf32_arm_section_map),
8911 elf32_arm_compare_mapping);
c7b8f16e 8912
a504d23a
LA		 8913 for (span = 0; span < sec_data->mapcount; span++)
8914 {
8915 unsigned int span_start = sec_data->map[span].vma;
8916 unsigned int span_end = (span == sec_data->mapcount - 1)
8917 ? sec->size : sec_data->map[span + 1].vma;
8918 char span_type = sec_data->map[span].type;
8919 int itblock_current_pos = 0;
c7b8f16e 8920
a504d23a
LA		 8921 /* Only Thumb2 mode need be supported with this CM4 specific
8922 code, we should not encounter any arm mode eg span_type
8923 != 'a'. */
8924 if (span_type != 't')
8925 continue;
c7b8f16e 8926
a504d23a
LA		 8927 for (i = span_start; i < span_end;)
8928 {
8929 unsigned int insn = bfd_get_16 (abfd, &contents[i]);
8930 bfd_boolean insn_32bit = FALSE;
8931 bfd_boolean is_ldm = FALSE;
8932 bfd_boolean is_vldm = FALSE;
8933 bfd_boolean is_not_last_in_it_block = FALSE;
8934
8935 /* The first 16-bits of all 32-bit thumb2 instructions start
8936 with opcode[15..13]=0b111 and the encoded op1 can be anything
8937 except opcode[12..11]!=0b00.
8938 See 32-bit Thumb instruction encoding. */
8939 if ((insn & 0xe000) == 0xe000 && (insn & 0x1800) != 0x0000)
8940 insn_32bit = TRUE;
c7b8f16e 8941
a504d23a
LA		 8942 /* Compute the predicate that tells if the instruction
8943 is concerned by the IT block
8944 - Creates an error if there is a ldm that is not
8945 last in the IT block thus cannot be replaced
8946 - Otherwise we can create a branch at the end of the
8947 IT block, it will be controlled naturally by IT
8948 with the proper pseudo-predicate
8949 - So the only interesting predicate is the one that
8950 tells that we are not on the last item of an IT
8951 block. */
8952 if (itblock_current_pos != 0)
8953 is_not_last_in_it_block = !!--itblock_current_pos;
906e58ca 8954
a504d23a
LA		 8955 if (insn_32bit)
8956 {
8957 /* Load the rest of the insn (in manual-friendly order). */
8958 insn = (insn << 16) | bfd_get_16 (abfd, &contents[i + 2]);
8959 is_ldm = is_thumb2_ldmia (insn) || is_thumb2_ldmdb (insn);
8960 is_vldm = is_thumb2_vldm (insn);
8961
8962 /* Veneers are created for (v)ldm depending on
8963 option flags and memory accesses conditions; but
8964 if the instruction is not the last instruction of
8965 an IT block, we cannot create a jump there, so we
8966 bail out. */
5025eb7c
AO		 8967 if ((is_ldm || is_vldm)
8968 && stm32l4xx_need_create_replacing_stub
a504d23a
LA		 8969 (insn, globals->stm32l4xx_fix))
8970 {
8971 if (is_not_last_in_it_block)
8972 {
4eca0228 8973 _bfd_error_handler
695344c0 8974 /* xgettext:c-format */
871b3ab2 8975 (_("%pB(%pA+%#x): error: multiple load detected"
90b6238f
AM		 8976 " in non-last IT block instruction:"
8977 " STM32L4XX veneer cannot be generated; "
8978 "use gcc option -mrestrict-it to generate"
8979 " only one instruction per IT block"),
d42c267e 8980 abfd, sec, i);
a504d23a
LA		 8981 }
8982 else
8983 {
8984 elf32_stm32l4xx_erratum_list *newerr =
8985 (elf32_stm32l4xx_erratum_list *)
8986 bfd_zmalloc
8987 (sizeof (elf32_stm32l4xx_erratum_list));
8988
8989 elf32_arm_section_data (sec)
8990 ->stm32l4xx_erratumcount += 1;
8991 newerr->u.b.insn = insn;
8992 /* We create only thumb branches. */
8993 newerr->type =
8994 STM32L4XX_ERRATUM_BRANCH_TO_VENEER;
8995 record_stm32l4xx_erratum_veneer
8996 (link_info, newerr, abfd, sec,
8997 i,
8998 is_ldm ?
8999 STM32L4XX_ERRATUM_LDM_VENEER_SIZE:
9000 STM32L4XX_ERRATUM_VLDM_VENEER_SIZE);
9001 newerr->vma = -1;
9002 newerr->next = sec_data->stm32l4xx_erratumlist;
9003 sec_data->stm32l4xx_erratumlist = newerr;
9004 }
9005 }
9006 }
9007 else
9008 {
9009 /* A7.7.37 IT p208
9010 IT blocks are only encoded in T1
9011 Encoding T1: IT{x{y{z}}} <firstcond>
9012 1 0 1 1 - 1 1 1 1 - firstcond - mask
9013 if mask = '0000' then see 'related encodings'
9014 We don't deal with UNPREDICTABLE, just ignore these.
9015 There can be no nested IT blocks so an IT block
9016 is naturally a new one for which it is worth
9017 computing its size. */
5025eb7c
AO		 9018 bfd_boolean is_newitblock = ((insn & 0xff00) == 0xbf00)
9019 && ((insn & 0x000f) != 0x0000);
a504d23a
LA		 9020 /* If we have a new IT block we compute its size. */
9021 if (is_newitblock)
9022 {
9023 /* Compute the number of instructions controlled
9024 by the IT block, it will be used to decide
9025 whether we are inside an IT block or not. */
9026 unsigned int mask = insn & 0x000f;
9027 itblock_current_pos = 4 - ctz (mask);
9028 }
9029 }
9030
9031 i += insn_32bit ? 4 : 2;
99059e56
RM		 9032 }
9033 }
a504d23a
LA		 9034
9035 if (contents != NULL
9036 && elf_section_data (sec)->this_hdr.contents != contents)
9037 free (contents);
9038 contents = NULL;
c7b8f16e 9039 }
906e58ca 9040
a504d23a
LA		 9041 return TRUE;
9042
9043error_return:
9044 if (contents != NULL
9045 && elf_section_data (sec)->this_hdr.contents != contents)
9046 free (contents);
c7b8f16e 9047
a504d23a
LA		 9048 return FALSE;
9049}
c7b8f16e 9050
eb043451
PB		 9051/* Set target relocation values needed during linking. */
9052
9053void
68c39892 9054bfd_elf32_arm_set_target_params (struct bfd *output_bfd,
bf21ed78 9055 struct bfd_link_info *link_info,
68c39892 9056 struct elf32_arm_params *params)
eb043451
PB		 9057{
9058 struct elf32_arm_link_hash_table *globals;
9059
9060 globals = elf32_arm_hash_table (link_info);
4dfe6ac6
NC		 9061 if (globals == NULL)
9062 return;
eb043451 9063
68c39892 9064 globals->target1_is_rel = params->target1_is_rel;
29e9b073
CL		 9065 if (globals->fdpic_p)
9066 globals->target2_reloc = R_ARM_GOT32;
9067 else if (strcmp (params->target2_type, "rel") == 0)
eb043451 9068 globals->target2_reloc = R_ARM_REL32;
68c39892 9069 else if (strcmp (params->target2_type, "abs") == 0)
eeac373a 9070 globals->target2_reloc = R_ARM_ABS32;
68c39892 9071 else if (strcmp (params->target2_type, "got-rel") == 0)
eb043451
PB		 9072 globals->target2_reloc = R_ARM_GOT_PREL;
9073 else
9074 {
90b6238f 9075 _bfd_error_handler (_("invalid TARGET2 relocation type '%s'"),
68c39892 9076 params->target2_type);
eb043451 9077 }
68c39892
TP		 9078 globals->fix_v4bx = params->fix_v4bx;
9079 globals->use_blx |= params->use_blx;
9080 globals->vfp11_fix = params->vfp11_denorm_fix;
9081 globals->stm32l4xx_fix = params->stm32l4xx_fix;
e8b09b87
CL		 9082 if (globals->fdpic_p)
9083 globals->pic_veneer = 1;
9084 else
9085 globals->pic_veneer = params->pic_veneer;
68c39892
TP		 9086 globals->fix_cortex_a8 = params->fix_cortex_a8;
9087 globals->fix_arm1176 = params->fix_arm1176;
9088 globals->cmse_implib = params->cmse_implib;
9089 globals->in_implib_bfd = params->in_implib_bfd;
bf21ed78 9090
0ffa91dd 9091 BFD_ASSERT (is_arm_elf (output_bfd));
68c39892
TP		 9092 elf_arm_tdata (output_bfd)->no_enum_size_warning
9093 = params->no_enum_size_warning;
9094 elf_arm_tdata (output_bfd)->no_wchar_size_warning
9095 = params->no_wchar_size_warning;
eb043451 9096}
eb043451 9097
12a0a0fd 9098/* Replace the target offset of a Thumb bl or b.w instruction. */
252b5132 9099
12a0a0fd
PB		 9100static void
9101insert_thumb_branch (bfd *abfd, long int offset, bfd_byte *insn)
9102{
9103 bfd_vma upper;
9104 bfd_vma lower;
9105 int reloc_sign;
9106
9107 BFD_ASSERT ((offset & 1) == 0);
9108
9109 upper = bfd_get_16 (abfd, insn);
9110 lower = bfd_get_16 (abfd, insn + 2);
9111 reloc_sign = (offset < 0) ? 1 : 0;
9112 upper = (upper & ~(bfd_vma) 0x7ff)
9113 | ((offset >> 12) & 0x3ff)
9114 | (reloc_sign << 10);
906e58ca 9115 lower = (lower & ~(bfd_vma) 0x2fff)
12a0a0fd
PB		 9116 | (((!((offset >> 23) & 1)) ^ reloc_sign) << 13)
9117 | (((!((offset >> 22) & 1)) ^ reloc_sign) << 11)
9118 | ((offset >> 1) & 0x7ff);
9119 bfd_put_16 (abfd, upper, insn);
9120 bfd_put_16 (abfd, lower, insn + 2);
252b5132
RH		 9121}
9122
9b485d32
NC		 9123/* Thumb code calling an ARM function. */
9124
252b5132 9125static int
57e8b36a 9126elf32_thumb_to_arm_stub (struct bfd_link_info * info,
07d6d2b8
AM		 9127 const char * name,
9128 bfd * input_bfd,
9129 bfd * output_bfd,
9130 asection * input_section,
9131 bfd_byte * hit_data,
9132 asection * sym_sec,
9133 bfd_vma offset,
9134 bfd_signed_vma addend,
9135 bfd_vma val,
f2a9dd69 9136 char **error_message)
252b5132 9137{
bcbdc74c 9138 asection * s = 0;
dc810e39 9139 bfd_vma my_offset;
252b5132 9140 long int ret_offset;
bcbdc74c
NC		 9141 struct elf_link_hash_entry * myh;
9142 struct elf32_arm_link_hash_table * globals;
252b5132 9143
f2a9dd69 9144 myh = find_thumb_glue (info, name, error_message);
252b5132 9145 if (myh == NULL)
b34976b6 9146 return FALSE;
252b5132
RH		 9147
9148 globals = elf32_arm_hash_table (info);
252b5132
RH		 9149 BFD_ASSERT (globals != NULL);
9150 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
9151
9152 my_offset = myh->root.u.def.value;
9153
3d4d4302
AM		 9154 s = bfd_get_linker_section (globals->bfd_of_glue_owner,
9155 THUMB2ARM_GLUE_SECTION_NAME);
252b5132
RH		 9156
9157 BFD_ASSERT (s != NULL);
9158 BFD_ASSERT (s->contents != NULL);
9159 BFD_ASSERT (s->output_section != NULL);
9160
9161 if ((my_offset & 0x01) == 0x01)
9162 {
9163 if (sym_sec != NULL
9164 && sym_sec->owner != NULL
9165 && !INTERWORK_FLAG (sym_sec->owner))
9166 {
4eca0228 9167 _bfd_error_handler
90b6238f
AM		 9168 (_("%pB(%s): warning: interworking not enabled;"
9169 " first occurrence: %pB: %s call to %s"),
9170 sym_sec->owner, name, input_bfd, "Thumb", "ARM");
252b5132 9171
b34976b6 9172 return FALSE;
252b5132
RH		 9173 }
9174
9175 --my_offset;
9176 myh->root.u.def.value = my_offset;
9177
52ab56c2
PB		 9178 put_thumb_insn (globals, output_bfd, (bfd_vma) t2a1_bx_pc_insn,
9179 s->contents + my_offset);
252b5132 9180
52ab56c2
PB		 9181 put_thumb_insn (globals, output_bfd, (bfd_vma) t2a2_noop_insn,
9182 s->contents + my_offset + 2);
252b5132
RH		 9183
9184 ret_offset =
9b485d32
NC		 9185 /* Address of destination of the stub. */
9186 ((bfd_signed_vma) val)
252b5132 9187 - ((bfd_signed_vma)
57e8b36a
NC		 9188 /* Offset from the start of the current section
9189 to the start of the stubs. */
9b485d32
NC		 9190 (s->output_offset
9191 /* Offset of the start of this stub from the start of the stubs. */
9192 + my_offset
9193 /* Address of the start of the current section. */
9194 + s->output_section->vma)
9195 /* The branch instruction is 4 bytes into the stub. */
9196 + 4
9197 /* ARM branches work from the pc of the instruction + 8. */
9198 + 8);
252b5132 9199
52ab56c2
PB		 9200 put_arm_insn (globals, output_bfd,
9201 (bfd_vma) t2a3_b_insn | ((ret_offset >> 2) & 0x00FFFFFF),
9202 s->contents + my_offset + 4);
252b5132
RH		 9203 }
9204
9205 BFD_ASSERT (my_offset <= globals->thumb_glue_size);
9206
427bfd90
NC		 9207 /* Now go back and fix up the original BL insn to point to here. */
9208 ret_offset =
9209 /* Address of where the stub is located. */
9210 (s->output_section->vma + s->output_offset + my_offset)
9211 /* Address of where the BL is located. */
57e8b36a
NC		 9212 - (input_section->output_section->vma + input_section->output_offset
9213 + offset)
427bfd90
NC		 9214 /* Addend in the relocation. */
9215 - addend
9216 /* Biassing for PC-relative addressing. */
9217 - 8;
252b5132 9218
12a0a0fd 9219 insert_thumb_branch (input_bfd, ret_offset, hit_data - input_section->vma);
252b5132 9220
b34976b6 9221 return TRUE;
252b5132
RH		 9222}
9223
a4fd1a8e 9224/* Populate an Arm to Thumb stub. Returns the stub symbol. */
9b485d32 9225
a4fd1a8e
PB		 9226static struct elf_link_hash_entry *
9227elf32_arm_create_thumb_stub (struct bfd_link_info * info,
07d6d2b8
AM		 9228 const char * name,
9229 bfd * input_bfd,
9230 bfd * output_bfd,
9231 asection * sym_sec,
9232 bfd_vma val,
9233 asection * s,
9234 char ** error_message)
252b5132 9235{
dc810e39 9236 bfd_vma my_offset;
252b5132 9237 long int ret_offset;
bcbdc74c
NC		 9238 struct elf_link_hash_entry * myh;
9239 struct elf32_arm_link_hash_table * globals;
252b5132 9240
f2a9dd69 9241 myh = find_arm_glue (info, name, error_message);
252b5132 9242 if (myh == NULL)
a4fd1a8e 9243 return NULL;
252b5132
RH		 9244
9245 globals = elf32_arm_hash_table (info);
252b5132
RH		 9246 BFD_ASSERT (globals != NULL);
9247 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
9248
9249 my_offset = myh->root.u.def.value;
252b5132
RH		 9250
9251 if ((my_offset & 0x01) == 0x01)
9252 {
9253 if (sym_sec != NULL
9254 && sym_sec->owner != NULL
9255 && !INTERWORK_FLAG (sym_sec->owner))
9256 {
4eca0228 9257 _bfd_error_handler
90b6238f
AM		 9258 (_("%pB(%s): warning: interworking not enabled;"
9259 " first occurrence: %pB: %s call to %s"),
9260 sym_sec->owner, name, input_bfd, "ARM", "Thumb");
252b5132 9261 }
9b485d32 9262
252b5132
RH		 9263 --my_offset;
9264 myh->root.u.def.value = my_offset;
9265
0e1862bb
L		 9266 if (bfd_link_pic (info)
9267 || globals->root.is_relocatable_executable
27e55c4d 9268 || globals->pic_veneer)
8f6277f5
PB		 9269 {
9270 /* For relocatable objects we can't use absolute addresses,
9271 so construct the address from a relative offset. */
9272 /* TODO: If the offset is small it's probably worth
9273 constructing the address with adds. */
52ab56c2
PB		 9274 put_arm_insn (globals, output_bfd, (bfd_vma) a2t1p_ldr_insn,
9275 s->contents + my_offset);
9276 put_arm_insn (globals, output_bfd, (bfd_vma) a2t2p_add_pc_insn,
9277 s->contents + my_offset + 4);
9278 put_arm_insn (globals, output_bfd, (bfd_vma) a2t3p_bx_r12_insn,
9279 s->contents + my_offset + 8);
8f6277f5
PB		 9280 /* Adjust the offset by 4 for the position of the add,
9281 and 8 for the pipeline offset. */
9282 ret_offset = (val - (s->output_offset
9283 + s->output_section->vma
9284 + my_offset + 12))
9285 | 1;
9286 bfd_put_32 (output_bfd, ret_offset,
9287 s->contents + my_offset + 12);
9288 }
26079076
PB		 9289 else if (globals->use_blx)
9290 {
9291 put_arm_insn (globals, output_bfd, (bfd_vma) a2t1v5_ldr_insn,
9292 s->contents + my_offset);
9293
9294 /* It's a thumb address. Add the low order bit. */
9295 bfd_put_32 (output_bfd, val | a2t2v5_func_addr_insn,
9296 s->contents + my_offset + 4);
9297 }
8f6277f5
PB		 9298 else
9299 {
52ab56c2
PB		 9300 put_arm_insn (globals, output_bfd, (bfd_vma) a2t1_ldr_insn,
9301 s->contents + my_offset);
252b5132 9302
52ab56c2
PB		 9303 put_arm_insn (globals, output_bfd, (bfd_vma) a2t2_bx_r12_insn,
9304 s->contents + my_offset + 4);
252b5132 9305
8f6277f5
PB		 9306 /* It's a thumb address. Add the low order bit. */
9307 bfd_put_32 (output_bfd, val | a2t3_func_addr_insn,
9308 s->contents + my_offset + 8);
8029a119
NC		 9309
9310 my_offset += 12;
8f6277f5 9311 }
252b5132
RH		 9312 }
9313
9314 BFD_ASSERT (my_offset <= globals->arm_glue_size);
9315
a4fd1a8e
PB		 9316 return myh;
9317}
9318
9319/* Arm code calling a Thumb function. */
9320
9321static int
9322elf32_arm_to_thumb_stub (struct bfd_link_info * info,
07d6d2b8
AM		 9323 const char * name,
9324 bfd * input_bfd,
9325 bfd * output_bfd,
9326 asection * input_section,
9327 bfd_byte * hit_data,
9328 asection * sym_sec,
9329 bfd_vma offset,
9330 bfd_signed_vma addend,
9331 bfd_vma val,
f2a9dd69 9332 char **error_message)
a4fd1a8e
PB		 9333{
9334 unsigned long int tmp;
9335 bfd_vma my_offset;
9336 asection * s;
9337 long int ret_offset;
9338 struct elf_link_hash_entry * myh;
9339 struct elf32_arm_link_hash_table * globals;
9340
9341 globals = elf32_arm_hash_table (info);
a4fd1a8e
PB		 9342 BFD_ASSERT (globals != NULL);
9343 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
9344
3d4d4302
AM		 9345 s = bfd_get_linker_section (globals->bfd_of_glue_owner,
9346 ARM2THUMB_GLUE_SECTION_NAME);
a4fd1a8e
PB		 9347 BFD_ASSERT (s != NULL);
9348 BFD_ASSERT (s->contents != NULL);
9349 BFD_ASSERT (s->output_section != NULL);
9350
9351 myh = elf32_arm_create_thumb_stub (info, name, input_bfd, output_bfd,
f2a9dd69 9352 sym_sec, val, s, error_message);
a4fd1a8e
PB		 9353 if (!myh)
9354 return FALSE;
9355
9356 my_offset = myh->root.u.def.value;
252b5132
RH		 9357 tmp = bfd_get_32 (input_bfd, hit_data);
9358 tmp = tmp & 0xFF000000;
9359
9b485d32 9360 /* Somehow these are both 4 too far, so subtract 8. */
dc810e39
AM		 9361 ret_offset = (s->output_offset
9362 + my_offset
9363 + s->output_section->vma
9364 - (input_section->output_offset
9365 + input_section->output_section->vma
9366 + offset + addend)
9367 - 8);
9a5aca8c 9368
252b5132
RH		 9369 tmp = tmp | ((ret_offset >> 2) & 0x00FFFFFF);
9370
dc810e39 9371 bfd_put_32 (output_bfd, (bfd_vma) tmp, hit_data - input_section->vma);
252b5132 9372
b34976b6 9373 return TRUE;
252b5132
RH		 9374}
9375
a4fd1a8e
PB		 9376/* Populate Arm stub for an exported Thumb function. */
9377
9378static bfd_boolean
9379elf32_arm_to_thumb_export_stub (struct elf_link_hash_entry *h, void * inf)
9380{
9381 struct bfd_link_info * info = (struct bfd_link_info *) inf;
9382 asection * s;
9383 struct elf_link_hash_entry * myh;
9384 struct elf32_arm_link_hash_entry *eh;
9385 struct elf32_arm_link_hash_table * globals;
9386 asection *sec;
9387 bfd_vma val;
f2a9dd69 9388 char *error_message;
a4fd1a8e 9389
906e58ca 9390 eh = elf32_arm_hash_entry (h);
a4fd1a8e
PB		 9391 /* Allocate stubs for exported Thumb functions on v4t. */
9392 if (eh->export_glue == NULL)
9393 return TRUE;
9394
9395 globals = elf32_arm_hash_table (info);
a4fd1a8e
PB		 9396 BFD_ASSERT (globals != NULL);
9397 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
9398
3d4d4302
AM		 9399 s = bfd_get_linker_section (globals->bfd_of_glue_owner,
9400 ARM2THUMB_GLUE_SECTION_NAME);
a4fd1a8e
PB		 9401 BFD_ASSERT (s != NULL);
9402 BFD_ASSERT (s->contents != NULL);
9403 BFD_ASSERT (s->output_section != NULL);
9404
9405 sec = eh->export_glue->root.u.def.section;
0eaedd0e
PB		 9406
9407 BFD_ASSERT (sec->output_section != NULL);
9408
a4fd1a8e
PB		 9409 val = eh->export_glue->root.u.def.value + sec->output_offset
9410 + sec->output_section->vma;
8029a119 9411
a4fd1a8e
PB		 9412 myh = elf32_arm_create_thumb_stub (info, h->root.root.string,
9413 h->root.u.def.section->owner,
f2a9dd69
DJ		 9414 globals->obfd, sec, val, s,
9415 &error_message);
a4fd1a8e
PB		 9416 BFD_ASSERT (myh);
9417 return TRUE;
9418}
9419
845b51d6
PB		 9420/* Populate ARMv4 BX veneers. Returns the absolute adress of the veneer. */
9421
9422static bfd_vma
9423elf32_arm_bx_glue (struct bfd_link_info * info, int reg)
9424{
9425 bfd_byte *p;
9426 bfd_vma glue_addr;
9427 asection *s;
9428 struct elf32_arm_link_hash_table *globals;
9429
9430 globals = elf32_arm_hash_table (info);
845b51d6
PB		 9431 BFD_ASSERT (globals != NULL);
9432 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
9433
3d4d4302
AM		 9434 s = bfd_get_linker_section (globals->bfd_of_glue_owner,
9435 ARM_BX_GLUE_SECTION_NAME);
845b51d6
PB		 9436 BFD_ASSERT (s != NULL);
9437 BFD_ASSERT (s->contents != NULL);
9438 BFD_ASSERT (s->output_section != NULL);
9439
9440 BFD_ASSERT (globals->bx_glue_offset[reg] & 2);
9441
9442 glue_addr = globals->bx_glue_offset[reg] & ~(bfd_vma)3;
9443
9444 if ((globals->bx_glue_offset[reg] & 1) == 0)
9445 {
9446 p = s->contents + glue_addr;
9447 bfd_put_32 (globals->obfd, armbx1_tst_insn + (reg << 16), p);
9448 bfd_put_32 (globals->obfd, armbx2_moveq_insn + reg, p + 4);
9449 bfd_put_32 (globals->obfd, armbx3_bx_insn + reg, p + 8);
9450 globals->bx_glue_offset[reg] |= 1;
9451 }
9452
9453 return glue_addr + s->output_section->vma + s->output_offset;
9454}
9455
a4fd1a8e
PB		 9456/* Generate Arm stubs for exported Thumb symbols. */
9457static void
906e58ca 9458elf32_arm_begin_write_processing (bfd *abfd ATTRIBUTE_UNUSED,
a4fd1a8e
PB		 9459 struct bfd_link_info *link_info)
9460{
9461 struct elf32_arm_link_hash_table * globals;
9462
8029a119
NC		 9463 if (link_info == NULL)
9464 /* Ignore this if we are not called by the ELF backend linker. */
a4fd1a8e
PB		 9465 return;
9466
9467 globals = elf32_arm_hash_table (link_info);
4dfe6ac6
NC		 9468 if (globals == NULL)
9469 return;
9470
84c08195
PB		 9471 /* If blx is available then exported Thumb symbols are OK and there is
9472 nothing to do. */
a4fd1a8e
PB		 9473 if (globals->use_blx)
9474 return;
9475
9476 elf_link_hash_traverse (&globals->root, elf32_arm_to_thumb_export_stub,
9477 link_info);
9478}
9479
47beaa6a
RS		 9480/* Reserve space for COUNT dynamic relocations in relocation selection
9481 SRELOC. */
9482
9483static void
9484elf32_arm_allocate_dynrelocs (struct bfd_link_info *info, asection *sreloc,
9485 bfd_size_type count)
9486{
9487 struct elf32_arm_link_hash_table *htab;
9488
9489 htab = elf32_arm_hash_table (info);
9490 BFD_ASSERT (htab->root.dynamic_sections_created);
9491 if (sreloc == NULL)
9492 abort ();
9493 sreloc->size += RELOC_SIZE (htab) * count;
9494}
9495
34e77a92
RS		 9496/* Reserve space for COUNT R_ARM_IRELATIVE relocations. If the link is
9497 dynamic, the relocations should go in SRELOC, otherwise they should
9498 go in the special .rel.iplt section. */
9499
9500static void
9501elf32_arm_allocate_irelocs (struct bfd_link_info *info, asection *sreloc,
9502 bfd_size_type count)
9503{
9504 struct elf32_arm_link_hash_table *htab;
9505
9506 htab = elf32_arm_hash_table (info);
9507 if (!htab->root.dynamic_sections_created)
9508 htab->root.irelplt->size += RELOC_SIZE (htab) * count;
9509 else
9510 {
9511 BFD_ASSERT (sreloc != NULL);
9512 sreloc->size += RELOC_SIZE (htab) * count;
9513 }
9514}
9515
47beaa6a
RS		 9516/* Add relocation REL to the end of relocation section SRELOC. */
9517
9518static void
9519elf32_arm_add_dynreloc (bfd *output_bfd, struct bfd_link_info *info,
9520 asection *sreloc, Elf_Internal_Rela *rel)
9521{
9522 bfd_byte *loc;
9523 struct elf32_arm_link_hash_table *htab;
9524
9525 htab = elf32_arm_hash_table (info);
34e77a92
RS		 9526 if (!htab->root.dynamic_sections_created
9527 && ELF32_R_TYPE (rel->r_info) == R_ARM_IRELATIVE)
9528 sreloc = htab->root.irelplt;
47beaa6a
RS		 9529 if (sreloc == NULL)
9530 abort ();
9531 loc = sreloc->contents;
9532 loc += sreloc->reloc_count++ * RELOC_SIZE (htab);
9533 if (sreloc->reloc_count * RELOC_SIZE (htab) > sreloc->size)
9534 abort ();
9535 SWAP_RELOC_OUT (htab) (output_bfd, rel, loc);
9536}
9537
34e77a92
RS		 9538/* Allocate room for a PLT entry described by ROOT_PLT and ARM_PLT.
9539 IS_IPLT_ENTRY says whether the entry belongs to .iplt rather than
9540 to .plt. */
9541
9542static void
9543elf32_arm_allocate_plt_entry (struct bfd_link_info *info,
9544 bfd_boolean is_iplt_entry,
9545 union gotplt_union *root_plt,
9546 struct arm_plt_info *arm_plt)
9547{
9548 struct elf32_arm_link_hash_table *htab;
9549 asection *splt;
9550 asection *sgotplt;
9551
9552 htab = elf32_arm_hash_table (info);
9553
9554 if (is_iplt_entry)
9555 {
9556 splt = htab->root.iplt;
9557 sgotplt = htab->root.igotplt;
9558
99059e56
RM		 9559 /* NaCl uses a special first entry in .iplt too. */
9560 if (htab->nacl_p && splt->size == 0)
9561 splt->size += htab->plt_header_size;
9562
34e77a92
RS		 9563 /* Allocate room for an R_ARM_IRELATIVE relocation in .rel.iplt. */
9564 elf32_arm_allocate_irelocs (info, htab->root.irelplt, 1);
9565 }
9566 else
9567 {
9568 splt = htab->root.splt;
9569 sgotplt = htab->root.sgotplt;
9570
7801f98f
CL		 9571 if (htab->fdpic_p)
9572 {
9573 /* Allocate room for R_ARM_FUNCDESC_VALUE. */
9574 /* For lazy binding, relocations will be put into .rel.plt, in
9575 .rel.got otherwise. */
9576 /* FIXME: today we don't support lazy binding so put it in .rel.got */
9577 if (info->flags & DF_BIND_NOW)
9578 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
9579 else
9580 elf32_arm_allocate_dynrelocs (info, htab->root.srelplt, 1);
9581 }
9582 else
9583 {
9584 /* Allocate room for an R_JUMP_SLOT relocation in .rel.plt. */
9585 elf32_arm_allocate_dynrelocs (info, htab->root.srelplt, 1);
9586 }
34e77a92
RS		 9587
9588 /* If this is the first .plt entry, make room for the special
9589 first entry. */
9590 if (splt->size == 0)
9591 splt->size += htab->plt_header_size;
9f19ab6d
WN		 9592
9593 htab->next_tls_desc_index++;
34e77a92
RS		 9594 }
9595
9596 /* Allocate the PLT entry itself, including any leading Thumb stub. */
9597 if (elf32_arm_plt_needs_thumb_stub_p (info, arm_plt))
9598 splt->size += PLT_THUMB_STUB_SIZE;
9599 root_plt->offset = splt->size;
9600 splt->size += htab->plt_entry_size;
9601
9602 if (!htab->symbian_p)
9603 {
9604 /* We also need to make an entry in the .got.plt section, which
9605 will be placed in the .got section by the linker script. */
9f19ab6d
WN		 9606 if (is_iplt_entry)
9607 arm_plt->got_offset = sgotplt->size;
9608 else
9609 arm_plt->got_offset = sgotplt->size - 8 * htab->num_tls_desc;
7801f98f
CL		 9610 if (htab->fdpic_p)
9611 /* Function descriptor takes 64 bits in GOT. */
4b24dd1a 9612 sgotplt->size += 8;
7801f98f
CL		 9613 else
9614 sgotplt->size += 4;
34e77a92
RS		 9615 }
9616}
9617
b38cadfb
NC		 9618static bfd_vma
9619arm_movw_immediate (bfd_vma value)
9620{
9621 return (value & 0x00000fff) | ((value & 0x0000f000) << 4);
9622}
9623
9624static bfd_vma
9625arm_movt_immediate (bfd_vma value)
9626{
9627 return ((value & 0x0fff0000) >> 16) | ((value & 0xf0000000) >> 12);
9628}
9629
34e77a92
RS		 9630/* Fill in a PLT entry and its associated GOT slot. If DYNINDX == -1,
9631 the entry lives in .iplt and resolves to (*SYM_VALUE)().
9632 Otherwise, DYNINDX is the index of the symbol in the dynamic
9633 symbol table and SYM_VALUE is undefined.
9634
9635 ROOT_PLT points to the offset of the PLT entry from the start of its
9636 section (.iplt or .plt). ARM_PLT points to the symbol's ARM-specific
57460bcf 9637 bookkeeping information.
34e77a92 9638
57460bcf
NC		 9639 Returns FALSE if there was a problem. */
9640
9641static bfd_boolean
34e77a92
RS		 9642elf32_arm_populate_plt_entry (bfd *output_bfd, struct bfd_link_info *info,
9643 union gotplt_union *root_plt,
9644 struct arm_plt_info *arm_plt,
9645 int dynindx, bfd_vma sym_value)
9646{
9647 struct elf32_arm_link_hash_table *htab;
9648 asection *sgot;
9649 asection *splt;
9650 asection *srel;
9651 bfd_byte *loc;
9652 bfd_vma plt_index;
9653 Elf_Internal_Rela rel;
9654 bfd_vma plt_header_size;
9655 bfd_vma got_header_size;
9656
9657 htab = elf32_arm_hash_table (info);
9658
9659 /* Pick the appropriate sections and sizes. */
9660 if (dynindx == -1)
9661 {
9662 splt = htab->root.iplt;
9663 sgot = htab->root.igotplt;
9664 srel = htab->root.irelplt;
9665
9666 /* There are no reserved entries in .igot.plt, and no special
9667 first entry in .iplt. */
9668 got_header_size = 0;
9669 plt_header_size = 0;
9670 }
9671 else
9672 {
9673 splt = htab->root.splt;
9674 sgot = htab->root.sgotplt;
9675 srel = htab->root.srelplt;
9676
9677 got_header_size = get_elf_backend_data (output_bfd)->got_header_size;
9678 plt_header_size = htab->plt_header_size;
9679 }
9680 BFD_ASSERT (splt != NULL && srel != NULL);
9681
9682 /* Fill in the entry in the procedure linkage table. */
9683 if (htab->symbian_p)
9684 {
9685 BFD_ASSERT (dynindx >= 0);
9686 put_arm_insn (htab, output_bfd,
9687 elf32_arm_symbian_plt_entry[0],
9688 splt->contents + root_plt->offset);
9689 bfd_put_32 (output_bfd,
9690 elf32_arm_symbian_plt_entry[1],
9691 splt->contents + root_plt->offset + 4);
9692
9693 /* Fill in the entry in the .rel.plt section. */
9694 rel.r_offset = (splt->output_section->vma
9695 + splt->output_offset
9696 + root_plt->offset + 4);
9697 rel.r_info = ELF32_R_INFO (dynindx, R_ARM_GLOB_DAT);
9698
9699 /* Get the index in the procedure linkage table which
9700 corresponds to this symbol. This is the index of this symbol
9701 in all the symbols for which we are making plt entries. The
9702 first entry in the procedure linkage table is reserved. */
9703 plt_index = ((root_plt->offset - plt_header_size)
9704 / htab->plt_entry_size);
9705 }
9706 else
9707 {
9708 bfd_vma got_offset, got_address, plt_address;
9709 bfd_vma got_displacement, initial_got_entry;
9710 bfd_byte * ptr;
9711
9712 BFD_ASSERT (sgot != NULL);
9713
9714 /* Get the offset into the .(i)got.plt table of the entry that
9715 corresponds to this function. */
9716 got_offset = (arm_plt->got_offset & -2);
9717
9718 /* Get the index in the procedure linkage table which
9719 corresponds to this symbol. This is the index of this symbol
9720 in all the symbols for which we are making plt entries.
9721 After the reserved .got.plt entries, all symbols appear in
9722 the same order as in .plt. */
7801f98f 9723 if (htab->fdpic_p)
4b24dd1a
AM		 9724 /* Function descriptor takes 8 bytes. */
9725 plt_index = (got_offset - got_header_size) / 8;
7801f98f 9726 else
4b24dd1a 9727 plt_index = (got_offset - got_header_size) / 4;
34e77a92
RS		 9728
9729 /* Calculate the address of the GOT entry. */
9730 got_address = (sgot->output_section->vma
9731 + sgot->output_offset
9732 + got_offset);
9733
9734 /* ...and the address of the PLT entry. */
9735 plt_address = (splt->output_section->vma
9736 + splt->output_offset
9737 + root_plt->offset);
9738
9739 ptr = splt->contents + root_plt->offset;
0e1862bb 9740 if (htab->vxworks_p && bfd_link_pic (info))
34e77a92
RS		 9741 {
9742 unsigned int i;
9743 bfd_vma val;
9744
9745 for (i = 0; i != htab->plt_entry_size / 4; i++, ptr += 4)
9746 {
9747 val = elf32_arm_vxworks_shared_plt_entry[i];
9748 if (i == 2)
9749 val |= got_address - sgot->output_section->vma;
9750 if (i == 5)
9751 val |= plt_index * RELOC_SIZE (htab);
9752 if (i == 2 || i == 5)
9753 bfd_put_32 (output_bfd, val, ptr);
9754 else
9755 put_arm_insn (htab, output_bfd, val, ptr);
9756 }
9757 }
9758 else if (htab->vxworks_p)
9759 {
9760 unsigned int i;
9761 bfd_vma val;
9762
9763 for (i = 0; i != htab->plt_entry_size / 4; i++, ptr += 4)
9764 {
9765 val = elf32_arm_vxworks_exec_plt_entry[i];
9766 if (i == 2)
9767 val |= got_address;
9768 if (i == 4)
9769 val |= 0xffffff & -((root_plt->offset + i * 4 + 8) >> 2);
9770 if (i == 5)
9771 val |= plt_index * RELOC_SIZE (htab);
9772 if (i == 2 || i == 5)
9773 bfd_put_32 (output_bfd, val, ptr);
9774 else
9775 put_arm_insn (htab, output_bfd, val, ptr);
9776 }
9777
9778 loc = (htab->srelplt2->contents
9779 + (plt_index * 2 + 1) * RELOC_SIZE (htab));
9780
9781 /* Create the .rela.plt.unloaded R_ARM_ABS32 relocation
9782 referencing the GOT for this PLT entry. */
9783 rel.r_offset = plt_address + 8;
9784 rel.r_info = ELF32_R_INFO (htab->root.hgot->indx, R_ARM_ABS32);
9785 rel.r_addend = got_offset;
9786 SWAP_RELOC_OUT (htab) (output_bfd, &rel, loc);
9787 loc += RELOC_SIZE (htab);
9788
9789 /* Create the R_ARM_ABS32 relocation referencing the
9790 beginning of the PLT for this GOT entry. */
9791 rel.r_offset = got_address;
9792 rel.r_info = ELF32_R_INFO (htab->root.hplt->indx, R_ARM_ABS32);
9793 rel.r_addend = 0;
9794 SWAP_RELOC_OUT (htab) (output_bfd, &rel, loc);
9795 }
b38cadfb
NC		 9796 else if (htab->nacl_p)
9797 {
9798 /* Calculate the displacement between the PLT slot and the
9799 common tail that's part of the special initial PLT slot. */
6034aab8 9800 int32_t tail_displacement
b38cadfb
NC		 9801 = ((splt->output_section->vma + splt->output_offset
9802 + ARM_NACL_PLT_TAIL_OFFSET)
9803 - (plt_address + htab->plt_entry_size + 4));
9804 BFD_ASSERT ((tail_displacement & 3) == 0);
9805 tail_displacement >>= 2;
9806
9807 BFD_ASSERT ((tail_displacement & 0xff000000) == 0
9808 || (-tail_displacement & 0xff000000) == 0);
9809
9810 /* Calculate the displacement between the PLT slot and the entry
9811 in the GOT. The offset accounts for the value produced by
9812 adding to pc in the penultimate instruction of the PLT stub. */
6034aab8 9813 got_displacement = (got_address
99059e56 9814 - (plt_address + htab->plt_entry_size));
b38cadfb
NC		 9815
9816 /* NaCl does not support interworking at all. */
9817 BFD_ASSERT (!elf32_arm_plt_needs_thumb_stub_p (info, arm_plt));
9818
9819 put_arm_insn (htab, output_bfd,
9820 elf32_arm_nacl_plt_entry[0]
9821 | arm_movw_immediate (got_displacement),
9822 ptr + 0);
9823 put_arm_insn (htab, output_bfd,
9824 elf32_arm_nacl_plt_entry[1]
9825 | arm_movt_immediate (got_displacement),
9826 ptr + 4);
9827 put_arm_insn (htab, output_bfd,
9828 elf32_arm_nacl_plt_entry[2],
9829 ptr + 8);
9830 put_arm_insn (htab, output_bfd,
9831 elf32_arm_nacl_plt_entry[3]
9832 | (tail_displacement & 0x00ffffff),
9833 ptr + 12);
9834 }
7801f98f
CL		 9835 else if (htab->fdpic_p)
9836 {
59029f57
CL		 9837 const bfd_vma *plt_entry = using_thumb_only(htab)
9838 ? elf32_arm_fdpic_thumb_plt_entry
9839 : elf32_arm_fdpic_plt_entry;
9840
7801f98f
CL		 9841 /* Fill-up Thumb stub if needed. */
9842 if (elf32_arm_plt_needs_thumb_stub_p (info, arm_plt))
9843 {
9844 put_thumb_insn (htab, output_bfd,
9845 elf32_arm_plt_thumb_stub[0], ptr - 4);
9846 put_thumb_insn (htab, output_bfd,
9847 elf32_arm_plt_thumb_stub[1], ptr - 2);
9848 }
59029f57
CL		 9849 /* As we are using 32 bit instructions even for the Thumb
9850 version, we have to use 'put_arm_insn' instead of
9851 'put_thumb_insn'. */
9852 put_arm_insn(htab, output_bfd, plt_entry[0], ptr + 0);
9853 put_arm_insn(htab, output_bfd, plt_entry[1], ptr + 4);
9854 put_arm_insn(htab, output_bfd, plt_entry[2], ptr + 8);
9855 put_arm_insn(htab, output_bfd, plt_entry[3], ptr + 12);
7801f98f
CL		 9856 bfd_put_32 (output_bfd, got_offset, ptr + 16);
9857
9858 if (!(info->flags & DF_BIND_NOW))
9859 {
9860 /* funcdesc_value_reloc_offset. */
9861 bfd_put_32 (output_bfd,
9862 htab->root.srelplt->reloc_count * RELOC_SIZE (htab),
9863 ptr + 20);
59029f57
CL		 9864 put_arm_insn(htab, output_bfd, plt_entry[6], ptr + 24);
9865 put_arm_insn(htab, output_bfd, plt_entry[7], ptr + 28);
9866 put_arm_insn(htab, output_bfd, plt_entry[8], ptr + 32);
9867 put_arm_insn(htab, output_bfd, plt_entry[9], ptr + 36);
7801f98f
CL		 9868 }
9869 }
57460bcf
NC		 9870 else if (using_thumb_only (htab))
9871 {
eed94f8f 9872 /* PR ld/16017: Generate thumb only PLT entries. */
469a3493 9873 if (!using_thumb2 (htab))
eed94f8f
NC		 9874 {
9875 /* FIXME: We ought to be able to generate thumb-1 PLT
9876 instructions... */
90b6238f 9877 _bfd_error_handler (_("%pB: warning: thumb-1 mode PLT generation not currently supported"),
eed94f8f
NC		 9878 output_bfd);
9879 return FALSE;
9880 }
57460bcf 9881
eed94f8f
NC		 9882 /* Calculate the displacement between the PLT slot and the entry in
9883 the GOT. The 12-byte offset accounts for the value produced by
9884 adding to pc in the 3rd instruction of the PLT stub. */
9885 got_displacement = got_address - (plt_address + 12);
9886
9887 /* As we are using 32 bit instructions we have to use 'put_arm_insn'
9888 instead of 'put_thumb_insn'. */
9889 put_arm_insn (htab, output_bfd,
9890 elf32_thumb2_plt_entry[0]
9891 | ((got_displacement & 0x000000ff) << 16)
9892 | ((got_displacement & 0x00000700) << 20)
9893 | ((got_displacement & 0x00000800) >> 1)
9894 | ((got_displacement & 0x0000f000) >> 12),
9895 ptr + 0);
9896 put_arm_insn (htab, output_bfd,
9897 elf32_thumb2_plt_entry[1]
9898 | ((got_displacement & 0x00ff0000) )
9899 | ((got_displacement & 0x07000000) << 4)
9900 | ((got_displacement & 0x08000000) >> 17)
9901 | ((got_displacement & 0xf0000000) >> 28),
9902 ptr + 4);
9903 put_arm_insn (htab, output_bfd,
9904 elf32_thumb2_plt_entry[2],
9905 ptr + 8);
9906 put_arm_insn (htab, output_bfd,
9907 elf32_thumb2_plt_entry[3],
9908 ptr + 12);
57460bcf 9909 }
34e77a92
RS		 9910 else
9911 {
9912 /* Calculate the displacement between the PLT slot and the
9913 entry in the GOT. The eight-byte offset accounts for the
9914 value produced by adding to pc in the first instruction
9915 of the PLT stub. */
9916 got_displacement = got_address - (plt_address + 8);
9917
34e77a92
RS		 9918 if (elf32_arm_plt_needs_thumb_stub_p (info, arm_plt))
9919 {
9920 put_thumb_insn (htab, output_bfd,
9921 elf32_arm_plt_thumb_stub[0], ptr - 4);
9922 put_thumb_insn (htab, output_bfd,
9923 elf32_arm_plt_thumb_stub[1], ptr - 2);
9924 }
9925
1db37fe6
YG		 9926 if (!elf32_arm_use_long_plt_entry)
9927 {
9928 BFD_ASSERT ((got_displacement & 0xf0000000) == 0);
9929
9930 put_arm_insn (htab, output_bfd,
9931 elf32_arm_plt_entry_short[0]
9932 | ((got_displacement & 0x0ff00000) >> 20),
9933 ptr + 0);
9934 put_arm_insn (htab, output_bfd,
9935 elf32_arm_plt_entry_short[1]
9936 | ((got_displacement & 0x000ff000) >> 12),
9937 ptr+ 4);
9938 put_arm_insn (htab, output_bfd,
9939 elf32_arm_plt_entry_short[2]
9940 | (got_displacement & 0x00000fff),
9941 ptr + 8);
34e77a92 9942#ifdef FOUR_WORD_PLT
1db37fe6 9943 bfd_put_32 (output_bfd, elf32_arm_plt_entry_short[3], ptr + 12);
34e77a92 9944#endif
1db37fe6
YG		 9945 }
9946 else
9947 {
9948 put_arm_insn (htab, output_bfd,
9949 elf32_arm_plt_entry_long[0]
9950 | ((got_displacement & 0xf0000000) >> 28),
9951 ptr + 0);
9952 put_arm_insn (htab, output_bfd,
9953 elf32_arm_plt_entry_long[1]
9954 | ((got_displacement & 0x0ff00000) >> 20),
9955 ptr + 4);
9956 put_arm_insn (htab, output_bfd,
9957 elf32_arm_plt_entry_long[2]
9958 | ((got_displacement & 0x000ff000) >> 12),
9959 ptr+ 8);
9960 put_arm_insn (htab, output_bfd,
9961 elf32_arm_plt_entry_long[3]
9962 | (got_displacement & 0x00000fff),
9963 ptr + 12);
9964 }
34e77a92
RS		 9965 }
9966
9967 /* Fill in the entry in the .rel(a).(i)plt section. */
9968 rel.r_offset = got_address;
9969 rel.r_addend = 0;
9970 if (dynindx == -1)
9971 {
9972 /* .igot.plt entries use IRELATIVE relocations against SYM_VALUE.
9973 The dynamic linker or static executable then calls SYM_VALUE
9974 to determine the correct run-time value of the .igot.plt entry. */
9975 rel.r_info = ELF32_R_INFO (0, R_ARM_IRELATIVE);
9976 initial_got_entry = sym_value;
9977 }
9978 else
9979 {
7801f98f
CL		 9980 /* For FDPIC we will have to resolve a R_ARM_FUNCDESC_VALUE
9981 used by PLT entry. */
9982 if (htab->fdpic_p)
9983 {
9984 rel.r_info = ELF32_R_INFO (dynindx, R_ARM_FUNCDESC_VALUE);
9985 initial_got_entry = 0;
9986 }
9987 else
9988 {
9989 rel.r_info = ELF32_R_INFO (dynindx, R_ARM_JUMP_SLOT);
9990 initial_got_entry = (splt->output_section->vma
9991 + splt->output_offset);
9992 }
34e77a92
RS		 9993 }
9994
9995 /* Fill in the entry in the global offset table. */
9996 bfd_put_32 (output_bfd, initial_got_entry,
9997 sgot->contents + got_offset);
7801f98f
CL		 9998
9999 if (htab->fdpic_p && !(info->flags & DF_BIND_NOW))
10000 {
10001 /* Setup initial funcdesc value. */
10002 /* FIXME: we don't support lazy binding because there is a
10003 race condition between both words getting written and
10004 some other thread attempting to read them. The ARM
10005 architecture does not have an atomic 64 bit load/store
10006 instruction that could be used to prevent it; it is
10007 recommended that threaded FDPIC applications run with the
10008 LD_BIND_NOW environment variable set. */
10009 bfd_put_32(output_bfd, plt_address + 0x18,
10010 sgot->contents + got_offset);
10011 bfd_put_32(output_bfd, -1 /*TODO*/,
10012 sgot->contents + got_offset + 4);
10013 }
34e77a92
RS		 10014 }
10015
aba8c3de
WN		 10016 if (dynindx == -1)
10017 elf32_arm_add_dynreloc (output_bfd, info, srel, &rel);
10018 else
10019 {
7801f98f
CL		 10020 if (htab->fdpic_p)
10021 {
10022 /* For FDPIC we put PLT relocationss into .rel.got when not
10023 lazy binding otherwise we put them in .rel.plt. For now,
10024 we don't support lazy binding so put it in .rel.got. */
10025 if (info->flags & DF_BIND_NOW)
10026 elf32_arm_add_dynreloc(output_bfd, info, htab->root.srelgot, &rel);
10027 else
10028 elf32_arm_add_dynreloc(output_bfd, info, htab->root.srelplt, &rel);
10029 }
10030 else
10031 {
10032 loc = srel->contents + plt_index * RELOC_SIZE (htab);
10033 SWAP_RELOC_OUT (htab) (output_bfd, &rel, loc);
10034 }
aba8c3de 10035 }
57460bcf
NC		 10036
10037 return TRUE;
34e77a92
RS		 10038}
10039
eb043451
PB		 10040/* Some relocations map to different relocations depending on the
10041 target. Return the real relocation. */
8029a119 10042
eb043451
PB		 10043static int
10044arm_real_reloc_type (struct elf32_arm_link_hash_table * globals,
10045 int r_type)
10046{
10047 switch (r_type)
10048 {
10049 case R_ARM_TARGET1:
10050 if (globals->target1_is_rel)
10051 return R_ARM_REL32;
10052 else
10053 return R_ARM_ABS32;
10054
10055 case R_ARM_TARGET2:
10056 return globals->target2_reloc;
10057
10058 default:
10059 return r_type;
10060 }
10061}
eb043451 10062
ba93b8ac
DJ		 10063/* Return the base VMA address which should be subtracted from real addresses
10064 when resolving @dtpoff relocation.
10065 This is PT_TLS segment p_vaddr. */
10066
10067static bfd_vma
10068dtpoff_base (struct bfd_link_info *info)
10069{
10070 /* If tls_sec is NULL, we should have signalled an error already. */
10071 if (elf_hash_table (info)->tls_sec == NULL)
10072 return 0;
10073 return elf_hash_table (info)->tls_sec->vma;
10074}
10075
10076/* Return the relocation value for @tpoff relocation
10077 if STT_TLS virtual address is ADDRESS. */
10078
10079static bfd_vma
10080tpoff (struct bfd_link_info *info, bfd_vma address)
10081{
10082 struct elf_link_hash_table *htab = elf_hash_table (info);
10083 bfd_vma base;
10084
10085 /* If tls_sec is NULL, we should have signalled an error already. */
10086 if (htab->tls_sec == NULL)
10087 return 0;
10088 base = align_power ((bfd_vma) TCB_SIZE, htab->tls_sec->alignment_power);
10089 return address - htab->tls_sec->vma + base;
10090}
10091
00a97672
RS		 10092/* Perform an R_ARM_ABS12 relocation on the field pointed to by DATA.
10093 VALUE is the relocation value. */
10094
10095static bfd_reloc_status_type
10096elf32_arm_abs12_reloc (bfd *abfd, void *data, bfd_vma value)
10097{
10098 if (value > 0xfff)
10099 return bfd_reloc_overflow;
10100
10101 value |= bfd_get_32 (abfd, data) & 0xfffff000;
10102 bfd_put_32 (abfd, value, data);
10103 return bfd_reloc_ok;
10104}
10105
0855e32b
NS		 10106/* Handle TLS relaxations. Relaxing is possible for symbols that use
10107 R_ARM_GOTDESC, R_ARM_{,THM_}TLS_CALL or
10108 R_ARM_{,THM_}TLS_DESCSEQ relocations, during a static link.
10109
10110 Return bfd_reloc_ok if we're done, bfd_reloc_continue if the caller
10111 is to then call final_link_relocate. Return other values in the
62672b10
NS		 10112 case of error.
10113
10114 FIXME:When --emit-relocs is in effect, we'll emit relocs describing
10115 the pre-relaxed code. It would be nice if the relocs were updated
10116 to match the optimization. */
0855e32b 10117
b38cadfb 10118static bfd_reloc_status_type
0855e32b 10119elf32_arm_tls_relax (struct elf32_arm_link_hash_table *globals,
b38cadfb 10120 bfd *input_bfd, asection *input_sec, bfd_byte *contents,
0855e32b
NS		 10121 Elf_Internal_Rela *rel, unsigned long is_local)
10122{
10123 unsigned long insn;
b38cadfb 10124
0855e32b
NS		 10125 switch (ELF32_R_TYPE (rel->r_info))
10126 {
10127 default:
10128 return bfd_reloc_notsupported;
b38cadfb 10129
0855e32b
NS		 10130 case R_ARM_TLS_GOTDESC:
10131 if (is_local)
10132 insn = 0;
10133 else
10134 {
10135 insn = bfd_get_32 (input_bfd, contents + rel->r_offset);
10136 if (insn & 1)
10137 insn -= 5; /* THUMB */
10138 else
10139 insn -= 8; /* ARM */
10140 }
10141 bfd_put_32 (input_bfd, insn, contents + rel->r_offset);
10142 return bfd_reloc_continue;
10143
10144 case R_ARM_THM_TLS_DESCSEQ:
10145 /* Thumb insn. */
10146 insn = bfd_get_16 (input_bfd, contents + rel->r_offset);
10147 if ((insn & 0xff78) == 0x4478) /* add rx, pc */
10148 {
10149 if (is_local)
10150 /* nop */
10151 bfd_put_16 (input_bfd, 0x46c0, contents + rel->r_offset);
10152 }
10153 else if ((insn & 0xffc0) == 0x6840) /* ldr rx,[ry,#4] */
10154 {
10155 if (is_local)
10156 /* nop */
10157 bfd_put_16 (input_bfd, 0x46c0, contents + rel->r_offset);
10158 else
10159 /* ldr rx,[ry] */
10160 bfd_put_16 (input_bfd, insn & 0xf83f, contents + rel->r_offset);
10161 }
10162 else if ((insn & 0xff87) == 0x4780) /* blx rx */
10163 {
10164 if (is_local)
10165 /* nop */
10166 bfd_put_16 (input_bfd, 0x46c0, contents + rel->r_offset);
10167 else
10168 /* mov r0, rx */
10169 bfd_put_16 (input_bfd, 0x4600 | (insn & 0x78),
10170 contents + rel->r_offset);
10171 }
10172 else
10173 {
10174 if ((insn & 0xf000) == 0xf000 || (insn & 0xf800) == 0xe800)
10175 /* It's a 32 bit instruction, fetch the rest of it for
10176 error generation. */
10177 insn = (insn << 16)
10178 | bfd_get_16 (input_bfd, contents + rel->r_offset + 2);
4eca0228 10179 _bfd_error_handler
695344c0 10180 /* xgettext:c-format */
2dcf00ce 10181 (_("%pB(%pA+%#" PRIx64 "): "
90b6238f
AM		 10182 "unexpected %s instruction '%#lx' in TLS trampoline"),
10183 input_bfd, input_sec, (uint64_t) rel->r_offset,
10184 "Thumb", insn);
0855e32b
NS		 10185 return bfd_reloc_notsupported;
10186 }
10187 break;
b38cadfb 10188
0855e32b
NS		 10189 case R_ARM_TLS_DESCSEQ:
10190 /* arm insn. */
10191 insn = bfd_get_32 (input_bfd, contents + rel->r_offset);
10192 if ((insn & 0xffff0ff0) == 0xe08f0000) /* add rx,pc,ry */
10193 {
10194 if (is_local)
10195 /* mov rx, ry */
10196 bfd_put_32 (input_bfd, 0xe1a00000 | (insn & 0xffff),
10197 contents + rel->r_offset);
10198 }
10199 else if ((insn & 0xfff00fff) == 0xe5900004) /* ldr rx,[ry,#4]*/
10200 {
10201 if (is_local)
10202 /* nop */
10203 bfd_put_32 (input_bfd, 0xe1a00000, contents + rel->r_offset);
10204 else
10205 /* ldr rx,[ry] */
10206 bfd_put_32 (input_bfd, insn & 0xfffff000,
10207 contents + rel->r_offset);
10208 }
10209 else if ((insn & 0xfffffff0) == 0xe12fff30) /* blx rx */
10210 {
10211 if (is_local)
10212 /* nop */
10213 bfd_put_32 (input_bfd, 0xe1a00000, contents + rel->r_offset);
10214 else
10215 /* mov r0, rx */
10216 bfd_put_32 (input_bfd, 0xe1a00000 | (insn & 0xf),
10217 contents + rel->r_offset);
10218 }
10219 else
10220 {
4eca0228 10221 _bfd_error_handler
695344c0 10222 /* xgettext:c-format */
2dcf00ce 10223 (_("%pB(%pA+%#" PRIx64 "): "
90b6238f
AM		 10224 "unexpected %s instruction '%#lx' in TLS trampoline"),
10225 input_bfd, input_sec, (uint64_t) rel->r_offset,
10226 "ARM", insn);
0855e32b
NS		 10227 return bfd_reloc_notsupported;
10228 }
10229 break;
10230
10231 case R_ARM_TLS_CALL:
10232 /* GD->IE relaxation, turn the instruction into 'nop' or
10233 'ldr r0, [pc,r0]' */
10234 insn = is_local ? 0xe1a00000 : 0xe79f0000;
10235 bfd_put_32 (input_bfd, insn, contents + rel->r_offset);
10236 break;
b38cadfb 10237
0855e32b 10238 case R_ARM_THM_TLS_CALL:
6a631e86 10239 /* GD->IE relaxation. */
0855e32b
NS		 10240 if (!is_local)
10241 /* add r0,pc; ldr r0, [r0] */
10242 insn = 0x44786800;
60a019a0 10243 else if (using_thumb2 (globals))
0855e32b
NS		 10244 /* nop.w */
10245 insn = 0xf3af8000;
10246 else
10247 /* nop; nop */
10248 insn = 0xbf00bf00;
b38cadfb 10249
0855e32b
NS		 10250 bfd_put_16 (input_bfd, insn >> 16, contents + rel->r_offset);
10251 bfd_put_16 (input_bfd, insn & 0xffff, contents + rel->r_offset + 2);
10252 break;
10253 }
10254 return bfd_reloc_ok;
10255}
10256
4962c51a
MS		 10257/* For a given value of n, calculate the value of G_n as required to
10258 deal with group relocations. We return it in the form of an
10259 encoded constant-and-rotation, together with the final residual. If n is
10260 specified as less than zero, then final_residual is filled with the
10261 input value and no further action is performed. */
10262
10263static bfd_vma
10264calculate_group_reloc_mask (bfd_vma value, int n, bfd_vma *final_residual)
10265{
10266 int current_n;
10267 bfd_vma g_n;
10268 bfd_vma encoded_g_n = 0;
10269 bfd_vma residual = value; /* Also known as Y_n. */
10270
10271 for (current_n = 0; current_n <= n; current_n++)
10272 {
10273 int shift;
10274
10275 /* Calculate which part of the value to mask. */
10276 if (residual == 0)
99059e56 10277 shift = 0;
4962c51a 10278 else
99059e56
RM		 10279 {
10280 int msb;
10281
10282 /* Determine the most significant bit in the residual and
10283 align the resulting value to a 2-bit boundary. */
10284 for (msb = 30; msb >= 0; msb -= 2)
10285 if (residual & (3 << msb))
10286 break;
10287
10288 /* The desired shift is now (msb - 6), or zero, whichever
10289 is the greater. */
10290 shift = msb - 6;
10291 if (shift < 0)
10292 shift = 0;
10293 }
4962c51a
MS		 10294
10295 /* Calculate g_n in 32-bit as well as encoded constant+rotation form. */
10296 g_n = residual & (0xff << shift);
10297 encoded_g_n = (g_n >> shift)
99059e56 10298 | ((g_n <= 0xff ? 0 : (32 - shift) / 2) << 8);
4962c51a
MS		 10299
10300 /* Calculate the residual for the next time around. */
10301 residual &= ~g_n;
10302 }
10303
10304 *final_residual = residual;
10305
10306 return encoded_g_n;
10307}
10308
10309/* Given an ARM instruction, determine whether it is an ADD or a SUB.
10310 Returns 1 if it is an ADD, -1 if it is a SUB, and 0 otherwise. */
906e58ca 10311
4962c51a 10312static int
906e58ca 10313identify_add_or_sub (bfd_vma insn)
4962c51a
MS		 10314{
10315 int opcode = insn & 0x1e00000;
10316
10317 if (opcode == 1 << 23) /* ADD */
10318 return 1;
10319
10320 if (opcode == 1 << 22) /* SUB */
10321 return -1;
10322
10323 return 0;
10324}
10325
252b5132 10326/* Perform a relocation as part of a final link. */
9b485d32 10327
252b5132 10328static bfd_reloc_status_type
07d6d2b8
AM		 10329elf32_arm_final_link_relocate (reloc_howto_type * howto,
10330 bfd * input_bfd,
10331 bfd * output_bfd,
10332 asection * input_section,
10333 bfd_byte * contents,
10334 Elf_Internal_Rela * rel,
10335 bfd_vma value,
10336 struct bfd_link_info * info,
10337 asection * sym_sec,
10338 const char * sym_name,
10339 unsigned char st_type,
10340 enum arm_st_branch_type branch_type,
0945cdfd 10341 struct elf_link_hash_entry * h,
07d6d2b8
AM		 10342 bfd_boolean * unresolved_reloc_p,
10343 char ** error_message)
10344{
10345 unsigned long r_type = howto->type;
10346 unsigned long r_symndx;
10347 bfd_byte * hit_data = contents + rel->r_offset;
10348 bfd_vma * local_got_offsets;
10349 bfd_vma * local_tlsdesc_gotents;
10350 asection * sgot;
10351 asection * splt;
10352 asection * sreloc = NULL;
10353 asection * srelgot;
10354 bfd_vma addend;
10355 bfd_signed_vma signed_addend;
10356 unsigned char dynreloc_st_type;
10357 bfd_vma dynreloc_value;
ba96a88f 10358 struct elf32_arm_link_hash_table * globals;
34e77a92 10359 struct elf32_arm_link_hash_entry *eh;
07d6d2b8
AM		 10360 union gotplt_union *root_plt;
10361 struct arm_plt_info *arm_plt;
10362 bfd_vma plt_offset;
10363 bfd_vma gotplt_offset;
10364 bfd_boolean has_iplt_entry;
10365 bfd_boolean resolved_to_zero;
f21f3fe0 10366
9c504268 10367 globals = elf32_arm_hash_table (info);
4dfe6ac6
NC		 10368 if (globals == NULL)
10369 return bfd_reloc_notsupported;
9c504268 10370
0ffa91dd 10371 BFD_ASSERT (is_arm_elf (input_bfd));
47aeb64c 10372 BFD_ASSERT (howto != NULL);
0ffa91dd
NC		 10373
10374 /* Some relocation types map to different relocations depending on the
9c504268 10375 target. We pick the right one here. */
eb043451 10376 r_type = arm_real_reloc_type (globals, r_type);
0855e32b
NS		 10377
10378 /* It is possible to have linker relaxations on some TLS access
10379 models. Update our information here. */
10380 r_type = elf32_arm_tls_transition (info, r_type, h);
10381
eb043451
PB		 10382 if (r_type != howto->type)
10383 howto = elf32_arm_howto_from_type (r_type);
9c504268 10384
34e77a92 10385 eh = (struct elf32_arm_link_hash_entry *) h;
362d30a1 10386 sgot = globals->root.sgot;
252b5132 10387 local_got_offsets = elf_local_got_offsets (input_bfd);
0855e32b
NS		 10388 local_tlsdesc_gotents = elf32_arm_local_tlsdesc_gotent (input_bfd);
10389
34e77a92
RS		 10390 if (globals->root.dynamic_sections_created)
10391 srelgot = globals->root.srelgot;
10392 else
10393 srelgot = NULL;
10394
252b5132
RH		 10395 r_symndx = ELF32_R_SYM (rel->r_info);
10396
4e7fd91e 10397 if (globals->use_rel)
ba96a88f 10398 {
4e7fd91e
PB		 10399 addend = bfd_get_32 (input_bfd, hit_data) & howto->src_mask;
10400
10401 if (addend & ((howto->src_mask + 1) >> 1))
10402 {
10403 signed_addend = -1;
10404 signed_addend &= ~ howto->src_mask;
10405 signed_addend |= addend;
10406 }
10407 else
10408 signed_addend = addend;
ba96a88f
NC		 10409 }
10410 else
4e7fd91e 10411 addend = signed_addend = rel->r_addend;
f21f3fe0 10412
39f21624
NC		 10413 /* ST_BRANCH_TO_ARM is nonsense to thumb-only targets when we
10414 are resolving a function call relocation. */
10415 if (using_thumb_only (globals)
10416 && (r_type == R_ARM_THM_CALL
10417 || r_type == R_ARM_THM_JUMP24)
10418 && branch_type == ST_BRANCH_TO_ARM)
10419 branch_type = ST_BRANCH_TO_THUMB;
10420
34e77a92
RS		 10421 /* Record the symbol information that should be used in dynamic
10422 relocations. */
10423 dynreloc_st_type = st_type;
10424 dynreloc_value = value;
10425 if (branch_type == ST_BRANCH_TO_THUMB)
10426 dynreloc_value |= 1;
10427
10428 /* Find out whether the symbol has a PLT. Set ST_VALUE, BRANCH_TYPE and
10429 VALUE appropriately for relocations that we resolve at link time. */
10430 has_iplt_entry = FALSE;
4ba2ef8f
TP		 10431 if (elf32_arm_get_plt_info (input_bfd, globals, eh, r_symndx, &root_plt,
10432 &arm_plt)
34e77a92
RS		 10433 && root_plt->offset != (bfd_vma) -1)
10434 {
10435 plt_offset = root_plt->offset;
10436 gotplt_offset = arm_plt->got_offset;
10437
10438 if (h == NULL || eh->is_iplt)
10439 {
10440 has_iplt_entry = TRUE;
10441 splt = globals->root.iplt;
10442
10443 /* Populate .iplt entries here, because not all of them will
10444 be seen by finish_dynamic_symbol. The lower bit is set if
10445 we have already populated the entry. */
10446 if (plt_offset & 1)
10447 plt_offset--;
10448 else
10449 {
57460bcf
NC		 10450 if (elf32_arm_populate_plt_entry (output_bfd, info, root_plt, arm_plt,
10451 -1, dynreloc_value))
10452 root_plt->offset |= 1;
10453 else
10454 return bfd_reloc_notsupported;
34e77a92
RS		 10455 }
10456
10457 /* Static relocations always resolve to the .iplt entry. */
10458 st_type = STT_FUNC;
10459 value = (splt->output_section->vma
10460 + splt->output_offset
10461 + plt_offset);
10462 branch_type = ST_BRANCH_TO_ARM;
10463
10464 /* If there are non-call relocations that resolve to the .iplt
10465 entry, then all dynamic ones must too. */
10466 if (arm_plt->noncall_refcount != 0)
10467 {
10468 dynreloc_st_type = st_type;
10469 dynreloc_value = value;
10470 }
10471 }
10472 else
10473 /* We populate the .plt entry in finish_dynamic_symbol. */
10474 splt = globals->root.splt;
10475 }
10476 else
10477 {
10478 splt = NULL;
10479 plt_offset = (bfd_vma) -1;
10480 gotplt_offset = (bfd_vma) -1;
10481 }
10482
95b03e4a
L		 10483 resolved_to_zero = (h != NULL
10484 && UNDEFWEAK_NO_DYNAMIC_RELOC (info, h));
10485
252b5132
RH		 10486 switch (r_type)
10487 {
10488 case R_ARM_NONE:
28a094c2
DJ		 10489 /* We don't need to find a value for this symbol. It's just a
10490 marker. */
10491 *unresolved_reloc_p = FALSE;
252b5132
RH		 10492 return bfd_reloc_ok;
10493
00a97672
RS		 10494 case R_ARM_ABS12:
10495 if (!globals->vxworks_p)
10496 return elf32_arm_abs12_reloc (input_bfd, hit_data, value + addend);
1a0670f3 10497 /* Fall through. */
00a97672 10498
252b5132
RH		 10499 case R_ARM_PC24:
10500 case R_ARM_ABS32:
bb224fc3 10501 case R_ARM_ABS32_NOI:
252b5132 10502 case R_ARM_REL32:
bb224fc3 10503 case R_ARM_REL32_NOI:
5b5bb741
PB		 10504 case R_ARM_CALL:
10505 case R_ARM_JUMP24:
dfc5f959 10506 case R_ARM_XPC25:
eb043451 10507 case R_ARM_PREL31:
7359ea65 10508 case R_ARM_PLT32:
7359ea65
DJ		 10509 /* Handle relocations which should use the PLT entry. ABS32/REL32
10510 will use the symbol's value, which may point to a PLT entry, but we
10511 don't need to handle that here. If we created a PLT entry, all
5fa9e92f
CL		 10512 branches in this object should go to it, except if the PLT is too
10513 far away, in which case a long branch stub should be inserted. */
bb224fc3 10514 if ((r_type != R_ARM_ABS32 && r_type != R_ARM_REL32
99059e56 10515 && r_type != R_ARM_ABS32_NOI && r_type != R_ARM_REL32_NOI
155d87d7
CL		 10516 && r_type != R_ARM_CALL
10517 && r_type != R_ARM_JUMP24
10518 && r_type != R_ARM_PLT32)
34e77a92 10519 && plt_offset != (bfd_vma) -1)
7359ea65 10520 {
34e77a92
RS		 10521 /* If we've created a .plt section, and assigned a PLT entry
10522 to this function, it must either be a STT_GNU_IFUNC reference
10523 or not be known to bind locally. In other cases, we should
10524 have cleared the PLT entry by now. */
10525 BFD_ASSERT (has_iplt_entry || !SYMBOL_CALLS_LOCAL (info, h));
7359ea65
DJ		 10526
10527 value = (splt->output_section->vma
10528 + splt->output_offset
34e77a92 10529 + plt_offset);
0945cdfd 10530 *unresolved_reloc_p = FALSE;
7359ea65
DJ		 10531 return _bfd_final_link_relocate (howto, input_bfd, input_section,
10532 contents, rel->r_offset, value,
00a97672 10533 rel->r_addend);
7359ea65
DJ		 10534 }
10535
67687978
PB		 10536 /* When generating a shared object or relocatable executable, these
10537 relocations are copied into the output file to be resolved at
10538 run time. */
0e1862bb 10539 if ((bfd_link_pic (info)
e8b09b87
CL		 10540 || globals->root.is_relocatable_executable
10541 || globals->fdpic_p)
7359ea65 10542 && (input_section->flags & SEC_ALLOC)
4dfe6ac6 10543 && !(globals->vxworks_p
3348747a
NS		 10544 && strcmp (input_section->output_section->name,
10545 ".tls_vars") == 0)
bb224fc3 10546 && ((r_type != R_ARM_REL32 && r_type != R_ARM_REL32_NOI)
ee06dc07 10547 || !SYMBOL_CALLS_LOCAL (info, h))
ca6b5f82
AM		 10548 && !(input_bfd == globals->stub_bfd
10549 && strstr (input_section->name, STUB_SUFFIX))
7359ea65 10550 && (h == NULL
95b03e4a
L		 10551 || (ELF_ST_VISIBILITY (h->other) == STV_DEFAULT
10552 && !resolved_to_zero)
7359ea65
DJ		 10553 || h->root.type != bfd_link_hash_undefweak)
10554 && r_type != R_ARM_PC24
5b5bb741
PB		 10555 && r_type != R_ARM_CALL
10556 && r_type != R_ARM_JUMP24
ee06dc07 10557 && r_type != R_ARM_PREL31
7359ea65 10558 && r_type != R_ARM_PLT32)
252b5132 10559 {
947216bf 10560 Elf_Internal_Rela outrel;
b34976b6 10561 bfd_boolean skip, relocate;
e8b09b87 10562 int isrofixup = 0;
f21f3fe0 10563
52db4ec2
JW		 10564 if ((r_type == R_ARM_REL32 || r_type == R_ARM_REL32_NOI)
10565 && !h->def_regular)
10566 {
10567 char *v = _("shared object");
10568
0e1862bb 10569 if (bfd_link_executable (info))
52db4ec2
JW		 10570 v = _("PIE executable");
10571
4eca0228 10572 _bfd_error_handler
871b3ab2 10573 (_("%pB: relocation %s against external or undefined symbol `%s'"
52db4ec2
JW		 10574 " can not be used when making a %s; recompile with -fPIC"), input_bfd,
10575 elf32_arm_howto_table_1[r_type].name, h->root.root.string, v);
10576 return bfd_reloc_notsupported;
10577 }
10578
0945cdfd
DJ		 10579 *unresolved_reloc_p = FALSE;
10580
34e77a92 10581 if (sreloc == NULL && globals->root.dynamic_sections_created)
252b5132 10582 {
83bac4b0
NC		 10583 sreloc = _bfd_elf_get_dynamic_reloc_section (input_bfd, input_section,
10584 ! globals->use_rel);
f21f3fe0 10585
83bac4b0 10586 if (sreloc == NULL)
252b5132 10587 return bfd_reloc_notsupported;
252b5132 10588 }
f21f3fe0 10589
b34976b6
AM		 10590 skip = FALSE;
10591 relocate = FALSE;
f21f3fe0 10592
00a97672 10593 outrel.r_addend = addend;
c629eae0
JJ		 10594 outrel.r_offset =
10595 _bfd_elf_section_offset (output_bfd, info, input_section,
10596 rel->r_offset);
10597 if (outrel.r_offset == (bfd_vma) -1)
b34976b6 10598 skip = TRUE;
0bb2d96a 10599 else if (outrel.r_offset == (bfd_vma) -2)
b34976b6 10600 skip = TRUE, relocate = TRUE;
252b5132
RH		 10601 outrel.r_offset += (input_section->output_section->vma
10602 + input_section->output_offset);
f21f3fe0 10603
252b5132 10604 if (skip)
0bb2d96a 10605 memset (&outrel, 0, sizeof outrel);
5e681ec4
PB		 10606 else if (h != NULL
10607 && h->dynindx != -1
0e1862bb 10608 && (!bfd_link_pic (info)
1dcb9720
JW		 10609 || !(bfd_link_pie (info)
10610 || SYMBOLIC_BIND (info, h))
f5385ebf 10611 || !h->def_regular))
5e681ec4 10612 outrel.r_info = ELF32_R_INFO (h->dynindx, r_type);
252b5132
RH		 10613 else
10614 {
a16385dc
MM		 10615 int symbol;
10616
5e681ec4 10617 /* This symbol is local, or marked to become local. */
e8b09b87
CL		 10618 BFD_ASSERT (r_type == R_ARM_ABS32 || r_type == R_ARM_ABS32_NOI
10619 || (globals->fdpic_p && !bfd_link_pic(info)));
a16385dc 10620 if (globals->symbian_p)
6366ff1e 10621 {
74541ad4
AM		 10622 asection *osec;
10623
6366ff1e
MM		 10624 /* On Symbian OS, the data segment and text segement
10625 can be relocated independently. Therefore, we
10626 must indicate the segment to which this
10627 relocation is relative. The BPABI allows us to
10628 use any symbol in the right segment; we just use
10629 the section symbol as it is convenient. (We
10630 cannot use the symbol given by "h" directly as it
74541ad4
AM		 10631 will not appear in the dynamic symbol table.)
10632
10633 Note that the dynamic linker ignores the section
10634 symbol value, so we don't subtract osec->vma
10635 from the emitted reloc addend. */
10dbd1f3 10636 if (sym_sec)
74541ad4 10637 osec = sym_sec->output_section;
10dbd1f3 10638 else
74541ad4
AM		 10639 osec = input_section->output_section;
10640 symbol = elf_section_data (osec)->dynindx;
10641 if (symbol == 0)
10642 {
10643 struct elf_link_hash_table *htab = elf_hash_table (info);
10644
10645 if ((osec->flags & SEC_READONLY) == 0
10646 && htab->data_index_section != NULL)
10647 osec = htab->data_index_section;
10648 else
10649 osec = htab->text_index_section;
10650 symbol = elf_section_data (osec)->dynindx;
10651 }
6366ff1e
MM		 10652 BFD_ASSERT (symbol != 0);
10653 }
a16385dc
MM		 10654 else
10655 /* On SVR4-ish systems, the dynamic loader cannot
10656 relocate the text and data segments independently,
10657 so the symbol does not matter. */
10658 symbol = 0;
34e77a92
RS		 10659 if (dynreloc_st_type == STT_GNU_IFUNC)
10660 /* We have an STT_GNU_IFUNC symbol that doesn't resolve
10661 to the .iplt entry. Instead, every non-call reference
10662 must use an R_ARM_IRELATIVE relocation to obtain the
10663 correct run-time address. */
10664 outrel.r_info = ELF32_R_INFO (symbol, R_ARM_IRELATIVE);
e8b09b87
CL		 10665 else if (globals->fdpic_p && !bfd_link_pic(info))
10666 isrofixup = 1;
34e77a92
RS		 10667 else
10668 outrel.r_info = ELF32_R_INFO (symbol, R_ARM_RELATIVE);
00a97672
RS		 10669 if (globals->use_rel)
10670 relocate = TRUE;
10671 else
34e77a92 10672 outrel.r_addend += dynreloc_value;
252b5132 10673 }
f21f3fe0 10674
e8b09b87
CL		 10675 if (isrofixup)
10676 arm_elf_add_rofixup(output_bfd, globals->srofixup, outrel.r_offset);
10677 else
10678 elf32_arm_add_dynreloc (output_bfd, info, sreloc, &outrel);
9a5aca8c 10679
f21f3fe0 10680 /* If this reloc is against an external symbol, we do not want to
252b5132 10681 fiddle with the addend. Otherwise, we need to include the symbol
9b485d32 10682 value so that it becomes an addend for the dynamic reloc. */
252b5132
RH		 10683 if (! relocate)
10684 return bfd_reloc_ok;
9a5aca8c 10685
f21f3fe0 10686 return _bfd_final_link_relocate (howto, input_bfd, input_section,
34e77a92
RS		 10687 contents, rel->r_offset,
10688 dynreloc_value, (bfd_vma) 0);
252b5132
RH		 10689 }
10690 else switch (r_type)
10691 {
00a97672
RS		 10692 case R_ARM_ABS12:
10693 return elf32_arm_abs12_reloc (input_bfd, hit_data, value + addend);
10694
dfc5f959 10695 case R_ARM_XPC25: /* Arm BLX instruction. */
5b5bb741
PB		 10696 case R_ARM_CALL:
10697 case R_ARM_JUMP24:
8029a119 10698 case R_ARM_PC24: /* Arm B/BL instruction. */
7359ea65 10699 case R_ARM_PLT32:
906e58ca 10700 {
906e58ca
NC		 10701 struct elf32_arm_stub_hash_entry *stub_entry = NULL;
10702
dfc5f959 10703 if (r_type == R_ARM_XPC25)
252b5132 10704 {
dfc5f959
NC		 10705 /* Check for Arm calling Arm function. */
10706 /* FIXME: Should we translate the instruction into a BL
10707 instruction instead ? */
35fc36a8 10708 if (branch_type != ST_BRANCH_TO_THUMB)
4eca0228 10709 _bfd_error_handler
90b6238f
AM		 10710 (_("\%pB: warning: %s BLX instruction targets"
10711 " %s function '%s'"),
10712 input_bfd, "ARM",
10713 "ARM", h ? h->root.root.string : "(local)");
dfc5f959 10714 }
155d87d7 10715 else if (r_type == R_ARM_PC24)
dfc5f959
NC		 10716 {
10717 /* Check for Arm calling Thumb function. */
35fc36a8 10718 if (branch_type == ST_BRANCH_TO_THUMB)
dfc5f959 10719 {
f2a9dd69
DJ		 10720 if (elf32_arm_to_thumb_stub (info, sym_name, input_bfd,
10721 output_bfd, input_section,
10722 hit_data, sym_sec, rel->r_offset,
10723 signed_addend, value,
10724 error_message))
10725 return bfd_reloc_ok;
10726 else
10727 return bfd_reloc_dangerous;
dfc5f959 10728 }
252b5132 10729 }
ba96a88f 10730
906e58ca 10731 /* Check if a stub has to be inserted because the
8029a119 10732 destination is too far or we are changing mode. */
155d87d7
CL		 10733 if ( r_type == R_ARM_CALL
10734 || r_type == R_ARM_JUMP24
10735 || r_type == R_ARM_PLT32)
906e58ca 10736 {
fe33d2fa
CL		 10737 enum elf32_arm_stub_type stub_type = arm_stub_none;
10738 struct elf32_arm_link_hash_entry *hash;
10739
10740 hash = (struct elf32_arm_link_hash_entry *) h;
10741 stub_type = arm_type_of_stub (info, input_section, rel,
34e77a92
RS		 10742 st_type, &branch_type,
10743 hash, value, sym_sec,
fe33d2fa 10744 input_bfd, sym_name);
5fa9e92f 10745
fe33d2fa 10746 if (stub_type != arm_stub_none)
906e58ca
NC		 10747 {
10748 /* The target is out of reach, so redirect the
10749 branch to the local stub for this function. */
906e58ca
NC		 10750 stub_entry = elf32_arm_get_stub_entry (input_section,
10751 sym_sec, h,
fe33d2fa
CL		 10752 rel, globals,
10753 stub_type);
9cd3e4e5
NC		 10754 {
10755 if (stub_entry != NULL)
10756 value = (stub_entry->stub_offset
10757 + stub_entry->stub_sec->output_offset
10758 + stub_entry->stub_sec->output_section->vma);
10759
10760 if (plt_offset != (bfd_vma) -1)
10761 *unresolved_reloc_p = FALSE;
10762 }
906e58ca 10763 }
fe33d2fa
CL		 10764 else
10765 {
10766 /* If the call goes through a PLT entry, make sure to
10767 check distance to the right destination address. */
34e77a92 10768 if (plt_offset != (bfd_vma) -1)
fe33d2fa
CL		 10769 {
10770 value = (splt->output_section->vma
10771 + splt->output_offset
34e77a92 10772 + plt_offset);
fe33d2fa
CL		 10773 *unresolved_reloc_p = FALSE;
10774 /* The PLT entry is in ARM mode, regardless of the
10775 target function. */
35fc36a8 10776 branch_type = ST_BRANCH_TO_ARM;
fe33d2fa
CL		 10777 }
10778 }
906e58ca
NC		 10779 }
10780
dea514f5
PB		 10781 /* The ARM ELF ABI says that this reloc is computed as: S - P + A
10782 where:
10783 S is the address of the symbol in the relocation.
10784 P is address of the instruction being relocated.
10785 A is the addend (extracted from the instruction) in bytes.
10786
10787 S is held in 'value'.
10788 P is the base address of the section containing the
10789 instruction plus the offset of the reloc into that
10790 section, ie:
10791 (input_section->output_section->vma +
10792 input_section->output_offset +
10793 rel->r_offset).
10794 A is the addend, converted into bytes, ie:
10795 (signed_addend * 4)
10796
10797 Note: None of these operations have knowledge of the pipeline
10798 size of the processor, thus it is up to the assembler to
10799 encode this information into the addend. */
10800 value -= (input_section->output_section->vma
10801 + input_section->output_offset);
10802 value -= rel->r_offset;
4e7fd91e
PB		 10803 if (globals->use_rel)
10804 value += (signed_addend << howto->size);
10805 else
10806 /* RELA addends do not have to be adjusted by howto->size. */
10807 value += signed_addend;
23080146 10808
dcb5e6e6
NC		 10809 signed_addend = value;
10810 signed_addend >>= howto->rightshift;
9a5aca8c 10811
5ab79981 10812 /* A branch to an undefined weak symbol is turned into a jump to
ffcb4889 10813 the next instruction unless a PLT entry will be created.
77b4f08f 10814 Do the same for local undefined symbols (but not for STN_UNDEF).
cd1dac3d
DG		 10815 The jump to the next instruction is optimized as a NOP depending
10816 on the architecture. */
ffcb4889 10817 if (h ? (h->root.type == bfd_link_hash_undefweak
34e77a92 10818 && plt_offset == (bfd_vma) -1)
77b4f08f 10819 : r_symndx != STN_UNDEF && bfd_is_und_section (sym_sec))
5ab79981 10820 {
cd1dac3d
DG		 10821 value = (bfd_get_32 (input_bfd, hit_data) & 0xf0000000);
10822
10823 if (arch_has_arm_nop (globals))
10824 value |= 0x0320f000;
10825 else
10826 value |= 0x01a00000; /* Using pre-UAL nop: mov r0, r0. */
5ab79981
PB		 10827 }
10828 else
59f2c4e7 10829 {
9b485d32 10830 /* Perform a signed range check. */
dcb5e6e6 10831 if ( signed_addend > ((bfd_signed_vma) (howto->dst_mask >> 1))
59f2c4e7
NC		 10832 || signed_addend < - ((bfd_signed_vma) ((howto->dst_mask + 1) >> 1)))
10833 return bfd_reloc_overflow;
9a5aca8c 10834
5ab79981 10835 addend = (value & 2);
39b41c9c 10836
5ab79981
PB		 10837 value = (signed_addend & howto->dst_mask)
10838 | (bfd_get_32 (input_bfd, hit_data) & (~ howto->dst_mask));
39b41c9c 10839
5ab79981
PB		 10840 if (r_type == R_ARM_CALL)
10841 {
155d87d7 10842 /* Set the H bit in the BLX instruction. */
35fc36a8 10843 if (branch_type == ST_BRANCH_TO_THUMB)
155d87d7
CL		 10844 {
10845 if (addend)
10846 value |= (1 << 24);
10847 else
10848 value &= ~(bfd_vma)(1 << 24);
10849 }
10850
5ab79981 10851 /* Select the correct instruction (BL or BLX). */
906e58ca 10852 /* Only if we are not handling a BL to a stub. In this
8029a119 10853 case, mode switching is performed by the stub. */
35fc36a8 10854 if (branch_type == ST_BRANCH_TO_THUMB && !stub_entry)
5ab79981 10855 value |= (1 << 28);
63e1a0fc 10856 else if (stub_entry || branch_type != ST_BRANCH_UNKNOWN)
5ab79981
PB		 10857 {
10858 value &= ~(bfd_vma)(1 << 28);
10859 value |= (1 << 24);
10860 }
39b41c9c
PB		 10861 }
10862 }
906e58ca 10863 }
252b5132 10864 break;
f21f3fe0 10865
252b5132
RH		 10866 case R_ARM_ABS32:
10867 value += addend;
35fc36a8 10868 if (branch_type == ST_BRANCH_TO_THUMB)
252b5132
RH		 10869 value |= 1;
10870 break;
f21f3fe0 10871
bb224fc3
MS		 10872 case R_ARM_ABS32_NOI:
10873 value += addend;
10874 break;
10875
252b5132 10876 case R_ARM_REL32:
a8bc6c78 10877 value += addend;
35fc36a8 10878 if (branch_type == ST_BRANCH_TO_THUMB)
a8bc6c78 10879 value |= 1;
252b5132 10880 value -= (input_section->output_section->vma
62efb346 10881 + input_section->output_offset + rel->r_offset);
252b5132 10882 break;
eb043451 10883
bb224fc3
MS		 10884 case R_ARM_REL32_NOI:
10885 value += addend;
10886 value -= (input_section->output_section->vma
10887 + input_section->output_offset + rel->r_offset);
10888 break;
10889
eb043451
PB		 10890 case R_ARM_PREL31:
10891 value -= (input_section->output_section->vma
10892 + input_section->output_offset + rel->r_offset);
10893 value += signed_addend;
10894 if (! h || h->root.type != bfd_link_hash_undefweak)
10895 {
8029a119 10896 /* Check for overflow. */
eb043451
PB		 10897 if ((value ^ (value >> 1)) & (1 << 30))
10898 return bfd_reloc_overflow;
10899 }
10900 value &= 0x7fffffff;
10901 value |= (bfd_get_32 (input_bfd, hit_data) & 0x80000000);
35fc36a8 10902 if (branch_type == ST_BRANCH_TO_THUMB)
eb043451
PB		 10903 value |= 1;
10904 break;
252b5132 10905 }
f21f3fe0 10906
252b5132
RH		 10907 bfd_put_32 (input_bfd, value, hit_data);
10908 return bfd_reloc_ok;
10909
10910 case R_ARM_ABS8:
fd0fd00c
MJ		 10911 /* PR 16202: Refectch the addend using the correct size. */
10912 if (globals->use_rel)
10913 addend = bfd_get_8 (input_bfd, hit_data);
252b5132 10914 value += addend;
4e67d4ca
DG		 10915
10916 /* There is no way to tell whether the user intended to use a signed or
10917 unsigned addend. When checking for overflow we accept either,
10918 as specified by the AAELF. */
10919 if ((long) value > 0xff || (long) value < -0x80)
252b5132
RH		 10920 return bfd_reloc_overflow;
10921
10922 bfd_put_8 (input_bfd, value, hit_data);
10923 return bfd_reloc_ok;
10924
10925 case R_ARM_ABS16:
fd0fd00c
MJ		 10926 /* PR 16202: Refectch the addend using the correct size. */
10927 if (globals->use_rel)
10928 addend = bfd_get_16 (input_bfd, hit_data);
252b5132
RH		 10929 value += addend;
10930
4e67d4ca
DG		 10931 /* See comment for R_ARM_ABS8. */
10932 if ((long) value > 0xffff || (long) value < -0x8000)
252b5132
RH		 10933 return bfd_reloc_overflow;
10934
10935 bfd_put_16 (input_bfd, value, hit_data);
10936 return bfd_reloc_ok;
10937
252b5132 10938 case R_ARM_THM_ABS5:
9b485d32 10939 /* Support ldr and str instructions for the thumb. */
4e7fd91e
PB		 10940 if (globals->use_rel)
10941 {
10942 /* Need to refetch addend. */
10943 addend = bfd_get_16 (input_bfd, hit_data) & howto->src_mask;
10944 /* ??? Need to determine shift amount from operand size. */
10945 addend >>= howto->rightshift;
10946 }
252b5132
RH		 10947 value += addend;
10948
10949 /* ??? Isn't value unsigned? */
10950 if ((long) value > 0x1f || (long) value < -0x10)
10951 return bfd_reloc_overflow;
10952
10953 /* ??? Value needs to be properly shifted into place first. */
10954 value |= bfd_get_16 (input_bfd, hit_data) & 0xf83f;
10955 bfd_put_16 (input_bfd, value, hit_data);
10956 return bfd_reloc_ok;
10957
2cab6cc3
MS		 10958 case R_ARM_THM_ALU_PREL_11_0:
10959 /* Corresponds to: addw.w reg, pc, #offset (and similarly for subw). */
10960 {
10961 bfd_vma insn;
10962 bfd_signed_vma relocation;
10963
10964 insn = (bfd_get_16 (input_bfd, hit_data) << 16)
99059e56 10965 | bfd_get_16 (input_bfd, hit_data + 2);
2cab6cc3 10966
99059e56
RM		 10967 if (globals->use_rel)
10968 {
10969 signed_addend = (insn & 0xff) | ((insn & 0x7000) >> 4)
10970 | ((insn & (1 << 26)) >> 15);
10971 if (insn & 0xf00000)
10972 signed_addend = -signed_addend;
10973 }
2cab6cc3
MS		 10974
10975 relocation = value + signed_addend;
79f08007 10976 relocation -= Pa (input_section->output_section->vma
99059e56
RM		 10977 + input_section->output_offset
10978 + rel->r_offset);
2cab6cc3 10979
8c65b54f
CS		 10980 /* PR 21523: Use an absolute value. The user of this reloc will
10981 have already selected an ADD or SUB insn appropriately. */
453f8e1e 10982 value = llabs (relocation);
2cab6cc3 10983
99059e56
RM		 10984 if (value >= 0x1000)
10985 return bfd_reloc_overflow;
2cab6cc3 10986
e645cf40
AG		 10987 /* Destination is Thumb. Force bit 0 to 1 to reflect this. */
10988 if (branch_type == ST_BRANCH_TO_THUMB)
10989 value |= 1;
10990
2cab6cc3 10991 insn = (insn & 0xfb0f8f00) | (value & 0xff)
99059e56
RM		 10992 | ((value & 0x700) << 4)
10993 | ((value & 0x800) << 15);
10994 if (relocation < 0)
10995 insn |= 0xa00000;
2cab6cc3
MS		 10996
10997 bfd_put_16 (input_bfd, insn >> 16, hit_data);
10998 bfd_put_16 (input_bfd, insn & 0xffff, hit_data + 2);
10999
99059e56 11000 return bfd_reloc_ok;
2cab6cc3
MS		 11001 }
11002
e1ec24c6
NC		 11003 case R_ARM_THM_PC8:
11004 /* PR 10073: This reloc is not generated by the GNU toolchain,
11005 but it is supported for compatibility with third party libraries
11006 generated by other compilers, specifically the ARM/IAR. */
11007 {
11008 bfd_vma insn;
11009 bfd_signed_vma relocation;
11010
11011 insn = bfd_get_16 (input_bfd, hit_data);
11012
99059e56 11013 if (globals->use_rel)
79f08007 11014 addend = ((((insn & 0x00ff) << 2) + 4) & 0x3ff) -4;
e1ec24c6
NC		 11015
11016 relocation = value + addend;
79f08007 11017 relocation -= Pa (input_section->output_section->vma
99059e56
RM		 11018 + input_section->output_offset
11019 + rel->r_offset);
e1ec24c6 11020
b6518b38 11021 value = relocation;
e1ec24c6
NC		 11022
11023 /* We do not check for overflow of this reloc. Although strictly
11024 speaking this is incorrect, it appears to be necessary in order
11025 to work with IAR generated relocs. Since GCC and GAS do not
11026 generate R_ARM_THM_PC8 relocs, the lack of a check should not be
11027 a problem for them. */
11028 value &= 0x3fc;
11029
11030 insn = (insn & 0xff00) | (value >> 2);
11031
11032 bfd_put_16 (input_bfd, insn, hit_data);
11033
99059e56 11034 return bfd_reloc_ok;
e1ec24c6
NC		 11035 }
11036
2cab6cc3
MS		 11037 case R_ARM_THM_PC12:
11038 /* Corresponds to: ldr.w reg, [pc, #offset]. */
11039 {
11040 bfd_vma insn;
11041 bfd_signed_vma relocation;
11042
11043 insn = (bfd_get_16 (input_bfd, hit_data) << 16)
99059e56 11044 | bfd_get_16 (input_bfd, hit_data + 2);
2cab6cc3 11045
99059e56
RM		 11046 if (globals->use_rel)
11047 {
11048 signed_addend = insn & 0xfff;
11049 if (!(insn & (1 << 23)))
11050 signed_addend = -signed_addend;
11051 }
2cab6cc3
MS		 11052
11053 relocation = value + signed_addend;
79f08007 11054 relocation -= Pa (input_section->output_section->vma
99059e56
RM		 11055 + input_section->output_offset
11056 + rel->r_offset);
2cab6cc3 11057
b6518b38 11058 value = relocation;
2cab6cc3 11059
99059e56
RM		 11060 if (value >= 0x1000)
11061 return bfd_reloc_overflow;
2cab6cc3
MS		 11062
11063 insn = (insn & 0xff7ff000) | value;
99059e56
RM		 11064 if (relocation >= 0)
11065 insn |= (1 << 23);
2cab6cc3
MS		 11066
11067 bfd_put_16 (input_bfd, insn >> 16, hit_data);
11068 bfd_put_16 (input_bfd, insn & 0xffff, hit_data + 2);
11069
99059e56 11070 return bfd_reloc_ok;
2cab6cc3
MS		 11071 }
11072
dfc5f959 11073 case R_ARM_THM_XPC22:
c19d1205 11074 case R_ARM_THM_CALL:
bd97cb95 11075 case R_ARM_THM_JUMP24:
dfc5f959 11076 /* Thumb BL (branch long instruction). */
252b5132 11077 {
b34976b6 11078 bfd_vma relocation;
99059e56 11079 bfd_vma reloc_sign;
b34976b6
AM		 11080 bfd_boolean overflow = FALSE;
11081 bfd_vma upper_insn = bfd_get_16 (input_bfd, hit_data);
11082 bfd_vma lower_insn = bfd_get_16 (input_bfd, hit_data + 2);
e95de063
MS		 11083 bfd_signed_vma reloc_signed_max;
11084 bfd_signed_vma reloc_signed_min;
b34976b6 11085 bfd_vma check;
252b5132 11086 bfd_signed_vma signed_check;
e95de063 11087 int bitsize;
cd1dac3d 11088 const int thumb2 = using_thumb2 (globals);
5e866f5a 11089 const int thumb2_bl = using_thumb2_bl (globals);
252b5132 11090
5ab79981 11091 /* A branch to an undefined weak symbol is turned into a jump to
cd1dac3d
DG		 11092 the next instruction unless a PLT entry will be created.
11093 The jump to the next instruction is optimized as a NOP.W for
11094 Thumb-2 enabled architectures. */
19540007 11095 if (h && h->root.type == bfd_link_hash_undefweak
34e77a92 11096 && plt_offset == (bfd_vma) -1)
5ab79981 11097 {
60a019a0 11098 if (thumb2)
cd1dac3d
DG		 11099 {
11100 bfd_put_16 (input_bfd, 0xf3af, hit_data);
11101 bfd_put_16 (input_bfd, 0x8000, hit_data + 2);
11102 }
11103 else
11104 {
11105 bfd_put_16 (input_bfd, 0xe000, hit_data);
11106 bfd_put_16 (input_bfd, 0xbf00, hit_data + 2);
11107 }
5ab79981
PB		 11108 return bfd_reloc_ok;
11109 }
11110
e95de063 11111 /* Fetch the addend. We use the Thumb-2 encoding (backwards compatible
99059e56 11112 with Thumb-1) involving the J1 and J2 bits. */
4e7fd91e
PB		 11113 if (globals->use_rel)
11114 {
99059e56
RM		 11115 bfd_vma s = (upper_insn & (1 << 10)) >> 10;
11116 bfd_vma upper = upper_insn & 0x3ff;
11117 bfd_vma lower = lower_insn & 0x7ff;
e95de063
MS		 11118 bfd_vma j1 = (lower_insn & (1 << 13)) >> 13;
11119 bfd_vma j2 = (lower_insn & (1 << 11)) >> 11;
99059e56
RM		 11120 bfd_vma i1 = j1 ^ s ? 0 : 1;
11121 bfd_vma i2 = j2 ^ s ? 0 : 1;
e95de063 11122
99059e56
RM		 11123 addend = (i1 << 23) | (i2 << 22) | (upper << 12) | (lower << 1);
11124 /* Sign extend. */
11125 addend = (addend | ((s ? 0 : 1) << 24)) - (1 << 24);
e95de063 11126
4e7fd91e
PB		 11127 signed_addend = addend;
11128 }
cb1afa5c 11129
dfc5f959
NC		 11130 if (r_type == R_ARM_THM_XPC22)
11131 {
11132 /* Check for Thumb to Thumb call. */
11133 /* FIXME: Should we translate the instruction into a BL
11134 instruction instead ? */
35fc36a8 11135 if (branch_type == ST_BRANCH_TO_THUMB)
4eca0228 11136 _bfd_error_handler
90b6238f
AM		 11137 (_("%pB: warning: %s BLX instruction targets"
11138 " %s function '%s'"),
11139 input_bfd, "Thumb",
11140 "Thumb", h ? h->root.root.string : "(local)");
dfc5f959
NC		 11141 }
11142 else
252b5132 11143 {
dfc5f959
NC		 11144 /* If it is not a call to Thumb, assume call to Arm.
11145 If it is a call relative to a section name, then it is not a
b7693d02
DJ		 11146 function call at all, but rather a long jump. Calls through
11147 the PLT do not require stubs. */
34e77a92 11148 if (branch_type == ST_BRANCH_TO_ARM && plt_offset == (bfd_vma) -1)
dfc5f959 11149 {
bd97cb95 11150 if (globals->use_blx && r_type == R_ARM_THM_CALL)
39b41c9c
PB		 11151 {
11152 /* Convert BL to BLX. */
11153 lower_insn = (lower_insn & ~0x1000) | 0x0800;
11154 }
155d87d7
CL		 11155 else if (( r_type != R_ARM_THM_CALL)
11156 && (r_type != R_ARM_THM_JUMP24))
8029a119
NC		 11157 {
11158 if (elf32_thumb_to_arm_stub
11159 (info, sym_name, input_bfd, output_bfd, input_section,
11160 hit_data, sym_sec, rel->r_offset, signed_addend, value,
11161 error_message))
11162 return bfd_reloc_ok;
11163 else
11164 return bfd_reloc_dangerous;
11165 }
da5938a2 11166 }
35fc36a8
RS		 11167 else if (branch_type == ST_BRANCH_TO_THUMB
11168 && globals->use_blx
bd97cb95 11169 && r_type == R_ARM_THM_CALL)
39b41c9c
PB		 11170 {
11171 /* Make sure this is a BL. */
11172 lower_insn |= 0x1800;
11173 }
252b5132 11174 }
f21f3fe0 11175
fe33d2fa 11176 enum elf32_arm_stub_type stub_type = arm_stub_none;
155d87d7 11177 if (r_type == R_ARM_THM_CALL || r_type == R_ARM_THM_JUMP24)
906e58ca
NC		 11178 {
11179 /* Check if a stub has to be inserted because the destination
8029a119 11180 is too far. */
fe33d2fa
CL		 11181 struct elf32_arm_stub_hash_entry *stub_entry;
11182 struct elf32_arm_link_hash_entry *hash;
11183
11184 hash = (struct elf32_arm_link_hash_entry *) h;
11185
11186 stub_type = arm_type_of_stub (info, input_section, rel,
34e77a92
RS		 11187 st_type, &branch_type,
11188 hash, value, sym_sec,
fe33d2fa
CL		 11189 input_bfd, sym_name);
11190
11191 if (stub_type != arm_stub_none)
906e58ca
NC		 11192 {
11193 /* The target is out of reach or we are changing modes, so
11194 redirect the branch to the local stub for this
11195 function. */
11196 stub_entry = elf32_arm_get_stub_entry (input_section,
11197 sym_sec, h,
fe33d2fa
CL		 11198 rel, globals,
11199 stub_type);
906e58ca 11200 if (stub_entry != NULL)
9cd3e4e5
NC		 11201 {
11202 value = (stub_entry->stub_offset
11203 + stub_entry->stub_sec->output_offset
11204 + stub_entry->stub_sec->output_section->vma);
11205
11206 if (plt_offset != (bfd_vma) -1)
11207 *unresolved_reloc_p = FALSE;
11208 }
906e58ca 11209
f4ac8484 11210 /* If this call becomes a call to Arm, force BLX. */
155d87d7 11211 if (globals->use_blx && (r_type == R_ARM_THM_CALL))
f4ac8484
DJ		 11212 {
11213 if ((stub_entry
11214 && !arm_stub_is_thumb (stub_entry->stub_type))
35fc36a8 11215 || branch_type != ST_BRANCH_TO_THUMB)
f4ac8484
DJ		 11216 lower_insn = (lower_insn & ~0x1000) | 0x0800;
11217 }
906e58ca
NC		 11218 }
11219 }
11220
fe33d2fa 11221 /* Handle calls via the PLT. */
34e77a92 11222 if (stub_type == arm_stub_none && plt_offset != (bfd_vma) -1)
fe33d2fa
CL		 11223 {
11224 value = (splt->output_section->vma
11225 + splt->output_offset
34e77a92 11226 + plt_offset);
fe33d2fa 11227
eed94f8f
NC		 11228 if (globals->use_blx
11229 && r_type == R_ARM_THM_CALL
11230 && ! using_thumb_only (globals))
fe33d2fa
CL		 11231 {
11232 /* If the Thumb BLX instruction is available, convert
11233 the BL to a BLX instruction to call the ARM-mode
11234 PLT entry. */
11235 lower_insn = (lower_insn & ~0x1000) | 0x0800;
35fc36a8 11236 branch_type = ST_BRANCH_TO_ARM;
fe33d2fa
CL		 11237 }
11238 else
11239 {
eed94f8f
NC		 11240 if (! using_thumb_only (globals))
11241 /* Target the Thumb stub before the ARM PLT entry. */
11242 value -= PLT_THUMB_STUB_SIZE;
35fc36a8 11243 branch_type = ST_BRANCH_TO_THUMB;
fe33d2fa
CL		 11244 }
11245 *unresolved_reloc_p = FALSE;
11246 }
11247
ba96a88f 11248 relocation = value + signed_addend;
f21f3fe0 11249
252b5132 11250 relocation -= (input_section->output_section->vma
ba96a88f
NC		 11251 + input_section->output_offset
11252 + rel->r_offset);
9a5aca8c 11253
252b5132
RH		 11254 check = relocation >> howto->rightshift;
11255
11256 /* If this is a signed value, the rightshift just dropped
11257 leading 1 bits (assuming twos complement). */
11258 if ((bfd_signed_vma) relocation >= 0)
11259 signed_check = check;
11260 else
11261 signed_check = check | ~((bfd_vma) -1 >> howto->rightshift);
11262
e95de063
MS		 11263 /* Calculate the permissable maximum and minimum values for
11264 this relocation according to whether we're relocating for
11265 Thumb-2 or not. */
11266 bitsize = howto->bitsize;
5e866f5a 11267 if (!thumb2_bl)
e95de063 11268 bitsize -= 2;
f6ebfac0 11269 reloc_signed_max = (1 << (bitsize - 1)) - 1;
e95de063
MS		 11270 reloc_signed_min = ~reloc_signed_max;
11271
252b5132 11272 /* Assumes two's complement. */
ba96a88f 11273 if (signed_check > reloc_signed_max || signed_check < reloc_signed_min)
b34976b6 11274 overflow = TRUE;
252b5132 11275
bd97cb95 11276 if ((lower_insn & 0x5000) == 0x4000)
c62e1cc3
NC		 11277 /* For a BLX instruction, make sure that the relocation is rounded up
11278 to a word boundary. This follows the semantics of the instruction
11279 which specifies that bit 1 of the target address will come from bit
11280 1 of the base address. */
11281 relocation = (relocation + 2) & ~ 3;
cb1afa5c 11282
e95de063
MS		 11283 /* Put RELOCATION back into the insn. Assumes two's complement.
11284 We use the Thumb-2 encoding, which is safe even if dealing with
11285 a Thumb-1 instruction by virtue of our overflow check above. */
99059e56 11286 reloc_sign = (signed_check < 0) ? 1 : 0;
e95de063 11287 upper_insn = (upper_insn & ~(bfd_vma) 0x7ff)
99059e56
RM		 11288 | ((relocation >> 12) & 0x3ff)
11289 | (reloc_sign << 10);
906e58ca 11290 lower_insn = (lower_insn & ~(bfd_vma) 0x2fff)
99059e56
RM		 11291 | (((!((relocation >> 23) & 1)) ^ reloc_sign) << 13)
11292 | (((!((relocation >> 22) & 1)) ^ reloc_sign) << 11)
11293 | ((relocation >> 1) & 0x7ff);
c62e1cc3 11294
252b5132
RH		 11295 /* Put the relocated value back in the object file: */
11296 bfd_put_16 (input_bfd, upper_insn, hit_data);
11297 bfd_put_16 (input_bfd, lower_insn, hit_data + 2);
11298
11299 return (overflow ? bfd_reloc_overflow : bfd_reloc_ok);
11300 }
11301 break;
11302
c19d1205
ZW		 11303 case R_ARM_THM_JUMP19:
11304 /* Thumb32 conditional branch instruction. */
11305 {
11306 bfd_vma relocation;
11307 bfd_boolean overflow = FALSE;
11308 bfd_vma upper_insn = bfd_get_16 (input_bfd, hit_data);
11309 bfd_vma lower_insn = bfd_get_16 (input_bfd, hit_data + 2);
a00a1f35
MS		 11310 bfd_signed_vma reloc_signed_max = 0xffffe;
11311 bfd_signed_vma reloc_signed_min = -0x100000;
c19d1205 11312 bfd_signed_vma signed_check;
07d6d2b8 11313 enum elf32_arm_stub_type stub_type = arm_stub_none;
c5423981
TG		 11314 struct elf32_arm_stub_hash_entry *stub_entry;
11315 struct elf32_arm_link_hash_entry *hash;
c19d1205
ZW		 11316
11317 /* Need to refetch the addend, reconstruct the top three bits,
11318 and squish the two 11 bit pieces together. */
11319 if (globals->use_rel)
11320 {
11321 bfd_vma S = (upper_insn & 0x0400) >> 10;
a00a1f35 11322 bfd_vma upper = (upper_insn & 0x003f);
c19d1205
ZW		 11323 bfd_vma J1 = (lower_insn & 0x2000) >> 13;
11324 bfd_vma J2 = (lower_insn & 0x0800) >> 11;
11325 bfd_vma lower = (lower_insn & 0x07ff);
11326
a00a1f35
MS		 11327 upper |= J1 << 6;
11328 upper |= J2 << 7;
11329 upper |= (!S) << 8;
c19d1205
ZW		 11330 upper -= 0x0100; /* Sign extend. */
11331
11332 addend = (upper << 12) | (lower << 1);
11333 signed_addend = addend;
11334 }
11335
bd97cb95 11336 /* Handle calls via the PLT. */
34e77a92 11337 if (plt_offset != (bfd_vma) -1)
bd97cb95
DJ		 11338 {
11339 value = (splt->output_section->vma
11340 + splt->output_offset
34e77a92 11341 + plt_offset);
bd97cb95
DJ		 11342 /* Target the Thumb stub before the ARM PLT entry. */
11343 value -= PLT_THUMB_STUB_SIZE;
11344 *unresolved_reloc_p = FALSE;
11345 }
11346
c5423981
TG		 11347 hash = (struct elf32_arm_link_hash_entry *)h;
11348
11349 stub_type = arm_type_of_stub (info, input_section, rel,
07d6d2b8
AM		 11350 st_type, &branch_type,
11351 hash, value, sym_sec,
11352 input_bfd, sym_name);
c5423981
TG		 11353 if (stub_type != arm_stub_none)
11354 {
11355 stub_entry = elf32_arm_get_stub_entry (input_section,
07d6d2b8
AM		 11356 sym_sec, h,
11357 rel, globals,
11358 stub_type);
c5423981
TG		 11359 if (stub_entry != NULL)
11360 {
07d6d2b8
AM		 11361 value = (stub_entry->stub_offset
11362 + stub_entry->stub_sec->output_offset
11363 + stub_entry->stub_sec->output_section->vma);
c5423981
TG		 11364 }
11365 }
c19d1205 11366
99059e56 11367 relocation = value + signed_addend;
c19d1205
ZW		 11368 relocation -= (input_section->output_section->vma
11369 + input_section->output_offset
11370 + rel->r_offset);
a00a1f35 11371 signed_check = (bfd_signed_vma) relocation;
c19d1205 11372
c19d1205
ZW		 11373 if (signed_check > reloc_signed_max || signed_check < reloc_signed_min)
11374 overflow = TRUE;
11375
11376 /* Put RELOCATION back into the insn. */
11377 {
11378 bfd_vma S = (relocation & 0x00100000) >> 20;
11379 bfd_vma J2 = (relocation & 0x00080000) >> 19;
11380 bfd_vma J1 = (relocation & 0x00040000) >> 18;
11381 bfd_vma hi = (relocation & 0x0003f000) >> 12;
11382 bfd_vma lo = (relocation & 0x00000ffe) >> 1;
11383
a00a1f35 11384 upper_insn = (upper_insn & 0xfbc0) | (S << 10) | hi;
c19d1205
ZW		 11385 lower_insn = (lower_insn & 0xd000) | (J1 << 13) | (J2 << 11) | lo;
11386 }
11387
11388 /* Put the relocated value back in the object file: */
11389 bfd_put_16 (input_bfd, upper_insn, hit_data);
11390 bfd_put_16 (input_bfd, lower_insn, hit_data + 2);
11391
11392 return (overflow ? bfd_reloc_overflow : bfd_reloc_ok);
11393 }
11394
11395 case R_ARM_THM_JUMP11:
11396 case R_ARM_THM_JUMP8:
11397 case R_ARM_THM_JUMP6:
51c5503b
NC		 11398 /* Thumb B (branch) instruction). */
11399 {
6cf9e9fe 11400 bfd_signed_vma relocation;
51c5503b
NC		 11401 bfd_signed_vma reloc_signed_max = (1 << (howto->bitsize - 1)) - 1;
11402 bfd_signed_vma reloc_signed_min = ~ reloc_signed_max;
51c5503b
NC		 11403 bfd_signed_vma signed_check;
11404
c19d1205
ZW		 11405 /* CZB cannot jump backward. */
11406 if (r_type == R_ARM_THM_JUMP6)
11407 reloc_signed_min = 0;
11408
4e7fd91e 11409 if (globals->use_rel)
6cf9e9fe 11410 {
4e7fd91e
PB		 11411 /* Need to refetch addend. */
11412 addend = bfd_get_16 (input_bfd, hit_data) & howto->src_mask;
11413 if (addend & ((howto->src_mask + 1) >> 1))
11414 {
11415 signed_addend = -1;
11416 signed_addend &= ~ howto->src_mask;
11417 signed_addend |= addend;
11418 }
11419 else
11420 signed_addend = addend;
11421 /* The value in the insn has been right shifted. We need to
11422 undo this, so that we can perform the address calculation
11423 in terms of bytes. */
11424 signed_addend <<= howto->rightshift;
6cf9e9fe 11425 }
6cf9e9fe 11426 relocation = value + signed_addend;
51c5503b
NC		 11427
11428 relocation -= (input_section->output_section->vma
11429 + input_section->output_offset
11430 + rel->r_offset);
11431
6cf9e9fe
NC		 11432 relocation >>= howto->rightshift;
11433 signed_check = relocation;
c19d1205
ZW		 11434
11435 if (r_type == R_ARM_THM_JUMP6)
11436 relocation = ((relocation & 0x0020) << 4) | ((relocation & 0x001f) << 3);
11437 else
11438 relocation &= howto->dst_mask;
51c5503b 11439 relocation |= (bfd_get_16 (input_bfd, hit_data) & (~ howto->dst_mask));
cedb70c5 11440
51c5503b
NC		 11441 bfd_put_16 (input_bfd, relocation, hit_data);
11442
11443 /* Assumes two's complement. */
11444 if (signed_check > reloc_signed_max || signed_check < reloc_signed_min)
11445 return bfd_reloc_overflow;
11446
11447 return bfd_reloc_ok;
11448 }
cedb70c5 11449
8375c36b
PB		 11450 case R_ARM_ALU_PCREL7_0:
11451 case R_ARM_ALU_PCREL15_8:
11452 case R_ARM_ALU_PCREL23_15:
11453 {
11454 bfd_vma insn;
11455 bfd_vma relocation;
11456
11457 insn = bfd_get_32 (input_bfd, hit_data);
4e7fd91e
PB		 11458 if (globals->use_rel)
11459 {
11460 /* Extract the addend. */
11461 addend = (insn & 0xff) << ((insn & 0xf00) >> 7);
11462 signed_addend = addend;
11463 }
8375c36b
PB		 11464 relocation = value + signed_addend;
11465
11466 relocation -= (input_section->output_section->vma
11467 + input_section->output_offset
11468 + rel->r_offset);
11469 insn = (insn & ~0xfff)
11470 | ((howto->bitpos << 7) & 0xf00)
11471 | ((relocation >> howto->bitpos) & 0xff);
11472 bfd_put_32 (input_bfd, value, hit_data);
11473 }
11474 return bfd_reloc_ok;
11475
252b5132
RH		 11476 case R_ARM_GNU_VTINHERIT:
11477 case R_ARM_GNU_VTENTRY:
11478 return bfd_reloc_ok;
11479
c19d1205 11480 case R_ARM_GOTOFF32:
252b5132 11481 /* Relocation is relative to the start of the
99059e56 11482 global offset table. */
252b5132
RH		 11483
11484 BFD_ASSERT (sgot != NULL);
11485 if (sgot == NULL)
99059e56 11486 return bfd_reloc_notsupported;
9a5aca8c 11487
cedb70c5 11488 /* If we are addressing a Thumb function, we need to adjust the
ee29b9fb
RE		 11489 address by one, so that attempts to call the function pointer will
11490 correctly interpret it as Thumb code. */
35fc36a8 11491 if (branch_type == ST_BRANCH_TO_THUMB)
ee29b9fb
RE		 11492 value += 1;
11493
252b5132 11494 /* Note that sgot->output_offset is not involved in this
99059e56
RM		 11495 calculation. We always want the start of .got. If we
11496 define _GLOBAL_OFFSET_TABLE in a different way, as is
11497 permitted by the ABI, we might have to change this
11498 calculation. */
252b5132 11499 value -= sgot->output_section->vma;
f21f3fe0 11500 return _bfd_final_link_relocate (howto, input_bfd, input_section,
99e4ae17 11501 contents, rel->r_offset, value,
00a97672 11502 rel->r_addend);
252b5132
RH		 11503
11504 case R_ARM_GOTPC:
a7c10850 11505 /* Use global offset table as symbol value. */
252b5132 11506 BFD_ASSERT (sgot != NULL);
f21f3fe0 11507
252b5132 11508 if (sgot == NULL)
99059e56 11509 return bfd_reloc_notsupported;
252b5132 11510
0945cdfd 11511 *unresolved_reloc_p = FALSE;
252b5132 11512 value = sgot->output_section->vma;
f21f3fe0 11513 return _bfd_final_link_relocate (howto, input_bfd, input_section,
99e4ae17 11514 contents, rel->r_offset, value,
00a97672 11515 rel->r_addend);
f21f3fe0 11516
252b5132 11517 case R_ARM_GOT32:
eb043451 11518 case R_ARM_GOT_PREL:
252b5132 11519 /* Relocation is to the entry for this symbol in the
99059e56 11520 global offset table. */
252b5132
RH		 11521 if (sgot == NULL)
11522 return bfd_reloc_notsupported;
f21f3fe0 11523
34e77a92
RS		 11524 if (dynreloc_st_type == STT_GNU_IFUNC
11525 && plt_offset != (bfd_vma) -1
11526 && (h == NULL || SYMBOL_REFERENCES_LOCAL (info, h)))
11527 {
11528 /* We have a relocation against a locally-binding STT_GNU_IFUNC
11529 symbol, and the relocation resolves directly to the runtime
11530 target rather than to the .iplt entry. This means that any
11531 .got entry would be the same value as the .igot.plt entry,
11532 so there's no point creating both. */
11533 sgot = globals->root.igotplt;
11534 value = sgot->output_offset + gotplt_offset;
11535 }
11536 else if (h != NULL)
252b5132
RH		 11537 {
11538 bfd_vma off;
f21f3fe0 11539
252b5132
RH		 11540 off = h->got.offset;
11541 BFD_ASSERT (off != (bfd_vma) -1);
b436d854 11542 if ((off & 1) != 0)
252b5132 11543 {
b436d854
RS		 11544 /* We have already processsed one GOT relocation against
11545 this symbol. */
11546 off &= ~1;
11547 if (globals->root.dynamic_sections_created
11548 && !SYMBOL_REFERENCES_LOCAL (info, h))
11549 *unresolved_reloc_p = FALSE;
11550 }
11551 else
11552 {
11553 Elf_Internal_Rela outrel;
e8b09b87 11554 int isrofixup = 0;
b436d854 11555
e8b09b87
CL		 11556 if (((h->dynindx != -1) || globals->fdpic_p)
11557 && !SYMBOL_REFERENCES_LOCAL (info, h))
b436d854
RS		 11558 {
11559 /* If the symbol doesn't resolve locally in a static
11560 object, we have an undefined reference. If the
11561 symbol doesn't resolve locally in a dynamic object,
11562 it should be resolved by the dynamic linker. */
11563 if (globals->root.dynamic_sections_created)
11564 {
11565 outrel.r_info = ELF32_R_INFO (h->dynindx, R_ARM_GLOB_DAT);
11566 *unresolved_reloc_p = FALSE;
11567 }
11568 else
11569 outrel.r_info = 0;
11570 outrel.r_addend = 0;
11571 }
252b5132
RH		 11572 else
11573 {
34e77a92 11574 if (dynreloc_st_type == STT_GNU_IFUNC)
99059e56 11575 outrel.r_info = ELF32_R_INFO (0, R_ARM_IRELATIVE);
5025eb7c
AO		 11576 else if (bfd_link_pic (info)
11577 && (ELF_ST_VISIBILITY (h->other) == STV_DEFAULT
11578 || h->root.type != bfd_link_hash_undefweak))
99059e56
RM		 11579 outrel.r_info = ELF32_R_INFO (0, R_ARM_RELATIVE);
11580 else
2376f038
EB		 11581 {
11582 outrel.r_info = 0;
11583 if (globals->fdpic_p)
11584 isrofixup = 1;
11585 }
34e77a92 11586 outrel.r_addend = dynreloc_value;
b436d854 11587 }
ee29b9fb 11588
b436d854
RS		 11589 /* The GOT entry is initialized to zero by default.
11590 See if we should install a different value. */
11591 if (outrel.r_addend != 0
2376f038 11592 && (globals->use_rel || outrel.r_info == 0))
b436d854
RS		 11593 {
11594 bfd_put_32 (output_bfd, outrel.r_addend,
11595 sgot->contents + off);
11596 outrel.r_addend = 0;
252b5132 11597 }
f21f3fe0 11598
2376f038
EB		 11599 if (isrofixup)
11600 arm_elf_add_rofixup (output_bfd,
11601 elf32_arm_hash_table(info)->srofixup,
11602 sgot->output_section->vma
11603 + sgot->output_offset + off);
11604
11605 else if (outrel.r_info != 0)
b436d854
RS		 11606 {
11607 outrel.r_offset = (sgot->output_section->vma
11608 + sgot->output_offset
11609 + off);
11610 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
11611 }
2376f038 11612
b436d854
RS		 11613 h->got.offset |= 1;
11614 }
252b5132
RH		 11615 value = sgot->output_offset + off;
11616 }
11617 else
11618 {
11619 bfd_vma off;
f21f3fe0 11620
5025eb7c
AO		 11621 BFD_ASSERT (local_got_offsets != NULL
11622 && local_got_offsets[r_symndx] != (bfd_vma) -1);
f21f3fe0 11623
252b5132 11624 off = local_got_offsets[r_symndx];
f21f3fe0 11625
252b5132
RH		 11626 /* The offset must always be a multiple of 4. We use the
11627 least significant bit to record whether we have already
9b485d32 11628 generated the necessary reloc. */
252b5132
RH		 11629 if ((off & 1) != 0)
11630 off &= ~1;
11631 else
11632 {
2376f038
EB		 11633 Elf_Internal_Rela outrel;
11634 int isrofixup = 0;
f21f3fe0 11635
2376f038
EB		 11636 if (dynreloc_st_type == STT_GNU_IFUNC)
11637 outrel.r_info = ELF32_R_INFO (0, R_ARM_IRELATIVE);
11638 else if (bfd_link_pic (info))
11639 outrel.r_info = ELF32_R_INFO (0, R_ARM_RELATIVE);
11640 else
252b5132 11641 {
2376f038
EB		 11642 outrel.r_info = 0;
11643 if (globals->fdpic_p)
11644 isrofixup = 1;
11645 }
11646
11647 /* The GOT entry is initialized to zero by default.
11648 See if we should install a different value. */
11649 if (globals->use_rel || outrel.r_info == 0)
11650 bfd_put_32 (output_bfd, dynreloc_value, sgot->contents + off);
11651
11652 if (isrofixup)
11653 arm_elf_add_rofixup (output_bfd,
11654 globals->srofixup,
11655 sgot->output_section->vma
11656 + sgot->output_offset + off);
f21f3fe0 11657
2376f038
EB		 11658 else if (outrel.r_info != 0)
11659 {
34e77a92 11660 outrel.r_addend = addend + dynreloc_value;
252b5132 11661 outrel.r_offset = (sgot->output_section->vma
f21f3fe0 11662 + sgot->output_offset
252b5132 11663 + off);
47beaa6a 11664 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
252b5132 11665 }
f21f3fe0 11666
252b5132
RH		 11667 local_got_offsets[r_symndx] |= 1;
11668 }
f21f3fe0 11669
252b5132
RH		 11670 value = sgot->output_offset + off;
11671 }
eb043451
PB		 11672 if (r_type != R_ARM_GOT32)
11673 value += sgot->output_section->vma;
9a5aca8c 11674
f21f3fe0 11675 return _bfd_final_link_relocate (howto, input_bfd, input_section,
99e4ae17 11676 contents, rel->r_offset, value,
00a97672 11677 rel->r_addend);
f21f3fe0 11678
ba93b8ac
DJ		 11679 case R_ARM_TLS_LDO32:
11680 value = value - dtpoff_base (info);
11681
11682 return _bfd_final_link_relocate (howto, input_bfd, input_section,
00a97672
RS		 11683 contents, rel->r_offset, value,
11684 rel->r_addend);
ba93b8ac
DJ		 11685
11686 case R_ARM_TLS_LDM32:
5c5a4843 11687 case R_ARM_TLS_LDM32_FDPIC:
ba93b8ac
DJ		 11688 {
11689 bfd_vma off;
11690
362d30a1 11691 if (sgot == NULL)
ba93b8ac
DJ		 11692 abort ();
11693
11694 off = globals->tls_ldm_got.offset;
11695
11696 if ((off & 1) != 0)
11697 off &= ~1;
11698 else
11699 {
11700 /* If we don't know the module number, create a relocation
11701 for it. */
0e1862bb 11702 if (bfd_link_pic (info))
ba93b8ac
DJ		 11703 {
11704 Elf_Internal_Rela outrel;
ba93b8ac 11705
362d30a1 11706 if (srelgot == NULL)
ba93b8ac
DJ		 11707 abort ();
11708
00a97672 11709 outrel.r_addend = 0;
362d30a1
RS		 11710 outrel.r_offset = (sgot->output_section->vma
11711 + sgot->output_offset + off);
ba93b8ac
DJ		 11712 outrel.r_info = ELF32_R_INFO (0, R_ARM_TLS_DTPMOD32);
11713
00a97672
RS		 11714 if (globals->use_rel)
11715 bfd_put_32 (output_bfd, outrel.r_addend,
362d30a1 11716 sgot->contents + off);
ba93b8ac 11717
47beaa6a 11718 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
ba93b8ac
DJ		 11719 }
11720 else
362d30a1 11721 bfd_put_32 (output_bfd, 1, sgot->contents + off);
ba93b8ac
DJ		 11722
11723 globals->tls_ldm_got.offset |= 1;
11724 }
11725
5c5a4843 11726 if (r_type == R_ARM_TLS_LDM32_FDPIC)
e8b09b87
CL		 11727 {
11728 bfd_put_32(output_bfd,
11729 globals->root.sgot->output_offset + off,
11730 contents + rel->r_offset);
11731
11732 return bfd_reloc_ok;
11733 }
11734 else
11735 {
11736 value = sgot->output_section->vma + sgot->output_offset + off
11737 - (input_section->output_section->vma
11738 + input_section->output_offset + rel->r_offset);
ba93b8ac 11739
e8b09b87
CL		 11740 return _bfd_final_link_relocate (howto, input_bfd, input_section,
11741 contents, rel->r_offset, value,
11742 rel->r_addend);
11743 }
ba93b8ac
DJ		 11744 }
11745
0855e32b
NS		 11746 case R_ARM_TLS_CALL:
11747 case R_ARM_THM_TLS_CALL:
ba93b8ac 11748 case R_ARM_TLS_GD32:
5c5a4843 11749 case R_ARM_TLS_GD32_FDPIC:
ba93b8ac 11750 case R_ARM_TLS_IE32:
5c5a4843 11751 case R_ARM_TLS_IE32_FDPIC:
0855e32b
NS		 11752 case R_ARM_TLS_GOTDESC:
11753 case R_ARM_TLS_DESCSEQ:
11754 case R_ARM_THM_TLS_DESCSEQ:
ba93b8ac 11755 {
0855e32b
NS		 11756 bfd_vma off, offplt;
11757 int indx = 0;
ba93b8ac
DJ		 11758 char tls_type;
11759
0855e32b 11760 BFD_ASSERT (sgot != NULL);
ba93b8ac 11761
ba93b8ac
DJ		 11762 if (h != NULL)
11763 {
11764 bfd_boolean dyn;
11765 dyn = globals->root.dynamic_sections_created;
0e1862bb
L		 11766 if (WILL_CALL_FINISH_DYNAMIC_SYMBOL (dyn,
11767 bfd_link_pic (info),
11768 h)
11769 && (!bfd_link_pic (info)
ba93b8ac
DJ		 11770 || !SYMBOL_REFERENCES_LOCAL (info, h)))
11771 {
11772 *unresolved_reloc_p = FALSE;
11773 indx = h->dynindx;
11774 }
11775 off = h->got.offset;
0855e32b 11776 offplt = elf32_arm_hash_entry (h)->tlsdesc_got;
ba93b8ac
DJ		 11777 tls_type = ((struct elf32_arm_link_hash_entry *) h)->tls_type;
11778 }
11779 else
11780 {
0855e32b 11781 BFD_ASSERT (local_got_offsets != NULL);
ba93b8ac 11782 off = local_got_offsets[r_symndx];
0855e32b 11783 offplt = local_tlsdesc_gotents[r_symndx];
ba93b8ac
DJ		 11784 tls_type = elf32_arm_local_got_tls_type (input_bfd)[r_symndx];
11785 }
11786
0855e32b 11787 /* Linker relaxations happens from one of the
b38cadfb 11788 R_ARM_{GOTDESC,CALL,DESCSEQ} relocations to IE or LE. */
0855e32b 11789 if (ELF32_R_TYPE(rel->r_info) != r_type)
b38cadfb 11790 tls_type = GOT_TLS_IE;
0855e32b
NS		 11791
11792 BFD_ASSERT (tls_type != GOT_UNKNOWN);
ba93b8ac
DJ		 11793
11794 if ((off & 1) != 0)
11795 off &= ~1;
11796 else
11797 {
11798 bfd_boolean need_relocs = FALSE;
11799 Elf_Internal_Rela outrel;
ba93b8ac
DJ		 11800 int cur_off = off;
11801
11802 /* The GOT entries have not been initialized yet. Do it
11803 now, and emit any relocations. If both an IE GOT and a
11804 GD GOT are necessary, we emit the GD first. */
11805
0e1862bb 11806 if ((bfd_link_pic (info) || indx != 0)
ba93b8ac 11807 && (h == NULL
95b03e4a
L		 11808 || (ELF_ST_VISIBILITY (h->other) == STV_DEFAULT
11809 && !resolved_to_zero)
ba93b8ac
DJ		 11810 || h->root.type != bfd_link_hash_undefweak))
11811 {
11812 need_relocs = TRUE;
0855e32b 11813 BFD_ASSERT (srelgot != NULL);
ba93b8ac
DJ		 11814 }
11815
0855e32b
NS		 11816 if (tls_type & GOT_TLS_GDESC)
11817 {
47beaa6a
RS		 11818 bfd_byte *loc;
11819
0855e32b
NS		 11820 /* We should have relaxed, unless this is an undefined
11821 weak symbol. */
11822 BFD_ASSERT ((h && (h->root.type == bfd_link_hash_undefweak))
0e1862bb 11823 || bfd_link_pic (info));
0855e32b 11824 BFD_ASSERT (globals->sgotplt_jump_table_size + offplt + 8
99059e56 11825 <= globals->root.sgotplt->size);
0855e32b
NS		 11826
11827 outrel.r_addend = 0;
11828 outrel.r_offset = (globals->root.sgotplt->output_section->vma
11829 + globals->root.sgotplt->output_offset
11830 + offplt
11831 + globals->sgotplt_jump_table_size);
b38cadfb 11832
0855e32b
NS		 11833 outrel.r_info = ELF32_R_INFO (indx, R_ARM_TLS_DESC);
11834 sreloc = globals->root.srelplt;
11835 loc = sreloc->contents;
11836 loc += globals->next_tls_desc_index++ * RELOC_SIZE (globals);
11837 BFD_ASSERT (loc + RELOC_SIZE (globals)
99059e56 11838 <= sreloc->contents + sreloc->size);
0855e32b
NS		 11839
11840 SWAP_RELOC_OUT (globals) (output_bfd, &outrel, loc);
11841
11842 /* For globals, the first word in the relocation gets
11843 the relocation index and the top bit set, or zero,
11844 if we're binding now. For locals, it gets the
11845 symbol's offset in the tls section. */
99059e56 11846 bfd_put_32 (output_bfd,
0855e32b
NS		 11847 !h ? value - elf_hash_table (info)->tls_sec->vma
11848 : info->flags & DF_BIND_NOW ? 0
11849 : 0x80000000 | ELF32_R_SYM (outrel.r_info),
b38cadfb
NC		 11850 globals->root.sgotplt->contents + offplt
11851 + globals->sgotplt_jump_table_size);
11852
0855e32b 11853 /* Second word in the relocation is always zero. */
99059e56 11854 bfd_put_32 (output_bfd, 0,
b38cadfb
NC		 11855 globals->root.sgotplt->contents + offplt
11856 + globals->sgotplt_jump_table_size + 4);
0855e32b 11857 }
ba93b8ac
DJ		 11858 if (tls_type & GOT_TLS_GD)
11859 {
11860 if (need_relocs)
11861 {
00a97672 11862 outrel.r_addend = 0;
362d30a1
RS		 11863 outrel.r_offset = (sgot->output_section->vma
11864 + sgot->output_offset
00a97672 11865 + cur_off);
ba93b8ac 11866 outrel.r_info = ELF32_R_INFO (indx, R_ARM_TLS_DTPMOD32);
ba93b8ac 11867
00a97672
RS		 11868 if (globals->use_rel)
11869 bfd_put_32 (output_bfd, outrel.r_addend,
362d30a1 11870 sgot->contents + cur_off);
00a97672 11871
47beaa6a 11872 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
ba93b8ac
DJ		 11873
11874 if (indx == 0)
11875 bfd_put_32 (output_bfd, value - dtpoff_base (info),
362d30a1 11876 sgot->contents + cur_off + 4);
ba93b8ac
DJ		 11877 else
11878 {
00a97672 11879 outrel.r_addend = 0;
ba93b8ac
DJ		 11880 outrel.r_info = ELF32_R_INFO (indx,
11881 R_ARM_TLS_DTPOFF32);
11882 outrel.r_offset += 4;
00a97672
RS		 11883
11884 if (globals->use_rel)
11885 bfd_put_32 (output_bfd, outrel.r_addend,
362d30a1 11886 sgot->contents + cur_off + 4);
00a97672 11887
47beaa6a
RS		 11888 elf32_arm_add_dynreloc (output_bfd, info,
11889 srelgot, &outrel);
ba93b8ac
DJ		 11890 }
11891 }
11892 else
11893 {
11894 /* If we are not emitting relocations for a
11895 general dynamic reference, then we must be in a
11896 static link or an executable link with the
11897 symbol binding locally. Mark it as belonging
11898 to module 1, the executable. */
11899 bfd_put_32 (output_bfd, 1,
362d30a1 11900 sgot->contents + cur_off);
ba93b8ac 11901 bfd_put_32 (output_bfd, value - dtpoff_base (info),
362d30a1 11902 sgot->contents + cur_off + 4);
ba93b8ac
DJ		 11903 }
11904
11905 cur_off += 8;
11906 }
11907
11908 if (tls_type & GOT_TLS_IE)
11909 {
11910 if (need_relocs)
11911 {
00a97672
RS		 11912 if (indx == 0)
11913 outrel.r_addend = value - dtpoff_base (info);
11914 else
11915 outrel.r_addend = 0;
362d30a1
RS		 11916 outrel.r_offset = (sgot->output_section->vma
11917 + sgot->output_offset
ba93b8ac
DJ		 11918 + cur_off);
11919 outrel.r_info = ELF32_R_INFO (indx, R_ARM_TLS_TPOFF32);
11920
00a97672
RS		 11921 if (globals->use_rel)
11922 bfd_put_32 (output_bfd, outrel.r_addend,
362d30a1 11923 sgot->contents + cur_off);
ba93b8ac 11924
47beaa6a 11925 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
ba93b8ac
DJ		 11926 }
11927 else
11928 bfd_put_32 (output_bfd, tpoff (info, value),
362d30a1 11929 sgot->contents + cur_off);
ba93b8ac
DJ		 11930 cur_off += 4;
11931 }
11932
11933 if (h != NULL)
11934 h->got.offset |= 1;
11935 else
11936 local_got_offsets[r_symndx] |= 1;
11937 }
11938
5c5a4843 11939 if ((tls_type & GOT_TLS_GD) && r_type != R_ARM_TLS_GD32 && r_type != R_ARM_TLS_GD32_FDPIC)
ba93b8ac 11940 off += 8;
0855e32b
NS		 11941 else if (tls_type & GOT_TLS_GDESC)
11942 off = offplt;
11943
11944 if (ELF32_R_TYPE(rel->r_info) == R_ARM_TLS_CALL
11945 || ELF32_R_TYPE(rel->r_info) == R_ARM_THM_TLS_CALL)
11946 {
11947 bfd_signed_vma offset;
12352d3f
PB		 11948 /* TLS stubs are arm mode. The original symbol is a
11949 data object, so branch_type is bogus. */
11950 branch_type = ST_BRANCH_TO_ARM;
0855e32b 11951 enum elf32_arm_stub_type stub_type
34e77a92
RS		 11952 = arm_type_of_stub (info, input_section, rel,
11953 st_type, &branch_type,
0855e32b
NS		 11954 (struct elf32_arm_link_hash_entry *)h,
11955 globals->tls_trampoline, globals->root.splt,
11956 input_bfd, sym_name);
11957
11958 if (stub_type != arm_stub_none)
11959 {
11960 struct elf32_arm_stub_hash_entry *stub_entry
11961 = elf32_arm_get_stub_entry
11962 (input_section, globals->root.splt, 0, rel,
11963 globals, stub_type);
11964 offset = (stub_entry->stub_offset
11965 + stub_entry->stub_sec->output_offset
11966 + stub_entry->stub_sec->output_section->vma);
11967 }
11968 else
11969 offset = (globals->root.splt->output_section->vma
11970 + globals->root.splt->output_offset
11971 + globals->tls_trampoline);
11972
11973 if (ELF32_R_TYPE(rel->r_info) == R_ARM_TLS_CALL)
11974 {
11975 unsigned long inst;
b38cadfb
NC		 11976
11977 offset -= (input_section->output_section->vma
11978 + input_section->output_offset
11979 + rel->r_offset + 8);
0855e32b
NS		 11980
11981 inst = offset >> 2;
11982 inst &= 0x00ffffff;
11983 value = inst | (globals->use_blx ? 0xfa000000 : 0xeb000000);
11984 }
11985 else
11986 {
11987 /* Thumb blx encodes the offset in a complicated
11988 fashion. */
11989 unsigned upper_insn, lower_insn;
11990 unsigned neg;
11991
b38cadfb
NC		 11992 offset -= (input_section->output_section->vma
11993 + input_section->output_offset
0855e32b 11994 + rel->r_offset + 4);
b38cadfb 11995
12352d3f
PB		 11996 if (stub_type != arm_stub_none
11997 && arm_stub_is_thumb (stub_type))
11998 {
11999 lower_insn = 0xd000;
12000 }
12001 else
12002 {
12003 lower_insn = 0xc000;
6a631e86 12004 /* Round up the offset to a word boundary. */
12352d3f
PB		 12005 offset = (offset + 2) & ~2;
12006 }
12007
0855e32b
NS		 12008 neg = offset < 0;
12009 upper_insn = (0xf000
12010 | ((offset >> 12) & 0x3ff)
12011 | (neg << 10));
12352d3f 12012 lower_insn |= (((!((offset >> 23) & 1)) ^ neg) << 13)
0855e32b 12013 | (((!((offset >> 22) & 1)) ^ neg) << 11)
12352d3f 12014 | ((offset >> 1) & 0x7ff);
0855e32b
NS		 12015 bfd_put_16 (input_bfd, upper_insn, hit_data);
12016 bfd_put_16 (input_bfd, lower_insn, hit_data + 2);
12017 return bfd_reloc_ok;
12018 }
12019 }
12020 /* These relocations needs special care, as besides the fact
12021 they point somewhere in .gotplt, the addend must be
12022 adjusted accordingly depending on the type of instruction
6a631e86 12023 we refer to. */
0855e32b
NS		 12024 else if ((r_type == R_ARM_TLS_GOTDESC) && (tls_type & GOT_TLS_GDESC))
12025 {
12026 unsigned long data, insn;
12027 unsigned thumb;
b38cadfb 12028
0855e32b
NS		 12029 data = bfd_get_32 (input_bfd, hit_data);
12030 thumb = data & 1;
12031 data &= ~1u;
b38cadfb 12032
0855e32b
NS		 12033 if (thumb)
12034 {
12035 insn = bfd_get_16 (input_bfd, contents + rel->r_offset - data);
12036 if ((insn & 0xf000) == 0xf000 || (insn & 0xf800) == 0xe800)
12037 insn = (insn << 16)
12038 | bfd_get_16 (input_bfd,
12039 contents + rel->r_offset - data + 2);
12040 if ((insn & 0xf800c000) == 0xf000c000)
12041 /* bl/blx */
12042 value = -6;
12043 else if ((insn & 0xffffff00) == 0x4400)
12044 /* add */
12045 value = -5;
12046 else
12047 {
4eca0228 12048 _bfd_error_handler
695344c0 12049 /* xgettext:c-format */
2dcf00ce 12050 (_("%pB(%pA+%#" PRIx64 "): "
90b6238f 12051 "unexpected %s instruction '%#lx' "
2dcf00ce
AM		 12052 "referenced by TLS_GOTDESC"),
12053 input_bfd, input_section, (uint64_t) rel->r_offset,
90b6238f 12054 "Thumb", insn);
0855e32b
NS		 12055 return bfd_reloc_notsupported;
12056 }
12057 }
12058 else
12059 {
12060 insn = bfd_get_32 (input_bfd, contents + rel->r_offset - data);
12061
12062 switch (insn >> 24)
12063 {
12064 case 0xeb: /* bl */
12065 case 0xfa: /* blx */
12066 value = -4;
12067 break;
12068
12069 case 0xe0: /* add */
12070 value = -8;
12071 break;
b38cadfb 12072
0855e32b 12073 default:
4eca0228 12074 _bfd_error_handler
695344c0 12075 /* xgettext:c-format */
2dcf00ce 12076 (_("%pB(%pA+%#" PRIx64 "): "
90b6238f 12077 "unexpected %s instruction '%#lx' "
2dcf00ce
AM		 12078 "referenced by TLS_GOTDESC"),
12079 input_bfd, input_section, (uint64_t) rel->r_offset,
90b6238f 12080 "ARM", insn);
0855e32b
NS		 12081 return bfd_reloc_notsupported;
12082 }
12083 }
b38cadfb 12084
0855e32b
NS		 12085 value += ((globals->root.sgotplt->output_section->vma
12086 + globals->root.sgotplt->output_offset + off)
12087 - (input_section->output_section->vma
12088 + input_section->output_offset
12089 + rel->r_offset)
12090 + globals->sgotplt_jump_table_size);
12091 }
12092 else
12093 value = ((globals->root.sgot->output_section->vma
12094 + globals->root.sgot->output_offset + off)
12095 - (input_section->output_section->vma
12096 + input_section->output_offset + rel->r_offset));
ba93b8ac 12097
5c5a4843
CL		 12098 if (globals->fdpic_p && (r_type == R_ARM_TLS_GD32_FDPIC ||
12099 r_type == R_ARM_TLS_IE32_FDPIC))
e8b09b87
CL		 12100 {
12101 /* For FDPIC relocations, resolve to the offset of the GOT
12102 entry from the start of GOT. */
12103 bfd_put_32(output_bfd,
12104 globals->root.sgot->output_offset + off,
12105 contents + rel->r_offset);
12106
12107 return bfd_reloc_ok;
12108 }
12109 else
12110 {
12111 return _bfd_final_link_relocate (howto, input_bfd, input_section,
12112 contents, rel->r_offset, value,
12113 rel->r_addend);
12114 }
ba93b8ac
DJ		 12115 }
12116
12117 case R_ARM_TLS_LE32:
3cbc1e5e 12118 if (bfd_link_dll (info))
ba93b8ac 12119 {
4eca0228 12120 _bfd_error_handler
695344c0 12121 /* xgettext:c-format */
2dcf00ce
AM		 12122 (_("%pB(%pA+%#" PRIx64 "): %s relocation not permitted "
12123 "in shared object"),
12124 input_bfd, input_section, (uint64_t) rel->r_offset, howto->name);
46691134 12125 return bfd_reloc_notsupported;
ba93b8ac
DJ		 12126 }
12127 else
12128 value = tpoff (info, value);
906e58ca 12129
ba93b8ac 12130 return _bfd_final_link_relocate (howto, input_bfd, input_section,
00a97672
RS		 12131 contents, rel->r_offset, value,
12132 rel->r_addend);
ba93b8ac 12133
319850b4
JB		 12134 case R_ARM_V4BX:
12135 if (globals->fix_v4bx)
845b51d6
PB		 12136 {
12137 bfd_vma insn = bfd_get_32 (input_bfd, hit_data);
319850b4 12138
845b51d6
PB		 12139 /* Ensure that we have a BX instruction. */
12140 BFD_ASSERT ((insn & 0x0ffffff0) == 0x012fff10);
319850b4 12141
845b51d6
PB		 12142 if (globals->fix_v4bx == 2 && (insn & 0xf) != 0xf)
12143 {
12144 /* Branch to veneer. */
12145 bfd_vma glue_addr;
12146 glue_addr = elf32_arm_bx_glue (info, insn & 0xf);
12147 glue_addr -= input_section->output_section->vma
12148 + input_section->output_offset
12149 + rel->r_offset + 8;
12150 insn = (insn & 0xf0000000) | 0x0a000000
12151 | ((glue_addr >> 2) & 0x00ffffff);
12152 }
12153 else
12154 {
12155 /* Preserve Rm (lowest four bits) and the condition code
12156 (highest four bits). Other bits encode MOV PC,Rm. */
12157 insn = (insn & 0xf000000f) | 0x01a0f000;
12158 }
319850b4 12159
845b51d6
PB		 12160 bfd_put_32 (input_bfd, insn, hit_data);
12161 }
319850b4
JB		 12162 return bfd_reloc_ok;
12163
b6895b4f
PB		 12164 case R_ARM_MOVW_ABS_NC:
12165 case R_ARM_MOVT_ABS:
12166 case R_ARM_MOVW_PREL_NC:
12167 case R_ARM_MOVT_PREL:
92f5d02b
MS		 12168 /* Until we properly support segment-base-relative addressing then
12169 we assume the segment base to be zero, as for the group relocations.
12170 Thus R_ARM_MOVW_BREL_NC has the same semantics as R_ARM_MOVW_ABS_NC
12171 and R_ARM_MOVT_BREL has the same semantics as R_ARM_MOVT_ABS. */
12172 case R_ARM_MOVW_BREL_NC:
12173 case R_ARM_MOVW_BREL:
12174 case R_ARM_MOVT_BREL:
b6895b4f
PB		 12175 {
12176 bfd_vma insn = bfd_get_32 (input_bfd, hit_data);
12177
12178 if (globals->use_rel)
12179 {
12180 addend = ((insn >> 4) & 0xf000) | (insn & 0xfff);
39623e12 12181 signed_addend = (addend ^ 0x8000) - 0x8000;
b6895b4f 12182 }
92f5d02b 12183
b6895b4f 12184 value += signed_addend;
b6895b4f
PB		 12185
12186 if (r_type == R_ARM_MOVW_PREL_NC || r_type == R_ARM_MOVT_PREL)
12187 value -= (input_section->output_section->vma
12188 + input_section->output_offset + rel->r_offset);
12189
92f5d02b 12190 if (r_type == R_ARM_MOVW_BREL && value >= 0x10000)
99059e56 12191 return bfd_reloc_overflow;
92f5d02b 12192
35fc36a8 12193 if (branch_type == ST_BRANCH_TO_THUMB)
92f5d02b
MS		 12194 value |= 1;
12195
12196 if (r_type == R_ARM_MOVT_ABS || r_type == R_ARM_MOVT_PREL
99059e56 12197 || r_type == R_ARM_MOVT_BREL)
b6895b4f
PB		 12198 value >>= 16;
12199
12200 insn &= 0xfff0f000;
12201 insn |= value & 0xfff;
12202 insn |= (value & 0xf000) << 4;
12203 bfd_put_32 (input_bfd, insn, hit_data);
12204 }
12205 return bfd_reloc_ok;
12206
12207 case R_ARM_THM_MOVW_ABS_NC:
12208 case R_ARM_THM_MOVT_ABS:
12209 case R_ARM_THM_MOVW_PREL_NC:
12210 case R_ARM_THM_MOVT_PREL:
92f5d02b
MS		 12211 /* Until we properly support segment-base-relative addressing then
12212 we assume the segment base to be zero, as for the above relocations.
12213 Thus R_ARM_THM_MOVW_BREL_NC has the same semantics as
12214 R_ARM_THM_MOVW_ABS_NC and R_ARM_THM_MOVT_BREL has the same semantics
12215 as R_ARM_THM_MOVT_ABS. */
12216 case R_ARM_THM_MOVW_BREL_NC:
12217 case R_ARM_THM_MOVW_BREL:
12218 case R_ARM_THM_MOVT_BREL:
b6895b4f
PB		 12219 {
12220 bfd_vma insn;
906e58ca 12221
b6895b4f
PB		 12222 insn = bfd_get_16 (input_bfd, hit_data) << 16;
12223 insn |= bfd_get_16 (input_bfd, hit_data + 2);
12224
12225 if (globals->use_rel)
12226 {
12227 addend = ((insn >> 4) & 0xf000)
12228 | ((insn >> 15) & 0x0800)
12229 | ((insn >> 4) & 0x0700)
07d6d2b8 12230 | (insn & 0x00ff);
39623e12 12231 signed_addend = (addend ^ 0x8000) - 0x8000;
b6895b4f 12232 }
92f5d02b 12233
b6895b4f 12234 value += signed_addend;
b6895b4f
PB		 12235
12236 if (r_type == R_ARM_THM_MOVW_PREL_NC || r_type == R_ARM_THM_MOVT_PREL)
12237 value -= (input_section->output_section->vma
12238 + input_section->output_offset + rel->r_offset);
12239
92f5d02b 12240 if (r_type == R_ARM_THM_MOVW_BREL && value >= 0x10000)
99059e56 12241 return bfd_reloc_overflow;
92f5d02b 12242
35fc36a8 12243 if (branch_type == ST_BRANCH_TO_THUMB)
92f5d02b
MS		 12244 value |= 1;
12245
12246 if (r_type == R_ARM_THM_MOVT_ABS || r_type == R_ARM_THM_MOVT_PREL
99059e56 12247 || r_type == R_ARM_THM_MOVT_BREL)
b6895b4f
PB		 12248 value >>= 16;
12249
12250 insn &= 0xfbf08f00;
12251 insn |= (value & 0xf000) << 4;
12252 insn |= (value & 0x0800) << 15;
12253 insn |= (value & 0x0700) << 4;
12254 insn |= (value & 0x00ff);
12255
12256 bfd_put_16 (input_bfd, insn >> 16, hit_data);
12257 bfd_put_16 (input_bfd, insn & 0xffff, hit_data + 2);
12258 }
12259 return bfd_reloc_ok;
12260
4962c51a
MS		 12261 case R_ARM_ALU_PC_G0_NC:
12262 case R_ARM_ALU_PC_G1_NC:
12263 case R_ARM_ALU_PC_G0:
12264 case R_ARM_ALU_PC_G1:
12265 case R_ARM_ALU_PC_G2:
12266 case R_ARM_ALU_SB_G0_NC:
12267 case R_ARM_ALU_SB_G1_NC:
12268 case R_ARM_ALU_SB_G0:
12269 case R_ARM_ALU_SB_G1:
12270 case R_ARM_ALU_SB_G2:
12271 {
12272 bfd_vma insn = bfd_get_32 (input_bfd, hit_data);
99059e56 12273 bfd_vma pc = input_section->output_section->vma
4962c51a 12274 + input_section->output_offset + rel->r_offset;
31a91d61 12275 /* sb is the origin of the *segment* containing the symbol. */
62c34db3 12276 bfd_vma sb = sym_sec ? sym_sec->output_section->vma : 0;
99059e56
RM		 12277 bfd_vma residual;
12278 bfd_vma g_n;
4962c51a 12279 bfd_signed_vma signed_value;
99059e56
RM		 12280 int group = 0;
12281
12282 /* Determine which group of bits to select. */
12283 switch (r_type)
12284 {
12285 case R_ARM_ALU_PC_G0_NC:
12286 case R_ARM_ALU_PC_G0:
12287 case R_ARM_ALU_SB_G0_NC:
12288 case R_ARM_ALU_SB_G0:
12289 group = 0;
12290 break;
12291
12292 case R_ARM_ALU_PC_G1_NC:
12293 case R_ARM_ALU_PC_G1:
12294 case R_ARM_ALU_SB_G1_NC:
12295 case R_ARM_ALU_SB_G1:
12296 group = 1;
12297 break;
12298
12299 case R_ARM_ALU_PC_G2:
12300 case R_ARM_ALU_SB_G2:
12301 group = 2;
12302 break;
12303
12304 default:
12305 abort ();
12306 }
12307
12308 /* If REL, extract the addend from the insn. If RELA, it will
12309 have already been fetched for us. */
4962c51a 12310 if (globals->use_rel)
99059e56
RM		 12311 {
12312 int negative;
12313 bfd_vma constant = insn & 0xff;
12314 bfd_vma rotation = (insn & 0xf00) >> 8;
12315
12316 if (rotation == 0)
12317 signed_addend = constant;
12318 else
12319 {
12320 /* Compensate for the fact that in the instruction, the
12321 rotation is stored in multiples of 2 bits. */
12322 rotation *= 2;
12323
12324 /* Rotate "constant" right by "rotation" bits. */
12325 signed_addend = (constant >> rotation) |
12326 (constant << (8 * sizeof (bfd_vma) - rotation));
12327 }
12328
12329 /* Determine if the instruction is an ADD or a SUB.
12330 (For REL, this determines the sign of the addend.) */
12331 negative = identify_add_or_sub (insn);
12332 if (negative == 0)
12333 {
4eca0228 12334 _bfd_error_handler
695344c0 12335 /* xgettext:c-format */
90b6238f 12336 (_("%pB(%pA+%#" PRIx64 "): only ADD or SUB instructions "
2dcf00ce
AM		 12337 "are allowed for ALU group relocations"),
12338 input_bfd, input_section, (uint64_t) rel->r_offset);
99059e56
RM		 12339 return bfd_reloc_overflow;
12340 }
12341
12342 signed_addend *= negative;
12343 }
4962c51a
MS		 12344
12345 /* Compute the value (X) to go in the place. */
99059e56
RM		 12346 if (r_type == R_ARM_ALU_PC_G0_NC
12347 || r_type == R_ARM_ALU_PC_G1_NC
12348 || r_type == R_ARM_ALU_PC_G0
12349 || r_type == R_ARM_ALU_PC_G1
12350 || r_type == R_ARM_ALU_PC_G2)
12351 /* PC relative. */
12352 signed_value = value - pc + signed_addend;
12353 else
12354 /* Section base relative. */
12355 signed_value = value - sb + signed_addend;
12356
12357 /* If the target symbol is a Thumb function, then set the
12358 Thumb bit in the address. */
35fc36a8 12359 if (branch_type == ST_BRANCH_TO_THUMB)
4962c51a
MS		 12360 signed_value |= 1;
12361
99059e56
RM		 12362 /* Calculate the value of the relevant G_n, in encoded
12363 constant-with-rotation format. */
b6518b38
NC		 12364 g_n = calculate_group_reloc_mask (signed_value < 0 ? - signed_value : signed_value,
12365 group, &residual);
99059e56
RM		 12366
12367 /* Check for overflow if required. */
12368 if ((r_type == R_ARM_ALU_PC_G0
12369 || r_type == R_ARM_ALU_PC_G1
12370 || r_type == R_ARM_ALU_PC_G2
12371 || r_type == R_ARM_ALU_SB_G0
12372 || r_type == R_ARM_ALU_SB_G1
12373 || r_type == R_ARM_ALU_SB_G2) && residual != 0)
12374 {
4eca0228 12375 _bfd_error_handler
695344c0 12376 /* xgettext:c-format */
90b6238f 12377 (_("%pB(%pA+%#" PRIx64 "): overflow whilst "
2dcf00ce
AM		 12378 "splitting %#" PRIx64 " for group relocation %s"),
12379 input_bfd, input_section, (uint64_t) rel->r_offset,
12380 (uint64_t) (signed_value < 0 ? -signed_value : signed_value),
12381 howto->name);
99059e56
RM		 12382 return bfd_reloc_overflow;
12383 }
12384
12385 /* Mask out the value and the ADD/SUB part of the opcode; take care
12386 not to destroy the S bit. */
12387 insn &= 0xff1ff000;
12388
12389 /* Set the opcode according to whether the value to go in the
12390 place is negative. */
12391 if (signed_value < 0)
12392 insn |= 1 << 22;
12393 else
12394 insn |= 1 << 23;
12395
12396 /* Encode the offset. */
12397 insn |= g_n;
4962c51a
MS		 12398
12399 bfd_put_32 (input_bfd, insn, hit_data);
12400 }
12401 return bfd_reloc_ok;
12402
12403 case R_ARM_LDR_PC_G0:
12404 case R_ARM_LDR_PC_G1:
12405 case R_ARM_LDR_PC_G2:
12406 case R_ARM_LDR_SB_G0:
12407 case R_ARM_LDR_SB_G1:
12408 case R_ARM_LDR_SB_G2:
12409 {
12410 bfd_vma insn = bfd_get_32 (input_bfd, hit_data);
99059e56 12411 bfd_vma pc = input_section->output_section->vma
4962c51a 12412 + input_section->output_offset + rel->r_offset;
31a91d61 12413 /* sb is the origin of the *segment* containing the symbol. */
62c34db3 12414 bfd_vma sb = sym_sec ? sym_sec->output_section->vma : 0;
99059e56 12415 bfd_vma residual;
4962c51a 12416 bfd_signed_vma signed_value;
99059e56
RM		 12417 int group = 0;
12418
12419 /* Determine which groups of bits to calculate. */
12420 switch (r_type)
12421 {
12422 case R_ARM_LDR_PC_G0:
12423 case R_ARM_LDR_SB_G0:
12424 group = 0;
12425 break;
12426
12427 case R_ARM_LDR_PC_G1:
12428 case R_ARM_LDR_SB_G1:
12429 group = 1;
12430 break;
12431
12432 case R_ARM_LDR_PC_G2:
12433 case R_ARM_LDR_SB_G2:
12434 group = 2;
12435 break;
12436
12437 default:
12438 abort ();
12439 }
12440
12441 /* If REL, extract the addend from the insn. If RELA, it will
12442 have already been fetched for us. */
4962c51a 12443 if (globals->use_rel)
99059e56
RM		 12444 {
12445 int negative = (insn & (1 << 23)) ? 1 : -1;
12446 signed_addend = negative * (insn & 0xfff);
12447 }
4962c51a
MS		 12448
12449 /* Compute the value (X) to go in the place. */
99059e56
RM		 12450 if (r_type == R_ARM_LDR_PC_G0
12451 || r_type == R_ARM_LDR_PC_G1
12452 || r_type == R_ARM_LDR_PC_G2)
12453 /* PC relative. */
12454 signed_value = value - pc + signed_addend;
12455 else
12456 /* Section base relative. */
12457 signed_value = value - sb + signed_addend;
12458
12459 /* Calculate the value of the relevant G_{n-1} to obtain
12460 the residual at that stage. */
b6518b38
NC		 12461 calculate_group_reloc_mask (signed_value < 0 ? - signed_value : signed_value,
12462 group - 1, &residual);
99059e56
RM		 12463
12464 /* Check for overflow. */
12465 if (residual >= 0x1000)
12466 {
4eca0228 12467 _bfd_error_handler
695344c0 12468 /* xgettext:c-format */
90b6238f 12469 (_("%pB(%pA+%#" PRIx64 "): overflow whilst "
2dcf00ce
AM		 12470 "splitting %#" PRIx64 " for group relocation %s"),
12471 input_bfd, input_section, (uint64_t) rel->r_offset,
12472 (uint64_t) (signed_value < 0 ? -signed_value : signed_value),
12473 howto->name);
99059e56
RM		 12474 return bfd_reloc_overflow;
12475 }
12476
12477 /* Mask out the value and U bit. */
12478 insn &= 0xff7ff000;
12479
12480 /* Set the U bit if the value to go in the place is non-negative. */
12481 if (signed_value >= 0)
12482 insn |= 1 << 23;
12483
12484 /* Encode the offset. */
12485 insn |= residual;
4962c51a
MS		 12486
12487 bfd_put_32 (input_bfd, insn, hit_data);
12488 }
12489 return bfd_reloc_ok;
12490
12491 case R_ARM_LDRS_PC_G0:
12492 case R_ARM_LDRS_PC_G1:
12493 case R_ARM_LDRS_PC_G2:
12494 case R_ARM_LDRS_SB_G0:
12495 case R_ARM_LDRS_SB_G1:
12496 case R_ARM_LDRS_SB_G2:
12497 {
12498 bfd_vma insn = bfd_get_32 (input_bfd, hit_data);
99059e56 12499 bfd_vma pc = input_section->output_section->vma
4962c51a 12500 + input_section->output_offset + rel->r_offset;
31a91d61 12501 /* sb is the origin of the *segment* containing the symbol. */
62c34db3 12502 bfd_vma sb = sym_sec ? sym_sec->output_section->vma : 0;
99059e56 12503 bfd_vma residual;
4962c51a 12504 bfd_signed_vma signed_value;
99059e56
RM		 12505 int group = 0;
12506
12507 /* Determine which groups of bits to calculate. */
12508 switch (r_type)
12509 {
12510 case R_ARM_LDRS_PC_G0:
12511 case R_ARM_LDRS_SB_G0:
12512 group = 0;
12513 break;
12514
12515 case R_ARM_LDRS_PC_G1:
12516 case R_ARM_LDRS_SB_G1:
12517 group = 1;
12518 break;
12519
12520 case R_ARM_LDRS_PC_G2:
12521 case R_ARM_LDRS_SB_G2:
12522 group = 2;
12523 break;
12524
12525 default:
12526 abort ();
12527 }
12528
12529 /* If REL, extract the addend from the insn. If RELA, it will
12530 have already been fetched for us. */
4962c51a 12531 if (globals->use_rel)
99059e56
RM		 12532 {
12533 int negative = (insn & (1 << 23)) ? 1 : -1;
12534 signed_addend = negative * (((insn & 0xf00) >> 4) + (insn & 0xf));
12535 }
4962c51a
MS		 12536
12537 /* Compute the value (X) to go in the place. */
99059e56
RM		 12538 if (r_type == R_ARM_LDRS_PC_G0
12539 || r_type == R_ARM_LDRS_PC_G1
12540 || r_type == R_ARM_LDRS_PC_G2)
12541 /* PC relative. */
12542 signed_value = value - pc + signed_addend;
12543 else
12544 /* Section base relative. */
12545 signed_value = value - sb + signed_addend;
12546
12547 /* Calculate the value of the relevant G_{n-1} to obtain
12548 the residual at that stage. */
b6518b38
NC		 12549 calculate_group_reloc_mask (signed_value < 0 ? - signed_value : signed_value,
12550 group - 1, &residual);
99059e56
RM		 12551
12552 /* Check for overflow. */
12553 if (residual >= 0x100)
12554 {
4eca0228 12555 _bfd_error_handler
695344c0 12556 /* xgettext:c-format */
90b6238f 12557 (_("%pB(%pA+%#" PRIx64 "): overflow whilst "
2dcf00ce
AM		 12558 "splitting %#" PRIx64 " for group relocation %s"),
12559 input_bfd, input_section, (uint64_t) rel->r_offset,
12560 (uint64_t) (signed_value < 0 ? -signed_value : signed_value),
12561 howto->name);
99059e56
RM		 12562 return bfd_reloc_overflow;
12563 }
12564
12565 /* Mask out the value and U bit. */
12566 insn &= 0xff7ff0f0;
12567
12568 /* Set the U bit if the value to go in the place is non-negative. */
12569 if (signed_value >= 0)
12570 insn |= 1 << 23;
12571
12572 /* Encode the offset. */
12573 insn |= ((residual & 0xf0) << 4) | (residual & 0xf);
4962c51a
MS		 12574
12575 bfd_put_32 (input_bfd, insn, hit_data);
12576 }
12577 return bfd_reloc_ok;
12578
12579 case R_ARM_LDC_PC_G0:
12580 case R_ARM_LDC_PC_G1:
12581 case R_ARM_LDC_PC_G2:
12582 case R_ARM_LDC_SB_G0:
12583 case R_ARM_LDC_SB_G1:
12584 case R_ARM_LDC_SB_G2:
12585 {
12586 bfd_vma insn = bfd_get_32 (input_bfd, hit_data);
99059e56 12587 bfd_vma pc = input_section->output_section->vma
4962c51a 12588 + input_section->output_offset + rel->r_offset;
31a91d61 12589 /* sb is the origin of the *segment* containing the symbol. */
62c34db3 12590 bfd_vma sb = sym_sec ? sym_sec->output_section->vma : 0;
99059e56 12591 bfd_vma residual;
4962c51a 12592 bfd_signed_vma signed_value;
99059e56
RM		 12593 int group = 0;
12594
12595 /* Determine which groups of bits to calculate. */
12596 switch (r_type)
12597 {
12598 case R_ARM_LDC_PC_G0:
12599 case R_ARM_LDC_SB_G0:
12600 group = 0;
12601 break;
12602
12603 case R_ARM_LDC_PC_G1:
12604 case R_ARM_LDC_SB_G1:
12605 group = 1;
12606 break;
12607
12608 case R_ARM_LDC_PC_G2:
12609 case R_ARM_LDC_SB_G2:
12610 group = 2;
12611 break;
12612
12613 default:
12614 abort ();
12615 }
12616
12617 /* If REL, extract the addend from the insn. If RELA, it will
12618 have already been fetched for us. */
4962c51a 12619 if (globals->use_rel)
99059e56
RM		 12620 {
12621 int negative = (insn & (1 << 23)) ? 1 : -1;
12622 signed_addend = negative * ((insn & 0xff) << 2);
12623 }
4962c51a
MS		 12624
12625 /* Compute the value (X) to go in the place. */
99059e56
RM		 12626 if (r_type == R_ARM_LDC_PC_G0
12627 || r_type == R_ARM_LDC_PC_G1
12628 || r_type == R_ARM_LDC_PC_G2)
12629 /* PC relative. */
12630 signed_value = value - pc + signed_addend;
12631 else
12632 /* Section base relative. */
12633 signed_value = value - sb + signed_addend;
12634
12635 /* Calculate the value of the relevant G_{n-1} to obtain
12636 the residual at that stage. */
b6518b38
NC		 12637 calculate_group_reloc_mask (signed_value < 0 ? - signed_value : signed_value,
12638 group - 1, &residual);
99059e56
RM		 12639
12640 /* Check for overflow. (The absolute value to go in the place must be
12641 divisible by four and, after having been divided by four, must
12642 fit in eight bits.) */
12643 if ((residual & 0x3) != 0 || residual >= 0x400)
12644 {
4eca0228 12645 _bfd_error_handler
695344c0 12646 /* xgettext:c-format */
90b6238f 12647 (_("%pB(%pA+%#" PRIx64 "): overflow whilst "
2dcf00ce
AM		 12648 "splitting %#" PRIx64 " for group relocation %s"),
12649 input_bfd, input_section, (uint64_t) rel->r_offset,
12650 (uint64_t) (signed_value < 0 ? -signed_value : signed_value),
12651 howto->name);
99059e56
RM		 12652 return bfd_reloc_overflow;
12653 }
12654
12655 /* Mask out the value and U bit. */
12656 insn &= 0xff7fff00;
12657
12658 /* Set the U bit if the value to go in the place is non-negative. */
12659 if (signed_value >= 0)
12660 insn |= 1 << 23;
12661
12662 /* Encode the offset. */
12663 insn |= residual >> 2;
4962c51a
MS		 12664
12665 bfd_put_32 (input_bfd, insn, hit_data);
12666 }
12667 return bfd_reloc_ok;
12668
72d98d16
MG		 12669 case R_ARM_THM_ALU_ABS_G0_NC:
12670 case R_ARM_THM_ALU_ABS_G1_NC:
12671 case R_ARM_THM_ALU_ABS_G2_NC:
12672 case R_ARM_THM_ALU_ABS_G3_NC:
12673 {
12674 const int shift_array[4] = {0, 8, 16, 24};
12675 bfd_vma insn = bfd_get_16 (input_bfd, hit_data);
12676 bfd_vma addr = value;
12677 int shift = shift_array[r_type - R_ARM_THM_ALU_ABS_G0_NC];
12678
12679 /* Compute address. */
12680 if (globals->use_rel)
12681 signed_addend = insn & 0xff;
12682 addr += signed_addend;
12683 if (branch_type == ST_BRANCH_TO_THUMB)
12684 addr |= 1;
12685 /* Clean imm8 insn. */
12686 insn &= 0xff00;
12687 /* And update with correct part of address. */
12688 insn |= (addr >> shift) & 0xff;
12689 /* Update insn. */
12690 bfd_put_16 (input_bfd, insn, hit_data);
12691 }
12692
12693 *unresolved_reloc_p = FALSE;
12694 return bfd_reloc_ok;
12695
e8b09b87
CL		 12696 case R_ARM_GOTOFFFUNCDESC:
12697 {
4b24dd1a 12698 if (h == NULL)
e8b09b87
CL		 12699 {
12700 struct fdpic_local *local_fdpic_cnts = elf32_arm_local_fdpic_cnts(input_bfd);
12701 int dynindx = elf_section_data (sym_sec->output_section)->dynindx;
12702 int offset = local_fdpic_cnts[r_symndx].funcdesc_offset & ~1;
12703 bfd_vma addr = dynreloc_value - sym_sec->output_section->vma;
12704 bfd_vma seg = -1;
12705
12706 if (bfd_link_pic(info) && dynindx == 0)
12707 abort();
12708
12709 /* Resolve relocation. */
12710 bfd_put_32(output_bfd, (offset + sgot->output_offset)
12711 , contents + rel->r_offset);
12712 /* Emit R_ARM_FUNCDESC_VALUE or two fixups on funcdesc if
12713 not done yet. */
12714 arm_elf_fill_funcdesc(output_bfd, info,
12715 &local_fdpic_cnts[r_symndx].funcdesc_offset,
12716 dynindx, offset, addr, dynreloc_value, seg);
12717 }
12718 else
12719 {
12720 int dynindx;
12721 int offset = eh->fdpic_cnts.funcdesc_offset & ~1;
12722 bfd_vma addr;
12723 bfd_vma seg = -1;
12724
12725 /* For static binaries, sym_sec can be null. */
12726 if (sym_sec)
12727 {
12728 dynindx = elf_section_data (sym_sec->output_section)->dynindx;
12729 addr = dynreloc_value - sym_sec->output_section->vma;
12730 }
12731 else
12732 {
12733 dynindx = 0;
12734 addr = 0;
12735 }
12736
12737 if (bfd_link_pic(info) && dynindx == 0)
12738 abort();
12739
12740 /* This case cannot occur since funcdesc is allocated by
12741 the dynamic loader so we cannot resolve the relocation. */
12742 if (h->dynindx != -1)
12743 abort();
12744
12745 /* Resolve relocation. */
12746 bfd_put_32(output_bfd, (offset + sgot->output_offset),
12747 contents + rel->r_offset);
12748 /* Emit R_ARM_FUNCDESC_VALUE on funcdesc if not done yet. */
12749 arm_elf_fill_funcdesc(output_bfd, info,
12750 &eh->fdpic_cnts.funcdesc_offset,
12751 dynindx, offset, addr, dynreloc_value, seg);
12752 }
12753 }
12754 *unresolved_reloc_p = FALSE;
12755 return bfd_reloc_ok;
12756
12757 case R_ARM_GOTFUNCDESC:
12758 {
4b24dd1a 12759 if (h != NULL)
e8b09b87
CL		 12760 {
12761 Elf_Internal_Rela outrel;
12762
12763 /* Resolve relocation. */
12764 bfd_put_32(output_bfd, ((eh->fdpic_cnts.gotfuncdesc_offset & ~1)
12765 + sgot->output_offset),
12766 contents + rel->r_offset);
12767 /* Add funcdesc and associated R_ARM_FUNCDESC_VALUE. */
12768 if(h->dynindx == -1)
12769 {
12770 int dynindx;
12771 int offset = eh->fdpic_cnts.funcdesc_offset & ~1;
12772 bfd_vma addr;
12773 bfd_vma seg = -1;
12774
12775 /* For static binaries sym_sec can be null. */
12776 if (sym_sec)
12777 {
12778 dynindx = elf_section_data (sym_sec->output_section)->dynindx;
12779 addr = dynreloc_value - sym_sec->output_section->vma;
12780 }
12781 else
12782 {
12783 dynindx = 0;
12784 addr = 0;
12785 }
12786
12787 /* Emit R_ARM_FUNCDESC_VALUE on funcdesc if not done yet. */
12788 arm_elf_fill_funcdesc(output_bfd, info,
12789 &eh->fdpic_cnts.funcdesc_offset,
12790 dynindx, offset, addr, dynreloc_value, seg);
12791 }
12792
12793 /* Add a dynamic relocation on GOT entry if not already done. */
12794 if ((eh->fdpic_cnts.gotfuncdesc_offset & 1) == 0)
12795 {
12796 if (h->dynindx == -1)
12797 {
12798 outrel.r_info = ELF32_R_INFO (0, R_ARM_RELATIVE);
12799 if (h->root.type == bfd_link_hash_undefweak)
12800 bfd_put_32(output_bfd, 0, sgot->contents
12801 + (eh->fdpic_cnts.gotfuncdesc_offset & ~1));
12802 else
12803 bfd_put_32(output_bfd, sgot->output_section->vma
12804 + sgot->output_offset
12805 + (eh->fdpic_cnts.funcdesc_offset & ~1),
12806 sgot->contents
12807 + (eh->fdpic_cnts.gotfuncdesc_offset & ~1));
12808 }
12809 else
12810 {
12811 outrel.r_info = ELF32_R_INFO (h->dynindx, R_ARM_FUNCDESC);
12812 }
12813 outrel.r_offset = sgot->output_section->vma
12814 + sgot->output_offset
12815 + (eh->fdpic_cnts.gotfuncdesc_offset & ~1);
12816 outrel.r_addend = 0;
12817 if (h->dynindx == -1 && !bfd_link_pic(info))
12818 if (h->root.type == bfd_link_hash_undefweak)
4b24dd1a 12819 arm_elf_add_rofixup(output_bfd, globals->srofixup, -1);
e8b09b87 12820 else
4b24dd1a
AM		 12821 arm_elf_add_rofixup(output_bfd, globals->srofixup,
12822 outrel.r_offset);
e8b09b87
CL		 12823 else
12824 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
12825 eh->fdpic_cnts.gotfuncdesc_offset |= 1;
12826 }
12827 }
12828 else
12829 {
12830 /* Such relocation on static function should not have been
12831 emitted by the compiler. */
12832 abort();
12833 }
12834 }
12835 *unresolved_reloc_p = FALSE;
12836 return bfd_reloc_ok;
12837
12838 case R_ARM_FUNCDESC:
12839 {
4b24dd1a 12840 if (h == NULL)
e8b09b87
CL		 12841 {
12842 struct fdpic_local *local_fdpic_cnts = elf32_arm_local_fdpic_cnts(input_bfd);
12843 Elf_Internal_Rela outrel;
12844 int dynindx = elf_section_data (sym_sec->output_section)->dynindx;
12845 int offset = local_fdpic_cnts[r_symndx].funcdesc_offset & ~1;
12846 bfd_vma addr = dynreloc_value - sym_sec->output_section->vma;
12847 bfd_vma seg = -1;
12848
12849 if (bfd_link_pic(info) && dynindx == 0)
12850 abort();
12851
12852 /* Replace static FUNCDESC relocation with a
12853 R_ARM_RELATIVE dynamic relocation or with a rofixup for
12854 executable. */
12855 outrel.r_info = ELF32_R_INFO (0, R_ARM_RELATIVE);
12856 outrel.r_offset = input_section->output_section->vma
12857 + input_section->output_offset + rel->r_offset;
12858 outrel.r_addend = 0;
12859 if (bfd_link_pic(info))
12860 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
12861 else
12862 arm_elf_add_rofixup(output_bfd, globals->srofixup, outrel.r_offset);
12863
12864 bfd_put_32 (input_bfd, sgot->output_section->vma
12865 + sgot->output_offset + offset, hit_data);
12866
12867 /* Emit R_ARM_FUNCDESC_VALUE on funcdesc if not done yet. */
12868 arm_elf_fill_funcdesc(output_bfd, info,
12869 &local_fdpic_cnts[r_symndx].funcdesc_offset,
12870 dynindx, offset, addr, dynreloc_value, seg);
12871 }
12872 else
12873 {
12874 if (h->dynindx == -1)
12875 {
12876 int dynindx;
12877 int offset = eh->fdpic_cnts.funcdesc_offset & ~1;
12878 bfd_vma addr;
12879 bfd_vma seg = -1;
12880 Elf_Internal_Rela outrel;
12881
12882 /* For static binaries sym_sec can be null. */
12883 if (sym_sec)
12884 {
12885 dynindx = elf_section_data (sym_sec->output_section)->dynindx;
12886 addr = dynreloc_value - sym_sec->output_section->vma;
12887 }
12888 else
12889 {
12890 dynindx = 0;
12891 addr = 0;
12892 }
12893
12894 if (bfd_link_pic(info) && dynindx == 0)
12895 abort();
12896
12897 /* Replace static FUNCDESC relocation with a
12898 R_ARM_RELATIVE dynamic relocation. */
12899 outrel.r_info = ELF32_R_INFO (0, R_ARM_RELATIVE);
12900 outrel.r_offset = input_section->output_section->vma
12901 + input_section->output_offset + rel->r_offset;
12902 outrel.r_addend = 0;
12903 if (bfd_link_pic(info))
12904 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
12905 else
12906 arm_elf_add_rofixup(output_bfd, globals->srofixup, outrel.r_offset);
12907
12908 bfd_put_32 (input_bfd, sgot->output_section->vma
12909 + sgot->output_offset + offset, hit_data);
12910
12911 /* Emit R_ARM_FUNCDESC_VALUE on funcdesc if not done yet. */
12912 arm_elf_fill_funcdesc(output_bfd, info,
12913 &eh->fdpic_cnts.funcdesc_offset,
12914 dynindx, offset, addr, dynreloc_value, seg);
12915 }
12916 else
12917 {
12918 Elf_Internal_Rela outrel;
12919
12920 /* Add a dynamic relocation. */
12921 outrel.r_info = ELF32_R_INFO (h->dynindx, R_ARM_FUNCDESC);
12922 outrel.r_offset = input_section->output_section->vma
12923 + input_section->output_offset + rel->r_offset;
12924 outrel.r_addend = 0;
12925 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
12926 }
12927 }
12928 }
12929 *unresolved_reloc_p = FALSE;
12930 return bfd_reloc_ok;
12931
e5d6e09e
AV		 12932 case R_ARM_THM_BF16:
12933 {
12934 bfd_vma relocation;
12935 bfd_vma upper_insn = bfd_get_16 (input_bfd, hit_data);
12936 bfd_vma lower_insn = bfd_get_16 (input_bfd, hit_data + 2);
12937
12938 if (globals->use_rel)
12939 {
12940 bfd_vma immA = (upper_insn & 0x001f);
12941 bfd_vma immB = (lower_insn & 0x07fe) >> 1;
12942 bfd_vma immC = (lower_insn & 0x0800) >> 11;
12943 addend = (immA << 12);
12944 addend |= (immB << 2);
12945 addend |= (immC << 1);
12946 addend |= 1;
12947 /* Sign extend. */
e6f65e75 12948 signed_addend = (addend & 0x10000) ? addend - (1 << 17) : addend;
e5d6e09e
AV		 12949 }
12950
e6f65e75 12951 relocation = value + signed_addend;
e5d6e09e
AV		 12952 relocation -= (input_section->output_section->vma
12953 + input_section->output_offset
12954 + rel->r_offset);
12955
12956 /* Put RELOCATION back into the insn. */
12957 {
12958 bfd_vma immA = (relocation & 0x0001f000) >> 12;
12959 bfd_vma immB = (relocation & 0x00000ffc) >> 2;
12960 bfd_vma immC = (relocation & 0x00000002) >> 1;
12961
12962 upper_insn = (upper_insn & 0xffe0) | immA;
12963 lower_insn = (lower_insn & 0xf001) | (immC << 11) | (immB << 1);
12964 }
12965
12966 /* Put the relocated value back in the object file: */
12967 bfd_put_16 (input_bfd, upper_insn, hit_data);
12968 bfd_put_16 (input_bfd, lower_insn, hit_data + 2);
12969
12970 return bfd_reloc_ok;
12971 }
12972
1889da70
AV		 12973 case R_ARM_THM_BF12:
12974 {
12975 bfd_vma relocation;
12976 bfd_vma upper_insn = bfd_get_16 (input_bfd, hit_data);
12977 bfd_vma lower_insn = bfd_get_16 (input_bfd, hit_data + 2);
12978
12979 if (globals->use_rel)
12980 {
12981 bfd_vma immA = (upper_insn & 0x0001);
12982 bfd_vma immB = (lower_insn & 0x07fe) >> 1;
12983 bfd_vma immC = (lower_insn & 0x0800) >> 11;
12984 addend = (immA << 12);
12985 addend |= (immB << 2);
12986 addend |= (immC << 1);
12987 addend |= 1;
12988 /* Sign extend. */
12989 addend = (addend & 0x1000) ? addend - (1 << 13) : addend;
e6f65e75 12990 signed_addend = addend;
1889da70
AV		 12991 }
12992
e6f65e75 12993 relocation = value + signed_addend;
1889da70
AV		 12994 relocation -= (input_section->output_section->vma
12995 + input_section->output_offset
12996 + rel->r_offset);
12997
12998 /* Put RELOCATION back into the insn. */
12999 {
13000 bfd_vma immA = (relocation & 0x00001000) >> 12;
13001 bfd_vma immB = (relocation & 0x00000ffc) >> 2;
13002 bfd_vma immC = (relocation & 0x00000002) >> 1;
13003
13004 upper_insn = (upper_insn & 0xfffe) | immA;
13005 lower_insn = (lower_insn & 0xf001) | (immC << 11) | (immB << 1);
13006 }
13007
13008 /* Put the relocated value back in the object file: */
13009 bfd_put_16 (input_bfd, upper_insn, hit_data);
13010 bfd_put_16 (input_bfd, lower_insn, hit_data + 2);
13011
13012 return bfd_reloc_ok;
13013 }
13014
1caf72a5
AV		 13015 case R_ARM_THM_BF18:
13016 {
13017 bfd_vma relocation;
13018 bfd_vma upper_insn = bfd_get_16 (input_bfd, hit_data);
13019 bfd_vma lower_insn = bfd_get_16 (input_bfd, hit_data + 2);
13020
13021 if (globals->use_rel)
13022 {
13023 bfd_vma immA = (upper_insn & 0x007f);
13024 bfd_vma immB = (lower_insn & 0x07fe) >> 1;
13025 bfd_vma immC = (lower_insn & 0x0800) >> 11;
13026 addend = (immA << 12);
13027 addend |= (immB << 2);
13028 addend |= (immC << 1);
13029 addend |= 1;
13030 /* Sign extend. */
13031 addend = (addend & 0x40000) ? addend - (1 << 19) : addend;
e6f65e75 13032 signed_addend = addend;
1caf72a5
AV		 13033 }
13034
e6f65e75 13035 relocation = value + signed_addend;
1caf72a5
AV		 13036 relocation -= (input_section->output_section->vma
13037 + input_section->output_offset
13038 + rel->r_offset);
13039
13040 /* Put RELOCATION back into the insn. */
13041 {
13042 bfd_vma immA = (relocation & 0x0007f000) >> 12;
13043 bfd_vma immB = (relocation & 0x00000ffc) >> 2;
13044 bfd_vma immC = (relocation & 0x00000002) >> 1;
13045
13046 upper_insn = (upper_insn & 0xff80) | immA;
13047 lower_insn = (lower_insn & 0xf001) | (immC << 11) | (immB << 1);
13048 }
13049
13050 /* Put the relocated value back in the object file: */
13051 bfd_put_16 (input_bfd, upper_insn, hit_data);
13052 bfd_put_16 (input_bfd, lower_insn, hit_data + 2);
13053
13054 return bfd_reloc_ok;
13055 }
13056
252b5132
RH		 13057 default:
13058 return bfd_reloc_notsupported;
13059 }
13060}
13061
98c1d4aa
NC		 13062/* Add INCREMENT to the reloc (of type HOWTO) at ADDRESS. */
13063static void
07d6d2b8
AM		 13064arm_add_to_rel (bfd * abfd,
13065 bfd_byte * address,
57e8b36a 13066 reloc_howto_type * howto,
07d6d2b8 13067 bfd_signed_vma increment)
98c1d4aa 13068{
98c1d4aa
NC		 13069 bfd_signed_vma addend;
13070
bd97cb95
DJ		 13071 if (howto->type == R_ARM_THM_CALL
13072 || howto->type == R_ARM_THM_JUMP24)
98c1d4aa 13073 {
9a5aca8c
AM		 13074 int upper_insn, lower_insn;
13075 int upper, lower;
98c1d4aa 13076
9a5aca8c
AM		 13077 upper_insn = bfd_get_16 (abfd, address);
13078 lower_insn = bfd_get_16 (abfd, address + 2);
13079 upper = upper_insn & 0x7ff;
13080 lower = lower_insn & 0x7ff;
13081
13082 addend = (upper << 12) | (lower << 1);
ddda4409 13083 addend += increment;
9a5aca8c 13084 addend >>= 1;
98c1d4aa 13085
9a5aca8c
AM		 13086 upper_insn = (upper_insn & 0xf800) | ((addend >> 11) & 0x7ff);
13087 lower_insn = (lower_insn & 0xf800) | (addend & 0x7ff);
13088
dc810e39
AM		 13089 bfd_put_16 (abfd, (bfd_vma) upper_insn, address);
13090 bfd_put_16 (abfd, (bfd_vma) lower_insn, address + 2);
9a5aca8c
AM		 13091 }
13092 else
13093 {
07d6d2b8 13094 bfd_vma contents;
9a5aca8c
AM		 13095
13096 contents = bfd_get_32 (abfd, address);
13097
13098 /* Get the (signed) value from the instruction. */
13099 addend = contents & howto->src_mask;
13100 if (addend & ((howto->src_mask + 1) >> 1))
13101 {
13102 bfd_signed_vma mask;
13103
13104 mask = -1;
13105 mask &= ~ howto->src_mask;
13106 addend |= mask;
13107 }
13108
13109 /* Add in the increment, (which is a byte value). */
13110 switch (howto->type)
13111 {
13112 default:
13113 addend += increment;
13114 break;
13115
13116 case R_ARM_PC24:
c6596c5e 13117 case R_ARM_PLT32:
5b5bb741
PB		 13118 case R_ARM_CALL:
13119 case R_ARM_JUMP24:
9a5aca8c 13120 addend <<= howto->size;
dc810e39 13121 addend += increment;
9a5aca8c
AM		 13122
13123 /* Should we check for overflow here ? */
13124
13125 /* Drop any undesired bits. */
13126 addend >>= howto->rightshift;
13127 break;
13128 }
13129
13130 contents = (contents & ~ howto->dst_mask) | (addend & howto->dst_mask);
13131
13132 bfd_put_32 (abfd, contents, address);
ddda4409 13133 }
98c1d4aa 13134}
252b5132 13135
ba93b8ac
DJ		 13136#define IS_ARM_TLS_RELOC(R_TYPE) \
13137 ((R_TYPE) == R_ARM_TLS_GD32 \
5c5a4843 13138 || (R_TYPE) == R_ARM_TLS_GD32_FDPIC \
ba93b8ac
DJ		 13139 || (R_TYPE) == R_ARM_TLS_LDO32 \
13140 || (R_TYPE) == R_ARM_TLS_LDM32 \
5c5a4843 13141 || (R_TYPE) == R_ARM_TLS_LDM32_FDPIC \
ba93b8ac
DJ		 13142 || (R_TYPE) == R_ARM_TLS_DTPOFF32 \
13143 || (R_TYPE) == R_ARM_TLS_DTPMOD32 \
13144 || (R_TYPE) == R_ARM_TLS_TPOFF32 \
13145 || (R_TYPE) == R_ARM_TLS_LE32 \
0855e32b 13146 || (R_TYPE) == R_ARM_TLS_IE32 \
5c5a4843 13147 || (R_TYPE) == R_ARM_TLS_IE32_FDPIC \
0855e32b
NS		 13148 || IS_ARM_TLS_GNU_RELOC (R_TYPE))
13149
13150/* Specific set of relocations for the gnu tls dialect. */
13151#define IS_ARM_TLS_GNU_RELOC(R_TYPE) \
13152 ((R_TYPE) == R_ARM_TLS_GOTDESC \
13153 || (R_TYPE) == R_ARM_TLS_CALL \
13154 || (R_TYPE) == R_ARM_THM_TLS_CALL \
13155 || (R_TYPE) == R_ARM_TLS_DESCSEQ \
13156 || (R_TYPE) == R_ARM_THM_TLS_DESCSEQ)
ba93b8ac 13157
252b5132 13158/* Relocate an ARM ELF section. */
906e58ca 13159
b34976b6 13160static bfd_boolean
07d6d2b8 13161elf32_arm_relocate_section (bfd * output_bfd,
57e8b36a 13162 struct bfd_link_info * info,
07d6d2b8
AM		 13163 bfd * input_bfd,
13164 asection * input_section,
13165 bfd_byte * contents,
13166 Elf_Internal_Rela * relocs,
13167 Elf_Internal_Sym * local_syms,
13168 asection ** local_sections)
252b5132 13169{
b34976b6
AM		 13170 Elf_Internal_Shdr *symtab_hdr;
13171 struct elf_link_hash_entry **sym_hashes;
13172 Elf_Internal_Rela *rel;
13173 Elf_Internal_Rela *relend;
13174 const char *name;
b32d3aa2 13175 struct elf32_arm_link_hash_table * globals;
252b5132 13176
4e7fd91e 13177 globals = elf32_arm_hash_table (info);
4dfe6ac6
NC		 13178 if (globals == NULL)
13179 return FALSE;
b491616a 13180
0ffa91dd 13181 symtab_hdr = & elf_symtab_hdr (input_bfd);
252b5132
RH		 13182 sym_hashes = elf_sym_hashes (input_bfd);
13183
13184 rel = relocs;
13185 relend = relocs + input_section->reloc_count;
13186 for (; rel < relend; rel++)
13187 {
07d6d2b8
AM		 13188 int r_type;
13189 reloc_howto_type * howto;
13190 unsigned long r_symndx;
13191 Elf_Internal_Sym * sym;
13192 asection * sec;
252b5132 13193 struct elf_link_hash_entry * h;
07d6d2b8
AM		 13194 bfd_vma relocation;
13195 bfd_reloc_status_type r;
13196 arelent bfd_reloc;
13197 char sym_type;
13198 bfd_boolean unresolved_reloc = FALSE;
f2a9dd69 13199 char *error_message = NULL;
f21f3fe0 13200
252b5132 13201 r_symndx = ELF32_R_SYM (rel->r_info);
ba96a88f 13202 r_type = ELF32_R_TYPE (rel->r_info);
b32d3aa2 13203 r_type = arm_real_reloc_type (globals, r_type);
252b5132 13204
ba96a88f 13205 if ( r_type == R_ARM_GNU_VTENTRY
99059e56
RM		 13206 || r_type == R_ARM_GNU_VTINHERIT)
13207 continue;
252b5132 13208
47aeb64c
NC		 13209 howto = bfd_reloc.howto = elf32_arm_howto_from_type (r_type);
13210
13211 if (howto == NULL)
13212 return _bfd_unrecognized_reloc (input_bfd, input_section, r_type);
252b5132 13213
252b5132
RH		 13214 h = NULL;
13215 sym = NULL;
13216 sec = NULL;
9b485d32 13217
252b5132
RH		 13218 if (r_symndx < symtab_hdr->sh_info)
13219 {
13220 sym = local_syms + r_symndx;
ba93b8ac 13221 sym_type = ELF32_ST_TYPE (sym->st_info);
252b5132 13222 sec = local_sections[r_symndx];
ffcb4889
NS		 13223
13224 /* An object file might have a reference to a local
13225 undefined symbol. This is a daft object file, but we
13226 should at least do something about it. V4BX & NONE
13227 relocations do not use the symbol and are explicitly
77b4f08f
TS		 13228 allowed to use the undefined symbol, so allow those.
13229 Likewise for relocations against STN_UNDEF. */
ffcb4889
NS		 13230 if (r_type != R_ARM_V4BX
13231 && r_type != R_ARM_NONE
77b4f08f 13232 && r_symndx != STN_UNDEF
ffcb4889
NS		 13233 && bfd_is_und_section (sec)
13234 && ELF_ST_BIND (sym->st_info) != STB_WEAK)
1a72702b
AM		 13235 (*info->callbacks->undefined_symbol)
13236 (info, bfd_elf_string_from_elf_section
13237 (input_bfd, symtab_hdr->sh_link, sym->st_name),
13238 input_bfd, input_section,
13239 rel->r_offset, TRUE);
b38cadfb 13240
4e7fd91e 13241 if (globals->use_rel)
f8df10f4 13242 {
4e7fd91e
PB		 13243 relocation = (sec->output_section->vma
13244 + sec->output_offset
13245 + sym->st_value);
0e1862bb 13246 if (!bfd_link_relocatable (info)
ab96bf03
AM		 13247 && (sec->flags & SEC_MERGE)
13248 && ELF_ST_TYPE (sym->st_info) == STT_SECTION)
f8df10f4 13249 {
4e7fd91e
PB		 13250 asection *msec;
13251 bfd_vma addend, value;
13252
39623e12 13253 switch (r_type)
4e7fd91e 13254 {
39623e12
PB		 13255 case R_ARM_MOVW_ABS_NC:
13256 case R_ARM_MOVT_ABS:
13257 value = bfd_get_32 (input_bfd, contents + rel->r_offset);
13258 addend = ((value & 0xf0000) >> 4) | (value & 0xfff);
13259 addend = (addend ^ 0x8000) - 0x8000;
13260 break;
f8df10f4 13261
39623e12
PB		 13262 case R_ARM_THM_MOVW_ABS_NC:
13263 case R_ARM_THM_MOVT_ABS:
13264 value = bfd_get_16 (input_bfd, contents + rel->r_offset)
13265 << 16;
13266 value |= bfd_get_16 (input_bfd,
13267 contents + rel->r_offset + 2);
13268 addend = ((value & 0xf7000) >> 4) | (value & 0xff)
13269 | ((value & 0x04000000) >> 15);
13270 addend = (addend ^ 0x8000) - 0x8000;
13271 break;
f8df10f4 13272
39623e12
PB		 13273 default:
13274 if (howto->rightshift
13275 || (howto->src_mask & (howto->src_mask + 1)))
13276 {
4eca0228 13277 _bfd_error_handler
695344c0 13278 /* xgettext:c-format */
2dcf00ce
AM		 13279 (_("%pB(%pA+%#" PRIx64 "): "
13280 "%s relocation against SEC_MERGE section"),
39623e12 13281 input_bfd, input_section,
2dcf00ce 13282 (uint64_t) rel->r_offset, howto->name);
39623e12
PB		 13283 return FALSE;
13284 }
13285
13286 value = bfd_get_32 (input_bfd, contents + rel->r_offset);
13287
13288 /* Get the (signed) value from the instruction. */
13289 addend = value & howto->src_mask;
13290 if (addend & ((howto->src_mask + 1) >> 1))
13291 {
13292 bfd_signed_vma mask;
13293
13294 mask = -1;
13295 mask &= ~ howto->src_mask;
13296 addend |= mask;
13297 }
13298 break;
4e7fd91e 13299 }
39623e12 13300
4e7fd91e
PB		 13301 msec = sec;
13302 addend =
13303 _bfd_elf_rel_local_sym (output_bfd, sym, &msec, addend)
13304 - relocation;
13305 addend += msec->output_section->vma + msec->output_offset;
39623e12 13306
cc643b88 13307 /* Cases here must match those in the preceding
39623e12
PB		 13308 switch statement. */
13309 switch (r_type)
13310 {
13311 case R_ARM_MOVW_ABS_NC:
13312 case R_ARM_MOVT_ABS:
13313 value = (value & 0xfff0f000) | ((addend & 0xf000) << 4)
13314 | (addend & 0xfff);
13315 bfd_put_32 (input_bfd, value, contents + rel->r_offset);
13316 break;
13317
13318 case R_ARM_THM_MOVW_ABS_NC:
13319 case R_ARM_THM_MOVT_ABS:
13320 value = (value & 0xfbf08f00) | ((addend & 0xf700) << 4)
13321 | (addend & 0xff) | ((addend & 0x0800) << 15);
13322 bfd_put_16 (input_bfd, value >> 16,
13323 contents + rel->r_offset);
13324 bfd_put_16 (input_bfd, value,
13325 contents + rel->r_offset + 2);
13326 break;
13327
13328 default:
13329 value = (value & ~ howto->dst_mask)
13330 | (addend & howto->dst_mask);
13331 bfd_put_32 (input_bfd, value, contents + rel->r_offset);
13332 break;
13333 }
f8df10f4 13334 }
f8df10f4 13335 }
4e7fd91e
PB		 13336 else
13337 relocation = _bfd_elf_rela_local_sym (output_bfd, sym, &sec, rel);
252b5132
RH		 13338 }
13339 else
13340 {
62d887d4 13341 bfd_boolean warned, ignored;
560e09e9 13342
b2a8e766
AM		 13343 RELOC_FOR_GLOBAL_SYMBOL (info, input_bfd, input_section, rel,
13344 r_symndx, symtab_hdr, sym_hashes,
13345 h, sec, relocation,
62d887d4 13346 unresolved_reloc, warned, ignored);
ba93b8ac
DJ		 13347
13348 sym_type = h->type;
252b5132
RH		 13349 }
13350
dbaa2011 13351 if (sec != NULL && discarded_section (sec))
e4067dbb 13352 RELOC_AGAINST_DISCARDED_SECTION (info, input_bfd, input_section,
545fd46b 13353 rel, 1, relend, howto, 0, contents);
ab96bf03 13354
0e1862bb 13355 if (bfd_link_relocatable (info))
ab96bf03
AM		 13356 {
13357 /* This is a relocatable link. We don't have to change
13358 anything, unless the reloc is against a section symbol,
13359 in which case we have to adjust according to where the
13360 section symbol winds up in the output section. */
13361 if (sym != NULL && ELF_ST_TYPE (sym->st_info) == STT_SECTION)
13362 {
13363 if (globals->use_rel)
13364 arm_add_to_rel (input_bfd, contents + rel->r_offset,
13365 howto, (bfd_signed_vma) sec->output_offset);
13366 else
13367 rel->r_addend += sec->output_offset;
13368 }
13369 continue;
13370 }
13371
252b5132
RH		 13372 if (h != NULL)
13373 name = h->root.root.string;
13374 else
13375 {
13376 name = (bfd_elf_string_from_elf_section
13377 (input_bfd, symtab_hdr->sh_link, sym->st_name));
13378 if (name == NULL || *name == '\0')
13379 name = bfd_section_name (input_bfd, sec);
13380 }
f21f3fe0 13381
cf35638d 13382 if (r_symndx != STN_UNDEF
ba93b8ac
DJ		 13383 && r_type != R_ARM_NONE
13384 && (h == NULL
13385 || h->root.type == bfd_link_hash_defined
13386 || h->root.type == bfd_link_hash_defweak)
13387 && IS_ARM_TLS_RELOC (r_type) != (sym_type == STT_TLS))
13388 {
4eca0228 13389 _bfd_error_handler
ba93b8ac 13390 ((sym_type == STT_TLS
695344c0 13391 /* xgettext:c-format */
2dcf00ce 13392 ? _("%pB(%pA+%#" PRIx64 "): %s used with TLS symbol %s")
695344c0 13393 /* xgettext:c-format */
2dcf00ce 13394 : _("%pB(%pA+%#" PRIx64 "): %s used with non-TLS symbol %s")),
ba93b8ac
DJ		 13395 input_bfd,
13396 input_section,
2dcf00ce 13397 (uint64_t) rel->r_offset,
ba93b8ac
DJ		 13398 howto->name,
13399 name);
13400 }
13401
0855e32b 13402 /* We call elf32_arm_final_link_relocate unless we're completely
99059e56
RM		 13403 done, i.e., the relaxation produced the final output we want,
13404 and we won't let anybody mess with it. Also, we have to do
13405 addend adjustments in case of a R_ARM_TLS_GOTDESC relocation
6a631e86 13406 both in relaxed and non-relaxed cases. */
39d911fc
TP		 13407 if ((elf32_arm_tls_transition (info, r_type, h) != (unsigned)r_type)
13408 || (IS_ARM_TLS_GNU_RELOC (r_type)
13409 && !((h ? elf32_arm_hash_entry (h)->tls_type :
13410 elf32_arm_local_got_tls_type (input_bfd)[r_symndx])
13411 & GOT_TLS_GDESC)))
13412 {
13413 r = elf32_arm_tls_relax (globals, input_bfd, input_section,
13414 contents, rel, h == NULL);
13415 /* This may have been marked unresolved because it came from
13416 a shared library. But we've just dealt with that. */
13417 unresolved_reloc = 0;
13418 }
13419 else
13420 r = bfd_reloc_continue;
b38cadfb 13421
39d911fc
TP		 13422 if (r == bfd_reloc_continue)
13423 {
13424 unsigned char branch_type =
13425 h ? ARM_GET_SYM_BRANCH_TYPE (h->target_internal)
13426 : ARM_GET_SYM_BRANCH_TYPE (sym->st_target_internal);
13427
13428 r = elf32_arm_final_link_relocate (howto, input_bfd, output_bfd,
13429 input_section, contents, rel,
13430 relocation, info, sec, name,
13431 sym_type, branch_type, h,
13432 &unresolved_reloc,
13433 &error_message);
13434 }
0945cdfd
DJ		 13435
13436 /* Dynamic relocs are not propagated for SEC_DEBUGGING sections
13437 because such sections are not SEC_ALLOC and thus ld.so will
13438 not process them. */
13439 if (unresolved_reloc
99059e56
RM		 13440 && !((input_section->flags & SEC_DEBUGGING) != 0
13441 && h->def_dynamic)
1d5316ab
AM		 13442 && _bfd_elf_section_offset (output_bfd, info, input_section,
13443 rel->r_offset) != (bfd_vma) -1)
0945cdfd 13444 {
4eca0228 13445 _bfd_error_handler
695344c0 13446 /* xgettext:c-format */
2dcf00ce
AM		 13447 (_("%pB(%pA+%#" PRIx64 "): "
13448 "unresolvable %s relocation against symbol `%s'"),
843fe662
L		 13449 input_bfd,
13450 input_section,
2dcf00ce 13451 (uint64_t) rel->r_offset,
843fe662
L		 13452 howto->name,
13453 h->root.root.string);
0945cdfd
DJ		 13454 return FALSE;
13455 }
252b5132
RH		 13456
13457 if (r != bfd_reloc_ok)
13458 {
252b5132
RH		 13459 switch (r)
13460 {
13461 case bfd_reloc_overflow:
cf919dfd
PB		 13462 /* If the overflowing reloc was to an undefined symbol,
13463 we have already printed one error message and there
13464 is no point complaining again. */
1a72702b
AM		 13465 if (!h || h->root.type != bfd_link_hash_undefined)
13466 (*info->callbacks->reloc_overflow)
13467 (info, (h ? &h->root : NULL), name, howto->name,
13468 (bfd_vma) 0, input_bfd, input_section, rel->r_offset);
252b5132
RH		 13469 break;
13470
13471 case bfd_reloc_undefined:
1a72702b
AM		 13472 (*info->callbacks->undefined_symbol)
13473 (info, name, input_bfd, input_section, rel->r_offset, TRUE);
252b5132
RH		 13474 break;
13475
13476 case bfd_reloc_outofrange:
f2a9dd69 13477 error_message = _("out of range");
252b5132
RH		 13478 goto common_error;
13479
13480 case bfd_reloc_notsupported:
f2a9dd69 13481 error_message = _("unsupported relocation");
252b5132
RH		 13482 goto common_error;
13483
13484 case bfd_reloc_dangerous:
f2a9dd69 13485 /* error_message should already be set. */
252b5132
RH		 13486 goto common_error;
13487
13488 default:
f2a9dd69 13489 error_message = _("unknown error");
8029a119 13490 /* Fall through. */
252b5132
RH		 13491
13492 common_error:
f2a9dd69 13493 BFD_ASSERT (error_message != NULL);
1a72702b
AM		 13494 (*info->callbacks->reloc_dangerous)
13495 (info, error_message, input_bfd, input_section, rel->r_offset);
252b5132
RH		 13496 break;
13497 }
13498 }
13499 }
13500
b34976b6 13501 return TRUE;
252b5132
RH		 13502}
13503
91d6fa6a 13504/* Add a new unwind edit to the list described by HEAD, TAIL. If TINDEX is zero,
2468f9c9 13505 adds the edit to the start of the list. (The list must be built in order of
91d6fa6a 13506 ascending TINDEX: the function's callers are primarily responsible for
2468f9c9
PB		 13507 maintaining that condition). */
13508
13509static void
13510add_unwind_table_edit (arm_unwind_table_edit **head,
13511 arm_unwind_table_edit **tail,
13512 arm_unwind_edit_type type,
13513 asection *linked_section,
91d6fa6a 13514 unsigned int tindex)
2468f9c9 13515{
21d799b5
NC		 13516 arm_unwind_table_edit *new_edit = (arm_unwind_table_edit *)
13517 xmalloc (sizeof (arm_unwind_table_edit));
b38cadfb 13518
2468f9c9
PB		 13519 new_edit->type = type;
13520 new_edit->linked_section = linked_section;
91d6fa6a 13521 new_edit->index = tindex;
b38cadfb 13522
91d6fa6a 13523 if (tindex > 0)
2468f9c9
PB		 13524 {
13525 new_edit->next = NULL;
13526
13527 if (*tail)
13528 (*tail)->next = new_edit;
13529
13530 (*tail) = new_edit;
13531
13532 if (!*head)
13533 (*head) = new_edit;
13534 }
13535 else
13536 {
13537 new_edit->next = *head;
13538
13539 if (!*tail)
13540 *tail = new_edit;
13541
13542 *head = new_edit;
13543 }
13544}
13545
13546static _arm_elf_section_data *get_arm_elf_section_data (asection *);
13547
13548/* Increase the size of EXIDX_SEC by ADJUST bytes. ADJUST mau be negative. */
13549static void
13550adjust_exidx_size(asection *exidx_sec, int adjust)
13551{
13552 asection *out_sec;
13553
13554 if (!exidx_sec->rawsize)
13555 exidx_sec->rawsize = exidx_sec->size;
13556
13557 bfd_set_section_size (exidx_sec->owner, exidx_sec, exidx_sec->size + adjust);
13558 out_sec = exidx_sec->output_section;
13559 /* Adjust size of output section. */
13560 bfd_set_section_size (out_sec->owner, out_sec, out_sec->size +adjust);
13561}
13562
13563/* Insert an EXIDX_CANTUNWIND marker at the end of a section. */
13564static void
13565insert_cantunwind_after(asection *text_sec, asection *exidx_sec)
13566{
13567 struct _arm_elf_section_data *exidx_arm_data;
13568
13569 exidx_arm_data = get_arm_elf_section_data (exidx_sec);
13570 add_unwind_table_edit (
13571 &exidx_arm_data->u.exidx.unwind_edit_list,
13572 &exidx_arm_data->u.exidx.unwind_edit_tail,
13573 INSERT_EXIDX_CANTUNWIND_AT_END, text_sec, UINT_MAX);
13574
491d01d3
YU		 13575 exidx_arm_data->additional_reloc_count++;
13576
2468f9c9
PB		 13577 adjust_exidx_size(exidx_sec, 8);
13578}
13579
13580/* Scan .ARM.exidx tables, and create a list describing edits which should be
13581 made to those tables, such that:
b38cadfb 13582
2468f9c9
PB		 13583 1. Regions without unwind data are marked with EXIDX_CANTUNWIND entries.
13584 2. Duplicate entries are merged together (EXIDX_CANTUNWIND, or unwind
99059e56 13585 codes which have been inlined into the index).
2468f9c9 13586
85fdf906
AH		 13587 If MERGE_EXIDX_ENTRIES is false, duplicate entries are not merged.
13588
2468f9c9 13589 The edits are applied when the tables are written
b38cadfb 13590 (in elf32_arm_write_section). */
2468f9c9
PB		 13591
13592bfd_boolean
13593elf32_arm_fix_exidx_coverage (asection **text_section_order,
13594 unsigned int num_text_sections,
85fdf906
AH		 13595 struct bfd_link_info *info,
13596 bfd_boolean merge_exidx_entries)
2468f9c9
PB		 13597{
13598 bfd *inp;
13599 unsigned int last_second_word = 0, i;
13600 asection *last_exidx_sec = NULL;
13601 asection *last_text_sec = NULL;
13602 int last_unwind_type = -1;
13603
13604 /* Walk over all EXIDX sections, and create backlinks from the corrsponding
13605 text sections. */
c72f2fb2 13606 for (inp = info->input_bfds; inp != NULL; inp = inp->link.next)
2468f9c9
PB		 13607 {
13608 asection *sec;
b38cadfb 13609
2468f9c9 13610 for (sec = inp->sections; sec != NULL; sec = sec->next)
99059e56 13611 {
2468f9c9
PB		 13612 struct bfd_elf_section_data *elf_sec = elf_section_data (sec);
13613 Elf_Internal_Shdr *hdr = &elf_sec->this_hdr;
b38cadfb 13614
dec9d5df 13615 if (!hdr || hdr->sh_type != SHT_ARM_EXIDX)
2468f9c9 13616 continue;
b38cadfb 13617
2468f9c9
PB		 13618 if (elf_sec->linked_to)
13619 {
13620 Elf_Internal_Shdr *linked_hdr
99059e56 13621 = &elf_section_data (elf_sec->linked_to)->this_hdr;
2468f9c9 13622 struct _arm_elf_section_data *linked_sec_arm_data
99059e56 13623 = get_arm_elf_section_data (linked_hdr->bfd_section);
2468f9c9
PB		 13624
13625 if (linked_sec_arm_data == NULL)
99059e56 13626 continue;
2468f9c9
PB		 13627
13628 /* Link this .ARM.exidx section back from the text section it
99059e56 13629 describes. */
2468f9c9
PB		 13630 linked_sec_arm_data->u.text.arm_exidx_sec = sec;
13631 }
13632 }
13633 }
13634
13635 /* Walk all text sections in order of increasing VMA. Eilminate duplicate
13636 index table entries (EXIDX_CANTUNWIND and inlined unwind opcodes),
91d6fa6a 13637 and add EXIDX_CANTUNWIND entries for sections with no unwind table data. */
2468f9c9
PB		 13638
13639 for (i = 0; i < num_text_sections; i++)
13640 {
13641 asection *sec = text_section_order[i];
13642 asection *exidx_sec;
13643 struct _arm_elf_section_data *arm_data = get_arm_elf_section_data (sec);
13644 struct _arm_elf_section_data *exidx_arm_data;
13645 bfd_byte *contents = NULL;
13646 int deleted_exidx_bytes = 0;
13647 bfd_vma j;
13648 arm_unwind_table_edit *unwind_edit_head = NULL;
13649 arm_unwind_table_edit *unwind_edit_tail = NULL;
13650 Elf_Internal_Shdr *hdr;
13651 bfd *ibfd;
13652
13653 if (arm_data == NULL)
99059e56 13654 continue;
2468f9c9
PB		 13655
13656 exidx_sec = arm_data->u.text.arm_exidx_sec;
13657 if (exidx_sec == NULL)
13658 {
13659 /* Section has no unwind data. */
13660 if (last_unwind_type == 0 || !last_exidx_sec)
13661 continue;
13662
13663 /* Ignore zero sized sections. */
13664 if (sec->size == 0)
13665 continue;
13666
13667 insert_cantunwind_after(last_text_sec, last_exidx_sec);
13668 last_unwind_type = 0;
13669 continue;
13670 }
13671
22a8f80e
PB		 13672 /* Skip /DISCARD/ sections. */
13673 if (bfd_is_abs_section (exidx_sec->output_section))
13674 continue;
13675
2468f9c9
PB		 13676 hdr = &elf_section_data (exidx_sec)->this_hdr;
13677 if (hdr->sh_type != SHT_ARM_EXIDX)
99059e56 13678 continue;
b38cadfb 13679
2468f9c9
PB		 13680 exidx_arm_data = get_arm_elf_section_data (exidx_sec);
13681 if (exidx_arm_data == NULL)
99059e56 13682 continue;
b38cadfb 13683
2468f9c9 13684 ibfd = exidx_sec->owner;
b38cadfb 13685
2468f9c9
PB		 13686 if (hdr->contents != NULL)
13687 contents = hdr->contents;
13688 else if (! bfd_malloc_and_get_section (ibfd, exidx_sec, &contents))
13689 /* An error? */
13690 continue;
13691
ac06903d
YU		 13692 if (last_unwind_type > 0)
13693 {
13694 unsigned int first_word = bfd_get_32 (ibfd, contents);
13695 /* Add cantunwind if first unwind item does not match section
13696 start. */
13697 if (first_word != sec->vma)
13698 {
13699 insert_cantunwind_after (last_text_sec, last_exidx_sec);
13700 last_unwind_type = 0;
13701 }
13702 }
13703
2468f9c9
PB		 13704 for (j = 0; j < hdr->sh_size; j += 8)
13705 {
13706 unsigned int second_word = bfd_get_32 (ibfd, contents + j + 4);
13707 int unwind_type;
13708 int elide = 0;
13709
13710 /* An EXIDX_CANTUNWIND entry. */
13711 if (second_word == 1)
13712 {
13713 if (last_unwind_type == 0)
13714 elide = 1;
13715 unwind_type = 0;
13716 }
13717 /* Inlined unwinding data. Merge if equal to previous. */
13718 else if ((second_word & 0x80000000) != 0)
13719 {
85fdf906
AH		 13720 if (merge_exidx_entries
13721 && last_second_word == second_word && last_unwind_type == 1)
2468f9c9
PB		 13722 elide = 1;
13723 unwind_type = 1;
13724 last_second_word = second_word;
13725 }
13726 /* Normal table entry. In theory we could merge these too,
13727 but duplicate entries are likely to be much less common. */
13728 else
13729 unwind_type = 2;
13730
491d01d3 13731 if (elide && !bfd_link_relocatable (info))
2468f9c9
PB		 13732 {
13733 add_unwind_table_edit (&unwind_edit_head, &unwind_edit_tail,
13734 DELETE_EXIDX_ENTRY, NULL, j / 8);
13735
13736 deleted_exidx_bytes += 8;
13737 }
13738
13739 last_unwind_type = unwind_type;
13740 }
13741
13742 /* Free contents if we allocated it ourselves. */
13743 if (contents != hdr->contents)
99059e56 13744 free (contents);
2468f9c9
PB		 13745
13746 /* Record edits to be applied later (in elf32_arm_write_section). */
13747 exidx_arm_data->u.exidx.unwind_edit_list = unwind_edit_head;
13748 exidx_arm_data->u.exidx.unwind_edit_tail = unwind_edit_tail;
b38cadfb 13749
2468f9c9
PB		 13750 if (deleted_exidx_bytes > 0)
13751 adjust_exidx_size(exidx_sec, -deleted_exidx_bytes);
13752
13753 last_exidx_sec = exidx_sec;
13754 last_text_sec = sec;
13755 }
13756
13757 /* Add terminating CANTUNWIND entry. */
491d01d3
YU		 13758 if (!bfd_link_relocatable (info) && last_exidx_sec
13759 && last_unwind_type != 0)
2468f9c9
PB		 13760 insert_cantunwind_after(last_text_sec, last_exidx_sec);
13761
13762 return TRUE;
13763}
13764
3e6b1042
DJ		 13765static bfd_boolean
13766elf32_arm_output_glue_section (struct bfd_link_info *info, bfd *obfd,
13767 bfd *ibfd, const char *name)
13768{
13769 asection *sec, *osec;
13770
3d4d4302 13771 sec = bfd_get_linker_section (ibfd, name);
3e6b1042
DJ		 13772 if (sec == NULL || (sec->flags & SEC_EXCLUDE) != 0)
13773 return TRUE;
13774
13775 osec = sec->output_section;
13776 if (elf32_arm_write_section (obfd, info, sec, sec->contents))
13777 return TRUE;
13778
13779 if (! bfd_set_section_contents (obfd, osec, sec->contents,
13780 sec->output_offset, sec->size))
13781 return FALSE;
13782
13783 return TRUE;
13784}
13785
13786static bfd_boolean
13787elf32_arm_final_link (bfd *abfd, struct bfd_link_info *info)
13788{
13789 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (info);
fe33d2fa 13790 asection *sec, *osec;
3e6b1042 13791
4dfe6ac6
NC		 13792 if (globals == NULL)
13793 return FALSE;
13794
3e6b1042
DJ		 13795 /* Invoke the regular ELF backend linker to do all the work. */
13796 if (!bfd_elf_final_link (abfd, info))
13797 return FALSE;
13798
fe33d2fa
CL		 13799 /* Process stub sections (eg BE8 encoding, ...). */
13800 struct elf32_arm_link_hash_table *htab = elf32_arm_hash_table (info);
7292b3ac 13801 unsigned int i;
cdb21a0a
NS		 13802 for (i=0; i<htab->top_id; i++)
13803 {
13804 sec = htab->stub_group[i].stub_sec;
13805 /* Only process it once, in its link_sec slot. */
13806 if (sec && i == htab->stub_group[i].link_sec->id)
13807 {
13808 osec = sec->output_section;
13809 elf32_arm_write_section (abfd, info, sec, sec->contents);
13810 if (! bfd_set_section_contents (abfd, osec, sec->contents,
13811 sec->output_offset, sec->size))
13812 return FALSE;
13813 }
fe33d2fa 13814 }
fe33d2fa 13815
3e6b1042
DJ		 13816 /* Write out any glue sections now that we have created all the
13817 stubs. */
13818 if (globals->bfd_of_glue_owner != NULL)
13819 {
13820 if (! elf32_arm_output_glue_section (info, abfd,
13821 globals->bfd_of_glue_owner,
13822 ARM2THUMB_GLUE_SECTION_NAME))
13823 return FALSE;
13824
13825 if (! elf32_arm_output_glue_section (info, abfd,
13826 globals->bfd_of_glue_owner,
13827 THUMB2ARM_GLUE_SECTION_NAME))
13828 return FALSE;
13829
13830 if (! elf32_arm_output_glue_section (info, abfd,
13831 globals->bfd_of_glue_owner,
13832 VFP11_ERRATUM_VENEER_SECTION_NAME))
13833 return FALSE;
13834
a504d23a
LA		 13835 if (! elf32_arm_output_glue_section (info, abfd,
13836 globals->bfd_of_glue_owner,
13837 STM32L4XX_ERRATUM_VENEER_SECTION_NAME))
13838 return FALSE;
13839
3e6b1042
DJ		 13840 if (! elf32_arm_output_glue_section (info, abfd,
13841 globals->bfd_of_glue_owner,
13842 ARM_BX_GLUE_SECTION_NAME))
13843 return FALSE;
13844 }
13845
13846 return TRUE;
13847}
13848
5968a7b8
NC		 13849/* Return a best guess for the machine number based on the attributes. */
13850
13851static unsigned int
13852bfd_arm_get_mach_from_attributes (bfd * abfd)
13853{
13854 int arch = bfd_elf_get_obj_attr_int (abfd, OBJ_ATTR_PROC, Tag_CPU_arch);
13855
13856 switch (arch)
13857 {
c0c468d5 13858 case TAG_CPU_ARCH_PRE_V4: return bfd_mach_arm_3M;
5968a7b8
NC		 13859 case TAG_CPU_ARCH_V4: return bfd_mach_arm_4;
13860 case TAG_CPU_ARCH_V4T: return bfd_mach_arm_4T;
13861 case TAG_CPU_ARCH_V5T: return bfd_mach_arm_5T;
13862
13863 case TAG_CPU_ARCH_V5TE:
13864 {
13865 char * name;
13866
13867 BFD_ASSERT (Tag_CPU_name < NUM_KNOWN_OBJ_ATTRIBUTES);
13868 name = elf_known_obj_attributes (abfd) [OBJ_ATTR_PROC][Tag_CPU_name].s;
13869
13870 if (name)
13871 {
13872 if (strcmp (name, "IWMMXT2") == 0)
13873 return bfd_mach_arm_iWMMXt2;
13874
13875 if (strcmp (name, "IWMMXT") == 0)
6034aab8 13876 return bfd_mach_arm_iWMMXt;
088ca6c1
NC		 13877
13878 if (strcmp (name, "XSCALE") == 0)
13879 {
13880 int wmmx;
13881
13882 BFD_ASSERT (Tag_WMMX_arch < NUM_KNOWN_OBJ_ATTRIBUTES);
13883 wmmx = elf_known_obj_attributes (abfd) [OBJ_ATTR_PROC][Tag_WMMX_arch].i;
13884 switch (wmmx)
13885 {
13886 case 1: return bfd_mach_arm_iWMMXt;
13887 case 2: return bfd_mach_arm_iWMMXt2;
13888 default: return bfd_mach_arm_XScale;
13889 }
13890 }
5968a7b8
NC		 13891 }
13892
13893 return bfd_mach_arm_5TE;
13894 }
13895
c0c468d5
TP		 13896 case TAG_CPU_ARCH_V5TEJ:
13897 return bfd_mach_arm_5TEJ;
13898 case TAG_CPU_ARCH_V6:
13899 return bfd_mach_arm_6;
13900 case TAG_CPU_ARCH_V6KZ:
13901 return bfd_mach_arm_6KZ;
13902 case TAG_CPU_ARCH_V6T2:
13903 return bfd_mach_arm_6T2;
13904 case TAG_CPU_ARCH_V6K:
13905 return bfd_mach_arm_6K;
13906 case TAG_CPU_ARCH_V7:
13907 return bfd_mach_arm_7;
13908 case TAG_CPU_ARCH_V6_M:
13909 return bfd_mach_arm_6M;
13910 case TAG_CPU_ARCH_V6S_M:
13911 return bfd_mach_arm_6SM;
13912 case TAG_CPU_ARCH_V7E_M:
13913 return bfd_mach_arm_7EM;
13914 case TAG_CPU_ARCH_V8:
13915 return bfd_mach_arm_8;
13916 case TAG_CPU_ARCH_V8R:
13917 return bfd_mach_arm_8R;
13918 case TAG_CPU_ARCH_V8M_BASE:
13919 return bfd_mach_arm_8M_BASE;
13920 case TAG_CPU_ARCH_V8M_MAIN:
13921 return bfd_mach_arm_8M_MAIN;
031254f2
AV		 13922 case TAG_CPU_ARCH_V8_1M_MAIN:
13923 return bfd_mach_arm_8_1M_MAIN;
c0c468d5 13924
5968a7b8 13925 default:
c0c468d5
TP		 13926 /* Force entry to be added for any new known Tag_CPU_arch value. */
13927 BFD_ASSERT (arch > MAX_TAG_CPU_ARCH);
13928
13929 /* Unknown Tag_CPU_arch value. */
5968a7b8
NC		 13930 return bfd_mach_arm_unknown;
13931 }
13932}
13933
c178919b
NC		 13934/* Set the right machine number. */
13935
13936static bfd_boolean
57e8b36a 13937elf32_arm_object_p (bfd *abfd)
c178919b 13938{
5a6c6817 13939 unsigned int mach;
57e8b36a 13940
5a6c6817 13941 mach = bfd_arm_get_mach_from_notes (abfd, ARM_NOTE_SECTION);
c178919b 13942
5968a7b8
NC		 13943 if (mach == bfd_mach_arm_unknown)
13944 {
13945 if (elf_elfheader (abfd)->e_flags & EF_ARM_MAVERICK_FLOAT)
13946 mach = bfd_mach_arm_ep9312;
13947 else
13948 mach = bfd_arm_get_mach_from_attributes (abfd);
13949 }
c178919b 13950
5968a7b8 13951 bfd_default_set_arch_mach (abfd, bfd_arch_arm, mach);
c178919b
NC		 13952 return TRUE;
13953}
13954
fc830a83 13955/* Function to keep ARM specific flags in the ELF header. */
3c9458e9 13956
b34976b6 13957static bfd_boolean
57e8b36a 13958elf32_arm_set_private_flags (bfd *abfd, flagword flags)
252b5132
RH		 13959{
13960 if (elf_flags_init (abfd)
13961 && elf_elfheader (abfd)->e_flags != flags)
13962 {
fc830a83
NC		 13963 if (EF_ARM_EABI_VERSION (flags) == EF_ARM_EABI_UNKNOWN)
13964 {
fd2ec330 13965 if (flags & EF_ARM_INTERWORK)
4eca0228 13966 _bfd_error_handler
90b6238f 13967 (_("warning: not setting interworking flag of %pB since it has already been specified as non-interworking"),
d003868e 13968 abfd);
fc830a83 13969 else
d003868e 13970 _bfd_error_handler
90b6238f 13971 (_("warning: clearing the interworking flag of %pB due to outside request"),
d003868e 13972 abfd);
fc830a83 13973 }
252b5132
RH		 13974 }
13975 else
13976 {
13977 elf_elfheader (abfd)->e_flags = flags;
b34976b6 13978 elf_flags_init (abfd) = TRUE;
252b5132
RH		 13979 }
13980
b34976b6 13981 return TRUE;
252b5132
RH		 13982}
13983
fc830a83 13984/* Copy backend specific data from one object module to another. */
9b485d32 13985
b34976b6 13986static bfd_boolean
57e8b36a 13987elf32_arm_copy_private_bfd_data (bfd *ibfd, bfd *obfd)
252b5132
RH		 13988{
13989 flagword in_flags;
13990 flagword out_flags;
13991
0ffa91dd 13992 if (! is_arm_elf (ibfd) || ! is_arm_elf (obfd))
b34976b6 13993 return TRUE;
252b5132 13994
fc830a83 13995 in_flags = elf_elfheader (ibfd)->e_flags;
252b5132
RH		 13996 out_flags = elf_elfheader (obfd)->e_flags;
13997
fc830a83
NC		 13998 if (elf_flags_init (obfd)
13999 && EF_ARM_EABI_VERSION (out_flags) == EF_ARM_EABI_UNKNOWN
14000 && in_flags != out_flags)
252b5132 14001 {
252b5132 14002 /* Cannot mix APCS26 and APCS32 code. */
fd2ec330 14003 if ((in_flags & EF_ARM_APCS_26) != (out_flags & EF_ARM_APCS_26))
b34976b6 14004 return FALSE;
252b5132
RH		 14005
14006 /* Cannot mix float APCS and non-float APCS code. */
fd2ec330 14007 if ((in_flags & EF_ARM_APCS_FLOAT) != (out_flags & EF_ARM_APCS_FLOAT))
b34976b6 14008 return FALSE;
252b5132
RH		 14009
14010 /* If the src and dest have different interworking flags
99059e56 14011 then turn off the interworking bit. */
fd2ec330 14012 if ((in_flags & EF_ARM_INTERWORK) != (out_flags & EF_ARM_INTERWORK))
252b5132 14013 {
fd2ec330 14014 if (out_flags & EF_ARM_INTERWORK)
d003868e 14015 _bfd_error_handler
90b6238f 14016 (_("warning: clearing the interworking flag of %pB because non-interworking code in %pB has been linked with it"),
d003868e 14017 obfd, ibfd);
252b5132 14018
fd2ec330 14019 in_flags &= ~EF_ARM_INTERWORK;
252b5132 14020 }
1006ba19
PB		 14021
14022 /* Likewise for PIC, though don't warn for this case. */
fd2ec330
PB		 14023 if ((in_flags & EF_ARM_PIC) != (out_flags & EF_ARM_PIC))
14024 in_flags &= ~EF_ARM_PIC;
252b5132
RH		 14025 }
14026
14027 elf_elfheader (obfd)->e_flags = in_flags;
b34976b6 14028 elf_flags_init (obfd) = TRUE;
252b5132 14029
e2349352 14030 return _bfd_elf_copy_private_bfd_data (ibfd, obfd);
ee065d83
PB		 14031}
14032
14033/* Values for Tag_ABI_PCS_R9_use. */
14034enum
14035{
14036 AEABI_R9_V6,
14037 AEABI_R9_SB,
14038 AEABI_R9_TLS,
14039 AEABI_R9_unused
14040};
14041
14042/* Values for Tag_ABI_PCS_RW_data. */
14043enum
14044{
14045 AEABI_PCS_RW_data_absolute,
14046 AEABI_PCS_RW_data_PCrel,
14047 AEABI_PCS_RW_data_SBrel,
14048 AEABI_PCS_RW_data_unused
14049};
14050
14051/* Values for Tag_ABI_enum_size. */
14052enum
14053{
14054 AEABI_enum_unused,
14055 AEABI_enum_short,
14056 AEABI_enum_wide,
14057 AEABI_enum_forced_wide
14058};
14059
104d59d1
JM		 14060/* Determine whether an object attribute tag takes an integer, a
14061 string or both. */
906e58ca 14062
104d59d1
JM		 14063static int
14064elf32_arm_obj_attrs_arg_type (int tag)
14065{
14066 if (tag == Tag_compatibility)
3483fe2e 14067 return ATTR_TYPE_FLAG_INT_VAL | ATTR_TYPE_FLAG_STR_VAL;
2d0bb761 14068 else if (tag == Tag_nodefaults)
3483fe2e
AS		 14069 return ATTR_TYPE_FLAG_INT_VAL | ATTR_TYPE_FLAG_NO_DEFAULT;
14070 else if (tag == Tag_CPU_raw_name || tag == Tag_CPU_name)
14071 return ATTR_TYPE_FLAG_STR_VAL;
104d59d1 14072 else if (tag < 32)
3483fe2e 14073 return ATTR_TYPE_FLAG_INT_VAL;
104d59d1 14074 else
3483fe2e 14075 return (tag & 1) != 0 ? ATTR_TYPE_FLAG_STR_VAL : ATTR_TYPE_FLAG_INT_VAL;
104d59d1
JM		 14076}
14077
5aa6ff7c
AS		 14078/* The ABI defines that Tag_conformance should be emitted first, and that
14079 Tag_nodefaults should be second (if either is defined). This sets those
14080 two positions, and bumps up the position of all the remaining tags to
14081 compensate. */
14082static int
14083elf32_arm_obj_attrs_order (int num)
14084{
3de4a297 14085 if (num == LEAST_KNOWN_OBJ_ATTRIBUTE)
5aa6ff7c 14086 return Tag_conformance;
3de4a297 14087 if (num == LEAST_KNOWN_OBJ_ATTRIBUTE + 1)
5aa6ff7c
AS		 14088 return Tag_nodefaults;
14089 if ((num - 2) < Tag_nodefaults)
14090 return num - 2;
14091 if ((num - 1) < Tag_conformance)
14092 return num - 1;
14093 return num;
14094}
14095
e8b36cd1
JM		 14096/* Attribute numbers >=64 (mod 128) can be safely ignored. */
14097static bfd_boolean
14098elf32_arm_obj_attrs_handle_unknown (bfd *abfd, int tag)
14099{
14100 if ((tag & 127) < 64)
14101 {
14102 _bfd_error_handler
90b6238f 14103 (_("%pB: unknown mandatory EABI object attribute %d"),
e8b36cd1
JM		 14104 abfd, tag);
14105 bfd_set_error (bfd_error_bad_value);
14106 return FALSE;
14107 }
14108 else
14109 {
14110 _bfd_error_handler
90b6238f 14111 (_("warning: %pB: unknown EABI object attribute %d"),
e8b36cd1
JM		 14112 abfd, tag);
14113 return TRUE;
14114 }
14115}
14116
91e22acd
AS		 14117/* Read the architecture from the Tag_also_compatible_with attribute, if any.
14118 Returns -1 if no architecture could be read. */
14119
14120static int
14121get_secondary_compatible_arch (bfd *abfd)
14122{
14123 obj_attribute *attr =
14124 &elf_known_obj_attributes_proc (abfd)[Tag_also_compatible_with];
14125
14126 /* Note: the tag and its argument below are uleb128 values, though
14127 currently-defined values fit in one byte for each. */
14128 if (attr->s
14129 && attr->s[0] == Tag_CPU_arch
14130 && (attr->s[1] & 128) != 128
14131 && attr->s[2] == 0)
14132 return attr->s[1];
14133
14134 /* This tag is "safely ignorable", so don't complain if it looks funny. */
14135 return -1;
14136}
14137
14138/* Set, or unset, the architecture of the Tag_also_compatible_with attribute.
14139 The tag is removed if ARCH is -1. */
14140
8e79c3df 14141static void
91e22acd 14142set_secondary_compatible_arch (bfd *abfd, int arch)
8e79c3df 14143{
91e22acd
AS		 14144 obj_attribute *attr =
14145 &elf_known_obj_attributes_proc (abfd)[Tag_also_compatible_with];
8e79c3df 14146
91e22acd
AS		 14147 if (arch == -1)
14148 {
14149 attr->s = NULL;
14150 return;
8e79c3df 14151 }
91e22acd
AS		 14152
14153 /* Note: the tag and its argument below are uleb128 values, though
14154 currently-defined values fit in one byte for each. */
14155 if (!attr->s)
21d799b5 14156 attr->s = (char *) bfd_alloc (abfd, 3);
91e22acd
AS		 14157 attr->s[0] = Tag_CPU_arch;
14158 attr->s[1] = arch;
14159 attr->s[2] = '\0';
8e79c3df
CM		 14160}
14161
91e22acd
AS		 14162/* Combine two values for Tag_CPU_arch, taking secondary compatibility tags
14163 into account. */
14164
14165static int
14166tag_cpu_arch_combine (bfd *ibfd, int oldtag, int *secondary_compat_out,
14167 int newtag, int secondary_compat)
8e79c3df 14168{
91e22acd
AS		 14169#define T(X) TAG_CPU_ARCH_##X
14170 int tagl, tagh, result;
14171 const int v6t2[] =
14172 {
14173 T(V6T2), /* PRE_V4. */
14174 T(V6T2), /* V4. */
14175 T(V6T2), /* V4T. */
14176 T(V6T2), /* V5T. */
14177 T(V6T2), /* V5TE. */
14178 T(V6T2), /* V5TEJ. */
14179 T(V6T2), /* V6. */
14180 T(V7), /* V6KZ. */
14181 T(V6T2) /* V6T2. */
14182 };
14183 const int v6k[] =
14184 {
14185 T(V6K), /* PRE_V4. */
14186 T(V6K), /* V4. */
14187 T(V6K), /* V4T. */
14188 T(V6K), /* V5T. */
14189 T(V6K), /* V5TE. */
14190 T(V6K), /* V5TEJ. */
14191 T(V6K), /* V6. */
14192 T(V6KZ), /* V6KZ. */
14193 T(V7), /* V6T2. */
14194 T(V6K) /* V6K. */
14195 };
14196 const int v7[] =
14197 {
14198 T(V7), /* PRE_V4. */
14199 T(V7), /* V4. */
14200 T(V7), /* V4T. */
14201 T(V7), /* V5T. */
14202 T(V7), /* V5TE. */
14203 T(V7), /* V5TEJ. */
14204 T(V7), /* V6. */
14205 T(V7), /* V6KZ. */
14206 T(V7), /* V6T2. */
14207 T(V7), /* V6K. */
14208 T(V7) /* V7. */
14209 };
14210 const int v6_m[] =
14211 {
07d6d2b8
AM		 14212 -1, /* PRE_V4. */
14213 -1, /* V4. */
91e22acd
AS		 14214 T(V6K), /* V4T. */
14215 T(V6K), /* V5T. */
14216 T(V6K), /* V5TE. */
14217 T(V6K), /* V5TEJ. */
14218 T(V6K), /* V6. */
14219 T(V6KZ), /* V6KZ. */
14220 T(V7), /* V6T2. */
14221 T(V6K), /* V6K. */
14222 T(V7), /* V7. */
14223 T(V6_M) /* V6_M. */
14224 };
14225 const int v6s_m[] =
14226 {
07d6d2b8
AM		 14227 -1, /* PRE_V4. */
14228 -1, /* V4. */
91e22acd
AS		 14229 T(V6K), /* V4T. */
14230 T(V6K), /* V5T. */
14231 T(V6K), /* V5TE. */
14232 T(V6K), /* V5TEJ. */
14233 T(V6K), /* V6. */
14234 T(V6KZ), /* V6KZ. */
14235 T(V7), /* V6T2. */
14236 T(V6K), /* V6K. */
14237 T(V7), /* V7. */
14238 T(V6S_M), /* V6_M. */
14239 T(V6S_M) /* V6S_M. */
14240 };
9e3c6df6
PB		 14241 const int v7e_m[] =
14242 {
07d6d2b8
AM		 14243 -1, /* PRE_V4. */
14244 -1, /* V4. */
9e3c6df6
PB		 14245 T(V7E_M), /* V4T. */
14246 T(V7E_M), /* V5T. */
14247 T(V7E_M), /* V5TE. */
14248 T(V7E_M), /* V5TEJ. */
14249 T(V7E_M), /* V6. */
14250 T(V7E_M), /* V6KZ. */
14251 T(V7E_M), /* V6T2. */
14252 T(V7E_M), /* V6K. */
14253 T(V7E_M), /* V7. */
14254 T(V7E_M), /* V6_M. */
14255 T(V7E_M), /* V6S_M. */
14256 T(V7E_M) /* V7E_M. */
14257 };
bca38921
MGD		 14258 const int v8[] =
14259 {
14260 T(V8), /* PRE_V4. */
14261 T(V8), /* V4. */
14262 T(V8), /* V4T. */
14263 T(V8), /* V5T. */
14264 T(V8), /* V5TE. */
14265 T(V8), /* V5TEJ. */
14266 T(V8), /* V6. */
14267 T(V8), /* V6KZ. */
14268 T(V8), /* V6T2. */
14269 T(V8), /* V6K. */
14270 T(V8), /* V7. */
14271 T(V8), /* V6_M. */
14272 T(V8), /* V6S_M. */
14273 T(V8), /* V7E_M. */
14274 T(V8) /* V8. */
14275 };
bff0500d
TP		 14276 const int v8r[] =
14277 {
14278 T(V8R), /* PRE_V4. */
14279 T(V8R), /* V4. */
14280 T(V8R), /* V4T. */
14281 T(V8R), /* V5T. */
14282 T(V8R), /* V5TE. */
14283 T(V8R), /* V5TEJ. */
14284 T(V8R), /* V6. */
14285 T(V8R), /* V6KZ. */
14286 T(V8R), /* V6T2. */
14287 T(V8R), /* V6K. */
14288 T(V8R), /* V7. */
14289 T(V8R), /* V6_M. */
14290 T(V8R), /* V6S_M. */
14291 T(V8R), /* V7E_M. */
14292 T(V8), /* V8. */
14293 T(V8R), /* V8R. */
14294 };
2fd158eb
TP		 14295 const int v8m_baseline[] =
14296 {
14297 -1, /* PRE_V4. */
14298 -1, /* V4. */
14299 -1, /* V4T. */
14300 -1, /* V5T. */
14301 -1, /* V5TE. */
14302 -1, /* V5TEJ. */
14303 -1, /* V6. */
14304 -1, /* V6KZ. */
14305 -1, /* V6T2. */
14306 -1, /* V6K. */
14307 -1, /* V7. */
14308 T(V8M_BASE), /* V6_M. */
14309 T(V8M_BASE), /* V6S_M. */
14310 -1, /* V7E_M. */
14311 -1, /* V8. */
bff0500d 14312 -1, /* V8R. */
2fd158eb
TP		 14313 T(V8M_BASE) /* V8-M BASELINE. */
14314 };
14315 const int v8m_mainline[] =
14316 {
14317 -1, /* PRE_V4. */
14318 -1, /* V4. */
14319 -1, /* V4T. */
14320 -1, /* V5T. */
14321 -1, /* V5TE. */
14322 -1, /* V5TEJ. */
14323 -1, /* V6. */
14324 -1, /* V6KZ. */
14325 -1, /* V6T2. */
14326 -1, /* V6K. */
14327 T(V8M_MAIN), /* V7. */
14328 T(V8M_MAIN), /* V6_M. */
14329 T(V8M_MAIN), /* V6S_M. */
14330 T(V8M_MAIN), /* V7E_M. */
14331 -1, /* V8. */
bff0500d 14332 -1, /* V8R. */
2fd158eb
TP		 14333 T(V8M_MAIN), /* V8-M BASELINE. */
14334 T(V8M_MAIN) /* V8-M MAINLINE. */
14335 };
031254f2
AV		 14336 const int v8_1m_mainline[] =
14337 {
14338 -1, /* PRE_V4. */
14339 -1, /* V4. */
14340 -1, /* V4T. */
14341 -1, /* V5T. */
14342 -1, /* V5TE. */
14343 -1, /* V5TEJ. */
14344 -1, /* V6. */
14345 -1, /* V6KZ. */
14346 -1, /* V6T2. */
14347 -1, /* V6K. */
14348 T(V8_1M_MAIN), /* V7. */
14349 T(V8_1M_MAIN), /* V6_M. */
14350 T(V8_1M_MAIN), /* V6S_M. */
14351 T(V8_1M_MAIN), /* V7E_M. */
14352 -1, /* V8. */
14353 -1, /* V8R. */
14354 T(V8_1M_MAIN), /* V8-M BASELINE. */
14355 T(V8_1M_MAIN), /* V8-M MAINLINE. */
14356 -1, /* Unused (18). */
14357 -1, /* Unused (19). */
14358 -1, /* Unused (20). */
14359 T(V8_1M_MAIN) /* V8.1-M MAINLINE. */
14360 };
91e22acd
AS		 14361 const int v4t_plus_v6_m[] =
14362 {
14363 -1, /* PRE_V4. */
14364 -1, /* V4. */
14365 T(V4T), /* V4T. */
14366 T(V5T), /* V5T. */
14367 T(V5TE), /* V5TE. */
14368 T(V5TEJ), /* V5TEJ. */
14369 T(V6), /* V6. */
14370 T(V6KZ), /* V6KZ. */
14371 T(V6T2), /* V6T2. */
14372 T(V6K), /* V6K. */
14373 T(V7), /* V7. */
14374 T(V6_M), /* V6_M. */
14375 T(V6S_M), /* V6S_M. */
9e3c6df6 14376 T(V7E_M), /* V7E_M. */
bca38921 14377 T(V8), /* V8. */
bff0500d 14378 -1, /* V8R. */
2fd158eb
TP		 14379 T(V8M_BASE), /* V8-M BASELINE. */
14380 T(V8M_MAIN), /* V8-M MAINLINE. */
031254f2
AV		 14381 -1, /* Unused (18). */
14382 -1, /* Unused (19). */
14383 -1, /* Unused (20). */
14384 T(V8_1M_MAIN), /* V8.1-M MAINLINE. */
91e22acd
AS		 14385 T(V4T_PLUS_V6_M) /* V4T plus V6_M. */
14386 };
14387 const int *comb[] =
14388 {
14389 v6t2,
14390 v6k,
14391 v7,
14392 v6_m,
14393 v6s_m,
9e3c6df6 14394 v7e_m,
bca38921 14395 v8,
bff0500d 14396 v8r,
2fd158eb
TP		 14397 v8m_baseline,
14398 v8m_mainline,
031254f2
AV		 14399 NULL,
14400 NULL,
14401 NULL,
14402 v8_1m_mainline,
91e22acd
AS		 14403 /* Pseudo-architecture. */
14404 v4t_plus_v6_m
14405 };
14406
14407 /* Check we've not got a higher architecture than we know about. */
14408
9e3c6df6 14409 if (oldtag > MAX_TAG_CPU_ARCH || newtag > MAX_TAG_CPU_ARCH)
91e22acd 14410 {
90b6238f 14411 _bfd_error_handler (_("error: %pB: unknown CPU architecture"), ibfd);
91e22acd
AS		 14412 return -1;
14413 }
14414
14415 /* Override old tag if we have a Tag_also_compatible_with on the output. */
14416
14417 if ((oldtag == T(V6_M) && *secondary_compat_out == T(V4T))
14418 || (oldtag == T(V4T) && *secondary_compat_out == T(V6_M)))
14419 oldtag = T(V4T_PLUS_V6_M);
14420
14421 /* And override the new tag if we have a Tag_also_compatible_with on the
14422 input. */
14423
14424 if ((newtag == T(V6_M) && secondary_compat == T(V4T))
14425 || (newtag == T(V4T) && secondary_compat == T(V6_M)))
14426 newtag = T(V4T_PLUS_V6_M);
14427
14428 tagl = (oldtag < newtag) ? oldtag : newtag;
14429 result = tagh = (oldtag > newtag) ? oldtag : newtag;
14430
14431 /* Architectures before V6KZ add features monotonically. */
14432 if (tagh <= TAG_CPU_ARCH_V6KZ)
14433 return result;
14434
4ed7ed8d 14435 result = comb[tagh - T(V6T2)] ? comb[tagh - T(V6T2)][tagl] : -1;
91e22acd
AS		 14436
14437 /* Use Tag_CPU_arch == V4T and Tag_also_compatible_with (Tag_CPU_arch V6_M)
14438 as the canonical version. */
14439 if (result == T(V4T_PLUS_V6_M))
14440 {
14441 result = T(V4T);
14442 *secondary_compat_out = T(V6_M);
14443 }
14444 else
14445 *secondary_compat_out = -1;
14446
14447 if (result == -1)
14448 {
90b6238f 14449 _bfd_error_handler (_("error: %pB: conflicting CPU architectures %d/%d"),
91e22acd
AS		 14450 ibfd, oldtag, newtag);
14451 return -1;
14452 }
14453
14454 return result;
14455#undef T
8e79c3df
CM		 14456}
14457
ac56ee8f
MGD		 14458/* Query attributes object to see if integer divide instructions may be
14459 present in an object. */
14460static bfd_boolean
14461elf32_arm_attributes_accept_div (const obj_attribute *attr)
14462{
14463 int arch = attr[Tag_CPU_arch].i;
14464 int profile = attr[Tag_CPU_arch_profile].i;
14465
14466 switch (attr[Tag_DIV_use].i)
14467 {
14468 case 0:
14469 /* Integer divide allowed if instruction contained in archetecture. */
14470 if (arch == TAG_CPU_ARCH_V7 && (profile == 'R' || profile == 'M'))
14471 return TRUE;
14472 else if (arch >= TAG_CPU_ARCH_V7E_M)
14473 return TRUE;
14474 else
14475 return FALSE;
14476
14477 case 1:
14478 /* Integer divide explicitly prohibited. */
14479 return FALSE;
14480
14481 default:
14482 /* Unrecognised case - treat as allowing divide everywhere. */
14483 case 2:
14484 /* Integer divide allowed in ARM state. */
14485 return TRUE;
14486 }
14487}
14488
14489/* Query attributes object to see if integer divide instructions are
14490 forbidden to be in the object. This is not the inverse of
14491 elf32_arm_attributes_accept_div. */
14492static bfd_boolean
14493elf32_arm_attributes_forbid_div (const obj_attribute *attr)
14494{
14495 return attr[Tag_DIV_use].i == 1;
14496}
14497
ee065d83
PB		 14498/* Merge EABI object attributes from IBFD into OBFD. Raise an error if there
14499 are conflicting attributes. */
906e58ca 14500
ee065d83 14501static bfd_boolean
50e03d47 14502elf32_arm_merge_eabi_attributes (bfd *ibfd, struct bfd_link_info *info)
ee065d83 14503{
50e03d47 14504 bfd *obfd = info->output_bfd;
104d59d1
JM		 14505 obj_attribute *in_attr;
14506 obj_attribute *out_attr;
ee065d83
PB		 14507 /* Some tags have 0 = don't care, 1 = strong requirement,
14508 2 = weak requirement. */
91e22acd 14509 static const int order_021[3] = {0, 2, 1};
ee065d83 14510 int i;
91e22acd 14511 bfd_boolean result = TRUE;
9274e9de 14512 const char *sec_name = get_elf_backend_data (ibfd)->obj_attrs_section;
ee065d83 14513
3e6b1042
DJ		 14514 /* Skip the linker stubs file. This preserves previous behavior
14515 of accepting unknown attributes in the first input file - but
14516 is that a bug? */
14517 if (ibfd->flags & BFD_LINKER_CREATED)
14518 return TRUE;
14519
9274e9de
TG		 14520 /* Skip any input that hasn't attribute section.
14521 This enables to link object files without attribute section with
14522 any others. */
14523 if (bfd_get_section_by_name (ibfd, sec_name) == NULL)
14524 return TRUE;
14525
104d59d1 14526 if (!elf_known_obj_attributes_proc (obfd)[0].i)
ee065d83
PB		 14527 {
14528 /* This is the first object. Copy the attributes. */
104d59d1 14529 _bfd_elf_copy_obj_attributes (ibfd, obfd);
004ae526 14530
cd21e546
MGD		 14531 out_attr = elf_known_obj_attributes_proc (obfd);
14532
004ae526
PB		 14533 /* Use the Tag_null value to indicate the attributes have been
14534 initialized. */
cd21e546 14535 out_attr[0].i = 1;
004ae526 14536
cd21e546
MGD		 14537 /* We do not output objects with Tag_MPextension_use_legacy - we move
14538 the attribute's value to Tag_MPextension_use. */
14539 if (out_attr[Tag_MPextension_use_legacy].i != 0)
14540 {
14541 if (out_attr[Tag_MPextension_use].i != 0
14542 && out_attr[Tag_MPextension_use_legacy].i
99059e56 14543 != out_attr[Tag_MPextension_use].i)
cd21e546
MGD		 14544 {
14545 _bfd_error_handler
871b3ab2 14546 (_("Error: %pB has both the current and legacy "
cd21e546
MGD		 14547 "Tag_MPextension_use attributes"), ibfd);
14548 result = FALSE;
14549 }
14550
14551 out_attr[Tag_MPextension_use] =
14552 out_attr[Tag_MPextension_use_legacy];
14553 out_attr[Tag_MPextension_use_legacy].type = 0;
14554 out_attr[Tag_MPextension_use_legacy].i = 0;
14555 }
14556
14557 return result;
ee065d83
PB		 14558 }
14559
104d59d1
JM		 14560 in_attr = elf_known_obj_attributes_proc (ibfd);
14561 out_attr = elf_known_obj_attributes_proc (obfd);
ee065d83
PB		 14562 /* This needs to happen before Tag_ABI_FP_number_model is merged. */
14563 if (in_attr[Tag_ABI_VFP_args].i != out_attr[Tag_ABI_VFP_args].i)
14564 {
5c294fee
TG		 14565 /* Ignore mismatches if the object doesn't use floating point or is
14566 floating point ABI independent. */
14567 if (out_attr[Tag_ABI_FP_number_model].i == AEABI_FP_number_model_none
14568 || (in_attr[Tag_ABI_FP_number_model].i != AEABI_FP_number_model_none
14569 && out_attr[Tag_ABI_VFP_args].i == AEABI_VFP_args_compatible))
ee065d83 14570 out_attr[Tag_ABI_VFP_args].i = in_attr[Tag_ABI_VFP_args].i;
5c294fee
TG		 14571 else if (in_attr[Tag_ABI_FP_number_model].i != AEABI_FP_number_model_none
14572 && in_attr[Tag_ABI_VFP_args].i != AEABI_VFP_args_compatible)
ee065d83
PB		 14573 {
14574 _bfd_error_handler
871b3ab2 14575 (_("error: %pB uses VFP register arguments, %pB does not"),
deddc40b
NS		 14576 in_attr[Tag_ABI_VFP_args].i ? ibfd : obfd,
14577 in_attr[Tag_ABI_VFP_args].i ? obfd : ibfd);
91e22acd 14578 result = FALSE;
ee065d83
PB		 14579 }
14580 }
14581
3de4a297 14582 for (i = LEAST_KNOWN_OBJ_ATTRIBUTE; i < NUM_KNOWN_OBJ_ATTRIBUTES; i++)
ee065d83
PB		 14583 {
14584 /* Merge this attribute with existing attributes. */
14585 switch (i)
14586 {
14587 case Tag_CPU_raw_name:
14588 case Tag_CPU_name:
6a631e86 14589 /* These are merged after Tag_CPU_arch. */
ee065d83
PB		 14590 break;
14591
14592 case Tag_ABI_optimization_goals:
14593 case Tag_ABI_FP_optimization_goals:
14594 /* Use the first value seen. */
14595 break;
14596
14597 case Tag_CPU_arch:
91e22acd
AS		 14598 {
14599 int secondary_compat = -1, secondary_compat_out = -1;
14600 unsigned int saved_out_attr = out_attr[i].i;
70e99720
TG		 14601 int arch_attr;
14602 static const char *name_table[] =
14603 {
91e22acd
AS		 14604 /* These aren't real CPU names, but we can't guess
14605 that from the architecture version alone. */
14606 "Pre v4",
14607 "ARM v4",
14608 "ARM v4T",
14609 "ARM v5T",
14610 "ARM v5TE",
14611 "ARM v5TEJ",
14612 "ARM v6",
14613 "ARM v6KZ",
14614 "ARM v6T2",
14615 "ARM v6K",
14616 "ARM v7",
14617 "ARM v6-M",
bca38921 14618 "ARM v6S-M",
2fd158eb
TP		 14619 "ARM v8",
14620 "",
14621 "ARM v8-M.baseline",
14622 "ARM v8-M.mainline",
91e22acd
AS		 14623 };
14624
14625 /* Merge Tag_CPU_arch and Tag_also_compatible_with. */
14626 secondary_compat = get_secondary_compatible_arch (ibfd);
14627 secondary_compat_out = get_secondary_compatible_arch (obfd);
70e99720
TG		 14628 arch_attr = tag_cpu_arch_combine (ibfd, out_attr[i].i,
14629 &secondary_compat_out,
14630 in_attr[i].i,
14631 secondary_compat);
14632
14633 /* Return with error if failed to merge. */
14634 if (arch_attr == -1)
14635 return FALSE;
14636
14637 out_attr[i].i = arch_attr;
14638
91e22acd
AS		 14639 set_secondary_compatible_arch (obfd, secondary_compat_out);
14640
14641 /* Merge Tag_CPU_name and Tag_CPU_raw_name. */
14642 if (out_attr[i].i == saved_out_attr)
14643 ; /* Leave the names alone. */
14644 else if (out_attr[i].i == in_attr[i].i)
14645 {
14646 /* The output architecture has been changed to match the
14647 input architecture. Use the input names. */
14648 out_attr[Tag_CPU_name].s = in_attr[Tag_CPU_name].s
14649 ? _bfd_elf_attr_strdup (obfd, in_attr[Tag_CPU_name].s)
14650 : NULL;
14651 out_attr[Tag_CPU_raw_name].s = in_attr[Tag_CPU_raw_name].s
14652 ? _bfd_elf_attr_strdup (obfd, in_attr[Tag_CPU_raw_name].s)
14653 : NULL;
14654 }
14655 else
14656 {
14657 out_attr[Tag_CPU_name].s = NULL;
14658 out_attr[Tag_CPU_raw_name].s = NULL;
14659 }
14660
14661 /* If we still don't have a value for Tag_CPU_name,
14662 make one up now. Tag_CPU_raw_name remains blank. */
14663 if (out_attr[Tag_CPU_name].s == NULL
14664 && out_attr[i].i < ARRAY_SIZE (name_table))
14665 out_attr[Tag_CPU_name].s =
14666 _bfd_elf_attr_strdup (obfd, name_table[out_attr[i].i]);
14667 }
14668 break;
14669
ee065d83
PB		 14670 case Tag_ARM_ISA_use:
14671 case Tag_THUMB_ISA_use:
ee065d83 14672 case Tag_WMMX_arch:
91e22acd
AS		 14673 case Tag_Advanced_SIMD_arch:
14674 /* ??? Do Advanced_SIMD (NEON) and WMMX conflict? */
ee065d83 14675 case Tag_ABI_FP_rounding:
ee065d83
PB		 14676 case Tag_ABI_FP_exceptions:
14677 case Tag_ABI_FP_user_exceptions:
14678 case Tag_ABI_FP_number_model:
75375b3e 14679 case Tag_FP_HP_extension:
91e22acd
AS		 14680 case Tag_CPU_unaligned_access:
14681 case Tag_T2EE_use:
91e22acd 14682 case Tag_MPextension_use:
a7ad558c 14683 case Tag_MVE_arch:
ee065d83
PB		 14684 /* Use the largest value specified. */
14685 if (in_attr[i].i > out_attr[i].i)
14686 out_attr[i].i = in_attr[i].i;
14687 break;
14688
75375b3e 14689 case Tag_ABI_align_preserved:
91e22acd
AS		 14690 case Tag_ABI_PCS_RO_data:
14691 /* Use the smallest value specified. */
14692 if (in_attr[i].i < out_attr[i].i)
14693 out_attr[i].i = in_attr[i].i;
14694 break;
14695
75375b3e 14696 case Tag_ABI_align_needed:
91e22acd 14697 if ((in_attr[i].i > 0 || out_attr[i].i > 0)
75375b3e
MGD		 14698 && (in_attr[Tag_ABI_align_preserved].i == 0
14699 || out_attr[Tag_ABI_align_preserved].i == 0))
ee065d83 14700 {
91e22acd
AS		 14701 /* This error message should be enabled once all non-conformant
14702 binaries in the toolchain have had the attributes set
14703 properly.
ee065d83 14704 _bfd_error_handler
871b3ab2 14705 (_("error: %pB: 8-byte data alignment conflicts with %pB"),
91e22acd
AS		 14706 obfd, ibfd);
14707 result = FALSE; */
ee065d83 14708 }
91e22acd
AS		 14709 /* Fall through. */
14710 case Tag_ABI_FP_denormal:
14711 case Tag_ABI_PCS_GOT_use:
14712 /* Use the "greatest" from the sequence 0, 2, 1, or the largest
14713 value if greater than 2 (for future-proofing). */
14714 if ((in_attr[i].i > 2 && in_attr[i].i > out_attr[i].i)
14715 || (in_attr[i].i <= 2 && out_attr[i].i <= 2
14716 && order_021[in_attr[i].i] > order_021[out_attr[i].i]))
ee065d83
PB		 14717 out_attr[i].i = in_attr[i].i;
14718 break;
91e22acd 14719
75375b3e
MGD		 14720 case Tag_Virtualization_use:
14721 /* The virtualization tag effectively stores two bits of
14722 information: the intended use of TrustZone (in bit 0), and the
14723 intended use of Virtualization (in bit 1). */
14724 if (out_attr[i].i == 0)
14725 out_attr[i].i = in_attr[i].i;
14726 else if (in_attr[i].i != 0
14727 && in_attr[i].i != out_attr[i].i)
14728 {
14729 if (in_attr[i].i <= 3 && out_attr[i].i <= 3)
14730 out_attr[i].i = 3;
14731 else
14732 {
14733 _bfd_error_handler
871b3ab2
AM		 14734 (_("error: %pB: unable to merge virtualization attributes "
14735 "with %pB"),
75375b3e
MGD		 14736 obfd, ibfd);
14737 result = FALSE;
14738 }
14739 }
14740 break;
91e22acd
AS		 14741
14742 case Tag_CPU_arch_profile:
14743 if (out_attr[i].i != in_attr[i].i)
14744 {
14745 /* 0 will merge with anything.
14746 'A' and 'S' merge to 'A'.
14747 'R' and 'S' merge to 'R'.
99059e56 14748 'M' and 'A|R|S' is an error. */
91e22acd
AS		 14749 if (out_attr[i].i == 0
14750 || (out_attr[i].i == 'S'
14751 && (in_attr[i].i == 'A' || in_attr[i].i == 'R')))
14752 out_attr[i].i = in_attr[i].i;
14753 else if (in_attr[i].i == 0
14754 || (in_attr[i].i == 'S'
14755 && (out_attr[i].i == 'A' || out_attr[i].i == 'R')))
6a631e86 14756 ; /* Do nothing. */
91e22acd
AS		 14757 else
14758 {
14759 _bfd_error_handler
90b6238f 14760 (_("error: %pB: conflicting architecture profiles %c/%c"),
91e22acd
AS		 14761 ibfd,
14762 in_attr[i].i ? in_attr[i].i : '0',
14763 out_attr[i].i ? out_attr[i].i : '0');
14764 result = FALSE;
14765 }
14766 }
14767 break;
15afaa63
TP		 14768
14769 case Tag_DSP_extension:
14770 /* No need to change output value if any of:
14771 - pre (<=) ARMv5T input architecture (do not have DSP)
14772 - M input profile not ARMv7E-M and do not have DSP. */
14773 if (in_attr[Tag_CPU_arch].i <= 3
14774 || (in_attr[Tag_CPU_arch_profile].i == 'M'
14775 && in_attr[Tag_CPU_arch].i != 13
14776 && in_attr[i].i == 0))
14777 ; /* Do nothing. */
14778 /* Output value should be 0 if DSP part of architecture, ie.
14779 - post (>=) ARMv5te architecture output
14780 - A, R or S profile output or ARMv7E-M output architecture. */
14781 else if (out_attr[Tag_CPU_arch].i >= 4
14782 && (out_attr[Tag_CPU_arch_profile].i == 'A'
14783 || out_attr[Tag_CPU_arch_profile].i == 'R'
14784 || out_attr[Tag_CPU_arch_profile].i == 'S'
14785 || out_attr[Tag_CPU_arch].i == 13))
14786 out_attr[i].i = 0;
14787 /* Otherwise, DSP instructions are added and not part of output
14788 architecture. */
14789 else
14790 out_attr[i].i = 1;
14791 break;
14792
75375b3e 14793 case Tag_FP_arch:
62f3b8c8 14794 {
4547cb56
NC		 14795 /* Tag_ABI_HardFP_use is handled along with Tag_FP_arch since
14796 the meaning of Tag_ABI_HardFP_use depends on Tag_FP_arch
14797 when it's 0. It might mean absence of FP hardware if
99654aaf 14798 Tag_FP_arch is zero. */
4547cb56 14799
a715796b 14800#define VFP_VERSION_COUNT 9
62f3b8c8
PB		 14801 static const struct
14802 {
14803 int ver;
14804 int regs;
bca38921 14805 } vfp_versions[VFP_VERSION_COUNT] =
62f3b8c8
PB		 14806 {
14807 {0, 0},
14808 {1, 16},
14809 {2, 16},
14810 {3, 32},
14811 {3, 16},
14812 {4, 32},
bca38921 14813 {4, 16},
a715796b
TG		 14814 {8, 32},
14815 {8, 16}
62f3b8c8
PB		 14816 };
14817 int ver;
14818 int regs;
14819 int newval;
14820
4547cb56
NC		 14821 /* If the output has no requirement about FP hardware,
14822 follow the requirement of the input. */
14823 if (out_attr[i].i == 0)
14824 {
4ec192e6
RE		 14825 /* This assert is still reasonable, we shouldn't
14826 produce the suspicious build attribute
14827 combination (See below for in_attr). */
4547cb56
NC		 14828 BFD_ASSERT (out_attr[Tag_ABI_HardFP_use].i == 0);
14829 out_attr[i].i = in_attr[i].i;
14830 out_attr[Tag_ABI_HardFP_use].i
14831 = in_attr[Tag_ABI_HardFP_use].i;
14832 break;
14833 }
14834 /* If the input has no requirement about FP hardware, do
14835 nothing. */
14836 else if (in_attr[i].i == 0)
14837 {
4ec192e6
RE		 14838 /* We used to assert that Tag_ABI_HardFP_use was
14839 zero here, but we should never assert when
14840 consuming an object file that has suspicious
14841 build attributes. The single precision variant
14842 of 'no FP architecture' is still 'no FP
14843 architecture', so we just ignore the tag in this
14844 case. */
4547cb56
NC		 14845 break;
14846 }
14847
14848 /* Both the input and the output have nonzero Tag_FP_arch.
99654aaf 14849 So Tag_ABI_HardFP_use is implied by Tag_FP_arch when it's zero. */
4547cb56
NC		 14850
14851 /* If both the input and the output have zero Tag_ABI_HardFP_use,
14852 do nothing. */
14853 if (in_attr[Tag_ABI_HardFP_use].i == 0
14854 && out_attr[Tag_ABI_HardFP_use].i == 0)
14855 ;
14856 /* If the input and the output have different Tag_ABI_HardFP_use,
99654aaf 14857 the combination of them is 0 (implied by Tag_FP_arch). */
4547cb56
NC		 14858 else if (in_attr[Tag_ABI_HardFP_use].i
14859 != out_attr[Tag_ABI_HardFP_use].i)
99654aaf 14860 out_attr[Tag_ABI_HardFP_use].i = 0;
4547cb56
NC		 14861
14862 /* Now we can handle Tag_FP_arch. */
14863
bca38921
MGD		 14864 /* Values of VFP_VERSION_COUNT or more aren't defined, so just
14865 pick the biggest. */
14866 if (in_attr[i].i >= VFP_VERSION_COUNT
14867 && in_attr[i].i > out_attr[i].i)
62f3b8c8
PB		 14868 {
14869 out_attr[i] = in_attr[i];
14870 break;
14871 }
14872 /* The output uses the superset of input features
14873 (ISA version) and registers. */
14874 ver = vfp_versions[in_attr[i].i].ver;
14875 if (ver < vfp_versions[out_attr[i].i].ver)
14876 ver = vfp_versions[out_attr[i].i].ver;
14877 regs = vfp_versions[in_attr[i].i].regs;
14878 if (regs < vfp_versions[out_attr[i].i].regs)
14879 regs = vfp_versions[out_attr[i].i].regs;
14880 /* This assumes all possible supersets are also a valid
99059e56 14881 options. */
bca38921 14882 for (newval = VFP_VERSION_COUNT - 1; newval > 0; newval--)
62f3b8c8
PB		 14883 {
14884 if (regs == vfp_versions[newval].regs
14885 && ver == vfp_versions[newval].ver)
14886 break;
14887 }
14888 out_attr[i].i = newval;
14889 }
b1cc4aeb 14890 break;
ee065d83
PB		 14891 case Tag_PCS_config:
14892 if (out_attr[i].i == 0)
14893 out_attr[i].i = in_attr[i].i;
b6009aca 14894 else if (in_attr[i].i != 0 && out_attr[i].i != in_attr[i].i)
ee065d83
PB		 14895 {
14896 /* It's sometimes ok to mix different configs, so this is only
99059e56 14897 a warning. */
ee065d83 14898 _bfd_error_handler
90b6238f 14899 (_("warning: %pB: conflicting platform configuration"), ibfd);
ee065d83
PB		 14900 }
14901 break;
14902 case Tag_ABI_PCS_R9_use:
004ae526
PB		 14903 if (in_attr[i].i != out_attr[i].i
14904 && out_attr[i].i != AEABI_R9_unused
ee065d83
PB		 14905 && in_attr[i].i != AEABI_R9_unused)
14906 {
14907 _bfd_error_handler
90b6238f 14908 (_("error: %pB: conflicting use of R9"), ibfd);
91e22acd 14909 result = FALSE;
ee065d83
PB		 14910 }
14911 if (out_attr[i].i == AEABI_R9_unused)
14912 out_attr[i].i = in_attr[i].i;
14913 break;
14914 case Tag_ABI_PCS_RW_data:
14915 if (in_attr[i].i == AEABI_PCS_RW_data_SBrel
14916 && out_attr[Tag_ABI_PCS_R9_use].i != AEABI_R9_SB
14917 && out_attr[Tag_ABI_PCS_R9_use].i != AEABI_R9_unused)
14918 {
14919 _bfd_error_handler
871b3ab2 14920 (_("error: %pB: SB relative addressing conflicts with use of R9"),
ee065d83 14921 ibfd);
91e22acd 14922 result = FALSE;
ee065d83
PB		 14923 }
14924 /* Use the smallest value specified. */
14925 if (in_attr[i].i < out_attr[i].i)
14926 out_attr[i].i = in_attr[i].i;
14927 break;
ee065d83 14928 case Tag_ABI_PCS_wchar_t:
a9dc9481
JM		 14929 if (out_attr[i].i && in_attr[i].i && out_attr[i].i != in_attr[i].i
14930 && !elf_arm_tdata (obfd)->no_wchar_size_warning)
ee065d83
PB		 14931 {
14932 _bfd_error_handler
871b3ab2 14933 (_("warning: %pB uses %u-byte wchar_t yet the output is to use %u-byte wchar_t; use of wchar_t values across objects may fail"),
a9dc9481 14934 ibfd, in_attr[i].i, out_attr[i].i);
ee065d83 14935 }
a9dc9481 14936 else if (in_attr[i].i && !out_attr[i].i)
ee065d83
PB		 14937 out_attr[i].i = in_attr[i].i;
14938 break;
ee065d83
PB		 14939 case Tag_ABI_enum_size:
14940 if (in_attr[i].i != AEABI_enum_unused)
14941 {
14942 if (out_attr[i].i == AEABI_enum_unused
14943 || out_attr[i].i == AEABI_enum_forced_wide)
14944 {
14945 /* The existing object is compatible with anything.
14946 Use whatever requirements the new object has. */
14947 out_attr[i].i = in_attr[i].i;
14948 }
14949 else if (in_attr[i].i != AEABI_enum_forced_wide
bf21ed78 14950 && out_attr[i].i != in_attr[i].i
0ffa91dd 14951 && !elf_arm_tdata (obfd)->no_enum_size_warning)
ee065d83 14952 {
91e22acd 14953 static const char *aeabi_enum_names[] =
bf21ed78 14954 { "", "variable-size", "32-bit", "" };
91e22acd
AS		 14955 const char *in_name =
14956 in_attr[i].i < ARRAY_SIZE(aeabi_enum_names)
14957 ? aeabi_enum_names[in_attr[i].i]
14958 : "<unknown>";
14959 const char *out_name =
14960 out_attr[i].i < ARRAY_SIZE(aeabi_enum_names)
14961 ? aeabi_enum_names[out_attr[i].i]
14962 : "<unknown>";
ee065d83 14963 _bfd_error_handler
871b3ab2 14964 (_("warning: %pB uses %s enums yet the output is to use %s enums; use of enum values across objects may fail"),
91e22acd 14965 ibfd, in_name, out_name);
ee065d83
PB		 14966 }
14967 }
14968 break;
14969 case Tag_ABI_VFP_args:
14970 /* Aready done. */
14971 break;
14972 case Tag_ABI_WMMX_args:
14973 if (in_attr[i].i != out_attr[i].i)
14974 {
14975 _bfd_error_handler
871b3ab2 14976 (_("error: %pB uses iWMMXt register arguments, %pB does not"),
ee065d83 14977 ibfd, obfd);
91e22acd 14978 result = FALSE;
ee065d83
PB		 14979 }
14980 break;
7b86a9fa
AS		 14981 case Tag_compatibility:
14982 /* Merged in target-independent code. */
14983 break;
91e22acd 14984 case Tag_ABI_HardFP_use:
4547cb56 14985 /* This is handled along with Tag_FP_arch. */
91e22acd
AS		 14986 break;
14987 case Tag_ABI_FP_16bit_format:
14988 if (in_attr[i].i != 0 && out_attr[i].i != 0)
14989 {
14990 if (in_attr[i].i != out_attr[i].i)
14991 {
14992 _bfd_error_handler
871b3ab2 14993 (_("error: fp16 format mismatch between %pB and %pB"),
91e22acd
AS		 14994 ibfd, obfd);
14995 result = FALSE;
14996 }
14997 }
14998 if (in_attr[i].i != 0)
14999 out_attr[i].i = in_attr[i].i;
15000 break;
7b86a9fa 15001
cd21e546 15002 case Tag_DIV_use:
ac56ee8f
MGD		 15003 /* A value of zero on input means that the divide instruction may
15004 be used if available in the base architecture as specified via
15005 Tag_CPU_arch and Tag_CPU_arch_profile. A value of 1 means that
15006 the user did not want divide instructions. A value of 2
15007 explicitly means that divide instructions were allowed in ARM
15008 and Thumb state. */
15009 if (in_attr[i].i == out_attr[i].i)
15010 /* Do nothing. */ ;
15011 else if (elf32_arm_attributes_forbid_div (in_attr)
15012 && !elf32_arm_attributes_accept_div (out_attr))
15013 out_attr[i].i = 1;
15014 else if (elf32_arm_attributes_forbid_div (out_attr)
15015 && elf32_arm_attributes_accept_div (in_attr))
15016 out_attr[i].i = in_attr[i].i;
15017 else if (in_attr[i].i == 2)
15018 out_attr[i].i = in_attr[i].i;
cd21e546
MGD		 15019 break;
15020
15021 case Tag_MPextension_use_legacy:
15022 /* We don't output objects with Tag_MPextension_use_legacy - we
15023 move the value to Tag_MPextension_use. */
15024 if (in_attr[i].i != 0 && in_attr[Tag_MPextension_use].i != 0)
15025 {
15026 if (in_attr[Tag_MPextension_use].i != in_attr[i].i)
15027 {
15028 _bfd_error_handler
871b3ab2 15029 (_("%pB has both the current and legacy "
b38cadfb 15030 "Tag_MPextension_use attributes"),
cd21e546
MGD		 15031 ibfd);
15032 result = FALSE;
15033 }
15034 }
15035
15036 if (in_attr[i].i > out_attr[Tag_MPextension_use].i)
15037 out_attr[Tag_MPextension_use] = in_attr[i];
15038
15039 break;
15040
91e22acd 15041 case Tag_nodefaults:
2d0bb761
AS		 15042 /* This tag is set if it exists, but the value is unused (and is
15043 typically zero). We don't actually need to do anything here -
15044 the merge happens automatically when the type flags are merged
15045 below. */
91e22acd
AS		 15046 break;
15047 case Tag_also_compatible_with:
15048 /* Already done in Tag_CPU_arch. */
15049 break;
15050 case Tag_conformance:
15051 /* Keep the attribute if it matches. Throw it away otherwise.
15052 No attribute means no claim to conform. */
15053 if (!in_attr[i].s || !out_attr[i].s
15054 || strcmp (in_attr[i].s, out_attr[i].s) != 0)
15055 out_attr[i].s = NULL;
15056 break;
3cfad14c 15057
91e22acd 15058 default:
e8b36cd1
JM		 15059 result
15060 = result && _bfd_elf_merge_unknown_attribute_low (ibfd, obfd, i);
91e22acd
AS		 15061 }
15062
15063 /* If out_attr was copied from in_attr then it won't have a type yet. */
15064 if (in_attr[i].type && !out_attr[i].type)
15065 out_attr[i].type = in_attr[i].type;
ee065d83
PB		 15066 }
15067
104d59d1 15068 /* Merge Tag_compatibility attributes and any common GNU ones. */
50e03d47 15069 if (!_bfd_elf_merge_object_attributes (ibfd, info))
5488d830 15070 return FALSE;
ee065d83 15071
104d59d1 15072 /* Check for any attributes not known on ARM. */
e8b36cd1 15073 result &= _bfd_elf_merge_unknown_attribute_list (ibfd, obfd);
91e22acd 15074
91e22acd 15075 return result;
252b5132
RH		 15076}
15077
3a4a14e9
PB		 15078
15079/* Return TRUE if the two EABI versions are incompatible. */
15080
15081static bfd_boolean
15082elf32_arm_versions_compatible (unsigned iver, unsigned over)
15083{
15084 /* v4 and v5 are the same spec before and after it was released,
15085 so allow mixing them. */
15086 if ((iver == EF_ARM_EABI_VER4 && over == EF_ARM_EABI_VER5)
15087 || (iver == EF_ARM_EABI_VER5 && over == EF_ARM_EABI_VER4))
15088 return TRUE;
15089
15090 return (iver == over);
15091}
15092
252b5132
RH		 15093/* Merge backend specific data from an object file to the output
15094 object file when linking. */
9b485d32 15095
b34976b6 15096static bfd_boolean
50e03d47 15097elf32_arm_merge_private_bfd_data (bfd *, struct bfd_link_info *);
252b5132 15098
9b485d32
NC		 15099/* Display the flags field. */
15100
b34976b6 15101static bfd_boolean
57e8b36a 15102elf32_arm_print_private_bfd_data (bfd *abfd, void * ptr)
252b5132 15103{
fc830a83
NC		 15104 FILE * file = (FILE *) ptr;
15105 unsigned long flags;
252b5132
RH		 15106
15107 BFD_ASSERT (abfd != NULL && ptr != NULL);
15108
15109 /* Print normal ELF private data. */
15110 _bfd_elf_print_private_bfd_data (abfd, ptr);
15111
fc830a83 15112 flags = elf_elfheader (abfd)->e_flags;
9b485d32
NC		 15113 /* Ignore init flag - it may not be set, despite the flags field
15114 containing valid data. */
252b5132 15115
9b485d32 15116 fprintf (file, _("private flags = %lx:"), elf_elfheader (abfd)->e_flags);
252b5132 15117
fc830a83
NC		 15118 switch (EF_ARM_EABI_VERSION (flags))
15119 {
15120 case EF_ARM_EABI_UNKNOWN:
4cc11e76 15121 /* The following flag bits are GNU extensions and not part of the
fc830a83
NC		 15122 official ARM ELF extended ABI. Hence they are only decoded if
15123 the EABI version is not set. */
fd2ec330 15124 if (flags & EF_ARM_INTERWORK)
9b485d32 15125 fprintf (file, _(" [interworking enabled]"));
9a5aca8c 15126
fd2ec330 15127 if (flags & EF_ARM_APCS_26)
6c571f00 15128 fprintf (file, " [APCS-26]");
fc830a83 15129 else
6c571f00 15130 fprintf (file, " [APCS-32]");
9a5aca8c 15131
96a846ea
RE		 15132 if (flags & EF_ARM_VFP_FLOAT)
15133 fprintf (file, _(" [VFP float format]"));
fde78edd
NC		 15134 else if (flags & EF_ARM_MAVERICK_FLOAT)
15135 fprintf (file, _(" [Maverick float format]"));
96a846ea
RE		 15136 else
15137 fprintf (file, _(" [FPA float format]"));
15138
fd2ec330 15139 if (flags & EF_ARM_APCS_FLOAT)
9b485d32 15140 fprintf (file, _(" [floats passed in float registers]"));
9a5aca8c 15141
fd2ec330 15142 if (flags & EF_ARM_PIC)
9b485d32 15143 fprintf (file, _(" [position independent]"));
fc830a83 15144
fd2ec330 15145 if (flags & EF_ARM_NEW_ABI)
9b485d32 15146 fprintf (file, _(" [new ABI]"));
9a5aca8c 15147
fd2ec330 15148 if (flags & EF_ARM_OLD_ABI)
9b485d32 15149 fprintf (file, _(" [old ABI]"));
9a5aca8c 15150
fd2ec330 15151 if (flags & EF_ARM_SOFT_FLOAT)
9b485d32 15152 fprintf (file, _(" [software FP]"));
9a5aca8c 15153
96a846ea
RE		 15154 flags &= ~(EF_ARM_INTERWORK | EF_ARM_APCS_26 | EF_ARM_APCS_FLOAT
15155 | EF_ARM_PIC | EF_ARM_NEW_ABI | EF_ARM_OLD_ABI
fde78edd
NC		 15156 | EF_ARM_SOFT_FLOAT | EF_ARM_VFP_FLOAT
15157 | EF_ARM_MAVERICK_FLOAT);
fc830a83 15158 break;
9a5aca8c 15159
fc830a83 15160 case EF_ARM_EABI_VER1:
9b485d32 15161 fprintf (file, _(" [Version1 EABI]"));
9a5aca8c 15162
fc830a83 15163 if (flags & EF_ARM_SYMSARESORTED)
9b485d32 15164 fprintf (file, _(" [sorted symbol table]"));
fc830a83 15165 else
9b485d32 15166 fprintf (file, _(" [unsorted symbol table]"));
9a5aca8c 15167
fc830a83
NC		 15168 flags &= ~ EF_ARM_SYMSARESORTED;
15169 break;
9a5aca8c 15170
fd2ec330
PB		 15171 case EF_ARM_EABI_VER2:
15172 fprintf (file, _(" [Version2 EABI]"));
15173
15174 if (flags & EF_ARM_SYMSARESORTED)
15175 fprintf (file, _(" [sorted symbol table]"));
15176 else
15177 fprintf (file, _(" [unsorted symbol table]"));
15178
15179 if (flags & EF_ARM_DYNSYMSUSESEGIDX)
15180 fprintf (file, _(" [dynamic symbols use segment index]"));
15181
15182 if (flags & EF_ARM_MAPSYMSFIRST)
15183 fprintf (file, _(" [mapping symbols precede others]"));
15184
99e4ae17 15185 flags &= ~(EF_ARM_SYMSARESORTED | EF_ARM_DYNSYMSUSESEGIDX
fd2ec330
PB		 15186 | EF_ARM_MAPSYMSFIRST);
15187 break;
15188
d507cf36
PB		 15189 case EF_ARM_EABI_VER3:
15190 fprintf (file, _(" [Version3 EABI]"));
8cb51566
PB		 15191 break;
15192
15193 case EF_ARM_EABI_VER4:
15194 fprintf (file, _(" [Version4 EABI]"));
3a4a14e9 15195 goto eabi;
d507cf36 15196
3a4a14e9
PB		 15197 case EF_ARM_EABI_VER5:
15198 fprintf (file, _(" [Version5 EABI]"));
3bfcb652
NC		 15199
15200 if (flags & EF_ARM_ABI_FLOAT_SOFT)
15201 fprintf (file, _(" [soft-float ABI]"));
15202
15203 if (flags & EF_ARM_ABI_FLOAT_HARD)
15204 fprintf (file, _(" [hard-float ABI]"));
15205
15206 flags &= ~(EF_ARM_ABI_FLOAT_SOFT | EF_ARM_ABI_FLOAT_HARD);
15207
3a4a14e9 15208 eabi:
d507cf36
PB		 15209 if (flags & EF_ARM_BE8)
15210 fprintf (file, _(" [BE8]"));
15211
15212 if (flags & EF_ARM_LE8)
15213 fprintf (file, _(" [LE8]"));
15214
15215 flags &= ~(EF_ARM_LE8 | EF_ARM_BE8);
15216 break;
15217
fc830a83 15218 default:
9b485d32 15219 fprintf (file, _(" <EABI version unrecognised>"));
fc830a83
NC		 15220 break;
15221 }
252b5132 15222
fc830a83 15223 flags &= ~ EF_ARM_EABIMASK;
252b5132 15224
fc830a83 15225 if (flags & EF_ARM_RELEXEC)
9b485d32 15226 fprintf (file, _(" [relocatable executable]"));
252b5132 15227
18a20338
CL		 15228 if (flags & EF_ARM_PIC)
15229 fprintf (file, _(" [position independent]"));
15230
15231 if (elf_elfheader (abfd)->e_ident[EI_OSABI] == ELFOSABI_ARM_FDPIC)
15232 fprintf (file, _(" [FDPIC ABI supplement]"));
15233
15234 flags &= ~ (EF_ARM_RELEXEC | EF_ARM_PIC);
fc830a83
NC		 15235
15236 if (flags)
9b485d32 15237 fprintf (file, _("<Unrecognised flag bits set>"));
9a5aca8c 15238
252b5132
RH		 15239 fputc ('\n', file);
15240
b34976b6 15241 return TRUE;
252b5132
RH		 15242}
15243
15244static int
57e8b36a 15245elf32_arm_get_symbol_type (Elf_Internal_Sym * elf_sym, int type)
252b5132 15246{
2f0ca46a
NC		 15247 switch (ELF_ST_TYPE (elf_sym->st_info))
15248 {
15249 case STT_ARM_TFUNC:
15250 return ELF_ST_TYPE (elf_sym->st_info);
ce855c42 15251
2f0ca46a
NC		 15252 case STT_ARM_16BIT:
15253 /* If the symbol is not an object, return the STT_ARM_16BIT flag.
15254 This allows us to distinguish between data used by Thumb instructions
15255 and non-data (which is probably code) inside Thumb regions of an
15256 executable. */
1a0eb693 15257 if (type != STT_OBJECT && type != STT_TLS)
2f0ca46a
NC		 15258 return ELF_ST_TYPE (elf_sym->st_info);
15259 break;
9a5aca8c 15260
ce855c42
NC		 15261 default:
15262 break;
2f0ca46a
NC		 15263 }
15264
15265 return type;
252b5132 15266}
f21f3fe0 15267
252b5132 15268static asection *
07adf181
AM		 15269elf32_arm_gc_mark_hook (asection *sec,
15270 struct bfd_link_info *info,
15271 Elf_Internal_Rela *rel,
15272 struct elf_link_hash_entry *h,
15273 Elf_Internal_Sym *sym)
252b5132
RH		 15274{
15275 if (h != NULL)
07adf181 15276 switch (ELF32_R_TYPE (rel->r_info))
252b5132
RH		 15277 {
15278 case R_ARM_GNU_VTINHERIT:
15279 case R_ARM_GNU_VTENTRY:
07adf181
AM		 15280 return NULL;
15281 }
9ad5cbcf 15282
07adf181 15283 return _bfd_elf_gc_mark_hook (sec, info, rel, h, sym);
252b5132
RH		 15284}
15285
780a67af
NC		 15286/* Look through the relocs for a section during the first phase. */
15287
b34976b6 15288static bfd_boolean
57e8b36a
NC		 15289elf32_arm_check_relocs (bfd *abfd, struct bfd_link_info *info,
15290 asection *sec, const Elf_Internal_Rela *relocs)
252b5132 15291{
b34976b6
AM		 15292 Elf_Internal_Shdr *symtab_hdr;
15293 struct elf_link_hash_entry **sym_hashes;
b34976b6
AM		 15294 const Elf_Internal_Rela *rel;
15295 const Elf_Internal_Rela *rel_end;
15296 bfd *dynobj;
5e681ec4 15297 asection *sreloc;
5e681ec4 15298 struct elf32_arm_link_hash_table *htab;
f6e32f6d
RS		 15299 bfd_boolean call_reloc_p;
15300 bfd_boolean may_become_dynamic_p;
15301 bfd_boolean may_need_local_target_p;
ce98a316 15302 unsigned long nsyms;
9a5aca8c 15303
0e1862bb 15304 if (bfd_link_relocatable (info))
b34976b6 15305 return TRUE;
9a5aca8c 15306
0ffa91dd
NC		 15307 BFD_ASSERT (is_arm_elf (abfd));
15308
5e681ec4 15309 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 15310 if (htab == NULL)
15311 return FALSE;
15312
5e681ec4 15313 sreloc = NULL;
9a5aca8c 15314
67687978
PB		 15315 /* Create dynamic sections for relocatable executables so that we can
15316 copy relocations. */
15317 if (htab->root.is_relocatable_executable
15318 && ! htab->root.dynamic_sections_created)
15319 {
15320 if (! _bfd_elf_link_create_dynamic_sections (abfd, info))
15321 return FALSE;
15322 }
15323
cbc704f3
RS		 15324 if (htab->root.dynobj == NULL)
15325 htab->root.dynobj = abfd;
34e77a92
RS		 15326 if (!create_ifunc_sections (info))
15327 return FALSE;
cbc704f3
RS		 15328
15329 dynobj = htab->root.dynobj;
15330
0ffa91dd 15331 symtab_hdr = & elf_symtab_hdr (abfd);
252b5132 15332 sym_hashes = elf_sym_hashes (abfd);
ce98a316 15333 nsyms = NUM_SHDR_ENTRIES (symtab_hdr);
b38cadfb 15334
252b5132
RH		 15335 rel_end = relocs + sec->reloc_count;
15336 for (rel = relocs; rel < rel_end; rel++)
15337 {
34e77a92 15338 Elf_Internal_Sym *isym;
252b5132 15339 struct elf_link_hash_entry *h;
b7693d02 15340 struct elf32_arm_link_hash_entry *eh;
d42c267e 15341 unsigned int r_symndx;
eb043451 15342 int r_type;
9a5aca8c 15343
252b5132 15344 r_symndx = ELF32_R_SYM (rel->r_info);
eb043451 15345 r_type = ELF32_R_TYPE (rel->r_info);
eb043451 15346 r_type = arm_real_reloc_type (htab, r_type);
ba93b8ac 15347
ce98a316
NC		 15348 if (r_symndx >= nsyms
15349 /* PR 9934: It is possible to have relocations that do not
15350 refer to symbols, thus it is also possible to have an
15351 object file containing relocations but no symbol table. */
cf35638d 15352 && (r_symndx > STN_UNDEF || nsyms > 0))
ba93b8ac 15353 {
871b3ab2 15354 _bfd_error_handler (_("%pB: bad symbol index: %d"), abfd,
4eca0228 15355 r_symndx);
ba93b8ac
DJ		 15356 return FALSE;
15357 }
15358
34e77a92
RS		 15359 h = NULL;
15360 isym = NULL;
15361 if (nsyms > 0)
973a3492 15362 {
34e77a92
RS		 15363 if (r_symndx < symtab_hdr->sh_info)
15364 {
15365 /* A local symbol. */
15366 isym = bfd_sym_from_r_symndx (&htab->sym_cache,
15367 abfd, r_symndx);
15368 if (isym == NULL)
15369 return FALSE;
15370 }
15371 else
15372 {
15373 h = sym_hashes[r_symndx - symtab_hdr->sh_info];
15374 while (h->root.type == bfd_link_hash_indirect
15375 || h->root.type == bfd_link_hash_warning)
15376 h = (struct elf_link_hash_entry *) h->root.u.i.link;
15377 }
973a3492 15378 }
9a5aca8c 15379
b7693d02
DJ		 15380 eh = (struct elf32_arm_link_hash_entry *) h;
15381
f6e32f6d
RS		 15382 call_reloc_p = FALSE;
15383 may_become_dynamic_p = FALSE;
15384 may_need_local_target_p = FALSE;
15385
0855e32b
NS		 15386 /* Could be done earlier, if h were already available. */
15387 r_type = elf32_arm_tls_transition (info, r_type, h);
eb043451 15388 switch (r_type)
99059e56 15389 {
e8b09b87
CL		 15390 case R_ARM_GOTOFFFUNCDESC:
15391 {
15392 if (h == NULL)
15393 {
15394 if (!elf32_arm_allocate_local_sym_info (abfd))
15395 return FALSE;
15396 elf32_arm_local_fdpic_cnts(abfd)[r_symndx].gotofffuncdesc_cnt += 1;
15397 elf32_arm_local_fdpic_cnts(abfd)[r_symndx].funcdesc_offset = -1;
15398 }
15399 else
15400 {
15401 eh->fdpic_cnts.gotofffuncdesc_cnt++;
15402 }
15403 }
15404 break;
15405
15406 case R_ARM_GOTFUNCDESC:
15407 {
15408 if (h == NULL)
15409 {
15410 /* Such a relocation is not supposed to be generated
15411 by gcc on a static function. */
15412 /* Anyway if needed it could be handled. */
15413 abort();
15414 }
15415 else
15416 {
15417 eh->fdpic_cnts.gotfuncdesc_cnt++;
15418 }
15419 }
15420 break;
15421
15422 case R_ARM_FUNCDESC:
15423 {
15424 if (h == NULL)
15425 {
15426 if (!elf32_arm_allocate_local_sym_info (abfd))
15427 return FALSE;
15428 elf32_arm_local_fdpic_cnts(abfd)[r_symndx].funcdesc_cnt += 1;
15429 elf32_arm_local_fdpic_cnts(abfd)[r_symndx].funcdesc_offset = -1;
15430 }
15431 else
15432 {
15433 eh->fdpic_cnts.funcdesc_cnt++;
15434 }
15435 }
15436 break;
15437
5e681ec4 15438 case R_ARM_GOT32:
eb043451 15439 case R_ARM_GOT_PREL:
ba93b8ac 15440 case R_ARM_TLS_GD32:
5c5a4843 15441 case R_ARM_TLS_GD32_FDPIC:
ba93b8ac 15442 case R_ARM_TLS_IE32:
5c5a4843 15443 case R_ARM_TLS_IE32_FDPIC:
0855e32b
NS		 15444 case R_ARM_TLS_GOTDESC:
15445 case R_ARM_TLS_DESCSEQ:
15446 case R_ARM_THM_TLS_DESCSEQ:
15447 case R_ARM_TLS_CALL:
15448 case R_ARM_THM_TLS_CALL:
5e681ec4 15449 /* This symbol requires a global offset table entry. */
ba93b8ac
DJ		 15450 {
15451 int tls_type, old_tls_type;
5e681ec4 15452
ba93b8ac
DJ		 15453 switch (r_type)
15454 {
15455 case R_ARM_TLS_GD32: tls_type = GOT_TLS_GD; break;
5c5a4843 15456 case R_ARM_TLS_GD32_FDPIC: tls_type = GOT_TLS_GD; break;
b38cadfb 15457
ba93b8ac 15458 case R_ARM_TLS_IE32: tls_type = GOT_TLS_IE; break;
5c5a4843 15459 case R_ARM_TLS_IE32_FDPIC: tls_type = GOT_TLS_IE; break;
b38cadfb 15460
0855e32b
NS		 15461 case R_ARM_TLS_GOTDESC:
15462 case R_ARM_TLS_CALL: case R_ARM_THM_TLS_CALL:
15463 case R_ARM_TLS_DESCSEQ: case R_ARM_THM_TLS_DESCSEQ:
15464 tls_type = GOT_TLS_GDESC; break;
b38cadfb 15465
ba93b8ac
DJ		 15466 default: tls_type = GOT_NORMAL; break;
15467 }
252b5132 15468
0e1862bb 15469 if (!bfd_link_executable (info) && (tls_type & GOT_TLS_IE))
eea6dad2
KM		 15470 info->flags |= DF_STATIC_TLS;
15471
ba93b8ac
DJ		 15472 if (h != NULL)
15473 {
15474 h->got.refcount++;
15475 old_tls_type = elf32_arm_hash_entry (h)->tls_type;
15476 }
15477 else
15478 {
ba93b8ac 15479 /* This is a global offset table entry for a local symbol. */
34e77a92
RS		 15480 if (!elf32_arm_allocate_local_sym_info (abfd))
15481 return FALSE;
15482 elf_local_got_refcounts (abfd)[r_symndx] += 1;
ba93b8ac
DJ		 15483 old_tls_type = elf32_arm_local_got_tls_type (abfd) [r_symndx];
15484 }
15485
0855e32b 15486 /* If a variable is accessed with both tls methods, two
99059e56 15487 slots may be created. */
0855e32b
NS		 15488 if (GOT_TLS_GD_ANY_P (old_tls_type)
15489 && GOT_TLS_GD_ANY_P (tls_type))
15490 tls_type |= old_tls_type;
15491
15492 /* We will already have issued an error message if there
15493 is a TLS/non-TLS mismatch, based on the symbol
15494 type. So just combine any TLS types needed. */
ba93b8ac
DJ		 15495 if (old_tls_type != GOT_UNKNOWN && old_tls_type != GOT_NORMAL
15496 && tls_type != GOT_NORMAL)
15497 tls_type |= old_tls_type;
15498
0855e32b 15499 /* If the symbol is accessed in both IE and GDESC
99059e56
RM		 15500 method, we're able to relax. Turn off the GDESC flag,
15501 without messing up with any other kind of tls types
6a631e86 15502 that may be involved. */
0855e32b
NS		 15503 if ((tls_type & GOT_TLS_IE) && (tls_type & GOT_TLS_GDESC))
15504 tls_type &= ~GOT_TLS_GDESC;
15505
ba93b8ac
DJ		 15506 if (old_tls_type != tls_type)
15507 {
15508 if (h != NULL)
15509 elf32_arm_hash_entry (h)->tls_type = tls_type;
15510 else
15511 elf32_arm_local_got_tls_type (abfd) [r_symndx] = tls_type;
15512 }
15513 }
8029a119 15514 /* Fall through. */
ba93b8ac
DJ		 15515
15516 case R_ARM_TLS_LDM32:
5c5a4843
CL		 15517 case R_ARM_TLS_LDM32_FDPIC:
15518 if (r_type == R_ARM_TLS_LDM32 || r_type == R_ARM_TLS_LDM32_FDPIC)
ba93b8ac 15519 htab->tls_ldm_got.refcount++;
8029a119 15520 /* Fall through. */
252b5132 15521
c19d1205 15522 case R_ARM_GOTOFF32:
5e681ec4 15523 case R_ARM_GOTPC:
cbc704f3
RS		 15524 if (htab->root.sgot == NULL
15525 && !create_got_section (htab->root.dynobj, info))
15526 return FALSE;
252b5132
RH		 15527 break;
15528
252b5132 15529 case R_ARM_PC24:
7359ea65 15530 case R_ARM_PLT32:
5b5bb741
PB		 15531 case R_ARM_CALL:
15532 case R_ARM_JUMP24:
eb043451 15533 case R_ARM_PREL31:
c19d1205 15534 case R_ARM_THM_CALL:
bd97cb95
DJ		 15535 case R_ARM_THM_JUMP24:
15536 case R_ARM_THM_JUMP19:
f6e32f6d
RS		 15537 call_reloc_p = TRUE;
15538 may_need_local_target_p = TRUE;
15539 break;
15540
15541 case R_ARM_ABS12:
15542 /* VxWorks uses dynamic R_ARM_ABS12 relocations for
15543 ldr __GOTT_INDEX__ offsets. */
15544 if (!htab->vxworks_p)
15545 {
15546 may_need_local_target_p = TRUE;
15547 break;
15548 }
aebf9be7 15549 else goto jump_over;
9eaff861 15550
f6e32f6d 15551 /* Fall through. */
39623e12 15552
96c23d59
JM		 15553 case R_ARM_MOVW_ABS_NC:
15554 case R_ARM_MOVT_ABS:
15555 case R_ARM_THM_MOVW_ABS_NC:
15556 case R_ARM_THM_MOVT_ABS:
0e1862bb 15557 if (bfd_link_pic (info))
96c23d59 15558 {
4eca0228 15559 _bfd_error_handler
871b3ab2 15560 (_("%pB: relocation %s against `%s' can not be used when making a shared object; recompile with -fPIC"),
96c23d59
JM		 15561 abfd, elf32_arm_howto_table_1[r_type].name,
15562 (h) ? h->root.root.string : "a local symbol");
15563 bfd_set_error (bfd_error_bad_value);
15564 return FALSE;
15565 }
15566
15567 /* Fall through. */
39623e12
PB		 15568 case R_ARM_ABS32:
15569 case R_ARM_ABS32_NOI:
aebf9be7 15570 jump_over:
0e1862bb 15571 if (h != NULL && bfd_link_executable (info))
97323ad1
WN		 15572 {
15573 h->pointer_equality_needed = 1;
15574 }
15575 /* Fall through. */
39623e12
PB		 15576 case R_ARM_REL32:
15577 case R_ARM_REL32_NOI:
b6895b4f
PB		 15578 case R_ARM_MOVW_PREL_NC:
15579 case R_ARM_MOVT_PREL:
b6895b4f
PB		 15580 case R_ARM_THM_MOVW_PREL_NC:
15581 case R_ARM_THM_MOVT_PREL:
39623e12 15582
b7693d02 15583 /* Should the interworking branches be listed here? */
e8b09b87
CL		 15584 if ((bfd_link_pic (info) || htab->root.is_relocatable_executable
15585 || htab->fdpic_p)
34e77a92
RS		 15586 && (sec->flags & SEC_ALLOC) != 0)
15587 {
15588 if (h == NULL
469a3493 15589 && elf32_arm_howto_from_type (r_type)->pc_relative)
34e77a92
RS		 15590 {
15591 /* In shared libraries and relocatable executables,
15592 we treat local relative references as calls;
15593 see the related SYMBOL_CALLS_LOCAL code in
15594 allocate_dynrelocs. */
15595 call_reloc_p = TRUE;
15596 may_need_local_target_p = TRUE;
15597 }
15598 else
15599 /* We are creating a shared library or relocatable
15600 executable, and this is a reloc against a global symbol,
15601 or a non-PC-relative reloc against a local symbol.
15602 We may need to copy the reloc into the output. */
15603 may_become_dynamic_p = TRUE;
15604 }
f6e32f6d
RS		 15605 else
15606 may_need_local_target_p = TRUE;
252b5132
RH		 15607 break;
15608
99059e56
RM		 15609 /* This relocation describes the C++ object vtable hierarchy.
15610 Reconstruct it for later use during GC. */
15611 case R_ARM_GNU_VTINHERIT:
15612 if (!bfd_elf_gc_record_vtinherit (abfd, sec, h, rel->r_offset))
15613 return FALSE;
15614 break;
15615
15616 /* This relocation describes which C++ vtable entries are actually
15617 used. Record for later use during GC. */
15618 case R_ARM_GNU_VTENTRY:
a0ea3a14 15619 if (!bfd_elf_gc_record_vtentry (abfd, sec, h, rel->r_offset))
99059e56
RM		 15620 return FALSE;
15621 break;
15622 }
f6e32f6d
RS		 15623
15624 if (h != NULL)
15625 {
15626 if (call_reloc_p)
15627 /* We may need a .plt entry if the function this reloc
15628 refers to is in a different object, regardless of the
15629 symbol's type. We can't tell for sure yet, because
15630 something later might force the symbol local. */
15631 h->needs_plt = 1;
15632 else if (may_need_local_target_p)
15633 /* If this reloc is in a read-only section, we might
15634 need a copy reloc. We can't check reliably at this
15635 stage whether the section is read-only, as input
15636 sections have not yet been mapped to output sections.
15637 Tentatively set the flag for now, and correct in
15638 adjust_dynamic_symbol. */
15639 h->non_got_ref = 1;
15640 }
15641
34e77a92
RS		 15642 if (may_need_local_target_p
15643 && (h != NULL || ELF32_ST_TYPE (isym->st_info) == STT_GNU_IFUNC))
f6e32f6d 15644 {
34e77a92
RS		 15645 union gotplt_union *root_plt;
15646 struct arm_plt_info *arm_plt;
15647 struct arm_local_iplt_info *local_iplt;
15648
15649 if (h != NULL)
15650 {
15651 root_plt = &h->plt;
15652 arm_plt = &eh->plt;
15653 }
15654 else
15655 {
15656 local_iplt = elf32_arm_create_local_iplt (abfd, r_symndx);
15657 if (local_iplt == NULL)
15658 return FALSE;
15659 root_plt = &local_iplt->root;
15660 arm_plt = &local_iplt->arm;
15661 }
15662
f6e32f6d
RS		 15663 /* If the symbol is a function that doesn't bind locally,
15664 this relocation will need a PLT entry. */
a8c887dd
NC		 15665 if (root_plt->refcount != -1)
15666 root_plt->refcount += 1;
34e77a92
RS		 15667
15668 if (!call_reloc_p)
15669 arm_plt->noncall_refcount++;
f6e32f6d
RS		 15670
15671 /* It's too early to use htab->use_blx here, so we have to
15672 record possible blx references separately from
15673 relocs that definitely need a thumb stub. */
15674
15675 if (r_type == R_ARM_THM_CALL)
34e77a92 15676 arm_plt->maybe_thumb_refcount += 1;
f6e32f6d
RS		 15677
15678 if (r_type == R_ARM_THM_JUMP24
15679 || r_type == R_ARM_THM_JUMP19)
34e77a92 15680 arm_plt->thumb_refcount += 1;
f6e32f6d
RS		 15681 }
15682
15683 if (may_become_dynamic_p)
15684 {
15685 struct elf_dyn_relocs *p, **head;
15686
15687 /* Create a reloc section in dynobj. */
15688 if (sreloc == NULL)
15689 {
15690 sreloc = _bfd_elf_make_dynamic_reloc_section
15691 (sec, dynobj, 2, abfd, ! htab->use_rel);
15692
15693 if (sreloc == NULL)
15694 return FALSE;
15695
15696 /* BPABI objects never have dynamic relocations mapped. */
15697 if (htab->symbian_p)
15698 {
15699 flagword flags;
15700
15701 flags = bfd_get_section_flags (dynobj, sreloc);
15702 flags &= ~(SEC_LOAD | SEC_ALLOC);
15703 bfd_set_section_flags (dynobj, sreloc, flags);
15704 }
15705 }
15706
15707 /* If this is a global symbol, count the number of
15708 relocations we need for this symbol. */
15709 if (h != NULL)
15710 head = &((struct elf32_arm_link_hash_entry *) h)->dyn_relocs;
15711 else
15712 {
34e77a92
RS		 15713 head = elf32_arm_get_local_dynreloc_list (abfd, r_symndx, isym);
15714 if (head == NULL)
f6e32f6d 15715 return FALSE;
f6e32f6d
RS		 15716 }
15717
15718 p = *head;
15719 if (p == NULL || p->sec != sec)
15720 {
15721 bfd_size_type amt = sizeof *p;
15722
15723 p = (struct elf_dyn_relocs *) bfd_alloc (htab->root.dynobj, amt);
15724 if (p == NULL)
15725 return FALSE;
15726 p->next = *head;
15727 *head = p;
15728 p->sec = sec;
15729 p->count = 0;
15730 p->pc_count = 0;
15731 }
15732
469a3493 15733 if (elf32_arm_howto_from_type (r_type)->pc_relative)
f6e32f6d
RS		 15734 p->pc_count += 1;
15735 p->count += 1;
e8b09b87
CL		 15736 if (h == NULL && htab->fdpic_p && !bfd_link_pic(info)
15737 && r_type != R_ARM_ABS32 && r_type != R_ARM_ABS32_NOI) {
15738 /* Here we only support R_ARM_ABS32 and R_ARM_ABS32_NOI
15739 that will become rofixup. */
15740 /* This is due to the fact that we suppose all will become rofixup. */
15741 fprintf(stderr, "FDPIC does not yet support %d relocation to become dynamic for executable\n", r_type);
15742 _bfd_error_handler
15743 (_("FDPIC does not yet support %s relocation"
15744 " to become dynamic for executable"),
15745 elf32_arm_howto_table_1[r_type].name);
15746 abort();
15747 }
f6e32f6d 15748 }
252b5132 15749 }
f21f3fe0 15750
b34976b6 15751 return TRUE;
252b5132
RH		 15752}
15753
9eaff861
AO		 15754static void
15755elf32_arm_update_relocs (asection *o,
15756 struct bfd_elf_section_reloc_data *reldata)
15757{
15758 void (*swap_in) (bfd *, const bfd_byte *, Elf_Internal_Rela *);
15759 void (*swap_out) (bfd *, const Elf_Internal_Rela *, bfd_byte *);
15760 const struct elf_backend_data *bed;
15761 _arm_elf_section_data *eado;
15762 struct bfd_link_order *p;
15763 bfd_byte *erela_head, *erela;
15764 Elf_Internal_Rela *irela_head, *irela;
15765 Elf_Internal_Shdr *rel_hdr;
15766 bfd *abfd;
15767 unsigned int count;
15768
15769 eado = get_arm_elf_section_data (o);
15770
15771 if (!eado || eado->elf.this_hdr.sh_type != SHT_ARM_EXIDX)
15772 return;
15773
15774 abfd = o->owner;
15775 bed = get_elf_backend_data (abfd);
15776 rel_hdr = reldata->hdr;
15777
15778 if (rel_hdr->sh_entsize == bed->s->sizeof_rel)
15779 {
15780 swap_in = bed->s->swap_reloc_in;
15781 swap_out = bed->s->swap_reloc_out;
15782 }
15783 else if (rel_hdr->sh_entsize == bed->s->sizeof_rela)
15784 {
15785 swap_in = bed->s->swap_reloca_in;
15786 swap_out = bed->s->swap_reloca_out;
15787 }
15788 else
15789 abort ();
15790
15791 erela_head = rel_hdr->contents;
15792 irela_head = (Elf_Internal_Rela *) bfd_zmalloc
15793 ((NUM_SHDR_ENTRIES (rel_hdr) + 1) * sizeof (*irela_head));
15794
15795 erela = erela_head;
15796 irela = irela_head;
15797 count = 0;
15798
15799 for (p = o->map_head.link_order; p; p = p->next)
15800 {
15801 if (p->type == bfd_section_reloc_link_order
15802 || p->type == bfd_symbol_reloc_link_order)
15803 {
15804 (*swap_in) (abfd, erela, irela);
15805 erela += rel_hdr->sh_entsize;
15806 irela++;
15807 count++;
15808 }
15809 else if (p->type == bfd_indirect_link_order)
15810 {
15811 struct bfd_elf_section_reloc_data *input_reldata;
15812 arm_unwind_table_edit *edit_list, *edit_tail;
15813 _arm_elf_section_data *eadi;
15814 bfd_size_type j;
15815 bfd_vma offset;
15816 asection *i;
15817
15818 i = p->u.indirect.section;
15819
15820 eadi = get_arm_elf_section_data (i);
15821 edit_list = eadi->u.exidx.unwind_edit_list;
15822 edit_tail = eadi->u.exidx.unwind_edit_tail;
539300fb 15823 offset = i->output_offset;
9eaff861
AO		 15824
15825 if (eadi->elf.rel.hdr &&
15826 eadi->elf.rel.hdr->sh_entsize == rel_hdr->sh_entsize)
15827 input_reldata = &eadi->elf.rel;
15828 else if (eadi->elf.rela.hdr &&
15829 eadi->elf.rela.hdr->sh_entsize == rel_hdr->sh_entsize)
15830 input_reldata = &eadi->elf.rela;
15831 else
15832 abort ();
15833
15834 if (edit_list)
15835 {
15836 for (j = 0; j < NUM_SHDR_ENTRIES (input_reldata->hdr); j++)
15837 {
15838 arm_unwind_table_edit *edit_node, *edit_next;
15839 bfd_vma bias;
c48182bf 15840 bfd_vma reloc_index;
9eaff861
AO		 15841
15842 (*swap_in) (abfd, erela, irela);
c48182bf 15843 reloc_index = (irela->r_offset - offset) / 8;
9eaff861
AO		 15844
15845 bias = 0;
15846 edit_node = edit_list;
15847 for (edit_next = edit_list;
c48182bf 15848 edit_next && edit_next->index <= reloc_index;
9eaff861
AO		 15849 edit_next = edit_node->next)
15850 {
15851 bias++;
15852 edit_node = edit_next;
15853 }
15854
15855 if (edit_node->type != DELETE_EXIDX_ENTRY
c48182bf 15856 || edit_node->index != reloc_index)
9eaff861
AO		 15857 {
15858 irela->r_offset -= bias * 8;
15859 irela++;
15860 count++;
15861 }
15862
15863 erela += rel_hdr->sh_entsize;
15864 }
15865
15866 if (edit_tail->type == INSERT_EXIDX_CANTUNWIND_AT_END)
15867 {
15868 /* New relocation entity. */
15869 asection *text_sec = edit_tail->linked_section;
15870 asection *text_out = text_sec->output_section;
15871 bfd_vma exidx_offset = offset + i->size - 8;
15872
15873 irela->r_addend = 0;
15874 irela->r_offset = exidx_offset;
15875 irela->r_info = ELF32_R_INFO
15876 (text_out->target_index, R_ARM_PREL31);
15877 irela++;
15878 count++;
15879 }
15880 }
15881 else
15882 {
15883 for (j = 0; j < NUM_SHDR_ENTRIES (input_reldata->hdr); j++)
15884 {
15885 (*swap_in) (abfd, erela, irela);
15886 erela += rel_hdr->sh_entsize;
15887 irela++;
15888 }
15889
15890 count += NUM_SHDR_ENTRIES (input_reldata->hdr);
15891 }
15892 }
15893 }
15894
15895 reldata->count = count;
15896 rel_hdr->sh_size = count * rel_hdr->sh_entsize;
15897
15898 erela = erela_head;
15899 irela = irela_head;
15900 while (count > 0)
15901 {
15902 (*swap_out) (abfd, irela, erela);
15903 erela += rel_hdr->sh_entsize;
15904 irela++;
15905 count--;
15906 }
15907
15908 free (irela_head);
15909
15910 /* Hashes are no longer valid. */
15911 free (reldata->hashes);
15912 reldata->hashes = NULL;
15913}
15914
6a5bb875 15915/* Unwinding tables are not referenced directly. This pass marks them as
4ba2ef8f
TP		 15916 required if the corresponding code section is marked. Similarly, ARMv8-M
15917 secure entry functions can only be referenced by SG veneers which are
15918 created after the GC process. They need to be marked in case they reside in
15919 their own section (as would be the case if code was compiled with
15920 -ffunction-sections). */
6a5bb875
PB		 15921
15922static bfd_boolean
906e58ca
NC		 15923elf32_arm_gc_mark_extra_sections (struct bfd_link_info *info,
15924 elf_gc_mark_hook_fn gc_mark_hook)
6a5bb875
PB		 15925{
15926 bfd *sub;
15927 Elf_Internal_Shdr **elf_shdrp;
4ba2ef8f
TP		 15928 asection *cmse_sec;
15929 obj_attribute *out_attr;
15930 Elf_Internal_Shdr *symtab_hdr;
15931 unsigned i, sym_count, ext_start;
15932 const struct elf_backend_data *bed;
15933 struct elf_link_hash_entry **sym_hashes;
15934 struct elf32_arm_link_hash_entry *cmse_hash;
15935 bfd_boolean again, is_v8m, first_bfd_browse = TRUE;
bb32413f
SP		 15936 bfd_boolean debug_sec_need_to_be_marked = FALSE;
15937 asection *isec;
6a5bb875 15938
7f6ab9f8
AM		 15939 _bfd_elf_gc_mark_extra_sections (info, gc_mark_hook);
15940
4ba2ef8f
TP		 15941 out_attr = elf_known_obj_attributes_proc (info->output_bfd);
15942 is_v8m = out_attr[Tag_CPU_arch].i >= TAG_CPU_ARCH_V8M_BASE
15943 && out_attr[Tag_CPU_arch_profile].i == 'M';
15944
6a5bb875
PB		 15945 /* Marking EH data may cause additional code sections to be marked,
15946 requiring multiple passes. */
15947 again = TRUE;
15948 while (again)
15949 {
15950 again = FALSE;
c72f2fb2 15951 for (sub = info->input_bfds; sub != NULL; sub = sub->link.next)
6a5bb875
PB		 15952 {
15953 asection *o;
15954
0ffa91dd 15955 if (! is_arm_elf (sub))
6a5bb875
PB		 15956 continue;
15957
15958 elf_shdrp = elf_elfsections (sub);
15959 for (o = sub->sections; o != NULL; o = o->next)
15960 {
15961 Elf_Internal_Shdr *hdr;
0ffa91dd 15962
6a5bb875 15963 hdr = &elf_section_data (o)->this_hdr;
4fbb74a6
AM		 15964 if (hdr->sh_type == SHT_ARM_EXIDX
15965 && hdr->sh_link
15966 && hdr->sh_link < elf_numsections (sub)
6a5bb875
PB		 15967 && !o->gc_mark
15968 && elf_shdrp[hdr->sh_link]->bfd_section->gc_mark)
15969 {
15970 again = TRUE;
15971 if (!_bfd_elf_gc_mark (info, o, gc_mark_hook))
15972 return FALSE;
15973 }
15974 }
4ba2ef8f
TP		 15975
15976 /* Mark section holding ARMv8-M secure entry functions. We mark all
15977 of them so no need for a second browsing. */
15978 if (is_v8m && first_bfd_browse)
15979 {
15980 sym_hashes = elf_sym_hashes (sub);
15981 bed = get_elf_backend_data (sub);
15982 symtab_hdr = &elf_tdata (sub)->symtab_hdr;
15983 sym_count = symtab_hdr->sh_size / bed->s->sizeof_sym;
15984 ext_start = symtab_hdr->sh_info;
15985
15986 /* Scan symbols. */
15987 for (i = ext_start; i < sym_count; i++)
15988 {
15989 cmse_hash = elf32_arm_hash_entry (sym_hashes[i - ext_start]);
15990
15991 /* Assume it is a special symbol. If not, cmse_scan will
15992 warn about it and user can do something about it. */
15993 if (ARM_GET_SYM_CMSE_SPCL (cmse_hash->root.target_internal))
15994 {
15995 cmse_sec = cmse_hash->root.root.u.def.section;
5025eb7c
AO		 15996 if (!cmse_sec->gc_mark
15997 && !_bfd_elf_gc_mark (info, cmse_sec, gc_mark_hook))
4ba2ef8f 15998 return FALSE;
bb32413f
SP		 15999 /* The debug sections related to these secure entry
16000 functions are marked on enabling below flag. */
16001 debug_sec_need_to_be_marked = TRUE;
4ba2ef8f
TP		 16002 }
16003 }
bb32413f
SP		 16004
16005 if (debug_sec_need_to_be_marked)
16006 {
16007 /* Looping over all the sections of the object file containing
16008 Armv8-M secure entry functions and marking all the debug
16009 sections. */
16010 for (isec = sub->sections; isec != NULL; isec = isec->next)
16011 {
16012 /* If not a debug sections, skip it. */
16013 if (!isec->gc_mark && (isec->flags & SEC_DEBUGGING))
16014 isec->gc_mark = 1 ;
16015 }
16016 debug_sec_need_to_be_marked = FALSE;
16017 }
4ba2ef8f 16018 }
6a5bb875 16019 }
4ba2ef8f 16020 first_bfd_browse = FALSE;
6a5bb875
PB		 16021 }
16022
16023 return TRUE;
16024}
16025
3c9458e9
NC		 16026/* Treat mapping symbols as special target symbols. */
16027
16028static bfd_boolean
16029elf32_arm_is_target_special_symbol (bfd * abfd ATTRIBUTE_UNUSED, asymbol * sym)
16030{
b0796911
PB		 16031 return bfd_is_arm_special_symbol_name (sym->name,
16032 BFD_ARM_SPECIAL_SYM_TYPE_ANY);
3c9458e9
NC		 16033}
16034
62e0492f 16035/* This is a version of _bfd_elf_find_function() from dwarf2.c except that
0367ecfb
NC		 16036 ARM mapping symbols are ignored when looking for function names
16037 and STT_ARM_TFUNC is considered to a function type. */
252b5132 16038
0367ecfb 16039static bfd_boolean
62e0492f 16040arm_elf_find_function (bfd * abfd,
0367ecfb 16041 asymbol ** symbols,
fb167eb2 16042 asection * section,
07d6d2b8 16043 bfd_vma offset,
0367ecfb
NC		 16044 const char ** filename_ptr,
16045 const char ** functionname_ptr)
16046{
16047 const char * filename = NULL;
16048 asymbol * func = NULL;
16049 bfd_vma low_func = 0;
16050 asymbol ** p;
252b5132 16051
62e0492f
AL		 16052 if (symbols == NULL)
16053 return FALSE;
16054
16055 if (bfd_get_flavour (abfd) != bfd_target_elf_flavour)
16056 return FALSE;
16057
252b5132
RH		 16058 for (p = symbols; *p != NULL; p++)
16059 {
16060 elf_symbol_type *q;
16061
16062 q = (elf_symbol_type *) *p;
16063
252b5132
RH		 16064 switch (ELF_ST_TYPE (q->internal_elf_sym.st_info))
16065 {
16066 default:
16067 break;
16068 case STT_FILE:
16069 filename = bfd_asymbol_name (&q->symbol);
16070 break;
252b5132
RH		 16071 case STT_FUNC:
16072 case STT_ARM_TFUNC:
9d2da7ca 16073 case STT_NOTYPE:
b0796911 16074 /* Skip mapping symbols. */
0367ecfb 16075 if ((q->symbol.flags & BSF_LOCAL)
b0796911
PB		 16076 && bfd_is_arm_special_symbol_name (q->symbol.name,
16077 BFD_ARM_SPECIAL_SYM_TYPE_ANY))
0367ecfb
NC		 16078 continue;
16079 /* Fall through. */
6b40fcba 16080 if (bfd_get_section (&q->symbol) == section
252b5132
RH		 16081 && q->symbol.value >= low_func
16082 && q->symbol.value <= offset)
16083 {
16084 func = (asymbol *) q;
16085 low_func = q->symbol.value;
16086 }
16087 break;
16088 }
16089 }
16090
16091 if (func == NULL)
b34976b6 16092 return FALSE;
252b5132 16093
0367ecfb
NC		 16094 if (filename_ptr)
16095 *filename_ptr = filename;
16096 if (functionname_ptr)
16097 *functionname_ptr = bfd_asymbol_name (func);
16098
16099 return TRUE;
906e58ca 16100}
0367ecfb
NC		 16101
16102
16103/* Find the nearest line to a particular section and offset, for error
16104 reporting. This code is a duplicate of the code in elf.c, except
16105 that it uses arm_elf_find_function. */
16106
16107static bfd_boolean
07d6d2b8
AM		 16108elf32_arm_find_nearest_line (bfd * abfd,
16109 asymbol ** symbols,
16110 asection * section,
16111 bfd_vma offset,
0367ecfb
NC		 16112 const char ** filename_ptr,
16113 const char ** functionname_ptr,
fb167eb2
AM		 16114 unsigned int * line_ptr,
16115 unsigned int * discriminator_ptr)
0367ecfb
NC		 16116{
16117 bfd_boolean found = FALSE;
16118
fb167eb2 16119 if (_bfd_dwarf2_find_nearest_line (abfd, symbols, NULL, section, offset,
0367ecfb 16120 filename_ptr, functionname_ptr,
fb167eb2 16121 line_ptr, discriminator_ptr,
9defd221 16122 dwarf_debug_sections,
0367ecfb
NC		 16123 & elf_tdata (abfd)->dwarf2_find_line_info))
16124 {
16125 if (!*functionname_ptr)
fb167eb2 16126 arm_elf_find_function (abfd, symbols, section, offset,
0367ecfb
NC		 16127 *filename_ptr ? NULL : filename_ptr,
16128 functionname_ptr);
f21f3fe0 16129
0367ecfb
NC		 16130 return TRUE;
16131 }
16132
fb167eb2
AM		 16133 /* Skip _bfd_dwarf1_find_nearest_line since no known ARM toolchain
16134 uses DWARF1. */
16135
0367ecfb
NC		 16136 if (! _bfd_stab_section_find_nearest_line (abfd, symbols, section, offset,
16137 & found, filename_ptr,
16138 functionname_ptr, line_ptr,
16139 & elf_tdata (abfd)->line_info))
16140 return FALSE;
16141
16142 if (found && (*functionname_ptr || *line_ptr))
16143 return TRUE;
16144
16145 if (symbols == NULL)
16146 return FALSE;
16147
fb167eb2 16148 if (! arm_elf_find_function (abfd, symbols, section, offset,
0367ecfb
NC		 16149 filename_ptr, functionname_ptr))
16150 return FALSE;
16151
16152 *line_ptr = 0;
b34976b6 16153 return TRUE;
252b5132
RH		 16154}
16155
4ab527b0 16156static bfd_boolean
07d6d2b8 16157elf32_arm_find_inliner_info (bfd * abfd,
4ab527b0
FF		 16158 const char ** filename_ptr,
16159 const char ** functionname_ptr,
16160 unsigned int * line_ptr)
16161{
16162 bfd_boolean found;
16163 found = _bfd_dwarf2_find_inliner_info (abfd, filename_ptr,
16164 functionname_ptr, line_ptr,
16165 & elf_tdata (abfd)->dwarf2_find_line_info);
16166 return found;
16167}
16168
63c1f59d
AM		 16169/* Find dynamic relocs for H that apply to read-only sections. */
16170
16171static asection *
16172readonly_dynrelocs (struct elf_link_hash_entry *h)
16173{
16174 struct elf_dyn_relocs *p;
16175
16176 for (p = elf32_arm_hash_entry (h)->dyn_relocs; p != NULL; p = p->next)
16177 {
16178 asection *s = p->sec->output_section;
16179
16180 if (s != NULL && (s->flags & SEC_READONLY) != 0)
16181 return p->sec;
16182 }
16183 return NULL;
16184}
16185
252b5132
RH		 16186/* Adjust a symbol defined by a dynamic object and referenced by a
16187 regular object. The current definition is in some section of the
16188 dynamic object, but we're not including those sections. We have to
16189 change the definition to something the rest of the link can
16190 understand. */
16191
b34976b6 16192static bfd_boolean
57e8b36a
NC		 16193elf32_arm_adjust_dynamic_symbol (struct bfd_link_info * info,
16194 struct elf_link_hash_entry * h)
252b5132
RH		 16195{
16196 bfd * dynobj;
5474d94f 16197 asection *s, *srel;
b7693d02 16198 struct elf32_arm_link_hash_entry * eh;
67687978 16199 struct elf32_arm_link_hash_table *globals;
252b5132 16200
67687978 16201 globals = elf32_arm_hash_table (info);
4dfe6ac6
NC		 16202 if (globals == NULL)
16203 return FALSE;
16204
252b5132
RH		 16205 dynobj = elf_hash_table (info)->dynobj;
16206
16207 /* Make sure we know what is going on here. */
16208 BFD_ASSERT (dynobj != NULL
f5385ebf 16209 && (h->needs_plt
34e77a92 16210 || h->type == STT_GNU_IFUNC
60d67dc8 16211 || h->is_weakalias
f5385ebf
AM		 16212 || (h->def_dynamic
16213 && h->ref_regular
16214 && !h->def_regular)));
252b5132 16215
b7693d02
DJ		 16216 eh = (struct elf32_arm_link_hash_entry *) h;
16217
252b5132
RH		 16218 /* If this is a function, put it in the procedure linkage table. We
16219 will fill in the contents of the procedure linkage table later,
16220 when we know the address of the .got section. */
34e77a92 16221 if (h->type == STT_FUNC || h->type == STT_GNU_IFUNC || h->needs_plt)
252b5132 16222 {
34e77a92
RS		 16223 /* Calls to STT_GNU_IFUNC symbols always use a PLT, even if the
16224 symbol binds locally. */
5e681ec4 16225 if (h->plt.refcount <= 0
34e77a92
RS		 16226 || (h->type != STT_GNU_IFUNC
16227 && (SYMBOL_CALLS_LOCAL (info, h)
16228 || (ELF_ST_VISIBILITY (h->other) != STV_DEFAULT
16229 && h->root.type == bfd_link_hash_undefweak))))
252b5132
RH		 16230 {
16231 /* This case can occur if we saw a PLT32 reloc in an input
5e681ec4
PB		 16232 file, but the symbol was never referred to by a dynamic
16233 object, or if all references were garbage collected. In
16234 such a case, we don't actually need to build a procedure
16235 linkage table, and we can just do a PC24 reloc instead. */
16236 h->plt.offset = (bfd_vma) -1;
34e77a92
RS		 16237 eh->plt.thumb_refcount = 0;
16238 eh->plt.maybe_thumb_refcount = 0;
16239 eh->plt.noncall_refcount = 0;
f5385ebf 16240 h->needs_plt = 0;
252b5132
RH		 16241 }
16242
b34976b6 16243 return TRUE;
252b5132 16244 }
5e681ec4 16245 else
b7693d02
DJ		 16246 {
16247 /* It's possible that we incorrectly decided a .plt reloc was
16248 needed for an R_ARM_PC24 or similar reloc to a non-function sym
16249 in check_relocs. We can't decide accurately between function
16250 and non-function syms in check-relocs; Objects loaded later in
16251 the link may change h->type. So fix it now. */
16252 h->plt.offset = (bfd_vma) -1;
34e77a92
RS		 16253 eh->plt.thumb_refcount = 0;
16254 eh->plt.maybe_thumb_refcount = 0;
16255 eh->plt.noncall_refcount = 0;
b7693d02 16256 }
252b5132
RH		 16257
16258 /* If this is a weak symbol, and there is a real definition, the
16259 processor independent code will have arranged for us to see the
16260 real definition first, and we can just use the same value. */
60d67dc8 16261 if (h->is_weakalias)
252b5132 16262 {
60d67dc8
AM		 16263 struct elf_link_hash_entry *def = weakdef (h);
16264 BFD_ASSERT (def->root.type == bfd_link_hash_defined);
16265 h->root.u.def.section = def->root.u.def.section;
16266 h->root.u.def.value = def->root.u.def.value;
b34976b6 16267 return TRUE;
252b5132
RH		 16268 }
16269
ba93b8ac
DJ		 16270 /* If there are no non-GOT references, we do not need a copy
16271 relocation. */
16272 if (!h->non_got_ref)
16273 return TRUE;
16274
252b5132
RH		 16275 /* This is a reference to a symbol defined by a dynamic object which
16276 is not a function. */
16277
16278 /* If we are creating a shared library, we must presume that the
16279 only references to the symbol are via the global offset table.
16280 For such cases we need not do anything here; the relocations will
67687978
PB		 16281 be handled correctly by relocate_section. Relocatable executables
16282 can reference data in shared objects directly, so we don't need to
16283 do anything here. */
0e1862bb 16284 if (bfd_link_pic (info) || globals->root.is_relocatable_executable)
b34976b6 16285 return TRUE;
252b5132
RH		 16286
16287 /* We must allocate the symbol in our .dynbss section, which will
16288 become part of the .bss section of the executable. There will be
16289 an entry for this symbol in the .dynsym section. The dynamic
16290 object will contain position independent code, so all references
16291 from the dynamic object to this symbol will go through the global
16292 offset table. The dynamic linker will use the .dynsym entry to
16293 determine the address it must put in the global offset table, so
16294 both the dynamic object and the regular object will refer to the
16295 same memory location for the variable. */
5522f910
NC		 16296 /* If allowed, we must generate a R_ARM_COPY reloc to tell the dynamic
16297 linker to copy the initial value out of the dynamic object and into
16298 the runtime process image. We need to remember the offset into the
00a97672 16299 .rel(a).bss section we are going to use. */
5474d94f
AM		 16300 if ((h->root.u.def.section->flags & SEC_READONLY) != 0)
16301 {
16302 s = globals->root.sdynrelro;
16303 srel = globals->root.sreldynrelro;
16304 }
16305 else
16306 {
16307 s = globals->root.sdynbss;
16308 srel = globals->root.srelbss;
16309 }
5522f910
NC		 16310 if (info->nocopyreloc == 0
16311 && (h->root.u.def.section->flags & SEC_ALLOC) != 0
5522f910 16312 && h->size != 0)
252b5132 16313 {
47beaa6a 16314 elf32_arm_allocate_dynrelocs (info, srel, 1);
f5385ebf 16315 h->needs_copy = 1;
252b5132
RH		 16316 }
16317
6cabe1ea 16318 return _bfd_elf_adjust_dynamic_copy (info, h, s);
252b5132
RH		 16319}
16320
5e681ec4
PB		 16321/* Allocate space in .plt, .got and associated reloc sections for
16322 dynamic relocs. */
16323
16324static bfd_boolean
47beaa6a 16325allocate_dynrelocs_for_symbol (struct elf_link_hash_entry *h, void * inf)
5e681ec4
PB		 16326{
16327 struct bfd_link_info *info;
16328 struct elf32_arm_link_hash_table *htab;
16329 struct elf32_arm_link_hash_entry *eh;
0bdcacaf 16330 struct elf_dyn_relocs *p;
5e681ec4
PB		 16331
16332 if (h->root.type == bfd_link_hash_indirect)
16333 return TRUE;
16334
e6a6bb22
AM		 16335 eh = (struct elf32_arm_link_hash_entry *) h;
16336
5e681ec4
PB		 16337 info = (struct bfd_link_info *) inf;
16338 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 16339 if (htab == NULL)
16340 return FALSE;
5e681ec4 16341
34e77a92 16342 if ((htab->root.dynamic_sections_created || h->type == STT_GNU_IFUNC)
5e681ec4
PB		 16343 && h->plt.refcount > 0)
16344 {
16345 /* Make sure this symbol is output as a dynamic symbol.
16346 Undefined weak syms won't yet be marked as dynamic. */
6c699715
RL		 16347 if (h->dynindx == -1 && !h->forced_local
16348 && h->root.type == bfd_link_hash_undefweak)
5e681ec4 16349 {
c152c796 16350 if (! bfd_elf_link_record_dynamic_symbol (info, h))
5e681ec4
PB		 16351 return FALSE;
16352 }
16353
34e77a92
RS		 16354 /* If the call in the PLT entry binds locally, the associated
16355 GOT entry should use an R_ARM_IRELATIVE relocation instead of
16356 the usual R_ARM_JUMP_SLOT. Put it in the .iplt section rather
16357 than the .plt section. */
16358 if (h->type == STT_GNU_IFUNC && SYMBOL_CALLS_LOCAL (info, h))
16359 {
16360 eh->is_iplt = 1;
16361 if (eh->plt.noncall_refcount == 0
16362 && SYMBOL_REFERENCES_LOCAL (info, h))
16363 /* All non-call references can be resolved directly.
16364 This means that they can (and in some cases, must)
16365 resolve directly to the run-time target, rather than
16366 to the PLT. That in turns means that any .got entry
16367 would be equal to the .igot.plt entry, so there's
16368 no point having both. */
16369 h->got.refcount = 0;
16370 }
16371
0e1862bb 16372 if (bfd_link_pic (info)
34e77a92 16373 || eh->is_iplt
7359ea65 16374 || WILL_CALL_FINISH_DYNAMIC_SYMBOL (1, 0, h))
5e681ec4 16375 {
34e77a92 16376 elf32_arm_allocate_plt_entry (info, eh->is_iplt, &h->plt, &eh->plt);
b7693d02 16377
5e681ec4
PB		 16378 /* If this symbol is not defined in a regular file, and we are
16379 not generating a shared library, then set the symbol to this
16380 location in the .plt. This is required to make function
16381 pointers compare as equal between the normal executable and
16382 the shared library. */
0e1862bb 16383 if (! bfd_link_pic (info)
f5385ebf 16384 && !h->def_regular)
5e681ec4 16385 {
34e77a92 16386 h->root.u.def.section = htab->root.splt;
5e681ec4 16387 h->root.u.def.value = h->plt.offset;
5e681ec4 16388
67d74e43
DJ		 16389 /* Make sure the function is not marked as Thumb, in case
16390 it is the target of an ABS32 relocation, which will
16391 point to the PLT entry. */
39d911fc 16392 ARM_SET_SYM_BRANCH_TYPE (h->target_internal, ST_BRANCH_TO_ARM);
67d74e43 16393 }
022f8312 16394
00a97672
RS		 16395 /* VxWorks executables have a second set of relocations for
16396 each PLT entry. They go in a separate relocation section,
16397 which is processed by the kernel loader. */
0e1862bb 16398 if (htab->vxworks_p && !bfd_link_pic (info))
00a97672
RS		 16399 {
16400 /* There is a relocation for the initial PLT entry:
16401 an R_ARM_32 relocation for _GLOBAL_OFFSET_TABLE_. */
16402 if (h->plt.offset == htab->plt_header_size)
47beaa6a 16403 elf32_arm_allocate_dynrelocs (info, htab->srelplt2, 1);
00a97672
RS		 16404
16405 /* There are two extra relocations for each subsequent
16406 PLT entry: an R_ARM_32 relocation for the GOT entry,
16407 and an R_ARM_32 relocation for the PLT entry. */
47beaa6a 16408 elf32_arm_allocate_dynrelocs (info, htab->srelplt2, 2);
00a97672 16409 }
5e681ec4
PB		 16410 }
16411 else
16412 {
16413 h->plt.offset = (bfd_vma) -1;
f5385ebf 16414 h->needs_plt = 0;
5e681ec4
PB		 16415 }
16416 }
16417 else
16418 {
16419 h->plt.offset = (bfd_vma) -1;
f5385ebf 16420 h->needs_plt = 0;
5e681ec4
PB		 16421 }
16422
0855e32b
NS		 16423 eh = (struct elf32_arm_link_hash_entry *) h;
16424 eh->tlsdesc_got = (bfd_vma) -1;
16425
5e681ec4
PB		 16426 if (h->got.refcount > 0)
16427 {
16428 asection *s;
16429 bfd_boolean dyn;
ba93b8ac
DJ		 16430 int tls_type = elf32_arm_hash_entry (h)->tls_type;
16431 int indx;
5e681ec4
PB		 16432
16433 /* Make sure this symbol is output as a dynamic symbol.
16434 Undefined weak syms won't yet be marked as dynamic. */
e8b09b87 16435 if (htab->root.dynamic_sections_created && h->dynindx == -1 && !h->forced_local
6c699715 16436 && h->root.type == bfd_link_hash_undefweak)
5e681ec4 16437 {
c152c796 16438 if (! bfd_elf_link_record_dynamic_symbol (info, h))
5e681ec4
PB		 16439 return FALSE;
16440 }
16441
e5a52504
MM		 16442 if (!htab->symbian_p)
16443 {
362d30a1 16444 s = htab->root.sgot;
e5a52504 16445 h->got.offset = s->size;
ba93b8ac
DJ		 16446
16447 if (tls_type == GOT_UNKNOWN)
16448 abort ();
16449
16450 if (tls_type == GOT_NORMAL)
16451 /* Non-TLS symbols need one GOT slot. */
16452 s->size += 4;
16453 else
16454 {
99059e56
RM		 16455 if (tls_type & GOT_TLS_GDESC)
16456 {
0855e32b 16457 /* R_ARM_TLS_DESC needs 2 GOT slots. */
99059e56 16458 eh->tlsdesc_got
0855e32b
NS		 16459 = (htab->root.sgotplt->size
16460 - elf32_arm_compute_jump_table_size (htab));
99059e56
RM		 16461 htab->root.sgotplt->size += 8;
16462 h->got.offset = (bfd_vma) -2;
34e77a92 16463 /* plt.got_offset needs to know there's a TLS_DESC
0855e32b 16464 reloc in the middle of .got.plt. */
99059e56
RM		 16465 htab->num_tls_desc++;
16466 }
0855e32b 16467
ba93b8ac 16468 if (tls_type & GOT_TLS_GD)
0855e32b 16469 {
5c5a4843
CL		 16470 /* R_ARM_TLS_GD32 and R_ARM_TLS_GD32_FDPIC need two
16471 consecutive GOT slots. If the symbol is both GD
16472 and GDESC, got.offset may have been
16473 overwritten. */
0855e32b
NS		 16474 h->got.offset = s->size;
16475 s->size += 8;
16476 }
16477
ba93b8ac 16478 if (tls_type & GOT_TLS_IE)
5c5a4843
CL		 16479 /* R_ARM_TLS_IE32/R_ARM_TLS_IE32_FDPIC need one GOT
16480 slot. */
ba93b8ac
DJ		 16481 s->size += 4;
16482 }
16483
e5a52504 16484 dyn = htab->root.dynamic_sections_created;
ba93b8ac
DJ		 16485
16486 indx = 0;
0e1862bb
L		 16487 if (WILL_CALL_FINISH_DYNAMIC_SYMBOL (dyn,
16488 bfd_link_pic (info),
16489 h)
16490 && (!bfd_link_pic (info)
ba93b8ac
DJ		 16491 || !SYMBOL_REFERENCES_LOCAL (info, h)))
16492 indx = h->dynindx;
16493
16494 if (tls_type != GOT_NORMAL
0e1862bb 16495 && (bfd_link_pic (info) || indx != 0)
ba93b8ac
DJ		 16496 && (ELF_ST_VISIBILITY (h->other) == STV_DEFAULT
16497 || h->root.type != bfd_link_hash_undefweak))
16498 {
16499 if (tls_type & GOT_TLS_IE)
47beaa6a 16500 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
ba93b8ac
DJ		 16501
16502 if (tls_type & GOT_TLS_GD)
47beaa6a 16503 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
ba93b8ac 16504
b38cadfb 16505 if (tls_type & GOT_TLS_GDESC)
0855e32b 16506 {
47beaa6a 16507 elf32_arm_allocate_dynrelocs (info, htab->root.srelplt, 1);
0855e32b
NS		 16508 /* GDESC needs a trampoline to jump to. */
16509 htab->tls_trampoline = -1;
16510 }
16511
16512 /* Only GD needs it. GDESC just emits one relocation per
16513 2 entries. */
b38cadfb 16514 if ((tls_type & GOT_TLS_GD) && indx != 0)
47beaa6a 16515 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
ba93b8ac 16516 }
e8b09b87
CL		 16517 else if (((indx != -1) || htab->fdpic_p)
16518 && !SYMBOL_REFERENCES_LOCAL (info, h))
b436d854
RS		 16519 {
16520 if (htab->root.dynamic_sections_created)
16521 /* Reserve room for the GOT entry's R_ARM_GLOB_DAT relocation. */
16522 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
16523 }
34e77a92
RS		 16524 else if (h->type == STT_GNU_IFUNC
16525 && eh->plt.noncall_refcount == 0)
16526 /* No non-call references resolve the STT_GNU_IFUNC's PLT entry;
16527 they all resolve dynamically instead. Reserve room for the
16528 GOT entry's R_ARM_IRELATIVE relocation. */
16529 elf32_arm_allocate_irelocs (info, htab->root.srelgot, 1);
0e1862bb
L		 16530 else if (bfd_link_pic (info)
16531 && (ELF_ST_VISIBILITY (h->other) == STV_DEFAULT
16532 || h->root.type != bfd_link_hash_undefweak))
b436d854 16533 /* Reserve room for the GOT entry's R_ARM_RELATIVE relocation. */
47beaa6a 16534 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
e8b09b87
CL		 16535 else if (htab->fdpic_p && tls_type == GOT_NORMAL)
16536 /* Reserve room for rofixup for FDPIC executable. */
16537 /* TLS relocs do not need space since they are completely
16538 resolved. */
16539 htab->srofixup->size += 4;
e5a52504 16540 }
5e681ec4
PB		 16541 }
16542 else
16543 h->got.offset = (bfd_vma) -1;
16544
e8b09b87
CL		 16545 /* FDPIC support. */
16546 if (eh->fdpic_cnts.gotofffuncdesc_cnt > 0)
16547 {
16548 /* Symbol musn't be exported. */
16549 if (h->dynindx != -1)
16550 abort();
16551
16552 /* We only allocate one function descriptor with its associated relocation. */
16553 if (eh->fdpic_cnts.funcdesc_offset == -1)
16554 {
16555 asection *s = htab->root.sgot;
16556
16557 eh->fdpic_cnts.funcdesc_offset = s->size;
16558 s->size += 8;
16559 /* We will add an R_ARM_FUNCDESC_VALUE relocation or two rofixups. */
16560 if (bfd_link_pic(info))
16561 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
16562 else
16563 htab->srofixup->size += 8;
16564 }
16565 }
16566
16567 if (eh->fdpic_cnts.gotfuncdesc_cnt > 0)
16568 {
16569 asection *s = htab->root.sgot;
16570
16571 if (htab->root.dynamic_sections_created && h->dynindx == -1
16572 && !h->forced_local)
16573 if (! bfd_elf_link_record_dynamic_symbol (info, h))
16574 return FALSE;
16575
16576 if (h->dynindx == -1)
16577 {
16578 /* We only allocate one function descriptor with its associated relocation. q */
16579 if (eh->fdpic_cnts.funcdesc_offset == -1)
16580 {
16581
16582 eh->fdpic_cnts.funcdesc_offset = s->size;
16583 s->size += 8;
16584 /* We will add an R_ARM_FUNCDESC_VALUE relocation or two rofixups. */
16585 if (bfd_link_pic(info))
16586 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
16587 else
16588 htab->srofixup->size += 8;
16589 }
16590 }
16591
16592 /* Add one entry into the GOT and a R_ARM_FUNCDESC or
16593 R_ARM_RELATIVE/rofixup relocation on it. */
16594 eh->fdpic_cnts.gotfuncdesc_offset = s->size;
16595 s->size += 4;
16596 if (h->dynindx == -1 && !bfd_link_pic(info))
4b24dd1a 16597 htab->srofixup->size += 4;
e8b09b87 16598 else
4b24dd1a 16599 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
e8b09b87
CL		 16600 }
16601
16602 if (eh->fdpic_cnts.funcdesc_cnt > 0)
16603 {
16604 if (htab->root.dynamic_sections_created && h->dynindx == -1
16605 && !h->forced_local)
16606 if (! bfd_elf_link_record_dynamic_symbol (info, h))
16607 return FALSE;
16608
16609 if (h->dynindx == -1)
16610 {
16611 /* We only allocate one function descriptor with its associated relocation. */
16612 if (eh->fdpic_cnts.funcdesc_offset == -1)
16613 {
16614 asection *s = htab->root.sgot;
16615
16616 eh->fdpic_cnts.funcdesc_offset = s->size;
16617 s->size += 8;
16618 /* We will add an R_ARM_FUNCDESC_VALUE relocation or two rofixups. */
16619 if (bfd_link_pic(info))
16620 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
16621 else
16622 htab->srofixup->size += 8;
16623 }
16624 }
16625 if (h->dynindx == -1 && !bfd_link_pic(info))
16626 {
16627 /* For FDPIC executable we replace R_ARM_RELATIVE with a rofixup. */
16628 htab->srofixup->size += 4 * eh->fdpic_cnts.funcdesc_cnt;
16629 }
16630 else
16631 {
16632 /* Will need one dynamic reloc per reference. will be either
16633 R_ARM_FUNCDESC or R_ARM_RELATIVE for hidden symbols. */
16634 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot,
16635 eh->fdpic_cnts.funcdesc_cnt);
16636 }
16637 }
16638
a4fd1a8e
PB		 16639 /* Allocate stubs for exported Thumb functions on v4t. */
16640 if (!htab->use_blx && h->dynindx != -1
0eaedd0e 16641 && h->def_regular
39d911fc 16642 && ARM_GET_SYM_BRANCH_TYPE (h->target_internal) == ST_BRANCH_TO_THUMB
a4fd1a8e
PB		 16643 && ELF_ST_VISIBILITY (h->other) == STV_DEFAULT)
16644 {
16645 struct elf_link_hash_entry * th;
16646 struct bfd_link_hash_entry * bh;
16647 struct elf_link_hash_entry * myh;
16648 char name[1024];
16649 asection *s;
16650 bh = NULL;
16651 /* Create a new symbol to regist the real location of the function. */
16652 s = h->root.u.def.section;
906e58ca 16653 sprintf (name, "__real_%s", h->root.root.string);
a4fd1a8e
PB		 16654 _bfd_generic_link_add_one_symbol (info, s->owner,
16655 name, BSF_GLOBAL, s,
16656 h->root.u.def.value,
16657 NULL, TRUE, FALSE, &bh);
16658
16659 myh = (struct elf_link_hash_entry *) bh;
35fc36a8 16660 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
a4fd1a8e 16661 myh->forced_local = 1;
39d911fc 16662 ARM_SET_SYM_BRANCH_TYPE (myh->target_internal, ST_BRANCH_TO_THUMB);
a4fd1a8e
PB		 16663 eh->export_glue = myh;
16664 th = record_arm_to_thumb_glue (info, h);
16665 /* Point the symbol at the stub. */
16666 h->type = ELF_ST_INFO (ELF_ST_BIND (h->type), STT_FUNC);
39d911fc 16667 ARM_SET_SYM_BRANCH_TYPE (h->target_internal, ST_BRANCH_TO_ARM);
a4fd1a8e
PB		 16668 h->root.u.def.section = th->root.u.def.section;
16669 h->root.u.def.value = th->root.u.def.value & ~1;
16670 }
16671
0bdcacaf 16672 if (eh->dyn_relocs == NULL)
5e681ec4
PB		 16673 return TRUE;
16674
16675 /* In the shared -Bsymbolic case, discard space allocated for
16676 dynamic pc-relative relocs against symbols which turn out to be
16677 defined in regular objects. For the normal shared case, discard
16678 space for pc-relative relocs that have become local due to symbol
16679 visibility changes. */
16680
e8b09b87 16681 if (bfd_link_pic (info) || htab->root.is_relocatable_executable || htab->fdpic_p)
5e681ec4 16682 {
469a3493
RM		 16683 /* Relocs that use pc_count are PC-relative forms, which will appear
16684 on something like ".long foo - ." or "movw REG, foo - .". We want
16685 calls to protected symbols to resolve directly to the function
16686 rather than going via the plt. If people want function pointer
16687 comparisons to work as expected then they should avoid writing
16688 assembly like ".long foo - .". */
ba93b8ac
DJ		 16689 if (SYMBOL_CALLS_LOCAL (info, h))
16690 {
0bdcacaf 16691 struct elf_dyn_relocs **pp;
ba93b8ac 16692
0bdcacaf 16693 for (pp = &eh->dyn_relocs; (p = *pp) != NULL; )
ba93b8ac
DJ		 16694 {
16695 p->count -= p->pc_count;
16696 p->pc_count = 0;
16697 if (p->count == 0)
16698 *pp = p->next;
16699 else
16700 pp = &p->next;
16701 }
16702 }
16703
4dfe6ac6 16704 if (htab->vxworks_p)
3348747a 16705 {
0bdcacaf 16706 struct elf_dyn_relocs **pp;
3348747a 16707
0bdcacaf 16708 for (pp = &eh->dyn_relocs; (p = *pp) != NULL; )
3348747a 16709 {
0bdcacaf 16710 if (strcmp (p->sec->output_section->name, ".tls_vars") == 0)
3348747a
NS		 16711 *pp = p->next;
16712 else
16713 pp = &p->next;
16714 }
16715 }
16716
ba93b8ac 16717 /* Also discard relocs on undefined weak syms with non-default
99059e56 16718 visibility. */
0bdcacaf 16719 if (eh->dyn_relocs != NULL
5e681ec4 16720 && h->root.type == bfd_link_hash_undefweak)
22d606e9 16721 {
95b03e4a
L		 16722 if (ELF_ST_VISIBILITY (h->other) != STV_DEFAULT
16723 || UNDEFWEAK_NO_DYNAMIC_RELOC (info, h))
0bdcacaf 16724 eh->dyn_relocs = NULL;
22d606e9
AM		 16725
16726 /* Make sure undefined weak symbols are output as a dynamic
16727 symbol in PIEs. */
e8b09b87 16728 else if (htab->root.dynamic_sections_created && h->dynindx == -1
22d606e9
AM		 16729 && !h->forced_local)
16730 {
16731 if (! bfd_elf_link_record_dynamic_symbol (info, h))
16732 return FALSE;
16733 }
16734 }
16735
67687978
PB		 16736 else if (htab->root.is_relocatable_executable && h->dynindx == -1
16737 && h->root.type == bfd_link_hash_new)
16738 {
16739 /* Output absolute symbols so that we can create relocations
16740 against them. For normal symbols we output a relocation
16741 against the section that contains them. */
16742 if (! bfd_elf_link_record_dynamic_symbol (info, h))
16743 return FALSE;
16744 }
16745
5e681ec4
PB		 16746 }
16747 else
16748 {
16749 /* For the non-shared case, discard space for relocs against
16750 symbols which turn out to need copy relocs or are not
16751 dynamic. */
16752
f5385ebf
AM		 16753 if (!h->non_got_ref
16754 && ((h->def_dynamic
16755 && !h->def_regular)
5e681ec4
PB		 16756 || (htab->root.dynamic_sections_created
16757 && (h->root.type == bfd_link_hash_undefweak
16758 || h->root.type == bfd_link_hash_undefined))))
16759 {
16760 /* Make sure this symbol is output as a dynamic symbol.
16761 Undefined weak syms won't yet be marked as dynamic. */
6c699715
RL		 16762 if (h->dynindx == -1 && !h->forced_local
16763 && h->root.type == bfd_link_hash_undefweak)
5e681ec4 16764 {
c152c796 16765 if (! bfd_elf_link_record_dynamic_symbol (info, h))
5e681ec4
PB		 16766 return FALSE;
16767 }
16768
16769 /* If that succeeded, we know we'll be keeping all the
16770 relocs. */
16771 if (h->dynindx != -1)
16772 goto keep;
16773 }
16774
0bdcacaf 16775 eh->dyn_relocs = NULL;
5e681ec4
PB		 16776
16777 keep: ;
16778 }
16779
16780 /* Finally, allocate space. */
0bdcacaf 16781 for (p = eh->dyn_relocs; p != NULL; p = p->next)
5e681ec4 16782 {
0bdcacaf 16783 asection *sreloc = elf_section_data (p->sec)->sreloc;
e8b09b87 16784
34e77a92
RS		 16785 if (h->type == STT_GNU_IFUNC
16786 && eh->plt.noncall_refcount == 0
16787 && SYMBOL_REFERENCES_LOCAL (info, h))
16788 elf32_arm_allocate_irelocs (info, sreloc, p->count);
e8b09b87
CL		 16789 else if (h->dynindx != -1 && (!bfd_link_pic(info) || !info->symbolic || !h->def_regular))
16790 elf32_arm_allocate_dynrelocs (info, sreloc, p->count);
16791 else if (htab->fdpic_p && !bfd_link_pic(info))
16792 htab->srofixup->size += 4 * p->count;
34e77a92
RS		 16793 else
16794 elf32_arm_allocate_dynrelocs (info, sreloc, p->count);
5e681ec4
PB		 16795 }
16796
16797 return TRUE;
16798}
16799
63c1f59d
AM		 16800/* Set DF_TEXTREL if we find any dynamic relocs that apply to
16801 read-only sections. */
08d1f311
DJ		 16802
16803static bfd_boolean
63c1f59d 16804maybe_set_textrel (struct elf_link_hash_entry *h, void *info_p)
08d1f311 16805{
63c1f59d 16806 asection *sec;
08d1f311 16807
63c1f59d
AM		 16808 if (h->root.type == bfd_link_hash_indirect)
16809 return TRUE;
08d1f311 16810
63c1f59d
AM		 16811 sec = readonly_dynrelocs (h);
16812 if (sec != NULL)
16813 {
16814 struct bfd_link_info *info = (struct bfd_link_info *) info_p;
08d1f311 16815
63c1f59d
AM		 16816 info->flags |= DF_TEXTREL;
16817 info->callbacks->minfo
c1c8c1ef 16818 (_("%pB: dynamic relocation against `%pT' in read-only section `%pA'\n"),
63c1f59d 16819 sec->owner, h->root.root.string, sec);
08d1f311 16820
63c1f59d
AM		 16821 /* Not an error, just cut short the traversal. */
16822 return FALSE;
08d1f311 16823 }
cb10292c 16824
08d1f311
DJ		 16825 return TRUE;
16826}
16827
d504ffc8
DJ		 16828void
16829bfd_elf32_arm_set_byteswap_code (struct bfd_link_info *info,
16830 int byteswap_code)
16831{
16832 struct elf32_arm_link_hash_table *globals;
16833
16834 globals = elf32_arm_hash_table (info);
4dfe6ac6
NC		 16835 if (globals == NULL)
16836 return;
16837
d504ffc8
DJ		 16838 globals->byteswap_code = byteswap_code;
16839}
16840
252b5132
RH		 16841/* Set the sizes of the dynamic sections. */
16842
b34976b6 16843static bfd_boolean
57e8b36a
NC		 16844elf32_arm_size_dynamic_sections (bfd * output_bfd ATTRIBUTE_UNUSED,
16845 struct bfd_link_info * info)
252b5132
RH		 16846{
16847 bfd * dynobj;
16848 asection * s;
b34976b6
AM		 16849 bfd_boolean plt;
16850 bfd_boolean relocs;
5e681ec4
PB		 16851 bfd *ibfd;
16852 struct elf32_arm_link_hash_table *htab;
252b5132 16853
5e681ec4 16854 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 16855 if (htab == NULL)
16856 return FALSE;
16857
252b5132
RH		 16858 dynobj = elf_hash_table (info)->dynobj;
16859 BFD_ASSERT (dynobj != NULL);
39b41c9c 16860 check_use_blx (htab);
252b5132
RH		 16861
16862 if (elf_hash_table (info)->dynamic_sections_created)
16863 {
16864 /* Set the contents of the .interp section to the interpreter. */
9b8b325a 16865 if (bfd_link_executable (info) && !info->nointerp)
252b5132 16866 {
3d4d4302 16867 s = bfd_get_linker_section (dynobj, ".interp");
252b5132 16868 BFD_ASSERT (s != NULL);
eea6121a 16869 s->size = sizeof ELF_DYNAMIC_INTERPRETER;
252b5132
RH		 16870 s->contents = (unsigned char *) ELF_DYNAMIC_INTERPRETER;
16871 }
16872 }
5e681ec4
PB		 16873
16874 /* Set up .got offsets for local syms, and space for local dynamic
16875 relocs. */
c72f2fb2 16876 for (ibfd = info->input_bfds; ibfd != NULL; ibfd = ibfd->link.next)
252b5132 16877 {
5e681ec4
PB		 16878 bfd_signed_vma *local_got;
16879 bfd_signed_vma *end_local_got;
34e77a92 16880 struct arm_local_iplt_info **local_iplt_ptr, *local_iplt;
5e681ec4 16881 char *local_tls_type;
0855e32b 16882 bfd_vma *local_tlsdesc_gotent;
5e681ec4
PB		 16883 bfd_size_type locsymcount;
16884 Elf_Internal_Shdr *symtab_hdr;
16885 asection *srel;
4dfe6ac6 16886 bfd_boolean is_vxworks = htab->vxworks_p;
34e77a92 16887 unsigned int symndx;
e8b09b87 16888 struct fdpic_local *local_fdpic_cnts;
5e681ec4 16889
0ffa91dd 16890 if (! is_arm_elf (ibfd))
5e681ec4
PB		 16891 continue;
16892
16893 for (s = ibfd->sections; s != NULL; s = s->next)
16894 {
0bdcacaf 16895 struct elf_dyn_relocs *p;
5e681ec4 16896
0bdcacaf 16897 for (p = (struct elf_dyn_relocs *)
99059e56 16898 elf_section_data (s)->local_dynrel; p != NULL; p = p->next)
5e681ec4 16899 {
0bdcacaf
RS		 16900 if (!bfd_is_abs_section (p->sec)
16901 && bfd_is_abs_section (p->sec->output_section))
5e681ec4
PB		 16902 {
16903 /* Input section has been discarded, either because
16904 it is a copy of a linkonce section or due to
16905 linker script /DISCARD/, so we'll be discarding
16906 the relocs too. */
16907 }
3348747a 16908 else if (is_vxworks
0bdcacaf 16909 && strcmp (p->sec->output_section->name,
3348747a
NS		 16910 ".tls_vars") == 0)
16911 {
16912 /* Relocations in vxworks .tls_vars sections are
16913 handled specially by the loader. */
16914 }
5e681ec4
PB		 16915 else if (p->count != 0)
16916 {
0bdcacaf 16917 srel = elf_section_data (p->sec)->sreloc;
e8b09b87
CL		 16918 if (htab->fdpic_p && !bfd_link_pic(info))
16919 htab->srofixup->size += 4 * p->count;
16920 else
16921 elf32_arm_allocate_dynrelocs (info, srel, p->count);
0bdcacaf 16922 if ((p->sec->output_section->flags & SEC_READONLY) != 0)
5e681ec4
PB		 16923 info->flags |= DF_TEXTREL;
16924 }
16925 }
16926 }
16927
16928 local_got = elf_local_got_refcounts (ibfd);
16929 if (!local_got)
16930 continue;
16931
0ffa91dd 16932 symtab_hdr = & elf_symtab_hdr (ibfd);
5e681ec4
PB		 16933 locsymcount = symtab_hdr->sh_info;
16934 end_local_got = local_got + locsymcount;
34e77a92 16935 local_iplt_ptr = elf32_arm_local_iplt (ibfd);
ba93b8ac 16936 local_tls_type = elf32_arm_local_got_tls_type (ibfd);
0855e32b 16937 local_tlsdesc_gotent = elf32_arm_local_tlsdesc_gotent (ibfd);
e8b09b87 16938 local_fdpic_cnts = elf32_arm_local_fdpic_cnts (ibfd);
34e77a92 16939 symndx = 0;
362d30a1
RS		 16940 s = htab->root.sgot;
16941 srel = htab->root.srelgot;
0855e32b 16942 for (; local_got < end_local_got;
34e77a92 16943 ++local_got, ++local_iplt_ptr, ++local_tls_type,
e8b09b87 16944 ++local_tlsdesc_gotent, ++symndx, ++local_fdpic_cnts)
5e681ec4 16945 {
0855e32b 16946 *local_tlsdesc_gotent = (bfd_vma) -1;
34e77a92 16947 local_iplt = *local_iplt_ptr;
e8b09b87
CL		 16948
16949 /* FDPIC support. */
16950 if (local_fdpic_cnts->gotofffuncdesc_cnt > 0)
16951 {
16952 if (local_fdpic_cnts->funcdesc_offset == -1)
16953 {
16954 local_fdpic_cnts->funcdesc_offset = s->size;
16955 s->size += 8;
16956
16957 /* We will add an R_ARM_FUNCDESC_VALUE relocation or two rofixups. */
16958 if (bfd_link_pic(info))
16959 elf32_arm_allocate_dynrelocs (info, srel, 1);
16960 else
16961 htab->srofixup->size += 8;
16962 }
16963 }
16964
16965 if (local_fdpic_cnts->funcdesc_cnt > 0)
16966 {
16967 if (local_fdpic_cnts->funcdesc_offset == -1)
16968 {
16969 local_fdpic_cnts->funcdesc_offset = s->size;
16970 s->size += 8;
16971
16972 /* We will add an R_ARM_FUNCDESC_VALUE relocation or two rofixups. */
16973 if (bfd_link_pic(info))
16974 elf32_arm_allocate_dynrelocs (info, srel, 1);
16975 else
16976 htab->srofixup->size += 8;
16977 }
16978
16979 /* We will add n R_ARM_RELATIVE relocations or n rofixups. */
16980 if (bfd_link_pic(info))
16981 elf32_arm_allocate_dynrelocs (info, srel, local_fdpic_cnts->funcdesc_cnt);
16982 else
16983 htab->srofixup->size += 4 * local_fdpic_cnts->funcdesc_cnt;
16984 }
16985
34e77a92
RS		 16986 if (local_iplt != NULL)
16987 {
16988 struct elf_dyn_relocs *p;
16989
16990 if (local_iplt->root.refcount > 0)
16991 {
16992 elf32_arm_allocate_plt_entry (info, TRUE,
16993 &local_iplt->root,
16994 &local_iplt->arm);
16995 if (local_iplt->arm.noncall_refcount == 0)
16996 /* All references to the PLT are calls, so all
16997 non-call references can resolve directly to the
16998 run-time target. This means that the .got entry
16999 would be the same as the .igot.plt entry, so there's
17000 no point creating both. */
17001 *local_got = 0;
17002 }
17003 else
17004 {
17005 BFD_ASSERT (local_iplt->arm.noncall_refcount == 0);
17006 local_iplt->root.offset = (bfd_vma) -1;
17007 }
17008
17009 for (p = local_iplt->dyn_relocs; p != NULL; p = p->next)
17010 {
17011 asection *psrel;
17012
17013 psrel = elf_section_data (p->sec)->sreloc;
17014 if (local_iplt->arm.noncall_refcount == 0)
17015 elf32_arm_allocate_irelocs (info, psrel, p->count);
17016 else
17017 elf32_arm_allocate_dynrelocs (info, psrel, p->count);
17018 }
17019 }
5e681ec4
PB		 17020 if (*local_got > 0)
17021 {
34e77a92
RS		 17022 Elf_Internal_Sym *isym;
17023
eea6121a 17024 *local_got = s->size;
ba93b8ac
DJ		 17025 if (*local_tls_type & GOT_TLS_GD)
17026 /* TLS_GD relocs need an 8-byte structure in the GOT. */
17027 s->size += 8;
0855e32b
NS		 17028 if (*local_tls_type & GOT_TLS_GDESC)
17029 {
17030 *local_tlsdesc_gotent = htab->root.sgotplt->size
17031 - elf32_arm_compute_jump_table_size (htab);
17032 htab->root.sgotplt->size += 8;
17033 *local_got = (bfd_vma) -2;
34e77a92 17034 /* plt.got_offset needs to know there's a TLS_DESC
0855e32b 17035 reloc in the middle of .got.plt. */
99059e56 17036 htab->num_tls_desc++;
0855e32b 17037 }
ba93b8ac
DJ		 17038 if (*local_tls_type & GOT_TLS_IE)
17039 s->size += 4;
ba93b8ac 17040
0855e32b
NS		 17041 if (*local_tls_type & GOT_NORMAL)
17042 {
17043 /* If the symbol is both GD and GDESC, *local_got
17044 may have been overwritten. */
17045 *local_got = s->size;
17046 s->size += 4;
17047 }
17048
34e77a92
RS		 17049 isym = bfd_sym_from_r_symndx (&htab->sym_cache, ibfd, symndx);
17050 if (isym == NULL)
17051 return FALSE;
17052
17053 /* If all references to an STT_GNU_IFUNC PLT are calls,
17054 then all non-call references, including this GOT entry,
17055 resolve directly to the run-time target. */
17056 if (ELF32_ST_TYPE (isym->st_info) == STT_GNU_IFUNC
17057 && (local_iplt == NULL
17058 || local_iplt->arm.noncall_refcount == 0))
17059 elf32_arm_allocate_irelocs (info, srel, 1);
e8b09b87 17060 else if (bfd_link_pic (info) || output_bfd->flags & DYNAMIC || htab->fdpic_p)
0855e32b 17061 {
e8b09b87 17062 if ((bfd_link_pic (info) && !(*local_tls_type & GOT_TLS_GDESC)))
3064e1ff 17063 elf32_arm_allocate_dynrelocs (info, srel, 1);
e8b09b87
CL		 17064 else if (htab->fdpic_p && *local_tls_type & GOT_NORMAL)
17065 htab->srofixup->size += 4;
99059e56 17066
e8b09b87
CL		 17067 if ((bfd_link_pic (info) || htab->fdpic_p)
17068 && *local_tls_type & GOT_TLS_GDESC)
3064e1ff
JB		 17069 {
17070 elf32_arm_allocate_dynrelocs (info,
17071 htab->root.srelplt, 1);
17072 htab->tls_trampoline = -1;
17073 }
0855e32b 17074 }
5e681ec4
PB		 17075 }
17076 else
17077 *local_got = (bfd_vma) -1;
17078 }
252b5132
RH		 17079 }
17080
ba93b8ac
DJ		 17081 if (htab->tls_ldm_got.refcount > 0)
17082 {
17083 /* Allocate two GOT entries and one dynamic relocation (if necessary)
5c5a4843 17084 for R_ARM_TLS_LDM32/R_ARM_TLS_LDM32_FDPIC relocations. */
362d30a1
RS		 17085 htab->tls_ldm_got.offset = htab->root.sgot->size;
17086 htab->root.sgot->size += 8;
0e1862bb 17087 if (bfd_link_pic (info))
47beaa6a 17088 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
ba93b8ac
DJ		 17089 }
17090 else
17091 htab->tls_ldm_got.offset = -1;
17092
e8b09b87
CL		 17093 /* At the very end of the .rofixup section is a pointer to the GOT,
17094 reserve space for it. */
17095 if (htab->fdpic_p && htab->srofixup != NULL)
17096 htab->srofixup->size += 4;
17097
5e681ec4
PB		 17098 /* Allocate global sym .plt and .got entries, and space for global
17099 sym dynamic relocs. */
47beaa6a 17100 elf_link_hash_traverse (& htab->root, allocate_dynrelocs_for_symbol, info);
252b5132 17101
d504ffc8 17102 /* Here we rummage through the found bfds to collect glue information. */
c72f2fb2 17103 for (ibfd = info->input_bfds; ibfd != NULL; ibfd = ibfd->link.next)
c7b8f16e 17104 {
0ffa91dd 17105 if (! is_arm_elf (ibfd))
e44a2c9c
AM		 17106 continue;
17107
c7b8f16e
JB		 17108 /* Initialise mapping tables for code/data. */
17109 bfd_elf32_arm_init_maps (ibfd);
906e58ca 17110
c7b8f16e 17111 if (!bfd_elf32_arm_process_before_allocation (ibfd, info)
a504d23a
LA		 17112 || !bfd_elf32_arm_vfp11_erratum_scan (ibfd, info)
17113 || !bfd_elf32_arm_stm32l4xx_erratum_scan (ibfd, info))
90b6238f 17114 _bfd_error_handler (_("errors encountered processing file %pB"), ibfd);
c7b8f16e 17115 }
d504ffc8 17116
3e6b1042
DJ		 17117 /* Allocate space for the glue sections now that we've sized them. */
17118 bfd_elf32_arm_allocate_interworking_sections (info);
17119
0855e32b
NS		 17120 /* For every jump slot reserved in the sgotplt, reloc_count is
17121 incremented. However, when we reserve space for TLS descriptors,
17122 it's not incremented, so in order to compute the space reserved
17123 for them, it suffices to multiply the reloc count by the jump
17124 slot size. */
17125 if (htab->root.srelplt)
17126 htab->sgotplt_jump_table_size = elf32_arm_compute_jump_table_size(htab);
17127
17128 if (htab->tls_trampoline)
17129 {
17130 if (htab->root.splt->size == 0)
17131 htab->root.splt->size += htab->plt_header_size;
b38cadfb 17132
0855e32b
NS		 17133 htab->tls_trampoline = htab->root.splt->size;
17134 htab->root.splt->size += htab->plt_entry_size;
b38cadfb 17135
0855e32b 17136 /* If we're not using lazy TLS relocations, don't generate the
99059e56 17137 PLT and GOT entries they require. */
0855e32b
NS		 17138 if (!(info->flags & DF_BIND_NOW))
17139 {
17140 htab->dt_tlsdesc_got = htab->root.sgot->size;
17141 htab->root.sgot->size += 4;
17142
17143 htab->dt_tlsdesc_plt = htab->root.splt->size;
17144 htab->root.splt->size += 4 * ARRAY_SIZE (dl_tlsdesc_lazy_trampoline);
17145 }
17146 }
17147
252b5132
RH		 17148 /* The check_relocs and adjust_dynamic_symbol entry points have
17149 determined the sizes of the various dynamic sections. Allocate
17150 memory for them. */
b34976b6
AM		 17151 plt = FALSE;
17152 relocs = FALSE;
252b5132
RH		 17153 for (s = dynobj->sections; s != NULL; s = s->next)
17154 {
17155 const char * name;
252b5132
RH		 17156
17157 if ((s->flags & SEC_LINKER_CREATED) == 0)
17158 continue;
17159
17160 /* It's OK to base decisions on the section name, because none
17161 of the dynobj section names depend upon the input files. */
17162 name = bfd_get_section_name (dynobj, s);
17163
34e77a92 17164 if (s == htab->root.splt)
252b5132 17165 {
c456f082
AM		 17166 /* Remember whether there is a PLT. */
17167 plt = s->size != 0;
252b5132 17168 }
0112cd26 17169 else if (CONST_STRNEQ (name, ".rel"))
252b5132 17170 {
c456f082 17171 if (s->size != 0)
252b5132 17172 {
252b5132 17173 /* Remember whether there are any reloc sections other
00a97672 17174 than .rel(a).plt and .rela.plt.unloaded. */
362d30a1 17175 if (s != htab->root.srelplt && s != htab->srelplt2)
b34976b6 17176 relocs = TRUE;
252b5132
RH		 17177
17178 /* We use the reloc_count field as a counter if we need
17179 to copy relocs into the output file. */
17180 s->reloc_count = 0;
17181 }
17182 }
34e77a92
RS		 17183 else if (s != htab->root.sgot
17184 && s != htab->root.sgotplt
17185 && s != htab->root.iplt
17186 && s != htab->root.igotplt
5474d94f 17187 && s != htab->root.sdynbss
e8b09b87
CL		 17188 && s != htab->root.sdynrelro
17189 && s != htab->srofixup)
252b5132
RH		 17190 {
17191 /* It's not one of our sections, so don't allocate space. */
17192 continue;
17193 }
17194
c456f082 17195 if (s->size == 0)
252b5132 17196 {
c456f082 17197 /* If we don't need this section, strip it from the
00a97672
RS		 17198 output file. This is mostly to handle .rel(a).bss and
17199 .rel(a).plt. We must create both sections in
c456f082
AM		 17200 create_dynamic_sections, because they must be created
17201 before the linker maps input sections to output
17202 sections. The linker does that before
17203 adjust_dynamic_symbol is called, and it is that
17204 function which decides whether anything needs to go
17205 into these sections. */
8423293d 17206 s->flags |= SEC_EXCLUDE;
252b5132
RH		 17207 continue;
17208 }
17209
c456f082
AM		 17210 if ((s->flags & SEC_HAS_CONTENTS) == 0)
17211 continue;
17212
252b5132 17213 /* Allocate memory for the section contents. */
21d799b5 17214 s->contents = (unsigned char *) bfd_zalloc (dynobj, s->size);
c456f082 17215 if (s->contents == NULL)
b34976b6 17216 return FALSE;
252b5132
RH		 17217 }
17218
17219 if (elf_hash_table (info)->dynamic_sections_created)
17220 {
17221 /* Add some entries to the .dynamic section. We fill in the
17222 values later, in elf32_arm_finish_dynamic_sections, but we
17223 must add the entries now so that we get the correct size for
17224 the .dynamic section. The DT_DEBUG entry is filled in by the
17225 dynamic linker and used by the debugger. */
dc810e39 17226#define add_dynamic_entry(TAG, VAL) \
5a580b3a 17227 _bfd_elf_add_dynamic_entry (info, TAG, VAL)
dc810e39 17228
0e1862bb 17229 if (bfd_link_executable (info))
252b5132 17230 {
dc810e39 17231 if (!add_dynamic_entry (DT_DEBUG, 0))
b34976b6 17232 return FALSE;
252b5132
RH		 17233 }
17234
17235 if (plt)
17236 {
dc810e39
AM		 17237 if ( !add_dynamic_entry (DT_PLTGOT, 0)
17238 || !add_dynamic_entry (DT_PLTRELSZ, 0)
00a97672
RS		 17239 || !add_dynamic_entry (DT_PLTREL,
17240 htab->use_rel ? DT_REL : DT_RELA)
dc810e39 17241 || !add_dynamic_entry (DT_JMPREL, 0))
b34976b6 17242 return FALSE;
0855e32b 17243
5025eb7c
AO		 17244 if (htab->dt_tlsdesc_plt
17245 && (!add_dynamic_entry (DT_TLSDESC_PLT,0)
17246 || !add_dynamic_entry (DT_TLSDESC_GOT,0)))
b38cadfb 17247 return FALSE;
252b5132
RH		 17248 }
17249
17250 if (relocs)
17251 {
00a97672
RS		 17252 if (htab->use_rel)
17253 {
17254 if (!add_dynamic_entry (DT_REL, 0)
17255 || !add_dynamic_entry (DT_RELSZ, 0)
17256 || !add_dynamic_entry (DT_RELENT, RELOC_SIZE (htab)))
17257 return FALSE;
17258 }
17259 else
17260 {
17261 if (!add_dynamic_entry (DT_RELA, 0)
17262 || !add_dynamic_entry (DT_RELASZ, 0)
17263 || !add_dynamic_entry (DT_RELAENT, RELOC_SIZE (htab)))
17264 return FALSE;
17265 }
252b5132
RH		 17266 }
17267
08d1f311
DJ		 17268 /* If any dynamic relocs apply to a read-only section,
17269 then we need a DT_TEXTREL entry. */
17270 if ((info->flags & DF_TEXTREL) == 0)
63c1f59d 17271 elf_link_hash_traverse (&htab->root, maybe_set_textrel, info);
08d1f311 17272
99e4ae17 17273 if ((info->flags & DF_TEXTREL) != 0)
252b5132 17274 {
dc810e39 17275 if (!add_dynamic_entry (DT_TEXTREL, 0))
b34976b6 17276 return FALSE;
252b5132 17277 }
7a2b07ff
NS		 17278 if (htab->vxworks_p
17279 && !elf_vxworks_add_dynamic_entries (output_bfd, info))
17280 return FALSE;
252b5132 17281 }
8532796c 17282#undef add_dynamic_entry
252b5132 17283
b34976b6 17284 return TRUE;
252b5132
RH		 17285}
17286
0855e32b
NS		 17287/* Size sections even though they're not dynamic. We use it to setup
17288 _TLS_MODULE_BASE_, if needed. */
17289
17290static bfd_boolean
17291elf32_arm_always_size_sections (bfd *output_bfd,
99059e56 17292 struct bfd_link_info *info)
0855e32b
NS		 17293{
17294 asection *tls_sec;
cb10292c
CL		 17295 struct elf32_arm_link_hash_table *htab;
17296
17297 htab = elf32_arm_hash_table (info);
0855e32b 17298
0e1862bb 17299 if (bfd_link_relocatable (info))
0855e32b
NS		 17300 return TRUE;
17301
17302 tls_sec = elf_hash_table (info)->tls_sec;
17303
17304 if (tls_sec)
17305 {
17306 struct elf_link_hash_entry *tlsbase;
17307
17308 tlsbase = elf_link_hash_lookup
17309 (elf_hash_table (info), "_TLS_MODULE_BASE_", TRUE, TRUE, FALSE);
17310
17311 if (tlsbase)
99059e56
RM		 17312 {
17313 struct bfd_link_hash_entry *bh = NULL;
0855e32b 17314 const struct elf_backend_data *bed
99059e56 17315 = get_elf_backend_data (output_bfd);
0855e32b 17316
99059e56 17317 if (!(_bfd_generic_link_add_one_symbol
0855e32b
NS		 17318 (info, output_bfd, "_TLS_MODULE_BASE_", BSF_LOCAL,
17319 tls_sec, 0, NULL, FALSE,
17320 bed->collect, &bh)))
17321 return FALSE;
b38cadfb 17322
99059e56
RM		 17323 tlsbase->type = STT_TLS;
17324 tlsbase = (struct elf_link_hash_entry *)bh;
17325 tlsbase->def_regular = 1;
17326 tlsbase->other = STV_HIDDEN;
17327 (*bed->elf_backend_hide_symbol) (info, tlsbase, TRUE);
0855e32b
NS		 17328 }
17329 }
cb10292c
CL		 17330
17331 if (htab->fdpic_p && !bfd_link_relocatable (info)
17332 && !bfd_elf_stack_segment_size (output_bfd, info,
17333 "__stacksize", DEFAULT_STACK_SIZE))
17334 return FALSE;
17335
0855e32b
NS		 17336 return TRUE;
17337}
17338
252b5132
RH		 17339/* Finish up dynamic symbol handling. We set the contents of various
17340 dynamic sections here. */
17341
b34976b6 17342static bfd_boolean
906e58ca
NC		 17343elf32_arm_finish_dynamic_symbol (bfd * output_bfd,
17344 struct bfd_link_info * info,
17345 struct elf_link_hash_entry * h,
17346 Elf_Internal_Sym * sym)
252b5132 17347{
e5a52504 17348 struct elf32_arm_link_hash_table *htab;
b7693d02 17349 struct elf32_arm_link_hash_entry *eh;
252b5132 17350
e5a52504 17351 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 17352 if (htab == NULL)
17353 return FALSE;
17354
b7693d02 17355 eh = (struct elf32_arm_link_hash_entry *) h;
252b5132
RH		 17356
17357 if (h->plt.offset != (bfd_vma) -1)
17358 {
34e77a92 17359 if (!eh->is_iplt)
e5a52504 17360 {
34e77a92 17361 BFD_ASSERT (h->dynindx != -1);
57460bcf
NC		 17362 if (! elf32_arm_populate_plt_entry (output_bfd, info, &h->plt, &eh->plt,
17363 h->dynindx, 0))
17364 return FALSE;
e5a52504 17365 }
57e8b36a 17366
f5385ebf 17367 if (!h->def_regular)
252b5132
RH		 17368 {
17369 /* Mark the symbol as undefined, rather than as defined in
3a635617 17370 the .plt section. */
252b5132 17371 sym->st_shndx = SHN_UNDEF;
3a635617 17372 /* If the symbol is weak we need to clear the value.
d982ba73
PB		 17373 Otherwise, the PLT entry would provide a definition for
17374 the symbol even if the symbol wasn't defined anywhere,
3a635617
WN		 17375 and so the symbol would never be NULL. Leave the value if
17376 there were any relocations where pointer equality matters
17377 (this is a clue for the dynamic linker, to make function
17378 pointer comparisons work between an application and shared
17379 library). */
97323ad1 17380 if (!h->ref_regular_nonweak || !h->pointer_equality_needed)
d982ba73 17381 sym->st_value = 0;
252b5132 17382 }
34e77a92
RS		 17383 else if (eh->is_iplt && eh->plt.noncall_refcount != 0)
17384 {
17385 /* At least one non-call relocation references this .iplt entry,
17386 so the .iplt entry is the function's canonical address. */
17387 sym->st_info = ELF_ST_INFO (ELF_ST_BIND (sym->st_info), STT_FUNC);
39d911fc 17388 ARM_SET_SYM_BRANCH_TYPE (sym->st_target_internal, ST_BRANCH_TO_ARM);
34e77a92
RS		 17389 sym->st_shndx = (_bfd_elf_section_from_bfd_section
17390 (output_bfd, htab->root.iplt->output_section));
17391 sym->st_value = (h->plt.offset
17392 + htab->root.iplt->output_section->vma
17393 + htab->root.iplt->output_offset);
17394 }
252b5132
RH		 17395 }
17396
f5385ebf 17397 if (h->needs_copy)
252b5132
RH		 17398 {
17399 asection * s;
947216bf 17400 Elf_Internal_Rela rel;
252b5132
RH		 17401
17402 /* This symbol needs a copy reloc. Set it up. */
252b5132
RH		 17403 BFD_ASSERT (h->dynindx != -1
17404 && (h->root.type == bfd_link_hash_defined
17405 || h->root.type == bfd_link_hash_defweak));
17406
00a97672 17407 rel.r_addend = 0;
252b5132
RH		 17408 rel.r_offset = (h->root.u.def.value
17409 + h->root.u.def.section->output_section->vma
17410 + h->root.u.def.section->output_offset);
17411 rel.r_info = ELF32_R_INFO (h->dynindx, R_ARM_COPY);
afbf7e8e 17412 if (h->root.u.def.section == htab->root.sdynrelro)
5474d94f
AM		 17413 s = htab->root.sreldynrelro;
17414 else
17415 s = htab->root.srelbss;
47beaa6a 17416 elf32_arm_add_dynreloc (output_bfd, info, s, &rel);
252b5132
RH		 17417 }
17418
00a97672 17419 /* Mark _DYNAMIC and _GLOBAL_OFFSET_TABLE_ as absolute. On VxWorks,
fac7bd64
CL		 17420 and for FDPIC, the _GLOBAL_OFFSET_TABLE_ symbol is not absolute:
17421 it is relative to the ".got" section. */
9637f6ef 17422 if (h == htab->root.hdynamic
fac7bd64 17423 || (!htab->fdpic_p && !htab->vxworks_p && h == htab->root.hgot))
252b5132
RH		 17424 sym->st_shndx = SHN_ABS;
17425
b34976b6 17426 return TRUE;
252b5132
RH		 17427}
17428
0855e32b
NS		 17429static void
17430arm_put_trampoline (struct elf32_arm_link_hash_table *htab, bfd *output_bfd,
17431 void *contents,
17432 const unsigned long *template, unsigned count)
17433{
17434 unsigned ix;
b38cadfb 17435
0855e32b
NS		 17436 for (ix = 0; ix != count; ix++)
17437 {
17438 unsigned long insn = template[ix];
17439
17440 /* Emit mov pc,rx if bx is not permitted. */
17441 if (htab->fix_v4bx == 1 && (insn & 0x0ffffff0) == 0x012fff10)
17442 insn = (insn & 0xf000000f) | 0x01a0f000;
17443 put_arm_insn (htab, output_bfd, insn, (char *)contents + ix*4);
17444 }
17445}
17446
99059e56
RM		 17447/* Install the special first PLT entry for elf32-arm-nacl. Unlike
17448 other variants, NaCl needs this entry in a static executable's
17449 .iplt too. When we're handling that case, GOT_DISPLACEMENT is
17450 zero. For .iplt really only the last bundle is useful, and .iplt
17451 could have a shorter first entry, with each individual PLT entry's
17452 relative branch calculated differently so it targets the last
17453 bundle instead of the instruction before it (labelled .Lplt_tail
17454 above). But it's simpler to keep the size and layout of PLT0
17455 consistent with the dynamic case, at the cost of some dead code at
17456 the start of .iplt and the one dead store to the stack at the start
17457 of .Lplt_tail. */
17458static void
17459arm_nacl_put_plt0 (struct elf32_arm_link_hash_table *htab, bfd *output_bfd,
17460 asection *plt, bfd_vma got_displacement)
17461{
17462 unsigned int i;
17463
17464 put_arm_insn (htab, output_bfd,
17465 elf32_arm_nacl_plt0_entry[0]
17466 | arm_movw_immediate (got_displacement),
17467 plt->contents + 0);
17468 put_arm_insn (htab, output_bfd,
17469 elf32_arm_nacl_plt0_entry[1]
17470 | arm_movt_immediate (got_displacement),
17471 plt->contents + 4);
17472
17473 for (i = 2; i < ARRAY_SIZE (elf32_arm_nacl_plt0_entry); ++i)
17474 put_arm_insn (htab, output_bfd,
17475 elf32_arm_nacl_plt0_entry[i],
17476 plt->contents + (i * 4));
17477}
17478
252b5132
RH		 17479/* Finish up the dynamic sections. */
17480
b34976b6 17481static bfd_boolean
57e8b36a 17482elf32_arm_finish_dynamic_sections (bfd * output_bfd, struct bfd_link_info * info)
252b5132
RH		 17483{
17484 bfd * dynobj;
17485 asection * sgot;
17486 asection * sdyn;
4dfe6ac6
NC		 17487 struct elf32_arm_link_hash_table *htab;
17488
17489 htab = elf32_arm_hash_table (info);
17490 if (htab == NULL)
17491 return FALSE;
252b5132
RH		 17492
17493 dynobj = elf_hash_table (info)->dynobj;
17494
362d30a1 17495 sgot = htab->root.sgotplt;
894891db
NC		 17496 /* A broken linker script might have discarded the dynamic sections.
17497 Catch this here so that we do not seg-fault later on. */
17498 if (sgot != NULL && bfd_is_abs_section (sgot->output_section))
17499 return FALSE;
3d4d4302 17500 sdyn = bfd_get_linker_section (dynobj, ".dynamic");
252b5132
RH		 17501
17502 if (elf_hash_table (info)->dynamic_sections_created)
17503 {
17504 asection *splt;
17505 Elf32_External_Dyn *dyncon, *dynconend;
17506
362d30a1 17507 splt = htab->root.splt;
24a1ba0f 17508 BFD_ASSERT (splt != NULL && sdyn != NULL);
cbc704f3 17509 BFD_ASSERT (htab->symbian_p || sgot != NULL);
252b5132
RH		 17510
17511 dyncon = (Elf32_External_Dyn *) sdyn->contents;
eea6121a 17512 dynconend = (Elf32_External_Dyn *) (sdyn->contents + sdyn->size);
9b485d32 17513
252b5132
RH		 17514 for (; dyncon < dynconend; dyncon++)
17515 {
17516 Elf_Internal_Dyn dyn;
17517 const char * name;
17518 asection * s;
17519
17520 bfd_elf32_swap_dyn_in (dynobj, dyncon, &dyn);
17521
17522 switch (dyn.d_tag)
17523 {
229fcec5
MM		 17524 unsigned int type;
17525
252b5132 17526 default:
7a2b07ff
NS		 17527 if (htab->vxworks_p
17528 && elf_vxworks_finish_dynamic_entry (output_bfd, &dyn))
17529 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
252b5132
RH		 17530 break;
17531
229fcec5
MM		 17532 case DT_HASH:
17533 name = ".hash";
17534 goto get_vma_if_bpabi;
17535 case DT_STRTAB:
17536 name = ".dynstr";
17537 goto get_vma_if_bpabi;
17538 case DT_SYMTAB:
17539 name = ".dynsym";
17540 goto get_vma_if_bpabi;
c0042f5d
MM		 17541 case DT_VERSYM:
17542 name = ".gnu.version";
17543 goto get_vma_if_bpabi;
17544 case DT_VERDEF:
17545 name = ".gnu.version_d";
17546 goto get_vma_if_bpabi;
17547 case DT_VERNEED:
17548 name = ".gnu.version_r";
17549 goto get_vma_if_bpabi;
17550
252b5132 17551 case DT_PLTGOT:
4ade44b7 17552 name = htab->symbian_p ? ".got" : ".got.plt";
252b5132
RH		 17553 goto get_vma;
17554 case DT_JMPREL:
00a97672 17555 name = RELOC_SECTION (htab, ".plt");
252b5132 17556 get_vma:
4ade44b7 17557 s = bfd_get_linker_section (dynobj, name);
05456594
NC		 17558 if (s == NULL)
17559 {
4eca0228 17560 _bfd_error_handler
4ade44b7 17561 (_("could not find section %s"), name);
05456594
NC		 17562 bfd_set_error (bfd_error_invalid_operation);
17563 return FALSE;
17564 }
229fcec5 17565 if (!htab->symbian_p)
4ade44b7 17566 dyn.d_un.d_ptr = s->output_section->vma + s->output_offset;
229fcec5
MM		 17567 else
17568 /* In the BPABI, tags in the PT_DYNAMIC section point
17569 at the file offset, not the memory address, for the
17570 convenience of the post linker. */
4ade44b7 17571 dyn.d_un.d_ptr = s->output_section->filepos + s->output_offset;
252b5132
RH		 17572 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
17573 break;
17574
229fcec5
MM		 17575 get_vma_if_bpabi:
17576 if (htab->symbian_p)
17577 goto get_vma;
17578 break;
17579
252b5132 17580 case DT_PLTRELSZ:
362d30a1 17581 s = htab->root.srelplt;
252b5132 17582 BFD_ASSERT (s != NULL);
eea6121a 17583 dyn.d_un.d_val = s->size;
252b5132
RH		 17584 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
17585 break;
906e58ca 17586
252b5132 17587 case DT_RELSZ:
00a97672 17588 case DT_RELASZ:
229fcec5
MM		 17589 case DT_REL:
17590 case DT_RELA:
229fcec5
MM		 17591 /* In the BPABI, the DT_REL tag must point at the file
17592 offset, not the VMA, of the first relocation
17593 section. So, we use code similar to that in
17594 elflink.c, but do not check for SHF_ALLOC on the
64f52338
AM		 17595 relocation section, since relocation sections are
17596 never allocated under the BPABI. PLT relocs are also
17597 included. */
229fcec5
MM		 17598 if (htab->symbian_p)
17599 {
17600 unsigned int i;
17601 type = ((dyn.d_tag == DT_REL || dyn.d_tag == DT_RELSZ)
17602 ? SHT_REL : SHT_RELA);
17603 dyn.d_un.d_val = 0;
17604 for (i = 1; i < elf_numsections (output_bfd); i++)
17605 {
906e58ca 17606 Elf_Internal_Shdr *hdr
229fcec5
MM		 17607 = elf_elfsections (output_bfd)[i];
17608 if (hdr->sh_type == type)
17609 {
906e58ca 17610 if (dyn.d_tag == DT_RELSZ
229fcec5
MM		 17611 || dyn.d_tag == DT_RELASZ)
17612 dyn.d_un.d_val += hdr->sh_size;
de52dba4
AM		 17613 else if ((ufile_ptr) hdr->sh_offset
17614 <= dyn.d_un.d_val - 1)
229fcec5
MM		 17615 dyn.d_un.d_val = hdr->sh_offset;
17616 }
17617 }
17618 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
17619 }
252b5132 17620 break;
88f7bcd5 17621
0855e32b 17622 case DT_TLSDESC_PLT:
99059e56 17623 s = htab->root.splt;
0855e32b
NS		 17624 dyn.d_un.d_ptr = (s->output_section->vma + s->output_offset
17625 + htab->dt_tlsdesc_plt);
17626 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
17627 break;
17628
17629 case DT_TLSDESC_GOT:
99059e56 17630 s = htab->root.sgot;
0855e32b 17631 dyn.d_un.d_ptr = (s->output_section->vma + s->output_offset
99059e56 17632 + htab->dt_tlsdesc_got);
0855e32b
NS		 17633 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
17634 break;
17635
88f7bcd5
NC		 17636 /* Set the bottom bit of DT_INIT/FINI if the
17637 corresponding function is Thumb. */
17638 case DT_INIT:
17639 name = info->init_function;
17640 goto get_sym;
17641 case DT_FINI:
17642 name = info->fini_function;
17643 get_sym:
17644 /* If it wasn't set by elf_bfd_final_link
4cc11e76 17645 then there is nothing to adjust. */
88f7bcd5
NC		 17646 if (dyn.d_un.d_val != 0)
17647 {
17648 struct elf_link_hash_entry * eh;
17649
17650 eh = elf_link_hash_lookup (elf_hash_table (info), name,
b34976b6 17651 FALSE, FALSE, TRUE);
39d911fc
TP		 17652 if (eh != NULL
17653 && ARM_GET_SYM_BRANCH_TYPE (eh->target_internal)
17654 == ST_BRANCH_TO_THUMB)
88f7bcd5
NC		 17655 {
17656 dyn.d_un.d_val |= 1;
b34976b6 17657 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
88f7bcd5
NC		 17658 }
17659 }
17660 break;
252b5132
RH		 17661 }
17662 }
17663
24a1ba0f 17664 /* Fill in the first entry in the procedure linkage table. */
4dfe6ac6 17665 if (splt->size > 0 && htab->plt_header_size)
f7a74f8c 17666 {
00a97672
RS		 17667 const bfd_vma *plt0_entry;
17668 bfd_vma got_address, plt_address, got_displacement;
17669
17670 /* Calculate the addresses of the GOT and PLT. */
17671 got_address = sgot->output_section->vma + sgot->output_offset;
17672 plt_address = splt->output_section->vma + splt->output_offset;
17673
17674 if (htab->vxworks_p)
17675 {
17676 /* The VxWorks GOT is relocated by the dynamic linker.
17677 Therefore, we must emit relocations rather than simply
17678 computing the values now. */
17679 Elf_Internal_Rela rel;
17680
17681 plt0_entry = elf32_arm_vxworks_exec_plt0_entry;
52ab56c2
PB		 17682 put_arm_insn (htab, output_bfd, plt0_entry[0],
17683 splt->contents + 0);
17684 put_arm_insn (htab, output_bfd, plt0_entry[1],
17685 splt->contents + 4);
17686 put_arm_insn (htab, output_bfd, plt0_entry[2],
17687 splt->contents + 8);
00a97672
RS		 17688 bfd_put_32 (output_bfd, got_address, splt->contents + 12);
17689
8029a119 17690 /* Generate a relocation for _GLOBAL_OFFSET_TABLE_. */
00a97672
RS		 17691 rel.r_offset = plt_address + 12;
17692 rel.r_info = ELF32_R_INFO (htab->root.hgot->indx, R_ARM_ABS32);
17693 rel.r_addend = 0;
17694 SWAP_RELOC_OUT (htab) (output_bfd, &rel,
17695 htab->srelplt2->contents);
17696 }
b38cadfb 17697 else if (htab->nacl_p)
99059e56
RM		 17698 arm_nacl_put_plt0 (htab, output_bfd, splt,
17699 got_address + 8 - (plt_address + 16));
eed94f8f
NC		 17700 else if (using_thumb_only (htab))
17701 {
17702 got_displacement = got_address - (plt_address + 12);
17703
17704 plt0_entry = elf32_thumb2_plt0_entry;
17705 put_arm_insn (htab, output_bfd, plt0_entry[0],
17706 splt->contents + 0);
17707 put_arm_insn (htab, output_bfd, plt0_entry[1],
17708 splt->contents + 4);
17709 put_arm_insn (htab, output_bfd, plt0_entry[2],
17710 splt->contents + 8);
17711
17712 bfd_put_32 (output_bfd, got_displacement, splt->contents + 12);
17713 }
00a97672
RS		 17714 else
17715 {
17716 got_displacement = got_address - (plt_address + 16);
17717
17718 plt0_entry = elf32_arm_plt0_entry;
52ab56c2
PB		 17719 put_arm_insn (htab, output_bfd, plt0_entry[0],
17720 splt->contents + 0);
17721 put_arm_insn (htab, output_bfd, plt0_entry[1],
17722 splt->contents + 4);
17723 put_arm_insn (htab, output_bfd, plt0_entry[2],
17724 splt->contents + 8);
17725 put_arm_insn (htab, output_bfd, plt0_entry[3],
17726 splt->contents + 12);
5e681ec4 17727
5e681ec4 17728#ifdef FOUR_WORD_PLT
00a97672
RS		 17729 /* The displacement value goes in the otherwise-unused
17730 last word of the second entry. */
17731 bfd_put_32 (output_bfd, got_displacement, splt->contents + 28);
5e681ec4 17732#else
00a97672 17733 bfd_put_32 (output_bfd, got_displacement, splt->contents + 16);
5e681ec4 17734#endif
00a97672 17735 }
f7a74f8c 17736 }
252b5132
RH		 17737
17738 /* UnixWare sets the entsize of .plt to 4, although that doesn't
17739 really seem like the right value. */
74541ad4
AM		 17740 if (splt->output_section->owner == output_bfd)
17741 elf_section_data (splt->output_section)->this_hdr.sh_entsize = 4;
00a97672 17742
0855e32b
NS		 17743 if (htab->dt_tlsdesc_plt)
17744 {
17745 bfd_vma got_address
17746 = sgot->output_section->vma + sgot->output_offset;
17747 bfd_vma gotplt_address = (htab->root.sgot->output_section->vma
17748 + htab->root.sgot->output_offset);
17749 bfd_vma plt_address
17750 = splt->output_section->vma + splt->output_offset;
17751
b38cadfb 17752 arm_put_trampoline (htab, output_bfd,
0855e32b
NS		 17753 splt->contents + htab->dt_tlsdesc_plt,
17754 dl_tlsdesc_lazy_trampoline, 6);
17755
17756 bfd_put_32 (output_bfd,
17757 gotplt_address + htab->dt_tlsdesc_got
17758 - (plt_address + htab->dt_tlsdesc_plt)
17759 - dl_tlsdesc_lazy_trampoline[6],
17760 splt->contents + htab->dt_tlsdesc_plt + 24);
17761 bfd_put_32 (output_bfd,
17762 got_address - (plt_address + htab->dt_tlsdesc_plt)
17763 - dl_tlsdesc_lazy_trampoline[7],
17764 splt->contents + htab->dt_tlsdesc_plt + 24 + 4);
17765 }
17766
17767 if (htab->tls_trampoline)
17768 {
b38cadfb 17769 arm_put_trampoline (htab, output_bfd,
0855e32b
NS		 17770 splt->contents + htab->tls_trampoline,
17771 tls_trampoline, 3);
17772#ifdef FOUR_WORD_PLT
17773 bfd_put_32 (output_bfd, 0x00000000,
17774 splt->contents + htab->tls_trampoline + 12);
b38cadfb 17775#endif
0855e32b
NS		 17776 }
17777
0e1862bb
L		 17778 if (htab->vxworks_p
17779 && !bfd_link_pic (info)
17780 && htab->root.splt->size > 0)
00a97672
RS		 17781 {
17782 /* Correct the .rel(a).plt.unloaded relocations. They will have
17783 incorrect symbol indexes. */
17784 int num_plts;
eed62c48 17785 unsigned char *p;
00a97672 17786
362d30a1 17787 num_plts = ((htab->root.splt->size - htab->plt_header_size)
00a97672
RS		 17788 / htab->plt_entry_size);
17789 p = htab->srelplt2->contents + RELOC_SIZE (htab);
17790
17791 for (; num_plts; num_plts--)
17792 {
17793 Elf_Internal_Rela rel;
17794
17795 SWAP_RELOC_IN (htab) (output_bfd, p, &rel);
17796 rel.r_info = ELF32_R_INFO (htab->root.hgot->indx, R_ARM_ABS32);
17797 SWAP_RELOC_OUT (htab) (output_bfd, &rel, p);
17798 p += RELOC_SIZE (htab);
17799
17800 SWAP_RELOC_IN (htab) (output_bfd, p, &rel);
17801 rel.r_info = ELF32_R_INFO (htab->root.hplt->indx, R_ARM_ABS32);
17802 SWAP_RELOC_OUT (htab) (output_bfd, &rel, p);
17803 p += RELOC_SIZE (htab);
17804 }
17805 }
252b5132
RH		 17806 }
17807
99059e56
RM		 17808 if (htab->nacl_p && htab->root.iplt != NULL && htab->root.iplt->size > 0)
17809 /* NaCl uses a special first entry in .iplt too. */
17810 arm_nacl_put_plt0 (htab, output_bfd, htab->root.iplt, 0);
17811
252b5132 17812 /* Fill in the first three entries in the global offset table. */
229fcec5 17813 if (sgot)
252b5132 17814 {
229fcec5
MM		 17815 if (sgot->size > 0)
17816 {
17817 if (sdyn == NULL)
17818 bfd_put_32 (output_bfd, (bfd_vma) 0, sgot->contents);
17819 else
17820 bfd_put_32 (output_bfd,
17821 sdyn->output_section->vma + sdyn->output_offset,
17822 sgot->contents);
17823 bfd_put_32 (output_bfd, (bfd_vma) 0, sgot->contents + 4);
17824 bfd_put_32 (output_bfd, (bfd_vma) 0, sgot->contents + 8);
17825 }
252b5132 17826
229fcec5
MM		 17827 elf_section_data (sgot->output_section)->this_hdr.sh_entsize = 4;
17828 }
252b5132 17829
e8b09b87
CL		 17830 /* At the very end of the .rofixup section is a pointer to the GOT. */
17831 if (htab->fdpic_p && htab->srofixup != NULL)
17832 {
17833 struct elf_link_hash_entry *hgot = htab->root.hgot;
17834
17835 bfd_vma got_value = hgot->root.u.def.value
17836 + hgot->root.u.def.section->output_section->vma
17837 + hgot->root.u.def.section->output_offset;
17838
17839 arm_elf_add_rofixup(output_bfd, htab->srofixup, got_value);
17840
17841 /* Make sure we allocated and generated the same number of fixups. */
17842 BFD_ASSERT (htab->srofixup->reloc_count * 4 == htab->srofixup->size);
17843 }
17844
b34976b6 17845 return TRUE;
252b5132
RH		 17846}
17847
ba96a88f 17848static void
57e8b36a 17849elf32_arm_post_process_headers (bfd * abfd, struct bfd_link_info * link_info ATTRIBUTE_UNUSED)
ba96a88f 17850{
9b485d32 17851 Elf_Internal_Ehdr * i_ehdrp; /* ELF file header, internal form. */
e489d0ae 17852 struct elf32_arm_link_hash_table *globals;
ac4c9b04 17853 struct elf_segment_map *m;
ba96a88f
NC		 17854
17855 i_ehdrp = elf_elfheader (abfd);
17856
94a3258f
PB		 17857 if (EF_ARM_EABI_VERSION (i_ehdrp->e_flags) == EF_ARM_EABI_UNKNOWN)
17858 i_ehdrp->e_ident[EI_OSABI] = ELFOSABI_ARM;
17859 else
7394f108 17860 _bfd_elf_post_process_headers (abfd, link_info);
ba96a88f 17861 i_ehdrp->e_ident[EI_ABIVERSION] = ARM_ELF_ABI_VERSION;
e489d0ae 17862
93204d3a
PB		 17863 if (link_info)
17864 {
17865 globals = elf32_arm_hash_table (link_info);
4dfe6ac6 17866 if (globals != NULL && globals->byteswap_code)
93204d3a 17867 i_ehdrp->e_flags |= EF_ARM_BE8;
18a20338
CL		 17868
17869 if (globals->fdpic_p)
17870 i_ehdrp->e_ident[EI_OSABI] |= ELFOSABI_ARM_FDPIC;
93204d3a 17871 }
3bfcb652
NC		 17872
17873 if (EF_ARM_EABI_VERSION (i_ehdrp->e_flags) == EF_ARM_EABI_VER5
17874 && ((i_ehdrp->e_type == ET_DYN) || (i_ehdrp->e_type == ET_EXEC)))
17875 {
17876 int abi = bfd_elf_get_obj_attr_int (abfd, OBJ_ATTR_PROC, Tag_ABI_VFP_args);
5c294fee 17877 if (abi == AEABI_VFP_args_vfp)
3bfcb652
NC		 17878 i_ehdrp->e_flags |= EF_ARM_ABI_FLOAT_HARD;
17879 else
17880 i_ehdrp->e_flags |= EF_ARM_ABI_FLOAT_SOFT;
17881 }
ac4c9b04
MG		 17882
17883 /* Scan segment to set p_flags attribute if it contains only sections with
f0728ee3 17884 SHF_ARM_PURECODE flag. */
ac4c9b04
MG		 17885 for (m = elf_seg_map (abfd); m != NULL; m = m->next)
17886 {
17887 unsigned int j;
17888
17889 if (m->count == 0)
17890 continue;
17891 for (j = 0; j < m->count; j++)
17892 {
f0728ee3 17893 if (!(elf_section_flags (m->sections[j]) & SHF_ARM_PURECODE))
ac4c9b04
MG		 17894 break;
17895 }
17896 if (j == m->count)
17897 {
17898 m->p_flags = PF_X;
17899 m->p_flags_valid = 1;
17900 }
17901 }
ba96a88f
NC		 17902}
17903
99e4ae17 17904static enum elf_reloc_type_class
7e612e98
AM		 17905elf32_arm_reloc_type_class (const struct bfd_link_info *info ATTRIBUTE_UNUSED,
17906 const asection *rel_sec ATTRIBUTE_UNUSED,
17907 const Elf_Internal_Rela *rela)
99e4ae17 17908{
f51e552e 17909 switch ((int) ELF32_R_TYPE (rela->r_info))
99e4ae17
AJ		 17910 {
17911 case R_ARM_RELATIVE:
17912 return reloc_class_relative;
17913 case R_ARM_JUMP_SLOT:
17914 return reloc_class_plt;
17915 case R_ARM_COPY:
17916 return reloc_class_copy;
109575d7
JW		 17917 case R_ARM_IRELATIVE:
17918 return reloc_class_ifunc;
99e4ae17
AJ		 17919 default:
17920 return reloc_class_normal;
17921 }
17922}
17923
e489d0ae 17924static void
cc364be6 17925arm_final_write_processing (bfd *abfd)
e16bb312 17926{
5a6c6817 17927 bfd_arm_update_notes (abfd, ARM_NOTE_SECTION);
e16bb312
NC		 17928}
17929
cc364be6
AM		 17930static bfd_boolean
17931elf32_arm_final_write_processing (bfd *abfd)
06f44071 17932{
cc364be6
AM		 17933 arm_final_write_processing (abfd);
17934 return _bfd_elf_final_write_processing (abfd);
06f44071
AM		 17935}
17936
40a18ebd
NC		 17937/* Return TRUE if this is an unwinding table entry. */
17938
17939static bfd_boolean
17940is_arm_elf_unwind_section_name (bfd * abfd ATTRIBUTE_UNUSED, const char * name)
17941{
0112cd26
NC		 17942 return (CONST_STRNEQ (name, ELF_STRING_ARM_unwind)
17943 || CONST_STRNEQ (name, ELF_STRING_ARM_unwind_once));
40a18ebd
NC		 17944}
17945
17946
17947/* Set the type and flags for an ARM section. We do this by
17948 the section name, which is a hack, but ought to work. */
17949
17950static bfd_boolean
17951elf32_arm_fake_sections (bfd * abfd, Elf_Internal_Shdr * hdr, asection * sec)
17952{
17953 const char * name;
17954
17955 name = bfd_get_section_name (abfd, sec);
17956
17957 if (is_arm_elf_unwind_section_name (abfd, name))
17958 {
17959 hdr->sh_type = SHT_ARM_EXIDX;
17960 hdr->sh_flags |= SHF_LINK_ORDER;
17961 }
ac4c9b04 17962
f0728ee3
AV		 17963 if (sec->flags & SEC_ELF_PURECODE)
17964 hdr->sh_flags |= SHF_ARM_PURECODE;
ac4c9b04 17965
40a18ebd
NC		 17966 return TRUE;
17967}
17968
6dc132d9
L		 17969/* Handle an ARM specific section when reading an object file. This is
17970 called when bfd_section_from_shdr finds a section with an unknown
17971 type. */
40a18ebd
NC		 17972
17973static bfd_boolean
17974elf32_arm_section_from_shdr (bfd *abfd,
17975 Elf_Internal_Shdr * hdr,
6dc132d9
L		 17976 const char *name,
17977 int shindex)
40a18ebd
NC		 17978{
17979 /* There ought to be a place to keep ELF backend specific flags, but
17980 at the moment there isn't one. We just keep track of the
17981 sections by their name, instead. Fortunately, the ABI gives
17982 names for all the ARM specific sections, so we will probably get
17983 away with this. */
17984 switch (hdr->sh_type)
17985 {
17986 case SHT_ARM_EXIDX:
0951f019
RE		 17987 case SHT_ARM_PREEMPTMAP:
17988 case SHT_ARM_ATTRIBUTES:
40a18ebd
NC		 17989 break;
17990
17991 default:
17992 return FALSE;
17993 }
17994
6dc132d9 17995 if (! _bfd_elf_make_section_from_shdr (abfd, hdr, name, shindex))
40a18ebd
NC		 17996 return FALSE;
17997
17998 return TRUE;
17999}
e489d0ae 18000
44444f50
NC		 18001static _arm_elf_section_data *
18002get_arm_elf_section_data (asection * sec)
18003{
47b2e99c
JZ		 18004 if (sec && sec->owner && is_arm_elf (sec->owner))
18005 return elf32_arm_section_data (sec);
44444f50
NC		 18006 else
18007 return NULL;
8e3de13a
NC		 18008}
18009
4e617b1e
PB		 18010typedef struct
18011{
57402f1e 18012 void *flaginfo;
4e617b1e 18013 struct bfd_link_info *info;
91a5743d
PB		 18014 asection *sec;
18015 int sec_shndx;
6e0b88f1
AM		 18016 int (*func) (void *, const char *, Elf_Internal_Sym *,
18017 asection *, struct elf_link_hash_entry *);
4e617b1e
PB		 18018} output_arch_syminfo;
18019
18020enum map_symbol_type
18021{
18022 ARM_MAP_ARM,
18023 ARM_MAP_THUMB,
18024 ARM_MAP_DATA
18025};
18026
18027
7413f23f 18028/* Output a single mapping symbol. */
4e617b1e
PB		 18029
18030static bfd_boolean
7413f23f
DJ		 18031elf32_arm_output_map_sym (output_arch_syminfo *osi,
18032 enum map_symbol_type type,
18033 bfd_vma offset)
4e617b1e
PB		 18034{
18035 static const char *names[3] = {"$a", "$t", "$d"};
4e617b1e
PB		 18036 Elf_Internal_Sym sym;
18037
91a5743d
PB		 18038 sym.st_value = osi->sec->output_section->vma
18039 + osi->sec->output_offset
18040 + offset;
4e617b1e
PB		 18041 sym.st_size = 0;
18042 sym.st_other = 0;
18043 sym.st_info = ELF_ST_INFO (STB_LOCAL, STT_NOTYPE);
91a5743d 18044 sym.st_shndx = osi->sec_shndx;
35fc36a8 18045 sym.st_target_internal = 0;
fe33d2fa 18046 elf32_arm_section_map_add (osi->sec, names[type][1], offset);
57402f1e 18047 return osi->func (osi->flaginfo, names[type], &sym, osi->sec, NULL) == 1;
4e617b1e
PB		 18048}
18049
34e77a92
RS		 18050/* Output mapping symbols for the PLT entry described by ROOT_PLT and ARM_PLT.
18051 IS_IPLT_ENTRY_P says whether the PLT is in .iplt rather than .plt. */
4e617b1e
PB		 18052
18053static bfd_boolean
34e77a92
RS		 18054elf32_arm_output_plt_map_1 (output_arch_syminfo *osi,
18055 bfd_boolean is_iplt_entry_p,
18056 union gotplt_union *root_plt,
18057 struct arm_plt_info *arm_plt)
4e617b1e 18058{
4e617b1e 18059 struct elf32_arm_link_hash_table *htab;
34e77a92 18060 bfd_vma addr, plt_header_size;
4e617b1e 18061
34e77a92 18062 if (root_plt->offset == (bfd_vma) -1)
4e617b1e
PB		 18063 return TRUE;
18064
4dfe6ac6
NC		 18065 htab = elf32_arm_hash_table (osi->info);
18066 if (htab == NULL)
18067 return FALSE;
18068
34e77a92
RS		 18069 if (is_iplt_entry_p)
18070 {
18071 osi->sec = htab->root.iplt;
18072 plt_header_size = 0;
18073 }
18074 else
18075 {
18076 osi->sec = htab->root.splt;
18077 plt_header_size = htab->plt_header_size;
18078 }
18079 osi->sec_shndx = (_bfd_elf_section_from_bfd_section
18080 (osi->info->output_bfd, osi->sec->output_section));
18081
18082 addr = root_plt->offset & -2;
4e617b1e
PB		 18083 if (htab->symbian_p)
18084 {
7413f23f 18085 if (!elf32_arm_output_map_sym (osi, ARM_MAP_ARM, addr))
4e617b1e 18086 return FALSE;
7413f23f 18087 if (!elf32_arm_output_map_sym (osi, ARM_MAP_DATA, addr + 4))
4e617b1e
PB		 18088 return FALSE;
18089 }
18090 else if (htab->vxworks_p)
18091 {
7413f23f 18092 if (!elf32_arm_output_map_sym (osi, ARM_MAP_ARM, addr))
4e617b1e 18093 return FALSE;
7413f23f 18094 if (!elf32_arm_output_map_sym (osi, ARM_MAP_DATA, addr + 8))
4e617b1e 18095 return FALSE;
7413f23f 18096 if (!elf32_arm_output_map_sym (osi, ARM_MAP_ARM, addr + 12))
4e617b1e 18097 return FALSE;
7413f23f 18098 if (!elf32_arm_output_map_sym (osi, ARM_MAP_DATA, addr + 20))
4e617b1e
PB		 18099 return FALSE;
18100 }
b38cadfb
NC		 18101 else if (htab->nacl_p)
18102 {
18103 if (!elf32_arm_output_map_sym (osi, ARM_MAP_ARM, addr))
18104 return FALSE;
18105 }
7801f98f
CL		 18106 else if (htab->fdpic_p)
18107 {
59029f57
CL		 18108 enum map_symbol_type type = using_thumb_only(htab)
18109 ? ARM_MAP_THUMB
18110 : ARM_MAP_ARM;
18111
7801f98f 18112 if (elf32_arm_plt_needs_thumb_stub_p (osi->info, arm_plt))
4b24dd1a
AM		 18113 if (!elf32_arm_output_map_sym (osi, ARM_MAP_THUMB, addr - 4))
18114 return FALSE;
59029f57 18115 if (!elf32_arm_output_map_sym (osi, type, addr))
4b24dd1a 18116 return FALSE;
7801f98f 18117 if (!elf32_arm_output_map_sym (osi, ARM_MAP_DATA, addr + 16))
4b24dd1a 18118 return FALSE;
7801f98f 18119 if (htab->plt_entry_size == 4 * ARRAY_SIZE(elf32_arm_fdpic_plt_entry))
4b24dd1a
AM		 18120 if (!elf32_arm_output_map_sym (osi, type, addr + 24))
18121 return FALSE;
7801f98f 18122 }
eed94f8f
NC		 18123 else if (using_thumb_only (htab))
18124 {
18125 if (!elf32_arm_output_map_sym (osi, ARM_MAP_THUMB, addr))
18126 return FALSE;
6a631e86 18127 }
4e617b1e
PB		 18128 else
18129 {
34e77a92 18130 bfd_boolean thumb_stub_p;
bd97cb95 18131
34e77a92
RS		 18132 thumb_stub_p = elf32_arm_plt_needs_thumb_stub_p (osi->info, arm_plt);
18133 if (thumb_stub_p)
4e617b1e 18134 {
7413f23f 18135 if (!elf32_arm_output_map_sym (osi, ARM_MAP_THUMB, addr - 4))
4e617b1e
PB		 18136 return FALSE;
18137 }
18138#ifdef FOUR_WORD_PLT
7413f23f 18139 if (!elf32_arm_output_map_sym (osi, ARM_MAP_ARM, addr))
4e617b1e 18140 return FALSE;
7413f23f 18141 if (!elf32_arm_output_map_sym (osi, ARM_MAP_DATA, addr + 12))
4e617b1e
PB		 18142 return FALSE;
18143#else
906e58ca 18144 /* A three-word PLT with no Thumb thunk contains only Arm code,
4e617b1e
PB		 18145 so only need to output a mapping symbol for the first PLT entry and
18146 entries with thumb thunks. */
34e77a92 18147 if (thumb_stub_p || addr == plt_header_size)
4e617b1e 18148 {
7413f23f 18149 if (!elf32_arm_output_map_sym (osi, ARM_MAP_ARM, addr))
4e617b1e
PB		 18150 return FALSE;
18151 }
18152#endif
18153 }
18154
18155 return TRUE;
18156}
18157
34e77a92
RS		 18158/* Output mapping symbols for PLT entries associated with H. */
18159
18160static bfd_boolean
18161elf32_arm_output_plt_map (struct elf_link_hash_entry *h, void *inf)
18162{
18163 output_arch_syminfo *osi = (output_arch_syminfo *) inf;
18164 struct elf32_arm_link_hash_entry *eh;
18165
18166 if (h->root.type == bfd_link_hash_indirect)
18167 return TRUE;
18168
18169 if (h->root.type == bfd_link_hash_warning)
18170 /* When warning symbols are created, they **replace** the "real"
18171 entry in the hash table, thus we never get to see the real
18172 symbol in a hash traversal. So look at it now. */
18173 h = (struct elf_link_hash_entry *) h->root.u.i.link;
18174
18175 eh = (struct elf32_arm_link_hash_entry *) h;
18176 return elf32_arm_output_plt_map_1 (osi, SYMBOL_CALLS_LOCAL (osi->info, h),
18177 &h->plt, &eh->plt);
18178}
18179
4f4faa4d
TP		 18180/* Bind a veneered symbol to its veneer identified by its hash entry
18181 STUB_ENTRY. The veneered location thus loose its symbol. */
18182
18183static void
18184arm_stub_claim_sym (struct elf32_arm_stub_hash_entry *stub_entry)
18185{
18186 struct elf32_arm_link_hash_entry *hash = stub_entry->h;
18187
18188 BFD_ASSERT (hash);
18189 hash->root.root.u.def.section = stub_entry->stub_sec;
18190 hash->root.root.u.def.value = stub_entry->stub_offset;
18191 hash->root.size = stub_entry->stub_size;
18192}
18193
7413f23f
DJ		 18194/* Output a single local symbol for a generated stub. */
18195
18196static bfd_boolean
18197elf32_arm_output_stub_sym (output_arch_syminfo *osi, const char *name,
18198 bfd_vma offset, bfd_vma size)
18199{
7413f23f
DJ		 18200 Elf_Internal_Sym sym;
18201
7413f23f
DJ		 18202 sym.st_value = osi->sec->output_section->vma
18203 + osi->sec->output_offset
18204 + offset;
18205 sym.st_size = size;
18206 sym.st_other = 0;
18207 sym.st_info = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
18208 sym.st_shndx = osi->sec_shndx;
35fc36a8 18209 sym.st_target_internal = 0;
57402f1e 18210 return osi->func (osi->flaginfo, name, &sym, osi->sec, NULL) == 1;
7413f23f 18211}
4e617b1e 18212
da5938a2 18213static bfd_boolean
8029a119
NC		 18214arm_map_one_stub (struct bfd_hash_entry * gen_entry,
18215 void * in_arg)
da5938a2
NC		 18216{
18217 struct elf32_arm_stub_hash_entry *stub_entry;
da5938a2
NC		 18218 asection *stub_sec;
18219 bfd_vma addr;
7413f23f 18220 char *stub_name;
9a008db3 18221 output_arch_syminfo *osi;
d3ce72d0 18222 const insn_sequence *template_sequence;
461a49ca
DJ		 18223 enum stub_insn_type prev_type;
18224 int size;
18225 int i;
18226 enum map_symbol_type sym_type;
da5938a2
NC		 18227
18228 /* Massage our args to the form they really have. */
18229 stub_entry = (struct elf32_arm_stub_hash_entry *) gen_entry;
9a008db3 18230 osi = (output_arch_syminfo *) in_arg;
da5938a2 18231
da5938a2
NC		 18232 stub_sec = stub_entry->stub_sec;
18233
18234 /* Ensure this stub is attached to the current section being
7413f23f 18235 processed. */
da5938a2
NC		 18236 if (stub_sec != osi->sec)
18237 return TRUE;
18238
7413f23f 18239 addr = (bfd_vma) stub_entry->stub_offset;
d3ce72d0 18240 template_sequence = stub_entry->stub_template;
4f4faa4d
TP		 18241
18242 if (arm_stub_sym_claimed (stub_entry->stub_type))
18243 arm_stub_claim_sym (stub_entry);
18244 else
7413f23f 18245 {
4f4faa4d
TP		 18246 stub_name = stub_entry->output_name;
18247 switch (template_sequence[0].type)
18248 {
18249 case ARM_TYPE:
18250 if (!elf32_arm_output_stub_sym (osi, stub_name, addr,
18251 stub_entry->stub_size))
18252 return FALSE;
18253 break;
18254 case THUMB16_TYPE:
18255 case THUMB32_TYPE:
18256 if (!elf32_arm_output_stub_sym (osi, stub_name, addr | 1,
18257 stub_entry->stub_size))
18258 return FALSE;
18259 break;
18260 default:
18261 BFD_FAIL ();
18262 return 0;
18263 }
7413f23f 18264 }
da5938a2 18265
461a49ca
DJ		 18266 prev_type = DATA_TYPE;
18267 size = 0;
18268 for (i = 0; i < stub_entry->stub_template_size; i++)
18269 {
d3ce72d0 18270 switch (template_sequence[i].type)
461a49ca
DJ		 18271 {
18272 case ARM_TYPE:
18273 sym_type = ARM_MAP_ARM;
18274 break;
18275
18276 case THUMB16_TYPE:
48229727 18277 case THUMB32_TYPE:
461a49ca
DJ		 18278 sym_type = ARM_MAP_THUMB;
18279 break;
18280
18281 case DATA_TYPE:
18282 sym_type = ARM_MAP_DATA;
18283 break;
18284
18285 default:
18286 BFD_FAIL ();
4e31c731 18287 return FALSE;
461a49ca
DJ		 18288 }
18289
d3ce72d0 18290 if (template_sequence[i].type != prev_type)
461a49ca 18291 {
d3ce72d0 18292 prev_type = template_sequence[i].type;
461a49ca
DJ		 18293 if (!elf32_arm_output_map_sym (osi, sym_type, addr + size))
18294 return FALSE;
18295 }
18296
d3ce72d0 18297 switch (template_sequence[i].type)
461a49ca
DJ		 18298 {
18299 case ARM_TYPE:
48229727 18300 case THUMB32_TYPE:
461a49ca
DJ		 18301 size += 4;
18302 break;
18303
18304 case THUMB16_TYPE:
18305 size += 2;
18306 break;
18307
18308 case DATA_TYPE:
18309 size += 4;
18310 break;
18311
18312 default:
18313 BFD_FAIL ();
4e31c731 18314 return FALSE;
461a49ca
DJ		 18315 }
18316 }
18317
da5938a2
NC		 18318 return TRUE;
18319}
18320
33811162
DG		 18321/* Output mapping symbols for linker generated sections,
18322 and for those data-only sections that do not have a
18323 $d. */
4e617b1e
PB		 18324
18325static bfd_boolean
18326elf32_arm_output_arch_local_syms (bfd *output_bfd,
906e58ca 18327 struct bfd_link_info *info,
57402f1e 18328 void *flaginfo,
6e0b88f1
AM		 18329 int (*func) (void *, const char *,
18330 Elf_Internal_Sym *,
18331 asection *,
18332 struct elf_link_hash_entry *))
4e617b1e
PB		 18333{
18334 output_arch_syminfo osi;
18335 struct elf32_arm_link_hash_table *htab;
91a5743d
PB		 18336 bfd_vma offset;
18337 bfd_size_type size;
33811162 18338 bfd *input_bfd;
4e617b1e
PB		 18339
18340 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 18341 if (htab == NULL)
18342 return FALSE;
18343
906e58ca 18344 check_use_blx (htab);
91a5743d 18345
57402f1e 18346 osi.flaginfo = flaginfo;
4e617b1e
PB		 18347 osi.info = info;
18348 osi.func = func;
906e58ca 18349
33811162
DG		 18350 /* Add a $d mapping symbol to data-only sections that
18351 don't have any mapping symbol. This may result in (harmless) redundant
18352 mapping symbols. */
18353 for (input_bfd = info->input_bfds;
18354 input_bfd != NULL;
c72f2fb2 18355 input_bfd = input_bfd->link.next)
33811162
DG		 18356 {
18357 if ((input_bfd->flags & (BFD_LINKER_CREATED | HAS_SYMS)) == HAS_SYMS)
18358 for (osi.sec = input_bfd->sections;
18359 osi.sec != NULL;
18360 osi.sec = osi.sec->next)
18361 {
18362 if (osi.sec->output_section != NULL
f7dd8c79
DJ		 18363 && ((osi.sec->output_section->flags & (SEC_ALLOC | SEC_CODE))
18364 != 0)
33811162
DG		 18365 && (osi.sec->flags & (SEC_HAS_CONTENTS | SEC_LINKER_CREATED))
18366 == SEC_HAS_CONTENTS
18367 && get_arm_elf_section_data (osi.sec) != NULL
501abfe0 18368 && get_arm_elf_section_data (osi.sec)->mapcount == 0
7d500b83
CL		 18369 && osi.sec->size > 0
18370 && (osi.sec->flags & SEC_EXCLUDE) == 0)
33811162
DG		 18371 {
18372 osi.sec_shndx = _bfd_elf_section_from_bfd_section
18373 (output_bfd, osi.sec->output_section);
18374 if (osi.sec_shndx != (int)SHN_BAD)
18375 elf32_arm_output_map_sym (&osi, ARM_MAP_DATA, 0);
18376 }
18377 }
18378 }
18379
91a5743d
PB		 18380 /* ARM->Thumb glue. */
18381 if (htab->arm_glue_size > 0)
18382 {
3d4d4302
AM		 18383 osi.sec = bfd_get_linker_section (htab->bfd_of_glue_owner,
18384 ARM2THUMB_GLUE_SECTION_NAME);
91a5743d
PB		 18385
18386 osi.sec_shndx = _bfd_elf_section_from_bfd_section
18387 (output_bfd, osi.sec->output_section);
0e1862bb 18388 if (bfd_link_pic (info) || htab->root.is_relocatable_executable
91a5743d
PB		 18389 || htab->pic_veneer)
18390 size = ARM2THUMB_PIC_GLUE_SIZE;
18391 else if (htab->use_blx)
18392 size = ARM2THUMB_V5_STATIC_GLUE_SIZE;
18393 else
18394 size = ARM2THUMB_STATIC_GLUE_SIZE;
4e617b1e 18395
91a5743d
PB		 18396 for (offset = 0; offset < htab->arm_glue_size; offset += size)
18397 {
7413f23f
DJ		 18398 elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, offset);
18399 elf32_arm_output_map_sym (&osi, ARM_MAP_DATA, offset + size - 4);
91a5743d
PB		 18400 }
18401 }
18402
18403 /* Thumb->ARM glue. */
18404 if (htab->thumb_glue_size > 0)
18405 {
3d4d4302
AM		 18406 osi.sec = bfd_get_linker_section (htab->bfd_of_glue_owner,
18407 THUMB2ARM_GLUE_SECTION_NAME);
91a5743d
PB		 18408
18409 osi.sec_shndx = _bfd_elf_section_from_bfd_section
18410 (output_bfd, osi.sec->output_section);
18411 size = THUMB2ARM_GLUE_SIZE;
18412
18413 for (offset = 0; offset < htab->thumb_glue_size; offset += size)
18414 {
7413f23f
DJ		 18415 elf32_arm_output_map_sym (&osi, ARM_MAP_THUMB, offset);
18416 elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, offset + 4);
91a5743d
PB		 18417 }
18418 }
18419
845b51d6
PB		 18420 /* ARMv4 BX veneers. */
18421 if (htab->bx_glue_size > 0)
18422 {
3d4d4302
AM		 18423 osi.sec = bfd_get_linker_section (htab->bfd_of_glue_owner,
18424 ARM_BX_GLUE_SECTION_NAME);
845b51d6
PB		 18425
18426 osi.sec_shndx = _bfd_elf_section_from_bfd_section
18427 (output_bfd, osi.sec->output_section);
18428
7413f23f 18429 elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, 0);
845b51d6
PB		 18430 }
18431
8029a119
NC		 18432 /* Long calls stubs. */
18433 if (htab->stub_bfd && htab->stub_bfd->sections)
18434 {
da5938a2 18435 asection* stub_sec;
8029a119 18436
da5938a2
NC		 18437 for (stub_sec = htab->stub_bfd->sections;
18438 stub_sec != NULL;
8029a119
NC		 18439 stub_sec = stub_sec->next)
18440 {
18441 /* Ignore non-stub sections. */
18442 if (!strstr (stub_sec->name, STUB_SUFFIX))
18443 continue;
da5938a2 18444
8029a119 18445 osi.sec = stub_sec;
da5938a2 18446
8029a119
NC		 18447 osi.sec_shndx = _bfd_elf_section_from_bfd_section
18448 (output_bfd, osi.sec->output_section);
da5938a2 18449
8029a119
NC		 18450 bfd_hash_traverse (&htab->stub_hash_table, arm_map_one_stub, &osi);
18451 }
18452 }
da5938a2 18453
91a5743d 18454 /* Finally, output mapping symbols for the PLT. */
34e77a92 18455 if (htab->root.splt && htab->root.splt->size > 0)
4e617b1e 18456 {
34e77a92
RS		 18457 osi.sec = htab->root.splt;
18458 osi.sec_shndx = (_bfd_elf_section_from_bfd_section
18459 (output_bfd, osi.sec->output_section));
18460
18461 /* Output mapping symbols for the plt header. SymbianOS does not have a
18462 plt header. */
18463 if (htab->vxworks_p)
18464 {
18465 /* VxWorks shared libraries have no PLT header. */
0e1862bb 18466 if (!bfd_link_pic (info))
34e77a92
RS		 18467 {
18468 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, 0))
18469 return FALSE;
18470 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_DATA, 12))
18471 return FALSE;
18472 }
18473 }
b38cadfb
NC		 18474 else if (htab->nacl_p)
18475 {
18476 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, 0))
18477 return FALSE;
18478 }
59029f57 18479 else if (using_thumb_only (htab) && !htab->fdpic_p)
eed94f8f
NC		 18480 {
18481 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_THUMB, 0))
18482 return FALSE;
18483 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_DATA, 12))
18484 return FALSE;
18485 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_THUMB, 16))
18486 return FALSE;
18487 }
e8b09b87 18488 else if (!htab->symbian_p && !htab->fdpic_p)
4e617b1e 18489 {
7413f23f 18490 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, 0))
4e617b1e 18491 return FALSE;
34e77a92
RS		 18492#ifndef FOUR_WORD_PLT
18493 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_DATA, 16))
4e617b1e 18494 return FALSE;
34e77a92 18495#endif
4e617b1e
PB		 18496 }
18497 }
99059e56
RM		 18498 if (htab->nacl_p && htab->root.iplt && htab->root.iplt->size > 0)
18499 {
18500 /* NaCl uses a special first entry in .iplt too. */
18501 osi.sec = htab->root.iplt;
18502 osi.sec_shndx = (_bfd_elf_section_from_bfd_section
18503 (output_bfd, osi.sec->output_section));
18504 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, 0))
18505 return FALSE;
18506 }
34e77a92
RS		 18507 if ((htab->root.splt && htab->root.splt->size > 0)
18508 || (htab->root.iplt && htab->root.iplt->size > 0))
4e617b1e 18509 {
34e77a92
RS		 18510 elf_link_hash_traverse (&htab->root, elf32_arm_output_plt_map, &osi);
18511 for (input_bfd = info->input_bfds;
18512 input_bfd != NULL;
c72f2fb2 18513 input_bfd = input_bfd->link.next)
34e77a92
RS		 18514 {
18515 struct arm_local_iplt_info **local_iplt;
18516 unsigned int i, num_syms;
4e617b1e 18517
34e77a92
RS		 18518 local_iplt = elf32_arm_local_iplt (input_bfd);
18519 if (local_iplt != NULL)
18520 {
18521 num_syms = elf_symtab_hdr (input_bfd).sh_info;
18522 for (i = 0; i < num_syms; i++)
18523 if (local_iplt[i] != NULL
18524 && !elf32_arm_output_plt_map_1 (&osi, TRUE,
18525 &local_iplt[i]->root,
18526 &local_iplt[i]->arm))
18527 return FALSE;
18528 }
18529 }
18530 }
0855e32b
NS		 18531 if (htab->dt_tlsdesc_plt != 0)
18532 {
18533 /* Mapping symbols for the lazy tls trampoline. */
18534 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, htab->dt_tlsdesc_plt))
18535 return FALSE;
b38cadfb 18536
0855e32b
NS		 18537 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_DATA,
18538 htab->dt_tlsdesc_plt + 24))
18539 return FALSE;
18540 }
18541 if (htab->tls_trampoline != 0)
18542 {
18543 /* Mapping symbols for the tls trampoline. */
18544 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, htab->tls_trampoline))
18545 return FALSE;
18546#ifdef FOUR_WORD_PLT
18547 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_DATA,
18548 htab->tls_trampoline + 12))
18549 return FALSE;
b38cadfb 18550#endif
0855e32b 18551 }
b38cadfb 18552
4e617b1e
PB		 18553 return TRUE;
18554}
18555
54ddd295
TP		 18556/* Filter normal symbols of CMSE entry functions of ABFD to include in
18557 the import library. All SYMCOUNT symbols of ABFD can be examined
18558 from their pointers in SYMS. Pointers of symbols to keep should be
18559 stored continuously at the beginning of that array.
18560
18561 Returns the number of symbols to keep. */
18562
18563static unsigned int
18564elf32_arm_filter_cmse_symbols (bfd *abfd ATTRIBUTE_UNUSED,
18565 struct bfd_link_info *info,
18566 asymbol **syms, long symcount)
18567{
18568 size_t maxnamelen;
18569 char *cmse_name;
18570 long src_count, dst_count = 0;
18571 struct elf32_arm_link_hash_table *htab;
18572
18573 htab = elf32_arm_hash_table (info);
18574 if (!htab->stub_bfd || !htab->stub_bfd->sections)
18575 symcount = 0;
18576
18577 maxnamelen = 128;
18578 cmse_name = (char *) bfd_malloc (maxnamelen);
18579 for (src_count = 0; src_count < symcount; src_count++)
18580 {
18581 struct elf32_arm_link_hash_entry *cmse_hash;
18582 asymbol *sym;
18583 flagword flags;
18584 char *name;
18585 size_t namelen;
18586
18587 sym = syms[src_count];
18588 flags = sym->flags;
18589 name = (char *) bfd_asymbol_name (sym);
18590
18591 if ((flags & BSF_FUNCTION) != BSF_FUNCTION)
18592 continue;
18593 if (!(flags & (BSF_GLOBAL | BSF_WEAK)))
18594 continue;
18595
18596 namelen = strlen (name) + sizeof (CMSE_PREFIX) + 1;
18597 if (namelen > maxnamelen)
18598 {
18599 cmse_name = (char *)
18600 bfd_realloc (cmse_name, namelen);
18601 maxnamelen = namelen;
18602 }
18603 snprintf (cmse_name, maxnamelen, "%s%s", CMSE_PREFIX, name);
18604 cmse_hash = (struct elf32_arm_link_hash_entry *)
18605 elf_link_hash_lookup (&(htab)->root, cmse_name, FALSE, FALSE, TRUE);
18606
18607 if (!cmse_hash
18608 || (cmse_hash->root.root.type != bfd_link_hash_defined
18609 && cmse_hash->root.root.type != bfd_link_hash_defweak)
18610 || cmse_hash->root.type != STT_FUNC)
18611 continue;
18612
18613 if (!ARM_GET_SYM_CMSE_SPCL (cmse_hash->root.target_internal))
18614 continue;
18615
18616 syms[dst_count++] = sym;
18617 }
18618 free (cmse_name);
18619
18620 syms[dst_count] = NULL;
18621
18622 return dst_count;
18623}
18624
18625/* Filter symbols of ABFD to include in the import library. All
18626 SYMCOUNT symbols of ABFD can be examined from their pointers in
18627 SYMS. Pointers of symbols to keep should be stored continuously at
18628 the beginning of that array.
18629
18630 Returns the number of symbols to keep. */
18631
18632static unsigned int
18633elf32_arm_filter_implib_symbols (bfd *abfd ATTRIBUTE_UNUSED,
18634 struct bfd_link_info *info,
18635 asymbol **syms, long symcount)
18636{
18637 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (info);
18638
046734ff
TP		 18639 /* Requirement 8 of "ARM v8-M Security Extensions: Requirements on
18640 Development Tools" (ARM-ECM-0359818) mandates Secure Gateway import
18641 library to be a relocatable object file. */
18642 BFD_ASSERT (!(bfd_get_file_flags (info->out_implib_bfd) & EXEC_P));
54ddd295
TP		 18643 if (globals->cmse_implib)
18644 return elf32_arm_filter_cmse_symbols (abfd, info, syms, symcount);
18645 else
18646 return _bfd_elf_filter_global_symbols (abfd, info, syms, symcount);
18647}
18648
e489d0ae
PB		 18649/* Allocate target specific section data. */
18650
18651static bfd_boolean
18652elf32_arm_new_section_hook (bfd *abfd, asection *sec)
18653{
f592407e
AM		 18654 if (!sec->used_by_bfd)
18655 {
18656 _arm_elf_section_data *sdata;
18657 bfd_size_type amt = sizeof (*sdata);
e489d0ae 18658
21d799b5 18659 sdata = (_arm_elf_section_data *) bfd_zalloc (abfd, amt);
f592407e
AM		 18660 if (sdata == NULL)
18661 return FALSE;
18662 sec->used_by_bfd = sdata;
18663 }
e489d0ae
PB		 18664
18665 return _bfd_elf_new_section_hook (abfd, sec);
18666}
18667
18668
18669/* Used to order a list of mapping symbols by address. */
18670
18671static int
18672elf32_arm_compare_mapping (const void * a, const void * b)
18673{
7f6a71ff
JM		 18674 const elf32_arm_section_map *amap = (const elf32_arm_section_map *) a;
18675 const elf32_arm_section_map *bmap = (const elf32_arm_section_map *) b;
18676
18677 if (amap->vma > bmap->vma)
18678 return 1;
18679 else if (amap->vma < bmap->vma)
18680 return -1;
18681 else if (amap->type > bmap->type)
18682 /* Ensure results do not depend on the host qsort for objects with
18683 multiple mapping symbols at the same address by sorting on type
18684 after vma. */
18685 return 1;
18686 else if (amap->type < bmap->type)
18687 return -1;
18688 else
18689 return 0;
e489d0ae
PB		 18690}
18691
2468f9c9
PB		 18692/* Add OFFSET to lower 31 bits of ADDR, leaving other bits unmodified. */
18693
18694static unsigned long
18695offset_prel31 (unsigned long addr, bfd_vma offset)
18696{
18697 return (addr & ~0x7ffffffful) | ((addr + offset) & 0x7ffffffful);
18698}
18699
18700/* Copy an .ARM.exidx table entry, adding OFFSET to (applied) PREL31
18701 relocations. */
18702
18703static void
18704copy_exidx_entry (bfd *output_bfd, bfd_byte *to, bfd_byte *from, bfd_vma offset)
18705{
18706 unsigned long first_word = bfd_get_32 (output_bfd, from);
18707 unsigned long second_word = bfd_get_32 (output_bfd, from + 4);
b38cadfb 18708
2468f9c9
PB		 18709 /* High bit of first word is supposed to be zero. */
18710 if ((first_word & 0x80000000ul) == 0)
18711 first_word = offset_prel31 (first_word, offset);
b38cadfb 18712
2468f9c9
PB		 18713 /* If the high bit of the first word is clear, and the bit pattern is not 0x1
18714 (EXIDX_CANTUNWIND), this is an offset to an .ARM.extab entry. */
18715 if ((second_word != 0x1) && ((second_word & 0x80000000ul) == 0))
18716 second_word = offset_prel31 (second_word, offset);
b38cadfb 18717
2468f9c9
PB		 18718 bfd_put_32 (output_bfd, first_word, to);
18719 bfd_put_32 (output_bfd, second_word, to + 4);
18720}
e489d0ae 18721
48229727
JB		 18722/* Data for make_branch_to_a8_stub(). */
18723
b38cadfb
NC		 18724struct a8_branch_to_stub_data
18725{
48229727
JB		 18726 asection *writing_section;
18727 bfd_byte *contents;
18728};
18729
18730
18731/* Helper to insert branches to Cortex-A8 erratum stubs in the right
18732 places for a particular section. */
18733
18734static bfd_boolean
18735make_branch_to_a8_stub (struct bfd_hash_entry *gen_entry,
99059e56 18736 void *in_arg)
48229727
JB		 18737{
18738 struct elf32_arm_stub_hash_entry *stub_entry;
18739 struct a8_branch_to_stub_data *data;
18740 bfd_byte *contents;
18741 unsigned long branch_insn;
18742 bfd_vma veneered_insn_loc, veneer_entry_loc;
18743 bfd_signed_vma branch_offset;
18744 bfd *abfd;
8d9d9490 18745 unsigned int loc;
48229727
JB		 18746
18747 stub_entry = (struct elf32_arm_stub_hash_entry *) gen_entry;
18748 data = (struct a8_branch_to_stub_data *) in_arg;
18749
18750 if (stub_entry->target_section != data->writing_section
4563a860 18751 || stub_entry->stub_type < arm_stub_a8_veneer_lwm)
48229727
JB		 18752 return TRUE;
18753
18754 contents = data->contents;
18755
8d9d9490
TP		 18756 /* We use target_section as Cortex-A8 erratum workaround stubs are only
18757 generated when both source and target are in the same section. */
48229727
JB		 18758 veneered_insn_loc = stub_entry->target_section->output_section->vma
18759 + stub_entry->target_section->output_offset
8d9d9490 18760 + stub_entry->source_value;
48229727
JB		 18761
18762 veneer_entry_loc = stub_entry->stub_sec->output_section->vma
18763 + stub_entry->stub_sec->output_offset
18764 + stub_entry->stub_offset;
18765
18766 if (stub_entry->stub_type == arm_stub_a8_veneer_blx)
18767 veneered_insn_loc &= ~3u;
18768
18769 branch_offset = veneer_entry_loc - veneered_insn_loc - 4;
18770
18771 abfd = stub_entry->target_section->owner;
8d9d9490 18772 loc = stub_entry->source_value;
48229727
JB		 18773
18774 /* We attempt to avoid this condition by setting stubs_always_after_branch
18775 in elf32_arm_size_stubs if we've enabled the Cortex-A8 erratum workaround.
18776 This check is just to be on the safe side... */
18777 if ((veneered_insn_loc & ~0xfff) == (veneer_entry_loc & ~0xfff))
18778 {
871b3ab2 18779 _bfd_error_handler (_("%pB: error: Cortex-A8 erratum stub is "
4eca0228 18780 "allocated in unsafe location"), abfd);
48229727
JB		 18781 return FALSE;
18782 }
18783
18784 switch (stub_entry->stub_type)
18785 {
18786 case arm_stub_a8_veneer_b:
18787 case arm_stub_a8_veneer_b_cond:
18788 branch_insn = 0xf0009000;
18789 goto jump24;
18790
18791 case arm_stub_a8_veneer_blx:
18792 branch_insn = 0xf000e800;
18793 goto jump24;
18794
18795 case arm_stub_a8_veneer_bl:
18796 {
18797 unsigned int i1, j1, i2, j2, s;
18798
18799 branch_insn = 0xf000d000;
18800
18801 jump24:
18802 if (branch_offset < -16777216 || branch_offset > 16777214)
18803 {
18804 /* There's not much we can do apart from complain if this
18805 happens. */
871b3ab2 18806 _bfd_error_handler (_("%pB: error: Cortex-A8 erratum stub out "
4eca0228 18807 "of range (input file too large)"), abfd);
48229727
JB		 18808 return FALSE;
18809 }
18810
18811 /* i1 = not(j1 eor s), so:
18812 not i1 = j1 eor s
18813 j1 = (not i1) eor s. */
18814
18815 branch_insn |= (branch_offset >> 1) & 0x7ff;
18816 branch_insn |= ((branch_offset >> 12) & 0x3ff) << 16;
18817 i2 = (branch_offset >> 22) & 1;
18818 i1 = (branch_offset >> 23) & 1;
18819 s = (branch_offset >> 24) & 1;
18820 j1 = (!i1) ^ s;
18821 j2 = (!i2) ^ s;
18822 branch_insn |= j2 << 11;
18823 branch_insn |= j1 << 13;
18824 branch_insn |= s << 26;
18825 }
18826 break;
18827
18828 default:
18829 BFD_FAIL ();
18830 return FALSE;
18831 }
18832
8d9d9490
TP		 18833 bfd_put_16 (abfd, (branch_insn >> 16) & 0xffff, &contents[loc]);
18834 bfd_put_16 (abfd, branch_insn & 0xffff, &contents[loc + 2]);
48229727
JB		 18835
18836 return TRUE;
18837}
18838
a504d23a
LA		 18839/* Beginning of stm32l4xx work-around. */
18840
18841/* Functions encoding instructions necessary for the emission of the
18842 fix-stm32l4xx-629360.
18843 Encoding is extracted from the
18844 ARM (C) Architecture Reference Manual
18845 ARMv7-A and ARMv7-R edition
18846 ARM DDI 0406C.b (ID072512). */
18847
18848static inline bfd_vma
82188b29 18849create_instruction_branch_absolute (int branch_offset)
a504d23a
LA		 18850{
18851 /* A8.8.18 B (A8-334)
18852 B target_address (Encoding T4). */
18853 /* 1111 - 0Sii - iiii - iiii - 10J1 - Jiii - iiii - iiii. */
18854 /* jump offset is: S:I1:I2:imm10:imm11:0. */
18855 /* with : I1 = NOT (J1 EOR S) I2 = NOT (J2 EOR S). */
18856
a504d23a
LA		 18857 int s = ((branch_offset & 0x1000000) >> 24);
18858 int j1 = s ^ !((branch_offset & 0x800000) >> 23);
18859 int j2 = s ^ !((branch_offset & 0x400000) >> 22);
18860
18861 if (branch_offset < -(1 << 24) || branch_offset >= (1 << 24))
18862 BFD_ASSERT (0 && "Error: branch out of range. Cannot create branch.");
18863
18864 bfd_vma patched_inst = 0xf0009000
18865 | s << 26 /* S. */
18866 | (((unsigned long) (branch_offset) >> 12) & 0x3ff) << 16 /* imm10. */
18867 | j1 << 13 /* J1. */
18868 | j2 << 11 /* J2. */
18869 | (((unsigned long) (branch_offset) >> 1) & 0x7ff); /* imm11. */
18870
18871 return patched_inst;
18872}
18873
18874static inline bfd_vma
18875create_instruction_ldmia (int base_reg, int wback, int reg_mask)
18876{
18877 /* A8.8.57 LDM/LDMIA/LDMFD (A8-396)
18878 LDMIA Rn!, {Ra, Rb, Rc, ...} (Encoding T2). */
18879 bfd_vma patched_inst = 0xe8900000
18880 | (/*W=*/wback << 21)
18881 | (base_reg << 16)
18882 | (reg_mask & 0x0000ffff);
18883
18884 return patched_inst;
18885}
18886
18887static inline bfd_vma
18888create_instruction_ldmdb (int base_reg, int wback, int reg_mask)
18889{
18890 /* A8.8.60 LDMDB/LDMEA (A8-402)
18891 LDMDB Rn!, {Ra, Rb, Rc, ...} (Encoding T1). */
18892 bfd_vma patched_inst = 0xe9100000
18893 | (/*W=*/wback << 21)
18894 | (base_reg << 16)
18895 | (reg_mask & 0x0000ffff);
18896
18897 return patched_inst;
18898}
18899
18900static inline bfd_vma
18901create_instruction_mov (int target_reg, int source_reg)
18902{
18903 /* A8.8.103 MOV (register) (A8-486)
18904 MOV Rd, Rm (Encoding T1). */
18905 bfd_vma patched_inst = 0x4600
18906 | (target_reg & 0x7)
18907 | ((target_reg & 0x8) >> 3) << 7
18908 | (source_reg << 3);
18909
18910 return patched_inst;
18911}
18912
18913static inline bfd_vma
18914create_instruction_sub (int target_reg, int source_reg, int value)
18915{
18916 /* A8.8.221 SUB (immediate) (A8-708)
18917 SUB Rd, Rn, #value (Encoding T3). */
18918 bfd_vma patched_inst = 0xf1a00000
18919 | (target_reg << 8)
18920 | (source_reg << 16)
18921 | (/*S=*/0 << 20)
18922 | ((value & 0x800) >> 11) << 26
18923 | ((value & 0x700) >> 8) << 12
18924 | (value & 0x0ff);
18925
18926 return patched_inst;
18927}
18928
18929static inline bfd_vma
9239bbd3 18930create_instruction_vldmia (int base_reg, int is_dp, int wback, int num_words,
a504d23a
LA		 18931 int first_reg)
18932{
18933 /* A8.8.332 VLDM (A8-922)
9239bbd3
CM		 18934 VLMD{MODE} Rn{!}, {list} (Encoding T1 or T2). */
18935 bfd_vma patched_inst = (is_dp ? 0xec900b00 : 0xec900a00)
a504d23a
LA		 18936 | (/*W=*/wback << 21)
18937 | (base_reg << 16)
9239bbd3
CM		 18938 | (num_words & 0x000000ff)
18939 | (((unsigned)first_reg >> 1) & 0x0000000f) << 12
a504d23a
LA		 18940 | (first_reg & 0x00000001) << 22;
18941
18942 return patched_inst;
18943}
18944
18945static inline bfd_vma
9239bbd3
CM		 18946create_instruction_vldmdb (int base_reg, int is_dp, int num_words,
18947 int first_reg)
a504d23a
LA		 18948{
18949 /* A8.8.332 VLDM (A8-922)
9239bbd3
CM		 18950 VLMD{MODE} Rn!, {} (Encoding T1 or T2). */
18951 bfd_vma patched_inst = (is_dp ? 0xed300b00 : 0xed300a00)
a504d23a 18952 | (base_reg << 16)
9239bbd3
CM		 18953 | (num_words & 0x000000ff)
18954 | (((unsigned)first_reg >>1 ) & 0x0000000f) << 12
a504d23a
LA		 18955 | (first_reg & 0x00000001) << 22;
18956
18957 return patched_inst;
18958}
18959
18960static inline bfd_vma
18961create_instruction_udf_w (int value)
18962{
18963 /* A8.8.247 UDF (A8-758)
18964 Undefined (Encoding T2). */
18965 bfd_vma patched_inst = 0xf7f0a000
18966 | (value & 0x00000fff)
18967 | (value & 0x000f0000) << 16;
18968
18969 return patched_inst;
18970}
18971
18972static inline bfd_vma
18973create_instruction_udf (int value)
18974{
18975 /* A8.8.247 UDF (A8-758)
18976 Undefined (Encoding T1). */
18977 bfd_vma patched_inst = 0xde00
18978 | (value & 0xff);
18979
18980 return patched_inst;
18981}
18982
18983/* Functions writing an instruction in memory, returning the next
18984 memory position to write to. */
18985
18986static inline bfd_byte *
18987push_thumb2_insn32 (struct elf32_arm_link_hash_table * htab,
18988 bfd * output_bfd, bfd_byte *pt, insn32 insn)
18989{
18990 put_thumb2_insn (htab, output_bfd, insn, pt);
18991 return pt + 4;
18992}
18993
18994static inline bfd_byte *
18995push_thumb2_insn16 (struct elf32_arm_link_hash_table * htab,
18996 bfd * output_bfd, bfd_byte *pt, insn32 insn)
18997{
18998 put_thumb_insn (htab, output_bfd, insn, pt);
18999 return pt + 2;
19000}
19001
19002/* Function filling up a region in memory with T1 and T2 UDFs taking
19003 care of alignment. */
19004
19005static bfd_byte *
19006stm32l4xx_fill_stub_udf (struct elf32_arm_link_hash_table * htab,
07d6d2b8
AM		 19007 bfd * output_bfd,
19008 const bfd_byte * const base_stub_contents,
19009 bfd_byte * const from_stub_contents,
19010 const bfd_byte * const end_stub_contents)
a504d23a
LA		 19011{
19012 bfd_byte *current_stub_contents = from_stub_contents;
19013
19014 /* Fill the remaining of the stub with deterministic contents : UDF
19015 instructions.
19016 Check if realignment is needed on modulo 4 frontier using T1, to
19017 further use T2. */
19018 if ((current_stub_contents < end_stub_contents)
19019 && !((current_stub_contents - base_stub_contents) % 2)
19020 && ((current_stub_contents - base_stub_contents) % 4))
19021 current_stub_contents =
19022 push_thumb2_insn16 (htab, output_bfd, current_stub_contents,
19023 create_instruction_udf (0));
19024
19025 for (; current_stub_contents < end_stub_contents;)
19026 current_stub_contents =
19027 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19028 create_instruction_udf_w (0));
19029
19030 return current_stub_contents;
19031}
19032
19033/* Functions writing the stream of instructions equivalent to the
19034 derived sequence for ldmia, ldmdb, vldm respectively. */
19035
19036static void
19037stm32l4xx_create_replacing_stub_ldmia (struct elf32_arm_link_hash_table * htab,
19038 bfd * output_bfd,
19039 const insn32 initial_insn,
19040 const bfd_byte *const initial_insn_addr,
19041 bfd_byte *const base_stub_contents)
19042{
19043 int wback = (initial_insn & 0x00200000) >> 21;
19044 int ri, rn = (initial_insn & 0x000F0000) >> 16;
19045 int insn_all_registers = initial_insn & 0x0000ffff;
19046 int insn_low_registers, insn_high_registers;
19047 int usable_register_mask;
b25e998d 19048 int nb_registers = elf32_arm_popcount (insn_all_registers);
a504d23a
LA		 19049 int restore_pc = (insn_all_registers & (1 << 15)) ? 1 : 0;
19050 int restore_rn = (insn_all_registers & (1 << rn)) ? 1 : 0;
19051 bfd_byte *current_stub_contents = base_stub_contents;
19052
19053 BFD_ASSERT (is_thumb2_ldmia (initial_insn));
19054
19055 /* In BFD_ARM_STM32L4XX_FIX_ALL mode we may have to deal with
19056 smaller than 8 registers load sequences that do not cause the
19057 hardware issue. */
19058 if (nb_registers <= 8)
19059 {
19060 /* UNTOUCHED : LDMIA Rn{!}, {R-all-register-list}. */
19061 current_stub_contents =
19062 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19063 initial_insn);
19064
19065 /* B initial_insn_addr+4. */
19066 if (!restore_pc)
19067 current_stub_contents =
19068 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19069 create_instruction_branch_absolute
82188b29 19070 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 19071
19072 /* Fill the remaining of the stub with deterministic contents. */
19073 current_stub_contents =
19074 stm32l4xx_fill_stub_udf (htab, output_bfd,
19075 base_stub_contents, current_stub_contents,
19076 base_stub_contents +
19077 STM32L4XX_ERRATUM_LDM_VENEER_SIZE);
19078
19079 return;
19080 }
19081
19082 /* - reg_list[13] == 0. */
19083 BFD_ASSERT ((insn_all_registers & (1 << 13))==0);
19084
19085 /* - reg_list[14] & reg_list[15] != 1. */
19086 BFD_ASSERT ((insn_all_registers & 0xC000) != 0xC000);
19087
19088 /* - if (wback==1) reg_list[rn] == 0. */
19089 BFD_ASSERT (!wback || !restore_rn);
19090
19091 /* - nb_registers > 8. */
b25e998d 19092 BFD_ASSERT (elf32_arm_popcount (insn_all_registers) > 8);
a504d23a
LA		 19093
19094 /* At this point, LDMxx initial insn loads between 9 and 14 registers. */
19095
19096 /* In the following algorithm, we split this wide LDM using 2 LDM insns:
19097 - One with the 7 lowest registers (register mask 0x007F)
19098 This LDM will finally contain between 2 and 7 registers
19099 - One with the 7 highest registers (register mask 0xDF80)
19100 This ldm will finally contain between 2 and 7 registers. */
19101 insn_low_registers = insn_all_registers & 0x007F;
19102 insn_high_registers = insn_all_registers & 0xDF80;
19103
19104 /* A spare register may be needed during this veneer to temporarily
19105 handle the base register. This register will be restored with the
19106 last LDM operation.
19107 The usable register may be any general purpose register (that
19108 excludes PC, SP, LR : register mask is 0x1FFF). */
19109 usable_register_mask = 0x1FFF;
19110
19111 /* Generate the stub function. */
19112 if (wback)
19113 {
19114 /* LDMIA Rn!, {R-low-register-list} : (Encoding T2). */
19115 current_stub_contents =
19116 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19117 create_instruction_ldmia
19118 (rn, /*wback=*/1, insn_low_registers));
19119
19120 /* LDMIA Rn!, {R-high-register-list} : (Encoding T2). */
19121 current_stub_contents =
19122 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19123 create_instruction_ldmia
19124 (rn, /*wback=*/1, insn_high_registers));
19125 if (!restore_pc)
19126 {
19127 /* B initial_insn_addr+4. */
19128 current_stub_contents =
19129 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19130 create_instruction_branch_absolute
82188b29 19131 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 19132 }
19133 }
19134 else /* if (!wback). */
19135 {
19136 ri = rn;
19137
19138 /* If Rn is not part of the high-register-list, move it there. */
19139 if (!(insn_high_registers & (1 << rn)))
19140 {
19141 /* Choose a Ri in the high-register-list that will be restored. */
19142 ri = ctz (insn_high_registers & usable_register_mask & ~(1 << rn));
19143
19144 /* MOV Ri, Rn. */
19145 current_stub_contents =
19146 push_thumb2_insn16 (htab, output_bfd, current_stub_contents,
19147 create_instruction_mov (ri, rn));
19148 }
19149
19150 /* LDMIA Ri!, {R-low-register-list} : (Encoding T2). */
19151 current_stub_contents =
19152 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19153 create_instruction_ldmia
19154 (ri, /*wback=*/1, insn_low_registers));
19155
19156 /* LDMIA Ri, {R-high-register-list} : (Encoding T2). */
19157 current_stub_contents =
19158 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19159 create_instruction_ldmia
19160 (ri, /*wback=*/0, insn_high_registers));
19161
19162 if (!restore_pc)
19163 {
19164 /* B initial_insn_addr+4. */
19165 current_stub_contents =
19166 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19167 create_instruction_branch_absolute
82188b29 19168 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 19169 }
19170 }
19171
19172 /* Fill the remaining of the stub with deterministic contents. */
19173 current_stub_contents =
19174 stm32l4xx_fill_stub_udf (htab, output_bfd,
19175 base_stub_contents, current_stub_contents,
19176 base_stub_contents +
19177 STM32L4XX_ERRATUM_LDM_VENEER_SIZE);
19178}
19179
19180static void
19181stm32l4xx_create_replacing_stub_ldmdb (struct elf32_arm_link_hash_table * htab,
19182 bfd * output_bfd,
19183 const insn32 initial_insn,
19184 const bfd_byte *const initial_insn_addr,
19185 bfd_byte *const base_stub_contents)
19186{
19187 int wback = (initial_insn & 0x00200000) >> 21;
19188 int ri, rn = (initial_insn & 0x000f0000) >> 16;
19189 int insn_all_registers = initial_insn & 0x0000ffff;
19190 int insn_low_registers, insn_high_registers;
19191 int usable_register_mask;
19192 int restore_pc = (insn_all_registers & (1 << 15)) ? 1 : 0;
19193 int restore_rn = (insn_all_registers & (1 << rn)) ? 1 : 0;
b25e998d 19194 int nb_registers = elf32_arm_popcount (insn_all_registers);
a504d23a
LA		 19195 bfd_byte *current_stub_contents = base_stub_contents;
19196
19197 BFD_ASSERT (is_thumb2_ldmdb (initial_insn));
19198
19199 /* In BFD_ARM_STM32L4XX_FIX_ALL mode we may have to deal with
19200 smaller than 8 registers load sequences that do not cause the
19201 hardware issue. */
19202 if (nb_registers <= 8)
19203 {
19204 /* UNTOUCHED : LDMIA Rn{!}, {R-all-register-list}. */
19205 current_stub_contents =
19206 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19207 initial_insn);
19208
19209 /* B initial_insn_addr+4. */
19210 current_stub_contents =
19211 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19212 create_instruction_branch_absolute
82188b29 19213 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 19214
19215 /* Fill the remaining of the stub with deterministic contents. */
19216 current_stub_contents =
19217 stm32l4xx_fill_stub_udf (htab, output_bfd,
19218 base_stub_contents, current_stub_contents,
19219 base_stub_contents +
19220 STM32L4XX_ERRATUM_LDM_VENEER_SIZE);
19221
19222 return;
19223 }
19224
19225 /* - reg_list[13] == 0. */
19226 BFD_ASSERT ((insn_all_registers & (1 << 13)) == 0);
19227
19228 /* - reg_list[14] & reg_list[15] != 1. */
19229 BFD_ASSERT ((insn_all_registers & 0xC000) != 0xC000);
19230
19231 /* - if (wback==1) reg_list[rn] == 0. */
19232 BFD_ASSERT (!wback || !restore_rn);
19233
19234 /* - nb_registers > 8. */
b25e998d 19235 BFD_ASSERT (elf32_arm_popcount (insn_all_registers) > 8);
a504d23a
LA		 19236
19237 /* At this point, LDMxx initial insn loads between 9 and 14 registers. */
19238
19239 /* In the following algorithm, we split this wide LDM using 2 LDM insn:
19240 - One with the 7 lowest registers (register mask 0x007F)
19241 This LDM will finally contain between 2 and 7 registers
19242 - One with the 7 highest registers (register mask 0xDF80)
19243 This ldm will finally contain between 2 and 7 registers. */
19244 insn_low_registers = insn_all_registers & 0x007F;
19245 insn_high_registers = insn_all_registers & 0xDF80;
19246
19247 /* A spare register may be needed during this veneer to temporarily
19248 handle the base register. This register will be restored with
19249 the last LDM operation.
19250 The usable register may be any general purpose register (that excludes
19251 PC, SP, LR : register mask is 0x1FFF). */
19252 usable_register_mask = 0x1FFF;
19253
19254 /* Generate the stub function. */
19255 if (!wback && !restore_pc && !restore_rn)
19256 {
19257 /* Choose a Ri in the low-register-list that will be restored. */
19258 ri = ctz (insn_low_registers & usable_register_mask & ~(1 << rn));
19259
19260 /* MOV Ri, Rn. */
19261 current_stub_contents =
19262 push_thumb2_insn16 (htab, output_bfd, current_stub_contents,
19263 create_instruction_mov (ri, rn));
19264
19265 /* LDMDB Ri!, {R-high-register-list}. */
19266 current_stub_contents =
19267 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19268 create_instruction_ldmdb
19269 (ri, /*wback=*/1, insn_high_registers));
19270
19271 /* LDMDB Ri, {R-low-register-list}. */
19272 current_stub_contents =
19273 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19274 create_instruction_ldmdb
19275 (ri, /*wback=*/0, insn_low_registers));
19276
19277 /* B initial_insn_addr+4. */
19278 current_stub_contents =
19279 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19280 create_instruction_branch_absolute
82188b29 19281 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 19282 }
19283 else if (wback && !restore_pc && !restore_rn)
19284 {
19285 /* LDMDB Rn!, {R-high-register-list}. */
19286 current_stub_contents =
19287 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19288 create_instruction_ldmdb
19289 (rn, /*wback=*/1, insn_high_registers));
19290
19291 /* LDMDB Rn!, {R-low-register-list}. */
19292 current_stub_contents =
19293 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19294 create_instruction_ldmdb
19295 (rn, /*wback=*/1, insn_low_registers));
19296
19297 /* B initial_insn_addr+4. */
19298 current_stub_contents =
19299 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19300 create_instruction_branch_absolute
82188b29 19301 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 19302 }
19303 else if (!wback && restore_pc && !restore_rn)
19304 {
19305 /* Choose a Ri in the high-register-list that will be restored. */
19306 ri = ctz (insn_high_registers & usable_register_mask & ~(1 << rn));
19307
19308 /* SUB Ri, Rn, #(4*nb_registers). */
19309 current_stub_contents =
19310 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19311 create_instruction_sub (ri, rn, (4 * nb_registers)));
19312
19313 /* LDMIA Ri!, {R-low-register-list}. */
19314 current_stub_contents =
19315 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19316 create_instruction_ldmia
19317 (ri, /*wback=*/1, insn_low_registers));
19318
19319 /* LDMIA Ri, {R-high-register-list}. */
19320 current_stub_contents =
19321 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19322 create_instruction_ldmia
19323 (ri, /*wback=*/0, insn_high_registers));
19324 }
19325 else if (wback && restore_pc && !restore_rn)
19326 {
19327 /* Choose a Ri in the high-register-list that will be restored. */
19328 ri = ctz (insn_high_registers & usable_register_mask & ~(1 << rn));
19329
19330 /* SUB Rn, Rn, #(4*nb_registers) */
19331 current_stub_contents =
19332 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19333 create_instruction_sub (rn, rn, (4 * nb_registers)));
19334
19335 /* MOV Ri, Rn. */
19336 current_stub_contents =
19337 push_thumb2_insn16 (htab, output_bfd, current_stub_contents,
19338 create_instruction_mov (ri, rn));
19339
19340 /* LDMIA Ri!, {R-low-register-list}. */
19341 current_stub_contents =
19342 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19343 create_instruction_ldmia
19344 (ri, /*wback=*/1, insn_low_registers));
19345
19346 /* LDMIA Ri, {R-high-register-list}. */
19347 current_stub_contents =
19348 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19349 create_instruction_ldmia
19350 (ri, /*wback=*/0, insn_high_registers));
19351 }
19352 else if (!wback && !restore_pc && restore_rn)
19353 {
19354 ri = rn;
19355 if (!(insn_low_registers & (1 << rn)))
19356 {
19357 /* Choose a Ri in the low-register-list that will be restored. */
19358 ri = ctz (insn_low_registers & usable_register_mask & ~(1 << rn));
19359
19360 /* MOV Ri, Rn. */
19361 current_stub_contents =
19362 push_thumb2_insn16 (htab, output_bfd, current_stub_contents,
19363 create_instruction_mov (ri, rn));
19364 }
19365
19366 /* LDMDB Ri!, {R-high-register-list}. */
19367 current_stub_contents =
19368 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19369 create_instruction_ldmdb
19370 (ri, /*wback=*/1, insn_high_registers));
19371
19372 /* LDMDB Ri, {R-low-register-list}. */
19373 current_stub_contents =
19374 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19375 create_instruction_ldmdb
19376 (ri, /*wback=*/0, insn_low_registers));
19377
19378 /* B initial_insn_addr+4. */
19379 current_stub_contents =
19380 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19381 create_instruction_branch_absolute
82188b29 19382 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 19383 }
19384 else if (!wback && restore_pc && restore_rn)
19385 {
19386 ri = rn;
19387 if (!(insn_high_registers & (1 << rn)))
19388 {
19389 /* Choose a Ri in the high-register-list that will be restored. */
19390 ri = ctz (insn_high_registers & usable_register_mask & ~(1 << rn));
19391 }
19392
19393 /* SUB Ri, Rn, #(4*nb_registers). */
19394 current_stub_contents =
19395 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19396 create_instruction_sub (ri, rn, (4 * nb_registers)));
19397
19398 /* LDMIA Ri!, {R-low-register-list}. */
19399 current_stub_contents =
19400 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19401 create_instruction_ldmia
19402 (ri, /*wback=*/1, insn_low_registers));
19403
19404 /* LDMIA Ri, {R-high-register-list}. */
19405 current_stub_contents =
19406 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19407 create_instruction_ldmia
19408 (ri, /*wback=*/0, insn_high_registers));
19409 }
19410 else if (wback && restore_rn)
19411 {
19412 /* The assembler should not have accepted to encode this. */
19413 BFD_ASSERT (0 && "Cannot patch an instruction that has an "
19414 "undefined behavior.\n");
19415 }
19416
19417 /* Fill the remaining of the stub with deterministic contents. */
19418 current_stub_contents =
19419 stm32l4xx_fill_stub_udf (htab, output_bfd,
19420 base_stub_contents, current_stub_contents,
19421 base_stub_contents +
19422 STM32L4XX_ERRATUM_LDM_VENEER_SIZE);
19423
19424}
19425
19426static void
19427stm32l4xx_create_replacing_stub_vldm (struct elf32_arm_link_hash_table * htab,
19428 bfd * output_bfd,
19429 const insn32 initial_insn,
19430 const bfd_byte *const initial_insn_addr,
19431 bfd_byte *const base_stub_contents)
19432{
9239bbd3 19433 int num_words = ((unsigned int) initial_insn << 24) >> 24;
a504d23a
LA		 19434 bfd_byte *current_stub_contents = base_stub_contents;
19435
19436 BFD_ASSERT (is_thumb2_vldm (initial_insn));
19437
19438 /* In BFD_ARM_STM32L4XX_FIX_ALL mode we may have to deal with
9239bbd3 19439 smaller than 8 words load sequences that do not cause the
a504d23a 19440 hardware issue. */
9239bbd3 19441 if (num_words <= 8)
a504d23a
LA		 19442 {
19443 /* Untouched instruction. */
19444 current_stub_contents =
19445 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19446 initial_insn);
19447
19448 /* B initial_insn_addr+4. */
19449 current_stub_contents =
19450 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19451 create_instruction_branch_absolute
82188b29 19452 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 19453 }
19454 else
19455 {
9eaff861 19456 bfd_boolean is_dp = /* DP encoding. */
9239bbd3 19457 (initial_insn & 0xfe100f00) == 0xec100b00;
a504d23a
LA		 19458 bfd_boolean is_ia_nobang = /* (IA without !). */
19459 (((initial_insn << 7) >> 28) & 0xd) == 0x4;
19460 bfd_boolean is_ia_bang = /* (IA with !) - includes VPOP. */
19461 (((initial_insn << 7) >> 28) & 0xd) == 0x5;
19462 bfd_boolean is_db_bang = /* (DB with !). */
19463 (((initial_insn << 7) >> 28) & 0xd) == 0x9;
9239bbd3 19464 int base_reg = ((unsigned int) initial_insn << 12) >> 28;
a504d23a 19465 /* d = UInt (Vd:D);. */
9239bbd3 19466 int first_reg = ((((unsigned int) initial_insn << 16) >> 28) << 1)
a504d23a
LA		 19467 | (((unsigned int)initial_insn << 9) >> 31);
19468
9239bbd3
CM		 19469 /* Compute the number of 8-words chunks needed to split. */
19470 int chunks = (num_words % 8) ? (num_words / 8 + 1) : (num_words / 8);
a504d23a
LA		 19471 int chunk;
19472
19473 /* The test coverage has been done assuming the following
19474 hypothesis that exactly one of the previous is_ predicates is
19475 true. */
9239bbd3
CM		 19476 BFD_ASSERT ( (is_ia_nobang ^ is_ia_bang ^ is_db_bang)
19477 && !(is_ia_nobang & is_ia_bang & is_db_bang));
a504d23a 19478
9239bbd3 19479 /* We treat the cutting of the words in one pass for all
a504d23a
LA		 19480 cases, then we emit the adjustments:
19481
19482 vldm rx, {...}
19483 -> vldm rx!, {8_words_or_less} for each needed 8_word
19484 -> sub rx, rx, #size (list)
19485
19486 vldm rx!, {...}
19487 -> vldm rx!, {8_words_or_less} for each needed 8_word
19488 This also handles vpop instruction (when rx is sp)
19489
19490 vldmd rx!, {...}
19491 -> vldmb rx!, {8_words_or_less} for each needed 8_word. */
9239bbd3 19492 for (chunk = 0; chunk < chunks; ++chunk)
a504d23a 19493 {
9239bbd3
CM		 19494 bfd_vma new_insn = 0;
19495
a504d23a
LA		 19496 if (is_ia_nobang || is_ia_bang)
19497 {
9239bbd3
CM		 19498 new_insn = create_instruction_vldmia
19499 (base_reg,
19500 is_dp,
19501 /*wback= . */1,
19502 chunks - (chunk + 1) ?
19503 8 : num_words - chunk * 8,
19504 first_reg + chunk * 8);
a504d23a
LA		 19505 }
19506 else if (is_db_bang)
19507 {
9239bbd3
CM		 19508 new_insn = create_instruction_vldmdb
19509 (base_reg,
19510 is_dp,
19511 chunks - (chunk + 1) ?
19512 8 : num_words - chunk * 8,
19513 first_reg + chunk * 8);
a504d23a 19514 }
9239bbd3
CM		 19515
19516 if (new_insn)
19517 current_stub_contents =
19518 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19519 new_insn);
a504d23a
LA		 19520 }
19521
19522 /* Only this case requires the base register compensation
19523 subtract. */
19524 if (is_ia_nobang)
19525 {
19526 current_stub_contents =
19527 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19528 create_instruction_sub
9239bbd3 19529 (base_reg, base_reg, 4*num_words));
a504d23a
LA		 19530 }
19531
19532 /* B initial_insn_addr+4. */
19533 current_stub_contents =
19534 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19535 create_instruction_branch_absolute
82188b29 19536 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 19537 }
19538
19539 /* Fill the remaining of the stub with deterministic contents. */
19540 current_stub_contents =
19541 stm32l4xx_fill_stub_udf (htab, output_bfd,
19542 base_stub_contents, current_stub_contents,
19543 base_stub_contents +
19544 STM32L4XX_ERRATUM_VLDM_VENEER_SIZE);
19545}
19546
19547static void
19548stm32l4xx_create_replacing_stub (struct elf32_arm_link_hash_table * htab,
19549 bfd * output_bfd,
19550 const insn32 wrong_insn,
19551 const bfd_byte *const wrong_insn_addr,
19552 bfd_byte *const stub_contents)
19553{
19554 if (is_thumb2_ldmia (wrong_insn))
19555 stm32l4xx_create_replacing_stub_ldmia (htab, output_bfd,
19556 wrong_insn, wrong_insn_addr,
19557 stub_contents);
19558 else if (is_thumb2_ldmdb (wrong_insn))
19559 stm32l4xx_create_replacing_stub_ldmdb (htab, output_bfd,
19560 wrong_insn, wrong_insn_addr,
19561 stub_contents);
19562 else if (is_thumb2_vldm (wrong_insn))
19563 stm32l4xx_create_replacing_stub_vldm (htab, output_bfd,
19564 wrong_insn, wrong_insn_addr,
19565 stub_contents);
19566}
19567
19568/* End of stm32l4xx work-around. */
19569
19570
e489d0ae
PB		 19571/* Do code byteswapping. Return FALSE afterwards so that the section is
19572 written out as normal. */
19573
19574static bfd_boolean
c7b8f16e 19575elf32_arm_write_section (bfd *output_bfd,
8029a119
NC		 19576 struct bfd_link_info *link_info,
19577 asection *sec,
e489d0ae
PB		 19578 bfd_byte *contents)
19579{
48229727 19580 unsigned int mapcount, errcount;
8e3de13a 19581 _arm_elf_section_data *arm_data;
c7b8f16e 19582 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (link_info);
e489d0ae 19583 elf32_arm_section_map *map;
c7b8f16e 19584 elf32_vfp11_erratum_list *errnode;
a504d23a 19585 elf32_stm32l4xx_erratum_list *stm32l4xx_errnode;
e489d0ae
PB		 19586 bfd_vma ptr;
19587 bfd_vma end;
c7b8f16e 19588 bfd_vma offset = sec->output_section->vma + sec->output_offset;
e489d0ae 19589 bfd_byte tmp;
48229727 19590 unsigned int i;
57e8b36a 19591
4dfe6ac6
NC		 19592 if (globals == NULL)
19593 return FALSE;
19594
8e3de13a
NC		 19595 /* If this section has not been allocated an _arm_elf_section_data
19596 structure then we cannot record anything. */
19597 arm_data = get_arm_elf_section_data (sec);
19598 if (arm_data == NULL)
19599 return FALSE;
19600
19601 mapcount = arm_data->mapcount;
19602 map = arm_data->map;
c7b8f16e
JB		 19603 errcount = arm_data->erratumcount;
19604
19605 if (errcount != 0)
19606 {
19607 unsigned int endianflip = bfd_big_endian (output_bfd) ? 3 : 0;
19608
19609 for (errnode = arm_data->erratumlist; errnode != 0;
99059e56
RM		 19610 errnode = errnode->next)
19611 {
19612 bfd_vma target = errnode->vma - offset;
19613
19614 switch (errnode->type)
19615 {
19616 case VFP11_ERRATUM_BRANCH_TO_ARM_VENEER:
19617 {
19618 bfd_vma branch_to_veneer;
19619 /* Original condition code of instruction, plus bit mask for
19620 ARM B instruction. */
19621 unsigned int insn = (errnode->u.b.vfp_insn & 0xf0000000)
19622 | 0x0a000000;
c7b8f16e
JB		 19623
19624 /* The instruction is before the label. */
91d6fa6a 19625 target -= 4;
c7b8f16e
JB		 19626
19627 /* Above offset included in -4 below. */
19628 branch_to_veneer = errnode->u.b.veneer->vma
99059e56 19629 - errnode->vma - 4;
c7b8f16e
JB		 19630
19631 if ((signed) branch_to_veneer < -(1 << 25)
19632 || (signed) branch_to_veneer >= (1 << 25))
871b3ab2 19633 _bfd_error_handler (_("%pB: error: VFP11 veneer out of "
4eca0228 19634 "range"), output_bfd);
c7b8f16e 19635
99059e56
RM		 19636 insn |= (branch_to_veneer >> 2) & 0xffffff;
19637 contents[endianflip ^ target] = insn & 0xff;
19638 contents[endianflip ^ (target + 1)] = (insn >> 8) & 0xff;
19639 contents[endianflip ^ (target + 2)] = (insn >> 16) & 0xff;
19640 contents[endianflip ^ (target + 3)] = (insn >> 24) & 0xff;
19641 }
19642 break;
c7b8f16e
JB		 19643
19644 case VFP11_ERRATUM_ARM_VENEER:
99059e56
RM		 19645 {
19646 bfd_vma branch_from_veneer;
19647 unsigned int insn;
c7b8f16e 19648
99059e56
RM		 19649 /* Take size of veneer into account. */
19650 branch_from_veneer = errnode->u.v.branch->vma
19651 - errnode->vma - 12;
c7b8f16e
JB		 19652
19653 if ((signed) branch_from_veneer < -(1 << 25)
19654 || (signed) branch_from_veneer >= (1 << 25))
871b3ab2 19655 _bfd_error_handler (_("%pB: error: VFP11 veneer out of "
4eca0228 19656 "range"), output_bfd);
c7b8f16e 19657
99059e56
RM		 19658 /* Original instruction. */
19659 insn = errnode->u.v.branch->u.b.vfp_insn;
19660 contents[endianflip ^ target] = insn & 0xff;
19661 contents[endianflip ^ (target + 1)] = (insn >> 8) & 0xff;
19662 contents[endianflip ^ (target + 2)] = (insn >> 16) & 0xff;
19663 contents[endianflip ^ (target + 3)] = (insn >> 24) & 0xff;
19664
19665 /* Branch back to insn after original insn. */
19666 insn = 0xea000000 | ((branch_from_veneer >> 2) & 0xffffff);
19667 contents[endianflip ^ (target + 4)] = insn & 0xff;
19668 contents[endianflip ^ (target + 5)] = (insn >> 8) & 0xff;
19669 contents[endianflip ^ (target + 6)] = (insn >> 16) & 0xff;
19670 contents[endianflip ^ (target + 7)] = (insn >> 24) & 0xff;
19671 }
19672 break;
c7b8f16e 19673
99059e56
RM		 19674 default:
19675 abort ();
19676 }
19677 }
c7b8f16e 19678 }
e489d0ae 19679
a504d23a
LA		 19680 if (arm_data->stm32l4xx_erratumcount != 0)
19681 {
19682 for (stm32l4xx_errnode = arm_data->stm32l4xx_erratumlist;
19683 stm32l4xx_errnode != 0;
19684 stm32l4xx_errnode = stm32l4xx_errnode->next)
19685 {
19686 bfd_vma target = stm32l4xx_errnode->vma - offset;
19687
19688 switch (stm32l4xx_errnode->type)
19689 {
19690 case STM32L4XX_ERRATUM_BRANCH_TO_VENEER:
19691 {
19692 unsigned int insn;
19693 bfd_vma branch_to_veneer =
19694 stm32l4xx_errnode->u.b.veneer->vma - stm32l4xx_errnode->vma;
19695
19696 if ((signed) branch_to_veneer < -(1 << 24)
19697 || (signed) branch_to_veneer >= (1 << 24))
19698 {
19699 bfd_vma out_of_range =
19700 ((signed) branch_to_veneer < -(1 << 24)) ?
19701 - branch_to_veneer - (1 << 24) :
19702 ((signed) branch_to_veneer >= (1 << 24)) ?
19703 branch_to_veneer - (1 << 24) : 0;
19704
4eca0228 19705 _bfd_error_handler
2dcf00ce 19706 (_("%pB(%#" PRIx64 "): error: "
90b6238f
AM		 19707 "cannot create STM32L4XX veneer; "
19708 "jump out of range by %" PRId64 " bytes; "
19709 "cannot encode branch instruction"),
a504d23a 19710 output_bfd,
2dcf00ce
AM		 19711 (uint64_t) (stm32l4xx_errnode->vma - 4),
19712 (int64_t) out_of_range);
a504d23a
LA		 19713 continue;
19714 }
19715
19716 insn = create_instruction_branch_absolute
82188b29 19717 (stm32l4xx_errnode->u.b.veneer->vma - stm32l4xx_errnode->vma);
a504d23a 19718
a2699ef2
AM		 19719 /* The instruction is before the label. */
19720 target -= 4;
19721
a504d23a
LA		 19722 put_thumb2_insn (globals, output_bfd,
19723 (bfd_vma) insn, contents + target);
19724 }
19725 break;
19726
19727 case STM32L4XX_ERRATUM_VENEER:
19728 {
82188b29
NC		 19729 bfd_byte * veneer;
19730 bfd_byte * veneer_r;
a504d23a
LA		 19731 unsigned int insn;
19732
82188b29
NC		 19733 veneer = contents + target;
19734 veneer_r = veneer
19735 + stm32l4xx_errnode->u.b.veneer->vma
19736 - stm32l4xx_errnode->vma - 4;
a504d23a
LA		 19737
19738 if ((signed) (veneer_r - veneer -
19739 STM32L4XX_ERRATUM_VLDM_VENEER_SIZE >
19740 STM32L4XX_ERRATUM_LDM_VENEER_SIZE ?
19741 STM32L4XX_ERRATUM_VLDM_VENEER_SIZE :
19742 STM32L4XX_ERRATUM_LDM_VENEER_SIZE) < -(1 << 24)
19743 || (signed) (veneer_r - veneer) >= (1 << 24))
19744 {
90b6238f
AM		 19745 _bfd_error_handler (_("%pB: error: cannot create STM32L4XX "
19746 "veneer"), output_bfd);
a504d23a
LA		 19747 continue;
19748 }
19749
19750 /* Original instruction. */
19751 insn = stm32l4xx_errnode->u.v.branch->u.b.insn;
19752
19753 stm32l4xx_create_replacing_stub
19754 (globals, output_bfd, insn, (void*)veneer_r, (void*)veneer);
19755 }
19756 break;
19757
19758 default:
19759 abort ();
19760 }
19761 }
19762 }
19763
2468f9c9
PB		 19764 if (arm_data->elf.this_hdr.sh_type == SHT_ARM_EXIDX)
19765 {
19766 arm_unwind_table_edit *edit_node
99059e56 19767 = arm_data->u.exidx.unwind_edit_list;
2468f9c9 19768 /* Now, sec->size is the size of the section we will write. The original
99059e56 19769 size (before we merged duplicate entries and inserted EXIDX_CANTUNWIND
2468f9c9
PB		 19770 markers) was sec->rawsize. (This isn't the case if we perform no
19771 edits, then rawsize will be zero and we should use size). */
21d799b5 19772 bfd_byte *edited_contents = (bfd_byte *) bfd_malloc (sec->size);
2468f9c9
PB		 19773 unsigned int input_size = sec->rawsize ? sec->rawsize : sec->size;
19774 unsigned int in_index, out_index;
19775 bfd_vma add_to_offsets = 0;
19776
19777 for (in_index = 0, out_index = 0; in_index * 8 < input_size || edit_node;)
99059e56 19778 {
2468f9c9
PB		 19779 if (edit_node)
19780 {
19781 unsigned int edit_index = edit_node->index;
b38cadfb 19782
2468f9c9 19783 if (in_index < edit_index && in_index * 8 < input_size)
99059e56 19784 {
2468f9c9
PB		 19785 copy_exidx_entry (output_bfd, edited_contents + out_index * 8,
19786 contents + in_index * 8, add_to_offsets);
19787 out_index++;
19788 in_index++;
19789 }
19790 else if (in_index == edit_index
19791 || (in_index * 8 >= input_size
19792 && edit_index == UINT_MAX))
99059e56 19793 {
2468f9c9
PB		 19794 switch (edit_node->type)
19795 {
19796 case DELETE_EXIDX_ENTRY:
19797 in_index++;
19798 add_to_offsets += 8;
19799 break;
b38cadfb 19800
2468f9c9
PB		 19801 case INSERT_EXIDX_CANTUNWIND_AT_END:
19802 {
99059e56 19803 asection *text_sec = edit_node->linked_section;
2468f9c9
PB		 19804 bfd_vma text_offset = text_sec->output_section->vma
19805 + text_sec->output_offset
19806 + text_sec->size;
19807 bfd_vma exidx_offset = offset + out_index * 8;
99059e56 19808 unsigned long prel31_offset;
2468f9c9
PB		 19809
19810 /* Note: this is meant to be equivalent to an
19811 R_ARM_PREL31 relocation. These synthetic
19812 EXIDX_CANTUNWIND markers are not relocated by the
19813 usual BFD method. */
19814 prel31_offset = (text_offset - exidx_offset)
19815 & 0x7ffffffful;
491d01d3
YU		 19816 if (bfd_link_relocatable (link_info))
19817 {
19818 /* Here relocation for new EXIDX_CANTUNWIND is
19819 created, so there is no need to
19820 adjust offset by hand. */
19821 prel31_offset = text_sec->output_offset
19822 + text_sec->size;
491d01d3 19823 }
2468f9c9
PB		 19824
19825 /* First address we can't unwind. */
19826 bfd_put_32 (output_bfd, prel31_offset,
19827 &edited_contents[out_index * 8]);
19828
19829 /* Code for EXIDX_CANTUNWIND. */
19830 bfd_put_32 (output_bfd, 0x1,
19831 &edited_contents[out_index * 8 + 4]);
19832
19833 out_index++;
19834 add_to_offsets -= 8;
19835 }
19836 break;
19837 }
b38cadfb 19838
2468f9c9
PB		 19839 edit_node = edit_node->next;
19840 }
19841 }
19842 else
19843 {
19844 /* No more edits, copy remaining entries verbatim. */
19845 copy_exidx_entry (output_bfd, edited_contents + out_index * 8,
19846 contents + in_index * 8, add_to_offsets);
19847 out_index++;
19848 in_index++;
19849 }
19850 }
19851
19852 if (!(sec->flags & SEC_EXCLUDE) && !(sec->flags & SEC_NEVER_LOAD))
19853 bfd_set_section_contents (output_bfd, sec->output_section,
19854 edited_contents,
19855 (file_ptr) sec->output_offset, sec->size);
19856
19857 return TRUE;
19858 }
19859
48229727
JB		 19860 /* Fix code to point to Cortex-A8 erratum stubs. */
19861 if (globals->fix_cortex_a8)
19862 {
19863 struct a8_branch_to_stub_data data;
19864
19865 data.writing_section = sec;
19866 data.contents = contents;
19867
a504d23a
LA		 19868 bfd_hash_traverse (& globals->stub_hash_table, make_branch_to_a8_stub,
19869 & data);
48229727
JB		 19870 }
19871
e489d0ae
PB		 19872 if (mapcount == 0)
19873 return FALSE;
19874
c7b8f16e 19875 if (globals->byteswap_code)
e489d0ae 19876 {
c7b8f16e 19877 qsort (map, mapcount, sizeof (* map), elf32_arm_compare_mapping);
57e8b36a 19878
c7b8f16e
JB		 19879 ptr = map[0].vma;
19880 for (i = 0; i < mapcount; i++)
99059e56
RM		 19881 {
19882 if (i == mapcount - 1)
c7b8f16e 19883 end = sec->size;
99059e56
RM		 19884 else
19885 end = map[i + 1].vma;
e489d0ae 19886
99059e56 19887 switch (map[i].type)
e489d0ae 19888 {
c7b8f16e
JB		 19889 case 'a':
19890 /* Byte swap code words. */
19891 while (ptr + 3 < end)
99059e56
RM		 19892 {
19893 tmp = contents[ptr];
19894 contents[ptr] = contents[ptr + 3];
19895 contents[ptr + 3] = tmp;
19896 tmp = contents[ptr + 1];
19897 contents[ptr + 1] = contents[ptr + 2];
19898 contents[ptr + 2] = tmp;
19899 ptr += 4;
19900 }
c7b8f16e 19901 break;
e489d0ae 19902
c7b8f16e
JB		 19903 case 't':
19904 /* Byte swap code halfwords. */
19905 while (ptr + 1 < end)
99059e56
RM		 19906 {
19907 tmp = contents[ptr];
19908 contents[ptr] = contents[ptr + 1];
19909 contents[ptr + 1] = tmp;
19910 ptr += 2;
19911 }
c7b8f16e
JB		 19912 break;
19913
19914 case 'd':
19915 /* Leave data alone. */
19916 break;
19917 }
99059e56
RM		 19918 ptr = end;
19919 }
e489d0ae 19920 }
8e3de13a 19921
93204d3a 19922 free (map);
47b2e99c 19923 arm_data->mapcount = -1;
c7b8f16e 19924 arm_data->mapsize = 0;
8e3de13a 19925 arm_data->map = NULL;
8e3de13a 19926
e489d0ae
PB		 19927 return FALSE;
19928}
19929
0beaef2b
PB		 19930/* Mangle thumb function symbols as we read them in. */
19931
8384fb8f 19932static bfd_boolean
0beaef2b
PB		 19933elf32_arm_swap_symbol_in (bfd * abfd,
19934 const void *psrc,
19935 const void *pshn,
19936 Elf_Internal_Sym *dst)
19937{
4ba2ef8f
TP		 19938 Elf_Internal_Shdr *symtab_hdr;
19939 const char *name = NULL;
19940
8384fb8f
AM		 19941 if (!bfd_elf32_swap_symbol_in (abfd, psrc, pshn, dst))
19942 return FALSE;
39d911fc 19943 dst->st_target_internal = 0;
0beaef2b
PB		 19944
19945 /* New EABI objects mark thumb function symbols by setting the low bit of
35fc36a8 19946 the address. */
63e1a0fc
PB		 19947 if (ELF_ST_TYPE (dst->st_info) == STT_FUNC
19948 || ELF_ST_TYPE (dst->st_info) == STT_GNU_IFUNC)
0beaef2b 19949 {
63e1a0fc
PB		 19950 if (dst->st_value & 1)
19951 {
19952 dst->st_value &= ~(bfd_vma) 1;
39d911fc
TP		 19953 ARM_SET_SYM_BRANCH_TYPE (dst->st_target_internal,
19954 ST_BRANCH_TO_THUMB);
63e1a0fc
PB		 19955 }
19956 else
39d911fc 19957 ARM_SET_SYM_BRANCH_TYPE (dst->st_target_internal, ST_BRANCH_TO_ARM);
35fc36a8
RS		 19958 }
19959 else if (ELF_ST_TYPE (dst->st_info) == STT_ARM_TFUNC)
19960 {
19961 dst->st_info = ELF_ST_INFO (ELF_ST_BIND (dst->st_info), STT_FUNC);
39d911fc 19962 ARM_SET_SYM_BRANCH_TYPE (dst->st_target_internal, ST_BRANCH_TO_THUMB);
0beaef2b 19963 }
35fc36a8 19964 else if (ELF_ST_TYPE (dst->st_info) == STT_SECTION)
39d911fc 19965 ARM_SET_SYM_BRANCH_TYPE (dst->st_target_internal, ST_BRANCH_LONG);
35fc36a8 19966 else
39d911fc 19967 ARM_SET_SYM_BRANCH_TYPE (dst->st_target_internal, ST_BRANCH_UNKNOWN);
35fc36a8 19968
4ba2ef8f
TP		 19969 /* Mark CMSE special symbols. */
19970 symtab_hdr = & elf_symtab_hdr (abfd);
19971 if (symtab_hdr->sh_size)
19972 name = bfd_elf_sym_name (abfd, symtab_hdr, dst, NULL);
19973 if (name && CONST_STRNEQ (name, CMSE_PREFIX))
19974 ARM_SET_SYM_CMSE_SPCL (dst->st_target_internal);
19975
8384fb8f 19976 return TRUE;
0beaef2b
PB		 19977}
19978
19979
19980/* Mangle thumb function symbols as we write them out. */
19981
19982static void
19983elf32_arm_swap_symbol_out (bfd *abfd,
19984 const Elf_Internal_Sym *src,
19985 void *cdst,
19986 void *shndx)
19987{
19988 Elf_Internal_Sym newsym;
19989
19990 /* We convert STT_ARM_TFUNC symbols into STT_FUNC with the low bit
19991 of the address set, as per the new EABI. We do this unconditionally
19992 because objcopy does not set the elf header flags until after
19993 it writes out the symbol table. */
39d911fc 19994 if (ARM_GET_SYM_BRANCH_TYPE (src->st_target_internal) == ST_BRANCH_TO_THUMB)
0beaef2b
PB		 19995 {
19996 newsym = *src;
34e77a92
RS		 19997 if (ELF_ST_TYPE (src->st_info) != STT_GNU_IFUNC)
19998 newsym.st_info = ELF_ST_INFO (ELF_ST_BIND (src->st_info), STT_FUNC);
0fa3dcad 19999 if (newsym.st_shndx != SHN_UNDEF)
99059e56
RM		 20000 {
20001 /* Do this only for defined symbols. At link type, the static
20002 linker will simulate the work of dynamic linker of resolving
20003 symbols and will carry over the thumbness of found symbols to
20004 the output symbol table. It's not clear how it happens, but
20005 the thumbness of undefined symbols can well be different at
20006 runtime, and writing '1' for them will be confusing for users
20007 and possibly for dynamic linker itself.
20008 */
20009 newsym.st_value |= 1;
20010 }
906e58ca 20011
0beaef2b
PB		 20012 src = &newsym;
20013 }
20014 bfd_elf32_swap_symbol_out (abfd, src, cdst, shndx);
20015}
20016
b294bdf8
MM		 20017/* Add the PT_ARM_EXIDX program header. */
20018
20019static bfd_boolean
906e58ca 20020elf32_arm_modify_segment_map (bfd *abfd,
b294bdf8
MM		 20021 struct bfd_link_info *info ATTRIBUTE_UNUSED)
20022{
20023 struct elf_segment_map *m;
20024 asection *sec;
20025
20026 sec = bfd_get_section_by_name (abfd, ".ARM.exidx");
20027 if (sec != NULL && (sec->flags & SEC_LOAD) != 0)
20028 {
20029 /* If there is already a PT_ARM_EXIDX header, then we do not
20030 want to add another one. This situation arises when running
20031 "strip"; the input binary already has the header. */
12bd6957 20032 m = elf_seg_map (abfd);
b294bdf8
MM		 20033 while (m && m->p_type != PT_ARM_EXIDX)
20034 m = m->next;
20035 if (!m)
20036 {
21d799b5 20037 m = (struct elf_segment_map *)
99059e56 20038 bfd_zalloc (abfd, sizeof (struct elf_segment_map));
b294bdf8
MM		 20039 if (m == NULL)
20040 return FALSE;
20041 m->p_type = PT_ARM_EXIDX;
20042 m->count = 1;
20043 m->sections[0] = sec;
20044
12bd6957
AM		 20045 m->next = elf_seg_map (abfd);
20046 elf_seg_map (abfd) = m;
b294bdf8
MM		 20047 }
20048 }
20049
20050 return TRUE;
20051}
20052
20053/* We may add a PT_ARM_EXIDX program header. */
20054
20055static int
a6b96beb
AM		 20056elf32_arm_additional_program_headers (bfd *abfd,
20057 struct bfd_link_info *info ATTRIBUTE_UNUSED)
b294bdf8
MM		 20058{
20059 asection *sec;
20060
20061 sec = bfd_get_section_by_name (abfd, ".ARM.exidx");
20062 if (sec != NULL && (sec->flags & SEC_LOAD) != 0)
20063 return 1;
20064 else
20065 return 0;
20066}
20067
34e77a92
RS		 20068/* Hook called by the linker routine which adds symbols from an object
20069 file. */
20070
20071static bfd_boolean
20072elf32_arm_add_symbol_hook (bfd *abfd, struct bfd_link_info *info,
20073 Elf_Internal_Sym *sym, const char **namep,
20074 flagword *flagsp, asection **secp, bfd_vma *valp)
20075{
c792917c
NC		 20076 if (elf32_arm_hash_table (info) == NULL)
20077 return FALSE;
20078
34e77a92
RS		 20079 if (elf32_arm_hash_table (info)->vxworks_p
20080 && !elf_vxworks_add_symbol_hook (abfd, info, sym, namep,
20081 flagsp, secp, valp))
20082 return FALSE;
20083
20084 return TRUE;
20085}
20086
0beaef2b 20087/* We use this to override swap_symbol_in and swap_symbol_out. */
906e58ca
NC		 20088const struct elf_size_info elf32_arm_size_info =
20089{
0beaef2b
PB		 20090 sizeof (Elf32_External_Ehdr),
20091 sizeof (Elf32_External_Phdr),
20092 sizeof (Elf32_External_Shdr),
20093 sizeof (Elf32_External_Rel),
20094 sizeof (Elf32_External_Rela),
20095 sizeof (Elf32_External_Sym),
20096 sizeof (Elf32_External_Dyn),
20097 sizeof (Elf_External_Note),
20098 4,
20099 1,
20100 32, 2,
20101 ELFCLASS32, EV_CURRENT,
20102 bfd_elf32_write_out_phdrs,
20103 bfd_elf32_write_shdrs_and_ehdr,
1489a3a0 20104 bfd_elf32_checksum_contents,
0beaef2b
PB		 20105 bfd_elf32_write_relocs,
20106 elf32_arm_swap_symbol_in,
20107 elf32_arm_swap_symbol_out,
20108 bfd_elf32_slurp_reloc_table,
20109 bfd_elf32_slurp_symbol_table,
20110 bfd_elf32_swap_dyn_in,
20111 bfd_elf32_swap_dyn_out,
20112 bfd_elf32_swap_reloc_in,
20113 bfd_elf32_swap_reloc_out,
20114 bfd_elf32_swap_reloca_in,
20115 bfd_elf32_swap_reloca_out
20116};
20117
685e70ae
VK		 20118static bfd_vma
20119read_code32 (const bfd *abfd, const bfd_byte *addr)
20120{
20121 /* V7 BE8 code is always little endian. */
20122 if ((elf_elfheader (abfd)->e_flags & EF_ARM_BE8) != 0)
20123 return bfd_getl32 (addr);
20124
20125 return bfd_get_32 (abfd, addr);
20126}
20127
20128static bfd_vma
20129read_code16 (const bfd *abfd, const bfd_byte *addr)
20130{
20131 /* V7 BE8 code is always little endian. */
20132 if ((elf_elfheader (abfd)->e_flags & EF_ARM_BE8) != 0)
20133 return bfd_getl16 (addr);
20134
20135 return bfd_get_16 (abfd, addr);
20136}
20137
6a631e86
YG		 20138/* Return size of plt0 entry starting at ADDR
20139 or (bfd_vma) -1 if size can not be determined. */
20140
20141static bfd_vma
20142elf32_arm_plt0_size (const bfd *abfd, const bfd_byte *addr)
20143{
20144 bfd_vma first_word;
20145 bfd_vma plt0_size;
20146
685e70ae 20147 first_word = read_code32 (abfd, addr);
6a631e86
YG		 20148
20149 if (first_word == elf32_arm_plt0_entry[0])
20150 plt0_size = 4 * ARRAY_SIZE (elf32_arm_plt0_entry);
20151 else if (first_word == elf32_thumb2_plt0_entry[0])
20152 plt0_size = 4 * ARRAY_SIZE (elf32_thumb2_plt0_entry);
20153 else
20154 /* We don't yet handle this PLT format. */
20155 return (bfd_vma) -1;
20156
20157 return plt0_size;
20158}
20159
20160/* Return size of plt entry starting at offset OFFSET
20161 of plt section located at address START
20162 or (bfd_vma) -1 if size can not be determined. */
20163
20164static bfd_vma
20165elf32_arm_plt_size (const bfd *abfd, const bfd_byte *start, bfd_vma offset)
20166{
20167 bfd_vma first_insn;
20168 bfd_vma plt_size = 0;
20169 const bfd_byte *addr = start + offset;
20170
20171 /* PLT entry size if fixed on Thumb-only platforms. */
685e70ae 20172 if (read_code32 (abfd, start) == elf32_thumb2_plt0_entry[0])
6a631e86
YG		 20173 return 4 * ARRAY_SIZE (elf32_thumb2_plt_entry);
20174
20175 /* Respect Thumb stub if necessary. */
685e70ae 20176 if (read_code16 (abfd, addr) == elf32_arm_plt_thumb_stub[0])
6a631e86
YG		 20177 {
20178 plt_size += 2 * ARRAY_SIZE(elf32_arm_plt_thumb_stub);
20179 }
20180
20181 /* Strip immediate from first add. */
685e70ae 20182 first_insn = read_code32 (abfd, addr + plt_size) & 0xffffff00;
6a631e86
YG		 20183
20184#ifdef FOUR_WORD_PLT
20185 if (first_insn == elf32_arm_plt_entry[0])
20186 plt_size += 4 * ARRAY_SIZE (elf32_arm_plt_entry);
20187#else
20188 if (first_insn == elf32_arm_plt_entry_long[0])
20189 plt_size += 4 * ARRAY_SIZE (elf32_arm_plt_entry_long);
20190 else if (first_insn == elf32_arm_plt_entry_short[0])
20191 plt_size += 4 * ARRAY_SIZE (elf32_arm_plt_entry_short);
20192#endif
20193 else
20194 /* We don't yet handle this PLT format. */
20195 return (bfd_vma) -1;
20196
20197 return plt_size;
20198}
20199
20200/* Implementation is shamelessly borrowed from _bfd_elf_get_synthetic_symtab. */
20201
20202static long
20203elf32_arm_get_synthetic_symtab (bfd *abfd,
20204 long symcount ATTRIBUTE_UNUSED,
20205 asymbol **syms ATTRIBUTE_UNUSED,
20206 long dynsymcount,
20207 asymbol **dynsyms,
20208 asymbol **ret)
20209{
20210 asection *relplt;
20211 asymbol *s;
20212 arelent *p;
20213 long count, i, n;
20214 size_t size;
20215 Elf_Internal_Shdr *hdr;
20216 char *names;
20217 asection *plt;
20218 bfd_vma offset;
20219 bfd_byte *data;
20220
20221 *ret = NULL;
20222
20223 if ((abfd->flags & (DYNAMIC | EXEC_P)) == 0)
20224 return 0;
20225
20226 if (dynsymcount <= 0)
20227 return 0;
20228
20229 relplt = bfd_get_section_by_name (abfd, ".rel.plt");
20230 if (relplt == NULL)
20231 return 0;
20232
20233 hdr = &elf_section_data (relplt)->this_hdr;
20234 if (hdr->sh_link != elf_dynsymtab (abfd)
20235 || (hdr->sh_type != SHT_REL && hdr->sh_type != SHT_RELA))
20236 return 0;
20237
20238 plt = bfd_get_section_by_name (abfd, ".plt");
20239 if (plt == NULL)
20240 return 0;
20241
20242 if (!elf32_arm_size_info.slurp_reloc_table (abfd, relplt, dynsyms, TRUE))
20243 return -1;
20244
20245 data = plt->contents;
20246 if (data == NULL)
20247 {
20248 if (!bfd_get_full_section_contents(abfd, (asection *) plt, &data) || data == NULL)
20249 return -1;
20250 bfd_cache_section_contents((asection *) plt, data);
20251 }
20252
20253 count = relplt->size / hdr->sh_entsize;
20254 size = count * sizeof (asymbol);
20255 p = relplt->relocation;
20256 for (i = 0; i < count; i++, p += elf32_arm_size_info.int_rels_per_ext_rel)
20257 {
20258 size += strlen ((*p->sym_ptr_ptr)->name) + sizeof ("@plt");
20259 if (p->addend != 0)
20260 size += sizeof ("+0x") - 1 + 8;
20261 }
20262
20263 s = *ret = (asymbol *) bfd_malloc (size);
20264 if (s == NULL)
20265 return -1;
20266
20267 offset = elf32_arm_plt0_size (abfd, data);
20268 if (offset == (bfd_vma) -1)
20269 return -1;
20270
20271 names = (char *) (s + count);
20272 p = relplt->relocation;
20273 n = 0;
20274 for (i = 0; i < count; i++, p += elf32_arm_size_info.int_rels_per_ext_rel)
20275 {
20276 size_t len;
20277
20278 bfd_vma plt_size = elf32_arm_plt_size (abfd, data, offset);
20279 if (plt_size == (bfd_vma) -1)
20280 break;
20281
20282 *s = **p->sym_ptr_ptr;
20283 /* Undefined syms won't have BSF_LOCAL or BSF_GLOBAL set. Since
20284 we are defining a symbol, ensure one of them is set. */
20285 if ((s->flags & BSF_LOCAL) == 0)
20286 s->flags |= BSF_GLOBAL;
20287 s->flags |= BSF_SYNTHETIC;
20288 s->section = plt;
20289 s->value = offset;
20290 s->name = names;
20291 s->udata.p = NULL;
20292 len = strlen ((*p->sym_ptr_ptr)->name);
20293 memcpy (names, (*p->sym_ptr_ptr)->name, len);
20294 names += len;
20295 if (p->addend != 0)
20296 {
20297 char buf[30], *a;
20298
20299 memcpy (names, "+0x", sizeof ("+0x") - 1);
20300 names += sizeof ("+0x") - 1;
20301 bfd_sprintf_vma (abfd, buf, p->addend);
20302 for (a = buf; *a == '0'; ++a)
20303 ;
20304 len = strlen (a);
20305 memcpy (names, a, len);
20306 names += len;
20307 }
20308 memcpy (names, "@plt", sizeof ("@plt"));
20309 names += sizeof ("@plt");
20310 ++s, ++n;
20311 offset += plt_size;
20312 }
20313
20314 return n;
20315}
20316
ac4c9b04
MG		 20317static bfd_boolean
20318elf32_arm_section_flags (flagword *flags, const Elf_Internal_Shdr * hdr)
20319{
f0728ee3
AV		 20320 if (hdr->sh_flags & SHF_ARM_PURECODE)
20321 *flags |= SEC_ELF_PURECODE;
ac4c9b04
MG		 20322 return TRUE;
20323}
20324
20325static flagword
20326elf32_arm_lookup_section_flags (char *flag_name)
20327{
f0728ee3
AV		 20328 if (!strcmp (flag_name, "SHF_ARM_PURECODE"))
20329 return SHF_ARM_PURECODE;
ac4c9b04
MG		 20330
20331 return SEC_NO_FLAGS;
20332}
20333
491d01d3
YU		 20334static unsigned int
20335elf32_arm_count_additional_relocs (asection *sec)
20336{
20337 struct _arm_elf_section_data *arm_data;
20338 arm_data = get_arm_elf_section_data (sec);
5025eb7c 20339
6342be70 20340 return arm_data == NULL ? 0 : arm_data->additional_reloc_count;
491d01d3
YU		 20341}
20342
5522f910 20343/* Called to set the sh_flags, sh_link and sh_info fields of OSECTION which
9eaff861 20344 has a type >= SHT_LOOS. Returns TRUE if these fields were initialised
5522f910
NC		 20345 FALSE otherwise. ISECTION is the best guess matching section from the
20346 input bfd IBFD, but it might be NULL. */
20347
20348static bfd_boolean
20349elf32_arm_copy_special_section_fields (const bfd *ibfd ATTRIBUTE_UNUSED,
20350 bfd *obfd ATTRIBUTE_UNUSED,
20351 const Elf_Internal_Shdr *isection ATTRIBUTE_UNUSED,
20352 Elf_Internal_Shdr *osection)
20353{
20354 switch (osection->sh_type)
20355 {
20356 case SHT_ARM_EXIDX:
20357 {
20358 Elf_Internal_Shdr **oheaders = elf_elfsections (obfd);
20359 Elf_Internal_Shdr **iheaders = elf_elfsections (ibfd);
20360 unsigned i = 0;
20361
20362 osection->sh_flags = SHF_ALLOC | SHF_LINK_ORDER;
20363 osection->sh_info = 0;
20364
20365 /* The sh_link field must be set to the text section associated with
20366 this index section. Unfortunately the ARM EHABI does not specify
20367 exactly how to determine this association. Our caller does try
20368 to match up OSECTION with its corresponding input section however
20369 so that is a good first guess. */
20370 if (isection != NULL
20371 && osection->bfd_section != NULL
20372 && isection->bfd_section != NULL
20373 && isection->bfd_section->output_section != NULL
20374 && isection->bfd_section->output_section == osection->bfd_section
20375 && iheaders != NULL
20376 && isection->sh_link > 0
20377 && isection->sh_link < elf_numsections (ibfd)
20378 && iheaders[isection->sh_link]->bfd_section != NULL
20379 && iheaders[isection->sh_link]->bfd_section->output_section != NULL
20380 )
20381 {
20382 for (i = elf_numsections (obfd); i-- > 0;)
20383 if (oheaders[i]->bfd_section
20384 == iheaders[isection->sh_link]->bfd_section->output_section)
20385 break;
20386 }
9eaff861 20387
5522f910
NC		 20388 if (i == 0)
20389 {
20390 /* Failing that we have to find a matching section ourselves. If
20391 we had the output section name available we could compare that
20392 with input section names. Unfortunately we don't. So instead
20393 we use a simple heuristic and look for the nearest executable
20394 section before this one. */
20395 for (i = elf_numsections (obfd); i-- > 0;)
20396 if (oheaders[i] == osection)
20397 break;
20398 if (i == 0)
20399 break;
20400
20401 while (i-- > 0)
20402 if (oheaders[i]->sh_type == SHT_PROGBITS
20403 && (oheaders[i]->sh_flags & (SHF_ALLOC | SHF_EXECINSTR))
20404 == (SHF_ALLOC | SHF_EXECINSTR))
20405 break;
20406 }
20407
20408 if (i)
20409 {
20410 osection->sh_link = i;
20411 /* If the text section was part of a group
20412 then the index section should be too. */
20413 if (oheaders[i]->sh_flags & SHF_GROUP)
20414 osection->sh_flags |= SHF_GROUP;
20415 return TRUE;
20416 }
20417 }
20418 break;
20419
20420 case SHT_ARM_PREEMPTMAP:
20421 osection->sh_flags = SHF_ALLOC;
20422 break;
20423
20424 case SHT_ARM_ATTRIBUTES:
20425 case SHT_ARM_DEBUGOVERLAY:
20426 case SHT_ARM_OVERLAYSECTION:
20427 default:
20428 break;
20429 }
20430
20431 return FALSE;
20432}
20433
d691934d
NC		 20434/* Returns TRUE if NAME is an ARM mapping symbol.
20435 Traditionally the symbols $a, $d and $t have been used.
20436 The ARM ELF standard also defines $x (for A64 code). It also allows a
20437 period initiated suffix to be added to the symbol: "$[adtx]\.[:sym_char]+".
20438 Other tools might also produce $b (Thumb BL), $f, $p, $m and $v, but we do
20439 not support them here. $t.x indicates the start of ThumbEE instructions. */
20440
20441static bfd_boolean
20442is_arm_mapping_symbol (const char * name)
20443{
20444 return name != NULL /* Paranoia. */
20445 && name[0] == '$' /* Note: if objcopy --prefix-symbols has been used then
20446 the mapping symbols could have acquired a prefix.
20447 We do not support this here, since such symbols no
20448 longer conform to the ARM ELF ABI. */
20449 && (name[1] == 'a' || name[1] == 'd' || name[1] == 't' || name[1] == 'x')
20450 && (name[2] == 0 || name[2] == '.');
20451 /* FIXME: Strictly speaking the symbol is only a valid mapping symbol if
20452 any characters that follow the period are legal characters for the body
20453 of a symbol's name. For now we just assume that this is the case. */
20454}
20455
fca2a38f
NC		 20456/* Make sure that mapping symbols in object files are not removed via the
20457 "strip --strip-unneeded" tool. These symbols are needed in order to
20458 correctly generate interworking veneers, and for byte swapping code
20459 regions. Once an object file has been linked, it is safe to remove the
20460 symbols as they will no longer be needed. */
20461
20462static void
20463elf32_arm_backend_symbol_processing (bfd *abfd, asymbol *sym)
20464{
20465 if (((abfd->flags & (EXEC_P | DYNAMIC)) == 0)
fca2a38f 20466 && sym->section != bfd_abs_section_ptr
d691934d 20467 && is_arm_mapping_symbol (sym->name))
fca2a38f
NC		 20468 sym->flags |= BSF_KEEP;
20469}
20470
5522f910
NC		 20471#undef elf_backend_copy_special_section_fields
20472#define elf_backend_copy_special_section_fields elf32_arm_copy_special_section_fields
20473
252b5132 20474#define ELF_ARCH bfd_arch_arm
ae95ffa6 20475#define ELF_TARGET_ID ARM_ELF_DATA
252b5132 20476#define ELF_MACHINE_CODE EM_ARM
d0facd1b
NC		 20477#ifdef __QNXTARGET__
20478#define ELF_MAXPAGESIZE 0x1000
20479#else
7572ca89 20480#define ELF_MAXPAGESIZE 0x10000
d0facd1b 20481#endif
b1342370 20482#define ELF_MINPAGESIZE 0x1000
24718e3b 20483#define ELF_COMMONPAGESIZE 0x1000
252b5132 20484
07d6d2b8 20485#define bfd_elf32_mkobject elf32_arm_mkobject
ba93b8ac 20486
99e4ae17
AJ		 20487#define bfd_elf32_bfd_copy_private_bfd_data elf32_arm_copy_private_bfd_data
20488#define bfd_elf32_bfd_merge_private_bfd_data elf32_arm_merge_private_bfd_data
252b5132
RH		 20489#define bfd_elf32_bfd_set_private_flags elf32_arm_set_private_flags
20490#define bfd_elf32_bfd_print_private_bfd_data elf32_arm_print_private_bfd_data
07d6d2b8 20491#define bfd_elf32_bfd_link_hash_table_create elf32_arm_link_hash_table_create
dc810e39 20492#define bfd_elf32_bfd_reloc_type_lookup elf32_arm_reloc_type_lookup
b38cadfb 20493#define bfd_elf32_bfd_reloc_name_lookup elf32_arm_reloc_name_lookup
07d6d2b8
AM		 20494#define bfd_elf32_find_nearest_line elf32_arm_find_nearest_line
20495#define bfd_elf32_find_inliner_info elf32_arm_find_inliner_info
e489d0ae 20496#define bfd_elf32_new_section_hook elf32_arm_new_section_hook
3c9458e9 20497#define bfd_elf32_bfd_is_target_special_symbol elf32_arm_is_target_special_symbol
3e6b1042 20498#define bfd_elf32_bfd_final_link elf32_arm_final_link
07d6d2b8 20499#define bfd_elf32_get_synthetic_symtab elf32_arm_get_synthetic_symtab
252b5132 20500
07d6d2b8
AM		 20501#define elf_backend_get_symbol_type elf32_arm_get_symbol_type
20502#define elf_backend_gc_mark_hook elf32_arm_gc_mark_hook
6a5bb875 20503#define elf_backend_gc_mark_extra_sections elf32_arm_gc_mark_extra_sections
07d6d2b8 20504#define elf_backend_check_relocs elf32_arm_check_relocs
9eaff861 20505#define elf_backend_update_relocs elf32_arm_update_relocs
dc810e39 20506#define elf_backend_relocate_section elf32_arm_relocate_section
e489d0ae 20507#define elf_backend_write_section elf32_arm_write_section
252b5132 20508#define elf_backend_adjust_dynamic_symbol elf32_arm_adjust_dynamic_symbol
07d6d2b8 20509#define elf_backend_create_dynamic_sections elf32_arm_create_dynamic_sections
252b5132
RH		 20510#define elf_backend_finish_dynamic_symbol elf32_arm_finish_dynamic_symbol
20511#define elf_backend_finish_dynamic_sections elf32_arm_finish_dynamic_sections
20512#define elf_backend_size_dynamic_sections elf32_arm_size_dynamic_sections
0855e32b 20513#define elf_backend_always_size_sections elf32_arm_always_size_sections
74541ad4 20514#define elf_backend_init_index_section _bfd_elf_init_2_index_sections
ba96a88f 20515#define elf_backend_post_process_headers elf32_arm_post_process_headers
99e4ae17 20516#define elf_backend_reloc_type_class elf32_arm_reloc_type_class
c178919b 20517#define elf_backend_object_p elf32_arm_object_p
07d6d2b8
AM		 20518#define elf_backend_fake_sections elf32_arm_fake_sections
20519#define elf_backend_section_from_shdr elf32_arm_section_from_shdr
20520#define elf_backend_final_write_processing elf32_arm_final_write_processing
20521#define elf_backend_copy_indirect_symbol elf32_arm_copy_indirect_symbol
0beaef2b 20522#define elf_backend_size_info elf32_arm_size_info
b294bdf8 20523#define elf_backend_modify_segment_map elf32_arm_modify_segment_map
07d6d2b8
AM		 20524#define elf_backend_additional_program_headers elf32_arm_additional_program_headers
20525#define elf_backend_output_arch_local_syms elf32_arm_output_arch_local_syms
54ddd295 20526#define elf_backend_filter_implib_symbols elf32_arm_filter_implib_symbols
07d6d2b8 20527#define elf_backend_begin_write_processing elf32_arm_begin_write_processing
34e77a92 20528#define elf_backend_add_symbol_hook elf32_arm_add_symbol_hook
491d01d3 20529#define elf_backend_count_additional_relocs elf32_arm_count_additional_relocs
fca2a38f 20530#define elf_backend_symbol_processing elf32_arm_backend_symbol_processing
906e58ca
NC		 20531
20532#define elf_backend_can_refcount 1
20533#define elf_backend_can_gc_sections 1
20534#define elf_backend_plt_readonly 1
20535#define elf_backend_want_got_plt 1
20536#define elf_backend_want_plt_sym 0
5474d94f 20537#define elf_backend_want_dynrelro 1
906e58ca
NC		 20538#define elf_backend_may_use_rel_p 1
20539#define elf_backend_may_use_rela_p 0
4e7fd91e 20540#define elf_backend_default_use_rela_p 0
64f52338 20541#define elf_backend_dtrel_excludes_plt 1
252b5132 20542
04f7c78d 20543#define elf_backend_got_header_size 12
b68a20d6 20544#define elf_backend_extern_protected_data 1
04f7c78d 20545
07d6d2b8 20546#undef elf_backend_obj_attrs_vendor
906e58ca 20547#define elf_backend_obj_attrs_vendor "aeabi"
07d6d2b8 20548#undef elf_backend_obj_attrs_section
906e58ca 20549#define elf_backend_obj_attrs_section ".ARM.attributes"
07d6d2b8 20550#undef elf_backend_obj_attrs_arg_type
906e58ca 20551#define elf_backend_obj_attrs_arg_type elf32_arm_obj_attrs_arg_type
07d6d2b8 20552#undef elf_backend_obj_attrs_section_type
104d59d1 20553#define elf_backend_obj_attrs_section_type SHT_ARM_ATTRIBUTES
b38cadfb 20554#define elf_backend_obj_attrs_order elf32_arm_obj_attrs_order
07d6d2b8 20555#define elf_backend_obj_attrs_handle_unknown elf32_arm_obj_attrs_handle_unknown
104d59d1 20556
07d6d2b8 20557#undef elf_backend_section_flags
ac4c9b04 20558#define elf_backend_section_flags elf32_arm_section_flags
07d6d2b8
AM		 20559#undef elf_backend_lookup_section_flags_hook
20560#define elf_backend_lookup_section_flags_hook elf32_arm_lookup_section_flags
ac4c9b04 20561
a2f63b2e
MR		 20562#define elf_backend_linux_prpsinfo32_ugid16 TRUE
20563
252b5132 20564#include "elf32-target.h"
7f266840 20565
b38cadfb
NC		 20566/* Native Client targets. */
20567
20568#undef TARGET_LITTLE_SYM
6d00b590 20569#define TARGET_LITTLE_SYM arm_elf32_nacl_le_vec
b38cadfb
NC		 20570#undef TARGET_LITTLE_NAME
20571#define TARGET_LITTLE_NAME "elf32-littlearm-nacl"
20572#undef TARGET_BIG_SYM
6d00b590 20573#define TARGET_BIG_SYM arm_elf32_nacl_be_vec
b38cadfb
NC		 20574#undef TARGET_BIG_NAME
20575#define TARGET_BIG_NAME "elf32-bigarm-nacl"
20576
20577/* Like elf32_arm_link_hash_table_create -- but overrides
20578 appropriately for NaCl. */
20579
20580static struct bfd_link_hash_table *
20581elf32_arm_nacl_link_hash_table_create (bfd *abfd)
20582{
20583 struct bfd_link_hash_table *ret;
20584
20585 ret = elf32_arm_link_hash_table_create (abfd);
20586 if (ret)
20587 {
20588 struct elf32_arm_link_hash_table *htab
20589 = (struct elf32_arm_link_hash_table *) ret;
20590
20591 htab->nacl_p = 1;
20592
20593 htab->plt_header_size = 4 * ARRAY_SIZE (elf32_arm_nacl_plt0_entry);
20594 htab->plt_entry_size = 4 * ARRAY_SIZE (elf32_arm_nacl_plt_entry);
20595 }
20596 return ret;
20597}
20598
20599/* Since NaCl doesn't use the ARM-specific unwind format, we don't
20600 really need to use elf32_arm_modify_segment_map. But we do it
20601 anyway just to reduce gratuitous differences with the stock ARM backend. */
20602
20603static bfd_boolean
20604elf32_arm_nacl_modify_segment_map (bfd *abfd, struct bfd_link_info *info)
20605{
20606 return (elf32_arm_modify_segment_map (abfd, info)
20607 && nacl_modify_segment_map (abfd, info));
20608}
20609
cc364be6
AM		 20610static bfd_boolean
20611elf32_arm_nacl_final_write_processing (bfd *abfd)
887badb3 20612{
cc364be6
AM		 20613 arm_final_write_processing (abfd);
20614 return nacl_final_write_processing (abfd);
887badb3
RM		 20615}
20616
6a631e86
YG		 20617static bfd_vma
20618elf32_arm_nacl_plt_sym_val (bfd_vma i, const asection *plt,
20619 const arelent *rel ATTRIBUTE_UNUSED)
20620{
20621 return plt->vma
20622 + 4 * (ARRAY_SIZE (elf32_arm_nacl_plt0_entry) +
20623 i * ARRAY_SIZE (elf32_arm_nacl_plt_entry));
20624}
887badb3 20625
b38cadfb 20626#undef elf32_bed
6a631e86 20627#define elf32_bed elf32_arm_nacl_bed
b38cadfb
NC		 20628#undef bfd_elf32_bfd_link_hash_table_create
20629#define bfd_elf32_bfd_link_hash_table_create \
20630 elf32_arm_nacl_link_hash_table_create
20631#undef elf_backend_plt_alignment
6a631e86 20632#define elf_backend_plt_alignment 4
b38cadfb
NC		 20633#undef elf_backend_modify_segment_map
20634#define elf_backend_modify_segment_map elf32_arm_nacl_modify_segment_map
20635#undef elf_backend_modify_program_headers
20636#define elf_backend_modify_program_headers nacl_modify_program_headers
887badb3
RM		 20637#undef elf_backend_final_write_processing
20638#define elf_backend_final_write_processing elf32_arm_nacl_final_write_processing
6a631e86
YG		 20639#undef bfd_elf32_get_synthetic_symtab
20640#undef elf_backend_plt_sym_val
20641#define elf_backend_plt_sym_val elf32_arm_nacl_plt_sym_val
5522f910 20642#undef elf_backend_copy_special_section_fields
b38cadfb 20643
887badb3
RM		 20644#undef ELF_MINPAGESIZE
20645#undef ELF_COMMONPAGESIZE
20646
b38cadfb
NC		 20647
20648#include "elf32-target.h"
20649
20650/* Reset to defaults. */
20651#undef elf_backend_plt_alignment
20652#undef elf_backend_modify_segment_map
20653#define elf_backend_modify_segment_map elf32_arm_modify_segment_map
20654#undef elf_backend_modify_program_headers
887badb3
RM		 20655#undef elf_backend_final_write_processing
20656#define elf_backend_final_write_processing elf32_arm_final_write_processing
20657#undef ELF_MINPAGESIZE
20658#define ELF_MINPAGESIZE 0x1000
20659#undef ELF_COMMONPAGESIZE
20660#define ELF_COMMONPAGESIZE 0x1000
20661
b38cadfb 20662
617a5ada
CL		 20663/* FDPIC Targets. */
20664
20665#undef TARGET_LITTLE_SYM
20666#define TARGET_LITTLE_SYM arm_elf32_fdpic_le_vec
20667#undef TARGET_LITTLE_NAME
20668#define TARGET_LITTLE_NAME "elf32-littlearm-fdpic"
20669#undef TARGET_BIG_SYM
20670#define TARGET_BIG_SYM arm_elf32_fdpic_be_vec
20671#undef TARGET_BIG_NAME
20672#define TARGET_BIG_NAME "elf32-bigarm-fdpic"
20673#undef elf_match_priority
20674#define elf_match_priority 128
18a20338
CL		 20675#undef ELF_OSABI
20676#define ELF_OSABI ELFOSABI_ARM_FDPIC
617a5ada
CL		 20677
20678/* Like elf32_arm_link_hash_table_create -- but overrides
20679 appropriately for FDPIC. */
20680
20681static struct bfd_link_hash_table *
20682elf32_arm_fdpic_link_hash_table_create (bfd *abfd)
20683{
20684 struct bfd_link_hash_table *ret;
20685
20686 ret = elf32_arm_link_hash_table_create (abfd);
20687 if (ret)
20688 {
20689 struct elf32_arm_link_hash_table *htab = (struct elf32_arm_link_hash_table *) ret;
20690
20691 htab->fdpic_p = 1;
20692 }
20693 return ret;
20694}
20695
e8b09b87
CL		 20696/* We need dynamic symbols for every section, since segments can
20697 relocate independently. */
20698static bfd_boolean
20699elf32_arm_fdpic_omit_section_dynsym (bfd *output_bfd ATTRIBUTE_UNUSED,
20700 struct bfd_link_info *info
20701 ATTRIBUTE_UNUSED,
20702 asection *p ATTRIBUTE_UNUSED)
20703{
20704 switch (elf_section_data (p)->this_hdr.sh_type)
20705 {
20706 case SHT_PROGBITS:
20707 case SHT_NOBITS:
20708 /* If sh_type is yet undecided, assume it could be
20709 SHT_PROGBITS/SHT_NOBITS. */
20710 case SHT_NULL:
20711 return FALSE;
20712
20713 /* There shouldn't be section relative relocations
20714 against any other section. */
20715 default:
20716 return TRUE;
20717 }
20718}
20719
617a5ada
CL		 20720#undef elf32_bed
20721#define elf32_bed elf32_arm_fdpic_bed
20722
20723#undef bfd_elf32_bfd_link_hash_table_create
4b24dd1a 20724#define bfd_elf32_bfd_link_hash_table_create elf32_arm_fdpic_link_hash_table_create
617a5ada 20725
e8b09b87
CL		 20726#undef elf_backend_omit_section_dynsym
20727#define elf_backend_omit_section_dynsym elf32_arm_fdpic_omit_section_dynsym
20728
617a5ada 20729#include "elf32-target.h"
e8b09b87 20730
617a5ada 20731#undef elf_match_priority
18a20338 20732#undef ELF_OSABI
e8b09b87 20733#undef elf_backend_omit_section_dynsym
617a5ada 20734
906e58ca 20735/* VxWorks Targets. */
4e7fd91e 20736
07d6d2b8
AM		 20737#undef TARGET_LITTLE_SYM
20738#define TARGET_LITTLE_SYM arm_elf32_vxworks_le_vec
20739#undef TARGET_LITTLE_NAME
20740#define TARGET_LITTLE_NAME "elf32-littlearm-vxworks"
20741#undef TARGET_BIG_SYM
20742#define TARGET_BIG_SYM arm_elf32_vxworks_be_vec
20743#undef TARGET_BIG_NAME
20744#define TARGET_BIG_NAME "elf32-bigarm-vxworks"
4e7fd91e
PB		 20745
20746/* Like elf32_arm_link_hash_table_create -- but overrides
20747 appropriately for VxWorks. */
906e58ca 20748
4e7fd91e
PB		 20749static struct bfd_link_hash_table *
20750elf32_arm_vxworks_link_hash_table_create (bfd *abfd)
20751{
20752 struct bfd_link_hash_table *ret;
20753
20754 ret = elf32_arm_link_hash_table_create (abfd);
20755 if (ret)
20756 {
20757 struct elf32_arm_link_hash_table *htab
00a97672 20758 = (struct elf32_arm_link_hash_table *) ret;
4e7fd91e 20759 htab->use_rel = 0;
00a97672 20760 htab->vxworks_p = 1;
4e7fd91e
PB		 20761 }
20762 return ret;
906e58ca 20763}
4e7fd91e 20764
cc364be6
AM		 20765static bfd_boolean
20766elf32_arm_vxworks_final_write_processing (bfd *abfd)
00a97672 20767{
cc364be6
AM		 20768 arm_final_write_processing (abfd);
20769 return elf_vxworks_final_write_processing (abfd);
00a97672
RS		 20770}
20771
906e58ca 20772#undef elf32_bed
4e7fd91e
PB		 20773#define elf32_bed elf32_arm_vxworks_bed
20774
906e58ca
NC		 20775#undef bfd_elf32_bfd_link_hash_table_create
20776#define bfd_elf32_bfd_link_hash_table_create elf32_arm_vxworks_link_hash_table_create
906e58ca
NC		 20777#undef elf_backend_final_write_processing
20778#define elf_backend_final_write_processing elf32_arm_vxworks_final_write_processing
20779#undef elf_backend_emit_relocs
9eaff861 20780#define elf_backend_emit_relocs elf_vxworks_emit_relocs
4e7fd91e 20781
906e58ca 20782#undef elf_backend_may_use_rel_p
00a97672 20783#define elf_backend_may_use_rel_p 0
906e58ca 20784#undef elf_backend_may_use_rela_p
00a97672 20785#define elf_backend_may_use_rela_p 1
906e58ca 20786#undef elf_backend_default_use_rela_p
00a97672 20787#define elf_backend_default_use_rela_p 1
906e58ca 20788#undef elf_backend_want_plt_sym
00a97672 20789#define elf_backend_want_plt_sym 1
906e58ca 20790#undef ELF_MAXPAGESIZE
00a97672 20791#define ELF_MAXPAGESIZE 0x1000
4e7fd91e
PB		 20792
20793#include "elf32-target.h"
20794
20795
21d799b5
NC		 20796/* Merge backend specific data from an object file to the output
20797 object file when linking. */
20798
20799static bfd_boolean
50e03d47 20800elf32_arm_merge_private_bfd_data (bfd *ibfd, struct bfd_link_info *info)
21d799b5 20801{
50e03d47 20802 bfd *obfd = info->output_bfd;
21d799b5
NC		 20803 flagword out_flags;
20804 flagword in_flags;
20805 bfd_boolean flags_compatible = TRUE;
20806 asection *sec;
20807
cc643b88 20808 /* Check if we have the same endianness. */
50e03d47 20809 if (! _bfd_generic_verify_endian_match (ibfd, info))
21d799b5
NC		 20810 return FALSE;
20811
20812 if (! is_arm_elf (ibfd) || ! is_arm_elf (obfd))
20813 return TRUE;
20814
50e03d47 20815 if (!elf32_arm_merge_eabi_attributes (ibfd, info))
21d799b5
NC		 20816 return FALSE;
20817
20818 /* The input BFD must have had its flags initialised. */
20819 /* The following seems bogus to me -- The flags are initialized in
20820 the assembler but I don't think an elf_flags_init field is
20821 written into the object. */
20822 /* BFD_ASSERT (elf_flags_init (ibfd)); */
20823
20824 in_flags = elf_elfheader (ibfd)->e_flags;
20825 out_flags = elf_elfheader (obfd)->e_flags;
20826
20827 /* In theory there is no reason why we couldn't handle this. However
20828 in practice it isn't even close to working and there is no real
20829 reason to want it. */
20830 if (EF_ARM_EABI_VERSION (in_flags) >= EF_ARM_EABI_VER4
20831 && !(ibfd->flags & DYNAMIC)
20832 && (in_flags & EF_ARM_BE8))
20833 {
871b3ab2 20834 _bfd_error_handler (_("error: %pB is already in final BE8 format"),
21d799b5
NC		 20835 ibfd);
20836 return FALSE;
20837 }
20838
20839 if (!elf_flags_init (obfd))
20840 {
20841 /* If the input is the default architecture and had the default
20842 flags then do not bother setting the flags for the output
20843 architecture, instead allow future merges to do this. If no
20844 future merges ever set these flags then they will retain their
99059e56
RM		 20845 uninitialised values, which surprise surprise, correspond
20846 to the default values. */
21d799b5
NC		 20847 if (bfd_get_arch_info (ibfd)->the_default
20848 && elf_elfheader (ibfd)->e_flags == 0)
20849 return TRUE;
20850
20851 elf_flags_init (obfd) = TRUE;
20852 elf_elfheader (obfd)->e_flags = in_flags;
20853
20854 if (bfd_get_arch (obfd) == bfd_get_arch (ibfd)
20855 && bfd_get_arch_info (obfd)->the_default)
20856 return bfd_set_arch_mach (obfd, bfd_get_arch (ibfd), bfd_get_mach (ibfd));
20857
20858 return TRUE;
20859 }
20860
20861 /* Determine what should happen if the input ARM architecture
20862 does not match the output ARM architecture. */
20863 if (! bfd_arm_merge_machines (ibfd, obfd))
20864 return FALSE;
20865
20866 /* Identical flags must be compatible. */
20867 if (in_flags == out_flags)
20868 return TRUE;
20869
20870 /* Check to see if the input BFD actually contains any sections. If
20871 not, its flags may not have been initialised either, but it
20872 cannot actually cause any incompatiblity. Do not short-circuit
20873 dynamic objects; their section list may be emptied by
20874 elf_link_add_object_symbols.
20875
20876 Also check to see if there are no code sections in the input.
20877 In this case there is no need to check for code specific flags.
20878 XXX - do we need to worry about floating-point format compatability
20879 in data sections ? */
20880 if (!(ibfd->flags & DYNAMIC))
20881 {
20882 bfd_boolean null_input_bfd = TRUE;
20883 bfd_boolean only_data_sections = TRUE;
20884
20885 for (sec = ibfd->sections; sec != NULL; sec = sec->next)
20886 {
20887 /* Ignore synthetic glue sections. */
20888 if (strcmp (sec->name, ".glue_7")
20889 && strcmp (sec->name, ".glue_7t"))
20890 {
20891 if ((bfd_get_section_flags (ibfd, sec)
20892 & (SEC_LOAD | SEC_CODE | SEC_HAS_CONTENTS))
20893 == (SEC_LOAD | SEC_CODE | SEC_HAS_CONTENTS))
99059e56 20894 only_data_sections = FALSE;
21d799b5
NC		 20895
20896 null_input_bfd = FALSE;
20897 break;
20898 }
20899 }
20900
20901 if (null_input_bfd || only_data_sections)
20902 return TRUE;
20903 }
20904
20905 /* Complain about various flag mismatches. */
20906 if (!elf32_arm_versions_compatible (EF_ARM_EABI_VERSION (in_flags),
20907 EF_ARM_EABI_VERSION (out_flags)))
20908 {
20909 _bfd_error_handler
90b6238f 20910 (_("error: source object %pB has EABI version %d, but target %pB has EABI version %d"),
c08bb8dd
AM		 20911 ibfd, (in_flags & EF_ARM_EABIMASK) >> 24,
20912 obfd, (out_flags & EF_ARM_EABIMASK) >> 24);
21d799b5
NC		 20913 return FALSE;
20914 }
20915
20916 /* Not sure what needs to be checked for EABI versions >= 1. */
20917 /* VxWorks libraries do not use these flags. */
20918 if (get_elf_backend_data (obfd) != &elf32_arm_vxworks_bed
20919 && get_elf_backend_data (ibfd) != &elf32_arm_vxworks_bed
20920 && EF_ARM_EABI_VERSION (in_flags) == EF_ARM_EABI_UNKNOWN)
20921 {
20922 if ((in_flags & EF_ARM_APCS_26) != (out_flags & EF_ARM_APCS_26))
20923 {
20924 _bfd_error_handler
871b3ab2 20925 (_("error: %pB is compiled for APCS-%d, whereas target %pB uses APCS-%d"),
c08bb8dd
AM		 20926 ibfd, in_flags & EF_ARM_APCS_26 ? 26 : 32,
20927 obfd, out_flags & EF_ARM_APCS_26 ? 26 : 32);
21d799b5
NC		 20928 flags_compatible = FALSE;
20929 }
20930
20931 if ((in_flags & EF_ARM_APCS_FLOAT) != (out_flags & EF_ARM_APCS_FLOAT))
20932 {
20933 if (in_flags & EF_ARM_APCS_FLOAT)
20934 _bfd_error_handler
871b3ab2 20935 (_("error: %pB passes floats in float registers, whereas %pB passes them in integer registers"),
21d799b5
NC		 20936 ibfd, obfd);
20937 else
20938 _bfd_error_handler
871b3ab2 20939 (_("error: %pB passes floats in integer registers, whereas %pB passes them in float registers"),
21d799b5
NC		 20940 ibfd, obfd);
20941
20942 flags_compatible = FALSE;
20943 }
20944
20945 if ((in_flags & EF_ARM_VFP_FLOAT) != (out_flags & EF_ARM_VFP_FLOAT))
20946 {
20947 if (in_flags & EF_ARM_VFP_FLOAT)
20948 _bfd_error_handler
90b6238f
AM		 20949 (_("error: %pB uses %s instructions, whereas %pB does not"),
20950 ibfd, "VFP", obfd);
21d799b5
NC		 20951 else
20952 _bfd_error_handler
90b6238f
AM		 20953 (_("error: %pB uses %s instructions, whereas %pB does not"),
20954 ibfd, "FPA", obfd);
21d799b5
NC		 20955
20956 flags_compatible = FALSE;
20957 }
20958
20959 if ((in_flags & EF_ARM_MAVERICK_FLOAT) != (out_flags & EF_ARM_MAVERICK_FLOAT))
20960 {
20961 if (in_flags & EF_ARM_MAVERICK_FLOAT)
20962 _bfd_error_handler
90b6238f
AM		 20963 (_("error: %pB uses %s instructions, whereas %pB does not"),
20964 ibfd, "Maverick", obfd);
21d799b5
NC		 20965 else
20966 _bfd_error_handler
90b6238f
AM		 20967 (_("error: %pB does not use %s instructions, whereas %pB does"),
20968 ibfd, "Maverick", obfd);
21d799b5
NC		 20969
20970 flags_compatible = FALSE;
20971 }
20972
20973#ifdef EF_ARM_SOFT_FLOAT
20974 if ((in_flags & EF_ARM_SOFT_FLOAT) != (out_flags & EF_ARM_SOFT_FLOAT))
20975 {
20976 /* We can allow interworking between code that is VFP format
20977 layout, and uses either soft float or integer regs for
20978 passing floating point arguments and results. We already
20979 know that the APCS_FLOAT flags match; similarly for VFP
20980 flags. */
20981 if ((in_flags & EF_ARM_APCS_FLOAT) != 0
20982 || (in_flags & EF_ARM_VFP_FLOAT) == 0)
20983 {
20984 if (in_flags & EF_ARM_SOFT_FLOAT)
20985 _bfd_error_handler
871b3ab2 20986 (_("error: %pB uses software FP, whereas %pB uses hardware FP"),
21d799b5
NC		 20987 ibfd, obfd);
20988 else
20989 _bfd_error_handler
871b3ab2 20990 (_("error: %pB uses hardware FP, whereas %pB uses software FP"),
21d799b5
NC		 20991 ibfd, obfd);
20992
20993 flags_compatible = FALSE;
20994 }
20995 }
20996#endif
20997
20998 /* Interworking mismatch is only a warning. */
20999 if ((in_flags & EF_ARM_INTERWORK) != (out_flags & EF_ARM_INTERWORK))
21000 {
21001 if (in_flags & EF_ARM_INTERWORK)
21002 {
21003 _bfd_error_handler
90b6238f 21004 (_("warning: %pB supports interworking, whereas %pB does not"),
21d799b5
NC		 21005 ibfd, obfd);
21006 }
21007 else
21008 {
21009 _bfd_error_handler
90b6238f 21010 (_("warning: %pB does not support interworking, whereas %pB does"),
21d799b5
NC		 21011 ibfd, obfd);
21012 }
21013 }
21014 }
21015
21016 return flags_compatible;
21017}
21018
21019
906e58ca 21020/* Symbian OS Targets. */
7f266840 21021
07d6d2b8
AM		 21022#undef TARGET_LITTLE_SYM
21023#define TARGET_LITTLE_SYM arm_elf32_symbian_le_vec
21024#undef TARGET_LITTLE_NAME
21025#define TARGET_LITTLE_NAME "elf32-littlearm-symbian"
21026#undef TARGET_BIG_SYM
21027#define TARGET_BIG_SYM arm_elf32_symbian_be_vec
21028#undef TARGET_BIG_NAME
21029#define TARGET_BIG_NAME "elf32-bigarm-symbian"
7f266840
DJ		 21030
21031/* Like elf32_arm_link_hash_table_create -- but overrides
21032 appropriately for Symbian OS. */
906e58ca 21033
7f266840
DJ		 21034static struct bfd_link_hash_table *
21035elf32_arm_symbian_link_hash_table_create (bfd *abfd)
21036{
21037 struct bfd_link_hash_table *ret;
21038
21039 ret = elf32_arm_link_hash_table_create (abfd);
21040 if (ret)
21041 {
21042 struct elf32_arm_link_hash_table *htab
21043 = (struct elf32_arm_link_hash_table *)ret;
21044 /* There is no PLT header for Symbian OS. */
21045 htab->plt_header_size = 0;
95720a86
DJ		 21046 /* The PLT entries are each one instruction and one word. */
21047 htab->plt_entry_size = 4 * ARRAY_SIZE (elf32_arm_symbian_plt_entry);
7f266840 21048 htab->symbian_p = 1;
33bfe774
JB		 21049 /* Symbian uses armv5t or above, so use_blx is always true. */
21050 htab->use_blx = 1;
67687978 21051 htab->root.is_relocatable_executable = 1;
7f266840
DJ		 21052 }
21053 return ret;
906e58ca 21054}
7f266840 21055
b35d266b 21056static const struct bfd_elf_special_section
551b43fd 21057elf32_arm_symbian_special_sections[] =
7f266840 21058{
5cd3778d
MM		 21059 /* In a BPABI executable, the dynamic linking sections do not go in
21060 the loadable read-only segment. The post-linker may wish to
21061 refer to these sections, but they are not part of the final
21062 program image. */
07d6d2b8
AM		 21063 { STRING_COMMA_LEN (".dynamic"), 0, SHT_DYNAMIC, 0 },
21064 { STRING_COMMA_LEN (".dynstr"), 0, SHT_STRTAB, 0 },
21065 { STRING_COMMA_LEN (".dynsym"), 0, SHT_DYNSYM, 0 },
21066 { STRING_COMMA_LEN (".got"), 0, SHT_PROGBITS, 0 },
21067 { STRING_COMMA_LEN (".hash"), 0, SHT_HASH, 0 },
5cd3778d
MM		 21068 /* These sections do not need to be writable as the SymbianOS
21069 postlinker will arrange things so that no dynamic relocation is
21070 required. */
07d6d2b8
AM		 21071 { STRING_COMMA_LEN (".init_array"), 0, SHT_INIT_ARRAY, SHF_ALLOC },
21072 { STRING_COMMA_LEN (".fini_array"), 0, SHT_FINI_ARRAY, SHF_ALLOC },
0112cd26 21073 { STRING_COMMA_LEN (".preinit_array"), 0, SHT_PREINIT_ARRAY, SHF_ALLOC },
07d6d2b8 21074 { NULL, 0, 0, 0, 0 }
7f266840
DJ		 21075};
21076
c3c76620 21077static void
906e58ca 21078elf32_arm_symbian_begin_write_processing (bfd *abfd,
a4fd1a8e 21079 struct bfd_link_info *link_info)
c3c76620
MM		 21080{
21081 /* BPABI objects are never loaded directly by an OS kernel; they are
21082 processed by a postlinker first, into an OS-specific format. If
21083 the D_PAGED bit is set on the file, BFD will align segments on
21084 page boundaries, so that an OS can directly map the file. With
21085 BPABI objects, that just results in wasted space. In addition,
21086 because we clear the D_PAGED bit, map_sections_to_segments will
21087 recognize that the program headers should not be mapped into any
21088 loadable segment. */
21089 abfd->flags &= ~D_PAGED;
906e58ca 21090 elf32_arm_begin_write_processing (abfd, link_info);
c3c76620 21091}
7f266840
DJ		 21092
21093static bfd_boolean
906e58ca 21094elf32_arm_symbian_modify_segment_map (bfd *abfd,
b294bdf8 21095 struct bfd_link_info *info)
7f266840
DJ		 21096{
21097 struct elf_segment_map *m;
21098 asection *dynsec;
21099
7f266840
DJ		 21100 /* BPABI shared libraries and executables should have a PT_DYNAMIC
21101 segment. However, because the .dynamic section is not marked
21102 with SEC_LOAD, the generic ELF code will not create such a
21103 segment. */
21104 dynsec = bfd_get_section_by_name (abfd, ".dynamic");
21105 if (dynsec)
21106 {
12bd6957 21107 for (m = elf_seg_map (abfd); m != NULL; m = m->next)
8ded5a0f
AM		 21108 if (m->p_type == PT_DYNAMIC)
21109 break;
21110
21111 if (m == NULL)
21112 {
21113 m = _bfd_elf_make_dynamic_segment (abfd, dynsec);
12bd6957
AM		 21114 m->next = elf_seg_map (abfd);
21115 elf_seg_map (abfd) = m;
8ded5a0f 21116 }
7f266840
DJ		 21117 }
21118
b294bdf8
MM		 21119 /* Also call the generic arm routine. */
21120 return elf32_arm_modify_segment_map (abfd, info);
7f266840
DJ		 21121}
21122
95720a86
DJ		 21123/* Return address for Ith PLT stub in section PLT, for relocation REL
21124 or (bfd_vma) -1 if it should not be included. */
21125
21126static bfd_vma
21127elf32_arm_symbian_plt_sym_val (bfd_vma i, const asection *plt,
21128 const arelent *rel ATTRIBUTE_UNUSED)
21129{
21130 return plt->vma + 4 * ARRAY_SIZE (elf32_arm_symbian_plt_entry) * i;
21131}
21132
8029a119 21133#undef elf32_bed
7f266840
DJ		 21134#define elf32_bed elf32_arm_symbian_bed
21135
21136/* The dynamic sections are not allocated on SymbianOS; the postlinker
21137 will process them and then discard them. */
906e58ca 21138#undef ELF_DYNAMIC_SEC_FLAGS
7f266840
DJ		 21139#define ELF_DYNAMIC_SEC_FLAGS \
21140 (SEC_HAS_CONTENTS | SEC_IN_MEMORY | SEC_LINKER_CREATED)
21141
9eaff861 21142#undef elf_backend_emit_relocs
c3c76620 21143
906e58ca
NC		 21144#undef bfd_elf32_bfd_link_hash_table_create
21145#define bfd_elf32_bfd_link_hash_table_create elf32_arm_symbian_link_hash_table_create
21146#undef elf_backend_special_sections
07d6d2b8 21147#define elf_backend_special_sections elf32_arm_symbian_special_sections
906e58ca
NC		 21148#undef elf_backend_begin_write_processing
21149#define elf_backend_begin_write_processing elf32_arm_symbian_begin_write_processing
21150#undef elf_backend_final_write_processing
21151#define elf_backend_final_write_processing elf32_arm_final_write_processing
21152
21153#undef elf_backend_modify_segment_map
7f266840
DJ		 21154#define elf_backend_modify_segment_map elf32_arm_symbian_modify_segment_map
21155
21156/* There is no .got section for BPABI objects, and hence no header. */
906e58ca 21157#undef elf_backend_got_header_size
7f266840
DJ		 21158#define elf_backend_got_header_size 0
21159
21160/* Similarly, there is no .got.plt section. */
906e58ca 21161#undef elf_backend_want_got_plt
7f266840
DJ		 21162#define elf_backend_want_got_plt 0
21163
906e58ca 21164#undef elf_backend_plt_sym_val
95720a86
DJ		 21165#define elf_backend_plt_sym_val elf32_arm_symbian_plt_sym_val
21166
906e58ca 21167#undef elf_backend_may_use_rel_p
00a97672 21168#define elf_backend_may_use_rel_p 1
906e58ca 21169#undef elf_backend_may_use_rela_p
00a97672 21170#define elf_backend_may_use_rela_p 0
906e58ca 21171#undef elf_backend_default_use_rela_p
00a97672 21172#define elf_backend_default_use_rela_p 0
906e58ca 21173#undef elf_backend_want_plt_sym
00a97672 21174#define elf_backend_want_plt_sym 0
64f52338
AM		 21175#undef elf_backend_dtrel_excludes_plt
21176#define elf_backend_dtrel_excludes_plt 0
906e58ca 21177#undef ELF_MAXPAGESIZE
00a97672 21178#define ELF_MAXPAGESIZE 0x8000
4e7fd91e 21179
7f266840 21180#include "elf32-target.h"
GDB Binutils - Deliverables
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