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Reduce parameter list in bfd_elf32_arm_target_relocs
[deliverable/binutils-gdb.git] / bfd / elf32-arm.c
CommitLineData
252b5132 1/* 32-bit ELF support for ARM
6f2750fe 2 Copyright (C) 1998-2016 Free Software Foundation, Inc.
252b5132
RH		 3
4 This file is part of BFD, the Binary File Descriptor library.
5
6 This program is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
cd123cb7 8 the Free Software Foundation; either version 3 of the License, or
252b5132
RH		 9 (at your option) any later version.
10
11 This program is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
15
16 You should have received a copy of the GNU General Public License
17 along with this program; if not, write to the Free Software
cd123cb7
NC		 18 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
19 MA 02110-1301, USA. */
252b5132 20
6e6718a3 21#include "sysdep.h"
2468f9c9
PB		 22#include <limits.h>
23
3db64b00 24#include "bfd.h"
6034aab8 25#include "bfd_stdint.h"
00a97672 26#include "libiberty.h"
7f266840
DJ		 27#include "libbfd.h"
28#include "elf-bfd.h"
b38cadfb 29#include "elf-nacl.h"
00a97672 30#include "elf-vxworks.h"
ee065d83 31#include "elf/arm.h"
7f266840 32
00a97672
RS		 33/* Return the relocation section associated with NAME. HTAB is the
34 bfd's elf32_arm_link_hash_entry. */
35#define RELOC_SECTION(HTAB, NAME) \
36 ((HTAB)->use_rel ? ".rel" NAME : ".rela" NAME)
37
38/* Return size of a relocation entry. HTAB is the bfd's
39 elf32_arm_link_hash_entry. */
40#define RELOC_SIZE(HTAB) \
41 ((HTAB)->use_rel \
42 ? sizeof (Elf32_External_Rel) \
43 : sizeof (Elf32_External_Rela))
44
45/* Return function to swap relocations in. HTAB is the bfd's
46 elf32_arm_link_hash_entry. */
47#define SWAP_RELOC_IN(HTAB) \
48 ((HTAB)->use_rel \
49 ? bfd_elf32_swap_reloc_in \
50 : bfd_elf32_swap_reloca_in)
51
52/* Return function to swap relocations out. HTAB is the bfd's
53 elf32_arm_link_hash_entry. */
54#define SWAP_RELOC_OUT(HTAB) \
55 ((HTAB)->use_rel \
56 ? bfd_elf32_swap_reloc_out \
57 : bfd_elf32_swap_reloca_out)
58
7f266840
DJ		 59#define elf_info_to_howto 0
60#define elf_info_to_howto_rel elf32_arm_info_to_howto
61
62#define ARM_ELF_ABI_VERSION 0
63#define ARM_ELF_OS_ABI_VERSION ELFOSABI_ARM
64
79f08007
YZ		 65/* The Adjusted Place, as defined by AAELF. */
66#define Pa(X) ((X) & 0xfffffffc)
67
3e6b1042
DJ		 68static bfd_boolean elf32_arm_write_section (bfd *output_bfd,
69 struct bfd_link_info *link_info,
70 asection *sec,
71 bfd_byte *contents);
72
7f266840
DJ		 73/* Note: code such as elf32_arm_reloc_type_lookup expect to use e.g.
74 R_ARM_PC24 as an index into this, and find the R_ARM_PC24 HOWTO
75 in that slot. */
76
c19d1205 77static reloc_howto_type elf32_arm_howto_table_1[] =
7f266840 78{
8029a119 79 /* No relocation. */
7f266840
DJ		 80 HOWTO (R_ARM_NONE, /* type */
81 0, /* rightshift */
6346d5ca 82 3, /* size (0 = byte, 1 = short, 2 = long) */
7f266840
DJ		 83 0, /* bitsize */
84 FALSE, /* pc_relative */
85 0, /* bitpos */
86 complain_overflow_dont,/* complain_on_overflow */
87 bfd_elf_generic_reloc, /* special_function */
88 "R_ARM_NONE", /* name */
89 FALSE, /* partial_inplace */
90 0, /* src_mask */
91 0, /* dst_mask */
92 FALSE), /* pcrel_offset */
93
94 HOWTO (R_ARM_PC24, /* type */
95 2, /* rightshift */
96 2, /* size (0 = byte, 1 = short, 2 = long) */
97 24, /* bitsize */
98 TRUE, /* pc_relative */
99 0, /* bitpos */
100 complain_overflow_signed,/* complain_on_overflow */
101 bfd_elf_generic_reloc, /* special_function */
102 "R_ARM_PC24", /* name */
103 FALSE, /* partial_inplace */
104 0x00ffffff, /* src_mask */
105 0x00ffffff, /* dst_mask */
106 TRUE), /* pcrel_offset */
107
108 /* 32 bit absolute */
109 HOWTO (R_ARM_ABS32, /* type */
110 0, /* rightshift */
111 2, /* size (0 = byte, 1 = short, 2 = long) */
112 32, /* bitsize */
113 FALSE, /* pc_relative */
114 0, /* bitpos */
115 complain_overflow_bitfield,/* complain_on_overflow */
116 bfd_elf_generic_reloc, /* special_function */
117 "R_ARM_ABS32", /* name */
118 FALSE, /* partial_inplace */
119 0xffffffff, /* src_mask */
120 0xffffffff, /* dst_mask */
121 FALSE), /* pcrel_offset */
122
123 /* standard 32bit pc-relative reloc */
124 HOWTO (R_ARM_REL32, /* type */
125 0, /* rightshift */
126 2, /* size (0 = byte, 1 = short, 2 = long) */
127 32, /* bitsize */
128 TRUE, /* pc_relative */
129 0, /* bitpos */
130 complain_overflow_bitfield,/* complain_on_overflow */
131 bfd_elf_generic_reloc, /* special_function */
132 "R_ARM_REL32", /* name */
133 FALSE, /* partial_inplace */
134 0xffffffff, /* src_mask */
135 0xffffffff, /* dst_mask */
136 TRUE), /* pcrel_offset */
137
c19d1205 138 /* 8 bit absolute - R_ARM_LDR_PC_G0 in AAELF */
4962c51a 139 HOWTO (R_ARM_LDR_PC_G0, /* type */
7f266840
DJ		 140 0, /* rightshift */
141 0, /* size (0 = byte, 1 = short, 2 = long) */
4962c51a
MS		 142 32, /* bitsize */
143 TRUE, /* pc_relative */
7f266840 144 0, /* bitpos */
4962c51a 145 complain_overflow_dont,/* complain_on_overflow */
7f266840 146 bfd_elf_generic_reloc, /* special_function */
4962c51a 147 "R_ARM_LDR_PC_G0", /* name */
7f266840 148 FALSE, /* partial_inplace */
4962c51a
MS		 149 0xffffffff, /* src_mask */
150 0xffffffff, /* dst_mask */
151 TRUE), /* pcrel_offset */
7f266840
DJ		 152
153 /* 16 bit absolute */
154 HOWTO (R_ARM_ABS16, /* type */
155 0, /* rightshift */
156 1, /* size (0 = byte, 1 = short, 2 = long) */
157 16, /* bitsize */
158 FALSE, /* pc_relative */
159 0, /* bitpos */
160 complain_overflow_bitfield,/* complain_on_overflow */
161 bfd_elf_generic_reloc, /* special_function */
162 "R_ARM_ABS16", /* name */
163 FALSE, /* partial_inplace */
164 0x0000ffff, /* src_mask */
165 0x0000ffff, /* dst_mask */
166 FALSE), /* pcrel_offset */
167
168 /* 12 bit absolute */
169 HOWTO (R_ARM_ABS12, /* type */
170 0, /* rightshift */
171 2, /* size (0 = byte, 1 = short, 2 = long) */
172 12, /* bitsize */
173 FALSE, /* pc_relative */
174 0, /* bitpos */
175 complain_overflow_bitfield,/* complain_on_overflow */
176 bfd_elf_generic_reloc, /* special_function */
177 "R_ARM_ABS12", /* name */
178 FALSE, /* partial_inplace */
00a97672
RS		 179 0x00000fff, /* src_mask */
180 0x00000fff, /* dst_mask */
7f266840
DJ		 181 FALSE), /* pcrel_offset */
182
183 HOWTO (R_ARM_THM_ABS5, /* type */
184 6, /* rightshift */
185 1, /* size (0 = byte, 1 = short, 2 = long) */
186 5, /* bitsize */
187 FALSE, /* pc_relative */
188 0, /* bitpos */
189 complain_overflow_bitfield,/* complain_on_overflow */
190 bfd_elf_generic_reloc, /* special_function */
191 "R_ARM_THM_ABS5", /* name */
192 FALSE, /* partial_inplace */
193 0x000007e0, /* src_mask */
194 0x000007e0, /* dst_mask */
195 FALSE), /* pcrel_offset */
196
197 /* 8 bit absolute */
198 HOWTO (R_ARM_ABS8, /* type */
199 0, /* rightshift */
200 0, /* size (0 = byte, 1 = short, 2 = long) */
201 8, /* bitsize */
202 FALSE, /* pc_relative */
203 0, /* bitpos */
204 complain_overflow_bitfield,/* complain_on_overflow */
205 bfd_elf_generic_reloc, /* special_function */
206 "R_ARM_ABS8", /* name */
207 FALSE, /* partial_inplace */
208 0x000000ff, /* src_mask */
209 0x000000ff, /* dst_mask */
210 FALSE), /* pcrel_offset */
211
212 HOWTO (R_ARM_SBREL32, /* type */
213 0, /* rightshift */
214 2, /* size (0 = byte, 1 = short, 2 = long) */
215 32, /* bitsize */
216 FALSE, /* pc_relative */
217 0, /* bitpos */
218 complain_overflow_dont,/* complain_on_overflow */
219 bfd_elf_generic_reloc, /* special_function */
220 "R_ARM_SBREL32", /* name */
221 FALSE, /* partial_inplace */
222 0xffffffff, /* src_mask */
223 0xffffffff, /* dst_mask */
224 FALSE), /* pcrel_offset */
225
c19d1205 226 HOWTO (R_ARM_THM_CALL, /* type */
7f266840
DJ		 227 1, /* rightshift */
228 2, /* size (0 = byte, 1 = short, 2 = long) */
f6ebfac0 229 24, /* bitsize */
7f266840
DJ		 230 TRUE, /* pc_relative */
231 0, /* bitpos */
232 complain_overflow_signed,/* complain_on_overflow */
233 bfd_elf_generic_reloc, /* special_function */
c19d1205 234 "R_ARM_THM_CALL", /* name */
7f266840 235 FALSE, /* partial_inplace */
7f6ab9f8
AM		 236 0x07ff2fff, /* src_mask */
237 0x07ff2fff, /* dst_mask */
7f266840
DJ		 238 TRUE), /* pcrel_offset */
239
240 HOWTO (R_ARM_THM_PC8, /* type */
241 1, /* rightshift */
242 1, /* size (0 = byte, 1 = short, 2 = long) */
243 8, /* bitsize */
244 TRUE, /* pc_relative */
245 0, /* bitpos */
246 complain_overflow_signed,/* complain_on_overflow */
247 bfd_elf_generic_reloc, /* special_function */
248 "R_ARM_THM_PC8", /* name */
249 FALSE, /* partial_inplace */
250 0x000000ff, /* src_mask */
251 0x000000ff, /* dst_mask */
252 TRUE), /* pcrel_offset */
253
c19d1205 254 HOWTO (R_ARM_BREL_ADJ, /* type */
7f266840
DJ		 255 1, /* rightshift */
256 1, /* size (0 = byte, 1 = short, 2 = long) */
c19d1205
ZW		 257 32, /* bitsize */
258 FALSE, /* pc_relative */
7f266840
DJ		 259 0, /* bitpos */
260 complain_overflow_signed,/* complain_on_overflow */
261 bfd_elf_generic_reloc, /* special_function */
c19d1205 262 "R_ARM_BREL_ADJ", /* name */
7f266840 263 FALSE, /* partial_inplace */
c19d1205
ZW		 264 0xffffffff, /* src_mask */
265 0xffffffff, /* dst_mask */
266 FALSE), /* pcrel_offset */
7f266840 267
0855e32b 268 HOWTO (R_ARM_TLS_DESC, /* type */
7f266840 269 0, /* rightshift */
0855e32b
NS		 270 2, /* size (0 = byte, 1 = short, 2 = long) */
271 32, /* bitsize */
7f266840
DJ		 272 FALSE, /* pc_relative */
273 0, /* bitpos */
0855e32b 274 complain_overflow_bitfield,/* complain_on_overflow */
7f266840 275 bfd_elf_generic_reloc, /* special_function */
0855e32b 276 "R_ARM_TLS_DESC", /* name */
7f266840 277 FALSE, /* partial_inplace */
0855e32b
NS		 278 0xffffffff, /* src_mask */
279 0xffffffff, /* dst_mask */
7f266840
DJ		 280 FALSE), /* pcrel_offset */
281
282 HOWTO (R_ARM_THM_SWI8, /* type */
283 0, /* rightshift */
284 0, /* size (0 = byte, 1 = short, 2 = long) */
285 0, /* bitsize */
286 FALSE, /* pc_relative */
287 0, /* bitpos */
288 complain_overflow_signed,/* complain_on_overflow */
289 bfd_elf_generic_reloc, /* special_function */
290 "R_ARM_SWI8", /* name */
291 FALSE, /* partial_inplace */
292 0x00000000, /* src_mask */
293 0x00000000, /* dst_mask */
294 FALSE), /* pcrel_offset */
295
296 /* BLX instruction for the ARM. */
297 HOWTO (R_ARM_XPC25, /* type */
298 2, /* rightshift */
299 2, /* size (0 = byte, 1 = short, 2 = long) */
7f6ab9f8 300 24, /* bitsize */
7f266840
DJ		 301 TRUE, /* pc_relative */
302 0, /* bitpos */
303 complain_overflow_signed,/* complain_on_overflow */
304 bfd_elf_generic_reloc, /* special_function */
305 "R_ARM_XPC25", /* name */
306 FALSE, /* partial_inplace */
307 0x00ffffff, /* src_mask */
308 0x00ffffff, /* dst_mask */
309 TRUE), /* pcrel_offset */
310
311 /* BLX instruction for the Thumb. */
312 HOWTO (R_ARM_THM_XPC22, /* type */
313 2, /* rightshift */
314 2, /* size (0 = byte, 1 = short, 2 = long) */
7f6ab9f8 315 24, /* bitsize */
7f266840
DJ		 316 TRUE, /* pc_relative */
317 0, /* bitpos */
318 complain_overflow_signed,/* complain_on_overflow */
319 bfd_elf_generic_reloc, /* special_function */
320 "R_ARM_THM_XPC22", /* name */
321 FALSE, /* partial_inplace */
7f6ab9f8
AM		 322 0x07ff2fff, /* src_mask */
323 0x07ff2fff, /* dst_mask */
7f266840
DJ		 324 TRUE), /* pcrel_offset */
325
ba93b8ac 326 /* Dynamic TLS relocations. */
7f266840 327
ba93b8ac 328 HOWTO (R_ARM_TLS_DTPMOD32, /* type */
99059e56
RM		 329 0, /* rightshift */
330 2, /* size (0 = byte, 1 = short, 2 = long) */
331 32, /* bitsize */
332 FALSE, /* pc_relative */
333 0, /* bitpos */
334 complain_overflow_bitfield,/* complain_on_overflow */
335 bfd_elf_generic_reloc, /* special_function */
336 "R_ARM_TLS_DTPMOD32", /* name */
337 TRUE, /* partial_inplace */
338 0xffffffff, /* src_mask */
339 0xffffffff, /* dst_mask */
340 FALSE), /* pcrel_offset */
7f266840 341
ba93b8ac 342 HOWTO (R_ARM_TLS_DTPOFF32, /* type */
99059e56
RM		 343 0, /* rightshift */
344 2, /* size (0 = byte, 1 = short, 2 = long) */
345 32, /* bitsize */
346 FALSE, /* pc_relative */
347 0, /* bitpos */
348 complain_overflow_bitfield,/* complain_on_overflow */
349 bfd_elf_generic_reloc, /* special_function */
350 "R_ARM_TLS_DTPOFF32", /* name */
351 TRUE, /* partial_inplace */
352 0xffffffff, /* src_mask */
353 0xffffffff, /* dst_mask */
354 FALSE), /* pcrel_offset */
7f266840 355
ba93b8ac 356 HOWTO (R_ARM_TLS_TPOFF32, /* type */
99059e56
RM		 357 0, /* rightshift */
358 2, /* size (0 = byte, 1 = short, 2 = long) */
359 32, /* bitsize */
360 FALSE, /* pc_relative */
361 0, /* bitpos */
362 complain_overflow_bitfield,/* complain_on_overflow */
363 bfd_elf_generic_reloc, /* special_function */
364 "R_ARM_TLS_TPOFF32", /* name */
365 TRUE, /* partial_inplace */
366 0xffffffff, /* src_mask */
367 0xffffffff, /* dst_mask */
368 FALSE), /* pcrel_offset */
7f266840
DJ		 369
370 /* Relocs used in ARM Linux */
371
372 HOWTO (R_ARM_COPY, /* type */
99059e56
RM		 373 0, /* rightshift */
374 2, /* size (0 = byte, 1 = short, 2 = long) */
375 32, /* bitsize */
376 FALSE, /* pc_relative */
377 0, /* bitpos */
378 complain_overflow_bitfield,/* complain_on_overflow */
379 bfd_elf_generic_reloc, /* special_function */
380 "R_ARM_COPY", /* name */
381 TRUE, /* partial_inplace */
382 0xffffffff, /* src_mask */
383 0xffffffff, /* dst_mask */
384 FALSE), /* pcrel_offset */
7f266840
DJ		 385
386 HOWTO (R_ARM_GLOB_DAT, /* type */
99059e56
RM		 387 0, /* rightshift */
388 2, /* size (0 = byte, 1 = short, 2 = long) */
389 32, /* bitsize */
390 FALSE, /* pc_relative */
391 0, /* bitpos */
392 complain_overflow_bitfield,/* complain_on_overflow */
393 bfd_elf_generic_reloc, /* special_function */
394 "R_ARM_GLOB_DAT", /* name */
395 TRUE, /* partial_inplace */
396 0xffffffff, /* src_mask */
397 0xffffffff, /* dst_mask */
398 FALSE), /* pcrel_offset */
7f266840
DJ		 399
400 HOWTO (R_ARM_JUMP_SLOT, /* type */
99059e56
RM		 401 0, /* rightshift */
402 2, /* size (0 = byte, 1 = short, 2 = long) */
403 32, /* bitsize */
404 FALSE, /* pc_relative */
405 0, /* bitpos */
406 complain_overflow_bitfield,/* complain_on_overflow */
407 bfd_elf_generic_reloc, /* special_function */
408 "R_ARM_JUMP_SLOT", /* name */
409 TRUE, /* partial_inplace */
410 0xffffffff, /* src_mask */
411 0xffffffff, /* dst_mask */
412 FALSE), /* pcrel_offset */
7f266840
DJ		 413
414 HOWTO (R_ARM_RELATIVE, /* type */
99059e56
RM		 415 0, /* rightshift */
416 2, /* size (0 = byte, 1 = short, 2 = long) */
417 32, /* bitsize */
418 FALSE, /* pc_relative */
419 0, /* bitpos */
420 complain_overflow_bitfield,/* complain_on_overflow */
421 bfd_elf_generic_reloc, /* special_function */
422 "R_ARM_RELATIVE", /* name */
423 TRUE, /* partial_inplace */
424 0xffffffff, /* src_mask */
425 0xffffffff, /* dst_mask */
426 FALSE), /* pcrel_offset */
7f266840 427
c19d1205 428 HOWTO (R_ARM_GOTOFF32, /* type */
99059e56
RM		 429 0, /* rightshift */
430 2, /* size (0 = byte, 1 = short, 2 = long) */
431 32, /* bitsize */
432 FALSE, /* pc_relative */
433 0, /* bitpos */
434 complain_overflow_bitfield,/* complain_on_overflow */
435 bfd_elf_generic_reloc, /* special_function */
436 "R_ARM_GOTOFF32", /* name */
437 TRUE, /* partial_inplace */
438 0xffffffff, /* src_mask */
439 0xffffffff, /* dst_mask */
440 FALSE), /* pcrel_offset */
7f266840
DJ		 441
442 HOWTO (R_ARM_GOTPC, /* type */
99059e56
RM		 443 0, /* rightshift */
444 2, /* size (0 = byte, 1 = short, 2 = long) */
445 32, /* bitsize */
446 TRUE, /* pc_relative */
447 0, /* bitpos */
448 complain_overflow_bitfield,/* complain_on_overflow */
449 bfd_elf_generic_reloc, /* special_function */
450 "R_ARM_GOTPC", /* name */
451 TRUE, /* partial_inplace */
452 0xffffffff, /* src_mask */
453 0xffffffff, /* dst_mask */
454 TRUE), /* pcrel_offset */
7f266840
DJ		 455
456 HOWTO (R_ARM_GOT32, /* type */
99059e56
RM		 457 0, /* rightshift */
458 2, /* size (0 = byte, 1 = short, 2 = long) */
459 32, /* bitsize */
460 FALSE, /* pc_relative */
461 0, /* bitpos */
462 complain_overflow_bitfield,/* complain_on_overflow */
463 bfd_elf_generic_reloc, /* special_function */
464 "R_ARM_GOT32", /* name */
465 TRUE, /* partial_inplace */
466 0xffffffff, /* src_mask */
467 0xffffffff, /* dst_mask */
468 FALSE), /* pcrel_offset */
7f266840
DJ		 469
470 HOWTO (R_ARM_PLT32, /* type */
99059e56
RM		 471 2, /* rightshift */
472 2, /* size (0 = byte, 1 = short, 2 = long) */
473 24, /* bitsize */
474 TRUE, /* pc_relative */
475 0, /* bitpos */
476 complain_overflow_bitfield,/* complain_on_overflow */
477 bfd_elf_generic_reloc, /* special_function */
478 "R_ARM_PLT32", /* name */
479 FALSE, /* partial_inplace */
480 0x00ffffff, /* src_mask */
481 0x00ffffff, /* dst_mask */
482 TRUE), /* pcrel_offset */
7f266840
DJ		 483
484 HOWTO (R_ARM_CALL, /* type */
485 2, /* rightshift */
486 2, /* size (0 = byte, 1 = short, 2 = long) */
487 24, /* bitsize */
488 TRUE, /* pc_relative */
489 0, /* bitpos */
490 complain_overflow_signed,/* complain_on_overflow */
491 bfd_elf_generic_reloc, /* special_function */
492 "R_ARM_CALL", /* name */
493 FALSE, /* partial_inplace */
494 0x00ffffff, /* src_mask */
495 0x00ffffff, /* dst_mask */
496 TRUE), /* pcrel_offset */
497
498 HOWTO (R_ARM_JUMP24, /* type */
499 2, /* rightshift */
500 2, /* size (0 = byte, 1 = short, 2 = long) */
501 24, /* bitsize */
502 TRUE, /* pc_relative */
503 0, /* bitpos */
504 complain_overflow_signed,/* complain_on_overflow */
505 bfd_elf_generic_reloc, /* special_function */
506 "R_ARM_JUMP24", /* name */
507 FALSE, /* partial_inplace */
508 0x00ffffff, /* src_mask */
509 0x00ffffff, /* dst_mask */
510 TRUE), /* pcrel_offset */
511
c19d1205
ZW		 512 HOWTO (R_ARM_THM_JUMP24, /* type */
513 1, /* rightshift */
514 2, /* size (0 = byte, 1 = short, 2 = long) */
515 24, /* bitsize */
516 TRUE, /* pc_relative */
7f266840 517 0, /* bitpos */
c19d1205 518 complain_overflow_signed,/* complain_on_overflow */
7f266840 519 bfd_elf_generic_reloc, /* special_function */
c19d1205 520 "R_ARM_THM_JUMP24", /* name */
7f266840 521 FALSE, /* partial_inplace */
c19d1205
ZW		 522 0x07ff2fff, /* src_mask */
523 0x07ff2fff, /* dst_mask */
524 TRUE), /* pcrel_offset */
7f266840 525
c19d1205 526 HOWTO (R_ARM_BASE_ABS, /* type */
7f266840 527 0, /* rightshift */
c19d1205
ZW		 528 2, /* size (0 = byte, 1 = short, 2 = long) */
529 32, /* bitsize */
7f266840
DJ		 530 FALSE, /* pc_relative */
531 0, /* bitpos */
532 complain_overflow_dont,/* complain_on_overflow */
533 bfd_elf_generic_reloc, /* special_function */
c19d1205 534 "R_ARM_BASE_ABS", /* name */
7f266840 535 FALSE, /* partial_inplace */
c19d1205
ZW		 536 0xffffffff, /* src_mask */
537 0xffffffff, /* dst_mask */
7f266840
DJ		 538 FALSE), /* pcrel_offset */
539
540 HOWTO (R_ARM_ALU_PCREL7_0, /* type */
541 0, /* rightshift */
542 2, /* size (0 = byte, 1 = short, 2 = long) */
543 12, /* bitsize */
544 TRUE, /* pc_relative */
545 0, /* bitpos */
546 complain_overflow_dont,/* complain_on_overflow */
547 bfd_elf_generic_reloc, /* special_function */
548 "R_ARM_ALU_PCREL_7_0", /* name */
549 FALSE, /* partial_inplace */
550 0x00000fff, /* src_mask */
551 0x00000fff, /* dst_mask */
552 TRUE), /* pcrel_offset */
553
554 HOWTO (R_ARM_ALU_PCREL15_8, /* type */
555 0, /* rightshift */
556 2, /* size (0 = byte, 1 = short, 2 = long) */
557 12, /* bitsize */
558 TRUE, /* pc_relative */
559 8, /* bitpos */
560 complain_overflow_dont,/* complain_on_overflow */
561 bfd_elf_generic_reloc, /* special_function */
562 "R_ARM_ALU_PCREL_15_8",/* name */
563 FALSE, /* partial_inplace */
564 0x00000fff, /* src_mask */
565 0x00000fff, /* dst_mask */
566 TRUE), /* pcrel_offset */
567
568 HOWTO (R_ARM_ALU_PCREL23_15, /* type */
569 0, /* rightshift */
570 2, /* size (0 = byte, 1 = short, 2 = long) */
571 12, /* bitsize */
572 TRUE, /* pc_relative */
573 16, /* bitpos */
574 complain_overflow_dont,/* complain_on_overflow */
575 bfd_elf_generic_reloc, /* special_function */
576 "R_ARM_ALU_PCREL_23_15",/* name */
577 FALSE, /* partial_inplace */
578 0x00000fff, /* src_mask */
579 0x00000fff, /* dst_mask */
580 TRUE), /* pcrel_offset */
581
582 HOWTO (R_ARM_LDR_SBREL_11_0, /* type */
583 0, /* rightshift */
584 2, /* size (0 = byte, 1 = short, 2 = long) */
585 12, /* bitsize */
586 FALSE, /* pc_relative */
587 0, /* bitpos */
588 complain_overflow_dont,/* complain_on_overflow */
589 bfd_elf_generic_reloc, /* special_function */
590 "R_ARM_LDR_SBREL_11_0",/* name */
591 FALSE, /* partial_inplace */
592 0x00000fff, /* src_mask */
593 0x00000fff, /* dst_mask */
594 FALSE), /* pcrel_offset */
595
596 HOWTO (R_ARM_ALU_SBREL_19_12, /* type */
597 0, /* rightshift */
598 2, /* size (0 = byte, 1 = short, 2 = long) */
599 8, /* bitsize */
600 FALSE, /* pc_relative */
601 12, /* bitpos */
602 complain_overflow_dont,/* complain_on_overflow */
603 bfd_elf_generic_reloc, /* special_function */
604 "R_ARM_ALU_SBREL_19_12",/* name */
605 FALSE, /* partial_inplace */
606 0x000ff000, /* src_mask */
607 0x000ff000, /* dst_mask */
608 FALSE), /* pcrel_offset */
609
610 HOWTO (R_ARM_ALU_SBREL_27_20, /* type */
611 0, /* rightshift */
612 2, /* size (0 = byte, 1 = short, 2 = long) */
613 8, /* bitsize */
614 FALSE, /* pc_relative */
615 20, /* bitpos */
616 complain_overflow_dont,/* complain_on_overflow */
617 bfd_elf_generic_reloc, /* special_function */
618 "R_ARM_ALU_SBREL_27_20",/* name */
619 FALSE, /* partial_inplace */
620 0x0ff00000, /* src_mask */
621 0x0ff00000, /* dst_mask */
622 FALSE), /* pcrel_offset */
623
624 HOWTO (R_ARM_TARGET1, /* type */
625 0, /* rightshift */
626 2, /* size (0 = byte, 1 = short, 2 = long) */
627 32, /* bitsize */
628 FALSE, /* pc_relative */
629 0, /* bitpos */
630 complain_overflow_dont,/* complain_on_overflow */
631 bfd_elf_generic_reloc, /* special_function */
632 "R_ARM_TARGET1", /* name */
633 FALSE, /* partial_inplace */
634 0xffffffff, /* src_mask */
635 0xffffffff, /* dst_mask */
636 FALSE), /* pcrel_offset */
637
638 HOWTO (R_ARM_ROSEGREL32, /* type */
639 0, /* rightshift */
640 2, /* size (0 = byte, 1 = short, 2 = long) */
641 32, /* bitsize */
642 FALSE, /* pc_relative */
643 0, /* bitpos */
644 complain_overflow_dont,/* complain_on_overflow */
645 bfd_elf_generic_reloc, /* special_function */
646 "R_ARM_ROSEGREL32", /* name */
647 FALSE, /* partial_inplace */
648 0xffffffff, /* src_mask */
649 0xffffffff, /* dst_mask */
650 FALSE), /* pcrel_offset */
651
652 HOWTO (R_ARM_V4BX, /* type */
653 0, /* rightshift */
654 2, /* size (0 = byte, 1 = short, 2 = long) */
655 32, /* bitsize */
656 FALSE, /* pc_relative */
657 0, /* bitpos */
658 complain_overflow_dont,/* complain_on_overflow */
659 bfd_elf_generic_reloc, /* special_function */
660 "R_ARM_V4BX", /* name */
661 FALSE, /* partial_inplace */
662 0xffffffff, /* src_mask */
663 0xffffffff, /* dst_mask */
664 FALSE), /* pcrel_offset */
665
666 HOWTO (R_ARM_TARGET2, /* type */
667 0, /* rightshift */
668 2, /* size (0 = byte, 1 = short, 2 = long) */
669 32, /* bitsize */
670 FALSE, /* pc_relative */
671 0, /* bitpos */
672 complain_overflow_signed,/* complain_on_overflow */
673 bfd_elf_generic_reloc, /* special_function */
674 "R_ARM_TARGET2", /* name */
675 FALSE, /* partial_inplace */
676 0xffffffff, /* src_mask */
677 0xffffffff, /* dst_mask */
678 TRUE), /* pcrel_offset */
679
680 HOWTO (R_ARM_PREL31, /* type */
681 0, /* rightshift */
682 2, /* size (0 = byte, 1 = short, 2 = long) */
683 31, /* bitsize */
684 TRUE, /* pc_relative */
685 0, /* bitpos */
686 complain_overflow_signed,/* complain_on_overflow */
687 bfd_elf_generic_reloc, /* special_function */
688 "R_ARM_PREL31", /* name */
689 FALSE, /* partial_inplace */
690 0x7fffffff, /* src_mask */
691 0x7fffffff, /* dst_mask */
692 TRUE), /* pcrel_offset */
c19d1205
ZW		 693
694 HOWTO (R_ARM_MOVW_ABS_NC, /* type */
695 0, /* rightshift */
696 2, /* size (0 = byte, 1 = short, 2 = long) */
697 16, /* bitsize */
698 FALSE, /* pc_relative */
699 0, /* bitpos */
700 complain_overflow_dont,/* complain_on_overflow */
701 bfd_elf_generic_reloc, /* special_function */
702 "R_ARM_MOVW_ABS_NC", /* name */
703 FALSE, /* partial_inplace */
39623e12
PB		 704 0x000f0fff, /* src_mask */
705 0x000f0fff, /* dst_mask */
c19d1205
ZW		 706 FALSE), /* pcrel_offset */
707
708 HOWTO (R_ARM_MOVT_ABS, /* type */
709 0, /* rightshift */
710 2, /* size (0 = byte, 1 = short, 2 = long) */
711 16, /* bitsize */
712 FALSE, /* pc_relative */
713 0, /* bitpos */
714 complain_overflow_bitfield,/* complain_on_overflow */
715 bfd_elf_generic_reloc, /* special_function */
716 "R_ARM_MOVT_ABS", /* name */
717 FALSE, /* partial_inplace */
39623e12
PB		 718 0x000f0fff, /* src_mask */
719 0x000f0fff, /* dst_mask */
c19d1205
ZW		 720 FALSE), /* pcrel_offset */
721
722 HOWTO (R_ARM_MOVW_PREL_NC, /* type */
723 0, /* rightshift */
724 2, /* size (0 = byte, 1 = short, 2 = long) */
725 16, /* bitsize */
726 TRUE, /* pc_relative */
727 0, /* bitpos */
728 complain_overflow_dont,/* complain_on_overflow */
729 bfd_elf_generic_reloc, /* special_function */
730 "R_ARM_MOVW_PREL_NC", /* name */
731 FALSE, /* partial_inplace */
39623e12
PB		 732 0x000f0fff, /* src_mask */
733 0x000f0fff, /* dst_mask */
c19d1205
ZW		 734 TRUE), /* pcrel_offset */
735
736 HOWTO (R_ARM_MOVT_PREL, /* type */
737 0, /* rightshift */
738 2, /* size (0 = byte, 1 = short, 2 = long) */
739 16, /* bitsize */
740 TRUE, /* pc_relative */
741 0, /* bitpos */
742 complain_overflow_bitfield,/* complain_on_overflow */
743 bfd_elf_generic_reloc, /* special_function */
744 "R_ARM_MOVT_PREL", /* name */
745 FALSE, /* partial_inplace */
39623e12
PB		 746 0x000f0fff, /* src_mask */
747 0x000f0fff, /* dst_mask */
c19d1205
ZW		 748 TRUE), /* pcrel_offset */
749
750 HOWTO (R_ARM_THM_MOVW_ABS_NC, /* type */
751 0, /* rightshift */
752 2, /* size (0 = byte, 1 = short, 2 = long) */
753 16, /* bitsize */
754 FALSE, /* pc_relative */
755 0, /* bitpos */
756 complain_overflow_dont,/* complain_on_overflow */
757 bfd_elf_generic_reloc, /* special_function */
758 "R_ARM_THM_MOVW_ABS_NC",/* name */
759 FALSE, /* partial_inplace */
760 0x040f70ff, /* src_mask */
761 0x040f70ff, /* dst_mask */
762 FALSE), /* pcrel_offset */
763
764 HOWTO (R_ARM_THM_MOVT_ABS, /* type */
765 0, /* rightshift */
766 2, /* size (0 = byte, 1 = short, 2 = long) */
767 16, /* bitsize */
768 FALSE, /* pc_relative */
769 0, /* bitpos */
770 complain_overflow_bitfield,/* complain_on_overflow */
771 bfd_elf_generic_reloc, /* special_function */
772 "R_ARM_THM_MOVT_ABS", /* name */
773 FALSE, /* partial_inplace */
774 0x040f70ff, /* src_mask */
775 0x040f70ff, /* dst_mask */
776 FALSE), /* pcrel_offset */
777
778 HOWTO (R_ARM_THM_MOVW_PREL_NC,/* type */
779 0, /* rightshift */
780 2, /* size (0 = byte, 1 = short, 2 = long) */
781 16, /* bitsize */
782 TRUE, /* pc_relative */
783 0, /* bitpos */
784 complain_overflow_dont,/* complain_on_overflow */
785 bfd_elf_generic_reloc, /* special_function */
786 "R_ARM_THM_MOVW_PREL_NC",/* name */
787 FALSE, /* partial_inplace */
788 0x040f70ff, /* src_mask */
789 0x040f70ff, /* dst_mask */
790 TRUE), /* pcrel_offset */
791
792 HOWTO (R_ARM_THM_MOVT_PREL, /* type */
793 0, /* rightshift */
794 2, /* size (0 = byte, 1 = short, 2 = long) */
795 16, /* bitsize */
796 TRUE, /* pc_relative */
797 0, /* bitpos */
798 complain_overflow_bitfield,/* complain_on_overflow */
799 bfd_elf_generic_reloc, /* special_function */
800 "R_ARM_THM_MOVT_PREL", /* name */
801 FALSE, /* partial_inplace */
802 0x040f70ff, /* src_mask */
803 0x040f70ff, /* dst_mask */
804 TRUE), /* pcrel_offset */
805
806 HOWTO (R_ARM_THM_JUMP19, /* type */
807 1, /* rightshift */
808 2, /* size (0 = byte, 1 = short, 2 = long) */
809 19, /* bitsize */
810 TRUE, /* pc_relative */
811 0, /* bitpos */
812 complain_overflow_signed,/* complain_on_overflow */
813 bfd_elf_generic_reloc, /* special_function */
814 "R_ARM_THM_JUMP19", /* name */
815 FALSE, /* partial_inplace */
816 0x043f2fff, /* src_mask */
817 0x043f2fff, /* dst_mask */
818 TRUE), /* pcrel_offset */
819
820 HOWTO (R_ARM_THM_JUMP6, /* type */
821 1, /* rightshift */
822 1, /* size (0 = byte, 1 = short, 2 = long) */
823 6, /* bitsize */
824 TRUE, /* pc_relative */
825 0, /* bitpos */
826 complain_overflow_unsigned,/* complain_on_overflow */
827 bfd_elf_generic_reloc, /* special_function */
828 "R_ARM_THM_JUMP6", /* name */
829 FALSE, /* partial_inplace */
830 0x02f8, /* src_mask */
831 0x02f8, /* dst_mask */
832 TRUE), /* pcrel_offset */
833
834 /* These are declared as 13-bit signed relocations because we can
835 address -4095 .. 4095(base) by altering ADDW to SUBW or vice
836 versa. */
837 HOWTO (R_ARM_THM_ALU_PREL_11_0,/* type */
838 0, /* rightshift */
839 2, /* size (0 = byte, 1 = short, 2 = long) */
840 13, /* bitsize */
841 TRUE, /* pc_relative */
842 0, /* bitpos */
2cab6cc3 843 complain_overflow_dont,/* complain_on_overflow */
c19d1205
ZW		 844 bfd_elf_generic_reloc, /* special_function */
845 "R_ARM_THM_ALU_PREL_11_0",/* name */
846 FALSE, /* partial_inplace */
2cab6cc3
MS		 847 0xffffffff, /* src_mask */
848 0xffffffff, /* dst_mask */
c19d1205
ZW		 849 TRUE), /* pcrel_offset */
850
851 HOWTO (R_ARM_THM_PC12, /* type */
852 0, /* rightshift */
853 2, /* size (0 = byte, 1 = short, 2 = long) */
854 13, /* bitsize */
855 TRUE, /* pc_relative */
856 0, /* bitpos */
2cab6cc3 857 complain_overflow_dont,/* complain_on_overflow */
c19d1205
ZW		 858 bfd_elf_generic_reloc, /* special_function */
859 "R_ARM_THM_PC12", /* name */
860 FALSE, /* partial_inplace */
2cab6cc3
MS		 861 0xffffffff, /* src_mask */
862 0xffffffff, /* dst_mask */
c19d1205
ZW		 863 TRUE), /* pcrel_offset */
864
865 HOWTO (R_ARM_ABS32_NOI, /* type */
866 0, /* rightshift */
867 2, /* size (0 = byte, 1 = short, 2 = long) */
868 32, /* bitsize */
869 FALSE, /* pc_relative */
870 0, /* bitpos */
871 complain_overflow_dont,/* complain_on_overflow */
872 bfd_elf_generic_reloc, /* special_function */
873 "R_ARM_ABS32_NOI", /* name */
874 FALSE, /* partial_inplace */
875 0xffffffff, /* src_mask */
876 0xffffffff, /* dst_mask */
877 FALSE), /* pcrel_offset */
878
879 HOWTO (R_ARM_REL32_NOI, /* type */
880 0, /* rightshift */
881 2, /* size (0 = byte, 1 = short, 2 = long) */
882 32, /* bitsize */
883 TRUE, /* pc_relative */
884 0, /* bitpos */
885 complain_overflow_dont,/* complain_on_overflow */
886 bfd_elf_generic_reloc, /* special_function */
887 "R_ARM_REL32_NOI", /* name */
888 FALSE, /* partial_inplace */
889 0xffffffff, /* src_mask */
890 0xffffffff, /* dst_mask */
891 FALSE), /* pcrel_offset */
7f266840 892
4962c51a
MS		 893 /* Group relocations. */
894
895 HOWTO (R_ARM_ALU_PC_G0_NC, /* type */
896 0, /* rightshift */
897 2, /* size (0 = byte, 1 = short, 2 = long) */
898 32, /* bitsize */
899 TRUE, /* pc_relative */
900 0, /* bitpos */
901 complain_overflow_dont,/* complain_on_overflow */
902 bfd_elf_generic_reloc, /* special_function */
903 "R_ARM_ALU_PC_G0_NC", /* name */
904 FALSE, /* partial_inplace */
905 0xffffffff, /* src_mask */
906 0xffffffff, /* dst_mask */
907 TRUE), /* pcrel_offset */
908
909 HOWTO (R_ARM_ALU_PC_G0, /* type */
910 0, /* rightshift */
911 2, /* size (0 = byte, 1 = short, 2 = long) */
912 32, /* bitsize */
913 TRUE, /* pc_relative */
914 0, /* bitpos */
915 complain_overflow_dont,/* complain_on_overflow */
916 bfd_elf_generic_reloc, /* special_function */
917 "R_ARM_ALU_PC_G0", /* name */
918 FALSE, /* partial_inplace */
919 0xffffffff, /* src_mask */
920 0xffffffff, /* dst_mask */
921 TRUE), /* pcrel_offset */
922
923 HOWTO (R_ARM_ALU_PC_G1_NC, /* type */
924 0, /* rightshift */
925 2, /* size (0 = byte, 1 = short, 2 = long) */
926 32, /* bitsize */
927 TRUE, /* pc_relative */
928 0, /* bitpos */
929 complain_overflow_dont,/* complain_on_overflow */
930 bfd_elf_generic_reloc, /* special_function */
931 "R_ARM_ALU_PC_G1_NC", /* name */
932 FALSE, /* partial_inplace */
933 0xffffffff, /* src_mask */
934 0xffffffff, /* dst_mask */
935 TRUE), /* pcrel_offset */
936
937 HOWTO (R_ARM_ALU_PC_G1, /* type */
938 0, /* rightshift */
939 2, /* size (0 = byte, 1 = short, 2 = long) */
940 32, /* bitsize */
941 TRUE, /* pc_relative */
942 0, /* bitpos */
943 complain_overflow_dont,/* complain_on_overflow */
944 bfd_elf_generic_reloc, /* special_function */
945 "R_ARM_ALU_PC_G1", /* name */
946 FALSE, /* partial_inplace */
947 0xffffffff, /* src_mask */
948 0xffffffff, /* dst_mask */
949 TRUE), /* pcrel_offset */
950
951 HOWTO (R_ARM_ALU_PC_G2, /* type */
952 0, /* rightshift */
953 2, /* size (0 = byte, 1 = short, 2 = long) */
954 32, /* bitsize */
955 TRUE, /* pc_relative */
956 0, /* bitpos */
957 complain_overflow_dont,/* complain_on_overflow */
958 bfd_elf_generic_reloc, /* special_function */
959 "R_ARM_ALU_PC_G2", /* name */
960 FALSE, /* partial_inplace */
961 0xffffffff, /* src_mask */
962 0xffffffff, /* dst_mask */
963 TRUE), /* pcrel_offset */
964
965 HOWTO (R_ARM_LDR_PC_G1, /* type */
966 0, /* rightshift */
967 2, /* size (0 = byte, 1 = short, 2 = long) */
968 32, /* bitsize */
969 TRUE, /* pc_relative */
970 0, /* bitpos */
971 complain_overflow_dont,/* complain_on_overflow */
972 bfd_elf_generic_reloc, /* special_function */
973 "R_ARM_LDR_PC_G1", /* name */
974 FALSE, /* partial_inplace */
975 0xffffffff, /* src_mask */
976 0xffffffff, /* dst_mask */
977 TRUE), /* pcrel_offset */
978
979 HOWTO (R_ARM_LDR_PC_G2, /* type */
980 0, /* rightshift */
981 2, /* size (0 = byte, 1 = short, 2 = long) */
982 32, /* bitsize */
983 TRUE, /* pc_relative */
984 0, /* bitpos */
985 complain_overflow_dont,/* complain_on_overflow */
986 bfd_elf_generic_reloc, /* special_function */
987 "R_ARM_LDR_PC_G2", /* name */
988 FALSE, /* partial_inplace */
989 0xffffffff, /* src_mask */
990 0xffffffff, /* dst_mask */
991 TRUE), /* pcrel_offset */
992
993 HOWTO (R_ARM_LDRS_PC_G0, /* type */
994 0, /* rightshift */
995 2, /* size (0 = byte, 1 = short, 2 = long) */
996 32, /* bitsize */
997 TRUE, /* pc_relative */
998 0, /* bitpos */
999 complain_overflow_dont,/* complain_on_overflow */
1000 bfd_elf_generic_reloc, /* special_function */
1001 "R_ARM_LDRS_PC_G0", /* name */
1002 FALSE, /* partial_inplace */
1003 0xffffffff, /* src_mask */
1004 0xffffffff, /* dst_mask */
1005 TRUE), /* pcrel_offset */
1006
1007 HOWTO (R_ARM_LDRS_PC_G1, /* type */
1008 0, /* rightshift */
1009 2, /* size (0 = byte, 1 = short, 2 = long) */
1010 32, /* bitsize */
1011 TRUE, /* pc_relative */
1012 0, /* bitpos */
1013 complain_overflow_dont,/* complain_on_overflow */
1014 bfd_elf_generic_reloc, /* special_function */
1015 "R_ARM_LDRS_PC_G1", /* name */
1016 FALSE, /* partial_inplace */
1017 0xffffffff, /* src_mask */
1018 0xffffffff, /* dst_mask */
1019 TRUE), /* pcrel_offset */
1020
1021 HOWTO (R_ARM_LDRS_PC_G2, /* type */
1022 0, /* rightshift */
1023 2, /* size (0 = byte, 1 = short, 2 = long) */
1024 32, /* bitsize */
1025 TRUE, /* pc_relative */
1026 0, /* bitpos */
1027 complain_overflow_dont,/* complain_on_overflow */
1028 bfd_elf_generic_reloc, /* special_function */
1029 "R_ARM_LDRS_PC_G2", /* name */
1030 FALSE, /* partial_inplace */
1031 0xffffffff, /* src_mask */
1032 0xffffffff, /* dst_mask */
1033 TRUE), /* pcrel_offset */
1034
1035 HOWTO (R_ARM_LDC_PC_G0, /* type */
1036 0, /* rightshift */
1037 2, /* size (0 = byte, 1 = short, 2 = long) */
1038 32, /* bitsize */
1039 TRUE, /* pc_relative */
1040 0, /* bitpos */
1041 complain_overflow_dont,/* complain_on_overflow */
1042 bfd_elf_generic_reloc, /* special_function */
1043 "R_ARM_LDC_PC_G0", /* name */
1044 FALSE, /* partial_inplace */
1045 0xffffffff, /* src_mask */
1046 0xffffffff, /* dst_mask */
1047 TRUE), /* pcrel_offset */
1048
1049 HOWTO (R_ARM_LDC_PC_G1, /* type */
1050 0, /* rightshift */
1051 2, /* size (0 = byte, 1 = short, 2 = long) */
1052 32, /* bitsize */
1053 TRUE, /* pc_relative */
1054 0, /* bitpos */
1055 complain_overflow_dont,/* complain_on_overflow */
1056 bfd_elf_generic_reloc, /* special_function */
1057 "R_ARM_LDC_PC_G1", /* name */
1058 FALSE, /* partial_inplace */
1059 0xffffffff, /* src_mask */
1060 0xffffffff, /* dst_mask */
1061 TRUE), /* pcrel_offset */
1062
1063 HOWTO (R_ARM_LDC_PC_G2, /* type */
1064 0, /* rightshift */
1065 2, /* size (0 = byte, 1 = short, 2 = long) */
1066 32, /* bitsize */
1067 TRUE, /* pc_relative */
1068 0, /* bitpos */
1069 complain_overflow_dont,/* complain_on_overflow */
1070 bfd_elf_generic_reloc, /* special_function */
1071 "R_ARM_LDC_PC_G2", /* name */
1072 FALSE, /* partial_inplace */
1073 0xffffffff, /* src_mask */
1074 0xffffffff, /* dst_mask */
1075 TRUE), /* pcrel_offset */
1076
1077 HOWTO (R_ARM_ALU_SB_G0_NC, /* type */
1078 0, /* rightshift */
1079 2, /* size (0 = byte, 1 = short, 2 = long) */
1080 32, /* bitsize */
1081 TRUE, /* pc_relative */
1082 0, /* bitpos */
1083 complain_overflow_dont,/* complain_on_overflow */
1084 bfd_elf_generic_reloc, /* special_function */
1085 "R_ARM_ALU_SB_G0_NC", /* name */
1086 FALSE, /* partial_inplace */
1087 0xffffffff, /* src_mask */
1088 0xffffffff, /* dst_mask */
1089 TRUE), /* pcrel_offset */
1090
1091 HOWTO (R_ARM_ALU_SB_G0, /* type */
1092 0, /* rightshift */
1093 2, /* size (0 = byte, 1 = short, 2 = long) */
1094 32, /* bitsize */
1095 TRUE, /* pc_relative */
1096 0, /* bitpos */
1097 complain_overflow_dont,/* complain_on_overflow */
1098 bfd_elf_generic_reloc, /* special_function */
1099 "R_ARM_ALU_SB_G0", /* name */
1100 FALSE, /* partial_inplace */
1101 0xffffffff, /* src_mask */
1102 0xffffffff, /* dst_mask */
1103 TRUE), /* pcrel_offset */
1104
1105 HOWTO (R_ARM_ALU_SB_G1_NC, /* type */
1106 0, /* rightshift */
1107 2, /* size (0 = byte, 1 = short, 2 = long) */
1108 32, /* bitsize */
1109 TRUE, /* pc_relative */
1110 0, /* bitpos */
1111 complain_overflow_dont,/* complain_on_overflow */
1112 bfd_elf_generic_reloc, /* special_function */
1113 "R_ARM_ALU_SB_G1_NC", /* name */
1114 FALSE, /* partial_inplace */
1115 0xffffffff, /* src_mask */
1116 0xffffffff, /* dst_mask */
1117 TRUE), /* pcrel_offset */
1118
1119 HOWTO (R_ARM_ALU_SB_G1, /* type */
1120 0, /* rightshift */
1121 2, /* size (0 = byte, 1 = short, 2 = long) */
1122 32, /* bitsize */
1123 TRUE, /* pc_relative */
1124 0, /* bitpos */
1125 complain_overflow_dont,/* complain_on_overflow */
1126 bfd_elf_generic_reloc, /* special_function */
1127 "R_ARM_ALU_SB_G1", /* name */
1128 FALSE, /* partial_inplace */
1129 0xffffffff, /* src_mask */
1130 0xffffffff, /* dst_mask */
1131 TRUE), /* pcrel_offset */
1132
1133 HOWTO (R_ARM_ALU_SB_G2, /* type */
1134 0, /* rightshift */
1135 2, /* size (0 = byte, 1 = short, 2 = long) */
1136 32, /* bitsize */
1137 TRUE, /* pc_relative */
1138 0, /* bitpos */
1139 complain_overflow_dont,/* complain_on_overflow */
1140 bfd_elf_generic_reloc, /* special_function */
1141 "R_ARM_ALU_SB_G2", /* name */
1142 FALSE, /* partial_inplace */
1143 0xffffffff, /* src_mask */
1144 0xffffffff, /* dst_mask */
1145 TRUE), /* pcrel_offset */
1146
1147 HOWTO (R_ARM_LDR_SB_G0, /* type */
1148 0, /* rightshift */
1149 2, /* size (0 = byte, 1 = short, 2 = long) */
1150 32, /* bitsize */
1151 TRUE, /* pc_relative */
1152 0, /* bitpos */
1153 complain_overflow_dont,/* complain_on_overflow */
1154 bfd_elf_generic_reloc, /* special_function */
1155 "R_ARM_LDR_SB_G0", /* name */
1156 FALSE, /* partial_inplace */
1157 0xffffffff, /* src_mask */
1158 0xffffffff, /* dst_mask */
1159 TRUE), /* pcrel_offset */
1160
1161 HOWTO (R_ARM_LDR_SB_G1, /* type */
1162 0, /* rightshift */
1163 2, /* size (0 = byte, 1 = short, 2 = long) */
1164 32, /* bitsize */
1165 TRUE, /* pc_relative */
1166 0, /* bitpos */
1167 complain_overflow_dont,/* complain_on_overflow */
1168 bfd_elf_generic_reloc, /* special_function */
1169 "R_ARM_LDR_SB_G1", /* name */
1170 FALSE, /* partial_inplace */
1171 0xffffffff, /* src_mask */
1172 0xffffffff, /* dst_mask */
1173 TRUE), /* pcrel_offset */
1174
1175 HOWTO (R_ARM_LDR_SB_G2, /* type */
1176 0, /* rightshift */
1177 2, /* size (0 = byte, 1 = short, 2 = long) */
1178 32, /* bitsize */
1179 TRUE, /* pc_relative */
1180 0, /* bitpos */
1181 complain_overflow_dont,/* complain_on_overflow */
1182 bfd_elf_generic_reloc, /* special_function */
1183 "R_ARM_LDR_SB_G2", /* name */
1184 FALSE, /* partial_inplace */
1185 0xffffffff, /* src_mask */
1186 0xffffffff, /* dst_mask */
1187 TRUE), /* pcrel_offset */
1188
1189 HOWTO (R_ARM_LDRS_SB_G0, /* type */
1190 0, /* rightshift */
1191 2, /* size (0 = byte, 1 = short, 2 = long) */
1192 32, /* bitsize */
1193 TRUE, /* pc_relative */
1194 0, /* bitpos */
1195 complain_overflow_dont,/* complain_on_overflow */
1196 bfd_elf_generic_reloc, /* special_function */
1197 "R_ARM_LDRS_SB_G0", /* name */
1198 FALSE, /* partial_inplace */
1199 0xffffffff, /* src_mask */
1200 0xffffffff, /* dst_mask */
1201 TRUE), /* pcrel_offset */
1202
1203 HOWTO (R_ARM_LDRS_SB_G1, /* type */
1204 0, /* rightshift */
1205 2, /* size (0 = byte, 1 = short, 2 = long) */
1206 32, /* bitsize */
1207 TRUE, /* pc_relative */
1208 0, /* bitpos */
1209 complain_overflow_dont,/* complain_on_overflow */
1210 bfd_elf_generic_reloc, /* special_function */
1211 "R_ARM_LDRS_SB_G1", /* name */
1212 FALSE, /* partial_inplace */
1213 0xffffffff, /* src_mask */
1214 0xffffffff, /* dst_mask */
1215 TRUE), /* pcrel_offset */
1216
1217 HOWTO (R_ARM_LDRS_SB_G2, /* type */
1218 0, /* rightshift */
1219 2, /* size (0 = byte, 1 = short, 2 = long) */
1220 32, /* bitsize */
1221 TRUE, /* pc_relative */
1222 0, /* bitpos */
1223 complain_overflow_dont,/* complain_on_overflow */
1224 bfd_elf_generic_reloc, /* special_function */
1225 "R_ARM_LDRS_SB_G2", /* name */
1226 FALSE, /* partial_inplace */
1227 0xffffffff, /* src_mask */
1228 0xffffffff, /* dst_mask */
1229 TRUE), /* pcrel_offset */
1230
1231 HOWTO (R_ARM_LDC_SB_G0, /* type */
1232 0, /* rightshift */
1233 2, /* size (0 = byte, 1 = short, 2 = long) */
1234 32, /* bitsize */
1235 TRUE, /* pc_relative */
1236 0, /* bitpos */
1237 complain_overflow_dont,/* complain_on_overflow */
1238 bfd_elf_generic_reloc, /* special_function */
1239 "R_ARM_LDC_SB_G0", /* name */
1240 FALSE, /* partial_inplace */
1241 0xffffffff, /* src_mask */
1242 0xffffffff, /* dst_mask */
1243 TRUE), /* pcrel_offset */
1244
1245 HOWTO (R_ARM_LDC_SB_G1, /* type */
1246 0, /* rightshift */
1247 2, /* size (0 = byte, 1 = short, 2 = long) */
1248 32, /* bitsize */
1249 TRUE, /* pc_relative */
1250 0, /* bitpos */
1251 complain_overflow_dont,/* complain_on_overflow */
1252 bfd_elf_generic_reloc, /* special_function */
1253 "R_ARM_LDC_SB_G1", /* name */
1254 FALSE, /* partial_inplace */
1255 0xffffffff, /* src_mask */
1256 0xffffffff, /* dst_mask */
1257 TRUE), /* pcrel_offset */
1258
1259 HOWTO (R_ARM_LDC_SB_G2, /* type */
1260 0, /* rightshift */
1261 2, /* size (0 = byte, 1 = short, 2 = long) */
1262 32, /* bitsize */
1263 TRUE, /* pc_relative */
1264 0, /* bitpos */
1265 complain_overflow_dont,/* complain_on_overflow */
1266 bfd_elf_generic_reloc, /* special_function */
1267 "R_ARM_LDC_SB_G2", /* name */
1268 FALSE, /* partial_inplace */
1269 0xffffffff, /* src_mask */
1270 0xffffffff, /* dst_mask */
1271 TRUE), /* pcrel_offset */
1272
1273 /* End of group relocations. */
c19d1205 1274
c19d1205
ZW		 1275 HOWTO (R_ARM_MOVW_BREL_NC, /* type */
1276 0, /* rightshift */
1277 2, /* size (0 = byte, 1 = short, 2 = long) */
1278 16, /* bitsize */
1279 FALSE, /* pc_relative */
1280 0, /* bitpos */
1281 complain_overflow_dont,/* complain_on_overflow */
1282 bfd_elf_generic_reloc, /* special_function */
1283 "R_ARM_MOVW_BREL_NC", /* name */
1284 FALSE, /* partial_inplace */
1285 0x0000ffff, /* src_mask */
1286 0x0000ffff, /* dst_mask */
1287 FALSE), /* pcrel_offset */
1288
1289 HOWTO (R_ARM_MOVT_BREL, /* type */
1290 0, /* rightshift */
1291 2, /* size (0 = byte, 1 = short, 2 = long) */
1292 16, /* bitsize */
1293 FALSE, /* pc_relative */
1294 0, /* bitpos */
1295 complain_overflow_bitfield,/* complain_on_overflow */
1296 bfd_elf_generic_reloc, /* special_function */
1297 "R_ARM_MOVT_BREL", /* name */
1298 FALSE, /* partial_inplace */
1299 0x0000ffff, /* src_mask */
1300 0x0000ffff, /* dst_mask */
1301 FALSE), /* pcrel_offset */
1302
1303 HOWTO (R_ARM_MOVW_BREL, /* type */
1304 0, /* rightshift */
1305 2, /* size (0 = byte, 1 = short, 2 = long) */
1306 16, /* bitsize */
1307 FALSE, /* pc_relative */
1308 0, /* bitpos */
1309 complain_overflow_dont,/* complain_on_overflow */
1310 bfd_elf_generic_reloc, /* special_function */
1311 "R_ARM_MOVW_BREL", /* name */
1312 FALSE, /* partial_inplace */
1313 0x0000ffff, /* src_mask */
1314 0x0000ffff, /* dst_mask */
1315 FALSE), /* pcrel_offset */
1316
1317 HOWTO (R_ARM_THM_MOVW_BREL_NC,/* type */
1318 0, /* rightshift */
1319 2, /* size (0 = byte, 1 = short, 2 = long) */
1320 16, /* bitsize */
1321 FALSE, /* pc_relative */
1322 0, /* bitpos */
1323 complain_overflow_dont,/* complain_on_overflow */
1324 bfd_elf_generic_reloc, /* special_function */
1325 "R_ARM_THM_MOVW_BREL_NC",/* name */
1326 FALSE, /* partial_inplace */
1327 0x040f70ff, /* src_mask */
1328 0x040f70ff, /* dst_mask */
1329 FALSE), /* pcrel_offset */
1330
1331 HOWTO (R_ARM_THM_MOVT_BREL, /* type */
1332 0, /* rightshift */
1333 2, /* size (0 = byte, 1 = short, 2 = long) */
1334 16, /* bitsize */
1335 FALSE, /* pc_relative */
1336 0, /* bitpos */
1337 complain_overflow_bitfield,/* complain_on_overflow */
1338 bfd_elf_generic_reloc, /* special_function */
1339 "R_ARM_THM_MOVT_BREL", /* name */
1340 FALSE, /* partial_inplace */
1341 0x040f70ff, /* src_mask */
1342 0x040f70ff, /* dst_mask */
1343 FALSE), /* pcrel_offset */
1344
1345 HOWTO (R_ARM_THM_MOVW_BREL, /* type */
1346 0, /* rightshift */
1347 2, /* size (0 = byte, 1 = short, 2 = long) */
1348 16, /* bitsize */
1349 FALSE, /* pc_relative */
1350 0, /* bitpos */
1351 complain_overflow_dont,/* complain_on_overflow */
1352 bfd_elf_generic_reloc, /* special_function */
1353 "R_ARM_THM_MOVW_BREL", /* name */
1354 FALSE, /* partial_inplace */
1355 0x040f70ff, /* src_mask */
1356 0x040f70ff, /* dst_mask */
1357 FALSE), /* pcrel_offset */
1358
0855e32b
NS		 1359 HOWTO (R_ARM_TLS_GOTDESC, /* type */
1360 0, /* rightshift */
1361 2, /* size (0 = byte, 1 = short, 2 = long) */
1362 32, /* bitsize */
1363 FALSE, /* pc_relative */
1364 0, /* bitpos */
1365 complain_overflow_bitfield,/* complain_on_overflow */
1366 NULL, /* special_function */
1367 "R_ARM_TLS_GOTDESC", /* name */
1368 TRUE, /* partial_inplace */
1369 0xffffffff, /* src_mask */
1370 0xffffffff, /* dst_mask */
1371 FALSE), /* pcrel_offset */
1372
1373 HOWTO (R_ARM_TLS_CALL, /* type */
1374 0, /* rightshift */
1375 2, /* size (0 = byte, 1 = short, 2 = long) */
1376 24, /* bitsize */
1377 FALSE, /* pc_relative */
1378 0, /* bitpos */
1379 complain_overflow_dont,/* complain_on_overflow */
1380 bfd_elf_generic_reloc, /* special_function */
1381 "R_ARM_TLS_CALL", /* name */
1382 FALSE, /* partial_inplace */
1383 0x00ffffff, /* src_mask */
1384 0x00ffffff, /* dst_mask */
1385 FALSE), /* pcrel_offset */
1386
1387 HOWTO (R_ARM_TLS_DESCSEQ, /* type */
1388 0, /* rightshift */
1389 2, /* size (0 = byte, 1 = short, 2 = long) */
1390 0, /* bitsize */
1391 FALSE, /* pc_relative */
1392 0, /* bitpos */
1393 complain_overflow_bitfield,/* complain_on_overflow */
1394 bfd_elf_generic_reloc, /* special_function */
1395 "R_ARM_TLS_DESCSEQ", /* name */
1396 FALSE, /* partial_inplace */
1397 0x00000000, /* src_mask */
1398 0x00000000, /* dst_mask */
1399 FALSE), /* pcrel_offset */
1400
1401 HOWTO (R_ARM_THM_TLS_CALL, /* type */
1402 0, /* rightshift */
1403 2, /* size (0 = byte, 1 = short, 2 = long) */
1404 24, /* bitsize */
1405 FALSE, /* pc_relative */
1406 0, /* bitpos */
1407 complain_overflow_dont,/* complain_on_overflow */
1408 bfd_elf_generic_reloc, /* special_function */
1409 "R_ARM_THM_TLS_CALL", /* name */
1410 FALSE, /* partial_inplace */
1411 0x07ff07ff, /* src_mask */
1412 0x07ff07ff, /* dst_mask */
1413 FALSE), /* pcrel_offset */
c19d1205
ZW		 1414
1415 HOWTO (R_ARM_PLT32_ABS, /* type */
1416 0, /* rightshift */
1417 2, /* size (0 = byte, 1 = short, 2 = long) */
1418 32, /* bitsize */
1419 FALSE, /* pc_relative */
1420 0, /* bitpos */
1421 complain_overflow_dont,/* complain_on_overflow */
1422 bfd_elf_generic_reloc, /* special_function */
1423 "R_ARM_PLT32_ABS", /* name */
1424 FALSE, /* partial_inplace */
1425 0xffffffff, /* src_mask */
1426 0xffffffff, /* dst_mask */
1427 FALSE), /* pcrel_offset */
1428
1429 HOWTO (R_ARM_GOT_ABS, /* type */
1430 0, /* rightshift */
1431 2, /* size (0 = byte, 1 = short, 2 = long) */
1432 32, /* bitsize */
1433 FALSE, /* pc_relative */
1434 0, /* bitpos */
1435 complain_overflow_dont,/* complain_on_overflow */
1436 bfd_elf_generic_reloc, /* special_function */
1437 "R_ARM_GOT_ABS", /* name */
1438 FALSE, /* partial_inplace */
1439 0xffffffff, /* src_mask */
1440 0xffffffff, /* dst_mask */
1441 FALSE), /* pcrel_offset */
1442
1443 HOWTO (R_ARM_GOT_PREL, /* type */
1444 0, /* rightshift */
1445 2, /* size (0 = byte, 1 = short, 2 = long) */
1446 32, /* bitsize */
1447 TRUE, /* pc_relative */
1448 0, /* bitpos */
1449 complain_overflow_dont, /* complain_on_overflow */
1450 bfd_elf_generic_reloc, /* special_function */
1451 "R_ARM_GOT_PREL", /* name */
1452 FALSE, /* partial_inplace */
1453 0xffffffff, /* src_mask */
1454 0xffffffff, /* dst_mask */
1455 TRUE), /* pcrel_offset */
1456
1457 HOWTO (R_ARM_GOT_BREL12, /* type */
1458 0, /* rightshift */
1459 2, /* size (0 = byte, 1 = short, 2 = long) */
1460 12, /* bitsize */
1461 FALSE, /* pc_relative */
1462 0, /* bitpos */
1463 complain_overflow_bitfield,/* complain_on_overflow */
1464 bfd_elf_generic_reloc, /* special_function */
1465 "R_ARM_GOT_BREL12", /* name */
1466 FALSE, /* partial_inplace */
1467 0x00000fff, /* src_mask */
1468 0x00000fff, /* dst_mask */
1469 FALSE), /* pcrel_offset */
1470
1471 HOWTO (R_ARM_GOTOFF12, /* type */
1472 0, /* rightshift */
1473 2, /* size (0 = byte, 1 = short, 2 = long) */
1474 12, /* bitsize */
1475 FALSE, /* pc_relative */
1476 0, /* bitpos */
1477 complain_overflow_bitfield,/* complain_on_overflow */
1478 bfd_elf_generic_reloc, /* special_function */
1479 "R_ARM_GOTOFF12", /* name */
1480 FALSE, /* partial_inplace */
1481 0x00000fff, /* src_mask */
1482 0x00000fff, /* dst_mask */
1483 FALSE), /* pcrel_offset */
1484
1485 EMPTY_HOWTO (R_ARM_GOTRELAX), /* reserved for future GOT-load optimizations */
1486
1487 /* GNU extension to record C++ vtable member usage */
1488 HOWTO (R_ARM_GNU_VTENTRY, /* type */
99059e56
RM		 1489 0, /* rightshift */
1490 2, /* size (0 = byte, 1 = short, 2 = long) */
1491 0, /* bitsize */
1492 FALSE, /* pc_relative */
1493 0, /* bitpos */
1494 complain_overflow_dont, /* complain_on_overflow */
1495 _bfd_elf_rel_vtable_reloc_fn, /* special_function */
1496 "R_ARM_GNU_VTENTRY", /* name */
1497 FALSE, /* partial_inplace */
1498 0, /* src_mask */
1499 0, /* dst_mask */
1500 FALSE), /* pcrel_offset */
c19d1205
ZW		 1501
1502 /* GNU extension to record C++ vtable hierarchy */
1503 HOWTO (R_ARM_GNU_VTINHERIT, /* type */
99059e56
RM		 1504 0, /* rightshift */
1505 2, /* size (0 = byte, 1 = short, 2 = long) */
1506 0, /* bitsize */
1507 FALSE, /* pc_relative */
1508 0, /* bitpos */
1509 complain_overflow_dont, /* complain_on_overflow */
1510 NULL, /* special_function */
1511 "R_ARM_GNU_VTINHERIT", /* name */
1512 FALSE, /* partial_inplace */
1513 0, /* src_mask */
1514 0, /* dst_mask */
1515 FALSE), /* pcrel_offset */
c19d1205
ZW		 1516
1517 HOWTO (R_ARM_THM_JUMP11, /* type */
1518 1, /* rightshift */
1519 1, /* size (0 = byte, 1 = short, 2 = long) */
1520 11, /* bitsize */
1521 TRUE, /* pc_relative */
1522 0, /* bitpos */
1523 complain_overflow_signed, /* complain_on_overflow */
1524 bfd_elf_generic_reloc, /* special_function */
1525 "R_ARM_THM_JUMP11", /* name */
1526 FALSE, /* partial_inplace */
1527 0x000007ff, /* src_mask */
1528 0x000007ff, /* dst_mask */
1529 TRUE), /* pcrel_offset */
1530
1531 HOWTO (R_ARM_THM_JUMP8, /* type */
1532 1, /* rightshift */
1533 1, /* size (0 = byte, 1 = short, 2 = long) */
1534 8, /* bitsize */
1535 TRUE, /* pc_relative */
1536 0, /* bitpos */
1537 complain_overflow_signed, /* complain_on_overflow */
1538 bfd_elf_generic_reloc, /* special_function */
1539 "R_ARM_THM_JUMP8", /* name */
1540 FALSE, /* partial_inplace */
1541 0x000000ff, /* src_mask */
1542 0x000000ff, /* dst_mask */
1543 TRUE), /* pcrel_offset */
ba93b8ac 1544
c19d1205
ZW		 1545 /* TLS relocations */
1546 HOWTO (R_ARM_TLS_GD32, /* type */
99059e56
RM		 1547 0, /* rightshift */
1548 2, /* size (0 = byte, 1 = short, 2 = long) */
1549 32, /* bitsize */
1550 FALSE, /* pc_relative */
1551 0, /* bitpos */
1552 complain_overflow_bitfield,/* complain_on_overflow */
1553 NULL, /* special_function */
1554 "R_ARM_TLS_GD32", /* name */
1555 TRUE, /* partial_inplace */
1556 0xffffffff, /* src_mask */
1557 0xffffffff, /* dst_mask */
1558 FALSE), /* pcrel_offset */
ba93b8ac 1559
ba93b8ac 1560 HOWTO (R_ARM_TLS_LDM32, /* type */
99059e56
RM		 1561 0, /* rightshift */
1562 2, /* size (0 = byte, 1 = short, 2 = long) */
1563 32, /* bitsize */
1564 FALSE, /* pc_relative */
1565 0, /* bitpos */
1566 complain_overflow_bitfield,/* complain_on_overflow */
1567 bfd_elf_generic_reloc, /* special_function */
1568 "R_ARM_TLS_LDM32", /* name */
1569 TRUE, /* partial_inplace */
1570 0xffffffff, /* src_mask */
1571 0xffffffff, /* dst_mask */
1572 FALSE), /* pcrel_offset */
ba93b8ac 1573
c19d1205 1574 HOWTO (R_ARM_TLS_LDO32, /* type */
99059e56
RM		 1575 0, /* rightshift */
1576 2, /* size (0 = byte, 1 = short, 2 = long) */
1577 32, /* bitsize */
1578 FALSE, /* pc_relative */
1579 0, /* bitpos */
1580 complain_overflow_bitfield,/* complain_on_overflow */
1581 bfd_elf_generic_reloc, /* special_function */
1582 "R_ARM_TLS_LDO32", /* name */
1583 TRUE, /* partial_inplace */
1584 0xffffffff, /* src_mask */
1585 0xffffffff, /* dst_mask */
1586 FALSE), /* pcrel_offset */
ba93b8ac 1587
ba93b8ac 1588 HOWTO (R_ARM_TLS_IE32, /* type */
99059e56
RM		 1589 0, /* rightshift */
1590 2, /* size (0 = byte, 1 = short, 2 = long) */
1591 32, /* bitsize */
1592 FALSE, /* pc_relative */
1593 0, /* bitpos */
1594 complain_overflow_bitfield,/* complain_on_overflow */
1595 NULL, /* special_function */
1596 "R_ARM_TLS_IE32", /* name */
1597 TRUE, /* partial_inplace */
1598 0xffffffff, /* src_mask */
1599 0xffffffff, /* dst_mask */
1600 FALSE), /* pcrel_offset */
7f266840 1601
c19d1205 1602 HOWTO (R_ARM_TLS_LE32, /* type */
99059e56
RM		 1603 0, /* rightshift */
1604 2, /* size (0 = byte, 1 = short, 2 = long) */
1605 32, /* bitsize */
1606 FALSE, /* pc_relative */
1607 0, /* bitpos */
1608 complain_overflow_bitfield,/* complain_on_overflow */
75c11999 1609 NULL, /* special_function */
99059e56
RM		 1610 "R_ARM_TLS_LE32", /* name */
1611 TRUE, /* partial_inplace */
1612 0xffffffff, /* src_mask */
1613 0xffffffff, /* dst_mask */
1614 FALSE), /* pcrel_offset */
7f266840 1615
c19d1205
ZW		 1616 HOWTO (R_ARM_TLS_LDO12, /* type */
1617 0, /* rightshift */
1618 2, /* size (0 = byte, 1 = short, 2 = long) */
1619 12, /* bitsize */
1620 FALSE, /* pc_relative */
7f266840 1621 0, /* bitpos */
c19d1205 1622 complain_overflow_bitfield,/* complain_on_overflow */
7f266840 1623 bfd_elf_generic_reloc, /* special_function */
c19d1205 1624 "R_ARM_TLS_LDO12", /* name */
7f266840 1625 FALSE, /* partial_inplace */
c19d1205
ZW		 1626 0x00000fff, /* src_mask */
1627 0x00000fff, /* dst_mask */
1628 FALSE), /* pcrel_offset */
7f266840 1629
c19d1205
ZW		 1630 HOWTO (R_ARM_TLS_LE12, /* type */
1631 0, /* rightshift */
1632 2, /* size (0 = byte, 1 = short, 2 = long) */
1633 12, /* bitsize */
1634 FALSE, /* pc_relative */
7f266840 1635 0, /* bitpos */
c19d1205 1636 complain_overflow_bitfield,/* complain_on_overflow */
7f266840 1637 bfd_elf_generic_reloc, /* special_function */
c19d1205 1638 "R_ARM_TLS_LE12", /* name */
7f266840 1639 FALSE, /* partial_inplace */
c19d1205
ZW		 1640 0x00000fff, /* src_mask */
1641 0x00000fff, /* dst_mask */
1642 FALSE), /* pcrel_offset */
7f266840 1643
c19d1205 1644 HOWTO (R_ARM_TLS_IE12GP, /* type */
7f266840
DJ		 1645 0, /* rightshift */
1646 2, /* size (0 = byte, 1 = short, 2 = long) */
c19d1205
ZW		 1647 12, /* bitsize */
1648 FALSE, /* pc_relative */
7f266840 1649 0, /* bitpos */
c19d1205 1650 complain_overflow_bitfield,/* complain_on_overflow */
7f266840 1651 bfd_elf_generic_reloc, /* special_function */
c19d1205 1652 "R_ARM_TLS_IE12GP", /* name */
7f266840 1653 FALSE, /* partial_inplace */
c19d1205
ZW		 1654 0x00000fff, /* src_mask */
1655 0x00000fff, /* dst_mask */
1656 FALSE), /* pcrel_offset */
0855e32b 1657
34e77a92 1658 /* 112-127 private relocations. */
0855e32b
NS		 1659 EMPTY_HOWTO (112),
1660 EMPTY_HOWTO (113),
1661 EMPTY_HOWTO (114),
1662 EMPTY_HOWTO (115),
1663 EMPTY_HOWTO (116),
1664 EMPTY_HOWTO (117),
1665 EMPTY_HOWTO (118),
1666 EMPTY_HOWTO (119),
1667 EMPTY_HOWTO (120),
1668 EMPTY_HOWTO (121),
1669 EMPTY_HOWTO (122),
1670 EMPTY_HOWTO (123),
1671 EMPTY_HOWTO (124),
1672 EMPTY_HOWTO (125),
1673 EMPTY_HOWTO (126),
1674 EMPTY_HOWTO (127),
34e77a92
RS		 1675
1676 /* R_ARM_ME_TOO, obsolete. */
0855e32b
NS		 1677 EMPTY_HOWTO (128),
1678
1679 HOWTO (R_ARM_THM_TLS_DESCSEQ, /* type */
1680 0, /* rightshift */
1681 1, /* size (0 = byte, 1 = short, 2 = long) */
1682 0, /* bitsize */
1683 FALSE, /* pc_relative */
1684 0, /* bitpos */
1685 complain_overflow_bitfield,/* complain_on_overflow */
1686 bfd_elf_generic_reloc, /* special_function */
1687 "R_ARM_THM_TLS_DESCSEQ",/* name */
1688 FALSE, /* partial_inplace */
1689 0x00000000, /* src_mask */
1690 0x00000000, /* dst_mask */
1691 FALSE), /* pcrel_offset */
72d98d16
MG		 1692 EMPTY_HOWTO (130),
1693 EMPTY_HOWTO (131),
1694 HOWTO (R_ARM_THM_ALU_ABS_G0_NC,/* type. */
1695 0, /* rightshift. */
1696 1, /* size (0 = byte, 1 = short, 2 = long). */
1697 16, /* bitsize. */
1698 FALSE, /* pc_relative. */
1699 0, /* bitpos. */
1700 complain_overflow_bitfield,/* complain_on_overflow. */
1701 bfd_elf_generic_reloc, /* special_function. */
1702 "R_ARM_THM_ALU_ABS_G0_NC",/* name. */
1703 FALSE, /* partial_inplace. */
1704 0x00000000, /* src_mask. */
1705 0x00000000, /* dst_mask. */
1706 FALSE), /* pcrel_offset. */
1707 HOWTO (R_ARM_THM_ALU_ABS_G1_NC,/* type. */
1708 0, /* rightshift. */
1709 1, /* size (0 = byte, 1 = short, 2 = long). */
1710 16, /* bitsize. */
1711 FALSE, /* pc_relative. */
1712 0, /* bitpos. */
1713 complain_overflow_bitfield,/* complain_on_overflow. */
1714 bfd_elf_generic_reloc, /* special_function. */
1715 "R_ARM_THM_ALU_ABS_G1_NC",/* name. */
1716 FALSE, /* partial_inplace. */
1717 0x00000000, /* src_mask. */
1718 0x00000000, /* dst_mask. */
1719 FALSE), /* pcrel_offset. */
1720 HOWTO (R_ARM_THM_ALU_ABS_G2_NC,/* type. */
1721 0, /* rightshift. */
1722 1, /* size (0 = byte, 1 = short, 2 = long). */
1723 16, /* bitsize. */
1724 FALSE, /* pc_relative. */
1725 0, /* bitpos. */
1726 complain_overflow_bitfield,/* complain_on_overflow. */
1727 bfd_elf_generic_reloc, /* special_function. */
1728 "R_ARM_THM_ALU_ABS_G2_NC",/* name. */
1729 FALSE, /* partial_inplace. */
1730 0x00000000, /* src_mask. */
1731 0x00000000, /* dst_mask. */
1732 FALSE), /* pcrel_offset. */
1733 HOWTO (R_ARM_THM_ALU_ABS_G3_NC,/* type. */
1734 0, /* rightshift. */
1735 1, /* size (0 = byte, 1 = short, 2 = long). */
1736 16, /* bitsize. */
1737 FALSE, /* pc_relative. */
1738 0, /* bitpos. */
1739 complain_overflow_bitfield,/* complain_on_overflow. */
1740 bfd_elf_generic_reloc, /* special_function. */
1741 "R_ARM_THM_ALU_ABS_G3_NC",/* name. */
1742 FALSE, /* partial_inplace. */
1743 0x00000000, /* src_mask. */
1744 0x00000000, /* dst_mask. */
1745 FALSE), /* pcrel_offset. */
c19d1205
ZW		 1746};
1747
34e77a92
RS		 1748/* 160 onwards: */
1749static reloc_howto_type elf32_arm_howto_table_2[1] =
1750{
1751 HOWTO (R_ARM_IRELATIVE, /* type */
99059e56
RM		 1752 0, /* rightshift */
1753 2, /* size (0 = byte, 1 = short, 2 = long) */
1754 32, /* bitsize */
1755 FALSE, /* pc_relative */
1756 0, /* bitpos */
1757 complain_overflow_bitfield,/* complain_on_overflow */
1758 bfd_elf_generic_reloc, /* special_function */
1759 "R_ARM_IRELATIVE", /* name */
1760 TRUE, /* partial_inplace */
1761 0xffffffff, /* src_mask */
1762 0xffffffff, /* dst_mask */
1763 FALSE) /* pcrel_offset */
34e77a92 1764};
c19d1205 1765
34e77a92
RS		 1766/* 249-255 extended, currently unused, relocations: */
1767static reloc_howto_type elf32_arm_howto_table_3[4] =
7f266840
DJ		 1768{
1769 HOWTO (R_ARM_RREL32, /* type */
1770 0, /* rightshift */
1771 0, /* size (0 = byte, 1 = short, 2 = long) */
1772 0, /* bitsize */
1773 FALSE, /* pc_relative */
1774 0, /* bitpos */
1775 complain_overflow_dont,/* complain_on_overflow */
1776 bfd_elf_generic_reloc, /* special_function */
1777 "R_ARM_RREL32", /* name */
1778 FALSE, /* partial_inplace */
1779 0, /* src_mask */
1780 0, /* dst_mask */
1781 FALSE), /* pcrel_offset */
1782
1783 HOWTO (R_ARM_RABS32, /* type */
1784 0, /* rightshift */
1785 0, /* size (0 = byte, 1 = short, 2 = long) */
1786 0, /* bitsize */
1787 FALSE, /* pc_relative */
1788 0, /* bitpos */
1789 complain_overflow_dont,/* complain_on_overflow */
1790 bfd_elf_generic_reloc, /* special_function */
1791 "R_ARM_RABS32", /* name */
1792 FALSE, /* partial_inplace */
1793 0, /* src_mask */
1794 0, /* dst_mask */
1795 FALSE), /* pcrel_offset */
1796
1797 HOWTO (R_ARM_RPC24, /* type */
1798 0, /* rightshift */
1799 0, /* size (0 = byte, 1 = short, 2 = long) */
1800 0, /* bitsize */
1801 FALSE, /* pc_relative */
1802 0, /* bitpos */
1803 complain_overflow_dont,/* complain_on_overflow */
1804 bfd_elf_generic_reloc, /* special_function */
1805 "R_ARM_RPC24", /* name */
1806 FALSE, /* partial_inplace */
1807 0, /* src_mask */
1808 0, /* dst_mask */
1809 FALSE), /* pcrel_offset */
1810
1811 HOWTO (R_ARM_RBASE, /* type */
1812 0, /* rightshift */
1813 0, /* size (0 = byte, 1 = short, 2 = long) */
1814 0, /* bitsize */
1815 FALSE, /* pc_relative */
1816 0, /* bitpos */
1817 complain_overflow_dont,/* complain_on_overflow */
1818 bfd_elf_generic_reloc, /* special_function */
1819 "R_ARM_RBASE", /* name */
1820 FALSE, /* partial_inplace */
1821 0, /* src_mask */
1822 0, /* dst_mask */
1823 FALSE) /* pcrel_offset */
1824};
1825
1826static reloc_howto_type *
1827elf32_arm_howto_from_type (unsigned int r_type)
1828{
906e58ca 1829 if (r_type < ARRAY_SIZE (elf32_arm_howto_table_1))
c19d1205 1830 return &elf32_arm_howto_table_1[r_type];
ba93b8ac 1831
34e77a92
RS		 1832 if (r_type == R_ARM_IRELATIVE)
1833 return &elf32_arm_howto_table_2[r_type - R_ARM_IRELATIVE];
1834
c19d1205 1835 if (r_type >= R_ARM_RREL32
34e77a92
RS		 1836 && r_type < R_ARM_RREL32 + ARRAY_SIZE (elf32_arm_howto_table_3))
1837 return &elf32_arm_howto_table_3[r_type - R_ARM_RREL32];
7f266840 1838
c19d1205 1839 return NULL;
7f266840
DJ		 1840}
1841
1842static void
1843elf32_arm_info_to_howto (bfd * abfd ATTRIBUTE_UNUSED, arelent * bfd_reloc,
1844 Elf_Internal_Rela * elf_reloc)
1845{
1846 unsigned int r_type;
1847
1848 r_type = ELF32_R_TYPE (elf_reloc->r_info);
1849 bfd_reloc->howto = elf32_arm_howto_from_type (r_type);
1850}
1851
1852struct elf32_arm_reloc_map
1853 {
1854 bfd_reloc_code_real_type bfd_reloc_val;
1855 unsigned char elf_reloc_val;
1856 };
1857
1858/* All entries in this list must also be present in elf32_arm_howto_table. */
1859static const struct elf32_arm_reloc_map elf32_arm_reloc_map[] =
1860 {
1861 {BFD_RELOC_NONE, R_ARM_NONE},
1862 {BFD_RELOC_ARM_PCREL_BRANCH, R_ARM_PC24},
39b41c9c
PB		 1863 {BFD_RELOC_ARM_PCREL_CALL, R_ARM_CALL},
1864 {BFD_RELOC_ARM_PCREL_JUMP, R_ARM_JUMP24},
7f266840
DJ		 1865 {BFD_RELOC_ARM_PCREL_BLX, R_ARM_XPC25},
1866 {BFD_RELOC_THUMB_PCREL_BLX, R_ARM_THM_XPC22},
1867 {BFD_RELOC_32, R_ARM_ABS32},
1868 {BFD_RELOC_32_PCREL, R_ARM_REL32},
1869 {BFD_RELOC_8, R_ARM_ABS8},
1870 {BFD_RELOC_16, R_ARM_ABS16},
1871 {BFD_RELOC_ARM_OFFSET_IMM, R_ARM_ABS12},
1872 {BFD_RELOC_ARM_THUMB_OFFSET, R_ARM_THM_ABS5},
c19d1205
ZW		 1873 {BFD_RELOC_THUMB_PCREL_BRANCH25, R_ARM_THM_JUMP24},
1874 {BFD_RELOC_THUMB_PCREL_BRANCH23, R_ARM_THM_CALL},
1875 {BFD_RELOC_THUMB_PCREL_BRANCH12, R_ARM_THM_JUMP11},
1876 {BFD_RELOC_THUMB_PCREL_BRANCH20, R_ARM_THM_JUMP19},
1877 {BFD_RELOC_THUMB_PCREL_BRANCH9, R_ARM_THM_JUMP8},
1878 {BFD_RELOC_THUMB_PCREL_BRANCH7, R_ARM_THM_JUMP6},
7f266840
DJ		 1879 {BFD_RELOC_ARM_GLOB_DAT, R_ARM_GLOB_DAT},
1880 {BFD_RELOC_ARM_JUMP_SLOT, R_ARM_JUMP_SLOT},
1881 {BFD_RELOC_ARM_RELATIVE, R_ARM_RELATIVE},
c19d1205 1882 {BFD_RELOC_ARM_GOTOFF, R_ARM_GOTOFF32},
7f266840 1883 {BFD_RELOC_ARM_GOTPC, R_ARM_GOTPC},
b43420e6 1884 {BFD_RELOC_ARM_GOT_PREL, R_ARM_GOT_PREL},
7f266840
DJ		 1885 {BFD_RELOC_ARM_GOT32, R_ARM_GOT32},
1886 {BFD_RELOC_ARM_PLT32, R_ARM_PLT32},
1887 {BFD_RELOC_ARM_TARGET1, R_ARM_TARGET1},
1888 {BFD_RELOC_ARM_ROSEGREL32, R_ARM_ROSEGREL32},
1889 {BFD_RELOC_ARM_SBREL32, R_ARM_SBREL32},
1890 {BFD_RELOC_ARM_PREL31, R_ARM_PREL31},
ba93b8ac
DJ		 1891 {BFD_RELOC_ARM_TARGET2, R_ARM_TARGET2},
1892 {BFD_RELOC_ARM_PLT32, R_ARM_PLT32},
0855e32b
NS		 1893 {BFD_RELOC_ARM_TLS_GOTDESC, R_ARM_TLS_GOTDESC},
1894 {BFD_RELOC_ARM_TLS_CALL, R_ARM_TLS_CALL},
1895 {BFD_RELOC_ARM_THM_TLS_CALL, R_ARM_THM_TLS_CALL},
1896 {BFD_RELOC_ARM_TLS_DESCSEQ, R_ARM_TLS_DESCSEQ},
1897 {BFD_RELOC_ARM_THM_TLS_DESCSEQ, R_ARM_THM_TLS_DESCSEQ},
1898 {BFD_RELOC_ARM_TLS_DESC, R_ARM_TLS_DESC},
ba93b8ac
DJ		 1899 {BFD_RELOC_ARM_TLS_GD32, R_ARM_TLS_GD32},
1900 {BFD_RELOC_ARM_TLS_LDO32, R_ARM_TLS_LDO32},
1901 {BFD_RELOC_ARM_TLS_LDM32, R_ARM_TLS_LDM32},
1902 {BFD_RELOC_ARM_TLS_DTPMOD32, R_ARM_TLS_DTPMOD32},
1903 {BFD_RELOC_ARM_TLS_DTPOFF32, R_ARM_TLS_DTPOFF32},
1904 {BFD_RELOC_ARM_TLS_TPOFF32, R_ARM_TLS_TPOFF32},
1905 {BFD_RELOC_ARM_TLS_IE32, R_ARM_TLS_IE32},
1906 {BFD_RELOC_ARM_TLS_LE32, R_ARM_TLS_LE32},
34e77a92 1907 {BFD_RELOC_ARM_IRELATIVE, R_ARM_IRELATIVE},
c19d1205
ZW		 1908 {BFD_RELOC_VTABLE_INHERIT, R_ARM_GNU_VTINHERIT},
1909 {BFD_RELOC_VTABLE_ENTRY, R_ARM_GNU_VTENTRY},
b6895b4f
PB		 1910 {BFD_RELOC_ARM_MOVW, R_ARM_MOVW_ABS_NC},
1911 {BFD_RELOC_ARM_MOVT, R_ARM_MOVT_ABS},
1912 {BFD_RELOC_ARM_MOVW_PCREL, R_ARM_MOVW_PREL_NC},
1913 {BFD_RELOC_ARM_MOVT_PCREL, R_ARM_MOVT_PREL},
1914 {BFD_RELOC_ARM_THUMB_MOVW, R_ARM_THM_MOVW_ABS_NC},
1915 {BFD_RELOC_ARM_THUMB_MOVT, R_ARM_THM_MOVT_ABS},
1916 {BFD_RELOC_ARM_THUMB_MOVW_PCREL, R_ARM_THM_MOVW_PREL_NC},
1917 {BFD_RELOC_ARM_THUMB_MOVT_PCREL, R_ARM_THM_MOVT_PREL},
4962c51a
MS		 1918 {BFD_RELOC_ARM_ALU_PC_G0_NC, R_ARM_ALU_PC_G0_NC},
1919 {BFD_RELOC_ARM_ALU_PC_G0, R_ARM_ALU_PC_G0},
1920 {BFD_RELOC_ARM_ALU_PC_G1_NC, R_ARM_ALU_PC_G1_NC},
1921 {BFD_RELOC_ARM_ALU_PC_G1, R_ARM_ALU_PC_G1},
1922 {BFD_RELOC_ARM_ALU_PC_G2, R_ARM_ALU_PC_G2},
1923 {BFD_RELOC_ARM_LDR_PC_G0, R_ARM_LDR_PC_G0},
1924 {BFD_RELOC_ARM_LDR_PC_G1, R_ARM_LDR_PC_G1},
1925 {BFD_RELOC_ARM_LDR_PC_G2, R_ARM_LDR_PC_G2},
1926 {BFD_RELOC_ARM_LDRS_PC_G0, R_ARM_LDRS_PC_G0},
1927 {BFD_RELOC_ARM_LDRS_PC_G1, R_ARM_LDRS_PC_G1},
1928 {BFD_RELOC_ARM_LDRS_PC_G2, R_ARM_LDRS_PC_G2},
1929 {BFD_RELOC_ARM_LDC_PC_G0, R_ARM_LDC_PC_G0},
1930 {BFD_RELOC_ARM_LDC_PC_G1, R_ARM_LDC_PC_G1},
1931 {BFD_RELOC_ARM_LDC_PC_G2, R_ARM_LDC_PC_G2},
1932 {BFD_RELOC_ARM_ALU_SB_G0_NC, R_ARM_ALU_SB_G0_NC},
1933 {BFD_RELOC_ARM_ALU_SB_G0, R_ARM_ALU_SB_G0},
1934 {BFD_RELOC_ARM_ALU_SB_G1_NC, R_ARM_ALU_SB_G1_NC},
1935 {BFD_RELOC_ARM_ALU_SB_G1, R_ARM_ALU_SB_G1},
1936 {BFD_RELOC_ARM_ALU_SB_G2, R_ARM_ALU_SB_G2},
1937 {BFD_RELOC_ARM_LDR_SB_G0, R_ARM_LDR_SB_G0},
1938 {BFD_RELOC_ARM_LDR_SB_G1, R_ARM_LDR_SB_G1},
1939 {BFD_RELOC_ARM_LDR_SB_G2, R_ARM_LDR_SB_G2},
1940 {BFD_RELOC_ARM_LDRS_SB_G0, R_ARM_LDRS_SB_G0},
1941 {BFD_RELOC_ARM_LDRS_SB_G1, R_ARM_LDRS_SB_G1},
1942 {BFD_RELOC_ARM_LDRS_SB_G2, R_ARM_LDRS_SB_G2},
1943 {BFD_RELOC_ARM_LDC_SB_G0, R_ARM_LDC_SB_G0},
1944 {BFD_RELOC_ARM_LDC_SB_G1, R_ARM_LDC_SB_G1},
845b51d6 1945 {BFD_RELOC_ARM_LDC_SB_G2, R_ARM_LDC_SB_G2},
72d98d16
MG		 1946 {BFD_RELOC_ARM_V4BX, R_ARM_V4BX},
1947 {BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC, R_ARM_THM_ALU_ABS_G3_NC},
1948 {BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC, R_ARM_THM_ALU_ABS_G2_NC},
1949 {BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC, R_ARM_THM_ALU_ABS_G1_NC},
1950 {BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC, R_ARM_THM_ALU_ABS_G0_NC}
7f266840
DJ		 1951 };
1952
1953static reloc_howto_type *
f1c71a59
ZW		 1954elf32_arm_reloc_type_lookup (bfd *abfd ATTRIBUTE_UNUSED,
1955 bfd_reloc_code_real_type code)
7f266840
DJ		 1956{
1957 unsigned int i;
8029a119 1958
906e58ca 1959 for (i = 0; i < ARRAY_SIZE (elf32_arm_reloc_map); i ++)
c19d1205
ZW		 1960 if (elf32_arm_reloc_map[i].bfd_reloc_val == code)
1961 return elf32_arm_howto_from_type (elf32_arm_reloc_map[i].elf_reloc_val);
7f266840 1962
c19d1205 1963 return NULL;
7f266840
DJ		 1964}
1965
157090f7
AM		 1966static reloc_howto_type *
1967elf32_arm_reloc_name_lookup (bfd *abfd ATTRIBUTE_UNUSED,
1968 const char *r_name)
1969{
1970 unsigned int i;
1971
906e58ca 1972 for (i = 0; i < ARRAY_SIZE (elf32_arm_howto_table_1); i++)
157090f7
AM		 1973 if (elf32_arm_howto_table_1[i].name != NULL
1974 && strcasecmp (elf32_arm_howto_table_1[i].name, r_name) == 0)
1975 return &elf32_arm_howto_table_1[i];
1976
906e58ca 1977 for (i = 0; i < ARRAY_SIZE (elf32_arm_howto_table_2); i++)
157090f7
AM		 1978 if (elf32_arm_howto_table_2[i].name != NULL
1979 && strcasecmp (elf32_arm_howto_table_2[i].name, r_name) == 0)
1980 return &elf32_arm_howto_table_2[i];
1981
34e77a92
RS		 1982 for (i = 0; i < ARRAY_SIZE (elf32_arm_howto_table_3); i++)
1983 if (elf32_arm_howto_table_3[i].name != NULL
1984 && strcasecmp (elf32_arm_howto_table_3[i].name, r_name) == 0)
1985 return &elf32_arm_howto_table_3[i];
1986
157090f7
AM		 1987 return NULL;
1988}
1989
906e58ca
NC		 1990/* Support for core dump NOTE sections. */
1991
7f266840 1992static bfd_boolean
f1c71a59 1993elf32_arm_nabi_grok_prstatus (bfd *abfd, Elf_Internal_Note *note)
7f266840
DJ		 1994{
1995 int offset;
1996 size_t size;
1997
1998 switch (note->descsz)
1999 {
2000 default:
2001 return FALSE;
2002
8029a119 2003 case 148: /* Linux/ARM 32-bit. */
7f266840 2004 /* pr_cursig */
228e534f 2005 elf_tdata (abfd)->core->signal = bfd_get_16 (abfd, note->descdata + 12);
7f266840
DJ		 2006
2007 /* pr_pid */
228e534f 2008 elf_tdata (abfd)->core->lwpid = bfd_get_32 (abfd, note->descdata + 24);
7f266840
DJ		 2009
2010 /* pr_reg */
2011 offset = 72;
2012 size = 72;
2013
2014 break;
2015 }
2016
2017 /* Make a ".reg/999" section. */
2018 return _bfd_elfcore_make_pseudosection (abfd, ".reg",
2019 size, note->descpos + offset);
2020}
2021
2022static bfd_boolean
f1c71a59 2023elf32_arm_nabi_grok_psinfo (bfd *abfd, Elf_Internal_Note *note)
7f266840
DJ		 2024{
2025 switch (note->descsz)
2026 {
2027 default:
2028 return FALSE;
2029
8029a119 2030 case 124: /* Linux/ARM elf_prpsinfo. */
228e534f 2031 elf_tdata (abfd)->core->pid
4395ee08 2032 = bfd_get_32 (abfd, note->descdata + 12);
228e534f 2033 elf_tdata (abfd)->core->program
7f266840 2034 = _bfd_elfcore_strndup (abfd, note->descdata + 28, 16);
228e534f 2035 elf_tdata (abfd)->core->command
7f266840
DJ		 2036 = _bfd_elfcore_strndup (abfd, note->descdata + 44, 80);
2037 }
2038
2039 /* Note that for some reason, a spurious space is tacked
2040 onto the end of the args in some (at least one anyway)
2041 implementations, so strip it off if it exists. */
7f266840 2042 {
228e534f 2043 char *command = elf_tdata (abfd)->core->command;
7f266840
DJ		 2044 int n = strlen (command);
2045
2046 if (0 < n && command[n - 1] == ' ')
2047 command[n - 1] = '\0';
2048 }
2049
2050 return TRUE;
2051}
2052
1f20dca5
UW		 2053static char *
2054elf32_arm_nabi_write_core_note (bfd *abfd, char *buf, int *bufsiz,
2055 int note_type, ...)
2056{
2057 switch (note_type)
2058 {
2059 default:
2060 return NULL;
2061
2062 case NT_PRPSINFO:
2063 {
2064 char data[124];
2065 va_list ap;
2066
2067 va_start (ap, note_type);
2068 memset (data, 0, sizeof (data));
2069 strncpy (data + 28, va_arg (ap, const char *), 16);
2070 strncpy (data + 44, va_arg (ap, const char *), 80);
2071 va_end (ap);
2072
2073 return elfcore_write_note (abfd, buf, bufsiz,
2074 "CORE", note_type, data, sizeof (data));
2075 }
2076
2077 case NT_PRSTATUS:
2078 {
2079 char data[148];
2080 va_list ap;
2081 long pid;
2082 int cursig;
2083 const void *greg;
2084
2085 va_start (ap, note_type);
2086 memset (data, 0, sizeof (data));
2087 pid = va_arg (ap, long);
2088 bfd_put_32 (abfd, pid, data + 24);
2089 cursig = va_arg (ap, int);
2090 bfd_put_16 (abfd, cursig, data + 12);
2091 greg = va_arg (ap, const void *);
2092 memcpy (data + 72, greg, 72);
2093 va_end (ap);
2094
2095 return elfcore_write_note (abfd, buf, bufsiz,
2096 "CORE", note_type, data, sizeof (data));
2097 }
2098 }
2099}
2100
6d00b590 2101#define TARGET_LITTLE_SYM arm_elf32_le_vec
7f266840 2102#define TARGET_LITTLE_NAME "elf32-littlearm"
6d00b590 2103#define TARGET_BIG_SYM arm_elf32_be_vec
7f266840
DJ		 2104#define TARGET_BIG_NAME "elf32-bigarm"
2105
2106#define elf_backend_grok_prstatus elf32_arm_nabi_grok_prstatus
2107#define elf_backend_grok_psinfo elf32_arm_nabi_grok_psinfo
1f20dca5 2108#define elf_backend_write_core_note elf32_arm_nabi_write_core_note
7f266840 2109
252b5132
RH		 2110typedef unsigned long int insn32;
2111typedef unsigned short int insn16;
2112
3a4a14e9
PB		 2113/* In lieu of proper flags, assume all EABIv4 or later objects are
2114 interworkable. */
57e8b36a 2115#define INTERWORK_FLAG(abfd) \
3a4a14e9 2116 (EF_ARM_EABI_VERSION (elf_elfheader (abfd)->e_flags) >= EF_ARM_EABI_VER4 \
3e6b1042
DJ		 2117 || (elf_elfheader (abfd)->e_flags & EF_ARM_INTERWORK) \
2118 || ((abfd)->flags & BFD_LINKER_CREATED))
9b485d32 2119
252b5132
RH		 2120/* The linker script knows the section names for placement.
2121 The entry_names are used to do simple name mangling on the stubs.
2122 Given a function name, and its type, the stub can be found. The
9b485d32 2123 name can be changed. The only requirement is the %s be present. */
252b5132
RH		 2124#define THUMB2ARM_GLUE_SECTION_NAME ".glue_7t"
2125#define THUMB2ARM_GLUE_ENTRY_NAME "__%s_from_thumb"
2126
2127#define ARM2THUMB_GLUE_SECTION_NAME ".glue_7"
2128#define ARM2THUMB_GLUE_ENTRY_NAME "__%s_from_arm"
2129
c7b8f16e
JB		 2130#define VFP11_ERRATUM_VENEER_SECTION_NAME ".vfp11_veneer"
2131#define VFP11_ERRATUM_VENEER_ENTRY_NAME "__vfp11_veneer_%x"
2132
a504d23a
LA		 2133#define STM32L4XX_ERRATUM_VENEER_SECTION_NAME ".text.stm32l4xx_veneer"
2134#define STM32L4XX_ERRATUM_VENEER_ENTRY_NAME "__stm32l4xx_veneer_%x"
2135
845b51d6
PB		 2136#define ARM_BX_GLUE_SECTION_NAME ".v4_bx"
2137#define ARM_BX_GLUE_ENTRY_NAME "__bx_r%d"
2138
7413f23f
DJ		 2139#define STUB_ENTRY_NAME "__%s_veneer"
2140
4ba2ef8f
TP		 2141#define CMSE_PREFIX "__acle_se_"
2142
252b5132
RH		 2143/* The name of the dynamic interpreter. This is put in the .interp
2144 section. */
2145#define ELF_DYNAMIC_INTERPRETER "/usr/lib/ld.so.1"
2146
0855e32b 2147static const unsigned long tls_trampoline [] =
b38cadfb
NC		 2148{
2149 0xe08e0000, /* add r0, lr, r0 */
2150 0xe5901004, /* ldr r1, [r0,#4] */
2151 0xe12fff11, /* bx r1 */
2152};
0855e32b
NS		 2153
2154static const unsigned long dl_tlsdesc_lazy_trampoline [] =
b38cadfb
NC		 2155{
2156 0xe52d2004, /* push {r2} */
2157 0xe59f200c, /* ldr r2, [pc, #3f - . - 8] */
2158 0xe59f100c, /* ldr r1, [pc, #4f - . - 8] */
2159 0xe79f2002, /* 1: ldr r2, [pc, r2] */
2160 0xe081100f, /* 2: add r1, pc */
2161 0xe12fff12, /* bx r2 */
2162 0x00000014, /* 3: .word _GLOBAL_OFFSET_TABLE_ - 1b - 8
99059e56 2163 + dl_tlsdesc_lazy_resolver(GOT) */
b38cadfb
NC		 2164 0x00000018, /* 4: .word _GLOBAL_OFFSET_TABLE_ - 2b - 8 */
2165};
0855e32b 2166
5e681ec4
PB		 2167#ifdef FOUR_WORD_PLT
2168
252b5132
RH		 2169/* The first entry in a procedure linkage table looks like
2170 this. It is set up so that any shared library function that is
59f2c4e7 2171 called before the relocation has been set up calls the dynamic
9b485d32 2172 linker first. */
e5a52504 2173static const bfd_vma elf32_arm_plt0_entry [] =
b38cadfb
NC		 2174{
2175 0xe52de004, /* str lr, [sp, #-4]! */
2176 0xe59fe010, /* ldr lr, [pc, #16] */
2177 0xe08fe00e, /* add lr, pc, lr */
2178 0xe5bef008, /* ldr pc, [lr, #8]! */
2179};
5e681ec4
PB		 2180
2181/* Subsequent entries in a procedure linkage table look like
2182 this. */
e5a52504 2183static const bfd_vma elf32_arm_plt_entry [] =
b38cadfb
NC		 2184{
2185 0xe28fc600, /* add ip, pc, #NN */
2186 0xe28cca00, /* add ip, ip, #NN */
2187 0xe5bcf000, /* ldr pc, [ip, #NN]! */
2188 0x00000000, /* unused */
2189};
5e681ec4 2190
eed94f8f 2191#else /* not FOUR_WORD_PLT */
5e681ec4 2192
5e681ec4
PB		 2193/* The first entry in a procedure linkage table looks like
2194 this. It is set up so that any shared library function that is
2195 called before the relocation has been set up calls the dynamic
2196 linker first. */
e5a52504 2197static const bfd_vma elf32_arm_plt0_entry [] =
b38cadfb
NC		 2198{
2199 0xe52de004, /* str lr, [sp, #-4]! */
2200 0xe59fe004, /* ldr lr, [pc, #4] */
2201 0xe08fe00e, /* add lr, pc, lr */
2202 0xe5bef008, /* ldr pc, [lr, #8]! */
2203 0x00000000, /* &GOT[0] - . */
2204};
252b5132 2205
1db37fe6
YG		 2206/* By default subsequent entries in a procedure linkage table look like
2207 this. Offsets that don't fit into 28 bits will cause link error. */
2208static const bfd_vma elf32_arm_plt_entry_short [] =
b38cadfb
NC		 2209{
2210 0xe28fc600, /* add ip, pc, #0xNN00000 */
2211 0xe28cca00, /* add ip, ip, #0xNN000 */
2212 0xe5bcf000, /* ldr pc, [ip, #0xNNN]! */
2213};
5e681ec4 2214
1db37fe6
YG		 2215/* When explicitly asked, we'll use this "long" entry format
2216 which can cope with arbitrary displacements. */
2217static const bfd_vma elf32_arm_plt_entry_long [] =
2218{
2219 0xe28fc200, /* add ip, pc, #0xN0000000 */
2220 0xe28cc600, /* add ip, ip, #0xNN00000 */
2221 0xe28cca00, /* add ip, ip, #0xNN000 */
2222 0xe5bcf000, /* ldr pc, [ip, #0xNNN]! */
2223};
2224
2225static bfd_boolean elf32_arm_use_long_plt_entry = FALSE;
2226
eed94f8f
NC		 2227#endif /* not FOUR_WORD_PLT */
2228
2229/* The first entry in a procedure linkage table looks like this.
2230 It is set up so that any shared library function that is called before the
2231 relocation has been set up calls the dynamic linker first. */
2232static const bfd_vma elf32_thumb2_plt0_entry [] =
2233{
2234 /* NOTE: As this is a mixture of 16-bit and 32-bit instructions,
2235 an instruction maybe encoded to one or two array elements. */
2236 0xf8dfb500, /* push {lr} */
2237 0x44fee008, /* ldr.w lr, [pc, #8] */
469a3493 2238 /* add lr, pc */
eed94f8f
NC		 2239 0xff08f85e, /* ldr.w pc, [lr, #8]! */
2240 0x00000000, /* &GOT[0] - . */
2241};
2242
2243/* Subsequent entries in a procedure linkage table for thumb only target
2244 look like this. */
2245static const bfd_vma elf32_thumb2_plt_entry [] =
2246{
2247 /* NOTE: As this is a mixture of 16-bit and 32-bit instructions,
2248 an instruction maybe encoded to one or two array elements. */
2249 0x0c00f240, /* movw ip, #0xNNNN */
2250 0x0c00f2c0, /* movt ip, #0xNNNN */
2251 0xf8dc44fc, /* add ip, pc */
2252 0xbf00f000 /* ldr.w pc, [ip] */
469a3493 2253 /* nop */
eed94f8f 2254};
252b5132 2255
00a97672
RS		 2256/* The format of the first entry in the procedure linkage table
2257 for a VxWorks executable. */
2258static const bfd_vma elf32_arm_vxworks_exec_plt0_entry[] =
b38cadfb
NC		 2259{
2260 0xe52dc008, /* str ip,[sp,#-8]! */
2261 0xe59fc000, /* ldr ip,[pc] */
2262 0xe59cf008, /* ldr pc,[ip,#8] */
2263 0x00000000, /* .long _GLOBAL_OFFSET_TABLE_ */
2264};
00a97672
RS		 2265
2266/* The format of subsequent entries in a VxWorks executable. */
2267static const bfd_vma elf32_arm_vxworks_exec_plt_entry[] =
b38cadfb
NC		 2268{
2269 0xe59fc000, /* ldr ip,[pc] */
2270 0xe59cf000, /* ldr pc,[ip] */
2271 0x00000000, /* .long @got */
2272 0xe59fc000, /* ldr ip,[pc] */
2273 0xea000000, /* b _PLT */
2274 0x00000000, /* .long @pltindex*sizeof(Elf32_Rela) */
2275};
00a97672
RS		 2276
2277/* The format of entries in a VxWorks shared library. */
2278static const bfd_vma elf32_arm_vxworks_shared_plt_entry[] =
b38cadfb
NC		 2279{
2280 0xe59fc000, /* ldr ip,[pc] */
2281 0xe79cf009, /* ldr pc,[ip,r9] */
2282 0x00000000, /* .long @got */
2283 0xe59fc000, /* ldr ip,[pc] */
2284 0xe599f008, /* ldr pc,[r9,#8] */
2285 0x00000000, /* .long @pltindex*sizeof(Elf32_Rela) */
2286};
00a97672 2287
b7693d02
DJ		 2288/* An initial stub used if the PLT entry is referenced from Thumb code. */
2289#define PLT_THUMB_STUB_SIZE 4
2290static const bfd_vma elf32_arm_plt_thumb_stub [] =
b38cadfb
NC		 2291{
2292 0x4778, /* bx pc */
2293 0x46c0 /* nop */
2294};
b7693d02 2295
e5a52504
MM		 2296/* The entries in a PLT when using a DLL-based target with multiple
2297 address spaces. */
906e58ca 2298static const bfd_vma elf32_arm_symbian_plt_entry [] =
b38cadfb
NC		 2299{
2300 0xe51ff004, /* ldr pc, [pc, #-4] */
2301 0x00000000, /* dcd R_ARM_GLOB_DAT(X) */
2302};
2303
2304/* The first entry in a procedure linkage table looks like
2305 this. It is set up so that any shared library function that is
2306 called before the relocation has been set up calls the dynamic
2307 linker first. */
2308static const bfd_vma elf32_arm_nacl_plt0_entry [] =
2309{
2310 /* First bundle: */
2311 0xe300c000, /* movw ip, #:lower16:&GOT[2]-.+8 */
2312 0xe340c000, /* movt ip, #:upper16:&GOT[2]-.+8 */
2313 0xe08cc00f, /* add ip, ip, pc */
2314 0xe52dc008, /* str ip, [sp, #-8]! */
2315 /* Second bundle: */
edccdf7c
RM		 2316 0xe3ccc103, /* bic ip, ip, #0xc0000000 */
2317 0xe59cc000, /* ldr ip, [ip] */
b38cadfb 2318 0xe3ccc13f, /* bic ip, ip, #0xc000000f */
edccdf7c 2319 0xe12fff1c, /* bx ip */
b38cadfb 2320 /* Third bundle: */
edccdf7c
RM		 2321 0xe320f000, /* nop */
2322 0xe320f000, /* nop */
2323 0xe320f000, /* nop */
b38cadfb
NC		 2324 /* .Lplt_tail: */
2325 0xe50dc004, /* str ip, [sp, #-4] */
2326 /* Fourth bundle: */
edccdf7c
RM		 2327 0xe3ccc103, /* bic ip, ip, #0xc0000000 */
2328 0xe59cc000, /* ldr ip, [ip] */
b38cadfb 2329 0xe3ccc13f, /* bic ip, ip, #0xc000000f */
edccdf7c 2330 0xe12fff1c, /* bx ip */
b38cadfb
NC		 2331};
2332#define ARM_NACL_PLT_TAIL_OFFSET (11 * 4)
2333
2334/* Subsequent entries in a procedure linkage table look like this. */
2335static const bfd_vma elf32_arm_nacl_plt_entry [] =
2336{
2337 0xe300c000, /* movw ip, #:lower16:&GOT[n]-.+8 */
2338 0xe340c000, /* movt ip, #:upper16:&GOT[n]-.+8 */
2339 0xe08cc00f, /* add ip, ip, pc */
2340 0xea000000, /* b .Lplt_tail */
2341};
e5a52504 2342
906e58ca
NC		 2343#define ARM_MAX_FWD_BRANCH_OFFSET ((((1 << 23) - 1) << 2) + 8)
2344#define ARM_MAX_BWD_BRANCH_OFFSET ((-((1 << 23) << 2)) + 8)
2345#define THM_MAX_FWD_BRANCH_OFFSET ((1 << 22) -2 + 4)
2346#define THM_MAX_BWD_BRANCH_OFFSET (-(1 << 22) + 4)
2347#define THM2_MAX_FWD_BRANCH_OFFSET (((1 << 24) - 2) + 4)
2348#define THM2_MAX_BWD_BRANCH_OFFSET (-(1 << 24) + 4)
c5423981
TG		 2349#define THM2_MAX_FWD_COND_BRANCH_OFFSET (((1 << 20) -2) + 4)
2350#define THM2_MAX_BWD_COND_BRANCH_OFFSET (-(1 << 20) + 4)
906e58ca 2351
461a49ca 2352enum stub_insn_type
b38cadfb
NC		 2353{
2354 THUMB16_TYPE = 1,
2355 THUMB32_TYPE,
2356 ARM_TYPE,
2357 DATA_TYPE
2358};
461a49ca 2359
48229727
JB		 2360#define THUMB16_INSN(X) {(X), THUMB16_TYPE, R_ARM_NONE, 0}
2361/* A bit of a hack. A Thumb conditional branch, in which the proper condition
2362 is inserted in arm_build_one_stub(). */
2363#define THUMB16_BCOND_INSN(X) {(X), THUMB16_TYPE, R_ARM_NONE, 1}
2364#define THUMB32_INSN(X) {(X), THUMB32_TYPE, R_ARM_NONE, 0}
d5a67c02
AV		 2365#define THUMB32_MOVT(X) {(X), THUMB32_TYPE, R_ARM_THM_MOVT_ABS, 0}
2366#define THUMB32_MOVW(X) {(X), THUMB32_TYPE, R_ARM_THM_MOVW_ABS_NC, 0}
48229727
JB		 2367#define THUMB32_B_INSN(X, Z) {(X), THUMB32_TYPE, R_ARM_THM_JUMP24, (Z)}
2368#define ARM_INSN(X) {(X), ARM_TYPE, R_ARM_NONE, 0}
2369#define ARM_REL_INSN(X, Z) {(X), ARM_TYPE, R_ARM_JUMP24, (Z)}
2370#define DATA_WORD(X,Y,Z) {(X), DATA_TYPE, (Y), (Z)}
461a49ca
DJ		 2371
2372typedef struct
2373{
b38cadfb
NC		 2374 bfd_vma data;
2375 enum stub_insn_type type;
2376 unsigned int r_type;
2377 int reloc_addend;
461a49ca
DJ		 2378} insn_sequence;
2379
fea2b4d6
CL		 2380/* Arm/Thumb -> Arm/Thumb long branch stub. On V5T and above, use blx
2381 to reach the stub if necessary. */
461a49ca 2382static const insn_sequence elf32_arm_stub_long_branch_any_any[] =
b38cadfb
NC		 2383{
2384 ARM_INSN (0xe51ff004), /* ldr pc, [pc, #-4] */
2385 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(X) */
2386};
906e58ca 2387
fea2b4d6
CL		 2388/* V4T Arm -> Thumb long branch stub. Used on V4T where blx is not
2389 available. */
461a49ca 2390static const insn_sequence elf32_arm_stub_long_branch_v4t_arm_thumb[] =
b38cadfb
NC		 2391{
2392 ARM_INSN (0xe59fc000), /* ldr ip, [pc, #0] */
2393 ARM_INSN (0xe12fff1c), /* bx ip */
2394 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(X) */
2395};
906e58ca 2396
d3626fb0 2397/* Thumb -> Thumb long branch stub. Used on M-profile architectures. */
461a49ca 2398static const insn_sequence elf32_arm_stub_long_branch_thumb_only[] =
b38cadfb
NC		 2399{
2400 THUMB16_INSN (0xb401), /* push {r0} */
2401 THUMB16_INSN (0x4802), /* ldr r0, [pc, #8] */
2402 THUMB16_INSN (0x4684), /* mov ip, r0 */
2403 THUMB16_INSN (0xbc01), /* pop {r0} */
2404 THUMB16_INSN (0x4760), /* bx ip */
2405 THUMB16_INSN (0xbf00), /* nop */
2406 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(X) */
2407};
906e58ca 2408
80c135e5
TP		 2409/* Thumb -> Thumb long branch stub in thumb2 encoding. Used on armv7. */
2410static const insn_sequence elf32_arm_stub_long_branch_thumb2_only[] =
2411{
2412 THUMB32_INSN (0xf85ff000), /* ldr.w pc, [pc, #-0] */
2413 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(x) */
2414};
2415
d5a67c02
AV		 2416/* Thumb -> Thumb long branch stub. Used for PureCode sections on Thumb2
2417 M-profile architectures. */
2418static const insn_sequence elf32_arm_stub_long_branch_thumb2_only_pure[] =
2419{
2420 THUMB32_MOVW (0xf2400c00), /* mov.w ip, R_ARM_MOVW_ABS_NC */
2421 THUMB32_MOVT (0xf2c00c00), /* movt ip, R_ARM_MOVT_ABS << 16 */
2422 THUMB16_INSN (0x4760), /* bx ip */
2423};
2424
d3626fb0
CL		 2425/* V4T Thumb -> Thumb long branch stub. Using the stack is not
2426 allowed. */
2427static const insn_sequence elf32_arm_stub_long_branch_v4t_thumb_thumb[] =
b38cadfb
NC		 2428{
2429 THUMB16_INSN (0x4778), /* bx pc */
2430 THUMB16_INSN (0x46c0), /* nop */
2431 ARM_INSN (0xe59fc000), /* ldr ip, [pc, #0] */
2432 ARM_INSN (0xe12fff1c), /* bx ip */
2433 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(X) */
2434};
d3626fb0 2435
fea2b4d6
CL		 2436/* V4T Thumb -> ARM long branch stub. Used on V4T where blx is not
2437 available. */
461a49ca 2438static const insn_sequence elf32_arm_stub_long_branch_v4t_thumb_arm[] =
b38cadfb
NC		 2439{
2440 THUMB16_INSN (0x4778), /* bx pc */
2441 THUMB16_INSN (0x46c0), /* nop */
2442 ARM_INSN (0xe51ff004), /* ldr pc, [pc, #-4] */
2443 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(X) */
2444};
906e58ca 2445
fea2b4d6
CL		 2446/* V4T Thumb -> ARM short branch stub. Shorter variant of the above
2447 one, when the destination is close enough. */
461a49ca 2448static const insn_sequence elf32_arm_stub_short_branch_v4t_thumb_arm[] =
b38cadfb
NC		 2449{
2450 THUMB16_INSN (0x4778), /* bx pc */
2451 THUMB16_INSN (0x46c0), /* nop */
2452 ARM_REL_INSN (0xea000000, -8), /* b (X-8) */
2453};
c820be07 2454
cf3eccff 2455/* ARM/Thumb -> ARM long branch stub, PIC. On V5T and above, use
fea2b4d6 2456 blx to reach the stub if necessary. */
cf3eccff 2457static const insn_sequence elf32_arm_stub_long_branch_any_arm_pic[] =
b38cadfb
NC		 2458{
2459 ARM_INSN (0xe59fc000), /* ldr ip, [pc] */
2460 ARM_INSN (0xe08ff00c), /* add pc, pc, ip */
2461 DATA_WORD (0, R_ARM_REL32, -4), /* dcd R_ARM_REL32(X-4) */
2462};
906e58ca 2463
cf3eccff
DJ		 2464/* ARM/Thumb -> Thumb long branch stub, PIC. On V5T and above, use
2465 blx to reach the stub if necessary. We can not add into pc;
2466 it is not guaranteed to mode switch (different in ARMv6 and
2467 ARMv7). */
2468static const insn_sequence elf32_arm_stub_long_branch_any_thumb_pic[] =
b38cadfb
NC		 2469{
2470 ARM_INSN (0xe59fc004), /* ldr ip, [pc, #4] */
2471 ARM_INSN (0xe08fc00c), /* add ip, pc, ip */
2472 ARM_INSN (0xe12fff1c), /* bx ip */
2473 DATA_WORD (0, R_ARM_REL32, 0), /* dcd R_ARM_REL32(X) */
2474};
cf3eccff 2475
ebe24dd4
CL		 2476/* V4T ARM -> ARM long branch stub, PIC. */
2477static const insn_sequence elf32_arm_stub_long_branch_v4t_arm_thumb_pic[] =
b38cadfb
NC		 2478{
2479 ARM_INSN (0xe59fc004), /* ldr ip, [pc, #4] */
2480 ARM_INSN (0xe08fc00c), /* add ip, pc, ip */
2481 ARM_INSN (0xe12fff1c), /* bx ip */
2482 DATA_WORD (0, R_ARM_REL32, 0), /* dcd R_ARM_REL32(X) */
2483};
ebe24dd4
CL		 2484
2485/* V4T Thumb -> ARM long branch stub, PIC. */
2486static const insn_sequence elf32_arm_stub_long_branch_v4t_thumb_arm_pic[] =
b38cadfb
NC		 2487{
2488 THUMB16_INSN (0x4778), /* bx pc */
2489 THUMB16_INSN (0x46c0), /* nop */
2490 ARM_INSN (0xe59fc000), /* ldr ip, [pc, #0] */
2491 ARM_INSN (0xe08cf00f), /* add pc, ip, pc */
2492 DATA_WORD (0, R_ARM_REL32, -4), /* dcd R_ARM_REL32(X) */
2493};
ebe24dd4 2494
d3626fb0
CL		 2495/* Thumb -> Thumb long branch stub, PIC. Used on M-profile
2496 architectures. */
ebe24dd4 2497static const insn_sequence elf32_arm_stub_long_branch_thumb_only_pic[] =
b38cadfb
NC		 2498{
2499 THUMB16_INSN (0xb401), /* push {r0} */
2500 THUMB16_INSN (0x4802), /* ldr r0, [pc, #8] */
2501 THUMB16_INSN (0x46fc), /* mov ip, pc */
2502 THUMB16_INSN (0x4484), /* add ip, r0 */
2503 THUMB16_INSN (0xbc01), /* pop {r0} */
2504 THUMB16_INSN (0x4760), /* bx ip */
2505 DATA_WORD (0, R_ARM_REL32, 4), /* dcd R_ARM_REL32(X) */
2506};
ebe24dd4 2507
d3626fb0
CL		 2508/* V4T Thumb -> Thumb long branch stub, PIC. Using the stack is not
2509 allowed. */
2510static const insn_sequence elf32_arm_stub_long_branch_v4t_thumb_thumb_pic[] =
b38cadfb
NC		 2511{
2512 THUMB16_INSN (0x4778), /* bx pc */
2513 THUMB16_INSN (0x46c0), /* nop */
2514 ARM_INSN (0xe59fc004), /* ldr ip, [pc, #4] */
2515 ARM_INSN (0xe08fc00c), /* add ip, pc, ip */
2516 ARM_INSN (0xe12fff1c), /* bx ip */
2517 DATA_WORD (0, R_ARM_REL32, 0), /* dcd R_ARM_REL32(X) */
2518};
d3626fb0 2519
0855e32b
NS		 2520/* Thumb2/ARM -> TLS trampoline. Lowest common denominator, which is a
2521 long PIC stub. We can use r1 as a scratch -- and cannot use ip. */
2522static const insn_sequence elf32_arm_stub_long_branch_any_tls_pic[] =
2523{
b38cadfb
NC		 2524 ARM_INSN (0xe59f1000), /* ldr r1, [pc] */
2525 ARM_INSN (0xe08ff001), /* add pc, pc, r1 */
2526 DATA_WORD (0, R_ARM_REL32, -4), /* dcd R_ARM_REL32(X-4) */
0855e32b
NS		 2527};
2528
2529/* V4T Thumb -> TLS trampoline. lowest common denominator, which is a
2530 long PIC stub. We can use r1 as a scratch -- and cannot use ip. */
2531static const insn_sequence elf32_arm_stub_long_branch_v4t_thumb_tls_pic[] =
2532{
b38cadfb
NC		 2533 THUMB16_INSN (0x4778), /* bx pc */
2534 THUMB16_INSN (0x46c0), /* nop */
2535 ARM_INSN (0xe59f1000), /* ldr r1, [pc, #0] */
2536 ARM_INSN (0xe081f00f), /* add pc, r1, pc */
2537 DATA_WORD (0, R_ARM_REL32, -4), /* dcd R_ARM_REL32(X) */
0855e32b
NS		 2538};
2539
7a89b94e
NC		 2540/* NaCl ARM -> ARM long branch stub. */
2541static const insn_sequence elf32_arm_stub_long_branch_arm_nacl[] =
2542{
2543 ARM_INSN (0xe59fc00c), /* ldr ip, [pc, #12] */
2544 ARM_INSN (0xe3ccc13f), /* bic ip, ip, #0xc000000f */
2545 ARM_INSN (0xe12fff1c), /* bx ip */
2546 ARM_INSN (0xe320f000), /* nop */
2547 ARM_INSN (0xe125be70), /* bkpt 0x5be0 */
2548 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(X) */
2549 DATA_WORD (0, R_ARM_NONE, 0), /* .word 0 */
2550 DATA_WORD (0, R_ARM_NONE, 0), /* .word 0 */
2551};
2552
2553/* NaCl ARM -> ARM long branch stub, PIC. */
2554static const insn_sequence elf32_arm_stub_long_branch_arm_nacl_pic[] =
2555{
2556 ARM_INSN (0xe59fc00c), /* ldr ip, [pc, #12] */
2557 ARM_INSN (0xe08cc00f), /* add ip, ip, pc */
2558 ARM_INSN (0xe3ccc13f), /* bic ip, ip, #0xc000000f */
2559 ARM_INSN (0xe12fff1c), /* bx ip */
2560 ARM_INSN (0xe125be70), /* bkpt 0x5be0 */
2561 DATA_WORD (0, R_ARM_REL32, 8), /* dcd R_ARM_REL32(X+8) */
2562 DATA_WORD (0, R_ARM_NONE, 0), /* .word 0 */
2563 DATA_WORD (0, R_ARM_NONE, 0), /* .word 0 */
2564};
2565
4ba2ef8f
TP		 2566/* Stub used for transition to secure state (aka SG veneer). */
2567static const insn_sequence elf32_arm_stub_cmse_branch_thumb_only[] =
2568{
2569 THUMB32_INSN (0xe97fe97f), /* sg. */
2570 THUMB32_B_INSN (0xf000b800, -4), /* b.w original_branch_dest. */
2571};
2572
7a89b94e 2573
48229727
JB		 2574/* Cortex-A8 erratum-workaround stubs. */
2575
2576/* Stub used for conditional branches (which may be beyond +/-1MB away, so we
2577 can't use a conditional branch to reach this stub). */
2578
2579static const insn_sequence elf32_arm_stub_a8_veneer_b_cond[] =
b38cadfb
NC		 2580{
2581 THUMB16_BCOND_INSN (0xd001), /* b<cond>.n true. */
2582 THUMB32_B_INSN (0xf000b800, -4), /* b.w insn_after_original_branch. */
2583 THUMB32_B_INSN (0xf000b800, -4) /* true: b.w original_branch_dest. */
2584};
48229727
JB		 2585
2586/* Stub used for b.w and bl.w instructions. */
2587
2588static const insn_sequence elf32_arm_stub_a8_veneer_b[] =
b38cadfb
NC		 2589{
2590 THUMB32_B_INSN (0xf000b800, -4) /* b.w original_branch_dest. */
2591};
48229727
JB		 2592
2593static const insn_sequence elf32_arm_stub_a8_veneer_bl[] =
b38cadfb
NC		 2594{
2595 THUMB32_B_INSN (0xf000b800, -4) /* b.w original_branch_dest. */
2596};
48229727
JB		 2597
2598/* Stub used for Thumb-2 blx.w instructions. We modified the original blx.w
2599 instruction (which switches to ARM mode) to point to this stub. Jump to the
2600 real destination using an ARM-mode branch. */
2601
2602static const insn_sequence elf32_arm_stub_a8_veneer_blx[] =
b38cadfb
NC		 2603{
2604 ARM_REL_INSN (0xea000000, -8) /* b original_branch_dest. */
2605};
48229727 2606
9553db3c
NC		 2607/* For each section group there can be a specially created linker section
2608 to hold the stubs for that group. The name of the stub section is based
2609 upon the name of another section within that group with the suffix below
2610 applied.
2611
2612 PR 13049: STUB_SUFFIX used to be ".stub", but this allowed the user to
2613 create what appeared to be a linker stub section when it actually
2614 contained user code/data. For example, consider this fragment:
b38cadfb 2615
9553db3c
NC		 2616 const char * stubborn_problems[] = { "np" };
2617
2618 If this is compiled with "-fPIC -fdata-sections" then gcc produces a
2619 section called:
2620
2621 .data.rel.local.stubborn_problems
2622
2623 This then causes problems in arm32_arm_build_stubs() as it triggers:
2624
2625 // Ignore non-stub sections.
2626 if (!strstr (stub_sec->name, STUB_SUFFIX))
2627 continue;
2628
2629 And so the section would be ignored instead of being processed. Hence
2630 the change in definition of STUB_SUFFIX to a name that cannot be a valid
2631 C identifier. */
2632#define STUB_SUFFIX ".__stub"
906e58ca 2633
738a79f6
CL		 2634/* One entry per long/short branch stub defined above. */
2635#define DEF_STUBS \
2636 DEF_STUB(long_branch_any_any) \
2637 DEF_STUB(long_branch_v4t_arm_thumb) \
2638 DEF_STUB(long_branch_thumb_only) \
2639 DEF_STUB(long_branch_v4t_thumb_thumb) \
2640 DEF_STUB(long_branch_v4t_thumb_arm) \
2641 DEF_STUB(short_branch_v4t_thumb_arm) \
2642 DEF_STUB(long_branch_any_arm_pic) \
2643 DEF_STUB(long_branch_any_thumb_pic) \
2644 DEF_STUB(long_branch_v4t_thumb_thumb_pic) \
2645 DEF_STUB(long_branch_v4t_arm_thumb_pic) \
2646 DEF_STUB(long_branch_v4t_thumb_arm_pic) \
48229727 2647 DEF_STUB(long_branch_thumb_only_pic) \
0855e32b
NS		 2648 DEF_STUB(long_branch_any_tls_pic) \
2649 DEF_STUB(long_branch_v4t_thumb_tls_pic) \
7a89b94e
NC		 2650 DEF_STUB(long_branch_arm_nacl) \
2651 DEF_STUB(long_branch_arm_nacl_pic) \
4ba2ef8f 2652 DEF_STUB(cmse_branch_thumb_only) \
48229727
JB		 2653 DEF_STUB(a8_veneer_b_cond) \
2654 DEF_STUB(a8_veneer_b) \
2655 DEF_STUB(a8_veneer_bl) \
80c135e5
TP		 2656 DEF_STUB(a8_veneer_blx) \
2657 DEF_STUB(long_branch_thumb2_only) \
d5a67c02 2658 DEF_STUB(long_branch_thumb2_only_pure)
738a79f6
CL		 2659
2660#define DEF_STUB(x) arm_stub_##x,
b38cadfb
NC		 2661enum elf32_arm_stub_type
2662{
906e58ca 2663 arm_stub_none,
738a79f6 2664 DEF_STUBS
4f4faa4d 2665 max_stub_type
738a79f6
CL		 2666};
2667#undef DEF_STUB
2668
8d9d9490
TP		 2669/* Note the first a8_veneer type. */
2670const unsigned arm_stub_a8_veneer_lwm = arm_stub_a8_veneer_b_cond;
2671
738a79f6
CL		 2672typedef struct
2673{
d3ce72d0 2674 const insn_sequence* template_sequence;
738a79f6
CL		 2675 int template_size;
2676} stub_def;
2677
2678#define DEF_STUB(x) {elf32_arm_stub_##x, ARRAY_SIZE(elf32_arm_stub_##x)},
b38cadfb
NC		 2679static const stub_def stub_definitions[] =
2680{
738a79f6
CL		 2681 {NULL, 0},
2682 DEF_STUBS
906e58ca
NC		 2683};
2684
2685struct elf32_arm_stub_hash_entry
2686{
2687 /* Base hash table entry structure. */
2688 struct bfd_hash_entry root;
2689
2690 /* The stub section. */
2691 asection *stub_sec;
2692
2693 /* Offset within stub_sec of the beginning of this stub. */
2694 bfd_vma stub_offset;
2695
2696 /* Given the symbol's value and its section we can determine its final
2697 value when building the stubs (so the stub knows where to jump). */
2698 bfd_vma target_value;
2699 asection *target_section;
2700
8d9d9490
TP		 2701 /* Same as above but for the source of the branch to the stub. Used for
2702 Cortex-A8 erratum workaround to patch it to branch to the stub. As
2703 such, source section does not need to be recorded since Cortex-A8 erratum
2704 workaround stubs are only generated when both source and target are in the
2705 same section. */
2706 bfd_vma source_value;
48229727
JB		 2707
2708 /* The instruction which caused this stub to be generated (only valid for
2709 Cortex-A8 erratum workaround stubs at present). */
2710 unsigned long orig_insn;
2711
461a49ca 2712 /* The stub type. */
906e58ca 2713 enum elf32_arm_stub_type stub_type;
461a49ca
DJ		 2714 /* Its encoding size in bytes. */
2715 int stub_size;
2716 /* Its template. */
2717 const insn_sequence *stub_template;
2718 /* The size of the template (number of entries). */
2719 int stub_template_size;
906e58ca
NC		 2720
2721 /* The symbol table entry, if any, that this was derived from. */
2722 struct elf32_arm_link_hash_entry *h;
2723
35fc36a8
RS		 2724 /* Type of branch. */
2725 enum arm_st_branch_type branch_type;
906e58ca
NC		 2726
2727 /* Where this stub is being called from, or, in the case of combined
2728 stub sections, the first input section in the group. */
2729 asection *id_sec;
7413f23f
DJ		 2730
2731 /* The name for the local symbol at the start of this stub. The
2732 stub name in the hash table has to be unique; this does not, so
2733 it can be friendlier. */
2734 char *output_name;
906e58ca
NC		 2735};
2736
e489d0ae
PB		 2737/* Used to build a map of a section. This is required for mixed-endian
2738 code/data. */
2739
2740typedef struct elf32_elf_section_map
2741{
2742 bfd_vma vma;
2743 char type;
2744}
2745elf32_arm_section_map;
2746
c7b8f16e
JB		 2747/* Information about a VFP11 erratum veneer, or a branch to such a veneer. */
2748
2749typedef enum
2750{
2751 VFP11_ERRATUM_BRANCH_TO_ARM_VENEER,
2752 VFP11_ERRATUM_BRANCH_TO_THUMB_VENEER,
2753 VFP11_ERRATUM_ARM_VENEER,
2754 VFP11_ERRATUM_THUMB_VENEER
2755}
2756elf32_vfp11_erratum_type;
2757
2758typedef struct elf32_vfp11_erratum_list
2759{
2760 struct elf32_vfp11_erratum_list *next;
2761 bfd_vma vma;
2762 union
2763 {
2764 struct
2765 {
2766 struct elf32_vfp11_erratum_list *veneer;
2767 unsigned int vfp_insn;
2768 } b;
2769 struct
2770 {
2771 struct elf32_vfp11_erratum_list *branch;
2772 unsigned int id;
2773 } v;
2774 } u;
2775 elf32_vfp11_erratum_type type;
2776}
2777elf32_vfp11_erratum_list;
2778
a504d23a
LA		 2779/* Information about a STM32L4XX erratum veneer, or a branch to such a
2780 veneer. */
2781typedef enum
2782{
2783 STM32L4XX_ERRATUM_BRANCH_TO_VENEER,
2784 STM32L4XX_ERRATUM_VENEER
2785}
2786elf32_stm32l4xx_erratum_type;
2787
2788typedef struct elf32_stm32l4xx_erratum_list
2789{
2790 struct elf32_stm32l4xx_erratum_list *next;
2791 bfd_vma vma;
2792 union
2793 {
2794 struct
2795 {
2796 struct elf32_stm32l4xx_erratum_list *veneer;
2797 unsigned int insn;
2798 } b;
2799 struct
2800 {
2801 struct elf32_stm32l4xx_erratum_list *branch;
2802 unsigned int id;
2803 } v;
2804 } u;
2805 elf32_stm32l4xx_erratum_type type;
2806}
2807elf32_stm32l4xx_erratum_list;
2808
2468f9c9
PB		 2809typedef enum
2810{
2811 DELETE_EXIDX_ENTRY,
2812 INSERT_EXIDX_CANTUNWIND_AT_END
2813}
2814arm_unwind_edit_type;
2815
2816/* A (sorted) list of edits to apply to an unwind table. */
2817typedef struct arm_unwind_table_edit
2818{
2819 arm_unwind_edit_type type;
2820 /* Note: we sometimes want to insert an unwind entry corresponding to a
2821 section different from the one we're currently writing out, so record the
2822 (text) section this edit relates to here. */
2823 asection *linked_section;
2824 unsigned int index;
2825 struct arm_unwind_table_edit *next;
2826}
2827arm_unwind_table_edit;
2828
8e3de13a 2829typedef struct _arm_elf_section_data
e489d0ae 2830{
2468f9c9 2831 /* Information about mapping symbols. */
e489d0ae 2832 struct bfd_elf_section_data elf;
8e3de13a 2833 unsigned int mapcount;
c7b8f16e 2834 unsigned int mapsize;
e489d0ae 2835 elf32_arm_section_map *map;
2468f9c9 2836 /* Information about CPU errata. */
c7b8f16e
JB		 2837 unsigned int erratumcount;
2838 elf32_vfp11_erratum_list *erratumlist;
a504d23a
LA		 2839 unsigned int stm32l4xx_erratumcount;
2840 elf32_stm32l4xx_erratum_list *stm32l4xx_erratumlist;
491d01d3 2841 unsigned int additional_reloc_count;
2468f9c9
PB		 2842 /* Information about unwind tables. */
2843 union
2844 {
2845 /* Unwind info attached to a text section. */
2846 struct
2847 {
2848 asection *arm_exidx_sec;
2849 } text;
2850
2851 /* Unwind info attached to an .ARM.exidx section. */
2852 struct
2853 {
2854 arm_unwind_table_edit *unwind_edit_list;
2855 arm_unwind_table_edit *unwind_edit_tail;
2856 } exidx;
2857 } u;
8e3de13a
NC		 2858}
2859_arm_elf_section_data;
e489d0ae
PB		 2860
2861#define elf32_arm_section_data(sec) \
8e3de13a 2862 ((_arm_elf_section_data *) elf_section_data (sec))
e489d0ae 2863
48229727
JB		 2864/* A fix which might be required for Cortex-A8 Thumb-2 branch/TLB erratum.
2865 These fixes are subject to a relaxation procedure (in elf32_arm_size_stubs),
2866 so may be created multiple times: we use an array of these entries whilst
2867 relaxing which we can refresh easily, then create stubs for each potentially
2868 erratum-triggering instruction once we've settled on a solution. */
2869
b38cadfb
NC		 2870struct a8_erratum_fix
2871{
48229727
JB		 2872 bfd *input_bfd;
2873 asection *section;
2874 bfd_vma offset;
8d9d9490 2875 bfd_vma target_offset;
48229727
JB		 2876 unsigned long orig_insn;
2877 char *stub_name;
2878 enum elf32_arm_stub_type stub_type;
35fc36a8 2879 enum arm_st_branch_type branch_type;
48229727
JB		 2880};
2881
2882/* A table of relocs applied to branches which might trigger Cortex-A8
2883 erratum. */
2884
b38cadfb
NC		 2885struct a8_erratum_reloc
2886{
48229727
JB		 2887 bfd_vma from;
2888 bfd_vma destination;
92750f34
DJ		 2889 struct elf32_arm_link_hash_entry *hash;
2890 const char *sym_name;
48229727 2891 unsigned int r_type;
35fc36a8 2892 enum arm_st_branch_type branch_type;
48229727
JB		 2893 bfd_boolean non_a8_stub;
2894};
2895
ba93b8ac
DJ		 2896/* The size of the thread control block. */
2897#define TCB_SIZE 8
2898
34e77a92
RS		 2899/* ARM-specific information about a PLT entry, over and above the usual
2900 gotplt_union. */
b38cadfb
NC		 2901struct arm_plt_info
2902{
34e77a92
RS		 2903 /* We reference count Thumb references to a PLT entry separately,
2904 so that we can emit the Thumb trampoline only if needed. */
2905 bfd_signed_vma thumb_refcount;
2906
2907 /* Some references from Thumb code may be eliminated by BL->BLX
2908 conversion, so record them separately. */
2909 bfd_signed_vma maybe_thumb_refcount;
2910
2911 /* How many of the recorded PLT accesses were from non-call relocations.
2912 This information is useful when deciding whether anything takes the
2913 address of an STT_GNU_IFUNC PLT. A value of 0 means that all
2914 non-call references to the function should resolve directly to the
2915 real runtime target. */
2916 unsigned int noncall_refcount;
2917
2918 /* Since PLT entries have variable size if the Thumb prologue is
2919 used, we need to record the index into .got.plt instead of
2920 recomputing it from the PLT offset. */
2921 bfd_signed_vma got_offset;
2922};
2923
2924/* Information about an .iplt entry for a local STT_GNU_IFUNC symbol. */
b38cadfb
NC		 2925struct arm_local_iplt_info
2926{
34e77a92
RS		 2927 /* The information that is usually found in the generic ELF part of
2928 the hash table entry. */
2929 union gotplt_union root;
2930
2931 /* The information that is usually found in the ARM-specific part of
2932 the hash table entry. */
2933 struct arm_plt_info arm;
2934
2935 /* A list of all potential dynamic relocations against this symbol. */
2936 struct elf_dyn_relocs *dyn_relocs;
2937};
2938
0ffa91dd 2939struct elf_arm_obj_tdata
ba93b8ac
DJ		 2940{
2941 struct elf_obj_tdata root;
2942
2943 /* tls_type for each local got entry. */
2944 char *local_got_tls_type;
ee065d83 2945
0855e32b
NS		 2946 /* GOTPLT entries for TLS descriptors. */
2947 bfd_vma *local_tlsdesc_gotent;
2948
34e77a92
RS		 2949 /* Information for local symbols that need entries in .iplt. */
2950 struct arm_local_iplt_info **local_iplt;
2951
bf21ed78
MS		 2952 /* Zero to warn when linking objects with incompatible enum sizes. */
2953 int no_enum_size_warning;
a9dc9481
JM		 2954
2955 /* Zero to warn when linking objects with incompatible wchar_t sizes. */
2956 int no_wchar_size_warning;
ba93b8ac
DJ		 2957};
2958
0ffa91dd
NC		 2959#define elf_arm_tdata(bfd) \
2960 ((struct elf_arm_obj_tdata *) (bfd)->tdata.any)
ba93b8ac 2961
0ffa91dd
NC		 2962#define elf32_arm_local_got_tls_type(bfd) \
2963 (elf_arm_tdata (bfd)->local_got_tls_type)
2964
0855e32b
NS		 2965#define elf32_arm_local_tlsdesc_gotent(bfd) \
2966 (elf_arm_tdata (bfd)->local_tlsdesc_gotent)
2967
34e77a92
RS		 2968#define elf32_arm_local_iplt(bfd) \
2969 (elf_arm_tdata (bfd)->local_iplt)
2970
0ffa91dd
NC		 2971#define is_arm_elf(bfd) \
2972 (bfd_get_flavour (bfd) == bfd_target_elf_flavour \
2973 && elf_tdata (bfd) != NULL \
4dfe6ac6 2974 && elf_object_id (bfd) == ARM_ELF_DATA)
ba93b8ac
DJ		 2975
2976static bfd_boolean
2977elf32_arm_mkobject (bfd *abfd)
2978{
0ffa91dd 2979 return bfd_elf_allocate_object (abfd, sizeof (struct elf_arm_obj_tdata),
4dfe6ac6 2980 ARM_ELF_DATA);
ba93b8ac
DJ		 2981}
2982
ba93b8ac
DJ		 2983#define elf32_arm_hash_entry(ent) ((struct elf32_arm_link_hash_entry *)(ent))
2984
ba96a88f 2985/* Arm ELF linker hash entry. */
252b5132 2986struct elf32_arm_link_hash_entry
b38cadfb
NC		 2987{
2988 struct elf_link_hash_entry root;
252b5132 2989
b38cadfb
NC		 2990 /* Track dynamic relocs copied for this symbol. */
2991 struct elf_dyn_relocs *dyn_relocs;
b7693d02 2992
b38cadfb
NC		 2993 /* ARM-specific PLT information. */
2994 struct arm_plt_info plt;
ba93b8ac
DJ		 2995
2996#define GOT_UNKNOWN 0
2997#define GOT_NORMAL 1
2998#define GOT_TLS_GD 2
2999#define GOT_TLS_IE 4
0855e32b
NS		 3000#define GOT_TLS_GDESC 8
3001#define GOT_TLS_GD_ANY_P(type) ((type & GOT_TLS_GD) || (type & GOT_TLS_GDESC))
b38cadfb 3002 unsigned int tls_type : 8;
34e77a92 3003
b38cadfb
NC		 3004 /* True if the symbol's PLT entry is in .iplt rather than .plt. */
3005 unsigned int is_iplt : 1;
34e77a92 3006
b38cadfb 3007 unsigned int unused : 23;
a4fd1a8e 3008
b38cadfb
NC		 3009 /* Offset of the GOTPLT entry reserved for the TLS descriptor,
3010 starting at the end of the jump table. */
3011 bfd_vma tlsdesc_got;
0855e32b 3012
b38cadfb
NC		 3013 /* The symbol marking the real symbol location for exported thumb
3014 symbols with Arm stubs. */
3015 struct elf_link_hash_entry *export_glue;
906e58ca 3016
b38cadfb 3017 /* A pointer to the most recently used stub hash entry against this
8029a119 3018 symbol. */
b38cadfb
NC		 3019 struct elf32_arm_stub_hash_entry *stub_cache;
3020};
252b5132 3021
252b5132 3022/* Traverse an arm ELF linker hash table. */
252b5132
RH		 3023#define elf32_arm_link_hash_traverse(table, func, info) \
3024 (elf_link_hash_traverse \
3025 (&(table)->root, \
b7693d02 3026 (bfd_boolean (*) (struct elf_link_hash_entry *, void *)) (func), \
252b5132
RH		 3027 (info)))
3028
3029/* Get the ARM elf linker hash table from a link_info structure. */
3030#define elf32_arm_hash_table(info) \
4dfe6ac6
NC		 3031 (elf_hash_table_id ((struct elf_link_hash_table *) ((info)->hash)) \
3032 == ARM_ELF_DATA ? ((struct elf32_arm_link_hash_table *) ((info)->hash)) : NULL)
252b5132 3033
906e58ca
NC		 3034#define arm_stub_hash_lookup(table, string, create, copy) \
3035 ((struct elf32_arm_stub_hash_entry *) \
3036 bfd_hash_lookup ((table), (string), (create), (copy)))
3037
21d799b5
NC		 3038/* Array to keep track of which stub sections have been created, and
3039 information on stub grouping. */
3040struct map_stub
3041{
3042 /* This is the section to which stubs in the group will be
3043 attached. */
3044 asection *link_sec;
3045 /* The stub section. */
3046 asection *stub_sec;
3047};
3048
0855e32b
NS		 3049#define elf32_arm_compute_jump_table_size(htab) \
3050 ((htab)->next_tls_desc_index * 4)
3051
9b485d32 3052/* ARM ELF linker hash table. */
252b5132 3053struct elf32_arm_link_hash_table
906e58ca
NC		 3054{
3055 /* The main hash table. */
3056 struct elf_link_hash_table root;
252b5132 3057
906e58ca
NC		 3058 /* The size in bytes of the section containing the Thumb-to-ARM glue. */
3059 bfd_size_type thumb_glue_size;
252b5132 3060
906e58ca
NC		 3061 /* The size in bytes of the section containing the ARM-to-Thumb glue. */
3062 bfd_size_type arm_glue_size;
252b5132 3063
906e58ca
NC		 3064 /* The size in bytes of section containing the ARMv4 BX veneers. */
3065 bfd_size_type bx_glue_size;
845b51d6 3066
906e58ca
NC		 3067 /* Offsets of ARMv4 BX veneers. Bit1 set if present, and Bit0 set when
3068 veneer has been populated. */
3069 bfd_vma bx_glue_offset[15];
845b51d6 3070
906e58ca
NC		 3071 /* The size in bytes of the section containing glue for VFP11 erratum
3072 veneers. */
3073 bfd_size_type vfp11_erratum_glue_size;
c7b8f16e 3074
a504d23a
LA		 3075 /* The size in bytes of the section containing glue for STM32L4XX erratum
3076 veneers. */
3077 bfd_size_type stm32l4xx_erratum_glue_size;
3078
48229727
JB		 3079 /* A table of fix locations for Cortex-A8 Thumb-2 branch/TLB erratum. This
3080 holds Cortex-A8 erratum fix locations between elf32_arm_size_stubs() and
3081 elf32_arm_write_section(). */
3082 struct a8_erratum_fix *a8_erratum_fixes;
3083 unsigned int num_a8_erratum_fixes;
3084
906e58ca
NC		 3085 /* An arbitrary input BFD chosen to hold the glue sections. */
3086 bfd * bfd_of_glue_owner;
ba96a88f 3087
906e58ca
NC		 3088 /* Nonzero to output a BE8 image. */
3089 int byteswap_code;
e489d0ae 3090
906e58ca
NC		 3091 /* Zero if R_ARM_TARGET1 means R_ARM_ABS32.
3092 Nonzero if R_ARM_TARGET1 means R_ARM_REL32. */
3093 int target1_is_rel;
9c504268 3094
906e58ca
NC		 3095 /* The relocation to use for R_ARM_TARGET2 relocations. */
3096 int target2_reloc;
eb043451 3097
906e58ca
NC		 3098 /* 0 = Ignore R_ARM_V4BX.
3099 1 = Convert BX to MOV PC.
3100 2 = Generate v4 interworing stubs. */
3101 int fix_v4bx;
319850b4 3102
48229727
JB		 3103 /* Whether we should fix the Cortex-A8 Thumb-2 branch/TLB erratum. */
3104 int fix_cortex_a8;
3105
2de70689
MGD		 3106 /* Whether we should fix the ARM1176 BLX immediate issue. */
3107 int fix_arm1176;
3108
906e58ca
NC		 3109 /* Nonzero if the ARM/Thumb BLX instructions are available for use. */
3110 int use_blx;
33bfe774 3111
906e58ca
NC		 3112 /* What sort of code sequences we should look for which may trigger the
3113 VFP11 denorm erratum. */
3114 bfd_arm_vfp11_fix vfp11_fix;
c7b8f16e 3115
906e58ca
NC		 3116 /* Global counter for the number of fixes we have emitted. */
3117 int num_vfp11_fixes;
c7b8f16e 3118
a504d23a
LA		 3119 /* What sort of code sequences we should look for which may trigger the
3120 STM32L4XX erratum. */
3121 bfd_arm_stm32l4xx_fix stm32l4xx_fix;
3122
3123 /* Global counter for the number of fixes we have emitted. */
3124 int num_stm32l4xx_fixes;
3125
906e58ca
NC		 3126 /* Nonzero to force PIC branch veneers. */
3127 int pic_veneer;
27e55c4d 3128
906e58ca
NC		 3129 /* The number of bytes in the initial entry in the PLT. */
3130 bfd_size_type plt_header_size;
e5a52504 3131
906e58ca
NC		 3132 /* The number of bytes in the subsequent PLT etries. */
3133 bfd_size_type plt_entry_size;
e5a52504 3134
906e58ca
NC		 3135 /* True if the target system is VxWorks. */
3136 int vxworks_p;
00a97672 3137
906e58ca
NC		 3138 /* True if the target system is Symbian OS. */
3139 int symbian_p;
e5a52504 3140
b38cadfb
NC		 3141 /* True if the target system is Native Client. */
3142 int nacl_p;
3143
906e58ca
NC		 3144 /* True if the target uses REL relocations. */
3145 int use_rel;
4e7fd91e 3146
54ddd295
TP		 3147 /* Nonzero if import library must be a secure gateway import library
3148 as per ARMv8-M Security Extensions. */
3149 int cmse_implib;
3150
0955507f
TP		 3151 /* The import library whose symbols' address must remain stable in
3152 the import library generated. */
3153 bfd *in_implib_bfd;
3154
0855e32b
NS		 3155 /* The index of the next unused R_ARM_TLS_DESC slot in .rel.plt. */
3156 bfd_vma next_tls_desc_index;
3157
3158 /* How many R_ARM_TLS_DESC relocations were generated so far. */
3159 bfd_vma num_tls_desc;
3160
906e58ca 3161 /* Short-cuts to get to dynamic linker sections. */
906e58ca
NC		 3162 asection *sdynbss;
3163 asection *srelbss;
5e681ec4 3164
906e58ca
NC		 3165 /* The (unloaded but important) VxWorks .rela.plt.unloaded section. */
3166 asection *srelplt2;
00a97672 3167
0855e32b
NS		 3168 /* The offset into splt of the PLT entry for the TLS descriptor
3169 resolver. Special values are 0, if not necessary (or not found
3170 to be necessary yet), and -1 if needed but not determined
3171 yet. */
3172 bfd_vma dt_tlsdesc_plt;
3173
3174 /* The offset into sgot of the GOT entry used by the PLT entry
3175 above. */
b38cadfb 3176 bfd_vma dt_tlsdesc_got;
0855e32b
NS		 3177
3178 /* Offset in .plt section of tls_arm_trampoline. */
3179 bfd_vma tls_trampoline;
3180
906e58ca
NC		 3181 /* Data for R_ARM_TLS_LDM32 relocations. */
3182 union
3183 {
3184 bfd_signed_vma refcount;
3185 bfd_vma offset;
3186 } tls_ldm_got;
b7693d02 3187
87d72d41
AM		 3188 /* Small local sym cache. */
3189 struct sym_cache sym_cache;
906e58ca
NC		 3190
3191 /* For convenience in allocate_dynrelocs. */
3192 bfd * obfd;
3193
0855e32b
NS		 3194 /* The amount of space used by the reserved portion of the sgotplt
3195 section, plus whatever space is used by the jump slots. */
3196 bfd_vma sgotplt_jump_table_size;
3197
906e58ca
NC		 3198 /* The stub hash table. */
3199 struct bfd_hash_table stub_hash_table;
3200
3201 /* Linker stub bfd. */
3202 bfd *stub_bfd;
3203
3204 /* Linker call-backs. */
6bde4c52
TP		 3205 asection * (*add_stub_section) (const char *, asection *, asection *,
3206 unsigned int);
906e58ca
NC		 3207 void (*layout_sections_again) (void);
3208
3209 /* Array to keep track of which stub sections have been created, and
3210 information on stub grouping. */
21d799b5 3211 struct map_stub *stub_group;
906e58ca 3212
4ba2ef8f
TP		 3213 /* Input stub section holding secure gateway veneers. */
3214 asection *cmse_stub_sec;
3215
0955507f
TP		 3216 /* Offset in cmse_stub_sec where new SG veneers (not in input import library)
3217 start to be allocated. */
3218 bfd_vma new_cmse_stub_offset;
3219
fe33d2fa 3220 /* Number of elements in stub_group. */
7292b3ac 3221 unsigned int top_id;
fe33d2fa 3222
906e58ca
NC		 3223 /* Assorted information used by elf32_arm_size_stubs. */
3224 unsigned int bfd_count;
7292b3ac 3225 unsigned int top_index;
906e58ca
NC		 3226 asection **input_list;
3227};
252b5132 3228
a504d23a
LA		 3229static inline int
3230ctz (unsigned int mask)
3231{
3232#if GCC_VERSION >= 3004
3233 return __builtin_ctz (mask);
3234#else
3235 unsigned int i;
3236
3237 for (i = 0; i < 8 * sizeof (mask); i++)
3238 {
3239 if (mask & 0x1)
3240 break;
3241 mask = (mask >> 1);
3242 }
3243 return i;
3244#endif
3245}
3246
3247static inline int
3248popcount (unsigned int mask)
3249{
3250#if GCC_VERSION >= 3004
3251 return __builtin_popcount (mask);
3252#else
3253 unsigned int i, sum = 0;
3254
3255 for (i = 0; i < 8 * sizeof (mask); i++)
3256 {
3257 if (mask & 0x1)
3258 sum++;
3259 mask = (mask >> 1);
3260 }
3261 return sum;
3262#endif
3263}
3264
780a67af
NC		 3265/* Create an entry in an ARM ELF linker hash table. */
3266
3267static struct bfd_hash_entry *
57e8b36a 3268elf32_arm_link_hash_newfunc (struct bfd_hash_entry * entry,
99059e56
RM		 3269 struct bfd_hash_table * table,
3270 const char * string)
780a67af
NC		 3271{
3272 struct elf32_arm_link_hash_entry * ret =
3273 (struct elf32_arm_link_hash_entry *) entry;
3274
3275 /* Allocate the structure if it has not already been allocated by a
3276 subclass. */
906e58ca 3277 if (ret == NULL)
21d799b5 3278 ret = (struct elf32_arm_link_hash_entry *)
99059e56 3279 bfd_hash_allocate (table, sizeof (struct elf32_arm_link_hash_entry));
57e8b36a 3280 if (ret == NULL)
780a67af
NC		 3281 return (struct bfd_hash_entry *) ret;
3282
3283 /* Call the allocation method of the superclass. */
3284 ret = ((struct elf32_arm_link_hash_entry *)
3285 _bfd_elf_link_hash_newfunc ((struct bfd_hash_entry *) ret,
3286 table, string));
57e8b36a 3287 if (ret != NULL)
b7693d02 3288 {
0bdcacaf 3289 ret->dyn_relocs = NULL;
ba93b8ac 3290 ret->tls_type = GOT_UNKNOWN;
0855e32b 3291 ret->tlsdesc_got = (bfd_vma) -1;
34e77a92
RS		 3292 ret->plt.thumb_refcount = 0;
3293 ret->plt.maybe_thumb_refcount = 0;
3294 ret->plt.noncall_refcount = 0;
3295 ret->plt.got_offset = -1;
3296 ret->is_iplt = FALSE;
a4fd1a8e 3297 ret->export_glue = NULL;
906e58ca
NC		 3298
3299 ret->stub_cache = NULL;
b7693d02 3300 }
780a67af
NC		 3301
3302 return (struct bfd_hash_entry *) ret;
3303}
3304
34e77a92
RS		 3305/* Ensure that we have allocated bookkeeping structures for ABFD's local
3306 symbols. */
3307
3308static bfd_boolean
3309elf32_arm_allocate_local_sym_info (bfd *abfd)
3310{
3311 if (elf_local_got_refcounts (abfd) == NULL)
3312 {
3313 bfd_size_type num_syms;
3314 bfd_size_type size;
3315 char *data;
3316
3317 num_syms = elf_tdata (abfd)->symtab_hdr.sh_info;
3318 size = num_syms * (sizeof (bfd_signed_vma)
3319 + sizeof (struct arm_local_iplt_info *)
3320 + sizeof (bfd_vma)
3321 + sizeof (char));
3322 data = bfd_zalloc (abfd, size);
3323 if (data == NULL)
3324 return FALSE;
3325
3326 elf_local_got_refcounts (abfd) = (bfd_signed_vma *) data;
3327 data += num_syms * sizeof (bfd_signed_vma);
3328
3329 elf32_arm_local_iplt (abfd) = (struct arm_local_iplt_info **) data;
3330 data += num_syms * sizeof (struct arm_local_iplt_info *);
3331
3332 elf32_arm_local_tlsdesc_gotent (abfd) = (bfd_vma *) data;
3333 data += num_syms * sizeof (bfd_vma);
3334
3335 elf32_arm_local_got_tls_type (abfd) = data;
3336 }
3337 return TRUE;
3338}
3339
3340/* Return the .iplt information for local symbol R_SYMNDX, which belongs
3341 to input bfd ABFD. Create the information if it doesn't already exist.
3342 Return null if an allocation fails. */
3343
3344static struct arm_local_iplt_info *
3345elf32_arm_create_local_iplt (bfd *abfd, unsigned long r_symndx)
3346{
3347 struct arm_local_iplt_info **ptr;
3348
3349 if (!elf32_arm_allocate_local_sym_info (abfd))
3350 return NULL;
3351
3352 BFD_ASSERT (r_symndx < elf_tdata (abfd)->symtab_hdr.sh_info);
3353 ptr = &elf32_arm_local_iplt (abfd)[r_symndx];
3354 if (*ptr == NULL)
3355 *ptr = bfd_zalloc (abfd, sizeof (**ptr));
3356 return *ptr;
3357}
3358
3359/* Try to obtain PLT information for the symbol with index R_SYMNDX
3360 in ABFD's symbol table. If the symbol is global, H points to its
3361 hash table entry, otherwise H is null.
3362
3363 Return true if the symbol does have PLT information. When returning
3364 true, point *ROOT_PLT at the target-independent reference count/offset
3365 union and *ARM_PLT at the ARM-specific information. */
3366
3367static bfd_boolean
4ba2ef8f
TP		 3368elf32_arm_get_plt_info (bfd *abfd, struct elf32_arm_link_hash_table *globals,
3369 struct elf32_arm_link_hash_entry *h,
34e77a92
RS		 3370 unsigned long r_symndx, union gotplt_union **root_plt,
3371 struct arm_plt_info **arm_plt)
3372{
3373 struct arm_local_iplt_info *local_iplt;
3374
4ba2ef8f
TP		 3375 if (globals->root.splt == NULL && globals->root.iplt == NULL)
3376 return FALSE;
3377
34e77a92
RS		 3378 if (h != NULL)
3379 {
3380 *root_plt = &h->root.plt;
3381 *arm_plt = &h->plt;
3382 return TRUE;
3383 }
3384
3385 if (elf32_arm_local_iplt (abfd) == NULL)
3386 return FALSE;
3387
3388 local_iplt = elf32_arm_local_iplt (abfd)[r_symndx];
3389 if (local_iplt == NULL)
3390 return FALSE;
3391
3392 *root_plt = &local_iplt->root;
3393 *arm_plt = &local_iplt->arm;
3394 return TRUE;
3395}
3396
3397/* Return true if the PLT described by ARM_PLT requires a Thumb stub
3398 before it. */
3399
3400static bfd_boolean
3401elf32_arm_plt_needs_thumb_stub_p (struct bfd_link_info *info,
3402 struct arm_plt_info *arm_plt)
3403{
3404 struct elf32_arm_link_hash_table *htab;
3405
3406 htab = elf32_arm_hash_table (info);
3407 return (arm_plt->thumb_refcount != 0
3408 || (!htab->use_blx && arm_plt->maybe_thumb_refcount != 0));
3409}
3410
3411/* Return a pointer to the head of the dynamic reloc list that should
3412 be used for local symbol ISYM, which is symbol number R_SYMNDX in
3413 ABFD's symbol table. Return null if an error occurs. */
3414
3415static struct elf_dyn_relocs **
3416elf32_arm_get_local_dynreloc_list (bfd *abfd, unsigned long r_symndx,
3417 Elf_Internal_Sym *isym)
3418{
3419 if (ELF32_ST_TYPE (isym->st_info) == STT_GNU_IFUNC)
3420 {
3421 struct arm_local_iplt_info *local_iplt;
3422
3423 local_iplt = elf32_arm_create_local_iplt (abfd, r_symndx);
3424 if (local_iplt == NULL)
3425 return NULL;
3426 return &local_iplt->dyn_relocs;
3427 }
3428 else
3429 {
3430 /* Track dynamic relocs needed for local syms too.
3431 We really need local syms available to do this
3432 easily. Oh well. */
3433 asection *s;
3434 void *vpp;
3435
3436 s = bfd_section_from_elf_index (abfd, isym->st_shndx);
3437 if (s == NULL)
3438 abort ();
3439
3440 vpp = &elf_section_data (s)->local_dynrel;
3441 return (struct elf_dyn_relocs **) vpp;
3442 }
3443}
3444
906e58ca
NC		 3445/* Initialize an entry in the stub hash table. */
3446
3447static struct bfd_hash_entry *
3448stub_hash_newfunc (struct bfd_hash_entry *entry,
3449 struct bfd_hash_table *table,
3450 const char *string)
3451{
3452 /* Allocate the structure if it has not already been allocated by a
3453 subclass. */
3454 if (entry == NULL)
3455 {
21d799b5 3456 entry = (struct bfd_hash_entry *)
99059e56 3457 bfd_hash_allocate (table, sizeof (struct elf32_arm_stub_hash_entry));
906e58ca
NC		 3458 if (entry == NULL)
3459 return entry;
3460 }
3461
3462 /* Call the allocation method of the superclass. */
3463 entry = bfd_hash_newfunc (entry, table, string);
3464 if (entry != NULL)
3465 {
3466 struct elf32_arm_stub_hash_entry *eh;
3467
3468 /* Initialize the local fields. */
3469 eh = (struct elf32_arm_stub_hash_entry *) entry;
3470 eh->stub_sec = NULL;
0955507f 3471 eh->stub_offset = (bfd_vma) -1;
8d9d9490 3472 eh->source_value = 0;
906e58ca
NC		 3473 eh->target_value = 0;
3474 eh->target_section = NULL;
cedfb179 3475 eh->orig_insn = 0;
906e58ca 3476 eh->stub_type = arm_stub_none;
461a49ca
DJ		 3477 eh->stub_size = 0;
3478 eh->stub_template = NULL;
0955507f 3479 eh->stub_template_size = -1;
906e58ca
NC		 3480 eh->h = NULL;
3481 eh->id_sec = NULL;
d8d2f433 3482 eh->output_name = NULL;
906e58ca
NC		 3483 }
3484
3485 return entry;
3486}
3487
00a97672 3488/* Create .got, .gotplt, and .rel(a).got sections in DYNOBJ, and set up
5e681ec4
PB		 3489 shortcuts to them in our hash table. */
3490
3491static bfd_boolean
57e8b36a 3492create_got_section (bfd *dynobj, struct bfd_link_info *info)
5e681ec4
PB		 3493{
3494 struct elf32_arm_link_hash_table *htab;
3495
e5a52504 3496 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 3497 if (htab == NULL)
3498 return FALSE;
3499
e5a52504
MM		 3500 /* BPABI objects never have a GOT, or associated sections. */
3501 if (htab->symbian_p)
3502 return TRUE;
3503
5e681ec4
PB		 3504 if (! _bfd_elf_create_got_section (dynobj, info))
3505 return FALSE;
3506
5e681ec4
PB		 3507 return TRUE;
3508}
3509
34e77a92
RS		 3510/* Create the .iplt, .rel(a).iplt and .igot.plt sections. */
3511
3512static bfd_boolean
3513create_ifunc_sections (struct bfd_link_info *info)
3514{
3515 struct elf32_arm_link_hash_table *htab;
3516 const struct elf_backend_data *bed;
3517 bfd *dynobj;
3518 asection *s;
3519 flagword flags;
b38cadfb 3520
34e77a92
RS		 3521 htab = elf32_arm_hash_table (info);
3522 dynobj = htab->root.dynobj;
3523 bed = get_elf_backend_data (dynobj);
3524 flags = bed->dynamic_sec_flags;
3525
3526 if (htab->root.iplt == NULL)
3527 {
3d4d4302
AM		 3528 s = bfd_make_section_anyway_with_flags (dynobj, ".iplt",
3529 flags | SEC_READONLY | SEC_CODE);
34e77a92 3530 if (s == NULL
a0f49396 3531 || !bfd_set_section_alignment (dynobj, s, bed->plt_alignment))
34e77a92
RS		 3532 return FALSE;
3533 htab->root.iplt = s;
3534 }
3535
3536 if (htab->root.irelplt == NULL)
3537 {
3d4d4302
AM		 3538 s = bfd_make_section_anyway_with_flags (dynobj,
3539 RELOC_SECTION (htab, ".iplt"),
3540 flags | SEC_READONLY);
34e77a92 3541 if (s == NULL
a0f49396 3542 || !bfd_set_section_alignment (dynobj, s, bed->s->log_file_align))
34e77a92
RS		 3543 return FALSE;
3544 htab->root.irelplt = s;
3545 }
3546
3547 if (htab->root.igotplt == NULL)
3548 {
3d4d4302 3549 s = bfd_make_section_anyway_with_flags (dynobj, ".igot.plt", flags);
34e77a92
RS		 3550 if (s == NULL
3551 || !bfd_set_section_alignment (dynobj, s, bed->s->log_file_align))
3552 return FALSE;
3553 htab->root.igotplt = s;
3554 }
3555 return TRUE;
3556}
3557
eed94f8f
NC		 3558/* Determine if we're dealing with a Thumb only architecture. */
3559
3560static bfd_boolean
3561using_thumb_only (struct elf32_arm_link_hash_table *globals)
3562{
2fd158eb
TP		 3563 int arch;
3564 int profile = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC,
3565 Tag_CPU_arch_profile);
eed94f8f 3566
2fd158eb
TP		 3567 if (profile)
3568 return profile == 'M';
eed94f8f 3569
2fd158eb 3570 arch = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC, Tag_CPU_arch);
eed94f8f 3571
60a019a0
TP		 3572 /* Force return logic to be reviewed for each new architecture. */
3573 BFD_ASSERT (arch <= TAG_CPU_ARCH_V8
3574 || arch == TAG_CPU_ARCH_V8M_BASE
3575 || arch == TAG_CPU_ARCH_V8M_MAIN);
3576
2fd158eb
TP		 3577 if (arch == TAG_CPU_ARCH_V6_M
3578 || arch == TAG_CPU_ARCH_V6S_M
3579 || arch == TAG_CPU_ARCH_V7E_M
3580 || arch == TAG_CPU_ARCH_V8M_BASE
3581 || arch == TAG_CPU_ARCH_V8M_MAIN)
3582 return TRUE;
eed94f8f 3583
2fd158eb 3584 return FALSE;
eed94f8f
NC		 3585}
3586
3587/* Determine if we're dealing with a Thumb-2 object. */
3588
3589static bfd_boolean
3590using_thumb2 (struct elf32_arm_link_hash_table *globals)
3591{
60a019a0
TP		 3592 int arch;
3593 int thumb_isa = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC,
3594 Tag_THUMB_ISA_use);
3595
3596 if (thumb_isa)
3597 return thumb_isa == 2;
3598
3599 arch = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC, Tag_CPU_arch);
3600
3601 /* Force return logic to be reviewed for each new architecture. */
3602 BFD_ASSERT (arch <= TAG_CPU_ARCH_V8
3603 || arch == TAG_CPU_ARCH_V8M_BASE
3604 || arch == TAG_CPU_ARCH_V8M_MAIN);
3605
3606 return (arch == TAG_CPU_ARCH_V6T2
3607 || arch == TAG_CPU_ARCH_V7
3608 || arch == TAG_CPU_ARCH_V7E_M
3609 || arch == TAG_CPU_ARCH_V8
3610 || arch == TAG_CPU_ARCH_V8M_MAIN);
eed94f8f
NC		 3611}
3612
5e866f5a
TP		 3613/* Determine whether Thumb-2 BL instruction is available. */
3614
3615static bfd_boolean
3616using_thumb2_bl (struct elf32_arm_link_hash_table *globals)
3617{
3618 int arch =
3619 bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC, Tag_CPU_arch);
3620
3621 /* Force return logic to be reviewed for each new architecture. */
3622 BFD_ASSERT (arch <= TAG_CPU_ARCH_V8
3623 || arch == TAG_CPU_ARCH_V8M_BASE
3624 || arch == TAG_CPU_ARCH_V8M_MAIN);
3625
3626 /* Architecture was introduced after ARMv6T2 (eg. ARMv6-M). */
3627 return (arch == TAG_CPU_ARCH_V6T2
3628 || arch >= TAG_CPU_ARCH_V7);
3629}
3630
00a97672
RS		 3631/* Create .plt, .rel(a).plt, .got, .got.plt, .rel(a).got, .dynbss, and
3632 .rel(a).bss sections in DYNOBJ, and set up shortcuts to them in our
5e681ec4
PB		 3633 hash table. */
3634
3635static bfd_boolean
57e8b36a 3636elf32_arm_create_dynamic_sections (bfd *dynobj, struct bfd_link_info *info)
5e681ec4
PB		 3637{
3638 struct elf32_arm_link_hash_table *htab;
3639
3640 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 3641 if (htab == NULL)
3642 return FALSE;
3643
362d30a1 3644 if (!htab->root.sgot && !create_got_section (dynobj, info))
5e681ec4
PB		 3645 return FALSE;
3646
3647 if (!_bfd_elf_create_dynamic_sections (dynobj, info))
3648 return FALSE;
3649
3d4d4302 3650 htab->sdynbss = bfd_get_linker_section (dynobj, ".dynbss");
0e1862bb 3651 if (!bfd_link_pic (info))
3d4d4302
AM		 3652 htab->srelbss = bfd_get_linker_section (dynobj,
3653 RELOC_SECTION (htab, ".bss"));
00a97672
RS		 3654
3655 if (htab->vxworks_p)
3656 {
3657 if (!elf_vxworks_create_dynamic_sections (dynobj, info, &htab->srelplt2))
3658 return FALSE;
3659
0e1862bb 3660 if (bfd_link_pic (info))
00a97672
RS		 3661 {
3662 htab->plt_header_size = 0;
3663 htab->plt_entry_size
3664 = 4 * ARRAY_SIZE (elf32_arm_vxworks_shared_plt_entry);
3665 }
3666 else
3667 {
3668 htab->plt_header_size
3669 = 4 * ARRAY_SIZE (elf32_arm_vxworks_exec_plt0_entry);
3670 htab->plt_entry_size
3671 = 4 * ARRAY_SIZE (elf32_arm_vxworks_exec_plt_entry);
3672 }
aebf9be7
NC		 3673
3674 if (elf_elfheader (dynobj))
3675 elf_elfheader (dynobj)->e_ident[EI_CLASS] = ELFCLASS32;
00a97672 3676 }
eed94f8f
NC		 3677 else
3678 {
3679 /* PR ld/16017
3680 Test for thumb only architectures. Note - we cannot just call
3681 using_thumb_only() as the attributes in the output bfd have not been
3682 initialised at this point, so instead we use the input bfd. */
3683 bfd * saved_obfd = htab->obfd;
3684
3685 htab->obfd = dynobj;
3686 if (using_thumb_only (htab))
3687 {
3688 htab->plt_header_size = 4 * ARRAY_SIZE (elf32_thumb2_plt0_entry);
3689 htab->plt_entry_size = 4 * ARRAY_SIZE (elf32_thumb2_plt_entry);
3690 }
3691 htab->obfd = saved_obfd;
3692 }
5e681ec4 3693
362d30a1
RS		 3694 if (!htab->root.splt
3695 || !htab->root.srelplt
e5a52504 3696 || !htab->sdynbss
0e1862bb 3697 || (!bfd_link_pic (info) && !htab->srelbss))
5e681ec4
PB		 3698 abort ();
3699
3700 return TRUE;
3701}
3702
906e58ca
NC		 3703/* Copy the extra info we tack onto an elf_link_hash_entry. */
3704
3705static void
3706elf32_arm_copy_indirect_symbol (struct bfd_link_info *info,
3707 struct elf_link_hash_entry *dir,
3708 struct elf_link_hash_entry *ind)
3709{
3710 struct elf32_arm_link_hash_entry *edir, *eind;
3711
3712 edir = (struct elf32_arm_link_hash_entry *) dir;
3713 eind = (struct elf32_arm_link_hash_entry *) ind;
3714
0bdcacaf 3715 if (eind->dyn_relocs != NULL)
906e58ca 3716 {
0bdcacaf 3717 if (edir->dyn_relocs != NULL)
906e58ca 3718 {
0bdcacaf
RS		 3719 struct elf_dyn_relocs **pp;
3720 struct elf_dyn_relocs *p;
906e58ca
NC		 3721
3722 /* Add reloc counts against the indirect sym to the direct sym
3723 list. Merge any entries against the same section. */
0bdcacaf 3724 for (pp = &eind->dyn_relocs; (p = *pp) != NULL; )
906e58ca 3725 {
0bdcacaf 3726 struct elf_dyn_relocs *q;
906e58ca 3727
0bdcacaf
RS		 3728 for (q = edir->dyn_relocs; q != NULL; q = q->next)
3729 if (q->sec == p->sec)
906e58ca
NC		 3730 {
3731 q->pc_count += p->pc_count;
3732 q->count += p->count;
3733 *pp = p->next;
3734 break;
3735 }
3736 if (q == NULL)
3737 pp = &p->next;
3738 }
0bdcacaf 3739 *pp = edir->dyn_relocs;
906e58ca
NC		 3740 }
3741
0bdcacaf
RS		 3742 edir->dyn_relocs = eind->dyn_relocs;
3743 eind->dyn_relocs = NULL;
906e58ca
NC		 3744 }
3745
3746 if (ind->root.type == bfd_link_hash_indirect)
3747 {
3748 /* Copy over PLT info. */
34e77a92
RS		 3749 edir->plt.thumb_refcount += eind->plt.thumb_refcount;
3750 eind->plt.thumb_refcount = 0;
3751 edir->plt.maybe_thumb_refcount += eind->plt.maybe_thumb_refcount;
3752 eind->plt.maybe_thumb_refcount = 0;
3753 edir->plt.noncall_refcount += eind->plt.noncall_refcount;
3754 eind->plt.noncall_refcount = 0;
3755
3756 /* We should only allocate a function to .iplt once the final
3757 symbol information is known. */
3758 BFD_ASSERT (!eind->is_iplt);
906e58ca
NC		 3759
3760 if (dir->got.refcount <= 0)
3761 {
3762 edir->tls_type = eind->tls_type;
3763 eind->tls_type = GOT_UNKNOWN;
3764 }
3765 }
3766
3767 _bfd_elf_link_hash_copy_indirect (info, dir, ind);
3768}
3769
68faa637
AM		 3770/* Destroy an ARM elf linker hash table. */
3771
3772static void
d495ab0d 3773elf32_arm_link_hash_table_free (bfd *obfd)
68faa637
AM		 3774{
3775 struct elf32_arm_link_hash_table *ret
d495ab0d 3776 = (struct elf32_arm_link_hash_table *) obfd->link.hash;
68faa637
AM		 3777
3778 bfd_hash_table_free (&ret->stub_hash_table);
d495ab0d 3779 _bfd_elf_link_hash_table_free (obfd);
68faa637
AM		 3780}
3781
906e58ca
NC		 3782/* Create an ARM elf linker hash table. */
3783
3784static struct bfd_link_hash_table *
3785elf32_arm_link_hash_table_create (bfd *abfd)
3786{
3787 struct elf32_arm_link_hash_table *ret;
3788 bfd_size_type amt = sizeof (struct elf32_arm_link_hash_table);
3789
7bf52ea2 3790 ret = (struct elf32_arm_link_hash_table *) bfd_zmalloc (amt);
906e58ca
NC		 3791 if (ret == NULL)
3792 return NULL;
3793
3794 if (!_bfd_elf_link_hash_table_init (& ret->root, abfd,
3795 elf32_arm_link_hash_newfunc,
4dfe6ac6
NC		 3796 sizeof (struct elf32_arm_link_hash_entry),
3797 ARM_ELF_DATA))
906e58ca
NC		 3798 {
3799 free (ret);
3800 return NULL;
3801 }
3802
906e58ca 3803 ret->vfp11_fix = BFD_ARM_VFP11_FIX_NONE;
a504d23a 3804 ret->stm32l4xx_fix = BFD_ARM_STM32L4XX_FIX_NONE;
906e58ca
NC		 3805#ifdef FOUR_WORD_PLT
3806 ret->plt_header_size = 16;
3807 ret->plt_entry_size = 16;
3808#else
3809 ret->plt_header_size = 20;
1db37fe6 3810 ret->plt_entry_size = elf32_arm_use_long_plt_entry ? 16 : 12;
906e58ca 3811#endif
906e58ca 3812 ret->use_rel = 1;
906e58ca 3813 ret->obfd = abfd;
906e58ca
NC		 3814
3815 if (!bfd_hash_table_init (&ret->stub_hash_table, stub_hash_newfunc,
3816 sizeof (struct elf32_arm_stub_hash_entry)))
3817 {
d495ab0d 3818 _bfd_elf_link_hash_table_free (abfd);
906e58ca
NC		 3819 return NULL;
3820 }
d495ab0d 3821 ret->root.root.hash_table_free = elf32_arm_link_hash_table_free;
906e58ca
NC		 3822
3823 return &ret->root.root;
3824}
3825
cd1dac3d
DG		 3826/* Determine what kind of NOPs are available. */
3827
3828static bfd_boolean
3829arch_has_arm_nop (struct elf32_arm_link_hash_table *globals)
3830{
3831 const int arch = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC,
3832 Tag_CPU_arch);
cd1dac3d 3833
60a019a0
TP		 3834 /* Force return logic to be reviewed for each new architecture. */
3835 BFD_ASSERT (arch <= TAG_CPU_ARCH_V8
3836 || arch == TAG_CPU_ARCH_V8M_BASE
3837 || arch == TAG_CPU_ARCH_V8M_MAIN);
3838
3839 return (arch == TAG_CPU_ARCH_V6T2
3840 || arch == TAG_CPU_ARCH_V6K
3841 || arch == TAG_CPU_ARCH_V7
3842 || arch == TAG_CPU_ARCH_V8);
cd1dac3d
DG		 3843}
3844
f4ac8484
DJ		 3845static bfd_boolean
3846arm_stub_is_thumb (enum elf32_arm_stub_type stub_type)
3847{
3848 switch (stub_type)
3849 {
fea2b4d6 3850 case arm_stub_long_branch_thumb_only:
80c135e5 3851 case arm_stub_long_branch_thumb2_only:
d5a67c02 3852 case arm_stub_long_branch_thumb2_only_pure:
fea2b4d6
CL		 3853 case arm_stub_long_branch_v4t_thumb_arm:
3854 case arm_stub_short_branch_v4t_thumb_arm:
ebe24dd4 3855 case arm_stub_long_branch_v4t_thumb_arm_pic:
12352d3f 3856 case arm_stub_long_branch_v4t_thumb_tls_pic:
ebe24dd4 3857 case arm_stub_long_branch_thumb_only_pic:
4ba2ef8f 3858 case arm_stub_cmse_branch_thumb_only:
f4ac8484
DJ		 3859 return TRUE;
3860 case arm_stub_none:
3861 BFD_FAIL ();
3862 return FALSE;
3863 break;
3864 default:
3865 return FALSE;
3866 }
3867}
3868
906e58ca
NC		 3869/* Determine the type of stub needed, if any, for a call. */
3870
3871static enum elf32_arm_stub_type
3872arm_type_of_stub (struct bfd_link_info *info,
3873 asection *input_sec,
3874 const Elf_Internal_Rela *rel,
34e77a92 3875 unsigned char st_type,
35fc36a8 3876 enum arm_st_branch_type *actual_branch_type,
906e58ca 3877 struct elf32_arm_link_hash_entry *hash,
c820be07
NC		 3878 bfd_vma destination,
3879 asection *sym_sec,
3880 bfd *input_bfd,
3881 const char *name)
906e58ca
NC		 3882{
3883 bfd_vma location;
3884 bfd_signed_vma branch_offset;
3885 unsigned int r_type;
3886 struct elf32_arm_link_hash_table * globals;
5e866f5a 3887 bfd_boolean thumb2, thumb2_bl, thumb_only;
906e58ca 3888 enum elf32_arm_stub_type stub_type = arm_stub_none;
5fa9e92f 3889 int use_plt = 0;
35fc36a8 3890 enum arm_st_branch_type branch_type = *actual_branch_type;
34e77a92
RS		 3891 union gotplt_union *root_plt;
3892 struct arm_plt_info *arm_plt;
d5a67c02
AV		 3893 int arch;
3894 int thumb2_movw;
906e58ca 3895
35fc36a8 3896 if (branch_type == ST_BRANCH_LONG)
da5938a2
NC		 3897 return stub_type;
3898
906e58ca 3899 globals = elf32_arm_hash_table (info);
4dfe6ac6
NC		 3900 if (globals == NULL)
3901 return stub_type;
906e58ca
NC		 3902
3903 thumb_only = using_thumb_only (globals);
906e58ca 3904 thumb2 = using_thumb2 (globals);
5e866f5a 3905 thumb2_bl = using_thumb2_bl (globals);
906e58ca 3906
d5a67c02
AV		 3907 arch = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC, Tag_CPU_arch);
3908
3909 /* True for architectures that implement the thumb2 movw instruction. */
3910 thumb2_movw = thumb2 || (arch == TAG_CPU_ARCH_V8M_BASE);
3911
906e58ca
NC		 3912 /* Determine where the call point is. */
3913 location = (input_sec->output_offset
3914 + input_sec->output_section->vma
3915 + rel->r_offset);
3916
906e58ca
NC		 3917 r_type = ELF32_R_TYPE (rel->r_info);
3918
39f21624
NC		 3919 /* ST_BRANCH_TO_ARM is nonsense to thumb-only targets when we
3920 are considering a function call relocation. */
c5423981
TG		 3921 if (thumb_only && (r_type == R_ARM_THM_CALL || r_type == R_ARM_THM_JUMP24
3922 || r_type == R_ARM_THM_JUMP19)
39f21624
NC		 3923 && branch_type == ST_BRANCH_TO_ARM)
3924 branch_type = ST_BRANCH_TO_THUMB;
3925
34e77a92
RS		 3926 /* For TLS call relocs, it is the caller's responsibility to provide
3927 the address of the appropriate trampoline. */
3928 if (r_type != R_ARM_TLS_CALL
3929 && r_type != R_ARM_THM_TLS_CALL
4ba2ef8f
TP		 3930 && elf32_arm_get_plt_info (input_bfd, globals, hash,
3931 ELF32_R_SYM (rel->r_info), &root_plt,
3932 &arm_plt)
34e77a92 3933 && root_plt->offset != (bfd_vma) -1)
5fa9e92f 3934 {
34e77a92 3935 asection *splt;
fe33d2fa 3936
34e77a92
RS		 3937 if (hash == NULL || hash->is_iplt)
3938 splt = globals->root.iplt;
3939 else
3940 splt = globals->root.splt;
3941 if (splt != NULL)
b38cadfb 3942 {
34e77a92
RS		 3943 use_plt = 1;
3944
3945 /* Note when dealing with PLT entries: the main PLT stub is in
3946 ARM mode, so if the branch is in Thumb mode, another
3947 Thumb->ARM stub will be inserted later just before the ARM
3948 PLT stub. We don't take this extra distance into account
3949 here, because if a long branch stub is needed, we'll add a
3950 Thumb->Arm one and branch directly to the ARM PLT entry
3951 because it avoids spreading offset corrections in several
3952 places. */
3953
3954 destination = (splt->output_section->vma
3955 + splt->output_offset
3956 + root_plt->offset);
3957 st_type = STT_FUNC;
3958 branch_type = ST_BRANCH_TO_ARM;
3959 }
5fa9e92f 3960 }
34e77a92
RS		 3961 /* Calls to STT_GNU_IFUNC symbols should go through a PLT. */
3962 BFD_ASSERT (st_type != STT_GNU_IFUNC);
906e58ca 3963
fe33d2fa
CL		 3964 branch_offset = (bfd_signed_vma)(destination - location);
3965
0855e32b 3966 if (r_type == R_ARM_THM_CALL || r_type == R_ARM_THM_JUMP24
c5423981 3967 || r_type == R_ARM_THM_TLS_CALL || r_type == R_ARM_THM_JUMP19)
906e58ca 3968 {
5fa9e92f
CL		 3969 /* Handle cases where:
3970 - this call goes too far (different Thumb/Thumb2 max
99059e56 3971 distance)
155d87d7 3972 - it's a Thumb->Arm call and blx is not available, or it's a
99059e56
RM		 3973 Thumb->Arm branch (not bl). A stub is needed in this case,
3974 but only if this call is not through a PLT entry. Indeed,
3975 PLT stubs handle mode switching already.
5fa9e92f 3976 */
5e866f5a 3977 if ((!thumb2_bl
906e58ca
NC		 3978 && (branch_offset > THM_MAX_FWD_BRANCH_OFFSET
3979 || (branch_offset < THM_MAX_BWD_BRANCH_OFFSET)))
5e866f5a 3980 || (thumb2_bl
906e58ca
NC		 3981 && (branch_offset > THM2_MAX_FWD_BRANCH_OFFSET
3982 || (branch_offset < THM2_MAX_BWD_BRANCH_OFFSET)))
c5423981
TG		 3983 || (thumb2
3984 && (branch_offset > THM2_MAX_FWD_COND_BRANCH_OFFSET
3985 || (branch_offset < THM2_MAX_BWD_COND_BRANCH_OFFSET))
3986 && (r_type == R_ARM_THM_JUMP19))
35fc36a8 3987 || (branch_type == ST_BRANCH_TO_ARM
0855e32b
NS		 3988 && (((r_type == R_ARM_THM_CALL
3989 || r_type == R_ARM_THM_TLS_CALL) && !globals->use_blx)
c5423981
TG		 3990 || (r_type == R_ARM_THM_JUMP24)
3991 || (r_type == R_ARM_THM_JUMP19))
5fa9e92f 3992 && !use_plt))
906e58ca 3993 {
35fc36a8 3994 if (branch_type == ST_BRANCH_TO_THUMB)
906e58ca
NC		 3995 {
3996 /* Thumb to thumb. */
3997 if (!thumb_only)
3998 {
d5a67c02
AV		 3999 if (input_sec->flags & SEC_ELF_PURECODE)
4000 (*_bfd_error_handler) (_("%B(%s): warning: long branch "
4001 " veneers used in section with "
4002 "SHF_ARM_PURECODE section "
4003 "attribute is only supported"
4004 " for M-profile targets that "
4005 "implement the movw "
4006 "instruction."));
4007
0e1862bb 4008 stub_type = (bfd_link_pic (info) | globals->pic_veneer)
c2b4a39d 4009 /* PIC stubs. */
155d87d7 4010 ? ((globals->use_blx
9553db3c 4011 && (r_type == R_ARM_THM_CALL))
155d87d7
CL		 4012 /* V5T and above. Stub starts with ARM code, so
4013 we must be able to switch mode before
4014 reaching it, which is only possible for 'bl'
4015 (ie R_ARM_THM_CALL relocation). */
cf3eccff 4016 ? arm_stub_long_branch_any_thumb_pic
ebe24dd4 4017 /* On V4T, use Thumb code only. */
d3626fb0 4018 : arm_stub_long_branch_v4t_thumb_thumb_pic)
c2b4a39d
CL		 4019
4020 /* non-PIC stubs. */
155d87d7 4021 : ((globals->use_blx
9553db3c 4022 && (r_type == R_ARM_THM_CALL))
c2b4a39d
CL		 4023 /* V5T and above. */
4024 ? arm_stub_long_branch_any_any
4025 /* V4T. */
d3626fb0 4026 : arm_stub_long_branch_v4t_thumb_thumb);
906e58ca
NC		 4027 }
4028 else
4029 {
d5a67c02
AV		 4030 if (thumb2_movw && (input_sec->flags & SEC_ELF_PURECODE))
4031 stub_type = arm_stub_long_branch_thumb2_only_pure;
4032 else
4033 {
4034 if (input_sec->flags & SEC_ELF_PURECODE)
4035 (*_bfd_error_handler) (_("%B(%s): warning: long branch "
4036 " veneers used in section with "
4037 "SHF_ARM_PURECODE section "
4038 "attribute is only supported"
4039 " for M-profile targets that "
4040 "implement the movw "
4041 "instruction."));
4042
4043 stub_type = (bfd_link_pic (info) | globals->pic_veneer)
4044 /* PIC stub. */
4045 ? arm_stub_long_branch_thumb_only_pic
4046 /* non-PIC stub. */
4047 : (thumb2 ? arm_stub_long_branch_thumb2_only
4048 : arm_stub_long_branch_thumb_only);
4049 }
906e58ca
NC		 4050 }
4051 }
4052 else
4053 {
d5a67c02
AV		 4054 if (input_sec->flags & SEC_ELF_PURECODE)
4055 (*_bfd_error_handler) (_("%B(%s): warning: long branch "
4056 " veneers used in section with "
4057 "SHF_ARM_PURECODE section "
4058 "attribute is only supported"
4059 " for M-profile targets that "
4060 "implement the movw "
4061 "instruction."));
4062
906e58ca 4063 /* Thumb to arm. */
c820be07
NC		 4064 if (sym_sec != NULL
4065 && sym_sec->owner != NULL
4066 && !INTERWORK_FLAG (sym_sec->owner))
4067 {
4068 (*_bfd_error_handler)
4069 (_("%B(%s): warning: interworking not enabled.\n"
4070 " first occurrence: %B: Thumb call to ARM"),
4071 sym_sec->owner, input_bfd, name);
4072 }
4073
0855e32b 4074 stub_type =
0e1862bb 4075 (bfd_link_pic (info) | globals->pic_veneer)
c2b4a39d 4076 /* PIC stubs. */
0855e32b 4077 ? (r_type == R_ARM_THM_TLS_CALL
6a631e86 4078 /* TLS PIC stubs. */
0855e32b
NS		 4079 ? (globals->use_blx ? arm_stub_long_branch_any_tls_pic
4080 : arm_stub_long_branch_v4t_thumb_tls_pic)
4081 : ((globals->use_blx && r_type == R_ARM_THM_CALL)
4082 /* V5T PIC and above. */
4083 ? arm_stub_long_branch_any_arm_pic
4084 /* V4T PIC stub. */
4085 : arm_stub_long_branch_v4t_thumb_arm_pic))
c2b4a39d
CL		 4086
4087 /* non-PIC stubs. */
0855e32b 4088 : ((globals->use_blx && r_type == R_ARM_THM_CALL)
c2b4a39d
CL		 4089 /* V5T and above. */
4090 ? arm_stub_long_branch_any_any
4091 /* V4T. */
4092 : arm_stub_long_branch_v4t_thumb_arm);
c820be07
NC		 4093
4094 /* Handle v4t short branches. */
fea2b4d6 4095 if ((stub_type == arm_stub_long_branch_v4t_thumb_arm)
c820be07
NC		 4096 && (branch_offset <= THM_MAX_FWD_BRANCH_OFFSET)
4097 && (branch_offset >= THM_MAX_BWD_BRANCH_OFFSET))
fea2b4d6 4098 stub_type = arm_stub_short_branch_v4t_thumb_arm;
906e58ca
NC		 4099 }
4100 }
4101 }
fe33d2fa
CL		 4102 else if (r_type == R_ARM_CALL
4103 || r_type == R_ARM_JUMP24
0855e32b
NS		 4104 || r_type == R_ARM_PLT32
4105 || r_type == R_ARM_TLS_CALL)
906e58ca 4106 {
d5a67c02
AV		 4107 if (input_sec->flags & SEC_ELF_PURECODE)
4108 (*_bfd_error_handler) (_("%B(%s): warning: long branch "
4109 " veneers used in section with "
4110 "SHF_ARM_PURECODE section "
4111 "attribute is only supported"
4112 " for M-profile targets that "
4113 "implement the movw "
4114 "instruction."));
35fc36a8 4115 if (branch_type == ST_BRANCH_TO_THUMB)
906e58ca
NC		 4116 {
4117 /* Arm to thumb. */
c820be07
NC		 4118
4119 if (sym_sec != NULL
4120 && sym_sec->owner != NULL
4121 && !INTERWORK_FLAG (sym_sec->owner))
4122 {
4123 (*_bfd_error_handler)
4124 (_("%B(%s): warning: interworking not enabled.\n"
c2b4a39d 4125 " first occurrence: %B: ARM call to Thumb"),
c820be07
NC		 4126 sym_sec->owner, input_bfd, name);
4127 }
4128
4129 /* We have an extra 2-bytes reach because of
4130 the mode change (bit 24 (H) of BLX encoding). */
4116d8d7
PB		 4131 if (branch_offset > (ARM_MAX_FWD_BRANCH_OFFSET + 2)
4132 || (branch_offset < ARM_MAX_BWD_BRANCH_OFFSET)
0855e32b 4133 || (r_type == R_ARM_CALL && !globals->use_blx)
4116d8d7
PB		 4134 || (r_type == R_ARM_JUMP24)
4135 || (r_type == R_ARM_PLT32))
906e58ca 4136 {
0e1862bb 4137 stub_type = (bfd_link_pic (info) | globals->pic_veneer)
c2b4a39d 4138 /* PIC stubs. */
ebe24dd4
CL		 4139 ? ((globals->use_blx)
4140 /* V5T and above. */
4141 ? arm_stub_long_branch_any_thumb_pic
4142 /* V4T stub. */
4143 : arm_stub_long_branch_v4t_arm_thumb_pic)
4144
c2b4a39d
CL		 4145 /* non-PIC stubs. */
4146 : ((globals->use_blx)
4147 /* V5T and above. */
4148 ? arm_stub_long_branch_any_any
4149 /* V4T. */
4150 : arm_stub_long_branch_v4t_arm_thumb);
906e58ca
NC		 4151 }
4152 }
4153 else
4154 {
4155 /* Arm to arm. */
4156 if (branch_offset > ARM_MAX_FWD_BRANCH_OFFSET
4157 || (branch_offset < ARM_MAX_BWD_BRANCH_OFFSET))
4158 {
0855e32b 4159 stub_type =
0e1862bb 4160 (bfd_link_pic (info) | globals->pic_veneer)
c2b4a39d 4161 /* PIC stubs. */
0855e32b 4162 ? (r_type == R_ARM_TLS_CALL
6a631e86 4163 /* TLS PIC Stub. */
0855e32b 4164 ? arm_stub_long_branch_any_tls_pic
7a89b94e
NC		 4165 : (globals->nacl_p
4166 ? arm_stub_long_branch_arm_nacl_pic
4167 : arm_stub_long_branch_any_arm_pic))
c2b4a39d 4168 /* non-PIC stubs. */
7a89b94e
NC		 4169 : (globals->nacl_p
4170 ? arm_stub_long_branch_arm_nacl
4171 : arm_stub_long_branch_any_any);
906e58ca
NC		 4172 }
4173 }
4174 }
4175
fe33d2fa
CL		 4176 /* If a stub is needed, record the actual destination type. */
4177 if (stub_type != arm_stub_none)
35fc36a8 4178 *actual_branch_type = branch_type;
fe33d2fa 4179
906e58ca
NC		 4180 return stub_type;
4181}
4182
4183/* Build a name for an entry in the stub hash table. */
4184
4185static char *
4186elf32_arm_stub_name (const asection *input_section,
4187 const asection *sym_sec,
4188 const struct elf32_arm_link_hash_entry *hash,
fe33d2fa
CL		 4189 const Elf_Internal_Rela *rel,
4190 enum elf32_arm_stub_type stub_type)
906e58ca
NC		 4191{
4192 char *stub_name;
4193 bfd_size_type len;
4194
4195 if (hash)
4196 {
fe33d2fa 4197 len = 8 + 1 + strlen (hash->root.root.root.string) + 1 + 8 + 1 + 2 + 1;
21d799b5 4198 stub_name = (char *) bfd_malloc (len);
906e58ca 4199 if (stub_name != NULL)
fe33d2fa 4200 sprintf (stub_name, "%08x_%s+%x_%d",
906e58ca
NC		 4201 input_section->id & 0xffffffff,
4202 hash->root.root.root.string,
fe33d2fa
CL		 4203 (int) rel->r_addend & 0xffffffff,
4204 (int) stub_type);
906e58ca
NC		 4205 }
4206 else
4207 {
fe33d2fa 4208 len = 8 + 1 + 8 + 1 + 8 + 1 + 8 + 1 + 2 + 1;
21d799b5 4209 stub_name = (char *) bfd_malloc (len);
906e58ca 4210 if (stub_name != NULL)
fe33d2fa 4211 sprintf (stub_name, "%08x_%x:%x+%x_%d",
906e58ca
NC		 4212 input_section->id & 0xffffffff,
4213 sym_sec->id & 0xffffffff,
0855e32b
NS		 4214 ELF32_R_TYPE (rel->r_info) == R_ARM_TLS_CALL
4215 || ELF32_R_TYPE (rel->r_info) == R_ARM_THM_TLS_CALL
4216 ? 0 : (int) ELF32_R_SYM (rel->r_info) & 0xffffffff,
fe33d2fa
CL		 4217 (int) rel->r_addend & 0xffffffff,
4218 (int) stub_type);
906e58ca
NC		 4219 }
4220
4221 return stub_name;
4222}
4223
4224/* Look up an entry in the stub hash. Stub entries are cached because
4225 creating the stub name takes a bit of time. */
4226
4227static struct elf32_arm_stub_hash_entry *
4228elf32_arm_get_stub_entry (const asection *input_section,
4229 const asection *sym_sec,
4230 struct elf_link_hash_entry *hash,
4231 const Elf_Internal_Rela *rel,
fe33d2fa
CL		 4232 struct elf32_arm_link_hash_table *htab,
4233 enum elf32_arm_stub_type stub_type)
906e58ca
NC		 4234{
4235 struct elf32_arm_stub_hash_entry *stub_entry;
4236 struct elf32_arm_link_hash_entry *h = (struct elf32_arm_link_hash_entry *) hash;
4237 const asection *id_sec;
4238
4239 if ((input_section->flags & SEC_CODE) == 0)
4240 return NULL;
4241
4242 /* If this input section is part of a group of sections sharing one
4243 stub section, then use the id of the first section in the group.
4244 Stub names need to include a section id, as there may well be
4245 more than one stub used to reach say, printf, and we need to
4246 distinguish between them. */
c2abbbeb 4247 BFD_ASSERT (input_section->id <= htab->top_id);
906e58ca
NC		 4248 id_sec = htab->stub_group[input_section->id].link_sec;
4249
4250 if (h != NULL && h->stub_cache != NULL
4251 && h->stub_cache->h == h
fe33d2fa
CL		 4252 && h->stub_cache->id_sec == id_sec
4253 && h->stub_cache->stub_type == stub_type)
906e58ca
NC		 4254 {
4255 stub_entry = h->stub_cache;
4256 }
4257 else
4258 {
4259 char *stub_name;
4260
fe33d2fa 4261 stub_name = elf32_arm_stub_name (id_sec, sym_sec, h, rel, stub_type);
906e58ca
NC		 4262 if (stub_name == NULL)
4263 return NULL;
4264
4265 stub_entry = arm_stub_hash_lookup (&htab->stub_hash_table,
4266 stub_name, FALSE, FALSE);
4267 if (h != NULL)
4268 h->stub_cache = stub_entry;
4269
4270 free (stub_name);
4271 }
4272
4273 return stub_entry;
4274}
4275
daa4adae
TP		 4276/* Whether veneers of type STUB_TYPE require to be in a dedicated output
4277 section. */
4278
4279static bfd_boolean
4280arm_dedicated_stub_output_section_required (enum elf32_arm_stub_type stub_type)
4281{
4282 if (stub_type >= max_stub_type)
4283 abort (); /* Should be unreachable. */
4284
4ba2ef8f
TP		 4285 switch (stub_type)
4286 {
4287 case arm_stub_cmse_branch_thumb_only:
4288 return TRUE;
4289
4290 default:
4291 return FALSE;
4292 }
4293
4294 abort (); /* Should be unreachable. */
daa4adae
TP		 4295}
4296
4297/* Required alignment (as a power of 2) for the dedicated section holding
4298 veneers of type STUB_TYPE, or 0 if veneers of this type are interspersed
4299 with input sections. */
4300
4301static int
4302arm_dedicated_stub_output_section_required_alignment
4303 (enum elf32_arm_stub_type stub_type)
4304{
4305 if (stub_type >= max_stub_type)
4306 abort (); /* Should be unreachable. */
4307
4ba2ef8f
TP		 4308 switch (stub_type)
4309 {
4310 /* Vectors of Secure Gateway veneers must be aligned on 32byte
4311 boundary. */
4312 case arm_stub_cmse_branch_thumb_only:
4313 return 5;
4314
4315 default:
4316 BFD_ASSERT (!arm_dedicated_stub_output_section_required (stub_type));
4317 return 0;
4318 }
4319
4320 abort (); /* Should be unreachable. */
daa4adae
TP		 4321}
4322
4323/* Name of the dedicated output section to put veneers of type STUB_TYPE, or
4324 NULL if veneers of this type are interspersed with input sections. */
4325
4326static const char *
4327arm_dedicated_stub_output_section_name (enum elf32_arm_stub_type stub_type)
4328{
4329 if (stub_type >= max_stub_type)
4330 abort (); /* Should be unreachable. */
4331
4ba2ef8f
TP		 4332 switch (stub_type)
4333 {
4334 case arm_stub_cmse_branch_thumb_only:
4335 return ".gnu.sgstubs";
4336
4337 default:
4338 BFD_ASSERT (!arm_dedicated_stub_output_section_required (stub_type));
4339 return NULL;
4340 }
4341
4342 abort (); /* Should be unreachable. */
daa4adae
TP		 4343}
4344
4345/* If veneers of type STUB_TYPE should go in a dedicated output section,
4346 returns the address of the hash table field in HTAB holding a pointer to the
4347 corresponding input section. Otherwise, returns NULL. */
4348
4349static asection **
4ba2ef8f
TP		 4350arm_dedicated_stub_input_section_ptr (struct elf32_arm_link_hash_table *htab,
4351 enum elf32_arm_stub_type stub_type)
daa4adae
TP		 4352{
4353 if (stub_type >= max_stub_type)
4354 abort (); /* Should be unreachable. */
4355
4ba2ef8f
TP		 4356 switch (stub_type)
4357 {
4358 case arm_stub_cmse_branch_thumb_only:
4359 return &htab->cmse_stub_sec;
4360
4361 default:
4362 BFD_ASSERT (!arm_dedicated_stub_output_section_required (stub_type));
4363 return NULL;
4364 }
4365
4366 abort (); /* Should be unreachable. */
daa4adae
TP		 4367}
4368
4369/* Find or create a stub section to contain a stub of type STUB_TYPE. SECTION
4370 is the section that branch into veneer and can be NULL if stub should go in
4371 a dedicated output section. Returns a pointer to the stub section, and the
4372 section to which the stub section will be attached (in *LINK_SEC_P).
48229727 4373 LINK_SEC_P may be NULL. */
906e58ca 4374
48229727
JB		 4375static asection *
4376elf32_arm_create_or_find_stub_sec (asection **link_sec_p, asection *section,
daa4adae
TP		 4377 struct elf32_arm_link_hash_table *htab,
4378 enum elf32_arm_stub_type stub_type)
906e58ca 4379{
daa4adae
TP		 4380 asection *link_sec, *out_sec, **stub_sec_p;
4381 const char *stub_sec_prefix;
4382 bfd_boolean dedicated_output_section =
4383 arm_dedicated_stub_output_section_required (stub_type);
4384 int align;
906e58ca 4385
daa4adae 4386 if (dedicated_output_section)
906e58ca 4387 {
daa4adae
TP		 4388 bfd *output_bfd = htab->obfd;
4389 const char *out_sec_name =
4390 arm_dedicated_stub_output_section_name (stub_type);
4391 link_sec = NULL;
4392 stub_sec_p = arm_dedicated_stub_input_section_ptr (htab, stub_type);
4393 stub_sec_prefix = out_sec_name;
4394 align = arm_dedicated_stub_output_section_required_alignment (stub_type);
4395 out_sec = bfd_get_section_by_name (output_bfd, out_sec_name);
4396 if (out_sec == NULL)
906e58ca 4397 {
daa4adae
TP		 4398 (*_bfd_error_handler) (_("No address assigned to the veneers output "
4399 "section %s"), out_sec_name);
4400 return NULL;
906e58ca 4401 }
daa4adae
TP		 4402 }
4403 else
4404 {
c2abbbeb 4405 BFD_ASSERT (section->id <= htab->top_id);
daa4adae
TP		 4406 link_sec = htab->stub_group[section->id].link_sec;
4407 BFD_ASSERT (link_sec != NULL);
4408 stub_sec_p = &htab->stub_group[section->id].stub_sec;
4409 if (*stub_sec_p == NULL)
4410 stub_sec_p = &htab->stub_group[link_sec->id].stub_sec;
4411 stub_sec_prefix = link_sec->name;
4412 out_sec = link_sec->output_section;
4413 align = htab->nacl_p ? 4 : 3;
906e58ca 4414 }
b38cadfb 4415
daa4adae
TP		 4416 if (*stub_sec_p == NULL)
4417 {
4418 size_t namelen;
4419 bfd_size_type len;
4420 char *s_name;
4421
4422 namelen = strlen (stub_sec_prefix);
4423 len = namelen + sizeof (STUB_SUFFIX);
4424 s_name = (char *) bfd_alloc (htab->stub_bfd, len);
4425 if (s_name == NULL)
4426 return NULL;
4427
4428 memcpy (s_name, stub_sec_prefix, namelen);
4429 memcpy (s_name + namelen, STUB_SUFFIX, sizeof (STUB_SUFFIX));
4430 *stub_sec_p = (*htab->add_stub_section) (s_name, out_sec, link_sec,
4431 align);
4432 if (*stub_sec_p == NULL)
4433 return NULL;
4434
4435 out_sec->flags |= SEC_ALLOC | SEC_LOAD | SEC_READONLY | SEC_CODE
4436 | SEC_HAS_CONTENTS | SEC_RELOC | SEC_IN_MEMORY
4437 | SEC_KEEP;
4438 }
4439
4440 if (!dedicated_output_section)
4441 htab->stub_group[section->id].stub_sec = *stub_sec_p;
4442
48229727
JB		 4443 if (link_sec_p)
4444 *link_sec_p = link_sec;
b38cadfb 4445
daa4adae 4446 return *stub_sec_p;
48229727
JB		 4447}
4448
4449/* Add a new stub entry to the stub hash. Not all fields of the new
4450 stub entry are initialised. */
4451
4452static struct elf32_arm_stub_hash_entry *
daa4adae
TP		 4453elf32_arm_add_stub (const char *stub_name, asection *section,
4454 struct elf32_arm_link_hash_table *htab,
4455 enum elf32_arm_stub_type stub_type)
48229727
JB		 4456{
4457 asection *link_sec;
4458 asection *stub_sec;
4459 struct elf32_arm_stub_hash_entry *stub_entry;
4460
daa4adae
TP		 4461 stub_sec = elf32_arm_create_or_find_stub_sec (&link_sec, section, htab,
4462 stub_type);
48229727
JB		 4463 if (stub_sec == NULL)
4464 return NULL;
906e58ca
NC		 4465
4466 /* Enter this entry into the linker stub hash table. */
4467 stub_entry = arm_stub_hash_lookup (&htab->stub_hash_table, stub_name,
4468 TRUE, FALSE);
4469 if (stub_entry == NULL)
4470 {
6bde4c52
TP		 4471 if (section == NULL)
4472 section = stub_sec;
906e58ca
NC		 4473 (*_bfd_error_handler) (_("%s: cannot create stub entry %s"),
4474 section->owner,
4475 stub_name);
4476 return NULL;
4477 }
4478
4479 stub_entry->stub_sec = stub_sec;
0955507f 4480 stub_entry->stub_offset = (bfd_vma) -1;
906e58ca
NC		 4481 stub_entry->id_sec = link_sec;
4482
906e58ca
NC		 4483 return stub_entry;
4484}
4485
4486/* Store an Arm insn into an output section not processed by
4487 elf32_arm_write_section. */
4488
4489static void
8029a119
NC		 4490put_arm_insn (struct elf32_arm_link_hash_table * htab,
4491 bfd * output_bfd, bfd_vma val, void * ptr)
906e58ca
NC		 4492{
4493 if (htab->byteswap_code != bfd_little_endian (output_bfd))
4494 bfd_putl32 (val, ptr);
4495 else
4496 bfd_putb32 (val, ptr);
4497}
4498
4499/* Store a 16-bit Thumb insn into an output section not processed by
4500 elf32_arm_write_section. */
4501
4502static void
8029a119
NC		 4503put_thumb_insn (struct elf32_arm_link_hash_table * htab,
4504 bfd * output_bfd, bfd_vma val, void * ptr)
906e58ca
NC		 4505{
4506 if (htab->byteswap_code != bfd_little_endian (output_bfd))
4507 bfd_putl16 (val, ptr);
4508 else
4509 bfd_putb16 (val, ptr);
4510}
4511
a504d23a
LA		 4512/* Store a Thumb2 insn into an output section not processed by
4513 elf32_arm_write_section. */
4514
4515static void
4516put_thumb2_insn (struct elf32_arm_link_hash_table * htab,
b98e6871 4517 bfd * output_bfd, bfd_vma val, bfd_byte * ptr)
a504d23a
LA		 4518{
4519 /* T2 instructions are 16-bit streamed. */
4520 if (htab->byteswap_code != bfd_little_endian (output_bfd))
4521 {
4522 bfd_putl16 ((val >> 16) & 0xffff, ptr);
4523 bfd_putl16 ((val & 0xffff), ptr + 2);
4524 }
4525 else
4526 {
4527 bfd_putb16 ((val >> 16) & 0xffff, ptr);
4528 bfd_putb16 ((val & 0xffff), ptr + 2);
4529 }
4530}
4531
0855e32b
NS		 4532/* If it's possible to change R_TYPE to a more efficient access
4533 model, return the new reloc type. */
4534
4535static unsigned
b38cadfb 4536elf32_arm_tls_transition (struct bfd_link_info *info, int r_type,
0855e32b
NS		 4537 struct elf_link_hash_entry *h)
4538{
4539 int is_local = (h == NULL);
4540
0e1862bb
L		 4541 if (bfd_link_pic (info)
4542 || (h && h->root.type == bfd_link_hash_undefweak))
0855e32b
NS		 4543 return r_type;
4544
b38cadfb 4545 /* We do not support relaxations for Old TLS models. */
0855e32b
NS		 4546 switch (r_type)
4547 {
4548 case R_ARM_TLS_GOTDESC:
4549 case R_ARM_TLS_CALL:
4550 case R_ARM_THM_TLS_CALL:
4551 case R_ARM_TLS_DESCSEQ:
4552 case R_ARM_THM_TLS_DESCSEQ:
4553 return is_local ? R_ARM_TLS_LE32 : R_ARM_TLS_IE32;
4554 }
4555
4556 return r_type;
4557}
4558
48229727
JB		 4559static bfd_reloc_status_type elf32_arm_final_link_relocate
4560 (reloc_howto_type *, bfd *, bfd *, asection *, bfd_byte *,
4561 Elf_Internal_Rela *, bfd_vma, struct bfd_link_info *, asection *,
34e77a92
RS		 4562 const char *, unsigned char, enum arm_st_branch_type,
4563 struct elf_link_hash_entry *, bfd_boolean *, char **);
48229727 4564
4563a860
JB		 4565static unsigned int
4566arm_stub_required_alignment (enum elf32_arm_stub_type stub_type)
4567{
4568 switch (stub_type)
4569 {
4570 case arm_stub_a8_veneer_b_cond:
4571 case arm_stub_a8_veneer_b:
4572 case arm_stub_a8_veneer_bl:
4573 return 2;
4574
4575 case arm_stub_long_branch_any_any:
4576 case arm_stub_long_branch_v4t_arm_thumb:
4577 case arm_stub_long_branch_thumb_only:
80c135e5 4578 case arm_stub_long_branch_thumb2_only:
d5a67c02 4579 case arm_stub_long_branch_thumb2_only_pure:
4563a860
JB		 4580 case arm_stub_long_branch_v4t_thumb_thumb:
4581 case arm_stub_long_branch_v4t_thumb_arm:
4582 case arm_stub_short_branch_v4t_thumb_arm:
4583 case arm_stub_long_branch_any_arm_pic:
4584 case arm_stub_long_branch_any_thumb_pic:
4585 case arm_stub_long_branch_v4t_thumb_thumb_pic:
4586 case arm_stub_long_branch_v4t_arm_thumb_pic:
4587 case arm_stub_long_branch_v4t_thumb_arm_pic:
4588 case arm_stub_long_branch_thumb_only_pic:
0855e32b
NS		 4589 case arm_stub_long_branch_any_tls_pic:
4590 case arm_stub_long_branch_v4t_thumb_tls_pic:
4ba2ef8f 4591 case arm_stub_cmse_branch_thumb_only:
4563a860
JB		 4592 case arm_stub_a8_veneer_blx:
4593 return 4;
b38cadfb 4594
7a89b94e
NC		 4595 case arm_stub_long_branch_arm_nacl:
4596 case arm_stub_long_branch_arm_nacl_pic:
4597 return 16;
4598
4563a860
JB		 4599 default:
4600 abort (); /* Should be unreachable. */
4601 }
4602}
4603
4f4faa4d
TP		 4604/* Returns whether stubs of type STUB_TYPE take over the symbol they are
4605 veneering (TRUE) or have their own symbol (FALSE). */
4606
4607static bfd_boolean
4608arm_stub_sym_claimed (enum elf32_arm_stub_type stub_type)
4609{
4610 if (stub_type >= max_stub_type)
4611 abort (); /* Should be unreachable. */
4612
4ba2ef8f
TP		 4613 switch (stub_type)
4614 {
4615 case arm_stub_cmse_branch_thumb_only:
4616 return TRUE;
4617
4618 default:
4619 return FALSE;
4620 }
4621
4622 abort (); /* Should be unreachable. */
4f4faa4d
TP		 4623}
4624
d7c5bd02
TP		 4625/* Returns the padding needed for the dedicated section used stubs of type
4626 STUB_TYPE. */
4627
4628static int
4629arm_dedicated_stub_section_padding (enum elf32_arm_stub_type stub_type)
4630{
4631 if (stub_type >= max_stub_type)
4632 abort (); /* Should be unreachable. */
4633
4ba2ef8f
TP		 4634 switch (stub_type)
4635 {
4636 case arm_stub_cmse_branch_thumb_only:
4637 return 32;
4638
4639 default:
4640 return 0;
4641 }
4642
4643 abort (); /* Should be unreachable. */
d7c5bd02
TP		 4644}
4645
0955507f
TP		 4646/* If veneers of type STUB_TYPE should go in a dedicated output section,
4647 returns the address of the hash table field in HTAB holding the offset at
4648 which new veneers should be layed out in the stub section. */
4649
4650static bfd_vma*
4651arm_new_stubs_start_offset_ptr (struct elf32_arm_link_hash_table *htab,
4652 enum elf32_arm_stub_type stub_type)
4653{
4654 switch (stub_type)
4655 {
4656 case arm_stub_cmse_branch_thumb_only:
4657 return &htab->new_cmse_stub_offset;
4658
4659 default:
4660 BFD_ASSERT (!arm_dedicated_stub_output_section_required (stub_type));
4661 return NULL;
4662 }
4663}
4664
906e58ca
NC		 4665static bfd_boolean
4666arm_build_one_stub (struct bfd_hash_entry *gen_entry,
4667 void * in_arg)
4668{
7a89b94e 4669#define MAXRELOCS 3
0955507f 4670 bfd_boolean removed_sg_veneer;
906e58ca 4671 struct elf32_arm_stub_hash_entry *stub_entry;
4dfe6ac6 4672 struct elf32_arm_link_hash_table *globals;
906e58ca 4673 struct bfd_link_info *info;
906e58ca
NC		 4674 asection *stub_sec;
4675 bfd *stub_bfd;
906e58ca
NC		 4676 bfd_byte *loc;
4677 bfd_vma sym_value;
4678 int template_size;
4679 int size;
d3ce72d0 4680 const insn_sequence *template_sequence;
906e58ca 4681 int i;
48229727
JB		 4682 int stub_reloc_idx[MAXRELOCS] = {-1, -1};
4683 int stub_reloc_offset[MAXRELOCS] = {0, 0};
4684 int nrelocs = 0;
0955507f 4685 int just_allocated = 0;
906e58ca
NC		 4686
4687 /* Massage our args to the form they really have. */
4688 stub_entry = (struct elf32_arm_stub_hash_entry *) gen_entry;
4689 info = (struct bfd_link_info *) in_arg;
4690
4691 globals = elf32_arm_hash_table (info);
4dfe6ac6
NC		 4692 if (globals == NULL)
4693 return FALSE;
906e58ca 4694
906e58ca
NC		 4695 stub_sec = stub_entry->stub_sec;
4696
4dfe6ac6 4697 if ((globals->fix_cortex_a8 < 0)
4563a860
JB		 4698 != (arm_stub_required_alignment (stub_entry->stub_type) == 2))
4699 /* We have to do less-strictly-aligned fixes last. */
eb7c4339 4700 return TRUE;
fe33d2fa 4701
0955507f
TP		 4702 /* Assign a slot at the end of section if none assigned yet. */
4703 if (stub_entry->stub_offset == (bfd_vma) -1)
4704 {
4705 stub_entry->stub_offset = stub_sec->size;
4706 just_allocated = 1;
4707 }
906e58ca
NC		 4708 loc = stub_sec->contents + stub_entry->stub_offset;
4709
4710 stub_bfd = stub_sec->owner;
4711
906e58ca
NC		 4712 /* This is the address of the stub destination. */
4713 sym_value = (stub_entry->target_value
4714 + stub_entry->target_section->output_offset
4715 + stub_entry->target_section->output_section->vma);
4716
d3ce72d0 4717 template_sequence = stub_entry->stub_template;
461a49ca 4718 template_size = stub_entry->stub_template_size;
906e58ca
NC		 4719
4720 size = 0;
461a49ca 4721 for (i = 0; i < template_size; i++)
906e58ca 4722 {
d3ce72d0 4723 switch (template_sequence[i].type)
461a49ca
DJ		 4724 {
4725 case THUMB16_TYPE:
48229727 4726 {
d3ce72d0
NC		 4727 bfd_vma data = (bfd_vma) template_sequence[i].data;
4728 if (template_sequence[i].reloc_addend != 0)
48229727 4729 {
99059e56
RM		 4730 /* We've borrowed the reloc_addend field to mean we should
4731 insert a condition code into this (Thumb-1 branch)
4732 instruction. See THUMB16_BCOND_INSN. */
4733 BFD_ASSERT ((data & 0xff00) == 0xd000);
4734 data |= ((stub_entry->orig_insn >> 22) & 0xf) << 8;
48229727 4735 }
fe33d2fa 4736 bfd_put_16 (stub_bfd, data, loc + size);
48229727
JB		 4737 size += 2;
4738 }
461a49ca 4739 break;
906e58ca 4740
48229727 4741 case THUMB32_TYPE:
fe33d2fa
CL		 4742 bfd_put_16 (stub_bfd,
4743 (template_sequence[i].data >> 16) & 0xffff,
4744 loc + size);
4745 bfd_put_16 (stub_bfd, template_sequence[i].data & 0xffff,
4746 loc + size + 2);
99059e56
RM		 4747 if (template_sequence[i].r_type != R_ARM_NONE)
4748 {
4749 stub_reloc_idx[nrelocs] = i;
4750 stub_reloc_offset[nrelocs++] = size;
4751 }
4752 size += 4;
4753 break;
48229727 4754
461a49ca 4755 case ARM_TYPE:
fe33d2fa
CL		 4756 bfd_put_32 (stub_bfd, template_sequence[i].data,
4757 loc + size);
461a49ca
DJ		 4758 /* Handle cases where the target is encoded within the
4759 instruction. */
d3ce72d0 4760 if (template_sequence[i].r_type == R_ARM_JUMP24)
461a49ca 4761 {
48229727
JB		 4762 stub_reloc_idx[nrelocs] = i;
4763 stub_reloc_offset[nrelocs++] = size;
461a49ca
DJ		 4764 }
4765 size += 4;
4766 break;
4767
4768 case DATA_TYPE:
d3ce72d0 4769 bfd_put_32 (stub_bfd, template_sequence[i].data, loc + size);
48229727
JB		 4770 stub_reloc_idx[nrelocs] = i;
4771 stub_reloc_offset[nrelocs++] = size;
461a49ca
DJ		 4772 size += 4;
4773 break;
4774
4775 default:
4776 BFD_FAIL ();
4777 return FALSE;
4778 }
906e58ca 4779 }
461a49ca 4780
0955507f
TP		 4781 if (just_allocated)
4782 stub_sec->size += size;
906e58ca 4783
461a49ca
DJ		 4784 /* Stub size has already been computed in arm_size_one_stub. Check
4785 consistency. */
4786 BFD_ASSERT (size == stub_entry->stub_size);
4787
906e58ca 4788 /* Destination is Thumb. Force bit 0 to 1 to reflect this. */
35fc36a8 4789 if (stub_entry->branch_type == ST_BRANCH_TO_THUMB)
906e58ca
NC		 4790 sym_value |= 1;
4791
0955507f
TP		 4792 /* Assume non empty slots have at least one and at most MAXRELOCS entries
4793 to relocate in each stub. */
4794 removed_sg_veneer =
4795 (size == 0 && stub_entry->stub_type == arm_stub_cmse_branch_thumb_only);
4796 BFD_ASSERT (removed_sg_veneer || (nrelocs != 0 && nrelocs <= MAXRELOCS));
c820be07 4797
48229727 4798 for (i = 0; i < nrelocs; i++)
8d9d9490
TP		 4799 {
4800 Elf_Internal_Rela rel;
4801 bfd_boolean unresolved_reloc;
4802 char *error_message;
4803 bfd_vma points_to =
4804 sym_value + template_sequence[stub_reloc_idx[i]].reloc_addend;
4805
4806 rel.r_offset = stub_entry->stub_offset + stub_reloc_offset[i];
4807 rel.r_info = ELF32_R_INFO (0,
4808 template_sequence[stub_reloc_idx[i]].r_type);
4809 rel.r_addend = 0;
4810
4811 if (stub_entry->stub_type == arm_stub_a8_veneer_b_cond && i == 0)
4812 /* The first relocation in the elf32_arm_stub_a8_veneer_b_cond[]
4813 template should refer back to the instruction after the original
4814 branch. We use target_section as Cortex-A8 erratum workaround stubs
4815 are only generated when both source and target are in the same
4816 section. */
4817 points_to = stub_entry->target_section->output_section->vma
4818 + stub_entry->target_section->output_offset
4819 + stub_entry->source_value;
4820
4821 elf32_arm_final_link_relocate (elf32_arm_howto_from_type
4822 (template_sequence[stub_reloc_idx[i]].r_type),
4823 stub_bfd, info->output_bfd, stub_sec, stub_sec->contents, &rel,
4824 points_to, info, stub_entry->target_section, "", STT_FUNC,
4825 stub_entry->branch_type,
4826 (struct elf_link_hash_entry *) stub_entry->h, &unresolved_reloc,
4827 &error_message);
4828 }
906e58ca
NC		 4829
4830 return TRUE;
48229727 4831#undef MAXRELOCS
906e58ca
NC		 4832}
4833
48229727
JB		 4834/* Calculate the template, template size and instruction size for a stub.
4835 Return value is the instruction size. */
906e58ca 4836
48229727
JB		 4837static unsigned int
4838find_stub_size_and_template (enum elf32_arm_stub_type stub_type,
4839 const insn_sequence **stub_template,
4840 int *stub_template_size)
906e58ca 4841{
d3ce72d0 4842 const insn_sequence *template_sequence = NULL;
48229727
JB		 4843 int template_size = 0, i;
4844 unsigned int size;
906e58ca 4845
d3ce72d0 4846 template_sequence = stub_definitions[stub_type].template_sequence;
2a229407
AM		 4847 if (stub_template)
4848 *stub_template = template_sequence;
4849
48229727 4850 template_size = stub_definitions[stub_type].template_size;
2a229407
AM		 4851 if (stub_template_size)
4852 *stub_template_size = template_size;
906e58ca
NC		 4853
4854 size = 0;
461a49ca
DJ		 4855 for (i = 0; i < template_size; i++)
4856 {
d3ce72d0 4857 switch (template_sequence[i].type)
461a49ca
DJ		 4858 {
4859 case THUMB16_TYPE:
4860 size += 2;
4861 break;
4862
4863 case ARM_TYPE:
48229727 4864 case THUMB32_TYPE:
461a49ca
DJ		 4865 case DATA_TYPE:
4866 size += 4;
4867 break;
4868
4869 default:
4870 BFD_FAIL ();
2a229407 4871 return 0;
461a49ca
DJ		 4872 }
4873 }
4874
48229727
JB		 4875 return size;
4876}
4877
4878/* As above, but don't actually build the stub. Just bump offset so
4879 we know stub section sizes. */
4880
4881static bfd_boolean
4882arm_size_one_stub (struct bfd_hash_entry *gen_entry,
c7e2358a 4883 void *in_arg ATTRIBUTE_UNUSED)
48229727
JB		 4884{
4885 struct elf32_arm_stub_hash_entry *stub_entry;
d3ce72d0 4886 const insn_sequence *template_sequence;
48229727
JB		 4887 int template_size, size;
4888
4889 /* Massage our args to the form they really have. */
4890 stub_entry = (struct elf32_arm_stub_hash_entry *) gen_entry;
48229727
JB		 4891
4892 BFD_ASSERT((stub_entry->stub_type > arm_stub_none)
4893 && stub_entry->stub_type < ARRAY_SIZE(stub_definitions));
4894
d3ce72d0 4895 size = find_stub_size_and_template (stub_entry->stub_type, &template_sequence,
48229727
JB		 4896 &template_size);
4897
0955507f
TP		 4898 /* Initialized to -1. Null size indicates an empty slot full of zeros. */
4899 if (stub_entry->stub_template_size)
4900 {
4901 stub_entry->stub_size = size;
4902 stub_entry->stub_template = template_sequence;
4903 stub_entry->stub_template_size = template_size;
4904 }
4905
4906 /* Already accounted for. */
4907 if (stub_entry->stub_offset != (bfd_vma) -1)
4908 return TRUE;
461a49ca 4909
906e58ca
NC		 4910 size = (size + 7) & ~7;
4911 stub_entry->stub_sec->size += size;
461a49ca 4912
906e58ca
NC		 4913 return TRUE;
4914}
4915
4916/* External entry points for sizing and building linker stubs. */
4917
4918/* Set up various things so that we can make a list of input sections
4919 for each output section included in the link. Returns -1 on error,
4920 0 when no stubs will be needed, and 1 on success. */
4921
4922int
4923elf32_arm_setup_section_lists (bfd *output_bfd,
4924 struct bfd_link_info *info)
4925{
4926 bfd *input_bfd;
4927 unsigned int bfd_count;
7292b3ac 4928 unsigned int top_id, top_index;
906e58ca
NC		 4929 asection *section;
4930 asection **input_list, **list;
4931 bfd_size_type amt;
4932 struct elf32_arm_link_hash_table *htab = elf32_arm_hash_table (info);
4933
4dfe6ac6
NC		 4934 if (htab == NULL)
4935 return 0;
906e58ca
NC		 4936 if (! is_elf_hash_table (htab))
4937 return 0;
4938
4939 /* Count the number of input BFDs and find the top input section id. */
4940 for (input_bfd = info->input_bfds, bfd_count = 0, top_id = 0;
4941 input_bfd != NULL;
c72f2fb2 4942 input_bfd = input_bfd->link.next)
906e58ca
NC		 4943 {
4944 bfd_count += 1;
4945 for (section = input_bfd->sections;
4946 section != NULL;
4947 section = section->next)
4948 {
4949 if (top_id < section->id)
4950 top_id = section->id;
4951 }
4952 }
4953 htab->bfd_count = bfd_count;
4954
4955 amt = sizeof (struct map_stub) * (top_id + 1);
21d799b5 4956 htab->stub_group = (struct map_stub *) bfd_zmalloc (amt);
906e58ca
NC		 4957 if (htab->stub_group == NULL)
4958 return -1;
fe33d2fa 4959 htab->top_id = top_id;
906e58ca
NC		 4960
4961 /* We can't use output_bfd->section_count here to find the top output
4962 section index as some sections may have been removed, and
4963 _bfd_strip_section_from_output doesn't renumber the indices. */
4964 for (section = output_bfd->sections, top_index = 0;
4965 section != NULL;
4966 section = section->next)
4967 {
4968 if (top_index < section->index)
4969 top_index = section->index;
4970 }
4971
4972 htab->top_index = top_index;
4973 amt = sizeof (asection *) * (top_index + 1);
21d799b5 4974 input_list = (asection **) bfd_malloc (amt);
906e58ca
NC		 4975 htab->input_list = input_list;
4976 if (input_list == NULL)
4977 return -1;
4978
4979 /* For sections we aren't interested in, mark their entries with a
4980 value we can check later. */
4981 list = input_list + top_index;
4982 do
4983 *list = bfd_abs_section_ptr;
4984 while (list-- != input_list);
4985
4986 for (section = output_bfd->sections;
4987 section != NULL;
4988 section = section->next)
4989 {
4990 if ((section->flags & SEC_CODE) != 0)
4991 input_list[section->index] = NULL;
4992 }
4993
4994 return 1;
4995}
4996
4997/* The linker repeatedly calls this function for each input section,
4998 in the order that input sections are linked into output sections.
4999 Build lists of input sections to determine groupings between which
5000 we may insert linker stubs. */
5001
5002void
5003elf32_arm_next_input_section (struct bfd_link_info *info,
5004 asection *isec)
5005{
5006 struct elf32_arm_link_hash_table *htab = elf32_arm_hash_table (info);
5007
4dfe6ac6
NC		 5008 if (htab == NULL)
5009 return;
5010
906e58ca
NC		 5011 if (isec->output_section->index <= htab->top_index)
5012 {
5013 asection **list = htab->input_list + isec->output_section->index;
5014
a7470592 5015 if (*list != bfd_abs_section_ptr && (isec->flags & SEC_CODE) != 0)
906e58ca
NC		 5016 {
5017 /* Steal the link_sec pointer for our list. */
5018#define PREV_SEC(sec) (htab->stub_group[(sec)->id].link_sec)
5019 /* This happens to make the list in reverse order,
07d72278 5020 which we reverse later. */
906e58ca
NC		 5021 PREV_SEC (isec) = *list;
5022 *list = isec;
5023 }
5024 }
5025}
5026
5027/* See whether we can group stub sections together. Grouping stub
5028 sections may result in fewer stubs. More importantly, we need to
07d72278 5029 put all .init* and .fini* stubs at the end of the .init or
906e58ca
NC		 5030 .fini output sections respectively, because glibc splits the
5031 _init and _fini functions into multiple parts. Putting a stub in
5032 the middle of a function is not a good idea. */
5033
5034static void
5035group_sections (struct elf32_arm_link_hash_table *htab,
5036 bfd_size_type stub_group_size,
07d72278 5037 bfd_boolean stubs_always_after_branch)
906e58ca 5038{
07d72278 5039 asection **list = htab->input_list;
906e58ca
NC		 5040
5041 do
5042 {
5043 asection *tail = *list;
07d72278 5044 asection *head;
906e58ca
NC		 5045
5046 if (tail == bfd_abs_section_ptr)
5047 continue;
5048
07d72278
DJ		 5049 /* Reverse the list: we must avoid placing stubs at the
5050 beginning of the section because the beginning of the text
5051 section may be required for an interrupt vector in bare metal
5052 code. */
5053#define NEXT_SEC PREV_SEC
e780aef2
CL		 5054 head = NULL;
5055 while (tail != NULL)
99059e56
RM		 5056 {
5057 /* Pop from tail. */
5058 asection *item = tail;
5059 tail = PREV_SEC (item);
e780aef2 5060
99059e56
RM		 5061 /* Push on head. */
5062 NEXT_SEC (item) = head;
5063 head = item;
5064 }
07d72278
DJ		 5065
5066 while (head != NULL)
906e58ca
NC		 5067 {
5068 asection *curr;
07d72278 5069 asection *next;
e780aef2
CL		 5070 bfd_vma stub_group_start = head->output_offset;
5071 bfd_vma end_of_next;
906e58ca 5072
07d72278 5073 curr = head;
e780aef2 5074 while (NEXT_SEC (curr) != NULL)
8cd931b7 5075 {
e780aef2
CL		 5076 next = NEXT_SEC (curr);
5077 end_of_next = next->output_offset + next->size;
5078 if (end_of_next - stub_group_start >= stub_group_size)
5079 /* End of NEXT is too far from start, so stop. */
8cd931b7 5080 break;
e780aef2
CL		 5081 /* Add NEXT to the group. */
5082 curr = next;
8cd931b7 5083 }
906e58ca 5084
07d72278 5085 /* OK, the size from the start to the start of CURR is less
906e58ca 5086 than stub_group_size and thus can be handled by one stub
07d72278 5087 section. (Or the head section is itself larger than
906e58ca
NC		 5088 stub_group_size, in which case we may be toast.)
5089 We should really be keeping track of the total size of
5090 stubs added here, as stubs contribute to the final output
7fb9f789 5091 section size. */
906e58ca
NC		 5092 do
5093 {
07d72278 5094 next = NEXT_SEC (head);
906e58ca 5095 /* Set up this stub group. */
07d72278 5096 htab->stub_group[head->id].link_sec = curr;
906e58ca 5097 }
07d72278 5098 while (head != curr && (head = next) != NULL);
906e58ca
NC		 5099
5100 /* But wait, there's more! Input sections up to stub_group_size
07d72278
DJ		 5101 bytes after the stub section can be handled by it too. */
5102 if (!stubs_always_after_branch)
906e58ca 5103 {
e780aef2
CL		 5104 stub_group_start = curr->output_offset + curr->size;
5105
8cd931b7 5106 while (next != NULL)
906e58ca 5107 {
e780aef2
CL		 5108 end_of_next = next->output_offset + next->size;
5109 if (end_of_next - stub_group_start >= stub_group_size)
5110 /* End of NEXT is too far from stubs, so stop. */
8cd931b7 5111 break;
e780aef2 5112 /* Add NEXT to the stub group. */
07d72278
DJ		 5113 head = next;
5114 next = NEXT_SEC (head);
5115 htab->stub_group[head->id].link_sec = curr;
906e58ca
NC		 5116 }
5117 }
07d72278 5118 head = next;
906e58ca
NC		 5119 }
5120 }
07d72278 5121 while (list++ != htab->input_list + htab->top_index);
906e58ca
NC		 5122
5123 free (htab->input_list);
5124#undef PREV_SEC
07d72278 5125#undef NEXT_SEC
906e58ca
NC		 5126}
5127
48229727
JB		 5128/* Comparison function for sorting/searching relocations relating to Cortex-A8
5129 erratum fix. */
5130
5131static int
5132a8_reloc_compare (const void *a, const void *b)
5133{
21d799b5
NC		 5134 const struct a8_erratum_reloc *ra = (const struct a8_erratum_reloc *) a;
5135 const struct a8_erratum_reloc *rb = (const struct a8_erratum_reloc *) b;
48229727
JB		 5136
5137 if (ra->from < rb->from)
5138 return -1;
5139 else if (ra->from > rb->from)
5140 return 1;
5141 else
5142 return 0;
5143}
5144
5145static struct elf_link_hash_entry *find_thumb_glue (struct bfd_link_info *,
5146 const char *, char **);
5147
5148/* Helper function to scan code for sequences which might trigger the Cortex-A8
5149 branch/TLB erratum. Fill in the table described by A8_FIXES_P,
81694485 5150 NUM_A8_FIXES_P, A8_FIX_TABLE_SIZE_P. Returns true if an error occurs, false
48229727
JB		 5151 otherwise. */
5152
81694485
NC		 5153static bfd_boolean
5154cortex_a8_erratum_scan (bfd *input_bfd,
5155 struct bfd_link_info *info,
48229727
JB		 5156 struct a8_erratum_fix **a8_fixes_p,
5157 unsigned int *num_a8_fixes_p,
5158 unsigned int *a8_fix_table_size_p,
5159 struct a8_erratum_reloc *a8_relocs,
eb7c4339
NS		 5160 unsigned int num_a8_relocs,
5161 unsigned prev_num_a8_fixes,
5162 bfd_boolean *stub_changed_p)
48229727
JB		 5163{
5164 asection *section;
5165 struct elf32_arm_link_hash_table *htab = elf32_arm_hash_table (info);
5166 struct a8_erratum_fix *a8_fixes = *a8_fixes_p;
5167 unsigned int num_a8_fixes = *num_a8_fixes_p;
5168 unsigned int a8_fix_table_size = *a8_fix_table_size_p;
5169
4dfe6ac6
NC		 5170 if (htab == NULL)
5171 return FALSE;
5172
48229727
JB		 5173 for (section = input_bfd->sections;
5174 section != NULL;
5175 section = section->next)
5176 {
5177 bfd_byte *contents = NULL;
5178 struct _arm_elf_section_data *sec_data;
5179 unsigned int span;
5180 bfd_vma base_vma;
5181
5182 if (elf_section_type (section) != SHT_PROGBITS
99059e56
RM		 5183 || (elf_section_flags (section) & SHF_EXECINSTR) == 0
5184 || (section->flags & SEC_EXCLUDE) != 0
5185 || (section->sec_info_type == SEC_INFO_TYPE_JUST_SYMS)
5186 || (section->output_section == bfd_abs_section_ptr))
5187 continue;
48229727
JB		 5188
5189 base_vma = section->output_section->vma + section->output_offset;
5190
5191 if (elf_section_data (section)->this_hdr.contents != NULL)
99059e56 5192 contents = elf_section_data (section)->this_hdr.contents;
48229727 5193 else if (! bfd_malloc_and_get_section (input_bfd, section, &contents))
99059e56 5194 return TRUE;
48229727
JB		 5195
5196 sec_data = elf32_arm_section_data (section);
5197
5198 for (span = 0; span < sec_data->mapcount; span++)
99059e56
RM		 5199 {
5200 unsigned int span_start = sec_data->map[span].vma;
5201 unsigned int span_end = (span == sec_data->mapcount - 1)
5202 ? section->size : sec_data->map[span + 1].vma;
5203 unsigned int i;
5204 char span_type = sec_data->map[span].type;
5205 bfd_boolean last_was_32bit = FALSE, last_was_branch = FALSE;
5206
5207 if (span_type != 't')
5208 continue;
5209
5210 /* Span is entirely within a single 4KB region: skip scanning. */
5211 if (((base_vma + span_start) & ~0xfff)
48229727 5212 == ((base_vma + span_end) & ~0xfff))
99059e56
RM		 5213 continue;
5214
5215 /* Scan for 32-bit Thumb-2 branches which span two 4K regions, where:
5216
5217 * The opcode is BLX.W, BL.W, B.W, Bcc.W
5218 * The branch target is in the same 4KB region as the
5219 first half of the branch.
5220 * The instruction before the branch is a 32-bit
5221 length non-branch instruction. */
5222 for (i = span_start; i < span_end;)
5223 {
5224 unsigned int insn = bfd_getl16 (&contents[i]);
5225 bfd_boolean insn_32bit = FALSE, is_blx = FALSE, is_b = FALSE;
48229727
JB		 5226 bfd_boolean is_bl = FALSE, is_bcc = FALSE, is_32bit_branch;
5227
99059e56
RM		 5228 if ((insn & 0xe000) == 0xe000 && (insn & 0x1800) != 0x0000)
5229 insn_32bit = TRUE;
48229727
JB		 5230
5231 if (insn_32bit)
99059e56
RM		 5232 {
5233 /* Load the rest of the insn (in manual-friendly order). */
5234 insn = (insn << 16) | bfd_getl16 (&contents[i + 2]);
5235
5236 /* Encoding T4: B<c>.W. */
5237 is_b = (insn & 0xf800d000) == 0xf0009000;
5238 /* Encoding T1: BL<c>.W. */
5239 is_bl = (insn & 0xf800d000) == 0xf000d000;
5240 /* Encoding T2: BLX<c>.W. */
5241 is_blx = (insn & 0xf800d000) == 0xf000c000;
48229727
JB		 5242 /* Encoding T3: B<c>.W (not permitted in IT block). */
5243 is_bcc = (insn & 0xf800d000) == 0xf0008000
5244 && (insn & 0x07f00000) != 0x03800000;
5245 }
5246
5247 is_32bit_branch = is_b || is_bl || is_blx || is_bcc;
fe33d2fa 5248
99059e56 5249 if (((base_vma + i) & 0xfff) == 0xffe
81694485
NC		 5250 && insn_32bit
5251 && is_32bit_branch
5252 && last_was_32bit
5253 && ! last_was_branch)
99059e56
RM		 5254 {
5255 bfd_signed_vma offset = 0;
5256 bfd_boolean force_target_arm = FALSE;
48229727 5257 bfd_boolean force_target_thumb = FALSE;
99059e56
RM		 5258 bfd_vma target;
5259 enum elf32_arm_stub_type stub_type = arm_stub_none;
5260 struct a8_erratum_reloc key, *found;
5261 bfd_boolean use_plt = FALSE;
48229727 5262
99059e56
RM		 5263 key.from = base_vma + i;
5264 found = (struct a8_erratum_reloc *)
5265 bsearch (&key, a8_relocs, num_a8_relocs,
5266 sizeof (struct a8_erratum_reloc),
5267 &a8_reloc_compare);
48229727
JB		 5268
5269 if (found)
5270 {
5271 char *error_message = NULL;
5272 struct elf_link_hash_entry *entry;
5273
5274 /* We don't care about the error returned from this
99059e56 5275 function, only if there is glue or not. */
48229727
JB		 5276 entry = find_thumb_glue (info, found->sym_name,
5277 &error_message);
5278
5279 if (entry)
5280 found->non_a8_stub = TRUE;
5281
92750f34 5282 /* Keep a simpler condition, for the sake of clarity. */
362d30a1 5283 if (htab->root.splt != NULL && found->hash != NULL
92750f34
DJ		 5284 && found->hash->root.plt.offset != (bfd_vma) -1)
5285 use_plt = TRUE;
5286
5287 if (found->r_type == R_ARM_THM_CALL)
5288 {
35fc36a8
RS		 5289 if (found->branch_type == ST_BRANCH_TO_ARM
5290 || use_plt)
92750f34
DJ		 5291 force_target_arm = TRUE;
5292 else
5293 force_target_thumb = TRUE;
5294 }
48229727
JB		 5295 }
5296
99059e56 5297 /* Check if we have an offending branch instruction. */
48229727
JB		 5298
5299 if (found && found->non_a8_stub)
5300 /* We've already made a stub for this instruction, e.g.
5301 it's a long branch or a Thumb->ARM stub. Assume that
5302 stub will suffice to work around the A8 erratum (see
5303 setting of always_after_branch above). */
5304 ;
99059e56
RM		 5305 else if (is_bcc)
5306 {
5307 offset = (insn & 0x7ff) << 1;
5308 offset |= (insn & 0x3f0000) >> 4;
5309 offset |= (insn & 0x2000) ? 0x40000 : 0;
5310 offset |= (insn & 0x800) ? 0x80000 : 0;
5311 offset |= (insn & 0x4000000) ? 0x100000 : 0;
5312 if (offset & 0x100000)
5313 offset |= ~ ((bfd_signed_vma) 0xfffff);
5314 stub_type = arm_stub_a8_veneer_b_cond;
5315 }
5316 else if (is_b || is_bl || is_blx)
5317 {
5318 int s = (insn & 0x4000000) != 0;
5319 int j1 = (insn & 0x2000) != 0;
5320 int j2 = (insn & 0x800) != 0;
5321 int i1 = !(j1 ^ s);
5322 int i2 = !(j2 ^ s);
5323
5324 offset = (insn & 0x7ff) << 1;
5325 offset |= (insn & 0x3ff0000) >> 4;
5326 offset |= i2 << 22;
5327 offset |= i1 << 23;
5328 offset |= s << 24;
5329 if (offset & 0x1000000)
5330 offset |= ~ ((bfd_signed_vma) 0xffffff);
5331
5332 if (is_blx)
5333 offset &= ~ ((bfd_signed_vma) 3);
5334
5335 stub_type = is_blx ? arm_stub_a8_veneer_blx :
5336 is_bl ? arm_stub_a8_veneer_bl : arm_stub_a8_veneer_b;
5337 }
5338
5339 if (stub_type != arm_stub_none)
5340 {
5341 bfd_vma pc_for_insn = base_vma + i + 4;
48229727
JB		 5342
5343 /* The original instruction is a BL, but the target is
99059e56 5344 an ARM instruction. If we were not making a stub,
48229727
JB		 5345 the BL would have been converted to a BLX. Use the
5346 BLX stub instead in that case. */
5347 if (htab->use_blx && force_target_arm
5348 && stub_type == arm_stub_a8_veneer_bl)
5349 {
5350 stub_type = arm_stub_a8_veneer_blx;
5351 is_blx = TRUE;
5352 is_bl = FALSE;
5353 }
5354 /* Conversely, if the original instruction was
5355 BLX but the target is Thumb mode, use the BL
5356 stub. */
5357 else if (force_target_thumb
5358 && stub_type == arm_stub_a8_veneer_blx)
5359 {
5360 stub_type = arm_stub_a8_veneer_bl;
5361 is_blx = FALSE;
5362 is_bl = TRUE;
5363 }
5364
99059e56
RM		 5365 if (is_blx)
5366 pc_for_insn &= ~ ((bfd_vma) 3);
48229727 5367
99059e56
RM		 5368 /* If we found a relocation, use the proper destination,
5369 not the offset in the (unrelocated) instruction.
48229727
JB		 5370 Note this is always done if we switched the stub type
5371 above. */
99059e56
RM		 5372 if (found)
5373 offset =
81694485 5374 (bfd_signed_vma) (found->destination - pc_for_insn);
48229727 5375
99059e56
RM		 5376 /* If the stub will use a Thumb-mode branch to a
5377 PLT target, redirect it to the preceding Thumb
5378 entry point. */
5379 if (stub_type != arm_stub_a8_veneer_blx && use_plt)
5380 offset -= PLT_THUMB_STUB_SIZE;
7d24e6a6 5381
99059e56 5382 target = pc_for_insn + offset;
48229727 5383
99059e56
RM		 5384 /* The BLX stub is ARM-mode code. Adjust the offset to
5385 take the different PC value (+8 instead of +4) into
48229727 5386 account. */
99059e56
RM		 5387 if (stub_type == arm_stub_a8_veneer_blx)
5388 offset += 4;
5389
5390 if (((base_vma + i) & ~0xfff) == (target & ~0xfff))
5391 {
5392 char *stub_name = NULL;
5393
5394 if (num_a8_fixes == a8_fix_table_size)
5395 {
5396 a8_fix_table_size *= 2;
5397 a8_fixes = (struct a8_erratum_fix *)
5398 bfd_realloc (a8_fixes,
5399 sizeof (struct a8_erratum_fix)
5400 * a8_fix_table_size);
5401 }
48229727 5402
eb7c4339
NS		 5403 if (num_a8_fixes < prev_num_a8_fixes)
5404 {
5405 /* If we're doing a subsequent scan,
5406 check if we've found the same fix as
5407 before, and try and reuse the stub
5408 name. */
5409 stub_name = a8_fixes[num_a8_fixes].stub_name;
5410 if ((a8_fixes[num_a8_fixes].section != section)
5411 || (a8_fixes[num_a8_fixes].offset != i))
5412 {
5413 free (stub_name);
5414 stub_name = NULL;
5415 *stub_changed_p = TRUE;
5416 }
5417 }
5418
5419 if (!stub_name)
5420 {
21d799b5 5421 stub_name = (char *) bfd_malloc (8 + 1 + 8 + 1);
eb7c4339
NS		 5422 if (stub_name != NULL)
5423 sprintf (stub_name, "%x:%x", section->id, i);
5424 }
48229727 5425
99059e56
RM		 5426 a8_fixes[num_a8_fixes].input_bfd = input_bfd;
5427 a8_fixes[num_a8_fixes].section = section;
5428 a8_fixes[num_a8_fixes].offset = i;
8d9d9490
TP		 5429 a8_fixes[num_a8_fixes].target_offset =
5430 target - base_vma;
99059e56
RM		 5431 a8_fixes[num_a8_fixes].orig_insn = insn;
5432 a8_fixes[num_a8_fixes].stub_name = stub_name;
5433 a8_fixes[num_a8_fixes].stub_type = stub_type;
5434 a8_fixes[num_a8_fixes].branch_type =
35fc36a8 5435 is_blx ? ST_BRANCH_TO_ARM : ST_BRANCH_TO_THUMB;
48229727 5436
99059e56
RM		 5437 num_a8_fixes++;
5438 }
5439 }
5440 }
48229727 5441
99059e56
RM		 5442 i += insn_32bit ? 4 : 2;
5443 last_was_32bit = insn_32bit;
48229727 5444 last_was_branch = is_32bit_branch;
99059e56
RM		 5445 }
5446 }
48229727
JB		 5447
5448 if (elf_section_data (section)->this_hdr.contents == NULL)
99059e56 5449 free (contents);
48229727 5450 }
fe33d2fa 5451
48229727
JB		 5452 *a8_fixes_p = a8_fixes;
5453 *num_a8_fixes_p = num_a8_fixes;
5454 *a8_fix_table_size_p = a8_fix_table_size;
fe33d2fa 5455
81694485 5456 return FALSE;
48229727
JB		 5457}
5458
b715f643
TP		 5459/* Create or update a stub entry depending on whether the stub can already be
5460 found in HTAB. The stub is identified by:
5461 - its type STUB_TYPE
5462 - its source branch (note that several can share the same stub) whose
5463 section and relocation (if any) are given by SECTION and IRELA
5464 respectively
5465 - its target symbol whose input section, hash, name, value and branch type
5466 are given in SYM_SEC, HASH, SYM_NAME, SYM_VALUE and BRANCH_TYPE
5467 respectively
5468
5469 If found, the value of the stub's target symbol is updated from SYM_VALUE
5470 and *NEW_STUB is set to FALSE. Otherwise, *NEW_STUB is set to
5471 TRUE and the stub entry is initialized.
5472
0955507f
TP		 5473 Returns the stub that was created or updated, or NULL if an error
5474 occurred. */
b715f643 5475
0955507f 5476static struct elf32_arm_stub_hash_entry *
b715f643
TP		 5477elf32_arm_create_stub (struct elf32_arm_link_hash_table *htab,
5478 enum elf32_arm_stub_type stub_type, asection *section,
5479 Elf_Internal_Rela *irela, asection *sym_sec,
5480 struct elf32_arm_link_hash_entry *hash, char *sym_name,
5481 bfd_vma sym_value, enum arm_st_branch_type branch_type,
5482 bfd_boolean *new_stub)
5483{
5484 const asection *id_sec;
5485 char *stub_name;
5486 struct elf32_arm_stub_hash_entry *stub_entry;
5487 unsigned int r_type;
4f4faa4d 5488 bfd_boolean sym_claimed = arm_stub_sym_claimed (stub_type);
b715f643
TP		 5489
5490 BFD_ASSERT (stub_type != arm_stub_none);
5491 *new_stub = FALSE;
5492
4f4faa4d
TP		 5493 if (sym_claimed)
5494 stub_name = sym_name;
5495 else
5496 {
5497 BFD_ASSERT (irela);
5498 BFD_ASSERT (section);
c2abbbeb 5499 BFD_ASSERT (section->id <= htab->top_id);
b715f643 5500
4f4faa4d
TP		 5501 /* Support for grouping stub sections. */
5502 id_sec = htab->stub_group[section->id].link_sec;
b715f643 5503
4f4faa4d
TP		 5504 /* Get the name of this stub. */
5505 stub_name = elf32_arm_stub_name (id_sec, sym_sec, hash, irela,
5506 stub_type);
5507 if (!stub_name)
0955507f 5508 return NULL;
4f4faa4d 5509 }
b715f643
TP		 5510
5511 stub_entry = arm_stub_hash_lookup (&htab->stub_hash_table, stub_name, FALSE,
5512 FALSE);
5513 /* The proper stub has already been created, just update its value. */
5514 if (stub_entry != NULL)
5515 {
4f4faa4d
TP		 5516 if (!sym_claimed)
5517 free (stub_name);
b715f643 5518 stub_entry->target_value = sym_value;
0955507f 5519 return stub_entry;
b715f643
TP		 5520 }
5521
daa4adae 5522 stub_entry = elf32_arm_add_stub (stub_name, section, htab, stub_type);
b715f643
TP		 5523 if (stub_entry == NULL)
5524 {
4f4faa4d
TP		 5525 if (!sym_claimed)
5526 free (stub_name);
0955507f 5527 return NULL;
b715f643
TP		 5528 }
5529
5530 stub_entry->target_value = sym_value;
5531 stub_entry->target_section = sym_sec;
5532 stub_entry->stub_type = stub_type;
5533 stub_entry->h = hash;
5534 stub_entry->branch_type = branch_type;
5535
4f4faa4d
TP		 5536 if (sym_claimed)
5537 stub_entry->output_name = sym_name;
5538 else
b715f643 5539 {
4f4faa4d
TP		 5540 if (sym_name == NULL)
5541 sym_name = "unnamed";
5542 stub_entry->output_name = (char *)
5543 bfd_alloc (htab->stub_bfd, sizeof (THUMB2ARM_GLUE_ENTRY_NAME)
5544 + strlen (sym_name));
5545 if (stub_entry->output_name == NULL)
5546 {
5547 free (stub_name);
0955507f 5548 return NULL;
4f4faa4d 5549 }
b715f643 5550
4f4faa4d
TP		 5551 /* For historical reasons, use the existing names for ARM-to-Thumb and
5552 Thumb-to-ARM stubs. */
5553 r_type = ELF32_R_TYPE (irela->r_info);
5554 if ((r_type == (unsigned int) R_ARM_THM_CALL
5555 || r_type == (unsigned int) R_ARM_THM_JUMP24
5556 || r_type == (unsigned int) R_ARM_THM_JUMP19)
5557 && branch_type == ST_BRANCH_TO_ARM)
5558 sprintf (stub_entry->output_name, THUMB2ARM_GLUE_ENTRY_NAME, sym_name);
5559 else if ((r_type == (unsigned int) R_ARM_CALL
5560 || r_type == (unsigned int) R_ARM_JUMP24)
5561 && branch_type == ST_BRANCH_TO_THUMB)
5562 sprintf (stub_entry->output_name, ARM2THUMB_GLUE_ENTRY_NAME, sym_name);
5563 else
5564 sprintf (stub_entry->output_name, STUB_ENTRY_NAME, sym_name);
5565 }
b715f643
TP		 5566
5567 *new_stub = TRUE;
0955507f 5568 return stub_entry;
b715f643
TP		 5569}
5570
4ba2ef8f
TP		 5571/* Scan symbols in INPUT_BFD to identify secure entry functions needing a
5572 gateway veneer to transition from non secure to secure state and create them
5573 accordingly.
5574
5575 "ARMv8-M Security Extensions: Requirements on Development Tools" document
5576 defines the conditions that govern Secure Gateway veneer creation for a
5577 given symbol <SYM> as follows:
5578 - it has function type
5579 - it has non local binding
5580 - a symbol named __acle_se_<SYM> (called special symbol) exists with the
5581 same type, binding and value as <SYM> (called normal symbol).
5582 An entry function can handle secure state transition itself in which case
5583 its special symbol would have a different value from the normal symbol.
5584
5585 OUT_ATTR gives the output attributes, SYM_HASHES the symbol index to hash
5586 entry mapping while HTAB gives the name to hash entry mapping.
0955507f
TP		 5587 *CMSE_STUB_CREATED is increased by the number of secure gateway veneer
5588 created.
4ba2ef8f 5589
0955507f 5590 The return value gives whether a stub failed to be allocated. */
4ba2ef8f
TP		 5591
5592static bfd_boolean
5593cmse_scan (bfd *input_bfd, struct elf32_arm_link_hash_table *htab,
5594 obj_attribute *out_attr, struct elf_link_hash_entry **sym_hashes,
0955507f 5595 int *cmse_stub_created)
4ba2ef8f
TP		 5596{
5597 const struct elf_backend_data *bed;
5598 Elf_Internal_Shdr *symtab_hdr;
5599 unsigned i, j, sym_count, ext_start;
5600 Elf_Internal_Sym *cmse_sym, *local_syms;
5601 struct elf32_arm_link_hash_entry *hash, *cmse_hash = NULL;
5602 enum arm_st_branch_type branch_type;
5603 char *sym_name, *lsym_name;
5604 bfd_vma sym_value;
5605 asection *section;
0955507f
TP		 5606 struct elf32_arm_stub_hash_entry *stub_entry;
5607 bfd_boolean is_v8m, new_stub, cmse_invalid, ret = TRUE;
4ba2ef8f
TP		 5608
5609 bed = get_elf_backend_data (input_bfd);
5610 symtab_hdr = &elf_tdata (input_bfd)->symtab_hdr;
5611 sym_count = symtab_hdr->sh_size / bed->s->sizeof_sym;
5612 ext_start = symtab_hdr->sh_info;
5613 is_v8m = (out_attr[Tag_CPU_arch].i >= TAG_CPU_ARCH_V8M_BASE
5614 && out_attr[Tag_CPU_arch_profile].i == 'M');
5615
5616 local_syms = (Elf_Internal_Sym *) symtab_hdr->contents;
5617 if (local_syms == NULL)
5618 local_syms = bfd_elf_get_elf_syms (input_bfd, symtab_hdr,
5619 symtab_hdr->sh_info, 0, NULL, NULL,
5620 NULL);
5621 if (symtab_hdr->sh_info && local_syms == NULL)
5622 return FALSE;
5623
5624 /* Scan symbols. */
5625 for (i = 0; i < sym_count; i++)
5626 {
5627 cmse_invalid = FALSE;
5628
5629 if (i < ext_start)
5630 {
5631 cmse_sym = &local_syms[i];
5632 /* Not a special symbol. */
5633 if (!ARM_GET_SYM_CMSE_SPCL (cmse_sym->st_target_internal))
5634 continue;
5635 sym_name = bfd_elf_string_from_elf_section (input_bfd,
5636 symtab_hdr->sh_link,
5637 cmse_sym->st_name);
5638 /* Special symbol with local binding. */
5639 cmse_invalid = TRUE;
5640 }
5641 else
5642 {
5643 cmse_hash = elf32_arm_hash_entry (sym_hashes[i - ext_start]);
5644 sym_name = (char *) cmse_hash->root.root.root.string;
5645
5646 /* Not a special symbol. */
5647 if (!ARM_GET_SYM_CMSE_SPCL (cmse_hash->root.target_internal))
5648 continue;
5649
5650 /* Special symbol has incorrect binding or type. */
5651 if ((cmse_hash->root.root.type != bfd_link_hash_defined
5652 && cmse_hash->root.root.type != bfd_link_hash_defweak)
5653 || cmse_hash->root.type != STT_FUNC)
5654 cmse_invalid = TRUE;
5655 }
5656
5657 if (!is_v8m)
5658 {
5659 (*_bfd_error_handler) (_("%B: Special symbol `%s' only allowed for "
5660 "ARMv8-M architecture or later."),
5661 input_bfd, sym_name);
5662 is_v8m = TRUE; /* Avoid multiple warning. */
5663 ret = FALSE;
5664 }
5665
5666 if (cmse_invalid)
5667 {
5668 (*_bfd_error_handler) (_("%B: invalid special symbol `%s'."),
5669 input_bfd, sym_name);
5670 (*_bfd_error_handler) (_("It must be a global or weak function "
5671 "symbol."));
5672 ret = FALSE;
5673 if (i < ext_start)
5674 continue;
5675 }
5676
5677 sym_name += strlen (CMSE_PREFIX);
5678 hash = (struct elf32_arm_link_hash_entry *)
5679 elf_link_hash_lookup (&(htab)->root, sym_name, FALSE, FALSE, TRUE);
5680
5681 /* No associated normal symbol or it is neither global nor weak. */
5682 if (!hash
5683 || (hash->root.root.type != bfd_link_hash_defined
5684 && hash->root.root.type != bfd_link_hash_defweak)
5685 || hash->root.type != STT_FUNC)
5686 {
5687 /* Initialize here to avoid warning about use of possibly
5688 uninitialized variable. */
5689 j = 0;
5690
5691 if (!hash)
5692 {
5693 /* Searching for a normal symbol with local binding. */
5694 for (; j < ext_start; j++)
5695 {
5696 lsym_name =
5697 bfd_elf_string_from_elf_section (input_bfd,
5698 symtab_hdr->sh_link,
5699 local_syms[j].st_name);
5700 if (!strcmp (sym_name, lsym_name))
5701 break;
5702 }
5703 }
5704
5705 if (hash || j < ext_start)
5706 {
5707 (*_bfd_error_handler)
5708 (_("%B: invalid standard symbol `%s'."), input_bfd, sym_name);
5709 (*_bfd_error_handler)
5710 (_("It must be a global or weak function symbol."));
5711 }
5712 else
5713 (*_bfd_error_handler)
5714 (_("%B: absent standard symbol `%s'."), input_bfd, sym_name);
5715 ret = FALSE;
5716 if (!hash)
5717 continue;
5718 }
5719
5720 sym_value = hash->root.root.u.def.value;
5721 section = hash->root.root.u.def.section;
5722
5723 if (cmse_hash->root.root.u.def.section != section)
5724 {
5725 (*_bfd_error_handler)
5726 (_("%B: `%s' and its special symbol are in different sections."),
5727 input_bfd, sym_name);
5728 ret = FALSE;
5729 }
5730 if (cmse_hash->root.root.u.def.value != sym_value)
5731 continue; /* Ignore: could be an entry function starting with SG. */
5732
5733 /* If this section is a link-once section that will be discarded, then
5734 don't create any stubs. */
5735 if (section->output_section == NULL)
5736 {
5737 (*_bfd_error_handler)
5738 (_("%B: entry function `%s' not output."), input_bfd, sym_name);
5739 continue;
5740 }
5741
5742 if (hash->root.size == 0)
5743 {
5744 (*_bfd_error_handler)
5745 (_("%B: entry function `%s' is empty."), input_bfd, sym_name);
5746 ret = FALSE;
5747 }
5748
5749 if (!ret)
5750 continue;
5751 branch_type = ARM_GET_SYM_BRANCH_TYPE (hash->root.target_internal);
0955507f 5752 stub_entry
4ba2ef8f
TP		 5753 = elf32_arm_create_stub (htab, arm_stub_cmse_branch_thumb_only,
5754 NULL, NULL, section, hash, sym_name,
5755 sym_value, branch_type, &new_stub);
5756
0955507f 5757 if (stub_entry == NULL)
4ba2ef8f
TP		 5758 ret = FALSE;
5759 else
5760 {
5761 BFD_ASSERT (new_stub);
0955507f 5762 (*cmse_stub_created)++;
4ba2ef8f
TP		 5763 }
5764 }
5765
5766 if (!symtab_hdr->contents)
5767 free (local_syms);
5768 return ret;
5769}
5770
0955507f
TP		 5771/* Return TRUE iff a symbol identified by its linker HASH entry is a secure
5772 code entry function, ie can be called from non secure code without using a
5773 veneer. */
5774
5775static bfd_boolean
5776cmse_entry_fct_p (struct elf32_arm_link_hash_entry *hash)
5777{
5778 uint32_t first_insn;
5779 asection *section;
5780 file_ptr offset;
5781 bfd *abfd;
5782
5783 /* Defined symbol of function type. */
5784 if (hash->root.root.type != bfd_link_hash_defined
5785 && hash->root.root.type != bfd_link_hash_defweak)
5786 return FALSE;
5787 if (hash->root.type != STT_FUNC)
5788 return FALSE;
5789
5790 /* Read first instruction. */
5791 section = hash->root.root.u.def.section;
5792 abfd = section->owner;
5793 offset = hash->root.root.u.def.value - section->vma;
5794 if (!bfd_get_section_contents (abfd, section, &first_insn, offset,
5795 sizeof (first_insn)))
5796 return FALSE;
5797
5798 /* Start by SG instruction. */
5799 return first_insn == 0xe97fe97f;
5800}
5801
5802/* Output the name (in symbol table) of the veneer GEN_ENTRY if it is a new
5803 secure gateway veneers (ie. the veneers was not in the input import library)
5804 and there is no output import library (GEN_INFO->out_implib_bfd is NULL. */
5805
5806static bfd_boolean
5807arm_list_new_cmse_stub (struct bfd_hash_entry *gen_entry, void *gen_info)
5808{
5809 struct elf32_arm_stub_hash_entry *stub_entry;
5810 struct bfd_link_info *info;
5811
5812 /* Massage our args to the form they really have. */
5813 stub_entry = (struct elf32_arm_stub_hash_entry *) gen_entry;
5814 info = (struct bfd_link_info *) gen_info;
5815
5816 if (info->out_implib_bfd)
5817 return TRUE;
5818
5819 if (stub_entry->stub_type != arm_stub_cmse_branch_thumb_only)
5820 return TRUE;
5821
5822 if (stub_entry->stub_offset == (bfd_vma) -1)
5823 (*_bfd_error_handler) (" %s", stub_entry->output_name);
5824
5825 return TRUE;
5826}
5827
5828/* Set offset of each secure gateway veneers so that its address remain
5829 identical to the one in the input import library referred by
5830 HTAB->in_implib_bfd. A warning is issued for veneers that disappeared
5831 (present in input import library but absent from the executable being
5832 linked) or if new veneers appeared and there is no output import library
5833 (INFO->out_implib_bfd is NULL and *CMSE_STUB_CREATED is bigger than the
5834 number of secure gateway veneers found in the input import library.
5835
5836 The function returns whether an error occurred. If no error occurred,
5837 *CMSE_STUB_CREATED gives the number of SG veneers created by both cmse_scan
5838 and this function and HTAB->new_cmse_stub_offset is set to the biggest
5839 veneer observed set for new veneers to be layed out after. */
5840
5841static bfd_boolean
5842set_cmse_veneer_addr_from_implib (struct bfd_link_info *info,
5843 struct elf32_arm_link_hash_table *htab,
5844 int *cmse_stub_created)
5845{
5846 long symsize;
5847 char *sym_name;
5848 flagword flags;
5849 long i, symcount;
5850 bfd *in_implib_bfd;
5851 asection *stub_out_sec;
5852 bfd_boolean ret = TRUE;
5853 Elf_Internal_Sym *intsym;
5854 const char *out_sec_name;
5855 bfd_size_type cmse_stub_size;
5856 asymbol **sympp = NULL, *sym;
5857 struct elf32_arm_link_hash_entry *hash;
5858 const insn_sequence *cmse_stub_template;
5859 struct elf32_arm_stub_hash_entry *stub_entry;
5860 int cmse_stub_template_size, new_cmse_stubs_created = *cmse_stub_created;
5861 bfd_vma veneer_value, stub_offset, next_cmse_stub_offset;
5862 bfd_vma cmse_stub_array_start = (bfd_vma) -1, cmse_stub_sec_vma = 0;
5863
5864 /* No input secure gateway import library. */
5865 if (!htab->in_implib_bfd)
5866 return TRUE;
5867
5868 in_implib_bfd = htab->in_implib_bfd;
5869 if (!htab->cmse_implib)
5870 {
5871 (*_bfd_error_handler) (_("%B: --in-implib only supported for Secure "
5872 "Gateway import libraries."), in_implib_bfd);
5873 return FALSE;
5874 }
5875
5876 /* Get symbol table size. */
5877 symsize = bfd_get_symtab_upper_bound (in_implib_bfd);
5878 if (symsize < 0)
5879 return FALSE;
5880
5881 /* Read in the input secure gateway import library's symbol table. */
5882 sympp = (asymbol **) xmalloc (symsize);
5883 symcount = bfd_canonicalize_symtab (in_implib_bfd, sympp);
5884 if (symcount < 0)
5885 {
5886 ret = FALSE;
5887 goto free_sym_buf;
5888 }
5889
5890 htab->new_cmse_stub_offset = 0;
5891 cmse_stub_size =
5892 find_stub_size_and_template (arm_stub_cmse_branch_thumb_only,
5893 &cmse_stub_template,
5894 &cmse_stub_template_size);
5895 out_sec_name =
5896 arm_dedicated_stub_output_section_name (arm_stub_cmse_branch_thumb_only);
5897 stub_out_sec =
5898 bfd_get_section_by_name (htab->obfd, out_sec_name);
5899 if (stub_out_sec != NULL)
5900 cmse_stub_sec_vma = stub_out_sec->vma;
5901
5902 /* Set addresses of veneers mentionned in input secure gateway import
5903 library's symbol table. */
5904 for (i = 0; i < symcount; i++)
5905 {
5906 sym = sympp[i];
5907 flags = sym->flags;
5908 sym_name = (char *) bfd_asymbol_name (sym);
5909 intsym = &((elf_symbol_type *) sym)->internal_elf_sym;
5910
5911 if (sym->section != bfd_abs_section_ptr
5912 || !(flags & (BSF_GLOBAL | BSF_WEAK))
5913 || (flags & BSF_FUNCTION) != BSF_FUNCTION
5914 || (ARM_GET_SYM_BRANCH_TYPE (intsym->st_target_internal)
5915 != ST_BRANCH_TO_THUMB))
5916 {
5917 (*_bfd_error_handler) (_("%B: invalid import library entry: `%s'."),
5918 in_implib_bfd, sym_name);
5919 (*_bfd_error_handler) (_("Symbol should be absolute, global and "
5920 "refer to Thumb functions."));
5921 ret = FALSE;
5922 continue;
5923 }
5924
5925 veneer_value = bfd_asymbol_value (sym);
5926 stub_offset = veneer_value - cmse_stub_sec_vma;
5927 stub_entry = arm_stub_hash_lookup (&htab->stub_hash_table, sym_name,
5928 FALSE, FALSE);
5929 hash = (struct elf32_arm_link_hash_entry *)
5930 elf_link_hash_lookup (&(htab)->root, sym_name, FALSE, FALSE, TRUE);
5931
5932 /* Stub entry should have been created by cmse_scan or the symbol be of
5933 a secure function callable from non secure code. */
5934 if (!stub_entry && !hash)
5935 {
5936 bfd_boolean new_stub;
5937
5938 (*_bfd_error_handler)
5939 (_("Entry function `%s' disappeared from secure code."), sym_name);
5940 hash = (struct elf32_arm_link_hash_entry *)
5941 elf_link_hash_lookup (&(htab)->root, sym_name, TRUE, TRUE, TRUE);
5942 stub_entry
5943 = elf32_arm_create_stub (htab, arm_stub_cmse_branch_thumb_only,
5944 NULL, NULL, bfd_abs_section_ptr, hash,
5945 sym_name, veneer_value,
5946 ST_BRANCH_TO_THUMB, &new_stub);
5947 if (stub_entry == NULL)
5948 ret = FALSE;
5949 else
5950 {
5951 BFD_ASSERT (new_stub);
5952 new_cmse_stubs_created++;
5953 (*cmse_stub_created)++;
5954 }
5955 stub_entry->stub_template_size = stub_entry->stub_size = 0;
5956 stub_entry->stub_offset = stub_offset;
5957 }
5958 /* Symbol found is not callable from non secure code. */
5959 else if (!stub_entry)
5960 {
5961 if (!cmse_entry_fct_p (hash))
5962 {
5963 (*_bfd_error_handler) (_("`%s' refers to a non entry function."),
5964 sym_name);
5965 ret = FALSE;
5966 }
5967 continue;
5968 }
5969 else
5970 {
5971 /* Only stubs for SG veneers should have been created. */
5972 BFD_ASSERT (stub_entry->stub_type == arm_stub_cmse_branch_thumb_only);
5973
5974 /* Check visibility hasn't changed. */
5975 if (!!(flags & BSF_GLOBAL)
5976 != (hash->root.root.type == bfd_link_hash_defined))
5977 (*_bfd_error_handler)
5978 (_("%B: visibility of symbol `%s' has changed."), in_implib_bfd,
5979 sym_name);
5980
5981 stub_entry->stub_offset = stub_offset;
5982 }
5983
5984 /* Size should match that of a SG veneer. */
5985 if (intsym->st_size != cmse_stub_size)
5986 {
5987 (*_bfd_error_handler) (_("%B: incorrect size for symbol `%s'."),
5988 in_implib_bfd, sym_name);
5989 ret = FALSE;
5990 }
5991
5992 /* Previous veneer address is before current SG veneer section. */
5993 if (veneer_value < cmse_stub_sec_vma)
5994 {
5995 /* Avoid offset underflow. */
5996 if (stub_entry)
5997 stub_entry->stub_offset = 0;
5998 stub_offset = 0;
5999 ret = FALSE;
6000 }
6001
6002 /* Complain if stub offset not a multiple of stub size. */
6003 if (stub_offset % cmse_stub_size)
6004 {
6005 (*_bfd_error_handler)
6006 (_("Offset of veneer for entry function `%s' not a multiple of "
6007 "its size."), sym_name);
6008 ret = FALSE;
6009 }
6010
6011 if (!ret)
6012 continue;
6013
6014 new_cmse_stubs_created--;
6015 if (veneer_value < cmse_stub_array_start)
6016 cmse_stub_array_start = veneer_value;
6017 next_cmse_stub_offset = stub_offset + ((cmse_stub_size + 7) & ~7);
6018 if (next_cmse_stub_offset > htab->new_cmse_stub_offset)
6019 htab->new_cmse_stub_offset = next_cmse_stub_offset;
6020 }
6021
6022 if (!info->out_implib_bfd && new_cmse_stubs_created != 0)
6023 {
6024 BFD_ASSERT (new_cmse_stubs_created > 0);
6025 (*_bfd_error_handler)
6026 (_("new entry function(s) introduced but no output import library "
6027 "specified:"));
6028 bfd_hash_traverse (&htab->stub_hash_table, arm_list_new_cmse_stub, info);
6029 }
6030
6031 if (cmse_stub_array_start != cmse_stub_sec_vma)
6032 {
6033 (*_bfd_error_handler)
6034 (_("Start address of `%s' is different from previous link."),
6035 out_sec_name);
6036 ret = FALSE;
6037 }
6038
6039free_sym_buf:
6040 free (sympp);
6041 return ret;
6042}
6043
906e58ca
NC		 6044/* Determine and set the size of the stub section for a final link.
6045
6046 The basic idea here is to examine all the relocations looking for
6047 PC-relative calls to a target that is unreachable with a "bl"
6048 instruction. */
6049
6050bfd_boolean
6051elf32_arm_size_stubs (bfd *output_bfd,
6052 bfd *stub_bfd,
6053 struct bfd_link_info *info,
6054 bfd_signed_vma group_size,
7a89b94e 6055 asection * (*add_stub_section) (const char *, asection *,
6bde4c52 6056 asection *,
7a89b94e 6057 unsigned int),
906e58ca
NC		 6058 void (*layout_sections_again) (void))
6059{
0955507f 6060 bfd_boolean ret = TRUE;
4ba2ef8f 6061 obj_attribute *out_attr;
0955507f 6062 int cmse_stub_created = 0;
906e58ca 6063 bfd_size_type stub_group_size;
4ba2ef8f 6064 bfd_boolean m_profile, stubs_always_after_branch, first_veneer_scan = TRUE;
906e58ca 6065 struct elf32_arm_link_hash_table *htab = elf32_arm_hash_table (info);
48229727 6066 struct a8_erratum_fix *a8_fixes = NULL;
eb7c4339 6067 unsigned int num_a8_fixes = 0, a8_fix_table_size = 10;
48229727
JB		 6068 struct a8_erratum_reloc *a8_relocs = NULL;
6069 unsigned int num_a8_relocs = 0, a8_reloc_table_size = 10, i;
6070
4dfe6ac6
NC		 6071 if (htab == NULL)
6072 return FALSE;
6073
48229727
JB		 6074 if (htab->fix_cortex_a8)
6075 {
21d799b5 6076 a8_fixes = (struct a8_erratum_fix *)
99059e56 6077 bfd_zmalloc (sizeof (struct a8_erratum_fix) * a8_fix_table_size);
21d799b5 6078 a8_relocs = (struct a8_erratum_reloc *)
99059e56 6079 bfd_zmalloc (sizeof (struct a8_erratum_reloc) * a8_reloc_table_size);
48229727 6080 }
906e58ca
NC		 6081
6082 /* Propagate mach to stub bfd, because it may not have been
6083 finalized when we created stub_bfd. */
6084 bfd_set_arch_mach (stub_bfd, bfd_get_arch (output_bfd),
6085 bfd_get_mach (output_bfd));
6086
6087 /* Stash our params away. */
6088 htab->stub_bfd = stub_bfd;
6089 htab->add_stub_section = add_stub_section;
6090 htab->layout_sections_again = layout_sections_again;
07d72278 6091 stubs_always_after_branch = group_size < 0;
48229727 6092
4ba2ef8f
TP		 6093 out_attr = elf_known_obj_attributes_proc (output_bfd);
6094 m_profile = out_attr[Tag_CPU_arch_profile].i == 'M';
0955507f 6095
48229727
JB		 6096 /* The Cortex-A8 erratum fix depends on stubs not being in the same 4K page
6097 as the first half of a 32-bit branch straddling two 4K pages. This is a
6098 crude way of enforcing that. */
6099 if (htab->fix_cortex_a8)
6100 stubs_always_after_branch = 1;
6101
906e58ca
NC		 6102 if (group_size < 0)
6103 stub_group_size = -group_size;
6104 else
6105 stub_group_size = group_size;
6106
6107 if (stub_group_size == 1)
6108 {
6109 /* Default values. */
6110 /* Thumb branch range is +-4MB has to be used as the default
6111 maximum size (a given section can contain both ARM and Thumb
6112 code, so the worst case has to be taken into account).
6113
6114 This value is 24K less than that, which allows for 2025
6115 12-byte stubs. If we exceed that, then we will fail to link.
6116 The user will have to relink with an explicit group size
6117 option. */
6118 stub_group_size = 4170000;
6119 }
6120
07d72278 6121 group_sections (htab, stub_group_size, stubs_always_after_branch);
906e58ca 6122
3ae046cc
NS		 6123 /* If we're applying the cortex A8 fix, we need to determine the
6124 program header size now, because we cannot change it later --
6125 that could alter section placements. Notice the A8 erratum fix
6126 ends up requiring the section addresses to remain unchanged
6127 modulo the page size. That's something we cannot represent
6128 inside BFD, and we don't want to force the section alignment to
6129 be the page size. */
6130 if (htab->fix_cortex_a8)
6131 (*htab->layout_sections_again) ();
6132
906e58ca
NC		 6133 while (1)
6134 {
6135 bfd *input_bfd;
6136 unsigned int bfd_indx;
6137 asection *stub_sec;
d7c5bd02 6138 enum elf32_arm_stub_type stub_type;
eb7c4339
NS		 6139 bfd_boolean stub_changed = FALSE;
6140 unsigned prev_num_a8_fixes = num_a8_fixes;
906e58ca 6141
48229727 6142 num_a8_fixes = 0;
906e58ca
NC		 6143 for (input_bfd = info->input_bfds, bfd_indx = 0;
6144 input_bfd != NULL;
c72f2fb2 6145 input_bfd = input_bfd->link.next, bfd_indx++)
906e58ca
NC		 6146 {
6147 Elf_Internal_Shdr *symtab_hdr;
6148 asection *section;
6149 Elf_Internal_Sym *local_syms = NULL;
6150
99059e56
RM		 6151 if (!is_arm_elf (input_bfd))
6152 continue;
adbcc655 6153
48229727
JB		 6154 num_a8_relocs = 0;
6155
906e58ca
NC		 6156 /* We'll need the symbol table in a second. */
6157 symtab_hdr = &elf_tdata (input_bfd)->symtab_hdr;
6158 if (symtab_hdr->sh_info == 0)
6159 continue;
6160
4ba2ef8f
TP		 6161 /* Limit scan of symbols to object file whose profile is
6162 Microcontroller to not hinder performance in the general case. */
6163 if (m_profile && first_veneer_scan)
6164 {
6165 struct elf_link_hash_entry **sym_hashes;
6166
6167 sym_hashes = elf_sym_hashes (input_bfd);
6168 if (!cmse_scan (input_bfd, htab, out_attr, sym_hashes,
0955507f 6169 &cmse_stub_created))
4ba2ef8f 6170 goto error_ret_free_local;
0955507f
TP		 6171
6172 if (cmse_stub_created != 0)
6173 stub_changed = TRUE;
4ba2ef8f
TP		 6174 }
6175
906e58ca
NC		 6176 /* Walk over each section attached to the input bfd. */
6177 for (section = input_bfd->sections;
6178 section != NULL;
6179 section = section->next)
6180 {
6181 Elf_Internal_Rela *internal_relocs, *irelaend, *irela;
6182
6183 /* If there aren't any relocs, then there's nothing more
6184 to do. */
6185 if ((section->flags & SEC_RELOC) == 0
6186 || section->reloc_count == 0
6187 || (section->flags & SEC_CODE) == 0)
6188 continue;
6189
6190 /* If this section is a link-once section that will be
6191 discarded, then don't create any stubs. */
6192 if (section->output_section == NULL
6193 || section->output_section->owner != output_bfd)
6194 continue;
6195
6196 /* Get the relocs. */
6197 internal_relocs
6198 = _bfd_elf_link_read_relocs (input_bfd, section, NULL,
6199 NULL, info->keep_memory);
6200 if (internal_relocs == NULL)
6201 goto error_ret_free_local;
6202
6203 /* Now examine each relocation. */
6204 irela = internal_relocs;
6205 irelaend = irela + section->reloc_count;
6206 for (; irela < irelaend; irela++)
6207 {
6208 unsigned int r_type, r_indx;
906e58ca
NC		 6209 asection *sym_sec;
6210 bfd_vma sym_value;
6211 bfd_vma destination;
6212 struct elf32_arm_link_hash_entry *hash;
7413f23f 6213 const char *sym_name;
34e77a92 6214 unsigned char st_type;
35fc36a8 6215 enum arm_st_branch_type branch_type;
48229727 6216 bfd_boolean created_stub = FALSE;
906e58ca
NC		 6217
6218 r_type = ELF32_R_TYPE (irela->r_info);
6219 r_indx = ELF32_R_SYM (irela->r_info);
6220
6221 if (r_type >= (unsigned int) R_ARM_max)
6222 {
6223 bfd_set_error (bfd_error_bad_value);
6224 error_ret_free_internal:
6225 if (elf_section_data (section)->relocs == NULL)
6226 free (internal_relocs);
15dd01b1
TP		 6227 /* Fall through. */
6228 error_ret_free_local:
6229 if (local_syms != NULL
6230 && (symtab_hdr->contents
6231 != (unsigned char *) local_syms))
6232 free (local_syms);
6233 return FALSE;
906e58ca 6234 }
b38cadfb 6235
0855e32b
NS		 6236 hash = NULL;
6237 if (r_indx >= symtab_hdr->sh_info)
6238 hash = elf32_arm_hash_entry
6239 (elf_sym_hashes (input_bfd)
6240 [r_indx - symtab_hdr->sh_info]);
b38cadfb 6241
0855e32b
NS		 6242 /* Only look for stubs on branch instructions, or
6243 non-relaxed TLSCALL */
906e58ca 6244 if ((r_type != (unsigned int) R_ARM_CALL)
155d87d7
CL		 6245 && (r_type != (unsigned int) R_ARM_THM_CALL)
6246 && (r_type != (unsigned int) R_ARM_JUMP24)
48229727
JB		 6247 && (r_type != (unsigned int) R_ARM_THM_JUMP19)
6248 && (r_type != (unsigned int) R_ARM_THM_XPC22)
155d87d7 6249 && (r_type != (unsigned int) R_ARM_THM_JUMP24)
0855e32b
NS		 6250 && (r_type != (unsigned int) R_ARM_PLT32)
6251 && !((r_type == (unsigned int) R_ARM_TLS_CALL
6252 || r_type == (unsigned int) R_ARM_THM_TLS_CALL)
6253 && r_type == elf32_arm_tls_transition
6254 (info, r_type, &hash->root)
6255 && ((hash ? hash->tls_type
6256 : (elf32_arm_local_got_tls_type
6257 (input_bfd)[r_indx]))
6258 & GOT_TLS_GDESC) != 0))
906e58ca
NC		 6259 continue;
6260
6261 /* Now determine the call target, its name, value,
6262 section. */
6263 sym_sec = NULL;
6264 sym_value = 0;
6265 destination = 0;
7413f23f 6266 sym_name = NULL;
b38cadfb 6267
0855e32b
NS		 6268 if (r_type == (unsigned int) R_ARM_TLS_CALL
6269 || r_type == (unsigned int) R_ARM_THM_TLS_CALL)
6270 {
6271 /* A non-relaxed TLS call. The target is the
6272 plt-resident trampoline and nothing to do
6273 with the symbol. */
6274 BFD_ASSERT (htab->tls_trampoline > 0);
6275 sym_sec = htab->root.splt;
6276 sym_value = htab->tls_trampoline;
6277 hash = 0;
34e77a92 6278 st_type = STT_FUNC;
35fc36a8 6279 branch_type = ST_BRANCH_TO_ARM;
0855e32b
NS		 6280 }
6281 else if (!hash)
906e58ca
NC		 6282 {
6283 /* It's a local symbol. */
6284 Elf_Internal_Sym *sym;
906e58ca
NC		 6285
6286 if (local_syms == NULL)
6287 {
6288 local_syms
6289 = (Elf_Internal_Sym *) symtab_hdr->contents;
6290 if (local_syms == NULL)
6291 local_syms
6292 = bfd_elf_get_elf_syms (input_bfd, symtab_hdr,
6293 symtab_hdr->sh_info, 0,
6294 NULL, NULL, NULL);
6295 if (local_syms == NULL)
6296 goto error_ret_free_internal;
6297 }
6298
6299 sym = local_syms + r_indx;
f6d250ce
TS		 6300 if (sym->st_shndx == SHN_UNDEF)
6301 sym_sec = bfd_und_section_ptr;
6302 else if (sym->st_shndx == SHN_ABS)
6303 sym_sec = bfd_abs_section_ptr;
6304 else if (sym->st_shndx == SHN_COMMON)
6305 sym_sec = bfd_com_section_ptr;
6306 else
6307 sym_sec =
6308 bfd_section_from_elf_index (input_bfd, sym->st_shndx);
6309
ffcb4889
NS		 6310 if (!sym_sec)
6311 /* This is an undefined symbol. It can never
6a631e86 6312 be resolved. */
ffcb4889 6313 continue;
fe33d2fa 6314
906e58ca
NC		 6315 if (ELF_ST_TYPE (sym->st_info) != STT_SECTION)
6316 sym_value = sym->st_value;
6317 destination = (sym_value + irela->r_addend
6318 + sym_sec->output_offset
6319 + sym_sec->output_section->vma);
34e77a92 6320 st_type = ELF_ST_TYPE (sym->st_info);
39d911fc
TP		 6321 branch_type =
6322 ARM_GET_SYM_BRANCH_TYPE (sym->st_target_internal);
7413f23f
DJ		 6323 sym_name
6324 = bfd_elf_string_from_elf_section (input_bfd,
6325 symtab_hdr->sh_link,
6326 sym->st_name);
906e58ca
NC		 6327 }
6328 else
6329 {
6330 /* It's an external symbol. */
906e58ca
NC		 6331 while (hash->root.root.type == bfd_link_hash_indirect
6332 || hash->root.root.type == bfd_link_hash_warning)
6333 hash = ((struct elf32_arm_link_hash_entry *)
6334 hash->root.root.u.i.link);
6335
6336 if (hash->root.root.type == bfd_link_hash_defined
6337 || hash->root.root.type == bfd_link_hash_defweak)
6338 {
6339 sym_sec = hash->root.root.u.def.section;
6340 sym_value = hash->root.root.u.def.value;
022f8312
CL		 6341
6342 struct elf32_arm_link_hash_table *globals =
6343 elf32_arm_hash_table (info);
6344
6345 /* For a destination in a shared library,
6346 use the PLT stub as target address to
6347 decide whether a branch stub is
6348 needed. */
4dfe6ac6 6349 if (globals != NULL
362d30a1 6350 && globals->root.splt != NULL
4dfe6ac6 6351 && hash != NULL
022f8312
CL		 6352 && hash->root.plt.offset != (bfd_vma) -1)
6353 {
362d30a1 6354 sym_sec = globals->root.splt;
022f8312
CL		 6355 sym_value = hash->root.plt.offset;
6356 if (sym_sec->output_section != NULL)
6357 destination = (sym_value
6358 + sym_sec->output_offset
6359 + sym_sec->output_section->vma);
6360 }
6361 else if (sym_sec->output_section != NULL)
906e58ca
NC		 6362 destination = (sym_value + irela->r_addend
6363 + sym_sec->output_offset
6364 + sym_sec->output_section->vma);
6365 }
69c5861e
CL		 6366 else if ((hash->root.root.type == bfd_link_hash_undefined)
6367 || (hash->root.root.type == bfd_link_hash_undefweak))
6368 {
6369 /* For a shared library, use the PLT stub as
6370 target address to decide whether a long
6371 branch stub is needed.
6372 For absolute code, they cannot be handled. */
6373 struct elf32_arm_link_hash_table *globals =
6374 elf32_arm_hash_table (info);
6375
4dfe6ac6 6376 if (globals != NULL
362d30a1 6377 && globals->root.splt != NULL
4dfe6ac6 6378 && hash != NULL
69c5861e
CL		 6379 && hash->root.plt.offset != (bfd_vma) -1)
6380 {
362d30a1 6381 sym_sec = globals->root.splt;
69c5861e
CL		 6382 sym_value = hash->root.plt.offset;
6383 if (sym_sec->output_section != NULL)
6384 destination = (sym_value
6385 + sym_sec->output_offset
6386 + sym_sec->output_section->vma);
6387 }
6388 else
6389 continue;
6390 }
906e58ca
NC		 6391 else
6392 {
6393 bfd_set_error (bfd_error_bad_value);
6394 goto error_ret_free_internal;
6395 }
34e77a92 6396 st_type = hash->root.type;
39d911fc
TP		 6397 branch_type =
6398 ARM_GET_SYM_BRANCH_TYPE (hash->root.target_internal);
7413f23f 6399 sym_name = hash->root.root.root.string;
906e58ca
NC		 6400 }
6401
48229727 6402 do
7413f23f 6403 {
b715f643 6404 bfd_boolean new_stub;
0955507f 6405 struct elf32_arm_stub_hash_entry *stub_entry;
b715f643 6406
48229727
JB		 6407 /* Determine what (if any) linker stub is needed. */
6408 stub_type = arm_type_of_stub (info, section, irela,
34e77a92
RS		 6409 st_type, &branch_type,
6410 hash, destination, sym_sec,
48229727
JB		 6411 input_bfd, sym_name);
6412 if (stub_type == arm_stub_none)
6413 break;
6414
48229727
JB		 6415 /* We've either created a stub for this reloc already,
6416 or we are about to. */
0955507f 6417 stub_entry =
b715f643
TP		 6418 elf32_arm_create_stub (htab, stub_type, section, irela,
6419 sym_sec, hash,
6420 (char *) sym_name, sym_value,
6421 branch_type, &new_stub);
7413f23f 6422
0955507f 6423 created_stub = stub_entry != NULL;
b715f643
TP		 6424 if (!created_stub)
6425 goto error_ret_free_internal;
6426 else if (!new_stub)
6427 break;
99059e56 6428 else
b715f643 6429 stub_changed = TRUE;
99059e56
RM		 6430 }
6431 while (0);
6432
6433 /* Look for relocations which might trigger Cortex-A8
6434 erratum. */
6435 if (htab->fix_cortex_a8
6436 && (r_type == (unsigned int) R_ARM_THM_JUMP24
6437 || r_type == (unsigned int) R_ARM_THM_JUMP19
6438 || r_type == (unsigned int) R_ARM_THM_CALL
6439 || r_type == (unsigned int) R_ARM_THM_XPC22))
6440 {
6441 bfd_vma from = section->output_section->vma
6442 + section->output_offset
6443 + irela->r_offset;
6444
6445 if ((from & 0xfff) == 0xffe)
6446 {
6447 /* Found a candidate. Note we haven't checked the
6448 destination is within 4K here: if we do so (and
6449 don't create an entry in a8_relocs) we can't tell
6450 that a branch should have been relocated when
6451 scanning later. */
6452 if (num_a8_relocs == a8_reloc_table_size)
6453 {
6454 a8_reloc_table_size *= 2;
6455 a8_relocs = (struct a8_erratum_reloc *)
6456 bfd_realloc (a8_relocs,
6457 sizeof (struct a8_erratum_reloc)
6458 * a8_reloc_table_size);
6459 }
6460
6461 a8_relocs[num_a8_relocs].from = from;
6462 a8_relocs[num_a8_relocs].destination = destination;
6463 a8_relocs[num_a8_relocs].r_type = r_type;
6464 a8_relocs[num_a8_relocs].branch_type = branch_type;
6465 a8_relocs[num_a8_relocs].sym_name = sym_name;
6466 a8_relocs[num_a8_relocs].non_a8_stub = created_stub;
6467 a8_relocs[num_a8_relocs].hash = hash;
6468
6469 num_a8_relocs++;
6470 }
6471 }
906e58ca
NC		 6472 }
6473
99059e56
RM		 6474 /* We're done with the internal relocs, free them. */
6475 if (elf_section_data (section)->relocs == NULL)
6476 free (internal_relocs);
6477 }
48229727 6478
99059e56 6479 if (htab->fix_cortex_a8)
48229727 6480 {
99059e56
RM		 6481 /* Sort relocs which might apply to Cortex-A8 erratum. */
6482 qsort (a8_relocs, num_a8_relocs,
eb7c4339 6483 sizeof (struct a8_erratum_reloc),
99059e56 6484 &a8_reloc_compare);
48229727 6485
99059e56
RM		 6486 /* Scan for branches which might trigger Cortex-A8 erratum. */
6487 if (cortex_a8_erratum_scan (input_bfd, info, &a8_fixes,
48229727 6488 &num_a8_fixes, &a8_fix_table_size,
eb7c4339
NS		 6489 a8_relocs, num_a8_relocs,
6490 prev_num_a8_fixes, &stub_changed)
6491 != 0)
48229727 6492 goto error_ret_free_local;
5e681ec4 6493 }
7f991970
AM		 6494
6495 if (local_syms != NULL
6496 && symtab_hdr->contents != (unsigned char *) local_syms)
6497 {
6498 if (!info->keep_memory)
6499 free (local_syms);
6500 else
6501 symtab_hdr->contents = (unsigned char *) local_syms;
6502 }
5e681ec4
PB		 6503 }
6504
0955507f
TP		 6505 if (first_veneer_scan
6506 && !set_cmse_veneer_addr_from_implib (info, htab,
6507 &cmse_stub_created))
6508 ret = FALSE;
6509
eb7c4339 6510 if (prev_num_a8_fixes != num_a8_fixes)
99059e56 6511 stub_changed = TRUE;
48229727 6512
906e58ca
NC		 6513 if (!stub_changed)
6514 break;
5e681ec4 6515
906e58ca
NC		 6516 /* OK, we've added some stubs. Find out the new size of the
6517 stub sections. */
6518 for (stub_sec = htab->stub_bfd->sections;
6519 stub_sec != NULL;
6520 stub_sec = stub_sec->next)
3e6b1042
DJ		 6521 {
6522 /* Ignore non-stub sections. */
6523 if (!strstr (stub_sec->name, STUB_SUFFIX))
6524 continue;
6525
6526 stub_sec->size = 0;
6527 }
b34b2d70 6528
0955507f
TP		 6529 /* Add new SG veneers after those already in the input import
6530 library. */
6531 for (stub_type = arm_stub_none + 1; stub_type < max_stub_type;
6532 stub_type++)
6533 {
6534 bfd_vma *start_offset_p;
6535 asection **stub_sec_p;
6536
6537 start_offset_p = arm_new_stubs_start_offset_ptr (htab, stub_type);
6538 stub_sec_p = arm_dedicated_stub_input_section_ptr (htab, stub_type);
6539 if (start_offset_p == NULL)
6540 continue;
6541
6542 BFD_ASSERT (stub_sec_p != NULL);
6543 if (*stub_sec_p != NULL)
6544 (*stub_sec_p)->size = *start_offset_p;
6545 }
6546
d7c5bd02 6547 /* Compute stub section size, considering padding. */
906e58ca 6548 bfd_hash_traverse (&htab->stub_hash_table, arm_size_one_stub, htab);
d7c5bd02
TP		 6549 for (stub_type = arm_stub_none + 1; stub_type < max_stub_type;
6550 stub_type++)
6551 {
6552 int size, padding;
6553 asection **stub_sec_p;
6554
6555 padding = arm_dedicated_stub_section_padding (stub_type);
6556 stub_sec_p = arm_dedicated_stub_input_section_ptr (htab, stub_type);
6557 /* Skip if no stub input section or no stub section padding
6558 required. */
6559 if ((stub_sec_p != NULL && *stub_sec_p == NULL) || padding == 0)
6560 continue;
6561 /* Stub section padding required but no dedicated section. */
6562 BFD_ASSERT (stub_sec_p);
6563
6564 size = (*stub_sec_p)->size;
6565 size = (size + padding - 1) & ~(padding - 1);
6566 (*stub_sec_p)->size = size;
6567 }
906e58ca 6568
48229727
JB		 6569 /* Add Cortex-A8 erratum veneers to stub section sizes too. */
6570 if (htab->fix_cortex_a8)
99059e56
RM		 6571 for (i = 0; i < num_a8_fixes; i++)
6572 {
48229727 6573 stub_sec = elf32_arm_create_or_find_stub_sec (NULL,
daa4adae 6574 a8_fixes[i].section, htab, a8_fixes[i].stub_type);
48229727
JB		 6575
6576 if (stub_sec == NULL)
7f991970 6577 return FALSE;
48229727 6578
99059e56
RM		 6579 stub_sec->size
6580 += find_stub_size_and_template (a8_fixes[i].stub_type, NULL,
6581 NULL);
6582 }
48229727
JB		 6583
6584
906e58ca
NC		 6585 /* Ask the linker to do its stuff. */
6586 (*htab->layout_sections_again) ();
4ba2ef8f 6587 first_veneer_scan = FALSE;
ba93b8ac
DJ		 6588 }
6589
48229727
JB		 6590 /* Add stubs for Cortex-A8 erratum fixes now. */
6591 if (htab->fix_cortex_a8)
6592 {
6593 for (i = 0; i < num_a8_fixes; i++)
99059e56
RM		 6594 {
6595 struct elf32_arm_stub_hash_entry *stub_entry;
6596 char *stub_name = a8_fixes[i].stub_name;
6597 asection *section = a8_fixes[i].section;
6598 unsigned int section_id = a8_fixes[i].section->id;
6599 asection *link_sec = htab->stub_group[section_id].link_sec;
6600 asection *stub_sec = htab->stub_group[section_id].stub_sec;
6601 const insn_sequence *template_sequence;
6602 int template_size, size = 0;
6603
6604 stub_entry = arm_stub_hash_lookup (&htab->stub_hash_table, stub_name,
6605 TRUE, FALSE);
6606 if (stub_entry == NULL)
6607 {
6608 (*_bfd_error_handler) (_("%s: cannot create stub entry %s"),
6609 section->owner,
6610 stub_name);
6611 return FALSE;
6612 }
6613
6614 stub_entry->stub_sec = stub_sec;
0955507f 6615 stub_entry->stub_offset = (bfd_vma) -1;
99059e56
RM		 6616 stub_entry->id_sec = link_sec;
6617 stub_entry->stub_type = a8_fixes[i].stub_type;
8d9d9490 6618 stub_entry->source_value = a8_fixes[i].offset;
99059e56 6619 stub_entry->target_section = a8_fixes[i].section;
8d9d9490 6620 stub_entry->target_value = a8_fixes[i].target_offset;
99059e56 6621 stub_entry->orig_insn = a8_fixes[i].orig_insn;
35fc36a8 6622 stub_entry->branch_type = a8_fixes[i].branch_type;
48229727 6623
99059e56
RM		 6624 size = find_stub_size_and_template (a8_fixes[i].stub_type,
6625 &template_sequence,
6626 &template_size);
48229727 6627
99059e56
RM		 6628 stub_entry->stub_size = size;
6629 stub_entry->stub_template = template_sequence;
6630 stub_entry->stub_template_size = template_size;
6631 }
48229727
JB		 6632
6633 /* Stash the Cortex-A8 erratum fix array for use later in
99059e56 6634 elf32_arm_write_section(). */
48229727
JB		 6635 htab->a8_erratum_fixes = a8_fixes;
6636 htab->num_a8_erratum_fixes = num_a8_fixes;
6637 }
6638 else
6639 {
6640 htab->a8_erratum_fixes = NULL;
6641 htab->num_a8_erratum_fixes = 0;
6642 }
0955507f 6643 return ret;
5e681ec4
PB		 6644}
6645
906e58ca
NC		 6646/* Build all the stubs associated with the current output file. The
6647 stubs are kept in a hash table attached to the main linker hash
6648 table. We also set up the .plt entries for statically linked PIC
6649 functions here. This function is called via arm_elf_finish in the
6650 linker. */
252b5132 6651
906e58ca
NC		 6652bfd_boolean
6653elf32_arm_build_stubs (struct bfd_link_info *info)
252b5132 6654{
906e58ca
NC		 6655 asection *stub_sec;
6656 struct bfd_hash_table *table;
0955507f 6657 enum elf32_arm_stub_type stub_type;
906e58ca 6658 struct elf32_arm_link_hash_table *htab;
252b5132 6659
906e58ca 6660 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 6661 if (htab == NULL)
6662 return FALSE;
252b5132 6663
906e58ca
NC		 6664 for (stub_sec = htab->stub_bfd->sections;
6665 stub_sec != NULL;
6666 stub_sec = stub_sec->next)
252b5132 6667 {
906e58ca
NC		 6668 bfd_size_type size;
6669
8029a119 6670 /* Ignore non-stub sections. */
906e58ca
NC		 6671 if (!strstr (stub_sec->name, STUB_SUFFIX))
6672 continue;
6673
d7c5bd02 6674 /* Allocate memory to hold the linker stubs. Zeroing the stub sections
0955507f
TP		 6675 must at least be done for stub section requiring padding and for SG
6676 veneers to ensure that a non secure code branching to a removed SG
6677 veneer causes an error. */
906e58ca 6678 size = stub_sec->size;
21d799b5 6679 stub_sec->contents = (unsigned char *) bfd_zalloc (htab->stub_bfd, size);
906e58ca
NC		 6680 if (stub_sec->contents == NULL && size != 0)
6681 return FALSE;
0955507f 6682
906e58ca 6683 stub_sec->size = 0;
252b5132
RH		 6684 }
6685
0955507f
TP		 6686 /* Add new SG veneers after those already in the input import library. */
6687 for (stub_type = arm_stub_none + 1; stub_type < max_stub_type; stub_type++)
6688 {
6689 bfd_vma *start_offset_p;
6690 asection **stub_sec_p;
6691
6692 start_offset_p = arm_new_stubs_start_offset_ptr (htab, stub_type);
6693 stub_sec_p = arm_dedicated_stub_input_section_ptr (htab, stub_type);
6694 if (start_offset_p == NULL)
6695 continue;
6696
6697 BFD_ASSERT (stub_sec_p != NULL);
6698 if (*stub_sec_p != NULL)
6699 (*stub_sec_p)->size = *start_offset_p;
6700 }
6701
906e58ca
NC		 6702 /* Build the stubs as directed by the stub hash table. */
6703 table = &htab->stub_hash_table;
6704 bfd_hash_traverse (table, arm_build_one_stub, info);
eb7c4339
NS		 6705 if (htab->fix_cortex_a8)
6706 {
6707 /* Place the cortex a8 stubs last. */
6708 htab->fix_cortex_a8 = -1;
6709 bfd_hash_traverse (table, arm_build_one_stub, info);
6710 }
252b5132 6711
906e58ca 6712 return TRUE;
252b5132
RH		 6713}
6714
9b485d32
NC		 6715/* Locate the Thumb encoded calling stub for NAME. */
6716
252b5132 6717static struct elf_link_hash_entry *
57e8b36a
NC		 6718find_thumb_glue (struct bfd_link_info *link_info,
6719 const char *name,
f2a9dd69 6720 char **error_message)
252b5132
RH		 6721{
6722 char *tmp_name;
6723 struct elf_link_hash_entry *hash;
6724 struct elf32_arm_link_hash_table *hash_table;
6725
6726 /* We need a pointer to the armelf specific hash table. */
6727 hash_table = elf32_arm_hash_table (link_info);
4dfe6ac6
NC		 6728 if (hash_table == NULL)
6729 return NULL;
252b5132 6730
21d799b5 6731 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen (name)
99059e56 6732 + strlen (THUMB2ARM_GLUE_ENTRY_NAME) + 1);
252b5132
RH		 6733
6734 BFD_ASSERT (tmp_name);
6735
6736 sprintf (tmp_name, THUMB2ARM_GLUE_ENTRY_NAME, name);
6737
6738 hash = elf_link_hash_lookup
b34976b6 6739 (&(hash_table)->root, tmp_name, FALSE, FALSE, TRUE);
252b5132 6740
b1657152
AM		 6741 if (hash == NULL
6742 && asprintf (error_message, _("unable to find THUMB glue '%s' for '%s'"),
6743 tmp_name, name) == -1)
6744 *error_message = (char *) bfd_errmsg (bfd_error_system_call);
252b5132
RH		 6745
6746 free (tmp_name);
6747
6748 return hash;
6749}
6750
9b485d32
NC		 6751/* Locate the ARM encoded calling stub for NAME. */
6752
252b5132 6753static struct elf_link_hash_entry *
57e8b36a
NC		 6754find_arm_glue (struct bfd_link_info *link_info,
6755 const char *name,
f2a9dd69 6756 char **error_message)
252b5132
RH		 6757{
6758 char *tmp_name;
6759 struct elf_link_hash_entry *myh;
6760 struct elf32_arm_link_hash_table *hash_table;
6761
6762 /* We need a pointer to the elfarm specific hash table. */
6763 hash_table = elf32_arm_hash_table (link_info);
4dfe6ac6
NC		 6764 if (hash_table == NULL)
6765 return NULL;
252b5132 6766
21d799b5 6767 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen (name)
99059e56 6768 + strlen (ARM2THUMB_GLUE_ENTRY_NAME) + 1);
252b5132
RH		 6769
6770 BFD_ASSERT (tmp_name);
6771
6772 sprintf (tmp_name, ARM2THUMB_GLUE_ENTRY_NAME, name);
6773
6774 myh = elf_link_hash_lookup
b34976b6 6775 (&(hash_table)->root, tmp_name, FALSE, FALSE, TRUE);
252b5132 6776
b1657152
AM		 6777 if (myh == NULL
6778 && asprintf (error_message, _("unable to find ARM glue '%s' for '%s'"),
6779 tmp_name, name) == -1)
6780 *error_message = (char *) bfd_errmsg (bfd_error_system_call);
252b5132
RH		 6781
6782 free (tmp_name);
6783
6784 return myh;
6785}
6786
8f6277f5 6787/* ARM->Thumb glue (static images):
252b5132
RH		 6788
6789 .arm
6790 __func_from_arm:
6791 ldr r12, __func_addr
6792 bx r12
6793 __func_addr:
906e58ca 6794 .word func @ behave as if you saw a ARM_32 reloc.
252b5132 6795
26079076
PB		 6796 (v5t static images)
6797 .arm
6798 __func_from_arm:
6799 ldr pc, __func_addr
6800 __func_addr:
906e58ca 6801 .word func @ behave as if you saw a ARM_32 reloc.
26079076 6802
8f6277f5
PB		 6803 (relocatable images)
6804 .arm
6805 __func_from_arm:
6806 ldr r12, __func_offset
6807 add r12, r12, pc
6808 bx r12
6809 __func_offset:
8029a119 6810 .word func - . */
8f6277f5
PB		 6811
6812#define ARM2THUMB_STATIC_GLUE_SIZE 12
252b5132
RH		 6813static const insn32 a2t1_ldr_insn = 0xe59fc000;
6814static const insn32 a2t2_bx_r12_insn = 0xe12fff1c;
6815static const insn32 a2t3_func_addr_insn = 0x00000001;
6816
26079076
PB		 6817#define ARM2THUMB_V5_STATIC_GLUE_SIZE 8
6818static const insn32 a2t1v5_ldr_insn = 0xe51ff004;
6819static const insn32 a2t2v5_func_addr_insn = 0x00000001;
6820
8f6277f5
PB		 6821#define ARM2THUMB_PIC_GLUE_SIZE 16
6822static const insn32 a2t1p_ldr_insn = 0xe59fc004;
6823static const insn32 a2t2p_add_pc_insn = 0xe08cc00f;
6824static const insn32 a2t3p_bx_r12_insn = 0xe12fff1c;
6825
9b485d32 6826/* Thumb->ARM: Thumb->(non-interworking aware) ARM
252b5132 6827
8029a119
NC		 6828 .thumb .thumb
6829 .align 2 .align 2
6830 __func_from_thumb: __func_from_thumb:
6831 bx pc push {r6, lr}
6832 nop ldr r6, __func_addr
6833 .arm mov lr, pc
6834 b func bx r6
99059e56
RM		 6835 .arm
6836 ;; back_to_thumb
6837 ldmia r13! {r6, lr}
6838 bx lr
6839 __func_addr:
6840 .word func */
252b5132
RH		 6841
6842#define THUMB2ARM_GLUE_SIZE 8
6843static const insn16 t2a1_bx_pc_insn = 0x4778;
6844static const insn16 t2a2_noop_insn = 0x46c0;
6845static const insn32 t2a3_b_insn = 0xea000000;
6846
c7b8f16e 6847#define VFP11_ERRATUM_VENEER_SIZE 8
a504d23a
LA		 6848#define STM32L4XX_ERRATUM_LDM_VENEER_SIZE 16
6849#define STM32L4XX_ERRATUM_VLDM_VENEER_SIZE 24
c7b8f16e 6850
845b51d6
PB		 6851#define ARM_BX_VENEER_SIZE 12
6852static const insn32 armbx1_tst_insn = 0xe3100001;
6853static const insn32 armbx2_moveq_insn = 0x01a0f000;
6854static const insn32 armbx3_bx_insn = 0xe12fff10;
6855
7e392df6 6856#ifndef ELFARM_NABI_C_INCLUDED
8029a119
NC		 6857static void
6858arm_allocate_glue_section_space (bfd * abfd, bfd_size_type size, const char * name)
252b5132
RH		 6859{
6860 asection * s;
8029a119 6861 bfd_byte * contents;
252b5132 6862
8029a119 6863 if (size == 0)
3e6b1042
DJ		 6864 {
6865 /* Do not include empty glue sections in the output. */
6866 if (abfd != NULL)
6867 {
3d4d4302 6868 s = bfd_get_linker_section (abfd, name);
3e6b1042
DJ		 6869 if (s != NULL)
6870 s->flags |= SEC_EXCLUDE;
6871 }
6872 return;
6873 }
252b5132 6874
8029a119 6875 BFD_ASSERT (abfd != NULL);
252b5132 6876
3d4d4302 6877 s = bfd_get_linker_section (abfd, name);
8029a119 6878 BFD_ASSERT (s != NULL);
252b5132 6879
21d799b5 6880 contents = (bfd_byte *) bfd_alloc (abfd, size);
252b5132 6881
8029a119
NC		 6882 BFD_ASSERT (s->size == size);
6883 s->contents = contents;
6884}
906e58ca 6885
8029a119
NC		 6886bfd_boolean
6887bfd_elf32_arm_allocate_interworking_sections (struct bfd_link_info * info)
6888{
6889 struct elf32_arm_link_hash_table * globals;
906e58ca 6890
8029a119
NC		 6891 globals = elf32_arm_hash_table (info);
6892 BFD_ASSERT (globals != NULL);
906e58ca 6893
8029a119
NC		 6894 arm_allocate_glue_section_space (globals->bfd_of_glue_owner,
6895 globals->arm_glue_size,
6896 ARM2THUMB_GLUE_SECTION_NAME);
906e58ca 6897
8029a119
NC		 6898 arm_allocate_glue_section_space (globals->bfd_of_glue_owner,
6899 globals->thumb_glue_size,
6900 THUMB2ARM_GLUE_SECTION_NAME);
252b5132 6901
8029a119
NC		 6902 arm_allocate_glue_section_space (globals->bfd_of_glue_owner,
6903 globals->vfp11_erratum_glue_size,
6904 VFP11_ERRATUM_VENEER_SECTION_NAME);
845b51d6 6905
a504d23a
LA		 6906 arm_allocate_glue_section_space (globals->bfd_of_glue_owner,
6907 globals->stm32l4xx_erratum_glue_size,
6908 STM32L4XX_ERRATUM_VENEER_SECTION_NAME);
6909
8029a119
NC		 6910 arm_allocate_glue_section_space (globals->bfd_of_glue_owner,
6911 globals->bx_glue_size,
845b51d6
PB		 6912 ARM_BX_GLUE_SECTION_NAME);
6913
b34976b6 6914 return TRUE;
252b5132
RH		 6915}
6916
a4fd1a8e 6917/* Allocate space and symbols for calling a Thumb function from Arm mode.
906e58ca
NC		 6918 returns the symbol identifying the stub. */
6919
a4fd1a8e 6920static struct elf_link_hash_entry *
57e8b36a
NC		 6921record_arm_to_thumb_glue (struct bfd_link_info * link_info,
6922 struct elf_link_hash_entry * h)
252b5132
RH		 6923{
6924 const char * name = h->root.root.string;
63b0f745 6925 asection * s;
252b5132
RH		 6926 char * tmp_name;
6927 struct elf_link_hash_entry * myh;
14a793b2 6928 struct bfd_link_hash_entry * bh;
252b5132 6929 struct elf32_arm_link_hash_table * globals;
dc810e39 6930 bfd_vma val;
2f475487 6931 bfd_size_type size;
252b5132
RH		 6932
6933 globals = elf32_arm_hash_table (link_info);
252b5132
RH		 6934 BFD_ASSERT (globals != NULL);
6935 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
6936
3d4d4302 6937 s = bfd_get_linker_section
252b5132
RH		 6938 (globals->bfd_of_glue_owner, ARM2THUMB_GLUE_SECTION_NAME);
6939
252b5132
RH		 6940 BFD_ASSERT (s != NULL);
6941
21d799b5 6942 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen (name)
99059e56 6943 + strlen (ARM2THUMB_GLUE_ENTRY_NAME) + 1);
252b5132
RH		 6944
6945 BFD_ASSERT (tmp_name);
6946
6947 sprintf (tmp_name, ARM2THUMB_GLUE_ENTRY_NAME, name);
6948
6949 myh = elf_link_hash_lookup
b34976b6 6950 (&(globals)->root, tmp_name, FALSE, FALSE, TRUE);
252b5132
RH		 6951
6952 if (myh != NULL)
6953 {
9b485d32 6954 /* We've already seen this guy. */
252b5132 6955 free (tmp_name);
a4fd1a8e 6956 return myh;
252b5132
RH		 6957 }
6958
57e8b36a
NC		 6959 /* The only trick here is using hash_table->arm_glue_size as the value.
6960 Even though the section isn't allocated yet, this is where we will be
3dccd7b7
DJ		 6961 putting it. The +1 on the value marks that the stub has not been
6962 output yet - not that it is a Thumb function. */
14a793b2 6963 bh = NULL;
dc810e39
AM		 6964 val = globals->arm_glue_size + 1;
6965 _bfd_generic_link_add_one_symbol (link_info, globals->bfd_of_glue_owner,
6966 tmp_name, BSF_GLOBAL, s, val,
b34976b6 6967 NULL, TRUE, FALSE, &bh);
252b5132 6968
b7693d02
DJ		 6969 myh = (struct elf_link_hash_entry *) bh;
6970 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
6971 myh->forced_local = 1;
6972
252b5132
RH		 6973 free (tmp_name);
6974
0e1862bb
L		 6975 if (bfd_link_pic (link_info)
6976 || globals->root.is_relocatable_executable
27e55c4d 6977 || globals->pic_veneer)
2f475487 6978 size = ARM2THUMB_PIC_GLUE_SIZE;
26079076
PB		 6979 else if (globals->use_blx)
6980 size = ARM2THUMB_V5_STATIC_GLUE_SIZE;
8f6277f5 6981 else
2f475487
AM		 6982 size = ARM2THUMB_STATIC_GLUE_SIZE;
6983
6984 s->size += size;
6985 globals->arm_glue_size += size;
252b5132 6986
a4fd1a8e 6987 return myh;
252b5132
RH		 6988}
6989
845b51d6
PB		 6990/* Allocate space for ARMv4 BX veneers. */
6991
6992static void
6993record_arm_bx_glue (struct bfd_link_info * link_info, int reg)
6994{
6995 asection * s;
6996 struct elf32_arm_link_hash_table *globals;
6997 char *tmp_name;
6998 struct elf_link_hash_entry *myh;
6999 struct bfd_link_hash_entry *bh;
7000 bfd_vma val;
7001
7002 /* BX PC does not need a veneer. */
7003 if (reg == 15)
7004 return;
7005
7006 globals = elf32_arm_hash_table (link_info);
845b51d6
PB		 7007 BFD_ASSERT (globals != NULL);
7008 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
7009
7010 /* Check if this veneer has already been allocated. */
7011 if (globals->bx_glue_offset[reg])
7012 return;
7013
3d4d4302 7014 s = bfd_get_linker_section
845b51d6
PB		 7015 (globals->bfd_of_glue_owner, ARM_BX_GLUE_SECTION_NAME);
7016
7017 BFD_ASSERT (s != NULL);
7018
7019 /* Add symbol for veneer. */
21d799b5
NC		 7020 tmp_name = (char *)
7021 bfd_malloc ((bfd_size_type) strlen (ARM_BX_GLUE_ENTRY_NAME) + 1);
906e58ca 7022
845b51d6 7023 BFD_ASSERT (tmp_name);
906e58ca 7024
845b51d6 7025 sprintf (tmp_name, ARM_BX_GLUE_ENTRY_NAME, reg);
906e58ca 7026
845b51d6
PB		 7027 myh = elf_link_hash_lookup
7028 (&(globals)->root, tmp_name, FALSE, FALSE, FALSE);
906e58ca 7029
845b51d6 7030 BFD_ASSERT (myh == NULL);
906e58ca 7031
845b51d6
PB		 7032 bh = NULL;
7033 val = globals->bx_glue_size;
7034 _bfd_generic_link_add_one_symbol (link_info, globals->bfd_of_glue_owner,
99059e56
RM		 7035 tmp_name, BSF_FUNCTION | BSF_LOCAL, s, val,
7036 NULL, TRUE, FALSE, &bh);
845b51d6
PB		 7037
7038 myh = (struct elf_link_hash_entry *) bh;
7039 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
7040 myh->forced_local = 1;
7041
7042 s->size += ARM_BX_VENEER_SIZE;
7043 globals->bx_glue_offset[reg] = globals->bx_glue_size | 2;
7044 globals->bx_glue_size += ARM_BX_VENEER_SIZE;
7045}
7046
7047
c7b8f16e
JB		 7048/* Add an entry to the code/data map for section SEC. */
7049
7050static void
7051elf32_arm_section_map_add (asection *sec, char type, bfd_vma vma)
7052{
7053 struct _arm_elf_section_data *sec_data = elf32_arm_section_data (sec);
7054 unsigned int newidx;
906e58ca 7055
c7b8f16e
JB		 7056 if (sec_data->map == NULL)
7057 {
21d799b5 7058 sec_data->map = (elf32_arm_section_map *)
99059e56 7059 bfd_malloc (sizeof (elf32_arm_section_map));
c7b8f16e
JB		 7060 sec_data->mapcount = 0;
7061 sec_data->mapsize = 1;
7062 }
906e58ca 7063
c7b8f16e 7064 newidx = sec_data->mapcount++;
906e58ca 7065
c7b8f16e
JB		 7066 if (sec_data->mapcount > sec_data->mapsize)
7067 {
7068 sec_data->mapsize *= 2;
21d799b5 7069 sec_data->map = (elf32_arm_section_map *)
99059e56
RM		 7070 bfd_realloc_or_free (sec_data->map, sec_data->mapsize
7071 * sizeof (elf32_arm_section_map));
515ef31d
NC		 7072 }
7073
7074 if (sec_data->map)
7075 {
7076 sec_data->map[newidx].vma = vma;
7077 sec_data->map[newidx].type = type;
c7b8f16e 7078 }
c7b8f16e
JB		 7079}
7080
7081
7082/* Record information about a VFP11 denorm-erratum veneer. Only ARM-mode
7083 veneers are handled for now. */
7084
7085static bfd_vma
7086record_vfp11_erratum_veneer (struct bfd_link_info *link_info,
99059e56
RM		 7087 elf32_vfp11_erratum_list *branch,
7088 bfd *branch_bfd,
7089 asection *branch_sec,
7090 unsigned int offset)
c7b8f16e
JB		 7091{
7092 asection *s;
7093 struct elf32_arm_link_hash_table *hash_table;
7094 char *tmp_name;
7095 struct elf_link_hash_entry *myh;
7096 struct bfd_link_hash_entry *bh;
7097 bfd_vma val;
7098 struct _arm_elf_section_data *sec_data;
c7b8f16e 7099 elf32_vfp11_erratum_list *newerr;
906e58ca 7100
c7b8f16e 7101 hash_table = elf32_arm_hash_table (link_info);
c7b8f16e
JB		 7102 BFD_ASSERT (hash_table != NULL);
7103 BFD_ASSERT (hash_table->bfd_of_glue_owner != NULL);
906e58ca 7104
3d4d4302 7105 s = bfd_get_linker_section
c7b8f16e 7106 (hash_table->bfd_of_glue_owner, VFP11_ERRATUM_VENEER_SECTION_NAME);
906e58ca 7107
c7b8f16e 7108 sec_data = elf32_arm_section_data (s);
906e58ca 7109
c7b8f16e 7110 BFD_ASSERT (s != NULL);
906e58ca 7111
21d799b5 7112 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen
99059e56 7113 (VFP11_ERRATUM_VENEER_ENTRY_NAME) + 10);
906e58ca 7114
c7b8f16e 7115 BFD_ASSERT (tmp_name);
906e58ca 7116
c7b8f16e
JB		 7117 sprintf (tmp_name, VFP11_ERRATUM_VENEER_ENTRY_NAME,
7118 hash_table->num_vfp11_fixes);
906e58ca 7119
c7b8f16e
JB		 7120 myh = elf_link_hash_lookup
7121 (&(hash_table)->root, tmp_name, FALSE, FALSE, FALSE);
906e58ca 7122
c7b8f16e 7123 BFD_ASSERT (myh == NULL);
906e58ca 7124
c7b8f16e
JB		 7125 bh = NULL;
7126 val = hash_table->vfp11_erratum_glue_size;
7127 _bfd_generic_link_add_one_symbol (link_info, hash_table->bfd_of_glue_owner,
99059e56
RM		 7128 tmp_name, BSF_FUNCTION | BSF_LOCAL, s, val,
7129 NULL, TRUE, FALSE, &bh);
c7b8f16e
JB		 7130
7131 myh = (struct elf_link_hash_entry *) bh;
7132 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
7133 myh->forced_local = 1;
7134
7135 /* Link veneer back to calling location. */
c7e2358a 7136 sec_data->erratumcount += 1;
21d799b5
NC		 7137 newerr = (elf32_vfp11_erratum_list *)
7138 bfd_zmalloc (sizeof (elf32_vfp11_erratum_list));
906e58ca 7139
c7b8f16e
JB		 7140 newerr->type = VFP11_ERRATUM_ARM_VENEER;
7141 newerr->vma = -1;
7142 newerr->u.v.branch = branch;
7143 newerr->u.v.id = hash_table->num_vfp11_fixes;
7144 branch->u.b.veneer = newerr;
7145
7146 newerr->next = sec_data->erratumlist;
7147 sec_data->erratumlist = newerr;
7148
7149 /* A symbol for the return from the veneer. */
7150 sprintf (tmp_name, VFP11_ERRATUM_VENEER_ENTRY_NAME "_r",
7151 hash_table->num_vfp11_fixes);
7152
7153 myh = elf_link_hash_lookup
7154 (&(hash_table)->root, tmp_name, FALSE, FALSE, FALSE);
906e58ca 7155
c7b8f16e
JB		 7156 if (myh != NULL)
7157 abort ();
7158
7159 bh = NULL;
7160 val = offset + 4;
7161 _bfd_generic_link_add_one_symbol (link_info, branch_bfd, tmp_name, BSF_LOCAL,
7162 branch_sec, val, NULL, TRUE, FALSE, &bh);
906e58ca 7163
c7b8f16e
JB		 7164 myh = (struct elf_link_hash_entry *) bh;
7165 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
7166 myh->forced_local = 1;
7167
7168 free (tmp_name);
906e58ca 7169
c7b8f16e
JB		 7170 /* Generate a mapping symbol for the veneer section, and explicitly add an
7171 entry for that symbol to the code/data map for the section. */
7172 if (hash_table->vfp11_erratum_glue_size == 0)
7173 {
7174 bh = NULL;
7175 /* FIXME: Creates an ARM symbol. Thumb mode will need attention if it
99059e56 7176 ever requires this erratum fix. */
c7b8f16e
JB		 7177 _bfd_generic_link_add_one_symbol (link_info,
7178 hash_table->bfd_of_glue_owner, "$a",
7179 BSF_LOCAL, s, 0, NULL,
99059e56 7180 TRUE, FALSE, &bh);
c7b8f16e
JB		 7181
7182 myh = (struct elf_link_hash_entry *) bh;
7183 myh->type = ELF_ST_INFO (STB_LOCAL, STT_NOTYPE);
7184 myh->forced_local = 1;
906e58ca 7185
c7b8f16e 7186 /* The elf32_arm_init_maps function only cares about symbols from input
99059e56
RM		 7187 BFDs. We must make a note of this generated mapping symbol
7188 ourselves so that code byteswapping works properly in
7189 elf32_arm_write_section. */
c7b8f16e
JB		 7190 elf32_arm_section_map_add (s, 'a', 0);
7191 }
906e58ca 7192
c7b8f16e
JB		 7193 s->size += VFP11_ERRATUM_VENEER_SIZE;
7194 hash_table->vfp11_erratum_glue_size += VFP11_ERRATUM_VENEER_SIZE;
7195 hash_table->num_vfp11_fixes++;
906e58ca 7196
c7b8f16e
JB		 7197 /* The offset of the veneer. */
7198 return val;
7199}
7200
a504d23a
LA		 7201/* Record information about a STM32L4XX STM erratum veneer. Only THUMB-mode
7202 veneers need to be handled because used only in Cortex-M. */
7203
7204static bfd_vma
7205record_stm32l4xx_erratum_veneer (struct bfd_link_info *link_info,
7206 elf32_stm32l4xx_erratum_list *branch,
7207 bfd *branch_bfd,
7208 asection *branch_sec,
7209 unsigned int offset,
7210 bfd_size_type veneer_size)
7211{
7212 asection *s;
7213 struct elf32_arm_link_hash_table *hash_table;
7214 char *tmp_name;
7215 struct elf_link_hash_entry *myh;
7216 struct bfd_link_hash_entry *bh;
7217 bfd_vma val;
7218 struct _arm_elf_section_data *sec_data;
7219 elf32_stm32l4xx_erratum_list *newerr;
7220
7221 hash_table = elf32_arm_hash_table (link_info);
7222 BFD_ASSERT (hash_table != NULL);
7223 BFD_ASSERT (hash_table->bfd_of_glue_owner != NULL);
7224
7225 s = bfd_get_linker_section
7226 (hash_table->bfd_of_glue_owner, STM32L4XX_ERRATUM_VENEER_SECTION_NAME);
7227
7228 BFD_ASSERT (s != NULL);
7229
7230 sec_data = elf32_arm_section_data (s);
7231
7232 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen
7233 (STM32L4XX_ERRATUM_VENEER_ENTRY_NAME) + 10);
7234
7235 BFD_ASSERT (tmp_name);
7236
7237 sprintf (tmp_name, STM32L4XX_ERRATUM_VENEER_ENTRY_NAME,
7238 hash_table->num_stm32l4xx_fixes);
7239
7240 myh = elf_link_hash_lookup
7241 (&(hash_table)->root, tmp_name, FALSE, FALSE, FALSE);
7242
7243 BFD_ASSERT (myh == NULL);
7244
7245 bh = NULL;
7246 val = hash_table->stm32l4xx_erratum_glue_size;
7247 _bfd_generic_link_add_one_symbol (link_info, hash_table->bfd_of_glue_owner,
7248 tmp_name, BSF_FUNCTION | BSF_LOCAL, s, val,
7249 NULL, TRUE, FALSE, &bh);
7250
7251 myh = (struct elf_link_hash_entry *) bh;
7252 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
7253 myh->forced_local = 1;
7254
7255 /* Link veneer back to calling location. */
7256 sec_data->stm32l4xx_erratumcount += 1;
7257 newerr = (elf32_stm32l4xx_erratum_list *)
7258 bfd_zmalloc (sizeof (elf32_stm32l4xx_erratum_list));
7259
7260 newerr->type = STM32L4XX_ERRATUM_VENEER;
7261 newerr->vma = -1;
7262 newerr->u.v.branch = branch;
7263 newerr->u.v.id = hash_table->num_stm32l4xx_fixes;
7264 branch->u.b.veneer = newerr;
7265
7266 newerr->next = sec_data->stm32l4xx_erratumlist;
7267 sec_data->stm32l4xx_erratumlist = newerr;
7268
7269 /* A symbol for the return from the veneer. */
7270 sprintf (tmp_name, STM32L4XX_ERRATUM_VENEER_ENTRY_NAME "_r",
7271 hash_table->num_stm32l4xx_fixes);
7272
7273 myh = elf_link_hash_lookup
7274 (&(hash_table)->root, tmp_name, FALSE, FALSE, FALSE);
7275
7276 if (myh != NULL)
7277 abort ();
7278
7279 bh = NULL;
7280 val = offset + 4;
7281 _bfd_generic_link_add_one_symbol (link_info, branch_bfd, tmp_name, BSF_LOCAL,
7282 branch_sec, val, NULL, TRUE, FALSE, &bh);
7283
7284 myh = (struct elf_link_hash_entry *) bh;
7285 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
7286 myh->forced_local = 1;
7287
7288 free (tmp_name);
7289
7290 /* Generate a mapping symbol for the veneer section, and explicitly add an
7291 entry for that symbol to the code/data map for the section. */
7292 if (hash_table->stm32l4xx_erratum_glue_size == 0)
7293 {
7294 bh = NULL;
7295 /* Creates a THUMB symbol since there is no other choice. */
7296 _bfd_generic_link_add_one_symbol (link_info,
7297 hash_table->bfd_of_glue_owner, "$t",
7298 BSF_LOCAL, s, 0, NULL,
7299 TRUE, FALSE, &bh);
7300
7301 myh = (struct elf_link_hash_entry *) bh;
7302 myh->type = ELF_ST_INFO (STB_LOCAL, STT_NOTYPE);
7303 myh->forced_local = 1;
7304
7305 /* The elf32_arm_init_maps function only cares about symbols from input
7306 BFDs. We must make a note of this generated mapping symbol
7307 ourselves so that code byteswapping works properly in
7308 elf32_arm_write_section. */
7309 elf32_arm_section_map_add (s, 't', 0);
7310 }
7311
7312 s->size += veneer_size;
7313 hash_table->stm32l4xx_erratum_glue_size += veneer_size;
7314 hash_table->num_stm32l4xx_fixes++;
7315
7316 /* The offset of the veneer. */
7317 return val;
7318}
7319
8029a119 7320#define ARM_GLUE_SECTION_FLAGS \
3e6b1042
DJ		 7321 (SEC_ALLOC | SEC_LOAD | SEC_HAS_CONTENTS | SEC_IN_MEMORY | SEC_CODE \
7322 | SEC_READONLY | SEC_LINKER_CREATED)
8029a119
NC		 7323
7324/* Create a fake section for use by the ARM backend of the linker. */
7325
7326static bfd_boolean
7327arm_make_glue_section (bfd * abfd, const char * name)
7328{
7329 asection * sec;
7330
3d4d4302 7331 sec = bfd_get_linker_section (abfd, name);
8029a119
NC		 7332 if (sec != NULL)
7333 /* Already made. */
7334 return TRUE;
7335
3d4d4302 7336 sec = bfd_make_section_anyway_with_flags (abfd, name, ARM_GLUE_SECTION_FLAGS);
8029a119
NC		 7337
7338 if (sec == NULL
7339 || !bfd_set_section_alignment (abfd, sec, 2))
7340 return FALSE;
7341
7342 /* Set the gc mark to prevent the section from being removed by garbage
7343 collection, despite the fact that no relocs refer to this section. */
7344 sec->gc_mark = 1;
7345
7346 return TRUE;
7347}
7348
1db37fe6
YG		 7349/* Set size of .plt entries. This function is called from the
7350 linker scripts in ld/emultempl/{armelf}.em. */
7351
7352void
7353bfd_elf32_arm_use_long_plt (void)
7354{
7355 elf32_arm_use_long_plt_entry = TRUE;
7356}
7357
8afb0e02
NC		 7358/* Add the glue sections to ABFD. This function is called from the
7359 linker scripts in ld/emultempl/{armelf}.em. */
9b485d32 7360
b34976b6 7361bfd_boolean
57e8b36a
NC		 7362bfd_elf32_arm_add_glue_sections_to_bfd (bfd *abfd,
7363 struct bfd_link_info *info)
252b5132 7364{
a504d23a
LA		 7365 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (info);
7366 bfd_boolean dostm32l4xx = globals
7367 && globals->stm32l4xx_fix != BFD_ARM_STM32L4XX_FIX_NONE;
7368 bfd_boolean addglue;
7369
8afb0e02
NC		 7370 /* If we are only performing a partial
7371 link do not bother adding the glue. */
0e1862bb 7372 if (bfd_link_relocatable (info))
b34976b6 7373 return TRUE;
252b5132 7374
a504d23a 7375 addglue = arm_make_glue_section (abfd, ARM2THUMB_GLUE_SECTION_NAME)
8029a119
NC		 7376 && arm_make_glue_section (abfd, THUMB2ARM_GLUE_SECTION_NAME)
7377 && arm_make_glue_section (abfd, VFP11_ERRATUM_VENEER_SECTION_NAME)
7378 && arm_make_glue_section (abfd, ARM_BX_GLUE_SECTION_NAME);
a504d23a
LA		 7379
7380 if (!dostm32l4xx)
7381 return addglue;
7382
7383 return addglue
7384 && arm_make_glue_section (abfd, STM32L4XX_ERRATUM_VENEER_SECTION_NAME);
8afb0e02
NC		 7385}
7386
daa4adae
TP		 7387/* Mark output sections of veneers needing a dedicated one with SEC_KEEP. This
7388 ensures they are not marked for deletion by
7389 strip_excluded_output_sections () when veneers are going to be created
7390 later. Not doing so would trigger assert on empty section size in
7391 lang_size_sections_1 (). */
7392
7393void
7394bfd_elf32_arm_keep_private_stub_output_sections (struct bfd_link_info *info)
7395{
7396 enum elf32_arm_stub_type stub_type;
7397
7398 /* If we are only performing a partial
7399 link do not bother adding the glue. */
7400 if (bfd_link_relocatable (info))
7401 return;
7402
7403 for (stub_type = arm_stub_none + 1; stub_type < max_stub_type; stub_type++)
7404 {
7405 asection *out_sec;
7406 const char *out_sec_name;
7407
7408 if (!arm_dedicated_stub_output_section_required (stub_type))
7409 continue;
7410
7411 out_sec_name = arm_dedicated_stub_output_section_name (stub_type);
7412 out_sec = bfd_get_section_by_name (info->output_bfd, out_sec_name);
7413 if (out_sec != NULL)
7414 out_sec->flags |= SEC_KEEP;
7415 }
7416}
7417
8afb0e02
NC		 7418/* Select a BFD to be used to hold the sections used by the glue code.
7419 This function is called from the linker scripts in ld/emultempl/
8029a119 7420 {armelf/pe}.em. */
8afb0e02 7421
b34976b6 7422bfd_boolean
57e8b36a 7423bfd_elf32_arm_get_bfd_for_interworking (bfd *abfd, struct bfd_link_info *info)
8afb0e02
NC		 7424{
7425 struct elf32_arm_link_hash_table *globals;
7426
7427 /* If we are only performing a partial link
7428 do not bother getting a bfd to hold the glue. */
0e1862bb 7429 if (bfd_link_relocatable (info))
b34976b6 7430 return TRUE;
8afb0e02 7431
b7693d02
DJ		 7432 /* Make sure we don't attach the glue sections to a dynamic object. */
7433 BFD_ASSERT (!(abfd->flags & DYNAMIC));
7434
8afb0e02 7435 globals = elf32_arm_hash_table (info);
8afb0e02
NC		 7436 BFD_ASSERT (globals != NULL);
7437
7438 if (globals->bfd_of_glue_owner != NULL)
b34976b6 7439 return TRUE;
8afb0e02 7440
252b5132
RH		 7441 /* Save the bfd for later use. */
7442 globals->bfd_of_glue_owner = abfd;
cedb70c5 7443
b34976b6 7444 return TRUE;
252b5132
RH		 7445}
7446
906e58ca
NC		 7447static void
7448check_use_blx (struct elf32_arm_link_hash_table *globals)
39b41c9c 7449{
2de70689
MGD		 7450 int cpu_arch;
7451
b38cadfb 7452 cpu_arch = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC,
2de70689
MGD		 7453 Tag_CPU_arch);
7454
7455 if (globals->fix_arm1176)
7456 {
7457 if (cpu_arch == TAG_CPU_ARCH_V6T2 || cpu_arch > TAG_CPU_ARCH_V6K)
7458 globals->use_blx = 1;
7459 }
7460 else
7461 {
7462 if (cpu_arch > TAG_CPU_ARCH_V4T)
7463 globals->use_blx = 1;
7464 }
39b41c9c
PB		 7465}
7466
b34976b6 7467bfd_boolean
57e8b36a 7468bfd_elf32_arm_process_before_allocation (bfd *abfd,
d504ffc8 7469 struct bfd_link_info *link_info)
252b5132
RH		 7470{
7471 Elf_Internal_Shdr *symtab_hdr;
6cdc0ccc 7472 Elf_Internal_Rela *internal_relocs = NULL;
252b5132
RH		 7473 Elf_Internal_Rela *irel, *irelend;
7474 bfd_byte *contents = NULL;
252b5132
RH		 7475
7476 asection *sec;
7477 struct elf32_arm_link_hash_table *globals;
7478
7479 /* If we are only performing a partial link do not bother
7480 to construct any glue. */
0e1862bb 7481 if (bfd_link_relocatable (link_info))
b34976b6 7482 return TRUE;
252b5132 7483
39ce1a6a
NC		 7484 /* Here we have a bfd that is to be included on the link. We have a
7485 hook to do reloc rummaging, before section sizes are nailed down. */
252b5132 7486 globals = elf32_arm_hash_table (link_info);
252b5132 7487 BFD_ASSERT (globals != NULL);
39ce1a6a
NC		 7488
7489 check_use_blx (globals);
252b5132 7490
d504ffc8 7491 if (globals->byteswap_code && !bfd_big_endian (abfd))
e489d0ae 7492 {
d003868e
AM		 7493 _bfd_error_handler (_("%B: BE8 images only valid in big-endian mode."),
7494 abfd);
e489d0ae
PB		 7495 return FALSE;
7496 }
f21f3fe0 7497
39ce1a6a
NC		 7498 /* PR 5398: If we have not decided to include any loadable sections in
7499 the output then we will not have a glue owner bfd. This is OK, it
7500 just means that there is nothing else for us to do here. */
7501 if (globals->bfd_of_glue_owner == NULL)
7502 return TRUE;
7503
252b5132
RH		 7504 /* Rummage around all the relocs and map the glue vectors. */
7505 sec = abfd->sections;
7506
7507 if (sec == NULL)
b34976b6 7508 return TRUE;
252b5132
RH		 7509
7510 for (; sec != NULL; sec = sec->next)
7511 {
7512 if (sec->reloc_count == 0)
7513 continue;
7514
2f475487
AM		 7515 if ((sec->flags & SEC_EXCLUDE) != 0)
7516 continue;
7517
0ffa91dd 7518 symtab_hdr = & elf_symtab_hdr (abfd);
252b5132 7519
9b485d32 7520 /* Load the relocs. */
6cdc0ccc 7521 internal_relocs
906e58ca 7522 = _bfd_elf_link_read_relocs (abfd, sec, NULL, NULL, FALSE);
252b5132 7523
6cdc0ccc
AM		 7524 if (internal_relocs == NULL)
7525 goto error_return;
252b5132 7526
6cdc0ccc
AM		 7527 irelend = internal_relocs + sec->reloc_count;
7528 for (irel = internal_relocs; irel < irelend; irel++)
252b5132
RH		 7529 {
7530 long r_type;
7531 unsigned long r_index;
252b5132
RH		 7532
7533 struct elf_link_hash_entry *h;
7534
7535 r_type = ELF32_R_TYPE (irel->r_info);
7536 r_index = ELF32_R_SYM (irel->r_info);
7537
9b485d32 7538 /* These are the only relocation types we care about. */
ba96a88f 7539 if ( r_type != R_ARM_PC24
845b51d6 7540 && (r_type != R_ARM_V4BX || globals->fix_v4bx < 2))
252b5132
RH		 7541 continue;
7542
7543 /* Get the section contents if we haven't done so already. */
7544 if (contents == NULL)
7545 {
7546 /* Get cached copy if it exists. */
7547 if (elf_section_data (sec)->this_hdr.contents != NULL)
7548 contents = elf_section_data (sec)->this_hdr.contents;
7549 else
7550 {
7551 /* Go get them off disk. */
57e8b36a 7552 if (! bfd_malloc_and_get_section (abfd, sec, &contents))
252b5132
RH		 7553 goto error_return;
7554 }
7555 }
7556
845b51d6
PB		 7557 if (r_type == R_ARM_V4BX)
7558 {
7559 int reg;
7560
7561 reg = bfd_get_32 (abfd, contents + irel->r_offset) & 0xf;
7562 record_arm_bx_glue (link_info, reg);
7563 continue;
7564 }
7565
a7c10850 7566 /* If the relocation is not against a symbol it cannot concern us. */
252b5132
RH		 7567 h = NULL;
7568
9b485d32 7569 /* We don't care about local symbols. */
252b5132
RH		 7570 if (r_index < symtab_hdr->sh_info)
7571 continue;
7572
9b485d32 7573 /* This is an external symbol. */
252b5132
RH		 7574 r_index -= symtab_hdr->sh_info;
7575 h = (struct elf_link_hash_entry *)
7576 elf_sym_hashes (abfd)[r_index];
7577
7578 /* If the relocation is against a static symbol it must be within
7579 the current section and so cannot be a cross ARM/Thumb relocation. */
7580 if (h == NULL)
7581 continue;
7582
d504ffc8
DJ		 7583 /* If the call will go through a PLT entry then we do not need
7584 glue. */
362d30a1 7585 if (globals->root.splt != NULL && h->plt.offset != (bfd_vma) -1)
b7693d02
DJ		 7586 continue;
7587
252b5132
RH		 7588 switch (r_type)
7589 {
7590 case R_ARM_PC24:
7591 /* This one is a call from arm code. We need to look up
99059e56
RM		 7592 the target of the call. If it is a thumb target, we
7593 insert glue. */
39d911fc
TP		 7594 if (ARM_GET_SYM_BRANCH_TYPE (h->target_internal)
7595 == ST_BRANCH_TO_THUMB)
252b5132
RH		 7596 record_arm_to_thumb_glue (link_info, h);
7597 break;
7598
252b5132 7599 default:
c6596c5e 7600 abort ();
252b5132
RH		 7601 }
7602 }
6cdc0ccc
AM		 7603
7604 if (contents != NULL
7605 && elf_section_data (sec)->this_hdr.contents != contents)
7606 free (contents);
7607 contents = NULL;
7608
7609 if (internal_relocs != NULL
7610 && elf_section_data (sec)->relocs != internal_relocs)
7611 free (internal_relocs);
7612 internal_relocs = NULL;
252b5132
RH		 7613 }
7614
b34976b6 7615 return TRUE;
9a5aca8c 7616
252b5132 7617error_return:
6cdc0ccc
AM		 7618 if (contents != NULL
7619 && elf_section_data (sec)->this_hdr.contents != contents)
7620 free (contents);
7621 if (internal_relocs != NULL
7622 && elf_section_data (sec)->relocs != internal_relocs)
7623 free (internal_relocs);
9a5aca8c 7624
b34976b6 7625 return FALSE;
252b5132 7626}
7e392df6 7627#endif
252b5132 7628
eb043451 7629
c7b8f16e
JB		 7630/* Initialise maps of ARM/Thumb/data for input BFDs. */
7631
7632void
7633bfd_elf32_arm_init_maps (bfd *abfd)
7634{
7635 Elf_Internal_Sym *isymbuf;
7636 Elf_Internal_Shdr *hdr;
7637 unsigned int i, localsyms;
7638
af1f4419
NC		 7639 /* PR 7093: Make sure that we are dealing with an arm elf binary. */
7640 if (! is_arm_elf (abfd))
7641 return;
7642
c7b8f16e
JB		 7643 if ((abfd->flags & DYNAMIC) != 0)
7644 return;
7645
0ffa91dd 7646 hdr = & elf_symtab_hdr (abfd);
c7b8f16e
JB		 7647 localsyms = hdr->sh_info;
7648
7649 /* Obtain a buffer full of symbols for this BFD. The hdr->sh_info field
7650 should contain the number of local symbols, which should come before any
7651 global symbols. Mapping symbols are always local. */
7652 isymbuf = bfd_elf_get_elf_syms (abfd, hdr, localsyms, 0, NULL, NULL,
7653 NULL);
7654
7655 /* No internal symbols read? Skip this BFD. */
7656 if (isymbuf == NULL)
7657 return;
7658
7659 for (i = 0; i < localsyms; i++)
7660 {
7661 Elf_Internal_Sym *isym = &isymbuf[i];
7662 asection *sec = bfd_section_from_elf_index (abfd, isym->st_shndx);
7663 const char *name;
906e58ca 7664
c7b8f16e 7665 if (sec != NULL
99059e56
RM		 7666 && ELF_ST_BIND (isym->st_info) == STB_LOCAL)
7667 {
7668 name = bfd_elf_string_from_elf_section (abfd,
7669 hdr->sh_link, isym->st_name);
906e58ca 7670
99059e56 7671 if (bfd_is_arm_special_symbol_name (name,
c7b8f16e 7672 BFD_ARM_SPECIAL_SYM_TYPE_MAP))
99059e56
RM		 7673 elf32_arm_section_map_add (sec, name[1], isym->st_value);
7674 }
c7b8f16e
JB		 7675 }
7676}
7677
7678
48229727
JB		 7679/* Auto-select enabling of Cortex-A8 erratum fix if the user didn't explicitly
7680 say what they wanted. */
7681
7682void
7683bfd_elf32_arm_set_cortex_a8_fix (bfd *obfd, struct bfd_link_info *link_info)
7684{
7685 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (link_info);
7686 obj_attribute *out_attr = elf_known_obj_attributes_proc (obfd);
7687
4dfe6ac6
NC		 7688 if (globals == NULL)
7689 return;
7690
48229727
JB		 7691 if (globals->fix_cortex_a8 == -1)
7692 {
7693 /* Turn on Cortex-A8 erratum workaround for ARMv7-A. */
7694 if (out_attr[Tag_CPU_arch].i == TAG_CPU_ARCH_V7
7695 && (out_attr[Tag_CPU_arch_profile].i == 'A'
7696 || out_attr[Tag_CPU_arch_profile].i == 0))
7697 globals->fix_cortex_a8 = 1;
7698 else
7699 globals->fix_cortex_a8 = 0;
7700 }
7701}
7702
7703
c7b8f16e
JB		 7704void
7705bfd_elf32_arm_set_vfp11_fix (bfd *obfd, struct bfd_link_info *link_info)
7706{
7707 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (link_info);
104d59d1 7708 obj_attribute *out_attr = elf_known_obj_attributes_proc (obfd);
906e58ca 7709
4dfe6ac6
NC		 7710 if (globals == NULL)
7711 return;
c7b8f16e
JB		 7712 /* We assume that ARMv7+ does not need the VFP11 denorm erratum fix. */
7713 if (out_attr[Tag_CPU_arch].i >= TAG_CPU_ARCH_V7)
7714 {
7715 switch (globals->vfp11_fix)
99059e56
RM		 7716 {
7717 case BFD_ARM_VFP11_FIX_DEFAULT:
7718 case BFD_ARM_VFP11_FIX_NONE:
7719 globals->vfp11_fix = BFD_ARM_VFP11_FIX_NONE;
7720 break;
7721
7722 default:
7723 /* Give a warning, but do as the user requests anyway. */
7724 (*_bfd_error_handler) (_("%B: warning: selected VFP11 erratum "
7725 "workaround is not necessary for target architecture"), obfd);
7726 }
c7b8f16e
JB		 7727 }
7728 else if (globals->vfp11_fix == BFD_ARM_VFP11_FIX_DEFAULT)
7729 /* For earlier architectures, we might need the workaround, but do not
7730 enable it by default. If users is running with broken hardware, they
7731 must enable the erratum fix explicitly. */
7732 globals->vfp11_fix = BFD_ARM_VFP11_FIX_NONE;
7733}
7734
a504d23a
LA		 7735void
7736bfd_elf32_arm_set_stm32l4xx_fix (bfd *obfd, struct bfd_link_info *link_info)
7737{
7738 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (link_info);
7739 obj_attribute *out_attr = elf_known_obj_attributes_proc (obfd);
7740
7741 if (globals == NULL)
7742 return;
7743
7744 /* We assume only Cortex-M4 may require the fix. */
7745 if (out_attr[Tag_CPU_arch].i != TAG_CPU_ARCH_V7E_M
7746 || out_attr[Tag_CPU_arch_profile].i != 'M')
7747 {
7748 if (globals->stm32l4xx_fix != BFD_ARM_STM32L4XX_FIX_NONE)
7749 /* Give a warning, but do as the user requests anyway. */
7750 (*_bfd_error_handler)
7751 (_("%B: warning: selected STM32L4XX erratum "
7752 "workaround is not necessary for target architecture"), obfd);
7753 }
7754}
c7b8f16e 7755
906e58ca
NC		 7756enum bfd_arm_vfp11_pipe
7757{
c7b8f16e
JB		 7758 VFP11_FMAC,
7759 VFP11_LS,
7760 VFP11_DS,
7761 VFP11_BAD
7762};
7763
7764/* Return a VFP register number. This is encoded as RX:X for single-precision
7765 registers, or X:RX for double-precision registers, where RX is the group of
7766 four bits in the instruction encoding and X is the single extension bit.
7767 RX and X fields are specified using their lowest (starting) bit. The return
7768 value is:
7769
7770 0...31: single-precision registers s0...s31
7771 32...63: double-precision registers d0...d31.
906e58ca 7772
c7b8f16e
JB		 7773 Although X should be zero for VFP11 (encoding d0...d15 only), we might
7774 encounter VFP3 instructions, so we allow the full range for DP registers. */
906e58ca 7775
c7b8f16e
JB		 7776static unsigned int
7777bfd_arm_vfp11_regno (unsigned int insn, bfd_boolean is_double, unsigned int rx,
99059e56 7778 unsigned int x)
c7b8f16e
JB		 7779{
7780 if (is_double)
7781 return (((insn >> rx) & 0xf) | (((insn >> x) & 1) << 4)) + 32;
7782 else
7783 return (((insn >> rx) & 0xf) << 1) | ((insn >> x) & 1);
7784}
7785
7786/* Set bits in *WMASK according to a register number REG as encoded by
7787 bfd_arm_vfp11_regno(). Ignore d16-d31. */
7788
7789static void
7790bfd_arm_vfp11_write_mask (unsigned int *wmask, unsigned int reg)
7791{
7792 if (reg < 32)
7793 *wmask |= 1 << reg;
7794 else if (reg < 48)
7795 *wmask |= 3 << ((reg - 32) * 2);
7796}
7797
7798/* Return TRUE if WMASK overwrites anything in REGS. */
7799
7800static bfd_boolean
7801bfd_arm_vfp11_antidependency (unsigned int wmask, int *regs, int numregs)
7802{
7803 int i;
906e58ca 7804
c7b8f16e
JB		 7805 for (i = 0; i < numregs; i++)
7806 {
7807 unsigned int reg = regs[i];
7808
7809 if (reg < 32 && (wmask & (1 << reg)) != 0)
99059e56 7810 return TRUE;
906e58ca 7811
c7b8f16e
JB		 7812 reg -= 32;
7813
7814 if (reg >= 16)
99059e56 7815 continue;
906e58ca 7816
c7b8f16e 7817 if ((wmask & (3 << (reg * 2))) != 0)
99059e56 7818 return TRUE;
c7b8f16e 7819 }
906e58ca 7820
c7b8f16e
JB		 7821 return FALSE;
7822}
7823
7824/* In this function, we're interested in two things: finding input registers
7825 for VFP data-processing instructions, and finding the set of registers which
7826 arbitrary VFP instructions may write to. We use a 32-bit unsigned int to
7827 hold the written set, so FLDM etc. are easy to deal with (we're only
7828 interested in 32 SP registers or 16 dp registers, due to the VFP version
7829 implemented by the chip in question). DP registers are marked by setting
7830 both SP registers in the write mask). */
7831
7832static enum bfd_arm_vfp11_pipe
7833bfd_arm_vfp11_insn_decode (unsigned int insn, unsigned int *destmask, int *regs,
99059e56 7834 int *numregs)
c7b8f16e 7835{
91d6fa6a 7836 enum bfd_arm_vfp11_pipe vpipe = VFP11_BAD;
c7b8f16e
JB		 7837 bfd_boolean is_double = ((insn & 0xf00) == 0xb00) ? 1 : 0;
7838
7839 if ((insn & 0x0f000e10) == 0x0e000a00) /* A data-processing insn. */
7840 {
7841 unsigned int pqrs;
7842 unsigned int fd = bfd_arm_vfp11_regno (insn, is_double, 12, 22);
7843 unsigned int fm = bfd_arm_vfp11_regno (insn, is_double, 0, 5);
7844
7845 pqrs = ((insn & 0x00800000) >> 20)
99059e56
RM		 7846 | ((insn & 0x00300000) >> 19)
7847 | ((insn & 0x00000040) >> 6);
c7b8f16e
JB		 7848
7849 switch (pqrs)
99059e56
RM		 7850 {
7851 case 0: /* fmac[sd]. */
7852 case 1: /* fnmac[sd]. */
7853 case 2: /* fmsc[sd]. */
7854 case 3: /* fnmsc[sd]. */
7855 vpipe = VFP11_FMAC;
7856 bfd_arm_vfp11_write_mask (destmask, fd);
7857 regs[0] = fd;
7858 regs[1] = bfd_arm_vfp11_regno (insn, is_double, 16, 7); /* Fn. */
7859 regs[2] = fm;
7860 *numregs = 3;
7861 break;
7862
7863 case 4: /* fmul[sd]. */
7864 case 5: /* fnmul[sd]. */
7865 case 6: /* fadd[sd]. */
7866 case 7: /* fsub[sd]. */
7867 vpipe = VFP11_FMAC;
7868 goto vfp_binop;
7869
7870 case 8: /* fdiv[sd]. */
7871 vpipe = VFP11_DS;
7872 vfp_binop:
7873 bfd_arm_vfp11_write_mask (destmask, fd);
7874 regs[0] = bfd_arm_vfp11_regno (insn, is_double, 16, 7); /* Fn. */
7875 regs[1] = fm;
7876 *numregs = 2;
7877 break;
7878
7879 case 15: /* extended opcode. */
7880 {
7881 unsigned int extn = ((insn >> 15) & 0x1e)
7882 | ((insn >> 7) & 1);
7883
7884 switch (extn)
7885 {
7886 case 0: /* fcpy[sd]. */
7887 case 1: /* fabs[sd]. */
7888 case 2: /* fneg[sd]. */
7889 case 8: /* fcmp[sd]. */
7890 case 9: /* fcmpe[sd]. */
7891 case 10: /* fcmpz[sd]. */
7892 case 11: /* fcmpez[sd]. */
7893 case 16: /* fuito[sd]. */
7894 case 17: /* fsito[sd]. */
7895 case 24: /* ftoui[sd]. */
7896 case 25: /* ftouiz[sd]. */
7897 case 26: /* ftosi[sd]. */
7898 case 27: /* ftosiz[sd]. */
7899 /* These instructions will not bounce due to underflow. */
7900 *numregs = 0;
7901 vpipe = VFP11_FMAC;
7902 break;
7903
7904 case 3: /* fsqrt[sd]. */
7905 /* fsqrt cannot underflow, but it can (perhaps) overwrite
7906 registers to cause the erratum in previous instructions. */
7907 bfd_arm_vfp11_write_mask (destmask, fd);
7908 vpipe = VFP11_DS;
7909 break;
7910
7911 case 15: /* fcvt{ds,sd}. */
7912 {
7913 int rnum = 0;
7914
7915 bfd_arm_vfp11_write_mask (destmask, fd);
c7b8f16e
JB		 7916
7917 /* Only FCVTSD can underflow. */
99059e56
RM		 7918 if ((insn & 0x100) != 0)
7919 regs[rnum++] = fm;
c7b8f16e 7920
99059e56 7921 *numregs = rnum;
c7b8f16e 7922
99059e56
RM		 7923 vpipe = VFP11_FMAC;
7924 }
7925 break;
c7b8f16e 7926
99059e56
RM		 7927 default:
7928 return VFP11_BAD;
7929 }
7930 }
7931 break;
c7b8f16e 7932
99059e56
RM		 7933 default:
7934 return VFP11_BAD;
7935 }
c7b8f16e
JB		 7936 }
7937 /* Two-register transfer. */
7938 else if ((insn & 0x0fe00ed0) == 0x0c400a10)
7939 {
7940 unsigned int fm = bfd_arm_vfp11_regno (insn, is_double, 0, 5);
906e58ca 7941
c7b8f16e
JB		 7942 if ((insn & 0x100000) == 0)
7943 {
99059e56
RM		 7944 if (is_double)
7945 bfd_arm_vfp11_write_mask (destmask, fm);
7946 else
7947 {
7948 bfd_arm_vfp11_write_mask (destmask, fm);
7949 bfd_arm_vfp11_write_mask (destmask, fm + 1);
7950 }
c7b8f16e
JB		 7951 }
7952
91d6fa6a 7953 vpipe = VFP11_LS;
c7b8f16e
JB		 7954 }
7955 else if ((insn & 0x0e100e00) == 0x0c100a00) /* A load insn. */
7956 {
7957 int fd = bfd_arm_vfp11_regno (insn, is_double, 12, 22);
7958 unsigned int puw = ((insn >> 21) & 0x1) | (((insn >> 23) & 3) << 1);
906e58ca 7959
c7b8f16e 7960 switch (puw)
99059e56
RM		 7961 {
7962 case 0: /* Two-reg transfer. We should catch these above. */
7963 abort ();
906e58ca 7964
99059e56
RM		 7965 case 2: /* fldm[sdx]. */
7966 case 3:
7967 case 5:
7968 {
7969 unsigned int i, offset = insn & 0xff;
c7b8f16e 7970
99059e56
RM		 7971 if (is_double)
7972 offset >>= 1;
c7b8f16e 7973
99059e56
RM		 7974 for (i = fd; i < fd + offset; i++)
7975 bfd_arm_vfp11_write_mask (destmask, i);
7976 }
7977 break;
906e58ca 7978
99059e56
RM		 7979 case 4: /* fld[sd]. */
7980 case 6:
7981 bfd_arm_vfp11_write_mask (destmask, fd);
7982 break;
906e58ca 7983
99059e56
RM		 7984 default:
7985 return VFP11_BAD;
7986 }
c7b8f16e 7987
91d6fa6a 7988 vpipe = VFP11_LS;
c7b8f16e
JB		 7989 }
7990 /* Single-register transfer. Note L==0. */
7991 else if ((insn & 0x0f100e10) == 0x0e000a10)
7992 {
7993 unsigned int opcode = (insn >> 21) & 7;
7994 unsigned int fn = bfd_arm_vfp11_regno (insn, is_double, 16, 7);
7995
7996 switch (opcode)
99059e56
RM		 7997 {
7998 case 0: /* fmsr/fmdlr. */
7999 case 1: /* fmdhr. */
8000 /* Mark fmdhr and fmdlr as writing to the whole of the DP
8001 destination register. I don't know if this is exactly right,
8002 but it is the conservative choice. */
8003 bfd_arm_vfp11_write_mask (destmask, fn);
8004 break;
8005
8006 case 7: /* fmxr. */
8007 break;
8008 }
c7b8f16e 8009
91d6fa6a 8010 vpipe = VFP11_LS;
c7b8f16e
JB		 8011 }
8012
91d6fa6a 8013 return vpipe;
c7b8f16e
JB		 8014}
8015
8016
8017static int elf32_arm_compare_mapping (const void * a, const void * b);
8018
8019
8020/* Look for potentially-troublesome code sequences which might trigger the
8021 VFP11 denormal/antidependency erratum. See, e.g., the ARM1136 errata sheet
8022 (available from ARM) for details of the erratum. A short version is
8023 described in ld.texinfo. */
8024
8025bfd_boolean
8026bfd_elf32_arm_vfp11_erratum_scan (bfd *abfd, struct bfd_link_info *link_info)
8027{
8028 asection *sec;
8029 bfd_byte *contents = NULL;
8030 int state = 0;
8031 int regs[3], numregs = 0;
8032 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (link_info);
8033 int use_vector = (globals->vfp11_fix == BFD_ARM_VFP11_FIX_VECTOR);
906e58ca 8034
4dfe6ac6
NC		 8035 if (globals == NULL)
8036 return FALSE;
8037
c7b8f16e
JB		 8038 /* We use a simple FSM to match troublesome VFP11 instruction sequences.
8039 The states transition as follows:
906e58ca 8040
c7b8f16e 8041 0 -> 1 (vector) or 0 -> 2 (scalar)
99059e56
RM		 8042 A VFP FMAC-pipeline instruction has been seen. Fill
8043 regs[0]..regs[numregs-1] with its input operands. Remember this
8044 instruction in 'first_fmac'.
c7b8f16e
JB		 8045
8046 1 -> 2
99059e56
RM		 8047 Any instruction, except for a VFP instruction which overwrites
8048 regs[*].
906e58ca 8049
c7b8f16e
JB		 8050 1 -> 3 [ -> 0 ] or
8051 2 -> 3 [ -> 0 ]
99059e56
RM		 8052 A VFP instruction has been seen which overwrites any of regs[*].
8053 We must make a veneer! Reset state to 0 before examining next
8054 instruction.
906e58ca 8055
c7b8f16e 8056 2 -> 0
99059e56
RM		 8057 If we fail to match anything in state 2, reset to state 0 and reset
8058 the instruction pointer to the instruction after 'first_fmac'.
c7b8f16e
JB		 8059
8060 If the VFP11 vector mode is in use, there must be at least two unrelated
8061 instructions between anti-dependent VFP11 instructions to properly avoid
906e58ca 8062 triggering the erratum, hence the use of the extra state 1. */
c7b8f16e
JB		 8063
8064 /* If we are only performing a partial link do not bother
8065 to construct any glue. */
0e1862bb 8066 if (bfd_link_relocatable (link_info))
c7b8f16e
JB		 8067 return TRUE;
8068
0ffa91dd
NC		 8069 /* Skip if this bfd does not correspond to an ELF image. */
8070 if (! is_arm_elf (abfd))
8071 return TRUE;
906e58ca 8072
c7b8f16e
JB		 8073 /* We should have chosen a fix type by the time we get here. */
8074 BFD_ASSERT (globals->vfp11_fix != BFD_ARM_VFP11_FIX_DEFAULT);
8075
8076 if (globals->vfp11_fix == BFD_ARM_VFP11_FIX_NONE)
8077 return TRUE;
2e6030b9 8078
33a7ffc2
JM		 8079 /* Skip this BFD if it corresponds to an executable or dynamic object. */
8080 if ((abfd->flags & (EXEC_P | DYNAMIC)) != 0)
8081 return TRUE;
8082
c7b8f16e
JB		 8083 for (sec = abfd->sections; sec != NULL; sec = sec->next)
8084 {
8085 unsigned int i, span, first_fmac = 0, veneer_of_insn = 0;
8086 struct _arm_elf_section_data *sec_data;
8087
8088 /* If we don't have executable progbits, we're not interested in this
99059e56 8089 section. Also skip if section is to be excluded. */
c7b8f16e 8090 if (elf_section_type (sec) != SHT_PROGBITS
99059e56
RM		 8091 || (elf_section_flags (sec) & SHF_EXECINSTR) == 0
8092 || (sec->flags & SEC_EXCLUDE) != 0
dbaa2011 8093 || sec->sec_info_type == SEC_INFO_TYPE_JUST_SYMS
33a7ffc2 8094 || sec->output_section == bfd_abs_section_ptr
99059e56
RM		 8095 || strcmp (sec->name, VFP11_ERRATUM_VENEER_SECTION_NAME) == 0)
8096 continue;
c7b8f16e
JB		 8097
8098 sec_data = elf32_arm_section_data (sec);
906e58ca 8099
c7b8f16e 8100 if (sec_data->mapcount == 0)
99059e56 8101 continue;
906e58ca 8102
c7b8f16e
JB		 8103 if (elf_section_data (sec)->this_hdr.contents != NULL)
8104 contents = elf_section_data (sec)->this_hdr.contents;
8105 else if (! bfd_malloc_and_get_section (abfd, sec, &contents))
8106 goto error_return;
8107
8108 qsort (sec_data->map, sec_data->mapcount, sizeof (elf32_arm_section_map),
8109 elf32_arm_compare_mapping);
8110
8111 for (span = 0; span < sec_data->mapcount; span++)
99059e56
RM		 8112 {
8113 unsigned int span_start = sec_data->map[span].vma;
8114 unsigned int span_end = (span == sec_data->mapcount - 1)
c7b8f16e 8115 ? sec->size : sec_data->map[span + 1].vma;
99059e56
RM		 8116 char span_type = sec_data->map[span].type;
8117
8118 /* FIXME: Only ARM mode is supported at present. We may need to
8119 support Thumb-2 mode also at some point. */
8120 if (span_type != 'a')
8121 continue;
8122
8123 for (i = span_start; i < span_end;)
8124 {
8125 unsigned int next_i = i + 4;
8126 unsigned int insn = bfd_big_endian (abfd)
8127 ? (contents[i] << 24)
8128 | (contents[i + 1] << 16)
8129 | (contents[i + 2] << 8)
8130 | contents[i + 3]
8131 : (contents[i + 3] << 24)
8132 | (contents[i + 2] << 16)
8133 | (contents[i + 1] << 8)
8134 | contents[i];
8135 unsigned int writemask = 0;
8136 enum bfd_arm_vfp11_pipe vpipe;
8137
8138 switch (state)
8139 {
8140 case 0:
8141 vpipe = bfd_arm_vfp11_insn_decode (insn, &writemask, regs,
8142 &numregs);
8143 /* I'm assuming the VFP11 erratum can trigger with denorm
8144 operands on either the FMAC or the DS pipeline. This might
8145 lead to slightly overenthusiastic veneer insertion. */
8146 if (vpipe == VFP11_FMAC || vpipe == VFP11_DS)
8147 {
8148 state = use_vector ? 1 : 2;
8149 first_fmac = i;
8150 veneer_of_insn = insn;
8151 }
8152 break;
8153
8154 case 1:
8155 {
8156 int other_regs[3], other_numregs;
8157 vpipe = bfd_arm_vfp11_insn_decode (insn, &writemask,
c7b8f16e 8158 other_regs,
99059e56
RM		 8159 &other_numregs);
8160 if (vpipe != VFP11_BAD
8161 && bfd_arm_vfp11_antidependency (writemask, regs,
c7b8f16e 8162 numregs))
99059e56
RM		 8163 state = 3;
8164 else
8165 state = 2;
8166 }
8167 break;
8168
8169 case 2:
8170 {
8171 int other_regs[3], other_numregs;
8172 vpipe = bfd_arm_vfp11_insn_decode (insn, &writemask,
c7b8f16e 8173 other_regs,
99059e56
RM		 8174 &other_numregs);
8175 if (vpipe != VFP11_BAD
8176 && bfd_arm_vfp11_antidependency (writemask, regs,
c7b8f16e 8177 numregs))
99059e56
RM		 8178 state = 3;
8179 else
8180 {
8181 state = 0;
8182 next_i = first_fmac + 4;
8183 }
8184 }
8185 break;
8186
8187 case 3:
8188 abort (); /* Should be unreachable. */
8189 }
8190
8191 if (state == 3)
8192 {
8193 elf32_vfp11_erratum_list *newerr =(elf32_vfp11_erratum_list *)
8194 bfd_zmalloc (sizeof (elf32_vfp11_erratum_list));
8195
8196 elf32_arm_section_data (sec)->erratumcount += 1;
8197
8198 newerr->u.b.vfp_insn = veneer_of_insn;
8199
8200 switch (span_type)
8201 {
8202 case 'a':
8203 newerr->type = VFP11_ERRATUM_BRANCH_TO_ARM_VENEER;
8204 break;
8205
8206 default:
8207 abort ();
8208 }
8209
8210 record_vfp11_erratum_veneer (link_info, newerr, abfd, sec,
c7b8f16e
JB		 8211 first_fmac);
8212
99059e56 8213 newerr->vma = -1;
c7b8f16e 8214
99059e56
RM		 8215 newerr->next = sec_data->erratumlist;
8216 sec_data->erratumlist = newerr;
c7b8f16e 8217
99059e56
RM		 8218 state = 0;
8219 }
c7b8f16e 8220
99059e56
RM		 8221 i = next_i;
8222 }
8223 }
906e58ca 8224
c7b8f16e 8225 if (contents != NULL
99059e56
RM		 8226 && elf_section_data (sec)->this_hdr.contents != contents)
8227 free (contents);
c7b8f16e
JB		 8228 contents = NULL;
8229 }
8230
8231 return TRUE;
8232
8233error_return:
8234 if (contents != NULL
8235 && elf_section_data (sec)->this_hdr.contents != contents)
8236 free (contents);
906e58ca 8237
c7b8f16e
JB		 8238 return FALSE;
8239}
8240
8241/* Find virtual-memory addresses for VFP11 erratum veneers and return locations
8242 after sections have been laid out, using specially-named symbols. */
8243
8244void
8245bfd_elf32_arm_vfp11_fix_veneer_locations (bfd *abfd,
8246 struct bfd_link_info *link_info)
8247{
8248 asection *sec;
8249 struct elf32_arm_link_hash_table *globals;
8250 char *tmp_name;
906e58ca 8251
0e1862bb 8252 if (bfd_link_relocatable (link_info))
c7b8f16e 8253 return;
2e6030b9
MS		 8254
8255 /* Skip if this bfd does not correspond to an ELF image. */
0ffa91dd 8256 if (! is_arm_elf (abfd))
2e6030b9
MS		 8257 return;
8258
c7b8f16e 8259 globals = elf32_arm_hash_table (link_info);
4dfe6ac6
NC		 8260 if (globals == NULL)
8261 return;
906e58ca 8262
21d799b5 8263 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen
99059e56 8264 (VFP11_ERRATUM_VENEER_ENTRY_NAME) + 10);
c7b8f16e
JB		 8265
8266 for (sec = abfd->sections; sec != NULL; sec = sec->next)
8267 {
8268 struct _arm_elf_section_data *sec_data = elf32_arm_section_data (sec);
8269 elf32_vfp11_erratum_list *errnode = sec_data->erratumlist;
906e58ca 8270
c7b8f16e 8271 for (; errnode != NULL; errnode = errnode->next)
99059e56
RM		 8272 {
8273 struct elf_link_hash_entry *myh;
8274 bfd_vma vma;
8275
8276 switch (errnode->type)
8277 {
8278 case VFP11_ERRATUM_BRANCH_TO_ARM_VENEER:
8279 case VFP11_ERRATUM_BRANCH_TO_THUMB_VENEER:
8280 /* Find veneer symbol. */
8281 sprintf (tmp_name, VFP11_ERRATUM_VENEER_ENTRY_NAME,
c7b8f16e
JB		 8282 errnode->u.b.veneer->u.v.id);
8283
99059e56
RM		 8284 myh = elf_link_hash_lookup
8285 (&(globals)->root, tmp_name, FALSE, FALSE, TRUE);
c7b8f16e 8286
a504d23a
LA		 8287 if (myh == NULL)
8288 (*_bfd_error_handler) (_("%B: unable to find VFP11 veneer "
8289 "`%s'"), abfd, tmp_name);
8290
8291 vma = myh->root.u.def.section->output_section->vma
8292 + myh->root.u.def.section->output_offset
8293 + myh->root.u.def.value;
8294
8295 errnode->u.b.veneer->vma = vma;
8296 break;
8297
8298 case VFP11_ERRATUM_ARM_VENEER:
8299 case VFP11_ERRATUM_THUMB_VENEER:
8300 /* Find return location. */
8301 sprintf (tmp_name, VFP11_ERRATUM_VENEER_ENTRY_NAME "_r",
8302 errnode->u.v.id);
8303
8304 myh = elf_link_hash_lookup
8305 (&(globals)->root, tmp_name, FALSE, FALSE, TRUE);
8306
8307 if (myh == NULL)
8308 (*_bfd_error_handler) (_("%B: unable to find VFP11 veneer "
8309 "`%s'"), abfd, tmp_name);
8310
8311 vma = myh->root.u.def.section->output_section->vma
8312 + myh->root.u.def.section->output_offset
8313 + myh->root.u.def.value;
8314
8315 errnode->u.v.branch->vma = vma;
8316 break;
8317
8318 default:
8319 abort ();
8320 }
8321 }
8322 }
8323
8324 free (tmp_name);
8325}
8326
8327/* Find virtual-memory addresses for STM32L4XX erratum veneers and
8328 return locations after sections have been laid out, using
8329 specially-named symbols. */
8330
8331void
8332bfd_elf32_arm_stm32l4xx_fix_veneer_locations (bfd *abfd,
8333 struct bfd_link_info *link_info)
8334{
8335 asection *sec;
8336 struct elf32_arm_link_hash_table *globals;
8337 char *tmp_name;
8338
8339 if (bfd_link_relocatable (link_info))
8340 return;
8341
8342 /* Skip if this bfd does not correspond to an ELF image. */
8343 if (! is_arm_elf (abfd))
8344 return;
8345
8346 globals = elf32_arm_hash_table (link_info);
8347 if (globals == NULL)
8348 return;
8349
8350 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen
8351 (STM32L4XX_ERRATUM_VENEER_ENTRY_NAME) + 10);
8352
8353 for (sec = abfd->sections; sec != NULL; sec = sec->next)
8354 {
8355 struct _arm_elf_section_data *sec_data = elf32_arm_section_data (sec);
8356 elf32_stm32l4xx_erratum_list *errnode = sec_data->stm32l4xx_erratumlist;
8357
8358 for (; errnode != NULL; errnode = errnode->next)
8359 {
8360 struct elf_link_hash_entry *myh;
8361 bfd_vma vma;
8362
8363 switch (errnode->type)
8364 {
8365 case STM32L4XX_ERRATUM_BRANCH_TO_VENEER:
8366 /* Find veneer symbol. */
8367 sprintf (tmp_name, STM32L4XX_ERRATUM_VENEER_ENTRY_NAME,
8368 errnode->u.b.veneer->u.v.id);
8369
8370 myh = elf_link_hash_lookup
8371 (&(globals)->root, tmp_name, FALSE, FALSE, TRUE);
8372
8373 if (myh == NULL)
8374 (*_bfd_error_handler) (_("%B: unable to find STM32L4XX veneer "
8375 "`%s'"), abfd, tmp_name);
8376
8377 vma = myh->root.u.def.section->output_section->vma
8378 + myh->root.u.def.section->output_offset
8379 + myh->root.u.def.value;
8380
8381 errnode->u.b.veneer->vma = vma;
8382 break;
8383
8384 case STM32L4XX_ERRATUM_VENEER:
8385 /* Find return location. */
8386 sprintf (tmp_name, STM32L4XX_ERRATUM_VENEER_ENTRY_NAME "_r",
8387 errnode->u.v.id);
8388
8389 myh = elf_link_hash_lookup
8390 (&(globals)->root, tmp_name, FALSE, FALSE, TRUE);
8391
8392 if (myh == NULL)
8393 (*_bfd_error_handler) (_("%B: unable to find STM32L4XX veneer "
8394 "`%s'"), abfd, tmp_name);
8395
8396 vma = myh->root.u.def.section->output_section->vma
8397 + myh->root.u.def.section->output_offset
8398 + myh->root.u.def.value;
8399
8400 errnode->u.v.branch->vma = vma;
8401 break;
8402
8403 default:
8404 abort ();
8405 }
8406 }
8407 }
8408
8409 free (tmp_name);
8410}
8411
8412static inline bfd_boolean
8413is_thumb2_ldmia (const insn32 insn)
8414{
8415 /* Encoding T2: LDM<c>.W <Rn>{!},<registers>
8416 1110 - 1000 - 10W1 - rrrr - PM (0) l - llll - llll - llll. */
8417 return (insn & 0xffd02000) == 0xe8900000;
8418}
8419
8420static inline bfd_boolean
8421is_thumb2_ldmdb (const insn32 insn)
8422{
8423 /* Encoding T1: LDMDB<c> <Rn>{!},<registers>
8424 1110 - 1001 - 00W1 - rrrr - PM (0) l - llll - llll - llll. */
8425 return (insn & 0xffd02000) == 0xe9100000;
8426}
8427
8428static inline bfd_boolean
8429is_thumb2_vldm (const insn32 insn)
8430{
8431 /* A6.5 Extension register load or store instruction
8432 A7.7.229
9239bbd3
CM		 8433 We look for SP 32-bit and DP 64-bit registers.
8434 Encoding T1 VLDM{mode}<c> <Rn>{!}, <list>
8435 <list> is consecutive 64-bit registers
8436 1110 - 110P - UDW1 - rrrr - vvvv - 1011 - iiii - iiii
a504d23a
LA		 8437 Encoding T2 VLDM{mode}<c> <Rn>{!}, <list>
8438 <list> is consecutive 32-bit registers
8439 1110 - 110P - UDW1 - rrrr - vvvv - 1010 - iiii - iiii
8440 if P==0 && U==1 && W==1 && Rn=1101 VPOP
8441 if PUW=010 || PUW=011 || PUW=101 VLDM. */
8442 return
9239bbd3
CM		 8443 (((insn & 0xfe100f00) == 0xec100b00) ||
8444 ((insn & 0xfe100f00) == 0xec100a00))
a504d23a
LA		 8445 && /* (IA without !). */
8446 (((((insn << 7) >> 28) & 0xd) == 0x4)
9239bbd3 8447 /* (IA with !), includes VPOP (when reg number is SP). */
a504d23a
LA		 8448 || ((((insn << 7) >> 28) & 0xd) == 0x5)
8449 /* (DB with !). */
8450 || ((((insn << 7) >> 28) & 0xd) == 0x9));
8451}
8452
8453/* STM STM32L4XX erratum : This function assumes that it receives an LDM or
8454 VLDM opcode and:
8455 - computes the number and the mode of memory accesses
8456 - decides if the replacement should be done:
8457 . replaces only if > 8-word accesses
8458 . or (testing purposes only) replaces all accesses. */
8459
8460static bfd_boolean
8461stm32l4xx_need_create_replacing_stub (const insn32 insn,
8462 bfd_arm_stm32l4xx_fix stm32l4xx_fix)
8463{
9239bbd3 8464 int nb_words = 0;
a504d23a
LA		 8465
8466 /* The field encoding the register list is the same for both LDMIA
8467 and LDMDB encodings. */
8468 if (is_thumb2_ldmia (insn) || is_thumb2_ldmdb (insn))
9239bbd3 8469 nb_words = popcount (insn & 0x0000ffff);
a504d23a 8470 else if (is_thumb2_vldm (insn))
9239bbd3 8471 nb_words = (insn & 0xff);
a504d23a
LA		 8472
8473 /* DEFAULT mode accounts for the real bug condition situation,
8474 ALL mode inserts stubs for each LDM/VLDM instruction (testing). */
8475 return
9239bbd3 8476 (stm32l4xx_fix == BFD_ARM_STM32L4XX_FIX_DEFAULT) ? nb_words > 8 :
a504d23a
LA		 8477 (stm32l4xx_fix == BFD_ARM_STM32L4XX_FIX_ALL) ? TRUE : FALSE;
8478}
8479
8480/* Look for potentially-troublesome code sequences which might trigger
8481 the STM STM32L4XX erratum. */
8482
8483bfd_boolean
8484bfd_elf32_arm_stm32l4xx_erratum_scan (bfd *abfd,
8485 struct bfd_link_info *link_info)
8486{
8487 asection *sec;
8488 bfd_byte *contents = NULL;
8489 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (link_info);
8490
8491 if (globals == NULL)
8492 return FALSE;
8493
8494 /* If we are only performing a partial link do not bother
8495 to construct any glue. */
8496 if (bfd_link_relocatable (link_info))
8497 return TRUE;
8498
8499 /* Skip if this bfd does not correspond to an ELF image. */
8500 if (! is_arm_elf (abfd))
8501 return TRUE;
8502
8503 if (globals->stm32l4xx_fix == BFD_ARM_STM32L4XX_FIX_NONE)
8504 return TRUE;
8505
8506 /* Skip this BFD if it corresponds to an executable or dynamic object. */
8507 if ((abfd->flags & (EXEC_P | DYNAMIC)) != 0)
8508 return TRUE;
8509
8510 for (sec = abfd->sections; sec != NULL; sec = sec->next)
8511 {
8512 unsigned int i, span;
8513 struct _arm_elf_section_data *sec_data;
8514
8515 /* If we don't have executable progbits, we're not interested in this
8516 section. Also skip if section is to be excluded. */
8517 if (elf_section_type (sec) != SHT_PROGBITS
8518 || (elf_section_flags (sec) & SHF_EXECINSTR) == 0
8519 || (sec->flags & SEC_EXCLUDE) != 0
8520 || sec->sec_info_type == SEC_INFO_TYPE_JUST_SYMS
8521 || sec->output_section == bfd_abs_section_ptr
8522 || strcmp (sec->name, STM32L4XX_ERRATUM_VENEER_SECTION_NAME) == 0)
8523 continue;
8524
8525 sec_data = elf32_arm_section_data (sec);
c7b8f16e 8526
a504d23a
LA		 8527 if (sec_data->mapcount == 0)
8528 continue;
c7b8f16e 8529
a504d23a
LA		 8530 if (elf_section_data (sec)->this_hdr.contents != NULL)
8531 contents = elf_section_data (sec)->this_hdr.contents;
8532 else if (! bfd_malloc_and_get_section (abfd, sec, &contents))
8533 goto error_return;
c7b8f16e 8534
a504d23a
LA		 8535 qsort (sec_data->map, sec_data->mapcount, sizeof (elf32_arm_section_map),
8536 elf32_arm_compare_mapping);
c7b8f16e 8537
a504d23a
LA		 8538 for (span = 0; span < sec_data->mapcount; span++)
8539 {
8540 unsigned int span_start = sec_data->map[span].vma;
8541 unsigned int span_end = (span == sec_data->mapcount - 1)
8542 ? sec->size : sec_data->map[span + 1].vma;
8543 char span_type = sec_data->map[span].type;
8544 int itblock_current_pos = 0;
c7b8f16e 8545
a504d23a
LA		 8546 /* Only Thumb2 mode need be supported with this CM4 specific
8547 code, we should not encounter any arm mode eg span_type
8548 != 'a'. */
8549 if (span_type != 't')
8550 continue;
c7b8f16e 8551
a504d23a
LA		 8552 for (i = span_start; i < span_end;)
8553 {
8554 unsigned int insn = bfd_get_16 (abfd, &contents[i]);
8555 bfd_boolean insn_32bit = FALSE;
8556 bfd_boolean is_ldm = FALSE;
8557 bfd_boolean is_vldm = FALSE;
8558 bfd_boolean is_not_last_in_it_block = FALSE;
8559
8560 /* The first 16-bits of all 32-bit thumb2 instructions start
8561 with opcode[15..13]=0b111 and the encoded op1 can be anything
8562 except opcode[12..11]!=0b00.
8563 See 32-bit Thumb instruction encoding. */
8564 if ((insn & 0xe000) == 0xe000 && (insn & 0x1800) != 0x0000)
8565 insn_32bit = TRUE;
c7b8f16e 8566
a504d23a
LA		 8567 /* Compute the predicate that tells if the instruction
8568 is concerned by the IT block
8569 - Creates an error if there is a ldm that is not
8570 last in the IT block thus cannot be replaced
8571 - Otherwise we can create a branch at the end of the
8572 IT block, it will be controlled naturally by IT
8573 with the proper pseudo-predicate
8574 - So the only interesting predicate is the one that
8575 tells that we are not on the last item of an IT
8576 block. */
8577 if (itblock_current_pos != 0)
8578 is_not_last_in_it_block = !!--itblock_current_pos;
906e58ca 8579
a504d23a
LA		 8580 if (insn_32bit)
8581 {
8582 /* Load the rest of the insn (in manual-friendly order). */
8583 insn = (insn << 16) | bfd_get_16 (abfd, &contents[i + 2]);
8584 is_ldm = is_thumb2_ldmia (insn) || is_thumb2_ldmdb (insn);
8585 is_vldm = is_thumb2_vldm (insn);
8586
8587 /* Veneers are created for (v)ldm depending on
8588 option flags and memory accesses conditions; but
8589 if the instruction is not the last instruction of
8590 an IT block, we cannot create a jump there, so we
8591 bail out. */
8592 if ((is_ldm || is_vldm) &&
8593 stm32l4xx_need_create_replacing_stub
8594 (insn, globals->stm32l4xx_fix))
8595 {
8596 if (is_not_last_in_it_block)
8597 {
8598 (*_bfd_error_handler)
8599 /* Note - overlong line used here to allow for translation. */
8600 (_("\
8601%B(%A+0x%lx): error: multiple load detected in non-last IT block instruction : STM32L4XX veneer cannot be generated.\n"
8602 "Use gcc option -mrestrict-it to generate only one instruction per IT block.\n"),
8603 abfd, sec, (long)i);
8604 }
8605 else
8606 {
8607 elf32_stm32l4xx_erratum_list *newerr =
8608 (elf32_stm32l4xx_erratum_list *)
8609 bfd_zmalloc
8610 (sizeof (elf32_stm32l4xx_erratum_list));
8611
8612 elf32_arm_section_data (sec)
8613 ->stm32l4xx_erratumcount += 1;
8614 newerr->u.b.insn = insn;
8615 /* We create only thumb branches. */
8616 newerr->type =
8617 STM32L4XX_ERRATUM_BRANCH_TO_VENEER;
8618 record_stm32l4xx_erratum_veneer
8619 (link_info, newerr, abfd, sec,
8620 i,
8621 is_ldm ?
8622 STM32L4XX_ERRATUM_LDM_VENEER_SIZE:
8623 STM32L4XX_ERRATUM_VLDM_VENEER_SIZE);
8624 newerr->vma = -1;
8625 newerr->next = sec_data->stm32l4xx_erratumlist;
8626 sec_data->stm32l4xx_erratumlist = newerr;
8627 }
8628 }
8629 }
8630 else
8631 {
8632 /* A7.7.37 IT p208
8633 IT blocks are only encoded in T1
8634 Encoding T1: IT{x{y{z}}} <firstcond>
8635 1 0 1 1 - 1 1 1 1 - firstcond - mask
8636 if mask = '0000' then see 'related encodings'
8637 We don't deal with UNPREDICTABLE, just ignore these.
8638 There can be no nested IT blocks so an IT block
8639 is naturally a new one for which it is worth
8640 computing its size. */
8641 bfd_boolean is_newitblock = ((insn & 0xff00) == 0xbf00) &&
8642 ((insn & 0x000f) != 0x0000);
8643 /* If we have a new IT block we compute its size. */
8644 if (is_newitblock)
8645 {
8646 /* Compute the number of instructions controlled
8647 by the IT block, it will be used to decide
8648 whether we are inside an IT block or not. */
8649 unsigned int mask = insn & 0x000f;
8650 itblock_current_pos = 4 - ctz (mask);
8651 }
8652 }
8653
8654 i += insn_32bit ? 4 : 2;
99059e56
RM		 8655 }
8656 }
a504d23a
LA		 8657
8658 if (contents != NULL
8659 && elf_section_data (sec)->this_hdr.contents != contents)
8660 free (contents);
8661 contents = NULL;
c7b8f16e 8662 }
906e58ca 8663
a504d23a
LA		 8664 return TRUE;
8665
8666error_return:
8667 if (contents != NULL
8668 && elf_section_data (sec)->this_hdr.contents != contents)
8669 free (contents);
c7b8f16e 8670
a504d23a
LA		 8671 return FALSE;
8672}
c7b8f16e 8673
eb043451
PB		 8674/* Set target relocation values needed during linking. */
8675
8676void
68c39892 8677bfd_elf32_arm_set_target_params (struct bfd *output_bfd,
bf21ed78 8678 struct bfd_link_info *link_info,
68c39892 8679 struct elf32_arm_params *params)
eb043451
PB		 8680{
8681 struct elf32_arm_link_hash_table *globals;
8682
8683 globals = elf32_arm_hash_table (link_info);
4dfe6ac6
NC		 8684 if (globals == NULL)
8685 return;
eb043451 8686
68c39892
TP		 8687 globals->target1_is_rel = params->target1_is_rel;
8688 if (strcmp (params->target2_type, "rel") == 0)
eb043451 8689 globals->target2_reloc = R_ARM_REL32;
68c39892 8690 else if (strcmp (params->target2_type, "abs") == 0)
eeac373a 8691 globals->target2_reloc = R_ARM_ABS32;
68c39892 8692 else if (strcmp (params->target2_type, "got-rel") == 0)
eb043451
PB		 8693 globals->target2_reloc = R_ARM_GOT_PREL;
8694 else
8695 {
8696 _bfd_error_handler (_("Invalid TARGET2 relocation type '%s'."),
68c39892 8697 params->target2_type);
eb043451 8698 }
68c39892
TP		 8699 globals->fix_v4bx = params->fix_v4bx;
8700 globals->use_blx |= params->use_blx;
8701 globals->vfp11_fix = params->vfp11_denorm_fix;
8702 globals->stm32l4xx_fix = params->stm32l4xx_fix;
8703 globals->pic_veneer = params->pic_veneer;
8704 globals->fix_cortex_a8 = params->fix_cortex_a8;
8705 globals->fix_arm1176 = params->fix_arm1176;
8706 globals->cmse_implib = params->cmse_implib;
8707 globals->in_implib_bfd = params->in_implib_bfd;
bf21ed78 8708
0ffa91dd 8709 BFD_ASSERT (is_arm_elf (output_bfd));
68c39892
TP		 8710 elf_arm_tdata (output_bfd)->no_enum_size_warning
8711 = params->no_enum_size_warning;
8712 elf_arm_tdata (output_bfd)->no_wchar_size_warning
8713 = params->no_wchar_size_warning;
eb043451 8714}
eb043451 8715
12a0a0fd 8716/* Replace the target offset of a Thumb bl or b.w instruction. */
252b5132 8717
12a0a0fd
PB		 8718static void
8719insert_thumb_branch (bfd *abfd, long int offset, bfd_byte *insn)
8720{
8721 bfd_vma upper;
8722 bfd_vma lower;
8723 int reloc_sign;
8724
8725 BFD_ASSERT ((offset & 1) == 0);
8726
8727 upper = bfd_get_16 (abfd, insn);
8728 lower = bfd_get_16 (abfd, insn + 2);
8729 reloc_sign = (offset < 0) ? 1 : 0;
8730 upper = (upper & ~(bfd_vma) 0x7ff)
8731 | ((offset >> 12) & 0x3ff)
8732 | (reloc_sign << 10);
906e58ca 8733 lower = (lower & ~(bfd_vma) 0x2fff)
12a0a0fd
PB		 8734 | (((!((offset >> 23) & 1)) ^ reloc_sign) << 13)
8735 | (((!((offset >> 22) & 1)) ^ reloc_sign) << 11)
8736 | ((offset >> 1) & 0x7ff);
8737 bfd_put_16 (abfd, upper, insn);
8738 bfd_put_16 (abfd, lower, insn + 2);
252b5132
RH		 8739}
8740
9b485d32
NC		 8741/* Thumb code calling an ARM function. */
8742
252b5132 8743static int
57e8b36a
NC		 8744elf32_thumb_to_arm_stub (struct bfd_link_info * info,
8745 const char * name,
8746 bfd * input_bfd,
8747 bfd * output_bfd,
8748 asection * input_section,
8749 bfd_byte * hit_data,
8750 asection * sym_sec,
8751 bfd_vma offset,
8752 bfd_signed_vma addend,
f2a9dd69
DJ		 8753 bfd_vma val,
8754 char **error_message)
252b5132 8755{
bcbdc74c 8756 asection * s = 0;
dc810e39 8757 bfd_vma my_offset;
252b5132 8758 long int ret_offset;
bcbdc74c
NC		 8759 struct elf_link_hash_entry * myh;
8760 struct elf32_arm_link_hash_table * globals;
252b5132 8761
f2a9dd69 8762 myh = find_thumb_glue (info, name, error_message);
252b5132 8763 if (myh == NULL)
b34976b6 8764 return FALSE;
252b5132
RH		 8765
8766 globals = elf32_arm_hash_table (info);
252b5132
RH		 8767 BFD_ASSERT (globals != NULL);
8768 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
8769
8770 my_offset = myh->root.u.def.value;
8771
3d4d4302
AM		 8772 s = bfd_get_linker_section (globals->bfd_of_glue_owner,
8773 THUMB2ARM_GLUE_SECTION_NAME);
252b5132
RH		 8774
8775 BFD_ASSERT (s != NULL);
8776 BFD_ASSERT (s->contents != NULL);
8777 BFD_ASSERT (s->output_section != NULL);
8778
8779 if ((my_offset & 0x01) == 0x01)
8780 {
8781 if (sym_sec != NULL
8782 && sym_sec->owner != NULL
8783 && !INTERWORK_FLAG (sym_sec->owner))
8784 {
8f615d07 8785 (*_bfd_error_handler)
d003868e 8786 (_("%B(%s): warning: interworking not enabled.\n"
3aaeb7d3 8787 " first occurrence: %B: Thumb call to ARM"),
d003868e 8788 sym_sec->owner, input_bfd, name);
252b5132 8789
b34976b6 8790 return FALSE;
252b5132
RH		 8791 }
8792
8793 --my_offset;
8794 myh->root.u.def.value = my_offset;
8795
52ab56c2
PB		 8796 put_thumb_insn (globals, output_bfd, (bfd_vma) t2a1_bx_pc_insn,
8797 s->contents + my_offset);
252b5132 8798
52ab56c2
PB		 8799 put_thumb_insn (globals, output_bfd, (bfd_vma) t2a2_noop_insn,
8800 s->contents + my_offset + 2);
252b5132
RH		 8801
8802 ret_offset =
9b485d32
NC		 8803 /* Address of destination of the stub. */
8804 ((bfd_signed_vma) val)
252b5132 8805 - ((bfd_signed_vma)
57e8b36a
NC		 8806 /* Offset from the start of the current section
8807 to the start of the stubs. */
9b485d32
NC		 8808 (s->output_offset
8809 /* Offset of the start of this stub from the start of the stubs. */
8810 + my_offset
8811 /* Address of the start of the current section. */
8812 + s->output_section->vma)
8813 /* The branch instruction is 4 bytes into the stub. */
8814 + 4
8815 /* ARM branches work from the pc of the instruction + 8. */
8816 + 8);
252b5132 8817
52ab56c2
PB		 8818 put_arm_insn (globals, output_bfd,
8819 (bfd_vma) t2a3_b_insn | ((ret_offset >> 2) & 0x00FFFFFF),
8820 s->contents + my_offset + 4);
252b5132
RH		 8821 }
8822
8823 BFD_ASSERT (my_offset <= globals->thumb_glue_size);
8824
427bfd90
NC		 8825 /* Now go back and fix up the original BL insn to point to here. */
8826 ret_offset =
8827 /* Address of where the stub is located. */
8828 (s->output_section->vma + s->output_offset + my_offset)
8829 /* Address of where the BL is located. */
57e8b36a
NC		 8830 - (input_section->output_section->vma + input_section->output_offset
8831 + offset)
427bfd90
NC		 8832 /* Addend in the relocation. */
8833 - addend
8834 /* Biassing for PC-relative addressing. */
8835 - 8;
252b5132 8836
12a0a0fd 8837 insert_thumb_branch (input_bfd, ret_offset, hit_data - input_section->vma);
252b5132 8838
b34976b6 8839 return TRUE;
252b5132
RH		 8840}
8841
a4fd1a8e 8842/* Populate an Arm to Thumb stub. Returns the stub symbol. */
9b485d32 8843
a4fd1a8e
PB		 8844static struct elf_link_hash_entry *
8845elf32_arm_create_thumb_stub (struct bfd_link_info * info,
8846 const char * name,
8847 bfd * input_bfd,
8848 bfd * output_bfd,
8849 asection * sym_sec,
8850 bfd_vma val,
8029a119
NC		 8851 asection * s,
8852 char ** error_message)
252b5132 8853{
dc810e39 8854 bfd_vma my_offset;
252b5132 8855 long int ret_offset;
bcbdc74c
NC		 8856 struct elf_link_hash_entry * myh;
8857 struct elf32_arm_link_hash_table * globals;
252b5132 8858
f2a9dd69 8859 myh = find_arm_glue (info, name, error_message);
252b5132 8860 if (myh == NULL)
a4fd1a8e 8861 return NULL;
252b5132
RH		 8862
8863 globals = elf32_arm_hash_table (info);
252b5132
RH		 8864 BFD_ASSERT (globals != NULL);
8865 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
8866
8867 my_offset = myh->root.u.def.value;
252b5132
RH		 8868
8869 if ((my_offset & 0x01) == 0x01)
8870 {
8871 if (sym_sec != NULL
8872 && sym_sec->owner != NULL
8873 && !INTERWORK_FLAG (sym_sec->owner))
8874 {
8f615d07 8875 (*_bfd_error_handler)
d003868e
AM		 8876 (_("%B(%s): warning: interworking not enabled.\n"
8877 " first occurrence: %B: arm call to thumb"),
8878 sym_sec->owner, input_bfd, name);
252b5132 8879 }
9b485d32 8880
252b5132
RH		 8881 --my_offset;
8882 myh->root.u.def.value = my_offset;
8883
0e1862bb
L		 8884 if (bfd_link_pic (info)
8885 || globals->root.is_relocatable_executable
27e55c4d 8886 || globals->pic_veneer)
8f6277f5
PB		 8887 {
8888 /* For relocatable objects we can't use absolute addresses,
8889 so construct the address from a relative offset. */
8890 /* TODO: If the offset is small it's probably worth
8891 constructing the address with adds. */
52ab56c2
PB		 8892 put_arm_insn (globals, output_bfd, (bfd_vma) a2t1p_ldr_insn,
8893 s->contents + my_offset);
8894 put_arm_insn (globals, output_bfd, (bfd_vma) a2t2p_add_pc_insn,
8895 s->contents + my_offset + 4);
8896 put_arm_insn (globals, output_bfd, (bfd_vma) a2t3p_bx_r12_insn,
8897 s->contents + my_offset + 8);
8f6277f5
PB		 8898 /* Adjust the offset by 4 for the position of the add,
8899 and 8 for the pipeline offset. */
8900 ret_offset = (val - (s->output_offset
8901 + s->output_section->vma
8902 + my_offset + 12))
8903 | 1;
8904 bfd_put_32 (output_bfd, ret_offset,
8905 s->contents + my_offset + 12);
8906 }
26079076
PB		 8907 else if (globals->use_blx)
8908 {
8909 put_arm_insn (globals, output_bfd, (bfd_vma) a2t1v5_ldr_insn,
8910 s->contents + my_offset);
8911
8912 /* It's a thumb address. Add the low order bit. */
8913 bfd_put_32 (output_bfd, val | a2t2v5_func_addr_insn,
8914 s->contents + my_offset + 4);
8915 }
8f6277f5
PB		 8916 else
8917 {
52ab56c2
PB		 8918 put_arm_insn (globals, output_bfd, (bfd_vma) a2t1_ldr_insn,
8919 s->contents + my_offset);
252b5132 8920
52ab56c2
PB		 8921 put_arm_insn (globals, output_bfd, (bfd_vma) a2t2_bx_r12_insn,
8922 s->contents + my_offset + 4);
252b5132 8923
8f6277f5
PB		 8924 /* It's a thumb address. Add the low order bit. */
8925 bfd_put_32 (output_bfd, val | a2t3_func_addr_insn,
8926 s->contents + my_offset + 8);
8029a119
NC		 8927
8928 my_offset += 12;
8f6277f5 8929 }
252b5132
RH		 8930 }
8931
8932 BFD_ASSERT (my_offset <= globals->arm_glue_size);
8933
a4fd1a8e
PB		 8934 return myh;
8935}
8936
8937/* Arm code calling a Thumb function. */
8938
8939static int
8940elf32_arm_to_thumb_stub (struct bfd_link_info * info,
8941 const char * name,
8942 bfd * input_bfd,
8943 bfd * output_bfd,
8944 asection * input_section,
8945 bfd_byte * hit_data,
8946 asection * sym_sec,
8947 bfd_vma offset,
8948 bfd_signed_vma addend,
f2a9dd69
DJ		 8949 bfd_vma val,
8950 char **error_message)
a4fd1a8e
PB		 8951{
8952 unsigned long int tmp;
8953 bfd_vma my_offset;
8954 asection * s;
8955 long int ret_offset;
8956 struct elf_link_hash_entry * myh;
8957 struct elf32_arm_link_hash_table * globals;
8958
8959 globals = elf32_arm_hash_table (info);
a4fd1a8e
PB		 8960 BFD_ASSERT (globals != NULL);
8961 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
8962
3d4d4302
AM		 8963 s = bfd_get_linker_section (globals->bfd_of_glue_owner,
8964 ARM2THUMB_GLUE_SECTION_NAME);
a4fd1a8e
PB		 8965 BFD_ASSERT (s != NULL);
8966 BFD_ASSERT (s->contents != NULL);
8967 BFD_ASSERT (s->output_section != NULL);
8968
8969 myh = elf32_arm_create_thumb_stub (info, name, input_bfd, output_bfd,
f2a9dd69 8970 sym_sec, val, s, error_message);
a4fd1a8e
PB		 8971 if (!myh)
8972 return FALSE;
8973
8974 my_offset = myh->root.u.def.value;
252b5132
RH		 8975 tmp = bfd_get_32 (input_bfd, hit_data);
8976 tmp = tmp & 0xFF000000;
8977
9b485d32 8978 /* Somehow these are both 4 too far, so subtract 8. */
dc810e39
AM		 8979 ret_offset = (s->output_offset
8980 + my_offset
8981 + s->output_section->vma
8982 - (input_section->output_offset
8983 + input_section->output_section->vma
8984 + offset + addend)
8985 - 8);
9a5aca8c 8986
252b5132
RH		 8987 tmp = tmp | ((ret_offset >> 2) & 0x00FFFFFF);
8988
dc810e39 8989 bfd_put_32 (output_bfd, (bfd_vma) tmp, hit_data - input_section->vma);
252b5132 8990
b34976b6 8991 return TRUE;
252b5132
RH		 8992}
8993
a4fd1a8e
PB		 8994/* Populate Arm stub for an exported Thumb function. */
8995
8996static bfd_boolean
8997elf32_arm_to_thumb_export_stub (struct elf_link_hash_entry *h, void * inf)
8998{
8999 struct bfd_link_info * info = (struct bfd_link_info *) inf;
9000 asection * s;
9001 struct elf_link_hash_entry * myh;
9002 struct elf32_arm_link_hash_entry *eh;
9003 struct elf32_arm_link_hash_table * globals;
9004 asection *sec;
9005 bfd_vma val;
f2a9dd69 9006 char *error_message;
a4fd1a8e 9007
906e58ca 9008 eh = elf32_arm_hash_entry (h);
a4fd1a8e
PB		 9009 /* Allocate stubs for exported Thumb functions on v4t. */
9010 if (eh->export_glue == NULL)
9011 return TRUE;
9012
9013 globals = elf32_arm_hash_table (info);
a4fd1a8e
PB		 9014 BFD_ASSERT (globals != NULL);
9015 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
9016
3d4d4302
AM		 9017 s = bfd_get_linker_section (globals->bfd_of_glue_owner,
9018 ARM2THUMB_GLUE_SECTION_NAME);
a4fd1a8e
PB		 9019 BFD_ASSERT (s != NULL);
9020 BFD_ASSERT (s->contents != NULL);
9021 BFD_ASSERT (s->output_section != NULL);
9022
9023 sec = eh->export_glue->root.u.def.section;
0eaedd0e
PB		 9024
9025 BFD_ASSERT (sec->output_section != NULL);
9026
a4fd1a8e
PB		 9027 val = eh->export_glue->root.u.def.value + sec->output_offset
9028 + sec->output_section->vma;
8029a119 9029
a4fd1a8e
PB		 9030 myh = elf32_arm_create_thumb_stub (info, h->root.root.string,
9031 h->root.u.def.section->owner,
f2a9dd69
DJ		 9032 globals->obfd, sec, val, s,
9033 &error_message);
a4fd1a8e
PB		 9034 BFD_ASSERT (myh);
9035 return TRUE;
9036}
9037
845b51d6
PB		 9038/* Populate ARMv4 BX veneers. Returns the absolute adress of the veneer. */
9039
9040static bfd_vma
9041elf32_arm_bx_glue (struct bfd_link_info * info, int reg)
9042{
9043 bfd_byte *p;
9044 bfd_vma glue_addr;
9045 asection *s;
9046 struct elf32_arm_link_hash_table *globals;
9047
9048 globals = elf32_arm_hash_table (info);
845b51d6
PB		 9049 BFD_ASSERT (globals != NULL);
9050 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
9051
3d4d4302
AM		 9052 s = bfd_get_linker_section (globals->bfd_of_glue_owner,
9053 ARM_BX_GLUE_SECTION_NAME);
845b51d6
PB		 9054 BFD_ASSERT (s != NULL);
9055 BFD_ASSERT (s->contents != NULL);
9056 BFD_ASSERT (s->output_section != NULL);
9057
9058 BFD_ASSERT (globals->bx_glue_offset[reg] & 2);
9059
9060 glue_addr = globals->bx_glue_offset[reg] & ~(bfd_vma)3;
9061
9062 if ((globals->bx_glue_offset[reg] & 1) == 0)
9063 {
9064 p = s->contents + glue_addr;
9065 bfd_put_32 (globals->obfd, armbx1_tst_insn + (reg << 16), p);
9066 bfd_put_32 (globals->obfd, armbx2_moveq_insn + reg, p + 4);
9067 bfd_put_32 (globals->obfd, armbx3_bx_insn + reg, p + 8);
9068 globals->bx_glue_offset[reg] |= 1;
9069 }
9070
9071 return glue_addr + s->output_section->vma + s->output_offset;
9072}
9073
a4fd1a8e
PB		 9074/* Generate Arm stubs for exported Thumb symbols. */
9075static void
906e58ca 9076elf32_arm_begin_write_processing (bfd *abfd ATTRIBUTE_UNUSED,
a4fd1a8e
PB		 9077 struct bfd_link_info *link_info)
9078{
9079 struct elf32_arm_link_hash_table * globals;
9080
8029a119
NC		 9081 if (link_info == NULL)
9082 /* Ignore this if we are not called by the ELF backend linker. */
a4fd1a8e
PB		 9083 return;
9084
9085 globals = elf32_arm_hash_table (link_info);
4dfe6ac6
NC		 9086 if (globals == NULL)
9087 return;
9088
84c08195
PB		 9089 /* If blx is available then exported Thumb symbols are OK and there is
9090 nothing to do. */
a4fd1a8e
PB		 9091 if (globals->use_blx)
9092 return;
9093
9094 elf_link_hash_traverse (&globals->root, elf32_arm_to_thumb_export_stub,
9095 link_info);
9096}
9097
47beaa6a
RS		 9098/* Reserve space for COUNT dynamic relocations in relocation selection
9099 SRELOC. */
9100
9101static void
9102elf32_arm_allocate_dynrelocs (struct bfd_link_info *info, asection *sreloc,
9103 bfd_size_type count)
9104{
9105 struct elf32_arm_link_hash_table *htab;
9106
9107 htab = elf32_arm_hash_table (info);
9108 BFD_ASSERT (htab->root.dynamic_sections_created);
9109 if (sreloc == NULL)
9110 abort ();
9111 sreloc->size += RELOC_SIZE (htab) * count;
9112}
9113
34e77a92
RS		 9114/* Reserve space for COUNT R_ARM_IRELATIVE relocations. If the link is
9115 dynamic, the relocations should go in SRELOC, otherwise they should
9116 go in the special .rel.iplt section. */
9117
9118static void
9119elf32_arm_allocate_irelocs (struct bfd_link_info *info, asection *sreloc,
9120 bfd_size_type count)
9121{
9122 struct elf32_arm_link_hash_table *htab;
9123
9124 htab = elf32_arm_hash_table (info);
9125 if (!htab->root.dynamic_sections_created)
9126 htab->root.irelplt->size += RELOC_SIZE (htab) * count;
9127 else
9128 {
9129 BFD_ASSERT (sreloc != NULL);
9130 sreloc->size += RELOC_SIZE (htab) * count;
9131 }
9132}
9133
47beaa6a
RS		 9134/* Add relocation REL to the end of relocation section SRELOC. */
9135
9136static void
9137elf32_arm_add_dynreloc (bfd *output_bfd, struct bfd_link_info *info,
9138 asection *sreloc, Elf_Internal_Rela *rel)
9139{
9140 bfd_byte *loc;
9141 struct elf32_arm_link_hash_table *htab;
9142
9143 htab = elf32_arm_hash_table (info);
34e77a92
RS		 9144 if (!htab->root.dynamic_sections_created
9145 && ELF32_R_TYPE (rel->r_info) == R_ARM_IRELATIVE)
9146 sreloc = htab->root.irelplt;
47beaa6a
RS		 9147 if (sreloc == NULL)
9148 abort ();
9149 loc = sreloc->contents;
9150 loc += sreloc->reloc_count++ * RELOC_SIZE (htab);
9151 if (sreloc->reloc_count * RELOC_SIZE (htab) > sreloc->size)
9152 abort ();
9153 SWAP_RELOC_OUT (htab) (output_bfd, rel, loc);
9154}
9155
34e77a92
RS		 9156/* Allocate room for a PLT entry described by ROOT_PLT and ARM_PLT.
9157 IS_IPLT_ENTRY says whether the entry belongs to .iplt rather than
9158 to .plt. */
9159
9160static void
9161elf32_arm_allocate_plt_entry (struct bfd_link_info *info,
9162 bfd_boolean is_iplt_entry,
9163 union gotplt_union *root_plt,
9164 struct arm_plt_info *arm_plt)
9165{
9166 struct elf32_arm_link_hash_table *htab;
9167 asection *splt;
9168 asection *sgotplt;
9169
9170 htab = elf32_arm_hash_table (info);
9171
9172 if (is_iplt_entry)
9173 {
9174 splt = htab->root.iplt;
9175 sgotplt = htab->root.igotplt;
9176
99059e56
RM		 9177 /* NaCl uses a special first entry in .iplt too. */
9178 if (htab->nacl_p && splt->size == 0)
9179 splt->size += htab->plt_header_size;
9180
34e77a92
RS		 9181 /* Allocate room for an R_ARM_IRELATIVE relocation in .rel.iplt. */
9182 elf32_arm_allocate_irelocs (info, htab->root.irelplt, 1);
9183 }
9184 else
9185 {
9186 splt = htab->root.splt;
9187 sgotplt = htab->root.sgotplt;
9188
9189 /* Allocate room for an R_JUMP_SLOT relocation in .rel.plt. */
9190 elf32_arm_allocate_dynrelocs (info, htab->root.srelplt, 1);
9191
9192 /* If this is the first .plt entry, make room for the special
9193 first entry. */
9194 if (splt->size == 0)
9195 splt->size += htab->plt_header_size;
9f19ab6d
WN		 9196
9197 htab->next_tls_desc_index++;
34e77a92
RS		 9198 }
9199
9200 /* Allocate the PLT entry itself, including any leading Thumb stub. */
9201 if (elf32_arm_plt_needs_thumb_stub_p (info, arm_plt))
9202 splt->size += PLT_THUMB_STUB_SIZE;
9203 root_plt->offset = splt->size;
9204 splt->size += htab->plt_entry_size;
9205
9206 if (!htab->symbian_p)
9207 {
9208 /* We also need to make an entry in the .got.plt section, which
9209 will be placed in the .got section by the linker script. */
9f19ab6d
WN		 9210 if (is_iplt_entry)
9211 arm_plt->got_offset = sgotplt->size;
9212 else
9213 arm_plt->got_offset = sgotplt->size - 8 * htab->num_tls_desc;
34e77a92
RS		 9214 sgotplt->size += 4;
9215 }
9216}
9217
b38cadfb
NC		 9218static bfd_vma
9219arm_movw_immediate (bfd_vma value)
9220{
9221 return (value & 0x00000fff) | ((value & 0x0000f000) << 4);
9222}
9223
9224static bfd_vma
9225arm_movt_immediate (bfd_vma value)
9226{
9227 return ((value & 0x0fff0000) >> 16) | ((value & 0xf0000000) >> 12);
9228}
9229
34e77a92
RS		 9230/* Fill in a PLT entry and its associated GOT slot. If DYNINDX == -1,
9231 the entry lives in .iplt and resolves to (*SYM_VALUE)().
9232 Otherwise, DYNINDX is the index of the symbol in the dynamic
9233 symbol table and SYM_VALUE is undefined.
9234
9235 ROOT_PLT points to the offset of the PLT entry from the start of its
9236 section (.iplt or .plt). ARM_PLT points to the symbol's ARM-specific
57460bcf 9237 bookkeeping information.
34e77a92 9238
57460bcf
NC		 9239 Returns FALSE if there was a problem. */
9240
9241static bfd_boolean
34e77a92
RS		 9242elf32_arm_populate_plt_entry (bfd *output_bfd, struct bfd_link_info *info,
9243 union gotplt_union *root_plt,
9244 struct arm_plt_info *arm_plt,
9245 int dynindx, bfd_vma sym_value)
9246{
9247 struct elf32_arm_link_hash_table *htab;
9248 asection *sgot;
9249 asection *splt;
9250 asection *srel;
9251 bfd_byte *loc;
9252 bfd_vma plt_index;
9253 Elf_Internal_Rela rel;
9254 bfd_vma plt_header_size;
9255 bfd_vma got_header_size;
9256
9257 htab = elf32_arm_hash_table (info);
9258
9259 /* Pick the appropriate sections and sizes. */
9260 if (dynindx == -1)
9261 {
9262 splt = htab->root.iplt;
9263 sgot = htab->root.igotplt;
9264 srel = htab->root.irelplt;
9265
9266 /* There are no reserved entries in .igot.plt, and no special
9267 first entry in .iplt. */
9268 got_header_size = 0;
9269 plt_header_size = 0;
9270 }
9271 else
9272 {
9273 splt = htab->root.splt;
9274 sgot = htab->root.sgotplt;
9275 srel = htab->root.srelplt;
9276
9277 got_header_size = get_elf_backend_data (output_bfd)->got_header_size;
9278 plt_header_size = htab->plt_header_size;
9279 }
9280 BFD_ASSERT (splt != NULL && srel != NULL);
9281
9282 /* Fill in the entry in the procedure linkage table. */
9283 if (htab->symbian_p)
9284 {
9285 BFD_ASSERT (dynindx >= 0);
9286 put_arm_insn (htab, output_bfd,
9287 elf32_arm_symbian_plt_entry[0],
9288 splt->contents + root_plt->offset);
9289 bfd_put_32 (output_bfd,
9290 elf32_arm_symbian_plt_entry[1],
9291 splt->contents + root_plt->offset + 4);
9292
9293 /* Fill in the entry in the .rel.plt section. */
9294 rel.r_offset = (splt->output_section->vma
9295 + splt->output_offset
9296 + root_plt->offset + 4);
9297 rel.r_info = ELF32_R_INFO (dynindx, R_ARM_GLOB_DAT);
9298
9299 /* Get the index in the procedure linkage table which
9300 corresponds to this symbol. This is the index of this symbol
9301 in all the symbols for which we are making plt entries. The
9302 first entry in the procedure linkage table is reserved. */
9303 plt_index = ((root_plt->offset - plt_header_size)
9304 / htab->plt_entry_size);
9305 }
9306 else
9307 {
9308 bfd_vma got_offset, got_address, plt_address;
9309 bfd_vma got_displacement, initial_got_entry;
9310 bfd_byte * ptr;
9311
9312 BFD_ASSERT (sgot != NULL);
9313
9314 /* Get the offset into the .(i)got.plt table of the entry that
9315 corresponds to this function. */
9316 got_offset = (arm_plt->got_offset & -2);
9317
9318 /* Get the index in the procedure linkage table which
9319 corresponds to this symbol. This is the index of this symbol
9320 in all the symbols for which we are making plt entries.
9321 After the reserved .got.plt entries, all symbols appear in
9322 the same order as in .plt. */
9323 plt_index = (got_offset - got_header_size) / 4;
9324
9325 /* Calculate the address of the GOT entry. */
9326 got_address = (sgot->output_section->vma
9327 + sgot->output_offset
9328 + got_offset);
9329
9330 /* ...and the address of the PLT entry. */
9331 plt_address = (splt->output_section->vma
9332 + splt->output_offset
9333 + root_plt->offset);
9334
9335 ptr = splt->contents + root_plt->offset;
0e1862bb 9336 if (htab->vxworks_p && bfd_link_pic (info))
34e77a92
RS		 9337 {
9338 unsigned int i;
9339 bfd_vma val;
9340
9341 for (i = 0; i != htab->plt_entry_size / 4; i++, ptr += 4)
9342 {
9343 val = elf32_arm_vxworks_shared_plt_entry[i];
9344 if (i == 2)
9345 val |= got_address - sgot->output_section->vma;
9346 if (i == 5)
9347 val |= plt_index * RELOC_SIZE (htab);
9348 if (i == 2 || i == 5)
9349 bfd_put_32 (output_bfd, val, ptr);
9350 else
9351 put_arm_insn (htab, output_bfd, val, ptr);
9352 }
9353 }
9354 else if (htab->vxworks_p)
9355 {
9356 unsigned int i;
9357 bfd_vma val;
9358
9359 for (i = 0; i != htab->plt_entry_size / 4; i++, ptr += 4)
9360 {
9361 val = elf32_arm_vxworks_exec_plt_entry[i];
9362 if (i == 2)
9363 val |= got_address;
9364 if (i == 4)
9365 val |= 0xffffff & -((root_plt->offset + i * 4 + 8) >> 2);
9366 if (i == 5)
9367 val |= plt_index * RELOC_SIZE (htab);
9368 if (i == 2 || i == 5)
9369 bfd_put_32 (output_bfd, val, ptr);
9370 else
9371 put_arm_insn (htab, output_bfd, val, ptr);
9372 }
9373
9374 loc = (htab->srelplt2->contents
9375 + (plt_index * 2 + 1) * RELOC_SIZE (htab));
9376
9377 /* Create the .rela.plt.unloaded R_ARM_ABS32 relocation
9378 referencing the GOT for this PLT entry. */
9379 rel.r_offset = plt_address + 8;
9380 rel.r_info = ELF32_R_INFO (htab->root.hgot->indx, R_ARM_ABS32);
9381 rel.r_addend = got_offset;
9382 SWAP_RELOC_OUT (htab) (output_bfd, &rel, loc);
9383 loc += RELOC_SIZE (htab);
9384
9385 /* Create the R_ARM_ABS32 relocation referencing the
9386 beginning of the PLT for this GOT entry. */
9387 rel.r_offset = got_address;
9388 rel.r_info = ELF32_R_INFO (htab->root.hplt->indx, R_ARM_ABS32);
9389 rel.r_addend = 0;
9390 SWAP_RELOC_OUT (htab) (output_bfd, &rel, loc);
9391 }
b38cadfb
NC		 9392 else if (htab->nacl_p)
9393 {
9394 /* Calculate the displacement between the PLT slot and the
9395 common tail that's part of the special initial PLT slot. */
6034aab8 9396 int32_t tail_displacement
b38cadfb
NC		 9397 = ((splt->output_section->vma + splt->output_offset
9398 + ARM_NACL_PLT_TAIL_OFFSET)
9399 - (plt_address + htab->plt_entry_size + 4));
9400 BFD_ASSERT ((tail_displacement & 3) == 0);
9401 tail_displacement >>= 2;
9402
9403 BFD_ASSERT ((tail_displacement & 0xff000000) == 0
9404 || (-tail_displacement & 0xff000000) == 0);
9405
9406 /* Calculate the displacement between the PLT slot and the entry
9407 in the GOT. The offset accounts for the value produced by
9408 adding to pc in the penultimate instruction of the PLT stub. */
6034aab8 9409 got_displacement = (got_address
99059e56 9410 - (plt_address + htab->plt_entry_size));
b38cadfb
NC		 9411
9412 /* NaCl does not support interworking at all. */
9413 BFD_ASSERT (!elf32_arm_plt_needs_thumb_stub_p (info, arm_plt));
9414
9415 put_arm_insn (htab, output_bfd,
9416 elf32_arm_nacl_plt_entry[0]
9417 | arm_movw_immediate (got_displacement),
9418 ptr + 0);
9419 put_arm_insn (htab, output_bfd,
9420 elf32_arm_nacl_plt_entry[1]
9421 | arm_movt_immediate (got_displacement),
9422 ptr + 4);
9423 put_arm_insn (htab, output_bfd,
9424 elf32_arm_nacl_plt_entry[2],
9425 ptr + 8);
9426 put_arm_insn (htab, output_bfd,
9427 elf32_arm_nacl_plt_entry[3]
9428 | (tail_displacement & 0x00ffffff),
9429 ptr + 12);
9430 }
57460bcf
NC		 9431 else if (using_thumb_only (htab))
9432 {
eed94f8f 9433 /* PR ld/16017: Generate thumb only PLT entries. */
469a3493 9434 if (!using_thumb2 (htab))
eed94f8f
NC		 9435 {
9436 /* FIXME: We ought to be able to generate thumb-1 PLT
9437 instructions... */
9438 _bfd_error_handler (_("%B: Warning: thumb-1 mode PLT generation not currently supported"),
9439 output_bfd);
9440 return FALSE;
9441 }
57460bcf 9442
eed94f8f
NC		 9443 /* Calculate the displacement between the PLT slot and the entry in
9444 the GOT. The 12-byte offset accounts for the value produced by
9445 adding to pc in the 3rd instruction of the PLT stub. */
9446 got_displacement = got_address - (plt_address + 12);
9447
9448 /* As we are using 32 bit instructions we have to use 'put_arm_insn'
9449 instead of 'put_thumb_insn'. */
9450 put_arm_insn (htab, output_bfd,
9451 elf32_thumb2_plt_entry[0]
9452 | ((got_displacement & 0x000000ff) << 16)
9453 | ((got_displacement & 0x00000700) << 20)
9454 | ((got_displacement & 0x00000800) >> 1)
9455 | ((got_displacement & 0x0000f000) >> 12),
9456 ptr + 0);
9457 put_arm_insn (htab, output_bfd,
9458 elf32_thumb2_plt_entry[1]
9459 | ((got_displacement & 0x00ff0000) )
9460 | ((got_displacement & 0x07000000) << 4)
9461 | ((got_displacement & 0x08000000) >> 17)
9462 | ((got_displacement & 0xf0000000) >> 28),
9463 ptr + 4);
9464 put_arm_insn (htab, output_bfd,
9465 elf32_thumb2_plt_entry[2],
9466 ptr + 8);
9467 put_arm_insn (htab, output_bfd,
9468 elf32_thumb2_plt_entry[3],
9469 ptr + 12);
57460bcf 9470 }
34e77a92
RS		 9471 else
9472 {
9473 /* Calculate the displacement between the PLT slot and the
9474 entry in the GOT. The eight-byte offset accounts for the
9475 value produced by adding to pc in the first instruction
9476 of the PLT stub. */
9477 got_displacement = got_address - (plt_address + 8);
9478
34e77a92
RS		 9479 if (elf32_arm_plt_needs_thumb_stub_p (info, arm_plt))
9480 {
9481 put_thumb_insn (htab, output_bfd,
9482 elf32_arm_plt_thumb_stub[0], ptr - 4);
9483 put_thumb_insn (htab, output_bfd,
9484 elf32_arm_plt_thumb_stub[1], ptr - 2);
9485 }
9486
1db37fe6
YG		 9487 if (!elf32_arm_use_long_plt_entry)
9488 {
9489 BFD_ASSERT ((got_displacement & 0xf0000000) == 0);
9490
9491 put_arm_insn (htab, output_bfd,
9492 elf32_arm_plt_entry_short[0]
9493 | ((got_displacement & 0x0ff00000) >> 20),
9494 ptr + 0);
9495 put_arm_insn (htab, output_bfd,
9496 elf32_arm_plt_entry_short[1]
9497 | ((got_displacement & 0x000ff000) >> 12),
9498 ptr+ 4);
9499 put_arm_insn (htab, output_bfd,
9500 elf32_arm_plt_entry_short[2]
9501 | (got_displacement & 0x00000fff),
9502 ptr + 8);
34e77a92 9503#ifdef FOUR_WORD_PLT
1db37fe6 9504 bfd_put_32 (output_bfd, elf32_arm_plt_entry_short[3], ptr + 12);
34e77a92 9505#endif
1db37fe6
YG		 9506 }
9507 else
9508 {
9509 put_arm_insn (htab, output_bfd,
9510 elf32_arm_plt_entry_long[0]
9511 | ((got_displacement & 0xf0000000) >> 28),
9512 ptr + 0);
9513 put_arm_insn (htab, output_bfd,
9514 elf32_arm_plt_entry_long[1]
9515 | ((got_displacement & 0x0ff00000) >> 20),
9516 ptr + 4);
9517 put_arm_insn (htab, output_bfd,
9518 elf32_arm_plt_entry_long[2]
9519 | ((got_displacement & 0x000ff000) >> 12),
9520 ptr+ 8);
9521 put_arm_insn (htab, output_bfd,
9522 elf32_arm_plt_entry_long[3]
9523 | (got_displacement & 0x00000fff),
9524 ptr + 12);
9525 }
34e77a92
RS		 9526 }
9527
9528 /* Fill in the entry in the .rel(a).(i)plt section. */
9529 rel.r_offset = got_address;
9530 rel.r_addend = 0;
9531 if (dynindx == -1)
9532 {
9533 /* .igot.plt entries use IRELATIVE relocations against SYM_VALUE.
9534 The dynamic linker or static executable then calls SYM_VALUE
9535 to determine the correct run-time value of the .igot.plt entry. */
9536 rel.r_info = ELF32_R_INFO (0, R_ARM_IRELATIVE);
9537 initial_got_entry = sym_value;
9538 }
9539 else
9540 {
9541 rel.r_info = ELF32_R_INFO (dynindx, R_ARM_JUMP_SLOT);
9542 initial_got_entry = (splt->output_section->vma
9543 + splt->output_offset);
9544 }
9545
9546 /* Fill in the entry in the global offset table. */
9547 bfd_put_32 (output_bfd, initial_got_entry,
9548 sgot->contents + got_offset);
9549 }
9550
aba8c3de
WN		 9551 if (dynindx == -1)
9552 elf32_arm_add_dynreloc (output_bfd, info, srel, &rel);
9553 else
9554 {
9555 loc = srel->contents + plt_index * RELOC_SIZE (htab);
9556 SWAP_RELOC_OUT (htab) (output_bfd, &rel, loc);
9557 }
57460bcf
NC		 9558
9559 return TRUE;
34e77a92
RS		 9560}
9561
eb043451
PB		 9562/* Some relocations map to different relocations depending on the
9563 target. Return the real relocation. */
8029a119 9564
eb043451
PB		 9565static int
9566arm_real_reloc_type (struct elf32_arm_link_hash_table * globals,
9567 int r_type)
9568{
9569 switch (r_type)
9570 {
9571 case R_ARM_TARGET1:
9572 if (globals->target1_is_rel)
9573 return R_ARM_REL32;
9574 else
9575 return R_ARM_ABS32;
9576
9577 case R_ARM_TARGET2:
9578 return globals->target2_reloc;
9579
9580 default:
9581 return r_type;
9582 }
9583}
eb043451 9584
ba93b8ac
DJ		 9585/* Return the base VMA address which should be subtracted from real addresses
9586 when resolving @dtpoff relocation.
9587 This is PT_TLS segment p_vaddr. */
9588
9589static bfd_vma
9590dtpoff_base (struct bfd_link_info *info)
9591{
9592 /* If tls_sec is NULL, we should have signalled an error already. */
9593 if (elf_hash_table (info)->tls_sec == NULL)
9594 return 0;
9595 return elf_hash_table (info)->tls_sec->vma;
9596}
9597
9598/* Return the relocation value for @tpoff relocation
9599 if STT_TLS virtual address is ADDRESS. */
9600
9601static bfd_vma
9602tpoff (struct bfd_link_info *info, bfd_vma address)
9603{
9604 struct elf_link_hash_table *htab = elf_hash_table (info);
9605 bfd_vma base;
9606
9607 /* If tls_sec is NULL, we should have signalled an error already. */
9608 if (htab->tls_sec == NULL)
9609 return 0;
9610 base = align_power ((bfd_vma) TCB_SIZE, htab->tls_sec->alignment_power);
9611 return address - htab->tls_sec->vma + base;
9612}
9613
00a97672
RS		 9614/* Perform an R_ARM_ABS12 relocation on the field pointed to by DATA.
9615 VALUE is the relocation value. */
9616
9617static bfd_reloc_status_type
9618elf32_arm_abs12_reloc (bfd *abfd, void *data, bfd_vma value)
9619{
9620 if (value > 0xfff)
9621 return bfd_reloc_overflow;
9622
9623 value |= bfd_get_32 (abfd, data) & 0xfffff000;
9624 bfd_put_32 (abfd, value, data);
9625 return bfd_reloc_ok;
9626}
9627
0855e32b
NS		 9628/* Handle TLS relaxations. Relaxing is possible for symbols that use
9629 R_ARM_GOTDESC, R_ARM_{,THM_}TLS_CALL or
9630 R_ARM_{,THM_}TLS_DESCSEQ relocations, during a static link.
9631
9632 Return bfd_reloc_ok if we're done, bfd_reloc_continue if the caller
9633 is to then call final_link_relocate. Return other values in the
62672b10
NS		 9634 case of error.
9635
9636 FIXME:When --emit-relocs is in effect, we'll emit relocs describing
9637 the pre-relaxed code. It would be nice if the relocs were updated
9638 to match the optimization. */
0855e32b 9639
b38cadfb 9640static bfd_reloc_status_type
0855e32b 9641elf32_arm_tls_relax (struct elf32_arm_link_hash_table *globals,
b38cadfb 9642 bfd *input_bfd, asection *input_sec, bfd_byte *contents,
0855e32b
NS		 9643 Elf_Internal_Rela *rel, unsigned long is_local)
9644{
9645 unsigned long insn;
b38cadfb 9646
0855e32b
NS		 9647 switch (ELF32_R_TYPE (rel->r_info))
9648 {
9649 default:
9650 return bfd_reloc_notsupported;
b38cadfb 9651
0855e32b
NS		 9652 case R_ARM_TLS_GOTDESC:
9653 if (is_local)
9654 insn = 0;
9655 else
9656 {
9657 insn = bfd_get_32 (input_bfd, contents + rel->r_offset);
9658 if (insn & 1)
9659 insn -= 5; /* THUMB */
9660 else
9661 insn -= 8; /* ARM */
9662 }
9663 bfd_put_32 (input_bfd, insn, contents + rel->r_offset);
9664 return bfd_reloc_continue;
9665
9666 case R_ARM_THM_TLS_DESCSEQ:
9667 /* Thumb insn. */
9668 insn = bfd_get_16 (input_bfd, contents + rel->r_offset);
9669 if ((insn & 0xff78) == 0x4478) /* add rx, pc */
9670 {
9671 if (is_local)
9672 /* nop */
9673 bfd_put_16 (input_bfd, 0x46c0, contents + rel->r_offset);
9674 }
9675 else if ((insn & 0xffc0) == 0x6840) /* ldr rx,[ry,#4] */
9676 {
9677 if (is_local)
9678 /* nop */
9679 bfd_put_16 (input_bfd, 0x46c0, contents + rel->r_offset);
9680 else
9681 /* ldr rx,[ry] */
9682 bfd_put_16 (input_bfd, insn & 0xf83f, contents + rel->r_offset);
9683 }
9684 else if ((insn & 0xff87) == 0x4780) /* blx rx */
9685 {
9686 if (is_local)
9687 /* nop */
9688 bfd_put_16 (input_bfd, 0x46c0, contents + rel->r_offset);
9689 else
9690 /* mov r0, rx */
9691 bfd_put_16 (input_bfd, 0x4600 | (insn & 0x78),
9692 contents + rel->r_offset);
9693 }
9694 else
9695 {
9696 if ((insn & 0xf000) == 0xf000 || (insn & 0xf800) == 0xe800)
9697 /* It's a 32 bit instruction, fetch the rest of it for
9698 error generation. */
9699 insn = (insn << 16)
9700 | bfd_get_16 (input_bfd, contents + rel->r_offset + 2);
9701 (*_bfd_error_handler)
9702 (_("%B(%A+0x%lx):unexpected Thumb instruction '0x%x' in TLS trampoline"),
9703 input_bfd, input_sec, (unsigned long)rel->r_offset, insn);
9704 return bfd_reloc_notsupported;
9705 }
9706 break;
b38cadfb 9707
0855e32b
NS		 9708 case R_ARM_TLS_DESCSEQ:
9709 /* arm insn. */
9710 insn = bfd_get_32 (input_bfd, contents + rel->r_offset);
9711 if ((insn & 0xffff0ff0) == 0xe08f0000) /* add rx,pc,ry */
9712 {
9713 if (is_local)
9714 /* mov rx, ry */
9715 bfd_put_32 (input_bfd, 0xe1a00000 | (insn & 0xffff),
9716 contents + rel->r_offset);
9717 }
9718 else if ((insn & 0xfff00fff) == 0xe5900004) /* ldr rx,[ry,#4]*/
9719 {
9720 if (is_local)
9721 /* nop */
9722 bfd_put_32 (input_bfd, 0xe1a00000, contents + rel->r_offset);
9723 else
9724 /* ldr rx,[ry] */
9725 bfd_put_32 (input_bfd, insn & 0xfffff000,
9726 contents + rel->r_offset);
9727 }
9728 else if ((insn & 0xfffffff0) == 0xe12fff30) /* blx rx */
9729 {
9730 if (is_local)
9731 /* nop */
9732 bfd_put_32 (input_bfd, 0xe1a00000, contents + rel->r_offset);
9733 else
9734 /* mov r0, rx */
9735 bfd_put_32 (input_bfd, 0xe1a00000 | (insn & 0xf),
9736 contents + rel->r_offset);
9737 }
9738 else
9739 {
9740 (*_bfd_error_handler)
9741 (_("%B(%A+0x%lx):unexpected ARM instruction '0x%x' in TLS trampoline"),
9742 input_bfd, input_sec, (unsigned long)rel->r_offset, insn);
9743 return bfd_reloc_notsupported;
9744 }
9745 break;
9746
9747 case R_ARM_TLS_CALL:
9748 /* GD->IE relaxation, turn the instruction into 'nop' or
9749 'ldr r0, [pc,r0]' */
9750 insn = is_local ? 0xe1a00000 : 0xe79f0000;
9751 bfd_put_32 (input_bfd, insn, contents + rel->r_offset);
9752 break;
b38cadfb 9753
0855e32b 9754 case R_ARM_THM_TLS_CALL:
6a631e86 9755 /* GD->IE relaxation. */
0855e32b
NS		 9756 if (!is_local)
9757 /* add r0,pc; ldr r0, [r0] */
9758 insn = 0x44786800;
60a019a0 9759 else if (using_thumb2 (globals))
0855e32b
NS		 9760 /* nop.w */
9761 insn = 0xf3af8000;
9762 else
9763 /* nop; nop */
9764 insn = 0xbf00bf00;
b38cadfb 9765
0855e32b
NS		 9766 bfd_put_16 (input_bfd, insn >> 16, contents + rel->r_offset);
9767 bfd_put_16 (input_bfd, insn & 0xffff, contents + rel->r_offset + 2);
9768 break;
9769 }
9770 return bfd_reloc_ok;
9771}
9772
4962c51a
MS		 9773/* For a given value of n, calculate the value of G_n as required to
9774 deal with group relocations. We return it in the form of an
9775 encoded constant-and-rotation, together with the final residual. If n is
9776 specified as less than zero, then final_residual is filled with the
9777 input value and no further action is performed. */
9778
9779static bfd_vma
9780calculate_group_reloc_mask (bfd_vma value, int n, bfd_vma *final_residual)
9781{
9782 int current_n;
9783 bfd_vma g_n;
9784 bfd_vma encoded_g_n = 0;
9785 bfd_vma residual = value; /* Also known as Y_n. */
9786
9787 for (current_n = 0; current_n <= n; current_n++)
9788 {
9789 int shift;
9790
9791 /* Calculate which part of the value to mask. */
9792 if (residual == 0)
99059e56 9793 shift = 0;
4962c51a 9794 else
99059e56
RM		 9795 {
9796 int msb;
9797
9798 /* Determine the most significant bit in the residual and
9799 align the resulting value to a 2-bit boundary. */
9800 for (msb = 30; msb >= 0; msb -= 2)
9801 if (residual & (3 << msb))
9802 break;
9803
9804 /* The desired shift is now (msb - 6), or zero, whichever
9805 is the greater. */
9806 shift = msb - 6;
9807 if (shift < 0)
9808 shift = 0;
9809 }
4962c51a
MS		 9810
9811 /* Calculate g_n in 32-bit as well as encoded constant+rotation form. */
9812 g_n = residual & (0xff << shift);
9813 encoded_g_n = (g_n >> shift)
99059e56 9814 | ((g_n <= 0xff ? 0 : (32 - shift) / 2) << 8);
4962c51a
MS		 9815
9816 /* Calculate the residual for the next time around. */
9817 residual &= ~g_n;
9818 }
9819
9820 *final_residual = residual;
9821
9822 return encoded_g_n;
9823}
9824
9825/* Given an ARM instruction, determine whether it is an ADD or a SUB.
9826 Returns 1 if it is an ADD, -1 if it is a SUB, and 0 otherwise. */
906e58ca 9827
4962c51a 9828static int
906e58ca 9829identify_add_or_sub (bfd_vma insn)
4962c51a
MS		 9830{
9831 int opcode = insn & 0x1e00000;
9832
9833 if (opcode == 1 << 23) /* ADD */
9834 return 1;
9835
9836 if (opcode == 1 << 22) /* SUB */
9837 return -1;
9838
9839 return 0;
9840}
9841
252b5132 9842/* Perform a relocation as part of a final link. */
9b485d32 9843
252b5132 9844static bfd_reloc_status_type
57e8b36a
NC		 9845elf32_arm_final_link_relocate (reloc_howto_type * howto,
9846 bfd * input_bfd,
9847 bfd * output_bfd,
9848 asection * input_section,
9849 bfd_byte * contents,
9850 Elf_Internal_Rela * rel,
9851 bfd_vma value,
9852 struct bfd_link_info * info,
9853 asection * sym_sec,
9854 const char * sym_name,
34e77a92
RS		 9855 unsigned char st_type,
9856 enum arm_st_branch_type branch_type,
0945cdfd 9857 struct elf_link_hash_entry * h,
f2a9dd69 9858 bfd_boolean * unresolved_reloc_p,
8029a119 9859 char ** error_message)
252b5132
RH		 9860{
9861 unsigned long r_type = howto->type;
9862 unsigned long r_symndx;
9863 bfd_byte * hit_data = contents + rel->r_offset;
252b5132 9864 bfd_vma * local_got_offsets;
0855e32b 9865 bfd_vma * local_tlsdesc_gotents;
34e77a92
RS		 9866 asection * sgot;
9867 asection * splt;
252b5132 9868 asection * sreloc = NULL;
362d30a1 9869 asection * srelgot;
252b5132 9870 bfd_vma addend;
ba96a88f 9871 bfd_signed_vma signed_addend;
34e77a92
RS		 9872 unsigned char dynreloc_st_type;
9873 bfd_vma dynreloc_value;
ba96a88f 9874 struct elf32_arm_link_hash_table * globals;
34e77a92
RS		 9875 struct elf32_arm_link_hash_entry *eh;
9876 union gotplt_union *root_plt;
9877 struct arm_plt_info *arm_plt;
9878 bfd_vma plt_offset;
9879 bfd_vma gotplt_offset;
9880 bfd_boolean has_iplt_entry;
f21f3fe0 9881
9c504268 9882 globals = elf32_arm_hash_table (info);
4dfe6ac6
NC		 9883 if (globals == NULL)
9884 return bfd_reloc_notsupported;
9c504268 9885
0ffa91dd
NC		 9886 BFD_ASSERT (is_arm_elf (input_bfd));
9887
9888 /* Some relocation types map to different relocations depending on the
9c504268 9889 target. We pick the right one here. */
eb043451 9890 r_type = arm_real_reloc_type (globals, r_type);
0855e32b
NS		 9891
9892 /* It is possible to have linker relaxations on some TLS access
9893 models. Update our information here. */
9894 r_type = elf32_arm_tls_transition (info, r_type, h);
9895
eb043451
PB		 9896 if (r_type != howto->type)
9897 howto = elf32_arm_howto_from_type (r_type);
9c504268 9898
34e77a92 9899 eh = (struct elf32_arm_link_hash_entry *) h;
362d30a1 9900 sgot = globals->root.sgot;
252b5132 9901 local_got_offsets = elf_local_got_offsets (input_bfd);
0855e32b
NS		 9902 local_tlsdesc_gotents = elf32_arm_local_tlsdesc_gotent (input_bfd);
9903
34e77a92
RS		 9904 if (globals->root.dynamic_sections_created)
9905 srelgot = globals->root.srelgot;
9906 else
9907 srelgot = NULL;
9908
252b5132
RH		 9909 r_symndx = ELF32_R_SYM (rel->r_info);
9910
4e7fd91e 9911 if (globals->use_rel)
ba96a88f 9912 {
4e7fd91e
PB		 9913 addend = bfd_get_32 (input_bfd, hit_data) & howto->src_mask;
9914
9915 if (addend & ((howto->src_mask + 1) >> 1))
9916 {
9917 signed_addend = -1;
9918 signed_addend &= ~ howto->src_mask;
9919 signed_addend |= addend;
9920 }
9921 else
9922 signed_addend = addend;
ba96a88f
NC		 9923 }
9924 else
4e7fd91e 9925 addend = signed_addend = rel->r_addend;
f21f3fe0 9926
39f21624
NC		 9927 /* ST_BRANCH_TO_ARM is nonsense to thumb-only targets when we
9928 are resolving a function call relocation. */
9929 if (using_thumb_only (globals)
9930 && (r_type == R_ARM_THM_CALL
9931 || r_type == R_ARM_THM_JUMP24)
9932 && branch_type == ST_BRANCH_TO_ARM)
9933 branch_type = ST_BRANCH_TO_THUMB;
9934
34e77a92
RS		 9935 /* Record the symbol information that should be used in dynamic
9936 relocations. */
9937 dynreloc_st_type = st_type;
9938 dynreloc_value = value;
9939 if (branch_type == ST_BRANCH_TO_THUMB)
9940 dynreloc_value |= 1;
9941
9942 /* Find out whether the symbol has a PLT. Set ST_VALUE, BRANCH_TYPE and
9943 VALUE appropriately for relocations that we resolve at link time. */
9944 has_iplt_entry = FALSE;
4ba2ef8f
TP		 9945 if (elf32_arm_get_plt_info (input_bfd, globals, eh, r_symndx, &root_plt,
9946 &arm_plt)
34e77a92
RS		 9947 && root_plt->offset != (bfd_vma) -1)
9948 {
9949 plt_offset = root_plt->offset;
9950 gotplt_offset = arm_plt->got_offset;
9951
9952 if (h == NULL || eh->is_iplt)
9953 {
9954 has_iplt_entry = TRUE;
9955 splt = globals->root.iplt;
9956
9957 /* Populate .iplt entries here, because not all of them will
9958 be seen by finish_dynamic_symbol. The lower bit is set if
9959 we have already populated the entry. */
9960 if (plt_offset & 1)
9961 plt_offset--;
9962 else
9963 {
57460bcf
NC		 9964 if (elf32_arm_populate_plt_entry (output_bfd, info, root_plt, arm_plt,
9965 -1, dynreloc_value))
9966 root_plt->offset |= 1;
9967 else
9968 return bfd_reloc_notsupported;
34e77a92
RS		 9969 }
9970
9971 /* Static relocations always resolve to the .iplt entry. */
9972 st_type = STT_FUNC;
9973 value = (splt->output_section->vma
9974 + splt->output_offset
9975 + plt_offset);
9976 branch_type = ST_BRANCH_TO_ARM;
9977
9978 /* If there are non-call relocations that resolve to the .iplt
9979 entry, then all dynamic ones must too. */
9980 if (arm_plt->noncall_refcount != 0)
9981 {
9982 dynreloc_st_type = st_type;
9983 dynreloc_value = value;
9984 }
9985 }
9986 else
9987 /* We populate the .plt entry in finish_dynamic_symbol. */
9988 splt = globals->root.splt;
9989 }
9990 else
9991 {
9992 splt = NULL;
9993 plt_offset = (bfd_vma) -1;
9994 gotplt_offset = (bfd_vma) -1;
9995 }
9996
252b5132
RH		 9997 switch (r_type)
9998 {
9999 case R_ARM_NONE:
28a094c2
DJ		 10000 /* We don't need to find a value for this symbol. It's just a
10001 marker. */
10002 *unresolved_reloc_p = FALSE;
252b5132
RH		 10003 return bfd_reloc_ok;
10004
00a97672
RS		 10005 case R_ARM_ABS12:
10006 if (!globals->vxworks_p)
10007 return elf32_arm_abs12_reloc (input_bfd, hit_data, value + addend);
10008
252b5132
RH		 10009 case R_ARM_PC24:
10010 case R_ARM_ABS32:
bb224fc3 10011 case R_ARM_ABS32_NOI:
252b5132 10012 case R_ARM_REL32:
bb224fc3 10013 case R_ARM_REL32_NOI:
5b5bb741
PB		 10014 case R_ARM_CALL:
10015 case R_ARM_JUMP24:
dfc5f959 10016 case R_ARM_XPC25:
eb043451 10017 case R_ARM_PREL31:
7359ea65 10018 case R_ARM_PLT32:
7359ea65
DJ		 10019 /* Handle relocations which should use the PLT entry. ABS32/REL32
10020 will use the symbol's value, which may point to a PLT entry, but we
10021 don't need to handle that here. If we created a PLT entry, all
5fa9e92f
CL		 10022 branches in this object should go to it, except if the PLT is too
10023 far away, in which case a long branch stub should be inserted. */
bb224fc3 10024 if ((r_type != R_ARM_ABS32 && r_type != R_ARM_REL32
99059e56 10025 && r_type != R_ARM_ABS32_NOI && r_type != R_ARM_REL32_NOI
155d87d7
CL		 10026 && r_type != R_ARM_CALL
10027 && r_type != R_ARM_JUMP24
10028 && r_type != R_ARM_PLT32)
34e77a92 10029 && plt_offset != (bfd_vma) -1)
7359ea65 10030 {
34e77a92
RS		 10031 /* If we've created a .plt section, and assigned a PLT entry
10032 to this function, it must either be a STT_GNU_IFUNC reference
10033 or not be known to bind locally. In other cases, we should
10034 have cleared the PLT entry by now. */
10035 BFD_ASSERT (has_iplt_entry || !SYMBOL_CALLS_LOCAL (info, h));
7359ea65
DJ		 10036
10037 value = (splt->output_section->vma
10038 + splt->output_offset
34e77a92 10039 + plt_offset);
0945cdfd 10040 *unresolved_reloc_p = FALSE;
7359ea65
DJ		 10041 return _bfd_final_link_relocate (howto, input_bfd, input_section,
10042 contents, rel->r_offset, value,
00a97672 10043 rel->r_addend);
7359ea65
DJ		 10044 }
10045
67687978
PB		 10046 /* When generating a shared object or relocatable executable, these
10047 relocations are copied into the output file to be resolved at
10048 run time. */
0e1862bb
L		 10049 if ((bfd_link_pic (info)
10050 || globals->root.is_relocatable_executable)
7359ea65 10051 && (input_section->flags & SEC_ALLOC)
4dfe6ac6 10052 && !(globals->vxworks_p
3348747a
NS		 10053 && strcmp (input_section->output_section->name,
10054 ".tls_vars") == 0)
bb224fc3 10055 && ((r_type != R_ARM_REL32 && r_type != R_ARM_REL32_NOI)
ee06dc07 10056 || !SYMBOL_CALLS_LOCAL (info, h))
ca6b5f82
AM		 10057 && !(input_bfd == globals->stub_bfd
10058 && strstr (input_section->name, STUB_SUFFIX))
7359ea65
DJ		 10059 && (h == NULL
10060 || ELF_ST_VISIBILITY (h->other) == STV_DEFAULT
10061 || h->root.type != bfd_link_hash_undefweak)
10062 && r_type != R_ARM_PC24
5b5bb741
PB		 10063 && r_type != R_ARM_CALL
10064 && r_type != R_ARM_JUMP24
ee06dc07 10065 && r_type != R_ARM_PREL31
7359ea65 10066 && r_type != R_ARM_PLT32)
252b5132 10067 {
947216bf 10068 Elf_Internal_Rela outrel;
b34976b6 10069 bfd_boolean skip, relocate;
f21f3fe0 10070
52db4ec2
JW		 10071 if ((r_type == R_ARM_REL32 || r_type == R_ARM_REL32_NOI)
10072 && !h->def_regular)
10073 {
10074 char *v = _("shared object");
10075
0e1862bb 10076 if (bfd_link_executable (info))
52db4ec2
JW		 10077 v = _("PIE executable");
10078
10079 (*_bfd_error_handler)
10080 (_("%B: relocation %s against external or undefined symbol `%s'"
10081 " can not be used when making a %s; recompile with -fPIC"), input_bfd,
10082 elf32_arm_howto_table_1[r_type].name, h->root.root.string, v);
10083 return bfd_reloc_notsupported;
10084 }
10085
0945cdfd
DJ		 10086 *unresolved_reloc_p = FALSE;
10087
34e77a92 10088 if (sreloc == NULL && globals->root.dynamic_sections_created)
252b5132 10089 {
83bac4b0
NC		 10090 sreloc = _bfd_elf_get_dynamic_reloc_section (input_bfd, input_section,
10091 ! globals->use_rel);
f21f3fe0 10092
83bac4b0 10093 if (sreloc == NULL)
252b5132 10094 return bfd_reloc_notsupported;
252b5132 10095 }
f21f3fe0 10096
b34976b6
AM		 10097 skip = FALSE;
10098 relocate = FALSE;
f21f3fe0 10099
00a97672 10100 outrel.r_addend = addend;
c629eae0
JJ		 10101 outrel.r_offset =
10102 _bfd_elf_section_offset (output_bfd, info, input_section,
10103 rel->r_offset);
10104 if (outrel.r_offset == (bfd_vma) -1)
b34976b6 10105 skip = TRUE;
0bb2d96a 10106 else if (outrel.r_offset == (bfd_vma) -2)
b34976b6 10107 skip = TRUE, relocate = TRUE;
252b5132
RH		 10108 outrel.r_offset += (input_section->output_section->vma
10109 + input_section->output_offset);
f21f3fe0 10110
252b5132 10111 if (skip)
0bb2d96a 10112 memset (&outrel, 0, sizeof outrel);
5e681ec4
PB		 10113 else if (h != NULL
10114 && h->dynindx != -1
0e1862bb 10115 && (!bfd_link_pic (info)
a496fbc8 10116 || !SYMBOLIC_BIND (info, h)
f5385ebf 10117 || !h->def_regular))
5e681ec4 10118 outrel.r_info = ELF32_R_INFO (h->dynindx, r_type);
252b5132
RH		 10119 else
10120 {
a16385dc
MM		 10121 int symbol;
10122
5e681ec4 10123 /* This symbol is local, or marked to become local. */
34e77a92 10124 BFD_ASSERT (r_type == R_ARM_ABS32 || r_type == R_ARM_ABS32_NOI);
a16385dc 10125 if (globals->symbian_p)
6366ff1e 10126 {
74541ad4
AM		 10127 asection *osec;
10128
6366ff1e
MM		 10129 /* On Symbian OS, the data segment and text segement
10130 can be relocated independently. Therefore, we
10131 must indicate the segment to which this
10132 relocation is relative. The BPABI allows us to
10133 use any symbol in the right segment; we just use
10134 the section symbol as it is convenient. (We
10135 cannot use the symbol given by "h" directly as it
74541ad4
AM		 10136 will not appear in the dynamic symbol table.)
10137
10138 Note that the dynamic linker ignores the section
10139 symbol value, so we don't subtract osec->vma
10140 from the emitted reloc addend. */
10dbd1f3 10141 if (sym_sec)
74541ad4 10142 osec = sym_sec->output_section;
10dbd1f3 10143 else
74541ad4
AM		 10144 osec = input_section->output_section;
10145 symbol = elf_section_data (osec)->dynindx;
10146 if (symbol == 0)
10147 {
10148 struct elf_link_hash_table *htab = elf_hash_table (info);
10149
10150 if ((osec->flags & SEC_READONLY) == 0
10151 && htab->data_index_section != NULL)
10152 osec = htab->data_index_section;
10153 else
10154 osec = htab->text_index_section;
10155 symbol = elf_section_data (osec)->dynindx;
10156 }
6366ff1e
MM		 10157 BFD_ASSERT (symbol != 0);
10158 }
a16385dc
MM		 10159 else
10160 /* On SVR4-ish systems, the dynamic loader cannot
10161 relocate the text and data segments independently,
10162 so the symbol does not matter. */
10163 symbol = 0;
34e77a92
RS		 10164 if (dynreloc_st_type == STT_GNU_IFUNC)
10165 /* We have an STT_GNU_IFUNC symbol that doesn't resolve
10166 to the .iplt entry. Instead, every non-call reference
10167 must use an R_ARM_IRELATIVE relocation to obtain the
10168 correct run-time address. */
10169 outrel.r_info = ELF32_R_INFO (symbol, R_ARM_IRELATIVE);
10170 else
10171 outrel.r_info = ELF32_R_INFO (symbol, R_ARM_RELATIVE);
00a97672
RS		 10172 if (globals->use_rel)
10173 relocate = TRUE;
10174 else
34e77a92 10175 outrel.r_addend += dynreloc_value;
252b5132 10176 }
f21f3fe0 10177
47beaa6a 10178 elf32_arm_add_dynreloc (output_bfd, info, sreloc, &outrel);
9a5aca8c 10179
f21f3fe0 10180 /* If this reloc is against an external symbol, we do not want to
252b5132 10181 fiddle with the addend. Otherwise, we need to include the symbol
9b485d32 10182 value so that it becomes an addend for the dynamic reloc. */
252b5132
RH		 10183 if (! relocate)
10184 return bfd_reloc_ok;
9a5aca8c 10185
f21f3fe0 10186 return _bfd_final_link_relocate (howto, input_bfd, input_section,
34e77a92
RS		 10187 contents, rel->r_offset,
10188 dynreloc_value, (bfd_vma) 0);
252b5132
RH		 10189 }
10190 else switch (r_type)
10191 {
00a97672
RS		 10192 case R_ARM_ABS12:
10193 return elf32_arm_abs12_reloc (input_bfd, hit_data, value + addend);
10194
dfc5f959 10195 case R_ARM_XPC25: /* Arm BLX instruction. */
5b5bb741
PB		 10196 case R_ARM_CALL:
10197 case R_ARM_JUMP24:
8029a119 10198 case R_ARM_PC24: /* Arm B/BL instruction. */
7359ea65 10199 case R_ARM_PLT32:
906e58ca 10200 {
906e58ca
NC		 10201 struct elf32_arm_stub_hash_entry *stub_entry = NULL;
10202
dfc5f959 10203 if (r_type == R_ARM_XPC25)
252b5132 10204 {
dfc5f959
NC		 10205 /* Check for Arm calling Arm function. */
10206 /* FIXME: Should we translate the instruction into a BL
10207 instruction instead ? */
35fc36a8 10208 if (branch_type != ST_BRANCH_TO_THUMB)
d003868e
AM		 10209 (*_bfd_error_handler)
10210 (_("\%B: Warning: Arm BLX instruction targets Arm function '%s'."),
10211 input_bfd,
10212 h ? h->root.root.string : "(local)");
dfc5f959 10213 }
155d87d7 10214 else if (r_type == R_ARM_PC24)
dfc5f959
NC		 10215 {
10216 /* Check for Arm calling Thumb function. */
35fc36a8 10217 if (branch_type == ST_BRANCH_TO_THUMB)
dfc5f959 10218 {
f2a9dd69
DJ		 10219 if (elf32_arm_to_thumb_stub (info, sym_name, input_bfd,
10220 output_bfd, input_section,
10221 hit_data, sym_sec, rel->r_offset,
10222 signed_addend, value,
10223 error_message))
10224 return bfd_reloc_ok;
10225 else
10226 return bfd_reloc_dangerous;
dfc5f959 10227 }
252b5132 10228 }
ba96a88f 10229
906e58ca 10230 /* Check if a stub has to be inserted because the
8029a119 10231 destination is too far or we are changing mode. */
155d87d7
CL		 10232 if ( r_type == R_ARM_CALL
10233 || r_type == R_ARM_JUMP24
10234 || r_type == R_ARM_PLT32)
906e58ca 10235 {
fe33d2fa
CL		 10236 enum elf32_arm_stub_type stub_type = arm_stub_none;
10237 struct elf32_arm_link_hash_entry *hash;
10238
10239 hash = (struct elf32_arm_link_hash_entry *) h;
10240 stub_type = arm_type_of_stub (info, input_section, rel,
34e77a92
RS		 10241 st_type, &branch_type,
10242 hash, value, sym_sec,
fe33d2fa 10243 input_bfd, sym_name);
5fa9e92f 10244
fe33d2fa 10245 if (stub_type != arm_stub_none)
906e58ca
NC		 10246 {
10247 /* The target is out of reach, so redirect the
10248 branch to the local stub for this function. */
906e58ca
NC		 10249 stub_entry = elf32_arm_get_stub_entry (input_section,
10250 sym_sec, h,
fe33d2fa
CL		 10251 rel, globals,
10252 stub_type);
9cd3e4e5
NC		 10253 {
10254 if (stub_entry != NULL)
10255 value = (stub_entry->stub_offset
10256 + stub_entry->stub_sec->output_offset
10257 + stub_entry->stub_sec->output_section->vma);
10258
10259 if (plt_offset != (bfd_vma) -1)
10260 *unresolved_reloc_p = FALSE;
10261 }
906e58ca 10262 }
fe33d2fa
CL		 10263 else
10264 {
10265 /* If the call goes through a PLT entry, make sure to
10266 check distance to the right destination address. */
34e77a92 10267 if (plt_offset != (bfd_vma) -1)
fe33d2fa
CL		 10268 {
10269 value = (splt->output_section->vma
10270 + splt->output_offset
34e77a92 10271 + plt_offset);
fe33d2fa
CL		 10272 *unresolved_reloc_p = FALSE;
10273 /* The PLT entry is in ARM mode, regardless of the
10274 target function. */
35fc36a8 10275 branch_type = ST_BRANCH_TO_ARM;
fe33d2fa
CL		 10276 }
10277 }
906e58ca
NC		 10278 }
10279
dea514f5
PB		 10280 /* The ARM ELF ABI says that this reloc is computed as: S - P + A
10281 where:
10282 S is the address of the symbol in the relocation.
10283 P is address of the instruction being relocated.
10284 A is the addend (extracted from the instruction) in bytes.
10285
10286 S is held in 'value'.
10287 P is the base address of the section containing the
10288 instruction plus the offset of the reloc into that
10289 section, ie:
10290 (input_section->output_section->vma +
10291 input_section->output_offset +
10292 rel->r_offset).
10293 A is the addend, converted into bytes, ie:
10294 (signed_addend * 4)
10295
10296 Note: None of these operations have knowledge of the pipeline
10297 size of the processor, thus it is up to the assembler to
10298 encode this information into the addend. */
10299 value -= (input_section->output_section->vma
10300 + input_section->output_offset);
10301 value -= rel->r_offset;
4e7fd91e
PB		 10302 if (globals->use_rel)
10303 value += (signed_addend << howto->size);
10304 else
10305 /* RELA addends do not have to be adjusted by howto->size. */
10306 value += signed_addend;
23080146 10307
dcb5e6e6
NC		 10308 signed_addend = value;
10309 signed_addend >>= howto->rightshift;
9a5aca8c 10310
5ab79981 10311 /* A branch to an undefined weak symbol is turned into a jump to
ffcb4889 10312 the next instruction unless a PLT entry will be created.
77b4f08f 10313 Do the same for local undefined symbols (but not for STN_UNDEF).
cd1dac3d
DG		 10314 The jump to the next instruction is optimized as a NOP depending
10315 on the architecture. */
ffcb4889 10316 if (h ? (h->root.type == bfd_link_hash_undefweak
34e77a92 10317 && plt_offset == (bfd_vma) -1)
77b4f08f 10318 : r_symndx != STN_UNDEF && bfd_is_und_section (sym_sec))
5ab79981 10319 {
cd1dac3d
DG		 10320 value = (bfd_get_32 (input_bfd, hit_data) & 0xf0000000);
10321
10322 if (arch_has_arm_nop (globals))
10323 value |= 0x0320f000;
10324 else
10325 value |= 0x01a00000; /* Using pre-UAL nop: mov r0, r0. */
5ab79981
PB		 10326 }
10327 else
59f2c4e7 10328 {
9b485d32 10329 /* Perform a signed range check. */
dcb5e6e6 10330 if ( signed_addend > ((bfd_signed_vma) (howto->dst_mask >> 1))
59f2c4e7
NC		 10331 || signed_addend < - ((bfd_signed_vma) ((howto->dst_mask + 1) >> 1)))
10332 return bfd_reloc_overflow;
9a5aca8c 10333
5ab79981 10334 addend = (value & 2);
39b41c9c 10335
5ab79981
PB		 10336 value = (signed_addend & howto->dst_mask)
10337 | (bfd_get_32 (input_bfd, hit_data) & (~ howto->dst_mask));
39b41c9c 10338
5ab79981
PB		 10339 if (r_type == R_ARM_CALL)
10340 {
155d87d7 10341 /* Set the H bit in the BLX instruction. */
35fc36a8 10342 if (branch_type == ST_BRANCH_TO_THUMB)
155d87d7
CL		 10343 {
10344 if (addend)
10345 value |= (1 << 24);
10346 else
10347 value &= ~(bfd_vma)(1 << 24);
10348 }
10349
5ab79981 10350 /* Select the correct instruction (BL or BLX). */
906e58ca 10351 /* Only if we are not handling a BL to a stub. In this
8029a119 10352 case, mode switching is performed by the stub. */
35fc36a8 10353 if (branch_type == ST_BRANCH_TO_THUMB && !stub_entry)
5ab79981 10354 value |= (1 << 28);
63e1a0fc 10355 else if (stub_entry || branch_type != ST_BRANCH_UNKNOWN)
5ab79981
PB		 10356 {
10357 value &= ~(bfd_vma)(1 << 28);
10358 value |= (1 << 24);
10359 }
39b41c9c
PB		 10360 }
10361 }
906e58ca 10362 }
252b5132 10363 break;
f21f3fe0 10364
252b5132
RH		 10365 case R_ARM_ABS32:
10366 value += addend;
35fc36a8 10367 if (branch_type == ST_BRANCH_TO_THUMB)
252b5132
RH		 10368 value |= 1;
10369 break;
f21f3fe0 10370
bb224fc3
MS		 10371 case R_ARM_ABS32_NOI:
10372 value += addend;
10373 break;
10374
252b5132 10375 case R_ARM_REL32:
a8bc6c78 10376 value += addend;
35fc36a8 10377 if (branch_type == ST_BRANCH_TO_THUMB)
a8bc6c78 10378 value |= 1;
252b5132 10379 value -= (input_section->output_section->vma
62efb346 10380 + input_section->output_offset + rel->r_offset);
252b5132 10381 break;
eb043451 10382
bb224fc3
MS		 10383 case R_ARM_REL32_NOI:
10384 value += addend;
10385 value -= (input_section->output_section->vma
10386 + input_section->output_offset + rel->r_offset);
10387 break;
10388
eb043451
PB		 10389 case R_ARM_PREL31:
10390 value -= (input_section->output_section->vma
10391 + input_section->output_offset + rel->r_offset);
10392 value += signed_addend;
10393 if (! h || h->root.type != bfd_link_hash_undefweak)
10394 {
8029a119 10395 /* Check for overflow. */
eb043451
PB		 10396 if ((value ^ (value >> 1)) & (1 << 30))
10397 return bfd_reloc_overflow;
10398 }
10399 value &= 0x7fffffff;
10400 value |= (bfd_get_32 (input_bfd, hit_data) & 0x80000000);
35fc36a8 10401 if (branch_type == ST_BRANCH_TO_THUMB)
eb043451
PB		 10402 value |= 1;
10403 break;
252b5132 10404 }
f21f3fe0 10405
252b5132
RH		 10406 bfd_put_32 (input_bfd, value, hit_data);
10407 return bfd_reloc_ok;
10408
10409 case R_ARM_ABS8:
fd0fd00c
MJ		 10410 /* PR 16202: Refectch the addend using the correct size. */
10411 if (globals->use_rel)
10412 addend = bfd_get_8 (input_bfd, hit_data);
252b5132 10413 value += addend;
4e67d4ca
DG		 10414
10415 /* There is no way to tell whether the user intended to use a signed or
10416 unsigned addend. When checking for overflow we accept either,
10417 as specified by the AAELF. */
10418 if ((long) value > 0xff || (long) value < -0x80)
252b5132
RH		 10419 return bfd_reloc_overflow;
10420
10421 bfd_put_8 (input_bfd, value, hit_data);
10422 return bfd_reloc_ok;
10423
10424 case R_ARM_ABS16:
fd0fd00c
MJ		 10425 /* PR 16202: Refectch the addend using the correct size. */
10426 if (globals->use_rel)
10427 addend = bfd_get_16 (input_bfd, hit_data);
252b5132
RH		 10428 value += addend;
10429
4e67d4ca
DG		 10430 /* See comment for R_ARM_ABS8. */
10431 if ((long) value > 0xffff || (long) value < -0x8000)
252b5132
RH		 10432 return bfd_reloc_overflow;
10433
10434 bfd_put_16 (input_bfd, value, hit_data);
10435 return bfd_reloc_ok;
10436
252b5132 10437 case R_ARM_THM_ABS5:
9b485d32 10438 /* Support ldr and str instructions for the thumb. */
4e7fd91e
PB		 10439 if (globals->use_rel)
10440 {
10441 /* Need to refetch addend. */
10442 addend = bfd_get_16 (input_bfd, hit_data) & howto->src_mask;
10443 /* ??? Need to determine shift amount from operand size. */
10444 addend >>= howto->rightshift;
10445 }
252b5132
RH		 10446 value += addend;
10447
10448 /* ??? Isn't value unsigned? */
10449 if ((long) value > 0x1f || (long) value < -0x10)
10450 return bfd_reloc_overflow;
10451
10452 /* ??? Value needs to be properly shifted into place first. */
10453 value |= bfd_get_16 (input_bfd, hit_data) & 0xf83f;
10454 bfd_put_16 (input_bfd, value, hit_data);
10455 return bfd_reloc_ok;
10456
2cab6cc3
MS		 10457 case R_ARM_THM_ALU_PREL_11_0:
10458 /* Corresponds to: addw.w reg, pc, #offset (and similarly for subw). */
10459 {
10460 bfd_vma insn;
10461 bfd_signed_vma relocation;
10462
10463 insn = (bfd_get_16 (input_bfd, hit_data) << 16)
99059e56 10464 | bfd_get_16 (input_bfd, hit_data + 2);
2cab6cc3 10465
99059e56
RM		 10466 if (globals->use_rel)
10467 {
10468 signed_addend = (insn & 0xff) | ((insn & 0x7000) >> 4)
10469 | ((insn & (1 << 26)) >> 15);
10470 if (insn & 0xf00000)
10471 signed_addend = -signed_addend;
10472 }
2cab6cc3
MS		 10473
10474 relocation = value + signed_addend;
79f08007 10475 relocation -= Pa (input_section->output_section->vma
99059e56
RM		 10476 + input_section->output_offset
10477 + rel->r_offset);
2cab6cc3 10478
b6518b38 10479 value = relocation;
2cab6cc3 10480
99059e56
RM		 10481 if (value >= 0x1000)
10482 return bfd_reloc_overflow;
2cab6cc3
MS		 10483
10484 insn = (insn & 0xfb0f8f00) | (value & 0xff)
99059e56
RM		 10485 | ((value & 0x700) << 4)
10486 | ((value & 0x800) << 15);
10487 if (relocation < 0)
10488 insn |= 0xa00000;
2cab6cc3
MS		 10489
10490 bfd_put_16 (input_bfd, insn >> 16, hit_data);
10491 bfd_put_16 (input_bfd, insn & 0xffff, hit_data + 2);
10492
99059e56 10493 return bfd_reloc_ok;
2cab6cc3
MS		 10494 }
10495
e1ec24c6
NC		 10496 case R_ARM_THM_PC8:
10497 /* PR 10073: This reloc is not generated by the GNU toolchain,
10498 but it is supported for compatibility with third party libraries
10499 generated by other compilers, specifically the ARM/IAR. */
10500 {
10501 bfd_vma insn;
10502 bfd_signed_vma relocation;
10503
10504 insn = bfd_get_16 (input_bfd, hit_data);
10505
99059e56 10506 if (globals->use_rel)
79f08007 10507 addend = ((((insn & 0x00ff) << 2) + 4) & 0x3ff) -4;
e1ec24c6
NC		 10508
10509 relocation = value + addend;
79f08007 10510 relocation -= Pa (input_section->output_section->vma
99059e56
RM		 10511 + input_section->output_offset
10512 + rel->r_offset);
e1ec24c6 10513
b6518b38 10514 value = relocation;
e1ec24c6
NC		 10515
10516 /* We do not check for overflow of this reloc. Although strictly
10517 speaking this is incorrect, it appears to be necessary in order
10518 to work with IAR generated relocs. Since GCC and GAS do not
10519 generate R_ARM_THM_PC8 relocs, the lack of a check should not be
10520 a problem for them. */
10521 value &= 0x3fc;
10522
10523 insn = (insn & 0xff00) | (value >> 2);
10524
10525 bfd_put_16 (input_bfd, insn, hit_data);
10526
99059e56 10527 return bfd_reloc_ok;
e1ec24c6
NC		 10528 }
10529
2cab6cc3
MS		 10530 case R_ARM_THM_PC12:
10531 /* Corresponds to: ldr.w reg, [pc, #offset]. */
10532 {
10533 bfd_vma insn;
10534 bfd_signed_vma relocation;
10535
10536 insn = (bfd_get_16 (input_bfd, hit_data) << 16)
99059e56 10537 | bfd_get_16 (input_bfd, hit_data + 2);
2cab6cc3 10538
99059e56
RM		 10539 if (globals->use_rel)
10540 {
10541 signed_addend = insn & 0xfff;
10542 if (!(insn & (1 << 23)))
10543 signed_addend = -signed_addend;
10544 }
2cab6cc3
MS		 10545
10546 relocation = value + signed_addend;
79f08007 10547 relocation -= Pa (input_section->output_section->vma
99059e56
RM		 10548 + input_section->output_offset
10549 + rel->r_offset);
2cab6cc3 10550
b6518b38 10551 value = relocation;
2cab6cc3 10552
99059e56
RM		 10553 if (value >= 0x1000)
10554 return bfd_reloc_overflow;
2cab6cc3
MS		 10555
10556 insn = (insn & 0xff7ff000) | value;
99059e56
RM		 10557 if (relocation >= 0)
10558 insn |= (1 << 23);
2cab6cc3
MS		 10559
10560 bfd_put_16 (input_bfd, insn >> 16, hit_data);
10561 bfd_put_16 (input_bfd, insn & 0xffff, hit_data + 2);
10562
99059e56 10563 return bfd_reloc_ok;
2cab6cc3
MS		 10564 }
10565
dfc5f959 10566 case R_ARM_THM_XPC22:
c19d1205 10567 case R_ARM_THM_CALL:
bd97cb95 10568 case R_ARM_THM_JUMP24:
dfc5f959 10569 /* Thumb BL (branch long instruction). */
252b5132 10570 {
b34976b6 10571 bfd_vma relocation;
99059e56 10572 bfd_vma reloc_sign;
b34976b6
AM		 10573 bfd_boolean overflow = FALSE;
10574 bfd_vma upper_insn = bfd_get_16 (input_bfd, hit_data);
10575 bfd_vma lower_insn = bfd_get_16 (input_bfd, hit_data + 2);
e95de063
MS		 10576 bfd_signed_vma reloc_signed_max;
10577 bfd_signed_vma reloc_signed_min;
b34976b6 10578 bfd_vma check;
252b5132 10579 bfd_signed_vma signed_check;
e95de063 10580 int bitsize;
cd1dac3d 10581 const int thumb2 = using_thumb2 (globals);
5e866f5a 10582 const int thumb2_bl = using_thumb2_bl (globals);
252b5132 10583
5ab79981 10584 /* A branch to an undefined weak symbol is turned into a jump to
cd1dac3d
DG		 10585 the next instruction unless a PLT entry will be created.
10586 The jump to the next instruction is optimized as a NOP.W for
10587 Thumb-2 enabled architectures. */
19540007 10588 if (h && h->root.type == bfd_link_hash_undefweak
34e77a92 10589 && plt_offset == (bfd_vma) -1)
5ab79981 10590 {
60a019a0 10591 if (thumb2)
cd1dac3d
DG		 10592 {
10593 bfd_put_16 (input_bfd, 0xf3af, hit_data);
10594 bfd_put_16 (input_bfd, 0x8000, hit_data + 2);
10595 }
10596 else
10597 {
10598 bfd_put_16 (input_bfd, 0xe000, hit_data);
10599 bfd_put_16 (input_bfd, 0xbf00, hit_data + 2);
10600 }
5ab79981
PB		 10601 return bfd_reloc_ok;
10602 }
10603
e95de063 10604 /* Fetch the addend. We use the Thumb-2 encoding (backwards compatible
99059e56 10605 with Thumb-1) involving the J1 and J2 bits. */
4e7fd91e
PB		 10606 if (globals->use_rel)
10607 {
99059e56
RM		 10608 bfd_vma s = (upper_insn & (1 << 10)) >> 10;
10609 bfd_vma upper = upper_insn & 0x3ff;
10610 bfd_vma lower = lower_insn & 0x7ff;
e95de063
MS		 10611 bfd_vma j1 = (lower_insn & (1 << 13)) >> 13;
10612 bfd_vma j2 = (lower_insn & (1 << 11)) >> 11;
99059e56
RM		 10613 bfd_vma i1 = j1 ^ s ? 0 : 1;
10614 bfd_vma i2 = j2 ^ s ? 0 : 1;
e95de063 10615
99059e56
RM		 10616 addend = (i1 << 23) | (i2 << 22) | (upper << 12) | (lower << 1);
10617 /* Sign extend. */
10618 addend = (addend | ((s ? 0 : 1) << 24)) - (1 << 24);
e95de063 10619
4e7fd91e
PB		 10620 signed_addend = addend;
10621 }
cb1afa5c 10622
dfc5f959
NC		 10623 if (r_type == R_ARM_THM_XPC22)
10624 {
10625 /* Check for Thumb to Thumb call. */
10626 /* FIXME: Should we translate the instruction into a BL
10627 instruction instead ? */
35fc36a8 10628 if (branch_type == ST_BRANCH_TO_THUMB)
d003868e
AM		 10629 (*_bfd_error_handler)
10630 (_("%B: Warning: Thumb BLX instruction targets thumb function '%s'."),
10631 input_bfd,
10632 h ? h->root.root.string : "(local)");
dfc5f959
NC		 10633 }
10634 else
252b5132 10635 {
dfc5f959
NC		 10636 /* If it is not a call to Thumb, assume call to Arm.
10637 If it is a call relative to a section name, then it is not a
b7693d02
DJ		 10638 function call at all, but rather a long jump. Calls through
10639 the PLT do not require stubs. */
34e77a92 10640 if (branch_type == ST_BRANCH_TO_ARM && plt_offset == (bfd_vma) -1)
dfc5f959 10641 {
bd97cb95 10642 if (globals->use_blx && r_type == R_ARM_THM_CALL)
39b41c9c
PB		 10643 {
10644 /* Convert BL to BLX. */
10645 lower_insn = (lower_insn & ~0x1000) | 0x0800;
10646 }
155d87d7
CL		 10647 else if (( r_type != R_ARM_THM_CALL)
10648 && (r_type != R_ARM_THM_JUMP24))
8029a119
NC		 10649 {
10650 if (elf32_thumb_to_arm_stub
10651 (info, sym_name, input_bfd, output_bfd, input_section,
10652 hit_data, sym_sec, rel->r_offset, signed_addend, value,
10653 error_message))
10654 return bfd_reloc_ok;
10655 else
10656 return bfd_reloc_dangerous;
10657 }
da5938a2 10658 }
35fc36a8
RS		 10659 else if (branch_type == ST_BRANCH_TO_THUMB
10660 && globals->use_blx
bd97cb95 10661 && r_type == R_ARM_THM_CALL)
39b41c9c
PB		 10662 {
10663 /* Make sure this is a BL. */
10664 lower_insn |= 0x1800;
10665 }
252b5132 10666 }
f21f3fe0 10667
fe33d2fa 10668 enum elf32_arm_stub_type stub_type = arm_stub_none;
155d87d7 10669 if (r_type == R_ARM_THM_CALL || r_type == R_ARM_THM_JUMP24)
906e58ca
NC		 10670 {
10671 /* Check if a stub has to be inserted because the destination
8029a119 10672 is too far. */
fe33d2fa
CL		 10673 struct elf32_arm_stub_hash_entry *stub_entry;
10674 struct elf32_arm_link_hash_entry *hash;
10675
10676 hash = (struct elf32_arm_link_hash_entry *) h;
10677
10678 stub_type = arm_type_of_stub (info, input_section, rel,
34e77a92
RS		 10679 st_type, &branch_type,
10680 hash, value, sym_sec,
fe33d2fa
CL		 10681 input_bfd, sym_name);
10682
10683 if (stub_type != arm_stub_none)
906e58ca
NC		 10684 {
10685 /* The target is out of reach or we are changing modes, so
10686 redirect the branch to the local stub for this
10687 function. */
10688 stub_entry = elf32_arm_get_stub_entry (input_section,
10689 sym_sec, h,
fe33d2fa
CL		 10690 rel, globals,
10691 stub_type);
906e58ca 10692 if (stub_entry != NULL)
9cd3e4e5
NC		 10693 {
10694 value = (stub_entry->stub_offset
10695 + stub_entry->stub_sec->output_offset
10696 + stub_entry->stub_sec->output_section->vma);
10697
10698 if (plt_offset != (bfd_vma) -1)
10699 *unresolved_reloc_p = FALSE;
10700 }
906e58ca 10701
f4ac8484 10702 /* If this call becomes a call to Arm, force BLX. */
155d87d7 10703 if (globals->use_blx && (r_type == R_ARM_THM_CALL))
f4ac8484
DJ		 10704 {
10705 if ((stub_entry
10706 && !arm_stub_is_thumb (stub_entry->stub_type))
35fc36a8 10707 || branch_type != ST_BRANCH_TO_THUMB)
f4ac8484
DJ		 10708 lower_insn = (lower_insn & ~0x1000) | 0x0800;
10709 }
906e58ca
NC		 10710 }
10711 }
10712
fe33d2fa 10713 /* Handle calls via the PLT. */
34e77a92 10714 if (stub_type == arm_stub_none && plt_offset != (bfd_vma) -1)
fe33d2fa
CL		 10715 {
10716 value = (splt->output_section->vma
10717 + splt->output_offset
34e77a92 10718 + plt_offset);
fe33d2fa 10719
eed94f8f
NC		 10720 if (globals->use_blx
10721 && r_type == R_ARM_THM_CALL
10722 && ! using_thumb_only (globals))
fe33d2fa
CL		 10723 {
10724 /* If the Thumb BLX instruction is available, convert
10725 the BL to a BLX instruction to call the ARM-mode
10726 PLT entry. */
10727 lower_insn = (lower_insn & ~0x1000) | 0x0800;
35fc36a8 10728 branch_type = ST_BRANCH_TO_ARM;
fe33d2fa
CL		 10729 }
10730 else
10731 {
eed94f8f
NC		 10732 if (! using_thumb_only (globals))
10733 /* Target the Thumb stub before the ARM PLT entry. */
10734 value -= PLT_THUMB_STUB_SIZE;
35fc36a8 10735 branch_type = ST_BRANCH_TO_THUMB;
fe33d2fa
CL		 10736 }
10737 *unresolved_reloc_p = FALSE;
10738 }
10739
ba96a88f 10740 relocation = value + signed_addend;
f21f3fe0 10741
252b5132 10742 relocation -= (input_section->output_section->vma
ba96a88f
NC		 10743 + input_section->output_offset
10744 + rel->r_offset);
9a5aca8c 10745
252b5132
RH		 10746 check = relocation >> howto->rightshift;
10747
10748 /* If this is a signed value, the rightshift just dropped
10749 leading 1 bits (assuming twos complement). */
10750 if ((bfd_signed_vma) relocation >= 0)
10751 signed_check = check;
10752 else
10753 signed_check = check | ~((bfd_vma) -1 >> howto->rightshift);
10754
e95de063
MS		 10755 /* Calculate the permissable maximum and minimum values for
10756 this relocation according to whether we're relocating for
10757 Thumb-2 or not. */
10758 bitsize = howto->bitsize;
5e866f5a 10759 if (!thumb2_bl)
e95de063 10760 bitsize -= 2;
f6ebfac0 10761 reloc_signed_max = (1 << (bitsize - 1)) - 1;
e95de063
MS		 10762 reloc_signed_min = ~reloc_signed_max;
10763
252b5132 10764 /* Assumes two's complement. */
ba96a88f 10765 if (signed_check > reloc_signed_max || signed_check < reloc_signed_min)
b34976b6 10766 overflow = TRUE;
252b5132 10767
bd97cb95 10768 if ((lower_insn & 0x5000) == 0x4000)
c62e1cc3
NC		 10769 /* For a BLX instruction, make sure that the relocation is rounded up
10770 to a word boundary. This follows the semantics of the instruction
10771 which specifies that bit 1 of the target address will come from bit
10772 1 of the base address. */
10773 relocation = (relocation + 2) & ~ 3;
cb1afa5c 10774
e95de063
MS		 10775 /* Put RELOCATION back into the insn. Assumes two's complement.
10776 We use the Thumb-2 encoding, which is safe even if dealing with
10777 a Thumb-1 instruction by virtue of our overflow check above. */
99059e56 10778 reloc_sign = (signed_check < 0) ? 1 : 0;
e95de063 10779 upper_insn = (upper_insn & ~(bfd_vma) 0x7ff)
99059e56
RM		 10780 | ((relocation >> 12) & 0x3ff)
10781 | (reloc_sign << 10);
906e58ca 10782 lower_insn = (lower_insn & ~(bfd_vma) 0x2fff)
99059e56
RM		 10783 | (((!((relocation >> 23) & 1)) ^ reloc_sign) << 13)
10784 | (((!((relocation >> 22) & 1)) ^ reloc_sign) << 11)
10785 | ((relocation >> 1) & 0x7ff);
c62e1cc3 10786
252b5132
RH		 10787 /* Put the relocated value back in the object file: */
10788 bfd_put_16 (input_bfd, upper_insn, hit_data);
10789 bfd_put_16 (input_bfd, lower_insn, hit_data + 2);
10790
10791 return (overflow ? bfd_reloc_overflow : bfd_reloc_ok);
10792 }
10793 break;
10794
c19d1205
ZW		 10795 case R_ARM_THM_JUMP19:
10796 /* Thumb32 conditional branch instruction. */
10797 {
10798 bfd_vma relocation;
10799 bfd_boolean overflow = FALSE;
10800 bfd_vma upper_insn = bfd_get_16 (input_bfd, hit_data);
10801 bfd_vma lower_insn = bfd_get_16 (input_bfd, hit_data + 2);
a00a1f35
MS		 10802 bfd_signed_vma reloc_signed_max = 0xffffe;
10803 bfd_signed_vma reloc_signed_min = -0x100000;
c19d1205 10804 bfd_signed_vma signed_check;
c5423981
TG		 10805 enum elf32_arm_stub_type stub_type = arm_stub_none;
10806 struct elf32_arm_stub_hash_entry *stub_entry;
10807 struct elf32_arm_link_hash_entry *hash;
c19d1205
ZW		 10808
10809 /* Need to refetch the addend, reconstruct the top three bits,
10810 and squish the two 11 bit pieces together. */
10811 if (globals->use_rel)
10812 {
10813 bfd_vma S = (upper_insn & 0x0400) >> 10;
a00a1f35 10814 bfd_vma upper = (upper_insn & 0x003f);
c19d1205
ZW		 10815 bfd_vma J1 = (lower_insn & 0x2000) >> 13;
10816 bfd_vma J2 = (lower_insn & 0x0800) >> 11;
10817 bfd_vma lower = (lower_insn & 0x07ff);
10818
a00a1f35
MS		 10819 upper |= J1 << 6;
10820 upper |= J2 << 7;
10821 upper |= (!S) << 8;
c19d1205
ZW		 10822 upper -= 0x0100; /* Sign extend. */
10823
10824 addend = (upper << 12) | (lower << 1);
10825 signed_addend = addend;
10826 }
10827
bd97cb95 10828 /* Handle calls via the PLT. */
34e77a92 10829 if (plt_offset != (bfd_vma) -1)
bd97cb95
DJ		 10830 {
10831 value = (splt->output_section->vma
10832 + splt->output_offset
34e77a92 10833 + plt_offset);
bd97cb95
DJ		 10834 /* Target the Thumb stub before the ARM PLT entry. */
10835 value -= PLT_THUMB_STUB_SIZE;
10836 *unresolved_reloc_p = FALSE;
10837 }
10838
c5423981
TG		 10839 hash = (struct elf32_arm_link_hash_entry *)h;
10840
10841 stub_type = arm_type_of_stub (info, input_section, rel,
10842 st_type, &branch_type,
10843 hash, value, sym_sec,
10844 input_bfd, sym_name);
10845 if (stub_type != arm_stub_none)
10846 {
10847 stub_entry = elf32_arm_get_stub_entry (input_section,
10848 sym_sec, h,
10849 rel, globals,
10850 stub_type);
10851 if (stub_entry != NULL)
10852 {
10853 value = (stub_entry->stub_offset
10854 + stub_entry->stub_sec->output_offset
10855 + stub_entry->stub_sec->output_section->vma);
10856 }
10857 }
c19d1205 10858
99059e56 10859 relocation = value + signed_addend;
c19d1205
ZW		 10860 relocation -= (input_section->output_section->vma
10861 + input_section->output_offset
10862 + rel->r_offset);
a00a1f35 10863 signed_check = (bfd_signed_vma) relocation;
c19d1205 10864
c19d1205
ZW		 10865 if (signed_check > reloc_signed_max || signed_check < reloc_signed_min)
10866 overflow = TRUE;
10867
10868 /* Put RELOCATION back into the insn. */
10869 {
10870 bfd_vma S = (relocation & 0x00100000) >> 20;
10871 bfd_vma J2 = (relocation & 0x00080000) >> 19;
10872 bfd_vma J1 = (relocation & 0x00040000) >> 18;
10873 bfd_vma hi = (relocation & 0x0003f000) >> 12;
10874 bfd_vma lo = (relocation & 0x00000ffe) >> 1;
10875
a00a1f35 10876 upper_insn = (upper_insn & 0xfbc0) | (S << 10) | hi;
c19d1205
ZW		 10877 lower_insn = (lower_insn & 0xd000) | (J1 << 13) | (J2 << 11) | lo;
10878 }
10879
10880 /* Put the relocated value back in the object file: */
10881 bfd_put_16 (input_bfd, upper_insn, hit_data);
10882 bfd_put_16 (input_bfd, lower_insn, hit_data + 2);
10883
10884 return (overflow ? bfd_reloc_overflow : bfd_reloc_ok);
10885 }
10886
10887 case R_ARM_THM_JUMP11:
10888 case R_ARM_THM_JUMP8:
10889 case R_ARM_THM_JUMP6:
51c5503b
NC		 10890 /* Thumb B (branch) instruction). */
10891 {
6cf9e9fe 10892 bfd_signed_vma relocation;
51c5503b
NC		 10893 bfd_signed_vma reloc_signed_max = (1 << (howto->bitsize - 1)) - 1;
10894 bfd_signed_vma reloc_signed_min = ~ reloc_signed_max;
51c5503b
NC		 10895 bfd_signed_vma signed_check;
10896
c19d1205
ZW		 10897 /* CZB cannot jump backward. */
10898 if (r_type == R_ARM_THM_JUMP6)
10899 reloc_signed_min = 0;
10900
4e7fd91e 10901 if (globals->use_rel)
6cf9e9fe 10902 {
4e7fd91e
PB		 10903 /* Need to refetch addend. */
10904 addend = bfd_get_16 (input_bfd, hit_data) & howto->src_mask;
10905 if (addend & ((howto->src_mask + 1) >> 1))
10906 {
10907 signed_addend = -1;
10908 signed_addend &= ~ howto->src_mask;
10909 signed_addend |= addend;
10910 }
10911 else
10912 signed_addend = addend;
10913 /* The value in the insn has been right shifted. We need to
10914 undo this, so that we can perform the address calculation
10915 in terms of bytes. */
10916 signed_addend <<= howto->rightshift;
6cf9e9fe 10917 }
6cf9e9fe 10918 relocation = value + signed_addend;
51c5503b
NC		 10919
10920 relocation -= (input_section->output_section->vma
10921 + input_section->output_offset
10922 + rel->r_offset);
10923
6cf9e9fe
NC		 10924 relocation >>= howto->rightshift;
10925 signed_check = relocation;
c19d1205
ZW		 10926
10927 if (r_type == R_ARM_THM_JUMP6)
10928 relocation = ((relocation & 0x0020) << 4) | ((relocation & 0x001f) << 3);
10929 else
10930 relocation &= howto->dst_mask;
51c5503b 10931 relocation |= (bfd_get_16 (input_bfd, hit_data) & (~ howto->dst_mask));
cedb70c5 10932
51c5503b
NC		 10933 bfd_put_16 (input_bfd, relocation, hit_data);
10934
10935 /* Assumes two's complement. */
10936 if (signed_check > reloc_signed_max || signed_check < reloc_signed_min)
10937 return bfd_reloc_overflow;
10938
10939 return bfd_reloc_ok;
10940 }
cedb70c5 10941
8375c36b
PB		 10942 case R_ARM_ALU_PCREL7_0:
10943 case R_ARM_ALU_PCREL15_8:
10944 case R_ARM_ALU_PCREL23_15:
10945 {
10946 bfd_vma insn;
10947 bfd_vma relocation;
10948
10949 insn = bfd_get_32 (input_bfd, hit_data);
4e7fd91e
PB		 10950 if (globals->use_rel)
10951 {
10952 /* Extract the addend. */
10953 addend = (insn & 0xff) << ((insn & 0xf00) >> 7);
10954 signed_addend = addend;
10955 }
8375c36b
PB		 10956 relocation = value + signed_addend;
10957
10958 relocation -= (input_section->output_section->vma
10959 + input_section->output_offset
10960 + rel->r_offset);
10961 insn = (insn & ~0xfff)
10962 | ((howto->bitpos << 7) & 0xf00)
10963 | ((relocation >> howto->bitpos) & 0xff);
10964 bfd_put_32 (input_bfd, value, hit_data);
10965 }
10966 return bfd_reloc_ok;
10967
252b5132
RH		 10968 case R_ARM_GNU_VTINHERIT:
10969 case R_ARM_GNU_VTENTRY:
10970 return bfd_reloc_ok;
10971
c19d1205 10972 case R_ARM_GOTOFF32:
252b5132 10973 /* Relocation is relative to the start of the
99059e56 10974 global offset table. */
252b5132
RH		 10975
10976 BFD_ASSERT (sgot != NULL);
10977 if (sgot == NULL)
99059e56 10978 return bfd_reloc_notsupported;
9a5aca8c 10979
cedb70c5 10980 /* If we are addressing a Thumb function, we need to adjust the
ee29b9fb
RE		 10981 address by one, so that attempts to call the function pointer will
10982 correctly interpret it as Thumb code. */
35fc36a8 10983 if (branch_type == ST_BRANCH_TO_THUMB)
ee29b9fb
RE		 10984 value += 1;
10985
252b5132 10986 /* Note that sgot->output_offset is not involved in this
99059e56
RM		 10987 calculation. We always want the start of .got. If we
10988 define _GLOBAL_OFFSET_TABLE in a different way, as is
10989 permitted by the ABI, we might have to change this
10990 calculation. */
252b5132 10991 value -= sgot->output_section->vma;
f21f3fe0 10992 return _bfd_final_link_relocate (howto, input_bfd, input_section,
99e4ae17 10993 contents, rel->r_offset, value,
00a97672 10994 rel->r_addend);
252b5132
RH		 10995
10996 case R_ARM_GOTPC:
a7c10850 10997 /* Use global offset table as symbol value. */
252b5132 10998 BFD_ASSERT (sgot != NULL);
f21f3fe0 10999
252b5132 11000 if (sgot == NULL)
99059e56 11001 return bfd_reloc_notsupported;
252b5132 11002
0945cdfd 11003 *unresolved_reloc_p = FALSE;
252b5132 11004 value = sgot->output_section->vma;
f21f3fe0 11005 return _bfd_final_link_relocate (howto, input_bfd, input_section,
99e4ae17 11006 contents, rel->r_offset, value,
00a97672 11007 rel->r_addend);
f21f3fe0 11008
252b5132 11009 case R_ARM_GOT32:
eb043451 11010 case R_ARM_GOT_PREL:
252b5132 11011 /* Relocation is to the entry for this symbol in the
99059e56 11012 global offset table. */
252b5132
RH		 11013 if (sgot == NULL)
11014 return bfd_reloc_notsupported;
f21f3fe0 11015
34e77a92
RS		 11016 if (dynreloc_st_type == STT_GNU_IFUNC
11017 && plt_offset != (bfd_vma) -1
11018 && (h == NULL || SYMBOL_REFERENCES_LOCAL (info, h)))
11019 {
11020 /* We have a relocation against a locally-binding STT_GNU_IFUNC
11021 symbol, and the relocation resolves directly to the runtime
11022 target rather than to the .iplt entry. This means that any
11023 .got entry would be the same value as the .igot.plt entry,
11024 so there's no point creating both. */
11025 sgot = globals->root.igotplt;
11026 value = sgot->output_offset + gotplt_offset;
11027 }
11028 else if (h != NULL)
252b5132
RH		 11029 {
11030 bfd_vma off;
f21f3fe0 11031
252b5132
RH		 11032 off = h->got.offset;
11033 BFD_ASSERT (off != (bfd_vma) -1);
b436d854 11034 if ((off & 1) != 0)
252b5132 11035 {
b436d854
RS		 11036 /* We have already processsed one GOT relocation against
11037 this symbol. */
11038 off &= ~1;
11039 if (globals->root.dynamic_sections_created
11040 && !SYMBOL_REFERENCES_LOCAL (info, h))
11041 *unresolved_reloc_p = FALSE;
11042 }
11043 else
11044 {
11045 Elf_Internal_Rela outrel;
11046
6f820c85 11047 if (h->dynindx != -1 && !SYMBOL_REFERENCES_LOCAL (info, h))
b436d854
RS		 11048 {
11049 /* If the symbol doesn't resolve locally in a static
11050 object, we have an undefined reference. If the
11051 symbol doesn't resolve locally in a dynamic object,
11052 it should be resolved by the dynamic linker. */
11053 if (globals->root.dynamic_sections_created)
11054 {
11055 outrel.r_info = ELF32_R_INFO (h->dynindx, R_ARM_GLOB_DAT);
11056 *unresolved_reloc_p = FALSE;
11057 }
11058 else
11059 outrel.r_info = 0;
11060 outrel.r_addend = 0;
11061 }
252b5132
RH		 11062 else
11063 {
34e77a92 11064 if (dynreloc_st_type == STT_GNU_IFUNC)
99059e56 11065 outrel.r_info = ELF32_R_INFO (0, R_ARM_IRELATIVE);
0e1862bb 11066 else if (bfd_link_pic (info) &&
31943882
WN		 11067 (ELF_ST_VISIBILITY (h->other) == STV_DEFAULT
11068 || h->root.type != bfd_link_hash_undefweak))
99059e56
RM		 11069 outrel.r_info = ELF32_R_INFO (0, R_ARM_RELATIVE);
11070 else
11071 outrel.r_info = 0;
34e77a92 11072 outrel.r_addend = dynreloc_value;
b436d854 11073 }
ee29b9fb 11074
b436d854
RS		 11075 /* The GOT entry is initialized to zero by default.
11076 See if we should install a different value. */
11077 if (outrel.r_addend != 0
11078 && (outrel.r_info == 0 || globals->use_rel))
11079 {
11080 bfd_put_32 (output_bfd, outrel.r_addend,
11081 sgot->contents + off);
11082 outrel.r_addend = 0;
252b5132 11083 }
f21f3fe0 11084
b436d854
RS		 11085 if (outrel.r_info != 0)
11086 {
11087 outrel.r_offset = (sgot->output_section->vma
11088 + sgot->output_offset
11089 + off);
11090 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
11091 }
11092 h->got.offset |= 1;
11093 }
252b5132
RH		 11094 value = sgot->output_offset + off;
11095 }
11096 else
11097 {
11098 bfd_vma off;
f21f3fe0 11099
252b5132
RH		 11100 BFD_ASSERT (local_got_offsets != NULL &&
11101 local_got_offsets[r_symndx] != (bfd_vma) -1);
f21f3fe0 11102
252b5132 11103 off = local_got_offsets[r_symndx];
f21f3fe0 11104
252b5132
RH		 11105 /* The offset must always be a multiple of 4. We use the
11106 least significant bit to record whether we have already
9b485d32 11107 generated the necessary reloc. */
252b5132
RH		 11108 if ((off & 1) != 0)
11109 off &= ~1;
11110 else
11111 {
00a97672 11112 if (globals->use_rel)
34e77a92 11113 bfd_put_32 (output_bfd, dynreloc_value, sgot->contents + off);
f21f3fe0 11114
0e1862bb 11115 if (bfd_link_pic (info) || dynreloc_st_type == STT_GNU_IFUNC)
252b5132 11116 {
947216bf 11117 Elf_Internal_Rela outrel;
f21f3fe0 11118
34e77a92 11119 outrel.r_addend = addend + dynreloc_value;
252b5132 11120 outrel.r_offset = (sgot->output_section->vma
f21f3fe0 11121 + sgot->output_offset
252b5132 11122 + off);
34e77a92 11123 if (dynreloc_st_type == STT_GNU_IFUNC)
99059e56 11124 outrel.r_info = ELF32_R_INFO (0, R_ARM_IRELATIVE);
34e77a92
RS		 11125 else
11126 outrel.r_info = ELF32_R_INFO (0, R_ARM_RELATIVE);
47beaa6a 11127 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
252b5132 11128 }
f21f3fe0 11129
252b5132
RH		 11130 local_got_offsets[r_symndx] |= 1;
11131 }
f21f3fe0 11132
252b5132
RH		 11133 value = sgot->output_offset + off;
11134 }
eb043451
PB		 11135 if (r_type != R_ARM_GOT32)
11136 value += sgot->output_section->vma;
9a5aca8c 11137
f21f3fe0 11138 return _bfd_final_link_relocate (howto, input_bfd, input_section,
99e4ae17 11139 contents, rel->r_offset, value,
00a97672 11140 rel->r_addend);
f21f3fe0 11141
ba93b8ac
DJ		 11142 case R_ARM_TLS_LDO32:
11143 value = value - dtpoff_base (info);
11144
11145 return _bfd_final_link_relocate (howto, input_bfd, input_section,
00a97672
RS		 11146 contents, rel->r_offset, value,
11147 rel->r_addend);
ba93b8ac
DJ		 11148
11149 case R_ARM_TLS_LDM32:
11150 {
11151 bfd_vma off;
11152
362d30a1 11153 if (sgot == NULL)
ba93b8ac
DJ		 11154 abort ();
11155
11156 off = globals->tls_ldm_got.offset;
11157
11158 if ((off & 1) != 0)
11159 off &= ~1;
11160 else
11161 {
11162 /* If we don't know the module number, create a relocation
11163 for it. */
0e1862bb 11164 if (bfd_link_pic (info))
ba93b8ac
DJ		 11165 {
11166 Elf_Internal_Rela outrel;
ba93b8ac 11167
362d30a1 11168 if (srelgot == NULL)
ba93b8ac
DJ		 11169 abort ();
11170
00a97672 11171 outrel.r_addend = 0;
362d30a1
RS		 11172 outrel.r_offset = (sgot->output_section->vma
11173 + sgot->output_offset + off);
ba93b8ac
DJ		 11174 outrel.r_info = ELF32_R_INFO (0, R_ARM_TLS_DTPMOD32);
11175
00a97672
RS		 11176 if (globals->use_rel)
11177 bfd_put_32 (output_bfd, outrel.r_addend,
362d30a1 11178 sgot->contents + off);
ba93b8ac 11179
47beaa6a 11180 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
ba93b8ac
DJ		 11181 }
11182 else
362d30a1 11183 bfd_put_32 (output_bfd, 1, sgot->contents + off);
ba93b8ac
DJ		 11184
11185 globals->tls_ldm_got.offset |= 1;
11186 }
11187
362d30a1 11188 value = sgot->output_section->vma + sgot->output_offset + off
ba93b8ac
DJ		 11189 - (input_section->output_section->vma + input_section->output_offset + rel->r_offset);
11190
11191 return _bfd_final_link_relocate (howto, input_bfd, input_section,
11192 contents, rel->r_offset, value,
00a97672 11193 rel->r_addend);
ba93b8ac
DJ		 11194 }
11195
0855e32b
NS		 11196 case R_ARM_TLS_CALL:
11197 case R_ARM_THM_TLS_CALL:
ba93b8ac
DJ		 11198 case R_ARM_TLS_GD32:
11199 case R_ARM_TLS_IE32:
0855e32b
NS		 11200 case R_ARM_TLS_GOTDESC:
11201 case R_ARM_TLS_DESCSEQ:
11202 case R_ARM_THM_TLS_DESCSEQ:
ba93b8ac 11203 {
0855e32b
NS		 11204 bfd_vma off, offplt;
11205 int indx = 0;
ba93b8ac
DJ		 11206 char tls_type;
11207
0855e32b 11208 BFD_ASSERT (sgot != NULL);
ba93b8ac 11209
ba93b8ac
DJ		 11210 if (h != NULL)
11211 {
11212 bfd_boolean dyn;
11213 dyn = globals->root.dynamic_sections_created;
0e1862bb
L		 11214 if (WILL_CALL_FINISH_DYNAMIC_SYMBOL (dyn,
11215 bfd_link_pic (info),
11216 h)
11217 && (!bfd_link_pic (info)
ba93b8ac
DJ		 11218 || !SYMBOL_REFERENCES_LOCAL (info, h)))
11219 {
11220 *unresolved_reloc_p = FALSE;
11221 indx = h->dynindx;
11222 }
11223 off = h->got.offset;
0855e32b 11224 offplt = elf32_arm_hash_entry (h)->tlsdesc_got;
ba93b8ac
DJ		 11225 tls_type = ((struct elf32_arm_link_hash_entry *) h)->tls_type;
11226 }
11227 else
11228 {
0855e32b 11229 BFD_ASSERT (local_got_offsets != NULL);
ba93b8ac 11230 off = local_got_offsets[r_symndx];
0855e32b 11231 offplt = local_tlsdesc_gotents[r_symndx];
ba93b8ac
DJ		 11232 tls_type = elf32_arm_local_got_tls_type (input_bfd)[r_symndx];
11233 }
11234
0855e32b 11235 /* Linker relaxations happens from one of the
b38cadfb 11236 R_ARM_{GOTDESC,CALL,DESCSEQ} relocations to IE or LE. */
0855e32b 11237 if (ELF32_R_TYPE(rel->r_info) != r_type)
b38cadfb 11238 tls_type = GOT_TLS_IE;
0855e32b
NS		 11239
11240 BFD_ASSERT (tls_type != GOT_UNKNOWN);
ba93b8ac
DJ		 11241
11242 if ((off & 1) != 0)
11243 off &= ~1;
11244 else
11245 {
11246 bfd_boolean need_relocs = FALSE;
11247 Elf_Internal_Rela outrel;
ba93b8ac
DJ		 11248 int cur_off = off;
11249
11250 /* The GOT entries have not been initialized yet. Do it
11251 now, and emit any relocations. If both an IE GOT and a
11252 GD GOT are necessary, we emit the GD first. */
11253
0e1862bb 11254 if ((bfd_link_pic (info) || indx != 0)
ba93b8ac
DJ		 11255 && (h == NULL
11256 || ELF_ST_VISIBILITY (h->other) == STV_DEFAULT
11257 || h->root.type != bfd_link_hash_undefweak))
11258 {
11259 need_relocs = TRUE;
0855e32b 11260 BFD_ASSERT (srelgot != NULL);
ba93b8ac
DJ		 11261 }
11262
0855e32b
NS		 11263 if (tls_type & GOT_TLS_GDESC)
11264 {
47beaa6a
RS		 11265 bfd_byte *loc;
11266
0855e32b
NS		 11267 /* We should have relaxed, unless this is an undefined
11268 weak symbol. */
11269 BFD_ASSERT ((h && (h->root.type == bfd_link_hash_undefweak))
0e1862bb 11270 || bfd_link_pic (info));
0855e32b 11271 BFD_ASSERT (globals->sgotplt_jump_table_size + offplt + 8
99059e56 11272 <= globals->root.sgotplt->size);
0855e32b
NS		 11273
11274 outrel.r_addend = 0;
11275 outrel.r_offset = (globals->root.sgotplt->output_section->vma
11276 + globals->root.sgotplt->output_offset
11277 + offplt
11278 + globals->sgotplt_jump_table_size);
b38cadfb 11279
0855e32b
NS		 11280 outrel.r_info = ELF32_R_INFO (indx, R_ARM_TLS_DESC);
11281 sreloc = globals->root.srelplt;
11282 loc = sreloc->contents;
11283 loc += globals->next_tls_desc_index++ * RELOC_SIZE (globals);
11284 BFD_ASSERT (loc + RELOC_SIZE (globals)
99059e56 11285 <= sreloc->contents + sreloc->size);
0855e32b
NS		 11286
11287 SWAP_RELOC_OUT (globals) (output_bfd, &outrel, loc);
11288
11289 /* For globals, the first word in the relocation gets
11290 the relocation index and the top bit set, or zero,
11291 if we're binding now. For locals, it gets the
11292 symbol's offset in the tls section. */
99059e56 11293 bfd_put_32 (output_bfd,
0855e32b
NS		 11294 !h ? value - elf_hash_table (info)->tls_sec->vma
11295 : info->flags & DF_BIND_NOW ? 0
11296 : 0x80000000 | ELF32_R_SYM (outrel.r_info),
b38cadfb
NC		 11297 globals->root.sgotplt->contents + offplt
11298 + globals->sgotplt_jump_table_size);
11299
0855e32b 11300 /* Second word in the relocation is always zero. */
99059e56 11301 bfd_put_32 (output_bfd, 0,
b38cadfb
NC		 11302 globals->root.sgotplt->contents + offplt
11303 + globals->sgotplt_jump_table_size + 4);
0855e32b 11304 }
ba93b8ac
DJ		 11305 if (tls_type & GOT_TLS_GD)
11306 {
11307 if (need_relocs)
11308 {
00a97672 11309 outrel.r_addend = 0;
362d30a1
RS		 11310 outrel.r_offset = (sgot->output_section->vma
11311 + sgot->output_offset
00a97672 11312 + cur_off);
ba93b8ac 11313 outrel.r_info = ELF32_R_INFO (indx, R_ARM_TLS_DTPMOD32);
ba93b8ac 11314
00a97672
RS		 11315 if (globals->use_rel)
11316 bfd_put_32 (output_bfd, outrel.r_addend,
362d30a1 11317 sgot->contents + cur_off);
00a97672 11318
47beaa6a 11319 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
ba93b8ac
DJ		 11320
11321 if (indx == 0)
11322 bfd_put_32 (output_bfd, value - dtpoff_base (info),
362d30a1 11323 sgot->contents + cur_off + 4);
ba93b8ac
DJ		 11324 else
11325 {
00a97672 11326 outrel.r_addend = 0;
ba93b8ac
DJ		 11327 outrel.r_info = ELF32_R_INFO (indx,
11328 R_ARM_TLS_DTPOFF32);
11329 outrel.r_offset += 4;
00a97672
RS		 11330
11331 if (globals->use_rel)
11332 bfd_put_32 (output_bfd, outrel.r_addend,
362d30a1 11333 sgot->contents + cur_off + 4);
00a97672 11334
47beaa6a
RS		 11335 elf32_arm_add_dynreloc (output_bfd, info,
11336 srelgot, &outrel);
ba93b8ac
DJ		 11337 }
11338 }
11339 else
11340 {
11341 /* If we are not emitting relocations for a
11342 general dynamic reference, then we must be in a
11343 static link or an executable link with the
11344 symbol binding locally. Mark it as belonging
11345 to module 1, the executable. */
11346 bfd_put_32 (output_bfd, 1,
362d30a1 11347 sgot->contents + cur_off);
ba93b8ac 11348 bfd_put_32 (output_bfd, value - dtpoff_base (info),
362d30a1 11349 sgot->contents + cur_off + 4);
ba93b8ac
DJ		 11350 }
11351
11352 cur_off += 8;
11353 }
11354
11355 if (tls_type & GOT_TLS_IE)
11356 {
11357 if (need_relocs)
11358 {
00a97672
RS		 11359 if (indx == 0)
11360 outrel.r_addend = value - dtpoff_base (info);
11361 else
11362 outrel.r_addend = 0;
362d30a1
RS		 11363 outrel.r_offset = (sgot->output_section->vma
11364 + sgot->output_offset
ba93b8ac
DJ		 11365 + cur_off);
11366 outrel.r_info = ELF32_R_INFO (indx, R_ARM_TLS_TPOFF32);
11367
00a97672
RS		 11368 if (globals->use_rel)
11369 bfd_put_32 (output_bfd, outrel.r_addend,
362d30a1 11370 sgot->contents + cur_off);
ba93b8ac 11371
47beaa6a 11372 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
ba93b8ac
DJ		 11373 }
11374 else
11375 bfd_put_32 (output_bfd, tpoff (info, value),
362d30a1 11376 sgot->contents + cur_off);
ba93b8ac
DJ		 11377 cur_off += 4;
11378 }
11379
11380 if (h != NULL)
11381 h->got.offset |= 1;
11382 else
11383 local_got_offsets[r_symndx] |= 1;
11384 }
11385
11386 if ((tls_type & GOT_TLS_GD) && r_type != R_ARM_TLS_GD32)
11387 off += 8;
0855e32b
NS		 11388 else if (tls_type & GOT_TLS_GDESC)
11389 off = offplt;
11390
11391 if (ELF32_R_TYPE(rel->r_info) == R_ARM_TLS_CALL
11392 || ELF32_R_TYPE(rel->r_info) == R_ARM_THM_TLS_CALL)
11393 {
11394 bfd_signed_vma offset;
12352d3f
PB		 11395 /* TLS stubs are arm mode. The original symbol is a
11396 data object, so branch_type is bogus. */
11397 branch_type = ST_BRANCH_TO_ARM;
0855e32b 11398 enum elf32_arm_stub_type stub_type
34e77a92
RS		 11399 = arm_type_of_stub (info, input_section, rel,
11400 st_type, &branch_type,
0855e32b
NS		 11401 (struct elf32_arm_link_hash_entry *)h,
11402 globals->tls_trampoline, globals->root.splt,
11403 input_bfd, sym_name);
11404
11405 if (stub_type != arm_stub_none)
11406 {
11407 struct elf32_arm_stub_hash_entry *stub_entry
11408 = elf32_arm_get_stub_entry
11409 (input_section, globals->root.splt, 0, rel,
11410 globals, stub_type);
11411 offset = (stub_entry->stub_offset
11412 + stub_entry->stub_sec->output_offset
11413 + stub_entry->stub_sec->output_section->vma);
11414 }
11415 else
11416 offset = (globals->root.splt->output_section->vma
11417 + globals->root.splt->output_offset
11418 + globals->tls_trampoline);
11419
11420 if (ELF32_R_TYPE(rel->r_info) == R_ARM_TLS_CALL)
11421 {
11422 unsigned long inst;
b38cadfb
NC		 11423
11424 offset -= (input_section->output_section->vma
11425 + input_section->output_offset
11426 + rel->r_offset + 8);
0855e32b
NS		 11427
11428 inst = offset >> 2;
11429 inst &= 0x00ffffff;
11430 value = inst | (globals->use_blx ? 0xfa000000 : 0xeb000000);
11431 }
11432 else
11433 {
11434 /* Thumb blx encodes the offset in a complicated
11435 fashion. */
11436 unsigned upper_insn, lower_insn;
11437 unsigned neg;
11438
b38cadfb
NC		 11439 offset -= (input_section->output_section->vma
11440 + input_section->output_offset
0855e32b 11441 + rel->r_offset + 4);
b38cadfb 11442
12352d3f
PB		 11443 if (stub_type != arm_stub_none
11444 && arm_stub_is_thumb (stub_type))
11445 {
11446 lower_insn = 0xd000;
11447 }
11448 else
11449 {
11450 lower_insn = 0xc000;
6a631e86 11451 /* Round up the offset to a word boundary. */
12352d3f
PB		 11452 offset = (offset + 2) & ~2;
11453 }
11454
0855e32b
NS		 11455 neg = offset < 0;
11456 upper_insn = (0xf000
11457 | ((offset >> 12) & 0x3ff)
11458 | (neg << 10));
12352d3f 11459 lower_insn |= (((!((offset >> 23) & 1)) ^ neg) << 13)
0855e32b 11460 | (((!((offset >> 22) & 1)) ^ neg) << 11)
12352d3f 11461 | ((offset >> 1) & 0x7ff);
0855e32b
NS		 11462 bfd_put_16 (input_bfd, upper_insn, hit_data);
11463 bfd_put_16 (input_bfd, lower_insn, hit_data + 2);
11464 return bfd_reloc_ok;
11465 }
11466 }
11467 /* These relocations needs special care, as besides the fact
11468 they point somewhere in .gotplt, the addend must be
11469 adjusted accordingly depending on the type of instruction
6a631e86 11470 we refer to. */
0855e32b
NS		 11471 else if ((r_type == R_ARM_TLS_GOTDESC) && (tls_type & GOT_TLS_GDESC))
11472 {
11473 unsigned long data, insn;
11474 unsigned thumb;
b38cadfb 11475
0855e32b
NS		 11476 data = bfd_get_32 (input_bfd, hit_data);
11477 thumb = data & 1;
11478 data &= ~1u;
b38cadfb 11479
0855e32b
NS		 11480 if (thumb)
11481 {
11482 insn = bfd_get_16 (input_bfd, contents + rel->r_offset - data);
11483 if ((insn & 0xf000) == 0xf000 || (insn & 0xf800) == 0xe800)
11484 insn = (insn << 16)
11485 | bfd_get_16 (input_bfd,
11486 contents + rel->r_offset - data + 2);
11487 if ((insn & 0xf800c000) == 0xf000c000)
11488 /* bl/blx */
11489 value = -6;
11490 else if ((insn & 0xffffff00) == 0x4400)
11491 /* add */
11492 value = -5;
11493 else
11494 {
11495 (*_bfd_error_handler)
11496 (_("%B(%A+0x%lx):unexpected Thumb instruction '0x%x' referenced by TLS_GOTDESC"),
11497 input_bfd, input_section,
11498 (unsigned long)rel->r_offset, insn);
11499 return bfd_reloc_notsupported;
11500 }
11501 }
11502 else
11503 {
11504 insn = bfd_get_32 (input_bfd, contents + rel->r_offset - data);
11505
11506 switch (insn >> 24)
11507 {
11508 case 0xeb: /* bl */
11509 case 0xfa: /* blx */
11510 value = -4;
11511 break;
11512
11513 case 0xe0: /* add */
11514 value = -8;
11515 break;
b38cadfb 11516
0855e32b
NS		 11517 default:
11518 (*_bfd_error_handler)
11519 (_("%B(%A+0x%lx):unexpected ARM instruction '0x%x' referenced by TLS_GOTDESC"),
11520 input_bfd, input_section,
11521 (unsigned long)rel->r_offset, insn);
11522 return bfd_reloc_notsupported;
11523 }
11524 }
b38cadfb 11525
0855e32b
NS		 11526 value += ((globals->root.sgotplt->output_section->vma
11527 + globals->root.sgotplt->output_offset + off)
11528 - (input_section->output_section->vma
11529 + input_section->output_offset
11530 + rel->r_offset)
11531 + globals->sgotplt_jump_table_size);
11532 }
11533 else
11534 value = ((globals->root.sgot->output_section->vma
11535 + globals->root.sgot->output_offset + off)
11536 - (input_section->output_section->vma
11537 + input_section->output_offset + rel->r_offset));
ba93b8ac
DJ		 11538
11539 return _bfd_final_link_relocate (howto, input_bfd, input_section,
11540 contents, rel->r_offset, value,
00a97672 11541 rel->r_addend);
ba93b8ac
DJ		 11542 }
11543
11544 case R_ARM_TLS_LE32:
3cbc1e5e 11545 if (bfd_link_dll (info))
ba93b8ac
DJ		 11546 {
11547 (*_bfd_error_handler)
11548 (_("%B(%A+0x%lx): R_ARM_TLS_LE32 relocation not permitted in shared object"),
11549 input_bfd, input_section,
11550 (long) rel->r_offset, howto->name);
46691134 11551 return bfd_reloc_notsupported;
ba93b8ac
DJ		 11552 }
11553 else
11554 value = tpoff (info, value);
906e58ca 11555
ba93b8ac 11556 return _bfd_final_link_relocate (howto, input_bfd, input_section,
00a97672
RS		 11557 contents, rel->r_offset, value,
11558 rel->r_addend);
ba93b8ac 11559
319850b4
JB		 11560 case R_ARM_V4BX:
11561 if (globals->fix_v4bx)
845b51d6
PB		 11562 {
11563 bfd_vma insn = bfd_get_32 (input_bfd, hit_data);
319850b4 11564
845b51d6
PB		 11565 /* Ensure that we have a BX instruction. */
11566 BFD_ASSERT ((insn & 0x0ffffff0) == 0x012fff10);
319850b4 11567
845b51d6
PB		 11568 if (globals->fix_v4bx == 2 && (insn & 0xf) != 0xf)
11569 {
11570 /* Branch to veneer. */
11571 bfd_vma glue_addr;
11572 glue_addr = elf32_arm_bx_glue (info, insn & 0xf);
11573 glue_addr -= input_section->output_section->vma
11574 + input_section->output_offset
11575 + rel->r_offset + 8;
11576 insn = (insn & 0xf0000000) | 0x0a000000
11577 | ((glue_addr >> 2) & 0x00ffffff);
11578 }
11579 else
11580 {
11581 /* Preserve Rm (lowest four bits) and the condition code
11582 (highest four bits). Other bits encode MOV PC,Rm. */
11583 insn = (insn & 0xf000000f) | 0x01a0f000;
11584 }
319850b4 11585
845b51d6
PB		 11586 bfd_put_32 (input_bfd, insn, hit_data);
11587 }
319850b4
JB		 11588 return bfd_reloc_ok;
11589
b6895b4f
PB		 11590 case R_ARM_MOVW_ABS_NC:
11591 case R_ARM_MOVT_ABS:
11592 case R_ARM_MOVW_PREL_NC:
11593 case R_ARM_MOVT_PREL:
92f5d02b
MS		 11594 /* Until we properly support segment-base-relative addressing then
11595 we assume the segment base to be zero, as for the group relocations.
11596 Thus R_ARM_MOVW_BREL_NC has the same semantics as R_ARM_MOVW_ABS_NC
11597 and R_ARM_MOVT_BREL has the same semantics as R_ARM_MOVT_ABS. */
11598 case R_ARM_MOVW_BREL_NC:
11599 case R_ARM_MOVW_BREL:
11600 case R_ARM_MOVT_BREL:
b6895b4f
PB		 11601 {
11602 bfd_vma insn = bfd_get_32 (input_bfd, hit_data);
11603
11604 if (globals->use_rel)
11605 {
11606 addend = ((insn >> 4) & 0xf000) | (insn & 0xfff);
39623e12 11607 signed_addend = (addend ^ 0x8000) - 0x8000;
b6895b4f 11608 }
92f5d02b 11609
b6895b4f 11610 value += signed_addend;
b6895b4f
PB		 11611
11612 if (r_type == R_ARM_MOVW_PREL_NC || r_type == R_ARM_MOVT_PREL)
11613 value -= (input_section->output_section->vma
11614 + input_section->output_offset + rel->r_offset);
11615
92f5d02b 11616 if (r_type == R_ARM_MOVW_BREL && value >= 0x10000)
99059e56 11617 return bfd_reloc_overflow;
92f5d02b 11618
35fc36a8 11619 if (branch_type == ST_BRANCH_TO_THUMB)
92f5d02b
MS		 11620 value |= 1;
11621
11622 if (r_type == R_ARM_MOVT_ABS || r_type == R_ARM_MOVT_PREL
99059e56 11623 || r_type == R_ARM_MOVT_BREL)
b6895b4f
PB		 11624 value >>= 16;
11625
11626 insn &= 0xfff0f000;
11627 insn |= value & 0xfff;
11628 insn |= (value & 0xf000) << 4;
11629 bfd_put_32 (input_bfd, insn, hit_data);
11630 }
11631 return bfd_reloc_ok;
11632
11633 case R_ARM_THM_MOVW_ABS_NC:
11634 case R_ARM_THM_MOVT_ABS:
11635 case R_ARM_THM_MOVW_PREL_NC:
11636 case R_ARM_THM_MOVT_PREL:
92f5d02b
MS		 11637 /* Until we properly support segment-base-relative addressing then
11638 we assume the segment base to be zero, as for the above relocations.
11639 Thus R_ARM_THM_MOVW_BREL_NC has the same semantics as
11640 R_ARM_THM_MOVW_ABS_NC and R_ARM_THM_MOVT_BREL has the same semantics
11641 as R_ARM_THM_MOVT_ABS. */
11642 case R_ARM_THM_MOVW_BREL_NC:
11643 case R_ARM_THM_MOVW_BREL:
11644 case R_ARM_THM_MOVT_BREL:
b6895b4f
PB		 11645 {
11646 bfd_vma insn;
906e58ca 11647
b6895b4f
PB		 11648 insn = bfd_get_16 (input_bfd, hit_data) << 16;
11649 insn |= bfd_get_16 (input_bfd, hit_data + 2);
11650
11651 if (globals->use_rel)
11652 {
11653 addend = ((insn >> 4) & 0xf000)
11654 | ((insn >> 15) & 0x0800)
11655 | ((insn >> 4) & 0x0700)
11656 | (insn & 0x00ff);
39623e12 11657 signed_addend = (addend ^ 0x8000) - 0x8000;
b6895b4f 11658 }
92f5d02b 11659
b6895b4f 11660 value += signed_addend;
b6895b4f
PB		 11661
11662 if (r_type == R_ARM_THM_MOVW_PREL_NC || r_type == R_ARM_THM_MOVT_PREL)
11663 value -= (input_section->output_section->vma
11664 + input_section->output_offset + rel->r_offset);
11665
92f5d02b 11666 if (r_type == R_ARM_THM_MOVW_BREL && value >= 0x10000)
99059e56 11667 return bfd_reloc_overflow;
92f5d02b 11668
35fc36a8 11669 if (branch_type == ST_BRANCH_TO_THUMB)
92f5d02b
MS		 11670 value |= 1;
11671
11672 if (r_type == R_ARM_THM_MOVT_ABS || r_type == R_ARM_THM_MOVT_PREL
99059e56 11673 || r_type == R_ARM_THM_MOVT_BREL)
b6895b4f
PB		 11674 value >>= 16;
11675
11676 insn &= 0xfbf08f00;
11677 insn |= (value & 0xf000) << 4;
11678 insn |= (value & 0x0800) << 15;
11679 insn |= (value & 0x0700) << 4;
11680 insn |= (value & 0x00ff);
11681
11682 bfd_put_16 (input_bfd, insn >> 16, hit_data);
11683 bfd_put_16 (input_bfd, insn & 0xffff, hit_data + 2);
11684 }
11685 return bfd_reloc_ok;
11686
4962c51a
MS		 11687 case R_ARM_ALU_PC_G0_NC:
11688 case R_ARM_ALU_PC_G1_NC:
11689 case R_ARM_ALU_PC_G0:
11690 case R_ARM_ALU_PC_G1:
11691 case R_ARM_ALU_PC_G2:
11692 case R_ARM_ALU_SB_G0_NC:
11693 case R_ARM_ALU_SB_G1_NC:
11694 case R_ARM_ALU_SB_G0:
11695 case R_ARM_ALU_SB_G1:
11696 case R_ARM_ALU_SB_G2:
11697 {
11698 bfd_vma insn = bfd_get_32 (input_bfd, hit_data);
99059e56 11699 bfd_vma pc = input_section->output_section->vma
4962c51a 11700 + input_section->output_offset + rel->r_offset;
31a91d61 11701 /* sb is the origin of the *segment* containing the symbol. */
62c34db3 11702 bfd_vma sb = sym_sec ? sym_sec->output_section->vma : 0;
99059e56
RM		 11703 bfd_vma residual;
11704 bfd_vma g_n;
4962c51a 11705 bfd_signed_vma signed_value;
99059e56
RM		 11706 int group = 0;
11707
11708 /* Determine which group of bits to select. */
11709 switch (r_type)
11710 {
11711 case R_ARM_ALU_PC_G0_NC:
11712 case R_ARM_ALU_PC_G0:
11713 case R_ARM_ALU_SB_G0_NC:
11714 case R_ARM_ALU_SB_G0:
11715 group = 0;
11716 break;
11717
11718 case R_ARM_ALU_PC_G1_NC:
11719 case R_ARM_ALU_PC_G1:
11720 case R_ARM_ALU_SB_G1_NC:
11721 case R_ARM_ALU_SB_G1:
11722 group = 1;
11723 break;
11724
11725 case R_ARM_ALU_PC_G2:
11726 case R_ARM_ALU_SB_G2:
11727 group = 2;
11728 break;
11729
11730 default:
11731 abort ();
11732 }
11733
11734 /* If REL, extract the addend from the insn. If RELA, it will
11735 have already been fetched for us. */
4962c51a 11736 if (globals->use_rel)
99059e56
RM		 11737 {
11738 int negative;
11739 bfd_vma constant = insn & 0xff;
11740 bfd_vma rotation = (insn & 0xf00) >> 8;
11741
11742 if (rotation == 0)
11743 signed_addend = constant;
11744 else
11745 {
11746 /* Compensate for the fact that in the instruction, the
11747 rotation is stored in multiples of 2 bits. */
11748 rotation *= 2;
11749
11750 /* Rotate "constant" right by "rotation" bits. */
11751 signed_addend = (constant >> rotation) |
11752 (constant << (8 * sizeof (bfd_vma) - rotation));
11753 }
11754
11755 /* Determine if the instruction is an ADD or a SUB.
11756 (For REL, this determines the sign of the addend.) */
11757 negative = identify_add_or_sub (insn);
11758 if (negative == 0)
11759 {
11760 (*_bfd_error_handler)
11761 (_("%B(%A+0x%lx): Only ADD or SUB instructions are allowed for ALU group relocations"),
11762 input_bfd, input_section,
11763 (long) rel->r_offset, howto->name);
11764 return bfd_reloc_overflow;
11765 }
11766
11767 signed_addend *= negative;
11768 }
4962c51a
MS		 11769
11770 /* Compute the value (X) to go in the place. */
99059e56
RM		 11771 if (r_type == R_ARM_ALU_PC_G0_NC
11772 || r_type == R_ARM_ALU_PC_G1_NC
11773 || r_type == R_ARM_ALU_PC_G0
11774 || r_type == R_ARM_ALU_PC_G1
11775 || r_type == R_ARM_ALU_PC_G2)
11776 /* PC relative. */
11777 signed_value = value - pc + signed_addend;
11778 else
11779 /* Section base relative. */
11780 signed_value = value - sb + signed_addend;
11781
11782 /* If the target symbol is a Thumb function, then set the
11783 Thumb bit in the address. */
35fc36a8 11784 if (branch_type == ST_BRANCH_TO_THUMB)
4962c51a
MS		 11785 signed_value |= 1;
11786
99059e56
RM		 11787 /* Calculate the value of the relevant G_n, in encoded
11788 constant-with-rotation format. */
b6518b38
NC		 11789 g_n = calculate_group_reloc_mask (signed_value < 0 ? - signed_value : signed_value,
11790 group, &residual);
99059e56
RM		 11791
11792 /* Check for overflow if required. */
11793 if ((r_type == R_ARM_ALU_PC_G0
11794 || r_type == R_ARM_ALU_PC_G1
11795 || r_type == R_ARM_ALU_PC_G2
11796 || r_type == R_ARM_ALU_SB_G0
11797 || r_type == R_ARM_ALU_SB_G1
11798 || r_type == R_ARM_ALU_SB_G2) && residual != 0)
11799 {
11800 (*_bfd_error_handler)
11801 (_("%B(%A+0x%lx): Overflow whilst splitting 0x%lx for group relocation %s"),
11802 input_bfd, input_section,
b6518b38
NC		 11803 (long) rel->r_offset, signed_value < 0 ? - signed_value : signed_value,
11804 howto->name);
99059e56
RM		 11805 return bfd_reloc_overflow;
11806 }
11807
11808 /* Mask out the value and the ADD/SUB part of the opcode; take care
11809 not to destroy the S bit. */
11810 insn &= 0xff1ff000;
11811
11812 /* Set the opcode according to whether the value to go in the
11813 place is negative. */
11814 if (signed_value < 0)
11815 insn |= 1 << 22;
11816 else
11817 insn |= 1 << 23;
11818
11819 /* Encode the offset. */
11820 insn |= g_n;
4962c51a
MS		 11821
11822 bfd_put_32 (input_bfd, insn, hit_data);
11823 }
11824 return bfd_reloc_ok;
11825
11826 case R_ARM_LDR_PC_G0:
11827 case R_ARM_LDR_PC_G1:
11828 case R_ARM_LDR_PC_G2:
11829 case R_ARM_LDR_SB_G0:
11830 case R_ARM_LDR_SB_G1:
11831 case R_ARM_LDR_SB_G2:
11832 {
11833 bfd_vma insn = bfd_get_32 (input_bfd, hit_data);
99059e56 11834 bfd_vma pc = input_section->output_section->vma
4962c51a 11835 + input_section->output_offset + rel->r_offset;
31a91d61 11836 /* sb is the origin of the *segment* containing the symbol. */
62c34db3 11837 bfd_vma sb = sym_sec ? sym_sec->output_section->vma : 0;
99059e56 11838 bfd_vma residual;
4962c51a 11839 bfd_signed_vma signed_value;
99059e56
RM		 11840 int group = 0;
11841
11842 /* Determine which groups of bits to calculate. */
11843 switch (r_type)
11844 {
11845 case R_ARM_LDR_PC_G0:
11846 case R_ARM_LDR_SB_G0:
11847 group = 0;
11848 break;
11849
11850 case R_ARM_LDR_PC_G1:
11851 case R_ARM_LDR_SB_G1:
11852 group = 1;
11853 break;
11854
11855 case R_ARM_LDR_PC_G2:
11856 case R_ARM_LDR_SB_G2:
11857 group = 2;
11858 break;
11859
11860 default:
11861 abort ();
11862 }
11863
11864 /* If REL, extract the addend from the insn. If RELA, it will
11865 have already been fetched for us. */
4962c51a 11866 if (globals->use_rel)
99059e56
RM		 11867 {
11868 int negative = (insn & (1 << 23)) ? 1 : -1;
11869 signed_addend = negative * (insn & 0xfff);
11870 }
4962c51a
MS		 11871
11872 /* Compute the value (X) to go in the place. */
99059e56
RM		 11873 if (r_type == R_ARM_LDR_PC_G0
11874 || r_type == R_ARM_LDR_PC_G1
11875 || r_type == R_ARM_LDR_PC_G2)
11876 /* PC relative. */
11877 signed_value = value - pc + signed_addend;
11878 else
11879 /* Section base relative. */
11880 signed_value = value - sb + signed_addend;
11881
11882 /* Calculate the value of the relevant G_{n-1} to obtain
11883 the residual at that stage. */
b6518b38
NC		 11884 calculate_group_reloc_mask (signed_value < 0 ? - signed_value : signed_value,
11885 group - 1, &residual);
99059e56
RM		 11886
11887 /* Check for overflow. */
11888 if (residual >= 0x1000)
11889 {
11890 (*_bfd_error_handler)
11891 (_("%B(%A+0x%lx): Overflow whilst splitting 0x%lx for group relocation %s"),
b6518b38
NC		 11892 input_bfd, input_section,
11893 (long) rel->r_offset, labs (signed_value), howto->name);
99059e56
RM		 11894 return bfd_reloc_overflow;
11895 }
11896
11897 /* Mask out the value and U bit. */
11898 insn &= 0xff7ff000;
11899
11900 /* Set the U bit if the value to go in the place is non-negative. */
11901 if (signed_value >= 0)
11902 insn |= 1 << 23;
11903
11904 /* Encode the offset. */
11905 insn |= residual;
4962c51a
MS		 11906
11907 bfd_put_32 (input_bfd, insn, hit_data);
11908 }
11909 return bfd_reloc_ok;
11910
11911 case R_ARM_LDRS_PC_G0:
11912 case R_ARM_LDRS_PC_G1:
11913 case R_ARM_LDRS_PC_G2:
11914 case R_ARM_LDRS_SB_G0:
11915 case R_ARM_LDRS_SB_G1:
11916 case R_ARM_LDRS_SB_G2:
11917 {
11918 bfd_vma insn = bfd_get_32 (input_bfd, hit_data);
99059e56 11919 bfd_vma pc = input_section->output_section->vma
4962c51a 11920 + input_section->output_offset + rel->r_offset;
31a91d61 11921 /* sb is the origin of the *segment* containing the symbol. */
62c34db3 11922 bfd_vma sb = sym_sec ? sym_sec->output_section->vma : 0;
99059e56 11923 bfd_vma residual;
4962c51a 11924 bfd_signed_vma signed_value;
99059e56
RM		 11925 int group = 0;
11926
11927 /* Determine which groups of bits to calculate. */
11928 switch (r_type)
11929 {
11930 case R_ARM_LDRS_PC_G0:
11931 case R_ARM_LDRS_SB_G0:
11932 group = 0;
11933 break;
11934
11935 case R_ARM_LDRS_PC_G1:
11936 case R_ARM_LDRS_SB_G1:
11937 group = 1;
11938 break;
11939
11940 case R_ARM_LDRS_PC_G2:
11941 case R_ARM_LDRS_SB_G2:
11942 group = 2;
11943 break;
11944
11945 default:
11946 abort ();
11947 }
11948
11949 /* If REL, extract the addend from the insn. If RELA, it will
11950 have already been fetched for us. */
4962c51a 11951 if (globals->use_rel)
99059e56
RM		 11952 {
11953 int negative = (insn & (1 << 23)) ? 1 : -1;
11954 signed_addend = negative * (((insn & 0xf00) >> 4) + (insn & 0xf));
11955 }
4962c51a
MS		 11956
11957 /* Compute the value (X) to go in the place. */
99059e56
RM		 11958 if (r_type == R_ARM_LDRS_PC_G0
11959 || r_type == R_ARM_LDRS_PC_G1
11960 || r_type == R_ARM_LDRS_PC_G2)
11961 /* PC relative. */
11962 signed_value = value - pc + signed_addend;
11963 else
11964 /* Section base relative. */
11965 signed_value = value - sb + signed_addend;
11966
11967 /* Calculate the value of the relevant G_{n-1} to obtain
11968 the residual at that stage. */
b6518b38
NC		 11969 calculate_group_reloc_mask (signed_value < 0 ? - signed_value : signed_value,
11970 group - 1, &residual);
99059e56
RM		 11971
11972 /* Check for overflow. */
11973 if (residual >= 0x100)
11974 {
11975 (*_bfd_error_handler)
11976 (_("%B(%A+0x%lx): Overflow whilst splitting 0x%lx for group relocation %s"),
b6518b38
NC		 11977 input_bfd, input_section,
11978 (long) rel->r_offset, labs (signed_value), howto->name);
99059e56
RM		 11979 return bfd_reloc_overflow;
11980 }
11981
11982 /* Mask out the value and U bit. */
11983 insn &= 0xff7ff0f0;
11984
11985 /* Set the U bit if the value to go in the place is non-negative. */
11986 if (signed_value >= 0)
11987 insn |= 1 << 23;
11988
11989 /* Encode the offset. */
11990 insn |= ((residual & 0xf0) << 4) | (residual & 0xf);
4962c51a
MS		 11991
11992 bfd_put_32 (input_bfd, insn, hit_data);
11993 }
11994 return bfd_reloc_ok;
11995
11996 case R_ARM_LDC_PC_G0:
11997 case R_ARM_LDC_PC_G1:
11998 case R_ARM_LDC_PC_G2:
11999 case R_ARM_LDC_SB_G0:
12000 case R_ARM_LDC_SB_G1:
12001 case R_ARM_LDC_SB_G2:
12002 {
12003 bfd_vma insn = bfd_get_32 (input_bfd, hit_data);
99059e56 12004 bfd_vma pc = input_section->output_section->vma
4962c51a 12005 + input_section->output_offset + rel->r_offset;
31a91d61 12006 /* sb is the origin of the *segment* containing the symbol. */
62c34db3 12007 bfd_vma sb = sym_sec ? sym_sec->output_section->vma : 0;
99059e56 12008 bfd_vma residual;
4962c51a 12009 bfd_signed_vma signed_value;
99059e56
RM		 12010 int group = 0;
12011
12012 /* Determine which groups of bits to calculate. */
12013 switch (r_type)
12014 {
12015 case R_ARM_LDC_PC_G0:
12016 case R_ARM_LDC_SB_G0:
12017 group = 0;
12018 break;
12019
12020 case R_ARM_LDC_PC_G1:
12021 case R_ARM_LDC_SB_G1:
12022 group = 1;
12023 break;
12024
12025 case R_ARM_LDC_PC_G2:
12026 case R_ARM_LDC_SB_G2:
12027 group = 2;
12028 break;
12029
12030 default:
12031 abort ();
12032 }
12033
12034 /* If REL, extract the addend from the insn. If RELA, it will
12035 have already been fetched for us. */
4962c51a 12036 if (globals->use_rel)
99059e56
RM		 12037 {
12038 int negative = (insn & (1 << 23)) ? 1 : -1;
12039 signed_addend = negative * ((insn & 0xff) << 2);
12040 }
4962c51a
MS		 12041
12042 /* Compute the value (X) to go in the place. */
99059e56
RM		 12043 if (r_type == R_ARM_LDC_PC_G0
12044 || r_type == R_ARM_LDC_PC_G1
12045 || r_type == R_ARM_LDC_PC_G2)
12046 /* PC relative. */
12047 signed_value = value - pc + signed_addend;
12048 else
12049 /* Section base relative. */
12050 signed_value = value - sb + signed_addend;
12051
12052 /* Calculate the value of the relevant G_{n-1} to obtain
12053 the residual at that stage. */
b6518b38
NC		 12054 calculate_group_reloc_mask (signed_value < 0 ? - signed_value : signed_value,
12055 group - 1, &residual);
99059e56
RM		 12056
12057 /* Check for overflow. (The absolute value to go in the place must be
12058 divisible by four and, after having been divided by four, must
12059 fit in eight bits.) */
12060 if ((residual & 0x3) != 0 || residual >= 0x400)
12061 {
12062 (*_bfd_error_handler)
12063 (_("%B(%A+0x%lx): Overflow whilst splitting 0x%lx for group relocation %s"),
12064 input_bfd, input_section,
b6518b38 12065 (long) rel->r_offset, labs (signed_value), howto->name);
99059e56
RM		 12066 return bfd_reloc_overflow;
12067 }
12068
12069 /* Mask out the value and U bit. */
12070 insn &= 0xff7fff00;
12071
12072 /* Set the U bit if the value to go in the place is non-negative. */
12073 if (signed_value >= 0)
12074 insn |= 1 << 23;
12075
12076 /* Encode the offset. */
12077 insn |= residual >> 2;
4962c51a
MS		 12078
12079 bfd_put_32 (input_bfd, insn, hit_data);
12080 }
12081 return bfd_reloc_ok;
12082
72d98d16
MG		 12083 case R_ARM_THM_ALU_ABS_G0_NC:
12084 case R_ARM_THM_ALU_ABS_G1_NC:
12085 case R_ARM_THM_ALU_ABS_G2_NC:
12086 case R_ARM_THM_ALU_ABS_G3_NC:
12087 {
12088 const int shift_array[4] = {0, 8, 16, 24};
12089 bfd_vma insn = bfd_get_16 (input_bfd, hit_data);
12090 bfd_vma addr = value;
12091 int shift = shift_array[r_type - R_ARM_THM_ALU_ABS_G0_NC];
12092
12093 /* Compute address. */
12094 if (globals->use_rel)
12095 signed_addend = insn & 0xff;
12096 addr += signed_addend;
12097 if (branch_type == ST_BRANCH_TO_THUMB)
12098 addr |= 1;
12099 /* Clean imm8 insn. */
12100 insn &= 0xff00;
12101 /* And update with correct part of address. */
12102 insn |= (addr >> shift) & 0xff;
12103 /* Update insn. */
12104 bfd_put_16 (input_bfd, insn, hit_data);
12105 }
12106
12107 *unresolved_reloc_p = FALSE;
12108 return bfd_reloc_ok;
12109
252b5132
RH		 12110 default:
12111 return bfd_reloc_notsupported;
12112 }
12113}
12114
98c1d4aa
NC		 12115/* Add INCREMENT to the reloc (of type HOWTO) at ADDRESS. */
12116static void
57e8b36a
NC		 12117arm_add_to_rel (bfd * abfd,
12118 bfd_byte * address,
12119 reloc_howto_type * howto,
12120 bfd_signed_vma increment)
98c1d4aa 12121{
98c1d4aa
NC		 12122 bfd_signed_vma addend;
12123
bd97cb95
DJ		 12124 if (howto->type == R_ARM_THM_CALL
12125 || howto->type == R_ARM_THM_JUMP24)
98c1d4aa 12126 {
9a5aca8c
AM		 12127 int upper_insn, lower_insn;
12128 int upper, lower;
98c1d4aa 12129
9a5aca8c
AM		 12130 upper_insn = bfd_get_16 (abfd, address);
12131 lower_insn = bfd_get_16 (abfd, address + 2);
12132 upper = upper_insn & 0x7ff;
12133 lower = lower_insn & 0x7ff;
12134
12135 addend = (upper << 12) | (lower << 1);
ddda4409 12136 addend += increment;
9a5aca8c 12137 addend >>= 1;
98c1d4aa 12138
9a5aca8c
AM		 12139 upper_insn = (upper_insn & 0xf800) | ((addend >> 11) & 0x7ff);
12140 lower_insn = (lower_insn & 0xf800) | (addend & 0x7ff);
12141
dc810e39
AM		 12142 bfd_put_16 (abfd, (bfd_vma) upper_insn, address);
12143 bfd_put_16 (abfd, (bfd_vma) lower_insn, address + 2);
9a5aca8c
AM		 12144 }
12145 else
12146 {
12147 bfd_vma contents;
12148
12149 contents = bfd_get_32 (abfd, address);
12150
12151 /* Get the (signed) value from the instruction. */
12152 addend = contents & howto->src_mask;
12153 if (addend & ((howto->src_mask + 1) >> 1))
12154 {
12155 bfd_signed_vma mask;
12156
12157 mask = -1;
12158 mask &= ~ howto->src_mask;
12159 addend |= mask;
12160 }
12161
12162 /* Add in the increment, (which is a byte value). */
12163 switch (howto->type)
12164 {
12165 default:
12166 addend += increment;
12167 break;
12168
12169 case R_ARM_PC24:
c6596c5e 12170 case R_ARM_PLT32:
5b5bb741
PB		 12171 case R_ARM_CALL:
12172 case R_ARM_JUMP24:
9a5aca8c 12173 addend <<= howto->size;
dc810e39 12174 addend += increment;
9a5aca8c
AM		 12175
12176 /* Should we check for overflow here ? */
12177
12178 /* Drop any undesired bits. */
12179 addend >>= howto->rightshift;
12180 break;
12181 }
12182
12183 contents = (contents & ~ howto->dst_mask) | (addend & howto->dst_mask);
12184
12185 bfd_put_32 (abfd, contents, address);
ddda4409 12186 }
98c1d4aa 12187}
252b5132 12188
ba93b8ac
DJ		 12189#define IS_ARM_TLS_RELOC(R_TYPE) \
12190 ((R_TYPE) == R_ARM_TLS_GD32 \
12191 || (R_TYPE) == R_ARM_TLS_LDO32 \
12192 || (R_TYPE) == R_ARM_TLS_LDM32 \
12193 || (R_TYPE) == R_ARM_TLS_DTPOFF32 \
12194 || (R_TYPE) == R_ARM_TLS_DTPMOD32 \
12195 || (R_TYPE) == R_ARM_TLS_TPOFF32 \
12196 || (R_TYPE) == R_ARM_TLS_LE32 \
0855e32b
NS		 12197 || (R_TYPE) == R_ARM_TLS_IE32 \
12198 || IS_ARM_TLS_GNU_RELOC (R_TYPE))
12199
12200/* Specific set of relocations for the gnu tls dialect. */
12201#define IS_ARM_TLS_GNU_RELOC(R_TYPE) \
12202 ((R_TYPE) == R_ARM_TLS_GOTDESC \
12203 || (R_TYPE) == R_ARM_TLS_CALL \
12204 || (R_TYPE) == R_ARM_THM_TLS_CALL \
12205 || (R_TYPE) == R_ARM_TLS_DESCSEQ \
12206 || (R_TYPE) == R_ARM_THM_TLS_DESCSEQ)
ba93b8ac 12207
252b5132 12208/* Relocate an ARM ELF section. */
906e58ca 12209
b34976b6 12210static bfd_boolean
57e8b36a
NC		 12211elf32_arm_relocate_section (bfd * output_bfd,
12212 struct bfd_link_info * info,
12213 bfd * input_bfd,
12214 asection * input_section,
12215 bfd_byte * contents,
12216 Elf_Internal_Rela * relocs,
12217 Elf_Internal_Sym * local_syms,
12218 asection ** local_sections)
252b5132 12219{
b34976b6
AM		 12220 Elf_Internal_Shdr *symtab_hdr;
12221 struct elf_link_hash_entry **sym_hashes;
12222 Elf_Internal_Rela *rel;
12223 Elf_Internal_Rela *relend;
12224 const char *name;
b32d3aa2 12225 struct elf32_arm_link_hash_table * globals;
252b5132 12226
4e7fd91e 12227 globals = elf32_arm_hash_table (info);
4dfe6ac6
NC		 12228 if (globals == NULL)
12229 return FALSE;
b491616a 12230
0ffa91dd 12231 symtab_hdr = & elf_symtab_hdr (input_bfd);
252b5132
RH		 12232 sym_hashes = elf_sym_hashes (input_bfd);
12233
12234 rel = relocs;
12235 relend = relocs + input_section->reloc_count;
12236 for (; rel < relend; rel++)
12237 {
ba96a88f
NC		 12238 int r_type;
12239 reloc_howto_type * howto;
12240 unsigned long r_symndx;
12241 Elf_Internal_Sym * sym;
12242 asection * sec;
252b5132 12243 struct elf_link_hash_entry * h;
ba96a88f
NC		 12244 bfd_vma relocation;
12245 bfd_reloc_status_type r;
12246 arelent bfd_reloc;
ba93b8ac 12247 char sym_type;
0945cdfd 12248 bfd_boolean unresolved_reloc = FALSE;
f2a9dd69 12249 char *error_message = NULL;
f21f3fe0 12250
252b5132 12251 r_symndx = ELF32_R_SYM (rel->r_info);
ba96a88f 12252 r_type = ELF32_R_TYPE (rel->r_info);
b32d3aa2 12253 r_type = arm_real_reloc_type (globals, r_type);
252b5132 12254
ba96a88f 12255 if ( r_type == R_ARM_GNU_VTENTRY
99059e56
RM		 12256 || r_type == R_ARM_GNU_VTINHERIT)
12257 continue;
252b5132 12258
b32d3aa2 12259 bfd_reloc.howto = elf32_arm_howto_from_type (r_type);
ba96a88f 12260 howto = bfd_reloc.howto;
252b5132 12261
252b5132
RH		 12262 h = NULL;
12263 sym = NULL;
12264 sec = NULL;
9b485d32 12265
252b5132
RH		 12266 if (r_symndx < symtab_hdr->sh_info)
12267 {
12268 sym = local_syms + r_symndx;
ba93b8ac 12269 sym_type = ELF32_ST_TYPE (sym->st_info);
252b5132 12270 sec = local_sections[r_symndx];
ffcb4889
NS		 12271
12272 /* An object file might have a reference to a local
12273 undefined symbol. This is a daft object file, but we
12274 should at least do something about it. V4BX & NONE
12275 relocations do not use the symbol and are explicitly
77b4f08f
TS		 12276 allowed to use the undefined symbol, so allow those.
12277 Likewise for relocations against STN_UNDEF. */
ffcb4889
NS		 12278 if (r_type != R_ARM_V4BX
12279 && r_type != R_ARM_NONE
77b4f08f 12280 && r_symndx != STN_UNDEF
ffcb4889
NS		 12281 && bfd_is_und_section (sec)
12282 && ELF_ST_BIND (sym->st_info) != STB_WEAK)
1a72702b
AM		 12283 (*info->callbacks->undefined_symbol)
12284 (info, bfd_elf_string_from_elf_section
12285 (input_bfd, symtab_hdr->sh_link, sym->st_name),
12286 input_bfd, input_section,
12287 rel->r_offset, TRUE);
b38cadfb 12288
4e7fd91e 12289 if (globals->use_rel)
f8df10f4 12290 {
4e7fd91e
PB		 12291 relocation = (sec->output_section->vma
12292 + sec->output_offset
12293 + sym->st_value);
0e1862bb 12294 if (!bfd_link_relocatable (info)
ab96bf03
AM		 12295 && (sec->flags & SEC_MERGE)
12296 && ELF_ST_TYPE (sym->st_info) == STT_SECTION)
f8df10f4 12297 {
4e7fd91e
PB		 12298 asection *msec;
12299 bfd_vma addend, value;
12300
39623e12 12301 switch (r_type)
4e7fd91e 12302 {
39623e12
PB		 12303 case R_ARM_MOVW_ABS_NC:
12304 case R_ARM_MOVT_ABS:
12305 value = bfd_get_32 (input_bfd, contents + rel->r_offset);
12306 addend = ((value & 0xf0000) >> 4) | (value & 0xfff);
12307 addend = (addend ^ 0x8000) - 0x8000;
12308 break;
f8df10f4 12309
39623e12
PB		 12310 case R_ARM_THM_MOVW_ABS_NC:
12311 case R_ARM_THM_MOVT_ABS:
12312 value = bfd_get_16 (input_bfd, contents + rel->r_offset)
12313 << 16;
12314 value |= bfd_get_16 (input_bfd,
12315 contents + rel->r_offset + 2);
12316 addend = ((value & 0xf7000) >> 4) | (value & 0xff)
12317 | ((value & 0x04000000) >> 15);
12318 addend = (addend ^ 0x8000) - 0x8000;
12319 break;
f8df10f4 12320
39623e12
PB		 12321 default:
12322 if (howto->rightshift
12323 || (howto->src_mask & (howto->src_mask + 1)))
12324 {
12325 (*_bfd_error_handler)
12326 (_("%B(%A+0x%lx): %s relocation against SEC_MERGE section"),
12327 input_bfd, input_section,
12328 (long) rel->r_offset, howto->name);
12329 return FALSE;
12330 }
12331
12332 value = bfd_get_32 (input_bfd, contents + rel->r_offset);
12333
12334 /* Get the (signed) value from the instruction. */
12335 addend = value & howto->src_mask;
12336 if (addend & ((howto->src_mask + 1) >> 1))
12337 {
12338 bfd_signed_vma mask;
12339
12340 mask = -1;
12341 mask &= ~ howto->src_mask;
12342 addend |= mask;
12343 }
12344 break;
4e7fd91e 12345 }
39623e12 12346
4e7fd91e
PB		 12347 msec = sec;
12348 addend =
12349 _bfd_elf_rel_local_sym (output_bfd, sym, &msec, addend)
12350 - relocation;
12351 addend += msec->output_section->vma + msec->output_offset;
39623e12 12352
cc643b88 12353 /* Cases here must match those in the preceding
39623e12
PB		 12354 switch statement. */
12355 switch (r_type)
12356 {
12357 case R_ARM_MOVW_ABS_NC:
12358 case R_ARM_MOVT_ABS:
12359 value = (value & 0xfff0f000) | ((addend & 0xf000) << 4)
12360 | (addend & 0xfff);
12361 bfd_put_32 (input_bfd, value, contents + rel->r_offset);
12362 break;
12363
12364 case R_ARM_THM_MOVW_ABS_NC:
12365 case R_ARM_THM_MOVT_ABS:
12366 value = (value & 0xfbf08f00) | ((addend & 0xf700) << 4)
12367 | (addend & 0xff) | ((addend & 0x0800) << 15);
12368 bfd_put_16 (input_bfd, value >> 16,
12369 contents + rel->r_offset);
12370 bfd_put_16 (input_bfd, value,
12371 contents + rel->r_offset + 2);
12372 break;
12373
12374 default:
12375 value = (value & ~ howto->dst_mask)
12376 | (addend & howto->dst_mask);
12377 bfd_put_32 (input_bfd, value, contents + rel->r_offset);
12378 break;
12379 }
f8df10f4 12380 }
f8df10f4 12381 }
4e7fd91e
PB		 12382 else
12383 relocation = _bfd_elf_rela_local_sym (output_bfd, sym, &sec, rel);
252b5132
RH		 12384 }
12385 else
12386 {
62d887d4 12387 bfd_boolean warned, ignored;
560e09e9 12388
b2a8e766
AM		 12389 RELOC_FOR_GLOBAL_SYMBOL (info, input_bfd, input_section, rel,
12390 r_symndx, symtab_hdr, sym_hashes,
12391 h, sec, relocation,
62d887d4 12392 unresolved_reloc, warned, ignored);
ba93b8ac
DJ		 12393
12394 sym_type = h->type;
252b5132
RH		 12395 }
12396
dbaa2011 12397 if (sec != NULL && discarded_section (sec))
e4067dbb 12398 RELOC_AGAINST_DISCARDED_SECTION (info, input_bfd, input_section,
545fd46b 12399 rel, 1, relend, howto, 0, contents);
ab96bf03 12400
0e1862bb 12401 if (bfd_link_relocatable (info))
ab96bf03
AM		 12402 {
12403 /* This is a relocatable link. We don't have to change
12404 anything, unless the reloc is against a section symbol,
12405 in which case we have to adjust according to where the
12406 section symbol winds up in the output section. */
12407 if (sym != NULL && ELF_ST_TYPE (sym->st_info) == STT_SECTION)
12408 {
12409 if (globals->use_rel)
12410 arm_add_to_rel (input_bfd, contents + rel->r_offset,
12411 howto, (bfd_signed_vma) sec->output_offset);
12412 else
12413 rel->r_addend += sec->output_offset;
12414 }
12415 continue;
12416 }
12417
252b5132
RH		 12418 if (h != NULL)
12419 name = h->root.root.string;
12420 else
12421 {
12422 name = (bfd_elf_string_from_elf_section
12423 (input_bfd, symtab_hdr->sh_link, sym->st_name));
12424 if (name == NULL || *name == '\0')
12425 name = bfd_section_name (input_bfd, sec);
12426 }
f21f3fe0 12427
cf35638d 12428 if (r_symndx != STN_UNDEF
ba93b8ac
DJ		 12429 && r_type != R_ARM_NONE
12430 && (h == NULL
12431 || h->root.type == bfd_link_hash_defined
12432 || h->root.type == bfd_link_hash_defweak)
12433 && IS_ARM_TLS_RELOC (r_type) != (sym_type == STT_TLS))
12434 {
12435 (*_bfd_error_handler)
12436 ((sym_type == STT_TLS
12437 ? _("%B(%A+0x%lx): %s used with TLS symbol %s")
12438 : _("%B(%A+0x%lx): %s used with non-TLS symbol %s")),
12439 input_bfd,
12440 input_section,
12441 (long) rel->r_offset,
12442 howto->name,
12443 name);
12444 }
12445
0855e32b 12446 /* We call elf32_arm_final_link_relocate unless we're completely
99059e56
RM		 12447 done, i.e., the relaxation produced the final output we want,
12448 and we won't let anybody mess with it. Also, we have to do
12449 addend adjustments in case of a R_ARM_TLS_GOTDESC relocation
6a631e86 12450 both in relaxed and non-relaxed cases. */
39d911fc
TP		 12451 if ((elf32_arm_tls_transition (info, r_type, h) != (unsigned)r_type)
12452 || (IS_ARM_TLS_GNU_RELOC (r_type)
12453 && !((h ? elf32_arm_hash_entry (h)->tls_type :
12454 elf32_arm_local_got_tls_type (input_bfd)[r_symndx])
12455 & GOT_TLS_GDESC)))
12456 {
12457 r = elf32_arm_tls_relax (globals, input_bfd, input_section,
12458 contents, rel, h == NULL);
12459 /* This may have been marked unresolved because it came from
12460 a shared library. But we've just dealt with that. */
12461 unresolved_reloc = 0;
12462 }
12463 else
12464 r = bfd_reloc_continue;
b38cadfb 12465
39d911fc
TP		 12466 if (r == bfd_reloc_continue)
12467 {
12468 unsigned char branch_type =
12469 h ? ARM_GET_SYM_BRANCH_TYPE (h->target_internal)
12470 : ARM_GET_SYM_BRANCH_TYPE (sym->st_target_internal);
12471
12472 r = elf32_arm_final_link_relocate (howto, input_bfd, output_bfd,
12473 input_section, contents, rel,
12474 relocation, info, sec, name,
12475 sym_type, branch_type, h,
12476 &unresolved_reloc,
12477 &error_message);
12478 }
0945cdfd
DJ		 12479
12480 /* Dynamic relocs are not propagated for SEC_DEBUGGING sections
12481 because such sections are not SEC_ALLOC and thus ld.so will
12482 not process them. */
12483 if (unresolved_reloc
99059e56
RM		 12484 && !((input_section->flags & SEC_DEBUGGING) != 0
12485 && h->def_dynamic)
1d5316ab
AM		 12486 && _bfd_elf_section_offset (output_bfd, info, input_section,
12487 rel->r_offset) != (bfd_vma) -1)
0945cdfd
DJ		 12488 {
12489 (*_bfd_error_handler)
843fe662
L		 12490 (_("%B(%A+0x%lx): unresolvable %s relocation against symbol `%s'"),
12491 input_bfd,
12492 input_section,
12493 (long) rel->r_offset,
12494 howto->name,
12495 h->root.root.string);
0945cdfd
DJ		 12496 return FALSE;
12497 }
252b5132
RH		 12498
12499 if (r != bfd_reloc_ok)
12500 {
252b5132
RH		 12501 switch (r)
12502 {
12503 case bfd_reloc_overflow:
cf919dfd
PB		 12504 /* If the overflowing reloc was to an undefined symbol,
12505 we have already printed one error message and there
12506 is no point complaining again. */
1a72702b
AM		 12507 if (!h || h->root.type != bfd_link_hash_undefined)
12508 (*info->callbacks->reloc_overflow)
12509 (info, (h ? &h->root : NULL), name, howto->name,
12510 (bfd_vma) 0, input_bfd, input_section, rel->r_offset);
252b5132
RH		 12511 break;
12512
12513 case bfd_reloc_undefined:
1a72702b
AM		 12514 (*info->callbacks->undefined_symbol)
12515 (info, name, input_bfd, input_section, rel->r_offset, TRUE);
252b5132
RH		 12516 break;
12517
12518 case bfd_reloc_outofrange:
f2a9dd69 12519 error_message = _("out of range");
252b5132
RH		 12520 goto common_error;
12521
12522 case bfd_reloc_notsupported:
f2a9dd69 12523 error_message = _("unsupported relocation");
252b5132
RH		 12524 goto common_error;
12525
12526 case bfd_reloc_dangerous:
f2a9dd69 12527 /* error_message should already be set. */
252b5132
RH		 12528 goto common_error;
12529
12530 default:
f2a9dd69 12531 error_message = _("unknown error");
8029a119 12532 /* Fall through. */
252b5132
RH		 12533
12534 common_error:
f2a9dd69 12535 BFD_ASSERT (error_message != NULL);
1a72702b
AM		 12536 (*info->callbacks->reloc_dangerous)
12537 (info, error_message, input_bfd, input_section, rel->r_offset);
252b5132
RH		 12538 break;
12539 }
12540 }
12541 }
12542
b34976b6 12543 return TRUE;
252b5132
RH		 12544}
12545
91d6fa6a 12546/* Add a new unwind edit to the list described by HEAD, TAIL. If TINDEX is zero,
2468f9c9 12547 adds the edit to the start of the list. (The list must be built in order of
91d6fa6a 12548 ascending TINDEX: the function's callers are primarily responsible for
2468f9c9
PB		 12549 maintaining that condition). */
12550
12551static void
12552add_unwind_table_edit (arm_unwind_table_edit **head,
12553 arm_unwind_table_edit **tail,
12554 arm_unwind_edit_type type,
12555 asection *linked_section,
91d6fa6a 12556 unsigned int tindex)
2468f9c9 12557{
21d799b5
NC		 12558 arm_unwind_table_edit *new_edit = (arm_unwind_table_edit *)
12559 xmalloc (sizeof (arm_unwind_table_edit));
b38cadfb 12560
2468f9c9
PB		 12561 new_edit->type = type;
12562 new_edit->linked_section = linked_section;
91d6fa6a 12563 new_edit->index = tindex;
b38cadfb 12564
91d6fa6a 12565 if (tindex > 0)
2468f9c9
PB		 12566 {
12567 new_edit->next = NULL;
12568
12569 if (*tail)
12570 (*tail)->next = new_edit;
12571
12572 (*tail) = new_edit;
12573
12574 if (!*head)
12575 (*head) = new_edit;
12576 }
12577 else
12578 {
12579 new_edit->next = *head;
12580
12581 if (!*tail)
12582 *tail = new_edit;
12583
12584 *head = new_edit;
12585 }
12586}
12587
12588static _arm_elf_section_data *get_arm_elf_section_data (asection *);
12589
12590/* Increase the size of EXIDX_SEC by ADJUST bytes. ADJUST mau be negative. */
12591static void
12592adjust_exidx_size(asection *exidx_sec, int adjust)
12593{
12594 asection *out_sec;
12595
12596 if (!exidx_sec->rawsize)
12597 exidx_sec->rawsize = exidx_sec->size;
12598
12599 bfd_set_section_size (exidx_sec->owner, exidx_sec, exidx_sec->size + adjust);
12600 out_sec = exidx_sec->output_section;
12601 /* Adjust size of output section. */
12602 bfd_set_section_size (out_sec->owner, out_sec, out_sec->size +adjust);
12603}
12604
12605/* Insert an EXIDX_CANTUNWIND marker at the end of a section. */
12606static void
12607insert_cantunwind_after(asection *text_sec, asection *exidx_sec)
12608{
12609 struct _arm_elf_section_data *exidx_arm_data;
12610
12611 exidx_arm_data = get_arm_elf_section_data (exidx_sec);
12612 add_unwind_table_edit (
12613 &exidx_arm_data->u.exidx.unwind_edit_list,
12614 &exidx_arm_data->u.exidx.unwind_edit_tail,
12615 INSERT_EXIDX_CANTUNWIND_AT_END, text_sec, UINT_MAX);
12616
491d01d3
YU		 12617 exidx_arm_data->additional_reloc_count++;
12618
2468f9c9
PB		 12619 adjust_exidx_size(exidx_sec, 8);
12620}
12621
12622/* Scan .ARM.exidx tables, and create a list describing edits which should be
12623 made to those tables, such that:
b38cadfb 12624
2468f9c9
PB		 12625 1. Regions without unwind data are marked with EXIDX_CANTUNWIND entries.
12626 2. Duplicate entries are merged together (EXIDX_CANTUNWIND, or unwind
99059e56 12627 codes which have been inlined into the index).
2468f9c9 12628
85fdf906
AH		 12629 If MERGE_EXIDX_ENTRIES is false, duplicate entries are not merged.
12630
2468f9c9 12631 The edits are applied when the tables are written
b38cadfb 12632 (in elf32_arm_write_section). */
2468f9c9
PB		 12633
12634bfd_boolean
12635elf32_arm_fix_exidx_coverage (asection **text_section_order,
12636 unsigned int num_text_sections,
85fdf906
AH		 12637 struct bfd_link_info *info,
12638 bfd_boolean merge_exidx_entries)
2468f9c9
PB		 12639{
12640 bfd *inp;
12641 unsigned int last_second_word = 0, i;
12642 asection *last_exidx_sec = NULL;
12643 asection *last_text_sec = NULL;
12644 int last_unwind_type = -1;
12645
12646 /* Walk over all EXIDX sections, and create backlinks from the corrsponding
12647 text sections. */
c72f2fb2 12648 for (inp = info->input_bfds; inp != NULL; inp = inp->link.next)
2468f9c9
PB		 12649 {
12650 asection *sec;
b38cadfb 12651
2468f9c9 12652 for (sec = inp->sections; sec != NULL; sec = sec->next)
99059e56 12653 {
2468f9c9
PB		 12654 struct bfd_elf_section_data *elf_sec = elf_section_data (sec);
12655 Elf_Internal_Shdr *hdr = &elf_sec->this_hdr;
b38cadfb 12656
dec9d5df 12657 if (!hdr || hdr->sh_type != SHT_ARM_EXIDX)
2468f9c9 12658 continue;
b38cadfb 12659
2468f9c9
PB		 12660 if (elf_sec->linked_to)
12661 {
12662 Elf_Internal_Shdr *linked_hdr
99059e56 12663 = &elf_section_data (elf_sec->linked_to)->this_hdr;
2468f9c9 12664 struct _arm_elf_section_data *linked_sec_arm_data
99059e56 12665 = get_arm_elf_section_data (linked_hdr->bfd_section);
2468f9c9
PB		 12666
12667 if (linked_sec_arm_data == NULL)
99059e56 12668 continue;
2468f9c9
PB		 12669
12670 /* Link this .ARM.exidx section back from the text section it
99059e56 12671 describes. */
2468f9c9
PB		 12672 linked_sec_arm_data->u.text.arm_exidx_sec = sec;
12673 }
12674 }
12675 }
12676
12677 /* Walk all text sections in order of increasing VMA. Eilminate duplicate
12678 index table entries (EXIDX_CANTUNWIND and inlined unwind opcodes),
91d6fa6a 12679 and add EXIDX_CANTUNWIND entries for sections with no unwind table data. */
2468f9c9
PB		 12680
12681 for (i = 0; i < num_text_sections; i++)
12682 {
12683 asection *sec = text_section_order[i];
12684 asection *exidx_sec;
12685 struct _arm_elf_section_data *arm_data = get_arm_elf_section_data (sec);
12686 struct _arm_elf_section_data *exidx_arm_data;
12687 bfd_byte *contents = NULL;
12688 int deleted_exidx_bytes = 0;
12689 bfd_vma j;
12690 arm_unwind_table_edit *unwind_edit_head = NULL;
12691 arm_unwind_table_edit *unwind_edit_tail = NULL;
12692 Elf_Internal_Shdr *hdr;
12693 bfd *ibfd;
12694
12695 if (arm_data == NULL)
99059e56 12696 continue;
2468f9c9
PB		 12697
12698 exidx_sec = arm_data->u.text.arm_exidx_sec;
12699 if (exidx_sec == NULL)
12700 {
12701 /* Section has no unwind data. */
12702 if (last_unwind_type == 0 || !last_exidx_sec)
12703 continue;
12704
12705 /* Ignore zero sized sections. */
12706 if (sec->size == 0)
12707 continue;
12708
12709 insert_cantunwind_after(last_text_sec, last_exidx_sec);
12710 last_unwind_type = 0;
12711 continue;
12712 }
12713
22a8f80e
PB		 12714 /* Skip /DISCARD/ sections. */
12715 if (bfd_is_abs_section (exidx_sec->output_section))
12716 continue;
12717
2468f9c9
PB		 12718 hdr = &elf_section_data (exidx_sec)->this_hdr;
12719 if (hdr->sh_type != SHT_ARM_EXIDX)
99059e56 12720 continue;
b38cadfb 12721
2468f9c9
PB		 12722 exidx_arm_data = get_arm_elf_section_data (exidx_sec);
12723 if (exidx_arm_data == NULL)
99059e56 12724 continue;
b38cadfb 12725
2468f9c9 12726 ibfd = exidx_sec->owner;
b38cadfb 12727
2468f9c9
PB		 12728 if (hdr->contents != NULL)
12729 contents = hdr->contents;
12730 else if (! bfd_malloc_and_get_section (ibfd, exidx_sec, &contents))
12731 /* An error? */
12732 continue;
12733
ac06903d
YU		 12734 if (last_unwind_type > 0)
12735 {
12736 unsigned int first_word = bfd_get_32 (ibfd, contents);
12737 /* Add cantunwind if first unwind item does not match section
12738 start. */
12739 if (first_word != sec->vma)
12740 {
12741 insert_cantunwind_after (last_text_sec, last_exidx_sec);
12742 last_unwind_type = 0;
12743 }
12744 }
12745
2468f9c9
PB		 12746 for (j = 0; j < hdr->sh_size; j += 8)
12747 {
12748 unsigned int second_word = bfd_get_32 (ibfd, contents + j + 4);
12749 int unwind_type;
12750 int elide = 0;
12751
12752 /* An EXIDX_CANTUNWIND entry. */
12753 if (second_word == 1)
12754 {
12755 if (last_unwind_type == 0)
12756 elide = 1;
12757 unwind_type = 0;
12758 }
12759 /* Inlined unwinding data. Merge if equal to previous. */
12760 else if ((second_word & 0x80000000) != 0)
12761 {
85fdf906
AH		 12762 if (merge_exidx_entries
12763 && last_second_word == second_word && last_unwind_type == 1)
2468f9c9
PB		 12764 elide = 1;
12765 unwind_type = 1;
12766 last_second_word = second_word;
12767 }
12768 /* Normal table entry. In theory we could merge these too,
12769 but duplicate entries are likely to be much less common. */
12770 else
12771 unwind_type = 2;
12772
491d01d3 12773 if (elide && !bfd_link_relocatable (info))
2468f9c9
PB		 12774 {
12775 add_unwind_table_edit (&unwind_edit_head, &unwind_edit_tail,
12776 DELETE_EXIDX_ENTRY, NULL, j / 8);
12777
12778 deleted_exidx_bytes += 8;
12779 }
12780
12781 last_unwind_type = unwind_type;
12782 }
12783
12784 /* Free contents if we allocated it ourselves. */
12785 if (contents != hdr->contents)
99059e56 12786 free (contents);
2468f9c9
PB		 12787
12788 /* Record edits to be applied later (in elf32_arm_write_section). */
12789 exidx_arm_data->u.exidx.unwind_edit_list = unwind_edit_head;
12790 exidx_arm_data->u.exidx.unwind_edit_tail = unwind_edit_tail;
b38cadfb 12791
2468f9c9
PB		 12792 if (deleted_exidx_bytes > 0)
12793 adjust_exidx_size(exidx_sec, -deleted_exidx_bytes);
12794
12795 last_exidx_sec = exidx_sec;
12796 last_text_sec = sec;
12797 }
12798
12799 /* Add terminating CANTUNWIND entry. */
491d01d3
YU		 12800 if (!bfd_link_relocatable (info) && last_exidx_sec
12801 && last_unwind_type != 0)
2468f9c9
PB		 12802 insert_cantunwind_after(last_text_sec, last_exidx_sec);
12803
12804 return TRUE;
12805}
12806
3e6b1042
DJ		 12807static bfd_boolean
12808elf32_arm_output_glue_section (struct bfd_link_info *info, bfd *obfd,
12809 bfd *ibfd, const char *name)
12810{
12811 asection *sec, *osec;
12812
3d4d4302 12813 sec = bfd_get_linker_section (ibfd, name);
3e6b1042
DJ		 12814 if (sec == NULL || (sec->flags & SEC_EXCLUDE) != 0)
12815 return TRUE;
12816
12817 osec = sec->output_section;
12818 if (elf32_arm_write_section (obfd, info, sec, sec->contents))
12819 return TRUE;
12820
12821 if (! bfd_set_section_contents (obfd, osec, sec->contents,
12822 sec->output_offset, sec->size))
12823 return FALSE;
12824
12825 return TRUE;
12826}
12827
12828static bfd_boolean
12829elf32_arm_final_link (bfd *abfd, struct bfd_link_info *info)
12830{
12831 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (info);
fe33d2fa 12832 asection *sec, *osec;
3e6b1042 12833
4dfe6ac6
NC		 12834 if (globals == NULL)
12835 return FALSE;
12836
3e6b1042
DJ		 12837 /* Invoke the regular ELF backend linker to do all the work. */
12838 if (!bfd_elf_final_link (abfd, info))
12839 return FALSE;
12840
fe33d2fa
CL		 12841 /* Process stub sections (eg BE8 encoding, ...). */
12842 struct elf32_arm_link_hash_table *htab = elf32_arm_hash_table (info);
7292b3ac 12843 unsigned int i;
cdb21a0a
NS		 12844 for (i=0; i<htab->top_id; i++)
12845 {
12846 sec = htab->stub_group[i].stub_sec;
12847 /* Only process it once, in its link_sec slot. */
12848 if (sec && i == htab->stub_group[i].link_sec->id)
12849 {
12850 osec = sec->output_section;
12851 elf32_arm_write_section (abfd, info, sec, sec->contents);
12852 if (! bfd_set_section_contents (abfd, osec, sec->contents,
12853 sec->output_offset, sec->size))
12854 return FALSE;
12855 }
fe33d2fa 12856 }
fe33d2fa 12857
3e6b1042
DJ		 12858 /* Write out any glue sections now that we have created all the
12859 stubs. */
12860 if (globals->bfd_of_glue_owner != NULL)
12861 {
12862 if (! elf32_arm_output_glue_section (info, abfd,
12863 globals->bfd_of_glue_owner,
12864 ARM2THUMB_GLUE_SECTION_NAME))
12865 return FALSE;
12866
12867 if (! elf32_arm_output_glue_section (info, abfd,
12868 globals->bfd_of_glue_owner,
12869 THUMB2ARM_GLUE_SECTION_NAME))
12870 return FALSE;
12871
12872 if (! elf32_arm_output_glue_section (info, abfd,
12873 globals->bfd_of_glue_owner,
12874 VFP11_ERRATUM_VENEER_SECTION_NAME))
12875 return FALSE;
12876
a504d23a
LA		 12877 if (! elf32_arm_output_glue_section (info, abfd,
12878 globals->bfd_of_glue_owner,
12879 STM32L4XX_ERRATUM_VENEER_SECTION_NAME))
12880 return FALSE;
12881
3e6b1042
DJ		 12882 if (! elf32_arm_output_glue_section (info, abfd,
12883 globals->bfd_of_glue_owner,
12884 ARM_BX_GLUE_SECTION_NAME))
12885 return FALSE;
12886 }
12887
12888 return TRUE;
12889}
12890
5968a7b8
NC		 12891/* Return a best guess for the machine number based on the attributes. */
12892
12893static unsigned int
12894bfd_arm_get_mach_from_attributes (bfd * abfd)
12895{
12896 int arch = bfd_elf_get_obj_attr_int (abfd, OBJ_ATTR_PROC, Tag_CPU_arch);
12897
12898 switch (arch)
12899 {
12900 case TAG_CPU_ARCH_V4: return bfd_mach_arm_4;
12901 case TAG_CPU_ARCH_V4T: return bfd_mach_arm_4T;
12902 case TAG_CPU_ARCH_V5T: return bfd_mach_arm_5T;
12903
12904 case TAG_CPU_ARCH_V5TE:
12905 {
12906 char * name;
12907
12908 BFD_ASSERT (Tag_CPU_name < NUM_KNOWN_OBJ_ATTRIBUTES);
12909 name = elf_known_obj_attributes (abfd) [OBJ_ATTR_PROC][Tag_CPU_name].s;
12910
12911 if (name)
12912 {
12913 if (strcmp (name, "IWMMXT2") == 0)
12914 return bfd_mach_arm_iWMMXt2;
12915
12916 if (strcmp (name, "IWMMXT") == 0)
6034aab8 12917 return bfd_mach_arm_iWMMXt;
088ca6c1
NC		 12918
12919 if (strcmp (name, "XSCALE") == 0)
12920 {
12921 int wmmx;
12922
12923 BFD_ASSERT (Tag_WMMX_arch < NUM_KNOWN_OBJ_ATTRIBUTES);
12924 wmmx = elf_known_obj_attributes (abfd) [OBJ_ATTR_PROC][Tag_WMMX_arch].i;
12925 switch (wmmx)
12926 {
12927 case 1: return bfd_mach_arm_iWMMXt;
12928 case 2: return bfd_mach_arm_iWMMXt2;
12929 default: return bfd_mach_arm_XScale;
12930 }
12931 }
5968a7b8
NC		 12932 }
12933
12934 return bfd_mach_arm_5TE;
12935 }
12936
12937 default:
12938 return bfd_mach_arm_unknown;
12939 }
12940}
12941
c178919b
NC		 12942/* Set the right machine number. */
12943
12944static bfd_boolean
57e8b36a 12945elf32_arm_object_p (bfd *abfd)
c178919b 12946{
5a6c6817 12947 unsigned int mach;
57e8b36a 12948
5a6c6817 12949 mach = bfd_arm_get_mach_from_notes (abfd, ARM_NOTE_SECTION);
c178919b 12950
5968a7b8
NC		 12951 if (mach == bfd_mach_arm_unknown)
12952 {
12953 if (elf_elfheader (abfd)->e_flags & EF_ARM_MAVERICK_FLOAT)
12954 mach = bfd_mach_arm_ep9312;
12955 else
12956 mach = bfd_arm_get_mach_from_attributes (abfd);
12957 }
c178919b 12958
5968a7b8 12959 bfd_default_set_arch_mach (abfd, bfd_arch_arm, mach);
c178919b
NC		 12960 return TRUE;
12961}
12962
fc830a83 12963/* Function to keep ARM specific flags in the ELF header. */
3c9458e9 12964
b34976b6 12965static bfd_boolean
57e8b36a 12966elf32_arm_set_private_flags (bfd *abfd, flagword flags)
252b5132
RH		 12967{
12968 if (elf_flags_init (abfd)
12969 && elf_elfheader (abfd)->e_flags != flags)
12970 {
fc830a83
NC		 12971 if (EF_ARM_EABI_VERSION (flags) == EF_ARM_EABI_UNKNOWN)
12972 {
fd2ec330 12973 if (flags & EF_ARM_INTERWORK)
d003868e
AM		 12974 (*_bfd_error_handler)
12975 (_("Warning: Not setting interworking flag of %B since it has already been specified as non-interworking"),
12976 abfd);
fc830a83 12977 else
d003868e
AM		 12978 _bfd_error_handler
12979 (_("Warning: Clearing the interworking flag of %B due to outside request"),
12980 abfd);
fc830a83 12981 }
252b5132
RH		 12982 }
12983 else
12984 {
12985 elf_elfheader (abfd)->e_flags = flags;
b34976b6 12986 elf_flags_init (abfd) = TRUE;
252b5132
RH		 12987 }
12988
b34976b6 12989 return TRUE;
252b5132
RH		 12990}
12991
fc830a83 12992/* Copy backend specific data from one object module to another. */
9b485d32 12993
b34976b6 12994static bfd_boolean
57e8b36a 12995elf32_arm_copy_private_bfd_data (bfd *ibfd, bfd *obfd)
252b5132
RH		 12996{
12997 flagword in_flags;
12998 flagword out_flags;
12999
0ffa91dd 13000 if (! is_arm_elf (ibfd) || ! is_arm_elf (obfd))
b34976b6 13001 return TRUE;
252b5132 13002
fc830a83 13003 in_flags = elf_elfheader (ibfd)->e_flags;
252b5132
RH		 13004 out_flags = elf_elfheader (obfd)->e_flags;
13005
fc830a83
NC		 13006 if (elf_flags_init (obfd)
13007 && EF_ARM_EABI_VERSION (out_flags) == EF_ARM_EABI_UNKNOWN
13008 && in_flags != out_flags)
252b5132 13009 {
252b5132 13010 /* Cannot mix APCS26 and APCS32 code. */
fd2ec330 13011 if ((in_flags & EF_ARM_APCS_26) != (out_flags & EF_ARM_APCS_26))
b34976b6 13012 return FALSE;
252b5132
RH		 13013
13014 /* Cannot mix float APCS and non-float APCS code. */
fd2ec330 13015 if ((in_flags & EF_ARM_APCS_FLOAT) != (out_flags & EF_ARM_APCS_FLOAT))
b34976b6 13016 return FALSE;
252b5132
RH		 13017
13018 /* If the src and dest have different interworking flags
99059e56 13019 then turn off the interworking bit. */
fd2ec330 13020 if ((in_flags & EF_ARM_INTERWORK) != (out_flags & EF_ARM_INTERWORK))
252b5132 13021 {
fd2ec330 13022 if (out_flags & EF_ARM_INTERWORK)
d003868e
AM		 13023 _bfd_error_handler
13024 (_("Warning: Clearing the interworking flag of %B because non-interworking code in %B has been linked with it"),
13025 obfd, ibfd);
252b5132 13026
fd2ec330 13027 in_flags &= ~EF_ARM_INTERWORK;
252b5132 13028 }
1006ba19
PB		 13029
13030 /* Likewise for PIC, though don't warn for this case. */
fd2ec330
PB		 13031 if ((in_flags & EF_ARM_PIC) != (out_flags & EF_ARM_PIC))
13032 in_flags &= ~EF_ARM_PIC;
252b5132
RH		 13033 }
13034
13035 elf_elfheader (obfd)->e_flags = in_flags;
b34976b6 13036 elf_flags_init (obfd) = TRUE;
252b5132 13037
e2349352 13038 return _bfd_elf_copy_private_bfd_data (ibfd, obfd);
ee065d83
PB		 13039}
13040
13041/* Values for Tag_ABI_PCS_R9_use. */
13042enum
13043{
13044 AEABI_R9_V6,
13045 AEABI_R9_SB,
13046 AEABI_R9_TLS,
13047 AEABI_R9_unused
13048};
13049
13050/* Values for Tag_ABI_PCS_RW_data. */
13051enum
13052{
13053 AEABI_PCS_RW_data_absolute,
13054 AEABI_PCS_RW_data_PCrel,
13055 AEABI_PCS_RW_data_SBrel,
13056 AEABI_PCS_RW_data_unused
13057};
13058
13059/* Values for Tag_ABI_enum_size. */
13060enum
13061{
13062 AEABI_enum_unused,
13063 AEABI_enum_short,
13064 AEABI_enum_wide,
13065 AEABI_enum_forced_wide
13066};
13067
104d59d1
JM		 13068/* Determine whether an object attribute tag takes an integer, a
13069 string or both. */
906e58ca 13070
104d59d1
JM		 13071static int
13072elf32_arm_obj_attrs_arg_type (int tag)
13073{
13074 if (tag == Tag_compatibility)
3483fe2e 13075 return ATTR_TYPE_FLAG_INT_VAL | ATTR_TYPE_FLAG_STR_VAL;
2d0bb761 13076 else if (tag == Tag_nodefaults)
3483fe2e
AS		 13077 return ATTR_TYPE_FLAG_INT_VAL | ATTR_TYPE_FLAG_NO_DEFAULT;
13078 else if (tag == Tag_CPU_raw_name || tag == Tag_CPU_name)
13079 return ATTR_TYPE_FLAG_STR_VAL;
104d59d1 13080 else if (tag < 32)
3483fe2e 13081 return ATTR_TYPE_FLAG_INT_VAL;
104d59d1 13082 else
3483fe2e 13083 return (tag & 1) != 0 ? ATTR_TYPE_FLAG_STR_VAL : ATTR_TYPE_FLAG_INT_VAL;
104d59d1
JM		 13084}
13085
5aa6ff7c
AS		 13086/* The ABI defines that Tag_conformance should be emitted first, and that
13087 Tag_nodefaults should be second (if either is defined). This sets those
13088 two positions, and bumps up the position of all the remaining tags to
13089 compensate. */
13090static int
13091elf32_arm_obj_attrs_order (int num)
13092{
3de4a297 13093 if (num == LEAST_KNOWN_OBJ_ATTRIBUTE)
5aa6ff7c 13094 return Tag_conformance;
3de4a297 13095 if (num == LEAST_KNOWN_OBJ_ATTRIBUTE + 1)
5aa6ff7c
AS		 13096 return Tag_nodefaults;
13097 if ((num - 2) < Tag_nodefaults)
13098 return num - 2;
13099 if ((num - 1) < Tag_conformance)
13100 return num - 1;
13101 return num;
13102}
13103
e8b36cd1
JM		 13104/* Attribute numbers >=64 (mod 128) can be safely ignored. */
13105static bfd_boolean
13106elf32_arm_obj_attrs_handle_unknown (bfd *abfd, int tag)
13107{
13108 if ((tag & 127) < 64)
13109 {
13110 _bfd_error_handler
13111 (_("%B: Unknown mandatory EABI object attribute %d"),
13112 abfd, tag);
13113 bfd_set_error (bfd_error_bad_value);
13114 return FALSE;
13115 }
13116 else
13117 {
13118 _bfd_error_handler
13119 (_("Warning: %B: Unknown EABI object attribute %d"),
13120 abfd, tag);
13121 return TRUE;
13122 }
13123}
13124
91e22acd
AS		 13125/* Read the architecture from the Tag_also_compatible_with attribute, if any.
13126 Returns -1 if no architecture could be read. */
13127
13128static int
13129get_secondary_compatible_arch (bfd *abfd)
13130{
13131 obj_attribute *attr =
13132 &elf_known_obj_attributes_proc (abfd)[Tag_also_compatible_with];
13133
13134 /* Note: the tag and its argument below are uleb128 values, though
13135 currently-defined values fit in one byte for each. */
13136 if (attr->s
13137 && attr->s[0] == Tag_CPU_arch
13138 && (attr->s[1] & 128) != 128
13139 && attr->s[2] == 0)
13140 return attr->s[1];
13141
13142 /* This tag is "safely ignorable", so don't complain if it looks funny. */
13143 return -1;
13144}
13145
13146/* Set, or unset, the architecture of the Tag_also_compatible_with attribute.
13147 The tag is removed if ARCH is -1. */
13148
8e79c3df 13149static void
91e22acd 13150set_secondary_compatible_arch (bfd *abfd, int arch)
8e79c3df 13151{
91e22acd
AS		 13152 obj_attribute *attr =
13153 &elf_known_obj_attributes_proc (abfd)[Tag_also_compatible_with];
8e79c3df 13154
91e22acd
AS		 13155 if (arch == -1)
13156 {
13157 attr->s = NULL;
13158 return;
8e79c3df 13159 }
91e22acd
AS		 13160
13161 /* Note: the tag and its argument below are uleb128 values, though
13162 currently-defined values fit in one byte for each. */
13163 if (!attr->s)
21d799b5 13164 attr->s = (char *) bfd_alloc (abfd, 3);
91e22acd
AS		 13165 attr->s[0] = Tag_CPU_arch;
13166 attr->s[1] = arch;
13167 attr->s[2] = '\0';
8e79c3df
CM		 13168}
13169
91e22acd
AS		 13170/* Combine two values for Tag_CPU_arch, taking secondary compatibility tags
13171 into account. */
13172
13173static int
13174tag_cpu_arch_combine (bfd *ibfd, int oldtag, int *secondary_compat_out,
13175 int newtag, int secondary_compat)
8e79c3df 13176{
91e22acd
AS		 13177#define T(X) TAG_CPU_ARCH_##X
13178 int tagl, tagh, result;
13179 const int v6t2[] =
13180 {
13181 T(V6T2), /* PRE_V4. */
13182 T(V6T2), /* V4. */
13183 T(V6T2), /* V4T. */
13184 T(V6T2), /* V5T. */
13185 T(V6T2), /* V5TE. */
13186 T(V6T2), /* V5TEJ. */
13187 T(V6T2), /* V6. */
13188 T(V7), /* V6KZ. */
13189 T(V6T2) /* V6T2. */
13190 };
13191 const int v6k[] =
13192 {
13193 T(V6K), /* PRE_V4. */
13194 T(V6K), /* V4. */
13195 T(V6K), /* V4T. */
13196 T(V6K), /* V5T. */
13197 T(V6K), /* V5TE. */
13198 T(V6K), /* V5TEJ. */
13199 T(V6K), /* V6. */
13200 T(V6KZ), /* V6KZ. */
13201 T(V7), /* V6T2. */
13202 T(V6K) /* V6K. */
13203 };
13204 const int v7[] =
13205 {
13206 T(V7), /* PRE_V4. */
13207 T(V7), /* V4. */
13208 T(V7), /* V4T. */
13209 T(V7), /* V5T. */
13210 T(V7), /* V5TE. */
13211 T(V7), /* V5TEJ. */
13212 T(V7), /* V6. */
13213 T(V7), /* V6KZ. */
13214 T(V7), /* V6T2. */
13215 T(V7), /* V6K. */
13216 T(V7) /* V7. */
13217 };
13218 const int v6_m[] =
13219 {
13220 -1, /* PRE_V4. */
13221 -1, /* V4. */
13222 T(V6K), /* V4T. */
13223 T(V6K), /* V5T. */
13224 T(V6K), /* V5TE. */
13225 T(V6K), /* V5TEJ. */
13226 T(V6K), /* V6. */
13227 T(V6KZ), /* V6KZ. */
13228 T(V7), /* V6T2. */
13229 T(V6K), /* V6K. */
13230 T(V7), /* V7. */
13231 T(V6_M) /* V6_M. */
13232 };
13233 const int v6s_m[] =
13234 {
13235 -1, /* PRE_V4. */
13236 -1, /* V4. */
13237 T(V6K), /* V4T. */
13238 T(V6K), /* V5T. */
13239 T(V6K), /* V5TE. */
13240 T(V6K), /* V5TEJ. */
13241 T(V6K), /* V6. */
13242 T(V6KZ), /* V6KZ. */
13243 T(V7), /* V6T2. */
13244 T(V6K), /* V6K. */
13245 T(V7), /* V7. */
13246 T(V6S_M), /* V6_M. */
13247 T(V6S_M) /* V6S_M. */
13248 };
9e3c6df6
PB		 13249 const int v7e_m[] =
13250 {
13251 -1, /* PRE_V4. */
13252 -1, /* V4. */
13253 T(V7E_M), /* V4T. */
13254 T(V7E_M), /* V5T. */
13255 T(V7E_M), /* V5TE. */
13256 T(V7E_M), /* V5TEJ. */
13257 T(V7E_M), /* V6. */
13258 T(V7E_M), /* V6KZ. */
13259 T(V7E_M), /* V6T2. */
13260 T(V7E_M), /* V6K. */
13261 T(V7E_M), /* V7. */
13262 T(V7E_M), /* V6_M. */
13263 T(V7E_M), /* V6S_M. */
13264 T(V7E_M) /* V7E_M. */
13265 };
bca38921
MGD		 13266 const int v8[] =
13267 {
13268 T(V8), /* PRE_V4. */
13269 T(V8), /* V4. */
13270 T(V8), /* V4T. */
13271 T(V8), /* V5T. */
13272 T(V8), /* V5TE. */
13273 T(V8), /* V5TEJ. */
13274 T(V8), /* V6. */
13275 T(V8), /* V6KZ. */
13276 T(V8), /* V6T2. */
13277 T(V8), /* V6K. */
13278 T(V8), /* V7. */
13279 T(V8), /* V6_M. */
13280 T(V8), /* V6S_M. */
13281 T(V8), /* V7E_M. */
13282 T(V8) /* V8. */
13283 };
2fd158eb
TP		 13284 const int v8m_baseline[] =
13285 {
13286 -1, /* PRE_V4. */
13287 -1, /* V4. */
13288 -1, /* V4T. */
13289 -1, /* V5T. */
13290 -1, /* V5TE. */
13291 -1, /* V5TEJ. */
13292 -1, /* V6. */
13293 -1, /* V6KZ. */
13294 -1, /* V6T2. */
13295 -1, /* V6K. */
13296 -1, /* V7. */
13297 T(V8M_BASE), /* V6_M. */
13298 T(V8M_BASE), /* V6S_M. */
13299 -1, /* V7E_M. */
13300 -1, /* V8. */
13301 -1,
13302 T(V8M_BASE) /* V8-M BASELINE. */
13303 };
13304 const int v8m_mainline[] =
13305 {
13306 -1, /* PRE_V4. */
13307 -1, /* V4. */
13308 -1, /* V4T. */
13309 -1, /* V5T. */
13310 -1, /* V5TE. */
13311 -1, /* V5TEJ. */
13312 -1, /* V6. */
13313 -1, /* V6KZ. */
13314 -1, /* V6T2. */
13315 -1, /* V6K. */
13316 T(V8M_MAIN), /* V7. */
13317 T(V8M_MAIN), /* V6_M. */
13318 T(V8M_MAIN), /* V6S_M. */
13319 T(V8M_MAIN), /* V7E_M. */
13320 -1, /* V8. */
13321 -1,
13322 T(V8M_MAIN), /* V8-M BASELINE. */
13323 T(V8M_MAIN) /* V8-M MAINLINE. */
13324 };
91e22acd
AS		 13325 const int v4t_plus_v6_m[] =
13326 {
13327 -1, /* PRE_V4. */
13328 -1, /* V4. */
13329 T(V4T), /* V4T. */
13330 T(V5T), /* V5T. */
13331 T(V5TE), /* V5TE. */
13332 T(V5TEJ), /* V5TEJ. */
13333 T(V6), /* V6. */
13334 T(V6KZ), /* V6KZ. */
13335 T(V6T2), /* V6T2. */
13336 T(V6K), /* V6K. */
13337 T(V7), /* V7. */
13338 T(V6_M), /* V6_M. */
13339 T(V6S_M), /* V6S_M. */
9e3c6df6 13340 T(V7E_M), /* V7E_M. */
bca38921 13341 T(V8), /* V8. */
4ed7ed8d 13342 -1, /* Unused. */
2fd158eb
TP		 13343 T(V8M_BASE), /* V8-M BASELINE. */
13344 T(V8M_MAIN), /* V8-M MAINLINE. */
91e22acd
AS		 13345 T(V4T_PLUS_V6_M) /* V4T plus V6_M. */
13346 };
13347 const int *comb[] =
13348 {
13349 v6t2,
13350 v6k,
13351 v7,
13352 v6_m,
13353 v6s_m,
9e3c6df6 13354 v7e_m,
bca38921 13355 v8,
4ed7ed8d 13356 NULL,
2fd158eb
TP		 13357 v8m_baseline,
13358 v8m_mainline,
91e22acd
AS		 13359 /* Pseudo-architecture. */
13360 v4t_plus_v6_m
13361 };
13362
13363 /* Check we've not got a higher architecture than we know about. */
13364
9e3c6df6 13365 if (oldtag > MAX_TAG_CPU_ARCH || newtag > MAX_TAG_CPU_ARCH)
91e22acd 13366 {
3895f852 13367 _bfd_error_handler (_("error: %B: Unknown CPU architecture"), ibfd);
91e22acd
AS		 13368 return -1;
13369 }
13370
13371 /* Override old tag if we have a Tag_also_compatible_with on the output. */
13372
13373 if ((oldtag == T(V6_M) && *secondary_compat_out == T(V4T))
13374 || (oldtag == T(V4T) && *secondary_compat_out == T(V6_M)))
13375 oldtag = T(V4T_PLUS_V6_M);
13376
13377 /* And override the new tag if we have a Tag_also_compatible_with on the
13378 input. */
13379
13380 if ((newtag == T(V6_M) && secondary_compat == T(V4T))
13381 || (newtag == T(V4T) && secondary_compat == T(V6_M)))
13382 newtag = T(V4T_PLUS_V6_M);
13383
13384 tagl = (oldtag < newtag) ? oldtag : newtag;
13385 result = tagh = (oldtag > newtag) ? oldtag : newtag;
13386
13387 /* Architectures before V6KZ add features monotonically. */
13388 if (tagh <= TAG_CPU_ARCH_V6KZ)
13389 return result;
13390
4ed7ed8d 13391 result = comb[tagh - T(V6T2)] ? comb[tagh - T(V6T2)][tagl] : -1;
91e22acd
AS		 13392
13393 /* Use Tag_CPU_arch == V4T and Tag_also_compatible_with (Tag_CPU_arch V6_M)
13394 as the canonical version. */
13395 if (result == T(V4T_PLUS_V6_M))
13396 {
13397 result = T(V4T);
13398 *secondary_compat_out = T(V6_M);
13399 }
13400 else
13401 *secondary_compat_out = -1;
13402
13403 if (result == -1)
13404 {
3895f852 13405 _bfd_error_handler (_("error: %B: Conflicting CPU architectures %d/%d"),
91e22acd
AS		 13406 ibfd, oldtag, newtag);
13407 return -1;
13408 }
13409
13410 return result;
13411#undef T
8e79c3df
CM		 13412}
13413
ac56ee8f
MGD		 13414/* Query attributes object to see if integer divide instructions may be
13415 present in an object. */
13416static bfd_boolean
13417elf32_arm_attributes_accept_div (const obj_attribute *attr)
13418{
13419 int arch = attr[Tag_CPU_arch].i;
13420 int profile = attr[Tag_CPU_arch_profile].i;
13421
13422 switch (attr[Tag_DIV_use].i)
13423 {
13424 case 0:
13425 /* Integer divide allowed if instruction contained in archetecture. */
13426 if (arch == TAG_CPU_ARCH_V7 && (profile == 'R' || profile == 'M'))
13427 return TRUE;
13428 else if (arch >= TAG_CPU_ARCH_V7E_M)
13429 return TRUE;
13430 else
13431 return FALSE;
13432
13433 case 1:
13434 /* Integer divide explicitly prohibited. */
13435 return FALSE;
13436
13437 default:
13438 /* Unrecognised case - treat as allowing divide everywhere. */
13439 case 2:
13440 /* Integer divide allowed in ARM state. */
13441 return TRUE;
13442 }
13443}
13444
13445/* Query attributes object to see if integer divide instructions are
13446 forbidden to be in the object. This is not the inverse of
13447 elf32_arm_attributes_accept_div. */
13448static bfd_boolean
13449elf32_arm_attributes_forbid_div (const obj_attribute *attr)
13450{
13451 return attr[Tag_DIV_use].i == 1;
13452}
13453
ee065d83
PB		 13454/* Merge EABI object attributes from IBFD into OBFD. Raise an error if there
13455 are conflicting attributes. */
906e58ca 13456
ee065d83
PB		 13457static bfd_boolean
13458elf32_arm_merge_eabi_attributes (bfd *ibfd, bfd *obfd)
13459{
104d59d1
JM		 13460 obj_attribute *in_attr;
13461 obj_attribute *out_attr;
ee065d83
PB		 13462 /* Some tags have 0 = don't care, 1 = strong requirement,
13463 2 = weak requirement. */
91e22acd 13464 static const int order_021[3] = {0, 2, 1};
ee065d83 13465 int i;
91e22acd 13466 bfd_boolean result = TRUE;
9274e9de 13467 const char *sec_name = get_elf_backend_data (ibfd)->obj_attrs_section;
ee065d83 13468
3e6b1042
DJ		 13469 /* Skip the linker stubs file. This preserves previous behavior
13470 of accepting unknown attributes in the first input file - but
13471 is that a bug? */
13472 if (ibfd->flags & BFD_LINKER_CREATED)
13473 return TRUE;
13474
9274e9de
TG		 13475 /* Skip any input that hasn't attribute section.
13476 This enables to link object files without attribute section with
13477 any others. */
13478 if (bfd_get_section_by_name (ibfd, sec_name) == NULL)
13479 return TRUE;
13480
104d59d1 13481 if (!elf_known_obj_attributes_proc (obfd)[0].i)
ee065d83
PB		 13482 {
13483 /* This is the first object. Copy the attributes. */
104d59d1 13484 _bfd_elf_copy_obj_attributes (ibfd, obfd);
004ae526 13485
cd21e546
MGD		 13486 out_attr = elf_known_obj_attributes_proc (obfd);
13487
004ae526
PB		 13488 /* Use the Tag_null value to indicate the attributes have been
13489 initialized. */
cd21e546 13490 out_attr[0].i = 1;
004ae526 13491
cd21e546
MGD		 13492 /* We do not output objects with Tag_MPextension_use_legacy - we move
13493 the attribute's value to Tag_MPextension_use. */
13494 if (out_attr[Tag_MPextension_use_legacy].i != 0)
13495 {
13496 if (out_attr[Tag_MPextension_use].i != 0
13497 && out_attr[Tag_MPextension_use_legacy].i
99059e56 13498 != out_attr[Tag_MPextension_use].i)
cd21e546
MGD		 13499 {
13500 _bfd_error_handler
13501 (_("Error: %B has both the current and legacy "
13502 "Tag_MPextension_use attributes"), ibfd);
13503 result = FALSE;
13504 }
13505
13506 out_attr[Tag_MPextension_use] =
13507 out_attr[Tag_MPextension_use_legacy];
13508 out_attr[Tag_MPextension_use_legacy].type = 0;
13509 out_attr[Tag_MPextension_use_legacy].i = 0;
13510 }
13511
13512 return result;
ee065d83
PB		 13513 }
13514
104d59d1
JM		 13515 in_attr = elf_known_obj_attributes_proc (ibfd);
13516 out_attr = elf_known_obj_attributes_proc (obfd);
ee065d83
PB		 13517 /* This needs to happen before Tag_ABI_FP_number_model is merged. */
13518 if (in_attr[Tag_ABI_VFP_args].i != out_attr[Tag_ABI_VFP_args].i)
13519 {
5c294fee
TG		 13520 /* Ignore mismatches if the object doesn't use floating point or is
13521 floating point ABI independent. */
13522 if (out_attr[Tag_ABI_FP_number_model].i == AEABI_FP_number_model_none
13523 || (in_attr[Tag_ABI_FP_number_model].i != AEABI_FP_number_model_none
13524 && out_attr[Tag_ABI_VFP_args].i == AEABI_VFP_args_compatible))
ee065d83 13525 out_attr[Tag_ABI_VFP_args].i = in_attr[Tag_ABI_VFP_args].i;
5c294fee
TG		 13526 else if (in_attr[Tag_ABI_FP_number_model].i != AEABI_FP_number_model_none
13527 && in_attr[Tag_ABI_VFP_args].i != AEABI_VFP_args_compatible)
ee065d83
PB		 13528 {
13529 _bfd_error_handler
3895f852 13530 (_("error: %B uses VFP register arguments, %B does not"),
deddc40b
NS		 13531 in_attr[Tag_ABI_VFP_args].i ? ibfd : obfd,
13532 in_attr[Tag_ABI_VFP_args].i ? obfd : ibfd);
91e22acd 13533 result = FALSE;
ee065d83
PB		 13534 }
13535 }
13536
3de4a297 13537 for (i = LEAST_KNOWN_OBJ_ATTRIBUTE; i < NUM_KNOWN_OBJ_ATTRIBUTES; i++)
ee065d83
PB		 13538 {
13539 /* Merge this attribute with existing attributes. */
13540 switch (i)
13541 {
13542 case Tag_CPU_raw_name:
13543 case Tag_CPU_name:
6a631e86 13544 /* These are merged after Tag_CPU_arch. */
ee065d83
PB		 13545 break;
13546
13547 case Tag_ABI_optimization_goals:
13548 case Tag_ABI_FP_optimization_goals:
13549 /* Use the first value seen. */
13550 break;
13551
13552 case Tag_CPU_arch:
91e22acd
AS		 13553 {
13554 int secondary_compat = -1, secondary_compat_out = -1;
13555 unsigned int saved_out_attr = out_attr[i].i;
70e99720
TG		 13556 int arch_attr;
13557 static const char *name_table[] =
13558 {
91e22acd
AS		 13559 /* These aren't real CPU names, but we can't guess
13560 that from the architecture version alone. */
13561 "Pre v4",
13562 "ARM v4",
13563 "ARM v4T",
13564 "ARM v5T",
13565 "ARM v5TE",
13566 "ARM v5TEJ",
13567 "ARM v6",
13568 "ARM v6KZ",
13569 "ARM v6T2",
13570 "ARM v6K",
13571 "ARM v7",
13572 "ARM v6-M",
bca38921 13573 "ARM v6S-M",
2fd158eb
TP		 13574 "ARM v8",
13575 "",
13576 "ARM v8-M.baseline",
13577 "ARM v8-M.mainline",
91e22acd
AS		 13578 };
13579
13580 /* Merge Tag_CPU_arch and Tag_also_compatible_with. */
13581 secondary_compat = get_secondary_compatible_arch (ibfd);
13582 secondary_compat_out = get_secondary_compatible_arch (obfd);
70e99720
TG		 13583 arch_attr = tag_cpu_arch_combine (ibfd, out_attr[i].i,
13584 &secondary_compat_out,
13585 in_attr[i].i,
13586 secondary_compat);
13587
13588 /* Return with error if failed to merge. */
13589 if (arch_attr == -1)
13590 return FALSE;
13591
13592 out_attr[i].i = arch_attr;
13593
91e22acd
AS		 13594 set_secondary_compatible_arch (obfd, secondary_compat_out);
13595
13596 /* Merge Tag_CPU_name and Tag_CPU_raw_name. */
13597 if (out_attr[i].i == saved_out_attr)
13598 ; /* Leave the names alone. */
13599 else if (out_attr[i].i == in_attr[i].i)
13600 {
13601 /* The output architecture has been changed to match the
13602 input architecture. Use the input names. */
13603 out_attr[Tag_CPU_name].s = in_attr[Tag_CPU_name].s
13604 ? _bfd_elf_attr_strdup (obfd, in_attr[Tag_CPU_name].s)
13605 : NULL;
13606 out_attr[Tag_CPU_raw_name].s = in_attr[Tag_CPU_raw_name].s
13607 ? _bfd_elf_attr_strdup (obfd, in_attr[Tag_CPU_raw_name].s)
13608 : NULL;
13609 }
13610 else
13611 {
13612 out_attr[Tag_CPU_name].s = NULL;
13613 out_attr[Tag_CPU_raw_name].s = NULL;
13614 }
13615
13616 /* If we still don't have a value for Tag_CPU_name,
13617 make one up now. Tag_CPU_raw_name remains blank. */
13618 if (out_attr[Tag_CPU_name].s == NULL
13619 && out_attr[i].i < ARRAY_SIZE (name_table))
13620 out_attr[Tag_CPU_name].s =
13621 _bfd_elf_attr_strdup (obfd, name_table[out_attr[i].i]);
13622 }
13623 break;
13624
ee065d83
PB		 13625 case Tag_ARM_ISA_use:
13626 case Tag_THUMB_ISA_use:
ee065d83 13627 case Tag_WMMX_arch:
91e22acd
AS		 13628 case Tag_Advanced_SIMD_arch:
13629 /* ??? Do Advanced_SIMD (NEON) and WMMX conflict? */
ee065d83 13630 case Tag_ABI_FP_rounding:
ee065d83
PB		 13631 case Tag_ABI_FP_exceptions:
13632 case Tag_ABI_FP_user_exceptions:
13633 case Tag_ABI_FP_number_model:
75375b3e 13634 case Tag_FP_HP_extension:
91e22acd
AS		 13635 case Tag_CPU_unaligned_access:
13636 case Tag_T2EE_use:
91e22acd 13637 case Tag_MPextension_use:
ee065d83
PB		 13638 /* Use the largest value specified. */
13639 if (in_attr[i].i > out_attr[i].i)
13640 out_attr[i].i = in_attr[i].i;
13641 break;
13642
75375b3e 13643 case Tag_ABI_align_preserved:
91e22acd
AS		 13644 case Tag_ABI_PCS_RO_data:
13645 /* Use the smallest value specified. */
13646 if (in_attr[i].i < out_attr[i].i)
13647 out_attr[i].i = in_attr[i].i;
13648 break;
13649
75375b3e 13650 case Tag_ABI_align_needed:
91e22acd 13651 if ((in_attr[i].i > 0 || out_attr[i].i > 0)
75375b3e
MGD		 13652 && (in_attr[Tag_ABI_align_preserved].i == 0
13653 || out_attr[Tag_ABI_align_preserved].i == 0))
ee065d83 13654 {
91e22acd
AS		 13655 /* This error message should be enabled once all non-conformant
13656 binaries in the toolchain have had the attributes set
13657 properly.
ee065d83 13658 _bfd_error_handler
3895f852 13659 (_("error: %B: 8-byte data alignment conflicts with %B"),
91e22acd
AS		 13660 obfd, ibfd);
13661 result = FALSE; */
ee065d83 13662 }
91e22acd
AS		 13663 /* Fall through. */
13664 case Tag_ABI_FP_denormal:
13665 case Tag_ABI_PCS_GOT_use:
13666 /* Use the "greatest" from the sequence 0, 2, 1, or the largest
13667 value if greater than 2 (for future-proofing). */
13668 if ((in_attr[i].i > 2 && in_attr[i].i > out_attr[i].i)
13669 || (in_attr[i].i <= 2 && out_attr[i].i <= 2
13670 && order_021[in_attr[i].i] > order_021[out_attr[i].i]))
ee065d83
PB		 13671 out_attr[i].i = in_attr[i].i;
13672 break;
91e22acd 13673
75375b3e
MGD		 13674 case Tag_Virtualization_use:
13675 /* The virtualization tag effectively stores two bits of
13676 information: the intended use of TrustZone (in bit 0), and the
13677 intended use of Virtualization (in bit 1). */
13678 if (out_attr[i].i == 0)
13679 out_attr[i].i = in_attr[i].i;
13680 else if (in_attr[i].i != 0
13681 && in_attr[i].i != out_attr[i].i)
13682 {
13683 if (in_attr[i].i <= 3 && out_attr[i].i <= 3)
13684 out_attr[i].i = 3;
13685 else
13686 {
13687 _bfd_error_handler
13688 (_("error: %B: unable to merge virtualization attributes "
13689 "with %B"),
13690 obfd, ibfd);
13691 result = FALSE;
13692 }
13693 }
13694 break;
91e22acd
AS		 13695
13696 case Tag_CPU_arch_profile:
13697 if (out_attr[i].i != in_attr[i].i)
13698 {
13699 /* 0 will merge with anything.
13700 'A' and 'S' merge to 'A'.
13701 'R' and 'S' merge to 'R'.
99059e56 13702 'M' and 'A|R|S' is an error. */
91e22acd
AS		 13703 if (out_attr[i].i == 0
13704 || (out_attr[i].i == 'S'
13705 && (in_attr[i].i == 'A' || in_attr[i].i == 'R')))
13706 out_attr[i].i = in_attr[i].i;
13707 else if (in_attr[i].i == 0
13708 || (in_attr[i].i == 'S'
13709 && (out_attr[i].i == 'A' || out_attr[i].i == 'R')))
6a631e86 13710 ; /* Do nothing. */
91e22acd
AS		 13711 else
13712 {
13713 _bfd_error_handler
3895f852 13714 (_("error: %B: Conflicting architecture profiles %c/%c"),
91e22acd
AS		 13715 ibfd,
13716 in_attr[i].i ? in_attr[i].i : '0',
13717 out_attr[i].i ? out_attr[i].i : '0');
13718 result = FALSE;
13719 }
13720 }
13721 break;
15afaa63
TP		 13722
13723 case Tag_DSP_extension:
13724 /* No need to change output value if any of:
13725 - pre (<=) ARMv5T input architecture (do not have DSP)
13726 - M input profile not ARMv7E-M and do not have DSP. */
13727 if (in_attr[Tag_CPU_arch].i <= 3
13728 || (in_attr[Tag_CPU_arch_profile].i == 'M'
13729 && in_attr[Tag_CPU_arch].i != 13
13730 && in_attr[i].i == 0))
13731 ; /* Do nothing. */
13732 /* Output value should be 0 if DSP part of architecture, ie.
13733 - post (>=) ARMv5te architecture output
13734 - A, R or S profile output or ARMv7E-M output architecture. */
13735 else if (out_attr[Tag_CPU_arch].i >= 4
13736 && (out_attr[Tag_CPU_arch_profile].i == 'A'
13737 || out_attr[Tag_CPU_arch_profile].i == 'R'
13738 || out_attr[Tag_CPU_arch_profile].i == 'S'
13739 || out_attr[Tag_CPU_arch].i == 13))
13740 out_attr[i].i = 0;
13741 /* Otherwise, DSP instructions are added and not part of output
13742 architecture. */
13743 else
13744 out_attr[i].i = 1;
13745 break;
13746
75375b3e 13747 case Tag_FP_arch:
62f3b8c8 13748 {
4547cb56
NC		 13749 /* Tag_ABI_HardFP_use is handled along with Tag_FP_arch since
13750 the meaning of Tag_ABI_HardFP_use depends on Tag_FP_arch
13751 when it's 0. It might mean absence of FP hardware if
99654aaf 13752 Tag_FP_arch is zero. */
4547cb56 13753
a715796b 13754#define VFP_VERSION_COUNT 9
62f3b8c8
PB		 13755 static const struct
13756 {
13757 int ver;
13758 int regs;
bca38921 13759 } vfp_versions[VFP_VERSION_COUNT] =
62f3b8c8
PB		 13760 {
13761 {0, 0},
13762 {1, 16},
13763 {2, 16},
13764 {3, 32},
13765 {3, 16},
13766 {4, 32},
bca38921 13767 {4, 16},
a715796b
TG		 13768 {8, 32},
13769 {8, 16}
62f3b8c8
PB		 13770 };
13771 int ver;
13772 int regs;
13773 int newval;
13774
4547cb56
NC		 13775 /* If the output has no requirement about FP hardware,
13776 follow the requirement of the input. */
13777 if (out_attr[i].i == 0)
13778 {
13779 BFD_ASSERT (out_attr[Tag_ABI_HardFP_use].i == 0);
13780 out_attr[i].i = in_attr[i].i;
13781 out_attr[Tag_ABI_HardFP_use].i
13782 = in_attr[Tag_ABI_HardFP_use].i;
13783 break;
13784 }
13785 /* If the input has no requirement about FP hardware, do
13786 nothing. */
13787 else if (in_attr[i].i == 0)
13788 {
13789 BFD_ASSERT (in_attr[Tag_ABI_HardFP_use].i == 0);
13790 break;
13791 }
13792
13793 /* Both the input and the output have nonzero Tag_FP_arch.
99654aaf 13794 So Tag_ABI_HardFP_use is implied by Tag_FP_arch when it's zero. */
4547cb56
NC		 13795
13796 /* If both the input and the output have zero Tag_ABI_HardFP_use,
13797 do nothing. */
13798 if (in_attr[Tag_ABI_HardFP_use].i == 0
13799 && out_attr[Tag_ABI_HardFP_use].i == 0)
13800 ;
13801 /* If the input and the output have different Tag_ABI_HardFP_use,
99654aaf 13802 the combination of them is 0 (implied by Tag_FP_arch). */
4547cb56
NC		 13803 else if (in_attr[Tag_ABI_HardFP_use].i
13804 != out_attr[Tag_ABI_HardFP_use].i)
99654aaf 13805 out_attr[Tag_ABI_HardFP_use].i = 0;
4547cb56
NC		 13806
13807 /* Now we can handle Tag_FP_arch. */
13808
bca38921
MGD		 13809 /* Values of VFP_VERSION_COUNT or more aren't defined, so just
13810 pick the biggest. */
13811 if (in_attr[i].i >= VFP_VERSION_COUNT
13812 && in_attr[i].i > out_attr[i].i)
62f3b8c8
PB		 13813 {
13814 out_attr[i] = in_attr[i];
13815 break;
13816 }
13817 /* The output uses the superset of input features
13818 (ISA version) and registers. */
13819 ver = vfp_versions[in_attr[i].i].ver;
13820 if (ver < vfp_versions[out_attr[i].i].ver)
13821 ver = vfp_versions[out_attr[i].i].ver;
13822 regs = vfp_versions[in_attr[i].i].regs;
13823 if (regs < vfp_versions[out_attr[i].i].regs)
13824 regs = vfp_versions[out_attr[i].i].regs;
13825 /* This assumes all possible supersets are also a valid
99059e56 13826 options. */
bca38921 13827 for (newval = VFP_VERSION_COUNT - 1; newval > 0; newval--)
62f3b8c8
PB		 13828 {
13829 if (regs == vfp_versions[newval].regs
13830 && ver == vfp_versions[newval].ver)
13831 break;
13832 }
13833 out_attr[i].i = newval;
13834 }
b1cc4aeb 13835 break;
ee065d83
PB		 13836 case Tag_PCS_config:
13837 if (out_attr[i].i == 0)
13838 out_attr[i].i = in_attr[i].i;
b6009aca 13839 else if (in_attr[i].i != 0 && out_attr[i].i != in_attr[i].i)
ee065d83
PB		 13840 {
13841 /* It's sometimes ok to mix different configs, so this is only
99059e56 13842 a warning. */
ee065d83
PB		 13843 _bfd_error_handler
13844 (_("Warning: %B: Conflicting platform configuration"), ibfd);
13845 }
13846 break;
13847 case Tag_ABI_PCS_R9_use:
004ae526
PB		 13848 if (in_attr[i].i != out_attr[i].i
13849 && out_attr[i].i != AEABI_R9_unused
ee065d83
PB		 13850 && in_attr[i].i != AEABI_R9_unused)
13851 {
13852 _bfd_error_handler
3895f852 13853 (_("error: %B: Conflicting use of R9"), ibfd);
91e22acd 13854 result = FALSE;
ee065d83
PB		 13855 }
13856 if (out_attr[i].i == AEABI_R9_unused)
13857 out_attr[i].i = in_attr[i].i;
13858 break;
13859 case Tag_ABI_PCS_RW_data:
13860 if (in_attr[i].i == AEABI_PCS_RW_data_SBrel
13861 && out_attr[Tag_ABI_PCS_R9_use].i != AEABI_R9_SB
13862 && out_attr[Tag_ABI_PCS_R9_use].i != AEABI_R9_unused)
13863 {
13864 _bfd_error_handler
3895f852 13865 (_("error: %B: SB relative addressing conflicts with use of R9"),
ee065d83 13866 ibfd);
91e22acd 13867 result = FALSE;
ee065d83
PB		 13868 }
13869 /* Use the smallest value specified. */
13870 if (in_attr[i].i < out_attr[i].i)
13871 out_attr[i].i = in_attr[i].i;
13872 break;
ee065d83 13873 case Tag_ABI_PCS_wchar_t:
a9dc9481
JM		 13874 if (out_attr[i].i && in_attr[i].i && out_attr[i].i != in_attr[i].i
13875 && !elf_arm_tdata (obfd)->no_wchar_size_warning)
ee065d83
PB		 13876 {
13877 _bfd_error_handler
a9dc9481
JM		 13878 (_("warning: %B uses %u-byte wchar_t yet the output is to use %u-byte wchar_t; use of wchar_t values across objects may fail"),
13879 ibfd, in_attr[i].i, out_attr[i].i);
ee065d83 13880 }
a9dc9481 13881 else if (in_attr[i].i && !out_attr[i].i)
ee065d83
PB		 13882 out_attr[i].i = in_attr[i].i;
13883 break;
ee065d83
PB		 13884 case Tag_ABI_enum_size:
13885 if (in_attr[i].i != AEABI_enum_unused)
13886 {
13887 if (out_attr[i].i == AEABI_enum_unused
13888 || out_attr[i].i == AEABI_enum_forced_wide)
13889 {
13890 /* The existing object is compatible with anything.
13891 Use whatever requirements the new object has. */
13892 out_attr[i].i = in_attr[i].i;
13893 }
13894 else if (in_attr[i].i != AEABI_enum_forced_wide
bf21ed78 13895 && out_attr[i].i != in_attr[i].i
0ffa91dd 13896 && !elf_arm_tdata (obfd)->no_enum_size_warning)
ee065d83 13897 {
91e22acd 13898 static const char *aeabi_enum_names[] =
bf21ed78 13899 { "", "variable-size", "32-bit", "" };
91e22acd
AS		 13900 const char *in_name =
13901 in_attr[i].i < ARRAY_SIZE(aeabi_enum_names)
13902 ? aeabi_enum_names[in_attr[i].i]
13903 : "<unknown>";
13904 const char *out_name =
13905 out_attr[i].i < ARRAY_SIZE(aeabi_enum_names)
13906 ? aeabi_enum_names[out_attr[i].i]
13907 : "<unknown>";
ee065d83 13908 _bfd_error_handler
bf21ed78 13909 (_("warning: %B uses %s enums yet the output is to use %s enums; use of enum values across objects may fail"),
91e22acd 13910 ibfd, in_name, out_name);
ee065d83
PB		 13911 }
13912 }
13913 break;
13914 case Tag_ABI_VFP_args:
13915 /* Aready done. */
13916 break;
13917 case Tag_ABI_WMMX_args:
13918 if (in_attr[i].i != out_attr[i].i)
13919 {
13920 _bfd_error_handler
3895f852 13921 (_("error: %B uses iWMMXt register arguments, %B does not"),
ee065d83 13922 ibfd, obfd);
91e22acd 13923 result = FALSE;
ee065d83
PB		 13924 }
13925 break;
7b86a9fa
AS		 13926 case Tag_compatibility:
13927 /* Merged in target-independent code. */
13928 break;
91e22acd 13929 case Tag_ABI_HardFP_use:
4547cb56 13930 /* This is handled along with Tag_FP_arch. */
91e22acd
AS		 13931 break;
13932 case Tag_ABI_FP_16bit_format:
13933 if (in_attr[i].i != 0 && out_attr[i].i != 0)
13934 {
13935 if (in_attr[i].i != out_attr[i].i)
13936 {
13937 _bfd_error_handler
3895f852 13938 (_("error: fp16 format mismatch between %B and %B"),
91e22acd
AS		 13939 ibfd, obfd);
13940 result = FALSE;
13941 }
13942 }
13943 if (in_attr[i].i != 0)
13944 out_attr[i].i = in_attr[i].i;
13945 break;
7b86a9fa 13946
cd21e546 13947 case Tag_DIV_use:
ac56ee8f
MGD		 13948 /* A value of zero on input means that the divide instruction may
13949 be used if available in the base architecture as specified via
13950 Tag_CPU_arch and Tag_CPU_arch_profile. A value of 1 means that
13951 the user did not want divide instructions. A value of 2
13952 explicitly means that divide instructions were allowed in ARM
13953 and Thumb state. */
13954 if (in_attr[i].i == out_attr[i].i)
13955 /* Do nothing. */ ;
13956 else if (elf32_arm_attributes_forbid_div (in_attr)
13957 && !elf32_arm_attributes_accept_div (out_attr))
13958 out_attr[i].i = 1;
13959 else if (elf32_arm_attributes_forbid_div (out_attr)
13960 && elf32_arm_attributes_accept_div (in_attr))
13961 out_attr[i].i = in_attr[i].i;
13962 else if (in_attr[i].i == 2)
13963 out_attr[i].i = in_attr[i].i;
cd21e546
MGD		 13964 break;
13965
13966 case Tag_MPextension_use_legacy:
13967 /* We don't output objects with Tag_MPextension_use_legacy - we
13968 move the value to Tag_MPextension_use. */
13969 if (in_attr[i].i != 0 && in_attr[Tag_MPextension_use].i != 0)
13970 {
13971 if (in_attr[Tag_MPextension_use].i != in_attr[i].i)
13972 {
13973 _bfd_error_handler
13974 (_("%B has has both the current and legacy "
b38cadfb 13975 "Tag_MPextension_use attributes"),
cd21e546
MGD		 13976 ibfd);
13977 result = FALSE;
13978 }
13979 }
13980
13981 if (in_attr[i].i > out_attr[Tag_MPextension_use].i)
13982 out_attr[Tag_MPextension_use] = in_attr[i];
13983
13984 break;
13985
91e22acd 13986 case Tag_nodefaults:
2d0bb761
AS		 13987 /* This tag is set if it exists, but the value is unused (and is
13988 typically zero). We don't actually need to do anything here -
13989 the merge happens automatically when the type flags are merged
13990 below. */
91e22acd
AS		 13991 break;
13992 case Tag_also_compatible_with:
13993 /* Already done in Tag_CPU_arch. */
13994 break;
13995 case Tag_conformance:
13996 /* Keep the attribute if it matches. Throw it away otherwise.
13997 No attribute means no claim to conform. */
13998 if (!in_attr[i].s || !out_attr[i].s
13999 || strcmp (in_attr[i].s, out_attr[i].s) != 0)
14000 out_attr[i].s = NULL;
14001 break;
3cfad14c 14002
91e22acd 14003 default:
e8b36cd1
JM		 14004 result
14005 = result && _bfd_elf_merge_unknown_attribute_low (ibfd, obfd, i);
91e22acd
AS		 14006 }
14007
14008 /* If out_attr was copied from in_attr then it won't have a type yet. */
14009 if (in_attr[i].type && !out_attr[i].type)
14010 out_attr[i].type = in_attr[i].type;
ee065d83
PB		 14011 }
14012
104d59d1 14013 /* Merge Tag_compatibility attributes and any common GNU ones. */
5488d830
MGD		 14014 if (!_bfd_elf_merge_object_attributes (ibfd, obfd))
14015 return FALSE;
ee065d83 14016
104d59d1 14017 /* Check for any attributes not known on ARM. */
e8b36cd1 14018 result &= _bfd_elf_merge_unknown_attribute_list (ibfd, obfd);
91e22acd 14019
91e22acd 14020 return result;
252b5132
RH		 14021}
14022
3a4a14e9
PB		 14023
14024/* Return TRUE if the two EABI versions are incompatible. */
14025
14026static bfd_boolean
14027elf32_arm_versions_compatible (unsigned iver, unsigned over)
14028{
14029 /* v4 and v5 are the same spec before and after it was released,
14030 so allow mixing them. */
14031 if ((iver == EF_ARM_EABI_VER4 && over == EF_ARM_EABI_VER5)
14032 || (iver == EF_ARM_EABI_VER5 && over == EF_ARM_EABI_VER4))
14033 return TRUE;
14034
14035 return (iver == over);
14036}
14037
252b5132
RH		 14038/* Merge backend specific data from an object file to the output
14039 object file when linking. */
9b485d32 14040
b34976b6 14041static bfd_boolean
21d799b5 14042elf32_arm_merge_private_bfd_data (bfd * ibfd, bfd * obfd);
252b5132 14043
9b485d32
NC		 14044/* Display the flags field. */
14045
b34976b6 14046static bfd_boolean
57e8b36a 14047elf32_arm_print_private_bfd_data (bfd *abfd, void * ptr)
252b5132 14048{
fc830a83
NC		 14049 FILE * file = (FILE *) ptr;
14050 unsigned long flags;
252b5132
RH		 14051
14052 BFD_ASSERT (abfd != NULL && ptr != NULL);
14053
14054 /* Print normal ELF private data. */
14055 _bfd_elf_print_private_bfd_data (abfd, ptr);
14056
fc830a83 14057 flags = elf_elfheader (abfd)->e_flags;
9b485d32
NC		 14058 /* Ignore init flag - it may not be set, despite the flags field
14059 containing valid data. */
252b5132
RH		 14060
14061 /* xgettext:c-format */
9b485d32 14062 fprintf (file, _("private flags = %lx:"), elf_elfheader (abfd)->e_flags);
252b5132 14063
fc830a83
NC		 14064 switch (EF_ARM_EABI_VERSION (flags))
14065 {
14066 case EF_ARM_EABI_UNKNOWN:
4cc11e76 14067 /* The following flag bits are GNU extensions and not part of the
fc830a83
NC		 14068 official ARM ELF extended ABI. Hence they are only decoded if
14069 the EABI version is not set. */
fd2ec330 14070 if (flags & EF_ARM_INTERWORK)
9b485d32 14071 fprintf (file, _(" [interworking enabled]"));
9a5aca8c 14072
fd2ec330 14073 if (flags & EF_ARM_APCS_26)
6c571f00 14074 fprintf (file, " [APCS-26]");
fc830a83 14075 else
6c571f00 14076 fprintf (file, " [APCS-32]");
9a5aca8c 14077
96a846ea
RE		 14078 if (flags & EF_ARM_VFP_FLOAT)
14079 fprintf (file, _(" [VFP float format]"));
fde78edd
NC		 14080 else if (flags & EF_ARM_MAVERICK_FLOAT)
14081 fprintf (file, _(" [Maverick float format]"));
96a846ea
RE		 14082 else
14083 fprintf (file, _(" [FPA float format]"));
14084
fd2ec330 14085 if (flags & EF_ARM_APCS_FLOAT)
9b485d32 14086 fprintf (file, _(" [floats passed in float registers]"));
9a5aca8c 14087
fd2ec330 14088 if (flags & EF_ARM_PIC)
9b485d32 14089 fprintf (file, _(" [position independent]"));
fc830a83 14090
fd2ec330 14091 if (flags & EF_ARM_NEW_ABI)
9b485d32 14092 fprintf (file, _(" [new ABI]"));
9a5aca8c 14093
fd2ec330 14094 if (flags & EF_ARM_OLD_ABI)
9b485d32 14095 fprintf (file, _(" [old ABI]"));
9a5aca8c 14096
fd2ec330 14097 if (flags & EF_ARM_SOFT_FLOAT)
9b485d32 14098 fprintf (file, _(" [software FP]"));
9a5aca8c 14099
96a846ea
RE		 14100 flags &= ~(EF_ARM_INTERWORK | EF_ARM_APCS_26 | EF_ARM_APCS_FLOAT
14101 | EF_ARM_PIC | EF_ARM_NEW_ABI | EF_ARM_OLD_ABI
fde78edd
NC		 14102 | EF_ARM_SOFT_FLOAT | EF_ARM_VFP_FLOAT
14103 | EF_ARM_MAVERICK_FLOAT);
fc830a83 14104 break;
9a5aca8c 14105
fc830a83 14106 case EF_ARM_EABI_VER1:
9b485d32 14107 fprintf (file, _(" [Version1 EABI]"));
9a5aca8c 14108
fc830a83 14109 if (flags & EF_ARM_SYMSARESORTED)
9b485d32 14110 fprintf (file, _(" [sorted symbol table]"));
fc830a83 14111 else
9b485d32 14112 fprintf (file, _(" [unsorted symbol table]"));
9a5aca8c 14113
fc830a83
NC		 14114 flags &= ~ EF_ARM_SYMSARESORTED;
14115 break;
9a5aca8c 14116
fd2ec330
PB		 14117 case EF_ARM_EABI_VER2:
14118 fprintf (file, _(" [Version2 EABI]"));
14119
14120 if (flags & EF_ARM_SYMSARESORTED)
14121 fprintf (file, _(" [sorted symbol table]"));
14122 else
14123 fprintf (file, _(" [unsorted symbol table]"));
14124
14125 if (flags & EF_ARM_DYNSYMSUSESEGIDX)
14126 fprintf (file, _(" [dynamic symbols use segment index]"));
14127
14128 if (flags & EF_ARM_MAPSYMSFIRST)
14129 fprintf (file, _(" [mapping symbols precede others]"));
14130
99e4ae17 14131 flags &= ~(EF_ARM_SYMSARESORTED | EF_ARM_DYNSYMSUSESEGIDX
fd2ec330
PB		 14132 | EF_ARM_MAPSYMSFIRST);
14133 break;
14134
d507cf36
PB		 14135 case EF_ARM_EABI_VER3:
14136 fprintf (file, _(" [Version3 EABI]"));
8cb51566
PB		 14137 break;
14138
14139 case EF_ARM_EABI_VER4:
14140 fprintf (file, _(" [Version4 EABI]"));
3a4a14e9 14141 goto eabi;
d507cf36 14142
3a4a14e9
PB		 14143 case EF_ARM_EABI_VER5:
14144 fprintf (file, _(" [Version5 EABI]"));
3bfcb652
NC		 14145
14146 if (flags & EF_ARM_ABI_FLOAT_SOFT)
14147 fprintf (file, _(" [soft-float ABI]"));
14148
14149 if (flags & EF_ARM_ABI_FLOAT_HARD)
14150 fprintf (file, _(" [hard-float ABI]"));
14151
14152 flags &= ~(EF_ARM_ABI_FLOAT_SOFT | EF_ARM_ABI_FLOAT_HARD);
14153
3a4a14e9 14154 eabi:
d507cf36
PB		 14155 if (flags & EF_ARM_BE8)
14156 fprintf (file, _(" [BE8]"));
14157
14158 if (flags & EF_ARM_LE8)
14159 fprintf (file, _(" [LE8]"));
14160
14161 flags &= ~(EF_ARM_LE8 | EF_ARM_BE8);
14162 break;
14163
fc830a83 14164 default:
9b485d32 14165 fprintf (file, _(" <EABI version unrecognised>"));
fc830a83
NC		 14166 break;
14167 }
252b5132 14168
fc830a83 14169 flags &= ~ EF_ARM_EABIMASK;
252b5132 14170
fc830a83 14171 if (flags & EF_ARM_RELEXEC)
9b485d32 14172 fprintf (file, _(" [relocatable executable]"));
252b5132 14173
a5721edd 14174 flags &= ~EF_ARM_RELEXEC;
fc830a83
NC		 14175
14176 if (flags)
9b485d32 14177 fprintf (file, _("<Unrecognised flag bits set>"));
9a5aca8c 14178
252b5132
RH		 14179 fputc ('\n', file);
14180
b34976b6 14181 return TRUE;
252b5132
RH		 14182}
14183
14184static int
57e8b36a 14185elf32_arm_get_symbol_type (Elf_Internal_Sym * elf_sym, int type)
252b5132 14186{
2f0ca46a
NC		 14187 switch (ELF_ST_TYPE (elf_sym->st_info))
14188 {
14189 case STT_ARM_TFUNC:
14190 return ELF_ST_TYPE (elf_sym->st_info);
ce855c42 14191
2f0ca46a
NC		 14192 case STT_ARM_16BIT:
14193 /* If the symbol is not an object, return the STT_ARM_16BIT flag.
14194 This allows us to distinguish between data used by Thumb instructions
14195 and non-data (which is probably code) inside Thumb regions of an
14196 executable. */
1a0eb693 14197 if (type != STT_OBJECT && type != STT_TLS)
2f0ca46a
NC		 14198 return ELF_ST_TYPE (elf_sym->st_info);
14199 break;
9a5aca8c 14200
ce855c42
NC		 14201 default:
14202 break;
2f0ca46a
NC		 14203 }
14204
14205 return type;
252b5132 14206}
f21f3fe0 14207
252b5132 14208static asection *
07adf181
AM		 14209elf32_arm_gc_mark_hook (asection *sec,
14210 struct bfd_link_info *info,
14211 Elf_Internal_Rela *rel,
14212 struct elf_link_hash_entry *h,
14213 Elf_Internal_Sym *sym)
252b5132
RH		 14214{
14215 if (h != NULL)
07adf181 14216 switch (ELF32_R_TYPE (rel->r_info))
252b5132
RH		 14217 {
14218 case R_ARM_GNU_VTINHERIT:
14219 case R_ARM_GNU_VTENTRY:
07adf181
AM		 14220 return NULL;
14221 }
9ad5cbcf 14222
07adf181 14223 return _bfd_elf_gc_mark_hook (sec, info, rel, h, sym);
252b5132
RH		 14224}
14225
780a67af
NC		 14226/* Update the got entry reference counts for the section being removed. */
14227
b34976b6 14228static bfd_boolean
ba93b8ac
DJ		 14229elf32_arm_gc_sweep_hook (bfd * abfd,
14230 struct bfd_link_info * info,
14231 asection * sec,
14232 const Elf_Internal_Rela * relocs)
252b5132 14233{
5e681ec4
PB		 14234 Elf_Internal_Shdr *symtab_hdr;
14235 struct elf_link_hash_entry **sym_hashes;
14236 bfd_signed_vma *local_got_refcounts;
14237 const Elf_Internal_Rela *rel, *relend;
eb043451
PB		 14238 struct elf32_arm_link_hash_table * globals;
14239
0e1862bb 14240 if (bfd_link_relocatable (info))
7dda2462
TG		 14241 return TRUE;
14242
eb043451 14243 globals = elf32_arm_hash_table (info);
4dfe6ac6
NC		 14244 if (globals == NULL)
14245 return FALSE;
5e681ec4
PB		 14246
14247 elf_section_data (sec)->local_dynrel = NULL;
14248
0ffa91dd 14249 symtab_hdr = & elf_symtab_hdr (abfd);
5e681ec4
PB		 14250 sym_hashes = elf_sym_hashes (abfd);
14251 local_got_refcounts = elf_local_got_refcounts (abfd);
14252
906e58ca 14253 check_use_blx (globals);
bd97cb95 14254
5e681ec4
PB		 14255 relend = relocs + sec->reloc_count;
14256 for (rel = relocs; rel < relend; rel++)
eb043451 14257 {
3eb128b2
AM		 14258 unsigned long r_symndx;
14259 struct elf_link_hash_entry *h = NULL;
f6e32f6d 14260 struct elf32_arm_link_hash_entry *eh;
eb043451 14261 int r_type;
34e77a92 14262 bfd_boolean call_reloc_p;
f6e32f6d
RS		 14263 bfd_boolean may_become_dynamic_p;
14264 bfd_boolean may_need_local_target_p;
34e77a92
RS		 14265 union gotplt_union *root_plt;
14266 struct arm_plt_info *arm_plt;
5e681ec4 14267
3eb128b2
AM		 14268 r_symndx = ELF32_R_SYM (rel->r_info);
14269 if (r_symndx >= symtab_hdr->sh_info)
14270 {
14271 h = sym_hashes[r_symndx - symtab_hdr->sh_info];
14272 while (h->root.type == bfd_link_hash_indirect
14273 || h->root.type == bfd_link_hash_warning)
14274 h = (struct elf_link_hash_entry *) h->root.u.i.link;
14275 }
f6e32f6d
RS		 14276 eh = (struct elf32_arm_link_hash_entry *) h;
14277
34e77a92 14278 call_reloc_p = FALSE;
f6e32f6d
RS		 14279 may_become_dynamic_p = FALSE;
14280 may_need_local_target_p = FALSE;
3eb128b2 14281
eb043451 14282 r_type = ELF32_R_TYPE (rel->r_info);
eb043451 14283 r_type = arm_real_reloc_type (globals, r_type);
eb043451
PB		 14284 switch (r_type)
14285 {
14286 case R_ARM_GOT32:
eb043451 14287 case R_ARM_GOT_PREL:
ba93b8ac
DJ		 14288 case R_ARM_TLS_GD32:
14289 case R_ARM_TLS_IE32:
3eb128b2 14290 if (h != NULL)
eb043451 14291 {
eb043451
PB		 14292 if (h->got.refcount > 0)
14293 h->got.refcount -= 1;
14294 }
14295 else if (local_got_refcounts != NULL)
14296 {
14297 if (local_got_refcounts[r_symndx] > 0)
14298 local_got_refcounts[r_symndx] -= 1;
14299 }
14300 break;
14301
ba93b8ac 14302 case R_ARM_TLS_LDM32:
4dfe6ac6 14303 globals->tls_ldm_got.refcount -= 1;
ba93b8ac
DJ		 14304 break;
14305
eb043451
PB		 14306 case R_ARM_PC24:
14307 case R_ARM_PLT32:
5b5bb741
PB		 14308 case R_ARM_CALL:
14309 case R_ARM_JUMP24:
eb043451 14310 case R_ARM_PREL31:
c19d1205 14311 case R_ARM_THM_CALL:
bd97cb95
DJ		 14312 case R_ARM_THM_JUMP24:
14313 case R_ARM_THM_JUMP19:
34e77a92 14314 call_reloc_p = TRUE;
f6e32f6d
RS		 14315 may_need_local_target_p = TRUE;
14316 break;
14317
14318 case R_ARM_ABS12:
14319 if (!globals->vxworks_p)
14320 {
14321 may_need_local_target_p = TRUE;
14322 break;
14323 }
14324 /* Fall through. */
14325 case R_ARM_ABS32:
14326 case R_ARM_ABS32_NOI:
14327 case R_ARM_REL32:
14328 case R_ARM_REL32_NOI:
b6895b4f
PB		 14329 case R_ARM_MOVW_ABS_NC:
14330 case R_ARM_MOVT_ABS:
14331 case R_ARM_MOVW_PREL_NC:
14332 case R_ARM_MOVT_PREL:
14333 case R_ARM_THM_MOVW_ABS_NC:
14334 case R_ARM_THM_MOVT_ABS:
14335 case R_ARM_THM_MOVW_PREL_NC:
14336 case R_ARM_THM_MOVT_PREL:
b7693d02 14337 /* Should the interworking branches be here also? */
0e1862bb 14338 if ((bfd_link_pic (info) || globals->root.is_relocatable_executable)
34e77a92
RS		 14339 && (sec->flags & SEC_ALLOC) != 0)
14340 {
14341 if (h == NULL
469a3493 14342 && elf32_arm_howto_from_type (r_type)->pc_relative)
34e77a92
RS		 14343 {
14344 call_reloc_p = TRUE;
14345 may_need_local_target_p = TRUE;
14346 }
14347 else
14348 may_become_dynamic_p = TRUE;
14349 }
f6e32f6d
RS		 14350 else
14351 may_need_local_target_p = TRUE;
14352 break;
b7693d02 14353
f6e32f6d
RS		 14354 default:
14355 break;
14356 }
5e681ec4 14357
34e77a92 14358 if (may_need_local_target_p
4ba2ef8f
TP		 14359 && elf32_arm_get_plt_info (abfd, globals, eh, r_symndx, &root_plt,
14360 &arm_plt))
f6e32f6d 14361 {
27586251
HPN		 14362 /* If PLT refcount book-keeping is wrong and too low, we'll
14363 see a zero value (going to -1) for the root PLT reference
14364 count. */
14365 if (root_plt->refcount >= 0)
14366 {
14367 BFD_ASSERT (root_plt->refcount != 0);
14368 root_plt->refcount -= 1;
14369 }
14370 else
14371 /* A value of -1 means the symbol has become local, forced
14372 or seeing a hidden definition. Any other negative value
14373 is an error. */
14374 BFD_ASSERT (root_plt->refcount == -1);
34e77a92
RS		 14375
14376 if (!call_reloc_p)
14377 arm_plt->noncall_refcount--;
5e681ec4 14378
f6e32f6d 14379 if (r_type == R_ARM_THM_CALL)
34e77a92 14380 arm_plt->maybe_thumb_refcount--;
bd97cb95 14381
f6e32f6d
RS		 14382 if (r_type == R_ARM_THM_JUMP24
14383 || r_type == R_ARM_THM_JUMP19)
34e77a92 14384 arm_plt->thumb_refcount--;
f6e32f6d 14385 }
5e681ec4 14386
34e77a92 14387 if (may_become_dynamic_p)
f6e32f6d
RS		 14388 {
14389 struct elf_dyn_relocs **pp;
14390 struct elf_dyn_relocs *p;
5e681ec4 14391
34e77a92 14392 if (h != NULL)
9c489990 14393 pp = &(eh->dyn_relocs);
34e77a92
RS		 14394 else
14395 {
14396 Elf_Internal_Sym *isym;
14397
14398 isym = bfd_sym_from_r_symndx (&globals->sym_cache,
14399 abfd, r_symndx);
14400 if (isym == NULL)
14401 return FALSE;
14402 pp = elf32_arm_get_local_dynreloc_list (abfd, r_symndx, isym);
14403 if (pp == NULL)
14404 return FALSE;
14405 }
9c489990 14406 for (; (p = *pp) != NULL; pp = &p->next)
f6e32f6d
RS		 14407 if (p->sec == sec)
14408 {
14409 /* Everything must go for SEC. */
14410 *pp = p->next;
14411 break;
14412 }
eb043451
PB		 14413 }
14414 }
5e681ec4 14415
b34976b6 14416 return TRUE;
252b5132
RH		 14417}
14418
780a67af
NC		 14419/* Look through the relocs for a section during the first phase. */
14420
b34976b6 14421static bfd_boolean
57e8b36a
NC		 14422elf32_arm_check_relocs (bfd *abfd, struct bfd_link_info *info,
14423 asection *sec, const Elf_Internal_Rela *relocs)
252b5132 14424{
b34976b6
AM		 14425 Elf_Internal_Shdr *symtab_hdr;
14426 struct elf_link_hash_entry **sym_hashes;
b34976b6
AM		 14427 const Elf_Internal_Rela *rel;
14428 const Elf_Internal_Rela *rel_end;
14429 bfd *dynobj;
5e681ec4 14430 asection *sreloc;
5e681ec4 14431 struct elf32_arm_link_hash_table *htab;
f6e32f6d
RS		 14432 bfd_boolean call_reloc_p;
14433 bfd_boolean may_become_dynamic_p;
14434 bfd_boolean may_need_local_target_p;
ce98a316 14435 unsigned long nsyms;
9a5aca8c 14436
0e1862bb 14437 if (bfd_link_relocatable (info))
b34976b6 14438 return TRUE;
9a5aca8c 14439
0ffa91dd
NC		 14440 BFD_ASSERT (is_arm_elf (abfd));
14441
5e681ec4 14442 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 14443 if (htab == NULL)
14444 return FALSE;
14445
5e681ec4 14446 sreloc = NULL;
9a5aca8c 14447
67687978
PB		 14448 /* Create dynamic sections for relocatable executables so that we can
14449 copy relocations. */
14450 if (htab->root.is_relocatable_executable
14451 && ! htab->root.dynamic_sections_created)
14452 {
14453 if (! _bfd_elf_link_create_dynamic_sections (abfd, info))
14454 return FALSE;
14455 }
14456
cbc704f3
RS		 14457 if (htab->root.dynobj == NULL)
14458 htab->root.dynobj = abfd;
34e77a92
RS		 14459 if (!create_ifunc_sections (info))
14460 return FALSE;
cbc704f3
RS		 14461
14462 dynobj = htab->root.dynobj;
14463
0ffa91dd 14464 symtab_hdr = & elf_symtab_hdr (abfd);
252b5132 14465 sym_hashes = elf_sym_hashes (abfd);
ce98a316 14466 nsyms = NUM_SHDR_ENTRIES (symtab_hdr);
b38cadfb 14467
252b5132
RH		 14468 rel_end = relocs + sec->reloc_count;
14469 for (rel = relocs; rel < rel_end; rel++)
14470 {
34e77a92 14471 Elf_Internal_Sym *isym;
252b5132 14472 struct elf_link_hash_entry *h;
b7693d02 14473 struct elf32_arm_link_hash_entry *eh;
252b5132 14474 unsigned long r_symndx;
eb043451 14475 int r_type;
9a5aca8c 14476
252b5132 14477 r_symndx = ELF32_R_SYM (rel->r_info);
eb043451 14478 r_type = ELF32_R_TYPE (rel->r_info);
eb043451 14479 r_type = arm_real_reloc_type (htab, r_type);
ba93b8ac 14480
ce98a316
NC		 14481 if (r_symndx >= nsyms
14482 /* PR 9934: It is possible to have relocations that do not
14483 refer to symbols, thus it is also possible to have an
14484 object file containing relocations but no symbol table. */
cf35638d 14485 && (r_symndx > STN_UNDEF || nsyms > 0))
ba93b8ac
DJ		 14486 {
14487 (*_bfd_error_handler) (_("%B: bad symbol index: %d"), abfd,
ce98a316 14488 r_symndx);
ba93b8ac
DJ		 14489 return FALSE;
14490 }
14491
34e77a92
RS		 14492 h = NULL;
14493 isym = NULL;
14494 if (nsyms > 0)
973a3492 14495 {
34e77a92
RS		 14496 if (r_symndx < symtab_hdr->sh_info)
14497 {
14498 /* A local symbol. */
14499 isym = bfd_sym_from_r_symndx (&htab->sym_cache,
14500 abfd, r_symndx);
14501 if (isym == NULL)
14502 return FALSE;
14503 }
14504 else
14505 {
14506 h = sym_hashes[r_symndx - symtab_hdr->sh_info];
14507 while (h->root.type == bfd_link_hash_indirect
14508 || h->root.type == bfd_link_hash_warning)
14509 h = (struct elf_link_hash_entry *) h->root.u.i.link;
81fbe831
AM		 14510
14511 /* PR15323, ref flags aren't set for references in the
14512 same object. */
14513 h->root.non_ir_ref = 1;
34e77a92 14514 }
973a3492 14515 }
9a5aca8c 14516
b7693d02
DJ		 14517 eh = (struct elf32_arm_link_hash_entry *) h;
14518
f6e32f6d
RS		 14519 call_reloc_p = FALSE;
14520 may_become_dynamic_p = FALSE;
14521 may_need_local_target_p = FALSE;
14522
0855e32b
NS		 14523 /* Could be done earlier, if h were already available. */
14524 r_type = elf32_arm_tls_transition (info, r_type, h);
eb043451 14525 switch (r_type)
99059e56 14526 {
5e681ec4 14527 case R_ARM_GOT32:
eb043451 14528 case R_ARM_GOT_PREL:
ba93b8ac
DJ		 14529 case R_ARM_TLS_GD32:
14530 case R_ARM_TLS_IE32:
0855e32b
NS		 14531 case R_ARM_TLS_GOTDESC:
14532 case R_ARM_TLS_DESCSEQ:
14533 case R_ARM_THM_TLS_DESCSEQ:
14534 case R_ARM_TLS_CALL:
14535 case R_ARM_THM_TLS_CALL:
5e681ec4 14536 /* This symbol requires a global offset table entry. */
ba93b8ac
DJ		 14537 {
14538 int tls_type, old_tls_type;
5e681ec4 14539
ba93b8ac
DJ		 14540 switch (r_type)
14541 {
14542 case R_ARM_TLS_GD32: tls_type = GOT_TLS_GD; break;
b38cadfb 14543
ba93b8ac 14544 case R_ARM_TLS_IE32: tls_type = GOT_TLS_IE; break;
b38cadfb 14545
0855e32b
NS		 14546 case R_ARM_TLS_GOTDESC:
14547 case R_ARM_TLS_CALL: case R_ARM_THM_TLS_CALL:
14548 case R_ARM_TLS_DESCSEQ: case R_ARM_THM_TLS_DESCSEQ:
14549 tls_type = GOT_TLS_GDESC; break;
b38cadfb 14550
ba93b8ac
DJ		 14551 default: tls_type = GOT_NORMAL; break;
14552 }
252b5132 14553
0e1862bb 14554 if (!bfd_link_executable (info) && (tls_type & GOT_TLS_IE))
eea6dad2
KM		 14555 info->flags |= DF_STATIC_TLS;
14556
ba93b8ac
DJ		 14557 if (h != NULL)
14558 {
14559 h->got.refcount++;
14560 old_tls_type = elf32_arm_hash_entry (h)->tls_type;
14561 }
14562 else
14563 {
ba93b8ac 14564 /* This is a global offset table entry for a local symbol. */
34e77a92
RS		 14565 if (!elf32_arm_allocate_local_sym_info (abfd))
14566 return FALSE;
14567 elf_local_got_refcounts (abfd)[r_symndx] += 1;
ba93b8ac
DJ		 14568 old_tls_type = elf32_arm_local_got_tls_type (abfd) [r_symndx];
14569 }
14570
0855e32b 14571 /* If a variable is accessed with both tls methods, two
99059e56 14572 slots may be created. */
0855e32b
NS		 14573 if (GOT_TLS_GD_ANY_P (old_tls_type)
14574 && GOT_TLS_GD_ANY_P (tls_type))
14575 tls_type |= old_tls_type;
14576
14577 /* We will already have issued an error message if there
14578 is a TLS/non-TLS mismatch, based on the symbol
14579 type. So just combine any TLS types needed. */
ba93b8ac
DJ		 14580 if (old_tls_type != GOT_UNKNOWN && old_tls_type != GOT_NORMAL
14581 && tls_type != GOT_NORMAL)
14582 tls_type |= old_tls_type;
14583
0855e32b 14584 /* If the symbol is accessed in both IE and GDESC
99059e56
RM		 14585 method, we're able to relax. Turn off the GDESC flag,
14586 without messing up with any other kind of tls types
6a631e86 14587 that may be involved. */
0855e32b
NS		 14588 if ((tls_type & GOT_TLS_IE) && (tls_type & GOT_TLS_GDESC))
14589 tls_type &= ~GOT_TLS_GDESC;
14590
ba93b8ac
DJ		 14591 if (old_tls_type != tls_type)
14592 {
14593 if (h != NULL)
14594 elf32_arm_hash_entry (h)->tls_type = tls_type;
14595 else
14596 elf32_arm_local_got_tls_type (abfd) [r_symndx] = tls_type;
14597 }
14598 }
8029a119 14599 /* Fall through. */
ba93b8ac
DJ		 14600
14601 case R_ARM_TLS_LDM32:
14602 if (r_type == R_ARM_TLS_LDM32)
14603 htab->tls_ldm_got.refcount++;
8029a119 14604 /* Fall through. */
252b5132 14605
c19d1205 14606 case R_ARM_GOTOFF32:
5e681ec4 14607 case R_ARM_GOTPC:
cbc704f3
RS		 14608 if (htab->root.sgot == NULL
14609 && !create_got_section (htab->root.dynobj, info))
14610 return FALSE;
252b5132
RH		 14611 break;
14612
252b5132 14613 case R_ARM_PC24:
7359ea65 14614 case R_ARM_PLT32:
5b5bb741
PB		 14615 case R_ARM_CALL:
14616 case R_ARM_JUMP24:
eb043451 14617 case R_ARM_PREL31:
c19d1205 14618 case R_ARM_THM_CALL:
bd97cb95
DJ		 14619 case R_ARM_THM_JUMP24:
14620 case R_ARM_THM_JUMP19:
f6e32f6d
RS		 14621 call_reloc_p = TRUE;
14622 may_need_local_target_p = TRUE;
14623 break;
14624
14625 case R_ARM_ABS12:
14626 /* VxWorks uses dynamic R_ARM_ABS12 relocations for
14627 ldr __GOTT_INDEX__ offsets. */
14628 if (!htab->vxworks_p)
14629 {
14630 may_need_local_target_p = TRUE;
14631 break;
14632 }
aebf9be7
NC		 14633 else goto jump_over;
14634
f6e32f6d 14635 /* Fall through. */
39623e12 14636
96c23d59
JM		 14637 case R_ARM_MOVW_ABS_NC:
14638 case R_ARM_MOVT_ABS:
14639 case R_ARM_THM_MOVW_ABS_NC:
14640 case R_ARM_THM_MOVT_ABS:
0e1862bb 14641 if (bfd_link_pic (info))
96c23d59
JM		 14642 {
14643 (*_bfd_error_handler)
14644 (_("%B: relocation %s against `%s' can not be used when making a shared object; recompile with -fPIC"),
14645 abfd, elf32_arm_howto_table_1[r_type].name,
14646 (h) ? h->root.root.string : "a local symbol");
14647 bfd_set_error (bfd_error_bad_value);
14648 return FALSE;
14649 }
14650
14651 /* Fall through. */
39623e12
PB		 14652 case R_ARM_ABS32:
14653 case R_ARM_ABS32_NOI:
aebf9be7 14654 jump_over:
0e1862bb 14655 if (h != NULL && bfd_link_executable (info))
97323ad1
WN		 14656 {
14657 h->pointer_equality_needed = 1;
14658 }
14659 /* Fall through. */
39623e12
PB		 14660 case R_ARM_REL32:
14661 case R_ARM_REL32_NOI:
b6895b4f
PB		 14662 case R_ARM_MOVW_PREL_NC:
14663 case R_ARM_MOVT_PREL:
b6895b4f
PB		 14664 case R_ARM_THM_MOVW_PREL_NC:
14665 case R_ARM_THM_MOVT_PREL:
39623e12 14666
b7693d02 14667 /* Should the interworking branches be listed here? */
0e1862bb 14668 if ((bfd_link_pic (info) || htab->root.is_relocatable_executable)
34e77a92
RS		 14669 && (sec->flags & SEC_ALLOC) != 0)
14670 {
14671 if (h == NULL
469a3493 14672 && elf32_arm_howto_from_type (r_type)->pc_relative)
34e77a92
RS		 14673 {
14674 /* In shared libraries and relocatable executables,
14675 we treat local relative references as calls;
14676 see the related SYMBOL_CALLS_LOCAL code in
14677 allocate_dynrelocs. */
14678 call_reloc_p = TRUE;
14679 may_need_local_target_p = TRUE;
14680 }
14681 else
14682 /* We are creating a shared library or relocatable
14683 executable, and this is a reloc against a global symbol,
14684 or a non-PC-relative reloc against a local symbol.
14685 We may need to copy the reloc into the output. */
14686 may_become_dynamic_p = TRUE;
14687 }
f6e32f6d
RS		 14688 else
14689 may_need_local_target_p = TRUE;
252b5132
RH		 14690 break;
14691
99059e56
RM		 14692 /* This relocation describes the C++ object vtable hierarchy.
14693 Reconstruct it for later use during GC. */
14694 case R_ARM_GNU_VTINHERIT:
14695 if (!bfd_elf_gc_record_vtinherit (abfd, sec, h, rel->r_offset))
14696 return FALSE;
14697 break;
14698
14699 /* This relocation describes which C++ vtable entries are actually
14700 used. Record for later use during GC. */
14701 case R_ARM_GNU_VTENTRY:
14702 BFD_ASSERT (h != NULL);
14703 if (h != NULL
14704 && !bfd_elf_gc_record_vtentry (abfd, sec, h, rel->r_offset))
14705 return FALSE;
14706 break;
14707 }
f6e32f6d
RS		 14708
14709 if (h != NULL)
14710 {
14711 if (call_reloc_p)
14712 /* We may need a .plt entry if the function this reloc
14713 refers to is in a different object, regardless of the
14714 symbol's type. We can't tell for sure yet, because
14715 something later might force the symbol local. */
14716 h->needs_plt = 1;
14717 else if (may_need_local_target_p)
14718 /* If this reloc is in a read-only section, we might
14719 need a copy reloc. We can't check reliably at this
14720 stage whether the section is read-only, as input
14721 sections have not yet been mapped to output sections.
14722 Tentatively set the flag for now, and correct in
14723 adjust_dynamic_symbol. */
14724 h->non_got_ref = 1;
14725 }
14726
34e77a92
RS		 14727 if (may_need_local_target_p
14728 && (h != NULL || ELF32_ST_TYPE (isym->st_info) == STT_GNU_IFUNC))
f6e32f6d 14729 {
34e77a92
RS		 14730 union gotplt_union *root_plt;
14731 struct arm_plt_info *arm_plt;
14732 struct arm_local_iplt_info *local_iplt;
14733
14734 if (h != NULL)
14735 {
14736 root_plt = &h->plt;
14737 arm_plt = &eh->plt;
14738 }
14739 else
14740 {
14741 local_iplt = elf32_arm_create_local_iplt (abfd, r_symndx);
14742 if (local_iplt == NULL)
14743 return FALSE;
14744 root_plt = &local_iplt->root;
14745 arm_plt = &local_iplt->arm;
14746 }
14747
f6e32f6d
RS		 14748 /* If the symbol is a function that doesn't bind locally,
14749 this relocation will need a PLT entry. */
a8c887dd
NC		 14750 if (root_plt->refcount != -1)
14751 root_plt->refcount += 1;
34e77a92
RS		 14752
14753 if (!call_reloc_p)
14754 arm_plt->noncall_refcount++;
f6e32f6d
RS		 14755
14756 /* It's too early to use htab->use_blx here, so we have to
14757 record possible blx references separately from
14758 relocs that definitely need a thumb stub. */
14759
14760 if (r_type == R_ARM_THM_CALL)
34e77a92 14761 arm_plt->maybe_thumb_refcount += 1;
f6e32f6d
RS		 14762
14763 if (r_type == R_ARM_THM_JUMP24
14764 || r_type == R_ARM_THM_JUMP19)
34e77a92 14765 arm_plt->thumb_refcount += 1;
f6e32f6d
RS		 14766 }
14767
14768 if (may_become_dynamic_p)
14769 {
14770 struct elf_dyn_relocs *p, **head;
14771
14772 /* Create a reloc section in dynobj. */
14773 if (sreloc == NULL)
14774 {
14775 sreloc = _bfd_elf_make_dynamic_reloc_section
14776 (sec, dynobj, 2, abfd, ! htab->use_rel);
14777
14778 if (sreloc == NULL)
14779 return FALSE;
14780
14781 /* BPABI objects never have dynamic relocations mapped. */
14782 if (htab->symbian_p)
14783 {
14784 flagword flags;
14785
14786 flags = bfd_get_section_flags (dynobj, sreloc);
14787 flags &= ~(SEC_LOAD | SEC_ALLOC);
14788 bfd_set_section_flags (dynobj, sreloc, flags);
14789 }
14790 }
14791
14792 /* If this is a global symbol, count the number of
14793 relocations we need for this symbol. */
14794 if (h != NULL)
14795 head = &((struct elf32_arm_link_hash_entry *) h)->dyn_relocs;
14796 else
14797 {
34e77a92
RS		 14798 head = elf32_arm_get_local_dynreloc_list (abfd, r_symndx, isym);
14799 if (head == NULL)
f6e32f6d 14800 return FALSE;
f6e32f6d
RS		 14801 }
14802
14803 p = *head;
14804 if (p == NULL || p->sec != sec)
14805 {
14806 bfd_size_type amt = sizeof *p;
14807
14808 p = (struct elf_dyn_relocs *) bfd_alloc (htab->root.dynobj, amt);
14809 if (p == NULL)
14810 return FALSE;
14811 p->next = *head;
14812 *head = p;
14813 p->sec = sec;
14814 p->count = 0;
14815 p->pc_count = 0;
14816 }
14817
469a3493 14818 if (elf32_arm_howto_from_type (r_type)->pc_relative)
f6e32f6d
RS		 14819 p->pc_count += 1;
14820 p->count += 1;
14821 }
252b5132 14822 }
f21f3fe0 14823
b34976b6 14824 return TRUE;
252b5132
RH		 14825}
14826
6a5bb875 14827/* Unwinding tables are not referenced directly. This pass marks them as
4ba2ef8f
TP		 14828 required if the corresponding code section is marked. Similarly, ARMv8-M
14829 secure entry functions can only be referenced by SG veneers which are
14830 created after the GC process. They need to be marked in case they reside in
14831 their own section (as would be the case if code was compiled with
14832 -ffunction-sections). */
6a5bb875
PB		 14833
14834static bfd_boolean
906e58ca
NC		 14835elf32_arm_gc_mark_extra_sections (struct bfd_link_info *info,
14836 elf_gc_mark_hook_fn gc_mark_hook)
6a5bb875
PB		 14837{
14838 bfd *sub;
14839 Elf_Internal_Shdr **elf_shdrp;
4ba2ef8f
TP		 14840 asection *cmse_sec;
14841 obj_attribute *out_attr;
14842 Elf_Internal_Shdr *symtab_hdr;
14843 unsigned i, sym_count, ext_start;
14844 const struct elf_backend_data *bed;
14845 struct elf_link_hash_entry **sym_hashes;
14846 struct elf32_arm_link_hash_entry *cmse_hash;
14847 bfd_boolean again, is_v8m, first_bfd_browse = TRUE;
6a5bb875 14848
7f6ab9f8
AM		 14849 _bfd_elf_gc_mark_extra_sections (info, gc_mark_hook);
14850
4ba2ef8f
TP		 14851 out_attr = elf_known_obj_attributes_proc (info->output_bfd);
14852 is_v8m = out_attr[Tag_CPU_arch].i >= TAG_CPU_ARCH_V8M_BASE
14853 && out_attr[Tag_CPU_arch_profile].i == 'M';
14854
6a5bb875
PB		 14855 /* Marking EH data may cause additional code sections to be marked,
14856 requiring multiple passes. */
14857 again = TRUE;
14858 while (again)
14859 {
14860 again = FALSE;
c72f2fb2 14861 for (sub = info->input_bfds; sub != NULL; sub = sub->link.next)
6a5bb875
PB		 14862 {
14863 asection *o;
14864
0ffa91dd 14865 if (! is_arm_elf (sub))
6a5bb875
PB		 14866 continue;
14867
14868 elf_shdrp = elf_elfsections (sub);
14869 for (o = sub->sections; o != NULL; o = o->next)
14870 {
14871 Elf_Internal_Shdr *hdr;
0ffa91dd 14872
6a5bb875 14873 hdr = &elf_section_data (o)->this_hdr;
4fbb74a6
AM		 14874 if (hdr->sh_type == SHT_ARM_EXIDX
14875 && hdr->sh_link
14876 && hdr->sh_link < elf_numsections (sub)
6a5bb875
PB		 14877 && !o->gc_mark
14878 && elf_shdrp[hdr->sh_link]->bfd_section->gc_mark)
14879 {
14880 again = TRUE;
14881 if (!_bfd_elf_gc_mark (info, o, gc_mark_hook))
14882 return FALSE;
14883 }
14884 }
4ba2ef8f
TP		 14885
14886 /* Mark section holding ARMv8-M secure entry functions. We mark all
14887 of them so no need for a second browsing. */
14888 if (is_v8m && first_bfd_browse)
14889 {
14890 sym_hashes = elf_sym_hashes (sub);
14891 bed = get_elf_backend_data (sub);
14892 symtab_hdr = &elf_tdata (sub)->symtab_hdr;
14893 sym_count = symtab_hdr->sh_size / bed->s->sizeof_sym;
14894 ext_start = symtab_hdr->sh_info;
14895
14896 /* Scan symbols. */
14897 for (i = ext_start; i < sym_count; i++)
14898 {
14899 cmse_hash = elf32_arm_hash_entry (sym_hashes[i - ext_start]);
14900
14901 /* Assume it is a special symbol. If not, cmse_scan will
14902 warn about it and user can do something about it. */
14903 if (ARM_GET_SYM_CMSE_SPCL (cmse_hash->root.target_internal))
14904 {
14905 cmse_sec = cmse_hash->root.root.u.def.section;
14906 if (!_bfd_elf_gc_mark (info, cmse_sec, gc_mark_hook))
14907 return FALSE;
14908 }
14909 }
14910 }
6a5bb875 14911 }
4ba2ef8f 14912 first_bfd_browse = FALSE;
6a5bb875
PB		 14913 }
14914
14915 return TRUE;
14916}
14917
3c9458e9
NC		 14918/* Treat mapping symbols as special target symbols. */
14919
14920static bfd_boolean
14921elf32_arm_is_target_special_symbol (bfd * abfd ATTRIBUTE_UNUSED, asymbol * sym)
14922{
b0796911
PB		 14923 return bfd_is_arm_special_symbol_name (sym->name,
14924 BFD_ARM_SPECIAL_SYM_TYPE_ANY);
3c9458e9
NC		 14925}
14926
0367ecfb
NC		 14927/* This is a copy of elf_find_function() from elf.c except that
14928 ARM mapping symbols are ignored when looking for function names
14929 and STT_ARM_TFUNC is considered to a function type. */
252b5132 14930
0367ecfb
NC		 14931static bfd_boolean
14932arm_elf_find_function (bfd * abfd ATTRIBUTE_UNUSED,
0367ecfb 14933 asymbol ** symbols,
fb167eb2 14934 asection * section,
0367ecfb
NC		 14935 bfd_vma offset,
14936 const char ** filename_ptr,
14937 const char ** functionname_ptr)
14938{
14939 const char * filename = NULL;
14940 asymbol * func = NULL;
14941 bfd_vma low_func = 0;
14942 asymbol ** p;
252b5132
RH		 14943
14944 for (p = symbols; *p != NULL; p++)
14945 {
14946 elf_symbol_type *q;
14947
14948 q = (elf_symbol_type *) *p;
14949
252b5132
RH		 14950 switch (ELF_ST_TYPE (q->internal_elf_sym.st_info))
14951 {
14952 default:
14953 break;
14954 case STT_FILE:
14955 filename = bfd_asymbol_name (&q->symbol);
14956 break;
252b5132
RH		 14957 case STT_FUNC:
14958 case STT_ARM_TFUNC:
9d2da7ca 14959 case STT_NOTYPE:
b0796911 14960 /* Skip mapping symbols. */
0367ecfb 14961 if ((q->symbol.flags & BSF_LOCAL)
b0796911
PB		 14962 && bfd_is_arm_special_symbol_name (q->symbol.name,
14963 BFD_ARM_SPECIAL_SYM_TYPE_ANY))
0367ecfb
NC		 14964 continue;
14965 /* Fall through. */
6b40fcba 14966 if (bfd_get_section (&q->symbol) == section
252b5132
RH		 14967 && q->symbol.value >= low_func
14968 && q->symbol.value <= offset)
14969 {
14970 func = (asymbol *) q;
14971 low_func = q->symbol.value;
14972 }
14973 break;
14974 }
14975 }
14976
14977 if (func == NULL)
b34976b6 14978 return FALSE;
252b5132 14979
0367ecfb
NC		 14980 if (filename_ptr)
14981 *filename_ptr = filename;
14982 if (functionname_ptr)
14983 *functionname_ptr = bfd_asymbol_name (func);
14984
14985 return TRUE;
906e58ca 14986}
0367ecfb
NC		 14987
14988
14989/* Find the nearest line to a particular section and offset, for error
14990 reporting. This code is a duplicate of the code in elf.c, except
14991 that it uses arm_elf_find_function. */
14992
14993static bfd_boolean
14994elf32_arm_find_nearest_line (bfd * abfd,
0367ecfb 14995 asymbol ** symbols,
fb167eb2 14996 asection * section,
0367ecfb
NC		 14997 bfd_vma offset,
14998 const char ** filename_ptr,
14999 const char ** functionname_ptr,
fb167eb2
AM		 15000 unsigned int * line_ptr,
15001 unsigned int * discriminator_ptr)
0367ecfb
NC		 15002{
15003 bfd_boolean found = FALSE;
15004
fb167eb2 15005 if (_bfd_dwarf2_find_nearest_line (abfd, symbols, NULL, section, offset,
0367ecfb 15006 filename_ptr, functionname_ptr,
fb167eb2
AM		 15007 line_ptr, discriminator_ptr,
15008 dwarf_debug_sections, 0,
0367ecfb
NC		 15009 & elf_tdata (abfd)->dwarf2_find_line_info))
15010 {
15011 if (!*functionname_ptr)
fb167eb2 15012 arm_elf_find_function (abfd, symbols, section, offset,
0367ecfb
NC		 15013 *filename_ptr ? NULL : filename_ptr,
15014 functionname_ptr);
f21f3fe0 15015
0367ecfb
NC		 15016 return TRUE;
15017 }
15018
fb167eb2
AM		 15019 /* Skip _bfd_dwarf1_find_nearest_line since no known ARM toolchain
15020 uses DWARF1. */
15021
0367ecfb
NC		 15022 if (! _bfd_stab_section_find_nearest_line (abfd, symbols, section, offset,
15023 & found, filename_ptr,
15024 functionname_ptr, line_ptr,
15025 & elf_tdata (abfd)->line_info))
15026 return FALSE;
15027
15028 if (found && (*functionname_ptr || *line_ptr))
15029 return TRUE;
15030
15031 if (symbols == NULL)
15032 return FALSE;
15033
fb167eb2 15034 if (! arm_elf_find_function (abfd, symbols, section, offset,
0367ecfb
NC		 15035 filename_ptr, functionname_ptr))
15036 return FALSE;
15037
15038 *line_ptr = 0;
b34976b6 15039 return TRUE;
252b5132
RH		 15040}
15041
4ab527b0
FF		 15042static bfd_boolean
15043elf32_arm_find_inliner_info (bfd * abfd,
15044 const char ** filename_ptr,
15045 const char ** functionname_ptr,
15046 unsigned int * line_ptr)
15047{
15048 bfd_boolean found;
15049 found = _bfd_dwarf2_find_inliner_info (abfd, filename_ptr,
15050 functionname_ptr, line_ptr,
15051 & elf_tdata (abfd)->dwarf2_find_line_info);
15052 return found;
15053}
15054
252b5132
RH		 15055/* Adjust a symbol defined by a dynamic object and referenced by a
15056 regular object. The current definition is in some section of the
15057 dynamic object, but we're not including those sections. We have to
15058 change the definition to something the rest of the link can
15059 understand. */
15060
b34976b6 15061static bfd_boolean
57e8b36a
NC		 15062elf32_arm_adjust_dynamic_symbol (struct bfd_link_info * info,
15063 struct elf_link_hash_entry * h)
252b5132
RH		 15064{
15065 bfd * dynobj;
15066 asection * s;
b7693d02 15067 struct elf32_arm_link_hash_entry * eh;
67687978 15068 struct elf32_arm_link_hash_table *globals;
252b5132 15069
67687978 15070 globals = elf32_arm_hash_table (info);
4dfe6ac6
NC		 15071 if (globals == NULL)
15072 return FALSE;
15073
252b5132
RH		 15074 dynobj = elf_hash_table (info)->dynobj;
15075
15076 /* Make sure we know what is going on here. */
15077 BFD_ASSERT (dynobj != NULL
f5385ebf 15078 && (h->needs_plt
34e77a92 15079 || h->type == STT_GNU_IFUNC
f6e332e6 15080 || h->u.weakdef != NULL
f5385ebf
AM		 15081 || (h->def_dynamic
15082 && h->ref_regular
15083 && !h->def_regular)));
252b5132 15084
b7693d02
DJ		 15085 eh = (struct elf32_arm_link_hash_entry *) h;
15086
252b5132
RH		 15087 /* If this is a function, put it in the procedure linkage table. We
15088 will fill in the contents of the procedure linkage table later,
15089 when we know the address of the .got section. */
34e77a92 15090 if (h->type == STT_FUNC || h->type == STT_GNU_IFUNC || h->needs_plt)
252b5132 15091 {
34e77a92
RS		 15092 /* Calls to STT_GNU_IFUNC symbols always use a PLT, even if the
15093 symbol binds locally. */
5e681ec4 15094 if (h->plt.refcount <= 0
34e77a92
RS		 15095 || (h->type != STT_GNU_IFUNC
15096 && (SYMBOL_CALLS_LOCAL (info, h)
15097 || (ELF_ST_VISIBILITY (h->other) != STV_DEFAULT
15098 && h->root.type == bfd_link_hash_undefweak))))
252b5132
RH		 15099 {
15100 /* This case can occur if we saw a PLT32 reloc in an input
5e681ec4
PB		 15101 file, but the symbol was never referred to by a dynamic
15102 object, or if all references were garbage collected. In
15103 such a case, we don't actually need to build a procedure
15104 linkage table, and we can just do a PC24 reloc instead. */
15105 h->plt.offset = (bfd_vma) -1;
34e77a92
RS		 15106 eh->plt.thumb_refcount = 0;
15107 eh->plt.maybe_thumb_refcount = 0;
15108 eh->plt.noncall_refcount = 0;
f5385ebf 15109 h->needs_plt = 0;
252b5132
RH		 15110 }
15111
b34976b6 15112 return TRUE;
252b5132 15113 }
5e681ec4 15114 else
b7693d02
DJ		 15115 {
15116 /* It's possible that we incorrectly decided a .plt reloc was
15117 needed for an R_ARM_PC24 or similar reloc to a non-function sym
15118 in check_relocs. We can't decide accurately between function
15119 and non-function syms in check-relocs; Objects loaded later in
15120 the link may change h->type. So fix it now. */
15121 h->plt.offset = (bfd_vma) -1;
34e77a92
RS		 15122 eh->plt.thumb_refcount = 0;
15123 eh->plt.maybe_thumb_refcount = 0;
15124 eh->plt.noncall_refcount = 0;
b7693d02 15125 }
252b5132
RH		 15126
15127 /* If this is a weak symbol, and there is a real definition, the
15128 processor independent code will have arranged for us to see the
15129 real definition first, and we can just use the same value. */
f6e332e6 15130 if (h->u.weakdef != NULL)
252b5132 15131 {
f6e332e6
AM		 15132 BFD_ASSERT (h->u.weakdef->root.type == bfd_link_hash_defined
15133 || h->u.weakdef->root.type == bfd_link_hash_defweak);
15134 h->root.u.def.section = h->u.weakdef->root.u.def.section;
15135 h->root.u.def.value = h->u.weakdef->root.u.def.value;
b34976b6 15136 return TRUE;
252b5132
RH		 15137 }
15138
ba93b8ac
DJ		 15139 /* If there are no non-GOT references, we do not need a copy
15140 relocation. */
15141 if (!h->non_got_ref)
15142 return TRUE;
15143
252b5132
RH		 15144 /* This is a reference to a symbol defined by a dynamic object which
15145 is not a function. */
15146
15147 /* If we are creating a shared library, we must presume that the
15148 only references to the symbol are via the global offset table.
15149 For such cases we need not do anything here; the relocations will
67687978
PB		 15150 be handled correctly by relocate_section. Relocatable executables
15151 can reference data in shared objects directly, so we don't need to
15152 do anything here. */
0e1862bb 15153 if (bfd_link_pic (info) || globals->root.is_relocatable_executable)
b34976b6 15154 return TRUE;
252b5132
RH		 15155
15156 /* We must allocate the symbol in our .dynbss section, which will
15157 become part of the .bss section of the executable. There will be
15158 an entry for this symbol in the .dynsym section. The dynamic
15159 object will contain position independent code, so all references
15160 from the dynamic object to this symbol will go through the global
15161 offset table. The dynamic linker will use the .dynsym entry to
15162 determine the address it must put in the global offset table, so
15163 both the dynamic object and the regular object will refer to the
15164 same memory location for the variable. */
3d4d4302 15165 s = bfd_get_linker_section (dynobj, ".dynbss");
252b5132
RH		 15166 BFD_ASSERT (s != NULL);
15167
5522f910
NC		 15168 /* If allowed, we must generate a R_ARM_COPY reloc to tell the dynamic
15169 linker to copy the initial value out of the dynamic object and into
15170 the runtime process image. We need to remember the offset into the
00a97672 15171 .rel(a).bss section we are going to use. */
5522f910
NC		 15172 if (info->nocopyreloc == 0
15173 && (h->root.u.def.section->flags & SEC_ALLOC) != 0
5522f910 15174 && h->size != 0)
252b5132
RH		 15175 {
15176 asection *srel;
15177
3d4d4302 15178 srel = bfd_get_linker_section (dynobj, RELOC_SECTION (globals, ".bss"));
47beaa6a 15179 elf32_arm_allocate_dynrelocs (info, srel, 1);
f5385ebf 15180 h->needs_copy = 1;
252b5132
RH		 15181 }
15182
6cabe1ea 15183 return _bfd_elf_adjust_dynamic_copy (info, h, s);
252b5132
RH		 15184}
15185
5e681ec4
PB		 15186/* Allocate space in .plt, .got and associated reloc sections for
15187 dynamic relocs. */
15188
15189static bfd_boolean
47beaa6a 15190allocate_dynrelocs_for_symbol (struct elf_link_hash_entry *h, void * inf)
5e681ec4
PB		 15191{
15192 struct bfd_link_info *info;
15193 struct elf32_arm_link_hash_table *htab;
15194 struct elf32_arm_link_hash_entry *eh;
0bdcacaf 15195 struct elf_dyn_relocs *p;
5e681ec4
PB		 15196
15197 if (h->root.type == bfd_link_hash_indirect)
15198 return TRUE;
15199
e6a6bb22
AM		 15200 eh = (struct elf32_arm_link_hash_entry *) h;
15201
5e681ec4
PB		 15202 info = (struct bfd_link_info *) inf;
15203 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 15204 if (htab == NULL)
15205 return FALSE;
5e681ec4 15206
34e77a92 15207 if ((htab->root.dynamic_sections_created || h->type == STT_GNU_IFUNC)
5e681ec4
PB		 15208 && h->plt.refcount > 0)
15209 {
15210 /* Make sure this symbol is output as a dynamic symbol.
15211 Undefined weak syms won't yet be marked as dynamic. */
15212 if (h->dynindx == -1
f5385ebf 15213 && !h->forced_local)
5e681ec4 15214 {
c152c796 15215 if (! bfd_elf_link_record_dynamic_symbol (info, h))
5e681ec4
PB		 15216 return FALSE;
15217 }
15218
34e77a92
RS		 15219 /* If the call in the PLT entry binds locally, the associated
15220 GOT entry should use an R_ARM_IRELATIVE relocation instead of
15221 the usual R_ARM_JUMP_SLOT. Put it in the .iplt section rather
15222 than the .plt section. */
15223 if (h->type == STT_GNU_IFUNC && SYMBOL_CALLS_LOCAL (info, h))
15224 {
15225 eh->is_iplt = 1;
15226 if (eh->plt.noncall_refcount == 0
15227 && SYMBOL_REFERENCES_LOCAL (info, h))
15228 /* All non-call references can be resolved directly.
15229 This means that they can (and in some cases, must)
15230 resolve directly to the run-time target, rather than
15231 to the PLT. That in turns means that any .got entry
15232 would be equal to the .igot.plt entry, so there's
15233 no point having both. */
15234 h->got.refcount = 0;
15235 }
15236
0e1862bb 15237 if (bfd_link_pic (info)
34e77a92 15238 || eh->is_iplt
7359ea65 15239 || WILL_CALL_FINISH_DYNAMIC_SYMBOL (1, 0, h))
5e681ec4 15240 {
34e77a92 15241 elf32_arm_allocate_plt_entry (info, eh->is_iplt, &h->plt, &eh->plt);
b7693d02 15242
5e681ec4
PB		 15243 /* If this symbol is not defined in a regular file, and we are
15244 not generating a shared library, then set the symbol to this
15245 location in the .plt. This is required to make function
15246 pointers compare as equal between the normal executable and
15247 the shared library. */
0e1862bb 15248 if (! bfd_link_pic (info)
f5385ebf 15249 && !h->def_regular)
5e681ec4 15250 {
34e77a92 15251 h->root.u.def.section = htab->root.splt;
5e681ec4 15252 h->root.u.def.value = h->plt.offset;
5e681ec4 15253
67d74e43
DJ		 15254 /* Make sure the function is not marked as Thumb, in case
15255 it is the target of an ABS32 relocation, which will
15256 point to the PLT entry. */
39d911fc 15257 ARM_SET_SYM_BRANCH_TYPE (h->target_internal, ST_BRANCH_TO_ARM);
67d74e43 15258 }
022f8312 15259
00a97672
RS		 15260 /* VxWorks executables have a second set of relocations for
15261 each PLT entry. They go in a separate relocation section,
15262 which is processed by the kernel loader. */
0e1862bb 15263 if (htab->vxworks_p && !bfd_link_pic (info))
00a97672
RS		 15264 {
15265 /* There is a relocation for the initial PLT entry:
15266 an R_ARM_32 relocation for _GLOBAL_OFFSET_TABLE_. */
15267 if (h->plt.offset == htab->plt_header_size)
47beaa6a 15268 elf32_arm_allocate_dynrelocs (info, htab->srelplt2, 1);
00a97672
RS		 15269
15270 /* There are two extra relocations for each subsequent
15271 PLT entry: an R_ARM_32 relocation for the GOT entry,
15272 and an R_ARM_32 relocation for the PLT entry. */
47beaa6a 15273 elf32_arm_allocate_dynrelocs (info, htab->srelplt2, 2);
00a97672 15274 }
5e681ec4
PB		 15275 }
15276 else
15277 {
15278 h->plt.offset = (bfd_vma) -1;
f5385ebf 15279 h->needs_plt = 0;
5e681ec4
PB		 15280 }
15281 }
15282 else
15283 {
15284 h->plt.offset = (bfd_vma) -1;
f5385ebf 15285 h->needs_plt = 0;
5e681ec4
PB		 15286 }
15287
0855e32b
NS		 15288 eh = (struct elf32_arm_link_hash_entry *) h;
15289 eh->tlsdesc_got = (bfd_vma) -1;
15290
5e681ec4
PB		 15291 if (h->got.refcount > 0)
15292 {
15293 asection *s;
15294 bfd_boolean dyn;
ba93b8ac
DJ		 15295 int tls_type = elf32_arm_hash_entry (h)->tls_type;
15296 int indx;
5e681ec4
PB		 15297
15298 /* Make sure this symbol is output as a dynamic symbol.
15299 Undefined weak syms won't yet be marked as dynamic. */
15300 if (h->dynindx == -1
f5385ebf 15301 && !h->forced_local)
5e681ec4 15302 {
c152c796 15303 if (! bfd_elf_link_record_dynamic_symbol (info, h))
5e681ec4
PB		 15304 return FALSE;
15305 }
15306
e5a52504
MM		 15307 if (!htab->symbian_p)
15308 {
362d30a1 15309 s = htab->root.sgot;
e5a52504 15310 h->got.offset = s->size;
ba93b8ac
DJ		 15311
15312 if (tls_type == GOT_UNKNOWN)
15313 abort ();
15314
15315 if (tls_type == GOT_NORMAL)
15316 /* Non-TLS symbols need one GOT slot. */
15317 s->size += 4;
15318 else
15319 {
99059e56
RM		 15320 if (tls_type & GOT_TLS_GDESC)
15321 {
0855e32b 15322 /* R_ARM_TLS_DESC needs 2 GOT slots. */
99059e56 15323 eh->tlsdesc_got
0855e32b
NS		 15324 = (htab->root.sgotplt->size
15325 - elf32_arm_compute_jump_table_size (htab));
99059e56
RM		 15326 htab->root.sgotplt->size += 8;
15327 h->got.offset = (bfd_vma) -2;
34e77a92 15328 /* plt.got_offset needs to know there's a TLS_DESC
0855e32b 15329 reloc in the middle of .got.plt. */
99059e56
RM		 15330 htab->num_tls_desc++;
15331 }
0855e32b 15332
ba93b8ac 15333 if (tls_type & GOT_TLS_GD)
0855e32b
NS		 15334 {
15335 /* R_ARM_TLS_GD32 needs 2 consecutive GOT slots. If
15336 the symbol is both GD and GDESC, got.offset may
15337 have been overwritten. */
15338 h->got.offset = s->size;
15339 s->size += 8;
15340 }
15341
ba93b8ac
DJ		 15342 if (tls_type & GOT_TLS_IE)
15343 /* R_ARM_TLS_IE32 needs one GOT slot. */
15344 s->size += 4;
15345 }
15346
e5a52504 15347 dyn = htab->root.dynamic_sections_created;
ba93b8ac
DJ		 15348
15349 indx = 0;
0e1862bb
L		 15350 if (WILL_CALL_FINISH_DYNAMIC_SYMBOL (dyn,
15351 bfd_link_pic (info),
15352 h)
15353 && (!bfd_link_pic (info)
ba93b8ac
DJ		 15354 || !SYMBOL_REFERENCES_LOCAL (info, h)))
15355 indx = h->dynindx;
15356
15357 if (tls_type != GOT_NORMAL
0e1862bb 15358 && (bfd_link_pic (info) || indx != 0)
ba93b8ac
DJ		 15359 && (ELF_ST_VISIBILITY (h->other) == STV_DEFAULT
15360 || h->root.type != bfd_link_hash_undefweak))
15361 {
15362 if (tls_type & GOT_TLS_IE)
47beaa6a 15363 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
ba93b8ac
DJ		 15364
15365 if (tls_type & GOT_TLS_GD)
47beaa6a 15366 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
ba93b8ac 15367
b38cadfb 15368 if (tls_type & GOT_TLS_GDESC)
0855e32b 15369 {
47beaa6a 15370 elf32_arm_allocate_dynrelocs (info, htab->root.srelplt, 1);
0855e32b
NS		 15371 /* GDESC needs a trampoline to jump to. */
15372 htab->tls_trampoline = -1;
15373 }
15374
15375 /* Only GD needs it. GDESC just emits one relocation per
15376 2 entries. */
b38cadfb 15377 if ((tls_type & GOT_TLS_GD) && indx != 0)
47beaa6a 15378 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
ba93b8ac 15379 }
6f820c85 15380 else if (indx != -1 && !SYMBOL_REFERENCES_LOCAL (info, h))
b436d854
RS		 15381 {
15382 if (htab->root.dynamic_sections_created)
15383 /* Reserve room for the GOT entry's R_ARM_GLOB_DAT relocation. */
15384 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
15385 }
34e77a92
RS		 15386 else if (h->type == STT_GNU_IFUNC
15387 && eh->plt.noncall_refcount == 0)
15388 /* No non-call references resolve the STT_GNU_IFUNC's PLT entry;
15389 they all resolve dynamically instead. Reserve room for the
15390 GOT entry's R_ARM_IRELATIVE relocation. */
15391 elf32_arm_allocate_irelocs (info, htab->root.srelgot, 1);
0e1862bb
L		 15392 else if (bfd_link_pic (info)
15393 && (ELF_ST_VISIBILITY (h->other) == STV_DEFAULT
15394 || h->root.type != bfd_link_hash_undefweak))
b436d854 15395 /* Reserve room for the GOT entry's R_ARM_RELATIVE relocation. */
47beaa6a 15396 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
e5a52504 15397 }
5e681ec4
PB		 15398 }
15399 else
15400 h->got.offset = (bfd_vma) -1;
15401
a4fd1a8e
PB		 15402 /* Allocate stubs for exported Thumb functions on v4t. */
15403 if (!htab->use_blx && h->dynindx != -1
0eaedd0e 15404 && h->def_regular
39d911fc 15405 && ARM_GET_SYM_BRANCH_TYPE (h->target_internal) == ST_BRANCH_TO_THUMB
a4fd1a8e
PB		 15406 && ELF_ST_VISIBILITY (h->other) == STV_DEFAULT)
15407 {
15408 struct elf_link_hash_entry * th;
15409 struct bfd_link_hash_entry * bh;
15410 struct elf_link_hash_entry * myh;
15411 char name[1024];
15412 asection *s;
15413 bh = NULL;
15414 /* Create a new symbol to regist the real location of the function. */
15415 s = h->root.u.def.section;
906e58ca 15416 sprintf (name, "__real_%s", h->root.root.string);
a4fd1a8e
PB		 15417 _bfd_generic_link_add_one_symbol (info, s->owner,
15418 name, BSF_GLOBAL, s,
15419 h->root.u.def.value,
15420 NULL, TRUE, FALSE, &bh);
15421
15422 myh = (struct elf_link_hash_entry *) bh;
35fc36a8 15423 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
a4fd1a8e 15424 myh->forced_local = 1;
39d911fc 15425 ARM_SET_SYM_BRANCH_TYPE (myh->target_internal, ST_BRANCH_TO_THUMB);
a4fd1a8e
PB		 15426 eh->export_glue = myh;
15427 th = record_arm_to_thumb_glue (info, h);
15428 /* Point the symbol at the stub. */
15429 h->type = ELF_ST_INFO (ELF_ST_BIND (h->type), STT_FUNC);
39d911fc 15430 ARM_SET_SYM_BRANCH_TYPE (h->target_internal, ST_BRANCH_TO_ARM);
a4fd1a8e
PB		 15431 h->root.u.def.section = th->root.u.def.section;
15432 h->root.u.def.value = th->root.u.def.value & ~1;
15433 }
15434
0bdcacaf 15435 if (eh->dyn_relocs == NULL)
5e681ec4
PB		 15436 return TRUE;
15437
15438 /* In the shared -Bsymbolic case, discard space allocated for
15439 dynamic pc-relative relocs against symbols which turn out to be
15440 defined in regular objects. For the normal shared case, discard
15441 space for pc-relative relocs that have become local due to symbol
15442 visibility changes. */
15443
0e1862bb 15444 if (bfd_link_pic (info) || htab->root.is_relocatable_executable)
5e681ec4 15445 {
469a3493
RM		 15446 /* Relocs that use pc_count are PC-relative forms, which will appear
15447 on something like ".long foo - ." or "movw REG, foo - .". We want
15448 calls to protected symbols to resolve directly to the function
15449 rather than going via the plt. If people want function pointer
15450 comparisons to work as expected then they should avoid writing
15451 assembly like ".long foo - .". */
ba93b8ac
DJ		 15452 if (SYMBOL_CALLS_LOCAL (info, h))
15453 {
0bdcacaf 15454 struct elf_dyn_relocs **pp;
ba93b8ac 15455
0bdcacaf 15456 for (pp = &eh->dyn_relocs; (p = *pp) != NULL; )
ba93b8ac
DJ		 15457 {
15458 p->count -= p->pc_count;
15459 p->pc_count = 0;
15460 if (p->count == 0)
15461 *pp = p->next;
15462 else
15463 pp = &p->next;
15464 }
15465 }
15466
4dfe6ac6 15467 if (htab->vxworks_p)
3348747a 15468 {
0bdcacaf 15469 struct elf_dyn_relocs **pp;
3348747a 15470
0bdcacaf 15471 for (pp = &eh->dyn_relocs; (p = *pp) != NULL; )
3348747a 15472 {
0bdcacaf 15473 if (strcmp (p->sec->output_section->name, ".tls_vars") == 0)
3348747a
NS		 15474 *pp = p->next;
15475 else
15476 pp = &p->next;
15477 }
15478 }
15479
ba93b8ac 15480 /* Also discard relocs on undefined weak syms with non-default
99059e56 15481 visibility. */
0bdcacaf 15482 if (eh->dyn_relocs != NULL
5e681ec4 15483 && h->root.type == bfd_link_hash_undefweak)
22d606e9
AM		 15484 {
15485 if (ELF_ST_VISIBILITY (h->other) != STV_DEFAULT)
0bdcacaf 15486 eh->dyn_relocs = NULL;
22d606e9
AM		 15487
15488 /* Make sure undefined weak symbols are output as a dynamic
15489 symbol in PIEs. */
15490 else if (h->dynindx == -1
15491 && !h->forced_local)
15492 {
15493 if (! bfd_elf_link_record_dynamic_symbol (info, h))
15494 return FALSE;
15495 }
15496 }
15497
67687978
PB		 15498 else if (htab->root.is_relocatable_executable && h->dynindx == -1
15499 && h->root.type == bfd_link_hash_new)
15500 {
15501 /* Output absolute symbols so that we can create relocations
15502 against them. For normal symbols we output a relocation
15503 against the section that contains them. */
15504 if (! bfd_elf_link_record_dynamic_symbol (info, h))
15505 return FALSE;
15506 }
15507
5e681ec4
PB		 15508 }
15509 else
15510 {
15511 /* For the non-shared case, discard space for relocs against
15512 symbols which turn out to need copy relocs or are not
15513 dynamic. */
15514
f5385ebf
AM		 15515 if (!h->non_got_ref
15516 && ((h->def_dynamic
15517 && !h->def_regular)
5e681ec4
PB		 15518 || (htab->root.dynamic_sections_created
15519 && (h->root.type == bfd_link_hash_undefweak
15520 || h->root.type == bfd_link_hash_undefined))))
15521 {
15522 /* Make sure this symbol is output as a dynamic symbol.
15523 Undefined weak syms won't yet be marked as dynamic. */
15524 if (h->dynindx == -1
f5385ebf 15525 && !h->forced_local)
5e681ec4 15526 {
c152c796 15527 if (! bfd_elf_link_record_dynamic_symbol (info, h))
5e681ec4
PB		 15528 return FALSE;
15529 }
15530
15531 /* If that succeeded, we know we'll be keeping all the
15532 relocs. */
15533 if (h->dynindx != -1)
15534 goto keep;
15535 }
15536
0bdcacaf 15537 eh->dyn_relocs = NULL;
5e681ec4
PB		 15538
15539 keep: ;
15540 }
15541
15542 /* Finally, allocate space. */
0bdcacaf 15543 for (p = eh->dyn_relocs; p != NULL; p = p->next)
5e681ec4 15544 {
0bdcacaf 15545 asection *sreloc = elf_section_data (p->sec)->sreloc;
34e77a92
RS		 15546 if (h->type == STT_GNU_IFUNC
15547 && eh->plt.noncall_refcount == 0
15548 && SYMBOL_REFERENCES_LOCAL (info, h))
15549 elf32_arm_allocate_irelocs (info, sreloc, p->count);
15550 else
15551 elf32_arm_allocate_dynrelocs (info, sreloc, p->count);
5e681ec4
PB		 15552 }
15553
15554 return TRUE;
15555}
15556
08d1f311
DJ		 15557/* Find any dynamic relocs that apply to read-only sections. */
15558
15559static bfd_boolean
8029a119 15560elf32_arm_readonly_dynrelocs (struct elf_link_hash_entry * h, void * inf)
08d1f311 15561{
8029a119 15562 struct elf32_arm_link_hash_entry * eh;
0bdcacaf 15563 struct elf_dyn_relocs * p;
08d1f311 15564
08d1f311 15565 eh = (struct elf32_arm_link_hash_entry *) h;
0bdcacaf 15566 for (p = eh->dyn_relocs; p != NULL; p = p->next)
08d1f311 15567 {
0bdcacaf 15568 asection *s = p->sec;
08d1f311
DJ		 15569
15570 if (s != NULL && (s->flags & SEC_READONLY) != 0)
15571 {
15572 struct bfd_link_info *info = (struct bfd_link_info *) inf;
15573
15574 info->flags |= DF_TEXTREL;
15575
15576 /* Not an error, just cut short the traversal. */
15577 return FALSE;
15578 }
15579 }
15580 return TRUE;
15581}
15582
d504ffc8
DJ		 15583void
15584bfd_elf32_arm_set_byteswap_code (struct bfd_link_info *info,
15585 int byteswap_code)
15586{
15587 struct elf32_arm_link_hash_table *globals;
15588
15589 globals = elf32_arm_hash_table (info);
4dfe6ac6
NC		 15590 if (globals == NULL)
15591 return;
15592
d504ffc8
DJ		 15593 globals->byteswap_code = byteswap_code;
15594}
15595
252b5132
RH		 15596/* Set the sizes of the dynamic sections. */
15597
b34976b6 15598static bfd_boolean
57e8b36a
NC		 15599elf32_arm_size_dynamic_sections (bfd * output_bfd ATTRIBUTE_UNUSED,
15600 struct bfd_link_info * info)
252b5132
RH		 15601{
15602 bfd * dynobj;
15603 asection * s;
b34976b6
AM		 15604 bfd_boolean plt;
15605 bfd_boolean relocs;
5e681ec4
PB		 15606 bfd *ibfd;
15607 struct elf32_arm_link_hash_table *htab;
252b5132 15608
5e681ec4 15609 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 15610 if (htab == NULL)
15611 return FALSE;
15612
252b5132
RH		 15613 dynobj = elf_hash_table (info)->dynobj;
15614 BFD_ASSERT (dynobj != NULL);
39b41c9c 15615 check_use_blx (htab);
252b5132
RH		 15616
15617 if (elf_hash_table (info)->dynamic_sections_created)
15618 {
15619 /* Set the contents of the .interp section to the interpreter. */
9b8b325a 15620 if (bfd_link_executable (info) && !info->nointerp)
252b5132 15621 {
3d4d4302 15622 s = bfd_get_linker_section (dynobj, ".interp");
252b5132 15623 BFD_ASSERT (s != NULL);
eea6121a 15624 s->size = sizeof ELF_DYNAMIC_INTERPRETER;
252b5132
RH		 15625 s->contents = (unsigned char *) ELF_DYNAMIC_INTERPRETER;
15626 }
15627 }
5e681ec4
PB		 15628
15629 /* Set up .got offsets for local syms, and space for local dynamic
15630 relocs. */
c72f2fb2 15631 for (ibfd = info->input_bfds; ibfd != NULL; ibfd = ibfd->link.next)
252b5132 15632 {
5e681ec4
PB		 15633 bfd_signed_vma *local_got;
15634 bfd_signed_vma *end_local_got;
34e77a92 15635 struct arm_local_iplt_info **local_iplt_ptr, *local_iplt;
5e681ec4 15636 char *local_tls_type;
0855e32b 15637 bfd_vma *local_tlsdesc_gotent;
5e681ec4
PB		 15638 bfd_size_type locsymcount;
15639 Elf_Internal_Shdr *symtab_hdr;
15640 asection *srel;
4dfe6ac6 15641 bfd_boolean is_vxworks = htab->vxworks_p;
34e77a92 15642 unsigned int symndx;
5e681ec4 15643
0ffa91dd 15644 if (! is_arm_elf (ibfd))
5e681ec4
PB		 15645 continue;
15646
15647 for (s = ibfd->sections; s != NULL; s = s->next)
15648 {
0bdcacaf 15649 struct elf_dyn_relocs *p;
5e681ec4 15650
0bdcacaf 15651 for (p = (struct elf_dyn_relocs *)
99059e56 15652 elf_section_data (s)->local_dynrel; p != NULL; p = p->next)
5e681ec4 15653 {
0bdcacaf
RS		 15654 if (!bfd_is_abs_section (p->sec)
15655 && bfd_is_abs_section (p->sec->output_section))
5e681ec4
PB		 15656 {
15657 /* Input section has been discarded, either because
15658 it is a copy of a linkonce section or due to
15659 linker script /DISCARD/, so we'll be discarding
15660 the relocs too. */
15661 }
3348747a 15662 else if (is_vxworks
0bdcacaf 15663 && strcmp (p->sec->output_section->name,
3348747a
NS		 15664 ".tls_vars") == 0)
15665 {
15666 /* Relocations in vxworks .tls_vars sections are
15667 handled specially by the loader. */
15668 }
5e681ec4
PB		 15669 else if (p->count != 0)
15670 {
0bdcacaf 15671 srel = elf_section_data (p->sec)->sreloc;
47beaa6a 15672 elf32_arm_allocate_dynrelocs (info, srel, p->count);
0bdcacaf 15673 if ((p->sec->output_section->flags & SEC_READONLY) != 0)
5e681ec4
PB		 15674 info->flags |= DF_TEXTREL;
15675 }
15676 }
15677 }
15678
15679 local_got = elf_local_got_refcounts (ibfd);
15680 if (!local_got)
15681 continue;
15682
0ffa91dd 15683 symtab_hdr = & elf_symtab_hdr (ibfd);
5e681ec4
PB		 15684 locsymcount = symtab_hdr->sh_info;
15685 end_local_got = local_got + locsymcount;
34e77a92 15686 local_iplt_ptr = elf32_arm_local_iplt (ibfd);
ba93b8ac 15687 local_tls_type = elf32_arm_local_got_tls_type (ibfd);
0855e32b 15688 local_tlsdesc_gotent = elf32_arm_local_tlsdesc_gotent (ibfd);
34e77a92 15689 symndx = 0;
362d30a1
RS		 15690 s = htab->root.sgot;
15691 srel = htab->root.srelgot;
0855e32b 15692 for (; local_got < end_local_got;
34e77a92
RS		 15693 ++local_got, ++local_iplt_ptr, ++local_tls_type,
15694 ++local_tlsdesc_gotent, ++symndx)
5e681ec4 15695 {
0855e32b 15696 *local_tlsdesc_gotent = (bfd_vma) -1;
34e77a92
RS		 15697 local_iplt = *local_iplt_ptr;
15698 if (local_iplt != NULL)
15699 {
15700 struct elf_dyn_relocs *p;
15701
15702 if (local_iplt->root.refcount > 0)
15703 {
15704 elf32_arm_allocate_plt_entry (info, TRUE,
15705 &local_iplt->root,
15706 &local_iplt->arm);
15707 if (local_iplt->arm.noncall_refcount == 0)
15708 /* All references to the PLT are calls, so all
15709 non-call references can resolve directly to the
15710 run-time target. This means that the .got entry
15711 would be the same as the .igot.plt entry, so there's
15712 no point creating both. */
15713 *local_got = 0;
15714 }
15715 else
15716 {
15717 BFD_ASSERT (local_iplt->arm.noncall_refcount == 0);
15718 local_iplt->root.offset = (bfd_vma) -1;
15719 }
15720
15721 for (p = local_iplt->dyn_relocs; p != NULL; p = p->next)
15722 {
15723 asection *psrel;
15724
15725 psrel = elf_section_data (p->sec)->sreloc;
15726 if (local_iplt->arm.noncall_refcount == 0)
15727 elf32_arm_allocate_irelocs (info, psrel, p->count);
15728 else
15729 elf32_arm_allocate_dynrelocs (info, psrel, p->count);
15730 }
15731 }
5e681ec4
PB		 15732 if (*local_got > 0)
15733 {
34e77a92
RS		 15734 Elf_Internal_Sym *isym;
15735
eea6121a 15736 *local_got = s->size;
ba93b8ac
DJ		 15737 if (*local_tls_type & GOT_TLS_GD)
15738 /* TLS_GD relocs need an 8-byte structure in the GOT. */
15739 s->size += 8;
0855e32b
NS		 15740 if (*local_tls_type & GOT_TLS_GDESC)
15741 {
15742 *local_tlsdesc_gotent = htab->root.sgotplt->size
15743 - elf32_arm_compute_jump_table_size (htab);
15744 htab->root.sgotplt->size += 8;
15745 *local_got = (bfd_vma) -2;
34e77a92 15746 /* plt.got_offset needs to know there's a TLS_DESC
0855e32b 15747 reloc in the middle of .got.plt. */
99059e56 15748 htab->num_tls_desc++;
0855e32b 15749 }
ba93b8ac
DJ		 15750 if (*local_tls_type & GOT_TLS_IE)
15751 s->size += 4;
ba93b8ac 15752
0855e32b
NS		 15753 if (*local_tls_type & GOT_NORMAL)
15754 {
15755 /* If the symbol is both GD and GDESC, *local_got
15756 may have been overwritten. */
15757 *local_got = s->size;
15758 s->size += 4;
15759 }
15760
34e77a92
RS		 15761 isym = bfd_sym_from_r_symndx (&htab->sym_cache, ibfd, symndx);
15762 if (isym == NULL)
15763 return FALSE;
15764
15765 /* If all references to an STT_GNU_IFUNC PLT are calls,
15766 then all non-call references, including this GOT entry,
15767 resolve directly to the run-time target. */
15768 if (ELF32_ST_TYPE (isym->st_info) == STT_GNU_IFUNC
15769 && (local_iplt == NULL
15770 || local_iplt->arm.noncall_refcount == 0))
15771 elf32_arm_allocate_irelocs (info, srel, 1);
0e1862bb 15772 else if (bfd_link_pic (info) || output_bfd->flags & DYNAMIC)
0855e32b 15773 {
0e1862bb 15774 if ((bfd_link_pic (info) && !(*local_tls_type & GOT_TLS_GDESC))
3064e1ff
JB		 15775 || *local_tls_type & GOT_TLS_GD)
15776 elf32_arm_allocate_dynrelocs (info, srel, 1);
99059e56 15777
0e1862bb 15778 if (bfd_link_pic (info) && *local_tls_type & GOT_TLS_GDESC)
3064e1ff
JB		 15779 {
15780 elf32_arm_allocate_dynrelocs (info,
15781 htab->root.srelplt, 1);
15782 htab->tls_trampoline = -1;
15783 }
0855e32b 15784 }
5e681ec4
PB		 15785 }
15786 else
15787 *local_got = (bfd_vma) -1;
15788 }
252b5132
RH		 15789 }
15790
ba93b8ac
DJ		 15791 if (htab->tls_ldm_got.refcount > 0)
15792 {
15793 /* Allocate two GOT entries and one dynamic relocation (if necessary)
15794 for R_ARM_TLS_LDM32 relocations. */
362d30a1
RS		 15795 htab->tls_ldm_got.offset = htab->root.sgot->size;
15796 htab->root.sgot->size += 8;
0e1862bb 15797 if (bfd_link_pic (info))
47beaa6a 15798 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
ba93b8ac
DJ		 15799 }
15800 else
15801 htab->tls_ldm_got.offset = -1;
15802
5e681ec4
PB		 15803 /* Allocate global sym .plt and .got entries, and space for global
15804 sym dynamic relocs. */
47beaa6a 15805 elf_link_hash_traverse (& htab->root, allocate_dynrelocs_for_symbol, info);
252b5132 15806
d504ffc8 15807 /* Here we rummage through the found bfds to collect glue information. */
c72f2fb2 15808 for (ibfd = info->input_bfds; ibfd != NULL; ibfd = ibfd->link.next)
c7b8f16e 15809 {
0ffa91dd 15810 if (! is_arm_elf (ibfd))
e44a2c9c
AM		 15811 continue;
15812
c7b8f16e
JB		 15813 /* Initialise mapping tables for code/data. */
15814 bfd_elf32_arm_init_maps (ibfd);
906e58ca 15815
c7b8f16e 15816 if (!bfd_elf32_arm_process_before_allocation (ibfd, info)
a504d23a
LA		 15817 || !bfd_elf32_arm_vfp11_erratum_scan (ibfd, info)
15818 || !bfd_elf32_arm_stm32l4xx_erratum_scan (ibfd, info))
99059e56
RM		 15819 /* xgettext:c-format */
15820 _bfd_error_handler (_("Errors encountered processing file %s"),
c7b8f16e
JB		 15821 ibfd->filename);
15822 }
d504ffc8 15823
3e6b1042
DJ		 15824 /* Allocate space for the glue sections now that we've sized them. */
15825 bfd_elf32_arm_allocate_interworking_sections (info);
15826
0855e32b
NS		 15827 /* For every jump slot reserved in the sgotplt, reloc_count is
15828 incremented. However, when we reserve space for TLS descriptors,
15829 it's not incremented, so in order to compute the space reserved
15830 for them, it suffices to multiply the reloc count by the jump
15831 slot size. */
15832 if (htab->root.srelplt)
15833 htab->sgotplt_jump_table_size = elf32_arm_compute_jump_table_size(htab);
15834
15835 if (htab->tls_trampoline)
15836 {
15837 if (htab->root.splt->size == 0)
15838 htab->root.splt->size += htab->plt_header_size;
b38cadfb 15839
0855e32b
NS		 15840 htab->tls_trampoline = htab->root.splt->size;
15841 htab->root.splt->size += htab->plt_entry_size;
b38cadfb 15842
0855e32b 15843 /* If we're not using lazy TLS relocations, don't generate the
99059e56 15844 PLT and GOT entries they require. */
0855e32b
NS		 15845 if (!(info->flags & DF_BIND_NOW))
15846 {
15847 htab->dt_tlsdesc_got = htab->root.sgot->size;
15848 htab->root.sgot->size += 4;
15849
15850 htab->dt_tlsdesc_plt = htab->root.splt->size;
15851 htab->root.splt->size += 4 * ARRAY_SIZE (dl_tlsdesc_lazy_trampoline);
15852 }
15853 }
15854
252b5132
RH		 15855 /* The check_relocs and adjust_dynamic_symbol entry points have
15856 determined the sizes of the various dynamic sections. Allocate
15857 memory for them. */
b34976b6
AM		 15858 plt = FALSE;
15859 relocs = FALSE;
252b5132
RH		 15860 for (s = dynobj->sections; s != NULL; s = s->next)
15861 {
15862 const char * name;
252b5132
RH		 15863
15864 if ((s->flags & SEC_LINKER_CREATED) == 0)
15865 continue;
15866
15867 /* It's OK to base decisions on the section name, because none
15868 of the dynobj section names depend upon the input files. */
15869 name = bfd_get_section_name (dynobj, s);
15870
34e77a92 15871 if (s == htab->root.splt)
252b5132 15872 {
c456f082
AM		 15873 /* Remember whether there is a PLT. */
15874 plt = s->size != 0;
252b5132 15875 }
0112cd26 15876 else if (CONST_STRNEQ (name, ".rel"))
252b5132 15877 {
c456f082 15878 if (s->size != 0)
252b5132 15879 {
252b5132 15880 /* Remember whether there are any reloc sections other
00a97672 15881 than .rel(a).plt and .rela.plt.unloaded. */
362d30a1 15882 if (s != htab->root.srelplt && s != htab->srelplt2)
b34976b6 15883 relocs = TRUE;
252b5132
RH		 15884
15885 /* We use the reloc_count field as a counter if we need
15886 to copy relocs into the output file. */
15887 s->reloc_count = 0;
15888 }
15889 }
34e77a92
RS		 15890 else if (s != htab->root.sgot
15891 && s != htab->root.sgotplt
15892 && s != htab->root.iplt
15893 && s != htab->root.igotplt
15894 && s != htab->sdynbss)
252b5132
RH		 15895 {
15896 /* It's not one of our sections, so don't allocate space. */
15897 continue;
15898 }
15899
c456f082 15900 if (s->size == 0)
252b5132 15901 {
c456f082 15902 /* If we don't need this section, strip it from the
00a97672
RS		 15903 output file. This is mostly to handle .rel(a).bss and
15904 .rel(a).plt. We must create both sections in
c456f082
AM		 15905 create_dynamic_sections, because they must be created
15906 before the linker maps input sections to output
15907 sections. The linker does that before
15908 adjust_dynamic_symbol is called, and it is that
15909 function which decides whether anything needs to go
15910 into these sections. */
8423293d 15911 s->flags |= SEC_EXCLUDE;
252b5132
RH		 15912 continue;
15913 }
15914
c456f082
AM		 15915 if ((s->flags & SEC_HAS_CONTENTS) == 0)
15916 continue;
15917
252b5132 15918 /* Allocate memory for the section contents. */
21d799b5 15919 s->contents = (unsigned char *) bfd_zalloc (dynobj, s->size);
c456f082 15920 if (s->contents == NULL)
b34976b6 15921 return FALSE;
252b5132
RH		 15922 }
15923
15924 if (elf_hash_table (info)->dynamic_sections_created)
15925 {
15926 /* Add some entries to the .dynamic section. We fill in the
15927 values later, in elf32_arm_finish_dynamic_sections, but we
15928 must add the entries now so that we get the correct size for
15929 the .dynamic section. The DT_DEBUG entry is filled in by the
15930 dynamic linker and used by the debugger. */
dc810e39 15931#define add_dynamic_entry(TAG, VAL) \
5a580b3a 15932 _bfd_elf_add_dynamic_entry (info, TAG, VAL)
dc810e39 15933
0e1862bb 15934 if (bfd_link_executable (info))
252b5132 15935 {
dc810e39 15936 if (!add_dynamic_entry (DT_DEBUG, 0))
b34976b6 15937 return FALSE;
252b5132
RH		 15938 }
15939
15940 if (plt)
15941 {
dc810e39
AM		 15942 if ( !add_dynamic_entry (DT_PLTGOT, 0)
15943 || !add_dynamic_entry (DT_PLTRELSZ, 0)
00a97672
RS		 15944 || !add_dynamic_entry (DT_PLTREL,
15945 htab->use_rel ? DT_REL : DT_RELA)
dc810e39 15946 || !add_dynamic_entry (DT_JMPREL, 0))
b34976b6 15947 return FALSE;
0855e32b
NS		 15948
15949 if (htab->dt_tlsdesc_plt &&
b38cadfb 15950 (!add_dynamic_entry (DT_TLSDESC_PLT,0)
0855e32b 15951 || !add_dynamic_entry (DT_TLSDESC_GOT,0)))
b38cadfb 15952 return FALSE;
252b5132
RH		 15953 }
15954
15955 if (relocs)
15956 {
00a97672
RS		 15957 if (htab->use_rel)
15958 {
15959 if (!add_dynamic_entry (DT_REL, 0)
15960 || !add_dynamic_entry (DT_RELSZ, 0)
15961 || !add_dynamic_entry (DT_RELENT, RELOC_SIZE (htab)))
15962 return FALSE;
15963 }
15964 else
15965 {
15966 if (!add_dynamic_entry (DT_RELA, 0)
15967 || !add_dynamic_entry (DT_RELASZ, 0)
15968 || !add_dynamic_entry (DT_RELAENT, RELOC_SIZE (htab)))
15969 return FALSE;
15970 }
252b5132
RH		 15971 }
15972
08d1f311
DJ		 15973 /* If any dynamic relocs apply to a read-only section,
15974 then we need a DT_TEXTREL entry. */
15975 if ((info->flags & DF_TEXTREL) == 0)
8029a119
NC		 15976 elf_link_hash_traverse (& htab->root, elf32_arm_readonly_dynrelocs,
15977 info);
08d1f311 15978
99e4ae17 15979 if ((info->flags & DF_TEXTREL) != 0)
252b5132 15980 {
dc810e39 15981 if (!add_dynamic_entry (DT_TEXTREL, 0))
b34976b6 15982 return FALSE;
252b5132 15983 }
7a2b07ff
NS		 15984 if (htab->vxworks_p
15985 && !elf_vxworks_add_dynamic_entries (output_bfd, info))
15986 return FALSE;
252b5132 15987 }
8532796c 15988#undef add_dynamic_entry
252b5132 15989
b34976b6 15990 return TRUE;
252b5132
RH		 15991}
15992
0855e32b
NS		 15993/* Size sections even though they're not dynamic. We use it to setup
15994 _TLS_MODULE_BASE_, if needed. */
15995
15996static bfd_boolean
15997elf32_arm_always_size_sections (bfd *output_bfd,
99059e56 15998 struct bfd_link_info *info)
0855e32b
NS		 15999{
16000 asection *tls_sec;
16001
0e1862bb 16002 if (bfd_link_relocatable (info))
0855e32b
NS		 16003 return TRUE;
16004
16005 tls_sec = elf_hash_table (info)->tls_sec;
16006
16007 if (tls_sec)
16008 {
16009 struct elf_link_hash_entry *tlsbase;
16010
16011 tlsbase = elf_link_hash_lookup
16012 (elf_hash_table (info), "_TLS_MODULE_BASE_", TRUE, TRUE, FALSE);
16013
16014 if (tlsbase)
99059e56
RM		 16015 {
16016 struct bfd_link_hash_entry *bh = NULL;
0855e32b 16017 const struct elf_backend_data *bed
99059e56 16018 = get_elf_backend_data (output_bfd);
0855e32b 16019
99059e56 16020 if (!(_bfd_generic_link_add_one_symbol
0855e32b
NS		 16021 (info, output_bfd, "_TLS_MODULE_BASE_", BSF_LOCAL,
16022 tls_sec, 0, NULL, FALSE,
16023 bed->collect, &bh)))
16024 return FALSE;
b38cadfb 16025
99059e56
RM		 16026 tlsbase->type = STT_TLS;
16027 tlsbase = (struct elf_link_hash_entry *)bh;
16028 tlsbase->def_regular = 1;
16029 tlsbase->other = STV_HIDDEN;
16030 (*bed->elf_backend_hide_symbol) (info, tlsbase, TRUE);
0855e32b
NS		 16031 }
16032 }
16033 return TRUE;
16034}
16035
252b5132
RH		 16036/* Finish up dynamic symbol handling. We set the contents of various
16037 dynamic sections here. */
16038
b34976b6 16039static bfd_boolean
906e58ca
NC		 16040elf32_arm_finish_dynamic_symbol (bfd * output_bfd,
16041 struct bfd_link_info * info,
16042 struct elf_link_hash_entry * h,
16043 Elf_Internal_Sym * sym)
252b5132 16044{
e5a52504 16045 struct elf32_arm_link_hash_table *htab;
b7693d02 16046 struct elf32_arm_link_hash_entry *eh;
252b5132 16047
e5a52504 16048 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 16049 if (htab == NULL)
16050 return FALSE;
16051
b7693d02 16052 eh = (struct elf32_arm_link_hash_entry *) h;
252b5132
RH		 16053
16054 if (h->plt.offset != (bfd_vma) -1)
16055 {
34e77a92 16056 if (!eh->is_iplt)
e5a52504 16057 {
34e77a92 16058 BFD_ASSERT (h->dynindx != -1);
57460bcf
NC		 16059 if (! elf32_arm_populate_plt_entry (output_bfd, info, &h->plt, &eh->plt,
16060 h->dynindx, 0))
16061 return FALSE;
e5a52504 16062 }
57e8b36a 16063
f5385ebf 16064 if (!h->def_regular)
252b5132
RH		 16065 {
16066 /* Mark the symbol as undefined, rather than as defined in
3a635617 16067 the .plt section. */
252b5132 16068 sym->st_shndx = SHN_UNDEF;
3a635617 16069 /* If the symbol is weak we need to clear the value.
d982ba73
PB		 16070 Otherwise, the PLT entry would provide a definition for
16071 the symbol even if the symbol wasn't defined anywhere,
3a635617
WN		 16072 and so the symbol would never be NULL. Leave the value if
16073 there were any relocations where pointer equality matters
16074 (this is a clue for the dynamic linker, to make function
16075 pointer comparisons work between an application and shared
16076 library). */
97323ad1 16077 if (!h->ref_regular_nonweak || !h->pointer_equality_needed)
d982ba73 16078 sym->st_value = 0;
252b5132 16079 }
34e77a92
RS		 16080 else if (eh->is_iplt && eh->plt.noncall_refcount != 0)
16081 {
16082 /* At least one non-call relocation references this .iplt entry,
16083 so the .iplt entry is the function's canonical address. */
16084 sym->st_info = ELF_ST_INFO (ELF_ST_BIND (sym->st_info), STT_FUNC);
39d911fc 16085 ARM_SET_SYM_BRANCH_TYPE (sym->st_target_internal, ST_BRANCH_TO_ARM);
34e77a92
RS		 16086 sym->st_shndx = (_bfd_elf_section_from_bfd_section
16087 (output_bfd, htab->root.iplt->output_section));
16088 sym->st_value = (h->plt.offset
16089 + htab->root.iplt->output_section->vma
16090 + htab->root.iplt->output_offset);
16091 }
252b5132
RH		 16092 }
16093
f5385ebf 16094 if (h->needs_copy)
252b5132
RH		 16095 {
16096 asection * s;
947216bf 16097 Elf_Internal_Rela rel;
252b5132
RH		 16098
16099 /* This symbol needs a copy reloc. Set it up. */
252b5132
RH		 16100 BFD_ASSERT (h->dynindx != -1
16101 && (h->root.type == bfd_link_hash_defined
16102 || h->root.type == bfd_link_hash_defweak));
16103
362d30a1 16104 s = htab->srelbss;
252b5132
RH		 16105 BFD_ASSERT (s != NULL);
16106
00a97672 16107 rel.r_addend = 0;
252b5132
RH		 16108 rel.r_offset = (h->root.u.def.value
16109 + h->root.u.def.section->output_section->vma
16110 + h->root.u.def.section->output_offset);
16111 rel.r_info = ELF32_R_INFO (h->dynindx, R_ARM_COPY);
47beaa6a 16112 elf32_arm_add_dynreloc (output_bfd, info, s, &rel);
252b5132
RH		 16113 }
16114
00a97672
RS		 16115 /* Mark _DYNAMIC and _GLOBAL_OFFSET_TABLE_ as absolute. On VxWorks,
16116 the _GLOBAL_OFFSET_TABLE_ symbol is not absolute: it is relative
16117 to the ".got" section. */
9637f6ef 16118 if (h == htab->root.hdynamic
00a97672 16119 || (!htab->vxworks_p && h == htab->root.hgot))
252b5132
RH		 16120 sym->st_shndx = SHN_ABS;
16121
b34976b6 16122 return TRUE;
252b5132
RH		 16123}
16124
0855e32b
NS		 16125static void
16126arm_put_trampoline (struct elf32_arm_link_hash_table *htab, bfd *output_bfd,
16127 void *contents,
16128 const unsigned long *template, unsigned count)
16129{
16130 unsigned ix;
b38cadfb 16131
0855e32b
NS		 16132 for (ix = 0; ix != count; ix++)
16133 {
16134 unsigned long insn = template[ix];
16135
16136 /* Emit mov pc,rx if bx is not permitted. */
16137 if (htab->fix_v4bx == 1 && (insn & 0x0ffffff0) == 0x012fff10)
16138 insn = (insn & 0xf000000f) | 0x01a0f000;
16139 put_arm_insn (htab, output_bfd, insn, (char *)contents + ix*4);
16140 }
16141}
16142
99059e56
RM		 16143/* Install the special first PLT entry for elf32-arm-nacl. Unlike
16144 other variants, NaCl needs this entry in a static executable's
16145 .iplt too. When we're handling that case, GOT_DISPLACEMENT is
16146 zero. For .iplt really only the last bundle is useful, and .iplt
16147 could have a shorter first entry, with each individual PLT entry's
16148 relative branch calculated differently so it targets the last
16149 bundle instead of the instruction before it (labelled .Lplt_tail
16150 above). But it's simpler to keep the size and layout of PLT0
16151 consistent with the dynamic case, at the cost of some dead code at
16152 the start of .iplt and the one dead store to the stack at the start
16153 of .Lplt_tail. */
16154static void
16155arm_nacl_put_plt0 (struct elf32_arm_link_hash_table *htab, bfd *output_bfd,
16156 asection *plt, bfd_vma got_displacement)
16157{
16158 unsigned int i;
16159
16160 put_arm_insn (htab, output_bfd,
16161 elf32_arm_nacl_plt0_entry[0]
16162 | arm_movw_immediate (got_displacement),
16163 plt->contents + 0);
16164 put_arm_insn (htab, output_bfd,
16165 elf32_arm_nacl_plt0_entry[1]
16166 | arm_movt_immediate (got_displacement),
16167 plt->contents + 4);
16168
16169 for (i = 2; i < ARRAY_SIZE (elf32_arm_nacl_plt0_entry); ++i)
16170 put_arm_insn (htab, output_bfd,
16171 elf32_arm_nacl_plt0_entry[i],
16172 plt->contents + (i * 4));
16173}
16174
252b5132
RH		 16175/* Finish up the dynamic sections. */
16176
b34976b6 16177static bfd_boolean
57e8b36a 16178elf32_arm_finish_dynamic_sections (bfd * output_bfd, struct bfd_link_info * info)
252b5132
RH		 16179{
16180 bfd * dynobj;
16181 asection * sgot;
16182 asection * sdyn;
4dfe6ac6
NC		 16183 struct elf32_arm_link_hash_table *htab;
16184
16185 htab = elf32_arm_hash_table (info);
16186 if (htab == NULL)
16187 return FALSE;
252b5132
RH		 16188
16189 dynobj = elf_hash_table (info)->dynobj;
16190
362d30a1 16191 sgot = htab->root.sgotplt;
894891db
NC		 16192 /* A broken linker script might have discarded the dynamic sections.
16193 Catch this here so that we do not seg-fault later on. */
16194 if (sgot != NULL && bfd_is_abs_section (sgot->output_section))
16195 return FALSE;
3d4d4302 16196 sdyn = bfd_get_linker_section (dynobj, ".dynamic");
252b5132
RH		 16197
16198 if (elf_hash_table (info)->dynamic_sections_created)
16199 {
16200 asection *splt;
16201 Elf32_External_Dyn *dyncon, *dynconend;
16202
362d30a1 16203 splt = htab->root.splt;
24a1ba0f 16204 BFD_ASSERT (splt != NULL && sdyn != NULL);
cbc704f3 16205 BFD_ASSERT (htab->symbian_p || sgot != NULL);
252b5132
RH		 16206
16207 dyncon = (Elf32_External_Dyn *) sdyn->contents;
eea6121a 16208 dynconend = (Elf32_External_Dyn *) (sdyn->contents + sdyn->size);
9b485d32 16209
252b5132
RH		 16210 for (; dyncon < dynconend; dyncon++)
16211 {
16212 Elf_Internal_Dyn dyn;
16213 const char * name;
16214 asection * s;
16215
16216 bfd_elf32_swap_dyn_in (dynobj, dyncon, &dyn);
16217
16218 switch (dyn.d_tag)
16219 {
229fcec5
MM		 16220 unsigned int type;
16221
252b5132 16222 default:
7a2b07ff
NS		 16223 if (htab->vxworks_p
16224 && elf_vxworks_finish_dynamic_entry (output_bfd, &dyn))
16225 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
252b5132
RH		 16226 break;
16227
229fcec5
MM		 16228 case DT_HASH:
16229 name = ".hash";
16230 goto get_vma_if_bpabi;
16231 case DT_STRTAB:
16232 name = ".dynstr";
16233 goto get_vma_if_bpabi;
16234 case DT_SYMTAB:
16235 name = ".dynsym";
16236 goto get_vma_if_bpabi;
c0042f5d
MM		 16237 case DT_VERSYM:
16238 name = ".gnu.version";
16239 goto get_vma_if_bpabi;
16240 case DT_VERDEF:
16241 name = ".gnu.version_d";
16242 goto get_vma_if_bpabi;
16243 case DT_VERNEED:
16244 name = ".gnu.version_r";
16245 goto get_vma_if_bpabi;
16246
252b5132 16247 case DT_PLTGOT:
4ade44b7 16248 name = htab->symbian_p ? ".got" : ".got.plt";
252b5132
RH		 16249 goto get_vma;
16250 case DT_JMPREL:
00a97672 16251 name = RELOC_SECTION (htab, ".plt");
252b5132 16252 get_vma:
4ade44b7 16253 s = bfd_get_linker_section (dynobj, name);
05456594
NC		 16254 if (s == NULL)
16255 {
05456594 16256 (*_bfd_error_handler)
4ade44b7 16257 (_("could not find section %s"), name);
05456594
NC		 16258 bfd_set_error (bfd_error_invalid_operation);
16259 return FALSE;
16260 }
229fcec5 16261 if (!htab->symbian_p)
4ade44b7 16262 dyn.d_un.d_ptr = s->output_section->vma + s->output_offset;
229fcec5
MM		 16263 else
16264 /* In the BPABI, tags in the PT_DYNAMIC section point
16265 at the file offset, not the memory address, for the
16266 convenience of the post linker. */
4ade44b7 16267 dyn.d_un.d_ptr = s->output_section->filepos + s->output_offset;
252b5132
RH		 16268 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
16269 break;
16270
229fcec5
MM		 16271 get_vma_if_bpabi:
16272 if (htab->symbian_p)
16273 goto get_vma;
16274 break;
16275
252b5132 16276 case DT_PLTRELSZ:
362d30a1 16277 s = htab->root.srelplt;
252b5132 16278 BFD_ASSERT (s != NULL);
eea6121a 16279 dyn.d_un.d_val = s->size;
252b5132
RH		 16280 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
16281 break;
906e58ca 16282
252b5132 16283 case DT_RELSZ:
00a97672 16284 case DT_RELASZ:
229fcec5
MM		 16285 if (!htab->symbian_p)
16286 {
16287 /* My reading of the SVR4 ABI indicates that the
16288 procedure linkage table relocs (DT_JMPREL) should be
16289 included in the overall relocs (DT_REL). This is
16290 what Solaris does. However, UnixWare can not handle
16291 that case. Therefore, we override the DT_RELSZ entry
16292 here to make it not include the JMPREL relocs. Since
00a97672 16293 the linker script arranges for .rel(a).plt to follow all
229fcec5
MM		 16294 other relocation sections, we don't have to worry
16295 about changing the DT_REL entry. */
362d30a1 16296 s = htab->root.srelplt;
229fcec5
MM		 16297 if (s != NULL)
16298 dyn.d_un.d_val -= s->size;
16299 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
16300 break;
16301 }
8029a119 16302 /* Fall through. */
229fcec5
MM		 16303
16304 case DT_REL:
16305 case DT_RELA:
229fcec5
MM		 16306 /* In the BPABI, the DT_REL tag must point at the file
16307 offset, not the VMA, of the first relocation
16308 section. So, we use code similar to that in
16309 elflink.c, but do not check for SHF_ALLOC on the
16310 relcoation section, since relocations sections are
16311 never allocated under the BPABI. The comments above
16312 about Unixware notwithstanding, we include all of the
16313 relocations here. */
16314 if (htab->symbian_p)
16315 {
16316 unsigned int i;
16317 type = ((dyn.d_tag == DT_REL || dyn.d_tag == DT_RELSZ)
16318 ? SHT_REL : SHT_RELA);
16319 dyn.d_un.d_val = 0;
16320 for (i = 1; i < elf_numsections (output_bfd); i++)
16321 {
906e58ca 16322 Elf_Internal_Shdr *hdr
229fcec5
MM		 16323 = elf_elfsections (output_bfd)[i];
16324 if (hdr->sh_type == type)
16325 {
906e58ca 16326 if (dyn.d_tag == DT_RELSZ
229fcec5
MM		 16327 || dyn.d_tag == DT_RELASZ)
16328 dyn.d_un.d_val += hdr->sh_size;
de52dba4
AM		 16329 else if ((ufile_ptr) hdr->sh_offset
16330 <= dyn.d_un.d_val - 1)
229fcec5
MM		 16331 dyn.d_un.d_val = hdr->sh_offset;
16332 }
16333 }
16334 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
16335 }
252b5132 16336 break;
88f7bcd5 16337
0855e32b 16338 case DT_TLSDESC_PLT:
99059e56 16339 s = htab->root.splt;
0855e32b
NS		 16340 dyn.d_un.d_ptr = (s->output_section->vma + s->output_offset
16341 + htab->dt_tlsdesc_plt);
16342 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
16343 break;
16344
16345 case DT_TLSDESC_GOT:
99059e56 16346 s = htab->root.sgot;
0855e32b 16347 dyn.d_un.d_ptr = (s->output_section->vma + s->output_offset
99059e56 16348 + htab->dt_tlsdesc_got);
0855e32b
NS		 16349 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
16350 break;
16351
88f7bcd5
NC		 16352 /* Set the bottom bit of DT_INIT/FINI if the
16353 corresponding function is Thumb. */
16354 case DT_INIT:
16355 name = info->init_function;
16356 goto get_sym;
16357 case DT_FINI:
16358 name = info->fini_function;
16359 get_sym:
16360 /* If it wasn't set by elf_bfd_final_link
4cc11e76 16361 then there is nothing to adjust. */
88f7bcd5
NC		 16362 if (dyn.d_un.d_val != 0)
16363 {
16364 struct elf_link_hash_entry * eh;
16365
16366 eh = elf_link_hash_lookup (elf_hash_table (info), name,
b34976b6 16367 FALSE, FALSE, TRUE);
39d911fc
TP		 16368 if (eh != NULL
16369 && ARM_GET_SYM_BRANCH_TYPE (eh->target_internal)
16370 == ST_BRANCH_TO_THUMB)
88f7bcd5
NC		 16371 {
16372 dyn.d_un.d_val |= 1;
b34976b6 16373 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
88f7bcd5
NC		 16374 }
16375 }
16376 break;
252b5132
RH		 16377 }
16378 }
16379
24a1ba0f 16380 /* Fill in the first entry in the procedure linkage table. */
4dfe6ac6 16381 if (splt->size > 0 && htab->plt_header_size)
f7a74f8c 16382 {
00a97672
RS		 16383 const bfd_vma *plt0_entry;
16384 bfd_vma got_address, plt_address, got_displacement;
16385
16386 /* Calculate the addresses of the GOT and PLT. */
16387 got_address = sgot->output_section->vma + sgot->output_offset;
16388 plt_address = splt->output_section->vma + splt->output_offset;
16389
16390 if (htab->vxworks_p)
16391 {
16392 /* The VxWorks GOT is relocated by the dynamic linker.
16393 Therefore, we must emit relocations rather than simply
16394 computing the values now. */
16395 Elf_Internal_Rela rel;
16396
16397 plt0_entry = elf32_arm_vxworks_exec_plt0_entry;
52ab56c2
PB		 16398 put_arm_insn (htab, output_bfd, plt0_entry[0],
16399 splt->contents + 0);
16400 put_arm_insn (htab, output_bfd, plt0_entry[1],
16401 splt->contents + 4);
16402 put_arm_insn (htab, output_bfd, plt0_entry[2],
16403 splt->contents + 8);
00a97672
RS		 16404 bfd_put_32 (output_bfd, got_address, splt->contents + 12);
16405
8029a119 16406 /* Generate a relocation for _GLOBAL_OFFSET_TABLE_. */
00a97672
RS		 16407 rel.r_offset = plt_address + 12;
16408 rel.r_info = ELF32_R_INFO (htab->root.hgot->indx, R_ARM_ABS32);
16409 rel.r_addend = 0;
16410 SWAP_RELOC_OUT (htab) (output_bfd, &rel,
16411 htab->srelplt2->contents);
16412 }
b38cadfb 16413 else if (htab->nacl_p)
99059e56
RM		 16414 arm_nacl_put_plt0 (htab, output_bfd, splt,
16415 got_address + 8 - (plt_address + 16));
eed94f8f
NC		 16416 else if (using_thumb_only (htab))
16417 {
16418 got_displacement = got_address - (plt_address + 12);
16419
16420 plt0_entry = elf32_thumb2_plt0_entry;
16421 put_arm_insn (htab, output_bfd, plt0_entry[0],
16422 splt->contents + 0);
16423 put_arm_insn (htab, output_bfd, plt0_entry[1],
16424 splt->contents + 4);
16425 put_arm_insn (htab, output_bfd, plt0_entry[2],
16426 splt->contents + 8);
16427
16428 bfd_put_32 (output_bfd, got_displacement, splt->contents + 12);
16429 }
00a97672
RS		 16430 else
16431 {
16432 got_displacement = got_address - (plt_address + 16);
16433
16434 plt0_entry = elf32_arm_plt0_entry;
52ab56c2
PB		 16435 put_arm_insn (htab, output_bfd, plt0_entry[0],
16436 splt->contents + 0);
16437 put_arm_insn (htab, output_bfd, plt0_entry[1],
16438 splt->contents + 4);
16439 put_arm_insn (htab, output_bfd, plt0_entry[2],
16440 splt->contents + 8);
16441 put_arm_insn (htab, output_bfd, plt0_entry[3],
16442 splt->contents + 12);
5e681ec4 16443
5e681ec4 16444#ifdef FOUR_WORD_PLT
00a97672
RS		 16445 /* The displacement value goes in the otherwise-unused
16446 last word of the second entry. */
16447 bfd_put_32 (output_bfd, got_displacement, splt->contents + 28);
5e681ec4 16448#else
00a97672 16449 bfd_put_32 (output_bfd, got_displacement, splt->contents + 16);
5e681ec4 16450#endif
00a97672 16451 }
f7a74f8c 16452 }
252b5132
RH		 16453
16454 /* UnixWare sets the entsize of .plt to 4, although that doesn't
16455 really seem like the right value. */
74541ad4
AM		 16456 if (splt->output_section->owner == output_bfd)
16457 elf_section_data (splt->output_section)->this_hdr.sh_entsize = 4;
00a97672 16458
0855e32b
NS		 16459 if (htab->dt_tlsdesc_plt)
16460 {
16461 bfd_vma got_address
16462 = sgot->output_section->vma + sgot->output_offset;
16463 bfd_vma gotplt_address = (htab->root.sgot->output_section->vma
16464 + htab->root.sgot->output_offset);
16465 bfd_vma plt_address
16466 = splt->output_section->vma + splt->output_offset;
16467
b38cadfb 16468 arm_put_trampoline (htab, output_bfd,
0855e32b
NS		 16469 splt->contents + htab->dt_tlsdesc_plt,
16470 dl_tlsdesc_lazy_trampoline, 6);
16471
16472 bfd_put_32 (output_bfd,
16473 gotplt_address + htab->dt_tlsdesc_got
16474 - (plt_address + htab->dt_tlsdesc_plt)
16475 - dl_tlsdesc_lazy_trampoline[6],
16476 splt->contents + htab->dt_tlsdesc_plt + 24);
16477 bfd_put_32 (output_bfd,
16478 got_address - (plt_address + htab->dt_tlsdesc_plt)
16479 - dl_tlsdesc_lazy_trampoline[7],
16480 splt->contents + htab->dt_tlsdesc_plt + 24 + 4);
16481 }
16482
16483 if (htab->tls_trampoline)
16484 {
b38cadfb 16485 arm_put_trampoline (htab, output_bfd,
0855e32b
NS		 16486 splt->contents + htab->tls_trampoline,
16487 tls_trampoline, 3);
16488#ifdef FOUR_WORD_PLT
16489 bfd_put_32 (output_bfd, 0x00000000,
16490 splt->contents + htab->tls_trampoline + 12);
b38cadfb 16491#endif
0855e32b
NS		 16492 }
16493
0e1862bb
L		 16494 if (htab->vxworks_p
16495 && !bfd_link_pic (info)
16496 && htab->root.splt->size > 0)
00a97672
RS		 16497 {
16498 /* Correct the .rel(a).plt.unloaded relocations. They will have
16499 incorrect symbol indexes. */
16500 int num_plts;
eed62c48 16501 unsigned char *p;
00a97672 16502
362d30a1 16503 num_plts = ((htab->root.splt->size - htab->plt_header_size)
00a97672
RS		 16504 / htab->plt_entry_size);
16505 p = htab->srelplt2->contents + RELOC_SIZE (htab);
16506
16507 for (; num_plts; num_plts--)
16508 {
16509 Elf_Internal_Rela rel;
16510
16511 SWAP_RELOC_IN (htab) (output_bfd, p, &rel);
16512 rel.r_info = ELF32_R_INFO (htab->root.hgot->indx, R_ARM_ABS32);
16513 SWAP_RELOC_OUT (htab) (output_bfd, &rel, p);
16514 p += RELOC_SIZE (htab);
16515
16516 SWAP_RELOC_IN (htab) (output_bfd, p, &rel);
16517 rel.r_info = ELF32_R_INFO (htab->root.hplt->indx, R_ARM_ABS32);
16518 SWAP_RELOC_OUT (htab) (output_bfd, &rel, p);
16519 p += RELOC_SIZE (htab);
16520 }
16521 }
252b5132
RH		 16522 }
16523
99059e56
RM		 16524 if (htab->nacl_p && htab->root.iplt != NULL && htab->root.iplt->size > 0)
16525 /* NaCl uses a special first entry in .iplt too. */
16526 arm_nacl_put_plt0 (htab, output_bfd, htab->root.iplt, 0);
16527
252b5132 16528 /* Fill in the first three entries in the global offset table. */
229fcec5 16529 if (sgot)
252b5132 16530 {
229fcec5
MM		 16531 if (sgot->size > 0)
16532 {
16533 if (sdyn == NULL)
16534 bfd_put_32 (output_bfd, (bfd_vma) 0, sgot->contents);
16535 else
16536 bfd_put_32 (output_bfd,
16537 sdyn->output_section->vma + sdyn->output_offset,
16538 sgot->contents);
16539 bfd_put_32 (output_bfd, (bfd_vma) 0, sgot->contents + 4);
16540 bfd_put_32 (output_bfd, (bfd_vma) 0, sgot->contents + 8);
16541 }
252b5132 16542
229fcec5
MM		 16543 elf_section_data (sgot->output_section)->this_hdr.sh_entsize = 4;
16544 }
252b5132 16545
b34976b6 16546 return TRUE;
252b5132
RH		 16547}
16548
ba96a88f 16549static void
57e8b36a 16550elf32_arm_post_process_headers (bfd * abfd, struct bfd_link_info * link_info ATTRIBUTE_UNUSED)
ba96a88f 16551{
9b485d32 16552 Elf_Internal_Ehdr * i_ehdrp; /* ELF file header, internal form. */
e489d0ae 16553 struct elf32_arm_link_hash_table *globals;
ac4c9b04 16554 struct elf_segment_map *m;
ba96a88f
NC		 16555
16556 i_ehdrp = elf_elfheader (abfd);
16557
94a3258f
PB		 16558 if (EF_ARM_EABI_VERSION (i_ehdrp->e_flags) == EF_ARM_EABI_UNKNOWN)
16559 i_ehdrp->e_ident[EI_OSABI] = ELFOSABI_ARM;
16560 else
7394f108 16561 _bfd_elf_post_process_headers (abfd, link_info);
ba96a88f 16562 i_ehdrp->e_ident[EI_ABIVERSION] = ARM_ELF_ABI_VERSION;
e489d0ae 16563
93204d3a
PB		 16564 if (link_info)
16565 {
16566 globals = elf32_arm_hash_table (link_info);
4dfe6ac6 16567 if (globals != NULL && globals->byteswap_code)
93204d3a
PB		 16568 i_ehdrp->e_flags |= EF_ARM_BE8;
16569 }
3bfcb652
NC		 16570
16571 if (EF_ARM_EABI_VERSION (i_ehdrp->e_flags) == EF_ARM_EABI_VER5
16572 && ((i_ehdrp->e_type == ET_DYN) || (i_ehdrp->e_type == ET_EXEC)))
16573 {
16574 int abi = bfd_elf_get_obj_attr_int (abfd, OBJ_ATTR_PROC, Tag_ABI_VFP_args);
5c294fee 16575 if (abi == AEABI_VFP_args_vfp)
3bfcb652
NC		 16576 i_ehdrp->e_flags |= EF_ARM_ABI_FLOAT_HARD;
16577 else
16578 i_ehdrp->e_flags |= EF_ARM_ABI_FLOAT_SOFT;
16579 }
ac4c9b04
MG		 16580
16581 /* Scan segment to set p_flags attribute if it contains only sections with
f0728ee3 16582 SHF_ARM_PURECODE flag. */
ac4c9b04
MG		 16583 for (m = elf_seg_map (abfd); m != NULL; m = m->next)
16584 {
16585 unsigned int j;
16586
16587 if (m->count == 0)
16588 continue;
16589 for (j = 0; j < m->count; j++)
16590 {
f0728ee3 16591 if (!(elf_section_flags (m->sections[j]) & SHF_ARM_PURECODE))
ac4c9b04
MG		 16592 break;
16593 }
16594 if (j == m->count)
16595 {
16596 m->p_flags = PF_X;
16597 m->p_flags_valid = 1;
16598 }
16599 }
ba96a88f
NC		 16600}
16601
99e4ae17 16602static enum elf_reloc_type_class
7e612e98
AM		 16603elf32_arm_reloc_type_class (const struct bfd_link_info *info ATTRIBUTE_UNUSED,
16604 const asection *rel_sec ATTRIBUTE_UNUSED,
16605 const Elf_Internal_Rela *rela)
99e4ae17 16606{
f51e552e 16607 switch ((int) ELF32_R_TYPE (rela->r_info))
99e4ae17
AJ		 16608 {
16609 case R_ARM_RELATIVE:
16610 return reloc_class_relative;
16611 case R_ARM_JUMP_SLOT:
16612 return reloc_class_plt;
16613 case R_ARM_COPY:
16614 return reloc_class_copy;
109575d7
JW		 16615 case R_ARM_IRELATIVE:
16616 return reloc_class_ifunc;
99e4ae17
AJ		 16617 default:
16618 return reloc_class_normal;
16619 }
16620}
16621
e489d0ae 16622static void
57e8b36a 16623elf32_arm_final_write_processing (bfd *abfd, bfd_boolean linker ATTRIBUTE_UNUSED)
e16bb312 16624{
5a6c6817 16625 bfd_arm_update_notes (abfd, ARM_NOTE_SECTION);
e16bb312
NC		 16626}
16627
40a18ebd
NC		 16628/* Return TRUE if this is an unwinding table entry. */
16629
16630static bfd_boolean
16631is_arm_elf_unwind_section_name (bfd * abfd ATTRIBUTE_UNUSED, const char * name)
16632{
0112cd26
NC		 16633 return (CONST_STRNEQ (name, ELF_STRING_ARM_unwind)
16634 || CONST_STRNEQ (name, ELF_STRING_ARM_unwind_once));
40a18ebd
NC		 16635}
16636
16637
16638/* Set the type and flags for an ARM section. We do this by
16639 the section name, which is a hack, but ought to work. */
16640
16641static bfd_boolean
16642elf32_arm_fake_sections (bfd * abfd, Elf_Internal_Shdr * hdr, asection * sec)
16643{
16644 const char * name;
16645
16646 name = bfd_get_section_name (abfd, sec);
16647
16648 if (is_arm_elf_unwind_section_name (abfd, name))
16649 {
16650 hdr->sh_type = SHT_ARM_EXIDX;
16651 hdr->sh_flags |= SHF_LINK_ORDER;
16652 }
ac4c9b04 16653
f0728ee3
AV		 16654 if (sec->flags & SEC_ELF_PURECODE)
16655 hdr->sh_flags |= SHF_ARM_PURECODE;
ac4c9b04 16656
40a18ebd
NC		 16657 return TRUE;
16658}
16659
6dc132d9
L		 16660/* Handle an ARM specific section when reading an object file. This is
16661 called when bfd_section_from_shdr finds a section with an unknown
16662 type. */
40a18ebd
NC		 16663
16664static bfd_boolean
16665elf32_arm_section_from_shdr (bfd *abfd,
16666 Elf_Internal_Shdr * hdr,
6dc132d9
L		 16667 const char *name,
16668 int shindex)
40a18ebd
NC		 16669{
16670 /* There ought to be a place to keep ELF backend specific flags, but
16671 at the moment there isn't one. We just keep track of the
16672 sections by their name, instead. Fortunately, the ABI gives
16673 names for all the ARM specific sections, so we will probably get
16674 away with this. */
16675 switch (hdr->sh_type)
16676 {
16677 case SHT_ARM_EXIDX:
0951f019
RE		 16678 case SHT_ARM_PREEMPTMAP:
16679 case SHT_ARM_ATTRIBUTES:
40a18ebd
NC		 16680 break;
16681
16682 default:
16683 return FALSE;
16684 }
16685
6dc132d9 16686 if (! _bfd_elf_make_section_from_shdr (abfd, hdr, name, shindex))
40a18ebd
NC		 16687 return FALSE;
16688
16689 return TRUE;
16690}
e489d0ae 16691
44444f50
NC		 16692static _arm_elf_section_data *
16693get_arm_elf_section_data (asection * sec)
16694{
47b2e99c
JZ		 16695 if (sec && sec->owner && is_arm_elf (sec->owner))
16696 return elf32_arm_section_data (sec);
44444f50
NC		 16697 else
16698 return NULL;
8e3de13a
NC		 16699}
16700
4e617b1e
PB		 16701typedef struct
16702{
57402f1e 16703 void *flaginfo;
4e617b1e 16704 struct bfd_link_info *info;
91a5743d
PB		 16705 asection *sec;
16706 int sec_shndx;
6e0b88f1
AM		 16707 int (*func) (void *, const char *, Elf_Internal_Sym *,
16708 asection *, struct elf_link_hash_entry *);
4e617b1e
PB		 16709} output_arch_syminfo;
16710
16711enum map_symbol_type
16712{
16713 ARM_MAP_ARM,
16714 ARM_MAP_THUMB,
16715 ARM_MAP_DATA
16716};
16717
16718
7413f23f 16719/* Output a single mapping symbol. */
4e617b1e
PB		 16720
16721static bfd_boolean
7413f23f
DJ		 16722elf32_arm_output_map_sym (output_arch_syminfo *osi,
16723 enum map_symbol_type type,
16724 bfd_vma offset)
4e617b1e
PB		 16725{
16726 static const char *names[3] = {"$a", "$t", "$d"};
4e617b1e
PB		 16727 Elf_Internal_Sym sym;
16728
91a5743d
PB		 16729 sym.st_value = osi->sec->output_section->vma
16730 + osi->sec->output_offset
16731 + offset;
4e617b1e
PB		 16732 sym.st_size = 0;
16733 sym.st_other = 0;
16734 sym.st_info = ELF_ST_INFO (STB_LOCAL, STT_NOTYPE);
91a5743d 16735 sym.st_shndx = osi->sec_shndx;
35fc36a8 16736 sym.st_target_internal = 0;
fe33d2fa 16737 elf32_arm_section_map_add (osi->sec, names[type][1], offset);
57402f1e 16738 return osi->func (osi->flaginfo, names[type], &sym, osi->sec, NULL) == 1;
4e617b1e
PB		 16739}
16740
34e77a92
RS		 16741/* Output mapping symbols for the PLT entry described by ROOT_PLT and ARM_PLT.
16742 IS_IPLT_ENTRY_P says whether the PLT is in .iplt rather than .plt. */
4e617b1e
PB		 16743
16744static bfd_boolean
34e77a92
RS		 16745elf32_arm_output_plt_map_1 (output_arch_syminfo *osi,
16746 bfd_boolean is_iplt_entry_p,
16747 union gotplt_union *root_plt,
16748 struct arm_plt_info *arm_plt)
4e617b1e 16749{
4e617b1e 16750 struct elf32_arm_link_hash_table *htab;
34e77a92 16751 bfd_vma addr, plt_header_size;
4e617b1e 16752
34e77a92 16753 if (root_plt->offset == (bfd_vma) -1)
4e617b1e
PB		 16754 return TRUE;
16755
4dfe6ac6
NC		 16756 htab = elf32_arm_hash_table (osi->info);
16757 if (htab == NULL)
16758 return FALSE;
16759
34e77a92
RS		 16760 if (is_iplt_entry_p)
16761 {
16762 osi->sec = htab->root.iplt;
16763 plt_header_size = 0;
16764 }
16765 else
16766 {
16767 osi->sec = htab->root.splt;
16768 plt_header_size = htab->plt_header_size;
16769 }
16770 osi->sec_shndx = (_bfd_elf_section_from_bfd_section
16771 (osi->info->output_bfd, osi->sec->output_section));
16772
16773 addr = root_plt->offset & -2;
4e617b1e
PB		 16774 if (htab->symbian_p)
16775 {
7413f23f 16776 if (!elf32_arm_output_map_sym (osi, ARM_MAP_ARM, addr))
4e617b1e 16777 return FALSE;
7413f23f 16778 if (!elf32_arm_output_map_sym (osi, ARM_MAP_DATA, addr + 4))
4e617b1e
PB		 16779 return FALSE;
16780 }
16781 else if (htab->vxworks_p)
16782 {
7413f23f 16783 if (!elf32_arm_output_map_sym (osi, ARM_MAP_ARM, addr))
4e617b1e 16784 return FALSE;
7413f23f 16785 if (!elf32_arm_output_map_sym (osi, ARM_MAP_DATA, addr + 8))
4e617b1e 16786 return FALSE;
7413f23f 16787 if (!elf32_arm_output_map_sym (osi, ARM_MAP_ARM, addr + 12))
4e617b1e 16788 return FALSE;
7413f23f 16789 if (!elf32_arm_output_map_sym (osi, ARM_MAP_DATA, addr + 20))
4e617b1e
PB		 16790 return FALSE;
16791 }
b38cadfb
NC		 16792 else if (htab->nacl_p)
16793 {
16794 if (!elf32_arm_output_map_sym (osi, ARM_MAP_ARM, addr))
16795 return FALSE;
16796 }
eed94f8f
NC		 16797 else if (using_thumb_only (htab))
16798 {
16799 if (!elf32_arm_output_map_sym (osi, ARM_MAP_THUMB, addr))
16800 return FALSE;
6a631e86 16801 }
4e617b1e
PB		 16802 else
16803 {
34e77a92 16804 bfd_boolean thumb_stub_p;
bd97cb95 16805
34e77a92
RS		 16806 thumb_stub_p = elf32_arm_plt_needs_thumb_stub_p (osi->info, arm_plt);
16807 if (thumb_stub_p)
4e617b1e 16808 {
7413f23f 16809 if (!elf32_arm_output_map_sym (osi, ARM_MAP_THUMB, addr - 4))
4e617b1e
PB		 16810 return FALSE;
16811 }
16812#ifdef FOUR_WORD_PLT
7413f23f 16813 if (!elf32_arm_output_map_sym (osi, ARM_MAP_ARM, addr))
4e617b1e 16814 return FALSE;
7413f23f 16815 if (!elf32_arm_output_map_sym (osi, ARM_MAP_DATA, addr + 12))
4e617b1e
PB		 16816 return FALSE;
16817#else
906e58ca 16818 /* A three-word PLT with no Thumb thunk contains only Arm code,
4e617b1e
PB		 16819 so only need to output a mapping symbol for the first PLT entry and
16820 entries with thumb thunks. */
34e77a92 16821 if (thumb_stub_p || addr == plt_header_size)
4e617b1e 16822 {
7413f23f 16823 if (!elf32_arm_output_map_sym (osi, ARM_MAP_ARM, addr))
4e617b1e
PB		 16824 return FALSE;
16825 }
16826#endif
16827 }
16828
16829 return TRUE;
16830}
16831
34e77a92
RS		 16832/* Output mapping symbols for PLT entries associated with H. */
16833
16834static bfd_boolean
16835elf32_arm_output_plt_map (struct elf_link_hash_entry *h, void *inf)
16836{
16837 output_arch_syminfo *osi = (output_arch_syminfo *) inf;
16838 struct elf32_arm_link_hash_entry *eh;
16839
16840 if (h->root.type == bfd_link_hash_indirect)
16841 return TRUE;
16842
16843 if (h->root.type == bfd_link_hash_warning)
16844 /* When warning symbols are created, they **replace** the "real"
16845 entry in the hash table, thus we never get to see the real
16846 symbol in a hash traversal. So look at it now. */
16847 h = (struct elf_link_hash_entry *) h->root.u.i.link;
16848
16849 eh = (struct elf32_arm_link_hash_entry *) h;
16850 return elf32_arm_output_plt_map_1 (osi, SYMBOL_CALLS_LOCAL (osi->info, h),
16851 &h->plt, &eh->plt);
16852}
16853
4f4faa4d
TP		 16854/* Bind a veneered symbol to its veneer identified by its hash entry
16855 STUB_ENTRY. The veneered location thus loose its symbol. */
16856
16857static void
16858arm_stub_claim_sym (struct elf32_arm_stub_hash_entry *stub_entry)
16859{
16860 struct elf32_arm_link_hash_entry *hash = stub_entry->h;
16861
16862 BFD_ASSERT (hash);
16863 hash->root.root.u.def.section = stub_entry->stub_sec;
16864 hash->root.root.u.def.value = stub_entry->stub_offset;
16865 hash->root.size = stub_entry->stub_size;
16866}
16867
7413f23f
DJ		 16868/* Output a single local symbol for a generated stub. */
16869
16870static bfd_boolean
16871elf32_arm_output_stub_sym (output_arch_syminfo *osi, const char *name,
16872 bfd_vma offset, bfd_vma size)
16873{
7413f23f
DJ		 16874 Elf_Internal_Sym sym;
16875
7413f23f
DJ		 16876 sym.st_value = osi->sec->output_section->vma
16877 + osi->sec->output_offset
16878 + offset;
16879 sym.st_size = size;
16880 sym.st_other = 0;
16881 sym.st_info = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
16882 sym.st_shndx = osi->sec_shndx;
35fc36a8 16883 sym.st_target_internal = 0;
57402f1e 16884 return osi->func (osi->flaginfo, name, &sym, osi->sec, NULL) == 1;
7413f23f 16885}
4e617b1e 16886
da5938a2 16887static bfd_boolean
8029a119
NC		 16888arm_map_one_stub (struct bfd_hash_entry * gen_entry,
16889 void * in_arg)
da5938a2
NC		 16890{
16891 struct elf32_arm_stub_hash_entry *stub_entry;
da5938a2
NC		 16892 asection *stub_sec;
16893 bfd_vma addr;
7413f23f 16894 char *stub_name;
9a008db3 16895 output_arch_syminfo *osi;
d3ce72d0 16896 const insn_sequence *template_sequence;
461a49ca
DJ		 16897 enum stub_insn_type prev_type;
16898 int size;
16899 int i;
16900 enum map_symbol_type sym_type;
da5938a2
NC		 16901
16902 /* Massage our args to the form they really have. */
16903 stub_entry = (struct elf32_arm_stub_hash_entry *) gen_entry;
9a008db3 16904 osi = (output_arch_syminfo *) in_arg;
da5938a2 16905
da5938a2
NC		 16906 stub_sec = stub_entry->stub_sec;
16907
16908 /* Ensure this stub is attached to the current section being
7413f23f 16909 processed. */
da5938a2
NC		 16910 if (stub_sec != osi->sec)
16911 return TRUE;
16912
7413f23f 16913 addr = (bfd_vma) stub_entry->stub_offset;
d3ce72d0 16914 template_sequence = stub_entry->stub_template;
4f4faa4d
TP		 16915
16916 if (arm_stub_sym_claimed (stub_entry->stub_type))
16917 arm_stub_claim_sym (stub_entry);
16918 else
7413f23f 16919 {
4f4faa4d
TP		 16920 stub_name = stub_entry->output_name;
16921 switch (template_sequence[0].type)
16922 {
16923 case ARM_TYPE:
16924 if (!elf32_arm_output_stub_sym (osi, stub_name, addr,
16925 stub_entry->stub_size))
16926 return FALSE;
16927 break;
16928 case THUMB16_TYPE:
16929 case THUMB32_TYPE:
16930 if (!elf32_arm_output_stub_sym (osi, stub_name, addr | 1,
16931 stub_entry->stub_size))
16932 return FALSE;
16933 break;
16934 default:
16935 BFD_FAIL ();
16936 return 0;
16937 }
7413f23f 16938 }
da5938a2 16939
461a49ca
DJ		 16940 prev_type = DATA_TYPE;
16941 size = 0;
16942 for (i = 0; i < stub_entry->stub_template_size; i++)
16943 {
d3ce72d0 16944 switch (template_sequence[i].type)
461a49ca
DJ		 16945 {
16946 case ARM_TYPE:
16947 sym_type = ARM_MAP_ARM;
16948 break;
16949
16950 case THUMB16_TYPE:
48229727 16951 case THUMB32_TYPE:
461a49ca
DJ		 16952 sym_type = ARM_MAP_THUMB;
16953 break;
16954
16955 case DATA_TYPE:
16956 sym_type = ARM_MAP_DATA;
16957 break;
16958
16959 default:
16960 BFD_FAIL ();
4e31c731 16961 return FALSE;
461a49ca
DJ		 16962 }
16963
d3ce72d0 16964 if (template_sequence[i].type != prev_type)
461a49ca 16965 {
d3ce72d0 16966 prev_type = template_sequence[i].type;
461a49ca
DJ		 16967 if (!elf32_arm_output_map_sym (osi, sym_type, addr + size))
16968 return FALSE;
16969 }
16970
d3ce72d0 16971 switch (template_sequence[i].type)
461a49ca
DJ		 16972 {
16973 case ARM_TYPE:
48229727 16974 case THUMB32_TYPE:
461a49ca
DJ		 16975 size += 4;
16976 break;
16977
16978 case THUMB16_TYPE:
16979 size += 2;
16980 break;
16981
16982 case DATA_TYPE:
16983 size += 4;
16984 break;
16985
16986 default:
16987 BFD_FAIL ();
4e31c731 16988 return FALSE;
461a49ca
DJ		 16989 }
16990 }
16991
da5938a2
NC		 16992 return TRUE;
16993}
16994
33811162
DG		 16995/* Output mapping symbols for linker generated sections,
16996 and for those data-only sections that do not have a
16997 $d. */
4e617b1e
PB		 16998
16999static bfd_boolean
17000elf32_arm_output_arch_local_syms (bfd *output_bfd,
906e58ca 17001 struct bfd_link_info *info,
57402f1e 17002 void *flaginfo,
6e0b88f1
AM		 17003 int (*func) (void *, const char *,
17004 Elf_Internal_Sym *,
17005 asection *,
17006 struct elf_link_hash_entry *))
4e617b1e
PB		 17007{
17008 output_arch_syminfo osi;
17009 struct elf32_arm_link_hash_table *htab;
91a5743d
PB		 17010 bfd_vma offset;
17011 bfd_size_type size;
33811162 17012 bfd *input_bfd;
4e617b1e
PB		 17013
17014 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 17015 if (htab == NULL)
17016 return FALSE;
17017
906e58ca 17018 check_use_blx (htab);
91a5743d 17019
57402f1e 17020 osi.flaginfo = flaginfo;
4e617b1e
PB		 17021 osi.info = info;
17022 osi.func = func;
906e58ca 17023
33811162
DG		 17024 /* Add a $d mapping symbol to data-only sections that
17025 don't have any mapping symbol. This may result in (harmless) redundant
17026 mapping symbols. */
17027 for (input_bfd = info->input_bfds;
17028 input_bfd != NULL;
c72f2fb2 17029 input_bfd = input_bfd->link.next)
33811162
DG		 17030 {
17031 if ((input_bfd->flags & (BFD_LINKER_CREATED | HAS_SYMS)) == HAS_SYMS)
17032 for (osi.sec = input_bfd->sections;
17033 osi.sec != NULL;
17034 osi.sec = osi.sec->next)
17035 {
17036 if (osi.sec->output_section != NULL
f7dd8c79
DJ		 17037 && ((osi.sec->output_section->flags & (SEC_ALLOC | SEC_CODE))
17038 != 0)
33811162
DG		 17039 && (osi.sec->flags & (SEC_HAS_CONTENTS | SEC_LINKER_CREATED))
17040 == SEC_HAS_CONTENTS
17041 && get_arm_elf_section_data (osi.sec) != NULL
501abfe0 17042 && get_arm_elf_section_data (osi.sec)->mapcount == 0
7d500b83
CL		 17043 && osi.sec->size > 0
17044 && (osi.sec->flags & SEC_EXCLUDE) == 0)
33811162
DG		 17045 {
17046 osi.sec_shndx = _bfd_elf_section_from_bfd_section
17047 (output_bfd, osi.sec->output_section);
17048 if (osi.sec_shndx != (int)SHN_BAD)
17049 elf32_arm_output_map_sym (&osi, ARM_MAP_DATA, 0);
17050 }
17051 }
17052 }
17053
91a5743d
PB		 17054 /* ARM->Thumb glue. */
17055 if (htab->arm_glue_size > 0)
17056 {
3d4d4302
AM		 17057 osi.sec = bfd_get_linker_section (htab->bfd_of_glue_owner,
17058 ARM2THUMB_GLUE_SECTION_NAME);
91a5743d
PB		 17059
17060 osi.sec_shndx = _bfd_elf_section_from_bfd_section
17061 (output_bfd, osi.sec->output_section);
0e1862bb 17062 if (bfd_link_pic (info) || htab->root.is_relocatable_executable
91a5743d
PB		 17063 || htab->pic_veneer)
17064 size = ARM2THUMB_PIC_GLUE_SIZE;
17065 else if (htab->use_blx)
17066 size = ARM2THUMB_V5_STATIC_GLUE_SIZE;
17067 else
17068 size = ARM2THUMB_STATIC_GLUE_SIZE;
4e617b1e 17069
91a5743d
PB		 17070 for (offset = 0; offset < htab->arm_glue_size; offset += size)
17071 {
7413f23f
DJ		 17072 elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, offset);
17073 elf32_arm_output_map_sym (&osi, ARM_MAP_DATA, offset + size - 4);
91a5743d
PB		 17074 }
17075 }
17076
17077 /* Thumb->ARM glue. */
17078 if (htab->thumb_glue_size > 0)
17079 {
3d4d4302
AM		 17080 osi.sec = bfd_get_linker_section (htab->bfd_of_glue_owner,
17081 THUMB2ARM_GLUE_SECTION_NAME);
91a5743d
PB		 17082
17083 osi.sec_shndx = _bfd_elf_section_from_bfd_section
17084 (output_bfd, osi.sec->output_section);
17085 size = THUMB2ARM_GLUE_SIZE;
17086
17087 for (offset = 0; offset < htab->thumb_glue_size; offset += size)
17088 {
7413f23f
DJ		 17089 elf32_arm_output_map_sym (&osi, ARM_MAP_THUMB, offset);
17090 elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, offset + 4);
91a5743d
PB		 17091 }
17092 }
17093
845b51d6
PB		 17094 /* ARMv4 BX veneers. */
17095 if (htab->bx_glue_size > 0)
17096 {
3d4d4302
AM		 17097 osi.sec = bfd_get_linker_section (htab->bfd_of_glue_owner,
17098 ARM_BX_GLUE_SECTION_NAME);
845b51d6
PB		 17099
17100 osi.sec_shndx = _bfd_elf_section_from_bfd_section
17101 (output_bfd, osi.sec->output_section);
17102
7413f23f 17103 elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, 0);
845b51d6
PB		 17104 }
17105
8029a119
NC		 17106 /* Long calls stubs. */
17107 if (htab->stub_bfd && htab->stub_bfd->sections)
17108 {
da5938a2 17109 asection* stub_sec;
8029a119 17110
da5938a2
NC		 17111 for (stub_sec = htab->stub_bfd->sections;
17112 stub_sec != NULL;
8029a119
NC		 17113 stub_sec = stub_sec->next)
17114 {
17115 /* Ignore non-stub sections. */
17116 if (!strstr (stub_sec->name, STUB_SUFFIX))
17117 continue;
da5938a2 17118
8029a119 17119 osi.sec = stub_sec;
da5938a2 17120
8029a119
NC		 17121 osi.sec_shndx = _bfd_elf_section_from_bfd_section
17122 (output_bfd, osi.sec->output_section);
da5938a2 17123
8029a119
NC		 17124 bfd_hash_traverse (&htab->stub_hash_table, arm_map_one_stub, &osi);
17125 }
17126 }
da5938a2 17127
91a5743d 17128 /* Finally, output mapping symbols for the PLT. */
34e77a92 17129 if (htab->root.splt && htab->root.splt->size > 0)
4e617b1e 17130 {
34e77a92
RS		 17131 osi.sec = htab->root.splt;
17132 osi.sec_shndx = (_bfd_elf_section_from_bfd_section
17133 (output_bfd, osi.sec->output_section));
17134
17135 /* Output mapping symbols for the plt header. SymbianOS does not have a
17136 plt header. */
17137 if (htab->vxworks_p)
17138 {
17139 /* VxWorks shared libraries have no PLT header. */
0e1862bb 17140 if (!bfd_link_pic (info))
34e77a92
RS		 17141 {
17142 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, 0))
17143 return FALSE;
17144 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_DATA, 12))
17145 return FALSE;
17146 }
17147 }
b38cadfb
NC		 17148 else if (htab->nacl_p)
17149 {
17150 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, 0))
17151 return FALSE;
17152 }
eed94f8f
NC		 17153 else if (using_thumb_only (htab))
17154 {
17155 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_THUMB, 0))
17156 return FALSE;
17157 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_DATA, 12))
17158 return FALSE;
17159 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_THUMB, 16))
17160 return FALSE;
17161 }
34e77a92 17162 else if (!htab->symbian_p)
4e617b1e 17163 {
7413f23f 17164 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, 0))
4e617b1e 17165 return FALSE;
34e77a92
RS		 17166#ifndef FOUR_WORD_PLT
17167 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_DATA, 16))
4e617b1e 17168 return FALSE;
34e77a92 17169#endif
4e617b1e
PB		 17170 }
17171 }
99059e56
RM		 17172 if (htab->nacl_p && htab->root.iplt && htab->root.iplt->size > 0)
17173 {
17174 /* NaCl uses a special first entry in .iplt too. */
17175 osi.sec = htab->root.iplt;
17176 osi.sec_shndx = (_bfd_elf_section_from_bfd_section
17177 (output_bfd, osi.sec->output_section));
17178 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, 0))
17179 return FALSE;
17180 }
34e77a92
RS		 17181 if ((htab->root.splt && htab->root.splt->size > 0)
17182 || (htab->root.iplt && htab->root.iplt->size > 0))
4e617b1e 17183 {
34e77a92
RS		 17184 elf_link_hash_traverse (&htab->root, elf32_arm_output_plt_map, &osi);
17185 for (input_bfd = info->input_bfds;
17186 input_bfd != NULL;
c72f2fb2 17187 input_bfd = input_bfd->link.next)
34e77a92
RS		 17188 {
17189 struct arm_local_iplt_info **local_iplt;
17190 unsigned int i, num_syms;
4e617b1e 17191
34e77a92
RS		 17192 local_iplt = elf32_arm_local_iplt (input_bfd);
17193 if (local_iplt != NULL)
17194 {
17195 num_syms = elf_symtab_hdr (input_bfd).sh_info;
17196 for (i = 0; i < num_syms; i++)
17197 if (local_iplt[i] != NULL
17198 && !elf32_arm_output_plt_map_1 (&osi, TRUE,
17199 &local_iplt[i]->root,
17200 &local_iplt[i]->arm))
17201 return FALSE;
17202 }
17203 }
17204 }
0855e32b
NS		 17205 if (htab->dt_tlsdesc_plt != 0)
17206 {
17207 /* Mapping symbols for the lazy tls trampoline. */
17208 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, htab->dt_tlsdesc_plt))
17209 return FALSE;
b38cadfb 17210
0855e32b
NS		 17211 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_DATA,
17212 htab->dt_tlsdesc_plt + 24))
17213 return FALSE;
17214 }
17215 if (htab->tls_trampoline != 0)
17216 {
17217 /* Mapping symbols for the tls trampoline. */
17218 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, htab->tls_trampoline))
17219 return FALSE;
17220#ifdef FOUR_WORD_PLT
17221 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_DATA,
17222 htab->tls_trampoline + 12))
17223 return FALSE;
b38cadfb 17224#endif
0855e32b 17225 }
b38cadfb 17226
4e617b1e
PB		 17227 return TRUE;
17228}
17229
54ddd295
TP		 17230/* Filter normal symbols of CMSE entry functions of ABFD to include in
17231 the import library. All SYMCOUNT symbols of ABFD can be examined
17232 from their pointers in SYMS. Pointers of symbols to keep should be
17233 stored continuously at the beginning of that array.
17234
17235 Returns the number of symbols to keep. */
17236
17237static unsigned int
17238elf32_arm_filter_cmse_symbols (bfd *abfd ATTRIBUTE_UNUSED,
17239 struct bfd_link_info *info,
17240 asymbol **syms, long symcount)
17241{
17242 size_t maxnamelen;
17243 char *cmse_name;
17244 long src_count, dst_count = 0;
17245 struct elf32_arm_link_hash_table *htab;
17246
17247 htab = elf32_arm_hash_table (info);
17248 if (!htab->stub_bfd || !htab->stub_bfd->sections)
17249 symcount = 0;
17250
17251 maxnamelen = 128;
17252 cmse_name = (char *) bfd_malloc (maxnamelen);
17253 for (src_count = 0; src_count < symcount; src_count++)
17254 {
17255 struct elf32_arm_link_hash_entry *cmse_hash;
17256 asymbol *sym;
17257 flagword flags;
17258 char *name;
17259 size_t namelen;
17260
17261 sym = syms[src_count];
17262 flags = sym->flags;
17263 name = (char *) bfd_asymbol_name (sym);
17264
17265 if ((flags & BSF_FUNCTION) != BSF_FUNCTION)
17266 continue;
17267 if (!(flags & (BSF_GLOBAL | BSF_WEAK)))
17268 continue;
17269
17270 namelen = strlen (name) + sizeof (CMSE_PREFIX) + 1;
17271 if (namelen > maxnamelen)
17272 {
17273 cmse_name = (char *)
17274 bfd_realloc (cmse_name, namelen);
17275 maxnamelen = namelen;
17276 }
17277 snprintf (cmse_name, maxnamelen, "%s%s", CMSE_PREFIX, name);
17278 cmse_hash = (struct elf32_arm_link_hash_entry *)
17279 elf_link_hash_lookup (&(htab)->root, cmse_name, FALSE, FALSE, TRUE);
17280
17281 if (!cmse_hash
17282 || (cmse_hash->root.root.type != bfd_link_hash_defined
17283 && cmse_hash->root.root.type != bfd_link_hash_defweak)
17284 || cmse_hash->root.type != STT_FUNC)
17285 continue;
17286
17287 if (!ARM_GET_SYM_CMSE_SPCL (cmse_hash->root.target_internal))
17288 continue;
17289
17290 syms[dst_count++] = sym;
17291 }
17292 free (cmse_name);
17293
17294 syms[dst_count] = NULL;
17295
17296 return dst_count;
17297}
17298
17299/* Filter symbols of ABFD to include in the import library. All
17300 SYMCOUNT symbols of ABFD can be examined from their pointers in
17301 SYMS. Pointers of symbols to keep should be stored continuously at
17302 the beginning of that array.
17303
17304 Returns the number of symbols to keep. */
17305
17306static unsigned int
17307elf32_arm_filter_implib_symbols (bfd *abfd ATTRIBUTE_UNUSED,
17308 struct bfd_link_info *info,
17309 asymbol **syms, long symcount)
17310{
17311 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (info);
17312
17313 if (globals->cmse_implib)
17314 return elf32_arm_filter_cmse_symbols (abfd, info, syms, symcount);
17315 else
17316 return _bfd_elf_filter_global_symbols (abfd, info, syms, symcount);
17317}
17318
e489d0ae
PB		 17319/* Allocate target specific section data. */
17320
17321static bfd_boolean
17322elf32_arm_new_section_hook (bfd *abfd, asection *sec)
17323{
f592407e
AM		 17324 if (!sec->used_by_bfd)
17325 {
17326 _arm_elf_section_data *sdata;
17327 bfd_size_type amt = sizeof (*sdata);
e489d0ae 17328
21d799b5 17329 sdata = (_arm_elf_section_data *) bfd_zalloc (abfd, amt);
f592407e
AM		 17330 if (sdata == NULL)
17331 return FALSE;
17332 sec->used_by_bfd = sdata;
17333 }
e489d0ae
PB		 17334
17335 return _bfd_elf_new_section_hook (abfd, sec);
17336}
17337
17338
17339/* Used to order a list of mapping symbols by address. */
17340
17341static int
17342elf32_arm_compare_mapping (const void * a, const void * b)
17343{
7f6a71ff
JM		 17344 const elf32_arm_section_map *amap = (const elf32_arm_section_map *) a;
17345 const elf32_arm_section_map *bmap = (const elf32_arm_section_map *) b;
17346
17347 if (amap->vma > bmap->vma)
17348 return 1;
17349 else if (amap->vma < bmap->vma)
17350 return -1;
17351 else if (amap->type > bmap->type)
17352 /* Ensure results do not depend on the host qsort for objects with
17353 multiple mapping symbols at the same address by sorting on type
17354 after vma. */
17355 return 1;
17356 else if (amap->type < bmap->type)
17357 return -1;
17358 else
17359 return 0;
e489d0ae
PB		 17360}
17361
2468f9c9
PB		 17362/* Add OFFSET to lower 31 bits of ADDR, leaving other bits unmodified. */
17363
17364static unsigned long
17365offset_prel31 (unsigned long addr, bfd_vma offset)
17366{
17367 return (addr & ~0x7ffffffful) | ((addr + offset) & 0x7ffffffful);
17368}
17369
17370/* Copy an .ARM.exidx table entry, adding OFFSET to (applied) PREL31
17371 relocations. */
17372
17373static void
17374copy_exidx_entry (bfd *output_bfd, bfd_byte *to, bfd_byte *from, bfd_vma offset)
17375{
17376 unsigned long first_word = bfd_get_32 (output_bfd, from);
17377 unsigned long second_word = bfd_get_32 (output_bfd, from + 4);
b38cadfb 17378
2468f9c9
PB		 17379 /* High bit of first word is supposed to be zero. */
17380 if ((first_word & 0x80000000ul) == 0)
17381 first_word = offset_prel31 (first_word, offset);
b38cadfb 17382
2468f9c9
PB		 17383 /* If the high bit of the first word is clear, and the bit pattern is not 0x1
17384 (EXIDX_CANTUNWIND), this is an offset to an .ARM.extab entry. */
17385 if ((second_word != 0x1) && ((second_word & 0x80000000ul) == 0))
17386 second_word = offset_prel31 (second_word, offset);
b38cadfb 17387
2468f9c9
PB		 17388 bfd_put_32 (output_bfd, first_word, to);
17389 bfd_put_32 (output_bfd, second_word, to + 4);
17390}
e489d0ae 17391
48229727
JB		 17392/* Data for make_branch_to_a8_stub(). */
17393
b38cadfb
NC		 17394struct a8_branch_to_stub_data
17395{
48229727
JB		 17396 asection *writing_section;
17397 bfd_byte *contents;
17398};
17399
17400
17401/* Helper to insert branches to Cortex-A8 erratum stubs in the right
17402 places for a particular section. */
17403
17404static bfd_boolean
17405make_branch_to_a8_stub (struct bfd_hash_entry *gen_entry,
99059e56 17406 void *in_arg)
48229727
JB		 17407{
17408 struct elf32_arm_stub_hash_entry *stub_entry;
17409 struct a8_branch_to_stub_data *data;
17410 bfd_byte *contents;
17411 unsigned long branch_insn;
17412 bfd_vma veneered_insn_loc, veneer_entry_loc;
17413 bfd_signed_vma branch_offset;
17414 bfd *abfd;
8d9d9490 17415 unsigned int loc;
48229727
JB		 17416
17417 stub_entry = (struct elf32_arm_stub_hash_entry *) gen_entry;
17418 data = (struct a8_branch_to_stub_data *) in_arg;
17419
17420 if (stub_entry->target_section != data->writing_section
4563a860 17421 || stub_entry->stub_type < arm_stub_a8_veneer_lwm)
48229727
JB		 17422 return TRUE;
17423
17424 contents = data->contents;
17425
8d9d9490
TP		 17426 /* We use target_section as Cortex-A8 erratum workaround stubs are only
17427 generated when both source and target are in the same section. */
48229727
JB		 17428 veneered_insn_loc = stub_entry->target_section->output_section->vma
17429 + stub_entry->target_section->output_offset
8d9d9490 17430 + stub_entry->source_value;
48229727
JB		 17431
17432 veneer_entry_loc = stub_entry->stub_sec->output_section->vma
17433 + stub_entry->stub_sec->output_offset
17434 + stub_entry->stub_offset;
17435
17436 if (stub_entry->stub_type == arm_stub_a8_veneer_blx)
17437 veneered_insn_loc &= ~3u;
17438
17439 branch_offset = veneer_entry_loc - veneered_insn_loc - 4;
17440
17441 abfd = stub_entry->target_section->owner;
8d9d9490 17442 loc = stub_entry->source_value;
48229727
JB		 17443
17444 /* We attempt to avoid this condition by setting stubs_always_after_branch
17445 in elf32_arm_size_stubs if we've enabled the Cortex-A8 erratum workaround.
17446 This check is just to be on the safe side... */
17447 if ((veneered_insn_loc & ~0xfff) == (veneer_entry_loc & ~0xfff))
17448 {
17449 (*_bfd_error_handler) (_("%B: error: Cortex-A8 erratum stub is "
17450 "allocated in unsafe location"), abfd);
17451 return FALSE;
17452 }
17453
17454 switch (stub_entry->stub_type)
17455 {
17456 case arm_stub_a8_veneer_b:
17457 case arm_stub_a8_veneer_b_cond:
17458 branch_insn = 0xf0009000;
17459 goto jump24;
17460
17461 case arm_stub_a8_veneer_blx:
17462 branch_insn = 0xf000e800;
17463 goto jump24;
17464
17465 case arm_stub_a8_veneer_bl:
17466 {
17467 unsigned int i1, j1, i2, j2, s;
17468
17469 branch_insn = 0xf000d000;
17470
17471 jump24:
17472 if (branch_offset < -16777216 || branch_offset > 16777214)
17473 {
17474 /* There's not much we can do apart from complain if this
17475 happens. */
17476 (*_bfd_error_handler) (_("%B: error: Cortex-A8 erratum stub out "
17477 "of range (input file too large)"), abfd);
17478 return FALSE;
17479 }
17480
17481 /* i1 = not(j1 eor s), so:
17482 not i1 = j1 eor s
17483 j1 = (not i1) eor s. */
17484
17485 branch_insn |= (branch_offset >> 1) & 0x7ff;
17486 branch_insn |= ((branch_offset >> 12) & 0x3ff) << 16;
17487 i2 = (branch_offset >> 22) & 1;
17488 i1 = (branch_offset >> 23) & 1;
17489 s = (branch_offset >> 24) & 1;
17490 j1 = (!i1) ^ s;
17491 j2 = (!i2) ^ s;
17492 branch_insn |= j2 << 11;
17493 branch_insn |= j1 << 13;
17494 branch_insn |= s << 26;
17495 }
17496 break;
17497
17498 default:
17499 BFD_FAIL ();
17500 return FALSE;
17501 }
17502
8d9d9490
TP		 17503 bfd_put_16 (abfd, (branch_insn >> 16) & 0xffff, &contents[loc]);
17504 bfd_put_16 (abfd, branch_insn & 0xffff, &contents[loc + 2]);
48229727
JB		 17505
17506 return TRUE;
17507}
17508
a504d23a
LA		 17509/* Beginning of stm32l4xx work-around. */
17510
17511/* Functions encoding instructions necessary for the emission of the
17512 fix-stm32l4xx-629360.
17513 Encoding is extracted from the
17514 ARM (C) Architecture Reference Manual
17515 ARMv7-A and ARMv7-R edition
17516 ARM DDI 0406C.b (ID072512). */
17517
17518static inline bfd_vma
82188b29 17519create_instruction_branch_absolute (int branch_offset)
a504d23a
LA		 17520{
17521 /* A8.8.18 B (A8-334)
17522 B target_address (Encoding T4). */
17523 /* 1111 - 0Sii - iiii - iiii - 10J1 - Jiii - iiii - iiii. */
17524 /* jump offset is: S:I1:I2:imm10:imm11:0. */
17525 /* with : I1 = NOT (J1 EOR S) I2 = NOT (J2 EOR S). */
17526
a504d23a
LA		 17527 int s = ((branch_offset & 0x1000000) >> 24);
17528 int j1 = s ^ !((branch_offset & 0x800000) >> 23);
17529 int j2 = s ^ !((branch_offset & 0x400000) >> 22);
17530
17531 if (branch_offset < -(1 << 24) || branch_offset >= (1 << 24))
17532 BFD_ASSERT (0 && "Error: branch out of range. Cannot create branch.");
17533
17534 bfd_vma patched_inst = 0xf0009000
17535 | s << 26 /* S. */
17536 | (((unsigned long) (branch_offset) >> 12) & 0x3ff) << 16 /* imm10. */
17537 | j1 << 13 /* J1. */
17538 | j2 << 11 /* J2. */
17539 | (((unsigned long) (branch_offset) >> 1) & 0x7ff); /* imm11. */
17540
17541 return patched_inst;
17542}
17543
17544static inline bfd_vma
17545create_instruction_ldmia (int base_reg, int wback, int reg_mask)
17546{
17547 /* A8.8.57 LDM/LDMIA/LDMFD (A8-396)
17548 LDMIA Rn!, {Ra, Rb, Rc, ...} (Encoding T2). */
17549 bfd_vma patched_inst = 0xe8900000
17550 | (/*W=*/wback << 21)
17551 | (base_reg << 16)
17552 | (reg_mask & 0x0000ffff);
17553
17554 return patched_inst;
17555}
17556
17557static inline bfd_vma
17558create_instruction_ldmdb (int base_reg, int wback, int reg_mask)
17559{
17560 /* A8.8.60 LDMDB/LDMEA (A8-402)
17561 LDMDB Rn!, {Ra, Rb, Rc, ...} (Encoding T1). */
17562 bfd_vma patched_inst = 0xe9100000
17563 | (/*W=*/wback << 21)
17564 | (base_reg << 16)
17565 | (reg_mask & 0x0000ffff);
17566
17567 return patched_inst;
17568}
17569
17570static inline bfd_vma
17571create_instruction_mov (int target_reg, int source_reg)
17572{
17573 /* A8.8.103 MOV (register) (A8-486)
17574 MOV Rd, Rm (Encoding T1). */
17575 bfd_vma patched_inst = 0x4600
17576 | (target_reg & 0x7)
17577 | ((target_reg & 0x8) >> 3) << 7
17578 | (source_reg << 3);
17579
17580 return patched_inst;
17581}
17582
17583static inline bfd_vma
17584create_instruction_sub (int target_reg, int source_reg, int value)
17585{
17586 /* A8.8.221 SUB (immediate) (A8-708)
17587 SUB Rd, Rn, #value (Encoding T3). */
17588 bfd_vma patched_inst = 0xf1a00000
17589 | (target_reg << 8)
17590 | (source_reg << 16)
17591 | (/*S=*/0 << 20)
17592 | ((value & 0x800) >> 11) << 26
17593 | ((value & 0x700) >> 8) << 12
17594 | (value & 0x0ff);
17595
17596 return patched_inst;
17597}
17598
17599static inline bfd_vma
9239bbd3 17600create_instruction_vldmia (int base_reg, int is_dp, int wback, int num_words,
a504d23a
LA		 17601 int first_reg)
17602{
17603 /* A8.8.332 VLDM (A8-922)
9239bbd3
CM		 17604 VLMD{MODE} Rn{!}, {list} (Encoding T1 or T2). */
17605 bfd_vma patched_inst = (is_dp ? 0xec900b00 : 0xec900a00)
a504d23a
LA		 17606 | (/*W=*/wback << 21)
17607 | (base_reg << 16)
9239bbd3
CM		 17608 | (num_words & 0x000000ff)
17609 | (((unsigned)first_reg >> 1) & 0x0000000f) << 12
a504d23a
LA		 17610 | (first_reg & 0x00000001) << 22;
17611
17612 return patched_inst;
17613}
17614
17615static inline bfd_vma
9239bbd3
CM		 17616create_instruction_vldmdb (int base_reg, int is_dp, int num_words,
17617 int first_reg)
a504d23a
LA		 17618{
17619 /* A8.8.332 VLDM (A8-922)
9239bbd3
CM		 17620 VLMD{MODE} Rn!, {} (Encoding T1 or T2). */
17621 bfd_vma patched_inst = (is_dp ? 0xed300b00 : 0xed300a00)
a504d23a 17622 | (base_reg << 16)
9239bbd3
CM		 17623 | (num_words & 0x000000ff)
17624 | (((unsigned)first_reg >>1 ) & 0x0000000f) << 12
a504d23a
LA		 17625 | (first_reg & 0x00000001) << 22;
17626
17627 return patched_inst;
17628}
17629
17630static inline bfd_vma
17631create_instruction_udf_w (int value)
17632{
17633 /* A8.8.247 UDF (A8-758)
17634 Undefined (Encoding T2). */
17635 bfd_vma patched_inst = 0xf7f0a000
17636 | (value & 0x00000fff)
17637 | (value & 0x000f0000) << 16;
17638
17639 return patched_inst;
17640}
17641
17642static inline bfd_vma
17643create_instruction_udf (int value)
17644{
17645 /* A8.8.247 UDF (A8-758)
17646 Undefined (Encoding T1). */
17647 bfd_vma patched_inst = 0xde00
17648 | (value & 0xff);
17649
17650 return patched_inst;
17651}
17652
17653/* Functions writing an instruction in memory, returning the next
17654 memory position to write to. */
17655
17656static inline bfd_byte *
17657push_thumb2_insn32 (struct elf32_arm_link_hash_table * htab,
17658 bfd * output_bfd, bfd_byte *pt, insn32 insn)
17659{
17660 put_thumb2_insn (htab, output_bfd, insn, pt);
17661 return pt + 4;
17662}
17663
17664static inline bfd_byte *
17665push_thumb2_insn16 (struct elf32_arm_link_hash_table * htab,
17666 bfd * output_bfd, bfd_byte *pt, insn32 insn)
17667{
17668 put_thumb_insn (htab, output_bfd, insn, pt);
17669 return pt + 2;
17670}
17671
17672/* Function filling up a region in memory with T1 and T2 UDFs taking
17673 care of alignment. */
17674
17675static bfd_byte *
17676stm32l4xx_fill_stub_udf (struct elf32_arm_link_hash_table * htab,
17677 bfd * output_bfd,
17678 const bfd_byte * const base_stub_contents,
17679 bfd_byte * const from_stub_contents,
17680 const bfd_byte * const end_stub_contents)
17681{
17682 bfd_byte *current_stub_contents = from_stub_contents;
17683
17684 /* Fill the remaining of the stub with deterministic contents : UDF
17685 instructions.
17686 Check if realignment is needed on modulo 4 frontier using T1, to
17687 further use T2. */
17688 if ((current_stub_contents < end_stub_contents)
17689 && !((current_stub_contents - base_stub_contents) % 2)
17690 && ((current_stub_contents - base_stub_contents) % 4))
17691 current_stub_contents =
17692 push_thumb2_insn16 (htab, output_bfd, current_stub_contents,
17693 create_instruction_udf (0));
17694
17695 for (; current_stub_contents < end_stub_contents;)
17696 current_stub_contents =
17697 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
17698 create_instruction_udf_w (0));
17699
17700 return current_stub_contents;
17701}
17702
17703/* Functions writing the stream of instructions equivalent to the
17704 derived sequence for ldmia, ldmdb, vldm respectively. */
17705
17706static void
17707stm32l4xx_create_replacing_stub_ldmia (struct elf32_arm_link_hash_table * htab,
17708 bfd * output_bfd,
17709 const insn32 initial_insn,
17710 const bfd_byte *const initial_insn_addr,
17711 bfd_byte *const base_stub_contents)
17712{
17713 int wback = (initial_insn & 0x00200000) >> 21;
17714 int ri, rn = (initial_insn & 0x000F0000) >> 16;
17715 int insn_all_registers = initial_insn & 0x0000ffff;
17716 int insn_low_registers, insn_high_registers;
17717 int usable_register_mask;
17718 int nb_registers = popcount (insn_all_registers);
17719 int restore_pc = (insn_all_registers & (1 << 15)) ? 1 : 0;
17720 int restore_rn = (insn_all_registers & (1 << rn)) ? 1 : 0;
17721 bfd_byte *current_stub_contents = base_stub_contents;
17722
17723 BFD_ASSERT (is_thumb2_ldmia (initial_insn));
17724
17725 /* In BFD_ARM_STM32L4XX_FIX_ALL mode we may have to deal with
17726 smaller than 8 registers load sequences that do not cause the
17727 hardware issue. */
17728 if (nb_registers <= 8)
17729 {
17730 /* UNTOUCHED : LDMIA Rn{!}, {R-all-register-list}. */
17731 current_stub_contents =
17732 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
17733 initial_insn);
17734
17735 /* B initial_insn_addr+4. */
17736 if (!restore_pc)
17737 current_stub_contents =
17738 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
17739 create_instruction_branch_absolute
82188b29
NC		 17740 (initial_insn_addr - current_stub_contents));
17741
a504d23a
LA		 17742
17743 /* Fill the remaining of the stub with deterministic contents. */
17744 current_stub_contents =
17745 stm32l4xx_fill_stub_udf (htab, output_bfd,
17746 base_stub_contents, current_stub_contents,
17747 base_stub_contents +
17748 STM32L4XX_ERRATUM_LDM_VENEER_SIZE);
17749
17750 return;
17751 }
17752
17753 /* - reg_list[13] == 0. */
17754 BFD_ASSERT ((insn_all_registers & (1 << 13))==0);
17755
17756 /* - reg_list[14] & reg_list[15] != 1. */
17757 BFD_ASSERT ((insn_all_registers & 0xC000) != 0xC000);
17758
17759 /* - if (wback==1) reg_list[rn] == 0. */
17760 BFD_ASSERT (!wback || !restore_rn);
17761
17762 /* - nb_registers > 8. */
17763 BFD_ASSERT (popcount (insn_all_registers) > 8);
17764
17765 /* At this point, LDMxx initial insn loads between 9 and 14 registers. */
17766
17767 /* In the following algorithm, we split this wide LDM using 2 LDM insns:
17768 - One with the 7 lowest registers (register mask 0x007F)
17769 This LDM will finally contain between 2 and 7 registers
17770 - One with the 7 highest registers (register mask 0xDF80)
17771 This ldm will finally contain between 2 and 7 registers. */
17772 insn_low_registers = insn_all_registers & 0x007F;
17773 insn_high_registers = insn_all_registers & 0xDF80;
17774
17775 /* A spare register may be needed during this veneer to temporarily
17776 handle the base register. This register will be restored with the
17777 last LDM operation.
17778 The usable register may be any general purpose register (that
17779 excludes PC, SP, LR : register mask is 0x1FFF). */
17780 usable_register_mask = 0x1FFF;
17781
17782 /* Generate the stub function. */
17783 if (wback)
17784 {
17785 /* LDMIA Rn!, {R-low-register-list} : (Encoding T2). */
17786 current_stub_contents =
17787 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
17788 create_instruction_ldmia
17789 (rn, /*wback=*/1, insn_low_registers));
17790
17791 /* LDMIA Rn!, {R-high-register-list} : (Encoding T2). */
17792 current_stub_contents =
17793 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
17794 create_instruction_ldmia
17795 (rn, /*wback=*/1, insn_high_registers));
17796 if (!restore_pc)
17797 {
17798 /* B initial_insn_addr+4. */
17799 current_stub_contents =
17800 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
17801 create_instruction_branch_absolute
82188b29 17802 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 17803 }
17804 }
17805 else /* if (!wback). */
17806 {
17807 ri = rn;
17808
17809 /* If Rn is not part of the high-register-list, move it there. */
17810 if (!(insn_high_registers & (1 << rn)))
17811 {
17812 /* Choose a Ri in the high-register-list that will be restored. */
17813 ri = ctz (insn_high_registers & usable_register_mask & ~(1 << rn));
17814
17815 /* MOV Ri, Rn. */
17816 current_stub_contents =
17817 push_thumb2_insn16 (htab, output_bfd, current_stub_contents,
17818 create_instruction_mov (ri, rn));
17819 }
17820
17821 /* LDMIA Ri!, {R-low-register-list} : (Encoding T2). */
17822 current_stub_contents =
17823 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
17824 create_instruction_ldmia
17825 (ri, /*wback=*/1, insn_low_registers));
17826
17827 /* LDMIA Ri, {R-high-register-list} : (Encoding T2). */
17828 current_stub_contents =
17829 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
17830 create_instruction_ldmia
17831 (ri, /*wback=*/0, insn_high_registers));
17832
17833 if (!restore_pc)
17834 {
17835 /* B initial_insn_addr+4. */
17836 current_stub_contents =
17837 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
17838 create_instruction_branch_absolute
82188b29 17839 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 17840 }
17841 }
17842
17843 /* Fill the remaining of the stub with deterministic contents. */
17844 current_stub_contents =
17845 stm32l4xx_fill_stub_udf (htab, output_bfd,
17846 base_stub_contents, current_stub_contents,
17847 base_stub_contents +
17848 STM32L4XX_ERRATUM_LDM_VENEER_SIZE);
17849}
17850
17851static void
17852stm32l4xx_create_replacing_stub_ldmdb (struct elf32_arm_link_hash_table * htab,
17853 bfd * output_bfd,
17854 const insn32 initial_insn,
17855 const bfd_byte *const initial_insn_addr,
17856 bfd_byte *const base_stub_contents)
17857{
17858 int wback = (initial_insn & 0x00200000) >> 21;
17859 int ri, rn = (initial_insn & 0x000f0000) >> 16;
17860 int insn_all_registers = initial_insn & 0x0000ffff;
17861 int insn_low_registers, insn_high_registers;
17862 int usable_register_mask;
17863 int restore_pc = (insn_all_registers & (1 << 15)) ? 1 : 0;
17864 int restore_rn = (insn_all_registers & (1 << rn)) ? 1 : 0;
17865 int nb_registers = popcount (insn_all_registers);
17866 bfd_byte *current_stub_contents = base_stub_contents;
17867
17868 BFD_ASSERT (is_thumb2_ldmdb (initial_insn));
17869
17870 /* In BFD_ARM_STM32L4XX_FIX_ALL mode we may have to deal with
17871 smaller than 8 registers load sequences that do not cause the
17872 hardware issue. */
17873 if (nb_registers <= 8)
17874 {
17875 /* UNTOUCHED : LDMIA Rn{!}, {R-all-register-list}. */
17876 current_stub_contents =
17877 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
17878 initial_insn);
17879
17880 /* B initial_insn_addr+4. */
17881 current_stub_contents =
17882 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
17883 create_instruction_branch_absolute
82188b29 17884 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 17885
17886 /* Fill the remaining of the stub with deterministic contents. */
17887 current_stub_contents =
17888 stm32l4xx_fill_stub_udf (htab, output_bfd,
17889 base_stub_contents, current_stub_contents,
17890 base_stub_contents +
17891 STM32L4XX_ERRATUM_LDM_VENEER_SIZE);
17892
17893 return;
17894 }
17895
17896 /* - reg_list[13] == 0. */
17897 BFD_ASSERT ((insn_all_registers & (1 << 13)) == 0);
17898
17899 /* - reg_list[14] & reg_list[15] != 1. */
17900 BFD_ASSERT ((insn_all_registers & 0xC000) != 0xC000);
17901
17902 /* - if (wback==1) reg_list[rn] == 0. */
17903 BFD_ASSERT (!wback || !restore_rn);
17904
17905 /* - nb_registers > 8. */
17906 BFD_ASSERT (popcount (insn_all_registers) > 8);
17907
17908 /* At this point, LDMxx initial insn loads between 9 and 14 registers. */
17909
17910 /* In the following algorithm, we split this wide LDM using 2 LDM insn:
17911 - One with the 7 lowest registers (register mask 0x007F)
17912 This LDM will finally contain between 2 and 7 registers
17913 - One with the 7 highest registers (register mask 0xDF80)
17914 This ldm will finally contain between 2 and 7 registers. */
17915 insn_low_registers = insn_all_registers & 0x007F;
17916 insn_high_registers = insn_all_registers & 0xDF80;
17917
17918 /* A spare register may be needed during this veneer to temporarily
17919 handle the base register. This register will be restored with
17920 the last LDM operation.
17921 The usable register may be any general purpose register (that excludes
17922 PC, SP, LR : register mask is 0x1FFF). */
17923 usable_register_mask = 0x1FFF;
17924
17925 /* Generate the stub function. */
17926 if (!wback && !restore_pc && !restore_rn)
17927 {
17928 /* Choose a Ri in the low-register-list that will be restored. */
17929 ri = ctz (insn_low_registers & usable_register_mask & ~(1 << rn));
17930
17931 /* MOV Ri, Rn. */
17932 current_stub_contents =
17933 push_thumb2_insn16 (htab, output_bfd, current_stub_contents,
17934 create_instruction_mov (ri, rn));
17935
17936 /* LDMDB Ri!, {R-high-register-list}. */
17937 current_stub_contents =
17938 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
17939 create_instruction_ldmdb
17940 (ri, /*wback=*/1, insn_high_registers));
17941
17942 /* LDMDB Ri, {R-low-register-list}. */
17943 current_stub_contents =
17944 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
17945 create_instruction_ldmdb
17946 (ri, /*wback=*/0, insn_low_registers));
17947
17948 /* B initial_insn_addr+4. */
17949 current_stub_contents =
17950 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
17951 create_instruction_branch_absolute
82188b29 17952 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 17953 }
17954 else if (wback && !restore_pc && !restore_rn)
17955 {
17956 /* LDMDB Rn!, {R-high-register-list}. */
17957 current_stub_contents =
17958 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
17959 create_instruction_ldmdb
17960 (rn, /*wback=*/1, insn_high_registers));
17961
17962 /* LDMDB Rn!, {R-low-register-list}. */
17963 current_stub_contents =
17964 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
17965 create_instruction_ldmdb
17966 (rn, /*wback=*/1, insn_low_registers));
17967
17968 /* B initial_insn_addr+4. */
17969 current_stub_contents =
17970 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
17971 create_instruction_branch_absolute
82188b29 17972 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 17973 }
17974 else if (!wback && restore_pc && !restore_rn)
17975 {
17976 /* Choose a Ri in the high-register-list that will be restored. */
17977 ri = ctz (insn_high_registers & usable_register_mask & ~(1 << rn));
17978
17979 /* SUB Ri, Rn, #(4*nb_registers). */
17980 current_stub_contents =
17981 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
17982 create_instruction_sub (ri, rn, (4 * nb_registers)));
17983
17984 /* LDMIA Ri!, {R-low-register-list}. */
17985 current_stub_contents =
17986 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
17987 create_instruction_ldmia
17988 (ri, /*wback=*/1, insn_low_registers));
17989
17990 /* LDMIA Ri, {R-high-register-list}. */
17991 current_stub_contents =
17992 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
17993 create_instruction_ldmia
17994 (ri, /*wback=*/0, insn_high_registers));
17995 }
17996 else if (wback && restore_pc && !restore_rn)
17997 {
17998 /* Choose a Ri in the high-register-list that will be restored. */
17999 ri = ctz (insn_high_registers & usable_register_mask & ~(1 << rn));
18000
18001 /* SUB Rn, Rn, #(4*nb_registers) */
18002 current_stub_contents =
18003 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18004 create_instruction_sub (rn, rn, (4 * nb_registers)));
18005
18006 /* MOV Ri, Rn. */
18007 current_stub_contents =
18008 push_thumb2_insn16 (htab, output_bfd, current_stub_contents,
18009 create_instruction_mov (ri, rn));
18010
18011 /* LDMIA Ri!, {R-low-register-list}. */
18012 current_stub_contents =
18013 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18014 create_instruction_ldmia
18015 (ri, /*wback=*/1, insn_low_registers));
18016
18017 /* LDMIA Ri, {R-high-register-list}. */
18018 current_stub_contents =
18019 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18020 create_instruction_ldmia
18021 (ri, /*wback=*/0, insn_high_registers));
18022 }
18023 else if (!wback && !restore_pc && restore_rn)
18024 {
18025 ri = rn;
18026 if (!(insn_low_registers & (1 << rn)))
18027 {
18028 /* Choose a Ri in the low-register-list that will be restored. */
18029 ri = ctz (insn_low_registers & usable_register_mask & ~(1 << rn));
18030
18031 /* MOV Ri, Rn. */
18032 current_stub_contents =
18033 push_thumb2_insn16 (htab, output_bfd, current_stub_contents,
18034 create_instruction_mov (ri, rn));
18035 }
18036
18037 /* LDMDB Ri!, {R-high-register-list}. */
18038 current_stub_contents =
18039 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18040 create_instruction_ldmdb
18041 (ri, /*wback=*/1, insn_high_registers));
18042
18043 /* LDMDB Ri, {R-low-register-list}. */
18044 current_stub_contents =
18045 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18046 create_instruction_ldmdb
18047 (ri, /*wback=*/0, insn_low_registers));
18048
18049 /* B initial_insn_addr+4. */
18050 current_stub_contents =
18051 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18052 create_instruction_branch_absolute
82188b29 18053 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 18054 }
18055 else if (!wback && restore_pc && restore_rn)
18056 {
18057 ri = rn;
18058 if (!(insn_high_registers & (1 << rn)))
18059 {
18060 /* Choose a Ri in the high-register-list that will be restored. */
18061 ri = ctz (insn_high_registers & usable_register_mask & ~(1 << rn));
18062 }
18063
18064 /* SUB Ri, Rn, #(4*nb_registers). */
18065 current_stub_contents =
18066 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18067 create_instruction_sub (ri, rn, (4 * nb_registers)));
18068
18069 /* LDMIA Ri!, {R-low-register-list}. */
18070 current_stub_contents =
18071 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18072 create_instruction_ldmia
18073 (ri, /*wback=*/1, insn_low_registers));
18074
18075 /* LDMIA Ri, {R-high-register-list}. */
18076 current_stub_contents =
18077 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18078 create_instruction_ldmia
18079 (ri, /*wback=*/0, insn_high_registers));
18080 }
18081 else if (wback && restore_rn)
18082 {
18083 /* The assembler should not have accepted to encode this. */
18084 BFD_ASSERT (0 && "Cannot patch an instruction that has an "
18085 "undefined behavior.\n");
18086 }
18087
18088 /* Fill the remaining of the stub with deterministic contents. */
18089 current_stub_contents =
18090 stm32l4xx_fill_stub_udf (htab, output_bfd,
18091 base_stub_contents, current_stub_contents,
18092 base_stub_contents +
18093 STM32L4XX_ERRATUM_LDM_VENEER_SIZE);
18094
18095}
18096
18097static void
18098stm32l4xx_create_replacing_stub_vldm (struct elf32_arm_link_hash_table * htab,
18099 bfd * output_bfd,
18100 const insn32 initial_insn,
18101 const bfd_byte *const initial_insn_addr,
18102 bfd_byte *const base_stub_contents)
18103{
9239bbd3 18104 int num_words = ((unsigned int) initial_insn << 24) >> 24;
a504d23a
LA		 18105 bfd_byte *current_stub_contents = base_stub_contents;
18106
18107 BFD_ASSERT (is_thumb2_vldm (initial_insn));
18108
18109 /* In BFD_ARM_STM32L4XX_FIX_ALL mode we may have to deal with
9239bbd3 18110 smaller than 8 words load sequences that do not cause the
a504d23a 18111 hardware issue. */
9239bbd3 18112 if (num_words <= 8)
a504d23a
LA		 18113 {
18114 /* Untouched instruction. */
18115 current_stub_contents =
18116 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18117 initial_insn);
18118
18119 /* B initial_insn_addr+4. */
18120 current_stub_contents =
18121 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18122 create_instruction_branch_absolute
82188b29 18123 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 18124 }
18125 else
18126 {
9239bbd3
CM		 18127 bfd_boolean is_dp = /* DP encoding. */
18128 (initial_insn & 0xfe100f00) == 0xec100b00;
a504d23a
LA		 18129 bfd_boolean is_ia_nobang = /* (IA without !). */
18130 (((initial_insn << 7) >> 28) & 0xd) == 0x4;
18131 bfd_boolean is_ia_bang = /* (IA with !) - includes VPOP. */
18132 (((initial_insn << 7) >> 28) & 0xd) == 0x5;
18133 bfd_boolean is_db_bang = /* (DB with !). */
18134 (((initial_insn << 7) >> 28) & 0xd) == 0x9;
9239bbd3 18135 int base_reg = ((unsigned int) initial_insn << 12) >> 28;
a504d23a 18136 /* d = UInt (Vd:D);. */
9239bbd3 18137 int first_reg = ((((unsigned int) initial_insn << 16) >> 28) << 1)
a504d23a
LA		 18138 | (((unsigned int)initial_insn << 9) >> 31);
18139
9239bbd3
CM		 18140 /* Compute the number of 8-words chunks needed to split. */
18141 int chunks = (num_words % 8) ? (num_words / 8 + 1) : (num_words / 8);
a504d23a
LA		 18142 int chunk;
18143
18144 /* The test coverage has been done assuming the following
18145 hypothesis that exactly one of the previous is_ predicates is
18146 true. */
9239bbd3
CM		 18147 BFD_ASSERT ( (is_ia_nobang ^ is_ia_bang ^ is_db_bang)
18148 && !(is_ia_nobang & is_ia_bang & is_db_bang));
a504d23a 18149
9239bbd3 18150 /* We treat the cutting of the words in one pass for all
a504d23a
LA		 18151 cases, then we emit the adjustments:
18152
18153 vldm rx, {...}
18154 -> vldm rx!, {8_words_or_less} for each needed 8_word
18155 -> sub rx, rx, #size (list)
18156
18157 vldm rx!, {...}
18158 -> vldm rx!, {8_words_or_less} for each needed 8_word
18159 This also handles vpop instruction (when rx is sp)
18160
18161 vldmd rx!, {...}
18162 -> vldmb rx!, {8_words_or_less} for each needed 8_word. */
9239bbd3 18163 for (chunk = 0; chunk < chunks; ++chunk)
a504d23a 18164 {
9239bbd3
CM		 18165 bfd_vma new_insn = 0;
18166
a504d23a
LA		 18167 if (is_ia_nobang || is_ia_bang)
18168 {
9239bbd3
CM		 18169 new_insn = create_instruction_vldmia
18170 (base_reg,
18171 is_dp,
18172 /*wback= . */1,
18173 chunks - (chunk + 1) ?
18174 8 : num_words - chunk * 8,
18175 first_reg + chunk * 8);
a504d23a
LA		 18176 }
18177 else if (is_db_bang)
18178 {
9239bbd3
CM		 18179 new_insn = create_instruction_vldmdb
18180 (base_reg,
18181 is_dp,
18182 chunks - (chunk + 1) ?
18183 8 : num_words - chunk * 8,
18184 first_reg + chunk * 8);
a504d23a 18185 }
9239bbd3
CM		 18186
18187 if (new_insn)
18188 current_stub_contents =
18189 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18190 new_insn);
a504d23a
LA		 18191 }
18192
18193 /* Only this case requires the base register compensation
18194 subtract. */
18195 if (is_ia_nobang)
18196 {
18197 current_stub_contents =
18198 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18199 create_instruction_sub
9239bbd3 18200 (base_reg, base_reg, 4*num_words));
a504d23a
LA		 18201 }
18202
18203 /* B initial_insn_addr+4. */
18204 current_stub_contents =
18205 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18206 create_instruction_branch_absolute
82188b29 18207 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 18208 }
18209
18210 /* Fill the remaining of the stub with deterministic contents. */
18211 current_stub_contents =
18212 stm32l4xx_fill_stub_udf (htab, output_bfd,
18213 base_stub_contents, current_stub_contents,
18214 base_stub_contents +
18215 STM32L4XX_ERRATUM_VLDM_VENEER_SIZE);
18216}
18217
18218static void
18219stm32l4xx_create_replacing_stub (struct elf32_arm_link_hash_table * htab,
18220 bfd * output_bfd,
18221 const insn32 wrong_insn,
18222 const bfd_byte *const wrong_insn_addr,
18223 bfd_byte *const stub_contents)
18224{
18225 if (is_thumb2_ldmia (wrong_insn))
18226 stm32l4xx_create_replacing_stub_ldmia (htab, output_bfd,
18227 wrong_insn, wrong_insn_addr,
18228 stub_contents);
18229 else if (is_thumb2_ldmdb (wrong_insn))
18230 stm32l4xx_create_replacing_stub_ldmdb (htab, output_bfd,
18231 wrong_insn, wrong_insn_addr,
18232 stub_contents);
18233 else if (is_thumb2_vldm (wrong_insn))
18234 stm32l4xx_create_replacing_stub_vldm (htab, output_bfd,
18235 wrong_insn, wrong_insn_addr,
18236 stub_contents);
18237}
18238
18239/* End of stm32l4xx work-around. */
18240
18241
491d01d3
YU		 18242static void
18243elf32_arm_add_relocation (bfd *output_bfd, struct bfd_link_info *info,
18244 asection *output_sec, Elf_Internal_Rela *rel)
18245{
18246 BFD_ASSERT (output_sec && rel);
18247 struct bfd_elf_section_reloc_data *output_reldata;
18248 struct elf32_arm_link_hash_table *htab;
18249 struct bfd_elf_section_data *oesd = elf_section_data (output_sec);
18250 Elf_Internal_Shdr *rel_hdr;
18251
18252
18253 if (oesd->rel.hdr)
18254 {
18255 rel_hdr = oesd->rel.hdr;
18256 output_reldata = &(oesd->rel);
18257 }
18258 else if (oesd->rela.hdr)
18259 {
18260 rel_hdr = oesd->rela.hdr;
18261 output_reldata = &(oesd->rela);
18262 }
18263 else
18264 {
18265 abort ();
18266 }
18267
18268 bfd_byte *erel = rel_hdr->contents;
18269 erel += output_reldata->count * rel_hdr->sh_entsize;
18270 htab = elf32_arm_hash_table (info);
18271 SWAP_RELOC_OUT (htab) (output_bfd, rel, erel);
18272 output_reldata->count++;
18273}
18274
e489d0ae
PB		 18275/* Do code byteswapping. Return FALSE afterwards so that the section is
18276 written out as normal. */
18277
18278static bfd_boolean
c7b8f16e 18279elf32_arm_write_section (bfd *output_bfd,
8029a119
NC		 18280 struct bfd_link_info *link_info,
18281 asection *sec,
e489d0ae
PB		 18282 bfd_byte *contents)
18283{
48229727 18284 unsigned int mapcount, errcount;
8e3de13a 18285 _arm_elf_section_data *arm_data;
c7b8f16e 18286 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (link_info);
e489d0ae 18287 elf32_arm_section_map *map;
c7b8f16e 18288 elf32_vfp11_erratum_list *errnode;
a504d23a 18289 elf32_stm32l4xx_erratum_list *stm32l4xx_errnode;
e489d0ae
PB		 18290 bfd_vma ptr;
18291 bfd_vma end;
c7b8f16e 18292 bfd_vma offset = sec->output_section->vma + sec->output_offset;
e489d0ae 18293 bfd_byte tmp;
48229727 18294 unsigned int i;
57e8b36a 18295
4dfe6ac6
NC		 18296 if (globals == NULL)
18297 return FALSE;
18298
8e3de13a
NC		 18299 /* If this section has not been allocated an _arm_elf_section_data
18300 structure then we cannot record anything. */
18301 arm_data = get_arm_elf_section_data (sec);
18302 if (arm_data == NULL)
18303 return FALSE;
18304
18305 mapcount = arm_data->mapcount;
18306 map = arm_data->map;
c7b8f16e
JB		 18307 errcount = arm_data->erratumcount;
18308
18309 if (errcount != 0)
18310 {
18311 unsigned int endianflip = bfd_big_endian (output_bfd) ? 3 : 0;
18312
18313 for (errnode = arm_data->erratumlist; errnode != 0;
99059e56
RM		 18314 errnode = errnode->next)
18315 {
18316 bfd_vma target = errnode->vma - offset;
18317
18318 switch (errnode->type)
18319 {
18320 case VFP11_ERRATUM_BRANCH_TO_ARM_VENEER:
18321 {
18322 bfd_vma branch_to_veneer;
18323 /* Original condition code of instruction, plus bit mask for
18324 ARM B instruction. */
18325 unsigned int insn = (errnode->u.b.vfp_insn & 0xf0000000)
18326 | 0x0a000000;
c7b8f16e
JB		 18327
18328 /* The instruction is before the label. */
91d6fa6a 18329 target -= 4;
c7b8f16e
JB		 18330
18331 /* Above offset included in -4 below. */
18332 branch_to_veneer = errnode->u.b.veneer->vma
99059e56 18333 - errnode->vma - 4;
c7b8f16e
JB		 18334
18335 if ((signed) branch_to_veneer < -(1 << 25)
18336 || (signed) branch_to_veneer >= (1 << 25))
18337 (*_bfd_error_handler) (_("%B: error: VFP11 veneer out of "
18338 "range"), output_bfd);
18339
99059e56
RM		 18340 insn |= (branch_to_veneer >> 2) & 0xffffff;
18341 contents[endianflip ^ target] = insn & 0xff;
18342 contents[endianflip ^ (target + 1)] = (insn >> 8) & 0xff;
18343 contents[endianflip ^ (target + 2)] = (insn >> 16) & 0xff;
18344 contents[endianflip ^ (target + 3)] = (insn >> 24) & 0xff;
18345 }
18346 break;
c7b8f16e
JB		 18347
18348 case VFP11_ERRATUM_ARM_VENEER:
99059e56
RM		 18349 {
18350 bfd_vma branch_from_veneer;
18351 unsigned int insn;
c7b8f16e 18352
99059e56
RM		 18353 /* Take size of veneer into account. */
18354 branch_from_veneer = errnode->u.v.branch->vma
18355 - errnode->vma - 12;
c7b8f16e
JB		 18356
18357 if ((signed) branch_from_veneer < -(1 << 25)
18358 || (signed) branch_from_veneer >= (1 << 25))
18359 (*_bfd_error_handler) (_("%B: error: VFP11 veneer out of "
18360 "range"), output_bfd);
18361
99059e56
RM		 18362 /* Original instruction. */
18363 insn = errnode->u.v.branch->u.b.vfp_insn;
18364 contents[endianflip ^ target] = insn & 0xff;
18365 contents[endianflip ^ (target + 1)] = (insn >> 8) & 0xff;
18366 contents[endianflip ^ (target + 2)] = (insn >> 16) & 0xff;
18367 contents[endianflip ^ (target + 3)] = (insn >> 24) & 0xff;
18368
18369 /* Branch back to insn after original insn. */
18370 insn = 0xea000000 | ((branch_from_veneer >> 2) & 0xffffff);
18371 contents[endianflip ^ (target + 4)] = insn & 0xff;
18372 contents[endianflip ^ (target + 5)] = (insn >> 8) & 0xff;
18373 contents[endianflip ^ (target + 6)] = (insn >> 16) & 0xff;
18374 contents[endianflip ^ (target + 7)] = (insn >> 24) & 0xff;
18375 }
18376 break;
c7b8f16e 18377
99059e56
RM		 18378 default:
18379 abort ();
18380 }
18381 }
c7b8f16e 18382 }
e489d0ae 18383
a504d23a
LA		 18384 if (arm_data->stm32l4xx_erratumcount != 0)
18385 {
18386 for (stm32l4xx_errnode = arm_data->stm32l4xx_erratumlist;
18387 stm32l4xx_errnode != 0;
18388 stm32l4xx_errnode = stm32l4xx_errnode->next)
18389 {
18390 bfd_vma target = stm32l4xx_errnode->vma - offset;
18391
18392 switch (stm32l4xx_errnode->type)
18393 {
18394 case STM32L4XX_ERRATUM_BRANCH_TO_VENEER:
18395 {
18396 unsigned int insn;
18397 bfd_vma branch_to_veneer =
18398 stm32l4xx_errnode->u.b.veneer->vma - stm32l4xx_errnode->vma;
18399
18400 if ((signed) branch_to_veneer < -(1 << 24)
18401 || (signed) branch_to_veneer >= (1 << 24))
18402 {
18403 bfd_vma out_of_range =
18404 ((signed) branch_to_veneer < -(1 << 24)) ?
18405 - branch_to_veneer - (1 << 24) :
18406 ((signed) branch_to_veneer >= (1 << 24)) ?
18407 branch_to_veneer - (1 << 24) : 0;
18408
18409 (*_bfd_error_handler)
18410 (_("%B(%#x): error: Cannot create STM32L4XX veneer. "
eee926f2 18411 "Jump out of range by %ld bytes. "
a504d23a
LA		 18412 "Cannot encode branch instruction. "),
18413 output_bfd,
eee926f2 18414 (long) (stm32l4xx_errnode->vma - 4),
a504d23a
LA		 18415 out_of_range);
18416 continue;
18417 }
18418
18419 insn = create_instruction_branch_absolute
82188b29 18420 (stm32l4xx_errnode->u.b.veneer->vma - stm32l4xx_errnode->vma);
a504d23a
LA		 18421
18422 /* The instruction is before the label. */
18423 target -= 4;
18424
18425 put_thumb2_insn (globals, output_bfd,
18426 (bfd_vma) insn, contents + target);
18427 }
18428 break;
18429
18430 case STM32L4XX_ERRATUM_VENEER:
18431 {
82188b29
NC		 18432 bfd_byte * veneer;
18433 bfd_byte * veneer_r;
a504d23a
LA		 18434 unsigned int insn;
18435
82188b29
NC		 18436 veneer = contents + target;
18437 veneer_r = veneer
18438 + stm32l4xx_errnode->u.b.veneer->vma
18439 - stm32l4xx_errnode->vma - 4;
a504d23a
LA		 18440
18441 if ((signed) (veneer_r - veneer -
18442 STM32L4XX_ERRATUM_VLDM_VENEER_SIZE >
18443 STM32L4XX_ERRATUM_LDM_VENEER_SIZE ?
18444 STM32L4XX_ERRATUM_VLDM_VENEER_SIZE :
18445 STM32L4XX_ERRATUM_LDM_VENEER_SIZE) < -(1 << 24)
18446 || (signed) (veneer_r - veneer) >= (1 << 24))
18447 {
18448 (*_bfd_error_handler) (_("%B: error: Cannot create STM32L4XX "
18449 "veneer."), output_bfd);
18450 continue;
18451 }
18452
18453 /* Original instruction. */
18454 insn = stm32l4xx_errnode->u.v.branch->u.b.insn;
18455
18456 stm32l4xx_create_replacing_stub
18457 (globals, output_bfd, insn, (void*)veneer_r, (void*)veneer);
18458 }
18459 break;
18460
18461 default:
18462 abort ();
18463 }
18464 }
18465 }
18466
2468f9c9
PB		 18467 if (arm_data->elf.this_hdr.sh_type == SHT_ARM_EXIDX)
18468 {
18469 arm_unwind_table_edit *edit_node
99059e56 18470 = arm_data->u.exidx.unwind_edit_list;
2468f9c9 18471 /* Now, sec->size is the size of the section we will write. The original
99059e56 18472 size (before we merged duplicate entries and inserted EXIDX_CANTUNWIND
2468f9c9
PB		 18473 markers) was sec->rawsize. (This isn't the case if we perform no
18474 edits, then rawsize will be zero and we should use size). */
21d799b5 18475 bfd_byte *edited_contents = (bfd_byte *) bfd_malloc (sec->size);
2468f9c9
PB		 18476 unsigned int input_size = sec->rawsize ? sec->rawsize : sec->size;
18477 unsigned int in_index, out_index;
18478 bfd_vma add_to_offsets = 0;
18479
18480 for (in_index = 0, out_index = 0; in_index * 8 < input_size || edit_node;)
99059e56 18481 {
2468f9c9
PB		 18482 if (edit_node)
18483 {
18484 unsigned int edit_index = edit_node->index;
b38cadfb 18485
2468f9c9 18486 if (in_index < edit_index && in_index * 8 < input_size)
99059e56 18487 {
2468f9c9
PB		 18488 copy_exidx_entry (output_bfd, edited_contents + out_index * 8,
18489 contents + in_index * 8, add_to_offsets);
18490 out_index++;
18491 in_index++;
18492 }
18493 else if (in_index == edit_index
18494 || (in_index * 8 >= input_size
18495 && edit_index == UINT_MAX))
99059e56 18496 {
2468f9c9
PB		 18497 switch (edit_node->type)
18498 {
18499 case DELETE_EXIDX_ENTRY:
18500 in_index++;
18501 add_to_offsets += 8;
18502 break;
b38cadfb 18503
2468f9c9
PB		 18504 case INSERT_EXIDX_CANTUNWIND_AT_END:
18505 {
99059e56 18506 asection *text_sec = edit_node->linked_section;
2468f9c9
PB		 18507 bfd_vma text_offset = text_sec->output_section->vma
18508 + text_sec->output_offset
18509 + text_sec->size;
18510 bfd_vma exidx_offset = offset + out_index * 8;
99059e56 18511 unsigned long prel31_offset;
2468f9c9
PB		 18512
18513 /* Note: this is meant to be equivalent to an
18514 R_ARM_PREL31 relocation. These synthetic
18515 EXIDX_CANTUNWIND markers are not relocated by the
18516 usual BFD method. */
18517 prel31_offset = (text_offset - exidx_offset)
18518 & 0x7ffffffful;
491d01d3
YU		 18519 if (bfd_link_relocatable (link_info))
18520 {
18521 /* Here relocation for new EXIDX_CANTUNWIND is
18522 created, so there is no need to
18523 adjust offset by hand. */
18524 prel31_offset = text_sec->output_offset
18525 + text_sec->size;
18526
18527 /* New relocation entity. */
18528 asection *text_out = text_sec->output_section;
18529 Elf_Internal_Rela rel;
18530 rel.r_addend = 0;
18531 rel.r_offset = exidx_offset;
18532 rel.r_info = ELF32_R_INFO (text_out->target_index,
18533 R_ARM_PREL31);
18534
18535 elf32_arm_add_relocation (output_bfd, link_info,
18536 sec->output_section,
18537 &rel);
18538 }
2468f9c9
PB		 18539
18540 /* First address we can't unwind. */
18541 bfd_put_32 (output_bfd, prel31_offset,
18542 &edited_contents[out_index * 8]);
18543
18544 /* Code for EXIDX_CANTUNWIND. */
18545 bfd_put_32 (output_bfd, 0x1,
18546 &edited_contents[out_index * 8 + 4]);
18547
18548 out_index++;
18549 add_to_offsets -= 8;
18550 }
18551 break;
18552 }
b38cadfb 18553
2468f9c9
PB		 18554 edit_node = edit_node->next;
18555 }
18556 }
18557 else
18558 {
18559 /* No more edits, copy remaining entries verbatim. */
18560 copy_exidx_entry (output_bfd, edited_contents + out_index * 8,
18561 contents + in_index * 8, add_to_offsets);
18562 out_index++;
18563 in_index++;
18564 }
18565 }
18566
18567 if (!(sec->flags & SEC_EXCLUDE) && !(sec->flags & SEC_NEVER_LOAD))
18568 bfd_set_section_contents (output_bfd, sec->output_section,
18569 edited_contents,
18570 (file_ptr) sec->output_offset, sec->size);
18571
18572 return TRUE;
18573 }
18574
48229727
JB		 18575 /* Fix code to point to Cortex-A8 erratum stubs. */
18576 if (globals->fix_cortex_a8)
18577 {
18578 struct a8_branch_to_stub_data data;
18579
18580 data.writing_section = sec;
18581 data.contents = contents;
18582
a504d23a
LA		 18583 bfd_hash_traverse (& globals->stub_hash_table, make_branch_to_a8_stub,
18584 & data);
48229727
JB		 18585 }
18586
e489d0ae
PB		 18587 if (mapcount == 0)
18588 return FALSE;
18589
c7b8f16e 18590 if (globals->byteswap_code)
e489d0ae 18591 {
c7b8f16e 18592 qsort (map, mapcount, sizeof (* map), elf32_arm_compare_mapping);
57e8b36a 18593
c7b8f16e
JB		 18594 ptr = map[0].vma;
18595 for (i = 0; i < mapcount; i++)
99059e56
RM		 18596 {
18597 if (i == mapcount - 1)
c7b8f16e 18598 end = sec->size;
99059e56
RM		 18599 else
18600 end = map[i + 1].vma;
e489d0ae 18601
99059e56 18602 switch (map[i].type)
e489d0ae 18603 {
c7b8f16e
JB		 18604 case 'a':
18605 /* Byte swap code words. */
18606 while (ptr + 3 < end)
99059e56
RM		 18607 {
18608 tmp = contents[ptr];
18609 contents[ptr] = contents[ptr + 3];
18610 contents[ptr + 3] = tmp;
18611 tmp = contents[ptr + 1];
18612 contents[ptr + 1] = contents[ptr + 2];
18613 contents[ptr + 2] = tmp;
18614 ptr += 4;
18615 }
c7b8f16e 18616 break;
e489d0ae 18617
c7b8f16e
JB		 18618 case 't':
18619 /* Byte swap code halfwords. */
18620 while (ptr + 1 < end)
99059e56
RM		 18621 {
18622 tmp = contents[ptr];
18623 contents[ptr] = contents[ptr + 1];
18624 contents[ptr + 1] = tmp;
18625 ptr += 2;
18626 }
c7b8f16e
JB		 18627 break;
18628
18629 case 'd':
18630 /* Leave data alone. */
18631 break;
18632 }
99059e56
RM		 18633 ptr = end;
18634 }
e489d0ae 18635 }
8e3de13a 18636
93204d3a 18637 free (map);
47b2e99c 18638 arm_data->mapcount = -1;
c7b8f16e 18639 arm_data->mapsize = 0;
8e3de13a 18640 arm_data->map = NULL;
8e3de13a 18641
e489d0ae
PB		 18642 return FALSE;
18643}
18644
0beaef2b
PB		 18645/* Mangle thumb function symbols as we read them in. */
18646
8384fb8f 18647static bfd_boolean
0beaef2b
PB		 18648elf32_arm_swap_symbol_in (bfd * abfd,
18649 const void *psrc,
18650 const void *pshn,
18651 Elf_Internal_Sym *dst)
18652{
4ba2ef8f
TP		 18653 Elf_Internal_Shdr *symtab_hdr;
18654 const char *name = NULL;
18655
8384fb8f
AM		 18656 if (!bfd_elf32_swap_symbol_in (abfd, psrc, pshn, dst))
18657 return FALSE;
39d911fc 18658 dst->st_target_internal = 0;
0beaef2b
PB		 18659
18660 /* New EABI objects mark thumb function symbols by setting the low bit of
35fc36a8 18661 the address. */
63e1a0fc
PB		 18662 if (ELF_ST_TYPE (dst->st_info) == STT_FUNC
18663 || ELF_ST_TYPE (dst->st_info) == STT_GNU_IFUNC)
0beaef2b 18664 {
63e1a0fc
PB		 18665 if (dst->st_value & 1)
18666 {
18667 dst->st_value &= ~(bfd_vma) 1;
39d911fc
TP		 18668 ARM_SET_SYM_BRANCH_TYPE (dst->st_target_internal,
18669 ST_BRANCH_TO_THUMB);
63e1a0fc
PB		 18670 }
18671 else
39d911fc 18672 ARM_SET_SYM_BRANCH_TYPE (dst->st_target_internal, ST_BRANCH_TO_ARM);
35fc36a8
RS		 18673 }
18674 else if (ELF_ST_TYPE (dst->st_info) == STT_ARM_TFUNC)
18675 {
18676 dst->st_info = ELF_ST_INFO (ELF_ST_BIND (dst->st_info), STT_FUNC);
39d911fc 18677 ARM_SET_SYM_BRANCH_TYPE (dst->st_target_internal, ST_BRANCH_TO_THUMB);
0beaef2b 18678 }
35fc36a8 18679 else if (ELF_ST_TYPE (dst->st_info) == STT_SECTION)
39d911fc 18680 ARM_SET_SYM_BRANCH_TYPE (dst->st_target_internal, ST_BRANCH_LONG);
35fc36a8 18681 else
39d911fc 18682 ARM_SET_SYM_BRANCH_TYPE (dst->st_target_internal, ST_BRANCH_UNKNOWN);
35fc36a8 18683
4ba2ef8f
TP		 18684 /* Mark CMSE special symbols. */
18685 symtab_hdr = & elf_symtab_hdr (abfd);
18686 if (symtab_hdr->sh_size)
18687 name = bfd_elf_sym_name (abfd, symtab_hdr, dst, NULL);
18688 if (name && CONST_STRNEQ (name, CMSE_PREFIX))
18689 ARM_SET_SYM_CMSE_SPCL (dst->st_target_internal);
18690
8384fb8f 18691 return TRUE;
0beaef2b
PB		 18692}
18693
18694
18695/* Mangle thumb function symbols as we write them out. */
18696
18697static void
18698elf32_arm_swap_symbol_out (bfd *abfd,
18699 const Elf_Internal_Sym *src,
18700 void *cdst,
18701 void *shndx)
18702{
18703 Elf_Internal_Sym newsym;
18704
18705 /* We convert STT_ARM_TFUNC symbols into STT_FUNC with the low bit
18706 of the address set, as per the new EABI. We do this unconditionally
18707 because objcopy does not set the elf header flags until after
18708 it writes out the symbol table. */
39d911fc 18709 if (ARM_GET_SYM_BRANCH_TYPE (src->st_target_internal) == ST_BRANCH_TO_THUMB)
0beaef2b
PB		 18710 {
18711 newsym = *src;
34e77a92
RS		 18712 if (ELF_ST_TYPE (src->st_info) != STT_GNU_IFUNC)
18713 newsym.st_info = ELF_ST_INFO (ELF_ST_BIND (src->st_info), STT_FUNC);
0fa3dcad 18714 if (newsym.st_shndx != SHN_UNDEF)
99059e56
RM		 18715 {
18716 /* Do this only for defined symbols. At link type, the static
18717 linker will simulate the work of dynamic linker of resolving
18718 symbols and will carry over the thumbness of found symbols to
18719 the output symbol table. It's not clear how it happens, but
18720 the thumbness of undefined symbols can well be different at
18721 runtime, and writing '1' for them will be confusing for users
18722 and possibly for dynamic linker itself.
18723 */
18724 newsym.st_value |= 1;
18725 }
906e58ca 18726
0beaef2b
PB		 18727 src = &newsym;
18728 }
18729 bfd_elf32_swap_symbol_out (abfd, src, cdst, shndx);
18730}
18731
b294bdf8
MM		 18732/* Add the PT_ARM_EXIDX program header. */
18733
18734static bfd_boolean
906e58ca 18735elf32_arm_modify_segment_map (bfd *abfd,
b294bdf8
MM		 18736 struct bfd_link_info *info ATTRIBUTE_UNUSED)
18737{
18738 struct elf_segment_map *m;
18739 asection *sec;
18740
18741 sec = bfd_get_section_by_name (abfd, ".ARM.exidx");
18742 if (sec != NULL && (sec->flags & SEC_LOAD) != 0)
18743 {
18744 /* If there is already a PT_ARM_EXIDX header, then we do not
18745 want to add another one. This situation arises when running
18746 "strip"; the input binary already has the header. */
12bd6957 18747 m = elf_seg_map (abfd);
b294bdf8
MM		 18748 while (m && m->p_type != PT_ARM_EXIDX)
18749 m = m->next;
18750 if (!m)
18751 {
21d799b5 18752 m = (struct elf_segment_map *)
99059e56 18753 bfd_zalloc (abfd, sizeof (struct elf_segment_map));
b294bdf8
MM		 18754 if (m == NULL)
18755 return FALSE;
18756 m->p_type = PT_ARM_EXIDX;
18757 m->count = 1;
18758 m->sections[0] = sec;
18759
12bd6957
AM		 18760 m->next = elf_seg_map (abfd);
18761 elf_seg_map (abfd) = m;
b294bdf8
MM		 18762 }
18763 }
18764
18765 return TRUE;
18766}
18767
18768/* We may add a PT_ARM_EXIDX program header. */
18769
18770static int
a6b96beb
AM		 18771elf32_arm_additional_program_headers (bfd *abfd,
18772 struct bfd_link_info *info ATTRIBUTE_UNUSED)
b294bdf8
MM		 18773{
18774 asection *sec;
18775
18776 sec = bfd_get_section_by_name (abfd, ".ARM.exidx");
18777 if (sec != NULL && (sec->flags & SEC_LOAD) != 0)
18778 return 1;
18779 else
18780 return 0;
18781}
18782
34e77a92
RS		 18783/* Hook called by the linker routine which adds symbols from an object
18784 file. */
18785
18786static bfd_boolean
18787elf32_arm_add_symbol_hook (bfd *abfd, struct bfd_link_info *info,
18788 Elf_Internal_Sym *sym, const char **namep,
18789 flagword *flagsp, asection **secp, bfd_vma *valp)
18790{
a43942db 18791 if (ELF_ST_TYPE (sym->st_info) == STT_GNU_IFUNC
f1885d1e
AM		 18792 && (abfd->flags & DYNAMIC) == 0
18793 && bfd_get_flavour (info->output_bfd) == bfd_target_elf_flavour)
a43942db 18794 elf_tdata (info->output_bfd)->has_gnu_symbols |= elf_gnu_symbol_ifunc;
34e77a92 18795
c792917c
NC		 18796 if (elf32_arm_hash_table (info) == NULL)
18797 return FALSE;
18798
34e77a92
RS		 18799 if (elf32_arm_hash_table (info)->vxworks_p
18800 && !elf_vxworks_add_symbol_hook (abfd, info, sym, namep,
18801 flagsp, secp, valp))
18802 return FALSE;
18803
18804 return TRUE;
18805}
18806
0beaef2b 18807/* We use this to override swap_symbol_in and swap_symbol_out. */
906e58ca
NC		 18808const struct elf_size_info elf32_arm_size_info =
18809{
0beaef2b
PB		 18810 sizeof (Elf32_External_Ehdr),
18811 sizeof (Elf32_External_Phdr),
18812 sizeof (Elf32_External_Shdr),
18813 sizeof (Elf32_External_Rel),
18814 sizeof (Elf32_External_Rela),
18815 sizeof (Elf32_External_Sym),
18816 sizeof (Elf32_External_Dyn),
18817 sizeof (Elf_External_Note),
18818 4,
18819 1,
18820 32, 2,
18821 ELFCLASS32, EV_CURRENT,
18822 bfd_elf32_write_out_phdrs,
18823 bfd_elf32_write_shdrs_and_ehdr,
1489a3a0 18824 bfd_elf32_checksum_contents,
0beaef2b
PB		 18825 bfd_elf32_write_relocs,
18826 elf32_arm_swap_symbol_in,
18827 elf32_arm_swap_symbol_out,
18828 bfd_elf32_slurp_reloc_table,
18829 bfd_elf32_slurp_symbol_table,
18830 bfd_elf32_swap_dyn_in,
18831 bfd_elf32_swap_dyn_out,
18832 bfd_elf32_swap_reloc_in,
18833 bfd_elf32_swap_reloc_out,
18834 bfd_elf32_swap_reloca_in,
18835 bfd_elf32_swap_reloca_out
18836};
18837
685e70ae
VK		 18838static bfd_vma
18839read_code32 (const bfd *abfd, const bfd_byte *addr)
18840{
18841 /* V7 BE8 code is always little endian. */
18842 if ((elf_elfheader (abfd)->e_flags & EF_ARM_BE8) != 0)
18843 return bfd_getl32 (addr);
18844
18845 return bfd_get_32 (abfd, addr);
18846}
18847
18848static bfd_vma
18849read_code16 (const bfd *abfd, const bfd_byte *addr)
18850{
18851 /* V7 BE8 code is always little endian. */
18852 if ((elf_elfheader (abfd)->e_flags & EF_ARM_BE8) != 0)
18853 return bfd_getl16 (addr);
18854
18855 return bfd_get_16 (abfd, addr);
18856}
18857
6a631e86
YG		 18858/* Return size of plt0 entry starting at ADDR
18859 or (bfd_vma) -1 if size can not be determined. */
18860
18861static bfd_vma
18862elf32_arm_plt0_size (const bfd *abfd, const bfd_byte *addr)
18863{
18864 bfd_vma first_word;
18865 bfd_vma plt0_size;
18866
685e70ae 18867 first_word = read_code32 (abfd, addr);
6a631e86
YG		 18868
18869 if (first_word == elf32_arm_plt0_entry[0])
18870 plt0_size = 4 * ARRAY_SIZE (elf32_arm_plt0_entry);
18871 else if (first_word == elf32_thumb2_plt0_entry[0])
18872 plt0_size = 4 * ARRAY_SIZE (elf32_thumb2_plt0_entry);
18873 else
18874 /* We don't yet handle this PLT format. */
18875 return (bfd_vma) -1;
18876
18877 return plt0_size;
18878}
18879
18880/* Return size of plt entry starting at offset OFFSET
18881 of plt section located at address START
18882 or (bfd_vma) -1 if size can not be determined. */
18883
18884static bfd_vma
18885elf32_arm_plt_size (const bfd *abfd, const bfd_byte *start, bfd_vma offset)
18886{
18887 bfd_vma first_insn;
18888 bfd_vma plt_size = 0;
18889 const bfd_byte *addr = start + offset;
18890
18891 /* PLT entry size if fixed on Thumb-only platforms. */
685e70ae 18892 if (read_code32 (abfd, start) == elf32_thumb2_plt0_entry[0])
6a631e86
YG		 18893 return 4 * ARRAY_SIZE (elf32_thumb2_plt_entry);
18894
18895 /* Respect Thumb stub if necessary. */
685e70ae 18896 if (read_code16 (abfd, addr) == elf32_arm_plt_thumb_stub[0])
6a631e86
YG		 18897 {
18898 plt_size += 2 * ARRAY_SIZE(elf32_arm_plt_thumb_stub);
18899 }
18900
18901 /* Strip immediate from first add. */
685e70ae 18902 first_insn = read_code32 (abfd, addr + plt_size) & 0xffffff00;
6a631e86
YG		 18903
18904#ifdef FOUR_WORD_PLT
18905 if (first_insn == elf32_arm_plt_entry[0])
18906 plt_size += 4 * ARRAY_SIZE (elf32_arm_plt_entry);
18907#else
18908 if (first_insn == elf32_arm_plt_entry_long[0])
18909 plt_size += 4 * ARRAY_SIZE (elf32_arm_plt_entry_long);
18910 else if (first_insn == elf32_arm_plt_entry_short[0])
18911 plt_size += 4 * ARRAY_SIZE (elf32_arm_plt_entry_short);
18912#endif
18913 else
18914 /* We don't yet handle this PLT format. */
18915 return (bfd_vma) -1;
18916
18917 return plt_size;
18918}
18919
18920/* Implementation is shamelessly borrowed from _bfd_elf_get_synthetic_symtab. */
18921
18922static long
18923elf32_arm_get_synthetic_symtab (bfd *abfd,
18924 long symcount ATTRIBUTE_UNUSED,
18925 asymbol **syms ATTRIBUTE_UNUSED,
18926 long dynsymcount,
18927 asymbol **dynsyms,
18928 asymbol **ret)
18929{
18930 asection *relplt;
18931 asymbol *s;
18932 arelent *p;
18933 long count, i, n;
18934 size_t size;
18935 Elf_Internal_Shdr *hdr;
18936 char *names;
18937 asection *plt;
18938 bfd_vma offset;
18939 bfd_byte *data;
18940
18941 *ret = NULL;
18942
18943 if ((abfd->flags & (DYNAMIC | EXEC_P)) == 0)
18944 return 0;
18945
18946 if (dynsymcount <= 0)
18947 return 0;
18948
18949 relplt = bfd_get_section_by_name (abfd, ".rel.plt");
18950 if (relplt == NULL)
18951 return 0;
18952
18953 hdr = &elf_section_data (relplt)->this_hdr;
18954 if (hdr->sh_link != elf_dynsymtab (abfd)
18955 || (hdr->sh_type != SHT_REL && hdr->sh_type != SHT_RELA))
18956 return 0;
18957
18958 plt = bfd_get_section_by_name (abfd, ".plt");
18959 if (plt == NULL)
18960 return 0;
18961
18962 if (!elf32_arm_size_info.slurp_reloc_table (abfd, relplt, dynsyms, TRUE))
18963 return -1;
18964
18965 data = plt->contents;
18966 if (data == NULL)
18967 {
18968 if (!bfd_get_full_section_contents(abfd, (asection *) plt, &data) || data == NULL)
18969 return -1;
18970 bfd_cache_section_contents((asection *) plt, data);
18971 }
18972
18973 count = relplt->size / hdr->sh_entsize;
18974 size = count * sizeof (asymbol);
18975 p = relplt->relocation;
18976 for (i = 0; i < count; i++, p += elf32_arm_size_info.int_rels_per_ext_rel)
18977 {
18978 size += strlen ((*p->sym_ptr_ptr)->name) + sizeof ("@plt");
18979 if (p->addend != 0)
18980 size += sizeof ("+0x") - 1 + 8;
18981 }
18982
18983 s = *ret = (asymbol *) bfd_malloc (size);
18984 if (s == NULL)
18985 return -1;
18986
18987 offset = elf32_arm_plt0_size (abfd, data);
18988 if (offset == (bfd_vma) -1)
18989 return -1;
18990
18991 names = (char *) (s + count);
18992 p = relplt->relocation;
18993 n = 0;
18994 for (i = 0; i < count; i++, p += elf32_arm_size_info.int_rels_per_ext_rel)
18995 {
18996 size_t len;
18997
18998 bfd_vma plt_size = elf32_arm_plt_size (abfd, data, offset);
18999 if (plt_size == (bfd_vma) -1)
19000 break;
19001
19002 *s = **p->sym_ptr_ptr;
19003 /* Undefined syms won't have BSF_LOCAL or BSF_GLOBAL set. Since
19004 we are defining a symbol, ensure one of them is set. */
19005 if ((s->flags & BSF_LOCAL) == 0)
19006 s->flags |= BSF_GLOBAL;
19007 s->flags |= BSF_SYNTHETIC;
19008 s->section = plt;
19009 s->value = offset;
19010 s->name = names;
19011 s->udata.p = NULL;
19012 len = strlen ((*p->sym_ptr_ptr)->name);
19013 memcpy (names, (*p->sym_ptr_ptr)->name, len);
19014 names += len;
19015 if (p->addend != 0)
19016 {
19017 char buf[30], *a;
19018
19019 memcpy (names, "+0x", sizeof ("+0x") - 1);
19020 names += sizeof ("+0x") - 1;
19021 bfd_sprintf_vma (abfd, buf, p->addend);
19022 for (a = buf; *a == '0'; ++a)
19023 ;
19024 len = strlen (a);
19025 memcpy (names, a, len);
19026 names += len;
19027 }
19028 memcpy (names, "@plt", sizeof ("@plt"));
19029 names += sizeof ("@plt");
19030 ++s, ++n;
19031 offset += plt_size;
19032 }
19033
19034 return n;
19035}
19036
ac4c9b04
MG		 19037static bfd_boolean
19038elf32_arm_section_flags (flagword *flags, const Elf_Internal_Shdr * hdr)
19039{
f0728ee3
AV		 19040 if (hdr->sh_flags & SHF_ARM_PURECODE)
19041 *flags |= SEC_ELF_PURECODE;
ac4c9b04
MG		 19042 return TRUE;
19043}
19044
19045static flagword
19046elf32_arm_lookup_section_flags (char *flag_name)
19047{
f0728ee3
AV		 19048 if (!strcmp (flag_name, "SHF_ARM_PURECODE"))
19049 return SHF_ARM_PURECODE;
ac4c9b04
MG		 19050
19051 return SEC_NO_FLAGS;
19052}
19053
491d01d3
YU		 19054static unsigned int
19055elf32_arm_count_additional_relocs (asection *sec)
19056{
19057 struct _arm_elf_section_data *arm_data;
19058 arm_data = get_arm_elf_section_data (sec);
6342be70 19059 return arm_data == NULL ? 0 : arm_data->additional_reloc_count;
491d01d3
YU		 19060}
19061
5522f910
NC		 19062/* Called to set the sh_flags, sh_link and sh_info fields of OSECTION which
19063 has a type >= SHT_LOOS. Returns TRUE if these fields were initialised
19064 FALSE otherwise. ISECTION is the best guess matching section from the
19065 input bfd IBFD, but it might be NULL. */
19066
19067static bfd_boolean
19068elf32_arm_copy_special_section_fields (const bfd *ibfd ATTRIBUTE_UNUSED,
19069 bfd *obfd ATTRIBUTE_UNUSED,
19070 const Elf_Internal_Shdr *isection ATTRIBUTE_UNUSED,
19071 Elf_Internal_Shdr *osection)
19072{
19073 switch (osection->sh_type)
19074 {
19075 case SHT_ARM_EXIDX:
19076 {
19077 Elf_Internal_Shdr **oheaders = elf_elfsections (obfd);
19078 Elf_Internal_Shdr **iheaders = elf_elfsections (ibfd);
19079 unsigned i = 0;
19080
19081 osection->sh_flags = SHF_ALLOC | SHF_LINK_ORDER;
19082 osection->sh_info = 0;
19083
19084 /* The sh_link field must be set to the text section associated with
19085 this index section. Unfortunately the ARM EHABI does not specify
19086 exactly how to determine this association. Our caller does try
19087 to match up OSECTION with its corresponding input section however
19088 so that is a good first guess. */
19089 if (isection != NULL
19090 && osection->bfd_section != NULL
19091 && isection->bfd_section != NULL
19092 && isection->bfd_section->output_section != NULL
19093 && isection->bfd_section->output_section == osection->bfd_section
19094 && iheaders != NULL
19095 && isection->sh_link > 0
19096 && isection->sh_link < elf_numsections (ibfd)
19097 && iheaders[isection->sh_link]->bfd_section != NULL
19098 && iheaders[isection->sh_link]->bfd_section->output_section != NULL
19099 )
19100 {
19101 for (i = elf_numsections (obfd); i-- > 0;)
19102 if (oheaders[i]->bfd_section
19103 == iheaders[isection->sh_link]->bfd_section->output_section)
19104 break;
19105 }
19106
19107 if (i == 0)
19108 {
19109 /* Failing that we have to find a matching section ourselves. If
19110 we had the output section name available we could compare that
19111 with input section names. Unfortunately we don't. So instead
19112 we use a simple heuristic and look for the nearest executable
19113 section before this one. */
19114 for (i = elf_numsections (obfd); i-- > 0;)
19115 if (oheaders[i] == osection)
19116 break;
19117 if (i == 0)
19118 break;
19119
19120 while (i-- > 0)
19121 if (oheaders[i]->sh_type == SHT_PROGBITS
19122 && (oheaders[i]->sh_flags & (SHF_ALLOC | SHF_EXECINSTR))
19123 == (SHF_ALLOC | SHF_EXECINSTR))
19124 break;
19125 }
19126
19127 if (i)
19128 {
19129 osection->sh_link = i;
19130 /* If the text section was part of a group
19131 then the index section should be too. */
19132 if (oheaders[i]->sh_flags & SHF_GROUP)
19133 osection->sh_flags |= SHF_GROUP;
19134 return TRUE;
19135 }
19136 }
19137 break;
19138
19139 case SHT_ARM_PREEMPTMAP:
19140 osection->sh_flags = SHF_ALLOC;
19141 break;
19142
19143 case SHT_ARM_ATTRIBUTES:
19144 case SHT_ARM_DEBUGOVERLAY:
19145 case SHT_ARM_OVERLAYSECTION:
19146 default:
19147 break;
19148 }
19149
19150 return FALSE;
19151}
19152
d691934d
NC		 19153/* Returns TRUE if NAME is an ARM mapping symbol.
19154 Traditionally the symbols $a, $d and $t have been used.
19155 The ARM ELF standard also defines $x (for A64 code). It also allows a
19156 period initiated suffix to be added to the symbol: "$[adtx]\.[:sym_char]+".
19157 Other tools might also produce $b (Thumb BL), $f, $p, $m and $v, but we do
19158 not support them here. $t.x indicates the start of ThumbEE instructions. */
19159
19160static bfd_boolean
19161is_arm_mapping_symbol (const char * name)
19162{
19163 return name != NULL /* Paranoia. */
19164 && name[0] == '$' /* Note: if objcopy --prefix-symbols has been used then
19165 the mapping symbols could have acquired a prefix.
19166 We do not support this here, since such symbols no
19167 longer conform to the ARM ELF ABI. */
19168 && (name[1] == 'a' || name[1] == 'd' || name[1] == 't' || name[1] == 'x')
19169 && (name[2] == 0 || name[2] == '.');
19170 /* FIXME: Strictly speaking the symbol is only a valid mapping symbol if
19171 any characters that follow the period are legal characters for the body
19172 of a symbol's name. For now we just assume that this is the case. */
19173}
19174
fca2a38f
NC		 19175/* Make sure that mapping symbols in object files are not removed via the
19176 "strip --strip-unneeded" tool. These symbols are needed in order to
19177 correctly generate interworking veneers, and for byte swapping code
19178 regions. Once an object file has been linked, it is safe to remove the
19179 symbols as they will no longer be needed. */
19180
19181static void
19182elf32_arm_backend_symbol_processing (bfd *abfd, asymbol *sym)
19183{
19184 if (((abfd->flags & (EXEC_P | DYNAMIC)) == 0)
fca2a38f 19185 && sym->section != bfd_abs_section_ptr
d691934d 19186 && is_arm_mapping_symbol (sym->name))
fca2a38f
NC		 19187 sym->flags |= BSF_KEEP;
19188}
19189
5522f910
NC		 19190#undef elf_backend_copy_special_section_fields
19191#define elf_backend_copy_special_section_fields elf32_arm_copy_special_section_fields
19192
252b5132 19193#define ELF_ARCH bfd_arch_arm
ae95ffa6 19194#define ELF_TARGET_ID ARM_ELF_DATA
252b5132 19195#define ELF_MACHINE_CODE EM_ARM
d0facd1b
NC		 19196#ifdef __QNXTARGET__
19197#define ELF_MAXPAGESIZE 0x1000
19198#else
7572ca89 19199#define ELF_MAXPAGESIZE 0x10000
d0facd1b 19200#endif
b1342370 19201#define ELF_MINPAGESIZE 0x1000
24718e3b 19202#define ELF_COMMONPAGESIZE 0x1000
252b5132 19203
ba93b8ac
DJ		 19204#define bfd_elf32_mkobject elf32_arm_mkobject
19205
99e4ae17
AJ		 19206#define bfd_elf32_bfd_copy_private_bfd_data elf32_arm_copy_private_bfd_data
19207#define bfd_elf32_bfd_merge_private_bfd_data elf32_arm_merge_private_bfd_data
252b5132
RH		 19208#define bfd_elf32_bfd_set_private_flags elf32_arm_set_private_flags
19209#define bfd_elf32_bfd_print_private_bfd_data elf32_arm_print_private_bfd_data
19210#define bfd_elf32_bfd_link_hash_table_create elf32_arm_link_hash_table_create
dc810e39 19211#define bfd_elf32_bfd_reloc_type_lookup elf32_arm_reloc_type_lookup
b38cadfb 19212#define bfd_elf32_bfd_reloc_name_lookup elf32_arm_reloc_name_lookup
252b5132 19213#define bfd_elf32_find_nearest_line elf32_arm_find_nearest_line
4ab527b0 19214#define bfd_elf32_find_inliner_info elf32_arm_find_inliner_info
e489d0ae 19215#define bfd_elf32_new_section_hook elf32_arm_new_section_hook
3c9458e9 19216#define bfd_elf32_bfd_is_target_special_symbol elf32_arm_is_target_special_symbol
3e6b1042 19217#define bfd_elf32_bfd_final_link elf32_arm_final_link
6a631e86 19218#define bfd_elf32_get_synthetic_symtab elf32_arm_get_synthetic_symtab
252b5132
RH		 19219
19220#define elf_backend_get_symbol_type elf32_arm_get_symbol_type
19221#define elf_backend_gc_mark_hook elf32_arm_gc_mark_hook
6a5bb875 19222#define elf_backend_gc_mark_extra_sections elf32_arm_gc_mark_extra_sections
252b5132
RH		 19223#define elf_backend_gc_sweep_hook elf32_arm_gc_sweep_hook
19224#define elf_backend_check_relocs elf32_arm_check_relocs
dc810e39 19225#define elf_backend_relocate_section elf32_arm_relocate_section
e489d0ae 19226#define elf_backend_write_section elf32_arm_write_section
252b5132 19227#define elf_backend_adjust_dynamic_symbol elf32_arm_adjust_dynamic_symbol
5e681ec4 19228#define elf_backend_create_dynamic_sections elf32_arm_create_dynamic_sections
252b5132
RH		 19229#define elf_backend_finish_dynamic_symbol elf32_arm_finish_dynamic_symbol
19230#define elf_backend_finish_dynamic_sections elf32_arm_finish_dynamic_sections
19231#define elf_backend_size_dynamic_sections elf32_arm_size_dynamic_sections
0855e32b 19232#define elf_backend_always_size_sections elf32_arm_always_size_sections
74541ad4 19233#define elf_backend_init_index_section _bfd_elf_init_2_index_sections
ba96a88f 19234#define elf_backend_post_process_headers elf32_arm_post_process_headers
99e4ae17 19235#define elf_backend_reloc_type_class elf32_arm_reloc_type_class
c178919b 19236#define elf_backend_object_p elf32_arm_object_p
40a18ebd
NC		 19237#define elf_backend_fake_sections elf32_arm_fake_sections
19238#define elf_backend_section_from_shdr elf32_arm_section_from_shdr
e16bb312 19239#define elf_backend_final_write_processing elf32_arm_final_write_processing
5e681ec4 19240#define elf_backend_copy_indirect_symbol elf32_arm_copy_indirect_symbol
0beaef2b 19241#define elf_backend_size_info elf32_arm_size_info
b294bdf8 19242#define elf_backend_modify_segment_map elf32_arm_modify_segment_map
906e58ca
NC		 19243#define elf_backend_additional_program_headers elf32_arm_additional_program_headers
19244#define elf_backend_output_arch_local_syms elf32_arm_output_arch_local_syms
54ddd295 19245#define elf_backend_filter_implib_symbols elf32_arm_filter_implib_symbols
906e58ca 19246#define elf_backend_begin_write_processing elf32_arm_begin_write_processing
34e77a92 19247#define elf_backend_add_symbol_hook elf32_arm_add_symbol_hook
491d01d3 19248#define elf_backend_count_additional_relocs elf32_arm_count_additional_relocs
fca2a38f 19249#define elf_backend_symbol_processing elf32_arm_backend_symbol_processing
906e58ca
NC		 19250
19251#define elf_backend_can_refcount 1
19252#define elf_backend_can_gc_sections 1
19253#define elf_backend_plt_readonly 1
19254#define elf_backend_want_got_plt 1
19255#define elf_backend_want_plt_sym 0
19256#define elf_backend_may_use_rel_p 1
19257#define elf_backend_may_use_rela_p 0
4e7fd91e 19258#define elf_backend_default_use_rela_p 0
252b5132 19259
04f7c78d 19260#define elf_backend_got_header_size 12
b68a20d6 19261#define elf_backend_extern_protected_data 1
04f7c78d 19262
906e58ca
NC		 19263#undef elf_backend_obj_attrs_vendor
19264#define elf_backend_obj_attrs_vendor "aeabi"
19265#undef elf_backend_obj_attrs_section
19266#define elf_backend_obj_attrs_section ".ARM.attributes"
19267#undef elf_backend_obj_attrs_arg_type
19268#define elf_backend_obj_attrs_arg_type elf32_arm_obj_attrs_arg_type
19269#undef elf_backend_obj_attrs_section_type
104d59d1 19270#define elf_backend_obj_attrs_section_type SHT_ARM_ATTRIBUTES
b38cadfb
NC		 19271#define elf_backend_obj_attrs_order elf32_arm_obj_attrs_order
19272#define elf_backend_obj_attrs_handle_unknown elf32_arm_obj_attrs_handle_unknown
104d59d1 19273
ac4c9b04
MG		 19274#undef elf_backend_section_flags
19275#define elf_backend_section_flags elf32_arm_section_flags
19276#undef elf_backend_lookup_section_flags_hook
19277#define elf_backend_lookup_section_flags_hook elf32_arm_lookup_section_flags
19278
252b5132 19279#include "elf32-target.h"
7f266840 19280
b38cadfb
NC		 19281/* Native Client targets. */
19282
19283#undef TARGET_LITTLE_SYM
6d00b590 19284#define TARGET_LITTLE_SYM arm_elf32_nacl_le_vec
b38cadfb
NC		 19285#undef TARGET_LITTLE_NAME
19286#define TARGET_LITTLE_NAME "elf32-littlearm-nacl"
19287#undef TARGET_BIG_SYM
6d00b590 19288#define TARGET_BIG_SYM arm_elf32_nacl_be_vec
b38cadfb
NC		 19289#undef TARGET_BIG_NAME
19290#define TARGET_BIG_NAME "elf32-bigarm-nacl"
19291
19292/* Like elf32_arm_link_hash_table_create -- but overrides
19293 appropriately for NaCl. */
19294
19295static struct bfd_link_hash_table *
19296elf32_arm_nacl_link_hash_table_create (bfd *abfd)
19297{
19298 struct bfd_link_hash_table *ret;
19299
19300 ret = elf32_arm_link_hash_table_create (abfd);
19301 if (ret)
19302 {
19303 struct elf32_arm_link_hash_table *htab
19304 = (struct elf32_arm_link_hash_table *) ret;
19305
19306 htab->nacl_p = 1;
19307
19308 htab->plt_header_size = 4 * ARRAY_SIZE (elf32_arm_nacl_plt0_entry);
19309 htab->plt_entry_size = 4 * ARRAY_SIZE (elf32_arm_nacl_plt_entry);
19310 }
19311 return ret;
19312}
19313
19314/* Since NaCl doesn't use the ARM-specific unwind format, we don't
19315 really need to use elf32_arm_modify_segment_map. But we do it
19316 anyway just to reduce gratuitous differences with the stock ARM backend. */
19317
19318static bfd_boolean
19319elf32_arm_nacl_modify_segment_map (bfd *abfd, struct bfd_link_info *info)
19320{
19321 return (elf32_arm_modify_segment_map (abfd, info)
19322 && nacl_modify_segment_map (abfd, info));
19323}
19324
887badb3
RM		 19325static void
19326elf32_arm_nacl_final_write_processing (bfd *abfd, bfd_boolean linker)
19327{
19328 elf32_arm_final_write_processing (abfd, linker);
19329 nacl_final_write_processing (abfd, linker);
19330}
19331
6a631e86
YG		 19332static bfd_vma
19333elf32_arm_nacl_plt_sym_val (bfd_vma i, const asection *plt,
19334 const arelent *rel ATTRIBUTE_UNUSED)
19335{
19336 return plt->vma
19337 + 4 * (ARRAY_SIZE (elf32_arm_nacl_plt0_entry) +
19338 i * ARRAY_SIZE (elf32_arm_nacl_plt_entry));
19339}
887badb3 19340
b38cadfb 19341#undef elf32_bed
6a631e86 19342#define elf32_bed elf32_arm_nacl_bed
b38cadfb
NC		 19343#undef bfd_elf32_bfd_link_hash_table_create
19344#define bfd_elf32_bfd_link_hash_table_create \
19345 elf32_arm_nacl_link_hash_table_create
19346#undef elf_backend_plt_alignment
6a631e86 19347#define elf_backend_plt_alignment 4
b38cadfb
NC		 19348#undef elf_backend_modify_segment_map
19349#define elf_backend_modify_segment_map elf32_arm_nacl_modify_segment_map
19350#undef elf_backend_modify_program_headers
19351#define elf_backend_modify_program_headers nacl_modify_program_headers
887badb3
RM		 19352#undef elf_backend_final_write_processing
19353#define elf_backend_final_write_processing elf32_arm_nacl_final_write_processing
6a631e86
YG		 19354#undef bfd_elf32_get_synthetic_symtab
19355#undef elf_backend_plt_sym_val
19356#define elf_backend_plt_sym_val elf32_arm_nacl_plt_sym_val
5522f910 19357#undef elf_backend_copy_special_section_fields
b38cadfb 19358
887badb3
RM		 19359#undef ELF_MINPAGESIZE
19360#undef ELF_COMMONPAGESIZE
19361
b38cadfb
NC		 19362
19363#include "elf32-target.h"
19364
19365/* Reset to defaults. */
19366#undef elf_backend_plt_alignment
19367#undef elf_backend_modify_segment_map
19368#define elf_backend_modify_segment_map elf32_arm_modify_segment_map
19369#undef elf_backend_modify_program_headers
887badb3
RM		 19370#undef elf_backend_final_write_processing
19371#define elf_backend_final_write_processing elf32_arm_final_write_processing
19372#undef ELF_MINPAGESIZE
19373#define ELF_MINPAGESIZE 0x1000
19374#undef ELF_COMMONPAGESIZE
19375#define ELF_COMMONPAGESIZE 0x1000
19376
b38cadfb 19377
906e58ca 19378/* VxWorks Targets. */
4e7fd91e 19379
906e58ca 19380#undef TARGET_LITTLE_SYM
6d00b590 19381#define TARGET_LITTLE_SYM arm_elf32_vxworks_le_vec
906e58ca 19382#undef TARGET_LITTLE_NAME
4e7fd91e 19383#define TARGET_LITTLE_NAME "elf32-littlearm-vxworks"
906e58ca 19384#undef TARGET_BIG_SYM
6d00b590 19385#define TARGET_BIG_SYM arm_elf32_vxworks_be_vec
906e58ca 19386#undef TARGET_BIG_NAME
4e7fd91e
PB		 19387#define TARGET_BIG_NAME "elf32-bigarm-vxworks"
19388
19389/* Like elf32_arm_link_hash_table_create -- but overrides
19390 appropriately for VxWorks. */
906e58ca 19391
4e7fd91e
PB		 19392static struct bfd_link_hash_table *
19393elf32_arm_vxworks_link_hash_table_create (bfd *abfd)
19394{
19395 struct bfd_link_hash_table *ret;
19396
19397 ret = elf32_arm_link_hash_table_create (abfd);
19398 if (ret)
19399 {
19400 struct elf32_arm_link_hash_table *htab
00a97672 19401 = (struct elf32_arm_link_hash_table *) ret;
4e7fd91e 19402 htab->use_rel = 0;
00a97672 19403 htab->vxworks_p = 1;
4e7fd91e
PB		 19404 }
19405 return ret;
906e58ca 19406}
4e7fd91e 19407
00a97672
RS		 19408static void
19409elf32_arm_vxworks_final_write_processing (bfd *abfd, bfd_boolean linker)
19410{
19411 elf32_arm_final_write_processing (abfd, linker);
19412 elf_vxworks_final_write_processing (abfd, linker);
19413}
19414
906e58ca 19415#undef elf32_bed
4e7fd91e
PB		 19416#define elf32_bed elf32_arm_vxworks_bed
19417
906e58ca
NC		 19418#undef bfd_elf32_bfd_link_hash_table_create
19419#define bfd_elf32_bfd_link_hash_table_create elf32_arm_vxworks_link_hash_table_create
906e58ca
NC		 19420#undef elf_backend_final_write_processing
19421#define elf_backend_final_write_processing elf32_arm_vxworks_final_write_processing
19422#undef elf_backend_emit_relocs
19423#define elf_backend_emit_relocs elf_vxworks_emit_relocs
4e7fd91e 19424
906e58ca 19425#undef elf_backend_may_use_rel_p
00a97672 19426#define elf_backend_may_use_rel_p 0
906e58ca 19427#undef elf_backend_may_use_rela_p
00a97672 19428#define elf_backend_may_use_rela_p 1
906e58ca 19429#undef elf_backend_default_use_rela_p
00a97672 19430#define elf_backend_default_use_rela_p 1
906e58ca 19431#undef elf_backend_want_plt_sym
00a97672 19432#define elf_backend_want_plt_sym 1
906e58ca 19433#undef ELF_MAXPAGESIZE
00a97672 19434#define ELF_MAXPAGESIZE 0x1000
4e7fd91e
PB		 19435
19436#include "elf32-target.h"
19437
19438
21d799b5
NC		 19439/* Merge backend specific data from an object file to the output
19440 object file when linking. */
19441
19442static bfd_boolean
19443elf32_arm_merge_private_bfd_data (bfd * ibfd, bfd * obfd)
19444{
19445 flagword out_flags;
19446 flagword in_flags;
19447 bfd_boolean flags_compatible = TRUE;
19448 asection *sec;
19449
cc643b88 19450 /* Check if we have the same endianness. */
21d799b5
NC		 19451 if (! _bfd_generic_verify_endian_match (ibfd, obfd))
19452 return FALSE;
19453
19454 if (! is_arm_elf (ibfd) || ! is_arm_elf (obfd))
19455 return TRUE;
19456
19457 if (!elf32_arm_merge_eabi_attributes (ibfd, obfd))
19458 return FALSE;
19459
19460 /* The input BFD must have had its flags initialised. */
19461 /* The following seems bogus to me -- The flags are initialized in
19462 the assembler but I don't think an elf_flags_init field is
19463 written into the object. */
19464 /* BFD_ASSERT (elf_flags_init (ibfd)); */
19465
19466 in_flags = elf_elfheader (ibfd)->e_flags;
19467 out_flags = elf_elfheader (obfd)->e_flags;
19468
19469 /* In theory there is no reason why we couldn't handle this. However
19470 in practice it isn't even close to working and there is no real
19471 reason to want it. */
19472 if (EF_ARM_EABI_VERSION (in_flags) >= EF_ARM_EABI_VER4
19473 && !(ibfd->flags & DYNAMIC)
19474 && (in_flags & EF_ARM_BE8))
19475 {
19476 _bfd_error_handler (_("error: %B is already in final BE8 format"),
19477 ibfd);
19478 return FALSE;
19479 }
19480
19481 if (!elf_flags_init (obfd))
19482 {
19483 /* If the input is the default architecture and had the default
19484 flags then do not bother setting the flags for the output
19485 architecture, instead allow future merges to do this. If no
19486 future merges ever set these flags then they will retain their
99059e56
RM		 19487 uninitialised values, which surprise surprise, correspond
19488 to the default values. */
21d799b5
NC		 19489 if (bfd_get_arch_info (ibfd)->the_default
19490 && elf_elfheader (ibfd)->e_flags == 0)
19491 return TRUE;
19492
19493 elf_flags_init (obfd) = TRUE;
19494 elf_elfheader (obfd)->e_flags = in_flags;
19495
19496 if (bfd_get_arch (obfd) == bfd_get_arch (ibfd)
19497 && bfd_get_arch_info (obfd)->the_default)
19498 return bfd_set_arch_mach (obfd, bfd_get_arch (ibfd), bfd_get_mach (ibfd));
19499
19500 return TRUE;
19501 }
19502
19503 /* Determine what should happen if the input ARM architecture
19504 does not match the output ARM architecture. */
19505 if (! bfd_arm_merge_machines (ibfd, obfd))
19506 return FALSE;
19507
19508 /* Identical flags must be compatible. */
19509 if (in_flags == out_flags)
19510 return TRUE;
19511
19512 /* Check to see if the input BFD actually contains any sections. If
19513 not, its flags may not have been initialised either, but it
19514 cannot actually cause any incompatiblity. Do not short-circuit
19515 dynamic objects; their section list may be emptied by
19516 elf_link_add_object_symbols.
19517
19518 Also check to see if there are no code sections in the input.
19519 In this case there is no need to check for code specific flags.
19520 XXX - do we need to worry about floating-point format compatability
19521 in data sections ? */
19522 if (!(ibfd->flags & DYNAMIC))
19523 {
19524 bfd_boolean null_input_bfd = TRUE;
19525 bfd_boolean only_data_sections = TRUE;
19526
19527 for (sec = ibfd->sections; sec != NULL; sec = sec->next)
19528 {
19529 /* Ignore synthetic glue sections. */
19530 if (strcmp (sec->name, ".glue_7")
19531 && strcmp (sec->name, ".glue_7t"))
19532 {
19533 if ((bfd_get_section_flags (ibfd, sec)
19534 & (SEC_LOAD | SEC_CODE | SEC_HAS_CONTENTS))
19535 == (SEC_LOAD | SEC_CODE | SEC_HAS_CONTENTS))
99059e56 19536 only_data_sections = FALSE;
21d799b5
NC		 19537
19538 null_input_bfd = FALSE;
19539 break;
19540 }
19541 }
19542
19543 if (null_input_bfd || only_data_sections)
19544 return TRUE;
19545 }
19546
19547 /* Complain about various flag mismatches. */
19548 if (!elf32_arm_versions_compatible (EF_ARM_EABI_VERSION (in_flags),
19549 EF_ARM_EABI_VERSION (out_flags)))
19550 {
19551 _bfd_error_handler
19552 (_("error: Source object %B has EABI version %d, but target %B has EABI version %d"),
19553 ibfd, obfd,
19554 (in_flags & EF_ARM_EABIMASK) >> 24,
19555 (out_flags & EF_ARM_EABIMASK) >> 24);
19556 return FALSE;
19557 }
19558
19559 /* Not sure what needs to be checked for EABI versions >= 1. */
19560 /* VxWorks libraries do not use these flags. */
19561 if (get_elf_backend_data (obfd) != &elf32_arm_vxworks_bed
19562 && get_elf_backend_data (ibfd) != &elf32_arm_vxworks_bed
19563 && EF_ARM_EABI_VERSION (in_flags) == EF_ARM_EABI_UNKNOWN)
19564 {
19565 if ((in_flags & EF_ARM_APCS_26) != (out_flags & EF_ARM_APCS_26))
19566 {
19567 _bfd_error_handler
19568 (_("error: %B is compiled for APCS-%d, whereas target %B uses APCS-%d"),
19569 ibfd, obfd,
19570 in_flags & EF_ARM_APCS_26 ? 26 : 32,
19571 out_flags & EF_ARM_APCS_26 ? 26 : 32);
19572 flags_compatible = FALSE;
19573 }
19574
19575 if ((in_flags & EF_ARM_APCS_FLOAT) != (out_flags & EF_ARM_APCS_FLOAT))
19576 {
19577 if (in_flags & EF_ARM_APCS_FLOAT)
19578 _bfd_error_handler
19579 (_("error: %B passes floats in float registers, whereas %B passes them in integer registers"),
19580 ibfd, obfd);
19581 else
19582 _bfd_error_handler
19583 (_("error: %B passes floats in integer registers, whereas %B passes them in float registers"),
19584 ibfd, obfd);
19585
19586 flags_compatible = FALSE;
19587 }
19588
19589 if ((in_flags & EF_ARM_VFP_FLOAT) != (out_flags & EF_ARM_VFP_FLOAT))
19590 {
19591 if (in_flags & EF_ARM_VFP_FLOAT)
19592 _bfd_error_handler
19593 (_("error: %B uses VFP instructions, whereas %B does not"),
19594 ibfd, obfd);
19595 else
19596 _bfd_error_handler
19597 (_("error: %B uses FPA instructions, whereas %B does not"),
19598 ibfd, obfd);
19599
19600 flags_compatible = FALSE;
19601 }
19602
19603 if ((in_flags & EF_ARM_MAVERICK_FLOAT) != (out_flags & EF_ARM_MAVERICK_FLOAT))
19604 {
19605 if (in_flags & EF_ARM_MAVERICK_FLOAT)
19606 _bfd_error_handler
19607 (_("error: %B uses Maverick instructions, whereas %B does not"),
19608 ibfd, obfd);
19609 else
19610 _bfd_error_handler
19611 (_("error: %B does not use Maverick instructions, whereas %B does"),
19612 ibfd, obfd);
19613
19614 flags_compatible = FALSE;
19615 }
19616
19617#ifdef EF_ARM_SOFT_FLOAT
19618 if ((in_flags & EF_ARM_SOFT_FLOAT) != (out_flags & EF_ARM_SOFT_FLOAT))
19619 {
19620 /* We can allow interworking between code that is VFP format
19621 layout, and uses either soft float or integer regs for
19622 passing floating point arguments and results. We already
19623 know that the APCS_FLOAT flags match; similarly for VFP
19624 flags. */
19625 if ((in_flags & EF_ARM_APCS_FLOAT) != 0
19626 || (in_flags & EF_ARM_VFP_FLOAT) == 0)
19627 {
19628 if (in_flags & EF_ARM_SOFT_FLOAT)
19629 _bfd_error_handler
19630 (_("error: %B uses software FP, whereas %B uses hardware FP"),
19631 ibfd, obfd);
19632 else
19633 _bfd_error_handler
19634 (_("error: %B uses hardware FP, whereas %B uses software FP"),
19635 ibfd, obfd);
19636
19637 flags_compatible = FALSE;
19638 }
19639 }
19640#endif
19641
19642 /* Interworking mismatch is only a warning. */
19643 if ((in_flags & EF_ARM_INTERWORK) != (out_flags & EF_ARM_INTERWORK))
19644 {
19645 if (in_flags & EF_ARM_INTERWORK)
19646 {
19647 _bfd_error_handler
19648 (_("Warning: %B supports interworking, whereas %B does not"),
19649 ibfd, obfd);
19650 }
19651 else
19652 {
19653 _bfd_error_handler
19654 (_("Warning: %B does not support interworking, whereas %B does"),
19655 ibfd, obfd);
19656 }
19657 }
19658 }
19659
19660 return flags_compatible;
19661}
19662
19663
906e58ca 19664/* Symbian OS Targets. */
7f266840 19665
906e58ca 19666#undef TARGET_LITTLE_SYM
6d00b590 19667#define TARGET_LITTLE_SYM arm_elf32_symbian_le_vec
906e58ca 19668#undef TARGET_LITTLE_NAME
7f266840 19669#define TARGET_LITTLE_NAME "elf32-littlearm-symbian"
906e58ca 19670#undef TARGET_BIG_SYM
6d00b590 19671#define TARGET_BIG_SYM arm_elf32_symbian_be_vec
906e58ca 19672#undef TARGET_BIG_NAME
7f266840
DJ		 19673#define TARGET_BIG_NAME "elf32-bigarm-symbian"
19674
19675/* Like elf32_arm_link_hash_table_create -- but overrides
19676 appropriately for Symbian OS. */
906e58ca 19677
7f266840
DJ		 19678static struct bfd_link_hash_table *
19679elf32_arm_symbian_link_hash_table_create (bfd *abfd)
19680{
19681 struct bfd_link_hash_table *ret;
19682
19683 ret = elf32_arm_link_hash_table_create (abfd);
19684 if (ret)
19685 {
19686 struct elf32_arm_link_hash_table *htab
19687 = (struct elf32_arm_link_hash_table *)ret;
19688 /* There is no PLT header for Symbian OS. */
19689 htab->plt_header_size = 0;
95720a86
DJ		 19690 /* The PLT entries are each one instruction and one word. */
19691 htab->plt_entry_size = 4 * ARRAY_SIZE (elf32_arm_symbian_plt_entry);
7f266840 19692 htab->symbian_p = 1;
33bfe774
JB		 19693 /* Symbian uses armv5t or above, so use_blx is always true. */
19694 htab->use_blx = 1;
67687978 19695 htab->root.is_relocatable_executable = 1;
7f266840
DJ		 19696 }
19697 return ret;
906e58ca 19698}
7f266840 19699
b35d266b 19700static const struct bfd_elf_special_section
551b43fd 19701elf32_arm_symbian_special_sections[] =
7f266840 19702{
5cd3778d
MM		 19703 /* In a BPABI executable, the dynamic linking sections do not go in
19704 the loadable read-only segment. The post-linker may wish to
19705 refer to these sections, but they are not part of the final
19706 program image. */
0112cd26
NC		 19707 { STRING_COMMA_LEN (".dynamic"), 0, SHT_DYNAMIC, 0 },
19708 { STRING_COMMA_LEN (".dynstr"), 0, SHT_STRTAB, 0 },
19709 { STRING_COMMA_LEN (".dynsym"), 0, SHT_DYNSYM, 0 },
19710 { STRING_COMMA_LEN (".got"), 0, SHT_PROGBITS, 0 },
19711 { STRING_COMMA_LEN (".hash"), 0, SHT_HASH, 0 },
5cd3778d
MM		 19712 /* These sections do not need to be writable as the SymbianOS
19713 postlinker will arrange things so that no dynamic relocation is
19714 required. */
0112cd26
NC		 19715 { STRING_COMMA_LEN (".init_array"), 0, SHT_INIT_ARRAY, SHF_ALLOC },
19716 { STRING_COMMA_LEN (".fini_array"), 0, SHT_FINI_ARRAY, SHF_ALLOC },
19717 { STRING_COMMA_LEN (".preinit_array"), 0, SHT_PREINIT_ARRAY, SHF_ALLOC },
19718 { NULL, 0, 0, 0, 0 }
7f266840
DJ		 19719};
19720
c3c76620 19721static void
906e58ca 19722elf32_arm_symbian_begin_write_processing (bfd *abfd,
a4fd1a8e 19723 struct bfd_link_info *link_info)
c3c76620
MM		 19724{
19725 /* BPABI objects are never loaded directly by an OS kernel; they are
19726 processed by a postlinker first, into an OS-specific format. If
19727 the D_PAGED bit is set on the file, BFD will align segments on
19728 page boundaries, so that an OS can directly map the file. With
19729 BPABI objects, that just results in wasted space. In addition,
19730 because we clear the D_PAGED bit, map_sections_to_segments will
19731 recognize that the program headers should not be mapped into any
19732 loadable segment. */
19733 abfd->flags &= ~D_PAGED;
906e58ca 19734 elf32_arm_begin_write_processing (abfd, link_info);
c3c76620 19735}
7f266840
DJ		 19736
19737static bfd_boolean
906e58ca 19738elf32_arm_symbian_modify_segment_map (bfd *abfd,
b294bdf8 19739 struct bfd_link_info *info)
7f266840
DJ		 19740{
19741 struct elf_segment_map *m;
19742 asection *dynsec;
19743
7f266840
DJ		 19744 /* BPABI shared libraries and executables should have a PT_DYNAMIC
19745 segment. However, because the .dynamic section is not marked
19746 with SEC_LOAD, the generic ELF code will not create such a
19747 segment. */
19748 dynsec = bfd_get_section_by_name (abfd, ".dynamic");
19749 if (dynsec)
19750 {
12bd6957 19751 for (m = elf_seg_map (abfd); m != NULL; m = m->next)
8ded5a0f
AM		 19752 if (m->p_type == PT_DYNAMIC)
19753 break;
19754
19755 if (m == NULL)
19756 {
19757 m = _bfd_elf_make_dynamic_segment (abfd, dynsec);
12bd6957
AM		 19758 m->next = elf_seg_map (abfd);
19759 elf_seg_map (abfd) = m;
8ded5a0f 19760 }
7f266840
DJ		 19761 }
19762
b294bdf8
MM		 19763 /* Also call the generic arm routine. */
19764 return elf32_arm_modify_segment_map (abfd, info);
7f266840
DJ		 19765}
19766
95720a86
DJ		 19767/* Return address for Ith PLT stub in section PLT, for relocation REL
19768 or (bfd_vma) -1 if it should not be included. */
19769
19770static bfd_vma
19771elf32_arm_symbian_plt_sym_val (bfd_vma i, const asection *plt,
19772 const arelent *rel ATTRIBUTE_UNUSED)
19773{
19774 return plt->vma + 4 * ARRAY_SIZE (elf32_arm_symbian_plt_entry) * i;
19775}
19776
8029a119 19777#undef elf32_bed
7f266840
DJ		 19778#define elf32_bed elf32_arm_symbian_bed
19779
19780/* The dynamic sections are not allocated on SymbianOS; the postlinker
19781 will process them and then discard them. */
906e58ca 19782#undef ELF_DYNAMIC_SEC_FLAGS
7f266840
DJ		 19783#define ELF_DYNAMIC_SEC_FLAGS \
19784 (SEC_HAS_CONTENTS | SEC_IN_MEMORY | SEC_LINKER_CREATED)
19785
00a97672 19786#undef elf_backend_emit_relocs
c3c76620 19787
906e58ca
NC		 19788#undef bfd_elf32_bfd_link_hash_table_create
19789#define bfd_elf32_bfd_link_hash_table_create elf32_arm_symbian_link_hash_table_create
19790#undef elf_backend_special_sections
19791#define elf_backend_special_sections elf32_arm_symbian_special_sections
19792#undef elf_backend_begin_write_processing
19793#define elf_backend_begin_write_processing elf32_arm_symbian_begin_write_processing
19794#undef elf_backend_final_write_processing
19795#define elf_backend_final_write_processing elf32_arm_final_write_processing
19796
19797#undef elf_backend_modify_segment_map
7f266840
DJ		 19798#define elf_backend_modify_segment_map elf32_arm_symbian_modify_segment_map
19799
19800/* There is no .got section for BPABI objects, and hence no header. */
906e58ca 19801#undef elf_backend_got_header_size
7f266840
DJ		 19802#define elf_backend_got_header_size 0
19803
19804/* Similarly, there is no .got.plt section. */
906e58ca 19805#undef elf_backend_want_got_plt
7f266840
DJ		 19806#define elf_backend_want_got_plt 0
19807
906e58ca 19808#undef elf_backend_plt_sym_val
95720a86
DJ		 19809#define elf_backend_plt_sym_val elf32_arm_symbian_plt_sym_val
19810
906e58ca 19811#undef elf_backend_may_use_rel_p
00a97672 19812#define elf_backend_may_use_rel_p 1
906e58ca 19813#undef elf_backend_may_use_rela_p
00a97672 19814#define elf_backend_may_use_rela_p 0
906e58ca 19815#undef elf_backend_default_use_rela_p
00a97672 19816#define elf_backend_default_use_rela_p 0
906e58ca 19817#undef elf_backend_want_plt_sym
00a97672 19818#define elf_backend_want_plt_sym 0
906e58ca 19819#undef ELF_MAXPAGESIZE
00a97672 19820#define ELF_MAXPAGESIZE 0x8000
4e7fd91e 19821
7f266840 19822#include "elf32-target.h"
GDB Binutils - Deliverables
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