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tic6x bfd.h tidy
[deliverable/binutils-gdb.git] / bfd / elf32-arm.c
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252b5132 1/* 32-bit ELF support for ARM
82704155 2 Copyright (C) 1998-2019 Free Software Foundation, Inc.
252b5132
RH		 3
4 This file is part of BFD, the Binary File Descriptor library.
5
6 This program is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
cd123cb7 8 the Free Software Foundation; either version 3 of the License, or
252b5132
RH		 9 (at your option) any later version.
10
11 This program is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
15
16 You should have received a copy of the GNU General Public License
17 along with this program; if not, write to the Free Software
cd123cb7
NC		 18 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
19 MA 02110-1301, USA. */
252b5132 20
6e6718a3 21#include "sysdep.h"
2468f9c9
PB		 22#include <limits.h>
23
3db64b00 24#include "bfd.h"
00a97672 25#include "libiberty.h"
7f266840
DJ		 26#include "libbfd.h"
27#include "elf-bfd.h"
b38cadfb 28#include "elf-nacl.h"
00a97672 29#include "elf-vxworks.h"
ee065d83 30#include "elf/arm.h"
7f266840 31
00a97672
RS		 32/* Return the relocation section associated with NAME. HTAB is the
33 bfd's elf32_arm_link_hash_entry. */
34#define RELOC_SECTION(HTAB, NAME) \
35 ((HTAB)->use_rel ? ".rel" NAME : ".rela" NAME)
36
37/* Return size of a relocation entry. HTAB is the bfd's
38 elf32_arm_link_hash_entry. */
39#define RELOC_SIZE(HTAB) \
40 ((HTAB)->use_rel \
41 ? sizeof (Elf32_External_Rel) \
42 : sizeof (Elf32_External_Rela))
43
44/* Return function to swap relocations in. HTAB is the bfd's
45 elf32_arm_link_hash_entry. */
46#define SWAP_RELOC_IN(HTAB) \
47 ((HTAB)->use_rel \
48 ? bfd_elf32_swap_reloc_in \
49 : bfd_elf32_swap_reloca_in)
50
51/* Return function to swap relocations out. HTAB is the bfd's
52 elf32_arm_link_hash_entry. */
53#define SWAP_RELOC_OUT(HTAB) \
54 ((HTAB)->use_rel \
55 ? bfd_elf32_swap_reloc_out \
56 : bfd_elf32_swap_reloca_out)
57
f3185997 58#define elf_info_to_howto NULL
07d6d2b8 59#define elf_info_to_howto_rel elf32_arm_info_to_howto
7f266840
DJ		 60
61#define ARM_ELF_ABI_VERSION 0
62#define ARM_ELF_OS_ABI_VERSION ELFOSABI_ARM
63
79f08007
YZ		 64/* The Adjusted Place, as defined by AAELF. */
65#define Pa(X) ((X) & 0xfffffffc)
66
3e6b1042
DJ		 67static bfd_boolean elf32_arm_write_section (bfd *output_bfd,
68 struct bfd_link_info *link_info,
69 asection *sec,
70 bfd_byte *contents);
71
7f266840
DJ		 72/* Note: code such as elf32_arm_reloc_type_lookup expect to use e.g.
73 R_ARM_PC24 as an index into this, and find the R_ARM_PC24 HOWTO
74 in that slot. */
75
c19d1205 76static reloc_howto_type elf32_arm_howto_table_1[] =
7f266840 77{
8029a119 78 /* No relocation. */
7f266840
DJ		 79 HOWTO (R_ARM_NONE, /* type */
80 0, /* rightshift */
6346d5ca 81 3, /* size (0 = byte, 1 = short, 2 = long) */
7f266840
DJ		 82 0, /* bitsize */
83 FALSE, /* pc_relative */
84 0, /* bitpos */
85 complain_overflow_dont,/* complain_on_overflow */
86 bfd_elf_generic_reloc, /* special_function */
87 "R_ARM_NONE", /* name */
88 FALSE, /* partial_inplace */
89 0, /* src_mask */
90 0, /* dst_mask */
91 FALSE), /* pcrel_offset */
92
93 HOWTO (R_ARM_PC24, /* type */
94 2, /* rightshift */
95 2, /* size (0 = byte, 1 = short, 2 = long) */
96 24, /* bitsize */
97 TRUE, /* pc_relative */
98 0, /* bitpos */
99 complain_overflow_signed,/* complain_on_overflow */
100 bfd_elf_generic_reloc, /* special_function */
101 "R_ARM_PC24", /* name */
102 FALSE, /* partial_inplace */
103 0x00ffffff, /* src_mask */
104 0x00ffffff, /* dst_mask */
105 TRUE), /* pcrel_offset */
106
107 /* 32 bit absolute */
108 HOWTO (R_ARM_ABS32, /* type */
109 0, /* rightshift */
110 2, /* size (0 = byte, 1 = short, 2 = long) */
111 32, /* bitsize */
112 FALSE, /* pc_relative */
113 0, /* bitpos */
114 complain_overflow_bitfield,/* complain_on_overflow */
115 bfd_elf_generic_reloc, /* special_function */
116 "R_ARM_ABS32", /* name */
117 FALSE, /* partial_inplace */
118 0xffffffff, /* src_mask */
119 0xffffffff, /* dst_mask */
120 FALSE), /* pcrel_offset */
121
122 /* standard 32bit pc-relative reloc */
123 HOWTO (R_ARM_REL32, /* type */
124 0, /* rightshift */
125 2, /* size (0 = byte, 1 = short, 2 = long) */
126 32, /* bitsize */
127 TRUE, /* pc_relative */
128 0, /* bitpos */
129 complain_overflow_bitfield,/* complain_on_overflow */
130 bfd_elf_generic_reloc, /* special_function */
131 "R_ARM_REL32", /* name */
132 FALSE, /* partial_inplace */
133 0xffffffff, /* src_mask */
134 0xffffffff, /* dst_mask */
135 TRUE), /* pcrel_offset */
136
c19d1205 137 /* 8 bit absolute - R_ARM_LDR_PC_G0 in AAELF */
4962c51a 138 HOWTO (R_ARM_LDR_PC_G0, /* type */
7f266840
DJ		 139 0, /* rightshift */
140 0, /* size (0 = byte, 1 = short, 2 = long) */
4962c51a
MS		 141 32, /* bitsize */
142 TRUE, /* pc_relative */
7f266840 143 0, /* bitpos */
4962c51a 144 complain_overflow_dont,/* complain_on_overflow */
7f266840 145 bfd_elf_generic_reloc, /* special_function */
4962c51a 146 "R_ARM_LDR_PC_G0", /* name */
7f266840 147 FALSE, /* partial_inplace */
4962c51a
MS		 148 0xffffffff, /* src_mask */
149 0xffffffff, /* dst_mask */
150 TRUE), /* pcrel_offset */
7f266840
DJ		 151
152 /* 16 bit absolute */
153 HOWTO (R_ARM_ABS16, /* type */
154 0, /* rightshift */
155 1, /* size (0 = byte, 1 = short, 2 = long) */
156 16, /* bitsize */
157 FALSE, /* pc_relative */
158 0, /* bitpos */
159 complain_overflow_bitfield,/* complain_on_overflow */
160 bfd_elf_generic_reloc, /* special_function */
161 "R_ARM_ABS16", /* name */
162 FALSE, /* partial_inplace */
163 0x0000ffff, /* src_mask */
164 0x0000ffff, /* dst_mask */
165 FALSE), /* pcrel_offset */
166
167 /* 12 bit absolute */
168 HOWTO (R_ARM_ABS12, /* type */
169 0, /* rightshift */
170 2, /* size (0 = byte, 1 = short, 2 = long) */
171 12, /* bitsize */
172 FALSE, /* pc_relative */
173 0, /* bitpos */
174 complain_overflow_bitfield,/* complain_on_overflow */
175 bfd_elf_generic_reloc, /* special_function */
176 "R_ARM_ABS12", /* name */
177 FALSE, /* partial_inplace */
00a97672
RS		 178 0x00000fff, /* src_mask */
179 0x00000fff, /* dst_mask */
7f266840
DJ		 180 FALSE), /* pcrel_offset */
181
182 HOWTO (R_ARM_THM_ABS5, /* type */
183 6, /* rightshift */
184 1, /* size (0 = byte, 1 = short, 2 = long) */
185 5, /* bitsize */
186 FALSE, /* pc_relative */
187 0, /* bitpos */
188 complain_overflow_bitfield,/* complain_on_overflow */
189 bfd_elf_generic_reloc, /* special_function */
190 "R_ARM_THM_ABS5", /* name */
191 FALSE, /* partial_inplace */
192 0x000007e0, /* src_mask */
193 0x000007e0, /* dst_mask */
194 FALSE), /* pcrel_offset */
195
196 /* 8 bit absolute */
197 HOWTO (R_ARM_ABS8, /* type */
198 0, /* rightshift */
199 0, /* size (0 = byte, 1 = short, 2 = long) */
200 8, /* bitsize */
201 FALSE, /* pc_relative */
202 0, /* bitpos */
203 complain_overflow_bitfield,/* complain_on_overflow */
204 bfd_elf_generic_reloc, /* special_function */
205 "R_ARM_ABS8", /* name */
206 FALSE, /* partial_inplace */
207 0x000000ff, /* src_mask */
208 0x000000ff, /* dst_mask */
209 FALSE), /* pcrel_offset */
210
211 HOWTO (R_ARM_SBREL32, /* type */
212 0, /* rightshift */
213 2, /* size (0 = byte, 1 = short, 2 = long) */
214 32, /* bitsize */
215 FALSE, /* pc_relative */
216 0, /* bitpos */
217 complain_overflow_dont,/* complain_on_overflow */
218 bfd_elf_generic_reloc, /* special_function */
219 "R_ARM_SBREL32", /* name */
220 FALSE, /* partial_inplace */
221 0xffffffff, /* src_mask */
222 0xffffffff, /* dst_mask */
223 FALSE), /* pcrel_offset */
224
c19d1205 225 HOWTO (R_ARM_THM_CALL, /* type */
7f266840
DJ		 226 1, /* rightshift */
227 2, /* size (0 = byte, 1 = short, 2 = long) */
f6ebfac0 228 24, /* bitsize */
7f266840
DJ		 229 TRUE, /* pc_relative */
230 0, /* bitpos */
231 complain_overflow_signed,/* complain_on_overflow */
232 bfd_elf_generic_reloc, /* special_function */
c19d1205 233 "R_ARM_THM_CALL", /* name */
7f266840 234 FALSE, /* partial_inplace */
7f6ab9f8
AM		 235 0x07ff2fff, /* src_mask */
236 0x07ff2fff, /* dst_mask */
7f266840
DJ		 237 TRUE), /* pcrel_offset */
238
07d6d2b8 239 HOWTO (R_ARM_THM_PC8, /* type */
7f266840
DJ		 240 1, /* rightshift */
241 1, /* size (0 = byte, 1 = short, 2 = long) */
242 8, /* bitsize */
243 TRUE, /* pc_relative */
244 0, /* bitpos */
245 complain_overflow_signed,/* complain_on_overflow */
246 bfd_elf_generic_reloc, /* special_function */
247 "R_ARM_THM_PC8", /* name */
248 FALSE, /* partial_inplace */
249 0x000000ff, /* src_mask */
250 0x000000ff, /* dst_mask */
251 TRUE), /* pcrel_offset */
252
c19d1205 253 HOWTO (R_ARM_BREL_ADJ, /* type */
7f266840
DJ		 254 1, /* rightshift */
255 1, /* size (0 = byte, 1 = short, 2 = long) */
c19d1205
ZW		 256 32, /* bitsize */
257 FALSE, /* pc_relative */
7f266840
DJ		 258 0, /* bitpos */
259 complain_overflow_signed,/* complain_on_overflow */
260 bfd_elf_generic_reloc, /* special_function */
c19d1205 261 "R_ARM_BREL_ADJ", /* name */
7f266840 262 FALSE, /* partial_inplace */
c19d1205
ZW		 263 0xffffffff, /* src_mask */
264 0xffffffff, /* dst_mask */
265 FALSE), /* pcrel_offset */
7f266840 266
0855e32b 267 HOWTO (R_ARM_TLS_DESC, /* type */
7f266840 268 0, /* rightshift */
0855e32b
NS		 269 2, /* size (0 = byte, 1 = short, 2 = long) */
270 32, /* bitsize */
7f266840
DJ		 271 FALSE, /* pc_relative */
272 0, /* bitpos */
0855e32b 273 complain_overflow_bitfield,/* complain_on_overflow */
7f266840 274 bfd_elf_generic_reloc, /* special_function */
0855e32b 275 "R_ARM_TLS_DESC", /* name */
7f266840 276 FALSE, /* partial_inplace */
0855e32b
NS		 277 0xffffffff, /* src_mask */
278 0xffffffff, /* dst_mask */
7f266840
DJ		 279 FALSE), /* pcrel_offset */
280
281 HOWTO (R_ARM_THM_SWI8, /* type */
282 0, /* rightshift */
283 0, /* size (0 = byte, 1 = short, 2 = long) */
284 0, /* bitsize */
285 FALSE, /* pc_relative */
286 0, /* bitpos */
287 complain_overflow_signed,/* complain_on_overflow */
288 bfd_elf_generic_reloc, /* special_function */
289 "R_ARM_SWI8", /* name */
290 FALSE, /* partial_inplace */
291 0x00000000, /* src_mask */
292 0x00000000, /* dst_mask */
293 FALSE), /* pcrel_offset */
294
295 /* BLX instruction for the ARM. */
296 HOWTO (R_ARM_XPC25, /* type */
297 2, /* rightshift */
298 2, /* size (0 = byte, 1 = short, 2 = long) */
7f6ab9f8 299 24, /* bitsize */
7f266840
DJ		 300 TRUE, /* pc_relative */
301 0, /* bitpos */
302 complain_overflow_signed,/* complain_on_overflow */
303 bfd_elf_generic_reloc, /* special_function */
304 "R_ARM_XPC25", /* name */
305 FALSE, /* partial_inplace */
306 0x00ffffff, /* src_mask */
307 0x00ffffff, /* dst_mask */
308 TRUE), /* pcrel_offset */
309
310 /* BLX instruction for the Thumb. */
311 HOWTO (R_ARM_THM_XPC22, /* type */
312 2, /* rightshift */
313 2, /* size (0 = byte, 1 = short, 2 = long) */
7f6ab9f8 314 24, /* bitsize */
7f266840
DJ		 315 TRUE, /* pc_relative */
316 0, /* bitpos */
317 complain_overflow_signed,/* complain_on_overflow */
318 bfd_elf_generic_reloc, /* special_function */
319 "R_ARM_THM_XPC22", /* name */
320 FALSE, /* partial_inplace */
7f6ab9f8
AM		 321 0x07ff2fff, /* src_mask */
322 0x07ff2fff, /* dst_mask */
7f266840
DJ		 323 TRUE), /* pcrel_offset */
324
ba93b8ac 325 /* Dynamic TLS relocations. */
7f266840 326
ba93b8ac 327 HOWTO (R_ARM_TLS_DTPMOD32, /* type */
07d6d2b8
AM		 328 0, /* rightshift */
329 2, /* size (0 = byte, 1 = short, 2 = long) */
330 32, /* bitsize */
331 FALSE, /* pc_relative */
332 0, /* bitpos */
99059e56
RM		 333 complain_overflow_bitfield,/* complain_on_overflow */
334 bfd_elf_generic_reloc, /* special_function */
335 "R_ARM_TLS_DTPMOD32", /* name */
336 TRUE, /* partial_inplace */
337 0xffffffff, /* src_mask */
338 0xffffffff, /* dst_mask */
07d6d2b8 339 FALSE), /* pcrel_offset */
7f266840 340
ba93b8ac 341 HOWTO (R_ARM_TLS_DTPOFF32, /* type */
07d6d2b8
AM		 342 0, /* rightshift */
343 2, /* size (0 = byte, 1 = short, 2 = long) */
344 32, /* bitsize */
345 FALSE, /* pc_relative */
346 0, /* bitpos */
99059e56
RM		 347 complain_overflow_bitfield,/* complain_on_overflow */
348 bfd_elf_generic_reloc, /* special_function */
349 "R_ARM_TLS_DTPOFF32", /* name */
350 TRUE, /* partial_inplace */
351 0xffffffff, /* src_mask */
352 0xffffffff, /* dst_mask */
07d6d2b8 353 FALSE), /* pcrel_offset */
7f266840 354
ba93b8ac 355 HOWTO (R_ARM_TLS_TPOFF32, /* type */
07d6d2b8
AM		 356 0, /* rightshift */
357 2, /* size (0 = byte, 1 = short, 2 = long) */
358 32, /* bitsize */
359 FALSE, /* pc_relative */
360 0, /* bitpos */
99059e56
RM		 361 complain_overflow_bitfield,/* complain_on_overflow */
362 bfd_elf_generic_reloc, /* special_function */
363 "R_ARM_TLS_TPOFF32", /* name */
364 TRUE, /* partial_inplace */
365 0xffffffff, /* src_mask */
366 0xffffffff, /* dst_mask */
07d6d2b8 367 FALSE), /* pcrel_offset */
7f266840
DJ		 368
369 /* Relocs used in ARM Linux */
370
371 HOWTO (R_ARM_COPY, /* type */
07d6d2b8
AM		 372 0, /* rightshift */
373 2, /* size (0 = byte, 1 = short, 2 = long) */
374 32, /* bitsize */
375 FALSE, /* pc_relative */
376 0, /* bitpos */
99059e56
RM		 377 complain_overflow_bitfield,/* complain_on_overflow */
378 bfd_elf_generic_reloc, /* special_function */
379 "R_ARM_COPY", /* name */
380 TRUE, /* partial_inplace */
381 0xffffffff, /* src_mask */
382 0xffffffff, /* dst_mask */
07d6d2b8 383 FALSE), /* pcrel_offset */
7f266840
DJ		 384
385 HOWTO (R_ARM_GLOB_DAT, /* type */
07d6d2b8
AM		 386 0, /* rightshift */
387 2, /* size (0 = byte, 1 = short, 2 = long) */
388 32, /* bitsize */
389 FALSE, /* pc_relative */
390 0, /* bitpos */
99059e56
RM		 391 complain_overflow_bitfield,/* complain_on_overflow */
392 bfd_elf_generic_reloc, /* special_function */
393 "R_ARM_GLOB_DAT", /* name */
394 TRUE, /* partial_inplace */
395 0xffffffff, /* src_mask */
396 0xffffffff, /* dst_mask */
07d6d2b8 397 FALSE), /* pcrel_offset */
7f266840
DJ		 398
399 HOWTO (R_ARM_JUMP_SLOT, /* type */
07d6d2b8
AM		 400 0, /* rightshift */
401 2, /* size (0 = byte, 1 = short, 2 = long) */
402 32, /* bitsize */
403 FALSE, /* pc_relative */
404 0, /* bitpos */
99059e56
RM		 405 complain_overflow_bitfield,/* complain_on_overflow */
406 bfd_elf_generic_reloc, /* special_function */
407 "R_ARM_JUMP_SLOT", /* name */
408 TRUE, /* partial_inplace */
409 0xffffffff, /* src_mask */
410 0xffffffff, /* dst_mask */
07d6d2b8 411 FALSE), /* pcrel_offset */
7f266840
DJ		 412
413 HOWTO (R_ARM_RELATIVE, /* type */
07d6d2b8
AM		 414 0, /* rightshift */
415 2, /* size (0 = byte, 1 = short, 2 = long) */
416 32, /* bitsize */
417 FALSE, /* pc_relative */
418 0, /* bitpos */
99059e56
RM		 419 complain_overflow_bitfield,/* complain_on_overflow */
420 bfd_elf_generic_reloc, /* special_function */
421 "R_ARM_RELATIVE", /* name */
422 TRUE, /* partial_inplace */
423 0xffffffff, /* src_mask */
424 0xffffffff, /* dst_mask */
07d6d2b8 425 FALSE), /* pcrel_offset */
7f266840 426
c19d1205 427 HOWTO (R_ARM_GOTOFF32, /* type */
07d6d2b8
AM		 428 0, /* rightshift */
429 2, /* size (0 = byte, 1 = short, 2 = long) */
430 32, /* bitsize */
431 FALSE, /* pc_relative */
432 0, /* bitpos */
99059e56
RM		 433 complain_overflow_bitfield,/* complain_on_overflow */
434 bfd_elf_generic_reloc, /* special_function */
435 "R_ARM_GOTOFF32", /* name */
436 TRUE, /* partial_inplace */
437 0xffffffff, /* src_mask */
438 0xffffffff, /* dst_mask */
07d6d2b8 439 FALSE), /* pcrel_offset */
7f266840
DJ		 440
441 HOWTO (R_ARM_GOTPC, /* type */
07d6d2b8
AM		 442 0, /* rightshift */
443 2, /* size (0 = byte, 1 = short, 2 = long) */
444 32, /* bitsize */
99059e56 445 TRUE, /* pc_relative */
07d6d2b8 446 0, /* bitpos */
99059e56
RM		 447 complain_overflow_bitfield,/* complain_on_overflow */
448 bfd_elf_generic_reloc, /* special_function */
449 "R_ARM_GOTPC", /* name */
450 TRUE, /* partial_inplace */
451 0xffffffff, /* src_mask */
452 0xffffffff, /* dst_mask */
453 TRUE), /* pcrel_offset */
7f266840
DJ		 454
455 HOWTO (R_ARM_GOT32, /* type */
07d6d2b8
AM		 456 0, /* rightshift */
457 2, /* size (0 = byte, 1 = short, 2 = long) */
458 32, /* bitsize */
99059e56 459 FALSE, /* pc_relative */
07d6d2b8 460 0, /* bitpos */
99059e56
RM		 461 complain_overflow_bitfield,/* complain_on_overflow */
462 bfd_elf_generic_reloc, /* special_function */
463 "R_ARM_GOT32", /* name */
464 TRUE, /* partial_inplace */
465 0xffffffff, /* src_mask */
466 0xffffffff, /* dst_mask */
467 FALSE), /* pcrel_offset */
7f266840
DJ		 468
469 HOWTO (R_ARM_PLT32, /* type */
07d6d2b8
AM		 470 2, /* rightshift */
471 2, /* size (0 = byte, 1 = short, 2 = long) */
472 24, /* bitsize */
99059e56 473 TRUE, /* pc_relative */
07d6d2b8 474 0, /* bitpos */
99059e56
RM		 475 complain_overflow_bitfield,/* complain_on_overflow */
476 bfd_elf_generic_reloc, /* special_function */
477 "R_ARM_PLT32", /* name */
478 FALSE, /* partial_inplace */
479 0x00ffffff, /* src_mask */
480 0x00ffffff, /* dst_mask */
481 TRUE), /* pcrel_offset */
7f266840
DJ		 482
483 HOWTO (R_ARM_CALL, /* type */
484 2, /* rightshift */
485 2, /* size (0 = byte, 1 = short, 2 = long) */
486 24, /* bitsize */
487 TRUE, /* pc_relative */
488 0, /* bitpos */
489 complain_overflow_signed,/* complain_on_overflow */
490 bfd_elf_generic_reloc, /* special_function */
491 "R_ARM_CALL", /* name */
492 FALSE, /* partial_inplace */
493 0x00ffffff, /* src_mask */
494 0x00ffffff, /* dst_mask */
495 TRUE), /* pcrel_offset */
496
497 HOWTO (R_ARM_JUMP24, /* type */
498 2, /* rightshift */
499 2, /* size (0 = byte, 1 = short, 2 = long) */
500 24, /* bitsize */
501 TRUE, /* pc_relative */
502 0, /* bitpos */
503 complain_overflow_signed,/* complain_on_overflow */
504 bfd_elf_generic_reloc, /* special_function */
505 "R_ARM_JUMP24", /* name */
506 FALSE, /* partial_inplace */
507 0x00ffffff, /* src_mask */
508 0x00ffffff, /* dst_mask */
509 TRUE), /* pcrel_offset */
510
c19d1205
ZW		 511 HOWTO (R_ARM_THM_JUMP24, /* type */
512 1, /* rightshift */
513 2, /* size (0 = byte, 1 = short, 2 = long) */
514 24, /* bitsize */
515 TRUE, /* pc_relative */
7f266840 516 0, /* bitpos */
c19d1205 517 complain_overflow_signed,/* complain_on_overflow */
7f266840 518 bfd_elf_generic_reloc, /* special_function */
c19d1205 519 "R_ARM_THM_JUMP24", /* name */
7f266840 520 FALSE, /* partial_inplace */
c19d1205
ZW		 521 0x07ff2fff, /* src_mask */
522 0x07ff2fff, /* dst_mask */
523 TRUE), /* pcrel_offset */
7f266840 524
c19d1205 525 HOWTO (R_ARM_BASE_ABS, /* type */
7f266840 526 0, /* rightshift */
c19d1205
ZW		 527 2, /* size (0 = byte, 1 = short, 2 = long) */
528 32, /* bitsize */
7f266840
DJ		 529 FALSE, /* pc_relative */
530 0, /* bitpos */
531 complain_overflow_dont,/* complain_on_overflow */
532 bfd_elf_generic_reloc, /* special_function */
c19d1205 533 "R_ARM_BASE_ABS", /* name */
7f266840 534 FALSE, /* partial_inplace */
c19d1205
ZW		 535 0xffffffff, /* src_mask */
536 0xffffffff, /* dst_mask */
7f266840
DJ		 537 FALSE), /* pcrel_offset */
538
539 HOWTO (R_ARM_ALU_PCREL7_0, /* type */
540 0, /* rightshift */
541 2, /* size (0 = byte, 1 = short, 2 = long) */
542 12, /* bitsize */
543 TRUE, /* pc_relative */
544 0, /* bitpos */
545 complain_overflow_dont,/* complain_on_overflow */
546 bfd_elf_generic_reloc, /* special_function */
547 "R_ARM_ALU_PCREL_7_0", /* name */
548 FALSE, /* partial_inplace */
549 0x00000fff, /* src_mask */
550 0x00000fff, /* dst_mask */
551 TRUE), /* pcrel_offset */
552
553 HOWTO (R_ARM_ALU_PCREL15_8, /* type */
554 0, /* rightshift */
555 2, /* size (0 = byte, 1 = short, 2 = long) */
556 12, /* bitsize */
557 TRUE, /* pc_relative */
558 8, /* bitpos */
559 complain_overflow_dont,/* complain_on_overflow */
560 bfd_elf_generic_reloc, /* special_function */
561 "R_ARM_ALU_PCREL_15_8",/* name */
562 FALSE, /* partial_inplace */
563 0x00000fff, /* src_mask */
564 0x00000fff, /* dst_mask */
565 TRUE), /* pcrel_offset */
566
567 HOWTO (R_ARM_ALU_PCREL23_15, /* type */
568 0, /* rightshift */
569 2, /* size (0 = byte, 1 = short, 2 = long) */
570 12, /* bitsize */
571 TRUE, /* pc_relative */
572 16, /* bitpos */
573 complain_overflow_dont,/* complain_on_overflow */
574 bfd_elf_generic_reloc, /* special_function */
575 "R_ARM_ALU_PCREL_23_15",/* name */
576 FALSE, /* partial_inplace */
577 0x00000fff, /* src_mask */
578 0x00000fff, /* dst_mask */
579 TRUE), /* pcrel_offset */
580
581 HOWTO (R_ARM_LDR_SBREL_11_0, /* type */
582 0, /* rightshift */
583 2, /* size (0 = byte, 1 = short, 2 = long) */
584 12, /* bitsize */
585 FALSE, /* pc_relative */
586 0, /* bitpos */
587 complain_overflow_dont,/* complain_on_overflow */
588 bfd_elf_generic_reloc, /* special_function */
589 "R_ARM_LDR_SBREL_11_0",/* name */
590 FALSE, /* partial_inplace */
591 0x00000fff, /* src_mask */
592 0x00000fff, /* dst_mask */
593 FALSE), /* pcrel_offset */
594
595 HOWTO (R_ARM_ALU_SBREL_19_12, /* type */
596 0, /* rightshift */
597 2, /* size (0 = byte, 1 = short, 2 = long) */
598 8, /* bitsize */
599 FALSE, /* pc_relative */
600 12, /* bitpos */
601 complain_overflow_dont,/* complain_on_overflow */
602 bfd_elf_generic_reloc, /* special_function */
603 "R_ARM_ALU_SBREL_19_12",/* name */
604 FALSE, /* partial_inplace */
605 0x000ff000, /* src_mask */
606 0x000ff000, /* dst_mask */
607 FALSE), /* pcrel_offset */
608
609 HOWTO (R_ARM_ALU_SBREL_27_20, /* type */
610 0, /* rightshift */
611 2, /* size (0 = byte, 1 = short, 2 = long) */
612 8, /* bitsize */
613 FALSE, /* pc_relative */
614 20, /* bitpos */
615 complain_overflow_dont,/* complain_on_overflow */
616 bfd_elf_generic_reloc, /* special_function */
617 "R_ARM_ALU_SBREL_27_20",/* name */
618 FALSE, /* partial_inplace */
619 0x0ff00000, /* src_mask */
620 0x0ff00000, /* dst_mask */
621 FALSE), /* pcrel_offset */
622
623 HOWTO (R_ARM_TARGET1, /* type */
624 0, /* rightshift */
625 2, /* size (0 = byte, 1 = short, 2 = long) */
626 32, /* bitsize */
627 FALSE, /* pc_relative */
628 0, /* bitpos */
629 complain_overflow_dont,/* complain_on_overflow */
630 bfd_elf_generic_reloc, /* special_function */
631 "R_ARM_TARGET1", /* name */
632 FALSE, /* partial_inplace */
633 0xffffffff, /* src_mask */
634 0xffffffff, /* dst_mask */
635 FALSE), /* pcrel_offset */
636
637 HOWTO (R_ARM_ROSEGREL32, /* type */
638 0, /* rightshift */
639 2, /* size (0 = byte, 1 = short, 2 = long) */
640 32, /* bitsize */
641 FALSE, /* pc_relative */
642 0, /* bitpos */
643 complain_overflow_dont,/* complain_on_overflow */
644 bfd_elf_generic_reloc, /* special_function */
645 "R_ARM_ROSEGREL32", /* name */
646 FALSE, /* partial_inplace */
647 0xffffffff, /* src_mask */
648 0xffffffff, /* dst_mask */
649 FALSE), /* pcrel_offset */
650
651 HOWTO (R_ARM_V4BX, /* type */
652 0, /* rightshift */
653 2, /* size (0 = byte, 1 = short, 2 = long) */
654 32, /* bitsize */
655 FALSE, /* pc_relative */
656 0, /* bitpos */
657 complain_overflow_dont,/* complain_on_overflow */
658 bfd_elf_generic_reloc, /* special_function */
659 "R_ARM_V4BX", /* name */
660 FALSE, /* partial_inplace */
661 0xffffffff, /* src_mask */
662 0xffffffff, /* dst_mask */
663 FALSE), /* pcrel_offset */
664
665 HOWTO (R_ARM_TARGET2, /* type */
666 0, /* rightshift */
667 2, /* size (0 = byte, 1 = short, 2 = long) */
668 32, /* bitsize */
669 FALSE, /* pc_relative */
670 0, /* bitpos */
671 complain_overflow_signed,/* complain_on_overflow */
672 bfd_elf_generic_reloc, /* special_function */
673 "R_ARM_TARGET2", /* name */
674 FALSE, /* partial_inplace */
675 0xffffffff, /* src_mask */
676 0xffffffff, /* dst_mask */
677 TRUE), /* pcrel_offset */
678
679 HOWTO (R_ARM_PREL31, /* type */
680 0, /* rightshift */
681 2, /* size (0 = byte, 1 = short, 2 = long) */
682 31, /* bitsize */
683 TRUE, /* pc_relative */
684 0, /* bitpos */
685 complain_overflow_signed,/* complain_on_overflow */
686 bfd_elf_generic_reloc, /* special_function */
687 "R_ARM_PREL31", /* name */
688 FALSE, /* partial_inplace */
689 0x7fffffff, /* src_mask */
690 0x7fffffff, /* dst_mask */
691 TRUE), /* pcrel_offset */
c19d1205
ZW		 692
693 HOWTO (R_ARM_MOVW_ABS_NC, /* type */
694 0, /* rightshift */
695 2, /* size (0 = byte, 1 = short, 2 = long) */
696 16, /* bitsize */
697 FALSE, /* pc_relative */
698 0, /* bitpos */
699 complain_overflow_dont,/* complain_on_overflow */
700 bfd_elf_generic_reloc, /* special_function */
701 "R_ARM_MOVW_ABS_NC", /* name */
702 FALSE, /* partial_inplace */
39623e12
PB		 703 0x000f0fff, /* src_mask */
704 0x000f0fff, /* dst_mask */
c19d1205
ZW		 705 FALSE), /* pcrel_offset */
706
707 HOWTO (R_ARM_MOVT_ABS, /* type */
708 0, /* rightshift */
709 2, /* size (0 = byte, 1 = short, 2 = long) */
710 16, /* bitsize */
711 FALSE, /* pc_relative */
712 0, /* bitpos */
713 complain_overflow_bitfield,/* complain_on_overflow */
714 bfd_elf_generic_reloc, /* special_function */
715 "R_ARM_MOVT_ABS", /* name */
716 FALSE, /* partial_inplace */
39623e12
PB		 717 0x000f0fff, /* src_mask */
718 0x000f0fff, /* dst_mask */
c19d1205
ZW		 719 FALSE), /* pcrel_offset */
720
721 HOWTO (R_ARM_MOVW_PREL_NC, /* type */
722 0, /* rightshift */
723 2, /* size (0 = byte, 1 = short, 2 = long) */
724 16, /* bitsize */
725 TRUE, /* pc_relative */
726 0, /* bitpos */
727 complain_overflow_dont,/* complain_on_overflow */
728 bfd_elf_generic_reloc, /* special_function */
729 "R_ARM_MOVW_PREL_NC", /* name */
730 FALSE, /* partial_inplace */
39623e12
PB		 731 0x000f0fff, /* src_mask */
732 0x000f0fff, /* dst_mask */
c19d1205
ZW		 733 TRUE), /* pcrel_offset */
734
735 HOWTO (R_ARM_MOVT_PREL, /* type */
736 0, /* rightshift */
737 2, /* size (0 = byte, 1 = short, 2 = long) */
738 16, /* bitsize */
739 TRUE, /* pc_relative */
740 0, /* bitpos */
741 complain_overflow_bitfield,/* complain_on_overflow */
742 bfd_elf_generic_reloc, /* special_function */
743 "R_ARM_MOVT_PREL", /* name */
744 FALSE, /* partial_inplace */
39623e12
PB		 745 0x000f0fff, /* src_mask */
746 0x000f0fff, /* dst_mask */
c19d1205
ZW		 747 TRUE), /* pcrel_offset */
748
749 HOWTO (R_ARM_THM_MOVW_ABS_NC, /* type */
750 0, /* rightshift */
751 2, /* size (0 = byte, 1 = short, 2 = long) */
752 16, /* bitsize */
753 FALSE, /* pc_relative */
754 0, /* bitpos */
755 complain_overflow_dont,/* complain_on_overflow */
756 bfd_elf_generic_reloc, /* special_function */
757 "R_ARM_THM_MOVW_ABS_NC",/* name */
758 FALSE, /* partial_inplace */
759 0x040f70ff, /* src_mask */
760 0x040f70ff, /* dst_mask */
761 FALSE), /* pcrel_offset */
762
763 HOWTO (R_ARM_THM_MOVT_ABS, /* type */
764 0, /* rightshift */
765 2, /* size (0 = byte, 1 = short, 2 = long) */
766 16, /* bitsize */
767 FALSE, /* pc_relative */
768 0, /* bitpos */
769 complain_overflow_bitfield,/* complain_on_overflow */
770 bfd_elf_generic_reloc, /* special_function */
771 "R_ARM_THM_MOVT_ABS", /* name */
772 FALSE, /* partial_inplace */
773 0x040f70ff, /* src_mask */
774 0x040f70ff, /* dst_mask */
775 FALSE), /* pcrel_offset */
776
777 HOWTO (R_ARM_THM_MOVW_PREL_NC,/* type */
778 0, /* rightshift */
779 2, /* size (0 = byte, 1 = short, 2 = long) */
780 16, /* bitsize */
781 TRUE, /* pc_relative */
782 0, /* bitpos */
783 complain_overflow_dont,/* complain_on_overflow */
784 bfd_elf_generic_reloc, /* special_function */
785 "R_ARM_THM_MOVW_PREL_NC",/* name */
786 FALSE, /* partial_inplace */
787 0x040f70ff, /* src_mask */
788 0x040f70ff, /* dst_mask */
789 TRUE), /* pcrel_offset */
790
791 HOWTO (R_ARM_THM_MOVT_PREL, /* type */
792 0, /* rightshift */
793 2, /* size (0 = byte, 1 = short, 2 = long) */
794 16, /* bitsize */
795 TRUE, /* pc_relative */
796 0, /* bitpos */
797 complain_overflow_bitfield,/* complain_on_overflow */
798 bfd_elf_generic_reloc, /* special_function */
799 "R_ARM_THM_MOVT_PREL", /* name */
800 FALSE, /* partial_inplace */
801 0x040f70ff, /* src_mask */
802 0x040f70ff, /* dst_mask */
803 TRUE), /* pcrel_offset */
804
805 HOWTO (R_ARM_THM_JUMP19, /* type */
806 1, /* rightshift */
807 2, /* size (0 = byte, 1 = short, 2 = long) */
808 19, /* bitsize */
809 TRUE, /* pc_relative */
810 0, /* bitpos */
811 complain_overflow_signed,/* complain_on_overflow */
812 bfd_elf_generic_reloc, /* special_function */
813 "R_ARM_THM_JUMP19", /* name */
814 FALSE, /* partial_inplace */
815 0x043f2fff, /* src_mask */
816 0x043f2fff, /* dst_mask */
817 TRUE), /* pcrel_offset */
818
819 HOWTO (R_ARM_THM_JUMP6, /* type */
820 1, /* rightshift */
821 1, /* size (0 = byte, 1 = short, 2 = long) */
822 6, /* bitsize */
823 TRUE, /* pc_relative */
824 0, /* bitpos */
825 complain_overflow_unsigned,/* complain_on_overflow */
826 bfd_elf_generic_reloc, /* special_function */
827 "R_ARM_THM_JUMP6", /* name */
828 FALSE, /* partial_inplace */
829 0x02f8, /* src_mask */
830 0x02f8, /* dst_mask */
831 TRUE), /* pcrel_offset */
832
833 /* These are declared as 13-bit signed relocations because we can
834 address -4095 .. 4095(base) by altering ADDW to SUBW or vice
835 versa. */
836 HOWTO (R_ARM_THM_ALU_PREL_11_0,/* type */
837 0, /* rightshift */
838 2, /* size (0 = byte, 1 = short, 2 = long) */
839 13, /* bitsize */
840 TRUE, /* pc_relative */
841 0, /* bitpos */
2cab6cc3 842 complain_overflow_dont,/* complain_on_overflow */
c19d1205
ZW		 843 bfd_elf_generic_reloc, /* special_function */
844 "R_ARM_THM_ALU_PREL_11_0",/* name */
845 FALSE, /* partial_inplace */
2cab6cc3
MS		 846 0xffffffff, /* src_mask */
847 0xffffffff, /* dst_mask */
c19d1205
ZW		 848 TRUE), /* pcrel_offset */
849
850 HOWTO (R_ARM_THM_PC12, /* type */
851 0, /* rightshift */
852 2, /* size (0 = byte, 1 = short, 2 = long) */
853 13, /* bitsize */
854 TRUE, /* pc_relative */
855 0, /* bitpos */
2cab6cc3 856 complain_overflow_dont,/* complain_on_overflow */
c19d1205
ZW		 857 bfd_elf_generic_reloc, /* special_function */
858 "R_ARM_THM_PC12", /* name */
859 FALSE, /* partial_inplace */
2cab6cc3
MS		 860 0xffffffff, /* src_mask */
861 0xffffffff, /* dst_mask */
c19d1205
ZW		 862 TRUE), /* pcrel_offset */
863
864 HOWTO (R_ARM_ABS32_NOI, /* type */
865 0, /* rightshift */
866 2, /* size (0 = byte, 1 = short, 2 = long) */
867 32, /* bitsize */
868 FALSE, /* pc_relative */
869 0, /* bitpos */
870 complain_overflow_dont,/* complain_on_overflow */
871 bfd_elf_generic_reloc, /* special_function */
872 "R_ARM_ABS32_NOI", /* name */
873 FALSE, /* partial_inplace */
874 0xffffffff, /* src_mask */
875 0xffffffff, /* dst_mask */
876 FALSE), /* pcrel_offset */
877
878 HOWTO (R_ARM_REL32_NOI, /* type */
879 0, /* rightshift */
880 2, /* size (0 = byte, 1 = short, 2 = long) */
881 32, /* bitsize */
882 TRUE, /* pc_relative */
883 0, /* bitpos */
884 complain_overflow_dont,/* complain_on_overflow */
885 bfd_elf_generic_reloc, /* special_function */
886 "R_ARM_REL32_NOI", /* name */
887 FALSE, /* partial_inplace */
888 0xffffffff, /* src_mask */
889 0xffffffff, /* dst_mask */
890 FALSE), /* pcrel_offset */
7f266840 891
4962c51a
MS		 892 /* Group relocations. */
893
894 HOWTO (R_ARM_ALU_PC_G0_NC, /* type */
895 0, /* rightshift */
896 2, /* size (0 = byte, 1 = short, 2 = long) */
897 32, /* bitsize */
898 TRUE, /* pc_relative */
899 0, /* bitpos */
900 complain_overflow_dont,/* complain_on_overflow */
901 bfd_elf_generic_reloc, /* special_function */
902 "R_ARM_ALU_PC_G0_NC", /* name */
903 FALSE, /* partial_inplace */
904 0xffffffff, /* src_mask */
905 0xffffffff, /* dst_mask */
906 TRUE), /* pcrel_offset */
907
07d6d2b8 908 HOWTO (R_ARM_ALU_PC_G0, /* type */
4962c51a
MS		 909 0, /* rightshift */
910 2, /* size (0 = byte, 1 = short, 2 = long) */
911 32, /* bitsize */
912 TRUE, /* pc_relative */
913 0, /* bitpos */
914 complain_overflow_dont,/* complain_on_overflow */
915 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 916 "R_ARM_ALU_PC_G0", /* name */
4962c51a
MS		 917 FALSE, /* partial_inplace */
918 0xffffffff, /* src_mask */
919 0xffffffff, /* dst_mask */
920 TRUE), /* pcrel_offset */
921
922 HOWTO (R_ARM_ALU_PC_G1_NC, /* type */
923 0, /* rightshift */
924 2, /* size (0 = byte, 1 = short, 2 = long) */
925 32, /* bitsize */
926 TRUE, /* pc_relative */
927 0, /* bitpos */
928 complain_overflow_dont,/* complain_on_overflow */
929 bfd_elf_generic_reloc, /* special_function */
930 "R_ARM_ALU_PC_G1_NC", /* name */
931 FALSE, /* partial_inplace */
932 0xffffffff, /* src_mask */
933 0xffffffff, /* dst_mask */
934 TRUE), /* pcrel_offset */
935
07d6d2b8 936 HOWTO (R_ARM_ALU_PC_G1, /* type */
4962c51a
MS		 937 0, /* rightshift */
938 2, /* size (0 = byte, 1 = short, 2 = long) */
939 32, /* bitsize */
940 TRUE, /* pc_relative */
941 0, /* bitpos */
942 complain_overflow_dont,/* complain_on_overflow */
943 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 944 "R_ARM_ALU_PC_G1", /* name */
4962c51a
MS		 945 FALSE, /* partial_inplace */
946 0xffffffff, /* src_mask */
947 0xffffffff, /* dst_mask */
948 TRUE), /* pcrel_offset */
949
07d6d2b8 950 HOWTO (R_ARM_ALU_PC_G2, /* type */
4962c51a
MS		 951 0, /* rightshift */
952 2, /* size (0 = byte, 1 = short, 2 = long) */
953 32, /* bitsize */
954 TRUE, /* pc_relative */
955 0, /* bitpos */
956 complain_overflow_dont,/* complain_on_overflow */
957 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 958 "R_ARM_ALU_PC_G2", /* name */
4962c51a
MS		 959 FALSE, /* partial_inplace */
960 0xffffffff, /* src_mask */
961 0xffffffff, /* dst_mask */
962 TRUE), /* pcrel_offset */
963
07d6d2b8 964 HOWTO (R_ARM_LDR_PC_G1, /* type */
4962c51a
MS		 965 0, /* rightshift */
966 2, /* size (0 = byte, 1 = short, 2 = long) */
967 32, /* bitsize */
968 TRUE, /* pc_relative */
969 0, /* bitpos */
970 complain_overflow_dont,/* complain_on_overflow */
971 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 972 "R_ARM_LDR_PC_G1", /* name */
4962c51a
MS		 973 FALSE, /* partial_inplace */
974 0xffffffff, /* src_mask */
975 0xffffffff, /* dst_mask */
976 TRUE), /* pcrel_offset */
977
07d6d2b8 978 HOWTO (R_ARM_LDR_PC_G2, /* type */
4962c51a
MS		 979 0, /* rightshift */
980 2, /* size (0 = byte, 1 = short, 2 = long) */
981 32, /* bitsize */
982 TRUE, /* pc_relative */
983 0, /* bitpos */
984 complain_overflow_dont,/* complain_on_overflow */
985 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 986 "R_ARM_LDR_PC_G2", /* name */
4962c51a
MS		 987 FALSE, /* partial_inplace */
988 0xffffffff, /* src_mask */
989 0xffffffff, /* dst_mask */
990 TRUE), /* pcrel_offset */
991
07d6d2b8 992 HOWTO (R_ARM_LDRS_PC_G0, /* type */
4962c51a
MS		 993 0, /* rightshift */
994 2, /* size (0 = byte, 1 = short, 2 = long) */
995 32, /* bitsize */
996 TRUE, /* pc_relative */
997 0, /* bitpos */
998 complain_overflow_dont,/* complain_on_overflow */
999 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1000 "R_ARM_LDRS_PC_G0", /* name */
4962c51a
MS		 1001 FALSE, /* partial_inplace */
1002 0xffffffff, /* src_mask */
1003 0xffffffff, /* dst_mask */
1004 TRUE), /* pcrel_offset */
1005
07d6d2b8 1006 HOWTO (R_ARM_LDRS_PC_G1, /* type */
4962c51a
MS		 1007 0, /* rightshift */
1008 2, /* size (0 = byte, 1 = short, 2 = long) */
1009 32, /* bitsize */
1010 TRUE, /* pc_relative */
1011 0, /* bitpos */
1012 complain_overflow_dont,/* complain_on_overflow */
1013 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1014 "R_ARM_LDRS_PC_G1", /* name */
4962c51a
MS		 1015 FALSE, /* partial_inplace */
1016 0xffffffff, /* src_mask */
1017 0xffffffff, /* dst_mask */
1018 TRUE), /* pcrel_offset */
1019
07d6d2b8 1020 HOWTO (R_ARM_LDRS_PC_G2, /* type */
4962c51a
MS		 1021 0, /* rightshift */
1022 2, /* size (0 = byte, 1 = short, 2 = long) */
1023 32, /* bitsize */
1024 TRUE, /* pc_relative */
1025 0, /* bitpos */
1026 complain_overflow_dont,/* complain_on_overflow */
1027 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1028 "R_ARM_LDRS_PC_G2", /* name */
4962c51a
MS		 1029 FALSE, /* partial_inplace */
1030 0xffffffff, /* src_mask */
1031 0xffffffff, /* dst_mask */
1032 TRUE), /* pcrel_offset */
1033
07d6d2b8 1034 HOWTO (R_ARM_LDC_PC_G0, /* type */
4962c51a
MS		 1035 0, /* rightshift */
1036 2, /* size (0 = byte, 1 = short, 2 = long) */
1037 32, /* bitsize */
1038 TRUE, /* pc_relative */
1039 0, /* bitpos */
1040 complain_overflow_dont,/* complain_on_overflow */
1041 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1042 "R_ARM_LDC_PC_G0", /* name */
4962c51a
MS		 1043 FALSE, /* partial_inplace */
1044 0xffffffff, /* src_mask */
1045 0xffffffff, /* dst_mask */
1046 TRUE), /* pcrel_offset */
1047
07d6d2b8 1048 HOWTO (R_ARM_LDC_PC_G1, /* type */
4962c51a
MS		 1049 0, /* rightshift */
1050 2, /* size (0 = byte, 1 = short, 2 = long) */
1051 32, /* bitsize */
1052 TRUE, /* pc_relative */
1053 0, /* bitpos */
1054 complain_overflow_dont,/* complain_on_overflow */
1055 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1056 "R_ARM_LDC_PC_G1", /* name */
4962c51a
MS		 1057 FALSE, /* partial_inplace */
1058 0xffffffff, /* src_mask */
1059 0xffffffff, /* dst_mask */
1060 TRUE), /* pcrel_offset */
1061
07d6d2b8 1062 HOWTO (R_ARM_LDC_PC_G2, /* type */
4962c51a
MS		 1063 0, /* rightshift */
1064 2, /* size (0 = byte, 1 = short, 2 = long) */
1065 32, /* bitsize */
1066 TRUE, /* pc_relative */
1067 0, /* bitpos */
1068 complain_overflow_dont,/* complain_on_overflow */
1069 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1070 "R_ARM_LDC_PC_G2", /* name */
4962c51a
MS		 1071 FALSE, /* partial_inplace */
1072 0xffffffff, /* src_mask */
1073 0xffffffff, /* dst_mask */
1074 TRUE), /* pcrel_offset */
1075
07d6d2b8 1076 HOWTO (R_ARM_ALU_SB_G0_NC, /* type */
4962c51a
MS		 1077 0, /* rightshift */
1078 2, /* size (0 = byte, 1 = short, 2 = long) */
1079 32, /* bitsize */
1080 TRUE, /* pc_relative */
1081 0, /* bitpos */
1082 complain_overflow_dont,/* complain_on_overflow */
1083 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1084 "R_ARM_ALU_SB_G0_NC", /* name */
4962c51a
MS		 1085 FALSE, /* partial_inplace */
1086 0xffffffff, /* src_mask */
1087 0xffffffff, /* dst_mask */
1088 TRUE), /* pcrel_offset */
1089
07d6d2b8 1090 HOWTO (R_ARM_ALU_SB_G0, /* type */
4962c51a
MS		 1091 0, /* rightshift */
1092 2, /* size (0 = byte, 1 = short, 2 = long) */
1093 32, /* bitsize */
1094 TRUE, /* pc_relative */
1095 0, /* bitpos */
1096 complain_overflow_dont,/* complain_on_overflow */
1097 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1098 "R_ARM_ALU_SB_G0", /* name */
4962c51a
MS		 1099 FALSE, /* partial_inplace */
1100 0xffffffff, /* src_mask */
1101 0xffffffff, /* dst_mask */
1102 TRUE), /* pcrel_offset */
1103
07d6d2b8 1104 HOWTO (R_ARM_ALU_SB_G1_NC, /* type */
4962c51a
MS		 1105 0, /* rightshift */
1106 2, /* size (0 = byte, 1 = short, 2 = long) */
1107 32, /* bitsize */
1108 TRUE, /* pc_relative */
1109 0, /* bitpos */
1110 complain_overflow_dont,/* complain_on_overflow */
1111 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1112 "R_ARM_ALU_SB_G1_NC", /* name */
4962c51a
MS		 1113 FALSE, /* partial_inplace */
1114 0xffffffff, /* src_mask */
1115 0xffffffff, /* dst_mask */
1116 TRUE), /* pcrel_offset */
1117
07d6d2b8 1118 HOWTO (R_ARM_ALU_SB_G1, /* type */
4962c51a
MS		 1119 0, /* rightshift */
1120 2, /* size (0 = byte, 1 = short, 2 = long) */
1121 32, /* bitsize */
1122 TRUE, /* pc_relative */
1123 0, /* bitpos */
1124 complain_overflow_dont,/* complain_on_overflow */
1125 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1126 "R_ARM_ALU_SB_G1", /* name */
4962c51a
MS		 1127 FALSE, /* partial_inplace */
1128 0xffffffff, /* src_mask */
1129 0xffffffff, /* dst_mask */
1130 TRUE), /* pcrel_offset */
1131
07d6d2b8 1132 HOWTO (R_ARM_ALU_SB_G2, /* type */
4962c51a
MS		 1133 0, /* rightshift */
1134 2, /* size (0 = byte, 1 = short, 2 = long) */
1135 32, /* bitsize */
1136 TRUE, /* pc_relative */
1137 0, /* bitpos */
1138 complain_overflow_dont,/* complain_on_overflow */
1139 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1140 "R_ARM_ALU_SB_G2", /* name */
4962c51a
MS		 1141 FALSE, /* partial_inplace */
1142 0xffffffff, /* src_mask */
1143 0xffffffff, /* dst_mask */
1144 TRUE), /* pcrel_offset */
1145
07d6d2b8 1146 HOWTO (R_ARM_LDR_SB_G0, /* type */
4962c51a
MS		 1147 0, /* rightshift */
1148 2, /* size (0 = byte, 1 = short, 2 = long) */
1149 32, /* bitsize */
1150 TRUE, /* pc_relative */
1151 0, /* bitpos */
1152 complain_overflow_dont,/* complain_on_overflow */
1153 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1154 "R_ARM_LDR_SB_G0", /* name */
4962c51a
MS		 1155 FALSE, /* partial_inplace */
1156 0xffffffff, /* src_mask */
1157 0xffffffff, /* dst_mask */
1158 TRUE), /* pcrel_offset */
1159
07d6d2b8 1160 HOWTO (R_ARM_LDR_SB_G1, /* type */
4962c51a
MS		 1161 0, /* rightshift */
1162 2, /* size (0 = byte, 1 = short, 2 = long) */
1163 32, /* bitsize */
1164 TRUE, /* pc_relative */
1165 0, /* bitpos */
1166 complain_overflow_dont,/* complain_on_overflow */
1167 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1168 "R_ARM_LDR_SB_G1", /* name */
4962c51a
MS		 1169 FALSE, /* partial_inplace */
1170 0xffffffff, /* src_mask */
1171 0xffffffff, /* dst_mask */
1172 TRUE), /* pcrel_offset */
1173
07d6d2b8 1174 HOWTO (R_ARM_LDR_SB_G2, /* type */
4962c51a
MS		 1175 0, /* rightshift */
1176 2, /* size (0 = byte, 1 = short, 2 = long) */
1177 32, /* bitsize */
1178 TRUE, /* pc_relative */
1179 0, /* bitpos */
1180 complain_overflow_dont,/* complain_on_overflow */
1181 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1182 "R_ARM_LDR_SB_G2", /* name */
4962c51a
MS		 1183 FALSE, /* partial_inplace */
1184 0xffffffff, /* src_mask */
1185 0xffffffff, /* dst_mask */
1186 TRUE), /* pcrel_offset */
1187
07d6d2b8 1188 HOWTO (R_ARM_LDRS_SB_G0, /* type */
4962c51a
MS		 1189 0, /* rightshift */
1190 2, /* size (0 = byte, 1 = short, 2 = long) */
1191 32, /* bitsize */
1192 TRUE, /* pc_relative */
1193 0, /* bitpos */
1194 complain_overflow_dont,/* complain_on_overflow */
1195 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1196 "R_ARM_LDRS_SB_G0", /* name */
4962c51a
MS		 1197 FALSE, /* partial_inplace */
1198 0xffffffff, /* src_mask */
1199 0xffffffff, /* dst_mask */
1200 TRUE), /* pcrel_offset */
1201
07d6d2b8 1202 HOWTO (R_ARM_LDRS_SB_G1, /* type */
4962c51a
MS		 1203 0, /* rightshift */
1204 2, /* size (0 = byte, 1 = short, 2 = long) */
1205 32, /* bitsize */
1206 TRUE, /* pc_relative */
1207 0, /* bitpos */
1208 complain_overflow_dont,/* complain_on_overflow */
1209 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1210 "R_ARM_LDRS_SB_G1", /* name */
4962c51a
MS		 1211 FALSE, /* partial_inplace */
1212 0xffffffff, /* src_mask */
1213 0xffffffff, /* dst_mask */
1214 TRUE), /* pcrel_offset */
1215
07d6d2b8 1216 HOWTO (R_ARM_LDRS_SB_G2, /* type */
4962c51a
MS		 1217 0, /* rightshift */
1218 2, /* size (0 = byte, 1 = short, 2 = long) */
1219 32, /* bitsize */
1220 TRUE, /* pc_relative */
1221 0, /* bitpos */
1222 complain_overflow_dont,/* complain_on_overflow */
1223 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1224 "R_ARM_LDRS_SB_G2", /* name */
4962c51a
MS		 1225 FALSE, /* partial_inplace */
1226 0xffffffff, /* src_mask */
1227 0xffffffff, /* dst_mask */
1228 TRUE), /* pcrel_offset */
1229
07d6d2b8 1230 HOWTO (R_ARM_LDC_SB_G0, /* type */
4962c51a
MS		 1231 0, /* rightshift */
1232 2, /* size (0 = byte, 1 = short, 2 = long) */
1233 32, /* bitsize */
1234 TRUE, /* pc_relative */
1235 0, /* bitpos */
1236 complain_overflow_dont,/* complain_on_overflow */
1237 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1238 "R_ARM_LDC_SB_G0", /* name */
4962c51a
MS		 1239 FALSE, /* partial_inplace */
1240 0xffffffff, /* src_mask */
1241 0xffffffff, /* dst_mask */
1242 TRUE), /* pcrel_offset */
1243
07d6d2b8 1244 HOWTO (R_ARM_LDC_SB_G1, /* type */
4962c51a
MS		 1245 0, /* rightshift */
1246 2, /* size (0 = byte, 1 = short, 2 = long) */
1247 32, /* bitsize */
1248 TRUE, /* pc_relative */
1249 0, /* bitpos */
1250 complain_overflow_dont,/* complain_on_overflow */
1251 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1252 "R_ARM_LDC_SB_G1", /* name */
4962c51a
MS		 1253 FALSE, /* partial_inplace */
1254 0xffffffff, /* src_mask */
1255 0xffffffff, /* dst_mask */
1256 TRUE), /* pcrel_offset */
1257
07d6d2b8 1258 HOWTO (R_ARM_LDC_SB_G2, /* type */
4962c51a
MS		 1259 0, /* rightshift */
1260 2, /* size (0 = byte, 1 = short, 2 = long) */
1261 32, /* bitsize */
1262 TRUE, /* pc_relative */
1263 0, /* bitpos */
1264 complain_overflow_dont,/* complain_on_overflow */
1265 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1266 "R_ARM_LDC_SB_G2", /* name */
4962c51a
MS		 1267 FALSE, /* partial_inplace */
1268 0xffffffff, /* src_mask */
1269 0xffffffff, /* dst_mask */
1270 TRUE), /* pcrel_offset */
1271
1272 /* End of group relocations. */
c19d1205 1273
c19d1205
ZW		 1274 HOWTO (R_ARM_MOVW_BREL_NC, /* type */
1275 0, /* rightshift */
1276 2, /* size (0 = byte, 1 = short, 2 = long) */
1277 16, /* bitsize */
1278 FALSE, /* pc_relative */
1279 0, /* bitpos */
1280 complain_overflow_dont,/* complain_on_overflow */
1281 bfd_elf_generic_reloc, /* special_function */
1282 "R_ARM_MOVW_BREL_NC", /* name */
1283 FALSE, /* partial_inplace */
1284 0x0000ffff, /* src_mask */
1285 0x0000ffff, /* dst_mask */
1286 FALSE), /* pcrel_offset */
1287
1288 HOWTO (R_ARM_MOVT_BREL, /* type */
1289 0, /* rightshift */
1290 2, /* size (0 = byte, 1 = short, 2 = long) */
1291 16, /* bitsize */
1292 FALSE, /* pc_relative */
1293 0, /* bitpos */
1294 complain_overflow_bitfield,/* complain_on_overflow */
1295 bfd_elf_generic_reloc, /* special_function */
1296 "R_ARM_MOVT_BREL", /* name */
1297 FALSE, /* partial_inplace */
1298 0x0000ffff, /* src_mask */
1299 0x0000ffff, /* dst_mask */
1300 FALSE), /* pcrel_offset */
1301
1302 HOWTO (R_ARM_MOVW_BREL, /* type */
1303 0, /* rightshift */
1304 2, /* size (0 = byte, 1 = short, 2 = long) */
1305 16, /* bitsize */
1306 FALSE, /* pc_relative */
1307 0, /* bitpos */
1308 complain_overflow_dont,/* complain_on_overflow */
1309 bfd_elf_generic_reloc, /* special_function */
1310 "R_ARM_MOVW_BREL", /* name */
1311 FALSE, /* partial_inplace */
1312 0x0000ffff, /* src_mask */
1313 0x0000ffff, /* dst_mask */
1314 FALSE), /* pcrel_offset */
1315
1316 HOWTO (R_ARM_THM_MOVW_BREL_NC,/* type */
1317 0, /* rightshift */
1318 2, /* size (0 = byte, 1 = short, 2 = long) */
1319 16, /* bitsize */
1320 FALSE, /* pc_relative */
1321 0, /* bitpos */
1322 complain_overflow_dont,/* complain_on_overflow */
1323 bfd_elf_generic_reloc, /* special_function */
1324 "R_ARM_THM_MOVW_BREL_NC",/* name */
1325 FALSE, /* partial_inplace */
1326 0x040f70ff, /* src_mask */
1327 0x040f70ff, /* dst_mask */
1328 FALSE), /* pcrel_offset */
1329
1330 HOWTO (R_ARM_THM_MOVT_BREL, /* type */
1331 0, /* rightshift */
1332 2, /* size (0 = byte, 1 = short, 2 = long) */
1333 16, /* bitsize */
1334 FALSE, /* pc_relative */
1335 0, /* bitpos */
1336 complain_overflow_bitfield,/* complain_on_overflow */
1337 bfd_elf_generic_reloc, /* special_function */
1338 "R_ARM_THM_MOVT_BREL", /* name */
1339 FALSE, /* partial_inplace */
1340 0x040f70ff, /* src_mask */
1341 0x040f70ff, /* dst_mask */
1342 FALSE), /* pcrel_offset */
1343
1344 HOWTO (R_ARM_THM_MOVW_BREL, /* type */
1345 0, /* rightshift */
1346 2, /* size (0 = byte, 1 = short, 2 = long) */
1347 16, /* bitsize */
1348 FALSE, /* pc_relative */
1349 0, /* bitpos */
1350 complain_overflow_dont,/* complain_on_overflow */
1351 bfd_elf_generic_reloc, /* special_function */
1352 "R_ARM_THM_MOVW_BREL", /* name */
1353 FALSE, /* partial_inplace */
1354 0x040f70ff, /* src_mask */
1355 0x040f70ff, /* dst_mask */
1356 FALSE), /* pcrel_offset */
1357
0855e32b
NS		 1358 HOWTO (R_ARM_TLS_GOTDESC, /* type */
1359 0, /* rightshift */
1360 2, /* size (0 = byte, 1 = short, 2 = long) */
1361 32, /* bitsize */
1362 FALSE, /* pc_relative */
1363 0, /* bitpos */
1364 complain_overflow_bitfield,/* complain_on_overflow */
1365 NULL, /* special_function */
1366 "R_ARM_TLS_GOTDESC", /* name */
1367 TRUE, /* partial_inplace */
1368 0xffffffff, /* src_mask */
1369 0xffffffff, /* dst_mask */
1370 FALSE), /* pcrel_offset */
1371
1372 HOWTO (R_ARM_TLS_CALL, /* type */
1373 0, /* rightshift */
1374 2, /* size (0 = byte, 1 = short, 2 = long) */
1375 24, /* bitsize */
1376 FALSE, /* pc_relative */
1377 0, /* bitpos */
1378 complain_overflow_dont,/* complain_on_overflow */
1379 bfd_elf_generic_reloc, /* special_function */
1380 "R_ARM_TLS_CALL", /* name */
1381 FALSE, /* partial_inplace */
1382 0x00ffffff, /* src_mask */
1383 0x00ffffff, /* dst_mask */
1384 FALSE), /* pcrel_offset */
1385
1386 HOWTO (R_ARM_TLS_DESCSEQ, /* type */
1387 0, /* rightshift */
1388 2, /* size (0 = byte, 1 = short, 2 = long) */
1389 0, /* bitsize */
1390 FALSE, /* pc_relative */
1391 0, /* bitpos */
1392 complain_overflow_bitfield,/* complain_on_overflow */
1393 bfd_elf_generic_reloc, /* special_function */
1394 "R_ARM_TLS_DESCSEQ", /* name */
1395 FALSE, /* partial_inplace */
1396 0x00000000, /* src_mask */
1397 0x00000000, /* dst_mask */
1398 FALSE), /* pcrel_offset */
1399
1400 HOWTO (R_ARM_THM_TLS_CALL, /* type */
1401 0, /* rightshift */
1402 2, /* size (0 = byte, 1 = short, 2 = long) */
1403 24, /* bitsize */
1404 FALSE, /* pc_relative */
1405 0, /* bitpos */
1406 complain_overflow_dont,/* complain_on_overflow */
1407 bfd_elf_generic_reloc, /* special_function */
1408 "R_ARM_THM_TLS_CALL", /* name */
1409 FALSE, /* partial_inplace */
1410 0x07ff07ff, /* src_mask */
1411 0x07ff07ff, /* dst_mask */
1412 FALSE), /* pcrel_offset */
c19d1205
ZW		 1413
1414 HOWTO (R_ARM_PLT32_ABS, /* type */
1415 0, /* rightshift */
1416 2, /* size (0 = byte, 1 = short, 2 = long) */
1417 32, /* bitsize */
1418 FALSE, /* pc_relative */
1419 0, /* bitpos */
1420 complain_overflow_dont,/* complain_on_overflow */
1421 bfd_elf_generic_reloc, /* special_function */
1422 "R_ARM_PLT32_ABS", /* name */
1423 FALSE, /* partial_inplace */
1424 0xffffffff, /* src_mask */
1425 0xffffffff, /* dst_mask */
1426 FALSE), /* pcrel_offset */
1427
1428 HOWTO (R_ARM_GOT_ABS, /* type */
1429 0, /* rightshift */
1430 2, /* size (0 = byte, 1 = short, 2 = long) */
1431 32, /* bitsize */
1432 FALSE, /* pc_relative */
1433 0, /* bitpos */
1434 complain_overflow_dont,/* complain_on_overflow */
1435 bfd_elf_generic_reloc, /* special_function */
1436 "R_ARM_GOT_ABS", /* name */
1437 FALSE, /* partial_inplace */
1438 0xffffffff, /* src_mask */
1439 0xffffffff, /* dst_mask */
1440 FALSE), /* pcrel_offset */
1441
1442 HOWTO (R_ARM_GOT_PREL, /* type */
1443 0, /* rightshift */
1444 2, /* size (0 = byte, 1 = short, 2 = long) */
1445 32, /* bitsize */
1446 TRUE, /* pc_relative */
1447 0, /* bitpos */
1448 complain_overflow_dont, /* complain_on_overflow */
1449 bfd_elf_generic_reloc, /* special_function */
1450 "R_ARM_GOT_PREL", /* name */
1451 FALSE, /* partial_inplace */
1452 0xffffffff, /* src_mask */
1453 0xffffffff, /* dst_mask */
1454 TRUE), /* pcrel_offset */
1455
1456 HOWTO (R_ARM_GOT_BREL12, /* type */
1457 0, /* rightshift */
1458 2, /* size (0 = byte, 1 = short, 2 = long) */
1459 12, /* bitsize */
1460 FALSE, /* pc_relative */
1461 0, /* bitpos */
1462 complain_overflow_bitfield,/* complain_on_overflow */
1463 bfd_elf_generic_reloc, /* special_function */
1464 "R_ARM_GOT_BREL12", /* name */
1465 FALSE, /* partial_inplace */
1466 0x00000fff, /* src_mask */
1467 0x00000fff, /* dst_mask */
1468 FALSE), /* pcrel_offset */
1469
1470 HOWTO (R_ARM_GOTOFF12, /* type */
1471 0, /* rightshift */
1472 2, /* size (0 = byte, 1 = short, 2 = long) */
1473 12, /* bitsize */
1474 FALSE, /* pc_relative */
1475 0, /* bitpos */
1476 complain_overflow_bitfield,/* complain_on_overflow */
1477 bfd_elf_generic_reloc, /* special_function */
1478 "R_ARM_GOTOFF12", /* name */
1479 FALSE, /* partial_inplace */
1480 0x00000fff, /* src_mask */
1481 0x00000fff, /* dst_mask */
1482 FALSE), /* pcrel_offset */
1483
07d6d2b8 1484 EMPTY_HOWTO (R_ARM_GOTRELAX), /* reserved for future GOT-load optimizations */
c19d1205
ZW		 1485
1486 /* GNU extension to record C++ vtable member usage */
07d6d2b8
AM		 1487 HOWTO (R_ARM_GNU_VTENTRY, /* type */
1488 0, /* rightshift */
1489 2, /* size (0 = byte, 1 = short, 2 = long) */
1490 0, /* bitsize */
1491 FALSE, /* pc_relative */
1492 0, /* bitpos */
99059e56 1493 complain_overflow_dont, /* complain_on_overflow */
07d6d2b8
AM		 1494 _bfd_elf_rel_vtable_reloc_fn, /* special_function */
1495 "R_ARM_GNU_VTENTRY", /* name */
1496 FALSE, /* partial_inplace */
1497 0, /* src_mask */
1498 0, /* dst_mask */
1499 FALSE), /* pcrel_offset */
c19d1205
ZW		 1500
1501 /* GNU extension to record C++ vtable hierarchy */
1502 HOWTO (R_ARM_GNU_VTINHERIT, /* type */
07d6d2b8
AM		 1503 0, /* rightshift */
1504 2, /* size (0 = byte, 1 = short, 2 = long) */
1505 0, /* bitsize */
1506 FALSE, /* pc_relative */
1507 0, /* bitpos */
99059e56 1508 complain_overflow_dont, /* complain_on_overflow */
07d6d2b8 1509 NULL, /* special_function */
99059e56 1510 "R_ARM_GNU_VTINHERIT", /* name */
07d6d2b8
AM		 1511 FALSE, /* partial_inplace */
1512 0, /* src_mask */
1513 0, /* dst_mask */
1514 FALSE), /* pcrel_offset */
c19d1205
ZW		 1515
1516 HOWTO (R_ARM_THM_JUMP11, /* type */
1517 1, /* rightshift */
1518 1, /* size (0 = byte, 1 = short, 2 = long) */
1519 11, /* bitsize */
1520 TRUE, /* pc_relative */
1521 0, /* bitpos */
1522 complain_overflow_signed, /* complain_on_overflow */
1523 bfd_elf_generic_reloc, /* special_function */
1524 "R_ARM_THM_JUMP11", /* name */
1525 FALSE, /* partial_inplace */
1526 0x000007ff, /* src_mask */
1527 0x000007ff, /* dst_mask */
1528 TRUE), /* pcrel_offset */
1529
1530 HOWTO (R_ARM_THM_JUMP8, /* type */
1531 1, /* rightshift */
1532 1, /* size (0 = byte, 1 = short, 2 = long) */
1533 8, /* bitsize */
1534 TRUE, /* pc_relative */
1535 0, /* bitpos */
1536 complain_overflow_signed, /* complain_on_overflow */
1537 bfd_elf_generic_reloc, /* special_function */
1538 "R_ARM_THM_JUMP8", /* name */
1539 FALSE, /* partial_inplace */
1540 0x000000ff, /* src_mask */
1541 0x000000ff, /* dst_mask */
1542 TRUE), /* pcrel_offset */
ba93b8ac 1543
c19d1205
ZW		 1544 /* TLS relocations */
1545 HOWTO (R_ARM_TLS_GD32, /* type */
07d6d2b8
AM		 1546 0, /* rightshift */
1547 2, /* size (0 = byte, 1 = short, 2 = long) */
1548 32, /* bitsize */
1549 FALSE, /* pc_relative */
1550 0, /* bitpos */
99059e56
RM		 1551 complain_overflow_bitfield,/* complain_on_overflow */
1552 NULL, /* special_function */
1553 "R_ARM_TLS_GD32", /* name */
1554 TRUE, /* partial_inplace */
1555 0xffffffff, /* src_mask */
1556 0xffffffff, /* dst_mask */
07d6d2b8 1557 FALSE), /* pcrel_offset */
ba93b8ac 1558
ba93b8ac 1559 HOWTO (R_ARM_TLS_LDM32, /* type */
07d6d2b8
AM		 1560 0, /* rightshift */
1561 2, /* size (0 = byte, 1 = short, 2 = long) */
1562 32, /* bitsize */
1563 FALSE, /* pc_relative */
1564 0, /* bitpos */
99059e56
RM		 1565 complain_overflow_bitfield,/* complain_on_overflow */
1566 bfd_elf_generic_reloc, /* special_function */
1567 "R_ARM_TLS_LDM32", /* name */
1568 TRUE, /* partial_inplace */
1569 0xffffffff, /* src_mask */
1570 0xffffffff, /* dst_mask */
07d6d2b8 1571 FALSE), /* pcrel_offset */
ba93b8ac 1572
c19d1205 1573 HOWTO (R_ARM_TLS_LDO32, /* type */
07d6d2b8
AM		 1574 0, /* rightshift */
1575 2, /* size (0 = byte, 1 = short, 2 = long) */
1576 32, /* bitsize */
1577 FALSE, /* pc_relative */
1578 0, /* bitpos */
99059e56
RM		 1579 complain_overflow_bitfield,/* complain_on_overflow */
1580 bfd_elf_generic_reloc, /* special_function */
1581 "R_ARM_TLS_LDO32", /* name */
1582 TRUE, /* partial_inplace */
1583 0xffffffff, /* src_mask */
1584 0xffffffff, /* dst_mask */
07d6d2b8 1585 FALSE), /* pcrel_offset */
ba93b8ac 1586
ba93b8ac 1587 HOWTO (R_ARM_TLS_IE32, /* type */
07d6d2b8
AM		 1588 0, /* rightshift */
1589 2, /* size (0 = byte, 1 = short, 2 = long) */
1590 32, /* bitsize */
1591 FALSE, /* pc_relative */
1592 0, /* bitpos */
99059e56
RM		 1593 complain_overflow_bitfield,/* complain_on_overflow */
1594 NULL, /* special_function */
1595 "R_ARM_TLS_IE32", /* name */
1596 TRUE, /* partial_inplace */
1597 0xffffffff, /* src_mask */
1598 0xffffffff, /* dst_mask */
07d6d2b8 1599 FALSE), /* pcrel_offset */
7f266840 1600
c19d1205 1601 HOWTO (R_ARM_TLS_LE32, /* type */
07d6d2b8
AM		 1602 0, /* rightshift */
1603 2, /* size (0 = byte, 1 = short, 2 = long) */
1604 32, /* bitsize */
1605 FALSE, /* pc_relative */
1606 0, /* bitpos */
99059e56 1607 complain_overflow_bitfield,/* complain_on_overflow */
07d6d2b8 1608 NULL, /* special_function */
99059e56
RM		 1609 "R_ARM_TLS_LE32", /* name */
1610 TRUE, /* partial_inplace */
1611 0xffffffff, /* src_mask */
1612 0xffffffff, /* dst_mask */
07d6d2b8 1613 FALSE), /* pcrel_offset */
7f266840 1614
c19d1205
ZW		 1615 HOWTO (R_ARM_TLS_LDO12, /* type */
1616 0, /* rightshift */
1617 2, /* size (0 = byte, 1 = short, 2 = long) */
1618 12, /* bitsize */
1619 FALSE, /* pc_relative */
7f266840 1620 0, /* bitpos */
c19d1205 1621 complain_overflow_bitfield,/* complain_on_overflow */
7f266840 1622 bfd_elf_generic_reloc, /* special_function */
c19d1205 1623 "R_ARM_TLS_LDO12", /* name */
7f266840 1624 FALSE, /* partial_inplace */
c19d1205
ZW		 1625 0x00000fff, /* src_mask */
1626 0x00000fff, /* dst_mask */
1627 FALSE), /* pcrel_offset */
7f266840 1628
c19d1205
ZW		 1629 HOWTO (R_ARM_TLS_LE12, /* type */
1630 0, /* rightshift */
1631 2, /* size (0 = byte, 1 = short, 2 = long) */
1632 12, /* bitsize */
1633 FALSE, /* pc_relative */
7f266840 1634 0, /* bitpos */
c19d1205 1635 complain_overflow_bitfield,/* complain_on_overflow */
7f266840 1636 bfd_elf_generic_reloc, /* special_function */
c19d1205 1637 "R_ARM_TLS_LE12", /* name */
7f266840 1638 FALSE, /* partial_inplace */
c19d1205
ZW		 1639 0x00000fff, /* src_mask */
1640 0x00000fff, /* dst_mask */
1641 FALSE), /* pcrel_offset */
7f266840 1642
c19d1205 1643 HOWTO (R_ARM_TLS_IE12GP, /* type */
7f266840
DJ		 1644 0, /* rightshift */
1645 2, /* size (0 = byte, 1 = short, 2 = long) */
c19d1205
ZW		 1646 12, /* bitsize */
1647 FALSE, /* pc_relative */
7f266840 1648 0, /* bitpos */
c19d1205 1649 complain_overflow_bitfield,/* complain_on_overflow */
7f266840 1650 bfd_elf_generic_reloc, /* special_function */
c19d1205 1651 "R_ARM_TLS_IE12GP", /* name */
7f266840 1652 FALSE, /* partial_inplace */
c19d1205
ZW		 1653 0x00000fff, /* src_mask */
1654 0x00000fff, /* dst_mask */
1655 FALSE), /* pcrel_offset */
0855e32b 1656
34e77a92 1657 /* 112-127 private relocations. */
0855e32b
NS		 1658 EMPTY_HOWTO (112),
1659 EMPTY_HOWTO (113),
1660 EMPTY_HOWTO (114),
1661 EMPTY_HOWTO (115),
1662 EMPTY_HOWTO (116),
1663 EMPTY_HOWTO (117),
1664 EMPTY_HOWTO (118),
1665 EMPTY_HOWTO (119),
1666 EMPTY_HOWTO (120),
1667 EMPTY_HOWTO (121),
1668 EMPTY_HOWTO (122),
1669 EMPTY_HOWTO (123),
1670 EMPTY_HOWTO (124),
1671 EMPTY_HOWTO (125),
1672 EMPTY_HOWTO (126),
1673 EMPTY_HOWTO (127),
34e77a92
RS		 1674
1675 /* R_ARM_ME_TOO, obsolete. */
0855e32b
NS		 1676 EMPTY_HOWTO (128),
1677
1678 HOWTO (R_ARM_THM_TLS_DESCSEQ, /* type */
1679 0, /* rightshift */
1680 1, /* size (0 = byte, 1 = short, 2 = long) */
1681 0, /* bitsize */
1682 FALSE, /* pc_relative */
1683 0, /* bitpos */
1684 complain_overflow_bitfield,/* complain_on_overflow */
1685 bfd_elf_generic_reloc, /* special_function */
1686 "R_ARM_THM_TLS_DESCSEQ",/* name */
1687 FALSE, /* partial_inplace */
1688 0x00000000, /* src_mask */
1689 0x00000000, /* dst_mask */
1690 FALSE), /* pcrel_offset */
72d98d16
MG		 1691 EMPTY_HOWTO (130),
1692 EMPTY_HOWTO (131),
1693 HOWTO (R_ARM_THM_ALU_ABS_G0_NC,/* type. */
1694 0, /* rightshift. */
1695 1, /* size (0 = byte, 1 = short, 2 = long). */
1696 16, /* bitsize. */
1697 FALSE, /* pc_relative. */
1698 0, /* bitpos. */
1699 complain_overflow_bitfield,/* complain_on_overflow. */
1700 bfd_elf_generic_reloc, /* special_function. */
1701 "R_ARM_THM_ALU_ABS_G0_NC",/* name. */
1702 FALSE, /* partial_inplace. */
1703 0x00000000, /* src_mask. */
1704 0x00000000, /* dst_mask. */
1705 FALSE), /* pcrel_offset. */
1706 HOWTO (R_ARM_THM_ALU_ABS_G1_NC,/* type. */
1707 0, /* rightshift. */
1708 1, /* size (0 = byte, 1 = short, 2 = long). */
1709 16, /* bitsize. */
1710 FALSE, /* pc_relative. */
1711 0, /* bitpos. */
1712 complain_overflow_bitfield,/* complain_on_overflow. */
1713 bfd_elf_generic_reloc, /* special_function. */
1714 "R_ARM_THM_ALU_ABS_G1_NC",/* name. */
1715 FALSE, /* partial_inplace. */
1716 0x00000000, /* src_mask. */
1717 0x00000000, /* dst_mask. */
1718 FALSE), /* pcrel_offset. */
1719 HOWTO (R_ARM_THM_ALU_ABS_G2_NC,/* type. */
1720 0, /* rightshift. */
1721 1, /* size (0 = byte, 1 = short, 2 = long). */
1722 16, /* bitsize. */
1723 FALSE, /* pc_relative. */
1724 0, /* bitpos. */
1725 complain_overflow_bitfield,/* complain_on_overflow. */
1726 bfd_elf_generic_reloc, /* special_function. */
1727 "R_ARM_THM_ALU_ABS_G2_NC",/* name. */
1728 FALSE, /* partial_inplace. */
1729 0x00000000, /* src_mask. */
1730 0x00000000, /* dst_mask. */
1731 FALSE), /* pcrel_offset. */
1732 HOWTO (R_ARM_THM_ALU_ABS_G3_NC,/* type. */
1733 0, /* rightshift. */
1734 1, /* size (0 = byte, 1 = short, 2 = long). */
1735 16, /* bitsize. */
1736 FALSE, /* pc_relative. */
1737 0, /* bitpos. */
1738 complain_overflow_bitfield,/* complain_on_overflow. */
1739 bfd_elf_generic_reloc, /* special_function. */
1740 "R_ARM_THM_ALU_ABS_G3_NC",/* name. */
1741 FALSE, /* partial_inplace. */
1742 0x00000000, /* src_mask. */
1743 0x00000000, /* dst_mask. */
1744 FALSE), /* pcrel_offset. */
e5d6e09e
AV		 1745 /* Relocations for Armv8.1-M Mainline. */
1746 HOWTO (R_ARM_THM_BF16, /* type. */
1747 0, /* rightshift. */
1748 1, /* size (0 = byte, 1 = short, 2 = long). */
1749 16, /* bitsize. */
1750 TRUE, /* pc_relative. */
1751 0, /* bitpos. */
1752 complain_overflow_dont,/* do not complain_on_overflow. */
1753 bfd_elf_generic_reloc, /* special_function. */
1754 "R_ARM_THM_BF16", /* name. */
1755 FALSE, /* partial_inplace. */
1756 0x001f0ffe, /* src_mask. */
1757 0x001f0ffe, /* dst_mask. */
1758 TRUE), /* pcrel_offset. */
1889da70
AV		 1759 HOWTO (R_ARM_THM_BF12, /* type. */
1760 0, /* rightshift. */
1761 1, /* size (0 = byte, 1 = short, 2 = long). */
1762 12, /* bitsize. */
1763 TRUE, /* pc_relative. */
1764 0, /* bitpos. */
1765 complain_overflow_dont,/* do not complain_on_overflow. */
1766 bfd_elf_generic_reloc, /* special_function. */
1767 "R_ARM_THM_BF12", /* name. */
1768 FALSE, /* partial_inplace. */
1769 0x00010ffe, /* src_mask. */
1770 0x00010ffe, /* dst_mask. */
1771 TRUE), /* pcrel_offset. */
1caf72a5
AV		 1772 HOWTO (R_ARM_THM_BF18, /* type. */
1773 0, /* rightshift. */
1774 1, /* size (0 = byte, 1 = short, 2 = long). */
1775 18, /* bitsize. */
1776 TRUE, /* pc_relative. */
1777 0, /* bitpos. */
1778 complain_overflow_dont,/* do not complain_on_overflow. */
1779 bfd_elf_generic_reloc, /* special_function. */
1780 "R_ARM_THM_BF18", /* name. */
1781 FALSE, /* partial_inplace. */
1782 0x007f0ffe, /* src_mask. */
1783 0x007f0ffe, /* dst_mask. */
1784 TRUE), /* pcrel_offset. */
c19d1205
ZW		 1785};
1786
34e77a92 1787/* 160 onwards: */
5c5a4843 1788static reloc_howto_type elf32_arm_howto_table_2[8] =
34e77a92
RS		 1789{
1790 HOWTO (R_ARM_IRELATIVE, /* type */
07d6d2b8
AM		 1791 0, /* rightshift */
1792 2, /* size (0 = byte, 1 = short, 2 = long) */
1793 32, /* bitsize */
1794 FALSE, /* pc_relative */
1795 0, /* bitpos */
99059e56
RM		 1796 complain_overflow_bitfield,/* complain_on_overflow */
1797 bfd_elf_generic_reloc, /* special_function */
1798 "R_ARM_IRELATIVE", /* name */
1799 TRUE, /* partial_inplace */
1800 0xffffffff, /* src_mask */
1801 0xffffffff, /* dst_mask */
188fd7ae
CL		 1802 FALSE), /* pcrel_offset */
1803 HOWTO (R_ARM_GOTFUNCDESC, /* type */
1804 0, /* rightshift */
1805 2, /* size (0 = byte, 1 = short, 2 = long) */
1806 32, /* bitsize */
1807 FALSE, /* pc_relative */
1808 0, /* bitpos */
1809 complain_overflow_bitfield,/* complain_on_overflow */
1810 bfd_elf_generic_reloc, /* special_function */
1811 "R_ARM_GOTFUNCDESC", /* name */
1812 FALSE, /* partial_inplace */
1813 0, /* src_mask */
1814 0xffffffff, /* dst_mask */
1815 FALSE), /* pcrel_offset */
1816 HOWTO (R_ARM_GOTOFFFUNCDESC, /* type */
1817 0, /* rightshift */
1818 2, /* size (0 = byte, 1 = short, 2 = long) */
1819 32, /* bitsize */
1820 FALSE, /* pc_relative */
1821 0, /* bitpos */
1822 complain_overflow_bitfield,/* complain_on_overflow */
1823 bfd_elf_generic_reloc, /* special_function */
1824 "R_ARM_GOTOFFFUNCDESC",/* name */
1825 FALSE, /* partial_inplace */
1826 0, /* src_mask */
1827 0xffffffff, /* dst_mask */
1828 FALSE), /* pcrel_offset */
1829 HOWTO (R_ARM_FUNCDESC, /* type */
1830 0, /* rightshift */
1831 2, /* size (0 = byte, 1 = short, 2 = long) */
1832 32, /* bitsize */
1833 FALSE, /* pc_relative */
1834 0, /* bitpos */
1835 complain_overflow_bitfield,/* complain_on_overflow */
1836 bfd_elf_generic_reloc, /* special_function */
1837 "R_ARM_FUNCDESC", /* name */
1838 FALSE, /* partial_inplace */
1839 0, /* src_mask */
1840 0xffffffff, /* dst_mask */
1841 FALSE), /* pcrel_offset */
1842 HOWTO (R_ARM_FUNCDESC_VALUE, /* type */
1843 0, /* rightshift */
1844 2, /* size (0 = byte, 1 = short, 2 = long) */
1845 64, /* bitsize */
1846 FALSE, /* pc_relative */
1847 0, /* bitpos */
1848 complain_overflow_bitfield,/* complain_on_overflow */
1849 bfd_elf_generic_reloc, /* special_function */
1850 "R_ARM_FUNCDESC_VALUE",/* name */
1851 FALSE, /* partial_inplace */
1852 0, /* src_mask */
1853 0xffffffff, /* dst_mask */
1854 FALSE), /* pcrel_offset */
5c5a4843
CL		 1855 HOWTO (R_ARM_TLS_GD32_FDPIC, /* type */
1856 0, /* rightshift */
1857 2, /* size (0 = byte, 1 = short, 2 = long) */
1858 32, /* bitsize */
1859 FALSE, /* pc_relative */
1860 0, /* bitpos */
1861 complain_overflow_bitfield,/* complain_on_overflow */
1862 bfd_elf_generic_reloc, /* special_function */
1863 "R_ARM_TLS_GD32_FDPIC",/* name */
1864 FALSE, /* partial_inplace */
1865 0, /* src_mask */
1866 0xffffffff, /* dst_mask */
1867 FALSE), /* pcrel_offset */
1868 HOWTO (R_ARM_TLS_LDM32_FDPIC, /* type */
1869 0, /* rightshift */
1870 2, /* size (0 = byte, 1 = short, 2 = long) */
1871 32, /* bitsize */
1872 FALSE, /* pc_relative */
1873 0, /* bitpos */
1874 complain_overflow_bitfield,/* complain_on_overflow */
1875 bfd_elf_generic_reloc, /* special_function */
1876 "R_ARM_TLS_LDM32_FDPIC",/* name */
1877 FALSE, /* partial_inplace */
1878 0, /* src_mask */
1879 0xffffffff, /* dst_mask */
1880 FALSE), /* pcrel_offset */
1881 HOWTO (R_ARM_TLS_IE32_FDPIC, /* type */
1882 0, /* rightshift */
1883 2, /* size (0 = byte, 1 = short, 2 = long) */
1884 32, /* bitsize */
1885 FALSE, /* pc_relative */
1886 0, /* bitpos */
1887 complain_overflow_bitfield,/* complain_on_overflow */
1888 bfd_elf_generic_reloc, /* special_function */
1889 "R_ARM_TLS_IE32_FDPIC",/* name */
1890 FALSE, /* partial_inplace */
1891 0, /* src_mask */
1892 0xffffffff, /* dst_mask */
1893 FALSE), /* pcrel_offset */
34e77a92 1894};
c19d1205 1895
34e77a92
RS		 1896/* 249-255 extended, currently unused, relocations: */
1897static reloc_howto_type elf32_arm_howto_table_3[4] =
7f266840
DJ		 1898{
1899 HOWTO (R_ARM_RREL32, /* type */
1900 0, /* rightshift */
1901 0, /* size (0 = byte, 1 = short, 2 = long) */
1902 0, /* bitsize */
1903 FALSE, /* pc_relative */
1904 0, /* bitpos */
1905 complain_overflow_dont,/* complain_on_overflow */
1906 bfd_elf_generic_reloc, /* special_function */
1907 "R_ARM_RREL32", /* name */
1908 FALSE, /* partial_inplace */
1909 0, /* src_mask */
1910 0, /* dst_mask */
1911 FALSE), /* pcrel_offset */
1912
1913 HOWTO (R_ARM_RABS32, /* type */
1914 0, /* rightshift */
1915 0, /* size (0 = byte, 1 = short, 2 = long) */
1916 0, /* bitsize */
1917 FALSE, /* pc_relative */
1918 0, /* bitpos */
1919 complain_overflow_dont,/* complain_on_overflow */
1920 bfd_elf_generic_reloc, /* special_function */
1921 "R_ARM_RABS32", /* name */
1922 FALSE, /* partial_inplace */
1923 0, /* src_mask */
1924 0, /* dst_mask */
1925 FALSE), /* pcrel_offset */
1926
1927 HOWTO (R_ARM_RPC24, /* type */
1928 0, /* rightshift */
1929 0, /* size (0 = byte, 1 = short, 2 = long) */
1930 0, /* bitsize */
1931 FALSE, /* pc_relative */
1932 0, /* bitpos */
1933 complain_overflow_dont,/* complain_on_overflow */
1934 bfd_elf_generic_reloc, /* special_function */
1935 "R_ARM_RPC24", /* name */
1936 FALSE, /* partial_inplace */
1937 0, /* src_mask */
1938 0, /* dst_mask */
1939 FALSE), /* pcrel_offset */
1940
1941 HOWTO (R_ARM_RBASE, /* type */
1942 0, /* rightshift */
1943 0, /* size (0 = byte, 1 = short, 2 = long) */
1944 0, /* bitsize */
1945 FALSE, /* pc_relative */
1946 0, /* bitpos */
1947 complain_overflow_dont,/* complain_on_overflow */
1948 bfd_elf_generic_reloc, /* special_function */
1949 "R_ARM_RBASE", /* name */
1950 FALSE, /* partial_inplace */
1951 0, /* src_mask */
1952 0, /* dst_mask */
1953 FALSE) /* pcrel_offset */
1954};
1955
1956static reloc_howto_type *
1957elf32_arm_howto_from_type (unsigned int r_type)
1958{
906e58ca 1959 if (r_type < ARRAY_SIZE (elf32_arm_howto_table_1))
c19d1205 1960 return &elf32_arm_howto_table_1[r_type];
ba93b8ac 1961
188fd7ae
CL		 1962 if (r_type >= R_ARM_IRELATIVE
1963 && r_type < R_ARM_IRELATIVE + ARRAY_SIZE (elf32_arm_howto_table_2))
34e77a92
RS		 1964 return &elf32_arm_howto_table_2[r_type - R_ARM_IRELATIVE];
1965
c19d1205 1966 if (r_type >= R_ARM_RREL32
34e77a92
RS		 1967 && r_type < R_ARM_RREL32 + ARRAY_SIZE (elf32_arm_howto_table_3))
1968 return &elf32_arm_howto_table_3[r_type - R_ARM_RREL32];
7f266840 1969
c19d1205 1970 return NULL;
7f266840
DJ		 1971}
1972
f3185997
NC		 1973static bfd_boolean
1974elf32_arm_info_to_howto (bfd * abfd, arelent * bfd_reloc,
7f266840
DJ		 1975 Elf_Internal_Rela * elf_reloc)
1976{
1977 unsigned int r_type;
1978
1979 r_type = ELF32_R_TYPE (elf_reloc->r_info);
f3185997
NC		 1980 if ((bfd_reloc->howto = elf32_arm_howto_from_type (r_type)) == NULL)
1981 {
1982 /* xgettext:c-format */
1983 _bfd_error_handler (_("%pB: unsupported relocation type %#x"),
1984 abfd, r_type);
1985 bfd_set_error (bfd_error_bad_value);
1986 return FALSE;
1987 }
1988 return TRUE;
7f266840
DJ		 1989}
1990
1991struct elf32_arm_reloc_map
1992 {
1993 bfd_reloc_code_real_type bfd_reloc_val;
07d6d2b8 1994 unsigned char elf_reloc_val;
7f266840
DJ		 1995 };
1996
1997/* All entries in this list must also be present in elf32_arm_howto_table. */
1998static const struct elf32_arm_reloc_map elf32_arm_reloc_map[] =
1999 {
07d6d2b8 2000 {BFD_RELOC_NONE, R_ARM_NONE},
7f266840 2001 {BFD_RELOC_ARM_PCREL_BRANCH, R_ARM_PC24},
39b41c9c
PB		 2002 {BFD_RELOC_ARM_PCREL_CALL, R_ARM_CALL},
2003 {BFD_RELOC_ARM_PCREL_JUMP, R_ARM_JUMP24},
07d6d2b8
AM		 2004 {BFD_RELOC_ARM_PCREL_BLX, R_ARM_XPC25},
2005 {BFD_RELOC_THUMB_PCREL_BLX, R_ARM_THM_XPC22},
2006 {BFD_RELOC_32, R_ARM_ABS32},
2007 {BFD_RELOC_32_PCREL, R_ARM_REL32},
2008 {BFD_RELOC_8, R_ARM_ABS8},
2009 {BFD_RELOC_16, R_ARM_ABS16},
2010 {BFD_RELOC_ARM_OFFSET_IMM, R_ARM_ABS12},
7f266840 2011 {BFD_RELOC_ARM_THUMB_OFFSET, R_ARM_THM_ABS5},
c19d1205
ZW		 2012 {BFD_RELOC_THUMB_PCREL_BRANCH25, R_ARM_THM_JUMP24},
2013 {BFD_RELOC_THUMB_PCREL_BRANCH23, R_ARM_THM_CALL},
2014 {BFD_RELOC_THUMB_PCREL_BRANCH12, R_ARM_THM_JUMP11},
2015 {BFD_RELOC_THUMB_PCREL_BRANCH20, R_ARM_THM_JUMP19},
2016 {BFD_RELOC_THUMB_PCREL_BRANCH9, R_ARM_THM_JUMP8},
2017 {BFD_RELOC_THUMB_PCREL_BRANCH7, R_ARM_THM_JUMP6},
07d6d2b8
AM		 2018 {BFD_RELOC_ARM_GLOB_DAT, R_ARM_GLOB_DAT},
2019 {BFD_RELOC_ARM_JUMP_SLOT, R_ARM_JUMP_SLOT},
2020 {BFD_RELOC_ARM_RELATIVE, R_ARM_RELATIVE},
2021 {BFD_RELOC_ARM_GOTOFF, R_ARM_GOTOFF32},
2022 {BFD_RELOC_ARM_GOTPC, R_ARM_GOTPC},
2023 {BFD_RELOC_ARM_GOT_PREL, R_ARM_GOT_PREL},
2024 {BFD_RELOC_ARM_GOT32, R_ARM_GOT32},
2025 {BFD_RELOC_ARM_PLT32, R_ARM_PLT32},
7f266840
DJ		 2026 {BFD_RELOC_ARM_TARGET1, R_ARM_TARGET1},
2027 {BFD_RELOC_ARM_ROSEGREL32, R_ARM_ROSEGREL32},
2028 {BFD_RELOC_ARM_SBREL32, R_ARM_SBREL32},
2029 {BFD_RELOC_ARM_PREL31, R_ARM_PREL31},
ba93b8ac 2030 {BFD_RELOC_ARM_TARGET2, R_ARM_TARGET2},
07d6d2b8
AM		 2031 {BFD_RELOC_ARM_PLT32, R_ARM_PLT32},
2032 {BFD_RELOC_ARM_TLS_GOTDESC, R_ARM_TLS_GOTDESC},
2033 {BFD_RELOC_ARM_TLS_CALL, R_ARM_TLS_CALL},
0855e32b 2034 {BFD_RELOC_ARM_THM_TLS_CALL, R_ARM_THM_TLS_CALL},
07d6d2b8 2035 {BFD_RELOC_ARM_TLS_DESCSEQ, R_ARM_TLS_DESCSEQ},
0855e32b 2036 {BFD_RELOC_ARM_THM_TLS_DESCSEQ, R_ARM_THM_TLS_DESCSEQ},
07d6d2b8 2037 {BFD_RELOC_ARM_TLS_DESC, R_ARM_TLS_DESC},
ba93b8ac
DJ		 2038 {BFD_RELOC_ARM_TLS_GD32, R_ARM_TLS_GD32},
2039 {BFD_RELOC_ARM_TLS_LDO32, R_ARM_TLS_LDO32},
2040 {BFD_RELOC_ARM_TLS_LDM32, R_ARM_TLS_LDM32},
2041 {BFD_RELOC_ARM_TLS_DTPMOD32, R_ARM_TLS_DTPMOD32},
2042 {BFD_RELOC_ARM_TLS_DTPOFF32, R_ARM_TLS_DTPOFF32},
07d6d2b8
AM		 2043 {BFD_RELOC_ARM_TLS_TPOFF32, R_ARM_TLS_TPOFF32},
2044 {BFD_RELOC_ARM_TLS_IE32, R_ARM_TLS_IE32},
2045 {BFD_RELOC_ARM_TLS_LE32, R_ARM_TLS_LE32},
2046 {BFD_RELOC_ARM_IRELATIVE, R_ARM_IRELATIVE},
188fd7ae
CL		 2047 {BFD_RELOC_ARM_GOTFUNCDESC, R_ARM_GOTFUNCDESC},
2048 {BFD_RELOC_ARM_GOTOFFFUNCDESC, R_ARM_GOTOFFFUNCDESC},
2049 {BFD_RELOC_ARM_FUNCDESC, R_ARM_FUNCDESC},
2050 {BFD_RELOC_ARM_FUNCDESC_VALUE, R_ARM_FUNCDESC_VALUE},
5c5a4843
CL		 2051 {BFD_RELOC_ARM_TLS_GD32_FDPIC, R_ARM_TLS_GD32_FDPIC},
2052 {BFD_RELOC_ARM_TLS_LDM32_FDPIC, R_ARM_TLS_LDM32_FDPIC},
2053 {BFD_RELOC_ARM_TLS_IE32_FDPIC, R_ARM_TLS_IE32_FDPIC},
c19d1205
ZW		 2054 {BFD_RELOC_VTABLE_INHERIT, R_ARM_GNU_VTINHERIT},
2055 {BFD_RELOC_VTABLE_ENTRY, R_ARM_GNU_VTENTRY},
b6895b4f
PB		 2056 {BFD_RELOC_ARM_MOVW, R_ARM_MOVW_ABS_NC},
2057 {BFD_RELOC_ARM_MOVT, R_ARM_MOVT_ABS},
2058 {BFD_RELOC_ARM_MOVW_PCREL, R_ARM_MOVW_PREL_NC},
2059 {BFD_RELOC_ARM_MOVT_PCREL, R_ARM_MOVT_PREL},
2060 {BFD_RELOC_ARM_THUMB_MOVW, R_ARM_THM_MOVW_ABS_NC},
2061 {BFD_RELOC_ARM_THUMB_MOVT, R_ARM_THM_MOVT_ABS},
2062 {BFD_RELOC_ARM_THUMB_MOVW_PCREL, R_ARM_THM_MOVW_PREL_NC},
2063 {BFD_RELOC_ARM_THUMB_MOVT_PCREL, R_ARM_THM_MOVT_PREL},
4962c51a
MS		 2064 {BFD_RELOC_ARM_ALU_PC_G0_NC, R_ARM_ALU_PC_G0_NC},
2065 {BFD_RELOC_ARM_ALU_PC_G0, R_ARM_ALU_PC_G0},
2066 {BFD_RELOC_ARM_ALU_PC_G1_NC, R_ARM_ALU_PC_G1_NC},
2067 {BFD_RELOC_ARM_ALU_PC_G1, R_ARM_ALU_PC_G1},
2068 {BFD_RELOC_ARM_ALU_PC_G2, R_ARM_ALU_PC_G2},
2069 {BFD_RELOC_ARM_LDR_PC_G0, R_ARM_LDR_PC_G0},
2070 {BFD_RELOC_ARM_LDR_PC_G1, R_ARM_LDR_PC_G1},
2071 {BFD_RELOC_ARM_LDR_PC_G2, R_ARM_LDR_PC_G2},
2072 {BFD_RELOC_ARM_LDRS_PC_G0, R_ARM_LDRS_PC_G0},
2073 {BFD_RELOC_ARM_LDRS_PC_G1, R_ARM_LDRS_PC_G1},
2074 {BFD_RELOC_ARM_LDRS_PC_G2, R_ARM_LDRS_PC_G2},
2075 {BFD_RELOC_ARM_LDC_PC_G0, R_ARM_LDC_PC_G0},
2076 {BFD_RELOC_ARM_LDC_PC_G1, R_ARM_LDC_PC_G1},
2077 {BFD_RELOC_ARM_LDC_PC_G2, R_ARM_LDC_PC_G2},
2078 {BFD_RELOC_ARM_ALU_SB_G0_NC, R_ARM_ALU_SB_G0_NC},
2079 {BFD_RELOC_ARM_ALU_SB_G0, R_ARM_ALU_SB_G0},
2080 {BFD_RELOC_ARM_ALU_SB_G1_NC, R_ARM_ALU_SB_G1_NC},
2081 {BFD_RELOC_ARM_ALU_SB_G1, R_ARM_ALU_SB_G1},
2082 {BFD_RELOC_ARM_ALU_SB_G2, R_ARM_ALU_SB_G2},
2083 {BFD_RELOC_ARM_LDR_SB_G0, R_ARM_LDR_SB_G0},
2084 {BFD_RELOC_ARM_LDR_SB_G1, R_ARM_LDR_SB_G1},
2085 {BFD_RELOC_ARM_LDR_SB_G2, R_ARM_LDR_SB_G2},
2086 {BFD_RELOC_ARM_LDRS_SB_G0, R_ARM_LDRS_SB_G0},
2087 {BFD_RELOC_ARM_LDRS_SB_G1, R_ARM_LDRS_SB_G1},
2088 {BFD_RELOC_ARM_LDRS_SB_G2, R_ARM_LDRS_SB_G2},
2089 {BFD_RELOC_ARM_LDC_SB_G0, R_ARM_LDC_SB_G0},
2090 {BFD_RELOC_ARM_LDC_SB_G1, R_ARM_LDC_SB_G1},
845b51d6 2091 {BFD_RELOC_ARM_LDC_SB_G2, R_ARM_LDC_SB_G2},
72d98d16
MG		 2092 {BFD_RELOC_ARM_V4BX, R_ARM_V4BX},
2093 {BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC, R_ARM_THM_ALU_ABS_G3_NC},
2094 {BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC, R_ARM_THM_ALU_ABS_G2_NC},
2095 {BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC, R_ARM_THM_ALU_ABS_G1_NC},
e5d6e09e 2096 {BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC, R_ARM_THM_ALU_ABS_G0_NC},
1caf72a5 2097 {BFD_RELOC_ARM_THUMB_BF17, R_ARM_THM_BF16},
1889da70 2098 {BFD_RELOC_ARM_THUMB_BF13, R_ARM_THM_BF12},
1caf72a5 2099 {BFD_RELOC_ARM_THUMB_BF19, R_ARM_THM_BF18}
7f266840
DJ		 2100 };
2101
2102static reloc_howto_type *
f1c71a59
ZW		 2103elf32_arm_reloc_type_lookup (bfd *abfd ATTRIBUTE_UNUSED,
2104 bfd_reloc_code_real_type code)
7f266840
DJ		 2105{
2106 unsigned int i;
8029a119 2107
906e58ca 2108 for (i = 0; i < ARRAY_SIZE (elf32_arm_reloc_map); i ++)
c19d1205
ZW		 2109 if (elf32_arm_reloc_map[i].bfd_reloc_val == code)
2110 return elf32_arm_howto_from_type (elf32_arm_reloc_map[i].elf_reloc_val);
7f266840 2111
c19d1205 2112 return NULL;
7f266840
DJ		 2113}
2114
157090f7
AM		 2115static reloc_howto_type *
2116elf32_arm_reloc_name_lookup (bfd *abfd ATTRIBUTE_UNUSED,
2117 const char *r_name)
2118{
2119 unsigned int i;
2120
906e58ca 2121 for (i = 0; i < ARRAY_SIZE (elf32_arm_howto_table_1); i++)
157090f7
AM		 2122 if (elf32_arm_howto_table_1[i].name != NULL
2123 && strcasecmp (elf32_arm_howto_table_1[i].name, r_name) == 0)
2124 return &elf32_arm_howto_table_1[i];
2125
906e58ca 2126 for (i = 0; i < ARRAY_SIZE (elf32_arm_howto_table_2); i++)
157090f7
AM		 2127 if (elf32_arm_howto_table_2[i].name != NULL
2128 && strcasecmp (elf32_arm_howto_table_2[i].name, r_name) == 0)
2129 return &elf32_arm_howto_table_2[i];
2130
34e77a92
RS		 2131 for (i = 0; i < ARRAY_SIZE (elf32_arm_howto_table_3); i++)
2132 if (elf32_arm_howto_table_3[i].name != NULL
2133 && strcasecmp (elf32_arm_howto_table_3[i].name, r_name) == 0)
2134 return &elf32_arm_howto_table_3[i];
2135
157090f7
AM		 2136 return NULL;
2137}
2138
906e58ca
NC		 2139/* Support for core dump NOTE sections. */
2140
7f266840 2141static bfd_boolean
f1c71a59 2142elf32_arm_nabi_grok_prstatus (bfd *abfd, Elf_Internal_Note *note)
7f266840
DJ		 2143{
2144 int offset;
2145 size_t size;
2146
2147 switch (note->descsz)
2148 {
2149 default:
2150 return FALSE;
2151
8029a119 2152 case 148: /* Linux/ARM 32-bit. */
7f266840 2153 /* pr_cursig */
228e534f 2154 elf_tdata (abfd)->core->signal = bfd_get_16 (abfd, note->descdata + 12);
7f266840
DJ		 2155
2156 /* pr_pid */
228e534f 2157 elf_tdata (abfd)->core->lwpid = bfd_get_32 (abfd, note->descdata + 24);
7f266840
DJ		 2158
2159 /* pr_reg */
2160 offset = 72;
2161 size = 72;
2162
2163 break;
2164 }
2165
2166 /* Make a ".reg/999" section. */
2167 return _bfd_elfcore_make_pseudosection (abfd, ".reg",
2168 size, note->descpos + offset);
2169}
2170
2171static bfd_boolean
f1c71a59 2172elf32_arm_nabi_grok_psinfo (bfd *abfd, Elf_Internal_Note *note)
7f266840
DJ		 2173{
2174 switch (note->descsz)
2175 {
2176 default:
2177 return FALSE;
2178
8029a119 2179 case 124: /* Linux/ARM elf_prpsinfo. */
228e534f 2180 elf_tdata (abfd)->core->pid
4395ee08 2181 = bfd_get_32 (abfd, note->descdata + 12);
228e534f 2182 elf_tdata (abfd)->core->program
7f266840 2183 = _bfd_elfcore_strndup (abfd, note->descdata + 28, 16);
228e534f 2184 elf_tdata (abfd)->core->command
7f266840
DJ		 2185 = _bfd_elfcore_strndup (abfd, note->descdata + 44, 80);
2186 }
2187
2188 /* Note that for some reason, a spurious space is tacked
2189 onto the end of the args in some (at least one anyway)
2190 implementations, so strip it off if it exists. */
7f266840 2191 {
228e534f 2192 char *command = elf_tdata (abfd)->core->command;
7f266840
DJ		 2193 int n = strlen (command);
2194
2195 if (0 < n && command[n - 1] == ' ')
2196 command[n - 1] = '\0';
2197 }
2198
2199 return TRUE;
2200}
2201
1f20dca5
UW		 2202static char *
2203elf32_arm_nabi_write_core_note (bfd *abfd, char *buf, int *bufsiz,
2204 int note_type, ...)
2205{
2206 switch (note_type)
2207 {
2208 default:
2209 return NULL;
2210
2211 case NT_PRPSINFO:
2212 {
602f1657 2213 char data[124] ATTRIBUTE_NONSTRING;
1f20dca5
UW		 2214 va_list ap;
2215
2216 va_start (ap, note_type);
2217 memset (data, 0, sizeof (data));
2218 strncpy (data + 28, va_arg (ap, const char *), 16);
be3e27bb 2219#if GCC_VERSION == 8000 || GCC_VERSION == 8001
95da9854 2220 DIAGNOSTIC_PUSH;
be3e27bb 2221 /* GCC 8.0 and 8.1 warn about 80 equals destination size with
95da9854
L		 2222 -Wstringop-truncation:
2223 https://gcc.gnu.org/bugzilla/show_bug.cgi?id=85643
2224 */
95da9854
L		 2225 DIAGNOSTIC_IGNORE_STRINGOP_TRUNCATION;
2226#endif
1f20dca5 2227 strncpy (data + 44, va_arg (ap, const char *), 80);
be3e27bb 2228#if GCC_VERSION == 8000 || GCC_VERSION == 8001
95da9854 2229 DIAGNOSTIC_POP;
fe75810f 2230#endif
1f20dca5
UW		 2231 va_end (ap);
2232
2233 return elfcore_write_note (abfd, buf, bufsiz,
2234 "CORE", note_type, data, sizeof (data));
2235 }
2236
2237 case NT_PRSTATUS:
2238 {
2239 char data[148];
2240 va_list ap;
2241 long pid;
2242 int cursig;
2243 const void *greg;
2244
2245 va_start (ap, note_type);
2246 memset (data, 0, sizeof (data));
2247 pid = va_arg (ap, long);
2248 bfd_put_32 (abfd, pid, data + 24);
2249 cursig = va_arg (ap, int);
2250 bfd_put_16 (abfd, cursig, data + 12);
2251 greg = va_arg (ap, const void *);
2252 memcpy (data + 72, greg, 72);
2253 va_end (ap);
2254
2255 return elfcore_write_note (abfd, buf, bufsiz,
2256 "CORE", note_type, data, sizeof (data));
2257 }
2258 }
2259}
2260
07d6d2b8
AM		 2261#define TARGET_LITTLE_SYM arm_elf32_le_vec
2262#define TARGET_LITTLE_NAME "elf32-littlearm"
2263#define TARGET_BIG_SYM arm_elf32_be_vec
2264#define TARGET_BIG_NAME "elf32-bigarm"
7f266840
DJ		 2265
2266#define elf_backend_grok_prstatus elf32_arm_nabi_grok_prstatus
2267#define elf_backend_grok_psinfo elf32_arm_nabi_grok_psinfo
1f20dca5 2268#define elf_backend_write_core_note elf32_arm_nabi_write_core_note
7f266840 2269
252b5132
RH		 2270typedef unsigned long int insn32;
2271typedef unsigned short int insn16;
2272
3a4a14e9
PB		 2273/* In lieu of proper flags, assume all EABIv4 or later objects are
2274 interworkable. */
57e8b36a 2275#define INTERWORK_FLAG(abfd) \
3a4a14e9 2276 (EF_ARM_EABI_VERSION (elf_elfheader (abfd)->e_flags) >= EF_ARM_EABI_VER4 \
3e6b1042
DJ		 2277 || (elf_elfheader (abfd)->e_flags & EF_ARM_INTERWORK) \
2278 || ((abfd)->flags & BFD_LINKER_CREATED))
9b485d32 2279
252b5132
RH		 2280/* The linker script knows the section names for placement.
2281 The entry_names are used to do simple name mangling on the stubs.
2282 Given a function name, and its type, the stub can be found. The
9b485d32 2283 name can be changed. The only requirement is the %s be present. */
252b5132
RH		 2284#define THUMB2ARM_GLUE_SECTION_NAME ".glue_7t"
2285#define THUMB2ARM_GLUE_ENTRY_NAME "__%s_from_thumb"
2286
2287#define ARM2THUMB_GLUE_SECTION_NAME ".glue_7"
2288#define ARM2THUMB_GLUE_ENTRY_NAME "__%s_from_arm"
2289
c7b8f16e
JB		 2290#define VFP11_ERRATUM_VENEER_SECTION_NAME ".vfp11_veneer"
2291#define VFP11_ERRATUM_VENEER_ENTRY_NAME "__vfp11_veneer_%x"
2292
a504d23a
LA		 2293#define STM32L4XX_ERRATUM_VENEER_SECTION_NAME ".text.stm32l4xx_veneer"
2294#define STM32L4XX_ERRATUM_VENEER_ENTRY_NAME "__stm32l4xx_veneer_%x"
2295
845b51d6
PB		 2296#define ARM_BX_GLUE_SECTION_NAME ".v4_bx"
2297#define ARM_BX_GLUE_ENTRY_NAME "__bx_r%d"
2298
7413f23f
DJ		 2299#define STUB_ENTRY_NAME "__%s_veneer"
2300
4ba2ef8f
TP		 2301#define CMSE_PREFIX "__acle_se_"
2302
4d83e8d9
CL		 2303#define CMSE_STUB_NAME ".gnu.sgstubs"
2304
252b5132
RH		 2305/* The name of the dynamic interpreter. This is put in the .interp
2306 section. */
2307#define ELF_DYNAMIC_INTERPRETER "/usr/lib/ld.so.1"
2308
cb10292c
CL		 2309/* FDPIC default stack size. */
2310#define DEFAULT_STACK_SIZE 0x8000
2311
0855e32b 2312static const unsigned long tls_trampoline [] =
b38cadfb
NC		 2313{
2314 0xe08e0000, /* add r0, lr, r0 */
2315 0xe5901004, /* ldr r1, [r0,#4] */
2316 0xe12fff11, /* bx r1 */
2317};
0855e32b
NS		 2318
2319static const unsigned long dl_tlsdesc_lazy_trampoline [] =
b38cadfb
NC		 2320{
2321 0xe52d2004, /* push {r2} */
2322 0xe59f200c, /* ldr r2, [pc, #3f - . - 8] */
2323 0xe59f100c, /* ldr r1, [pc, #4f - . - 8] */
2324 0xe79f2002, /* 1: ldr r2, [pc, r2] */
2325 0xe081100f, /* 2: add r1, pc */
2326 0xe12fff12, /* bx r2 */
2327 0x00000014, /* 3: .word _GLOBAL_OFFSET_TABLE_ - 1b - 8
99059e56 2328 + dl_tlsdesc_lazy_resolver(GOT) */
b38cadfb
NC		 2329 0x00000018, /* 4: .word _GLOBAL_OFFSET_TABLE_ - 2b - 8 */
2330};
0855e32b 2331
b4e87f2c
TC		 2332/* NOTE: [Thumb nop sequence]
2333 When adding code that transitions from Thumb to Arm the instruction that
2334 should be used for the alignment padding should be 0xe7fd (b .-2) instead of
2335 a nop for performance reasons. */
2336
7801f98f
CL		 2337/* ARM FDPIC PLT entry. */
2338/* The last 5 words contain PLT lazy fragment code and data. */
2339static const bfd_vma elf32_arm_fdpic_plt_entry [] =
2340 {
2341 0xe59fc008, /* ldr r12, .L1 */
2342 0xe08cc009, /* add r12, r12, r9 */
2343 0xe59c9004, /* ldr r9, [r12, #4] */
2344 0xe59cf000, /* ldr pc, [r12] */
2345 0x00000000, /* L1. .word foo(GOTOFFFUNCDESC) */
2346 0x00000000, /* L1. .word foo(funcdesc_value_reloc_offset) */
2347 0xe51fc00c, /* ldr r12, [pc, #-12] */
2348 0xe92d1000, /* push {r12} */
2349 0xe599c004, /* ldr r12, [r9, #4] */
2350 0xe599f000, /* ldr pc, [r9] */
2351 };
2352
59029f57
CL		 2353/* Thumb FDPIC PLT entry. */
2354/* The last 5 words contain PLT lazy fragment code and data. */
2355static const bfd_vma elf32_arm_fdpic_thumb_plt_entry [] =
2356 {
2357 0xc00cf8df, /* ldr.w r12, .L1 */
2358 0x0c09eb0c, /* add.w r12, r12, r9 */
2359 0x9004f8dc, /* ldr.w r9, [r12, #4] */
2360 0xf000f8dc, /* ldr.w pc, [r12] */
2361 0x00000000, /* .L1 .word foo(GOTOFFFUNCDESC) */
2362 0x00000000, /* .L2 .word foo(funcdesc_value_reloc_offset) */
2363 0xc008f85f, /* ldr.w r12, .L2 */
2364 0xcd04f84d, /* push {r12} */
2365 0xc004f8d9, /* ldr.w r12, [r9, #4] */
2366 0xf000f8d9, /* ldr.w pc, [r9] */
2367 };
2368
5e681ec4
PB		 2369#ifdef FOUR_WORD_PLT
2370
252b5132
RH		 2371/* The first entry in a procedure linkage table looks like
2372 this. It is set up so that any shared library function that is
59f2c4e7 2373 called before the relocation has been set up calls the dynamic
9b485d32 2374 linker first. */
e5a52504 2375static const bfd_vma elf32_arm_plt0_entry [] =
b38cadfb
NC		 2376{
2377 0xe52de004, /* str lr, [sp, #-4]! */
2378 0xe59fe010, /* ldr lr, [pc, #16] */
2379 0xe08fe00e, /* add lr, pc, lr */
2380 0xe5bef008, /* ldr pc, [lr, #8]! */
2381};
5e681ec4
PB		 2382
2383/* Subsequent entries in a procedure linkage table look like
2384 this. */
e5a52504 2385static const bfd_vma elf32_arm_plt_entry [] =
b38cadfb
NC		 2386{
2387 0xe28fc600, /* add ip, pc, #NN */
2388 0xe28cca00, /* add ip, ip, #NN */
2389 0xe5bcf000, /* ldr pc, [ip, #NN]! */
2390 0x00000000, /* unused */
2391};
5e681ec4 2392
eed94f8f 2393#else /* not FOUR_WORD_PLT */
5e681ec4 2394
5e681ec4
PB		 2395/* The first entry in a procedure linkage table looks like
2396 this. It is set up so that any shared library function that is
2397 called before the relocation has been set up calls the dynamic
2398 linker first. */
e5a52504 2399static const bfd_vma elf32_arm_plt0_entry [] =
b38cadfb 2400{
07d6d2b8
AM		 2401 0xe52de004, /* str lr, [sp, #-4]! */
2402 0xe59fe004, /* ldr lr, [pc, #4] */
2403 0xe08fe00e, /* add lr, pc, lr */
2404 0xe5bef008, /* ldr pc, [lr, #8]! */
2405 0x00000000, /* &GOT[0] - . */
b38cadfb 2406};
252b5132 2407
1db37fe6
YG		 2408/* By default subsequent entries in a procedure linkage table look like
2409 this. Offsets that don't fit into 28 bits will cause link error. */
2410static const bfd_vma elf32_arm_plt_entry_short [] =
b38cadfb
NC		 2411{
2412 0xe28fc600, /* add ip, pc, #0xNN00000 */
2413 0xe28cca00, /* add ip, ip, #0xNN000 */
2414 0xe5bcf000, /* ldr pc, [ip, #0xNNN]! */
2415};
5e681ec4 2416
1db37fe6
YG		 2417/* When explicitly asked, we'll use this "long" entry format
2418 which can cope with arbitrary displacements. */
2419static const bfd_vma elf32_arm_plt_entry_long [] =
2420{
07d6d2b8
AM		 2421 0xe28fc200, /* add ip, pc, #0xN0000000 */
2422 0xe28cc600, /* add ip, ip, #0xNN00000 */
1db37fe6
YG		 2423 0xe28cca00, /* add ip, ip, #0xNN000 */
2424 0xe5bcf000, /* ldr pc, [ip, #0xNNN]! */
2425};
2426
2427static bfd_boolean elf32_arm_use_long_plt_entry = FALSE;
2428
eed94f8f
NC		 2429#endif /* not FOUR_WORD_PLT */
2430
2431/* The first entry in a procedure linkage table looks like this.
2432 It is set up so that any shared library function that is called before the
2433 relocation has been set up calls the dynamic linker first. */
2434static const bfd_vma elf32_thumb2_plt0_entry [] =
2435{
2436 /* NOTE: As this is a mixture of 16-bit and 32-bit instructions,
2437 an instruction maybe encoded to one or two array elements. */
07d6d2b8
AM		 2438 0xf8dfb500, /* push {lr} */
2439 0x44fee008, /* ldr.w lr, [pc, #8] */
2440 /* add lr, pc */
eed94f8f 2441 0xff08f85e, /* ldr.w pc, [lr, #8]! */
07d6d2b8 2442 0x00000000, /* &GOT[0] - . */
eed94f8f
NC		 2443};
2444
2445/* Subsequent entries in a procedure linkage table for thumb only target
2446 look like this. */
2447static const bfd_vma elf32_thumb2_plt_entry [] =
2448{
2449 /* NOTE: As this is a mixture of 16-bit and 32-bit instructions,
2450 an instruction maybe encoded to one or two array elements. */
07d6d2b8
AM		 2451 0x0c00f240, /* movw ip, #0xNNNN */
2452 0x0c00f2c0, /* movt ip, #0xNNNN */
2453 0xf8dc44fc, /* add ip, pc */
b4e87f2c
TC		 2454 0xe7fdf000 /* ldr.w pc, [ip] */
2455 /* b .-2 */
eed94f8f 2456};
252b5132 2457
00a97672
RS		 2458/* The format of the first entry in the procedure linkage table
2459 for a VxWorks executable. */
2460static const bfd_vma elf32_arm_vxworks_exec_plt0_entry[] =
b38cadfb 2461{
07d6d2b8
AM		 2462 0xe52dc008, /* str ip,[sp,#-8]! */
2463 0xe59fc000, /* ldr ip,[pc] */
2464 0xe59cf008, /* ldr pc,[ip,#8] */
2465 0x00000000, /* .long _GLOBAL_OFFSET_TABLE_ */
b38cadfb 2466};
00a97672
RS		 2467
2468/* The format of subsequent entries in a VxWorks executable. */
2469static const bfd_vma elf32_arm_vxworks_exec_plt_entry[] =
b38cadfb 2470{
07d6d2b8
AM		 2471 0xe59fc000, /* ldr ip,[pc] */
2472 0xe59cf000, /* ldr pc,[ip] */
2473 0x00000000, /* .long @got */
2474 0xe59fc000, /* ldr ip,[pc] */
2475 0xea000000, /* b _PLT */
2476 0x00000000, /* .long @pltindex*sizeof(Elf32_Rela) */
b38cadfb 2477};
00a97672
RS		 2478
2479/* The format of entries in a VxWorks shared library. */
2480static const bfd_vma elf32_arm_vxworks_shared_plt_entry[] =
b38cadfb 2481{
07d6d2b8
AM		 2482 0xe59fc000, /* ldr ip,[pc] */
2483 0xe79cf009, /* ldr pc,[ip,r9] */
2484 0x00000000, /* .long @got */
2485 0xe59fc000, /* ldr ip,[pc] */
2486 0xe599f008, /* ldr pc,[r9,#8] */
2487 0x00000000, /* .long @pltindex*sizeof(Elf32_Rela) */
b38cadfb 2488};
00a97672 2489
b7693d02
DJ		 2490/* An initial stub used if the PLT entry is referenced from Thumb code. */
2491#define PLT_THUMB_STUB_SIZE 4
2492static const bfd_vma elf32_arm_plt_thumb_stub [] =
b38cadfb
NC		 2493{
2494 0x4778, /* bx pc */
b4e87f2c 2495 0xe7fd /* b .-2 */
b38cadfb 2496};
b7693d02 2497
e5a52504
MM		 2498/* The entries in a PLT when using a DLL-based target with multiple
2499 address spaces. */
906e58ca 2500static const bfd_vma elf32_arm_symbian_plt_entry [] =
b38cadfb 2501{
07d6d2b8
AM		 2502 0xe51ff004, /* ldr pc, [pc, #-4] */
2503 0x00000000, /* dcd R_ARM_GLOB_DAT(X) */
b38cadfb
NC		 2504};
2505
2506/* The first entry in a procedure linkage table looks like
2507 this. It is set up so that any shared library function that is
2508 called before the relocation has been set up calls the dynamic
2509 linker first. */
2510static const bfd_vma elf32_arm_nacl_plt0_entry [] =
2511{
2512 /* First bundle: */
2513 0xe300c000, /* movw ip, #:lower16:&GOT[2]-.+8 */
2514 0xe340c000, /* movt ip, #:upper16:&GOT[2]-.+8 */
2515 0xe08cc00f, /* add ip, ip, pc */
2516 0xe52dc008, /* str ip, [sp, #-8]! */
2517 /* Second bundle: */
edccdf7c
RM		 2518 0xe3ccc103, /* bic ip, ip, #0xc0000000 */
2519 0xe59cc000, /* ldr ip, [ip] */
b38cadfb 2520 0xe3ccc13f, /* bic ip, ip, #0xc000000f */
edccdf7c 2521 0xe12fff1c, /* bx ip */
b38cadfb 2522 /* Third bundle: */
edccdf7c
RM		 2523 0xe320f000, /* nop */
2524 0xe320f000, /* nop */
2525 0xe320f000, /* nop */
b38cadfb
NC		 2526 /* .Lplt_tail: */
2527 0xe50dc004, /* str ip, [sp, #-4] */
2528 /* Fourth bundle: */
edccdf7c
RM		 2529 0xe3ccc103, /* bic ip, ip, #0xc0000000 */
2530 0xe59cc000, /* ldr ip, [ip] */
b38cadfb 2531 0xe3ccc13f, /* bic ip, ip, #0xc000000f */
edccdf7c 2532 0xe12fff1c, /* bx ip */
b38cadfb
NC		 2533};
2534#define ARM_NACL_PLT_TAIL_OFFSET (11 * 4)
2535
2536/* Subsequent entries in a procedure linkage table look like this. */
2537static const bfd_vma elf32_arm_nacl_plt_entry [] =
2538{
2539 0xe300c000, /* movw ip, #:lower16:&GOT[n]-.+8 */
2540 0xe340c000, /* movt ip, #:upper16:&GOT[n]-.+8 */
2541 0xe08cc00f, /* add ip, ip, pc */
2542 0xea000000, /* b .Lplt_tail */
2543};
e5a52504 2544
906e58ca
NC		 2545#define ARM_MAX_FWD_BRANCH_OFFSET ((((1 << 23) - 1) << 2) + 8)
2546#define ARM_MAX_BWD_BRANCH_OFFSET ((-((1 << 23) << 2)) + 8)
2547#define THM_MAX_FWD_BRANCH_OFFSET ((1 << 22) -2 + 4)
2548#define THM_MAX_BWD_BRANCH_OFFSET (-(1 << 22) + 4)
2549#define THM2_MAX_FWD_BRANCH_OFFSET (((1 << 24) - 2) + 4)
2550#define THM2_MAX_BWD_BRANCH_OFFSET (-(1 << 24) + 4)
c5423981
TG		 2551#define THM2_MAX_FWD_COND_BRANCH_OFFSET (((1 << 20) -2) + 4)
2552#define THM2_MAX_BWD_COND_BRANCH_OFFSET (-(1 << 20) + 4)
906e58ca 2553
461a49ca 2554enum stub_insn_type
b38cadfb
NC		 2555{
2556 THUMB16_TYPE = 1,
2557 THUMB32_TYPE,
2558 ARM_TYPE,
2559 DATA_TYPE
2560};
461a49ca 2561
48229727
JB		 2562#define THUMB16_INSN(X) {(X), THUMB16_TYPE, R_ARM_NONE, 0}
2563/* A bit of a hack. A Thumb conditional branch, in which the proper condition
2564 is inserted in arm_build_one_stub(). */
2565#define THUMB16_BCOND_INSN(X) {(X), THUMB16_TYPE, R_ARM_NONE, 1}
2566#define THUMB32_INSN(X) {(X), THUMB32_TYPE, R_ARM_NONE, 0}
d5a67c02
AV		 2567#define THUMB32_MOVT(X) {(X), THUMB32_TYPE, R_ARM_THM_MOVT_ABS, 0}
2568#define THUMB32_MOVW(X) {(X), THUMB32_TYPE, R_ARM_THM_MOVW_ABS_NC, 0}
48229727
JB		 2569#define THUMB32_B_INSN(X, Z) {(X), THUMB32_TYPE, R_ARM_THM_JUMP24, (Z)}
2570#define ARM_INSN(X) {(X), ARM_TYPE, R_ARM_NONE, 0}
2571#define ARM_REL_INSN(X, Z) {(X), ARM_TYPE, R_ARM_JUMP24, (Z)}
2572#define DATA_WORD(X,Y,Z) {(X), DATA_TYPE, (Y), (Z)}
461a49ca
DJ		 2573
2574typedef struct
2575{
07d6d2b8 2576 bfd_vma data;
b38cadfb 2577 enum stub_insn_type type;
07d6d2b8
AM		 2578 unsigned int r_type;
2579 int reloc_addend;
461a49ca
DJ		 2580} insn_sequence;
2581
b4e87f2c
TC		 2582/* See note [Thumb nop sequence] when adding a veneer. */
2583
fea2b4d6
CL		 2584/* Arm/Thumb -> Arm/Thumb long branch stub. On V5T and above, use blx
2585 to reach the stub if necessary. */
461a49ca 2586static const insn_sequence elf32_arm_stub_long_branch_any_any[] =
b38cadfb 2587{
07d6d2b8 2588 ARM_INSN (0xe51ff004), /* ldr pc, [pc, #-4] */
b38cadfb
NC		 2589 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(X) */
2590};
906e58ca 2591
fea2b4d6
CL		 2592/* V4T Arm -> Thumb long branch stub. Used on V4T where blx is not
2593 available. */
461a49ca 2594static const insn_sequence elf32_arm_stub_long_branch_v4t_arm_thumb[] =
b38cadfb 2595{
07d6d2b8
AM		 2596 ARM_INSN (0xe59fc000), /* ldr ip, [pc, #0] */
2597 ARM_INSN (0xe12fff1c), /* bx ip */
b38cadfb
NC		 2598 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(X) */
2599};
906e58ca 2600
d3626fb0 2601/* Thumb -> Thumb long branch stub. Used on M-profile architectures. */
461a49ca 2602static const insn_sequence elf32_arm_stub_long_branch_thumb_only[] =
b38cadfb 2603{
07d6d2b8
AM		 2604 THUMB16_INSN (0xb401), /* push {r0} */
2605 THUMB16_INSN (0x4802), /* ldr r0, [pc, #8] */
2606 THUMB16_INSN (0x4684), /* mov ip, r0 */
2607 THUMB16_INSN (0xbc01), /* pop {r0} */
2608 THUMB16_INSN (0x4760), /* bx ip */
2609 THUMB16_INSN (0xbf00), /* nop */
b38cadfb
NC		 2610 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(X) */
2611};
906e58ca 2612
80c135e5
TP		 2613/* Thumb -> Thumb long branch stub in thumb2 encoding. Used on armv7. */
2614static const insn_sequence elf32_arm_stub_long_branch_thumb2_only[] =
2615{
07d6d2b8 2616 THUMB32_INSN (0xf85ff000), /* ldr.w pc, [pc, #-0] */
80c135e5
TP		 2617 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(x) */
2618};
2619
d5a67c02
AV		 2620/* Thumb -> Thumb long branch stub. Used for PureCode sections on Thumb2
2621 M-profile architectures. */
2622static const insn_sequence elf32_arm_stub_long_branch_thumb2_only_pure[] =
2623{
2624 THUMB32_MOVW (0xf2400c00), /* mov.w ip, R_ARM_MOVW_ABS_NC */
2625 THUMB32_MOVT (0xf2c00c00), /* movt ip, R_ARM_MOVT_ABS << 16 */
07d6d2b8 2626 THUMB16_INSN (0x4760), /* bx ip */
d5a67c02
AV		 2627};
2628
d3626fb0
CL		 2629/* V4T Thumb -> Thumb long branch stub. Using the stack is not
2630 allowed. */
2631static const insn_sequence elf32_arm_stub_long_branch_v4t_thumb_thumb[] =
b38cadfb 2632{
07d6d2b8 2633 THUMB16_INSN (0x4778), /* bx pc */
b4e87f2c 2634 THUMB16_INSN (0xe7fd), /* b .-2 */
07d6d2b8
AM		 2635 ARM_INSN (0xe59fc000), /* ldr ip, [pc, #0] */
2636 ARM_INSN (0xe12fff1c), /* bx ip */
b38cadfb
NC		 2637 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(X) */
2638};
d3626fb0 2639
fea2b4d6
CL		 2640/* V4T Thumb -> ARM long branch stub. Used on V4T where blx is not
2641 available. */
461a49ca 2642static const insn_sequence elf32_arm_stub_long_branch_v4t_thumb_arm[] =
b38cadfb 2643{
07d6d2b8 2644 THUMB16_INSN (0x4778), /* bx pc */
b4e87f2c 2645 THUMB16_INSN (0xe7fd), /* b .-2 */
07d6d2b8 2646 ARM_INSN (0xe51ff004), /* ldr pc, [pc, #-4] */
b38cadfb
NC		 2647 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(X) */
2648};
906e58ca 2649
fea2b4d6
CL		 2650/* V4T Thumb -> ARM short branch stub. Shorter variant of the above
2651 one, when the destination is close enough. */
461a49ca 2652static const insn_sequence elf32_arm_stub_short_branch_v4t_thumb_arm[] =
b38cadfb 2653{
07d6d2b8 2654 THUMB16_INSN (0x4778), /* bx pc */
b4e87f2c 2655 THUMB16_INSN (0xe7fd), /* b .-2 */
b38cadfb
NC		 2656 ARM_REL_INSN (0xea000000, -8), /* b (X-8) */
2657};
c820be07 2658
cf3eccff 2659/* ARM/Thumb -> ARM long branch stub, PIC. On V5T and above, use
fea2b4d6 2660 blx to reach the stub if necessary. */
cf3eccff 2661static const insn_sequence elf32_arm_stub_long_branch_any_arm_pic[] =
b38cadfb 2662{
07d6d2b8
AM		 2663 ARM_INSN (0xe59fc000), /* ldr ip, [pc] */
2664 ARM_INSN (0xe08ff00c), /* add pc, pc, ip */
b38cadfb
NC		 2665 DATA_WORD (0, R_ARM_REL32, -4), /* dcd R_ARM_REL32(X-4) */
2666};
906e58ca 2667
cf3eccff
DJ		 2668/* ARM/Thumb -> Thumb long branch stub, PIC. On V5T and above, use
2669 blx to reach the stub if necessary. We can not add into pc;
2670 it is not guaranteed to mode switch (different in ARMv6 and
2671 ARMv7). */
2672static const insn_sequence elf32_arm_stub_long_branch_any_thumb_pic[] =
b38cadfb 2673{
07d6d2b8
AM		 2674 ARM_INSN (0xe59fc004), /* ldr ip, [pc, #4] */
2675 ARM_INSN (0xe08fc00c), /* add ip, pc, ip */
2676 ARM_INSN (0xe12fff1c), /* bx ip */
b38cadfb
NC		 2677 DATA_WORD (0, R_ARM_REL32, 0), /* dcd R_ARM_REL32(X) */
2678};
cf3eccff 2679
ebe24dd4
CL		 2680/* V4T ARM -> ARM long branch stub, PIC. */
2681static const insn_sequence elf32_arm_stub_long_branch_v4t_arm_thumb_pic[] =
b38cadfb 2682{
07d6d2b8
AM		 2683 ARM_INSN (0xe59fc004), /* ldr ip, [pc, #4] */
2684 ARM_INSN (0xe08fc00c), /* add ip, pc, ip */
2685 ARM_INSN (0xe12fff1c), /* bx ip */
b38cadfb
NC		 2686 DATA_WORD (0, R_ARM_REL32, 0), /* dcd R_ARM_REL32(X) */
2687};
ebe24dd4
CL		 2688
2689/* V4T Thumb -> ARM long branch stub, PIC. */
2690static const insn_sequence elf32_arm_stub_long_branch_v4t_thumb_arm_pic[] =
b38cadfb 2691{
07d6d2b8 2692 THUMB16_INSN (0x4778), /* bx pc */
b4e87f2c 2693 THUMB16_INSN (0xe7fd), /* b .-2 */
07d6d2b8
AM		 2694 ARM_INSN (0xe59fc000), /* ldr ip, [pc, #0] */
2695 ARM_INSN (0xe08cf00f), /* add pc, ip, pc */
b38cadfb
NC		 2696 DATA_WORD (0, R_ARM_REL32, -4), /* dcd R_ARM_REL32(X) */
2697};
ebe24dd4 2698
d3626fb0
CL		 2699/* Thumb -> Thumb long branch stub, PIC. Used on M-profile
2700 architectures. */
ebe24dd4 2701static const insn_sequence elf32_arm_stub_long_branch_thumb_only_pic[] =
b38cadfb 2702{
07d6d2b8
AM		 2703 THUMB16_INSN (0xb401), /* push {r0} */
2704 THUMB16_INSN (0x4802), /* ldr r0, [pc, #8] */
2705 THUMB16_INSN (0x46fc), /* mov ip, pc */
2706 THUMB16_INSN (0x4484), /* add ip, r0 */
2707 THUMB16_INSN (0xbc01), /* pop {r0} */
2708 THUMB16_INSN (0x4760), /* bx ip */
b38cadfb
NC		 2709 DATA_WORD (0, R_ARM_REL32, 4), /* dcd R_ARM_REL32(X) */
2710};
ebe24dd4 2711
d3626fb0
CL		 2712/* V4T Thumb -> Thumb long branch stub, PIC. Using the stack is not
2713 allowed. */
2714static const insn_sequence elf32_arm_stub_long_branch_v4t_thumb_thumb_pic[] =
b38cadfb 2715{
07d6d2b8 2716 THUMB16_INSN (0x4778), /* bx pc */
b4e87f2c 2717 THUMB16_INSN (0xe7fd), /* b .-2 */
07d6d2b8
AM		 2718 ARM_INSN (0xe59fc004), /* ldr ip, [pc, #4] */
2719 ARM_INSN (0xe08fc00c), /* add ip, pc, ip */
2720 ARM_INSN (0xe12fff1c), /* bx ip */
b38cadfb
NC		 2721 DATA_WORD (0, R_ARM_REL32, 0), /* dcd R_ARM_REL32(X) */
2722};
d3626fb0 2723
0855e32b
NS		 2724/* Thumb2/ARM -> TLS trampoline. Lowest common denominator, which is a
2725 long PIC stub. We can use r1 as a scratch -- and cannot use ip. */
2726static const insn_sequence elf32_arm_stub_long_branch_any_tls_pic[] =
2727{
07d6d2b8
AM		 2728 ARM_INSN (0xe59f1000), /* ldr r1, [pc] */
2729 ARM_INSN (0xe08ff001), /* add pc, pc, r1 */
b38cadfb 2730 DATA_WORD (0, R_ARM_REL32, -4), /* dcd R_ARM_REL32(X-4) */
0855e32b
NS		 2731};
2732
2733/* V4T Thumb -> TLS trampoline. lowest common denominator, which is a
2734 long PIC stub. We can use r1 as a scratch -- and cannot use ip. */
2735static const insn_sequence elf32_arm_stub_long_branch_v4t_thumb_tls_pic[] =
2736{
07d6d2b8 2737 THUMB16_INSN (0x4778), /* bx pc */
b4e87f2c 2738 THUMB16_INSN (0xe7fd), /* b .-2 */
07d6d2b8
AM		 2739 ARM_INSN (0xe59f1000), /* ldr r1, [pc, #0] */
2740 ARM_INSN (0xe081f00f), /* add pc, r1, pc */
b38cadfb 2741 DATA_WORD (0, R_ARM_REL32, -4), /* dcd R_ARM_REL32(X) */
0855e32b
NS		 2742};
2743
7a89b94e
NC		 2744/* NaCl ARM -> ARM long branch stub. */
2745static const insn_sequence elf32_arm_stub_long_branch_arm_nacl[] =
2746{
2747 ARM_INSN (0xe59fc00c), /* ldr ip, [pc, #12] */
2748 ARM_INSN (0xe3ccc13f), /* bic ip, ip, #0xc000000f */
07d6d2b8
AM		 2749 ARM_INSN (0xe12fff1c), /* bx ip */
2750 ARM_INSN (0xe320f000), /* nop */
2751 ARM_INSN (0xe125be70), /* bkpt 0x5be0 */
2752 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(X) */
2753 DATA_WORD (0, R_ARM_NONE, 0), /* .word 0 */
2754 DATA_WORD (0, R_ARM_NONE, 0), /* .word 0 */
7a89b94e
NC		 2755};
2756
2757/* NaCl ARM -> ARM long branch stub, PIC. */
2758static const insn_sequence elf32_arm_stub_long_branch_arm_nacl_pic[] =
2759{
2760 ARM_INSN (0xe59fc00c), /* ldr ip, [pc, #12] */
07d6d2b8 2761 ARM_INSN (0xe08cc00f), /* add ip, ip, pc */
7a89b94e 2762 ARM_INSN (0xe3ccc13f), /* bic ip, ip, #0xc000000f */
07d6d2b8
AM		 2763 ARM_INSN (0xe12fff1c), /* bx ip */
2764 ARM_INSN (0xe125be70), /* bkpt 0x5be0 */
2765 DATA_WORD (0, R_ARM_REL32, 8), /* dcd R_ARM_REL32(X+8) */
2766 DATA_WORD (0, R_ARM_NONE, 0), /* .word 0 */
2767 DATA_WORD (0, R_ARM_NONE, 0), /* .word 0 */
7a89b94e
NC		 2768};
2769
4ba2ef8f
TP		 2770/* Stub used for transition to secure state (aka SG veneer). */
2771static const insn_sequence elf32_arm_stub_cmse_branch_thumb_only[] =
2772{
2773 THUMB32_INSN (0xe97fe97f), /* sg. */
2774 THUMB32_B_INSN (0xf000b800, -4), /* b.w original_branch_dest. */
2775};
2776
7a89b94e 2777
48229727
JB		 2778/* Cortex-A8 erratum-workaround stubs. */
2779
2780/* Stub used for conditional branches (which may be beyond +/-1MB away, so we
2781 can't use a conditional branch to reach this stub). */
2782
2783static const insn_sequence elf32_arm_stub_a8_veneer_b_cond[] =
b38cadfb 2784{
07d6d2b8 2785 THUMB16_BCOND_INSN (0xd001), /* b<cond>.n true. */
b38cadfb
NC		 2786 THUMB32_B_INSN (0xf000b800, -4), /* b.w insn_after_original_branch. */
2787 THUMB32_B_INSN (0xf000b800, -4) /* true: b.w original_branch_dest. */
2788};
48229727
JB		 2789
2790/* Stub used for b.w and bl.w instructions. */
2791
2792static const insn_sequence elf32_arm_stub_a8_veneer_b[] =
b38cadfb
NC		 2793{
2794 THUMB32_B_INSN (0xf000b800, -4) /* b.w original_branch_dest. */
2795};
48229727
JB		 2796
2797static const insn_sequence elf32_arm_stub_a8_veneer_bl[] =
b38cadfb
NC		 2798{
2799 THUMB32_B_INSN (0xf000b800, -4) /* b.w original_branch_dest. */
2800};
48229727
JB		 2801
2802/* Stub used for Thumb-2 blx.w instructions. We modified the original blx.w
2803 instruction (which switches to ARM mode) to point to this stub. Jump to the
2804 real destination using an ARM-mode branch. */
2805
2806static const insn_sequence elf32_arm_stub_a8_veneer_blx[] =
b38cadfb
NC		 2807{
2808 ARM_REL_INSN (0xea000000, -8) /* b original_branch_dest. */
2809};
48229727 2810
9553db3c
NC		 2811/* For each section group there can be a specially created linker section
2812 to hold the stubs for that group. The name of the stub section is based
2813 upon the name of another section within that group with the suffix below
2814 applied.
2815
2816 PR 13049: STUB_SUFFIX used to be ".stub", but this allowed the user to
2817 create what appeared to be a linker stub section when it actually
2818 contained user code/data. For example, consider this fragment:
b38cadfb 2819
9553db3c
NC		 2820 const char * stubborn_problems[] = { "np" };
2821
2822 If this is compiled with "-fPIC -fdata-sections" then gcc produces a
2823 section called:
2824
2825 .data.rel.local.stubborn_problems
2826
2827 This then causes problems in arm32_arm_build_stubs() as it triggers:
2828
2829 // Ignore non-stub sections.
2830 if (!strstr (stub_sec->name, STUB_SUFFIX))
2831 continue;
2832
2833 And so the section would be ignored instead of being processed. Hence
2834 the change in definition of STUB_SUFFIX to a name that cannot be a valid
2835 C identifier. */
2836#define STUB_SUFFIX ".__stub"
906e58ca 2837
738a79f6
CL		 2838/* One entry per long/short branch stub defined above. */
2839#define DEF_STUBS \
2840 DEF_STUB(long_branch_any_any) \
2841 DEF_STUB(long_branch_v4t_arm_thumb) \
2842 DEF_STUB(long_branch_thumb_only) \
2843 DEF_STUB(long_branch_v4t_thumb_thumb) \
2844 DEF_STUB(long_branch_v4t_thumb_arm) \
2845 DEF_STUB(short_branch_v4t_thumb_arm) \
2846 DEF_STUB(long_branch_any_arm_pic) \
2847 DEF_STUB(long_branch_any_thumb_pic) \
2848 DEF_STUB(long_branch_v4t_thumb_thumb_pic) \
2849 DEF_STUB(long_branch_v4t_arm_thumb_pic) \
2850 DEF_STUB(long_branch_v4t_thumb_arm_pic) \
48229727 2851 DEF_STUB(long_branch_thumb_only_pic) \
0855e32b
NS		 2852 DEF_STUB(long_branch_any_tls_pic) \
2853 DEF_STUB(long_branch_v4t_thumb_tls_pic) \
7a89b94e
NC		 2854 DEF_STUB(long_branch_arm_nacl) \
2855 DEF_STUB(long_branch_arm_nacl_pic) \
4ba2ef8f 2856 DEF_STUB(cmse_branch_thumb_only) \
48229727
JB		 2857 DEF_STUB(a8_veneer_b_cond) \
2858 DEF_STUB(a8_veneer_b) \
2859 DEF_STUB(a8_veneer_bl) \
80c135e5
TP		 2860 DEF_STUB(a8_veneer_blx) \
2861 DEF_STUB(long_branch_thumb2_only) \
d5a67c02 2862 DEF_STUB(long_branch_thumb2_only_pure)
738a79f6
CL		 2863
2864#define DEF_STUB(x) arm_stub_##x,
b38cadfb
NC		 2865enum elf32_arm_stub_type
2866{
906e58ca 2867 arm_stub_none,
738a79f6 2868 DEF_STUBS
4f4faa4d 2869 max_stub_type
738a79f6
CL		 2870};
2871#undef DEF_STUB
2872
8d9d9490
TP		 2873/* Note the first a8_veneer type. */
2874const unsigned arm_stub_a8_veneer_lwm = arm_stub_a8_veneer_b_cond;
2875
738a79f6
CL		 2876typedef struct
2877{
d3ce72d0 2878 const insn_sequence* template_sequence;
738a79f6
CL		 2879 int template_size;
2880} stub_def;
2881
2882#define DEF_STUB(x) {elf32_arm_stub_##x, ARRAY_SIZE(elf32_arm_stub_##x)},
b38cadfb
NC		 2883static const stub_def stub_definitions[] =
2884{
738a79f6
CL		 2885 {NULL, 0},
2886 DEF_STUBS
906e58ca
NC		 2887};
2888
2889struct elf32_arm_stub_hash_entry
2890{
2891 /* Base hash table entry structure. */
2892 struct bfd_hash_entry root;
2893
2894 /* The stub section. */
2895 asection *stub_sec;
2896
2897 /* Offset within stub_sec of the beginning of this stub. */
2898 bfd_vma stub_offset;
2899
2900 /* Given the symbol's value and its section we can determine its final
2901 value when building the stubs (so the stub knows where to jump). */
2902 bfd_vma target_value;
2903 asection *target_section;
2904
8d9d9490
TP		 2905 /* Same as above but for the source of the branch to the stub. Used for
2906 Cortex-A8 erratum workaround to patch it to branch to the stub. As
2907 such, source section does not need to be recorded since Cortex-A8 erratum
2908 workaround stubs are only generated when both source and target are in the
2909 same section. */
2910 bfd_vma source_value;
48229727
JB		 2911
2912 /* The instruction which caused this stub to be generated (only valid for
2913 Cortex-A8 erratum workaround stubs at present). */
2914 unsigned long orig_insn;
2915
461a49ca 2916 /* The stub type. */
906e58ca 2917 enum elf32_arm_stub_type stub_type;
461a49ca
DJ		 2918 /* Its encoding size in bytes. */
2919 int stub_size;
2920 /* Its template. */
2921 const insn_sequence *stub_template;
2922 /* The size of the template (number of entries). */
2923 int stub_template_size;
906e58ca
NC		 2924
2925 /* The symbol table entry, if any, that this was derived from. */
2926 struct elf32_arm_link_hash_entry *h;
2927
35fc36a8
RS		 2928 /* Type of branch. */
2929 enum arm_st_branch_type branch_type;
906e58ca
NC		 2930
2931 /* Where this stub is being called from, or, in the case of combined
2932 stub sections, the first input section in the group. */
2933 asection *id_sec;
7413f23f
DJ		 2934
2935 /* The name for the local symbol at the start of this stub. The
2936 stub name in the hash table has to be unique; this does not, so
2937 it can be friendlier. */
2938 char *output_name;
906e58ca
NC		 2939};
2940
e489d0ae
PB		 2941/* Used to build a map of a section. This is required for mixed-endian
2942 code/data. */
2943
2944typedef struct elf32_elf_section_map
2945{
2946 bfd_vma vma;
2947 char type;
2948}
2949elf32_arm_section_map;
2950
c7b8f16e
JB		 2951/* Information about a VFP11 erratum veneer, or a branch to such a veneer. */
2952
2953typedef enum
2954{
2955 VFP11_ERRATUM_BRANCH_TO_ARM_VENEER,
2956 VFP11_ERRATUM_BRANCH_TO_THUMB_VENEER,
2957 VFP11_ERRATUM_ARM_VENEER,
2958 VFP11_ERRATUM_THUMB_VENEER
2959}
2960elf32_vfp11_erratum_type;
2961
2962typedef struct elf32_vfp11_erratum_list
2963{
2964 struct elf32_vfp11_erratum_list *next;
2965 bfd_vma vma;
2966 union
2967 {
2968 struct
2969 {
2970 struct elf32_vfp11_erratum_list *veneer;
2971 unsigned int vfp_insn;
2972 } b;
2973 struct
2974 {
2975 struct elf32_vfp11_erratum_list *branch;
2976 unsigned int id;
2977 } v;
2978 } u;
2979 elf32_vfp11_erratum_type type;
2980}
2981elf32_vfp11_erratum_list;
2982
a504d23a
LA		 2983/* Information about a STM32L4XX erratum veneer, or a branch to such a
2984 veneer. */
2985typedef enum
2986{
2987 STM32L4XX_ERRATUM_BRANCH_TO_VENEER,
2988 STM32L4XX_ERRATUM_VENEER
2989}
2990elf32_stm32l4xx_erratum_type;
2991
2992typedef struct elf32_stm32l4xx_erratum_list
2993{
2994 struct elf32_stm32l4xx_erratum_list *next;
2995 bfd_vma vma;
2996 union
2997 {
2998 struct
2999 {
3000 struct elf32_stm32l4xx_erratum_list *veneer;
3001 unsigned int insn;
3002 } b;
3003 struct
3004 {
3005 struct elf32_stm32l4xx_erratum_list *branch;
3006 unsigned int id;
3007 } v;
3008 } u;
3009 elf32_stm32l4xx_erratum_type type;
3010}
3011elf32_stm32l4xx_erratum_list;
3012
2468f9c9
PB		 3013typedef enum
3014{
3015 DELETE_EXIDX_ENTRY,
3016 INSERT_EXIDX_CANTUNWIND_AT_END
3017}
3018arm_unwind_edit_type;
3019
3020/* A (sorted) list of edits to apply to an unwind table. */
3021typedef struct arm_unwind_table_edit
3022{
3023 arm_unwind_edit_type type;
3024 /* Note: we sometimes want to insert an unwind entry corresponding to a
3025 section different from the one we're currently writing out, so record the
3026 (text) section this edit relates to here. */
3027 asection *linked_section;
3028 unsigned int index;
3029 struct arm_unwind_table_edit *next;
3030}
3031arm_unwind_table_edit;
3032
8e3de13a 3033typedef struct _arm_elf_section_data
e489d0ae 3034{
2468f9c9 3035 /* Information about mapping symbols. */
e489d0ae 3036 struct bfd_elf_section_data elf;
8e3de13a 3037 unsigned int mapcount;
c7b8f16e 3038 unsigned int mapsize;
e489d0ae 3039 elf32_arm_section_map *map;
2468f9c9 3040 /* Information about CPU errata. */
c7b8f16e
JB		 3041 unsigned int erratumcount;
3042 elf32_vfp11_erratum_list *erratumlist;
a504d23a
LA		 3043 unsigned int stm32l4xx_erratumcount;
3044 elf32_stm32l4xx_erratum_list *stm32l4xx_erratumlist;
491d01d3 3045 unsigned int additional_reloc_count;
2468f9c9
PB		 3046 /* Information about unwind tables. */
3047 union
3048 {
3049 /* Unwind info attached to a text section. */
3050 struct
3051 {
3052 asection *arm_exidx_sec;
3053 } text;
3054
3055 /* Unwind info attached to an .ARM.exidx section. */
3056 struct
3057 {
3058 arm_unwind_table_edit *unwind_edit_list;
3059 arm_unwind_table_edit *unwind_edit_tail;
3060 } exidx;
3061 } u;
8e3de13a
NC		 3062}
3063_arm_elf_section_data;
e489d0ae
PB		 3064
3065#define elf32_arm_section_data(sec) \
8e3de13a 3066 ((_arm_elf_section_data *) elf_section_data (sec))
e489d0ae 3067
48229727
JB		 3068/* A fix which might be required for Cortex-A8 Thumb-2 branch/TLB erratum.
3069 These fixes are subject to a relaxation procedure (in elf32_arm_size_stubs),
3070 so may be created multiple times: we use an array of these entries whilst
3071 relaxing which we can refresh easily, then create stubs for each potentially
3072 erratum-triggering instruction once we've settled on a solution. */
3073
b38cadfb
NC		 3074struct a8_erratum_fix
3075{
48229727
JB		 3076 bfd *input_bfd;
3077 asection *section;
3078 bfd_vma offset;
8d9d9490 3079 bfd_vma target_offset;
48229727
JB		 3080 unsigned long orig_insn;
3081 char *stub_name;
3082 enum elf32_arm_stub_type stub_type;
35fc36a8 3083 enum arm_st_branch_type branch_type;
48229727
JB		 3084};
3085
3086/* A table of relocs applied to branches which might trigger Cortex-A8
3087 erratum. */
3088
b38cadfb
NC		 3089struct a8_erratum_reloc
3090{
48229727
JB		 3091 bfd_vma from;
3092 bfd_vma destination;
92750f34
DJ		 3093 struct elf32_arm_link_hash_entry *hash;
3094 const char *sym_name;
48229727 3095 unsigned int r_type;
35fc36a8 3096 enum arm_st_branch_type branch_type;
48229727
JB		 3097 bfd_boolean non_a8_stub;
3098};
3099
ba93b8ac
DJ		 3100/* The size of the thread control block. */
3101#define TCB_SIZE 8
3102
34e77a92
RS		 3103/* ARM-specific information about a PLT entry, over and above the usual
3104 gotplt_union. */
b38cadfb
NC		 3105struct arm_plt_info
3106{
34e77a92
RS		 3107 /* We reference count Thumb references to a PLT entry separately,
3108 so that we can emit the Thumb trampoline only if needed. */
3109 bfd_signed_vma thumb_refcount;
3110
3111 /* Some references from Thumb code may be eliminated by BL->BLX
3112 conversion, so record them separately. */
3113 bfd_signed_vma maybe_thumb_refcount;
3114
3115 /* How many of the recorded PLT accesses were from non-call relocations.
3116 This information is useful when deciding whether anything takes the
3117 address of an STT_GNU_IFUNC PLT. A value of 0 means that all
3118 non-call references to the function should resolve directly to the
3119 real runtime target. */
3120 unsigned int noncall_refcount;
3121
3122 /* Since PLT entries have variable size if the Thumb prologue is
3123 used, we need to record the index into .got.plt instead of
3124 recomputing it from the PLT offset. */
3125 bfd_signed_vma got_offset;
3126};
3127
3128/* Information about an .iplt entry for a local STT_GNU_IFUNC symbol. */
b38cadfb
NC		 3129struct arm_local_iplt_info
3130{
34e77a92
RS		 3131 /* The information that is usually found in the generic ELF part of
3132 the hash table entry. */
3133 union gotplt_union root;
3134
3135 /* The information that is usually found in the ARM-specific part of
3136 the hash table entry. */
3137 struct arm_plt_info arm;
3138
3139 /* A list of all potential dynamic relocations against this symbol. */
3140 struct elf_dyn_relocs *dyn_relocs;
3141};
3142
e8b09b87
CL		 3143/* Structure to handle FDPIC support for local functions. */
3144struct fdpic_local {
3145 unsigned int funcdesc_cnt;
3146 unsigned int gotofffuncdesc_cnt;
3147 int funcdesc_offset;
3148};
3149
0ffa91dd 3150struct elf_arm_obj_tdata
ba93b8ac
DJ		 3151{
3152 struct elf_obj_tdata root;
3153
3154 /* tls_type for each local got entry. */
3155 char *local_got_tls_type;
ee065d83 3156
0855e32b
NS		 3157 /* GOTPLT entries for TLS descriptors. */
3158 bfd_vma *local_tlsdesc_gotent;
3159
34e77a92
RS		 3160 /* Information for local symbols that need entries in .iplt. */
3161 struct arm_local_iplt_info **local_iplt;
3162
bf21ed78
MS		 3163 /* Zero to warn when linking objects with incompatible enum sizes. */
3164 int no_enum_size_warning;
a9dc9481
JM		 3165
3166 /* Zero to warn when linking objects with incompatible wchar_t sizes. */
3167 int no_wchar_size_warning;
e8b09b87
CL		 3168
3169 /* Maintains FDPIC counters and funcdesc info. */
3170 struct fdpic_local *local_fdpic_cnts;
ba93b8ac
DJ		 3171};
3172
0ffa91dd
NC		 3173#define elf_arm_tdata(bfd) \
3174 ((struct elf_arm_obj_tdata *) (bfd)->tdata.any)
ba93b8ac 3175
0ffa91dd
NC		 3176#define elf32_arm_local_got_tls_type(bfd) \
3177 (elf_arm_tdata (bfd)->local_got_tls_type)
3178
0855e32b
NS		 3179#define elf32_arm_local_tlsdesc_gotent(bfd) \
3180 (elf_arm_tdata (bfd)->local_tlsdesc_gotent)
3181
34e77a92
RS		 3182#define elf32_arm_local_iplt(bfd) \
3183 (elf_arm_tdata (bfd)->local_iplt)
3184
e8b09b87
CL		 3185#define elf32_arm_local_fdpic_cnts(bfd) \
3186 (elf_arm_tdata (bfd)->local_fdpic_cnts)
3187
0ffa91dd
NC		 3188#define is_arm_elf(bfd) \
3189 (bfd_get_flavour (bfd) == bfd_target_elf_flavour \
3190 && elf_tdata (bfd) != NULL \
4dfe6ac6 3191 && elf_object_id (bfd) == ARM_ELF_DATA)
ba93b8ac
DJ		 3192
3193static bfd_boolean
3194elf32_arm_mkobject (bfd *abfd)
3195{
0ffa91dd 3196 return bfd_elf_allocate_object (abfd, sizeof (struct elf_arm_obj_tdata),
4dfe6ac6 3197 ARM_ELF_DATA);
ba93b8ac
DJ		 3198}
3199
ba93b8ac
DJ		 3200#define elf32_arm_hash_entry(ent) ((struct elf32_arm_link_hash_entry *)(ent))
3201
e8b09b87
CL		 3202/* Structure to handle FDPIC support for extern functions. */
3203struct fdpic_global {
3204 unsigned int gotofffuncdesc_cnt;
3205 unsigned int gotfuncdesc_cnt;
3206 unsigned int funcdesc_cnt;
3207 int funcdesc_offset;
3208 int gotfuncdesc_offset;
3209};
3210
ba96a88f 3211/* Arm ELF linker hash entry. */
252b5132 3212struct elf32_arm_link_hash_entry
b38cadfb
NC		 3213{
3214 struct elf_link_hash_entry root;
252b5132 3215
b38cadfb
NC		 3216 /* Track dynamic relocs copied for this symbol. */
3217 struct elf_dyn_relocs *dyn_relocs;
b7693d02 3218
b38cadfb
NC		 3219 /* ARM-specific PLT information. */
3220 struct arm_plt_info plt;
ba93b8ac
DJ		 3221
3222#define GOT_UNKNOWN 0
3223#define GOT_NORMAL 1
3224#define GOT_TLS_GD 2
3225#define GOT_TLS_IE 4
0855e32b
NS		 3226#define GOT_TLS_GDESC 8
3227#define GOT_TLS_GD_ANY_P(type) ((type & GOT_TLS_GD) || (type & GOT_TLS_GDESC))
b38cadfb 3228 unsigned int tls_type : 8;
34e77a92 3229
b38cadfb
NC		 3230 /* True if the symbol's PLT entry is in .iplt rather than .plt. */
3231 unsigned int is_iplt : 1;
34e77a92 3232
b38cadfb 3233 unsigned int unused : 23;
a4fd1a8e 3234
b38cadfb
NC		 3235 /* Offset of the GOTPLT entry reserved for the TLS descriptor,
3236 starting at the end of the jump table. */
3237 bfd_vma tlsdesc_got;
0855e32b 3238
b38cadfb
NC		 3239 /* The symbol marking the real symbol location for exported thumb
3240 symbols with Arm stubs. */
3241 struct elf_link_hash_entry *export_glue;
906e58ca 3242
b38cadfb 3243 /* A pointer to the most recently used stub hash entry against this
8029a119 3244 symbol. */
b38cadfb 3245 struct elf32_arm_stub_hash_entry *stub_cache;
e8b09b87
CL		 3246
3247 /* Counter for FDPIC relocations against this symbol. */
3248 struct fdpic_global fdpic_cnts;
b38cadfb 3249};
252b5132 3250
252b5132 3251/* Traverse an arm ELF linker hash table. */
252b5132
RH		 3252#define elf32_arm_link_hash_traverse(table, func, info) \
3253 (elf_link_hash_traverse \
3254 (&(table)->root, \
b7693d02 3255 (bfd_boolean (*) (struct elf_link_hash_entry *, void *)) (func), \
252b5132
RH		 3256 (info)))
3257
3258/* Get the ARM elf linker hash table from a link_info structure. */
3259#define elf32_arm_hash_table(info) \
4dfe6ac6
NC		 3260 (elf_hash_table_id ((struct elf_link_hash_table *) ((info)->hash)) \
3261 == ARM_ELF_DATA ? ((struct elf32_arm_link_hash_table *) ((info)->hash)) : NULL)
252b5132 3262
906e58ca
NC		 3263#define arm_stub_hash_lookup(table, string, create, copy) \
3264 ((struct elf32_arm_stub_hash_entry *) \
3265 bfd_hash_lookup ((table), (string), (create), (copy)))
3266
21d799b5
NC		 3267/* Array to keep track of which stub sections have been created, and
3268 information on stub grouping. */
3269struct map_stub
3270{
3271 /* This is the section to which stubs in the group will be
3272 attached. */
3273 asection *link_sec;
3274 /* The stub section. */
3275 asection *stub_sec;
3276};
3277
0855e32b
NS		 3278#define elf32_arm_compute_jump_table_size(htab) \
3279 ((htab)->next_tls_desc_index * 4)
3280
9b485d32 3281/* ARM ELF linker hash table. */
252b5132 3282struct elf32_arm_link_hash_table
906e58ca
NC		 3283{
3284 /* The main hash table. */
3285 struct elf_link_hash_table root;
252b5132 3286
906e58ca
NC		 3287 /* The size in bytes of the section containing the Thumb-to-ARM glue. */
3288 bfd_size_type thumb_glue_size;
252b5132 3289
906e58ca
NC		 3290 /* The size in bytes of the section containing the ARM-to-Thumb glue. */
3291 bfd_size_type arm_glue_size;
252b5132 3292
906e58ca
NC		 3293 /* The size in bytes of section containing the ARMv4 BX veneers. */
3294 bfd_size_type bx_glue_size;
845b51d6 3295
906e58ca
NC		 3296 /* Offsets of ARMv4 BX veneers. Bit1 set if present, and Bit0 set when
3297 veneer has been populated. */
3298 bfd_vma bx_glue_offset[15];
845b51d6 3299
906e58ca
NC		 3300 /* The size in bytes of the section containing glue for VFP11 erratum
3301 veneers. */
3302 bfd_size_type vfp11_erratum_glue_size;
c7b8f16e 3303
a504d23a
LA		 3304 /* The size in bytes of the section containing glue for STM32L4XX erratum
3305 veneers. */
3306 bfd_size_type stm32l4xx_erratum_glue_size;
3307
48229727
JB		 3308 /* A table of fix locations for Cortex-A8 Thumb-2 branch/TLB erratum. This
3309 holds Cortex-A8 erratum fix locations between elf32_arm_size_stubs() and
3310 elf32_arm_write_section(). */
3311 struct a8_erratum_fix *a8_erratum_fixes;
3312 unsigned int num_a8_erratum_fixes;
3313
906e58ca
NC		 3314 /* An arbitrary input BFD chosen to hold the glue sections. */
3315 bfd * bfd_of_glue_owner;
ba96a88f 3316
906e58ca
NC		 3317 /* Nonzero to output a BE8 image. */
3318 int byteswap_code;
e489d0ae 3319
906e58ca
NC		 3320 /* Zero if R_ARM_TARGET1 means R_ARM_ABS32.
3321 Nonzero if R_ARM_TARGET1 means R_ARM_REL32. */
3322 int target1_is_rel;
9c504268 3323
906e58ca
NC		 3324 /* The relocation to use for R_ARM_TARGET2 relocations. */
3325 int target2_reloc;
eb043451 3326
906e58ca
NC		 3327 /* 0 = Ignore R_ARM_V4BX.
3328 1 = Convert BX to MOV PC.
3329 2 = Generate v4 interworing stubs. */
3330 int fix_v4bx;
319850b4 3331
48229727
JB		 3332 /* Whether we should fix the Cortex-A8 Thumb-2 branch/TLB erratum. */
3333 int fix_cortex_a8;
3334
2de70689
MGD		 3335 /* Whether we should fix the ARM1176 BLX immediate issue. */
3336 int fix_arm1176;
3337
906e58ca
NC		 3338 /* Nonzero if the ARM/Thumb BLX instructions are available for use. */
3339 int use_blx;
33bfe774 3340
906e58ca
NC		 3341 /* What sort of code sequences we should look for which may trigger the
3342 VFP11 denorm erratum. */
3343 bfd_arm_vfp11_fix vfp11_fix;
c7b8f16e 3344
906e58ca
NC		 3345 /* Global counter for the number of fixes we have emitted. */
3346 int num_vfp11_fixes;
c7b8f16e 3347
a504d23a
LA		 3348 /* What sort of code sequences we should look for which may trigger the
3349 STM32L4XX erratum. */
3350 bfd_arm_stm32l4xx_fix stm32l4xx_fix;
3351
3352 /* Global counter for the number of fixes we have emitted. */
3353 int num_stm32l4xx_fixes;
3354
906e58ca
NC		 3355 /* Nonzero to force PIC branch veneers. */
3356 int pic_veneer;
27e55c4d 3357
906e58ca
NC		 3358 /* The number of bytes in the initial entry in the PLT. */
3359 bfd_size_type plt_header_size;
e5a52504 3360
906e58ca
NC		 3361 /* The number of bytes in the subsequent PLT etries. */
3362 bfd_size_type plt_entry_size;
e5a52504 3363
906e58ca
NC		 3364 /* True if the target system is VxWorks. */
3365 int vxworks_p;
00a97672 3366
906e58ca
NC		 3367 /* True if the target system is Symbian OS. */
3368 int symbian_p;
e5a52504 3369
b38cadfb
NC		 3370 /* True if the target system is Native Client. */
3371 int nacl_p;
3372
906e58ca 3373 /* True if the target uses REL relocations. */
f3185997 3374 bfd_boolean use_rel;
4e7fd91e 3375
54ddd295
TP		 3376 /* Nonzero if import library must be a secure gateway import library
3377 as per ARMv8-M Security Extensions. */
3378 int cmse_implib;
3379
0955507f
TP		 3380 /* The import library whose symbols' address must remain stable in
3381 the import library generated. */
3382 bfd *in_implib_bfd;
3383
0855e32b
NS		 3384 /* The index of the next unused R_ARM_TLS_DESC slot in .rel.plt. */
3385 bfd_vma next_tls_desc_index;
3386
3387 /* How many R_ARM_TLS_DESC relocations were generated so far. */
3388 bfd_vma num_tls_desc;
3389
906e58ca
NC		 3390 /* The (unloaded but important) VxWorks .rela.plt.unloaded section. */
3391 asection *srelplt2;
00a97672 3392
0855e32b
NS		 3393 /* The offset into splt of the PLT entry for the TLS descriptor
3394 resolver. Special values are 0, if not necessary (or not found
3395 to be necessary yet), and -1 if needed but not determined
3396 yet. */
3397 bfd_vma dt_tlsdesc_plt;
3398
3399 /* The offset into sgot of the GOT entry used by the PLT entry
3400 above. */
b38cadfb 3401 bfd_vma dt_tlsdesc_got;
0855e32b
NS		 3402
3403 /* Offset in .plt section of tls_arm_trampoline. */
3404 bfd_vma tls_trampoline;
3405
5c5a4843 3406 /* Data for R_ARM_TLS_LDM32/R_ARM_TLS_LDM32_FDPIC relocations. */
906e58ca
NC		 3407 union
3408 {
3409 bfd_signed_vma refcount;
3410 bfd_vma offset;
3411 } tls_ldm_got;
b7693d02 3412
87d72d41
AM		 3413 /* Small local sym cache. */
3414 struct sym_cache sym_cache;
906e58ca
NC		 3415
3416 /* For convenience in allocate_dynrelocs. */
3417 bfd * obfd;
3418
0855e32b
NS		 3419 /* The amount of space used by the reserved portion of the sgotplt
3420 section, plus whatever space is used by the jump slots. */
3421 bfd_vma sgotplt_jump_table_size;
3422
906e58ca
NC		 3423 /* The stub hash table. */
3424 struct bfd_hash_table stub_hash_table;
3425
3426 /* Linker stub bfd. */
3427 bfd *stub_bfd;
3428
3429 /* Linker call-backs. */
6bde4c52
TP		 3430 asection * (*add_stub_section) (const char *, asection *, asection *,
3431 unsigned int);
906e58ca
NC		 3432 void (*layout_sections_again) (void);
3433
3434 /* Array to keep track of which stub sections have been created, and
3435 information on stub grouping. */
21d799b5 3436 struct map_stub *stub_group;
906e58ca 3437
4ba2ef8f
TP		 3438 /* Input stub section holding secure gateway veneers. */
3439 asection *cmse_stub_sec;
3440
0955507f
TP		 3441 /* Offset in cmse_stub_sec where new SG veneers (not in input import library)
3442 start to be allocated. */
3443 bfd_vma new_cmse_stub_offset;
3444
fe33d2fa 3445 /* Number of elements in stub_group. */
7292b3ac 3446 unsigned int top_id;
fe33d2fa 3447
906e58ca
NC		 3448 /* Assorted information used by elf32_arm_size_stubs. */
3449 unsigned int bfd_count;
7292b3ac 3450 unsigned int top_index;
906e58ca 3451 asection **input_list;
617a5ada
CL		 3452
3453 /* True if the target system uses FDPIC. */
3454 int fdpic_p;
e8b09b87
CL		 3455
3456 /* Fixup section. Used for FDPIC. */
3457 asection *srofixup;
906e58ca 3458};
252b5132 3459
e8b09b87
CL		 3460/* Add an FDPIC read-only fixup. */
3461static void
3462arm_elf_add_rofixup (bfd *output_bfd, asection *srofixup, bfd_vma offset)
3463{
3464 bfd_vma fixup_offset;
3465
3466 fixup_offset = srofixup->reloc_count++ * 4;
3467 BFD_ASSERT (fixup_offset < srofixup->size);
3468 bfd_put_32 (output_bfd, offset, srofixup->contents + fixup_offset);
3469}
3470
a504d23a
LA		 3471static inline int
3472ctz (unsigned int mask)
3473{
3474#if GCC_VERSION >= 3004
3475 return __builtin_ctz (mask);
3476#else
3477 unsigned int i;
3478
3479 for (i = 0; i < 8 * sizeof (mask); i++)
3480 {
3481 if (mask & 0x1)
3482 break;
3483 mask = (mask >> 1);
3484 }
3485 return i;
3486#endif
3487}
3488
3489static inline int
b25e998d 3490elf32_arm_popcount (unsigned int mask)
a504d23a
LA		 3491{
3492#if GCC_VERSION >= 3004
3493 return __builtin_popcount (mask);
3494#else
b25e998d
CG		 3495 unsigned int i;
3496 int sum = 0;
a504d23a
LA		 3497
3498 for (i = 0; i < 8 * sizeof (mask); i++)
3499 {
3500 if (mask & 0x1)
3501 sum++;
3502 mask = (mask >> 1);
3503 }
3504 return sum;
3505#endif
3506}
3507
e8b09b87
CL		 3508static void elf32_arm_add_dynreloc (bfd *output_bfd, struct bfd_link_info *info,
3509 asection *sreloc, Elf_Internal_Rela *rel);
3510
3511static void
3512arm_elf_fill_funcdesc(bfd *output_bfd,
3513 struct bfd_link_info *info,
3514 int *funcdesc_offset,
3515 int dynindx,
3516 int offset,
3517 bfd_vma addr,
3518 bfd_vma dynreloc_value,
3519 bfd_vma seg)
3520{
3521 if ((*funcdesc_offset & 1) == 0)
3522 {
3523 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (info);
3524 asection *sgot = globals->root.sgot;
3525
3526 if (bfd_link_pic(info))
3527 {
3528 asection *srelgot = globals->root.srelgot;
3529 Elf_Internal_Rela outrel;
3530
3531 outrel.r_info = ELF32_R_INFO (dynindx, R_ARM_FUNCDESC_VALUE);
3532 outrel.r_offset = sgot->output_section->vma + sgot->output_offset + offset;
3533 outrel.r_addend = 0;
3534
3535 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
3536 bfd_put_32 (output_bfd, addr, sgot->contents + offset);
3537 bfd_put_32 (output_bfd, seg, sgot->contents + offset + 4);
3538 }
3539 else
3540 {
3541 struct elf_link_hash_entry *hgot = globals->root.hgot;
3542 bfd_vma got_value = hgot->root.u.def.value
3543 + hgot->root.u.def.section->output_section->vma
3544 + hgot->root.u.def.section->output_offset;
3545
3546 arm_elf_add_rofixup(output_bfd, globals->srofixup,
3547 sgot->output_section->vma + sgot->output_offset
3548 + offset);
3549 arm_elf_add_rofixup(output_bfd, globals->srofixup,
3550 sgot->output_section->vma + sgot->output_offset
3551 + offset + 4);
3552 bfd_put_32 (output_bfd, dynreloc_value, sgot->contents + offset);
3553 bfd_put_32 (output_bfd, got_value, sgot->contents + offset + 4);
3554 }
3555 *funcdesc_offset |= 1;
3556 }
3557}
3558
780a67af
NC		 3559/* Create an entry in an ARM ELF linker hash table. */
3560
3561static struct bfd_hash_entry *
57e8b36a 3562elf32_arm_link_hash_newfunc (struct bfd_hash_entry * entry,
99059e56
RM		 3563 struct bfd_hash_table * table,
3564 const char * string)
780a67af
NC		 3565{
3566 struct elf32_arm_link_hash_entry * ret =
3567 (struct elf32_arm_link_hash_entry *) entry;
3568
3569 /* Allocate the structure if it has not already been allocated by a
3570 subclass. */
906e58ca 3571 if (ret == NULL)
21d799b5 3572 ret = (struct elf32_arm_link_hash_entry *)
99059e56 3573 bfd_hash_allocate (table, sizeof (struct elf32_arm_link_hash_entry));
57e8b36a 3574 if (ret == NULL)
780a67af
NC		 3575 return (struct bfd_hash_entry *) ret;
3576
3577 /* Call the allocation method of the superclass. */
3578 ret = ((struct elf32_arm_link_hash_entry *)
3579 _bfd_elf_link_hash_newfunc ((struct bfd_hash_entry *) ret,
3580 table, string));
57e8b36a 3581 if (ret != NULL)
b7693d02 3582 {
0bdcacaf 3583 ret->dyn_relocs = NULL;
ba93b8ac 3584 ret->tls_type = GOT_UNKNOWN;
0855e32b 3585 ret->tlsdesc_got = (bfd_vma) -1;
34e77a92
RS		 3586 ret->plt.thumb_refcount = 0;
3587 ret->plt.maybe_thumb_refcount = 0;
3588 ret->plt.noncall_refcount = 0;
3589 ret->plt.got_offset = -1;
3590 ret->is_iplt = FALSE;
a4fd1a8e 3591 ret->export_glue = NULL;
906e58ca
NC		 3592
3593 ret->stub_cache = NULL;
e8b09b87
CL		 3594
3595 ret->fdpic_cnts.gotofffuncdesc_cnt = 0;
3596 ret->fdpic_cnts.gotfuncdesc_cnt = 0;
3597 ret->fdpic_cnts.funcdesc_cnt = 0;
3598 ret->fdpic_cnts.funcdesc_offset = -1;
3599 ret->fdpic_cnts.gotfuncdesc_offset = -1;
b7693d02 3600 }
780a67af
NC		 3601
3602 return (struct bfd_hash_entry *) ret;
3603}
3604
34e77a92
RS		 3605/* Ensure that we have allocated bookkeeping structures for ABFD's local
3606 symbols. */
3607
3608static bfd_boolean
3609elf32_arm_allocate_local_sym_info (bfd *abfd)
3610{
3611 if (elf_local_got_refcounts (abfd) == NULL)
3612 {
3613 bfd_size_type num_syms;
3614 bfd_size_type size;
3615 char *data;
3616
3617 num_syms = elf_tdata (abfd)->symtab_hdr.sh_info;
3618 size = num_syms * (sizeof (bfd_signed_vma)
3619 + sizeof (struct arm_local_iplt_info *)
3620 + sizeof (bfd_vma)
e8b09b87
CL		 3621 + sizeof (char)
3622 + sizeof (struct fdpic_local));
34e77a92
RS		 3623 data = bfd_zalloc (abfd, size);
3624 if (data == NULL)
3625 return FALSE;
3626
e8b09b87
CL		 3627 elf32_arm_local_fdpic_cnts (abfd) = (struct fdpic_local *) data;
3628 data += num_syms * sizeof (struct fdpic_local);
3629
34e77a92
RS		 3630 elf_local_got_refcounts (abfd) = (bfd_signed_vma *) data;
3631 data += num_syms * sizeof (bfd_signed_vma);
3632
3633 elf32_arm_local_iplt (abfd) = (struct arm_local_iplt_info **) data;
3634 data += num_syms * sizeof (struct arm_local_iplt_info *);
3635
3636 elf32_arm_local_tlsdesc_gotent (abfd) = (bfd_vma *) data;
3637 data += num_syms * sizeof (bfd_vma);
3638
3639 elf32_arm_local_got_tls_type (abfd) = data;
3640 }
3641 return TRUE;
3642}
3643
3644/* Return the .iplt information for local symbol R_SYMNDX, which belongs
3645 to input bfd ABFD. Create the information if it doesn't already exist.
3646 Return null if an allocation fails. */
3647
3648static struct arm_local_iplt_info *
3649elf32_arm_create_local_iplt (bfd *abfd, unsigned long r_symndx)
3650{
3651 struct arm_local_iplt_info **ptr;
3652
3653 if (!elf32_arm_allocate_local_sym_info (abfd))
3654 return NULL;
3655
3656 BFD_ASSERT (r_symndx < elf_tdata (abfd)->symtab_hdr.sh_info);
3657 ptr = &elf32_arm_local_iplt (abfd)[r_symndx];
3658 if (*ptr == NULL)
3659 *ptr = bfd_zalloc (abfd, sizeof (**ptr));
3660 return *ptr;
3661}
3662
3663/* Try to obtain PLT information for the symbol with index R_SYMNDX
3664 in ABFD's symbol table. If the symbol is global, H points to its
3665 hash table entry, otherwise H is null.
3666
3667 Return true if the symbol does have PLT information. When returning
3668 true, point *ROOT_PLT at the target-independent reference count/offset
3669 union and *ARM_PLT at the ARM-specific information. */
3670
3671static bfd_boolean
4ba2ef8f
TP		 3672elf32_arm_get_plt_info (bfd *abfd, struct elf32_arm_link_hash_table *globals,
3673 struct elf32_arm_link_hash_entry *h,
34e77a92
RS		 3674 unsigned long r_symndx, union gotplt_union **root_plt,
3675 struct arm_plt_info **arm_plt)
3676{
3677 struct arm_local_iplt_info *local_iplt;
3678
4ba2ef8f
TP		 3679 if (globals->root.splt == NULL && globals->root.iplt == NULL)
3680 return FALSE;
3681
34e77a92
RS		 3682 if (h != NULL)
3683 {
3684 *root_plt = &h->root.plt;
3685 *arm_plt = &h->plt;
3686 return TRUE;
3687 }
3688
3689 if (elf32_arm_local_iplt (abfd) == NULL)
3690 return FALSE;
3691
3692 local_iplt = elf32_arm_local_iplt (abfd)[r_symndx];
3693 if (local_iplt == NULL)
3694 return FALSE;
3695
3696 *root_plt = &local_iplt->root;
3697 *arm_plt = &local_iplt->arm;
3698 return TRUE;
3699}
3700
59029f57
CL		 3701static bfd_boolean using_thumb_only (struct elf32_arm_link_hash_table *globals);
3702
34e77a92
RS		 3703/* Return true if the PLT described by ARM_PLT requires a Thumb stub
3704 before it. */
3705
3706static bfd_boolean
3707elf32_arm_plt_needs_thumb_stub_p (struct bfd_link_info *info,
3708 struct arm_plt_info *arm_plt)
3709{
3710 struct elf32_arm_link_hash_table *htab;
3711
3712 htab = elf32_arm_hash_table (info);
59029f57
CL		 3713
3714 return (!using_thumb_only(htab) && (arm_plt->thumb_refcount != 0
3715 || (!htab->use_blx && arm_plt->maybe_thumb_refcount != 0)));
34e77a92
RS		 3716}
3717
3718/* Return a pointer to the head of the dynamic reloc list that should
3719 be used for local symbol ISYM, which is symbol number R_SYMNDX in
3720 ABFD's symbol table. Return null if an error occurs. */
3721
3722static struct elf_dyn_relocs **
3723elf32_arm_get_local_dynreloc_list (bfd *abfd, unsigned long r_symndx,
3724 Elf_Internal_Sym *isym)
3725{
3726 if (ELF32_ST_TYPE (isym->st_info) == STT_GNU_IFUNC)
3727 {
3728 struct arm_local_iplt_info *local_iplt;
3729
3730 local_iplt = elf32_arm_create_local_iplt (abfd, r_symndx);
3731 if (local_iplt == NULL)
3732 return NULL;
3733 return &local_iplt->dyn_relocs;
3734 }
3735 else
3736 {
3737 /* Track dynamic relocs needed for local syms too.
3738 We really need local syms available to do this
3739 easily. Oh well. */
3740 asection *s;
3741 void *vpp;
3742
3743 s = bfd_section_from_elf_index (abfd, isym->st_shndx);
3744 if (s == NULL)
3745 abort ();
3746
3747 vpp = &elf_section_data (s)->local_dynrel;
3748 return (struct elf_dyn_relocs **) vpp;
3749 }
3750}
3751
906e58ca
NC		 3752/* Initialize an entry in the stub hash table. */
3753
3754static struct bfd_hash_entry *
3755stub_hash_newfunc (struct bfd_hash_entry *entry,
3756 struct bfd_hash_table *table,
3757 const char *string)
3758{
3759 /* Allocate the structure if it has not already been allocated by a
3760 subclass. */
3761 if (entry == NULL)
3762 {
21d799b5 3763 entry = (struct bfd_hash_entry *)
99059e56 3764 bfd_hash_allocate (table, sizeof (struct elf32_arm_stub_hash_entry));
906e58ca
NC		 3765 if (entry == NULL)
3766 return entry;
3767 }
3768
3769 /* Call the allocation method of the superclass. */
3770 entry = bfd_hash_newfunc (entry, table, string);
3771 if (entry != NULL)
3772 {
3773 struct elf32_arm_stub_hash_entry *eh;
3774
3775 /* Initialize the local fields. */
3776 eh = (struct elf32_arm_stub_hash_entry *) entry;
3777 eh->stub_sec = NULL;
0955507f 3778 eh->stub_offset = (bfd_vma) -1;
8d9d9490 3779 eh->source_value = 0;
906e58ca
NC		 3780 eh->target_value = 0;
3781 eh->target_section = NULL;
cedfb179 3782 eh->orig_insn = 0;
906e58ca 3783 eh->stub_type = arm_stub_none;
461a49ca
DJ		 3784 eh->stub_size = 0;
3785 eh->stub_template = NULL;
0955507f 3786 eh->stub_template_size = -1;
906e58ca
NC		 3787 eh->h = NULL;
3788 eh->id_sec = NULL;
d8d2f433 3789 eh->output_name = NULL;
906e58ca
NC		 3790 }
3791
3792 return entry;
3793}
3794
00a97672 3795/* Create .got, .gotplt, and .rel(a).got sections in DYNOBJ, and set up
5e681ec4
PB		 3796 shortcuts to them in our hash table. */
3797
3798static bfd_boolean
57e8b36a 3799create_got_section (bfd *dynobj, struct bfd_link_info *info)
5e681ec4
PB		 3800{
3801 struct elf32_arm_link_hash_table *htab;
3802
e5a52504 3803 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 3804 if (htab == NULL)
3805 return FALSE;
3806
e5a52504
MM		 3807 /* BPABI objects never have a GOT, or associated sections. */
3808 if (htab->symbian_p)
3809 return TRUE;
3810
5e681ec4
PB		 3811 if (! _bfd_elf_create_got_section (dynobj, info))
3812 return FALSE;
3813
e8b09b87
CL		 3814 /* Also create .rofixup. */
3815 if (htab->fdpic_p)
3816 {
3817 htab->srofixup = bfd_make_section_with_flags (dynobj, ".rofixup",
3818 (SEC_ALLOC | SEC_LOAD | SEC_HAS_CONTENTS
3819 | SEC_IN_MEMORY | SEC_LINKER_CREATED | SEC_READONLY));
fd361982
AM		 3820 if (htab->srofixup == NULL
3821 || !bfd_set_section_alignment (htab->srofixup, 2))
e8b09b87
CL		 3822 return FALSE;
3823 }
3824
5e681ec4
PB		 3825 return TRUE;
3826}
3827
34e77a92
RS		 3828/* Create the .iplt, .rel(a).iplt and .igot.plt sections. */
3829
3830static bfd_boolean
3831create_ifunc_sections (struct bfd_link_info *info)
3832{
3833 struct elf32_arm_link_hash_table *htab;
3834 const struct elf_backend_data *bed;
3835 bfd *dynobj;
3836 asection *s;
3837 flagword flags;
b38cadfb 3838
34e77a92
RS		 3839 htab = elf32_arm_hash_table (info);
3840 dynobj = htab->root.dynobj;
3841 bed = get_elf_backend_data (dynobj);
3842 flags = bed->dynamic_sec_flags;
3843
3844 if (htab->root.iplt == NULL)
3845 {
3d4d4302
AM		 3846 s = bfd_make_section_anyway_with_flags (dynobj, ".iplt",
3847 flags | SEC_READONLY | SEC_CODE);
34e77a92 3848 if (s == NULL
fd361982 3849 || !bfd_set_section_alignment (s, bed->plt_alignment))
34e77a92
RS		 3850 return FALSE;
3851 htab->root.iplt = s;
3852 }
3853
3854 if (htab->root.irelplt == NULL)
3855 {
3d4d4302
AM		 3856 s = bfd_make_section_anyway_with_flags (dynobj,
3857 RELOC_SECTION (htab, ".iplt"),
3858 flags | SEC_READONLY);
34e77a92 3859 if (s == NULL
fd361982 3860 || !bfd_set_section_alignment (s, bed->s->log_file_align))
34e77a92
RS		 3861 return FALSE;
3862 htab->root.irelplt = s;
3863 }
3864
3865 if (htab->root.igotplt == NULL)
3866 {
3d4d4302 3867 s = bfd_make_section_anyway_with_flags (dynobj, ".igot.plt", flags);
34e77a92 3868 if (s == NULL
fd361982 3869 || !bfd_set_section_alignment (s, bed->s->log_file_align))
34e77a92
RS		 3870 return FALSE;
3871 htab->root.igotplt = s;
3872 }
3873 return TRUE;
3874}
3875
eed94f8f
NC		 3876/* Determine if we're dealing with a Thumb only architecture. */
3877
3878static bfd_boolean
3879using_thumb_only (struct elf32_arm_link_hash_table *globals)
3880{
2fd158eb
TP		 3881 int arch;
3882 int profile = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC,
3883 Tag_CPU_arch_profile);
eed94f8f 3884
2fd158eb
TP		 3885 if (profile)
3886 return profile == 'M';
eed94f8f 3887
2fd158eb 3888 arch = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC, Tag_CPU_arch);
eed94f8f 3889
60a019a0 3890 /* Force return logic to be reviewed for each new architecture. */
031254f2 3891 BFD_ASSERT (arch <= TAG_CPU_ARCH_V8_1M_MAIN);
60a019a0 3892
2fd158eb
TP		 3893 if (arch == TAG_CPU_ARCH_V6_M
3894 || arch == TAG_CPU_ARCH_V6S_M
3895 || arch == TAG_CPU_ARCH_V7E_M
3896 || arch == TAG_CPU_ARCH_V8M_BASE
031254f2
AV		 3897 || arch == TAG_CPU_ARCH_V8M_MAIN
3898 || arch == TAG_CPU_ARCH_V8_1M_MAIN)
2fd158eb 3899 return TRUE;
eed94f8f 3900
2fd158eb 3901 return FALSE;
eed94f8f
NC		 3902}
3903
3904/* Determine if we're dealing with a Thumb-2 object. */
3905
3906static bfd_boolean
3907using_thumb2 (struct elf32_arm_link_hash_table *globals)
3908{
60a019a0
TP		 3909 int arch;
3910 int thumb_isa = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC,
3911 Tag_THUMB_ISA_use);
3912
3913 if (thumb_isa)
3914 return thumb_isa == 2;
3915
3916 arch = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC, Tag_CPU_arch);
3917
3918 /* Force return logic to be reviewed for each new architecture. */
031254f2 3919 BFD_ASSERT (arch <= TAG_CPU_ARCH_V8_1M_MAIN);
60a019a0
TP		 3920
3921 return (arch == TAG_CPU_ARCH_V6T2
3922 || arch == TAG_CPU_ARCH_V7
3923 || arch == TAG_CPU_ARCH_V7E_M
3924 || arch == TAG_CPU_ARCH_V8
bff0500d 3925 || arch == TAG_CPU_ARCH_V8R
031254f2
AV		 3926 || arch == TAG_CPU_ARCH_V8M_MAIN
3927 || arch == TAG_CPU_ARCH_V8_1M_MAIN);
eed94f8f
NC		 3928}
3929
5e866f5a
TP		 3930/* Determine whether Thumb-2 BL instruction is available. */
3931
3932static bfd_boolean
3933using_thumb2_bl (struct elf32_arm_link_hash_table *globals)
3934{
3935 int arch =
3936 bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC, Tag_CPU_arch);
3937
3938 /* Force return logic to be reviewed for each new architecture. */
031254f2 3939 BFD_ASSERT (arch <= TAG_CPU_ARCH_V8_1M_MAIN);
5e866f5a
TP		 3940
3941 /* Architecture was introduced after ARMv6T2 (eg. ARMv6-M). */
3942 return (arch == TAG_CPU_ARCH_V6T2
3943 || arch >= TAG_CPU_ARCH_V7);
3944}
3945
00a97672
RS		 3946/* Create .plt, .rel(a).plt, .got, .got.plt, .rel(a).got, .dynbss, and
3947 .rel(a).bss sections in DYNOBJ, and set up shortcuts to them in our
5e681ec4
PB		 3948 hash table. */
3949
3950static bfd_boolean
57e8b36a 3951elf32_arm_create_dynamic_sections (bfd *dynobj, struct bfd_link_info *info)
5e681ec4
PB		 3952{
3953 struct elf32_arm_link_hash_table *htab;
3954
3955 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 3956 if (htab == NULL)
3957 return FALSE;
3958
362d30a1 3959 if (!htab->root.sgot && !create_got_section (dynobj, info))
5e681ec4
PB		 3960 return FALSE;
3961
3962 if (!_bfd_elf_create_dynamic_sections (dynobj, info))
3963 return FALSE;
3964
00a97672
RS		 3965 if (htab->vxworks_p)
3966 {
3967 if (!elf_vxworks_create_dynamic_sections (dynobj, info, &htab->srelplt2))
3968 return FALSE;
3969
0e1862bb 3970 if (bfd_link_pic (info))
00a97672
RS		 3971 {
3972 htab->plt_header_size = 0;
3973 htab->plt_entry_size
3974 = 4 * ARRAY_SIZE (elf32_arm_vxworks_shared_plt_entry);
3975 }
3976 else
3977 {
3978 htab->plt_header_size
3979 = 4 * ARRAY_SIZE (elf32_arm_vxworks_exec_plt0_entry);
3980 htab->plt_entry_size
3981 = 4 * ARRAY_SIZE (elf32_arm_vxworks_exec_plt_entry);
3982 }
aebf9be7
NC		 3983
3984 if (elf_elfheader (dynobj))
3985 elf_elfheader (dynobj)->e_ident[EI_CLASS] = ELFCLASS32;
00a97672 3986 }
eed94f8f
NC		 3987 else
3988 {
3989 /* PR ld/16017
3990 Test for thumb only architectures. Note - we cannot just call
3991 using_thumb_only() as the attributes in the output bfd have not been
3992 initialised at this point, so instead we use the input bfd. */
3993 bfd * saved_obfd = htab->obfd;
3994
3995 htab->obfd = dynobj;
3996 if (using_thumb_only (htab))
3997 {
3998 htab->plt_header_size = 4 * ARRAY_SIZE (elf32_thumb2_plt0_entry);
3999 htab->plt_entry_size = 4 * ARRAY_SIZE (elf32_thumb2_plt_entry);
4000 }
4001 htab->obfd = saved_obfd;
4002 }
5e681ec4 4003
7801f98f
CL		 4004 if (htab->fdpic_p) {
4005 htab->plt_header_size = 0;
4006 if (info->flags & DF_BIND_NOW)
4007 htab->plt_entry_size = 4 * (ARRAY_SIZE(elf32_arm_fdpic_plt_entry) - 5);
4008 else
4009 htab->plt_entry_size = 4 * ARRAY_SIZE(elf32_arm_fdpic_plt_entry);
4010 }
4011
362d30a1
RS		 4012 if (!htab->root.splt
4013 || !htab->root.srelplt
9d19e4fd
AM		 4014 || !htab->root.sdynbss
4015 || (!bfd_link_pic (info) && !htab->root.srelbss))
5e681ec4
PB		 4016 abort ();
4017
4018 return TRUE;
4019}
4020
906e58ca
NC		 4021/* Copy the extra info we tack onto an elf_link_hash_entry. */
4022
4023static void
4024elf32_arm_copy_indirect_symbol (struct bfd_link_info *info,
4025 struct elf_link_hash_entry *dir,
4026 struct elf_link_hash_entry *ind)
4027{
4028 struct elf32_arm_link_hash_entry *edir, *eind;
4029
4030 edir = (struct elf32_arm_link_hash_entry *) dir;
4031 eind = (struct elf32_arm_link_hash_entry *) ind;
4032
0bdcacaf 4033 if (eind->dyn_relocs != NULL)
906e58ca 4034 {
0bdcacaf 4035 if (edir->dyn_relocs != NULL)
906e58ca 4036 {
0bdcacaf
RS		 4037 struct elf_dyn_relocs **pp;
4038 struct elf_dyn_relocs *p;
906e58ca
NC		 4039
4040 /* Add reloc counts against the indirect sym to the direct sym
4041 list. Merge any entries against the same section. */
0bdcacaf 4042 for (pp = &eind->dyn_relocs; (p = *pp) != NULL; )
906e58ca 4043 {
0bdcacaf 4044 struct elf_dyn_relocs *q;
906e58ca 4045
0bdcacaf
RS		 4046 for (q = edir->dyn_relocs; q != NULL; q = q->next)
4047 if (q->sec == p->sec)
906e58ca
NC		 4048 {
4049 q->pc_count += p->pc_count;
4050 q->count += p->count;
4051 *pp = p->next;
4052 break;
4053 }
4054 if (q == NULL)
4055 pp = &p->next;
4056 }
0bdcacaf 4057 *pp = edir->dyn_relocs;
906e58ca
NC		 4058 }
4059
0bdcacaf
RS		 4060 edir->dyn_relocs = eind->dyn_relocs;
4061 eind->dyn_relocs = NULL;
906e58ca
NC		 4062 }
4063
4064 if (ind->root.type == bfd_link_hash_indirect)
4065 {
4066 /* Copy over PLT info. */
34e77a92
RS		 4067 edir->plt.thumb_refcount += eind->plt.thumb_refcount;
4068 eind->plt.thumb_refcount = 0;
4069 edir->plt.maybe_thumb_refcount += eind->plt.maybe_thumb_refcount;
4070 eind->plt.maybe_thumb_refcount = 0;
4071 edir->plt.noncall_refcount += eind->plt.noncall_refcount;
4072 eind->plt.noncall_refcount = 0;
4073
e8b09b87
CL		 4074 /* Copy FDPIC counters. */
4075 edir->fdpic_cnts.gotofffuncdesc_cnt += eind->fdpic_cnts.gotofffuncdesc_cnt;
4076 edir->fdpic_cnts.gotfuncdesc_cnt += eind->fdpic_cnts.gotfuncdesc_cnt;
4077 edir->fdpic_cnts.funcdesc_cnt += eind->fdpic_cnts.funcdesc_cnt;
4078
34e77a92
RS		 4079 /* We should only allocate a function to .iplt once the final
4080 symbol information is known. */
4081 BFD_ASSERT (!eind->is_iplt);
906e58ca
NC		 4082
4083 if (dir->got.refcount <= 0)
4084 {
4085 edir->tls_type = eind->tls_type;
4086 eind->tls_type = GOT_UNKNOWN;
4087 }
4088 }
4089
4090 _bfd_elf_link_hash_copy_indirect (info, dir, ind);
4091}
4092
68faa637
AM		 4093/* Destroy an ARM elf linker hash table. */
4094
4095static void
d495ab0d 4096elf32_arm_link_hash_table_free (bfd *obfd)
68faa637
AM		 4097{
4098 struct elf32_arm_link_hash_table *ret
d495ab0d 4099 = (struct elf32_arm_link_hash_table *) obfd->link.hash;
68faa637
AM		 4100
4101 bfd_hash_table_free (&ret->stub_hash_table);
d495ab0d 4102 _bfd_elf_link_hash_table_free (obfd);
68faa637
AM		 4103}
4104
906e58ca
NC		 4105/* Create an ARM elf linker hash table. */
4106
4107static struct bfd_link_hash_table *
4108elf32_arm_link_hash_table_create (bfd *abfd)
4109{
4110 struct elf32_arm_link_hash_table *ret;
4111 bfd_size_type amt = sizeof (struct elf32_arm_link_hash_table);
4112
7bf52ea2 4113 ret = (struct elf32_arm_link_hash_table *) bfd_zmalloc (amt);
906e58ca
NC		 4114 if (ret == NULL)
4115 return NULL;
4116
4117 if (!_bfd_elf_link_hash_table_init (& ret->root, abfd,
4118 elf32_arm_link_hash_newfunc,
4dfe6ac6
NC		 4119 sizeof (struct elf32_arm_link_hash_entry),
4120 ARM_ELF_DATA))
906e58ca
NC		 4121 {
4122 free (ret);
4123 return NULL;
4124 }
4125
906e58ca 4126 ret->vfp11_fix = BFD_ARM_VFP11_FIX_NONE;
a504d23a 4127 ret->stm32l4xx_fix = BFD_ARM_STM32L4XX_FIX_NONE;
906e58ca
NC		 4128#ifdef FOUR_WORD_PLT
4129 ret->plt_header_size = 16;
4130 ret->plt_entry_size = 16;
4131#else
4132 ret->plt_header_size = 20;
1db37fe6 4133 ret->plt_entry_size = elf32_arm_use_long_plt_entry ? 16 : 12;
906e58ca 4134#endif
f3185997 4135 ret->use_rel = TRUE;
906e58ca 4136 ret->obfd = abfd;
617a5ada 4137 ret->fdpic_p = 0;
906e58ca
NC		 4138
4139 if (!bfd_hash_table_init (&ret->stub_hash_table, stub_hash_newfunc,
4140 sizeof (struct elf32_arm_stub_hash_entry)))
4141 {
d495ab0d 4142 _bfd_elf_link_hash_table_free (abfd);
906e58ca
NC		 4143 return NULL;
4144 }
d495ab0d 4145 ret->root.root.hash_table_free = elf32_arm_link_hash_table_free;
906e58ca
NC		 4146
4147 return &ret->root.root;
4148}
4149
cd1dac3d
DG		 4150/* Determine what kind of NOPs are available. */
4151
4152static bfd_boolean
4153arch_has_arm_nop (struct elf32_arm_link_hash_table *globals)
4154{
4155 const int arch = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC,
4156 Tag_CPU_arch);
cd1dac3d 4157
60a019a0 4158 /* Force return logic to be reviewed for each new architecture. */
031254f2 4159 BFD_ASSERT (arch <= TAG_CPU_ARCH_V8_1M_MAIN);
60a019a0
TP		 4160
4161 return (arch == TAG_CPU_ARCH_V6T2
4162 || arch == TAG_CPU_ARCH_V6K
4163 || arch == TAG_CPU_ARCH_V7
bff0500d
TP		 4164 || arch == TAG_CPU_ARCH_V8
4165 || arch == TAG_CPU_ARCH_V8R);
cd1dac3d
DG		 4166}
4167
f4ac8484
DJ		 4168static bfd_boolean
4169arm_stub_is_thumb (enum elf32_arm_stub_type stub_type)
4170{
4171 switch (stub_type)
4172 {
fea2b4d6 4173 case arm_stub_long_branch_thumb_only:
80c135e5 4174 case arm_stub_long_branch_thumb2_only:
d5a67c02 4175 case arm_stub_long_branch_thumb2_only_pure:
fea2b4d6
CL		 4176 case arm_stub_long_branch_v4t_thumb_arm:
4177 case arm_stub_short_branch_v4t_thumb_arm:
ebe24dd4 4178 case arm_stub_long_branch_v4t_thumb_arm_pic:
12352d3f 4179 case arm_stub_long_branch_v4t_thumb_tls_pic:
ebe24dd4 4180 case arm_stub_long_branch_thumb_only_pic:
4ba2ef8f 4181 case arm_stub_cmse_branch_thumb_only:
f4ac8484
DJ		 4182 return TRUE;
4183 case arm_stub_none:
4184 BFD_FAIL ();
4185 return FALSE;
4186 break;
4187 default:
4188 return FALSE;
4189 }
4190}
4191
906e58ca
NC		 4192/* Determine the type of stub needed, if any, for a call. */
4193
4194static enum elf32_arm_stub_type
4195arm_type_of_stub (struct bfd_link_info *info,
4196 asection *input_sec,
4197 const Elf_Internal_Rela *rel,
34e77a92 4198 unsigned char st_type,
35fc36a8 4199 enum arm_st_branch_type *actual_branch_type,
906e58ca 4200 struct elf32_arm_link_hash_entry *hash,
c820be07
NC		 4201 bfd_vma destination,
4202 asection *sym_sec,
4203 bfd *input_bfd,
4204 const char *name)
906e58ca
NC		 4205{
4206 bfd_vma location;
4207 bfd_signed_vma branch_offset;
4208 unsigned int r_type;
4209 struct elf32_arm_link_hash_table * globals;
5e866f5a 4210 bfd_boolean thumb2, thumb2_bl, thumb_only;
906e58ca 4211 enum elf32_arm_stub_type stub_type = arm_stub_none;
5fa9e92f 4212 int use_plt = 0;
35fc36a8 4213 enum arm_st_branch_type branch_type = *actual_branch_type;
34e77a92
RS		 4214 union gotplt_union *root_plt;
4215 struct arm_plt_info *arm_plt;
d5a67c02
AV		 4216 int arch;
4217 int thumb2_movw;
906e58ca 4218
35fc36a8 4219 if (branch_type == ST_BRANCH_LONG)
da5938a2
NC		 4220 return stub_type;
4221
906e58ca 4222 globals = elf32_arm_hash_table (info);
4dfe6ac6
NC		 4223 if (globals == NULL)
4224 return stub_type;
906e58ca
NC		 4225
4226 thumb_only = using_thumb_only (globals);
906e58ca 4227 thumb2 = using_thumb2 (globals);
5e866f5a 4228 thumb2_bl = using_thumb2_bl (globals);
906e58ca 4229
d5a67c02
AV		 4230 arch = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC, Tag_CPU_arch);
4231
4232 /* True for architectures that implement the thumb2 movw instruction. */
4233 thumb2_movw = thumb2 || (arch == TAG_CPU_ARCH_V8M_BASE);
4234
906e58ca
NC		 4235 /* Determine where the call point is. */
4236 location = (input_sec->output_offset
4237 + input_sec->output_section->vma
4238 + rel->r_offset);
4239
906e58ca
NC		 4240 r_type = ELF32_R_TYPE (rel->r_info);
4241
39f21624
NC		 4242 /* ST_BRANCH_TO_ARM is nonsense to thumb-only targets when we
4243 are considering a function call relocation. */
c5423981 4244 if (thumb_only && (r_type == R_ARM_THM_CALL || r_type == R_ARM_THM_JUMP24
07d6d2b8 4245 || r_type == R_ARM_THM_JUMP19)
39f21624
NC		 4246 && branch_type == ST_BRANCH_TO_ARM)
4247 branch_type = ST_BRANCH_TO_THUMB;
4248
34e77a92
RS		 4249 /* For TLS call relocs, it is the caller's responsibility to provide
4250 the address of the appropriate trampoline. */
4251 if (r_type != R_ARM_TLS_CALL
4252 && r_type != R_ARM_THM_TLS_CALL
4ba2ef8f
TP		 4253 && elf32_arm_get_plt_info (input_bfd, globals, hash,
4254 ELF32_R_SYM (rel->r_info), &root_plt,
4255 &arm_plt)
34e77a92 4256 && root_plt->offset != (bfd_vma) -1)
5fa9e92f 4257 {
34e77a92 4258 asection *splt;
fe33d2fa 4259
34e77a92
RS		 4260 if (hash == NULL || hash->is_iplt)
4261 splt = globals->root.iplt;
4262 else
4263 splt = globals->root.splt;
4264 if (splt != NULL)
b38cadfb 4265 {
34e77a92
RS		 4266 use_plt = 1;
4267
4268 /* Note when dealing with PLT entries: the main PLT stub is in
4269 ARM mode, so if the branch is in Thumb mode, another
4270 Thumb->ARM stub will be inserted later just before the ARM
2df2751d
CL		 4271 PLT stub. If a long branch stub is needed, we'll add a
4272 Thumb->Arm one and branch directly to the ARM PLT entry.
4273 Here, we have to check if a pre-PLT Thumb->ARM stub
4274 is needed and if it will be close enough. */
34e77a92
RS		 4275
4276 destination = (splt->output_section->vma
4277 + splt->output_offset
4278 + root_plt->offset);
4279 st_type = STT_FUNC;
2df2751d
CL		 4280
4281 /* Thumb branch/call to PLT: it can become a branch to ARM
4282 or to Thumb. We must perform the same checks and
4283 corrections as in elf32_arm_final_link_relocate. */
4284 if ((r_type == R_ARM_THM_CALL)
4285 || (r_type == R_ARM_THM_JUMP24))
4286 {
4287 if (globals->use_blx
4288 && r_type == R_ARM_THM_CALL
4289 && !thumb_only)
4290 {
4291 /* If the Thumb BLX instruction is available, convert
4292 the BL to a BLX instruction to call the ARM-mode
4293 PLT entry. */
4294 branch_type = ST_BRANCH_TO_ARM;
4295 }
4296 else
4297 {
4298 if (!thumb_only)
4299 /* Target the Thumb stub before the ARM PLT entry. */
4300 destination -= PLT_THUMB_STUB_SIZE;
4301 branch_type = ST_BRANCH_TO_THUMB;
4302 }
4303 }
4304 else
4305 {
4306 branch_type = ST_BRANCH_TO_ARM;
4307 }
34e77a92 4308 }
5fa9e92f 4309 }
34e77a92
RS		 4310 /* Calls to STT_GNU_IFUNC symbols should go through a PLT. */
4311 BFD_ASSERT (st_type != STT_GNU_IFUNC);
906e58ca 4312
fe33d2fa
CL		 4313 branch_offset = (bfd_signed_vma)(destination - location);
4314
0855e32b 4315 if (r_type == R_ARM_THM_CALL || r_type == R_ARM_THM_JUMP24
c5423981 4316 || r_type == R_ARM_THM_TLS_CALL || r_type == R_ARM_THM_JUMP19)
906e58ca 4317 {
5fa9e92f
CL		 4318 /* Handle cases where:
4319 - this call goes too far (different Thumb/Thumb2 max
99059e56 4320 distance)
155d87d7 4321 - it's a Thumb->Arm call and blx is not available, or it's a
99059e56
RM		 4322 Thumb->Arm branch (not bl). A stub is needed in this case,
4323 but only if this call is not through a PLT entry. Indeed,
695344c0 4324 PLT stubs handle mode switching already. */
5e866f5a 4325 if ((!thumb2_bl
906e58ca
NC		 4326 && (branch_offset > THM_MAX_FWD_BRANCH_OFFSET
4327 || (branch_offset < THM_MAX_BWD_BRANCH_OFFSET)))
5e866f5a 4328 || (thumb2_bl
906e58ca
NC		 4329 && (branch_offset > THM2_MAX_FWD_BRANCH_OFFSET
4330 || (branch_offset < THM2_MAX_BWD_BRANCH_OFFSET)))
c5423981
TG		 4331 || (thumb2
4332 && (branch_offset > THM2_MAX_FWD_COND_BRANCH_OFFSET
4333 || (branch_offset < THM2_MAX_BWD_COND_BRANCH_OFFSET))
4334 && (r_type == R_ARM_THM_JUMP19))
35fc36a8 4335 || (branch_type == ST_BRANCH_TO_ARM
0855e32b
NS		 4336 && (((r_type == R_ARM_THM_CALL
4337 || r_type == R_ARM_THM_TLS_CALL) && !globals->use_blx)
c5423981 4338 || (r_type == R_ARM_THM_JUMP24)
07d6d2b8 4339 || (r_type == R_ARM_THM_JUMP19))
5fa9e92f 4340 && !use_plt))
906e58ca 4341 {
2df2751d
CL		 4342 /* If we need to insert a Thumb-Thumb long branch stub to a
4343 PLT, use one that branches directly to the ARM PLT
4344 stub. If we pretended we'd use the pre-PLT Thumb->ARM
4345 stub, undo this now. */
695344c0
NC		 4346 if ((branch_type == ST_BRANCH_TO_THUMB) && use_plt && !thumb_only)
4347 {
4348 branch_type = ST_BRANCH_TO_ARM;
4349 branch_offset += PLT_THUMB_STUB_SIZE;
4350 }
2df2751d 4351
35fc36a8 4352 if (branch_type == ST_BRANCH_TO_THUMB)
906e58ca
NC		 4353 {
4354 /* Thumb to thumb. */
4355 if (!thumb_only)
4356 {
d5a67c02 4357 if (input_sec->flags & SEC_ELF_PURECODE)
10463f39 4358 _bfd_error_handler
871b3ab2 4359 (_("%pB(%pA): warning: long branch veneers used in"
10463f39
AM		 4360 " section with SHF_ARM_PURECODE section"
4361 " attribute is only supported for M-profile"
90b6238f 4362 " targets that implement the movw instruction"),
10463f39 4363 input_bfd, input_sec);
d5a67c02 4364
0e1862bb 4365 stub_type = (bfd_link_pic (info) | globals->pic_veneer)
c2b4a39d 4366 /* PIC stubs. */
155d87d7 4367 ? ((globals->use_blx
9553db3c 4368 && (r_type == R_ARM_THM_CALL))
155d87d7
CL		 4369 /* V5T and above. Stub starts with ARM code, so
4370 we must be able to switch mode before
4371 reaching it, which is only possible for 'bl'
4372 (ie R_ARM_THM_CALL relocation). */
cf3eccff 4373 ? arm_stub_long_branch_any_thumb_pic
ebe24dd4 4374 /* On V4T, use Thumb code only. */
d3626fb0 4375 : arm_stub_long_branch_v4t_thumb_thumb_pic)
c2b4a39d
CL		 4376
4377 /* non-PIC stubs. */
155d87d7 4378 : ((globals->use_blx
9553db3c 4379 && (r_type == R_ARM_THM_CALL))
c2b4a39d
CL		 4380 /* V5T and above. */
4381 ? arm_stub_long_branch_any_any
4382 /* V4T. */
d3626fb0 4383 : arm_stub_long_branch_v4t_thumb_thumb);
906e58ca
NC		 4384 }
4385 else
4386 {
d5a67c02
AV		 4387 if (thumb2_movw && (input_sec->flags & SEC_ELF_PURECODE))
4388 stub_type = arm_stub_long_branch_thumb2_only_pure;
4389 else
4390 {
4391 if (input_sec->flags & SEC_ELF_PURECODE)
10463f39 4392 _bfd_error_handler
871b3ab2 4393 (_("%pB(%pA): warning: long branch veneers used in"
10463f39
AM		 4394 " section with SHF_ARM_PURECODE section"
4395 " attribute is only supported for M-profile"
90b6238f 4396 " targets that implement the movw instruction"),
10463f39 4397 input_bfd, input_sec);
d5a67c02
AV		 4398
4399 stub_type = (bfd_link_pic (info) | globals->pic_veneer)
4400 /* PIC stub. */
4401 ? arm_stub_long_branch_thumb_only_pic
4402 /* non-PIC stub. */
4403 : (thumb2 ? arm_stub_long_branch_thumb2_only
4404 : arm_stub_long_branch_thumb_only);
4405 }
906e58ca
NC		 4406 }
4407 }
4408 else
4409 {
d5a67c02 4410 if (input_sec->flags & SEC_ELF_PURECODE)
10463f39 4411 _bfd_error_handler
871b3ab2 4412 (_("%pB(%pA): warning: long branch veneers used in"
10463f39
AM		 4413 " section with SHF_ARM_PURECODE section"
4414 " attribute is only supported" " for M-profile"
90b6238f 4415 " targets that implement the movw instruction"),
10463f39 4416 input_bfd, input_sec);
d5a67c02 4417
906e58ca 4418 /* Thumb to arm. */
c820be07
NC		 4419 if (sym_sec != NULL
4420 && sym_sec->owner != NULL
4421 && !INTERWORK_FLAG (sym_sec->owner))
4422 {
4eca0228 4423 _bfd_error_handler
90b6238f
AM		 4424 (_("%pB(%s): warning: interworking not enabled;"
4425 " first occurrence: %pB: %s call to %s"),
4426 sym_sec->owner, name, input_bfd, "Thumb", "ARM");
c820be07
NC		 4427 }
4428
0855e32b 4429 stub_type =
0e1862bb 4430 (bfd_link_pic (info) | globals->pic_veneer)
c2b4a39d 4431 /* PIC stubs. */
0855e32b 4432 ? (r_type == R_ARM_THM_TLS_CALL
6a631e86 4433 /* TLS PIC stubs. */
0855e32b
NS		 4434 ? (globals->use_blx ? arm_stub_long_branch_any_tls_pic
4435 : arm_stub_long_branch_v4t_thumb_tls_pic)
4436 : ((globals->use_blx && r_type == R_ARM_THM_CALL)
4437 /* V5T PIC and above. */
4438 ? arm_stub_long_branch_any_arm_pic
4439 /* V4T PIC stub. */
4440 : arm_stub_long_branch_v4t_thumb_arm_pic))
c2b4a39d
CL		 4441
4442 /* non-PIC stubs. */
0855e32b 4443 : ((globals->use_blx && r_type == R_ARM_THM_CALL)
c2b4a39d
CL		 4444 /* V5T and above. */
4445 ? arm_stub_long_branch_any_any
4446 /* V4T. */
4447 : arm_stub_long_branch_v4t_thumb_arm);
c820be07
NC		 4448
4449 /* Handle v4t short branches. */
fea2b4d6 4450 if ((stub_type == arm_stub_long_branch_v4t_thumb_arm)
c820be07
NC		 4451 && (branch_offset <= THM_MAX_FWD_BRANCH_OFFSET)
4452 && (branch_offset >= THM_MAX_BWD_BRANCH_OFFSET))
fea2b4d6 4453 stub_type = arm_stub_short_branch_v4t_thumb_arm;
906e58ca
NC		 4454 }
4455 }
4456 }
fe33d2fa
CL		 4457 else if (r_type == R_ARM_CALL
4458 || r_type == R_ARM_JUMP24
0855e32b
NS		 4459 || r_type == R_ARM_PLT32
4460 || r_type == R_ARM_TLS_CALL)
906e58ca 4461 {
d5a67c02 4462 if (input_sec->flags & SEC_ELF_PURECODE)
10463f39 4463 _bfd_error_handler
871b3ab2 4464 (_("%pB(%pA): warning: long branch veneers used in"
10463f39
AM		 4465 " section with SHF_ARM_PURECODE section"
4466 " attribute is only supported for M-profile"
90b6238f 4467 " targets that implement the movw instruction"),
10463f39 4468 input_bfd, input_sec);
35fc36a8 4469 if (branch_type == ST_BRANCH_TO_THUMB)
906e58ca
NC		 4470 {
4471 /* Arm to thumb. */
c820be07
NC		 4472
4473 if (sym_sec != NULL
4474 && sym_sec->owner != NULL
4475 && !INTERWORK_FLAG (sym_sec->owner))
4476 {
4eca0228 4477 _bfd_error_handler
90b6238f
AM		 4478 (_("%pB(%s): warning: interworking not enabled;"
4479 " first occurrence: %pB: %s call to %s"),
4480 sym_sec->owner, name, input_bfd, "ARM", "Thumb");
c820be07
NC		 4481 }
4482
4483 /* We have an extra 2-bytes reach because of
4484 the mode change (bit 24 (H) of BLX encoding). */
4116d8d7
PB		 4485 if (branch_offset > (ARM_MAX_FWD_BRANCH_OFFSET + 2)
4486 || (branch_offset < ARM_MAX_BWD_BRANCH_OFFSET)
0855e32b 4487 || (r_type == R_ARM_CALL && !globals->use_blx)
4116d8d7
PB		 4488 || (r_type == R_ARM_JUMP24)
4489 || (r_type == R_ARM_PLT32))
906e58ca 4490 {
0e1862bb 4491 stub_type = (bfd_link_pic (info) | globals->pic_veneer)
c2b4a39d 4492 /* PIC stubs. */
ebe24dd4
CL		 4493 ? ((globals->use_blx)
4494 /* V5T and above. */
4495 ? arm_stub_long_branch_any_thumb_pic
4496 /* V4T stub. */
4497 : arm_stub_long_branch_v4t_arm_thumb_pic)
4498
c2b4a39d
CL		 4499 /* non-PIC stubs. */
4500 : ((globals->use_blx)
4501 /* V5T and above. */
4502 ? arm_stub_long_branch_any_any
4503 /* V4T. */
4504 : arm_stub_long_branch_v4t_arm_thumb);
906e58ca
NC		 4505 }
4506 }
4507 else
4508 {
4509 /* Arm to arm. */
4510 if (branch_offset > ARM_MAX_FWD_BRANCH_OFFSET
4511 || (branch_offset < ARM_MAX_BWD_BRANCH_OFFSET))
4512 {
0855e32b 4513 stub_type =
0e1862bb 4514 (bfd_link_pic (info) | globals->pic_veneer)
c2b4a39d 4515 /* PIC stubs. */
0855e32b 4516 ? (r_type == R_ARM_TLS_CALL
6a631e86 4517 /* TLS PIC Stub. */
0855e32b 4518 ? arm_stub_long_branch_any_tls_pic
7a89b94e
NC		 4519 : (globals->nacl_p
4520 ? arm_stub_long_branch_arm_nacl_pic
4521 : arm_stub_long_branch_any_arm_pic))
c2b4a39d 4522 /* non-PIC stubs. */
7a89b94e
NC		 4523 : (globals->nacl_p
4524 ? arm_stub_long_branch_arm_nacl
4525 : arm_stub_long_branch_any_any);
906e58ca
NC		 4526 }
4527 }
4528 }
4529
fe33d2fa
CL		 4530 /* If a stub is needed, record the actual destination type. */
4531 if (stub_type != arm_stub_none)
35fc36a8 4532 *actual_branch_type = branch_type;
fe33d2fa 4533
906e58ca
NC		 4534 return stub_type;
4535}
4536
4537/* Build a name for an entry in the stub hash table. */
4538
4539static char *
4540elf32_arm_stub_name (const asection *input_section,
4541 const asection *sym_sec,
4542 const struct elf32_arm_link_hash_entry *hash,
fe33d2fa
CL		 4543 const Elf_Internal_Rela *rel,
4544 enum elf32_arm_stub_type stub_type)
906e58ca
NC		 4545{
4546 char *stub_name;
4547 bfd_size_type len;
4548
4549 if (hash)
4550 {
fe33d2fa 4551 len = 8 + 1 + strlen (hash->root.root.root.string) + 1 + 8 + 1 + 2 + 1;
21d799b5 4552 stub_name = (char *) bfd_malloc (len);
906e58ca 4553 if (stub_name != NULL)
fe33d2fa 4554 sprintf (stub_name, "%08x_%s+%x_%d",
906e58ca
NC		 4555 input_section->id & 0xffffffff,
4556 hash->root.root.root.string,
fe33d2fa
CL		 4557 (int) rel->r_addend & 0xffffffff,
4558 (int) stub_type);
906e58ca
NC		 4559 }
4560 else
4561 {
fe33d2fa 4562 len = 8 + 1 + 8 + 1 + 8 + 1 + 8 + 1 + 2 + 1;
21d799b5 4563 stub_name = (char *) bfd_malloc (len);
906e58ca 4564 if (stub_name != NULL)
fe33d2fa 4565 sprintf (stub_name, "%08x_%x:%x+%x_%d",
906e58ca
NC		 4566 input_section->id & 0xffffffff,
4567 sym_sec->id & 0xffffffff,
0855e32b
NS		 4568 ELF32_R_TYPE (rel->r_info) == R_ARM_TLS_CALL
4569 || ELF32_R_TYPE (rel->r_info) == R_ARM_THM_TLS_CALL
4570 ? 0 : (int) ELF32_R_SYM (rel->r_info) & 0xffffffff,
fe33d2fa
CL		 4571 (int) rel->r_addend & 0xffffffff,
4572 (int) stub_type);
906e58ca
NC		 4573 }
4574
4575 return stub_name;
4576}
4577
4578/* Look up an entry in the stub hash. Stub entries are cached because
4579 creating the stub name takes a bit of time. */
4580
4581static struct elf32_arm_stub_hash_entry *
4582elf32_arm_get_stub_entry (const asection *input_section,
4583 const asection *sym_sec,
4584 struct elf_link_hash_entry *hash,
4585 const Elf_Internal_Rela *rel,
fe33d2fa
CL		 4586 struct elf32_arm_link_hash_table *htab,
4587 enum elf32_arm_stub_type stub_type)
906e58ca
NC		 4588{
4589 struct elf32_arm_stub_hash_entry *stub_entry;
4590 struct elf32_arm_link_hash_entry *h = (struct elf32_arm_link_hash_entry *) hash;
4591 const asection *id_sec;
4592
4593 if ((input_section->flags & SEC_CODE) == 0)
4594 return NULL;
4595
4d83e8d9
CL		 4596 /* If the input section is the CMSE stubs one and it needs a long
4597 branch stub to reach it's final destination, give up with an
4598 error message: this is not supported. See PR ld/24709. */
4599 if (!strncmp (input_section->name, CMSE_STUB_NAME, strlen(CMSE_STUB_NAME)))
4600 {
4601 bfd *output_bfd = htab->obfd;
4602 asection *out_sec = bfd_get_section_by_name (output_bfd, CMSE_STUB_NAME);
4603
4604 _bfd_error_handler (_("ERROR: CMSE stub (%s section) too far "
4605 "(%#" PRIx64 ") from destination (%#" PRIx64 ")"),
4606 CMSE_STUB_NAME,
4607 (uint64_t)out_sec->output_section->vma
4608 + out_sec->output_offset,
4609 (uint64_t)sym_sec->output_section->vma
4610 + sym_sec->output_offset
4611 + h->root.root.u.def.value);
4612 /* Exit, rather than leave incompletely processed
4613 relocations. */
4614 xexit(1);
4615 }
4616
906e58ca
NC		 4617 /* If this input section is part of a group of sections sharing one
4618 stub section, then use the id of the first section in the group.
4619 Stub names need to include a section id, as there may well be
4620 more than one stub used to reach say, printf, and we need to
4621 distinguish between them. */
c2abbbeb 4622 BFD_ASSERT (input_section->id <= htab->top_id);
906e58ca
NC		 4623 id_sec = htab->stub_group[input_section->id].link_sec;
4624
4625 if (h != NULL && h->stub_cache != NULL
4626 && h->stub_cache->h == h
fe33d2fa
CL		 4627 && h->stub_cache->id_sec == id_sec
4628 && h->stub_cache->stub_type == stub_type)
906e58ca
NC		 4629 {
4630 stub_entry = h->stub_cache;
4631 }
4632 else
4633 {
4634 char *stub_name;
4635
fe33d2fa 4636 stub_name = elf32_arm_stub_name (id_sec, sym_sec, h, rel, stub_type);
906e58ca
NC		 4637 if (stub_name == NULL)
4638 return NULL;
4639
4640 stub_entry = arm_stub_hash_lookup (&htab->stub_hash_table,
4641 stub_name, FALSE, FALSE);
4642 if (h != NULL)
4643 h->stub_cache = stub_entry;
4644
4645 free (stub_name);
4646 }
4647
4648 return stub_entry;
4649}
4650
daa4adae
TP		 4651/* Whether veneers of type STUB_TYPE require to be in a dedicated output
4652 section. */
4653
4654static bfd_boolean
4655arm_dedicated_stub_output_section_required (enum elf32_arm_stub_type stub_type)
4656{
4657 if (stub_type >= max_stub_type)
4658 abort (); /* Should be unreachable. */
4659
4ba2ef8f
TP		 4660 switch (stub_type)
4661 {
4662 case arm_stub_cmse_branch_thumb_only:
4663 return TRUE;
4664
4665 default:
4666 return FALSE;
4667 }
4668
4669 abort (); /* Should be unreachable. */
daa4adae
TP		 4670}
4671
4672/* Required alignment (as a power of 2) for the dedicated section holding
4673 veneers of type STUB_TYPE, or 0 if veneers of this type are interspersed
4674 with input sections. */
4675
4676static int
4677arm_dedicated_stub_output_section_required_alignment
4678 (enum elf32_arm_stub_type stub_type)
4679{
4680 if (stub_type >= max_stub_type)
4681 abort (); /* Should be unreachable. */
4682
4ba2ef8f
TP		 4683 switch (stub_type)
4684 {
4685 /* Vectors of Secure Gateway veneers must be aligned on 32byte
4686 boundary. */
4687 case arm_stub_cmse_branch_thumb_only:
4688 return 5;
4689
4690 default:
4691 BFD_ASSERT (!arm_dedicated_stub_output_section_required (stub_type));
4692 return 0;
4693 }
4694
4695 abort (); /* Should be unreachable. */
daa4adae
TP		 4696}
4697
4698/* Name of the dedicated output section to put veneers of type STUB_TYPE, or
4699 NULL if veneers of this type are interspersed with input sections. */
4700
4701static const char *
4702arm_dedicated_stub_output_section_name (enum elf32_arm_stub_type stub_type)
4703{
4704 if (stub_type >= max_stub_type)
4705 abort (); /* Should be unreachable. */
4706
4ba2ef8f
TP		 4707 switch (stub_type)
4708 {
4709 case arm_stub_cmse_branch_thumb_only:
4d83e8d9 4710 return CMSE_STUB_NAME;
4ba2ef8f
TP		 4711
4712 default:
4713 BFD_ASSERT (!arm_dedicated_stub_output_section_required (stub_type));
4714 return NULL;
4715 }
4716
4717 abort (); /* Should be unreachable. */
daa4adae
TP		 4718}
4719
4720/* If veneers of type STUB_TYPE should go in a dedicated output section,
4721 returns the address of the hash table field in HTAB holding a pointer to the
4722 corresponding input section. Otherwise, returns NULL. */
4723
4724static asection **
4ba2ef8f
TP		 4725arm_dedicated_stub_input_section_ptr (struct elf32_arm_link_hash_table *htab,
4726 enum elf32_arm_stub_type stub_type)
daa4adae
TP		 4727{
4728 if (stub_type >= max_stub_type)
4729 abort (); /* Should be unreachable. */
4730
4ba2ef8f
TP		 4731 switch (stub_type)
4732 {
4733 case arm_stub_cmse_branch_thumb_only:
4734 return &htab->cmse_stub_sec;
4735
4736 default:
4737 BFD_ASSERT (!arm_dedicated_stub_output_section_required (stub_type));
4738 return NULL;
4739 }
4740
4741 abort (); /* Should be unreachable. */
daa4adae
TP		 4742}
4743
4744/* Find or create a stub section to contain a stub of type STUB_TYPE. SECTION
4745 is the section that branch into veneer and can be NULL if stub should go in
4746 a dedicated output section. Returns a pointer to the stub section, and the
4747 section to which the stub section will be attached (in *LINK_SEC_P).
48229727 4748 LINK_SEC_P may be NULL. */
906e58ca 4749
48229727
JB		 4750static asection *
4751elf32_arm_create_or_find_stub_sec (asection **link_sec_p, asection *section,
daa4adae
TP		 4752 struct elf32_arm_link_hash_table *htab,
4753 enum elf32_arm_stub_type stub_type)
906e58ca 4754{
daa4adae
TP		 4755 asection *link_sec, *out_sec, **stub_sec_p;
4756 const char *stub_sec_prefix;
4757 bfd_boolean dedicated_output_section =
4758 arm_dedicated_stub_output_section_required (stub_type);
4759 int align;
906e58ca 4760
daa4adae 4761 if (dedicated_output_section)
906e58ca 4762 {
daa4adae
TP		 4763 bfd *output_bfd = htab->obfd;
4764 const char *out_sec_name =
4765 arm_dedicated_stub_output_section_name (stub_type);
4766 link_sec = NULL;
4767 stub_sec_p = arm_dedicated_stub_input_section_ptr (htab, stub_type);
4768 stub_sec_prefix = out_sec_name;
4769 align = arm_dedicated_stub_output_section_required_alignment (stub_type);
4770 out_sec = bfd_get_section_by_name (output_bfd, out_sec_name);
4771 if (out_sec == NULL)
906e58ca 4772 {
90b6238f 4773 _bfd_error_handler (_("no address assigned to the veneers output "
4eca0228 4774 "section %s"), out_sec_name);
daa4adae 4775 return NULL;
906e58ca 4776 }
daa4adae
TP		 4777 }
4778 else
4779 {
c2abbbeb 4780 BFD_ASSERT (section->id <= htab->top_id);
daa4adae
TP		 4781 link_sec = htab->stub_group[section->id].link_sec;
4782 BFD_ASSERT (link_sec != NULL);
4783 stub_sec_p = &htab->stub_group[section->id].stub_sec;
4784 if (*stub_sec_p == NULL)
4785 stub_sec_p = &htab->stub_group[link_sec->id].stub_sec;
4786 stub_sec_prefix = link_sec->name;
4787 out_sec = link_sec->output_section;
4788 align = htab->nacl_p ? 4 : 3;
906e58ca 4789 }
b38cadfb 4790
daa4adae
TP		 4791 if (*stub_sec_p == NULL)
4792 {
4793 size_t namelen;
4794 bfd_size_type len;
4795 char *s_name;
4796
4797 namelen = strlen (stub_sec_prefix);
4798 len = namelen + sizeof (STUB_SUFFIX);
4799 s_name = (char *) bfd_alloc (htab->stub_bfd, len);
4800 if (s_name == NULL)
4801 return NULL;
4802
4803 memcpy (s_name, stub_sec_prefix, namelen);
4804 memcpy (s_name + namelen, STUB_SUFFIX, sizeof (STUB_SUFFIX));
4805 *stub_sec_p = (*htab->add_stub_section) (s_name, out_sec, link_sec,
4806 align);
4807 if (*stub_sec_p == NULL)
4808 return NULL;
4809
4810 out_sec->flags |= SEC_ALLOC | SEC_LOAD | SEC_READONLY | SEC_CODE
4811 | SEC_HAS_CONTENTS | SEC_RELOC | SEC_IN_MEMORY
4812 | SEC_KEEP;
4813 }
4814
4815 if (!dedicated_output_section)
4816 htab->stub_group[section->id].stub_sec = *stub_sec_p;
4817
48229727
JB		 4818 if (link_sec_p)
4819 *link_sec_p = link_sec;
b38cadfb 4820
daa4adae 4821 return *stub_sec_p;
48229727
JB		 4822}
4823
4824/* Add a new stub entry to the stub hash. Not all fields of the new
4825 stub entry are initialised. */
4826
4827static struct elf32_arm_stub_hash_entry *
daa4adae
TP		 4828elf32_arm_add_stub (const char *stub_name, asection *section,
4829 struct elf32_arm_link_hash_table *htab,
4830 enum elf32_arm_stub_type stub_type)
48229727
JB		 4831{
4832 asection *link_sec;
4833 asection *stub_sec;
4834 struct elf32_arm_stub_hash_entry *stub_entry;
4835
daa4adae
TP		 4836 stub_sec = elf32_arm_create_or_find_stub_sec (&link_sec, section, htab,
4837 stub_type);
48229727
JB		 4838 if (stub_sec == NULL)
4839 return NULL;
906e58ca
NC		 4840
4841 /* Enter this entry into the linker stub hash table. */
4842 stub_entry = arm_stub_hash_lookup (&htab->stub_hash_table, stub_name,
4843 TRUE, FALSE);
4844 if (stub_entry == NULL)
4845 {
6bde4c52
TP		 4846 if (section == NULL)
4847 section = stub_sec;
871b3ab2 4848 _bfd_error_handler (_("%pB: cannot create stub entry %s"),
4eca0228 4849 section->owner, stub_name);
906e58ca
NC		 4850 return NULL;
4851 }
4852
4853 stub_entry->stub_sec = stub_sec;
0955507f 4854 stub_entry->stub_offset = (bfd_vma) -1;
906e58ca
NC		 4855 stub_entry->id_sec = link_sec;
4856
906e58ca
NC		 4857 return stub_entry;
4858}
4859
4860/* Store an Arm insn into an output section not processed by
4861 elf32_arm_write_section. */
4862
4863static void
8029a119
NC		 4864put_arm_insn (struct elf32_arm_link_hash_table * htab,
4865 bfd * output_bfd, bfd_vma val, void * ptr)
906e58ca
NC		 4866{
4867 if (htab->byteswap_code != bfd_little_endian (output_bfd))
4868 bfd_putl32 (val, ptr);
4869 else
4870 bfd_putb32 (val, ptr);
4871}
4872
4873/* Store a 16-bit Thumb insn into an output section not processed by
4874 elf32_arm_write_section. */
4875
4876static void
8029a119
NC		 4877put_thumb_insn (struct elf32_arm_link_hash_table * htab,
4878 bfd * output_bfd, bfd_vma val, void * ptr)
906e58ca
NC		 4879{
4880 if (htab->byteswap_code != bfd_little_endian (output_bfd))
4881 bfd_putl16 (val, ptr);
4882 else
4883 bfd_putb16 (val, ptr);
4884}
4885
a504d23a
LA		 4886/* Store a Thumb2 insn into an output section not processed by
4887 elf32_arm_write_section. */
4888
4889static void
4890put_thumb2_insn (struct elf32_arm_link_hash_table * htab,
b98e6871 4891 bfd * output_bfd, bfd_vma val, bfd_byte * ptr)
a504d23a
LA		 4892{
4893 /* T2 instructions are 16-bit streamed. */
4894 if (htab->byteswap_code != bfd_little_endian (output_bfd))
4895 {
4896 bfd_putl16 ((val >> 16) & 0xffff, ptr);
4897 bfd_putl16 ((val & 0xffff), ptr + 2);
4898 }
4899 else
4900 {
4901 bfd_putb16 ((val >> 16) & 0xffff, ptr);
4902 bfd_putb16 ((val & 0xffff), ptr + 2);
4903 }
4904}
4905
0855e32b
NS		 4906/* If it's possible to change R_TYPE to a more efficient access
4907 model, return the new reloc type. */
4908
4909static unsigned
b38cadfb 4910elf32_arm_tls_transition (struct bfd_link_info *info, int r_type,
0855e32b
NS		 4911 struct elf_link_hash_entry *h)
4912{
4913 int is_local = (h == NULL);
4914
0e1862bb
L		 4915 if (bfd_link_pic (info)
4916 || (h && h->root.type == bfd_link_hash_undefweak))
0855e32b
NS		 4917 return r_type;
4918
b38cadfb 4919 /* We do not support relaxations for Old TLS models. */
0855e32b
NS		 4920 switch (r_type)
4921 {
4922 case R_ARM_TLS_GOTDESC:
4923 case R_ARM_TLS_CALL:
4924 case R_ARM_THM_TLS_CALL:
4925 case R_ARM_TLS_DESCSEQ:
4926 case R_ARM_THM_TLS_DESCSEQ:
4927 return is_local ? R_ARM_TLS_LE32 : R_ARM_TLS_IE32;
4928 }
4929
4930 return r_type;
4931}
4932
48229727
JB		 4933static bfd_reloc_status_type elf32_arm_final_link_relocate
4934 (reloc_howto_type *, bfd *, bfd *, asection *, bfd_byte *,
4935 Elf_Internal_Rela *, bfd_vma, struct bfd_link_info *, asection *,
34e77a92
RS		 4936 const char *, unsigned char, enum arm_st_branch_type,
4937 struct elf_link_hash_entry *, bfd_boolean *, char **);
48229727 4938
4563a860
JB		 4939static unsigned int
4940arm_stub_required_alignment (enum elf32_arm_stub_type stub_type)
4941{
4942 switch (stub_type)
4943 {
4944 case arm_stub_a8_veneer_b_cond:
4945 case arm_stub_a8_veneer_b:
4946 case arm_stub_a8_veneer_bl:
4947 return 2;
4948
4949 case arm_stub_long_branch_any_any:
4950 case arm_stub_long_branch_v4t_arm_thumb:
4951 case arm_stub_long_branch_thumb_only:
80c135e5 4952 case arm_stub_long_branch_thumb2_only:
d5a67c02 4953 case arm_stub_long_branch_thumb2_only_pure:
4563a860
JB		 4954 case arm_stub_long_branch_v4t_thumb_thumb:
4955 case arm_stub_long_branch_v4t_thumb_arm:
4956 case arm_stub_short_branch_v4t_thumb_arm:
4957 case arm_stub_long_branch_any_arm_pic:
4958 case arm_stub_long_branch_any_thumb_pic:
4959 case arm_stub_long_branch_v4t_thumb_thumb_pic:
4960 case arm_stub_long_branch_v4t_arm_thumb_pic:
4961 case arm_stub_long_branch_v4t_thumb_arm_pic:
4962 case arm_stub_long_branch_thumb_only_pic:
0855e32b
NS		 4963 case arm_stub_long_branch_any_tls_pic:
4964 case arm_stub_long_branch_v4t_thumb_tls_pic:
4ba2ef8f 4965 case arm_stub_cmse_branch_thumb_only:
4563a860
JB		 4966 case arm_stub_a8_veneer_blx:
4967 return 4;
b38cadfb 4968
7a89b94e
NC		 4969 case arm_stub_long_branch_arm_nacl:
4970 case arm_stub_long_branch_arm_nacl_pic:
4971 return 16;
4972
4563a860
JB		 4973 default:
4974 abort (); /* Should be unreachable. */
4975 }
4976}
4977
4f4faa4d
TP		 4978/* Returns whether stubs of type STUB_TYPE take over the symbol they are
4979 veneering (TRUE) or have their own symbol (FALSE). */
4980
4981static bfd_boolean
4982arm_stub_sym_claimed (enum elf32_arm_stub_type stub_type)
4983{
4984 if (stub_type >= max_stub_type)
4985 abort (); /* Should be unreachable. */
4986
4ba2ef8f
TP		 4987 switch (stub_type)
4988 {
4989 case arm_stub_cmse_branch_thumb_only:
4990 return TRUE;
4991
4992 default:
4993 return FALSE;
4994 }
4995
4996 abort (); /* Should be unreachable. */
4f4faa4d
TP		 4997}
4998
d7c5bd02
TP		 4999/* Returns the padding needed for the dedicated section used stubs of type
5000 STUB_TYPE. */
5001
5002static int
5003arm_dedicated_stub_section_padding (enum elf32_arm_stub_type stub_type)
5004{
5005 if (stub_type >= max_stub_type)
5006 abort (); /* Should be unreachable. */
5007
4ba2ef8f
TP		 5008 switch (stub_type)
5009 {
5010 case arm_stub_cmse_branch_thumb_only:
5011 return 32;
5012
5013 default:
5014 return 0;
5015 }
5016
5017 abort (); /* Should be unreachable. */
d7c5bd02
TP		 5018}
5019
0955507f
TP		 5020/* If veneers of type STUB_TYPE should go in a dedicated output section,
5021 returns the address of the hash table field in HTAB holding the offset at
5022 which new veneers should be layed out in the stub section. */
5023
5024static bfd_vma*
5025arm_new_stubs_start_offset_ptr (struct elf32_arm_link_hash_table *htab,
5026 enum elf32_arm_stub_type stub_type)
5027{
5028 switch (stub_type)
5029 {
5030 case arm_stub_cmse_branch_thumb_only:
5031 return &htab->new_cmse_stub_offset;
5032
5033 default:
5034 BFD_ASSERT (!arm_dedicated_stub_output_section_required (stub_type));
5035 return NULL;
5036 }
5037}
5038
906e58ca
NC		 5039static bfd_boolean
5040arm_build_one_stub (struct bfd_hash_entry *gen_entry,
5041 void * in_arg)
5042{
7a89b94e 5043#define MAXRELOCS 3
0955507f 5044 bfd_boolean removed_sg_veneer;
906e58ca 5045 struct elf32_arm_stub_hash_entry *stub_entry;
4dfe6ac6 5046 struct elf32_arm_link_hash_table *globals;
906e58ca 5047 struct bfd_link_info *info;
906e58ca
NC		 5048 asection *stub_sec;
5049 bfd *stub_bfd;
906e58ca
NC		 5050 bfd_byte *loc;
5051 bfd_vma sym_value;
5052 int template_size;
5053 int size;
d3ce72d0 5054 const insn_sequence *template_sequence;
906e58ca 5055 int i;
48229727
JB		 5056 int stub_reloc_idx[MAXRELOCS] = {-1, -1};
5057 int stub_reloc_offset[MAXRELOCS] = {0, 0};
5058 int nrelocs = 0;
0955507f 5059 int just_allocated = 0;
906e58ca
NC		 5060
5061 /* Massage our args to the form they really have. */
5062 stub_entry = (struct elf32_arm_stub_hash_entry *) gen_entry;
5063 info = (struct bfd_link_info *) in_arg;
5064
5065 globals = elf32_arm_hash_table (info);
4dfe6ac6
NC		 5066 if (globals == NULL)
5067 return FALSE;
906e58ca 5068
906e58ca
NC		 5069 stub_sec = stub_entry->stub_sec;
5070
4dfe6ac6 5071 if ((globals->fix_cortex_a8 < 0)
4563a860
JB		 5072 != (arm_stub_required_alignment (stub_entry->stub_type) == 2))
5073 /* We have to do less-strictly-aligned fixes last. */
eb7c4339 5074 return TRUE;
fe33d2fa 5075
0955507f
TP		 5076 /* Assign a slot at the end of section if none assigned yet. */
5077 if (stub_entry->stub_offset == (bfd_vma) -1)
5078 {
5079 stub_entry->stub_offset = stub_sec->size;
5080 just_allocated = 1;
5081 }
906e58ca
NC		 5082 loc = stub_sec->contents + stub_entry->stub_offset;
5083
5084 stub_bfd = stub_sec->owner;
5085
906e58ca
NC		 5086 /* This is the address of the stub destination. */
5087 sym_value = (stub_entry->target_value
5088 + stub_entry->target_section->output_offset
5089 + stub_entry->target_section->output_section->vma);
5090
d3ce72d0 5091 template_sequence = stub_entry->stub_template;
461a49ca 5092 template_size = stub_entry->stub_template_size;
906e58ca
NC		 5093
5094 size = 0;
461a49ca 5095 for (i = 0; i < template_size; i++)
906e58ca 5096 {
d3ce72d0 5097 switch (template_sequence[i].type)
461a49ca
DJ		 5098 {
5099 case THUMB16_TYPE:
48229727 5100 {
d3ce72d0
NC		 5101 bfd_vma data = (bfd_vma) template_sequence[i].data;
5102 if (template_sequence[i].reloc_addend != 0)
48229727 5103 {
99059e56
RM		 5104 /* We've borrowed the reloc_addend field to mean we should
5105 insert a condition code into this (Thumb-1 branch)
5106 instruction. See THUMB16_BCOND_INSN. */
5107 BFD_ASSERT ((data & 0xff00) == 0xd000);
5108 data |= ((stub_entry->orig_insn >> 22) & 0xf) << 8;
48229727 5109 }
fe33d2fa 5110 bfd_put_16 (stub_bfd, data, loc + size);
48229727
JB		 5111 size += 2;
5112 }
461a49ca 5113 break;
906e58ca 5114
48229727 5115 case THUMB32_TYPE:
fe33d2fa
CL		 5116 bfd_put_16 (stub_bfd,
5117 (template_sequence[i].data >> 16) & 0xffff,
5118 loc + size);
5119 bfd_put_16 (stub_bfd, template_sequence[i].data & 0xffff,
5120 loc + size + 2);
99059e56
RM		 5121 if (template_sequence[i].r_type != R_ARM_NONE)
5122 {
5123 stub_reloc_idx[nrelocs] = i;
5124 stub_reloc_offset[nrelocs++] = size;
5125 }
5126 size += 4;
5127 break;
48229727 5128
461a49ca 5129 case ARM_TYPE:
fe33d2fa
CL		 5130 bfd_put_32 (stub_bfd, template_sequence[i].data,
5131 loc + size);
461a49ca
DJ		 5132 /* Handle cases where the target is encoded within the
5133 instruction. */
d3ce72d0 5134 if (template_sequence[i].r_type == R_ARM_JUMP24)
461a49ca 5135 {
48229727
JB		 5136 stub_reloc_idx[nrelocs] = i;
5137 stub_reloc_offset[nrelocs++] = size;
461a49ca
DJ		 5138 }
5139 size += 4;
5140 break;
5141
5142 case DATA_TYPE:
d3ce72d0 5143 bfd_put_32 (stub_bfd, template_sequence[i].data, loc + size);
48229727
JB		 5144 stub_reloc_idx[nrelocs] = i;
5145 stub_reloc_offset[nrelocs++] = size;
461a49ca
DJ		 5146 size += 4;
5147 break;
5148
5149 default:
5150 BFD_FAIL ();
5151 return FALSE;
5152 }
906e58ca 5153 }
461a49ca 5154
0955507f
TP		 5155 if (just_allocated)
5156 stub_sec->size += size;
906e58ca 5157
461a49ca
DJ		 5158 /* Stub size has already been computed in arm_size_one_stub. Check
5159 consistency. */
5160 BFD_ASSERT (size == stub_entry->stub_size);
5161
906e58ca 5162 /* Destination is Thumb. Force bit 0 to 1 to reflect this. */
35fc36a8 5163 if (stub_entry->branch_type == ST_BRANCH_TO_THUMB)
906e58ca
NC		 5164 sym_value |= 1;
5165
0955507f
TP		 5166 /* Assume non empty slots have at least one and at most MAXRELOCS entries
5167 to relocate in each stub. */
5168 removed_sg_veneer =
5169 (size == 0 && stub_entry->stub_type == arm_stub_cmse_branch_thumb_only);
5170 BFD_ASSERT (removed_sg_veneer || (nrelocs != 0 && nrelocs <= MAXRELOCS));
c820be07 5171
48229727 5172 for (i = 0; i < nrelocs; i++)
8d9d9490
TP		 5173 {
5174 Elf_Internal_Rela rel;
5175 bfd_boolean unresolved_reloc;
5176 char *error_message;
5177 bfd_vma points_to =
5178 sym_value + template_sequence[stub_reloc_idx[i]].reloc_addend;
5179
5180 rel.r_offset = stub_entry->stub_offset + stub_reloc_offset[i];
5181 rel.r_info = ELF32_R_INFO (0,
5182 template_sequence[stub_reloc_idx[i]].r_type);
5183 rel.r_addend = 0;
5184
5185 if (stub_entry->stub_type == arm_stub_a8_veneer_b_cond && i == 0)
5186 /* The first relocation in the elf32_arm_stub_a8_veneer_b_cond[]
5187 template should refer back to the instruction after the original
5188 branch. We use target_section as Cortex-A8 erratum workaround stubs
5189 are only generated when both source and target are in the same
5190 section. */
5191 points_to = stub_entry->target_section->output_section->vma
5192 + stub_entry->target_section->output_offset
5193 + stub_entry->source_value;
5194
5195 elf32_arm_final_link_relocate (elf32_arm_howto_from_type
5196 (template_sequence[stub_reloc_idx[i]].r_type),
5197 stub_bfd, info->output_bfd, stub_sec, stub_sec->contents, &rel,
5198 points_to, info, stub_entry->target_section, "", STT_FUNC,
5199 stub_entry->branch_type,
5200 (struct elf_link_hash_entry *) stub_entry->h, &unresolved_reloc,
5201 &error_message);
5202 }
906e58ca
NC		 5203
5204 return TRUE;
48229727 5205#undef MAXRELOCS
906e58ca
NC		 5206}
5207
48229727
JB		 5208/* Calculate the template, template size and instruction size for a stub.
5209 Return value is the instruction size. */
906e58ca 5210
48229727
JB		 5211static unsigned int
5212find_stub_size_and_template (enum elf32_arm_stub_type stub_type,
5213 const insn_sequence **stub_template,
5214 int *stub_template_size)
906e58ca 5215{
d3ce72d0 5216 const insn_sequence *template_sequence = NULL;
48229727
JB		 5217 int template_size = 0, i;
5218 unsigned int size;
906e58ca 5219
d3ce72d0 5220 template_sequence = stub_definitions[stub_type].template_sequence;
2a229407
AM		 5221 if (stub_template)
5222 *stub_template = template_sequence;
5223
48229727 5224 template_size = stub_definitions[stub_type].template_size;
2a229407
AM		 5225 if (stub_template_size)
5226 *stub_template_size = template_size;
906e58ca
NC		 5227
5228 size = 0;
461a49ca
DJ		 5229 for (i = 0; i < template_size; i++)
5230 {
d3ce72d0 5231 switch (template_sequence[i].type)
461a49ca
DJ		 5232 {
5233 case THUMB16_TYPE:
5234 size += 2;
5235 break;
5236
5237 case ARM_TYPE:
48229727 5238 case THUMB32_TYPE:
461a49ca
DJ		 5239 case DATA_TYPE:
5240 size += 4;
5241 break;
5242
5243 default:
5244 BFD_FAIL ();
2a229407 5245 return 0;
461a49ca
DJ		 5246 }
5247 }
5248
48229727
JB		 5249 return size;
5250}
5251
5252/* As above, but don't actually build the stub. Just bump offset so
5253 we know stub section sizes. */
5254
5255static bfd_boolean
5256arm_size_one_stub (struct bfd_hash_entry *gen_entry,
c7e2358a 5257 void *in_arg ATTRIBUTE_UNUSED)
48229727
JB		 5258{
5259 struct elf32_arm_stub_hash_entry *stub_entry;
d3ce72d0 5260 const insn_sequence *template_sequence;
48229727
JB		 5261 int template_size, size;
5262
5263 /* Massage our args to the form they really have. */
5264 stub_entry = (struct elf32_arm_stub_hash_entry *) gen_entry;
48229727
JB		 5265
5266 BFD_ASSERT((stub_entry->stub_type > arm_stub_none)
5267 && stub_entry->stub_type < ARRAY_SIZE(stub_definitions));
5268
d3ce72d0 5269 size = find_stub_size_and_template (stub_entry->stub_type, &template_sequence,
48229727
JB		 5270 &template_size);
5271
0955507f
TP		 5272 /* Initialized to -1. Null size indicates an empty slot full of zeros. */
5273 if (stub_entry->stub_template_size)
5274 {
5275 stub_entry->stub_size = size;
5276 stub_entry->stub_template = template_sequence;
5277 stub_entry->stub_template_size = template_size;
5278 }
5279
5280 /* Already accounted for. */
5281 if (stub_entry->stub_offset != (bfd_vma) -1)
5282 return TRUE;
461a49ca 5283
906e58ca
NC		 5284 size = (size + 7) & ~7;
5285 stub_entry->stub_sec->size += size;
461a49ca 5286
906e58ca
NC		 5287 return TRUE;
5288}
5289
5290/* External entry points for sizing and building linker stubs. */
5291
5292/* Set up various things so that we can make a list of input sections
5293 for each output section included in the link. Returns -1 on error,
5294 0 when no stubs will be needed, and 1 on success. */
5295
5296int
5297elf32_arm_setup_section_lists (bfd *output_bfd,
5298 struct bfd_link_info *info)
5299{
5300 bfd *input_bfd;
5301 unsigned int bfd_count;
7292b3ac 5302 unsigned int top_id, top_index;
906e58ca
NC		 5303 asection *section;
5304 asection **input_list, **list;
5305 bfd_size_type amt;
5306 struct elf32_arm_link_hash_table *htab = elf32_arm_hash_table (info);
5307
4dfe6ac6
NC		 5308 if (htab == NULL)
5309 return 0;
906e58ca
NC		 5310 if (! is_elf_hash_table (htab))
5311 return 0;
5312
5313 /* Count the number of input BFDs and find the top input section id. */
5314 for (input_bfd = info->input_bfds, bfd_count = 0, top_id = 0;
5315 input_bfd != NULL;
c72f2fb2 5316 input_bfd = input_bfd->link.next)
906e58ca
NC		 5317 {
5318 bfd_count += 1;
5319 for (section = input_bfd->sections;
5320 section != NULL;
5321 section = section->next)
5322 {
5323 if (top_id < section->id)
5324 top_id = section->id;
5325 }
5326 }
5327 htab->bfd_count = bfd_count;
5328
5329 amt = sizeof (struct map_stub) * (top_id + 1);
21d799b5 5330 htab->stub_group = (struct map_stub *) bfd_zmalloc (amt);
906e58ca
NC		 5331 if (htab->stub_group == NULL)
5332 return -1;
fe33d2fa 5333 htab->top_id = top_id;
906e58ca
NC		 5334
5335 /* We can't use output_bfd->section_count here to find the top output
5336 section index as some sections may have been removed, and
5337 _bfd_strip_section_from_output doesn't renumber the indices. */
5338 for (section = output_bfd->sections, top_index = 0;
5339 section != NULL;
5340 section = section->next)
5341 {
5342 if (top_index < section->index)
5343 top_index = section->index;
5344 }
5345
5346 htab->top_index = top_index;
5347 amt = sizeof (asection *) * (top_index + 1);
21d799b5 5348 input_list = (asection **) bfd_malloc (amt);
906e58ca
NC		 5349 htab->input_list = input_list;
5350 if (input_list == NULL)
5351 return -1;
5352
5353 /* For sections we aren't interested in, mark their entries with a
5354 value we can check later. */
5355 list = input_list + top_index;
5356 do
5357 *list = bfd_abs_section_ptr;
5358 while (list-- != input_list);
5359
5360 for (section = output_bfd->sections;
5361 section != NULL;
5362 section = section->next)
5363 {
5364 if ((section->flags & SEC_CODE) != 0)
5365 input_list[section->index] = NULL;
5366 }
5367
5368 return 1;
5369}
5370
5371/* The linker repeatedly calls this function for each input section,
5372 in the order that input sections are linked into output sections.
5373 Build lists of input sections to determine groupings between which
5374 we may insert linker stubs. */
5375
5376void
5377elf32_arm_next_input_section (struct bfd_link_info *info,
5378 asection *isec)
5379{
5380 struct elf32_arm_link_hash_table *htab = elf32_arm_hash_table (info);
5381
4dfe6ac6
NC		 5382 if (htab == NULL)
5383 return;
5384
906e58ca
NC		 5385 if (isec->output_section->index <= htab->top_index)
5386 {
5387 asection **list = htab->input_list + isec->output_section->index;
5388
a7470592 5389 if (*list != bfd_abs_section_ptr && (isec->flags & SEC_CODE) != 0)
906e58ca
NC		 5390 {
5391 /* Steal the link_sec pointer for our list. */
5392#define PREV_SEC(sec) (htab->stub_group[(sec)->id].link_sec)
5393 /* This happens to make the list in reverse order,
07d72278 5394 which we reverse later. */
906e58ca
NC		 5395 PREV_SEC (isec) = *list;
5396 *list = isec;
5397 }
5398 }
5399}
5400
5401/* See whether we can group stub sections together. Grouping stub
5402 sections may result in fewer stubs. More importantly, we need to
07d72278 5403 put all .init* and .fini* stubs at the end of the .init or
906e58ca
NC		 5404 .fini output sections respectively, because glibc splits the
5405 _init and _fini functions into multiple parts. Putting a stub in
5406 the middle of a function is not a good idea. */
5407
5408static void
5409group_sections (struct elf32_arm_link_hash_table *htab,
5410 bfd_size_type stub_group_size,
07d72278 5411 bfd_boolean stubs_always_after_branch)
906e58ca 5412{
07d72278 5413 asection **list = htab->input_list;
906e58ca
NC		 5414
5415 do
5416 {
5417 asection *tail = *list;
07d72278 5418 asection *head;
906e58ca
NC		 5419
5420 if (tail == bfd_abs_section_ptr)
5421 continue;
5422
07d72278
DJ		 5423 /* Reverse the list: we must avoid placing stubs at the
5424 beginning of the section because the beginning of the text
5425 section may be required for an interrupt vector in bare metal
5426 code. */
5427#define NEXT_SEC PREV_SEC
e780aef2
CL		 5428 head = NULL;
5429 while (tail != NULL)
99059e56
RM		 5430 {
5431 /* Pop from tail. */
5432 asection *item = tail;
5433 tail = PREV_SEC (item);
e780aef2 5434
99059e56
RM		 5435 /* Push on head. */
5436 NEXT_SEC (item) = head;
5437 head = item;
5438 }
07d72278
DJ		 5439
5440 while (head != NULL)
906e58ca
NC		 5441 {
5442 asection *curr;
07d72278 5443 asection *next;
e780aef2
CL		 5444 bfd_vma stub_group_start = head->output_offset;
5445 bfd_vma end_of_next;
906e58ca 5446
07d72278 5447 curr = head;
e780aef2 5448 while (NEXT_SEC (curr) != NULL)
8cd931b7 5449 {
e780aef2
CL		 5450 next = NEXT_SEC (curr);
5451 end_of_next = next->output_offset + next->size;
5452 if (end_of_next - stub_group_start >= stub_group_size)
5453 /* End of NEXT is too far from start, so stop. */
8cd931b7 5454 break;
e780aef2
CL		 5455 /* Add NEXT to the group. */
5456 curr = next;
8cd931b7 5457 }
906e58ca 5458
07d72278 5459 /* OK, the size from the start to the start of CURR is less
906e58ca 5460 than stub_group_size and thus can be handled by one stub
07d72278 5461 section. (Or the head section is itself larger than
906e58ca
NC		 5462 stub_group_size, in which case we may be toast.)
5463 We should really be keeping track of the total size of
5464 stubs added here, as stubs contribute to the final output
7fb9f789 5465 section size. */
906e58ca
NC		 5466 do
5467 {
07d72278 5468 next = NEXT_SEC (head);
906e58ca 5469 /* Set up this stub group. */
07d72278 5470 htab->stub_group[head->id].link_sec = curr;
906e58ca 5471 }
07d72278 5472 while (head != curr && (head = next) != NULL);
906e58ca
NC		 5473
5474 /* But wait, there's more! Input sections up to stub_group_size
07d72278
DJ		 5475 bytes after the stub section can be handled by it too. */
5476 if (!stubs_always_after_branch)
906e58ca 5477 {
e780aef2
CL		 5478 stub_group_start = curr->output_offset + curr->size;
5479
8cd931b7 5480 while (next != NULL)
906e58ca 5481 {
e780aef2
CL		 5482 end_of_next = next->output_offset + next->size;
5483 if (end_of_next - stub_group_start >= stub_group_size)
5484 /* End of NEXT is too far from stubs, so stop. */
8cd931b7 5485 break;
e780aef2 5486 /* Add NEXT to the stub group. */
07d72278
DJ		 5487 head = next;
5488 next = NEXT_SEC (head);
5489 htab->stub_group[head->id].link_sec = curr;
906e58ca
NC		 5490 }
5491 }
07d72278 5492 head = next;
906e58ca
NC		 5493 }
5494 }
07d72278 5495 while (list++ != htab->input_list + htab->top_index);
906e58ca
NC		 5496
5497 free (htab->input_list);
5498#undef PREV_SEC
07d72278 5499#undef NEXT_SEC
906e58ca
NC		 5500}
5501
48229727
JB		 5502/* Comparison function for sorting/searching relocations relating to Cortex-A8
5503 erratum fix. */
5504
5505static int
5506a8_reloc_compare (const void *a, const void *b)
5507{
21d799b5
NC		 5508 const struct a8_erratum_reloc *ra = (const struct a8_erratum_reloc *) a;
5509 const struct a8_erratum_reloc *rb = (const struct a8_erratum_reloc *) b;
48229727
JB		 5510
5511 if (ra->from < rb->from)
5512 return -1;
5513 else if (ra->from > rb->from)
5514 return 1;
5515 else
5516 return 0;
5517}
5518
5519static struct elf_link_hash_entry *find_thumb_glue (struct bfd_link_info *,
5520 const char *, char **);
5521
5522/* Helper function to scan code for sequences which might trigger the Cortex-A8
5523 branch/TLB erratum. Fill in the table described by A8_FIXES_P,
81694485 5524 NUM_A8_FIXES_P, A8_FIX_TABLE_SIZE_P. Returns true if an error occurs, false
48229727
JB		 5525 otherwise. */
5526
81694485
NC		 5527static bfd_boolean
5528cortex_a8_erratum_scan (bfd *input_bfd,
5529 struct bfd_link_info *info,
48229727
JB		 5530 struct a8_erratum_fix **a8_fixes_p,
5531 unsigned int *num_a8_fixes_p,
5532 unsigned int *a8_fix_table_size_p,
5533 struct a8_erratum_reloc *a8_relocs,
eb7c4339
NS		 5534 unsigned int num_a8_relocs,
5535 unsigned prev_num_a8_fixes,
5536 bfd_boolean *stub_changed_p)
48229727
JB		 5537{
5538 asection *section;
5539 struct elf32_arm_link_hash_table *htab = elf32_arm_hash_table (info);
5540 struct a8_erratum_fix *a8_fixes = *a8_fixes_p;
5541 unsigned int num_a8_fixes = *num_a8_fixes_p;
5542 unsigned int a8_fix_table_size = *a8_fix_table_size_p;
5543
4dfe6ac6
NC		 5544 if (htab == NULL)
5545 return FALSE;
5546
48229727
JB		 5547 for (section = input_bfd->sections;
5548 section != NULL;
5549 section = section->next)
5550 {
5551 bfd_byte *contents = NULL;
5552 struct _arm_elf_section_data *sec_data;
5553 unsigned int span;
5554 bfd_vma base_vma;
5555
5556 if (elf_section_type (section) != SHT_PROGBITS
99059e56
RM		 5557 || (elf_section_flags (section) & SHF_EXECINSTR) == 0
5558 || (section->flags & SEC_EXCLUDE) != 0
5559 || (section->sec_info_type == SEC_INFO_TYPE_JUST_SYMS)
5560 || (section->output_section == bfd_abs_section_ptr))
5561 continue;
48229727
JB		 5562
5563 base_vma = section->output_section->vma + section->output_offset;
5564
5565 if (elf_section_data (section)->this_hdr.contents != NULL)
99059e56 5566 contents = elf_section_data (section)->this_hdr.contents;
48229727 5567 else if (! bfd_malloc_and_get_section (input_bfd, section, &contents))
99059e56 5568 return TRUE;
48229727
JB		 5569
5570 sec_data = elf32_arm_section_data (section);
5571
5572 for (span = 0; span < sec_data->mapcount; span++)
99059e56
RM		 5573 {
5574 unsigned int span_start = sec_data->map[span].vma;
5575 unsigned int span_end = (span == sec_data->mapcount - 1)
5576 ? section->size : sec_data->map[span + 1].vma;
5577 unsigned int i;
5578 char span_type = sec_data->map[span].type;
5579 bfd_boolean last_was_32bit = FALSE, last_was_branch = FALSE;
5580
5581 if (span_type != 't')
5582 continue;
5583
5584 /* Span is entirely within a single 4KB region: skip scanning. */
5585 if (((base_vma + span_start) & ~0xfff)
48229727 5586 == ((base_vma + span_end) & ~0xfff))
99059e56
RM		 5587 continue;
5588
5589 /* Scan for 32-bit Thumb-2 branches which span two 4K regions, where:
5590
5591 * The opcode is BLX.W, BL.W, B.W, Bcc.W
5592 * The branch target is in the same 4KB region as the
5593 first half of the branch.
5594 * The instruction before the branch is a 32-bit
5595 length non-branch instruction. */
5596 for (i = span_start; i < span_end;)
5597 {
5598 unsigned int insn = bfd_getl16 (&contents[i]);
5599 bfd_boolean insn_32bit = FALSE, is_blx = FALSE, is_b = FALSE;
48229727
JB		 5600 bfd_boolean is_bl = FALSE, is_bcc = FALSE, is_32bit_branch;
5601
99059e56
RM		 5602 if ((insn & 0xe000) == 0xe000 && (insn & 0x1800) != 0x0000)
5603 insn_32bit = TRUE;
48229727
JB		 5604
5605 if (insn_32bit)
99059e56
RM		 5606 {
5607 /* Load the rest of the insn (in manual-friendly order). */
5608 insn = (insn << 16) | bfd_getl16 (&contents[i + 2]);
5609
5610 /* Encoding T4: B<c>.W. */
5611 is_b = (insn & 0xf800d000) == 0xf0009000;
5612 /* Encoding T1: BL<c>.W. */
5613 is_bl = (insn & 0xf800d000) == 0xf000d000;
5614 /* Encoding T2: BLX<c>.W. */
5615 is_blx = (insn & 0xf800d000) == 0xf000c000;
48229727
JB		 5616 /* Encoding T3: B<c>.W (not permitted in IT block). */
5617 is_bcc = (insn & 0xf800d000) == 0xf0008000
5618 && (insn & 0x07f00000) != 0x03800000;
5619 }
5620
5621 is_32bit_branch = is_b || is_bl || is_blx || is_bcc;
fe33d2fa 5622
99059e56 5623 if (((base_vma + i) & 0xfff) == 0xffe
81694485
NC		 5624 && insn_32bit
5625 && is_32bit_branch
5626 && last_was_32bit
5627 && ! last_was_branch)
99059e56
RM		 5628 {
5629 bfd_signed_vma offset = 0;
5630 bfd_boolean force_target_arm = FALSE;
48229727 5631 bfd_boolean force_target_thumb = FALSE;
99059e56
RM		 5632 bfd_vma target;
5633 enum elf32_arm_stub_type stub_type = arm_stub_none;
5634 struct a8_erratum_reloc key, *found;
5635 bfd_boolean use_plt = FALSE;
48229727 5636
99059e56
RM		 5637 key.from = base_vma + i;
5638 found = (struct a8_erratum_reloc *)
5639 bsearch (&key, a8_relocs, num_a8_relocs,
5640 sizeof (struct a8_erratum_reloc),
5641 &a8_reloc_compare);
48229727
JB		 5642
5643 if (found)
5644 {
5645 char *error_message = NULL;
5646 struct elf_link_hash_entry *entry;
5647
5648 /* We don't care about the error returned from this
99059e56 5649 function, only if there is glue or not. */
48229727
JB		 5650 entry = find_thumb_glue (info, found->sym_name,
5651 &error_message);
5652
5653 if (entry)
5654 found->non_a8_stub = TRUE;
5655
92750f34 5656 /* Keep a simpler condition, for the sake of clarity. */
362d30a1 5657 if (htab->root.splt != NULL && found->hash != NULL
92750f34
DJ		 5658 && found->hash->root.plt.offset != (bfd_vma) -1)
5659 use_plt = TRUE;
5660
5661 if (found->r_type == R_ARM_THM_CALL)
5662 {
35fc36a8
RS		 5663 if (found->branch_type == ST_BRANCH_TO_ARM
5664 || use_plt)
92750f34
DJ		 5665 force_target_arm = TRUE;
5666 else
5667 force_target_thumb = TRUE;
5668 }
48229727
JB		 5669 }
5670
99059e56 5671 /* Check if we have an offending branch instruction. */
48229727
JB		 5672
5673 if (found && found->non_a8_stub)
5674 /* We've already made a stub for this instruction, e.g.
5675 it's a long branch or a Thumb->ARM stub. Assume that
5676 stub will suffice to work around the A8 erratum (see
5677 setting of always_after_branch above). */
5678 ;
99059e56
RM		 5679 else if (is_bcc)
5680 {
5681 offset = (insn & 0x7ff) << 1;
5682 offset |= (insn & 0x3f0000) >> 4;
5683 offset |= (insn & 0x2000) ? 0x40000 : 0;
5684 offset |= (insn & 0x800) ? 0x80000 : 0;
5685 offset |= (insn & 0x4000000) ? 0x100000 : 0;
5686 if (offset & 0x100000)
5687 offset |= ~ ((bfd_signed_vma) 0xfffff);
5688 stub_type = arm_stub_a8_veneer_b_cond;
5689 }
5690 else if (is_b || is_bl || is_blx)
5691 {
5692 int s = (insn & 0x4000000) != 0;
5693 int j1 = (insn & 0x2000) != 0;
5694 int j2 = (insn & 0x800) != 0;
5695 int i1 = !(j1 ^ s);
5696 int i2 = !(j2 ^ s);
5697
5698 offset = (insn & 0x7ff) << 1;
5699 offset |= (insn & 0x3ff0000) >> 4;
5700 offset |= i2 << 22;
5701 offset |= i1 << 23;
5702 offset |= s << 24;
5703 if (offset & 0x1000000)
5704 offset |= ~ ((bfd_signed_vma) 0xffffff);
5705
5706 if (is_blx)
5707 offset &= ~ ((bfd_signed_vma) 3);
5708
5709 stub_type = is_blx ? arm_stub_a8_veneer_blx :
5710 is_bl ? arm_stub_a8_veneer_bl : arm_stub_a8_veneer_b;
5711 }
5712
5713 if (stub_type != arm_stub_none)
5714 {
5715 bfd_vma pc_for_insn = base_vma + i + 4;
48229727
JB		 5716
5717 /* The original instruction is a BL, but the target is
99059e56 5718 an ARM instruction. If we were not making a stub,
48229727
JB		 5719 the BL would have been converted to a BLX. Use the
5720 BLX stub instead in that case. */
5721 if (htab->use_blx && force_target_arm
5722 && stub_type == arm_stub_a8_veneer_bl)
5723 {
5724 stub_type = arm_stub_a8_veneer_blx;
5725 is_blx = TRUE;
5726 is_bl = FALSE;
5727 }
5728 /* Conversely, if the original instruction was
5729 BLX but the target is Thumb mode, use the BL
5730 stub. */
5731 else if (force_target_thumb
5732 && stub_type == arm_stub_a8_veneer_blx)
5733 {
5734 stub_type = arm_stub_a8_veneer_bl;
5735 is_blx = FALSE;
5736 is_bl = TRUE;
5737 }
5738
99059e56
RM		 5739 if (is_blx)
5740 pc_for_insn &= ~ ((bfd_vma) 3);
48229727 5741
99059e56
RM		 5742 /* If we found a relocation, use the proper destination,
5743 not the offset in the (unrelocated) instruction.
48229727
JB		 5744 Note this is always done if we switched the stub type
5745 above. */
99059e56
RM		 5746 if (found)
5747 offset =
81694485 5748 (bfd_signed_vma) (found->destination - pc_for_insn);
48229727 5749
99059e56
RM		 5750 /* If the stub will use a Thumb-mode branch to a
5751 PLT target, redirect it to the preceding Thumb
5752 entry point. */
5753 if (stub_type != arm_stub_a8_veneer_blx && use_plt)
5754 offset -= PLT_THUMB_STUB_SIZE;
7d24e6a6 5755
99059e56 5756 target = pc_for_insn + offset;
48229727 5757
99059e56
RM		 5758 /* The BLX stub is ARM-mode code. Adjust the offset to
5759 take the different PC value (+8 instead of +4) into
48229727 5760 account. */
99059e56
RM		 5761 if (stub_type == arm_stub_a8_veneer_blx)
5762 offset += 4;
5763
5764 if (((base_vma + i) & ~0xfff) == (target & ~0xfff))
5765 {
5766 char *stub_name = NULL;
5767
5768 if (num_a8_fixes == a8_fix_table_size)
5769 {
5770 a8_fix_table_size *= 2;
5771 a8_fixes = (struct a8_erratum_fix *)
5772 bfd_realloc (a8_fixes,
5773 sizeof (struct a8_erratum_fix)
5774 * a8_fix_table_size);
5775 }
48229727 5776
eb7c4339
NS		 5777 if (num_a8_fixes < prev_num_a8_fixes)
5778 {
5779 /* If we're doing a subsequent scan,
5780 check if we've found the same fix as
5781 before, and try and reuse the stub
5782 name. */
5783 stub_name = a8_fixes[num_a8_fixes].stub_name;
5784 if ((a8_fixes[num_a8_fixes].section != section)
5785 || (a8_fixes[num_a8_fixes].offset != i))
5786 {
5787 free (stub_name);
5788 stub_name = NULL;
5789 *stub_changed_p = TRUE;
5790 }
5791 }
5792
5793 if (!stub_name)
5794 {
21d799b5 5795 stub_name = (char *) bfd_malloc (8 + 1 + 8 + 1);
eb7c4339
NS		 5796 if (stub_name != NULL)
5797 sprintf (stub_name, "%x:%x", section->id, i);
5798 }
48229727 5799
99059e56
RM		 5800 a8_fixes[num_a8_fixes].input_bfd = input_bfd;
5801 a8_fixes[num_a8_fixes].section = section;
5802 a8_fixes[num_a8_fixes].offset = i;
8d9d9490
TP		 5803 a8_fixes[num_a8_fixes].target_offset =
5804 target - base_vma;
99059e56
RM		 5805 a8_fixes[num_a8_fixes].orig_insn = insn;
5806 a8_fixes[num_a8_fixes].stub_name = stub_name;
5807 a8_fixes[num_a8_fixes].stub_type = stub_type;
5808 a8_fixes[num_a8_fixes].branch_type =
35fc36a8 5809 is_blx ? ST_BRANCH_TO_ARM : ST_BRANCH_TO_THUMB;
48229727 5810
99059e56
RM		 5811 num_a8_fixes++;
5812 }
5813 }
5814 }
48229727 5815
99059e56
RM		 5816 i += insn_32bit ? 4 : 2;
5817 last_was_32bit = insn_32bit;
48229727 5818 last_was_branch = is_32bit_branch;
99059e56
RM		 5819 }
5820 }
48229727
JB		 5821
5822 if (elf_section_data (section)->this_hdr.contents == NULL)
99059e56 5823 free (contents);
48229727 5824 }
fe33d2fa 5825
48229727
JB		 5826 *a8_fixes_p = a8_fixes;
5827 *num_a8_fixes_p = num_a8_fixes;
5828 *a8_fix_table_size_p = a8_fix_table_size;
fe33d2fa 5829
81694485 5830 return FALSE;
48229727
JB		 5831}
5832
b715f643
TP		 5833/* Create or update a stub entry depending on whether the stub can already be
5834 found in HTAB. The stub is identified by:
5835 - its type STUB_TYPE
5836 - its source branch (note that several can share the same stub) whose
5837 section and relocation (if any) are given by SECTION and IRELA
5838 respectively
5839 - its target symbol whose input section, hash, name, value and branch type
5840 are given in SYM_SEC, HASH, SYM_NAME, SYM_VALUE and BRANCH_TYPE
5841 respectively
5842
5843 If found, the value of the stub's target symbol is updated from SYM_VALUE
5844 and *NEW_STUB is set to FALSE. Otherwise, *NEW_STUB is set to
5845 TRUE and the stub entry is initialized.
5846
0955507f
TP		 5847 Returns the stub that was created or updated, or NULL if an error
5848 occurred. */
b715f643 5849
0955507f 5850static struct elf32_arm_stub_hash_entry *
b715f643
TP		 5851elf32_arm_create_stub (struct elf32_arm_link_hash_table *htab,
5852 enum elf32_arm_stub_type stub_type, asection *section,
5853 Elf_Internal_Rela *irela, asection *sym_sec,
5854 struct elf32_arm_link_hash_entry *hash, char *sym_name,
5855 bfd_vma sym_value, enum arm_st_branch_type branch_type,
5856 bfd_boolean *new_stub)
5857{
5858 const asection *id_sec;
5859 char *stub_name;
5860 struct elf32_arm_stub_hash_entry *stub_entry;
5861 unsigned int r_type;
4f4faa4d 5862 bfd_boolean sym_claimed = arm_stub_sym_claimed (stub_type);
b715f643
TP		 5863
5864 BFD_ASSERT (stub_type != arm_stub_none);
5865 *new_stub = FALSE;
5866
4f4faa4d
TP		 5867 if (sym_claimed)
5868 stub_name = sym_name;
5869 else
5870 {
5871 BFD_ASSERT (irela);
5872 BFD_ASSERT (section);
c2abbbeb 5873 BFD_ASSERT (section->id <= htab->top_id);
b715f643 5874
4f4faa4d
TP		 5875 /* Support for grouping stub sections. */
5876 id_sec = htab->stub_group[section->id].link_sec;
b715f643 5877
4f4faa4d
TP		 5878 /* Get the name of this stub. */
5879 stub_name = elf32_arm_stub_name (id_sec, sym_sec, hash, irela,
5880 stub_type);
5881 if (!stub_name)
0955507f 5882 return NULL;
4f4faa4d 5883 }
b715f643
TP		 5884
5885 stub_entry = arm_stub_hash_lookup (&htab->stub_hash_table, stub_name, FALSE,
5886 FALSE);
5887 /* The proper stub has already been created, just update its value. */
5888 if (stub_entry != NULL)
5889 {
4f4faa4d
TP		 5890 if (!sym_claimed)
5891 free (stub_name);
b715f643 5892 stub_entry->target_value = sym_value;
0955507f 5893 return stub_entry;
b715f643
TP		 5894 }
5895
daa4adae 5896 stub_entry = elf32_arm_add_stub (stub_name, section, htab, stub_type);
b715f643
TP		 5897 if (stub_entry == NULL)
5898 {
4f4faa4d
TP		 5899 if (!sym_claimed)
5900 free (stub_name);
0955507f 5901 return NULL;
b715f643
TP		 5902 }
5903
5904 stub_entry->target_value = sym_value;
5905 stub_entry->target_section = sym_sec;
5906 stub_entry->stub_type = stub_type;
5907 stub_entry->h = hash;
5908 stub_entry->branch_type = branch_type;
5909
4f4faa4d
TP		 5910 if (sym_claimed)
5911 stub_entry->output_name = sym_name;
5912 else
b715f643 5913 {
4f4faa4d
TP		 5914 if (sym_name == NULL)
5915 sym_name = "unnamed";
5916 stub_entry->output_name = (char *)
5917 bfd_alloc (htab->stub_bfd, sizeof (THUMB2ARM_GLUE_ENTRY_NAME)
5918 + strlen (sym_name));
5919 if (stub_entry->output_name == NULL)
5920 {
5921 free (stub_name);
0955507f 5922 return NULL;
4f4faa4d 5923 }
b715f643 5924
4f4faa4d
TP		 5925 /* For historical reasons, use the existing names for ARM-to-Thumb and
5926 Thumb-to-ARM stubs. */
5927 r_type = ELF32_R_TYPE (irela->r_info);
5928 if ((r_type == (unsigned int) R_ARM_THM_CALL
5929 || r_type == (unsigned int) R_ARM_THM_JUMP24
5930 || r_type == (unsigned int) R_ARM_THM_JUMP19)
5931 && branch_type == ST_BRANCH_TO_ARM)
5932 sprintf (stub_entry->output_name, THUMB2ARM_GLUE_ENTRY_NAME, sym_name);
5933 else if ((r_type == (unsigned int) R_ARM_CALL
5934 || r_type == (unsigned int) R_ARM_JUMP24)
5935 && branch_type == ST_BRANCH_TO_THUMB)
5936 sprintf (stub_entry->output_name, ARM2THUMB_GLUE_ENTRY_NAME, sym_name);
5937 else
5938 sprintf (stub_entry->output_name, STUB_ENTRY_NAME, sym_name);
5939 }
b715f643
TP		 5940
5941 *new_stub = TRUE;
0955507f 5942 return stub_entry;
b715f643
TP		 5943}
5944
4ba2ef8f
TP		 5945/* Scan symbols in INPUT_BFD to identify secure entry functions needing a
5946 gateway veneer to transition from non secure to secure state and create them
5947 accordingly.
5948
5949 "ARMv8-M Security Extensions: Requirements on Development Tools" document
5950 defines the conditions that govern Secure Gateway veneer creation for a
5951 given symbol <SYM> as follows:
5952 - it has function type
5953 - it has non local binding
5954 - a symbol named __acle_se_<SYM> (called special symbol) exists with the
5955 same type, binding and value as <SYM> (called normal symbol).
5956 An entry function can handle secure state transition itself in which case
5957 its special symbol would have a different value from the normal symbol.
5958
5959 OUT_ATTR gives the output attributes, SYM_HASHES the symbol index to hash
5960 entry mapping while HTAB gives the name to hash entry mapping.
0955507f
TP		 5961 *CMSE_STUB_CREATED is increased by the number of secure gateway veneer
5962 created.
4ba2ef8f 5963
0955507f 5964 The return value gives whether a stub failed to be allocated. */
4ba2ef8f
TP		 5965
5966static bfd_boolean
5967cmse_scan (bfd *input_bfd, struct elf32_arm_link_hash_table *htab,
5968 obj_attribute *out_attr, struct elf_link_hash_entry **sym_hashes,
0955507f 5969 int *cmse_stub_created)
4ba2ef8f
TP		 5970{
5971 const struct elf_backend_data *bed;
5972 Elf_Internal_Shdr *symtab_hdr;
5973 unsigned i, j, sym_count, ext_start;
5974 Elf_Internal_Sym *cmse_sym, *local_syms;
5975 struct elf32_arm_link_hash_entry *hash, *cmse_hash = NULL;
5976 enum arm_st_branch_type branch_type;
5977 char *sym_name, *lsym_name;
5978 bfd_vma sym_value;
5979 asection *section;
0955507f
TP		 5980 struct elf32_arm_stub_hash_entry *stub_entry;
5981 bfd_boolean is_v8m, new_stub, cmse_invalid, ret = TRUE;
4ba2ef8f
TP		 5982
5983 bed = get_elf_backend_data (input_bfd);
5984 symtab_hdr = &elf_tdata (input_bfd)->symtab_hdr;
5985 sym_count = symtab_hdr->sh_size / bed->s->sizeof_sym;
5986 ext_start = symtab_hdr->sh_info;
5987 is_v8m = (out_attr[Tag_CPU_arch].i >= TAG_CPU_ARCH_V8M_BASE
5988 && out_attr[Tag_CPU_arch_profile].i == 'M');
5989
5990 local_syms = (Elf_Internal_Sym *) symtab_hdr->contents;
5991 if (local_syms == NULL)
5992 local_syms = bfd_elf_get_elf_syms (input_bfd, symtab_hdr,
5993 symtab_hdr->sh_info, 0, NULL, NULL,
5994 NULL);
5995 if (symtab_hdr->sh_info && local_syms == NULL)
5996 return FALSE;
5997
5998 /* Scan symbols. */
5999 for (i = 0; i < sym_count; i++)
6000 {
6001 cmse_invalid = FALSE;
6002
6003 if (i < ext_start)
6004 {
6005 cmse_sym = &local_syms[i];
4ba2ef8f
TP		 6006 sym_name = bfd_elf_string_from_elf_section (input_bfd,
6007 symtab_hdr->sh_link,
6008 cmse_sym->st_name);
baf46cd7
AM		 6009 if (!sym_name || !CONST_STRNEQ (sym_name, CMSE_PREFIX))
6010 continue;
6011
4ba2ef8f
TP		 6012 /* Special symbol with local binding. */
6013 cmse_invalid = TRUE;
6014 }
6015 else
6016 {
6017 cmse_hash = elf32_arm_hash_entry (sym_hashes[i - ext_start]);
6018 sym_name = (char *) cmse_hash->root.root.root.string;
baf46cd7 6019 if (!CONST_STRNEQ (sym_name, CMSE_PREFIX))
4ba2ef8f
TP		 6020 continue;
6021
6022 /* Special symbol has incorrect binding or type. */
6023 if ((cmse_hash->root.root.type != bfd_link_hash_defined
6024 && cmse_hash->root.root.type != bfd_link_hash_defweak)
6025 || cmse_hash->root.type != STT_FUNC)
6026 cmse_invalid = TRUE;
6027 }
6028
6029 if (!is_v8m)
6030 {
90b6238f
AM		 6031 _bfd_error_handler (_("%pB: special symbol `%s' only allowed for "
6032 "ARMv8-M architecture or later"),
4eca0228 6033 input_bfd, sym_name);
4ba2ef8f
TP		 6034 is_v8m = TRUE; /* Avoid multiple warning. */
6035 ret = FALSE;
6036 }
6037
6038 if (cmse_invalid)
6039 {
90b6238f
AM		 6040 _bfd_error_handler (_("%pB: invalid special symbol `%s'; it must be"
6041 " a global or weak function symbol"),
4eca0228 6042 input_bfd, sym_name);
4ba2ef8f
TP		 6043 ret = FALSE;
6044 if (i < ext_start)
6045 continue;
6046 }
6047
6048 sym_name += strlen (CMSE_PREFIX);
6049 hash = (struct elf32_arm_link_hash_entry *)
6050 elf_link_hash_lookup (&(htab)->root, sym_name, FALSE, FALSE, TRUE);
6051
6052 /* No associated normal symbol or it is neither global nor weak. */
6053 if (!hash
6054 || (hash->root.root.type != bfd_link_hash_defined
6055 && hash->root.root.type != bfd_link_hash_defweak)
6056 || hash->root.type != STT_FUNC)
6057 {
6058 /* Initialize here to avoid warning about use of possibly
6059 uninitialized variable. */
6060 j = 0;
6061
6062 if (!hash)
6063 {
6064 /* Searching for a normal symbol with local binding. */
6065 for (; j < ext_start; j++)
6066 {
6067 lsym_name =
6068 bfd_elf_string_from_elf_section (input_bfd,
6069 symtab_hdr->sh_link,
6070 local_syms[j].st_name);
6071 if (!strcmp (sym_name, lsym_name))
6072 break;
6073 }
6074 }
6075
6076 if (hash || j < ext_start)
6077 {
4eca0228 6078 _bfd_error_handler
90b6238f
AM		 6079 (_("%pB: invalid standard symbol `%s'; it must be "
6080 "a global or weak function symbol"),
6081 input_bfd, sym_name);
4ba2ef8f
TP		 6082 }
6083 else
4eca0228 6084 _bfd_error_handler
90b6238f 6085 (_("%pB: absent standard symbol `%s'"), input_bfd, sym_name);
4ba2ef8f
TP		 6086 ret = FALSE;
6087 if (!hash)
6088 continue;
6089 }
6090
6091 sym_value = hash->root.root.u.def.value;
6092 section = hash->root.root.u.def.section;
6093
6094 if (cmse_hash->root.root.u.def.section != section)
6095 {
4eca0228 6096 _bfd_error_handler
90b6238f 6097 (_("%pB: `%s' and its special symbol are in different sections"),
4ba2ef8f
TP		 6098 input_bfd, sym_name);
6099 ret = FALSE;
6100 }
6101 if (cmse_hash->root.root.u.def.value != sym_value)
6102 continue; /* Ignore: could be an entry function starting with SG. */
6103
6104 /* If this section is a link-once section that will be discarded, then
6105 don't create any stubs. */
6106 if (section->output_section == NULL)
6107 {
4eca0228 6108 _bfd_error_handler
90b6238f 6109 (_("%pB: entry function `%s' not output"), input_bfd, sym_name);
4ba2ef8f
TP		 6110 continue;
6111 }
6112
6113 if (hash->root.size == 0)
6114 {
4eca0228 6115 _bfd_error_handler
90b6238f 6116 (_("%pB: entry function `%s' is empty"), input_bfd, sym_name);
4ba2ef8f
TP		 6117 ret = FALSE;
6118 }
6119
6120 if (!ret)
6121 continue;
6122 branch_type = ARM_GET_SYM_BRANCH_TYPE (hash->root.target_internal);
0955507f 6123 stub_entry
4ba2ef8f
TP		 6124 = elf32_arm_create_stub (htab, arm_stub_cmse_branch_thumb_only,
6125 NULL, NULL, section, hash, sym_name,
6126 sym_value, branch_type, &new_stub);
6127
0955507f 6128 if (stub_entry == NULL)
4ba2ef8f
TP		 6129 ret = FALSE;
6130 else
6131 {
6132 BFD_ASSERT (new_stub);
0955507f 6133 (*cmse_stub_created)++;
4ba2ef8f
TP		 6134 }
6135 }
6136
6137 if (!symtab_hdr->contents)
6138 free (local_syms);
6139 return ret;
6140}
6141
0955507f
TP		 6142/* Return TRUE iff a symbol identified by its linker HASH entry is a secure
6143 code entry function, ie can be called from non secure code without using a
6144 veneer. */
6145
6146static bfd_boolean
6147cmse_entry_fct_p (struct elf32_arm_link_hash_entry *hash)
6148{
42484486 6149 bfd_byte contents[4];
0955507f
TP		 6150 uint32_t first_insn;
6151 asection *section;
6152 file_ptr offset;
6153 bfd *abfd;
6154
6155 /* Defined symbol of function type. */
6156 if (hash->root.root.type != bfd_link_hash_defined
6157 && hash->root.root.type != bfd_link_hash_defweak)
6158 return FALSE;
6159 if (hash->root.type != STT_FUNC)
6160 return FALSE;
6161
6162 /* Read first instruction. */
6163 section = hash->root.root.u.def.section;
6164 abfd = section->owner;
6165 offset = hash->root.root.u.def.value - section->vma;
42484486
TP		 6166 if (!bfd_get_section_contents (abfd, section, contents, offset,
6167 sizeof (contents)))
0955507f
TP		 6168 return FALSE;
6169
42484486
TP		 6170 first_insn = bfd_get_32 (abfd, contents);
6171
6172 /* Starts by SG instruction. */
0955507f
TP		 6173 return first_insn == 0xe97fe97f;
6174}
6175
6176/* Output the name (in symbol table) of the veneer GEN_ENTRY if it is a new
6177 secure gateway veneers (ie. the veneers was not in the input import library)
6178 and there is no output import library (GEN_INFO->out_implib_bfd is NULL. */
6179
6180static bfd_boolean
6181arm_list_new_cmse_stub (struct bfd_hash_entry *gen_entry, void *gen_info)
6182{
6183 struct elf32_arm_stub_hash_entry *stub_entry;
6184 struct bfd_link_info *info;
6185
6186 /* Massage our args to the form they really have. */
6187 stub_entry = (struct elf32_arm_stub_hash_entry *) gen_entry;
6188 info = (struct bfd_link_info *) gen_info;
6189
6190 if (info->out_implib_bfd)
6191 return TRUE;
6192
6193 if (stub_entry->stub_type != arm_stub_cmse_branch_thumb_only)
6194 return TRUE;
6195
6196 if (stub_entry->stub_offset == (bfd_vma) -1)
4eca0228 6197 _bfd_error_handler (" %s", stub_entry->output_name);
0955507f
TP		 6198
6199 return TRUE;
6200}
6201
6202/* Set offset of each secure gateway veneers so that its address remain
6203 identical to the one in the input import library referred by
6204 HTAB->in_implib_bfd. A warning is issued for veneers that disappeared
6205 (present in input import library but absent from the executable being
6206 linked) or if new veneers appeared and there is no output import library
6207 (INFO->out_implib_bfd is NULL and *CMSE_STUB_CREATED is bigger than the
6208 number of secure gateway veneers found in the input import library.
6209
6210 The function returns whether an error occurred. If no error occurred,
6211 *CMSE_STUB_CREATED gives the number of SG veneers created by both cmse_scan
6212 and this function and HTAB->new_cmse_stub_offset is set to the biggest
6213 veneer observed set for new veneers to be layed out after. */
6214
6215static bfd_boolean
6216set_cmse_veneer_addr_from_implib (struct bfd_link_info *info,
6217 struct elf32_arm_link_hash_table *htab,
6218 int *cmse_stub_created)
6219{
6220 long symsize;
6221 char *sym_name;
6222 flagword flags;
6223 long i, symcount;
6224 bfd *in_implib_bfd;
6225 asection *stub_out_sec;
6226 bfd_boolean ret = TRUE;
6227 Elf_Internal_Sym *intsym;
6228 const char *out_sec_name;
6229 bfd_size_type cmse_stub_size;
6230 asymbol **sympp = NULL, *sym;
6231 struct elf32_arm_link_hash_entry *hash;
6232 const insn_sequence *cmse_stub_template;
6233 struct elf32_arm_stub_hash_entry *stub_entry;
6234 int cmse_stub_template_size, new_cmse_stubs_created = *cmse_stub_created;
6235 bfd_vma veneer_value, stub_offset, next_cmse_stub_offset;
6236 bfd_vma cmse_stub_array_start = (bfd_vma) -1, cmse_stub_sec_vma = 0;
6237
6238 /* No input secure gateway import library. */
6239 if (!htab->in_implib_bfd)
6240 return TRUE;
6241
6242 in_implib_bfd = htab->in_implib_bfd;
6243 if (!htab->cmse_implib)
6244 {
871b3ab2 6245 _bfd_error_handler (_("%pB: --in-implib only supported for Secure "
90b6238f 6246 "Gateway import libraries"), in_implib_bfd);
0955507f
TP		 6247 return FALSE;
6248 }
6249
6250 /* Get symbol table size. */
6251 symsize = bfd_get_symtab_upper_bound (in_implib_bfd);
6252 if (symsize < 0)
6253 return FALSE;
6254
6255 /* Read in the input secure gateway import library's symbol table. */
6256 sympp = (asymbol **) xmalloc (symsize);
6257 symcount = bfd_canonicalize_symtab (in_implib_bfd, sympp);
6258 if (symcount < 0)
6259 {
6260 ret = FALSE;
6261 goto free_sym_buf;
6262 }
6263
6264 htab->new_cmse_stub_offset = 0;
6265 cmse_stub_size =
6266 find_stub_size_and_template (arm_stub_cmse_branch_thumb_only,
6267 &cmse_stub_template,
6268 &cmse_stub_template_size);
6269 out_sec_name =
6270 arm_dedicated_stub_output_section_name (arm_stub_cmse_branch_thumb_only);
6271 stub_out_sec =
6272 bfd_get_section_by_name (htab->obfd, out_sec_name);
6273 if (stub_out_sec != NULL)
6274 cmse_stub_sec_vma = stub_out_sec->vma;
6275
6276 /* Set addresses of veneers mentionned in input secure gateway import
6277 library's symbol table. */
6278 for (i = 0; i < symcount; i++)
6279 {
6280 sym = sympp[i];
6281 flags = sym->flags;
6282 sym_name = (char *) bfd_asymbol_name (sym);
6283 intsym = &((elf_symbol_type *) sym)->internal_elf_sym;
6284
6285 if (sym->section != bfd_abs_section_ptr
6286 || !(flags & (BSF_GLOBAL | BSF_WEAK))
6287 || (flags & BSF_FUNCTION) != BSF_FUNCTION
6288 || (ARM_GET_SYM_BRANCH_TYPE (intsym->st_target_internal)
6289 != ST_BRANCH_TO_THUMB))
6290 {
90b6238f
AM		 6291 _bfd_error_handler (_("%pB: invalid import library entry: `%s'; "
6292 "symbol should be absolute, global and "
6293 "refer to Thumb functions"),
4eca0228 6294 in_implib_bfd, sym_name);
0955507f
TP		 6295 ret = FALSE;
6296 continue;
6297 }
6298
6299 veneer_value = bfd_asymbol_value (sym);
6300 stub_offset = veneer_value - cmse_stub_sec_vma;
6301 stub_entry = arm_stub_hash_lookup (&htab->stub_hash_table, sym_name,
6302 FALSE, FALSE);
6303 hash = (struct elf32_arm_link_hash_entry *)
6304 elf_link_hash_lookup (&(htab)->root, sym_name, FALSE, FALSE, TRUE);
6305
6306 /* Stub entry should have been created by cmse_scan or the symbol be of
6307 a secure function callable from non secure code. */
6308 if (!stub_entry && !hash)
6309 {
6310 bfd_boolean new_stub;
6311
4eca0228 6312 _bfd_error_handler
90b6238f 6313 (_("entry function `%s' disappeared from secure code"), sym_name);
0955507f
TP		 6314 hash = (struct elf32_arm_link_hash_entry *)
6315 elf_link_hash_lookup (&(htab)->root, sym_name, TRUE, TRUE, TRUE);
6316 stub_entry
6317 = elf32_arm_create_stub (htab, arm_stub_cmse_branch_thumb_only,
6318 NULL, NULL, bfd_abs_section_ptr, hash,
6319 sym_name, veneer_value,
6320 ST_BRANCH_TO_THUMB, &new_stub);
6321 if (stub_entry == NULL)
6322 ret = FALSE;
6323 else
6324 {
6325 BFD_ASSERT (new_stub);
6326 new_cmse_stubs_created++;
6327 (*cmse_stub_created)++;
6328 }
6329 stub_entry->stub_template_size = stub_entry->stub_size = 0;
6330 stub_entry->stub_offset = stub_offset;
6331 }
6332 /* Symbol found is not callable from non secure code. */
6333 else if (!stub_entry)
6334 {
6335 if (!cmse_entry_fct_p (hash))
6336 {
90b6238f 6337 _bfd_error_handler (_("`%s' refers to a non entry function"),
4eca0228 6338 sym_name);
0955507f
TP		 6339 ret = FALSE;
6340 }
6341 continue;
6342 }
6343 else
6344 {
6345 /* Only stubs for SG veneers should have been created. */
6346 BFD_ASSERT (stub_entry->stub_type == arm_stub_cmse_branch_thumb_only);
6347
6348 /* Check visibility hasn't changed. */
6349 if (!!(flags & BSF_GLOBAL)
6350 != (hash->root.root.type == bfd_link_hash_defined))
4eca0228 6351 _bfd_error_handler
90b6238f 6352 (_("%pB: visibility of symbol `%s' has changed"), in_implib_bfd,
0955507f
TP		 6353 sym_name);
6354
6355 stub_entry->stub_offset = stub_offset;
6356 }
6357
6358 /* Size should match that of a SG veneer. */
6359 if (intsym->st_size != cmse_stub_size)
6360 {
90b6238f 6361 _bfd_error_handler (_("%pB: incorrect size for symbol `%s'"),
4eca0228 6362 in_implib_bfd, sym_name);
0955507f
TP		 6363 ret = FALSE;
6364 }
6365
6366 /* Previous veneer address is before current SG veneer section. */
6367 if (veneer_value < cmse_stub_sec_vma)
6368 {
6369 /* Avoid offset underflow. */
6370 if (stub_entry)
6371 stub_entry->stub_offset = 0;
6372 stub_offset = 0;
6373 ret = FALSE;
6374 }
6375
6376 /* Complain if stub offset not a multiple of stub size. */
6377 if (stub_offset % cmse_stub_size)
6378 {
4eca0228 6379 _bfd_error_handler
90b6238f
AM		 6380 (_("offset of veneer for entry function `%s' not a multiple of "
6381 "its size"), sym_name);
0955507f
TP		 6382 ret = FALSE;
6383 }
6384
6385 if (!ret)
6386 continue;
6387
6388 new_cmse_stubs_created--;
6389 if (veneer_value < cmse_stub_array_start)
6390 cmse_stub_array_start = veneer_value;
6391 next_cmse_stub_offset = stub_offset + ((cmse_stub_size + 7) & ~7);
6392 if (next_cmse_stub_offset > htab->new_cmse_stub_offset)
6393 htab->new_cmse_stub_offset = next_cmse_stub_offset;
6394 }
6395
6396 if (!info->out_implib_bfd && new_cmse_stubs_created != 0)
6397 {
6398 BFD_ASSERT (new_cmse_stubs_created > 0);
4eca0228 6399 _bfd_error_handler
0955507f
TP		 6400 (_("new entry function(s) introduced but no output import library "
6401 "specified:"));
6402 bfd_hash_traverse (&htab->stub_hash_table, arm_list_new_cmse_stub, info);
6403 }
6404
6405 if (cmse_stub_array_start != cmse_stub_sec_vma)
6406 {
4eca0228 6407 _bfd_error_handler
90b6238f 6408 (_("start address of `%s' is different from previous link"),
0955507f
TP		 6409 out_sec_name);
6410 ret = FALSE;
6411 }
6412
6413free_sym_buf:
6414 free (sympp);
6415 return ret;
6416}
6417
906e58ca
NC		 6418/* Determine and set the size of the stub section for a final link.
6419
6420 The basic idea here is to examine all the relocations looking for
6421 PC-relative calls to a target that is unreachable with a "bl"
6422 instruction. */
6423
6424bfd_boolean
6425elf32_arm_size_stubs (bfd *output_bfd,
6426 bfd *stub_bfd,
6427 struct bfd_link_info *info,
6428 bfd_signed_vma group_size,
7a89b94e 6429 asection * (*add_stub_section) (const char *, asection *,
6bde4c52 6430 asection *,
7a89b94e 6431 unsigned int),
906e58ca
NC		 6432 void (*layout_sections_again) (void))
6433{
0955507f 6434 bfd_boolean ret = TRUE;
4ba2ef8f 6435 obj_attribute *out_attr;
0955507f 6436 int cmse_stub_created = 0;
906e58ca 6437 bfd_size_type stub_group_size;
4ba2ef8f 6438 bfd_boolean m_profile, stubs_always_after_branch, first_veneer_scan = TRUE;
906e58ca 6439 struct elf32_arm_link_hash_table *htab = elf32_arm_hash_table (info);
48229727 6440 struct a8_erratum_fix *a8_fixes = NULL;
eb7c4339 6441 unsigned int num_a8_fixes = 0, a8_fix_table_size = 10;
48229727
JB		 6442 struct a8_erratum_reloc *a8_relocs = NULL;
6443 unsigned int num_a8_relocs = 0, a8_reloc_table_size = 10, i;
6444
4dfe6ac6
NC		 6445 if (htab == NULL)
6446 return FALSE;
6447
48229727
JB		 6448 if (htab->fix_cortex_a8)
6449 {
21d799b5 6450 a8_fixes = (struct a8_erratum_fix *)
99059e56 6451 bfd_zmalloc (sizeof (struct a8_erratum_fix) * a8_fix_table_size);
21d799b5 6452 a8_relocs = (struct a8_erratum_reloc *)
99059e56 6453 bfd_zmalloc (sizeof (struct a8_erratum_reloc) * a8_reloc_table_size);
48229727 6454 }
906e58ca
NC		 6455
6456 /* Propagate mach to stub bfd, because it may not have been
6457 finalized when we created stub_bfd. */
6458 bfd_set_arch_mach (stub_bfd, bfd_get_arch (output_bfd),
6459 bfd_get_mach (output_bfd));
6460
6461 /* Stash our params away. */
6462 htab->stub_bfd = stub_bfd;
6463 htab->add_stub_section = add_stub_section;
6464 htab->layout_sections_again = layout_sections_again;
07d72278 6465 stubs_always_after_branch = group_size < 0;
48229727 6466
4ba2ef8f
TP		 6467 out_attr = elf_known_obj_attributes_proc (output_bfd);
6468 m_profile = out_attr[Tag_CPU_arch_profile].i == 'M';
0955507f 6469
48229727
JB		 6470 /* The Cortex-A8 erratum fix depends on stubs not being in the same 4K page
6471 as the first half of a 32-bit branch straddling two 4K pages. This is a
6472 crude way of enforcing that. */
6473 if (htab->fix_cortex_a8)
6474 stubs_always_after_branch = 1;
6475
906e58ca
NC		 6476 if (group_size < 0)
6477 stub_group_size = -group_size;
6478 else
6479 stub_group_size = group_size;
6480
6481 if (stub_group_size == 1)
6482 {
6483 /* Default values. */
6484 /* Thumb branch range is +-4MB has to be used as the default
6485 maximum size (a given section can contain both ARM and Thumb
6486 code, so the worst case has to be taken into account).
6487
6488 This value is 24K less than that, which allows for 2025
6489 12-byte stubs. If we exceed that, then we will fail to link.
6490 The user will have to relink with an explicit group size
6491 option. */
6492 stub_group_size = 4170000;
6493 }
6494
07d72278 6495 group_sections (htab, stub_group_size, stubs_always_after_branch);
906e58ca 6496
3ae046cc
NS		 6497 /* If we're applying the cortex A8 fix, we need to determine the
6498 program header size now, because we cannot change it later --
6499 that could alter section placements. Notice the A8 erratum fix
6500 ends up requiring the section addresses to remain unchanged
6501 modulo the page size. That's something we cannot represent
6502 inside BFD, and we don't want to force the section alignment to
6503 be the page size. */
6504 if (htab->fix_cortex_a8)
6505 (*htab->layout_sections_again) ();
6506
906e58ca
NC		 6507 while (1)
6508 {
6509 bfd *input_bfd;
6510 unsigned int bfd_indx;
6511 asection *stub_sec;
d7c5bd02 6512 enum elf32_arm_stub_type stub_type;
eb7c4339
NS		 6513 bfd_boolean stub_changed = FALSE;
6514 unsigned prev_num_a8_fixes = num_a8_fixes;
906e58ca 6515
48229727 6516 num_a8_fixes = 0;
906e58ca
NC		 6517 for (input_bfd = info->input_bfds, bfd_indx = 0;
6518 input_bfd != NULL;
c72f2fb2 6519 input_bfd = input_bfd->link.next, bfd_indx++)
906e58ca
NC		 6520 {
6521 Elf_Internal_Shdr *symtab_hdr;
6522 asection *section;
6523 Elf_Internal_Sym *local_syms = NULL;
6524
8c246a60
AM		 6525 if (!is_arm_elf (input_bfd)
6526 || (elf_dyn_lib_class (input_bfd) & DYN_AS_NEEDED) != 0)
99059e56 6527 continue;
adbcc655 6528
48229727
JB		 6529 num_a8_relocs = 0;
6530
906e58ca
NC		 6531 /* We'll need the symbol table in a second. */
6532 symtab_hdr = &elf_tdata (input_bfd)->symtab_hdr;
6533 if (symtab_hdr->sh_info == 0)
6534 continue;
6535
4ba2ef8f
TP		 6536 /* Limit scan of symbols to object file whose profile is
6537 Microcontroller to not hinder performance in the general case. */
6538 if (m_profile && first_veneer_scan)
6539 {
6540 struct elf_link_hash_entry **sym_hashes;
6541
6542 sym_hashes = elf_sym_hashes (input_bfd);
6543 if (!cmse_scan (input_bfd, htab, out_attr, sym_hashes,
0955507f 6544 &cmse_stub_created))
4ba2ef8f 6545 goto error_ret_free_local;
0955507f
TP		 6546
6547 if (cmse_stub_created != 0)
6548 stub_changed = TRUE;
4ba2ef8f
TP		 6549 }
6550
906e58ca
NC		 6551 /* Walk over each section attached to the input bfd. */
6552 for (section = input_bfd->sections;
6553 section != NULL;
6554 section = section->next)
6555 {
6556 Elf_Internal_Rela *internal_relocs, *irelaend, *irela;
6557
6558 /* If there aren't any relocs, then there's nothing more
6559 to do. */
6560 if ((section->flags & SEC_RELOC) == 0
6561 || section->reloc_count == 0
6562 || (section->flags & SEC_CODE) == 0)
6563 continue;
6564
6565 /* If this section is a link-once section that will be
6566 discarded, then don't create any stubs. */
6567 if (section->output_section == NULL
6568 || section->output_section->owner != output_bfd)
6569 continue;
6570
6571 /* Get the relocs. */
6572 internal_relocs
6573 = _bfd_elf_link_read_relocs (input_bfd, section, NULL,
6574 NULL, info->keep_memory);
6575 if (internal_relocs == NULL)
6576 goto error_ret_free_local;
6577
6578 /* Now examine each relocation. */
6579 irela = internal_relocs;
6580 irelaend = irela + section->reloc_count;
6581 for (; irela < irelaend; irela++)
6582 {
6583 unsigned int r_type, r_indx;
906e58ca
NC		 6584 asection *sym_sec;
6585 bfd_vma sym_value;
6586 bfd_vma destination;
6587 struct elf32_arm_link_hash_entry *hash;
7413f23f 6588 const char *sym_name;
34e77a92 6589 unsigned char st_type;
35fc36a8 6590 enum arm_st_branch_type branch_type;
48229727 6591 bfd_boolean created_stub = FALSE;
906e58ca
NC		 6592
6593 r_type = ELF32_R_TYPE (irela->r_info);
6594 r_indx = ELF32_R_SYM (irela->r_info);
6595
6596 if (r_type >= (unsigned int) R_ARM_max)
6597 {
6598 bfd_set_error (bfd_error_bad_value);
6599 error_ret_free_internal:
6600 if (elf_section_data (section)->relocs == NULL)
6601 free (internal_relocs);
15dd01b1
TP		 6602 /* Fall through. */
6603 error_ret_free_local:
6604 if (local_syms != NULL
6605 && (symtab_hdr->contents
6606 != (unsigned char *) local_syms))
6607 free (local_syms);
6608 return FALSE;
906e58ca 6609 }
b38cadfb 6610
0855e32b
NS		 6611 hash = NULL;
6612 if (r_indx >= symtab_hdr->sh_info)
6613 hash = elf32_arm_hash_entry
6614 (elf_sym_hashes (input_bfd)
6615 [r_indx - symtab_hdr->sh_info]);
b38cadfb 6616
0855e32b
NS		 6617 /* Only look for stubs on branch instructions, or
6618 non-relaxed TLSCALL */
906e58ca 6619 if ((r_type != (unsigned int) R_ARM_CALL)
155d87d7
CL		 6620 && (r_type != (unsigned int) R_ARM_THM_CALL)
6621 && (r_type != (unsigned int) R_ARM_JUMP24)
48229727
JB		 6622 && (r_type != (unsigned int) R_ARM_THM_JUMP19)
6623 && (r_type != (unsigned int) R_ARM_THM_XPC22)
155d87d7 6624 && (r_type != (unsigned int) R_ARM_THM_JUMP24)
0855e32b
NS		 6625 && (r_type != (unsigned int) R_ARM_PLT32)
6626 && !((r_type == (unsigned int) R_ARM_TLS_CALL
6627 || r_type == (unsigned int) R_ARM_THM_TLS_CALL)
6628 && r_type == elf32_arm_tls_transition
6629 (info, r_type, &hash->root)
6630 && ((hash ? hash->tls_type
6631 : (elf32_arm_local_got_tls_type
6632 (input_bfd)[r_indx]))
6633 & GOT_TLS_GDESC) != 0))
906e58ca
NC		 6634 continue;
6635
6636 /* Now determine the call target, its name, value,
6637 section. */
6638 sym_sec = NULL;
6639 sym_value = 0;
6640 destination = 0;
7413f23f 6641 sym_name = NULL;
b38cadfb 6642
0855e32b
NS		 6643 if (r_type == (unsigned int) R_ARM_TLS_CALL
6644 || r_type == (unsigned int) R_ARM_THM_TLS_CALL)
6645 {
6646 /* A non-relaxed TLS call. The target is the
6647 plt-resident trampoline and nothing to do
6648 with the symbol. */
6649 BFD_ASSERT (htab->tls_trampoline > 0);
6650 sym_sec = htab->root.splt;
6651 sym_value = htab->tls_trampoline;
6652 hash = 0;
34e77a92 6653 st_type = STT_FUNC;
35fc36a8 6654 branch_type = ST_BRANCH_TO_ARM;
0855e32b
NS		 6655 }
6656 else if (!hash)
906e58ca
NC		 6657 {
6658 /* It's a local symbol. */
6659 Elf_Internal_Sym *sym;
906e58ca
NC		 6660
6661 if (local_syms == NULL)
6662 {
6663 local_syms
6664 = (Elf_Internal_Sym *) symtab_hdr->contents;
6665 if (local_syms == NULL)
6666 local_syms
6667 = bfd_elf_get_elf_syms (input_bfd, symtab_hdr,
6668 symtab_hdr->sh_info, 0,
6669 NULL, NULL, NULL);
6670 if (local_syms == NULL)
6671 goto error_ret_free_internal;
6672 }
6673
6674 sym = local_syms + r_indx;
f6d250ce
TS		 6675 if (sym->st_shndx == SHN_UNDEF)
6676 sym_sec = bfd_und_section_ptr;
6677 else if (sym->st_shndx == SHN_ABS)
6678 sym_sec = bfd_abs_section_ptr;
6679 else if (sym->st_shndx == SHN_COMMON)
6680 sym_sec = bfd_com_section_ptr;
6681 else
6682 sym_sec =
6683 bfd_section_from_elf_index (input_bfd, sym->st_shndx);
6684
ffcb4889
NS		 6685 if (!sym_sec)
6686 /* This is an undefined symbol. It can never
6a631e86 6687 be resolved. */
ffcb4889 6688 continue;
fe33d2fa 6689
906e58ca
NC		 6690 if (ELF_ST_TYPE (sym->st_info) != STT_SECTION)
6691 sym_value = sym->st_value;
6692 destination = (sym_value + irela->r_addend
6693 + sym_sec->output_offset
6694 + sym_sec->output_section->vma);
34e77a92 6695 st_type = ELF_ST_TYPE (sym->st_info);
39d911fc
TP		 6696 branch_type =
6697 ARM_GET_SYM_BRANCH_TYPE (sym->st_target_internal);
7413f23f
DJ		 6698 sym_name
6699 = bfd_elf_string_from_elf_section (input_bfd,
6700 symtab_hdr->sh_link,
6701 sym->st_name);
906e58ca
NC		 6702 }
6703 else
6704 {
6705 /* It's an external symbol. */
906e58ca
NC		 6706 while (hash->root.root.type == bfd_link_hash_indirect
6707 || hash->root.root.type == bfd_link_hash_warning)
6708 hash = ((struct elf32_arm_link_hash_entry *)
6709 hash->root.root.u.i.link);
6710
6711 if (hash->root.root.type == bfd_link_hash_defined
6712 || hash->root.root.type == bfd_link_hash_defweak)
6713 {
6714 sym_sec = hash->root.root.u.def.section;
6715 sym_value = hash->root.root.u.def.value;
022f8312
CL		 6716
6717 struct elf32_arm_link_hash_table *globals =
6718 elf32_arm_hash_table (info);
6719
6720 /* For a destination in a shared library,
6721 use the PLT stub as target address to
6722 decide whether a branch stub is
6723 needed. */
4dfe6ac6 6724 if (globals != NULL
362d30a1 6725 && globals->root.splt != NULL
4dfe6ac6 6726 && hash != NULL
022f8312
CL		 6727 && hash->root.plt.offset != (bfd_vma) -1)
6728 {
362d30a1 6729 sym_sec = globals->root.splt;
022f8312
CL		 6730 sym_value = hash->root.plt.offset;
6731 if (sym_sec->output_section != NULL)
6732 destination = (sym_value
6733 + sym_sec->output_offset
6734 + sym_sec->output_section->vma);
6735 }
6736 else if (sym_sec->output_section != NULL)
906e58ca
NC		 6737 destination = (sym_value + irela->r_addend
6738 + sym_sec->output_offset
6739 + sym_sec->output_section->vma);
6740 }
69c5861e
CL		 6741 else if ((hash->root.root.type == bfd_link_hash_undefined)
6742 || (hash->root.root.type == bfd_link_hash_undefweak))
6743 {
6744 /* For a shared library, use the PLT stub as
6745 target address to decide whether a long
6746 branch stub is needed.
6747 For absolute code, they cannot be handled. */
6748 struct elf32_arm_link_hash_table *globals =
6749 elf32_arm_hash_table (info);
6750
4dfe6ac6 6751 if (globals != NULL
362d30a1 6752 && globals->root.splt != NULL
4dfe6ac6 6753 && hash != NULL
69c5861e
CL		 6754 && hash->root.plt.offset != (bfd_vma) -1)
6755 {
362d30a1 6756 sym_sec = globals->root.splt;
69c5861e
CL		 6757 sym_value = hash->root.plt.offset;
6758 if (sym_sec->output_section != NULL)
6759 destination = (sym_value
6760 + sym_sec->output_offset
6761 + sym_sec->output_section->vma);
6762 }
6763 else
6764 continue;
6765 }
906e58ca
NC		 6766 else
6767 {
6768 bfd_set_error (bfd_error_bad_value);
6769 goto error_ret_free_internal;
6770 }
34e77a92 6771 st_type = hash->root.type;
39d911fc
TP		 6772 branch_type =
6773 ARM_GET_SYM_BRANCH_TYPE (hash->root.target_internal);
7413f23f 6774 sym_name = hash->root.root.root.string;
906e58ca
NC		 6775 }
6776
48229727 6777 do
7413f23f 6778 {
b715f643 6779 bfd_boolean new_stub;
0955507f 6780 struct elf32_arm_stub_hash_entry *stub_entry;
b715f643 6781
48229727
JB		 6782 /* Determine what (if any) linker stub is needed. */
6783 stub_type = arm_type_of_stub (info, section, irela,
34e77a92
RS		 6784 st_type, &branch_type,
6785 hash, destination, sym_sec,
48229727
JB		 6786 input_bfd, sym_name);
6787 if (stub_type == arm_stub_none)
6788 break;
6789
48229727
JB		 6790 /* We've either created a stub for this reloc already,
6791 or we are about to. */
0955507f 6792 stub_entry =
b715f643
TP		 6793 elf32_arm_create_stub (htab, stub_type, section, irela,
6794 sym_sec, hash,
6795 (char *) sym_name, sym_value,
6796 branch_type, &new_stub);
7413f23f 6797
0955507f 6798 created_stub = stub_entry != NULL;
b715f643
TP		 6799 if (!created_stub)
6800 goto error_ret_free_internal;
6801 else if (!new_stub)
6802 break;
99059e56 6803 else
b715f643 6804 stub_changed = TRUE;
99059e56
RM		 6805 }
6806 while (0);
6807
6808 /* Look for relocations which might trigger Cortex-A8
6809 erratum. */
6810 if (htab->fix_cortex_a8
6811 && (r_type == (unsigned int) R_ARM_THM_JUMP24
6812 || r_type == (unsigned int) R_ARM_THM_JUMP19
6813 || r_type == (unsigned int) R_ARM_THM_CALL
6814 || r_type == (unsigned int) R_ARM_THM_XPC22))
6815 {
6816 bfd_vma from = section->output_section->vma
6817 + section->output_offset
6818 + irela->r_offset;
6819
6820 if ((from & 0xfff) == 0xffe)
6821 {
6822 /* Found a candidate. Note we haven't checked the
6823 destination is within 4K here: if we do so (and
6824 don't create an entry in a8_relocs) we can't tell
6825 that a branch should have been relocated when
6826 scanning later. */
6827 if (num_a8_relocs == a8_reloc_table_size)
6828 {
6829 a8_reloc_table_size *= 2;
6830 a8_relocs = (struct a8_erratum_reloc *)
6831 bfd_realloc (a8_relocs,
6832 sizeof (struct a8_erratum_reloc)
6833 * a8_reloc_table_size);
6834 }
6835
6836 a8_relocs[num_a8_relocs].from = from;
6837 a8_relocs[num_a8_relocs].destination = destination;
6838 a8_relocs[num_a8_relocs].r_type = r_type;
6839 a8_relocs[num_a8_relocs].branch_type = branch_type;
6840 a8_relocs[num_a8_relocs].sym_name = sym_name;
6841 a8_relocs[num_a8_relocs].non_a8_stub = created_stub;
6842 a8_relocs[num_a8_relocs].hash = hash;
6843
6844 num_a8_relocs++;
6845 }
6846 }
906e58ca
NC		 6847 }
6848
99059e56
RM		 6849 /* We're done with the internal relocs, free them. */
6850 if (elf_section_data (section)->relocs == NULL)
6851 free (internal_relocs);
6852 }
48229727 6853
99059e56 6854 if (htab->fix_cortex_a8)
48229727 6855 {
99059e56
RM		 6856 /* Sort relocs which might apply to Cortex-A8 erratum. */
6857 qsort (a8_relocs, num_a8_relocs,
eb7c4339 6858 sizeof (struct a8_erratum_reloc),
99059e56 6859 &a8_reloc_compare);
48229727 6860
99059e56
RM		 6861 /* Scan for branches which might trigger Cortex-A8 erratum. */
6862 if (cortex_a8_erratum_scan (input_bfd, info, &a8_fixes,
48229727 6863 &num_a8_fixes, &a8_fix_table_size,
eb7c4339
NS		 6864 a8_relocs, num_a8_relocs,
6865 prev_num_a8_fixes, &stub_changed)
6866 != 0)
48229727 6867 goto error_ret_free_local;
5e681ec4 6868 }
7f991970
AM		 6869
6870 if (local_syms != NULL
6871 && symtab_hdr->contents != (unsigned char *) local_syms)
6872 {
6873 if (!info->keep_memory)
6874 free (local_syms);
6875 else
6876 symtab_hdr->contents = (unsigned char *) local_syms;
6877 }
5e681ec4
PB		 6878 }
6879
0955507f
TP		 6880 if (first_veneer_scan
6881 && !set_cmse_veneer_addr_from_implib (info, htab,
6882 &cmse_stub_created))
6883 ret = FALSE;
6884
eb7c4339 6885 if (prev_num_a8_fixes != num_a8_fixes)
99059e56 6886 stub_changed = TRUE;
48229727 6887
906e58ca
NC		 6888 if (!stub_changed)
6889 break;
5e681ec4 6890
906e58ca
NC		 6891 /* OK, we've added some stubs. Find out the new size of the
6892 stub sections. */
6893 for (stub_sec = htab->stub_bfd->sections;
6894 stub_sec != NULL;
6895 stub_sec = stub_sec->next)
3e6b1042
DJ		 6896 {
6897 /* Ignore non-stub sections. */
6898 if (!strstr (stub_sec->name, STUB_SUFFIX))
6899 continue;
6900
6901 stub_sec->size = 0;
6902 }
b34b2d70 6903
0955507f
TP		 6904 /* Add new SG veneers after those already in the input import
6905 library. */
6906 for (stub_type = arm_stub_none + 1; stub_type < max_stub_type;
6907 stub_type++)
6908 {
6909 bfd_vma *start_offset_p;
6910 asection **stub_sec_p;
6911
6912 start_offset_p = arm_new_stubs_start_offset_ptr (htab, stub_type);
6913 stub_sec_p = arm_dedicated_stub_input_section_ptr (htab, stub_type);
6914 if (start_offset_p == NULL)
6915 continue;
6916
6917 BFD_ASSERT (stub_sec_p != NULL);
6918 if (*stub_sec_p != NULL)
6919 (*stub_sec_p)->size = *start_offset_p;
6920 }
6921
d7c5bd02 6922 /* Compute stub section size, considering padding. */
906e58ca 6923 bfd_hash_traverse (&htab->stub_hash_table, arm_size_one_stub, htab);
d7c5bd02
TP		 6924 for (stub_type = arm_stub_none + 1; stub_type < max_stub_type;
6925 stub_type++)
6926 {
6927 int size, padding;
6928 asection **stub_sec_p;
6929
6930 padding = arm_dedicated_stub_section_padding (stub_type);
6931 stub_sec_p = arm_dedicated_stub_input_section_ptr (htab, stub_type);
6932 /* Skip if no stub input section or no stub section padding
6933 required. */
6934 if ((stub_sec_p != NULL && *stub_sec_p == NULL) || padding == 0)
6935 continue;
6936 /* Stub section padding required but no dedicated section. */
6937 BFD_ASSERT (stub_sec_p);
6938
6939 size = (*stub_sec_p)->size;
6940 size = (size + padding - 1) & ~(padding - 1);
6941 (*stub_sec_p)->size = size;
6942 }
906e58ca 6943
48229727
JB		 6944 /* Add Cortex-A8 erratum veneers to stub section sizes too. */
6945 if (htab->fix_cortex_a8)
99059e56
RM		 6946 for (i = 0; i < num_a8_fixes; i++)
6947 {
48229727 6948 stub_sec = elf32_arm_create_or_find_stub_sec (NULL,
daa4adae 6949 a8_fixes[i].section, htab, a8_fixes[i].stub_type);
48229727
JB		 6950
6951 if (stub_sec == NULL)
7f991970 6952 return FALSE;
48229727 6953
99059e56
RM		 6954 stub_sec->size
6955 += find_stub_size_and_template (a8_fixes[i].stub_type, NULL,
6956 NULL);
6957 }
48229727
JB		 6958
6959
906e58ca
NC		 6960 /* Ask the linker to do its stuff. */
6961 (*htab->layout_sections_again) ();
4ba2ef8f 6962 first_veneer_scan = FALSE;
ba93b8ac
DJ		 6963 }
6964
48229727
JB		 6965 /* Add stubs for Cortex-A8 erratum fixes now. */
6966 if (htab->fix_cortex_a8)
6967 {
6968 for (i = 0; i < num_a8_fixes; i++)
99059e56
RM		 6969 {
6970 struct elf32_arm_stub_hash_entry *stub_entry;
6971 char *stub_name = a8_fixes[i].stub_name;
6972 asection *section = a8_fixes[i].section;
6973 unsigned int section_id = a8_fixes[i].section->id;
6974 asection *link_sec = htab->stub_group[section_id].link_sec;
6975 asection *stub_sec = htab->stub_group[section_id].stub_sec;
6976 const insn_sequence *template_sequence;
6977 int template_size, size = 0;
6978
6979 stub_entry = arm_stub_hash_lookup (&htab->stub_hash_table, stub_name,
6980 TRUE, FALSE);
6981 if (stub_entry == NULL)
6982 {
871b3ab2 6983 _bfd_error_handler (_("%pB: cannot create stub entry %s"),
4eca0228 6984 section->owner, stub_name);
99059e56
RM		 6985 return FALSE;
6986 }
6987
6988 stub_entry->stub_sec = stub_sec;
0955507f 6989 stub_entry->stub_offset = (bfd_vma) -1;
99059e56
RM		 6990 stub_entry->id_sec = link_sec;
6991 stub_entry->stub_type = a8_fixes[i].stub_type;
8d9d9490 6992 stub_entry->source_value = a8_fixes[i].offset;
99059e56 6993 stub_entry->target_section = a8_fixes[i].section;
8d9d9490 6994 stub_entry->target_value = a8_fixes[i].target_offset;
99059e56 6995 stub_entry->orig_insn = a8_fixes[i].orig_insn;
35fc36a8 6996 stub_entry->branch_type = a8_fixes[i].branch_type;
48229727 6997
99059e56
RM		 6998 size = find_stub_size_and_template (a8_fixes[i].stub_type,
6999 &template_sequence,
7000 &template_size);
48229727 7001
99059e56
RM		 7002 stub_entry->stub_size = size;
7003 stub_entry->stub_template = template_sequence;
7004 stub_entry->stub_template_size = template_size;
7005 }
48229727
JB		 7006
7007 /* Stash the Cortex-A8 erratum fix array for use later in
99059e56 7008 elf32_arm_write_section(). */
48229727
JB		 7009 htab->a8_erratum_fixes = a8_fixes;
7010 htab->num_a8_erratum_fixes = num_a8_fixes;
7011 }
7012 else
7013 {
7014 htab->a8_erratum_fixes = NULL;
7015 htab->num_a8_erratum_fixes = 0;
7016 }
0955507f 7017 return ret;
5e681ec4
PB		 7018}
7019
906e58ca
NC		 7020/* Build all the stubs associated with the current output file. The
7021 stubs are kept in a hash table attached to the main linker hash
7022 table. We also set up the .plt entries for statically linked PIC
7023 functions here. This function is called via arm_elf_finish in the
7024 linker. */
252b5132 7025
906e58ca
NC		 7026bfd_boolean
7027elf32_arm_build_stubs (struct bfd_link_info *info)
252b5132 7028{
906e58ca
NC		 7029 asection *stub_sec;
7030 struct bfd_hash_table *table;
0955507f 7031 enum elf32_arm_stub_type stub_type;
906e58ca 7032 struct elf32_arm_link_hash_table *htab;
252b5132 7033
906e58ca 7034 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 7035 if (htab == NULL)
7036 return FALSE;
252b5132 7037
906e58ca
NC		 7038 for (stub_sec = htab->stub_bfd->sections;
7039 stub_sec != NULL;
7040 stub_sec = stub_sec->next)
252b5132 7041 {
906e58ca
NC		 7042 bfd_size_type size;
7043
8029a119 7044 /* Ignore non-stub sections. */
906e58ca
NC		 7045 if (!strstr (stub_sec->name, STUB_SUFFIX))
7046 continue;
7047
d7c5bd02 7048 /* Allocate memory to hold the linker stubs. Zeroing the stub sections
0955507f
TP		 7049 must at least be done for stub section requiring padding and for SG
7050 veneers to ensure that a non secure code branching to a removed SG
7051 veneer causes an error. */
906e58ca 7052 size = stub_sec->size;
21d799b5 7053 stub_sec->contents = (unsigned char *) bfd_zalloc (htab->stub_bfd, size);
906e58ca
NC		 7054 if (stub_sec->contents == NULL && size != 0)
7055 return FALSE;
0955507f 7056
906e58ca 7057 stub_sec->size = 0;
252b5132
RH		 7058 }
7059
0955507f
TP		 7060 /* Add new SG veneers after those already in the input import library. */
7061 for (stub_type = arm_stub_none + 1; stub_type < max_stub_type; stub_type++)
7062 {
7063 bfd_vma *start_offset_p;
7064 asection **stub_sec_p;
7065
7066 start_offset_p = arm_new_stubs_start_offset_ptr (htab, stub_type);
7067 stub_sec_p = arm_dedicated_stub_input_section_ptr (htab, stub_type);
7068 if (start_offset_p == NULL)
7069 continue;
7070
7071 BFD_ASSERT (stub_sec_p != NULL);
7072 if (*stub_sec_p != NULL)
7073 (*stub_sec_p)->size = *start_offset_p;
7074 }
7075
906e58ca
NC		 7076 /* Build the stubs as directed by the stub hash table. */
7077 table = &htab->stub_hash_table;
7078 bfd_hash_traverse (table, arm_build_one_stub, info);
eb7c4339
NS		 7079 if (htab->fix_cortex_a8)
7080 {
7081 /* Place the cortex a8 stubs last. */
7082 htab->fix_cortex_a8 = -1;
7083 bfd_hash_traverse (table, arm_build_one_stub, info);
7084 }
252b5132 7085
906e58ca 7086 return TRUE;
252b5132
RH		 7087}
7088
9b485d32
NC		 7089/* Locate the Thumb encoded calling stub for NAME. */
7090
252b5132 7091static struct elf_link_hash_entry *
57e8b36a
NC		 7092find_thumb_glue (struct bfd_link_info *link_info,
7093 const char *name,
f2a9dd69 7094 char **error_message)
252b5132
RH		 7095{
7096 char *tmp_name;
7097 struct elf_link_hash_entry *hash;
7098 struct elf32_arm_link_hash_table *hash_table;
7099
7100 /* We need a pointer to the armelf specific hash table. */
7101 hash_table = elf32_arm_hash_table (link_info);
4dfe6ac6
NC		 7102 if (hash_table == NULL)
7103 return NULL;
252b5132 7104
21d799b5 7105 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen (name)
99059e56 7106 + strlen (THUMB2ARM_GLUE_ENTRY_NAME) + 1);
252b5132
RH		 7107
7108 BFD_ASSERT (tmp_name);
7109
7110 sprintf (tmp_name, THUMB2ARM_GLUE_ENTRY_NAME, name);
7111
7112 hash = elf_link_hash_lookup
b34976b6 7113 (&(hash_table)->root, tmp_name, FALSE, FALSE, TRUE);
252b5132 7114
b1657152 7115 if (hash == NULL
90b6238f
AM		 7116 && asprintf (error_message, _("unable to find %s glue '%s' for '%s'"),
7117 "Thumb", tmp_name, name) == -1)
b1657152 7118 *error_message = (char *) bfd_errmsg (bfd_error_system_call);
252b5132
RH		 7119
7120 free (tmp_name);
7121
7122 return hash;
7123}
7124
9b485d32
NC		 7125/* Locate the ARM encoded calling stub for NAME. */
7126
252b5132 7127static struct elf_link_hash_entry *
57e8b36a
NC		 7128find_arm_glue (struct bfd_link_info *link_info,
7129 const char *name,
f2a9dd69 7130 char **error_message)
252b5132
RH		 7131{
7132 char *tmp_name;
7133 struct elf_link_hash_entry *myh;
7134 struct elf32_arm_link_hash_table *hash_table;
7135
7136 /* We need a pointer to the elfarm specific hash table. */
7137 hash_table = elf32_arm_hash_table (link_info);
4dfe6ac6
NC		 7138 if (hash_table == NULL)
7139 return NULL;
252b5132 7140
21d799b5 7141 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen (name)
99059e56 7142 + strlen (ARM2THUMB_GLUE_ENTRY_NAME) + 1);
252b5132
RH		 7143
7144 BFD_ASSERT (tmp_name);
7145
7146 sprintf (tmp_name, ARM2THUMB_GLUE_ENTRY_NAME, name);
7147
7148 myh = elf_link_hash_lookup
b34976b6 7149 (&(hash_table)->root, tmp_name, FALSE, FALSE, TRUE);
252b5132 7150
b1657152 7151 if (myh == NULL
90b6238f
AM		 7152 && asprintf (error_message, _("unable to find %s glue '%s' for '%s'"),
7153 "ARM", tmp_name, name) == -1)
b1657152 7154 *error_message = (char *) bfd_errmsg (bfd_error_system_call);
252b5132
RH		 7155
7156 free (tmp_name);
7157
7158 return myh;
7159}
7160
8f6277f5 7161/* ARM->Thumb glue (static images):
252b5132
RH		 7162
7163 .arm
7164 __func_from_arm:
7165 ldr r12, __func_addr
7166 bx r12
7167 __func_addr:
906e58ca 7168 .word func @ behave as if you saw a ARM_32 reloc.
252b5132 7169
26079076
PB		 7170 (v5t static images)
7171 .arm
7172 __func_from_arm:
7173 ldr pc, __func_addr
7174 __func_addr:
906e58ca 7175 .word func @ behave as if you saw a ARM_32 reloc.
26079076 7176
8f6277f5
PB		 7177 (relocatable images)
7178 .arm
7179 __func_from_arm:
7180 ldr r12, __func_offset
7181 add r12, r12, pc
7182 bx r12
7183 __func_offset:
8029a119 7184 .word func - . */
8f6277f5
PB		 7185
7186#define ARM2THUMB_STATIC_GLUE_SIZE 12
252b5132
RH		 7187static const insn32 a2t1_ldr_insn = 0xe59fc000;
7188static const insn32 a2t2_bx_r12_insn = 0xe12fff1c;
7189static const insn32 a2t3_func_addr_insn = 0x00000001;
7190
26079076
PB		 7191#define ARM2THUMB_V5_STATIC_GLUE_SIZE 8
7192static const insn32 a2t1v5_ldr_insn = 0xe51ff004;
7193static const insn32 a2t2v5_func_addr_insn = 0x00000001;
7194
8f6277f5
PB		 7195#define ARM2THUMB_PIC_GLUE_SIZE 16
7196static const insn32 a2t1p_ldr_insn = 0xe59fc004;
7197static const insn32 a2t2p_add_pc_insn = 0xe08cc00f;
7198static const insn32 a2t3p_bx_r12_insn = 0xe12fff1c;
7199
07d6d2b8 7200/* Thumb->ARM: Thumb->(non-interworking aware) ARM
252b5132 7201
07d6d2b8
AM		 7202 .thumb .thumb
7203 .align 2 .align 2
7204 __func_from_thumb: __func_from_thumb:
7205 bx pc push {r6, lr}
7206 nop ldr r6, __func_addr
7207 .arm mov lr, pc
7208 b func bx r6
99059e56
RM		 7209 .arm
7210 ;; back_to_thumb
7211 ldmia r13! {r6, lr}
7212 bx lr
7213 __func_addr:
07d6d2b8 7214 .word func */
252b5132
RH		 7215
7216#define THUMB2ARM_GLUE_SIZE 8
7217static const insn16 t2a1_bx_pc_insn = 0x4778;
7218static const insn16 t2a2_noop_insn = 0x46c0;
7219static const insn32 t2a3_b_insn = 0xea000000;
7220
c7b8f16e 7221#define VFP11_ERRATUM_VENEER_SIZE 8
a504d23a
LA		 7222#define STM32L4XX_ERRATUM_LDM_VENEER_SIZE 16
7223#define STM32L4XX_ERRATUM_VLDM_VENEER_SIZE 24
c7b8f16e 7224
845b51d6
PB		 7225#define ARM_BX_VENEER_SIZE 12
7226static const insn32 armbx1_tst_insn = 0xe3100001;
7227static const insn32 armbx2_moveq_insn = 0x01a0f000;
7228static const insn32 armbx3_bx_insn = 0xe12fff10;
7229
7e392df6 7230#ifndef ELFARM_NABI_C_INCLUDED
8029a119
NC		 7231static void
7232arm_allocate_glue_section_space (bfd * abfd, bfd_size_type size, const char * name)
252b5132
RH		 7233{
7234 asection * s;
8029a119 7235 bfd_byte * contents;
252b5132 7236
8029a119 7237 if (size == 0)
3e6b1042
DJ		 7238 {
7239 /* Do not include empty glue sections in the output. */
7240 if (abfd != NULL)
7241 {
3d4d4302 7242 s = bfd_get_linker_section (abfd, name);
3e6b1042
DJ		 7243 if (s != NULL)
7244 s->flags |= SEC_EXCLUDE;
7245 }
7246 return;
7247 }
252b5132 7248
8029a119 7249 BFD_ASSERT (abfd != NULL);
252b5132 7250
3d4d4302 7251 s = bfd_get_linker_section (abfd, name);
8029a119 7252 BFD_ASSERT (s != NULL);
252b5132 7253
b0f4fbf8 7254 contents = (bfd_byte *) bfd_zalloc (abfd, size);
252b5132 7255
8029a119
NC		 7256 BFD_ASSERT (s->size == size);
7257 s->contents = contents;
7258}
906e58ca 7259
8029a119
NC		 7260bfd_boolean
7261bfd_elf32_arm_allocate_interworking_sections (struct bfd_link_info * info)
7262{
7263 struct elf32_arm_link_hash_table * globals;
906e58ca 7264
8029a119
NC		 7265 globals = elf32_arm_hash_table (info);
7266 BFD_ASSERT (globals != NULL);
906e58ca 7267
8029a119
NC		 7268 arm_allocate_glue_section_space (globals->bfd_of_glue_owner,
7269 globals->arm_glue_size,
7270 ARM2THUMB_GLUE_SECTION_NAME);
906e58ca 7271
8029a119
NC		 7272 arm_allocate_glue_section_space (globals->bfd_of_glue_owner,
7273 globals->thumb_glue_size,
7274 THUMB2ARM_GLUE_SECTION_NAME);
252b5132 7275
8029a119
NC		 7276 arm_allocate_glue_section_space (globals->bfd_of_glue_owner,
7277 globals->vfp11_erratum_glue_size,
7278 VFP11_ERRATUM_VENEER_SECTION_NAME);
845b51d6 7279
a504d23a
LA		 7280 arm_allocate_glue_section_space (globals->bfd_of_glue_owner,
7281 globals->stm32l4xx_erratum_glue_size,
7282 STM32L4XX_ERRATUM_VENEER_SECTION_NAME);
7283
8029a119
NC		 7284 arm_allocate_glue_section_space (globals->bfd_of_glue_owner,
7285 globals->bx_glue_size,
845b51d6
PB		 7286 ARM_BX_GLUE_SECTION_NAME);
7287
b34976b6 7288 return TRUE;
252b5132
RH		 7289}
7290
a4fd1a8e 7291/* Allocate space and symbols for calling a Thumb function from Arm mode.
906e58ca
NC		 7292 returns the symbol identifying the stub. */
7293
a4fd1a8e 7294static struct elf_link_hash_entry *
57e8b36a
NC		 7295record_arm_to_thumb_glue (struct bfd_link_info * link_info,
7296 struct elf_link_hash_entry * h)
252b5132
RH		 7297{
7298 const char * name = h->root.root.string;
63b0f745 7299 asection * s;
252b5132
RH		 7300 char * tmp_name;
7301 struct elf_link_hash_entry * myh;
14a793b2 7302 struct bfd_link_hash_entry * bh;
252b5132 7303 struct elf32_arm_link_hash_table * globals;
dc810e39 7304 bfd_vma val;
2f475487 7305 bfd_size_type size;
252b5132
RH		 7306
7307 globals = elf32_arm_hash_table (link_info);
252b5132
RH		 7308 BFD_ASSERT (globals != NULL);
7309 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
7310
3d4d4302 7311 s = bfd_get_linker_section
252b5132
RH		 7312 (globals->bfd_of_glue_owner, ARM2THUMB_GLUE_SECTION_NAME);
7313
252b5132
RH		 7314 BFD_ASSERT (s != NULL);
7315
21d799b5 7316 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen (name)
99059e56 7317 + strlen (ARM2THUMB_GLUE_ENTRY_NAME) + 1);
252b5132
RH		 7318
7319 BFD_ASSERT (tmp_name);
7320
7321 sprintf (tmp_name, ARM2THUMB_GLUE_ENTRY_NAME, name);
7322
7323 myh = elf_link_hash_lookup
b34976b6 7324 (&(globals)->root, tmp_name, FALSE, FALSE, TRUE);
252b5132
RH		 7325
7326 if (myh != NULL)
7327 {
9b485d32 7328 /* We've already seen this guy. */
252b5132 7329 free (tmp_name);
a4fd1a8e 7330 return myh;
252b5132
RH		 7331 }
7332
57e8b36a
NC		 7333 /* The only trick here is using hash_table->arm_glue_size as the value.
7334 Even though the section isn't allocated yet, this is where we will be
3dccd7b7
DJ		 7335 putting it. The +1 on the value marks that the stub has not been
7336 output yet - not that it is a Thumb function. */
14a793b2 7337 bh = NULL;
dc810e39
AM		 7338 val = globals->arm_glue_size + 1;
7339 _bfd_generic_link_add_one_symbol (link_info, globals->bfd_of_glue_owner,
7340 tmp_name, BSF_GLOBAL, s, val,
b34976b6 7341 NULL, TRUE, FALSE, &bh);
252b5132 7342
b7693d02
DJ		 7343 myh = (struct elf_link_hash_entry *) bh;
7344 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
7345 myh->forced_local = 1;
7346
252b5132
RH		 7347 free (tmp_name);
7348
0e1862bb
L		 7349 if (bfd_link_pic (link_info)
7350 || globals->root.is_relocatable_executable
27e55c4d 7351 || globals->pic_veneer)
2f475487 7352 size = ARM2THUMB_PIC_GLUE_SIZE;
26079076
PB		 7353 else if (globals->use_blx)
7354 size = ARM2THUMB_V5_STATIC_GLUE_SIZE;
8f6277f5 7355 else
2f475487
AM		 7356 size = ARM2THUMB_STATIC_GLUE_SIZE;
7357
7358 s->size += size;
7359 globals->arm_glue_size += size;
252b5132 7360
a4fd1a8e 7361 return myh;
252b5132
RH		 7362}
7363
845b51d6
PB		 7364/* Allocate space for ARMv4 BX veneers. */
7365
7366static void
7367record_arm_bx_glue (struct bfd_link_info * link_info, int reg)
7368{
7369 asection * s;
7370 struct elf32_arm_link_hash_table *globals;
7371 char *tmp_name;
7372 struct elf_link_hash_entry *myh;
7373 struct bfd_link_hash_entry *bh;
7374 bfd_vma val;
7375
7376 /* BX PC does not need a veneer. */
7377 if (reg == 15)
7378 return;
7379
7380 globals = elf32_arm_hash_table (link_info);
845b51d6
PB		 7381 BFD_ASSERT (globals != NULL);
7382 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
7383
7384 /* Check if this veneer has already been allocated. */
7385 if (globals->bx_glue_offset[reg])
7386 return;
7387
3d4d4302 7388 s = bfd_get_linker_section
845b51d6
PB		 7389 (globals->bfd_of_glue_owner, ARM_BX_GLUE_SECTION_NAME);
7390
7391 BFD_ASSERT (s != NULL);
7392
7393 /* Add symbol for veneer. */
21d799b5
NC		 7394 tmp_name = (char *)
7395 bfd_malloc ((bfd_size_type) strlen (ARM_BX_GLUE_ENTRY_NAME) + 1);
906e58ca 7396
845b51d6 7397 BFD_ASSERT (tmp_name);
906e58ca 7398
845b51d6 7399 sprintf (tmp_name, ARM_BX_GLUE_ENTRY_NAME, reg);
906e58ca 7400
845b51d6
PB		 7401 myh = elf_link_hash_lookup
7402 (&(globals)->root, tmp_name, FALSE, FALSE, FALSE);
906e58ca 7403
845b51d6 7404 BFD_ASSERT (myh == NULL);
906e58ca 7405
845b51d6
PB		 7406 bh = NULL;
7407 val = globals->bx_glue_size;
7408 _bfd_generic_link_add_one_symbol (link_info, globals->bfd_of_glue_owner,
99059e56
RM		 7409 tmp_name, BSF_FUNCTION | BSF_LOCAL, s, val,
7410 NULL, TRUE, FALSE, &bh);
845b51d6
PB		 7411
7412 myh = (struct elf_link_hash_entry *) bh;
7413 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
7414 myh->forced_local = 1;
7415
7416 s->size += ARM_BX_VENEER_SIZE;
7417 globals->bx_glue_offset[reg] = globals->bx_glue_size | 2;
7418 globals->bx_glue_size += ARM_BX_VENEER_SIZE;
7419}
7420
7421
c7b8f16e
JB		 7422/* Add an entry to the code/data map for section SEC. */
7423
7424static void
7425elf32_arm_section_map_add (asection *sec, char type, bfd_vma vma)
7426{
7427 struct _arm_elf_section_data *sec_data = elf32_arm_section_data (sec);
7428 unsigned int newidx;
906e58ca 7429
c7b8f16e
JB		 7430 if (sec_data->map == NULL)
7431 {
21d799b5 7432 sec_data->map = (elf32_arm_section_map *)
99059e56 7433 bfd_malloc (sizeof (elf32_arm_section_map));
c7b8f16e
JB		 7434 sec_data->mapcount = 0;
7435 sec_data->mapsize = 1;
7436 }
906e58ca 7437
c7b8f16e 7438 newidx = sec_data->mapcount++;
906e58ca 7439
c7b8f16e
JB		 7440 if (sec_data->mapcount > sec_data->mapsize)
7441 {
7442 sec_data->mapsize *= 2;
21d799b5 7443 sec_data->map = (elf32_arm_section_map *)
99059e56
RM		 7444 bfd_realloc_or_free (sec_data->map, sec_data->mapsize
7445 * sizeof (elf32_arm_section_map));
515ef31d
NC		 7446 }
7447
7448 if (sec_data->map)
7449 {
7450 sec_data->map[newidx].vma = vma;
7451 sec_data->map[newidx].type = type;
c7b8f16e 7452 }
c7b8f16e
JB		 7453}
7454
7455
7456/* Record information about a VFP11 denorm-erratum veneer. Only ARM-mode
7457 veneers are handled for now. */
7458
7459static bfd_vma
7460record_vfp11_erratum_veneer (struct bfd_link_info *link_info,
99059e56
RM		 7461 elf32_vfp11_erratum_list *branch,
7462 bfd *branch_bfd,
7463 asection *branch_sec,
7464 unsigned int offset)
c7b8f16e
JB		 7465{
7466 asection *s;
7467 struct elf32_arm_link_hash_table *hash_table;
7468 char *tmp_name;
7469 struct elf_link_hash_entry *myh;
7470 struct bfd_link_hash_entry *bh;
7471 bfd_vma val;
7472 struct _arm_elf_section_data *sec_data;
c7b8f16e 7473 elf32_vfp11_erratum_list *newerr;
906e58ca 7474
c7b8f16e 7475 hash_table = elf32_arm_hash_table (link_info);
c7b8f16e
JB		 7476 BFD_ASSERT (hash_table != NULL);
7477 BFD_ASSERT (hash_table->bfd_of_glue_owner != NULL);
906e58ca 7478
3d4d4302 7479 s = bfd_get_linker_section
c7b8f16e 7480 (hash_table->bfd_of_glue_owner, VFP11_ERRATUM_VENEER_SECTION_NAME);
906e58ca 7481
c7b8f16e 7482 sec_data = elf32_arm_section_data (s);
906e58ca 7483
c7b8f16e 7484 BFD_ASSERT (s != NULL);
906e58ca 7485
21d799b5 7486 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen
99059e56 7487 (VFP11_ERRATUM_VENEER_ENTRY_NAME) + 10);
906e58ca 7488
c7b8f16e 7489 BFD_ASSERT (tmp_name);
906e58ca 7490
c7b8f16e
JB		 7491 sprintf (tmp_name, VFP11_ERRATUM_VENEER_ENTRY_NAME,
7492 hash_table->num_vfp11_fixes);
906e58ca 7493
c7b8f16e
JB		 7494 myh = elf_link_hash_lookup
7495 (&(hash_table)->root, tmp_name, FALSE, FALSE, FALSE);
906e58ca 7496
c7b8f16e 7497 BFD_ASSERT (myh == NULL);
906e58ca 7498
c7b8f16e
JB		 7499 bh = NULL;
7500 val = hash_table->vfp11_erratum_glue_size;
7501 _bfd_generic_link_add_one_symbol (link_info, hash_table->bfd_of_glue_owner,
99059e56
RM		 7502 tmp_name, BSF_FUNCTION | BSF_LOCAL, s, val,
7503 NULL, TRUE, FALSE, &bh);
c7b8f16e
JB		 7504
7505 myh = (struct elf_link_hash_entry *) bh;
7506 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
7507 myh->forced_local = 1;
7508
7509 /* Link veneer back to calling location. */
c7e2358a 7510 sec_data->erratumcount += 1;
21d799b5
NC		 7511 newerr = (elf32_vfp11_erratum_list *)
7512 bfd_zmalloc (sizeof (elf32_vfp11_erratum_list));
906e58ca 7513
c7b8f16e
JB		 7514 newerr->type = VFP11_ERRATUM_ARM_VENEER;
7515 newerr->vma = -1;
7516 newerr->u.v.branch = branch;
7517 newerr->u.v.id = hash_table->num_vfp11_fixes;
7518 branch->u.b.veneer = newerr;
7519
7520 newerr->next = sec_data->erratumlist;
7521 sec_data->erratumlist = newerr;
7522
7523 /* A symbol for the return from the veneer. */
7524 sprintf (tmp_name, VFP11_ERRATUM_VENEER_ENTRY_NAME "_r",
7525 hash_table->num_vfp11_fixes);
7526
7527 myh = elf_link_hash_lookup
7528 (&(hash_table)->root, tmp_name, FALSE, FALSE, FALSE);
906e58ca 7529
c7b8f16e
JB		 7530 if (myh != NULL)
7531 abort ();
7532
7533 bh = NULL;
7534 val = offset + 4;
7535 _bfd_generic_link_add_one_symbol (link_info, branch_bfd, tmp_name, BSF_LOCAL,
7536 branch_sec, val, NULL, TRUE, FALSE, &bh);
906e58ca 7537
c7b8f16e
JB		 7538 myh = (struct elf_link_hash_entry *) bh;
7539 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
7540 myh->forced_local = 1;
7541
7542 free (tmp_name);
906e58ca 7543
c7b8f16e
JB		 7544 /* Generate a mapping symbol for the veneer section, and explicitly add an
7545 entry for that symbol to the code/data map for the section. */
7546 if (hash_table->vfp11_erratum_glue_size == 0)
7547 {
7548 bh = NULL;
7549 /* FIXME: Creates an ARM symbol. Thumb mode will need attention if it
99059e56 7550 ever requires this erratum fix. */
c7b8f16e
JB		 7551 _bfd_generic_link_add_one_symbol (link_info,
7552 hash_table->bfd_of_glue_owner, "$a",
7553 BSF_LOCAL, s, 0, NULL,
99059e56 7554 TRUE, FALSE, &bh);
c7b8f16e
JB		 7555
7556 myh = (struct elf_link_hash_entry *) bh;
7557 myh->type = ELF_ST_INFO (STB_LOCAL, STT_NOTYPE);
7558 myh->forced_local = 1;
906e58ca 7559
c7b8f16e 7560 /* The elf32_arm_init_maps function only cares about symbols from input
99059e56
RM		 7561 BFDs. We must make a note of this generated mapping symbol
7562 ourselves so that code byteswapping works properly in
7563 elf32_arm_write_section. */
c7b8f16e
JB		 7564 elf32_arm_section_map_add (s, 'a', 0);
7565 }
906e58ca 7566
c7b8f16e
JB		 7567 s->size += VFP11_ERRATUM_VENEER_SIZE;
7568 hash_table->vfp11_erratum_glue_size += VFP11_ERRATUM_VENEER_SIZE;
7569 hash_table->num_vfp11_fixes++;
906e58ca 7570
c7b8f16e
JB		 7571 /* The offset of the veneer. */
7572 return val;
7573}
7574
a504d23a
LA		 7575/* Record information about a STM32L4XX STM erratum veneer. Only THUMB-mode
7576 veneers need to be handled because used only in Cortex-M. */
7577
7578static bfd_vma
7579record_stm32l4xx_erratum_veneer (struct bfd_link_info *link_info,
7580 elf32_stm32l4xx_erratum_list *branch,
7581 bfd *branch_bfd,
7582 asection *branch_sec,
7583 unsigned int offset,
7584 bfd_size_type veneer_size)
7585{
7586 asection *s;
7587 struct elf32_arm_link_hash_table *hash_table;
7588 char *tmp_name;
7589 struct elf_link_hash_entry *myh;
7590 struct bfd_link_hash_entry *bh;
7591 bfd_vma val;
7592 struct _arm_elf_section_data *sec_data;
7593 elf32_stm32l4xx_erratum_list *newerr;
7594
7595 hash_table = elf32_arm_hash_table (link_info);
7596 BFD_ASSERT (hash_table != NULL);
7597 BFD_ASSERT (hash_table->bfd_of_glue_owner != NULL);
7598
7599 s = bfd_get_linker_section
7600 (hash_table->bfd_of_glue_owner, STM32L4XX_ERRATUM_VENEER_SECTION_NAME);
7601
7602 BFD_ASSERT (s != NULL);
7603
7604 sec_data = elf32_arm_section_data (s);
7605
7606 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen
7607 (STM32L4XX_ERRATUM_VENEER_ENTRY_NAME) + 10);
7608
7609 BFD_ASSERT (tmp_name);
7610
7611 sprintf (tmp_name, STM32L4XX_ERRATUM_VENEER_ENTRY_NAME,
7612 hash_table->num_stm32l4xx_fixes);
7613
7614 myh = elf_link_hash_lookup
7615 (&(hash_table)->root, tmp_name, FALSE, FALSE, FALSE);
7616
7617 BFD_ASSERT (myh == NULL);
7618
7619 bh = NULL;
7620 val = hash_table->stm32l4xx_erratum_glue_size;
7621 _bfd_generic_link_add_one_symbol (link_info, hash_table->bfd_of_glue_owner,
7622 tmp_name, BSF_FUNCTION | BSF_LOCAL, s, val,
7623 NULL, TRUE, FALSE, &bh);
7624
7625 myh = (struct elf_link_hash_entry *) bh;
7626 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
7627 myh->forced_local = 1;
7628
7629 /* Link veneer back to calling location. */
7630 sec_data->stm32l4xx_erratumcount += 1;
7631 newerr = (elf32_stm32l4xx_erratum_list *)
7632 bfd_zmalloc (sizeof (elf32_stm32l4xx_erratum_list));
7633
7634 newerr->type = STM32L4XX_ERRATUM_VENEER;
7635 newerr->vma = -1;
7636 newerr->u.v.branch = branch;
7637 newerr->u.v.id = hash_table->num_stm32l4xx_fixes;
7638 branch->u.b.veneer = newerr;
7639
7640 newerr->next = sec_data->stm32l4xx_erratumlist;
7641 sec_data->stm32l4xx_erratumlist = newerr;
7642
7643 /* A symbol for the return from the veneer. */
7644 sprintf (tmp_name, STM32L4XX_ERRATUM_VENEER_ENTRY_NAME "_r",
7645 hash_table->num_stm32l4xx_fixes);
7646
7647 myh = elf_link_hash_lookup
7648 (&(hash_table)->root, tmp_name, FALSE, FALSE, FALSE);
7649
7650 if (myh != NULL)
7651 abort ();
7652
7653 bh = NULL;
7654 val = offset + 4;
7655 _bfd_generic_link_add_one_symbol (link_info, branch_bfd, tmp_name, BSF_LOCAL,
7656 branch_sec, val, NULL, TRUE, FALSE, &bh);
7657
7658 myh = (struct elf_link_hash_entry *) bh;
7659 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
7660 myh->forced_local = 1;
7661
7662 free (tmp_name);
7663
7664 /* Generate a mapping symbol for the veneer section, and explicitly add an
7665 entry for that symbol to the code/data map for the section. */
7666 if (hash_table->stm32l4xx_erratum_glue_size == 0)
7667 {
7668 bh = NULL;
7669 /* Creates a THUMB symbol since there is no other choice. */
7670 _bfd_generic_link_add_one_symbol (link_info,
7671 hash_table->bfd_of_glue_owner, "$t",
7672 BSF_LOCAL, s, 0, NULL,
7673 TRUE, FALSE, &bh);
7674
7675 myh = (struct elf_link_hash_entry *) bh;
7676 myh->type = ELF_ST_INFO (STB_LOCAL, STT_NOTYPE);
7677 myh->forced_local = 1;
7678
7679 /* The elf32_arm_init_maps function only cares about symbols from input
7680 BFDs. We must make a note of this generated mapping symbol
7681 ourselves so that code byteswapping works properly in
7682 elf32_arm_write_section. */
7683 elf32_arm_section_map_add (s, 't', 0);
7684 }
7685
7686 s->size += veneer_size;
7687 hash_table->stm32l4xx_erratum_glue_size += veneer_size;
7688 hash_table->num_stm32l4xx_fixes++;
7689
7690 /* The offset of the veneer. */
7691 return val;
7692}
7693
8029a119 7694#define ARM_GLUE_SECTION_FLAGS \
3e6b1042
DJ		 7695 (SEC_ALLOC | SEC_LOAD | SEC_HAS_CONTENTS | SEC_IN_MEMORY | SEC_CODE \
7696 | SEC_READONLY | SEC_LINKER_CREATED)
8029a119
NC		 7697
7698/* Create a fake section for use by the ARM backend of the linker. */
7699
7700static bfd_boolean
7701arm_make_glue_section (bfd * abfd, const char * name)
7702{
7703 asection * sec;
7704
3d4d4302 7705 sec = bfd_get_linker_section (abfd, name);
8029a119
NC		 7706 if (sec != NULL)
7707 /* Already made. */
7708 return TRUE;
7709
3d4d4302 7710 sec = bfd_make_section_anyway_with_flags (abfd, name, ARM_GLUE_SECTION_FLAGS);
8029a119
NC		 7711
7712 if (sec == NULL
fd361982 7713 || !bfd_set_section_alignment (sec, 2))
8029a119
NC		 7714 return FALSE;
7715
7716 /* Set the gc mark to prevent the section from being removed by garbage
7717 collection, despite the fact that no relocs refer to this section. */
7718 sec->gc_mark = 1;
7719
7720 return TRUE;
7721}
7722
1db37fe6
YG		 7723/* Set size of .plt entries. This function is called from the
7724 linker scripts in ld/emultempl/{armelf}.em. */
7725
7726void
7727bfd_elf32_arm_use_long_plt (void)
7728{
7729 elf32_arm_use_long_plt_entry = TRUE;
7730}
7731
8afb0e02
NC		 7732/* Add the glue sections to ABFD. This function is called from the
7733 linker scripts in ld/emultempl/{armelf}.em. */
9b485d32 7734
b34976b6 7735bfd_boolean
57e8b36a
NC		 7736bfd_elf32_arm_add_glue_sections_to_bfd (bfd *abfd,
7737 struct bfd_link_info *info)
252b5132 7738{
a504d23a
LA		 7739 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (info);
7740 bfd_boolean dostm32l4xx = globals
7741 && globals->stm32l4xx_fix != BFD_ARM_STM32L4XX_FIX_NONE;
7742 bfd_boolean addglue;
7743
8afb0e02
NC		 7744 /* If we are only performing a partial
7745 link do not bother adding the glue. */
0e1862bb 7746 if (bfd_link_relocatable (info))
b34976b6 7747 return TRUE;
252b5132 7748
a504d23a 7749 addglue = arm_make_glue_section (abfd, ARM2THUMB_GLUE_SECTION_NAME)
8029a119
NC		 7750 && arm_make_glue_section (abfd, THUMB2ARM_GLUE_SECTION_NAME)
7751 && arm_make_glue_section (abfd, VFP11_ERRATUM_VENEER_SECTION_NAME)
7752 && arm_make_glue_section (abfd, ARM_BX_GLUE_SECTION_NAME);
a504d23a
LA		 7753
7754 if (!dostm32l4xx)
7755 return addglue;
7756
7757 return addglue
7758 && arm_make_glue_section (abfd, STM32L4XX_ERRATUM_VENEER_SECTION_NAME);
8afb0e02
NC		 7759}
7760
daa4adae
TP		 7761/* Mark output sections of veneers needing a dedicated one with SEC_KEEP. This
7762 ensures they are not marked for deletion by
7763 strip_excluded_output_sections () when veneers are going to be created
7764 later. Not doing so would trigger assert on empty section size in
7765 lang_size_sections_1 (). */
7766
7767void
7768bfd_elf32_arm_keep_private_stub_output_sections (struct bfd_link_info *info)
7769{
7770 enum elf32_arm_stub_type stub_type;
7771
7772 /* If we are only performing a partial
7773 link do not bother adding the glue. */
7774 if (bfd_link_relocatable (info))
7775 return;
7776
7777 for (stub_type = arm_stub_none + 1; stub_type < max_stub_type; stub_type++)
7778 {
7779 asection *out_sec;
7780 const char *out_sec_name;
7781
7782 if (!arm_dedicated_stub_output_section_required (stub_type))
7783 continue;
7784
7785 out_sec_name = arm_dedicated_stub_output_section_name (stub_type);
7786 out_sec = bfd_get_section_by_name (info->output_bfd, out_sec_name);
7787 if (out_sec != NULL)
7788 out_sec->flags |= SEC_KEEP;
7789 }
7790}
7791
8afb0e02
NC		 7792/* Select a BFD to be used to hold the sections used by the glue code.
7793 This function is called from the linker scripts in ld/emultempl/
8029a119 7794 {armelf/pe}.em. */
8afb0e02 7795
b34976b6 7796bfd_boolean
57e8b36a 7797bfd_elf32_arm_get_bfd_for_interworking (bfd *abfd, struct bfd_link_info *info)
8afb0e02
NC		 7798{
7799 struct elf32_arm_link_hash_table *globals;
7800
7801 /* If we are only performing a partial link
7802 do not bother getting a bfd to hold the glue. */
0e1862bb 7803 if (bfd_link_relocatable (info))
b34976b6 7804 return TRUE;
8afb0e02 7805
b7693d02
DJ		 7806 /* Make sure we don't attach the glue sections to a dynamic object. */
7807 BFD_ASSERT (!(abfd->flags & DYNAMIC));
7808
8afb0e02 7809 globals = elf32_arm_hash_table (info);
8afb0e02
NC		 7810 BFD_ASSERT (globals != NULL);
7811
7812 if (globals->bfd_of_glue_owner != NULL)
b34976b6 7813 return TRUE;
8afb0e02 7814
252b5132
RH		 7815 /* Save the bfd for later use. */
7816 globals->bfd_of_glue_owner = abfd;
cedb70c5 7817
b34976b6 7818 return TRUE;
252b5132
RH		 7819}
7820
906e58ca
NC		 7821static void
7822check_use_blx (struct elf32_arm_link_hash_table *globals)
39b41c9c 7823{
2de70689
MGD		 7824 int cpu_arch;
7825
b38cadfb 7826 cpu_arch = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC,
2de70689
MGD		 7827 Tag_CPU_arch);
7828
7829 if (globals->fix_arm1176)
7830 {
7831 if (cpu_arch == TAG_CPU_ARCH_V6T2 || cpu_arch > TAG_CPU_ARCH_V6K)
7832 globals->use_blx = 1;
7833 }
7834 else
7835 {
7836 if (cpu_arch > TAG_CPU_ARCH_V4T)
7837 globals->use_blx = 1;
7838 }
39b41c9c
PB		 7839}
7840
b34976b6 7841bfd_boolean
57e8b36a 7842bfd_elf32_arm_process_before_allocation (bfd *abfd,
d504ffc8 7843 struct bfd_link_info *link_info)
252b5132
RH		 7844{
7845 Elf_Internal_Shdr *symtab_hdr;
6cdc0ccc 7846 Elf_Internal_Rela *internal_relocs = NULL;
252b5132
RH		 7847 Elf_Internal_Rela *irel, *irelend;
7848 bfd_byte *contents = NULL;
252b5132
RH		 7849
7850 asection *sec;
7851 struct elf32_arm_link_hash_table *globals;
7852
7853 /* If we are only performing a partial link do not bother
7854 to construct any glue. */
0e1862bb 7855 if (bfd_link_relocatable (link_info))
b34976b6 7856 return TRUE;
252b5132 7857
39ce1a6a
NC		 7858 /* Here we have a bfd that is to be included on the link. We have a
7859 hook to do reloc rummaging, before section sizes are nailed down. */
252b5132 7860 globals = elf32_arm_hash_table (link_info);
252b5132 7861 BFD_ASSERT (globals != NULL);
39ce1a6a
NC		 7862
7863 check_use_blx (globals);
252b5132 7864
d504ffc8 7865 if (globals->byteswap_code && !bfd_big_endian (abfd))
e489d0ae 7866 {
90b6238f 7867 _bfd_error_handler (_("%pB: BE8 images only valid in big-endian mode"),
d003868e 7868 abfd);
e489d0ae
PB		 7869 return FALSE;
7870 }
f21f3fe0 7871
39ce1a6a
NC		 7872 /* PR 5398: If we have not decided to include any loadable sections in
7873 the output then we will not have a glue owner bfd. This is OK, it
7874 just means that there is nothing else for us to do here. */
7875 if (globals->bfd_of_glue_owner == NULL)
7876 return TRUE;
7877
252b5132
RH		 7878 /* Rummage around all the relocs and map the glue vectors. */
7879 sec = abfd->sections;
7880
7881 if (sec == NULL)
b34976b6 7882 return TRUE;
252b5132
RH		 7883
7884 for (; sec != NULL; sec = sec->next)
7885 {
7886 if (sec->reloc_count == 0)
7887 continue;
7888
2f475487
AM		 7889 if ((sec->flags & SEC_EXCLUDE) != 0)
7890 continue;
7891
0ffa91dd 7892 symtab_hdr = & elf_symtab_hdr (abfd);
252b5132 7893
9b485d32 7894 /* Load the relocs. */
6cdc0ccc 7895 internal_relocs
906e58ca 7896 = _bfd_elf_link_read_relocs (abfd, sec, NULL, NULL, FALSE);
252b5132 7897
6cdc0ccc
AM		 7898 if (internal_relocs == NULL)
7899 goto error_return;
252b5132 7900
6cdc0ccc
AM		 7901 irelend = internal_relocs + sec->reloc_count;
7902 for (irel = internal_relocs; irel < irelend; irel++)
252b5132
RH		 7903 {
7904 long r_type;
7905 unsigned long r_index;
252b5132
RH		 7906
7907 struct elf_link_hash_entry *h;
7908
7909 r_type = ELF32_R_TYPE (irel->r_info);
7910 r_index = ELF32_R_SYM (irel->r_info);
7911
9b485d32 7912 /* These are the only relocation types we care about. */
ba96a88f 7913 if ( r_type != R_ARM_PC24
845b51d6 7914 && (r_type != R_ARM_V4BX || globals->fix_v4bx < 2))
252b5132
RH		 7915 continue;
7916
7917 /* Get the section contents if we haven't done so already. */
7918 if (contents == NULL)
7919 {
7920 /* Get cached copy if it exists. */
7921 if (elf_section_data (sec)->this_hdr.contents != NULL)
7922 contents = elf_section_data (sec)->this_hdr.contents;
7923 else
7924 {
7925 /* Go get them off disk. */
57e8b36a 7926 if (! bfd_malloc_and_get_section (abfd, sec, &contents))
252b5132
RH		 7927 goto error_return;
7928 }
7929 }
7930
845b51d6
PB		 7931 if (r_type == R_ARM_V4BX)
7932 {
7933 int reg;
7934
7935 reg = bfd_get_32 (abfd, contents + irel->r_offset) & 0xf;
7936 record_arm_bx_glue (link_info, reg);
7937 continue;
7938 }
7939
a7c10850 7940 /* If the relocation is not against a symbol it cannot concern us. */
252b5132
RH		 7941 h = NULL;
7942
9b485d32 7943 /* We don't care about local symbols. */
252b5132
RH		 7944 if (r_index < symtab_hdr->sh_info)
7945 continue;
7946
9b485d32 7947 /* This is an external symbol. */
252b5132
RH		 7948 r_index -= symtab_hdr->sh_info;
7949 h = (struct elf_link_hash_entry *)
7950 elf_sym_hashes (abfd)[r_index];
7951
7952 /* If the relocation is against a static symbol it must be within
7953 the current section and so cannot be a cross ARM/Thumb relocation. */
7954 if (h == NULL)
7955 continue;
7956
d504ffc8
DJ		 7957 /* If the call will go through a PLT entry then we do not need
7958 glue. */
362d30a1 7959 if (globals->root.splt != NULL && h->plt.offset != (bfd_vma) -1)
b7693d02
DJ		 7960 continue;
7961
252b5132
RH		 7962 switch (r_type)
7963 {
7964 case R_ARM_PC24:
7965 /* This one is a call from arm code. We need to look up
99059e56
RM		 7966 the target of the call. If it is a thumb target, we
7967 insert glue. */
39d911fc
TP		 7968 if (ARM_GET_SYM_BRANCH_TYPE (h->target_internal)
7969 == ST_BRANCH_TO_THUMB)
252b5132
RH		 7970 record_arm_to_thumb_glue (link_info, h);
7971 break;
7972
252b5132 7973 default:
c6596c5e 7974 abort ();
252b5132
RH		 7975 }
7976 }
6cdc0ccc
AM		 7977
7978 if (contents != NULL
7979 && elf_section_data (sec)->this_hdr.contents != contents)
7980 free (contents);
7981 contents = NULL;
7982
7983 if (internal_relocs != NULL
7984 && elf_section_data (sec)->relocs != internal_relocs)
7985 free (internal_relocs);
7986 internal_relocs = NULL;
252b5132
RH		 7987 }
7988
b34976b6 7989 return TRUE;
9a5aca8c 7990
252b5132 7991error_return:
6cdc0ccc
AM		 7992 if (contents != NULL
7993 && elf_section_data (sec)->this_hdr.contents != contents)
7994 free (contents);
7995 if (internal_relocs != NULL
7996 && elf_section_data (sec)->relocs != internal_relocs)
7997 free (internal_relocs);
9a5aca8c 7998
b34976b6 7999 return FALSE;
252b5132 8000}
7e392df6 8001#endif
252b5132 8002
eb043451 8003
c7b8f16e
JB		 8004/* Initialise maps of ARM/Thumb/data for input BFDs. */
8005
8006void
8007bfd_elf32_arm_init_maps (bfd *abfd)
8008{
8009 Elf_Internal_Sym *isymbuf;
8010 Elf_Internal_Shdr *hdr;
8011 unsigned int i, localsyms;
8012
af1f4419
NC		 8013 /* PR 7093: Make sure that we are dealing with an arm elf binary. */
8014 if (! is_arm_elf (abfd))
8015 return;
8016
c7b8f16e
JB		 8017 if ((abfd->flags & DYNAMIC) != 0)
8018 return;
8019
0ffa91dd 8020 hdr = & elf_symtab_hdr (abfd);
c7b8f16e
JB		 8021 localsyms = hdr->sh_info;
8022
8023 /* Obtain a buffer full of symbols for this BFD. The hdr->sh_info field
8024 should contain the number of local symbols, which should come before any
8025 global symbols. Mapping symbols are always local. */
8026 isymbuf = bfd_elf_get_elf_syms (abfd, hdr, localsyms, 0, NULL, NULL,
8027 NULL);
8028
8029 /* No internal symbols read? Skip this BFD. */
8030 if (isymbuf == NULL)
8031 return;
8032
8033 for (i = 0; i < localsyms; i++)
8034 {
8035 Elf_Internal_Sym *isym = &isymbuf[i];
8036 asection *sec = bfd_section_from_elf_index (abfd, isym->st_shndx);
8037 const char *name;
906e58ca 8038
c7b8f16e 8039 if (sec != NULL
99059e56
RM		 8040 && ELF_ST_BIND (isym->st_info) == STB_LOCAL)
8041 {
8042 name = bfd_elf_string_from_elf_section (abfd,
8043 hdr->sh_link, isym->st_name);
906e58ca 8044
99059e56 8045 if (bfd_is_arm_special_symbol_name (name,
c7b8f16e 8046 BFD_ARM_SPECIAL_SYM_TYPE_MAP))
99059e56
RM		 8047 elf32_arm_section_map_add (sec, name[1], isym->st_value);
8048 }
c7b8f16e
JB		 8049 }
8050}
8051
8052
48229727
JB		 8053/* Auto-select enabling of Cortex-A8 erratum fix if the user didn't explicitly
8054 say what they wanted. */
8055
8056void
8057bfd_elf32_arm_set_cortex_a8_fix (bfd *obfd, struct bfd_link_info *link_info)
8058{
8059 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (link_info);
8060 obj_attribute *out_attr = elf_known_obj_attributes_proc (obfd);
8061
4dfe6ac6
NC		 8062 if (globals == NULL)
8063 return;
8064
48229727
JB		 8065 if (globals->fix_cortex_a8 == -1)
8066 {
8067 /* Turn on Cortex-A8 erratum workaround for ARMv7-A. */
8068 if (out_attr[Tag_CPU_arch].i == TAG_CPU_ARCH_V7
8069 && (out_attr[Tag_CPU_arch_profile].i == 'A'
8070 || out_attr[Tag_CPU_arch_profile].i == 0))
8071 globals->fix_cortex_a8 = 1;
8072 else
8073 globals->fix_cortex_a8 = 0;
8074 }
8075}
8076
8077
c7b8f16e
JB		 8078void
8079bfd_elf32_arm_set_vfp11_fix (bfd *obfd, struct bfd_link_info *link_info)
8080{
8081 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (link_info);
104d59d1 8082 obj_attribute *out_attr = elf_known_obj_attributes_proc (obfd);
906e58ca 8083
4dfe6ac6
NC		 8084 if (globals == NULL)
8085 return;
c7b8f16e
JB		 8086 /* We assume that ARMv7+ does not need the VFP11 denorm erratum fix. */
8087 if (out_attr[Tag_CPU_arch].i >= TAG_CPU_ARCH_V7)
8088 {
8089 switch (globals->vfp11_fix)
99059e56
RM		 8090 {
8091 case BFD_ARM_VFP11_FIX_DEFAULT:
8092 case BFD_ARM_VFP11_FIX_NONE:
8093 globals->vfp11_fix = BFD_ARM_VFP11_FIX_NONE;
8094 break;
8095
8096 default:
8097 /* Give a warning, but do as the user requests anyway. */
871b3ab2 8098 _bfd_error_handler (_("%pB: warning: selected VFP11 erratum "
99059e56
RM		 8099 "workaround is not necessary for target architecture"), obfd);
8100 }
c7b8f16e
JB		 8101 }
8102 else if (globals->vfp11_fix == BFD_ARM_VFP11_FIX_DEFAULT)
8103 /* For earlier architectures, we might need the workaround, but do not
8104 enable it by default. If users is running with broken hardware, they
8105 must enable the erratum fix explicitly. */
8106 globals->vfp11_fix = BFD_ARM_VFP11_FIX_NONE;
8107}
8108
a504d23a
LA		 8109void
8110bfd_elf32_arm_set_stm32l4xx_fix (bfd *obfd, struct bfd_link_info *link_info)
8111{
8112 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (link_info);
8113 obj_attribute *out_attr = elf_known_obj_attributes_proc (obfd);
8114
8115 if (globals == NULL)
8116 return;
8117
8118 /* We assume only Cortex-M4 may require the fix. */
8119 if (out_attr[Tag_CPU_arch].i != TAG_CPU_ARCH_V7E_M
8120 || out_attr[Tag_CPU_arch_profile].i != 'M')
8121 {
8122 if (globals->stm32l4xx_fix != BFD_ARM_STM32L4XX_FIX_NONE)
8123 /* Give a warning, but do as the user requests anyway. */
4eca0228 8124 _bfd_error_handler
871b3ab2 8125 (_("%pB: warning: selected STM32L4XX erratum "
a504d23a
LA		 8126 "workaround is not necessary for target architecture"), obfd);
8127 }
8128}
c7b8f16e 8129
906e58ca
NC		 8130enum bfd_arm_vfp11_pipe
8131{
c7b8f16e
JB		 8132 VFP11_FMAC,
8133 VFP11_LS,
8134 VFP11_DS,
8135 VFP11_BAD
8136};
8137
8138/* Return a VFP register number. This is encoded as RX:X for single-precision
8139 registers, or X:RX for double-precision registers, where RX is the group of
8140 four bits in the instruction encoding and X is the single extension bit.
8141 RX and X fields are specified using their lowest (starting) bit. The return
8142 value is:
8143
8144 0...31: single-precision registers s0...s31
8145 32...63: double-precision registers d0...d31.
906e58ca 8146
c7b8f16e
JB		 8147 Although X should be zero for VFP11 (encoding d0...d15 only), we might
8148 encounter VFP3 instructions, so we allow the full range for DP registers. */
906e58ca 8149
c7b8f16e
JB		 8150static unsigned int
8151bfd_arm_vfp11_regno (unsigned int insn, bfd_boolean is_double, unsigned int rx,
99059e56 8152 unsigned int x)
c7b8f16e
JB		 8153{
8154 if (is_double)
8155 return (((insn >> rx) & 0xf) | (((insn >> x) & 1) << 4)) + 32;
8156 else
8157 return (((insn >> rx) & 0xf) << 1) | ((insn >> x) & 1);
8158}
8159
8160/* Set bits in *WMASK according to a register number REG as encoded by
8161 bfd_arm_vfp11_regno(). Ignore d16-d31. */
8162
8163static void
8164bfd_arm_vfp11_write_mask (unsigned int *wmask, unsigned int reg)
8165{
8166 if (reg < 32)
8167 *wmask |= 1 << reg;
8168 else if (reg < 48)
8169 *wmask |= 3 << ((reg - 32) * 2);
8170}
8171
8172/* Return TRUE if WMASK overwrites anything in REGS. */
8173
8174static bfd_boolean
8175bfd_arm_vfp11_antidependency (unsigned int wmask, int *regs, int numregs)
8176{
8177 int i;
906e58ca 8178
c7b8f16e
JB		 8179 for (i = 0; i < numregs; i++)
8180 {
8181 unsigned int reg = regs[i];
8182
8183 if (reg < 32 && (wmask & (1 << reg)) != 0)
99059e56 8184 return TRUE;
906e58ca 8185
c7b8f16e
JB		 8186 reg -= 32;
8187
8188 if (reg >= 16)
99059e56 8189 continue;
906e58ca 8190
c7b8f16e 8191 if ((wmask & (3 << (reg * 2))) != 0)
99059e56 8192 return TRUE;
c7b8f16e 8193 }
906e58ca 8194
c7b8f16e
JB		 8195 return FALSE;
8196}
8197
8198/* In this function, we're interested in two things: finding input registers
8199 for VFP data-processing instructions, and finding the set of registers which
8200 arbitrary VFP instructions may write to. We use a 32-bit unsigned int to
8201 hold the written set, so FLDM etc. are easy to deal with (we're only
8202 interested in 32 SP registers or 16 dp registers, due to the VFP version
8203 implemented by the chip in question). DP registers are marked by setting
8204 both SP registers in the write mask). */
8205
8206static enum bfd_arm_vfp11_pipe
8207bfd_arm_vfp11_insn_decode (unsigned int insn, unsigned int *destmask, int *regs,
99059e56 8208 int *numregs)
c7b8f16e 8209{
91d6fa6a 8210 enum bfd_arm_vfp11_pipe vpipe = VFP11_BAD;
c7b8f16e
JB		 8211 bfd_boolean is_double = ((insn & 0xf00) == 0xb00) ? 1 : 0;
8212
8213 if ((insn & 0x0f000e10) == 0x0e000a00) /* A data-processing insn. */
8214 {
8215 unsigned int pqrs;
8216 unsigned int fd = bfd_arm_vfp11_regno (insn, is_double, 12, 22);
8217 unsigned int fm = bfd_arm_vfp11_regno (insn, is_double, 0, 5);
8218
8219 pqrs = ((insn & 0x00800000) >> 20)
99059e56
RM		 8220 | ((insn & 0x00300000) >> 19)
8221 | ((insn & 0x00000040) >> 6);
c7b8f16e
JB		 8222
8223 switch (pqrs)
99059e56
RM		 8224 {
8225 case 0: /* fmac[sd]. */
8226 case 1: /* fnmac[sd]. */
8227 case 2: /* fmsc[sd]. */
8228 case 3: /* fnmsc[sd]. */
8229 vpipe = VFP11_FMAC;
8230 bfd_arm_vfp11_write_mask (destmask, fd);
8231 regs[0] = fd;
8232 regs[1] = bfd_arm_vfp11_regno (insn, is_double, 16, 7); /* Fn. */
8233 regs[2] = fm;
8234 *numregs = 3;
8235 break;
8236
8237 case 4: /* fmul[sd]. */
8238 case 5: /* fnmul[sd]. */
8239 case 6: /* fadd[sd]. */
8240 case 7: /* fsub[sd]. */
8241 vpipe = VFP11_FMAC;
8242 goto vfp_binop;
8243
8244 case 8: /* fdiv[sd]. */
8245 vpipe = VFP11_DS;
8246 vfp_binop:
8247 bfd_arm_vfp11_write_mask (destmask, fd);
8248 regs[0] = bfd_arm_vfp11_regno (insn, is_double, 16, 7); /* Fn. */
8249 regs[1] = fm;
8250 *numregs = 2;
8251 break;
8252
8253 case 15: /* extended opcode. */
8254 {
8255 unsigned int extn = ((insn >> 15) & 0x1e)
8256 | ((insn >> 7) & 1);
8257
8258 switch (extn)
8259 {
8260 case 0: /* fcpy[sd]. */
8261 case 1: /* fabs[sd]. */
8262 case 2: /* fneg[sd]. */
8263 case 8: /* fcmp[sd]. */
8264 case 9: /* fcmpe[sd]. */
8265 case 10: /* fcmpz[sd]. */
8266 case 11: /* fcmpez[sd]. */
8267 case 16: /* fuito[sd]. */
8268 case 17: /* fsito[sd]. */
8269 case 24: /* ftoui[sd]. */
8270 case 25: /* ftouiz[sd]. */
8271 case 26: /* ftosi[sd]. */
8272 case 27: /* ftosiz[sd]. */
8273 /* These instructions will not bounce due to underflow. */
8274 *numregs = 0;
8275 vpipe = VFP11_FMAC;
8276 break;
8277
8278 case 3: /* fsqrt[sd]. */
8279 /* fsqrt cannot underflow, but it can (perhaps) overwrite
8280 registers to cause the erratum in previous instructions. */
8281 bfd_arm_vfp11_write_mask (destmask, fd);
8282 vpipe = VFP11_DS;
8283 break;
8284
8285 case 15: /* fcvt{ds,sd}. */
8286 {
8287 int rnum = 0;
8288
8289 bfd_arm_vfp11_write_mask (destmask, fd);
c7b8f16e
JB		 8290
8291 /* Only FCVTSD can underflow. */
99059e56
RM		 8292 if ((insn & 0x100) != 0)
8293 regs[rnum++] = fm;
c7b8f16e 8294
99059e56 8295 *numregs = rnum;
c7b8f16e 8296
99059e56
RM		 8297 vpipe = VFP11_FMAC;
8298 }
8299 break;
c7b8f16e 8300
99059e56
RM		 8301 default:
8302 return VFP11_BAD;
8303 }
8304 }
8305 break;
c7b8f16e 8306
99059e56
RM		 8307 default:
8308 return VFP11_BAD;
8309 }
c7b8f16e
JB		 8310 }
8311 /* Two-register transfer. */
8312 else if ((insn & 0x0fe00ed0) == 0x0c400a10)
8313 {
8314 unsigned int fm = bfd_arm_vfp11_regno (insn, is_double, 0, 5);
906e58ca 8315
c7b8f16e
JB		 8316 if ((insn & 0x100000) == 0)
8317 {
99059e56
RM		 8318 if (is_double)
8319 bfd_arm_vfp11_write_mask (destmask, fm);
8320 else
8321 {
8322 bfd_arm_vfp11_write_mask (destmask, fm);
8323 bfd_arm_vfp11_write_mask (destmask, fm + 1);
8324 }
c7b8f16e
JB		 8325 }
8326
91d6fa6a 8327 vpipe = VFP11_LS;
c7b8f16e
JB		 8328 }
8329 else if ((insn & 0x0e100e00) == 0x0c100a00) /* A load insn. */
8330 {
8331 int fd = bfd_arm_vfp11_regno (insn, is_double, 12, 22);
8332 unsigned int puw = ((insn >> 21) & 0x1) | (((insn >> 23) & 3) << 1);
906e58ca 8333
c7b8f16e 8334 switch (puw)
99059e56
RM		 8335 {
8336 case 0: /* Two-reg transfer. We should catch these above. */
8337 abort ();
906e58ca 8338
99059e56
RM		 8339 case 2: /* fldm[sdx]. */
8340 case 3:
8341 case 5:
8342 {
8343 unsigned int i, offset = insn & 0xff;
c7b8f16e 8344
99059e56
RM		 8345 if (is_double)
8346 offset >>= 1;
c7b8f16e 8347
99059e56
RM		 8348 for (i = fd; i < fd + offset; i++)
8349 bfd_arm_vfp11_write_mask (destmask, i);
8350 }
8351 break;
906e58ca 8352
99059e56
RM		 8353 case 4: /* fld[sd]. */
8354 case 6:
8355 bfd_arm_vfp11_write_mask (destmask, fd);
8356 break;
906e58ca 8357
99059e56
RM		 8358 default:
8359 return VFP11_BAD;
8360 }
c7b8f16e 8361
91d6fa6a 8362 vpipe = VFP11_LS;
c7b8f16e
JB		 8363 }
8364 /* Single-register transfer. Note L==0. */
8365 else if ((insn & 0x0f100e10) == 0x0e000a10)
8366 {
8367 unsigned int opcode = (insn >> 21) & 7;
8368 unsigned int fn = bfd_arm_vfp11_regno (insn, is_double, 16, 7);
8369
8370 switch (opcode)
99059e56
RM		 8371 {
8372 case 0: /* fmsr/fmdlr. */
8373 case 1: /* fmdhr. */
8374 /* Mark fmdhr and fmdlr as writing to the whole of the DP
8375 destination register. I don't know if this is exactly right,
8376 but it is the conservative choice. */
8377 bfd_arm_vfp11_write_mask (destmask, fn);
8378 break;
8379
8380 case 7: /* fmxr. */
8381 break;
8382 }
c7b8f16e 8383
91d6fa6a 8384 vpipe = VFP11_LS;
c7b8f16e
JB		 8385 }
8386
91d6fa6a 8387 return vpipe;
c7b8f16e
JB		 8388}
8389
8390
8391static int elf32_arm_compare_mapping (const void * a, const void * b);
8392
8393
8394/* Look for potentially-troublesome code sequences which might trigger the
8395 VFP11 denormal/antidependency erratum. See, e.g., the ARM1136 errata sheet
8396 (available from ARM) for details of the erratum. A short version is
8397 described in ld.texinfo. */
8398
8399bfd_boolean
8400bfd_elf32_arm_vfp11_erratum_scan (bfd *abfd, struct bfd_link_info *link_info)
8401{
8402 asection *sec;
8403 bfd_byte *contents = NULL;
8404 int state = 0;
8405 int regs[3], numregs = 0;
8406 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (link_info);
8407 int use_vector = (globals->vfp11_fix == BFD_ARM_VFP11_FIX_VECTOR);
906e58ca 8408
4dfe6ac6
NC		 8409 if (globals == NULL)
8410 return FALSE;
8411
c7b8f16e
JB		 8412 /* We use a simple FSM to match troublesome VFP11 instruction sequences.
8413 The states transition as follows:
906e58ca 8414
c7b8f16e 8415 0 -> 1 (vector) or 0 -> 2 (scalar)
99059e56
RM		 8416 A VFP FMAC-pipeline instruction has been seen. Fill
8417 regs[0]..regs[numregs-1] with its input operands. Remember this
8418 instruction in 'first_fmac'.
c7b8f16e
JB		 8419
8420 1 -> 2
99059e56
RM		 8421 Any instruction, except for a VFP instruction which overwrites
8422 regs[*].
906e58ca 8423
c7b8f16e
JB		 8424 1 -> 3 [ -> 0 ] or
8425 2 -> 3 [ -> 0 ]
99059e56
RM		 8426 A VFP instruction has been seen which overwrites any of regs[*].
8427 We must make a veneer! Reset state to 0 before examining next
8428 instruction.
906e58ca 8429
c7b8f16e 8430 2 -> 0
99059e56
RM		 8431 If we fail to match anything in state 2, reset to state 0 and reset
8432 the instruction pointer to the instruction after 'first_fmac'.
c7b8f16e
JB		 8433
8434 If the VFP11 vector mode is in use, there must be at least two unrelated
8435 instructions between anti-dependent VFP11 instructions to properly avoid
906e58ca 8436 triggering the erratum, hence the use of the extra state 1. */
c7b8f16e
JB		 8437
8438 /* If we are only performing a partial link do not bother
8439 to construct any glue. */
0e1862bb 8440 if (bfd_link_relocatable (link_info))
c7b8f16e
JB		 8441 return TRUE;
8442
0ffa91dd
NC		 8443 /* Skip if this bfd does not correspond to an ELF image. */
8444 if (! is_arm_elf (abfd))
8445 return TRUE;
906e58ca 8446
c7b8f16e
JB		 8447 /* We should have chosen a fix type by the time we get here. */
8448 BFD_ASSERT (globals->vfp11_fix != BFD_ARM_VFP11_FIX_DEFAULT);
8449
8450 if (globals->vfp11_fix == BFD_ARM_VFP11_FIX_NONE)
8451 return TRUE;
2e6030b9 8452
33a7ffc2
JM		 8453 /* Skip this BFD if it corresponds to an executable or dynamic object. */
8454 if ((abfd->flags & (EXEC_P | DYNAMIC)) != 0)
8455 return TRUE;
8456
c7b8f16e
JB		 8457 for (sec = abfd->sections; sec != NULL; sec = sec->next)
8458 {
8459 unsigned int i, span, first_fmac = 0, veneer_of_insn = 0;
8460 struct _arm_elf_section_data *sec_data;
8461
8462 /* If we don't have executable progbits, we're not interested in this
99059e56 8463 section. Also skip if section is to be excluded. */
c7b8f16e 8464 if (elf_section_type (sec) != SHT_PROGBITS
99059e56
RM		 8465 || (elf_section_flags (sec) & SHF_EXECINSTR) == 0
8466 || (sec->flags & SEC_EXCLUDE) != 0
dbaa2011 8467 || sec->sec_info_type == SEC_INFO_TYPE_JUST_SYMS
33a7ffc2 8468 || sec->output_section == bfd_abs_section_ptr
99059e56
RM		 8469 || strcmp (sec->name, VFP11_ERRATUM_VENEER_SECTION_NAME) == 0)
8470 continue;
c7b8f16e
JB		 8471
8472 sec_data = elf32_arm_section_data (sec);
906e58ca 8473
c7b8f16e 8474 if (sec_data->mapcount == 0)
99059e56 8475 continue;
906e58ca 8476
c7b8f16e
JB		 8477 if (elf_section_data (sec)->this_hdr.contents != NULL)
8478 contents = elf_section_data (sec)->this_hdr.contents;
8479 else if (! bfd_malloc_and_get_section (abfd, sec, &contents))
8480 goto error_return;
8481
8482 qsort (sec_data->map, sec_data->mapcount, sizeof (elf32_arm_section_map),
8483 elf32_arm_compare_mapping);
8484
8485 for (span = 0; span < sec_data->mapcount; span++)
99059e56
RM		 8486 {
8487 unsigned int span_start = sec_data->map[span].vma;
8488 unsigned int span_end = (span == sec_data->mapcount - 1)
c7b8f16e 8489 ? sec->size : sec_data->map[span + 1].vma;
99059e56
RM		 8490 char span_type = sec_data->map[span].type;
8491
8492 /* FIXME: Only ARM mode is supported at present. We may need to
8493 support Thumb-2 mode also at some point. */
8494 if (span_type != 'a')
8495 continue;
8496
8497 for (i = span_start; i < span_end;)
8498 {
8499 unsigned int next_i = i + 4;
8500 unsigned int insn = bfd_big_endian (abfd)
8501 ? (contents[i] << 24)
8502 | (contents[i + 1] << 16)
8503 | (contents[i + 2] << 8)
8504 | contents[i + 3]
8505 : (contents[i + 3] << 24)
8506 | (contents[i + 2] << 16)
8507 | (contents[i + 1] << 8)
8508 | contents[i];
8509 unsigned int writemask = 0;
8510 enum bfd_arm_vfp11_pipe vpipe;
8511
8512 switch (state)
8513 {
8514 case 0:
8515 vpipe = bfd_arm_vfp11_insn_decode (insn, &writemask, regs,
8516 &numregs);
8517 /* I'm assuming the VFP11 erratum can trigger with denorm
8518 operands on either the FMAC or the DS pipeline. This might
8519 lead to slightly overenthusiastic veneer insertion. */
8520 if (vpipe == VFP11_FMAC || vpipe == VFP11_DS)
8521 {
8522 state = use_vector ? 1 : 2;
8523 first_fmac = i;
8524 veneer_of_insn = insn;
8525 }
8526 break;
8527
8528 case 1:
8529 {
8530 int other_regs[3], other_numregs;
8531 vpipe = bfd_arm_vfp11_insn_decode (insn, &writemask,
c7b8f16e 8532 other_regs,
99059e56
RM		 8533 &other_numregs);
8534 if (vpipe != VFP11_BAD
8535 && bfd_arm_vfp11_antidependency (writemask, regs,
c7b8f16e 8536 numregs))
99059e56
RM		 8537 state = 3;
8538 else
8539 state = 2;
8540 }
8541 break;
8542
8543 case 2:
8544 {
8545 int other_regs[3], other_numregs;
8546 vpipe = bfd_arm_vfp11_insn_decode (insn, &writemask,
c7b8f16e 8547 other_regs,
99059e56
RM		 8548 &other_numregs);
8549 if (vpipe != VFP11_BAD
8550 && bfd_arm_vfp11_antidependency (writemask, regs,
c7b8f16e 8551 numregs))
99059e56
RM		 8552 state = 3;
8553 else
8554 {
8555 state = 0;
8556 next_i = first_fmac + 4;
8557 }
8558 }
8559 break;
8560
8561 case 3:
8562 abort (); /* Should be unreachable. */
8563 }
8564
8565 if (state == 3)
8566 {
8567 elf32_vfp11_erratum_list *newerr =(elf32_vfp11_erratum_list *)
8568 bfd_zmalloc (sizeof (elf32_vfp11_erratum_list));
8569
8570 elf32_arm_section_data (sec)->erratumcount += 1;
8571
8572 newerr->u.b.vfp_insn = veneer_of_insn;
8573
8574 switch (span_type)
8575 {
8576 case 'a':
8577 newerr->type = VFP11_ERRATUM_BRANCH_TO_ARM_VENEER;
8578 break;
8579
8580 default:
8581 abort ();
8582 }
8583
8584 record_vfp11_erratum_veneer (link_info, newerr, abfd, sec,
c7b8f16e
JB		 8585 first_fmac);
8586
99059e56 8587 newerr->vma = -1;
c7b8f16e 8588
99059e56
RM		 8589 newerr->next = sec_data->erratumlist;
8590 sec_data->erratumlist = newerr;
c7b8f16e 8591
99059e56
RM		 8592 state = 0;
8593 }
c7b8f16e 8594
99059e56
RM		 8595 i = next_i;
8596 }
8597 }
906e58ca 8598
c7b8f16e 8599 if (contents != NULL
99059e56
RM		 8600 && elf_section_data (sec)->this_hdr.contents != contents)
8601 free (contents);
c7b8f16e
JB		 8602 contents = NULL;
8603 }
8604
8605 return TRUE;
8606
8607error_return:
8608 if (contents != NULL
8609 && elf_section_data (sec)->this_hdr.contents != contents)
8610 free (contents);
906e58ca 8611
c7b8f16e
JB		 8612 return FALSE;
8613}
8614
8615/* Find virtual-memory addresses for VFP11 erratum veneers and return locations
8616 after sections have been laid out, using specially-named symbols. */
8617
8618void
8619bfd_elf32_arm_vfp11_fix_veneer_locations (bfd *abfd,
8620 struct bfd_link_info *link_info)
8621{
8622 asection *sec;
8623 struct elf32_arm_link_hash_table *globals;
8624 char *tmp_name;
906e58ca 8625
0e1862bb 8626 if (bfd_link_relocatable (link_info))
c7b8f16e 8627 return;
2e6030b9
MS		 8628
8629 /* Skip if this bfd does not correspond to an ELF image. */
0ffa91dd 8630 if (! is_arm_elf (abfd))
2e6030b9
MS		 8631 return;
8632
c7b8f16e 8633 globals = elf32_arm_hash_table (link_info);
4dfe6ac6
NC		 8634 if (globals == NULL)
8635 return;
906e58ca 8636
21d799b5 8637 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen
99059e56 8638 (VFP11_ERRATUM_VENEER_ENTRY_NAME) + 10);
c7b8f16e
JB		 8639
8640 for (sec = abfd->sections; sec != NULL; sec = sec->next)
8641 {
8642 struct _arm_elf_section_data *sec_data = elf32_arm_section_data (sec);
8643 elf32_vfp11_erratum_list *errnode = sec_data->erratumlist;
906e58ca 8644
c7b8f16e 8645 for (; errnode != NULL; errnode = errnode->next)
99059e56
RM		 8646 {
8647 struct elf_link_hash_entry *myh;
8648 bfd_vma vma;
8649
8650 switch (errnode->type)
8651 {
8652 case VFP11_ERRATUM_BRANCH_TO_ARM_VENEER:
8653 case VFP11_ERRATUM_BRANCH_TO_THUMB_VENEER:
8654 /* Find veneer symbol. */
8655 sprintf (tmp_name, VFP11_ERRATUM_VENEER_ENTRY_NAME,
c7b8f16e
JB		 8656 errnode->u.b.veneer->u.v.id);
8657
99059e56
RM		 8658 myh = elf_link_hash_lookup
8659 (&(globals)->root, tmp_name, FALSE, FALSE, TRUE);
c7b8f16e 8660
a504d23a 8661 if (myh == NULL)
90b6238f
AM		 8662 _bfd_error_handler (_("%pB: unable to find %s veneer `%s'"),
8663 abfd, "VFP11", tmp_name);
a504d23a
LA		 8664
8665 vma = myh->root.u.def.section->output_section->vma
8666 + myh->root.u.def.section->output_offset
8667 + myh->root.u.def.value;
8668
8669 errnode->u.b.veneer->vma = vma;
8670 break;
8671
8672 case VFP11_ERRATUM_ARM_VENEER:
8673 case VFP11_ERRATUM_THUMB_VENEER:
8674 /* Find return location. */
8675 sprintf (tmp_name, VFP11_ERRATUM_VENEER_ENTRY_NAME "_r",
8676 errnode->u.v.id);
8677
8678 myh = elf_link_hash_lookup
8679 (&(globals)->root, tmp_name, FALSE, FALSE, TRUE);
8680
8681 if (myh == NULL)
90b6238f
AM		 8682 _bfd_error_handler (_("%pB: unable to find %s veneer `%s'"),
8683 abfd, "VFP11", tmp_name);
a504d23a
LA		 8684
8685 vma = myh->root.u.def.section->output_section->vma
8686 + myh->root.u.def.section->output_offset
8687 + myh->root.u.def.value;
8688
8689 errnode->u.v.branch->vma = vma;
8690 break;
8691
8692 default:
8693 abort ();
8694 }
8695 }
8696 }
8697
8698 free (tmp_name);
8699}
8700
8701/* Find virtual-memory addresses for STM32L4XX erratum veneers and
8702 return locations after sections have been laid out, using
8703 specially-named symbols. */
8704
8705void
8706bfd_elf32_arm_stm32l4xx_fix_veneer_locations (bfd *abfd,
8707 struct bfd_link_info *link_info)
8708{
8709 asection *sec;
8710 struct elf32_arm_link_hash_table *globals;
8711 char *tmp_name;
8712
8713 if (bfd_link_relocatable (link_info))
8714 return;
8715
8716 /* Skip if this bfd does not correspond to an ELF image. */
8717 if (! is_arm_elf (abfd))
8718 return;
8719
8720 globals = elf32_arm_hash_table (link_info);
8721 if (globals == NULL)
8722 return;
8723
8724 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen
8725 (STM32L4XX_ERRATUM_VENEER_ENTRY_NAME) + 10);
8726
8727 for (sec = abfd->sections; sec != NULL; sec = sec->next)
8728 {
8729 struct _arm_elf_section_data *sec_data = elf32_arm_section_data (sec);
8730 elf32_stm32l4xx_erratum_list *errnode = sec_data->stm32l4xx_erratumlist;
8731
8732 for (; errnode != NULL; errnode = errnode->next)
8733 {
8734 struct elf_link_hash_entry *myh;
8735 bfd_vma vma;
8736
8737 switch (errnode->type)
8738 {
8739 case STM32L4XX_ERRATUM_BRANCH_TO_VENEER:
8740 /* Find veneer symbol. */
8741 sprintf (tmp_name, STM32L4XX_ERRATUM_VENEER_ENTRY_NAME,
8742 errnode->u.b.veneer->u.v.id);
8743
8744 myh = elf_link_hash_lookup
8745 (&(globals)->root, tmp_name, FALSE, FALSE, TRUE);
8746
8747 if (myh == NULL)
90b6238f
AM		 8748 _bfd_error_handler (_("%pB: unable to find %s veneer `%s'"),
8749 abfd, "STM32L4XX", tmp_name);
a504d23a
LA		 8750
8751 vma = myh->root.u.def.section->output_section->vma
8752 + myh->root.u.def.section->output_offset
8753 + myh->root.u.def.value;
8754
8755 errnode->u.b.veneer->vma = vma;
8756 break;
8757
8758 case STM32L4XX_ERRATUM_VENEER:
8759 /* Find return location. */
8760 sprintf (tmp_name, STM32L4XX_ERRATUM_VENEER_ENTRY_NAME "_r",
8761 errnode->u.v.id);
8762
8763 myh = elf_link_hash_lookup
8764 (&(globals)->root, tmp_name, FALSE, FALSE, TRUE);
8765
8766 if (myh == NULL)
90b6238f
AM		 8767 _bfd_error_handler (_("%pB: unable to find %s veneer `%s'"),
8768 abfd, "STM32L4XX", tmp_name);
a504d23a
LA		 8769
8770 vma = myh->root.u.def.section->output_section->vma
8771 + myh->root.u.def.section->output_offset
8772 + myh->root.u.def.value;
8773
8774 errnode->u.v.branch->vma = vma;
8775 break;
8776
8777 default:
8778 abort ();
8779 }
8780 }
8781 }
8782
8783 free (tmp_name);
8784}
8785
8786static inline bfd_boolean
8787is_thumb2_ldmia (const insn32 insn)
8788{
8789 /* Encoding T2: LDM<c>.W <Rn>{!},<registers>
8790 1110 - 1000 - 10W1 - rrrr - PM (0) l - llll - llll - llll. */
8791 return (insn & 0xffd02000) == 0xe8900000;
8792}
8793
8794static inline bfd_boolean
8795is_thumb2_ldmdb (const insn32 insn)
8796{
8797 /* Encoding T1: LDMDB<c> <Rn>{!},<registers>
8798 1110 - 1001 - 00W1 - rrrr - PM (0) l - llll - llll - llll. */
8799 return (insn & 0xffd02000) == 0xe9100000;
8800}
8801
8802static inline bfd_boolean
8803is_thumb2_vldm (const insn32 insn)
8804{
8805 /* A6.5 Extension register load or store instruction
8806 A7.7.229
9239bbd3
CM		 8807 We look for SP 32-bit and DP 64-bit registers.
8808 Encoding T1 VLDM{mode}<c> <Rn>{!}, <list>
8809 <list> is consecutive 64-bit registers
8810 1110 - 110P - UDW1 - rrrr - vvvv - 1011 - iiii - iiii
a504d23a
LA		 8811 Encoding T2 VLDM{mode}<c> <Rn>{!}, <list>
8812 <list> is consecutive 32-bit registers
8813 1110 - 110P - UDW1 - rrrr - vvvv - 1010 - iiii - iiii
8814 if P==0 && U==1 && W==1 && Rn=1101 VPOP
8815 if PUW=010 || PUW=011 || PUW=101 VLDM. */
8816 return
9239bbd3
CM		 8817 (((insn & 0xfe100f00) == 0xec100b00) ||
8818 ((insn & 0xfe100f00) == 0xec100a00))
a504d23a
LA		 8819 && /* (IA without !). */
8820 (((((insn << 7) >> 28) & 0xd) == 0x4)
9239bbd3 8821 /* (IA with !), includes VPOP (when reg number is SP). */
a504d23a
LA		 8822 || ((((insn << 7) >> 28) & 0xd) == 0x5)
8823 /* (DB with !). */
8824 || ((((insn << 7) >> 28) & 0xd) == 0x9));
8825}
8826
8827/* STM STM32L4XX erratum : This function assumes that it receives an LDM or
8828 VLDM opcode and:
8829 - computes the number and the mode of memory accesses
8830 - decides if the replacement should be done:
8831 . replaces only if > 8-word accesses
8832 . or (testing purposes only) replaces all accesses. */
8833
8834static bfd_boolean
8835stm32l4xx_need_create_replacing_stub (const insn32 insn,
8836 bfd_arm_stm32l4xx_fix stm32l4xx_fix)
8837{
9239bbd3 8838 int nb_words = 0;
a504d23a
LA		 8839
8840 /* The field encoding the register list is the same for both LDMIA
8841 and LDMDB encodings. */
8842 if (is_thumb2_ldmia (insn) || is_thumb2_ldmdb (insn))
b25e998d 8843 nb_words = elf32_arm_popcount (insn & 0x0000ffff);
a504d23a 8844 else if (is_thumb2_vldm (insn))
9239bbd3 8845 nb_words = (insn & 0xff);
a504d23a
LA		 8846
8847 /* DEFAULT mode accounts for the real bug condition situation,
8848 ALL mode inserts stubs for each LDM/VLDM instruction (testing). */
8849 return
9239bbd3 8850 (stm32l4xx_fix == BFD_ARM_STM32L4XX_FIX_DEFAULT) ? nb_words > 8 :
a504d23a
LA		 8851 (stm32l4xx_fix == BFD_ARM_STM32L4XX_FIX_ALL) ? TRUE : FALSE;
8852}
8853
8854/* Look for potentially-troublesome code sequences which might trigger
8855 the STM STM32L4XX erratum. */
8856
8857bfd_boolean
8858bfd_elf32_arm_stm32l4xx_erratum_scan (bfd *abfd,
8859 struct bfd_link_info *link_info)
8860{
8861 asection *sec;
8862 bfd_byte *contents = NULL;
8863 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (link_info);
8864
8865 if (globals == NULL)
8866 return FALSE;
8867
8868 /* If we are only performing a partial link do not bother
8869 to construct any glue. */
8870 if (bfd_link_relocatable (link_info))
8871 return TRUE;
8872
8873 /* Skip if this bfd does not correspond to an ELF image. */
8874 if (! is_arm_elf (abfd))
8875 return TRUE;
8876
8877 if (globals->stm32l4xx_fix == BFD_ARM_STM32L4XX_FIX_NONE)
8878 return TRUE;
8879
8880 /* Skip this BFD if it corresponds to an executable or dynamic object. */
8881 if ((abfd->flags & (EXEC_P | DYNAMIC)) != 0)
8882 return TRUE;
8883
8884 for (sec = abfd->sections; sec != NULL; sec = sec->next)
8885 {
8886 unsigned int i, span;
8887 struct _arm_elf_section_data *sec_data;
8888
8889 /* If we don't have executable progbits, we're not interested in this
8890 section. Also skip if section is to be excluded. */
8891 if (elf_section_type (sec) != SHT_PROGBITS
8892 || (elf_section_flags (sec) & SHF_EXECINSTR) == 0
8893 || (sec->flags & SEC_EXCLUDE) != 0
8894 || sec->sec_info_type == SEC_INFO_TYPE_JUST_SYMS
8895 || sec->output_section == bfd_abs_section_ptr
8896 || strcmp (sec->name, STM32L4XX_ERRATUM_VENEER_SECTION_NAME) == 0)
8897 continue;
8898
8899 sec_data = elf32_arm_section_data (sec);
c7b8f16e 8900
a504d23a
LA		 8901 if (sec_data->mapcount == 0)
8902 continue;
c7b8f16e 8903
a504d23a
LA		 8904 if (elf_section_data (sec)->this_hdr.contents != NULL)
8905 contents = elf_section_data (sec)->this_hdr.contents;
8906 else if (! bfd_malloc_and_get_section (abfd, sec, &contents))
8907 goto error_return;
c7b8f16e 8908
a504d23a
LA		 8909 qsort (sec_data->map, sec_data->mapcount, sizeof (elf32_arm_section_map),
8910 elf32_arm_compare_mapping);
c7b8f16e 8911
a504d23a
LA		 8912 for (span = 0; span < sec_data->mapcount; span++)
8913 {
8914 unsigned int span_start = sec_data->map[span].vma;
8915 unsigned int span_end = (span == sec_data->mapcount - 1)
8916 ? sec->size : sec_data->map[span + 1].vma;
8917 char span_type = sec_data->map[span].type;
8918 int itblock_current_pos = 0;
c7b8f16e 8919
a504d23a
LA		 8920 /* Only Thumb2 mode need be supported with this CM4 specific
8921 code, we should not encounter any arm mode eg span_type
8922 != 'a'. */
8923 if (span_type != 't')
8924 continue;
c7b8f16e 8925
a504d23a
LA		 8926 for (i = span_start; i < span_end;)
8927 {
8928 unsigned int insn = bfd_get_16 (abfd, &contents[i]);
8929 bfd_boolean insn_32bit = FALSE;
8930 bfd_boolean is_ldm = FALSE;
8931 bfd_boolean is_vldm = FALSE;
8932 bfd_boolean is_not_last_in_it_block = FALSE;
8933
8934 /* The first 16-bits of all 32-bit thumb2 instructions start
8935 with opcode[15..13]=0b111 and the encoded op1 can be anything
8936 except opcode[12..11]!=0b00.
8937 See 32-bit Thumb instruction encoding. */
8938 if ((insn & 0xe000) == 0xe000 && (insn & 0x1800) != 0x0000)
8939 insn_32bit = TRUE;
c7b8f16e 8940
a504d23a
LA		 8941 /* Compute the predicate that tells if the instruction
8942 is concerned by the IT block
8943 - Creates an error if there is a ldm that is not
8944 last in the IT block thus cannot be replaced
8945 - Otherwise we can create a branch at the end of the
8946 IT block, it will be controlled naturally by IT
8947 with the proper pseudo-predicate
8948 - So the only interesting predicate is the one that
8949 tells that we are not on the last item of an IT
8950 block. */
8951 if (itblock_current_pos != 0)
8952 is_not_last_in_it_block = !!--itblock_current_pos;
906e58ca 8953
a504d23a
LA		 8954 if (insn_32bit)
8955 {
8956 /* Load the rest of the insn (in manual-friendly order). */
8957 insn = (insn << 16) | bfd_get_16 (abfd, &contents[i + 2]);
8958 is_ldm = is_thumb2_ldmia (insn) || is_thumb2_ldmdb (insn);
8959 is_vldm = is_thumb2_vldm (insn);
8960
8961 /* Veneers are created for (v)ldm depending on
8962 option flags and memory accesses conditions; but
8963 if the instruction is not the last instruction of
8964 an IT block, we cannot create a jump there, so we
8965 bail out. */
5025eb7c
AO		 8966 if ((is_ldm || is_vldm)
8967 && stm32l4xx_need_create_replacing_stub
a504d23a
LA		 8968 (insn, globals->stm32l4xx_fix))
8969 {
8970 if (is_not_last_in_it_block)
8971 {
4eca0228 8972 _bfd_error_handler
695344c0 8973 /* xgettext:c-format */
871b3ab2 8974 (_("%pB(%pA+%#x): error: multiple load detected"
90b6238f
AM		 8975 " in non-last IT block instruction:"
8976 " STM32L4XX veneer cannot be generated; "
8977 "use gcc option -mrestrict-it to generate"
8978 " only one instruction per IT block"),
d42c267e 8979 abfd, sec, i);
a504d23a
LA		 8980 }
8981 else
8982 {
8983 elf32_stm32l4xx_erratum_list *newerr =
8984 (elf32_stm32l4xx_erratum_list *)
8985 bfd_zmalloc
8986 (sizeof (elf32_stm32l4xx_erratum_list));
8987
8988 elf32_arm_section_data (sec)
8989 ->stm32l4xx_erratumcount += 1;
8990 newerr->u.b.insn = insn;
8991 /* We create only thumb branches. */
8992 newerr->type =
8993 STM32L4XX_ERRATUM_BRANCH_TO_VENEER;
8994 record_stm32l4xx_erratum_veneer
8995 (link_info, newerr, abfd, sec,
8996 i,
8997 is_ldm ?
8998 STM32L4XX_ERRATUM_LDM_VENEER_SIZE:
8999 STM32L4XX_ERRATUM_VLDM_VENEER_SIZE);
9000 newerr->vma = -1;
9001 newerr->next = sec_data->stm32l4xx_erratumlist;
9002 sec_data->stm32l4xx_erratumlist = newerr;
9003 }
9004 }
9005 }
9006 else
9007 {
9008 /* A7.7.37 IT p208
9009 IT blocks are only encoded in T1
9010 Encoding T1: IT{x{y{z}}} <firstcond>
9011 1 0 1 1 - 1 1 1 1 - firstcond - mask
9012 if mask = '0000' then see 'related encodings'
9013 We don't deal with UNPREDICTABLE, just ignore these.
9014 There can be no nested IT blocks so an IT block
9015 is naturally a new one for which it is worth
9016 computing its size. */
5025eb7c
AO		 9017 bfd_boolean is_newitblock = ((insn & 0xff00) == 0xbf00)
9018 && ((insn & 0x000f) != 0x0000);
a504d23a
LA		 9019 /* If we have a new IT block we compute its size. */
9020 if (is_newitblock)
9021 {
9022 /* Compute the number of instructions controlled
9023 by the IT block, it will be used to decide
9024 whether we are inside an IT block or not. */
9025 unsigned int mask = insn & 0x000f;
9026 itblock_current_pos = 4 - ctz (mask);
9027 }
9028 }
9029
9030 i += insn_32bit ? 4 : 2;
99059e56
RM		 9031 }
9032 }
a504d23a
LA		 9033
9034 if (contents != NULL
9035 && elf_section_data (sec)->this_hdr.contents != contents)
9036 free (contents);
9037 contents = NULL;
c7b8f16e 9038 }
906e58ca 9039
a504d23a
LA		 9040 return TRUE;
9041
9042error_return:
9043 if (contents != NULL
9044 && elf_section_data (sec)->this_hdr.contents != contents)
9045 free (contents);
c7b8f16e 9046
a504d23a
LA		 9047 return FALSE;
9048}
c7b8f16e 9049
eb043451
PB		 9050/* Set target relocation values needed during linking. */
9051
9052void
68c39892 9053bfd_elf32_arm_set_target_params (struct bfd *output_bfd,
bf21ed78 9054 struct bfd_link_info *link_info,
68c39892 9055 struct elf32_arm_params *params)
eb043451
PB		 9056{
9057 struct elf32_arm_link_hash_table *globals;
9058
9059 globals = elf32_arm_hash_table (link_info);
4dfe6ac6
NC		 9060 if (globals == NULL)
9061 return;
eb043451 9062
68c39892 9063 globals->target1_is_rel = params->target1_is_rel;
29e9b073
CL		 9064 if (globals->fdpic_p)
9065 globals->target2_reloc = R_ARM_GOT32;
9066 else if (strcmp (params->target2_type, "rel") == 0)
eb043451 9067 globals->target2_reloc = R_ARM_REL32;
68c39892 9068 else if (strcmp (params->target2_type, "abs") == 0)
eeac373a 9069 globals->target2_reloc = R_ARM_ABS32;
68c39892 9070 else if (strcmp (params->target2_type, "got-rel") == 0)
eb043451
PB		 9071 globals->target2_reloc = R_ARM_GOT_PREL;
9072 else
9073 {
90b6238f 9074 _bfd_error_handler (_("invalid TARGET2 relocation type '%s'"),
68c39892 9075 params->target2_type);
eb043451 9076 }
68c39892
TP		 9077 globals->fix_v4bx = params->fix_v4bx;
9078 globals->use_blx |= params->use_blx;
9079 globals->vfp11_fix = params->vfp11_denorm_fix;
9080 globals->stm32l4xx_fix = params->stm32l4xx_fix;
e8b09b87
CL		 9081 if (globals->fdpic_p)
9082 globals->pic_veneer = 1;
9083 else
9084 globals->pic_veneer = params->pic_veneer;
68c39892
TP		 9085 globals->fix_cortex_a8 = params->fix_cortex_a8;
9086 globals->fix_arm1176 = params->fix_arm1176;
9087 globals->cmse_implib = params->cmse_implib;
9088 globals->in_implib_bfd = params->in_implib_bfd;
bf21ed78 9089
0ffa91dd 9090 BFD_ASSERT (is_arm_elf (output_bfd));
68c39892
TP		 9091 elf_arm_tdata (output_bfd)->no_enum_size_warning
9092 = params->no_enum_size_warning;
9093 elf_arm_tdata (output_bfd)->no_wchar_size_warning
9094 = params->no_wchar_size_warning;
eb043451 9095}
eb043451 9096
12a0a0fd 9097/* Replace the target offset of a Thumb bl or b.w instruction. */
252b5132 9098
12a0a0fd
PB		 9099static void
9100insert_thumb_branch (bfd *abfd, long int offset, bfd_byte *insn)
9101{
9102 bfd_vma upper;
9103 bfd_vma lower;
9104 int reloc_sign;
9105
9106 BFD_ASSERT ((offset & 1) == 0);
9107
9108 upper = bfd_get_16 (abfd, insn);
9109 lower = bfd_get_16 (abfd, insn + 2);
9110 reloc_sign = (offset < 0) ? 1 : 0;
9111 upper = (upper & ~(bfd_vma) 0x7ff)
9112 | ((offset >> 12) & 0x3ff)
9113 | (reloc_sign << 10);
906e58ca 9114 lower = (lower & ~(bfd_vma) 0x2fff)
12a0a0fd
PB		 9115 | (((!((offset >> 23) & 1)) ^ reloc_sign) << 13)
9116 | (((!((offset >> 22) & 1)) ^ reloc_sign) << 11)
9117 | ((offset >> 1) & 0x7ff);
9118 bfd_put_16 (abfd, upper, insn);
9119 bfd_put_16 (abfd, lower, insn + 2);
252b5132
RH		 9120}
9121
9b485d32
NC		 9122/* Thumb code calling an ARM function. */
9123
252b5132 9124static int
57e8b36a 9125elf32_thumb_to_arm_stub (struct bfd_link_info * info,
07d6d2b8
AM		 9126 const char * name,
9127 bfd * input_bfd,
9128 bfd * output_bfd,
9129 asection * input_section,
9130 bfd_byte * hit_data,
9131 asection * sym_sec,
9132 bfd_vma offset,
9133 bfd_signed_vma addend,
9134 bfd_vma val,
f2a9dd69 9135 char **error_message)
252b5132 9136{
bcbdc74c 9137 asection * s = 0;
dc810e39 9138 bfd_vma my_offset;
252b5132 9139 long int ret_offset;
bcbdc74c
NC		 9140 struct elf_link_hash_entry * myh;
9141 struct elf32_arm_link_hash_table * globals;
252b5132 9142
f2a9dd69 9143 myh = find_thumb_glue (info, name, error_message);
252b5132 9144 if (myh == NULL)
b34976b6 9145 return FALSE;
252b5132
RH		 9146
9147 globals = elf32_arm_hash_table (info);
252b5132
RH		 9148 BFD_ASSERT (globals != NULL);
9149 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
9150
9151 my_offset = myh->root.u.def.value;
9152
3d4d4302
AM		 9153 s = bfd_get_linker_section (globals->bfd_of_glue_owner,
9154 THUMB2ARM_GLUE_SECTION_NAME);
252b5132
RH		 9155
9156 BFD_ASSERT (s != NULL);
9157 BFD_ASSERT (s->contents != NULL);
9158 BFD_ASSERT (s->output_section != NULL);
9159
9160 if ((my_offset & 0x01) == 0x01)
9161 {
9162 if (sym_sec != NULL
9163 && sym_sec->owner != NULL
9164 && !INTERWORK_FLAG (sym_sec->owner))
9165 {
4eca0228 9166 _bfd_error_handler
90b6238f
AM		 9167 (_("%pB(%s): warning: interworking not enabled;"
9168 " first occurrence: %pB: %s call to %s"),
9169 sym_sec->owner, name, input_bfd, "Thumb", "ARM");
252b5132 9170
b34976b6 9171 return FALSE;
252b5132
RH		 9172 }
9173
9174 --my_offset;
9175 myh->root.u.def.value = my_offset;
9176
52ab56c2
PB		 9177 put_thumb_insn (globals, output_bfd, (bfd_vma) t2a1_bx_pc_insn,
9178 s->contents + my_offset);
252b5132 9179
52ab56c2
PB		 9180 put_thumb_insn (globals, output_bfd, (bfd_vma) t2a2_noop_insn,
9181 s->contents + my_offset + 2);
252b5132
RH		 9182
9183 ret_offset =
9b485d32
NC		 9184 /* Address of destination of the stub. */
9185 ((bfd_signed_vma) val)
252b5132 9186 - ((bfd_signed_vma)
57e8b36a
NC		 9187 /* Offset from the start of the current section
9188 to the start of the stubs. */
9b485d32
NC		 9189 (s->output_offset
9190 /* Offset of the start of this stub from the start of the stubs. */
9191 + my_offset
9192 /* Address of the start of the current section. */
9193 + s->output_section->vma)
9194 /* The branch instruction is 4 bytes into the stub. */
9195 + 4
9196 /* ARM branches work from the pc of the instruction + 8. */
9197 + 8);
252b5132 9198
52ab56c2
PB		 9199 put_arm_insn (globals, output_bfd,
9200 (bfd_vma) t2a3_b_insn | ((ret_offset >> 2) & 0x00FFFFFF),
9201 s->contents + my_offset + 4);
252b5132
RH		 9202 }
9203
9204 BFD_ASSERT (my_offset <= globals->thumb_glue_size);
9205
427bfd90
NC		 9206 /* Now go back and fix up the original BL insn to point to here. */
9207 ret_offset =
9208 /* Address of where the stub is located. */
9209 (s->output_section->vma + s->output_offset + my_offset)
9210 /* Address of where the BL is located. */
57e8b36a
NC		 9211 - (input_section->output_section->vma + input_section->output_offset
9212 + offset)
427bfd90
NC		 9213 /* Addend in the relocation. */
9214 - addend
9215 /* Biassing for PC-relative addressing. */
9216 - 8;
252b5132 9217
12a0a0fd 9218 insert_thumb_branch (input_bfd, ret_offset, hit_data - input_section->vma);
252b5132 9219
b34976b6 9220 return TRUE;
252b5132
RH		 9221}
9222
a4fd1a8e 9223/* Populate an Arm to Thumb stub. Returns the stub symbol. */
9b485d32 9224
a4fd1a8e
PB		 9225static struct elf_link_hash_entry *
9226elf32_arm_create_thumb_stub (struct bfd_link_info * info,
07d6d2b8
AM		 9227 const char * name,
9228 bfd * input_bfd,
9229 bfd * output_bfd,
9230 asection * sym_sec,
9231 bfd_vma val,
9232 asection * s,
9233 char ** error_message)
252b5132 9234{
dc810e39 9235 bfd_vma my_offset;
252b5132 9236 long int ret_offset;
bcbdc74c
NC		 9237 struct elf_link_hash_entry * myh;
9238 struct elf32_arm_link_hash_table * globals;
252b5132 9239
f2a9dd69 9240 myh = find_arm_glue (info, name, error_message);
252b5132 9241 if (myh == NULL)
a4fd1a8e 9242 return NULL;
252b5132
RH		 9243
9244 globals = elf32_arm_hash_table (info);
252b5132
RH		 9245 BFD_ASSERT (globals != NULL);
9246 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
9247
9248 my_offset = myh->root.u.def.value;
252b5132
RH		 9249
9250 if ((my_offset & 0x01) == 0x01)
9251 {
9252 if (sym_sec != NULL
9253 && sym_sec->owner != NULL
9254 && !INTERWORK_FLAG (sym_sec->owner))
9255 {
4eca0228 9256 _bfd_error_handler
90b6238f
AM		 9257 (_("%pB(%s): warning: interworking not enabled;"
9258 " first occurrence: %pB: %s call to %s"),
9259 sym_sec->owner, name, input_bfd, "ARM", "Thumb");
252b5132 9260 }
9b485d32 9261
252b5132
RH		 9262 --my_offset;
9263 myh->root.u.def.value = my_offset;
9264
0e1862bb
L		 9265 if (bfd_link_pic (info)
9266 || globals->root.is_relocatable_executable
27e55c4d 9267 || globals->pic_veneer)
8f6277f5
PB		 9268 {
9269 /* For relocatable objects we can't use absolute addresses,
9270 so construct the address from a relative offset. */
9271 /* TODO: If the offset is small it's probably worth
9272 constructing the address with adds. */
52ab56c2
PB		 9273 put_arm_insn (globals, output_bfd, (bfd_vma) a2t1p_ldr_insn,
9274 s->contents + my_offset);
9275 put_arm_insn (globals, output_bfd, (bfd_vma) a2t2p_add_pc_insn,
9276 s->contents + my_offset + 4);
9277 put_arm_insn (globals, output_bfd, (bfd_vma) a2t3p_bx_r12_insn,
9278 s->contents + my_offset + 8);
8f6277f5
PB		 9279 /* Adjust the offset by 4 for the position of the add,
9280 and 8 for the pipeline offset. */
9281 ret_offset = (val - (s->output_offset
9282 + s->output_section->vma
9283 + my_offset + 12))
9284 | 1;
9285 bfd_put_32 (output_bfd, ret_offset,
9286 s->contents + my_offset + 12);
9287 }
26079076
PB		 9288 else if (globals->use_blx)
9289 {
9290 put_arm_insn (globals, output_bfd, (bfd_vma) a2t1v5_ldr_insn,
9291 s->contents + my_offset);
9292
9293 /* It's a thumb address. Add the low order bit. */
9294 bfd_put_32 (output_bfd, val | a2t2v5_func_addr_insn,
9295 s->contents + my_offset + 4);
9296 }
8f6277f5
PB		 9297 else
9298 {
52ab56c2
PB		 9299 put_arm_insn (globals, output_bfd, (bfd_vma) a2t1_ldr_insn,
9300 s->contents + my_offset);
252b5132 9301
52ab56c2
PB		 9302 put_arm_insn (globals, output_bfd, (bfd_vma) a2t2_bx_r12_insn,
9303 s->contents + my_offset + 4);
252b5132 9304
8f6277f5
PB		 9305 /* It's a thumb address. Add the low order bit. */
9306 bfd_put_32 (output_bfd, val | a2t3_func_addr_insn,
9307 s->contents + my_offset + 8);
8029a119
NC		 9308
9309 my_offset += 12;
8f6277f5 9310 }
252b5132
RH		 9311 }
9312
9313 BFD_ASSERT (my_offset <= globals->arm_glue_size);
9314
a4fd1a8e
PB		 9315 return myh;
9316}
9317
9318/* Arm code calling a Thumb function. */
9319
9320static int
9321elf32_arm_to_thumb_stub (struct bfd_link_info * info,
07d6d2b8
AM		 9322 const char * name,
9323 bfd * input_bfd,
9324 bfd * output_bfd,
9325 asection * input_section,
9326 bfd_byte * hit_data,
9327 asection * sym_sec,
9328 bfd_vma offset,
9329 bfd_signed_vma addend,
9330 bfd_vma val,
f2a9dd69 9331 char **error_message)
a4fd1a8e
PB		 9332{
9333 unsigned long int tmp;
9334 bfd_vma my_offset;
9335 asection * s;
9336 long int ret_offset;
9337 struct elf_link_hash_entry * myh;
9338 struct elf32_arm_link_hash_table * globals;
9339
9340 globals = elf32_arm_hash_table (info);
a4fd1a8e
PB		 9341 BFD_ASSERT (globals != NULL);
9342 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
9343
3d4d4302
AM		 9344 s = bfd_get_linker_section (globals->bfd_of_glue_owner,
9345 ARM2THUMB_GLUE_SECTION_NAME);
a4fd1a8e
PB		 9346 BFD_ASSERT (s != NULL);
9347 BFD_ASSERT (s->contents != NULL);
9348 BFD_ASSERT (s->output_section != NULL);
9349
9350 myh = elf32_arm_create_thumb_stub (info, name, input_bfd, output_bfd,
f2a9dd69 9351 sym_sec, val, s, error_message);
a4fd1a8e
PB		 9352 if (!myh)
9353 return FALSE;
9354
9355 my_offset = myh->root.u.def.value;
252b5132
RH		 9356 tmp = bfd_get_32 (input_bfd, hit_data);
9357 tmp = tmp & 0xFF000000;
9358
9b485d32 9359 /* Somehow these are both 4 too far, so subtract 8. */
dc810e39
AM		 9360 ret_offset = (s->output_offset
9361 + my_offset
9362 + s->output_section->vma
9363 - (input_section->output_offset
9364 + input_section->output_section->vma
9365 + offset + addend)
9366 - 8);
9a5aca8c 9367
252b5132
RH		 9368 tmp = tmp | ((ret_offset >> 2) & 0x00FFFFFF);
9369
dc810e39 9370 bfd_put_32 (output_bfd, (bfd_vma) tmp, hit_data - input_section->vma);
252b5132 9371
b34976b6 9372 return TRUE;
252b5132
RH		 9373}
9374
a4fd1a8e
PB		 9375/* Populate Arm stub for an exported Thumb function. */
9376
9377static bfd_boolean
9378elf32_arm_to_thumb_export_stub (struct elf_link_hash_entry *h, void * inf)
9379{
9380 struct bfd_link_info * info = (struct bfd_link_info *) inf;
9381 asection * s;
9382 struct elf_link_hash_entry * myh;
9383 struct elf32_arm_link_hash_entry *eh;
9384 struct elf32_arm_link_hash_table * globals;
9385 asection *sec;
9386 bfd_vma val;
f2a9dd69 9387 char *error_message;
a4fd1a8e 9388
906e58ca 9389 eh = elf32_arm_hash_entry (h);
a4fd1a8e
PB		 9390 /* Allocate stubs for exported Thumb functions on v4t. */
9391 if (eh->export_glue == NULL)
9392 return TRUE;
9393
9394 globals = elf32_arm_hash_table (info);
a4fd1a8e
PB		 9395 BFD_ASSERT (globals != NULL);
9396 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
9397
3d4d4302
AM		 9398 s = bfd_get_linker_section (globals->bfd_of_glue_owner,
9399 ARM2THUMB_GLUE_SECTION_NAME);
a4fd1a8e
PB		 9400 BFD_ASSERT (s != NULL);
9401 BFD_ASSERT (s->contents != NULL);
9402 BFD_ASSERT (s->output_section != NULL);
9403
9404 sec = eh->export_glue->root.u.def.section;
0eaedd0e
PB		 9405
9406 BFD_ASSERT (sec->output_section != NULL);
9407
a4fd1a8e
PB		 9408 val = eh->export_glue->root.u.def.value + sec->output_offset
9409 + sec->output_section->vma;
8029a119 9410
a4fd1a8e
PB		 9411 myh = elf32_arm_create_thumb_stub (info, h->root.root.string,
9412 h->root.u.def.section->owner,
f2a9dd69
DJ		 9413 globals->obfd, sec, val, s,
9414 &error_message);
a4fd1a8e
PB		 9415 BFD_ASSERT (myh);
9416 return TRUE;
9417}
9418
845b51d6
PB		 9419/* Populate ARMv4 BX veneers. Returns the absolute adress of the veneer. */
9420
9421static bfd_vma
9422elf32_arm_bx_glue (struct bfd_link_info * info, int reg)
9423{
9424 bfd_byte *p;
9425 bfd_vma glue_addr;
9426 asection *s;
9427 struct elf32_arm_link_hash_table *globals;
9428
9429 globals = elf32_arm_hash_table (info);
845b51d6
PB		 9430 BFD_ASSERT (globals != NULL);
9431 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
9432
3d4d4302
AM		 9433 s = bfd_get_linker_section (globals->bfd_of_glue_owner,
9434 ARM_BX_GLUE_SECTION_NAME);
845b51d6
PB		 9435 BFD_ASSERT (s != NULL);
9436 BFD_ASSERT (s->contents != NULL);
9437 BFD_ASSERT (s->output_section != NULL);
9438
9439 BFD_ASSERT (globals->bx_glue_offset[reg] & 2);
9440
9441 glue_addr = globals->bx_glue_offset[reg] & ~(bfd_vma)3;
9442
9443 if ((globals->bx_glue_offset[reg] & 1) == 0)
9444 {
9445 p = s->contents + glue_addr;
9446 bfd_put_32 (globals->obfd, armbx1_tst_insn + (reg << 16), p);
9447 bfd_put_32 (globals->obfd, armbx2_moveq_insn + reg, p + 4);
9448 bfd_put_32 (globals->obfd, armbx3_bx_insn + reg, p + 8);
9449 globals->bx_glue_offset[reg] |= 1;
9450 }
9451
9452 return glue_addr + s->output_section->vma + s->output_offset;
9453}
9454
a4fd1a8e
PB		 9455/* Generate Arm stubs for exported Thumb symbols. */
9456static void
906e58ca 9457elf32_arm_begin_write_processing (bfd *abfd ATTRIBUTE_UNUSED,
a4fd1a8e
PB		 9458 struct bfd_link_info *link_info)
9459{
9460 struct elf32_arm_link_hash_table * globals;
9461
8029a119
NC		 9462 if (link_info == NULL)
9463 /* Ignore this if we are not called by the ELF backend linker. */
a4fd1a8e
PB		 9464 return;
9465
9466 globals = elf32_arm_hash_table (link_info);
4dfe6ac6
NC		 9467 if (globals == NULL)
9468 return;
9469
84c08195
PB		 9470 /* If blx is available then exported Thumb symbols are OK and there is
9471 nothing to do. */
a4fd1a8e
PB		 9472 if (globals->use_blx)
9473 return;
9474
9475 elf_link_hash_traverse (&globals->root, elf32_arm_to_thumb_export_stub,
9476 link_info);
9477}
9478
47beaa6a
RS		 9479/* Reserve space for COUNT dynamic relocations in relocation selection
9480 SRELOC. */
9481
9482static void
9483elf32_arm_allocate_dynrelocs (struct bfd_link_info *info, asection *sreloc,
9484 bfd_size_type count)
9485{
9486 struct elf32_arm_link_hash_table *htab;
9487
9488 htab = elf32_arm_hash_table (info);
9489 BFD_ASSERT (htab->root.dynamic_sections_created);
9490 if (sreloc == NULL)
9491 abort ();
9492 sreloc->size += RELOC_SIZE (htab) * count;
9493}
9494
34e77a92
RS		 9495/* Reserve space for COUNT R_ARM_IRELATIVE relocations. If the link is
9496 dynamic, the relocations should go in SRELOC, otherwise they should
9497 go in the special .rel.iplt section. */
9498
9499static void
9500elf32_arm_allocate_irelocs (struct bfd_link_info *info, asection *sreloc,
9501 bfd_size_type count)
9502{
9503 struct elf32_arm_link_hash_table *htab;
9504
9505 htab = elf32_arm_hash_table (info);
9506 if (!htab->root.dynamic_sections_created)
9507 htab->root.irelplt->size += RELOC_SIZE (htab) * count;
9508 else
9509 {
9510 BFD_ASSERT (sreloc != NULL);
9511 sreloc->size += RELOC_SIZE (htab) * count;
9512 }
9513}
9514
47beaa6a
RS		 9515/* Add relocation REL to the end of relocation section SRELOC. */
9516
9517static void
9518elf32_arm_add_dynreloc (bfd *output_bfd, struct bfd_link_info *info,
9519 asection *sreloc, Elf_Internal_Rela *rel)
9520{
9521 bfd_byte *loc;
9522 struct elf32_arm_link_hash_table *htab;
9523
9524 htab = elf32_arm_hash_table (info);
34e77a92
RS		 9525 if (!htab->root.dynamic_sections_created
9526 && ELF32_R_TYPE (rel->r_info) == R_ARM_IRELATIVE)
9527 sreloc = htab->root.irelplt;
47beaa6a
RS		 9528 if (sreloc == NULL)
9529 abort ();
9530 loc = sreloc->contents;
9531 loc += sreloc->reloc_count++ * RELOC_SIZE (htab);
9532 if (sreloc->reloc_count * RELOC_SIZE (htab) > sreloc->size)
9533 abort ();
9534 SWAP_RELOC_OUT (htab) (output_bfd, rel, loc);
9535}
9536
34e77a92
RS		 9537/* Allocate room for a PLT entry described by ROOT_PLT and ARM_PLT.
9538 IS_IPLT_ENTRY says whether the entry belongs to .iplt rather than
9539 to .plt. */
9540
9541static void
9542elf32_arm_allocate_plt_entry (struct bfd_link_info *info,
9543 bfd_boolean is_iplt_entry,
9544 union gotplt_union *root_plt,
9545 struct arm_plt_info *arm_plt)
9546{
9547 struct elf32_arm_link_hash_table *htab;
9548 asection *splt;
9549 asection *sgotplt;
9550
9551 htab = elf32_arm_hash_table (info);
9552
9553 if (is_iplt_entry)
9554 {
9555 splt = htab->root.iplt;
9556 sgotplt = htab->root.igotplt;
9557
99059e56
RM		 9558 /* NaCl uses a special first entry in .iplt too. */
9559 if (htab->nacl_p && splt->size == 0)
9560 splt->size += htab->plt_header_size;
9561
34e77a92
RS		 9562 /* Allocate room for an R_ARM_IRELATIVE relocation in .rel.iplt. */
9563 elf32_arm_allocate_irelocs (info, htab->root.irelplt, 1);
9564 }
9565 else
9566 {
9567 splt = htab->root.splt;
9568 sgotplt = htab->root.sgotplt;
9569
7801f98f
CL		 9570 if (htab->fdpic_p)
9571 {
9572 /* Allocate room for R_ARM_FUNCDESC_VALUE. */
9573 /* For lazy binding, relocations will be put into .rel.plt, in
9574 .rel.got otherwise. */
9575 /* FIXME: today we don't support lazy binding so put it in .rel.got */
9576 if (info->flags & DF_BIND_NOW)
9577 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
9578 else
9579 elf32_arm_allocate_dynrelocs (info, htab->root.srelplt, 1);
9580 }
9581 else
9582 {
9583 /* Allocate room for an R_JUMP_SLOT relocation in .rel.plt. */
9584 elf32_arm_allocate_dynrelocs (info, htab->root.srelplt, 1);
9585 }
34e77a92
RS		 9586
9587 /* If this is the first .plt entry, make room for the special
9588 first entry. */
9589 if (splt->size == 0)
9590 splt->size += htab->plt_header_size;
9f19ab6d
WN		 9591
9592 htab->next_tls_desc_index++;
34e77a92
RS		 9593 }
9594
9595 /* Allocate the PLT entry itself, including any leading Thumb stub. */
9596 if (elf32_arm_plt_needs_thumb_stub_p (info, arm_plt))
9597 splt->size += PLT_THUMB_STUB_SIZE;
9598 root_plt->offset = splt->size;
9599 splt->size += htab->plt_entry_size;
9600
9601 if (!htab->symbian_p)
9602 {
9603 /* We also need to make an entry in the .got.plt section, which
9604 will be placed in the .got section by the linker script. */
9f19ab6d
WN		 9605 if (is_iplt_entry)
9606 arm_plt->got_offset = sgotplt->size;
9607 else
9608 arm_plt->got_offset = sgotplt->size - 8 * htab->num_tls_desc;
7801f98f
CL		 9609 if (htab->fdpic_p)
9610 /* Function descriptor takes 64 bits in GOT. */
4b24dd1a 9611 sgotplt->size += 8;
7801f98f
CL		 9612 else
9613 sgotplt->size += 4;
34e77a92
RS		 9614 }
9615}
9616
b38cadfb
NC		 9617static bfd_vma
9618arm_movw_immediate (bfd_vma value)
9619{
9620 return (value & 0x00000fff) | ((value & 0x0000f000) << 4);
9621}
9622
9623static bfd_vma
9624arm_movt_immediate (bfd_vma value)
9625{
9626 return ((value & 0x0fff0000) >> 16) | ((value & 0xf0000000) >> 12);
9627}
9628
34e77a92
RS		 9629/* Fill in a PLT entry and its associated GOT slot. If DYNINDX == -1,
9630 the entry lives in .iplt and resolves to (*SYM_VALUE)().
9631 Otherwise, DYNINDX is the index of the symbol in the dynamic
9632 symbol table and SYM_VALUE is undefined.
9633
9634 ROOT_PLT points to the offset of the PLT entry from the start of its
9635 section (.iplt or .plt). ARM_PLT points to the symbol's ARM-specific
57460bcf 9636 bookkeeping information.
34e77a92 9637
57460bcf
NC		 9638 Returns FALSE if there was a problem. */
9639
9640static bfd_boolean
34e77a92
RS		 9641elf32_arm_populate_plt_entry (bfd *output_bfd, struct bfd_link_info *info,
9642 union gotplt_union *root_plt,
9643 struct arm_plt_info *arm_plt,
9644 int dynindx, bfd_vma sym_value)
9645{
9646 struct elf32_arm_link_hash_table *htab;
9647 asection *sgot;
9648 asection *splt;
9649 asection *srel;
9650 bfd_byte *loc;
9651 bfd_vma plt_index;
9652 Elf_Internal_Rela rel;
9653 bfd_vma plt_header_size;
9654 bfd_vma got_header_size;
9655
9656 htab = elf32_arm_hash_table (info);
9657
9658 /* Pick the appropriate sections and sizes. */
9659 if (dynindx == -1)
9660 {
9661 splt = htab->root.iplt;
9662 sgot = htab->root.igotplt;
9663 srel = htab->root.irelplt;
9664
9665 /* There are no reserved entries in .igot.plt, and no special
9666 first entry in .iplt. */
9667 got_header_size = 0;
9668 plt_header_size = 0;
9669 }
9670 else
9671 {
9672 splt = htab->root.splt;
9673 sgot = htab->root.sgotplt;
9674 srel = htab->root.srelplt;
9675
9676 got_header_size = get_elf_backend_data (output_bfd)->got_header_size;
9677 plt_header_size = htab->plt_header_size;
9678 }
9679 BFD_ASSERT (splt != NULL && srel != NULL);
9680
9681 /* Fill in the entry in the procedure linkage table. */
9682 if (htab->symbian_p)
9683 {
9684 BFD_ASSERT (dynindx >= 0);
9685 put_arm_insn (htab, output_bfd,
9686 elf32_arm_symbian_plt_entry[0],
9687 splt->contents + root_plt->offset);
9688 bfd_put_32 (output_bfd,
9689 elf32_arm_symbian_plt_entry[1],
9690 splt->contents + root_plt->offset + 4);
9691
9692 /* Fill in the entry in the .rel.plt section. */
9693 rel.r_offset = (splt->output_section->vma
9694 + splt->output_offset
9695 + root_plt->offset + 4);
9696 rel.r_info = ELF32_R_INFO (dynindx, R_ARM_GLOB_DAT);
9697
9698 /* Get the index in the procedure linkage table which
9699 corresponds to this symbol. This is the index of this symbol
9700 in all the symbols for which we are making plt entries. The
9701 first entry in the procedure linkage table is reserved. */
9702 plt_index = ((root_plt->offset - plt_header_size)
9703 / htab->plt_entry_size);
9704 }
9705 else
9706 {
9707 bfd_vma got_offset, got_address, plt_address;
9708 bfd_vma got_displacement, initial_got_entry;
9709 bfd_byte * ptr;
9710
9711 BFD_ASSERT (sgot != NULL);
9712
9713 /* Get the offset into the .(i)got.plt table of the entry that
9714 corresponds to this function. */
9715 got_offset = (arm_plt->got_offset & -2);
9716
9717 /* Get the index in the procedure linkage table which
9718 corresponds to this symbol. This is the index of this symbol
9719 in all the symbols for which we are making plt entries.
9720 After the reserved .got.plt entries, all symbols appear in
9721 the same order as in .plt. */
7801f98f 9722 if (htab->fdpic_p)
4b24dd1a
AM		 9723 /* Function descriptor takes 8 bytes. */
9724 plt_index = (got_offset - got_header_size) / 8;
7801f98f 9725 else
4b24dd1a 9726 plt_index = (got_offset - got_header_size) / 4;
34e77a92
RS		 9727
9728 /* Calculate the address of the GOT entry. */
9729 got_address = (sgot->output_section->vma
9730 + sgot->output_offset
9731 + got_offset);
9732
9733 /* ...and the address of the PLT entry. */
9734 plt_address = (splt->output_section->vma
9735 + splt->output_offset
9736 + root_plt->offset);
9737
9738 ptr = splt->contents + root_plt->offset;
0e1862bb 9739 if (htab->vxworks_p && bfd_link_pic (info))
34e77a92
RS		 9740 {
9741 unsigned int i;
9742 bfd_vma val;
9743
9744 for (i = 0; i != htab->plt_entry_size / 4; i++, ptr += 4)
9745 {
9746 val = elf32_arm_vxworks_shared_plt_entry[i];
9747 if (i == 2)
9748 val |= got_address - sgot->output_section->vma;
9749 if (i == 5)
9750 val |= plt_index * RELOC_SIZE (htab);
9751 if (i == 2 || i == 5)
9752 bfd_put_32 (output_bfd, val, ptr);
9753 else
9754 put_arm_insn (htab, output_bfd, val, ptr);
9755 }
9756 }
9757 else if (htab->vxworks_p)
9758 {
9759 unsigned int i;
9760 bfd_vma val;
9761
9762 for (i = 0; i != htab->plt_entry_size / 4; i++, ptr += 4)
9763 {
9764 val = elf32_arm_vxworks_exec_plt_entry[i];
9765 if (i == 2)
9766 val |= got_address;
9767 if (i == 4)
9768 val |= 0xffffff & -((root_plt->offset + i * 4 + 8) >> 2);
9769 if (i == 5)
9770 val |= plt_index * RELOC_SIZE (htab);
9771 if (i == 2 || i == 5)
9772 bfd_put_32 (output_bfd, val, ptr);
9773 else
9774 put_arm_insn (htab, output_bfd, val, ptr);
9775 }
9776
9777 loc = (htab->srelplt2->contents
9778 + (plt_index * 2 + 1) * RELOC_SIZE (htab));
9779
9780 /* Create the .rela.plt.unloaded R_ARM_ABS32 relocation
9781 referencing the GOT for this PLT entry. */
9782 rel.r_offset = plt_address + 8;
9783 rel.r_info = ELF32_R_INFO (htab->root.hgot->indx, R_ARM_ABS32);
9784 rel.r_addend = got_offset;
9785 SWAP_RELOC_OUT (htab) (output_bfd, &rel, loc);
9786 loc += RELOC_SIZE (htab);
9787
9788 /* Create the R_ARM_ABS32 relocation referencing the
9789 beginning of the PLT for this GOT entry. */
9790 rel.r_offset = got_address;
9791 rel.r_info = ELF32_R_INFO (htab->root.hplt->indx, R_ARM_ABS32);
9792 rel.r_addend = 0;
9793 SWAP_RELOC_OUT (htab) (output_bfd, &rel, loc);
9794 }
b38cadfb
NC		 9795 else if (htab->nacl_p)
9796 {
9797 /* Calculate the displacement between the PLT slot and the
9798 common tail that's part of the special initial PLT slot. */
6034aab8 9799 int32_t tail_displacement
b38cadfb
NC		 9800 = ((splt->output_section->vma + splt->output_offset
9801 + ARM_NACL_PLT_TAIL_OFFSET)
9802 - (plt_address + htab->plt_entry_size + 4));
9803 BFD_ASSERT ((tail_displacement & 3) == 0);
9804 tail_displacement >>= 2;
9805
9806 BFD_ASSERT ((tail_displacement & 0xff000000) == 0
9807 || (-tail_displacement & 0xff000000) == 0);
9808
9809 /* Calculate the displacement between the PLT slot and the entry
9810 in the GOT. The offset accounts for the value produced by
9811 adding to pc in the penultimate instruction of the PLT stub. */
6034aab8 9812 got_displacement = (got_address
99059e56 9813 - (plt_address + htab->plt_entry_size));
b38cadfb
NC		 9814
9815 /* NaCl does not support interworking at all. */
9816 BFD_ASSERT (!elf32_arm_plt_needs_thumb_stub_p (info, arm_plt));
9817
9818 put_arm_insn (htab, output_bfd,
9819 elf32_arm_nacl_plt_entry[0]
9820 | arm_movw_immediate (got_displacement),
9821 ptr + 0);
9822 put_arm_insn (htab, output_bfd,
9823 elf32_arm_nacl_plt_entry[1]
9824 | arm_movt_immediate (got_displacement),
9825 ptr + 4);
9826 put_arm_insn (htab, output_bfd,
9827 elf32_arm_nacl_plt_entry[2],
9828 ptr + 8);
9829 put_arm_insn (htab, output_bfd,
9830 elf32_arm_nacl_plt_entry[3]
9831 | (tail_displacement & 0x00ffffff),
9832 ptr + 12);
9833 }
7801f98f
CL		 9834 else if (htab->fdpic_p)
9835 {
59029f57
CL		 9836 const bfd_vma *plt_entry = using_thumb_only(htab)
9837 ? elf32_arm_fdpic_thumb_plt_entry
9838 : elf32_arm_fdpic_plt_entry;
9839
7801f98f
CL		 9840 /* Fill-up Thumb stub if needed. */
9841 if (elf32_arm_plt_needs_thumb_stub_p (info, arm_plt))
9842 {
9843 put_thumb_insn (htab, output_bfd,
9844 elf32_arm_plt_thumb_stub[0], ptr - 4);
9845 put_thumb_insn (htab, output_bfd,
9846 elf32_arm_plt_thumb_stub[1], ptr - 2);
9847 }
59029f57
CL		 9848 /* As we are using 32 bit instructions even for the Thumb
9849 version, we have to use 'put_arm_insn' instead of
9850 'put_thumb_insn'. */
9851 put_arm_insn(htab, output_bfd, plt_entry[0], ptr + 0);
9852 put_arm_insn(htab, output_bfd, plt_entry[1], ptr + 4);
9853 put_arm_insn(htab, output_bfd, plt_entry[2], ptr + 8);
9854 put_arm_insn(htab, output_bfd, plt_entry[3], ptr + 12);
7801f98f
CL		 9855 bfd_put_32 (output_bfd, got_offset, ptr + 16);
9856
9857 if (!(info->flags & DF_BIND_NOW))
9858 {
9859 /* funcdesc_value_reloc_offset. */
9860 bfd_put_32 (output_bfd,
9861 htab->root.srelplt->reloc_count * RELOC_SIZE (htab),
9862 ptr + 20);
59029f57
CL		 9863 put_arm_insn(htab, output_bfd, plt_entry[6], ptr + 24);
9864 put_arm_insn(htab, output_bfd, plt_entry[7], ptr + 28);
9865 put_arm_insn(htab, output_bfd, plt_entry[8], ptr + 32);
9866 put_arm_insn(htab, output_bfd, plt_entry[9], ptr + 36);
7801f98f
CL		 9867 }
9868 }
57460bcf
NC		 9869 else if (using_thumb_only (htab))
9870 {
eed94f8f 9871 /* PR ld/16017: Generate thumb only PLT entries. */
469a3493 9872 if (!using_thumb2 (htab))
eed94f8f
NC		 9873 {
9874 /* FIXME: We ought to be able to generate thumb-1 PLT
9875 instructions... */
90b6238f 9876 _bfd_error_handler (_("%pB: warning: thumb-1 mode PLT generation not currently supported"),
eed94f8f
NC		 9877 output_bfd);
9878 return FALSE;
9879 }
57460bcf 9880
eed94f8f
NC		 9881 /* Calculate the displacement between the PLT slot and the entry in
9882 the GOT. The 12-byte offset accounts for the value produced by
9883 adding to pc in the 3rd instruction of the PLT stub. */
9884 got_displacement = got_address - (plt_address + 12);
9885
9886 /* As we are using 32 bit instructions we have to use 'put_arm_insn'
9887 instead of 'put_thumb_insn'. */
9888 put_arm_insn (htab, output_bfd,
9889 elf32_thumb2_plt_entry[0]
9890 | ((got_displacement & 0x000000ff) << 16)
9891 | ((got_displacement & 0x00000700) << 20)
9892 | ((got_displacement & 0x00000800) >> 1)
9893 | ((got_displacement & 0x0000f000) >> 12),
9894 ptr + 0);
9895 put_arm_insn (htab, output_bfd,
9896 elf32_thumb2_plt_entry[1]
9897 | ((got_displacement & 0x00ff0000) )
9898 | ((got_displacement & 0x07000000) << 4)
9899 | ((got_displacement & 0x08000000) >> 17)
9900 | ((got_displacement & 0xf0000000) >> 28),
9901 ptr + 4);
9902 put_arm_insn (htab, output_bfd,
9903 elf32_thumb2_plt_entry[2],
9904 ptr + 8);
9905 put_arm_insn (htab, output_bfd,
9906 elf32_thumb2_plt_entry[3],
9907 ptr + 12);
57460bcf 9908 }
34e77a92
RS		 9909 else
9910 {
9911 /* Calculate the displacement between the PLT slot and the
9912 entry in the GOT. The eight-byte offset accounts for the
9913 value produced by adding to pc in the first instruction
9914 of the PLT stub. */
9915 got_displacement = got_address - (plt_address + 8);
9916
34e77a92
RS		 9917 if (elf32_arm_plt_needs_thumb_stub_p (info, arm_plt))
9918 {
9919 put_thumb_insn (htab, output_bfd,
9920 elf32_arm_plt_thumb_stub[0], ptr - 4);
9921 put_thumb_insn (htab, output_bfd,
9922 elf32_arm_plt_thumb_stub[1], ptr - 2);
9923 }
9924
1db37fe6
YG		 9925 if (!elf32_arm_use_long_plt_entry)
9926 {
9927 BFD_ASSERT ((got_displacement & 0xf0000000) == 0);
9928
9929 put_arm_insn (htab, output_bfd,
9930 elf32_arm_plt_entry_short[0]
9931 | ((got_displacement & 0x0ff00000) >> 20),
9932 ptr + 0);
9933 put_arm_insn (htab, output_bfd,
9934 elf32_arm_plt_entry_short[1]
9935 | ((got_displacement & 0x000ff000) >> 12),
9936 ptr+ 4);
9937 put_arm_insn (htab, output_bfd,
9938 elf32_arm_plt_entry_short[2]
9939 | (got_displacement & 0x00000fff),
9940 ptr + 8);
34e77a92 9941#ifdef FOUR_WORD_PLT
1db37fe6 9942 bfd_put_32 (output_bfd, elf32_arm_plt_entry_short[3], ptr + 12);
34e77a92 9943#endif
1db37fe6
YG		 9944 }
9945 else
9946 {
9947 put_arm_insn (htab, output_bfd,
9948 elf32_arm_plt_entry_long[0]
9949 | ((got_displacement & 0xf0000000) >> 28),
9950 ptr + 0);
9951 put_arm_insn (htab, output_bfd,
9952 elf32_arm_plt_entry_long[1]
9953 | ((got_displacement & 0x0ff00000) >> 20),
9954 ptr + 4);
9955 put_arm_insn (htab, output_bfd,
9956 elf32_arm_plt_entry_long[2]
9957 | ((got_displacement & 0x000ff000) >> 12),
9958 ptr+ 8);
9959 put_arm_insn (htab, output_bfd,
9960 elf32_arm_plt_entry_long[3]
9961 | (got_displacement & 0x00000fff),
9962 ptr + 12);
9963 }
34e77a92
RS		 9964 }
9965
9966 /* Fill in the entry in the .rel(a).(i)plt section. */
9967 rel.r_offset = got_address;
9968 rel.r_addend = 0;
9969 if (dynindx == -1)
9970 {
9971 /* .igot.plt entries use IRELATIVE relocations against SYM_VALUE.
9972 The dynamic linker or static executable then calls SYM_VALUE
9973 to determine the correct run-time value of the .igot.plt entry. */
9974 rel.r_info = ELF32_R_INFO (0, R_ARM_IRELATIVE);
9975 initial_got_entry = sym_value;
9976 }
9977 else
9978 {
7801f98f
CL		 9979 /* For FDPIC we will have to resolve a R_ARM_FUNCDESC_VALUE
9980 used by PLT entry. */
9981 if (htab->fdpic_p)
9982 {
9983 rel.r_info = ELF32_R_INFO (dynindx, R_ARM_FUNCDESC_VALUE);
9984 initial_got_entry = 0;
9985 }
9986 else
9987 {
9988 rel.r_info = ELF32_R_INFO (dynindx, R_ARM_JUMP_SLOT);
9989 initial_got_entry = (splt->output_section->vma
9990 + splt->output_offset);
9991 }
34e77a92
RS		 9992 }
9993
9994 /* Fill in the entry in the global offset table. */
9995 bfd_put_32 (output_bfd, initial_got_entry,
9996 sgot->contents + got_offset);
7801f98f
CL		 9997
9998 if (htab->fdpic_p && !(info->flags & DF_BIND_NOW))
9999 {
10000 /* Setup initial funcdesc value. */
10001 /* FIXME: we don't support lazy binding because there is a
10002 race condition between both words getting written and
10003 some other thread attempting to read them. The ARM
10004 architecture does not have an atomic 64 bit load/store
10005 instruction that could be used to prevent it; it is
10006 recommended that threaded FDPIC applications run with the
10007 LD_BIND_NOW environment variable set. */
10008 bfd_put_32(output_bfd, plt_address + 0x18,
10009 sgot->contents + got_offset);
10010 bfd_put_32(output_bfd, -1 /*TODO*/,
10011 sgot->contents + got_offset + 4);
10012 }
34e77a92
RS		 10013 }
10014
aba8c3de
WN		 10015 if (dynindx == -1)
10016 elf32_arm_add_dynreloc (output_bfd, info, srel, &rel);
10017 else
10018 {
7801f98f
CL		 10019 if (htab->fdpic_p)
10020 {
10021 /* For FDPIC we put PLT relocationss into .rel.got when not
10022 lazy binding otherwise we put them in .rel.plt. For now,
10023 we don't support lazy binding so put it in .rel.got. */
10024 if (info->flags & DF_BIND_NOW)
10025 elf32_arm_add_dynreloc(output_bfd, info, htab->root.srelgot, &rel);
10026 else
10027 elf32_arm_add_dynreloc(output_bfd, info, htab->root.srelplt, &rel);
10028 }
10029 else
10030 {
10031 loc = srel->contents + plt_index * RELOC_SIZE (htab);
10032 SWAP_RELOC_OUT (htab) (output_bfd, &rel, loc);
10033 }
aba8c3de 10034 }
57460bcf
NC		 10035
10036 return TRUE;
34e77a92
RS		 10037}
10038
eb043451
PB		 10039/* Some relocations map to different relocations depending on the
10040 target. Return the real relocation. */
8029a119 10041
eb043451
PB		 10042static int
10043arm_real_reloc_type (struct elf32_arm_link_hash_table * globals,
10044 int r_type)
10045{
10046 switch (r_type)
10047 {
10048 case R_ARM_TARGET1:
10049 if (globals->target1_is_rel)
10050 return R_ARM_REL32;
10051 else
10052 return R_ARM_ABS32;
10053
10054 case R_ARM_TARGET2:
10055 return globals->target2_reloc;
10056
10057 default:
10058 return r_type;
10059 }
10060}
eb043451 10061
ba93b8ac
DJ		 10062/* Return the base VMA address which should be subtracted from real addresses
10063 when resolving @dtpoff relocation.
10064 This is PT_TLS segment p_vaddr. */
10065
10066static bfd_vma
10067dtpoff_base (struct bfd_link_info *info)
10068{
10069 /* If tls_sec is NULL, we should have signalled an error already. */
10070 if (elf_hash_table (info)->tls_sec == NULL)
10071 return 0;
10072 return elf_hash_table (info)->tls_sec->vma;
10073}
10074
10075/* Return the relocation value for @tpoff relocation
10076 if STT_TLS virtual address is ADDRESS. */
10077
10078static bfd_vma
10079tpoff (struct bfd_link_info *info, bfd_vma address)
10080{
10081 struct elf_link_hash_table *htab = elf_hash_table (info);
10082 bfd_vma base;
10083
10084 /* If tls_sec is NULL, we should have signalled an error already. */
10085 if (htab->tls_sec == NULL)
10086 return 0;
10087 base = align_power ((bfd_vma) TCB_SIZE, htab->tls_sec->alignment_power);
10088 return address - htab->tls_sec->vma + base;
10089}
10090
00a97672
RS		 10091/* Perform an R_ARM_ABS12 relocation on the field pointed to by DATA.
10092 VALUE is the relocation value. */
10093
10094static bfd_reloc_status_type
10095elf32_arm_abs12_reloc (bfd *abfd, void *data, bfd_vma value)
10096{
10097 if (value > 0xfff)
10098 return bfd_reloc_overflow;
10099
10100 value |= bfd_get_32 (abfd, data) & 0xfffff000;
10101 bfd_put_32 (abfd, value, data);
10102 return bfd_reloc_ok;
10103}
10104
0855e32b
NS		 10105/* Handle TLS relaxations. Relaxing is possible for symbols that use
10106 R_ARM_GOTDESC, R_ARM_{,THM_}TLS_CALL or
10107 R_ARM_{,THM_}TLS_DESCSEQ relocations, during a static link.
10108
10109 Return bfd_reloc_ok if we're done, bfd_reloc_continue if the caller
10110 is to then call final_link_relocate. Return other values in the
62672b10
NS		 10111 case of error.
10112
10113 FIXME:When --emit-relocs is in effect, we'll emit relocs describing
10114 the pre-relaxed code. It would be nice if the relocs were updated
10115 to match the optimization. */
0855e32b 10116
b38cadfb 10117static bfd_reloc_status_type
0855e32b 10118elf32_arm_tls_relax (struct elf32_arm_link_hash_table *globals,
b38cadfb 10119 bfd *input_bfd, asection *input_sec, bfd_byte *contents,
0855e32b
NS		 10120 Elf_Internal_Rela *rel, unsigned long is_local)
10121{
10122 unsigned long insn;
b38cadfb 10123
0855e32b
NS		 10124 switch (ELF32_R_TYPE (rel->r_info))
10125 {
10126 default:
10127 return bfd_reloc_notsupported;
b38cadfb 10128
0855e32b
NS		 10129 case R_ARM_TLS_GOTDESC:
10130 if (is_local)
10131 insn = 0;
10132 else
10133 {
10134 insn = bfd_get_32 (input_bfd, contents + rel->r_offset);
10135 if (insn & 1)
10136 insn -= 5; /* THUMB */
10137 else
10138 insn -= 8; /* ARM */
10139 }
10140 bfd_put_32 (input_bfd, insn, contents + rel->r_offset);
10141 return bfd_reloc_continue;
10142
10143 case R_ARM_THM_TLS_DESCSEQ:
10144 /* Thumb insn. */
10145 insn = bfd_get_16 (input_bfd, contents + rel->r_offset);
10146 if ((insn & 0xff78) == 0x4478) /* add rx, pc */
10147 {
10148 if (is_local)
10149 /* nop */
10150 bfd_put_16 (input_bfd, 0x46c0, contents + rel->r_offset);
10151 }
10152 else if ((insn & 0xffc0) == 0x6840) /* ldr rx,[ry,#4] */
10153 {
10154 if (is_local)
10155 /* nop */
10156 bfd_put_16 (input_bfd, 0x46c0, contents + rel->r_offset);
10157 else
10158 /* ldr rx,[ry] */
10159 bfd_put_16 (input_bfd, insn & 0xf83f, contents + rel->r_offset);
10160 }
10161 else if ((insn & 0xff87) == 0x4780) /* blx rx */
10162 {
10163 if (is_local)
10164 /* nop */
10165 bfd_put_16 (input_bfd, 0x46c0, contents + rel->r_offset);
10166 else
10167 /* mov r0, rx */
10168 bfd_put_16 (input_bfd, 0x4600 | (insn & 0x78),
10169 contents + rel->r_offset);
10170 }
10171 else
10172 {
10173 if ((insn & 0xf000) == 0xf000 || (insn & 0xf800) == 0xe800)
10174 /* It's a 32 bit instruction, fetch the rest of it for
10175 error generation. */
10176 insn = (insn << 16)
10177 | bfd_get_16 (input_bfd, contents + rel->r_offset + 2);
4eca0228 10178 _bfd_error_handler
695344c0 10179 /* xgettext:c-format */
2dcf00ce 10180 (_("%pB(%pA+%#" PRIx64 "): "
90b6238f
AM		 10181 "unexpected %s instruction '%#lx' in TLS trampoline"),
10182 input_bfd, input_sec, (uint64_t) rel->r_offset,
10183 "Thumb", insn);
0855e32b
NS		 10184 return bfd_reloc_notsupported;
10185 }
10186 break;
b38cadfb 10187
0855e32b
NS		 10188 case R_ARM_TLS_DESCSEQ:
10189 /* arm insn. */
10190 insn = bfd_get_32 (input_bfd, contents + rel->r_offset);
10191 if ((insn & 0xffff0ff0) == 0xe08f0000) /* add rx,pc,ry */
10192 {
10193 if (is_local)
10194 /* mov rx, ry */
10195 bfd_put_32 (input_bfd, 0xe1a00000 | (insn & 0xffff),
10196 contents + rel->r_offset);
10197 }
10198 else if ((insn & 0xfff00fff) == 0xe5900004) /* ldr rx,[ry,#4]*/
10199 {
10200 if (is_local)
10201 /* nop */
10202 bfd_put_32 (input_bfd, 0xe1a00000, contents + rel->r_offset);
10203 else
10204 /* ldr rx,[ry] */
10205 bfd_put_32 (input_bfd, insn & 0xfffff000,
10206 contents + rel->r_offset);
10207 }
10208 else if ((insn & 0xfffffff0) == 0xe12fff30) /* blx rx */
10209 {
10210 if (is_local)
10211 /* nop */
10212 bfd_put_32 (input_bfd, 0xe1a00000, contents + rel->r_offset);
10213 else
10214 /* mov r0, rx */
10215 bfd_put_32 (input_bfd, 0xe1a00000 | (insn & 0xf),
10216 contents + rel->r_offset);
10217 }
10218 else
10219 {
4eca0228 10220 _bfd_error_handler
695344c0 10221 /* xgettext:c-format */
2dcf00ce 10222 (_("%pB(%pA+%#" PRIx64 "): "
90b6238f
AM		 10223 "unexpected %s instruction '%#lx' in TLS trampoline"),
10224 input_bfd, input_sec, (uint64_t) rel->r_offset,
10225 "ARM", insn);
0855e32b
NS		 10226 return bfd_reloc_notsupported;
10227 }
10228 break;
10229
10230 case R_ARM_TLS_CALL:
10231 /* GD->IE relaxation, turn the instruction into 'nop' or
10232 'ldr r0, [pc,r0]' */
10233 insn = is_local ? 0xe1a00000 : 0xe79f0000;
10234 bfd_put_32 (input_bfd, insn, contents + rel->r_offset);
10235 break;
b38cadfb 10236
0855e32b 10237 case R_ARM_THM_TLS_CALL:
6a631e86 10238 /* GD->IE relaxation. */
0855e32b
NS		 10239 if (!is_local)
10240 /* add r0,pc; ldr r0, [r0] */
10241 insn = 0x44786800;
60a019a0 10242 else if (using_thumb2 (globals))
0855e32b
NS		 10243 /* nop.w */
10244 insn = 0xf3af8000;
10245 else
10246 /* nop; nop */
10247 insn = 0xbf00bf00;
b38cadfb 10248
0855e32b
NS		 10249 bfd_put_16 (input_bfd, insn >> 16, contents + rel->r_offset);
10250 bfd_put_16 (input_bfd, insn & 0xffff, contents + rel->r_offset + 2);
10251 break;
10252 }
10253 return bfd_reloc_ok;
10254}
10255
4962c51a
MS		 10256/* For a given value of n, calculate the value of G_n as required to
10257 deal with group relocations. We return it in the form of an
10258 encoded constant-and-rotation, together with the final residual. If n is
10259 specified as less than zero, then final_residual is filled with the
10260 input value and no further action is performed. */
10261
10262static bfd_vma
10263calculate_group_reloc_mask (bfd_vma value, int n, bfd_vma *final_residual)
10264{
10265 int current_n;
10266 bfd_vma g_n;
10267 bfd_vma encoded_g_n = 0;
10268 bfd_vma residual = value; /* Also known as Y_n. */
10269
10270 for (current_n = 0; current_n <= n; current_n++)
10271 {
10272 int shift;
10273
10274 /* Calculate which part of the value to mask. */
10275 if (residual == 0)
99059e56 10276 shift = 0;
4962c51a 10277 else
99059e56
RM		 10278 {
10279 int msb;
10280
10281 /* Determine the most significant bit in the residual and
10282 align the resulting value to a 2-bit boundary. */
10283 for (msb = 30; msb >= 0; msb -= 2)
10284 if (residual & (3 << msb))
10285 break;
10286
10287 /* The desired shift is now (msb - 6), or zero, whichever
10288 is the greater. */
10289 shift = msb - 6;
10290 if (shift < 0)
10291 shift = 0;
10292 }
4962c51a
MS		 10293
10294 /* Calculate g_n in 32-bit as well as encoded constant+rotation form. */
10295 g_n = residual & (0xff << shift);
10296 encoded_g_n = (g_n >> shift)
99059e56 10297 | ((g_n <= 0xff ? 0 : (32 - shift) / 2) << 8);
4962c51a
MS		 10298
10299 /* Calculate the residual for the next time around. */
10300 residual &= ~g_n;
10301 }
10302
10303 *final_residual = residual;
10304
10305 return encoded_g_n;
10306}
10307
10308/* Given an ARM instruction, determine whether it is an ADD or a SUB.
10309 Returns 1 if it is an ADD, -1 if it is a SUB, and 0 otherwise. */
906e58ca 10310
4962c51a 10311static int
906e58ca 10312identify_add_or_sub (bfd_vma insn)
4962c51a
MS		 10313{
10314 int opcode = insn & 0x1e00000;
10315
10316 if (opcode == 1 << 23) /* ADD */
10317 return 1;
10318
10319 if (opcode == 1 << 22) /* SUB */
10320 return -1;
10321
10322 return 0;
10323}
10324
252b5132 10325/* Perform a relocation as part of a final link. */
9b485d32 10326
252b5132 10327static bfd_reloc_status_type
07d6d2b8
AM		 10328elf32_arm_final_link_relocate (reloc_howto_type * howto,
10329 bfd * input_bfd,
10330 bfd * output_bfd,
10331 asection * input_section,
10332 bfd_byte * contents,
10333 Elf_Internal_Rela * rel,
10334 bfd_vma value,
10335 struct bfd_link_info * info,
10336 asection * sym_sec,
10337 const char * sym_name,
10338 unsigned char st_type,
10339 enum arm_st_branch_type branch_type,
0945cdfd 10340 struct elf_link_hash_entry * h,
07d6d2b8
AM		 10341 bfd_boolean * unresolved_reloc_p,
10342 char ** error_message)
10343{
10344 unsigned long r_type = howto->type;
10345 unsigned long r_symndx;
10346 bfd_byte * hit_data = contents + rel->r_offset;
10347 bfd_vma * local_got_offsets;
10348 bfd_vma * local_tlsdesc_gotents;
10349 asection * sgot;
10350 asection * splt;
10351 asection * sreloc = NULL;
10352 asection * srelgot;
10353 bfd_vma addend;
10354 bfd_signed_vma signed_addend;
10355 unsigned char dynreloc_st_type;
10356 bfd_vma dynreloc_value;
ba96a88f 10357 struct elf32_arm_link_hash_table * globals;
34e77a92 10358 struct elf32_arm_link_hash_entry *eh;
07d6d2b8
AM		 10359 union gotplt_union *root_plt;
10360 struct arm_plt_info *arm_plt;
10361 bfd_vma plt_offset;
10362 bfd_vma gotplt_offset;
10363 bfd_boolean has_iplt_entry;
10364 bfd_boolean resolved_to_zero;
f21f3fe0 10365
9c504268 10366 globals = elf32_arm_hash_table (info);
4dfe6ac6
NC		 10367 if (globals == NULL)
10368 return bfd_reloc_notsupported;
9c504268 10369
0ffa91dd 10370 BFD_ASSERT (is_arm_elf (input_bfd));
47aeb64c 10371 BFD_ASSERT (howto != NULL);
0ffa91dd
NC		 10372
10373 /* Some relocation types map to different relocations depending on the
9c504268 10374 target. We pick the right one here. */
eb043451 10375 r_type = arm_real_reloc_type (globals, r_type);
0855e32b
NS		 10376
10377 /* It is possible to have linker relaxations on some TLS access
10378 models. Update our information here. */
10379 r_type = elf32_arm_tls_transition (info, r_type, h);
10380
eb043451
PB		 10381 if (r_type != howto->type)
10382 howto = elf32_arm_howto_from_type (r_type);
9c504268 10383
34e77a92 10384 eh = (struct elf32_arm_link_hash_entry *) h;
362d30a1 10385 sgot = globals->root.sgot;
252b5132 10386 local_got_offsets = elf_local_got_offsets (input_bfd);
0855e32b
NS		 10387 local_tlsdesc_gotents = elf32_arm_local_tlsdesc_gotent (input_bfd);
10388
34e77a92
RS		 10389 if (globals->root.dynamic_sections_created)
10390 srelgot = globals->root.srelgot;
10391 else
10392 srelgot = NULL;
10393
252b5132
RH		 10394 r_symndx = ELF32_R_SYM (rel->r_info);
10395
4e7fd91e 10396 if (globals->use_rel)
ba96a88f 10397 {
4e7fd91e
PB		 10398 addend = bfd_get_32 (input_bfd, hit_data) & howto->src_mask;
10399
10400 if (addend & ((howto->src_mask + 1) >> 1))
10401 {
10402 signed_addend = -1;
10403 signed_addend &= ~ howto->src_mask;
10404 signed_addend |= addend;
10405 }
10406 else
10407 signed_addend = addend;
ba96a88f
NC		 10408 }
10409 else
4e7fd91e 10410 addend = signed_addend = rel->r_addend;
f21f3fe0 10411
39f21624
NC		 10412 /* ST_BRANCH_TO_ARM is nonsense to thumb-only targets when we
10413 are resolving a function call relocation. */
10414 if (using_thumb_only (globals)
10415 && (r_type == R_ARM_THM_CALL
10416 || r_type == R_ARM_THM_JUMP24)
10417 && branch_type == ST_BRANCH_TO_ARM)
10418 branch_type = ST_BRANCH_TO_THUMB;
10419
34e77a92
RS		 10420 /* Record the symbol information that should be used in dynamic
10421 relocations. */
10422 dynreloc_st_type = st_type;
10423 dynreloc_value = value;
10424 if (branch_type == ST_BRANCH_TO_THUMB)
10425 dynreloc_value |= 1;
10426
10427 /* Find out whether the symbol has a PLT. Set ST_VALUE, BRANCH_TYPE and
10428 VALUE appropriately for relocations that we resolve at link time. */
10429 has_iplt_entry = FALSE;
4ba2ef8f
TP		 10430 if (elf32_arm_get_plt_info (input_bfd, globals, eh, r_symndx, &root_plt,
10431 &arm_plt)
34e77a92
RS		 10432 && root_plt->offset != (bfd_vma) -1)
10433 {
10434 plt_offset = root_plt->offset;
10435 gotplt_offset = arm_plt->got_offset;
10436
10437 if (h == NULL || eh->is_iplt)
10438 {
10439 has_iplt_entry = TRUE;
10440 splt = globals->root.iplt;
10441
10442 /* Populate .iplt entries here, because not all of them will
10443 be seen by finish_dynamic_symbol. The lower bit is set if
10444 we have already populated the entry. */
10445 if (plt_offset & 1)
10446 plt_offset--;
10447 else
10448 {
57460bcf
NC		 10449 if (elf32_arm_populate_plt_entry (output_bfd, info, root_plt, arm_plt,
10450 -1, dynreloc_value))
10451 root_plt->offset |= 1;
10452 else
10453 return bfd_reloc_notsupported;
34e77a92
RS		 10454 }
10455
10456 /* Static relocations always resolve to the .iplt entry. */
10457 st_type = STT_FUNC;
10458 value = (splt->output_section->vma
10459 + splt->output_offset
10460 + plt_offset);
10461 branch_type = ST_BRANCH_TO_ARM;
10462
10463 /* If there are non-call relocations that resolve to the .iplt
10464 entry, then all dynamic ones must too. */
10465 if (arm_plt->noncall_refcount != 0)
10466 {
10467 dynreloc_st_type = st_type;
10468 dynreloc_value = value;
10469 }
10470 }
10471 else
10472 /* We populate the .plt entry in finish_dynamic_symbol. */
10473 splt = globals->root.splt;
10474 }
10475 else
10476 {
10477 splt = NULL;
10478 plt_offset = (bfd_vma) -1;
10479 gotplt_offset = (bfd_vma) -1;
10480 }
10481
95b03e4a
L		 10482 resolved_to_zero = (h != NULL
10483 && UNDEFWEAK_NO_DYNAMIC_RELOC (info, h));
10484
252b5132
RH		 10485 switch (r_type)
10486 {
10487 case R_ARM_NONE:
28a094c2
DJ		 10488 /* We don't need to find a value for this symbol. It's just a
10489 marker. */
10490 *unresolved_reloc_p = FALSE;
252b5132
RH		 10491 return bfd_reloc_ok;
10492
00a97672
RS		 10493 case R_ARM_ABS12:
10494 if (!globals->vxworks_p)
10495 return elf32_arm_abs12_reloc (input_bfd, hit_data, value + addend);
1a0670f3 10496 /* Fall through. */
00a97672 10497
252b5132
RH		 10498 case R_ARM_PC24:
10499 case R_ARM_ABS32:
bb224fc3 10500 case R_ARM_ABS32_NOI:
252b5132 10501 case R_ARM_REL32:
bb224fc3 10502 case R_ARM_REL32_NOI:
5b5bb741
PB		 10503 case R_ARM_CALL:
10504 case R_ARM_JUMP24:
dfc5f959 10505 case R_ARM_XPC25:
eb043451 10506 case R_ARM_PREL31:
7359ea65 10507 case R_ARM_PLT32:
7359ea65
DJ		 10508 /* Handle relocations which should use the PLT entry. ABS32/REL32
10509 will use the symbol's value, which may point to a PLT entry, but we
10510 don't need to handle that here. If we created a PLT entry, all
5fa9e92f
CL		 10511 branches in this object should go to it, except if the PLT is too
10512 far away, in which case a long branch stub should be inserted. */
bb224fc3 10513 if ((r_type != R_ARM_ABS32 && r_type != R_ARM_REL32
99059e56 10514 && r_type != R_ARM_ABS32_NOI && r_type != R_ARM_REL32_NOI
155d87d7
CL		 10515 && r_type != R_ARM_CALL
10516 && r_type != R_ARM_JUMP24
10517 && r_type != R_ARM_PLT32)
34e77a92 10518 && plt_offset != (bfd_vma) -1)
7359ea65 10519 {
34e77a92
RS		 10520 /* If we've created a .plt section, and assigned a PLT entry
10521 to this function, it must either be a STT_GNU_IFUNC reference
10522 or not be known to bind locally. In other cases, we should
10523 have cleared the PLT entry by now. */
10524 BFD_ASSERT (has_iplt_entry || !SYMBOL_CALLS_LOCAL (info, h));
7359ea65
DJ		 10525
10526 value = (splt->output_section->vma
10527 + splt->output_offset
34e77a92 10528 + plt_offset);
0945cdfd 10529 *unresolved_reloc_p = FALSE;
7359ea65
DJ		 10530 return _bfd_final_link_relocate (howto, input_bfd, input_section,
10531 contents, rel->r_offset, value,
00a97672 10532 rel->r_addend);
7359ea65
DJ		 10533 }
10534
67687978
PB		 10535 /* When generating a shared object or relocatable executable, these
10536 relocations are copied into the output file to be resolved at
10537 run time. */
0e1862bb 10538 if ((bfd_link_pic (info)
e8b09b87
CL		 10539 || globals->root.is_relocatable_executable
10540 || globals->fdpic_p)
7359ea65 10541 && (input_section->flags & SEC_ALLOC)
4dfe6ac6 10542 && !(globals->vxworks_p
3348747a
NS		 10543 && strcmp (input_section->output_section->name,
10544 ".tls_vars") == 0)
bb224fc3 10545 && ((r_type != R_ARM_REL32 && r_type != R_ARM_REL32_NOI)
ee06dc07 10546 || !SYMBOL_CALLS_LOCAL (info, h))
ca6b5f82
AM		 10547 && !(input_bfd == globals->stub_bfd
10548 && strstr (input_section->name, STUB_SUFFIX))
7359ea65 10549 && (h == NULL
95b03e4a
L		 10550 || (ELF_ST_VISIBILITY (h->other) == STV_DEFAULT
10551 && !resolved_to_zero)
7359ea65
DJ		 10552 || h->root.type != bfd_link_hash_undefweak)
10553 && r_type != R_ARM_PC24
5b5bb741
PB		 10554 && r_type != R_ARM_CALL
10555 && r_type != R_ARM_JUMP24
ee06dc07 10556 && r_type != R_ARM_PREL31
7359ea65 10557 && r_type != R_ARM_PLT32)
252b5132 10558 {
947216bf 10559 Elf_Internal_Rela outrel;
b34976b6 10560 bfd_boolean skip, relocate;
e8b09b87 10561 int isrofixup = 0;
f21f3fe0 10562
52db4ec2
JW		 10563 if ((r_type == R_ARM_REL32 || r_type == R_ARM_REL32_NOI)
10564 && !h->def_regular)
10565 {
10566 char *v = _("shared object");
10567
0e1862bb 10568 if (bfd_link_executable (info))
52db4ec2
JW		 10569 v = _("PIE executable");
10570
4eca0228 10571 _bfd_error_handler
871b3ab2 10572 (_("%pB: relocation %s against external or undefined symbol `%s'"
52db4ec2
JW		 10573 " can not be used when making a %s; recompile with -fPIC"), input_bfd,
10574 elf32_arm_howto_table_1[r_type].name, h->root.root.string, v);
10575 return bfd_reloc_notsupported;
10576 }
10577
0945cdfd
DJ		 10578 *unresolved_reloc_p = FALSE;
10579
34e77a92 10580 if (sreloc == NULL && globals->root.dynamic_sections_created)
252b5132 10581 {
83bac4b0
NC		 10582 sreloc = _bfd_elf_get_dynamic_reloc_section (input_bfd, input_section,
10583 ! globals->use_rel);
f21f3fe0 10584
83bac4b0 10585 if (sreloc == NULL)
252b5132 10586 return bfd_reloc_notsupported;
252b5132 10587 }
f21f3fe0 10588
b34976b6
AM		 10589 skip = FALSE;
10590 relocate = FALSE;
f21f3fe0 10591
00a97672 10592 outrel.r_addend = addend;
c629eae0
JJ		 10593 outrel.r_offset =
10594 _bfd_elf_section_offset (output_bfd, info, input_section,
10595 rel->r_offset);
10596 if (outrel.r_offset == (bfd_vma) -1)
b34976b6 10597 skip = TRUE;
0bb2d96a 10598 else if (outrel.r_offset == (bfd_vma) -2)
b34976b6 10599 skip = TRUE, relocate = TRUE;
252b5132
RH		 10600 outrel.r_offset += (input_section->output_section->vma
10601 + input_section->output_offset);
f21f3fe0 10602
252b5132 10603 if (skip)
0bb2d96a 10604 memset (&outrel, 0, sizeof outrel);
5e681ec4
PB		 10605 else if (h != NULL
10606 && h->dynindx != -1
0e1862bb 10607 && (!bfd_link_pic (info)
1dcb9720
JW		 10608 || !(bfd_link_pie (info)
10609 || SYMBOLIC_BIND (info, h))
f5385ebf 10610 || !h->def_regular))
5e681ec4 10611 outrel.r_info = ELF32_R_INFO (h->dynindx, r_type);
252b5132
RH		 10612 else
10613 {
a16385dc
MM		 10614 int symbol;
10615
5e681ec4 10616 /* This symbol is local, or marked to become local. */
e8b09b87
CL		 10617 BFD_ASSERT (r_type == R_ARM_ABS32 || r_type == R_ARM_ABS32_NOI
10618 || (globals->fdpic_p && !bfd_link_pic(info)));
a16385dc 10619 if (globals->symbian_p)
6366ff1e 10620 {
74541ad4
AM		 10621 asection *osec;
10622
6366ff1e
MM		 10623 /* On Symbian OS, the data segment and text segement
10624 can be relocated independently. Therefore, we
10625 must indicate the segment to which this
10626 relocation is relative. The BPABI allows us to
10627 use any symbol in the right segment; we just use
10628 the section symbol as it is convenient. (We
10629 cannot use the symbol given by "h" directly as it
74541ad4
AM		 10630 will not appear in the dynamic symbol table.)
10631
10632 Note that the dynamic linker ignores the section
10633 symbol value, so we don't subtract osec->vma
10634 from the emitted reloc addend. */
10dbd1f3 10635 if (sym_sec)
74541ad4 10636 osec = sym_sec->output_section;
10dbd1f3 10637 else
74541ad4
AM		 10638 osec = input_section->output_section;
10639 symbol = elf_section_data (osec)->dynindx;
10640 if (symbol == 0)
10641 {
10642 struct elf_link_hash_table *htab = elf_hash_table (info);
10643
10644 if ((osec->flags & SEC_READONLY) == 0
10645 && htab->data_index_section != NULL)
10646 osec = htab->data_index_section;
10647 else
10648 osec = htab->text_index_section;
10649 symbol = elf_section_data (osec)->dynindx;
10650 }
6366ff1e
MM		 10651 BFD_ASSERT (symbol != 0);
10652 }
a16385dc
MM		 10653 else
10654 /* On SVR4-ish systems, the dynamic loader cannot
10655 relocate the text and data segments independently,
10656 so the symbol does not matter. */
10657 symbol = 0;
34e77a92
RS		 10658 if (dynreloc_st_type == STT_GNU_IFUNC)
10659 /* We have an STT_GNU_IFUNC symbol that doesn't resolve
10660 to the .iplt entry. Instead, every non-call reference
10661 must use an R_ARM_IRELATIVE relocation to obtain the
10662 correct run-time address. */
10663 outrel.r_info = ELF32_R_INFO (symbol, R_ARM_IRELATIVE);
e8b09b87
CL		 10664 else if (globals->fdpic_p && !bfd_link_pic(info))
10665 isrofixup = 1;
34e77a92
RS		 10666 else
10667 outrel.r_info = ELF32_R_INFO (symbol, R_ARM_RELATIVE);
00a97672
RS		 10668 if (globals->use_rel)
10669 relocate = TRUE;
10670 else
34e77a92 10671 outrel.r_addend += dynreloc_value;
252b5132 10672 }
f21f3fe0 10673
e8b09b87
CL		 10674 if (isrofixup)
10675 arm_elf_add_rofixup(output_bfd, globals->srofixup, outrel.r_offset);
10676 else
10677 elf32_arm_add_dynreloc (output_bfd, info, sreloc, &outrel);
9a5aca8c 10678
f21f3fe0 10679 /* If this reloc is against an external symbol, we do not want to
252b5132 10680 fiddle with the addend. Otherwise, we need to include the symbol
9b485d32 10681 value so that it becomes an addend for the dynamic reloc. */
252b5132
RH		 10682 if (! relocate)
10683 return bfd_reloc_ok;
9a5aca8c 10684
f21f3fe0 10685 return _bfd_final_link_relocate (howto, input_bfd, input_section,
34e77a92
RS		 10686 contents, rel->r_offset,
10687 dynreloc_value, (bfd_vma) 0);
252b5132
RH		 10688 }
10689 else switch (r_type)
10690 {
00a97672
RS		 10691 case R_ARM_ABS12:
10692 return elf32_arm_abs12_reloc (input_bfd, hit_data, value + addend);
10693
dfc5f959 10694 case R_ARM_XPC25: /* Arm BLX instruction. */
5b5bb741
PB		 10695 case R_ARM_CALL:
10696 case R_ARM_JUMP24:
8029a119 10697 case R_ARM_PC24: /* Arm B/BL instruction. */
7359ea65 10698 case R_ARM_PLT32:
906e58ca 10699 {
906e58ca
NC		 10700 struct elf32_arm_stub_hash_entry *stub_entry = NULL;
10701
dfc5f959 10702 if (r_type == R_ARM_XPC25)
252b5132 10703 {
dfc5f959
NC		 10704 /* Check for Arm calling Arm function. */
10705 /* FIXME: Should we translate the instruction into a BL
10706 instruction instead ? */
35fc36a8 10707 if (branch_type != ST_BRANCH_TO_THUMB)
4eca0228 10708 _bfd_error_handler
90b6238f
AM		 10709 (_("\%pB: warning: %s BLX instruction targets"
10710 " %s function '%s'"),
10711 input_bfd, "ARM",
10712 "ARM", h ? h->root.root.string : "(local)");
dfc5f959 10713 }
155d87d7 10714 else if (r_type == R_ARM_PC24)
dfc5f959
NC		 10715 {
10716 /* Check for Arm calling Thumb function. */
35fc36a8 10717 if (branch_type == ST_BRANCH_TO_THUMB)
dfc5f959 10718 {
f2a9dd69
DJ		 10719 if (elf32_arm_to_thumb_stub (info, sym_name, input_bfd,
10720 output_bfd, input_section,
10721 hit_data, sym_sec, rel->r_offset,
10722 signed_addend, value,
10723 error_message))
10724 return bfd_reloc_ok;
10725 else
10726 return bfd_reloc_dangerous;
dfc5f959 10727 }
252b5132 10728 }
ba96a88f 10729
906e58ca 10730 /* Check if a stub has to be inserted because the
8029a119 10731 destination is too far or we are changing mode. */
155d87d7
CL		 10732 if ( r_type == R_ARM_CALL
10733 || r_type == R_ARM_JUMP24
10734 || r_type == R_ARM_PLT32)
906e58ca 10735 {
fe33d2fa
CL		 10736 enum elf32_arm_stub_type stub_type = arm_stub_none;
10737 struct elf32_arm_link_hash_entry *hash;
10738
10739 hash = (struct elf32_arm_link_hash_entry *) h;
10740 stub_type = arm_type_of_stub (info, input_section, rel,
34e77a92
RS		 10741 st_type, &branch_type,
10742 hash, value, sym_sec,
fe33d2fa 10743 input_bfd, sym_name);
5fa9e92f 10744
fe33d2fa 10745 if (stub_type != arm_stub_none)
906e58ca
NC		 10746 {
10747 /* The target is out of reach, so redirect the
10748 branch to the local stub for this function. */
906e58ca
NC		 10749 stub_entry = elf32_arm_get_stub_entry (input_section,
10750 sym_sec, h,
fe33d2fa
CL		 10751 rel, globals,
10752 stub_type);
9cd3e4e5
NC		 10753 {
10754 if (stub_entry != NULL)
10755 value = (stub_entry->stub_offset
10756 + stub_entry->stub_sec->output_offset
10757 + stub_entry->stub_sec->output_section->vma);
10758
10759 if (plt_offset != (bfd_vma) -1)
10760 *unresolved_reloc_p = FALSE;
10761 }
906e58ca 10762 }
fe33d2fa
CL		 10763 else
10764 {
10765 /* If the call goes through a PLT entry, make sure to
10766 check distance to the right destination address. */
34e77a92 10767 if (plt_offset != (bfd_vma) -1)
fe33d2fa
CL		 10768 {
10769 value = (splt->output_section->vma
10770 + splt->output_offset
34e77a92 10771 + plt_offset);
fe33d2fa
CL		 10772 *unresolved_reloc_p = FALSE;
10773 /* The PLT entry is in ARM mode, regardless of the
10774 target function. */
35fc36a8 10775 branch_type = ST_BRANCH_TO_ARM;
fe33d2fa
CL		 10776 }
10777 }
906e58ca
NC		 10778 }
10779
dea514f5
PB		 10780 /* The ARM ELF ABI says that this reloc is computed as: S - P + A
10781 where:
10782 S is the address of the symbol in the relocation.
10783 P is address of the instruction being relocated.
10784 A is the addend (extracted from the instruction) in bytes.
10785
10786 S is held in 'value'.
10787 P is the base address of the section containing the
10788 instruction plus the offset of the reloc into that
10789 section, ie:
10790 (input_section->output_section->vma +
10791 input_section->output_offset +
10792 rel->r_offset).
10793 A is the addend, converted into bytes, ie:
10794 (signed_addend * 4)
10795
10796 Note: None of these operations have knowledge of the pipeline
10797 size of the processor, thus it is up to the assembler to
10798 encode this information into the addend. */
10799 value -= (input_section->output_section->vma
10800 + input_section->output_offset);
10801 value -= rel->r_offset;
4e7fd91e
PB		 10802 if (globals->use_rel)
10803 value += (signed_addend << howto->size);
10804 else
10805 /* RELA addends do not have to be adjusted by howto->size. */
10806 value += signed_addend;
23080146 10807
dcb5e6e6
NC		 10808 signed_addend = value;
10809 signed_addend >>= howto->rightshift;
9a5aca8c 10810
5ab79981 10811 /* A branch to an undefined weak symbol is turned into a jump to
ffcb4889 10812 the next instruction unless a PLT entry will be created.
77b4f08f 10813 Do the same for local undefined symbols (but not for STN_UNDEF).
cd1dac3d
DG		 10814 The jump to the next instruction is optimized as a NOP depending
10815 on the architecture. */
ffcb4889 10816 if (h ? (h->root.type == bfd_link_hash_undefweak
34e77a92 10817 && plt_offset == (bfd_vma) -1)
77b4f08f 10818 : r_symndx != STN_UNDEF && bfd_is_und_section (sym_sec))
5ab79981 10819 {
cd1dac3d
DG		 10820 value = (bfd_get_32 (input_bfd, hit_data) & 0xf0000000);
10821
10822 if (arch_has_arm_nop (globals))
10823 value |= 0x0320f000;
10824 else
10825 value |= 0x01a00000; /* Using pre-UAL nop: mov r0, r0. */
5ab79981
PB		 10826 }
10827 else
59f2c4e7 10828 {
9b485d32 10829 /* Perform a signed range check. */
dcb5e6e6 10830 if ( signed_addend > ((bfd_signed_vma) (howto->dst_mask >> 1))
59f2c4e7
NC		 10831 || signed_addend < - ((bfd_signed_vma) ((howto->dst_mask + 1) >> 1)))
10832 return bfd_reloc_overflow;
9a5aca8c 10833
5ab79981 10834 addend = (value & 2);
39b41c9c 10835
5ab79981
PB		 10836 value = (signed_addend & howto->dst_mask)
10837 | (bfd_get_32 (input_bfd, hit_data) & (~ howto->dst_mask));
39b41c9c 10838
5ab79981
PB		 10839 if (r_type == R_ARM_CALL)
10840 {
155d87d7 10841 /* Set the H bit in the BLX instruction. */
35fc36a8 10842 if (branch_type == ST_BRANCH_TO_THUMB)
155d87d7
CL		 10843 {
10844 if (addend)
10845 value |= (1 << 24);
10846 else
10847 value &= ~(bfd_vma)(1 << 24);
10848 }
10849
5ab79981 10850 /* Select the correct instruction (BL or BLX). */
906e58ca 10851 /* Only if we are not handling a BL to a stub. In this
8029a119 10852 case, mode switching is performed by the stub. */
35fc36a8 10853 if (branch_type == ST_BRANCH_TO_THUMB && !stub_entry)
5ab79981 10854 value |= (1 << 28);
63e1a0fc 10855 else if (stub_entry || branch_type != ST_BRANCH_UNKNOWN)
5ab79981
PB		 10856 {
10857 value &= ~(bfd_vma)(1 << 28);
10858 value |= (1 << 24);
10859 }
39b41c9c
PB		 10860 }
10861 }
906e58ca 10862 }
252b5132 10863 break;
f21f3fe0 10864
252b5132
RH		 10865 case R_ARM_ABS32:
10866 value += addend;
35fc36a8 10867 if (branch_type == ST_BRANCH_TO_THUMB)
252b5132
RH		 10868 value |= 1;
10869 break;
f21f3fe0 10870
bb224fc3
MS		 10871 case R_ARM_ABS32_NOI:
10872 value += addend;
10873 break;
10874
252b5132 10875 case R_ARM_REL32:
a8bc6c78 10876 value += addend;
35fc36a8 10877 if (branch_type == ST_BRANCH_TO_THUMB)
a8bc6c78 10878 value |= 1;
252b5132 10879 value -= (input_section->output_section->vma
62efb346 10880 + input_section->output_offset + rel->r_offset);
252b5132 10881 break;
eb043451 10882
bb224fc3
MS		 10883 case R_ARM_REL32_NOI:
10884 value += addend;
10885 value -= (input_section->output_section->vma
10886 + input_section->output_offset + rel->r_offset);
10887 break;
10888
eb043451
PB		 10889 case R_ARM_PREL31:
10890 value -= (input_section->output_section->vma
10891 + input_section->output_offset + rel->r_offset);
10892 value += signed_addend;
10893 if (! h || h->root.type != bfd_link_hash_undefweak)
10894 {
8029a119 10895 /* Check for overflow. */
eb043451
PB		 10896 if ((value ^ (value >> 1)) & (1 << 30))
10897 return bfd_reloc_overflow;
10898 }
10899 value &= 0x7fffffff;
10900 value |= (bfd_get_32 (input_bfd, hit_data) & 0x80000000);
35fc36a8 10901 if (branch_type == ST_BRANCH_TO_THUMB)
eb043451
PB		 10902 value |= 1;
10903 break;
252b5132 10904 }
f21f3fe0 10905
252b5132
RH		 10906 bfd_put_32 (input_bfd, value, hit_data);
10907 return bfd_reloc_ok;
10908
10909 case R_ARM_ABS8:
fd0fd00c
MJ		 10910 /* PR 16202: Refectch the addend using the correct size. */
10911 if (globals->use_rel)
10912 addend = bfd_get_8 (input_bfd, hit_data);
252b5132 10913 value += addend;
4e67d4ca
DG		 10914
10915 /* There is no way to tell whether the user intended to use a signed or
10916 unsigned addend. When checking for overflow we accept either,
10917 as specified by the AAELF. */
10918 if ((long) value > 0xff || (long) value < -0x80)
252b5132
RH		 10919 return bfd_reloc_overflow;
10920
10921 bfd_put_8 (input_bfd, value, hit_data);
10922 return bfd_reloc_ok;
10923
10924 case R_ARM_ABS16:
fd0fd00c
MJ		 10925 /* PR 16202: Refectch the addend using the correct size. */
10926 if (globals->use_rel)
10927 addend = bfd_get_16 (input_bfd, hit_data);
252b5132
RH		 10928 value += addend;
10929
4e67d4ca
DG		 10930 /* See comment for R_ARM_ABS8. */
10931 if ((long) value > 0xffff || (long) value < -0x8000)
252b5132
RH		 10932 return bfd_reloc_overflow;
10933
10934 bfd_put_16 (input_bfd, value, hit_data);
10935 return bfd_reloc_ok;
10936
252b5132 10937 case R_ARM_THM_ABS5:
9b485d32 10938 /* Support ldr and str instructions for the thumb. */
4e7fd91e
PB		 10939 if (globals->use_rel)
10940 {
10941 /* Need to refetch addend. */
10942 addend = bfd_get_16 (input_bfd, hit_data) & howto->src_mask;
10943 /* ??? Need to determine shift amount from operand size. */
10944 addend >>= howto->rightshift;
10945 }
252b5132
RH		 10946 value += addend;
10947
10948 /* ??? Isn't value unsigned? */
10949 if ((long) value > 0x1f || (long) value < -0x10)
10950 return bfd_reloc_overflow;
10951
10952 /* ??? Value needs to be properly shifted into place first. */
10953 value |= bfd_get_16 (input_bfd, hit_data) & 0xf83f;
10954 bfd_put_16 (input_bfd, value, hit_data);
10955 return bfd_reloc_ok;
10956
2cab6cc3
MS		 10957 case R_ARM_THM_ALU_PREL_11_0:
10958 /* Corresponds to: addw.w reg, pc, #offset (and similarly for subw). */
10959 {
10960 bfd_vma insn;
10961 bfd_signed_vma relocation;
10962
10963 insn = (bfd_get_16 (input_bfd, hit_data) << 16)
99059e56 10964 | bfd_get_16 (input_bfd, hit_data + 2);
2cab6cc3 10965
99059e56
RM		 10966 if (globals->use_rel)
10967 {
10968 signed_addend = (insn & 0xff) | ((insn & 0x7000) >> 4)
10969 | ((insn & (1 << 26)) >> 15);
10970 if (insn & 0xf00000)
10971 signed_addend = -signed_addend;
10972 }
2cab6cc3
MS		 10973
10974 relocation = value + signed_addend;
79f08007 10975 relocation -= Pa (input_section->output_section->vma
99059e56
RM		 10976 + input_section->output_offset
10977 + rel->r_offset);
2cab6cc3 10978
8c65b54f
CS		 10979 /* PR 21523: Use an absolute value. The user of this reloc will
10980 have already selected an ADD or SUB insn appropriately. */
453f8e1e 10981 value = llabs (relocation);
2cab6cc3 10982
99059e56
RM		 10983 if (value >= 0x1000)
10984 return bfd_reloc_overflow;
2cab6cc3 10985
e645cf40
AG		 10986 /* Destination is Thumb. Force bit 0 to 1 to reflect this. */
10987 if (branch_type == ST_BRANCH_TO_THUMB)
10988 value |= 1;
10989
2cab6cc3 10990 insn = (insn & 0xfb0f8f00) | (value & 0xff)
99059e56
RM		 10991 | ((value & 0x700) << 4)
10992 | ((value & 0x800) << 15);
10993 if (relocation < 0)
10994 insn |= 0xa00000;
2cab6cc3
MS		 10995
10996 bfd_put_16 (input_bfd, insn >> 16, hit_data);
10997 bfd_put_16 (input_bfd, insn & 0xffff, hit_data + 2);
10998
99059e56 10999 return bfd_reloc_ok;
2cab6cc3
MS		 11000 }
11001
e1ec24c6
NC		 11002 case R_ARM_THM_PC8:
11003 /* PR 10073: This reloc is not generated by the GNU toolchain,
11004 but it is supported for compatibility with third party libraries
11005 generated by other compilers, specifically the ARM/IAR. */
11006 {
11007 bfd_vma insn;
11008 bfd_signed_vma relocation;
11009
11010 insn = bfd_get_16 (input_bfd, hit_data);
11011
99059e56 11012 if (globals->use_rel)
79f08007 11013 addend = ((((insn & 0x00ff) << 2) + 4) & 0x3ff) -4;
e1ec24c6
NC		 11014
11015 relocation = value + addend;
79f08007 11016 relocation -= Pa (input_section->output_section->vma
99059e56
RM		 11017 + input_section->output_offset
11018 + rel->r_offset);
e1ec24c6 11019
b6518b38 11020 value = relocation;
e1ec24c6
NC		 11021
11022 /* We do not check for overflow of this reloc. Although strictly
11023 speaking this is incorrect, it appears to be necessary in order
11024 to work with IAR generated relocs. Since GCC and GAS do not
11025 generate R_ARM_THM_PC8 relocs, the lack of a check should not be
11026 a problem for them. */
11027 value &= 0x3fc;
11028
11029 insn = (insn & 0xff00) | (value >> 2);
11030
11031 bfd_put_16 (input_bfd, insn, hit_data);
11032
99059e56 11033 return bfd_reloc_ok;
e1ec24c6
NC		 11034 }
11035
2cab6cc3
MS		 11036 case R_ARM_THM_PC12:
11037 /* Corresponds to: ldr.w reg, [pc, #offset]. */
11038 {
11039 bfd_vma insn;
11040 bfd_signed_vma relocation;
11041
11042 insn = (bfd_get_16 (input_bfd, hit_data) << 16)
99059e56 11043 | bfd_get_16 (input_bfd, hit_data + 2);
2cab6cc3 11044
99059e56
RM		 11045 if (globals->use_rel)
11046 {
11047 signed_addend = insn & 0xfff;
11048 if (!(insn & (1 << 23)))
11049 signed_addend = -signed_addend;
11050 }
2cab6cc3
MS		 11051
11052 relocation = value + signed_addend;
79f08007 11053 relocation -= Pa (input_section->output_section->vma
99059e56
RM		 11054 + input_section->output_offset
11055 + rel->r_offset);
2cab6cc3 11056
b6518b38 11057 value = relocation;
2cab6cc3 11058
99059e56
RM		 11059 if (value >= 0x1000)
11060 return bfd_reloc_overflow;
2cab6cc3
MS		 11061
11062 insn = (insn & 0xff7ff000) | value;
99059e56
RM		 11063 if (relocation >= 0)
11064 insn |= (1 << 23);
2cab6cc3
MS		 11065
11066 bfd_put_16 (input_bfd, insn >> 16, hit_data);
11067 bfd_put_16 (input_bfd, insn & 0xffff, hit_data + 2);
11068
99059e56 11069 return bfd_reloc_ok;
2cab6cc3
MS		 11070 }
11071
dfc5f959 11072 case R_ARM_THM_XPC22:
c19d1205 11073 case R_ARM_THM_CALL:
bd97cb95 11074 case R_ARM_THM_JUMP24:
dfc5f959 11075 /* Thumb BL (branch long instruction). */
252b5132 11076 {
b34976b6 11077 bfd_vma relocation;
99059e56 11078 bfd_vma reloc_sign;
b34976b6
AM		 11079 bfd_boolean overflow = FALSE;
11080 bfd_vma upper_insn = bfd_get_16 (input_bfd, hit_data);
11081 bfd_vma lower_insn = bfd_get_16 (input_bfd, hit_data + 2);
e95de063
MS		 11082 bfd_signed_vma reloc_signed_max;
11083 bfd_signed_vma reloc_signed_min;
b34976b6 11084 bfd_vma check;
252b5132 11085 bfd_signed_vma signed_check;
e95de063 11086 int bitsize;
cd1dac3d 11087 const int thumb2 = using_thumb2 (globals);
5e866f5a 11088 const int thumb2_bl = using_thumb2_bl (globals);
252b5132 11089
5ab79981 11090 /* A branch to an undefined weak symbol is turned into a jump to
cd1dac3d
DG		 11091 the next instruction unless a PLT entry will be created.
11092 The jump to the next instruction is optimized as a NOP.W for
11093 Thumb-2 enabled architectures. */
19540007 11094 if (h && h->root.type == bfd_link_hash_undefweak
34e77a92 11095 && plt_offset == (bfd_vma) -1)
5ab79981 11096 {
60a019a0 11097 if (thumb2)
cd1dac3d
DG		 11098 {
11099 bfd_put_16 (input_bfd, 0xf3af, hit_data);
11100 bfd_put_16 (input_bfd, 0x8000, hit_data + 2);
11101 }
11102 else
11103 {
11104 bfd_put_16 (input_bfd, 0xe000, hit_data);
11105 bfd_put_16 (input_bfd, 0xbf00, hit_data + 2);
11106 }
5ab79981
PB		 11107 return bfd_reloc_ok;
11108 }
11109
e95de063 11110 /* Fetch the addend. We use the Thumb-2 encoding (backwards compatible
99059e56 11111 with Thumb-1) involving the J1 and J2 bits. */
4e7fd91e
PB		 11112 if (globals->use_rel)
11113 {
99059e56
RM		 11114 bfd_vma s = (upper_insn & (1 << 10)) >> 10;
11115 bfd_vma upper = upper_insn & 0x3ff;
11116 bfd_vma lower = lower_insn & 0x7ff;
e95de063
MS		 11117 bfd_vma j1 = (lower_insn & (1 << 13)) >> 13;
11118 bfd_vma j2 = (lower_insn & (1 << 11)) >> 11;
99059e56
RM		 11119 bfd_vma i1 = j1 ^ s ? 0 : 1;
11120 bfd_vma i2 = j2 ^ s ? 0 : 1;
e95de063 11121
99059e56
RM		 11122 addend = (i1 << 23) | (i2 << 22) | (upper << 12) | (lower << 1);
11123 /* Sign extend. */
11124 addend = (addend | ((s ? 0 : 1) << 24)) - (1 << 24);
e95de063 11125
4e7fd91e
PB		 11126 signed_addend = addend;
11127 }
cb1afa5c 11128
dfc5f959
NC		 11129 if (r_type == R_ARM_THM_XPC22)
11130 {
11131 /* Check for Thumb to Thumb call. */
11132 /* FIXME: Should we translate the instruction into a BL
11133 instruction instead ? */
35fc36a8 11134 if (branch_type == ST_BRANCH_TO_THUMB)
4eca0228 11135 _bfd_error_handler
90b6238f
AM		 11136 (_("%pB: warning: %s BLX instruction targets"
11137 " %s function '%s'"),
11138 input_bfd, "Thumb",
11139 "Thumb", h ? h->root.root.string : "(local)");
dfc5f959
NC		 11140 }
11141 else
252b5132 11142 {
dfc5f959
NC		 11143 /* If it is not a call to Thumb, assume call to Arm.
11144 If it is a call relative to a section name, then it is not a
b7693d02
DJ		 11145 function call at all, but rather a long jump. Calls through
11146 the PLT do not require stubs. */
34e77a92 11147 if (branch_type == ST_BRANCH_TO_ARM && plt_offset == (bfd_vma) -1)
dfc5f959 11148 {
bd97cb95 11149 if (globals->use_blx && r_type == R_ARM_THM_CALL)
39b41c9c
PB		 11150 {
11151 /* Convert BL to BLX. */
11152 lower_insn = (lower_insn & ~0x1000) | 0x0800;
11153 }
155d87d7
CL		 11154 else if (( r_type != R_ARM_THM_CALL)
11155 && (r_type != R_ARM_THM_JUMP24))
8029a119
NC		 11156 {
11157 if (elf32_thumb_to_arm_stub
11158 (info, sym_name, input_bfd, output_bfd, input_section,
11159 hit_data, sym_sec, rel->r_offset, signed_addend, value,
11160 error_message))
11161 return bfd_reloc_ok;
11162 else
11163 return bfd_reloc_dangerous;
11164 }
da5938a2 11165 }
35fc36a8
RS		 11166 else if (branch_type == ST_BRANCH_TO_THUMB
11167 && globals->use_blx
bd97cb95 11168 && r_type == R_ARM_THM_CALL)
39b41c9c
PB		 11169 {
11170 /* Make sure this is a BL. */
11171 lower_insn |= 0x1800;
11172 }
252b5132 11173 }
f21f3fe0 11174
fe33d2fa 11175 enum elf32_arm_stub_type stub_type = arm_stub_none;
155d87d7 11176 if (r_type == R_ARM_THM_CALL || r_type == R_ARM_THM_JUMP24)
906e58ca
NC		 11177 {
11178 /* Check if a stub has to be inserted because the destination
8029a119 11179 is too far. */
fe33d2fa
CL		 11180 struct elf32_arm_stub_hash_entry *stub_entry;
11181 struct elf32_arm_link_hash_entry *hash;
11182
11183 hash = (struct elf32_arm_link_hash_entry *) h;
11184
11185 stub_type = arm_type_of_stub (info, input_section, rel,
34e77a92
RS		 11186 st_type, &branch_type,
11187 hash, value, sym_sec,
fe33d2fa
CL		 11188 input_bfd, sym_name);
11189
11190 if (stub_type != arm_stub_none)
906e58ca
NC		 11191 {
11192 /* The target is out of reach or we are changing modes, so
11193 redirect the branch to the local stub for this
11194 function. */
11195 stub_entry = elf32_arm_get_stub_entry (input_section,
11196 sym_sec, h,
fe33d2fa
CL		 11197 rel, globals,
11198 stub_type);
906e58ca 11199 if (stub_entry != NULL)
9cd3e4e5
NC		 11200 {
11201 value = (stub_entry->stub_offset
11202 + stub_entry->stub_sec->output_offset
11203 + stub_entry->stub_sec->output_section->vma);
11204
11205 if (plt_offset != (bfd_vma) -1)
11206 *unresolved_reloc_p = FALSE;
11207 }
906e58ca 11208
f4ac8484 11209 /* If this call becomes a call to Arm, force BLX. */
155d87d7 11210 if (globals->use_blx && (r_type == R_ARM_THM_CALL))
f4ac8484
DJ		 11211 {
11212 if ((stub_entry
11213 && !arm_stub_is_thumb (stub_entry->stub_type))
35fc36a8 11214 || branch_type != ST_BRANCH_TO_THUMB)
f4ac8484
DJ		 11215 lower_insn = (lower_insn & ~0x1000) | 0x0800;
11216 }
906e58ca
NC		 11217 }
11218 }
11219
fe33d2fa 11220 /* Handle calls via the PLT. */
34e77a92 11221 if (stub_type == arm_stub_none && plt_offset != (bfd_vma) -1)
fe33d2fa
CL		 11222 {
11223 value = (splt->output_section->vma
11224 + splt->output_offset
34e77a92 11225 + plt_offset);
fe33d2fa 11226
eed94f8f
NC		 11227 if (globals->use_blx
11228 && r_type == R_ARM_THM_CALL
11229 && ! using_thumb_only (globals))
fe33d2fa
CL		 11230 {
11231 /* If the Thumb BLX instruction is available, convert
11232 the BL to a BLX instruction to call the ARM-mode
11233 PLT entry. */
11234 lower_insn = (lower_insn & ~0x1000) | 0x0800;
35fc36a8 11235 branch_type = ST_BRANCH_TO_ARM;
fe33d2fa
CL		 11236 }
11237 else
11238 {
eed94f8f
NC		 11239 if (! using_thumb_only (globals))
11240 /* Target the Thumb stub before the ARM PLT entry. */
11241 value -= PLT_THUMB_STUB_SIZE;
35fc36a8 11242 branch_type = ST_BRANCH_TO_THUMB;
fe33d2fa
CL		 11243 }
11244 *unresolved_reloc_p = FALSE;
11245 }
11246
ba96a88f 11247 relocation = value + signed_addend;
f21f3fe0 11248
252b5132 11249 relocation -= (input_section->output_section->vma
ba96a88f
NC		 11250 + input_section->output_offset
11251 + rel->r_offset);
9a5aca8c 11252
252b5132
RH		 11253 check = relocation >> howto->rightshift;
11254
11255 /* If this is a signed value, the rightshift just dropped
11256 leading 1 bits (assuming twos complement). */
11257 if ((bfd_signed_vma) relocation >= 0)
11258 signed_check = check;
11259 else
11260 signed_check = check | ~((bfd_vma) -1 >> howto->rightshift);
11261
e95de063
MS		 11262 /* Calculate the permissable maximum and minimum values for
11263 this relocation according to whether we're relocating for
11264 Thumb-2 or not. */
11265 bitsize = howto->bitsize;
5e866f5a 11266 if (!thumb2_bl)
e95de063 11267 bitsize -= 2;
f6ebfac0 11268 reloc_signed_max = (1 << (bitsize - 1)) - 1;
e95de063
MS		 11269 reloc_signed_min = ~reloc_signed_max;
11270
252b5132 11271 /* Assumes two's complement. */
ba96a88f 11272 if (signed_check > reloc_signed_max || signed_check < reloc_signed_min)
b34976b6 11273 overflow = TRUE;
252b5132 11274
bd97cb95 11275 if ((lower_insn & 0x5000) == 0x4000)
c62e1cc3
NC		 11276 /* For a BLX instruction, make sure that the relocation is rounded up
11277 to a word boundary. This follows the semantics of the instruction
11278 which specifies that bit 1 of the target address will come from bit
11279 1 of the base address. */
11280 relocation = (relocation + 2) & ~ 3;
cb1afa5c 11281
e95de063
MS		 11282 /* Put RELOCATION back into the insn. Assumes two's complement.
11283 We use the Thumb-2 encoding, which is safe even if dealing with
11284 a Thumb-1 instruction by virtue of our overflow check above. */
99059e56 11285 reloc_sign = (signed_check < 0) ? 1 : 0;
e95de063 11286 upper_insn = (upper_insn & ~(bfd_vma) 0x7ff)
99059e56
RM		 11287 | ((relocation >> 12) & 0x3ff)
11288 | (reloc_sign << 10);
906e58ca 11289 lower_insn = (lower_insn & ~(bfd_vma) 0x2fff)
99059e56
RM		 11290 | (((!((relocation >> 23) & 1)) ^ reloc_sign) << 13)
11291 | (((!((relocation >> 22) & 1)) ^ reloc_sign) << 11)
11292 | ((relocation >> 1) & 0x7ff);
c62e1cc3 11293
252b5132
RH		 11294 /* Put the relocated value back in the object file: */
11295 bfd_put_16 (input_bfd, upper_insn, hit_data);
11296 bfd_put_16 (input_bfd, lower_insn, hit_data + 2);
11297
11298 return (overflow ? bfd_reloc_overflow : bfd_reloc_ok);
11299 }
11300 break;
11301
c19d1205
ZW		 11302 case R_ARM_THM_JUMP19:
11303 /* Thumb32 conditional branch instruction. */
11304 {
11305 bfd_vma relocation;
11306 bfd_boolean overflow = FALSE;
11307 bfd_vma upper_insn = bfd_get_16 (input_bfd, hit_data);
11308 bfd_vma lower_insn = bfd_get_16 (input_bfd, hit_data + 2);
a00a1f35
MS		 11309 bfd_signed_vma reloc_signed_max = 0xffffe;
11310 bfd_signed_vma reloc_signed_min = -0x100000;
c19d1205 11311 bfd_signed_vma signed_check;
07d6d2b8 11312 enum elf32_arm_stub_type stub_type = arm_stub_none;
c5423981
TG		 11313 struct elf32_arm_stub_hash_entry *stub_entry;
11314 struct elf32_arm_link_hash_entry *hash;
c19d1205
ZW		 11315
11316 /* Need to refetch the addend, reconstruct the top three bits,
11317 and squish the two 11 bit pieces together. */
11318 if (globals->use_rel)
11319 {
11320 bfd_vma S = (upper_insn & 0x0400) >> 10;
a00a1f35 11321 bfd_vma upper = (upper_insn & 0x003f);
c19d1205
ZW		 11322 bfd_vma J1 = (lower_insn & 0x2000) >> 13;
11323 bfd_vma J2 = (lower_insn & 0x0800) >> 11;
11324 bfd_vma lower = (lower_insn & 0x07ff);
11325
a00a1f35
MS		 11326 upper |= J1 << 6;
11327 upper |= J2 << 7;
11328 upper |= (!S) << 8;
c19d1205
ZW		 11329 upper -= 0x0100; /* Sign extend. */
11330
11331 addend = (upper << 12) | (lower << 1);
11332 signed_addend = addend;
11333 }
11334
bd97cb95 11335 /* Handle calls via the PLT. */
34e77a92 11336 if (plt_offset != (bfd_vma) -1)
bd97cb95
DJ		 11337 {
11338 value = (splt->output_section->vma
11339 + splt->output_offset
34e77a92 11340 + plt_offset);
bd97cb95
DJ		 11341 /* Target the Thumb stub before the ARM PLT entry. */
11342 value -= PLT_THUMB_STUB_SIZE;
11343 *unresolved_reloc_p = FALSE;
11344 }
11345
c5423981
TG		 11346 hash = (struct elf32_arm_link_hash_entry *)h;
11347
11348 stub_type = arm_type_of_stub (info, input_section, rel,
07d6d2b8
AM		 11349 st_type, &branch_type,
11350 hash, value, sym_sec,
11351 input_bfd, sym_name);
c5423981
TG		 11352 if (stub_type != arm_stub_none)
11353 {
11354 stub_entry = elf32_arm_get_stub_entry (input_section,
07d6d2b8
AM		 11355 sym_sec, h,
11356 rel, globals,
11357 stub_type);
c5423981
TG		 11358 if (stub_entry != NULL)
11359 {
07d6d2b8
AM		 11360 value = (stub_entry->stub_offset
11361 + stub_entry->stub_sec->output_offset
11362 + stub_entry->stub_sec->output_section->vma);
c5423981
TG		 11363 }
11364 }
c19d1205 11365
99059e56 11366 relocation = value + signed_addend;
c19d1205
ZW		 11367 relocation -= (input_section->output_section->vma
11368 + input_section->output_offset
11369 + rel->r_offset);
a00a1f35 11370 signed_check = (bfd_signed_vma) relocation;
c19d1205 11371
c19d1205
ZW		 11372 if (signed_check > reloc_signed_max || signed_check < reloc_signed_min)
11373 overflow = TRUE;
11374
11375 /* Put RELOCATION back into the insn. */
11376 {
11377 bfd_vma S = (relocation & 0x00100000) >> 20;
11378 bfd_vma J2 = (relocation & 0x00080000) >> 19;
11379 bfd_vma J1 = (relocation & 0x00040000) >> 18;
11380 bfd_vma hi = (relocation & 0x0003f000) >> 12;
11381 bfd_vma lo = (relocation & 0x00000ffe) >> 1;
11382
a00a1f35 11383 upper_insn = (upper_insn & 0xfbc0) | (S << 10) | hi;
c19d1205
ZW		 11384 lower_insn = (lower_insn & 0xd000) | (J1 << 13) | (J2 << 11) | lo;
11385 }
11386
11387 /* Put the relocated value back in the object file: */
11388 bfd_put_16 (input_bfd, upper_insn, hit_data);
11389 bfd_put_16 (input_bfd, lower_insn, hit_data + 2);
11390
11391 return (overflow ? bfd_reloc_overflow : bfd_reloc_ok);
11392 }
11393
11394 case R_ARM_THM_JUMP11:
11395 case R_ARM_THM_JUMP8:
11396 case R_ARM_THM_JUMP6:
51c5503b
NC		 11397 /* Thumb B (branch) instruction). */
11398 {
6cf9e9fe 11399 bfd_signed_vma relocation;
51c5503b
NC		 11400 bfd_signed_vma reloc_signed_max = (1 << (howto->bitsize - 1)) - 1;
11401 bfd_signed_vma reloc_signed_min = ~ reloc_signed_max;
51c5503b
NC		 11402 bfd_signed_vma signed_check;
11403
c19d1205
ZW		 11404 /* CZB cannot jump backward. */
11405 if (r_type == R_ARM_THM_JUMP6)
11406 reloc_signed_min = 0;
11407
4e7fd91e 11408 if (globals->use_rel)
6cf9e9fe 11409 {
4e7fd91e
PB		 11410 /* Need to refetch addend. */
11411 addend = bfd_get_16 (input_bfd, hit_data) & howto->src_mask;
11412 if (addend & ((howto->src_mask + 1) >> 1))
11413 {
11414 signed_addend = -1;
11415 signed_addend &= ~ howto->src_mask;
11416 signed_addend |= addend;
11417 }
11418 else
11419 signed_addend = addend;
11420 /* The value in the insn has been right shifted. We need to
11421 undo this, so that we can perform the address calculation
11422 in terms of bytes. */
11423 signed_addend <<= howto->rightshift;
6cf9e9fe 11424 }
6cf9e9fe 11425 relocation = value + signed_addend;
51c5503b
NC		 11426
11427 relocation -= (input_section->output_section->vma
11428 + input_section->output_offset
11429 + rel->r_offset);
11430
6cf9e9fe
NC		 11431 relocation >>= howto->rightshift;
11432 signed_check = relocation;
c19d1205
ZW		 11433
11434 if (r_type == R_ARM_THM_JUMP6)
11435 relocation = ((relocation & 0x0020) << 4) | ((relocation & 0x001f) << 3);
11436 else
11437 relocation &= howto->dst_mask;
51c5503b 11438 relocation |= (bfd_get_16 (input_bfd, hit_data) & (~ howto->dst_mask));
cedb70c5 11439
51c5503b
NC		 11440 bfd_put_16 (input_bfd, relocation, hit_data);
11441
11442 /* Assumes two's complement. */
11443 if (signed_check > reloc_signed_max || signed_check < reloc_signed_min)
11444 return bfd_reloc_overflow;
11445
11446 return bfd_reloc_ok;
11447 }
cedb70c5 11448
8375c36b
PB		 11449 case R_ARM_ALU_PCREL7_0:
11450 case R_ARM_ALU_PCREL15_8:
11451 case R_ARM_ALU_PCREL23_15:
11452 {
11453 bfd_vma insn;
11454 bfd_vma relocation;
11455
11456 insn = bfd_get_32 (input_bfd, hit_data);
4e7fd91e
PB		 11457 if (globals->use_rel)
11458 {
11459 /* Extract the addend. */
11460 addend = (insn & 0xff) << ((insn & 0xf00) >> 7);
11461 signed_addend = addend;
11462 }
8375c36b
PB		 11463 relocation = value + signed_addend;
11464
11465 relocation -= (input_section->output_section->vma
11466 + input_section->output_offset
11467 + rel->r_offset);
11468 insn = (insn & ~0xfff)
11469 | ((howto->bitpos << 7) & 0xf00)
11470 | ((relocation >> howto->bitpos) & 0xff);
11471 bfd_put_32 (input_bfd, value, hit_data);
11472 }
11473 return bfd_reloc_ok;
11474
252b5132
RH		 11475 case R_ARM_GNU_VTINHERIT:
11476 case R_ARM_GNU_VTENTRY:
11477 return bfd_reloc_ok;
11478
c19d1205 11479 case R_ARM_GOTOFF32:
252b5132 11480 /* Relocation is relative to the start of the
99059e56 11481 global offset table. */
252b5132
RH		 11482
11483 BFD_ASSERT (sgot != NULL);
11484 if (sgot == NULL)
99059e56 11485 return bfd_reloc_notsupported;
9a5aca8c 11486
cedb70c5 11487 /* If we are addressing a Thumb function, we need to adjust the
ee29b9fb
RE		 11488 address by one, so that attempts to call the function pointer will
11489 correctly interpret it as Thumb code. */
35fc36a8 11490 if (branch_type == ST_BRANCH_TO_THUMB)
ee29b9fb
RE		 11491 value += 1;
11492
252b5132 11493 /* Note that sgot->output_offset is not involved in this
99059e56
RM		 11494 calculation. We always want the start of .got. If we
11495 define _GLOBAL_OFFSET_TABLE in a different way, as is
11496 permitted by the ABI, we might have to change this
11497 calculation. */
252b5132 11498 value -= sgot->output_section->vma;
f21f3fe0 11499 return _bfd_final_link_relocate (howto, input_bfd, input_section,
99e4ae17 11500 contents, rel->r_offset, value,
00a97672 11501 rel->r_addend);
252b5132
RH		 11502
11503 case R_ARM_GOTPC:
a7c10850 11504 /* Use global offset table as symbol value. */
252b5132 11505 BFD_ASSERT (sgot != NULL);
f21f3fe0 11506
252b5132 11507 if (sgot == NULL)
99059e56 11508 return bfd_reloc_notsupported;
252b5132 11509
0945cdfd 11510 *unresolved_reloc_p = FALSE;
252b5132 11511 value = sgot->output_section->vma;
f21f3fe0 11512 return _bfd_final_link_relocate (howto, input_bfd, input_section,
99e4ae17 11513 contents, rel->r_offset, value,
00a97672 11514 rel->r_addend);
f21f3fe0 11515
252b5132 11516 case R_ARM_GOT32:
eb043451 11517 case R_ARM_GOT_PREL:
252b5132 11518 /* Relocation is to the entry for this symbol in the
99059e56 11519 global offset table. */
252b5132
RH		 11520 if (sgot == NULL)
11521 return bfd_reloc_notsupported;
f21f3fe0 11522
34e77a92
RS		 11523 if (dynreloc_st_type == STT_GNU_IFUNC
11524 && plt_offset != (bfd_vma) -1
11525 && (h == NULL || SYMBOL_REFERENCES_LOCAL (info, h)))
11526 {
11527 /* We have a relocation against a locally-binding STT_GNU_IFUNC
11528 symbol, and the relocation resolves directly to the runtime
11529 target rather than to the .iplt entry. This means that any
11530 .got entry would be the same value as the .igot.plt entry,
11531 so there's no point creating both. */
11532 sgot = globals->root.igotplt;
11533 value = sgot->output_offset + gotplt_offset;
11534 }
11535 else if (h != NULL)
252b5132
RH		 11536 {
11537 bfd_vma off;
f21f3fe0 11538
252b5132
RH		 11539 off = h->got.offset;
11540 BFD_ASSERT (off != (bfd_vma) -1);
b436d854 11541 if ((off & 1) != 0)
252b5132 11542 {
b436d854
RS		 11543 /* We have already processsed one GOT relocation against
11544 this symbol. */
11545 off &= ~1;
11546 if (globals->root.dynamic_sections_created
11547 && !SYMBOL_REFERENCES_LOCAL (info, h))
11548 *unresolved_reloc_p = FALSE;
11549 }
11550 else
11551 {
11552 Elf_Internal_Rela outrel;
e8b09b87 11553 int isrofixup = 0;
b436d854 11554
e8b09b87
CL		 11555 if (((h->dynindx != -1) || globals->fdpic_p)
11556 && !SYMBOL_REFERENCES_LOCAL (info, h))
b436d854
RS		 11557 {
11558 /* If the symbol doesn't resolve locally in a static
11559 object, we have an undefined reference. If the
11560 symbol doesn't resolve locally in a dynamic object,
11561 it should be resolved by the dynamic linker. */
11562 if (globals->root.dynamic_sections_created)
11563 {
11564 outrel.r_info = ELF32_R_INFO (h->dynindx, R_ARM_GLOB_DAT);
11565 *unresolved_reloc_p = FALSE;
11566 }
11567 else
11568 outrel.r_info = 0;
11569 outrel.r_addend = 0;
11570 }
252b5132
RH		 11571 else
11572 {
34e77a92 11573 if (dynreloc_st_type == STT_GNU_IFUNC)
99059e56 11574 outrel.r_info = ELF32_R_INFO (0, R_ARM_IRELATIVE);
5025eb7c
AO		 11575 else if (bfd_link_pic (info)
11576 && (ELF_ST_VISIBILITY (h->other) == STV_DEFAULT
11577 || h->root.type != bfd_link_hash_undefweak))
99059e56
RM		 11578 outrel.r_info = ELF32_R_INFO (0, R_ARM_RELATIVE);
11579 else
2376f038
EB		 11580 {
11581 outrel.r_info = 0;
11582 if (globals->fdpic_p)
11583 isrofixup = 1;
11584 }
34e77a92 11585 outrel.r_addend = dynreloc_value;
b436d854 11586 }
ee29b9fb 11587
b436d854
RS		 11588 /* The GOT entry is initialized to zero by default.
11589 See if we should install a different value. */
11590 if (outrel.r_addend != 0
2376f038 11591 && (globals->use_rel || outrel.r_info == 0))
b436d854
RS		 11592 {
11593 bfd_put_32 (output_bfd, outrel.r_addend,
11594 sgot->contents + off);
11595 outrel.r_addend = 0;
252b5132 11596 }
f21f3fe0 11597
2376f038
EB		 11598 if (isrofixup)
11599 arm_elf_add_rofixup (output_bfd,
11600 elf32_arm_hash_table(info)->srofixup,
11601 sgot->output_section->vma
11602 + sgot->output_offset + off);
11603
11604 else if (outrel.r_info != 0)
b436d854
RS		 11605 {
11606 outrel.r_offset = (sgot->output_section->vma
11607 + sgot->output_offset
11608 + off);
11609 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
11610 }
2376f038 11611
b436d854
RS		 11612 h->got.offset |= 1;
11613 }
252b5132
RH		 11614 value = sgot->output_offset + off;
11615 }
11616 else
11617 {
11618 bfd_vma off;
f21f3fe0 11619
5025eb7c
AO		 11620 BFD_ASSERT (local_got_offsets != NULL
11621 && local_got_offsets[r_symndx] != (bfd_vma) -1);
f21f3fe0 11622
252b5132 11623 off = local_got_offsets[r_symndx];
f21f3fe0 11624
252b5132
RH		 11625 /* The offset must always be a multiple of 4. We use the
11626 least significant bit to record whether we have already
9b485d32 11627 generated the necessary reloc. */
252b5132
RH		 11628 if ((off & 1) != 0)
11629 off &= ~1;
11630 else
11631 {
2376f038
EB		 11632 Elf_Internal_Rela outrel;
11633 int isrofixup = 0;
f21f3fe0 11634
2376f038
EB		 11635 if (dynreloc_st_type == STT_GNU_IFUNC)
11636 outrel.r_info = ELF32_R_INFO (0, R_ARM_IRELATIVE);
11637 else if (bfd_link_pic (info))
11638 outrel.r_info = ELF32_R_INFO (0, R_ARM_RELATIVE);
11639 else
252b5132 11640 {
2376f038
EB		 11641 outrel.r_info = 0;
11642 if (globals->fdpic_p)
11643 isrofixup = 1;
11644 }
11645
11646 /* The GOT entry is initialized to zero by default.
11647 See if we should install a different value. */
11648 if (globals->use_rel || outrel.r_info == 0)
11649 bfd_put_32 (output_bfd, dynreloc_value, sgot->contents + off);
11650
11651 if (isrofixup)
11652 arm_elf_add_rofixup (output_bfd,
11653 globals->srofixup,
11654 sgot->output_section->vma
11655 + sgot->output_offset + off);
f21f3fe0 11656
2376f038
EB		 11657 else if (outrel.r_info != 0)
11658 {
34e77a92 11659 outrel.r_addend = addend + dynreloc_value;
252b5132 11660 outrel.r_offset = (sgot->output_section->vma
f21f3fe0 11661 + sgot->output_offset
252b5132 11662 + off);
47beaa6a 11663 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
252b5132 11664 }
f21f3fe0 11665
252b5132
RH		 11666 local_got_offsets[r_symndx] |= 1;
11667 }
f21f3fe0 11668
252b5132
RH		 11669 value = sgot->output_offset + off;
11670 }
eb043451
PB		 11671 if (r_type != R_ARM_GOT32)
11672 value += sgot->output_section->vma;
9a5aca8c 11673
f21f3fe0 11674 return _bfd_final_link_relocate (howto, input_bfd, input_section,
99e4ae17 11675 contents, rel->r_offset, value,
00a97672 11676 rel->r_addend);
f21f3fe0 11677
ba93b8ac
DJ		 11678 case R_ARM_TLS_LDO32:
11679 value = value - dtpoff_base (info);
11680
11681 return _bfd_final_link_relocate (howto, input_bfd, input_section,
00a97672
RS		 11682 contents, rel->r_offset, value,
11683 rel->r_addend);
ba93b8ac
DJ		 11684
11685 case R_ARM_TLS_LDM32:
5c5a4843 11686 case R_ARM_TLS_LDM32_FDPIC:
ba93b8ac
DJ		 11687 {
11688 bfd_vma off;
11689
362d30a1 11690 if (sgot == NULL)
ba93b8ac
DJ		 11691 abort ();
11692
11693 off = globals->tls_ldm_got.offset;
11694
11695 if ((off & 1) != 0)
11696 off &= ~1;
11697 else
11698 {
11699 /* If we don't know the module number, create a relocation
11700 for it. */
0e1862bb 11701 if (bfd_link_pic (info))
ba93b8ac
DJ		 11702 {
11703 Elf_Internal_Rela outrel;
ba93b8ac 11704
362d30a1 11705 if (srelgot == NULL)
ba93b8ac
DJ		 11706 abort ();
11707
00a97672 11708 outrel.r_addend = 0;
362d30a1
RS		 11709 outrel.r_offset = (sgot->output_section->vma
11710 + sgot->output_offset + off);
ba93b8ac
DJ		 11711 outrel.r_info = ELF32_R_INFO (0, R_ARM_TLS_DTPMOD32);
11712
00a97672
RS		 11713 if (globals->use_rel)
11714 bfd_put_32 (output_bfd, outrel.r_addend,
362d30a1 11715 sgot->contents + off);
ba93b8ac 11716
47beaa6a 11717 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
ba93b8ac
DJ		 11718 }
11719 else
362d30a1 11720 bfd_put_32 (output_bfd, 1, sgot->contents + off);
ba93b8ac
DJ		 11721
11722 globals->tls_ldm_got.offset |= 1;
11723 }
11724
5c5a4843 11725 if (r_type == R_ARM_TLS_LDM32_FDPIC)
e8b09b87
CL		 11726 {
11727 bfd_put_32(output_bfd,
11728 globals->root.sgot->output_offset + off,
11729 contents + rel->r_offset);
11730
11731 return bfd_reloc_ok;
11732 }
11733 else
11734 {
11735 value = sgot->output_section->vma + sgot->output_offset + off
11736 - (input_section->output_section->vma
11737 + input_section->output_offset + rel->r_offset);
ba93b8ac 11738
e8b09b87
CL		 11739 return _bfd_final_link_relocate (howto, input_bfd, input_section,
11740 contents, rel->r_offset, value,
11741 rel->r_addend);
11742 }
ba93b8ac
DJ		 11743 }
11744
0855e32b
NS		 11745 case R_ARM_TLS_CALL:
11746 case R_ARM_THM_TLS_CALL:
ba93b8ac 11747 case R_ARM_TLS_GD32:
5c5a4843 11748 case R_ARM_TLS_GD32_FDPIC:
ba93b8ac 11749 case R_ARM_TLS_IE32:
5c5a4843 11750 case R_ARM_TLS_IE32_FDPIC:
0855e32b
NS		 11751 case R_ARM_TLS_GOTDESC:
11752 case R_ARM_TLS_DESCSEQ:
11753 case R_ARM_THM_TLS_DESCSEQ:
ba93b8ac 11754 {
0855e32b
NS		 11755 bfd_vma off, offplt;
11756 int indx = 0;
ba93b8ac
DJ		 11757 char tls_type;
11758
0855e32b 11759 BFD_ASSERT (sgot != NULL);
ba93b8ac 11760
ba93b8ac
DJ		 11761 if (h != NULL)
11762 {
11763 bfd_boolean dyn;
11764 dyn = globals->root.dynamic_sections_created;
0e1862bb
L		 11765 if (WILL_CALL_FINISH_DYNAMIC_SYMBOL (dyn,
11766 bfd_link_pic (info),
11767 h)
11768 && (!bfd_link_pic (info)
ba93b8ac
DJ		 11769 || !SYMBOL_REFERENCES_LOCAL (info, h)))
11770 {
11771 *unresolved_reloc_p = FALSE;
11772 indx = h->dynindx;
11773 }
11774 off = h->got.offset;
0855e32b 11775 offplt = elf32_arm_hash_entry (h)->tlsdesc_got;
ba93b8ac
DJ		 11776 tls_type = ((struct elf32_arm_link_hash_entry *) h)->tls_type;
11777 }
11778 else
11779 {
0855e32b 11780 BFD_ASSERT (local_got_offsets != NULL);
ba93b8ac 11781 off = local_got_offsets[r_symndx];
0855e32b 11782 offplt = local_tlsdesc_gotents[r_symndx];
ba93b8ac
DJ		 11783 tls_type = elf32_arm_local_got_tls_type (input_bfd)[r_symndx];
11784 }
11785
0855e32b 11786 /* Linker relaxations happens from one of the
b38cadfb 11787 R_ARM_{GOTDESC,CALL,DESCSEQ} relocations to IE or LE. */
0855e32b 11788 if (ELF32_R_TYPE(rel->r_info) != r_type)
b38cadfb 11789 tls_type = GOT_TLS_IE;
0855e32b
NS		 11790
11791 BFD_ASSERT (tls_type != GOT_UNKNOWN);
ba93b8ac
DJ		 11792
11793 if ((off & 1) != 0)
11794 off &= ~1;
11795 else
11796 {
11797 bfd_boolean need_relocs = FALSE;
11798 Elf_Internal_Rela outrel;
ba93b8ac
DJ		 11799 int cur_off = off;
11800
11801 /* The GOT entries have not been initialized yet. Do it
11802 now, and emit any relocations. If both an IE GOT and a
11803 GD GOT are necessary, we emit the GD first. */
11804
0e1862bb 11805 if ((bfd_link_pic (info) || indx != 0)
ba93b8ac 11806 && (h == NULL
95b03e4a
L		 11807 || (ELF_ST_VISIBILITY (h->other) == STV_DEFAULT
11808 && !resolved_to_zero)
ba93b8ac
DJ		 11809 || h->root.type != bfd_link_hash_undefweak))
11810 {
11811 need_relocs = TRUE;
0855e32b 11812 BFD_ASSERT (srelgot != NULL);
ba93b8ac
DJ		 11813 }
11814
0855e32b
NS		 11815 if (tls_type & GOT_TLS_GDESC)
11816 {
47beaa6a
RS		 11817 bfd_byte *loc;
11818
0855e32b
NS		 11819 /* We should have relaxed, unless this is an undefined
11820 weak symbol. */
11821 BFD_ASSERT ((h && (h->root.type == bfd_link_hash_undefweak))
0e1862bb 11822 || bfd_link_pic (info));
0855e32b 11823 BFD_ASSERT (globals->sgotplt_jump_table_size + offplt + 8
99059e56 11824 <= globals->root.sgotplt->size);
0855e32b
NS		 11825
11826 outrel.r_addend = 0;
11827 outrel.r_offset = (globals->root.sgotplt->output_section->vma
11828 + globals->root.sgotplt->output_offset
11829 + offplt
11830 + globals->sgotplt_jump_table_size);
b38cadfb 11831
0855e32b
NS		 11832 outrel.r_info = ELF32_R_INFO (indx, R_ARM_TLS_DESC);
11833 sreloc = globals->root.srelplt;
11834 loc = sreloc->contents;
11835 loc += globals->next_tls_desc_index++ * RELOC_SIZE (globals);
11836 BFD_ASSERT (loc + RELOC_SIZE (globals)
99059e56 11837 <= sreloc->contents + sreloc->size);
0855e32b
NS		 11838
11839 SWAP_RELOC_OUT (globals) (output_bfd, &outrel, loc);
11840
11841 /* For globals, the first word in the relocation gets
11842 the relocation index and the top bit set, or zero,
11843 if we're binding now. For locals, it gets the
11844 symbol's offset in the tls section. */
99059e56 11845 bfd_put_32 (output_bfd,
0855e32b
NS		 11846 !h ? value - elf_hash_table (info)->tls_sec->vma
11847 : info->flags & DF_BIND_NOW ? 0
11848 : 0x80000000 | ELF32_R_SYM (outrel.r_info),
b38cadfb
NC		 11849 globals->root.sgotplt->contents + offplt
11850 + globals->sgotplt_jump_table_size);
11851
0855e32b 11852 /* Second word in the relocation is always zero. */
99059e56 11853 bfd_put_32 (output_bfd, 0,
b38cadfb
NC		 11854 globals->root.sgotplt->contents + offplt
11855 + globals->sgotplt_jump_table_size + 4);
0855e32b 11856 }
ba93b8ac
DJ		 11857 if (tls_type & GOT_TLS_GD)
11858 {
11859 if (need_relocs)
11860 {
00a97672 11861 outrel.r_addend = 0;
362d30a1
RS		 11862 outrel.r_offset = (sgot->output_section->vma
11863 + sgot->output_offset
00a97672 11864 + cur_off);
ba93b8ac 11865 outrel.r_info = ELF32_R_INFO (indx, R_ARM_TLS_DTPMOD32);
ba93b8ac 11866
00a97672
RS		 11867 if (globals->use_rel)
11868 bfd_put_32 (output_bfd, outrel.r_addend,
362d30a1 11869 sgot->contents + cur_off);
00a97672 11870
47beaa6a 11871 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
ba93b8ac
DJ		 11872
11873 if (indx == 0)
11874 bfd_put_32 (output_bfd, value - dtpoff_base (info),
362d30a1 11875 sgot->contents + cur_off + 4);
ba93b8ac
DJ		 11876 else
11877 {
00a97672 11878 outrel.r_addend = 0;
ba93b8ac
DJ		 11879 outrel.r_info = ELF32_R_INFO (indx,
11880 R_ARM_TLS_DTPOFF32);
11881 outrel.r_offset += 4;
00a97672
RS		 11882
11883 if (globals->use_rel)
11884 bfd_put_32 (output_bfd, outrel.r_addend,
362d30a1 11885 sgot->contents + cur_off + 4);
00a97672 11886
47beaa6a
RS		 11887 elf32_arm_add_dynreloc (output_bfd, info,
11888 srelgot, &outrel);
ba93b8ac
DJ		 11889 }
11890 }
11891 else
11892 {
11893 /* If we are not emitting relocations for a
11894 general dynamic reference, then we must be in a
11895 static link or an executable link with the
11896 symbol binding locally. Mark it as belonging
11897 to module 1, the executable. */
11898 bfd_put_32 (output_bfd, 1,
362d30a1 11899 sgot->contents + cur_off);
ba93b8ac 11900 bfd_put_32 (output_bfd, value - dtpoff_base (info),
362d30a1 11901 sgot->contents + cur_off + 4);
ba93b8ac
DJ		 11902 }
11903
11904 cur_off += 8;
11905 }
11906
11907 if (tls_type & GOT_TLS_IE)
11908 {
11909 if (need_relocs)
11910 {
00a97672
RS		 11911 if (indx == 0)
11912 outrel.r_addend = value - dtpoff_base (info);
11913 else
11914 outrel.r_addend = 0;
362d30a1
RS		 11915 outrel.r_offset = (sgot->output_section->vma
11916 + sgot->output_offset
ba93b8ac
DJ		 11917 + cur_off);
11918 outrel.r_info = ELF32_R_INFO (indx, R_ARM_TLS_TPOFF32);
11919
00a97672
RS		 11920 if (globals->use_rel)
11921 bfd_put_32 (output_bfd, outrel.r_addend,
362d30a1 11922 sgot->contents + cur_off);
ba93b8ac 11923
47beaa6a 11924 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
ba93b8ac
DJ		 11925 }
11926 else
11927 bfd_put_32 (output_bfd, tpoff (info, value),
362d30a1 11928 sgot->contents + cur_off);
ba93b8ac
DJ		 11929 cur_off += 4;
11930 }
11931
11932 if (h != NULL)
11933 h->got.offset |= 1;
11934 else
11935 local_got_offsets[r_symndx] |= 1;
11936 }
11937
5c5a4843 11938 if ((tls_type & GOT_TLS_GD) && r_type != R_ARM_TLS_GD32 && r_type != R_ARM_TLS_GD32_FDPIC)
ba93b8ac 11939 off += 8;
0855e32b
NS		 11940 else if (tls_type & GOT_TLS_GDESC)
11941 off = offplt;
11942
11943 if (ELF32_R_TYPE(rel->r_info) == R_ARM_TLS_CALL
11944 || ELF32_R_TYPE(rel->r_info) == R_ARM_THM_TLS_CALL)
11945 {
11946 bfd_signed_vma offset;
12352d3f
PB		 11947 /* TLS stubs are arm mode. The original symbol is a
11948 data object, so branch_type is bogus. */
11949 branch_type = ST_BRANCH_TO_ARM;
0855e32b 11950 enum elf32_arm_stub_type stub_type
34e77a92
RS		 11951 = arm_type_of_stub (info, input_section, rel,
11952 st_type, &branch_type,
0855e32b
NS		 11953 (struct elf32_arm_link_hash_entry *)h,
11954 globals->tls_trampoline, globals->root.splt,
11955 input_bfd, sym_name);
11956
11957 if (stub_type != arm_stub_none)
11958 {
11959 struct elf32_arm_stub_hash_entry *stub_entry
11960 = elf32_arm_get_stub_entry
11961 (input_section, globals->root.splt, 0, rel,
11962 globals, stub_type);
11963 offset = (stub_entry->stub_offset
11964 + stub_entry->stub_sec->output_offset
11965 + stub_entry->stub_sec->output_section->vma);
11966 }
11967 else
11968 offset = (globals->root.splt->output_section->vma
11969 + globals->root.splt->output_offset
11970 + globals->tls_trampoline);
11971
11972 if (ELF32_R_TYPE(rel->r_info) == R_ARM_TLS_CALL)
11973 {
11974 unsigned long inst;
b38cadfb
NC		 11975
11976 offset -= (input_section->output_section->vma
11977 + input_section->output_offset
11978 + rel->r_offset + 8);
0855e32b
NS		 11979
11980 inst = offset >> 2;
11981 inst &= 0x00ffffff;
11982 value = inst | (globals->use_blx ? 0xfa000000 : 0xeb000000);
11983 }
11984 else
11985 {
11986 /* Thumb blx encodes the offset in a complicated
11987 fashion. */
11988 unsigned upper_insn, lower_insn;
11989 unsigned neg;
11990
b38cadfb
NC		 11991 offset -= (input_section->output_section->vma
11992 + input_section->output_offset
0855e32b 11993 + rel->r_offset + 4);
b38cadfb 11994
12352d3f
PB		 11995 if (stub_type != arm_stub_none
11996 && arm_stub_is_thumb (stub_type))
11997 {
11998 lower_insn = 0xd000;
11999 }
12000 else
12001 {
12002 lower_insn = 0xc000;
6a631e86 12003 /* Round up the offset to a word boundary. */
12352d3f
PB		 12004 offset = (offset + 2) & ~2;
12005 }
12006
0855e32b
NS		 12007 neg = offset < 0;
12008 upper_insn = (0xf000
12009 | ((offset >> 12) & 0x3ff)
12010 | (neg << 10));
12352d3f 12011 lower_insn |= (((!((offset >> 23) & 1)) ^ neg) << 13)
0855e32b 12012 | (((!((offset >> 22) & 1)) ^ neg) << 11)
12352d3f 12013 | ((offset >> 1) & 0x7ff);
0855e32b
NS		 12014 bfd_put_16 (input_bfd, upper_insn, hit_data);
12015 bfd_put_16 (input_bfd, lower_insn, hit_data + 2);
12016 return bfd_reloc_ok;
12017 }
12018 }
12019 /* These relocations needs special care, as besides the fact
12020 they point somewhere in .gotplt, the addend must be
12021 adjusted accordingly depending on the type of instruction
6a631e86 12022 we refer to. */
0855e32b
NS		 12023 else if ((r_type == R_ARM_TLS_GOTDESC) && (tls_type & GOT_TLS_GDESC))
12024 {
12025 unsigned long data, insn;
12026 unsigned thumb;
b38cadfb 12027
0855e32b
NS		 12028 data = bfd_get_32 (input_bfd, hit_data);
12029 thumb = data & 1;
12030 data &= ~1u;
b38cadfb 12031
0855e32b
NS		 12032 if (thumb)
12033 {
12034 insn = bfd_get_16 (input_bfd, contents + rel->r_offset - data);
12035 if ((insn & 0xf000) == 0xf000 || (insn & 0xf800) == 0xe800)
12036 insn = (insn << 16)
12037 | bfd_get_16 (input_bfd,
12038 contents + rel->r_offset - data + 2);
12039 if ((insn & 0xf800c000) == 0xf000c000)
12040 /* bl/blx */
12041 value = -6;
12042 else if ((insn & 0xffffff00) == 0x4400)
12043 /* add */
12044 value = -5;
12045 else
12046 {
4eca0228 12047 _bfd_error_handler
695344c0 12048 /* xgettext:c-format */
2dcf00ce 12049 (_("%pB(%pA+%#" PRIx64 "): "
90b6238f 12050 "unexpected %s instruction '%#lx' "
2dcf00ce
AM		 12051 "referenced by TLS_GOTDESC"),
12052 input_bfd, input_section, (uint64_t) rel->r_offset,
90b6238f 12053 "Thumb", insn);
0855e32b
NS		 12054 return bfd_reloc_notsupported;
12055 }
12056 }
12057 else
12058 {
12059 insn = bfd_get_32 (input_bfd, contents + rel->r_offset - data);
12060
12061 switch (insn >> 24)
12062 {
12063 case 0xeb: /* bl */
12064 case 0xfa: /* blx */
12065 value = -4;
12066 break;
12067
12068 case 0xe0: /* add */
12069 value = -8;
12070 break;
b38cadfb 12071
0855e32b 12072 default:
4eca0228 12073 _bfd_error_handler
695344c0 12074 /* xgettext:c-format */
2dcf00ce 12075 (_("%pB(%pA+%#" PRIx64 "): "
90b6238f 12076 "unexpected %s instruction '%#lx' "
2dcf00ce
AM		 12077 "referenced by TLS_GOTDESC"),
12078 input_bfd, input_section, (uint64_t) rel->r_offset,
90b6238f 12079 "ARM", insn);
0855e32b
NS		 12080 return bfd_reloc_notsupported;
12081 }
12082 }
b38cadfb 12083
0855e32b
NS		 12084 value += ((globals->root.sgotplt->output_section->vma
12085 + globals->root.sgotplt->output_offset + off)
12086 - (input_section->output_section->vma
12087 + input_section->output_offset
12088 + rel->r_offset)
12089 + globals->sgotplt_jump_table_size);
12090 }
12091 else
12092 value = ((globals->root.sgot->output_section->vma
12093 + globals->root.sgot->output_offset + off)
12094 - (input_section->output_section->vma
12095 + input_section->output_offset + rel->r_offset));
ba93b8ac 12096
5c5a4843
CL		 12097 if (globals->fdpic_p && (r_type == R_ARM_TLS_GD32_FDPIC ||
12098 r_type == R_ARM_TLS_IE32_FDPIC))
e8b09b87
CL		 12099 {
12100 /* For FDPIC relocations, resolve to the offset of the GOT
12101 entry from the start of GOT. */
12102 bfd_put_32(output_bfd,
12103 globals->root.sgot->output_offset + off,
12104 contents + rel->r_offset);
12105
12106 return bfd_reloc_ok;
12107 }
12108 else
12109 {
12110 return _bfd_final_link_relocate (howto, input_bfd, input_section,
12111 contents, rel->r_offset, value,
12112 rel->r_addend);
12113 }
ba93b8ac
DJ		 12114 }
12115
12116 case R_ARM_TLS_LE32:
3cbc1e5e 12117 if (bfd_link_dll (info))
ba93b8ac 12118 {
4eca0228 12119 _bfd_error_handler
695344c0 12120 /* xgettext:c-format */
2dcf00ce
AM		 12121 (_("%pB(%pA+%#" PRIx64 "): %s relocation not permitted "
12122 "in shared object"),
12123 input_bfd, input_section, (uint64_t) rel->r_offset, howto->name);
46691134 12124 return bfd_reloc_notsupported;
ba93b8ac
DJ		 12125 }
12126 else
12127 value = tpoff (info, value);
906e58ca 12128
ba93b8ac 12129 return _bfd_final_link_relocate (howto, input_bfd, input_section,
00a97672
RS		 12130 contents, rel->r_offset, value,
12131 rel->r_addend);
ba93b8ac 12132
319850b4
JB		 12133 case R_ARM_V4BX:
12134 if (globals->fix_v4bx)
845b51d6
PB		 12135 {
12136 bfd_vma insn = bfd_get_32 (input_bfd, hit_data);
319850b4 12137
845b51d6
PB		 12138 /* Ensure that we have a BX instruction. */
12139 BFD_ASSERT ((insn & 0x0ffffff0) == 0x012fff10);
319850b4 12140
845b51d6
PB		 12141 if (globals->fix_v4bx == 2 && (insn & 0xf) != 0xf)
12142 {
12143 /* Branch to veneer. */
12144 bfd_vma glue_addr;
12145 glue_addr = elf32_arm_bx_glue (info, insn & 0xf);
12146 glue_addr -= input_section->output_section->vma
12147 + input_section->output_offset
12148 + rel->r_offset + 8;
12149 insn = (insn & 0xf0000000) | 0x0a000000
12150 | ((glue_addr >> 2) & 0x00ffffff);
12151 }
12152 else
12153 {
12154 /* Preserve Rm (lowest four bits) and the condition code
12155 (highest four bits). Other bits encode MOV PC,Rm. */
12156 insn = (insn & 0xf000000f) | 0x01a0f000;
12157 }
319850b4 12158
845b51d6
PB		 12159 bfd_put_32 (input_bfd, insn, hit_data);
12160 }
319850b4
JB		 12161 return bfd_reloc_ok;
12162
b6895b4f
PB		 12163 case R_ARM_MOVW_ABS_NC:
12164 case R_ARM_MOVT_ABS:
12165 case R_ARM_MOVW_PREL_NC:
12166 case R_ARM_MOVT_PREL:
92f5d02b
MS		 12167 /* Until we properly support segment-base-relative addressing then
12168 we assume the segment base to be zero, as for the group relocations.
12169 Thus R_ARM_MOVW_BREL_NC has the same semantics as R_ARM_MOVW_ABS_NC
12170 and R_ARM_MOVT_BREL has the same semantics as R_ARM_MOVT_ABS. */
12171 case R_ARM_MOVW_BREL_NC:
12172 case R_ARM_MOVW_BREL:
12173 case R_ARM_MOVT_BREL:
b6895b4f
PB		 12174 {
12175 bfd_vma insn = bfd_get_32 (input_bfd, hit_data);
12176
12177 if (globals->use_rel)
12178 {
12179 addend = ((insn >> 4) & 0xf000) | (insn & 0xfff);
39623e12 12180 signed_addend = (addend ^ 0x8000) - 0x8000;
b6895b4f 12181 }
92f5d02b 12182
b6895b4f 12183 value += signed_addend;
b6895b4f
PB		 12184
12185 if (r_type == R_ARM_MOVW_PREL_NC || r_type == R_ARM_MOVT_PREL)
12186 value -= (input_section->output_section->vma
12187 + input_section->output_offset + rel->r_offset);
12188
92f5d02b 12189 if (r_type == R_ARM_MOVW_BREL && value >= 0x10000)
99059e56 12190 return bfd_reloc_overflow;
92f5d02b 12191
35fc36a8 12192 if (branch_type == ST_BRANCH_TO_THUMB)
92f5d02b
MS		 12193 value |= 1;
12194
12195 if (r_type == R_ARM_MOVT_ABS || r_type == R_ARM_MOVT_PREL
99059e56 12196 || r_type == R_ARM_MOVT_BREL)
b6895b4f
PB		 12197 value >>= 16;
12198
12199 insn &= 0xfff0f000;
12200 insn |= value & 0xfff;
12201 insn |= (value & 0xf000) << 4;
12202 bfd_put_32 (input_bfd, insn, hit_data);
12203 }
12204 return bfd_reloc_ok;
12205
12206 case R_ARM_THM_MOVW_ABS_NC:
12207 case R_ARM_THM_MOVT_ABS:
12208 case R_ARM_THM_MOVW_PREL_NC:
12209 case R_ARM_THM_MOVT_PREL:
92f5d02b
MS		 12210 /* Until we properly support segment-base-relative addressing then
12211 we assume the segment base to be zero, as for the above relocations.
12212 Thus R_ARM_THM_MOVW_BREL_NC has the same semantics as
12213 R_ARM_THM_MOVW_ABS_NC and R_ARM_THM_MOVT_BREL has the same semantics
12214 as R_ARM_THM_MOVT_ABS. */
12215 case R_ARM_THM_MOVW_BREL_NC:
12216 case R_ARM_THM_MOVW_BREL:
12217 case R_ARM_THM_MOVT_BREL:
b6895b4f
PB		 12218 {
12219 bfd_vma insn;
906e58ca 12220
b6895b4f
PB		 12221 insn = bfd_get_16 (input_bfd, hit_data) << 16;
12222 insn |= bfd_get_16 (input_bfd, hit_data + 2);
12223
12224 if (globals->use_rel)
12225 {
12226 addend = ((insn >> 4) & 0xf000)
12227 | ((insn >> 15) & 0x0800)
12228 | ((insn >> 4) & 0x0700)
07d6d2b8 12229 | (insn & 0x00ff);
39623e12 12230 signed_addend = (addend ^ 0x8000) - 0x8000;
b6895b4f 12231 }
92f5d02b 12232
b6895b4f 12233 value += signed_addend;
b6895b4f
PB		 12234
12235 if (r_type == R_ARM_THM_MOVW_PREL_NC || r_type == R_ARM_THM_MOVT_PREL)
12236 value -= (input_section->output_section->vma
12237 + input_section->output_offset + rel->r_offset);
12238
92f5d02b 12239 if (r_type == R_ARM_THM_MOVW_BREL && value >= 0x10000)
99059e56 12240 return bfd_reloc_overflow;
92f5d02b 12241
35fc36a8 12242 if (branch_type == ST_BRANCH_TO_THUMB)
92f5d02b
MS		 12243 value |= 1;
12244
12245 if (r_type == R_ARM_THM_MOVT_ABS || r_type == R_ARM_THM_MOVT_PREL
99059e56 12246 || r_type == R_ARM_THM_MOVT_BREL)
b6895b4f
PB		 12247 value >>= 16;
12248
12249 insn &= 0xfbf08f00;
12250 insn |= (value & 0xf000) << 4;
12251 insn |= (value & 0x0800) << 15;
12252 insn |= (value & 0x0700) << 4;
12253 insn |= (value & 0x00ff);
12254
12255 bfd_put_16 (input_bfd, insn >> 16, hit_data);
12256 bfd_put_16 (input_bfd, insn & 0xffff, hit_data + 2);
12257 }
12258 return bfd_reloc_ok;
12259
4962c51a
MS		 12260 case R_ARM_ALU_PC_G0_NC:
12261 case R_ARM_ALU_PC_G1_NC:
12262 case R_ARM_ALU_PC_G0:
12263 case R_ARM_ALU_PC_G1:
12264 case R_ARM_ALU_PC_G2:
12265 case R_ARM_ALU_SB_G0_NC:
12266 case R_ARM_ALU_SB_G1_NC:
12267 case R_ARM_ALU_SB_G0:
12268 case R_ARM_ALU_SB_G1:
12269 case R_ARM_ALU_SB_G2:
12270 {
12271 bfd_vma insn = bfd_get_32 (input_bfd, hit_data);
99059e56 12272 bfd_vma pc = input_section->output_section->vma
4962c51a 12273 + input_section->output_offset + rel->r_offset;
31a91d61 12274 /* sb is the origin of the *segment* containing the symbol. */
62c34db3 12275 bfd_vma sb = sym_sec ? sym_sec->output_section->vma : 0;
99059e56
RM		 12276 bfd_vma residual;
12277 bfd_vma g_n;
4962c51a 12278 bfd_signed_vma signed_value;
99059e56
RM		 12279 int group = 0;
12280
12281 /* Determine which group of bits to select. */
12282 switch (r_type)
12283 {
12284 case R_ARM_ALU_PC_G0_NC:
12285 case R_ARM_ALU_PC_G0:
12286 case R_ARM_ALU_SB_G0_NC:
12287 case R_ARM_ALU_SB_G0:
12288 group = 0;
12289 break;
12290
12291 case R_ARM_ALU_PC_G1_NC:
12292 case R_ARM_ALU_PC_G1:
12293 case R_ARM_ALU_SB_G1_NC:
12294 case R_ARM_ALU_SB_G1:
12295 group = 1;
12296 break;
12297
12298 case R_ARM_ALU_PC_G2:
12299 case R_ARM_ALU_SB_G2:
12300 group = 2;
12301 break;
12302
12303 default:
12304 abort ();
12305 }
12306
12307 /* If REL, extract the addend from the insn. If RELA, it will
12308 have already been fetched for us. */
4962c51a 12309 if (globals->use_rel)
99059e56
RM		 12310 {
12311 int negative;
12312 bfd_vma constant = insn & 0xff;
12313 bfd_vma rotation = (insn & 0xf00) >> 8;
12314
12315 if (rotation == 0)
12316 signed_addend = constant;
12317 else
12318 {
12319 /* Compensate for the fact that in the instruction, the
12320 rotation is stored in multiples of 2 bits. */
12321 rotation *= 2;
12322
12323 /* Rotate "constant" right by "rotation" bits. */
12324 signed_addend = (constant >> rotation) |
12325 (constant << (8 * sizeof (bfd_vma) - rotation));
12326 }
12327
12328 /* Determine if the instruction is an ADD or a SUB.
12329 (For REL, this determines the sign of the addend.) */
12330 negative = identify_add_or_sub (insn);
12331 if (negative == 0)
12332 {
4eca0228 12333 _bfd_error_handler
695344c0 12334 /* xgettext:c-format */
90b6238f 12335 (_("%pB(%pA+%#" PRIx64 "): only ADD or SUB instructions "
2dcf00ce
AM		 12336 "are allowed for ALU group relocations"),
12337 input_bfd, input_section, (uint64_t) rel->r_offset);
99059e56
RM		 12338 return bfd_reloc_overflow;
12339 }
12340
12341 signed_addend *= negative;
12342 }
4962c51a
MS		 12343
12344 /* Compute the value (X) to go in the place. */
99059e56
RM		 12345 if (r_type == R_ARM_ALU_PC_G0_NC
12346 || r_type == R_ARM_ALU_PC_G1_NC
12347 || r_type == R_ARM_ALU_PC_G0
12348 || r_type == R_ARM_ALU_PC_G1
12349 || r_type == R_ARM_ALU_PC_G2)
12350 /* PC relative. */
12351 signed_value = value - pc + signed_addend;
12352 else
12353 /* Section base relative. */
12354 signed_value = value - sb + signed_addend;
12355
12356 /* If the target symbol is a Thumb function, then set the
12357 Thumb bit in the address. */
35fc36a8 12358 if (branch_type == ST_BRANCH_TO_THUMB)
4962c51a
MS		 12359 signed_value |= 1;
12360
99059e56
RM		 12361 /* Calculate the value of the relevant G_n, in encoded
12362 constant-with-rotation format. */
b6518b38
NC		 12363 g_n = calculate_group_reloc_mask (signed_value < 0 ? - signed_value : signed_value,
12364 group, &residual);
99059e56
RM		 12365
12366 /* Check for overflow if required. */
12367 if ((r_type == R_ARM_ALU_PC_G0
12368 || r_type == R_ARM_ALU_PC_G1
12369 || r_type == R_ARM_ALU_PC_G2
12370 || r_type == R_ARM_ALU_SB_G0
12371 || r_type == R_ARM_ALU_SB_G1
12372 || r_type == R_ARM_ALU_SB_G2) && residual != 0)
12373 {
4eca0228 12374 _bfd_error_handler
695344c0 12375 /* xgettext:c-format */
90b6238f 12376 (_("%pB(%pA+%#" PRIx64 "): overflow whilst "
2dcf00ce
AM		 12377 "splitting %#" PRIx64 " for group relocation %s"),
12378 input_bfd, input_section, (uint64_t) rel->r_offset,
12379 (uint64_t) (signed_value < 0 ? -signed_value : signed_value),
12380 howto->name);
99059e56
RM		 12381 return bfd_reloc_overflow;
12382 }
12383
12384 /* Mask out the value and the ADD/SUB part of the opcode; take care
12385 not to destroy the S bit. */
12386 insn &= 0xff1ff000;
12387
12388 /* Set the opcode according to whether the value to go in the
12389 place is negative. */
12390 if (signed_value < 0)
12391 insn |= 1 << 22;
12392 else
12393 insn |= 1 << 23;
12394
12395 /* Encode the offset. */
12396 insn |= g_n;
4962c51a
MS		 12397
12398 bfd_put_32 (input_bfd, insn, hit_data);
12399 }
12400 return bfd_reloc_ok;
12401
12402 case R_ARM_LDR_PC_G0:
12403 case R_ARM_LDR_PC_G1:
12404 case R_ARM_LDR_PC_G2:
12405 case R_ARM_LDR_SB_G0:
12406 case R_ARM_LDR_SB_G1:
12407 case R_ARM_LDR_SB_G2:
12408 {
12409 bfd_vma insn = bfd_get_32 (input_bfd, hit_data);
99059e56 12410 bfd_vma pc = input_section->output_section->vma
4962c51a 12411 + input_section->output_offset + rel->r_offset;
31a91d61 12412 /* sb is the origin of the *segment* containing the symbol. */
62c34db3 12413 bfd_vma sb = sym_sec ? sym_sec->output_section->vma : 0;
99059e56 12414 bfd_vma residual;
4962c51a 12415 bfd_signed_vma signed_value;
99059e56
RM		 12416 int group = 0;
12417
12418 /* Determine which groups of bits to calculate. */
12419 switch (r_type)
12420 {
12421 case R_ARM_LDR_PC_G0:
12422 case R_ARM_LDR_SB_G0:
12423 group = 0;
12424 break;
12425
12426 case R_ARM_LDR_PC_G1:
12427 case R_ARM_LDR_SB_G1:
12428 group = 1;
12429 break;
12430
12431 case R_ARM_LDR_PC_G2:
12432 case R_ARM_LDR_SB_G2:
12433 group = 2;
12434 break;
12435
12436 default:
12437 abort ();
12438 }
12439
12440 /* If REL, extract the addend from the insn. If RELA, it will
12441 have already been fetched for us. */
4962c51a 12442 if (globals->use_rel)
99059e56
RM		 12443 {
12444 int negative = (insn & (1 << 23)) ? 1 : -1;
12445 signed_addend = negative * (insn & 0xfff);
12446 }
4962c51a
MS		 12447
12448 /* Compute the value (X) to go in the place. */
99059e56
RM		 12449 if (r_type == R_ARM_LDR_PC_G0
12450 || r_type == R_ARM_LDR_PC_G1
12451 || r_type == R_ARM_LDR_PC_G2)
12452 /* PC relative. */
12453 signed_value = value - pc + signed_addend;
12454 else
12455 /* Section base relative. */
12456 signed_value = value - sb + signed_addend;
12457
12458 /* Calculate the value of the relevant G_{n-1} to obtain
12459 the residual at that stage. */
b6518b38
NC		 12460 calculate_group_reloc_mask (signed_value < 0 ? - signed_value : signed_value,
12461 group - 1, &residual);
99059e56
RM		 12462
12463 /* Check for overflow. */
12464 if (residual >= 0x1000)
12465 {
4eca0228 12466 _bfd_error_handler
695344c0 12467 /* xgettext:c-format */
90b6238f 12468 (_("%pB(%pA+%#" PRIx64 "): overflow whilst "
2dcf00ce
AM		 12469 "splitting %#" PRIx64 " for group relocation %s"),
12470 input_bfd, input_section, (uint64_t) rel->r_offset,
12471 (uint64_t) (signed_value < 0 ? -signed_value : signed_value),
12472 howto->name);
99059e56
RM		 12473 return bfd_reloc_overflow;
12474 }
12475
12476 /* Mask out the value and U bit. */
12477 insn &= 0xff7ff000;
12478
12479 /* Set the U bit if the value to go in the place is non-negative. */
12480 if (signed_value >= 0)
12481 insn |= 1 << 23;
12482
12483 /* Encode the offset. */
12484 insn |= residual;
4962c51a
MS		 12485
12486 bfd_put_32 (input_bfd, insn, hit_data);
12487 }
12488 return bfd_reloc_ok;
12489
12490 case R_ARM_LDRS_PC_G0:
12491 case R_ARM_LDRS_PC_G1:
12492 case R_ARM_LDRS_PC_G2:
12493 case R_ARM_LDRS_SB_G0:
12494 case R_ARM_LDRS_SB_G1:
12495 case R_ARM_LDRS_SB_G2:
12496 {
12497 bfd_vma insn = bfd_get_32 (input_bfd, hit_data);
99059e56 12498 bfd_vma pc = input_section->output_section->vma
4962c51a 12499 + input_section->output_offset + rel->r_offset;
31a91d61 12500 /* sb is the origin of the *segment* containing the symbol. */
62c34db3 12501 bfd_vma sb = sym_sec ? sym_sec->output_section->vma : 0;
99059e56 12502 bfd_vma residual;
4962c51a 12503 bfd_signed_vma signed_value;
99059e56
RM		 12504 int group = 0;
12505
12506 /* Determine which groups of bits to calculate. */
12507 switch (r_type)
12508 {
12509 case R_ARM_LDRS_PC_G0:
12510 case R_ARM_LDRS_SB_G0:
12511 group = 0;
12512 break;
12513
12514 case R_ARM_LDRS_PC_G1:
12515 case R_ARM_LDRS_SB_G1:
12516 group = 1;
12517 break;
12518
12519 case R_ARM_LDRS_PC_G2:
12520 case R_ARM_LDRS_SB_G2:
12521 group = 2;
12522 break;
12523
12524 default:
12525 abort ();
12526 }
12527
12528 /* If REL, extract the addend from the insn. If RELA, it will
12529 have already been fetched for us. */
4962c51a 12530 if (globals->use_rel)
99059e56
RM		 12531 {
12532 int negative = (insn & (1 << 23)) ? 1 : -1;
12533 signed_addend = negative * (((insn & 0xf00) >> 4) + (insn & 0xf));
12534 }
4962c51a
MS		 12535
12536 /* Compute the value (X) to go in the place. */
99059e56
RM		 12537 if (r_type == R_ARM_LDRS_PC_G0
12538 || r_type == R_ARM_LDRS_PC_G1
12539 || r_type == R_ARM_LDRS_PC_G2)
12540 /* PC relative. */
12541 signed_value = value - pc + signed_addend;
12542 else
12543 /* Section base relative. */
12544 signed_value = value - sb + signed_addend;
12545
12546 /* Calculate the value of the relevant G_{n-1} to obtain
12547 the residual at that stage. */
b6518b38
NC		 12548 calculate_group_reloc_mask (signed_value < 0 ? - signed_value : signed_value,
12549 group - 1, &residual);
99059e56
RM		 12550
12551 /* Check for overflow. */
12552 if (residual >= 0x100)
12553 {
4eca0228 12554 _bfd_error_handler
695344c0 12555 /* xgettext:c-format */
90b6238f 12556 (_("%pB(%pA+%#" PRIx64 "): overflow whilst "
2dcf00ce
AM		 12557 "splitting %#" PRIx64 " for group relocation %s"),
12558 input_bfd, input_section, (uint64_t) rel->r_offset,
12559 (uint64_t) (signed_value < 0 ? -signed_value : signed_value),
12560 howto->name);
99059e56
RM		 12561 return bfd_reloc_overflow;
12562 }
12563
12564 /* Mask out the value and U bit. */
12565 insn &= 0xff7ff0f0;
12566
12567 /* Set the U bit if the value to go in the place is non-negative. */
12568 if (signed_value >= 0)
12569 insn |= 1 << 23;
12570
12571 /* Encode the offset. */
12572 insn |= ((residual & 0xf0) << 4) | (residual & 0xf);
4962c51a
MS		 12573
12574 bfd_put_32 (input_bfd, insn, hit_data);
12575 }
12576 return bfd_reloc_ok;
12577
12578 case R_ARM_LDC_PC_G0:
12579 case R_ARM_LDC_PC_G1:
12580 case R_ARM_LDC_PC_G2:
12581 case R_ARM_LDC_SB_G0:
12582 case R_ARM_LDC_SB_G1:
12583 case R_ARM_LDC_SB_G2:
12584 {
12585 bfd_vma insn = bfd_get_32 (input_bfd, hit_data);
99059e56 12586 bfd_vma pc = input_section->output_section->vma
4962c51a 12587 + input_section->output_offset + rel->r_offset;
31a91d61 12588 /* sb is the origin of the *segment* containing the symbol. */
62c34db3 12589 bfd_vma sb = sym_sec ? sym_sec->output_section->vma : 0;
99059e56 12590 bfd_vma residual;
4962c51a 12591 bfd_signed_vma signed_value;
99059e56
RM		 12592 int group = 0;
12593
12594 /* Determine which groups of bits to calculate. */
12595 switch (r_type)
12596 {
12597 case R_ARM_LDC_PC_G0:
12598 case R_ARM_LDC_SB_G0:
12599 group = 0;
12600 break;
12601
12602 case R_ARM_LDC_PC_G1:
12603 case R_ARM_LDC_SB_G1:
12604 group = 1;
12605 break;
12606
12607 case R_ARM_LDC_PC_G2:
12608 case R_ARM_LDC_SB_G2:
12609 group = 2;
12610 break;
12611
12612 default:
12613 abort ();
12614 }
12615
12616 /* If REL, extract the addend from the insn. If RELA, it will
12617 have already been fetched for us. */
4962c51a 12618 if (globals->use_rel)
99059e56
RM		 12619 {
12620 int negative = (insn & (1 << 23)) ? 1 : -1;
12621 signed_addend = negative * ((insn & 0xff) << 2);
12622 }
4962c51a
MS		 12623
12624 /* Compute the value (X) to go in the place. */
99059e56
RM		 12625 if (r_type == R_ARM_LDC_PC_G0
12626 || r_type == R_ARM_LDC_PC_G1
12627 || r_type == R_ARM_LDC_PC_G2)
12628 /* PC relative. */
12629 signed_value = value - pc + signed_addend;
12630 else
12631 /* Section base relative. */
12632 signed_value = value - sb + signed_addend;
12633
12634 /* Calculate the value of the relevant G_{n-1} to obtain
12635 the residual at that stage. */
b6518b38
NC		 12636 calculate_group_reloc_mask (signed_value < 0 ? - signed_value : signed_value,
12637 group - 1, &residual);
99059e56
RM		 12638
12639 /* Check for overflow. (The absolute value to go in the place must be
12640 divisible by four and, after having been divided by four, must
12641 fit in eight bits.) */
12642 if ((residual & 0x3) != 0 || residual >= 0x400)
12643 {
4eca0228 12644 _bfd_error_handler
695344c0 12645 /* xgettext:c-format */
90b6238f 12646 (_("%pB(%pA+%#" PRIx64 "): overflow whilst "
2dcf00ce
AM		 12647 "splitting %#" PRIx64 " for group relocation %s"),
12648 input_bfd, input_section, (uint64_t) rel->r_offset,
12649 (uint64_t) (signed_value < 0 ? -signed_value : signed_value),
12650 howto->name);
99059e56
RM		 12651 return bfd_reloc_overflow;
12652 }
12653
12654 /* Mask out the value and U bit. */
12655 insn &= 0xff7fff00;
12656
12657 /* Set the U bit if the value to go in the place is non-negative. */
12658 if (signed_value >= 0)
12659 insn |= 1 << 23;
12660
12661 /* Encode the offset. */
12662 insn |= residual >> 2;
4962c51a
MS		 12663
12664 bfd_put_32 (input_bfd, insn, hit_data);
12665 }
12666 return bfd_reloc_ok;
12667
72d98d16
MG		 12668 case R_ARM_THM_ALU_ABS_G0_NC:
12669 case R_ARM_THM_ALU_ABS_G1_NC:
12670 case R_ARM_THM_ALU_ABS_G2_NC:
12671 case R_ARM_THM_ALU_ABS_G3_NC:
12672 {
12673 const int shift_array[4] = {0, 8, 16, 24};
12674 bfd_vma insn = bfd_get_16 (input_bfd, hit_data);
12675 bfd_vma addr = value;
12676 int shift = shift_array[r_type - R_ARM_THM_ALU_ABS_G0_NC];
12677
12678 /* Compute address. */
12679 if (globals->use_rel)
12680 signed_addend = insn & 0xff;
12681 addr += signed_addend;
12682 if (branch_type == ST_BRANCH_TO_THUMB)
12683 addr |= 1;
12684 /* Clean imm8 insn. */
12685 insn &= 0xff00;
12686 /* And update with correct part of address. */
12687 insn |= (addr >> shift) & 0xff;
12688 /* Update insn. */
12689 bfd_put_16 (input_bfd, insn, hit_data);
12690 }
12691
12692 *unresolved_reloc_p = FALSE;
12693 return bfd_reloc_ok;
12694
e8b09b87
CL		 12695 case R_ARM_GOTOFFFUNCDESC:
12696 {
4b24dd1a 12697 if (h == NULL)
e8b09b87
CL		 12698 {
12699 struct fdpic_local *local_fdpic_cnts = elf32_arm_local_fdpic_cnts(input_bfd);
12700 int dynindx = elf_section_data (sym_sec->output_section)->dynindx;
12701 int offset = local_fdpic_cnts[r_symndx].funcdesc_offset & ~1;
12702 bfd_vma addr = dynreloc_value - sym_sec->output_section->vma;
12703 bfd_vma seg = -1;
12704
12705 if (bfd_link_pic(info) && dynindx == 0)
12706 abort();
12707
12708 /* Resolve relocation. */
12709 bfd_put_32(output_bfd, (offset + sgot->output_offset)
12710 , contents + rel->r_offset);
12711 /* Emit R_ARM_FUNCDESC_VALUE or two fixups on funcdesc if
12712 not done yet. */
12713 arm_elf_fill_funcdesc(output_bfd, info,
12714 &local_fdpic_cnts[r_symndx].funcdesc_offset,
12715 dynindx, offset, addr, dynreloc_value, seg);
12716 }
12717 else
12718 {
12719 int dynindx;
12720 int offset = eh->fdpic_cnts.funcdesc_offset & ~1;
12721 bfd_vma addr;
12722 bfd_vma seg = -1;
12723
12724 /* For static binaries, sym_sec can be null. */
12725 if (sym_sec)
12726 {
12727 dynindx = elf_section_data (sym_sec->output_section)->dynindx;
12728 addr = dynreloc_value - sym_sec->output_section->vma;
12729 }
12730 else
12731 {
12732 dynindx = 0;
12733 addr = 0;
12734 }
12735
12736 if (bfd_link_pic(info) && dynindx == 0)
12737 abort();
12738
12739 /* This case cannot occur since funcdesc is allocated by
12740 the dynamic loader so we cannot resolve the relocation. */
12741 if (h->dynindx != -1)
12742 abort();
12743
12744 /* Resolve relocation. */
12745 bfd_put_32(output_bfd, (offset + sgot->output_offset),
12746 contents + rel->r_offset);
12747 /* Emit R_ARM_FUNCDESC_VALUE on funcdesc if not done yet. */
12748 arm_elf_fill_funcdesc(output_bfd, info,
12749 &eh->fdpic_cnts.funcdesc_offset,
12750 dynindx, offset, addr, dynreloc_value, seg);
12751 }
12752 }
12753 *unresolved_reloc_p = FALSE;
12754 return bfd_reloc_ok;
12755
12756 case R_ARM_GOTFUNCDESC:
12757 {
4b24dd1a 12758 if (h != NULL)
e8b09b87
CL		 12759 {
12760 Elf_Internal_Rela outrel;
12761
12762 /* Resolve relocation. */
12763 bfd_put_32(output_bfd, ((eh->fdpic_cnts.gotfuncdesc_offset & ~1)
12764 + sgot->output_offset),
12765 contents + rel->r_offset);
12766 /* Add funcdesc and associated R_ARM_FUNCDESC_VALUE. */
12767 if(h->dynindx == -1)
12768 {
12769 int dynindx;
12770 int offset = eh->fdpic_cnts.funcdesc_offset & ~1;
12771 bfd_vma addr;
12772 bfd_vma seg = -1;
12773
12774 /* For static binaries sym_sec can be null. */
12775 if (sym_sec)
12776 {
12777 dynindx = elf_section_data (sym_sec->output_section)->dynindx;
12778 addr = dynreloc_value - sym_sec->output_section->vma;
12779 }
12780 else
12781 {
12782 dynindx = 0;
12783 addr = 0;
12784 }
12785
12786 /* Emit R_ARM_FUNCDESC_VALUE on funcdesc if not done yet. */
12787 arm_elf_fill_funcdesc(output_bfd, info,
12788 &eh->fdpic_cnts.funcdesc_offset,
12789 dynindx, offset, addr, dynreloc_value, seg);
12790 }
12791
12792 /* Add a dynamic relocation on GOT entry if not already done. */
12793 if ((eh->fdpic_cnts.gotfuncdesc_offset & 1) == 0)
12794 {
12795 if (h->dynindx == -1)
12796 {
12797 outrel.r_info = ELF32_R_INFO (0, R_ARM_RELATIVE);
12798 if (h->root.type == bfd_link_hash_undefweak)
12799 bfd_put_32(output_bfd, 0, sgot->contents
12800 + (eh->fdpic_cnts.gotfuncdesc_offset & ~1));
12801 else
12802 bfd_put_32(output_bfd, sgot->output_section->vma
12803 + sgot->output_offset
12804 + (eh->fdpic_cnts.funcdesc_offset & ~1),
12805 sgot->contents
12806 + (eh->fdpic_cnts.gotfuncdesc_offset & ~1));
12807 }
12808 else
12809 {
12810 outrel.r_info = ELF32_R_INFO (h->dynindx, R_ARM_FUNCDESC);
12811 }
12812 outrel.r_offset = sgot->output_section->vma
12813 + sgot->output_offset
12814 + (eh->fdpic_cnts.gotfuncdesc_offset & ~1);
12815 outrel.r_addend = 0;
12816 if (h->dynindx == -1 && !bfd_link_pic(info))
12817 if (h->root.type == bfd_link_hash_undefweak)
4b24dd1a 12818 arm_elf_add_rofixup(output_bfd, globals->srofixup, -1);
e8b09b87 12819 else
4b24dd1a
AM		 12820 arm_elf_add_rofixup(output_bfd, globals->srofixup,
12821 outrel.r_offset);
e8b09b87
CL		 12822 else
12823 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
12824 eh->fdpic_cnts.gotfuncdesc_offset |= 1;
12825 }
12826 }
12827 else
12828 {
12829 /* Such relocation on static function should not have been
12830 emitted by the compiler. */
12831 abort();
12832 }
12833 }
12834 *unresolved_reloc_p = FALSE;
12835 return bfd_reloc_ok;
12836
12837 case R_ARM_FUNCDESC:
12838 {
4b24dd1a 12839 if (h == NULL)
e8b09b87
CL		 12840 {
12841 struct fdpic_local *local_fdpic_cnts = elf32_arm_local_fdpic_cnts(input_bfd);
12842 Elf_Internal_Rela outrel;
12843 int dynindx = elf_section_data (sym_sec->output_section)->dynindx;
12844 int offset = local_fdpic_cnts[r_symndx].funcdesc_offset & ~1;
12845 bfd_vma addr = dynreloc_value - sym_sec->output_section->vma;
12846 bfd_vma seg = -1;
12847
12848 if (bfd_link_pic(info) && dynindx == 0)
12849 abort();
12850
12851 /* Replace static FUNCDESC relocation with a
12852 R_ARM_RELATIVE dynamic relocation or with a rofixup for
12853 executable. */
12854 outrel.r_info = ELF32_R_INFO (0, R_ARM_RELATIVE);
12855 outrel.r_offset = input_section->output_section->vma
12856 + input_section->output_offset + rel->r_offset;
12857 outrel.r_addend = 0;
12858 if (bfd_link_pic(info))
12859 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
12860 else
12861 arm_elf_add_rofixup(output_bfd, globals->srofixup, outrel.r_offset);
12862
12863 bfd_put_32 (input_bfd, sgot->output_section->vma
12864 + sgot->output_offset + offset, hit_data);
12865
12866 /* Emit R_ARM_FUNCDESC_VALUE on funcdesc if not done yet. */
12867 arm_elf_fill_funcdesc(output_bfd, info,
12868 &local_fdpic_cnts[r_symndx].funcdesc_offset,
12869 dynindx, offset, addr, dynreloc_value, seg);
12870 }
12871 else
12872 {
12873 if (h->dynindx == -1)
12874 {
12875 int dynindx;
12876 int offset = eh->fdpic_cnts.funcdesc_offset & ~1;
12877 bfd_vma addr;
12878 bfd_vma seg = -1;
12879 Elf_Internal_Rela outrel;
12880
12881 /* For static binaries sym_sec can be null. */
12882 if (sym_sec)
12883 {
12884 dynindx = elf_section_data (sym_sec->output_section)->dynindx;
12885 addr = dynreloc_value - sym_sec->output_section->vma;
12886 }
12887 else
12888 {
12889 dynindx = 0;
12890 addr = 0;
12891 }
12892
12893 if (bfd_link_pic(info) && dynindx == 0)
12894 abort();
12895
12896 /* Replace static FUNCDESC relocation with a
12897 R_ARM_RELATIVE dynamic relocation. */
12898 outrel.r_info = ELF32_R_INFO (0, R_ARM_RELATIVE);
12899 outrel.r_offset = input_section->output_section->vma
12900 + input_section->output_offset + rel->r_offset;
12901 outrel.r_addend = 0;
12902 if (bfd_link_pic(info))
12903 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
12904 else
12905 arm_elf_add_rofixup(output_bfd, globals->srofixup, outrel.r_offset);
12906
12907 bfd_put_32 (input_bfd, sgot->output_section->vma
12908 + sgot->output_offset + offset, hit_data);
12909
12910 /* Emit R_ARM_FUNCDESC_VALUE on funcdesc if not done yet. */
12911 arm_elf_fill_funcdesc(output_bfd, info,
12912 &eh->fdpic_cnts.funcdesc_offset,
12913 dynindx, offset, addr, dynreloc_value, seg);
12914 }
12915 else
12916 {
12917 Elf_Internal_Rela outrel;
12918
12919 /* Add a dynamic relocation. */
12920 outrel.r_info = ELF32_R_INFO (h->dynindx, R_ARM_FUNCDESC);
12921 outrel.r_offset = input_section->output_section->vma
12922 + input_section->output_offset + rel->r_offset;
12923 outrel.r_addend = 0;
12924 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
12925 }
12926 }
12927 }
12928 *unresolved_reloc_p = FALSE;
12929 return bfd_reloc_ok;
12930
e5d6e09e
AV		 12931 case R_ARM_THM_BF16:
12932 {
12933 bfd_vma relocation;
12934 bfd_vma upper_insn = bfd_get_16 (input_bfd, hit_data);
12935 bfd_vma lower_insn = bfd_get_16 (input_bfd, hit_data + 2);
12936
12937 if (globals->use_rel)
12938 {
12939 bfd_vma immA = (upper_insn & 0x001f);
12940 bfd_vma immB = (lower_insn & 0x07fe) >> 1;
12941 bfd_vma immC = (lower_insn & 0x0800) >> 11;
12942 addend = (immA << 12);
12943 addend |= (immB << 2);
12944 addend |= (immC << 1);
12945 addend |= 1;
12946 /* Sign extend. */
e6f65e75 12947 signed_addend = (addend & 0x10000) ? addend - (1 << 17) : addend;
e5d6e09e
AV		 12948 }
12949
e6f65e75 12950 relocation = value + signed_addend;
e5d6e09e
AV		 12951 relocation -= (input_section->output_section->vma
12952 + input_section->output_offset
12953 + rel->r_offset);
12954
12955 /* Put RELOCATION back into the insn. */
12956 {
12957 bfd_vma immA = (relocation & 0x0001f000) >> 12;
12958 bfd_vma immB = (relocation & 0x00000ffc) >> 2;
12959 bfd_vma immC = (relocation & 0x00000002) >> 1;
12960
12961 upper_insn = (upper_insn & 0xffe0) | immA;
12962 lower_insn = (lower_insn & 0xf001) | (immC << 11) | (immB << 1);
12963 }
12964
12965 /* Put the relocated value back in the object file: */
12966 bfd_put_16 (input_bfd, upper_insn, hit_data);
12967 bfd_put_16 (input_bfd, lower_insn, hit_data + 2);
12968
12969 return bfd_reloc_ok;
12970 }
12971
1889da70
AV		 12972 case R_ARM_THM_BF12:
12973 {
12974 bfd_vma relocation;
12975 bfd_vma upper_insn = bfd_get_16 (input_bfd, hit_data);
12976 bfd_vma lower_insn = bfd_get_16 (input_bfd, hit_data + 2);
12977
12978 if (globals->use_rel)
12979 {
12980 bfd_vma immA = (upper_insn & 0x0001);
12981 bfd_vma immB = (lower_insn & 0x07fe) >> 1;
12982 bfd_vma immC = (lower_insn & 0x0800) >> 11;
12983 addend = (immA << 12);
12984 addend |= (immB << 2);
12985 addend |= (immC << 1);
12986 addend |= 1;
12987 /* Sign extend. */
12988 addend = (addend & 0x1000) ? addend - (1 << 13) : addend;
e6f65e75 12989 signed_addend = addend;
1889da70
AV		 12990 }
12991
e6f65e75 12992 relocation = value + signed_addend;
1889da70
AV		 12993 relocation -= (input_section->output_section->vma
12994 + input_section->output_offset
12995 + rel->r_offset);
12996
12997 /* Put RELOCATION back into the insn. */
12998 {
12999 bfd_vma immA = (relocation & 0x00001000) >> 12;
13000 bfd_vma immB = (relocation & 0x00000ffc) >> 2;
13001 bfd_vma immC = (relocation & 0x00000002) >> 1;
13002
13003 upper_insn = (upper_insn & 0xfffe) | immA;
13004 lower_insn = (lower_insn & 0xf001) | (immC << 11) | (immB << 1);
13005 }
13006
13007 /* Put the relocated value back in the object file: */
13008 bfd_put_16 (input_bfd, upper_insn, hit_data);
13009 bfd_put_16 (input_bfd, lower_insn, hit_data + 2);
13010
13011 return bfd_reloc_ok;
13012 }
13013
1caf72a5
AV		 13014 case R_ARM_THM_BF18:
13015 {
13016 bfd_vma relocation;
13017 bfd_vma upper_insn = bfd_get_16 (input_bfd, hit_data);
13018 bfd_vma lower_insn = bfd_get_16 (input_bfd, hit_data + 2);
13019
13020 if (globals->use_rel)
13021 {
13022 bfd_vma immA = (upper_insn & 0x007f);
13023 bfd_vma immB = (lower_insn & 0x07fe) >> 1;
13024 bfd_vma immC = (lower_insn & 0x0800) >> 11;
13025 addend = (immA << 12);
13026 addend |= (immB << 2);
13027 addend |= (immC << 1);
13028 addend |= 1;
13029 /* Sign extend. */
13030 addend = (addend & 0x40000) ? addend - (1 << 19) : addend;
e6f65e75 13031 signed_addend = addend;
1caf72a5
AV		 13032 }
13033
e6f65e75 13034 relocation = value + signed_addend;
1caf72a5
AV		 13035 relocation -= (input_section->output_section->vma
13036 + input_section->output_offset
13037 + rel->r_offset);
13038
13039 /* Put RELOCATION back into the insn. */
13040 {
13041 bfd_vma immA = (relocation & 0x0007f000) >> 12;
13042 bfd_vma immB = (relocation & 0x00000ffc) >> 2;
13043 bfd_vma immC = (relocation & 0x00000002) >> 1;
13044
13045 upper_insn = (upper_insn & 0xff80) | immA;
13046 lower_insn = (lower_insn & 0xf001) | (immC << 11) | (immB << 1);
13047 }
13048
13049 /* Put the relocated value back in the object file: */
13050 bfd_put_16 (input_bfd, upper_insn, hit_data);
13051 bfd_put_16 (input_bfd, lower_insn, hit_data + 2);
13052
13053 return bfd_reloc_ok;
13054 }
13055
252b5132
RH		 13056 default:
13057 return bfd_reloc_notsupported;
13058 }
13059}
13060
98c1d4aa
NC		 13061/* Add INCREMENT to the reloc (of type HOWTO) at ADDRESS. */
13062static void
07d6d2b8
AM		 13063arm_add_to_rel (bfd * abfd,
13064 bfd_byte * address,
57e8b36a 13065 reloc_howto_type * howto,
07d6d2b8 13066 bfd_signed_vma increment)
98c1d4aa 13067{
98c1d4aa
NC		 13068 bfd_signed_vma addend;
13069
bd97cb95
DJ		 13070 if (howto->type == R_ARM_THM_CALL
13071 || howto->type == R_ARM_THM_JUMP24)
98c1d4aa 13072 {
9a5aca8c
AM		 13073 int upper_insn, lower_insn;
13074 int upper, lower;
98c1d4aa 13075
9a5aca8c
AM		 13076 upper_insn = bfd_get_16 (abfd, address);
13077 lower_insn = bfd_get_16 (abfd, address + 2);
13078 upper = upper_insn & 0x7ff;
13079 lower = lower_insn & 0x7ff;
13080
13081 addend = (upper << 12) | (lower << 1);
ddda4409 13082 addend += increment;
9a5aca8c 13083 addend >>= 1;
98c1d4aa 13084
9a5aca8c
AM		 13085 upper_insn = (upper_insn & 0xf800) | ((addend >> 11) & 0x7ff);
13086 lower_insn = (lower_insn & 0xf800) | (addend & 0x7ff);
13087
dc810e39
AM		 13088 bfd_put_16 (abfd, (bfd_vma) upper_insn, address);
13089 bfd_put_16 (abfd, (bfd_vma) lower_insn, address + 2);
9a5aca8c
AM		 13090 }
13091 else
13092 {
07d6d2b8 13093 bfd_vma contents;
9a5aca8c
AM		 13094
13095 contents = bfd_get_32 (abfd, address);
13096
13097 /* Get the (signed) value from the instruction. */
13098 addend = contents & howto->src_mask;
13099 if (addend & ((howto->src_mask + 1) >> 1))
13100 {
13101 bfd_signed_vma mask;
13102
13103 mask = -1;
13104 mask &= ~ howto->src_mask;
13105 addend |= mask;
13106 }
13107
13108 /* Add in the increment, (which is a byte value). */
13109 switch (howto->type)
13110 {
13111 default:
13112 addend += increment;
13113 break;
13114
13115 case R_ARM_PC24:
c6596c5e 13116 case R_ARM_PLT32:
5b5bb741
PB		 13117 case R_ARM_CALL:
13118 case R_ARM_JUMP24:
9a5aca8c 13119 addend <<= howto->size;
dc810e39 13120 addend += increment;
9a5aca8c
AM		 13121
13122 /* Should we check for overflow here ? */
13123
13124 /* Drop any undesired bits. */
13125 addend >>= howto->rightshift;
13126 break;
13127 }
13128
13129 contents = (contents & ~ howto->dst_mask) | (addend & howto->dst_mask);
13130
13131 bfd_put_32 (abfd, contents, address);
ddda4409 13132 }
98c1d4aa 13133}
252b5132 13134
ba93b8ac
DJ		 13135#define IS_ARM_TLS_RELOC(R_TYPE) \
13136 ((R_TYPE) == R_ARM_TLS_GD32 \
5c5a4843 13137 || (R_TYPE) == R_ARM_TLS_GD32_FDPIC \
ba93b8ac
DJ		 13138 || (R_TYPE) == R_ARM_TLS_LDO32 \
13139 || (R_TYPE) == R_ARM_TLS_LDM32 \
5c5a4843 13140 || (R_TYPE) == R_ARM_TLS_LDM32_FDPIC \
ba93b8ac
DJ		 13141 || (R_TYPE) == R_ARM_TLS_DTPOFF32 \
13142 || (R_TYPE) == R_ARM_TLS_DTPMOD32 \
13143 || (R_TYPE) == R_ARM_TLS_TPOFF32 \
13144 || (R_TYPE) == R_ARM_TLS_LE32 \
0855e32b 13145 || (R_TYPE) == R_ARM_TLS_IE32 \
5c5a4843 13146 || (R_TYPE) == R_ARM_TLS_IE32_FDPIC \
0855e32b
NS		 13147 || IS_ARM_TLS_GNU_RELOC (R_TYPE))
13148
13149/* Specific set of relocations for the gnu tls dialect. */
13150#define IS_ARM_TLS_GNU_RELOC(R_TYPE) \
13151 ((R_TYPE) == R_ARM_TLS_GOTDESC \
13152 || (R_TYPE) == R_ARM_TLS_CALL \
13153 || (R_TYPE) == R_ARM_THM_TLS_CALL \
13154 || (R_TYPE) == R_ARM_TLS_DESCSEQ \
13155 || (R_TYPE) == R_ARM_THM_TLS_DESCSEQ)
ba93b8ac 13156
252b5132 13157/* Relocate an ARM ELF section. */
906e58ca 13158
b34976b6 13159static bfd_boolean
07d6d2b8 13160elf32_arm_relocate_section (bfd * output_bfd,
57e8b36a 13161 struct bfd_link_info * info,
07d6d2b8
AM		 13162 bfd * input_bfd,
13163 asection * input_section,
13164 bfd_byte * contents,
13165 Elf_Internal_Rela * relocs,
13166 Elf_Internal_Sym * local_syms,
13167 asection ** local_sections)
252b5132 13168{
b34976b6
AM		 13169 Elf_Internal_Shdr *symtab_hdr;
13170 struct elf_link_hash_entry **sym_hashes;
13171 Elf_Internal_Rela *rel;
13172 Elf_Internal_Rela *relend;
13173 const char *name;
b32d3aa2 13174 struct elf32_arm_link_hash_table * globals;
252b5132 13175
4e7fd91e 13176 globals = elf32_arm_hash_table (info);
4dfe6ac6
NC		 13177 if (globals == NULL)
13178 return FALSE;
b491616a 13179
0ffa91dd 13180 symtab_hdr = & elf_symtab_hdr (input_bfd);
252b5132
RH		 13181 sym_hashes = elf_sym_hashes (input_bfd);
13182
13183 rel = relocs;
13184 relend = relocs + input_section->reloc_count;
13185 for (; rel < relend; rel++)
13186 {
07d6d2b8
AM		 13187 int r_type;
13188 reloc_howto_type * howto;
13189 unsigned long r_symndx;
13190 Elf_Internal_Sym * sym;
13191 asection * sec;
252b5132 13192 struct elf_link_hash_entry * h;
07d6d2b8
AM		 13193 bfd_vma relocation;
13194 bfd_reloc_status_type r;
13195 arelent bfd_reloc;
13196 char sym_type;
13197 bfd_boolean unresolved_reloc = FALSE;
f2a9dd69 13198 char *error_message = NULL;
f21f3fe0 13199
252b5132 13200 r_symndx = ELF32_R_SYM (rel->r_info);
ba96a88f 13201 r_type = ELF32_R_TYPE (rel->r_info);
b32d3aa2 13202 r_type = arm_real_reloc_type (globals, r_type);
252b5132 13203
ba96a88f 13204 if ( r_type == R_ARM_GNU_VTENTRY
99059e56
RM		 13205 || r_type == R_ARM_GNU_VTINHERIT)
13206 continue;
252b5132 13207
47aeb64c
NC		 13208 howto = bfd_reloc.howto = elf32_arm_howto_from_type (r_type);
13209
13210 if (howto == NULL)
13211 return _bfd_unrecognized_reloc (input_bfd, input_section, r_type);
252b5132 13212
252b5132
RH		 13213 h = NULL;
13214 sym = NULL;
13215 sec = NULL;
9b485d32 13216
252b5132
RH		 13217 if (r_symndx < symtab_hdr->sh_info)
13218 {
13219 sym = local_syms + r_symndx;
ba93b8ac 13220 sym_type = ELF32_ST_TYPE (sym->st_info);
252b5132 13221 sec = local_sections[r_symndx];
ffcb4889
NS		 13222
13223 /* An object file might have a reference to a local
13224 undefined symbol. This is a daft object file, but we
13225 should at least do something about it. V4BX & NONE
13226 relocations do not use the symbol and are explicitly
77b4f08f
TS		 13227 allowed to use the undefined symbol, so allow those.
13228 Likewise for relocations against STN_UNDEF. */
ffcb4889
NS		 13229 if (r_type != R_ARM_V4BX
13230 && r_type != R_ARM_NONE
77b4f08f 13231 && r_symndx != STN_UNDEF
ffcb4889
NS		 13232 && bfd_is_und_section (sec)
13233 && ELF_ST_BIND (sym->st_info) != STB_WEAK)
1a72702b
AM		 13234 (*info->callbacks->undefined_symbol)
13235 (info, bfd_elf_string_from_elf_section
13236 (input_bfd, symtab_hdr->sh_link, sym->st_name),
13237 input_bfd, input_section,
13238 rel->r_offset, TRUE);
b38cadfb 13239
4e7fd91e 13240 if (globals->use_rel)
f8df10f4 13241 {
4e7fd91e
PB		 13242 relocation = (sec->output_section->vma
13243 + sec->output_offset
13244 + sym->st_value);
0e1862bb 13245 if (!bfd_link_relocatable (info)
ab96bf03
AM		 13246 && (sec->flags & SEC_MERGE)
13247 && ELF_ST_TYPE (sym->st_info) == STT_SECTION)
f8df10f4 13248 {
4e7fd91e
PB		 13249 asection *msec;
13250 bfd_vma addend, value;
13251
39623e12 13252 switch (r_type)
4e7fd91e 13253 {
39623e12
PB		 13254 case R_ARM_MOVW_ABS_NC:
13255 case R_ARM_MOVT_ABS:
13256 value = bfd_get_32 (input_bfd, contents + rel->r_offset);
13257 addend = ((value & 0xf0000) >> 4) | (value & 0xfff);
13258 addend = (addend ^ 0x8000) - 0x8000;
13259 break;
f8df10f4 13260
39623e12
PB		 13261 case R_ARM_THM_MOVW_ABS_NC:
13262 case R_ARM_THM_MOVT_ABS:
13263 value = bfd_get_16 (input_bfd, contents + rel->r_offset)
13264 << 16;
13265 value |= bfd_get_16 (input_bfd,
13266 contents + rel->r_offset + 2);
13267 addend = ((value & 0xf7000) >> 4) | (value & 0xff)
13268 | ((value & 0x04000000) >> 15);
13269 addend = (addend ^ 0x8000) - 0x8000;
13270 break;
f8df10f4 13271
39623e12
PB		 13272 default:
13273 if (howto->rightshift
13274 || (howto->src_mask & (howto->src_mask + 1)))
13275 {
4eca0228 13276 _bfd_error_handler
695344c0 13277 /* xgettext:c-format */
2dcf00ce
AM		 13278 (_("%pB(%pA+%#" PRIx64 "): "
13279 "%s relocation against SEC_MERGE section"),
39623e12 13280 input_bfd, input_section,
2dcf00ce 13281 (uint64_t) rel->r_offset, howto->name);
39623e12
PB		 13282 return FALSE;
13283 }
13284
13285 value = bfd_get_32 (input_bfd, contents + rel->r_offset);
13286
13287 /* Get the (signed) value from the instruction. */
13288 addend = value & howto->src_mask;
13289 if (addend & ((howto->src_mask + 1) >> 1))
13290 {
13291 bfd_signed_vma mask;
13292
13293 mask = -1;
13294 mask &= ~ howto->src_mask;
13295 addend |= mask;
13296 }
13297 break;
4e7fd91e 13298 }
39623e12 13299
4e7fd91e
PB		 13300 msec = sec;
13301 addend =
13302 _bfd_elf_rel_local_sym (output_bfd, sym, &msec, addend)
13303 - relocation;
13304 addend += msec->output_section->vma + msec->output_offset;
39623e12 13305
cc643b88 13306 /* Cases here must match those in the preceding
39623e12
PB		 13307 switch statement. */
13308 switch (r_type)
13309 {
13310 case R_ARM_MOVW_ABS_NC:
13311 case R_ARM_MOVT_ABS:
13312 value = (value & 0xfff0f000) | ((addend & 0xf000) << 4)
13313 | (addend & 0xfff);
13314 bfd_put_32 (input_bfd, value, contents + rel->r_offset);
13315 break;
13316
13317 case R_ARM_THM_MOVW_ABS_NC:
13318 case R_ARM_THM_MOVT_ABS:
13319 value = (value & 0xfbf08f00) | ((addend & 0xf700) << 4)
13320 | (addend & 0xff) | ((addend & 0x0800) << 15);
13321 bfd_put_16 (input_bfd, value >> 16,
13322 contents + rel->r_offset);
13323 bfd_put_16 (input_bfd, value,
13324 contents + rel->r_offset + 2);
13325 break;
13326
13327 default:
13328 value = (value & ~ howto->dst_mask)
13329 | (addend & howto->dst_mask);
13330 bfd_put_32 (input_bfd, value, contents + rel->r_offset);
13331 break;
13332 }
f8df10f4 13333 }
f8df10f4 13334 }
4e7fd91e
PB		 13335 else
13336 relocation = _bfd_elf_rela_local_sym (output_bfd, sym, &sec, rel);
252b5132
RH		 13337 }
13338 else
13339 {
62d887d4 13340 bfd_boolean warned, ignored;
560e09e9 13341
b2a8e766
AM		 13342 RELOC_FOR_GLOBAL_SYMBOL (info, input_bfd, input_section, rel,
13343 r_symndx, symtab_hdr, sym_hashes,
13344 h, sec, relocation,
62d887d4 13345 unresolved_reloc, warned, ignored);
ba93b8ac
DJ		 13346
13347 sym_type = h->type;
252b5132
RH		 13348 }
13349
dbaa2011 13350 if (sec != NULL && discarded_section (sec))
e4067dbb 13351 RELOC_AGAINST_DISCARDED_SECTION (info, input_bfd, input_section,
545fd46b 13352 rel, 1, relend, howto, 0, contents);
ab96bf03 13353
0e1862bb 13354 if (bfd_link_relocatable (info))
ab96bf03
AM		 13355 {
13356 /* This is a relocatable link. We don't have to change
13357 anything, unless the reloc is against a section symbol,
13358 in which case we have to adjust according to where the
13359 section symbol winds up in the output section. */
13360 if (sym != NULL && ELF_ST_TYPE (sym->st_info) == STT_SECTION)
13361 {
13362 if (globals->use_rel)
13363 arm_add_to_rel (input_bfd, contents + rel->r_offset,
13364 howto, (bfd_signed_vma) sec->output_offset);
13365 else
13366 rel->r_addend += sec->output_offset;
13367 }
13368 continue;
13369 }
13370
252b5132
RH		 13371 if (h != NULL)
13372 name = h->root.root.string;
13373 else
13374 {
13375 name = (bfd_elf_string_from_elf_section
13376 (input_bfd, symtab_hdr->sh_link, sym->st_name));
13377 if (name == NULL || *name == '\0')
fd361982 13378 name = bfd_section_name (sec);
252b5132 13379 }
f21f3fe0 13380
cf35638d 13381 if (r_symndx != STN_UNDEF
ba93b8ac
DJ		 13382 && r_type != R_ARM_NONE
13383 && (h == NULL
13384 || h->root.type == bfd_link_hash_defined
13385 || h->root.type == bfd_link_hash_defweak)
13386 && IS_ARM_TLS_RELOC (r_type) != (sym_type == STT_TLS))
13387 {
4eca0228 13388 _bfd_error_handler
ba93b8ac 13389 ((sym_type == STT_TLS
695344c0 13390 /* xgettext:c-format */
2dcf00ce 13391 ? _("%pB(%pA+%#" PRIx64 "): %s used with TLS symbol %s")
695344c0 13392 /* xgettext:c-format */
2dcf00ce 13393 : _("%pB(%pA+%#" PRIx64 "): %s used with non-TLS symbol %s")),
ba93b8ac
DJ		 13394 input_bfd,
13395 input_section,
2dcf00ce 13396 (uint64_t) rel->r_offset,
ba93b8ac
DJ		 13397 howto->name,
13398 name);
13399 }
13400
0855e32b 13401 /* We call elf32_arm_final_link_relocate unless we're completely
99059e56
RM		 13402 done, i.e., the relaxation produced the final output we want,
13403 and we won't let anybody mess with it. Also, we have to do
13404 addend adjustments in case of a R_ARM_TLS_GOTDESC relocation
6a631e86 13405 both in relaxed and non-relaxed cases. */
39d911fc
TP		 13406 if ((elf32_arm_tls_transition (info, r_type, h) != (unsigned)r_type)
13407 || (IS_ARM_TLS_GNU_RELOC (r_type)
13408 && !((h ? elf32_arm_hash_entry (h)->tls_type :
13409 elf32_arm_local_got_tls_type (input_bfd)[r_symndx])
13410 & GOT_TLS_GDESC)))
13411 {
13412 r = elf32_arm_tls_relax (globals, input_bfd, input_section,
13413 contents, rel, h == NULL);
13414 /* This may have been marked unresolved because it came from
13415 a shared library. But we've just dealt with that. */
13416 unresolved_reloc = 0;
13417 }
13418 else
13419 r = bfd_reloc_continue;
b38cadfb 13420
39d911fc
TP		 13421 if (r == bfd_reloc_continue)
13422 {
13423 unsigned char branch_type =
13424 h ? ARM_GET_SYM_BRANCH_TYPE (h->target_internal)
13425 : ARM_GET_SYM_BRANCH_TYPE (sym->st_target_internal);
13426
13427 r = elf32_arm_final_link_relocate (howto, input_bfd, output_bfd,
13428 input_section, contents, rel,
13429 relocation, info, sec, name,
13430 sym_type, branch_type, h,
13431 &unresolved_reloc,
13432 &error_message);
13433 }
0945cdfd
DJ		 13434
13435 /* Dynamic relocs are not propagated for SEC_DEBUGGING sections
13436 because such sections are not SEC_ALLOC and thus ld.so will
13437 not process them. */
13438 if (unresolved_reloc
99059e56
RM		 13439 && !((input_section->flags & SEC_DEBUGGING) != 0
13440 && h->def_dynamic)
1d5316ab
AM		 13441 && _bfd_elf_section_offset (output_bfd, info, input_section,
13442 rel->r_offset) != (bfd_vma) -1)
0945cdfd 13443 {
4eca0228 13444 _bfd_error_handler
695344c0 13445 /* xgettext:c-format */
2dcf00ce
AM		 13446 (_("%pB(%pA+%#" PRIx64 "): "
13447 "unresolvable %s relocation against symbol `%s'"),
843fe662
L		 13448 input_bfd,
13449 input_section,
2dcf00ce 13450 (uint64_t) rel->r_offset,
843fe662
L		 13451 howto->name,
13452 h->root.root.string);
0945cdfd
DJ		 13453 return FALSE;
13454 }
252b5132
RH		 13455
13456 if (r != bfd_reloc_ok)
13457 {
252b5132
RH		 13458 switch (r)
13459 {
13460 case bfd_reloc_overflow:
cf919dfd
PB		 13461 /* If the overflowing reloc was to an undefined symbol,
13462 we have already printed one error message and there
13463 is no point complaining again. */
1a72702b
AM		 13464 if (!h || h->root.type != bfd_link_hash_undefined)
13465 (*info->callbacks->reloc_overflow)
13466 (info, (h ? &h->root : NULL), name, howto->name,
13467 (bfd_vma) 0, input_bfd, input_section, rel->r_offset);
252b5132
RH		 13468 break;
13469
13470 case bfd_reloc_undefined:
1a72702b
AM		 13471 (*info->callbacks->undefined_symbol)
13472 (info, name, input_bfd, input_section, rel->r_offset, TRUE);
252b5132
RH		 13473 break;
13474
13475 case bfd_reloc_outofrange:
f2a9dd69 13476 error_message = _("out of range");
252b5132
RH		 13477 goto common_error;
13478
13479 case bfd_reloc_notsupported:
f2a9dd69 13480 error_message = _("unsupported relocation");
252b5132
RH		 13481 goto common_error;
13482
13483 case bfd_reloc_dangerous:
f2a9dd69 13484 /* error_message should already be set. */
252b5132
RH		 13485 goto common_error;
13486
13487 default:
f2a9dd69 13488 error_message = _("unknown error");
8029a119 13489 /* Fall through. */
252b5132
RH		 13490
13491 common_error:
f2a9dd69 13492 BFD_ASSERT (error_message != NULL);
1a72702b
AM		 13493 (*info->callbacks->reloc_dangerous)
13494 (info, error_message, input_bfd, input_section, rel->r_offset);
252b5132
RH		 13495 break;
13496 }
13497 }
13498 }
13499
b34976b6 13500 return TRUE;
252b5132
RH		 13501}
13502
91d6fa6a 13503/* Add a new unwind edit to the list described by HEAD, TAIL. If TINDEX is zero,
2468f9c9 13504 adds the edit to the start of the list. (The list must be built in order of
91d6fa6a 13505 ascending TINDEX: the function's callers are primarily responsible for
2468f9c9
PB		 13506 maintaining that condition). */
13507
13508static void
13509add_unwind_table_edit (arm_unwind_table_edit **head,
13510 arm_unwind_table_edit **tail,
13511 arm_unwind_edit_type type,
13512 asection *linked_section,
91d6fa6a 13513 unsigned int tindex)
2468f9c9 13514{
21d799b5
NC		 13515 arm_unwind_table_edit *new_edit = (arm_unwind_table_edit *)
13516 xmalloc (sizeof (arm_unwind_table_edit));
b38cadfb 13517
2468f9c9
PB		 13518 new_edit->type = type;
13519 new_edit->linked_section = linked_section;
91d6fa6a 13520 new_edit->index = tindex;
b38cadfb 13521
91d6fa6a 13522 if (tindex > 0)
2468f9c9
PB		 13523 {
13524 new_edit->next = NULL;
13525
13526 if (*tail)
13527 (*tail)->next = new_edit;
13528
13529 (*tail) = new_edit;
13530
13531 if (!*head)
13532 (*head) = new_edit;
13533 }
13534 else
13535 {
13536 new_edit->next = *head;
13537
13538 if (!*tail)
13539 *tail = new_edit;
13540
13541 *head = new_edit;
13542 }
13543}
13544
13545static _arm_elf_section_data *get_arm_elf_section_data (asection *);
13546
13547/* Increase the size of EXIDX_SEC by ADJUST bytes. ADJUST mau be negative. */
13548static void
13549adjust_exidx_size(asection *exidx_sec, int adjust)
13550{
13551 asection *out_sec;
13552
13553 if (!exidx_sec->rawsize)
13554 exidx_sec->rawsize = exidx_sec->size;
13555
fd361982 13556 bfd_set_section_size (exidx_sec, exidx_sec->size + adjust);
2468f9c9
PB		 13557 out_sec = exidx_sec->output_section;
13558 /* Adjust size of output section. */
fd361982 13559 bfd_set_section_size (out_sec, out_sec->size +adjust);
2468f9c9
PB		 13560}
13561
13562/* Insert an EXIDX_CANTUNWIND marker at the end of a section. */
13563static void
13564insert_cantunwind_after(asection *text_sec, asection *exidx_sec)
13565{
13566 struct _arm_elf_section_data *exidx_arm_data;
13567
13568 exidx_arm_data = get_arm_elf_section_data (exidx_sec);
13569 add_unwind_table_edit (
13570 &exidx_arm_data->u.exidx.unwind_edit_list,
13571 &exidx_arm_data->u.exidx.unwind_edit_tail,
13572 INSERT_EXIDX_CANTUNWIND_AT_END, text_sec, UINT_MAX);
13573
491d01d3
YU		 13574 exidx_arm_data->additional_reloc_count++;
13575
2468f9c9
PB		 13576 adjust_exidx_size(exidx_sec, 8);
13577}
13578
13579/* Scan .ARM.exidx tables, and create a list describing edits which should be
13580 made to those tables, such that:
b38cadfb 13581
2468f9c9
PB		 13582 1. Regions without unwind data are marked with EXIDX_CANTUNWIND entries.
13583 2. Duplicate entries are merged together (EXIDX_CANTUNWIND, or unwind
99059e56 13584 codes which have been inlined into the index).
2468f9c9 13585
85fdf906
AH		 13586 If MERGE_EXIDX_ENTRIES is false, duplicate entries are not merged.
13587
2468f9c9 13588 The edits are applied when the tables are written
b38cadfb 13589 (in elf32_arm_write_section). */
2468f9c9
PB		 13590
13591bfd_boolean
13592elf32_arm_fix_exidx_coverage (asection **text_section_order,
13593 unsigned int num_text_sections,
85fdf906
AH		 13594 struct bfd_link_info *info,
13595 bfd_boolean merge_exidx_entries)
2468f9c9
PB		 13596{
13597 bfd *inp;
13598 unsigned int last_second_word = 0, i;
13599 asection *last_exidx_sec = NULL;
13600 asection *last_text_sec = NULL;
13601 int last_unwind_type = -1;
13602
13603 /* Walk over all EXIDX sections, and create backlinks from the corrsponding
13604 text sections. */
c72f2fb2 13605 for (inp = info->input_bfds; inp != NULL; inp = inp->link.next)
2468f9c9
PB		 13606 {
13607 asection *sec;
b38cadfb 13608
2468f9c9 13609 for (sec = inp->sections; sec != NULL; sec = sec->next)
99059e56 13610 {
2468f9c9
PB		 13611 struct bfd_elf_section_data *elf_sec = elf_section_data (sec);
13612 Elf_Internal_Shdr *hdr = &elf_sec->this_hdr;
b38cadfb 13613
dec9d5df 13614 if (!hdr || hdr->sh_type != SHT_ARM_EXIDX)
2468f9c9 13615 continue;
b38cadfb 13616
2468f9c9
PB		 13617 if (elf_sec->linked_to)
13618 {
13619 Elf_Internal_Shdr *linked_hdr
99059e56 13620 = &elf_section_data (elf_sec->linked_to)->this_hdr;
2468f9c9 13621 struct _arm_elf_section_data *linked_sec_arm_data
99059e56 13622 = get_arm_elf_section_data (linked_hdr->bfd_section);
2468f9c9
PB		 13623
13624 if (linked_sec_arm_data == NULL)
99059e56 13625 continue;
2468f9c9
PB		 13626
13627 /* Link this .ARM.exidx section back from the text section it
99059e56 13628 describes. */
2468f9c9
PB		 13629 linked_sec_arm_data->u.text.arm_exidx_sec = sec;
13630 }
13631 }
13632 }
13633
13634 /* Walk all text sections in order of increasing VMA. Eilminate duplicate
13635 index table entries (EXIDX_CANTUNWIND and inlined unwind opcodes),
91d6fa6a 13636 and add EXIDX_CANTUNWIND entries for sections with no unwind table data. */
2468f9c9
PB		 13637
13638 for (i = 0; i < num_text_sections; i++)
13639 {
13640 asection *sec = text_section_order[i];
13641 asection *exidx_sec;
13642 struct _arm_elf_section_data *arm_data = get_arm_elf_section_data (sec);
13643 struct _arm_elf_section_data *exidx_arm_data;
13644 bfd_byte *contents = NULL;
13645 int deleted_exidx_bytes = 0;
13646 bfd_vma j;
13647 arm_unwind_table_edit *unwind_edit_head = NULL;
13648 arm_unwind_table_edit *unwind_edit_tail = NULL;
13649 Elf_Internal_Shdr *hdr;
13650 bfd *ibfd;
13651
13652 if (arm_data == NULL)
99059e56 13653 continue;
2468f9c9
PB		 13654
13655 exidx_sec = arm_data->u.text.arm_exidx_sec;
13656 if (exidx_sec == NULL)
13657 {
13658 /* Section has no unwind data. */
13659 if (last_unwind_type == 0 || !last_exidx_sec)
13660 continue;
13661
13662 /* Ignore zero sized sections. */
13663 if (sec->size == 0)
13664 continue;
13665
13666 insert_cantunwind_after(last_text_sec, last_exidx_sec);
13667 last_unwind_type = 0;
13668 continue;
13669 }
13670
22a8f80e
PB		 13671 /* Skip /DISCARD/ sections. */
13672 if (bfd_is_abs_section (exidx_sec->output_section))
13673 continue;
13674
2468f9c9
PB		 13675 hdr = &elf_section_data (exidx_sec)->this_hdr;
13676 if (hdr->sh_type != SHT_ARM_EXIDX)
99059e56 13677 continue;
b38cadfb 13678
2468f9c9
PB		 13679 exidx_arm_data = get_arm_elf_section_data (exidx_sec);
13680 if (exidx_arm_data == NULL)
99059e56 13681 continue;
b38cadfb 13682
2468f9c9 13683 ibfd = exidx_sec->owner;
b38cadfb 13684
2468f9c9
PB		 13685 if (hdr->contents != NULL)
13686 contents = hdr->contents;
13687 else if (! bfd_malloc_and_get_section (ibfd, exidx_sec, &contents))
13688 /* An error? */
13689 continue;
13690
ac06903d
YU		 13691 if (last_unwind_type > 0)
13692 {
13693 unsigned int first_word = bfd_get_32 (ibfd, contents);
13694 /* Add cantunwind if first unwind item does not match section
13695 start. */
13696 if (first_word != sec->vma)
13697 {
13698 insert_cantunwind_after (last_text_sec, last_exidx_sec);
13699 last_unwind_type = 0;
13700 }
13701 }
13702
2468f9c9
PB		 13703 for (j = 0; j < hdr->sh_size; j += 8)
13704 {
13705 unsigned int second_word = bfd_get_32 (ibfd, contents + j + 4);
13706 int unwind_type;
13707 int elide = 0;
13708
13709 /* An EXIDX_CANTUNWIND entry. */
13710 if (second_word == 1)
13711 {
13712 if (last_unwind_type == 0)
13713 elide = 1;
13714 unwind_type = 0;
13715 }
13716 /* Inlined unwinding data. Merge if equal to previous. */
13717 else if ((second_word & 0x80000000) != 0)
13718 {
85fdf906
AH		 13719 if (merge_exidx_entries
13720 && last_second_word == second_word && last_unwind_type == 1)
2468f9c9
PB		 13721 elide = 1;
13722 unwind_type = 1;
13723 last_second_word = second_word;
13724 }
13725 /* Normal table entry. In theory we could merge these too,
13726 but duplicate entries are likely to be much less common. */
13727 else
13728 unwind_type = 2;
13729
491d01d3 13730 if (elide && !bfd_link_relocatable (info))
2468f9c9
PB		 13731 {
13732 add_unwind_table_edit (&unwind_edit_head, &unwind_edit_tail,
13733 DELETE_EXIDX_ENTRY, NULL, j / 8);
13734
13735 deleted_exidx_bytes += 8;
13736 }
13737
13738 last_unwind_type = unwind_type;
13739 }
13740
13741 /* Free contents if we allocated it ourselves. */
13742 if (contents != hdr->contents)
99059e56 13743 free (contents);
2468f9c9
PB		 13744
13745 /* Record edits to be applied later (in elf32_arm_write_section). */
13746 exidx_arm_data->u.exidx.unwind_edit_list = unwind_edit_head;
13747 exidx_arm_data->u.exidx.unwind_edit_tail = unwind_edit_tail;
b38cadfb 13748
2468f9c9
PB		 13749 if (deleted_exidx_bytes > 0)
13750 adjust_exidx_size(exidx_sec, -deleted_exidx_bytes);
13751
13752 last_exidx_sec = exidx_sec;
13753 last_text_sec = sec;
13754 }
13755
13756 /* Add terminating CANTUNWIND entry. */
491d01d3
YU		 13757 if (!bfd_link_relocatable (info) && last_exidx_sec
13758 && last_unwind_type != 0)
2468f9c9
PB		 13759 insert_cantunwind_after(last_text_sec, last_exidx_sec);
13760
13761 return TRUE;
13762}
13763
3e6b1042
DJ		 13764static bfd_boolean
13765elf32_arm_output_glue_section (struct bfd_link_info *info, bfd *obfd,
13766 bfd *ibfd, const char *name)
13767{
13768 asection *sec, *osec;
13769
3d4d4302 13770 sec = bfd_get_linker_section (ibfd, name);
3e6b1042
DJ		 13771 if (sec == NULL || (sec->flags & SEC_EXCLUDE) != 0)
13772 return TRUE;
13773
13774 osec = sec->output_section;
13775 if (elf32_arm_write_section (obfd, info, sec, sec->contents))
13776 return TRUE;
13777
13778 if (! bfd_set_section_contents (obfd, osec, sec->contents,
13779 sec->output_offset, sec->size))
13780 return FALSE;
13781
13782 return TRUE;
13783}
13784
13785static bfd_boolean
13786elf32_arm_final_link (bfd *abfd, struct bfd_link_info *info)
13787{
13788 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (info);
fe33d2fa 13789 asection *sec, *osec;
3e6b1042 13790
4dfe6ac6
NC		 13791 if (globals == NULL)
13792 return FALSE;
13793
3e6b1042
DJ		 13794 /* Invoke the regular ELF backend linker to do all the work. */
13795 if (!bfd_elf_final_link (abfd, info))
13796 return FALSE;
13797
fe33d2fa
CL		 13798 /* Process stub sections (eg BE8 encoding, ...). */
13799 struct elf32_arm_link_hash_table *htab = elf32_arm_hash_table (info);
7292b3ac 13800 unsigned int i;
cdb21a0a
NS		 13801 for (i=0; i<htab->top_id; i++)
13802 {
13803 sec = htab->stub_group[i].stub_sec;
13804 /* Only process it once, in its link_sec slot. */
13805 if (sec && i == htab->stub_group[i].link_sec->id)
13806 {
13807 osec = sec->output_section;
13808 elf32_arm_write_section (abfd, info, sec, sec->contents);
13809 if (! bfd_set_section_contents (abfd, osec, sec->contents,
13810 sec->output_offset, sec->size))
13811 return FALSE;
13812 }
fe33d2fa 13813 }
fe33d2fa 13814
3e6b1042
DJ		 13815 /* Write out any glue sections now that we have created all the
13816 stubs. */
13817 if (globals->bfd_of_glue_owner != NULL)
13818 {
13819 if (! elf32_arm_output_glue_section (info, abfd,
13820 globals->bfd_of_glue_owner,
13821 ARM2THUMB_GLUE_SECTION_NAME))
13822 return FALSE;
13823
13824 if (! elf32_arm_output_glue_section (info, abfd,
13825 globals->bfd_of_glue_owner,
13826 THUMB2ARM_GLUE_SECTION_NAME))
13827 return FALSE;
13828
13829 if (! elf32_arm_output_glue_section (info, abfd,
13830 globals->bfd_of_glue_owner,
13831 VFP11_ERRATUM_VENEER_SECTION_NAME))
13832 return FALSE;
13833
a504d23a
LA		 13834 if (! elf32_arm_output_glue_section (info, abfd,
13835 globals->bfd_of_glue_owner,
13836 STM32L4XX_ERRATUM_VENEER_SECTION_NAME))
13837 return FALSE;
13838
3e6b1042
DJ		 13839 if (! elf32_arm_output_glue_section (info, abfd,
13840 globals->bfd_of_glue_owner,
13841 ARM_BX_GLUE_SECTION_NAME))
13842 return FALSE;
13843 }
13844
13845 return TRUE;
13846}
13847
5968a7b8
NC		 13848/* Return a best guess for the machine number based on the attributes. */
13849
13850static unsigned int
13851bfd_arm_get_mach_from_attributes (bfd * abfd)
13852{
13853 int arch = bfd_elf_get_obj_attr_int (abfd, OBJ_ATTR_PROC, Tag_CPU_arch);
13854
13855 switch (arch)
13856 {
c0c468d5 13857 case TAG_CPU_ARCH_PRE_V4: return bfd_mach_arm_3M;
5968a7b8
NC		 13858 case TAG_CPU_ARCH_V4: return bfd_mach_arm_4;
13859 case TAG_CPU_ARCH_V4T: return bfd_mach_arm_4T;
13860 case TAG_CPU_ARCH_V5T: return bfd_mach_arm_5T;
13861
13862 case TAG_CPU_ARCH_V5TE:
13863 {
13864 char * name;
13865
13866 BFD_ASSERT (Tag_CPU_name < NUM_KNOWN_OBJ_ATTRIBUTES);
13867 name = elf_known_obj_attributes (abfd) [OBJ_ATTR_PROC][Tag_CPU_name].s;
13868
13869 if (name)
13870 {
13871 if (strcmp (name, "IWMMXT2") == 0)
13872 return bfd_mach_arm_iWMMXt2;
13873
13874 if (strcmp (name, "IWMMXT") == 0)
6034aab8 13875 return bfd_mach_arm_iWMMXt;
088ca6c1
NC		 13876
13877 if (strcmp (name, "XSCALE") == 0)
13878 {
13879 int wmmx;
13880
13881 BFD_ASSERT (Tag_WMMX_arch < NUM_KNOWN_OBJ_ATTRIBUTES);
13882 wmmx = elf_known_obj_attributes (abfd) [OBJ_ATTR_PROC][Tag_WMMX_arch].i;
13883 switch (wmmx)
13884 {
13885 case 1: return bfd_mach_arm_iWMMXt;
13886 case 2: return bfd_mach_arm_iWMMXt2;
13887 default: return bfd_mach_arm_XScale;
13888 }
13889 }
5968a7b8
NC		 13890 }
13891
13892 return bfd_mach_arm_5TE;
13893 }
13894
c0c468d5
TP		 13895 case TAG_CPU_ARCH_V5TEJ:
13896 return bfd_mach_arm_5TEJ;
13897 case TAG_CPU_ARCH_V6:
13898 return bfd_mach_arm_6;
13899 case TAG_CPU_ARCH_V6KZ:
13900 return bfd_mach_arm_6KZ;
13901 case TAG_CPU_ARCH_V6T2:
13902 return bfd_mach_arm_6T2;
13903 case TAG_CPU_ARCH_V6K:
13904 return bfd_mach_arm_6K;
13905 case TAG_CPU_ARCH_V7:
13906 return bfd_mach_arm_7;
13907 case TAG_CPU_ARCH_V6_M:
13908 return bfd_mach_arm_6M;
13909 case TAG_CPU_ARCH_V6S_M:
13910 return bfd_mach_arm_6SM;
13911 case TAG_CPU_ARCH_V7E_M:
13912 return bfd_mach_arm_7EM;
13913 case TAG_CPU_ARCH_V8:
13914 return bfd_mach_arm_8;
13915 case TAG_CPU_ARCH_V8R:
13916 return bfd_mach_arm_8R;
13917 case TAG_CPU_ARCH_V8M_BASE:
13918 return bfd_mach_arm_8M_BASE;
13919 case TAG_CPU_ARCH_V8M_MAIN:
13920 return bfd_mach_arm_8M_MAIN;
031254f2
AV		 13921 case TAG_CPU_ARCH_V8_1M_MAIN:
13922 return bfd_mach_arm_8_1M_MAIN;
c0c468d5 13923
5968a7b8 13924 default:
c0c468d5
TP		 13925 /* Force entry to be added for any new known Tag_CPU_arch value. */
13926 BFD_ASSERT (arch > MAX_TAG_CPU_ARCH);
13927
13928 /* Unknown Tag_CPU_arch value. */
5968a7b8
NC		 13929 return bfd_mach_arm_unknown;
13930 }
13931}
13932
c178919b
NC		 13933/* Set the right machine number. */
13934
13935static bfd_boolean
57e8b36a 13936elf32_arm_object_p (bfd *abfd)
c178919b 13937{
5a6c6817 13938 unsigned int mach;
57e8b36a 13939
5a6c6817 13940 mach = bfd_arm_get_mach_from_notes (abfd, ARM_NOTE_SECTION);
c178919b 13941
5968a7b8
NC		 13942 if (mach == bfd_mach_arm_unknown)
13943 {
13944 if (elf_elfheader (abfd)->e_flags & EF_ARM_MAVERICK_FLOAT)
13945 mach = bfd_mach_arm_ep9312;
13946 else
13947 mach = bfd_arm_get_mach_from_attributes (abfd);
13948 }
c178919b 13949
5968a7b8 13950 bfd_default_set_arch_mach (abfd, bfd_arch_arm, mach);
c178919b
NC		 13951 return TRUE;
13952}
13953
fc830a83 13954/* Function to keep ARM specific flags in the ELF header. */
3c9458e9 13955
b34976b6 13956static bfd_boolean
57e8b36a 13957elf32_arm_set_private_flags (bfd *abfd, flagword flags)
252b5132
RH		 13958{
13959 if (elf_flags_init (abfd)
13960 && elf_elfheader (abfd)->e_flags != flags)
13961 {
fc830a83
NC		 13962 if (EF_ARM_EABI_VERSION (flags) == EF_ARM_EABI_UNKNOWN)
13963 {
fd2ec330 13964 if (flags & EF_ARM_INTERWORK)
4eca0228 13965 _bfd_error_handler
90b6238f 13966 (_("warning: not setting interworking flag of %pB since it has already been specified as non-interworking"),
d003868e 13967 abfd);
fc830a83 13968 else
d003868e 13969 _bfd_error_handler
90b6238f 13970 (_("warning: clearing the interworking flag of %pB due to outside request"),
d003868e 13971 abfd);
fc830a83 13972 }
252b5132
RH		 13973 }
13974 else
13975 {
13976 elf_elfheader (abfd)->e_flags = flags;
b34976b6 13977 elf_flags_init (abfd) = TRUE;
252b5132
RH		 13978 }
13979
b34976b6 13980 return TRUE;
252b5132
RH		 13981}
13982
fc830a83 13983/* Copy backend specific data from one object module to another. */
9b485d32 13984
b34976b6 13985static bfd_boolean
57e8b36a 13986elf32_arm_copy_private_bfd_data (bfd *ibfd, bfd *obfd)
252b5132
RH		 13987{
13988 flagword in_flags;
13989 flagword out_flags;
13990
0ffa91dd 13991 if (! is_arm_elf (ibfd) || ! is_arm_elf (obfd))
b34976b6 13992 return TRUE;
252b5132 13993
fc830a83 13994 in_flags = elf_elfheader (ibfd)->e_flags;
252b5132
RH		 13995 out_flags = elf_elfheader (obfd)->e_flags;
13996
fc830a83
NC		 13997 if (elf_flags_init (obfd)
13998 && EF_ARM_EABI_VERSION (out_flags) == EF_ARM_EABI_UNKNOWN
13999 && in_flags != out_flags)
252b5132 14000 {
252b5132 14001 /* Cannot mix APCS26 and APCS32 code. */
fd2ec330 14002 if ((in_flags & EF_ARM_APCS_26) != (out_flags & EF_ARM_APCS_26))
b34976b6 14003 return FALSE;
252b5132
RH		 14004
14005 /* Cannot mix float APCS and non-float APCS code. */
fd2ec330 14006 if ((in_flags & EF_ARM_APCS_FLOAT) != (out_flags & EF_ARM_APCS_FLOAT))
b34976b6 14007 return FALSE;
252b5132
RH		 14008
14009 /* If the src and dest have different interworking flags
99059e56 14010 then turn off the interworking bit. */
fd2ec330 14011 if ((in_flags & EF_ARM_INTERWORK) != (out_flags & EF_ARM_INTERWORK))
252b5132 14012 {
fd2ec330 14013 if (out_flags & EF_ARM_INTERWORK)
d003868e 14014 _bfd_error_handler
90b6238f 14015 (_("warning: clearing the interworking flag of %pB because non-interworking code in %pB has been linked with it"),
d003868e 14016 obfd, ibfd);
252b5132 14017
fd2ec330 14018 in_flags &= ~EF_ARM_INTERWORK;
252b5132 14019 }
1006ba19
PB		 14020
14021 /* Likewise for PIC, though don't warn for this case. */
fd2ec330
PB		 14022 if ((in_flags & EF_ARM_PIC) != (out_flags & EF_ARM_PIC))
14023 in_flags &= ~EF_ARM_PIC;
252b5132
RH		 14024 }
14025
14026 elf_elfheader (obfd)->e_flags = in_flags;
b34976b6 14027 elf_flags_init (obfd) = TRUE;
252b5132 14028
e2349352 14029 return _bfd_elf_copy_private_bfd_data (ibfd, obfd);
ee065d83
PB		 14030}
14031
14032/* Values for Tag_ABI_PCS_R9_use. */
14033enum
14034{
14035 AEABI_R9_V6,
14036 AEABI_R9_SB,
14037 AEABI_R9_TLS,
14038 AEABI_R9_unused
14039};
14040
14041/* Values for Tag_ABI_PCS_RW_data. */
14042enum
14043{
14044 AEABI_PCS_RW_data_absolute,
14045 AEABI_PCS_RW_data_PCrel,
14046 AEABI_PCS_RW_data_SBrel,
14047 AEABI_PCS_RW_data_unused
14048};
14049
14050/* Values for Tag_ABI_enum_size. */
14051enum
14052{
14053 AEABI_enum_unused,
14054 AEABI_enum_short,
14055 AEABI_enum_wide,
14056 AEABI_enum_forced_wide
14057};
14058
104d59d1
JM		 14059/* Determine whether an object attribute tag takes an integer, a
14060 string or both. */
906e58ca 14061
104d59d1
JM		 14062static int
14063elf32_arm_obj_attrs_arg_type (int tag)
14064{
14065 if (tag == Tag_compatibility)
3483fe2e 14066 return ATTR_TYPE_FLAG_INT_VAL | ATTR_TYPE_FLAG_STR_VAL;
2d0bb761 14067 else if (tag == Tag_nodefaults)
3483fe2e
AS		 14068 return ATTR_TYPE_FLAG_INT_VAL | ATTR_TYPE_FLAG_NO_DEFAULT;
14069 else if (tag == Tag_CPU_raw_name || tag == Tag_CPU_name)
14070 return ATTR_TYPE_FLAG_STR_VAL;
104d59d1 14071 else if (tag < 32)
3483fe2e 14072 return ATTR_TYPE_FLAG_INT_VAL;
104d59d1 14073 else
3483fe2e 14074 return (tag & 1) != 0 ? ATTR_TYPE_FLAG_STR_VAL : ATTR_TYPE_FLAG_INT_VAL;
104d59d1
JM		 14075}
14076
5aa6ff7c
AS		 14077/* The ABI defines that Tag_conformance should be emitted first, and that
14078 Tag_nodefaults should be second (if either is defined). This sets those
14079 two positions, and bumps up the position of all the remaining tags to
14080 compensate. */
14081static int
14082elf32_arm_obj_attrs_order (int num)
14083{
3de4a297 14084 if (num == LEAST_KNOWN_OBJ_ATTRIBUTE)
5aa6ff7c 14085 return Tag_conformance;
3de4a297 14086 if (num == LEAST_KNOWN_OBJ_ATTRIBUTE + 1)
5aa6ff7c
AS		 14087 return Tag_nodefaults;
14088 if ((num - 2) < Tag_nodefaults)
14089 return num - 2;
14090 if ((num - 1) < Tag_conformance)
14091 return num - 1;
14092 return num;
14093}
14094
e8b36cd1
JM		 14095/* Attribute numbers >=64 (mod 128) can be safely ignored. */
14096static bfd_boolean
14097elf32_arm_obj_attrs_handle_unknown (bfd *abfd, int tag)
14098{
14099 if ((tag & 127) < 64)
14100 {
14101 _bfd_error_handler
90b6238f 14102 (_("%pB: unknown mandatory EABI object attribute %d"),
e8b36cd1
JM		 14103 abfd, tag);
14104 bfd_set_error (bfd_error_bad_value);
14105 return FALSE;
14106 }
14107 else
14108 {
14109 _bfd_error_handler
90b6238f 14110 (_("warning: %pB: unknown EABI object attribute %d"),
e8b36cd1
JM		 14111 abfd, tag);
14112 return TRUE;
14113 }
14114}
14115
91e22acd
AS		 14116/* Read the architecture from the Tag_also_compatible_with attribute, if any.
14117 Returns -1 if no architecture could be read. */
14118
14119static int
14120get_secondary_compatible_arch (bfd *abfd)
14121{
14122 obj_attribute *attr =
14123 &elf_known_obj_attributes_proc (abfd)[Tag_also_compatible_with];
14124
14125 /* Note: the tag and its argument below are uleb128 values, though
14126 currently-defined values fit in one byte for each. */
14127 if (attr->s
14128 && attr->s[0] == Tag_CPU_arch
14129 && (attr->s[1] & 128) != 128
14130 && attr->s[2] == 0)
14131 return attr->s[1];
14132
14133 /* This tag is "safely ignorable", so don't complain if it looks funny. */
14134 return -1;
14135}
14136
14137/* Set, or unset, the architecture of the Tag_also_compatible_with attribute.
14138 The tag is removed if ARCH is -1. */
14139
8e79c3df 14140static void
91e22acd 14141set_secondary_compatible_arch (bfd *abfd, int arch)
8e79c3df 14142{
91e22acd
AS		 14143 obj_attribute *attr =
14144 &elf_known_obj_attributes_proc (abfd)[Tag_also_compatible_with];
8e79c3df 14145
91e22acd
AS		 14146 if (arch == -1)
14147 {
14148 attr->s = NULL;
14149 return;
8e79c3df 14150 }
91e22acd
AS		 14151
14152 /* Note: the tag and its argument below are uleb128 values, though
14153 currently-defined values fit in one byte for each. */
14154 if (!attr->s)
21d799b5 14155 attr->s = (char *) bfd_alloc (abfd, 3);
91e22acd
AS		 14156 attr->s[0] = Tag_CPU_arch;
14157 attr->s[1] = arch;
14158 attr->s[2] = '\0';
8e79c3df
CM		 14159}
14160
91e22acd
AS		 14161/* Combine two values for Tag_CPU_arch, taking secondary compatibility tags
14162 into account. */
14163
14164static int
14165tag_cpu_arch_combine (bfd *ibfd, int oldtag, int *secondary_compat_out,
14166 int newtag, int secondary_compat)
8e79c3df 14167{
91e22acd
AS		 14168#define T(X) TAG_CPU_ARCH_##X
14169 int tagl, tagh, result;
14170 const int v6t2[] =
14171 {
14172 T(V6T2), /* PRE_V4. */
14173 T(V6T2), /* V4. */
14174 T(V6T2), /* V4T. */
14175 T(V6T2), /* V5T. */
14176 T(V6T2), /* V5TE. */
14177 T(V6T2), /* V5TEJ. */
14178 T(V6T2), /* V6. */
14179 T(V7), /* V6KZ. */
14180 T(V6T2) /* V6T2. */
14181 };
14182 const int v6k[] =
14183 {
14184 T(V6K), /* PRE_V4. */
14185 T(V6K), /* V4. */
14186 T(V6K), /* V4T. */
14187 T(V6K), /* V5T. */
14188 T(V6K), /* V5TE. */
14189 T(V6K), /* V5TEJ. */
14190 T(V6K), /* V6. */
14191 T(V6KZ), /* V6KZ. */
14192 T(V7), /* V6T2. */
14193 T(V6K) /* V6K. */
14194 };
14195 const int v7[] =
14196 {
14197 T(V7), /* PRE_V4. */
14198 T(V7), /* V4. */
14199 T(V7), /* V4T. */
14200 T(V7), /* V5T. */
14201 T(V7), /* V5TE. */
14202 T(V7), /* V5TEJ. */
14203 T(V7), /* V6. */
14204 T(V7), /* V6KZ. */
14205 T(V7), /* V6T2. */
14206 T(V7), /* V6K. */
14207 T(V7) /* V7. */
14208 };
14209 const int v6_m[] =
14210 {
07d6d2b8
AM		 14211 -1, /* PRE_V4. */
14212 -1, /* V4. */
91e22acd
AS		 14213 T(V6K), /* V4T. */
14214 T(V6K), /* V5T. */
14215 T(V6K), /* V5TE. */
14216 T(V6K), /* V5TEJ. */
14217 T(V6K), /* V6. */
14218 T(V6KZ), /* V6KZ. */
14219 T(V7), /* V6T2. */
14220 T(V6K), /* V6K. */
14221 T(V7), /* V7. */
14222 T(V6_M) /* V6_M. */
14223 };
14224 const int v6s_m[] =
14225 {
07d6d2b8
AM		 14226 -1, /* PRE_V4. */
14227 -1, /* V4. */
91e22acd
AS		 14228 T(V6K), /* V4T. */
14229 T(V6K), /* V5T. */
14230 T(V6K), /* V5TE. */
14231 T(V6K), /* V5TEJ. */
14232 T(V6K), /* V6. */
14233 T(V6KZ), /* V6KZ. */
14234 T(V7), /* V6T2. */
14235 T(V6K), /* V6K. */
14236 T(V7), /* V7. */
14237 T(V6S_M), /* V6_M. */
14238 T(V6S_M) /* V6S_M. */
14239 };
9e3c6df6
PB		 14240 const int v7e_m[] =
14241 {
07d6d2b8
AM		 14242 -1, /* PRE_V4. */
14243 -1, /* V4. */
9e3c6df6
PB		 14244 T(V7E_M), /* V4T. */
14245 T(V7E_M), /* V5T. */
14246 T(V7E_M), /* V5TE. */
14247 T(V7E_M), /* V5TEJ. */
14248 T(V7E_M), /* V6. */
14249 T(V7E_M), /* V6KZ. */
14250 T(V7E_M), /* V6T2. */
14251 T(V7E_M), /* V6K. */
14252 T(V7E_M), /* V7. */
14253 T(V7E_M), /* V6_M. */
14254 T(V7E_M), /* V6S_M. */
14255 T(V7E_M) /* V7E_M. */
14256 };
bca38921
MGD		 14257 const int v8[] =
14258 {
14259 T(V8), /* PRE_V4. */
14260 T(V8), /* V4. */
14261 T(V8), /* V4T. */
14262 T(V8), /* V5T. */
14263 T(V8), /* V5TE. */
14264 T(V8), /* V5TEJ. */
14265 T(V8), /* V6. */
14266 T(V8), /* V6KZ. */
14267 T(V8), /* V6T2. */
14268 T(V8), /* V6K. */
14269 T(V8), /* V7. */
14270 T(V8), /* V6_M. */
14271 T(V8), /* V6S_M. */
14272 T(V8), /* V7E_M. */
14273 T(V8) /* V8. */
14274 };
bff0500d
TP		 14275 const int v8r[] =
14276 {
14277 T(V8R), /* PRE_V4. */
14278 T(V8R), /* V4. */
14279 T(V8R), /* V4T. */
14280 T(V8R), /* V5T. */
14281 T(V8R), /* V5TE. */
14282 T(V8R), /* V5TEJ. */
14283 T(V8R), /* V6. */
14284 T(V8R), /* V6KZ. */
14285 T(V8R), /* V6T2. */
14286 T(V8R), /* V6K. */
14287 T(V8R), /* V7. */
14288 T(V8R), /* V6_M. */
14289 T(V8R), /* V6S_M. */
14290 T(V8R), /* V7E_M. */
14291 T(V8), /* V8. */
14292 T(V8R), /* V8R. */
14293 };
2fd158eb
TP		 14294 const int v8m_baseline[] =
14295 {
14296 -1, /* PRE_V4. */
14297 -1, /* V4. */
14298 -1, /* V4T. */
14299 -1, /* V5T. */
14300 -1, /* V5TE. */
14301 -1, /* V5TEJ. */
14302 -1, /* V6. */
14303 -1, /* V6KZ. */
14304 -1, /* V6T2. */
14305 -1, /* V6K. */
14306 -1, /* V7. */
14307 T(V8M_BASE), /* V6_M. */
14308 T(V8M_BASE), /* V6S_M. */
14309 -1, /* V7E_M. */
14310 -1, /* V8. */
bff0500d 14311 -1, /* V8R. */
2fd158eb
TP		 14312 T(V8M_BASE) /* V8-M BASELINE. */
14313 };
14314 const int v8m_mainline[] =
14315 {
14316 -1, /* PRE_V4. */
14317 -1, /* V4. */
14318 -1, /* V4T. */
14319 -1, /* V5T. */
14320 -1, /* V5TE. */
14321 -1, /* V5TEJ. */
14322 -1, /* V6. */
14323 -1, /* V6KZ. */
14324 -1, /* V6T2. */
14325 -1, /* V6K. */
14326 T(V8M_MAIN), /* V7. */
14327 T(V8M_MAIN), /* V6_M. */
14328 T(V8M_MAIN), /* V6S_M. */
14329 T(V8M_MAIN), /* V7E_M. */
14330 -1, /* V8. */
bff0500d 14331 -1, /* V8R. */
2fd158eb
TP		 14332 T(V8M_MAIN), /* V8-M BASELINE. */
14333 T(V8M_MAIN) /* V8-M MAINLINE. */
14334 };
031254f2
AV		 14335 const int v8_1m_mainline[] =
14336 {
14337 -1, /* PRE_V4. */
14338 -1, /* V4. */
14339 -1, /* V4T. */
14340 -1, /* V5T. */
14341 -1, /* V5TE. */
14342 -1, /* V5TEJ. */
14343 -1, /* V6. */
14344 -1, /* V6KZ. */
14345 -1, /* V6T2. */
14346 -1, /* V6K. */
14347 T(V8_1M_MAIN), /* V7. */
14348 T(V8_1M_MAIN), /* V6_M. */
14349 T(V8_1M_MAIN), /* V6S_M. */
14350 T(V8_1M_MAIN), /* V7E_M. */
14351 -1, /* V8. */
14352 -1, /* V8R. */
14353 T(V8_1M_MAIN), /* V8-M BASELINE. */
14354 T(V8_1M_MAIN), /* V8-M MAINLINE. */
14355 -1, /* Unused (18). */
14356 -1, /* Unused (19). */
14357 -1, /* Unused (20). */
14358 T(V8_1M_MAIN) /* V8.1-M MAINLINE. */
14359 };
91e22acd
AS		 14360 const int v4t_plus_v6_m[] =
14361 {
14362 -1, /* PRE_V4. */
14363 -1, /* V4. */
14364 T(V4T), /* V4T. */
14365 T(V5T), /* V5T. */
14366 T(V5TE), /* V5TE. */
14367 T(V5TEJ), /* V5TEJ. */
14368 T(V6), /* V6. */
14369 T(V6KZ), /* V6KZ. */
14370 T(V6T2), /* V6T2. */
14371 T(V6K), /* V6K. */
14372 T(V7), /* V7. */
14373 T(V6_M), /* V6_M. */
14374 T(V6S_M), /* V6S_M. */
9e3c6df6 14375 T(V7E_M), /* V7E_M. */
bca38921 14376 T(V8), /* V8. */
bff0500d 14377 -1, /* V8R. */
2fd158eb
TP		 14378 T(V8M_BASE), /* V8-M BASELINE. */
14379 T(V8M_MAIN), /* V8-M MAINLINE. */
031254f2
AV		 14380 -1, /* Unused (18). */
14381 -1, /* Unused (19). */
14382 -1, /* Unused (20). */
14383 T(V8_1M_MAIN), /* V8.1-M MAINLINE. */
91e22acd
AS		 14384 T(V4T_PLUS_V6_M) /* V4T plus V6_M. */
14385 };
14386 const int *comb[] =
14387 {
14388 v6t2,
14389 v6k,
14390 v7,
14391 v6_m,
14392 v6s_m,
9e3c6df6 14393 v7e_m,
bca38921 14394 v8,
bff0500d 14395 v8r,
2fd158eb
TP		 14396 v8m_baseline,
14397 v8m_mainline,
031254f2
AV		 14398 NULL,
14399 NULL,
14400 NULL,
14401 v8_1m_mainline,
91e22acd
AS		 14402 /* Pseudo-architecture. */
14403 v4t_plus_v6_m
14404 };
14405
14406 /* Check we've not got a higher architecture than we know about. */
14407
9e3c6df6 14408 if (oldtag > MAX_TAG_CPU_ARCH || newtag > MAX_TAG_CPU_ARCH)
91e22acd 14409 {
90b6238f 14410 _bfd_error_handler (_("error: %pB: unknown CPU architecture"), ibfd);
91e22acd
AS		 14411 return -1;
14412 }
14413
14414 /* Override old tag if we have a Tag_also_compatible_with on the output. */
14415
14416 if ((oldtag == T(V6_M) && *secondary_compat_out == T(V4T))
14417 || (oldtag == T(V4T) && *secondary_compat_out == T(V6_M)))
14418 oldtag = T(V4T_PLUS_V6_M);
14419
14420 /* And override the new tag if we have a Tag_also_compatible_with on the
14421 input. */
14422
14423 if ((newtag == T(V6_M) && secondary_compat == T(V4T))
14424 || (newtag == T(V4T) && secondary_compat == T(V6_M)))
14425 newtag = T(V4T_PLUS_V6_M);
14426
14427 tagl = (oldtag < newtag) ? oldtag : newtag;
14428 result = tagh = (oldtag > newtag) ? oldtag : newtag;
14429
14430 /* Architectures before V6KZ add features monotonically. */
14431 if (tagh <= TAG_CPU_ARCH_V6KZ)
14432 return result;
14433
4ed7ed8d 14434 result = comb[tagh - T(V6T2)] ? comb[tagh - T(V6T2)][tagl] : -1;
91e22acd
AS		 14435
14436 /* Use Tag_CPU_arch == V4T and Tag_also_compatible_with (Tag_CPU_arch V6_M)
14437 as the canonical version. */
14438 if (result == T(V4T_PLUS_V6_M))
14439 {
14440 result = T(V4T);
14441 *secondary_compat_out = T(V6_M);
14442 }
14443 else
14444 *secondary_compat_out = -1;
14445
14446 if (result == -1)
14447 {
90b6238f 14448 _bfd_error_handler (_("error: %pB: conflicting CPU architectures %d/%d"),
91e22acd
AS		 14449 ibfd, oldtag, newtag);
14450 return -1;
14451 }
14452
14453 return result;
14454#undef T
8e79c3df
CM		 14455}
14456
ac56ee8f
MGD		 14457/* Query attributes object to see if integer divide instructions may be
14458 present in an object. */
14459static bfd_boolean
14460elf32_arm_attributes_accept_div (const obj_attribute *attr)
14461{
14462 int arch = attr[Tag_CPU_arch].i;
14463 int profile = attr[Tag_CPU_arch_profile].i;
14464
14465 switch (attr[Tag_DIV_use].i)
14466 {
14467 case 0:
14468 /* Integer divide allowed if instruction contained in archetecture. */
14469 if (arch == TAG_CPU_ARCH_V7 && (profile == 'R' || profile == 'M'))
14470 return TRUE;
14471 else if (arch >= TAG_CPU_ARCH_V7E_M)
14472 return TRUE;
14473 else
14474 return FALSE;
14475
14476 case 1:
14477 /* Integer divide explicitly prohibited. */
14478 return FALSE;
14479
14480 default:
14481 /* Unrecognised case - treat as allowing divide everywhere. */
14482 case 2:
14483 /* Integer divide allowed in ARM state. */
14484 return TRUE;
14485 }
14486}
14487
14488/* Query attributes object to see if integer divide instructions are
14489 forbidden to be in the object. This is not the inverse of
14490 elf32_arm_attributes_accept_div. */
14491static bfd_boolean
14492elf32_arm_attributes_forbid_div (const obj_attribute *attr)
14493{
14494 return attr[Tag_DIV_use].i == 1;
14495}
14496
ee065d83
PB		 14497/* Merge EABI object attributes from IBFD into OBFD. Raise an error if there
14498 are conflicting attributes. */
906e58ca 14499
ee065d83 14500static bfd_boolean
50e03d47 14501elf32_arm_merge_eabi_attributes (bfd *ibfd, struct bfd_link_info *info)
ee065d83 14502{
50e03d47 14503 bfd *obfd = info->output_bfd;
104d59d1
JM		 14504 obj_attribute *in_attr;
14505 obj_attribute *out_attr;
ee065d83
PB		 14506 /* Some tags have 0 = don't care, 1 = strong requirement,
14507 2 = weak requirement. */
91e22acd 14508 static const int order_021[3] = {0, 2, 1};
ee065d83 14509 int i;
91e22acd 14510 bfd_boolean result = TRUE;
9274e9de 14511 const char *sec_name = get_elf_backend_data (ibfd)->obj_attrs_section;
ee065d83 14512
3e6b1042
DJ		 14513 /* Skip the linker stubs file. This preserves previous behavior
14514 of accepting unknown attributes in the first input file - but
14515 is that a bug? */
14516 if (ibfd->flags & BFD_LINKER_CREATED)
14517 return TRUE;
14518
9274e9de
TG		 14519 /* Skip any input that hasn't attribute section.
14520 This enables to link object files without attribute section with
14521 any others. */
14522 if (bfd_get_section_by_name (ibfd, sec_name) == NULL)
14523 return TRUE;
14524
104d59d1 14525 if (!elf_known_obj_attributes_proc (obfd)[0].i)
ee065d83
PB		 14526 {
14527 /* This is the first object. Copy the attributes. */
104d59d1 14528 _bfd_elf_copy_obj_attributes (ibfd, obfd);
004ae526 14529
cd21e546
MGD		 14530 out_attr = elf_known_obj_attributes_proc (obfd);
14531
004ae526
PB		 14532 /* Use the Tag_null value to indicate the attributes have been
14533 initialized. */
cd21e546 14534 out_attr[0].i = 1;
004ae526 14535
cd21e546
MGD		 14536 /* We do not output objects with Tag_MPextension_use_legacy - we move
14537 the attribute's value to Tag_MPextension_use. */
14538 if (out_attr[Tag_MPextension_use_legacy].i != 0)
14539 {
14540 if (out_attr[Tag_MPextension_use].i != 0
14541 && out_attr[Tag_MPextension_use_legacy].i
99059e56 14542 != out_attr[Tag_MPextension_use].i)
cd21e546
MGD		 14543 {
14544 _bfd_error_handler
871b3ab2 14545 (_("Error: %pB has both the current and legacy "
cd21e546
MGD		 14546 "Tag_MPextension_use attributes"), ibfd);
14547 result = FALSE;
14548 }
14549
14550 out_attr[Tag_MPextension_use] =
14551 out_attr[Tag_MPextension_use_legacy];
14552 out_attr[Tag_MPextension_use_legacy].type = 0;
14553 out_attr[Tag_MPextension_use_legacy].i = 0;
14554 }
14555
14556 return result;
ee065d83
PB		 14557 }
14558
104d59d1
JM		 14559 in_attr = elf_known_obj_attributes_proc (ibfd);
14560 out_attr = elf_known_obj_attributes_proc (obfd);
ee065d83
PB		 14561 /* This needs to happen before Tag_ABI_FP_number_model is merged. */
14562 if (in_attr[Tag_ABI_VFP_args].i != out_attr[Tag_ABI_VFP_args].i)
14563 {
5c294fee
TG		 14564 /* Ignore mismatches if the object doesn't use floating point or is
14565 floating point ABI independent. */
14566 if (out_attr[Tag_ABI_FP_number_model].i == AEABI_FP_number_model_none
14567 || (in_attr[Tag_ABI_FP_number_model].i != AEABI_FP_number_model_none
14568 && out_attr[Tag_ABI_VFP_args].i == AEABI_VFP_args_compatible))
ee065d83 14569 out_attr[Tag_ABI_VFP_args].i = in_attr[Tag_ABI_VFP_args].i;
5c294fee
TG		 14570 else if (in_attr[Tag_ABI_FP_number_model].i != AEABI_FP_number_model_none
14571 && in_attr[Tag_ABI_VFP_args].i != AEABI_VFP_args_compatible)
ee065d83
PB		 14572 {
14573 _bfd_error_handler
871b3ab2 14574 (_("error: %pB uses VFP register arguments, %pB does not"),
deddc40b
NS		 14575 in_attr[Tag_ABI_VFP_args].i ? ibfd : obfd,
14576 in_attr[Tag_ABI_VFP_args].i ? obfd : ibfd);
91e22acd 14577 result = FALSE;
ee065d83
PB		 14578 }
14579 }
14580
3de4a297 14581 for (i = LEAST_KNOWN_OBJ_ATTRIBUTE; i < NUM_KNOWN_OBJ_ATTRIBUTES; i++)
ee065d83
PB		 14582 {
14583 /* Merge this attribute with existing attributes. */
14584 switch (i)
14585 {
14586 case Tag_CPU_raw_name:
14587 case Tag_CPU_name:
6a631e86 14588 /* These are merged after Tag_CPU_arch. */
ee065d83
PB		 14589 break;
14590
14591 case Tag_ABI_optimization_goals:
14592 case Tag_ABI_FP_optimization_goals:
14593 /* Use the first value seen. */
14594 break;
14595
14596 case Tag_CPU_arch:
91e22acd
AS		 14597 {
14598 int secondary_compat = -1, secondary_compat_out = -1;
14599 unsigned int saved_out_attr = out_attr[i].i;
70e99720
TG		 14600 int arch_attr;
14601 static const char *name_table[] =
14602 {
91e22acd
AS		 14603 /* These aren't real CPU names, but we can't guess
14604 that from the architecture version alone. */
14605 "Pre v4",
14606 "ARM v4",
14607 "ARM v4T",
14608 "ARM v5T",
14609 "ARM v5TE",
14610 "ARM v5TEJ",
14611 "ARM v6",
14612 "ARM v6KZ",
14613 "ARM v6T2",
14614 "ARM v6K",
14615 "ARM v7",
14616 "ARM v6-M",
bca38921 14617 "ARM v6S-M",
2fd158eb
TP		 14618 "ARM v8",
14619 "",
14620 "ARM v8-M.baseline",
14621 "ARM v8-M.mainline",
91e22acd
AS		 14622 };
14623
14624 /* Merge Tag_CPU_arch and Tag_also_compatible_with. */
14625 secondary_compat = get_secondary_compatible_arch (ibfd);
14626 secondary_compat_out = get_secondary_compatible_arch (obfd);
70e99720
TG		 14627 arch_attr = tag_cpu_arch_combine (ibfd, out_attr[i].i,
14628 &secondary_compat_out,
14629 in_attr[i].i,
14630 secondary_compat);
14631
14632 /* Return with error if failed to merge. */
14633 if (arch_attr == -1)
14634 return FALSE;
14635
14636 out_attr[i].i = arch_attr;
14637
91e22acd
AS		 14638 set_secondary_compatible_arch (obfd, secondary_compat_out);
14639
14640 /* Merge Tag_CPU_name and Tag_CPU_raw_name. */
14641 if (out_attr[i].i == saved_out_attr)
14642 ; /* Leave the names alone. */
14643 else if (out_attr[i].i == in_attr[i].i)
14644 {
14645 /* The output architecture has been changed to match the
14646 input architecture. Use the input names. */
14647 out_attr[Tag_CPU_name].s = in_attr[Tag_CPU_name].s
14648 ? _bfd_elf_attr_strdup (obfd, in_attr[Tag_CPU_name].s)
14649 : NULL;
14650 out_attr[Tag_CPU_raw_name].s = in_attr[Tag_CPU_raw_name].s
14651 ? _bfd_elf_attr_strdup (obfd, in_attr[Tag_CPU_raw_name].s)
14652 : NULL;
14653 }
14654 else
14655 {
14656 out_attr[Tag_CPU_name].s = NULL;
14657 out_attr[Tag_CPU_raw_name].s = NULL;
14658 }
14659
14660 /* If we still don't have a value for Tag_CPU_name,
14661 make one up now. Tag_CPU_raw_name remains blank. */
14662 if (out_attr[Tag_CPU_name].s == NULL
14663 && out_attr[i].i < ARRAY_SIZE (name_table))
14664 out_attr[Tag_CPU_name].s =
14665 _bfd_elf_attr_strdup (obfd, name_table[out_attr[i].i]);
14666 }
14667 break;
14668
ee065d83
PB		 14669 case Tag_ARM_ISA_use:
14670 case Tag_THUMB_ISA_use:
ee065d83 14671 case Tag_WMMX_arch:
91e22acd
AS		 14672 case Tag_Advanced_SIMD_arch:
14673 /* ??? Do Advanced_SIMD (NEON) and WMMX conflict? */
ee065d83 14674 case Tag_ABI_FP_rounding:
ee065d83
PB		 14675 case Tag_ABI_FP_exceptions:
14676 case Tag_ABI_FP_user_exceptions:
14677 case Tag_ABI_FP_number_model:
75375b3e 14678 case Tag_FP_HP_extension:
91e22acd
AS		 14679 case Tag_CPU_unaligned_access:
14680 case Tag_T2EE_use:
91e22acd 14681 case Tag_MPextension_use:
a7ad558c 14682 case Tag_MVE_arch:
ee065d83
PB		 14683 /* Use the largest value specified. */
14684 if (in_attr[i].i > out_attr[i].i)
14685 out_attr[i].i = in_attr[i].i;
14686 break;
14687
75375b3e 14688 case Tag_ABI_align_preserved:
91e22acd
AS		 14689 case Tag_ABI_PCS_RO_data:
14690 /* Use the smallest value specified. */
14691 if (in_attr[i].i < out_attr[i].i)
14692 out_attr[i].i = in_attr[i].i;
14693 break;
14694
75375b3e 14695 case Tag_ABI_align_needed:
91e22acd 14696 if ((in_attr[i].i > 0 || out_attr[i].i > 0)
75375b3e
MGD		 14697 && (in_attr[Tag_ABI_align_preserved].i == 0
14698 || out_attr[Tag_ABI_align_preserved].i == 0))
ee065d83 14699 {
91e22acd
AS		 14700 /* This error message should be enabled once all non-conformant
14701 binaries in the toolchain have had the attributes set
14702 properly.
ee065d83 14703 _bfd_error_handler
871b3ab2 14704 (_("error: %pB: 8-byte data alignment conflicts with %pB"),
91e22acd
AS		 14705 obfd, ibfd);
14706 result = FALSE; */
ee065d83 14707 }
91e22acd
AS		 14708 /* Fall through. */
14709 case Tag_ABI_FP_denormal:
14710 case Tag_ABI_PCS_GOT_use:
14711 /* Use the "greatest" from the sequence 0, 2, 1, or the largest
14712 value if greater than 2 (for future-proofing). */
14713 if ((in_attr[i].i > 2 && in_attr[i].i > out_attr[i].i)
14714 || (in_attr[i].i <= 2 && out_attr[i].i <= 2
14715 && order_021[in_attr[i].i] > order_021[out_attr[i].i]))
ee065d83
PB		 14716 out_attr[i].i = in_attr[i].i;
14717 break;
91e22acd 14718
75375b3e
MGD		 14719 case Tag_Virtualization_use:
14720 /* The virtualization tag effectively stores two bits of
14721 information: the intended use of TrustZone (in bit 0), and the
14722 intended use of Virtualization (in bit 1). */
14723 if (out_attr[i].i == 0)
14724 out_attr[i].i = in_attr[i].i;
14725 else if (in_attr[i].i != 0
14726 && in_attr[i].i != out_attr[i].i)
14727 {
14728 if (in_attr[i].i <= 3 && out_attr[i].i <= 3)
14729 out_attr[i].i = 3;
14730 else
14731 {
14732 _bfd_error_handler
871b3ab2
AM		 14733 (_("error: %pB: unable to merge virtualization attributes "
14734 "with %pB"),
75375b3e
MGD		 14735 obfd, ibfd);
14736 result = FALSE;
14737 }
14738 }
14739 break;
91e22acd
AS		 14740
14741 case Tag_CPU_arch_profile:
14742 if (out_attr[i].i != in_attr[i].i)
14743 {
14744 /* 0 will merge with anything.
14745 'A' and 'S' merge to 'A'.
14746 'R' and 'S' merge to 'R'.
99059e56 14747 'M' and 'A|R|S' is an error. */
91e22acd
AS		 14748 if (out_attr[i].i == 0
14749 || (out_attr[i].i == 'S'
14750 && (in_attr[i].i == 'A' || in_attr[i].i == 'R')))
14751 out_attr[i].i = in_attr[i].i;
14752 else if (in_attr[i].i == 0
14753 || (in_attr[i].i == 'S'
14754 && (out_attr[i].i == 'A' || out_attr[i].i == 'R')))
6a631e86 14755 ; /* Do nothing. */
91e22acd
AS		 14756 else
14757 {
14758 _bfd_error_handler
90b6238f 14759 (_("error: %pB: conflicting architecture profiles %c/%c"),
91e22acd
AS		 14760 ibfd,
14761 in_attr[i].i ? in_attr[i].i : '0',
14762 out_attr[i].i ? out_attr[i].i : '0');
14763 result = FALSE;
14764 }
14765 }
14766 break;
15afaa63
TP		 14767
14768 case Tag_DSP_extension:
14769 /* No need to change output value if any of:
14770 - pre (<=) ARMv5T input architecture (do not have DSP)
14771 - M input profile not ARMv7E-M and do not have DSP. */
14772 if (in_attr[Tag_CPU_arch].i <= 3
14773 || (in_attr[Tag_CPU_arch_profile].i == 'M'
14774 && in_attr[Tag_CPU_arch].i != 13
14775 && in_attr[i].i == 0))
14776 ; /* Do nothing. */
14777 /* Output value should be 0 if DSP part of architecture, ie.
14778 - post (>=) ARMv5te architecture output
14779 - A, R or S profile output or ARMv7E-M output architecture. */
14780 else if (out_attr[Tag_CPU_arch].i >= 4
14781 && (out_attr[Tag_CPU_arch_profile].i == 'A'
14782 || out_attr[Tag_CPU_arch_profile].i == 'R'
14783 || out_attr[Tag_CPU_arch_profile].i == 'S'
14784 || out_attr[Tag_CPU_arch].i == 13))
14785 out_attr[i].i = 0;
14786 /* Otherwise, DSP instructions are added and not part of output
14787 architecture. */
14788 else
14789 out_attr[i].i = 1;
14790 break;
14791
75375b3e 14792 case Tag_FP_arch:
62f3b8c8 14793 {
4547cb56
NC		 14794 /* Tag_ABI_HardFP_use is handled along with Tag_FP_arch since
14795 the meaning of Tag_ABI_HardFP_use depends on Tag_FP_arch
14796 when it's 0. It might mean absence of FP hardware if
99654aaf 14797 Tag_FP_arch is zero. */
4547cb56 14798
a715796b 14799#define VFP_VERSION_COUNT 9
62f3b8c8
PB		 14800 static const struct
14801 {
14802 int ver;
14803 int regs;
bca38921 14804 } vfp_versions[VFP_VERSION_COUNT] =
62f3b8c8
PB		 14805 {
14806 {0, 0},
14807 {1, 16},
14808 {2, 16},
14809 {3, 32},
14810 {3, 16},
14811 {4, 32},
bca38921 14812 {4, 16},
a715796b
TG		 14813 {8, 32},
14814 {8, 16}
62f3b8c8
PB		 14815 };
14816 int ver;
14817 int regs;
14818 int newval;
14819
4547cb56
NC		 14820 /* If the output has no requirement about FP hardware,
14821 follow the requirement of the input. */
14822 if (out_attr[i].i == 0)
14823 {
4ec192e6
RE		 14824 /* This assert is still reasonable, we shouldn't
14825 produce the suspicious build attribute
14826 combination (See below for in_attr). */
4547cb56
NC		 14827 BFD_ASSERT (out_attr[Tag_ABI_HardFP_use].i == 0);
14828 out_attr[i].i = in_attr[i].i;
14829 out_attr[Tag_ABI_HardFP_use].i
14830 = in_attr[Tag_ABI_HardFP_use].i;
14831 break;
14832 }
14833 /* If the input has no requirement about FP hardware, do
14834 nothing. */
14835 else if (in_attr[i].i == 0)
14836 {
4ec192e6
RE		 14837 /* We used to assert that Tag_ABI_HardFP_use was
14838 zero here, but we should never assert when
14839 consuming an object file that has suspicious
14840 build attributes. The single precision variant
14841 of 'no FP architecture' is still 'no FP
14842 architecture', so we just ignore the tag in this
14843 case. */
4547cb56
NC		 14844 break;
14845 }
14846
14847 /* Both the input and the output have nonzero Tag_FP_arch.
99654aaf 14848 So Tag_ABI_HardFP_use is implied by Tag_FP_arch when it's zero. */
4547cb56
NC		 14849
14850 /* If both the input and the output have zero Tag_ABI_HardFP_use,
14851 do nothing. */
14852 if (in_attr[Tag_ABI_HardFP_use].i == 0
14853 && out_attr[Tag_ABI_HardFP_use].i == 0)
14854 ;
14855 /* If the input and the output have different Tag_ABI_HardFP_use,
99654aaf 14856 the combination of them is 0 (implied by Tag_FP_arch). */
4547cb56
NC		 14857 else if (in_attr[Tag_ABI_HardFP_use].i
14858 != out_attr[Tag_ABI_HardFP_use].i)
99654aaf 14859 out_attr[Tag_ABI_HardFP_use].i = 0;
4547cb56
NC		 14860
14861 /* Now we can handle Tag_FP_arch. */
14862
bca38921
MGD		 14863 /* Values of VFP_VERSION_COUNT or more aren't defined, so just
14864 pick the biggest. */
14865 if (in_attr[i].i >= VFP_VERSION_COUNT
14866 && in_attr[i].i > out_attr[i].i)
62f3b8c8
PB		 14867 {
14868 out_attr[i] = in_attr[i];
14869 break;
14870 }
14871 /* The output uses the superset of input features
14872 (ISA version) and registers. */
14873 ver = vfp_versions[in_attr[i].i].ver;
14874 if (ver < vfp_versions[out_attr[i].i].ver)
14875 ver = vfp_versions[out_attr[i].i].ver;
14876 regs = vfp_versions[in_attr[i].i].regs;
14877 if (regs < vfp_versions[out_attr[i].i].regs)
14878 regs = vfp_versions[out_attr[i].i].regs;
14879 /* This assumes all possible supersets are also a valid
99059e56 14880 options. */
bca38921 14881 for (newval = VFP_VERSION_COUNT - 1; newval > 0; newval--)
62f3b8c8
PB		 14882 {
14883 if (regs == vfp_versions[newval].regs
14884 && ver == vfp_versions[newval].ver)
14885 break;
14886 }
14887 out_attr[i].i = newval;
14888 }
b1cc4aeb 14889 break;
ee065d83
PB		 14890 case Tag_PCS_config:
14891 if (out_attr[i].i == 0)
14892 out_attr[i].i = in_attr[i].i;
b6009aca 14893 else if (in_attr[i].i != 0 && out_attr[i].i != in_attr[i].i)
ee065d83
PB		 14894 {
14895 /* It's sometimes ok to mix different configs, so this is only
99059e56 14896 a warning. */
ee065d83 14897 _bfd_error_handler
90b6238f 14898 (_("warning: %pB: conflicting platform configuration"), ibfd);
ee065d83
PB		 14899 }
14900 break;
14901 case Tag_ABI_PCS_R9_use:
004ae526
PB		 14902 if (in_attr[i].i != out_attr[i].i
14903 && out_attr[i].i != AEABI_R9_unused
ee065d83
PB		 14904 && in_attr[i].i != AEABI_R9_unused)
14905 {
14906 _bfd_error_handler
90b6238f 14907 (_("error: %pB: conflicting use of R9"), ibfd);
91e22acd 14908 result = FALSE;
ee065d83
PB		 14909 }
14910 if (out_attr[i].i == AEABI_R9_unused)
14911 out_attr[i].i = in_attr[i].i;
14912 break;
14913 case Tag_ABI_PCS_RW_data:
14914 if (in_attr[i].i == AEABI_PCS_RW_data_SBrel
14915 && out_attr[Tag_ABI_PCS_R9_use].i != AEABI_R9_SB
14916 && out_attr[Tag_ABI_PCS_R9_use].i != AEABI_R9_unused)
14917 {
14918 _bfd_error_handler
871b3ab2 14919 (_("error: %pB: SB relative addressing conflicts with use of R9"),
ee065d83 14920 ibfd);
91e22acd 14921 result = FALSE;
ee065d83
PB		 14922 }
14923 /* Use the smallest value specified. */
14924 if (in_attr[i].i < out_attr[i].i)
14925 out_attr[i].i = in_attr[i].i;
14926 break;
ee065d83 14927 case Tag_ABI_PCS_wchar_t:
a9dc9481
JM		 14928 if (out_attr[i].i && in_attr[i].i && out_attr[i].i != in_attr[i].i
14929 && !elf_arm_tdata (obfd)->no_wchar_size_warning)
ee065d83
PB		 14930 {
14931 _bfd_error_handler
871b3ab2 14932 (_("warning: %pB uses %u-byte wchar_t yet the output is to use %u-byte wchar_t; use of wchar_t values across objects may fail"),
a9dc9481 14933 ibfd, in_attr[i].i, out_attr[i].i);
ee065d83 14934 }
a9dc9481 14935 else if (in_attr[i].i && !out_attr[i].i)
ee065d83
PB		 14936 out_attr[i].i = in_attr[i].i;
14937 break;
ee065d83
PB		 14938 case Tag_ABI_enum_size:
14939 if (in_attr[i].i != AEABI_enum_unused)
14940 {
14941 if (out_attr[i].i == AEABI_enum_unused
14942 || out_attr[i].i == AEABI_enum_forced_wide)
14943 {
14944 /* The existing object is compatible with anything.
14945 Use whatever requirements the new object has. */
14946 out_attr[i].i = in_attr[i].i;
14947 }
14948 else if (in_attr[i].i != AEABI_enum_forced_wide
bf21ed78 14949 && out_attr[i].i != in_attr[i].i
0ffa91dd 14950 && !elf_arm_tdata (obfd)->no_enum_size_warning)
ee065d83 14951 {
91e22acd 14952 static const char *aeabi_enum_names[] =
bf21ed78 14953 { "", "variable-size", "32-bit", "" };
91e22acd
AS		 14954 const char *in_name =
14955 in_attr[i].i < ARRAY_SIZE(aeabi_enum_names)
14956 ? aeabi_enum_names[in_attr[i].i]
14957 : "<unknown>";
14958 const char *out_name =
14959 out_attr[i].i < ARRAY_SIZE(aeabi_enum_names)
14960 ? aeabi_enum_names[out_attr[i].i]
14961 : "<unknown>";
ee065d83 14962 _bfd_error_handler
871b3ab2 14963 (_("warning: %pB uses %s enums yet the output is to use %s enums; use of enum values across objects may fail"),
91e22acd 14964 ibfd, in_name, out_name);
ee065d83
PB		 14965 }
14966 }
14967 break;
14968 case Tag_ABI_VFP_args:
14969 /* Aready done. */
14970 break;
14971 case Tag_ABI_WMMX_args:
14972 if (in_attr[i].i != out_attr[i].i)
14973 {
14974 _bfd_error_handler
871b3ab2 14975 (_("error: %pB uses iWMMXt register arguments, %pB does not"),
ee065d83 14976 ibfd, obfd);
91e22acd 14977 result = FALSE;
ee065d83
PB		 14978 }
14979 break;
7b86a9fa
AS		 14980 case Tag_compatibility:
14981 /* Merged in target-independent code. */
14982 break;
91e22acd 14983 case Tag_ABI_HardFP_use:
4547cb56 14984 /* This is handled along with Tag_FP_arch. */
91e22acd
AS		 14985 break;
14986 case Tag_ABI_FP_16bit_format:
14987 if (in_attr[i].i != 0 && out_attr[i].i != 0)
14988 {
14989 if (in_attr[i].i != out_attr[i].i)
14990 {
14991 _bfd_error_handler
871b3ab2 14992 (_("error: fp16 format mismatch between %pB and %pB"),
91e22acd
AS		 14993 ibfd, obfd);
14994 result = FALSE;
14995 }
14996 }
14997 if (in_attr[i].i != 0)
14998 out_attr[i].i = in_attr[i].i;
14999 break;
7b86a9fa 15000
cd21e546 15001 case Tag_DIV_use:
ac56ee8f
MGD		 15002 /* A value of zero on input means that the divide instruction may
15003 be used if available in the base architecture as specified via
15004 Tag_CPU_arch and Tag_CPU_arch_profile. A value of 1 means that
15005 the user did not want divide instructions. A value of 2
15006 explicitly means that divide instructions were allowed in ARM
15007 and Thumb state. */
15008 if (in_attr[i].i == out_attr[i].i)
15009 /* Do nothing. */ ;
15010 else if (elf32_arm_attributes_forbid_div (in_attr)
15011 && !elf32_arm_attributes_accept_div (out_attr))
15012 out_attr[i].i = 1;
15013 else if (elf32_arm_attributes_forbid_div (out_attr)
15014 && elf32_arm_attributes_accept_div (in_attr))
15015 out_attr[i].i = in_attr[i].i;
15016 else if (in_attr[i].i == 2)
15017 out_attr[i].i = in_attr[i].i;
cd21e546
MGD		 15018 break;
15019
15020 case Tag_MPextension_use_legacy:
15021 /* We don't output objects with Tag_MPextension_use_legacy - we
15022 move the value to Tag_MPextension_use. */
15023 if (in_attr[i].i != 0 && in_attr[Tag_MPextension_use].i != 0)
15024 {
15025 if (in_attr[Tag_MPextension_use].i != in_attr[i].i)
15026 {
15027 _bfd_error_handler
871b3ab2 15028 (_("%pB has both the current and legacy "
b38cadfb 15029 "Tag_MPextension_use attributes"),
cd21e546
MGD		 15030 ibfd);
15031 result = FALSE;
15032 }
15033 }
15034
15035 if (in_attr[i].i > out_attr[Tag_MPextension_use].i)
15036 out_attr[Tag_MPextension_use] = in_attr[i];
15037
15038 break;
15039
91e22acd 15040 case Tag_nodefaults:
2d0bb761
AS		 15041 /* This tag is set if it exists, but the value is unused (and is
15042 typically zero). We don't actually need to do anything here -
15043 the merge happens automatically when the type flags are merged
15044 below. */
91e22acd
AS		 15045 break;
15046 case Tag_also_compatible_with:
15047 /* Already done in Tag_CPU_arch. */
15048 break;
15049 case Tag_conformance:
15050 /* Keep the attribute if it matches. Throw it away otherwise.
15051 No attribute means no claim to conform. */
15052 if (!in_attr[i].s || !out_attr[i].s
15053 || strcmp (in_attr[i].s, out_attr[i].s) != 0)
15054 out_attr[i].s = NULL;
15055 break;
3cfad14c 15056
91e22acd 15057 default:
e8b36cd1
JM		 15058 result
15059 = result && _bfd_elf_merge_unknown_attribute_low (ibfd, obfd, i);
91e22acd
AS		 15060 }
15061
15062 /* If out_attr was copied from in_attr then it won't have a type yet. */
15063 if (in_attr[i].type && !out_attr[i].type)
15064 out_attr[i].type = in_attr[i].type;
ee065d83
PB		 15065 }
15066
104d59d1 15067 /* Merge Tag_compatibility attributes and any common GNU ones. */
50e03d47 15068 if (!_bfd_elf_merge_object_attributes (ibfd, info))
5488d830 15069 return FALSE;
ee065d83 15070
104d59d1 15071 /* Check for any attributes not known on ARM. */
e8b36cd1 15072 result &= _bfd_elf_merge_unknown_attribute_list (ibfd, obfd);
91e22acd 15073
91e22acd 15074 return result;
252b5132
RH		 15075}
15076
3a4a14e9
PB		 15077
15078/* Return TRUE if the two EABI versions are incompatible. */
15079
15080static bfd_boolean
15081elf32_arm_versions_compatible (unsigned iver, unsigned over)
15082{
15083 /* v4 and v5 are the same spec before and after it was released,
15084 so allow mixing them. */
15085 if ((iver == EF_ARM_EABI_VER4 && over == EF_ARM_EABI_VER5)
15086 || (iver == EF_ARM_EABI_VER5 && over == EF_ARM_EABI_VER4))
15087 return TRUE;
15088
15089 return (iver == over);
15090}
15091
252b5132
RH		 15092/* Merge backend specific data from an object file to the output
15093 object file when linking. */
9b485d32 15094
b34976b6 15095static bfd_boolean
50e03d47 15096elf32_arm_merge_private_bfd_data (bfd *, struct bfd_link_info *);
252b5132 15097
9b485d32
NC		 15098/* Display the flags field. */
15099
b34976b6 15100static bfd_boolean
57e8b36a 15101elf32_arm_print_private_bfd_data (bfd *abfd, void * ptr)
252b5132 15102{
fc830a83
NC		 15103 FILE * file = (FILE *) ptr;
15104 unsigned long flags;
252b5132
RH		 15105
15106 BFD_ASSERT (abfd != NULL && ptr != NULL);
15107
15108 /* Print normal ELF private data. */
15109 _bfd_elf_print_private_bfd_data (abfd, ptr);
15110
fc830a83 15111 flags = elf_elfheader (abfd)->e_flags;
9b485d32
NC		 15112 /* Ignore init flag - it may not be set, despite the flags field
15113 containing valid data. */
252b5132 15114
9b485d32 15115 fprintf (file, _("private flags = %lx:"), elf_elfheader (abfd)->e_flags);
252b5132 15116
fc830a83
NC		 15117 switch (EF_ARM_EABI_VERSION (flags))
15118 {
15119 case EF_ARM_EABI_UNKNOWN:
4cc11e76 15120 /* The following flag bits are GNU extensions and not part of the
fc830a83
NC		 15121 official ARM ELF extended ABI. Hence they are only decoded if
15122 the EABI version is not set. */
fd2ec330 15123 if (flags & EF_ARM_INTERWORK)
9b485d32 15124 fprintf (file, _(" [interworking enabled]"));
9a5aca8c 15125
fd2ec330 15126 if (flags & EF_ARM_APCS_26)
6c571f00 15127 fprintf (file, " [APCS-26]");
fc830a83 15128 else
6c571f00 15129 fprintf (file, " [APCS-32]");
9a5aca8c 15130
96a846ea
RE		 15131 if (flags & EF_ARM_VFP_FLOAT)
15132 fprintf (file, _(" [VFP float format]"));
fde78edd
NC		 15133 else if (flags & EF_ARM_MAVERICK_FLOAT)
15134 fprintf (file, _(" [Maverick float format]"));
96a846ea
RE		 15135 else
15136 fprintf (file, _(" [FPA float format]"));
15137
fd2ec330 15138 if (flags & EF_ARM_APCS_FLOAT)
9b485d32 15139 fprintf (file, _(" [floats passed in float registers]"));
9a5aca8c 15140
fd2ec330 15141 if (flags & EF_ARM_PIC)
9b485d32 15142 fprintf (file, _(" [position independent]"));
fc830a83 15143
fd2ec330 15144 if (flags & EF_ARM_NEW_ABI)
9b485d32 15145 fprintf (file, _(" [new ABI]"));
9a5aca8c 15146
fd2ec330 15147 if (flags & EF_ARM_OLD_ABI)
9b485d32 15148 fprintf (file, _(" [old ABI]"));
9a5aca8c 15149
fd2ec330 15150 if (flags & EF_ARM_SOFT_FLOAT)
9b485d32 15151 fprintf (file, _(" [software FP]"));
9a5aca8c 15152
96a846ea
RE		 15153 flags &= ~(EF_ARM_INTERWORK | EF_ARM_APCS_26 | EF_ARM_APCS_FLOAT
15154 | EF_ARM_PIC | EF_ARM_NEW_ABI | EF_ARM_OLD_ABI
fde78edd
NC		 15155 | EF_ARM_SOFT_FLOAT | EF_ARM_VFP_FLOAT
15156 | EF_ARM_MAVERICK_FLOAT);
fc830a83 15157 break;
9a5aca8c 15158
fc830a83 15159 case EF_ARM_EABI_VER1:
9b485d32 15160 fprintf (file, _(" [Version1 EABI]"));
9a5aca8c 15161
fc830a83 15162 if (flags & EF_ARM_SYMSARESORTED)
9b485d32 15163 fprintf (file, _(" [sorted symbol table]"));
fc830a83 15164 else
9b485d32 15165 fprintf (file, _(" [unsorted symbol table]"));
9a5aca8c 15166
fc830a83
NC		 15167 flags &= ~ EF_ARM_SYMSARESORTED;
15168 break;
9a5aca8c 15169
fd2ec330
PB		 15170 case EF_ARM_EABI_VER2:
15171 fprintf (file, _(" [Version2 EABI]"));
15172
15173 if (flags & EF_ARM_SYMSARESORTED)
15174 fprintf (file, _(" [sorted symbol table]"));
15175 else
15176 fprintf (file, _(" [unsorted symbol table]"));
15177
15178 if (flags & EF_ARM_DYNSYMSUSESEGIDX)
15179 fprintf (file, _(" [dynamic symbols use segment index]"));
15180
15181 if (flags & EF_ARM_MAPSYMSFIRST)
15182 fprintf (file, _(" [mapping symbols precede others]"));
15183
99e4ae17 15184 flags &= ~(EF_ARM_SYMSARESORTED | EF_ARM_DYNSYMSUSESEGIDX
fd2ec330
PB		 15185 | EF_ARM_MAPSYMSFIRST);
15186 break;
15187
d507cf36
PB		 15188 case EF_ARM_EABI_VER3:
15189 fprintf (file, _(" [Version3 EABI]"));
8cb51566
PB		 15190 break;
15191
15192 case EF_ARM_EABI_VER4:
15193 fprintf (file, _(" [Version4 EABI]"));
3a4a14e9 15194 goto eabi;
d507cf36 15195
3a4a14e9
PB		 15196 case EF_ARM_EABI_VER5:
15197 fprintf (file, _(" [Version5 EABI]"));
3bfcb652
NC		 15198
15199 if (flags & EF_ARM_ABI_FLOAT_SOFT)
15200 fprintf (file, _(" [soft-float ABI]"));
15201
15202 if (flags & EF_ARM_ABI_FLOAT_HARD)
15203 fprintf (file, _(" [hard-float ABI]"));
15204
15205 flags &= ~(EF_ARM_ABI_FLOAT_SOFT | EF_ARM_ABI_FLOAT_HARD);
15206
3a4a14e9 15207 eabi:
d507cf36
PB		 15208 if (flags & EF_ARM_BE8)
15209 fprintf (file, _(" [BE8]"));
15210
15211 if (flags & EF_ARM_LE8)
15212 fprintf (file, _(" [LE8]"));
15213
15214 flags &= ~(EF_ARM_LE8 | EF_ARM_BE8);
15215 break;
15216
fc830a83 15217 default:
9b485d32 15218 fprintf (file, _(" <EABI version unrecognised>"));
fc830a83
NC		 15219 break;
15220 }
252b5132 15221
fc830a83 15222 flags &= ~ EF_ARM_EABIMASK;
252b5132 15223
fc830a83 15224 if (flags & EF_ARM_RELEXEC)
9b485d32 15225 fprintf (file, _(" [relocatable executable]"));
252b5132 15226
18a20338
CL		 15227 if (flags & EF_ARM_PIC)
15228 fprintf (file, _(" [position independent]"));
15229
15230 if (elf_elfheader (abfd)->e_ident[EI_OSABI] == ELFOSABI_ARM_FDPIC)
15231 fprintf (file, _(" [FDPIC ABI supplement]"));
15232
15233 flags &= ~ (EF_ARM_RELEXEC | EF_ARM_PIC);
fc830a83
NC		 15234
15235 if (flags)
9b485d32 15236 fprintf (file, _("<Unrecognised flag bits set>"));
9a5aca8c 15237
252b5132
RH		 15238 fputc ('\n', file);
15239
b34976b6 15240 return TRUE;
252b5132
RH		 15241}
15242
15243static int
57e8b36a 15244elf32_arm_get_symbol_type (Elf_Internal_Sym * elf_sym, int type)
252b5132 15245{
2f0ca46a
NC		 15246 switch (ELF_ST_TYPE (elf_sym->st_info))
15247 {
15248 case STT_ARM_TFUNC:
15249 return ELF_ST_TYPE (elf_sym->st_info);
ce855c42 15250
2f0ca46a
NC		 15251 case STT_ARM_16BIT:
15252 /* If the symbol is not an object, return the STT_ARM_16BIT flag.
15253 This allows us to distinguish between data used by Thumb instructions
15254 and non-data (which is probably code) inside Thumb regions of an
15255 executable. */
1a0eb693 15256 if (type != STT_OBJECT && type != STT_TLS)
2f0ca46a
NC		 15257 return ELF_ST_TYPE (elf_sym->st_info);
15258 break;
9a5aca8c 15259
ce855c42
NC		 15260 default:
15261 break;
2f0ca46a
NC		 15262 }
15263
15264 return type;
252b5132 15265}
f21f3fe0 15266
252b5132 15267static asection *
07adf181
AM		 15268elf32_arm_gc_mark_hook (asection *sec,
15269 struct bfd_link_info *info,
15270 Elf_Internal_Rela *rel,
15271 struct elf_link_hash_entry *h,
15272 Elf_Internal_Sym *sym)
252b5132
RH		 15273{
15274 if (h != NULL)
07adf181 15275 switch (ELF32_R_TYPE (rel->r_info))
252b5132
RH		 15276 {
15277 case R_ARM_GNU_VTINHERIT:
15278 case R_ARM_GNU_VTENTRY:
07adf181
AM		 15279 return NULL;
15280 }
9ad5cbcf 15281
07adf181 15282 return _bfd_elf_gc_mark_hook (sec, info, rel, h, sym);
252b5132
RH		 15283}
15284
780a67af
NC		 15285/* Look through the relocs for a section during the first phase. */
15286
b34976b6 15287static bfd_boolean
57e8b36a
NC		 15288elf32_arm_check_relocs (bfd *abfd, struct bfd_link_info *info,
15289 asection *sec, const Elf_Internal_Rela *relocs)
252b5132 15290{
b34976b6
AM		 15291 Elf_Internal_Shdr *symtab_hdr;
15292 struct elf_link_hash_entry **sym_hashes;
b34976b6
AM		 15293 const Elf_Internal_Rela *rel;
15294 const Elf_Internal_Rela *rel_end;
15295 bfd *dynobj;
5e681ec4 15296 asection *sreloc;
5e681ec4 15297 struct elf32_arm_link_hash_table *htab;
f6e32f6d
RS		 15298 bfd_boolean call_reloc_p;
15299 bfd_boolean may_become_dynamic_p;
15300 bfd_boolean may_need_local_target_p;
ce98a316 15301 unsigned long nsyms;
9a5aca8c 15302
0e1862bb 15303 if (bfd_link_relocatable (info))
b34976b6 15304 return TRUE;
9a5aca8c 15305
0ffa91dd
NC		 15306 BFD_ASSERT (is_arm_elf (abfd));
15307
5e681ec4 15308 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 15309 if (htab == NULL)
15310 return FALSE;
15311
5e681ec4 15312 sreloc = NULL;
9a5aca8c 15313
67687978
PB		 15314 /* Create dynamic sections for relocatable executables so that we can
15315 copy relocations. */
15316 if (htab->root.is_relocatable_executable
15317 && ! htab->root.dynamic_sections_created)
15318 {
15319 if (! _bfd_elf_link_create_dynamic_sections (abfd, info))
15320 return FALSE;
15321 }
15322
cbc704f3
RS		 15323 if (htab->root.dynobj == NULL)
15324 htab->root.dynobj = abfd;
34e77a92
RS		 15325 if (!create_ifunc_sections (info))
15326 return FALSE;
cbc704f3
RS		 15327
15328 dynobj = htab->root.dynobj;
15329
0ffa91dd 15330 symtab_hdr = & elf_symtab_hdr (abfd);
252b5132 15331 sym_hashes = elf_sym_hashes (abfd);
ce98a316 15332 nsyms = NUM_SHDR_ENTRIES (symtab_hdr);
b38cadfb 15333
252b5132
RH		 15334 rel_end = relocs + sec->reloc_count;
15335 for (rel = relocs; rel < rel_end; rel++)
15336 {
34e77a92 15337 Elf_Internal_Sym *isym;
252b5132 15338 struct elf_link_hash_entry *h;
b7693d02 15339 struct elf32_arm_link_hash_entry *eh;
d42c267e 15340 unsigned int r_symndx;
eb043451 15341 int r_type;
9a5aca8c 15342
252b5132 15343 r_symndx = ELF32_R_SYM (rel->r_info);
eb043451 15344 r_type = ELF32_R_TYPE (rel->r_info);
eb043451 15345 r_type = arm_real_reloc_type (htab, r_type);
ba93b8ac 15346
ce98a316
NC		 15347 if (r_symndx >= nsyms
15348 /* PR 9934: It is possible to have relocations that do not
15349 refer to symbols, thus it is also possible to have an
15350 object file containing relocations but no symbol table. */
cf35638d 15351 && (r_symndx > STN_UNDEF || nsyms > 0))
ba93b8ac 15352 {
871b3ab2 15353 _bfd_error_handler (_("%pB: bad symbol index: %d"), abfd,
4eca0228 15354 r_symndx);
ba93b8ac
DJ		 15355 return FALSE;
15356 }
15357
34e77a92
RS		 15358 h = NULL;
15359 isym = NULL;
15360 if (nsyms > 0)
973a3492 15361 {
34e77a92
RS		 15362 if (r_symndx < symtab_hdr->sh_info)
15363 {
15364 /* A local symbol. */
15365 isym = bfd_sym_from_r_symndx (&htab->sym_cache,
15366 abfd, r_symndx);
15367 if (isym == NULL)
15368 return FALSE;
15369 }
15370 else
15371 {
15372 h = sym_hashes[r_symndx - symtab_hdr->sh_info];
15373 while (h->root.type == bfd_link_hash_indirect
15374 || h->root.type == bfd_link_hash_warning)
15375 h = (struct elf_link_hash_entry *) h->root.u.i.link;
15376 }
973a3492 15377 }
9a5aca8c 15378
b7693d02
DJ		 15379 eh = (struct elf32_arm_link_hash_entry *) h;
15380
f6e32f6d
RS		 15381 call_reloc_p = FALSE;
15382 may_become_dynamic_p = FALSE;
15383 may_need_local_target_p = FALSE;
15384
0855e32b
NS		 15385 /* Could be done earlier, if h were already available. */
15386 r_type = elf32_arm_tls_transition (info, r_type, h);
eb043451 15387 switch (r_type)
99059e56 15388 {
e8b09b87
CL		 15389 case R_ARM_GOTOFFFUNCDESC:
15390 {
15391 if (h == NULL)
15392 {
15393 if (!elf32_arm_allocate_local_sym_info (abfd))
15394 return FALSE;
15395 elf32_arm_local_fdpic_cnts(abfd)[r_symndx].gotofffuncdesc_cnt += 1;
15396 elf32_arm_local_fdpic_cnts(abfd)[r_symndx].funcdesc_offset = -1;
15397 }
15398 else
15399 {
15400 eh->fdpic_cnts.gotofffuncdesc_cnt++;
15401 }
15402 }
15403 break;
15404
15405 case R_ARM_GOTFUNCDESC:
15406 {
15407 if (h == NULL)
15408 {
15409 /* Such a relocation is not supposed to be generated
15410 by gcc on a static function. */
15411 /* Anyway if needed it could be handled. */
15412 abort();
15413 }
15414 else
15415 {
15416 eh->fdpic_cnts.gotfuncdesc_cnt++;
15417 }
15418 }
15419 break;
15420
15421 case R_ARM_FUNCDESC:
15422 {
15423 if (h == NULL)
15424 {
15425 if (!elf32_arm_allocate_local_sym_info (abfd))
15426 return FALSE;
15427 elf32_arm_local_fdpic_cnts(abfd)[r_symndx].funcdesc_cnt += 1;
15428 elf32_arm_local_fdpic_cnts(abfd)[r_symndx].funcdesc_offset = -1;
15429 }
15430 else
15431 {
15432 eh->fdpic_cnts.funcdesc_cnt++;
15433 }
15434 }
15435 break;
15436
5e681ec4 15437 case R_ARM_GOT32:
eb043451 15438 case R_ARM_GOT_PREL:
ba93b8ac 15439 case R_ARM_TLS_GD32:
5c5a4843 15440 case R_ARM_TLS_GD32_FDPIC:
ba93b8ac 15441 case R_ARM_TLS_IE32:
5c5a4843 15442 case R_ARM_TLS_IE32_FDPIC:
0855e32b
NS		 15443 case R_ARM_TLS_GOTDESC:
15444 case R_ARM_TLS_DESCSEQ:
15445 case R_ARM_THM_TLS_DESCSEQ:
15446 case R_ARM_TLS_CALL:
15447 case R_ARM_THM_TLS_CALL:
5e681ec4 15448 /* This symbol requires a global offset table entry. */
ba93b8ac
DJ		 15449 {
15450 int tls_type, old_tls_type;
5e681ec4 15451
ba93b8ac
DJ		 15452 switch (r_type)
15453 {
15454 case R_ARM_TLS_GD32: tls_type = GOT_TLS_GD; break;
5c5a4843 15455 case R_ARM_TLS_GD32_FDPIC: tls_type = GOT_TLS_GD; break;
b38cadfb 15456
ba93b8ac 15457 case R_ARM_TLS_IE32: tls_type = GOT_TLS_IE; break;
5c5a4843 15458 case R_ARM_TLS_IE32_FDPIC: tls_type = GOT_TLS_IE; break;
b38cadfb 15459
0855e32b
NS		 15460 case R_ARM_TLS_GOTDESC:
15461 case R_ARM_TLS_CALL: case R_ARM_THM_TLS_CALL:
15462 case R_ARM_TLS_DESCSEQ: case R_ARM_THM_TLS_DESCSEQ:
15463 tls_type = GOT_TLS_GDESC; break;
b38cadfb 15464
ba93b8ac
DJ		 15465 default: tls_type = GOT_NORMAL; break;
15466 }
252b5132 15467
0e1862bb 15468 if (!bfd_link_executable (info) && (tls_type & GOT_TLS_IE))
eea6dad2
KM		 15469 info->flags |= DF_STATIC_TLS;
15470
ba93b8ac
DJ		 15471 if (h != NULL)
15472 {
15473 h->got.refcount++;
15474 old_tls_type = elf32_arm_hash_entry (h)->tls_type;
15475 }
15476 else
15477 {
ba93b8ac 15478 /* This is a global offset table entry for a local symbol. */
34e77a92
RS		 15479 if (!elf32_arm_allocate_local_sym_info (abfd))
15480 return FALSE;
15481 elf_local_got_refcounts (abfd)[r_symndx] += 1;
ba93b8ac
DJ		 15482 old_tls_type = elf32_arm_local_got_tls_type (abfd) [r_symndx];
15483 }
15484
0855e32b 15485 /* If a variable is accessed with both tls methods, two
99059e56 15486 slots may be created. */
0855e32b
NS		 15487 if (GOT_TLS_GD_ANY_P (old_tls_type)
15488 && GOT_TLS_GD_ANY_P (tls_type))
15489 tls_type |= old_tls_type;
15490
15491 /* We will already have issued an error message if there
15492 is a TLS/non-TLS mismatch, based on the symbol
15493 type. So just combine any TLS types needed. */
ba93b8ac
DJ		 15494 if (old_tls_type != GOT_UNKNOWN && old_tls_type != GOT_NORMAL
15495 && tls_type != GOT_NORMAL)
15496 tls_type |= old_tls_type;
15497
0855e32b 15498 /* If the symbol is accessed in both IE and GDESC
99059e56
RM		 15499 method, we're able to relax. Turn off the GDESC flag,
15500 without messing up with any other kind of tls types
6a631e86 15501 that may be involved. */
0855e32b
NS		 15502 if ((tls_type & GOT_TLS_IE) && (tls_type & GOT_TLS_GDESC))
15503 tls_type &= ~GOT_TLS_GDESC;
15504
ba93b8ac
DJ		 15505 if (old_tls_type != tls_type)
15506 {
15507 if (h != NULL)
15508 elf32_arm_hash_entry (h)->tls_type = tls_type;
15509 else
15510 elf32_arm_local_got_tls_type (abfd) [r_symndx] = tls_type;
15511 }
15512 }
8029a119 15513 /* Fall through. */
ba93b8ac
DJ		 15514
15515 case R_ARM_TLS_LDM32:
5c5a4843
CL		 15516 case R_ARM_TLS_LDM32_FDPIC:
15517 if (r_type == R_ARM_TLS_LDM32 || r_type == R_ARM_TLS_LDM32_FDPIC)
ba93b8ac 15518 htab->tls_ldm_got.refcount++;
8029a119 15519 /* Fall through. */
252b5132 15520
c19d1205 15521 case R_ARM_GOTOFF32:
5e681ec4 15522 case R_ARM_GOTPC:
cbc704f3
RS		 15523 if (htab->root.sgot == NULL
15524 && !create_got_section (htab->root.dynobj, info))
15525 return FALSE;
252b5132
RH		 15526 break;
15527
252b5132 15528 case R_ARM_PC24:
7359ea65 15529 case R_ARM_PLT32:
5b5bb741
PB		 15530 case R_ARM_CALL:
15531 case R_ARM_JUMP24:
eb043451 15532 case R_ARM_PREL31:
c19d1205 15533 case R_ARM_THM_CALL:
bd97cb95
DJ		 15534 case R_ARM_THM_JUMP24:
15535 case R_ARM_THM_JUMP19:
f6e32f6d
RS		 15536 call_reloc_p = TRUE;
15537 may_need_local_target_p = TRUE;
15538 break;
15539
15540 case R_ARM_ABS12:
15541 /* VxWorks uses dynamic R_ARM_ABS12 relocations for
15542 ldr __GOTT_INDEX__ offsets. */
15543 if (!htab->vxworks_p)
15544 {
15545 may_need_local_target_p = TRUE;
15546 break;
15547 }
aebf9be7 15548 else goto jump_over;
9eaff861 15549
f6e32f6d 15550 /* Fall through. */
39623e12 15551
96c23d59
JM		 15552 case R_ARM_MOVW_ABS_NC:
15553 case R_ARM_MOVT_ABS:
15554 case R_ARM_THM_MOVW_ABS_NC:
15555 case R_ARM_THM_MOVT_ABS:
0e1862bb 15556 if (bfd_link_pic (info))
96c23d59 15557 {
4eca0228 15558 _bfd_error_handler
871b3ab2 15559 (_("%pB: relocation %s against `%s' can not be used when making a shared object; recompile with -fPIC"),
96c23d59
JM		 15560 abfd, elf32_arm_howto_table_1[r_type].name,
15561 (h) ? h->root.root.string : "a local symbol");
15562 bfd_set_error (bfd_error_bad_value);
15563 return FALSE;
15564 }
15565
15566 /* Fall through. */
39623e12
PB		 15567 case R_ARM_ABS32:
15568 case R_ARM_ABS32_NOI:
aebf9be7 15569 jump_over:
0e1862bb 15570 if (h != NULL && bfd_link_executable (info))
97323ad1
WN		 15571 {
15572 h->pointer_equality_needed = 1;
15573 }
15574 /* Fall through. */
39623e12
PB		 15575 case R_ARM_REL32:
15576 case R_ARM_REL32_NOI:
b6895b4f
PB		 15577 case R_ARM_MOVW_PREL_NC:
15578 case R_ARM_MOVT_PREL:
b6895b4f
PB		 15579 case R_ARM_THM_MOVW_PREL_NC:
15580 case R_ARM_THM_MOVT_PREL:
39623e12 15581
b7693d02 15582 /* Should the interworking branches be listed here? */
e8b09b87
CL		 15583 if ((bfd_link_pic (info) || htab->root.is_relocatable_executable
15584 || htab->fdpic_p)
34e77a92
RS		 15585 && (sec->flags & SEC_ALLOC) != 0)
15586 {
15587 if (h == NULL
469a3493 15588 && elf32_arm_howto_from_type (r_type)->pc_relative)
34e77a92
RS		 15589 {
15590 /* In shared libraries and relocatable executables,
15591 we treat local relative references as calls;
15592 see the related SYMBOL_CALLS_LOCAL code in
15593 allocate_dynrelocs. */
15594 call_reloc_p = TRUE;
15595 may_need_local_target_p = TRUE;
15596 }
15597 else
15598 /* We are creating a shared library or relocatable
15599 executable, and this is a reloc against a global symbol,
15600 or a non-PC-relative reloc against a local symbol.
15601 We may need to copy the reloc into the output. */
15602 may_become_dynamic_p = TRUE;
15603 }
f6e32f6d
RS		 15604 else
15605 may_need_local_target_p = TRUE;
252b5132
RH		 15606 break;
15607
99059e56
RM		 15608 /* This relocation describes the C++ object vtable hierarchy.
15609 Reconstruct it for later use during GC. */
15610 case R_ARM_GNU_VTINHERIT:
15611 if (!bfd_elf_gc_record_vtinherit (abfd, sec, h, rel->r_offset))
15612 return FALSE;
15613 break;
15614
15615 /* This relocation describes which C++ vtable entries are actually
15616 used. Record for later use during GC. */
15617 case R_ARM_GNU_VTENTRY:
a0ea3a14 15618 if (!bfd_elf_gc_record_vtentry (abfd, sec, h, rel->r_offset))
99059e56
RM		 15619 return FALSE;
15620 break;
15621 }
f6e32f6d
RS		 15622
15623 if (h != NULL)
15624 {
15625 if (call_reloc_p)
15626 /* We may need a .plt entry if the function this reloc
15627 refers to is in a different object, regardless of the
15628 symbol's type. We can't tell for sure yet, because
15629 something later might force the symbol local. */
15630 h->needs_plt = 1;
15631 else if (may_need_local_target_p)
15632 /* If this reloc is in a read-only section, we might
15633 need a copy reloc. We can't check reliably at this
15634 stage whether the section is read-only, as input
15635 sections have not yet been mapped to output sections.
15636 Tentatively set the flag for now, and correct in
15637 adjust_dynamic_symbol. */
15638 h->non_got_ref = 1;
15639 }
15640
34e77a92
RS		 15641 if (may_need_local_target_p
15642 && (h != NULL || ELF32_ST_TYPE (isym->st_info) == STT_GNU_IFUNC))
f6e32f6d 15643 {
34e77a92
RS		 15644 union gotplt_union *root_plt;
15645 struct arm_plt_info *arm_plt;
15646 struct arm_local_iplt_info *local_iplt;
15647
15648 if (h != NULL)
15649 {
15650 root_plt = &h->plt;
15651 arm_plt = &eh->plt;
15652 }
15653 else
15654 {
15655 local_iplt = elf32_arm_create_local_iplt (abfd, r_symndx);
15656 if (local_iplt == NULL)
15657 return FALSE;
15658 root_plt = &local_iplt->root;
15659 arm_plt = &local_iplt->arm;
15660 }
15661
f6e32f6d
RS		 15662 /* If the symbol is a function that doesn't bind locally,
15663 this relocation will need a PLT entry. */
a8c887dd
NC		 15664 if (root_plt->refcount != -1)
15665 root_plt->refcount += 1;
34e77a92
RS		 15666
15667 if (!call_reloc_p)
15668 arm_plt->noncall_refcount++;
f6e32f6d
RS		 15669
15670 /* It's too early to use htab->use_blx here, so we have to
15671 record possible blx references separately from
15672 relocs that definitely need a thumb stub. */
15673
15674 if (r_type == R_ARM_THM_CALL)
34e77a92 15675 arm_plt->maybe_thumb_refcount += 1;
f6e32f6d
RS		 15676
15677 if (r_type == R_ARM_THM_JUMP24
15678 || r_type == R_ARM_THM_JUMP19)
34e77a92 15679 arm_plt->thumb_refcount += 1;
f6e32f6d
RS		 15680 }
15681
15682 if (may_become_dynamic_p)
15683 {
15684 struct elf_dyn_relocs *p, **head;
15685
15686 /* Create a reloc section in dynobj. */
15687 if (sreloc == NULL)
15688 {
15689 sreloc = _bfd_elf_make_dynamic_reloc_section
15690 (sec, dynobj, 2, abfd, ! htab->use_rel);
15691
15692 if (sreloc == NULL)
15693 return FALSE;
15694
15695 /* BPABI objects never have dynamic relocations mapped. */
15696 if (htab->symbian_p)
15697 {
15698 flagword flags;
15699
fd361982 15700 flags = bfd_section_flags (sreloc);
f6e32f6d 15701 flags &= ~(SEC_LOAD | SEC_ALLOC);
fd361982 15702 bfd_set_section_flags (sreloc, flags);
f6e32f6d
RS		 15703 }
15704 }
15705
15706 /* If this is a global symbol, count the number of
15707 relocations we need for this symbol. */
15708 if (h != NULL)
15709 head = &((struct elf32_arm_link_hash_entry *) h)->dyn_relocs;
15710 else
15711 {
34e77a92
RS		 15712 head = elf32_arm_get_local_dynreloc_list (abfd, r_symndx, isym);
15713 if (head == NULL)
f6e32f6d 15714 return FALSE;
f6e32f6d
RS		 15715 }
15716
15717 p = *head;
15718 if (p == NULL || p->sec != sec)
15719 {
15720 bfd_size_type amt = sizeof *p;
15721
15722 p = (struct elf_dyn_relocs *) bfd_alloc (htab->root.dynobj, amt);
15723 if (p == NULL)
15724 return FALSE;
15725 p->next = *head;
15726 *head = p;
15727 p->sec = sec;
15728 p->count = 0;
15729 p->pc_count = 0;
15730 }
15731
469a3493 15732 if (elf32_arm_howto_from_type (r_type)->pc_relative)
f6e32f6d
RS		 15733 p->pc_count += 1;
15734 p->count += 1;
e8b09b87
CL		 15735 if (h == NULL && htab->fdpic_p && !bfd_link_pic(info)
15736 && r_type != R_ARM_ABS32 && r_type != R_ARM_ABS32_NOI) {
15737 /* Here we only support R_ARM_ABS32 and R_ARM_ABS32_NOI
15738 that will become rofixup. */
15739 /* This is due to the fact that we suppose all will become rofixup. */
15740 fprintf(stderr, "FDPIC does not yet support %d relocation to become dynamic for executable\n", r_type);
15741 _bfd_error_handler
15742 (_("FDPIC does not yet support %s relocation"
15743 " to become dynamic for executable"),
15744 elf32_arm_howto_table_1[r_type].name);
15745 abort();
15746 }
f6e32f6d 15747 }
252b5132 15748 }
f21f3fe0 15749
b34976b6 15750 return TRUE;
252b5132
RH		 15751}
15752
9eaff861
AO		 15753static void
15754elf32_arm_update_relocs (asection *o,
15755 struct bfd_elf_section_reloc_data *reldata)
15756{
15757 void (*swap_in) (bfd *, const bfd_byte *, Elf_Internal_Rela *);
15758 void (*swap_out) (bfd *, const Elf_Internal_Rela *, bfd_byte *);
15759 const struct elf_backend_data *bed;
15760 _arm_elf_section_data *eado;
15761 struct bfd_link_order *p;
15762 bfd_byte *erela_head, *erela;
15763 Elf_Internal_Rela *irela_head, *irela;
15764 Elf_Internal_Shdr *rel_hdr;
15765 bfd *abfd;
15766 unsigned int count;
15767
15768 eado = get_arm_elf_section_data (o);
15769
15770 if (!eado || eado->elf.this_hdr.sh_type != SHT_ARM_EXIDX)
15771 return;
15772
15773 abfd = o->owner;
15774 bed = get_elf_backend_data (abfd);
15775 rel_hdr = reldata->hdr;
15776
15777 if (rel_hdr->sh_entsize == bed->s->sizeof_rel)
15778 {
15779 swap_in = bed->s->swap_reloc_in;
15780 swap_out = bed->s->swap_reloc_out;
15781 }
15782 else if (rel_hdr->sh_entsize == bed->s->sizeof_rela)
15783 {
15784 swap_in = bed->s->swap_reloca_in;
15785 swap_out = bed->s->swap_reloca_out;
15786 }
15787 else
15788 abort ();
15789
15790 erela_head = rel_hdr->contents;
15791 irela_head = (Elf_Internal_Rela *) bfd_zmalloc
15792 ((NUM_SHDR_ENTRIES (rel_hdr) + 1) * sizeof (*irela_head));
15793
15794 erela = erela_head;
15795 irela = irela_head;
15796 count = 0;
15797
15798 for (p = o->map_head.link_order; p; p = p->next)
15799 {
15800 if (p->type == bfd_section_reloc_link_order
15801 || p->type == bfd_symbol_reloc_link_order)
15802 {
15803 (*swap_in) (abfd, erela, irela);
15804 erela += rel_hdr->sh_entsize;
15805 irela++;
15806 count++;
15807 }
15808 else if (p->type == bfd_indirect_link_order)
15809 {
15810 struct bfd_elf_section_reloc_data *input_reldata;
15811 arm_unwind_table_edit *edit_list, *edit_tail;
15812 _arm_elf_section_data *eadi;
15813 bfd_size_type j;
15814 bfd_vma offset;
15815 asection *i;
15816
15817 i = p->u.indirect.section;
15818
15819 eadi = get_arm_elf_section_data (i);
15820 edit_list = eadi->u.exidx.unwind_edit_list;
15821 edit_tail = eadi->u.exidx.unwind_edit_tail;
539300fb 15822 offset = i->output_offset;
9eaff861
AO		 15823
15824 if (eadi->elf.rel.hdr &&
15825 eadi->elf.rel.hdr->sh_entsize == rel_hdr->sh_entsize)
15826 input_reldata = &eadi->elf.rel;
15827 else if (eadi->elf.rela.hdr &&
15828 eadi->elf.rela.hdr->sh_entsize == rel_hdr->sh_entsize)
15829 input_reldata = &eadi->elf.rela;
15830 else
15831 abort ();
15832
15833 if (edit_list)
15834 {
15835 for (j = 0; j < NUM_SHDR_ENTRIES (input_reldata->hdr); j++)
15836 {
15837 arm_unwind_table_edit *edit_node, *edit_next;
15838 bfd_vma bias;
c48182bf 15839 bfd_vma reloc_index;
9eaff861
AO		 15840
15841 (*swap_in) (abfd, erela, irela);
c48182bf 15842 reloc_index = (irela->r_offset - offset) / 8;
9eaff861
AO		 15843
15844 bias = 0;
15845 edit_node = edit_list;
15846 for (edit_next = edit_list;
c48182bf 15847 edit_next && edit_next->index <= reloc_index;
9eaff861
AO		 15848 edit_next = edit_node->next)
15849 {
15850 bias++;
15851 edit_node = edit_next;
15852 }
15853
15854 if (edit_node->type != DELETE_EXIDX_ENTRY
c48182bf 15855 || edit_node->index != reloc_index)
9eaff861
AO		 15856 {
15857 irela->r_offset -= bias * 8;
15858 irela++;
15859 count++;
15860 }
15861
15862 erela += rel_hdr->sh_entsize;
15863 }
15864
15865 if (edit_tail->type == INSERT_EXIDX_CANTUNWIND_AT_END)
15866 {
15867 /* New relocation entity. */
15868 asection *text_sec = edit_tail->linked_section;
15869 asection *text_out = text_sec->output_section;
15870 bfd_vma exidx_offset = offset + i->size - 8;
15871
15872 irela->r_addend = 0;
15873 irela->r_offset = exidx_offset;
15874 irela->r_info = ELF32_R_INFO
15875 (text_out->target_index, R_ARM_PREL31);
15876 irela++;
15877 count++;
15878 }
15879 }
15880 else
15881 {
15882 for (j = 0; j < NUM_SHDR_ENTRIES (input_reldata->hdr); j++)
15883 {
15884 (*swap_in) (abfd, erela, irela);
15885 erela += rel_hdr->sh_entsize;
15886 irela++;
15887 }
15888
15889 count += NUM_SHDR_ENTRIES (input_reldata->hdr);
15890 }
15891 }
15892 }
15893
15894 reldata->count = count;
15895 rel_hdr->sh_size = count * rel_hdr->sh_entsize;
15896
15897 erela = erela_head;
15898 irela = irela_head;
15899 while (count > 0)
15900 {
15901 (*swap_out) (abfd, irela, erela);
15902 erela += rel_hdr->sh_entsize;
15903 irela++;
15904 count--;
15905 }
15906
15907 free (irela_head);
15908
15909 /* Hashes are no longer valid. */
15910 free (reldata->hashes);
15911 reldata->hashes = NULL;
15912}
15913
6a5bb875 15914/* Unwinding tables are not referenced directly. This pass marks them as
4ba2ef8f
TP		 15915 required if the corresponding code section is marked. Similarly, ARMv8-M
15916 secure entry functions can only be referenced by SG veneers which are
15917 created after the GC process. They need to be marked in case they reside in
15918 their own section (as would be the case if code was compiled with
15919 -ffunction-sections). */
6a5bb875
PB		 15920
15921static bfd_boolean
906e58ca
NC		 15922elf32_arm_gc_mark_extra_sections (struct bfd_link_info *info,
15923 elf_gc_mark_hook_fn gc_mark_hook)
6a5bb875
PB		 15924{
15925 bfd *sub;
15926 Elf_Internal_Shdr **elf_shdrp;
4ba2ef8f
TP		 15927 asection *cmse_sec;
15928 obj_attribute *out_attr;
15929 Elf_Internal_Shdr *symtab_hdr;
15930 unsigned i, sym_count, ext_start;
15931 const struct elf_backend_data *bed;
15932 struct elf_link_hash_entry **sym_hashes;
15933 struct elf32_arm_link_hash_entry *cmse_hash;
15934 bfd_boolean again, is_v8m, first_bfd_browse = TRUE;
bb32413f
SP		 15935 bfd_boolean debug_sec_need_to_be_marked = FALSE;
15936 asection *isec;
6a5bb875 15937
7f6ab9f8
AM		 15938 _bfd_elf_gc_mark_extra_sections (info, gc_mark_hook);
15939
4ba2ef8f
TP		 15940 out_attr = elf_known_obj_attributes_proc (info->output_bfd);
15941 is_v8m = out_attr[Tag_CPU_arch].i >= TAG_CPU_ARCH_V8M_BASE
15942 && out_attr[Tag_CPU_arch_profile].i == 'M';
15943
6a5bb875
PB		 15944 /* Marking EH data may cause additional code sections to be marked,
15945 requiring multiple passes. */
15946 again = TRUE;
15947 while (again)
15948 {
15949 again = FALSE;
c72f2fb2 15950 for (sub = info->input_bfds; sub != NULL; sub = sub->link.next)
6a5bb875
PB		 15951 {
15952 asection *o;
15953
0ffa91dd 15954 if (! is_arm_elf (sub))
6a5bb875
PB		 15955 continue;
15956
15957 elf_shdrp = elf_elfsections (sub);
15958 for (o = sub->sections; o != NULL; o = o->next)
15959 {
15960 Elf_Internal_Shdr *hdr;
0ffa91dd 15961
6a5bb875 15962 hdr = &elf_section_data (o)->this_hdr;
4fbb74a6
AM		 15963 if (hdr->sh_type == SHT_ARM_EXIDX
15964 && hdr->sh_link
15965 && hdr->sh_link < elf_numsections (sub)
6a5bb875
PB		 15966 && !o->gc_mark
15967 && elf_shdrp[hdr->sh_link]->bfd_section->gc_mark)
15968 {
15969 again = TRUE;
15970 if (!_bfd_elf_gc_mark (info, o, gc_mark_hook))
15971 return FALSE;
15972 }
15973 }
4ba2ef8f
TP		 15974
15975 /* Mark section holding ARMv8-M secure entry functions. We mark all
15976 of them so no need for a second browsing. */
15977 if (is_v8m && first_bfd_browse)
15978 {
15979 sym_hashes = elf_sym_hashes (sub);
15980 bed = get_elf_backend_data (sub);
15981 symtab_hdr = &elf_tdata (sub)->symtab_hdr;
15982 sym_count = symtab_hdr->sh_size / bed->s->sizeof_sym;
15983 ext_start = symtab_hdr->sh_info;
15984
15985 /* Scan symbols. */
15986 for (i = ext_start; i < sym_count; i++)
15987 {
15988 cmse_hash = elf32_arm_hash_entry (sym_hashes[i - ext_start]);
15989
15990 /* Assume it is a special symbol. If not, cmse_scan will
15991 warn about it and user can do something about it. */
baf46cd7
AM		 15992 if (CONST_STRNEQ (cmse_hash->root.root.root.string,
15993 CMSE_PREFIX))
4ba2ef8f
TP		 15994 {
15995 cmse_sec = cmse_hash->root.root.u.def.section;
5025eb7c
AO		 15996 if (!cmse_sec->gc_mark
15997 && !_bfd_elf_gc_mark (info, cmse_sec, gc_mark_hook))
4ba2ef8f 15998 return FALSE;
bb32413f
SP		 15999 /* The debug sections related to these secure entry
16000 functions are marked on enabling below flag. */
16001 debug_sec_need_to_be_marked = TRUE;
4ba2ef8f
TP		 16002 }
16003 }
bb32413f
SP		 16004
16005 if (debug_sec_need_to_be_marked)
16006 {
16007 /* Looping over all the sections of the object file containing
16008 Armv8-M secure entry functions and marking all the debug
16009 sections. */
16010 for (isec = sub->sections; isec != NULL; isec = isec->next)
16011 {
16012 /* If not a debug sections, skip it. */
16013 if (!isec->gc_mark && (isec->flags & SEC_DEBUGGING))
16014 isec->gc_mark = 1 ;
16015 }
16016 debug_sec_need_to_be_marked = FALSE;
16017 }
4ba2ef8f 16018 }
6a5bb875 16019 }
4ba2ef8f 16020 first_bfd_browse = FALSE;
6a5bb875
PB		 16021 }
16022
16023 return TRUE;
16024}
16025
3c9458e9
NC		 16026/* Treat mapping symbols as special target symbols. */
16027
16028static bfd_boolean
16029elf32_arm_is_target_special_symbol (bfd * abfd ATTRIBUTE_UNUSED, asymbol * sym)
16030{
b0796911
PB		 16031 return bfd_is_arm_special_symbol_name (sym->name,
16032 BFD_ARM_SPECIAL_SYM_TYPE_ANY);
3c9458e9
NC		 16033}
16034
62e0492f 16035/* This is a version of _bfd_elf_find_function() from dwarf2.c except that
0367ecfb
NC		 16036 ARM mapping symbols are ignored when looking for function names
16037 and STT_ARM_TFUNC is considered to a function type. */
252b5132 16038
0367ecfb 16039static bfd_boolean
62e0492f 16040arm_elf_find_function (bfd * abfd,
0367ecfb 16041 asymbol ** symbols,
fb167eb2 16042 asection * section,
07d6d2b8 16043 bfd_vma offset,
0367ecfb
NC		 16044 const char ** filename_ptr,
16045 const char ** functionname_ptr)
16046{
16047 const char * filename = NULL;
16048 asymbol * func = NULL;
16049 bfd_vma low_func = 0;
16050 asymbol ** p;
252b5132 16051
62e0492f
AL		 16052 if (symbols == NULL)
16053 return FALSE;
16054
16055 if (bfd_get_flavour (abfd) != bfd_target_elf_flavour)
16056 return FALSE;
16057
252b5132
RH		 16058 for (p = symbols; *p != NULL; p++)
16059 {
16060 elf_symbol_type *q;
16061
16062 q = (elf_symbol_type *) *p;
16063
252b5132
RH		 16064 switch (ELF_ST_TYPE (q->internal_elf_sym.st_info))
16065 {
16066 default:
16067 break;
16068 case STT_FILE:
16069 filename = bfd_asymbol_name (&q->symbol);
16070 break;
252b5132
RH		 16071 case STT_FUNC:
16072 case STT_ARM_TFUNC:
9d2da7ca 16073 case STT_NOTYPE:
b0796911 16074 /* Skip mapping symbols. */
0367ecfb 16075 if ((q->symbol.flags & BSF_LOCAL)
b0796911
PB		 16076 && bfd_is_arm_special_symbol_name (q->symbol.name,
16077 BFD_ARM_SPECIAL_SYM_TYPE_ANY))
0367ecfb
NC		 16078 continue;
16079 /* Fall through. */
e6f7f6d1 16080 if (bfd_asymbol_section (&q->symbol) == section
252b5132
RH		 16081 && q->symbol.value >= low_func
16082 && q->symbol.value <= offset)
16083 {
16084 func = (asymbol *) q;
16085 low_func = q->symbol.value;
16086 }
16087 break;
16088 }
16089 }
16090
16091 if (func == NULL)
b34976b6 16092 return FALSE;
252b5132 16093
0367ecfb
NC		 16094 if (filename_ptr)
16095 *filename_ptr = filename;
16096 if (functionname_ptr)
16097 *functionname_ptr = bfd_asymbol_name (func);
16098
16099 return TRUE;
906e58ca 16100}
0367ecfb
NC		 16101
16102
16103/* Find the nearest line to a particular section and offset, for error
16104 reporting. This code is a duplicate of the code in elf.c, except
16105 that it uses arm_elf_find_function. */
16106
16107static bfd_boolean
07d6d2b8
AM		 16108elf32_arm_find_nearest_line (bfd * abfd,
16109 asymbol ** symbols,
16110 asection * section,
16111 bfd_vma offset,
0367ecfb
NC		 16112 const char ** filename_ptr,
16113 const char ** functionname_ptr,
fb167eb2
AM		 16114 unsigned int * line_ptr,
16115 unsigned int * discriminator_ptr)
0367ecfb
NC		 16116{
16117 bfd_boolean found = FALSE;
16118
fb167eb2 16119 if (_bfd_dwarf2_find_nearest_line (abfd, symbols, NULL, section, offset,
0367ecfb 16120 filename_ptr, functionname_ptr,
fb167eb2 16121 line_ptr, discriminator_ptr,
9defd221 16122 dwarf_debug_sections,
0367ecfb
NC		 16123 & elf_tdata (abfd)->dwarf2_find_line_info))
16124 {
16125 if (!*functionname_ptr)
fb167eb2 16126 arm_elf_find_function (abfd, symbols, section, offset,
0367ecfb
NC		 16127 *filename_ptr ? NULL : filename_ptr,
16128 functionname_ptr);
f21f3fe0 16129
0367ecfb
NC		 16130 return TRUE;
16131 }
16132
fb167eb2
AM		 16133 /* Skip _bfd_dwarf1_find_nearest_line since no known ARM toolchain
16134 uses DWARF1. */
16135
0367ecfb
NC		 16136 if (! _bfd_stab_section_find_nearest_line (abfd, symbols, section, offset,
16137 & found, filename_ptr,
16138 functionname_ptr, line_ptr,
16139 & elf_tdata (abfd)->line_info))
16140 return FALSE;
16141
16142 if (found && (*functionname_ptr || *line_ptr))
16143 return TRUE;
16144
16145 if (symbols == NULL)
16146 return FALSE;
16147
fb167eb2 16148 if (! arm_elf_find_function (abfd, symbols, section, offset,
0367ecfb
NC		 16149 filename_ptr, functionname_ptr))
16150 return FALSE;
16151
16152 *line_ptr = 0;
b34976b6 16153 return TRUE;
252b5132
RH		 16154}
16155
4ab527b0 16156static bfd_boolean
07d6d2b8 16157elf32_arm_find_inliner_info (bfd * abfd,
4ab527b0
FF		 16158 const char ** filename_ptr,
16159 const char ** functionname_ptr,
16160 unsigned int * line_ptr)
16161{
16162 bfd_boolean found;
16163 found = _bfd_dwarf2_find_inliner_info (abfd, filename_ptr,
16164 functionname_ptr, line_ptr,
16165 & elf_tdata (abfd)->dwarf2_find_line_info);
16166 return found;
16167}
16168
63c1f59d
AM		 16169/* Find dynamic relocs for H that apply to read-only sections. */
16170
16171static asection *
16172readonly_dynrelocs (struct elf_link_hash_entry *h)
16173{
16174 struct elf_dyn_relocs *p;
16175
16176 for (p = elf32_arm_hash_entry (h)->dyn_relocs; p != NULL; p = p->next)
16177 {
16178 asection *s = p->sec->output_section;
16179
16180 if (s != NULL && (s->flags & SEC_READONLY) != 0)
16181 return p->sec;
16182 }
16183 return NULL;
16184}
16185
252b5132
RH		 16186/* Adjust a symbol defined by a dynamic object and referenced by a
16187 regular object. The current definition is in some section of the
16188 dynamic object, but we're not including those sections. We have to
16189 change the definition to something the rest of the link can
16190 understand. */
16191
b34976b6 16192static bfd_boolean
57e8b36a
NC		 16193elf32_arm_adjust_dynamic_symbol (struct bfd_link_info * info,
16194 struct elf_link_hash_entry * h)
252b5132
RH		 16195{
16196 bfd * dynobj;
5474d94f 16197 asection *s, *srel;
b7693d02 16198 struct elf32_arm_link_hash_entry * eh;
67687978 16199 struct elf32_arm_link_hash_table *globals;
252b5132 16200
67687978 16201 globals = elf32_arm_hash_table (info);
4dfe6ac6
NC		 16202 if (globals == NULL)
16203 return FALSE;
16204
252b5132
RH		 16205 dynobj = elf_hash_table (info)->dynobj;
16206
16207 /* Make sure we know what is going on here. */
16208 BFD_ASSERT (dynobj != NULL
f5385ebf 16209 && (h->needs_plt
34e77a92 16210 || h->type == STT_GNU_IFUNC
60d67dc8 16211 || h->is_weakalias
f5385ebf
AM		 16212 || (h->def_dynamic
16213 && h->ref_regular
16214 && !h->def_regular)));
252b5132 16215
b7693d02
DJ		 16216 eh = (struct elf32_arm_link_hash_entry *) h;
16217
252b5132
RH		 16218 /* If this is a function, put it in the procedure linkage table. We
16219 will fill in the contents of the procedure linkage table later,
16220 when we know the address of the .got section. */
34e77a92 16221 if (h->type == STT_FUNC || h->type == STT_GNU_IFUNC || h->needs_plt)
252b5132 16222 {
34e77a92
RS		 16223 /* Calls to STT_GNU_IFUNC symbols always use a PLT, even if the
16224 symbol binds locally. */
5e681ec4 16225 if (h->plt.refcount <= 0
34e77a92
RS		 16226 || (h->type != STT_GNU_IFUNC
16227 && (SYMBOL_CALLS_LOCAL (info, h)
16228 || (ELF_ST_VISIBILITY (h->other) != STV_DEFAULT
16229 && h->root.type == bfd_link_hash_undefweak))))
252b5132
RH		 16230 {
16231 /* This case can occur if we saw a PLT32 reloc in an input
5e681ec4
PB		 16232 file, but the symbol was never referred to by a dynamic
16233 object, or if all references were garbage collected. In
16234 such a case, we don't actually need to build a procedure
16235 linkage table, and we can just do a PC24 reloc instead. */
16236 h->plt.offset = (bfd_vma) -1;
34e77a92
RS		 16237 eh->plt.thumb_refcount = 0;
16238 eh->plt.maybe_thumb_refcount = 0;
16239 eh->plt.noncall_refcount = 0;
f5385ebf 16240 h->needs_plt = 0;
252b5132
RH		 16241 }
16242
b34976b6 16243 return TRUE;
252b5132 16244 }
5e681ec4 16245 else
b7693d02
DJ		 16246 {
16247 /* It's possible that we incorrectly decided a .plt reloc was
16248 needed for an R_ARM_PC24 or similar reloc to a non-function sym
16249 in check_relocs. We can't decide accurately between function
16250 and non-function syms in check-relocs; Objects loaded later in
16251 the link may change h->type. So fix it now. */
16252 h->plt.offset = (bfd_vma) -1;
34e77a92
RS		 16253 eh->plt.thumb_refcount = 0;
16254 eh->plt.maybe_thumb_refcount = 0;
16255 eh->plt.noncall_refcount = 0;
b7693d02 16256 }
252b5132
RH		 16257
16258 /* If this is a weak symbol, and there is a real definition, the
16259 processor independent code will have arranged for us to see the
16260 real definition first, and we can just use the same value. */
60d67dc8 16261 if (h->is_weakalias)
252b5132 16262 {
60d67dc8
AM		 16263 struct elf_link_hash_entry *def = weakdef (h);
16264 BFD_ASSERT (def->root.type == bfd_link_hash_defined);
16265 h->root.u.def.section = def->root.u.def.section;
16266 h->root.u.def.value = def->root.u.def.value;
b34976b6 16267 return TRUE;
252b5132
RH		 16268 }
16269
ba93b8ac
DJ		 16270 /* If there are no non-GOT references, we do not need a copy
16271 relocation. */
16272 if (!h->non_got_ref)
16273 return TRUE;
16274
252b5132
RH		 16275 /* This is a reference to a symbol defined by a dynamic object which
16276 is not a function. */
16277
16278 /* If we are creating a shared library, we must presume that the
16279 only references to the symbol are via the global offset table.
16280 For such cases we need not do anything here; the relocations will
67687978
PB		 16281 be handled correctly by relocate_section. Relocatable executables
16282 can reference data in shared objects directly, so we don't need to
16283 do anything here. */
0e1862bb 16284 if (bfd_link_pic (info) || globals->root.is_relocatable_executable)
b34976b6 16285 return TRUE;
252b5132
RH		 16286
16287 /* We must allocate the symbol in our .dynbss section, which will
16288 become part of the .bss section of the executable. There will be
16289 an entry for this symbol in the .dynsym section. The dynamic
16290 object will contain position independent code, so all references
16291 from the dynamic object to this symbol will go through the global
16292 offset table. The dynamic linker will use the .dynsym entry to
16293 determine the address it must put in the global offset table, so
16294 both the dynamic object and the regular object will refer to the
16295 same memory location for the variable. */
5522f910
NC		 16296 /* If allowed, we must generate a R_ARM_COPY reloc to tell the dynamic
16297 linker to copy the initial value out of the dynamic object and into
16298 the runtime process image. We need to remember the offset into the
00a97672 16299 .rel(a).bss section we are going to use. */
5474d94f
AM		 16300 if ((h->root.u.def.section->flags & SEC_READONLY) != 0)
16301 {
16302 s = globals->root.sdynrelro;
16303 srel = globals->root.sreldynrelro;
16304 }
16305 else
16306 {
16307 s = globals->root.sdynbss;
16308 srel = globals->root.srelbss;
16309 }
5522f910
NC		 16310 if (info->nocopyreloc == 0
16311 && (h->root.u.def.section->flags & SEC_ALLOC) != 0
5522f910 16312 && h->size != 0)
252b5132 16313 {
47beaa6a 16314 elf32_arm_allocate_dynrelocs (info, srel, 1);
f5385ebf 16315 h->needs_copy = 1;
252b5132
RH		 16316 }
16317
6cabe1ea 16318 return _bfd_elf_adjust_dynamic_copy (info, h, s);
252b5132
RH		 16319}
16320
5e681ec4
PB		 16321/* Allocate space in .plt, .got and associated reloc sections for
16322 dynamic relocs. */
16323
16324static bfd_boolean
47beaa6a 16325allocate_dynrelocs_for_symbol (struct elf_link_hash_entry *h, void * inf)
5e681ec4
PB		 16326{
16327 struct bfd_link_info *info;
16328 struct elf32_arm_link_hash_table *htab;
16329 struct elf32_arm_link_hash_entry *eh;
0bdcacaf 16330 struct elf_dyn_relocs *p;
5e681ec4
PB		 16331
16332 if (h->root.type == bfd_link_hash_indirect)
16333 return TRUE;
16334
e6a6bb22
AM		 16335 eh = (struct elf32_arm_link_hash_entry *) h;
16336
5e681ec4
PB		 16337 info = (struct bfd_link_info *) inf;
16338 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 16339 if (htab == NULL)
16340 return FALSE;
5e681ec4 16341
34e77a92 16342 if ((htab->root.dynamic_sections_created || h->type == STT_GNU_IFUNC)
5e681ec4
PB		 16343 && h->plt.refcount > 0)
16344 {
16345 /* Make sure this symbol is output as a dynamic symbol.
16346 Undefined weak syms won't yet be marked as dynamic. */
6c699715
RL		 16347 if (h->dynindx == -1 && !h->forced_local
16348 && h->root.type == bfd_link_hash_undefweak)
5e681ec4 16349 {
c152c796 16350 if (! bfd_elf_link_record_dynamic_symbol (info, h))
5e681ec4
PB		 16351 return FALSE;
16352 }
16353
34e77a92
RS		 16354 /* If the call in the PLT entry binds locally, the associated
16355 GOT entry should use an R_ARM_IRELATIVE relocation instead of
16356 the usual R_ARM_JUMP_SLOT. Put it in the .iplt section rather
16357 than the .plt section. */
16358 if (h->type == STT_GNU_IFUNC && SYMBOL_CALLS_LOCAL (info, h))
16359 {
16360 eh->is_iplt = 1;
16361 if (eh->plt.noncall_refcount == 0
16362 && SYMBOL_REFERENCES_LOCAL (info, h))
16363 /* All non-call references can be resolved directly.
16364 This means that they can (and in some cases, must)
16365 resolve directly to the run-time target, rather than
16366 to the PLT. That in turns means that any .got entry
16367 would be equal to the .igot.plt entry, so there's
16368 no point having both. */
16369 h->got.refcount = 0;
16370 }
16371
0e1862bb 16372 if (bfd_link_pic (info)
34e77a92 16373 || eh->is_iplt
7359ea65 16374 || WILL_CALL_FINISH_DYNAMIC_SYMBOL (1, 0, h))
5e681ec4 16375 {
34e77a92 16376 elf32_arm_allocate_plt_entry (info, eh->is_iplt, &h->plt, &eh->plt);
b7693d02 16377
5e681ec4
PB		 16378 /* If this symbol is not defined in a regular file, and we are
16379 not generating a shared library, then set the symbol to this
16380 location in the .plt. This is required to make function
16381 pointers compare as equal between the normal executable and
16382 the shared library. */
0e1862bb 16383 if (! bfd_link_pic (info)
f5385ebf 16384 && !h->def_regular)
5e681ec4 16385 {
34e77a92 16386 h->root.u.def.section = htab->root.splt;
5e681ec4 16387 h->root.u.def.value = h->plt.offset;
5e681ec4 16388
67d74e43
DJ		 16389 /* Make sure the function is not marked as Thumb, in case
16390 it is the target of an ABS32 relocation, which will
16391 point to the PLT entry. */
39d911fc 16392 ARM_SET_SYM_BRANCH_TYPE (h->target_internal, ST_BRANCH_TO_ARM);
67d74e43 16393 }
022f8312 16394
00a97672
RS		 16395 /* VxWorks executables have a second set of relocations for
16396 each PLT entry. They go in a separate relocation section,
16397 which is processed by the kernel loader. */
0e1862bb 16398 if (htab->vxworks_p && !bfd_link_pic (info))
00a97672
RS		 16399 {
16400 /* There is a relocation for the initial PLT entry:
16401 an R_ARM_32 relocation for _GLOBAL_OFFSET_TABLE_. */
16402 if (h->plt.offset == htab->plt_header_size)
47beaa6a 16403 elf32_arm_allocate_dynrelocs (info, htab->srelplt2, 1);
00a97672
RS		 16404
16405 /* There are two extra relocations for each subsequent
16406 PLT entry: an R_ARM_32 relocation for the GOT entry,
16407 and an R_ARM_32 relocation for the PLT entry. */
47beaa6a 16408 elf32_arm_allocate_dynrelocs (info, htab->srelplt2, 2);
00a97672 16409 }
5e681ec4
PB		 16410 }
16411 else
16412 {
16413 h->plt.offset = (bfd_vma) -1;
f5385ebf 16414 h->needs_plt = 0;
5e681ec4
PB		 16415 }
16416 }
16417 else
16418 {
16419 h->plt.offset = (bfd_vma) -1;
f5385ebf 16420 h->needs_plt = 0;
5e681ec4
PB		 16421 }
16422
0855e32b
NS		 16423 eh = (struct elf32_arm_link_hash_entry *) h;
16424 eh->tlsdesc_got = (bfd_vma) -1;
16425
5e681ec4
PB		 16426 if (h->got.refcount > 0)
16427 {
16428 asection *s;
16429 bfd_boolean dyn;
ba93b8ac
DJ		 16430 int tls_type = elf32_arm_hash_entry (h)->tls_type;
16431 int indx;
5e681ec4
PB		 16432
16433 /* Make sure this symbol is output as a dynamic symbol.
16434 Undefined weak syms won't yet be marked as dynamic. */
e8b09b87 16435 if (htab->root.dynamic_sections_created && h->dynindx == -1 && !h->forced_local
6c699715 16436 && h->root.type == bfd_link_hash_undefweak)
5e681ec4 16437 {
c152c796 16438 if (! bfd_elf_link_record_dynamic_symbol (info, h))
5e681ec4
PB		 16439 return FALSE;
16440 }
16441
e5a52504
MM		 16442 if (!htab->symbian_p)
16443 {
362d30a1 16444 s = htab->root.sgot;
e5a52504 16445 h->got.offset = s->size;
ba93b8ac
DJ		 16446
16447 if (tls_type == GOT_UNKNOWN)
16448 abort ();
16449
16450 if (tls_type == GOT_NORMAL)
16451 /* Non-TLS symbols need one GOT slot. */
16452 s->size += 4;
16453 else
16454 {
99059e56
RM		 16455 if (tls_type & GOT_TLS_GDESC)
16456 {
0855e32b 16457 /* R_ARM_TLS_DESC needs 2 GOT slots. */
99059e56 16458 eh->tlsdesc_got
0855e32b
NS		 16459 = (htab->root.sgotplt->size
16460 - elf32_arm_compute_jump_table_size (htab));
99059e56
RM		 16461 htab->root.sgotplt->size += 8;
16462 h->got.offset = (bfd_vma) -2;
34e77a92 16463 /* plt.got_offset needs to know there's a TLS_DESC
0855e32b 16464 reloc in the middle of .got.plt. */
99059e56
RM		 16465 htab->num_tls_desc++;
16466 }
0855e32b 16467
ba93b8ac 16468 if (tls_type & GOT_TLS_GD)
0855e32b 16469 {
5c5a4843
CL		 16470 /* R_ARM_TLS_GD32 and R_ARM_TLS_GD32_FDPIC need two
16471 consecutive GOT slots. If the symbol is both GD
16472 and GDESC, got.offset may have been
16473 overwritten. */
0855e32b
NS		 16474 h->got.offset = s->size;
16475 s->size += 8;
16476 }
16477
ba93b8ac 16478 if (tls_type & GOT_TLS_IE)
5c5a4843
CL		 16479 /* R_ARM_TLS_IE32/R_ARM_TLS_IE32_FDPIC need one GOT
16480 slot. */
ba93b8ac
DJ		 16481 s->size += 4;
16482 }
16483
e5a52504 16484 dyn = htab->root.dynamic_sections_created;
ba93b8ac
DJ		 16485
16486 indx = 0;
0e1862bb
L		 16487 if (WILL_CALL_FINISH_DYNAMIC_SYMBOL (dyn,
16488 bfd_link_pic (info),
16489 h)
16490 && (!bfd_link_pic (info)
ba93b8ac
DJ		 16491 || !SYMBOL_REFERENCES_LOCAL (info, h)))
16492 indx = h->dynindx;
16493
16494 if (tls_type != GOT_NORMAL
0e1862bb 16495 && (bfd_link_pic (info) || indx != 0)
ba93b8ac
DJ		 16496 && (ELF_ST_VISIBILITY (h->other) == STV_DEFAULT
16497 || h->root.type != bfd_link_hash_undefweak))
16498 {
16499 if (tls_type & GOT_TLS_IE)
47beaa6a 16500 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
ba93b8ac
DJ		 16501
16502 if (tls_type & GOT_TLS_GD)
47beaa6a 16503 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
ba93b8ac 16504
b38cadfb 16505 if (tls_type & GOT_TLS_GDESC)
0855e32b 16506 {
47beaa6a 16507 elf32_arm_allocate_dynrelocs (info, htab->root.srelplt, 1);
0855e32b
NS		 16508 /* GDESC needs a trampoline to jump to. */
16509 htab->tls_trampoline = -1;
16510 }
16511
16512 /* Only GD needs it. GDESC just emits one relocation per
16513 2 entries. */
b38cadfb 16514 if ((tls_type & GOT_TLS_GD) && indx != 0)
47beaa6a 16515 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
ba93b8ac 16516 }
e8b09b87
CL		 16517 else if (((indx != -1) || htab->fdpic_p)
16518 && !SYMBOL_REFERENCES_LOCAL (info, h))
b436d854
RS		 16519 {
16520 if (htab->root.dynamic_sections_created)
16521 /* Reserve room for the GOT entry's R_ARM_GLOB_DAT relocation. */
16522 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
16523 }
34e77a92
RS		 16524 else if (h->type == STT_GNU_IFUNC
16525 && eh->plt.noncall_refcount == 0)
16526 /* No non-call references resolve the STT_GNU_IFUNC's PLT entry;
16527 they all resolve dynamically instead. Reserve room for the
16528 GOT entry's R_ARM_IRELATIVE relocation. */
16529 elf32_arm_allocate_irelocs (info, htab->root.srelgot, 1);
0e1862bb
L		 16530 else if (bfd_link_pic (info)
16531 && (ELF_ST_VISIBILITY (h->other) == STV_DEFAULT
16532 || h->root.type != bfd_link_hash_undefweak))
b436d854 16533 /* Reserve room for the GOT entry's R_ARM_RELATIVE relocation. */
47beaa6a 16534 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
e8b09b87
CL		 16535 else if (htab->fdpic_p && tls_type == GOT_NORMAL)
16536 /* Reserve room for rofixup for FDPIC executable. */
16537 /* TLS relocs do not need space since they are completely
16538 resolved. */
16539 htab->srofixup->size += 4;
e5a52504 16540 }
5e681ec4
PB		 16541 }
16542 else
16543 h->got.offset = (bfd_vma) -1;
16544
e8b09b87
CL		 16545 /* FDPIC support. */
16546 if (eh->fdpic_cnts.gotofffuncdesc_cnt > 0)
16547 {
16548 /* Symbol musn't be exported. */
16549 if (h->dynindx != -1)
16550 abort();
16551
16552 /* We only allocate one function descriptor with its associated relocation. */
16553 if (eh->fdpic_cnts.funcdesc_offset == -1)
16554 {
16555 asection *s = htab->root.sgot;
16556
16557 eh->fdpic_cnts.funcdesc_offset = s->size;
16558 s->size += 8;
16559 /* We will add an R_ARM_FUNCDESC_VALUE relocation or two rofixups. */
16560 if (bfd_link_pic(info))
16561 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
16562 else
16563 htab->srofixup->size += 8;
16564 }
16565 }
16566
16567 if (eh->fdpic_cnts.gotfuncdesc_cnt > 0)
16568 {
16569 asection *s = htab->root.sgot;
16570
16571 if (htab->root.dynamic_sections_created && h->dynindx == -1
16572 && !h->forced_local)
16573 if (! bfd_elf_link_record_dynamic_symbol (info, h))
16574 return FALSE;
16575
16576 if (h->dynindx == -1)
16577 {
16578 /* We only allocate one function descriptor with its associated relocation. q */
16579 if (eh->fdpic_cnts.funcdesc_offset == -1)
16580 {
16581
16582 eh->fdpic_cnts.funcdesc_offset = s->size;
16583 s->size += 8;
16584 /* We will add an R_ARM_FUNCDESC_VALUE relocation or two rofixups. */
16585 if (bfd_link_pic(info))
16586 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
16587 else
16588 htab->srofixup->size += 8;
16589 }
16590 }
16591
16592 /* Add one entry into the GOT and a R_ARM_FUNCDESC or
16593 R_ARM_RELATIVE/rofixup relocation on it. */
16594 eh->fdpic_cnts.gotfuncdesc_offset = s->size;
16595 s->size += 4;
16596 if (h->dynindx == -1 && !bfd_link_pic(info))
4b24dd1a 16597 htab->srofixup->size += 4;
e8b09b87 16598 else
4b24dd1a 16599 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
e8b09b87
CL		 16600 }
16601
16602 if (eh->fdpic_cnts.funcdesc_cnt > 0)
16603 {
16604 if (htab->root.dynamic_sections_created && h->dynindx == -1
16605 && !h->forced_local)
16606 if (! bfd_elf_link_record_dynamic_symbol (info, h))
16607 return FALSE;
16608
16609 if (h->dynindx == -1)
16610 {
16611 /* We only allocate one function descriptor with its associated relocation. */
16612 if (eh->fdpic_cnts.funcdesc_offset == -1)
16613 {
16614 asection *s = htab->root.sgot;
16615
16616 eh->fdpic_cnts.funcdesc_offset = s->size;
16617 s->size += 8;
16618 /* We will add an R_ARM_FUNCDESC_VALUE relocation or two rofixups. */
16619 if (bfd_link_pic(info))
16620 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
16621 else
16622 htab->srofixup->size += 8;
16623 }
16624 }
16625 if (h->dynindx == -1 && !bfd_link_pic(info))
16626 {
16627 /* For FDPIC executable we replace R_ARM_RELATIVE with a rofixup. */
16628 htab->srofixup->size += 4 * eh->fdpic_cnts.funcdesc_cnt;
16629 }
16630 else
16631 {
16632 /* Will need one dynamic reloc per reference. will be either
16633 R_ARM_FUNCDESC or R_ARM_RELATIVE for hidden symbols. */
16634 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot,
16635 eh->fdpic_cnts.funcdesc_cnt);
16636 }
16637 }
16638
a4fd1a8e
PB		 16639 /* Allocate stubs for exported Thumb functions on v4t. */
16640 if (!htab->use_blx && h->dynindx != -1
0eaedd0e 16641 && h->def_regular
39d911fc 16642 && ARM_GET_SYM_BRANCH_TYPE (h->target_internal) == ST_BRANCH_TO_THUMB
a4fd1a8e
PB		 16643 && ELF_ST_VISIBILITY (h->other) == STV_DEFAULT)
16644 {
16645 struct elf_link_hash_entry * th;
16646 struct bfd_link_hash_entry * bh;
16647 struct elf_link_hash_entry * myh;
16648 char name[1024];
16649 asection *s;
16650 bh = NULL;
16651 /* Create a new symbol to regist the real location of the function. */
16652 s = h->root.u.def.section;
906e58ca 16653 sprintf (name, "__real_%s", h->root.root.string);
a4fd1a8e
PB		 16654 _bfd_generic_link_add_one_symbol (info, s->owner,
16655 name, BSF_GLOBAL, s,
16656 h->root.u.def.value,
16657 NULL, TRUE, FALSE, &bh);
16658
16659 myh = (struct elf_link_hash_entry *) bh;
35fc36a8 16660 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
a4fd1a8e 16661 myh->forced_local = 1;
39d911fc 16662 ARM_SET_SYM_BRANCH_TYPE (myh->target_internal, ST_BRANCH_TO_THUMB);
a4fd1a8e
PB		 16663 eh->export_glue = myh;
16664 th = record_arm_to_thumb_glue (info, h);
16665 /* Point the symbol at the stub. */
16666 h->type = ELF_ST_INFO (ELF_ST_BIND (h->type), STT_FUNC);
39d911fc 16667 ARM_SET_SYM_BRANCH_TYPE (h->target_internal, ST_BRANCH_TO_ARM);
a4fd1a8e
PB		 16668 h->root.u.def.section = th->root.u.def.section;
16669 h->root.u.def.value = th->root.u.def.value & ~1;
16670 }
16671
0bdcacaf 16672 if (eh->dyn_relocs == NULL)
5e681ec4
PB		 16673 return TRUE;
16674
16675 /* In the shared -Bsymbolic case, discard space allocated for
16676 dynamic pc-relative relocs against symbols which turn out to be
16677 defined in regular objects. For the normal shared case, discard
16678 space for pc-relative relocs that have become local due to symbol
16679 visibility changes. */
16680
e8b09b87 16681 if (bfd_link_pic (info) || htab->root.is_relocatable_executable || htab->fdpic_p)
5e681ec4 16682 {
469a3493
RM		 16683 /* Relocs that use pc_count are PC-relative forms, which will appear
16684 on something like ".long foo - ." or "movw REG, foo - .". We want
16685 calls to protected symbols to resolve directly to the function
16686 rather than going via the plt. If people want function pointer
16687 comparisons to work as expected then they should avoid writing
16688 assembly like ".long foo - .". */
ba93b8ac
DJ		 16689 if (SYMBOL_CALLS_LOCAL (info, h))
16690 {
0bdcacaf 16691 struct elf_dyn_relocs **pp;
ba93b8ac 16692
0bdcacaf 16693 for (pp = &eh->dyn_relocs; (p = *pp) != NULL; )
ba93b8ac
DJ		 16694 {
16695 p->count -= p->pc_count;
16696 p->pc_count = 0;
16697 if (p->count == 0)
16698 *pp = p->next;
16699 else
16700 pp = &p->next;
16701 }
16702 }
16703
4dfe6ac6 16704 if (htab->vxworks_p)
3348747a 16705 {
0bdcacaf 16706 struct elf_dyn_relocs **pp;
3348747a 16707
0bdcacaf 16708 for (pp = &eh->dyn_relocs; (p = *pp) != NULL; )
3348747a 16709 {
0bdcacaf 16710 if (strcmp (p->sec->output_section->name, ".tls_vars") == 0)
3348747a
NS		 16711 *pp = p->next;
16712 else
16713 pp = &p->next;
16714 }
16715 }
16716
ba93b8ac 16717 /* Also discard relocs on undefined weak syms with non-default
99059e56 16718 visibility. */
0bdcacaf 16719 if (eh->dyn_relocs != NULL
5e681ec4 16720 && h->root.type == bfd_link_hash_undefweak)
22d606e9 16721 {
95b03e4a
L		 16722 if (ELF_ST_VISIBILITY (h->other) != STV_DEFAULT
16723 || UNDEFWEAK_NO_DYNAMIC_RELOC (info, h))
0bdcacaf 16724 eh->dyn_relocs = NULL;
22d606e9
AM		 16725
16726 /* Make sure undefined weak symbols are output as a dynamic
16727 symbol in PIEs. */
e8b09b87 16728 else if (htab->root.dynamic_sections_created && h->dynindx == -1
22d606e9
AM		 16729 && !h->forced_local)
16730 {
16731 if (! bfd_elf_link_record_dynamic_symbol (info, h))
16732 return FALSE;
16733 }
16734 }
16735
67687978
PB		 16736 else if (htab->root.is_relocatable_executable && h->dynindx == -1
16737 && h->root.type == bfd_link_hash_new)
16738 {
16739 /* Output absolute symbols so that we can create relocations
16740 against them. For normal symbols we output a relocation
16741 against the section that contains them. */
16742 if (! bfd_elf_link_record_dynamic_symbol (info, h))
16743 return FALSE;
16744 }
16745
5e681ec4
PB		 16746 }
16747 else
16748 {
16749 /* For the non-shared case, discard space for relocs against
16750 symbols which turn out to need copy relocs or are not
16751 dynamic. */
16752
f5385ebf
AM		 16753 if (!h->non_got_ref
16754 && ((h->def_dynamic
16755 && !h->def_regular)
5e681ec4
PB		 16756 || (htab->root.dynamic_sections_created
16757 && (h->root.type == bfd_link_hash_undefweak
16758 || h->root.type == bfd_link_hash_undefined))))
16759 {
16760 /* Make sure this symbol is output as a dynamic symbol.
16761 Undefined weak syms won't yet be marked as dynamic. */
6c699715
RL		 16762 if (h->dynindx == -1 && !h->forced_local
16763 && h->root.type == bfd_link_hash_undefweak)
5e681ec4 16764 {
c152c796 16765 if (! bfd_elf_link_record_dynamic_symbol (info, h))
5e681ec4
PB		 16766 return FALSE;
16767 }
16768
16769 /* If that succeeded, we know we'll be keeping all the
16770 relocs. */
16771 if (h->dynindx != -1)
16772 goto keep;
16773 }
16774
0bdcacaf 16775 eh->dyn_relocs = NULL;
5e681ec4
PB		 16776
16777 keep: ;
16778 }
16779
16780 /* Finally, allocate space. */
0bdcacaf 16781 for (p = eh->dyn_relocs; p != NULL; p = p->next)
5e681ec4 16782 {
0bdcacaf 16783 asection *sreloc = elf_section_data (p->sec)->sreloc;
e8b09b87 16784
34e77a92
RS		 16785 if (h->type == STT_GNU_IFUNC
16786 && eh->plt.noncall_refcount == 0
16787 && SYMBOL_REFERENCES_LOCAL (info, h))
16788 elf32_arm_allocate_irelocs (info, sreloc, p->count);
e8b09b87
CL		 16789 else if (h->dynindx != -1 && (!bfd_link_pic(info) || !info->symbolic || !h->def_regular))
16790 elf32_arm_allocate_dynrelocs (info, sreloc, p->count);
16791 else if (htab->fdpic_p && !bfd_link_pic(info))
16792 htab->srofixup->size += 4 * p->count;
34e77a92
RS		 16793 else
16794 elf32_arm_allocate_dynrelocs (info, sreloc, p->count);
5e681ec4
PB		 16795 }
16796
16797 return TRUE;
16798}
16799
63c1f59d
AM		 16800/* Set DF_TEXTREL if we find any dynamic relocs that apply to
16801 read-only sections. */
08d1f311
DJ		 16802
16803static bfd_boolean
63c1f59d 16804maybe_set_textrel (struct elf_link_hash_entry *h, void *info_p)
08d1f311 16805{
63c1f59d 16806 asection *sec;
08d1f311 16807
63c1f59d
AM		 16808 if (h->root.type == bfd_link_hash_indirect)
16809 return TRUE;
08d1f311 16810
63c1f59d
AM		 16811 sec = readonly_dynrelocs (h);
16812 if (sec != NULL)
16813 {
16814 struct bfd_link_info *info = (struct bfd_link_info *) info_p;
08d1f311 16815
63c1f59d
AM		 16816 info->flags |= DF_TEXTREL;
16817 info->callbacks->minfo
c1c8c1ef 16818 (_("%pB: dynamic relocation against `%pT' in read-only section `%pA'\n"),
63c1f59d 16819 sec->owner, h->root.root.string, sec);
08d1f311 16820
63c1f59d
AM		 16821 /* Not an error, just cut short the traversal. */
16822 return FALSE;
08d1f311 16823 }
cb10292c 16824
08d1f311
DJ		 16825 return TRUE;
16826}
16827
d504ffc8
DJ		 16828void
16829bfd_elf32_arm_set_byteswap_code (struct bfd_link_info *info,
16830 int byteswap_code)
16831{
16832 struct elf32_arm_link_hash_table *globals;
16833
16834 globals = elf32_arm_hash_table (info);
4dfe6ac6
NC		 16835 if (globals == NULL)
16836 return;
16837
d504ffc8
DJ		 16838 globals->byteswap_code = byteswap_code;
16839}
16840
252b5132
RH		 16841/* Set the sizes of the dynamic sections. */
16842
b34976b6 16843static bfd_boolean
57e8b36a
NC		 16844elf32_arm_size_dynamic_sections (bfd * output_bfd ATTRIBUTE_UNUSED,
16845 struct bfd_link_info * info)
252b5132
RH		 16846{
16847 bfd * dynobj;
16848 asection * s;
b34976b6
AM		 16849 bfd_boolean plt;
16850 bfd_boolean relocs;
5e681ec4
PB		 16851 bfd *ibfd;
16852 struct elf32_arm_link_hash_table *htab;
252b5132 16853
5e681ec4 16854 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 16855 if (htab == NULL)
16856 return FALSE;
16857
252b5132
RH		 16858 dynobj = elf_hash_table (info)->dynobj;
16859 BFD_ASSERT (dynobj != NULL);
39b41c9c 16860 check_use_blx (htab);
252b5132
RH		 16861
16862 if (elf_hash_table (info)->dynamic_sections_created)
16863 {
16864 /* Set the contents of the .interp section to the interpreter. */
9b8b325a 16865 if (bfd_link_executable (info) && !info->nointerp)
252b5132 16866 {
3d4d4302 16867 s = bfd_get_linker_section (dynobj, ".interp");
252b5132 16868 BFD_ASSERT (s != NULL);
eea6121a 16869 s->size = sizeof ELF_DYNAMIC_INTERPRETER;
252b5132
RH		 16870 s->contents = (unsigned char *) ELF_DYNAMIC_INTERPRETER;
16871 }
16872 }
5e681ec4
PB		 16873
16874 /* Set up .got offsets for local syms, and space for local dynamic
16875 relocs. */
c72f2fb2 16876 for (ibfd = info->input_bfds; ibfd != NULL; ibfd = ibfd->link.next)
252b5132 16877 {
5e681ec4
PB		 16878 bfd_signed_vma *local_got;
16879 bfd_signed_vma *end_local_got;
34e77a92 16880 struct arm_local_iplt_info **local_iplt_ptr, *local_iplt;
5e681ec4 16881 char *local_tls_type;
0855e32b 16882 bfd_vma *local_tlsdesc_gotent;
5e681ec4
PB		 16883 bfd_size_type locsymcount;
16884 Elf_Internal_Shdr *symtab_hdr;
16885 asection *srel;
4dfe6ac6 16886 bfd_boolean is_vxworks = htab->vxworks_p;
34e77a92 16887 unsigned int symndx;
e8b09b87 16888 struct fdpic_local *local_fdpic_cnts;
5e681ec4 16889
0ffa91dd 16890 if (! is_arm_elf (ibfd))
5e681ec4
PB		 16891 continue;
16892
16893 for (s = ibfd->sections; s != NULL; s = s->next)
16894 {
0bdcacaf 16895 struct elf_dyn_relocs *p;
5e681ec4 16896
0bdcacaf 16897 for (p = (struct elf_dyn_relocs *)
99059e56 16898 elf_section_data (s)->local_dynrel; p != NULL; p = p->next)
5e681ec4 16899 {
0bdcacaf
RS		 16900 if (!bfd_is_abs_section (p->sec)
16901 && bfd_is_abs_section (p->sec->output_section))
5e681ec4
PB		 16902 {
16903 /* Input section has been discarded, either because
16904 it is a copy of a linkonce section or due to
16905 linker script /DISCARD/, so we'll be discarding
16906 the relocs too. */
16907 }
3348747a 16908 else if (is_vxworks
0bdcacaf 16909 && strcmp (p->sec->output_section->name,
3348747a
NS		 16910 ".tls_vars") == 0)
16911 {
16912 /* Relocations in vxworks .tls_vars sections are
16913 handled specially by the loader. */
16914 }
5e681ec4
PB		 16915 else if (p->count != 0)
16916 {
0bdcacaf 16917 srel = elf_section_data (p->sec)->sreloc;
e8b09b87
CL		 16918 if (htab->fdpic_p && !bfd_link_pic(info))
16919 htab->srofixup->size += 4 * p->count;
16920 else
16921 elf32_arm_allocate_dynrelocs (info, srel, p->count);
0bdcacaf 16922 if ((p->sec->output_section->flags & SEC_READONLY) != 0)
5e681ec4
PB		 16923 info->flags |= DF_TEXTREL;
16924 }
16925 }
16926 }
16927
16928 local_got = elf_local_got_refcounts (ibfd);
16929 if (!local_got)
16930 continue;
16931
0ffa91dd 16932 symtab_hdr = & elf_symtab_hdr (ibfd);
5e681ec4
PB		 16933 locsymcount = symtab_hdr->sh_info;
16934 end_local_got = local_got + locsymcount;
34e77a92 16935 local_iplt_ptr = elf32_arm_local_iplt (ibfd);
ba93b8ac 16936 local_tls_type = elf32_arm_local_got_tls_type (ibfd);
0855e32b 16937 local_tlsdesc_gotent = elf32_arm_local_tlsdesc_gotent (ibfd);
e8b09b87 16938 local_fdpic_cnts = elf32_arm_local_fdpic_cnts (ibfd);
34e77a92 16939 symndx = 0;
362d30a1
RS		 16940 s = htab->root.sgot;
16941 srel = htab->root.srelgot;
0855e32b 16942 for (; local_got < end_local_got;
34e77a92 16943 ++local_got, ++local_iplt_ptr, ++local_tls_type,
e8b09b87 16944 ++local_tlsdesc_gotent, ++symndx, ++local_fdpic_cnts)
5e681ec4 16945 {
0855e32b 16946 *local_tlsdesc_gotent = (bfd_vma) -1;
34e77a92 16947 local_iplt = *local_iplt_ptr;
e8b09b87
CL		 16948
16949 /* FDPIC support. */
16950 if (local_fdpic_cnts->gotofffuncdesc_cnt > 0)
16951 {
16952 if (local_fdpic_cnts->funcdesc_offset == -1)
16953 {
16954 local_fdpic_cnts->funcdesc_offset = s->size;
16955 s->size += 8;
16956
16957 /* We will add an R_ARM_FUNCDESC_VALUE relocation or two rofixups. */
16958 if (bfd_link_pic(info))
16959 elf32_arm_allocate_dynrelocs (info, srel, 1);
16960 else
16961 htab->srofixup->size += 8;
16962 }
16963 }
16964
16965 if (local_fdpic_cnts->funcdesc_cnt > 0)
16966 {
16967 if (local_fdpic_cnts->funcdesc_offset == -1)
16968 {
16969 local_fdpic_cnts->funcdesc_offset = s->size;
16970 s->size += 8;
16971
16972 /* We will add an R_ARM_FUNCDESC_VALUE relocation or two rofixups. */
16973 if (bfd_link_pic(info))
16974 elf32_arm_allocate_dynrelocs (info, srel, 1);
16975 else
16976 htab->srofixup->size += 8;
16977 }
16978
16979 /* We will add n R_ARM_RELATIVE relocations or n rofixups. */
16980 if (bfd_link_pic(info))
16981 elf32_arm_allocate_dynrelocs (info, srel, local_fdpic_cnts->funcdesc_cnt);
16982 else
16983 htab->srofixup->size += 4 * local_fdpic_cnts->funcdesc_cnt;
16984 }
16985
34e77a92
RS		 16986 if (local_iplt != NULL)
16987 {
16988 struct elf_dyn_relocs *p;
16989
16990 if (local_iplt->root.refcount > 0)
16991 {
16992 elf32_arm_allocate_plt_entry (info, TRUE,
16993 &local_iplt->root,
16994 &local_iplt->arm);
16995 if (local_iplt->arm.noncall_refcount == 0)
16996 /* All references to the PLT are calls, so all
16997 non-call references can resolve directly to the
16998 run-time target. This means that the .got entry
16999 would be the same as the .igot.plt entry, so there's
17000 no point creating both. */
17001 *local_got = 0;
17002 }
17003 else
17004 {
17005 BFD_ASSERT (local_iplt->arm.noncall_refcount == 0);
17006 local_iplt->root.offset = (bfd_vma) -1;
17007 }
17008
17009 for (p = local_iplt->dyn_relocs; p != NULL; p = p->next)
17010 {
17011 asection *psrel;
17012
17013 psrel = elf_section_data (p->sec)->sreloc;
17014 if (local_iplt->arm.noncall_refcount == 0)
17015 elf32_arm_allocate_irelocs (info, psrel, p->count);
17016 else
17017 elf32_arm_allocate_dynrelocs (info, psrel, p->count);
17018 }
17019 }
5e681ec4
PB		 17020 if (*local_got > 0)
17021 {
34e77a92
RS		 17022 Elf_Internal_Sym *isym;
17023
eea6121a 17024 *local_got = s->size;
ba93b8ac
DJ		 17025 if (*local_tls_type & GOT_TLS_GD)
17026 /* TLS_GD relocs need an 8-byte structure in the GOT. */
17027 s->size += 8;
0855e32b
NS		 17028 if (*local_tls_type & GOT_TLS_GDESC)
17029 {
17030 *local_tlsdesc_gotent = htab->root.sgotplt->size
17031 - elf32_arm_compute_jump_table_size (htab);
17032 htab->root.sgotplt->size += 8;
17033 *local_got = (bfd_vma) -2;
34e77a92 17034 /* plt.got_offset needs to know there's a TLS_DESC
0855e32b 17035 reloc in the middle of .got.plt. */
99059e56 17036 htab->num_tls_desc++;
0855e32b 17037 }
ba93b8ac
DJ		 17038 if (*local_tls_type & GOT_TLS_IE)
17039 s->size += 4;
ba93b8ac 17040
0855e32b
NS		 17041 if (*local_tls_type & GOT_NORMAL)
17042 {
17043 /* If the symbol is both GD and GDESC, *local_got
17044 may have been overwritten. */
17045 *local_got = s->size;
17046 s->size += 4;
17047 }
17048
34e77a92
RS		 17049 isym = bfd_sym_from_r_symndx (&htab->sym_cache, ibfd, symndx);
17050 if (isym == NULL)
17051 return FALSE;
17052
17053 /* If all references to an STT_GNU_IFUNC PLT are calls,
17054 then all non-call references, including this GOT entry,
17055 resolve directly to the run-time target. */
17056 if (ELF32_ST_TYPE (isym->st_info) == STT_GNU_IFUNC
17057 && (local_iplt == NULL
17058 || local_iplt->arm.noncall_refcount == 0))
17059 elf32_arm_allocate_irelocs (info, srel, 1);
e8b09b87 17060 else if (bfd_link_pic (info) || output_bfd->flags & DYNAMIC || htab->fdpic_p)
0855e32b 17061 {
e8b09b87 17062 if ((bfd_link_pic (info) && !(*local_tls_type & GOT_TLS_GDESC)))
3064e1ff 17063 elf32_arm_allocate_dynrelocs (info, srel, 1);
e8b09b87
CL		 17064 else if (htab->fdpic_p && *local_tls_type & GOT_NORMAL)
17065 htab->srofixup->size += 4;
99059e56 17066
e8b09b87
CL		 17067 if ((bfd_link_pic (info) || htab->fdpic_p)
17068 && *local_tls_type & GOT_TLS_GDESC)
3064e1ff
JB		 17069 {
17070 elf32_arm_allocate_dynrelocs (info,
17071 htab->root.srelplt, 1);
17072 htab->tls_trampoline = -1;
17073 }
0855e32b 17074 }
5e681ec4
PB		 17075 }
17076 else
17077 *local_got = (bfd_vma) -1;
17078 }
252b5132
RH		 17079 }
17080
ba93b8ac
DJ		 17081 if (htab->tls_ldm_got.refcount > 0)
17082 {
17083 /* Allocate two GOT entries and one dynamic relocation (if necessary)
5c5a4843 17084 for R_ARM_TLS_LDM32/R_ARM_TLS_LDM32_FDPIC relocations. */
362d30a1
RS		 17085 htab->tls_ldm_got.offset = htab->root.sgot->size;
17086 htab->root.sgot->size += 8;
0e1862bb 17087 if (bfd_link_pic (info))
47beaa6a 17088 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
ba93b8ac
DJ		 17089 }
17090 else
17091 htab->tls_ldm_got.offset = -1;
17092
e8b09b87
CL		 17093 /* At the very end of the .rofixup section is a pointer to the GOT,
17094 reserve space for it. */
17095 if (htab->fdpic_p && htab->srofixup != NULL)
17096 htab->srofixup->size += 4;
17097
5e681ec4
PB		 17098 /* Allocate global sym .plt and .got entries, and space for global
17099 sym dynamic relocs. */
47beaa6a 17100 elf_link_hash_traverse (& htab->root, allocate_dynrelocs_for_symbol, info);
252b5132 17101
d504ffc8 17102 /* Here we rummage through the found bfds to collect glue information. */
c72f2fb2 17103 for (ibfd = info->input_bfds; ibfd != NULL; ibfd = ibfd->link.next)
c7b8f16e 17104 {
0ffa91dd 17105 if (! is_arm_elf (ibfd))
e44a2c9c
AM		 17106 continue;
17107
c7b8f16e
JB		 17108 /* Initialise mapping tables for code/data. */
17109 bfd_elf32_arm_init_maps (ibfd);
906e58ca 17110
c7b8f16e 17111 if (!bfd_elf32_arm_process_before_allocation (ibfd, info)
a504d23a
LA		 17112 || !bfd_elf32_arm_vfp11_erratum_scan (ibfd, info)
17113 || !bfd_elf32_arm_stm32l4xx_erratum_scan (ibfd, info))
90b6238f 17114 _bfd_error_handler (_("errors encountered processing file %pB"), ibfd);
c7b8f16e 17115 }
d504ffc8 17116
3e6b1042
DJ		 17117 /* Allocate space for the glue sections now that we've sized them. */
17118 bfd_elf32_arm_allocate_interworking_sections (info);
17119
0855e32b
NS		 17120 /* For every jump slot reserved in the sgotplt, reloc_count is
17121 incremented. However, when we reserve space for TLS descriptors,
17122 it's not incremented, so in order to compute the space reserved
17123 for them, it suffices to multiply the reloc count by the jump
17124 slot size. */
17125 if (htab->root.srelplt)
17126 htab->sgotplt_jump_table_size = elf32_arm_compute_jump_table_size(htab);
17127
17128 if (htab->tls_trampoline)
17129 {
17130 if (htab->root.splt->size == 0)
17131 htab->root.splt->size += htab->plt_header_size;
b38cadfb 17132
0855e32b
NS		 17133 htab->tls_trampoline = htab->root.splt->size;
17134 htab->root.splt->size += htab->plt_entry_size;
b38cadfb 17135
0855e32b 17136 /* If we're not using lazy TLS relocations, don't generate the
99059e56 17137 PLT and GOT entries they require. */
0855e32b
NS		 17138 if (!(info->flags & DF_BIND_NOW))
17139 {
17140 htab->dt_tlsdesc_got = htab->root.sgot->size;
17141 htab->root.sgot->size += 4;
17142
17143 htab->dt_tlsdesc_plt = htab->root.splt->size;
17144 htab->root.splt->size += 4 * ARRAY_SIZE (dl_tlsdesc_lazy_trampoline);
17145 }
17146 }
17147
252b5132
RH		 17148 /* The check_relocs and adjust_dynamic_symbol entry points have
17149 determined the sizes of the various dynamic sections. Allocate
17150 memory for them. */
b34976b6
AM		 17151 plt = FALSE;
17152 relocs = FALSE;
252b5132
RH		 17153 for (s = dynobj->sections; s != NULL; s = s->next)
17154 {
17155 const char * name;
252b5132
RH		 17156
17157 if ((s->flags & SEC_LINKER_CREATED) == 0)
17158 continue;
17159
17160 /* It's OK to base decisions on the section name, because none
17161 of the dynobj section names depend upon the input files. */
fd361982 17162 name = bfd_section_name (s);
252b5132 17163
34e77a92 17164 if (s == htab->root.splt)
252b5132 17165 {
c456f082
AM		 17166 /* Remember whether there is a PLT. */
17167 plt = s->size != 0;
252b5132 17168 }
0112cd26 17169 else if (CONST_STRNEQ (name, ".rel"))
252b5132 17170 {
c456f082 17171 if (s->size != 0)
252b5132 17172 {
252b5132 17173 /* Remember whether there are any reloc sections other
00a97672 17174 than .rel(a).plt and .rela.plt.unloaded. */
362d30a1 17175 if (s != htab->root.srelplt && s != htab->srelplt2)
b34976b6 17176 relocs = TRUE;
252b5132
RH		 17177
17178 /* We use the reloc_count field as a counter if we need
17179 to copy relocs into the output file. */
17180 s->reloc_count = 0;
17181 }
17182 }
34e77a92
RS		 17183 else if (s != htab->root.sgot
17184 && s != htab->root.sgotplt
17185 && s != htab->root.iplt
17186 && s != htab->root.igotplt
5474d94f 17187 && s != htab->root.sdynbss
e8b09b87
CL		 17188 && s != htab->root.sdynrelro
17189 && s != htab->srofixup)
252b5132
RH		 17190 {
17191 /* It's not one of our sections, so don't allocate space. */
17192 continue;
17193 }
17194
c456f082 17195 if (s->size == 0)
252b5132 17196 {
c456f082 17197 /* If we don't need this section, strip it from the
00a97672
RS		 17198 output file. This is mostly to handle .rel(a).bss and
17199 .rel(a).plt. We must create both sections in
c456f082
AM		 17200 create_dynamic_sections, because they must be created
17201 before the linker maps input sections to output
17202 sections. The linker does that before
17203 adjust_dynamic_symbol is called, and it is that
17204 function which decides whether anything needs to go
17205 into these sections. */
8423293d 17206 s->flags |= SEC_EXCLUDE;
252b5132
RH		 17207 continue;
17208 }
17209
c456f082
AM		 17210 if ((s->flags & SEC_HAS_CONTENTS) == 0)
17211 continue;
17212
252b5132 17213 /* Allocate memory for the section contents. */
21d799b5 17214 s->contents = (unsigned char *) bfd_zalloc (dynobj, s->size);
c456f082 17215 if (s->contents == NULL)
b34976b6 17216 return FALSE;
252b5132
RH		 17217 }
17218
17219 if (elf_hash_table (info)->dynamic_sections_created)
17220 {
17221 /* Add some entries to the .dynamic section. We fill in the
17222 values later, in elf32_arm_finish_dynamic_sections, but we
17223 must add the entries now so that we get the correct size for
17224 the .dynamic section. The DT_DEBUG entry is filled in by the
17225 dynamic linker and used by the debugger. */
dc810e39 17226#define add_dynamic_entry(TAG, VAL) \
5a580b3a 17227 _bfd_elf_add_dynamic_entry (info, TAG, VAL)
dc810e39 17228
0e1862bb 17229 if (bfd_link_executable (info))
252b5132 17230 {
dc810e39 17231 if (!add_dynamic_entry (DT_DEBUG, 0))
b34976b6 17232 return FALSE;
252b5132
RH		 17233 }
17234
17235 if (plt)
17236 {
dc810e39
AM		 17237 if ( !add_dynamic_entry (DT_PLTGOT, 0)
17238 || !add_dynamic_entry (DT_PLTRELSZ, 0)
00a97672
RS		 17239 || !add_dynamic_entry (DT_PLTREL,
17240 htab->use_rel ? DT_REL : DT_RELA)
dc810e39 17241 || !add_dynamic_entry (DT_JMPREL, 0))
b34976b6 17242 return FALSE;
0855e32b 17243
5025eb7c
AO		 17244 if (htab->dt_tlsdesc_plt
17245 && (!add_dynamic_entry (DT_TLSDESC_PLT,0)
17246 || !add_dynamic_entry (DT_TLSDESC_GOT,0)))
b38cadfb 17247 return FALSE;
252b5132
RH		 17248 }
17249
17250 if (relocs)
17251 {
00a97672
RS		 17252 if (htab->use_rel)
17253 {
17254 if (!add_dynamic_entry (DT_REL, 0)
17255 || !add_dynamic_entry (DT_RELSZ, 0)
17256 || !add_dynamic_entry (DT_RELENT, RELOC_SIZE (htab)))
17257 return FALSE;
17258 }
17259 else
17260 {
17261 if (!add_dynamic_entry (DT_RELA, 0)
17262 || !add_dynamic_entry (DT_RELASZ, 0)
17263 || !add_dynamic_entry (DT_RELAENT, RELOC_SIZE (htab)))
17264 return FALSE;
17265 }
252b5132
RH		 17266 }
17267
08d1f311
DJ		 17268 /* If any dynamic relocs apply to a read-only section,
17269 then we need a DT_TEXTREL entry. */
17270 if ((info->flags & DF_TEXTREL) == 0)
63c1f59d 17271 elf_link_hash_traverse (&htab->root, maybe_set_textrel, info);
08d1f311 17272
99e4ae17 17273 if ((info->flags & DF_TEXTREL) != 0)
252b5132 17274 {
dc810e39 17275 if (!add_dynamic_entry (DT_TEXTREL, 0))
b34976b6 17276 return FALSE;
252b5132 17277 }
7a2b07ff
NS		 17278 if (htab->vxworks_p
17279 && !elf_vxworks_add_dynamic_entries (output_bfd, info))
17280 return FALSE;
252b5132 17281 }
8532796c 17282#undef add_dynamic_entry
252b5132 17283
b34976b6 17284 return TRUE;
252b5132
RH		 17285}
17286
0855e32b
NS		 17287/* Size sections even though they're not dynamic. We use it to setup
17288 _TLS_MODULE_BASE_, if needed. */
17289
17290static bfd_boolean
17291elf32_arm_always_size_sections (bfd *output_bfd,
99059e56 17292 struct bfd_link_info *info)
0855e32b
NS		 17293{
17294 asection *tls_sec;
cb10292c
CL		 17295 struct elf32_arm_link_hash_table *htab;
17296
17297 htab = elf32_arm_hash_table (info);
0855e32b 17298
0e1862bb 17299 if (bfd_link_relocatable (info))
0855e32b
NS		 17300 return TRUE;
17301
17302 tls_sec = elf_hash_table (info)->tls_sec;
17303
17304 if (tls_sec)
17305 {
17306 struct elf_link_hash_entry *tlsbase;
17307
17308 tlsbase = elf_link_hash_lookup
17309 (elf_hash_table (info), "_TLS_MODULE_BASE_", TRUE, TRUE, FALSE);
17310
17311 if (tlsbase)
99059e56
RM		 17312 {
17313 struct bfd_link_hash_entry *bh = NULL;
0855e32b 17314 const struct elf_backend_data *bed
99059e56 17315 = get_elf_backend_data (output_bfd);
0855e32b 17316
99059e56 17317 if (!(_bfd_generic_link_add_one_symbol
0855e32b
NS		 17318 (info, output_bfd, "_TLS_MODULE_BASE_", BSF_LOCAL,
17319 tls_sec, 0, NULL, FALSE,
17320 bed->collect, &bh)))
17321 return FALSE;
b38cadfb 17322
99059e56
RM		 17323 tlsbase->type = STT_TLS;
17324 tlsbase = (struct elf_link_hash_entry *)bh;
17325 tlsbase->def_regular = 1;
17326 tlsbase->other = STV_HIDDEN;
17327 (*bed->elf_backend_hide_symbol) (info, tlsbase, TRUE);
0855e32b
NS		 17328 }
17329 }
cb10292c
CL		 17330
17331 if (htab->fdpic_p && !bfd_link_relocatable (info)
17332 && !bfd_elf_stack_segment_size (output_bfd, info,
17333 "__stacksize", DEFAULT_STACK_SIZE))
17334 return FALSE;
17335
0855e32b
NS		 17336 return TRUE;
17337}
17338
252b5132
RH		 17339/* Finish up dynamic symbol handling. We set the contents of various
17340 dynamic sections here. */
17341
b34976b6 17342static bfd_boolean
906e58ca
NC		 17343elf32_arm_finish_dynamic_symbol (bfd * output_bfd,
17344 struct bfd_link_info * info,
17345 struct elf_link_hash_entry * h,
17346 Elf_Internal_Sym * sym)
252b5132 17347{
e5a52504 17348 struct elf32_arm_link_hash_table *htab;
b7693d02 17349 struct elf32_arm_link_hash_entry *eh;
252b5132 17350
e5a52504 17351 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 17352 if (htab == NULL)
17353 return FALSE;
17354
b7693d02 17355 eh = (struct elf32_arm_link_hash_entry *) h;
252b5132
RH		 17356
17357 if (h->plt.offset != (bfd_vma) -1)
17358 {
34e77a92 17359 if (!eh->is_iplt)
e5a52504 17360 {
34e77a92 17361 BFD_ASSERT (h->dynindx != -1);
57460bcf
NC		 17362 if (! elf32_arm_populate_plt_entry (output_bfd, info, &h->plt, &eh->plt,
17363 h->dynindx, 0))
17364 return FALSE;
e5a52504 17365 }
57e8b36a 17366
f5385ebf 17367 if (!h->def_regular)
252b5132
RH		 17368 {
17369 /* Mark the symbol as undefined, rather than as defined in
3a635617 17370 the .plt section. */
252b5132 17371 sym->st_shndx = SHN_UNDEF;
3a635617 17372 /* If the symbol is weak we need to clear the value.
d982ba73
PB		 17373 Otherwise, the PLT entry would provide a definition for
17374 the symbol even if the symbol wasn't defined anywhere,
3a635617
WN		 17375 and so the symbol would never be NULL. Leave the value if
17376 there were any relocations where pointer equality matters
17377 (this is a clue for the dynamic linker, to make function
17378 pointer comparisons work between an application and shared
17379 library). */
97323ad1 17380 if (!h->ref_regular_nonweak || !h->pointer_equality_needed)
d982ba73 17381 sym->st_value = 0;
252b5132 17382 }
34e77a92
RS		 17383 else if (eh->is_iplt && eh->plt.noncall_refcount != 0)
17384 {
17385 /* At least one non-call relocation references this .iplt entry,
17386 so the .iplt entry is the function's canonical address. */
17387 sym->st_info = ELF_ST_INFO (ELF_ST_BIND (sym->st_info), STT_FUNC);
39d911fc 17388 ARM_SET_SYM_BRANCH_TYPE (sym->st_target_internal, ST_BRANCH_TO_ARM);
34e77a92
RS		 17389 sym->st_shndx = (_bfd_elf_section_from_bfd_section
17390 (output_bfd, htab->root.iplt->output_section));
17391 sym->st_value = (h->plt.offset
17392 + htab->root.iplt->output_section->vma
17393 + htab->root.iplt->output_offset);
17394 }
252b5132
RH		 17395 }
17396
f5385ebf 17397 if (h->needs_copy)
252b5132
RH		 17398 {
17399 asection * s;
947216bf 17400 Elf_Internal_Rela rel;
252b5132
RH		 17401
17402 /* This symbol needs a copy reloc. Set it up. */
252b5132
RH		 17403 BFD_ASSERT (h->dynindx != -1
17404 && (h->root.type == bfd_link_hash_defined
17405 || h->root.type == bfd_link_hash_defweak));
17406
00a97672 17407 rel.r_addend = 0;
252b5132
RH		 17408 rel.r_offset = (h->root.u.def.value
17409 + h->root.u.def.section->output_section->vma
17410 + h->root.u.def.section->output_offset);
17411 rel.r_info = ELF32_R_INFO (h->dynindx, R_ARM_COPY);
afbf7e8e 17412 if (h->root.u.def.section == htab->root.sdynrelro)
5474d94f
AM		 17413 s = htab->root.sreldynrelro;
17414 else
17415 s = htab->root.srelbss;
47beaa6a 17416 elf32_arm_add_dynreloc (output_bfd, info, s, &rel);
252b5132
RH		 17417 }
17418
00a97672 17419 /* Mark _DYNAMIC and _GLOBAL_OFFSET_TABLE_ as absolute. On VxWorks,
fac7bd64
CL		 17420 and for FDPIC, the _GLOBAL_OFFSET_TABLE_ symbol is not absolute:
17421 it is relative to the ".got" section. */
9637f6ef 17422 if (h == htab->root.hdynamic
fac7bd64 17423 || (!htab->fdpic_p && !htab->vxworks_p && h == htab->root.hgot))
252b5132
RH		 17424 sym->st_shndx = SHN_ABS;
17425
b34976b6 17426 return TRUE;
252b5132
RH		 17427}
17428
0855e32b
NS		 17429static void
17430arm_put_trampoline (struct elf32_arm_link_hash_table *htab, bfd *output_bfd,
17431 void *contents,
17432 const unsigned long *template, unsigned count)
17433{
17434 unsigned ix;
b38cadfb 17435
0855e32b
NS		 17436 for (ix = 0; ix != count; ix++)
17437 {
17438 unsigned long insn = template[ix];
17439
17440 /* Emit mov pc,rx if bx is not permitted. */
17441 if (htab->fix_v4bx == 1 && (insn & 0x0ffffff0) == 0x012fff10)
17442 insn = (insn & 0xf000000f) | 0x01a0f000;
17443 put_arm_insn (htab, output_bfd, insn, (char *)contents + ix*4);
17444 }
17445}
17446
99059e56
RM		 17447/* Install the special first PLT entry for elf32-arm-nacl. Unlike
17448 other variants, NaCl needs this entry in a static executable's
17449 .iplt too. When we're handling that case, GOT_DISPLACEMENT is
17450 zero. For .iplt really only the last bundle is useful, and .iplt
17451 could have a shorter first entry, with each individual PLT entry's
17452 relative branch calculated differently so it targets the last
17453 bundle instead of the instruction before it (labelled .Lplt_tail
17454 above). But it's simpler to keep the size and layout of PLT0
17455 consistent with the dynamic case, at the cost of some dead code at
17456 the start of .iplt and the one dead store to the stack at the start
17457 of .Lplt_tail. */
17458static void
17459arm_nacl_put_plt0 (struct elf32_arm_link_hash_table *htab, bfd *output_bfd,
17460 asection *plt, bfd_vma got_displacement)
17461{
17462 unsigned int i;
17463
17464 put_arm_insn (htab, output_bfd,
17465 elf32_arm_nacl_plt0_entry[0]
17466 | arm_movw_immediate (got_displacement),
17467 plt->contents + 0);
17468 put_arm_insn (htab, output_bfd,
17469 elf32_arm_nacl_plt0_entry[1]
17470 | arm_movt_immediate (got_displacement),
17471 plt->contents + 4);
17472
17473 for (i = 2; i < ARRAY_SIZE (elf32_arm_nacl_plt0_entry); ++i)
17474 put_arm_insn (htab, output_bfd,
17475 elf32_arm_nacl_plt0_entry[i],
17476 plt->contents + (i * 4));
17477}
17478
252b5132
RH		 17479/* Finish up the dynamic sections. */
17480
b34976b6 17481static bfd_boolean
57e8b36a 17482elf32_arm_finish_dynamic_sections (bfd * output_bfd, struct bfd_link_info * info)
252b5132
RH		 17483{
17484 bfd * dynobj;
17485 asection * sgot;
17486 asection * sdyn;
4dfe6ac6
NC		 17487 struct elf32_arm_link_hash_table *htab;
17488
17489 htab = elf32_arm_hash_table (info);
17490 if (htab == NULL)
17491 return FALSE;
252b5132
RH		 17492
17493 dynobj = elf_hash_table (info)->dynobj;
17494
362d30a1 17495 sgot = htab->root.sgotplt;
894891db
NC		 17496 /* A broken linker script might have discarded the dynamic sections.
17497 Catch this here so that we do not seg-fault later on. */
17498 if (sgot != NULL && bfd_is_abs_section (sgot->output_section))
17499 return FALSE;
3d4d4302 17500 sdyn = bfd_get_linker_section (dynobj, ".dynamic");
252b5132
RH		 17501
17502 if (elf_hash_table (info)->dynamic_sections_created)
17503 {
17504 asection *splt;
17505 Elf32_External_Dyn *dyncon, *dynconend;
17506
362d30a1 17507 splt = htab->root.splt;
24a1ba0f 17508 BFD_ASSERT (splt != NULL && sdyn != NULL);
cbc704f3 17509 BFD_ASSERT (htab->symbian_p || sgot != NULL);
252b5132
RH		 17510
17511 dyncon = (Elf32_External_Dyn *) sdyn->contents;
eea6121a 17512 dynconend = (Elf32_External_Dyn *) (sdyn->contents + sdyn->size);
9b485d32 17513
252b5132
RH		 17514 for (; dyncon < dynconend; dyncon++)
17515 {
17516 Elf_Internal_Dyn dyn;
17517 const char * name;
17518 asection * s;
17519
17520 bfd_elf32_swap_dyn_in (dynobj, dyncon, &dyn);
17521
17522 switch (dyn.d_tag)
17523 {
229fcec5
MM		 17524 unsigned int type;
17525
252b5132 17526 default:
7a2b07ff
NS		 17527 if (htab->vxworks_p
17528 && elf_vxworks_finish_dynamic_entry (output_bfd, &dyn))
17529 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
252b5132
RH		 17530 break;
17531
229fcec5
MM		 17532 case DT_HASH:
17533 name = ".hash";
17534 goto get_vma_if_bpabi;
17535 case DT_STRTAB:
17536 name = ".dynstr";
17537 goto get_vma_if_bpabi;
17538 case DT_SYMTAB:
17539 name = ".dynsym";
17540 goto get_vma_if_bpabi;
c0042f5d
MM		 17541 case DT_VERSYM:
17542 name = ".gnu.version";
17543 goto get_vma_if_bpabi;
17544 case DT_VERDEF:
17545 name = ".gnu.version_d";
17546 goto get_vma_if_bpabi;
17547 case DT_VERNEED:
17548 name = ".gnu.version_r";
17549 goto get_vma_if_bpabi;
17550
252b5132 17551 case DT_PLTGOT:
4ade44b7 17552 name = htab->symbian_p ? ".got" : ".got.plt";
252b5132
RH		 17553 goto get_vma;
17554 case DT_JMPREL:
00a97672 17555 name = RELOC_SECTION (htab, ".plt");
252b5132 17556 get_vma:
4ade44b7 17557 s = bfd_get_linker_section (dynobj, name);
05456594
NC		 17558 if (s == NULL)
17559 {
4eca0228 17560 _bfd_error_handler
4ade44b7 17561 (_("could not find section %s"), name);
05456594
NC		 17562 bfd_set_error (bfd_error_invalid_operation);
17563 return FALSE;
17564 }
229fcec5 17565 if (!htab->symbian_p)
4ade44b7 17566 dyn.d_un.d_ptr = s->output_section->vma + s->output_offset;
229fcec5
MM		 17567 else
17568 /* In the BPABI, tags in the PT_DYNAMIC section point
17569 at the file offset, not the memory address, for the
17570 convenience of the post linker. */
4ade44b7 17571 dyn.d_un.d_ptr = s->output_section->filepos + s->output_offset;
252b5132
RH		 17572 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
17573 break;
17574
229fcec5
MM		 17575 get_vma_if_bpabi:
17576 if (htab->symbian_p)
17577 goto get_vma;
17578 break;
17579
252b5132 17580 case DT_PLTRELSZ:
362d30a1 17581 s = htab->root.srelplt;
252b5132 17582 BFD_ASSERT (s != NULL);
eea6121a 17583 dyn.d_un.d_val = s->size;
252b5132
RH		 17584 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
17585 break;
906e58ca 17586
252b5132 17587 case DT_RELSZ:
00a97672 17588 case DT_RELASZ:
229fcec5
MM		 17589 case DT_REL:
17590 case DT_RELA:
229fcec5
MM		 17591 /* In the BPABI, the DT_REL tag must point at the file
17592 offset, not the VMA, of the first relocation
17593 section. So, we use code similar to that in
17594 elflink.c, but do not check for SHF_ALLOC on the
64f52338
AM		 17595 relocation section, since relocation sections are
17596 never allocated under the BPABI. PLT relocs are also
17597 included. */
229fcec5
MM		 17598 if (htab->symbian_p)
17599 {
17600 unsigned int i;
17601 type = ((dyn.d_tag == DT_REL || dyn.d_tag == DT_RELSZ)
17602 ? SHT_REL : SHT_RELA);
17603 dyn.d_un.d_val = 0;
17604 for (i = 1; i < elf_numsections (output_bfd); i++)
17605 {
906e58ca 17606 Elf_Internal_Shdr *hdr
229fcec5
MM		 17607 = elf_elfsections (output_bfd)[i];
17608 if (hdr->sh_type == type)
17609 {
906e58ca 17610 if (dyn.d_tag == DT_RELSZ
229fcec5
MM		 17611 || dyn.d_tag == DT_RELASZ)
17612 dyn.d_un.d_val += hdr->sh_size;
de52dba4
AM		 17613 else if ((ufile_ptr) hdr->sh_offset
17614 <= dyn.d_un.d_val - 1)
229fcec5
MM		 17615 dyn.d_un.d_val = hdr->sh_offset;
17616 }
17617 }
17618 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
17619 }
252b5132 17620 break;
88f7bcd5 17621
0855e32b 17622 case DT_TLSDESC_PLT:
99059e56 17623 s = htab->root.splt;
0855e32b
NS		 17624 dyn.d_un.d_ptr = (s->output_section->vma + s->output_offset
17625 + htab->dt_tlsdesc_plt);
17626 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
17627 break;
17628
17629 case DT_TLSDESC_GOT:
99059e56 17630 s = htab->root.sgot;
0855e32b 17631 dyn.d_un.d_ptr = (s->output_section->vma + s->output_offset
99059e56 17632 + htab->dt_tlsdesc_got);
0855e32b
NS		 17633 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
17634 break;
17635
88f7bcd5
NC		 17636 /* Set the bottom bit of DT_INIT/FINI if the
17637 corresponding function is Thumb. */
17638 case DT_INIT:
17639 name = info->init_function;
17640 goto get_sym;
17641 case DT_FINI:
17642 name = info->fini_function;
17643 get_sym:
17644 /* If it wasn't set by elf_bfd_final_link
4cc11e76 17645 then there is nothing to adjust. */
88f7bcd5
NC		 17646 if (dyn.d_un.d_val != 0)
17647 {
17648 struct elf_link_hash_entry * eh;
17649
17650 eh = elf_link_hash_lookup (elf_hash_table (info), name,
b34976b6 17651 FALSE, FALSE, TRUE);
39d911fc
TP		 17652 if (eh != NULL
17653 && ARM_GET_SYM_BRANCH_TYPE (eh->target_internal)
17654 == ST_BRANCH_TO_THUMB)
88f7bcd5
NC		 17655 {
17656 dyn.d_un.d_val |= 1;
b34976b6 17657 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
88f7bcd5
NC		 17658 }
17659 }
17660 break;
252b5132
RH		 17661 }
17662 }
17663
24a1ba0f 17664 /* Fill in the first entry in the procedure linkage table. */
4dfe6ac6 17665 if (splt->size > 0 && htab->plt_header_size)
f7a74f8c 17666 {
00a97672
RS		 17667 const bfd_vma *plt0_entry;
17668 bfd_vma got_address, plt_address, got_displacement;
17669
17670 /* Calculate the addresses of the GOT and PLT. */
17671 got_address = sgot->output_section->vma + sgot->output_offset;
17672 plt_address = splt->output_section->vma + splt->output_offset;
17673
17674 if (htab->vxworks_p)
17675 {
17676 /* The VxWorks GOT is relocated by the dynamic linker.
17677 Therefore, we must emit relocations rather than simply
17678 computing the values now. */
17679 Elf_Internal_Rela rel;
17680
17681 plt0_entry = elf32_arm_vxworks_exec_plt0_entry;
52ab56c2
PB		 17682 put_arm_insn (htab, output_bfd, plt0_entry[0],
17683 splt->contents + 0);
17684 put_arm_insn (htab, output_bfd, plt0_entry[1],
17685 splt->contents + 4);
17686 put_arm_insn (htab, output_bfd, plt0_entry[2],
17687 splt->contents + 8);
00a97672
RS		 17688 bfd_put_32 (output_bfd, got_address, splt->contents + 12);
17689
8029a119 17690 /* Generate a relocation for _GLOBAL_OFFSET_TABLE_. */
00a97672
RS		 17691 rel.r_offset = plt_address + 12;
17692 rel.r_info = ELF32_R_INFO (htab->root.hgot->indx, R_ARM_ABS32);
17693 rel.r_addend = 0;
17694 SWAP_RELOC_OUT (htab) (output_bfd, &rel,
17695 htab->srelplt2->contents);
17696 }
b38cadfb 17697 else if (htab->nacl_p)
99059e56
RM		 17698 arm_nacl_put_plt0 (htab, output_bfd, splt,
17699 got_address + 8 - (plt_address + 16));
eed94f8f
NC		 17700 else if (using_thumb_only (htab))
17701 {
17702 got_displacement = got_address - (plt_address + 12);
17703
17704 plt0_entry = elf32_thumb2_plt0_entry;
17705 put_arm_insn (htab, output_bfd, plt0_entry[0],
17706 splt->contents + 0);
17707 put_arm_insn (htab, output_bfd, plt0_entry[1],
17708 splt->contents + 4);
17709 put_arm_insn (htab, output_bfd, plt0_entry[2],
17710 splt->contents + 8);
17711
17712 bfd_put_32 (output_bfd, got_displacement, splt->contents + 12);
17713 }
00a97672
RS		 17714 else
17715 {
17716 got_displacement = got_address - (plt_address + 16);
17717
17718 plt0_entry = elf32_arm_plt0_entry;
52ab56c2
PB		 17719 put_arm_insn (htab, output_bfd, plt0_entry[0],
17720 splt->contents + 0);
17721 put_arm_insn (htab, output_bfd, plt0_entry[1],
17722 splt->contents + 4);
17723 put_arm_insn (htab, output_bfd, plt0_entry[2],
17724 splt->contents + 8);
17725 put_arm_insn (htab, output_bfd, plt0_entry[3],
17726 splt->contents + 12);
5e681ec4 17727
5e681ec4 17728#ifdef FOUR_WORD_PLT
00a97672
RS		 17729 /* The displacement value goes in the otherwise-unused
17730 last word of the second entry. */
17731 bfd_put_32 (output_bfd, got_displacement, splt->contents + 28);
5e681ec4 17732#else
00a97672 17733 bfd_put_32 (output_bfd, got_displacement, splt->contents + 16);
5e681ec4 17734#endif
00a97672 17735 }
f7a74f8c 17736 }
252b5132
RH		 17737
17738 /* UnixWare sets the entsize of .plt to 4, although that doesn't
17739 really seem like the right value. */
74541ad4
AM		 17740 if (splt->output_section->owner == output_bfd)
17741 elf_section_data (splt->output_section)->this_hdr.sh_entsize = 4;
00a97672 17742
0855e32b
NS		 17743 if (htab->dt_tlsdesc_plt)
17744 {
17745 bfd_vma got_address
17746 = sgot->output_section->vma + sgot->output_offset;
17747 bfd_vma gotplt_address = (htab->root.sgot->output_section->vma
17748 + htab->root.sgot->output_offset);
17749 bfd_vma plt_address
17750 = splt->output_section->vma + splt->output_offset;
17751
b38cadfb 17752 arm_put_trampoline (htab, output_bfd,
0855e32b
NS		 17753 splt->contents + htab->dt_tlsdesc_plt,
17754 dl_tlsdesc_lazy_trampoline, 6);
17755
17756 bfd_put_32 (output_bfd,
17757 gotplt_address + htab->dt_tlsdesc_got
17758 - (plt_address + htab->dt_tlsdesc_plt)
17759 - dl_tlsdesc_lazy_trampoline[6],
17760 splt->contents + htab->dt_tlsdesc_plt + 24);
17761 bfd_put_32 (output_bfd,
17762 got_address - (plt_address + htab->dt_tlsdesc_plt)
17763 - dl_tlsdesc_lazy_trampoline[7],
17764 splt->contents + htab->dt_tlsdesc_plt + 24 + 4);
17765 }
17766
17767 if (htab->tls_trampoline)
17768 {
b38cadfb 17769 arm_put_trampoline (htab, output_bfd,
0855e32b
NS		 17770 splt->contents + htab->tls_trampoline,
17771 tls_trampoline, 3);
17772#ifdef FOUR_WORD_PLT
17773 bfd_put_32 (output_bfd, 0x00000000,
17774 splt->contents + htab->tls_trampoline + 12);
b38cadfb 17775#endif
0855e32b
NS		 17776 }
17777
0e1862bb
L		 17778 if (htab->vxworks_p
17779 && !bfd_link_pic (info)
17780 && htab->root.splt->size > 0)
00a97672
RS		 17781 {
17782 /* Correct the .rel(a).plt.unloaded relocations. They will have
17783 incorrect symbol indexes. */
17784 int num_plts;
eed62c48 17785 unsigned char *p;
00a97672 17786
362d30a1 17787 num_plts = ((htab->root.splt->size - htab->plt_header_size)
00a97672
RS		 17788 / htab->plt_entry_size);
17789 p = htab->srelplt2->contents + RELOC_SIZE (htab);
17790
17791 for (; num_plts; num_plts--)
17792 {
17793 Elf_Internal_Rela rel;
17794
17795 SWAP_RELOC_IN (htab) (output_bfd, p, &rel);
17796 rel.r_info = ELF32_R_INFO (htab->root.hgot->indx, R_ARM_ABS32);
17797 SWAP_RELOC_OUT (htab) (output_bfd, &rel, p);
17798 p += RELOC_SIZE (htab);
17799
17800 SWAP_RELOC_IN (htab) (output_bfd, p, &rel);
17801 rel.r_info = ELF32_R_INFO (htab->root.hplt->indx, R_ARM_ABS32);
17802 SWAP_RELOC_OUT (htab) (output_bfd, &rel, p);
17803 p += RELOC_SIZE (htab);
17804 }
17805 }
252b5132
RH		 17806 }
17807
99059e56
RM		 17808 if (htab->nacl_p && htab->root.iplt != NULL && htab->root.iplt->size > 0)
17809 /* NaCl uses a special first entry in .iplt too. */
17810 arm_nacl_put_plt0 (htab, output_bfd, htab->root.iplt, 0);
17811
252b5132 17812 /* Fill in the first three entries in the global offset table. */
229fcec5 17813 if (sgot)
252b5132 17814 {
229fcec5
MM		 17815 if (sgot->size > 0)
17816 {
17817 if (sdyn == NULL)
17818 bfd_put_32 (output_bfd, (bfd_vma) 0, sgot->contents);
17819 else
17820 bfd_put_32 (output_bfd,
17821 sdyn->output_section->vma + sdyn->output_offset,
17822 sgot->contents);
17823 bfd_put_32 (output_bfd, (bfd_vma) 0, sgot->contents + 4);
17824 bfd_put_32 (output_bfd, (bfd_vma) 0, sgot->contents + 8);
17825 }
252b5132 17826
229fcec5
MM		 17827 elf_section_data (sgot->output_section)->this_hdr.sh_entsize = 4;
17828 }
252b5132 17829
e8b09b87
CL		 17830 /* At the very end of the .rofixup section is a pointer to the GOT. */
17831 if (htab->fdpic_p && htab->srofixup != NULL)
17832 {
17833 struct elf_link_hash_entry *hgot = htab->root.hgot;
17834
17835 bfd_vma got_value = hgot->root.u.def.value
17836 + hgot->root.u.def.section->output_section->vma
17837 + hgot->root.u.def.section->output_offset;
17838
17839 arm_elf_add_rofixup(output_bfd, htab->srofixup, got_value);
17840
17841 /* Make sure we allocated and generated the same number of fixups. */
17842 BFD_ASSERT (htab->srofixup->reloc_count * 4 == htab->srofixup->size);
17843 }
17844
b34976b6 17845 return TRUE;
252b5132
RH		 17846}
17847
ba96a88f 17848static void
57e8b36a 17849elf32_arm_post_process_headers (bfd * abfd, struct bfd_link_info * link_info ATTRIBUTE_UNUSED)
ba96a88f 17850{
9b485d32 17851 Elf_Internal_Ehdr * i_ehdrp; /* ELF file header, internal form. */
e489d0ae 17852 struct elf32_arm_link_hash_table *globals;
ac4c9b04 17853 struct elf_segment_map *m;
ba96a88f
NC		 17854
17855 i_ehdrp = elf_elfheader (abfd);
17856
94a3258f
PB		 17857 if (EF_ARM_EABI_VERSION (i_ehdrp->e_flags) == EF_ARM_EABI_UNKNOWN)
17858 i_ehdrp->e_ident[EI_OSABI] = ELFOSABI_ARM;
17859 else
7394f108 17860 _bfd_elf_post_process_headers (abfd, link_info);
ba96a88f 17861 i_ehdrp->e_ident[EI_ABIVERSION] = ARM_ELF_ABI_VERSION;
e489d0ae 17862
93204d3a
PB		 17863 if (link_info)
17864 {
17865 globals = elf32_arm_hash_table (link_info);
4dfe6ac6 17866 if (globals != NULL && globals->byteswap_code)
93204d3a 17867 i_ehdrp->e_flags |= EF_ARM_BE8;
18a20338
CL		 17868
17869 if (globals->fdpic_p)
17870 i_ehdrp->e_ident[EI_OSABI] |= ELFOSABI_ARM_FDPIC;
93204d3a 17871 }
3bfcb652
NC		 17872
17873 if (EF_ARM_EABI_VERSION (i_ehdrp->e_flags) == EF_ARM_EABI_VER5
17874 && ((i_ehdrp->e_type == ET_DYN) || (i_ehdrp->e_type == ET_EXEC)))
17875 {
17876 int abi = bfd_elf_get_obj_attr_int (abfd, OBJ_ATTR_PROC, Tag_ABI_VFP_args);
5c294fee 17877 if (abi == AEABI_VFP_args_vfp)
3bfcb652
NC		 17878 i_ehdrp->e_flags |= EF_ARM_ABI_FLOAT_HARD;
17879 else
17880 i_ehdrp->e_flags |= EF_ARM_ABI_FLOAT_SOFT;
17881 }
ac4c9b04
MG		 17882
17883 /* Scan segment to set p_flags attribute if it contains only sections with
f0728ee3 17884 SHF_ARM_PURECODE flag. */
ac4c9b04
MG		 17885 for (m = elf_seg_map (abfd); m != NULL; m = m->next)
17886 {
17887 unsigned int j;
17888
17889 if (m->count == 0)
17890 continue;
17891 for (j = 0; j < m->count; j++)
17892 {
f0728ee3 17893 if (!(elf_section_flags (m->sections[j]) & SHF_ARM_PURECODE))
ac4c9b04
MG		 17894 break;
17895 }
17896 if (j == m->count)
17897 {
17898 m->p_flags = PF_X;
17899 m->p_flags_valid = 1;
17900 }
17901 }
ba96a88f
NC		 17902}
17903
99e4ae17 17904static enum elf_reloc_type_class
7e612e98
AM		 17905elf32_arm_reloc_type_class (const struct bfd_link_info *info ATTRIBUTE_UNUSED,
17906 const asection *rel_sec ATTRIBUTE_UNUSED,
17907 const Elf_Internal_Rela *rela)
99e4ae17 17908{
f51e552e 17909 switch ((int) ELF32_R_TYPE (rela->r_info))
99e4ae17
AJ		 17910 {
17911 case R_ARM_RELATIVE:
17912 return reloc_class_relative;
17913 case R_ARM_JUMP_SLOT:
17914 return reloc_class_plt;
17915 case R_ARM_COPY:
17916 return reloc_class_copy;
109575d7
JW		 17917 case R_ARM_IRELATIVE:
17918 return reloc_class_ifunc;
99e4ae17
AJ		 17919 default:
17920 return reloc_class_normal;
17921 }
17922}
17923
e489d0ae 17924static void
cc364be6 17925arm_final_write_processing (bfd *abfd)
e16bb312 17926{
5a6c6817 17927 bfd_arm_update_notes (abfd, ARM_NOTE_SECTION);
e16bb312
NC		 17928}
17929
cc364be6
AM		 17930static bfd_boolean
17931elf32_arm_final_write_processing (bfd *abfd)
06f44071 17932{
cc364be6
AM		 17933 arm_final_write_processing (abfd);
17934 return _bfd_elf_final_write_processing (abfd);
06f44071
AM		 17935}
17936
40a18ebd
NC		 17937/* Return TRUE if this is an unwinding table entry. */
17938
17939static bfd_boolean
17940is_arm_elf_unwind_section_name (bfd * abfd ATTRIBUTE_UNUSED, const char * name)
17941{
0112cd26
NC		 17942 return (CONST_STRNEQ (name, ELF_STRING_ARM_unwind)
17943 || CONST_STRNEQ (name, ELF_STRING_ARM_unwind_once));
40a18ebd
NC		 17944}
17945
17946
17947/* Set the type and flags for an ARM section. We do this by
17948 the section name, which is a hack, but ought to work. */
17949
17950static bfd_boolean
17951elf32_arm_fake_sections (bfd * abfd, Elf_Internal_Shdr * hdr, asection * sec)
17952{
17953 const char * name;
17954
fd361982 17955 name = bfd_section_name (sec);
40a18ebd
NC		 17956
17957 if (is_arm_elf_unwind_section_name (abfd, name))
17958 {
17959 hdr->sh_type = SHT_ARM_EXIDX;
17960 hdr->sh_flags |= SHF_LINK_ORDER;
17961 }
ac4c9b04 17962
f0728ee3
AV		 17963 if (sec->flags & SEC_ELF_PURECODE)
17964 hdr->sh_flags |= SHF_ARM_PURECODE;
ac4c9b04 17965
40a18ebd
NC		 17966 return TRUE;
17967}
17968
6dc132d9
L		 17969/* Handle an ARM specific section when reading an object file. This is
17970 called when bfd_section_from_shdr finds a section with an unknown
17971 type. */
40a18ebd
NC		 17972
17973static bfd_boolean
17974elf32_arm_section_from_shdr (bfd *abfd,
17975 Elf_Internal_Shdr * hdr,
6dc132d9
L		 17976 const char *name,
17977 int shindex)
40a18ebd
NC		 17978{
17979 /* There ought to be a place to keep ELF backend specific flags, but
17980 at the moment there isn't one. We just keep track of the
17981 sections by their name, instead. Fortunately, the ABI gives
17982 names for all the ARM specific sections, so we will probably get
17983 away with this. */
17984 switch (hdr->sh_type)
17985 {
17986 case SHT_ARM_EXIDX:
0951f019
RE		 17987 case SHT_ARM_PREEMPTMAP:
17988 case SHT_ARM_ATTRIBUTES:
40a18ebd
NC		 17989 break;
17990
17991 default:
17992 return FALSE;
17993 }
17994
6dc132d9 17995 if (! _bfd_elf_make_section_from_shdr (abfd, hdr, name, shindex))
40a18ebd
NC		 17996 return FALSE;
17997
17998 return TRUE;
17999}
e489d0ae 18000
44444f50
NC		 18001static _arm_elf_section_data *
18002get_arm_elf_section_data (asection * sec)
18003{
47b2e99c
JZ		 18004 if (sec && sec->owner && is_arm_elf (sec->owner))
18005 return elf32_arm_section_data (sec);
44444f50
NC		 18006 else
18007 return NULL;
8e3de13a
NC		 18008}
18009
4e617b1e
PB		 18010typedef struct
18011{
57402f1e 18012 void *flaginfo;
4e617b1e 18013 struct bfd_link_info *info;
91a5743d
PB		 18014 asection *sec;
18015 int sec_shndx;
6e0b88f1
AM		 18016 int (*func) (void *, const char *, Elf_Internal_Sym *,
18017 asection *, struct elf_link_hash_entry *);
4e617b1e
PB		 18018} output_arch_syminfo;
18019
18020enum map_symbol_type
18021{
18022 ARM_MAP_ARM,
18023 ARM_MAP_THUMB,
18024 ARM_MAP_DATA
18025};
18026
18027
7413f23f 18028/* Output a single mapping symbol. */
4e617b1e
PB		 18029
18030static bfd_boolean
7413f23f
DJ		 18031elf32_arm_output_map_sym (output_arch_syminfo *osi,
18032 enum map_symbol_type type,
18033 bfd_vma offset)
4e617b1e
PB		 18034{
18035 static const char *names[3] = {"$a", "$t", "$d"};
4e617b1e
PB		 18036 Elf_Internal_Sym sym;
18037
91a5743d
PB		 18038 sym.st_value = osi->sec->output_section->vma
18039 + osi->sec->output_offset
18040 + offset;
4e617b1e
PB		 18041 sym.st_size = 0;
18042 sym.st_other = 0;
18043 sym.st_info = ELF_ST_INFO (STB_LOCAL, STT_NOTYPE);
91a5743d 18044 sym.st_shndx = osi->sec_shndx;
35fc36a8 18045 sym.st_target_internal = 0;
fe33d2fa 18046 elf32_arm_section_map_add (osi->sec, names[type][1], offset);
57402f1e 18047 return osi->func (osi->flaginfo, names[type], &sym, osi->sec, NULL) == 1;
4e617b1e
PB		 18048}
18049
34e77a92
RS		 18050/* Output mapping symbols for the PLT entry described by ROOT_PLT and ARM_PLT.
18051 IS_IPLT_ENTRY_P says whether the PLT is in .iplt rather than .plt. */
4e617b1e
PB		 18052
18053static bfd_boolean
34e77a92
RS		 18054elf32_arm_output_plt_map_1 (output_arch_syminfo *osi,
18055 bfd_boolean is_iplt_entry_p,
18056 union gotplt_union *root_plt,
18057 struct arm_plt_info *arm_plt)
4e617b1e 18058{
4e617b1e 18059 struct elf32_arm_link_hash_table *htab;
34e77a92 18060 bfd_vma addr, plt_header_size;
4e617b1e 18061
34e77a92 18062 if (root_plt->offset == (bfd_vma) -1)
4e617b1e
PB		 18063 return TRUE;
18064
4dfe6ac6
NC		 18065 htab = elf32_arm_hash_table (osi->info);
18066 if (htab == NULL)
18067 return FALSE;
18068
34e77a92
RS		 18069 if (is_iplt_entry_p)
18070 {
18071 osi->sec = htab->root.iplt;
18072 plt_header_size = 0;
18073 }
18074 else
18075 {
18076 osi->sec = htab->root.splt;
18077 plt_header_size = htab->plt_header_size;
18078 }
18079 osi->sec_shndx = (_bfd_elf_section_from_bfd_section
18080 (osi->info->output_bfd, osi->sec->output_section));
18081
18082 addr = root_plt->offset & -2;
4e617b1e
PB		 18083 if (htab->symbian_p)
18084 {
7413f23f 18085 if (!elf32_arm_output_map_sym (osi, ARM_MAP_ARM, addr))
4e617b1e 18086 return FALSE;
7413f23f 18087 if (!elf32_arm_output_map_sym (osi, ARM_MAP_DATA, addr + 4))
4e617b1e
PB		 18088 return FALSE;
18089 }
18090 else if (htab->vxworks_p)
18091 {
7413f23f 18092 if (!elf32_arm_output_map_sym (osi, ARM_MAP_ARM, addr))
4e617b1e 18093 return FALSE;
7413f23f 18094 if (!elf32_arm_output_map_sym (osi, ARM_MAP_DATA, addr + 8))
4e617b1e 18095 return FALSE;
7413f23f 18096 if (!elf32_arm_output_map_sym (osi, ARM_MAP_ARM, addr + 12))
4e617b1e 18097 return FALSE;
7413f23f 18098 if (!elf32_arm_output_map_sym (osi, ARM_MAP_DATA, addr + 20))
4e617b1e
PB		 18099 return FALSE;
18100 }
b38cadfb
NC		 18101 else if (htab->nacl_p)
18102 {
18103 if (!elf32_arm_output_map_sym (osi, ARM_MAP_ARM, addr))
18104 return FALSE;
18105 }
7801f98f
CL		 18106 else if (htab->fdpic_p)
18107 {
59029f57
CL		 18108 enum map_symbol_type type = using_thumb_only(htab)
18109 ? ARM_MAP_THUMB
18110 : ARM_MAP_ARM;
18111
7801f98f 18112 if (elf32_arm_plt_needs_thumb_stub_p (osi->info, arm_plt))
4b24dd1a
AM		 18113 if (!elf32_arm_output_map_sym (osi, ARM_MAP_THUMB, addr - 4))
18114 return FALSE;
59029f57 18115 if (!elf32_arm_output_map_sym (osi, type, addr))
4b24dd1a 18116 return FALSE;
7801f98f 18117 if (!elf32_arm_output_map_sym (osi, ARM_MAP_DATA, addr + 16))
4b24dd1a 18118 return FALSE;
7801f98f 18119 if (htab->plt_entry_size == 4 * ARRAY_SIZE(elf32_arm_fdpic_plt_entry))
4b24dd1a
AM		 18120 if (!elf32_arm_output_map_sym (osi, type, addr + 24))
18121 return FALSE;
7801f98f 18122 }
eed94f8f
NC		 18123 else if (using_thumb_only (htab))
18124 {
18125 if (!elf32_arm_output_map_sym (osi, ARM_MAP_THUMB, addr))
18126 return FALSE;
6a631e86 18127 }
4e617b1e
PB		 18128 else
18129 {
34e77a92 18130 bfd_boolean thumb_stub_p;
bd97cb95 18131
34e77a92
RS		 18132 thumb_stub_p = elf32_arm_plt_needs_thumb_stub_p (osi->info, arm_plt);
18133 if (thumb_stub_p)
4e617b1e 18134 {
7413f23f 18135 if (!elf32_arm_output_map_sym (osi, ARM_MAP_THUMB, addr - 4))
4e617b1e
PB		 18136 return FALSE;
18137 }
18138#ifdef FOUR_WORD_PLT
7413f23f 18139 if (!elf32_arm_output_map_sym (osi, ARM_MAP_ARM, addr))
4e617b1e 18140 return FALSE;
7413f23f 18141 if (!elf32_arm_output_map_sym (osi, ARM_MAP_DATA, addr + 12))
4e617b1e
PB		 18142 return FALSE;
18143#else
906e58ca 18144 /* A three-word PLT with no Thumb thunk contains only Arm code,
4e617b1e
PB		 18145 so only need to output a mapping symbol for the first PLT entry and
18146 entries with thumb thunks. */
34e77a92 18147 if (thumb_stub_p || addr == plt_header_size)
4e617b1e 18148 {
7413f23f 18149 if (!elf32_arm_output_map_sym (osi, ARM_MAP_ARM, addr))
4e617b1e
PB		 18150 return FALSE;
18151 }
18152#endif
18153 }
18154
18155 return TRUE;
18156}
18157
34e77a92
RS		 18158/* Output mapping symbols for PLT entries associated with H. */
18159
18160static bfd_boolean
18161elf32_arm_output_plt_map (struct elf_link_hash_entry *h, void *inf)
18162{
18163 output_arch_syminfo *osi = (output_arch_syminfo *) inf;
18164 struct elf32_arm_link_hash_entry *eh;
18165
18166 if (h->root.type == bfd_link_hash_indirect)
18167 return TRUE;
18168
18169 if (h->root.type == bfd_link_hash_warning)
18170 /* When warning symbols are created, they **replace** the "real"
18171 entry in the hash table, thus we never get to see the real
18172 symbol in a hash traversal. So look at it now. */
18173 h = (struct elf_link_hash_entry *) h->root.u.i.link;
18174
18175 eh = (struct elf32_arm_link_hash_entry *) h;
18176 return elf32_arm_output_plt_map_1 (osi, SYMBOL_CALLS_LOCAL (osi->info, h),
18177 &h->plt, &eh->plt);
18178}
18179
4f4faa4d
TP		 18180/* Bind a veneered symbol to its veneer identified by its hash entry
18181 STUB_ENTRY. The veneered location thus loose its symbol. */
18182
18183static void
18184arm_stub_claim_sym (struct elf32_arm_stub_hash_entry *stub_entry)
18185{
18186 struct elf32_arm_link_hash_entry *hash = stub_entry->h;
18187
18188 BFD_ASSERT (hash);
18189 hash->root.root.u.def.section = stub_entry->stub_sec;
18190 hash->root.root.u.def.value = stub_entry->stub_offset;
18191 hash->root.size = stub_entry->stub_size;
18192}
18193
7413f23f
DJ		 18194/* Output a single local symbol for a generated stub. */
18195
18196static bfd_boolean
18197elf32_arm_output_stub_sym (output_arch_syminfo *osi, const char *name,
18198 bfd_vma offset, bfd_vma size)
18199{
7413f23f
DJ		 18200 Elf_Internal_Sym sym;
18201
7413f23f
DJ		 18202 sym.st_value = osi->sec->output_section->vma
18203 + osi->sec->output_offset
18204 + offset;
18205 sym.st_size = size;
18206 sym.st_other = 0;
18207 sym.st_info = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
18208 sym.st_shndx = osi->sec_shndx;
35fc36a8 18209 sym.st_target_internal = 0;
57402f1e 18210 return osi->func (osi->flaginfo, name, &sym, osi->sec, NULL) == 1;
7413f23f 18211}
4e617b1e 18212
da5938a2 18213static bfd_boolean
8029a119
NC		 18214arm_map_one_stub (struct bfd_hash_entry * gen_entry,
18215 void * in_arg)
da5938a2
NC		 18216{
18217 struct elf32_arm_stub_hash_entry *stub_entry;
da5938a2
NC		 18218 asection *stub_sec;
18219 bfd_vma addr;
7413f23f 18220 char *stub_name;
9a008db3 18221 output_arch_syminfo *osi;
d3ce72d0 18222 const insn_sequence *template_sequence;
461a49ca
DJ		 18223 enum stub_insn_type prev_type;
18224 int size;
18225 int i;
18226 enum map_symbol_type sym_type;
da5938a2
NC		 18227
18228 /* Massage our args to the form they really have. */
18229 stub_entry = (struct elf32_arm_stub_hash_entry *) gen_entry;
9a008db3 18230 osi = (output_arch_syminfo *) in_arg;
da5938a2 18231
da5938a2
NC		 18232 stub_sec = stub_entry->stub_sec;
18233
18234 /* Ensure this stub is attached to the current section being
7413f23f 18235 processed. */
da5938a2
NC		 18236 if (stub_sec != osi->sec)
18237 return TRUE;
18238
7413f23f 18239 addr = (bfd_vma) stub_entry->stub_offset;
d3ce72d0 18240 template_sequence = stub_entry->stub_template;
4f4faa4d
TP		 18241
18242 if (arm_stub_sym_claimed (stub_entry->stub_type))
18243 arm_stub_claim_sym (stub_entry);
18244 else
7413f23f 18245 {
4f4faa4d
TP		 18246 stub_name = stub_entry->output_name;
18247 switch (template_sequence[0].type)
18248 {
18249 case ARM_TYPE:
18250 if (!elf32_arm_output_stub_sym (osi, stub_name, addr,
18251 stub_entry->stub_size))
18252 return FALSE;
18253 break;
18254 case THUMB16_TYPE:
18255 case THUMB32_TYPE:
18256 if (!elf32_arm_output_stub_sym (osi, stub_name, addr | 1,
18257 stub_entry->stub_size))
18258 return FALSE;
18259 break;
18260 default:
18261 BFD_FAIL ();
18262 return 0;
18263 }
7413f23f 18264 }
da5938a2 18265
461a49ca
DJ		 18266 prev_type = DATA_TYPE;
18267 size = 0;
18268 for (i = 0; i < stub_entry->stub_template_size; i++)
18269 {
d3ce72d0 18270 switch (template_sequence[i].type)
461a49ca
DJ		 18271 {
18272 case ARM_TYPE:
18273 sym_type = ARM_MAP_ARM;
18274 break;
18275
18276 case THUMB16_TYPE:
48229727 18277 case THUMB32_TYPE:
461a49ca
DJ		 18278 sym_type = ARM_MAP_THUMB;
18279 break;
18280
18281 case DATA_TYPE:
18282 sym_type = ARM_MAP_DATA;
18283 break;
18284
18285 default:
18286 BFD_FAIL ();
4e31c731 18287 return FALSE;
461a49ca
DJ		 18288 }
18289
d3ce72d0 18290 if (template_sequence[i].type != prev_type)
461a49ca 18291 {
d3ce72d0 18292 prev_type = template_sequence[i].type;
461a49ca
DJ		 18293 if (!elf32_arm_output_map_sym (osi, sym_type, addr + size))
18294 return FALSE;
18295 }
18296
d3ce72d0 18297 switch (template_sequence[i].type)
461a49ca
DJ		 18298 {
18299 case ARM_TYPE:
48229727 18300 case THUMB32_TYPE:
461a49ca
DJ		 18301 size += 4;
18302 break;
18303
18304 case THUMB16_TYPE:
18305 size += 2;
18306 break;
18307
18308 case DATA_TYPE:
18309 size += 4;
18310 break;
18311
18312 default:
18313 BFD_FAIL ();
4e31c731 18314 return FALSE;
461a49ca
DJ		 18315 }
18316 }
18317
da5938a2
NC		 18318 return TRUE;
18319}
18320
33811162
DG		 18321/* Output mapping symbols for linker generated sections,
18322 and for those data-only sections that do not have a
18323 $d. */
4e617b1e
PB		 18324
18325static bfd_boolean
18326elf32_arm_output_arch_local_syms (bfd *output_bfd,
906e58ca 18327 struct bfd_link_info *info,
57402f1e 18328 void *flaginfo,
6e0b88f1
AM		 18329 int (*func) (void *, const char *,
18330 Elf_Internal_Sym *,
18331 asection *,
18332 struct elf_link_hash_entry *))
4e617b1e
PB		 18333{
18334 output_arch_syminfo osi;
18335 struct elf32_arm_link_hash_table *htab;
91a5743d
PB		 18336 bfd_vma offset;
18337 bfd_size_type size;
33811162 18338 bfd *input_bfd;
4e617b1e
PB		 18339
18340 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 18341 if (htab == NULL)
18342 return FALSE;
18343
906e58ca 18344 check_use_blx (htab);
91a5743d 18345
57402f1e 18346 osi.flaginfo = flaginfo;
4e617b1e
PB		 18347 osi.info = info;
18348 osi.func = func;
906e58ca 18349
33811162
DG		 18350 /* Add a $d mapping symbol to data-only sections that
18351 don't have any mapping symbol. This may result in (harmless) redundant
18352 mapping symbols. */
18353 for (input_bfd = info->input_bfds;
18354 input_bfd != NULL;
c72f2fb2 18355 input_bfd = input_bfd->link.next)
33811162
DG		 18356 {
18357 if ((input_bfd->flags & (BFD_LINKER_CREATED | HAS_SYMS)) == HAS_SYMS)
18358 for (osi.sec = input_bfd->sections;
18359 osi.sec != NULL;
18360 osi.sec = osi.sec->next)
18361 {
18362 if (osi.sec->output_section != NULL
f7dd8c79
DJ		 18363 && ((osi.sec->output_section->flags & (SEC_ALLOC | SEC_CODE))
18364 != 0)
33811162
DG		 18365 && (osi.sec->flags & (SEC_HAS_CONTENTS | SEC_LINKER_CREATED))
18366 == SEC_HAS_CONTENTS
18367 && get_arm_elf_section_data (osi.sec) != NULL
501abfe0 18368 && get_arm_elf_section_data (osi.sec)->mapcount == 0
7d500b83
CL		 18369 && osi.sec->size > 0
18370 && (osi.sec->flags & SEC_EXCLUDE) == 0)
33811162
DG		 18371 {
18372 osi.sec_shndx = _bfd_elf_section_from_bfd_section
18373 (output_bfd, osi.sec->output_section);
18374 if (osi.sec_shndx != (int)SHN_BAD)
18375 elf32_arm_output_map_sym (&osi, ARM_MAP_DATA, 0);
18376 }
18377 }
18378 }
18379
91a5743d
PB		 18380 /* ARM->Thumb glue. */
18381 if (htab->arm_glue_size > 0)
18382 {
3d4d4302
AM		 18383 osi.sec = bfd_get_linker_section (htab->bfd_of_glue_owner,
18384 ARM2THUMB_GLUE_SECTION_NAME);
91a5743d
PB		 18385
18386 osi.sec_shndx = _bfd_elf_section_from_bfd_section
18387 (output_bfd, osi.sec->output_section);
0e1862bb 18388 if (bfd_link_pic (info) || htab->root.is_relocatable_executable
91a5743d
PB		 18389 || htab->pic_veneer)
18390 size = ARM2THUMB_PIC_GLUE_SIZE;
18391 else if (htab->use_blx)
18392 size = ARM2THUMB_V5_STATIC_GLUE_SIZE;
18393 else
18394 size = ARM2THUMB_STATIC_GLUE_SIZE;
4e617b1e 18395
91a5743d
PB		 18396 for (offset = 0; offset < htab->arm_glue_size; offset += size)
18397 {
7413f23f
DJ		 18398 elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, offset);
18399 elf32_arm_output_map_sym (&osi, ARM_MAP_DATA, offset + size - 4);
91a5743d
PB		 18400 }
18401 }
18402
18403 /* Thumb->ARM glue. */
18404 if (htab->thumb_glue_size > 0)
18405 {
3d4d4302
AM		 18406 osi.sec = bfd_get_linker_section (htab->bfd_of_glue_owner,
18407 THUMB2ARM_GLUE_SECTION_NAME);
91a5743d
PB		 18408
18409 osi.sec_shndx = _bfd_elf_section_from_bfd_section
18410 (output_bfd, osi.sec->output_section);
18411 size = THUMB2ARM_GLUE_SIZE;
18412
18413 for (offset = 0; offset < htab->thumb_glue_size; offset += size)
18414 {
7413f23f
DJ		 18415 elf32_arm_output_map_sym (&osi, ARM_MAP_THUMB, offset);
18416 elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, offset + 4);
91a5743d
PB		 18417 }
18418 }
18419
845b51d6
PB		 18420 /* ARMv4 BX veneers. */
18421 if (htab->bx_glue_size > 0)
18422 {
3d4d4302
AM		 18423 osi.sec = bfd_get_linker_section (htab->bfd_of_glue_owner,
18424 ARM_BX_GLUE_SECTION_NAME);
845b51d6
PB		 18425
18426 osi.sec_shndx = _bfd_elf_section_from_bfd_section
18427 (output_bfd, osi.sec->output_section);
18428
7413f23f 18429 elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, 0);
845b51d6
PB		 18430 }
18431
8029a119
NC		 18432 /* Long calls stubs. */
18433 if (htab->stub_bfd && htab->stub_bfd->sections)
18434 {
da5938a2 18435 asection* stub_sec;
8029a119 18436
da5938a2
NC		 18437 for (stub_sec = htab->stub_bfd->sections;
18438 stub_sec != NULL;
8029a119
NC		 18439 stub_sec = stub_sec->next)
18440 {
18441 /* Ignore non-stub sections. */
18442 if (!strstr (stub_sec->name, STUB_SUFFIX))
18443 continue;
da5938a2 18444
8029a119 18445 osi.sec = stub_sec;
da5938a2 18446
8029a119
NC		 18447 osi.sec_shndx = _bfd_elf_section_from_bfd_section
18448 (output_bfd, osi.sec->output_section);
da5938a2 18449
8029a119
NC		 18450 bfd_hash_traverse (&htab->stub_hash_table, arm_map_one_stub, &osi);
18451 }
18452 }
da5938a2 18453
91a5743d 18454 /* Finally, output mapping symbols for the PLT. */
34e77a92 18455 if (htab->root.splt && htab->root.splt->size > 0)
4e617b1e 18456 {
34e77a92
RS		 18457 osi.sec = htab->root.splt;
18458 osi.sec_shndx = (_bfd_elf_section_from_bfd_section
18459 (output_bfd, osi.sec->output_section));
18460
18461 /* Output mapping symbols for the plt header. SymbianOS does not have a
18462 plt header. */
18463 if (htab->vxworks_p)
18464 {
18465 /* VxWorks shared libraries have no PLT header. */
0e1862bb 18466 if (!bfd_link_pic (info))
34e77a92
RS		 18467 {
18468 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, 0))
18469 return FALSE;
18470 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_DATA, 12))
18471 return FALSE;
18472 }
18473 }
b38cadfb
NC		 18474 else if (htab->nacl_p)
18475 {
18476 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, 0))
18477 return FALSE;
18478 }
59029f57 18479 else if (using_thumb_only (htab) && !htab->fdpic_p)
eed94f8f
NC		 18480 {
18481 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_THUMB, 0))
18482 return FALSE;
18483 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_DATA, 12))
18484 return FALSE;
18485 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_THUMB, 16))
18486 return FALSE;
18487 }
e8b09b87 18488 else if (!htab->symbian_p && !htab->fdpic_p)
4e617b1e 18489 {
7413f23f 18490 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, 0))
4e617b1e 18491 return FALSE;
34e77a92
RS		 18492#ifndef FOUR_WORD_PLT
18493 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_DATA, 16))
4e617b1e 18494 return FALSE;
34e77a92 18495#endif
4e617b1e
PB		 18496 }
18497 }
99059e56
RM		 18498 if (htab->nacl_p && htab->root.iplt && htab->root.iplt->size > 0)
18499 {
18500 /* NaCl uses a special first entry in .iplt too. */
18501 osi.sec = htab->root.iplt;
18502 osi.sec_shndx = (_bfd_elf_section_from_bfd_section
18503 (output_bfd, osi.sec->output_section));
18504 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, 0))
18505 return FALSE;
18506 }
34e77a92
RS		 18507 if ((htab->root.splt && htab->root.splt->size > 0)
18508 || (htab->root.iplt && htab->root.iplt->size > 0))
4e617b1e 18509 {
34e77a92
RS		 18510 elf_link_hash_traverse (&htab->root, elf32_arm_output_plt_map, &osi);
18511 for (input_bfd = info->input_bfds;
18512 input_bfd != NULL;
c72f2fb2 18513 input_bfd = input_bfd->link.next)
34e77a92
RS		 18514 {
18515 struct arm_local_iplt_info **local_iplt;
18516 unsigned int i, num_syms;
4e617b1e 18517
34e77a92
RS		 18518 local_iplt = elf32_arm_local_iplt (input_bfd);
18519 if (local_iplt != NULL)
18520 {
18521 num_syms = elf_symtab_hdr (input_bfd).sh_info;
18522 for (i = 0; i < num_syms; i++)
18523 if (local_iplt[i] != NULL
18524 && !elf32_arm_output_plt_map_1 (&osi, TRUE,
18525 &local_iplt[i]->root,
18526 &local_iplt[i]->arm))
18527 return FALSE;
18528 }
18529 }
18530 }
0855e32b
NS		 18531 if (htab->dt_tlsdesc_plt != 0)
18532 {
18533 /* Mapping symbols for the lazy tls trampoline. */
18534 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, htab->dt_tlsdesc_plt))
18535 return FALSE;
b38cadfb 18536
0855e32b
NS		 18537 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_DATA,
18538 htab->dt_tlsdesc_plt + 24))
18539 return FALSE;
18540 }
18541 if (htab->tls_trampoline != 0)
18542 {
18543 /* Mapping symbols for the tls trampoline. */
18544 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, htab->tls_trampoline))
18545 return FALSE;
18546#ifdef FOUR_WORD_PLT
18547 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_DATA,
18548 htab->tls_trampoline + 12))
18549 return FALSE;
b38cadfb 18550#endif
0855e32b 18551 }
b38cadfb 18552
4e617b1e
PB		 18553 return TRUE;
18554}
18555
54ddd295
TP		 18556/* Filter normal symbols of CMSE entry functions of ABFD to include in
18557 the import library. All SYMCOUNT symbols of ABFD can be examined
18558 from their pointers in SYMS. Pointers of symbols to keep should be
18559 stored continuously at the beginning of that array.
18560
18561 Returns the number of symbols to keep. */
18562
18563static unsigned int
18564elf32_arm_filter_cmse_symbols (bfd *abfd ATTRIBUTE_UNUSED,
18565 struct bfd_link_info *info,
18566 asymbol **syms, long symcount)
18567{
18568 size_t maxnamelen;
18569 char *cmse_name;
18570 long src_count, dst_count = 0;
18571 struct elf32_arm_link_hash_table *htab;
18572
18573 htab = elf32_arm_hash_table (info);
18574 if (!htab->stub_bfd || !htab->stub_bfd->sections)
18575 symcount = 0;
18576
18577 maxnamelen = 128;
18578 cmse_name = (char *) bfd_malloc (maxnamelen);
18579 for (src_count = 0; src_count < symcount; src_count++)
18580 {
18581 struct elf32_arm_link_hash_entry *cmse_hash;
18582 asymbol *sym;
18583 flagword flags;
18584 char *name;
18585 size_t namelen;
18586
18587 sym = syms[src_count];
18588 flags = sym->flags;
18589 name = (char *) bfd_asymbol_name (sym);
18590
18591 if ((flags & BSF_FUNCTION) != BSF_FUNCTION)
18592 continue;
18593 if (!(flags & (BSF_GLOBAL | BSF_WEAK)))
18594 continue;
18595
18596 namelen = strlen (name) + sizeof (CMSE_PREFIX) + 1;
18597 if (namelen > maxnamelen)
18598 {
18599 cmse_name = (char *)
18600 bfd_realloc (cmse_name, namelen);
18601 maxnamelen = namelen;
18602 }
18603 snprintf (cmse_name, maxnamelen, "%s%s", CMSE_PREFIX, name);
18604 cmse_hash = (struct elf32_arm_link_hash_entry *)
18605 elf_link_hash_lookup (&(htab)->root, cmse_name, FALSE, FALSE, TRUE);
18606
18607 if (!cmse_hash
18608 || (cmse_hash->root.root.type != bfd_link_hash_defined
18609 && cmse_hash->root.root.type != bfd_link_hash_defweak)
18610 || cmse_hash->root.type != STT_FUNC)
18611 continue;
18612
54ddd295
TP		 18613 syms[dst_count++] = sym;
18614 }
18615 free (cmse_name);
18616
18617 syms[dst_count] = NULL;
18618
18619 return dst_count;
18620}
18621
18622/* Filter symbols of ABFD to include in the import library. All
18623 SYMCOUNT symbols of ABFD can be examined from their pointers in
18624 SYMS. Pointers of symbols to keep should be stored continuously at
18625 the beginning of that array.
18626
18627 Returns the number of symbols to keep. */
18628
18629static unsigned int
18630elf32_arm_filter_implib_symbols (bfd *abfd ATTRIBUTE_UNUSED,
18631 struct bfd_link_info *info,
18632 asymbol **syms, long symcount)
18633{
18634 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (info);
18635
046734ff
TP		 18636 /* Requirement 8 of "ARM v8-M Security Extensions: Requirements on
18637 Development Tools" (ARM-ECM-0359818) mandates Secure Gateway import
18638 library to be a relocatable object file. */
18639 BFD_ASSERT (!(bfd_get_file_flags (info->out_implib_bfd) & EXEC_P));
54ddd295
TP		 18640 if (globals->cmse_implib)
18641 return elf32_arm_filter_cmse_symbols (abfd, info, syms, symcount);
18642 else
18643 return _bfd_elf_filter_global_symbols (abfd, info, syms, symcount);
18644}
18645
e489d0ae
PB		 18646/* Allocate target specific section data. */
18647
18648static bfd_boolean
18649elf32_arm_new_section_hook (bfd *abfd, asection *sec)
18650{
f592407e
AM		 18651 if (!sec->used_by_bfd)
18652 {
18653 _arm_elf_section_data *sdata;
18654 bfd_size_type amt = sizeof (*sdata);
e489d0ae 18655
21d799b5 18656 sdata = (_arm_elf_section_data *) bfd_zalloc (abfd, amt);
f592407e
AM		 18657 if (sdata == NULL)
18658 return FALSE;
18659 sec->used_by_bfd = sdata;
18660 }
e489d0ae
PB		 18661
18662 return _bfd_elf_new_section_hook (abfd, sec);
18663}
18664
18665
18666/* Used to order a list of mapping symbols by address. */
18667
18668static int
18669elf32_arm_compare_mapping (const void * a, const void * b)
18670{
7f6a71ff
JM		 18671 const elf32_arm_section_map *amap = (const elf32_arm_section_map *) a;
18672 const elf32_arm_section_map *bmap = (const elf32_arm_section_map *) b;
18673
18674 if (amap->vma > bmap->vma)
18675 return 1;
18676 else if (amap->vma < bmap->vma)
18677 return -1;
18678 else if (amap->type > bmap->type)
18679 /* Ensure results do not depend on the host qsort for objects with
18680 multiple mapping symbols at the same address by sorting on type
18681 after vma. */
18682 return 1;
18683 else if (amap->type < bmap->type)
18684 return -1;
18685 else
18686 return 0;
e489d0ae
PB		 18687}
18688
2468f9c9
PB		 18689/* Add OFFSET to lower 31 bits of ADDR, leaving other bits unmodified. */
18690
18691static unsigned long
18692offset_prel31 (unsigned long addr, bfd_vma offset)
18693{
18694 return (addr & ~0x7ffffffful) | ((addr + offset) & 0x7ffffffful);
18695}
18696
18697/* Copy an .ARM.exidx table entry, adding OFFSET to (applied) PREL31
18698 relocations. */
18699
18700static void
18701copy_exidx_entry (bfd *output_bfd, bfd_byte *to, bfd_byte *from, bfd_vma offset)
18702{
18703 unsigned long first_word = bfd_get_32 (output_bfd, from);
18704 unsigned long second_word = bfd_get_32 (output_bfd, from + 4);
b38cadfb 18705
2468f9c9
PB		 18706 /* High bit of first word is supposed to be zero. */
18707 if ((first_word & 0x80000000ul) == 0)
18708 first_word = offset_prel31 (first_word, offset);
b38cadfb 18709
2468f9c9
PB		 18710 /* If the high bit of the first word is clear, and the bit pattern is not 0x1
18711 (EXIDX_CANTUNWIND), this is an offset to an .ARM.extab entry. */
18712 if ((second_word != 0x1) && ((second_word & 0x80000000ul) == 0))
18713 second_word = offset_prel31 (second_word, offset);
b38cadfb 18714
2468f9c9
PB		 18715 bfd_put_32 (output_bfd, first_word, to);
18716 bfd_put_32 (output_bfd, second_word, to + 4);
18717}
e489d0ae 18718
48229727
JB		 18719/* Data for make_branch_to_a8_stub(). */
18720
b38cadfb
NC		 18721struct a8_branch_to_stub_data
18722{
48229727
JB		 18723 asection *writing_section;
18724 bfd_byte *contents;
18725};
18726
18727
18728/* Helper to insert branches to Cortex-A8 erratum stubs in the right
18729 places for a particular section. */
18730
18731static bfd_boolean
18732make_branch_to_a8_stub (struct bfd_hash_entry *gen_entry,
99059e56 18733 void *in_arg)
48229727
JB		 18734{
18735 struct elf32_arm_stub_hash_entry *stub_entry;
18736 struct a8_branch_to_stub_data *data;
18737 bfd_byte *contents;
18738 unsigned long branch_insn;
18739 bfd_vma veneered_insn_loc, veneer_entry_loc;
18740 bfd_signed_vma branch_offset;
18741 bfd *abfd;
8d9d9490 18742 unsigned int loc;
48229727
JB		 18743
18744 stub_entry = (struct elf32_arm_stub_hash_entry *) gen_entry;
18745 data = (struct a8_branch_to_stub_data *) in_arg;
18746
18747 if (stub_entry->target_section != data->writing_section
4563a860 18748 || stub_entry->stub_type < arm_stub_a8_veneer_lwm)
48229727
JB		 18749 return TRUE;
18750
18751 contents = data->contents;
18752
8d9d9490
TP		 18753 /* We use target_section as Cortex-A8 erratum workaround stubs are only
18754 generated when both source and target are in the same section. */
48229727
JB		 18755 veneered_insn_loc = stub_entry->target_section->output_section->vma
18756 + stub_entry->target_section->output_offset
8d9d9490 18757 + stub_entry->source_value;
48229727
JB		 18758
18759 veneer_entry_loc = stub_entry->stub_sec->output_section->vma
18760 + stub_entry->stub_sec->output_offset
18761 + stub_entry->stub_offset;
18762
18763 if (stub_entry->stub_type == arm_stub_a8_veneer_blx)
18764 veneered_insn_loc &= ~3u;
18765
18766 branch_offset = veneer_entry_loc - veneered_insn_loc - 4;
18767
18768 abfd = stub_entry->target_section->owner;
8d9d9490 18769 loc = stub_entry->source_value;
48229727
JB		 18770
18771 /* We attempt to avoid this condition by setting stubs_always_after_branch
18772 in elf32_arm_size_stubs if we've enabled the Cortex-A8 erratum workaround.
18773 This check is just to be on the safe side... */
18774 if ((veneered_insn_loc & ~0xfff) == (veneer_entry_loc & ~0xfff))
18775 {
871b3ab2 18776 _bfd_error_handler (_("%pB: error: Cortex-A8 erratum stub is "
4eca0228 18777 "allocated in unsafe location"), abfd);
48229727
JB		 18778 return FALSE;
18779 }
18780
18781 switch (stub_entry->stub_type)
18782 {
18783 case arm_stub_a8_veneer_b:
18784 case arm_stub_a8_veneer_b_cond:
18785 branch_insn = 0xf0009000;
18786 goto jump24;
18787
18788 case arm_stub_a8_veneer_blx:
18789 branch_insn = 0xf000e800;
18790 goto jump24;
18791
18792 case arm_stub_a8_veneer_bl:
18793 {
18794 unsigned int i1, j1, i2, j2, s;
18795
18796 branch_insn = 0xf000d000;
18797
18798 jump24:
18799 if (branch_offset < -16777216 || branch_offset > 16777214)
18800 {
18801 /* There's not much we can do apart from complain if this
18802 happens. */
871b3ab2 18803 _bfd_error_handler (_("%pB: error: Cortex-A8 erratum stub out "
4eca0228 18804 "of range (input file too large)"), abfd);
48229727
JB		 18805 return FALSE;
18806 }
18807
18808 /* i1 = not(j1 eor s), so:
18809 not i1 = j1 eor s
18810 j1 = (not i1) eor s. */
18811
18812 branch_insn |= (branch_offset >> 1) & 0x7ff;
18813 branch_insn |= ((branch_offset >> 12) & 0x3ff) << 16;
18814 i2 = (branch_offset >> 22) & 1;
18815 i1 = (branch_offset >> 23) & 1;
18816 s = (branch_offset >> 24) & 1;
18817 j1 = (!i1) ^ s;
18818 j2 = (!i2) ^ s;
18819 branch_insn |= j2 << 11;
18820 branch_insn |= j1 << 13;
18821 branch_insn |= s << 26;
18822 }
18823 break;
18824
18825 default:
18826 BFD_FAIL ();
18827 return FALSE;
18828 }
18829
8d9d9490
TP		 18830 bfd_put_16 (abfd, (branch_insn >> 16) & 0xffff, &contents[loc]);
18831 bfd_put_16 (abfd, branch_insn & 0xffff, &contents[loc + 2]);
48229727
JB		 18832
18833 return TRUE;
18834}
18835
a504d23a
LA		 18836/* Beginning of stm32l4xx work-around. */
18837
18838/* Functions encoding instructions necessary for the emission of the
18839 fix-stm32l4xx-629360.
18840 Encoding is extracted from the
18841 ARM (C) Architecture Reference Manual
18842 ARMv7-A and ARMv7-R edition
18843 ARM DDI 0406C.b (ID072512). */
18844
18845static inline bfd_vma
82188b29 18846create_instruction_branch_absolute (int branch_offset)
a504d23a
LA		 18847{
18848 /* A8.8.18 B (A8-334)
18849 B target_address (Encoding T4). */
18850 /* 1111 - 0Sii - iiii - iiii - 10J1 - Jiii - iiii - iiii. */
18851 /* jump offset is: S:I1:I2:imm10:imm11:0. */
18852 /* with : I1 = NOT (J1 EOR S) I2 = NOT (J2 EOR S). */
18853
a504d23a
LA		 18854 int s = ((branch_offset & 0x1000000) >> 24);
18855 int j1 = s ^ !((branch_offset & 0x800000) >> 23);
18856 int j2 = s ^ !((branch_offset & 0x400000) >> 22);
18857
18858 if (branch_offset < -(1 << 24) || branch_offset >= (1 << 24))
18859 BFD_ASSERT (0 && "Error: branch out of range. Cannot create branch.");
18860
18861 bfd_vma patched_inst = 0xf0009000
18862 | s << 26 /* S. */
18863 | (((unsigned long) (branch_offset) >> 12) & 0x3ff) << 16 /* imm10. */
18864 | j1 << 13 /* J1. */
18865 | j2 << 11 /* J2. */
18866 | (((unsigned long) (branch_offset) >> 1) & 0x7ff); /* imm11. */
18867
18868 return patched_inst;
18869}
18870
18871static inline bfd_vma
18872create_instruction_ldmia (int base_reg, int wback, int reg_mask)
18873{
18874 /* A8.8.57 LDM/LDMIA/LDMFD (A8-396)
18875 LDMIA Rn!, {Ra, Rb, Rc, ...} (Encoding T2). */
18876 bfd_vma patched_inst = 0xe8900000
18877 | (/*W=*/wback << 21)
18878 | (base_reg << 16)
18879 | (reg_mask & 0x0000ffff);
18880
18881 return patched_inst;
18882}
18883
18884static inline bfd_vma
18885create_instruction_ldmdb (int base_reg, int wback, int reg_mask)
18886{
18887 /* A8.8.60 LDMDB/LDMEA (A8-402)
18888 LDMDB Rn!, {Ra, Rb, Rc, ...} (Encoding T1). */
18889 bfd_vma patched_inst = 0xe9100000
18890 | (/*W=*/wback << 21)
18891 | (base_reg << 16)
18892 | (reg_mask & 0x0000ffff);
18893
18894 return patched_inst;
18895}
18896
18897static inline bfd_vma
18898create_instruction_mov (int target_reg, int source_reg)
18899{
18900 /* A8.8.103 MOV (register) (A8-486)
18901 MOV Rd, Rm (Encoding T1). */
18902 bfd_vma patched_inst = 0x4600
18903 | (target_reg & 0x7)
18904 | ((target_reg & 0x8) >> 3) << 7
18905 | (source_reg << 3);
18906
18907 return patched_inst;
18908}
18909
18910static inline bfd_vma
18911create_instruction_sub (int target_reg, int source_reg, int value)
18912{
18913 /* A8.8.221 SUB (immediate) (A8-708)
18914 SUB Rd, Rn, #value (Encoding T3). */
18915 bfd_vma patched_inst = 0xf1a00000
18916 | (target_reg << 8)
18917 | (source_reg << 16)
18918 | (/*S=*/0 << 20)
18919 | ((value & 0x800) >> 11) << 26
18920 | ((value & 0x700) >> 8) << 12
18921 | (value & 0x0ff);
18922
18923 return patched_inst;
18924}
18925
18926static inline bfd_vma
9239bbd3 18927create_instruction_vldmia (int base_reg, int is_dp, int wback, int num_words,
a504d23a
LA		 18928 int first_reg)
18929{
18930 /* A8.8.332 VLDM (A8-922)
9239bbd3
CM		 18931 VLMD{MODE} Rn{!}, {list} (Encoding T1 or T2). */
18932 bfd_vma patched_inst = (is_dp ? 0xec900b00 : 0xec900a00)
a504d23a
LA		 18933 | (/*W=*/wback << 21)
18934 | (base_reg << 16)
9239bbd3
CM		 18935 | (num_words & 0x000000ff)
18936 | (((unsigned)first_reg >> 1) & 0x0000000f) << 12
a504d23a
LA		 18937 | (first_reg & 0x00000001) << 22;
18938
18939 return patched_inst;
18940}
18941
18942static inline bfd_vma
9239bbd3
CM		 18943create_instruction_vldmdb (int base_reg, int is_dp, int num_words,
18944 int first_reg)
a504d23a
LA		 18945{
18946 /* A8.8.332 VLDM (A8-922)
9239bbd3
CM		 18947 VLMD{MODE} Rn!, {} (Encoding T1 or T2). */
18948 bfd_vma patched_inst = (is_dp ? 0xed300b00 : 0xed300a00)
a504d23a 18949 | (base_reg << 16)
9239bbd3
CM		 18950 | (num_words & 0x000000ff)
18951 | (((unsigned)first_reg >>1 ) & 0x0000000f) << 12
a504d23a
LA		 18952 | (first_reg & 0x00000001) << 22;
18953
18954 return patched_inst;
18955}
18956
18957static inline bfd_vma
18958create_instruction_udf_w (int value)
18959{
18960 /* A8.8.247 UDF (A8-758)
18961 Undefined (Encoding T2). */
18962 bfd_vma patched_inst = 0xf7f0a000
18963 | (value & 0x00000fff)
18964 | (value & 0x000f0000) << 16;
18965
18966 return patched_inst;
18967}
18968
18969static inline bfd_vma
18970create_instruction_udf (int value)
18971{
18972 /* A8.8.247 UDF (A8-758)
18973 Undefined (Encoding T1). */
18974 bfd_vma patched_inst = 0xde00
18975 | (value & 0xff);
18976
18977 return patched_inst;
18978}
18979
18980/* Functions writing an instruction in memory, returning the next
18981 memory position to write to. */
18982
18983static inline bfd_byte *
18984push_thumb2_insn32 (struct elf32_arm_link_hash_table * htab,
18985 bfd * output_bfd, bfd_byte *pt, insn32 insn)
18986{
18987 put_thumb2_insn (htab, output_bfd, insn, pt);
18988 return pt + 4;
18989}
18990
18991static inline bfd_byte *
18992push_thumb2_insn16 (struct elf32_arm_link_hash_table * htab,
18993 bfd * output_bfd, bfd_byte *pt, insn32 insn)
18994{
18995 put_thumb_insn (htab, output_bfd, insn, pt);
18996 return pt + 2;
18997}
18998
18999/* Function filling up a region in memory with T1 and T2 UDFs taking
19000 care of alignment. */
19001
19002static bfd_byte *
19003stm32l4xx_fill_stub_udf (struct elf32_arm_link_hash_table * htab,
07d6d2b8
AM		 19004 bfd * output_bfd,
19005 const bfd_byte * const base_stub_contents,
19006 bfd_byte * const from_stub_contents,
19007 const bfd_byte * const end_stub_contents)
a504d23a
LA		 19008{
19009 bfd_byte *current_stub_contents = from_stub_contents;
19010
19011 /* Fill the remaining of the stub with deterministic contents : UDF
19012 instructions.
19013 Check if realignment is needed on modulo 4 frontier using T1, to
19014 further use T2. */
19015 if ((current_stub_contents < end_stub_contents)
19016 && !((current_stub_contents - base_stub_contents) % 2)
19017 && ((current_stub_contents - base_stub_contents) % 4))
19018 current_stub_contents =
19019 push_thumb2_insn16 (htab, output_bfd, current_stub_contents,
19020 create_instruction_udf (0));
19021
19022 for (; current_stub_contents < end_stub_contents;)
19023 current_stub_contents =
19024 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19025 create_instruction_udf_w (0));
19026
19027 return current_stub_contents;
19028}
19029
19030/* Functions writing the stream of instructions equivalent to the
19031 derived sequence for ldmia, ldmdb, vldm respectively. */
19032
19033static void
19034stm32l4xx_create_replacing_stub_ldmia (struct elf32_arm_link_hash_table * htab,
19035 bfd * output_bfd,
19036 const insn32 initial_insn,
19037 const bfd_byte *const initial_insn_addr,
19038 bfd_byte *const base_stub_contents)
19039{
19040 int wback = (initial_insn & 0x00200000) >> 21;
19041 int ri, rn = (initial_insn & 0x000F0000) >> 16;
19042 int insn_all_registers = initial_insn & 0x0000ffff;
19043 int insn_low_registers, insn_high_registers;
19044 int usable_register_mask;
b25e998d 19045 int nb_registers = elf32_arm_popcount (insn_all_registers);
a504d23a
LA		 19046 int restore_pc = (insn_all_registers & (1 << 15)) ? 1 : 0;
19047 int restore_rn = (insn_all_registers & (1 << rn)) ? 1 : 0;
19048 bfd_byte *current_stub_contents = base_stub_contents;
19049
19050 BFD_ASSERT (is_thumb2_ldmia (initial_insn));
19051
19052 /* In BFD_ARM_STM32L4XX_FIX_ALL mode we may have to deal with
19053 smaller than 8 registers load sequences that do not cause the
19054 hardware issue. */
19055 if (nb_registers <= 8)
19056 {
19057 /* UNTOUCHED : LDMIA Rn{!}, {R-all-register-list}. */
19058 current_stub_contents =
19059 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19060 initial_insn);
19061
19062 /* B initial_insn_addr+4. */
19063 if (!restore_pc)
19064 current_stub_contents =
19065 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19066 create_instruction_branch_absolute
82188b29 19067 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 19068
19069 /* Fill the remaining of the stub with deterministic contents. */
19070 current_stub_contents =
19071 stm32l4xx_fill_stub_udf (htab, output_bfd,
19072 base_stub_contents, current_stub_contents,
19073 base_stub_contents +
19074 STM32L4XX_ERRATUM_LDM_VENEER_SIZE);
19075
19076 return;
19077 }
19078
19079 /* - reg_list[13] == 0. */
19080 BFD_ASSERT ((insn_all_registers & (1 << 13))==0);
19081
19082 /* - reg_list[14] & reg_list[15] != 1. */
19083 BFD_ASSERT ((insn_all_registers & 0xC000) != 0xC000);
19084
19085 /* - if (wback==1) reg_list[rn] == 0. */
19086 BFD_ASSERT (!wback || !restore_rn);
19087
19088 /* - nb_registers > 8. */
b25e998d 19089 BFD_ASSERT (elf32_arm_popcount (insn_all_registers) > 8);
a504d23a
LA		 19090
19091 /* At this point, LDMxx initial insn loads between 9 and 14 registers. */
19092
19093 /* In the following algorithm, we split this wide LDM using 2 LDM insns:
19094 - One with the 7 lowest registers (register mask 0x007F)
19095 This LDM will finally contain between 2 and 7 registers
19096 - One with the 7 highest registers (register mask 0xDF80)
19097 This ldm will finally contain between 2 and 7 registers. */
19098 insn_low_registers = insn_all_registers & 0x007F;
19099 insn_high_registers = insn_all_registers & 0xDF80;
19100
19101 /* A spare register may be needed during this veneer to temporarily
19102 handle the base register. This register will be restored with the
19103 last LDM operation.
19104 The usable register may be any general purpose register (that
19105 excludes PC, SP, LR : register mask is 0x1FFF). */
19106 usable_register_mask = 0x1FFF;
19107
19108 /* Generate the stub function. */
19109 if (wback)
19110 {
19111 /* LDMIA Rn!, {R-low-register-list} : (Encoding T2). */
19112 current_stub_contents =
19113 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19114 create_instruction_ldmia
19115 (rn, /*wback=*/1, insn_low_registers));
19116
19117 /* LDMIA Rn!, {R-high-register-list} : (Encoding T2). */
19118 current_stub_contents =
19119 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19120 create_instruction_ldmia
19121 (rn, /*wback=*/1, insn_high_registers));
19122 if (!restore_pc)
19123 {
19124 /* B initial_insn_addr+4. */
19125 current_stub_contents =
19126 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19127 create_instruction_branch_absolute
82188b29 19128 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 19129 }
19130 }
19131 else /* if (!wback). */
19132 {
19133 ri = rn;
19134
19135 /* If Rn is not part of the high-register-list, move it there. */
19136 if (!(insn_high_registers & (1 << rn)))
19137 {
19138 /* Choose a Ri in the high-register-list that will be restored. */
19139 ri = ctz (insn_high_registers & usable_register_mask & ~(1 << rn));
19140
19141 /* MOV Ri, Rn. */
19142 current_stub_contents =
19143 push_thumb2_insn16 (htab, output_bfd, current_stub_contents,
19144 create_instruction_mov (ri, rn));
19145 }
19146
19147 /* LDMIA Ri!, {R-low-register-list} : (Encoding T2). */
19148 current_stub_contents =
19149 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19150 create_instruction_ldmia
19151 (ri, /*wback=*/1, insn_low_registers));
19152
19153 /* LDMIA Ri, {R-high-register-list} : (Encoding T2). */
19154 current_stub_contents =
19155 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19156 create_instruction_ldmia
19157 (ri, /*wback=*/0, insn_high_registers));
19158
19159 if (!restore_pc)
19160 {
19161 /* B initial_insn_addr+4. */
19162 current_stub_contents =
19163 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19164 create_instruction_branch_absolute
82188b29 19165 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 19166 }
19167 }
19168
19169 /* Fill the remaining of the stub with deterministic contents. */
19170 current_stub_contents =
19171 stm32l4xx_fill_stub_udf (htab, output_bfd,
19172 base_stub_contents, current_stub_contents,
19173 base_stub_contents +
19174 STM32L4XX_ERRATUM_LDM_VENEER_SIZE);
19175}
19176
19177static void
19178stm32l4xx_create_replacing_stub_ldmdb (struct elf32_arm_link_hash_table * htab,
19179 bfd * output_bfd,
19180 const insn32 initial_insn,
19181 const bfd_byte *const initial_insn_addr,
19182 bfd_byte *const base_stub_contents)
19183{
19184 int wback = (initial_insn & 0x00200000) >> 21;
19185 int ri, rn = (initial_insn & 0x000f0000) >> 16;
19186 int insn_all_registers = initial_insn & 0x0000ffff;
19187 int insn_low_registers, insn_high_registers;
19188 int usable_register_mask;
19189 int restore_pc = (insn_all_registers & (1 << 15)) ? 1 : 0;
19190 int restore_rn = (insn_all_registers & (1 << rn)) ? 1 : 0;
b25e998d 19191 int nb_registers = elf32_arm_popcount (insn_all_registers);
a504d23a
LA		 19192 bfd_byte *current_stub_contents = base_stub_contents;
19193
19194 BFD_ASSERT (is_thumb2_ldmdb (initial_insn));
19195
19196 /* In BFD_ARM_STM32L4XX_FIX_ALL mode we may have to deal with
19197 smaller than 8 registers load sequences that do not cause the
19198 hardware issue. */
19199 if (nb_registers <= 8)
19200 {
19201 /* UNTOUCHED : LDMIA Rn{!}, {R-all-register-list}. */
19202 current_stub_contents =
19203 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19204 initial_insn);
19205
19206 /* B initial_insn_addr+4. */
19207 current_stub_contents =
19208 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19209 create_instruction_branch_absolute
82188b29 19210 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 19211
19212 /* Fill the remaining of the stub with deterministic contents. */
19213 current_stub_contents =
19214 stm32l4xx_fill_stub_udf (htab, output_bfd,
19215 base_stub_contents, current_stub_contents,
19216 base_stub_contents +
19217 STM32L4XX_ERRATUM_LDM_VENEER_SIZE);
19218
19219 return;
19220 }
19221
19222 /* - reg_list[13] == 0. */
19223 BFD_ASSERT ((insn_all_registers & (1 << 13)) == 0);
19224
19225 /* - reg_list[14] & reg_list[15] != 1. */
19226 BFD_ASSERT ((insn_all_registers & 0xC000) != 0xC000);
19227
19228 /* - if (wback==1) reg_list[rn] == 0. */
19229 BFD_ASSERT (!wback || !restore_rn);
19230
19231 /* - nb_registers > 8. */
b25e998d 19232 BFD_ASSERT (elf32_arm_popcount (insn_all_registers) > 8);
a504d23a
LA		 19233
19234 /* At this point, LDMxx initial insn loads between 9 and 14 registers. */
19235
19236 /* In the following algorithm, we split this wide LDM using 2 LDM insn:
19237 - One with the 7 lowest registers (register mask 0x007F)
19238 This LDM will finally contain between 2 and 7 registers
19239 - One with the 7 highest registers (register mask 0xDF80)
19240 This ldm will finally contain between 2 and 7 registers. */
19241 insn_low_registers = insn_all_registers & 0x007F;
19242 insn_high_registers = insn_all_registers & 0xDF80;
19243
19244 /* A spare register may be needed during this veneer to temporarily
19245 handle the base register. This register will be restored with
19246 the last LDM operation.
19247 The usable register may be any general purpose register (that excludes
19248 PC, SP, LR : register mask is 0x1FFF). */
19249 usable_register_mask = 0x1FFF;
19250
19251 /* Generate the stub function. */
19252 if (!wback && !restore_pc && !restore_rn)
19253 {
19254 /* Choose a Ri in the low-register-list that will be restored. */
19255 ri = ctz (insn_low_registers & usable_register_mask & ~(1 << rn));
19256
19257 /* MOV Ri, Rn. */
19258 current_stub_contents =
19259 push_thumb2_insn16 (htab, output_bfd, current_stub_contents,
19260 create_instruction_mov (ri, rn));
19261
19262 /* LDMDB Ri!, {R-high-register-list}. */
19263 current_stub_contents =
19264 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19265 create_instruction_ldmdb
19266 (ri, /*wback=*/1, insn_high_registers));
19267
19268 /* LDMDB Ri, {R-low-register-list}. */
19269 current_stub_contents =
19270 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19271 create_instruction_ldmdb
19272 (ri, /*wback=*/0, insn_low_registers));
19273
19274 /* B initial_insn_addr+4. */
19275 current_stub_contents =
19276 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19277 create_instruction_branch_absolute
82188b29 19278 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 19279 }
19280 else if (wback && !restore_pc && !restore_rn)
19281 {
19282 /* LDMDB Rn!, {R-high-register-list}. */
19283 current_stub_contents =
19284 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19285 create_instruction_ldmdb
19286 (rn, /*wback=*/1, insn_high_registers));
19287
19288 /* LDMDB Rn!, {R-low-register-list}. */
19289 current_stub_contents =
19290 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19291 create_instruction_ldmdb
19292 (rn, /*wback=*/1, insn_low_registers));
19293
19294 /* B initial_insn_addr+4. */
19295 current_stub_contents =
19296 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19297 create_instruction_branch_absolute
82188b29 19298 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 19299 }
19300 else if (!wback && restore_pc && !restore_rn)
19301 {
19302 /* Choose a Ri in the high-register-list that will be restored. */
19303 ri = ctz (insn_high_registers & usable_register_mask & ~(1 << rn));
19304
19305 /* SUB Ri, Rn, #(4*nb_registers). */
19306 current_stub_contents =
19307 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19308 create_instruction_sub (ri, rn, (4 * nb_registers)));
19309
19310 /* LDMIA Ri!, {R-low-register-list}. */
19311 current_stub_contents =
19312 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19313 create_instruction_ldmia
19314 (ri, /*wback=*/1, insn_low_registers));
19315
19316 /* LDMIA Ri, {R-high-register-list}. */
19317 current_stub_contents =
19318 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19319 create_instruction_ldmia
19320 (ri, /*wback=*/0, insn_high_registers));
19321 }
19322 else if (wback && restore_pc && !restore_rn)
19323 {
19324 /* Choose a Ri in the high-register-list that will be restored. */
19325 ri = ctz (insn_high_registers & usable_register_mask & ~(1 << rn));
19326
19327 /* SUB Rn, Rn, #(4*nb_registers) */
19328 current_stub_contents =
19329 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19330 create_instruction_sub (rn, rn, (4 * nb_registers)));
19331
19332 /* MOV Ri, Rn. */
19333 current_stub_contents =
19334 push_thumb2_insn16 (htab, output_bfd, current_stub_contents,
19335 create_instruction_mov (ri, rn));
19336
19337 /* LDMIA Ri!, {R-low-register-list}. */
19338 current_stub_contents =
19339 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19340 create_instruction_ldmia
19341 (ri, /*wback=*/1, insn_low_registers));
19342
19343 /* LDMIA Ri, {R-high-register-list}. */
19344 current_stub_contents =
19345 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19346 create_instruction_ldmia
19347 (ri, /*wback=*/0, insn_high_registers));
19348 }
19349 else if (!wback && !restore_pc && restore_rn)
19350 {
19351 ri = rn;
19352 if (!(insn_low_registers & (1 << rn)))
19353 {
19354 /* Choose a Ri in the low-register-list that will be restored. */
19355 ri = ctz (insn_low_registers & usable_register_mask & ~(1 << rn));
19356
19357 /* MOV Ri, Rn. */
19358 current_stub_contents =
19359 push_thumb2_insn16 (htab, output_bfd, current_stub_contents,
19360 create_instruction_mov (ri, rn));
19361 }
19362
19363 /* LDMDB Ri!, {R-high-register-list}. */
19364 current_stub_contents =
19365 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19366 create_instruction_ldmdb
19367 (ri, /*wback=*/1, insn_high_registers));
19368
19369 /* LDMDB Ri, {R-low-register-list}. */
19370 current_stub_contents =
19371 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19372 create_instruction_ldmdb
19373 (ri, /*wback=*/0, insn_low_registers));
19374
19375 /* B initial_insn_addr+4. */
19376 current_stub_contents =
19377 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19378 create_instruction_branch_absolute
82188b29 19379 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 19380 }
19381 else if (!wback && restore_pc && restore_rn)
19382 {
19383 ri = rn;
19384 if (!(insn_high_registers & (1 << rn)))
19385 {
19386 /* Choose a Ri in the high-register-list that will be restored. */
19387 ri = ctz (insn_high_registers & usable_register_mask & ~(1 << rn));
19388 }
19389
19390 /* SUB Ri, Rn, #(4*nb_registers). */
19391 current_stub_contents =
19392 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19393 create_instruction_sub (ri, rn, (4 * nb_registers)));
19394
19395 /* LDMIA Ri!, {R-low-register-list}. */
19396 current_stub_contents =
19397 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19398 create_instruction_ldmia
19399 (ri, /*wback=*/1, insn_low_registers));
19400
19401 /* LDMIA Ri, {R-high-register-list}. */
19402 current_stub_contents =
19403 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19404 create_instruction_ldmia
19405 (ri, /*wback=*/0, insn_high_registers));
19406 }
19407 else if (wback && restore_rn)
19408 {
19409 /* The assembler should not have accepted to encode this. */
19410 BFD_ASSERT (0 && "Cannot patch an instruction that has an "
19411 "undefined behavior.\n");
19412 }
19413
19414 /* Fill the remaining of the stub with deterministic contents. */
19415 current_stub_contents =
19416 stm32l4xx_fill_stub_udf (htab, output_bfd,
19417 base_stub_contents, current_stub_contents,
19418 base_stub_contents +
19419 STM32L4XX_ERRATUM_LDM_VENEER_SIZE);
19420
19421}
19422
19423static void
19424stm32l4xx_create_replacing_stub_vldm (struct elf32_arm_link_hash_table * htab,
19425 bfd * output_bfd,
19426 const insn32 initial_insn,
19427 const bfd_byte *const initial_insn_addr,
19428 bfd_byte *const base_stub_contents)
19429{
9239bbd3 19430 int num_words = ((unsigned int) initial_insn << 24) >> 24;
a504d23a
LA		 19431 bfd_byte *current_stub_contents = base_stub_contents;
19432
19433 BFD_ASSERT (is_thumb2_vldm (initial_insn));
19434
19435 /* In BFD_ARM_STM32L4XX_FIX_ALL mode we may have to deal with
9239bbd3 19436 smaller than 8 words load sequences that do not cause the
a504d23a 19437 hardware issue. */
9239bbd3 19438 if (num_words <= 8)
a504d23a
LA		 19439 {
19440 /* Untouched instruction. */
19441 current_stub_contents =
19442 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19443 initial_insn);
19444
19445 /* B initial_insn_addr+4. */
19446 current_stub_contents =
19447 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19448 create_instruction_branch_absolute
82188b29 19449 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 19450 }
19451 else
19452 {
9eaff861 19453 bfd_boolean is_dp = /* DP encoding. */
9239bbd3 19454 (initial_insn & 0xfe100f00) == 0xec100b00;
a504d23a
LA		 19455 bfd_boolean is_ia_nobang = /* (IA without !). */
19456 (((initial_insn << 7) >> 28) & 0xd) == 0x4;
19457 bfd_boolean is_ia_bang = /* (IA with !) - includes VPOP. */
19458 (((initial_insn << 7) >> 28) & 0xd) == 0x5;
19459 bfd_boolean is_db_bang = /* (DB with !). */
19460 (((initial_insn << 7) >> 28) & 0xd) == 0x9;
9239bbd3 19461 int base_reg = ((unsigned int) initial_insn << 12) >> 28;
a504d23a 19462 /* d = UInt (Vd:D);. */
9239bbd3 19463 int first_reg = ((((unsigned int) initial_insn << 16) >> 28) << 1)
a504d23a
LA		 19464 | (((unsigned int)initial_insn << 9) >> 31);
19465
9239bbd3
CM		 19466 /* Compute the number of 8-words chunks needed to split. */
19467 int chunks = (num_words % 8) ? (num_words / 8 + 1) : (num_words / 8);
a504d23a
LA		 19468 int chunk;
19469
19470 /* The test coverage has been done assuming the following
19471 hypothesis that exactly one of the previous is_ predicates is
19472 true. */
9239bbd3
CM		 19473 BFD_ASSERT ( (is_ia_nobang ^ is_ia_bang ^ is_db_bang)
19474 && !(is_ia_nobang & is_ia_bang & is_db_bang));
a504d23a 19475
9239bbd3 19476 /* We treat the cutting of the words in one pass for all
a504d23a
LA		 19477 cases, then we emit the adjustments:
19478
19479 vldm rx, {...}
19480 -> vldm rx!, {8_words_or_less} for each needed 8_word
19481 -> sub rx, rx, #size (list)
19482
19483 vldm rx!, {...}
19484 -> vldm rx!, {8_words_or_less} for each needed 8_word
19485 This also handles vpop instruction (when rx is sp)
19486
19487 vldmd rx!, {...}
19488 -> vldmb rx!, {8_words_or_less} for each needed 8_word. */
9239bbd3 19489 for (chunk = 0; chunk < chunks; ++chunk)
a504d23a 19490 {
9239bbd3
CM		 19491 bfd_vma new_insn = 0;
19492
a504d23a
LA		 19493 if (is_ia_nobang || is_ia_bang)
19494 {
9239bbd3
CM		 19495 new_insn = create_instruction_vldmia
19496 (base_reg,
19497 is_dp,
19498 /*wback= . */1,
19499 chunks - (chunk + 1) ?
19500 8 : num_words - chunk * 8,
19501 first_reg + chunk * 8);
a504d23a
LA		 19502 }
19503 else if (is_db_bang)
19504 {
9239bbd3
CM		 19505 new_insn = create_instruction_vldmdb
19506 (base_reg,
19507 is_dp,
19508 chunks - (chunk + 1) ?
19509 8 : num_words - chunk * 8,
19510 first_reg + chunk * 8);
a504d23a 19511 }
9239bbd3
CM		 19512
19513 if (new_insn)
19514 current_stub_contents =
19515 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19516 new_insn);
a504d23a
LA		 19517 }
19518
19519 /* Only this case requires the base register compensation
19520 subtract. */
19521 if (is_ia_nobang)
19522 {
19523 current_stub_contents =
19524 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19525 create_instruction_sub
9239bbd3 19526 (base_reg, base_reg, 4*num_words));
a504d23a
LA		 19527 }
19528
19529 /* B initial_insn_addr+4. */
19530 current_stub_contents =
19531 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19532 create_instruction_branch_absolute
82188b29 19533 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 19534 }
19535
19536 /* Fill the remaining of the stub with deterministic contents. */
19537 current_stub_contents =
19538 stm32l4xx_fill_stub_udf (htab, output_bfd,
19539 base_stub_contents, current_stub_contents,
19540 base_stub_contents +
19541 STM32L4XX_ERRATUM_VLDM_VENEER_SIZE);
19542}
19543
19544static void
19545stm32l4xx_create_replacing_stub (struct elf32_arm_link_hash_table * htab,
19546 bfd * output_bfd,
19547 const insn32 wrong_insn,
19548 const bfd_byte *const wrong_insn_addr,
19549 bfd_byte *const stub_contents)
19550{
19551 if (is_thumb2_ldmia (wrong_insn))
19552 stm32l4xx_create_replacing_stub_ldmia (htab, output_bfd,
19553 wrong_insn, wrong_insn_addr,
19554 stub_contents);
19555 else if (is_thumb2_ldmdb (wrong_insn))
19556 stm32l4xx_create_replacing_stub_ldmdb (htab, output_bfd,
19557 wrong_insn, wrong_insn_addr,
19558 stub_contents);
19559 else if (is_thumb2_vldm (wrong_insn))
19560 stm32l4xx_create_replacing_stub_vldm (htab, output_bfd,
19561 wrong_insn, wrong_insn_addr,
19562 stub_contents);
19563}
19564
19565/* End of stm32l4xx work-around. */
19566
19567
e489d0ae
PB		 19568/* Do code byteswapping. Return FALSE afterwards so that the section is
19569 written out as normal. */
19570
19571static bfd_boolean
c7b8f16e 19572elf32_arm_write_section (bfd *output_bfd,
8029a119
NC		 19573 struct bfd_link_info *link_info,
19574 asection *sec,
e489d0ae
PB		 19575 bfd_byte *contents)
19576{
48229727 19577 unsigned int mapcount, errcount;
8e3de13a 19578 _arm_elf_section_data *arm_data;
c7b8f16e 19579 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (link_info);
e489d0ae 19580 elf32_arm_section_map *map;
c7b8f16e 19581 elf32_vfp11_erratum_list *errnode;
a504d23a 19582 elf32_stm32l4xx_erratum_list *stm32l4xx_errnode;
e489d0ae
PB		 19583 bfd_vma ptr;
19584 bfd_vma end;
c7b8f16e 19585 bfd_vma offset = sec->output_section->vma + sec->output_offset;
e489d0ae 19586 bfd_byte tmp;
48229727 19587 unsigned int i;
57e8b36a 19588
4dfe6ac6
NC		 19589 if (globals == NULL)
19590 return FALSE;
19591
8e3de13a
NC		 19592 /* If this section has not been allocated an _arm_elf_section_data
19593 structure then we cannot record anything. */
19594 arm_data = get_arm_elf_section_data (sec);
19595 if (arm_data == NULL)
19596 return FALSE;
19597
19598 mapcount = arm_data->mapcount;
19599 map = arm_data->map;
c7b8f16e
JB		 19600 errcount = arm_data->erratumcount;
19601
19602 if (errcount != 0)
19603 {
19604 unsigned int endianflip = bfd_big_endian (output_bfd) ? 3 : 0;
19605
19606 for (errnode = arm_data->erratumlist; errnode != 0;
99059e56
RM		 19607 errnode = errnode->next)
19608 {
19609 bfd_vma target = errnode->vma - offset;
19610
19611 switch (errnode->type)
19612 {
19613 case VFP11_ERRATUM_BRANCH_TO_ARM_VENEER:
19614 {
19615 bfd_vma branch_to_veneer;
19616 /* Original condition code of instruction, plus bit mask for
19617 ARM B instruction. */
19618 unsigned int insn = (errnode->u.b.vfp_insn & 0xf0000000)
19619 | 0x0a000000;
c7b8f16e
JB		 19620
19621 /* The instruction is before the label. */
91d6fa6a 19622 target -= 4;
c7b8f16e
JB		 19623
19624 /* Above offset included in -4 below. */
19625 branch_to_veneer = errnode->u.b.veneer->vma
99059e56 19626 - errnode->vma - 4;
c7b8f16e
JB		 19627
19628 if ((signed) branch_to_veneer < -(1 << 25)
19629 || (signed) branch_to_veneer >= (1 << 25))
871b3ab2 19630 _bfd_error_handler (_("%pB: error: VFP11 veneer out of "
4eca0228 19631 "range"), output_bfd);
c7b8f16e 19632
99059e56
RM		 19633 insn |= (branch_to_veneer >> 2) & 0xffffff;
19634 contents[endianflip ^ target] = insn & 0xff;
19635 contents[endianflip ^ (target + 1)] = (insn >> 8) & 0xff;
19636 contents[endianflip ^ (target + 2)] = (insn >> 16) & 0xff;
19637 contents[endianflip ^ (target + 3)] = (insn >> 24) & 0xff;
19638 }
19639 break;
c7b8f16e
JB		 19640
19641 case VFP11_ERRATUM_ARM_VENEER:
99059e56
RM		 19642 {
19643 bfd_vma branch_from_veneer;
19644 unsigned int insn;
c7b8f16e 19645
99059e56
RM		 19646 /* Take size of veneer into account. */
19647 branch_from_veneer = errnode->u.v.branch->vma
19648 - errnode->vma - 12;
c7b8f16e
JB		 19649
19650 if ((signed) branch_from_veneer < -(1 << 25)
19651 || (signed) branch_from_veneer >= (1 << 25))
871b3ab2 19652 _bfd_error_handler (_("%pB: error: VFP11 veneer out of "
4eca0228 19653 "range"), output_bfd);
c7b8f16e 19654
99059e56
RM		 19655 /* Original instruction. */
19656 insn = errnode->u.v.branch->u.b.vfp_insn;
19657 contents[endianflip ^ target] = insn & 0xff;
19658 contents[endianflip ^ (target + 1)] = (insn >> 8) & 0xff;
19659 contents[endianflip ^ (target + 2)] = (insn >> 16) & 0xff;
19660 contents[endianflip ^ (target + 3)] = (insn >> 24) & 0xff;
19661
19662 /* Branch back to insn after original insn. */
19663 insn = 0xea000000 | ((branch_from_veneer >> 2) & 0xffffff);
19664 contents[endianflip ^ (target + 4)] = insn & 0xff;
19665 contents[endianflip ^ (target + 5)] = (insn >> 8) & 0xff;
19666 contents[endianflip ^ (target + 6)] = (insn >> 16) & 0xff;
19667 contents[endianflip ^ (target + 7)] = (insn >> 24) & 0xff;
19668 }
19669 break;
c7b8f16e 19670
99059e56
RM		 19671 default:
19672 abort ();
19673 }
19674 }
c7b8f16e 19675 }
e489d0ae 19676
a504d23a
LA		 19677 if (arm_data->stm32l4xx_erratumcount != 0)
19678 {
19679 for (stm32l4xx_errnode = arm_data->stm32l4xx_erratumlist;
19680 stm32l4xx_errnode != 0;
19681 stm32l4xx_errnode = stm32l4xx_errnode->next)
19682 {
19683 bfd_vma target = stm32l4xx_errnode->vma - offset;
19684
19685 switch (stm32l4xx_errnode->type)
19686 {
19687 case STM32L4XX_ERRATUM_BRANCH_TO_VENEER:
19688 {
19689 unsigned int insn;
19690 bfd_vma branch_to_veneer =
19691 stm32l4xx_errnode->u.b.veneer->vma - stm32l4xx_errnode->vma;
19692
19693 if ((signed) branch_to_veneer < -(1 << 24)
19694 || (signed) branch_to_veneer >= (1 << 24))
19695 {
19696 bfd_vma out_of_range =
19697 ((signed) branch_to_veneer < -(1 << 24)) ?
19698 - branch_to_veneer - (1 << 24) :
19699 ((signed) branch_to_veneer >= (1 << 24)) ?
19700 branch_to_veneer - (1 << 24) : 0;
19701
4eca0228 19702 _bfd_error_handler
2dcf00ce 19703 (_("%pB(%#" PRIx64 "): error: "
90b6238f
AM		 19704 "cannot create STM32L4XX veneer; "
19705 "jump out of range by %" PRId64 " bytes; "
19706 "cannot encode branch instruction"),
a504d23a 19707 output_bfd,
2dcf00ce
AM		 19708 (uint64_t) (stm32l4xx_errnode->vma - 4),
19709 (int64_t) out_of_range);
a504d23a
LA		 19710 continue;
19711 }
19712
19713 insn = create_instruction_branch_absolute
82188b29 19714 (stm32l4xx_errnode->u.b.veneer->vma - stm32l4xx_errnode->vma);
a504d23a 19715
a2699ef2
AM		 19716 /* The instruction is before the label. */
19717 target -= 4;
19718
a504d23a
LA		 19719 put_thumb2_insn (globals, output_bfd,
19720 (bfd_vma) insn, contents + target);
19721 }
19722 break;
19723
19724 case STM32L4XX_ERRATUM_VENEER:
19725 {
82188b29
NC		 19726 bfd_byte * veneer;
19727 bfd_byte * veneer_r;
a504d23a
LA		 19728 unsigned int insn;
19729
82188b29
NC		 19730 veneer = contents + target;
19731 veneer_r = veneer
19732 + stm32l4xx_errnode->u.b.veneer->vma
19733 - stm32l4xx_errnode->vma - 4;
a504d23a
LA		 19734
19735 if ((signed) (veneer_r - veneer -
19736 STM32L4XX_ERRATUM_VLDM_VENEER_SIZE >
19737 STM32L4XX_ERRATUM_LDM_VENEER_SIZE ?
19738 STM32L4XX_ERRATUM_VLDM_VENEER_SIZE :
19739 STM32L4XX_ERRATUM_LDM_VENEER_SIZE) < -(1 << 24)
19740 || (signed) (veneer_r - veneer) >= (1 << 24))
19741 {
90b6238f
AM		 19742 _bfd_error_handler (_("%pB: error: cannot create STM32L4XX "
19743 "veneer"), output_bfd);
a504d23a
LA		 19744 continue;
19745 }
19746
19747 /* Original instruction. */
19748 insn = stm32l4xx_errnode->u.v.branch->u.b.insn;
19749
19750 stm32l4xx_create_replacing_stub
19751 (globals, output_bfd, insn, (void*)veneer_r, (void*)veneer);
19752 }
19753 break;
19754
19755 default:
19756 abort ();
19757 }
19758 }
19759 }
19760
2468f9c9
PB		 19761 if (arm_data->elf.this_hdr.sh_type == SHT_ARM_EXIDX)
19762 {
19763 arm_unwind_table_edit *edit_node
99059e56 19764 = arm_data->u.exidx.unwind_edit_list;
2468f9c9 19765 /* Now, sec->size is the size of the section we will write. The original
99059e56 19766 size (before we merged duplicate entries and inserted EXIDX_CANTUNWIND
2468f9c9
PB		 19767 markers) was sec->rawsize. (This isn't the case if we perform no
19768 edits, then rawsize will be zero and we should use size). */
21d799b5 19769 bfd_byte *edited_contents = (bfd_byte *) bfd_malloc (sec->size);
2468f9c9
PB		 19770 unsigned int input_size = sec->rawsize ? sec->rawsize : sec->size;
19771 unsigned int in_index, out_index;
19772 bfd_vma add_to_offsets = 0;
19773
19774 for (in_index = 0, out_index = 0; in_index * 8 < input_size || edit_node;)
99059e56 19775 {
2468f9c9
PB		 19776 if (edit_node)
19777 {
19778 unsigned int edit_index = edit_node->index;
b38cadfb 19779
2468f9c9 19780 if (in_index < edit_index && in_index * 8 < input_size)
99059e56 19781 {
2468f9c9
PB		 19782 copy_exidx_entry (output_bfd, edited_contents + out_index * 8,
19783 contents + in_index * 8, add_to_offsets);
19784 out_index++;
19785 in_index++;
19786 }
19787 else if (in_index == edit_index
19788 || (in_index * 8 >= input_size
19789 && edit_index == UINT_MAX))
99059e56 19790 {
2468f9c9
PB		 19791 switch (edit_node->type)
19792 {
19793 case DELETE_EXIDX_ENTRY:
19794 in_index++;
19795 add_to_offsets += 8;
19796 break;
b38cadfb 19797
2468f9c9
PB		 19798 case INSERT_EXIDX_CANTUNWIND_AT_END:
19799 {
99059e56 19800 asection *text_sec = edit_node->linked_section;
2468f9c9
PB		 19801 bfd_vma text_offset = text_sec->output_section->vma
19802 + text_sec->output_offset
19803 + text_sec->size;
19804 bfd_vma exidx_offset = offset + out_index * 8;
99059e56 19805 unsigned long prel31_offset;
2468f9c9
PB		 19806
19807 /* Note: this is meant to be equivalent to an
19808 R_ARM_PREL31 relocation. These synthetic
19809 EXIDX_CANTUNWIND markers are not relocated by the
19810 usual BFD method. */
19811 prel31_offset = (text_offset - exidx_offset)
19812 & 0x7ffffffful;
491d01d3
YU		 19813 if (bfd_link_relocatable (link_info))
19814 {
19815 /* Here relocation for new EXIDX_CANTUNWIND is
19816 created, so there is no need to
19817 adjust offset by hand. */
19818 prel31_offset = text_sec->output_offset
19819 + text_sec->size;
491d01d3 19820 }
2468f9c9
PB		 19821
19822 /* First address we can't unwind. */
19823 bfd_put_32 (output_bfd, prel31_offset,
19824 &edited_contents[out_index * 8]);
19825
19826 /* Code for EXIDX_CANTUNWIND. */
19827 bfd_put_32 (output_bfd, 0x1,
19828 &edited_contents[out_index * 8 + 4]);
19829
19830 out_index++;
19831 add_to_offsets -= 8;
19832 }
19833 break;
19834 }
b38cadfb 19835
2468f9c9
PB		 19836 edit_node = edit_node->next;
19837 }
19838 }
19839 else
19840 {
19841 /* No more edits, copy remaining entries verbatim. */
19842 copy_exidx_entry (output_bfd, edited_contents + out_index * 8,
19843 contents + in_index * 8, add_to_offsets);
19844 out_index++;
19845 in_index++;
19846 }
19847 }
19848
19849 if (!(sec->flags & SEC_EXCLUDE) && !(sec->flags & SEC_NEVER_LOAD))
19850 bfd_set_section_contents (output_bfd, sec->output_section,
19851 edited_contents,
19852 (file_ptr) sec->output_offset, sec->size);
19853
19854 return TRUE;
19855 }
19856
48229727
JB		 19857 /* Fix code to point to Cortex-A8 erratum stubs. */
19858 if (globals->fix_cortex_a8)
19859 {
19860 struct a8_branch_to_stub_data data;
19861
19862 data.writing_section = sec;
19863 data.contents = contents;
19864
a504d23a
LA		 19865 bfd_hash_traverse (& globals->stub_hash_table, make_branch_to_a8_stub,
19866 & data);
48229727
JB		 19867 }
19868
e489d0ae
PB		 19869 if (mapcount == 0)
19870 return FALSE;
19871
c7b8f16e 19872 if (globals->byteswap_code)
e489d0ae 19873 {
c7b8f16e 19874 qsort (map, mapcount, sizeof (* map), elf32_arm_compare_mapping);
57e8b36a 19875
c7b8f16e
JB		 19876 ptr = map[0].vma;
19877 for (i = 0; i < mapcount; i++)
99059e56
RM		 19878 {
19879 if (i == mapcount - 1)
c7b8f16e 19880 end = sec->size;
99059e56
RM		 19881 else
19882 end = map[i + 1].vma;
e489d0ae 19883
99059e56 19884 switch (map[i].type)
e489d0ae 19885 {
c7b8f16e
JB		 19886 case 'a':
19887 /* Byte swap code words. */
19888 while (ptr + 3 < end)
99059e56
RM		 19889 {
19890 tmp = contents[ptr];
19891 contents[ptr] = contents[ptr + 3];
19892 contents[ptr + 3] = tmp;
19893 tmp = contents[ptr + 1];
19894 contents[ptr + 1] = contents[ptr + 2];
19895 contents[ptr + 2] = tmp;
19896 ptr += 4;
19897 }
c7b8f16e 19898 break;
e489d0ae 19899
c7b8f16e
JB		 19900 case 't':
19901 /* Byte swap code halfwords. */
19902 while (ptr + 1 < end)
99059e56
RM		 19903 {
19904 tmp = contents[ptr];
19905 contents[ptr] = contents[ptr + 1];
19906 contents[ptr + 1] = tmp;
19907 ptr += 2;
19908 }
c7b8f16e
JB		 19909 break;
19910
19911 case 'd':
19912 /* Leave data alone. */
19913 break;
19914 }
99059e56
RM		 19915 ptr = end;
19916 }
e489d0ae 19917 }
8e3de13a 19918
93204d3a 19919 free (map);
47b2e99c 19920 arm_data->mapcount = -1;
c7b8f16e 19921 arm_data->mapsize = 0;
8e3de13a 19922 arm_data->map = NULL;
8e3de13a 19923
e489d0ae
PB		 19924 return FALSE;
19925}
19926
0beaef2b
PB		 19927/* Mangle thumb function symbols as we read them in. */
19928
8384fb8f 19929static bfd_boolean
0beaef2b
PB		 19930elf32_arm_swap_symbol_in (bfd * abfd,
19931 const void *psrc,
19932 const void *pshn,
19933 Elf_Internal_Sym *dst)
19934{
8384fb8f
AM		 19935 if (!bfd_elf32_swap_symbol_in (abfd, psrc, pshn, dst))
19936 return FALSE;
39d911fc 19937 dst->st_target_internal = 0;
0beaef2b
PB		 19938
19939 /* New EABI objects mark thumb function symbols by setting the low bit of
35fc36a8 19940 the address. */
63e1a0fc
PB		 19941 if (ELF_ST_TYPE (dst->st_info) == STT_FUNC
19942 || ELF_ST_TYPE (dst->st_info) == STT_GNU_IFUNC)
0beaef2b 19943 {
63e1a0fc
PB		 19944 if (dst->st_value & 1)
19945 {
19946 dst->st_value &= ~(bfd_vma) 1;
39d911fc
TP		 19947 ARM_SET_SYM_BRANCH_TYPE (dst->st_target_internal,
19948 ST_BRANCH_TO_THUMB);
63e1a0fc
PB		 19949 }
19950 else
39d911fc 19951 ARM_SET_SYM_BRANCH_TYPE (dst->st_target_internal, ST_BRANCH_TO_ARM);
35fc36a8
RS		 19952 }
19953 else if (ELF_ST_TYPE (dst->st_info) == STT_ARM_TFUNC)
19954 {
19955 dst->st_info = ELF_ST_INFO (ELF_ST_BIND (dst->st_info), STT_FUNC);
39d911fc 19956 ARM_SET_SYM_BRANCH_TYPE (dst->st_target_internal, ST_BRANCH_TO_THUMB);
0beaef2b 19957 }
35fc36a8 19958 else if (ELF_ST_TYPE (dst->st_info) == STT_SECTION)
39d911fc 19959 ARM_SET_SYM_BRANCH_TYPE (dst->st_target_internal, ST_BRANCH_LONG);
35fc36a8 19960 else
39d911fc 19961 ARM_SET_SYM_BRANCH_TYPE (dst->st_target_internal, ST_BRANCH_UNKNOWN);
35fc36a8 19962
8384fb8f 19963 return TRUE;
0beaef2b
PB		 19964}
19965
19966
19967/* Mangle thumb function symbols as we write them out. */
19968
19969static void
19970elf32_arm_swap_symbol_out (bfd *abfd,
19971 const Elf_Internal_Sym *src,
19972 void *cdst,
19973 void *shndx)
19974{
19975 Elf_Internal_Sym newsym;
19976
19977 /* We convert STT_ARM_TFUNC symbols into STT_FUNC with the low bit
19978 of the address set, as per the new EABI. We do this unconditionally
19979 because objcopy does not set the elf header flags until after
19980 it writes out the symbol table. */
39d911fc 19981 if (ARM_GET_SYM_BRANCH_TYPE (src->st_target_internal) == ST_BRANCH_TO_THUMB)
0beaef2b
PB		 19982 {
19983 newsym = *src;
34e77a92
RS		 19984 if (ELF_ST_TYPE (src->st_info) != STT_GNU_IFUNC)
19985 newsym.st_info = ELF_ST_INFO (ELF_ST_BIND (src->st_info), STT_FUNC);
0fa3dcad 19986 if (newsym.st_shndx != SHN_UNDEF)
99059e56
RM		 19987 {
19988 /* Do this only for defined symbols. At link type, the static
19989 linker will simulate the work of dynamic linker of resolving
19990 symbols and will carry over the thumbness of found symbols to
19991 the output symbol table. It's not clear how it happens, but
19992 the thumbness of undefined symbols can well be different at
19993 runtime, and writing '1' for them will be confusing for users
19994 and possibly for dynamic linker itself.
19995 */
19996 newsym.st_value |= 1;
19997 }
906e58ca 19998
0beaef2b
PB		 19999 src = &newsym;
20000 }
20001 bfd_elf32_swap_symbol_out (abfd, src, cdst, shndx);
20002}
20003
b294bdf8
MM		 20004/* Add the PT_ARM_EXIDX program header. */
20005
20006static bfd_boolean
906e58ca 20007elf32_arm_modify_segment_map (bfd *abfd,
b294bdf8
MM		 20008 struct bfd_link_info *info ATTRIBUTE_UNUSED)
20009{
20010 struct elf_segment_map *m;
20011 asection *sec;
20012
20013 sec = bfd_get_section_by_name (abfd, ".ARM.exidx");
20014 if (sec != NULL && (sec->flags & SEC_LOAD) != 0)
20015 {
20016 /* If there is already a PT_ARM_EXIDX header, then we do not
20017 want to add another one. This situation arises when running
20018 "strip"; the input binary already has the header. */
12bd6957 20019 m = elf_seg_map (abfd);
b294bdf8
MM		 20020 while (m && m->p_type != PT_ARM_EXIDX)
20021 m = m->next;
20022 if (!m)
20023 {
21d799b5 20024 m = (struct elf_segment_map *)
99059e56 20025 bfd_zalloc (abfd, sizeof (struct elf_segment_map));
b294bdf8
MM		 20026 if (m == NULL)
20027 return FALSE;
20028 m->p_type = PT_ARM_EXIDX;
20029 m->count = 1;
20030 m->sections[0] = sec;
20031
12bd6957
AM		 20032 m->next = elf_seg_map (abfd);
20033 elf_seg_map (abfd) = m;
b294bdf8
MM		 20034 }
20035 }
20036
20037 return TRUE;
20038}
20039
20040/* We may add a PT_ARM_EXIDX program header. */
20041
20042static int
a6b96beb
AM		 20043elf32_arm_additional_program_headers (bfd *abfd,
20044 struct bfd_link_info *info ATTRIBUTE_UNUSED)
b294bdf8
MM		 20045{
20046 asection *sec;
20047
20048 sec = bfd_get_section_by_name (abfd, ".ARM.exidx");
20049 if (sec != NULL && (sec->flags & SEC_LOAD) != 0)
20050 return 1;
20051 else
20052 return 0;
20053}
20054
34e77a92
RS		 20055/* Hook called by the linker routine which adds symbols from an object
20056 file. */
20057
20058static bfd_boolean
20059elf32_arm_add_symbol_hook (bfd *abfd, struct bfd_link_info *info,
20060 Elf_Internal_Sym *sym, const char **namep,
20061 flagword *flagsp, asection **secp, bfd_vma *valp)
20062{
c792917c
NC		 20063 if (elf32_arm_hash_table (info) == NULL)
20064 return FALSE;
20065
34e77a92
RS		 20066 if (elf32_arm_hash_table (info)->vxworks_p
20067 && !elf_vxworks_add_symbol_hook (abfd, info, sym, namep,
20068 flagsp, secp, valp))
20069 return FALSE;
20070
20071 return TRUE;
20072}
20073
0beaef2b 20074/* We use this to override swap_symbol_in and swap_symbol_out. */
906e58ca
NC		 20075const struct elf_size_info elf32_arm_size_info =
20076{
0beaef2b
PB		 20077 sizeof (Elf32_External_Ehdr),
20078 sizeof (Elf32_External_Phdr),
20079 sizeof (Elf32_External_Shdr),
20080 sizeof (Elf32_External_Rel),
20081 sizeof (Elf32_External_Rela),
20082 sizeof (Elf32_External_Sym),
20083 sizeof (Elf32_External_Dyn),
20084 sizeof (Elf_External_Note),
20085 4,
20086 1,
20087 32, 2,
20088 ELFCLASS32, EV_CURRENT,
20089 bfd_elf32_write_out_phdrs,
20090 bfd_elf32_write_shdrs_and_ehdr,
1489a3a0 20091 bfd_elf32_checksum_contents,
0beaef2b
PB		 20092 bfd_elf32_write_relocs,
20093 elf32_arm_swap_symbol_in,
20094 elf32_arm_swap_symbol_out,
20095 bfd_elf32_slurp_reloc_table,
20096 bfd_elf32_slurp_symbol_table,
20097 bfd_elf32_swap_dyn_in,
20098 bfd_elf32_swap_dyn_out,
20099 bfd_elf32_swap_reloc_in,
20100 bfd_elf32_swap_reloc_out,
20101 bfd_elf32_swap_reloca_in,
20102 bfd_elf32_swap_reloca_out
20103};
20104
685e70ae
VK		 20105static bfd_vma
20106read_code32 (const bfd *abfd, const bfd_byte *addr)
20107{
20108 /* V7 BE8 code is always little endian. */
20109 if ((elf_elfheader (abfd)->e_flags & EF_ARM_BE8) != 0)
20110 return bfd_getl32 (addr);
20111
20112 return bfd_get_32 (abfd, addr);
20113}
20114
20115static bfd_vma
20116read_code16 (const bfd *abfd, const bfd_byte *addr)
20117{
20118 /* V7 BE8 code is always little endian. */
20119 if ((elf_elfheader (abfd)->e_flags & EF_ARM_BE8) != 0)
20120 return bfd_getl16 (addr);
20121
20122 return bfd_get_16 (abfd, addr);
20123}
20124
6a631e86
YG		 20125/* Return size of plt0 entry starting at ADDR
20126 or (bfd_vma) -1 if size can not be determined. */
20127
20128static bfd_vma
20129elf32_arm_plt0_size (const bfd *abfd, const bfd_byte *addr)
20130{
20131 bfd_vma first_word;
20132 bfd_vma plt0_size;
20133
685e70ae 20134 first_word = read_code32 (abfd, addr);
6a631e86
YG		 20135
20136 if (first_word == elf32_arm_plt0_entry[0])
20137 plt0_size = 4 * ARRAY_SIZE (elf32_arm_plt0_entry);
20138 else if (first_word == elf32_thumb2_plt0_entry[0])
20139 plt0_size = 4 * ARRAY_SIZE (elf32_thumb2_plt0_entry);
20140 else
20141 /* We don't yet handle this PLT format. */
20142 return (bfd_vma) -1;
20143
20144 return plt0_size;
20145}
20146
20147/* Return size of plt entry starting at offset OFFSET
20148 of plt section located at address START
20149 or (bfd_vma) -1 if size can not be determined. */
20150
20151static bfd_vma
20152elf32_arm_plt_size (const bfd *abfd, const bfd_byte *start, bfd_vma offset)
20153{
20154 bfd_vma first_insn;
20155 bfd_vma plt_size = 0;
20156 const bfd_byte *addr = start + offset;
20157
20158 /* PLT entry size if fixed on Thumb-only platforms. */
685e70ae 20159 if (read_code32 (abfd, start) == elf32_thumb2_plt0_entry[0])
6a631e86
YG		 20160 return 4 * ARRAY_SIZE (elf32_thumb2_plt_entry);
20161
20162 /* Respect Thumb stub if necessary. */
685e70ae 20163 if (read_code16 (abfd, addr) == elf32_arm_plt_thumb_stub[0])
6a631e86
YG		 20164 {
20165 plt_size += 2 * ARRAY_SIZE(elf32_arm_plt_thumb_stub);
20166 }
20167
20168 /* Strip immediate from first add. */
685e70ae 20169 first_insn = read_code32 (abfd, addr + plt_size) & 0xffffff00;
6a631e86
YG		 20170
20171#ifdef FOUR_WORD_PLT
20172 if (first_insn == elf32_arm_plt_entry[0])
20173 plt_size += 4 * ARRAY_SIZE (elf32_arm_plt_entry);
20174#else
20175 if (first_insn == elf32_arm_plt_entry_long[0])
20176 plt_size += 4 * ARRAY_SIZE (elf32_arm_plt_entry_long);
20177 else if (first_insn == elf32_arm_plt_entry_short[0])
20178 plt_size += 4 * ARRAY_SIZE (elf32_arm_plt_entry_short);
20179#endif
20180 else
20181 /* We don't yet handle this PLT format. */
20182 return (bfd_vma) -1;
20183
20184 return plt_size;
20185}
20186
20187/* Implementation is shamelessly borrowed from _bfd_elf_get_synthetic_symtab. */
20188
20189static long
20190elf32_arm_get_synthetic_symtab (bfd *abfd,
20191 long symcount ATTRIBUTE_UNUSED,
20192 asymbol **syms ATTRIBUTE_UNUSED,
20193 long dynsymcount,
20194 asymbol **dynsyms,
20195 asymbol **ret)
20196{
20197 asection *relplt;
20198 asymbol *s;
20199 arelent *p;
20200 long count, i, n;
20201 size_t size;
20202 Elf_Internal_Shdr *hdr;
20203 char *names;
20204 asection *plt;
20205 bfd_vma offset;
20206 bfd_byte *data;
20207
20208 *ret = NULL;
20209
20210 if ((abfd->flags & (DYNAMIC | EXEC_P)) == 0)
20211 return 0;
20212
20213 if (dynsymcount <= 0)
20214 return 0;
20215
20216 relplt = bfd_get_section_by_name (abfd, ".rel.plt");
20217 if (relplt == NULL)
20218 return 0;
20219
20220 hdr = &elf_section_data (relplt)->this_hdr;
20221 if (hdr->sh_link != elf_dynsymtab (abfd)
20222 || (hdr->sh_type != SHT_REL && hdr->sh_type != SHT_RELA))
20223 return 0;
20224
20225 plt = bfd_get_section_by_name (abfd, ".plt");
20226 if (plt == NULL)
20227 return 0;
20228
20229 if (!elf32_arm_size_info.slurp_reloc_table (abfd, relplt, dynsyms, TRUE))
20230 return -1;
20231
20232 data = plt->contents;
20233 if (data == NULL)
20234 {
20235 if (!bfd_get_full_section_contents(abfd, (asection *) plt, &data) || data == NULL)
20236 return -1;
20237 bfd_cache_section_contents((asection *) plt, data);
20238 }
20239
20240 count = relplt->size / hdr->sh_entsize;
20241 size = count * sizeof (asymbol);
20242 p = relplt->relocation;
20243 for (i = 0; i < count; i++, p += elf32_arm_size_info.int_rels_per_ext_rel)
20244 {
20245 size += strlen ((*p->sym_ptr_ptr)->name) + sizeof ("@plt");
20246 if (p->addend != 0)
20247 size += sizeof ("+0x") - 1 + 8;
20248 }
20249
20250 s = *ret = (asymbol *) bfd_malloc (size);
20251 if (s == NULL)
20252 return -1;
20253
20254 offset = elf32_arm_plt0_size (abfd, data);
20255 if (offset == (bfd_vma) -1)
20256 return -1;
20257
20258 names = (char *) (s + count);
20259 p = relplt->relocation;
20260 n = 0;
20261 for (i = 0; i < count; i++, p += elf32_arm_size_info.int_rels_per_ext_rel)
20262 {
20263 size_t len;
20264
20265 bfd_vma plt_size = elf32_arm_plt_size (abfd, data, offset);
20266 if (plt_size == (bfd_vma) -1)
20267 break;
20268
20269 *s = **p->sym_ptr_ptr;
20270 /* Undefined syms won't have BSF_LOCAL or BSF_GLOBAL set. Since
20271 we are defining a symbol, ensure one of them is set. */
20272 if ((s->flags & BSF_LOCAL) == 0)
20273 s->flags |= BSF_GLOBAL;
20274 s->flags |= BSF_SYNTHETIC;
20275 s->section = plt;
20276 s->value = offset;
20277 s->name = names;
20278 s->udata.p = NULL;
20279 len = strlen ((*p->sym_ptr_ptr)->name);
20280 memcpy (names, (*p->sym_ptr_ptr)->name, len);
20281 names += len;
20282 if (p->addend != 0)
20283 {
20284 char buf[30], *a;
20285
20286 memcpy (names, "+0x", sizeof ("+0x") - 1);
20287 names += sizeof ("+0x") - 1;
20288 bfd_sprintf_vma (abfd, buf, p->addend);
20289 for (a = buf; *a == '0'; ++a)
20290 ;
20291 len = strlen (a);
20292 memcpy (names, a, len);
20293 names += len;
20294 }
20295 memcpy (names, "@plt", sizeof ("@plt"));
20296 names += sizeof ("@plt");
20297 ++s, ++n;
20298 offset += plt_size;
20299 }
20300
20301 return n;
20302}
20303
ac4c9b04
MG		 20304static bfd_boolean
20305elf32_arm_section_flags (flagword *flags, const Elf_Internal_Shdr * hdr)
20306{
f0728ee3
AV		 20307 if (hdr->sh_flags & SHF_ARM_PURECODE)
20308 *flags |= SEC_ELF_PURECODE;
ac4c9b04
MG		 20309 return TRUE;
20310}
20311
20312static flagword
20313elf32_arm_lookup_section_flags (char *flag_name)
20314{
f0728ee3
AV		 20315 if (!strcmp (flag_name, "SHF_ARM_PURECODE"))
20316 return SHF_ARM_PURECODE;
ac4c9b04
MG		 20317
20318 return SEC_NO_FLAGS;
20319}
20320
491d01d3
YU		 20321static unsigned int
20322elf32_arm_count_additional_relocs (asection *sec)
20323{
20324 struct _arm_elf_section_data *arm_data;
20325 arm_data = get_arm_elf_section_data (sec);
5025eb7c 20326
6342be70 20327 return arm_data == NULL ? 0 : arm_data->additional_reloc_count;
491d01d3
YU		 20328}
20329
5522f910 20330/* Called to set the sh_flags, sh_link and sh_info fields of OSECTION which
9eaff861 20331 has a type >= SHT_LOOS. Returns TRUE if these fields were initialised
5522f910
NC		 20332 FALSE otherwise. ISECTION is the best guess matching section from the
20333 input bfd IBFD, but it might be NULL. */
20334
20335static bfd_boolean
20336elf32_arm_copy_special_section_fields (const bfd *ibfd ATTRIBUTE_UNUSED,
20337 bfd *obfd ATTRIBUTE_UNUSED,
20338 const Elf_Internal_Shdr *isection ATTRIBUTE_UNUSED,
20339 Elf_Internal_Shdr *osection)
20340{
20341 switch (osection->sh_type)
20342 {
20343 case SHT_ARM_EXIDX:
20344 {
20345 Elf_Internal_Shdr **oheaders = elf_elfsections (obfd);
20346 Elf_Internal_Shdr **iheaders = elf_elfsections (ibfd);
20347 unsigned i = 0;
20348
20349 osection->sh_flags = SHF_ALLOC | SHF_LINK_ORDER;
20350 osection->sh_info = 0;
20351
20352 /* The sh_link field must be set to the text section associated with
20353 this index section. Unfortunately the ARM EHABI does not specify
20354 exactly how to determine this association. Our caller does try
20355 to match up OSECTION with its corresponding input section however
20356 so that is a good first guess. */
20357 if (isection != NULL
20358 && osection->bfd_section != NULL
20359 && isection->bfd_section != NULL
20360 && isection->bfd_section->output_section != NULL
20361 && isection->bfd_section->output_section == osection->bfd_section
20362 && iheaders != NULL
20363 && isection->sh_link > 0
20364 && isection->sh_link < elf_numsections (ibfd)
20365 && iheaders[isection->sh_link]->bfd_section != NULL
20366 && iheaders[isection->sh_link]->bfd_section->output_section != NULL
20367 )
20368 {
20369 for (i = elf_numsections (obfd); i-- > 0;)
20370 if (oheaders[i]->bfd_section
20371 == iheaders[isection->sh_link]->bfd_section->output_section)
20372 break;
20373 }
9eaff861 20374
5522f910
NC		 20375 if (i == 0)
20376 {
20377 /* Failing that we have to find a matching section ourselves. If
20378 we had the output section name available we could compare that
20379 with input section names. Unfortunately we don't. So instead
20380 we use a simple heuristic and look for the nearest executable
20381 section before this one. */
20382 for (i = elf_numsections (obfd); i-- > 0;)
20383 if (oheaders[i] == osection)
20384 break;
20385 if (i == 0)
20386 break;
20387
20388 while (i-- > 0)
20389 if (oheaders[i]->sh_type == SHT_PROGBITS
20390 && (oheaders[i]->sh_flags & (SHF_ALLOC | SHF_EXECINSTR))
20391 == (SHF_ALLOC | SHF_EXECINSTR))
20392 break;
20393 }
20394
20395 if (i)
20396 {
20397 osection->sh_link = i;
20398 /* If the text section was part of a group
20399 then the index section should be too. */
20400 if (oheaders[i]->sh_flags & SHF_GROUP)
20401 osection->sh_flags |= SHF_GROUP;
20402 return TRUE;
20403 }
20404 }
20405 break;
20406
20407 case SHT_ARM_PREEMPTMAP:
20408 osection->sh_flags = SHF_ALLOC;
20409 break;
20410
20411 case SHT_ARM_ATTRIBUTES:
20412 case SHT_ARM_DEBUGOVERLAY:
20413 case SHT_ARM_OVERLAYSECTION:
20414 default:
20415 break;
20416 }
20417
20418 return FALSE;
20419}
20420
d691934d
NC		 20421/* Returns TRUE if NAME is an ARM mapping symbol.
20422 Traditionally the symbols $a, $d and $t have been used.
20423 The ARM ELF standard also defines $x (for A64 code). It also allows a
20424 period initiated suffix to be added to the symbol: "$[adtx]\.[:sym_char]+".
20425 Other tools might also produce $b (Thumb BL), $f, $p, $m and $v, but we do
20426 not support them here. $t.x indicates the start of ThumbEE instructions. */
20427
20428static bfd_boolean
20429is_arm_mapping_symbol (const char * name)
20430{
20431 return name != NULL /* Paranoia. */
20432 && name[0] == '$' /* Note: if objcopy --prefix-symbols has been used then
20433 the mapping symbols could have acquired a prefix.
20434 We do not support this here, since such symbols no
20435 longer conform to the ARM ELF ABI. */
20436 && (name[1] == 'a' || name[1] == 'd' || name[1] == 't' || name[1] == 'x')
20437 && (name[2] == 0 || name[2] == '.');
20438 /* FIXME: Strictly speaking the symbol is only a valid mapping symbol if
20439 any characters that follow the period are legal characters for the body
20440 of a symbol's name. For now we just assume that this is the case. */
20441}
20442
fca2a38f
NC		 20443/* Make sure that mapping symbols in object files are not removed via the
20444 "strip --strip-unneeded" tool. These symbols are needed in order to
20445 correctly generate interworking veneers, and for byte swapping code
20446 regions. Once an object file has been linked, it is safe to remove the
20447 symbols as they will no longer be needed. */
20448
20449static void
20450elf32_arm_backend_symbol_processing (bfd *abfd, asymbol *sym)
20451{
20452 if (((abfd->flags & (EXEC_P | DYNAMIC)) == 0)
fca2a38f 20453 && sym->section != bfd_abs_section_ptr
d691934d 20454 && is_arm_mapping_symbol (sym->name))
fca2a38f
NC		 20455 sym->flags |= BSF_KEEP;
20456}
20457
5522f910
NC		 20458#undef elf_backend_copy_special_section_fields
20459#define elf_backend_copy_special_section_fields elf32_arm_copy_special_section_fields
20460
252b5132 20461#define ELF_ARCH bfd_arch_arm
ae95ffa6 20462#define ELF_TARGET_ID ARM_ELF_DATA
252b5132 20463#define ELF_MACHINE_CODE EM_ARM
d0facd1b
NC		 20464#ifdef __QNXTARGET__
20465#define ELF_MAXPAGESIZE 0x1000
20466#else
7572ca89 20467#define ELF_MAXPAGESIZE 0x10000
d0facd1b 20468#endif
b1342370 20469#define ELF_MINPAGESIZE 0x1000
24718e3b 20470#define ELF_COMMONPAGESIZE 0x1000
252b5132 20471
07d6d2b8 20472#define bfd_elf32_mkobject elf32_arm_mkobject
ba93b8ac 20473
99e4ae17
AJ		 20474#define bfd_elf32_bfd_copy_private_bfd_data elf32_arm_copy_private_bfd_data
20475#define bfd_elf32_bfd_merge_private_bfd_data elf32_arm_merge_private_bfd_data
252b5132
RH		 20476#define bfd_elf32_bfd_set_private_flags elf32_arm_set_private_flags
20477#define bfd_elf32_bfd_print_private_bfd_data elf32_arm_print_private_bfd_data
07d6d2b8 20478#define bfd_elf32_bfd_link_hash_table_create elf32_arm_link_hash_table_create
dc810e39 20479#define bfd_elf32_bfd_reloc_type_lookup elf32_arm_reloc_type_lookup
b38cadfb 20480#define bfd_elf32_bfd_reloc_name_lookup elf32_arm_reloc_name_lookup
07d6d2b8
AM		 20481#define bfd_elf32_find_nearest_line elf32_arm_find_nearest_line
20482#define bfd_elf32_find_inliner_info elf32_arm_find_inliner_info
e489d0ae 20483#define bfd_elf32_new_section_hook elf32_arm_new_section_hook
3c9458e9 20484#define bfd_elf32_bfd_is_target_special_symbol elf32_arm_is_target_special_symbol
3e6b1042 20485#define bfd_elf32_bfd_final_link elf32_arm_final_link
07d6d2b8 20486#define bfd_elf32_get_synthetic_symtab elf32_arm_get_synthetic_symtab
252b5132 20487
07d6d2b8
AM		 20488#define elf_backend_get_symbol_type elf32_arm_get_symbol_type
20489#define elf_backend_gc_mark_hook elf32_arm_gc_mark_hook
6a5bb875 20490#define elf_backend_gc_mark_extra_sections elf32_arm_gc_mark_extra_sections
07d6d2b8 20491#define elf_backend_check_relocs elf32_arm_check_relocs
9eaff861 20492#define elf_backend_update_relocs elf32_arm_update_relocs
dc810e39 20493#define elf_backend_relocate_section elf32_arm_relocate_section
e489d0ae 20494#define elf_backend_write_section elf32_arm_write_section
252b5132 20495#define elf_backend_adjust_dynamic_symbol elf32_arm_adjust_dynamic_symbol
07d6d2b8 20496#define elf_backend_create_dynamic_sections elf32_arm_create_dynamic_sections
252b5132
RH		 20497#define elf_backend_finish_dynamic_symbol elf32_arm_finish_dynamic_symbol
20498#define elf_backend_finish_dynamic_sections elf32_arm_finish_dynamic_sections
20499#define elf_backend_size_dynamic_sections elf32_arm_size_dynamic_sections
0855e32b 20500#define elf_backend_always_size_sections elf32_arm_always_size_sections
74541ad4 20501#define elf_backend_init_index_section _bfd_elf_init_2_index_sections
ba96a88f 20502#define elf_backend_post_process_headers elf32_arm_post_process_headers
99e4ae17 20503#define elf_backend_reloc_type_class elf32_arm_reloc_type_class
c178919b 20504#define elf_backend_object_p elf32_arm_object_p
07d6d2b8
AM		 20505#define elf_backend_fake_sections elf32_arm_fake_sections
20506#define elf_backend_section_from_shdr elf32_arm_section_from_shdr
20507#define elf_backend_final_write_processing elf32_arm_final_write_processing
20508#define elf_backend_copy_indirect_symbol elf32_arm_copy_indirect_symbol
0beaef2b 20509#define elf_backend_size_info elf32_arm_size_info
b294bdf8 20510#define elf_backend_modify_segment_map elf32_arm_modify_segment_map
07d6d2b8
AM		 20511#define elf_backend_additional_program_headers elf32_arm_additional_program_headers
20512#define elf_backend_output_arch_local_syms elf32_arm_output_arch_local_syms
54ddd295 20513#define elf_backend_filter_implib_symbols elf32_arm_filter_implib_symbols
07d6d2b8 20514#define elf_backend_begin_write_processing elf32_arm_begin_write_processing
34e77a92 20515#define elf_backend_add_symbol_hook elf32_arm_add_symbol_hook
491d01d3 20516#define elf_backend_count_additional_relocs elf32_arm_count_additional_relocs
fca2a38f 20517#define elf_backend_symbol_processing elf32_arm_backend_symbol_processing
906e58ca
NC		 20518
20519#define elf_backend_can_refcount 1
20520#define elf_backend_can_gc_sections 1
20521#define elf_backend_plt_readonly 1
20522#define elf_backend_want_got_plt 1
20523#define elf_backend_want_plt_sym 0
5474d94f 20524#define elf_backend_want_dynrelro 1
906e58ca
NC		 20525#define elf_backend_may_use_rel_p 1
20526#define elf_backend_may_use_rela_p 0
4e7fd91e 20527#define elf_backend_default_use_rela_p 0
64f52338 20528#define elf_backend_dtrel_excludes_plt 1
252b5132 20529
04f7c78d 20530#define elf_backend_got_header_size 12
b68a20d6 20531#define elf_backend_extern_protected_data 1
04f7c78d 20532
07d6d2b8 20533#undef elf_backend_obj_attrs_vendor
906e58ca 20534#define elf_backend_obj_attrs_vendor "aeabi"
07d6d2b8 20535#undef elf_backend_obj_attrs_section
906e58ca 20536#define elf_backend_obj_attrs_section ".ARM.attributes"
07d6d2b8 20537#undef elf_backend_obj_attrs_arg_type
906e58ca 20538#define elf_backend_obj_attrs_arg_type elf32_arm_obj_attrs_arg_type
07d6d2b8 20539#undef elf_backend_obj_attrs_section_type
104d59d1 20540#define elf_backend_obj_attrs_section_type SHT_ARM_ATTRIBUTES
b38cadfb 20541#define elf_backend_obj_attrs_order elf32_arm_obj_attrs_order
07d6d2b8 20542#define elf_backend_obj_attrs_handle_unknown elf32_arm_obj_attrs_handle_unknown
104d59d1 20543
07d6d2b8 20544#undef elf_backend_section_flags
ac4c9b04 20545#define elf_backend_section_flags elf32_arm_section_flags
07d6d2b8
AM		 20546#undef elf_backend_lookup_section_flags_hook
20547#define elf_backend_lookup_section_flags_hook elf32_arm_lookup_section_flags
ac4c9b04 20548
a2f63b2e
MR		 20549#define elf_backend_linux_prpsinfo32_ugid16 TRUE
20550
252b5132 20551#include "elf32-target.h"
7f266840 20552
b38cadfb
NC		 20553/* Native Client targets. */
20554
20555#undef TARGET_LITTLE_SYM
6d00b590 20556#define TARGET_LITTLE_SYM arm_elf32_nacl_le_vec
b38cadfb
NC		 20557#undef TARGET_LITTLE_NAME
20558#define TARGET_LITTLE_NAME "elf32-littlearm-nacl"
20559#undef TARGET_BIG_SYM
6d00b590 20560#define TARGET_BIG_SYM arm_elf32_nacl_be_vec
b38cadfb
NC		 20561#undef TARGET_BIG_NAME
20562#define TARGET_BIG_NAME "elf32-bigarm-nacl"
20563
20564/* Like elf32_arm_link_hash_table_create -- but overrides
20565 appropriately for NaCl. */
20566
20567static struct bfd_link_hash_table *
20568elf32_arm_nacl_link_hash_table_create (bfd *abfd)
20569{
20570 struct bfd_link_hash_table *ret;
20571
20572 ret = elf32_arm_link_hash_table_create (abfd);
20573 if (ret)
20574 {
20575 struct elf32_arm_link_hash_table *htab
20576 = (struct elf32_arm_link_hash_table *) ret;
20577
20578 htab->nacl_p = 1;
20579
20580 htab->plt_header_size = 4 * ARRAY_SIZE (elf32_arm_nacl_plt0_entry);
20581 htab->plt_entry_size = 4 * ARRAY_SIZE (elf32_arm_nacl_plt_entry);
20582 }
20583 return ret;
20584}
20585
20586/* Since NaCl doesn't use the ARM-specific unwind format, we don't
20587 really need to use elf32_arm_modify_segment_map. But we do it
20588 anyway just to reduce gratuitous differences with the stock ARM backend. */
20589
20590static bfd_boolean
20591elf32_arm_nacl_modify_segment_map (bfd *abfd, struct bfd_link_info *info)
20592{
20593 return (elf32_arm_modify_segment_map (abfd, info)
20594 && nacl_modify_segment_map (abfd, info));
20595}
20596
cc364be6
AM		 20597static bfd_boolean
20598elf32_arm_nacl_final_write_processing (bfd *abfd)
887badb3 20599{
cc364be6
AM		 20600 arm_final_write_processing (abfd);
20601 return nacl_final_write_processing (abfd);
887badb3
RM		 20602}
20603
6a631e86
YG		 20604static bfd_vma
20605elf32_arm_nacl_plt_sym_val (bfd_vma i, const asection *plt,
20606 const arelent *rel ATTRIBUTE_UNUSED)
20607{
20608 return plt->vma
20609 + 4 * (ARRAY_SIZE (elf32_arm_nacl_plt0_entry) +
20610 i * ARRAY_SIZE (elf32_arm_nacl_plt_entry));
20611}
887badb3 20612
b38cadfb 20613#undef elf32_bed
6a631e86 20614#define elf32_bed elf32_arm_nacl_bed
b38cadfb
NC		 20615#undef bfd_elf32_bfd_link_hash_table_create
20616#define bfd_elf32_bfd_link_hash_table_create \
20617 elf32_arm_nacl_link_hash_table_create
20618#undef elf_backend_plt_alignment
6a631e86 20619#define elf_backend_plt_alignment 4
b38cadfb
NC		 20620#undef elf_backend_modify_segment_map
20621#define elf_backend_modify_segment_map elf32_arm_nacl_modify_segment_map
20622#undef elf_backend_modify_program_headers
20623#define elf_backend_modify_program_headers nacl_modify_program_headers
887badb3
RM		 20624#undef elf_backend_final_write_processing
20625#define elf_backend_final_write_processing elf32_arm_nacl_final_write_processing
6a631e86
YG		 20626#undef bfd_elf32_get_synthetic_symtab
20627#undef elf_backend_plt_sym_val
20628#define elf_backend_plt_sym_val elf32_arm_nacl_plt_sym_val
5522f910 20629#undef elf_backend_copy_special_section_fields
b38cadfb 20630
887badb3
RM		 20631#undef ELF_MINPAGESIZE
20632#undef ELF_COMMONPAGESIZE
20633
b38cadfb
NC		 20634
20635#include "elf32-target.h"
20636
20637/* Reset to defaults. */
20638#undef elf_backend_plt_alignment
20639#undef elf_backend_modify_segment_map
20640#define elf_backend_modify_segment_map elf32_arm_modify_segment_map
20641#undef elf_backend_modify_program_headers
887badb3
RM		 20642#undef elf_backend_final_write_processing
20643#define elf_backend_final_write_processing elf32_arm_final_write_processing
20644#undef ELF_MINPAGESIZE
20645#define ELF_MINPAGESIZE 0x1000
20646#undef ELF_COMMONPAGESIZE
20647#define ELF_COMMONPAGESIZE 0x1000
20648
b38cadfb 20649
617a5ada
CL		 20650/* FDPIC Targets. */
20651
20652#undef TARGET_LITTLE_SYM
20653#define TARGET_LITTLE_SYM arm_elf32_fdpic_le_vec
20654#undef TARGET_LITTLE_NAME
20655#define TARGET_LITTLE_NAME "elf32-littlearm-fdpic"
20656#undef TARGET_BIG_SYM
20657#define TARGET_BIG_SYM arm_elf32_fdpic_be_vec
20658#undef TARGET_BIG_NAME
20659#define TARGET_BIG_NAME "elf32-bigarm-fdpic"
20660#undef elf_match_priority
20661#define elf_match_priority 128
18a20338
CL		 20662#undef ELF_OSABI
20663#define ELF_OSABI ELFOSABI_ARM_FDPIC
617a5ada
CL		 20664
20665/* Like elf32_arm_link_hash_table_create -- but overrides
20666 appropriately for FDPIC. */
20667
20668static struct bfd_link_hash_table *
20669elf32_arm_fdpic_link_hash_table_create (bfd *abfd)
20670{
20671 struct bfd_link_hash_table *ret;
20672
20673 ret = elf32_arm_link_hash_table_create (abfd);
20674 if (ret)
20675 {
20676 struct elf32_arm_link_hash_table *htab = (struct elf32_arm_link_hash_table *) ret;
20677
20678 htab->fdpic_p = 1;
20679 }
20680 return ret;
20681}
20682
e8b09b87
CL		 20683/* We need dynamic symbols for every section, since segments can
20684 relocate independently. */
20685static bfd_boolean
20686elf32_arm_fdpic_omit_section_dynsym (bfd *output_bfd ATTRIBUTE_UNUSED,
20687 struct bfd_link_info *info
20688 ATTRIBUTE_UNUSED,
20689 asection *p ATTRIBUTE_UNUSED)
20690{
20691 switch (elf_section_data (p)->this_hdr.sh_type)
20692 {
20693 case SHT_PROGBITS:
20694 case SHT_NOBITS:
20695 /* If sh_type is yet undecided, assume it could be
20696 SHT_PROGBITS/SHT_NOBITS. */
20697 case SHT_NULL:
20698 return FALSE;
20699
20700 /* There shouldn't be section relative relocations
20701 against any other section. */
20702 default:
20703 return TRUE;
20704 }
20705}
20706
617a5ada
CL		 20707#undef elf32_bed
20708#define elf32_bed elf32_arm_fdpic_bed
20709
20710#undef bfd_elf32_bfd_link_hash_table_create
4b24dd1a 20711#define bfd_elf32_bfd_link_hash_table_create elf32_arm_fdpic_link_hash_table_create
617a5ada 20712
e8b09b87
CL		 20713#undef elf_backend_omit_section_dynsym
20714#define elf_backend_omit_section_dynsym elf32_arm_fdpic_omit_section_dynsym
20715
617a5ada 20716#include "elf32-target.h"
e8b09b87 20717
617a5ada 20718#undef elf_match_priority
18a20338 20719#undef ELF_OSABI
e8b09b87 20720#undef elf_backend_omit_section_dynsym
617a5ada 20721
906e58ca 20722/* VxWorks Targets. */
4e7fd91e 20723
07d6d2b8
AM		 20724#undef TARGET_LITTLE_SYM
20725#define TARGET_LITTLE_SYM arm_elf32_vxworks_le_vec
20726#undef TARGET_LITTLE_NAME
20727#define TARGET_LITTLE_NAME "elf32-littlearm-vxworks"
20728#undef TARGET_BIG_SYM
20729#define TARGET_BIG_SYM arm_elf32_vxworks_be_vec
20730#undef TARGET_BIG_NAME
20731#define TARGET_BIG_NAME "elf32-bigarm-vxworks"
4e7fd91e
PB		 20732
20733/* Like elf32_arm_link_hash_table_create -- but overrides
20734 appropriately for VxWorks. */
906e58ca 20735
4e7fd91e
PB		 20736static struct bfd_link_hash_table *
20737elf32_arm_vxworks_link_hash_table_create (bfd *abfd)
20738{
20739 struct bfd_link_hash_table *ret;
20740
20741 ret = elf32_arm_link_hash_table_create (abfd);
20742 if (ret)
20743 {
20744 struct elf32_arm_link_hash_table *htab
00a97672 20745 = (struct elf32_arm_link_hash_table *) ret;
4e7fd91e 20746 htab->use_rel = 0;
00a97672 20747 htab->vxworks_p = 1;
4e7fd91e
PB		 20748 }
20749 return ret;
906e58ca 20750}
4e7fd91e 20751
cc364be6
AM		 20752static bfd_boolean
20753elf32_arm_vxworks_final_write_processing (bfd *abfd)
00a97672 20754{
cc364be6
AM		 20755 arm_final_write_processing (abfd);
20756 return elf_vxworks_final_write_processing (abfd);
00a97672
RS		 20757}
20758
906e58ca 20759#undef elf32_bed
4e7fd91e
PB		 20760#define elf32_bed elf32_arm_vxworks_bed
20761
906e58ca
NC		 20762#undef bfd_elf32_bfd_link_hash_table_create
20763#define bfd_elf32_bfd_link_hash_table_create elf32_arm_vxworks_link_hash_table_create
906e58ca
NC		 20764#undef elf_backend_final_write_processing
20765#define elf_backend_final_write_processing elf32_arm_vxworks_final_write_processing
20766#undef elf_backend_emit_relocs
9eaff861 20767#define elf_backend_emit_relocs elf_vxworks_emit_relocs
4e7fd91e 20768
906e58ca 20769#undef elf_backend_may_use_rel_p
00a97672 20770#define elf_backend_may_use_rel_p 0
906e58ca 20771#undef elf_backend_may_use_rela_p
00a97672 20772#define elf_backend_may_use_rela_p 1
906e58ca 20773#undef elf_backend_default_use_rela_p
00a97672 20774#define elf_backend_default_use_rela_p 1
906e58ca 20775#undef elf_backend_want_plt_sym
00a97672 20776#define elf_backend_want_plt_sym 1
906e58ca 20777#undef ELF_MAXPAGESIZE
00a97672 20778#define ELF_MAXPAGESIZE 0x1000
4e7fd91e
PB		 20779
20780#include "elf32-target.h"
20781
20782
21d799b5
NC		 20783/* Merge backend specific data from an object file to the output
20784 object file when linking. */
20785
20786static bfd_boolean
50e03d47 20787elf32_arm_merge_private_bfd_data (bfd *ibfd, struct bfd_link_info *info)
21d799b5 20788{
50e03d47 20789 bfd *obfd = info->output_bfd;
21d799b5
NC		 20790 flagword out_flags;
20791 flagword in_flags;
20792 bfd_boolean flags_compatible = TRUE;
20793 asection *sec;
20794
cc643b88 20795 /* Check if we have the same endianness. */
50e03d47 20796 if (! _bfd_generic_verify_endian_match (ibfd, info))
21d799b5
NC		 20797 return FALSE;
20798
20799 if (! is_arm_elf (ibfd) || ! is_arm_elf (obfd))
20800 return TRUE;
20801
50e03d47 20802 if (!elf32_arm_merge_eabi_attributes (ibfd, info))
21d799b5
NC		 20803 return FALSE;
20804
20805 /* The input BFD must have had its flags initialised. */
20806 /* The following seems bogus to me -- The flags are initialized in
20807 the assembler but I don't think an elf_flags_init field is
20808 written into the object. */
20809 /* BFD_ASSERT (elf_flags_init (ibfd)); */
20810
20811 in_flags = elf_elfheader (ibfd)->e_flags;
20812 out_flags = elf_elfheader (obfd)->e_flags;
20813
20814 /* In theory there is no reason why we couldn't handle this. However
20815 in practice it isn't even close to working and there is no real
20816 reason to want it. */
20817 if (EF_ARM_EABI_VERSION (in_flags) >= EF_ARM_EABI_VER4
20818 && !(ibfd->flags & DYNAMIC)
20819 && (in_flags & EF_ARM_BE8))
20820 {
871b3ab2 20821 _bfd_error_handler (_("error: %pB is already in final BE8 format"),
21d799b5
NC		 20822 ibfd);
20823 return FALSE;
20824 }
20825
20826 if (!elf_flags_init (obfd))
20827 {
20828 /* If the input is the default architecture and had the default
20829 flags then do not bother setting the flags for the output
20830 architecture, instead allow future merges to do this. If no
20831 future merges ever set these flags then they will retain their
99059e56
RM		 20832 uninitialised values, which surprise surprise, correspond
20833 to the default values. */
21d799b5
NC		 20834 if (bfd_get_arch_info (ibfd)->the_default
20835 && elf_elfheader (ibfd)->e_flags == 0)
20836 return TRUE;
20837
20838 elf_flags_init (obfd) = TRUE;
20839 elf_elfheader (obfd)->e_flags = in_flags;
20840
20841 if (bfd_get_arch (obfd) == bfd_get_arch (ibfd)
20842 && bfd_get_arch_info (obfd)->the_default)
20843 return bfd_set_arch_mach (obfd, bfd_get_arch (ibfd), bfd_get_mach (ibfd));
20844
20845 return TRUE;
20846 }
20847
20848 /* Determine what should happen if the input ARM architecture
20849 does not match the output ARM architecture. */
20850 if (! bfd_arm_merge_machines (ibfd, obfd))
20851 return FALSE;
20852
20853 /* Identical flags must be compatible. */
20854 if (in_flags == out_flags)
20855 return TRUE;
20856
20857 /* Check to see if the input BFD actually contains any sections. If
20858 not, its flags may not have been initialised either, but it
20859 cannot actually cause any incompatiblity. Do not short-circuit
20860 dynamic objects; their section list may be emptied by
20861 elf_link_add_object_symbols.
20862
20863 Also check to see if there are no code sections in the input.
20864 In this case there is no need to check for code specific flags.
20865 XXX - do we need to worry about floating-point format compatability
20866 in data sections ? */
20867 if (!(ibfd->flags & DYNAMIC))
20868 {
20869 bfd_boolean null_input_bfd = TRUE;
20870 bfd_boolean only_data_sections = TRUE;
20871
20872 for (sec = ibfd->sections; sec != NULL; sec = sec->next)
20873 {
20874 /* Ignore synthetic glue sections. */
20875 if (strcmp (sec->name, ".glue_7")
20876 && strcmp (sec->name, ".glue_7t"))
20877 {
fd361982 20878 if ((bfd_section_flags (sec)
21d799b5
NC		 20879 & (SEC_LOAD | SEC_CODE | SEC_HAS_CONTENTS))
20880 == (SEC_LOAD | SEC_CODE | SEC_HAS_CONTENTS))
99059e56 20881 only_data_sections = FALSE;
21d799b5
NC		 20882
20883 null_input_bfd = FALSE;
20884 break;
20885 }
20886 }
20887
20888 if (null_input_bfd || only_data_sections)
20889 return TRUE;
20890 }
20891
20892 /* Complain about various flag mismatches. */
20893 if (!elf32_arm_versions_compatible (EF_ARM_EABI_VERSION (in_flags),
20894 EF_ARM_EABI_VERSION (out_flags)))
20895 {
20896 _bfd_error_handler
90b6238f 20897 (_("error: source object %pB has EABI version %d, but target %pB has EABI version %d"),
c08bb8dd
AM		 20898 ibfd, (in_flags & EF_ARM_EABIMASK) >> 24,
20899 obfd, (out_flags & EF_ARM_EABIMASK) >> 24);
21d799b5
NC		 20900 return FALSE;
20901 }
20902
20903 /* Not sure what needs to be checked for EABI versions >= 1. */
20904 /* VxWorks libraries do not use these flags. */
20905 if (get_elf_backend_data (obfd) != &elf32_arm_vxworks_bed
20906 && get_elf_backend_data (ibfd) != &elf32_arm_vxworks_bed
20907 && EF_ARM_EABI_VERSION (in_flags) == EF_ARM_EABI_UNKNOWN)
20908 {
20909 if ((in_flags & EF_ARM_APCS_26) != (out_flags & EF_ARM_APCS_26))
20910 {
20911 _bfd_error_handler
871b3ab2 20912 (_("error: %pB is compiled for APCS-%d, whereas target %pB uses APCS-%d"),
c08bb8dd
AM		 20913 ibfd, in_flags & EF_ARM_APCS_26 ? 26 : 32,
20914 obfd, out_flags & EF_ARM_APCS_26 ? 26 : 32);
21d799b5
NC		 20915 flags_compatible = FALSE;
20916 }
20917
20918 if ((in_flags & EF_ARM_APCS_FLOAT) != (out_flags & EF_ARM_APCS_FLOAT))
20919 {
20920 if (in_flags & EF_ARM_APCS_FLOAT)
20921 _bfd_error_handler
871b3ab2 20922 (_("error: %pB passes floats in float registers, whereas %pB passes them in integer registers"),
21d799b5
NC		 20923 ibfd, obfd);
20924 else
20925 _bfd_error_handler
871b3ab2 20926 (_("error: %pB passes floats in integer registers, whereas %pB passes them in float registers"),
21d799b5
NC		 20927 ibfd, obfd);
20928
20929 flags_compatible = FALSE;
20930 }
20931
20932 if ((in_flags & EF_ARM_VFP_FLOAT) != (out_flags & EF_ARM_VFP_FLOAT))
20933 {
20934 if (in_flags & EF_ARM_VFP_FLOAT)
20935 _bfd_error_handler
90b6238f
AM		 20936 (_("error: %pB uses %s instructions, whereas %pB does not"),
20937 ibfd, "VFP", obfd);
21d799b5
NC		 20938 else
20939 _bfd_error_handler
90b6238f
AM		 20940 (_("error: %pB uses %s instructions, whereas %pB does not"),
20941 ibfd, "FPA", obfd);
21d799b5
NC		 20942
20943 flags_compatible = FALSE;
20944 }
20945
20946 if ((in_flags & EF_ARM_MAVERICK_FLOAT) != (out_flags & EF_ARM_MAVERICK_FLOAT))
20947 {
20948 if (in_flags & EF_ARM_MAVERICK_FLOAT)
20949 _bfd_error_handler
90b6238f
AM		 20950 (_("error: %pB uses %s instructions, whereas %pB does not"),
20951 ibfd, "Maverick", obfd);
21d799b5
NC		 20952 else
20953 _bfd_error_handler
90b6238f
AM		 20954 (_("error: %pB does not use %s instructions, whereas %pB does"),
20955 ibfd, "Maverick", obfd);
21d799b5
NC		 20956
20957 flags_compatible = FALSE;
20958 }
20959
20960#ifdef EF_ARM_SOFT_FLOAT
20961 if ((in_flags & EF_ARM_SOFT_FLOAT) != (out_flags & EF_ARM_SOFT_FLOAT))
20962 {
20963 /* We can allow interworking between code that is VFP format
20964 layout, and uses either soft float or integer regs for
20965 passing floating point arguments and results. We already
20966 know that the APCS_FLOAT flags match; similarly for VFP
20967 flags. */
20968 if ((in_flags & EF_ARM_APCS_FLOAT) != 0
20969 || (in_flags & EF_ARM_VFP_FLOAT) == 0)
20970 {
20971 if (in_flags & EF_ARM_SOFT_FLOAT)
20972 _bfd_error_handler
871b3ab2 20973 (_("error: %pB uses software FP, whereas %pB uses hardware FP"),
21d799b5
NC		 20974 ibfd, obfd);
20975 else
20976 _bfd_error_handler
871b3ab2 20977 (_("error: %pB uses hardware FP, whereas %pB uses software FP"),
21d799b5
NC		 20978 ibfd, obfd);
20979
20980 flags_compatible = FALSE;
20981 }
20982 }
20983#endif
20984
20985 /* Interworking mismatch is only a warning. */
20986 if ((in_flags & EF_ARM_INTERWORK) != (out_flags & EF_ARM_INTERWORK))
20987 {
20988 if (in_flags & EF_ARM_INTERWORK)
20989 {
20990 _bfd_error_handler
90b6238f 20991 (_("warning: %pB supports interworking, whereas %pB does not"),
21d799b5
NC		 20992 ibfd, obfd);
20993 }
20994 else
20995 {
20996 _bfd_error_handler
90b6238f 20997 (_("warning: %pB does not support interworking, whereas %pB does"),
21d799b5
NC		 20998 ibfd, obfd);
20999 }
21000 }
21001 }
21002
21003 return flags_compatible;
21004}
21005
21006
906e58ca 21007/* Symbian OS Targets. */
7f266840 21008
07d6d2b8
AM		 21009#undef TARGET_LITTLE_SYM
21010#define TARGET_LITTLE_SYM arm_elf32_symbian_le_vec
21011#undef TARGET_LITTLE_NAME
21012#define TARGET_LITTLE_NAME "elf32-littlearm-symbian"
21013#undef TARGET_BIG_SYM
21014#define TARGET_BIG_SYM arm_elf32_symbian_be_vec
21015#undef TARGET_BIG_NAME
21016#define TARGET_BIG_NAME "elf32-bigarm-symbian"
7f266840
DJ		 21017
21018/* Like elf32_arm_link_hash_table_create -- but overrides
21019 appropriately for Symbian OS. */
906e58ca 21020
7f266840
DJ		 21021static struct bfd_link_hash_table *
21022elf32_arm_symbian_link_hash_table_create (bfd *abfd)
21023{
21024 struct bfd_link_hash_table *ret;
21025
21026 ret = elf32_arm_link_hash_table_create (abfd);
21027 if (ret)
21028 {
21029 struct elf32_arm_link_hash_table *htab
21030 = (struct elf32_arm_link_hash_table *)ret;
21031 /* There is no PLT header for Symbian OS. */
21032 htab->plt_header_size = 0;
95720a86
DJ		 21033 /* The PLT entries are each one instruction and one word. */
21034 htab->plt_entry_size = 4 * ARRAY_SIZE (elf32_arm_symbian_plt_entry);
7f266840 21035 htab->symbian_p = 1;
33bfe774
JB		 21036 /* Symbian uses armv5t or above, so use_blx is always true. */
21037 htab->use_blx = 1;
67687978 21038 htab->root.is_relocatable_executable = 1;
7f266840
DJ		 21039 }
21040 return ret;
906e58ca 21041}
7f266840 21042
b35d266b 21043static const struct bfd_elf_special_section
551b43fd 21044elf32_arm_symbian_special_sections[] =
7f266840 21045{
5cd3778d
MM		 21046 /* In a BPABI executable, the dynamic linking sections do not go in
21047 the loadable read-only segment. The post-linker may wish to
21048 refer to these sections, but they are not part of the final
21049 program image. */
07d6d2b8
AM		 21050 { STRING_COMMA_LEN (".dynamic"), 0, SHT_DYNAMIC, 0 },
21051 { STRING_COMMA_LEN (".dynstr"), 0, SHT_STRTAB, 0 },
21052 { STRING_COMMA_LEN (".dynsym"), 0, SHT_DYNSYM, 0 },
21053 { STRING_COMMA_LEN (".got"), 0, SHT_PROGBITS, 0 },
21054 { STRING_COMMA_LEN (".hash"), 0, SHT_HASH, 0 },
5cd3778d
MM		 21055 /* These sections do not need to be writable as the SymbianOS
21056 postlinker will arrange things so that no dynamic relocation is
21057 required. */
07d6d2b8
AM		 21058 { STRING_COMMA_LEN (".init_array"), 0, SHT_INIT_ARRAY, SHF_ALLOC },
21059 { STRING_COMMA_LEN (".fini_array"), 0, SHT_FINI_ARRAY, SHF_ALLOC },
0112cd26 21060 { STRING_COMMA_LEN (".preinit_array"), 0, SHT_PREINIT_ARRAY, SHF_ALLOC },
07d6d2b8 21061 { NULL, 0, 0, 0, 0 }
7f266840
DJ		 21062};
21063
c3c76620 21064static void
906e58ca 21065elf32_arm_symbian_begin_write_processing (bfd *abfd,
a4fd1a8e 21066 struct bfd_link_info *link_info)
c3c76620
MM		 21067{
21068 /* BPABI objects are never loaded directly by an OS kernel; they are
21069 processed by a postlinker first, into an OS-specific format. If
21070 the D_PAGED bit is set on the file, BFD will align segments on
21071 page boundaries, so that an OS can directly map the file. With
21072 BPABI objects, that just results in wasted space. In addition,
21073 because we clear the D_PAGED bit, map_sections_to_segments will
21074 recognize that the program headers should not be mapped into any
21075 loadable segment. */
21076 abfd->flags &= ~D_PAGED;
906e58ca 21077 elf32_arm_begin_write_processing (abfd, link_info);
c3c76620 21078}
7f266840
DJ		 21079
21080static bfd_boolean
906e58ca 21081elf32_arm_symbian_modify_segment_map (bfd *abfd,
b294bdf8 21082 struct bfd_link_info *info)
7f266840
DJ		 21083{
21084 struct elf_segment_map *m;
21085 asection *dynsec;
21086
7f266840
DJ		 21087 /* BPABI shared libraries and executables should have a PT_DYNAMIC
21088 segment. However, because the .dynamic section is not marked
21089 with SEC_LOAD, the generic ELF code will not create such a
21090 segment. */
21091 dynsec = bfd_get_section_by_name (abfd, ".dynamic");
21092 if (dynsec)
21093 {
12bd6957 21094 for (m = elf_seg_map (abfd); m != NULL; m = m->next)
8ded5a0f
AM		 21095 if (m->p_type == PT_DYNAMIC)
21096 break;
21097
21098 if (m == NULL)
21099 {
21100 m = _bfd_elf_make_dynamic_segment (abfd, dynsec);
12bd6957
AM		 21101 m->next = elf_seg_map (abfd);
21102 elf_seg_map (abfd) = m;
8ded5a0f 21103 }
7f266840
DJ		 21104 }
21105
b294bdf8
MM		 21106 /* Also call the generic arm routine. */
21107 return elf32_arm_modify_segment_map (abfd, info);
7f266840
DJ		 21108}
21109
95720a86
DJ		 21110/* Return address for Ith PLT stub in section PLT, for relocation REL
21111 or (bfd_vma) -1 if it should not be included. */
21112
21113static bfd_vma
21114elf32_arm_symbian_plt_sym_val (bfd_vma i, const asection *plt,
21115 const arelent *rel ATTRIBUTE_UNUSED)
21116{
21117 return plt->vma + 4 * ARRAY_SIZE (elf32_arm_symbian_plt_entry) * i;
21118}
21119
8029a119 21120#undef elf32_bed
7f266840
DJ		 21121#define elf32_bed elf32_arm_symbian_bed
21122
21123/* The dynamic sections are not allocated on SymbianOS; the postlinker
21124 will process them and then discard them. */
906e58ca 21125#undef ELF_DYNAMIC_SEC_FLAGS
7f266840
DJ		 21126#define ELF_DYNAMIC_SEC_FLAGS \
21127 (SEC_HAS_CONTENTS | SEC_IN_MEMORY | SEC_LINKER_CREATED)
21128
9eaff861 21129#undef elf_backend_emit_relocs
c3c76620 21130
906e58ca
NC		 21131#undef bfd_elf32_bfd_link_hash_table_create
21132#define bfd_elf32_bfd_link_hash_table_create elf32_arm_symbian_link_hash_table_create
21133#undef elf_backend_special_sections
07d6d2b8 21134#define elf_backend_special_sections elf32_arm_symbian_special_sections
906e58ca
NC		 21135#undef elf_backend_begin_write_processing
21136#define elf_backend_begin_write_processing elf32_arm_symbian_begin_write_processing
21137#undef elf_backend_final_write_processing
21138#define elf_backend_final_write_processing elf32_arm_final_write_processing
21139
21140#undef elf_backend_modify_segment_map
7f266840
DJ		 21141#define elf_backend_modify_segment_map elf32_arm_symbian_modify_segment_map
21142
21143/* There is no .got section for BPABI objects, and hence no header. */
906e58ca 21144#undef elf_backend_got_header_size
7f266840
DJ		 21145#define elf_backend_got_header_size 0
21146
21147/* Similarly, there is no .got.plt section. */
906e58ca 21148#undef elf_backend_want_got_plt
7f266840
DJ		 21149#define elf_backend_want_got_plt 0
21150
906e58ca 21151#undef elf_backend_plt_sym_val
95720a86
DJ		 21152#define elf_backend_plt_sym_val elf32_arm_symbian_plt_sym_val
21153
906e58ca 21154#undef elf_backend_may_use_rel_p
00a97672 21155#define elf_backend_may_use_rel_p 1
906e58ca 21156#undef elf_backend_may_use_rela_p
00a97672 21157#define elf_backend_may_use_rela_p 0
906e58ca 21158#undef elf_backend_default_use_rela_p
00a97672 21159#define elf_backend_default_use_rela_p 0
906e58ca 21160#undef elf_backend_want_plt_sym
00a97672 21161#define elf_backend_want_plt_sym 0
64f52338
AM		 21162#undef elf_backend_dtrel_excludes_plt
21163#define elf_backend_dtrel_excludes_plt 0
906e58ca 21164#undef ELF_MAXPAGESIZE
00a97672 21165#define ELF_MAXPAGESIZE 0x8000
4e7fd91e 21166
7f266840 21167#include "elf32-target.h"
GDB Binutils - Deliverables
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