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Refactor Cortex-A8 erratum workaround in preparation
[deliverable/binutils-gdb.git] / bfd / elf32-arm.c
CommitLineData
252b5132 1/* 32-bit ELF support for ARM
6f2750fe 2 Copyright (C) 1998-2016 Free Software Foundation, Inc.
252b5132
RH		 3
4 This file is part of BFD, the Binary File Descriptor library.
5
6 This program is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
cd123cb7 8 the Free Software Foundation; either version 3 of the License, or
252b5132
RH		 9 (at your option) any later version.
10
11 This program is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
15
16 You should have received a copy of the GNU General Public License
17 along with this program; if not, write to the Free Software
cd123cb7
NC		 18 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
19 MA 02110-1301, USA. */
252b5132 20
6e6718a3 21#include "sysdep.h"
2468f9c9
PB		 22#include <limits.h>
23
3db64b00 24#include "bfd.h"
6034aab8 25#include "bfd_stdint.h"
00a97672 26#include "libiberty.h"
7f266840
DJ		 27#include "libbfd.h"
28#include "elf-bfd.h"
b38cadfb 29#include "elf-nacl.h"
00a97672 30#include "elf-vxworks.h"
ee065d83 31#include "elf/arm.h"
7f266840 32
00a97672
RS		 33/* Return the relocation section associated with NAME. HTAB is the
34 bfd's elf32_arm_link_hash_entry. */
35#define RELOC_SECTION(HTAB, NAME) \
36 ((HTAB)->use_rel ? ".rel" NAME : ".rela" NAME)
37
38/* Return size of a relocation entry. HTAB is the bfd's
39 elf32_arm_link_hash_entry. */
40#define RELOC_SIZE(HTAB) \
41 ((HTAB)->use_rel \
42 ? sizeof (Elf32_External_Rel) \
43 : sizeof (Elf32_External_Rela))
44
45/* Return function to swap relocations in. HTAB is the bfd's
46 elf32_arm_link_hash_entry. */
47#define SWAP_RELOC_IN(HTAB) \
48 ((HTAB)->use_rel \
49 ? bfd_elf32_swap_reloc_in \
50 : bfd_elf32_swap_reloca_in)
51
52/* Return function to swap relocations out. HTAB is the bfd's
53 elf32_arm_link_hash_entry. */
54#define SWAP_RELOC_OUT(HTAB) \
55 ((HTAB)->use_rel \
56 ? bfd_elf32_swap_reloc_out \
57 : bfd_elf32_swap_reloca_out)
58
7f266840
DJ		 59#define elf_info_to_howto 0
60#define elf_info_to_howto_rel elf32_arm_info_to_howto
61
62#define ARM_ELF_ABI_VERSION 0
63#define ARM_ELF_OS_ABI_VERSION ELFOSABI_ARM
64
79f08007
YZ		 65/* The Adjusted Place, as defined by AAELF. */
66#define Pa(X) ((X) & 0xfffffffc)
67
3e6b1042
DJ		 68static bfd_boolean elf32_arm_write_section (bfd *output_bfd,
69 struct bfd_link_info *link_info,
70 asection *sec,
71 bfd_byte *contents);
72
7f266840
DJ		 73/* Note: code such as elf32_arm_reloc_type_lookup expect to use e.g.
74 R_ARM_PC24 as an index into this, and find the R_ARM_PC24 HOWTO
75 in that slot. */
76
c19d1205 77static reloc_howto_type elf32_arm_howto_table_1[] =
7f266840 78{
8029a119 79 /* No relocation. */
7f266840
DJ		 80 HOWTO (R_ARM_NONE, /* type */
81 0, /* rightshift */
6346d5ca 82 3, /* size (0 = byte, 1 = short, 2 = long) */
7f266840
DJ		 83 0, /* bitsize */
84 FALSE, /* pc_relative */
85 0, /* bitpos */
86 complain_overflow_dont,/* complain_on_overflow */
87 bfd_elf_generic_reloc, /* special_function */
88 "R_ARM_NONE", /* name */
89 FALSE, /* partial_inplace */
90 0, /* src_mask */
91 0, /* dst_mask */
92 FALSE), /* pcrel_offset */
93
94 HOWTO (R_ARM_PC24, /* type */
95 2, /* rightshift */
96 2, /* size (0 = byte, 1 = short, 2 = long) */
97 24, /* bitsize */
98 TRUE, /* pc_relative */
99 0, /* bitpos */
100 complain_overflow_signed,/* complain_on_overflow */
101 bfd_elf_generic_reloc, /* special_function */
102 "R_ARM_PC24", /* name */
103 FALSE, /* partial_inplace */
104 0x00ffffff, /* src_mask */
105 0x00ffffff, /* dst_mask */
106 TRUE), /* pcrel_offset */
107
108 /* 32 bit absolute */
109 HOWTO (R_ARM_ABS32, /* type */
110 0, /* rightshift */
111 2, /* size (0 = byte, 1 = short, 2 = long) */
112 32, /* bitsize */
113 FALSE, /* pc_relative */
114 0, /* bitpos */
115 complain_overflow_bitfield,/* complain_on_overflow */
116 bfd_elf_generic_reloc, /* special_function */
117 "R_ARM_ABS32", /* name */
118 FALSE, /* partial_inplace */
119 0xffffffff, /* src_mask */
120 0xffffffff, /* dst_mask */
121 FALSE), /* pcrel_offset */
122
123 /* standard 32bit pc-relative reloc */
124 HOWTO (R_ARM_REL32, /* type */
125 0, /* rightshift */
126 2, /* size (0 = byte, 1 = short, 2 = long) */
127 32, /* bitsize */
128 TRUE, /* pc_relative */
129 0, /* bitpos */
130 complain_overflow_bitfield,/* complain_on_overflow */
131 bfd_elf_generic_reloc, /* special_function */
132 "R_ARM_REL32", /* name */
133 FALSE, /* partial_inplace */
134 0xffffffff, /* src_mask */
135 0xffffffff, /* dst_mask */
136 TRUE), /* pcrel_offset */
137
c19d1205 138 /* 8 bit absolute - R_ARM_LDR_PC_G0 in AAELF */
4962c51a 139 HOWTO (R_ARM_LDR_PC_G0, /* type */
7f266840
DJ		 140 0, /* rightshift */
141 0, /* size (0 = byte, 1 = short, 2 = long) */
4962c51a
MS		 142 32, /* bitsize */
143 TRUE, /* pc_relative */
7f266840 144 0, /* bitpos */
4962c51a 145 complain_overflow_dont,/* complain_on_overflow */
7f266840 146 bfd_elf_generic_reloc, /* special_function */
4962c51a 147 "R_ARM_LDR_PC_G0", /* name */
7f266840 148 FALSE, /* partial_inplace */
4962c51a
MS		 149 0xffffffff, /* src_mask */
150 0xffffffff, /* dst_mask */
151 TRUE), /* pcrel_offset */
7f266840
DJ		 152
153 /* 16 bit absolute */
154 HOWTO (R_ARM_ABS16, /* type */
155 0, /* rightshift */
156 1, /* size (0 = byte, 1 = short, 2 = long) */
157 16, /* bitsize */
158 FALSE, /* pc_relative */
159 0, /* bitpos */
160 complain_overflow_bitfield,/* complain_on_overflow */
161 bfd_elf_generic_reloc, /* special_function */
162 "R_ARM_ABS16", /* name */
163 FALSE, /* partial_inplace */
164 0x0000ffff, /* src_mask */
165 0x0000ffff, /* dst_mask */
166 FALSE), /* pcrel_offset */
167
168 /* 12 bit absolute */
169 HOWTO (R_ARM_ABS12, /* type */
170 0, /* rightshift */
171 2, /* size (0 = byte, 1 = short, 2 = long) */
172 12, /* bitsize */
173 FALSE, /* pc_relative */
174 0, /* bitpos */
175 complain_overflow_bitfield,/* complain_on_overflow */
176 bfd_elf_generic_reloc, /* special_function */
177 "R_ARM_ABS12", /* name */
178 FALSE, /* partial_inplace */
00a97672
RS		 179 0x00000fff, /* src_mask */
180 0x00000fff, /* dst_mask */
7f266840
DJ		 181 FALSE), /* pcrel_offset */
182
183 HOWTO (R_ARM_THM_ABS5, /* type */
184 6, /* rightshift */
185 1, /* size (0 = byte, 1 = short, 2 = long) */
186 5, /* bitsize */
187 FALSE, /* pc_relative */
188 0, /* bitpos */
189 complain_overflow_bitfield,/* complain_on_overflow */
190 bfd_elf_generic_reloc, /* special_function */
191 "R_ARM_THM_ABS5", /* name */
192 FALSE, /* partial_inplace */
193 0x000007e0, /* src_mask */
194 0x000007e0, /* dst_mask */
195 FALSE), /* pcrel_offset */
196
197 /* 8 bit absolute */
198 HOWTO (R_ARM_ABS8, /* type */
199 0, /* rightshift */
200 0, /* size (0 = byte, 1 = short, 2 = long) */
201 8, /* bitsize */
202 FALSE, /* pc_relative */
203 0, /* bitpos */
204 complain_overflow_bitfield,/* complain_on_overflow */
205 bfd_elf_generic_reloc, /* special_function */
206 "R_ARM_ABS8", /* name */
207 FALSE, /* partial_inplace */
208 0x000000ff, /* src_mask */
209 0x000000ff, /* dst_mask */
210 FALSE), /* pcrel_offset */
211
212 HOWTO (R_ARM_SBREL32, /* type */
213 0, /* rightshift */
214 2, /* size (0 = byte, 1 = short, 2 = long) */
215 32, /* bitsize */
216 FALSE, /* pc_relative */
217 0, /* bitpos */
218 complain_overflow_dont,/* complain_on_overflow */
219 bfd_elf_generic_reloc, /* special_function */
220 "R_ARM_SBREL32", /* name */
221 FALSE, /* partial_inplace */
222 0xffffffff, /* src_mask */
223 0xffffffff, /* dst_mask */
224 FALSE), /* pcrel_offset */
225
c19d1205 226 HOWTO (R_ARM_THM_CALL, /* type */
7f266840
DJ		 227 1, /* rightshift */
228 2, /* size (0 = byte, 1 = short, 2 = long) */
f6ebfac0 229 24, /* bitsize */
7f266840
DJ		 230 TRUE, /* pc_relative */
231 0, /* bitpos */
232 complain_overflow_signed,/* complain_on_overflow */
233 bfd_elf_generic_reloc, /* special_function */
c19d1205 234 "R_ARM_THM_CALL", /* name */
7f266840 235 FALSE, /* partial_inplace */
7f6ab9f8
AM		 236 0x07ff2fff, /* src_mask */
237 0x07ff2fff, /* dst_mask */
7f266840
DJ		 238 TRUE), /* pcrel_offset */
239
240 HOWTO (R_ARM_THM_PC8, /* type */
241 1, /* rightshift */
242 1, /* size (0 = byte, 1 = short, 2 = long) */
243 8, /* bitsize */
244 TRUE, /* pc_relative */
245 0, /* bitpos */
246 complain_overflow_signed,/* complain_on_overflow */
247 bfd_elf_generic_reloc, /* special_function */
248 "R_ARM_THM_PC8", /* name */
249 FALSE, /* partial_inplace */
250 0x000000ff, /* src_mask */
251 0x000000ff, /* dst_mask */
252 TRUE), /* pcrel_offset */
253
c19d1205 254 HOWTO (R_ARM_BREL_ADJ, /* type */
7f266840
DJ		 255 1, /* rightshift */
256 1, /* size (0 = byte, 1 = short, 2 = long) */
c19d1205
ZW		 257 32, /* bitsize */
258 FALSE, /* pc_relative */
7f266840
DJ		 259 0, /* bitpos */
260 complain_overflow_signed,/* complain_on_overflow */
261 bfd_elf_generic_reloc, /* special_function */
c19d1205 262 "R_ARM_BREL_ADJ", /* name */
7f266840 263 FALSE, /* partial_inplace */
c19d1205
ZW		 264 0xffffffff, /* src_mask */
265 0xffffffff, /* dst_mask */
266 FALSE), /* pcrel_offset */
7f266840 267
0855e32b 268 HOWTO (R_ARM_TLS_DESC, /* type */
7f266840 269 0, /* rightshift */
0855e32b
NS		 270 2, /* size (0 = byte, 1 = short, 2 = long) */
271 32, /* bitsize */
7f266840
DJ		 272 FALSE, /* pc_relative */
273 0, /* bitpos */
0855e32b 274 complain_overflow_bitfield,/* complain_on_overflow */
7f266840 275 bfd_elf_generic_reloc, /* special_function */
0855e32b 276 "R_ARM_TLS_DESC", /* name */
7f266840 277 FALSE, /* partial_inplace */
0855e32b
NS		 278 0xffffffff, /* src_mask */
279 0xffffffff, /* dst_mask */
7f266840
DJ		 280 FALSE), /* pcrel_offset */
281
282 HOWTO (R_ARM_THM_SWI8, /* type */
283 0, /* rightshift */
284 0, /* size (0 = byte, 1 = short, 2 = long) */
285 0, /* bitsize */
286 FALSE, /* pc_relative */
287 0, /* bitpos */
288 complain_overflow_signed,/* complain_on_overflow */
289 bfd_elf_generic_reloc, /* special_function */
290 "R_ARM_SWI8", /* name */
291 FALSE, /* partial_inplace */
292 0x00000000, /* src_mask */
293 0x00000000, /* dst_mask */
294 FALSE), /* pcrel_offset */
295
296 /* BLX instruction for the ARM. */
297 HOWTO (R_ARM_XPC25, /* type */
298 2, /* rightshift */
299 2, /* size (0 = byte, 1 = short, 2 = long) */
7f6ab9f8 300 24, /* bitsize */
7f266840
DJ		 301 TRUE, /* pc_relative */
302 0, /* bitpos */
303 complain_overflow_signed,/* complain_on_overflow */
304 bfd_elf_generic_reloc, /* special_function */
305 "R_ARM_XPC25", /* name */
306 FALSE, /* partial_inplace */
307 0x00ffffff, /* src_mask */
308 0x00ffffff, /* dst_mask */
309 TRUE), /* pcrel_offset */
310
311 /* BLX instruction for the Thumb. */
312 HOWTO (R_ARM_THM_XPC22, /* type */
313 2, /* rightshift */
314 2, /* size (0 = byte, 1 = short, 2 = long) */
7f6ab9f8 315 24, /* bitsize */
7f266840
DJ		 316 TRUE, /* pc_relative */
317 0, /* bitpos */
318 complain_overflow_signed,/* complain_on_overflow */
319 bfd_elf_generic_reloc, /* special_function */
320 "R_ARM_THM_XPC22", /* name */
321 FALSE, /* partial_inplace */
7f6ab9f8
AM		 322 0x07ff2fff, /* src_mask */
323 0x07ff2fff, /* dst_mask */
7f266840
DJ		 324 TRUE), /* pcrel_offset */
325
ba93b8ac 326 /* Dynamic TLS relocations. */
7f266840 327
ba93b8ac 328 HOWTO (R_ARM_TLS_DTPMOD32, /* type */
99059e56
RM		 329 0, /* rightshift */
330 2, /* size (0 = byte, 1 = short, 2 = long) */
331 32, /* bitsize */
332 FALSE, /* pc_relative */
333 0, /* bitpos */
334 complain_overflow_bitfield,/* complain_on_overflow */
335 bfd_elf_generic_reloc, /* special_function */
336 "R_ARM_TLS_DTPMOD32", /* name */
337 TRUE, /* partial_inplace */
338 0xffffffff, /* src_mask */
339 0xffffffff, /* dst_mask */
340 FALSE), /* pcrel_offset */
7f266840 341
ba93b8ac 342 HOWTO (R_ARM_TLS_DTPOFF32, /* type */
99059e56
RM		 343 0, /* rightshift */
344 2, /* size (0 = byte, 1 = short, 2 = long) */
345 32, /* bitsize */
346 FALSE, /* pc_relative */
347 0, /* bitpos */
348 complain_overflow_bitfield,/* complain_on_overflow */
349 bfd_elf_generic_reloc, /* special_function */
350 "R_ARM_TLS_DTPOFF32", /* name */
351 TRUE, /* partial_inplace */
352 0xffffffff, /* src_mask */
353 0xffffffff, /* dst_mask */
354 FALSE), /* pcrel_offset */
7f266840 355
ba93b8ac 356 HOWTO (R_ARM_TLS_TPOFF32, /* type */
99059e56
RM		 357 0, /* rightshift */
358 2, /* size (0 = byte, 1 = short, 2 = long) */
359 32, /* bitsize */
360 FALSE, /* pc_relative */
361 0, /* bitpos */
362 complain_overflow_bitfield,/* complain_on_overflow */
363 bfd_elf_generic_reloc, /* special_function */
364 "R_ARM_TLS_TPOFF32", /* name */
365 TRUE, /* partial_inplace */
366 0xffffffff, /* src_mask */
367 0xffffffff, /* dst_mask */
368 FALSE), /* pcrel_offset */
7f266840
DJ		 369
370 /* Relocs used in ARM Linux */
371
372 HOWTO (R_ARM_COPY, /* type */
99059e56
RM		 373 0, /* rightshift */
374 2, /* size (0 = byte, 1 = short, 2 = long) */
375 32, /* bitsize */
376 FALSE, /* pc_relative */
377 0, /* bitpos */
378 complain_overflow_bitfield,/* complain_on_overflow */
379 bfd_elf_generic_reloc, /* special_function */
380 "R_ARM_COPY", /* name */
381 TRUE, /* partial_inplace */
382 0xffffffff, /* src_mask */
383 0xffffffff, /* dst_mask */
384 FALSE), /* pcrel_offset */
7f266840
DJ		 385
386 HOWTO (R_ARM_GLOB_DAT, /* type */
99059e56
RM		 387 0, /* rightshift */
388 2, /* size (0 = byte, 1 = short, 2 = long) */
389 32, /* bitsize */
390 FALSE, /* pc_relative */
391 0, /* bitpos */
392 complain_overflow_bitfield,/* complain_on_overflow */
393 bfd_elf_generic_reloc, /* special_function */
394 "R_ARM_GLOB_DAT", /* name */
395 TRUE, /* partial_inplace */
396 0xffffffff, /* src_mask */
397 0xffffffff, /* dst_mask */
398 FALSE), /* pcrel_offset */
7f266840
DJ		 399
400 HOWTO (R_ARM_JUMP_SLOT, /* type */
99059e56
RM		 401 0, /* rightshift */
402 2, /* size (0 = byte, 1 = short, 2 = long) */
403 32, /* bitsize */
404 FALSE, /* pc_relative */
405 0, /* bitpos */
406 complain_overflow_bitfield,/* complain_on_overflow */
407 bfd_elf_generic_reloc, /* special_function */
408 "R_ARM_JUMP_SLOT", /* name */
409 TRUE, /* partial_inplace */
410 0xffffffff, /* src_mask */
411 0xffffffff, /* dst_mask */
412 FALSE), /* pcrel_offset */
7f266840
DJ		 413
414 HOWTO (R_ARM_RELATIVE, /* type */
99059e56
RM		 415 0, /* rightshift */
416 2, /* size (0 = byte, 1 = short, 2 = long) */
417 32, /* bitsize */
418 FALSE, /* pc_relative */
419 0, /* bitpos */
420 complain_overflow_bitfield,/* complain_on_overflow */
421 bfd_elf_generic_reloc, /* special_function */
422 "R_ARM_RELATIVE", /* name */
423 TRUE, /* partial_inplace */
424 0xffffffff, /* src_mask */
425 0xffffffff, /* dst_mask */
426 FALSE), /* pcrel_offset */
7f266840 427
c19d1205 428 HOWTO (R_ARM_GOTOFF32, /* type */
99059e56
RM		 429 0, /* rightshift */
430 2, /* size (0 = byte, 1 = short, 2 = long) */
431 32, /* bitsize */
432 FALSE, /* pc_relative */
433 0, /* bitpos */
434 complain_overflow_bitfield,/* complain_on_overflow */
435 bfd_elf_generic_reloc, /* special_function */
436 "R_ARM_GOTOFF32", /* name */
437 TRUE, /* partial_inplace */
438 0xffffffff, /* src_mask */
439 0xffffffff, /* dst_mask */
440 FALSE), /* pcrel_offset */
7f266840
DJ		 441
442 HOWTO (R_ARM_GOTPC, /* type */
99059e56
RM		 443 0, /* rightshift */
444 2, /* size (0 = byte, 1 = short, 2 = long) */
445 32, /* bitsize */
446 TRUE, /* pc_relative */
447 0, /* bitpos */
448 complain_overflow_bitfield,/* complain_on_overflow */
449 bfd_elf_generic_reloc, /* special_function */
450 "R_ARM_GOTPC", /* name */
451 TRUE, /* partial_inplace */
452 0xffffffff, /* src_mask */
453 0xffffffff, /* dst_mask */
454 TRUE), /* pcrel_offset */
7f266840
DJ		 455
456 HOWTO (R_ARM_GOT32, /* type */
99059e56
RM		 457 0, /* rightshift */
458 2, /* size (0 = byte, 1 = short, 2 = long) */
459 32, /* bitsize */
460 FALSE, /* pc_relative */
461 0, /* bitpos */
462 complain_overflow_bitfield,/* complain_on_overflow */
463 bfd_elf_generic_reloc, /* special_function */
464 "R_ARM_GOT32", /* name */
465 TRUE, /* partial_inplace */
466 0xffffffff, /* src_mask */
467 0xffffffff, /* dst_mask */
468 FALSE), /* pcrel_offset */
7f266840
DJ		 469
470 HOWTO (R_ARM_PLT32, /* type */
99059e56
RM		 471 2, /* rightshift */
472 2, /* size (0 = byte, 1 = short, 2 = long) */
473 24, /* bitsize */
474 TRUE, /* pc_relative */
475 0, /* bitpos */
476 complain_overflow_bitfield,/* complain_on_overflow */
477 bfd_elf_generic_reloc, /* special_function */
478 "R_ARM_PLT32", /* name */
479 FALSE, /* partial_inplace */
480 0x00ffffff, /* src_mask */
481 0x00ffffff, /* dst_mask */
482 TRUE), /* pcrel_offset */
7f266840
DJ		 483
484 HOWTO (R_ARM_CALL, /* type */
485 2, /* rightshift */
486 2, /* size (0 = byte, 1 = short, 2 = long) */
487 24, /* bitsize */
488 TRUE, /* pc_relative */
489 0, /* bitpos */
490 complain_overflow_signed,/* complain_on_overflow */
491 bfd_elf_generic_reloc, /* special_function */
492 "R_ARM_CALL", /* name */
493 FALSE, /* partial_inplace */
494 0x00ffffff, /* src_mask */
495 0x00ffffff, /* dst_mask */
496 TRUE), /* pcrel_offset */
497
498 HOWTO (R_ARM_JUMP24, /* type */
499 2, /* rightshift */
500 2, /* size (0 = byte, 1 = short, 2 = long) */
501 24, /* bitsize */
502 TRUE, /* pc_relative */
503 0, /* bitpos */
504 complain_overflow_signed,/* complain_on_overflow */
505 bfd_elf_generic_reloc, /* special_function */
506 "R_ARM_JUMP24", /* name */
507 FALSE, /* partial_inplace */
508 0x00ffffff, /* src_mask */
509 0x00ffffff, /* dst_mask */
510 TRUE), /* pcrel_offset */
511
c19d1205
ZW		 512 HOWTO (R_ARM_THM_JUMP24, /* type */
513 1, /* rightshift */
514 2, /* size (0 = byte, 1 = short, 2 = long) */
515 24, /* bitsize */
516 TRUE, /* pc_relative */
7f266840 517 0, /* bitpos */
c19d1205 518 complain_overflow_signed,/* complain_on_overflow */
7f266840 519 bfd_elf_generic_reloc, /* special_function */
c19d1205 520 "R_ARM_THM_JUMP24", /* name */
7f266840 521 FALSE, /* partial_inplace */
c19d1205
ZW		 522 0x07ff2fff, /* src_mask */
523 0x07ff2fff, /* dst_mask */
524 TRUE), /* pcrel_offset */
7f266840 525
c19d1205 526 HOWTO (R_ARM_BASE_ABS, /* type */
7f266840 527 0, /* rightshift */
c19d1205
ZW		 528 2, /* size (0 = byte, 1 = short, 2 = long) */
529 32, /* bitsize */
7f266840
DJ		 530 FALSE, /* pc_relative */
531 0, /* bitpos */
532 complain_overflow_dont,/* complain_on_overflow */
533 bfd_elf_generic_reloc, /* special_function */
c19d1205 534 "R_ARM_BASE_ABS", /* name */
7f266840 535 FALSE, /* partial_inplace */
c19d1205
ZW		 536 0xffffffff, /* src_mask */
537 0xffffffff, /* dst_mask */
7f266840
DJ		 538 FALSE), /* pcrel_offset */
539
540 HOWTO (R_ARM_ALU_PCREL7_0, /* type */
541 0, /* rightshift */
542 2, /* size (0 = byte, 1 = short, 2 = long) */
543 12, /* bitsize */
544 TRUE, /* pc_relative */
545 0, /* bitpos */
546 complain_overflow_dont,/* complain_on_overflow */
547 bfd_elf_generic_reloc, /* special_function */
548 "R_ARM_ALU_PCREL_7_0", /* name */
549 FALSE, /* partial_inplace */
550 0x00000fff, /* src_mask */
551 0x00000fff, /* dst_mask */
552 TRUE), /* pcrel_offset */
553
554 HOWTO (R_ARM_ALU_PCREL15_8, /* type */
555 0, /* rightshift */
556 2, /* size (0 = byte, 1 = short, 2 = long) */
557 12, /* bitsize */
558 TRUE, /* pc_relative */
559 8, /* bitpos */
560 complain_overflow_dont,/* complain_on_overflow */
561 bfd_elf_generic_reloc, /* special_function */
562 "R_ARM_ALU_PCREL_15_8",/* name */
563 FALSE, /* partial_inplace */
564 0x00000fff, /* src_mask */
565 0x00000fff, /* dst_mask */
566 TRUE), /* pcrel_offset */
567
568 HOWTO (R_ARM_ALU_PCREL23_15, /* type */
569 0, /* rightshift */
570 2, /* size (0 = byte, 1 = short, 2 = long) */
571 12, /* bitsize */
572 TRUE, /* pc_relative */
573 16, /* bitpos */
574 complain_overflow_dont,/* complain_on_overflow */
575 bfd_elf_generic_reloc, /* special_function */
576 "R_ARM_ALU_PCREL_23_15",/* name */
577 FALSE, /* partial_inplace */
578 0x00000fff, /* src_mask */
579 0x00000fff, /* dst_mask */
580 TRUE), /* pcrel_offset */
581
582 HOWTO (R_ARM_LDR_SBREL_11_0, /* type */
583 0, /* rightshift */
584 2, /* size (0 = byte, 1 = short, 2 = long) */
585 12, /* bitsize */
586 FALSE, /* pc_relative */
587 0, /* bitpos */
588 complain_overflow_dont,/* complain_on_overflow */
589 bfd_elf_generic_reloc, /* special_function */
590 "R_ARM_LDR_SBREL_11_0",/* name */
591 FALSE, /* partial_inplace */
592 0x00000fff, /* src_mask */
593 0x00000fff, /* dst_mask */
594 FALSE), /* pcrel_offset */
595
596 HOWTO (R_ARM_ALU_SBREL_19_12, /* type */
597 0, /* rightshift */
598 2, /* size (0 = byte, 1 = short, 2 = long) */
599 8, /* bitsize */
600 FALSE, /* pc_relative */
601 12, /* bitpos */
602 complain_overflow_dont,/* complain_on_overflow */
603 bfd_elf_generic_reloc, /* special_function */
604 "R_ARM_ALU_SBREL_19_12",/* name */
605 FALSE, /* partial_inplace */
606 0x000ff000, /* src_mask */
607 0x000ff000, /* dst_mask */
608 FALSE), /* pcrel_offset */
609
610 HOWTO (R_ARM_ALU_SBREL_27_20, /* type */
611 0, /* rightshift */
612 2, /* size (0 = byte, 1 = short, 2 = long) */
613 8, /* bitsize */
614 FALSE, /* pc_relative */
615 20, /* bitpos */
616 complain_overflow_dont,/* complain_on_overflow */
617 bfd_elf_generic_reloc, /* special_function */
618 "R_ARM_ALU_SBREL_27_20",/* name */
619 FALSE, /* partial_inplace */
620 0x0ff00000, /* src_mask */
621 0x0ff00000, /* dst_mask */
622 FALSE), /* pcrel_offset */
623
624 HOWTO (R_ARM_TARGET1, /* type */
625 0, /* rightshift */
626 2, /* size (0 = byte, 1 = short, 2 = long) */
627 32, /* bitsize */
628 FALSE, /* pc_relative */
629 0, /* bitpos */
630 complain_overflow_dont,/* complain_on_overflow */
631 bfd_elf_generic_reloc, /* special_function */
632 "R_ARM_TARGET1", /* name */
633 FALSE, /* partial_inplace */
634 0xffffffff, /* src_mask */
635 0xffffffff, /* dst_mask */
636 FALSE), /* pcrel_offset */
637
638 HOWTO (R_ARM_ROSEGREL32, /* type */
639 0, /* rightshift */
640 2, /* size (0 = byte, 1 = short, 2 = long) */
641 32, /* bitsize */
642 FALSE, /* pc_relative */
643 0, /* bitpos */
644 complain_overflow_dont,/* complain_on_overflow */
645 bfd_elf_generic_reloc, /* special_function */
646 "R_ARM_ROSEGREL32", /* name */
647 FALSE, /* partial_inplace */
648 0xffffffff, /* src_mask */
649 0xffffffff, /* dst_mask */
650 FALSE), /* pcrel_offset */
651
652 HOWTO (R_ARM_V4BX, /* type */
653 0, /* rightshift */
654 2, /* size (0 = byte, 1 = short, 2 = long) */
655 32, /* bitsize */
656 FALSE, /* pc_relative */
657 0, /* bitpos */
658 complain_overflow_dont,/* complain_on_overflow */
659 bfd_elf_generic_reloc, /* special_function */
660 "R_ARM_V4BX", /* name */
661 FALSE, /* partial_inplace */
662 0xffffffff, /* src_mask */
663 0xffffffff, /* dst_mask */
664 FALSE), /* pcrel_offset */
665
666 HOWTO (R_ARM_TARGET2, /* type */
667 0, /* rightshift */
668 2, /* size (0 = byte, 1 = short, 2 = long) */
669 32, /* bitsize */
670 FALSE, /* pc_relative */
671 0, /* bitpos */
672 complain_overflow_signed,/* complain_on_overflow */
673 bfd_elf_generic_reloc, /* special_function */
674 "R_ARM_TARGET2", /* name */
675 FALSE, /* partial_inplace */
676 0xffffffff, /* src_mask */
677 0xffffffff, /* dst_mask */
678 TRUE), /* pcrel_offset */
679
680 HOWTO (R_ARM_PREL31, /* type */
681 0, /* rightshift */
682 2, /* size (0 = byte, 1 = short, 2 = long) */
683 31, /* bitsize */
684 TRUE, /* pc_relative */
685 0, /* bitpos */
686 complain_overflow_signed,/* complain_on_overflow */
687 bfd_elf_generic_reloc, /* special_function */
688 "R_ARM_PREL31", /* name */
689 FALSE, /* partial_inplace */
690 0x7fffffff, /* src_mask */
691 0x7fffffff, /* dst_mask */
692 TRUE), /* pcrel_offset */
c19d1205
ZW		 693
694 HOWTO (R_ARM_MOVW_ABS_NC, /* type */
695 0, /* rightshift */
696 2, /* size (0 = byte, 1 = short, 2 = long) */
697 16, /* bitsize */
698 FALSE, /* pc_relative */
699 0, /* bitpos */
700 complain_overflow_dont,/* complain_on_overflow */
701 bfd_elf_generic_reloc, /* special_function */
702 "R_ARM_MOVW_ABS_NC", /* name */
703 FALSE, /* partial_inplace */
39623e12
PB		 704 0x000f0fff, /* src_mask */
705 0x000f0fff, /* dst_mask */
c19d1205
ZW		 706 FALSE), /* pcrel_offset */
707
708 HOWTO (R_ARM_MOVT_ABS, /* type */
709 0, /* rightshift */
710 2, /* size (0 = byte, 1 = short, 2 = long) */
711 16, /* bitsize */
712 FALSE, /* pc_relative */
713 0, /* bitpos */
714 complain_overflow_bitfield,/* complain_on_overflow */
715 bfd_elf_generic_reloc, /* special_function */
716 "R_ARM_MOVT_ABS", /* name */
717 FALSE, /* partial_inplace */
39623e12
PB		 718 0x000f0fff, /* src_mask */
719 0x000f0fff, /* dst_mask */
c19d1205
ZW		 720 FALSE), /* pcrel_offset */
721
722 HOWTO (R_ARM_MOVW_PREL_NC, /* type */
723 0, /* rightshift */
724 2, /* size (0 = byte, 1 = short, 2 = long) */
725 16, /* bitsize */
726 TRUE, /* pc_relative */
727 0, /* bitpos */
728 complain_overflow_dont,/* complain_on_overflow */
729 bfd_elf_generic_reloc, /* special_function */
730 "R_ARM_MOVW_PREL_NC", /* name */
731 FALSE, /* partial_inplace */
39623e12
PB		 732 0x000f0fff, /* src_mask */
733 0x000f0fff, /* dst_mask */
c19d1205
ZW		 734 TRUE), /* pcrel_offset */
735
736 HOWTO (R_ARM_MOVT_PREL, /* type */
737 0, /* rightshift */
738 2, /* size (0 = byte, 1 = short, 2 = long) */
739 16, /* bitsize */
740 TRUE, /* pc_relative */
741 0, /* bitpos */
742 complain_overflow_bitfield,/* complain_on_overflow */
743 bfd_elf_generic_reloc, /* special_function */
744 "R_ARM_MOVT_PREL", /* name */
745 FALSE, /* partial_inplace */
39623e12
PB		 746 0x000f0fff, /* src_mask */
747 0x000f0fff, /* dst_mask */
c19d1205
ZW		 748 TRUE), /* pcrel_offset */
749
750 HOWTO (R_ARM_THM_MOVW_ABS_NC, /* type */
751 0, /* rightshift */
752 2, /* size (0 = byte, 1 = short, 2 = long) */
753 16, /* bitsize */
754 FALSE, /* pc_relative */
755 0, /* bitpos */
756 complain_overflow_dont,/* complain_on_overflow */
757 bfd_elf_generic_reloc, /* special_function */
758 "R_ARM_THM_MOVW_ABS_NC",/* name */
759 FALSE, /* partial_inplace */
760 0x040f70ff, /* src_mask */
761 0x040f70ff, /* dst_mask */
762 FALSE), /* pcrel_offset */
763
764 HOWTO (R_ARM_THM_MOVT_ABS, /* type */
765 0, /* rightshift */
766 2, /* size (0 = byte, 1 = short, 2 = long) */
767 16, /* bitsize */
768 FALSE, /* pc_relative */
769 0, /* bitpos */
770 complain_overflow_bitfield,/* complain_on_overflow */
771 bfd_elf_generic_reloc, /* special_function */
772 "R_ARM_THM_MOVT_ABS", /* name */
773 FALSE, /* partial_inplace */
774 0x040f70ff, /* src_mask */
775 0x040f70ff, /* dst_mask */
776 FALSE), /* pcrel_offset */
777
778 HOWTO (R_ARM_THM_MOVW_PREL_NC,/* type */
779 0, /* rightshift */
780 2, /* size (0 = byte, 1 = short, 2 = long) */
781 16, /* bitsize */
782 TRUE, /* pc_relative */
783 0, /* bitpos */
784 complain_overflow_dont,/* complain_on_overflow */
785 bfd_elf_generic_reloc, /* special_function */
786 "R_ARM_THM_MOVW_PREL_NC",/* name */
787 FALSE, /* partial_inplace */
788 0x040f70ff, /* src_mask */
789 0x040f70ff, /* dst_mask */
790 TRUE), /* pcrel_offset */
791
792 HOWTO (R_ARM_THM_MOVT_PREL, /* type */
793 0, /* rightshift */
794 2, /* size (0 = byte, 1 = short, 2 = long) */
795 16, /* bitsize */
796 TRUE, /* pc_relative */
797 0, /* bitpos */
798 complain_overflow_bitfield,/* complain_on_overflow */
799 bfd_elf_generic_reloc, /* special_function */
800 "R_ARM_THM_MOVT_PREL", /* name */
801 FALSE, /* partial_inplace */
802 0x040f70ff, /* src_mask */
803 0x040f70ff, /* dst_mask */
804 TRUE), /* pcrel_offset */
805
806 HOWTO (R_ARM_THM_JUMP19, /* type */
807 1, /* rightshift */
808 2, /* size (0 = byte, 1 = short, 2 = long) */
809 19, /* bitsize */
810 TRUE, /* pc_relative */
811 0, /* bitpos */
812 complain_overflow_signed,/* complain_on_overflow */
813 bfd_elf_generic_reloc, /* special_function */
814 "R_ARM_THM_JUMP19", /* name */
815 FALSE, /* partial_inplace */
816 0x043f2fff, /* src_mask */
817 0x043f2fff, /* dst_mask */
818 TRUE), /* pcrel_offset */
819
820 HOWTO (R_ARM_THM_JUMP6, /* type */
821 1, /* rightshift */
822 1, /* size (0 = byte, 1 = short, 2 = long) */
823 6, /* bitsize */
824 TRUE, /* pc_relative */
825 0, /* bitpos */
826 complain_overflow_unsigned,/* complain_on_overflow */
827 bfd_elf_generic_reloc, /* special_function */
828 "R_ARM_THM_JUMP6", /* name */
829 FALSE, /* partial_inplace */
830 0x02f8, /* src_mask */
831 0x02f8, /* dst_mask */
832 TRUE), /* pcrel_offset */
833
834 /* These are declared as 13-bit signed relocations because we can
835 address -4095 .. 4095(base) by altering ADDW to SUBW or vice
836 versa. */
837 HOWTO (R_ARM_THM_ALU_PREL_11_0,/* type */
838 0, /* rightshift */
839 2, /* size (0 = byte, 1 = short, 2 = long) */
840 13, /* bitsize */
841 TRUE, /* pc_relative */
842 0, /* bitpos */
2cab6cc3 843 complain_overflow_dont,/* complain_on_overflow */
c19d1205
ZW		 844 bfd_elf_generic_reloc, /* special_function */
845 "R_ARM_THM_ALU_PREL_11_0",/* name */
846 FALSE, /* partial_inplace */
2cab6cc3
MS		 847 0xffffffff, /* src_mask */
848 0xffffffff, /* dst_mask */
c19d1205
ZW		 849 TRUE), /* pcrel_offset */
850
851 HOWTO (R_ARM_THM_PC12, /* type */
852 0, /* rightshift */
853 2, /* size (0 = byte, 1 = short, 2 = long) */
854 13, /* bitsize */
855 TRUE, /* pc_relative */
856 0, /* bitpos */
2cab6cc3 857 complain_overflow_dont,/* complain_on_overflow */
c19d1205
ZW		 858 bfd_elf_generic_reloc, /* special_function */
859 "R_ARM_THM_PC12", /* name */
860 FALSE, /* partial_inplace */
2cab6cc3
MS		 861 0xffffffff, /* src_mask */
862 0xffffffff, /* dst_mask */
c19d1205
ZW		 863 TRUE), /* pcrel_offset */
864
865 HOWTO (R_ARM_ABS32_NOI, /* type */
866 0, /* rightshift */
867 2, /* size (0 = byte, 1 = short, 2 = long) */
868 32, /* bitsize */
869 FALSE, /* pc_relative */
870 0, /* bitpos */
871 complain_overflow_dont,/* complain_on_overflow */
872 bfd_elf_generic_reloc, /* special_function */
873 "R_ARM_ABS32_NOI", /* name */
874 FALSE, /* partial_inplace */
875 0xffffffff, /* src_mask */
876 0xffffffff, /* dst_mask */
877 FALSE), /* pcrel_offset */
878
879 HOWTO (R_ARM_REL32_NOI, /* type */
880 0, /* rightshift */
881 2, /* size (0 = byte, 1 = short, 2 = long) */
882 32, /* bitsize */
883 TRUE, /* pc_relative */
884 0, /* bitpos */
885 complain_overflow_dont,/* complain_on_overflow */
886 bfd_elf_generic_reloc, /* special_function */
887 "R_ARM_REL32_NOI", /* name */
888 FALSE, /* partial_inplace */
889 0xffffffff, /* src_mask */
890 0xffffffff, /* dst_mask */
891 FALSE), /* pcrel_offset */
7f266840 892
4962c51a
MS		 893 /* Group relocations. */
894
895 HOWTO (R_ARM_ALU_PC_G0_NC, /* type */
896 0, /* rightshift */
897 2, /* size (0 = byte, 1 = short, 2 = long) */
898 32, /* bitsize */
899 TRUE, /* pc_relative */
900 0, /* bitpos */
901 complain_overflow_dont,/* complain_on_overflow */
902 bfd_elf_generic_reloc, /* special_function */
903 "R_ARM_ALU_PC_G0_NC", /* name */
904 FALSE, /* partial_inplace */
905 0xffffffff, /* src_mask */
906 0xffffffff, /* dst_mask */
907 TRUE), /* pcrel_offset */
908
909 HOWTO (R_ARM_ALU_PC_G0, /* type */
910 0, /* rightshift */
911 2, /* size (0 = byte, 1 = short, 2 = long) */
912 32, /* bitsize */
913 TRUE, /* pc_relative */
914 0, /* bitpos */
915 complain_overflow_dont,/* complain_on_overflow */
916 bfd_elf_generic_reloc, /* special_function */
917 "R_ARM_ALU_PC_G0", /* name */
918 FALSE, /* partial_inplace */
919 0xffffffff, /* src_mask */
920 0xffffffff, /* dst_mask */
921 TRUE), /* pcrel_offset */
922
923 HOWTO (R_ARM_ALU_PC_G1_NC, /* type */
924 0, /* rightshift */
925 2, /* size (0 = byte, 1 = short, 2 = long) */
926 32, /* bitsize */
927 TRUE, /* pc_relative */
928 0, /* bitpos */
929 complain_overflow_dont,/* complain_on_overflow */
930 bfd_elf_generic_reloc, /* special_function */
931 "R_ARM_ALU_PC_G1_NC", /* name */
932 FALSE, /* partial_inplace */
933 0xffffffff, /* src_mask */
934 0xffffffff, /* dst_mask */
935 TRUE), /* pcrel_offset */
936
937 HOWTO (R_ARM_ALU_PC_G1, /* type */
938 0, /* rightshift */
939 2, /* size (0 = byte, 1 = short, 2 = long) */
940 32, /* bitsize */
941 TRUE, /* pc_relative */
942 0, /* bitpos */
943 complain_overflow_dont,/* complain_on_overflow */
944 bfd_elf_generic_reloc, /* special_function */
945 "R_ARM_ALU_PC_G1", /* name */
946 FALSE, /* partial_inplace */
947 0xffffffff, /* src_mask */
948 0xffffffff, /* dst_mask */
949 TRUE), /* pcrel_offset */
950
951 HOWTO (R_ARM_ALU_PC_G2, /* type */
952 0, /* rightshift */
953 2, /* size (0 = byte, 1 = short, 2 = long) */
954 32, /* bitsize */
955 TRUE, /* pc_relative */
956 0, /* bitpos */
957 complain_overflow_dont,/* complain_on_overflow */
958 bfd_elf_generic_reloc, /* special_function */
959 "R_ARM_ALU_PC_G2", /* name */
960 FALSE, /* partial_inplace */
961 0xffffffff, /* src_mask */
962 0xffffffff, /* dst_mask */
963 TRUE), /* pcrel_offset */
964
965 HOWTO (R_ARM_LDR_PC_G1, /* type */
966 0, /* rightshift */
967 2, /* size (0 = byte, 1 = short, 2 = long) */
968 32, /* bitsize */
969 TRUE, /* pc_relative */
970 0, /* bitpos */
971 complain_overflow_dont,/* complain_on_overflow */
972 bfd_elf_generic_reloc, /* special_function */
973 "R_ARM_LDR_PC_G1", /* name */
974 FALSE, /* partial_inplace */
975 0xffffffff, /* src_mask */
976 0xffffffff, /* dst_mask */
977 TRUE), /* pcrel_offset */
978
979 HOWTO (R_ARM_LDR_PC_G2, /* type */
980 0, /* rightshift */
981 2, /* size (0 = byte, 1 = short, 2 = long) */
982 32, /* bitsize */
983 TRUE, /* pc_relative */
984 0, /* bitpos */
985 complain_overflow_dont,/* complain_on_overflow */
986 bfd_elf_generic_reloc, /* special_function */
987 "R_ARM_LDR_PC_G2", /* name */
988 FALSE, /* partial_inplace */
989 0xffffffff, /* src_mask */
990 0xffffffff, /* dst_mask */
991 TRUE), /* pcrel_offset */
992
993 HOWTO (R_ARM_LDRS_PC_G0, /* type */
994 0, /* rightshift */
995 2, /* size (0 = byte, 1 = short, 2 = long) */
996 32, /* bitsize */
997 TRUE, /* pc_relative */
998 0, /* bitpos */
999 complain_overflow_dont,/* complain_on_overflow */
1000 bfd_elf_generic_reloc, /* special_function */
1001 "R_ARM_LDRS_PC_G0", /* name */
1002 FALSE, /* partial_inplace */
1003 0xffffffff, /* src_mask */
1004 0xffffffff, /* dst_mask */
1005 TRUE), /* pcrel_offset */
1006
1007 HOWTO (R_ARM_LDRS_PC_G1, /* type */
1008 0, /* rightshift */
1009 2, /* size (0 = byte, 1 = short, 2 = long) */
1010 32, /* bitsize */
1011 TRUE, /* pc_relative */
1012 0, /* bitpos */
1013 complain_overflow_dont,/* complain_on_overflow */
1014 bfd_elf_generic_reloc, /* special_function */
1015 "R_ARM_LDRS_PC_G1", /* name */
1016 FALSE, /* partial_inplace */
1017 0xffffffff, /* src_mask */
1018 0xffffffff, /* dst_mask */
1019 TRUE), /* pcrel_offset */
1020
1021 HOWTO (R_ARM_LDRS_PC_G2, /* type */
1022 0, /* rightshift */
1023 2, /* size (0 = byte, 1 = short, 2 = long) */
1024 32, /* bitsize */
1025 TRUE, /* pc_relative */
1026 0, /* bitpos */
1027 complain_overflow_dont,/* complain_on_overflow */
1028 bfd_elf_generic_reloc, /* special_function */
1029 "R_ARM_LDRS_PC_G2", /* name */
1030 FALSE, /* partial_inplace */
1031 0xffffffff, /* src_mask */
1032 0xffffffff, /* dst_mask */
1033 TRUE), /* pcrel_offset */
1034
1035 HOWTO (R_ARM_LDC_PC_G0, /* type */
1036 0, /* rightshift */
1037 2, /* size (0 = byte, 1 = short, 2 = long) */
1038 32, /* bitsize */
1039 TRUE, /* pc_relative */
1040 0, /* bitpos */
1041 complain_overflow_dont,/* complain_on_overflow */
1042 bfd_elf_generic_reloc, /* special_function */
1043 "R_ARM_LDC_PC_G0", /* name */
1044 FALSE, /* partial_inplace */
1045 0xffffffff, /* src_mask */
1046 0xffffffff, /* dst_mask */
1047 TRUE), /* pcrel_offset */
1048
1049 HOWTO (R_ARM_LDC_PC_G1, /* type */
1050 0, /* rightshift */
1051 2, /* size (0 = byte, 1 = short, 2 = long) */
1052 32, /* bitsize */
1053 TRUE, /* pc_relative */
1054 0, /* bitpos */
1055 complain_overflow_dont,/* complain_on_overflow */
1056 bfd_elf_generic_reloc, /* special_function */
1057 "R_ARM_LDC_PC_G1", /* name */
1058 FALSE, /* partial_inplace */
1059 0xffffffff, /* src_mask */
1060 0xffffffff, /* dst_mask */
1061 TRUE), /* pcrel_offset */
1062
1063 HOWTO (R_ARM_LDC_PC_G2, /* type */
1064 0, /* rightshift */
1065 2, /* size (0 = byte, 1 = short, 2 = long) */
1066 32, /* bitsize */
1067 TRUE, /* pc_relative */
1068 0, /* bitpos */
1069 complain_overflow_dont,/* complain_on_overflow */
1070 bfd_elf_generic_reloc, /* special_function */
1071 "R_ARM_LDC_PC_G2", /* name */
1072 FALSE, /* partial_inplace */
1073 0xffffffff, /* src_mask */
1074 0xffffffff, /* dst_mask */
1075 TRUE), /* pcrel_offset */
1076
1077 HOWTO (R_ARM_ALU_SB_G0_NC, /* type */
1078 0, /* rightshift */
1079 2, /* size (0 = byte, 1 = short, 2 = long) */
1080 32, /* bitsize */
1081 TRUE, /* pc_relative */
1082 0, /* bitpos */
1083 complain_overflow_dont,/* complain_on_overflow */
1084 bfd_elf_generic_reloc, /* special_function */
1085 "R_ARM_ALU_SB_G0_NC", /* name */
1086 FALSE, /* partial_inplace */
1087 0xffffffff, /* src_mask */
1088 0xffffffff, /* dst_mask */
1089 TRUE), /* pcrel_offset */
1090
1091 HOWTO (R_ARM_ALU_SB_G0, /* type */
1092 0, /* rightshift */
1093 2, /* size (0 = byte, 1 = short, 2 = long) */
1094 32, /* bitsize */
1095 TRUE, /* pc_relative */
1096 0, /* bitpos */
1097 complain_overflow_dont,/* complain_on_overflow */
1098 bfd_elf_generic_reloc, /* special_function */
1099 "R_ARM_ALU_SB_G0", /* name */
1100 FALSE, /* partial_inplace */
1101 0xffffffff, /* src_mask */
1102 0xffffffff, /* dst_mask */
1103 TRUE), /* pcrel_offset */
1104
1105 HOWTO (R_ARM_ALU_SB_G1_NC, /* type */
1106 0, /* rightshift */
1107 2, /* size (0 = byte, 1 = short, 2 = long) */
1108 32, /* bitsize */
1109 TRUE, /* pc_relative */
1110 0, /* bitpos */
1111 complain_overflow_dont,/* complain_on_overflow */
1112 bfd_elf_generic_reloc, /* special_function */
1113 "R_ARM_ALU_SB_G1_NC", /* name */
1114 FALSE, /* partial_inplace */
1115 0xffffffff, /* src_mask */
1116 0xffffffff, /* dst_mask */
1117 TRUE), /* pcrel_offset */
1118
1119 HOWTO (R_ARM_ALU_SB_G1, /* type */
1120 0, /* rightshift */
1121 2, /* size (0 = byte, 1 = short, 2 = long) */
1122 32, /* bitsize */
1123 TRUE, /* pc_relative */
1124 0, /* bitpos */
1125 complain_overflow_dont,/* complain_on_overflow */
1126 bfd_elf_generic_reloc, /* special_function */
1127 "R_ARM_ALU_SB_G1", /* name */
1128 FALSE, /* partial_inplace */
1129 0xffffffff, /* src_mask */
1130 0xffffffff, /* dst_mask */
1131 TRUE), /* pcrel_offset */
1132
1133 HOWTO (R_ARM_ALU_SB_G2, /* type */
1134 0, /* rightshift */
1135 2, /* size (0 = byte, 1 = short, 2 = long) */
1136 32, /* bitsize */
1137 TRUE, /* pc_relative */
1138 0, /* bitpos */
1139 complain_overflow_dont,/* complain_on_overflow */
1140 bfd_elf_generic_reloc, /* special_function */
1141 "R_ARM_ALU_SB_G2", /* name */
1142 FALSE, /* partial_inplace */
1143 0xffffffff, /* src_mask */
1144 0xffffffff, /* dst_mask */
1145 TRUE), /* pcrel_offset */
1146
1147 HOWTO (R_ARM_LDR_SB_G0, /* type */
1148 0, /* rightshift */
1149 2, /* size (0 = byte, 1 = short, 2 = long) */
1150 32, /* bitsize */
1151 TRUE, /* pc_relative */
1152 0, /* bitpos */
1153 complain_overflow_dont,/* complain_on_overflow */
1154 bfd_elf_generic_reloc, /* special_function */
1155 "R_ARM_LDR_SB_G0", /* name */
1156 FALSE, /* partial_inplace */
1157 0xffffffff, /* src_mask */
1158 0xffffffff, /* dst_mask */
1159 TRUE), /* pcrel_offset */
1160
1161 HOWTO (R_ARM_LDR_SB_G1, /* type */
1162 0, /* rightshift */
1163 2, /* size (0 = byte, 1 = short, 2 = long) */
1164 32, /* bitsize */
1165 TRUE, /* pc_relative */
1166 0, /* bitpos */
1167 complain_overflow_dont,/* complain_on_overflow */
1168 bfd_elf_generic_reloc, /* special_function */
1169 "R_ARM_LDR_SB_G1", /* name */
1170 FALSE, /* partial_inplace */
1171 0xffffffff, /* src_mask */
1172 0xffffffff, /* dst_mask */
1173 TRUE), /* pcrel_offset */
1174
1175 HOWTO (R_ARM_LDR_SB_G2, /* type */
1176 0, /* rightshift */
1177 2, /* size (0 = byte, 1 = short, 2 = long) */
1178 32, /* bitsize */
1179 TRUE, /* pc_relative */
1180 0, /* bitpos */
1181 complain_overflow_dont,/* complain_on_overflow */
1182 bfd_elf_generic_reloc, /* special_function */
1183 "R_ARM_LDR_SB_G2", /* name */
1184 FALSE, /* partial_inplace */
1185 0xffffffff, /* src_mask */
1186 0xffffffff, /* dst_mask */
1187 TRUE), /* pcrel_offset */
1188
1189 HOWTO (R_ARM_LDRS_SB_G0, /* type */
1190 0, /* rightshift */
1191 2, /* size (0 = byte, 1 = short, 2 = long) */
1192 32, /* bitsize */
1193 TRUE, /* pc_relative */
1194 0, /* bitpos */
1195 complain_overflow_dont,/* complain_on_overflow */
1196 bfd_elf_generic_reloc, /* special_function */
1197 "R_ARM_LDRS_SB_G0", /* name */
1198 FALSE, /* partial_inplace */
1199 0xffffffff, /* src_mask */
1200 0xffffffff, /* dst_mask */
1201 TRUE), /* pcrel_offset */
1202
1203 HOWTO (R_ARM_LDRS_SB_G1, /* type */
1204 0, /* rightshift */
1205 2, /* size (0 = byte, 1 = short, 2 = long) */
1206 32, /* bitsize */
1207 TRUE, /* pc_relative */
1208 0, /* bitpos */
1209 complain_overflow_dont,/* complain_on_overflow */
1210 bfd_elf_generic_reloc, /* special_function */
1211 "R_ARM_LDRS_SB_G1", /* name */
1212 FALSE, /* partial_inplace */
1213 0xffffffff, /* src_mask */
1214 0xffffffff, /* dst_mask */
1215 TRUE), /* pcrel_offset */
1216
1217 HOWTO (R_ARM_LDRS_SB_G2, /* type */
1218 0, /* rightshift */
1219 2, /* size (0 = byte, 1 = short, 2 = long) */
1220 32, /* bitsize */
1221 TRUE, /* pc_relative */
1222 0, /* bitpos */
1223 complain_overflow_dont,/* complain_on_overflow */
1224 bfd_elf_generic_reloc, /* special_function */
1225 "R_ARM_LDRS_SB_G2", /* name */
1226 FALSE, /* partial_inplace */
1227 0xffffffff, /* src_mask */
1228 0xffffffff, /* dst_mask */
1229 TRUE), /* pcrel_offset */
1230
1231 HOWTO (R_ARM_LDC_SB_G0, /* type */
1232 0, /* rightshift */
1233 2, /* size (0 = byte, 1 = short, 2 = long) */
1234 32, /* bitsize */
1235 TRUE, /* pc_relative */
1236 0, /* bitpos */
1237 complain_overflow_dont,/* complain_on_overflow */
1238 bfd_elf_generic_reloc, /* special_function */
1239 "R_ARM_LDC_SB_G0", /* name */
1240 FALSE, /* partial_inplace */
1241 0xffffffff, /* src_mask */
1242 0xffffffff, /* dst_mask */
1243 TRUE), /* pcrel_offset */
1244
1245 HOWTO (R_ARM_LDC_SB_G1, /* type */
1246 0, /* rightshift */
1247 2, /* size (0 = byte, 1 = short, 2 = long) */
1248 32, /* bitsize */
1249 TRUE, /* pc_relative */
1250 0, /* bitpos */
1251 complain_overflow_dont,/* complain_on_overflow */
1252 bfd_elf_generic_reloc, /* special_function */
1253 "R_ARM_LDC_SB_G1", /* name */
1254 FALSE, /* partial_inplace */
1255 0xffffffff, /* src_mask */
1256 0xffffffff, /* dst_mask */
1257 TRUE), /* pcrel_offset */
1258
1259 HOWTO (R_ARM_LDC_SB_G2, /* type */
1260 0, /* rightshift */
1261 2, /* size (0 = byte, 1 = short, 2 = long) */
1262 32, /* bitsize */
1263 TRUE, /* pc_relative */
1264 0, /* bitpos */
1265 complain_overflow_dont,/* complain_on_overflow */
1266 bfd_elf_generic_reloc, /* special_function */
1267 "R_ARM_LDC_SB_G2", /* name */
1268 FALSE, /* partial_inplace */
1269 0xffffffff, /* src_mask */
1270 0xffffffff, /* dst_mask */
1271 TRUE), /* pcrel_offset */
1272
1273 /* End of group relocations. */
c19d1205 1274
c19d1205
ZW		 1275 HOWTO (R_ARM_MOVW_BREL_NC, /* type */
1276 0, /* rightshift */
1277 2, /* size (0 = byte, 1 = short, 2 = long) */
1278 16, /* bitsize */
1279 FALSE, /* pc_relative */
1280 0, /* bitpos */
1281 complain_overflow_dont,/* complain_on_overflow */
1282 bfd_elf_generic_reloc, /* special_function */
1283 "R_ARM_MOVW_BREL_NC", /* name */
1284 FALSE, /* partial_inplace */
1285 0x0000ffff, /* src_mask */
1286 0x0000ffff, /* dst_mask */
1287 FALSE), /* pcrel_offset */
1288
1289 HOWTO (R_ARM_MOVT_BREL, /* type */
1290 0, /* rightshift */
1291 2, /* size (0 = byte, 1 = short, 2 = long) */
1292 16, /* bitsize */
1293 FALSE, /* pc_relative */
1294 0, /* bitpos */
1295 complain_overflow_bitfield,/* complain_on_overflow */
1296 bfd_elf_generic_reloc, /* special_function */
1297 "R_ARM_MOVT_BREL", /* name */
1298 FALSE, /* partial_inplace */
1299 0x0000ffff, /* src_mask */
1300 0x0000ffff, /* dst_mask */
1301 FALSE), /* pcrel_offset */
1302
1303 HOWTO (R_ARM_MOVW_BREL, /* type */
1304 0, /* rightshift */
1305 2, /* size (0 = byte, 1 = short, 2 = long) */
1306 16, /* bitsize */
1307 FALSE, /* pc_relative */
1308 0, /* bitpos */
1309 complain_overflow_dont,/* complain_on_overflow */
1310 bfd_elf_generic_reloc, /* special_function */
1311 "R_ARM_MOVW_BREL", /* name */
1312 FALSE, /* partial_inplace */
1313 0x0000ffff, /* src_mask */
1314 0x0000ffff, /* dst_mask */
1315 FALSE), /* pcrel_offset */
1316
1317 HOWTO (R_ARM_THM_MOVW_BREL_NC,/* type */
1318 0, /* rightshift */
1319 2, /* size (0 = byte, 1 = short, 2 = long) */
1320 16, /* bitsize */
1321 FALSE, /* pc_relative */
1322 0, /* bitpos */
1323 complain_overflow_dont,/* complain_on_overflow */
1324 bfd_elf_generic_reloc, /* special_function */
1325 "R_ARM_THM_MOVW_BREL_NC",/* name */
1326 FALSE, /* partial_inplace */
1327 0x040f70ff, /* src_mask */
1328 0x040f70ff, /* dst_mask */
1329 FALSE), /* pcrel_offset */
1330
1331 HOWTO (R_ARM_THM_MOVT_BREL, /* type */
1332 0, /* rightshift */
1333 2, /* size (0 = byte, 1 = short, 2 = long) */
1334 16, /* bitsize */
1335 FALSE, /* pc_relative */
1336 0, /* bitpos */
1337 complain_overflow_bitfield,/* complain_on_overflow */
1338 bfd_elf_generic_reloc, /* special_function */
1339 "R_ARM_THM_MOVT_BREL", /* name */
1340 FALSE, /* partial_inplace */
1341 0x040f70ff, /* src_mask */
1342 0x040f70ff, /* dst_mask */
1343 FALSE), /* pcrel_offset */
1344
1345 HOWTO (R_ARM_THM_MOVW_BREL, /* type */
1346 0, /* rightshift */
1347 2, /* size (0 = byte, 1 = short, 2 = long) */
1348 16, /* bitsize */
1349 FALSE, /* pc_relative */
1350 0, /* bitpos */
1351 complain_overflow_dont,/* complain_on_overflow */
1352 bfd_elf_generic_reloc, /* special_function */
1353 "R_ARM_THM_MOVW_BREL", /* name */
1354 FALSE, /* partial_inplace */
1355 0x040f70ff, /* src_mask */
1356 0x040f70ff, /* dst_mask */
1357 FALSE), /* pcrel_offset */
1358
0855e32b
NS		 1359 HOWTO (R_ARM_TLS_GOTDESC, /* type */
1360 0, /* rightshift */
1361 2, /* size (0 = byte, 1 = short, 2 = long) */
1362 32, /* bitsize */
1363 FALSE, /* pc_relative */
1364 0, /* bitpos */
1365 complain_overflow_bitfield,/* complain_on_overflow */
1366 NULL, /* special_function */
1367 "R_ARM_TLS_GOTDESC", /* name */
1368 TRUE, /* partial_inplace */
1369 0xffffffff, /* src_mask */
1370 0xffffffff, /* dst_mask */
1371 FALSE), /* pcrel_offset */
1372
1373 HOWTO (R_ARM_TLS_CALL, /* type */
1374 0, /* rightshift */
1375 2, /* size (0 = byte, 1 = short, 2 = long) */
1376 24, /* bitsize */
1377 FALSE, /* pc_relative */
1378 0, /* bitpos */
1379 complain_overflow_dont,/* complain_on_overflow */
1380 bfd_elf_generic_reloc, /* special_function */
1381 "R_ARM_TLS_CALL", /* name */
1382 FALSE, /* partial_inplace */
1383 0x00ffffff, /* src_mask */
1384 0x00ffffff, /* dst_mask */
1385 FALSE), /* pcrel_offset */
1386
1387 HOWTO (R_ARM_TLS_DESCSEQ, /* type */
1388 0, /* rightshift */
1389 2, /* size (0 = byte, 1 = short, 2 = long) */
1390 0, /* bitsize */
1391 FALSE, /* pc_relative */
1392 0, /* bitpos */
1393 complain_overflow_bitfield,/* complain_on_overflow */
1394 bfd_elf_generic_reloc, /* special_function */
1395 "R_ARM_TLS_DESCSEQ", /* name */
1396 FALSE, /* partial_inplace */
1397 0x00000000, /* src_mask */
1398 0x00000000, /* dst_mask */
1399 FALSE), /* pcrel_offset */
1400
1401 HOWTO (R_ARM_THM_TLS_CALL, /* type */
1402 0, /* rightshift */
1403 2, /* size (0 = byte, 1 = short, 2 = long) */
1404 24, /* bitsize */
1405 FALSE, /* pc_relative */
1406 0, /* bitpos */
1407 complain_overflow_dont,/* complain_on_overflow */
1408 bfd_elf_generic_reloc, /* special_function */
1409 "R_ARM_THM_TLS_CALL", /* name */
1410 FALSE, /* partial_inplace */
1411 0x07ff07ff, /* src_mask */
1412 0x07ff07ff, /* dst_mask */
1413 FALSE), /* pcrel_offset */
c19d1205
ZW		 1414
1415 HOWTO (R_ARM_PLT32_ABS, /* type */
1416 0, /* rightshift */
1417 2, /* size (0 = byte, 1 = short, 2 = long) */
1418 32, /* bitsize */
1419 FALSE, /* pc_relative */
1420 0, /* bitpos */
1421 complain_overflow_dont,/* complain_on_overflow */
1422 bfd_elf_generic_reloc, /* special_function */
1423 "R_ARM_PLT32_ABS", /* name */
1424 FALSE, /* partial_inplace */
1425 0xffffffff, /* src_mask */
1426 0xffffffff, /* dst_mask */
1427 FALSE), /* pcrel_offset */
1428
1429 HOWTO (R_ARM_GOT_ABS, /* type */
1430 0, /* rightshift */
1431 2, /* size (0 = byte, 1 = short, 2 = long) */
1432 32, /* bitsize */
1433 FALSE, /* pc_relative */
1434 0, /* bitpos */
1435 complain_overflow_dont,/* complain_on_overflow */
1436 bfd_elf_generic_reloc, /* special_function */
1437 "R_ARM_GOT_ABS", /* name */
1438 FALSE, /* partial_inplace */
1439 0xffffffff, /* src_mask */
1440 0xffffffff, /* dst_mask */
1441 FALSE), /* pcrel_offset */
1442
1443 HOWTO (R_ARM_GOT_PREL, /* type */
1444 0, /* rightshift */
1445 2, /* size (0 = byte, 1 = short, 2 = long) */
1446 32, /* bitsize */
1447 TRUE, /* pc_relative */
1448 0, /* bitpos */
1449 complain_overflow_dont, /* complain_on_overflow */
1450 bfd_elf_generic_reloc, /* special_function */
1451 "R_ARM_GOT_PREL", /* name */
1452 FALSE, /* partial_inplace */
1453 0xffffffff, /* src_mask */
1454 0xffffffff, /* dst_mask */
1455 TRUE), /* pcrel_offset */
1456
1457 HOWTO (R_ARM_GOT_BREL12, /* type */
1458 0, /* rightshift */
1459 2, /* size (0 = byte, 1 = short, 2 = long) */
1460 12, /* bitsize */
1461 FALSE, /* pc_relative */
1462 0, /* bitpos */
1463 complain_overflow_bitfield,/* complain_on_overflow */
1464 bfd_elf_generic_reloc, /* special_function */
1465 "R_ARM_GOT_BREL12", /* name */
1466 FALSE, /* partial_inplace */
1467 0x00000fff, /* src_mask */
1468 0x00000fff, /* dst_mask */
1469 FALSE), /* pcrel_offset */
1470
1471 HOWTO (R_ARM_GOTOFF12, /* type */
1472 0, /* rightshift */
1473 2, /* size (0 = byte, 1 = short, 2 = long) */
1474 12, /* bitsize */
1475 FALSE, /* pc_relative */
1476 0, /* bitpos */
1477 complain_overflow_bitfield,/* complain_on_overflow */
1478 bfd_elf_generic_reloc, /* special_function */
1479 "R_ARM_GOTOFF12", /* name */
1480 FALSE, /* partial_inplace */
1481 0x00000fff, /* src_mask */
1482 0x00000fff, /* dst_mask */
1483 FALSE), /* pcrel_offset */
1484
1485 EMPTY_HOWTO (R_ARM_GOTRELAX), /* reserved for future GOT-load optimizations */
1486
1487 /* GNU extension to record C++ vtable member usage */
1488 HOWTO (R_ARM_GNU_VTENTRY, /* type */
99059e56
RM		 1489 0, /* rightshift */
1490 2, /* size (0 = byte, 1 = short, 2 = long) */
1491 0, /* bitsize */
1492 FALSE, /* pc_relative */
1493 0, /* bitpos */
1494 complain_overflow_dont, /* complain_on_overflow */
1495 _bfd_elf_rel_vtable_reloc_fn, /* special_function */
1496 "R_ARM_GNU_VTENTRY", /* name */
1497 FALSE, /* partial_inplace */
1498 0, /* src_mask */
1499 0, /* dst_mask */
1500 FALSE), /* pcrel_offset */
c19d1205
ZW		 1501
1502 /* GNU extension to record C++ vtable hierarchy */
1503 HOWTO (R_ARM_GNU_VTINHERIT, /* type */
99059e56
RM		 1504 0, /* rightshift */
1505 2, /* size (0 = byte, 1 = short, 2 = long) */
1506 0, /* bitsize */
1507 FALSE, /* pc_relative */
1508 0, /* bitpos */
1509 complain_overflow_dont, /* complain_on_overflow */
1510 NULL, /* special_function */
1511 "R_ARM_GNU_VTINHERIT", /* name */
1512 FALSE, /* partial_inplace */
1513 0, /* src_mask */
1514 0, /* dst_mask */
1515 FALSE), /* pcrel_offset */
c19d1205
ZW		 1516
1517 HOWTO (R_ARM_THM_JUMP11, /* type */
1518 1, /* rightshift */
1519 1, /* size (0 = byte, 1 = short, 2 = long) */
1520 11, /* bitsize */
1521 TRUE, /* pc_relative */
1522 0, /* bitpos */
1523 complain_overflow_signed, /* complain_on_overflow */
1524 bfd_elf_generic_reloc, /* special_function */
1525 "R_ARM_THM_JUMP11", /* name */
1526 FALSE, /* partial_inplace */
1527 0x000007ff, /* src_mask */
1528 0x000007ff, /* dst_mask */
1529 TRUE), /* pcrel_offset */
1530
1531 HOWTO (R_ARM_THM_JUMP8, /* type */
1532 1, /* rightshift */
1533 1, /* size (0 = byte, 1 = short, 2 = long) */
1534 8, /* bitsize */
1535 TRUE, /* pc_relative */
1536 0, /* bitpos */
1537 complain_overflow_signed, /* complain_on_overflow */
1538 bfd_elf_generic_reloc, /* special_function */
1539 "R_ARM_THM_JUMP8", /* name */
1540 FALSE, /* partial_inplace */
1541 0x000000ff, /* src_mask */
1542 0x000000ff, /* dst_mask */
1543 TRUE), /* pcrel_offset */
ba93b8ac 1544
c19d1205
ZW		 1545 /* TLS relocations */
1546 HOWTO (R_ARM_TLS_GD32, /* type */
99059e56
RM		 1547 0, /* rightshift */
1548 2, /* size (0 = byte, 1 = short, 2 = long) */
1549 32, /* bitsize */
1550 FALSE, /* pc_relative */
1551 0, /* bitpos */
1552 complain_overflow_bitfield,/* complain_on_overflow */
1553 NULL, /* special_function */
1554 "R_ARM_TLS_GD32", /* name */
1555 TRUE, /* partial_inplace */
1556 0xffffffff, /* src_mask */
1557 0xffffffff, /* dst_mask */
1558 FALSE), /* pcrel_offset */
ba93b8ac 1559
ba93b8ac 1560 HOWTO (R_ARM_TLS_LDM32, /* type */
99059e56
RM		 1561 0, /* rightshift */
1562 2, /* size (0 = byte, 1 = short, 2 = long) */
1563 32, /* bitsize */
1564 FALSE, /* pc_relative */
1565 0, /* bitpos */
1566 complain_overflow_bitfield,/* complain_on_overflow */
1567 bfd_elf_generic_reloc, /* special_function */
1568 "R_ARM_TLS_LDM32", /* name */
1569 TRUE, /* partial_inplace */
1570 0xffffffff, /* src_mask */
1571 0xffffffff, /* dst_mask */
1572 FALSE), /* pcrel_offset */
ba93b8ac 1573
c19d1205 1574 HOWTO (R_ARM_TLS_LDO32, /* type */
99059e56
RM		 1575 0, /* rightshift */
1576 2, /* size (0 = byte, 1 = short, 2 = long) */
1577 32, /* bitsize */
1578 FALSE, /* pc_relative */
1579 0, /* bitpos */
1580 complain_overflow_bitfield,/* complain_on_overflow */
1581 bfd_elf_generic_reloc, /* special_function */
1582 "R_ARM_TLS_LDO32", /* name */
1583 TRUE, /* partial_inplace */
1584 0xffffffff, /* src_mask */
1585 0xffffffff, /* dst_mask */
1586 FALSE), /* pcrel_offset */
ba93b8ac 1587
ba93b8ac 1588 HOWTO (R_ARM_TLS_IE32, /* type */
99059e56
RM		 1589 0, /* rightshift */
1590 2, /* size (0 = byte, 1 = short, 2 = long) */
1591 32, /* bitsize */
1592 FALSE, /* pc_relative */
1593 0, /* bitpos */
1594 complain_overflow_bitfield,/* complain_on_overflow */
1595 NULL, /* special_function */
1596 "R_ARM_TLS_IE32", /* name */
1597 TRUE, /* partial_inplace */
1598 0xffffffff, /* src_mask */
1599 0xffffffff, /* dst_mask */
1600 FALSE), /* pcrel_offset */
7f266840 1601
c19d1205 1602 HOWTO (R_ARM_TLS_LE32, /* type */
99059e56
RM		 1603 0, /* rightshift */
1604 2, /* size (0 = byte, 1 = short, 2 = long) */
1605 32, /* bitsize */
1606 FALSE, /* pc_relative */
1607 0, /* bitpos */
1608 complain_overflow_bitfield,/* complain_on_overflow */
75c11999 1609 NULL, /* special_function */
99059e56
RM		 1610 "R_ARM_TLS_LE32", /* name */
1611 TRUE, /* partial_inplace */
1612 0xffffffff, /* src_mask */
1613 0xffffffff, /* dst_mask */
1614 FALSE), /* pcrel_offset */
7f266840 1615
c19d1205
ZW		 1616 HOWTO (R_ARM_TLS_LDO12, /* type */
1617 0, /* rightshift */
1618 2, /* size (0 = byte, 1 = short, 2 = long) */
1619 12, /* bitsize */
1620 FALSE, /* pc_relative */
7f266840 1621 0, /* bitpos */
c19d1205 1622 complain_overflow_bitfield,/* complain_on_overflow */
7f266840 1623 bfd_elf_generic_reloc, /* special_function */
c19d1205 1624 "R_ARM_TLS_LDO12", /* name */
7f266840 1625 FALSE, /* partial_inplace */
c19d1205
ZW		 1626 0x00000fff, /* src_mask */
1627 0x00000fff, /* dst_mask */
1628 FALSE), /* pcrel_offset */
7f266840 1629
c19d1205
ZW		 1630 HOWTO (R_ARM_TLS_LE12, /* type */
1631 0, /* rightshift */
1632 2, /* size (0 = byte, 1 = short, 2 = long) */
1633 12, /* bitsize */
1634 FALSE, /* pc_relative */
7f266840 1635 0, /* bitpos */
c19d1205 1636 complain_overflow_bitfield,/* complain_on_overflow */
7f266840 1637 bfd_elf_generic_reloc, /* special_function */
c19d1205 1638 "R_ARM_TLS_LE12", /* name */
7f266840 1639 FALSE, /* partial_inplace */
c19d1205
ZW		 1640 0x00000fff, /* src_mask */
1641 0x00000fff, /* dst_mask */
1642 FALSE), /* pcrel_offset */
7f266840 1643
c19d1205 1644 HOWTO (R_ARM_TLS_IE12GP, /* type */
7f266840
DJ		 1645 0, /* rightshift */
1646 2, /* size (0 = byte, 1 = short, 2 = long) */
c19d1205
ZW		 1647 12, /* bitsize */
1648 FALSE, /* pc_relative */
7f266840 1649 0, /* bitpos */
c19d1205 1650 complain_overflow_bitfield,/* complain_on_overflow */
7f266840 1651 bfd_elf_generic_reloc, /* special_function */
c19d1205 1652 "R_ARM_TLS_IE12GP", /* name */
7f266840 1653 FALSE, /* partial_inplace */
c19d1205
ZW		 1654 0x00000fff, /* src_mask */
1655 0x00000fff, /* dst_mask */
1656 FALSE), /* pcrel_offset */
0855e32b 1657
34e77a92 1658 /* 112-127 private relocations. */
0855e32b
NS		 1659 EMPTY_HOWTO (112),
1660 EMPTY_HOWTO (113),
1661 EMPTY_HOWTO (114),
1662 EMPTY_HOWTO (115),
1663 EMPTY_HOWTO (116),
1664 EMPTY_HOWTO (117),
1665 EMPTY_HOWTO (118),
1666 EMPTY_HOWTO (119),
1667 EMPTY_HOWTO (120),
1668 EMPTY_HOWTO (121),
1669 EMPTY_HOWTO (122),
1670 EMPTY_HOWTO (123),
1671 EMPTY_HOWTO (124),
1672 EMPTY_HOWTO (125),
1673 EMPTY_HOWTO (126),
1674 EMPTY_HOWTO (127),
34e77a92
RS		 1675
1676 /* R_ARM_ME_TOO, obsolete. */
0855e32b
NS		 1677 EMPTY_HOWTO (128),
1678
1679 HOWTO (R_ARM_THM_TLS_DESCSEQ, /* type */
1680 0, /* rightshift */
1681 1, /* size (0 = byte, 1 = short, 2 = long) */
1682 0, /* bitsize */
1683 FALSE, /* pc_relative */
1684 0, /* bitpos */
1685 complain_overflow_bitfield,/* complain_on_overflow */
1686 bfd_elf_generic_reloc, /* special_function */
1687 "R_ARM_THM_TLS_DESCSEQ",/* name */
1688 FALSE, /* partial_inplace */
1689 0x00000000, /* src_mask */
1690 0x00000000, /* dst_mask */
1691 FALSE), /* pcrel_offset */
72d98d16
MG		 1692 EMPTY_HOWTO (130),
1693 EMPTY_HOWTO (131),
1694 HOWTO (R_ARM_THM_ALU_ABS_G0_NC,/* type. */
1695 0, /* rightshift. */
1696 1, /* size (0 = byte, 1 = short, 2 = long). */
1697 16, /* bitsize. */
1698 FALSE, /* pc_relative. */
1699 0, /* bitpos. */
1700 complain_overflow_bitfield,/* complain_on_overflow. */
1701 bfd_elf_generic_reloc, /* special_function. */
1702 "R_ARM_THM_ALU_ABS_G0_NC",/* name. */
1703 FALSE, /* partial_inplace. */
1704 0x00000000, /* src_mask. */
1705 0x00000000, /* dst_mask. */
1706 FALSE), /* pcrel_offset. */
1707 HOWTO (R_ARM_THM_ALU_ABS_G1_NC,/* type. */
1708 0, /* rightshift. */
1709 1, /* size (0 = byte, 1 = short, 2 = long). */
1710 16, /* bitsize. */
1711 FALSE, /* pc_relative. */
1712 0, /* bitpos. */
1713 complain_overflow_bitfield,/* complain_on_overflow. */
1714 bfd_elf_generic_reloc, /* special_function. */
1715 "R_ARM_THM_ALU_ABS_G1_NC",/* name. */
1716 FALSE, /* partial_inplace. */
1717 0x00000000, /* src_mask. */
1718 0x00000000, /* dst_mask. */
1719 FALSE), /* pcrel_offset. */
1720 HOWTO (R_ARM_THM_ALU_ABS_G2_NC,/* type. */
1721 0, /* rightshift. */
1722 1, /* size (0 = byte, 1 = short, 2 = long). */
1723 16, /* bitsize. */
1724 FALSE, /* pc_relative. */
1725 0, /* bitpos. */
1726 complain_overflow_bitfield,/* complain_on_overflow. */
1727 bfd_elf_generic_reloc, /* special_function. */
1728 "R_ARM_THM_ALU_ABS_G2_NC",/* name. */
1729 FALSE, /* partial_inplace. */
1730 0x00000000, /* src_mask. */
1731 0x00000000, /* dst_mask. */
1732 FALSE), /* pcrel_offset. */
1733 HOWTO (R_ARM_THM_ALU_ABS_G3_NC,/* type. */
1734 0, /* rightshift. */
1735 1, /* size (0 = byte, 1 = short, 2 = long). */
1736 16, /* bitsize. */
1737 FALSE, /* pc_relative. */
1738 0, /* bitpos. */
1739 complain_overflow_bitfield,/* complain_on_overflow. */
1740 bfd_elf_generic_reloc, /* special_function. */
1741 "R_ARM_THM_ALU_ABS_G3_NC",/* name. */
1742 FALSE, /* partial_inplace. */
1743 0x00000000, /* src_mask. */
1744 0x00000000, /* dst_mask. */
1745 FALSE), /* pcrel_offset. */
c19d1205
ZW		 1746};
1747
34e77a92
RS		 1748/* 160 onwards: */
1749static reloc_howto_type elf32_arm_howto_table_2[1] =
1750{
1751 HOWTO (R_ARM_IRELATIVE, /* type */
99059e56
RM		 1752 0, /* rightshift */
1753 2, /* size (0 = byte, 1 = short, 2 = long) */
1754 32, /* bitsize */
1755 FALSE, /* pc_relative */
1756 0, /* bitpos */
1757 complain_overflow_bitfield,/* complain_on_overflow */
1758 bfd_elf_generic_reloc, /* special_function */
1759 "R_ARM_IRELATIVE", /* name */
1760 TRUE, /* partial_inplace */
1761 0xffffffff, /* src_mask */
1762 0xffffffff, /* dst_mask */
1763 FALSE) /* pcrel_offset */
34e77a92 1764};
c19d1205 1765
34e77a92
RS		 1766/* 249-255 extended, currently unused, relocations: */
1767static reloc_howto_type elf32_arm_howto_table_3[4] =
7f266840
DJ		 1768{
1769 HOWTO (R_ARM_RREL32, /* type */
1770 0, /* rightshift */
1771 0, /* size (0 = byte, 1 = short, 2 = long) */
1772 0, /* bitsize */
1773 FALSE, /* pc_relative */
1774 0, /* bitpos */
1775 complain_overflow_dont,/* complain_on_overflow */
1776 bfd_elf_generic_reloc, /* special_function */
1777 "R_ARM_RREL32", /* name */
1778 FALSE, /* partial_inplace */
1779 0, /* src_mask */
1780 0, /* dst_mask */
1781 FALSE), /* pcrel_offset */
1782
1783 HOWTO (R_ARM_RABS32, /* type */
1784 0, /* rightshift */
1785 0, /* size (0 = byte, 1 = short, 2 = long) */
1786 0, /* bitsize */
1787 FALSE, /* pc_relative */
1788 0, /* bitpos */
1789 complain_overflow_dont,/* complain_on_overflow */
1790 bfd_elf_generic_reloc, /* special_function */
1791 "R_ARM_RABS32", /* name */
1792 FALSE, /* partial_inplace */
1793 0, /* src_mask */
1794 0, /* dst_mask */
1795 FALSE), /* pcrel_offset */
1796
1797 HOWTO (R_ARM_RPC24, /* type */
1798 0, /* rightshift */
1799 0, /* size (0 = byte, 1 = short, 2 = long) */
1800 0, /* bitsize */
1801 FALSE, /* pc_relative */
1802 0, /* bitpos */
1803 complain_overflow_dont,/* complain_on_overflow */
1804 bfd_elf_generic_reloc, /* special_function */
1805 "R_ARM_RPC24", /* name */
1806 FALSE, /* partial_inplace */
1807 0, /* src_mask */
1808 0, /* dst_mask */
1809 FALSE), /* pcrel_offset */
1810
1811 HOWTO (R_ARM_RBASE, /* type */
1812 0, /* rightshift */
1813 0, /* size (0 = byte, 1 = short, 2 = long) */
1814 0, /* bitsize */
1815 FALSE, /* pc_relative */
1816 0, /* bitpos */
1817 complain_overflow_dont,/* complain_on_overflow */
1818 bfd_elf_generic_reloc, /* special_function */
1819 "R_ARM_RBASE", /* name */
1820 FALSE, /* partial_inplace */
1821 0, /* src_mask */
1822 0, /* dst_mask */
1823 FALSE) /* pcrel_offset */
1824};
1825
1826static reloc_howto_type *
1827elf32_arm_howto_from_type (unsigned int r_type)
1828{
906e58ca 1829 if (r_type < ARRAY_SIZE (elf32_arm_howto_table_1))
c19d1205 1830 return &elf32_arm_howto_table_1[r_type];
ba93b8ac 1831
34e77a92
RS		 1832 if (r_type == R_ARM_IRELATIVE)
1833 return &elf32_arm_howto_table_2[r_type - R_ARM_IRELATIVE];
1834
c19d1205 1835 if (r_type >= R_ARM_RREL32
34e77a92
RS		 1836 && r_type < R_ARM_RREL32 + ARRAY_SIZE (elf32_arm_howto_table_3))
1837 return &elf32_arm_howto_table_3[r_type - R_ARM_RREL32];
7f266840 1838
c19d1205 1839 return NULL;
7f266840
DJ		 1840}
1841
1842static void
1843elf32_arm_info_to_howto (bfd * abfd ATTRIBUTE_UNUSED, arelent * bfd_reloc,
1844 Elf_Internal_Rela * elf_reloc)
1845{
1846 unsigned int r_type;
1847
1848 r_type = ELF32_R_TYPE (elf_reloc->r_info);
1849 bfd_reloc->howto = elf32_arm_howto_from_type (r_type);
1850}
1851
1852struct elf32_arm_reloc_map
1853 {
1854 bfd_reloc_code_real_type bfd_reloc_val;
1855 unsigned char elf_reloc_val;
1856 };
1857
1858/* All entries in this list must also be present in elf32_arm_howto_table. */
1859static const struct elf32_arm_reloc_map elf32_arm_reloc_map[] =
1860 {
1861 {BFD_RELOC_NONE, R_ARM_NONE},
1862 {BFD_RELOC_ARM_PCREL_BRANCH, R_ARM_PC24},
39b41c9c
PB		 1863 {BFD_RELOC_ARM_PCREL_CALL, R_ARM_CALL},
1864 {BFD_RELOC_ARM_PCREL_JUMP, R_ARM_JUMP24},
7f266840
DJ		 1865 {BFD_RELOC_ARM_PCREL_BLX, R_ARM_XPC25},
1866 {BFD_RELOC_THUMB_PCREL_BLX, R_ARM_THM_XPC22},
1867 {BFD_RELOC_32, R_ARM_ABS32},
1868 {BFD_RELOC_32_PCREL, R_ARM_REL32},
1869 {BFD_RELOC_8, R_ARM_ABS8},
1870 {BFD_RELOC_16, R_ARM_ABS16},
1871 {BFD_RELOC_ARM_OFFSET_IMM, R_ARM_ABS12},
1872 {BFD_RELOC_ARM_THUMB_OFFSET, R_ARM_THM_ABS5},
c19d1205
ZW		 1873 {BFD_RELOC_THUMB_PCREL_BRANCH25, R_ARM_THM_JUMP24},
1874 {BFD_RELOC_THUMB_PCREL_BRANCH23, R_ARM_THM_CALL},
1875 {BFD_RELOC_THUMB_PCREL_BRANCH12, R_ARM_THM_JUMP11},
1876 {BFD_RELOC_THUMB_PCREL_BRANCH20, R_ARM_THM_JUMP19},
1877 {BFD_RELOC_THUMB_PCREL_BRANCH9, R_ARM_THM_JUMP8},
1878 {BFD_RELOC_THUMB_PCREL_BRANCH7, R_ARM_THM_JUMP6},
7f266840
DJ		 1879 {BFD_RELOC_ARM_GLOB_DAT, R_ARM_GLOB_DAT},
1880 {BFD_RELOC_ARM_JUMP_SLOT, R_ARM_JUMP_SLOT},
1881 {BFD_RELOC_ARM_RELATIVE, R_ARM_RELATIVE},
c19d1205 1882 {BFD_RELOC_ARM_GOTOFF, R_ARM_GOTOFF32},
7f266840 1883 {BFD_RELOC_ARM_GOTPC, R_ARM_GOTPC},
b43420e6 1884 {BFD_RELOC_ARM_GOT_PREL, R_ARM_GOT_PREL},
7f266840
DJ		 1885 {BFD_RELOC_ARM_GOT32, R_ARM_GOT32},
1886 {BFD_RELOC_ARM_PLT32, R_ARM_PLT32},
1887 {BFD_RELOC_ARM_TARGET1, R_ARM_TARGET1},
1888 {BFD_RELOC_ARM_ROSEGREL32, R_ARM_ROSEGREL32},
1889 {BFD_RELOC_ARM_SBREL32, R_ARM_SBREL32},
1890 {BFD_RELOC_ARM_PREL31, R_ARM_PREL31},
ba93b8ac
DJ		 1891 {BFD_RELOC_ARM_TARGET2, R_ARM_TARGET2},
1892 {BFD_RELOC_ARM_PLT32, R_ARM_PLT32},
0855e32b
NS		 1893 {BFD_RELOC_ARM_TLS_GOTDESC, R_ARM_TLS_GOTDESC},
1894 {BFD_RELOC_ARM_TLS_CALL, R_ARM_TLS_CALL},
1895 {BFD_RELOC_ARM_THM_TLS_CALL, R_ARM_THM_TLS_CALL},
1896 {BFD_RELOC_ARM_TLS_DESCSEQ, R_ARM_TLS_DESCSEQ},
1897 {BFD_RELOC_ARM_THM_TLS_DESCSEQ, R_ARM_THM_TLS_DESCSEQ},
1898 {BFD_RELOC_ARM_TLS_DESC, R_ARM_TLS_DESC},
ba93b8ac
DJ		 1899 {BFD_RELOC_ARM_TLS_GD32, R_ARM_TLS_GD32},
1900 {BFD_RELOC_ARM_TLS_LDO32, R_ARM_TLS_LDO32},
1901 {BFD_RELOC_ARM_TLS_LDM32, R_ARM_TLS_LDM32},
1902 {BFD_RELOC_ARM_TLS_DTPMOD32, R_ARM_TLS_DTPMOD32},
1903 {BFD_RELOC_ARM_TLS_DTPOFF32, R_ARM_TLS_DTPOFF32},
1904 {BFD_RELOC_ARM_TLS_TPOFF32, R_ARM_TLS_TPOFF32},
1905 {BFD_RELOC_ARM_TLS_IE32, R_ARM_TLS_IE32},
1906 {BFD_RELOC_ARM_TLS_LE32, R_ARM_TLS_LE32},
34e77a92 1907 {BFD_RELOC_ARM_IRELATIVE, R_ARM_IRELATIVE},
c19d1205
ZW		 1908 {BFD_RELOC_VTABLE_INHERIT, R_ARM_GNU_VTINHERIT},
1909 {BFD_RELOC_VTABLE_ENTRY, R_ARM_GNU_VTENTRY},
b6895b4f
PB		 1910 {BFD_RELOC_ARM_MOVW, R_ARM_MOVW_ABS_NC},
1911 {BFD_RELOC_ARM_MOVT, R_ARM_MOVT_ABS},
1912 {BFD_RELOC_ARM_MOVW_PCREL, R_ARM_MOVW_PREL_NC},
1913 {BFD_RELOC_ARM_MOVT_PCREL, R_ARM_MOVT_PREL},
1914 {BFD_RELOC_ARM_THUMB_MOVW, R_ARM_THM_MOVW_ABS_NC},
1915 {BFD_RELOC_ARM_THUMB_MOVT, R_ARM_THM_MOVT_ABS},
1916 {BFD_RELOC_ARM_THUMB_MOVW_PCREL, R_ARM_THM_MOVW_PREL_NC},
1917 {BFD_RELOC_ARM_THUMB_MOVT_PCREL, R_ARM_THM_MOVT_PREL},
4962c51a
MS		 1918 {BFD_RELOC_ARM_ALU_PC_G0_NC, R_ARM_ALU_PC_G0_NC},
1919 {BFD_RELOC_ARM_ALU_PC_G0, R_ARM_ALU_PC_G0},
1920 {BFD_RELOC_ARM_ALU_PC_G1_NC, R_ARM_ALU_PC_G1_NC},
1921 {BFD_RELOC_ARM_ALU_PC_G1, R_ARM_ALU_PC_G1},
1922 {BFD_RELOC_ARM_ALU_PC_G2, R_ARM_ALU_PC_G2},
1923 {BFD_RELOC_ARM_LDR_PC_G0, R_ARM_LDR_PC_G0},
1924 {BFD_RELOC_ARM_LDR_PC_G1, R_ARM_LDR_PC_G1},
1925 {BFD_RELOC_ARM_LDR_PC_G2, R_ARM_LDR_PC_G2},
1926 {BFD_RELOC_ARM_LDRS_PC_G0, R_ARM_LDRS_PC_G0},
1927 {BFD_RELOC_ARM_LDRS_PC_G1, R_ARM_LDRS_PC_G1},
1928 {BFD_RELOC_ARM_LDRS_PC_G2, R_ARM_LDRS_PC_G2},
1929 {BFD_RELOC_ARM_LDC_PC_G0, R_ARM_LDC_PC_G0},
1930 {BFD_RELOC_ARM_LDC_PC_G1, R_ARM_LDC_PC_G1},
1931 {BFD_RELOC_ARM_LDC_PC_G2, R_ARM_LDC_PC_G2},
1932 {BFD_RELOC_ARM_ALU_SB_G0_NC, R_ARM_ALU_SB_G0_NC},
1933 {BFD_RELOC_ARM_ALU_SB_G0, R_ARM_ALU_SB_G0},
1934 {BFD_RELOC_ARM_ALU_SB_G1_NC, R_ARM_ALU_SB_G1_NC},
1935 {BFD_RELOC_ARM_ALU_SB_G1, R_ARM_ALU_SB_G1},
1936 {BFD_RELOC_ARM_ALU_SB_G2, R_ARM_ALU_SB_G2},
1937 {BFD_RELOC_ARM_LDR_SB_G0, R_ARM_LDR_SB_G0},
1938 {BFD_RELOC_ARM_LDR_SB_G1, R_ARM_LDR_SB_G1},
1939 {BFD_RELOC_ARM_LDR_SB_G2, R_ARM_LDR_SB_G2},
1940 {BFD_RELOC_ARM_LDRS_SB_G0, R_ARM_LDRS_SB_G0},
1941 {BFD_RELOC_ARM_LDRS_SB_G1, R_ARM_LDRS_SB_G1},
1942 {BFD_RELOC_ARM_LDRS_SB_G2, R_ARM_LDRS_SB_G2},
1943 {BFD_RELOC_ARM_LDC_SB_G0, R_ARM_LDC_SB_G0},
1944 {BFD_RELOC_ARM_LDC_SB_G1, R_ARM_LDC_SB_G1},
845b51d6 1945 {BFD_RELOC_ARM_LDC_SB_G2, R_ARM_LDC_SB_G2},
72d98d16
MG		 1946 {BFD_RELOC_ARM_V4BX, R_ARM_V4BX},
1947 {BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC, R_ARM_THM_ALU_ABS_G3_NC},
1948 {BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC, R_ARM_THM_ALU_ABS_G2_NC},
1949 {BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC, R_ARM_THM_ALU_ABS_G1_NC},
1950 {BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC, R_ARM_THM_ALU_ABS_G0_NC}
7f266840
DJ		 1951 };
1952
1953static reloc_howto_type *
f1c71a59
ZW		 1954elf32_arm_reloc_type_lookup (bfd *abfd ATTRIBUTE_UNUSED,
1955 bfd_reloc_code_real_type code)
7f266840
DJ		 1956{
1957 unsigned int i;
8029a119 1958
906e58ca 1959 for (i = 0; i < ARRAY_SIZE (elf32_arm_reloc_map); i ++)
c19d1205
ZW		 1960 if (elf32_arm_reloc_map[i].bfd_reloc_val == code)
1961 return elf32_arm_howto_from_type (elf32_arm_reloc_map[i].elf_reloc_val);
7f266840 1962
c19d1205 1963 return NULL;
7f266840
DJ		 1964}
1965
157090f7
AM		 1966static reloc_howto_type *
1967elf32_arm_reloc_name_lookup (bfd *abfd ATTRIBUTE_UNUSED,
1968 const char *r_name)
1969{
1970 unsigned int i;
1971
906e58ca 1972 for (i = 0; i < ARRAY_SIZE (elf32_arm_howto_table_1); i++)
157090f7
AM		 1973 if (elf32_arm_howto_table_1[i].name != NULL
1974 && strcasecmp (elf32_arm_howto_table_1[i].name, r_name) == 0)
1975 return &elf32_arm_howto_table_1[i];
1976
906e58ca 1977 for (i = 0; i < ARRAY_SIZE (elf32_arm_howto_table_2); i++)
157090f7
AM		 1978 if (elf32_arm_howto_table_2[i].name != NULL
1979 && strcasecmp (elf32_arm_howto_table_2[i].name, r_name) == 0)
1980 return &elf32_arm_howto_table_2[i];
1981
34e77a92
RS		 1982 for (i = 0; i < ARRAY_SIZE (elf32_arm_howto_table_3); i++)
1983 if (elf32_arm_howto_table_3[i].name != NULL
1984 && strcasecmp (elf32_arm_howto_table_3[i].name, r_name) == 0)
1985 return &elf32_arm_howto_table_3[i];
1986
157090f7
AM		 1987 return NULL;
1988}
1989
906e58ca
NC		 1990/* Support for core dump NOTE sections. */
1991
7f266840 1992static bfd_boolean
f1c71a59 1993elf32_arm_nabi_grok_prstatus (bfd *abfd, Elf_Internal_Note *note)
7f266840
DJ		 1994{
1995 int offset;
1996 size_t size;
1997
1998 switch (note->descsz)
1999 {
2000 default:
2001 return FALSE;
2002
8029a119 2003 case 148: /* Linux/ARM 32-bit. */
7f266840 2004 /* pr_cursig */
228e534f 2005 elf_tdata (abfd)->core->signal = bfd_get_16 (abfd, note->descdata + 12);
7f266840
DJ		 2006
2007 /* pr_pid */
228e534f 2008 elf_tdata (abfd)->core->lwpid = bfd_get_32 (abfd, note->descdata + 24);
7f266840
DJ		 2009
2010 /* pr_reg */
2011 offset = 72;
2012 size = 72;
2013
2014 break;
2015 }
2016
2017 /* Make a ".reg/999" section. */
2018 return _bfd_elfcore_make_pseudosection (abfd, ".reg",
2019 size, note->descpos + offset);
2020}
2021
2022static bfd_boolean
f1c71a59 2023elf32_arm_nabi_grok_psinfo (bfd *abfd, Elf_Internal_Note *note)
7f266840
DJ		 2024{
2025 switch (note->descsz)
2026 {
2027 default:
2028 return FALSE;
2029
8029a119 2030 case 124: /* Linux/ARM elf_prpsinfo. */
228e534f 2031 elf_tdata (abfd)->core->pid
4395ee08 2032 = bfd_get_32 (abfd, note->descdata + 12);
228e534f 2033 elf_tdata (abfd)->core->program
7f266840 2034 = _bfd_elfcore_strndup (abfd, note->descdata + 28, 16);
228e534f 2035 elf_tdata (abfd)->core->command
7f266840
DJ		 2036 = _bfd_elfcore_strndup (abfd, note->descdata + 44, 80);
2037 }
2038
2039 /* Note that for some reason, a spurious space is tacked
2040 onto the end of the args in some (at least one anyway)
2041 implementations, so strip it off if it exists. */
7f266840 2042 {
228e534f 2043 char *command = elf_tdata (abfd)->core->command;
7f266840
DJ		 2044 int n = strlen (command);
2045
2046 if (0 < n && command[n - 1] == ' ')
2047 command[n - 1] = '\0';
2048 }
2049
2050 return TRUE;
2051}
2052
1f20dca5
UW		 2053static char *
2054elf32_arm_nabi_write_core_note (bfd *abfd, char *buf, int *bufsiz,
2055 int note_type, ...)
2056{
2057 switch (note_type)
2058 {
2059 default:
2060 return NULL;
2061
2062 case NT_PRPSINFO:
2063 {
2064 char data[124];
2065 va_list ap;
2066
2067 va_start (ap, note_type);
2068 memset (data, 0, sizeof (data));
2069 strncpy (data + 28, va_arg (ap, const char *), 16);
2070 strncpy (data + 44, va_arg (ap, const char *), 80);
2071 va_end (ap);
2072
2073 return elfcore_write_note (abfd, buf, bufsiz,
2074 "CORE", note_type, data, sizeof (data));
2075 }
2076
2077 case NT_PRSTATUS:
2078 {
2079 char data[148];
2080 va_list ap;
2081 long pid;
2082 int cursig;
2083 const void *greg;
2084
2085 va_start (ap, note_type);
2086 memset (data, 0, sizeof (data));
2087 pid = va_arg (ap, long);
2088 bfd_put_32 (abfd, pid, data + 24);
2089 cursig = va_arg (ap, int);
2090 bfd_put_16 (abfd, cursig, data + 12);
2091 greg = va_arg (ap, const void *);
2092 memcpy (data + 72, greg, 72);
2093 va_end (ap);
2094
2095 return elfcore_write_note (abfd, buf, bufsiz,
2096 "CORE", note_type, data, sizeof (data));
2097 }
2098 }
2099}
2100
6d00b590 2101#define TARGET_LITTLE_SYM arm_elf32_le_vec
7f266840 2102#define TARGET_LITTLE_NAME "elf32-littlearm"
6d00b590 2103#define TARGET_BIG_SYM arm_elf32_be_vec
7f266840
DJ		 2104#define TARGET_BIG_NAME "elf32-bigarm"
2105
2106#define elf_backend_grok_prstatus elf32_arm_nabi_grok_prstatus
2107#define elf_backend_grok_psinfo elf32_arm_nabi_grok_psinfo
1f20dca5 2108#define elf_backend_write_core_note elf32_arm_nabi_write_core_note
7f266840 2109
252b5132
RH		 2110typedef unsigned long int insn32;
2111typedef unsigned short int insn16;
2112
3a4a14e9
PB		 2113/* In lieu of proper flags, assume all EABIv4 or later objects are
2114 interworkable. */
57e8b36a 2115#define INTERWORK_FLAG(abfd) \
3a4a14e9 2116 (EF_ARM_EABI_VERSION (elf_elfheader (abfd)->e_flags) >= EF_ARM_EABI_VER4 \
3e6b1042
DJ		 2117 || (elf_elfheader (abfd)->e_flags & EF_ARM_INTERWORK) \
2118 || ((abfd)->flags & BFD_LINKER_CREATED))
9b485d32 2119
252b5132
RH		 2120/* The linker script knows the section names for placement.
2121 The entry_names are used to do simple name mangling on the stubs.
2122 Given a function name, and its type, the stub can be found. The
9b485d32 2123 name can be changed. The only requirement is the %s be present. */
252b5132
RH		 2124#define THUMB2ARM_GLUE_SECTION_NAME ".glue_7t"
2125#define THUMB2ARM_GLUE_ENTRY_NAME "__%s_from_thumb"
2126
2127#define ARM2THUMB_GLUE_SECTION_NAME ".glue_7"
2128#define ARM2THUMB_GLUE_ENTRY_NAME "__%s_from_arm"
2129
c7b8f16e
JB		 2130#define VFP11_ERRATUM_VENEER_SECTION_NAME ".vfp11_veneer"
2131#define VFP11_ERRATUM_VENEER_ENTRY_NAME "__vfp11_veneer_%x"
2132
a504d23a
LA		 2133#define STM32L4XX_ERRATUM_VENEER_SECTION_NAME ".text.stm32l4xx_veneer"
2134#define STM32L4XX_ERRATUM_VENEER_ENTRY_NAME "__stm32l4xx_veneer_%x"
2135
845b51d6
PB		 2136#define ARM_BX_GLUE_SECTION_NAME ".v4_bx"
2137#define ARM_BX_GLUE_ENTRY_NAME "__bx_r%d"
2138
7413f23f
DJ		 2139#define STUB_ENTRY_NAME "__%s_veneer"
2140
252b5132
RH		 2141/* The name of the dynamic interpreter. This is put in the .interp
2142 section. */
2143#define ELF_DYNAMIC_INTERPRETER "/usr/lib/ld.so.1"
2144
0855e32b 2145static const unsigned long tls_trampoline [] =
b38cadfb
NC		 2146{
2147 0xe08e0000, /* add r0, lr, r0 */
2148 0xe5901004, /* ldr r1, [r0,#4] */
2149 0xe12fff11, /* bx r1 */
2150};
0855e32b
NS		 2151
2152static const unsigned long dl_tlsdesc_lazy_trampoline [] =
b38cadfb
NC		 2153{
2154 0xe52d2004, /* push {r2} */
2155 0xe59f200c, /* ldr r2, [pc, #3f - . - 8] */
2156 0xe59f100c, /* ldr r1, [pc, #4f - . - 8] */
2157 0xe79f2002, /* 1: ldr r2, [pc, r2] */
2158 0xe081100f, /* 2: add r1, pc */
2159 0xe12fff12, /* bx r2 */
2160 0x00000014, /* 3: .word _GLOBAL_OFFSET_TABLE_ - 1b - 8
99059e56 2161 + dl_tlsdesc_lazy_resolver(GOT) */
b38cadfb
NC		 2162 0x00000018, /* 4: .word _GLOBAL_OFFSET_TABLE_ - 2b - 8 */
2163};
0855e32b 2164
5e681ec4
PB		 2165#ifdef FOUR_WORD_PLT
2166
252b5132
RH		 2167/* The first entry in a procedure linkage table looks like
2168 this. It is set up so that any shared library function that is
59f2c4e7 2169 called before the relocation has been set up calls the dynamic
9b485d32 2170 linker first. */
e5a52504 2171static const bfd_vma elf32_arm_plt0_entry [] =
b38cadfb
NC		 2172{
2173 0xe52de004, /* str lr, [sp, #-4]! */
2174 0xe59fe010, /* ldr lr, [pc, #16] */
2175 0xe08fe00e, /* add lr, pc, lr */
2176 0xe5bef008, /* ldr pc, [lr, #8]! */
2177};
5e681ec4
PB		 2178
2179/* Subsequent entries in a procedure linkage table look like
2180 this. */
e5a52504 2181static const bfd_vma elf32_arm_plt_entry [] =
b38cadfb
NC		 2182{
2183 0xe28fc600, /* add ip, pc, #NN */
2184 0xe28cca00, /* add ip, ip, #NN */
2185 0xe5bcf000, /* ldr pc, [ip, #NN]! */
2186 0x00000000, /* unused */
2187};
5e681ec4 2188
eed94f8f 2189#else /* not FOUR_WORD_PLT */
5e681ec4 2190
5e681ec4
PB		 2191/* The first entry in a procedure linkage table looks like
2192 this. It is set up so that any shared library function that is
2193 called before the relocation has been set up calls the dynamic
2194 linker first. */
e5a52504 2195static const bfd_vma elf32_arm_plt0_entry [] =
b38cadfb
NC		 2196{
2197 0xe52de004, /* str lr, [sp, #-4]! */
2198 0xe59fe004, /* ldr lr, [pc, #4] */
2199 0xe08fe00e, /* add lr, pc, lr */
2200 0xe5bef008, /* ldr pc, [lr, #8]! */
2201 0x00000000, /* &GOT[0] - . */
2202};
252b5132 2203
1db37fe6
YG		 2204/* By default subsequent entries in a procedure linkage table look like
2205 this. Offsets that don't fit into 28 bits will cause link error. */
2206static const bfd_vma elf32_arm_plt_entry_short [] =
b38cadfb
NC		 2207{
2208 0xe28fc600, /* add ip, pc, #0xNN00000 */
2209 0xe28cca00, /* add ip, ip, #0xNN000 */
2210 0xe5bcf000, /* ldr pc, [ip, #0xNNN]! */
2211};
5e681ec4 2212
1db37fe6
YG		 2213/* When explicitly asked, we'll use this "long" entry format
2214 which can cope with arbitrary displacements. */
2215static const bfd_vma elf32_arm_plt_entry_long [] =
2216{
2217 0xe28fc200, /* add ip, pc, #0xN0000000 */
2218 0xe28cc600, /* add ip, ip, #0xNN00000 */
2219 0xe28cca00, /* add ip, ip, #0xNN000 */
2220 0xe5bcf000, /* ldr pc, [ip, #0xNNN]! */
2221};
2222
2223static bfd_boolean elf32_arm_use_long_plt_entry = FALSE;
2224
eed94f8f
NC		 2225#endif /* not FOUR_WORD_PLT */
2226
2227/* The first entry in a procedure linkage table looks like this.
2228 It is set up so that any shared library function that is called before the
2229 relocation has been set up calls the dynamic linker first. */
2230static const bfd_vma elf32_thumb2_plt0_entry [] =
2231{
2232 /* NOTE: As this is a mixture of 16-bit and 32-bit instructions,
2233 an instruction maybe encoded to one or two array elements. */
2234 0xf8dfb500, /* push {lr} */
2235 0x44fee008, /* ldr.w lr, [pc, #8] */
469a3493 2236 /* add lr, pc */
eed94f8f
NC		 2237 0xff08f85e, /* ldr.w pc, [lr, #8]! */
2238 0x00000000, /* &GOT[0] - . */
2239};
2240
2241/* Subsequent entries in a procedure linkage table for thumb only target
2242 look like this. */
2243static const bfd_vma elf32_thumb2_plt_entry [] =
2244{
2245 /* NOTE: As this is a mixture of 16-bit and 32-bit instructions,
2246 an instruction maybe encoded to one or two array elements. */
2247 0x0c00f240, /* movw ip, #0xNNNN */
2248 0x0c00f2c0, /* movt ip, #0xNNNN */
2249 0xf8dc44fc, /* add ip, pc */
2250 0xbf00f000 /* ldr.w pc, [ip] */
469a3493 2251 /* nop */
eed94f8f 2252};
252b5132 2253
00a97672
RS		 2254/* The format of the first entry in the procedure linkage table
2255 for a VxWorks executable. */
2256static const bfd_vma elf32_arm_vxworks_exec_plt0_entry[] =
b38cadfb
NC		 2257{
2258 0xe52dc008, /* str ip,[sp,#-8]! */
2259 0xe59fc000, /* ldr ip,[pc] */
2260 0xe59cf008, /* ldr pc,[ip,#8] */
2261 0x00000000, /* .long _GLOBAL_OFFSET_TABLE_ */
2262};
00a97672
RS		 2263
2264/* The format of subsequent entries in a VxWorks executable. */
2265static const bfd_vma elf32_arm_vxworks_exec_plt_entry[] =
b38cadfb
NC		 2266{
2267 0xe59fc000, /* ldr ip,[pc] */
2268 0xe59cf000, /* ldr pc,[ip] */
2269 0x00000000, /* .long @got */
2270 0xe59fc000, /* ldr ip,[pc] */
2271 0xea000000, /* b _PLT */
2272 0x00000000, /* .long @pltindex*sizeof(Elf32_Rela) */
2273};
00a97672
RS		 2274
2275/* The format of entries in a VxWorks shared library. */
2276static const bfd_vma elf32_arm_vxworks_shared_plt_entry[] =
b38cadfb
NC		 2277{
2278 0xe59fc000, /* ldr ip,[pc] */
2279 0xe79cf009, /* ldr pc,[ip,r9] */
2280 0x00000000, /* .long @got */
2281 0xe59fc000, /* ldr ip,[pc] */
2282 0xe599f008, /* ldr pc,[r9,#8] */
2283 0x00000000, /* .long @pltindex*sizeof(Elf32_Rela) */
2284};
00a97672 2285
b7693d02
DJ		 2286/* An initial stub used if the PLT entry is referenced from Thumb code. */
2287#define PLT_THUMB_STUB_SIZE 4
2288static const bfd_vma elf32_arm_plt_thumb_stub [] =
b38cadfb
NC		 2289{
2290 0x4778, /* bx pc */
2291 0x46c0 /* nop */
2292};
b7693d02 2293
e5a52504
MM		 2294/* The entries in a PLT when using a DLL-based target with multiple
2295 address spaces. */
906e58ca 2296static const bfd_vma elf32_arm_symbian_plt_entry [] =
b38cadfb
NC		 2297{
2298 0xe51ff004, /* ldr pc, [pc, #-4] */
2299 0x00000000, /* dcd R_ARM_GLOB_DAT(X) */
2300};
2301
2302/* The first entry in a procedure linkage table looks like
2303 this. It is set up so that any shared library function that is
2304 called before the relocation has been set up calls the dynamic
2305 linker first. */
2306static const bfd_vma elf32_arm_nacl_plt0_entry [] =
2307{
2308 /* First bundle: */
2309 0xe300c000, /* movw ip, #:lower16:&GOT[2]-.+8 */
2310 0xe340c000, /* movt ip, #:upper16:&GOT[2]-.+8 */
2311 0xe08cc00f, /* add ip, ip, pc */
2312 0xe52dc008, /* str ip, [sp, #-8]! */
2313 /* Second bundle: */
edccdf7c
RM		 2314 0xe3ccc103, /* bic ip, ip, #0xc0000000 */
2315 0xe59cc000, /* ldr ip, [ip] */
b38cadfb 2316 0xe3ccc13f, /* bic ip, ip, #0xc000000f */
edccdf7c 2317 0xe12fff1c, /* bx ip */
b38cadfb 2318 /* Third bundle: */
edccdf7c
RM		 2319 0xe320f000, /* nop */
2320 0xe320f000, /* nop */
2321 0xe320f000, /* nop */
b38cadfb
NC		 2322 /* .Lplt_tail: */
2323 0xe50dc004, /* str ip, [sp, #-4] */
2324 /* Fourth bundle: */
edccdf7c
RM		 2325 0xe3ccc103, /* bic ip, ip, #0xc0000000 */
2326 0xe59cc000, /* ldr ip, [ip] */
b38cadfb 2327 0xe3ccc13f, /* bic ip, ip, #0xc000000f */
edccdf7c 2328 0xe12fff1c, /* bx ip */
b38cadfb
NC		 2329};
2330#define ARM_NACL_PLT_TAIL_OFFSET (11 * 4)
2331
2332/* Subsequent entries in a procedure linkage table look like this. */
2333static const bfd_vma elf32_arm_nacl_plt_entry [] =
2334{
2335 0xe300c000, /* movw ip, #:lower16:&GOT[n]-.+8 */
2336 0xe340c000, /* movt ip, #:upper16:&GOT[n]-.+8 */
2337 0xe08cc00f, /* add ip, ip, pc */
2338 0xea000000, /* b .Lplt_tail */
2339};
e5a52504 2340
906e58ca
NC		 2341#define ARM_MAX_FWD_BRANCH_OFFSET ((((1 << 23) - 1) << 2) + 8)
2342#define ARM_MAX_BWD_BRANCH_OFFSET ((-((1 << 23) << 2)) + 8)
2343#define THM_MAX_FWD_BRANCH_OFFSET ((1 << 22) -2 + 4)
2344#define THM_MAX_BWD_BRANCH_OFFSET (-(1 << 22) + 4)
2345#define THM2_MAX_FWD_BRANCH_OFFSET (((1 << 24) - 2) + 4)
2346#define THM2_MAX_BWD_BRANCH_OFFSET (-(1 << 24) + 4)
c5423981
TG		 2347#define THM2_MAX_FWD_COND_BRANCH_OFFSET (((1 << 20) -2) + 4)
2348#define THM2_MAX_BWD_COND_BRANCH_OFFSET (-(1 << 20) + 4)
906e58ca 2349
461a49ca 2350enum stub_insn_type
b38cadfb
NC		 2351{
2352 THUMB16_TYPE = 1,
2353 THUMB32_TYPE,
2354 ARM_TYPE,
2355 DATA_TYPE
2356};
461a49ca 2357
48229727
JB		 2358#define THUMB16_INSN(X) {(X), THUMB16_TYPE, R_ARM_NONE, 0}
2359/* A bit of a hack. A Thumb conditional branch, in which the proper condition
2360 is inserted in arm_build_one_stub(). */
2361#define THUMB16_BCOND_INSN(X) {(X), THUMB16_TYPE, R_ARM_NONE, 1}
2362#define THUMB32_INSN(X) {(X), THUMB32_TYPE, R_ARM_NONE, 0}
2363#define THUMB32_B_INSN(X, Z) {(X), THUMB32_TYPE, R_ARM_THM_JUMP24, (Z)}
2364#define ARM_INSN(X) {(X), ARM_TYPE, R_ARM_NONE, 0}
2365#define ARM_REL_INSN(X, Z) {(X), ARM_TYPE, R_ARM_JUMP24, (Z)}
2366#define DATA_WORD(X,Y,Z) {(X), DATA_TYPE, (Y), (Z)}
461a49ca
DJ		 2367
2368typedef struct
2369{
b38cadfb
NC		 2370 bfd_vma data;
2371 enum stub_insn_type type;
2372 unsigned int r_type;
2373 int reloc_addend;
461a49ca
DJ		 2374} insn_sequence;
2375
fea2b4d6
CL		 2376/* Arm/Thumb -> Arm/Thumb long branch stub. On V5T and above, use blx
2377 to reach the stub if necessary. */
461a49ca 2378static const insn_sequence elf32_arm_stub_long_branch_any_any[] =
b38cadfb
NC		 2379{
2380 ARM_INSN (0xe51ff004), /* ldr pc, [pc, #-4] */
2381 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(X) */
2382};
906e58ca 2383
fea2b4d6
CL		 2384/* V4T Arm -> Thumb long branch stub. Used on V4T where blx is not
2385 available. */
461a49ca 2386static const insn_sequence elf32_arm_stub_long_branch_v4t_arm_thumb[] =
b38cadfb
NC		 2387{
2388 ARM_INSN (0xe59fc000), /* ldr ip, [pc, #0] */
2389 ARM_INSN (0xe12fff1c), /* bx ip */
2390 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(X) */
2391};
906e58ca 2392
d3626fb0 2393/* Thumb -> Thumb long branch stub. Used on M-profile architectures. */
461a49ca 2394static const insn_sequence elf32_arm_stub_long_branch_thumb_only[] =
b38cadfb
NC		 2395{
2396 THUMB16_INSN (0xb401), /* push {r0} */
2397 THUMB16_INSN (0x4802), /* ldr r0, [pc, #8] */
2398 THUMB16_INSN (0x4684), /* mov ip, r0 */
2399 THUMB16_INSN (0xbc01), /* pop {r0} */
2400 THUMB16_INSN (0x4760), /* bx ip */
2401 THUMB16_INSN (0xbf00), /* nop */
2402 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(X) */
2403};
906e58ca 2404
d3626fb0
CL		 2405/* V4T Thumb -> Thumb long branch stub. Using the stack is not
2406 allowed. */
2407static const insn_sequence elf32_arm_stub_long_branch_v4t_thumb_thumb[] =
b38cadfb
NC		 2408{
2409 THUMB16_INSN (0x4778), /* bx pc */
2410 THUMB16_INSN (0x46c0), /* nop */
2411 ARM_INSN (0xe59fc000), /* ldr ip, [pc, #0] */
2412 ARM_INSN (0xe12fff1c), /* bx ip */
2413 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(X) */
2414};
d3626fb0 2415
fea2b4d6
CL		 2416/* V4T Thumb -> ARM long branch stub. Used on V4T where blx is not
2417 available. */
461a49ca 2418static const insn_sequence elf32_arm_stub_long_branch_v4t_thumb_arm[] =
b38cadfb
NC		 2419{
2420 THUMB16_INSN (0x4778), /* bx pc */
2421 THUMB16_INSN (0x46c0), /* nop */
2422 ARM_INSN (0xe51ff004), /* ldr pc, [pc, #-4] */
2423 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(X) */
2424};
906e58ca 2425
fea2b4d6
CL		 2426/* V4T Thumb -> ARM short branch stub. Shorter variant of the above
2427 one, when the destination is close enough. */
461a49ca 2428static const insn_sequence elf32_arm_stub_short_branch_v4t_thumb_arm[] =
b38cadfb
NC		 2429{
2430 THUMB16_INSN (0x4778), /* bx pc */
2431 THUMB16_INSN (0x46c0), /* nop */
2432 ARM_REL_INSN (0xea000000, -8), /* b (X-8) */
2433};
c820be07 2434
cf3eccff 2435/* ARM/Thumb -> ARM long branch stub, PIC. On V5T and above, use
fea2b4d6 2436 blx to reach the stub if necessary. */
cf3eccff 2437static const insn_sequence elf32_arm_stub_long_branch_any_arm_pic[] =
b38cadfb
NC		 2438{
2439 ARM_INSN (0xe59fc000), /* ldr ip, [pc] */
2440 ARM_INSN (0xe08ff00c), /* add pc, pc, ip */
2441 DATA_WORD (0, R_ARM_REL32, -4), /* dcd R_ARM_REL32(X-4) */
2442};
906e58ca 2443
cf3eccff
DJ		 2444/* ARM/Thumb -> Thumb long branch stub, PIC. On V5T and above, use
2445 blx to reach the stub if necessary. We can not add into pc;
2446 it is not guaranteed to mode switch (different in ARMv6 and
2447 ARMv7). */
2448static const insn_sequence elf32_arm_stub_long_branch_any_thumb_pic[] =
b38cadfb
NC		 2449{
2450 ARM_INSN (0xe59fc004), /* ldr ip, [pc, #4] */
2451 ARM_INSN (0xe08fc00c), /* add ip, pc, ip */
2452 ARM_INSN (0xe12fff1c), /* bx ip */
2453 DATA_WORD (0, R_ARM_REL32, 0), /* dcd R_ARM_REL32(X) */
2454};
cf3eccff 2455
ebe24dd4
CL		 2456/* V4T ARM -> ARM long branch stub, PIC. */
2457static const insn_sequence elf32_arm_stub_long_branch_v4t_arm_thumb_pic[] =
b38cadfb
NC		 2458{
2459 ARM_INSN (0xe59fc004), /* ldr ip, [pc, #4] */
2460 ARM_INSN (0xe08fc00c), /* add ip, pc, ip */
2461 ARM_INSN (0xe12fff1c), /* bx ip */
2462 DATA_WORD (0, R_ARM_REL32, 0), /* dcd R_ARM_REL32(X) */
2463};
ebe24dd4
CL		 2464
2465/* V4T Thumb -> ARM long branch stub, PIC. */
2466static const insn_sequence elf32_arm_stub_long_branch_v4t_thumb_arm_pic[] =
b38cadfb
NC		 2467{
2468 THUMB16_INSN (0x4778), /* bx pc */
2469 THUMB16_INSN (0x46c0), /* nop */
2470 ARM_INSN (0xe59fc000), /* ldr ip, [pc, #0] */
2471 ARM_INSN (0xe08cf00f), /* add pc, ip, pc */
2472 DATA_WORD (0, R_ARM_REL32, -4), /* dcd R_ARM_REL32(X) */
2473};
ebe24dd4 2474
d3626fb0
CL		 2475/* Thumb -> Thumb long branch stub, PIC. Used on M-profile
2476 architectures. */
ebe24dd4 2477static const insn_sequence elf32_arm_stub_long_branch_thumb_only_pic[] =
b38cadfb
NC		 2478{
2479 THUMB16_INSN (0xb401), /* push {r0} */
2480 THUMB16_INSN (0x4802), /* ldr r0, [pc, #8] */
2481 THUMB16_INSN (0x46fc), /* mov ip, pc */
2482 THUMB16_INSN (0x4484), /* add ip, r0 */
2483 THUMB16_INSN (0xbc01), /* pop {r0} */
2484 THUMB16_INSN (0x4760), /* bx ip */
2485 DATA_WORD (0, R_ARM_REL32, 4), /* dcd R_ARM_REL32(X) */
2486};
ebe24dd4 2487
d3626fb0
CL		 2488/* V4T Thumb -> Thumb long branch stub, PIC. Using the stack is not
2489 allowed. */
2490static const insn_sequence elf32_arm_stub_long_branch_v4t_thumb_thumb_pic[] =
b38cadfb
NC		 2491{
2492 THUMB16_INSN (0x4778), /* bx pc */
2493 THUMB16_INSN (0x46c0), /* nop */
2494 ARM_INSN (0xe59fc004), /* ldr ip, [pc, #4] */
2495 ARM_INSN (0xe08fc00c), /* add ip, pc, ip */
2496 ARM_INSN (0xe12fff1c), /* bx ip */
2497 DATA_WORD (0, R_ARM_REL32, 0), /* dcd R_ARM_REL32(X) */
2498};
d3626fb0 2499
0855e32b
NS		 2500/* Thumb2/ARM -> TLS trampoline. Lowest common denominator, which is a
2501 long PIC stub. We can use r1 as a scratch -- and cannot use ip. */
2502static const insn_sequence elf32_arm_stub_long_branch_any_tls_pic[] =
2503{
b38cadfb
NC		 2504 ARM_INSN (0xe59f1000), /* ldr r1, [pc] */
2505 ARM_INSN (0xe08ff001), /* add pc, pc, r1 */
2506 DATA_WORD (0, R_ARM_REL32, -4), /* dcd R_ARM_REL32(X-4) */
0855e32b
NS		 2507};
2508
2509/* V4T Thumb -> TLS trampoline. lowest common denominator, which is a
2510 long PIC stub. We can use r1 as a scratch -- and cannot use ip. */
2511static const insn_sequence elf32_arm_stub_long_branch_v4t_thumb_tls_pic[] =
2512{
b38cadfb
NC		 2513 THUMB16_INSN (0x4778), /* bx pc */
2514 THUMB16_INSN (0x46c0), /* nop */
2515 ARM_INSN (0xe59f1000), /* ldr r1, [pc, #0] */
2516 ARM_INSN (0xe081f00f), /* add pc, r1, pc */
2517 DATA_WORD (0, R_ARM_REL32, -4), /* dcd R_ARM_REL32(X) */
0855e32b
NS		 2518};
2519
7a89b94e
NC		 2520/* NaCl ARM -> ARM long branch stub. */
2521static const insn_sequence elf32_arm_stub_long_branch_arm_nacl[] =
2522{
2523 ARM_INSN (0xe59fc00c), /* ldr ip, [pc, #12] */
2524 ARM_INSN (0xe3ccc13f), /* bic ip, ip, #0xc000000f */
2525 ARM_INSN (0xe12fff1c), /* bx ip */
2526 ARM_INSN (0xe320f000), /* nop */
2527 ARM_INSN (0xe125be70), /* bkpt 0x5be0 */
2528 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(X) */
2529 DATA_WORD (0, R_ARM_NONE, 0), /* .word 0 */
2530 DATA_WORD (0, R_ARM_NONE, 0), /* .word 0 */
2531};
2532
2533/* NaCl ARM -> ARM long branch stub, PIC. */
2534static const insn_sequence elf32_arm_stub_long_branch_arm_nacl_pic[] =
2535{
2536 ARM_INSN (0xe59fc00c), /* ldr ip, [pc, #12] */
2537 ARM_INSN (0xe08cc00f), /* add ip, ip, pc */
2538 ARM_INSN (0xe3ccc13f), /* bic ip, ip, #0xc000000f */
2539 ARM_INSN (0xe12fff1c), /* bx ip */
2540 ARM_INSN (0xe125be70), /* bkpt 0x5be0 */
2541 DATA_WORD (0, R_ARM_REL32, 8), /* dcd R_ARM_REL32(X+8) */
2542 DATA_WORD (0, R_ARM_NONE, 0), /* .word 0 */
2543 DATA_WORD (0, R_ARM_NONE, 0), /* .word 0 */
2544};
2545
2546
48229727
JB		 2547/* Cortex-A8 erratum-workaround stubs. */
2548
2549/* Stub used for conditional branches (which may be beyond +/-1MB away, so we
2550 can't use a conditional branch to reach this stub). */
2551
2552static const insn_sequence elf32_arm_stub_a8_veneer_b_cond[] =
b38cadfb
NC		 2553{
2554 THUMB16_BCOND_INSN (0xd001), /* b<cond>.n true. */
2555 THUMB32_B_INSN (0xf000b800, -4), /* b.w insn_after_original_branch. */
2556 THUMB32_B_INSN (0xf000b800, -4) /* true: b.w original_branch_dest. */
2557};
48229727
JB		 2558
2559/* Stub used for b.w and bl.w instructions. */
2560
2561static const insn_sequence elf32_arm_stub_a8_veneer_b[] =
b38cadfb
NC		 2562{
2563 THUMB32_B_INSN (0xf000b800, -4) /* b.w original_branch_dest. */
2564};
48229727
JB		 2565
2566static const insn_sequence elf32_arm_stub_a8_veneer_bl[] =
b38cadfb
NC		 2567{
2568 THUMB32_B_INSN (0xf000b800, -4) /* b.w original_branch_dest. */
2569};
48229727
JB		 2570
2571/* Stub used for Thumb-2 blx.w instructions. We modified the original blx.w
2572 instruction (which switches to ARM mode) to point to this stub. Jump to the
2573 real destination using an ARM-mode branch. */
2574
2575static const insn_sequence elf32_arm_stub_a8_veneer_blx[] =
b38cadfb
NC		 2576{
2577 ARM_REL_INSN (0xea000000, -8) /* b original_branch_dest. */
2578};
48229727 2579
9553db3c
NC		 2580/* For each section group there can be a specially created linker section
2581 to hold the stubs for that group. The name of the stub section is based
2582 upon the name of another section within that group with the suffix below
2583 applied.
2584
2585 PR 13049: STUB_SUFFIX used to be ".stub", but this allowed the user to
2586 create what appeared to be a linker stub section when it actually
2587 contained user code/data. For example, consider this fragment:
b38cadfb 2588
9553db3c
NC		 2589 const char * stubborn_problems[] = { "np" };
2590
2591 If this is compiled with "-fPIC -fdata-sections" then gcc produces a
2592 section called:
2593
2594 .data.rel.local.stubborn_problems
2595
2596 This then causes problems in arm32_arm_build_stubs() as it triggers:
2597
2598 // Ignore non-stub sections.
2599 if (!strstr (stub_sec->name, STUB_SUFFIX))
2600 continue;
2601
2602 And so the section would be ignored instead of being processed. Hence
2603 the change in definition of STUB_SUFFIX to a name that cannot be a valid
2604 C identifier. */
2605#define STUB_SUFFIX ".__stub"
906e58ca 2606
738a79f6
CL		 2607/* One entry per long/short branch stub defined above. */
2608#define DEF_STUBS \
2609 DEF_STUB(long_branch_any_any) \
2610 DEF_STUB(long_branch_v4t_arm_thumb) \
2611 DEF_STUB(long_branch_thumb_only) \
2612 DEF_STUB(long_branch_v4t_thumb_thumb) \
2613 DEF_STUB(long_branch_v4t_thumb_arm) \
2614 DEF_STUB(short_branch_v4t_thumb_arm) \
2615 DEF_STUB(long_branch_any_arm_pic) \
2616 DEF_STUB(long_branch_any_thumb_pic) \
2617 DEF_STUB(long_branch_v4t_thumb_thumb_pic) \
2618 DEF_STUB(long_branch_v4t_arm_thumb_pic) \
2619 DEF_STUB(long_branch_v4t_thumb_arm_pic) \
48229727 2620 DEF_STUB(long_branch_thumb_only_pic) \
0855e32b
NS		 2621 DEF_STUB(long_branch_any_tls_pic) \
2622 DEF_STUB(long_branch_v4t_thumb_tls_pic) \
7a89b94e
NC		 2623 DEF_STUB(long_branch_arm_nacl) \
2624 DEF_STUB(long_branch_arm_nacl_pic) \
48229727
JB		 2625 DEF_STUB(a8_veneer_b_cond) \
2626 DEF_STUB(a8_veneer_b) \
2627 DEF_STUB(a8_veneer_bl) \
2628 DEF_STUB(a8_veneer_blx)
738a79f6
CL		 2629
2630#define DEF_STUB(x) arm_stub_##x,
b38cadfb
NC		 2631enum elf32_arm_stub_type
2632{
906e58ca 2633 arm_stub_none,
738a79f6
CL		 2634 DEF_STUBS
2635};
2636#undef DEF_STUB
2637
8d9d9490
TP		 2638/* Note the first a8_veneer type. */
2639const unsigned arm_stub_a8_veneer_lwm = arm_stub_a8_veneer_b_cond;
2640
738a79f6
CL		 2641typedef struct
2642{
d3ce72d0 2643 const insn_sequence* template_sequence;
738a79f6
CL		 2644 int template_size;
2645} stub_def;
2646
2647#define DEF_STUB(x) {elf32_arm_stub_##x, ARRAY_SIZE(elf32_arm_stub_##x)},
b38cadfb
NC		 2648static const stub_def stub_definitions[] =
2649{
738a79f6
CL		 2650 {NULL, 0},
2651 DEF_STUBS
906e58ca
NC		 2652};
2653
2654struct elf32_arm_stub_hash_entry
2655{
2656 /* Base hash table entry structure. */
2657 struct bfd_hash_entry root;
2658
2659 /* The stub section. */
2660 asection *stub_sec;
2661
2662 /* Offset within stub_sec of the beginning of this stub. */
2663 bfd_vma stub_offset;
2664
2665 /* Given the symbol's value and its section we can determine its final
2666 value when building the stubs (so the stub knows where to jump). */
2667 bfd_vma target_value;
2668 asection *target_section;
2669
8d9d9490
TP		 2670 /* Same as above but for the source of the branch to the stub. Used for
2671 Cortex-A8 erratum workaround to patch it to branch to the stub. As
2672 such, source section does not need to be recorded since Cortex-A8 erratum
2673 workaround stubs are only generated when both source and target are in the
2674 same section. */
2675 bfd_vma source_value;
48229727
JB		 2676
2677 /* The instruction which caused this stub to be generated (only valid for
2678 Cortex-A8 erratum workaround stubs at present). */
2679 unsigned long orig_insn;
2680
461a49ca 2681 /* The stub type. */
906e58ca 2682 enum elf32_arm_stub_type stub_type;
461a49ca
DJ		 2683 /* Its encoding size in bytes. */
2684 int stub_size;
2685 /* Its template. */
2686 const insn_sequence *stub_template;
2687 /* The size of the template (number of entries). */
2688 int stub_template_size;
906e58ca
NC		 2689
2690 /* The symbol table entry, if any, that this was derived from. */
2691 struct elf32_arm_link_hash_entry *h;
2692
35fc36a8
RS		 2693 /* Type of branch. */
2694 enum arm_st_branch_type branch_type;
906e58ca
NC		 2695
2696 /* Where this stub is being called from, or, in the case of combined
2697 stub sections, the first input section in the group. */
2698 asection *id_sec;
7413f23f
DJ		 2699
2700 /* The name for the local symbol at the start of this stub. The
2701 stub name in the hash table has to be unique; this does not, so
2702 it can be friendlier. */
2703 char *output_name;
906e58ca
NC		 2704};
2705
e489d0ae
PB		 2706/* Used to build a map of a section. This is required for mixed-endian
2707 code/data. */
2708
2709typedef struct elf32_elf_section_map
2710{
2711 bfd_vma vma;
2712 char type;
2713}
2714elf32_arm_section_map;
2715
c7b8f16e
JB		 2716/* Information about a VFP11 erratum veneer, or a branch to such a veneer. */
2717
2718typedef enum
2719{
2720 VFP11_ERRATUM_BRANCH_TO_ARM_VENEER,
2721 VFP11_ERRATUM_BRANCH_TO_THUMB_VENEER,
2722 VFP11_ERRATUM_ARM_VENEER,
2723 VFP11_ERRATUM_THUMB_VENEER
2724}
2725elf32_vfp11_erratum_type;
2726
2727typedef struct elf32_vfp11_erratum_list
2728{
2729 struct elf32_vfp11_erratum_list *next;
2730 bfd_vma vma;
2731 union
2732 {
2733 struct
2734 {
2735 struct elf32_vfp11_erratum_list *veneer;
2736 unsigned int vfp_insn;
2737 } b;
2738 struct
2739 {
2740 struct elf32_vfp11_erratum_list *branch;
2741 unsigned int id;
2742 } v;
2743 } u;
2744 elf32_vfp11_erratum_type type;
2745}
2746elf32_vfp11_erratum_list;
2747
a504d23a
LA		 2748/* Information about a STM32L4XX erratum veneer, or a branch to such a
2749 veneer. */
2750typedef enum
2751{
2752 STM32L4XX_ERRATUM_BRANCH_TO_VENEER,
2753 STM32L4XX_ERRATUM_VENEER
2754}
2755elf32_stm32l4xx_erratum_type;
2756
2757typedef struct elf32_stm32l4xx_erratum_list
2758{
2759 struct elf32_stm32l4xx_erratum_list *next;
2760 bfd_vma vma;
2761 union
2762 {
2763 struct
2764 {
2765 struct elf32_stm32l4xx_erratum_list *veneer;
2766 unsigned int insn;
2767 } b;
2768 struct
2769 {
2770 struct elf32_stm32l4xx_erratum_list *branch;
2771 unsigned int id;
2772 } v;
2773 } u;
2774 elf32_stm32l4xx_erratum_type type;
2775}
2776elf32_stm32l4xx_erratum_list;
2777
2468f9c9
PB		 2778typedef enum
2779{
2780 DELETE_EXIDX_ENTRY,
2781 INSERT_EXIDX_CANTUNWIND_AT_END
2782}
2783arm_unwind_edit_type;
2784
2785/* A (sorted) list of edits to apply to an unwind table. */
2786typedef struct arm_unwind_table_edit
2787{
2788 arm_unwind_edit_type type;
2789 /* Note: we sometimes want to insert an unwind entry corresponding to a
2790 section different from the one we're currently writing out, so record the
2791 (text) section this edit relates to here. */
2792 asection *linked_section;
2793 unsigned int index;
2794 struct arm_unwind_table_edit *next;
2795}
2796arm_unwind_table_edit;
2797
8e3de13a 2798typedef struct _arm_elf_section_data
e489d0ae 2799{
2468f9c9 2800 /* Information about mapping symbols. */
e489d0ae 2801 struct bfd_elf_section_data elf;
8e3de13a 2802 unsigned int mapcount;
c7b8f16e 2803 unsigned int mapsize;
e489d0ae 2804 elf32_arm_section_map *map;
2468f9c9 2805 /* Information about CPU errata. */
c7b8f16e
JB		 2806 unsigned int erratumcount;
2807 elf32_vfp11_erratum_list *erratumlist;
a504d23a
LA		 2808 unsigned int stm32l4xx_erratumcount;
2809 elf32_stm32l4xx_erratum_list *stm32l4xx_erratumlist;
491d01d3 2810 unsigned int additional_reloc_count;
2468f9c9
PB		 2811 /* Information about unwind tables. */
2812 union
2813 {
2814 /* Unwind info attached to a text section. */
2815 struct
2816 {
2817 asection *arm_exidx_sec;
2818 } text;
2819
2820 /* Unwind info attached to an .ARM.exidx section. */
2821 struct
2822 {
2823 arm_unwind_table_edit *unwind_edit_list;
2824 arm_unwind_table_edit *unwind_edit_tail;
2825 } exidx;
2826 } u;
8e3de13a
NC		 2827}
2828_arm_elf_section_data;
e489d0ae
PB		 2829
2830#define elf32_arm_section_data(sec) \
8e3de13a 2831 ((_arm_elf_section_data *) elf_section_data (sec))
e489d0ae 2832
48229727
JB		 2833/* A fix which might be required for Cortex-A8 Thumb-2 branch/TLB erratum.
2834 These fixes are subject to a relaxation procedure (in elf32_arm_size_stubs),
2835 so may be created multiple times: we use an array of these entries whilst
2836 relaxing which we can refresh easily, then create stubs for each potentially
2837 erratum-triggering instruction once we've settled on a solution. */
2838
b38cadfb
NC		 2839struct a8_erratum_fix
2840{
48229727
JB		 2841 bfd *input_bfd;
2842 asection *section;
2843 bfd_vma offset;
8d9d9490 2844 bfd_vma target_offset;
48229727
JB		 2845 unsigned long orig_insn;
2846 char *stub_name;
2847 enum elf32_arm_stub_type stub_type;
35fc36a8 2848 enum arm_st_branch_type branch_type;
48229727
JB		 2849};
2850
2851/* A table of relocs applied to branches which might trigger Cortex-A8
2852 erratum. */
2853
b38cadfb
NC		 2854struct a8_erratum_reloc
2855{
48229727
JB		 2856 bfd_vma from;
2857 bfd_vma destination;
92750f34
DJ		 2858 struct elf32_arm_link_hash_entry *hash;
2859 const char *sym_name;
48229727 2860 unsigned int r_type;
35fc36a8 2861 enum arm_st_branch_type branch_type;
48229727
JB		 2862 bfd_boolean non_a8_stub;
2863};
2864
ba93b8ac
DJ		 2865/* The size of the thread control block. */
2866#define TCB_SIZE 8
2867
34e77a92
RS		 2868/* ARM-specific information about a PLT entry, over and above the usual
2869 gotplt_union. */
b38cadfb
NC		 2870struct arm_plt_info
2871{
34e77a92
RS		 2872 /* We reference count Thumb references to a PLT entry separately,
2873 so that we can emit the Thumb trampoline only if needed. */
2874 bfd_signed_vma thumb_refcount;
2875
2876 /* Some references from Thumb code may be eliminated by BL->BLX
2877 conversion, so record them separately. */
2878 bfd_signed_vma maybe_thumb_refcount;
2879
2880 /* How many of the recorded PLT accesses were from non-call relocations.
2881 This information is useful when deciding whether anything takes the
2882 address of an STT_GNU_IFUNC PLT. A value of 0 means that all
2883 non-call references to the function should resolve directly to the
2884 real runtime target. */
2885 unsigned int noncall_refcount;
2886
2887 /* Since PLT entries have variable size if the Thumb prologue is
2888 used, we need to record the index into .got.plt instead of
2889 recomputing it from the PLT offset. */
2890 bfd_signed_vma got_offset;
2891};
2892
2893/* Information about an .iplt entry for a local STT_GNU_IFUNC symbol. */
b38cadfb
NC		 2894struct arm_local_iplt_info
2895{
34e77a92
RS		 2896 /* The information that is usually found in the generic ELF part of
2897 the hash table entry. */
2898 union gotplt_union root;
2899
2900 /* The information that is usually found in the ARM-specific part of
2901 the hash table entry. */
2902 struct arm_plt_info arm;
2903
2904 /* A list of all potential dynamic relocations against this symbol. */
2905 struct elf_dyn_relocs *dyn_relocs;
2906};
2907
0ffa91dd 2908struct elf_arm_obj_tdata
ba93b8ac
DJ		 2909{
2910 struct elf_obj_tdata root;
2911
2912 /* tls_type for each local got entry. */
2913 char *local_got_tls_type;
ee065d83 2914
0855e32b
NS		 2915 /* GOTPLT entries for TLS descriptors. */
2916 bfd_vma *local_tlsdesc_gotent;
2917
34e77a92
RS		 2918 /* Information for local symbols that need entries in .iplt. */
2919 struct arm_local_iplt_info **local_iplt;
2920
bf21ed78
MS		 2921 /* Zero to warn when linking objects with incompatible enum sizes. */
2922 int no_enum_size_warning;
a9dc9481
JM		 2923
2924 /* Zero to warn when linking objects with incompatible wchar_t sizes. */
2925 int no_wchar_size_warning;
ba93b8ac
DJ		 2926};
2927
0ffa91dd
NC		 2928#define elf_arm_tdata(bfd) \
2929 ((struct elf_arm_obj_tdata *) (bfd)->tdata.any)
ba93b8ac 2930
0ffa91dd
NC		 2931#define elf32_arm_local_got_tls_type(bfd) \
2932 (elf_arm_tdata (bfd)->local_got_tls_type)
2933
0855e32b
NS		 2934#define elf32_arm_local_tlsdesc_gotent(bfd) \
2935 (elf_arm_tdata (bfd)->local_tlsdesc_gotent)
2936
34e77a92
RS		 2937#define elf32_arm_local_iplt(bfd) \
2938 (elf_arm_tdata (bfd)->local_iplt)
2939
0ffa91dd
NC		 2940#define is_arm_elf(bfd) \
2941 (bfd_get_flavour (bfd) == bfd_target_elf_flavour \
2942 && elf_tdata (bfd) != NULL \
4dfe6ac6 2943 && elf_object_id (bfd) == ARM_ELF_DATA)
ba93b8ac
DJ		 2944
2945static bfd_boolean
2946elf32_arm_mkobject (bfd *abfd)
2947{
0ffa91dd 2948 return bfd_elf_allocate_object (abfd, sizeof (struct elf_arm_obj_tdata),
4dfe6ac6 2949 ARM_ELF_DATA);
ba93b8ac
DJ		 2950}
2951
ba93b8ac
DJ		 2952#define elf32_arm_hash_entry(ent) ((struct elf32_arm_link_hash_entry *)(ent))
2953
ba96a88f 2954/* Arm ELF linker hash entry. */
252b5132 2955struct elf32_arm_link_hash_entry
b38cadfb
NC		 2956{
2957 struct elf_link_hash_entry root;
252b5132 2958
b38cadfb
NC		 2959 /* Track dynamic relocs copied for this symbol. */
2960 struct elf_dyn_relocs *dyn_relocs;
b7693d02 2961
b38cadfb
NC		 2962 /* ARM-specific PLT information. */
2963 struct arm_plt_info plt;
ba93b8ac
DJ		 2964
2965#define GOT_UNKNOWN 0
2966#define GOT_NORMAL 1
2967#define GOT_TLS_GD 2
2968#define GOT_TLS_IE 4
0855e32b
NS		 2969#define GOT_TLS_GDESC 8
2970#define GOT_TLS_GD_ANY_P(type) ((type & GOT_TLS_GD) || (type & GOT_TLS_GDESC))
b38cadfb 2971 unsigned int tls_type : 8;
34e77a92 2972
b38cadfb
NC		 2973 /* True if the symbol's PLT entry is in .iplt rather than .plt. */
2974 unsigned int is_iplt : 1;
34e77a92 2975
b38cadfb 2976 unsigned int unused : 23;
a4fd1a8e 2977
b38cadfb
NC		 2978 /* Offset of the GOTPLT entry reserved for the TLS descriptor,
2979 starting at the end of the jump table. */
2980 bfd_vma tlsdesc_got;
0855e32b 2981
b38cadfb
NC		 2982 /* The symbol marking the real symbol location for exported thumb
2983 symbols with Arm stubs. */
2984 struct elf_link_hash_entry *export_glue;
906e58ca 2985
b38cadfb 2986 /* A pointer to the most recently used stub hash entry against this
8029a119 2987 symbol. */
b38cadfb
NC		 2988 struct elf32_arm_stub_hash_entry *stub_cache;
2989};
252b5132 2990
252b5132 2991/* Traverse an arm ELF linker hash table. */
252b5132
RH		 2992#define elf32_arm_link_hash_traverse(table, func, info) \
2993 (elf_link_hash_traverse \
2994 (&(table)->root, \
b7693d02 2995 (bfd_boolean (*) (struct elf_link_hash_entry *, void *)) (func), \
252b5132
RH		 2996 (info)))
2997
2998/* Get the ARM elf linker hash table from a link_info structure. */
2999#define elf32_arm_hash_table(info) \
4dfe6ac6
NC		 3000 (elf_hash_table_id ((struct elf_link_hash_table *) ((info)->hash)) \
3001 == ARM_ELF_DATA ? ((struct elf32_arm_link_hash_table *) ((info)->hash)) : NULL)
252b5132 3002
906e58ca
NC		 3003#define arm_stub_hash_lookup(table, string, create, copy) \
3004 ((struct elf32_arm_stub_hash_entry *) \
3005 bfd_hash_lookup ((table), (string), (create), (copy)))
3006
21d799b5
NC		 3007/* Array to keep track of which stub sections have been created, and
3008 information on stub grouping. */
3009struct map_stub
3010{
3011 /* This is the section to which stubs in the group will be
3012 attached. */
3013 asection *link_sec;
3014 /* The stub section. */
3015 asection *stub_sec;
3016};
3017
0855e32b
NS		 3018#define elf32_arm_compute_jump_table_size(htab) \
3019 ((htab)->next_tls_desc_index * 4)
3020
9b485d32 3021/* ARM ELF linker hash table. */
252b5132 3022struct elf32_arm_link_hash_table
906e58ca
NC		 3023{
3024 /* The main hash table. */
3025 struct elf_link_hash_table root;
252b5132 3026
906e58ca
NC		 3027 /* The size in bytes of the section containing the Thumb-to-ARM glue. */
3028 bfd_size_type thumb_glue_size;
252b5132 3029
906e58ca
NC		 3030 /* The size in bytes of the section containing the ARM-to-Thumb glue. */
3031 bfd_size_type arm_glue_size;
252b5132 3032
906e58ca
NC		 3033 /* The size in bytes of section containing the ARMv4 BX veneers. */
3034 bfd_size_type bx_glue_size;
845b51d6 3035
906e58ca
NC		 3036 /* Offsets of ARMv4 BX veneers. Bit1 set if present, and Bit0 set when
3037 veneer has been populated. */
3038 bfd_vma bx_glue_offset[15];
845b51d6 3039
906e58ca
NC		 3040 /* The size in bytes of the section containing glue for VFP11 erratum
3041 veneers. */
3042 bfd_size_type vfp11_erratum_glue_size;
c7b8f16e 3043
a504d23a
LA		 3044 /* The size in bytes of the section containing glue for STM32L4XX erratum
3045 veneers. */
3046 bfd_size_type stm32l4xx_erratum_glue_size;
3047
48229727
JB		 3048 /* A table of fix locations for Cortex-A8 Thumb-2 branch/TLB erratum. This
3049 holds Cortex-A8 erratum fix locations between elf32_arm_size_stubs() and
3050 elf32_arm_write_section(). */
3051 struct a8_erratum_fix *a8_erratum_fixes;
3052 unsigned int num_a8_erratum_fixes;
3053
906e58ca
NC		 3054 /* An arbitrary input BFD chosen to hold the glue sections. */
3055 bfd * bfd_of_glue_owner;
ba96a88f 3056
906e58ca
NC		 3057 /* Nonzero to output a BE8 image. */
3058 int byteswap_code;
e489d0ae 3059
906e58ca
NC		 3060 /* Zero if R_ARM_TARGET1 means R_ARM_ABS32.
3061 Nonzero if R_ARM_TARGET1 means R_ARM_REL32. */
3062 int target1_is_rel;
9c504268 3063
906e58ca
NC		 3064 /* The relocation to use for R_ARM_TARGET2 relocations. */
3065 int target2_reloc;
eb043451 3066
906e58ca
NC		 3067 /* 0 = Ignore R_ARM_V4BX.
3068 1 = Convert BX to MOV PC.
3069 2 = Generate v4 interworing stubs. */
3070 int fix_v4bx;
319850b4 3071
48229727
JB		 3072 /* Whether we should fix the Cortex-A8 Thumb-2 branch/TLB erratum. */
3073 int fix_cortex_a8;
3074
2de70689
MGD		 3075 /* Whether we should fix the ARM1176 BLX immediate issue. */
3076 int fix_arm1176;
3077
906e58ca
NC		 3078 /* Nonzero if the ARM/Thumb BLX instructions are available for use. */
3079 int use_blx;
33bfe774 3080
906e58ca
NC		 3081 /* What sort of code sequences we should look for which may trigger the
3082 VFP11 denorm erratum. */
3083 bfd_arm_vfp11_fix vfp11_fix;
c7b8f16e 3084
906e58ca
NC		 3085 /* Global counter for the number of fixes we have emitted. */
3086 int num_vfp11_fixes;
c7b8f16e 3087
a504d23a
LA		 3088 /* What sort of code sequences we should look for which may trigger the
3089 STM32L4XX erratum. */
3090 bfd_arm_stm32l4xx_fix stm32l4xx_fix;
3091
3092 /* Global counter for the number of fixes we have emitted. */
3093 int num_stm32l4xx_fixes;
3094
906e58ca
NC		 3095 /* Nonzero to force PIC branch veneers. */
3096 int pic_veneer;
27e55c4d 3097
906e58ca
NC		 3098 /* The number of bytes in the initial entry in the PLT. */
3099 bfd_size_type plt_header_size;
e5a52504 3100
906e58ca
NC		 3101 /* The number of bytes in the subsequent PLT etries. */
3102 bfd_size_type plt_entry_size;
e5a52504 3103
906e58ca
NC		 3104 /* True if the target system is VxWorks. */
3105 int vxworks_p;
00a97672 3106
906e58ca
NC		 3107 /* True if the target system is Symbian OS. */
3108 int symbian_p;
e5a52504 3109
b38cadfb
NC		 3110 /* True if the target system is Native Client. */
3111 int nacl_p;
3112
906e58ca
NC		 3113 /* True if the target uses REL relocations. */
3114 int use_rel;
4e7fd91e 3115
0855e32b
NS		 3116 /* The index of the next unused R_ARM_TLS_DESC slot in .rel.plt. */
3117 bfd_vma next_tls_desc_index;
3118
3119 /* How many R_ARM_TLS_DESC relocations were generated so far. */
3120 bfd_vma num_tls_desc;
3121
906e58ca 3122 /* Short-cuts to get to dynamic linker sections. */
906e58ca
NC		 3123 asection *sdynbss;
3124 asection *srelbss;
5e681ec4 3125
906e58ca
NC		 3126 /* The (unloaded but important) VxWorks .rela.plt.unloaded section. */
3127 asection *srelplt2;
00a97672 3128
0855e32b
NS		 3129 /* The offset into splt of the PLT entry for the TLS descriptor
3130 resolver. Special values are 0, if not necessary (or not found
3131 to be necessary yet), and -1 if needed but not determined
3132 yet. */
3133 bfd_vma dt_tlsdesc_plt;
3134
3135 /* The offset into sgot of the GOT entry used by the PLT entry
3136 above. */
b38cadfb 3137 bfd_vma dt_tlsdesc_got;
0855e32b
NS		 3138
3139 /* Offset in .plt section of tls_arm_trampoline. */
3140 bfd_vma tls_trampoline;
3141
906e58ca
NC		 3142 /* Data for R_ARM_TLS_LDM32 relocations. */
3143 union
3144 {
3145 bfd_signed_vma refcount;
3146 bfd_vma offset;
3147 } tls_ldm_got;
b7693d02 3148
87d72d41
AM		 3149 /* Small local sym cache. */
3150 struct sym_cache sym_cache;
906e58ca
NC		 3151
3152 /* For convenience in allocate_dynrelocs. */
3153 bfd * obfd;
3154
0855e32b
NS		 3155 /* The amount of space used by the reserved portion of the sgotplt
3156 section, plus whatever space is used by the jump slots. */
3157 bfd_vma sgotplt_jump_table_size;
3158
906e58ca
NC		 3159 /* The stub hash table. */
3160 struct bfd_hash_table stub_hash_table;
3161
3162 /* Linker stub bfd. */
3163 bfd *stub_bfd;
3164
3165 /* Linker call-backs. */
7a89b94e 3166 asection * (*add_stub_section) (const char *, asection *, unsigned int);
906e58ca
NC		 3167 void (*layout_sections_again) (void);
3168
3169 /* Array to keep track of which stub sections have been created, and
3170 information on stub grouping. */
21d799b5 3171 struct map_stub *stub_group;
906e58ca 3172
fe33d2fa 3173 /* Number of elements in stub_group. */
7292b3ac 3174 unsigned int top_id;
fe33d2fa 3175
906e58ca
NC		 3176 /* Assorted information used by elf32_arm_size_stubs. */
3177 unsigned int bfd_count;
7292b3ac 3178 unsigned int top_index;
906e58ca
NC		 3179 asection **input_list;
3180};
252b5132 3181
a504d23a
LA		 3182static inline int
3183ctz (unsigned int mask)
3184{
3185#if GCC_VERSION >= 3004
3186 return __builtin_ctz (mask);
3187#else
3188 unsigned int i;
3189
3190 for (i = 0; i < 8 * sizeof (mask); i++)
3191 {
3192 if (mask & 0x1)
3193 break;
3194 mask = (mask >> 1);
3195 }
3196 return i;
3197#endif
3198}
3199
3200static inline int
3201popcount (unsigned int mask)
3202{
3203#if GCC_VERSION >= 3004
3204 return __builtin_popcount (mask);
3205#else
3206 unsigned int i, sum = 0;
3207
3208 for (i = 0; i < 8 * sizeof (mask); i++)
3209 {
3210 if (mask & 0x1)
3211 sum++;
3212 mask = (mask >> 1);
3213 }
3214 return sum;
3215#endif
3216}
3217
780a67af
NC		 3218/* Create an entry in an ARM ELF linker hash table. */
3219
3220static struct bfd_hash_entry *
57e8b36a 3221elf32_arm_link_hash_newfunc (struct bfd_hash_entry * entry,
99059e56
RM		 3222 struct bfd_hash_table * table,
3223 const char * string)
780a67af
NC		 3224{
3225 struct elf32_arm_link_hash_entry * ret =
3226 (struct elf32_arm_link_hash_entry *) entry;
3227
3228 /* Allocate the structure if it has not already been allocated by a
3229 subclass. */
906e58ca 3230 if (ret == NULL)
21d799b5 3231 ret = (struct elf32_arm_link_hash_entry *)
99059e56 3232 bfd_hash_allocate (table, sizeof (struct elf32_arm_link_hash_entry));
57e8b36a 3233 if (ret == NULL)
780a67af
NC		 3234 return (struct bfd_hash_entry *) ret;
3235
3236 /* Call the allocation method of the superclass. */
3237 ret = ((struct elf32_arm_link_hash_entry *)
3238 _bfd_elf_link_hash_newfunc ((struct bfd_hash_entry *) ret,
3239 table, string));
57e8b36a 3240 if (ret != NULL)
b7693d02 3241 {
0bdcacaf 3242 ret->dyn_relocs = NULL;
ba93b8ac 3243 ret->tls_type = GOT_UNKNOWN;
0855e32b 3244 ret->tlsdesc_got = (bfd_vma) -1;
34e77a92
RS		 3245 ret->plt.thumb_refcount = 0;
3246 ret->plt.maybe_thumb_refcount = 0;
3247 ret->plt.noncall_refcount = 0;
3248 ret->plt.got_offset = -1;
3249 ret->is_iplt = FALSE;
a4fd1a8e 3250 ret->export_glue = NULL;
906e58ca
NC		 3251
3252 ret->stub_cache = NULL;
b7693d02 3253 }
780a67af
NC		 3254
3255 return (struct bfd_hash_entry *) ret;
3256}
3257
34e77a92
RS		 3258/* Ensure that we have allocated bookkeeping structures for ABFD's local
3259 symbols. */
3260
3261static bfd_boolean
3262elf32_arm_allocate_local_sym_info (bfd *abfd)
3263{
3264 if (elf_local_got_refcounts (abfd) == NULL)
3265 {
3266 bfd_size_type num_syms;
3267 bfd_size_type size;
3268 char *data;
3269
3270 num_syms = elf_tdata (abfd)->symtab_hdr.sh_info;
3271 size = num_syms * (sizeof (bfd_signed_vma)
3272 + sizeof (struct arm_local_iplt_info *)
3273 + sizeof (bfd_vma)
3274 + sizeof (char));
3275 data = bfd_zalloc (abfd, size);
3276 if (data == NULL)
3277 return FALSE;
3278
3279 elf_local_got_refcounts (abfd) = (bfd_signed_vma *) data;
3280 data += num_syms * sizeof (bfd_signed_vma);
3281
3282 elf32_arm_local_iplt (abfd) = (struct arm_local_iplt_info **) data;
3283 data += num_syms * sizeof (struct arm_local_iplt_info *);
3284
3285 elf32_arm_local_tlsdesc_gotent (abfd) = (bfd_vma *) data;
3286 data += num_syms * sizeof (bfd_vma);
3287
3288 elf32_arm_local_got_tls_type (abfd) = data;
3289 }
3290 return TRUE;
3291}
3292
3293/* Return the .iplt information for local symbol R_SYMNDX, which belongs
3294 to input bfd ABFD. Create the information if it doesn't already exist.
3295 Return null if an allocation fails. */
3296
3297static struct arm_local_iplt_info *
3298elf32_arm_create_local_iplt (bfd *abfd, unsigned long r_symndx)
3299{
3300 struct arm_local_iplt_info **ptr;
3301
3302 if (!elf32_arm_allocate_local_sym_info (abfd))
3303 return NULL;
3304
3305 BFD_ASSERT (r_symndx < elf_tdata (abfd)->symtab_hdr.sh_info);
3306 ptr = &elf32_arm_local_iplt (abfd)[r_symndx];
3307 if (*ptr == NULL)
3308 *ptr = bfd_zalloc (abfd, sizeof (**ptr));
3309 return *ptr;
3310}
3311
3312/* Try to obtain PLT information for the symbol with index R_SYMNDX
3313 in ABFD's symbol table. If the symbol is global, H points to its
3314 hash table entry, otherwise H is null.
3315
3316 Return true if the symbol does have PLT information. When returning
3317 true, point *ROOT_PLT at the target-independent reference count/offset
3318 union and *ARM_PLT at the ARM-specific information. */
3319
3320static bfd_boolean
3321elf32_arm_get_plt_info (bfd *abfd, struct elf32_arm_link_hash_entry *h,
3322 unsigned long r_symndx, union gotplt_union **root_plt,
3323 struct arm_plt_info **arm_plt)
3324{
3325 struct arm_local_iplt_info *local_iplt;
3326
3327 if (h != NULL)
3328 {
3329 *root_plt = &h->root.plt;
3330 *arm_plt = &h->plt;
3331 return TRUE;
3332 }
3333
3334 if (elf32_arm_local_iplt (abfd) == NULL)
3335 return FALSE;
3336
3337 local_iplt = elf32_arm_local_iplt (abfd)[r_symndx];
3338 if (local_iplt == NULL)
3339 return FALSE;
3340
3341 *root_plt = &local_iplt->root;
3342 *arm_plt = &local_iplt->arm;
3343 return TRUE;
3344}
3345
3346/* Return true if the PLT described by ARM_PLT requires a Thumb stub
3347 before it. */
3348
3349static bfd_boolean
3350elf32_arm_plt_needs_thumb_stub_p (struct bfd_link_info *info,
3351 struct arm_plt_info *arm_plt)
3352{
3353 struct elf32_arm_link_hash_table *htab;
3354
3355 htab = elf32_arm_hash_table (info);
3356 return (arm_plt->thumb_refcount != 0
3357 || (!htab->use_blx && arm_plt->maybe_thumb_refcount != 0));
3358}
3359
3360/* Return a pointer to the head of the dynamic reloc list that should
3361 be used for local symbol ISYM, which is symbol number R_SYMNDX in
3362 ABFD's symbol table. Return null if an error occurs. */
3363
3364static struct elf_dyn_relocs **
3365elf32_arm_get_local_dynreloc_list (bfd *abfd, unsigned long r_symndx,
3366 Elf_Internal_Sym *isym)
3367{
3368 if (ELF32_ST_TYPE (isym->st_info) == STT_GNU_IFUNC)
3369 {
3370 struct arm_local_iplt_info *local_iplt;
3371
3372 local_iplt = elf32_arm_create_local_iplt (abfd, r_symndx);
3373 if (local_iplt == NULL)
3374 return NULL;
3375 return &local_iplt->dyn_relocs;
3376 }
3377 else
3378 {
3379 /* Track dynamic relocs needed for local syms too.
3380 We really need local syms available to do this
3381 easily. Oh well. */
3382 asection *s;
3383 void *vpp;
3384
3385 s = bfd_section_from_elf_index (abfd, isym->st_shndx);
3386 if (s == NULL)
3387 abort ();
3388
3389 vpp = &elf_section_data (s)->local_dynrel;
3390 return (struct elf_dyn_relocs **) vpp;
3391 }
3392}
3393
906e58ca
NC		 3394/* Initialize an entry in the stub hash table. */
3395
3396static struct bfd_hash_entry *
3397stub_hash_newfunc (struct bfd_hash_entry *entry,
3398 struct bfd_hash_table *table,
3399 const char *string)
3400{
3401 /* Allocate the structure if it has not already been allocated by a
3402 subclass. */
3403 if (entry == NULL)
3404 {
21d799b5 3405 entry = (struct bfd_hash_entry *)
99059e56 3406 bfd_hash_allocate (table, sizeof (struct elf32_arm_stub_hash_entry));
906e58ca
NC		 3407 if (entry == NULL)
3408 return entry;
3409 }
3410
3411 /* Call the allocation method of the superclass. */
3412 entry = bfd_hash_newfunc (entry, table, string);
3413 if (entry != NULL)
3414 {
3415 struct elf32_arm_stub_hash_entry *eh;
3416
3417 /* Initialize the local fields. */
3418 eh = (struct elf32_arm_stub_hash_entry *) entry;
3419 eh->stub_sec = NULL;
3420 eh->stub_offset = 0;
8d9d9490 3421 eh->source_value = 0;
906e58ca
NC		 3422 eh->target_value = 0;
3423 eh->target_section = NULL;
cedfb179 3424 eh->orig_insn = 0;
906e58ca 3425 eh->stub_type = arm_stub_none;
461a49ca
DJ		 3426 eh->stub_size = 0;
3427 eh->stub_template = NULL;
3428 eh->stub_template_size = 0;
906e58ca
NC		 3429 eh->h = NULL;
3430 eh->id_sec = NULL;
d8d2f433 3431 eh->output_name = NULL;
906e58ca
NC		 3432 }
3433
3434 return entry;
3435}
3436
00a97672 3437/* Create .got, .gotplt, and .rel(a).got sections in DYNOBJ, and set up
5e681ec4
PB		 3438 shortcuts to them in our hash table. */
3439
3440static bfd_boolean
57e8b36a 3441create_got_section (bfd *dynobj, struct bfd_link_info *info)
5e681ec4
PB		 3442{
3443 struct elf32_arm_link_hash_table *htab;
3444
e5a52504 3445 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 3446 if (htab == NULL)
3447 return FALSE;
3448
e5a52504
MM		 3449 /* BPABI objects never have a GOT, or associated sections. */
3450 if (htab->symbian_p)
3451 return TRUE;
3452
5e681ec4
PB		 3453 if (! _bfd_elf_create_got_section (dynobj, info))
3454 return FALSE;
3455
5e681ec4
PB		 3456 return TRUE;
3457}
3458
34e77a92
RS		 3459/* Create the .iplt, .rel(a).iplt and .igot.plt sections. */
3460
3461static bfd_boolean
3462create_ifunc_sections (struct bfd_link_info *info)
3463{
3464 struct elf32_arm_link_hash_table *htab;
3465 const struct elf_backend_data *bed;
3466 bfd *dynobj;
3467 asection *s;
3468 flagword flags;
b38cadfb 3469
34e77a92
RS		 3470 htab = elf32_arm_hash_table (info);
3471 dynobj = htab->root.dynobj;
3472 bed = get_elf_backend_data (dynobj);
3473 flags = bed->dynamic_sec_flags;
3474
3475 if (htab->root.iplt == NULL)
3476 {
3d4d4302
AM		 3477 s = bfd_make_section_anyway_with_flags (dynobj, ".iplt",
3478 flags | SEC_READONLY | SEC_CODE);
34e77a92 3479 if (s == NULL
a0f49396 3480 || !bfd_set_section_alignment (dynobj, s, bed->plt_alignment))
34e77a92
RS		 3481 return FALSE;
3482 htab->root.iplt = s;
3483 }
3484
3485 if (htab->root.irelplt == NULL)
3486 {
3d4d4302
AM		 3487 s = bfd_make_section_anyway_with_flags (dynobj,
3488 RELOC_SECTION (htab, ".iplt"),
3489 flags | SEC_READONLY);
34e77a92 3490 if (s == NULL
a0f49396 3491 || !bfd_set_section_alignment (dynobj, s, bed->s->log_file_align))
34e77a92
RS		 3492 return FALSE;
3493 htab->root.irelplt = s;
3494 }
3495
3496 if (htab->root.igotplt == NULL)
3497 {
3d4d4302 3498 s = bfd_make_section_anyway_with_flags (dynobj, ".igot.plt", flags);
34e77a92
RS		 3499 if (s == NULL
3500 || !bfd_set_section_alignment (dynobj, s, bed->s->log_file_align))
3501 return FALSE;
3502 htab->root.igotplt = s;
3503 }
3504 return TRUE;
3505}
3506
eed94f8f
NC		 3507/* Determine if we're dealing with a Thumb only architecture. */
3508
3509static bfd_boolean
3510using_thumb_only (struct elf32_arm_link_hash_table *globals)
3511{
2fd158eb
TP		 3512 int arch;
3513 int profile = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC,
3514 Tag_CPU_arch_profile);
eed94f8f 3515
2fd158eb
TP		 3516 if (profile)
3517 return profile == 'M';
eed94f8f 3518
2fd158eb 3519 arch = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC, Tag_CPU_arch);
eed94f8f 3520
2fd158eb
TP		 3521 if (arch == TAG_CPU_ARCH_V6_M
3522 || arch == TAG_CPU_ARCH_V6S_M
3523 || arch == TAG_CPU_ARCH_V7E_M
3524 || arch == TAG_CPU_ARCH_V8M_BASE
3525 || arch == TAG_CPU_ARCH_V8M_MAIN)
3526 return TRUE;
eed94f8f 3527
2fd158eb 3528 return FALSE;
eed94f8f
NC		 3529}
3530
3531/* Determine if we're dealing with a Thumb-2 object. */
3532
3533static bfd_boolean
3534using_thumb2 (struct elf32_arm_link_hash_table *globals)
3535{
3536 int arch = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC,
3537 Tag_CPU_arch);
3538 return arch == TAG_CPU_ARCH_V6T2 || arch >= TAG_CPU_ARCH_V7;
3539}
3540
00a97672
RS		 3541/* Create .plt, .rel(a).plt, .got, .got.plt, .rel(a).got, .dynbss, and
3542 .rel(a).bss sections in DYNOBJ, and set up shortcuts to them in our
5e681ec4
PB		 3543 hash table. */
3544
3545static bfd_boolean
57e8b36a 3546elf32_arm_create_dynamic_sections (bfd *dynobj, struct bfd_link_info *info)
5e681ec4
PB		 3547{
3548 struct elf32_arm_link_hash_table *htab;
3549
3550 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 3551 if (htab == NULL)
3552 return FALSE;
3553
362d30a1 3554 if (!htab->root.sgot && !create_got_section (dynobj, info))
5e681ec4
PB		 3555 return FALSE;
3556
3557 if (!_bfd_elf_create_dynamic_sections (dynobj, info))
3558 return FALSE;
3559
3d4d4302 3560 htab->sdynbss = bfd_get_linker_section (dynobj, ".dynbss");
0e1862bb 3561 if (!bfd_link_pic (info))
3d4d4302
AM		 3562 htab->srelbss = bfd_get_linker_section (dynobj,
3563 RELOC_SECTION (htab, ".bss"));
00a97672
RS		 3564
3565 if (htab->vxworks_p)
3566 {
3567 if (!elf_vxworks_create_dynamic_sections (dynobj, info, &htab->srelplt2))
3568 return FALSE;
3569
0e1862bb 3570 if (bfd_link_pic (info))
00a97672
RS		 3571 {
3572 htab->plt_header_size = 0;
3573 htab->plt_entry_size
3574 = 4 * ARRAY_SIZE (elf32_arm_vxworks_shared_plt_entry);
3575 }
3576 else
3577 {
3578 htab->plt_header_size
3579 = 4 * ARRAY_SIZE (elf32_arm_vxworks_exec_plt0_entry);
3580 htab->plt_entry_size
3581 = 4 * ARRAY_SIZE (elf32_arm_vxworks_exec_plt_entry);
3582 }
aebf9be7
NC		 3583
3584 if (elf_elfheader (dynobj))
3585 elf_elfheader (dynobj)->e_ident[EI_CLASS] = ELFCLASS32;
00a97672 3586 }
eed94f8f
NC		 3587 else
3588 {
3589 /* PR ld/16017
3590 Test for thumb only architectures. Note - we cannot just call
3591 using_thumb_only() as the attributes in the output bfd have not been
3592 initialised at this point, so instead we use the input bfd. */
3593 bfd * saved_obfd = htab->obfd;
3594
3595 htab->obfd = dynobj;
3596 if (using_thumb_only (htab))
3597 {
3598 htab->plt_header_size = 4 * ARRAY_SIZE (elf32_thumb2_plt0_entry);
3599 htab->plt_entry_size = 4 * ARRAY_SIZE (elf32_thumb2_plt_entry);
3600 }
3601 htab->obfd = saved_obfd;
3602 }
5e681ec4 3603
362d30a1
RS		 3604 if (!htab->root.splt
3605 || !htab->root.srelplt
e5a52504 3606 || !htab->sdynbss
0e1862bb 3607 || (!bfd_link_pic (info) && !htab->srelbss))
5e681ec4
PB		 3608 abort ();
3609
3610 return TRUE;
3611}
3612
906e58ca
NC		 3613/* Copy the extra info we tack onto an elf_link_hash_entry. */
3614
3615static void
3616elf32_arm_copy_indirect_symbol (struct bfd_link_info *info,
3617 struct elf_link_hash_entry *dir,
3618 struct elf_link_hash_entry *ind)
3619{
3620 struct elf32_arm_link_hash_entry *edir, *eind;
3621
3622 edir = (struct elf32_arm_link_hash_entry *) dir;
3623 eind = (struct elf32_arm_link_hash_entry *) ind;
3624
0bdcacaf 3625 if (eind->dyn_relocs != NULL)
906e58ca 3626 {
0bdcacaf 3627 if (edir->dyn_relocs != NULL)
906e58ca 3628 {
0bdcacaf
RS		 3629 struct elf_dyn_relocs **pp;
3630 struct elf_dyn_relocs *p;
906e58ca
NC		 3631
3632 /* Add reloc counts against the indirect sym to the direct sym
3633 list. Merge any entries against the same section. */
0bdcacaf 3634 for (pp = &eind->dyn_relocs; (p = *pp) != NULL; )
906e58ca 3635 {
0bdcacaf 3636 struct elf_dyn_relocs *q;
906e58ca 3637
0bdcacaf
RS		 3638 for (q = edir->dyn_relocs; q != NULL; q = q->next)
3639 if (q->sec == p->sec)
906e58ca
NC		 3640 {
3641 q->pc_count += p->pc_count;
3642 q->count += p->count;
3643 *pp = p->next;
3644 break;
3645 }
3646 if (q == NULL)
3647 pp = &p->next;
3648 }
0bdcacaf 3649 *pp = edir->dyn_relocs;
906e58ca
NC		 3650 }
3651
0bdcacaf
RS		 3652 edir->dyn_relocs = eind->dyn_relocs;
3653 eind->dyn_relocs = NULL;
906e58ca
NC		 3654 }
3655
3656 if (ind->root.type == bfd_link_hash_indirect)
3657 {
3658 /* Copy over PLT info. */
34e77a92
RS		 3659 edir->plt.thumb_refcount += eind->plt.thumb_refcount;
3660 eind->plt.thumb_refcount = 0;
3661 edir->plt.maybe_thumb_refcount += eind->plt.maybe_thumb_refcount;
3662 eind->plt.maybe_thumb_refcount = 0;
3663 edir->plt.noncall_refcount += eind->plt.noncall_refcount;
3664 eind->plt.noncall_refcount = 0;
3665
3666 /* We should only allocate a function to .iplt once the final
3667 symbol information is known. */
3668 BFD_ASSERT (!eind->is_iplt);
906e58ca
NC		 3669
3670 if (dir->got.refcount <= 0)
3671 {
3672 edir->tls_type = eind->tls_type;
3673 eind->tls_type = GOT_UNKNOWN;
3674 }
3675 }
3676
3677 _bfd_elf_link_hash_copy_indirect (info, dir, ind);
3678}
3679
68faa637
AM		 3680/* Destroy an ARM elf linker hash table. */
3681
3682static void
d495ab0d 3683elf32_arm_link_hash_table_free (bfd *obfd)
68faa637
AM		 3684{
3685 struct elf32_arm_link_hash_table *ret
d495ab0d 3686 = (struct elf32_arm_link_hash_table *) obfd->link.hash;
68faa637
AM		 3687
3688 bfd_hash_table_free (&ret->stub_hash_table);
d495ab0d 3689 _bfd_elf_link_hash_table_free (obfd);
68faa637
AM		 3690}
3691
906e58ca
NC		 3692/* Create an ARM elf linker hash table. */
3693
3694static struct bfd_link_hash_table *
3695elf32_arm_link_hash_table_create (bfd *abfd)
3696{
3697 struct elf32_arm_link_hash_table *ret;
3698 bfd_size_type amt = sizeof (struct elf32_arm_link_hash_table);
3699
7bf52ea2 3700 ret = (struct elf32_arm_link_hash_table *) bfd_zmalloc (amt);
906e58ca
NC		 3701 if (ret == NULL)
3702 return NULL;
3703
3704 if (!_bfd_elf_link_hash_table_init (& ret->root, abfd,
3705 elf32_arm_link_hash_newfunc,
4dfe6ac6
NC		 3706 sizeof (struct elf32_arm_link_hash_entry),
3707 ARM_ELF_DATA))
906e58ca
NC		 3708 {
3709 free (ret);
3710 return NULL;
3711 }
3712
906e58ca 3713 ret->vfp11_fix = BFD_ARM_VFP11_FIX_NONE;
a504d23a 3714 ret->stm32l4xx_fix = BFD_ARM_STM32L4XX_FIX_NONE;
906e58ca
NC		 3715#ifdef FOUR_WORD_PLT
3716 ret->plt_header_size = 16;
3717 ret->plt_entry_size = 16;
3718#else
3719 ret->plt_header_size = 20;
1db37fe6 3720 ret->plt_entry_size = elf32_arm_use_long_plt_entry ? 16 : 12;
906e58ca 3721#endif
906e58ca 3722 ret->use_rel = 1;
906e58ca 3723 ret->obfd = abfd;
906e58ca
NC		 3724
3725 if (!bfd_hash_table_init (&ret->stub_hash_table, stub_hash_newfunc,
3726 sizeof (struct elf32_arm_stub_hash_entry)))
3727 {
d495ab0d 3728 _bfd_elf_link_hash_table_free (abfd);
906e58ca
NC		 3729 return NULL;
3730 }
d495ab0d 3731 ret->root.root.hash_table_free = elf32_arm_link_hash_table_free;
906e58ca
NC		 3732
3733 return &ret->root.root;
3734}
3735
cd1dac3d
DG		 3736/* Determine what kind of NOPs are available. */
3737
3738static bfd_boolean
3739arch_has_arm_nop (struct elf32_arm_link_hash_table *globals)
3740{
3741 const int arch = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC,
3742 Tag_CPU_arch);
3743 return arch == TAG_CPU_ARCH_V6T2
3744 || arch == TAG_CPU_ARCH_V6K
9e3c6df6
PB		 3745 || arch == TAG_CPU_ARCH_V7
3746 || arch == TAG_CPU_ARCH_V7E_M;
cd1dac3d
DG		 3747}
3748
3749static bfd_boolean
3750arch_has_thumb2_nop (struct elf32_arm_link_hash_table *globals)
3751{
3752 const int arch = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC,
3753 Tag_CPU_arch);
9e3c6df6
PB		 3754 return (arch == TAG_CPU_ARCH_V6T2 || arch == TAG_CPU_ARCH_V7
3755 || arch == TAG_CPU_ARCH_V7E_M);
cd1dac3d
DG		 3756}
3757
f4ac8484
DJ		 3758static bfd_boolean
3759arm_stub_is_thumb (enum elf32_arm_stub_type stub_type)
3760{
3761 switch (stub_type)
3762 {
fea2b4d6
CL		 3763 case arm_stub_long_branch_thumb_only:
3764 case arm_stub_long_branch_v4t_thumb_arm:
3765 case arm_stub_short_branch_v4t_thumb_arm:
ebe24dd4 3766 case arm_stub_long_branch_v4t_thumb_arm_pic:
12352d3f 3767 case arm_stub_long_branch_v4t_thumb_tls_pic:
ebe24dd4 3768 case arm_stub_long_branch_thumb_only_pic:
f4ac8484
DJ		 3769 return TRUE;
3770 case arm_stub_none:
3771 BFD_FAIL ();
3772 return FALSE;
3773 break;
3774 default:
3775 return FALSE;
3776 }
3777}
3778
906e58ca
NC		 3779/* Determine the type of stub needed, if any, for a call. */
3780
3781static enum elf32_arm_stub_type
3782arm_type_of_stub (struct bfd_link_info *info,
3783 asection *input_sec,
3784 const Elf_Internal_Rela *rel,
34e77a92 3785 unsigned char st_type,
35fc36a8 3786 enum arm_st_branch_type *actual_branch_type,
906e58ca 3787 struct elf32_arm_link_hash_entry *hash,
c820be07
NC		 3788 bfd_vma destination,
3789 asection *sym_sec,
3790 bfd *input_bfd,
3791 const char *name)
906e58ca
NC		 3792{
3793 bfd_vma location;
3794 bfd_signed_vma branch_offset;
3795 unsigned int r_type;
3796 struct elf32_arm_link_hash_table * globals;
3797 int thumb2;
3798 int thumb_only;
3799 enum elf32_arm_stub_type stub_type = arm_stub_none;
5fa9e92f 3800 int use_plt = 0;
35fc36a8 3801 enum arm_st_branch_type branch_type = *actual_branch_type;
34e77a92
RS		 3802 union gotplt_union *root_plt;
3803 struct arm_plt_info *arm_plt;
906e58ca 3804
35fc36a8 3805 if (branch_type == ST_BRANCH_LONG)
da5938a2
NC		 3806 return stub_type;
3807
906e58ca 3808 globals = elf32_arm_hash_table (info);
4dfe6ac6
NC		 3809 if (globals == NULL)
3810 return stub_type;
906e58ca
NC		 3811
3812 thumb_only = using_thumb_only (globals);
3813
3814 thumb2 = using_thumb2 (globals);
3815
3816 /* Determine where the call point is. */
3817 location = (input_sec->output_offset
3818 + input_sec->output_section->vma
3819 + rel->r_offset);
3820
906e58ca
NC		 3821 r_type = ELF32_R_TYPE (rel->r_info);
3822
39f21624
NC		 3823 /* ST_BRANCH_TO_ARM is nonsense to thumb-only targets when we
3824 are considering a function call relocation. */
c5423981
TG		 3825 if (thumb_only && (r_type == R_ARM_THM_CALL || r_type == R_ARM_THM_JUMP24
3826 || r_type == R_ARM_THM_JUMP19)
39f21624
NC		 3827 && branch_type == ST_BRANCH_TO_ARM)
3828 branch_type = ST_BRANCH_TO_THUMB;
3829
34e77a92
RS		 3830 /* For TLS call relocs, it is the caller's responsibility to provide
3831 the address of the appropriate trampoline. */
3832 if (r_type != R_ARM_TLS_CALL
3833 && r_type != R_ARM_THM_TLS_CALL
3834 && elf32_arm_get_plt_info (input_bfd, hash, ELF32_R_SYM (rel->r_info),
3835 &root_plt, &arm_plt)
3836 && root_plt->offset != (bfd_vma) -1)
5fa9e92f 3837 {
34e77a92 3838 asection *splt;
fe33d2fa 3839
34e77a92
RS		 3840 if (hash == NULL || hash->is_iplt)
3841 splt = globals->root.iplt;
3842 else
3843 splt = globals->root.splt;
3844 if (splt != NULL)
b38cadfb 3845 {
34e77a92
RS		 3846 use_plt = 1;
3847
3848 /* Note when dealing with PLT entries: the main PLT stub is in
3849 ARM mode, so if the branch is in Thumb mode, another
3850 Thumb->ARM stub will be inserted later just before the ARM
3851 PLT stub. We don't take this extra distance into account
3852 here, because if a long branch stub is needed, we'll add a
3853 Thumb->Arm one and branch directly to the ARM PLT entry
3854 because it avoids spreading offset corrections in several
3855 places. */
3856
3857 destination = (splt->output_section->vma
3858 + splt->output_offset
3859 + root_plt->offset);
3860 st_type = STT_FUNC;
3861 branch_type = ST_BRANCH_TO_ARM;
3862 }
5fa9e92f 3863 }
34e77a92
RS		 3864 /* Calls to STT_GNU_IFUNC symbols should go through a PLT. */
3865 BFD_ASSERT (st_type != STT_GNU_IFUNC);
906e58ca 3866
fe33d2fa
CL		 3867 branch_offset = (bfd_signed_vma)(destination - location);
3868
0855e32b 3869 if (r_type == R_ARM_THM_CALL || r_type == R_ARM_THM_JUMP24
c5423981 3870 || r_type == R_ARM_THM_TLS_CALL || r_type == R_ARM_THM_JUMP19)
906e58ca 3871 {
5fa9e92f
CL		 3872 /* Handle cases where:
3873 - this call goes too far (different Thumb/Thumb2 max
99059e56 3874 distance)
155d87d7 3875 - it's a Thumb->Arm call and blx is not available, or it's a
99059e56
RM		 3876 Thumb->Arm branch (not bl). A stub is needed in this case,
3877 but only if this call is not through a PLT entry. Indeed,
3878 PLT stubs handle mode switching already.
5fa9e92f 3879 */
906e58ca
NC		 3880 if ((!thumb2
3881 && (branch_offset > THM_MAX_FWD_BRANCH_OFFSET
3882 || (branch_offset < THM_MAX_BWD_BRANCH_OFFSET)))
3883 || (thumb2
3884 && (branch_offset > THM2_MAX_FWD_BRANCH_OFFSET
3885 || (branch_offset < THM2_MAX_BWD_BRANCH_OFFSET)))
c5423981
TG		 3886 || (thumb2
3887 && (branch_offset > THM2_MAX_FWD_COND_BRANCH_OFFSET
3888 || (branch_offset < THM2_MAX_BWD_COND_BRANCH_OFFSET))
3889 && (r_type == R_ARM_THM_JUMP19))
35fc36a8 3890 || (branch_type == ST_BRANCH_TO_ARM
0855e32b
NS		 3891 && (((r_type == R_ARM_THM_CALL
3892 || r_type == R_ARM_THM_TLS_CALL) && !globals->use_blx)
c5423981
TG		 3893 || (r_type == R_ARM_THM_JUMP24)
3894 || (r_type == R_ARM_THM_JUMP19))
5fa9e92f 3895 && !use_plt))
906e58ca 3896 {
35fc36a8 3897 if (branch_type == ST_BRANCH_TO_THUMB)
906e58ca
NC		 3898 {
3899 /* Thumb to thumb. */
3900 if (!thumb_only)
3901 {
0e1862bb 3902 stub_type = (bfd_link_pic (info) | globals->pic_veneer)
c2b4a39d 3903 /* PIC stubs. */
155d87d7 3904 ? ((globals->use_blx
9553db3c 3905 && (r_type == R_ARM_THM_CALL))
155d87d7
CL		 3906 /* V5T and above. Stub starts with ARM code, so
3907 we must be able to switch mode before
3908 reaching it, which is only possible for 'bl'
3909 (ie R_ARM_THM_CALL relocation). */
cf3eccff 3910 ? arm_stub_long_branch_any_thumb_pic
ebe24dd4 3911 /* On V4T, use Thumb code only. */
d3626fb0 3912 : arm_stub_long_branch_v4t_thumb_thumb_pic)
c2b4a39d
CL		 3913
3914 /* non-PIC stubs. */
155d87d7 3915 : ((globals->use_blx
9553db3c 3916 && (r_type == R_ARM_THM_CALL))
c2b4a39d
CL		 3917 /* V5T and above. */
3918 ? arm_stub_long_branch_any_any
3919 /* V4T. */
d3626fb0 3920 : arm_stub_long_branch_v4t_thumb_thumb);
906e58ca
NC		 3921 }
3922 else
3923 {
0e1862bb 3924 stub_type = (bfd_link_pic (info) | globals->pic_veneer)
ebe24dd4
CL		 3925 /* PIC stub. */
3926 ? arm_stub_long_branch_thumb_only_pic
c2b4a39d
CL		 3927 /* non-PIC stub. */
3928 : arm_stub_long_branch_thumb_only;
906e58ca
NC		 3929 }
3930 }
3931 else
3932 {
3933 /* Thumb to arm. */
c820be07
NC		 3934 if (sym_sec != NULL
3935 && sym_sec->owner != NULL
3936 && !INTERWORK_FLAG (sym_sec->owner))
3937 {
3938 (*_bfd_error_handler)
3939 (_("%B(%s): warning: interworking not enabled.\n"
3940 " first occurrence: %B: Thumb call to ARM"),
3941 sym_sec->owner, input_bfd, name);
3942 }
3943
0855e32b 3944 stub_type =
0e1862bb 3945 (bfd_link_pic (info) | globals->pic_veneer)
c2b4a39d 3946 /* PIC stubs. */
0855e32b 3947 ? (r_type == R_ARM_THM_TLS_CALL
6a631e86 3948 /* TLS PIC stubs. */
0855e32b
NS		 3949 ? (globals->use_blx ? arm_stub_long_branch_any_tls_pic
3950 : arm_stub_long_branch_v4t_thumb_tls_pic)
3951 : ((globals->use_blx && r_type == R_ARM_THM_CALL)
3952 /* V5T PIC and above. */
3953 ? arm_stub_long_branch_any_arm_pic
3954 /* V4T PIC stub. */
3955 : arm_stub_long_branch_v4t_thumb_arm_pic))
c2b4a39d
CL		 3956
3957 /* non-PIC stubs. */
0855e32b 3958 : ((globals->use_blx && r_type == R_ARM_THM_CALL)
c2b4a39d
CL		 3959 /* V5T and above. */
3960 ? arm_stub_long_branch_any_any
3961 /* V4T. */
3962 : arm_stub_long_branch_v4t_thumb_arm);
c820be07
NC		 3963
3964 /* Handle v4t short branches. */
fea2b4d6 3965 if ((stub_type == arm_stub_long_branch_v4t_thumb_arm)
c820be07
NC		 3966 && (branch_offset <= THM_MAX_FWD_BRANCH_OFFSET)
3967 && (branch_offset >= THM_MAX_BWD_BRANCH_OFFSET))
fea2b4d6 3968 stub_type = arm_stub_short_branch_v4t_thumb_arm;
906e58ca
NC		 3969 }
3970 }
3971 }
fe33d2fa
CL		 3972 else if (r_type == R_ARM_CALL
3973 || r_type == R_ARM_JUMP24
0855e32b
NS		 3974 || r_type == R_ARM_PLT32
3975 || r_type == R_ARM_TLS_CALL)
906e58ca 3976 {
35fc36a8 3977 if (branch_type == ST_BRANCH_TO_THUMB)
906e58ca
NC		 3978 {
3979 /* Arm to thumb. */
c820be07
NC		 3980
3981 if (sym_sec != NULL
3982 && sym_sec->owner != NULL
3983 && !INTERWORK_FLAG (sym_sec->owner))
3984 {
3985 (*_bfd_error_handler)
3986 (_("%B(%s): warning: interworking not enabled.\n"
c2b4a39d 3987 " first occurrence: %B: ARM call to Thumb"),
c820be07
NC		 3988 sym_sec->owner, input_bfd, name);
3989 }
3990
3991 /* We have an extra 2-bytes reach because of
3992 the mode change (bit 24 (H) of BLX encoding). */
4116d8d7
PB		 3993 if (branch_offset > (ARM_MAX_FWD_BRANCH_OFFSET + 2)
3994 || (branch_offset < ARM_MAX_BWD_BRANCH_OFFSET)
0855e32b 3995 || (r_type == R_ARM_CALL && !globals->use_blx)
4116d8d7
PB		 3996 || (r_type == R_ARM_JUMP24)
3997 || (r_type == R_ARM_PLT32))
906e58ca 3998 {
0e1862bb 3999 stub_type = (bfd_link_pic (info) | globals->pic_veneer)
c2b4a39d 4000 /* PIC stubs. */
ebe24dd4
CL		 4001 ? ((globals->use_blx)
4002 /* V5T and above. */
4003 ? arm_stub_long_branch_any_thumb_pic
4004 /* V4T stub. */
4005 : arm_stub_long_branch_v4t_arm_thumb_pic)
4006
c2b4a39d
CL		 4007 /* non-PIC stubs. */
4008 : ((globals->use_blx)
4009 /* V5T and above. */
4010 ? arm_stub_long_branch_any_any
4011 /* V4T. */
4012 : arm_stub_long_branch_v4t_arm_thumb);
906e58ca
NC		 4013 }
4014 }
4015 else
4016 {
4017 /* Arm to arm. */
4018 if (branch_offset > ARM_MAX_FWD_BRANCH_OFFSET
4019 || (branch_offset < ARM_MAX_BWD_BRANCH_OFFSET))
4020 {
0855e32b 4021 stub_type =
0e1862bb 4022 (bfd_link_pic (info) | globals->pic_veneer)
c2b4a39d 4023 /* PIC stubs. */
0855e32b 4024 ? (r_type == R_ARM_TLS_CALL
6a631e86 4025 /* TLS PIC Stub. */
0855e32b 4026 ? arm_stub_long_branch_any_tls_pic
7a89b94e
NC		 4027 : (globals->nacl_p
4028 ? arm_stub_long_branch_arm_nacl_pic
4029 : arm_stub_long_branch_any_arm_pic))
c2b4a39d 4030 /* non-PIC stubs. */
7a89b94e
NC		 4031 : (globals->nacl_p
4032 ? arm_stub_long_branch_arm_nacl
4033 : arm_stub_long_branch_any_any);
906e58ca
NC		 4034 }
4035 }
4036 }
4037
fe33d2fa
CL		 4038 /* If a stub is needed, record the actual destination type. */
4039 if (stub_type != arm_stub_none)
35fc36a8 4040 *actual_branch_type = branch_type;
fe33d2fa 4041
906e58ca
NC		 4042 return stub_type;
4043}
4044
4045/* Build a name for an entry in the stub hash table. */
4046
4047static char *
4048elf32_arm_stub_name (const asection *input_section,
4049 const asection *sym_sec,
4050 const struct elf32_arm_link_hash_entry *hash,
fe33d2fa
CL		 4051 const Elf_Internal_Rela *rel,
4052 enum elf32_arm_stub_type stub_type)
906e58ca
NC		 4053{
4054 char *stub_name;
4055 bfd_size_type len;
4056
4057 if (hash)
4058 {
fe33d2fa 4059 len = 8 + 1 + strlen (hash->root.root.root.string) + 1 + 8 + 1 + 2 + 1;
21d799b5 4060 stub_name = (char *) bfd_malloc (len);
906e58ca 4061 if (stub_name != NULL)
fe33d2fa 4062 sprintf (stub_name, "%08x_%s+%x_%d",
906e58ca
NC		 4063 input_section->id & 0xffffffff,
4064 hash->root.root.root.string,
fe33d2fa
CL		 4065 (int) rel->r_addend & 0xffffffff,
4066 (int) stub_type);
906e58ca
NC		 4067 }
4068 else
4069 {
fe33d2fa 4070 len = 8 + 1 + 8 + 1 + 8 + 1 + 8 + 1 + 2 + 1;
21d799b5 4071 stub_name = (char *) bfd_malloc (len);
906e58ca 4072 if (stub_name != NULL)
fe33d2fa 4073 sprintf (stub_name, "%08x_%x:%x+%x_%d",
906e58ca
NC		 4074 input_section->id & 0xffffffff,
4075 sym_sec->id & 0xffffffff,
0855e32b
NS		 4076 ELF32_R_TYPE (rel->r_info) == R_ARM_TLS_CALL
4077 || ELF32_R_TYPE (rel->r_info) == R_ARM_THM_TLS_CALL
4078 ? 0 : (int) ELF32_R_SYM (rel->r_info) & 0xffffffff,
fe33d2fa
CL		 4079 (int) rel->r_addend & 0xffffffff,
4080 (int) stub_type);
906e58ca
NC		 4081 }
4082
4083 return stub_name;
4084}
4085
4086/* Look up an entry in the stub hash. Stub entries are cached because
4087 creating the stub name takes a bit of time. */
4088
4089static struct elf32_arm_stub_hash_entry *
4090elf32_arm_get_stub_entry (const asection *input_section,
4091 const asection *sym_sec,
4092 struct elf_link_hash_entry *hash,
4093 const Elf_Internal_Rela *rel,
fe33d2fa
CL		 4094 struct elf32_arm_link_hash_table *htab,
4095 enum elf32_arm_stub_type stub_type)
906e58ca
NC		 4096{
4097 struct elf32_arm_stub_hash_entry *stub_entry;
4098 struct elf32_arm_link_hash_entry *h = (struct elf32_arm_link_hash_entry *) hash;
4099 const asection *id_sec;
4100
4101 if ((input_section->flags & SEC_CODE) == 0)
4102 return NULL;
4103
4104 /* If this input section is part of a group of sections sharing one
4105 stub section, then use the id of the first section in the group.
4106 Stub names need to include a section id, as there may well be
4107 more than one stub used to reach say, printf, and we need to
4108 distinguish between them. */
4109 id_sec = htab->stub_group[input_section->id].link_sec;
4110
4111 if (h != NULL && h->stub_cache != NULL
4112 && h->stub_cache->h == h
fe33d2fa
CL		 4113 && h->stub_cache->id_sec == id_sec
4114 && h->stub_cache->stub_type == stub_type)
906e58ca
NC		 4115 {
4116 stub_entry = h->stub_cache;
4117 }
4118 else
4119 {
4120 char *stub_name;
4121
fe33d2fa 4122 stub_name = elf32_arm_stub_name (id_sec, sym_sec, h, rel, stub_type);
906e58ca
NC		 4123 if (stub_name == NULL)
4124 return NULL;
4125
4126 stub_entry = arm_stub_hash_lookup (&htab->stub_hash_table,
4127 stub_name, FALSE, FALSE);
4128 if (h != NULL)
4129 h->stub_cache = stub_entry;
4130
4131 free (stub_name);
4132 }
4133
4134 return stub_entry;
4135}
4136
48229727 4137/* Find or create a stub section. Returns a pointer to the stub section, and
b38cadfb 4138 the section to which the stub section will be attached (in *LINK_SEC_P).
48229727 4139 LINK_SEC_P may be NULL. */
906e58ca 4140
48229727
JB		 4141static asection *
4142elf32_arm_create_or_find_stub_sec (asection **link_sec_p, asection *section,
4143 struct elf32_arm_link_hash_table *htab)
906e58ca
NC		 4144{
4145 asection *link_sec;
4146 asection *stub_sec;
906e58ca
NC		 4147
4148 link_sec = htab->stub_group[section->id].link_sec;
9553db3c 4149 BFD_ASSERT (link_sec != NULL);
906e58ca 4150 stub_sec = htab->stub_group[section->id].stub_sec;
9553db3c 4151
906e58ca
NC		 4152 if (stub_sec == NULL)
4153 {
4154 stub_sec = htab->stub_group[link_sec->id].stub_sec;
4155 if (stub_sec == NULL)
4156 {
4157 size_t namelen;
4158 bfd_size_type len;
4159 char *s_name;
4160
4161 namelen = strlen (link_sec->name);
4162 len = namelen + sizeof (STUB_SUFFIX);
21d799b5 4163 s_name = (char *) bfd_alloc (htab->stub_bfd, len);
906e58ca
NC		 4164 if (s_name == NULL)
4165 return NULL;
4166
4167 memcpy (s_name, link_sec->name, namelen);
4168 memcpy (s_name + namelen, STUB_SUFFIX, sizeof (STUB_SUFFIX));
7a89b94e
NC		 4169 stub_sec = (*htab->add_stub_section) (s_name, link_sec,
4170 htab->nacl_p ? 4 : 3);
906e58ca
NC		 4171 if (stub_sec == NULL)
4172 return NULL;
4173 htab->stub_group[link_sec->id].stub_sec = stub_sec;
4174 }
4175 htab->stub_group[section->id].stub_sec = stub_sec;
4176 }
b38cadfb 4177
48229727
JB		 4178 if (link_sec_p)
4179 *link_sec_p = link_sec;
b38cadfb 4180
48229727
JB		 4181 return stub_sec;
4182}
4183
4184/* Add a new stub entry to the stub hash. Not all fields of the new
4185 stub entry are initialised. */
4186
4187static struct elf32_arm_stub_hash_entry *
4188elf32_arm_add_stub (const char *stub_name,
4189 asection *section,
4190 struct elf32_arm_link_hash_table *htab)
4191{
4192 asection *link_sec;
4193 asection *stub_sec;
4194 struct elf32_arm_stub_hash_entry *stub_entry;
4195
4196 stub_sec = elf32_arm_create_or_find_stub_sec (&link_sec, section, htab);
4197 if (stub_sec == NULL)
4198 return NULL;
906e58ca
NC		 4199
4200 /* Enter this entry into the linker stub hash table. */
4201 stub_entry = arm_stub_hash_lookup (&htab->stub_hash_table, stub_name,
4202 TRUE, FALSE);
4203 if (stub_entry == NULL)
4204 {
4205 (*_bfd_error_handler) (_("%s: cannot create stub entry %s"),
4206 section->owner,
4207 stub_name);
4208 return NULL;
4209 }
4210
4211 stub_entry->stub_sec = stub_sec;
4212 stub_entry->stub_offset = 0;
4213 stub_entry->id_sec = link_sec;
4214
906e58ca
NC		 4215 return stub_entry;
4216}
4217
4218/* Store an Arm insn into an output section not processed by
4219 elf32_arm_write_section. */
4220
4221static void
8029a119
NC		 4222put_arm_insn (struct elf32_arm_link_hash_table * htab,
4223 bfd * output_bfd, bfd_vma val, void * ptr)
906e58ca
NC		 4224{
4225 if (htab->byteswap_code != bfd_little_endian (output_bfd))
4226 bfd_putl32 (val, ptr);
4227 else
4228 bfd_putb32 (val, ptr);
4229}
4230
4231/* Store a 16-bit Thumb insn into an output section not processed by
4232 elf32_arm_write_section. */
4233
4234static void
8029a119
NC		 4235put_thumb_insn (struct elf32_arm_link_hash_table * htab,
4236 bfd * output_bfd, bfd_vma val, void * ptr)
906e58ca
NC		 4237{
4238 if (htab->byteswap_code != bfd_little_endian (output_bfd))
4239 bfd_putl16 (val, ptr);
4240 else
4241 bfd_putb16 (val, ptr);
4242}
4243
a504d23a
LA		 4244/* Store a Thumb2 insn into an output section not processed by
4245 elf32_arm_write_section. */
4246
4247static void
4248put_thumb2_insn (struct elf32_arm_link_hash_table * htab,
b98e6871 4249 bfd * output_bfd, bfd_vma val, bfd_byte * ptr)
a504d23a
LA		 4250{
4251 /* T2 instructions are 16-bit streamed. */
4252 if (htab->byteswap_code != bfd_little_endian (output_bfd))
4253 {
4254 bfd_putl16 ((val >> 16) & 0xffff, ptr);
4255 bfd_putl16 ((val & 0xffff), ptr + 2);
4256 }
4257 else
4258 {
4259 bfd_putb16 ((val >> 16) & 0xffff, ptr);
4260 bfd_putb16 ((val & 0xffff), ptr + 2);
4261 }
4262}
4263
0855e32b
NS		 4264/* If it's possible to change R_TYPE to a more efficient access
4265 model, return the new reloc type. */
4266
4267static unsigned
b38cadfb 4268elf32_arm_tls_transition (struct bfd_link_info *info, int r_type,
0855e32b
NS		 4269 struct elf_link_hash_entry *h)
4270{
4271 int is_local = (h == NULL);
4272
0e1862bb
L		 4273 if (bfd_link_pic (info)
4274 || (h && h->root.type == bfd_link_hash_undefweak))
0855e32b
NS		 4275 return r_type;
4276
b38cadfb 4277 /* We do not support relaxations for Old TLS models. */
0855e32b
NS		 4278 switch (r_type)
4279 {
4280 case R_ARM_TLS_GOTDESC:
4281 case R_ARM_TLS_CALL:
4282 case R_ARM_THM_TLS_CALL:
4283 case R_ARM_TLS_DESCSEQ:
4284 case R_ARM_THM_TLS_DESCSEQ:
4285 return is_local ? R_ARM_TLS_LE32 : R_ARM_TLS_IE32;
4286 }
4287
4288 return r_type;
4289}
4290
48229727
JB		 4291static bfd_reloc_status_type elf32_arm_final_link_relocate
4292 (reloc_howto_type *, bfd *, bfd *, asection *, bfd_byte *,
4293 Elf_Internal_Rela *, bfd_vma, struct bfd_link_info *, asection *,
34e77a92
RS		 4294 const char *, unsigned char, enum arm_st_branch_type,
4295 struct elf_link_hash_entry *, bfd_boolean *, char **);
48229727 4296
4563a860
JB		 4297static unsigned int
4298arm_stub_required_alignment (enum elf32_arm_stub_type stub_type)
4299{
4300 switch (stub_type)
4301 {
4302 case arm_stub_a8_veneer_b_cond:
4303 case arm_stub_a8_veneer_b:
4304 case arm_stub_a8_veneer_bl:
4305 return 2;
4306
4307 case arm_stub_long_branch_any_any:
4308 case arm_stub_long_branch_v4t_arm_thumb:
4309 case arm_stub_long_branch_thumb_only:
4310 case arm_stub_long_branch_v4t_thumb_thumb:
4311 case arm_stub_long_branch_v4t_thumb_arm:
4312 case arm_stub_short_branch_v4t_thumb_arm:
4313 case arm_stub_long_branch_any_arm_pic:
4314 case arm_stub_long_branch_any_thumb_pic:
4315 case arm_stub_long_branch_v4t_thumb_thumb_pic:
4316 case arm_stub_long_branch_v4t_arm_thumb_pic:
4317 case arm_stub_long_branch_v4t_thumb_arm_pic:
4318 case arm_stub_long_branch_thumb_only_pic:
0855e32b
NS		 4319 case arm_stub_long_branch_any_tls_pic:
4320 case arm_stub_long_branch_v4t_thumb_tls_pic:
4563a860
JB		 4321 case arm_stub_a8_veneer_blx:
4322 return 4;
b38cadfb 4323
7a89b94e
NC		 4324 case arm_stub_long_branch_arm_nacl:
4325 case arm_stub_long_branch_arm_nacl_pic:
4326 return 16;
4327
4563a860
JB		 4328 default:
4329 abort (); /* Should be unreachable. */
4330 }
4331}
4332
906e58ca
NC		 4333static bfd_boolean
4334arm_build_one_stub (struct bfd_hash_entry *gen_entry,
4335 void * in_arg)
4336{
7a89b94e 4337#define MAXRELOCS 3
906e58ca 4338 struct elf32_arm_stub_hash_entry *stub_entry;
4dfe6ac6 4339 struct elf32_arm_link_hash_table *globals;
906e58ca 4340 struct bfd_link_info *info;
906e58ca
NC		 4341 asection *stub_sec;
4342 bfd *stub_bfd;
906e58ca
NC		 4343 bfd_byte *loc;
4344 bfd_vma sym_value;
4345 int template_size;
4346 int size;
d3ce72d0 4347 const insn_sequence *template_sequence;
906e58ca 4348 int i;
48229727
JB		 4349 int stub_reloc_idx[MAXRELOCS] = {-1, -1};
4350 int stub_reloc_offset[MAXRELOCS] = {0, 0};
4351 int nrelocs = 0;
906e58ca
NC		 4352
4353 /* Massage our args to the form they really have. */
4354 stub_entry = (struct elf32_arm_stub_hash_entry *) gen_entry;
4355 info = (struct bfd_link_info *) in_arg;
4356
4357 globals = elf32_arm_hash_table (info);
4dfe6ac6
NC		 4358 if (globals == NULL)
4359 return FALSE;
906e58ca 4360
906e58ca
NC		 4361 stub_sec = stub_entry->stub_sec;
4362
4dfe6ac6 4363 if ((globals->fix_cortex_a8 < 0)
4563a860
JB		 4364 != (arm_stub_required_alignment (stub_entry->stub_type) == 2))
4365 /* We have to do less-strictly-aligned fixes last. */
eb7c4339 4366 return TRUE;
fe33d2fa 4367
906e58ca
NC		 4368 /* Make a note of the offset within the stubs for this entry. */
4369 stub_entry->stub_offset = stub_sec->size;
4370 loc = stub_sec->contents + stub_entry->stub_offset;
4371
4372 stub_bfd = stub_sec->owner;
4373
906e58ca
NC		 4374 /* This is the address of the stub destination. */
4375 sym_value = (stub_entry->target_value
4376 + stub_entry->target_section->output_offset
4377 + stub_entry->target_section->output_section->vma);
4378
d3ce72d0 4379 template_sequence = stub_entry->stub_template;
461a49ca 4380 template_size = stub_entry->stub_template_size;
906e58ca
NC		 4381
4382 size = 0;
461a49ca 4383 for (i = 0; i < template_size; i++)
906e58ca 4384 {
d3ce72d0 4385 switch (template_sequence[i].type)
461a49ca
DJ		 4386 {
4387 case THUMB16_TYPE:
48229727 4388 {
d3ce72d0
NC		 4389 bfd_vma data = (bfd_vma) template_sequence[i].data;
4390 if (template_sequence[i].reloc_addend != 0)
48229727 4391 {
99059e56
RM		 4392 /* We've borrowed the reloc_addend field to mean we should
4393 insert a condition code into this (Thumb-1 branch)
4394 instruction. See THUMB16_BCOND_INSN. */
4395 BFD_ASSERT ((data & 0xff00) == 0xd000);
4396 data |= ((stub_entry->orig_insn >> 22) & 0xf) << 8;
48229727 4397 }
fe33d2fa 4398 bfd_put_16 (stub_bfd, data, loc + size);
48229727
JB		 4399 size += 2;
4400 }
461a49ca 4401 break;
906e58ca 4402
48229727 4403 case THUMB32_TYPE:
fe33d2fa
CL		 4404 bfd_put_16 (stub_bfd,
4405 (template_sequence[i].data >> 16) & 0xffff,
4406 loc + size);
4407 bfd_put_16 (stub_bfd, template_sequence[i].data & 0xffff,
4408 loc + size + 2);
99059e56
RM		 4409 if (template_sequence[i].r_type != R_ARM_NONE)
4410 {
4411 stub_reloc_idx[nrelocs] = i;
4412 stub_reloc_offset[nrelocs++] = size;
4413 }
4414 size += 4;
4415 break;
48229727 4416
461a49ca 4417 case ARM_TYPE:
fe33d2fa
CL		 4418 bfd_put_32 (stub_bfd, template_sequence[i].data,
4419 loc + size);
461a49ca
DJ		 4420 /* Handle cases where the target is encoded within the
4421 instruction. */
d3ce72d0 4422 if (template_sequence[i].r_type == R_ARM_JUMP24)
461a49ca 4423 {
48229727
JB		 4424 stub_reloc_idx[nrelocs] = i;
4425 stub_reloc_offset[nrelocs++] = size;
461a49ca
DJ		 4426 }
4427 size += 4;
4428 break;
4429
4430 case DATA_TYPE:
d3ce72d0 4431 bfd_put_32 (stub_bfd, template_sequence[i].data, loc + size);
48229727
JB		 4432 stub_reloc_idx[nrelocs] = i;
4433 stub_reloc_offset[nrelocs++] = size;
461a49ca
DJ		 4434 size += 4;
4435 break;
4436
4437 default:
4438 BFD_FAIL ();
4439 return FALSE;
4440 }
906e58ca 4441 }
461a49ca 4442
906e58ca
NC		 4443 stub_sec->size += size;
4444
461a49ca
DJ		 4445 /* Stub size has already been computed in arm_size_one_stub. Check
4446 consistency. */
4447 BFD_ASSERT (size == stub_entry->stub_size);
4448
906e58ca 4449 /* Destination is Thumb. Force bit 0 to 1 to reflect this. */
35fc36a8 4450 if (stub_entry->branch_type == ST_BRANCH_TO_THUMB)
906e58ca
NC		 4451 sym_value |= 1;
4452
48229727
JB		 4453 /* Assume there is at least one and at most MAXRELOCS entries to relocate
4454 in each stub. */
4455 BFD_ASSERT (nrelocs != 0 && nrelocs <= MAXRELOCS);
c820be07 4456
48229727 4457 for (i = 0; i < nrelocs; i++)
8d9d9490
TP		 4458 {
4459 Elf_Internal_Rela rel;
4460 bfd_boolean unresolved_reloc;
4461 char *error_message;
4462 bfd_vma points_to =
4463 sym_value + template_sequence[stub_reloc_idx[i]].reloc_addend;
4464
4465 rel.r_offset = stub_entry->stub_offset + stub_reloc_offset[i];
4466 rel.r_info = ELF32_R_INFO (0,
4467 template_sequence[stub_reloc_idx[i]].r_type);
4468 rel.r_addend = 0;
4469
4470 if (stub_entry->stub_type == arm_stub_a8_veneer_b_cond && i == 0)
4471 /* The first relocation in the elf32_arm_stub_a8_veneer_b_cond[]
4472 template should refer back to the instruction after the original
4473 branch. We use target_section as Cortex-A8 erratum workaround stubs
4474 are only generated when both source and target are in the same
4475 section. */
4476 points_to = stub_entry->target_section->output_section->vma
4477 + stub_entry->target_section->output_offset
4478 + stub_entry->source_value;
4479
4480 elf32_arm_final_link_relocate (elf32_arm_howto_from_type
4481 (template_sequence[stub_reloc_idx[i]].r_type),
4482 stub_bfd, info->output_bfd, stub_sec, stub_sec->contents, &rel,
4483 points_to, info, stub_entry->target_section, "", STT_FUNC,
4484 stub_entry->branch_type,
4485 (struct elf_link_hash_entry *) stub_entry->h, &unresolved_reloc,
4486 &error_message);
4487 }
906e58ca
NC		 4488
4489 return TRUE;
48229727 4490#undef MAXRELOCS
906e58ca
NC		 4491}
4492
48229727
JB		 4493/* Calculate the template, template size and instruction size for a stub.
4494 Return value is the instruction size. */
906e58ca 4495
48229727
JB		 4496static unsigned int
4497find_stub_size_and_template (enum elf32_arm_stub_type stub_type,
4498 const insn_sequence **stub_template,
4499 int *stub_template_size)
906e58ca 4500{
d3ce72d0 4501 const insn_sequence *template_sequence = NULL;
48229727
JB		 4502 int template_size = 0, i;
4503 unsigned int size;
906e58ca 4504
d3ce72d0 4505 template_sequence = stub_definitions[stub_type].template_sequence;
2a229407
AM		 4506 if (stub_template)
4507 *stub_template = template_sequence;
4508
48229727 4509 template_size = stub_definitions[stub_type].template_size;
2a229407
AM		 4510 if (stub_template_size)
4511 *stub_template_size = template_size;
906e58ca
NC		 4512
4513 size = 0;
461a49ca
DJ		 4514 for (i = 0; i < template_size; i++)
4515 {
d3ce72d0 4516 switch (template_sequence[i].type)
461a49ca
DJ		 4517 {
4518 case THUMB16_TYPE:
4519 size += 2;
4520 break;
4521
4522 case ARM_TYPE:
48229727 4523 case THUMB32_TYPE:
461a49ca
DJ		 4524 case DATA_TYPE:
4525 size += 4;
4526 break;
4527
4528 default:
4529 BFD_FAIL ();
2a229407 4530 return 0;
461a49ca
DJ		 4531 }
4532 }
4533
48229727
JB		 4534 return size;
4535}
4536
4537/* As above, but don't actually build the stub. Just bump offset so
4538 we know stub section sizes. */
4539
4540static bfd_boolean
4541arm_size_one_stub (struct bfd_hash_entry *gen_entry,
c7e2358a 4542 void *in_arg ATTRIBUTE_UNUSED)
48229727
JB		 4543{
4544 struct elf32_arm_stub_hash_entry *stub_entry;
d3ce72d0 4545 const insn_sequence *template_sequence;
48229727
JB		 4546 int template_size, size;
4547
4548 /* Massage our args to the form they really have. */
4549 stub_entry = (struct elf32_arm_stub_hash_entry *) gen_entry;
48229727
JB		 4550
4551 BFD_ASSERT((stub_entry->stub_type > arm_stub_none)
4552 && stub_entry->stub_type < ARRAY_SIZE(stub_definitions));
4553
d3ce72d0 4554 size = find_stub_size_and_template (stub_entry->stub_type, &template_sequence,
48229727
JB		 4555 &template_size);
4556
461a49ca 4557 stub_entry->stub_size = size;
d3ce72d0 4558 stub_entry->stub_template = template_sequence;
461a49ca
DJ		 4559 stub_entry->stub_template_size = template_size;
4560
906e58ca
NC		 4561 size = (size + 7) & ~7;
4562 stub_entry->stub_sec->size += size;
461a49ca 4563
906e58ca
NC		 4564 return TRUE;
4565}
4566
4567/* External entry points for sizing and building linker stubs. */
4568
4569/* Set up various things so that we can make a list of input sections
4570 for each output section included in the link. Returns -1 on error,
4571 0 when no stubs will be needed, and 1 on success. */
4572
4573int
4574elf32_arm_setup_section_lists (bfd *output_bfd,
4575 struct bfd_link_info *info)
4576{
4577 bfd *input_bfd;
4578 unsigned int bfd_count;
7292b3ac 4579 unsigned int top_id, top_index;
906e58ca
NC		 4580 asection *section;
4581 asection **input_list, **list;
4582 bfd_size_type amt;
4583 struct elf32_arm_link_hash_table *htab = elf32_arm_hash_table (info);
4584
4dfe6ac6
NC		 4585 if (htab == NULL)
4586 return 0;
906e58ca
NC		 4587 if (! is_elf_hash_table (htab))
4588 return 0;
4589
4590 /* Count the number of input BFDs and find the top input section id. */
4591 for (input_bfd = info->input_bfds, bfd_count = 0, top_id = 0;
4592 input_bfd != NULL;
c72f2fb2 4593 input_bfd = input_bfd->link.next)
906e58ca
NC		 4594 {
4595 bfd_count += 1;
4596 for (section = input_bfd->sections;
4597 section != NULL;
4598 section = section->next)
4599 {
4600 if (top_id < section->id)
4601 top_id = section->id;
4602 }
4603 }
4604 htab->bfd_count = bfd_count;
4605
4606 amt = sizeof (struct map_stub) * (top_id + 1);
21d799b5 4607 htab->stub_group = (struct map_stub *) bfd_zmalloc (amt);
906e58ca
NC		 4608 if (htab->stub_group == NULL)
4609 return -1;
fe33d2fa 4610 htab->top_id = top_id;
906e58ca
NC		 4611
4612 /* We can't use output_bfd->section_count here to find the top output
4613 section index as some sections may have been removed, and
4614 _bfd_strip_section_from_output doesn't renumber the indices. */
4615 for (section = output_bfd->sections, top_index = 0;
4616 section != NULL;
4617 section = section->next)
4618 {
4619 if (top_index < section->index)
4620 top_index = section->index;
4621 }
4622
4623 htab->top_index = top_index;
4624 amt = sizeof (asection *) * (top_index + 1);
21d799b5 4625 input_list = (asection **) bfd_malloc (amt);
906e58ca
NC		 4626 htab->input_list = input_list;
4627 if (input_list == NULL)
4628 return -1;
4629
4630 /* For sections we aren't interested in, mark their entries with a
4631 value we can check later. */
4632 list = input_list + top_index;
4633 do
4634 *list = bfd_abs_section_ptr;
4635 while (list-- != input_list);
4636
4637 for (section = output_bfd->sections;
4638 section != NULL;
4639 section = section->next)
4640 {
4641 if ((section->flags & SEC_CODE) != 0)
4642 input_list[section->index] = NULL;
4643 }
4644
4645 return 1;
4646}
4647
4648/* The linker repeatedly calls this function for each input section,
4649 in the order that input sections are linked into output sections.
4650 Build lists of input sections to determine groupings between which
4651 we may insert linker stubs. */
4652
4653void
4654elf32_arm_next_input_section (struct bfd_link_info *info,
4655 asection *isec)
4656{
4657 struct elf32_arm_link_hash_table *htab = elf32_arm_hash_table (info);
4658
4dfe6ac6
NC		 4659 if (htab == NULL)
4660 return;
4661
906e58ca
NC		 4662 if (isec->output_section->index <= htab->top_index)
4663 {
4664 asection **list = htab->input_list + isec->output_section->index;
4665
a7470592 4666 if (*list != bfd_abs_section_ptr && (isec->flags & SEC_CODE) != 0)
906e58ca
NC		 4667 {
4668 /* Steal the link_sec pointer for our list. */
4669#define PREV_SEC(sec) (htab->stub_group[(sec)->id].link_sec)
4670 /* This happens to make the list in reverse order,
07d72278 4671 which we reverse later. */
906e58ca
NC		 4672 PREV_SEC (isec) = *list;
4673 *list = isec;
4674 }
4675 }
4676}
4677
4678/* See whether we can group stub sections together. Grouping stub
4679 sections may result in fewer stubs. More importantly, we need to
07d72278 4680 put all .init* and .fini* stubs at the end of the .init or
906e58ca
NC		 4681 .fini output sections respectively, because glibc splits the
4682 _init and _fini functions into multiple parts. Putting a stub in
4683 the middle of a function is not a good idea. */
4684
4685static void
4686group_sections (struct elf32_arm_link_hash_table *htab,
4687 bfd_size_type stub_group_size,
07d72278 4688 bfd_boolean stubs_always_after_branch)
906e58ca 4689{
07d72278 4690 asection **list = htab->input_list;
906e58ca
NC		 4691
4692 do
4693 {
4694 asection *tail = *list;
07d72278 4695 asection *head;
906e58ca
NC		 4696
4697 if (tail == bfd_abs_section_ptr)
4698 continue;
4699
07d72278
DJ		 4700 /* Reverse the list: we must avoid placing stubs at the
4701 beginning of the section because the beginning of the text
4702 section may be required for an interrupt vector in bare metal
4703 code. */
4704#define NEXT_SEC PREV_SEC
e780aef2
CL		 4705 head = NULL;
4706 while (tail != NULL)
99059e56
RM		 4707 {
4708 /* Pop from tail. */
4709 asection *item = tail;
4710 tail = PREV_SEC (item);
e780aef2 4711
99059e56
RM		 4712 /* Push on head. */
4713 NEXT_SEC (item) = head;
4714 head = item;
4715 }
07d72278
DJ		 4716
4717 while (head != NULL)
906e58ca
NC		 4718 {
4719 asection *curr;
07d72278 4720 asection *next;
e780aef2
CL		 4721 bfd_vma stub_group_start = head->output_offset;
4722 bfd_vma end_of_next;
906e58ca 4723
07d72278 4724 curr = head;
e780aef2 4725 while (NEXT_SEC (curr) != NULL)
8cd931b7 4726 {
e780aef2
CL		 4727 next = NEXT_SEC (curr);
4728 end_of_next = next->output_offset + next->size;
4729 if (end_of_next - stub_group_start >= stub_group_size)
4730 /* End of NEXT is too far from start, so stop. */
8cd931b7 4731 break;
e780aef2
CL		 4732 /* Add NEXT to the group. */
4733 curr = next;
8cd931b7 4734 }
906e58ca 4735
07d72278 4736 /* OK, the size from the start to the start of CURR is less
906e58ca 4737 than stub_group_size and thus can be handled by one stub
07d72278 4738 section. (Or the head section is itself larger than
906e58ca
NC		 4739 stub_group_size, in which case we may be toast.)
4740 We should really be keeping track of the total size of
4741 stubs added here, as stubs contribute to the final output
7fb9f789 4742 section size. */
906e58ca
NC		 4743 do
4744 {
07d72278 4745 next = NEXT_SEC (head);
906e58ca 4746 /* Set up this stub group. */
07d72278 4747 htab->stub_group[head->id].link_sec = curr;
906e58ca 4748 }
07d72278 4749 while (head != curr && (head = next) != NULL);
906e58ca
NC		 4750
4751 /* But wait, there's more! Input sections up to stub_group_size
07d72278
DJ		 4752 bytes after the stub section can be handled by it too. */
4753 if (!stubs_always_after_branch)
906e58ca 4754 {
e780aef2
CL		 4755 stub_group_start = curr->output_offset + curr->size;
4756
8cd931b7 4757 while (next != NULL)
906e58ca 4758 {
e780aef2
CL		 4759 end_of_next = next->output_offset + next->size;
4760 if (end_of_next - stub_group_start >= stub_group_size)
4761 /* End of NEXT is too far from stubs, so stop. */
8cd931b7 4762 break;
e780aef2 4763 /* Add NEXT to the stub group. */
07d72278
DJ		 4764 head = next;
4765 next = NEXT_SEC (head);
4766 htab->stub_group[head->id].link_sec = curr;
906e58ca
NC		 4767 }
4768 }
07d72278 4769 head = next;
906e58ca
NC		 4770 }
4771 }
07d72278 4772 while (list++ != htab->input_list + htab->top_index);
906e58ca
NC		 4773
4774 free (htab->input_list);
4775#undef PREV_SEC
07d72278 4776#undef NEXT_SEC
906e58ca
NC		 4777}
4778
48229727
JB		 4779/* Comparison function for sorting/searching relocations relating to Cortex-A8
4780 erratum fix. */
4781
4782static int
4783a8_reloc_compare (const void *a, const void *b)
4784{
21d799b5
NC		 4785 const struct a8_erratum_reloc *ra = (const struct a8_erratum_reloc *) a;
4786 const struct a8_erratum_reloc *rb = (const struct a8_erratum_reloc *) b;
48229727
JB		 4787
4788 if (ra->from < rb->from)
4789 return -1;
4790 else if (ra->from > rb->from)
4791 return 1;
4792 else
4793 return 0;
4794}
4795
4796static struct elf_link_hash_entry *find_thumb_glue (struct bfd_link_info *,
4797 const char *, char **);
4798
4799/* Helper function to scan code for sequences which might trigger the Cortex-A8
4800 branch/TLB erratum. Fill in the table described by A8_FIXES_P,
81694485 4801 NUM_A8_FIXES_P, A8_FIX_TABLE_SIZE_P. Returns true if an error occurs, false
48229727
JB		 4802 otherwise. */
4803
81694485
NC		 4804static bfd_boolean
4805cortex_a8_erratum_scan (bfd *input_bfd,
4806 struct bfd_link_info *info,
48229727
JB		 4807 struct a8_erratum_fix **a8_fixes_p,
4808 unsigned int *num_a8_fixes_p,
4809 unsigned int *a8_fix_table_size_p,
4810 struct a8_erratum_reloc *a8_relocs,
eb7c4339
NS		 4811 unsigned int num_a8_relocs,
4812 unsigned prev_num_a8_fixes,
4813 bfd_boolean *stub_changed_p)
48229727
JB		 4814{
4815 asection *section;
4816 struct elf32_arm_link_hash_table *htab = elf32_arm_hash_table (info);
4817 struct a8_erratum_fix *a8_fixes = *a8_fixes_p;
4818 unsigned int num_a8_fixes = *num_a8_fixes_p;
4819 unsigned int a8_fix_table_size = *a8_fix_table_size_p;
4820
4dfe6ac6
NC		 4821 if (htab == NULL)
4822 return FALSE;
4823
48229727
JB		 4824 for (section = input_bfd->sections;
4825 section != NULL;
4826 section = section->next)
4827 {
4828 bfd_byte *contents = NULL;
4829 struct _arm_elf_section_data *sec_data;
4830 unsigned int span;
4831 bfd_vma base_vma;
4832
4833 if (elf_section_type (section) != SHT_PROGBITS
99059e56
RM		 4834 || (elf_section_flags (section) & SHF_EXECINSTR) == 0
4835 || (section->flags & SEC_EXCLUDE) != 0
4836 || (section->sec_info_type == SEC_INFO_TYPE_JUST_SYMS)
4837 || (section->output_section == bfd_abs_section_ptr))
4838 continue;
48229727
JB		 4839
4840 base_vma = section->output_section->vma + section->output_offset;
4841
4842 if (elf_section_data (section)->this_hdr.contents != NULL)
99059e56 4843 contents = elf_section_data (section)->this_hdr.contents;
48229727 4844 else if (! bfd_malloc_and_get_section (input_bfd, section, &contents))
99059e56 4845 return TRUE;
48229727
JB		 4846
4847 sec_data = elf32_arm_section_data (section);
4848
4849 for (span = 0; span < sec_data->mapcount; span++)
99059e56
RM		 4850 {
4851 unsigned int span_start = sec_data->map[span].vma;
4852 unsigned int span_end = (span == sec_data->mapcount - 1)
4853 ? section->size : sec_data->map[span + 1].vma;
4854 unsigned int i;
4855 char span_type = sec_data->map[span].type;
4856 bfd_boolean last_was_32bit = FALSE, last_was_branch = FALSE;
4857
4858 if (span_type != 't')
4859 continue;
4860
4861 /* Span is entirely within a single 4KB region: skip scanning. */
4862 if (((base_vma + span_start) & ~0xfff)
48229727 4863 == ((base_vma + span_end) & ~0xfff))
99059e56
RM		 4864 continue;
4865
4866 /* Scan for 32-bit Thumb-2 branches which span two 4K regions, where:
4867
4868 * The opcode is BLX.W, BL.W, B.W, Bcc.W
4869 * The branch target is in the same 4KB region as the
4870 first half of the branch.
4871 * The instruction before the branch is a 32-bit
4872 length non-branch instruction. */
4873 for (i = span_start; i < span_end;)
4874 {
4875 unsigned int insn = bfd_getl16 (&contents[i]);
4876 bfd_boolean insn_32bit = FALSE, is_blx = FALSE, is_b = FALSE;
48229727
JB		 4877 bfd_boolean is_bl = FALSE, is_bcc = FALSE, is_32bit_branch;
4878
99059e56
RM		 4879 if ((insn & 0xe000) == 0xe000 && (insn & 0x1800) != 0x0000)
4880 insn_32bit = TRUE;
48229727
JB		 4881
4882 if (insn_32bit)
99059e56
RM		 4883 {
4884 /* Load the rest of the insn (in manual-friendly order). */
4885 insn = (insn << 16) | bfd_getl16 (&contents[i + 2]);
4886
4887 /* Encoding T4: B<c>.W. */
4888 is_b = (insn & 0xf800d000) == 0xf0009000;
4889 /* Encoding T1: BL<c>.W. */
4890 is_bl = (insn & 0xf800d000) == 0xf000d000;
4891 /* Encoding T2: BLX<c>.W. */
4892 is_blx = (insn & 0xf800d000) == 0xf000c000;
48229727
JB		 4893 /* Encoding T3: B<c>.W (not permitted in IT block). */
4894 is_bcc = (insn & 0xf800d000) == 0xf0008000
4895 && (insn & 0x07f00000) != 0x03800000;
4896 }
4897
4898 is_32bit_branch = is_b || is_bl || is_blx || is_bcc;
fe33d2fa 4899
99059e56 4900 if (((base_vma + i) & 0xfff) == 0xffe
81694485
NC		 4901 && insn_32bit
4902 && is_32bit_branch
4903 && last_was_32bit
4904 && ! last_was_branch)
99059e56
RM		 4905 {
4906 bfd_signed_vma offset = 0;
4907 bfd_boolean force_target_arm = FALSE;
48229727 4908 bfd_boolean force_target_thumb = FALSE;
99059e56
RM		 4909 bfd_vma target;
4910 enum elf32_arm_stub_type stub_type = arm_stub_none;
4911 struct a8_erratum_reloc key, *found;
4912 bfd_boolean use_plt = FALSE;
48229727 4913
99059e56
RM		 4914 key.from = base_vma + i;
4915 found = (struct a8_erratum_reloc *)
4916 bsearch (&key, a8_relocs, num_a8_relocs,
4917 sizeof (struct a8_erratum_reloc),
4918 &a8_reloc_compare);
48229727
JB		 4919
4920 if (found)
4921 {
4922 char *error_message = NULL;
4923 struct elf_link_hash_entry *entry;
4924
4925 /* We don't care about the error returned from this
99059e56 4926 function, only if there is glue or not. */
48229727
JB		 4927 entry = find_thumb_glue (info, found->sym_name,
4928 &error_message);
4929
4930 if (entry)
4931 found->non_a8_stub = TRUE;
4932
92750f34 4933 /* Keep a simpler condition, for the sake of clarity. */
362d30a1 4934 if (htab->root.splt != NULL && found->hash != NULL
92750f34
DJ		 4935 && found->hash->root.plt.offset != (bfd_vma) -1)
4936 use_plt = TRUE;
4937
4938 if (found->r_type == R_ARM_THM_CALL)
4939 {
35fc36a8
RS		 4940 if (found->branch_type == ST_BRANCH_TO_ARM
4941 || use_plt)
92750f34
DJ		 4942 force_target_arm = TRUE;
4943 else
4944 force_target_thumb = TRUE;
4945 }
48229727
JB		 4946 }
4947
99059e56 4948 /* Check if we have an offending branch instruction. */
48229727
JB		 4949
4950 if (found && found->non_a8_stub)
4951 /* We've already made a stub for this instruction, e.g.
4952 it's a long branch or a Thumb->ARM stub. Assume that
4953 stub will suffice to work around the A8 erratum (see
4954 setting of always_after_branch above). */
4955 ;
99059e56
RM		 4956 else if (is_bcc)
4957 {
4958 offset = (insn & 0x7ff) << 1;
4959 offset |= (insn & 0x3f0000) >> 4;
4960 offset |= (insn & 0x2000) ? 0x40000 : 0;
4961 offset |= (insn & 0x800) ? 0x80000 : 0;
4962 offset |= (insn & 0x4000000) ? 0x100000 : 0;
4963 if (offset & 0x100000)
4964 offset |= ~ ((bfd_signed_vma) 0xfffff);
4965 stub_type = arm_stub_a8_veneer_b_cond;
4966 }
4967 else if (is_b || is_bl || is_blx)
4968 {
4969 int s = (insn & 0x4000000) != 0;
4970 int j1 = (insn & 0x2000) != 0;
4971 int j2 = (insn & 0x800) != 0;
4972 int i1 = !(j1 ^ s);
4973 int i2 = !(j2 ^ s);
4974
4975 offset = (insn & 0x7ff) << 1;
4976 offset |= (insn & 0x3ff0000) >> 4;
4977 offset |= i2 << 22;
4978 offset |= i1 << 23;
4979 offset |= s << 24;
4980 if (offset & 0x1000000)
4981 offset |= ~ ((bfd_signed_vma) 0xffffff);
4982
4983 if (is_blx)
4984 offset &= ~ ((bfd_signed_vma) 3);
4985
4986 stub_type = is_blx ? arm_stub_a8_veneer_blx :
4987 is_bl ? arm_stub_a8_veneer_bl : arm_stub_a8_veneer_b;
4988 }
4989
4990 if (stub_type != arm_stub_none)
4991 {
4992 bfd_vma pc_for_insn = base_vma + i + 4;
48229727
JB		 4993
4994 /* The original instruction is a BL, but the target is
99059e56 4995 an ARM instruction. If we were not making a stub,
48229727
JB		 4996 the BL would have been converted to a BLX. Use the
4997 BLX stub instead in that case. */
4998 if (htab->use_blx && force_target_arm
4999 && stub_type == arm_stub_a8_veneer_bl)
5000 {
5001 stub_type = arm_stub_a8_veneer_blx;
5002 is_blx = TRUE;
5003 is_bl = FALSE;
5004 }
5005 /* Conversely, if the original instruction was
5006 BLX but the target is Thumb mode, use the BL
5007 stub. */
5008 else if (force_target_thumb
5009 && stub_type == arm_stub_a8_veneer_blx)
5010 {
5011 stub_type = arm_stub_a8_veneer_bl;
5012 is_blx = FALSE;
5013 is_bl = TRUE;
5014 }
5015
99059e56
RM		 5016 if (is_blx)
5017 pc_for_insn &= ~ ((bfd_vma) 3);
48229727 5018
99059e56
RM		 5019 /* If we found a relocation, use the proper destination,
5020 not the offset in the (unrelocated) instruction.
48229727
JB		 5021 Note this is always done if we switched the stub type
5022 above. */
99059e56
RM		 5023 if (found)
5024 offset =
81694485 5025 (bfd_signed_vma) (found->destination - pc_for_insn);
48229727 5026
99059e56
RM		 5027 /* If the stub will use a Thumb-mode branch to a
5028 PLT target, redirect it to the preceding Thumb
5029 entry point. */
5030 if (stub_type != arm_stub_a8_veneer_blx && use_plt)
5031 offset -= PLT_THUMB_STUB_SIZE;
7d24e6a6 5032
99059e56 5033 target = pc_for_insn + offset;
48229727 5034
99059e56
RM		 5035 /* The BLX stub is ARM-mode code. Adjust the offset to
5036 take the different PC value (+8 instead of +4) into
48229727 5037 account. */
99059e56
RM		 5038 if (stub_type == arm_stub_a8_veneer_blx)
5039 offset += 4;
5040
5041 if (((base_vma + i) & ~0xfff) == (target & ~0xfff))
5042 {
5043 char *stub_name = NULL;
5044
5045 if (num_a8_fixes == a8_fix_table_size)
5046 {
5047 a8_fix_table_size *= 2;
5048 a8_fixes = (struct a8_erratum_fix *)
5049 bfd_realloc (a8_fixes,
5050 sizeof (struct a8_erratum_fix)
5051 * a8_fix_table_size);
5052 }
48229727 5053
eb7c4339
NS		 5054 if (num_a8_fixes < prev_num_a8_fixes)
5055 {
5056 /* If we're doing a subsequent scan,
5057 check if we've found the same fix as
5058 before, and try and reuse the stub
5059 name. */
5060 stub_name = a8_fixes[num_a8_fixes].stub_name;
5061 if ((a8_fixes[num_a8_fixes].section != section)
5062 || (a8_fixes[num_a8_fixes].offset != i))
5063 {
5064 free (stub_name);
5065 stub_name = NULL;
5066 *stub_changed_p = TRUE;
5067 }
5068 }
5069
5070 if (!stub_name)
5071 {
21d799b5 5072 stub_name = (char *) bfd_malloc (8 + 1 + 8 + 1);
eb7c4339
NS		 5073 if (stub_name != NULL)
5074 sprintf (stub_name, "%x:%x", section->id, i);
5075 }
48229727 5076
99059e56
RM		 5077 a8_fixes[num_a8_fixes].input_bfd = input_bfd;
5078 a8_fixes[num_a8_fixes].section = section;
5079 a8_fixes[num_a8_fixes].offset = i;
8d9d9490
TP		 5080 a8_fixes[num_a8_fixes].target_offset =
5081 target - base_vma;
99059e56
RM		 5082 a8_fixes[num_a8_fixes].orig_insn = insn;
5083 a8_fixes[num_a8_fixes].stub_name = stub_name;
5084 a8_fixes[num_a8_fixes].stub_type = stub_type;
5085 a8_fixes[num_a8_fixes].branch_type =
35fc36a8 5086 is_blx ? ST_BRANCH_TO_ARM : ST_BRANCH_TO_THUMB;
48229727 5087
99059e56
RM		 5088 num_a8_fixes++;
5089 }
5090 }
5091 }
48229727 5092
99059e56
RM		 5093 i += insn_32bit ? 4 : 2;
5094 last_was_32bit = insn_32bit;
48229727 5095 last_was_branch = is_32bit_branch;
99059e56
RM		 5096 }
5097 }
48229727
JB		 5098
5099 if (elf_section_data (section)->this_hdr.contents == NULL)
99059e56 5100 free (contents);
48229727 5101 }
fe33d2fa 5102
48229727
JB		 5103 *a8_fixes_p = a8_fixes;
5104 *num_a8_fixes_p = num_a8_fixes;
5105 *a8_fix_table_size_p = a8_fix_table_size;
fe33d2fa 5106
81694485 5107 return FALSE;
48229727
JB		 5108}
5109
906e58ca
NC		 5110/* Determine and set the size of the stub section for a final link.
5111
5112 The basic idea here is to examine all the relocations looking for
5113 PC-relative calls to a target that is unreachable with a "bl"
5114 instruction. */
5115
5116bfd_boolean
5117elf32_arm_size_stubs (bfd *output_bfd,
5118 bfd *stub_bfd,
5119 struct bfd_link_info *info,
5120 bfd_signed_vma group_size,
7a89b94e
NC		 5121 asection * (*add_stub_section) (const char *, asection *,
5122 unsigned int),
906e58ca
NC		 5123 void (*layout_sections_again) (void))
5124{
5125 bfd_size_type stub_group_size;
07d72278 5126 bfd_boolean stubs_always_after_branch;
906e58ca 5127 struct elf32_arm_link_hash_table *htab = elf32_arm_hash_table (info);
48229727 5128 struct a8_erratum_fix *a8_fixes = NULL;
eb7c4339 5129 unsigned int num_a8_fixes = 0, a8_fix_table_size = 10;
48229727
JB		 5130 struct a8_erratum_reloc *a8_relocs = NULL;
5131 unsigned int num_a8_relocs = 0, a8_reloc_table_size = 10, i;
5132
4dfe6ac6
NC		 5133 if (htab == NULL)
5134 return FALSE;
5135
48229727
JB		 5136 if (htab->fix_cortex_a8)
5137 {
21d799b5 5138 a8_fixes = (struct a8_erratum_fix *)
99059e56 5139 bfd_zmalloc (sizeof (struct a8_erratum_fix) * a8_fix_table_size);
21d799b5 5140 a8_relocs = (struct a8_erratum_reloc *)
99059e56 5141 bfd_zmalloc (sizeof (struct a8_erratum_reloc) * a8_reloc_table_size);
48229727 5142 }
906e58ca
NC		 5143
5144 /* Propagate mach to stub bfd, because it may not have been
5145 finalized when we created stub_bfd. */
5146 bfd_set_arch_mach (stub_bfd, bfd_get_arch (output_bfd),
5147 bfd_get_mach (output_bfd));
5148
5149 /* Stash our params away. */
5150 htab->stub_bfd = stub_bfd;
5151 htab->add_stub_section = add_stub_section;
5152 htab->layout_sections_again = layout_sections_again;
07d72278 5153 stubs_always_after_branch = group_size < 0;
48229727
JB		 5154
5155 /* The Cortex-A8 erratum fix depends on stubs not being in the same 4K page
5156 as the first half of a 32-bit branch straddling two 4K pages. This is a
5157 crude way of enforcing that. */
5158 if (htab->fix_cortex_a8)
5159 stubs_always_after_branch = 1;
5160
906e58ca
NC		 5161 if (group_size < 0)
5162 stub_group_size = -group_size;
5163 else
5164 stub_group_size = group_size;
5165
5166 if (stub_group_size == 1)
5167 {
5168 /* Default values. */
5169 /* Thumb branch range is +-4MB has to be used as the default
5170 maximum size (a given section can contain both ARM and Thumb
5171 code, so the worst case has to be taken into account).
5172
5173 This value is 24K less than that, which allows for 2025
5174 12-byte stubs. If we exceed that, then we will fail to link.
5175 The user will have to relink with an explicit group size
5176 option. */
5177 stub_group_size = 4170000;
5178 }
5179
07d72278 5180 group_sections (htab, stub_group_size, stubs_always_after_branch);
906e58ca 5181
3ae046cc
NS		 5182 /* If we're applying the cortex A8 fix, we need to determine the
5183 program header size now, because we cannot change it later --
5184 that could alter section placements. Notice the A8 erratum fix
5185 ends up requiring the section addresses to remain unchanged
5186 modulo the page size. That's something we cannot represent
5187 inside BFD, and we don't want to force the section alignment to
5188 be the page size. */
5189 if (htab->fix_cortex_a8)
5190 (*htab->layout_sections_again) ();
5191
906e58ca
NC		 5192 while (1)
5193 {
5194 bfd *input_bfd;
5195 unsigned int bfd_indx;
5196 asection *stub_sec;
eb7c4339
NS		 5197 bfd_boolean stub_changed = FALSE;
5198 unsigned prev_num_a8_fixes = num_a8_fixes;
906e58ca 5199
48229727 5200 num_a8_fixes = 0;
906e58ca
NC		 5201 for (input_bfd = info->input_bfds, bfd_indx = 0;
5202 input_bfd != NULL;
c72f2fb2 5203 input_bfd = input_bfd->link.next, bfd_indx++)
906e58ca
NC		 5204 {
5205 Elf_Internal_Shdr *symtab_hdr;
5206 asection *section;
5207 Elf_Internal_Sym *local_syms = NULL;
5208
99059e56
RM		 5209 if (!is_arm_elf (input_bfd))
5210 continue;
adbcc655 5211
48229727
JB		 5212 num_a8_relocs = 0;
5213
906e58ca
NC		 5214 /* We'll need the symbol table in a second. */
5215 symtab_hdr = &elf_tdata (input_bfd)->symtab_hdr;
5216 if (symtab_hdr->sh_info == 0)
5217 continue;
5218
5219 /* Walk over each section attached to the input bfd. */
5220 for (section = input_bfd->sections;
5221 section != NULL;
5222 section = section->next)
5223 {
5224 Elf_Internal_Rela *internal_relocs, *irelaend, *irela;
5225
5226 /* If there aren't any relocs, then there's nothing more
5227 to do. */
5228 if ((section->flags & SEC_RELOC) == 0
5229 || section->reloc_count == 0
5230 || (section->flags & SEC_CODE) == 0)
5231 continue;
5232
5233 /* If this section is a link-once section that will be
5234 discarded, then don't create any stubs. */
5235 if (section->output_section == NULL
5236 || section->output_section->owner != output_bfd)
5237 continue;
5238
5239 /* Get the relocs. */
5240 internal_relocs
5241 = _bfd_elf_link_read_relocs (input_bfd, section, NULL,
5242 NULL, info->keep_memory);
5243 if (internal_relocs == NULL)
5244 goto error_ret_free_local;
5245
5246 /* Now examine each relocation. */
5247 irela = internal_relocs;
5248 irelaend = irela + section->reloc_count;
5249 for (; irela < irelaend; irela++)
5250 {
5251 unsigned int r_type, r_indx;
5252 enum elf32_arm_stub_type stub_type;
5253 struct elf32_arm_stub_hash_entry *stub_entry;
5254 asection *sym_sec;
5255 bfd_vma sym_value;
5256 bfd_vma destination;
5257 struct elf32_arm_link_hash_entry *hash;
7413f23f 5258 const char *sym_name;
906e58ca
NC		 5259 char *stub_name;
5260 const asection *id_sec;
34e77a92 5261 unsigned char st_type;
35fc36a8 5262 enum arm_st_branch_type branch_type;
48229727 5263 bfd_boolean created_stub = FALSE;
906e58ca
NC		 5264
5265 r_type = ELF32_R_TYPE (irela->r_info);
5266 r_indx = ELF32_R_SYM (irela->r_info);
5267
5268 if (r_type >= (unsigned int) R_ARM_max)
5269 {
5270 bfd_set_error (bfd_error_bad_value);
5271 error_ret_free_internal:
5272 if (elf_section_data (section)->relocs == NULL)
5273 free (internal_relocs);
15dd01b1
TP		 5274 /* Fall through. */
5275 error_ret_free_local:
5276 if (local_syms != NULL
5277 && (symtab_hdr->contents
5278 != (unsigned char *) local_syms))
5279 free (local_syms);
5280 return FALSE;
906e58ca 5281 }
b38cadfb 5282
0855e32b
NS		 5283 hash = NULL;
5284 if (r_indx >= symtab_hdr->sh_info)
5285 hash = elf32_arm_hash_entry
5286 (elf_sym_hashes (input_bfd)
5287 [r_indx - symtab_hdr->sh_info]);
b38cadfb 5288
0855e32b
NS		 5289 /* Only look for stubs on branch instructions, or
5290 non-relaxed TLSCALL */
906e58ca 5291 if ((r_type != (unsigned int) R_ARM_CALL)
155d87d7
CL		 5292 && (r_type != (unsigned int) R_ARM_THM_CALL)
5293 && (r_type != (unsigned int) R_ARM_JUMP24)
48229727
JB		 5294 && (r_type != (unsigned int) R_ARM_THM_JUMP19)
5295 && (r_type != (unsigned int) R_ARM_THM_XPC22)
155d87d7 5296 && (r_type != (unsigned int) R_ARM_THM_JUMP24)
0855e32b
NS		 5297 && (r_type != (unsigned int) R_ARM_PLT32)
5298 && !((r_type == (unsigned int) R_ARM_TLS_CALL
5299 || r_type == (unsigned int) R_ARM_THM_TLS_CALL)
5300 && r_type == elf32_arm_tls_transition
5301 (info, r_type, &hash->root)
5302 && ((hash ? hash->tls_type
5303 : (elf32_arm_local_got_tls_type
5304 (input_bfd)[r_indx]))
5305 & GOT_TLS_GDESC) != 0))
906e58ca
NC		 5306 continue;
5307
5308 /* Now determine the call target, its name, value,
5309 section. */
5310 sym_sec = NULL;
5311 sym_value = 0;
5312 destination = 0;
7413f23f 5313 sym_name = NULL;
b38cadfb 5314
0855e32b
NS		 5315 if (r_type == (unsigned int) R_ARM_TLS_CALL
5316 || r_type == (unsigned int) R_ARM_THM_TLS_CALL)
5317 {
5318 /* A non-relaxed TLS call. The target is the
5319 plt-resident trampoline and nothing to do
5320 with the symbol. */
5321 BFD_ASSERT (htab->tls_trampoline > 0);
5322 sym_sec = htab->root.splt;
5323 sym_value = htab->tls_trampoline;
5324 hash = 0;
34e77a92 5325 st_type = STT_FUNC;
35fc36a8 5326 branch_type = ST_BRANCH_TO_ARM;
0855e32b
NS		 5327 }
5328 else if (!hash)
906e58ca
NC		 5329 {
5330 /* It's a local symbol. */
5331 Elf_Internal_Sym *sym;
906e58ca
NC		 5332
5333 if (local_syms == NULL)
5334 {
5335 local_syms
5336 = (Elf_Internal_Sym *) symtab_hdr->contents;
5337 if (local_syms == NULL)
5338 local_syms
5339 = bfd_elf_get_elf_syms (input_bfd, symtab_hdr,
5340 symtab_hdr->sh_info, 0,
5341 NULL, NULL, NULL);
5342 if (local_syms == NULL)
5343 goto error_ret_free_internal;
5344 }
5345
5346 sym = local_syms + r_indx;
f6d250ce
TS		 5347 if (sym->st_shndx == SHN_UNDEF)
5348 sym_sec = bfd_und_section_ptr;
5349 else if (sym->st_shndx == SHN_ABS)
5350 sym_sec = bfd_abs_section_ptr;
5351 else if (sym->st_shndx == SHN_COMMON)
5352 sym_sec = bfd_com_section_ptr;
5353 else
5354 sym_sec =
5355 bfd_section_from_elf_index (input_bfd, sym->st_shndx);
5356
ffcb4889
NS		 5357 if (!sym_sec)
5358 /* This is an undefined symbol. It can never
6a631e86 5359 be resolved. */
ffcb4889 5360 continue;
fe33d2fa 5361
906e58ca
NC		 5362 if (ELF_ST_TYPE (sym->st_info) != STT_SECTION)
5363 sym_value = sym->st_value;
5364 destination = (sym_value + irela->r_addend
5365 + sym_sec->output_offset
5366 + sym_sec->output_section->vma);
34e77a92 5367 st_type = ELF_ST_TYPE (sym->st_info);
35fc36a8 5368 branch_type = ARM_SYM_BRANCH_TYPE (sym);
7413f23f
DJ		 5369 sym_name
5370 = bfd_elf_string_from_elf_section (input_bfd,
5371 symtab_hdr->sh_link,
5372 sym->st_name);
906e58ca
NC		 5373 }
5374 else
5375 {
5376 /* It's an external symbol. */
906e58ca
NC		 5377 while (hash->root.root.type == bfd_link_hash_indirect
5378 || hash->root.root.type == bfd_link_hash_warning)
5379 hash = ((struct elf32_arm_link_hash_entry *)
5380 hash->root.root.u.i.link);
5381
5382 if (hash->root.root.type == bfd_link_hash_defined
5383 || hash->root.root.type == bfd_link_hash_defweak)
5384 {
5385 sym_sec = hash->root.root.u.def.section;
5386 sym_value = hash->root.root.u.def.value;
022f8312
CL		 5387
5388 struct elf32_arm_link_hash_table *globals =
5389 elf32_arm_hash_table (info);
5390
5391 /* For a destination in a shared library,
5392 use the PLT stub as target address to
5393 decide whether a branch stub is
5394 needed. */
4dfe6ac6 5395 if (globals != NULL
362d30a1 5396 && globals->root.splt != NULL
4dfe6ac6 5397 && hash != NULL
022f8312
CL		 5398 && hash->root.plt.offset != (bfd_vma) -1)
5399 {
362d30a1 5400 sym_sec = globals->root.splt;
022f8312
CL		 5401 sym_value = hash->root.plt.offset;
5402 if (sym_sec->output_section != NULL)
5403 destination = (sym_value
5404 + sym_sec->output_offset
5405 + sym_sec->output_section->vma);
5406 }
5407 else if (sym_sec->output_section != NULL)
906e58ca
NC		 5408 destination = (sym_value + irela->r_addend
5409 + sym_sec->output_offset
5410 + sym_sec->output_section->vma);
5411 }
69c5861e
CL		 5412 else if ((hash->root.root.type == bfd_link_hash_undefined)
5413 || (hash->root.root.type == bfd_link_hash_undefweak))
5414 {
5415 /* For a shared library, use the PLT stub as
5416 target address to decide whether a long
5417 branch stub is needed.
5418 For absolute code, they cannot be handled. */
5419 struct elf32_arm_link_hash_table *globals =
5420 elf32_arm_hash_table (info);
5421
4dfe6ac6 5422 if (globals != NULL
362d30a1 5423 && globals->root.splt != NULL
4dfe6ac6 5424 && hash != NULL
69c5861e
CL		 5425 && hash->root.plt.offset != (bfd_vma) -1)
5426 {
362d30a1 5427 sym_sec = globals->root.splt;
69c5861e
CL		 5428 sym_value = hash->root.plt.offset;
5429 if (sym_sec->output_section != NULL)
5430 destination = (sym_value
5431 + sym_sec->output_offset
5432 + sym_sec->output_section->vma);
5433 }
5434 else
5435 continue;
5436 }
906e58ca
NC		 5437 else
5438 {
5439 bfd_set_error (bfd_error_bad_value);
5440 goto error_ret_free_internal;
5441 }
34e77a92 5442 st_type = hash->root.type;
35fc36a8 5443 branch_type = hash->root.target_internal;
7413f23f 5444 sym_name = hash->root.root.root.string;
906e58ca
NC		 5445 }
5446
48229727 5447 do
7413f23f 5448 {
48229727
JB		 5449 /* Determine what (if any) linker stub is needed. */
5450 stub_type = arm_type_of_stub (info, section, irela,
34e77a92
RS		 5451 st_type, &branch_type,
5452 hash, destination, sym_sec,
48229727
JB		 5453 input_bfd, sym_name);
5454 if (stub_type == arm_stub_none)
5455 break;
5456
5457 /* Support for grouping stub sections. */
5458 id_sec = htab->stub_group[section->id].link_sec;
5459
5460 /* Get the name of this stub. */
5461 stub_name = elf32_arm_stub_name (id_sec, sym_sec, hash,
fe33d2fa 5462 irela, stub_type);
48229727
JB		 5463 if (!stub_name)
5464 goto error_ret_free_internal;
5465
5466 /* We've either created a stub for this reloc already,
5467 or we are about to. */
5468 created_stub = TRUE;
5469
5470 stub_entry = arm_stub_hash_lookup
5471 (&htab->stub_hash_table, stub_name,
5472 FALSE, FALSE);
5473 if (stub_entry != NULL)
5474 {
5475 /* The proper stub has already been created. */
5476 free (stub_name);
eb7c4339 5477 stub_entry->target_value = sym_value;
48229727
JB		 5478 break;
5479 }
7413f23f 5480
48229727
JB		 5481 stub_entry = elf32_arm_add_stub (stub_name, section,
5482 htab);
5483 if (stub_entry == NULL)
5484 {
5485 free (stub_name);
5486 goto error_ret_free_internal;
5487 }
7413f23f 5488
99059e56
RM		 5489 stub_entry->target_value = sym_value;
5490 stub_entry->target_section = sym_sec;
5491 stub_entry->stub_type = stub_type;
5492 stub_entry->h = hash;
5493 stub_entry->branch_type = branch_type;
5494
5495 if (sym_name == NULL)
5496 sym_name = "unnamed";
5497 stub_entry->output_name = (char *)
5498 bfd_alloc (htab->stub_bfd,
5499 sizeof (THUMB2ARM_GLUE_ENTRY_NAME)
5500 + strlen (sym_name));
5501 if (stub_entry->output_name == NULL)
5502 {
5503 free (stub_name);
5504 goto error_ret_free_internal;
5505 }
5506
5507 /* For historical reasons, use the existing names for
5508 ARM-to-Thumb and Thumb-to-ARM stubs. */
5509 if ((r_type == (unsigned int) R_ARM_THM_CALL
c5423981
TG		 5510 || r_type == (unsigned int) R_ARM_THM_JUMP24
5511 || r_type == (unsigned int) R_ARM_THM_JUMP19)
35fc36a8 5512 && branch_type == ST_BRANCH_TO_ARM)
99059e56
RM		 5513 sprintf (stub_entry->output_name,
5514 THUMB2ARM_GLUE_ENTRY_NAME, sym_name);
5515 else if ((r_type == (unsigned int) R_ARM_CALL
35fc36a8
RS		 5516 || r_type == (unsigned int) R_ARM_JUMP24)
5517 && branch_type == ST_BRANCH_TO_THUMB)
99059e56
RM		 5518 sprintf (stub_entry->output_name,
5519 ARM2THUMB_GLUE_ENTRY_NAME, sym_name);
5520 else
5521 sprintf (stub_entry->output_name, STUB_ENTRY_NAME,
5522 sym_name);
5523
5524 stub_changed = TRUE;
5525 }
5526 while (0);
5527
5528 /* Look for relocations which might trigger Cortex-A8
5529 erratum. */
5530 if (htab->fix_cortex_a8
5531 && (r_type == (unsigned int) R_ARM_THM_JUMP24
5532 || r_type == (unsigned int) R_ARM_THM_JUMP19
5533 || r_type == (unsigned int) R_ARM_THM_CALL
5534 || r_type == (unsigned int) R_ARM_THM_XPC22))
5535 {
5536 bfd_vma from = section->output_section->vma
5537 + section->output_offset
5538 + irela->r_offset;
5539
5540 if ((from & 0xfff) == 0xffe)
5541 {
5542 /* Found a candidate. Note we haven't checked the
5543 destination is within 4K here: if we do so (and
5544 don't create an entry in a8_relocs) we can't tell
5545 that a branch should have been relocated when
5546 scanning later. */
5547 if (num_a8_relocs == a8_reloc_table_size)
5548 {
5549 a8_reloc_table_size *= 2;
5550 a8_relocs = (struct a8_erratum_reloc *)
5551 bfd_realloc (a8_relocs,
5552 sizeof (struct a8_erratum_reloc)
5553 * a8_reloc_table_size);
5554 }
5555
5556 a8_relocs[num_a8_relocs].from = from;
5557 a8_relocs[num_a8_relocs].destination = destination;
5558 a8_relocs[num_a8_relocs].r_type = r_type;
5559 a8_relocs[num_a8_relocs].branch_type = branch_type;
5560 a8_relocs[num_a8_relocs].sym_name = sym_name;
5561 a8_relocs[num_a8_relocs].non_a8_stub = created_stub;
5562 a8_relocs[num_a8_relocs].hash = hash;
5563
5564 num_a8_relocs++;
5565 }
5566 }
906e58ca
NC		 5567 }
5568
99059e56
RM		 5569 /* We're done with the internal relocs, free them. */
5570 if (elf_section_data (section)->relocs == NULL)
5571 free (internal_relocs);
5572 }
48229727 5573
99059e56 5574 if (htab->fix_cortex_a8)
48229727 5575 {
99059e56
RM		 5576 /* Sort relocs which might apply to Cortex-A8 erratum. */
5577 qsort (a8_relocs, num_a8_relocs,
eb7c4339 5578 sizeof (struct a8_erratum_reloc),
99059e56 5579 &a8_reloc_compare);
48229727 5580
99059e56
RM		 5581 /* Scan for branches which might trigger Cortex-A8 erratum. */
5582 if (cortex_a8_erratum_scan (input_bfd, info, &a8_fixes,
48229727 5583 &num_a8_fixes, &a8_fix_table_size,
eb7c4339
NS		 5584 a8_relocs, num_a8_relocs,
5585 prev_num_a8_fixes, &stub_changed)
5586 != 0)
48229727 5587 goto error_ret_free_local;
5e681ec4 5588 }
5e681ec4
PB		 5589 }
5590
eb7c4339 5591 if (prev_num_a8_fixes != num_a8_fixes)
99059e56 5592 stub_changed = TRUE;
48229727 5593
906e58ca
NC		 5594 if (!stub_changed)
5595 break;
5e681ec4 5596
906e58ca
NC		 5597 /* OK, we've added some stubs. Find out the new size of the
5598 stub sections. */
5599 for (stub_sec = htab->stub_bfd->sections;
5600 stub_sec != NULL;
5601 stub_sec = stub_sec->next)
3e6b1042
DJ		 5602 {
5603 /* Ignore non-stub sections. */
5604 if (!strstr (stub_sec->name, STUB_SUFFIX))
5605 continue;
5606
5607 stub_sec->size = 0;
5608 }
b34b2d70 5609
906e58ca
NC		 5610 bfd_hash_traverse (&htab->stub_hash_table, arm_size_one_stub, htab);
5611
48229727
JB		 5612 /* Add Cortex-A8 erratum veneers to stub section sizes too. */
5613 if (htab->fix_cortex_a8)
99059e56
RM		 5614 for (i = 0; i < num_a8_fixes; i++)
5615 {
48229727
JB		 5616 stub_sec = elf32_arm_create_or_find_stub_sec (NULL,
5617 a8_fixes[i].section, htab);
5618
5619 if (stub_sec == NULL)
5620 goto error_ret_free_local;
5621
99059e56
RM		 5622 stub_sec->size
5623 += find_stub_size_and_template (a8_fixes[i].stub_type, NULL,
5624 NULL);
5625 }
48229727
JB		 5626
5627
906e58ca
NC		 5628 /* Ask the linker to do its stuff. */
5629 (*htab->layout_sections_again) ();
ba93b8ac
DJ		 5630 }
5631
48229727
JB		 5632 /* Add stubs for Cortex-A8 erratum fixes now. */
5633 if (htab->fix_cortex_a8)
5634 {
5635 for (i = 0; i < num_a8_fixes; i++)
99059e56
RM		 5636 {
5637 struct elf32_arm_stub_hash_entry *stub_entry;
5638 char *stub_name = a8_fixes[i].stub_name;
5639 asection *section = a8_fixes[i].section;
5640 unsigned int section_id = a8_fixes[i].section->id;
5641 asection *link_sec = htab->stub_group[section_id].link_sec;
5642 asection *stub_sec = htab->stub_group[section_id].stub_sec;
5643 const insn_sequence *template_sequence;
5644 int template_size, size = 0;
5645
5646 stub_entry = arm_stub_hash_lookup (&htab->stub_hash_table, stub_name,
5647 TRUE, FALSE);
5648 if (stub_entry == NULL)
5649 {
5650 (*_bfd_error_handler) (_("%s: cannot create stub entry %s"),
5651 section->owner,
5652 stub_name);
5653 return FALSE;
5654 }
5655
5656 stub_entry->stub_sec = stub_sec;
5657 stub_entry->stub_offset = 0;
5658 stub_entry->id_sec = link_sec;
5659 stub_entry->stub_type = a8_fixes[i].stub_type;
8d9d9490 5660 stub_entry->source_value = a8_fixes[i].offset;
99059e56 5661 stub_entry->target_section = a8_fixes[i].section;
8d9d9490 5662 stub_entry->target_value = a8_fixes[i].target_offset;
99059e56 5663 stub_entry->orig_insn = a8_fixes[i].orig_insn;
35fc36a8 5664 stub_entry->branch_type = a8_fixes[i].branch_type;
48229727 5665
99059e56
RM		 5666 size = find_stub_size_and_template (a8_fixes[i].stub_type,
5667 &template_sequence,
5668 &template_size);
48229727 5669
99059e56
RM		 5670 stub_entry->stub_size = size;
5671 stub_entry->stub_template = template_sequence;
5672 stub_entry->stub_template_size = template_size;
5673 }
48229727
JB		 5674
5675 /* Stash the Cortex-A8 erratum fix array for use later in
99059e56 5676 elf32_arm_write_section(). */
48229727
JB		 5677 htab->a8_erratum_fixes = a8_fixes;
5678 htab->num_a8_erratum_fixes = num_a8_fixes;
5679 }
5680 else
5681 {
5682 htab->a8_erratum_fixes = NULL;
5683 htab->num_a8_erratum_fixes = 0;
5684 }
906e58ca 5685 return TRUE;
5e681ec4
PB		 5686}
5687
906e58ca
NC		 5688/* Build all the stubs associated with the current output file. The
5689 stubs are kept in a hash table attached to the main linker hash
5690 table. We also set up the .plt entries for statically linked PIC
5691 functions here. This function is called via arm_elf_finish in the
5692 linker. */
252b5132 5693
906e58ca
NC		 5694bfd_boolean
5695elf32_arm_build_stubs (struct bfd_link_info *info)
252b5132 5696{
906e58ca
NC		 5697 asection *stub_sec;
5698 struct bfd_hash_table *table;
5699 struct elf32_arm_link_hash_table *htab;
252b5132 5700
906e58ca 5701 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 5702 if (htab == NULL)
5703 return FALSE;
252b5132 5704
906e58ca
NC		 5705 for (stub_sec = htab->stub_bfd->sections;
5706 stub_sec != NULL;
5707 stub_sec = stub_sec->next)
252b5132 5708 {
906e58ca
NC		 5709 bfd_size_type size;
5710
8029a119 5711 /* Ignore non-stub sections. */
906e58ca
NC		 5712 if (!strstr (stub_sec->name, STUB_SUFFIX))
5713 continue;
5714
5715 /* Allocate memory to hold the linker stubs. */
5716 size = stub_sec->size;
21d799b5 5717 stub_sec->contents = (unsigned char *) bfd_zalloc (htab->stub_bfd, size);
906e58ca
NC		 5718 if (stub_sec->contents == NULL && size != 0)
5719 return FALSE;
5720 stub_sec->size = 0;
252b5132
RH		 5721 }
5722
906e58ca
NC		 5723 /* Build the stubs as directed by the stub hash table. */
5724 table = &htab->stub_hash_table;
5725 bfd_hash_traverse (table, arm_build_one_stub, info);
eb7c4339
NS		 5726 if (htab->fix_cortex_a8)
5727 {
5728 /* Place the cortex a8 stubs last. */
5729 htab->fix_cortex_a8 = -1;
5730 bfd_hash_traverse (table, arm_build_one_stub, info);
5731 }
252b5132 5732
906e58ca 5733 return TRUE;
252b5132
RH		 5734}
5735
9b485d32
NC		 5736/* Locate the Thumb encoded calling stub for NAME. */
5737
252b5132 5738static struct elf_link_hash_entry *
57e8b36a
NC		 5739find_thumb_glue (struct bfd_link_info *link_info,
5740 const char *name,
f2a9dd69 5741 char **error_message)
252b5132
RH		 5742{
5743 char *tmp_name;
5744 struct elf_link_hash_entry *hash;
5745 struct elf32_arm_link_hash_table *hash_table;
5746
5747 /* We need a pointer to the armelf specific hash table. */
5748 hash_table = elf32_arm_hash_table (link_info);
4dfe6ac6
NC		 5749 if (hash_table == NULL)
5750 return NULL;
252b5132 5751
21d799b5 5752 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen (name)
99059e56 5753 + strlen (THUMB2ARM_GLUE_ENTRY_NAME) + 1);
252b5132
RH		 5754
5755 BFD_ASSERT (tmp_name);
5756
5757 sprintf (tmp_name, THUMB2ARM_GLUE_ENTRY_NAME, name);
5758
5759 hash = elf_link_hash_lookup
b34976b6 5760 (&(hash_table)->root, tmp_name, FALSE, FALSE, TRUE);
252b5132 5761
b1657152
AM		 5762 if (hash == NULL
5763 && asprintf (error_message, _("unable to find THUMB glue '%s' for '%s'"),
5764 tmp_name, name) == -1)
5765 *error_message = (char *) bfd_errmsg (bfd_error_system_call);
252b5132
RH		 5766
5767 free (tmp_name);
5768
5769 return hash;
5770}
5771
9b485d32
NC		 5772/* Locate the ARM encoded calling stub for NAME. */
5773
252b5132 5774static struct elf_link_hash_entry *
57e8b36a
NC		 5775find_arm_glue (struct bfd_link_info *link_info,
5776 const char *name,
f2a9dd69 5777 char **error_message)
252b5132
RH		 5778{
5779 char *tmp_name;
5780 struct elf_link_hash_entry *myh;
5781 struct elf32_arm_link_hash_table *hash_table;
5782
5783 /* We need a pointer to the elfarm specific hash table. */
5784 hash_table = elf32_arm_hash_table (link_info);
4dfe6ac6
NC		 5785 if (hash_table == NULL)
5786 return NULL;
252b5132 5787
21d799b5 5788 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen (name)
99059e56 5789 + strlen (ARM2THUMB_GLUE_ENTRY_NAME) + 1);
252b5132
RH		 5790
5791 BFD_ASSERT (tmp_name);
5792
5793 sprintf (tmp_name, ARM2THUMB_GLUE_ENTRY_NAME, name);
5794
5795 myh = elf_link_hash_lookup
b34976b6 5796 (&(hash_table)->root, tmp_name, FALSE, FALSE, TRUE);
252b5132 5797
b1657152
AM		 5798 if (myh == NULL
5799 && asprintf (error_message, _("unable to find ARM glue '%s' for '%s'"),
5800 tmp_name, name) == -1)
5801 *error_message = (char *) bfd_errmsg (bfd_error_system_call);
252b5132
RH		 5802
5803 free (tmp_name);
5804
5805 return myh;
5806}
5807
8f6277f5 5808/* ARM->Thumb glue (static images):
252b5132
RH		 5809
5810 .arm
5811 __func_from_arm:
5812 ldr r12, __func_addr
5813 bx r12
5814 __func_addr:
906e58ca 5815 .word func @ behave as if you saw a ARM_32 reloc.
252b5132 5816
26079076
PB		 5817 (v5t static images)
5818 .arm
5819 __func_from_arm:
5820 ldr pc, __func_addr
5821 __func_addr:
906e58ca 5822 .word func @ behave as if you saw a ARM_32 reloc.
26079076 5823
8f6277f5
PB		 5824 (relocatable images)
5825 .arm
5826 __func_from_arm:
5827 ldr r12, __func_offset
5828 add r12, r12, pc
5829 bx r12
5830 __func_offset:
8029a119 5831 .word func - . */
8f6277f5
PB		 5832
5833#define ARM2THUMB_STATIC_GLUE_SIZE 12
252b5132
RH		 5834static const insn32 a2t1_ldr_insn = 0xe59fc000;
5835static const insn32 a2t2_bx_r12_insn = 0xe12fff1c;
5836static const insn32 a2t3_func_addr_insn = 0x00000001;
5837
26079076
PB		 5838#define ARM2THUMB_V5_STATIC_GLUE_SIZE 8
5839static const insn32 a2t1v5_ldr_insn = 0xe51ff004;
5840static const insn32 a2t2v5_func_addr_insn = 0x00000001;
5841
8f6277f5
PB		 5842#define ARM2THUMB_PIC_GLUE_SIZE 16
5843static const insn32 a2t1p_ldr_insn = 0xe59fc004;
5844static const insn32 a2t2p_add_pc_insn = 0xe08cc00f;
5845static const insn32 a2t3p_bx_r12_insn = 0xe12fff1c;
5846
9b485d32 5847/* Thumb->ARM: Thumb->(non-interworking aware) ARM
252b5132 5848
8029a119
NC		 5849 .thumb .thumb
5850 .align 2 .align 2
5851 __func_from_thumb: __func_from_thumb:
5852 bx pc push {r6, lr}
5853 nop ldr r6, __func_addr
5854 .arm mov lr, pc
5855 b func bx r6
99059e56
RM		 5856 .arm
5857 ;; back_to_thumb
5858 ldmia r13! {r6, lr}
5859 bx lr
5860 __func_addr:
5861 .word func */
252b5132
RH		 5862
5863#define THUMB2ARM_GLUE_SIZE 8
5864static const insn16 t2a1_bx_pc_insn = 0x4778;
5865static const insn16 t2a2_noop_insn = 0x46c0;
5866static const insn32 t2a3_b_insn = 0xea000000;
5867
c7b8f16e 5868#define VFP11_ERRATUM_VENEER_SIZE 8
a504d23a
LA		 5869#define STM32L4XX_ERRATUM_LDM_VENEER_SIZE 16
5870#define STM32L4XX_ERRATUM_VLDM_VENEER_SIZE 24
c7b8f16e 5871
845b51d6
PB		 5872#define ARM_BX_VENEER_SIZE 12
5873static const insn32 armbx1_tst_insn = 0xe3100001;
5874static const insn32 armbx2_moveq_insn = 0x01a0f000;
5875static const insn32 armbx3_bx_insn = 0xe12fff10;
5876
7e392df6 5877#ifndef ELFARM_NABI_C_INCLUDED
8029a119
NC		 5878static void
5879arm_allocate_glue_section_space (bfd * abfd, bfd_size_type size, const char * name)
252b5132
RH		 5880{
5881 asection * s;
8029a119 5882 bfd_byte * contents;
252b5132 5883
8029a119 5884 if (size == 0)
3e6b1042
DJ		 5885 {
5886 /* Do not include empty glue sections in the output. */
5887 if (abfd != NULL)
5888 {
3d4d4302 5889 s = bfd_get_linker_section (abfd, name);
3e6b1042
DJ		 5890 if (s != NULL)
5891 s->flags |= SEC_EXCLUDE;
5892 }
5893 return;
5894 }
252b5132 5895
8029a119 5896 BFD_ASSERT (abfd != NULL);
252b5132 5897
3d4d4302 5898 s = bfd_get_linker_section (abfd, name);
8029a119 5899 BFD_ASSERT (s != NULL);
252b5132 5900
21d799b5 5901 contents = (bfd_byte *) bfd_alloc (abfd, size);
252b5132 5902
8029a119
NC		 5903 BFD_ASSERT (s->size == size);
5904 s->contents = contents;
5905}
906e58ca 5906
8029a119
NC		 5907bfd_boolean
5908bfd_elf32_arm_allocate_interworking_sections (struct bfd_link_info * info)
5909{
5910 struct elf32_arm_link_hash_table * globals;
906e58ca 5911
8029a119
NC		 5912 globals = elf32_arm_hash_table (info);
5913 BFD_ASSERT (globals != NULL);
906e58ca 5914
8029a119
NC		 5915 arm_allocate_glue_section_space (globals->bfd_of_glue_owner,
5916 globals->arm_glue_size,
5917 ARM2THUMB_GLUE_SECTION_NAME);
906e58ca 5918
8029a119
NC		 5919 arm_allocate_glue_section_space (globals->bfd_of_glue_owner,
5920 globals->thumb_glue_size,
5921 THUMB2ARM_GLUE_SECTION_NAME);
252b5132 5922
8029a119
NC		 5923 arm_allocate_glue_section_space (globals->bfd_of_glue_owner,
5924 globals->vfp11_erratum_glue_size,
5925 VFP11_ERRATUM_VENEER_SECTION_NAME);
845b51d6 5926
a504d23a
LA		 5927 arm_allocate_glue_section_space (globals->bfd_of_glue_owner,
5928 globals->stm32l4xx_erratum_glue_size,
5929 STM32L4XX_ERRATUM_VENEER_SECTION_NAME);
5930
8029a119
NC		 5931 arm_allocate_glue_section_space (globals->bfd_of_glue_owner,
5932 globals->bx_glue_size,
845b51d6
PB		 5933 ARM_BX_GLUE_SECTION_NAME);
5934
b34976b6 5935 return TRUE;
252b5132
RH		 5936}
5937
a4fd1a8e 5938/* Allocate space and symbols for calling a Thumb function from Arm mode.
906e58ca
NC		 5939 returns the symbol identifying the stub. */
5940
a4fd1a8e 5941static struct elf_link_hash_entry *
57e8b36a
NC		 5942record_arm_to_thumb_glue (struct bfd_link_info * link_info,
5943 struct elf_link_hash_entry * h)
252b5132
RH		 5944{
5945 const char * name = h->root.root.string;
63b0f745 5946 asection * s;
252b5132
RH		 5947 char * tmp_name;
5948 struct elf_link_hash_entry * myh;
14a793b2 5949 struct bfd_link_hash_entry * bh;
252b5132 5950 struct elf32_arm_link_hash_table * globals;
dc810e39 5951 bfd_vma val;
2f475487 5952 bfd_size_type size;
252b5132
RH		 5953
5954 globals = elf32_arm_hash_table (link_info);
252b5132
RH		 5955 BFD_ASSERT (globals != NULL);
5956 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
5957
3d4d4302 5958 s = bfd_get_linker_section
252b5132
RH		 5959 (globals->bfd_of_glue_owner, ARM2THUMB_GLUE_SECTION_NAME);
5960
252b5132
RH		 5961 BFD_ASSERT (s != NULL);
5962
21d799b5 5963 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen (name)
99059e56 5964 + strlen (ARM2THUMB_GLUE_ENTRY_NAME) + 1);
252b5132
RH		 5965
5966 BFD_ASSERT (tmp_name);
5967
5968 sprintf (tmp_name, ARM2THUMB_GLUE_ENTRY_NAME, name);
5969
5970 myh = elf_link_hash_lookup
b34976b6 5971 (&(globals)->root, tmp_name, FALSE, FALSE, TRUE);
252b5132
RH		 5972
5973 if (myh != NULL)
5974 {
9b485d32 5975 /* We've already seen this guy. */
252b5132 5976 free (tmp_name);
a4fd1a8e 5977 return myh;
252b5132
RH		 5978 }
5979
57e8b36a
NC		 5980 /* The only trick here is using hash_table->arm_glue_size as the value.
5981 Even though the section isn't allocated yet, this is where we will be
3dccd7b7
DJ		 5982 putting it. The +1 on the value marks that the stub has not been
5983 output yet - not that it is a Thumb function. */
14a793b2 5984 bh = NULL;
dc810e39
AM		 5985 val = globals->arm_glue_size + 1;
5986 _bfd_generic_link_add_one_symbol (link_info, globals->bfd_of_glue_owner,
5987 tmp_name, BSF_GLOBAL, s, val,
b34976b6 5988 NULL, TRUE, FALSE, &bh);
252b5132 5989
b7693d02
DJ		 5990 myh = (struct elf_link_hash_entry *) bh;
5991 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
5992 myh->forced_local = 1;
5993
252b5132
RH		 5994 free (tmp_name);
5995
0e1862bb
L		 5996 if (bfd_link_pic (link_info)
5997 || globals->root.is_relocatable_executable
27e55c4d 5998 || globals->pic_veneer)
2f475487 5999 size = ARM2THUMB_PIC_GLUE_SIZE;
26079076
PB		 6000 else if (globals->use_blx)
6001 size = ARM2THUMB_V5_STATIC_GLUE_SIZE;
8f6277f5 6002 else
2f475487
AM		 6003 size = ARM2THUMB_STATIC_GLUE_SIZE;
6004
6005 s->size += size;
6006 globals->arm_glue_size += size;
252b5132 6007
a4fd1a8e 6008 return myh;
252b5132
RH		 6009}
6010
845b51d6
PB		 6011/* Allocate space for ARMv4 BX veneers. */
6012
6013static void
6014record_arm_bx_glue (struct bfd_link_info * link_info, int reg)
6015{
6016 asection * s;
6017 struct elf32_arm_link_hash_table *globals;
6018 char *tmp_name;
6019 struct elf_link_hash_entry *myh;
6020 struct bfd_link_hash_entry *bh;
6021 bfd_vma val;
6022
6023 /* BX PC does not need a veneer. */
6024 if (reg == 15)
6025 return;
6026
6027 globals = elf32_arm_hash_table (link_info);
845b51d6
PB		 6028 BFD_ASSERT (globals != NULL);
6029 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
6030
6031 /* Check if this veneer has already been allocated. */
6032 if (globals->bx_glue_offset[reg])
6033 return;
6034
3d4d4302 6035 s = bfd_get_linker_section
845b51d6
PB		 6036 (globals->bfd_of_glue_owner, ARM_BX_GLUE_SECTION_NAME);
6037
6038 BFD_ASSERT (s != NULL);
6039
6040 /* Add symbol for veneer. */
21d799b5
NC		 6041 tmp_name = (char *)
6042 bfd_malloc ((bfd_size_type) strlen (ARM_BX_GLUE_ENTRY_NAME) + 1);
906e58ca 6043
845b51d6 6044 BFD_ASSERT (tmp_name);
906e58ca 6045
845b51d6 6046 sprintf (tmp_name, ARM_BX_GLUE_ENTRY_NAME, reg);
906e58ca 6047
845b51d6
PB		 6048 myh = elf_link_hash_lookup
6049 (&(globals)->root, tmp_name, FALSE, FALSE, FALSE);
906e58ca 6050
845b51d6 6051 BFD_ASSERT (myh == NULL);
906e58ca 6052
845b51d6
PB		 6053 bh = NULL;
6054 val = globals->bx_glue_size;
6055 _bfd_generic_link_add_one_symbol (link_info, globals->bfd_of_glue_owner,
99059e56
RM		 6056 tmp_name, BSF_FUNCTION | BSF_LOCAL, s, val,
6057 NULL, TRUE, FALSE, &bh);
845b51d6
PB		 6058
6059 myh = (struct elf_link_hash_entry *) bh;
6060 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
6061 myh->forced_local = 1;
6062
6063 s->size += ARM_BX_VENEER_SIZE;
6064 globals->bx_glue_offset[reg] = globals->bx_glue_size | 2;
6065 globals->bx_glue_size += ARM_BX_VENEER_SIZE;
6066}
6067
6068
c7b8f16e
JB		 6069/* Add an entry to the code/data map for section SEC. */
6070
6071static void
6072elf32_arm_section_map_add (asection *sec, char type, bfd_vma vma)
6073{
6074 struct _arm_elf_section_data *sec_data = elf32_arm_section_data (sec);
6075 unsigned int newidx;
906e58ca 6076
c7b8f16e
JB		 6077 if (sec_data->map == NULL)
6078 {
21d799b5 6079 sec_data->map = (elf32_arm_section_map *)
99059e56 6080 bfd_malloc (sizeof (elf32_arm_section_map));
c7b8f16e
JB		 6081 sec_data->mapcount = 0;
6082 sec_data->mapsize = 1;
6083 }
906e58ca 6084
c7b8f16e 6085 newidx = sec_data->mapcount++;
906e58ca 6086
c7b8f16e
JB		 6087 if (sec_data->mapcount > sec_data->mapsize)
6088 {
6089 sec_data->mapsize *= 2;
21d799b5 6090 sec_data->map = (elf32_arm_section_map *)
99059e56
RM		 6091 bfd_realloc_or_free (sec_data->map, sec_data->mapsize
6092 * sizeof (elf32_arm_section_map));
515ef31d
NC		 6093 }
6094
6095 if (sec_data->map)
6096 {
6097 sec_data->map[newidx].vma = vma;
6098 sec_data->map[newidx].type = type;
c7b8f16e 6099 }
c7b8f16e
JB		 6100}
6101
6102
6103/* Record information about a VFP11 denorm-erratum veneer. Only ARM-mode
6104 veneers are handled for now. */
6105
6106static bfd_vma
6107record_vfp11_erratum_veneer (struct bfd_link_info *link_info,
99059e56
RM		 6108 elf32_vfp11_erratum_list *branch,
6109 bfd *branch_bfd,
6110 asection *branch_sec,
6111 unsigned int offset)
c7b8f16e
JB		 6112{
6113 asection *s;
6114 struct elf32_arm_link_hash_table *hash_table;
6115 char *tmp_name;
6116 struct elf_link_hash_entry *myh;
6117 struct bfd_link_hash_entry *bh;
6118 bfd_vma val;
6119 struct _arm_elf_section_data *sec_data;
c7b8f16e 6120 elf32_vfp11_erratum_list *newerr;
906e58ca 6121
c7b8f16e 6122 hash_table = elf32_arm_hash_table (link_info);
c7b8f16e
JB		 6123 BFD_ASSERT (hash_table != NULL);
6124 BFD_ASSERT (hash_table->bfd_of_glue_owner != NULL);
906e58ca 6125
3d4d4302 6126 s = bfd_get_linker_section
c7b8f16e 6127 (hash_table->bfd_of_glue_owner, VFP11_ERRATUM_VENEER_SECTION_NAME);
906e58ca 6128
c7b8f16e 6129 sec_data = elf32_arm_section_data (s);
906e58ca 6130
c7b8f16e 6131 BFD_ASSERT (s != NULL);
906e58ca 6132
21d799b5 6133 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen
99059e56 6134 (VFP11_ERRATUM_VENEER_ENTRY_NAME) + 10);
906e58ca 6135
c7b8f16e 6136 BFD_ASSERT (tmp_name);
906e58ca 6137
c7b8f16e
JB		 6138 sprintf (tmp_name, VFP11_ERRATUM_VENEER_ENTRY_NAME,
6139 hash_table->num_vfp11_fixes);
906e58ca 6140
c7b8f16e
JB		 6141 myh = elf_link_hash_lookup
6142 (&(hash_table)->root, tmp_name, FALSE, FALSE, FALSE);
906e58ca 6143
c7b8f16e 6144 BFD_ASSERT (myh == NULL);
906e58ca 6145
c7b8f16e
JB		 6146 bh = NULL;
6147 val = hash_table->vfp11_erratum_glue_size;
6148 _bfd_generic_link_add_one_symbol (link_info, hash_table->bfd_of_glue_owner,
99059e56
RM		 6149 tmp_name, BSF_FUNCTION | BSF_LOCAL, s, val,
6150 NULL, TRUE, FALSE, &bh);
c7b8f16e
JB		 6151
6152 myh = (struct elf_link_hash_entry *) bh;
6153 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
6154 myh->forced_local = 1;
6155
6156 /* Link veneer back to calling location. */
c7e2358a 6157 sec_data->erratumcount += 1;
21d799b5
NC		 6158 newerr = (elf32_vfp11_erratum_list *)
6159 bfd_zmalloc (sizeof (elf32_vfp11_erratum_list));
906e58ca 6160
c7b8f16e
JB		 6161 newerr->type = VFP11_ERRATUM_ARM_VENEER;
6162 newerr->vma = -1;
6163 newerr->u.v.branch = branch;
6164 newerr->u.v.id = hash_table->num_vfp11_fixes;
6165 branch->u.b.veneer = newerr;
6166
6167 newerr->next = sec_data->erratumlist;
6168 sec_data->erratumlist = newerr;
6169
6170 /* A symbol for the return from the veneer. */
6171 sprintf (tmp_name, VFP11_ERRATUM_VENEER_ENTRY_NAME "_r",
6172 hash_table->num_vfp11_fixes);
6173
6174 myh = elf_link_hash_lookup
6175 (&(hash_table)->root, tmp_name, FALSE, FALSE, FALSE);
906e58ca 6176
c7b8f16e
JB		 6177 if (myh != NULL)
6178 abort ();
6179
6180 bh = NULL;
6181 val = offset + 4;
6182 _bfd_generic_link_add_one_symbol (link_info, branch_bfd, tmp_name, BSF_LOCAL,
6183 branch_sec, val, NULL, TRUE, FALSE, &bh);
906e58ca 6184
c7b8f16e
JB		 6185 myh = (struct elf_link_hash_entry *) bh;
6186 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
6187 myh->forced_local = 1;
6188
6189 free (tmp_name);
906e58ca 6190
c7b8f16e
JB		 6191 /* Generate a mapping symbol for the veneer section, and explicitly add an
6192 entry for that symbol to the code/data map for the section. */
6193 if (hash_table->vfp11_erratum_glue_size == 0)
6194 {
6195 bh = NULL;
6196 /* FIXME: Creates an ARM symbol. Thumb mode will need attention if it
99059e56 6197 ever requires this erratum fix. */
c7b8f16e
JB		 6198 _bfd_generic_link_add_one_symbol (link_info,
6199 hash_table->bfd_of_glue_owner, "$a",
6200 BSF_LOCAL, s, 0, NULL,
99059e56 6201 TRUE, FALSE, &bh);
c7b8f16e
JB		 6202
6203 myh = (struct elf_link_hash_entry *) bh;
6204 myh->type = ELF_ST_INFO (STB_LOCAL, STT_NOTYPE);
6205 myh->forced_local = 1;
906e58ca 6206
c7b8f16e 6207 /* The elf32_arm_init_maps function only cares about symbols from input
99059e56
RM		 6208 BFDs. We must make a note of this generated mapping symbol
6209 ourselves so that code byteswapping works properly in
6210 elf32_arm_write_section. */
c7b8f16e
JB		 6211 elf32_arm_section_map_add (s, 'a', 0);
6212 }
906e58ca 6213
c7b8f16e
JB		 6214 s->size += VFP11_ERRATUM_VENEER_SIZE;
6215 hash_table->vfp11_erratum_glue_size += VFP11_ERRATUM_VENEER_SIZE;
6216 hash_table->num_vfp11_fixes++;
906e58ca 6217
c7b8f16e
JB		 6218 /* The offset of the veneer. */
6219 return val;
6220}
6221
a504d23a
LA		 6222/* Record information about a STM32L4XX STM erratum veneer. Only THUMB-mode
6223 veneers need to be handled because used only in Cortex-M. */
6224
6225static bfd_vma
6226record_stm32l4xx_erratum_veneer (struct bfd_link_info *link_info,
6227 elf32_stm32l4xx_erratum_list *branch,
6228 bfd *branch_bfd,
6229 asection *branch_sec,
6230 unsigned int offset,
6231 bfd_size_type veneer_size)
6232{
6233 asection *s;
6234 struct elf32_arm_link_hash_table *hash_table;
6235 char *tmp_name;
6236 struct elf_link_hash_entry *myh;
6237 struct bfd_link_hash_entry *bh;
6238 bfd_vma val;
6239 struct _arm_elf_section_data *sec_data;
6240 elf32_stm32l4xx_erratum_list *newerr;
6241
6242 hash_table = elf32_arm_hash_table (link_info);
6243 BFD_ASSERT (hash_table != NULL);
6244 BFD_ASSERT (hash_table->bfd_of_glue_owner != NULL);
6245
6246 s = bfd_get_linker_section
6247 (hash_table->bfd_of_glue_owner, STM32L4XX_ERRATUM_VENEER_SECTION_NAME);
6248
6249 BFD_ASSERT (s != NULL);
6250
6251 sec_data = elf32_arm_section_data (s);
6252
6253 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen
6254 (STM32L4XX_ERRATUM_VENEER_ENTRY_NAME) + 10);
6255
6256 BFD_ASSERT (tmp_name);
6257
6258 sprintf (tmp_name, STM32L4XX_ERRATUM_VENEER_ENTRY_NAME,
6259 hash_table->num_stm32l4xx_fixes);
6260
6261 myh = elf_link_hash_lookup
6262 (&(hash_table)->root, tmp_name, FALSE, FALSE, FALSE);
6263
6264 BFD_ASSERT (myh == NULL);
6265
6266 bh = NULL;
6267 val = hash_table->stm32l4xx_erratum_glue_size;
6268 _bfd_generic_link_add_one_symbol (link_info, hash_table->bfd_of_glue_owner,
6269 tmp_name, BSF_FUNCTION | BSF_LOCAL, s, val,
6270 NULL, TRUE, FALSE, &bh);
6271
6272 myh = (struct elf_link_hash_entry *) bh;
6273 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
6274 myh->forced_local = 1;
6275
6276 /* Link veneer back to calling location. */
6277 sec_data->stm32l4xx_erratumcount += 1;
6278 newerr = (elf32_stm32l4xx_erratum_list *)
6279 bfd_zmalloc (sizeof (elf32_stm32l4xx_erratum_list));
6280
6281 newerr->type = STM32L4XX_ERRATUM_VENEER;
6282 newerr->vma = -1;
6283 newerr->u.v.branch = branch;
6284 newerr->u.v.id = hash_table->num_stm32l4xx_fixes;
6285 branch->u.b.veneer = newerr;
6286
6287 newerr->next = sec_data->stm32l4xx_erratumlist;
6288 sec_data->stm32l4xx_erratumlist = newerr;
6289
6290 /* A symbol for the return from the veneer. */
6291 sprintf (tmp_name, STM32L4XX_ERRATUM_VENEER_ENTRY_NAME "_r",
6292 hash_table->num_stm32l4xx_fixes);
6293
6294 myh = elf_link_hash_lookup
6295 (&(hash_table)->root, tmp_name, FALSE, FALSE, FALSE);
6296
6297 if (myh != NULL)
6298 abort ();
6299
6300 bh = NULL;
6301 val = offset + 4;
6302 _bfd_generic_link_add_one_symbol (link_info, branch_bfd, tmp_name, BSF_LOCAL,
6303 branch_sec, val, NULL, TRUE, FALSE, &bh);
6304
6305 myh = (struct elf_link_hash_entry *) bh;
6306 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
6307 myh->forced_local = 1;
6308
6309 free (tmp_name);
6310
6311 /* Generate a mapping symbol for the veneer section, and explicitly add an
6312 entry for that symbol to the code/data map for the section. */
6313 if (hash_table->stm32l4xx_erratum_glue_size == 0)
6314 {
6315 bh = NULL;
6316 /* Creates a THUMB symbol since there is no other choice. */
6317 _bfd_generic_link_add_one_symbol (link_info,
6318 hash_table->bfd_of_glue_owner, "$t",
6319 BSF_LOCAL, s, 0, NULL,
6320 TRUE, FALSE, &bh);
6321
6322 myh = (struct elf_link_hash_entry *) bh;
6323 myh->type = ELF_ST_INFO (STB_LOCAL, STT_NOTYPE);
6324 myh->forced_local = 1;
6325
6326 /* The elf32_arm_init_maps function only cares about symbols from input
6327 BFDs. We must make a note of this generated mapping symbol
6328 ourselves so that code byteswapping works properly in
6329 elf32_arm_write_section. */
6330 elf32_arm_section_map_add (s, 't', 0);
6331 }
6332
6333 s->size += veneer_size;
6334 hash_table->stm32l4xx_erratum_glue_size += veneer_size;
6335 hash_table->num_stm32l4xx_fixes++;
6336
6337 /* The offset of the veneer. */
6338 return val;
6339}
6340
8029a119 6341#define ARM_GLUE_SECTION_FLAGS \
3e6b1042
DJ		 6342 (SEC_ALLOC | SEC_LOAD | SEC_HAS_CONTENTS | SEC_IN_MEMORY | SEC_CODE \
6343 | SEC_READONLY | SEC_LINKER_CREATED)
8029a119
NC		 6344
6345/* Create a fake section for use by the ARM backend of the linker. */
6346
6347static bfd_boolean
6348arm_make_glue_section (bfd * abfd, const char * name)
6349{
6350 asection * sec;
6351
3d4d4302 6352 sec = bfd_get_linker_section (abfd, name);
8029a119
NC		 6353 if (sec != NULL)
6354 /* Already made. */
6355 return TRUE;
6356
3d4d4302 6357 sec = bfd_make_section_anyway_with_flags (abfd, name, ARM_GLUE_SECTION_FLAGS);
8029a119
NC		 6358
6359 if (sec == NULL
6360 || !bfd_set_section_alignment (abfd, sec, 2))
6361 return FALSE;
6362
6363 /* Set the gc mark to prevent the section from being removed by garbage
6364 collection, despite the fact that no relocs refer to this section. */
6365 sec->gc_mark = 1;
6366
6367 return TRUE;
6368}
6369
1db37fe6
YG		 6370/* Set size of .plt entries. This function is called from the
6371 linker scripts in ld/emultempl/{armelf}.em. */
6372
6373void
6374bfd_elf32_arm_use_long_plt (void)
6375{
6376 elf32_arm_use_long_plt_entry = TRUE;
6377}
6378
8afb0e02
NC		 6379/* Add the glue sections to ABFD. This function is called from the
6380 linker scripts in ld/emultempl/{armelf}.em. */
9b485d32 6381
b34976b6 6382bfd_boolean
57e8b36a
NC		 6383bfd_elf32_arm_add_glue_sections_to_bfd (bfd *abfd,
6384 struct bfd_link_info *info)
252b5132 6385{
a504d23a
LA		 6386 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (info);
6387 bfd_boolean dostm32l4xx = globals
6388 && globals->stm32l4xx_fix != BFD_ARM_STM32L4XX_FIX_NONE;
6389 bfd_boolean addglue;
6390
8afb0e02
NC		 6391 /* If we are only performing a partial
6392 link do not bother adding the glue. */
0e1862bb 6393 if (bfd_link_relocatable (info))
b34976b6 6394 return TRUE;
252b5132 6395
a504d23a 6396 addglue = arm_make_glue_section (abfd, ARM2THUMB_GLUE_SECTION_NAME)
8029a119
NC		 6397 && arm_make_glue_section (abfd, THUMB2ARM_GLUE_SECTION_NAME)
6398 && arm_make_glue_section (abfd, VFP11_ERRATUM_VENEER_SECTION_NAME)
6399 && arm_make_glue_section (abfd, ARM_BX_GLUE_SECTION_NAME);
a504d23a
LA		 6400
6401 if (!dostm32l4xx)
6402 return addglue;
6403
6404 return addglue
6405 && arm_make_glue_section (abfd, STM32L4XX_ERRATUM_VENEER_SECTION_NAME);
8afb0e02
NC		 6406}
6407
6408/* Select a BFD to be used to hold the sections used by the glue code.
6409 This function is called from the linker scripts in ld/emultempl/
8029a119 6410 {armelf/pe}.em. */
8afb0e02 6411
b34976b6 6412bfd_boolean
57e8b36a 6413bfd_elf32_arm_get_bfd_for_interworking (bfd *abfd, struct bfd_link_info *info)
8afb0e02
NC		 6414{
6415 struct elf32_arm_link_hash_table *globals;
6416
6417 /* If we are only performing a partial link
6418 do not bother getting a bfd to hold the glue. */
0e1862bb 6419 if (bfd_link_relocatable (info))
b34976b6 6420 return TRUE;
8afb0e02 6421
b7693d02
DJ		 6422 /* Make sure we don't attach the glue sections to a dynamic object. */
6423 BFD_ASSERT (!(abfd->flags & DYNAMIC));
6424
8afb0e02 6425 globals = elf32_arm_hash_table (info);
8afb0e02
NC		 6426 BFD_ASSERT (globals != NULL);
6427
6428 if (globals->bfd_of_glue_owner != NULL)
b34976b6 6429 return TRUE;
8afb0e02 6430
252b5132
RH		 6431 /* Save the bfd for later use. */
6432 globals->bfd_of_glue_owner = abfd;
cedb70c5 6433
b34976b6 6434 return TRUE;
252b5132
RH		 6435}
6436
906e58ca
NC		 6437static void
6438check_use_blx (struct elf32_arm_link_hash_table *globals)
39b41c9c 6439{
2de70689
MGD		 6440 int cpu_arch;
6441
b38cadfb 6442 cpu_arch = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC,
2de70689
MGD		 6443 Tag_CPU_arch);
6444
6445 if (globals->fix_arm1176)
6446 {
6447 if (cpu_arch == TAG_CPU_ARCH_V6T2 || cpu_arch > TAG_CPU_ARCH_V6K)
6448 globals->use_blx = 1;
6449 }
6450 else
6451 {
6452 if (cpu_arch > TAG_CPU_ARCH_V4T)
6453 globals->use_blx = 1;
6454 }
39b41c9c
PB		 6455}
6456
b34976b6 6457bfd_boolean
57e8b36a 6458bfd_elf32_arm_process_before_allocation (bfd *abfd,
d504ffc8 6459 struct bfd_link_info *link_info)
252b5132
RH		 6460{
6461 Elf_Internal_Shdr *symtab_hdr;
6cdc0ccc 6462 Elf_Internal_Rela *internal_relocs = NULL;
252b5132
RH		 6463 Elf_Internal_Rela *irel, *irelend;
6464 bfd_byte *contents = NULL;
252b5132
RH		 6465
6466 asection *sec;
6467 struct elf32_arm_link_hash_table *globals;
6468
6469 /* If we are only performing a partial link do not bother
6470 to construct any glue. */
0e1862bb 6471 if (bfd_link_relocatable (link_info))
b34976b6 6472 return TRUE;
252b5132 6473
39ce1a6a
NC		 6474 /* Here we have a bfd that is to be included on the link. We have a
6475 hook to do reloc rummaging, before section sizes are nailed down. */
252b5132 6476 globals = elf32_arm_hash_table (link_info);
252b5132 6477 BFD_ASSERT (globals != NULL);
39ce1a6a
NC		 6478
6479 check_use_blx (globals);
252b5132 6480
d504ffc8 6481 if (globals->byteswap_code && !bfd_big_endian (abfd))
e489d0ae 6482 {
d003868e
AM		 6483 _bfd_error_handler (_("%B: BE8 images only valid in big-endian mode."),
6484 abfd);
e489d0ae
PB		 6485 return FALSE;
6486 }
f21f3fe0 6487
39ce1a6a
NC		 6488 /* PR 5398: If we have not decided to include any loadable sections in
6489 the output then we will not have a glue owner bfd. This is OK, it
6490 just means that there is nothing else for us to do here. */
6491 if (globals->bfd_of_glue_owner == NULL)
6492 return TRUE;
6493
252b5132
RH		 6494 /* Rummage around all the relocs and map the glue vectors. */
6495 sec = abfd->sections;
6496
6497 if (sec == NULL)
b34976b6 6498 return TRUE;
252b5132
RH		 6499
6500 for (; sec != NULL; sec = sec->next)
6501 {
6502 if (sec->reloc_count == 0)
6503 continue;
6504
2f475487
AM		 6505 if ((sec->flags & SEC_EXCLUDE) != 0)
6506 continue;
6507
0ffa91dd 6508 symtab_hdr = & elf_symtab_hdr (abfd);
252b5132 6509
9b485d32 6510 /* Load the relocs. */
6cdc0ccc 6511 internal_relocs
906e58ca 6512 = _bfd_elf_link_read_relocs (abfd, sec, NULL, NULL, FALSE);
252b5132 6513
6cdc0ccc
AM		 6514 if (internal_relocs == NULL)
6515 goto error_return;
252b5132 6516
6cdc0ccc
AM		 6517 irelend = internal_relocs + sec->reloc_count;
6518 for (irel = internal_relocs; irel < irelend; irel++)
252b5132
RH		 6519 {
6520 long r_type;
6521 unsigned long r_index;
252b5132
RH		 6522
6523 struct elf_link_hash_entry *h;
6524
6525 r_type = ELF32_R_TYPE (irel->r_info);
6526 r_index = ELF32_R_SYM (irel->r_info);
6527
9b485d32 6528 /* These are the only relocation types we care about. */
ba96a88f 6529 if ( r_type != R_ARM_PC24
845b51d6 6530 && (r_type != R_ARM_V4BX || globals->fix_v4bx < 2))
252b5132
RH		 6531 continue;
6532
6533 /* Get the section contents if we haven't done so already. */
6534 if (contents == NULL)
6535 {
6536 /* Get cached copy if it exists. */
6537 if (elf_section_data (sec)->this_hdr.contents != NULL)
6538 contents = elf_section_data (sec)->this_hdr.contents;
6539 else
6540 {
6541 /* Go get them off disk. */
57e8b36a 6542 if (! bfd_malloc_and_get_section (abfd, sec, &contents))
252b5132
RH		 6543 goto error_return;
6544 }
6545 }
6546
845b51d6
PB		 6547 if (r_type == R_ARM_V4BX)
6548 {
6549 int reg;
6550
6551 reg = bfd_get_32 (abfd, contents + irel->r_offset) & 0xf;
6552 record_arm_bx_glue (link_info, reg);
6553 continue;
6554 }
6555
a7c10850 6556 /* If the relocation is not against a symbol it cannot concern us. */
252b5132
RH		 6557 h = NULL;
6558
9b485d32 6559 /* We don't care about local symbols. */
252b5132
RH		 6560 if (r_index < symtab_hdr->sh_info)
6561 continue;
6562
9b485d32 6563 /* This is an external symbol. */
252b5132
RH		 6564 r_index -= symtab_hdr->sh_info;
6565 h = (struct elf_link_hash_entry *)
6566 elf_sym_hashes (abfd)[r_index];
6567
6568 /* If the relocation is against a static symbol it must be within
6569 the current section and so cannot be a cross ARM/Thumb relocation. */
6570 if (h == NULL)
6571 continue;
6572
d504ffc8
DJ		 6573 /* If the call will go through a PLT entry then we do not need
6574 glue. */
362d30a1 6575 if (globals->root.splt != NULL && h->plt.offset != (bfd_vma) -1)
b7693d02
DJ		 6576 continue;
6577
252b5132
RH		 6578 switch (r_type)
6579 {
6580 case R_ARM_PC24:
6581 /* This one is a call from arm code. We need to look up
99059e56
RM		 6582 the target of the call. If it is a thumb target, we
6583 insert glue. */
35fc36a8 6584 if (h->target_internal == ST_BRANCH_TO_THUMB)
252b5132
RH		 6585 record_arm_to_thumb_glue (link_info, h);
6586 break;
6587
252b5132 6588 default:
c6596c5e 6589 abort ();
252b5132
RH		 6590 }
6591 }
6cdc0ccc
AM		 6592
6593 if (contents != NULL
6594 && elf_section_data (sec)->this_hdr.contents != contents)
6595 free (contents);
6596 contents = NULL;
6597
6598 if (internal_relocs != NULL
6599 && elf_section_data (sec)->relocs != internal_relocs)
6600 free (internal_relocs);
6601 internal_relocs = NULL;
252b5132
RH		 6602 }
6603
b34976b6 6604 return TRUE;
9a5aca8c 6605
252b5132 6606error_return:
6cdc0ccc
AM		 6607 if (contents != NULL
6608 && elf_section_data (sec)->this_hdr.contents != contents)
6609 free (contents);
6610 if (internal_relocs != NULL
6611 && elf_section_data (sec)->relocs != internal_relocs)
6612 free (internal_relocs);
9a5aca8c 6613
b34976b6 6614 return FALSE;
252b5132 6615}
7e392df6 6616#endif
252b5132 6617
eb043451 6618
c7b8f16e
JB		 6619/* Initialise maps of ARM/Thumb/data for input BFDs. */
6620
6621void
6622bfd_elf32_arm_init_maps (bfd *abfd)
6623{
6624 Elf_Internal_Sym *isymbuf;
6625 Elf_Internal_Shdr *hdr;
6626 unsigned int i, localsyms;
6627
af1f4419
NC		 6628 /* PR 7093: Make sure that we are dealing with an arm elf binary. */
6629 if (! is_arm_elf (abfd))
6630 return;
6631
c7b8f16e
JB		 6632 if ((abfd->flags & DYNAMIC) != 0)
6633 return;
6634
0ffa91dd 6635 hdr = & elf_symtab_hdr (abfd);
c7b8f16e
JB		 6636 localsyms = hdr->sh_info;
6637
6638 /* Obtain a buffer full of symbols for this BFD. The hdr->sh_info field
6639 should contain the number of local symbols, which should come before any
6640 global symbols. Mapping symbols are always local. */
6641 isymbuf = bfd_elf_get_elf_syms (abfd, hdr, localsyms, 0, NULL, NULL,
6642 NULL);
6643
6644 /* No internal symbols read? Skip this BFD. */
6645 if (isymbuf == NULL)
6646 return;
6647
6648 for (i = 0; i < localsyms; i++)
6649 {
6650 Elf_Internal_Sym *isym = &isymbuf[i];
6651 asection *sec = bfd_section_from_elf_index (abfd, isym->st_shndx);
6652 const char *name;
906e58ca 6653
c7b8f16e 6654 if (sec != NULL
99059e56
RM		 6655 && ELF_ST_BIND (isym->st_info) == STB_LOCAL)
6656 {
6657 name = bfd_elf_string_from_elf_section (abfd,
6658 hdr->sh_link, isym->st_name);
906e58ca 6659
99059e56 6660 if (bfd_is_arm_special_symbol_name (name,
c7b8f16e 6661 BFD_ARM_SPECIAL_SYM_TYPE_MAP))
99059e56
RM		 6662 elf32_arm_section_map_add (sec, name[1], isym->st_value);
6663 }
c7b8f16e
JB		 6664 }
6665}
6666
6667
48229727
JB		 6668/* Auto-select enabling of Cortex-A8 erratum fix if the user didn't explicitly
6669 say what they wanted. */
6670
6671void
6672bfd_elf32_arm_set_cortex_a8_fix (bfd *obfd, struct bfd_link_info *link_info)
6673{
6674 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (link_info);
6675 obj_attribute *out_attr = elf_known_obj_attributes_proc (obfd);
6676
4dfe6ac6
NC		 6677 if (globals == NULL)
6678 return;
6679
48229727
JB		 6680 if (globals->fix_cortex_a8 == -1)
6681 {
6682 /* Turn on Cortex-A8 erratum workaround for ARMv7-A. */
6683 if (out_attr[Tag_CPU_arch].i == TAG_CPU_ARCH_V7
6684 && (out_attr[Tag_CPU_arch_profile].i == 'A'
6685 || out_attr[Tag_CPU_arch_profile].i == 0))
6686 globals->fix_cortex_a8 = 1;
6687 else
6688 globals->fix_cortex_a8 = 0;
6689 }
6690}
6691
6692
c7b8f16e
JB		 6693void
6694bfd_elf32_arm_set_vfp11_fix (bfd *obfd, struct bfd_link_info *link_info)
6695{
6696 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (link_info);
104d59d1 6697 obj_attribute *out_attr = elf_known_obj_attributes_proc (obfd);
906e58ca 6698
4dfe6ac6
NC		 6699 if (globals == NULL)
6700 return;
c7b8f16e
JB		 6701 /* We assume that ARMv7+ does not need the VFP11 denorm erratum fix. */
6702 if (out_attr[Tag_CPU_arch].i >= TAG_CPU_ARCH_V7)
6703 {
6704 switch (globals->vfp11_fix)
99059e56
RM		 6705 {
6706 case BFD_ARM_VFP11_FIX_DEFAULT:
6707 case BFD_ARM_VFP11_FIX_NONE:
6708 globals->vfp11_fix = BFD_ARM_VFP11_FIX_NONE;
6709 break;
6710
6711 default:
6712 /* Give a warning, but do as the user requests anyway. */
6713 (*_bfd_error_handler) (_("%B: warning: selected VFP11 erratum "
6714 "workaround is not necessary for target architecture"), obfd);
6715 }
c7b8f16e
JB		 6716 }
6717 else if (globals->vfp11_fix == BFD_ARM_VFP11_FIX_DEFAULT)
6718 /* For earlier architectures, we might need the workaround, but do not
6719 enable it by default. If users is running with broken hardware, they
6720 must enable the erratum fix explicitly. */
6721 globals->vfp11_fix = BFD_ARM_VFP11_FIX_NONE;
6722}
6723
a504d23a
LA		 6724void
6725bfd_elf32_arm_set_stm32l4xx_fix (bfd *obfd, struct bfd_link_info *link_info)
6726{
6727 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (link_info);
6728 obj_attribute *out_attr = elf_known_obj_attributes_proc (obfd);
6729
6730 if (globals == NULL)
6731 return;
6732
6733 /* We assume only Cortex-M4 may require the fix. */
6734 if (out_attr[Tag_CPU_arch].i != TAG_CPU_ARCH_V7E_M
6735 || out_attr[Tag_CPU_arch_profile].i != 'M')
6736 {
6737 if (globals->stm32l4xx_fix != BFD_ARM_STM32L4XX_FIX_NONE)
6738 /* Give a warning, but do as the user requests anyway. */
6739 (*_bfd_error_handler)
6740 (_("%B: warning: selected STM32L4XX erratum "
6741 "workaround is not necessary for target architecture"), obfd);
6742 }
6743}
c7b8f16e 6744
906e58ca
NC		 6745enum bfd_arm_vfp11_pipe
6746{
c7b8f16e
JB		 6747 VFP11_FMAC,
6748 VFP11_LS,
6749 VFP11_DS,
6750 VFP11_BAD
6751};
6752
6753/* Return a VFP register number. This is encoded as RX:X for single-precision
6754 registers, or X:RX for double-precision registers, where RX is the group of
6755 four bits in the instruction encoding and X is the single extension bit.
6756 RX and X fields are specified using their lowest (starting) bit. The return
6757 value is:
6758
6759 0...31: single-precision registers s0...s31
6760 32...63: double-precision registers d0...d31.
906e58ca 6761
c7b8f16e
JB		 6762 Although X should be zero for VFP11 (encoding d0...d15 only), we might
6763 encounter VFP3 instructions, so we allow the full range for DP registers. */
906e58ca 6764
c7b8f16e
JB		 6765static unsigned int
6766bfd_arm_vfp11_regno (unsigned int insn, bfd_boolean is_double, unsigned int rx,
99059e56 6767 unsigned int x)
c7b8f16e
JB		 6768{
6769 if (is_double)
6770 return (((insn >> rx) & 0xf) | (((insn >> x) & 1) << 4)) + 32;
6771 else
6772 return (((insn >> rx) & 0xf) << 1) | ((insn >> x) & 1);
6773}
6774
6775/* Set bits in *WMASK according to a register number REG as encoded by
6776 bfd_arm_vfp11_regno(). Ignore d16-d31. */
6777
6778static void
6779bfd_arm_vfp11_write_mask (unsigned int *wmask, unsigned int reg)
6780{
6781 if (reg < 32)
6782 *wmask |= 1 << reg;
6783 else if (reg < 48)
6784 *wmask |= 3 << ((reg - 32) * 2);
6785}
6786
6787/* Return TRUE if WMASK overwrites anything in REGS. */
6788
6789static bfd_boolean
6790bfd_arm_vfp11_antidependency (unsigned int wmask, int *regs, int numregs)
6791{
6792 int i;
906e58ca 6793
c7b8f16e
JB		 6794 for (i = 0; i < numregs; i++)
6795 {
6796 unsigned int reg = regs[i];
6797
6798 if (reg < 32 && (wmask & (1 << reg)) != 0)
99059e56 6799 return TRUE;
906e58ca 6800
c7b8f16e
JB		 6801 reg -= 32;
6802
6803 if (reg >= 16)
99059e56 6804 continue;
906e58ca 6805
c7b8f16e 6806 if ((wmask & (3 << (reg * 2))) != 0)
99059e56 6807 return TRUE;
c7b8f16e 6808 }
906e58ca 6809
c7b8f16e
JB		 6810 return FALSE;
6811}
6812
6813/* In this function, we're interested in two things: finding input registers
6814 for VFP data-processing instructions, and finding the set of registers which
6815 arbitrary VFP instructions may write to. We use a 32-bit unsigned int to
6816 hold the written set, so FLDM etc. are easy to deal with (we're only
6817 interested in 32 SP registers or 16 dp registers, due to the VFP version
6818 implemented by the chip in question). DP registers are marked by setting
6819 both SP registers in the write mask). */
6820
6821static enum bfd_arm_vfp11_pipe
6822bfd_arm_vfp11_insn_decode (unsigned int insn, unsigned int *destmask, int *regs,
99059e56 6823 int *numregs)
c7b8f16e 6824{
91d6fa6a 6825 enum bfd_arm_vfp11_pipe vpipe = VFP11_BAD;
c7b8f16e
JB		 6826 bfd_boolean is_double = ((insn & 0xf00) == 0xb00) ? 1 : 0;
6827
6828 if ((insn & 0x0f000e10) == 0x0e000a00) /* A data-processing insn. */
6829 {
6830 unsigned int pqrs;
6831 unsigned int fd = bfd_arm_vfp11_regno (insn, is_double, 12, 22);
6832 unsigned int fm = bfd_arm_vfp11_regno (insn, is_double, 0, 5);
6833
6834 pqrs = ((insn & 0x00800000) >> 20)
99059e56
RM		 6835 | ((insn & 0x00300000) >> 19)
6836 | ((insn & 0x00000040) >> 6);
c7b8f16e
JB		 6837
6838 switch (pqrs)
99059e56
RM		 6839 {
6840 case 0: /* fmac[sd]. */
6841 case 1: /* fnmac[sd]. */
6842 case 2: /* fmsc[sd]. */
6843 case 3: /* fnmsc[sd]. */
6844 vpipe = VFP11_FMAC;
6845 bfd_arm_vfp11_write_mask (destmask, fd);
6846 regs[0] = fd;
6847 regs[1] = bfd_arm_vfp11_regno (insn, is_double, 16, 7); /* Fn. */
6848 regs[2] = fm;
6849 *numregs = 3;
6850 break;
6851
6852 case 4: /* fmul[sd]. */
6853 case 5: /* fnmul[sd]. */
6854 case 6: /* fadd[sd]. */
6855 case 7: /* fsub[sd]. */
6856 vpipe = VFP11_FMAC;
6857 goto vfp_binop;
6858
6859 case 8: /* fdiv[sd]. */
6860 vpipe = VFP11_DS;
6861 vfp_binop:
6862 bfd_arm_vfp11_write_mask (destmask, fd);
6863 regs[0] = bfd_arm_vfp11_regno (insn, is_double, 16, 7); /* Fn. */
6864 regs[1] = fm;
6865 *numregs = 2;
6866 break;
6867
6868 case 15: /* extended opcode. */
6869 {
6870 unsigned int extn = ((insn >> 15) & 0x1e)
6871 | ((insn >> 7) & 1);
6872
6873 switch (extn)
6874 {
6875 case 0: /* fcpy[sd]. */
6876 case 1: /* fabs[sd]. */
6877 case 2: /* fneg[sd]. */
6878 case 8: /* fcmp[sd]. */
6879 case 9: /* fcmpe[sd]. */
6880 case 10: /* fcmpz[sd]. */
6881 case 11: /* fcmpez[sd]. */
6882 case 16: /* fuito[sd]. */
6883 case 17: /* fsito[sd]. */
6884 case 24: /* ftoui[sd]. */
6885 case 25: /* ftouiz[sd]. */
6886 case 26: /* ftosi[sd]. */
6887 case 27: /* ftosiz[sd]. */
6888 /* These instructions will not bounce due to underflow. */
6889 *numregs = 0;
6890 vpipe = VFP11_FMAC;
6891 break;
6892
6893 case 3: /* fsqrt[sd]. */
6894 /* fsqrt cannot underflow, but it can (perhaps) overwrite
6895 registers to cause the erratum in previous instructions. */
6896 bfd_arm_vfp11_write_mask (destmask, fd);
6897 vpipe = VFP11_DS;
6898 break;
6899
6900 case 15: /* fcvt{ds,sd}. */
6901 {
6902 int rnum = 0;
6903
6904 bfd_arm_vfp11_write_mask (destmask, fd);
c7b8f16e
JB		 6905
6906 /* Only FCVTSD can underflow. */
99059e56
RM		 6907 if ((insn & 0x100) != 0)
6908 regs[rnum++] = fm;
c7b8f16e 6909
99059e56 6910 *numregs = rnum;
c7b8f16e 6911
99059e56
RM		 6912 vpipe = VFP11_FMAC;
6913 }
6914 break;
c7b8f16e 6915
99059e56
RM		 6916 default:
6917 return VFP11_BAD;
6918 }
6919 }
6920 break;
c7b8f16e 6921
99059e56
RM		 6922 default:
6923 return VFP11_BAD;
6924 }
c7b8f16e
JB		 6925 }
6926 /* Two-register transfer. */
6927 else if ((insn & 0x0fe00ed0) == 0x0c400a10)
6928 {
6929 unsigned int fm = bfd_arm_vfp11_regno (insn, is_double, 0, 5);
906e58ca 6930
c7b8f16e
JB		 6931 if ((insn & 0x100000) == 0)
6932 {
99059e56
RM		 6933 if (is_double)
6934 bfd_arm_vfp11_write_mask (destmask, fm);
6935 else
6936 {
6937 bfd_arm_vfp11_write_mask (destmask, fm);
6938 bfd_arm_vfp11_write_mask (destmask, fm + 1);
6939 }
c7b8f16e
JB		 6940 }
6941
91d6fa6a 6942 vpipe = VFP11_LS;
c7b8f16e
JB		 6943 }
6944 else if ((insn & 0x0e100e00) == 0x0c100a00) /* A load insn. */
6945 {
6946 int fd = bfd_arm_vfp11_regno (insn, is_double, 12, 22);
6947 unsigned int puw = ((insn >> 21) & 0x1) | (((insn >> 23) & 3) << 1);
906e58ca 6948
c7b8f16e 6949 switch (puw)
99059e56
RM		 6950 {
6951 case 0: /* Two-reg transfer. We should catch these above. */
6952 abort ();
906e58ca 6953
99059e56
RM		 6954 case 2: /* fldm[sdx]. */
6955 case 3:
6956 case 5:
6957 {
6958 unsigned int i, offset = insn & 0xff;
c7b8f16e 6959
99059e56
RM		 6960 if (is_double)
6961 offset >>= 1;
c7b8f16e 6962
99059e56
RM		 6963 for (i = fd; i < fd + offset; i++)
6964 bfd_arm_vfp11_write_mask (destmask, i);
6965 }
6966 break;
906e58ca 6967
99059e56
RM		 6968 case 4: /* fld[sd]. */
6969 case 6:
6970 bfd_arm_vfp11_write_mask (destmask, fd);
6971 break;
906e58ca 6972
99059e56
RM		 6973 default:
6974 return VFP11_BAD;
6975 }
c7b8f16e 6976
91d6fa6a 6977 vpipe = VFP11_LS;
c7b8f16e
JB		 6978 }
6979 /* Single-register transfer. Note L==0. */
6980 else if ((insn & 0x0f100e10) == 0x0e000a10)
6981 {
6982 unsigned int opcode = (insn >> 21) & 7;
6983 unsigned int fn = bfd_arm_vfp11_regno (insn, is_double, 16, 7);
6984
6985 switch (opcode)
99059e56
RM		 6986 {
6987 case 0: /* fmsr/fmdlr. */
6988 case 1: /* fmdhr. */
6989 /* Mark fmdhr and fmdlr as writing to the whole of the DP
6990 destination register. I don't know if this is exactly right,
6991 but it is the conservative choice. */
6992 bfd_arm_vfp11_write_mask (destmask, fn);
6993 break;
6994
6995 case 7: /* fmxr. */
6996 break;
6997 }
c7b8f16e 6998
91d6fa6a 6999 vpipe = VFP11_LS;
c7b8f16e
JB		 7000 }
7001
91d6fa6a 7002 return vpipe;
c7b8f16e
JB		 7003}
7004
7005
7006static int elf32_arm_compare_mapping (const void * a, const void * b);
7007
7008
7009/* Look for potentially-troublesome code sequences which might trigger the
7010 VFP11 denormal/antidependency erratum. See, e.g., the ARM1136 errata sheet
7011 (available from ARM) for details of the erratum. A short version is
7012 described in ld.texinfo. */
7013
7014bfd_boolean
7015bfd_elf32_arm_vfp11_erratum_scan (bfd *abfd, struct bfd_link_info *link_info)
7016{
7017 asection *sec;
7018 bfd_byte *contents = NULL;
7019 int state = 0;
7020 int regs[3], numregs = 0;
7021 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (link_info);
7022 int use_vector = (globals->vfp11_fix == BFD_ARM_VFP11_FIX_VECTOR);
906e58ca 7023
4dfe6ac6
NC		 7024 if (globals == NULL)
7025 return FALSE;
7026
c7b8f16e
JB		 7027 /* We use a simple FSM to match troublesome VFP11 instruction sequences.
7028 The states transition as follows:
906e58ca 7029
c7b8f16e 7030 0 -> 1 (vector) or 0 -> 2 (scalar)
99059e56
RM		 7031 A VFP FMAC-pipeline instruction has been seen. Fill
7032 regs[0]..regs[numregs-1] with its input operands. Remember this
7033 instruction in 'first_fmac'.
c7b8f16e
JB		 7034
7035 1 -> 2
99059e56
RM		 7036 Any instruction, except for a VFP instruction which overwrites
7037 regs[*].
906e58ca 7038
c7b8f16e
JB		 7039 1 -> 3 [ -> 0 ] or
7040 2 -> 3 [ -> 0 ]
99059e56
RM		 7041 A VFP instruction has been seen which overwrites any of regs[*].
7042 We must make a veneer! Reset state to 0 before examining next
7043 instruction.
906e58ca 7044
c7b8f16e 7045 2 -> 0
99059e56
RM		 7046 If we fail to match anything in state 2, reset to state 0 and reset
7047 the instruction pointer to the instruction after 'first_fmac'.
c7b8f16e
JB		 7048
7049 If the VFP11 vector mode is in use, there must be at least two unrelated
7050 instructions between anti-dependent VFP11 instructions to properly avoid
906e58ca 7051 triggering the erratum, hence the use of the extra state 1. */
c7b8f16e
JB		 7052
7053 /* If we are only performing a partial link do not bother
7054 to construct any glue. */
0e1862bb 7055 if (bfd_link_relocatable (link_info))
c7b8f16e
JB		 7056 return TRUE;
7057
0ffa91dd
NC		 7058 /* Skip if this bfd does not correspond to an ELF image. */
7059 if (! is_arm_elf (abfd))
7060 return TRUE;
906e58ca 7061
c7b8f16e
JB		 7062 /* We should have chosen a fix type by the time we get here. */
7063 BFD_ASSERT (globals->vfp11_fix != BFD_ARM_VFP11_FIX_DEFAULT);
7064
7065 if (globals->vfp11_fix == BFD_ARM_VFP11_FIX_NONE)
7066 return TRUE;
2e6030b9 7067
33a7ffc2
JM		 7068 /* Skip this BFD if it corresponds to an executable or dynamic object. */
7069 if ((abfd->flags & (EXEC_P | DYNAMIC)) != 0)
7070 return TRUE;
7071
c7b8f16e
JB		 7072 for (sec = abfd->sections; sec != NULL; sec = sec->next)
7073 {
7074 unsigned int i, span, first_fmac = 0, veneer_of_insn = 0;
7075 struct _arm_elf_section_data *sec_data;
7076
7077 /* If we don't have executable progbits, we're not interested in this
99059e56 7078 section. Also skip if section is to be excluded. */
c7b8f16e 7079 if (elf_section_type (sec) != SHT_PROGBITS
99059e56
RM		 7080 || (elf_section_flags (sec) & SHF_EXECINSTR) == 0
7081 || (sec->flags & SEC_EXCLUDE) != 0
dbaa2011 7082 || sec->sec_info_type == SEC_INFO_TYPE_JUST_SYMS
33a7ffc2 7083 || sec->output_section == bfd_abs_section_ptr
99059e56
RM		 7084 || strcmp (sec->name, VFP11_ERRATUM_VENEER_SECTION_NAME) == 0)
7085 continue;
c7b8f16e
JB		 7086
7087 sec_data = elf32_arm_section_data (sec);
906e58ca 7088
c7b8f16e 7089 if (sec_data->mapcount == 0)
99059e56 7090 continue;
906e58ca 7091
c7b8f16e
JB		 7092 if (elf_section_data (sec)->this_hdr.contents != NULL)
7093 contents = elf_section_data (sec)->this_hdr.contents;
7094 else if (! bfd_malloc_and_get_section (abfd, sec, &contents))
7095 goto error_return;
7096
7097 qsort (sec_data->map, sec_data->mapcount, sizeof (elf32_arm_section_map),
7098 elf32_arm_compare_mapping);
7099
7100 for (span = 0; span < sec_data->mapcount; span++)
99059e56
RM		 7101 {
7102 unsigned int span_start = sec_data->map[span].vma;
7103 unsigned int span_end = (span == sec_data->mapcount - 1)
c7b8f16e 7104 ? sec->size : sec_data->map[span + 1].vma;
99059e56
RM		 7105 char span_type = sec_data->map[span].type;
7106
7107 /* FIXME: Only ARM mode is supported at present. We may need to
7108 support Thumb-2 mode also at some point. */
7109 if (span_type != 'a')
7110 continue;
7111
7112 for (i = span_start; i < span_end;)
7113 {
7114 unsigned int next_i = i + 4;
7115 unsigned int insn = bfd_big_endian (abfd)
7116 ? (contents[i] << 24)
7117 | (contents[i + 1] << 16)
7118 | (contents[i + 2] << 8)
7119 | contents[i + 3]
7120 : (contents[i + 3] << 24)
7121 | (contents[i + 2] << 16)
7122 | (contents[i + 1] << 8)
7123 | contents[i];
7124 unsigned int writemask = 0;
7125 enum bfd_arm_vfp11_pipe vpipe;
7126
7127 switch (state)
7128 {
7129 case 0:
7130 vpipe = bfd_arm_vfp11_insn_decode (insn, &writemask, regs,
7131 &numregs);
7132 /* I'm assuming the VFP11 erratum can trigger with denorm
7133 operands on either the FMAC or the DS pipeline. This might
7134 lead to slightly overenthusiastic veneer insertion. */
7135 if (vpipe == VFP11_FMAC || vpipe == VFP11_DS)
7136 {
7137 state = use_vector ? 1 : 2;
7138 first_fmac = i;
7139 veneer_of_insn = insn;
7140 }
7141 break;
7142
7143 case 1:
7144 {
7145 int other_regs[3], other_numregs;
7146 vpipe = bfd_arm_vfp11_insn_decode (insn, &writemask,
c7b8f16e 7147 other_regs,
99059e56
RM		 7148 &other_numregs);
7149 if (vpipe != VFP11_BAD
7150 && bfd_arm_vfp11_antidependency (writemask, regs,
c7b8f16e 7151 numregs))
99059e56
RM		 7152 state = 3;
7153 else
7154 state = 2;
7155 }
7156 break;
7157
7158 case 2:
7159 {
7160 int other_regs[3], other_numregs;
7161 vpipe = bfd_arm_vfp11_insn_decode (insn, &writemask,
c7b8f16e 7162 other_regs,
99059e56
RM		 7163 &other_numregs);
7164 if (vpipe != VFP11_BAD
7165 && bfd_arm_vfp11_antidependency (writemask, regs,
c7b8f16e 7166 numregs))
99059e56
RM		 7167 state = 3;
7168 else
7169 {
7170 state = 0;
7171 next_i = first_fmac + 4;
7172 }
7173 }
7174 break;
7175
7176 case 3:
7177 abort (); /* Should be unreachable. */
7178 }
7179
7180 if (state == 3)
7181 {
7182 elf32_vfp11_erratum_list *newerr =(elf32_vfp11_erratum_list *)
7183 bfd_zmalloc (sizeof (elf32_vfp11_erratum_list));
7184
7185 elf32_arm_section_data (sec)->erratumcount += 1;
7186
7187 newerr->u.b.vfp_insn = veneer_of_insn;
7188
7189 switch (span_type)
7190 {
7191 case 'a':
7192 newerr->type = VFP11_ERRATUM_BRANCH_TO_ARM_VENEER;
7193 break;
7194
7195 default:
7196 abort ();
7197 }
7198
7199 record_vfp11_erratum_veneer (link_info, newerr, abfd, sec,
c7b8f16e
JB		 7200 first_fmac);
7201
99059e56 7202 newerr->vma = -1;
c7b8f16e 7203
99059e56
RM		 7204 newerr->next = sec_data->erratumlist;
7205 sec_data->erratumlist = newerr;
c7b8f16e 7206
99059e56
RM		 7207 state = 0;
7208 }
c7b8f16e 7209
99059e56
RM		 7210 i = next_i;
7211 }
7212 }
906e58ca 7213
c7b8f16e 7214 if (contents != NULL
99059e56
RM		 7215 && elf_section_data (sec)->this_hdr.contents != contents)
7216 free (contents);
c7b8f16e
JB		 7217 contents = NULL;
7218 }
7219
7220 return TRUE;
7221
7222error_return:
7223 if (contents != NULL
7224 && elf_section_data (sec)->this_hdr.contents != contents)
7225 free (contents);
906e58ca 7226
c7b8f16e
JB		 7227 return FALSE;
7228}
7229
7230/* Find virtual-memory addresses for VFP11 erratum veneers and return locations
7231 after sections have been laid out, using specially-named symbols. */
7232
7233void
7234bfd_elf32_arm_vfp11_fix_veneer_locations (bfd *abfd,
7235 struct bfd_link_info *link_info)
7236{
7237 asection *sec;
7238 struct elf32_arm_link_hash_table *globals;
7239 char *tmp_name;
906e58ca 7240
0e1862bb 7241 if (bfd_link_relocatable (link_info))
c7b8f16e 7242 return;
2e6030b9
MS		 7243
7244 /* Skip if this bfd does not correspond to an ELF image. */
0ffa91dd 7245 if (! is_arm_elf (abfd))
2e6030b9
MS		 7246 return;
7247
c7b8f16e 7248 globals = elf32_arm_hash_table (link_info);
4dfe6ac6
NC		 7249 if (globals == NULL)
7250 return;
906e58ca 7251
21d799b5 7252 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen
99059e56 7253 (VFP11_ERRATUM_VENEER_ENTRY_NAME) + 10);
c7b8f16e
JB		 7254
7255 for (sec = abfd->sections; sec != NULL; sec = sec->next)
7256 {
7257 struct _arm_elf_section_data *sec_data = elf32_arm_section_data (sec);
7258 elf32_vfp11_erratum_list *errnode = sec_data->erratumlist;
906e58ca 7259
c7b8f16e 7260 for (; errnode != NULL; errnode = errnode->next)
99059e56
RM		 7261 {
7262 struct elf_link_hash_entry *myh;
7263 bfd_vma vma;
7264
7265 switch (errnode->type)
7266 {
7267 case VFP11_ERRATUM_BRANCH_TO_ARM_VENEER:
7268 case VFP11_ERRATUM_BRANCH_TO_THUMB_VENEER:
7269 /* Find veneer symbol. */
7270 sprintf (tmp_name, VFP11_ERRATUM_VENEER_ENTRY_NAME,
c7b8f16e
JB		 7271 errnode->u.b.veneer->u.v.id);
7272
99059e56
RM		 7273 myh = elf_link_hash_lookup
7274 (&(globals)->root, tmp_name, FALSE, FALSE, TRUE);
c7b8f16e 7275
a504d23a
LA		 7276 if (myh == NULL)
7277 (*_bfd_error_handler) (_("%B: unable to find VFP11 veneer "
7278 "`%s'"), abfd, tmp_name);
7279
7280 vma = myh->root.u.def.section->output_section->vma
7281 + myh->root.u.def.section->output_offset
7282 + myh->root.u.def.value;
7283
7284 errnode->u.b.veneer->vma = vma;
7285 break;
7286
7287 case VFP11_ERRATUM_ARM_VENEER:
7288 case VFP11_ERRATUM_THUMB_VENEER:
7289 /* Find return location. */
7290 sprintf (tmp_name, VFP11_ERRATUM_VENEER_ENTRY_NAME "_r",
7291 errnode->u.v.id);
7292
7293 myh = elf_link_hash_lookup
7294 (&(globals)->root, tmp_name, FALSE, FALSE, TRUE);
7295
7296 if (myh == NULL)
7297 (*_bfd_error_handler) (_("%B: unable to find VFP11 veneer "
7298 "`%s'"), abfd, tmp_name);
7299
7300 vma = myh->root.u.def.section->output_section->vma
7301 + myh->root.u.def.section->output_offset
7302 + myh->root.u.def.value;
7303
7304 errnode->u.v.branch->vma = vma;
7305 break;
7306
7307 default:
7308 abort ();
7309 }
7310 }
7311 }
7312
7313 free (tmp_name);
7314}
7315
7316/* Find virtual-memory addresses for STM32L4XX erratum veneers and
7317 return locations after sections have been laid out, using
7318 specially-named symbols. */
7319
7320void
7321bfd_elf32_arm_stm32l4xx_fix_veneer_locations (bfd *abfd,
7322 struct bfd_link_info *link_info)
7323{
7324 asection *sec;
7325 struct elf32_arm_link_hash_table *globals;
7326 char *tmp_name;
7327
7328 if (bfd_link_relocatable (link_info))
7329 return;
7330
7331 /* Skip if this bfd does not correspond to an ELF image. */
7332 if (! is_arm_elf (abfd))
7333 return;
7334
7335 globals = elf32_arm_hash_table (link_info);
7336 if (globals == NULL)
7337 return;
7338
7339 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen
7340 (STM32L4XX_ERRATUM_VENEER_ENTRY_NAME) + 10);
7341
7342 for (sec = abfd->sections; sec != NULL; sec = sec->next)
7343 {
7344 struct _arm_elf_section_data *sec_data = elf32_arm_section_data (sec);
7345 elf32_stm32l4xx_erratum_list *errnode = sec_data->stm32l4xx_erratumlist;
7346
7347 for (; errnode != NULL; errnode = errnode->next)
7348 {
7349 struct elf_link_hash_entry *myh;
7350 bfd_vma vma;
7351
7352 switch (errnode->type)
7353 {
7354 case STM32L4XX_ERRATUM_BRANCH_TO_VENEER:
7355 /* Find veneer symbol. */
7356 sprintf (tmp_name, STM32L4XX_ERRATUM_VENEER_ENTRY_NAME,
7357 errnode->u.b.veneer->u.v.id);
7358
7359 myh = elf_link_hash_lookup
7360 (&(globals)->root, tmp_name, FALSE, FALSE, TRUE);
7361
7362 if (myh == NULL)
7363 (*_bfd_error_handler) (_("%B: unable to find STM32L4XX veneer "
7364 "`%s'"), abfd, tmp_name);
7365
7366 vma = myh->root.u.def.section->output_section->vma
7367 + myh->root.u.def.section->output_offset
7368 + myh->root.u.def.value;
7369
7370 errnode->u.b.veneer->vma = vma;
7371 break;
7372
7373 case STM32L4XX_ERRATUM_VENEER:
7374 /* Find return location. */
7375 sprintf (tmp_name, STM32L4XX_ERRATUM_VENEER_ENTRY_NAME "_r",
7376 errnode->u.v.id);
7377
7378 myh = elf_link_hash_lookup
7379 (&(globals)->root, tmp_name, FALSE, FALSE, TRUE);
7380
7381 if (myh == NULL)
7382 (*_bfd_error_handler) (_("%B: unable to find STM32L4XX veneer "
7383 "`%s'"), abfd, tmp_name);
7384
7385 vma = myh->root.u.def.section->output_section->vma
7386 + myh->root.u.def.section->output_offset
7387 + myh->root.u.def.value;
7388
7389 errnode->u.v.branch->vma = vma;
7390 break;
7391
7392 default:
7393 abort ();
7394 }
7395 }
7396 }
7397
7398 free (tmp_name);
7399}
7400
7401static inline bfd_boolean
7402is_thumb2_ldmia (const insn32 insn)
7403{
7404 /* Encoding T2: LDM<c>.W <Rn>{!},<registers>
7405 1110 - 1000 - 10W1 - rrrr - PM (0) l - llll - llll - llll. */
7406 return (insn & 0xffd02000) == 0xe8900000;
7407}
7408
7409static inline bfd_boolean
7410is_thumb2_ldmdb (const insn32 insn)
7411{
7412 /* Encoding T1: LDMDB<c> <Rn>{!},<registers>
7413 1110 - 1001 - 00W1 - rrrr - PM (0) l - llll - llll - llll. */
7414 return (insn & 0xffd02000) == 0xe9100000;
7415}
7416
7417static inline bfd_boolean
7418is_thumb2_vldm (const insn32 insn)
7419{
7420 /* A6.5 Extension register load or store instruction
7421 A7.7.229
9239bbd3
CM		 7422 We look for SP 32-bit and DP 64-bit registers.
7423 Encoding T1 VLDM{mode}<c> <Rn>{!}, <list>
7424 <list> is consecutive 64-bit registers
7425 1110 - 110P - UDW1 - rrrr - vvvv - 1011 - iiii - iiii
a504d23a
LA		 7426 Encoding T2 VLDM{mode}<c> <Rn>{!}, <list>
7427 <list> is consecutive 32-bit registers
7428 1110 - 110P - UDW1 - rrrr - vvvv - 1010 - iiii - iiii
7429 if P==0 && U==1 && W==1 && Rn=1101 VPOP
7430 if PUW=010 || PUW=011 || PUW=101 VLDM. */
7431 return
9239bbd3
CM		 7432 (((insn & 0xfe100f00) == 0xec100b00) ||
7433 ((insn & 0xfe100f00) == 0xec100a00))
a504d23a
LA		 7434 && /* (IA without !). */
7435 (((((insn << 7) >> 28) & 0xd) == 0x4)
9239bbd3 7436 /* (IA with !), includes VPOP (when reg number is SP). */
a504d23a
LA		 7437 || ((((insn << 7) >> 28) & 0xd) == 0x5)
7438 /* (DB with !). */
7439 || ((((insn << 7) >> 28) & 0xd) == 0x9));
7440}
7441
7442/* STM STM32L4XX erratum : This function assumes that it receives an LDM or
7443 VLDM opcode and:
7444 - computes the number and the mode of memory accesses
7445 - decides if the replacement should be done:
7446 . replaces only if > 8-word accesses
7447 . or (testing purposes only) replaces all accesses. */
7448
7449static bfd_boolean
7450stm32l4xx_need_create_replacing_stub (const insn32 insn,
7451 bfd_arm_stm32l4xx_fix stm32l4xx_fix)
7452{
9239bbd3 7453 int nb_words = 0;
a504d23a
LA		 7454
7455 /* The field encoding the register list is the same for both LDMIA
7456 and LDMDB encodings. */
7457 if (is_thumb2_ldmia (insn) || is_thumb2_ldmdb (insn))
9239bbd3 7458 nb_words = popcount (insn & 0x0000ffff);
a504d23a 7459 else if (is_thumb2_vldm (insn))
9239bbd3 7460 nb_words = (insn & 0xff);
a504d23a
LA		 7461
7462 /* DEFAULT mode accounts for the real bug condition situation,
7463 ALL mode inserts stubs for each LDM/VLDM instruction (testing). */
7464 return
9239bbd3 7465 (stm32l4xx_fix == BFD_ARM_STM32L4XX_FIX_DEFAULT) ? nb_words > 8 :
a504d23a
LA		 7466 (stm32l4xx_fix == BFD_ARM_STM32L4XX_FIX_ALL) ? TRUE : FALSE;
7467}
7468
7469/* Look for potentially-troublesome code sequences which might trigger
7470 the STM STM32L4XX erratum. */
7471
7472bfd_boolean
7473bfd_elf32_arm_stm32l4xx_erratum_scan (bfd *abfd,
7474 struct bfd_link_info *link_info)
7475{
7476 asection *sec;
7477 bfd_byte *contents = NULL;
7478 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (link_info);
7479
7480 if (globals == NULL)
7481 return FALSE;
7482
7483 /* If we are only performing a partial link do not bother
7484 to construct any glue. */
7485 if (bfd_link_relocatable (link_info))
7486 return TRUE;
7487
7488 /* Skip if this bfd does not correspond to an ELF image. */
7489 if (! is_arm_elf (abfd))
7490 return TRUE;
7491
7492 if (globals->stm32l4xx_fix == BFD_ARM_STM32L4XX_FIX_NONE)
7493 return TRUE;
7494
7495 /* Skip this BFD if it corresponds to an executable or dynamic object. */
7496 if ((abfd->flags & (EXEC_P | DYNAMIC)) != 0)
7497 return TRUE;
7498
7499 for (sec = abfd->sections; sec != NULL; sec = sec->next)
7500 {
7501 unsigned int i, span;
7502 struct _arm_elf_section_data *sec_data;
7503
7504 /* If we don't have executable progbits, we're not interested in this
7505 section. Also skip if section is to be excluded. */
7506 if (elf_section_type (sec) != SHT_PROGBITS
7507 || (elf_section_flags (sec) & SHF_EXECINSTR) == 0
7508 || (sec->flags & SEC_EXCLUDE) != 0
7509 || sec->sec_info_type == SEC_INFO_TYPE_JUST_SYMS
7510 || sec->output_section == bfd_abs_section_ptr
7511 || strcmp (sec->name, STM32L4XX_ERRATUM_VENEER_SECTION_NAME) == 0)
7512 continue;
7513
7514 sec_data = elf32_arm_section_data (sec);
c7b8f16e 7515
a504d23a
LA		 7516 if (sec_data->mapcount == 0)
7517 continue;
c7b8f16e 7518
a504d23a
LA		 7519 if (elf_section_data (sec)->this_hdr.contents != NULL)
7520 contents = elf_section_data (sec)->this_hdr.contents;
7521 else if (! bfd_malloc_and_get_section (abfd, sec, &contents))
7522 goto error_return;
c7b8f16e 7523
a504d23a
LA		 7524 qsort (sec_data->map, sec_data->mapcount, sizeof (elf32_arm_section_map),
7525 elf32_arm_compare_mapping);
c7b8f16e 7526
a504d23a
LA		 7527 for (span = 0; span < sec_data->mapcount; span++)
7528 {
7529 unsigned int span_start = sec_data->map[span].vma;
7530 unsigned int span_end = (span == sec_data->mapcount - 1)
7531 ? sec->size : sec_data->map[span + 1].vma;
7532 char span_type = sec_data->map[span].type;
7533 int itblock_current_pos = 0;
c7b8f16e 7534
a504d23a
LA		 7535 /* Only Thumb2 mode need be supported with this CM4 specific
7536 code, we should not encounter any arm mode eg span_type
7537 != 'a'. */
7538 if (span_type != 't')
7539 continue;
c7b8f16e 7540
a504d23a
LA		 7541 for (i = span_start; i < span_end;)
7542 {
7543 unsigned int insn = bfd_get_16 (abfd, &contents[i]);
7544 bfd_boolean insn_32bit = FALSE;
7545 bfd_boolean is_ldm = FALSE;
7546 bfd_boolean is_vldm = FALSE;
7547 bfd_boolean is_not_last_in_it_block = FALSE;
7548
7549 /* The first 16-bits of all 32-bit thumb2 instructions start
7550 with opcode[15..13]=0b111 and the encoded op1 can be anything
7551 except opcode[12..11]!=0b00.
7552 See 32-bit Thumb instruction encoding. */
7553 if ((insn & 0xe000) == 0xe000 && (insn & 0x1800) != 0x0000)
7554 insn_32bit = TRUE;
c7b8f16e 7555
a504d23a
LA		 7556 /* Compute the predicate that tells if the instruction
7557 is concerned by the IT block
7558 - Creates an error if there is a ldm that is not
7559 last in the IT block thus cannot be replaced
7560 - Otherwise we can create a branch at the end of the
7561 IT block, it will be controlled naturally by IT
7562 with the proper pseudo-predicate
7563 - So the only interesting predicate is the one that
7564 tells that we are not on the last item of an IT
7565 block. */
7566 if (itblock_current_pos != 0)
7567 is_not_last_in_it_block = !!--itblock_current_pos;
906e58ca 7568
a504d23a
LA		 7569 if (insn_32bit)
7570 {
7571 /* Load the rest of the insn (in manual-friendly order). */
7572 insn = (insn << 16) | bfd_get_16 (abfd, &contents[i + 2]);
7573 is_ldm = is_thumb2_ldmia (insn) || is_thumb2_ldmdb (insn);
7574 is_vldm = is_thumb2_vldm (insn);
7575
7576 /* Veneers are created for (v)ldm depending on
7577 option flags and memory accesses conditions; but
7578 if the instruction is not the last instruction of
7579 an IT block, we cannot create a jump there, so we
7580 bail out. */
7581 if ((is_ldm || is_vldm) &&
7582 stm32l4xx_need_create_replacing_stub
7583 (insn, globals->stm32l4xx_fix))
7584 {
7585 if (is_not_last_in_it_block)
7586 {
7587 (*_bfd_error_handler)
7588 /* Note - overlong line used here to allow for translation. */
7589 (_("\
7590%B(%A+0x%lx): error: multiple load detected in non-last IT block instruction : STM32L4XX veneer cannot be generated.\n"
7591 "Use gcc option -mrestrict-it to generate only one instruction per IT block.\n"),
7592 abfd, sec, (long)i);
7593 }
7594 else
7595 {
7596 elf32_stm32l4xx_erratum_list *newerr =
7597 (elf32_stm32l4xx_erratum_list *)
7598 bfd_zmalloc
7599 (sizeof (elf32_stm32l4xx_erratum_list));
7600
7601 elf32_arm_section_data (sec)
7602 ->stm32l4xx_erratumcount += 1;
7603 newerr->u.b.insn = insn;
7604 /* We create only thumb branches. */
7605 newerr->type =
7606 STM32L4XX_ERRATUM_BRANCH_TO_VENEER;
7607 record_stm32l4xx_erratum_veneer
7608 (link_info, newerr, abfd, sec,
7609 i,
7610 is_ldm ?
7611 STM32L4XX_ERRATUM_LDM_VENEER_SIZE:
7612 STM32L4XX_ERRATUM_VLDM_VENEER_SIZE);
7613 newerr->vma = -1;
7614 newerr->next = sec_data->stm32l4xx_erratumlist;
7615 sec_data->stm32l4xx_erratumlist = newerr;
7616 }
7617 }
7618 }
7619 else
7620 {
7621 /* A7.7.37 IT p208
7622 IT blocks are only encoded in T1
7623 Encoding T1: IT{x{y{z}}} <firstcond>
7624 1 0 1 1 - 1 1 1 1 - firstcond - mask
7625 if mask = '0000' then see 'related encodings'
7626 We don't deal with UNPREDICTABLE, just ignore these.
7627 There can be no nested IT blocks so an IT block
7628 is naturally a new one for which it is worth
7629 computing its size. */
7630 bfd_boolean is_newitblock = ((insn & 0xff00) == 0xbf00) &&
7631 ((insn & 0x000f) != 0x0000);
7632 /* If we have a new IT block we compute its size. */
7633 if (is_newitblock)
7634 {
7635 /* Compute the number of instructions controlled
7636 by the IT block, it will be used to decide
7637 whether we are inside an IT block or not. */
7638 unsigned int mask = insn & 0x000f;
7639 itblock_current_pos = 4 - ctz (mask);
7640 }
7641 }
7642
7643 i += insn_32bit ? 4 : 2;
99059e56
RM		 7644 }
7645 }
a504d23a
LA		 7646
7647 if (contents != NULL
7648 && elf_section_data (sec)->this_hdr.contents != contents)
7649 free (contents);
7650 contents = NULL;
c7b8f16e 7651 }
906e58ca 7652
a504d23a
LA		 7653 return TRUE;
7654
7655error_return:
7656 if (contents != NULL
7657 && elf_section_data (sec)->this_hdr.contents != contents)
7658 free (contents);
c7b8f16e 7659
a504d23a
LA		 7660 return FALSE;
7661}
c7b8f16e 7662
eb043451
PB		 7663/* Set target relocation values needed during linking. */
7664
7665void
bf21ed78
MS		 7666bfd_elf32_arm_set_target_relocs (struct bfd *output_bfd,
7667 struct bfd_link_info *link_info,
eb043451 7668 int target1_is_rel,
319850b4 7669 char * target2_type,
99059e56 7670 int fix_v4bx,
c7b8f16e 7671 int use_blx,
99059e56 7672 bfd_arm_vfp11_fix vfp11_fix,
a504d23a 7673 bfd_arm_stm32l4xx_fix stm32l4xx_fix,
a9dc9481 7674 int no_enum_warn, int no_wchar_warn,
2de70689
MGD		 7675 int pic_veneer, int fix_cortex_a8,
7676 int fix_arm1176)
eb043451
PB		 7677{
7678 struct elf32_arm_link_hash_table *globals;
7679
7680 globals = elf32_arm_hash_table (link_info);
4dfe6ac6
NC		 7681 if (globals == NULL)
7682 return;
eb043451
PB		 7683
7684 globals->target1_is_rel = target1_is_rel;
7685 if (strcmp (target2_type, "rel") == 0)
7686 globals->target2_reloc = R_ARM_REL32;
eeac373a
PB		 7687 else if (strcmp (target2_type, "abs") == 0)
7688 globals->target2_reloc = R_ARM_ABS32;
eb043451
PB		 7689 else if (strcmp (target2_type, "got-rel") == 0)
7690 globals->target2_reloc = R_ARM_GOT_PREL;
7691 else
7692 {
7693 _bfd_error_handler (_("Invalid TARGET2 relocation type '%s'."),
7694 target2_type);
7695 }
319850b4 7696 globals->fix_v4bx = fix_v4bx;
33bfe774 7697 globals->use_blx |= use_blx;
c7b8f16e 7698 globals->vfp11_fix = vfp11_fix;
a504d23a 7699 globals->stm32l4xx_fix = stm32l4xx_fix;
27e55c4d 7700 globals->pic_veneer = pic_veneer;
48229727 7701 globals->fix_cortex_a8 = fix_cortex_a8;
2de70689 7702 globals->fix_arm1176 = fix_arm1176;
bf21ed78 7703
0ffa91dd
NC		 7704 BFD_ASSERT (is_arm_elf (output_bfd));
7705 elf_arm_tdata (output_bfd)->no_enum_size_warning = no_enum_warn;
a9dc9481 7706 elf_arm_tdata (output_bfd)->no_wchar_size_warning = no_wchar_warn;
eb043451 7707}
eb043451 7708
12a0a0fd 7709/* Replace the target offset of a Thumb bl or b.w instruction. */
252b5132 7710
12a0a0fd
PB		 7711static void
7712insert_thumb_branch (bfd *abfd, long int offset, bfd_byte *insn)
7713{
7714 bfd_vma upper;
7715 bfd_vma lower;
7716 int reloc_sign;
7717
7718 BFD_ASSERT ((offset & 1) == 0);
7719
7720 upper = bfd_get_16 (abfd, insn);
7721 lower = bfd_get_16 (abfd, insn + 2);
7722 reloc_sign = (offset < 0) ? 1 : 0;
7723 upper = (upper & ~(bfd_vma) 0x7ff)
7724 | ((offset >> 12) & 0x3ff)
7725 | (reloc_sign << 10);
906e58ca 7726 lower = (lower & ~(bfd_vma) 0x2fff)
12a0a0fd
PB		 7727 | (((!((offset >> 23) & 1)) ^ reloc_sign) << 13)
7728 | (((!((offset >> 22) & 1)) ^ reloc_sign) << 11)
7729 | ((offset >> 1) & 0x7ff);
7730 bfd_put_16 (abfd, upper, insn);
7731 bfd_put_16 (abfd, lower, insn + 2);
252b5132
RH		 7732}
7733
9b485d32
NC		 7734/* Thumb code calling an ARM function. */
7735
252b5132 7736static int
57e8b36a
NC		 7737elf32_thumb_to_arm_stub (struct bfd_link_info * info,
7738 const char * name,
7739 bfd * input_bfd,
7740 bfd * output_bfd,
7741 asection * input_section,
7742 bfd_byte * hit_data,
7743 asection * sym_sec,
7744 bfd_vma offset,
7745 bfd_signed_vma addend,
f2a9dd69
DJ		 7746 bfd_vma val,
7747 char **error_message)
252b5132 7748{
bcbdc74c 7749 asection * s = 0;
dc810e39 7750 bfd_vma my_offset;
252b5132 7751 long int ret_offset;
bcbdc74c
NC		 7752 struct elf_link_hash_entry * myh;
7753 struct elf32_arm_link_hash_table * globals;
252b5132 7754
f2a9dd69 7755 myh = find_thumb_glue (info, name, error_message);
252b5132 7756 if (myh == NULL)
b34976b6 7757 return FALSE;
252b5132
RH		 7758
7759 globals = elf32_arm_hash_table (info);
252b5132
RH		 7760 BFD_ASSERT (globals != NULL);
7761 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
7762
7763 my_offset = myh->root.u.def.value;
7764
3d4d4302
AM		 7765 s = bfd_get_linker_section (globals->bfd_of_glue_owner,
7766 THUMB2ARM_GLUE_SECTION_NAME);
252b5132
RH		 7767
7768 BFD_ASSERT (s != NULL);
7769 BFD_ASSERT (s->contents != NULL);
7770 BFD_ASSERT (s->output_section != NULL);
7771
7772 if ((my_offset & 0x01) == 0x01)
7773 {
7774 if (sym_sec != NULL
7775 && sym_sec->owner != NULL
7776 && !INTERWORK_FLAG (sym_sec->owner))
7777 {
8f615d07 7778 (*_bfd_error_handler)
d003868e 7779 (_("%B(%s): warning: interworking not enabled.\n"
3aaeb7d3 7780 " first occurrence: %B: Thumb call to ARM"),
d003868e 7781 sym_sec->owner, input_bfd, name);
252b5132 7782
b34976b6 7783 return FALSE;
252b5132
RH		 7784 }
7785
7786 --my_offset;
7787 myh->root.u.def.value = my_offset;
7788
52ab56c2
PB		 7789 put_thumb_insn (globals, output_bfd, (bfd_vma) t2a1_bx_pc_insn,
7790 s->contents + my_offset);
252b5132 7791
52ab56c2
PB		 7792 put_thumb_insn (globals, output_bfd, (bfd_vma) t2a2_noop_insn,
7793 s->contents + my_offset + 2);
252b5132
RH		 7794
7795 ret_offset =
9b485d32
NC		 7796 /* Address of destination of the stub. */
7797 ((bfd_signed_vma) val)
252b5132 7798 - ((bfd_signed_vma)
57e8b36a
NC		 7799 /* Offset from the start of the current section
7800 to the start of the stubs. */
9b485d32
NC		 7801 (s->output_offset
7802 /* Offset of the start of this stub from the start of the stubs. */
7803 + my_offset
7804 /* Address of the start of the current section. */
7805 + s->output_section->vma)
7806 /* The branch instruction is 4 bytes into the stub. */
7807 + 4
7808 /* ARM branches work from the pc of the instruction + 8. */
7809 + 8);
252b5132 7810
52ab56c2
PB		 7811 put_arm_insn (globals, output_bfd,
7812 (bfd_vma) t2a3_b_insn | ((ret_offset >> 2) & 0x00FFFFFF),
7813 s->contents + my_offset + 4);
252b5132
RH		 7814 }
7815
7816 BFD_ASSERT (my_offset <= globals->thumb_glue_size);
7817
427bfd90
NC		 7818 /* Now go back and fix up the original BL insn to point to here. */
7819 ret_offset =
7820 /* Address of where the stub is located. */
7821 (s->output_section->vma + s->output_offset + my_offset)
7822 /* Address of where the BL is located. */
57e8b36a
NC		 7823 - (input_section->output_section->vma + input_section->output_offset
7824 + offset)
427bfd90
NC		 7825 /* Addend in the relocation. */
7826 - addend
7827 /* Biassing for PC-relative addressing. */
7828 - 8;
252b5132 7829
12a0a0fd 7830 insert_thumb_branch (input_bfd, ret_offset, hit_data - input_section->vma);
252b5132 7831
b34976b6 7832 return TRUE;
252b5132
RH		 7833}
7834
a4fd1a8e 7835/* Populate an Arm to Thumb stub. Returns the stub symbol. */
9b485d32 7836
a4fd1a8e
PB		 7837static struct elf_link_hash_entry *
7838elf32_arm_create_thumb_stub (struct bfd_link_info * info,
7839 const char * name,
7840 bfd * input_bfd,
7841 bfd * output_bfd,
7842 asection * sym_sec,
7843 bfd_vma val,
8029a119
NC		 7844 asection * s,
7845 char ** error_message)
252b5132 7846{
dc810e39 7847 bfd_vma my_offset;
252b5132 7848 long int ret_offset;
bcbdc74c
NC		 7849 struct elf_link_hash_entry * myh;
7850 struct elf32_arm_link_hash_table * globals;
252b5132 7851
f2a9dd69 7852 myh = find_arm_glue (info, name, error_message);
252b5132 7853 if (myh == NULL)
a4fd1a8e 7854 return NULL;
252b5132
RH		 7855
7856 globals = elf32_arm_hash_table (info);
252b5132
RH		 7857 BFD_ASSERT (globals != NULL);
7858 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
7859
7860 my_offset = myh->root.u.def.value;
252b5132
RH		 7861
7862 if ((my_offset & 0x01) == 0x01)
7863 {
7864 if (sym_sec != NULL
7865 && sym_sec->owner != NULL
7866 && !INTERWORK_FLAG (sym_sec->owner))
7867 {
8f615d07 7868 (*_bfd_error_handler)
d003868e
AM		 7869 (_("%B(%s): warning: interworking not enabled.\n"
7870 " first occurrence: %B: arm call to thumb"),
7871 sym_sec->owner, input_bfd, name);
252b5132 7872 }
9b485d32 7873
252b5132
RH		 7874 --my_offset;
7875 myh->root.u.def.value = my_offset;
7876
0e1862bb
L		 7877 if (bfd_link_pic (info)
7878 || globals->root.is_relocatable_executable
27e55c4d 7879 || globals->pic_veneer)
8f6277f5
PB		 7880 {
7881 /* For relocatable objects we can't use absolute addresses,
7882 so construct the address from a relative offset. */
7883 /* TODO: If the offset is small it's probably worth
7884 constructing the address with adds. */
52ab56c2
PB		 7885 put_arm_insn (globals, output_bfd, (bfd_vma) a2t1p_ldr_insn,
7886 s->contents + my_offset);
7887 put_arm_insn (globals, output_bfd, (bfd_vma) a2t2p_add_pc_insn,
7888 s->contents + my_offset + 4);
7889 put_arm_insn (globals, output_bfd, (bfd_vma) a2t3p_bx_r12_insn,
7890 s->contents + my_offset + 8);
8f6277f5
PB		 7891 /* Adjust the offset by 4 for the position of the add,
7892 and 8 for the pipeline offset. */
7893 ret_offset = (val - (s->output_offset
7894 + s->output_section->vma
7895 + my_offset + 12))
7896 | 1;
7897 bfd_put_32 (output_bfd, ret_offset,
7898 s->contents + my_offset + 12);
7899 }
26079076
PB		 7900 else if (globals->use_blx)
7901 {
7902 put_arm_insn (globals, output_bfd, (bfd_vma) a2t1v5_ldr_insn,
7903 s->contents + my_offset);
7904
7905 /* It's a thumb address. Add the low order bit. */
7906 bfd_put_32 (output_bfd, val | a2t2v5_func_addr_insn,
7907 s->contents + my_offset + 4);
7908 }
8f6277f5
PB		 7909 else
7910 {
52ab56c2
PB		 7911 put_arm_insn (globals, output_bfd, (bfd_vma) a2t1_ldr_insn,
7912 s->contents + my_offset);
252b5132 7913
52ab56c2
PB		 7914 put_arm_insn (globals, output_bfd, (bfd_vma) a2t2_bx_r12_insn,
7915 s->contents + my_offset + 4);
252b5132 7916
8f6277f5
PB		 7917 /* It's a thumb address. Add the low order bit. */
7918 bfd_put_32 (output_bfd, val | a2t3_func_addr_insn,
7919 s->contents + my_offset + 8);
8029a119
NC		 7920
7921 my_offset += 12;
8f6277f5 7922 }
252b5132
RH		 7923 }
7924
7925 BFD_ASSERT (my_offset <= globals->arm_glue_size);
7926
a4fd1a8e
PB		 7927 return myh;
7928}
7929
7930/* Arm code calling a Thumb function. */
7931
7932static int
7933elf32_arm_to_thumb_stub (struct bfd_link_info * info,
7934 const char * name,
7935 bfd * input_bfd,
7936 bfd * output_bfd,
7937 asection * input_section,
7938 bfd_byte * hit_data,
7939 asection * sym_sec,
7940 bfd_vma offset,
7941 bfd_signed_vma addend,
f2a9dd69
DJ		 7942 bfd_vma val,
7943 char **error_message)
a4fd1a8e
PB		 7944{
7945 unsigned long int tmp;
7946 bfd_vma my_offset;
7947 asection * s;
7948 long int ret_offset;
7949 struct elf_link_hash_entry * myh;
7950 struct elf32_arm_link_hash_table * globals;
7951
7952 globals = elf32_arm_hash_table (info);
a4fd1a8e
PB		 7953 BFD_ASSERT (globals != NULL);
7954 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
7955
3d4d4302
AM		 7956 s = bfd_get_linker_section (globals->bfd_of_glue_owner,
7957 ARM2THUMB_GLUE_SECTION_NAME);
a4fd1a8e
PB		 7958 BFD_ASSERT (s != NULL);
7959 BFD_ASSERT (s->contents != NULL);
7960 BFD_ASSERT (s->output_section != NULL);
7961
7962 myh = elf32_arm_create_thumb_stub (info, name, input_bfd, output_bfd,
f2a9dd69 7963 sym_sec, val, s, error_message);
a4fd1a8e
PB		 7964 if (!myh)
7965 return FALSE;
7966
7967 my_offset = myh->root.u.def.value;
252b5132
RH		 7968 tmp = bfd_get_32 (input_bfd, hit_data);
7969 tmp = tmp & 0xFF000000;
7970
9b485d32 7971 /* Somehow these are both 4 too far, so subtract 8. */
dc810e39
AM		 7972 ret_offset = (s->output_offset
7973 + my_offset
7974 + s->output_section->vma
7975 - (input_section->output_offset
7976 + input_section->output_section->vma
7977 + offset + addend)
7978 - 8);
9a5aca8c 7979
252b5132
RH		 7980 tmp = tmp | ((ret_offset >> 2) & 0x00FFFFFF);
7981
dc810e39 7982 bfd_put_32 (output_bfd, (bfd_vma) tmp, hit_data - input_section->vma);
252b5132 7983
b34976b6 7984 return TRUE;
252b5132
RH		 7985}
7986
a4fd1a8e
PB		 7987/* Populate Arm stub for an exported Thumb function. */
7988
7989static bfd_boolean
7990elf32_arm_to_thumb_export_stub (struct elf_link_hash_entry *h, void * inf)
7991{
7992 struct bfd_link_info * info = (struct bfd_link_info *) inf;
7993 asection * s;
7994 struct elf_link_hash_entry * myh;
7995 struct elf32_arm_link_hash_entry *eh;
7996 struct elf32_arm_link_hash_table * globals;
7997 asection *sec;
7998 bfd_vma val;
f2a9dd69 7999 char *error_message;
a4fd1a8e 8000
906e58ca 8001 eh = elf32_arm_hash_entry (h);
a4fd1a8e
PB		 8002 /* Allocate stubs for exported Thumb functions on v4t. */
8003 if (eh->export_glue == NULL)
8004 return TRUE;
8005
8006 globals = elf32_arm_hash_table (info);
a4fd1a8e
PB		 8007 BFD_ASSERT (globals != NULL);
8008 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
8009
3d4d4302
AM		 8010 s = bfd_get_linker_section (globals->bfd_of_glue_owner,
8011 ARM2THUMB_GLUE_SECTION_NAME);
a4fd1a8e
PB		 8012 BFD_ASSERT (s != NULL);
8013 BFD_ASSERT (s->contents != NULL);
8014 BFD_ASSERT (s->output_section != NULL);
8015
8016 sec = eh->export_glue->root.u.def.section;
0eaedd0e
PB		 8017
8018 BFD_ASSERT (sec->output_section != NULL);
8019
a4fd1a8e
PB		 8020 val = eh->export_glue->root.u.def.value + sec->output_offset
8021 + sec->output_section->vma;
8029a119 8022
a4fd1a8e
PB		 8023 myh = elf32_arm_create_thumb_stub (info, h->root.root.string,
8024 h->root.u.def.section->owner,
f2a9dd69
DJ		 8025 globals->obfd, sec, val, s,
8026 &error_message);
a4fd1a8e
PB		 8027 BFD_ASSERT (myh);
8028 return TRUE;
8029}
8030
845b51d6
PB		 8031/* Populate ARMv4 BX veneers. Returns the absolute adress of the veneer. */
8032
8033static bfd_vma
8034elf32_arm_bx_glue (struct bfd_link_info * info, int reg)
8035{
8036 bfd_byte *p;
8037 bfd_vma glue_addr;
8038 asection *s;
8039 struct elf32_arm_link_hash_table *globals;
8040
8041 globals = elf32_arm_hash_table (info);
845b51d6
PB		 8042 BFD_ASSERT (globals != NULL);
8043 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
8044
3d4d4302
AM		 8045 s = bfd_get_linker_section (globals->bfd_of_glue_owner,
8046 ARM_BX_GLUE_SECTION_NAME);
845b51d6
PB		 8047 BFD_ASSERT (s != NULL);
8048 BFD_ASSERT (s->contents != NULL);
8049 BFD_ASSERT (s->output_section != NULL);
8050
8051 BFD_ASSERT (globals->bx_glue_offset[reg] & 2);
8052
8053 glue_addr = globals->bx_glue_offset[reg] & ~(bfd_vma)3;
8054
8055 if ((globals->bx_glue_offset[reg] & 1) == 0)
8056 {
8057 p = s->contents + glue_addr;
8058 bfd_put_32 (globals->obfd, armbx1_tst_insn + (reg << 16), p);
8059 bfd_put_32 (globals->obfd, armbx2_moveq_insn + reg, p + 4);
8060 bfd_put_32 (globals->obfd, armbx3_bx_insn + reg, p + 8);
8061 globals->bx_glue_offset[reg] |= 1;
8062 }
8063
8064 return glue_addr + s->output_section->vma + s->output_offset;
8065}
8066
a4fd1a8e
PB		 8067/* Generate Arm stubs for exported Thumb symbols. */
8068static void
906e58ca 8069elf32_arm_begin_write_processing (bfd *abfd ATTRIBUTE_UNUSED,
a4fd1a8e
PB		 8070 struct bfd_link_info *link_info)
8071{
8072 struct elf32_arm_link_hash_table * globals;
8073
8029a119
NC		 8074 if (link_info == NULL)
8075 /* Ignore this if we are not called by the ELF backend linker. */
a4fd1a8e
PB		 8076 return;
8077
8078 globals = elf32_arm_hash_table (link_info);
4dfe6ac6
NC		 8079 if (globals == NULL)
8080 return;
8081
84c08195
PB		 8082 /* If blx is available then exported Thumb symbols are OK and there is
8083 nothing to do. */
a4fd1a8e
PB		 8084 if (globals->use_blx)
8085 return;
8086
8087 elf_link_hash_traverse (&globals->root, elf32_arm_to_thumb_export_stub,
8088 link_info);
8089}
8090
47beaa6a
RS		 8091/* Reserve space for COUNT dynamic relocations in relocation selection
8092 SRELOC. */
8093
8094static void
8095elf32_arm_allocate_dynrelocs (struct bfd_link_info *info, asection *sreloc,
8096 bfd_size_type count)
8097{
8098 struct elf32_arm_link_hash_table *htab;
8099
8100 htab = elf32_arm_hash_table (info);
8101 BFD_ASSERT (htab->root.dynamic_sections_created);
8102 if (sreloc == NULL)
8103 abort ();
8104 sreloc->size += RELOC_SIZE (htab) * count;
8105}
8106
34e77a92
RS		 8107/* Reserve space for COUNT R_ARM_IRELATIVE relocations. If the link is
8108 dynamic, the relocations should go in SRELOC, otherwise they should
8109 go in the special .rel.iplt section. */
8110
8111static void
8112elf32_arm_allocate_irelocs (struct bfd_link_info *info, asection *sreloc,
8113 bfd_size_type count)
8114{
8115 struct elf32_arm_link_hash_table *htab;
8116
8117 htab = elf32_arm_hash_table (info);
8118 if (!htab->root.dynamic_sections_created)
8119 htab->root.irelplt->size += RELOC_SIZE (htab) * count;
8120 else
8121 {
8122 BFD_ASSERT (sreloc != NULL);
8123 sreloc->size += RELOC_SIZE (htab) * count;
8124 }
8125}
8126
47beaa6a
RS		 8127/* Add relocation REL to the end of relocation section SRELOC. */
8128
8129static void
8130elf32_arm_add_dynreloc (bfd *output_bfd, struct bfd_link_info *info,
8131 asection *sreloc, Elf_Internal_Rela *rel)
8132{
8133 bfd_byte *loc;
8134 struct elf32_arm_link_hash_table *htab;
8135
8136 htab = elf32_arm_hash_table (info);
34e77a92
RS		 8137 if (!htab->root.dynamic_sections_created
8138 && ELF32_R_TYPE (rel->r_info) == R_ARM_IRELATIVE)
8139 sreloc = htab->root.irelplt;
47beaa6a
RS		 8140 if (sreloc == NULL)
8141 abort ();
8142 loc = sreloc->contents;
8143 loc += sreloc->reloc_count++ * RELOC_SIZE (htab);
8144 if (sreloc->reloc_count * RELOC_SIZE (htab) > sreloc->size)
8145 abort ();
8146 SWAP_RELOC_OUT (htab) (output_bfd, rel, loc);
8147}
8148
34e77a92
RS		 8149/* Allocate room for a PLT entry described by ROOT_PLT and ARM_PLT.
8150 IS_IPLT_ENTRY says whether the entry belongs to .iplt rather than
8151 to .plt. */
8152
8153static void
8154elf32_arm_allocate_plt_entry (struct bfd_link_info *info,
8155 bfd_boolean is_iplt_entry,
8156 union gotplt_union *root_plt,
8157 struct arm_plt_info *arm_plt)
8158{
8159 struct elf32_arm_link_hash_table *htab;
8160 asection *splt;
8161 asection *sgotplt;
8162
8163 htab = elf32_arm_hash_table (info);
8164
8165 if (is_iplt_entry)
8166 {
8167 splt = htab->root.iplt;
8168 sgotplt = htab->root.igotplt;
8169
99059e56
RM		 8170 /* NaCl uses a special first entry in .iplt too. */
8171 if (htab->nacl_p && splt->size == 0)
8172 splt->size += htab->plt_header_size;
8173
34e77a92
RS		 8174 /* Allocate room for an R_ARM_IRELATIVE relocation in .rel.iplt. */
8175 elf32_arm_allocate_irelocs (info, htab->root.irelplt, 1);
8176 }
8177 else
8178 {
8179 splt = htab->root.splt;
8180 sgotplt = htab->root.sgotplt;
8181
8182 /* Allocate room for an R_JUMP_SLOT relocation in .rel.plt. */
8183 elf32_arm_allocate_dynrelocs (info, htab->root.srelplt, 1);
8184
8185 /* If this is the first .plt entry, make room for the special
8186 first entry. */
8187 if (splt->size == 0)
8188 splt->size += htab->plt_header_size;
9f19ab6d
WN		 8189
8190 htab->next_tls_desc_index++;
34e77a92
RS		 8191 }
8192
8193 /* Allocate the PLT entry itself, including any leading Thumb stub. */
8194 if (elf32_arm_plt_needs_thumb_stub_p (info, arm_plt))
8195 splt->size += PLT_THUMB_STUB_SIZE;
8196 root_plt->offset = splt->size;
8197 splt->size += htab->plt_entry_size;
8198
8199 if (!htab->symbian_p)
8200 {
8201 /* We also need to make an entry in the .got.plt section, which
8202 will be placed in the .got section by the linker script. */
9f19ab6d
WN		 8203 if (is_iplt_entry)
8204 arm_plt->got_offset = sgotplt->size;
8205 else
8206 arm_plt->got_offset = sgotplt->size - 8 * htab->num_tls_desc;
34e77a92
RS		 8207 sgotplt->size += 4;
8208 }
8209}
8210
b38cadfb
NC		 8211static bfd_vma
8212arm_movw_immediate (bfd_vma value)
8213{
8214 return (value & 0x00000fff) | ((value & 0x0000f000) << 4);
8215}
8216
8217static bfd_vma
8218arm_movt_immediate (bfd_vma value)
8219{
8220 return ((value & 0x0fff0000) >> 16) | ((value & 0xf0000000) >> 12);
8221}
8222
34e77a92
RS		 8223/* Fill in a PLT entry and its associated GOT slot. If DYNINDX == -1,
8224 the entry lives in .iplt and resolves to (*SYM_VALUE)().
8225 Otherwise, DYNINDX is the index of the symbol in the dynamic
8226 symbol table and SYM_VALUE is undefined.
8227
8228 ROOT_PLT points to the offset of the PLT entry from the start of its
8229 section (.iplt or .plt). ARM_PLT points to the symbol's ARM-specific
57460bcf 8230 bookkeeping information.
34e77a92 8231
57460bcf
NC		 8232 Returns FALSE if there was a problem. */
8233
8234static bfd_boolean
34e77a92
RS		 8235elf32_arm_populate_plt_entry (bfd *output_bfd, struct bfd_link_info *info,
8236 union gotplt_union *root_plt,
8237 struct arm_plt_info *arm_plt,
8238 int dynindx, bfd_vma sym_value)
8239{
8240 struct elf32_arm_link_hash_table *htab;
8241 asection *sgot;
8242 asection *splt;
8243 asection *srel;
8244 bfd_byte *loc;
8245 bfd_vma plt_index;
8246 Elf_Internal_Rela rel;
8247 bfd_vma plt_header_size;
8248 bfd_vma got_header_size;
8249
8250 htab = elf32_arm_hash_table (info);
8251
8252 /* Pick the appropriate sections and sizes. */
8253 if (dynindx == -1)
8254 {
8255 splt = htab->root.iplt;
8256 sgot = htab->root.igotplt;
8257 srel = htab->root.irelplt;
8258
8259 /* There are no reserved entries in .igot.plt, and no special
8260 first entry in .iplt. */
8261 got_header_size = 0;
8262 plt_header_size = 0;
8263 }
8264 else
8265 {
8266 splt = htab->root.splt;
8267 sgot = htab->root.sgotplt;
8268 srel = htab->root.srelplt;
8269
8270 got_header_size = get_elf_backend_data (output_bfd)->got_header_size;
8271 plt_header_size = htab->plt_header_size;
8272 }
8273 BFD_ASSERT (splt != NULL && srel != NULL);
8274
8275 /* Fill in the entry in the procedure linkage table. */
8276 if (htab->symbian_p)
8277 {
8278 BFD_ASSERT (dynindx >= 0);
8279 put_arm_insn (htab, output_bfd,
8280 elf32_arm_symbian_plt_entry[0],
8281 splt->contents + root_plt->offset);
8282 bfd_put_32 (output_bfd,
8283 elf32_arm_symbian_plt_entry[1],
8284 splt->contents + root_plt->offset + 4);
8285
8286 /* Fill in the entry in the .rel.plt section. */
8287 rel.r_offset = (splt->output_section->vma
8288 + splt->output_offset
8289 + root_plt->offset + 4);
8290 rel.r_info = ELF32_R_INFO (dynindx, R_ARM_GLOB_DAT);
8291
8292 /* Get the index in the procedure linkage table which
8293 corresponds to this symbol. This is the index of this symbol
8294 in all the symbols for which we are making plt entries. The
8295 first entry in the procedure linkage table is reserved. */
8296 plt_index = ((root_plt->offset - plt_header_size)
8297 / htab->plt_entry_size);
8298 }
8299 else
8300 {
8301 bfd_vma got_offset, got_address, plt_address;
8302 bfd_vma got_displacement, initial_got_entry;
8303 bfd_byte * ptr;
8304
8305 BFD_ASSERT (sgot != NULL);
8306
8307 /* Get the offset into the .(i)got.plt table of the entry that
8308 corresponds to this function. */
8309 got_offset = (arm_plt->got_offset & -2);
8310
8311 /* Get the index in the procedure linkage table which
8312 corresponds to this symbol. This is the index of this symbol
8313 in all the symbols for which we are making plt entries.
8314 After the reserved .got.plt entries, all symbols appear in
8315 the same order as in .plt. */
8316 plt_index = (got_offset - got_header_size) / 4;
8317
8318 /* Calculate the address of the GOT entry. */
8319 got_address = (sgot->output_section->vma
8320 + sgot->output_offset
8321 + got_offset);
8322
8323 /* ...and the address of the PLT entry. */
8324 plt_address = (splt->output_section->vma
8325 + splt->output_offset
8326 + root_plt->offset);
8327
8328 ptr = splt->contents + root_plt->offset;
0e1862bb 8329 if (htab->vxworks_p && bfd_link_pic (info))
34e77a92
RS		 8330 {
8331 unsigned int i;
8332 bfd_vma val;
8333
8334 for (i = 0; i != htab->plt_entry_size / 4; i++, ptr += 4)
8335 {
8336 val = elf32_arm_vxworks_shared_plt_entry[i];
8337 if (i == 2)
8338 val |= got_address - sgot->output_section->vma;
8339 if (i == 5)
8340 val |= plt_index * RELOC_SIZE (htab);
8341 if (i == 2 || i == 5)
8342 bfd_put_32 (output_bfd, val, ptr);
8343 else
8344 put_arm_insn (htab, output_bfd, val, ptr);
8345 }
8346 }
8347 else if (htab->vxworks_p)
8348 {
8349 unsigned int i;
8350 bfd_vma val;
8351
8352 for (i = 0; i != htab->plt_entry_size / 4; i++, ptr += 4)
8353 {
8354 val = elf32_arm_vxworks_exec_plt_entry[i];
8355 if (i == 2)
8356 val |= got_address;
8357 if (i == 4)
8358 val |= 0xffffff & -((root_plt->offset + i * 4 + 8) >> 2);
8359 if (i == 5)
8360 val |= plt_index * RELOC_SIZE (htab);
8361 if (i == 2 || i == 5)
8362 bfd_put_32 (output_bfd, val, ptr);
8363 else
8364 put_arm_insn (htab, output_bfd, val, ptr);
8365 }
8366
8367 loc = (htab->srelplt2->contents
8368 + (plt_index * 2 + 1) * RELOC_SIZE (htab));
8369
8370 /* Create the .rela.plt.unloaded R_ARM_ABS32 relocation
8371 referencing the GOT for this PLT entry. */
8372 rel.r_offset = plt_address + 8;
8373 rel.r_info = ELF32_R_INFO (htab->root.hgot->indx, R_ARM_ABS32);
8374 rel.r_addend = got_offset;
8375 SWAP_RELOC_OUT (htab) (output_bfd, &rel, loc);
8376 loc += RELOC_SIZE (htab);
8377
8378 /* Create the R_ARM_ABS32 relocation referencing the
8379 beginning of the PLT for this GOT entry. */
8380 rel.r_offset = got_address;
8381 rel.r_info = ELF32_R_INFO (htab->root.hplt->indx, R_ARM_ABS32);
8382 rel.r_addend = 0;
8383 SWAP_RELOC_OUT (htab) (output_bfd, &rel, loc);
8384 }
b38cadfb
NC		 8385 else if (htab->nacl_p)
8386 {
8387 /* Calculate the displacement between the PLT slot and the
8388 common tail that's part of the special initial PLT slot. */
6034aab8 8389 int32_t tail_displacement
b38cadfb
NC		 8390 = ((splt->output_section->vma + splt->output_offset
8391 + ARM_NACL_PLT_TAIL_OFFSET)
8392 - (plt_address + htab->plt_entry_size + 4));
8393 BFD_ASSERT ((tail_displacement & 3) == 0);
8394 tail_displacement >>= 2;
8395
8396 BFD_ASSERT ((tail_displacement & 0xff000000) == 0
8397 || (-tail_displacement & 0xff000000) == 0);
8398
8399 /* Calculate the displacement between the PLT slot and the entry
8400 in the GOT. The offset accounts for the value produced by
8401 adding to pc in the penultimate instruction of the PLT stub. */
6034aab8 8402 got_displacement = (got_address
99059e56 8403 - (plt_address + htab->plt_entry_size));
b38cadfb
NC		 8404
8405 /* NaCl does not support interworking at all. */
8406 BFD_ASSERT (!elf32_arm_plt_needs_thumb_stub_p (info, arm_plt));
8407
8408 put_arm_insn (htab, output_bfd,
8409 elf32_arm_nacl_plt_entry[0]
8410 | arm_movw_immediate (got_displacement),
8411 ptr + 0);
8412 put_arm_insn (htab, output_bfd,
8413 elf32_arm_nacl_plt_entry[1]
8414 | arm_movt_immediate (got_displacement),
8415 ptr + 4);
8416 put_arm_insn (htab, output_bfd,
8417 elf32_arm_nacl_plt_entry[2],
8418 ptr + 8);
8419 put_arm_insn (htab, output_bfd,
8420 elf32_arm_nacl_plt_entry[3]
8421 | (tail_displacement & 0x00ffffff),
8422 ptr + 12);
8423 }
57460bcf
NC		 8424 else if (using_thumb_only (htab))
8425 {
eed94f8f 8426 /* PR ld/16017: Generate thumb only PLT entries. */
469a3493 8427 if (!using_thumb2 (htab))
eed94f8f
NC		 8428 {
8429 /* FIXME: We ought to be able to generate thumb-1 PLT
8430 instructions... */
8431 _bfd_error_handler (_("%B: Warning: thumb-1 mode PLT generation not currently supported"),
8432 output_bfd);
8433 return FALSE;
8434 }
57460bcf 8435
eed94f8f
NC		 8436 /* Calculate the displacement between the PLT slot and the entry in
8437 the GOT. The 12-byte offset accounts for the value produced by
8438 adding to pc in the 3rd instruction of the PLT stub. */
8439 got_displacement = got_address - (plt_address + 12);
8440
8441 /* As we are using 32 bit instructions we have to use 'put_arm_insn'
8442 instead of 'put_thumb_insn'. */
8443 put_arm_insn (htab, output_bfd,
8444 elf32_thumb2_plt_entry[0]
8445 | ((got_displacement & 0x000000ff) << 16)
8446 | ((got_displacement & 0x00000700) << 20)
8447 | ((got_displacement & 0x00000800) >> 1)
8448 | ((got_displacement & 0x0000f000) >> 12),
8449 ptr + 0);
8450 put_arm_insn (htab, output_bfd,
8451 elf32_thumb2_plt_entry[1]
8452 | ((got_displacement & 0x00ff0000) )
8453 | ((got_displacement & 0x07000000) << 4)
8454 | ((got_displacement & 0x08000000) >> 17)
8455 | ((got_displacement & 0xf0000000) >> 28),
8456 ptr + 4);
8457 put_arm_insn (htab, output_bfd,
8458 elf32_thumb2_plt_entry[2],
8459 ptr + 8);
8460 put_arm_insn (htab, output_bfd,
8461 elf32_thumb2_plt_entry[3],
8462 ptr + 12);
57460bcf 8463 }
34e77a92
RS		 8464 else
8465 {
8466 /* Calculate the displacement between the PLT slot and the
8467 entry in the GOT. The eight-byte offset accounts for the
8468 value produced by adding to pc in the first instruction
8469 of the PLT stub. */
8470 got_displacement = got_address - (plt_address + 8);
8471
34e77a92
RS		 8472 if (elf32_arm_plt_needs_thumb_stub_p (info, arm_plt))
8473 {
8474 put_thumb_insn (htab, output_bfd,
8475 elf32_arm_plt_thumb_stub[0], ptr - 4);
8476 put_thumb_insn (htab, output_bfd,
8477 elf32_arm_plt_thumb_stub[1], ptr - 2);
8478 }
8479
1db37fe6
YG		 8480 if (!elf32_arm_use_long_plt_entry)
8481 {
8482 BFD_ASSERT ((got_displacement & 0xf0000000) == 0);
8483
8484 put_arm_insn (htab, output_bfd,
8485 elf32_arm_plt_entry_short[0]
8486 | ((got_displacement & 0x0ff00000) >> 20),
8487 ptr + 0);
8488 put_arm_insn (htab, output_bfd,
8489 elf32_arm_plt_entry_short[1]
8490 | ((got_displacement & 0x000ff000) >> 12),
8491 ptr+ 4);
8492 put_arm_insn (htab, output_bfd,
8493 elf32_arm_plt_entry_short[2]
8494 | (got_displacement & 0x00000fff),
8495 ptr + 8);
34e77a92 8496#ifdef FOUR_WORD_PLT
1db37fe6 8497 bfd_put_32 (output_bfd, elf32_arm_plt_entry_short[3], ptr + 12);
34e77a92 8498#endif
1db37fe6
YG		 8499 }
8500 else
8501 {
8502 put_arm_insn (htab, output_bfd,
8503 elf32_arm_plt_entry_long[0]
8504 | ((got_displacement & 0xf0000000) >> 28),
8505 ptr + 0);
8506 put_arm_insn (htab, output_bfd,
8507 elf32_arm_plt_entry_long[1]
8508 | ((got_displacement & 0x0ff00000) >> 20),
8509 ptr + 4);
8510 put_arm_insn (htab, output_bfd,
8511 elf32_arm_plt_entry_long[2]
8512 | ((got_displacement & 0x000ff000) >> 12),
8513 ptr+ 8);
8514 put_arm_insn (htab, output_bfd,
8515 elf32_arm_plt_entry_long[3]
8516 | (got_displacement & 0x00000fff),
8517 ptr + 12);
8518 }
34e77a92
RS		 8519 }
8520
8521 /* Fill in the entry in the .rel(a).(i)plt section. */
8522 rel.r_offset = got_address;
8523 rel.r_addend = 0;
8524 if (dynindx == -1)
8525 {
8526 /* .igot.plt entries use IRELATIVE relocations against SYM_VALUE.
8527 The dynamic linker or static executable then calls SYM_VALUE
8528 to determine the correct run-time value of the .igot.plt entry. */
8529 rel.r_info = ELF32_R_INFO (0, R_ARM_IRELATIVE);
8530 initial_got_entry = sym_value;
8531 }
8532 else
8533 {
8534 rel.r_info = ELF32_R_INFO (dynindx, R_ARM_JUMP_SLOT);
8535 initial_got_entry = (splt->output_section->vma
8536 + splt->output_offset);
8537 }
8538
8539 /* Fill in the entry in the global offset table. */
8540 bfd_put_32 (output_bfd, initial_got_entry,
8541 sgot->contents + got_offset);
8542 }
8543
aba8c3de
WN		 8544 if (dynindx == -1)
8545 elf32_arm_add_dynreloc (output_bfd, info, srel, &rel);
8546 else
8547 {
8548 loc = srel->contents + plt_index * RELOC_SIZE (htab);
8549 SWAP_RELOC_OUT (htab) (output_bfd, &rel, loc);
8550 }
57460bcf
NC		 8551
8552 return TRUE;
34e77a92
RS		 8553}
8554
eb043451
PB		 8555/* Some relocations map to different relocations depending on the
8556 target. Return the real relocation. */
8029a119 8557
eb043451
PB		 8558static int
8559arm_real_reloc_type (struct elf32_arm_link_hash_table * globals,
8560 int r_type)
8561{
8562 switch (r_type)
8563 {
8564 case R_ARM_TARGET1:
8565 if (globals->target1_is_rel)
8566 return R_ARM_REL32;
8567 else
8568 return R_ARM_ABS32;
8569
8570 case R_ARM_TARGET2:
8571 return globals->target2_reloc;
8572
8573 default:
8574 return r_type;
8575 }
8576}
eb043451 8577
ba93b8ac
DJ		 8578/* Return the base VMA address which should be subtracted from real addresses
8579 when resolving @dtpoff relocation.
8580 This is PT_TLS segment p_vaddr. */
8581
8582static bfd_vma
8583dtpoff_base (struct bfd_link_info *info)
8584{
8585 /* If tls_sec is NULL, we should have signalled an error already. */
8586 if (elf_hash_table (info)->tls_sec == NULL)
8587 return 0;
8588 return elf_hash_table (info)->tls_sec->vma;
8589}
8590
8591/* Return the relocation value for @tpoff relocation
8592 if STT_TLS virtual address is ADDRESS. */
8593
8594static bfd_vma
8595tpoff (struct bfd_link_info *info, bfd_vma address)
8596{
8597 struct elf_link_hash_table *htab = elf_hash_table (info);
8598 bfd_vma base;
8599
8600 /* If tls_sec is NULL, we should have signalled an error already. */
8601 if (htab->tls_sec == NULL)
8602 return 0;
8603 base = align_power ((bfd_vma) TCB_SIZE, htab->tls_sec->alignment_power);
8604 return address - htab->tls_sec->vma + base;
8605}
8606
00a97672
RS		 8607/* Perform an R_ARM_ABS12 relocation on the field pointed to by DATA.
8608 VALUE is the relocation value. */
8609
8610static bfd_reloc_status_type
8611elf32_arm_abs12_reloc (bfd *abfd, void *data, bfd_vma value)
8612{
8613 if (value > 0xfff)
8614 return bfd_reloc_overflow;
8615
8616 value |= bfd_get_32 (abfd, data) & 0xfffff000;
8617 bfd_put_32 (abfd, value, data);
8618 return bfd_reloc_ok;
8619}
8620
0855e32b
NS		 8621/* Handle TLS relaxations. Relaxing is possible for symbols that use
8622 R_ARM_GOTDESC, R_ARM_{,THM_}TLS_CALL or
8623 R_ARM_{,THM_}TLS_DESCSEQ relocations, during a static link.
8624
8625 Return bfd_reloc_ok if we're done, bfd_reloc_continue if the caller
8626 is to then call final_link_relocate. Return other values in the
62672b10
NS		 8627 case of error.
8628
8629 FIXME:When --emit-relocs is in effect, we'll emit relocs describing
8630 the pre-relaxed code. It would be nice if the relocs were updated
8631 to match the optimization. */
0855e32b 8632
b38cadfb 8633static bfd_reloc_status_type
0855e32b 8634elf32_arm_tls_relax (struct elf32_arm_link_hash_table *globals,
b38cadfb 8635 bfd *input_bfd, asection *input_sec, bfd_byte *contents,
0855e32b
NS		 8636 Elf_Internal_Rela *rel, unsigned long is_local)
8637{
8638 unsigned long insn;
b38cadfb 8639
0855e32b
NS		 8640 switch (ELF32_R_TYPE (rel->r_info))
8641 {
8642 default:
8643 return bfd_reloc_notsupported;
b38cadfb 8644
0855e32b
NS		 8645 case R_ARM_TLS_GOTDESC:
8646 if (is_local)
8647 insn = 0;
8648 else
8649 {
8650 insn = bfd_get_32 (input_bfd, contents + rel->r_offset);
8651 if (insn & 1)
8652 insn -= 5; /* THUMB */
8653 else
8654 insn -= 8; /* ARM */
8655 }
8656 bfd_put_32 (input_bfd, insn, contents + rel->r_offset);
8657 return bfd_reloc_continue;
8658
8659 case R_ARM_THM_TLS_DESCSEQ:
8660 /* Thumb insn. */
8661 insn = bfd_get_16 (input_bfd, contents + rel->r_offset);
8662 if ((insn & 0xff78) == 0x4478) /* add rx, pc */
8663 {
8664 if (is_local)
8665 /* nop */
8666 bfd_put_16 (input_bfd, 0x46c0, contents + rel->r_offset);
8667 }
8668 else if ((insn & 0xffc0) == 0x6840) /* ldr rx,[ry,#4] */
8669 {
8670 if (is_local)
8671 /* nop */
8672 bfd_put_16 (input_bfd, 0x46c0, contents + rel->r_offset);
8673 else
8674 /* ldr rx,[ry] */
8675 bfd_put_16 (input_bfd, insn & 0xf83f, contents + rel->r_offset);
8676 }
8677 else if ((insn & 0xff87) == 0x4780) /* blx rx */
8678 {
8679 if (is_local)
8680 /* nop */
8681 bfd_put_16 (input_bfd, 0x46c0, contents + rel->r_offset);
8682 else
8683 /* mov r0, rx */
8684 bfd_put_16 (input_bfd, 0x4600 | (insn & 0x78),
8685 contents + rel->r_offset);
8686 }
8687 else
8688 {
8689 if ((insn & 0xf000) == 0xf000 || (insn & 0xf800) == 0xe800)
8690 /* It's a 32 bit instruction, fetch the rest of it for
8691 error generation. */
8692 insn = (insn << 16)
8693 | bfd_get_16 (input_bfd, contents + rel->r_offset + 2);
8694 (*_bfd_error_handler)
8695 (_("%B(%A+0x%lx):unexpected Thumb instruction '0x%x' in TLS trampoline"),
8696 input_bfd, input_sec, (unsigned long)rel->r_offset, insn);
8697 return bfd_reloc_notsupported;
8698 }
8699 break;
b38cadfb 8700
0855e32b
NS		 8701 case R_ARM_TLS_DESCSEQ:
8702 /* arm insn. */
8703 insn = bfd_get_32 (input_bfd, contents + rel->r_offset);
8704 if ((insn & 0xffff0ff0) == 0xe08f0000) /* add rx,pc,ry */
8705 {
8706 if (is_local)
8707 /* mov rx, ry */
8708 bfd_put_32 (input_bfd, 0xe1a00000 | (insn & 0xffff),
8709 contents + rel->r_offset);
8710 }
8711 else if ((insn & 0xfff00fff) == 0xe5900004) /* ldr rx,[ry,#4]*/
8712 {
8713 if (is_local)
8714 /* nop */
8715 bfd_put_32 (input_bfd, 0xe1a00000, contents + rel->r_offset);
8716 else
8717 /* ldr rx,[ry] */
8718 bfd_put_32 (input_bfd, insn & 0xfffff000,
8719 contents + rel->r_offset);
8720 }
8721 else if ((insn & 0xfffffff0) == 0xe12fff30) /* blx rx */
8722 {
8723 if (is_local)
8724 /* nop */
8725 bfd_put_32 (input_bfd, 0xe1a00000, contents + rel->r_offset);
8726 else
8727 /* mov r0, rx */
8728 bfd_put_32 (input_bfd, 0xe1a00000 | (insn & 0xf),
8729 contents + rel->r_offset);
8730 }
8731 else
8732 {
8733 (*_bfd_error_handler)
8734 (_("%B(%A+0x%lx):unexpected ARM instruction '0x%x' in TLS trampoline"),
8735 input_bfd, input_sec, (unsigned long)rel->r_offset, insn);
8736 return bfd_reloc_notsupported;
8737 }
8738 break;
8739
8740 case R_ARM_TLS_CALL:
8741 /* GD->IE relaxation, turn the instruction into 'nop' or
8742 'ldr r0, [pc,r0]' */
8743 insn = is_local ? 0xe1a00000 : 0xe79f0000;
8744 bfd_put_32 (input_bfd, insn, contents + rel->r_offset);
8745 break;
b38cadfb 8746
0855e32b 8747 case R_ARM_THM_TLS_CALL:
6a631e86 8748 /* GD->IE relaxation. */
0855e32b
NS		 8749 if (!is_local)
8750 /* add r0,pc; ldr r0, [r0] */
8751 insn = 0x44786800;
8752 else if (arch_has_thumb2_nop (globals))
8753 /* nop.w */
8754 insn = 0xf3af8000;
8755 else
8756 /* nop; nop */
8757 insn = 0xbf00bf00;
b38cadfb 8758
0855e32b
NS		 8759 bfd_put_16 (input_bfd, insn >> 16, contents + rel->r_offset);
8760 bfd_put_16 (input_bfd, insn & 0xffff, contents + rel->r_offset + 2);
8761 break;
8762 }
8763 return bfd_reloc_ok;
8764}
8765
4962c51a
MS		 8766/* For a given value of n, calculate the value of G_n as required to
8767 deal with group relocations. We return it in the form of an
8768 encoded constant-and-rotation, together with the final residual. If n is
8769 specified as less than zero, then final_residual is filled with the
8770 input value and no further action is performed. */
8771
8772static bfd_vma
8773calculate_group_reloc_mask (bfd_vma value, int n, bfd_vma *final_residual)
8774{
8775 int current_n;
8776 bfd_vma g_n;
8777 bfd_vma encoded_g_n = 0;
8778 bfd_vma residual = value; /* Also known as Y_n. */
8779
8780 for (current_n = 0; current_n <= n; current_n++)
8781 {
8782 int shift;
8783
8784 /* Calculate which part of the value to mask. */
8785 if (residual == 0)
99059e56 8786 shift = 0;
4962c51a 8787 else
99059e56
RM		 8788 {
8789 int msb;
8790
8791 /* Determine the most significant bit in the residual and
8792 align the resulting value to a 2-bit boundary. */
8793 for (msb = 30; msb >= 0; msb -= 2)
8794 if (residual & (3 << msb))
8795 break;
8796
8797 /* The desired shift is now (msb - 6), or zero, whichever
8798 is the greater. */
8799 shift = msb - 6;
8800 if (shift < 0)
8801 shift = 0;
8802 }
4962c51a
MS		 8803
8804 /* Calculate g_n in 32-bit as well as encoded constant+rotation form. */
8805 g_n = residual & (0xff << shift);
8806 encoded_g_n = (g_n >> shift)
99059e56 8807 | ((g_n <= 0xff ? 0 : (32 - shift) / 2) << 8);
4962c51a
MS		 8808
8809 /* Calculate the residual for the next time around. */
8810 residual &= ~g_n;
8811 }
8812
8813 *final_residual = residual;
8814
8815 return encoded_g_n;
8816}
8817
8818/* Given an ARM instruction, determine whether it is an ADD or a SUB.
8819 Returns 1 if it is an ADD, -1 if it is a SUB, and 0 otherwise. */
906e58ca 8820
4962c51a 8821static int
906e58ca 8822identify_add_or_sub (bfd_vma insn)
4962c51a
MS		 8823{
8824 int opcode = insn & 0x1e00000;
8825
8826 if (opcode == 1 << 23) /* ADD */
8827 return 1;
8828
8829 if (opcode == 1 << 22) /* SUB */
8830 return -1;
8831
8832 return 0;
8833}
8834
252b5132 8835/* Perform a relocation as part of a final link. */
9b485d32 8836
252b5132 8837static bfd_reloc_status_type
57e8b36a
NC		 8838elf32_arm_final_link_relocate (reloc_howto_type * howto,
8839 bfd * input_bfd,
8840 bfd * output_bfd,
8841 asection * input_section,
8842 bfd_byte * contents,
8843 Elf_Internal_Rela * rel,
8844 bfd_vma value,
8845 struct bfd_link_info * info,
8846 asection * sym_sec,
8847 const char * sym_name,
34e77a92
RS		 8848 unsigned char st_type,
8849 enum arm_st_branch_type branch_type,
0945cdfd 8850 struct elf_link_hash_entry * h,
f2a9dd69 8851 bfd_boolean * unresolved_reloc_p,
8029a119 8852 char ** error_message)
252b5132
RH		 8853{
8854 unsigned long r_type = howto->type;
8855 unsigned long r_symndx;
8856 bfd_byte * hit_data = contents + rel->r_offset;
252b5132 8857 bfd_vma * local_got_offsets;
0855e32b 8858 bfd_vma * local_tlsdesc_gotents;
34e77a92
RS		 8859 asection * sgot;
8860 asection * splt;
252b5132 8861 asection * sreloc = NULL;
362d30a1 8862 asection * srelgot;
252b5132 8863 bfd_vma addend;
ba96a88f 8864 bfd_signed_vma signed_addend;
34e77a92
RS		 8865 unsigned char dynreloc_st_type;
8866 bfd_vma dynreloc_value;
ba96a88f 8867 struct elf32_arm_link_hash_table * globals;
34e77a92
RS		 8868 struct elf32_arm_link_hash_entry *eh;
8869 union gotplt_union *root_plt;
8870 struct arm_plt_info *arm_plt;
8871 bfd_vma plt_offset;
8872 bfd_vma gotplt_offset;
8873 bfd_boolean has_iplt_entry;
f21f3fe0 8874
9c504268 8875 globals = elf32_arm_hash_table (info);
4dfe6ac6
NC		 8876 if (globals == NULL)
8877 return bfd_reloc_notsupported;
9c504268 8878
0ffa91dd
NC		 8879 BFD_ASSERT (is_arm_elf (input_bfd));
8880
8881 /* Some relocation types map to different relocations depending on the
9c504268 8882 target. We pick the right one here. */
eb043451 8883 r_type = arm_real_reloc_type (globals, r_type);
0855e32b
NS		 8884
8885 /* It is possible to have linker relaxations on some TLS access
8886 models. Update our information here. */
8887 r_type = elf32_arm_tls_transition (info, r_type, h);
8888
eb043451
PB		 8889 if (r_type != howto->type)
8890 howto = elf32_arm_howto_from_type (r_type);
9c504268 8891
34e77a92 8892 eh = (struct elf32_arm_link_hash_entry *) h;
362d30a1 8893 sgot = globals->root.sgot;
252b5132 8894 local_got_offsets = elf_local_got_offsets (input_bfd);
0855e32b
NS		 8895 local_tlsdesc_gotents = elf32_arm_local_tlsdesc_gotent (input_bfd);
8896
34e77a92
RS		 8897 if (globals->root.dynamic_sections_created)
8898 srelgot = globals->root.srelgot;
8899 else
8900 srelgot = NULL;
8901
252b5132
RH		 8902 r_symndx = ELF32_R_SYM (rel->r_info);
8903
4e7fd91e 8904 if (globals->use_rel)
ba96a88f 8905 {
4e7fd91e
PB		 8906 addend = bfd_get_32 (input_bfd, hit_data) & howto->src_mask;
8907
8908 if (addend & ((howto->src_mask + 1) >> 1))
8909 {
8910 signed_addend = -1;
8911 signed_addend &= ~ howto->src_mask;
8912 signed_addend |= addend;
8913 }
8914 else
8915 signed_addend = addend;
ba96a88f
NC		 8916 }
8917 else
4e7fd91e 8918 addend = signed_addend = rel->r_addend;
f21f3fe0 8919
39f21624
NC		 8920 /* ST_BRANCH_TO_ARM is nonsense to thumb-only targets when we
8921 are resolving a function call relocation. */
8922 if (using_thumb_only (globals)
8923 && (r_type == R_ARM_THM_CALL
8924 || r_type == R_ARM_THM_JUMP24)
8925 && branch_type == ST_BRANCH_TO_ARM)
8926 branch_type = ST_BRANCH_TO_THUMB;
8927
34e77a92
RS		 8928 /* Record the symbol information that should be used in dynamic
8929 relocations. */
8930 dynreloc_st_type = st_type;
8931 dynreloc_value = value;
8932 if (branch_type == ST_BRANCH_TO_THUMB)
8933 dynreloc_value |= 1;
8934
8935 /* Find out whether the symbol has a PLT. Set ST_VALUE, BRANCH_TYPE and
8936 VALUE appropriately for relocations that we resolve at link time. */
8937 has_iplt_entry = FALSE;
8938 if (elf32_arm_get_plt_info (input_bfd, eh, r_symndx, &root_plt, &arm_plt)
8939 && root_plt->offset != (bfd_vma) -1)
8940 {
8941 plt_offset = root_plt->offset;
8942 gotplt_offset = arm_plt->got_offset;
8943
8944 if (h == NULL || eh->is_iplt)
8945 {
8946 has_iplt_entry = TRUE;
8947 splt = globals->root.iplt;
8948
8949 /* Populate .iplt entries here, because not all of them will
8950 be seen by finish_dynamic_symbol. The lower bit is set if
8951 we have already populated the entry. */
8952 if (plt_offset & 1)
8953 plt_offset--;
8954 else
8955 {
57460bcf
NC		 8956 if (elf32_arm_populate_plt_entry (output_bfd, info, root_plt, arm_plt,
8957 -1, dynreloc_value))
8958 root_plt->offset |= 1;
8959 else
8960 return bfd_reloc_notsupported;
34e77a92
RS		 8961 }
8962
8963 /* Static relocations always resolve to the .iplt entry. */
8964 st_type = STT_FUNC;
8965 value = (splt->output_section->vma
8966 + splt->output_offset
8967 + plt_offset);
8968 branch_type = ST_BRANCH_TO_ARM;
8969
8970 /* If there are non-call relocations that resolve to the .iplt
8971 entry, then all dynamic ones must too. */
8972 if (arm_plt->noncall_refcount != 0)
8973 {
8974 dynreloc_st_type = st_type;
8975 dynreloc_value = value;
8976 }
8977 }
8978 else
8979 /* We populate the .plt entry in finish_dynamic_symbol. */
8980 splt = globals->root.splt;
8981 }
8982 else
8983 {
8984 splt = NULL;
8985 plt_offset = (bfd_vma) -1;
8986 gotplt_offset = (bfd_vma) -1;
8987 }
8988
252b5132
RH		 8989 switch (r_type)
8990 {
8991 case R_ARM_NONE:
28a094c2
DJ		 8992 /* We don't need to find a value for this symbol. It's just a
8993 marker. */
8994 *unresolved_reloc_p = FALSE;
252b5132
RH		 8995 return bfd_reloc_ok;
8996
00a97672
RS		 8997 case R_ARM_ABS12:
8998 if (!globals->vxworks_p)
8999 return elf32_arm_abs12_reloc (input_bfd, hit_data, value + addend);
9000
252b5132
RH		 9001 case R_ARM_PC24:
9002 case R_ARM_ABS32:
bb224fc3 9003 case R_ARM_ABS32_NOI:
252b5132 9004 case R_ARM_REL32:
bb224fc3 9005 case R_ARM_REL32_NOI:
5b5bb741
PB		 9006 case R_ARM_CALL:
9007 case R_ARM_JUMP24:
dfc5f959 9008 case R_ARM_XPC25:
eb043451 9009 case R_ARM_PREL31:
7359ea65 9010 case R_ARM_PLT32:
7359ea65
DJ		 9011 /* Handle relocations which should use the PLT entry. ABS32/REL32
9012 will use the symbol's value, which may point to a PLT entry, but we
9013 don't need to handle that here. If we created a PLT entry, all
5fa9e92f
CL		 9014 branches in this object should go to it, except if the PLT is too
9015 far away, in which case a long branch stub should be inserted. */
bb224fc3 9016 if ((r_type != R_ARM_ABS32 && r_type != R_ARM_REL32
99059e56 9017 && r_type != R_ARM_ABS32_NOI && r_type != R_ARM_REL32_NOI
155d87d7
CL		 9018 && r_type != R_ARM_CALL
9019 && r_type != R_ARM_JUMP24
9020 && r_type != R_ARM_PLT32)
34e77a92 9021 && plt_offset != (bfd_vma) -1)
7359ea65 9022 {
34e77a92
RS		 9023 /* If we've created a .plt section, and assigned a PLT entry
9024 to this function, it must either be a STT_GNU_IFUNC reference
9025 or not be known to bind locally. In other cases, we should
9026 have cleared the PLT entry by now. */
9027 BFD_ASSERT (has_iplt_entry || !SYMBOL_CALLS_LOCAL (info, h));
7359ea65
DJ		 9028
9029 value = (splt->output_section->vma
9030 + splt->output_offset
34e77a92 9031 + plt_offset);
0945cdfd 9032 *unresolved_reloc_p = FALSE;
7359ea65
DJ		 9033 return _bfd_final_link_relocate (howto, input_bfd, input_section,
9034 contents, rel->r_offset, value,
00a97672 9035 rel->r_addend);
7359ea65
DJ		 9036 }
9037
67687978
PB		 9038 /* When generating a shared object or relocatable executable, these
9039 relocations are copied into the output file to be resolved at
9040 run time. */
0e1862bb
L		 9041 if ((bfd_link_pic (info)
9042 || globals->root.is_relocatable_executable)
7359ea65 9043 && (input_section->flags & SEC_ALLOC)
4dfe6ac6 9044 && !(globals->vxworks_p
3348747a
NS		 9045 && strcmp (input_section->output_section->name,
9046 ".tls_vars") == 0)
bb224fc3 9047 && ((r_type != R_ARM_REL32 && r_type != R_ARM_REL32_NOI)
ee06dc07 9048 || !SYMBOL_CALLS_LOCAL (info, h))
ca6b5f82
AM		 9049 && !(input_bfd == globals->stub_bfd
9050 && strstr (input_section->name, STUB_SUFFIX))
7359ea65
DJ		 9051 && (h == NULL
9052 || ELF_ST_VISIBILITY (h->other) == STV_DEFAULT
9053 || h->root.type != bfd_link_hash_undefweak)
9054 && r_type != R_ARM_PC24
5b5bb741
PB		 9055 && r_type != R_ARM_CALL
9056 && r_type != R_ARM_JUMP24
ee06dc07 9057 && r_type != R_ARM_PREL31
7359ea65 9058 && r_type != R_ARM_PLT32)
252b5132 9059 {
947216bf 9060 Elf_Internal_Rela outrel;
b34976b6 9061 bfd_boolean skip, relocate;
f21f3fe0 9062
52db4ec2
JW		 9063 if ((r_type == R_ARM_REL32 || r_type == R_ARM_REL32_NOI)
9064 && !h->def_regular)
9065 {
9066 char *v = _("shared object");
9067
0e1862bb 9068 if (bfd_link_executable (info))
52db4ec2
JW		 9069 v = _("PIE executable");
9070
9071 (*_bfd_error_handler)
9072 (_("%B: relocation %s against external or undefined symbol `%s'"
9073 " can not be used when making a %s; recompile with -fPIC"), input_bfd,
9074 elf32_arm_howto_table_1[r_type].name, h->root.root.string, v);
9075 return bfd_reloc_notsupported;
9076 }
9077
0945cdfd
DJ		 9078 *unresolved_reloc_p = FALSE;
9079
34e77a92 9080 if (sreloc == NULL && globals->root.dynamic_sections_created)
252b5132 9081 {
83bac4b0
NC		 9082 sreloc = _bfd_elf_get_dynamic_reloc_section (input_bfd, input_section,
9083 ! globals->use_rel);
f21f3fe0 9084
83bac4b0 9085 if (sreloc == NULL)
252b5132 9086 return bfd_reloc_notsupported;
252b5132 9087 }
f21f3fe0 9088
b34976b6
AM		 9089 skip = FALSE;
9090 relocate = FALSE;
f21f3fe0 9091
00a97672 9092 outrel.r_addend = addend;
c629eae0
JJ		 9093 outrel.r_offset =
9094 _bfd_elf_section_offset (output_bfd, info, input_section,
9095 rel->r_offset);
9096 if (outrel.r_offset == (bfd_vma) -1)
b34976b6 9097 skip = TRUE;
0bb2d96a 9098 else if (outrel.r_offset == (bfd_vma) -2)
b34976b6 9099 skip = TRUE, relocate = TRUE;
252b5132
RH		 9100 outrel.r_offset += (input_section->output_section->vma
9101 + input_section->output_offset);
f21f3fe0 9102
252b5132 9103 if (skip)
0bb2d96a 9104 memset (&outrel, 0, sizeof outrel);
5e681ec4
PB		 9105 else if (h != NULL
9106 && h->dynindx != -1
0e1862bb 9107 && (!bfd_link_pic (info)
a496fbc8 9108 || !SYMBOLIC_BIND (info, h)
f5385ebf 9109 || !h->def_regular))
5e681ec4 9110 outrel.r_info = ELF32_R_INFO (h->dynindx, r_type);
252b5132
RH		 9111 else
9112 {
a16385dc
MM		 9113 int symbol;
9114
5e681ec4 9115 /* This symbol is local, or marked to become local. */
34e77a92 9116 BFD_ASSERT (r_type == R_ARM_ABS32 || r_type == R_ARM_ABS32_NOI);
a16385dc 9117 if (globals->symbian_p)
6366ff1e 9118 {
74541ad4
AM		 9119 asection *osec;
9120
6366ff1e
MM		 9121 /* On Symbian OS, the data segment and text segement
9122 can be relocated independently. Therefore, we
9123 must indicate the segment to which this
9124 relocation is relative. The BPABI allows us to
9125 use any symbol in the right segment; we just use
9126 the section symbol as it is convenient. (We
9127 cannot use the symbol given by "h" directly as it
74541ad4
AM		 9128 will not appear in the dynamic symbol table.)
9129
9130 Note that the dynamic linker ignores the section
9131 symbol value, so we don't subtract osec->vma
9132 from the emitted reloc addend. */
10dbd1f3 9133 if (sym_sec)
74541ad4 9134 osec = sym_sec->output_section;
10dbd1f3 9135 else
74541ad4
AM		 9136 osec = input_section->output_section;
9137 symbol = elf_section_data (osec)->dynindx;
9138 if (symbol == 0)
9139 {
9140 struct elf_link_hash_table *htab = elf_hash_table (info);
9141
9142 if ((osec->flags & SEC_READONLY) == 0
9143 && htab->data_index_section != NULL)
9144 osec = htab->data_index_section;
9145 else
9146 osec = htab->text_index_section;
9147 symbol = elf_section_data (osec)->dynindx;
9148 }
6366ff1e
MM		 9149 BFD_ASSERT (symbol != 0);
9150 }
a16385dc
MM		 9151 else
9152 /* On SVR4-ish systems, the dynamic loader cannot
9153 relocate the text and data segments independently,
9154 so the symbol does not matter. */
9155 symbol = 0;
34e77a92
RS		 9156 if (dynreloc_st_type == STT_GNU_IFUNC)
9157 /* We have an STT_GNU_IFUNC symbol that doesn't resolve
9158 to the .iplt entry. Instead, every non-call reference
9159 must use an R_ARM_IRELATIVE relocation to obtain the
9160 correct run-time address. */
9161 outrel.r_info = ELF32_R_INFO (symbol, R_ARM_IRELATIVE);
9162 else
9163 outrel.r_info = ELF32_R_INFO (symbol, R_ARM_RELATIVE);
00a97672
RS		 9164 if (globals->use_rel)
9165 relocate = TRUE;
9166 else
34e77a92 9167 outrel.r_addend += dynreloc_value;
252b5132 9168 }
f21f3fe0 9169
47beaa6a 9170 elf32_arm_add_dynreloc (output_bfd, info, sreloc, &outrel);
9a5aca8c 9171
f21f3fe0 9172 /* If this reloc is against an external symbol, we do not want to
252b5132 9173 fiddle with the addend. Otherwise, we need to include the symbol
9b485d32 9174 value so that it becomes an addend for the dynamic reloc. */
252b5132
RH		 9175 if (! relocate)
9176 return bfd_reloc_ok;
9a5aca8c 9177
f21f3fe0 9178 return _bfd_final_link_relocate (howto, input_bfd, input_section,
34e77a92
RS		 9179 contents, rel->r_offset,
9180 dynreloc_value, (bfd_vma) 0);
252b5132
RH		 9181 }
9182 else switch (r_type)
9183 {
00a97672
RS		 9184 case R_ARM_ABS12:
9185 return elf32_arm_abs12_reloc (input_bfd, hit_data, value + addend);
9186
dfc5f959 9187 case R_ARM_XPC25: /* Arm BLX instruction. */
5b5bb741
PB		 9188 case R_ARM_CALL:
9189 case R_ARM_JUMP24:
8029a119 9190 case R_ARM_PC24: /* Arm B/BL instruction. */
7359ea65 9191 case R_ARM_PLT32:
906e58ca 9192 {
906e58ca
NC		 9193 struct elf32_arm_stub_hash_entry *stub_entry = NULL;
9194
dfc5f959 9195 if (r_type == R_ARM_XPC25)
252b5132 9196 {
dfc5f959
NC		 9197 /* Check for Arm calling Arm function. */
9198 /* FIXME: Should we translate the instruction into a BL
9199 instruction instead ? */
35fc36a8 9200 if (branch_type != ST_BRANCH_TO_THUMB)
d003868e
AM		 9201 (*_bfd_error_handler)
9202 (_("\%B: Warning: Arm BLX instruction targets Arm function '%s'."),
9203 input_bfd,
9204 h ? h->root.root.string : "(local)");
dfc5f959 9205 }
155d87d7 9206 else if (r_type == R_ARM_PC24)
dfc5f959
NC		 9207 {
9208 /* Check for Arm calling Thumb function. */
35fc36a8 9209 if (branch_type == ST_BRANCH_TO_THUMB)
dfc5f959 9210 {
f2a9dd69
DJ		 9211 if (elf32_arm_to_thumb_stub (info, sym_name, input_bfd,
9212 output_bfd, input_section,
9213 hit_data, sym_sec, rel->r_offset,
9214 signed_addend, value,
9215 error_message))
9216 return bfd_reloc_ok;
9217 else
9218 return bfd_reloc_dangerous;
dfc5f959 9219 }
252b5132 9220 }
ba96a88f 9221
906e58ca 9222 /* Check if a stub has to be inserted because the
8029a119 9223 destination is too far or we are changing mode. */
155d87d7
CL		 9224 if ( r_type == R_ARM_CALL
9225 || r_type == R_ARM_JUMP24
9226 || r_type == R_ARM_PLT32)
906e58ca 9227 {
fe33d2fa
CL		 9228 enum elf32_arm_stub_type stub_type = arm_stub_none;
9229 struct elf32_arm_link_hash_entry *hash;
9230
9231 hash = (struct elf32_arm_link_hash_entry *) h;
9232 stub_type = arm_type_of_stub (info, input_section, rel,
34e77a92
RS		 9233 st_type, &branch_type,
9234 hash, value, sym_sec,
fe33d2fa 9235 input_bfd, sym_name);
5fa9e92f 9236
fe33d2fa 9237 if (stub_type != arm_stub_none)
906e58ca
NC		 9238 {
9239 /* The target is out of reach, so redirect the
9240 branch to the local stub for this function. */
906e58ca
NC		 9241 stub_entry = elf32_arm_get_stub_entry (input_section,
9242 sym_sec, h,
fe33d2fa
CL		 9243 rel, globals,
9244 stub_type);
9cd3e4e5
NC		 9245 {
9246 if (stub_entry != NULL)
9247 value = (stub_entry->stub_offset
9248 + stub_entry->stub_sec->output_offset
9249 + stub_entry->stub_sec->output_section->vma);
9250
9251 if (plt_offset != (bfd_vma) -1)
9252 *unresolved_reloc_p = FALSE;
9253 }
906e58ca 9254 }
fe33d2fa
CL		 9255 else
9256 {
9257 /* If the call goes through a PLT entry, make sure to
9258 check distance to the right destination address. */
34e77a92 9259 if (plt_offset != (bfd_vma) -1)
fe33d2fa
CL		 9260 {
9261 value = (splt->output_section->vma
9262 + splt->output_offset
34e77a92 9263 + plt_offset);
fe33d2fa
CL		 9264 *unresolved_reloc_p = FALSE;
9265 /* The PLT entry is in ARM mode, regardless of the
9266 target function. */
35fc36a8 9267 branch_type = ST_BRANCH_TO_ARM;
fe33d2fa
CL		 9268 }
9269 }
906e58ca
NC		 9270 }
9271
dea514f5
PB		 9272 /* The ARM ELF ABI says that this reloc is computed as: S - P + A
9273 where:
9274 S is the address of the symbol in the relocation.
9275 P is address of the instruction being relocated.
9276 A is the addend (extracted from the instruction) in bytes.
9277
9278 S is held in 'value'.
9279 P is the base address of the section containing the
9280 instruction plus the offset of the reloc into that
9281 section, ie:
9282 (input_section->output_section->vma +
9283 input_section->output_offset +
9284 rel->r_offset).
9285 A is the addend, converted into bytes, ie:
9286 (signed_addend * 4)
9287
9288 Note: None of these operations have knowledge of the pipeline
9289 size of the processor, thus it is up to the assembler to
9290 encode this information into the addend. */
9291 value -= (input_section->output_section->vma
9292 + input_section->output_offset);
9293 value -= rel->r_offset;
4e7fd91e
PB		 9294 if (globals->use_rel)
9295 value += (signed_addend << howto->size);
9296 else
9297 /* RELA addends do not have to be adjusted by howto->size. */
9298 value += signed_addend;
23080146 9299
dcb5e6e6
NC		 9300 signed_addend = value;
9301 signed_addend >>= howto->rightshift;
9a5aca8c 9302
5ab79981 9303 /* A branch to an undefined weak symbol is turned into a jump to
ffcb4889 9304 the next instruction unless a PLT entry will be created.
77b4f08f 9305 Do the same for local undefined symbols (but not for STN_UNDEF).
cd1dac3d
DG		 9306 The jump to the next instruction is optimized as a NOP depending
9307 on the architecture. */
ffcb4889 9308 if (h ? (h->root.type == bfd_link_hash_undefweak
34e77a92 9309 && plt_offset == (bfd_vma) -1)
77b4f08f 9310 : r_symndx != STN_UNDEF && bfd_is_und_section (sym_sec))
5ab79981 9311 {
cd1dac3d
DG		 9312 value = (bfd_get_32 (input_bfd, hit_data) & 0xf0000000);
9313
9314 if (arch_has_arm_nop (globals))
9315 value |= 0x0320f000;
9316 else
9317 value |= 0x01a00000; /* Using pre-UAL nop: mov r0, r0. */
5ab79981
PB		 9318 }
9319 else
59f2c4e7 9320 {
9b485d32 9321 /* Perform a signed range check. */
dcb5e6e6 9322 if ( signed_addend > ((bfd_signed_vma) (howto->dst_mask >> 1))
59f2c4e7
NC		 9323 || signed_addend < - ((bfd_signed_vma) ((howto->dst_mask + 1) >> 1)))
9324 return bfd_reloc_overflow;
9a5aca8c 9325
5ab79981 9326 addend = (value & 2);
39b41c9c 9327
5ab79981
PB		 9328 value = (signed_addend & howto->dst_mask)
9329 | (bfd_get_32 (input_bfd, hit_data) & (~ howto->dst_mask));
39b41c9c 9330
5ab79981
PB		 9331 if (r_type == R_ARM_CALL)
9332 {
155d87d7 9333 /* Set the H bit in the BLX instruction. */
35fc36a8 9334 if (branch_type == ST_BRANCH_TO_THUMB)
155d87d7
CL		 9335 {
9336 if (addend)
9337 value |= (1 << 24);
9338 else
9339 value &= ~(bfd_vma)(1 << 24);
9340 }
9341
5ab79981 9342 /* Select the correct instruction (BL or BLX). */
906e58ca 9343 /* Only if we are not handling a BL to a stub. In this
8029a119 9344 case, mode switching is performed by the stub. */
35fc36a8 9345 if (branch_type == ST_BRANCH_TO_THUMB && !stub_entry)
5ab79981 9346 value |= (1 << 28);
63e1a0fc 9347 else if (stub_entry || branch_type != ST_BRANCH_UNKNOWN)
5ab79981
PB		 9348 {
9349 value &= ~(bfd_vma)(1 << 28);
9350 value |= (1 << 24);
9351 }
39b41c9c
PB		 9352 }
9353 }
906e58ca 9354 }
252b5132 9355 break;
f21f3fe0 9356
252b5132
RH		 9357 case R_ARM_ABS32:
9358 value += addend;
35fc36a8 9359 if (branch_type == ST_BRANCH_TO_THUMB)
252b5132
RH		 9360 value |= 1;
9361 break;
f21f3fe0 9362
bb224fc3
MS		 9363 case R_ARM_ABS32_NOI:
9364 value += addend;
9365 break;
9366
252b5132 9367 case R_ARM_REL32:
a8bc6c78 9368 value += addend;
35fc36a8 9369 if (branch_type == ST_BRANCH_TO_THUMB)
a8bc6c78 9370 value |= 1;
252b5132 9371 value -= (input_section->output_section->vma
62efb346 9372 + input_section->output_offset + rel->r_offset);
252b5132 9373 break;
eb043451 9374
bb224fc3
MS		 9375 case R_ARM_REL32_NOI:
9376 value += addend;
9377 value -= (input_section->output_section->vma
9378 + input_section->output_offset + rel->r_offset);
9379 break;
9380
eb043451
PB		 9381 case R_ARM_PREL31:
9382 value -= (input_section->output_section->vma
9383 + input_section->output_offset + rel->r_offset);
9384 value += signed_addend;
9385 if (! h || h->root.type != bfd_link_hash_undefweak)
9386 {
8029a119 9387 /* Check for overflow. */
eb043451
PB		 9388 if ((value ^ (value >> 1)) & (1 << 30))
9389 return bfd_reloc_overflow;
9390 }
9391 value &= 0x7fffffff;
9392 value |= (bfd_get_32 (input_bfd, hit_data) & 0x80000000);
35fc36a8 9393 if (branch_type == ST_BRANCH_TO_THUMB)
eb043451
PB		 9394 value |= 1;
9395 break;
252b5132 9396 }
f21f3fe0 9397
252b5132
RH		 9398 bfd_put_32 (input_bfd, value, hit_data);
9399 return bfd_reloc_ok;
9400
9401 case R_ARM_ABS8:
fd0fd00c
MJ		 9402 /* PR 16202: Refectch the addend using the correct size. */
9403 if (globals->use_rel)
9404 addend = bfd_get_8 (input_bfd, hit_data);
252b5132 9405 value += addend;
4e67d4ca
DG		 9406
9407 /* There is no way to tell whether the user intended to use a signed or
9408 unsigned addend. When checking for overflow we accept either,
9409 as specified by the AAELF. */
9410 if ((long) value > 0xff || (long) value < -0x80)
252b5132
RH		 9411 return bfd_reloc_overflow;
9412
9413 bfd_put_8 (input_bfd, value, hit_data);
9414 return bfd_reloc_ok;
9415
9416 case R_ARM_ABS16:
fd0fd00c
MJ		 9417 /* PR 16202: Refectch the addend using the correct size. */
9418 if (globals->use_rel)
9419 addend = bfd_get_16 (input_bfd, hit_data);
252b5132
RH		 9420 value += addend;
9421
4e67d4ca
DG		 9422 /* See comment for R_ARM_ABS8. */
9423 if ((long) value > 0xffff || (long) value < -0x8000)
252b5132
RH		 9424 return bfd_reloc_overflow;
9425
9426 bfd_put_16 (input_bfd, value, hit_data);
9427 return bfd_reloc_ok;
9428
252b5132 9429 case R_ARM_THM_ABS5:
9b485d32 9430 /* Support ldr and str instructions for the thumb. */
4e7fd91e
PB		 9431 if (globals->use_rel)
9432 {
9433 /* Need to refetch addend. */
9434 addend = bfd_get_16 (input_bfd, hit_data) & howto->src_mask;
9435 /* ??? Need to determine shift amount from operand size. */
9436 addend >>= howto->rightshift;
9437 }
252b5132
RH		 9438 value += addend;
9439
9440 /* ??? Isn't value unsigned? */
9441 if ((long) value > 0x1f || (long) value < -0x10)
9442 return bfd_reloc_overflow;
9443
9444 /* ??? Value needs to be properly shifted into place first. */
9445 value |= bfd_get_16 (input_bfd, hit_data) & 0xf83f;
9446 bfd_put_16 (input_bfd, value, hit_data);
9447 return bfd_reloc_ok;
9448
2cab6cc3
MS		 9449 case R_ARM_THM_ALU_PREL_11_0:
9450 /* Corresponds to: addw.w reg, pc, #offset (and similarly for subw). */
9451 {
9452 bfd_vma insn;
9453 bfd_signed_vma relocation;
9454
9455 insn = (bfd_get_16 (input_bfd, hit_data) << 16)
99059e56 9456 | bfd_get_16 (input_bfd, hit_data + 2);
2cab6cc3 9457
99059e56
RM		 9458 if (globals->use_rel)
9459 {
9460 signed_addend = (insn & 0xff) | ((insn & 0x7000) >> 4)
9461 | ((insn & (1 << 26)) >> 15);
9462 if (insn & 0xf00000)
9463 signed_addend = -signed_addend;
9464 }
2cab6cc3
MS		 9465
9466 relocation = value + signed_addend;
79f08007 9467 relocation -= Pa (input_section->output_section->vma
99059e56
RM		 9468 + input_section->output_offset
9469 + rel->r_offset);
2cab6cc3 9470
b6518b38 9471 value = relocation;
2cab6cc3 9472
99059e56
RM		 9473 if (value >= 0x1000)
9474 return bfd_reloc_overflow;
2cab6cc3
MS		 9475
9476 insn = (insn & 0xfb0f8f00) | (value & 0xff)
99059e56
RM		 9477 | ((value & 0x700) << 4)
9478 | ((value & 0x800) << 15);
9479 if (relocation < 0)
9480 insn |= 0xa00000;
2cab6cc3
MS		 9481
9482 bfd_put_16 (input_bfd, insn >> 16, hit_data);
9483 bfd_put_16 (input_bfd, insn & 0xffff, hit_data + 2);
9484
99059e56 9485 return bfd_reloc_ok;
2cab6cc3
MS		 9486 }
9487
e1ec24c6
NC		 9488 case R_ARM_THM_PC8:
9489 /* PR 10073: This reloc is not generated by the GNU toolchain,
9490 but it is supported for compatibility with third party libraries
9491 generated by other compilers, specifically the ARM/IAR. */
9492 {
9493 bfd_vma insn;
9494 bfd_signed_vma relocation;
9495
9496 insn = bfd_get_16 (input_bfd, hit_data);
9497
99059e56 9498 if (globals->use_rel)
79f08007 9499 addend = ((((insn & 0x00ff) << 2) + 4) & 0x3ff) -4;
e1ec24c6
NC		 9500
9501 relocation = value + addend;
79f08007 9502 relocation -= Pa (input_section->output_section->vma
99059e56
RM		 9503 + input_section->output_offset
9504 + rel->r_offset);
e1ec24c6 9505
b6518b38 9506 value = relocation;
e1ec24c6
NC		 9507
9508 /* We do not check for overflow of this reloc. Although strictly
9509 speaking this is incorrect, it appears to be necessary in order
9510 to work with IAR generated relocs. Since GCC and GAS do not
9511 generate R_ARM_THM_PC8 relocs, the lack of a check should not be
9512 a problem for them. */
9513 value &= 0x3fc;
9514
9515 insn = (insn & 0xff00) | (value >> 2);
9516
9517 bfd_put_16 (input_bfd, insn, hit_data);
9518
99059e56 9519 return bfd_reloc_ok;
e1ec24c6
NC		 9520 }
9521
2cab6cc3
MS		 9522 case R_ARM_THM_PC12:
9523 /* Corresponds to: ldr.w reg, [pc, #offset]. */
9524 {
9525 bfd_vma insn;
9526 bfd_signed_vma relocation;
9527
9528 insn = (bfd_get_16 (input_bfd, hit_data) << 16)
99059e56 9529 | bfd_get_16 (input_bfd, hit_data + 2);
2cab6cc3 9530
99059e56
RM		 9531 if (globals->use_rel)
9532 {
9533 signed_addend = insn & 0xfff;
9534 if (!(insn & (1 << 23)))
9535 signed_addend = -signed_addend;
9536 }
2cab6cc3
MS		 9537
9538 relocation = value + signed_addend;
79f08007 9539 relocation -= Pa (input_section->output_section->vma
99059e56
RM		 9540 + input_section->output_offset
9541 + rel->r_offset);
2cab6cc3 9542
b6518b38 9543 value = relocation;
2cab6cc3 9544
99059e56
RM		 9545 if (value >= 0x1000)
9546 return bfd_reloc_overflow;
2cab6cc3
MS		 9547
9548 insn = (insn & 0xff7ff000) | value;
99059e56
RM		 9549 if (relocation >= 0)
9550 insn |= (1 << 23);
2cab6cc3
MS		 9551
9552 bfd_put_16 (input_bfd, insn >> 16, hit_data);
9553 bfd_put_16 (input_bfd, insn & 0xffff, hit_data + 2);
9554
99059e56 9555 return bfd_reloc_ok;
2cab6cc3
MS		 9556 }
9557
dfc5f959 9558 case R_ARM_THM_XPC22:
c19d1205 9559 case R_ARM_THM_CALL:
bd97cb95 9560 case R_ARM_THM_JUMP24:
dfc5f959 9561 /* Thumb BL (branch long instruction). */
252b5132 9562 {
b34976b6 9563 bfd_vma relocation;
99059e56 9564 bfd_vma reloc_sign;
b34976b6
AM		 9565 bfd_boolean overflow = FALSE;
9566 bfd_vma upper_insn = bfd_get_16 (input_bfd, hit_data);
9567 bfd_vma lower_insn = bfd_get_16 (input_bfd, hit_data + 2);
e95de063
MS		 9568 bfd_signed_vma reloc_signed_max;
9569 bfd_signed_vma reloc_signed_min;
b34976b6 9570 bfd_vma check;
252b5132 9571 bfd_signed_vma signed_check;
e95de063 9572 int bitsize;
cd1dac3d 9573 const int thumb2 = using_thumb2 (globals);
252b5132 9574
5ab79981 9575 /* A branch to an undefined weak symbol is turned into a jump to
cd1dac3d
DG		 9576 the next instruction unless a PLT entry will be created.
9577 The jump to the next instruction is optimized as a NOP.W for
9578 Thumb-2 enabled architectures. */
19540007 9579 if (h && h->root.type == bfd_link_hash_undefweak
34e77a92 9580 && plt_offset == (bfd_vma) -1)
5ab79981 9581 {
cd1dac3d
DG		 9582 if (arch_has_thumb2_nop (globals))
9583 {
9584 bfd_put_16 (input_bfd, 0xf3af, hit_data);
9585 bfd_put_16 (input_bfd, 0x8000, hit_data + 2);
9586 }
9587 else
9588 {
9589 bfd_put_16 (input_bfd, 0xe000, hit_data);
9590 bfd_put_16 (input_bfd, 0xbf00, hit_data + 2);
9591 }
5ab79981
PB		 9592 return bfd_reloc_ok;
9593 }
9594
e95de063 9595 /* Fetch the addend. We use the Thumb-2 encoding (backwards compatible
99059e56 9596 with Thumb-1) involving the J1 and J2 bits. */
4e7fd91e
PB		 9597 if (globals->use_rel)
9598 {
99059e56
RM		 9599 bfd_vma s = (upper_insn & (1 << 10)) >> 10;
9600 bfd_vma upper = upper_insn & 0x3ff;
9601 bfd_vma lower = lower_insn & 0x7ff;
e95de063
MS		 9602 bfd_vma j1 = (lower_insn & (1 << 13)) >> 13;
9603 bfd_vma j2 = (lower_insn & (1 << 11)) >> 11;
99059e56
RM		 9604 bfd_vma i1 = j1 ^ s ? 0 : 1;
9605 bfd_vma i2 = j2 ^ s ? 0 : 1;
e95de063 9606
99059e56
RM		 9607 addend = (i1 << 23) | (i2 << 22) | (upper << 12) | (lower << 1);
9608 /* Sign extend. */
9609 addend = (addend | ((s ? 0 : 1) << 24)) - (1 << 24);
e95de063 9610
4e7fd91e
PB		 9611 signed_addend = addend;
9612 }
cb1afa5c 9613
dfc5f959
NC		 9614 if (r_type == R_ARM_THM_XPC22)
9615 {
9616 /* Check for Thumb to Thumb call. */
9617 /* FIXME: Should we translate the instruction into a BL
9618 instruction instead ? */
35fc36a8 9619 if (branch_type == ST_BRANCH_TO_THUMB)
d003868e
AM		 9620 (*_bfd_error_handler)
9621 (_("%B: Warning: Thumb BLX instruction targets thumb function '%s'."),
9622 input_bfd,
9623 h ? h->root.root.string : "(local)");
dfc5f959
NC		 9624 }
9625 else
252b5132 9626 {
dfc5f959
NC		 9627 /* If it is not a call to Thumb, assume call to Arm.
9628 If it is a call relative to a section name, then it is not a
b7693d02
DJ		 9629 function call at all, but rather a long jump. Calls through
9630 the PLT do not require stubs. */
34e77a92 9631 if (branch_type == ST_BRANCH_TO_ARM && plt_offset == (bfd_vma) -1)
dfc5f959 9632 {
bd97cb95 9633 if (globals->use_blx && r_type == R_ARM_THM_CALL)
39b41c9c
PB		 9634 {
9635 /* Convert BL to BLX. */
9636 lower_insn = (lower_insn & ~0x1000) | 0x0800;
9637 }
155d87d7
CL		 9638 else if (( r_type != R_ARM_THM_CALL)
9639 && (r_type != R_ARM_THM_JUMP24))
8029a119
NC		 9640 {
9641 if (elf32_thumb_to_arm_stub
9642 (info, sym_name, input_bfd, output_bfd, input_section,
9643 hit_data, sym_sec, rel->r_offset, signed_addend, value,
9644 error_message))
9645 return bfd_reloc_ok;
9646 else
9647 return bfd_reloc_dangerous;
9648 }
da5938a2 9649 }
35fc36a8
RS		 9650 else if (branch_type == ST_BRANCH_TO_THUMB
9651 && globals->use_blx
bd97cb95 9652 && r_type == R_ARM_THM_CALL)
39b41c9c
PB		 9653 {
9654 /* Make sure this is a BL. */
9655 lower_insn |= 0x1800;
9656 }
252b5132 9657 }
f21f3fe0 9658
fe33d2fa 9659 enum elf32_arm_stub_type stub_type = arm_stub_none;
155d87d7 9660 if (r_type == R_ARM_THM_CALL || r_type == R_ARM_THM_JUMP24)
906e58ca
NC		 9661 {
9662 /* Check if a stub has to be inserted because the destination
8029a119 9663 is too far. */
fe33d2fa
CL		 9664 struct elf32_arm_stub_hash_entry *stub_entry;
9665 struct elf32_arm_link_hash_entry *hash;
9666
9667 hash = (struct elf32_arm_link_hash_entry *) h;
9668
9669 stub_type = arm_type_of_stub (info, input_section, rel,
34e77a92
RS		 9670 st_type, &branch_type,
9671 hash, value, sym_sec,
fe33d2fa
CL		 9672 input_bfd, sym_name);
9673
9674 if (stub_type != arm_stub_none)
906e58ca
NC		 9675 {
9676 /* The target is out of reach or we are changing modes, so
9677 redirect the branch to the local stub for this
9678 function. */
9679 stub_entry = elf32_arm_get_stub_entry (input_section,
9680 sym_sec, h,
fe33d2fa
CL		 9681 rel, globals,
9682 stub_type);
906e58ca 9683 if (stub_entry != NULL)
9cd3e4e5
NC		 9684 {
9685 value = (stub_entry->stub_offset
9686 + stub_entry->stub_sec->output_offset
9687 + stub_entry->stub_sec->output_section->vma);
9688
9689 if (plt_offset != (bfd_vma) -1)
9690 *unresolved_reloc_p = FALSE;
9691 }
906e58ca 9692
f4ac8484 9693 /* If this call becomes a call to Arm, force BLX. */
155d87d7 9694 if (globals->use_blx && (r_type == R_ARM_THM_CALL))
f4ac8484
DJ		 9695 {
9696 if ((stub_entry
9697 && !arm_stub_is_thumb (stub_entry->stub_type))
35fc36a8 9698 || branch_type != ST_BRANCH_TO_THUMB)
f4ac8484
DJ		 9699 lower_insn = (lower_insn & ~0x1000) | 0x0800;
9700 }
906e58ca
NC		 9701 }
9702 }
9703
fe33d2fa 9704 /* Handle calls via the PLT. */
34e77a92 9705 if (stub_type == arm_stub_none && plt_offset != (bfd_vma) -1)
fe33d2fa
CL		 9706 {
9707 value = (splt->output_section->vma
9708 + splt->output_offset
34e77a92 9709 + plt_offset);
fe33d2fa 9710
eed94f8f
NC		 9711 if (globals->use_blx
9712 && r_type == R_ARM_THM_CALL
9713 && ! using_thumb_only (globals))
fe33d2fa
CL		 9714 {
9715 /* If the Thumb BLX instruction is available, convert
9716 the BL to a BLX instruction to call the ARM-mode
9717 PLT entry. */
9718 lower_insn = (lower_insn & ~0x1000) | 0x0800;
35fc36a8 9719 branch_type = ST_BRANCH_TO_ARM;
fe33d2fa
CL		 9720 }
9721 else
9722 {
eed94f8f
NC		 9723 if (! using_thumb_only (globals))
9724 /* Target the Thumb stub before the ARM PLT entry. */
9725 value -= PLT_THUMB_STUB_SIZE;
35fc36a8 9726 branch_type = ST_BRANCH_TO_THUMB;
fe33d2fa
CL		 9727 }
9728 *unresolved_reloc_p = FALSE;
9729 }
9730
ba96a88f 9731 relocation = value + signed_addend;
f21f3fe0 9732
252b5132 9733 relocation -= (input_section->output_section->vma
ba96a88f
NC		 9734 + input_section->output_offset
9735 + rel->r_offset);
9a5aca8c 9736
252b5132
RH		 9737 check = relocation >> howto->rightshift;
9738
9739 /* If this is a signed value, the rightshift just dropped
9740 leading 1 bits (assuming twos complement). */
9741 if ((bfd_signed_vma) relocation >= 0)
9742 signed_check = check;
9743 else
9744 signed_check = check | ~((bfd_vma) -1 >> howto->rightshift);
9745
e95de063
MS		 9746 /* Calculate the permissable maximum and minimum values for
9747 this relocation according to whether we're relocating for
9748 Thumb-2 or not. */
9749 bitsize = howto->bitsize;
9750 if (!thumb2)
9751 bitsize -= 2;
f6ebfac0 9752 reloc_signed_max = (1 << (bitsize - 1)) - 1;
e95de063
MS		 9753 reloc_signed_min = ~reloc_signed_max;
9754
252b5132 9755 /* Assumes two's complement. */
ba96a88f 9756 if (signed_check > reloc_signed_max || signed_check < reloc_signed_min)
b34976b6 9757 overflow = TRUE;
252b5132 9758
bd97cb95 9759 if ((lower_insn & 0x5000) == 0x4000)
c62e1cc3
NC		 9760 /* For a BLX instruction, make sure that the relocation is rounded up
9761 to a word boundary. This follows the semantics of the instruction
9762 which specifies that bit 1 of the target address will come from bit
9763 1 of the base address. */
9764 relocation = (relocation + 2) & ~ 3;
cb1afa5c 9765
e95de063
MS		 9766 /* Put RELOCATION back into the insn. Assumes two's complement.
9767 We use the Thumb-2 encoding, which is safe even if dealing with
9768 a Thumb-1 instruction by virtue of our overflow check above. */
99059e56 9769 reloc_sign = (signed_check < 0) ? 1 : 0;
e95de063 9770 upper_insn = (upper_insn & ~(bfd_vma) 0x7ff)
99059e56
RM		 9771 | ((relocation >> 12) & 0x3ff)
9772 | (reloc_sign << 10);
906e58ca 9773 lower_insn = (lower_insn & ~(bfd_vma) 0x2fff)
99059e56
RM		 9774 | (((!((relocation >> 23) & 1)) ^ reloc_sign) << 13)
9775 | (((!((relocation >> 22) & 1)) ^ reloc_sign) << 11)
9776 | ((relocation >> 1) & 0x7ff);
c62e1cc3 9777
252b5132
RH		 9778 /* Put the relocated value back in the object file: */
9779 bfd_put_16 (input_bfd, upper_insn, hit_data);
9780 bfd_put_16 (input_bfd, lower_insn, hit_data + 2);
9781
9782 return (overflow ? bfd_reloc_overflow : bfd_reloc_ok);
9783 }
9784 break;
9785
c19d1205
ZW		 9786 case R_ARM_THM_JUMP19:
9787 /* Thumb32 conditional branch instruction. */
9788 {
9789 bfd_vma relocation;
9790 bfd_boolean overflow = FALSE;
9791 bfd_vma upper_insn = bfd_get_16 (input_bfd, hit_data);
9792 bfd_vma lower_insn = bfd_get_16 (input_bfd, hit_data + 2);
a00a1f35
MS		 9793 bfd_signed_vma reloc_signed_max = 0xffffe;
9794 bfd_signed_vma reloc_signed_min = -0x100000;
c19d1205 9795 bfd_signed_vma signed_check;
c5423981
TG		 9796 enum elf32_arm_stub_type stub_type = arm_stub_none;
9797 struct elf32_arm_stub_hash_entry *stub_entry;
9798 struct elf32_arm_link_hash_entry *hash;
c19d1205
ZW		 9799
9800 /* Need to refetch the addend, reconstruct the top three bits,
9801 and squish the two 11 bit pieces together. */
9802 if (globals->use_rel)
9803 {
9804 bfd_vma S = (upper_insn & 0x0400) >> 10;
a00a1f35 9805 bfd_vma upper = (upper_insn & 0x003f);
c19d1205
ZW		 9806 bfd_vma J1 = (lower_insn & 0x2000) >> 13;
9807 bfd_vma J2 = (lower_insn & 0x0800) >> 11;
9808 bfd_vma lower = (lower_insn & 0x07ff);
9809
a00a1f35
MS		 9810 upper |= J1 << 6;
9811 upper |= J2 << 7;
9812 upper |= (!S) << 8;
c19d1205
ZW		 9813 upper -= 0x0100; /* Sign extend. */
9814
9815 addend = (upper << 12) | (lower << 1);
9816 signed_addend = addend;
9817 }
9818
bd97cb95 9819 /* Handle calls via the PLT. */
34e77a92 9820 if (plt_offset != (bfd_vma) -1)
bd97cb95
DJ		 9821 {
9822 value = (splt->output_section->vma
9823 + splt->output_offset
34e77a92 9824 + plt_offset);
bd97cb95
DJ		 9825 /* Target the Thumb stub before the ARM PLT entry. */
9826 value -= PLT_THUMB_STUB_SIZE;
9827 *unresolved_reloc_p = FALSE;
9828 }
9829
c5423981
TG		 9830 hash = (struct elf32_arm_link_hash_entry *)h;
9831
9832 stub_type = arm_type_of_stub (info, input_section, rel,
9833 st_type, &branch_type,
9834 hash, value, sym_sec,
9835 input_bfd, sym_name);
9836 if (stub_type != arm_stub_none)
9837 {
9838 stub_entry = elf32_arm_get_stub_entry (input_section,
9839 sym_sec, h,
9840 rel, globals,
9841 stub_type);
9842 if (stub_entry != NULL)
9843 {
9844 value = (stub_entry->stub_offset
9845 + stub_entry->stub_sec->output_offset
9846 + stub_entry->stub_sec->output_section->vma);
9847 }
9848 }
c19d1205 9849
99059e56 9850 relocation = value + signed_addend;
c19d1205
ZW		 9851 relocation -= (input_section->output_section->vma
9852 + input_section->output_offset
9853 + rel->r_offset);
a00a1f35 9854 signed_check = (bfd_signed_vma) relocation;
c19d1205 9855
c19d1205
ZW		 9856 if (signed_check > reloc_signed_max || signed_check < reloc_signed_min)
9857 overflow = TRUE;
9858
9859 /* Put RELOCATION back into the insn. */
9860 {
9861 bfd_vma S = (relocation & 0x00100000) >> 20;
9862 bfd_vma J2 = (relocation & 0x00080000) >> 19;
9863 bfd_vma J1 = (relocation & 0x00040000) >> 18;
9864 bfd_vma hi = (relocation & 0x0003f000) >> 12;
9865 bfd_vma lo = (relocation & 0x00000ffe) >> 1;
9866
a00a1f35 9867 upper_insn = (upper_insn & 0xfbc0) | (S << 10) | hi;
c19d1205
ZW		 9868 lower_insn = (lower_insn & 0xd000) | (J1 << 13) | (J2 << 11) | lo;
9869 }
9870
9871 /* Put the relocated value back in the object file: */
9872 bfd_put_16 (input_bfd, upper_insn, hit_data);
9873 bfd_put_16 (input_bfd, lower_insn, hit_data + 2);
9874
9875 return (overflow ? bfd_reloc_overflow : bfd_reloc_ok);
9876 }
9877
9878 case R_ARM_THM_JUMP11:
9879 case R_ARM_THM_JUMP8:
9880 case R_ARM_THM_JUMP6:
51c5503b
NC		 9881 /* Thumb B (branch) instruction). */
9882 {
6cf9e9fe 9883 bfd_signed_vma relocation;
51c5503b
NC		 9884 bfd_signed_vma reloc_signed_max = (1 << (howto->bitsize - 1)) - 1;
9885 bfd_signed_vma reloc_signed_min = ~ reloc_signed_max;
51c5503b
NC		 9886 bfd_signed_vma signed_check;
9887
c19d1205
ZW		 9888 /* CZB cannot jump backward. */
9889 if (r_type == R_ARM_THM_JUMP6)
9890 reloc_signed_min = 0;
9891
4e7fd91e 9892 if (globals->use_rel)
6cf9e9fe 9893 {
4e7fd91e
PB		 9894 /* Need to refetch addend. */
9895 addend = bfd_get_16 (input_bfd, hit_data) & howto->src_mask;
9896 if (addend & ((howto->src_mask + 1) >> 1))
9897 {
9898 signed_addend = -1;
9899 signed_addend &= ~ howto->src_mask;
9900 signed_addend |= addend;
9901 }
9902 else
9903 signed_addend = addend;
9904 /* The value in the insn has been right shifted. We need to
9905 undo this, so that we can perform the address calculation
9906 in terms of bytes. */
9907 signed_addend <<= howto->rightshift;
6cf9e9fe 9908 }
6cf9e9fe 9909 relocation = value + signed_addend;
51c5503b
NC		 9910
9911 relocation -= (input_section->output_section->vma
9912 + input_section->output_offset
9913 + rel->r_offset);
9914
6cf9e9fe
NC		 9915 relocation >>= howto->rightshift;
9916 signed_check = relocation;
c19d1205
ZW		 9917
9918 if (r_type == R_ARM_THM_JUMP6)
9919 relocation = ((relocation & 0x0020) << 4) | ((relocation & 0x001f) << 3);
9920 else
9921 relocation &= howto->dst_mask;
51c5503b 9922 relocation |= (bfd_get_16 (input_bfd, hit_data) & (~ howto->dst_mask));
cedb70c5 9923
51c5503b
NC		 9924 bfd_put_16 (input_bfd, relocation, hit_data);
9925
9926 /* Assumes two's complement. */
9927 if (signed_check > reloc_signed_max || signed_check < reloc_signed_min)
9928 return bfd_reloc_overflow;
9929
9930 return bfd_reloc_ok;
9931 }
cedb70c5 9932
8375c36b
PB		 9933 case R_ARM_ALU_PCREL7_0:
9934 case R_ARM_ALU_PCREL15_8:
9935 case R_ARM_ALU_PCREL23_15:
9936 {
9937 bfd_vma insn;
9938 bfd_vma relocation;
9939
9940 insn = bfd_get_32 (input_bfd, hit_data);
4e7fd91e
PB		 9941 if (globals->use_rel)
9942 {
9943 /* Extract the addend. */
9944 addend = (insn & 0xff) << ((insn & 0xf00) >> 7);
9945 signed_addend = addend;
9946 }
8375c36b
PB		 9947 relocation = value + signed_addend;
9948
9949 relocation -= (input_section->output_section->vma
9950 + input_section->output_offset
9951 + rel->r_offset);
9952 insn = (insn & ~0xfff)
9953 | ((howto->bitpos << 7) & 0xf00)
9954 | ((relocation >> howto->bitpos) & 0xff);
9955 bfd_put_32 (input_bfd, value, hit_data);
9956 }
9957 return bfd_reloc_ok;
9958
252b5132
RH		 9959 case R_ARM_GNU_VTINHERIT:
9960 case R_ARM_GNU_VTENTRY:
9961 return bfd_reloc_ok;
9962
c19d1205 9963 case R_ARM_GOTOFF32:
252b5132 9964 /* Relocation is relative to the start of the
99059e56 9965 global offset table. */
252b5132
RH		 9966
9967 BFD_ASSERT (sgot != NULL);
9968 if (sgot == NULL)
99059e56 9969 return bfd_reloc_notsupported;
9a5aca8c 9970
cedb70c5 9971 /* If we are addressing a Thumb function, we need to adjust the
ee29b9fb
RE		 9972 address by one, so that attempts to call the function pointer will
9973 correctly interpret it as Thumb code. */
35fc36a8 9974 if (branch_type == ST_BRANCH_TO_THUMB)
ee29b9fb
RE		 9975 value += 1;
9976
252b5132 9977 /* Note that sgot->output_offset is not involved in this
99059e56
RM		 9978 calculation. We always want the start of .got. If we
9979 define _GLOBAL_OFFSET_TABLE in a different way, as is
9980 permitted by the ABI, we might have to change this
9981 calculation. */
252b5132 9982 value -= sgot->output_section->vma;
f21f3fe0 9983 return _bfd_final_link_relocate (howto, input_bfd, input_section,
99e4ae17 9984 contents, rel->r_offset, value,
00a97672 9985 rel->r_addend);
252b5132
RH		 9986
9987 case R_ARM_GOTPC:
a7c10850 9988 /* Use global offset table as symbol value. */
252b5132 9989 BFD_ASSERT (sgot != NULL);
f21f3fe0 9990
252b5132 9991 if (sgot == NULL)
99059e56 9992 return bfd_reloc_notsupported;
252b5132 9993
0945cdfd 9994 *unresolved_reloc_p = FALSE;
252b5132 9995 value = sgot->output_section->vma;
f21f3fe0 9996 return _bfd_final_link_relocate (howto, input_bfd, input_section,
99e4ae17 9997 contents, rel->r_offset, value,
00a97672 9998 rel->r_addend);
f21f3fe0 9999
252b5132 10000 case R_ARM_GOT32:
eb043451 10001 case R_ARM_GOT_PREL:
252b5132 10002 /* Relocation is to the entry for this symbol in the
99059e56 10003 global offset table. */
252b5132
RH		 10004 if (sgot == NULL)
10005 return bfd_reloc_notsupported;
f21f3fe0 10006
34e77a92
RS		 10007 if (dynreloc_st_type == STT_GNU_IFUNC
10008 && plt_offset != (bfd_vma) -1
10009 && (h == NULL || SYMBOL_REFERENCES_LOCAL (info, h)))
10010 {
10011 /* We have a relocation against a locally-binding STT_GNU_IFUNC
10012 symbol, and the relocation resolves directly to the runtime
10013 target rather than to the .iplt entry. This means that any
10014 .got entry would be the same value as the .igot.plt entry,
10015 so there's no point creating both. */
10016 sgot = globals->root.igotplt;
10017 value = sgot->output_offset + gotplt_offset;
10018 }
10019 else if (h != NULL)
252b5132
RH		 10020 {
10021 bfd_vma off;
f21f3fe0 10022
252b5132
RH		 10023 off = h->got.offset;
10024 BFD_ASSERT (off != (bfd_vma) -1);
b436d854 10025 if ((off & 1) != 0)
252b5132 10026 {
b436d854
RS		 10027 /* We have already processsed one GOT relocation against
10028 this symbol. */
10029 off &= ~1;
10030 if (globals->root.dynamic_sections_created
10031 && !SYMBOL_REFERENCES_LOCAL (info, h))
10032 *unresolved_reloc_p = FALSE;
10033 }
10034 else
10035 {
10036 Elf_Internal_Rela outrel;
10037
6f820c85 10038 if (h->dynindx != -1 && !SYMBOL_REFERENCES_LOCAL (info, h))
b436d854
RS		 10039 {
10040 /* If the symbol doesn't resolve locally in a static
10041 object, we have an undefined reference. If the
10042 symbol doesn't resolve locally in a dynamic object,
10043 it should be resolved by the dynamic linker. */
10044 if (globals->root.dynamic_sections_created)
10045 {
10046 outrel.r_info = ELF32_R_INFO (h->dynindx, R_ARM_GLOB_DAT);
10047 *unresolved_reloc_p = FALSE;
10048 }
10049 else
10050 outrel.r_info = 0;
10051 outrel.r_addend = 0;
10052 }
252b5132
RH		 10053 else
10054 {
34e77a92 10055 if (dynreloc_st_type == STT_GNU_IFUNC)
99059e56 10056 outrel.r_info = ELF32_R_INFO (0, R_ARM_IRELATIVE);
0e1862bb 10057 else if (bfd_link_pic (info) &&
31943882
WN		 10058 (ELF_ST_VISIBILITY (h->other) == STV_DEFAULT
10059 || h->root.type != bfd_link_hash_undefweak))
99059e56
RM		 10060 outrel.r_info = ELF32_R_INFO (0, R_ARM_RELATIVE);
10061 else
10062 outrel.r_info = 0;
34e77a92 10063 outrel.r_addend = dynreloc_value;
b436d854 10064 }
ee29b9fb 10065
b436d854
RS		 10066 /* The GOT entry is initialized to zero by default.
10067 See if we should install a different value. */
10068 if (outrel.r_addend != 0
10069 && (outrel.r_info == 0 || globals->use_rel))
10070 {
10071 bfd_put_32 (output_bfd, outrel.r_addend,
10072 sgot->contents + off);
10073 outrel.r_addend = 0;
252b5132 10074 }
f21f3fe0 10075
b436d854
RS		 10076 if (outrel.r_info != 0)
10077 {
10078 outrel.r_offset = (sgot->output_section->vma
10079 + sgot->output_offset
10080 + off);
10081 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
10082 }
10083 h->got.offset |= 1;
10084 }
252b5132
RH		 10085 value = sgot->output_offset + off;
10086 }
10087 else
10088 {
10089 bfd_vma off;
f21f3fe0 10090
252b5132
RH		 10091 BFD_ASSERT (local_got_offsets != NULL &&
10092 local_got_offsets[r_symndx] != (bfd_vma) -1);
f21f3fe0 10093
252b5132 10094 off = local_got_offsets[r_symndx];
f21f3fe0 10095
252b5132
RH		 10096 /* The offset must always be a multiple of 4. We use the
10097 least significant bit to record whether we have already
9b485d32 10098 generated the necessary reloc. */
252b5132
RH		 10099 if ((off & 1) != 0)
10100 off &= ~1;
10101 else
10102 {
00a97672 10103 if (globals->use_rel)
34e77a92 10104 bfd_put_32 (output_bfd, dynreloc_value, sgot->contents + off);
f21f3fe0 10105
0e1862bb 10106 if (bfd_link_pic (info) || dynreloc_st_type == STT_GNU_IFUNC)
252b5132 10107 {
947216bf 10108 Elf_Internal_Rela outrel;
f21f3fe0 10109
34e77a92 10110 outrel.r_addend = addend + dynreloc_value;
252b5132 10111 outrel.r_offset = (sgot->output_section->vma
f21f3fe0 10112 + sgot->output_offset
252b5132 10113 + off);
34e77a92 10114 if (dynreloc_st_type == STT_GNU_IFUNC)
99059e56 10115 outrel.r_info = ELF32_R_INFO (0, R_ARM_IRELATIVE);
34e77a92
RS		 10116 else
10117 outrel.r_info = ELF32_R_INFO (0, R_ARM_RELATIVE);
47beaa6a 10118 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
252b5132 10119 }
f21f3fe0 10120
252b5132
RH		 10121 local_got_offsets[r_symndx] |= 1;
10122 }
f21f3fe0 10123
252b5132
RH		 10124 value = sgot->output_offset + off;
10125 }
eb043451
PB		 10126 if (r_type != R_ARM_GOT32)
10127 value += sgot->output_section->vma;
9a5aca8c 10128
f21f3fe0 10129 return _bfd_final_link_relocate (howto, input_bfd, input_section,
99e4ae17 10130 contents, rel->r_offset, value,
00a97672 10131 rel->r_addend);
f21f3fe0 10132
ba93b8ac
DJ		 10133 case R_ARM_TLS_LDO32:
10134 value = value - dtpoff_base (info);
10135
10136 return _bfd_final_link_relocate (howto, input_bfd, input_section,
00a97672
RS		 10137 contents, rel->r_offset, value,
10138 rel->r_addend);
ba93b8ac
DJ		 10139
10140 case R_ARM_TLS_LDM32:
10141 {
10142 bfd_vma off;
10143
362d30a1 10144 if (sgot == NULL)
ba93b8ac
DJ		 10145 abort ();
10146
10147 off = globals->tls_ldm_got.offset;
10148
10149 if ((off & 1) != 0)
10150 off &= ~1;
10151 else
10152 {
10153 /* If we don't know the module number, create a relocation
10154 for it. */
0e1862bb 10155 if (bfd_link_pic (info))
ba93b8ac
DJ		 10156 {
10157 Elf_Internal_Rela outrel;
ba93b8ac 10158
362d30a1 10159 if (srelgot == NULL)
ba93b8ac
DJ		 10160 abort ();
10161
00a97672 10162 outrel.r_addend = 0;
362d30a1
RS		 10163 outrel.r_offset = (sgot->output_section->vma
10164 + sgot->output_offset + off);
ba93b8ac
DJ		 10165 outrel.r_info = ELF32_R_INFO (0, R_ARM_TLS_DTPMOD32);
10166
00a97672
RS		 10167 if (globals->use_rel)
10168 bfd_put_32 (output_bfd, outrel.r_addend,
362d30a1 10169 sgot->contents + off);
ba93b8ac 10170
47beaa6a 10171 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
ba93b8ac
DJ		 10172 }
10173 else
362d30a1 10174 bfd_put_32 (output_bfd, 1, sgot->contents + off);
ba93b8ac
DJ		 10175
10176 globals->tls_ldm_got.offset |= 1;
10177 }
10178
362d30a1 10179 value = sgot->output_section->vma + sgot->output_offset + off
ba93b8ac
DJ		 10180 - (input_section->output_section->vma + input_section->output_offset + rel->r_offset);
10181
10182 return _bfd_final_link_relocate (howto, input_bfd, input_section,
10183 contents, rel->r_offset, value,
00a97672 10184 rel->r_addend);
ba93b8ac
DJ		 10185 }
10186
0855e32b
NS		 10187 case R_ARM_TLS_CALL:
10188 case R_ARM_THM_TLS_CALL:
ba93b8ac
DJ		 10189 case R_ARM_TLS_GD32:
10190 case R_ARM_TLS_IE32:
0855e32b
NS		 10191 case R_ARM_TLS_GOTDESC:
10192 case R_ARM_TLS_DESCSEQ:
10193 case R_ARM_THM_TLS_DESCSEQ:
ba93b8ac 10194 {
0855e32b
NS		 10195 bfd_vma off, offplt;
10196 int indx = 0;
ba93b8ac
DJ		 10197 char tls_type;
10198
0855e32b 10199 BFD_ASSERT (sgot != NULL);
ba93b8ac 10200
ba93b8ac
DJ		 10201 if (h != NULL)
10202 {
10203 bfd_boolean dyn;
10204 dyn = globals->root.dynamic_sections_created;
0e1862bb
L		 10205 if (WILL_CALL_FINISH_DYNAMIC_SYMBOL (dyn,
10206 bfd_link_pic (info),
10207 h)
10208 && (!bfd_link_pic (info)
ba93b8ac
DJ		 10209 || !SYMBOL_REFERENCES_LOCAL (info, h)))
10210 {
10211 *unresolved_reloc_p = FALSE;
10212 indx = h->dynindx;
10213 }
10214 off = h->got.offset;
0855e32b 10215 offplt = elf32_arm_hash_entry (h)->tlsdesc_got;
ba93b8ac
DJ		 10216 tls_type = ((struct elf32_arm_link_hash_entry *) h)->tls_type;
10217 }
10218 else
10219 {
0855e32b 10220 BFD_ASSERT (local_got_offsets != NULL);
ba93b8ac 10221 off = local_got_offsets[r_symndx];
0855e32b 10222 offplt = local_tlsdesc_gotents[r_symndx];
ba93b8ac
DJ		 10223 tls_type = elf32_arm_local_got_tls_type (input_bfd)[r_symndx];
10224 }
10225
0855e32b 10226 /* Linker relaxations happens from one of the
b38cadfb 10227 R_ARM_{GOTDESC,CALL,DESCSEQ} relocations to IE or LE. */
0855e32b 10228 if (ELF32_R_TYPE(rel->r_info) != r_type)
b38cadfb 10229 tls_type = GOT_TLS_IE;
0855e32b
NS		 10230
10231 BFD_ASSERT (tls_type != GOT_UNKNOWN);
ba93b8ac
DJ		 10232
10233 if ((off & 1) != 0)
10234 off &= ~1;
10235 else
10236 {
10237 bfd_boolean need_relocs = FALSE;
10238 Elf_Internal_Rela outrel;
ba93b8ac
DJ		 10239 int cur_off = off;
10240
10241 /* The GOT entries have not been initialized yet. Do it
10242 now, and emit any relocations. If both an IE GOT and a
10243 GD GOT are necessary, we emit the GD first. */
10244
0e1862bb 10245 if ((bfd_link_pic (info) || indx != 0)
ba93b8ac
DJ		 10246 && (h == NULL
10247 || ELF_ST_VISIBILITY (h->other) == STV_DEFAULT
10248 || h->root.type != bfd_link_hash_undefweak))
10249 {
10250 need_relocs = TRUE;
0855e32b 10251 BFD_ASSERT (srelgot != NULL);
ba93b8ac
DJ		 10252 }
10253
0855e32b
NS		 10254 if (tls_type & GOT_TLS_GDESC)
10255 {
47beaa6a
RS		 10256 bfd_byte *loc;
10257
0855e32b
NS		 10258 /* We should have relaxed, unless this is an undefined
10259 weak symbol. */
10260 BFD_ASSERT ((h && (h->root.type == bfd_link_hash_undefweak))
0e1862bb 10261 || bfd_link_pic (info));
0855e32b 10262 BFD_ASSERT (globals->sgotplt_jump_table_size + offplt + 8
99059e56 10263 <= globals->root.sgotplt->size);
0855e32b
NS		 10264
10265 outrel.r_addend = 0;
10266 outrel.r_offset = (globals->root.sgotplt->output_section->vma
10267 + globals->root.sgotplt->output_offset
10268 + offplt
10269 + globals->sgotplt_jump_table_size);
b38cadfb 10270
0855e32b
NS		 10271 outrel.r_info = ELF32_R_INFO (indx, R_ARM_TLS_DESC);
10272 sreloc = globals->root.srelplt;
10273 loc = sreloc->contents;
10274 loc += globals->next_tls_desc_index++ * RELOC_SIZE (globals);
10275 BFD_ASSERT (loc + RELOC_SIZE (globals)
99059e56 10276 <= sreloc->contents + sreloc->size);
0855e32b
NS		 10277
10278 SWAP_RELOC_OUT (globals) (output_bfd, &outrel, loc);
10279
10280 /* For globals, the first word in the relocation gets
10281 the relocation index and the top bit set, or zero,
10282 if we're binding now. For locals, it gets the
10283 symbol's offset in the tls section. */
99059e56 10284 bfd_put_32 (output_bfd,
0855e32b
NS		 10285 !h ? value - elf_hash_table (info)->tls_sec->vma
10286 : info->flags & DF_BIND_NOW ? 0
10287 : 0x80000000 | ELF32_R_SYM (outrel.r_info),
b38cadfb
NC		 10288 globals->root.sgotplt->contents + offplt
10289 + globals->sgotplt_jump_table_size);
10290
0855e32b 10291 /* Second word in the relocation is always zero. */
99059e56 10292 bfd_put_32 (output_bfd, 0,
b38cadfb
NC		 10293 globals->root.sgotplt->contents + offplt
10294 + globals->sgotplt_jump_table_size + 4);
0855e32b 10295 }
ba93b8ac
DJ		 10296 if (tls_type & GOT_TLS_GD)
10297 {
10298 if (need_relocs)
10299 {
00a97672 10300 outrel.r_addend = 0;
362d30a1
RS		 10301 outrel.r_offset = (sgot->output_section->vma
10302 + sgot->output_offset
00a97672 10303 + cur_off);
ba93b8ac 10304 outrel.r_info = ELF32_R_INFO (indx, R_ARM_TLS_DTPMOD32);
ba93b8ac 10305
00a97672
RS		 10306 if (globals->use_rel)
10307 bfd_put_32 (output_bfd, outrel.r_addend,
362d30a1 10308 sgot->contents + cur_off);
00a97672 10309
47beaa6a 10310 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
ba93b8ac
DJ		 10311
10312 if (indx == 0)
10313 bfd_put_32 (output_bfd, value - dtpoff_base (info),
362d30a1 10314 sgot->contents + cur_off + 4);
ba93b8ac
DJ		 10315 else
10316 {
00a97672 10317 outrel.r_addend = 0;
ba93b8ac
DJ		 10318 outrel.r_info = ELF32_R_INFO (indx,
10319 R_ARM_TLS_DTPOFF32);
10320 outrel.r_offset += 4;
00a97672
RS		 10321
10322 if (globals->use_rel)
10323 bfd_put_32 (output_bfd, outrel.r_addend,
362d30a1 10324 sgot->contents + cur_off + 4);
00a97672 10325
47beaa6a
RS		 10326 elf32_arm_add_dynreloc (output_bfd, info,
10327 srelgot, &outrel);
ba93b8ac
DJ		 10328 }
10329 }
10330 else
10331 {
10332 /* If we are not emitting relocations for a
10333 general dynamic reference, then we must be in a
10334 static link or an executable link with the
10335 symbol binding locally. Mark it as belonging
10336 to module 1, the executable. */
10337 bfd_put_32 (output_bfd, 1,
362d30a1 10338 sgot->contents + cur_off);
ba93b8ac 10339 bfd_put_32 (output_bfd, value - dtpoff_base (info),
362d30a1 10340 sgot->contents + cur_off + 4);
ba93b8ac
DJ		 10341 }
10342
10343 cur_off += 8;
10344 }
10345
10346 if (tls_type & GOT_TLS_IE)
10347 {
10348 if (need_relocs)
10349 {
00a97672
RS		 10350 if (indx == 0)
10351 outrel.r_addend = value - dtpoff_base (info);
10352 else
10353 outrel.r_addend = 0;
362d30a1
RS		 10354 outrel.r_offset = (sgot->output_section->vma
10355 + sgot->output_offset
ba93b8ac
DJ		 10356 + cur_off);
10357 outrel.r_info = ELF32_R_INFO (indx, R_ARM_TLS_TPOFF32);
10358
00a97672
RS		 10359 if (globals->use_rel)
10360 bfd_put_32 (output_bfd, outrel.r_addend,
362d30a1 10361 sgot->contents + cur_off);
ba93b8ac 10362
47beaa6a 10363 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
ba93b8ac
DJ		 10364 }
10365 else
10366 bfd_put_32 (output_bfd, tpoff (info, value),
362d30a1 10367 sgot->contents + cur_off);
ba93b8ac
DJ		 10368 cur_off += 4;
10369 }
10370
10371 if (h != NULL)
10372 h->got.offset |= 1;
10373 else
10374 local_got_offsets[r_symndx] |= 1;
10375 }
10376
10377 if ((tls_type & GOT_TLS_GD) && r_type != R_ARM_TLS_GD32)
10378 off += 8;
0855e32b
NS		 10379 else if (tls_type & GOT_TLS_GDESC)
10380 off = offplt;
10381
10382 if (ELF32_R_TYPE(rel->r_info) == R_ARM_TLS_CALL
10383 || ELF32_R_TYPE(rel->r_info) == R_ARM_THM_TLS_CALL)
10384 {
10385 bfd_signed_vma offset;
12352d3f
PB		 10386 /* TLS stubs are arm mode. The original symbol is a
10387 data object, so branch_type is bogus. */
10388 branch_type = ST_BRANCH_TO_ARM;
0855e32b 10389 enum elf32_arm_stub_type stub_type
34e77a92
RS		 10390 = arm_type_of_stub (info, input_section, rel,
10391 st_type, &branch_type,
0855e32b
NS		 10392 (struct elf32_arm_link_hash_entry *)h,
10393 globals->tls_trampoline, globals->root.splt,
10394 input_bfd, sym_name);
10395
10396 if (stub_type != arm_stub_none)
10397 {
10398 struct elf32_arm_stub_hash_entry *stub_entry
10399 = elf32_arm_get_stub_entry
10400 (input_section, globals->root.splt, 0, rel,
10401 globals, stub_type);
10402 offset = (stub_entry->stub_offset
10403 + stub_entry->stub_sec->output_offset
10404 + stub_entry->stub_sec->output_section->vma);
10405 }
10406 else
10407 offset = (globals->root.splt->output_section->vma
10408 + globals->root.splt->output_offset
10409 + globals->tls_trampoline);
10410
10411 if (ELF32_R_TYPE(rel->r_info) == R_ARM_TLS_CALL)
10412 {
10413 unsigned long inst;
b38cadfb
NC		 10414
10415 offset -= (input_section->output_section->vma
10416 + input_section->output_offset
10417 + rel->r_offset + 8);
0855e32b
NS		 10418
10419 inst = offset >> 2;
10420 inst &= 0x00ffffff;
10421 value = inst | (globals->use_blx ? 0xfa000000 : 0xeb000000);
10422 }
10423 else
10424 {
10425 /* Thumb blx encodes the offset in a complicated
10426 fashion. */
10427 unsigned upper_insn, lower_insn;
10428 unsigned neg;
10429
b38cadfb
NC		 10430 offset -= (input_section->output_section->vma
10431 + input_section->output_offset
0855e32b 10432 + rel->r_offset + 4);
b38cadfb 10433
12352d3f
PB		 10434 if (stub_type != arm_stub_none
10435 && arm_stub_is_thumb (stub_type))
10436 {
10437 lower_insn = 0xd000;
10438 }
10439 else
10440 {
10441 lower_insn = 0xc000;
6a631e86 10442 /* Round up the offset to a word boundary. */
12352d3f
PB		 10443 offset = (offset + 2) & ~2;
10444 }
10445
0855e32b
NS		 10446 neg = offset < 0;
10447 upper_insn = (0xf000
10448 | ((offset >> 12) & 0x3ff)
10449 | (neg << 10));
12352d3f 10450 lower_insn |= (((!((offset >> 23) & 1)) ^ neg) << 13)
0855e32b 10451 | (((!((offset >> 22) & 1)) ^ neg) << 11)
12352d3f 10452 | ((offset >> 1) & 0x7ff);
0855e32b
NS		 10453 bfd_put_16 (input_bfd, upper_insn, hit_data);
10454 bfd_put_16 (input_bfd, lower_insn, hit_data + 2);
10455 return bfd_reloc_ok;
10456 }
10457 }
10458 /* These relocations needs special care, as besides the fact
10459 they point somewhere in .gotplt, the addend must be
10460 adjusted accordingly depending on the type of instruction
6a631e86 10461 we refer to. */
0855e32b
NS		 10462 else if ((r_type == R_ARM_TLS_GOTDESC) && (tls_type & GOT_TLS_GDESC))
10463 {
10464 unsigned long data, insn;
10465 unsigned thumb;
b38cadfb 10466
0855e32b
NS		 10467 data = bfd_get_32 (input_bfd, hit_data);
10468 thumb = data & 1;
10469 data &= ~1u;
b38cadfb 10470
0855e32b
NS		 10471 if (thumb)
10472 {
10473 insn = bfd_get_16 (input_bfd, contents + rel->r_offset - data);
10474 if ((insn & 0xf000) == 0xf000 || (insn & 0xf800) == 0xe800)
10475 insn = (insn << 16)
10476 | bfd_get_16 (input_bfd,
10477 contents + rel->r_offset - data + 2);
10478 if ((insn & 0xf800c000) == 0xf000c000)
10479 /* bl/blx */
10480 value = -6;
10481 else if ((insn & 0xffffff00) == 0x4400)
10482 /* add */
10483 value = -5;
10484 else
10485 {
10486 (*_bfd_error_handler)
10487 (_("%B(%A+0x%lx):unexpected Thumb instruction '0x%x' referenced by TLS_GOTDESC"),
10488 input_bfd, input_section,
10489 (unsigned long)rel->r_offset, insn);
10490 return bfd_reloc_notsupported;
10491 }
10492 }
10493 else
10494 {
10495 insn = bfd_get_32 (input_bfd, contents + rel->r_offset - data);
10496
10497 switch (insn >> 24)
10498 {
10499 case 0xeb: /* bl */
10500 case 0xfa: /* blx */
10501 value = -4;
10502 break;
10503
10504 case 0xe0: /* add */
10505 value = -8;
10506 break;
b38cadfb 10507
0855e32b
NS		 10508 default:
10509 (*_bfd_error_handler)
10510 (_("%B(%A+0x%lx):unexpected ARM instruction '0x%x' referenced by TLS_GOTDESC"),
10511 input_bfd, input_section,
10512 (unsigned long)rel->r_offset, insn);
10513 return bfd_reloc_notsupported;
10514 }
10515 }
b38cadfb 10516
0855e32b
NS		 10517 value += ((globals->root.sgotplt->output_section->vma
10518 + globals->root.sgotplt->output_offset + off)
10519 - (input_section->output_section->vma
10520 + input_section->output_offset
10521 + rel->r_offset)
10522 + globals->sgotplt_jump_table_size);
10523 }
10524 else
10525 value = ((globals->root.sgot->output_section->vma
10526 + globals->root.sgot->output_offset + off)
10527 - (input_section->output_section->vma
10528 + input_section->output_offset + rel->r_offset));
ba93b8ac
DJ		 10529
10530 return _bfd_final_link_relocate (howto, input_bfd, input_section,
10531 contents, rel->r_offset, value,
00a97672 10532 rel->r_addend);
ba93b8ac
DJ		 10533 }
10534
10535 case R_ARM_TLS_LE32:
3cbc1e5e 10536 if (bfd_link_dll (info))
ba93b8ac
DJ		 10537 {
10538 (*_bfd_error_handler)
10539 (_("%B(%A+0x%lx): R_ARM_TLS_LE32 relocation not permitted in shared object"),
10540 input_bfd, input_section,
10541 (long) rel->r_offset, howto->name);
46691134 10542 return bfd_reloc_notsupported;
ba93b8ac
DJ		 10543 }
10544 else
10545 value = tpoff (info, value);
906e58ca 10546
ba93b8ac 10547 return _bfd_final_link_relocate (howto, input_bfd, input_section,
00a97672
RS		 10548 contents, rel->r_offset, value,
10549 rel->r_addend);
ba93b8ac 10550
319850b4
JB		 10551 case R_ARM_V4BX:
10552 if (globals->fix_v4bx)
845b51d6
PB		 10553 {
10554 bfd_vma insn = bfd_get_32 (input_bfd, hit_data);
319850b4 10555
845b51d6
PB		 10556 /* Ensure that we have a BX instruction. */
10557 BFD_ASSERT ((insn & 0x0ffffff0) == 0x012fff10);
319850b4 10558
845b51d6
PB		 10559 if (globals->fix_v4bx == 2 && (insn & 0xf) != 0xf)
10560 {
10561 /* Branch to veneer. */
10562 bfd_vma glue_addr;
10563 glue_addr = elf32_arm_bx_glue (info, insn & 0xf);
10564 glue_addr -= input_section->output_section->vma
10565 + input_section->output_offset
10566 + rel->r_offset + 8;
10567 insn = (insn & 0xf0000000) | 0x0a000000
10568 | ((glue_addr >> 2) & 0x00ffffff);
10569 }
10570 else
10571 {
10572 /* Preserve Rm (lowest four bits) and the condition code
10573 (highest four bits). Other bits encode MOV PC,Rm. */
10574 insn = (insn & 0xf000000f) | 0x01a0f000;
10575 }
319850b4 10576
845b51d6
PB		 10577 bfd_put_32 (input_bfd, insn, hit_data);
10578 }
319850b4
JB		 10579 return bfd_reloc_ok;
10580
b6895b4f
PB		 10581 case R_ARM_MOVW_ABS_NC:
10582 case R_ARM_MOVT_ABS:
10583 case R_ARM_MOVW_PREL_NC:
10584 case R_ARM_MOVT_PREL:
92f5d02b
MS		 10585 /* Until we properly support segment-base-relative addressing then
10586 we assume the segment base to be zero, as for the group relocations.
10587 Thus R_ARM_MOVW_BREL_NC has the same semantics as R_ARM_MOVW_ABS_NC
10588 and R_ARM_MOVT_BREL has the same semantics as R_ARM_MOVT_ABS. */
10589 case R_ARM_MOVW_BREL_NC:
10590 case R_ARM_MOVW_BREL:
10591 case R_ARM_MOVT_BREL:
b6895b4f
PB		 10592 {
10593 bfd_vma insn = bfd_get_32 (input_bfd, hit_data);
10594
10595 if (globals->use_rel)
10596 {
10597 addend = ((insn >> 4) & 0xf000) | (insn & 0xfff);
39623e12 10598 signed_addend = (addend ^ 0x8000) - 0x8000;
b6895b4f 10599 }
92f5d02b 10600
b6895b4f 10601 value += signed_addend;
b6895b4f
PB		 10602
10603 if (r_type == R_ARM_MOVW_PREL_NC || r_type == R_ARM_MOVT_PREL)
10604 value -= (input_section->output_section->vma
10605 + input_section->output_offset + rel->r_offset);
10606
92f5d02b 10607 if (r_type == R_ARM_MOVW_BREL && value >= 0x10000)
99059e56 10608 return bfd_reloc_overflow;
92f5d02b 10609
35fc36a8 10610 if (branch_type == ST_BRANCH_TO_THUMB)
92f5d02b
MS		 10611 value |= 1;
10612
10613 if (r_type == R_ARM_MOVT_ABS || r_type == R_ARM_MOVT_PREL
99059e56 10614 || r_type == R_ARM_MOVT_BREL)
b6895b4f
PB		 10615 value >>= 16;
10616
10617 insn &= 0xfff0f000;
10618 insn |= value & 0xfff;
10619 insn |= (value & 0xf000) << 4;
10620 bfd_put_32 (input_bfd, insn, hit_data);
10621 }
10622 return bfd_reloc_ok;
10623
10624 case R_ARM_THM_MOVW_ABS_NC:
10625 case R_ARM_THM_MOVT_ABS:
10626 case R_ARM_THM_MOVW_PREL_NC:
10627 case R_ARM_THM_MOVT_PREL:
92f5d02b
MS		 10628 /* Until we properly support segment-base-relative addressing then
10629 we assume the segment base to be zero, as for the above relocations.
10630 Thus R_ARM_THM_MOVW_BREL_NC has the same semantics as
10631 R_ARM_THM_MOVW_ABS_NC and R_ARM_THM_MOVT_BREL has the same semantics
10632 as R_ARM_THM_MOVT_ABS. */
10633 case R_ARM_THM_MOVW_BREL_NC:
10634 case R_ARM_THM_MOVW_BREL:
10635 case R_ARM_THM_MOVT_BREL:
b6895b4f
PB		 10636 {
10637 bfd_vma insn;
906e58ca 10638
b6895b4f
PB		 10639 insn = bfd_get_16 (input_bfd, hit_data) << 16;
10640 insn |= bfd_get_16 (input_bfd, hit_data + 2);
10641
10642 if (globals->use_rel)
10643 {
10644 addend = ((insn >> 4) & 0xf000)
10645 | ((insn >> 15) & 0x0800)
10646 | ((insn >> 4) & 0x0700)
10647 | (insn & 0x00ff);
39623e12 10648 signed_addend = (addend ^ 0x8000) - 0x8000;
b6895b4f 10649 }
92f5d02b 10650
b6895b4f 10651 value += signed_addend;
b6895b4f
PB		 10652
10653 if (r_type == R_ARM_THM_MOVW_PREL_NC || r_type == R_ARM_THM_MOVT_PREL)
10654 value -= (input_section->output_section->vma
10655 + input_section->output_offset + rel->r_offset);
10656
92f5d02b 10657 if (r_type == R_ARM_THM_MOVW_BREL && value >= 0x10000)
99059e56 10658 return bfd_reloc_overflow;
92f5d02b 10659
35fc36a8 10660 if (branch_type == ST_BRANCH_TO_THUMB)
92f5d02b
MS		 10661 value |= 1;
10662
10663 if (r_type == R_ARM_THM_MOVT_ABS || r_type == R_ARM_THM_MOVT_PREL
99059e56 10664 || r_type == R_ARM_THM_MOVT_BREL)
b6895b4f
PB		 10665 value >>= 16;
10666
10667 insn &= 0xfbf08f00;
10668 insn |= (value & 0xf000) << 4;
10669 insn |= (value & 0x0800) << 15;
10670 insn |= (value & 0x0700) << 4;
10671 insn |= (value & 0x00ff);
10672
10673 bfd_put_16 (input_bfd, insn >> 16, hit_data);
10674 bfd_put_16 (input_bfd, insn & 0xffff, hit_data + 2);
10675 }
10676 return bfd_reloc_ok;
10677
4962c51a
MS		 10678 case R_ARM_ALU_PC_G0_NC:
10679 case R_ARM_ALU_PC_G1_NC:
10680 case R_ARM_ALU_PC_G0:
10681 case R_ARM_ALU_PC_G1:
10682 case R_ARM_ALU_PC_G2:
10683 case R_ARM_ALU_SB_G0_NC:
10684 case R_ARM_ALU_SB_G1_NC:
10685 case R_ARM_ALU_SB_G0:
10686 case R_ARM_ALU_SB_G1:
10687 case R_ARM_ALU_SB_G2:
10688 {
10689 bfd_vma insn = bfd_get_32 (input_bfd, hit_data);
99059e56 10690 bfd_vma pc = input_section->output_section->vma
4962c51a 10691 + input_section->output_offset + rel->r_offset;
31a91d61 10692 /* sb is the origin of the *segment* containing the symbol. */
62c34db3 10693 bfd_vma sb = sym_sec ? sym_sec->output_section->vma : 0;
99059e56
RM		 10694 bfd_vma residual;
10695 bfd_vma g_n;
4962c51a 10696 bfd_signed_vma signed_value;
99059e56
RM		 10697 int group = 0;
10698
10699 /* Determine which group of bits to select. */
10700 switch (r_type)
10701 {
10702 case R_ARM_ALU_PC_G0_NC:
10703 case R_ARM_ALU_PC_G0:
10704 case R_ARM_ALU_SB_G0_NC:
10705 case R_ARM_ALU_SB_G0:
10706 group = 0;
10707 break;
10708
10709 case R_ARM_ALU_PC_G1_NC:
10710 case R_ARM_ALU_PC_G1:
10711 case R_ARM_ALU_SB_G1_NC:
10712 case R_ARM_ALU_SB_G1:
10713 group = 1;
10714 break;
10715
10716 case R_ARM_ALU_PC_G2:
10717 case R_ARM_ALU_SB_G2:
10718 group = 2;
10719 break;
10720
10721 default:
10722 abort ();
10723 }
10724
10725 /* If REL, extract the addend from the insn. If RELA, it will
10726 have already been fetched for us. */
4962c51a 10727 if (globals->use_rel)
99059e56
RM		 10728 {
10729 int negative;
10730 bfd_vma constant = insn & 0xff;
10731 bfd_vma rotation = (insn & 0xf00) >> 8;
10732
10733 if (rotation == 0)
10734 signed_addend = constant;
10735 else
10736 {
10737 /* Compensate for the fact that in the instruction, the
10738 rotation is stored in multiples of 2 bits. */
10739 rotation *= 2;
10740
10741 /* Rotate "constant" right by "rotation" bits. */
10742 signed_addend = (constant >> rotation) |
10743 (constant << (8 * sizeof (bfd_vma) - rotation));
10744 }
10745
10746 /* Determine if the instruction is an ADD or a SUB.
10747 (For REL, this determines the sign of the addend.) */
10748 negative = identify_add_or_sub (insn);
10749 if (negative == 0)
10750 {
10751 (*_bfd_error_handler)
10752 (_("%B(%A+0x%lx): Only ADD or SUB instructions are allowed for ALU group relocations"),
10753 input_bfd, input_section,
10754 (long) rel->r_offset, howto->name);
10755 return bfd_reloc_overflow;
10756 }
10757
10758 signed_addend *= negative;
10759 }
4962c51a
MS		 10760
10761 /* Compute the value (X) to go in the place. */
99059e56
RM		 10762 if (r_type == R_ARM_ALU_PC_G0_NC
10763 || r_type == R_ARM_ALU_PC_G1_NC
10764 || r_type == R_ARM_ALU_PC_G0
10765 || r_type == R_ARM_ALU_PC_G1
10766 || r_type == R_ARM_ALU_PC_G2)
10767 /* PC relative. */
10768 signed_value = value - pc + signed_addend;
10769 else
10770 /* Section base relative. */
10771 signed_value = value - sb + signed_addend;
10772
10773 /* If the target symbol is a Thumb function, then set the
10774 Thumb bit in the address. */
35fc36a8 10775 if (branch_type == ST_BRANCH_TO_THUMB)
4962c51a
MS		 10776 signed_value |= 1;
10777
99059e56
RM		 10778 /* Calculate the value of the relevant G_n, in encoded
10779 constant-with-rotation format. */
b6518b38
NC		 10780 g_n = calculate_group_reloc_mask (signed_value < 0 ? - signed_value : signed_value,
10781 group, &residual);
99059e56
RM		 10782
10783 /* Check for overflow if required. */
10784 if ((r_type == R_ARM_ALU_PC_G0
10785 || r_type == R_ARM_ALU_PC_G1
10786 || r_type == R_ARM_ALU_PC_G2
10787 || r_type == R_ARM_ALU_SB_G0
10788 || r_type == R_ARM_ALU_SB_G1
10789 || r_type == R_ARM_ALU_SB_G2) && residual != 0)
10790 {
10791 (*_bfd_error_handler)
10792 (_("%B(%A+0x%lx): Overflow whilst splitting 0x%lx for group relocation %s"),
10793 input_bfd, input_section,
b6518b38
NC		 10794 (long) rel->r_offset, signed_value < 0 ? - signed_value : signed_value,
10795 howto->name);
99059e56
RM		 10796 return bfd_reloc_overflow;
10797 }
10798
10799 /* Mask out the value and the ADD/SUB part of the opcode; take care
10800 not to destroy the S bit. */
10801 insn &= 0xff1ff000;
10802
10803 /* Set the opcode according to whether the value to go in the
10804 place is negative. */
10805 if (signed_value < 0)
10806 insn |= 1 << 22;
10807 else
10808 insn |= 1 << 23;
10809
10810 /* Encode the offset. */
10811 insn |= g_n;
4962c51a
MS		 10812
10813 bfd_put_32 (input_bfd, insn, hit_data);
10814 }
10815 return bfd_reloc_ok;
10816
10817 case R_ARM_LDR_PC_G0:
10818 case R_ARM_LDR_PC_G1:
10819 case R_ARM_LDR_PC_G2:
10820 case R_ARM_LDR_SB_G0:
10821 case R_ARM_LDR_SB_G1:
10822 case R_ARM_LDR_SB_G2:
10823 {
10824 bfd_vma insn = bfd_get_32 (input_bfd, hit_data);
99059e56 10825 bfd_vma pc = input_section->output_section->vma
4962c51a 10826 + input_section->output_offset + rel->r_offset;
31a91d61 10827 /* sb is the origin of the *segment* containing the symbol. */
62c34db3 10828 bfd_vma sb = sym_sec ? sym_sec->output_section->vma : 0;
99059e56 10829 bfd_vma residual;
4962c51a 10830 bfd_signed_vma signed_value;
99059e56
RM		 10831 int group = 0;
10832
10833 /* Determine which groups of bits to calculate. */
10834 switch (r_type)
10835 {
10836 case R_ARM_LDR_PC_G0:
10837 case R_ARM_LDR_SB_G0:
10838 group = 0;
10839 break;
10840
10841 case R_ARM_LDR_PC_G1:
10842 case R_ARM_LDR_SB_G1:
10843 group = 1;
10844 break;
10845
10846 case R_ARM_LDR_PC_G2:
10847 case R_ARM_LDR_SB_G2:
10848 group = 2;
10849 break;
10850
10851 default:
10852 abort ();
10853 }
10854
10855 /* If REL, extract the addend from the insn. If RELA, it will
10856 have already been fetched for us. */
4962c51a 10857 if (globals->use_rel)
99059e56
RM		 10858 {
10859 int negative = (insn & (1 << 23)) ? 1 : -1;
10860 signed_addend = negative * (insn & 0xfff);
10861 }
4962c51a
MS		 10862
10863 /* Compute the value (X) to go in the place. */
99059e56
RM		 10864 if (r_type == R_ARM_LDR_PC_G0
10865 || r_type == R_ARM_LDR_PC_G1
10866 || r_type == R_ARM_LDR_PC_G2)
10867 /* PC relative. */
10868 signed_value = value - pc + signed_addend;
10869 else
10870 /* Section base relative. */
10871 signed_value = value - sb + signed_addend;
10872
10873 /* Calculate the value of the relevant G_{n-1} to obtain
10874 the residual at that stage. */
b6518b38
NC		 10875 calculate_group_reloc_mask (signed_value < 0 ? - signed_value : signed_value,
10876 group - 1, &residual);
99059e56
RM		 10877
10878 /* Check for overflow. */
10879 if (residual >= 0x1000)
10880 {
10881 (*_bfd_error_handler)
10882 (_("%B(%A+0x%lx): Overflow whilst splitting 0x%lx for group relocation %s"),
b6518b38
NC		 10883 input_bfd, input_section,
10884 (long) rel->r_offset, labs (signed_value), howto->name);
99059e56
RM		 10885 return bfd_reloc_overflow;
10886 }
10887
10888 /* Mask out the value and U bit. */
10889 insn &= 0xff7ff000;
10890
10891 /* Set the U bit if the value to go in the place is non-negative. */
10892 if (signed_value >= 0)
10893 insn |= 1 << 23;
10894
10895 /* Encode the offset. */
10896 insn |= residual;
4962c51a
MS		 10897
10898 bfd_put_32 (input_bfd, insn, hit_data);
10899 }
10900 return bfd_reloc_ok;
10901
10902 case R_ARM_LDRS_PC_G0:
10903 case R_ARM_LDRS_PC_G1:
10904 case R_ARM_LDRS_PC_G2:
10905 case R_ARM_LDRS_SB_G0:
10906 case R_ARM_LDRS_SB_G1:
10907 case R_ARM_LDRS_SB_G2:
10908 {
10909 bfd_vma insn = bfd_get_32 (input_bfd, hit_data);
99059e56 10910 bfd_vma pc = input_section->output_section->vma
4962c51a 10911 + input_section->output_offset + rel->r_offset;
31a91d61 10912 /* sb is the origin of the *segment* containing the symbol. */
62c34db3 10913 bfd_vma sb = sym_sec ? sym_sec->output_section->vma : 0;
99059e56 10914 bfd_vma residual;
4962c51a 10915 bfd_signed_vma signed_value;
99059e56
RM		 10916 int group = 0;
10917
10918 /* Determine which groups of bits to calculate. */
10919 switch (r_type)
10920 {
10921 case R_ARM_LDRS_PC_G0:
10922 case R_ARM_LDRS_SB_G0:
10923 group = 0;
10924 break;
10925
10926 case R_ARM_LDRS_PC_G1:
10927 case R_ARM_LDRS_SB_G1:
10928 group = 1;
10929 break;
10930
10931 case R_ARM_LDRS_PC_G2:
10932 case R_ARM_LDRS_SB_G2:
10933 group = 2;
10934 break;
10935
10936 default:
10937 abort ();
10938 }
10939
10940 /* If REL, extract the addend from the insn. If RELA, it will
10941 have already been fetched for us. */
4962c51a 10942 if (globals->use_rel)
99059e56
RM		 10943 {
10944 int negative = (insn & (1 << 23)) ? 1 : -1;
10945 signed_addend = negative * (((insn & 0xf00) >> 4) + (insn & 0xf));
10946 }
4962c51a
MS		 10947
10948 /* Compute the value (X) to go in the place. */
99059e56
RM		 10949 if (r_type == R_ARM_LDRS_PC_G0
10950 || r_type == R_ARM_LDRS_PC_G1
10951 || r_type == R_ARM_LDRS_PC_G2)
10952 /* PC relative. */
10953 signed_value = value - pc + signed_addend;
10954 else
10955 /* Section base relative. */
10956 signed_value = value - sb + signed_addend;
10957
10958 /* Calculate the value of the relevant G_{n-1} to obtain
10959 the residual at that stage. */
b6518b38
NC		 10960 calculate_group_reloc_mask (signed_value < 0 ? - signed_value : signed_value,
10961 group - 1, &residual);
99059e56
RM		 10962
10963 /* Check for overflow. */
10964 if (residual >= 0x100)
10965 {
10966 (*_bfd_error_handler)
10967 (_("%B(%A+0x%lx): Overflow whilst splitting 0x%lx for group relocation %s"),
b6518b38
NC		 10968 input_bfd, input_section,
10969 (long) rel->r_offset, labs (signed_value), howto->name);
99059e56
RM		 10970 return bfd_reloc_overflow;
10971 }
10972
10973 /* Mask out the value and U bit. */
10974 insn &= 0xff7ff0f0;
10975
10976 /* Set the U bit if the value to go in the place is non-negative. */
10977 if (signed_value >= 0)
10978 insn |= 1 << 23;
10979
10980 /* Encode the offset. */
10981 insn |= ((residual & 0xf0) << 4) | (residual & 0xf);
4962c51a
MS		 10982
10983 bfd_put_32 (input_bfd, insn, hit_data);
10984 }
10985 return bfd_reloc_ok;
10986
10987 case R_ARM_LDC_PC_G0:
10988 case R_ARM_LDC_PC_G1:
10989 case R_ARM_LDC_PC_G2:
10990 case R_ARM_LDC_SB_G0:
10991 case R_ARM_LDC_SB_G1:
10992 case R_ARM_LDC_SB_G2:
10993 {
10994 bfd_vma insn = bfd_get_32 (input_bfd, hit_data);
99059e56 10995 bfd_vma pc = input_section->output_section->vma
4962c51a 10996 + input_section->output_offset + rel->r_offset;
31a91d61 10997 /* sb is the origin of the *segment* containing the symbol. */
62c34db3 10998 bfd_vma sb = sym_sec ? sym_sec->output_section->vma : 0;
99059e56 10999 bfd_vma residual;
4962c51a 11000 bfd_signed_vma signed_value;
99059e56
RM		 11001 int group = 0;
11002
11003 /* Determine which groups of bits to calculate. */
11004 switch (r_type)
11005 {
11006 case R_ARM_LDC_PC_G0:
11007 case R_ARM_LDC_SB_G0:
11008 group = 0;
11009 break;
11010
11011 case R_ARM_LDC_PC_G1:
11012 case R_ARM_LDC_SB_G1:
11013 group = 1;
11014 break;
11015
11016 case R_ARM_LDC_PC_G2:
11017 case R_ARM_LDC_SB_G2:
11018 group = 2;
11019 break;
11020
11021 default:
11022 abort ();
11023 }
11024
11025 /* If REL, extract the addend from the insn. If RELA, it will
11026 have already been fetched for us. */
4962c51a 11027 if (globals->use_rel)
99059e56
RM		 11028 {
11029 int negative = (insn & (1 << 23)) ? 1 : -1;
11030 signed_addend = negative * ((insn & 0xff) << 2);
11031 }
4962c51a
MS		 11032
11033 /* Compute the value (X) to go in the place. */
99059e56
RM		 11034 if (r_type == R_ARM_LDC_PC_G0
11035 || r_type == R_ARM_LDC_PC_G1
11036 || r_type == R_ARM_LDC_PC_G2)
11037 /* PC relative. */
11038 signed_value = value - pc + signed_addend;
11039 else
11040 /* Section base relative. */
11041 signed_value = value - sb + signed_addend;
11042
11043 /* Calculate the value of the relevant G_{n-1} to obtain
11044 the residual at that stage. */
b6518b38
NC		 11045 calculate_group_reloc_mask (signed_value < 0 ? - signed_value : signed_value,
11046 group - 1, &residual);
99059e56
RM		 11047
11048 /* Check for overflow. (The absolute value to go in the place must be
11049 divisible by four and, after having been divided by four, must
11050 fit in eight bits.) */
11051 if ((residual & 0x3) != 0 || residual >= 0x400)
11052 {
11053 (*_bfd_error_handler)
11054 (_("%B(%A+0x%lx): Overflow whilst splitting 0x%lx for group relocation %s"),
11055 input_bfd, input_section,
b6518b38 11056 (long) rel->r_offset, labs (signed_value), howto->name);
99059e56
RM		 11057 return bfd_reloc_overflow;
11058 }
11059
11060 /* Mask out the value and U bit. */
11061 insn &= 0xff7fff00;
11062
11063 /* Set the U bit if the value to go in the place is non-negative. */
11064 if (signed_value >= 0)
11065 insn |= 1 << 23;
11066
11067 /* Encode the offset. */
11068 insn |= residual >> 2;
4962c51a
MS		 11069
11070 bfd_put_32 (input_bfd, insn, hit_data);
11071 }
11072 return bfd_reloc_ok;
11073
72d98d16
MG		 11074 case R_ARM_THM_ALU_ABS_G0_NC:
11075 case R_ARM_THM_ALU_ABS_G1_NC:
11076 case R_ARM_THM_ALU_ABS_G2_NC:
11077 case R_ARM_THM_ALU_ABS_G3_NC:
11078 {
11079 const int shift_array[4] = {0, 8, 16, 24};
11080 bfd_vma insn = bfd_get_16 (input_bfd, hit_data);
11081 bfd_vma addr = value;
11082 int shift = shift_array[r_type - R_ARM_THM_ALU_ABS_G0_NC];
11083
11084 /* Compute address. */
11085 if (globals->use_rel)
11086 signed_addend = insn & 0xff;
11087 addr += signed_addend;
11088 if (branch_type == ST_BRANCH_TO_THUMB)
11089 addr |= 1;
11090 /* Clean imm8 insn. */
11091 insn &= 0xff00;
11092 /* And update with correct part of address. */
11093 insn |= (addr >> shift) & 0xff;
11094 /* Update insn. */
11095 bfd_put_16 (input_bfd, insn, hit_data);
11096 }
11097
11098 *unresolved_reloc_p = FALSE;
11099 return bfd_reloc_ok;
11100
252b5132
RH		 11101 default:
11102 return bfd_reloc_notsupported;
11103 }
11104}
11105
98c1d4aa
NC		 11106/* Add INCREMENT to the reloc (of type HOWTO) at ADDRESS. */
11107static void
57e8b36a
NC		 11108arm_add_to_rel (bfd * abfd,
11109 bfd_byte * address,
11110 reloc_howto_type * howto,
11111 bfd_signed_vma increment)
98c1d4aa 11112{
98c1d4aa
NC		 11113 bfd_signed_vma addend;
11114
bd97cb95
DJ		 11115 if (howto->type == R_ARM_THM_CALL
11116 || howto->type == R_ARM_THM_JUMP24)
98c1d4aa 11117 {
9a5aca8c
AM		 11118 int upper_insn, lower_insn;
11119 int upper, lower;
98c1d4aa 11120
9a5aca8c
AM		 11121 upper_insn = bfd_get_16 (abfd, address);
11122 lower_insn = bfd_get_16 (abfd, address + 2);
11123 upper = upper_insn & 0x7ff;
11124 lower = lower_insn & 0x7ff;
11125
11126 addend = (upper << 12) | (lower << 1);
ddda4409 11127 addend += increment;
9a5aca8c 11128 addend >>= 1;
98c1d4aa 11129
9a5aca8c
AM		 11130 upper_insn = (upper_insn & 0xf800) | ((addend >> 11) & 0x7ff);
11131 lower_insn = (lower_insn & 0xf800) | (addend & 0x7ff);
11132
dc810e39
AM		 11133 bfd_put_16 (abfd, (bfd_vma) upper_insn, address);
11134 bfd_put_16 (abfd, (bfd_vma) lower_insn, address + 2);
9a5aca8c
AM		 11135 }
11136 else
11137 {
11138 bfd_vma contents;
11139
11140 contents = bfd_get_32 (abfd, address);
11141
11142 /* Get the (signed) value from the instruction. */
11143 addend = contents & howto->src_mask;
11144 if (addend & ((howto->src_mask + 1) >> 1))
11145 {
11146 bfd_signed_vma mask;
11147
11148 mask = -1;
11149 mask &= ~ howto->src_mask;
11150 addend |= mask;
11151 }
11152
11153 /* Add in the increment, (which is a byte value). */
11154 switch (howto->type)
11155 {
11156 default:
11157 addend += increment;
11158 break;
11159
11160 case R_ARM_PC24:
c6596c5e 11161 case R_ARM_PLT32:
5b5bb741
PB		 11162 case R_ARM_CALL:
11163 case R_ARM_JUMP24:
9a5aca8c 11164 addend <<= howto->size;
dc810e39 11165 addend += increment;
9a5aca8c
AM		 11166
11167 /* Should we check for overflow here ? */
11168
11169 /* Drop any undesired bits. */
11170 addend >>= howto->rightshift;
11171 break;
11172 }
11173
11174 contents = (contents & ~ howto->dst_mask) | (addend & howto->dst_mask);
11175
11176 bfd_put_32 (abfd, contents, address);
ddda4409 11177 }
98c1d4aa 11178}
252b5132 11179
ba93b8ac
DJ		 11180#define IS_ARM_TLS_RELOC(R_TYPE) \
11181 ((R_TYPE) == R_ARM_TLS_GD32 \
11182 || (R_TYPE) == R_ARM_TLS_LDO32 \
11183 || (R_TYPE) == R_ARM_TLS_LDM32 \
11184 || (R_TYPE) == R_ARM_TLS_DTPOFF32 \
11185 || (R_TYPE) == R_ARM_TLS_DTPMOD32 \
11186 || (R_TYPE) == R_ARM_TLS_TPOFF32 \
11187 || (R_TYPE) == R_ARM_TLS_LE32 \
0855e32b
NS		 11188 || (R_TYPE) == R_ARM_TLS_IE32 \
11189 || IS_ARM_TLS_GNU_RELOC (R_TYPE))
11190
11191/* Specific set of relocations for the gnu tls dialect. */
11192#define IS_ARM_TLS_GNU_RELOC(R_TYPE) \
11193 ((R_TYPE) == R_ARM_TLS_GOTDESC \
11194 || (R_TYPE) == R_ARM_TLS_CALL \
11195 || (R_TYPE) == R_ARM_THM_TLS_CALL \
11196 || (R_TYPE) == R_ARM_TLS_DESCSEQ \
11197 || (R_TYPE) == R_ARM_THM_TLS_DESCSEQ)
ba93b8ac 11198
252b5132 11199/* Relocate an ARM ELF section. */
906e58ca 11200
b34976b6 11201static bfd_boolean
57e8b36a
NC		 11202elf32_arm_relocate_section (bfd * output_bfd,
11203 struct bfd_link_info * info,
11204 bfd * input_bfd,
11205 asection * input_section,
11206 bfd_byte * contents,
11207 Elf_Internal_Rela * relocs,
11208 Elf_Internal_Sym * local_syms,
11209 asection ** local_sections)
252b5132 11210{
b34976b6
AM		 11211 Elf_Internal_Shdr *symtab_hdr;
11212 struct elf_link_hash_entry **sym_hashes;
11213 Elf_Internal_Rela *rel;
11214 Elf_Internal_Rela *relend;
11215 const char *name;
b32d3aa2 11216 struct elf32_arm_link_hash_table * globals;
252b5132 11217
4e7fd91e 11218 globals = elf32_arm_hash_table (info);
4dfe6ac6
NC		 11219 if (globals == NULL)
11220 return FALSE;
b491616a 11221
0ffa91dd 11222 symtab_hdr = & elf_symtab_hdr (input_bfd);
252b5132
RH		 11223 sym_hashes = elf_sym_hashes (input_bfd);
11224
11225 rel = relocs;
11226 relend = relocs + input_section->reloc_count;
11227 for (; rel < relend; rel++)
11228 {
ba96a88f
NC		 11229 int r_type;
11230 reloc_howto_type * howto;
11231 unsigned long r_symndx;
11232 Elf_Internal_Sym * sym;
11233 asection * sec;
252b5132 11234 struct elf_link_hash_entry * h;
ba96a88f
NC		 11235 bfd_vma relocation;
11236 bfd_reloc_status_type r;
11237 arelent bfd_reloc;
ba93b8ac 11238 char sym_type;
0945cdfd 11239 bfd_boolean unresolved_reloc = FALSE;
f2a9dd69 11240 char *error_message = NULL;
f21f3fe0 11241
252b5132 11242 r_symndx = ELF32_R_SYM (rel->r_info);
ba96a88f 11243 r_type = ELF32_R_TYPE (rel->r_info);
b32d3aa2 11244 r_type = arm_real_reloc_type (globals, r_type);
252b5132 11245
ba96a88f 11246 if ( r_type == R_ARM_GNU_VTENTRY
99059e56
RM		 11247 || r_type == R_ARM_GNU_VTINHERIT)
11248 continue;
252b5132 11249
b32d3aa2 11250 bfd_reloc.howto = elf32_arm_howto_from_type (r_type);
ba96a88f 11251 howto = bfd_reloc.howto;
252b5132 11252
252b5132
RH		 11253 h = NULL;
11254 sym = NULL;
11255 sec = NULL;
9b485d32 11256
252b5132
RH		 11257 if (r_symndx < symtab_hdr->sh_info)
11258 {
11259 sym = local_syms + r_symndx;
ba93b8ac 11260 sym_type = ELF32_ST_TYPE (sym->st_info);
252b5132 11261 sec = local_sections[r_symndx];
ffcb4889
NS		 11262
11263 /* An object file might have a reference to a local
11264 undefined symbol. This is a daft object file, but we
11265 should at least do something about it. V4BX & NONE
11266 relocations do not use the symbol and are explicitly
77b4f08f
TS		 11267 allowed to use the undefined symbol, so allow those.
11268 Likewise for relocations against STN_UNDEF. */
ffcb4889
NS		 11269 if (r_type != R_ARM_V4BX
11270 && r_type != R_ARM_NONE
77b4f08f 11271 && r_symndx != STN_UNDEF
ffcb4889
NS		 11272 && bfd_is_und_section (sec)
11273 && ELF_ST_BIND (sym->st_info) != STB_WEAK)
11274 {
11275 if (!info->callbacks->undefined_symbol
11276 (info, bfd_elf_string_from_elf_section
11277 (input_bfd, symtab_hdr->sh_link, sym->st_name),
11278 input_bfd, input_section,
11279 rel->r_offset, TRUE))
11280 return FALSE;
11281 }
b38cadfb 11282
4e7fd91e 11283 if (globals->use_rel)
f8df10f4 11284 {
4e7fd91e
PB		 11285 relocation = (sec->output_section->vma
11286 + sec->output_offset
11287 + sym->st_value);
0e1862bb 11288 if (!bfd_link_relocatable (info)
ab96bf03
AM		 11289 && (sec->flags & SEC_MERGE)
11290 && ELF_ST_TYPE (sym->st_info) == STT_SECTION)
f8df10f4 11291 {
4e7fd91e
PB		 11292 asection *msec;
11293 bfd_vma addend, value;
11294
39623e12 11295 switch (r_type)
4e7fd91e 11296 {
39623e12
PB		 11297 case R_ARM_MOVW_ABS_NC:
11298 case R_ARM_MOVT_ABS:
11299 value = bfd_get_32 (input_bfd, contents + rel->r_offset);
11300 addend = ((value & 0xf0000) >> 4) | (value & 0xfff);
11301 addend = (addend ^ 0x8000) - 0x8000;
11302 break;
f8df10f4 11303
39623e12
PB		 11304 case R_ARM_THM_MOVW_ABS_NC:
11305 case R_ARM_THM_MOVT_ABS:
11306 value = bfd_get_16 (input_bfd, contents + rel->r_offset)
11307 << 16;
11308 value |= bfd_get_16 (input_bfd,
11309 contents + rel->r_offset + 2);
11310 addend = ((value & 0xf7000) >> 4) | (value & 0xff)
11311 | ((value & 0x04000000) >> 15);
11312 addend = (addend ^ 0x8000) - 0x8000;
11313 break;
f8df10f4 11314
39623e12
PB		 11315 default:
11316 if (howto->rightshift
11317 || (howto->src_mask & (howto->src_mask + 1)))
11318 {
11319 (*_bfd_error_handler)
11320 (_("%B(%A+0x%lx): %s relocation against SEC_MERGE section"),
11321 input_bfd, input_section,
11322 (long) rel->r_offset, howto->name);
11323 return FALSE;
11324 }
11325
11326 value = bfd_get_32 (input_bfd, contents + rel->r_offset);
11327
11328 /* Get the (signed) value from the instruction. */
11329 addend = value & howto->src_mask;
11330 if (addend & ((howto->src_mask + 1) >> 1))
11331 {
11332 bfd_signed_vma mask;
11333
11334 mask = -1;
11335 mask &= ~ howto->src_mask;
11336 addend |= mask;
11337 }
11338 break;
4e7fd91e 11339 }
39623e12 11340
4e7fd91e
PB		 11341 msec = sec;
11342 addend =
11343 _bfd_elf_rel_local_sym (output_bfd, sym, &msec, addend)
11344 - relocation;
11345 addend += msec->output_section->vma + msec->output_offset;
39623e12 11346
cc643b88 11347 /* Cases here must match those in the preceding
39623e12
PB		 11348 switch statement. */
11349 switch (r_type)
11350 {
11351 case R_ARM_MOVW_ABS_NC:
11352 case R_ARM_MOVT_ABS:
11353 value = (value & 0xfff0f000) | ((addend & 0xf000) << 4)
11354 | (addend & 0xfff);
11355 bfd_put_32 (input_bfd, value, contents + rel->r_offset);
11356 break;
11357
11358 case R_ARM_THM_MOVW_ABS_NC:
11359 case R_ARM_THM_MOVT_ABS:
11360 value = (value & 0xfbf08f00) | ((addend & 0xf700) << 4)
11361 | (addend & 0xff) | ((addend & 0x0800) << 15);
11362 bfd_put_16 (input_bfd, value >> 16,
11363 contents + rel->r_offset);
11364 bfd_put_16 (input_bfd, value,
11365 contents + rel->r_offset + 2);
11366 break;
11367
11368 default:
11369 value = (value & ~ howto->dst_mask)
11370 | (addend & howto->dst_mask);
11371 bfd_put_32 (input_bfd, value, contents + rel->r_offset);
11372 break;
11373 }
f8df10f4 11374 }
f8df10f4 11375 }
4e7fd91e
PB		 11376 else
11377 relocation = _bfd_elf_rela_local_sym (output_bfd, sym, &sec, rel);
252b5132
RH		 11378 }
11379 else
11380 {
62d887d4 11381 bfd_boolean warned, ignored;
560e09e9 11382
b2a8e766
AM		 11383 RELOC_FOR_GLOBAL_SYMBOL (info, input_bfd, input_section, rel,
11384 r_symndx, symtab_hdr, sym_hashes,
11385 h, sec, relocation,
62d887d4 11386 unresolved_reloc, warned, ignored);
ba93b8ac
DJ		 11387
11388 sym_type = h->type;
252b5132
RH		 11389 }
11390
dbaa2011 11391 if (sec != NULL && discarded_section (sec))
e4067dbb 11392 RELOC_AGAINST_DISCARDED_SECTION (info, input_bfd, input_section,
545fd46b 11393 rel, 1, relend, howto, 0, contents);
ab96bf03 11394
0e1862bb 11395 if (bfd_link_relocatable (info))
ab96bf03
AM		 11396 {
11397 /* This is a relocatable link. We don't have to change
11398 anything, unless the reloc is against a section symbol,
11399 in which case we have to adjust according to where the
11400 section symbol winds up in the output section. */
11401 if (sym != NULL && ELF_ST_TYPE (sym->st_info) == STT_SECTION)
11402 {
11403 if (globals->use_rel)
11404 arm_add_to_rel (input_bfd, contents + rel->r_offset,
11405 howto, (bfd_signed_vma) sec->output_offset);
11406 else
11407 rel->r_addend += sec->output_offset;
11408 }
11409 continue;
11410 }
11411
252b5132
RH		 11412 if (h != NULL)
11413 name = h->root.root.string;
11414 else
11415 {
11416 name = (bfd_elf_string_from_elf_section
11417 (input_bfd, symtab_hdr->sh_link, sym->st_name));
11418 if (name == NULL || *name == '\0')
11419 name = bfd_section_name (input_bfd, sec);
11420 }
f21f3fe0 11421
cf35638d 11422 if (r_symndx != STN_UNDEF
ba93b8ac
DJ		 11423 && r_type != R_ARM_NONE
11424 && (h == NULL
11425 || h->root.type == bfd_link_hash_defined
11426 || h->root.type == bfd_link_hash_defweak)
11427 && IS_ARM_TLS_RELOC (r_type) != (sym_type == STT_TLS))
11428 {
11429 (*_bfd_error_handler)
11430 ((sym_type == STT_TLS
11431 ? _("%B(%A+0x%lx): %s used with TLS symbol %s")
11432 : _("%B(%A+0x%lx): %s used with non-TLS symbol %s")),
11433 input_bfd,
11434 input_section,
11435 (long) rel->r_offset,
11436 howto->name,
11437 name);
11438 }
11439
0855e32b 11440 /* We call elf32_arm_final_link_relocate unless we're completely
99059e56
RM		 11441 done, i.e., the relaxation produced the final output we want,
11442 and we won't let anybody mess with it. Also, we have to do
11443 addend adjustments in case of a R_ARM_TLS_GOTDESC relocation
6a631e86 11444 both in relaxed and non-relaxed cases. */
0855e32b
NS		 11445 if ((elf32_arm_tls_transition (info, r_type, h) != (unsigned)r_type)
11446 || (IS_ARM_TLS_GNU_RELOC (r_type)
b38cadfb 11447 && !((h ? elf32_arm_hash_entry (h)->tls_type :
0855e32b
NS		 11448 elf32_arm_local_got_tls_type (input_bfd)[r_symndx])
11449 & GOT_TLS_GDESC)))
11450 {
11451 r = elf32_arm_tls_relax (globals, input_bfd, input_section,
11452 contents, rel, h == NULL);
11453 /* This may have been marked unresolved because it came from
11454 a shared library. But we've just dealt with that. */
11455 unresolved_reloc = 0;
11456 }
11457 else
11458 r = bfd_reloc_continue;
b38cadfb 11459
0855e32b
NS		 11460 if (r == bfd_reloc_continue)
11461 r = elf32_arm_final_link_relocate (howto, input_bfd, output_bfd,
11462 input_section, contents, rel,
34e77a92 11463 relocation, info, sec, name, sym_type,
35fc36a8
RS		 11464 (h ? h->target_internal
11465 : ARM_SYM_BRANCH_TYPE (sym)), h,
0855e32b 11466 &unresolved_reloc, &error_message);
0945cdfd
DJ		 11467
11468 /* Dynamic relocs are not propagated for SEC_DEBUGGING sections
11469 because such sections are not SEC_ALLOC and thus ld.so will
11470 not process them. */
11471 if (unresolved_reloc
99059e56
RM		 11472 && !((input_section->flags & SEC_DEBUGGING) != 0
11473 && h->def_dynamic)
1d5316ab
AM		 11474 && _bfd_elf_section_offset (output_bfd, info, input_section,
11475 rel->r_offset) != (bfd_vma) -1)
0945cdfd
DJ		 11476 {
11477 (*_bfd_error_handler)
843fe662
L		 11478 (_("%B(%A+0x%lx): unresolvable %s relocation against symbol `%s'"),
11479 input_bfd,
11480 input_section,
11481 (long) rel->r_offset,
11482 howto->name,
11483 h->root.root.string);
0945cdfd
DJ		 11484 return FALSE;
11485 }
252b5132
RH		 11486
11487 if (r != bfd_reloc_ok)
11488 {
252b5132
RH		 11489 switch (r)
11490 {
11491 case bfd_reloc_overflow:
cf919dfd
PB		 11492 /* If the overflowing reloc was to an undefined symbol,
11493 we have already printed one error message and there
11494 is no point complaining again. */
11495 if ((! h ||
11496 h->root.type != bfd_link_hash_undefined)
11497 && (!((*info->callbacks->reloc_overflow)
dfeffb9f
L		 11498 (info, (h ? &h->root : NULL), name, howto->name,
11499 (bfd_vma) 0, input_bfd, input_section,
11500 rel->r_offset))))
b34976b6 11501 return FALSE;
252b5132
RH		 11502 break;
11503
11504 case bfd_reloc_undefined:
11505 if (!((*info->callbacks->undefined_symbol)
11506 (info, name, input_bfd, input_section,
b34976b6
AM		 11507 rel->r_offset, TRUE)))
11508 return FALSE;
252b5132
RH		 11509 break;
11510
11511 case bfd_reloc_outofrange:
f2a9dd69 11512 error_message = _("out of range");
252b5132
RH		 11513 goto common_error;
11514
11515 case bfd_reloc_notsupported:
f2a9dd69 11516 error_message = _("unsupported relocation");
252b5132
RH		 11517 goto common_error;
11518
11519 case bfd_reloc_dangerous:
f2a9dd69 11520 /* error_message should already be set. */
252b5132
RH		 11521 goto common_error;
11522
11523 default:
f2a9dd69 11524 error_message = _("unknown error");
8029a119 11525 /* Fall through. */
252b5132
RH		 11526
11527 common_error:
f2a9dd69
DJ		 11528 BFD_ASSERT (error_message != NULL);
11529 if (!((*info->callbacks->reloc_dangerous)
11530 (info, error_message, input_bfd, input_section,
252b5132 11531 rel->r_offset)))
b34976b6 11532 return FALSE;
252b5132
RH		 11533 break;
11534 }
11535 }
11536 }
11537
b34976b6 11538 return TRUE;
252b5132
RH		 11539}
11540
91d6fa6a 11541/* Add a new unwind edit to the list described by HEAD, TAIL. If TINDEX is zero,
2468f9c9 11542 adds the edit to the start of the list. (The list must be built in order of
91d6fa6a 11543 ascending TINDEX: the function's callers are primarily responsible for
2468f9c9
PB		 11544 maintaining that condition). */
11545
11546static void
11547add_unwind_table_edit (arm_unwind_table_edit **head,
11548 arm_unwind_table_edit **tail,
11549 arm_unwind_edit_type type,
11550 asection *linked_section,
91d6fa6a 11551 unsigned int tindex)
2468f9c9 11552{
21d799b5
NC		 11553 arm_unwind_table_edit *new_edit = (arm_unwind_table_edit *)
11554 xmalloc (sizeof (arm_unwind_table_edit));
b38cadfb 11555
2468f9c9
PB		 11556 new_edit->type = type;
11557 new_edit->linked_section = linked_section;
91d6fa6a 11558 new_edit->index = tindex;
b38cadfb 11559
91d6fa6a 11560 if (tindex > 0)
2468f9c9
PB		 11561 {
11562 new_edit->next = NULL;
11563
11564 if (*tail)
11565 (*tail)->next = new_edit;
11566
11567 (*tail) = new_edit;
11568
11569 if (!*head)
11570 (*head) = new_edit;
11571 }
11572 else
11573 {
11574 new_edit->next = *head;
11575
11576 if (!*tail)
11577 *tail = new_edit;
11578
11579 *head = new_edit;
11580 }
11581}
11582
11583static _arm_elf_section_data *get_arm_elf_section_data (asection *);
11584
11585/* Increase the size of EXIDX_SEC by ADJUST bytes. ADJUST mau be negative. */
11586static void
11587adjust_exidx_size(asection *exidx_sec, int adjust)
11588{
11589 asection *out_sec;
11590
11591 if (!exidx_sec->rawsize)
11592 exidx_sec->rawsize = exidx_sec->size;
11593
11594 bfd_set_section_size (exidx_sec->owner, exidx_sec, exidx_sec->size + adjust);
11595 out_sec = exidx_sec->output_section;
11596 /* Adjust size of output section. */
11597 bfd_set_section_size (out_sec->owner, out_sec, out_sec->size +adjust);
11598}
11599
11600/* Insert an EXIDX_CANTUNWIND marker at the end of a section. */
11601static void
11602insert_cantunwind_after(asection *text_sec, asection *exidx_sec)
11603{
11604 struct _arm_elf_section_data *exidx_arm_data;
11605
11606 exidx_arm_data = get_arm_elf_section_data (exidx_sec);
11607 add_unwind_table_edit (
11608 &exidx_arm_data->u.exidx.unwind_edit_list,
11609 &exidx_arm_data->u.exidx.unwind_edit_tail,
11610 INSERT_EXIDX_CANTUNWIND_AT_END, text_sec, UINT_MAX);
11611
491d01d3
YU		 11612 exidx_arm_data->additional_reloc_count++;
11613
2468f9c9
PB		 11614 adjust_exidx_size(exidx_sec, 8);
11615}
11616
11617/* Scan .ARM.exidx tables, and create a list describing edits which should be
11618 made to those tables, such that:
b38cadfb 11619
2468f9c9
PB		 11620 1. Regions without unwind data are marked with EXIDX_CANTUNWIND entries.
11621 2. Duplicate entries are merged together (EXIDX_CANTUNWIND, or unwind
99059e56 11622 codes which have been inlined into the index).
2468f9c9 11623
85fdf906
AH		 11624 If MERGE_EXIDX_ENTRIES is false, duplicate entries are not merged.
11625
2468f9c9 11626 The edits are applied when the tables are written
b38cadfb 11627 (in elf32_arm_write_section). */
2468f9c9
PB		 11628
11629bfd_boolean
11630elf32_arm_fix_exidx_coverage (asection **text_section_order,
11631 unsigned int num_text_sections,
85fdf906
AH		 11632 struct bfd_link_info *info,
11633 bfd_boolean merge_exidx_entries)
2468f9c9
PB		 11634{
11635 bfd *inp;
11636 unsigned int last_second_word = 0, i;
11637 asection *last_exidx_sec = NULL;
11638 asection *last_text_sec = NULL;
11639 int last_unwind_type = -1;
11640
11641 /* Walk over all EXIDX sections, and create backlinks from the corrsponding
11642 text sections. */
c72f2fb2 11643 for (inp = info->input_bfds; inp != NULL; inp = inp->link.next)
2468f9c9
PB		 11644 {
11645 asection *sec;
b38cadfb 11646
2468f9c9 11647 for (sec = inp->sections; sec != NULL; sec = sec->next)
99059e56 11648 {
2468f9c9
PB		 11649 struct bfd_elf_section_data *elf_sec = elf_section_data (sec);
11650 Elf_Internal_Shdr *hdr = &elf_sec->this_hdr;
b38cadfb 11651
dec9d5df 11652 if (!hdr || hdr->sh_type != SHT_ARM_EXIDX)
2468f9c9 11653 continue;
b38cadfb 11654
2468f9c9
PB		 11655 if (elf_sec->linked_to)
11656 {
11657 Elf_Internal_Shdr *linked_hdr
99059e56 11658 = &elf_section_data (elf_sec->linked_to)->this_hdr;
2468f9c9 11659 struct _arm_elf_section_data *linked_sec_arm_data
99059e56 11660 = get_arm_elf_section_data (linked_hdr->bfd_section);
2468f9c9
PB		 11661
11662 if (linked_sec_arm_data == NULL)
99059e56 11663 continue;
2468f9c9
PB		 11664
11665 /* Link this .ARM.exidx section back from the text section it
99059e56 11666 describes. */
2468f9c9
PB		 11667 linked_sec_arm_data->u.text.arm_exidx_sec = sec;
11668 }
11669 }
11670 }
11671
11672 /* Walk all text sections in order of increasing VMA. Eilminate duplicate
11673 index table entries (EXIDX_CANTUNWIND and inlined unwind opcodes),
91d6fa6a 11674 and add EXIDX_CANTUNWIND entries for sections with no unwind table data. */
2468f9c9
PB		 11675
11676 for (i = 0; i < num_text_sections; i++)
11677 {
11678 asection *sec = text_section_order[i];
11679 asection *exidx_sec;
11680 struct _arm_elf_section_data *arm_data = get_arm_elf_section_data (sec);
11681 struct _arm_elf_section_data *exidx_arm_data;
11682 bfd_byte *contents = NULL;
11683 int deleted_exidx_bytes = 0;
11684 bfd_vma j;
11685 arm_unwind_table_edit *unwind_edit_head = NULL;
11686 arm_unwind_table_edit *unwind_edit_tail = NULL;
11687 Elf_Internal_Shdr *hdr;
11688 bfd *ibfd;
11689
11690 if (arm_data == NULL)
99059e56 11691 continue;
2468f9c9
PB		 11692
11693 exidx_sec = arm_data->u.text.arm_exidx_sec;
11694 if (exidx_sec == NULL)
11695 {
11696 /* Section has no unwind data. */
11697 if (last_unwind_type == 0 || !last_exidx_sec)
11698 continue;
11699
11700 /* Ignore zero sized sections. */
11701 if (sec->size == 0)
11702 continue;
11703
11704 insert_cantunwind_after(last_text_sec, last_exidx_sec);
11705 last_unwind_type = 0;
11706 continue;
11707 }
11708
22a8f80e
PB		 11709 /* Skip /DISCARD/ sections. */
11710 if (bfd_is_abs_section (exidx_sec->output_section))
11711 continue;
11712
2468f9c9
PB		 11713 hdr = &elf_section_data (exidx_sec)->this_hdr;
11714 if (hdr->sh_type != SHT_ARM_EXIDX)
99059e56 11715 continue;
b38cadfb 11716
2468f9c9
PB		 11717 exidx_arm_data = get_arm_elf_section_data (exidx_sec);
11718 if (exidx_arm_data == NULL)
99059e56 11719 continue;
b38cadfb 11720
2468f9c9 11721 ibfd = exidx_sec->owner;
b38cadfb 11722
2468f9c9
PB		 11723 if (hdr->contents != NULL)
11724 contents = hdr->contents;
11725 else if (! bfd_malloc_and_get_section (ibfd, exidx_sec, &contents))
11726 /* An error? */
11727 continue;
11728
ac06903d
YU		 11729 if (last_unwind_type > 0)
11730 {
11731 unsigned int first_word = bfd_get_32 (ibfd, contents);
11732 /* Add cantunwind if first unwind item does not match section
11733 start. */
11734 if (first_word != sec->vma)
11735 {
11736 insert_cantunwind_after (last_text_sec, last_exidx_sec);
11737 last_unwind_type = 0;
11738 }
11739 }
11740
2468f9c9
PB		 11741 for (j = 0; j < hdr->sh_size; j += 8)
11742 {
11743 unsigned int second_word = bfd_get_32 (ibfd, contents + j + 4);
11744 int unwind_type;
11745 int elide = 0;
11746
11747 /* An EXIDX_CANTUNWIND entry. */
11748 if (second_word == 1)
11749 {
11750 if (last_unwind_type == 0)
11751 elide = 1;
11752 unwind_type = 0;
11753 }
11754 /* Inlined unwinding data. Merge if equal to previous. */
11755 else if ((second_word & 0x80000000) != 0)
11756 {
85fdf906
AH		 11757 if (merge_exidx_entries
11758 && last_second_word == second_word && last_unwind_type == 1)
2468f9c9
PB		 11759 elide = 1;
11760 unwind_type = 1;
11761 last_second_word = second_word;
11762 }
11763 /* Normal table entry. In theory we could merge these too,
11764 but duplicate entries are likely to be much less common. */
11765 else
11766 unwind_type = 2;
11767
491d01d3 11768 if (elide && !bfd_link_relocatable (info))
2468f9c9
PB		 11769 {
11770 add_unwind_table_edit (&unwind_edit_head, &unwind_edit_tail,
11771 DELETE_EXIDX_ENTRY, NULL, j / 8);
11772
11773 deleted_exidx_bytes += 8;
11774 }
11775
11776 last_unwind_type = unwind_type;
11777 }
11778
11779 /* Free contents if we allocated it ourselves. */
11780 if (contents != hdr->contents)
99059e56 11781 free (contents);
2468f9c9
PB		 11782
11783 /* Record edits to be applied later (in elf32_arm_write_section). */
11784 exidx_arm_data->u.exidx.unwind_edit_list = unwind_edit_head;
11785 exidx_arm_data->u.exidx.unwind_edit_tail = unwind_edit_tail;
b38cadfb 11786
2468f9c9
PB		 11787 if (deleted_exidx_bytes > 0)
11788 adjust_exidx_size(exidx_sec, -deleted_exidx_bytes);
11789
11790 last_exidx_sec = exidx_sec;
11791 last_text_sec = sec;
11792 }
11793
11794 /* Add terminating CANTUNWIND entry. */
491d01d3
YU		 11795 if (!bfd_link_relocatable (info) && last_exidx_sec
11796 && last_unwind_type != 0)
2468f9c9
PB		 11797 insert_cantunwind_after(last_text_sec, last_exidx_sec);
11798
11799 return TRUE;
11800}
11801
3e6b1042
DJ		 11802static bfd_boolean
11803elf32_arm_output_glue_section (struct bfd_link_info *info, bfd *obfd,
11804 bfd *ibfd, const char *name)
11805{
11806 asection *sec, *osec;
11807
3d4d4302 11808 sec = bfd_get_linker_section (ibfd, name);
3e6b1042
DJ		 11809 if (sec == NULL || (sec->flags & SEC_EXCLUDE) != 0)
11810 return TRUE;
11811
11812 osec = sec->output_section;
11813 if (elf32_arm_write_section (obfd, info, sec, sec->contents))
11814 return TRUE;
11815
11816 if (! bfd_set_section_contents (obfd, osec, sec->contents,
11817 sec->output_offset, sec->size))
11818 return FALSE;
11819
11820 return TRUE;
11821}
11822
11823static bfd_boolean
11824elf32_arm_final_link (bfd *abfd, struct bfd_link_info *info)
11825{
11826 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (info);
fe33d2fa 11827 asection *sec, *osec;
3e6b1042 11828
4dfe6ac6
NC		 11829 if (globals == NULL)
11830 return FALSE;
11831
3e6b1042
DJ		 11832 /* Invoke the regular ELF backend linker to do all the work. */
11833 if (!bfd_elf_final_link (abfd, info))
11834 return FALSE;
11835
fe33d2fa
CL		 11836 /* Process stub sections (eg BE8 encoding, ...). */
11837 struct elf32_arm_link_hash_table *htab = elf32_arm_hash_table (info);
7292b3ac 11838 unsigned int i;
cdb21a0a
NS		 11839 for (i=0; i<htab->top_id; i++)
11840 {
11841 sec = htab->stub_group[i].stub_sec;
11842 /* Only process it once, in its link_sec slot. */
11843 if (sec && i == htab->stub_group[i].link_sec->id)
11844 {
11845 osec = sec->output_section;
11846 elf32_arm_write_section (abfd, info, sec, sec->contents);
11847 if (! bfd_set_section_contents (abfd, osec, sec->contents,
11848 sec->output_offset, sec->size))
11849 return FALSE;
11850 }
fe33d2fa 11851 }
fe33d2fa 11852
3e6b1042
DJ		 11853 /* Write out any glue sections now that we have created all the
11854 stubs. */
11855 if (globals->bfd_of_glue_owner != NULL)
11856 {
11857 if (! elf32_arm_output_glue_section (info, abfd,
11858 globals->bfd_of_glue_owner,
11859 ARM2THUMB_GLUE_SECTION_NAME))
11860 return FALSE;
11861
11862 if (! elf32_arm_output_glue_section (info, abfd,
11863 globals->bfd_of_glue_owner,
11864 THUMB2ARM_GLUE_SECTION_NAME))
11865 return FALSE;
11866
11867 if (! elf32_arm_output_glue_section (info, abfd,
11868 globals->bfd_of_glue_owner,
11869 VFP11_ERRATUM_VENEER_SECTION_NAME))
11870 return FALSE;
11871
a504d23a
LA		 11872 if (! elf32_arm_output_glue_section (info, abfd,
11873 globals->bfd_of_glue_owner,
11874 STM32L4XX_ERRATUM_VENEER_SECTION_NAME))
11875 return FALSE;
11876
3e6b1042
DJ		 11877 if (! elf32_arm_output_glue_section (info, abfd,
11878 globals->bfd_of_glue_owner,
11879 ARM_BX_GLUE_SECTION_NAME))
11880 return FALSE;
11881 }
11882
11883 return TRUE;
11884}
11885
5968a7b8
NC		 11886/* Return a best guess for the machine number based on the attributes. */
11887
11888static unsigned int
11889bfd_arm_get_mach_from_attributes (bfd * abfd)
11890{
11891 int arch = bfd_elf_get_obj_attr_int (abfd, OBJ_ATTR_PROC, Tag_CPU_arch);
11892
11893 switch (arch)
11894 {
11895 case TAG_CPU_ARCH_V4: return bfd_mach_arm_4;
11896 case TAG_CPU_ARCH_V4T: return bfd_mach_arm_4T;
11897 case TAG_CPU_ARCH_V5T: return bfd_mach_arm_5T;
11898
11899 case TAG_CPU_ARCH_V5TE:
11900 {
11901 char * name;
11902
11903 BFD_ASSERT (Tag_CPU_name < NUM_KNOWN_OBJ_ATTRIBUTES);
11904 name = elf_known_obj_attributes (abfd) [OBJ_ATTR_PROC][Tag_CPU_name].s;
11905
11906 if (name)
11907 {
11908 if (strcmp (name, "IWMMXT2") == 0)
11909 return bfd_mach_arm_iWMMXt2;
11910
11911 if (strcmp (name, "IWMMXT") == 0)
6034aab8 11912 return bfd_mach_arm_iWMMXt;
088ca6c1
NC		 11913
11914 if (strcmp (name, "XSCALE") == 0)
11915 {
11916 int wmmx;
11917
11918 BFD_ASSERT (Tag_WMMX_arch < NUM_KNOWN_OBJ_ATTRIBUTES);
11919 wmmx = elf_known_obj_attributes (abfd) [OBJ_ATTR_PROC][Tag_WMMX_arch].i;
11920 switch (wmmx)
11921 {
11922 case 1: return bfd_mach_arm_iWMMXt;
11923 case 2: return bfd_mach_arm_iWMMXt2;
11924 default: return bfd_mach_arm_XScale;
11925 }
11926 }
5968a7b8
NC		 11927 }
11928
11929 return bfd_mach_arm_5TE;
11930 }
11931
11932 default:
11933 return bfd_mach_arm_unknown;
11934 }
11935}
11936
c178919b
NC		 11937/* Set the right machine number. */
11938
11939static bfd_boolean
57e8b36a 11940elf32_arm_object_p (bfd *abfd)
c178919b 11941{
5a6c6817 11942 unsigned int mach;
57e8b36a 11943
5a6c6817 11944 mach = bfd_arm_get_mach_from_notes (abfd, ARM_NOTE_SECTION);
c178919b 11945
5968a7b8
NC		 11946 if (mach == bfd_mach_arm_unknown)
11947 {
11948 if (elf_elfheader (abfd)->e_flags & EF_ARM_MAVERICK_FLOAT)
11949 mach = bfd_mach_arm_ep9312;
11950 else
11951 mach = bfd_arm_get_mach_from_attributes (abfd);
11952 }
c178919b 11953
5968a7b8 11954 bfd_default_set_arch_mach (abfd, bfd_arch_arm, mach);
c178919b
NC		 11955 return TRUE;
11956}
11957
fc830a83 11958/* Function to keep ARM specific flags in the ELF header. */
3c9458e9 11959
b34976b6 11960static bfd_boolean
57e8b36a 11961elf32_arm_set_private_flags (bfd *abfd, flagword flags)
252b5132
RH		 11962{
11963 if (elf_flags_init (abfd)
11964 && elf_elfheader (abfd)->e_flags != flags)
11965 {
fc830a83
NC		 11966 if (EF_ARM_EABI_VERSION (flags) == EF_ARM_EABI_UNKNOWN)
11967 {
fd2ec330 11968 if (flags & EF_ARM_INTERWORK)
d003868e
AM		 11969 (*_bfd_error_handler)
11970 (_("Warning: Not setting interworking flag of %B since it has already been specified as non-interworking"),
11971 abfd);
fc830a83 11972 else
d003868e
AM		 11973 _bfd_error_handler
11974 (_("Warning: Clearing the interworking flag of %B due to outside request"),
11975 abfd);
fc830a83 11976 }
252b5132
RH		 11977 }
11978 else
11979 {
11980 elf_elfheader (abfd)->e_flags = flags;
b34976b6 11981 elf_flags_init (abfd) = TRUE;
252b5132
RH		 11982 }
11983
b34976b6 11984 return TRUE;
252b5132
RH		 11985}
11986
fc830a83 11987/* Copy backend specific data from one object module to another. */
9b485d32 11988
b34976b6 11989static bfd_boolean
57e8b36a 11990elf32_arm_copy_private_bfd_data (bfd *ibfd, bfd *obfd)
252b5132
RH		 11991{
11992 flagword in_flags;
11993 flagword out_flags;
11994
0ffa91dd 11995 if (! is_arm_elf (ibfd) || ! is_arm_elf (obfd))
b34976b6 11996 return TRUE;
252b5132 11997
fc830a83 11998 in_flags = elf_elfheader (ibfd)->e_flags;
252b5132
RH		 11999 out_flags = elf_elfheader (obfd)->e_flags;
12000
fc830a83
NC		 12001 if (elf_flags_init (obfd)
12002 && EF_ARM_EABI_VERSION (out_flags) == EF_ARM_EABI_UNKNOWN
12003 && in_flags != out_flags)
252b5132 12004 {
252b5132 12005 /* Cannot mix APCS26 and APCS32 code. */
fd2ec330 12006 if ((in_flags & EF_ARM_APCS_26) != (out_flags & EF_ARM_APCS_26))
b34976b6 12007 return FALSE;
252b5132
RH		 12008
12009 /* Cannot mix float APCS and non-float APCS code. */
fd2ec330 12010 if ((in_flags & EF_ARM_APCS_FLOAT) != (out_flags & EF_ARM_APCS_FLOAT))
b34976b6 12011 return FALSE;
252b5132
RH		 12012
12013 /* If the src and dest have different interworking flags
99059e56 12014 then turn off the interworking bit. */
fd2ec330 12015 if ((in_flags & EF_ARM_INTERWORK) != (out_flags & EF_ARM_INTERWORK))
252b5132 12016 {
fd2ec330 12017 if (out_flags & EF_ARM_INTERWORK)
d003868e
AM		 12018 _bfd_error_handler
12019 (_("Warning: Clearing the interworking flag of %B because non-interworking code in %B has been linked with it"),
12020 obfd, ibfd);
252b5132 12021
fd2ec330 12022 in_flags &= ~EF_ARM_INTERWORK;
252b5132 12023 }
1006ba19
PB		 12024
12025 /* Likewise for PIC, though don't warn for this case. */
fd2ec330
PB		 12026 if ((in_flags & EF_ARM_PIC) != (out_flags & EF_ARM_PIC))
12027 in_flags &= ~EF_ARM_PIC;
252b5132
RH		 12028 }
12029
12030 elf_elfheader (obfd)->e_flags = in_flags;
b34976b6 12031 elf_flags_init (obfd) = TRUE;
252b5132 12032
e2349352 12033 return _bfd_elf_copy_private_bfd_data (ibfd, obfd);
ee065d83
PB		 12034}
12035
12036/* Values for Tag_ABI_PCS_R9_use. */
12037enum
12038{
12039 AEABI_R9_V6,
12040 AEABI_R9_SB,
12041 AEABI_R9_TLS,
12042 AEABI_R9_unused
12043};
12044
12045/* Values for Tag_ABI_PCS_RW_data. */
12046enum
12047{
12048 AEABI_PCS_RW_data_absolute,
12049 AEABI_PCS_RW_data_PCrel,
12050 AEABI_PCS_RW_data_SBrel,
12051 AEABI_PCS_RW_data_unused
12052};
12053
12054/* Values for Tag_ABI_enum_size. */
12055enum
12056{
12057 AEABI_enum_unused,
12058 AEABI_enum_short,
12059 AEABI_enum_wide,
12060 AEABI_enum_forced_wide
12061};
12062
104d59d1
JM		 12063/* Determine whether an object attribute tag takes an integer, a
12064 string or both. */
906e58ca 12065
104d59d1
JM		 12066static int
12067elf32_arm_obj_attrs_arg_type (int tag)
12068{
12069 if (tag == Tag_compatibility)
3483fe2e 12070 return ATTR_TYPE_FLAG_INT_VAL | ATTR_TYPE_FLAG_STR_VAL;
2d0bb761 12071 else if (tag == Tag_nodefaults)
3483fe2e
AS		 12072 return ATTR_TYPE_FLAG_INT_VAL | ATTR_TYPE_FLAG_NO_DEFAULT;
12073 else if (tag == Tag_CPU_raw_name || tag == Tag_CPU_name)
12074 return ATTR_TYPE_FLAG_STR_VAL;
104d59d1 12075 else if (tag < 32)
3483fe2e 12076 return ATTR_TYPE_FLAG_INT_VAL;
104d59d1 12077 else
3483fe2e 12078 return (tag & 1) != 0 ? ATTR_TYPE_FLAG_STR_VAL : ATTR_TYPE_FLAG_INT_VAL;
104d59d1
JM		 12079}
12080
5aa6ff7c
AS		 12081/* The ABI defines that Tag_conformance should be emitted first, and that
12082 Tag_nodefaults should be second (if either is defined). This sets those
12083 two positions, and bumps up the position of all the remaining tags to
12084 compensate. */
12085static int
12086elf32_arm_obj_attrs_order (int num)
12087{
3de4a297 12088 if (num == LEAST_KNOWN_OBJ_ATTRIBUTE)
5aa6ff7c 12089 return Tag_conformance;
3de4a297 12090 if (num == LEAST_KNOWN_OBJ_ATTRIBUTE + 1)
5aa6ff7c
AS		 12091 return Tag_nodefaults;
12092 if ((num - 2) < Tag_nodefaults)
12093 return num - 2;
12094 if ((num - 1) < Tag_conformance)
12095 return num - 1;
12096 return num;
12097}
12098
e8b36cd1
JM		 12099/* Attribute numbers >=64 (mod 128) can be safely ignored. */
12100static bfd_boolean
12101elf32_arm_obj_attrs_handle_unknown (bfd *abfd, int tag)
12102{
12103 if ((tag & 127) < 64)
12104 {
12105 _bfd_error_handler
12106 (_("%B: Unknown mandatory EABI object attribute %d"),
12107 abfd, tag);
12108 bfd_set_error (bfd_error_bad_value);
12109 return FALSE;
12110 }
12111 else
12112 {
12113 _bfd_error_handler
12114 (_("Warning: %B: Unknown EABI object attribute %d"),
12115 abfd, tag);
12116 return TRUE;
12117 }
12118}
12119
91e22acd
AS		 12120/* Read the architecture from the Tag_also_compatible_with attribute, if any.
12121 Returns -1 if no architecture could be read. */
12122
12123static int
12124get_secondary_compatible_arch (bfd *abfd)
12125{
12126 obj_attribute *attr =
12127 &elf_known_obj_attributes_proc (abfd)[Tag_also_compatible_with];
12128
12129 /* Note: the tag and its argument below are uleb128 values, though
12130 currently-defined values fit in one byte for each. */
12131 if (attr->s
12132 && attr->s[0] == Tag_CPU_arch
12133 && (attr->s[1] & 128) != 128
12134 && attr->s[2] == 0)
12135 return attr->s[1];
12136
12137 /* This tag is "safely ignorable", so don't complain if it looks funny. */
12138 return -1;
12139}
12140
12141/* Set, or unset, the architecture of the Tag_also_compatible_with attribute.
12142 The tag is removed if ARCH is -1. */
12143
8e79c3df 12144static void
91e22acd 12145set_secondary_compatible_arch (bfd *abfd, int arch)
8e79c3df 12146{
91e22acd
AS		 12147 obj_attribute *attr =
12148 &elf_known_obj_attributes_proc (abfd)[Tag_also_compatible_with];
8e79c3df 12149
91e22acd
AS		 12150 if (arch == -1)
12151 {
12152 attr->s = NULL;
12153 return;
8e79c3df 12154 }
91e22acd
AS		 12155
12156 /* Note: the tag and its argument below are uleb128 values, though
12157 currently-defined values fit in one byte for each. */
12158 if (!attr->s)
21d799b5 12159 attr->s = (char *) bfd_alloc (abfd, 3);
91e22acd
AS		 12160 attr->s[0] = Tag_CPU_arch;
12161 attr->s[1] = arch;
12162 attr->s[2] = '\0';
8e79c3df
CM		 12163}
12164
91e22acd
AS		 12165/* Combine two values for Tag_CPU_arch, taking secondary compatibility tags
12166 into account. */
12167
12168static int
12169tag_cpu_arch_combine (bfd *ibfd, int oldtag, int *secondary_compat_out,
12170 int newtag, int secondary_compat)
8e79c3df 12171{
91e22acd
AS		 12172#define T(X) TAG_CPU_ARCH_##X
12173 int tagl, tagh, result;
12174 const int v6t2[] =
12175 {
12176 T(V6T2), /* PRE_V4. */
12177 T(V6T2), /* V4. */
12178 T(V6T2), /* V4T. */
12179 T(V6T2), /* V5T. */
12180 T(V6T2), /* V5TE. */
12181 T(V6T2), /* V5TEJ. */
12182 T(V6T2), /* V6. */
12183 T(V7), /* V6KZ. */
12184 T(V6T2) /* V6T2. */
12185 };
12186 const int v6k[] =
12187 {
12188 T(V6K), /* PRE_V4. */
12189 T(V6K), /* V4. */
12190 T(V6K), /* V4T. */
12191 T(V6K), /* V5T. */
12192 T(V6K), /* V5TE. */
12193 T(V6K), /* V5TEJ. */
12194 T(V6K), /* V6. */
12195 T(V6KZ), /* V6KZ. */
12196 T(V7), /* V6T2. */
12197 T(V6K) /* V6K. */
12198 };
12199 const int v7[] =
12200 {
12201 T(V7), /* PRE_V4. */
12202 T(V7), /* V4. */
12203 T(V7), /* V4T. */
12204 T(V7), /* V5T. */
12205 T(V7), /* V5TE. */
12206 T(V7), /* V5TEJ. */
12207 T(V7), /* V6. */
12208 T(V7), /* V6KZ. */
12209 T(V7), /* V6T2. */
12210 T(V7), /* V6K. */
12211 T(V7) /* V7. */
12212 };
12213 const int v6_m[] =
12214 {
12215 -1, /* PRE_V4. */
12216 -1, /* V4. */
12217 T(V6K), /* V4T. */
12218 T(V6K), /* V5T. */
12219 T(V6K), /* V5TE. */
12220 T(V6K), /* V5TEJ. */
12221 T(V6K), /* V6. */
12222 T(V6KZ), /* V6KZ. */
12223 T(V7), /* V6T2. */
12224 T(V6K), /* V6K. */
12225 T(V7), /* V7. */
12226 T(V6_M) /* V6_M. */
12227 };
12228 const int v6s_m[] =
12229 {
12230 -1, /* PRE_V4. */
12231 -1, /* V4. */
12232 T(V6K), /* V4T. */
12233 T(V6K), /* V5T. */
12234 T(V6K), /* V5TE. */
12235 T(V6K), /* V5TEJ. */
12236 T(V6K), /* V6. */
12237 T(V6KZ), /* V6KZ. */
12238 T(V7), /* V6T2. */
12239 T(V6K), /* V6K. */
12240 T(V7), /* V7. */
12241 T(V6S_M), /* V6_M. */
12242 T(V6S_M) /* V6S_M. */
12243 };
9e3c6df6
PB		 12244 const int v7e_m[] =
12245 {
12246 -1, /* PRE_V4. */
12247 -1, /* V4. */
12248 T(V7E_M), /* V4T. */
12249 T(V7E_M), /* V5T. */
12250 T(V7E_M), /* V5TE. */
12251 T(V7E_M), /* V5TEJ. */
12252 T(V7E_M), /* V6. */
12253 T(V7E_M), /* V6KZ. */
12254 T(V7E_M), /* V6T2. */
12255 T(V7E_M), /* V6K. */
12256 T(V7E_M), /* V7. */
12257 T(V7E_M), /* V6_M. */
12258 T(V7E_M), /* V6S_M. */
12259 T(V7E_M) /* V7E_M. */
12260 };
bca38921
MGD		 12261 const int v8[] =
12262 {
12263 T(V8), /* PRE_V4. */
12264 T(V8), /* V4. */
12265 T(V8), /* V4T. */
12266 T(V8), /* V5T. */
12267 T(V8), /* V5TE. */
12268 T(V8), /* V5TEJ. */
12269 T(V8), /* V6. */
12270 T(V8), /* V6KZ. */
12271 T(V8), /* V6T2. */
12272 T(V8), /* V6K. */
12273 T(V8), /* V7. */
12274 T(V8), /* V6_M. */
12275 T(V8), /* V6S_M. */
12276 T(V8), /* V7E_M. */
12277 T(V8) /* V8. */
12278 };
2fd158eb
TP		 12279 const int v8m_baseline[] =
12280 {
12281 -1, /* PRE_V4. */
12282 -1, /* V4. */
12283 -1, /* V4T. */
12284 -1, /* V5T. */
12285 -1, /* V5TE. */
12286 -1, /* V5TEJ. */
12287 -1, /* V6. */
12288 -1, /* V6KZ. */
12289 -1, /* V6T2. */
12290 -1, /* V6K. */
12291 -1, /* V7. */
12292 T(V8M_BASE), /* V6_M. */
12293 T(V8M_BASE), /* V6S_M. */
12294 -1, /* V7E_M. */
12295 -1, /* V8. */
12296 -1,
12297 T(V8M_BASE) /* V8-M BASELINE. */
12298 };
12299 const int v8m_mainline[] =
12300 {
12301 -1, /* PRE_V4. */
12302 -1, /* V4. */
12303 -1, /* V4T. */
12304 -1, /* V5T. */
12305 -1, /* V5TE. */
12306 -1, /* V5TEJ. */
12307 -1, /* V6. */
12308 -1, /* V6KZ. */
12309 -1, /* V6T2. */
12310 -1, /* V6K. */
12311 T(V8M_MAIN), /* V7. */
12312 T(V8M_MAIN), /* V6_M. */
12313 T(V8M_MAIN), /* V6S_M. */
12314 T(V8M_MAIN), /* V7E_M. */
12315 -1, /* V8. */
12316 -1,
12317 T(V8M_MAIN), /* V8-M BASELINE. */
12318 T(V8M_MAIN) /* V8-M MAINLINE. */
12319 };
91e22acd
AS		 12320 const int v4t_plus_v6_m[] =
12321 {
12322 -1, /* PRE_V4. */
12323 -1, /* V4. */
12324 T(V4T), /* V4T. */
12325 T(V5T), /* V5T. */
12326 T(V5TE), /* V5TE. */
12327 T(V5TEJ), /* V5TEJ. */
12328 T(V6), /* V6. */
12329 T(V6KZ), /* V6KZ. */
12330 T(V6T2), /* V6T2. */
12331 T(V6K), /* V6K. */
12332 T(V7), /* V7. */
12333 T(V6_M), /* V6_M. */
12334 T(V6S_M), /* V6S_M. */
9e3c6df6 12335 T(V7E_M), /* V7E_M. */
bca38921 12336 T(V8), /* V8. */
4ed7ed8d 12337 -1, /* Unused. */
2fd158eb
TP		 12338 T(V8M_BASE), /* V8-M BASELINE. */
12339 T(V8M_MAIN), /* V8-M MAINLINE. */
91e22acd
AS		 12340 T(V4T_PLUS_V6_M) /* V4T plus V6_M. */
12341 };
12342 const int *comb[] =
12343 {
12344 v6t2,
12345 v6k,
12346 v7,
12347 v6_m,
12348 v6s_m,
9e3c6df6 12349 v7e_m,
bca38921 12350 v8,
4ed7ed8d 12351 NULL,
2fd158eb
TP		 12352 v8m_baseline,
12353 v8m_mainline,
91e22acd
AS		 12354 /* Pseudo-architecture. */
12355 v4t_plus_v6_m
12356 };
12357
12358 /* Check we've not got a higher architecture than we know about. */
12359
9e3c6df6 12360 if (oldtag > MAX_TAG_CPU_ARCH || newtag > MAX_TAG_CPU_ARCH)
91e22acd 12361 {
3895f852 12362 _bfd_error_handler (_("error: %B: Unknown CPU architecture"), ibfd);
91e22acd
AS		 12363 return -1;
12364 }
12365
12366 /* Override old tag if we have a Tag_also_compatible_with on the output. */
12367
12368 if ((oldtag == T(V6_M) && *secondary_compat_out == T(V4T))
12369 || (oldtag == T(V4T) && *secondary_compat_out == T(V6_M)))
12370 oldtag = T(V4T_PLUS_V6_M);
12371
12372 /* And override the new tag if we have a Tag_also_compatible_with on the
12373 input. */
12374
12375 if ((newtag == T(V6_M) && secondary_compat == T(V4T))
12376 || (newtag == T(V4T) && secondary_compat == T(V6_M)))
12377 newtag = T(V4T_PLUS_V6_M);
12378
12379 tagl = (oldtag < newtag) ? oldtag : newtag;
12380 result = tagh = (oldtag > newtag) ? oldtag : newtag;
12381
12382 /* Architectures before V6KZ add features monotonically. */
12383 if (tagh <= TAG_CPU_ARCH_V6KZ)
12384 return result;
12385
4ed7ed8d 12386 result = comb[tagh - T(V6T2)] ? comb[tagh - T(V6T2)][tagl] : -1;
91e22acd
AS		 12387
12388 /* Use Tag_CPU_arch == V4T and Tag_also_compatible_with (Tag_CPU_arch V6_M)
12389 as the canonical version. */
12390 if (result == T(V4T_PLUS_V6_M))
12391 {
12392 result = T(V4T);
12393 *secondary_compat_out = T(V6_M);
12394 }
12395 else
12396 *secondary_compat_out = -1;
12397
12398 if (result == -1)
12399 {
3895f852 12400 _bfd_error_handler (_("error: %B: Conflicting CPU architectures %d/%d"),
91e22acd
AS		 12401 ibfd, oldtag, newtag);
12402 return -1;
12403 }
12404
12405 return result;
12406#undef T
8e79c3df
CM		 12407}
12408
ac56ee8f
MGD		 12409/* Query attributes object to see if integer divide instructions may be
12410 present in an object. */
12411static bfd_boolean
12412elf32_arm_attributes_accept_div (const obj_attribute *attr)
12413{
12414 int arch = attr[Tag_CPU_arch].i;
12415 int profile = attr[Tag_CPU_arch_profile].i;
12416
12417 switch (attr[Tag_DIV_use].i)
12418 {
12419 case 0:
12420 /* Integer divide allowed if instruction contained in archetecture. */
12421 if (arch == TAG_CPU_ARCH_V7 && (profile == 'R' || profile == 'M'))
12422 return TRUE;
12423 else if (arch >= TAG_CPU_ARCH_V7E_M)
12424 return TRUE;
12425 else
12426 return FALSE;
12427
12428 case 1:
12429 /* Integer divide explicitly prohibited. */
12430 return FALSE;
12431
12432 default:
12433 /* Unrecognised case - treat as allowing divide everywhere. */
12434 case 2:
12435 /* Integer divide allowed in ARM state. */
12436 return TRUE;
12437 }
12438}
12439
12440/* Query attributes object to see if integer divide instructions are
12441 forbidden to be in the object. This is not the inverse of
12442 elf32_arm_attributes_accept_div. */
12443static bfd_boolean
12444elf32_arm_attributes_forbid_div (const obj_attribute *attr)
12445{
12446 return attr[Tag_DIV_use].i == 1;
12447}
12448
ee065d83
PB		 12449/* Merge EABI object attributes from IBFD into OBFD. Raise an error if there
12450 are conflicting attributes. */
906e58ca 12451
ee065d83
PB		 12452static bfd_boolean
12453elf32_arm_merge_eabi_attributes (bfd *ibfd, bfd *obfd)
12454{
104d59d1
JM		 12455 obj_attribute *in_attr;
12456 obj_attribute *out_attr;
ee065d83
PB		 12457 /* Some tags have 0 = don't care, 1 = strong requirement,
12458 2 = weak requirement. */
91e22acd 12459 static const int order_021[3] = {0, 2, 1};
ee065d83 12460 int i;
91e22acd 12461 bfd_boolean result = TRUE;
9274e9de 12462 const char *sec_name = get_elf_backend_data (ibfd)->obj_attrs_section;
ee065d83 12463
3e6b1042
DJ		 12464 /* Skip the linker stubs file. This preserves previous behavior
12465 of accepting unknown attributes in the first input file - but
12466 is that a bug? */
12467 if (ibfd->flags & BFD_LINKER_CREATED)
12468 return TRUE;
12469
9274e9de
TG		 12470 /* Skip any input that hasn't attribute section.
12471 This enables to link object files without attribute section with
12472 any others. */
12473 if (bfd_get_section_by_name (ibfd, sec_name) == NULL)
12474 return TRUE;
12475
104d59d1 12476 if (!elf_known_obj_attributes_proc (obfd)[0].i)
ee065d83
PB		 12477 {
12478 /* This is the first object. Copy the attributes. */
104d59d1 12479 _bfd_elf_copy_obj_attributes (ibfd, obfd);
004ae526 12480
cd21e546
MGD		 12481 out_attr = elf_known_obj_attributes_proc (obfd);
12482
004ae526
PB		 12483 /* Use the Tag_null value to indicate the attributes have been
12484 initialized. */
cd21e546 12485 out_attr[0].i = 1;
004ae526 12486
cd21e546
MGD		 12487 /* We do not output objects with Tag_MPextension_use_legacy - we move
12488 the attribute's value to Tag_MPextension_use. */
12489 if (out_attr[Tag_MPextension_use_legacy].i != 0)
12490 {
12491 if (out_attr[Tag_MPextension_use].i != 0
12492 && out_attr[Tag_MPextension_use_legacy].i
99059e56 12493 != out_attr[Tag_MPextension_use].i)
cd21e546
MGD		 12494 {
12495 _bfd_error_handler
12496 (_("Error: %B has both the current and legacy "
12497 "Tag_MPextension_use attributes"), ibfd);
12498 result = FALSE;
12499 }
12500
12501 out_attr[Tag_MPextension_use] =
12502 out_attr[Tag_MPextension_use_legacy];
12503 out_attr[Tag_MPextension_use_legacy].type = 0;
12504 out_attr[Tag_MPextension_use_legacy].i = 0;
12505 }
12506
12507 return result;
ee065d83
PB		 12508 }
12509
104d59d1
JM		 12510 in_attr = elf_known_obj_attributes_proc (ibfd);
12511 out_attr = elf_known_obj_attributes_proc (obfd);
ee065d83
PB		 12512 /* This needs to happen before Tag_ABI_FP_number_model is merged. */
12513 if (in_attr[Tag_ABI_VFP_args].i != out_attr[Tag_ABI_VFP_args].i)
12514 {
5c294fee
TG		 12515 /* Ignore mismatches if the object doesn't use floating point or is
12516 floating point ABI independent. */
12517 if (out_attr[Tag_ABI_FP_number_model].i == AEABI_FP_number_model_none
12518 || (in_attr[Tag_ABI_FP_number_model].i != AEABI_FP_number_model_none
12519 && out_attr[Tag_ABI_VFP_args].i == AEABI_VFP_args_compatible))
ee065d83 12520 out_attr[Tag_ABI_VFP_args].i = in_attr[Tag_ABI_VFP_args].i;
5c294fee
TG		 12521 else if (in_attr[Tag_ABI_FP_number_model].i != AEABI_FP_number_model_none
12522 && in_attr[Tag_ABI_VFP_args].i != AEABI_VFP_args_compatible)
ee065d83
PB		 12523 {
12524 _bfd_error_handler
3895f852 12525 (_("error: %B uses VFP register arguments, %B does not"),
deddc40b
NS		 12526 in_attr[Tag_ABI_VFP_args].i ? ibfd : obfd,
12527 in_attr[Tag_ABI_VFP_args].i ? obfd : ibfd);
91e22acd 12528 result = FALSE;
ee065d83
PB		 12529 }
12530 }
12531
3de4a297 12532 for (i = LEAST_KNOWN_OBJ_ATTRIBUTE; i < NUM_KNOWN_OBJ_ATTRIBUTES; i++)
ee065d83
PB		 12533 {
12534 /* Merge this attribute with existing attributes. */
12535 switch (i)
12536 {
12537 case Tag_CPU_raw_name:
12538 case Tag_CPU_name:
6a631e86 12539 /* These are merged after Tag_CPU_arch. */
ee065d83
PB		 12540 break;
12541
12542 case Tag_ABI_optimization_goals:
12543 case Tag_ABI_FP_optimization_goals:
12544 /* Use the first value seen. */
12545 break;
12546
12547 case Tag_CPU_arch:
91e22acd
AS		 12548 {
12549 int secondary_compat = -1, secondary_compat_out = -1;
12550 unsigned int saved_out_attr = out_attr[i].i;
70e99720
TG		 12551 int arch_attr;
12552 static const char *name_table[] =
12553 {
91e22acd
AS		 12554 /* These aren't real CPU names, but we can't guess
12555 that from the architecture version alone. */
12556 "Pre v4",
12557 "ARM v4",
12558 "ARM v4T",
12559 "ARM v5T",
12560 "ARM v5TE",
12561 "ARM v5TEJ",
12562 "ARM v6",
12563 "ARM v6KZ",
12564 "ARM v6T2",
12565 "ARM v6K",
12566 "ARM v7",
12567 "ARM v6-M",
bca38921 12568 "ARM v6S-M",
2fd158eb
TP		 12569 "ARM v8",
12570 "",
12571 "ARM v8-M.baseline",
12572 "ARM v8-M.mainline",
91e22acd
AS		 12573 };
12574
12575 /* Merge Tag_CPU_arch and Tag_also_compatible_with. */
12576 secondary_compat = get_secondary_compatible_arch (ibfd);
12577 secondary_compat_out = get_secondary_compatible_arch (obfd);
70e99720
TG		 12578 arch_attr = tag_cpu_arch_combine (ibfd, out_attr[i].i,
12579 &secondary_compat_out,
12580 in_attr[i].i,
12581 secondary_compat);
12582
12583 /* Return with error if failed to merge. */
12584 if (arch_attr == -1)
12585 return FALSE;
12586
12587 out_attr[i].i = arch_attr;
12588
91e22acd
AS		 12589 set_secondary_compatible_arch (obfd, secondary_compat_out);
12590
12591 /* Merge Tag_CPU_name and Tag_CPU_raw_name. */
12592 if (out_attr[i].i == saved_out_attr)
12593 ; /* Leave the names alone. */
12594 else if (out_attr[i].i == in_attr[i].i)
12595 {
12596 /* The output architecture has been changed to match the
12597 input architecture. Use the input names. */
12598 out_attr[Tag_CPU_name].s = in_attr[Tag_CPU_name].s
12599 ? _bfd_elf_attr_strdup (obfd, in_attr[Tag_CPU_name].s)
12600 : NULL;
12601 out_attr[Tag_CPU_raw_name].s = in_attr[Tag_CPU_raw_name].s
12602 ? _bfd_elf_attr_strdup (obfd, in_attr[Tag_CPU_raw_name].s)
12603 : NULL;
12604 }
12605 else
12606 {
12607 out_attr[Tag_CPU_name].s = NULL;
12608 out_attr[Tag_CPU_raw_name].s = NULL;
12609 }
12610
12611 /* If we still don't have a value for Tag_CPU_name,
12612 make one up now. Tag_CPU_raw_name remains blank. */
12613 if (out_attr[Tag_CPU_name].s == NULL
12614 && out_attr[i].i < ARRAY_SIZE (name_table))
12615 out_attr[Tag_CPU_name].s =
12616 _bfd_elf_attr_strdup (obfd, name_table[out_attr[i].i]);
12617 }
12618 break;
12619
ee065d83
PB		 12620 case Tag_ARM_ISA_use:
12621 case Tag_THUMB_ISA_use:
ee065d83 12622 case Tag_WMMX_arch:
91e22acd
AS		 12623 case Tag_Advanced_SIMD_arch:
12624 /* ??? Do Advanced_SIMD (NEON) and WMMX conflict? */
ee065d83 12625 case Tag_ABI_FP_rounding:
ee065d83
PB		 12626 case Tag_ABI_FP_exceptions:
12627 case Tag_ABI_FP_user_exceptions:
12628 case Tag_ABI_FP_number_model:
75375b3e 12629 case Tag_FP_HP_extension:
91e22acd
AS		 12630 case Tag_CPU_unaligned_access:
12631 case Tag_T2EE_use:
91e22acd 12632 case Tag_MPextension_use:
ee065d83
PB		 12633 /* Use the largest value specified. */
12634 if (in_attr[i].i > out_attr[i].i)
12635 out_attr[i].i = in_attr[i].i;
12636 break;
12637
75375b3e 12638 case Tag_ABI_align_preserved:
91e22acd
AS		 12639 case Tag_ABI_PCS_RO_data:
12640 /* Use the smallest value specified. */
12641 if (in_attr[i].i < out_attr[i].i)
12642 out_attr[i].i = in_attr[i].i;
12643 break;
12644
75375b3e 12645 case Tag_ABI_align_needed:
91e22acd 12646 if ((in_attr[i].i > 0 || out_attr[i].i > 0)
75375b3e
MGD		 12647 && (in_attr[Tag_ABI_align_preserved].i == 0
12648 || out_attr[Tag_ABI_align_preserved].i == 0))
ee065d83 12649 {
91e22acd
AS		 12650 /* This error message should be enabled once all non-conformant
12651 binaries in the toolchain have had the attributes set
12652 properly.
ee065d83 12653 _bfd_error_handler
3895f852 12654 (_("error: %B: 8-byte data alignment conflicts with %B"),
91e22acd
AS		 12655 obfd, ibfd);
12656 result = FALSE; */
ee065d83 12657 }
91e22acd
AS		 12658 /* Fall through. */
12659 case Tag_ABI_FP_denormal:
12660 case Tag_ABI_PCS_GOT_use:
12661 /* Use the "greatest" from the sequence 0, 2, 1, or the largest
12662 value if greater than 2 (for future-proofing). */
12663 if ((in_attr[i].i > 2 && in_attr[i].i > out_attr[i].i)
12664 || (in_attr[i].i <= 2 && out_attr[i].i <= 2
12665 && order_021[in_attr[i].i] > order_021[out_attr[i].i]))
ee065d83
PB		 12666 out_attr[i].i = in_attr[i].i;
12667 break;
91e22acd 12668
75375b3e
MGD		 12669 case Tag_Virtualization_use:
12670 /* The virtualization tag effectively stores two bits of
12671 information: the intended use of TrustZone (in bit 0), and the
12672 intended use of Virtualization (in bit 1). */
12673 if (out_attr[i].i == 0)
12674 out_attr[i].i = in_attr[i].i;
12675 else if (in_attr[i].i != 0
12676 && in_attr[i].i != out_attr[i].i)
12677 {
12678 if (in_attr[i].i <= 3 && out_attr[i].i <= 3)
12679 out_attr[i].i = 3;
12680 else
12681 {
12682 _bfd_error_handler
12683 (_("error: %B: unable to merge virtualization attributes "
12684 "with %B"),
12685 obfd, ibfd);
12686 result = FALSE;
12687 }
12688 }
12689 break;
91e22acd
AS		 12690
12691 case Tag_CPU_arch_profile:
12692 if (out_attr[i].i != in_attr[i].i)
12693 {
12694 /* 0 will merge with anything.
12695 'A' and 'S' merge to 'A'.
12696 'R' and 'S' merge to 'R'.
99059e56 12697 'M' and 'A|R|S' is an error. */
91e22acd
AS		 12698 if (out_attr[i].i == 0
12699 || (out_attr[i].i == 'S'
12700 && (in_attr[i].i == 'A' || in_attr[i].i == 'R')))
12701 out_attr[i].i = in_attr[i].i;
12702 else if (in_attr[i].i == 0
12703 || (in_attr[i].i == 'S'
12704 && (out_attr[i].i == 'A' || out_attr[i].i == 'R')))
6a631e86 12705 ; /* Do nothing. */
91e22acd
AS		 12706 else
12707 {
12708 _bfd_error_handler
3895f852 12709 (_("error: %B: Conflicting architecture profiles %c/%c"),
91e22acd
AS		 12710 ibfd,
12711 in_attr[i].i ? in_attr[i].i : '0',
12712 out_attr[i].i ? out_attr[i].i : '0');
12713 result = FALSE;
12714 }
12715 }
12716 break;
15afaa63
TP		 12717
12718 case Tag_DSP_extension:
12719 /* No need to change output value if any of:
12720 - pre (<=) ARMv5T input architecture (do not have DSP)
12721 - M input profile not ARMv7E-M and do not have DSP. */
12722 if (in_attr[Tag_CPU_arch].i <= 3
12723 || (in_attr[Tag_CPU_arch_profile].i == 'M'
12724 && in_attr[Tag_CPU_arch].i != 13
12725 && in_attr[i].i == 0))
12726 ; /* Do nothing. */
12727 /* Output value should be 0 if DSP part of architecture, ie.
12728 - post (>=) ARMv5te architecture output
12729 - A, R or S profile output or ARMv7E-M output architecture. */
12730 else if (out_attr[Tag_CPU_arch].i >= 4
12731 && (out_attr[Tag_CPU_arch_profile].i == 'A'
12732 || out_attr[Tag_CPU_arch_profile].i == 'R'
12733 || out_attr[Tag_CPU_arch_profile].i == 'S'
12734 || out_attr[Tag_CPU_arch].i == 13))
12735 out_attr[i].i = 0;
12736 /* Otherwise, DSP instructions are added and not part of output
12737 architecture. */
12738 else
12739 out_attr[i].i = 1;
12740 break;
12741
75375b3e 12742 case Tag_FP_arch:
62f3b8c8 12743 {
4547cb56
NC		 12744 /* Tag_ABI_HardFP_use is handled along with Tag_FP_arch since
12745 the meaning of Tag_ABI_HardFP_use depends on Tag_FP_arch
12746 when it's 0. It might mean absence of FP hardware if
99654aaf 12747 Tag_FP_arch is zero. */
4547cb56 12748
a715796b 12749#define VFP_VERSION_COUNT 9
62f3b8c8
PB		 12750 static const struct
12751 {
12752 int ver;
12753 int regs;
bca38921 12754 } vfp_versions[VFP_VERSION_COUNT] =
62f3b8c8
PB		 12755 {
12756 {0, 0},
12757 {1, 16},
12758 {2, 16},
12759 {3, 32},
12760 {3, 16},
12761 {4, 32},
bca38921 12762 {4, 16},
a715796b
TG		 12763 {8, 32},
12764 {8, 16}
62f3b8c8
PB		 12765 };
12766 int ver;
12767 int regs;
12768 int newval;
12769
4547cb56
NC		 12770 /* If the output has no requirement about FP hardware,
12771 follow the requirement of the input. */
12772 if (out_attr[i].i == 0)
12773 {
12774 BFD_ASSERT (out_attr[Tag_ABI_HardFP_use].i == 0);
12775 out_attr[i].i = in_attr[i].i;
12776 out_attr[Tag_ABI_HardFP_use].i
12777 = in_attr[Tag_ABI_HardFP_use].i;
12778 break;
12779 }
12780 /* If the input has no requirement about FP hardware, do
12781 nothing. */
12782 else if (in_attr[i].i == 0)
12783 {
12784 BFD_ASSERT (in_attr[Tag_ABI_HardFP_use].i == 0);
12785 break;
12786 }
12787
12788 /* Both the input and the output have nonzero Tag_FP_arch.
99654aaf 12789 So Tag_ABI_HardFP_use is implied by Tag_FP_arch when it's zero. */
4547cb56
NC		 12790
12791 /* If both the input and the output have zero Tag_ABI_HardFP_use,
12792 do nothing. */
12793 if (in_attr[Tag_ABI_HardFP_use].i == 0
12794 && out_attr[Tag_ABI_HardFP_use].i == 0)
12795 ;
12796 /* If the input and the output have different Tag_ABI_HardFP_use,
99654aaf 12797 the combination of them is 0 (implied by Tag_FP_arch). */
4547cb56
NC		 12798 else if (in_attr[Tag_ABI_HardFP_use].i
12799 != out_attr[Tag_ABI_HardFP_use].i)
99654aaf 12800 out_attr[Tag_ABI_HardFP_use].i = 0;
4547cb56
NC		 12801
12802 /* Now we can handle Tag_FP_arch. */
12803
bca38921
MGD		 12804 /* Values of VFP_VERSION_COUNT or more aren't defined, so just
12805 pick the biggest. */
12806 if (in_attr[i].i >= VFP_VERSION_COUNT
12807 && in_attr[i].i > out_attr[i].i)
62f3b8c8
PB		 12808 {
12809 out_attr[i] = in_attr[i];
12810 break;
12811 }
12812 /* The output uses the superset of input features
12813 (ISA version) and registers. */
12814 ver = vfp_versions[in_attr[i].i].ver;
12815 if (ver < vfp_versions[out_attr[i].i].ver)
12816 ver = vfp_versions[out_attr[i].i].ver;
12817 regs = vfp_versions[in_attr[i].i].regs;
12818 if (regs < vfp_versions[out_attr[i].i].regs)
12819 regs = vfp_versions[out_attr[i].i].regs;
12820 /* This assumes all possible supersets are also a valid
99059e56 12821 options. */
bca38921 12822 for (newval = VFP_VERSION_COUNT - 1; newval > 0; newval--)
62f3b8c8
PB		 12823 {
12824 if (regs == vfp_versions[newval].regs
12825 && ver == vfp_versions[newval].ver)
12826 break;
12827 }
12828 out_attr[i].i = newval;
12829 }
b1cc4aeb 12830 break;
ee065d83
PB		 12831 case Tag_PCS_config:
12832 if (out_attr[i].i == 0)
12833 out_attr[i].i = in_attr[i].i;
b6009aca 12834 else if (in_attr[i].i != 0 && out_attr[i].i != in_attr[i].i)
ee065d83
PB		 12835 {
12836 /* It's sometimes ok to mix different configs, so this is only
99059e56 12837 a warning. */
ee065d83
PB		 12838 _bfd_error_handler
12839 (_("Warning: %B: Conflicting platform configuration"), ibfd);
12840 }
12841 break;
12842 case Tag_ABI_PCS_R9_use:
004ae526
PB		 12843 if (in_attr[i].i != out_attr[i].i
12844 && out_attr[i].i != AEABI_R9_unused
ee065d83
PB		 12845 && in_attr[i].i != AEABI_R9_unused)
12846 {
12847 _bfd_error_handler
3895f852 12848 (_("error: %B: Conflicting use of R9"), ibfd);
91e22acd 12849 result = FALSE;
ee065d83
PB		 12850 }
12851 if (out_attr[i].i == AEABI_R9_unused)
12852 out_attr[i].i = in_attr[i].i;
12853 break;
12854 case Tag_ABI_PCS_RW_data:
12855 if (in_attr[i].i == AEABI_PCS_RW_data_SBrel
12856 && out_attr[Tag_ABI_PCS_R9_use].i != AEABI_R9_SB
12857 && out_attr[Tag_ABI_PCS_R9_use].i != AEABI_R9_unused)
12858 {
12859 _bfd_error_handler
3895f852 12860 (_("error: %B: SB relative addressing conflicts with use of R9"),
ee065d83 12861 ibfd);
91e22acd 12862 result = FALSE;
ee065d83
PB		 12863 }
12864 /* Use the smallest value specified. */
12865 if (in_attr[i].i < out_attr[i].i)
12866 out_attr[i].i = in_attr[i].i;
12867 break;
ee065d83 12868 case Tag_ABI_PCS_wchar_t:
a9dc9481
JM		 12869 if (out_attr[i].i && in_attr[i].i && out_attr[i].i != in_attr[i].i
12870 && !elf_arm_tdata (obfd)->no_wchar_size_warning)
ee065d83
PB		 12871 {
12872 _bfd_error_handler
a9dc9481
JM		 12873 (_("warning: %B uses %u-byte wchar_t yet the output is to use %u-byte wchar_t; use of wchar_t values across objects may fail"),
12874 ibfd, in_attr[i].i, out_attr[i].i);
ee065d83 12875 }
a9dc9481 12876 else if (in_attr[i].i && !out_attr[i].i)
ee065d83
PB		 12877 out_attr[i].i = in_attr[i].i;
12878 break;
ee065d83
PB		 12879 case Tag_ABI_enum_size:
12880 if (in_attr[i].i != AEABI_enum_unused)
12881 {
12882 if (out_attr[i].i == AEABI_enum_unused
12883 || out_attr[i].i == AEABI_enum_forced_wide)
12884 {
12885 /* The existing object is compatible with anything.
12886 Use whatever requirements the new object has. */
12887 out_attr[i].i = in_attr[i].i;
12888 }
12889 else if (in_attr[i].i != AEABI_enum_forced_wide
bf21ed78 12890 && out_attr[i].i != in_attr[i].i
0ffa91dd 12891 && !elf_arm_tdata (obfd)->no_enum_size_warning)
ee065d83 12892 {
91e22acd 12893 static const char *aeabi_enum_names[] =
bf21ed78 12894 { "", "variable-size", "32-bit", "" };
91e22acd
AS		 12895 const char *in_name =
12896 in_attr[i].i < ARRAY_SIZE(aeabi_enum_names)
12897 ? aeabi_enum_names[in_attr[i].i]
12898 : "<unknown>";
12899 const char *out_name =
12900 out_attr[i].i < ARRAY_SIZE(aeabi_enum_names)
12901 ? aeabi_enum_names[out_attr[i].i]
12902 : "<unknown>";
ee065d83 12903 _bfd_error_handler
bf21ed78 12904 (_("warning: %B uses %s enums yet the output is to use %s enums; use of enum values across objects may fail"),
91e22acd 12905 ibfd, in_name, out_name);
ee065d83
PB		 12906 }
12907 }
12908 break;
12909 case Tag_ABI_VFP_args:
12910 /* Aready done. */
12911 break;
12912 case Tag_ABI_WMMX_args:
12913 if (in_attr[i].i != out_attr[i].i)
12914 {
12915 _bfd_error_handler
3895f852 12916 (_("error: %B uses iWMMXt register arguments, %B does not"),
ee065d83 12917 ibfd, obfd);
91e22acd 12918 result = FALSE;
ee065d83
PB		 12919 }
12920 break;
7b86a9fa
AS		 12921 case Tag_compatibility:
12922 /* Merged in target-independent code. */
12923 break;
91e22acd 12924 case Tag_ABI_HardFP_use:
4547cb56 12925 /* This is handled along with Tag_FP_arch. */
91e22acd
AS		 12926 break;
12927 case Tag_ABI_FP_16bit_format:
12928 if (in_attr[i].i != 0 && out_attr[i].i != 0)
12929 {
12930 if (in_attr[i].i != out_attr[i].i)
12931 {
12932 _bfd_error_handler
3895f852 12933 (_("error: fp16 format mismatch between %B and %B"),
91e22acd
AS		 12934 ibfd, obfd);
12935 result = FALSE;
12936 }
12937 }
12938 if (in_attr[i].i != 0)
12939 out_attr[i].i = in_attr[i].i;
12940 break;
7b86a9fa 12941
cd21e546 12942 case Tag_DIV_use:
ac56ee8f
MGD		 12943 /* A value of zero on input means that the divide instruction may
12944 be used if available in the base architecture as specified via
12945 Tag_CPU_arch and Tag_CPU_arch_profile. A value of 1 means that
12946 the user did not want divide instructions. A value of 2
12947 explicitly means that divide instructions were allowed in ARM
12948 and Thumb state. */
12949 if (in_attr[i].i == out_attr[i].i)
12950 /* Do nothing. */ ;
12951 else if (elf32_arm_attributes_forbid_div (in_attr)
12952 && !elf32_arm_attributes_accept_div (out_attr))
12953 out_attr[i].i = 1;
12954 else if (elf32_arm_attributes_forbid_div (out_attr)
12955 && elf32_arm_attributes_accept_div (in_attr))
12956 out_attr[i].i = in_attr[i].i;
12957 else if (in_attr[i].i == 2)
12958 out_attr[i].i = in_attr[i].i;
cd21e546
MGD		 12959 break;
12960
12961 case Tag_MPextension_use_legacy:
12962 /* We don't output objects with Tag_MPextension_use_legacy - we
12963 move the value to Tag_MPextension_use. */
12964 if (in_attr[i].i != 0 && in_attr[Tag_MPextension_use].i != 0)
12965 {
12966 if (in_attr[Tag_MPextension_use].i != in_attr[i].i)
12967 {
12968 _bfd_error_handler
12969 (_("%B has has both the current and legacy "
b38cadfb 12970 "Tag_MPextension_use attributes"),
cd21e546
MGD		 12971 ibfd);
12972 result = FALSE;
12973 }
12974 }
12975
12976 if (in_attr[i].i > out_attr[Tag_MPextension_use].i)
12977 out_attr[Tag_MPextension_use] = in_attr[i];
12978
12979 break;
12980
91e22acd 12981 case Tag_nodefaults:
2d0bb761
AS		 12982 /* This tag is set if it exists, but the value is unused (and is
12983 typically zero). We don't actually need to do anything here -
12984 the merge happens automatically when the type flags are merged
12985 below. */
91e22acd
AS		 12986 break;
12987 case Tag_also_compatible_with:
12988 /* Already done in Tag_CPU_arch. */
12989 break;
12990 case Tag_conformance:
12991 /* Keep the attribute if it matches. Throw it away otherwise.
12992 No attribute means no claim to conform. */
12993 if (!in_attr[i].s || !out_attr[i].s
12994 || strcmp (in_attr[i].s, out_attr[i].s) != 0)
12995 out_attr[i].s = NULL;
12996 break;
3cfad14c 12997
91e22acd 12998 default:
e8b36cd1
JM		 12999 result
13000 = result && _bfd_elf_merge_unknown_attribute_low (ibfd, obfd, i);
91e22acd
AS		 13001 }
13002
13003 /* If out_attr was copied from in_attr then it won't have a type yet. */
13004 if (in_attr[i].type && !out_attr[i].type)
13005 out_attr[i].type = in_attr[i].type;
ee065d83
PB		 13006 }
13007
104d59d1 13008 /* Merge Tag_compatibility attributes and any common GNU ones. */
5488d830
MGD		 13009 if (!_bfd_elf_merge_object_attributes (ibfd, obfd))
13010 return FALSE;
ee065d83 13011
104d59d1 13012 /* Check for any attributes not known on ARM. */
e8b36cd1 13013 result &= _bfd_elf_merge_unknown_attribute_list (ibfd, obfd);
91e22acd 13014
91e22acd 13015 return result;
252b5132
RH		 13016}
13017
3a4a14e9
PB		 13018
13019/* Return TRUE if the two EABI versions are incompatible. */
13020
13021static bfd_boolean
13022elf32_arm_versions_compatible (unsigned iver, unsigned over)
13023{
13024 /* v4 and v5 are the same spec before and after it was released,
13025 so allow mixing them. */
13026 if ((iver == EF_ARM_EABI_VER4 && over == EF_ARM_EABI_VER5)
13027 || (iver == EF_ARM_EABI_VER5 && over == EF_ARM_EABI_VER4))
13028 return TRUE;
13029
13030 return (iver == over);
13031}
13032
252b5132
RH		 13033/* Merge backend specific data from an object file to the output
13034 object file when linking. */
9b485d32 13035
b34976b6 13036static bfd_boolean
21d799b5 13037elf32_arm_merge_private_bfd_data (bfd * ibfd, bfd * obfd);
252b5132 13038
9b485d32
NC		 13039/* Display the flags field. */
13040
b34976b6 13041static bfd_boolean
57e8b36a 13042elf32_arm_print_private_bfd_data (bfd *abfd, void * ptr)
252b5132 13043{
fc830a83
NC		 13044 FILE * file = (FILE *) ptr;
13045 unsigned long flags;
252b5132
RH		 13046
13047 BFD_ASSERT (abfd != NULL && ptr != NULL);
13048
13049 /* Print normal ELF private data. */
13050 _bfd_elf_print_private_bfd_data (abfd, ptr);
13051
fc830a83 13052 flags = elf_elfheader (abfd)->e_flags;
9b485d32
NC		 13053 /* Ignore init flag - it may not be set, despite the flags field
13054 containing valid data. */
252b5132
RH		 13055
13056 /* xgettext:c-format */
9b485d32 13057 fprintf (file, _("private flags = %lx:"), elf_elfheader (abfd)->e_flags);
252b5132 13058
fc830a83
NC		 13059 switch (EF_ARM_EABI_VERSION (flags))
13060 {
13061 case EF_ARM_EABI_UNKNOWN:
4cc11e76 13062 /* The following flag bits are GNU extensions and not part of the
fc830a83
NC		 13063 official ARM ELF extended ABI. Hence they are only decoded if
13064 the EABI version is not set. */
fd2ec330 13065 if (flags & EF_ARM_INTERWORK)
9b485d32 13066 fprintf (file, _(" [interworking enabled]"));
9a5aca8c 13067
fd2ec330 13068 if (flags & EF_ARM_APCS_26)
6c571f00 13069 fprintf (file, " [APCS-26]");
fc830a83 13070 else
6c571f00 13071 fprintf (file, " [APCS-32]");
9a5aca8c 13072
96a846ea
RE		 13073 if (flags & EF_ARM_VFP_FLOAT)
13074 fprintf (file, _(" [VFP float format]"));
fde78edd
NC		 13075 else if (flags & EF_ARM_MAVERICK_FLOAT)
13076 fprintf (file, _(" [Maverick float format]"));
96a846ea
RE		 13077 else
13078 fprintf (file, _(" [FPA float format]"));
13079
fd2ec330 13080 if (flags & EF_ARM_APCS_FLOAT)
9b485d32 13081 fprintf (file, _(" [floats passed in float registers]"));
9a5aca8c 13082
fd2ec330 13083 if (flags & EF_ARM_PIC)
9b485d32 13084 fprintf (file, _(" [position independent]"));
fc830a83 13085
fd2ec330 13086 if (flags & EF_ARM_NEW_ABI)
9b485d32 13087 fprintf (file, _(" [new ABI]"));
9a5aca8c 13088
fd2ec330 13089 if (flags & EF_ARM_OLD_ABI)
9b485d32 13090 fprintf (file, _(" [old ABI]"));
9a5aca8c 13091
fd2ec330 13092 if (flags & EF_ARM_SOFT_FLOAT)
9b485d32 13093 fprintf (file, _(" [software FP]"));
9a5aca8c 13094
96a846ea
RE		 13095 flags &= ~(EF_ARM_INTERWORK | EF_ARM_APCS_26 | EF_ARM_APCS_FLOAT
13096 | EF_ARM_PIC | EF_ARM_NEW_ABI | EF_ARM_OLD_ABI
fde78edd
NC		 13097 | EF_ARM_SOFT_FLOAT | EF_ARM_VFP_FLOAT
13098 | EF_ARM_MAVERICK_FLOAT);
fc830a83 13099 break;
9a5aca8c 13100
fc830a83 13101 case EF_ARM_EABI_VER1:
9b485d32 13102 fprintf (file, _(" [Version1 EABI]"));
9a5aca8c 13103
fc830a83 13104 if (flags & EF_ARM_SYMSARESORTED)
9b485d32 13105 fprintf (file, _(" [sorted symbol table]"));
fc830a83 13106 else
9b485d32 13107 fprintf (file, _(" [unsorted symbol table]"));
9a5aca8c 13108
fc830a83
NC		 13109 flags &= ~ EF_ARM_SYMSARESORTED;
13110 break;
9a5aca8c 13111
fd2ec330
PB		 13112 case EF_ARM_EABI_VER2:
13113 fprintf (file, _(" [Version2 EABI]"));
13114
13115 if (flags & EF_ARM_SYMSARESORTED)
13116 fprintf (file, _(" [sorted symbol table]"));
13117 else
13118 fprintf (file, _(" [unsorted symbol table]"));
13119
13120 if (flags & EF_ARM_DYNSYMSUSESEGIDX)
13121 fprintf (file, _(" [dynamic symbols use segment index]"));
13122
13123 if (flags & EF_ARM_MAPSYMSFIRST)
13124 fprintf (file, _(" [mapping symbols precede others]"));
13125
99e4ae17 13126 flags &= ~(EF_ARM_SYMSARESORTED | EF_ARM_DYNSYMSUSESEGIDX
fd2ec330
PB		 13127 | EF_ARM_MAPSYMSFIRST);
13128 break;
13129
d507cf36
PB		 13130 case EF_ARM_EABI_VER3:
13131 fprintf (file, _(" [Version3 EABI]"));
8cb51566
PB		 13132 break;
13133
13134 case EF_ARM_EABI_VER4:
13135 fprintf (file, _(" [Version4 EABI]"));
3a4a14e9 13136 goto eabi;
d507cf36 13137
3a4a14e9
PB		 13138 case EF_ARM_EABI_VER5:
13139 fprintf (file, _(" [Version5 EABI]"));
3bfcb652
NC		 13140
13141 if (flags & EF_ARM_ABI_FLOAT_SOFT)
13142 fprintf (file, _(" [soft-float ABI]"));
13143
13144 if (flags & EF_ARM_ABI_FLOAT_HARD)
13145 fprintf (file, _(" [hard-float ABI]"));
13146
13147 flags &= ~(EF_ARM_ABI_FLOAT_SOFT | EF_ARM_ABI_FLOAT_HARD);
13148
3a4a14e9 13149 eabi:
d507cf36
PB		 13150 if (flags & EF_ARM_BE8)
13151 fprintf (file, _(" [BE8]"));
13152
13153 if (flags & EF_ARM_LE8)
13154 fprintf (file, _(" [LE8]"));
13155
13156 flags &= ~(EF_ARM_LE8 | EF_ARM_BE8);
13157 break;
13158
fc830a83 13159 default:
9b485d32 13160 fprintf (file, _(" <EABI version unrecognised>"));
fc830a83
NC		 13161 break;
13162 }
252b5132 13163
fc830a83 13164 flags &= ~ EF_ARM_EABIMASK;
252b5132 13165
fc830a83 13166 if (flags & EF_ARM_RELEXEC)
9b485d32 13167 fprintf (file, _(" [relocatable executable]"));
252b5132 13168
a5721edd 13169 flags &= ~EF_ARM_RELEXEC;
fc830a83
NC		 13170
13171 if (flags)
9b485d32 13172 fprintf (file, _("<Unrecognised flag bits set>"));
9a5aca8c 13173
252b5132
RH		 13174 fputc ('\n', file);
13175
b34976b6 13176 return TRUE;
252b5132
RH		 13177}
13178
13179static int
57e8b36a 13180elf32_arm_get_symbol_type (Elf_Internal_Sym * elf_sym, int type)
252b5132 13181{
2f0ca46a
NC		 13182 switch (ELF_ST_TYPE (elf_sym->st_info))
13183 {
13184 case STT_ARM_TFUNC:
13185 return ELF_ST_TYPE (elf_sym->st_info);
ce855c42 13186
2f0ca46a
NC		 13187 case STT_ARM_16BIT:
13188 /* If the symbol is not an object, return the STT_ARM_16BIT flag.
13189 This allows us to distinguish between data used by Thumb instructions
13190 and non-data (which is probably code) inside Thumb regions of an
13191 executable. */
1a0eb693 13192 if (type != STT_OBJECT && type != STT_TLS)
2f0ca46a
NC		 13193 return ELF_ST_TYPE (elf_sym->st_info);
13194 break;
9a5aca8c 13195
ce855c42
NC		 13196 default:
13197 break;
2f0ca46a
NC		 13198 }
13199
13200 return type;
252b5132 13201}
f21f3fe0 13202
252b5132 13203static asection *
07adf181
AM		 13204elf32_arm_gc_mark_hook (asection *sec,
13205 struct bfd_link_info *info,
13206 Elf_Internal_Rela *rel,
13207 struct elf_link_hash_entry *h,
13208 Elf_Internal_Sym *sym)
252b5132
RH		 13209{
13210 if (h != NULL)
07adf181 13211 switch (ELF32_R_TYPE (rel->r_info))
252b5132
RH		 13212 {
13213 case R_ARM_GNU_VTINHERIT:
13214 case R_ARM_GNU_VTENTRY:
07adf181
AM		 13215 return NULL;
13216 }
9ad5cbcf 13217
07adf181 13218 return _bfd_elf_gc_mark_hook (sec, info, rel, h, sym);
252b5132
RH		 13219}
13220
780a67af
NC		 13221/* Update the got entry reference counts for the section being removed. */
13222
b34976b6 13223static bfd_boolean
ba93b8ac
DJ		 13224elf32_arm_gc_sweep_hook (bfd * abfd,
13225 struct bfd_link_info * info,
13226 asection * sec,
13227 const Elf_Internal_Rela * relocs)
252b5132 13228{
5e681ec4
PB		 13229 Elf_Internal_Shdr *symtab_hdr;
13230 struct elf_link_hash_entry **sym_hashes;
13231 bfd_signed_vma *local_got_refcounts;
13232 const Elf_Internal_Rela *rel, *relend;
eb043451
PB		 13233 struct elf32_arm_link_hash_table * globals;
13234
0e1862bb 13235 if (bfd_link_relocatable (info))
7dda2462
TG		 13236 return TRUE;
13237
eb043451 13238 globals = elf32_arm_hash_table (info);
4dfe6ac6
NC		 13239 if (globals == NULL)
13240 return FALSE;
5e681ec4
PB		 13241
13242 elf_section_data (sec)->local_dynrel = NULL;
13243
0ffa91dd 13244 symtab_hdr = & elf_symtab_hdr (abfd);
5e681ec4
PB		 13245 sym_hashes = elf_sym_hashes (abfd);
13246 local_got_refcounts = elf_local_got_refcounts (abfd);
13247
906e58ca 13248 check_use_blx (globals);
bd97cb95 13249
5e681ec4
PB		 13250 relend = relocs + sec->reloc_count;
13251 for (rel = relocs; rel < relend; rel++)
eb043451 13252 {
3eb128b2
AM		 13253 unsigned long r_symndx;
13254 struct elf_link_hash_entry *h = NULL;
f6e32f6d 13255 struct elf32_arm_link_hash_entry *eh;
eb043451 13256 int r_type;
34e77a92 13257 bfd_boolean call_reloc_p;
f6e32f6d
RS		 13258 bfd_boolean may_become_dynamic_p;
13259 bfd_boolean may_need_local_target_p;
34e77a92
RS		 13260 union gotplt_union *root_plt;
13261 struct arm_plt_info *arm_plt;
5e681ec4 13262
3eb128b2
AM		 13263 r_symndx = ELF32_R_SYM (rel->r_info);
13264 if (r_symndx >= symtab_hdr->sh_info)
13265 {
13266 h = sym_hashes[r_symndx - symtab_hdr->sh_info];
13267 while (h->root.type == bfd_link_hash_indirect
13268 || h->root.type == bfd_link_hash_warning)
13269 h = (struct elf_link_hash_entry *) h->root.u.i.link;
13270 }
f6e32f6d
RS		 13271 eh = (struct elf32_arm_link_hash_entry *) h;
13272
34e77a92 13273 call_reloc_p = FALSE;
f6e32f6d
RS		 13274 may_become_dynamic_p = FALSE;
13275 may_need_local_target_p = FALSE;
3eb128b2 13276
eb043451 13277 r_type = ELF32_R_TYPE (rel->r_info);
eb043451 13278 r_type = arm_real_reloc_type (globals, r_type);
eb043451
PB		 13279 switch (r_type)
13280 {
13281 case R_ARM_GOT32:
eb043451 13282 case R_ARM_GOT_PREL:
ba93b8ac
DJ		 13283 case R_ARM_TLS_GD32:
13284 case R_ARM_TLS_IE32:
3eb128b2 13285 if (h != NULL)
eb043451 13286 {
eb043451
PB		 13287 if (h->got.refcount > 0)
13288 h->got.refcount -= 1;
13289 }
13290 else if (local_got_refcounts != NULL)
13291 {
13292 if (local_got_refcounts[r_symndx] > 0)
13293 local_got_refcounts[r_symndx] -= 1;
13294 }
13295 break;
13296
ba93b8ac 13297 case R_ARM_TLS_LDM32:
4dfe6ac6 13298 globals->tls_ldm_got.refcount -= 1;
ba93b8ac
DJ		 13299 break;
13300
eb043451
PB		 13301 case R_ARM_PC24:
13302 case R_ARM_PLT32:
5b5bb741
PB		 13303 case R_ARM_CALL:
13304 case R_ARM_JUMP24:
eb043451 13305 case R_ARM_PREL31:
c19d1205 13306 case R_ARM_THM_CALL:
bd97cb95
DJ		 13307 case R_ARM_THM_JUMP24:
13308 case R_ARM_THM_JUMP19:
34e77a92 13309 call_reloc_p = TRUE;
f6e32f6d
RS		 13310 may_need_local_target_p = TRUE;
13311 break;
13312
13313 case R_ARM_ABS12:
13314 if (!globals->vxworks_p)
13315 {
13316 may_need_local_target_p = TRUE;
13317 break;
13318 }
13319 /* Fall through. */
13320 case R_ARM_ABS32:
13321 case R_ARM_ABS32_NOI:
13322 case R_ARM_REL32:
13323 case R_ARM_REL32_NOI:
b6895b4f
PB		 13324 case R_ARM_MOVW_ABS_NC:
13325 case R_ARM_MOVT_ABS:
13326 case R_ARM_MOVW_PREL_NC:
13327 case R_ARM_MOVT_PREL:
13328 case R_ARM_THM_MOVW_ABS_NC:
13329 case R_ARM_THM_MOVT_ABS:
13330 case R_ARM_THM_MOVW_PREL_NC:
13331 case R_ARM_THM_MOVT_PREL:
b7693d02 13332 /* Should the interworking branches be here also? */
0e1862bb 13333 if ((bfd_link_pic (info) || globals->root.is_relocatable_executable)
34e77a92
RS		 13334 && (sec->flags & SEC_ALLOC) != 0)
13335 {
13336 if (h == NULL
469a3493 13337 && elf32_arm_howto_from_type (r_type)->pc_relative)
34e77a92
RS		 13338 {
13339 call_reloc_p = TRUE;
13340 may_need_local_target_p = TRUE;
13341 }
13342 else
13343 may_become_dynamic_p = TRUE;
13344 }
f6e32f6d
RS		 13345 else
13346 may_need_local_target_p = TRUE;
13347 break;
b7693d02 13348
f6e32f6d
RS		 13349 default:
13350 break;
13351 }
5e681ec4 13352
34e77a92
RS		 13353 if (may_need_local_target_p
13354 && elf32_arm_get_plt_info (abfd, eh, r_symndx, &root_plt, &arm_plt))
f6e32f6d 13355 {
27586251
HPN		 13356 /* If PLT refcount book-keeping is wrong and too low, we'll
13357 see a zero value (going to -1) for the root PLT reference
13358 count. */
13359 if (root_plt->refcount >= 0)
13360 {
13361 BFD_ASSERT (root_plt->refcount != 0);
13362 root_plt->refcount -= 1;
13363 }
13364 else
13365 /* A value of -1 means the symbol has become local, forced
13366 or seeing a hidden definition. Any other negative value
13367 is an error. */
13368 BFD_ASSERT (root_plt->refcount == -1);
34e77a92
RS		 13369
13370 if (!call_reloc_p)
13371 arm_plt->noncall_refcount--;
5e681ec4 13372
f6e32f6d 13373 if (r_type == R_ARM_THM_CALL)
34e77a92 13374 arm_plt->maybe_thumb_refcount--;
bd97cb95 13375
f6e32f6d
RS		 13376 if (r_type == R_ARM_THM_JUMP24
13377 || r_type == R_ARM_THM_JUMP19)
34e77a92 13378 arm_plt->thumb_refcount--;
f6e32f6d 13379 }
5e681ec4 13380
34e77a92 13381 if (may_become_dynamic_p)
f6e32f6d
RS		 13382 {
13383 struct elf_dyn_relocs **pp;
13384 struct elf_dyn_relocs *p;
5e681ec4 13385
34e77a92 13386 if (h != NULL)
9c489990 13387 pp = &(eh->dyn_relocs);
34e77a92
RS		 13388 else
13389 {
13390 Elf_Internal_Sym *isym;
13391
13392 isym = bfd_sym_from_r_symndx (&globals->sym_cache,
13393 abfd, r_symndx);
13394 if (isym == NULL)
13395 return FALSE;
13396 pp = elf32_arm_get_local_dynreloc_list (abfd, r_symndx, isym);
13397 if (pp == NULL)
13398 return FALSE;
13399 }
9c489990 13400 for (; (p = *pp) != NULL; pp = &p->next)
f6e32f6d
RS		 13401 if (p->sec == sec)
13402 {
13403 /* Everything must go for SEC. */
13404 *pp = p->next;
13405 break;
13406 }
eb043451
PB		 13407 }
13408 }
5e681ec4 13409
b34976b6 13410 return TRUE;
252b5132
RH		 13411}
13412
780a67af
NC		 13413/* Look through the relocs for a section during the first phase. */
13414
b34976b6 13415static bfd_boolean
57e8b36a
NC		 13416elf32_arm_check_relocs (bfd *abfd, struct bfd_link_info *info,
13417 asection *sec, const Elf_Internal_Rela *relocs)
252b5132 13418{
b34976b6
AM		 13419 Elf_Internal_Shdr *symtab_hdr;
13420 struct elf_link_hash_entry **sym_hashes;
b34976b6
AM		 13421 const Elf_Internal_Rela *rel;
13422 const Elf_Internal_Rela *rel_end;
13423 bfd *dynobj;
5e681ec4 13424 asection *sreloc;
5e681ec4 13425 struct elf32_arm_link_hash_table *htab;
f6e32f6d
RS		 13426 bfd_boolean call_reloc_p;
13427 bfd_boolean may_become_dynamic_p;
13428 bfd_boolean may_need_local_target_p;
ce98a316 13429 unsigned long nsyms;
9a5aca8c 13430
0e1862bb 13431 if (bfd_link_relocatable (info))
b34976b6 13432 return TRUE;
9a5aca8c 13433
0ffa91dd
NC		 13434 BFD_ASSERT (is_arm_elf (abfd));
13435
5e681ec4 13436 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 13437 if (htab == NULL)
13438 return FALSE;
13439
5e681ec4 13440 sreloc = NULL;
9a5aca8c 13441
67687978
PB		 13442 /* Create dynamic sections for relocatable executables so that we can
13443 copy relocations. */
13444 if (htab->root.is_relocatable_executable
13445 && ! htab->root.dynamic_sections_created)
13446 {
13447 if (! _bfd_elf_link_create_dynamic_sections (abfd, info))
13448 return FALSE;
13449 }
13450
cbc704f3
RS		 13451 if (htab->root.dynobj == NULL)
13452 htab->root.dynobj = abfd;
34e77a92
RS		 13453 if (!create_ifunc_sections (info))
13454 return FALSE;
cbc704f3
RS		 13455
13456 dynobj = htab->root.dynobj;
13457
0ffa91dd 13458 symtab_hdr = & elf_symtab_hdr (abfd);
252b5132 13459 sym_hashes = elf_sym_hashes (abfd);
ce98a316 13460 nsyms = NUM_SHDR_ENTRIES (symtab_hdr);
b38cadfb 13461
252b5132
RH		 13462 rel_end = relocs + sec->reloc_count;
13463 for (rel = relocs; rel < rel_end; rel++)
13464 {
34e77a92 13465 Elf_Internal_Sym *isym;
252b5132 13466 struct elf_link_hash_entry *h;
b7693d02 13467 struct elf32_arm_link_hash_entry *eh;
252b5132 13468 unsigned long r_symndx;
eb043451 13469 int r_type;
9a5aca8c 13470
252b5132 13471 r_symndx = ELF32_R_SYM (rel->r_info);
eb043451 13472 r_type = ELF32_R_TYPE (rel->r_info);
eb043451 13473 r_type = arm_real_reloc_type (htab, r_type);
ba93b8ac 13474
ce98a316
NC		 13475 if (r_symndx >= nsyms
13476 /* PR 9934: It is possible to have relocations that do not
13477 refer to symbols, thus it is also possible to have an
13478 object file containing relocations but no symbol table. */
cf35638d 13479 && (r_symndx > STN_UNDEF || nsyms > 0))
ba93b8ac
DJ		 13480 {
13481 (*_bfd_error_handler) (_("%B: bad symbol index: %d"), abfd,
ce98a316 13482 r_symndx);
ba93b8ac
DJ		 13483 return FALSE;
13484 }
13485
34e77a92
RS		 13486 h = NULL;
13487 isym = NULL;
13488 if (nsyms > 0)
973a3492 13489 {
34e77a92
RS		 13490 if (r_symndx < symtab_hdr->sh_info)
13491 {
13492 /* A local symbol. */
13493 isym = bfd_sym_from_r_symndx (&htab->sym_cache,
13494 abfd, r_symndx);
13495 if (isym == NULL)
13496 return FALSE;
13497 }
13498 else
13499 {
13500 h = sym_hashes[r_symndx - symtab_hdr->sh_info];
13501 while (h->root.type == bfd_link_hash_indirect
13502 || h->root.type == bfd_link_hash_warning)
13503 h = (struct elf_link_hash_entry *) h->root.u.i.link;
81fbe831
AM		 13504
13505 /* PR15323, ref flags aren't set for references in the
13506 same object. */
13507 h->root.non_ir_ref = 1;
34e77a92 13508 }
973a3492 13509 }
9a5aca8c 13510
b7693d02
DJ		 13511 eh = (struct elf32_arm_link_hash_entry *) h;
13512
f6e32f6d
RS		 13513 call_reloc_p = FALSE;
13514 may_become_dynamic_p = FALSE;
13515 may_need_local_target_p = FALSE;
13516
0855e32b
NS		 13517 /* Could be done earlier, if h were already available. */
13518 r_type = elf32_arm_tls_transition (info, r_type, h);
eb043451 13519 switch (r_type)
99059e56 13520 {
5e681ec4 13521 case R_ARM_GOT32:
eb043451 13522 case R_ARM_GOT_PREL:
ba93b8ac
DJ		 13523 case R_ARM_TLS_GD32:
13524 case R_ARM_TLS_IE32:
0855e32b
NS		 13525 case R_ARM_TLS_GOTDESC:
13526 case R_ARM_TLS_DESCSEQ:
13527 case R_ARM_THM_TLS_DESCSEQ:
13528 case R_ARM_TLS_CALL:
13529 case R_ARM_THM_TLS_CALL:
5e681ec4 13530 /* This symbol requires a global offset table entry. */
ba93b8ac
DJ		 13531 {
13532 int tls_type, old_tls_type;
5e681ec4 13533
ba93b8ac
DJ		 13534 switch (r_type)
13535 {
13536 case R_ARM_TLS_GD32: tls_type = GOT_TLS_GD; break;
b38cadfb 13537
ba93b8ac 13538 case R_ARM_TLS_IE32: tls_type = GOT_TLS_IE; break;
b38cadfb 13539
0855e32b
NS		 13540 case R_ARM_TLS_GOTDESC:
13541 case R_ARM_TLS_CALL: case R_ARM_THM_TLS_CALL:
13542 case R_ARM_TLS_DESCSEQ: case R_ARM_THM_TLS_DESCSEQ:
13543 tls_type = GOT_TLS_GDESC; break;
b38cadfb 13544
ba93b8ac
DJ		 13545 default: tls_type = GOT_NORMAL; break;
13546 }
252b5132 13547
0e1862bb 13548 if (!bfd_link_executable (info) && (tls_type & GOT_TLS_IE))
eea6dad2
KM		 13549 info->flags |= DF_STATIC_TLS;
13550
ba93b8ac
DJ		 13551 if (h != NULL)
13552 {
13553 h->got.refcount++;
13554 old_tls_type = elf32_arm_hash_entry (h)->tls_type;
13555 }
13556 else
13557 {
ba93b8ac 13558 /* This is a global offset table entry for a local symbol. */
34e77a92
RS		 13559 if (!elf32_arm_allocate_local_sym_info (abfd))
13560 return FALSE;
13561 elf_local_got_refcounts (abfd)[r_symndx] += 1;
ba93b8ac
DJ		 13562 old_tls_type = elf32_arm_local_got_tls_type (abfd) [r_symndx];
13563 }
13564
0855e32b 13565 /* If a variable is accessed with both tls methods, two
99059e56 13566 slots may be created. */
0855e32b
NS		 13567 if (GOT_TLS_GD_ANY_P (old_tls_type)
13568 && GOT_TLS_GD_ANY_P (tls_type))
13569 tls_type |= old_tls_type;
13570
13571 /* We will already have issued an error message if there
13572 is a TLS/non-TLS mismatch, based on the symbol
13573 type. So just combine any TLS types needed. */
ba93b8ac
DJ		 13574 if (old_tls_type != GOT_UNKNOWN && old_tls_type != GOT_NORMAL
13575 && tls_type != GOT_NORMAL)
13576 tls_type |= old_tls_type;
13577
0855e32b 13578 /* If the symbol is accessed in both IE and GDESC
99059e56
RM		 13579 method, we're able to relax. Turn off the GDESC flag,
13580 without messing up with any other kind of tls types
6a631e86 13581 that may be involved. */
0855e32b
NS		 13582 if ((tls_type & GOT_TLS_IE) && (tls_type & GOT_TLS_GDESC))
13583 tls_type &= ~GOT_TLS_GDESC;
13584
ba93b8ac
DJ		 13585 if (old_tls_type != tls_type)
13586 {
13587 if (h != NULL)
13588 elf32_arm_hash_entry (h)->tls_type = tls_type;
13589 else
13590 elf32_arm_local_got_tls_type (abfd) [r_symndx] = tls_type;
13591 }
13592 }
8029a119 13593 /* Fall through. */
ba93b8ac
DJ		 13594
13595 case R_ARM_TLS_LDM32:
13596 if (r_type == R_ARM_TLS_LDM32)
13597 htab->tls_ldm_got.refcount++;
8029a119 13598 /* Fall through. */
252b5132 13599
c19d1205 13600 case R_ARM_GOTOFF32:
5e681ec4 13601 case R_ARM_GOTPC:
cbc704f3
RS		 13602 if (htab->root.sgot == NULL
13603 && !create_got_section (htab->root.dynobj, info))
13604 return FALSE;
252b5132
RH		 13605 break;
13606
252b5132 13607 case R_ARM_PC24:
7359ea65 13608 case R_ARM_PLT32:
5b5bb741
PB		 13609 case R_ARM_CALL:
13610 case R_ARM_JUMP24:
eb043451 13611 case R_ARM_PREL31:
c19d1205 13612 case R_ARM_THM_CALL:
bd97cb95
DJ		 13613 case R_ARM_THM_JUMP24:
13614 case R_ARM_THM_JUMP19:
f6e32f6d
RS		 13615 call_reloc_p = TRUE;
13616 may_need_local_target_p = TRUE;
13617 break;
13618
13619 case R_ARM_ABS12:
13620 /* VxWorks uses dynamic R_ARM_ABS12 relocations for
13621 ldr __GOTT_INDEX__ offsets. */
13622 if (!htab->vxworks_p)
13623 {
13624 may_need_local_target_p = TRUE;
13625 break;
13626 }
aebf9be7
NC		 13627 else goto jump_over;
13628
f6e32f6d 13629 /* Fall through. */
39623e12 13630
96c23d59
JM		 13631 case R_ARM_MOVW_ABS_NC:
13632 case R_ARM_MOVT_ABS:
13633 case R_ARM_THM_MOVW_ABS_NC:
13634 case R_ARM_THM_MOVT_ABS:
0e1862bb 13635 if (bfd_link_pic (info))
96c23d59
JM		 13636 {
13637 (*_bfd_error_handler)
13638 (_("%B: relocation %s against `%s' can not be used when making a shared object; recompile with -fPIC"),
13639 abfd, elf32_arm_howto_table_1[r_type].name,
13640 (h) ? h->root.root.string : "a local symbol");
13641 bfd_set_error (bfd_error_bad_value);
13642 return FALSE;
13643 }
13644
13645 /* Fall through. */
39623e12
PB		 13646 case R_ARM_ABS32:
13647 case R_ARM_ABS32_NOI:
aebf9be7 13648 jump_over:
0e1862bb 13649 if (h != NULL && bfd_link_executable (info))
97323ad1
WN		 13650 {
13651 h->pointer_equality_needed = 1;
13652 }
13653 /* Fall through. */
39623e12
PB		 13654 case R_ARM_REL32:
13655 case R_ARM_REL32_NOI:
b6895b4f
PB		 13656 case R_ARM_MOVW_PREL_NC:
13657 case R_ARM_MOVT_PREL:
b6895b4f
PB		 13658 case R_ARM_THM_MOVW_PREL_NC:
13659 case R_ARM_THM_MOVT_PREL:
39623e12 13660
b7693d02 13661 /* Should the interworking branches be listed here? */
0e1862bb 13662 if ((bfd_link_pic (info) || htab->root.is_relocatable_executable)
34e77a92
RS		 13663 && (sec->flags & SEC_ALLOC) != 0)
13664 {
13665 if (h == NULL
469a3493 13666 && elf32_arm_howto_from_type (r_type)->pc_relative)
34e77a92
RS		 13667 {
13668 /* In shared libraries and relocatable executables,
13669 we treat local relative references as calls;
13670 see the related SYMBOL_CALLS_LOCAL code in
13671 allocate_dynrelocs. */
13672 call_reloc_p = TRUE;
13673 may_need_local_target_p = TRUE;
13674 }
13675 else
13676 /* We are creating a shared library or relocatable
13677 executable, and this is a reloc against a global symbol,
13678 or a non-PC-relative reloc against a local symbol.
13679 We may need to copy the reloc into the output. */
13680 may_become_dynamic_p = TRUE;
13681 }
f6e32f6d
RS		 13682 else
13683 may_need_local_target_p = TRUE;
252b5132
RH		 13684 break;
13685
99059e56
RM		 13686 /* This relocation describes the C++ object vtable hierarchy.
13687 Reconstruct it for later use during GC. */
13688 case R_ARM_GNU_VTINHERIT:
13689 if (!bfd_elf_gc_record_vtinherit (abfd, sec, h, rel->r_offset))
13690 return FALSE;
13691 break;
13692
13693 /* This relocation describes which C++ vtable entries are actually
13694 used. Record for later use during GC. */
13695 case R_ARM_GNU_VTENTRY:
13696 BFD_ASSERT (h != NULL);
13697 if (h != NULL
13698 && !bfd_elf_gc_record_vtentry (abfd, sec, h, rel->r_offset))
13699 return FALSE;
13700 break;
13701 }
f6e32f6d
RS		 13702
13703 if (h != NULL)
13704 {
13705 if (call_reloc_p)
13706 /* We may need a .plt entry if the function this reloc
13707 refers to is in a different object, regardless of the
13708 symbol's type. We can't tell for sure yet, because
13709 something later might force the symbol local. */
13710 h->needs_plt = 1;
13711 else if (may_need_local_target_p)
13712 /* If this reloc is in a read-only section, we might
13713 need a copy reloc. We can't check reliably at this
13714 stage whether the section is read-only, as input
13715 sections have not yet been mapped to output sections.
13716 Tentatively set the flag for now, and correct in
13717 adjust_dynamic_symbol. */
13718 h->non_got_ref = 1;
13719 }
13720
34e77a92
RS		 13721 if (may_need_local_target_p
13722 && (h != NULL || ELF32_ST_TYPE (isym->st_info) == STT_GNU_IFUNC))
f6e32f6d 13723 {
34e77a92
RS		 13724 union gotplt_union *root_plt;
13725 struct arm_plt_info *arm_plt;
13726 struct arm_local_iplt_info *local_iplt;
13727
13728 if (h != NULL)
13729 {
13730 root_plt = &h->plt;
13731 arm_plt = &eh->plt;
13732 }
13733 else
13734 {
13735 local_iplt = elf32_arm_create_local_iplt (abfd, r_symndx);
13736 if (local_iplt == NULL)
13737 return FALSE;
13738 root_plt = &local_iplt->root;
13739 arm_plt = &local_iplt->arm;
13740 }
13741
f6e32f6d
RS		 13742 /* If the symbol is a function that doesn't bind locally,
13743 this relocation will need a PLT entry. */
a8c887dd
NC		 13744 if (root_plt->refcount != -1)
13745 root_plt->refcount += 1;
34e77a92
RS		 13746
13747 if (!call_reloc_p)
13748 arm_plt->noncall_refcount++;
f6e32f6d
RS		 13749
13750 /* It's too early to use htab->use_blx here, so we have to
13751 record possible blx references separately from
13752 relocs that definitely need a thumb stub. */
13753
13754 if (r_type == R_ARM_THM_CALL)
34e77a92 13755 arm_plt->maybe_thumb_refcount += 1;
f6e32f6d
RS		 13756
13757 if (r_type == R_ARM_THM_JUMP24
13758 || r_type == R_ARM_THM_JUMP19)
34e77a92 13759 arm_plt->thumb_refcount += 1;
f6e32f6d
RS		 13760 }
13761
13762 if (may_become_dynamic_p)
13763 {
13764 struct elf_dyn_relocs *p, **head;
13765
13766 /* Create a reloc section in dynobj. */
13767 if (sreloc == NULL)
13768 {
13769 sreloc = _bfd_elf_make_dynamic_reloc_section
13770 (sec, dynobj, 2, abfd, ! htab->use_rel);
13771
13772 if (sreloc == NULL)
13773 return FALSE;
13774
13775 /* BPABI objects never have dynamic relocations mapped. */
13776 if (htab->symbian_p)
13777 {
13778 flagword flags;
13779
13780 flags = bfd_get_section_flags (dynobj, sreloc);
13781 flags &= ~(SEC_LOAD | SEC_ALLOC);
13782 bfd_set_section_flags (dynobj, sreloc, flags);
13783 }
13784 }
13785
13786 /* If this is a global symbol, count the number of
13787 relocations we need for this symbol. */
13788 if (h != NULL)
13789 head = &((struct elf32_arm_link_hash_entry *) h)->dyn_relocs;
13790 else
13791 {
34e77a92
RS		 13792 head = elf32_arm_get_local_dynreloc_list (abfd, r_symndx, isym);
13793 if (head == NULL)
f6e32f6d 13794 return FALSE;
f6e32f6d
RS		 13795 }
13796
13797 p = *head;
13798 if (p == NULL || p->sec != sec)
13799 {
13800 bfd_size_type amt = sizeof *p;
13801
13802 p = (struct elf_dyn_relocs *) bfd_alloc (htab->root.dynobj, amt);
13803 if (p == NULL)
13804 return FALSE;
13805 p->next = *head;
13806 *head = p;
13807 p->sec = sec;
13808 p->count = 0;
13809 p->pc_count = 0;
13810 }
13811
469a3493 13812 if (elf32_arm_howto_from_type (r_type)->pc_relative)
f6e32f6d
RS		 13813 p->pc_count += 1;
13814 p->count += 1;
13815 }
252b5132 13816 }
f21f3fe0 13817
b34976b6 13818 return TRUE;
252b5132
RH		 13819}
13820
6a5bb875
PB		 13821/* Unwinding tables are not referenced directly. This pass marks them as
13822 required if the corresponding code section is marked. */
13823
13824static bfd_boolean
906e58ca
NC		 13825elf32_arm_gc_mark_extra_sections (struct bfd_link_info *info,
13826 elf_gc_mark_hook_fn gc_mark_hook)
6a5bb875
PB		 13827{
13828 bfd *sub;
13829 Elf_Internal_Shdr **elf_shdrp;
13830 bfd_boolean again;
13831
7f6ab9f8
AM		 13832 _bfd_elf_gc_mark_extra_sections (info, gc_mark_hook);
13833
6a5bb875
PB		 13834 /* Marking EH data may cause additional code sections to be marked,
13835 requiring multiple passes. */
13836 again = TRUE;
13837 while (again)
13838 {
13839 again = FALSE;
c72f2fb2 13840 for (sub = info->input_bfds; sub != NULL; sub = sub->link.next)
6a5bb875
PB		 13841 {
13842 asection *o;
13843
0ffa91dd 13844 if (! is_arm_elf (sub))
6a5bb875
PB		 13845 continue;
13846
13847 elf_shdrp = elf_elfsections (sub);
13848 for (o = sub->sections; o != NULL; o = o->next)
13849 {
13850 Elf_Internal_Shdr *hdr;
0ffa91dd 13851
6a5bb875 13852 hdr = &elf_section_data (o)->this_hdr;
4fbb74a6
AM		 13853 if (hdr->sh_type == SHT_ARM_EXIDX
13854 && hdr->sh_link
13855 && hdr->sh_link < elf_numsections (sub)
6a5bb875
PB		 13856 && !o->gc_mark
13857 && elf_shdrp[hdr->sh_link]->bfd_section->gc_mark)
13858 {
13859 again = TRUE;
13860 if (!_bfd_elf_gc_mark (info, o, gc_mark_hook))
13861 return FALSE;
13862 }
13863 }
13864 }
13865 }
13866
13867 return TRUE;
13868}
13869
3c9458e9
NC		 13870/* Treat mapping symbols as special target symbols. */
13871
13872static bfd_boolean
13873elf32_arm_is_target_special_symbol (bfd * abfd ATTRIBUTE_UNUSED, asymbol * sym)
13874{
b0796911
PB		 13875 return bfd_is_arm_special_symbol_name (sym->name,
13876 BFD_ARM_SPECIAL_SYM_TYPE_ANY);
3c9458e9
NC		 13877}
13878
0367ecfb
NC		 13879/* This is a copy of elf_find_function() from elf.c except that
13880 ARM mapping symbols are ignored when looking for function names
13881 and STT_ARM_TFUNC is considered to a function type. */
252b5132 13882
0367ecfb
NC		 13883static bfd_boolean
13884arm_elf_find_function (bfd * abfd ATTRIBUTE_UNUSED,
0367ecfb 13885 asymbol ** symbols,
fb167eb2 13886 asection * section,
0367ecfb
NC		 13887 bfd_vma offset,
13888 const char ** filename_ptr,
13889 const char ** functionname_ptr)
13890{
13891 const char * filename = NULL;
13892 asymbol * func = NULL;
13893 bfd_vma low_func = 0;
13894 asymbol ** p;
252b5132
RH		 13895
13896 for (p = symbols; *p != NULL; p++)
13897 {
13898 elf_symbol_type *q;
13899
13900 q = (elf_symbol_type *) *p;
13901
252b5132
RH		 13902 switch (ELF_ST_TYPE (q->internal_elf_sym.st_info))
13903 {
13904 default:
13905 break;
13906 case STT_FILE:
13907 filename = bfd_asymbol_name (&q->symbol);
13908 break;
252b5132
RH		 13909 case STT_FUNC:
13910 case STT_ARM_TFUNC:
9d2da7ca 13911 case STT_NOTYPE:
b0796911 13912 /* Skip mapping symbols. */
0367ecfb 13913 if ((q->symbol.flags & BSF_LOCAL)
b0796911
PB		 13914 && bfd_is_arm_special_symbol_name (q->symbol.name,
13915 BFD_ARM_SPECIAL_SYM_TYPE_ANY))
0367ecfb
NC		 13916 continue;
13917 /* Fall through. */
6b40fcba 13918 if (bfd_get_section (&q->symbol) == section
252b5132
RH		 13919 && q->symbol.value >= low_func
13920 && q->symbol.value <= offset)
13921 {
13922 func = (asymbol *) q;
13923 low_func = q->symbol.value;
13924 }
13925 break;
13926 }
13927 }
13928
13929 if (func == NULL)
b34976b6 13930 return FALSE;
252b5132 13931
0367ecfb
NC		 13932 if (filename_ptr)
13933 *filename_ptr = filename;
13934 if (functionname_ptr)
13935 *functionname_ptr = bfd_asymbol_name (func);
13936
13937 return TRUE;
906e58ca 13938}
0367ecfb
NC		 13939
13940
13941/* Find the nearest line to a particular section and offset, for error
13942 reporting. This code is a duplicate of the code in elf.c, except
13943 that it uses arm_elf_find_function. */
13944
13945static bfd_boolean
13946elf32_arm_find_nearest_line (bfd * abfd,
0367ecfb 13947 asymbol ** symbols,
fb167eb2 13948 asection * section,
0367ecfb
NC		 13949 bfd_vma offset,
13950 const char ** filename_ptr,
13951 const char ** functionname_ptr,
fb167eb2
AM		 13952 unsigned int * line_ptr,
13953 unsigned int * discriminator_ptr)
0367ecfb
NC		 13954{
13955 bfd_boolean found = FALSE;
13956
fb167eb2 13957 if (_bfd_dwarf2_find_nearest_line (abfd, symbols, NULL, section, offset,
0367ecfb 13958 filename_ptr, functionname_ptr,
fb167eb2
AM		 13959 line_ptr, discriminator_ptr,
13960 dwarf_debug_sections, 0,
0367ecfb
NC		 13961 & elf_tdata (abfd)->dwarf2_find_line_info))
13962 {
13963 if (!*functionname_ptr)
fb167eb2 13964 arm_elf_find_function (abfd, symbols, section, offset,
0367ecfb
NC		 13965 *filename_ptr ? NULL : filename_ptr,
13966 functionname_ptr);
f21f3fe0 13967
0367ecfb
NC		 13968 return TRUE;
13969 }
13970
fb167eb2
AM		 13971 /* Skip _bfd_dwarf1_find_nearest_line since no known ARM toolchain
13972 uses DWARF1. */
13973
0367ecfb
NC		 13974 if (! _bfd_stab_section_find_nearest_line (abfd, symbols, section, offset,
13975 & found, filename_ptr,
13976 functionname_ptr, line_ptr,
13977 & elf_tdata (abfd)->line_info))
13978 return FALSE;
13979
13980 if (found && (*functionname_ptr || *line_ptr))
13981 return TRUE;
13982
13983 if (symbols == NULL)
13984 return FALSE;
13985
fb167eb2 13986 if (! arm_elf_find_function (abfd, symbols, section, offset,
0367ecfb
NC		 13987 filename_ptr, functionname_ptr))
13988 return FALSE;
13989
13990 *line_ptr = 0;
b34976b6 13991 return TRUE;
252b5132
RH		 13992}
13993
4ab527b0
FF		 13994static bfd_boolean
13995elf32_arm_find_inliner_info (bfd * abfd,
13996 const char ** filename_ptr,
13997 const char ** functionname_ptr,
13998 unsigned int * line_ptr)
13999{
14000 bfd_boolean found;
14001 found = _bfd_dwarf2_find_inliner_info (abfd, filename_ptr,
14002 functionname_ptr, line_ptr,
14003 & elf_tdata (abfd)->dwarf2_find_line_info);
14004 return found;
14005}
14006
252b5132
RH		 14007/* Adjust a symbol defined by a dynamic object and referenced by a
14008 regular object. The current definition is in some section of the
14009 dynamic object, but we're not including those sections. We have to
14010 change the definition to something the rest of the link can
14011 understand. */
14012
b34976b6 14013static bfd_boolean
57e8b36a
NC		 14014elf32_arm_adjust_dynamic_symbol (struct bfd_link_info * info,
14015 struct elf_link_hash_entry * h)
252b5132
RH		 14016{
14017 bfd * dynobj;
14018 asection * s;
b7693d02 14019 struct elf32_arm_link_hash_entry * eh;
67687978 14020 struct elf32_arm_link_hash_table *globals;
252b5132 14021
67687978 14022 globals = elf32_arm_hash_table (info);
4dfe6ac6
NC		 14023 if (globals == NULL)
14024 return FALSE;
14025
252b5132
RH		 14026 dynobj = elf_hash_table (info)->dynobj;
14027
14028 /* Make sure we know what is going on here. */
14029 BFD_ASSERT (dynobj != NULL
f5385ebf 14030 && (h->needs_plt
34e77a92 14031 || h->type == STT_GNU_IFUNC
f6e332e6 14032 || h->u.weakdef != NULL
f5385ebf
AM		 14033 || (h->def_dynamic
14034 && h->ref_regular
14035 && !h->def_regular)));
252b5132 14036
b7693d02
DJ		 14037 eh = (struct elf32_arm_link_hash_entry *) h;
14038
252b5132
RH		 14039 /* If this is a function, put it in the procedure linkage table. We
14040 will fill in the contents of the procedure linkage table later,
14041 when we know the address of the .got section. */
34e77a92 14042 if (h->type == STT_FUNC || h->type == STT_GNU_IFUNC || h->needs_plt)
252b5132 14043 {
34e77a92
RS		 14044 /* Calls to STT_GNU_IFUNC symbols always use a PLT, even if the
14045 symbol binds locally. */
5e681ec4 14046 if (h->plt.refcount <= 0
34e77a92
RS		 14047 || (h->type != STT_GNU_IFUNC
14048 && (SYMBOL_CALLS_LOCAL (info, h)
14049 || (ELF_ST_VISIBILITY (h->other) != STV_DEFAULT
14050 && h->root.type == bfd_link_hash_undefweak))))
252b5132
RH		 14051 {
14052 /* This case can occur if we saw a PLT32 reloc in an input
5e681ec4
PB		 14053 file, but the symbol was never referred to by a dynamic
14054 object, or if all references were garbage collected. In
14055 such a case, we don't actually need to build a procedure
14056 linkage table, and we can just do a PC24 reloc instead. */
14057 h->plt.offset = (bfd_vma) -1;
34e77a92
RS		 14058 eh->plt.thumb_refcount = 0;
14059 eh->plt.maybe_thumb_refcount = 0;
14060 eh->plt.noncall_refcount = 0;
f5385ebf 14061 h->needs_plt = 0;
252b5132
RH		 14062 }
14063
b34976b6 14064 return TRUE;
252b5132 14065 }
5e681ec4 14066 else
b7693d02
DJ		 14067 {
14068 /* It's possible that we incorrectly decided a .plt reloc was
14069 needed for an R_ARM_PC24 or similar reloc to a non-function sym
14070 in check_relocs. We can't decide accurately between function
14071 and non-function syms in check-relocs; Objects loaded later in
14072 the link may change h->type. So fix it now. */
14073 h->plt.offset = (bfd_vma) -1;
34e77a92
RS		 14074 eh->plt.thumb_refcount = 0;
14075 eh->plt.maybe_thumb_refcount = 0;
14076 eh->plt.noncall_refcount = 0;
b7693d02 14077 }
252b5132
RH		 14078
14079 /* If this is a weak symbol, and there is a real definition, the
14080 processor independent code will have arranged for us to see the
14081 real definition first, and we can just use the same value. */
f6e332e6 14082 if (h->u.weakdef != NULL)
252b5132 14083 {
f6e332e6
AM		 14084 BFD_ASSERT (h->u.weakdef->root.type == bfd_link_hash_defined
14085 || h->u.weakdef->root.type == bfd_link_hash_defweak);
14086 h->root.u.def.section = h->u.weakdef->root.u.def.section;
14087 h->root.u.def.value = h->u.weakdef->root.u.def.value;
b34976b6 14088 return TRUE;
252b5132
RH		 14089 }
14090
ba93b8ac
DJ		 14091 /* If there are no non-GOT references, we do not need a copy
14092 relocation. */
14093 if (!h->non_got_ref)
14094 return TRUE;
14095
252b5132
RH		 14096 /* This is a reference to a symbol defined by a dynamic object which
14097 is not a function. */
14098
14099 /* If we are creating a shared library, we must presume that the
14100 only references to the symbol are via the global offset table.
14101 For such cases we need not do anything here; the relocations will
67687978
PB		 14102 be handled correctly by relocate_section. Relocatable executables
14103 can reference data in shared objects directly, so we don't need to
14104 do anything here. */
0e1862bb 14105 if (bfd_link_pic (info) || globals->root.is_relocatable_executable)
b34976b6 14106 return TRUE;
252b5132
RH		 14107
14108 /* We must allocate the symbol in our .dynbss section, which will
14109 become part of the .bss section of the executable. There will be
14110 an entry for this symbol in the .dynsym section. The dynamic
14111 object will contain position independent code, so all references
14112 from the dynamic object to this symbol will go through the global
14113 offset table. The dynamic linker will use the .dynsym entry to
14114 determine the address it must put in the global offset table, so
14115 both the dynamic object and the regular object will refer to the
14116 same memory location for the variable. */
3d4d4302 14117 s = bfd_get_linker_section (dynobj, ".dynbss");
252b5132
RH		 14118 BFD_ASSERT (s != NULL);
14119
5522f910
NC		 14120 /* If allowed, we must generate a R_ARM_COPY reloc to tell the dynamic
14121 linker to copy the initial value out of the dynamic object and into
14122 the runtime process image. We need to remember the offset into the
00a97672 14123 .rel(a).bss section we are going to use. */
5522f910
NC		 14124 if (info->nocopyreloc == 0
14125 && (h->root.u.def.section->flags & SEC_ALLOC) != 0
5522f910 14126 && h->size != 0)
252b5132
RH		 14127 {
14128 asection *srel;
14129
3d4d4302 14130 srel = bfd_get_linker_section (dynobj, RELOC_SECTION (globals, ".bss"));
47beaa6a 14131 elf32_arm_allocate_dynrelocs (info, srel, 1);
f5385ebf 14132 h->needs_copy = 1;
252b5132
RH		 14133 }
14134
6cabe1ea 14135 return _bfd_elf_adjust_dynamic_copy (info, h, s);
252b5132
RH		 14136}
14137
5e681ec4
PB		 14138/* Allocate space in .plt, .got and associated reloc sections for
14139 dynamic relocs. */
14140
14141static bfd_boolean
47beaa6a 14142allocate_dynrelocs_for_symbol (struct elf_link_hash_entry *h, void * inf)
5e681ec4
PB		 14143{
14144 struct bfd_link_info *info;
14145 struct elf32_arm_link_hash_table *htab;
14146 struct elf32_arm_link_hash_entry *eh;
0bdcacaf 14147 struct elf_dyn_relocs *p;
5e681ec4
PB		 14148
14149 if (h->root.type == bfd_link_hash_indirect)
14150 return TRUE;
14151
e6a6bb22
AM		 14152 eh = (struct elf32_arm_link_hash_entry *) h;
14153
5e681ec4
PB		 14154 info = (struct bfd_link_info *) inf;
14155 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 14156 if (htab == NULL)
14157 return FALSE;
5e681ec4 14158
34e77a92 14159 if ((htab->root.dynamic_sections_created || h->type == STT_GNU_IFUNC)
5e681ec4
PB		 14160 && h->plt.refcount > 0)
14161 {
14162 /* Make sure this symbol is output as a dynamic symbol.
14163 Undefined weak syms won't yet be marked as dynamic. */
14164 if (h->dynindx == -1
f5385ebf 14165 && !h->forced_local)
5e681ec4 14166 {
c152c796 14167 if (! bfd_elf_link_record_dynamic_symbol (info, h))
5e681ec4
PB		 14168 return FALSE;
14169 }
14170
34e77a92
RS		 14171 /* If the call in the PLT entry binds locally, the associated
14172 GOT entry should use an R_ARM_IRELATIVE relocation instead of
14173 the usual R_ARM_JUMP_SLOT. Put it in the .iplt section rather
14174 than the .plt section. */
14175 if (h->type == STT_GNU_IFUNC && SYMBOL_CALLS_LOCAL (info, h))
14176 {
14177 eh->is_iplt = 1;
14178 if (eh->plt.noncall_refcount == 0
14179 && SYMBOL_REFERENCES_LOCAL (info, h))
14180 /* All non-call references can be resolved directly.
14181 This means that they can (and in some cases, must)
14182 resolve directly to the run-time target, rather than
14183 to the PLT. That in turns means that any .got entry
14184 would be equal to the .igot.plt entry, so there's
14185 no point having both. */
14186 h->got.refcount = 0;
14187 }
14188
0e1862bb 14189 if (bfd_link_pic (info)
34e77a92 14190 || eh->is_iplt
7359ea65 14191 || WILL_CALL_FINISH_DYNAMIC_SYMBOL (1, 0, h))
5e681ec4 14192 {
34e77a92 14193 elf32_arm_allocate_plt_entry (info, eh->is_iplt, &h->plt, &eh->plt);
b7693d02 14194
5e681ec4
PB		 14195 /* If this symbol is not defined in a regular file, and we are
14196 not generating a shared library, then set the symbol to this
14197 location in the .plt. This is required to make function
14198 pointers compare as equal between the normal executable and
14199 the shared library. */
0e1862bb 14200 if (! bfd_link_pic (info)
f5385ebf 14201 && !h->def_regular)
5e681ec4 14202 {
34e77a92 14203 h->root.u.def.section = htab->root.splt;
5e681ec4 14204 h->root.u.def.value = h->plt.offset;
5e681ec4 14205
67d74e43
DJ		 14206 /* Make sure the function is not marked as Thumb, in case
14207 it is the target of an ABS32 relocation, which will
14208 point to the PLT entry. */
35fc36a8 14209 h->target_internal = ST_BRANCH_TO_ARM;
67d74e43 14210 }
022f8312 14211
00a97672
RS		 14212 /* VxWorks executables have a second set of relocations for
14213 each PLT entry. They go in a separate relocation section,
14214 which is processed by the kernel loader. */
0e1862bb 14215 if (htab->vxworks_p && !bfd_link_pic (info))
00a97672
RS		 14216 {
14217 /* There is a relocation for the initial PLT entry:
14218 an R_ARM_32 relocation for _GLOBAL_OFFSET_TABLE_. */
14219 if (h->plt.offset == htab->plt_header_size)
47beaa6a 14220 elf32_arm_allocate_dynrelocs (info, htab->srelplt2, 1);
00a97672
RS		 14221
14222 /* There are two extra relocations for each subsequent
14223 PLT entry: an R_ARM_32 relocation for the GOT entry,
14224 and an R_ARM_32 relocation for the PLT entry. */
47beaa6a 14225 elf32_arm_allocate_dynrelocs (info, htab->srelplt2, 2);
00a97672 14226 }
5e681ec4
PB		 14227 }
14228 else
14229 {
14230 h->plt.offset = (bfd_vma) -1;
f5385ebf 14231 h->needs_plt = 0;
5e681ec4
PB		 14232 }
14233 }
14234 else
14235 {
14236 h->plt.offset = (bfd_vma) -1;
f5385ebf 14237 h->needs_plt = 0;
5e681ec4
PB		 14238 }
14239
0855e32b
NS		 14240 eh = (struct elf32_arm_link_hash_entry *) h;
14241 eh->tlsdesc_got = (bfd_vma) -1;
14242
5e681ec4
PB		 14243 if (h->got.refcount > 0)
14244 {
14245 asection *s;
14246 bfd_boolean dyn;
ba93b8ac
DJ		 14247 int tls_type = elf32_arm_hash_entry (h)->tls_type;
14248 int indx;
5e681ec4
PB		 14249
14250 /* Make sure this symbol is output as a dynamic symbol.
14251 Undefined weak syms won't yet be marked as dynamic. */
14252 if (h->dynindx == -1
f5385ebf 14253 && !h->forced_local)
5e681ec4 14254 {
c152c796 14255 if (! bfd_elf_link_record_dynamic_symbol (info, h))
5e681ec4
PB		 14256 return FALSE;
14257 }
14258
e5a52504
MM		 14259 if (!htab->symbian_p)
14260 {
362d30a1 14261 s = htab->root.sgot;
e5a52504 14262 h->got.offset = s->size;
ba93b8ac
DJ		 14263
14264 if (tls_type == GOT_UNKNOWN)
14265 abort ();
14266
14267 if (tls_type == GOT_NORMAL)
14268 /* Non-TLS symbols need one GOT slot. */
14269 s->size += 4;
14270 else
14271 {
99059e56
RM		 14272 if (tls_type & GOT_TLS_GDESC)
14273 {
0855e32b 14274 /* R_ARM_TLS_DESC needs 2 GOT slots. */
99059e56 14275 eh->tlsdesc_got
0855e32b
NS		 14276 = (htab->root.sgotplt->size
14277 - elf32_arm_compute_jump_table_size (htab));
99059e56
RM		 14278 htab->root.sgotplt->size += 8;
14279 h->got.offset = (bfd_vma) -2;
34e77a92 14280 /* plt.got_offset needs to know there's a TLS_DESC
0855e32b 14281 reloc in the middle of .got.plt. */
99059e56
RM		 14282 htab->num_tls_desc++;
14283 }
0855e32b 14284
ba93b8ac 14285 if (tls_type & GOT_TLS_GD)
0855e32b
NS		 14286 {
14287 /* R_ARM_TLS_GD32 needs 2 consecutive GOT slots. If
14288 the symbol is both GD and GDESC, got.offset may
14289 have been overwritten. */
14290 h->got.offset = s->size;
14291 s->size += 8;
14292 }
14293
ba93b8ac
DJ		 14294 if (tls_type & GOT_TLS_IE)
14295 /* R_ARM_TLS_IE32 needs one GOT slot. */
14296 s->size += 4;
14297 }
14298
e5a52504 14299 dyn = htab->root.dynamic_sections_created;
ba93b8ac
DJ		 14300
14301 indx = 0;
0e1862bb
L		 14302 if (WILL_CALL_FINISH_DYNAMIC_SYMBOL (dyn,
14303 bfd_link_pic (info),
14304 h)
14305 && (!bfd_link_pic (info)
ba93b8ac
DJ		 14306 || !SYMBOL_REFERENCES_LOCAL (info, h)))
14307 indx = h->dynindx;
14308
14309 if (tls_type != GOT_NORMAL
0e1862bb 14310 && (bfd_link_pic (info) || indx != 0)
ba93b8ac
DJ		 14311 && (ELF_ST_VISIBILITY (h->other) == STV_DEFAULT
14312 || h->root.type != bfd_link_hash_undefweak))
14313 {
14314 if (tls_type & GOT_TLS_IE)
47beaa6a 14315 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
ba93b8ac
DJ		 14316
14317 if (tls_type & GOT_TLS_GD)
47beaa6a 14318 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
ba93b8ac 14319
b38cadfb 14320 if (tls_type & GOT_TLS_GDESC)
0855e32b 14321 {
47beaa6a 14322 elf32_arm_allocate_dynrelocs (info, htab->root.srelplt, 1);
0855e32b
NS		 14323 /* GDESC needs a trampoline to jump to. */
14324 htab->tls_trampoline = -1;
14325 }
14326
14327 /* Only GD needs it. GDESC just emits one relocation per
14328 2 entries. */
b38cadfb 14329 if ((tls_type & GOT_TLS_GD) && indx != 0)
47beaa6a 14330 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
ba93b8ac 14331 }
6f820c85 14332 else if (indx != -1 && !SYMBOL_REFERENCES_LOCAL (info, h))
b436d854
RS		 14333 {
14334 if (htab->root.dynamic_sections_created)
14335 /* Reserve room for the GOT entry's R_ARM_GLOB_DAT relocation. */
14336 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
14337 }
34e77a92
RS		 14338 else if (h->type == STT_GNU_IFUNC
14339 && eh->plt.noncall_refcount == 0)
14340 /* No non-call references resolve the STT_GNU_IFUNC's PLT entry;
14341 they all resolve dynamically instead. Reserve room for the
14342 GOT entry's R_ARM_IRELATIVE relocation. */
14343 elf32_arm_allocate_irelocs (info, htab->root.srelgot, 1);
0e1862bb
L		 14344 else if (bfd_link_pic (info)
14345 && (ELF_ST_VISIBILITY (h->other) == STV_DEFAULT
14346 || h->root.type != bfd_link_hash_undefweak))
b436d854 14347 /* Reserve room for the GOT entry's R_ARM_RELATIVE relocation. */
47beaa6a 14348 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
e5a52504 14349 }
5e681ec4
PB		 14350 }
14351 else
14352 h->got.offset = (bfd_vma) -1;
14353
a4fd1a8e
PB		 14354 /* Allocate stubs for exported Thumb functions on v4t. */
14355 if (!htab->use_blx && h->dynindx != -1
0eaedd0e 14356 && h->def_regular
35fc36a8 14357 && h->target_internal == ST_BRANCH_TO_THUMB
a4fd1a8e
PB		 14358 && ELF_ST_VISIBILITY (h->other) == STV_DEFAULT)
14359 {
14360 struct elf_link_hash_entry * th;
14361 struct bfd_link_hash_entry * bh;
14362 struct elf_link_hash_entry * myh;
14363 char name[1024];
14364 asection *s;
14365 bh = NULL;
14366 /* Create a new symbol to regist the real location of the function. */
14367 s = h->root.u.def.section;
906e58ca 14368 sprintf (name, "__real_%s", h->root.root.string);
a4fd1a8e
PB		 14369 _bfd_generic_link_add_one_symbol (info, s->owner,
14370 name, BSF_GLOBAL, s,
14371 h->root.u.def.value,
14372 NULL, TRUE, FALSE, &bh);
14373
14374 myh = (struct elf_link_hash_entry *) bh;
35fc36a8 14375 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
a4fd1a8e 14376 myh->forced_local = 1;
35fc36a8 14377 myh->target_internal = ST_BRANCH_TO_THUMB;
a4fd1a8e
PB		 14378 eh->export_glue = myh;
14379 th = record_arm_to_thumb_glue (info, h);
14380 /* Point the symbol at the stub. */
14381 h->type = ELF_ST_INFO (ELF_ST_BIND (h->type), STT_FUNC);
35fc36a8 14382 h->target_internal = ST_BRANCH_TO_ARM;
a4fd1a8e
PB		 14383 h->root.u.def.section = th->root.u.def.section;
14384 h->root.u.def.value = th->root.u.def.value & ~1;
14385 }
14386
0bdcacaf 14387 if (eh->dyn_relocs == NULL)
5e681ec4
PB		 14388 return TRUE;
14389
14390 /* In the shared -Bsymbolic case, discard space allocated for
14391 dynamic pc-relative relocs against symbols which turn out to be
14392 defined in regular objects. For the normal shared case, discard
14393 space for pc-relative relocs that have become local due to symbol
14394 visibility changes. */
14395
0e1862bb 14396 if (bfd_link_pic (info) || htab->root.is_relocatable_executable)
5e681ec4 14397 {
469a3493
RM		 14398 /* Relocs that use pc_count are PC-relative forms, which will appear
14399 on something like ".long foo - ." or "movw REG, foo - .". We want
14400 calls to protected symbols to resolve directly to the function
14401 rather than going via the plt. If people want function pointer
14402 comparisons to work as expected then they should avoid writing
14403 assembly like ".long foo - .". */
ba93b8ac
DJ		 14404 if (SYMBOL_CALLS_LOCAL (info, h))
14405 {
0bdcacaf 14406 struct elf_dyn_relocs **pp;
ba93b8ac 14407
0bdcacaf 14408 for (pp = &eh->dyn_relocs; (p = *pp) != NULL; )
ba93b8ac
DJ		 14409 {
14410 p->count -= p->pc_count;
14411 p->pc_count = 0;
14412 if (p->count == 0)
14413 *pp = p->next;
14414 else
14415 pp = &p->next;
14416 }
14417 }
14418
4dfe6ac6 14419 if (htab->vxworks_p)
3348747a 14420 {
0bdcacaf 14421 struct elf_dyn_relocs **pp;
3348747a 14422
0bdcacaf 14423 for (pp = &eh->dyn_relocs; (p = *pp) != NULL; )
3348747a 14424 {
0bdcacaf 14425 if (strcmp (p->sec->output_section->name, ".tls_vars") == 0)
3348747a
NS		 14426 *pp = p->next;
14427 else
14428 pp = &p->next;
14429 }
14430 }
14431
ba93b8ac 14432 /* Also discard relocs on undefined weak syms with non-default
99059e56 14433 visibility. */
0bdcacaf 14434 if (eh->dyn_relocs != NULL
5e681ec4 14435 && h->root.type == bfd_link_hash_undefweak)
22d606e9
AM		 14436 {
14437 if (ELF_ST_VISIBILITY (h->other) != STV_DEFAULT)
0bdcacaf 14438 eh->dyn_relocs = NULL;
22d606e9
AM		 14439
14440 /* Make sure undefined weak symbols are output as a dynamic
14441 symbol in PIEs. */
14442 else if (h->dynindx == -1
14443 && !h->forced_local)
14444 {
14445 if (! bfd_elf_link_record_dynamic_symbol (info, h))
14446 return FALSE;
14447 }
14448 }
14449
67687978
PB		 14450 else if (htab->root.is_relocatable_executable && h->dynindx == -1
14451 && h->root.type == bfd_link_hash_new)
14452 {
14453 /* Output absolute symbols so that we can create relocations
14454 against them. For normal symbols we output a relocation
14455 against the section that contains them. */
14456 if (! bfd_elf_link_record_dynamic_symbol (info, h))
14457 return FALSE;
14458 }
14459
5e681ec4
PB		 14460 }
14461 else
14462 {
14463 /* For the non-shared case, discard space for relocs against
14464 symbols which turn out to need copy relocs or are not
14465 dynamic. */
14466
f5385ebf
AM		 14467 if (!h->non_got_ref
14468 && ((h->def_dynamic
14469 && !h->def_regular)
5e681ec4
PB		 14470 || (htab->root.dynamic_sections_created
14471 && (h->root.type == bfd_link_hash_undefweak
14472 || h->root.type == bfd_link_hash_undefined))))
14473 {
14474 /* Make sure this symbol is output as a dynamic symbol.
14475 Undefined weak syms won't yet be marked as dynamic. */
14476 if (h->dynindx == -1
f5385ebf 14477 && !h->forced_local)
5e681ec4 14478 {
c152c796 14479 if (! bfd_elf_link_record_dynamic_symbol (info, h))
5e681ec4
PB		 14480 return FALSE;
14481 }
14482
14483 /* If that succeeded, we know we'll be keeping all the
14484 relocs. */
14485 if (h->dynindx != -1)
14486 goto keep;
14487 }
14488
0bdcacaf 14489 eh->dyn_relocs = NULL;
5e681ec4
PB		 14490
14491 keep: ;
14492 }
14493
14494 /* Finally, allocate space. */
0bdcacaf 14495 for (p = eh->dyn_relocs; p != NULL; p = p->next)
5e681ec4 14496 {
0bdcacaf 14497 asection *sreloc = elf_section_data (p->sec)->sreloc;
34e77a92
RS		 14498 if (h->type == STT_GNU_IFUNC
14499 && eh->plt.noncall_refcount == 0
14500 && SYMBOL_REFERENCES_LOCAL (info, h))
14501 elf32_arm_allocate_irelocs (info, sreloc, p->count);
14502 else
14503 elf32_arm_allocate_dynrelocs (info, sreloc, p->count);
5e681ec4
PB		 14504 }
14505
14506 return TRUE;
14507}
14508
08d1f311
DJ		 14509/* Find any dynamic relocs that apply to read-only sections. */
14510
14511static bfd_boolean
8029a119 14512elf32_arm_readonly_dynrelocs (struct elf_link_hash_entry * h, void * inf)
08d1f311 14513{
8029a119 14514 struct elf32_arm_link_hash_entry * eh;
0bdcacaf 14515 struct elf_dyn_relocs * p;
08d1f311 14516
08d1f311 14517 eh = (struct elf32_arm_link_hash_entry *) h;
0bdcacaf 14518 for (p = eh->dyn_relocs; p != NULL; p = p->next)
08d1f311 14519 {
0bdcacaf 14520 asection *s = p->sec;
08d1f311
DJ		 14521
14522 if (s != NULL && (s->flags & SEC_READONLY) != 0)
14523 {
14524 struct bfd_link_info *info = (struct bfd_link_info *) inf;
14525
14526 info->flags |= DF_TEXTREL;
14527
14528 /* Not an error, just cut short the traversal. */
14529 return FALSE;
14530 }
14531 }
14532 return TRUE;
14533}
14534
d504ffc8
DJ		 14535void
14536bfd_elf32_arm_set_byteswap_code (struct bfd_link_info *info,
14537 int byteswap_code)
14538{
14539 struct elf32_arm_link_hash_table *globals;
14540
14541 globals = elf32_arm_hash_table (info);
4dfe6ac6
NC		 14542 if (globals == NULL)
14543 return;
14544
d504ffc8
DJ		 14545 globals->byteswap_code = byteswap_code;
14546}
14547
252b5132
RH		 14548/* Set the sizes of the dynamic sections. */
14549
b34976b6 14550static bfd_boolean
57e8b36a
NC		 14551elf32_arm_size_dynamic_sections (bfd * output_bfd ATTRIBUTE_UNUSED,
14552 struct bfd_link_info * info)
252b5132
RH		 14553{
14554 bfd * dynobj;
14555 asection * s;
b34976b6
AM		 14556 bfd_boolean plt;
14557 bfd_boolean relocs;
5e681ec4
PB		 14558 bfd *ibfd;
14559 struct elf32_arm_link_hash_table *htab;
252b5132 14560
5e681ec4 14561 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 14562 if (htab == NULL)
14563 return FALSE;
14564
252b5132
RH		 14565 dynobj = elf_hash_table (info)->dynobj;
14566 BFD_ASSERT (dynobj != NULL);
39b41c9c 14567 check_use_blx (htab);
252b5132
RH		 14568
14569 if (elf_hash_table (info)->dynamic_sections_created)
14570 {
14571 /* Set the contents of the .interp section to the interpreter. */
9b8b325a 14572 if (bfd_link_executable (info) && !info->nointerp)
252b5132 14573 {
3d4d4302 14574 s = bfd_get_linker_section (dynobj, ".interp");
252b5132 14575 BFD_ASSERT (s != NULL);
eea6121a 14576 s->size = sizeof ELF_DYNAMIC_INTERPRETER;
252b5132
RH		 14577 s->contents = (unsigned char *) ELF_DYNAMIC_INTERPRETER;
14578 }
14579 }
5e681ec4
PB		 14580
14581 /* Set up .got offsets for local syms, and space for local dynamic
14582 relocs. */
c72f2fb2 14583 for (ibfd = info->input_bfds; ibfd != NULL; ibfd = ibfd->link.next)
252b5132 14584 {
5e681ec4
PB		 14585 bfd_signed_vma *local_got;
14586 bfd_signed_vma *end_local_got;
34e77a92 14587 struct arm_local_iplt_info **local_iplt_ptr, *local_iplt;
5e681ec4 14588 char *local_tls_type;
0855e32b 14589 bfd_vma *local_tlsdesc_gotent;
5e681ec4
PB		 14590 bfd_size_type locsymcount;
14591 Elf_Internal_Shdr *symtab_hdr;
14592 asection *srel;
4dfe6ac6 14593 bfd_boolean is_vxworks = htab->vxworks_p;
34e77a92 14594 unsigned int symndx;
5e681ec4 14595
0ffa91dd 14596 if (! is_arm_elf (ibfd))
5e681ec4
PB		 14597 continue;
14598
14599 for (s = ibfd->sections; s != NULL; s = s->next)
14600 {
0bdcacaf 14601 struct elf_dyn_relocs *p;
5e681ec4 14602
0bdcacaf 14603 for (p = (struct elf_dyn_relocs *)
99059e56 14604 elf_section_data (s)->local_dynrel; p != NULL; p = p->next)
5e681ec4 14605 {
0bdcacaf
RS		 14606 if (!bfd_is_abs_section (p->sec)
14607 && bfd_is_abs_section (p->sec->output_section))
5e681ec4
PB		 14608 {
14609 /* Input section has been discarded, either because
14610 it is a copy of a linkonce section or due to
14611 linker script /DISCARD/, so we'll be discarding
14612 the relocs too. */
14613 }
3348747a 14614 else if (is_vxworks
0bdcacaf 14615 && strcmp (p->sec->output_section->name,
3348747a
NS		 14616 ".tls_vars") == 0)
14617 {
14618 /* Relocations in vxworks .tls_vars sections are
14619 handled specially by the loader. */
14620 }
5e681ec4
PB		 14621 else if (p->count != 0)
14622 {
0bdcacaf 14623 srel = elf_section_data (p->sec)->sreloc;
47beaa6a 14624 elf32_arm_allocate_dynrelocs (info, srel, p->count);
0bdcacaf 14625 if ((p->sec->output_section->flags & SEC_READONLY) != 0)
5e681ec4
PB		 14626 info->flags |= DF_TEXTREL;
14627 }
14628 }
14629 }
14630
14631 local_got = elf_local_got_refcounts (ibfd);
14632 if (!local_got)
14633 continue;
14634
0ffa91dd 14635 symtab_hdr = & elf_symtab_hdr (ibfd);
5e681ec4
PB		 14636 locsymcount = symtab_hdr->sh_info;
14637 end_local_got = local_got + locsymcount;
34e77a92 14638 local_iplt_ptr = elf32_arm_local_iplt (ibfd);
ba93b8ac 14639 local_tls_type = elf32_arm_local_got_tls_type (ibfd);
0855e32b 14640 local_tlsdesc_gotent = elf32_arm_local_tlsdesc_gotent (ibfd);
34e77a92 14641 symndx = 0;
362d30a1
RS		 14642 s = htab->root.sgot;
14643 srel = htab->root.srelgot;
0855e32b 14644 for (; local_got < end_local_got;
34e77a92
RS		 14645 ++local_got, ++local_iplt_ptr, ++local_tls_type,
14646 ++local_tlsdesc_gotent, ++symndx)
5e681ec4 14647 {
0855e32b 14648 *local_tlsdesc_gotent = (bfd_vma) -1;
34e77a92
RS		 14649 local_iplt = *local_iplt_ptr;
14650 if (local_iplt != NULL)
14651 {
14652 struct elf_dyn_relocs *p;
14653
14654 if (local_iplt->root.refcount > 0)
14655 {
14656 elf32_arm_allocate_plt_entry (info, TRUE,
14657 &local_iplt->root,
14658 &local_iplt->arm);
14659 if (local_iplt->arm.noncall_refcount == 0)
14660 /* All references to the PLT are calls, so all
14661 non-call references can resolve directly to the
14662 run-time target. This means that the .got entry
14663 would be the same as the .igot.plt entry, so there's
14664 no point creating both. */
14665 *local_got = 0;
14666 }
14667 else
14668 {
14669 BFD_ASSERT (local_iplt->arm.noncall_refcount == 0);
14670 local_iplt->root.offset = (bfd_vma) -1;
14671 }
14672
14673 for (p = local_iplt->dyn_relocs; p != NULL; p = p->next)
14674 {
14675 asection *psrel;
14676
14677 psrel = elf_section_data (p->sec)->sreloc;
14678 if (local_iplt->arm.noncall_refcount == 0)
14679 elf32_arm_allocate_irelocs (info, psrel, p->count);
14680 else
14681 elf32_arm_allocate_dynrelocs (info, psrel, p->count);
14682 }
14683 }
5e681ec4
PB		 14684 if (*local_got > 0)
14685 {
34e77a92
RS		 14686 Elf_Internal_Sym *isym;
14687
eea6121a 14688 *local_got = s->size;
ba93b8ac
DJ		 14689 if (*local_tls_type & GOT_TLS_GD)
14690 /* TLS_GD relocs need an 8-byte structure in the GOT. */
14691 s->size += 8;
0855e32b
NS		 14692 if (*local_tls_type & GOT_TLS_GDESC)
14693 {
14694 *local_tlsdesc_gotent = htab->root.sgotplt->size
14695 - elf32_arm_compute_jump_table_size (htab);
14696 htab->root.sgotplt->size += 8;
14697 *local_got = (bfd_vma) -2;
34e77a92 14698 /* plt.got_offset needs to know there's a TLS_DESC
0855e32b 14699 reloc in the middle of .got.plt. */
99059e56 14700 htab->num_tls_desc++;
0855e32b 14701 }
ba93b8ac
DJ		 14702 if (*local_tls_type & GOT_TLS_IE)
14703 s->size += 4;
ba93b8ac 14704
0855e32b
NS		 14705 if (*local_tls_type & GOT_NORMAL)
14706 {
14707 /* If the symbol is both GD and GDESC, *local_got
14708 may have been overwritten. */
14709 *local_got = s->size;
14710 s->size += 4;
14711 }
14712
34e77a92
RS		 14713 isym = bfd_sym_from_r_symndx (&htab->sym_cache, ibfd, symndx);
14714 if (isym == NULL)
14715 return FALSE;
14716
14717 /* If all references to an STT_GNU_IFUNC PLT are calls,
14718 then all non-call references, including this GOT entry,
14719 resolve directly to the run-time target. */
14720 if (ELF32_ST_TYPE (isym->st_info) == STT_GNU_IFUNC
14721 && (local_iplt == NULL
14722 || local_iplt->arm.noncall_refcount == 0))
14723 elf32_arm_allocate_irelocs (info, srel, 1);
0e1862bb 14724 else if (bfd_link_pic (info) || output_bfd->flags & DYNAMIC)
0855e32b 14725 {
0e1862bb 14726 if ((bfd_link_pic (info) && !(*local_tls_type & GOT_TLS_GDESC))
3064e1ff
JB		 14727 || *local_tls_type & GOT_TLS_GD)
14728 elf32_arm_allocate_dynrelocs (info, srel, 1);
99059e56 14729
0e1862bb 14730 if (bfd_link_pic (info) && *local_tls_type & GOT_TLS_GDESC)
3064e1ff
JB		 14731 {
14732 elf32_arm_allocate_dynrelocs (info,
14733 htab->root.srelplt, 1);
14734 htab->tls_trampoline = -1;
14735 }
0855e32b 14736 }
5e681ec4
PB		 14737 }
14738 else
14739 *local_got = (bfd_vma) -1;
14740 }
252b5132
RH		 14741 }
14742
ba93b8ac
DJ		 14743 if (htab->tls_ldm_got.refcount > 0)
14744 {
14745 /* Allocate two GOT entries and one dynamic relocation (if necessary)
14746 for R_ARM_TLS_LDM32 relocations. */
362d30a1
RS		 14747 htab->tls_ldm_got.offset = htab->root.sgot->size;
14748 htab->root.sgot->size += 8;
0e1862bb 14749 if (bfd_link_pic (info))
47beaa6a 14750 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
ba93b8ac
DJ		 14751 }
14752 else
14753 htab->tls_ldm_got.offset = -1;
14754
5e681ec4
PB		 14755 /* Allocate global sym .plt and .got entries, and space for global
14756 sym dynamic relocs. */
47beaa6a 14757 elf_link_hash_traverse (& htab->root, allocate_dynrelocs_for_symbol, info);
252b5132 14758
d504ffc8 14759 /* Here we rummage through the found bfds to collect glue information. */
c72f2fb2 14760 for (ibfd = info->input_bfds; ibfd != NULL; ibfd = ibfd->link.next)
c7b8f16e 14761 {
0ffa91dd 14762 if (! is_arm_elf (ibfd))
e44a2c9c
AM		 14763 continue;
14764
c7b8f16e
JB		 14765 /* Initialise mapping tables for code/data. */
14766 bfd_elf32_arm_init_maps (ibfd);
906e58ca 14767
c7b8f16e 14768 if (!bfd_elf32_arm_process_before_allocation (ibfd, info)
a504d23a
LA		 14769 || !bfd_elf32_arm_vfp11_erratum_scan (ibfd, info)
14770 || !bfd_elf32_arm_stm32l4xx_erratum_scan (ibfd, info))
99059e56
RM		 14771 /* xgettext:c-format */
14772 _bfd_error_handler (_("Errors encountered processing file %s"),
c7b8f16e
JB		 14773 ibfd->filename);
14774 }
d504ffc8 14775
3e6b1042
DJ		 14776 /* Allocate space for the glue sections now that we've sized them. */
14777 bfd_elf32_arm_allocate_interworking_sections (info);
14778
0855e32b
NS		 14779 /* For every jump slot reserved in the sgotplt, reloc_count is
14780 incremented. However, when we reserve space for TLS descriptors,
14781 it's not incremented, so in order to compute the space reserved
14782 for them, it suffices to multiply the reloc count by the jump
14783 slot size. */
14784 if (htab->root.srelplt)
14785 htab->sgotplt_jump_table_size = elf32_arm_compute_jump_table_size(htab);
14786
14787 if (htab->tls_trampoline)
14788 {
14789 if (htab->root.splt->size == 0)
14790 htab->root.splt->size += htab->plt_header_size;
b38cadfb 14791
0855e32b
NS		 14792 htab->tls_trampoline = htab->root.splt->size;
14793 htab->root.splt->size += htab->plt_entry_size;
b38cadfb 14794
0855e32b 14795 /* If we're not using lazy TLS relocations, don't generate the
99059e56 14796 PLT and GOT entries they require. */
0855e32b
NS		 14797 if (!(info->flags & DF_BIND_NOW))
14798 {
14799 htab->dt_tlsdesc_got = htab->root.sgot->size;
14800 htab->root.sgot->size += 4;
14801
14802 htab->dt_tlsdesc_plt = htab->root.splt->size;
14803 htab->root.splt->size += 4 * ARRAY_SIZE (dl_tlsdesc_lazy_trampoline);
14804 }
14805 }
14806
252b5132
RH		 14807 /* The check_relocs and adjust_dynamic_symbol entry points have
14808 determined the sizes of the various dynamic sections. Allocate
14809 memory for them. */
b34976b6
AM		 14810 plt = FALSE;
14811 relocs = FALSE;
252b5132
RH		 14812 for (s = dynobj->sections; s != NULL; s = s->next)
14813 {
14814 const char * name;
252b5132
RH		 14815
14816 if ((s->flags & SEC_LINKER_CREATED) == 0)
14817 continue;
14818
14819 /* It's OK to base decisions on the section name, because none
14820 of the dynobj section names depend upon the input files. */
14821 name = bfd_get_section_name (dynobj, s);
14822
34e77a92 14823 if (s == htab->root.splt)
252b5132 14824 {
c456f082
AM		 14825 /* Remember whether there is a PLT. */
14826 plt = s->size != 0;
252b5132 14827 }
0112cd26 14828 else if (CONST_STRNEQ (name, ".rel"))
252b5132 14829 {
c456f082 14830 if (s->size != 0)
252b5132 14831 {
252b5132 14832 /* Remember whether there are any reloc sections other
00a97672 14833 than .rel(a).plt and .rela.plt.unloaded. */
362d30a1 14834 if (s != htab->root.srelplt && s != htab->srelplt2)
b34976b6 14835 relocs = TRUE;
252b5132
RH		 14836
14837 /* We use the reloc_count field as a counter if we need
14838 to copy relocs into the output file. */
14839 s->reloc_count = 0;
14840 }
14841 }
34e77a92
RS		 14842 else if (s != htab->root.sgot
14843 && s != htab->root.sgotplt
14844 && s != htab->root.iplt
14845 && s != htab->root.igotplt
14846 && s != htab->sdynbss)
252b5132
RH		 14847 {
14848 /* It's not one of our sections, so don't allocate space. */
14849 continue;
14850 }
14851
c456f082 14852 if (s->size == 0)
252b5132 14853 {
c456f082 14854 /* If we don't need this section, strip it from the
00a97672
RS		 14855 output file. This is mostly to handle .rel(a).bss and
14856 .rel(a).plt. We must create both sections in
c456f082
AM		 14857 create_dynamic_sections, because they must be created
14858 before the linker maps input sections to output
14859 sections. The linker does that before
14860 adjust_dynamic_symbol is called, and it is that
14861 function which decides whether anything needs to go
14862 into these sections. */
8423293d 14863 s->flags |= SEC_EXCLUDE;
252b5132
RH		 14864 continue;
14865 }
14866
c456f082
AM		 14867 if ((s->flags & SEC_HAS_CONTENTS) == 0)
14868 continue;
14869
252b5132 14870 /* Allocate memory for the section contents. */
21d799b5 14871 s->contents = (unsigned char *) bfd_zalloc (dynobj, s->size);
c456f082 14872 if (s->contents == NULL)
b34976b6 14873 return FALSE;
252b5132
RH		 14874 }
14875
14876 if (elf_hash_table (info)->dynamic_sections_created)
14877 {
14878 /* Add some entries to the .dynamic section. We fill in the
14879 values later, in elf32_arm_finish_dynamic_sections, but we
14880 must add the entries now so that we get the correct size for
14881 the .dynamic section. The DT_DEBUG entry is filled in by the
14882 dynamic linker and used by the debugger. */
dc810e39 14883#define add_dynamic_entry(TAG, VAL) \
5a580b3a 14884 _bfd_elf_add_dynamic_entry (info, TAG, VAL)
dc810e39 14885
0e1862bb 14886 if (bfd_link_executable (info))
252b5132 14887 {
dc810e39 14888 if (!add_dynamic_entry (DT_DEBUG, 0))
b34976b6 14889 return FALSE;
252b5132
RH		 14890 }
14891
14892 if (plt)
14893 {
dc810e39
AM		 14894 if ( !add_dynamic_entry (DT_PLTGOT, 0)
14895 || !add_dynamic_entry (DT_PLTRELSZ, 0)
00a97672
RS		 14896 || !add_dynamic_entry (DT_PLTREL,
14897 htab->use_rel ? DT_REL : DT_RELA)
dc810e39 14898 || !add_dynamic_entry (DT_JMPREL, 0))
b34976b6 14899 return FALSE;
0855e32b
NS		 14900
14901 if (htab->dt_tlsdesc_plt &&
b38cadfb 14902 (!add_dynamic_entry (DT_TLSDESC_PLT,0)
0855e32b 14903 || !add_dynamic_entry (DT_TLSDESC_GOT,0)))
b38cadfb 14904 return FALSE;
252b5132
RH		 14905 }
14906
14907 if (relocs)
14908 {
00a97672
RS		 14909 if (htab->use_rel)
14910 {
14911 if (!add_dynamic_entry (DT_REL, 0)
14912 || !add_dynamic_entry (DT_RELSZ, 0)
14913 || !add_dynamic_entry (DT_RELENT, RELOC_SIZE (htab)))
14914 return FALSE;
14915 }
14916 else
14917 {
14918 if (!add_dynamic_entry (DT_RELA, 0)
14919 || !add_dynamic_entry (DT_RELASZ, 0)
14920 || !add_dynamic_entry (DT_RELAENT, RELOC_SIZE (htab)))
14921 return FALSE;
14922 }
252b5132
RH		 14923 }
14924
08d1f311
DJ		 14925 /* If any dynamic relocs apply to a read-only section,
14926 then we need a DT_TEXTREL entry. */
14927 if ((info->flags & DF_TEXTREL) == 0)
8029a119
NC		 14928 elf_link_hash_traverse (& htab->root, elf32_arm_readonly_dynrelocs,
14929 info);
08d1f311 14930
99e4ae17 14931 if ((info->flags & DF_TEXTREL) != 0)
252b5132 14932 {
dc810e39 14933 if (!add_dynamic_entry (DT_TEXTREL, 0))
b34976b6 14934 return FALSE;
252b5132 14935 }
7a2b07ff
NS		 14936 if (htab->vxworks_p
14937 && !elf_vxworks_add_dynamic_entries (output_bfd, info))
14938 return FALSE;
252b5132 14939 }
8532796c 14940#undef add_dynamic_entry
252b5132 14941
b34976b6 14942 return TRUE;
252b5132
RH		 14943}
14944
0855e32b
NS		 14945/* Size sections even though they're not dynamic. We use it to setup
14946 _TLS_MODULE_BASE_, if needed. */
14947
14948static bfd_boolean
14949elf32_arm_always_size_sections (bfd *output_bfd,
99059e56 14950 struct bfd_link_info *info)
0855e32b
NS		 14951{
14952 asection *tls_sec;
14953
0e1862bb 14954 if (bfd_link_relocatable (info))
0855e32b
NS		 14955 return TRUE;
14956
14957 tls_sec = elf_hash_table (info)->tls_sec;
14958
14959 if (tls_sec)
14960 {
14961 struct elf_link_hash_entry *tlsbase;
14962
14963 tlsbase = elf_link_hash_lookup
14964 (elf_hash_table (info), "_TLS_MODULE_BASE_", TRUE, TRUE, FALSE);
14965
14966 if (tlsbase)
99059e56
RM		 14967 {
14968 struct bfd_link_hash_entry *bh = NULL;
0855e32b 14969 const struct elf_backend_data *bed
99059e56 14970 = get_elf_backend_data (output_bfd);
0855e32b 14971
99059e56 14972 if (!(_bfd_generic_link_add_one_symbol
0855e32b
NS		 14973 (info, output_bfd, "_TLS_MODULE_BASE_", BSF_LOCAL,
14974 tls_sec, 0, NULL, FALSE,
14975 bed->collect, &bh)))
14976 return FALSE;
b38cadfb 14977
99059e56
RM		 14978 tlsbase->type = STT_TLS;
14979 tlsbase = (struct elf_link_hash_entry *)bh;
14980 tlsbase->def_regular = 1;
14981 tlsbase->other = STV_HIDDEN;
14982 (*bed->elf_backend_hide_symbol) (info, tlsbase, TRUE);
0855e32b
NS		 14983 }
14984 }
14985 return TRUE;
14986}
14987
252b5132
RH		 14988/* Finish up dynamic symbol handling. We set the contents of various
14989 dynamic sections here. */
14990
b34976b6 14991static bfd_boolean
906e58ca
NC		 14992elf32_arm_finish_dynamic_symbol (bfd * output_bfd,
14993 struct bfd_link_info * info,
14994 struct elf_link_hash_entry * h,
14995 Elf_Internal_Sym * sym)
252b5132 14996{
e5a52504 14997 struct elf32_arm_link_hash_table *htab;
b7693d02 14998 struct elf32_arm_link_hash_entry *eh;
252b5132 14999
e5a52504 15000 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 15001 if (htab == NULL)
15002 return FALSE;
15003
b7693d02 15004 eh = (struct elf32_arm_link_hash_entry *) h;
252b5132
RH		 15005
15006 if (h->plt.offset != (bfd_vma) -1)
15007 {
34e77a92 15008 if (!eh->is_iplt)
e5a52504 15009 {
34e77a92 15010 BFD_ASSERT (h->dynindx != -1);
57460bcf
NC		 15011 if (! elf32_arm_populate_plt_entry (output_bfd, info, &h->plt, &eh->plt,
15012 h->dynindx, 0))
15013 return FALSE;
e5a52504 15014 }
57e8b36a 15015
f5385ebf 15016 if (!h->def_regular)
252b5132
RH		 15017 {
15018 /* Mark the symbol as undefined, rather than as defined in
3a635617 15019 the .plt section. */
252b5132 15020 sym->st_shndx = SHN_UNDEF;
3a635617 15021 /* If the symbol is weak we need to clear the value.
d982ba73
PB		 15022 Otherwise, the PLT entry would provide a definition for
15023 the symbol even if the symbol wasn't defined anywhere,
3a635617
WN		 15024 and so the symbol would never be NULL. Leave the value if
15025 there were any relocations where pointer equality matters
15026 (this is a clue for the dynamic linker, to make function
15027 pointer comparisons work between an application and shared
15028 library). */
97323ad1 15029 if (!h->ref_regular_nonweak || !h->pointer_equality_needed)
d982ba73 15030 sym->st_value = 0;
252b5132 15031 }
34e77a92
RS		 15032 else if (eh->is_iplt && eh->plt.noncall_refcount != 0)
15033 {
15034 /* At least one non-call relocation references this .iplt entry,
15035 so the .iplt entry is the function's canonical address. */
15036 sym->st_info = ELF_ST_INFO (ELF_ST_BIND (sym->st_info), STT_FUNC);
15037 sym->st_target_internal = ST_BRANCH_TO_ARM;
15038 sym->st_shndx = (_bfd_elf_section_from_bfd_section
15039 (output_bfd, htab->root.iplt->output_section));
15040 sym->st_value = (h->plt.offset
15041 + htab->root.iplt->output_section->vma
15042 + htab->root.iplt->output_offset);
15043 }
252b5132
RH		 15044 }
15045
f5385ebf 15046 if (h->needs_copy)
252b5132
RH		 15047 {
15048 asection * s;
947216bf 15049 Elf_Internal_Rela rel;
252b5132
RH		 15050
15051 /* This symbol needs a copy reloc. Set it up. */
252b5132
RH		 15052 BFD_ASSERT (h->dynindx != -1
15053 && (h->root.type == bfd_link_hash_defined
15054 || h->root.type == bfd_link_hash_defweak));
15055
362d30a1 15056 s = htab->srelbss;
252b5132
RH		 15057 BFD_ASSERT (s != NULL);
15058
00a97672 15059 rel.r_addend = 0;
252b5132
RH		 15060 rel.r_offset = (h->root.u.def.value
15061 + h->root.u.def.section->output_section->vma
15062 + h->root.u.def.section->output_offset);
15063 rel.r_info = ELF32_R_INFO (h->dynindx, R_ARM_COPY);
47beaa6a 15064 elf32_arm_add_dynreloc (output_bfd, info, s, &rel);
252b5132
RH		 15065 }
15066
00a97672
RS		 15067 /* Mark _DYNAMIC and _GLOBAL_OFFSET_TABLE_ as absolute. On VxWorks,
15068 the _GLOBAL_OFFSET_TABLE_ symbol is not absolute: it is relative
15069 to the ".got" section. */
9637f6ef 15070 if (h == htab->root.hdynamic
00a97672 15071 || (!htab->vxworks_p && h == htab->root.hgot))
252b5132
RH		 15072 sym->st_shndx = SHN_ABS;
15073
b34976b6 15074 return TRUE;
252b5132
RH		 15075}
15076
0855e32b
NS		 15077static void
15078arm_put_trampoline (struct elf32_arm_link_hash_table *htab, bfd *output_bfd,
15079 void *contents,
15080 const unsigned long *template, unsigned count)
15081{
15082 unsigned ix;
b38cadfb 15083
0855e32b
NS		 15084 for (ix = 0; ix != count; ix++)
15085 {
15086 unsigned long insn = template[ix];
15087
15088 /* Emit mov pc,rx if bx is not permitted. */
15089 if (htab->fix_v4bx == 1 && (insn & 0x0ffffff0) == 0x012fff10)
15090 insn = (insn & 0xf000000f) | 0x01a0f000;
15091 put_arm_insn (htab, output_bfd, insn, (char *)contents + ix*4);
15092 }
15093}
15094
99059e56
RM		 15095/* Install the special first PLT entry for elf32-arm-nacl. Unlike
15096 other variants, NaCl needs this entry in a static executable's
15097 .iplt too. When we're handling that case, GOT_DISPLACEMENT is
15098 zero. For .iplt really only the last bundle is useful, and .iplt
15099 could have a shorter first entry, with each individual PLT entry's
15100 relative branch calculated differently so it targets the last
15101 bundle instead of the instruction before it (labelled .Lplt_tail
15102 above). But it's simpler to keep the size and layout of PLT0
15103 consistent with the dynamic case, at the cost of some dead code at
15104 the start of .iplt and the one dead store to the stack at the start
15105 of .Lplt_tail. */
15106static void
15107arm_nacl_put_plt0 (struct elf32_arm_link_hash_table *htab, bfd *output_bfd,
15108 asection *plt, bfd_vma got_displacement)
15109{
15110 unsigned int i;
15111
15112 put_arm_insn (htab, output_bfd,
15113 elf32_arm_nacl_plt0_entry[0]
15114 | arm_movw_immediate (got_displacement),
15115 plt->contents + 0);
15116 put_arm_insn (htab, output_bfd,
15117 elf32_arm_nacl_plt0_entry[1]
15118 | arm_movt_immediate (got_displacement),
15119 plt->contents + 4);
15120
15121 for (i = 2; i < ARRAY_SIZE (elf32_arm_nacl_plt0_entry); ++i)
15122 put_arm_insn (htab, output_bfd,
15123 elf32_arm_nacl_plt0_entry[i],
15124 plt->contents + (i * 4));
15125}
15126
252b5132
RH		 15127/* Finish up the dynamic sections. */
15128
b34976b6 15129static bfd_boolean
57e8b36a 15130elf32_arm_finish_dynamic_sections (bfd * output_bfd, struct bfd_link_info * info)
252b5132
RH		 15131{
15132 bfd * dynobj;
15133 asection * sgot;
15134 asection * sdyn;
4dfe6ac6
NC		 15135 struct elf32_arm_link_hash_table *htab;
15136
15137 htab = elf32_arm_hash_table (info);
15138 if (htab == NULL)
15139 return FALSE;
252b5132
RH		 15140
15141 dynobj = elf_hash_table (info)->dynobj;
15142
362d30a1 15143 sgot = htab->root.sgotplt;
894891db
NC		 15144 /* A broken linker script might have discarded the dynamic sections.
15145 Catch this here so that we do not seg-fault later on. */
15146 if (sgot != NULL && bfd_is_abs_section (sgot->output_section))
15147 return FALSE;
3d4d4302 15148 sdyn = bfd_get_linker_section (dynobj, ".dynamic");
252b5132
RH		 15149
15150 if (elf_hash_table (info)->dynamic_sections_created)
15151 {
15152 asection *splt;
15153 Elf32_External_Dyn *dyncon, *dynconend;
15154
362d30a1 15155 splt = htab->root.splt;
24a1ba0f 15156 BFD_ASSERT (splt != NULL && sdyn != NULL);
cbc704f3 15157 BFD_ASSERT (htab->symbian_p || sgot != NULL);
252b5132
RH		 15158
15159 dyncon = (Elf32_External_Dyn *) sdyn->contents;
eea6121a 15160 dynconend = (Elf32_External_Dyn *) (sdyn->contents + sdyn->size);
9b485d32 15161
252b5132
RH		 15162 for (; dyncon < dynconend; dyncon++)
15163 {
15164 Elf_Internal_Dyn dyn;
15165 const char * name;
15166 asection * s;
15167
15168 bfd_elf32_swap_dyn_in (dynobj, dyncon, &dyn);
15169
15170 switch (dyn.d_tag)
15171 {
229fcec5
MM		 15172 unsigned int type;
15173
252b5132 15174 default:
7a2b07ff
NS		 15175 if (htab->vxworks_p
15176 && elf_vxworks_finish_dynamic_entry (output_bfd, &dyn))
15177 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
252b5132
RH		 15178 break;
15179
229fcec5
MM		 15180 case DT_HASH:
15181 name = ".hash";
15182 goto get_vma_if_bpabi;
15183 case DT_STRTAB:
15184 name = ".dynstr";
15185 goto get_vma_if_bpabi;
15186 case DT_SYMTAB:
15187 name = ".dynsym";
15188 goto get_vma_if_bpabi;
c0042f5d
MM		 15189 case DT_VERSYM:
15190 name = ".gnu.version";
15191 goto get_vma_if_bpabi;
15192 case DT_VERDEF:
15193 name = ".gnu.version_d";
15194 goto get_vma_if_bpabi;
15195 case DT_VERNEED:
15196 name = ".gnu.version_r";
15197 goto get_vma_if_bpabi;
15198
252b5132
RH		 15199 case DT_PLTGOT:
15200 name = ".got";
15201 goto get_vma;
15202 case DT_JMPREL:
00a97672 15203 name = RELOC_SECTION (htab, ".plt");
252b5132
RH		 15204 get_vma:
15205 s = bfd_get_section_by_name (output_bfd, name);
05456594
NC		 15206 if (s == NULL)
15207 {
15208 /* PR ld/14397: Issue an error message if a required section is missing. */
15209 (*_bfd_error_handler)
15210 (_("error: required section '%s' not found in the linker script"), name);
15211 bfd_set_error (bfd_error_invalid_operation);
15212 return FALSE;
15213 }
229fcec5
MM		 15214 if (!htab->symbian_p)
15215 dyn.d_un.d_ptr = s->vma;
15216 else
15217 /* In the BPABI, tags in the PT_DYNAMIC section point
15218 at the file offset, not the memory address, for the
15219 convenience of the post linker. */
15220 dyn.d_un.d_ptr = s->filepos;
252b5132
RH		 15221 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
15222 break;
15223
229fcec5
MM		 15224 get_vma_if_bpabi:
15225 if (htab->symbian_p)
15226 goto get_vma;
15227 break;
15228
252b5132 15229 case DT_PLTRELSZ:
362d30a1 15230 s = htab->root.srelplt;
252b5132 15231 BFD_ASSERT (s != NULL);
eea6121a 15232 dyn.d_un.d_val = s->size;
252b5132
RH		 15233 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
15234 break;
906e58ca 15235
252b5132 15236 case DT_RELSZ:
00a97672 15237 case DT_RELASZ:
229fcec5
MM		 15238 if (!htab->symbian_p)
15239 {
15240 /* My reading of the SVR4 ABI indicates that the
15241 procedure linkage table relocs (DT_JMPREL) should be
15242 included in the overall relocs (DT_REL). This is
15243 what Solaris does. However, UnixWare can not handle
15244 that case. Therefore, we override the DT_RELSZ entry
15245 here to make it not include the JMPREL relocs. Since
00a97672 15246 the linker script arranges for .rel(a).plt to follow all
229fcec5
MM		 15247 other relocation sections, we don't have to worry
15248 about changing the DT_REL entry. */
362d30a1 15249 s = htab->root.srelplt;
229fcec5
MM		 15250 if (s != NULL)
15251 dyn.d_un.d_val -= s->size;
15252 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
15253 break;
15254 }
8029a119 15255 /* Fall through. */
229fcec5
MM		 15256
15257 case DT_REL:
15258 case DT_RELA:
229fcec5
MM		 15259 /* In the BPABI, the DT_REL tag must point at the file
15260 offset, not the VMA, of the first relocation
15261 section. So, we use code similar to that in
15262 elflink.c, but do not check for SHF_ALLOC on the
15263 relcoation section, since relocations sections are
15264 never allocated under the BPABI. The comments above
15265 about Unixware notwithstanding, we include all of the
15266 relocations here. */
15267 if (htab->symbian_p)
15268 {
15269 unsigned int i;
15270 type = ((dyn.d_tag == DT_REL || dyn.d_tag == DT_RELSZ)
15271 ? SHT_REL : SHT_RELA);
15272 dyn.d_un.d_val = 0;
15273 for (i = 1; i < elf_numsections (output_bfd); i++)
15274 {
906e58ca 15275 Elf_Internal_Shdr *hdr
229fcec5
MM		 15276 = elf_elfsections (output_bfd)[i];
15277 if (hdr->sh_type == type)
15278 {
906e58ca 15279 if (dyn.d_tag == DT_RELSZ
229fcec5
MM		 15280 || dyn.d_tag == DT_RELASZ)
15281 dyn.d_un.d_val += hdr->sh_size;
de52dba4
AM		 15282 else if ((ufile_ptr) hdr->sh_offset
15283 <= dyn.d_un.d_val - 1)
229fcec5
MM		 15284 dyn.d_un.d_val = hdr->sh_offset;
15285 }
15286 }
15287 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
15288 }
252b5132 15289 break;
88f7bcd5 15290
0855e32b 15291 case DT_TLSDESC_PLT:
99059e56 15292 s = htab->root.splt;
0855e32b
NS		 15293 dyn.d_un.d_ptr = (s->output_section->vma + s->output_offset
15294 + htab->dt_tlsdesc_plt);
15295 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
15296 break;
15297
15298 case DT_TLSDESC_GOT:
99059e56 15299 s = htab->root.sgot;
0855e32b 15300 dyn.d_un.d_ptr = (s->output_section->vma + s->output_offset
99059e56 15301 + htab->dt_tlsdesc_got);
0855e32b
NS		 15302 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
15303 break;
15304
88f7bcd5
NC		 15305 /* Set the bottom bit of DT_INIT/FINI if the
15306 corresponding function is Thumb. */
15307 case DT_INIT:
15308 name = info->init_function;
15309 goto get_sym;
15310 case DT_FINI:
15311 name = info->fini_function;
15312 get_sym:
15313 /* If it wasn't set by elf_bfd_final_link
4cc11e76 15314 then there is nothing to adjust. */
88f7bcd5
NC		 15315 if (dyn.d_un.d_val != 0)
15316 {
15317 struct elf_link_hash_entry * eh;
15318
15319 eh = elf_link_hash_lookup (elf_hash_table (info), name,
b34976b6 15320 FALSE, FALSE, TRUE);
35fc36a8 15321 if (eh != NULL && eh->target_internal == ST_BRANCH_TO_THUMB)
88f7bcd5
NC		 15322 {
15323 dyn.d_un.d_val |= 1;
b34976b6 15324 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
88f7bcd5
NC		 15325 }
15326 }
15327 break;
252b5132
RH		 15328 }
15329 }
15330
24a1ba0f 15331 /* Fill in the first entry in the procedure linkage table. */
4dfe6ac6 15332 if (splt->size > 0 && htab->plt_header_size)
f7a74f8c 15333 {
00a97672
RS		 15334 const bfd_vma *plt0_entry;
15335 bfd_vma got_address, plt_address, got_displacement;
15336
15337 /* Calculate the addresses of the GOT and PLT. */
15338 got_address = sgot->output_section->vma + sgot->output_offset;
15339 plt_address = splt->output_section->vma + splt->output_offset;
15340
15341 if (htab->vxworks_p)
15342 {
15343 /* The VxWorks GOT is relocated by the dynamic linker.
15344 Therefore, we must emit relocations rather than simply
15345 computing the values now. */
15346 Elf_Internal_Rela rel;
15347
15348 plt0_entry = elf32_arm_vxworks_exec_plt0_entry;
52ab56c2
PB		 15349 put_arm_insn (htab, output_bfd, plt0_entry[0],
15350 splt->contents + 0);
15351 put_arm_insn (htab, output_bfd, plt0_entry[1],
15352 splt->contents + 4);
15353 put_arm_insn (htab, output_bfd, plt0_entry[2],
15354 splt->contents + 8);
00a97672
RS		 15355 bfd_put_32 (output_bfd, got_address, splt->contents + 12);
15356
8029a119 15357 /* Generate a relocation for _GLOBAL_OFFSET_TABLE_. */
00a97672
RS		 15358 rel.r_offset = plt_address + 12;
15359 rel.r_info = ELF32_R_INFO (htab->root.hgot->indx, R_ARM_ABS32);
15360 rel.r_addend = 0;
15361 SWAP_RELOC_OUT (htab) (output_bfd, &rel,
15362 htab->srelplt2->contents);
15363 }
b38cadfb 15364 else if (htab->nacl_p)
99059e56
RM		 15365 arm_nacl_put_plt0 (htab, output_bfd, splt,
15366 got_address + 8 - (plt_address + 16));
eed94f8f
NC		 15367 else if (using_thumb_only (htab))
15368 {
15369 got_displacement = got_address - (plt_address + 12);
15370
15371 plt0_entry = elf32_thumb2_plt0_entry;
15372 put_arm_insn (htab, output_bfd, plt0_entry[0],
15373 splt->contents + 0);
15374 put_arm_insn (htab, output_bfd, plt0_entry[1],
15375 splt->contents + 4);
15376 put_arm_insn (htab, output_bfd, plt0_entry[2],
15377 splt->contents + 8);
15378
15379 bfd_put_32 (output_bfd, got_displacement, splt->contents + 12);
15380 }
00a97672
RS		 15381 else
15382 {
15383 got_displacement = got_address - (plt_address + 16);
15384
15385 plt0_entry = elf32_arm_plt0_entry;
52ab56c2
PB		 15386 put_arm_insn (htab, output_bfd, plt0_entry[0],
15387 splt->contents + 0);
15388 put_arm_insn (htab, output_bfd, plt0_entry[1],
15389 splt->contents + 4);
15390 put_arm_insn (htab, output_bfd, plt0_entry[2],
15391 splt->contents + 8);
15392 put_arm_insn (htab, output_bfd, plt0_entry[3],
15393 splt->contents + 12);
5e681ec4 15394
5e681ec4 15395#ifdef FOUR_WORD_PLT
00a97672
RS		 15396 /* The displacement value goes in the otherwise-unused
15397 last word of the second entry. */
15398 bfd_put_32 (output_bfd, got_displacement, splt->contents + 28);
5e681ec4 15399#else
00a97672 15400 bfd_put_32 (output_bfd, got_displacement, splt->contents + 16);
5e681ec4 15401#endif
00a97672 15402 }
f7a74f8c 15403 }
252b5132
RH		 15404
15405 /* UnixWare sets the entsize of .plt to 4, although that doesn't
15406 really seem like the right value. */
74541ad4
AM		 15407 if (splt->output_section->owner == output_bfd)
15408 elf_section_data (splt->output_section)->this_hdr.sh_entsize = 4;
00a97672 15409
0855e32b
NS		 15410 if (htab->dt_tlsdesc_plt)
15411 {
15412 bfd_vma got_address
15413 = sgot->output_section->vma + sgot->output_offset;
15414 bfd_vma gotplt_address = (htab->root.sgot->output_section->vma
15415 + htab->root.sgot->output_offset);
15416 bfd_vma plt_address
15417 = splt->output_section->vma + splt->output_offset;
15418
b38cadfb 15419 arm_put_trampoline (htab, output_bfd,
0855e32b
NS		 15420 splt->contents + htab->dt_tlsdesc_plt,
15421 dl_tlsdesc_lazy_trampoline, 6);
15422
15423 bfd_put_32 (output_bfd,
15424 gotplt_address + htab->dt_tlsdesc_got
15425 - (plt_address + htab->dt_tlsdesc_plt)
15426 - dl_tlsdesc_lazy_trampoline[6],
15427 splt->contents + htab->dt_tlsdesc_plt + 24);
15428 bfd_put_32 (output_bfd,
15429 got_address - (plt_address + htab->dt_tlsdesc_plt)
15430 - dl_tlsdesc_lazy_trampoline[7],
15431 splt->contents + htab->dt_tlsdesc_plt + 24 + 4);
15432 }
15433
15434 if (htab->tls_trampoline)
15435 {
b38cadfb 15436 arm_put_trampoline (htab, output_bfd,
0855e32b
NS		 15437 splt->contents + htab->tls_trampoline,
15438 tls_trampoline, 3);
15439#ifdef FOUR_WORD_PLT
15440 bfd_put_32 (output_bfd, 0x00000000,
15441 splt->contents + htab->tls_trampoline + 12);
b38cadfb 15442#endif
0855e32b
NS		 15443 }
15444
0e1862bb
L		 15445 if (htab->vxworks_p
15446 && !bfd_link_pic (info)
15447 && htab->root.splt->size > 0)
00a97672
RS		 15448 {
15449 /* Correct the .rel(a).plt.unloaded relocations. They will have
15450 incorrect symbol indexes. */
15451 int num_plts;
eed62c48 15452 unsigned char *p;
00a97672 15453
362d30a1 15454 num_plts = ((htab->root.splt->size - htab->plt_header_size)
00a97672
RS		 15455 / htab->plt_entry_size);
15456 p = htab->srelplt2->contents + RELOC_SIZE (htab);
15457
15458 for (; num_plts; num_plts--)
15459 {
15460 Elf_Internal_Rela rel;
15461
15462 SWAP_RELOC_IN (htab) (output_bfd, p, &rel);
15463 rel.r_info = ELF32_R_INFO (htab->root.hgot->indx, R_ARM_ABS32);
15464 SWAP_RELOC_OUT (htab) (output_bfd, &rel, p);
15465 p += RELOC_SIZE (htab);
15466
15467 SWAP_RELOC_IN (htab) (output_bfd, p, &rel);
15468 rel.r_info = ELF32_R_INFO (htab->root.hplt->indx, R_ARM_ABS32);
15469 SWAP_RELOC_OUT (htab) (output_bfd, &rel, p);
15470 p += RELOC_SIZE (htab);
15471 }
15472 }
252b5132
RH		 15473 }
15474
99059e56
RM		 15475 if (htab->nacl_p && htab->root.iplt != NULL && htab->root.iplt->size > 0)
15476 /* NaCl uses a special first entry in .iplt too. */
15477 arm_nacl_put_plt0 (htab, output_bfd, htab->root.iplt, 0);
15478
252b5132 15479 /* Fill in the first three entries in the global offset table. */
229fcec5 15480 if (sgot)
252b5132 15481 {
229fcec5
MM		 15482 if (sgot->size > 0)
15483 {
15484 if (sdyn == NULL)
15485 bfd_put_32 (output_bfd, (bfd_vma) 0, sgot->contents);
15486 else
15487 bfd_put_32 (output_bfd,
15488 sdyn->output_section->vma + sdyn->output_offset,
15489 sgot->contents);
15490 bfd_put_32 (output_bfd, (bfd_vma) 0, sgot->contents + 4);
15491 bfd_put_32 (output_bfd, (bfd_vma) 0, sgot->contents + 8);
15492 }
252b5132 15493
229fcec5
MM		 15494 elf_section_data (sgot->output_section)->this_hdr.sh_entsize = 4;
15495 }
252b5132 15496
b34976b6 15497 return TRUE;
252b5132
RH		 15498}
15499
ba96a88f 15500static void
57e8b36a 15501elf32_arm_post_process_headers (bfd * abfd, struct bfd_link_info * link_info ATTRIBUTE_UNUSED)
ba96a88f 15502{
9b485d32 15503 Elf_Internal_Ehdr * i_ehdrp; /* ELF file header, internal form. */
e489d0ae 15504 struct elf32_arm_link_hash_table *globals;
ac4c9b04 15505 struct elf_segment_map *m;
ba96a88f
NC		 15506
15507 i_ehdrp = elf_elfheader (abfd);
15508
94a3258f
PB		 15509 if (EF_ARM_EABI_VERSION (i_ehdrp->e_flags) == EF_ARM_EABI_UNKNOWN)
15510 i_ehdrp->e_ident[EI_OSABI] = ELFOSABI_ARM;
15511 else
7394f108 15512 _bfd_elf_post_process_headers (abfd, link_info);
ba96a88f 15513 i_ehdrp->e_ident[EI_ABIVERSION] = ARM_ELF_ABI_VERSION;
e489d0ae 15514
93204d3a
PB		 15515 if (link_info)
15516 {
15517 globals = elf32_arm_hash_table (link_info);
4dfe6ac6 15518 if (globals != NULL && globals->byteswap_code)
93204d3a
PB		 15519 i_ehdrp->e_flags |= EF_ARM_BE8;
15520 }
3bfcb652
NC		 15521
15522 if (EF_ARM_EABI_VERSION (i_ehdrp->e_flags) == EF_ARM_EABI_VER5
15523 && ((i_ehdrp->e_type == ET_DYN) || (i_ehdrp->e_type == ET_EXEC)))
15524 {
15525 int abi = bfd_elf_get_obj_attr_int (abfd, OBJ_ATTR_PROC, Tag_ABI_VFP_args);
5c294fee 15526 if (abi == AEABI_VFP_args_vfp)
3bfcb652
NC		 15527 i_ehdrp->e_flags |= EF_ARM_ABI_FLOAT_HARD;
15528 else
15529 i_ehdrp->e_flags |= EF_ARM_ABI_FLOAT_SOFT;
15530 }
ac4c9b04
MG		 15531
15532 /* Scan segment to set p_flags attribute if it contains only sections with
15533 SHF_ARM_NOREAD flag. */
15534 for (m = elf_seg_map (abfd); m != NULL; m = m->next)
15535 {
15536 unsigned int j;
15537
15538 if (m->count == 0)
15539 continue;
15540 for (j = 0; j < m->count; j++)
15541 {
15542 if (!(elf_section_flags (m->sections[j]) & SHF_ARM_NOREAD))
15543 break;
15544 }
15545 if (j == m->count)
15546 {
15547 m->p_flags = PF_X;
15548 m->p_flags_valid = 1;
15549 }
15550 }
ba96a88f
NC		 15551}
15552
99e4ae17 15553static enum elf_reloc_type_class
7e612e98
AM		 15554elf32_arm_reloc_type_class (const struct bfd_link_info *info ATTRIBUTE_UNUSED,
15555 const asection *rel_sec ATTRIBUTE_UNUSED,
15556 const Elf_Internal_Rela *rela)
99e4ae17 15557{
f51e552e 15558 switch ((int) ELF32_R_TYPE (rela->r_info))
99e4ae17
AJ		 15559 {
15560 case R_ARM_RELATIVE:
15561 return reloc_class_relative;
15562 case R_ARM_JUMP_SLOT:
15563 return reloc_class_plt;
15564 case R_ARM_COPY:
15565 return reloc_class_copy;
109575d7
JW		 15566 case R_ARM_IRELATIVE:
15567 return reloc_class_ifunc;
99e4ae17
AJ		 15568 default:
15569 return reloc_class_normal;
15570 }
15571}
15572
e489d0ae 15573static void
57e8b36a 15574elf32_arm_final_write_processing (bfd *abfd, bfd_boolean linker ATTRIBUTE_UNUSED)
e16bb312 15575{
5a6c6817 15576 bfd_arm_update_notes (abfd, ARM_NOTE_SECTION);
e16bb312
NC		 15577}
15578
40a18ebd
NC		 15579/* Return TRUE if this is an unwinding table entry. */
15580
15581static bfd_boolean
15582is_arm_elf_unwind_section_name (bfd * abfd ATTRIBUTE_UNUSED, const char * name)
15583{
0112cd26
NC		 15584 return (CONST_STRNEQ (name, ELF_STRING_ARM_unwind)
15585 || CONST_STRNEQ (name, ELF_STRING_ARM_unwind_once));
40a18ebd
NC		 15586}
15587
15588
15589/* Set the type and flags for an ARM section. We do this by
15590 the section name, which is a hack, but ought to work. */
15591
15592static bfd_boolean
15593elf32_arm_fake_sections (bfd * abfd, Elf_Internal_Shdr * hdr, asection * sec)
15594{
15595 const char * name;
15596
15597 name = bfd_get_section_name (abfd, sec);
15598
15599 if (is_arm_elf_unwind_section_name (abfd, name))
15600 {
15601 hdr->sh_type = SHT_ARM_EXIDX;
15602 hdr->sh_flags |= SHF_LINK_ORDER;
15603 }
ac4c9b04
MG		 15604
15605 if (sec->flags & SEC_ELF_NOREAD)
15606 hdr->sh_flags |= SHF_ARM_NOREAD;
15607
40a18ebd
NC		 15608 return TRUE;
15609}
15610
6dc132d9
L		 15611/* Handle an ARM specific section when reading an object file. This is
15612 called when bfd_section_from_shdr finds a section with an unknown
15613 type. */
40a18ebd
NC		 15614
15615static bfd_boolean
15616elf32_arm_section_from_shdr (bfd *abfd,
15617 Elf_Internal_Shdr * hdr,
6dc132d9
L		 15618 const char *name,
15619 int shindex)
40a18ebd
NC		 15620{
15621 /* There ought to be a place to keep ELF backend specific flags, but
15622 at the moment there isn't one. We just keep track of the
15623 sections by their name, instead. Fortunately, the ABI gives
15624 names for all the ARM specific sections, so we will probably get
15625 away with this. */
15626 switch (hdr->sh_type)
15627 {
15628 case SHT_ARM_EXIDX:
0951f019
RE		 15629 case SHT_ARM_PREEMPTMAP:
15630 case SHT_ARM_ATTRIBUTES:
40a18ebd
NC		 15631 break;
15632
15633 default:
15634 return FALSE;
15635 }
15636
6dc132d9 15637 if (! _bfd_elf_make_section_from_shdr (abfd, hdr, name, shindex))
40a18ebd
NC		 15638 return FALSE;
15639
15640 return TRUE;
15641}
e489d0ae 15642
44444f50
NC		 15643static _arm_elf_section_data *
15644get_arm_elf_section_data (asection * sec)
15645{
47b2e99c
JZ		 15646 if (sec && sec->owner && is_arm_elf (sec->owner))
15647 return elf32_arm_section_data (sec);
44444f50
NC		 15648 else
15649 return NULL;
8e3de13a
NC		 15650}
15651
4e617b1e
PB		 15652typedef struct
15653{
57402f1e 15654 void *flaginfo;
4e617b1e 15655 struct bfd_link_info *info;
91a5743d
PB		 15656 asection *sec;
15657 int sec_shndx;
6e0b88f1
AM		 15658 int (*func) (void *, const char *, Elf_Internal_Sym *,
15659 asection *, struct elf_link_hash_entry *);
4e617b1e
PB		 15660} output_arch_syminfo;
15661
15662enum map_symbol_type
15663{
15664 ARM_MAP_ARM,
15665 ARM_MAP_THUMB,
15666 ARM_MAP_DATA
15667};
15668
15669
7413f23f 15670/* Output a single mapping symbol. */
4e617b1e
PB		 15671
15672static bfd_boolean
7413f23f
DJ		 15673elf32_arm_output_map_sym (output_arch_syminfo *osi,
15674 enum map_symbol_type type,
15675 bfd_vma offset)
4e617b1e
PB		 15676{
15677 static const char *names[3] = {"$a", "$t", "$d"};
4e617b1e
PB		 15678 Elf_Internal_Sym sym;
15679
91a5743d
PB		 15680 sym.st_value = osi->sec->output_section->vma
15681 + osi->sec->output_offset
15682 + offset;
4e617b1e
PB		 15683 sym.st_size = 0;
15684 sym.st_other = 0;
15685 sym.st_info = ELF_ST_INFO (STB_LOCAL, STT_NOTYPE);
91a5743d 15686 sym.st_shndx = osi->sec_shndx;
35fc36a8 15687 sym.st_target_internal = 0;
fe33d2fa 15688 elf32_arm_section_map_add (osi->sec, names[type][1], offset);
57402f1e 15689 return osi->func (osi->flaginfo, names[type], &sym, osi->sec, NULL) == 1;
4e617b1e
PB		 15690}
15691
34e77a92
RS		 15692/* Output mapping symbols for the PLT entry described by ROOT_PLT and ARM_PLT.
15693 IS_IPLT_ENTRY_P says whether the PLT is in .iplt rather than .plt. */
4e617b1e
PB		 15694
15695static bfd_boolean
34e77a92
RS		 15696elf32_arm_output_plt_map_1 (output_arch_syminfo *osi,
15697 bfd_boolean is_iplt_entry_p,
15698 union gotplt_union *root_plt,
15699 struct arm_plt_info *arm_plt)
4e617b1e 15700{
4e617b1e 15701 struct elf32_arm_link_hash_table *htab;
34e77a92 15702 bfd_vma addr, plt_header_size;
4e617b1e 15703
34e77a92 15704 if (root_plt->offset == (bfd_vma) -1)
4e617b1e
PB		 15705 return TRUE;
15706
4dfe6ac6
NC		 15707 htab = elf32_arm_hash_table (osi->info);
15708 if (htab == NULL)
15709 return FALSE;
15710
34e77a92
RS		 15711 if (is_iplt_entry_p)
15712 {
15713 osi->sec = htab->root.iplt;
15714 plt_header_size = 0;
15715 }
15716 else
15717 {
15718 osi->sec = htab->root.splt;
15719 plt_header_size = htab->plt_header_size;
15720 }
15721 osi->sec_shndx = (_bfd_elf_section_from_bfd_section
15722 (osi->info->output_bfd, osi->sec->output_section));
15723
15724 addr = root_plt->offset & -2;
4e617b1e
PB		 15725 if (htab->symbian_p)
15726 {
7413f23f 15727 if (!elf32_arm_output_map_sym (osi, ARM_MAP_ARM, addr))
4e617b1e 15728 return FALSE;
7413f23f 15729 if (!elf32_arm_output_map_sym (osi, ARM_MAP_DATA, addr + 4))
4e617b1e
PB		 15730 return FALSE;
15731 }
15732 else if (htab->vxworks_p)
15733 {
7413f23f 15734 if (!elf32_arm_output_map_sym (osi, ARM_MAP_ARM, addr))
4e617b1e 15735 return FALSE;
7413f23f 15736 if (!elf32_arm_output_map_sym (osi, ARM_MAP_DATA, addr + 8))
4e617b1e 15737 return FALSE;
7413f23f 15738 if (!elf32_arm_output_map_sym (osi, ARM_MAP_ARM, addr + 12))
4e617b1e 15739 return FALSE;
7413f23f 15740 if (!elf32_arm_output_map_sym (osi, ARM_MAP_DATA, addr + 20))
4e617b1e
PB		 15741 return FALSE;
15742 }
b38cadfb
NC		 15743 else if (htab->nacl_p)
15744 {
15745 if (!elf32_arm_output_map_sym (osi, ARM_MAP_ARM, addr))
15746 return FALSE;
15747 }
eed94f8f
NC		 15748 else if (using_thumb_only (htab))
15749 {
15750 if (!elf32_arm_output_map_sym (osi, ARM_MAP_THUMB, addr))
15751 return FALSE;
6a631e86 15752 }
4e617b1e
PB		 15753 else
15754 {
34e77a92 15755 bfd_boolean thumb_stub_p;
bd97cb95 15756
34e77a92
RS		 15757 thumb_stub_p = elf32_arm_plt_needs_thumb_stub_p (osi->info, arm_plt);
15758 if (thumb_stub_p)
4e617b1e 15759 {
7413f23f 15760 if (!elf32_arm_output_map_sym (osi, ARM_MAP_THUMB, addr - 4))
4e617b1e
PB		 15761 return FALSE;
15762 }
15763#ifdef FOUR_WORD_PLT
7413f23f 15764 if (!elf32_arm_output_map_sym (osi, ARM_MAP_ARM, addr))
4e617b1e 15765 return FALSE;
7413f23f 15766 if (!elf32_arm_output_map_sym (osi, ARM_MAP_DATA, addr + 12))
4e617b1e
PB		 15767 return FALSE;
15768#else
906e58ca 15769 /* A three-word PLT with no Thumb thunk contains only Arm code,
4e617b1e
PB		 15770 so only need to output a mapping symbol for the first PLT entry and
15771 entries with thumb thunks. */
34e77a92 15772 if (thumb_stub_p || addr == plt_header_size)
4e617b1e 15773 {
7413f23f 15774 if (!elf32_arm_output_map_sym (osi, ARM_MAP_ARM, addr))
4e617b1e
PB		 15775 return FALSE;
15776 }
15777#endif
15778 }
15779
15780 return TRUE;
15781}
15782
34e77a92
RS		 15783/* Output mapping symbols for PLT entries associated with H. */
15784
15785static bfd_boolean
15786elf32_arm_output_plt_map (struct elf_link_hash_entry *h, void *inf)
15787{
15788 output_arch_syminfo *osi = (output_arch_syminfo *) inf;
15789 struct elf32_arm_link_hash_entry *eh;
15790
15791 if (h->root.type == bfd_link_hash_indirect)
15792 return TRUE;
15793
15794 if (h->root.type == bfd_link_hash_warning)
15795 /* When warning symbols are created, they **replace** the "real"
15796 entry in the hash table, thus we never get to see the real
15797 symbol in a hash traversal. So look at it now. */
15798 h = (struct elf_link_hash_entry *) h->root.u.i.link;
15799
15800 eh = (struct elf32_arm_link_hash_entry *) h;
15801 return elf32_arm_output_plt_map_1 (osi, SYMBOL_CALLS_LOCAL (osi->info, h),
15802 &h->plt, &eh->plt);
15803}
15804
7413f23f
DJ		 15805/* Output a single local symbol for a generated stub. */
15806
15807static bfd_boolean
15808elf32_arm_output_stub_sym (output_arch_syminfo *osi, const char *name,
15809 bfd_vma offset, bfd_vma size)
15810{
7413f23f
DJ		 15811 Elf_Internal_Sym sym;
15812
7413f23f
DJ		 15813 sym.st_value = osi->sec->output_section->vma
15814 + osi->sec->output_offset
15815 + offset;
15816 sym.st_size = size;
15817 sym.st_other = 0;
15818 sym.st_info = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
15819 sym.st_shndx = osi->sec_shndx;
35fc36a8 15820 sym.st_target_internal = 0;
57402f1e 15821 return osi->func (osi->flaginfo, name, &sym, osi->sec, NULL) == 1;
7413f23f 15822}
4e617b1e 15823
da5938a2 15824static bfd_boolean
8029a119
NC		 15825arm_map_one_stub (struct bfd_hash_entry * gen_entry,
15826 void * in_arg)
da5938a2
NC		 15827{
15828 struct elf32_arm_stub_hash_entry *stub_entry;
da5938a2
NC		 15829 asection *stub_sec;
15830 bfd_vma addr;
7413f23f 15831 char *stub_name;
9a008db3 15832 output_arch_syminfo *osi;
d3ce72d0 15833 const insn_sequence *template_sequence;
461a49ca
DJ		 15834 enum stub_insn_type prev_type;
15835 int size;
15836 int i;
15837 enum map_symbol_type sym_type;
da5938a2
NC		 15838
15839 /* Massage our args to the form they really have. */
15840 stub_entry = (struct elf32_arm_stub_hash_entry *) gen_entry;
9a008db3 15841 osi = (output_arch_syminfo *) in_arg;
da5938a2 15842
da5938a2
NC		 15843 stub_sec = stub_entry->stub_sec;
15844
15845 /* Ensure this stub is attached to the current section being
7413f23f 15846 processed. */
da5938a2
NC		 15847 if (stub_sec != osi->sec)
15848 return TRUE;
15849
7413f23f
DJ		 15850 addr = (bfd_vma) stub_entry->stub_offset;
15851 stub_name = stub_entry->output_name;
da5938a2 15852
d3ce72d0
NC		 15853 template_sequence = stub_entry->stub_template;
15854 switch (template_sequence[0].type)
7413f23f 15855 {
461a49ca
DJ		 15856 case ARM_TYPE:
15857 if (!elf32_arm_output_stub_sym (osi, stub_name, addr, stub_entry->stub_size))
da5938a2
NC		 15858 return FALSE;
15859 break;
461a49ca 15860 case THUMB16_TYPE:
48229727 15861 case THUMB32_TYPE:
461a49ca
DJ		 15862 if (!elf32_arm_output_stub_sym (osi, stub_name, addr | 1,
15863 stub_entry->stub_size))
da5938a2
NC		 15864 return FALSE;
15865 break;
15866 default:
15867 BFD_FAIL ();
48229727 15868 return 0;
7413f23f 15869 }
da5938a2 15870
461a49ca
DJ		 15871 prev_type = DATA_TYPE;
15872 size = 0;
15873 for (i = 0; i < stub_entry->stub_template_size; i++)
15874 {
d3ce72d0 15875 switch (template_sequence[i].type)
461a49ca
DJ		 15876 {
15877 case ARM_TYPE:
15878 sym_type = ARM_MAP_ARM;
15879 break;
15880
15881 case THUMB16_TYPE:
48229727 15882 case THUMB32_TYPE:
461a49ca
DJ		 15883 sym_type = ARM_MAP_THUMB;
15884 break;
15885
15886 case DATA_TYPE:
15887 sym_type = ARM_MAP_DATA;
15888 break;
15889
15890 default:
15891 BFD_FAIL ();
4e31c731 15892 return FALSE;
461a49ca
DJ		 15893 }
15894
d3ce72d0 15895 if (template_sequence[i].type != prev_type)
461a49ca 15896 {
d3ce72d0 15897 prev_type = template_sequence[i].type;
461a49ca
DJ		 15898 if (!elf32_arm_output_map_sym (osi, sym_type, addr + size))
15899 return FALSE;
15900 }
15901
d3ce72d0 15902 switch (template_sequence[i].type)
461a49ca
DJ		 15903 {
15904 case ARM_TYPE:
48229727 15905 case THUMB32_TYPE:
461a49ca
DJ		 15906 size += 4;
15907 break;
15908
15909 case THUMB16_TYPE:
15910 size += 2;
15911 break;
15912
15913 case DATA_TYPE:
15914 size += 4;
15915 break;
15916
15917 default:
15918 BFD_FAIL ();
4e31c731 15919 return FALSE;
461a49ca
DJ		 15920 }
15921 }
15922
da5938a2
NC		 15923 return TRUE;
15924}
15925
33811162
DG		 15926/* Output mapping symbols for linker generated sections,
15927 and for those data-only sections that do not have a
15928 $d. */
4e617b1e
PB		 15929
15930static bfd_boolean
15931elf32_arm_output_arch_local_syms (bfd *output_bfd,
906e58ca 15932 struct bfd_link_info *info,
57402f1e 15933 void *flaginfo,
6e0b88f1
AM		 15934 int (*func) (void *, const char *,
15935 Elf_Internal_Sym *,
15936 asection *,
15937 struct elf_link_hash_entry *))
4e617b1e
PB		 15938{
15939 output_arch_syminfo osi;
15940 struct elf32_arm_link_hash_table *htab;
91a5743d
PB		 15941 bfd_vma offset;
15942 bfd_size_type size;
33811162 15943 bfd *input_bfd;
4e617b1e
PB		 15944
15945 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 15946 if (htab == NULL)
15947 return FALSE;
15948
906e58ca 15949 check_use_blx (htab);
91a5743d 15950
57402f1e 15951 osi.flaginfo = flaginfo;
4e617b1e
PB		 15952 osi.info = info;
15953 osi.func = func;
906e58ca 15954
33811162
DG		 15955 /* Add a $d mapping symbol to data-only sections that
15956 don't have any mapping symbol. This may result in (harmless) redundant
15957 mapping symbols. */
15958 for (input_bfd = info->input_bfds;
15959 input_bfd != NULL;
c72f2fb2 15960 input_bfd = input_bfd->link.next)
33811162
DG		 15961 {
15962 if ((input_bfd->flags & (BFD_LINKER_CREATED | HAS_SYMS)) == HAS_SYMS)
15963 for (osi.sec = input_bfd->sections;
15964 osi.sec != NULL;
15965 osi.sec = osi.sec->next)
15966 {
15967 if (osi.sec->output_section != NULL
f7dd8c79
DJ		 15968 && ((osi.sec->output_section->flags & (SEC_ALLOC | SEC_CODE))
15969 != 0)
33811162
DG		 15970 && (osi.sec->flags & (SEC_HAS_CONTENTS | SEC_LINKER_CREATED))
15971 == SEC_HAS_CONTENTS
15972 && get_arm_elf_section_data (osi.sec) != NULL
501abfe0 15973 && get_arm_elf_section_data (osi.sec)->mapcount == 0
7d500b83
CL		 15974 && osi.sec->size > 0
15975 && (osi.sec->flags & SEC_EXCLUDE) == 0)
33811162
DG		 15976 {
15977 osi.sec_shndx = _bfd_elf_section_from_bfd_section
15978 (output_bfd, osi.sec->output_section);
15979 if (osi.sec_shndx != (int)SHN_BAD)
15980 elf32_arm_output_map_sym (&osi, ARM_MAP_DATA, 0);
15981 }
15982 }
15983 }
15984
91a5743d
PB		 15985 /* ARM->Thumb glue. */
15986 if (htab->arm_glue_size > 0)
15987 {
3d4d4302
AM		 15988 osi.sec = bfd_get_linker_section (htab->bfd_of_glue_owner,
15989 ARM2THUMB_GLUE_SECTION_NAME);
91a5743d
PB		 15990
15991 osi.sec_shndx = _bfd_elf_section_from_bfd_section
15992 (output_bfd, osi.sec->output_section);
0e1862bb 15993 if (bfd_link_pic (info) || htab->root.is_relocatable_executable
91a5743d
PB		 15994 || htab->pic_veneer)
15995 size = ARM2THUMB_PIC_GLUE_SIZE;
15996 else if (htab->use_blx)
15997 size = ARM2THUMB_V5_STATIC_GLUE_SIZE;
15998 else
15999 size = ARM2THUMB_STATIC_GLUE_SIZE;
4e617b1e 16000
91a5743d
PB		 16001 for (offset = 0; offset < htab->arm_glue_size; offset += size)
16002 {
7413f23f
DJ		 16003 elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, offset);
16004 elf32_arm_output_map_sym (&osi, ARM_MAP_DATA, offset + size - 4);
91a5743d
PB		 16005 }
16006 }
16007
16008 /* Thumb->ARM glue. */
16009 if (htab->thumb_glue_size > 0)
16010 {
3d4d4302
AM		 16011 osi.sec = bfd_get_linker_section (htab->bfd_of_glue_owner,
16012 THUMB2ARM_GLUE_SECTION_NAME);
91a5743d
PB		 16013
16014 osi.sec_shndx = _bfd_elf_section_from_bfd_section
16015 (output_bfd, osi.sec->output_section);
16016 size = THUMB2ARM_GLUE_SIZE;
16017
16018 for (offset = 0; offset < htab->thumb_glue_size; offset += size)
16019 {
7413f23f
DJ		 16020 elf32_arm_output_map_sym (&osi, ARM_MAP_THUMB, offset);
16021 elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, offset + 4);
91a5743d
PB		 16022 }
16023 }
16024
845b51d6
PB		 16025 /* ARMv4 BX veneers. */
16026 if (htab->bx_glue_size > 0)
16027 {
3d4d4302
AM		 16028 osi.sec = bfd_get_linker_section (htab->bfd_of_glue_owner,
16029 ARM_BX_GLUE_SECTION_NAME);
845b51d6
PB		 16030
16031 osi.sec_shndx = _bfd_elf_section_from_bfd_section
16032 (output_bfd, osi.sec->output_section);
16033
7413f23f 16034 elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, 0);
845b51d6
PB		 16035 }
16036
8029a119
NC		 16037 /* Long calls stubs. */
16038 if (htab->stub_bfd && htab->stub_bfd->sections)
16039 {
da5938a2 16040 asection* stub_sec;
8029a119 16041
da5938a2
NC		 16042 for (stub_sec = htab->stub_bfd->sections;
16043 stub_sec != NULL;
8029a119
NC		 16044 stub_sec = stub_sec->next)
16045 {
16046 /* Ignore non-stub sections. */
16047 if (!strstr (stub_sec->name, STUB_SUFFIX))
16048 continue;
da5938a2 16049
8029a119 16050 osi.sec = stub_sec;
da5938a2 16051
8029a119
NC		 16052 osi.sec_shndx = _bfd_elf_section_from_bfd_section
16053 (output_bfd, osi.sec->output_section);
da5938a2 16054
8029a119
NC		 16055 bfd_hash_traverse (&htab->stub_hash_table, arm_map_one_stub, &osi);
16056 }
16057 }
da5938a2 16058
91a5743d 16059 /* Finally, output mapping symbols for the PLT. */
34e77a92 16060 if (htab->root.splt && htab->root.splt->size > 0)
4e617b1e 16061 {
34e77a92
RS		 16062 osi.sec = htab->root.splt;
16063 osi.sec_shndx = (_bfd_elf_section_from_bfd_section
16064 (output_bfd, osi.sec->output_section));
16065
16066 /* Output mapping symbols for the plt header. SymbianOS does not have a
16067 plt header. */
16068 if (htab->vxworks_p)
16069 {
16070 /* VxWorks shared libraries have no PLT header. */
0e1862bb 16071 if (!bfd_link_pic (info))
34e77a92
RS		 16072 {
16073 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, 0))
16074 return FALSE;
16075 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_DATA, 12))
16076 return FALSE;
16077 }
16078 }
b38cadfb
NC		 16079 else if (htab->nacl_p)
16080 {
16081 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, 0))
16082 return FALSE;
16083 }
eed94f8f
NC		 16084 else if (using_thumb_only (htab))
16085 {
16086 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_THUMB, 0))
16087 return FALSE;
16088 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_DATA, 12))
16089 return FALSE;
16090 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_THUMB, 16))
16091 return FALSE;
16092 }
34e77a92 16093 else if (!htab->symbian_p)
4e617b1e 16094 {
7413f23f 16095 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, 0))
4e617b1e 16096 return FALSE;
34e77a92
RS		 16097#ifndef FOUR_WORD_PLT
16098 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_DATA, 16))
4e617b1e 16099 return FALSE;
34e77a92 16100#endif
4e617b1e
PB		 16101 }
16102 }
99059e56
RM		 16103 if (htab->nacl_p && htab->root.iplt && htab->root.iplt->size > 0)
16104 {
16105 /* NaCl uses a special first entry in .iplt too. */
16106 osi.sec = htab->root.iplt;
16107 osi.sec_shndx = (_bfd_elf_section_from_bfd_section
16108 (output_bfd, osi.sec->output_section));
16109 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, 0))
16110 return FALSE;
16111 }
34e77a92
RS		 16112 if ((htab->root.splt && htab->root.splt->size > 0)
16113 || (htab->root.iplt && htab->root.iplt->size > 0))
4e617b1e 16114 {
34e77a92
RS		 16115 elf_link_hash_traverse (&htab->root, elf32_arm_output_plt_map, &osi);
16116 for (input_bfd = info->input_bfds;
16117 input_bfd != NULL;
c72f2fb2 16118 input_bfd = input_bfd->link.next)
34e77a92
RS		 16119 {
16120 struct arm_local_iplt_info **local_iplt;
16121 unsigned int i, num_syms;
4e617b1e 16122
34e77a92
RS		 16123 local_iplt = elf32_arm_local_iplt (input_bfd);
16124 if (local_iplt != NULL)
16125 {
16126 num_syms = elf_symtab_hdr (input_bfd).sh_info;
16127 for (i = 0; i < num_syms; i++)
16128 if (local_iplt[i] != NULL
16129 && !elf32_arm_output_plt_map_1 (&osi, TRUE,
16130 &local_iplt[i]->root,
16131 &local_iplt[i]->arm))
16132 return FALSE;
16133 }
16134 }
16135 }
0855e32b
NS		 16136 if (htab->dt_tlsdesc_plt != 0)
16137 {
16138 /* Mapping symbols for the lazy tls trampoline. */
16139 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, htab->dt_tlsdesc_plt))
16140 return FALSE;
b38cadfb 16141
0855e32b
NS		 16142 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_DATA,
16143 htab->dt_tlsdesc_plt + 24))
16144 return FALSE;
16145 }
16146 if (htab->tls_trampoline != 0)
16147 {
16148 /* Mapping symbols for the tls trampoline. */
16149 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, htab->tls_trampoline))
16150 return FALSE;
16151#ifdef FOUR_WORD_PLT
16152 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_DATA,
16153 htab->tls_trampoline + 12))
16154 return FALSE;
b38cadfb 16155#endif
0855e32b 16156 }
b38cadfb 16157
4e617b1e
PB		 16158 return TRUE;
16159}
16160
e489d0ae
PB		 16161/* Allocate target specific section data. */
16162
16163static bfd_boolean
16164elf32_arm_new_section_hook (bfd *abfd, asection *sec)
16165{
f592407e
AM		 16166 if (!sec->used_by_bfd)
16167 {
16168 _arm_elf_section_data *sdata;
16169 bfd_size_type amt = sizeof (*sdata);
e489d0ae 16170
21d799b5 16171 sdata = (_arm_elf_section_data *) bfd_zalloc (abfd, amt);
f592407e
AM		 16172 if (sdata == NULL)
16173 return FALSE;
16174 sec->used_by_bfd = sdata;
16175 }
e489d0ae
PB		 16176
16177 return _bfd_elf_new_section_hook (abfd, sec);
16178}
16179
16180
16181/* Used to order a list of mapping symbols by address. */
16182
16183static int
16184elf32_arm_compare_mapping (const void * a, const void * b)
16185{
7f6a71ff
JM		 16186 const elf32_arm_section_map *amap = (const elf32_arm_section_map *) a;
16187 const elf32_arm_section_map *bmap = (const elf32_arm_section_map *) b;
16188
16189 if (amap->vma > bmap->vma)
16190 return 1;
16191 else if (amap->vma < bmap->vma)
16192 return -1;
16193 else if (amap->type > bmap->type)
16194 /* Ensure results do not depend on the host qsort for objects with
16195 multiple mapping symbols at the same address by sorting on type
16196 after vma. */
16197 return 1;
16198 else if (amap->type < bmap->type)
16199 return -1;
16200 else
16201 return 0;
e489d0ae
PB		 16202}
16203
2468f9c9
PB		 16204/* Add OFFSET to lower 31 bits of ADDR, leaving other bits unmodified. */
16205
16206static unsigned long
16207offset_prel31 (unsigned long addr, bfd_vma offset)
16208{
16209 return (addr & ~0x7ffffffful) | ((addr + offset) & 0x7ffffffful);
16210}
16211
16212/* Copy an .ARM.exidx table entry, adding OFFSET to (applied) PREL31
16213 relocations. */
16214
16215static void
16216copy_exidx_entry (bfd *output_bfd, bfd_byte *to, bfd_byte *from, bfd_vma offset)
16217{
16218 unsigned long first_word = bfd_get_32 (output_bfd, from);
16219 unsigned long second_word = bfd_get_32 (output_bfd, from + 4);
b38cadfb 16220
2468f9c9
PB		 16221 /* High bit of first word is supposed to be zero. */
16222 if ((first_word & 0x80000000ul) == 0)
16223 first_word = offset_prel31 (first_word, offset);
b38cadfb 16224
2468f9c9
PB		 16225 /* If the high bit of the first word is clear, and the bit pattern is not 0x1
16226 (EXIDX_CANTUNWIND), this is an offset to an .ARM.extab entry. */
16227 if ((second_word != 0x1) && ((second_word & 0x80000000ul) == 0))
16228 second_word = offset_prel31 (second_word, offset);
b38cadfb 16229
2468f9c9
PB		 16230 bfd_put_32 (output_bfd, first_word, to);
16231 bfd_put_32 (output_bfd, second_word, to + 4);
16232}
e489d0ae 16233
48229727
JB		 16234/* Data for make_branch_to_a8_stub(). */
16235
b38cadfb
NC		 16236struct a8_branch_to_stub_data
16237{
48229727
JB		 16238 asection *writing_section;
16239 bfd_byte *contents;
16240};
16241
16242
16243/* Helper to insert branches to Cortex-A8 erratum stubs in the right
16244 places for a particular section. */
16245
16246static bfd_boolean
16247make_branch_to_a8_stub (struct bfd_hash_entry *gen_entry,
99059e56 16248 void *in_arg)
48229727
JB		 16249{
16250 struct elf32_arm_stub_hash_entry *stub_entry;
16251 struct a8_branch_to_stub_data *data;
16252 bfd_byte *contents;
16253 unsigned long branch_insn;
16254 bfd_vma veneered_insn_loc, veneer_entry_loc;
16255 bfd_signed_vma branch_offset;
16256 bfd *abfd;
8d9d9490 16257 unsigned int loc;
48229727
JB		 16258
16259 stub_entry = (struct elf32_arm_stub_hash_entry *) gen_entry;
16260 data = (struct a8_branch_to_stub_data *) in_arg;
16261
16262 if (stub_entry->target_section != data->writing_section
4563a860 16263 || stub_entry->stub_type < arm_stub_a8_veneer_lwm)
48229727
JB		 16264 return TRUE;
16265
16266 contents = data->contents;
16267
8d9d9490
TP		 16268 /* We use target_section as Cortex-A8 erratum workaround stubs are only
16269 generated when both source and target are in the same section. */
48229727
JB		 16270 veneered_insn_loc = stub_entry->target_section->output_section->vma
16271 + stub_entry->target_section->output_offset
8d9d9490 16272 + stub_entry->source_value;
48229727
JB		 16273
16274 veneer_entry_loc = stub_entry->stub_sec->output_section->vma
16275 + stub_entry->stub_sec->output_offset
16276 + stub_entry->stub_offset;
16277
16278 if (stub_entry->stub_type == arm_stub_a8_veneer_blx)
16279 veneered_insn_loc &= ~3u;
16280
16281 branch_offset = veneer_entry_loc - veneered_insn_loc - 4;
16282
16283 abfd = stub_entry->target_section->owner;
8d9d9490 16284 loc = stub_entry->source_value;
48229727
JB		 16285
16286 /* We attempt to avoid this condition by setting stubs_always_after_branch
16287 in elf32_arm_size_stubs if we've enabled the Cortex-A8 erratum workaround.
16288 This check is just to be on the safe side... */
16289 if ((veneered_insn_loc & ~0xfff) == (veneer_entry_loc & ~0xfff))
16290 {
16291 (*_bfd_error_handler) (_("%B: error: Cortex-A8 erratum stub is "
16292 "allocated in unsafe location"), abfd);
16293 return FALSE;
16294 }
16295
16296 switch (stub_entry->stub_type)
16297 {
16298 case arm_stub_a8_veneer_b:
16299 case arm_stub_a8_veneer_b_cond:
16300 branch_insn = 0xf0009000;
16301 goto jump24;
16302
16303 case arm_stub_a8_veneer_blx:
16304 branch_insn = 0xf000e800;
16305 goto jump24;
16306
16307 case arm_stub_a8_veneer_bl:
16308 {
16309 unsigned int i1, j1, i2, j2, s;
16310
16311 branch_insn = 0xf000d000;
16312
16313 jump24:
16314 if (branch_offset < -16777216 || branch_offset > 16777214)
16315 {
16316 /* There's not much we can do apart from complain if this
16317 happens. */
16318 (*_bfd_error_handler) (_("%B: error: Cortex-A8 erratum stub out "
16319 "of range (input file too large)"), abfd);
16320 return FALSE;
16321 }
16322
16323 /* i1 = not(j1 eor s), so:
16324 not i1 = j1 eor s
16325 j1 = (not i1) eor s. */
16326
16327 branch_insn |= (branch_offset >> 1) & 0x7ff;
16328 branch_insn |= ((branch_offset >> 12) & 0x3ff) << 16;
16329 i2 = (branch_offset >> 22) & 1;
16330 i1 = (branch_offset >> 23) & 1;
16331 s = (branch_offset >> 24) & 1;
16332 j1 = (!i1) ^ s;
16333 j2 = (!i2) ^ s;
16334 branch_insn |= j2 << 11;
16335 branch_insn |= j1 << 13;
16336 branch_insn |= s << 26;
16337 }
16338 break;
16339
16340 default:
16341 BFD_FAIL ();
16342 return FALSE;
16343 }
16344
8d9d9490
TP		 16345 bfd_put_16 (abfd, (branch_insn >> 16) & 0xffff, &contents[loc]);
16346 bfd_put_16 (abfd, branch_insn & 0xffff, &contents[loc + 2]);
48229727
JB		 16347
16348 return TRUE;
16349}
16350
a504d23a
LA		 16351/* Beginning of stm32l4xx work-around. */
16352
16353/* Functions encoding instructions necessary for the emission of the
16354 fix-stm32l4xx-629360.
16355 Encoding is extracted from the
16356 ARM (C) Architecture Reference Manual
16357 ARMv7-A and ARMv7-R edition
16358 ARM DDI 0406C.b (ID072512). */
16359
16360static inline bfd_vma
82188b29 16361create_instruction_branch_absolute (int branch_offset)
a504d23a
LA		 16362{
16363 /* A8.8.18 B (A8-334)
16364 B target_address (Encoding T4). */
16365 /* 1111 - 0Sii - iiii - iiii - 10J1 - Jiii - iiii - iiii. */
16366 /* jump offset is: S:I1:I2:imm10:imm11:0. */
16367 /* with : I1 = NOT (J1 EOR S) I2 = NOT (J2 EOR S). */
16368
a504d23a
LA		 16369 int s = ((branch_offset & 0x1000000) >> 24);
16370 int j1 = s ^ !((branch_offset & 0x800000) >> 23);
16371 int j2 = s ^ !((branch_offset & 0x400000) >> 22);
16372
16373 if (branch_offset < -(1 << 24) || branch_offset >= (1 << 24))
16374 BFD_ASSERT (0 && "Error: branch out of range. Cannot create branch.");
16375
16376 bfd_vma patched_inst = 0xf0009000
16377 | s << 26 /* S. */
16378 | (((unsigned long) (branch_offset) >> 12) & 0x3ff) << 16 /* imm10. */
16379 | j1 << 13 /* J1. */
16380 | j2 << 11 /* J2. */
16381 | (((unsigned long) (branch_offset) >> 1) & 0x7ff); /* imm11. */
16382
16383 return patched_inst;
16384}
16385
16386static inline bfd_vma
16387create_instruction_ldmia (int base_reg, int wback, int reg_mask)
16388{
16389 /* A8.8.57 LDM/LDMIA/LDMFD (A8-396)
16390 LDMIA Rn!, {Ra, Rb, Rc, ...} (Encoding T2). */
16391 bfd_vma patched_inst = 0xe8900000
16392 | (/*W=*/wback << 21)
16393 | (base_reg << 16)
16394 | (reg_mask & 0x0000ffff);
16395
16396 return patched_inst;
16397}
16398
16399static inline bfd_vma
16400create_instruction_ldmdb (int base_reg, int wback, int reg_mask)
16401{
16402 /* A8.8.60 LDMDB/LDMEA (A8-402)
16403 LDMDB Rn!, {Ra, Rb, Rc, ...} (Encoding T1). */
16404 bfd_vma patched_inst = 0xe9100000
16405 | (/*W=*/wback << 21)
16406 | (base_reg << 16)
16407 | (reg_mask & 0x0000ffff);
16408
16409 return patched_inst;
16410}
16411
16412static inline bfd_vma
16413create_instruction_mov (int target_reg, int source_reg)
16414{
16415 /* A8.8.103 MOV (register) (A8-486)
16416 MOV Rd, Rm (Encoding T1). */
16417 bfd_vma patched_inst = 0x4600
16418 | (target_reg & 0x7)
16419 | ((target_reg & 0x8) >> 3) << 7
16420 | (source_reg << 3);
16421
16422 return patched_inst;
16423}
16424
16425static inline bfd_vma
16426create_instruction_sub (int target_reg, int source_reg, int value)
16427{
16428 /* A8.8.221 SUB (immediate) (A8-708)
16429 SUB Rd, Rn, #value (Encoding T3). */
16430 bfd_vma patched_inst = 0xf1a00000
16431 | (target_reg << 8)
16432 | (source_reg << 16)
16433 | (/*S=*/0 << 20)
16434 | ((value & 0x800) >> 11) << 26
16435 | ((value & 0x700) >> 8) << 12
16436 | (value & 0x0ff);
16437
16438 return patched_inst;
16439}
16440
16441static inline bfd_vma
9239bbd3 16442create_instruction_vldmia (int base_reg, int is_dp, int wback, int num_words,
a504d23a
LA		 16443 int first_reg)
16444{
16445 /* A8.8.332 VLDM (A8-922)
9239bbd3
CM		 16446 VLMD{MODE} Rn{!}, {list} (Encoding T1 or T2). */
16447 bfd_vma patched_inst = (is_dp ? 0xec900b00 : 0xec900a00)
a504d23a
LA		 16448 | (/*W=*/wback << 21)
16449 | (base_reg << 16)
9239bbd3
CM		 16450 | (num_words & 0x000000ff)
16451 | (((unsigned)first_reg >> 1) & 0x0000000f) << 12
a504d23a
LA		 16452 | (first_reg & 0x00000001) << 22;
16453
16454 return patched_inst;
16455}
16456
16457static inline bfd_vma
9239bbd3
CM		 16458create_instruction_vldmdb (int base_reg, int is_dp, int num_words,
16459 int first_reg)
a504d23a
LA		 16460{
16461 /* A8.8.332 VLDM (A8-922)
9239bbd3
CM		 16462 VLMD{MODE} Rn!, {} (Encoding T1 or T2). */
16463 bfd_vma patched_inst = (is_dp ? 0xed300b00 : 0xed300a00)
a504d23a 16464 | (base_reg << 16)
9239bbd3
CM		 16465 | (num_words & 0x000000ff)
16466 | (((unsigned)first_reg >>1 ) & 0x0000000f) << 12
a504d23a
LA		 16467 | (first_reg & 0x00000001) << 22;
16468
16469 return patched_inst;
16470}
16471
16472static inline bfd_vma
16473create_instruction_udf_w (int value)
16474{
16475 /* A8.8.247 UDF (A8-758)
16476 Undefined (Encoding T2). */
16477 bfd_vma patched_inst = 0xf7f0a000
16478 | (value & 0x00000fff)
16479 | (value & 0x000f0000) << 16;
16480
16481 return patched_inst;
16482}
16483
16484static inline bfd_vma
16485create_instruction_udf (int value)
16486{
16487 /* A8.8.247 UDF (A8-758)
16488 Undefined (Encoding T1). */
16489 bfd_vma patched_inst = 0xde00
16490 | (value & 0xff);
16491
16492 return patched_inst;
16493}
16494
16495/* Functions writing an instruction in memory, returning the next
16496 memory position to write to. */
16497
16498static inline bfd_byte *
16499push_thumb2_insn32 (struct elf32_arm_link_hash_table * htab,
16500 bfd * output_bfd, bfd_byte *pt, insn32 insn)
16501{
16502 put_thumb2_insn (htab, output_bfd, insn, pt);
16503 return pt + 4;
16504}
16505
16506static inline bfd_byte *
16507push_thumb2_insn16 (struct elf32_arm_link_hash_table * htab,
16508 bfd * output_bfd, bfd_byte *pt, insn32 insn)
16509{
16510 put_thumb_insn (htab, output_bfd, insn, pt);
16511 return pt + 2;
16512}
16513
16514/* Function filling up a region in memory with T1 and T2 UDFs taking
16515 care of alignment. */
16516
16517static bfd_byte *
16518stm32l4xx_fill_stub_udf (struct elf32_arm_link_hash_table * htab,
16519 bfd * output_bfd,
16520 const bfd_byte * const base_stub_contents,
16521 bfd_byte * const from_stub_contents,
16522 const bfd_byte * const end_stub_contents)
16523{
16524 bfd_byte *current_stub_contents = from_stub_contents;
16525
16526 /* Fill the remaining of the stub with deterministic contents : UDF
16527 instructions.
16528 Check if realignment is needed on modulo 4 frontier using T1, to
16529 further use T2. */
16530 if ((current_stub_contents < end_stub_contents)
16531 && !((current_stub_contents - base_stub_contents) % 2)
16532 && ((current_stub_contents - base_stub_contents) % 4))
16533 current_stub_contents =
16534 push_thumb2_insn16 (htab, output_bfd, current_stub_contents,
16535 create_instruction_udf (0));
16536
16537 for (; current_stub_contents < end_stub_contents;)
16538 current_stub_contents =
16539 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
16540 create_instruction_udf_w (0));
16541
16542 return current_stub_contents;
16543}
16544
16545/* Functions writing the stream of instructions equivalent to the
16546 derived sequence for ldmia, ldmdb, vldm respectively. */
16547
16548static void
16549stm32l4xx_create_replacing_stub_ldmia (struct elf32_arm_link_hash_table * htab,
16550 bfd * output_bfd,
16551 const insn32 initial_insn,
16552 const bfd_byte *const initial_insn_addr,
16553 bfd_byte *const base_stub_contents)
16554{
16555 int wback = (initial_insn & 0x00200000) >> 21;
16556 int ri, rn = (initial_insn & 0x000F0000) >> 16;
16557 int insn_all_registers = initial_insn & 0x0000ffff;
16558 int insn_low_registers, insn_high_registers;
16559 int usable_register_mask;
16560 int nb_registers = popcount (insn_all_registers);
16561 int restore_pc = (insn_all_registers & (1 << 15)) ? 1 : 0;
16562 int restore_rn = (insn_all_registers & (1 << rn)) ? 1 : 0;
16563 bfd_byte *current_stub_contents = base_stub_contents;
16564
16565 BFD_ASSERT (is_thumb2_ldmia (initial_insn));
16566
16567 /* In BFD_ARM_STM32L4XX_FIX_ALL mode we may have to deal with
16568 smaller than 8 registers load sequences that do not cause the
16569 hardware issue. */
16570 if (nb_registers <= 8)
16571 {
16572 /* UNTOUCHED : LDMIA Rn{!}, {R-all-register-list}. */
16573 current_stub_contents =
16574 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
16575 initial_insn);
16576
16577 /* B initial_insn_addr+4. */
16578 if (!restore_pc)
16579 current_stub_contents =
16580 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
16581 create_instruction_branch_absolute
82188b29
NC		 16582 (initial_insn_addr - current_stub_contents));
16583
a504d23a
LA		 16584
16585 /* Fill the remaining of the stub with deterministic contents. */
16586 current_stub_contents =
16587 stm32l4xx_fill_stub_udf (htab, output_bfd,
16588 base_stub_contents, current_stub_contents,
16589 base_stub_contents +
16590 STM32L4XX_ERRATUM_LDM_VENEER_SIZE);
16591
16592 return;
16593 }
16594
16595 /* - reg_list[13] == 0. */
16596 BFD_ASSERT ((insn_all_registers & (1 << 13))==0);
16597
16598 /* - reg_list[14] & reg_list[15] != 1. */
16599 BFD_ASSERT ((insn_all_registers & 0xC000) != 0xC000);
16600
16601 /* - if (wback==1) reg_list[rn] == 0. */
16602 BFD_ASSERT (!wback || !restore_rn);
16603
16604 /* - nb_registers > 8. */
16605 BFD_ASSERT (popcount (insn_all_registers) > 8);
16606
16607 /* At this point, LDMxx initial insn loads between 9 and 14 registers. */
16608
16609 /* In the following algorithm, we split this wide LDM using 2 LDM insns:
16610 - One with the 7 lowest registers (register mask 0x007F)
16611 This LDM will finally contain between 2 and 7 registers
16612 - One with the 7 highest registers (register mask 0xDF80)
16613 This ldm will finally contain between 2 and 7 registers. */
16614 insn_low_registers = insn_all_registers & 0x007F;
16615 insn_high_registers = insn_all_registers & 0xDF80;
16616
16617 /* A spare register may be needed during this veneer to temporarily
16618 handle the base register. This register will be restored with the
16619 last LDM operation.
16620 The usable register may be any general purpose register (that
16621 excludes PC, SP, LR : register mask is 0x1FFF). */
16622 usable_register_mask = 0x1FFF;
16623
16624 /* Generate the stub function. */
16625 if (wback)
16626 {
16627 /* LDMIA Rn!, {R-low-register-list} : (Encoding T2). */
16628 current_stub_contents =
16629 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
16630 create_instruction_ldmia
16631 (rn, /*wback=*/1, insn_low_registers));
16632
16633 /* LDMIA Rn!, {R-high-register-list} : (Encoding T2). */
16634 current_stub_contents =
16635 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
16636 create_instruction_ldmia
16637 (rn, /*wback=*/1, insn_high_registers));
16638 if (!restore_pc)
16639 {
16640 /* B initial_insn_addr+4. */
16641 current_stub_contents =
16642 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
16643 create_instruction_branch_absolute
82188b29 16644 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 16645 }
16646 }
16647 else /* if (!wback). */
16648 {
16649 ri = rn;
16650
16651 /* If Rn is not part of the high-register-list, move it there. */
16652 if (!(insn_high_registers & (1 << rn)))
16653 {
16654 /* Choose a Ri in the high-register-list that will be restored. */
16655 ri = ctz (insn_high_registers & usable_register_mask & ~(1 << rn));
16656
16657 /* MOV Ri, Rn. */
16658 current_stub_contents =
16659 push_thumb2_insn16 (htab, output_bfd, current_stub_contents,
16660 create_instruction_mov (ri, rn));
16661 }
16662
16663 /* LDMIA Ri!, {R-low-register-list} : (Encoding T2). */
16664 current_stub_contents =
16665 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
16666 create_instruction_ldmia
16667 (ri, /*wback=*/1, insn_low_registers));
16668
16669 /* LDMIA Ri, {R-high-register-list} : (Encoding T2). */
16670 current_stub_contents =
16671 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
16672 create_instruction_ldmia
16673 (ri, /*wback=*/0, insn_high_registers));
16674
16675 if (!restore_pc)
16676 {
16677 /* B initial_insn_addr+4. */
16678 current_stub_contents =
16679 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
16680 create_instruction_branch_absolute
82188b29 16681 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 16682 }
16683 }
16684
16685 /* Fill the remaining of the stub with deterministic contents. */
16686 current_stub_contents =
16687 stm32l4xx_fill_stub_udf (htab, output_bfd,
16688 base_stub_contents, current_stub_contents,
16689 base_stub_contents +
16690 STM32L4XX_ERRATUM_LDM_VENEER_SIZE);
16691}
16692
16693static void
16694stm32l4xx_create_replacing_stub_ldmdb (struct elf32_arm_link_hash_table * htab,
16695 bfd * output_bfd,
16696 const insn32 initial_insn,
16697 const bfd_byte *const initial_insn_addr,
16698 bfd_byte *const base_stub_contents)
16699{
16700 int wback = (initial_insn & 0x00200000) >> 21;
16701 int ri, rn = (initial_insn & 0x000f0000) >> 16;
16702 int insn_all_registers = initial_insn & 0x0000ffff;
16703 int insn_low_registers, insn_high_registers;
16704 int usable_register_mask;
16705 int restore_pc = (insn_all_registers & (1 << 15)) ? 1 : 0;
16706 int restore_rn = (insn_all_registers & (1 << rn)) ? 1 : 0;
16707 int nb_registers = popcount (insn_all_registers);
16708 bfd_byte *current_stub_contents = base_stub_contents;
16709
16710 BFD_ASSERT (is_thumb2_ldmdb (initial_insn));
16711
16712 /* In BFD_ARM_STM32L4XX_FIX_ALL mode we may have to deal with
16713 smaller than 8 registers load sequences that do not cause the
16714 hardware issue. */
16715 if (nb_registers <= 8)
16716 {
16717 /* UNTOUCHED : LDMIA Rn{!}, {R-all-register-list}. */
16718 current_stub_contents =
16719 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
16720 initial_insn);
16721
16722 /* B initial_insn_addr+4. */
16723 current_stub_contents =
16724 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
16725 create_instruction_branch_absolute
82188b29 16726 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 16727
16728 /* Fill the remaining of the stub with deterministic contents. */
16729 current_stub_contents =
16730 stm32l4xx_fill_stub_udf (htab, output_bfd,
16731 base_stub_contents, current_stub_contents,
16732 base_stub_contents +
16733 STM32L4XX_ERRATUM_LDM_VENEER_SIZE);
16734
16735 return;
16736 }
16737
16738 /* - reg_list[13] == 0. */
16739 BFD_ASSERT ((insn_all_registers & (1 << 13)) == 0);
16740
16741 /* - reg_list[14] & reg_list[15] != 1. */
16742 BFD_ASSERT ((insn_all_registers & 0xC000) != 0xC000);
16743
16744 /* - if (wback==1) reg_list[rn] == 0. */
16745 BFD_ASSERT (!wback || !restore_rn);
16746
16747 /* - nb_registers > 8. */
16748 BFD_ASSERT (popcount (insn_all_registers) > 8);
16749
16750 /* At this point, LDMxx initial insn loads between 9 and 14 registers. */
16751
16752 /* In the following algorithm, we split this wide LDM using 2 LDM insn:
16753 - One with the 7 lowest registers (register mask 0x007F)
16754 This LDM will finally contain between 2 and 7 registers
16755 - One with the 7 highest registers (register mask 0xDF80)
16756 This ldm will finally contain between 2 and 7 registers. */
16757 insn_low_registers = insn_all_registers & 0x007F;
16758 insn_high_registers = insn_all_registers & 0xDF80;
16759
16760 /* A spare register may be needed during this veneer to temporarily
16761 handle the base register. This register will be restored with
16762 the last LDM operation.
16763 The usable register may be any general purpose register (that excludes
16764 PC, SP, LR : register mask is 0x1FFF). */
16765 usable_register_mask = 0x1FFF;
16766
16767 /* Generate the stub function. */
16768 if (!wback && !restore_pc && !restore_rn)
16769 {
16770 /* Choose a Ri in the low-register-list that will be restored. */
16771 ri = ctz (insn_low_registers & usable_register_mask & ~(1 << rn));
16772
16773 /* MOV Ri, Rn. */
16774 current_stub_contents =
16775 push_thumb2_insn16 (htab, output_bfd, current_stub_contents,
16776 create_instruction_mov (ri, rn));
16777
16778 /* LDMDB Ri!, {R-high-register-list}. */
16779 current_stub_contents =
16780 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
16781 create_instruction_ldmdb
16782 (ri, /*wback=*/1, insn_high_registers));
16783
16784 /* LDMDB Ri, {R-low-register-list}. */
16785 current_stub_contents =
16786 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
16787 create_instruction_ldmdb
16788 (ri, /*wback=*/0, insn_low_registers));
16789
16790 /* B initial_insn_addr+4. */
16791 current_stub_contents =
16792 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
16793 create_instruction_branch_absolute
82188b29 16794 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 16795 }
16796 else if (wback && !restore_pc && !restore_rn)
16797 {
16798 /* LDMDB Rn!, {R-high-register-list}. */
16799 current_stub_contents =
16800 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
16801 create_instruction_ldmdb
16802 (rn, /*wback=*/1, insn_high_registers));
16803
16804 /* LDMDB Rn!, {R-low-register-list}. */
16805 current_stub_contents =
16806 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
16807 create_instruction_ldmdb
16808 (rn, /*wback=*/1, insn_low_registers));
16809
16810 /* B initial_insn_addr+4. */
16811 current_stub_contents =
16812 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
16813 create_instruction_branch_absolute
82188b29 16814 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 16815 }
16816 else if (!wback && restore_pc && !restore_rn)
16817 {
16818 /* Choose a Ri in the high-register-list that will be restored. */
16819 ri = ctz (insn_high_registers & usable_register_mask & ~(1 << rn));
16820
16821 /* SUB Ri, Rn, #(4*nb_registers). */
16822 current_stub_contents =
16823 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
16824 create_instruction_sub (ri, rn, (4 * nb_registers)));
16825
16826 /* LDMIA Ri!, {R-low-register-list}. */
16827 current_stub_contents =
16828 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
16829 create_instruction_ldmia
16830 (ri, /*wback=*/1, insn_low_registers));
16831
16832 /* LDMIA Ri, {R-high-register-list}. */
16833 current_stub_contents =
16834 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
16835 create_instruction_ldmia
16836 (ri, /*wback=*/0, insn_high_registers));
16837 }
16838 else if (wback && restore_pc && !restore_rn)
16839 {
16840 /* Choose a Ri in the high-register-list that will be restored. */
16841 ri = ctz (insn_high_registers & usable_register_mask & ~(1 << rn));
16842
16843 /* SUB Rn, Rn, #(4*nb_registers) */
16844 current_stub_contents =
16845 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
16846 create_instruction_sub (rn, rn, (4 * nb_registers)));
16847
16848 /* MOV Ri, Rn. */
16849 current_stub_contents =
16850 push_thumb2_insn16 (htab, output_bfd, current_stub_contents,
16851 create_instruction_mov (ri, rn));
16852
16853 /* LDMIA Ri!, {R-low-register-list}. */
16854 current_stub_contents =
16855 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
16856 create_instruction_ldmia
16857 (ri, /*wback=*/1, insn_low_registers));
16858
16859 /* LDMIA Ri, {R-high-register-list}. */
16860 current_stub_contents =
16861 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
16862 create_instruction_ldmia
16863 (ri, /*wback=*/0, insn_high_registers));
16864 }
16865 else if (!wback && !restore_pc && restore_rn)
16866 {
16867 ri = rn;
16868 if (!(insn_low_registers & (1 << rn)))
16869 {
16870 /* Choose a Ri in the low-register-list that will be restored. */
16871 ri = ctz (insn_low_registers & usable_register_mask & ~(1 << rn));
16872
16873 /* MOV Ri, Rn. */
16874 current_stub_contents =
16875 push_thumb2_insn16 (htab, output_bfd, current_stub_contents,
16876 create_instruction_mov (ri, rn));
16877 }
16878
16879 /* LDMDB Ri!, {R-high-register-list}. */
16880 current_stub_contents =
16881 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
16882 create_instruction_ldmdb
16883 (ri, /*wback=*/1, insn_high_registers));
16884
16885 /* LDMDB Ri, {R-low-register-list}. */
16886 current_stub_contents =
16887 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
16888 create_instruction_ldmdb
16889 (ri, /*wback=*/0, insn_low_registers));
16890
16891 /* B initial_insn_addr+4. */
16892 current_stub_contents =
16893 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
16894 create_instruction_branch_absolute
82188b29 16895 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 16896 }
16897 else if (!wback && restore_pc && restore_rn)
16898 {
16899 ri = rn;
16900 if (!(insn_high_registers & (1 << rn)))
16901 {
16902 /* Choose a Ri in the high-register-list that will be restored. */
16903 ri = ctz (insn_high_registers & usable_register_mask & ~(1 << rn));
16904 }
16905
16906 /* SUB Ri, Rn, #(4*nb_registers). */
16907 current_stub_contents =
16908 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
16909 create_instruction_sub (ri, rn, (4 * nb_registers)));
16910
16911 /* LDMIA Ri!, {R-low-register-list}. */
16912 current_stub_contents =
16913 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
16914 create_instruction_ldmia
16915 (ri, /*wback=*/1, insn_low_registers));
16916
16917 /* LDMIA Ri, {R-high-register-list}. */
16918 current_stub_contents =
16919 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
16920 create_instruction_ldmia
16921 (ri, /*wback=*/0, insn_high_registers));
16922 }
16923 else if (wback && restore_rn)
16924 {
16925 /* The assembler should not have accepted to encode this. */
16926 BFD_ASSERT (0 && "Cannot patch an instruction that has an "
16927 "undefined behavior.\n");
16928 }
16929
16930 /* Fill the remaining of the stub with deterministic contents. */
16931 current_stub_contents =
16932 stm32l4xx_fill_stub_udf (htab, output_bfd,
16933 base_stub_contents, current_stub_contents,
16934 base_stub_contents +
16935 STM32L4XX_ERRATUM_LDM_VENEER_SIZE);
16936
16937}
16938
16939static void
16940stm32l4xx_create_replacing_stub_vldm (struct elf32_arm_link_hash_table * htab,
16941 bfd * output_bfd,
16942 const insn32 initial_insn,
16943 const bfd_byte *const initial_insn_addr,
16944 bfd_byte *const base_stub_contents)
16945{
9239bbd3 16946 int num_words = ((unsigned int) initial_insn << 24) >> 24;
a504d23a
LA		 16947 bfd_byte *current_stub_contents = base_stub_contents;
16948
16949 BFD_ASSERT (is_thumb2_vldm (initial_insn));
16950
16951 /* In BFD_ARM_STM32L4XX_FIX_ALL mode we may have to deal with
9239bbd3 16952 smaller than 8 words load sequences that do not cause the
a504d23a 16953 hardware issue. */
9239bbd3 16954 if (num_words <= 8)
a504d23a
LA		 16955 {
16956 /* Untouched instruction. */
16957 current_stub_contents =
16958 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
16959 initial_insn);
16960
16961 /* B initial_insn_addr+4. */
16962 current_stub_contents =
16963 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
16964 create_instruction_branch_absolute
82188b29 16965 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 16966 }
16967 else
16968 {
9239bbd3
CM		 16969 bfd_boolean is_dp = /* DP encoding. */
16970 (initial_insn & 0xfe100f00) == 0xec100b00;
a504d23a
LA		 16971 bfd_boolean is_ia_nobang = /* (IA without !). */
16972 (((initial_insn << 7) >> 28) & 0xd) == 0x4;
16973 bfd_boolean is_ia_bang = /* (IA with !) - includes VPOP. */
16974 (((initial_insn << 7) >> 28) & 0xd) == 0x5;
16975 bfd_boolean is_db_bang = /* (DB with !). */
16976 (((initial_insn << 7) >> 28) & 0xd) == 0x9;
9239bbd3 16977 int base_reg = ((unsigned int) initial_insn << 12) >> 28;
a504d23a 16978 /* d = UInt (Vd:D);. */
9239bbd3 16979 int first_reg = ((((unsigned int) initial_insn << 16) >> 28) << 1)
a504d23a
LA		 16980 | (((unsigned int)initial_insn << 9) >> 31);
16981
9239bbd3
CM		 16982 /* Compute the number of 8-words chunks needed to split. */
16983 int chunks = (num_words % 8) ? (num_words / 8 + 1) : (num_words / 8);
a504d23a
LA		 16984 int chunk;
16985
16986 /* The test coverage has been done assuming the following
16987 hypothesis that exactly one of the previous is_ predicates is
16988 true. */
9239bbd3
CM		 16989 BFD_ASSERT ( (is_ia_nobang ^ is_ia_bang ^ is_db_bang)
16990 && !(is_ia_nobang & is_ia_bang & is_db_bang));
a504d23a 16991
9239bbd3 16992 /* We treat the cutting of the words in one pass for all
a504d23a
LA		 16993 cases, then we emit the adjustments:
16994
16995 vldm rx, {...}
16996 -> vldm rx!, {8_words_or_less} for each needed 8_word
16997 -> sub rx, rx, #size (list)
16998
16999 vldm rx!, {...}
17000 -> vldm rx!, {8_words_or_less} for each needed 8_word
17001 This also handles vpop instruction (when rx is sp)
17002
17003 vldmd rx!, {...}
17004 -> vldmb rx!, {8_words_or_less} for each needed 8_word. */
9239bbd3 17005 for (chunk = 0; chunk < chunks; ++chunk)
a504d23a 17006 {
9239bbd3
CM		 17007 bfd_vma new_insn = 0;
17008
a504d23a
LA		 17009 if (is_ia_nobang || is_ia_bang)
17010 {
9239bbd3
CM		 17011 new_insn = create_instruction_vldmia
17012 (base_reg,
17013 is_dp,
17014 /*wback= . */1,
17015 chunks - (chunk + 1) ?
17016 8 : num_words - chunk * 8,
17017 first_reg + chunk * 8);
a504d23a
LA		 17018 }
17019 else if (is_db_bang)
17020 {
9239bbd3
CM		 17021 new_insn = create_instruction_vldmdb
17022 (base_reg,
17023 is_dp,
17024 chunks - (chunk + 1) ?
17025 8 : num_words - chunk * 8,
17026 first_reg + chunk * 8);
a504d23a 17027 }
9239bbd3
CM		 17028
17029 if (new_insn)
17030 current_stub_contents =
17031 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
17032 new_insn);
a504d23a
LA		 17033 }
17034
17035 /* Only this case requires the base register compensation
17036 subtract. */
17037 if (is_ia_nobang)
17038 {
17039 current_stub_contents =
17040 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
17041 create_instruction_sub
9239bbd3 17042 (base_reg, base_reg, 4*num_words));
a504d23a
LA		 17043 }
17044
17045 /* B initial_insn_addr+4. */
17046 current_stub_contents =
17047 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
17048 create_instruction_branch_absolute
82188b29 17049 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 17050 }
17051
17052 /* Fill the remaining of the stub with deterministic contents. */
17053 current_stub_contents =
17054 stm32l4xx_fill_stub_udf (htab, output_bfd,
17055 base_stub_contents, current_stub_contents,
17056 base_stub_contents +
17057 STM32L4XX_ERRATUM_VLDM_VENEER_SIZE);
17058}
17059
17060static void
17061stm32l4xx_create_replacing_stub (struct elf32_arm_link_hash_table * htab,
17062 bfd * output_bfd,
17063 const insn32 wrong_insn,
17064 const bfd_byte *const wrong_insn_addr,
17065 bfd_byte *const stub_contents)
17066{
17067 if (is_thumb2_ldmia (wrong_insn))
17068 stm32l4xx_create_replacing_stub_ldmia (htab, output_bfd,
17069 wrong_insn, wrong_insn_addr,
17070 stub_contents);
17071 else if (is_thumb2_ldmdb (wrong_insn))
17072 stm32l4xx_create_replacing_stub_ldmdb (htab, output_bfd,
17073 wrong_insn, wrong_insn_addr,
17074 stub_contents);
17075 else if (is_thumb2_vldm (wrong_insn))
17076 stm32l4xx_create_replacing_stub_vldm (htab, output_bfd,
17077 wrong_insn, wrong_insn_addr,
17078 stub_contents);
17079}
17080
17081/* End of stm32l4xx work-around. */
17082
17083
491d01d3
YU		 17084static void
17085elf32_arm_add_relocation (bfd *output_bfd, struct bfd_link_info *info,
17086 asection *output_sec, Elf_Internal_Rela *rel)
17087{
17088 BFD_ASSERT (output_sec && rel);
17089 struct bfd_elf_section_reloc_data *output_reldata;
17090 struct elf32_arm_link_hash_table *htab;
17091 struct bfd_elf_section_data *oesd = elf_section_data (output_sec);
17092 Elf_Internal_Shdr *rel_hdr;
17093
17094
17095 if (oesd->rel.hdr)
17096 {
17097 rel_hdr = oesd->rel.hdr;
17098 output_reldata = &(oesd->rel);
17099 }
17100 else if (oesd->rela.hdr)
17101 {
17102 rel_hdr = oesd->rela.hdr;
17103 output_reldata = &(oesd->rela);
17104 }
17105 else
17106 {
17107 abort ();
17108 }
17109
17110 bfd_byte *erel = rel_hdr->contents;
17111 erel += output_reldata->count * rel_hdr->sh_entsize;
17112 htab = elf32_arm_hash_table (info);
17113 SWAP_RELOC_OUT (htab) (output_bfd, rel, erel);
17114 output_reldata->count++;
17115}
17116
e489d0ae
PB		 17117/* Do code byteswapping. Return FALSE afterwards so that the section is
17118 written out as normal. */
17119
17120static bfd_boolean
c7b8f16e 17121elf32_arm_write_section (bfd *output_bfd,
8029a119
NC		 17122 struct bfd_link_info *link_info,
17123 asection *sec,
e489d0ae
PB		 17124 bfd_byte *contents)
17125{
48229727 17126 unsigned int mapcount, errcount;
8e3de13a 17127 _arm_elf_section_data *arm_data;
c7b8f16e 17128 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (link_info);
e489d0ae 17129 elf32_arm_section_map *map;
c7b8f16e 17130 elf32_vfp11_erratum_list *errnode;
a504d23a 17131 elf32_stm32l4xx_erratum_list *stm32l4xx_errnode;
e489d0ae
PB		 17132 bfd_vma ptr;
17133 bfd_vma end;
c7b8f16e 17134 bfd_vma offset = sec->output_section->vma + sec->output_offset;
e489d0ae 17135 bfd_byte tmp;
48229727 17136 unsigned int i;
57e8b36a 17137
4dfe6ac6
NC		 17138 if (globals == NULL)
17139 return FALSE;
17140
8e3de13a
NC		 17141 /* If this section has not been allocated an _arm_elf_section_data
17142 structure then we cannot record anything. */
17143 arm_data = get_arm_elf_section_data (sec);
17144 if (arm_data == NULL)
17145 return FALSE;
17146
17147 mapcount = arm_data->mapcount;
17148 map = arm_data->map;
c7b8f16e
JB		 17149 errcount = arm_data->erratumcount;
17150
17151 if (errcount != 0)
17152 {
17153 unsigned int endianflip = bfd_big_endian (output_bfd) ? 3 : 0;
17154
17155 for (errnode = arm_data->erratumlist; errnode != 0;
99059e56
RM		 17156 errnode = errnode->next)
17157 {
17158 bfd_vma target = errnode->vma - offset;
17159
17160 switch (errnode->type)
17161 {
17162 case VFP11_ERRATUM_BRANCH_TO_ARM_VENEER:
17163 {
17164 bfd_vma branch_to_veneer;
17165 /* Original condition code of instruction, plus bit mask for
17166 ARM B instruction. */
17167 unsigned int insn = (errnode->u.b.vfp_insn & 0xf0000000)
17168 | 0x0a000000;
c7b8f16e
JB		 17169
17170 /* The instruction is before the label. */
91d6fa6a 17171 target -= 4;
c7b8f16e
JB		 17172
17173 /* Above offset included in -4 below. */
17174 branch_to_veneer = errnode->u.b.veneer->vma
99059e56 17175 - errnode->vma - 4;
c7b8f16e
JB		 17176
17177 if ((signed) branch_to_veneer < -(1 << 25)
17178 || (signed) branch_to_veneer >= (1 << 25))
17179 (*_bfd_error_handler) (_("%B: error: VFP11 veneer out of "
17180 "range"), output_bfd);
17181
99059e56
RM		 17182 insn |= (branch_to_veneer >> 2) & 0xffffff;
17183 contents[endianflip ^ target] = insn & 0xff;
17184 contents[endianflip ^ (target + 1)] = (insn >> 8) & 0xff;
17185 contents[endianflip ^ (target + 2)] = (insn >> 16) & 0xff;
17186 contents[endianflip ^ (target + 3)] = (insn >> 24) & 0xff;
17187 }
17188 break;
c7b8f16e
JB		 17189
17190 case VFP11_ERRATUM_ARM_VENEER:
99059e56
RM		 17191 {
17192 bfd_vma branch_from_veneer;
17193 unsigned int insn;
c7b8f16e 17194
99059e56
RM		 17195 /* Take size of veneer into account. */
17196 branch_from_veneer = errnode->u.v.branch->vma
17197 - errnode->vma - 12;
c7b8f16e
JB		 17198
17199 if ((signed) branch_from_veneer < -(1 << 25)
17200 || (signed) branch_from_veneer >= (1 << 25))
17201 (*_bfd_error_handler) (_("%B: error: VFP11 veneer out of "
17202 "range"), output_bfd);
17203
99059e56
RM		 17204 /* Original instruction. */
17205 insn = errnode->u.v.branch->u.b.vfp_insn;
17206 contents[endianflip ^ target] = insn & 0xff;
17207 contents[endianflip ^ (target + 1)] = (insn >> 8) & 0xff;
17208 contents[endianflip ^ (target + 2)] = (insn >> 16) & 0xff;
17209 contents[endianflip ^ (target + 3)] = (insn >> 24) & 0xff;
17210
17211 /* Branch back to insn after original insn. */
17212 insn = 0xea000000 | ((branch_from_veneer >> 2) & 0xffffff);
17213 contents[endianflip ^ (target + 4)] = insn & 0xff;
17214 contents[endianflip ^ (target + 5)] = (insn >> 8) & 0xff;
17215 contents[endianflip ^ (target + 6)] = (insn >> 16) & 0xff;
17216 contents[endianflip ^ (target + 7)] = (insn >> 24) & 0xff;
17217 }
17218 break;
c7b8f16e 17219
99059e56
RM		 17220 default:
17221 abort ();
17222 }
17223 }
c7b8f16e 17224 }
e489d0ae 17225
a504d23a
LA		 17226 if (arm_data->stm32l4xx_erratumcount != 0)
17227 {
17228 for (stm32l4xx_errnode = arm_data->stm32l4xx_erratumlist;
17229 stm32l4xx_errnode != 0;
17230 stm32l4xx_errnode = stm32l4xx_errnode->next)
17231 {
17232 bfd_vma target = stm32l4xx_errnode->vma - offset;
17233
17234 switch (stm32l4xx_errnode->type)
17235 {
17236 case STM32L4XX_ERRATUM_BRANCH_TO_VENEER:
17237 {
17238 unsigned int insn;
17239 bfd_vma branch_to_veneer =
17240 stm32l4xx_errnode->u.b.veneer->vma - stm32l4xx_errnode->vma;
17241
17242 if ((signed) branch_to_veneer < -(1 << 24)
17243 || (signed) branch_to_veneer >= (1 << 24))
17244 {
17245 bfd_vma out_of_range =
17246 ((signed) branch_to_veneer < -(1 << 24)) ?
17247 - branch_to_veneer - (1 << 24) :
17248 ((signed) branch_to_veneer >= (1 << 24)) ?
17249 branch_to_veneer - (1 << 24) : 0;
17250
17251 (*_bfd_error_handler)
17252 (_("%B(%#x): error: Cannot create STM32L4XX veneer. "
eee926f2 17253 "Jump out of range by %ld bytes. "
a504d23a
LA		 17254 "Cannot encode branch instruction. "),
17255 output_bfd,
eee926f2 17256 (long) (stm32l4xx_errnode->vma - 4),
a504d23a
LA		 17257 out_of_range);
17258 continue;
17259 }
17260
17261 insn = create_instruction_branch_absolute
82188b29 17262 (stm32l4xx_errnode->u.b.veneer->vma - stm32l4xx_errnode->vma);
a504d23a
LA		 17263
17264 /* The instruction is before the label. */
17265 target -= 4;
17266
17267 put_thumb2_insn (globals, output_bfd,
17268 (bfd_vma) insn, contents + target);
17269 }
17270 break;
17271
17272 case STM32L4XX_ERRATUM_VENEER:
17273 {
82188b29
NC		 17274 bfd_byte * veneer;
17275 bfd_byte * veneer_r;
a504d23a
LA		 17276 unsigned int insn;
17277
82188b29
NC		 17278 veneer = contents + target;
17279 veneer_r = veneer
17280 + stm32l4xx_errnode->u.b.veneer->vma
17281 - stm32l4xx_errnode->vma - 4;
a504d23a
LA		 17282
17283 if ((signed) (veneer_r - veneer -
17284 STM32L4XX_ERRATUM_VLDM_VENEER_SIZE >
17285 STM32L4XX_ERRATUM_LDM_VENEER_SIZE ?
17286 STM32L4XX_ERRATUM_VLDM_VENEER_SIZE :
17287 STM32L4XX_ERRATUM_LDM_VENEER_SIZE) < -(1 << 24)
17288 || (signed) (veneer_r - veneer) >= (1 << 24))
17289 {
17290 (*_bfd_error_handler) (_("%B: error: Cannot create STM32L4XX "
17291 "veneer."), output_bfd);
17292 continue;
17293 }
17294
17295 /* Original instruction. */
17296 insn = stm32l4xx_errnode->u.v.branch->u.b.insn;
17297
17298 stm32l4xx_create_replacing_stub
17299 (globals, output_bfd, insn, (void*)veneer_r, (void*)veneer);
17300 }
17301 break;
17302
17303 default:
17304 abort ();
17305 }
17306 }
17307 }
17308
2468f9c9
PB		 17309 if (arm_data->elf.this_hdr.sh_type == SHT_ARM_EXIDX)
17310 {
17311 arm_unwind_table_edit *edit_node
99059e56 17312 = arm_data->u.exidx.unwind_edit_list;
2468f9c9 17313 /* Now, sec->size is the size of the section we will write. The original
99059e56 17314 size (before we merged duplicate entries and inserted EXIDX_CANTUNWIND
2468f9c9
PB		 17315 markers) was sec->rawsize. (This isn't the case if we perform no
17316 edits, then rawsize will be zero and we should use size). */
21d799b5 17317 bfd_byte *edited_contents = (bfd_byte *) bfd_malloc (sec->size);
2468f9c9
PB		 17318 unsigned int input_size = sec->rawsize ? sec->rawsize : sec->size;
17319 unsigned int in_index, out_index;
17320 bfd_vma add_to_offsets = 0;
17321
17322 for (in_index = 0, out_index = 0; in_index * 8 < input_size || edit_node;)
99059e56 17323 {
2468f9c9
PB		 17324 if (edit_node)
17325 {
17326 unsigned int edit_index = edit_node->index;
b38cadfb 17327
2468f9c9 17328 if (in_index < edit_index && in_index * 8 < input_size)
99059e56 17329 {
2468f9c9
PB		 17330 copy_exidx_entry (output_bfd, edited_contents + out_index * 8,
17331 contents + in_index * 8, add_to_offsets);
17332 out_index++;
17333 in_index++;
17334 }
17335 else if (in_index == edit_index
17336 || (in_index * 8 >= input_size
17337 && edit_index == UINT_MAX))
99059e56 17338 {
2468f9c9
PB		 17339 switch (edit_node->type)
17340 {
17341 case DELETE_EXIDX_ENTRY:
17342 in_index++;
17343 add_to_offsets += 8;
17344 break;
b38cadfb 17345
2468f9c9
PB		 17346 case INSERT_EXIDX_CANTUNWIND_AT_END:
17347 {
99059e56 17348 asection *text_sec = edit_node->linked_section;
2468f9c9
PB		 17349 bfd_vma text_offset = text_sec->output_section->vma
17350 + text_sec->output_offset
17351 + text_sec->size;
17352 bfd_vma exidx_offset = offset + out_index * 8;
99059e56 17353 unsigned long prel31_offset;
2468f9c9
PB		 17354
17355 /* Note: this is meant to be equivalent to an
17356 R_ARM_PREL31 relocation. These synthetic
17357 EXIDX_CANTUNWIND markers are not relocated by the
17358 usual BFD method. */
17359 prel31_offset = (text_offset - exidx_offset)
17360 & 0x7ffffffful;
491d01d3
YU		 17361 if (bfd_link_relocatable (link_info))
17362 {
17363 /* Here relocation for new EXIDX_CANTUNWIND is
17364 created, so there is no need to
17365 adjust offset by hand. */
17366 prel31_offset = text_sec->output_offset
17367 + text_sec->size;
17368
17369 /* New relocation entity. */
17370 asection *text_out = text_sec->output_section;
17371 Elf_Internal_Rela rel;
17372 rel.r_addend = 0;
17373 rel.r_offset = exidx_offset;
17374 rel.r_info = ELF32_R_INFO (text_out->target_index,
17375 R_ARM_PREL31);
17376
17377 elf32_arm_add_relocation (output_bfd, link_info,
17378 sec->output_section,
17379 &rel);
17380 }
2468f9c9
PB		 17381
17382 /* First address we can't unwind. */
17383 bfd_put_32 (output_bfd, prel31_offset,
17384 &edited_contents[out_index * 8]);
17385
17386 /* Code for EXIDX_CANTUNWIND. */
17387 bfd_put_32 (output_bfd, 0x1,
17388 &edited_contents[out_index * 8 + 4]);
17389
17390 out_index++;
17391 add_to_offsets -= 8;
17392 }
17393 break;
17394 }
b38cadfb 17395
2468f9c9
PB		 17396 edit_node = edit_node->next;
17397 }
17398 }
17399 else
17400 {
17401 /* No more edits, copy remaining entries verbatim. */
17402 copy_exidx_entry (output_bfd, edited_contents + out_index * 8,
17403 contents + in_index * 8, add_to_offsets);
17404 out_index++;
17405 in_index++;
17406 }
17407 }
17408
17409 if (!(sec->flags & SEC_EXCLUDE) && !(sec->flags & SEC_NEVER_LOAD))
17410 bfd_set_section_contents (output_bfd, sec->output_section,
17411 edited_contents,
17412 (file_ptr) sec->output_offset, sec->size);
17413
17414 return TRUE;
17415 }
17416
48229727
JB		 17417 /* Fix code to point to Cortex-A8 erratum stubs. */
17418 if (globals->fix_cortex_a8)
17419 {
17420 struct a8_branch_to_stub_data data;
17421
17422 data.writing_section = sec;
17423 data.contents = contents;
17424
a504d23a
LA		 17425 bfd_hash_traverse (& globals->stub_hash_table, make_branch_to_a8_stub,
17426 & data);
48229727
JB		 17427 }
17428
e489d0ae
PB		 17429 if (mapcount == 0)
17430 return FALSE;
17431
c7b8f16e 17432 if (globals->byteswap_code)
e489d0ae 17433 {
c7b8f16e 17434 qsort (map, mapcount, sizeof (* map), elf32_arm_compare_mapping);
57e8b36a 17435
c7b8f16e
JB		 17436 ptr = map[0].vma;
17437 for (i = 0; i < mapcount; i++)
99059e56
RM		 17438 {
17439 if (i == mapcount - 1)
c7b8f16e 17440 end = sec->size;
99059e56
RM		 17441 else
17442 end = map[i + 1].vma;
e489d0ae 17443
99059e56 17444 switch (map[i].type)
e489d0ae 17445 {
c7b8f16e
JB		 17446 case 'a':
17447 /* Byte swap code words. */
17448 while (ptr + 3 < end)
99059e56
RM		 17449 {
17450 tmp = contents[ptr];
17451 contents[ptr] = contents[ptr + 3];
17452 contents[ptr + 3] = tmp;
17453 tmp = contents[ptr + 1];
17454 contents[ptr + 1] = contents[ptr + 2];
17455 contents[ptr + 2] = tmp;
17456 ptr += 4;
17457 }
c7b8f16e 17458 break;
e489d0ae 17459
c7b8f16e
JB		 17460 case 't':
17461 /* Byte swap code halfwords. */
17462 while (ptr + 1 < end)
99059e56
RM		 17463 {
17464 tmp = contents[ptr];
17465 contents[ptr] = contents[ptr + 1];
17466 contents[ptr + 1] = tmp;
17467 ptr += 2;
17468 }
c7b8f16e
JB		 17469 break;
17470
17471 case 'd':
17472 /* Leave data alone. */
17473 break;
17474 }
99059e56
RM		 17475 ptr = end;
17476 }
e489d0ae 17477 }
8e3de13a 17478
93204d3a 17479 free (map);
47b2e99c 17480 arm_data->mapcount = -1;
c7b8f16e 17481 arm_data->mapsize = 0;
8e3de13a 17482 arm_data->map = NULL;
8e3de13a 17483
e489d0ae
PB		 17484 return FALSE;
17485}
17486
0beaef2b
PB		 17487/* Mangle thumb function symbols as we read them in. */
17488
8384fb8f 17489static bfd_boolean
0beaef2b
PB		 17490elf32_arm_swap_symbol_in (bfd * abfd,
17491 const void *psrc,
17492 const void *pshn,
17493 Elf_Internal_Sym *dst)
17494{
8384fb8f
AM		 17495 if (!bfd_elf32_swap_symbol_in (abfd, psrc, pshn, dst))
17496 return FALSE;
0beaef2b
PB		 17497
17498 /* New EABI objects mark thumb function symbols by setting the low bit of
35fc36a8 17499 the address. */
63e1a0fc
PB		 17500 if (ELF_ST_TYPE (dst->st_info) == STT_FUNC
17501 || ELF_ST_TYPE (dst->st_info) == STT_GNU_IFUNC)
0beaef2b 17502 {
63e1a0fc
PB		 17503 if (dst->st_value & 1)
17504 {
17505 dst->st_value &= ~(bfd_vma) 1;
17506 dst->st_target_internal = ST_BRANCH_TO_THUMB;
17507 }
17508 else
17509 dst->st_target_internal = ST_BRANCH_TO_ARM;
35fc36a8
RS		 17510 }
17511 else if (ELF_ST_TYPE (dst->st_info) == STT_ARM_TFUNC)
17512 {
17513 dst->st_info = ELF_ST_INFO (ELF_ST_BIND (dst->st_info), STT_FUNC);
17514 dst->st_target_internal = ST_BRANCH_TO_THUMB;
0beaef2b 17515 }
35fc36a8
RS		 17516 else if (ELF_ST_TYPE (dst->st_info) == STT_SECTION)
17517 dst->st_target_internal = ST_BRANCH_LONG;
17518 else
63e1a0fc 17519 dst->st_target_internal = ST_BRANCH_UNKNOWN;
35fc36a8 17520
8384fb8f 17521 return TRUE;
0beaef2b
PB		 17522}
17523
17524
17525/* Mangle thumb function symbols as we write them out. */
17526
17527static void
17528elf32_arm_swap_symbol_out (bfd *abfd,
17529 const Elf_Internal_Sym *src,
17530 void *cdst,
17531 void *shndx)
17532{
17533 Elf_Internal_Sym newsym;
17534
17535 /* We convert STT_ARM_TFUNC symbols into STT_FUNC with the low bit
17536 of the address set, as per the new EABI. We do this unconditionally
17537 because objcopy does not set the elf header flags until after
17538 it writes out the symbol table. */
35fc36a8 17539 if (src->st_target_internal == ST_BRANCH_TO_THUMB)
0beaef2b
PB		 17540 {
17541 newsym = *src;
34e77a92
RS		 17542 if (ELF_ST_TYPE (src->st_info) != STT_GNU_IFUNC)
17543 newsym.st_info = ELF_ST_INFO (ELF_ST_BIND (src->st_info), STT_FUNC);
0fa3dcad 17544 if (newsym.st_shndx != SHN_UNDEF)
99059e56
RM		 17545 {
17546 /* Do this only for defined symbols. At link type, the static
17547 linker will simulate the work of dynamic linker of resolving
17548 symbols and will carry over the thumbness of found symbols to
17549 the output symbol table. It's not clear how it happens, but
17550 the thumbness of undefined symbols can well be different at
17551 runtime, and writing '1' for them will be confusing for users
17552 and possibly for dynamic linker itself.
17553 */
17554 newsym.st_value |= 1;
17555 }
906e58ca 17556
0beaef2b
PB		 17557 src = &newsym;
17558 }
17559 bfd_elf32_swap_symbol_out (abfd, src, cdst, shndx);
17560}
17561
b294bdf8
MM		 17562/* Add the PT_ARM_EXIDX program header. */
17563
17564static bfd_boolean
906e58ca 17565elf32_arm_modify_segment_map (bfd *abfd,
b294bdf8
MM		 17566 struct bfd_link_info *info ATTRIBUTE_UNUSED)
17567{
17568 struct elf_segment_map *m;
17569 asection *sec;
17570
17571 sec = bfd_get_section_by_name (abfd, ".ARM.exidx");
17572 if (sec != NULL && (sec->flags & SEC_LOAD) != 0)
17573 {
17574 /* If there is already a PT_ARM_EXIDX header, then we do not
17575 want to add another one. This situation arises when running
17576 "strip"; the input binary already has the header. */
12bd6957 17577 m = elf_seg_map (abfd);
b294bdf8
MM		 17578 while (m && m->p_type != PT_ARM_EXIDX)
17579 m = m->next;
17580 if (!m)
17581 {
21d799b5 17582 m = (struct elf_segment_map *)
99059e56 17583 bfd_zalloc (abfd, sizeof (struct elf_segment_map));
b294bdf8
MM		 17584 if (m == NULL)
17585 return FALSE;
17586 m->p_type = PT_ARM_EXIDX;
17587 m->count = 1;
17588 m->sections[0] = sec;
17589
12bd6957
AM		 17590 m->next = elf_seg_map (abfd);
17591 elf_seg_map (abfd) = m;
b294bdf8
MM		 17592 }
17593 }
17594
17595 return TRUE;
17596}
17597
17598/* We may add a PT_ARM_EXIDX program header. */
17599
17600static int
a6b96beb
AM		 17601elf32_arm_additional_program_headers (bfd *abfd,
17602 struct bfd_link_info *info ATTRIBUTE_UNUSED)
b294bdf8
MM		 17603{
17604 asection *sec;
17605
17606 sec = bfd_get_section_by_name (abfd, ".ARM.exidx");
17607 if (sec != NULL && (sec->flags & SEC_LOAD) != 0)
17608 return 1;
17609 else
17610 return 0;
17611}
17612
34e77a92
RS		 17613/* Hook called by the linker routine which adds symbols from an object
17614 file. */
17615
17616static bfd_boolean
17617elf32_arm_add_symbol_hook (bfd *abfd, struct bfd_link_info *info,
17618 Elf_Internal_Sym *sym, const char **namep,
17619 flagword *flagsp, asection **secp, bfd_vma *valp)
17620{
f1885d1e
AM		 17621 if ((ELF_ST_TYPE (sym->st_info) == STT_GNU_IFUNC
17622 || ELF_ST_BIND (sym->st_info) == STB_GNU_UNIQUE)
17623 && (abfd->flags & DYNAMIC) == 0
17624 && bfd_get_flavour (info->output_bfd) == bfd_target_elf_flavour)
13a2df29 17625 elf_tdata (info->output_bfd)->has_gnu_symbols = elf_gnu_symbol_any;
34e77a92 17626
c792917c
NC		 17627 if (elf32_arm_hash_table (info) == NULL)
17628 return FALSE;
17629
34e77a92
RS		 17630 if (elf32_arm_hash_table (info)->vxworks_p
17631 && !elf_vxworks_add_symbol_hook (abfd, info, sym, namep,
17632 flagsp, secp, valp))
17633 return FALSE;
17634
17635 return TRUE;
17636}
17637
0beaef2b 17638/* We use this to override swap_symbol_in and swap_symbol_out. */
906e58ca
NC		 17639const struct elf_size_info elf32_arm_size_info =
17640{
0beaef2b
PB		 17641 sizeof (Elf32_External_Ehdr),
17642 sizeof (Elf32_External_Phdr),
17643 sizeof (Elf32_External_Shdr),
17644 sizeof (Elf32_External_Rel),
17645 sizeof (Elf32_External_Rela),
17646 sizeof (Elf32_External_Sym),
17647 sizeof (Elf32_External_Dyn),
17648 sizeof (Elf_External_Note),
17649 4,
17650 1,
17651 32, 2,
17652 ELFCLASS32, EV_CURRENT,
17653 bfd_elf32_write_out_phdrs,
17654 bfd_elf32_write_shdrs_and_ehdr,
1489a3a0 17655 bfd_elf32_checksum_contents,
0beaef2b
PB		 17656 bfd_elf32_write_relocs,
17657 elf32_arm_swap_symbol_in,
17658 elf32_arm_swap_symbol_out,
17659 bfd_elf32_slurp_reloc_table,
17660 bfd_elf32_slurp_symbol_table,
17661 bfd_elf32_swap_dyn_in,
17662 bfd_elf32_swap_dyn_out,
17663 bfd_elf32_swap_reloc_in,
17664 bfd_elf32_swap_reloc_out,
17665 bfd_elf32_swap_reloca_in,
17666 bfd_elf32_swap_reloca_out
17667};
17668
685e70ae
VK		 17669static bfd_vma
17670read_code32 (const bfd *abfd, const bfd_byte *addr)
17671{
17672 /* V7 BE8 code is always little endian. */
17673 if ((elf_elfheader (abfd)->e_flags & EF_ARM_BE8) != 0)
17674 return bfd_getl32 (addr);
17675
17676 return bfd_get_32 (abfd, addr);
17677}
17678
17679static bfd_vma
17680read_code16 (const bfd *abfd, const bfd_byte *addr)
17681{
17682 /* V7 BE8 code is always little endian. */
17683 if ((elf_elfheader (abfd)->e_flags & EF_ARM_BE8) != 0)
17684 return bfd_getl16 (addr);
17685
17686 return bfd_get_16 (abfd, addr);
17687}
17688
6a631e86
YG		 17689/* Return size of plt0 entry starting at ADDR
17690 or (bfd_vma) -1 if size can not be determined. */
17691
17692static bfd_vma
17693elf32_arm_plt0_size (const bfd *abfd, const bfd_byte *addr)
17694{
17695 bfd_vma first_word;
17696 bfd_vma plt0_size;
17697
685e70ae 17698 first_word = read_code32 (abfd, addr);
6a631e86
YG		 17699
17700 if (first_word == elf32_arm_plt0_entry[0])
17701 plt0_size = 4 * ARRAY_SIZE (elf32_arm_plt0_entry);
17702 else if (first_word == elf32_thumb2_plt0_entry[0])
17703 plt0_size = 4 * ARRAY_SIZE (elf32_thumb2_plt0_entry);
17704 else
17705 /* We don't yet handle this PLT format. */
17706 return (bfd_vma) -1;
17707
17708 return plt0_size;
17709}
17710
17711/* Return size of plt entry starting at offset OFFSET
17712 of plt section located at address START
17713 or (bfd_vma) -1 if size can not be determined. */
17714
17715static bfd_vma
17716elf32_arm_plt_size (const bfd *abfd, const bfd_byte *start, bfd_vma offset)
17717{
17718 bfd_vma first_insn;
17719 bfd_vma plt_size = 0;
17720 const bfd_byte *addr = start + offset;
17721
17722 /* PLT entry size if fixed on Thumb-only platforms. */
685e70ae 17723 if (read_code32 (abfd, start) == elf32_thumb2_plt0_entry[0])
6a631e86
YG		 17724 return 4 * ARRAY_SIZE (elf32_thumb2_plt_entry);
17725
17726 /* Respect Thumb stub if necessary. */
685e70ae 17727 if (read_code16 (abfd, addr) == elf32_arm_plt_thumb_stub[0])
6a631e86
YG		 17728 {
17729 plt_size += 2 * ARRAY_SIZE(elf32_arm_plt_thumb_stub);
17730 }
17731
17732 /* Strip immediate from first add. */
685e70ae 17733 first_insn = read_code32 (abfd, addr + plt_size) & 0xffffff00;
6a631e86
YG		 17734
17735#ifdef FOUR_WORD_PLT
17736 if (first_insn == elf32_arm_plt_entry[0])
17737 plt_size += 4 * ARRAY_SIZE (elf32_arm_plt_entry);
17738#else
17739 if (first_insn == elf32_arm_plt_entry_long[0])
17740 plt_size += 4 * ARRAY_SIZE (elf32_arm_plt_entry_long);
17741 else if (first_insn == elf32_arm_plt_entry_short[0])
17742 plt_size += 4 * ARRAY_SIZE (elf32_arm_plt_entry_short);
17743#endif
17744 else
17745 /* We don't yet handle this PLT format. */
17746 return (bfd_vma) -1;
17747
17748 return plt_size;
17749}
17750
17751/* Implementation is shamelessly borrowed from _bfd_elf_get_synthetic_symtab. */
17752
17753static long
17754elf32_arm_get_synthetic_symtab (bfd *abfd,
17755 long symcount ATTRIBUTE_UNUSED,
17756 asymbol **syms ATTRIBUTE_UNUSED,
17757 long dynsymcount,
17758 asymbol **dynsyms,
17759 asymbol **ret)
17760{
17761 asection *relplt;
17762 asymbol *s;
17763 arelent *p;
17764 long count, i, n;
17765 size_t size;
17766 Elf_Internal_Shdr *hdr;
17767 char *names;
17768 asection *plt;
17769 bfd_vma offset;
17770 bfd_byte *data;
17771
17772 *ret = NULL;
17773
17774 if ((abfd->flags & (DYNAMIC | EXEC_P)) == 0)
17775 return 0;
17776
17777 if (dynsymcount <= 0)
17778 return 0;
17779
17780 relplt = bfd_get_section_by_name (abfd, ".rel.plt");
17781 if (relplt == NULL)
17782 return 0;
17783
17784 hdr = &elf_section_data (relplt)->this_hdr;
17785 if (hdr->sh_link != elf_dynsymtab (abfd)
17786 || (hdr->sh_type != SHT_REL && hdr->sh_type != SHT_RELA))
17787 return 0;
17788
17789 plt = bfd_get_section_by_name (abfd, ".plt");
17790 if (plt == NULL)
17791 return 0;
17792
17793 if (!elf32_arm_size_info.slurp_reloc_table (abfd, relplt, dynsyms, TRUE))
17794 return -1;
17795
17796 data = plt->contents;
17797 if (data == NULL)
17798 {
17799 if (!bfd_get_full_section_contents(abfd, (asection *) plt, &data) || data == NULL)
17800 return -1;
17801 bfd_cache_section_contents((asection *) plt, data);
17802 }
17803
17804 count = relplt->size / hdr->sh_entsize;
17805 size = count * sizeof (asymbol);
17806 p = relplt->relocation;
17807 for (i = 0; i < count; i++, p += elf32_arm_size_info.int_rels_per_ext_rel)
17808 {
17809 size += strlen ((*p->sym_ptr_ptr)->name) + sizeof ("@plt");
17810 if (p->addend != 0)
17811 size += sizeof ("+0x") - 1 + 8;
17812 }
17813
17814 s = *ret = (asymbol *) bfd_malloc (size);
17815 if (s == NULL)
17816 return -1;
17817
17818 offset = elf32_arm_plt0_size (abfd, data);
17819 if (offset == (bfd_vma) -1)
17820 return -1;
17821
17822 names = (char *) (s + count);
17823 p = relplt->relocation;
17824 n = 0;
17825 for (i = 0; i < count; i++, p += elf32_arm_size_info.int_rels_per_ext_rel)
17826 {
17827 size_t len;
17828
17829 bfd_vma plt_size = elf32_arm_plt_size (abfd, data, offset);
17830 if (plt_size == (bfd_vma) -1)
17831 break;
17832
17833 *s = **p->sym_ptr_ptr;
17834 /* Undefined syms won't have BSF_LOCAL or BSF_GLOBAL set. Since
17835 we are defining a symbol, ensure one of them is set. */
17836 if ((s->flags & BSF_LOCAL) == 0)
17837 s->flags |= BSF_GLOBAL;
17838 s->flags |= BSF_SYNTHETIC;
17839 s->section = plt;
17840 s->value = offset;
17841 s->name = names;
17842 s->udata.p = NULL;
17843 len = strlen ((*p->sym_ptr_ptr)->name);
17844 memcpy (names, (*p->sym_ptr_ptr)->name, len);
17845 names += len;
17846 if (p->addend != 0)
17847 {
17848 char buf[30], *a;
17849
17850 memcpy (names, "+0x", sizeof ("+0x") - 1);
17851 names += sizeof ("+0x") - 1;
17852 bfd_sprintf_vma (abfd, buf, p->addend);
17853 for (a = buf; *a == '0'; ++a)
17854 ;
17855 len = strlen (a);
17856 memcpy (names, a, len);
17857 names += len;
17858 }
17859 memcpy (names, "@plt", sizeof ("@plt"));
17860 names += sizeof ("@plt");
17861 ++s, ++n;
17862 offset += plt_size;
17863 }
17864
17865 return n;
17866}
17867
ac4c9b04
MG		 17868static bfd_boolean
17869elf32_arm_section_flags (flagword *flags, const Elf_Internal_Shdr * hdr)
17870{
17871 if (hdr->sh_flags & SHF_ARM_NOREAD)
17872 *flags |= SEC_ELF_NOREAD;
17873 return TRUE;
17874}
17875
17876static flagword
17877elf32_arm_lookup_section_flags (char *flag_name)
17878{
17879 if (!strcmp (flag_name, "SHF_ARM_NOREAD"))
17880 return SHF_ARM_NOREAD;
17881
17882 return SEC_NO_FLAGS;
17883}
17884
491d01d3
YU		 17885static unsigned int
17886elf32_arm_count_additional_relocs (asection *sec)
17887{
17888 struct _arm_elf_section_data *arm_data;
17889 arm_data = get_arm_elf_section_data (sec);
17890 return arm_data->additional_reloc_count;
17891}
17892
5522f910
NC		 17893/* Called to set the sh_flags, sh_link and sh_info fields of OSECTION which
17894 has a type >= SHT_LOOS. Returns TRUE if these fields were initialised
17895 FALSE otherwise. ISECTION is the best guess matching section from the
17896 input bfd IBFD, but it might be NULL. */
17897
17898static bfd_boolean
17899elf32_arm_copy_special_section_fields (const bfd *ibfd ATTRIBUTE_UNUSED,
17900 bfd *obfd ATTRIBUTE_UNUSED,
17901 const Elf_Internal_Shdr *isection ATTRIBUTE_UNUSED,
17902 Elf_Internal_Shdr *osection)
17903{
17904 switch (osection->sh_type)
17905 {
17906 case SHT_ARM_EXIDX:
17907 {
17908 Elf_Internal_Shdr **oheaders = elf_elfsections (obfd);
17909 Elf_Internal_Shdr **iheaders = elf_elfsections (ibfd);
17910 unsigned i = 0;
17911
17912 osection->sh_flags = SHF_ALLOC | SHF_LINK_ORDER;
17913 osection->sh_info = 0;
17914
17915 /* The sh_link field must be set to the text section associated with
17916 this index section. Unfortunately the ARM EHABI does not specify
17917 exactly how to determine this association. Our caller does try
17918 to match up OSECTION with its corresponding input section however
17919 so that is a good first guess. */
17920 if (isection != NULL
17921 && osection->bfd_section != NULL
17922 && isection->bfd_section != NULL
17923 && isection->bfd_section->output_section != NULL
17924 && isection->bfd_section->output_section == osection->bfd_section
17925 && iheaders != NULL
17926 && isection->sh_link > 0
17927 && isection->sh_link < elf_numsections (ibfd)
17928 && iheaders[isection->sh_link]->bfd_section != NULL
17929 && iheaders[isection->sh_link]->bfd_section->output_section != NULL
17930 )
17931 {
17932 for (i = elf_numsections (obfd); i-- > 0;)
17933 if (oheaders[i]->bfd_section
17934 == iheaders[isection->sh_link]->bfd_section->output_section)
17935 break;
17936 }
17937
17938 if (i == 0)
17939 {
17940 /* Failing that we have to find a matching section ourselves. If
17941 we had the output section name available we could compare that
17942 with input section names. Unfortunately we don't. So instead
17943 we use a simple heuristic and look for the nearest executable
17944 section before this one. */
17945 for (i = elf_numsections (obfd); i-- > 0;)
17946 if (oheaders[i] == osection)
17947 break;
17948 if (i == 0)
17949 break;
17950
17951 while (i-- > 0)
17952 if (oheaders[i]->sh_type == SHT_PROGBITS
17953 && (oheaders[i]->sh_flags & (SHF_ALLOC | SHF_EXECINSTR))
17954 == (SHF_ALLOC | SHF_EXECINSTR))
17955 break;
17956 }
17957
17958 if (i)
17959 {
17960 osection->sh_link = i;
17961 /* If the text section was part of a group
17962 then the index section should be too. */
17963 if (oheaders[i]->sh_flags & SHF_GROUP)
17964 osection->sh_flags |= SHF_GROUP;
17965 return TRUE;
17966 }
17967 }
17968 break;
17969
17970 case SHT_ARM_PREEMPTMAP:
17971 osection->sh_flags = SHF_ALLOC;
17972 break;
17973
17974 case SHT_ARM_ATTRIBUTES:
17975 case SHT_ARM_DEBUGOVERLAY:
17976 case SHT_ARM_OVERLAYSECTION:
17977 default:
17978 break;
17979 }
17980
17981 return FALSE;
17982}
17983
17984#undef elf_backend_copy_special_section_fields
17985#define elf_backend_copy_special_section_fields elf32_arm_copy_special_section_fields
17986
252b5132 17987#define ELF_ARCH bfd_arch_arm
ae95ffa6 17988#define ELF_TARGET_ID ARM_ELF_DATA
252b5132 17989#define ELF_MACHINE_CODE EM_ARM
d0facd1b
NC		 17990#ifdef __QNXTARGET__
17991#define ELF_MAXPAGESIZE 0x1000
17992#else
7572ca89 17993#define ELF_MAXPAGESIZE 0x10000
d0facd1b 17994#endif
b1342370 17995#define ELF_MINPAGESIZE 0x1000
24718e3b 17996#define ELF_COMMONPAGESIZE 0x1000
252b5132 17997
ba93b8ac
DJ		 17998#define bfd_elf32_mkobject elf32_arm_mkobject
17999
99e4ae17
AJ		 18000#define bfd_elf32_bfd_copy_private_bfd_data elf32_arm_copy_private_bfd_data
18001#define bfd_elf32_bfd_merge_private_bfd_data elf32_arm_merge_private_bfd_data
252b5132
RH		 18002#define bfd_elf32_bfd_set_private_flags elf32_arm_set_private_flags
18003#define bfd_elf32_bfd_print_private_bfd_data elf32_arm_print_private_bfd_data
18004#define bfd_elf32_bfd_link_hash_table_create elf32_arm_link_hash_table_create
dc810e39 18005#define bfd_elf32_bfd_reloc_type_lookup elf32_arm_reloc_type_lookup
b38cadfb 18006#define bfd_elf32_bfd_reloc_name_lookup elf32_arm_reloc_name_lookup
252b5132 18007#define bfd_elf32_find_nearest_line elf32_arm_find_nearest_line
4ab527b0 18008#define bfd_elf32_find_inliner_info elf32_arm_find_inliner_info
e489d0ae 18009#define bfd_elf32_new_section_hook elf32_arm_new_section_hook
3c9458e9 18010#define bfd_elf32_bfd_is_target_special_symbol elf32_arm_is_target_special_symbol
3e6b1042 18011#define bfd_elf32_bfd_final_link elf32_arm_final_link
6a631e86 18012#define bfd_elf32_get_synthetic_symtab elf32_arm_get_synthetic_symtab
252b5132
RH		 18013
18014#define elf_backend_get_symbol_type elf32_arm_get_symbol_type
18015#define elf_backend_gc_mark_hook elf32_arm_gc_mark_hook
6a5bb875 18016#define elf_backend_gc_mark_extra_sections elf32_arm_gc_mark_extra_sections
252b5132
RH		 18017#define elf_backend_gc_sweep_hook elf32_arm_gc_sweep_hook
18018#define elf_backend_check_relocs elf32_arm_check_relocs
dc810e39 18019#define elf_backend_relocate_section elf32_arm_relocate_section
e489d0ae 18020#define elf_backend_write_section elf32_arm_write_section
252b5132 18021#define elf_backend_adjust_dynamic_symbol elf32_arm_adjust_dynamic_symbol
5e681ec4 18022#define elf_backend_create_dynamic_sections elf32_arm_create_dynamic_sections
252b5132
RH		 18023#define elf_backend_finish_dynamic_symbol elf32_arm_finish_dynamic_symbol
18024#define elf_backend_finish_dynamic_sections elf32_arm_finish_dynamic_sections
18025#define elf_backend_size_dynamic_sections elf32_arm_size_dynamic_sections
0855e32b 18026#define elf_backend_always_size_sections elf32_arm_always_size_sections
74541ad4 18027#define elf_backend_init_index_section _bfd_elf_init_2_index_sections
ba96a88f 18028#define elf_backend_post_process_headers elf32_arm_post_process_headers
99e4ae17 18029#define elf_backend_reloc_type_class elf32_arm_reloc_type_class
c178919b 18030#define elf_backend_object_p elf32_arm_object_p
40a18ebd
NC		 18031#define elf_backend_fake_sections elf32_arm_fake_sections
18032#define elf_backend_section_from_shdr elf32_arm_section_from_shdr
e16bb312 18033#define elf_backend_final_write_processing elf32_arm_final_write_processing
5e681ec4 18034#define elf_backend_copy_indirect_symbol elf32_arm_copy_indirect_symbol
0beaef2b 18035#define elf_backend_size_info elf32_arm_size_info
b294bdf8 18036#define elf_backend_modify_segment_map elf32_arm_modify_segment_map
906e58ca
NC		 18037#define elf_backend_additional_program_headers elf32_arm_additional_program_headers
18038#define elf_backend_output_arch_local_syms elf32_arm_output_arch_local_syms
18039#define elf_backend_begin_write_processing elf32_arm_begin_write_processing
34e77a92 18040#define elf_backend_add_symbol_hook elf32_arm_add_symbol_hook
491d01d3 18041#define elf_backend_count_additional_relocs elf32_arm_count_additional_relocs
906e58ca
NC		 18042
18043#define elf_backend_can_refcount 1
18044#define elf_backend_can_gc_sections 1
18045#define elf_backend_plt_readonly 1
18046#define elf_backend_want_got_plt 1
18047#define elf_backend_want_plt_sym 0
18048#define elf_backend_may_use_rel_p 1
18049#define elf_backend_may_use_rela_p 0
4e7fd91e 18050#define elf_backend_default_use_rela_p 0
252b5132 18051
04f7c78d 18052#define elf_backend_got_header_size 12
b68a20d6 18053#define elf_backend_extern_protected_data 1
04f7c78d 18054
906e58ca
NC		 18055#undef elf_backend_obj_attrs_vendor
18056#define elf_backend_obj_attrs_vendor "aeabi"
18057#undef elf_backend_obj_attrs_section
18058#define elf_backend_obj_attrs_section ".ARM.attributes"
18059#undef elf_backend_obj_attrs_arg_type
18060#define elf_backend_obj_attrs_arg_type elf32_arm_obj_attrs_arg_type
18061#undef elf_backend_obj_attrs_section_type
104d59d1 18062#define elf_backend_obj_attrs_section_type SHT_ARM_ATTRIBUTES
b38cadfb
NC		 18063#define elf_backend_obj_attrs_order elf32_arm_obj_attrs_order
18064#define elf_backend_obj_attrs_handle_unknown elf32_arm_obj_attrs_handle_unknown
104d59d1 18065
ac4c9b04
MG		 18066#undef elf_backend_section_flags
18067#define elf_backend_section_flags elf32_arm_section_flags
18068#undef elf_backend_lookup_section_flags_hook
18069#define elf_backend_lookup_section_flags_hook elf32_arm_lookup_section_flags
18070
252b5132 18071#include "elf32-target.h"
7f266840 18072
b38cadfb
NC		 18073/* Native Client targets. */
18074
18075#undef TARGET_LITTLE_SYM
6d00b590 18076#define TARGET_LITTLE_SYM arm_elf32_nacl_le_vec
b38cadfb
NC		 18077#undef TARGET_LITTLE_NAME
18078#define TARGET_LITTLE_NAME "elf32-littlearm-nacl"
18079#undef TARGET_BIG_SYM
6d00b590 18080#define TARGET_BIG_SYM arm_elf32_nacl_be_vec
b38cadfb
NC		 18081#undef TARGET_BIG_NAME
18082#define TARGET_BIG_NAME "elf32-bigarm-nacl"
18083
18084/* Like elf32_arm_link_hash_table_create -- but overrides
18085 appropriately for NaCl. */
18086
18087static struct bfd_link_hash_table *
18088elf32_arm_nacl_link_hash_table_create (bfd *abfd)
18089{
18090 struct bfd_link_hash_table *ret;
18091
18092 ret = elf32_arm_link_hash_table_create (abfd);
18093 if (ret)
18094 {
18095 struct elf32_arm_link_hash_table *htab
18096 = (struct elf32_arm_link_hash_table *) ret;
18097
18098 htab->nacl_p = 1;
18099
18100 htab->plt_header_size = 4 * ARRAY_SIZE (elf32_arm_nacl_plt0_entry);
18101 htab->plt_entry_size = 4 * ARRAY_SIZE (elf32_arm_nacl_plt_entry);
18102 }
18103 return ret;
18104}
18105
18106/* Since NaCl doesn't use the ARM-specific unwind format, we don't
18107 really need to use elf32_arm_modify_segment_map. But we do it
18108 anyway just to reduce gratuitous differences with the stock ARM backend. */
18109
18110static bfd_boolean
18111elf32_arm_nacl_modify_segment_map (bfd *abfd, struct bfd_link_info *info)
18112{
18113 return (elf32_arm_modify_segment_map (abfd, info)
18114 && nacl_modify_segment_map (abfd, info));
18115}
18116
887badb3
RM		 18117static void
18118elf32_arm_nacl_final_write_processing (bfd *abfd, bfd_boolean linker)
18119{
18120 elf32_arm_final_write_processing (abfd, linker);
18121 nacl_final_write_processing (abfd, linker);
18122}
18123
6a631e86
YG		 18124static bfd_vma
18125elf32_arm_nacl_plt_sym_val (bfd_vma i, const asection *plt,
18126 const arelent *rel ATTRIBUTE_UNUSED)
18127{
18128 return plt->vma
18129 + 4 * (ARRAY_SIZE (elf32_arm_nacl_plt0_entry) +
18130 i * ARRAY_SIZE (elf32_arm_nacl_plt_entry));
18131}
887badb3 18132
b38cadfb 18133#undef elf32_bed
6a631e86 18134#define elf32_bed elf32_arm_nacl_bed
b38cadfb
NC		 18135#undef bfd_elf32_bfd_link_hash_table_create
18136#define bfd_elf32_bfd_link_hash_table_create \
18137 elf32_arm_nacl_link_hash_table_create
18138#undef elf_backend_plt_alignment
6a631e86 18139#define elf_backend_plt_alignment 4
b38cadfb
NC		 18140#undef elf_backend_modify_segment_map
18141#define elf_backend_modify_segment_map elf32_arm_nacl_modify_segment_map
18142#undef elf_backend_modify_program_headers
18143#define elf_backend_modify_program_headers nacl_modify_program_headers
887badb3
RM		 18144#undef elf_backend_final_write_processing
18145#define elf_backend_final_write_processing elf32_arm_nacl_final_write_processing
6a631e86
YG		 18146#undef bfd_elf32_get_synthetic_symtab
18147#undef elf_backend_plt_sym_val
18148#define elf_backend_plt_sym_val elf32_arm_nacl_plt_sym_val
5522f910 18149#undef elf_backend_copy_special_section_fields
b38cadfb 18150
887badb3
RM		 18151#undef ELF_MINPAGESIZE
18152#undef ELF_COMMONPAGESIZE
18153
b38cadfb
NC		 18154
18155#include "elf32-target.h"
18156
18157/* Reset to defaults. */
18158#undef elf_backend_plt_alignment
18159#undef elf_backend_modify_segment_map
18160#define elf_backend_modify_segment_map elf32_arm_modify_segment_map
18161#undef elf_backend_modify_program_headers
887badb3
RM		 18162#undef elf_backend_final_write_processing
18163#define elf_backend_final_write_processing elf32_arm_final_write_processing
18164#undef ELF_MINPAGESIZE
18165#define ELF_MINPAGESIZE 0x1000
18166#undef ELF_COMMONPAGESIZE
18167#define ELF_COMMONPAGESIZE 0x1000
18168
b38cadfb 18169
906e58ca 18170/* VxWorks Targets. */
4e7fd91e 18171
906e58ca 18172#undef TARGET_LITTLE_SYM
6d00b590 18173#define TARGET_LITTLE_SYM arm_elf32_vxworks_le_vec
906e58ca 18174#undef TARGET_LITTLE_NAME
4e7fd91e 18175#define TARGET_LITTLE_NAME "elf32-littlearm-vxworks"
906e58ca 18176#undef TARGET_BIG_SYM
6d00b590 18177#define TARGET_BIG_SYM arm_elf32_vxworks_be_vec
906e58ca 18178#undef TARGET_BIG_NAME
4e7fd91e
PB		 18179#define TARGET_BIG_NAME "elf32-bigarm-vxworks"
18180
18181/* Like elf32_arm_link_hash_table_create -- but overrides
18182 appropriately for VxWorks. */
906e58ca 18183
4e7fd91e
PB		 18184static struct bfd_link_hash_table *
18185elf32_arm_vxworks_link_hash_table_create (bfd *abfd)
18186{
18187 struct bfd_link_hash_table *ret;
18188
18189 ret = elf32_arm_link_hash_table_create (abfd);
18190 if (ret)
18191 {
18192 struct elf32_arm_link_hash_table *htab
00a97672 18193 = (struct elf32_arm_link_hash_table *) ret;
4e7fd91e 18194 htab->use_rel = 0;
00a97672 18195 htab->vxworks_p = 1;
4e7fd91e
PB		 18196 }
18197 return ret;
906e58ca 18198}
4e7fd91e 18199
00a97672
RS		 18200static void
18201elf32_arm_vxworks_final_write_processing (bfd *abfd, bfd_boolean linker)
18202{
18203 elf32_arm_final_write_processing (abfd, linker);
18204 elf_vxworks_final_write_processing (abfd, linker);
18205}
18206
906e58ca 18207#undef elf32_bed
4e7fd91e
PB		 18208#define elf32_bed elf32_arm_vxworks_bed
18209
906e58ca
NC		 18210#undef bfd_elf32_bfd_link_hash_table_create
18211#define bfd_elf32_bfd_link_hash_table_create elf32_arm_vxworks_link_hash_table_create
906e58ca
NC		 18212#undef elf_backend_final_write_processing
18213#define elf_backend_final_write_processing elf32_arm_vxworks_final_write_processing
18214#undef elf_backend_emit_relocs
18215#define elf_backend_emit_relocs elf_vxworks_emit_relocs
4e7fd91e 18216
906e58ca 18217#undef elf_backend_may_use_rel_p
00a97672 18218#define elf_backend_may_use_rel_p 0
906e58ca 18219#undef elf_backend_may_use_rela_p
00a97672 18220#define elf_backend_may_use_rela_p 1
906e58ca 18221#undef elf_backend_default_use_rela_p
00a97672 18222#define elf_backend_default_use_rela_p 1
906e58ca 18223#undef elf_backend_want_plt_sym
00a97672 18224#define elf_backend_want_plt_sym 1
906e58ca 18225#undef ELF_MAXPAGESIZE
00a97672 18226#define ELF_MAXPAGESIZE 0x1000
4e7fd91e
PB		 18227
18228#include "elf32-target.h"
18229
18230
21d799b5
NC		 18231/* Merge backend specific data from an object file to the output
18232 object file when linking. */
18233
18234static bfd_boolean
18235elf32_arm_merge_private_bfd_data (bfd * ibfd, bfd * obfd)
18236{
18237 flagword out_flags;
18238 flagword in_flags;
18239 bfd_boolean flags_compatible = TRUE;
18240 asection *sec;
18241
cc643b88 18242 /* Check if we have the same endianness. */
21d799b5
NC		 18243 if (! _bfd_generic_verify_endian_match (ibfd, obfd))
18244 return FALSE;
18245
18246 if (! is_arm_elf (ibfd) || ! is_arm_elf (obfd))
18247 return TRUE;
18248
18249 if (!elf32_arm_merge_eabi_attributes (ibfd, obfd))
18250 return FALSE;
18251
18252 /* The input BFD must have had its flags initialised. */
18253 /* The following seems bogus to me -- The flags are initialized in
18254 the assembler but I don't think an elf_flags_init field is
18255 written into the object. */
18256 /* BFD_ASSERT (elf_flags_init (ibfd)); */
18257
18258 in_flags = elf_elfheader (ibfd)->e_flags;
18259 out_flags = elf_elfheader (obfd)->e_flags;
18260
18261 /* In theory there is no reason why we couldn't handle this. However
18262 in practice it isn't even close to working and there is no real
18263 reason to want it. */
18264 if (EF_ARM_EABI_VERSION (in_flags) >= EF_ARM_EABI_VER4
18265 && !(ibfd->flags & DYNAMIC)
18266 && (in_flags & EF_ARM_BE8))
18267 {
18268 _bfd_error_handler (_("error: %B is already in final BE8 format"),
18269 ibfd);
18270 return FALSE;
18271 }
18272
18273 if (!elf_flags_init (obfd))
18274 {
18275 /* If the input is the default architecture and had the default
18276 flags then do not bother setting the flags for the output
18277 architecture, instead allow future merges to do this. If no
18278 future merges ever set these flags then they will retain their
99059e56
RM		 18279 uninitialised values, which surprise surprise, correspond
18280 to the default values. */
21d799b5
NC		 18281 if (bfd_get_arch_info (ibfd)->the_default
18282 && elf_elfheader (ibfd)->e_flags == 0)
18283 return TRUE;
18284
18285 elf_flags_init (obfd) = TRUE;
18286 elf_elfheader (obfd)->e_flags = in_flags;
18287
18288 if (bfd_get_arch (obfd) == bfd_get_arch (ibfd)
18289 && bfd_get_arch_info (obfd)->the_default)
18290 return bfd_set_arch_mach (obfd, bfd_get_arch (ibfd), bfd_get_mach (ibfd));
18291
18292 return TRUE;
18293 }
18294
18295 /* Determine what should happen if the input ARM architecture
18296 does not match the output ARM architecture. */
18297 if (! bfd_arm_merge_machines (ibfd, obfd))
18298 return FALSE;
18299
18300 /* Identical flags must be compatible. */
18301 if (in_flags == out_flags)
18302 return TRUE;
18303
18304 /* Check to see if the input BFD actually contains any sections. If
18305 not, its flags may not have been initialised either, but it
18306 cannot actually cause any incompatiblity. Do not short-circuit
18307 dynamic objects; their section list may be emptied by
18308 elf_link_add_object_symbols.
18309
18310 Also check to see if there are no code sections in the input.
18311 In this case there is no need to check for code specific flags.
18312 XXX - do we need to worry about floating-point format compatability
18313 in data sections ? */
18314 if (!(ibfd->flags & DYNAMIC))
18315 {
18316 bfd_boolean null_input_bfd = TRUE;
18317 bfd_boolean only_data_sections = TRUE;
18318
18319 for (sec = ibfd->sections; sec != NULL; sec = sec->next)
18320 {
18321 /* Ignore synthetic glue sections. */
18322 if (strcmp (sec->name, ".glue_7")
18323 && strcmp (sec->name, ".glue_7t"))
18324 {
18325 if ((bfd_get_section_flags (ibfd, sec)
18326 & (SEC_LOAD | SEC_CODE | SEC_HAS_CONTENTS))
18327 == (SEC_LOAD | SEC_CODE | SEC_HAS_CONTENTS))
99059e56 18328 only_data_sections = FALSE;
21d799b5
NC		 18329
18330 null_input_bfd = FALSE;
18331 break;
18332 }
18333 }
18334
18335 if (null_input_bfd || only_data_sections)
18336 return TRUE;
18337 }
18338
18339 /* Complain about various flag mismatches. */
18340 if (!elf32_arm_versions_compatible (EF_ARM_EABI_VERSION (in_flags),
18341 EF_ARM_EABI_VERSION (out_flags)))
18342 {
18343 _bfd_error_handler
18344 (_("error: Source object %B has EABI version %d, but target %B has EABI version %d"),
18345 ibfd, obfd,
18346 (in_flags & EF_ARM_EABIMASK) >> 24,
18347 (out_flags & EF_ARM_EABIMASK) >> 24);
18348 return FALSE;
18349 }
18350
18351 /* Not sure what needs to be checked for EABI versions >= 1. */
18352 /* VxWorks libraries do not use these flags. */
18353 if (get_elf_backend_data (obfd) != &elf32_arm_vxworks_bed
18354 && get_elf_backend_data (ibfd) != &elf32_arm_vxworks_bed
18355 && EF_ARM_EABI_VERSION (in_flags) == EF_ARM_EABI_UNKNOWN)
18356 {
18357 if ((in_flags & EF_ARM_APCS_26) != (out_flags & EF_ARM_APCS_26))
18358 {
18359 _bfd_error_handler
18360 (_("error: %B is compiled for APCS-%d, whereas target %B uses APCS-%d"),
18361 ibfd, obfd,
18362 in_flags & EF_ARM_APCS_26 ? 26 : 32,
18363 out_flags & EF_ARM_APCS_26 ? 26 : 32);
18364 flags_compatible = FALSE;
18365 }
18366
18367 if ((in_flags & EF_ARM_APCS_FLOAT) != (out_flags & EF_ARM_APCS_FLOAT))
18368 {
18369 if (in_flags & EF_ARM_APCS_FLOAT)
18370 _bfd_error_handler
18371 (_("error: %B passes floats in float registers, whereas %B passes them in integer registers"),
18372 ibfd, obfd);
18373 else
18374 _bfd_error_handler
18375 (_("error: %B passes floats in integer registers, whereas %B passes them in float registers"),
18376 ibfd, obfd);
18377
18378 flags_compatible = FALSE;
18379 }
18380
18381 if ((in_flags & EF_ARM_VFP_FLOAT) != (out_flags & EF_ARM_VFP_FLOAT))
18382 {
18383 if (in_flags & EF_ARM_VFP_FLOAT)
18384 _bfd_error_handler
18385 (_("error: %B uses VFP instructions, whereas %B does not"),
18386 ibfd, obfd);
18387 else
18388 _bfd_error_handler
18389 (_("error: %B uses FPA instructions, whereas %B does not"),
18390 ibfd, obfd);
18391
18392 flags_compatible = FALSE;
18393 }
18394
18395 if ((in_flags & EF_ARM_MAVERICK_FLOAT) != (out_flags & EF_ARM_MAVERICK_FLOAT))
18396 {
18397 if (in_flags & EF_ARM_MAVERICK_FLOAT)
18398 _bfd_error_handler
18399 (_("error: %B uses Maverick instructions, whereas %B does not"),
18400 ibfd, obfd);
18401 else
18402 _bfd_error_handler
18403 (_("error: %B does not use Maverick instructions, whereas %B does"),
18404 ibfd, obfd);
18405
18406 flags_compatible = FALSE;
18407 }
18408
18409#ifdef EF_ARM_SOFT_FLOAT
18410 if ((in_flags & EF_ARM_SOFT_FLOAT) != (out_flags & EF_ARM_SOFT_FLOAT))
18411 {
18412 /* We can allow interworking between code that is VFP format
18413 layout, and uses either soft float or integer regs for
18414 passing floating point arguments and results. We already
18415 know that the APCS_FLOAT flags match; similarly for VFP
18416 flags. */
18417 if ((in_flags & EF_ARM_APCS_FLOAT) != 0
18418 || (in_flags & EF_ARM_VFP_FLOAT) == 0)
18419 {
18420 if (in_flags & EF_ARM_SOFT_FLOAT)
18421 _bfd_error_handler
18422 (_("error: %B uses software FP, whereas %B uses hardware FP"),
18423 ibfd, obfd);
18424 else
18425 _bfd_error_handler
18426 (_("error: %B uses hardware FP, whereas %B uses software FP"),
18427 ibfd, obfd);
18428
18429 flags_compatible = FALSE;
18430 }
18431 }
18432#endif
18433
18434 /* Interworking mismatch is only a warning. */
18435 if ((in_flags & EF_ARM_INTERWORK) != (out_flags & EF_ARM_INTERWORK))
18436 {
18437 if (in_flags & EF_ARM_INTERWORK)
18438 {
18439 _bfd_error_handler
18440 (_("Warning: %B supports interworking, whereas %B does not"),
18441 ibfd, obfd);
18442 }
18443 else
18444 {
18445 _bfd_error_handler
18446 (_("Warning: %B does not support interworking, whereas %B does"),
18447 ibfd, obfd);
18448 }
18449 }
18450 }
18451
18452 return flags_compatible;
18453}
18454
18455
906e58ca 18456/* Symbian OS Targets. */
7f266840 18457
906e58ca 18458#undef TARGET_LITTLE_SYM
6d00b590 18459#define TARGET_LITTLE_SYM arm_elf32_symbian_le_vec
906e58ca 18460#undef TARGET_LITTLE_NAME
7f266840 18461#define TARGET_LITTLE_NAME "elf32-littlearm-symbian"
906e58ca 18462#undef TARGET_BIG_SYM
6d00b590 18463#define TARGET_BIG_SYM arm_elf32_symbian_be_vec
906e58ca 18464#undef TARGET_BIG_NAME
7f266840
DJ		 18465#define TARGET_BIG_NAME "elf32-bigarm-symbian"
18466
18467/* Like elf32_arm_link_hash_table_create -- but overrides
18468 appropriately for Symbian OS. */
906e58ca 18469
7f266840
DJ		 18470static struct bfd_link_hash_table *
18471elf32_arm_symbian_link_hash_table_create (bfd *abfd)
18472{
18473 struct bfd_link_hash_table *ret;
18474
18475 ret = elf32_arm_link_hash_table_create (abfd);
18476 if (ret)
18477 {
18478 struct elf32_arm_link_hash_table *htab
18479 = (struct elf32_arm_link_hash_table *)ret;
18480 /* There is no PLT header for Symbian OS. */
18481 htab->plt_header_size = 0;
95720a86
DJ		 18482 /* The PLT entries are each one instruction and one word. */
18483 htab->plt_entry_size = 4 * ARRAY_SIZE (elf32_arm_symbian_plt_entry);
7f266840 18484 htab->symbian_p = 1;
33bfe774
JB		 18485 /* Symbian uses armv5t or above, so use_blx is always true. */
18486 htab->use_blx = 1;
67687978 18487 htab->root.is_relocatable_executable = 1;
7f266840
DJ		 18488 }
18489 return ret;
906e58ca 18490}
7f266840 18491
b35d266b 18492static const struct bfd_elf_special_section
551b43fd 18493elf32_arm_symbian_special_sections[] =
7f266840 18494{
5cd3778d
MM		 18495 /* In a BPABI executable, the dynamic linking sections do not go in
18496 the loadable read-only segment. The post-linker may wish to
18497 refer to these sections, but they are not part of the final
18498 program image. */
0112cd26
NC		 18499 { STRING_COMMA_LEN (".dynamic"), 0, SHT_DYNAMIC, 0 },
18500 { STRING_COMMA_LEN (".dynstr"), 0, SHT_STRTAB, 0 },
18501 { STRING_COMMA_LEN (".dynsym"), 0, SHT_DYNSYM, 0 },
18502 { STRING_COMMA_LEN (".got"), 0, SHT_PROGBITS, 0 },
18503 { STRING_COMMA_LEN (".hash"), 0, SHT_HASH, 0 },
5cd3778d
MM		 18504 /* These sections do not need to be writable as the SymbianOS
18505 postlinker will arrange things so that no dynamic relocation is
18506 required. */
0112cd26
NC		 18507 { STRING_COMMA_LEN (".init_array"), 0, SHT_INIT_ARRAY, SHF_ALLOC },
18508 { STRING_COMMA_LEN (".fini_array"), 0, SHT_FINI_ARRAY, SHF_ALLOC },
18509 { STRING_COMMA_LEN (".preinit_array"), 0, SHT_PREINIT_ARRAY, SHF_ALLOC },
18510 { NULL, 0, 0, 0, 0 }
7f266840
DJ		 18511};
18512
c3c76620 18513static void
906e58ca 18514elf32_arm_symbian_begin_write_processing (bfd *abfd,
a4fd1a8e 18515 struct bfd_link_info *link_info)
c3c76620
MM		 18516{
18517 /* BPABI objects are never loaded directly by an OS kernel; they are
18518 processed by a postlinker first, into an OS-specific format. If
18519 the D_PAGED bit is set on the file, BFD will align segments on
18520 page boundaries, so that an OS can directly map the file. With
18521 BPABI objects, that just results in wasted space. In addition,
18522 because we clear the D_PAGED bit, map_sections_to_segments will
18523 recognize that the program headers should not be mapped into any
18524 loadable segment. */
18525 abfd->flags &= ~D_PAGED;
906e58ca 18526 elf32_arm_begin_write_processing (abfd, link_info);
c3c76620 18527}
7f266840
DJ		 18528
18529static bfd_boolean
906e58ca 18530elf32_arm_symbian_modify_segment_map (bfd *abfd,
b294bdf8 18531 struct bfd_link_info *info)
7f266840
DJ		 18532{
18533 struct elf_segment_map *m;
18534 asection *dynsec;
18535
7f266840
DJ		 18536 /* BPABI shared libraries and executables should have a PT_DYNAMIC
18537 segment. However, because the .dynamic section is not marked
18538 with SEC_LOAD, the generic ELF code will not create such a
18539 segment. */
18540 dynsec = bfd_get_section_by_name (abfd, ".dynamic");
18541 if (dynsec)
18542 {
12bd6957 18543 for (m = elf_seg_map (abfd); m != NULL; m = m->next)
8ded5a0f
AM		 18544 if (m->p_type == PT_DYNAMIC)
18545 break;
18546
18547 if (m == NULL)
18548 {
18549 m = _bfd_elf_make_dynamic_segment (abfd, dynsec);
12bd6957
AM		 18550 m->next = elf_seg_map (abfd);
18551 elf_seg_map (abfd) = m;
8ded5a0f 18552 }
7f266840
DJ		 18553 }
18554
b294bdf8
MM		 18555 /* Also call the generic arm routine. */
18556 return elf32_arm_modify_segment_map (abfd, info);
7f266840
DJ		 18557}
18558
95720a86
DJ		 18559/* Return address for Ith PLT stub in section PLT, for relocation REL
18560 or (bfd_vma) -1 if it should not be included. */
18561
18562static bfd_vma
18563elf32_arm_symbian_plt_sym_val (bfd_vma i, const asection *plt,
18564 const arelent *rel ATTRIBUTE_UNUSED)
18565{
18566 return plt->vma + 4 * ARRAY_SIZE (elf32_arm_symbian_plt_entry) * i;
18567}
18568
8029a119 18569#undef elf32_bed
7f266840
DJ		 18570#define elf32_bed elf32_arm_symbian_bed
18571
18572/* The dynamic sections are not allocated on SymbianOS; the postlinker
18573 will process them and then discard them. */
906e58ca 18574#undef ELF_DYNAMIC_SEC_FLAGS
7f266840
DJ		 18575#define ELF_DYNAMIC_SEC_FLAGS \
18576 (SEC_HAS_CONTENTS | SEC_IN_MEMORY | SEC_LINKER_CREATED)
18577
00a97672 18578#undef elf_backend_emit_relocs
c3c76620 18579
906e58ca
NC		 18580#undef bfd_elf32_bfd_link_hash_table_create
18581#define bfd_elf32_bfd_link_hash_table_create elf32_arm_symbian_link_hash_table_create
18582#undef elf_backend_special_sections
18583#define elf_backend_special_sections elf32_arm_symbian_special_sections
18584#undef elf_backend_begin_write_processing
18585#define elf_backend_begin_write_processing elf32_arm_symbian_begin_write_processing
18586#undef elf_backend_final_write_processing
18587#define elf_backend_final_write_processing elf32_arm_final_write_processing
18588
18589#undef elf_backend_modify_segment_map
7f266840
DJ		 18590#define elf_backend_modify_segment_map elf32_arm_symbian_modify_segment_map
18591
18592/* There is no .got section for BPABI objects, and hence no header. */
906e58ca 18593#undef elf_backend_got_header_size
7f266840
DJ		 18594#define elf_backend_got_header_size 0
18595
18596/* Similarly, there is no .got.plt section. */
906e58ca 18597#undef elf_backend_want_got_plt
7f266840
DJ		 18598#define elf_backend_want_got_plt 0
18599
906e58ca 18600#undef elf_backend_plt_sym_val
95720a86
DJ		 18601#define elf_backend_plt_sym_val elf32_arm_symbian_plt_sym_val
18602
906e58ca 18603#undef elf_backend_may_use_rel_p
00a97672 18604#define elf_backend_may_use_rel_p 1
906e58ca 18605#undef elf_backend_may_use_rela_p
00a97672 18606#define elf_backend_may_use_rela_p 0
906e58ca 18607#undef elf_backend_default_use_rela_p
00a97672 18608#define elf_backend_default_use_rela_p 0
906e58ca 18609#undef elf_backend_want_plt_sym
00a97672 18610#define elf_backend_want_plt_sym 0
906e58ca 18611#undef ELF_MAXPAGESIZE
00a97672 18612#define ELF_MAXPAGESIZE 0x8000
4e7fd91e 18613
7f266840 18614#include "elf32-target.h"
GDB Binutils - Deliverables
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