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[ARM] Add linker support for ARMv8-R
[deliverable/binutils-gdb.git] / bfd / elf32-arm.c
CommitLineData
252b5132 1/* 32-bit ELF support for ARM
2571583a 2 Copyright (C) 1998-2017 Free Software Foundation, Inc.
252b5132
RH		 3
4 This file is part of BFD, the Binary File Descriptor library.
5
6 This program is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
cd123cb7 8 the Free Software Foundation; either version 3 of the License, or
252b5132
RH		 9 (at your option) any later version.
10
11 This program is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
15
16 You should have received a copy of the GNU General Public License
17 along with this program; if not, write to the Free Software
cd123cb7
NC		 18 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
19 MA 02110-1301, USA. */
252b5132 20
6e6718a3 21#include "sysdep.h"
2468f9c9
PB		 22#include <limits.h>
23
3db64b00 24#include "bfd.h"
6034aab8 25#include "bfd_stdint.h"
00a97672 26#include "libiberty.h"
7f266840
DJ		 27#include "libbfd.h"
28#include "elf-bfd.h"
b38cadfb 29#include "elf-nacl.h"
00a97672 30#include "elf-vxworks.h"
ee065d83 31#include "elf/arm.h"
7f266840 32
00a97672
RS		 33/* Return the relocation section associated with NAME. HTAB is the
34 bfd's elf32_arm_link_hash_entry. */
35#define RELOC_SECTION(HTAB, NAME) \
36 ((HTAB)->use_rel ? ".rel" NAME : ".rela" NAME)
37
38/* Return size of a relocation entry. HTAB is the bfd's
39 elf32_arm_link_hash_entry. */
40#define RELOC_SIZE(HTAB) \
41 ((HTAB)->use_rel \
42 ? sizeof (Elf32_External_Rel) \
43 : sizeof (Elf32_External_Rela))
44
45/* Return function to swap relocations in. HTAB is the bfd's
46 elf32_arm_link_hash_entry. */
47#define SWAP_RELOC_IN(HTAB) \
48 ((HTAB)->use_rel \
49 ? bfd_elf32_swap_reloc_in \
50 : bfd_elf32_swap_reloca_in)
51
52/* Return function to swap relocations out. HTAB is the bfd's
53 elf32_arm_link_hash_entry. */
54#define SWAP_RELOC_OUT(HTAB) \
55 ((HTAB)->use_rel \
56 ? bfd_elf32_swap_reloc_out \
57 : bfd_elf32_swap_reloca_out)
58
7f266840
DJ		 59#define elf_info_to_howto 0
60#define elf_info_to_howto_rel elf32_arm_info_to_howto
61
62#define ARM_ELF_ABI_VERSION 0
63#define ARM_ELF_OS_ABI_VERSION ELFOSABI_ARM
64
79f08007
YZ		 65/* The Adjusted Place, as defined by AAELF. */
66#define Pa(X) ((X) & 0xfffffffc)
67
3e6b1042
DJ		 68static bfd_boolean elf32_arm_write_section (bfd *output_bfd,
69 struct bfd_link_info *link_info,
70 asection *sec,
71 bfd_byte *contents);
72
7f266840
DJ		 73/* Note: code such as elf32_arm_reloc_type_lookup expect to use e.g.
74 R_ARM_PC24 as an index into this, and find the R_ARM_PC24 HOWTO
75 in that slot. */
76
c19d1205 77static reloc_howto_type elf32_arm_howto_table_1[] =
7f266840 78{
8029a119 79 /* No relocation. */
7f266840
DJ		 80 HOWTO (R_ARM_NONE, /* type */
81 0, /* rightshift */
6346d5ca 82 3, /* size (0 = byte, 1 = short, 2 = long) */
7f266840
DJ		 83 0, /* bitsize */
84 FALSE, /* pc_relative */
85 0, /* bitpos */
86 complain_overflow_dont,/* complain_on_overflow */
87 bfd_elf_generic_reloc, /* special_function */
88 "R_ARM_NONE", /* name */
89 FALSE, /* partial_inplace */
90 0, /* src_mask */
91 0, /* dst_mask */
92 FALSE), /* pcrel_offset */
93
94 HOWTO (R_ARM_PC24, /* type */
95 2, /* rightshift */
96 2, /* size (0 = byte, 1 = short, 2 = long) */
97 24, /* bitsize */
98 TRUE, /* pc_relative */
99 0, /* bitpos */
100 complain_overflow_signed,/* complain_on_overflow */
101 bfd_elf_generic_reloc, /* special_function */
102 "R_ARM_PC24", /* name */
103 FALSE, /* partial_inplace */
104 0x00ffffff, /* src_mask */
105 0x00ffffff, /* dst_mask */
106 TRUE), /* pcrel_offset */
107
108 /* 32 bit absolute */
109 HOWTO (R_ARM_ABS32, /* type */
110 0, /* rightshift */
111 2, /* size (0 = byte, 1 = short, 2 = long) */
112 32, /* bitsize */
113 FALSE, /* pc_relative */
114 0, /* bitpos */
115 complain_overflow_bitfield,/* complain_on_overflow */
116 bfd_elf_generic_reloc, /* special_function */
117 "R_ARM_ABS32", /* name */
118 FALSE, /* partial_inplace */
119 0xffffffff, /* src_mask */
120 0xffffffff, /* dst_mask */
121 FALSE), /* pcrel_offset */
122
123 /* standard 32bit pc-relative reloc */
124 HOWTO (R_ARM_REL32, /* type */
125 0, /* rightshift */
126 2, /* size (0 = byte, 1 = short, 2 = long) */
127 32, /* bitsize */
128 TRUE, /* pc_relative */
129 0, /* bitpos */
130 complain_overflow_bitfield,/* complain_on_overflow */
131 bfd_elf_generic_reloc, /* special_function */
132 "R_ARM_REL32", /* name */
133 FALSE, /* partial_inplace */
134 0xffffffff, /* src_mask */
135 0xffffffff, /* dst_mask */
136 TRUE), /* pcrel_offset */
137
c19d1205 138 /* 8 bit absolute - R_ARM_LDR_PC_G0 in AAELF */
4962c51a 139 HOWTO (R_ARM_LDR_PC_G0, /* type */
7f266840
DJ		 140 0, /* rightshift */
141 0, /* size (0 = byte, 1 = short, 2 = long) */
4962c51a
MS		 142 32, /* bitsize */
143 TRUE, /* pc_relative */
7f266840 144 0, /* bitpos */
4962c51a 145 complain_overflow_dont,/* complain_on_overflow */
7f266840 146 bfd_elf_generic_reloc, /* special_function */
4962c51a 147 "R_ARM_LDR_PC_G0", /* name */
7f266840 148 FALSE, /* partial_inplace */
4962c51a
MS		 149 0xffffffff, /* src_mask */
150 0xffffffff, /* dst_mask */
151 TRUE), /* pcrel_offset */
7f266840
DJ		 152
153 /* 16 bit absolute */
154 HOWTO (R_ARM_ABS16, /* type */
155 0, /* rightshift */
156 1, /* size (0 = byte, 1 = short, 2 = long) */
157 16, /* bitsize */
158 FALSE, /* pc_relative */
159 0, /* bitpos */
160 complain_overflow_bitfield,/* complain_on_overflow */
161 bfd_elf_generic_reloc, /* special_function */
162 "R_ARM_ABS16", /* name */
163 FALSE, /* partial_inplace */
164 0x0000ffff, /* src_mask */
165 0x0000ffff, /* dst_mask */
166 FALSE), /* pcrel_offset */
167
168 /* 12 bit absolute */
169 HOWTO (R_ARM_ABS12, /* type */
170 0, /* rightshift */
171 2, /* size (0 = byte, 1 = short, 2 = long) */
172 12, /* bitsize */
173 FALSE, /* pc_relative */
174 0, /* bitpos */
175 complain_overflow_bitfield,/* complain_on_overflow */
176 bfd_elf_generic_reloc, /* special_function */
177 "R_ARM_ABS12", /* name */
178 FALSE, /* partial_inplace */
00a97672
RS		 179 0x00000fff, /* src_mask */
180 0x00000fff, /* dst_mask */
7f266840
DJ		 181 FALSE), /* pcrel_offset */
182
183 HOWTO (R_ARM_THM_ABS5, /* type */
184 6, /* rightshift */
185 1, /* size (0 = byte, 1 = short, 2 = long) */
186 5, /* bitsize */
187 FALSE, /* pc_relative */
188 0, /* bitpos */
189 complain_overflow_bitfield,/* complain_on_overflow */
190 bfd_elf_generic_reloc, /* special_function */
191 "R_ARM_THM_ABS5", /* name */
192 FALSE, /* partial_inplace */
193 0x000007e0, /* src_mask */
194 0x000007e0, /* dst_mask */
195 FALSE), /* pcrel_offset */
196
197 /* 8 bit absolute */
198 HOWTO (R_ARM_ABS8, /* type */
199 0, /* rightshift */
200 0, /* size (0 = byte, 1 = short, 2 = long) */
201 8, /* bitsize */
202 FALSE, /* pc_relative */
203 0, /* bitpos */
204 complain_overflow_bitfield,/* complain_on_overflow */
205 bfd_elf_generic_reloc, /* special_function */
206 "R_ARM_ABS8", /* name */
207 FALSE, /* partial_inplace */
208 0x000000ff, /* src_mask */
209 0x000000ff, /* dst_mask */
210 FALSE), /* pcrel_offset */
211
212 HOWTO (R_ARM_SBREL32, /* type */
213 0, /* rightshift */
214 2, /* size (0 = byte, 1 = short, 2 = long) */
215 32, /* bitsize */
216 FALSE, /* pc_relative */
217 0, /* bitpos */
218 complain_overflow_dont,/* complain_on_overflow */
219 bfd_elf_generic_reloc, /* special_function */
220 "R_ARM_SBREL32", /* name */
221 FALSE, /* partial_inplace */
222 0xffffffff, /* src_mask */
223 0xffffffff, /* dst_mask */
224 FALSE), /* pcrel_offset */
225
c19d1205 226 HOWTO (R_ARM_THM_CALL, /* type */
7f266840
DJ		 227 1, /* rightshift */
228 2, /* size (0 = byte, 1 = short, 2 = long) */
f6ebfac0 229 24, /* bitsize */
7f266840
DJ		 230 TRUE, /* pc_relative */
231 0, /* bitpos */
232 complain_overflow_signed,/* complain_on_overflow */
233 bfd_elf_generic_reloc, /* special_function */
c19d1205 234 "R_ARM_THM_CALL", /* name */
7f266840 235 FALSE, /* partial_inplace */
7f6ab9f8
AM		 236 0x07ff2fff, /* src_mask */
237 0x07ff2fff, /* dst_mask */
7f266840
DJ		 238 TRUE), /* pcrel_offset */
239
240 HOWTO (R_ARM_THM_PC8, /* type */
241 1, /* rightshift */
242 1, /* size (0 = byte, 1 = short, 2 = long) */
243 8, /* bitsize */
244 TRUE, /* pc_relative */
245 0, /* bitpos */
246 complain_overflow_signed,/* complain_on_overflow */
247 bfd_elf_generic_reloc, /* special_function */
248 "R_ARM_THM_PC8", /* name */
249 FALSE, /* partial_inplace */
250 0x000000ff, /* src_mask */
251 0x000000ff, /* dst_mask */
252 TRUE), /* pcrel_offset */
253
c19d1205 254 HOWTO (R_ARM_BREL_ADJ, /* type */
7f266840
DJ		 255 1, /* rightshift */
256 1, /* size (0 = byte, 1 = short, 2 = long) */
c19d1205
ZW		 257 32, /* bitsize */
258 FALSE, /* pc_relative */
7f266840
DJ		 259 0, /* bitpos */
260 complain_overflow_signed,/* complain_on_overflow */
261 bfd_elf_generic_reloc, /* special_function */
c19d1205 262 "R_ARM_BREL_ADJ", /* name */
7f266840 263 FALSE, /* partial_inplace */
c19d1205
ZW		 264 0xffffffff, /* src_mask */
265 0xffffffff, /* dst_mask */
266 FALSE), /* pcrel_offset */
7f266840 267
0855e32b 268 HOWTO (R_ARM_TLS_DESC, /* type */
7f266840 269 0, /* rightshift */
0855e32b
NS		 270 2, /* size (0 = byte, 1 = short, 2 = long) */
271 32, /* bitsize */
7f266840
DJ		 272 FALSE, /* pc_relative */
273 0, /* bitpos */
0855e32b 274 complain_overflow_bitfield,/* complain_on_overflow */
7f266840 275 bfd_elf_generic_reloc, /* special_function */
0855e32b 276 "R_ARM_TLS_DESC", /* name */
7f266840 277 FALSE, /* partial_inplace */
0855e32b
NS		 278 0xffffffff, /* src_mask */
279 0xffffffff, /* dst_mask */
7f266840
DJ		 280 FALSE), /* pcrel_offset */
281
282 HOWTO (R_ARM_THM_SWI8, /* type */
283 0, /* rightshift */
284 0, /* size (0 = byte, 1 = short, 2 = long) */
285 0, /* bitsize */
286 FALSE, /* pc_relative */
287 0, /* bitpos */
288 complain_overflow_signed,/* complain_on_overflow */
289 bfd_elf_generic_reloc, /* special_function */
290 "R_ARM_SWI8", /* name */
291 FALSE, /* partial_inplace */
292 0x00000000, /* src_mask */
293 0x00000000, /* dst_mask */
294 FALSE), /* pcrel_offset */
295
296 /* BLX instruction for the ARM. */
297 HOWTO (R_ARM_XPC25, /* type */
298 2, /* rightshift */
299 2, /* size (0 = byte, 1 = short, 2 = long) */
7f6ab9f8 300 24, /* bitsize */
7f266840
DJ		 301 TRUE, /* pc_relative */
302 0, /* bitpos */
303 complain_overflow_signed,/* complain_on_overflow */
304 bfd_elf_generic_reloc, /* special_function */
305 "R_ARM_XPC25", /* name */
306 FALSE, /* partial_inplace */
307 0x00ffffff, /* src_mask */
308 0x00ffffff, /* dst_mask */
309 TRUE), /* pcrel_offset */
310
311 /* BLX instruction for the Thumb. */
312 HOWTO (R_ARM_THM_XPC22, /* type */
313 2, /* rightshift */
314 2, /* size (0 = byte, 1 = short, 2 = long) */
7f6ab9f8 315 24, /* bitsize */
7f266840
DJ		 316 TRUE, /* pc_relative */
317 0, /* bitpos */
318 complain_overflow_signed,/* complain_on_overflow */
319 bfd_elf_generic_reloc, /* special_function */
320 "R_ARM_THM_XPC22", /* name */
321 FALSE, /* partial_inplace */
7f6ab9f8
AM		 322 0x07ff2fff, /* src_mask */
323 0x07ff2fff, /* dst_mask */
7f266840
DJ		 324 TRUE), /* pcrel_offset */
325
ba93b8ac 326 /* Dynamic TLS relocations. */
7f266840 327
ba93b8ac 328 HOWTO (R_ARM_TLS_DTPMOD32, /* type */
99059e56
RM		 329 0, /* rightshift */
330 2, /* size (0 = byte, 1 = short, 2 = long) */
331 32, /* bitsize */
332 FALSE, /* pc_relative */
333 0, /* bitpos */
334 complain_overflow_bitfield,/* complain_on_overflow */
335 bfd_elf_generic_reloc, /* special_function */
336 "R_ARM_TLS_DTPMOD32", /* name */
337 TRUE, /* partial_inplace */
338 0xffffffff, /* src_mask */
339 0xffffffff, /* dst_mask */
340 FALSE), /* pcrel_offset */
7f266840 341
ba93b8ac 342 HOWTO (R_ARM_TLS_DTPOFF32, /* type */
99059e56
RM		 343 0, /* rightshift */
344 2, /* size (0 = byte, 1 = short, 2 = long) */
345 32, /* bitsize */
346 FALSE, /* pc_relative */
347 0, /* bitpos */
348 complain_overflow_bitfield,/* complain_on_overflow */
349 bfd_elf_generic_reloc, /* special_function */
350 "R_ARM_TLS_DTPOFF32", /* name */
351 TRUE, /* partial_inplace */
352 0xffffffff, /* src_mask */
353 0xffffffff, /* dst_mask */
354 FALSE), /* pcrel_offset */
7f266840 355
ba93b8ac 356 HOWTO (R_ARM_TLS_TPOFF32, /* type */
99059e56
RM		 357 0, /* rightshift */
358 2, /* size (0 = byte, 1 = short, 2 = long) */
359 32, /* bitsize */
360 FALSE, /* pc_relative */
361 0, /* bitpos */
362 complain_overflow_bitfield,/* complain_on_overflow */
363 bfd_elf_generic_reloc, /* special_function */
364 "R_ARM_TLS_TPOFF32", /* name */
365 TRUE, /* partial_inplace */
366 0xffffffff, /* src_mask */
367 0xffffffff, /* dst_mask */
368 FALSE), /* pcrel_offset */
7f266840
DJ		 369
370 /* Relocs used in ARM Linux */
371
372 HOWTO (R_ARM_COPY, /* type */
99059e56
RM		 373 0, /* rightshift */
374 2, /* size (0 = byte, 1 = short, 2 = long) */
375 32, /* bitsize */
376 FALSE, /* pc_relative */
377 0, /* bitpos */
378 complain_overflow_bitfield,/* complain_on_overflow */
379 bfd_elf_generic_reloc, /* special_function */
380 "R_ARM_COPY", /* name */
381 TRUE, /* partial_inplace */
382 0xffffffff, /* src_mask */
383 0xffffffff, /* dst_mask */
384 FALSE), /* pcrel_offset */
7f266840
DJ		 385
386 HOWTO (R_ARM_GLOB_DAT, /* type */
99059e56
RM		 387 0, /* rightshift */
388 2, /* size (0 = byte, 1 = short, 2 = long) */
389 32, /* bitsize */
390 FALSE, /* pc_relative */
391 0, /* bitpos */
392 complain_overflow_bitfield,/* complain_on_overflow */
393 bfd_elf_generic_reloc, /* special_function */
394 "R_ARM_GLOB_DAT", /* name */
395 TRUE, /* partial_inplace */
396 0xffffffff, /* src_mask */
397 0xffffffff, /* dst_mask */
398 FALSE), /* pcrel_offset */
7f266840
DJ		 399
400 HOWTO (R_ARM_JUMP_SLOT, /* type */
99059e56
RM		 401 0, /* rightshift */
402 2, /* size (0 = byte, 1 = short, 2 = long) */
403 32, /* bitsize */
404 FALSE, /* pc_relative */
405 0, /* bitpos */
406 complain_overflow_bitfield,/* complain_on_overflow */
407 bfd_elf_generic_reloc, /* special_function */
408 "R_ARM_JUMP_SLOT", /* name */
409 TRUE, /* partial_inplace */
410 0xffffffff, /* src_mask */
411 0xffffffff, /* dst_mask */
412 FALSE), /* pcrel_offset */
7f266840
DJ		 413
414 HOWTO (R_ARM_RELATIVE, /* type */
99059e56
RM		 415 0, /* rightshift */
416 2, /* size (0 = byte, 1 = short, 2 = long) */
417 32, /* bitsize */
418 FALSE, /* pc_relative */
419 0, /* bitpos */
420 complain_overflow_bitfield,/* complain_on_overflow */
421 bfd_elf_generic_reloc, /* special_function */
422 "R_ARM_RELATIVE", /* name */
423 TRUE, /* partial_inplace */
424 0xffffffff, /* src_mask */
425 0xffffffff, /* dst_mask */
426 FALSE), /* pcrel_offset */
7f266840 427
c19d1205 428 HOWTO (R_ARM_GOTOFF32, /* type */
99059e56
RM		 429 0, /* rightshift */
430 2, /* size (0 = byte, 1 = short, 2 = long) */
431 32, /* bitsize */
432 FALSE, /* pc_relative */
433 0, /* bitpos */
434 complain_overflow_bitfield,/* complain_on_overflow */
435 bfd_elf_generic_reloc, /* special_function */
436 "R_ARM_GOTOFF32", /* name */
437 TRUE, /* partial_inplace */
438 0xffffffff, /* src_mask */
439 0xffffffff, /* dst_mask */
440 FALSE), /* pcrel_offset */
7f266840
DJ		 441
442 HOWTO (R_ARM_GOTPC, /* type */
99059e56
RM		 443 0, /* rightshift */
444 2, /* size (0 = byte, 1 = short, 2 = long) */
445 32, /* bitsize */
446 TRUE, /* pc_relative */
447 0, /* bitpos */
448 complain_overflow_bitfield,/* complain_on_overflow */
449 bfd_elf_generic_reloc, /* special_function */
450 "R_ARM_GOTPC", /* name */
451 TRUE, /* partial_inplace */
452 0xffffffff, /* src_mask */
453 0xffffffff, /* dst_mask */
454 TRUE), /* pcrel_offset */
7f266840
DJ		 455
456 HOWTO (R_ARM_GOT32, /* type */
99059e56
RM		 457 0, /* rightshift */
458 2, /* size (0 = byte, 1 = short, 2 = long) */
459 32, /* bitsize */
460 FALSE, /* pc_relative */
461 0, /* bitpos */
462 complain_overflow_bitfield,/* complain_on_overflow */
463 bfd_elf_generic_reloc, /* special_function */
464 "R_ARM_GOT32", /* name */
465 TRUE, /* partial_inplace */
466 0xffffffff, /* src_mask */
467 0xffffffff, /* dst_mask */
468 FALSE), /* pcrel_offset */
7f266840
DJ		 469
470 HOWTO (R_ARM_PLT32, /* type */
99059e56
RM		 471 2, /* rightshift */
472 2, /* size (0 = byte, 1 = short, 2 = long) */
473 24, /* bitsize */
474 TRUE, /* pc_relative */
475 0, /* bitpos */
476 complain_overflow_bitfield,/* complain_on_overflow */
477 bfd_elf_generic_reloc, /* special_function */
478 "R_ARM_PLT32", /* name */
479 FALSE, /* partial_inplace */
480 0x00ffffff, /* src_mask */
481 0x00ffffff, /* dst_mask */
482 TRUE), /* pcrel_offset */
7f266840
DJ		 483
484 HOWTO (R_ARM_CALL, /* type */
485 2, /* rightshift */
486 2, /* size (0 = byte, 1 = short, 2 = long) */
487 24, /* bitsize */
488 TRUE, /* pc_relative */
489 0, /* bitpos */
490 complain_overflow_signed,/* complain_on_overflow */
491 bfd_elf_generic_reloc, /* special_function */
492 "R_ARM_CALL", /* name */
493 FALSE, /* partial_inplace */
494 0x00ffffff, /* src_mask */
495 0x00ffffff, /* dst_mask */
496 TRUE), /* pcrel_offset */
497
498 HOWTO (R_ARM_JUMP24, /* type */
499 2, /* rightshift */
500 2, /* size (0 = byte, 1 = short, 2 = long) */
501 24, /* bitsize */
502 TRUE, /* pc_relative */
503 0, /* bitpos */
504 complain_overflow_signed,/* complain_on_overflow */
505 bfd_elf_generic_reloc, /* special_function */
506 "R_ARM_JUMP24", /* name */
507 FALSE, /* partial_inplace */
508 0x00ffffff, /* src_mask */
509 0x00ffffff, /* dst_mask */
510 TRUE), /* pcrel_offset */
511
c19d1205
ZW		 512 HOWTO (R_ARM_THM_JUMP24, /* type */
513 1, /* rightshift */
514 2, /* size (0 = byte, 1 = short, 2 = long) */
515 24, /* bitsize */
516 TRUE, /* pc_relative */
7f266840 517 0, /* bitpos */
c19d1205 518 complain_overflow_signed,/* complain_on_overflow */
7f266840 519 bfd_elf_generic_reloc, /* special_function */
c19d1205 520 "R_ARM_THM_JUMP24", /* name */
7f266840 521 FALSE, /* partial_inplace */
c19d1205
ZW		 522 0x07ff2fff, /* src_mask */
523 0x07ff2fff, /* dst_mask */
524 TRUE), /* pcrel_offset */
7f266840 525
c19d1205 526 HOWTO (R_ARM_BASE_ABS, /* type */
7f266840 527 0, /* rightshift */
c19d1205
ZW		 528 2, /* size (0 = byte, 1 = short, 2 = long) */
529 32, /* bitsize */
7f266840
DJ		 530 FALSE, /* pc_relative */
531 0, /* bitpos */
532 complain_overflow_dont,/* complain_on_overflow */
533 bfd_elf_generic_reloc, /* special_function */
c19d1205 534 "R_ARM_BASE_ABS", /* name */
7f266840 535 FALSE, /* partial_inplace */
c19d1205
ZW		 536 0xffffffff, /* src_mask */
537 0xffffffff, /* dst_mask */
7f266840
DJ		 538 FALSE), /* pcrel_offset */
539
540 HOWTO (R_ARM_ALU_PCREL7_0, /* type */
541 0, /* rightshift */
542 2, /* size (0 = byte, 1 = short, 2 = long) */
543 12, /* bitsize */
544 TRUE, /* pc_relative */
545 0, /* bitpos */
546 complain_overflow_dont,/* complain_on_overflow */
547 bfd_elf_generic_reloc, /* special_function */
548 "R_ARM_ALU_PCREL_7_0", /* name */
549 FALSE, /* partial_inplace */
550 0x00000fff, /* src_mask */
551 0x00000fff, /* dst_mask */
552 TRUE), /* pcrel_offset */
553
554 HOWTO (R_ARM_ALU_PCREL15_8, /* type */
555 0, /* rightshift */
556 2, /* size (0 = byte, 1 = short, 2 = long) */
557 12, /* bitsize */
558 TRUE, /* pc_relative */
559 8, /* bitpos */
560 complain_overflow_dont,/* complain_on_overflow */
561 bfd_elf_generic_reloc, /* special_function */
562 "R_ARM_ALU_PCREL_15_8",/* name */
563 FALSE, /* partial_inplace */
564 0x00000fff, /* src_mask */
565 0x00000fff, /* dst_mask */
566 TRUE), /* pcrel_offset */
567
568 HOWTO (R_ARM_ALU_PCREL23_15, /* type */
569 0, /* rightshift */
570 2, /* size (0 = byte, 1 = short, 2 = long) */
571 12, /* bitsize */
572 TRUE, /* pc_relative */
573 16, /* bitpos */
574 complain_overflow_dont,/* complain_on_overflow */
575 bfd_elf_generic_reloc, /* special_function */
576 "R_ARM_ALU_PCREL_23_15",/* name */
577 FALSE, /* partial_inplace */
578 0x00000fff, /* src_mask */
579 0x00000fff, /* dst_mask */
580 TRUE), /* pcrel_offset */
581
582 HOWTO (R_ARM_LDR_SBREL_11_0, /* type */
583 0, /* rightshift */
584 2, /* size (0 = byte, 1 = short, 2 = long) */
585 12, /* bitsize */
586 FALSE, /* pc_relative */
587 0, /* bitpos */
588 complain_overflow_dont,/* complain_on_overflow */
589 bfd_elf_generic_reloc, /* special_function */
590 "R_ARM_LDR_SBREL_11_0",/* name */
591 FALSE, /* partial_inplace */
592 0x00000fff, /* src_mask */
593 0x00000fff, /* dst_mask */
594 FALSE), /* pcrel_offset */
595
596 HOWTO (R_ARM_ALU_SBREL_19_12, /* type */
597 0, /* rightshift */
598 2, /* size (0 = byte, 1 = short, 2 = long) */
599 8, /* bitsize */
600 FALSE, /* pc_relative */
601 12, /* bitpos */
602 complain_overflow_dont,/* complain_on_overflow */
603 bfd_elf_generic_reloc, /* special_function */
604 "R_ARM_ALU_SBREL_19_12",/* name */
605 FALSE, /* partial_inplace */
606 0x000ff000, /* src_mask */
607 0x000ff000, /* dst_mask */
608 FALSE), /* pcrel_offset */
609
610 HOWTO (R_ARM_ALU_SBREL_27_20, /* type */
611 0, /* rightshift */
612 2, /* size (0 = byte, 1 = short, 2 = long) */
613 8, /* bitsize */
614 FALSE, /* pc_relative */
615 20, /* bitpos */
616 complain_overflow_dont,/* complain_on_overflow */
617 bfd_elf_generic_reloc, /* special_function */
618 "R_ARM_ALU_SBREL_27_20",/* name */
619 FALSE, /* partial_inplace */
620 0x0ff00000, /* src_mask */
621 0x0ff00000, /* dst_mask */
622 FALSE), /* pcrel_offset */
623
624 HOWTO (R_ARM_TARGET1, /* type */
625 0, /* rightshift */
626 2, /* size (0 = byte, 1 = short, 2 = long) */
627 32, /* bitsize */
628 FALSE, /* pc_relative */
629 0, /* bitpos */
630 complain_overflow_dont,/* complain_on_overflow */
631 bfd_elf_generic_reloc, /* special_function */
632 "R_ARM_TARGET1", /* name */
633 FALSE, /* partial_inplace */
634 0xffffffff, /* src_mask */
635 0xffffffff, /* dst_mask */
636 FALSE), /* pcrel_offset */
637
638 HOWTO (R_ARM_ROSEGREL32, /* type */
639 0, /* rightshift */
640 2, /* size (0 = byte, 1 = short, 2 = long) */
641 32, /* bitsize */
642 FALSE, /* pc_relative */
643 0, /* bitpos */
644 complain_overflow_dont,/* complain_on_overflow */
645 bfd_elf_generic_reloc, /* special_function */
646 "R_ARM_ROSEGREL32", /* name */
647 FALSE, /* partial_inplace */
648 0xffffffff, /* src_mask */
649 0xffffffff, /* dst_mask */
650 FALSE), /* pcrel_offset */
651
652 HOWTO (R_ARM_V4BX, /* type */
653 0, /* rightshift */
654 2, /* size (0 = byte, 1 = short, 2 = long) */
655 32, /* bitsize */
656 FALSE, /* pc_relative */
657 0, /* bitpos */
658 complain_overflow_dont,/* complain_on_overflow */
659 bfd_elf_generic_reloc, /* special_function */
660 "R_ARM_V4BX", /* name */
661 FALSE, /* partial_inplace */
662 0xffffffff, /* src_mask */
663 0xffffffff, /* dst_mask */
664 FALSE), /* pcrel_offset */
665
666 HOWTO (R_ARM_TARGET2, /* type */
667 0, /* rightshift */
668 2, /* size (0 = byte, 1 = short, 2 = long) */
669 32, /* bitsize */
670 FALSE, /* pc_relative */
671 0, /* bitpos */
672 complain_overflow_signed,/* complain_on_overflow */
673 bfd_elf_generic_reloc, /* special_function */
674 "R_ARM_TARGET2", /* name */
675 FALSE, /* partial_inplace */
676 0xffffffff, /* src_mask */
677 0xffffffff, /* dst_mask */
678 TRUE), /* pcrel_offset */
679
680 HOWTO (R_ARM_PREL31, /* type */
681 0, /* rightshift */
682 2, /* size (0 = byte, 1 = short, 2 = long) */
683 31, /* bitsize */
684 TRUE, /* pc_relative */
685 0, /* bitpos */
686 complain_overflow_signed,/* complain_on_overflow */
687 bfd_elf_generic_reloc, /* special_function */
688 "R_ARM_PREL31", /* name */
689 FALSE, /* partial_inplace */
690 0x7fffffff, /* src_mask */
691 0x7fffffff, /* dst_mask */
692 TRUE), /* pcrel_offset */
c19d1205
ZW		 693
694 HOWTO (R_ARM_MOVW_ABS_NC, /* type */
695 0, /* rightshift */
696 2, /* size (0 = byte, 1 = short, 2 = long) */
697 16, /* bitsize */
698 FALSE, /* pc_relative */
699 0, /* bitpos */
700 complain_overflow_dont,/* complain_on_overflow */
701 bfd_elf_generic_reloc, /* special_function */
702 "R_ARM_MOVW_ABS_NC", /* name */
703 FALSE, /* partial_inplace */
39623e12
PB		 704 0x000f0fff, /* src_mask */
705 0x000f0fff, /* dst_mask */
c19d1205
ZW		 706 FALSE), /* pcrel_offset */
707
708 HOWTO (R_ARM_MOVT_ABS, /* type */
709 0, /* rightshift */
710 2, /* size (0 = byte, 1 = short, 2 = long) */
711 16, /* bitsize */
712 FALSE, /* pc_relative */
713 0, /* bitpos */
714 complain_overflow_bitfield,/* complain_on_overflow */
715 bfd_elf_generic_reloc, /* special_function */
716 "R_ARM_MOVT_ABS", /* name */
717 FALSE, /* partial_inplace */
39623e12
PB		 718 0x000f0fff, /* src_mask */
719 0x000f0fff, /* dst_mask */
c19d1205
ZW		 720 FALSE), /* pcrel_offset */
721
722 HOWTO (R_ARM_MOVW_PREL_NC, /* type */
723 0, /* rightshift */
724 2, /* size (0 = byte, 1 = short, 2 = long) */
725 16, /* bitsize */
726 TRUE, /* pc_relative */
727 0, /* bitpos */
728 complain_overflow_dont,/* complain_on_overflow */
729 bfd_elf_generic_reloc, /* special_function */
730 "R_ARM_MOVW_PREL_NC", /* name */
731 FALSE, /* partial_inplace */
39623e12
PB		 732 0x000f0fff, /* src_mask */
733 0x000f0fff, /* dst_mask */
c19d1205
ZW		 734 TRUE), /* pcrel_offset */
735
736 HOWTO (R_ARM_MOVT_PREL, /* type */
737 0, /* rightshift */
738 2, /* size (0 = byte, 1 = short, 2 = long) */
739 16, /* bitsize */
740 TRUE, /* pc_relative */
741 0, /* bitpos */
742 complain_overflow_bitfield,/* complain_on_overflow */
743 bfd_elf_generic_reloc, /* special_function */
744 "R_ARM_MOVT_PREL", /* name */
745 FALSE, /* partial_inplace */
39623e12
PB		 746 0x000f0fff, /* src_mask */
747 0x000f0fff, /* dst_mask */
c19d1205
ZW		 748 TRUE), /* pcrel_offset */
749
750 HOWTO (R_ARM_THM_MOVW_ABS_NC, /* type */
751 0, /* rightshift */
752 2, /* size (0 = byte, 1 = short, 2 = long) */
753 16, /* bitsize */
754 FALSE, /* pc_relative */
755 0, /* bitpos */
756 complain_overflow_dont,/* complain_on_overflow */
757 bfd_elf_generic_reloc, /* special_function */
758 "R_ARM_THM_MOVW_ABS_NC",/* name */
759 FALSE, /* partial_inplace */
760 0x040f70ff, /* src_mask */
761 0x040f70ff, /* dst_mask */
762 FALSE), /* pcrel_offset */
763
764 HOWTO (R_ARM_THM_MOVT_ABS, /* type */
765 0, /* rightshift */
766 2, /* size (0 = byte, 1 = short, 2 = long) */
767 16, /* bitsize */
768 FALSE, /* pc_relative */
769 0, /* bitpos */
770 complain_overflow_bitfield,/* complain_on_overflow */
771 bfd_elf_generic_reloc, /* special_function */
772 "R_ARM_THM_MOVT_ABS", /* name */
773 FALSE, /* partial_inplace */
774 0x040f70ff, /* src_mask */
775 0x040f70ff, /* dst_mask */
776 FALSE), /* pcrel_offset */
777
778 HOWTO (R_ARM_THM_MOVW_PREL_NC,/* type */
779 0, /* rightshift */
780 2, /* size (0 = byte, 1 = short, 2 = long) */
781 16, /* bitsize */
782 TRUE, /* pc_relative */
783 0, /* bitpos */
784 complain_overflow_dont,/* complain_on_overflow */
785 bfd_elf_generic_reloc, /* special_function */
786 "R_ARM_THM_MOVW_PREL_NC",/* name */
787 FALSE, /* partial_inplace */
788 0x040f70ff, /* src_mask */
789 0x040f70ff, /* dst_mask */
790 TRUE), /* pcrel_offset */
791
792 HOWTO (R_ARM_THM_MOVT_PREL, /* type */
793 0, /* rightshift */
794 2, /* size (0 = byte, 1 = short, 2 = long) */
795 16, /* bitsize */
796 TRUE, /* pc_relative */
797 0, /* bitpos */
798 complain_overflow_bitfield,/* complain_on_overflow */
799 bfd_elf_generic_reloc, /* special_function */
800 "R_ARM_THM_MOVT_PREL", /* name */
801 FALSE, /* partial_inplace */
802 0x040f70ff, /* src_mask */
803 0x040f70ff, /* dst_mask */
804 TRUE), /* pcrel_offset */
805
806 HOWTO (R_ARM_THM_JUMP19, /* type */
807 1, /* rightshift */
808 2, /* size (0 = byte, 1 = short, 2 = long) */
809 19, /* bitsize */
810 TRUE, /* pc_relative */
811 0, /* bitpos */
812 complain_overflow_signed,/* complain_on_overflow */
813 bfd_elf_generic_reloc, /* special_function */
814 "R_ARM_THM_JUMP19", /* name */
815 FALSE, /* partial_inplace */
816 0x043f2fff, /* src_mask */
817 0x043f2fff, /* dst_mask */
818 TRUE), /* pcrel_offset */
819
820 HOWTO (R_ARM_THM_JUMP6, /* type */
821 1, /* rightshift */
822 1, /* size (0 = byte, 1 = short, 2 = long) */
823 6, /* bitsize */
824 TRUE, /* pc_relative */
825 0, /* bitpos */
826 complain_overflow_unsigned,/* complain_on_overflow */
827 bfd_elf_generic_reloc, /* special_function */
828 "R_ARM_THM_JUMP6", /* name */
829 FALSE, /* partial_inplace */
830 0x02f8, /* src_mask */
831 0x02f8, /* dst_mask */
832 TRUE), /* pcrel_offset */
833
834 /* These are declared as 13-bit signed relocations because we can
835 address -4095 .. 4095(base) by altering ADDW to SUBW or vice
836 versa. */
837 HOWTO (R_ARM_THM_ALU_PREL_11_0,/* type */
838 0, /* rightshift */
839 2, /* size (0 = byte, 1 = short, 2 = long) */
840 13, /* bitsize */
841 TRUE, /* pc_relative */
842 0, /* bitpos */
2cab6cc3 843 complain_overflow_dont,/* complain_on_overflow */
c19d1205
ZW		 844 bfd_elf_generic_reloc, /* special_function */
845 "R_ARM_THM_ALU_PREL_11_0",/* name */
846 FALSE, /* partial_inplace */
2cab6cc3
MS		 847 0xffffffff, /* src_mask */
848 0xffffffff, /* dst_mask */
c19d1205
ZW		 849 TRUE), /* pcrel_offset */
850
851 HOWTO (R_ARM_THM_PC12, /* type */
852 0, /* rightshift */
853 2, /* size (0 = byte, 1 = short, 2 = long) */
854 13, /* bitsize */
855 TRUE, /* pc_relative */
856 0, /* bitpos */
2cab6cc3 857 complain_overflow_dont,/* complain_on_overflow */
c19d1205
ZW		 858 bfd_elf_generic_reloc, /* special_function */
859 "R_ARM_THM_PC12", /* name */
860 FALSE, /* partial_inplace */
2cab6cc3
MS		 861 0xffffffff, /* src_mask */
862 0xffffffff, /* dst_mask */
c19d1205
ZW		 863 TRUE), /* pcrel_offset */
864
865 HOWTO (R_ARM_ABS32_NOI, /* type */
866 0, /* rightshift */
867 2, /* size (0 = byte, 1 = short, 2 = long) */
868 32, /* bitsize */
869 FALSE, /* pc_relative */
870 0, /* bitpos */
871 complain_overflow_dont,/* complain_on_overflow */
872 bfd_elf_generic_reloc, /* special_function */
873 "R_ARM_ABS32_NOI", /* name */
874 FALSE, /* partial_inplace */
875 0xffffffff, /* src_mask */
876 0xffffffff, /* dst_mask */
877 FALSE), /* pcrel_offset */
878
879 HOWTO (R_ARM_REL32_NOI, /* type */
880 0, /* rightshift */
881 2, /* size (0 = byte, 1 = short, 2 = long) */
882 32, /* bitsize */
883 TRUE, /* pc_relative */
884 0, /* bitpos */
885 complain_overflow_dont,/* complain_on_overflow */
886 bfd_elf_generic_reloc, /* special_function */
887 "R_ARM_REL32_NOI", /* name */
888 FALSE, /* partial_inplace */
889 0xffffffff, /* src_mask */
890 0xffffffff, /* dst_mask */
891 FALSE), /* pcrel_offset */
7f266840 892
4962c51a
MS		 893 /* Group relocations. */
894
895 HOWTO (R_ARM_ALU_PC_G0_NC, /* type */
896 0, /* rightshift */
897 2, /* size (0 = byte, 1 = short, 2 = long) */
898 32, /* bitsize */
899 TRUE, /* pc_relative */
900 0, /* bitpos */
901 complain_overflow_dont,/* complain_on_overflow */
902 bfd_elf_generic_reloc, /* special_function */
903 "R_ARM_ALU_PC_G0_NC", /* name */
904 FALSE, /* partial_inplace */
905 0xffffffff, /* src_mask */
906 0xffffffff, /* dst_mask */
907 TRUE), /* pcrel_offset */
908
909 HOWTO (R_ARM_ALU_PC_G0, /* type */
910 0, /* rightshift */
911 2, /* size (0 = byte, 1 = short, 2 = long) */
912 32, /* bitsize */
913 TRUE, /* pc_relative */
914 0, /* bitpos */
915 complain_overflow_dont,/* complain_on_overflow */
916 bfd_elf_generic_reloc, /* special_function */
917 "R_ARM_ALU_PC_G0", /* name */
918 FALSE, /* partial_inplace */
919 0xffffffff, /* src_mask */
920 0xffffffff, /* dst_mask */
921 TRUE), /* pcrel_offset */
922
923 HOWTO (R_ARM_ALU_PC_G1_NC, /* type */
924 0, /* rightshift */
925 2, /* size (0 = byte, 1 = short, 2 = long) */
926 32, /* bitsize */
927 TRUE, /* pc_relative */
928 0, /* bitpos */
929 complain_overflow_dont,/* complain_on_overflow */
930 bfd_elf_generic_reloc, /* special_function */
931 "R_ARM_ALU_PC_G1_NC", /* name */
932 FALSE, /* partial_inplace */
933 0xffffffff, /* src_mask */
934 0xffffffff, /* dst_mask */
935 TRUE), /* pcrel_offset */
936
937 HOWTO (R_ARM_ALU_PC_G1, /* type */
938 0, /* rightshift */
939 2, /* size (0 = byte, 1 = short, 2 = long) */
940 32, /* bitsize */
941 TRUE, /* pc_relative */
942 0, /* bitpos */
943 complain_overflow_dont,/* complain_on_overflow */
944 bfd_elf_generic_reloc, /* special_function */
945 "R_ARM_ALU_PC_G1", /* name */
946 FALSE, /* partial_inplace */
947 0xffffffff, /* src_mask */
948 0xffffffff, /* dst_mask */
949 TRUE), /* pcrel_offset */
950
951 HOWTO (R_ARM_ALU_PC_G2, /* type */
952 0, /* rightshift */
953 2, /* size (0 = byte, 1 = short, 2 = long) */
954 32, /* bitsize */
955 TRUE, /* pc_relative */
956 0, /* bitpos */
957 complain_overflow_dont,/* complain_on_overflow */
958 bfd_elf_generic_reloc, /* special_function */
959 "R_ARM_ALU_PC_G2", /* name */
960 FALSE, /* partial_inplace */
961 0xffffffff, /* src_mask */
962 0xffffffff, /* dst_mask */
963 TRUE), /* pcrel_offset */
964
965 HOWTO (R_ARM_LDR_PC_G1, /* type */
966 0, /* rightshift */
967 2, /* size (0 = byte, 1 = short, 2 = long) */
968 32, /* bitsize */
969 TRUE, /* pc_relative */
970 0, /* bitpos */
971 complain_overflow_dont,/* complain_on_overflow */
972 bfd_elf_generic_reloc, /* special_function */
973 "R_ARM_LDR_PC_G1", /* name */
974 FALSE, /* partial_inplace */
975 0xffffffff, /* src_mask */
976 0xffffffff, /* dst_mask */
977 TRUE), /* pcrel_offset */
978
979 HOWTO (R_ARM_LDR_PC_G2, /* type */
980 0, /* rightshift */
981 2, /* size (0 = byte, 1 = short, 2 = long) */
982 32, /* bitsize */
983 TRUE, /* pc_relative */
984 0, /* bitpos */
985 complain_overflow_dont,/* complain_on_overflow */
986 bfd_elf_generic_reloc, /* special_function */
987 "R_ARM_LDR_PC_G2", /* name */
988 FALSE, /* partial_inplace */
989 0xffffffff, /* src_mask */
990 0xffffffff, /* dst_mask */
991 TRUE), /* pcrel_offset */
992
993 HOWTO (R_ARM_LDRS_PC_G0, /* type */
994 0, /* rightshift */
995 2, /* size (0 = byte, 1 = short, 2 = long) */
996 32, /* bitsize */
997 TRUE, /* pc_relative */
998 0, /* bitpos */
999 complain_overflow_dont,/* complain_on_overflow */
1000 bfd_elf_generic_reloc, /* special_function */
1001 "R_ARM_LDRS_PC_G0", /* name */
1002 FALSE, /* partial_inplace */
1003 0xffffffff, /* src_mask */
1004 0xffffffff, /* dst_mask */
1005 TRUE), /* pcrel_offset */
1006
1007 HOWTO (R_ARM_LDRS_PC_G1, /* type */
1008 0, /* rightshift */
1009 2, /* size (0 = byte, 1 = short, 2 = long) */
1010 32, /* bitsize */
1011 TRUE, /* pc_relative */
1012 0, /* bitpos */
1013 complain_overflow_dont,/* complain_on_overflow */
1014 bfd_elf_generic_reloc, /* special_function */
1015 "R_ARM_LDRS_PC_G1", /* name */
1016 FALSE, /* partial_inplace */
1017 0xffffffff, /* src_mask */
1018 0xffffffff, /* dst_mask */
1019 TRUE), /* pcrel_offset */
1020
1021 HOWTO (R_ARM_LDRS_PC_G2, /* type */
1022 0, /* rightshift */
1023 2, /* size (0 = byte, 1 = short, 2 = long) */
1024 32, /* bitsize */
1025 TRUE, /* pc_relative */
1026 0, /* bitpos */
1027 complain_overflow_dont,/* complain_on_overflow */
1028 bfd_elf_generic_reloc, /* special_function */
1029 "R_ARM_LDRS_PC_G2", /* name */
1030 FALSE, /* partial_inplace */
1031 0xffffffff, /* src_mask */
1032 0xffffffff, /* dst_mask */
1033 TRUE), /* pcrel_offset */
1034
1035 HOWTO (R_ARM_LDC_PC_G0, /* type */
1036 0, /* rightshift */
1037 2, /* size (0 = byte, 1 = short, 2 = long) */
1038 32, /* bitsize */
1039 TRUE, /* pc_relative */
1040 0, /* bitpos */
1041 complain_overflow_dont,/* complain_on_overflow */
1042 bfd_elf_generic_reloc, /* special_function */
1043 "R_ARM_LDC_PC_G0", /* name */
1044 FALSE, /* partial_inplace */
1045 0xffffffff, /* src_mask */
1046 0xffffffff, /* dst_mask */
1047 TRUE), /* pcrel_offset */
1048
1049 HOWTO (R_ARM_LDC_PC_G1, /* type */
1050 0, /* rightshift */
1051 2, /* size (0 = byte, 1 = short, 2 = long) */
1052 32, /* bitsize */
1053 TRUE, /* pc_relative */
1054 0, /* bitpos */
1055 complain_overflow_dont,/* complain_on_overflow */
1056 bfd_elf_generic_reloc, /* special_function */
1057 "R_ARM_LDC_PC_G1", /* name */
1058 FALSE, /* partial_inplace */
1059 0xffffffff, /* src_mask */
1060 0xffffffff, /* dst_mask */
1061 TRUE), /* pcrel_offset */
1062
1063 HOWTO (R_ARM_LDC_PC_G2, /* type */
1064 0, /* rightshift */
1065 2, /* size (0 = byte, 1 = short, 2 = long) */
1066 32, /* bitsize */
1067 TRUE, /* pc_relative */
1068 0, /* bitpos */
1069 complain_overflow_dont,/* complain_on_overflow */
1070 bfd_elf_generic_reloc, /* special_function */
1071 "R_ARM_LDC_PC_G2", /* name */
1072 FALSE, /* partial_inplace */
1073 0xffffffff, /* src_mask */
1074 0xffffffff, /* dst_mask */
1075 TRUE), /* pcrel_offset */
1076
1077 HOWTO (R_ARM_ALU_SB_G0_NC, /* type */
1078 0, /* rightshift */
1079 2, /* size (0 = byte, 1 = short, 2 = long) */
1080 32, /* bitsize */
1081 TRUE, /* pc_relative */
1082 0, /* bitpos */
1083 complain_overflow_dont,/* complain_on_overflow */
1084 bfd_elf_generic_reloc, /* special_function */
1085 "R_ARM_ALU_SB_G0_NC", /* name */
1086 FALSE, /* partial_inplace */
1087 0xffffffff, /* src_mask */
1088 0xffffffff, /* dst_mask */
1089 TRUE), /* pcrel_offset */
1090
1091 HOWTO (R_ARM_ALU_SB_G0, /* type */
1092 0, /* rightshift */
1093 2, /* size (0 = byte, 1 = short, 2 = long) */
1094 32, /* bitsize */
1095 TRUE, /* pc_relative */
1096 0, /* bitpos */
1097 complain_overflow_dont,/* complain_on_overflow */
1098 bfd_elf_generic_reloc, /* special_function */
1099 "R_ARM_ALU_SB_G0", /* name */
1100 FALSE, /* partial_inplace */
1101 0xffffffff, /* src_mask */
1102 0xffffffff, /* dst_mask */
1103 TRUE), /* pcrel_offset */
1104
1105 HOWTO (R_ARM_ALU_SB_G1_NC, /* type */
1106 0, /* rightshift */
1107 2, /* size (0 = byte, 1 = short, 2 = long) */
1108 32, /* bitsize */
1109 TRUE, /* pc_relative */
1110 0, /* bitpos */
1111 complain_overflow_dont,/* complain_on_overflow */
1112 bfd_elf_generic_reloc, /* special_function */
1113 "R_ARM_ALU_SB_G1_NC", /* name */
1114 FALSE, /* partial_inplace */
1115 0xffffffff, /* src_mask */
1116 0xffffffff, /* dst_mask */
1117 TRUE), /* pcrel_offset */
1118
1119 HOWTO (R_ARM_ALU_SB_G1, /* type */
1120 0, /* rightshift */
1121 2, /* size (0 = byte, 1 = short, 2 = long) */
1122 32, /* bitsize */
1123 TRUE, /* pc_relative */
1124 0, /* bitpos */
1125 complain_overflow_dont,/* complain_on_overflow */
1126 bfd_elf_generic_reloc, /* special_function */
1127 "R_ARM_ALU_SB_G1", /* name */
1128 FALSE, /* partial_inplace */
1129 0xffffffff, /* src_mask */
1130 0xffffffff, /* dst_mask */
1131 TRUE), /* pcrel_offset */
1132
1133 HOWTO (R_ARM_ALU_SB_G2, /* type */
1134 0, /* rightshift */
1135 2, /* size (0 = byte, 1 = short, 2 = long) */
1136 32, /* bitsize */
1137 TRUE, /* pc_relative */
1138 0, /* bitpos */
1139 complain_overflow_dont,/* complain_on_overflow */
1140 bfd_elf_generic_reloc, /* special_function */
1141 "R_ARM_ALU_SB_G2", /* name */
1142 FALSE, /* partial_inplace */
1143 0xffffffff, /* src_mask */
1144 0xffffffff, /* dst_mask */
1145 TRUE), /* pcrel_offset */
1146
1147 HOWTO (R_ARM_LDR_SB_G0, /* type */
1148 0, /* rightshift */
1149 2, /* size (0 = byte, 1 = short, 2 = long) */
1150 32, /* bitsize */
1151 TRUE, /* pc_relative */
1152 0, /* bitpos */
1153 complain_overflow_dont,/* complain_on_overflow */
1154 bfd_elf_generic_reloc, /* special_function */
1155 "R_ARM_LDR_SB_G0", /* name */
1156 FALSE, /* partial_inplace */
1157 0xffffffff, /* src_mask */
1158 0xffffffff, /* dst_mask */
1159 TRUE), /* pcrel_offset */
1160
1161 HOWTO (R_ARM_LDR_SB_G1, /* type */
1162 0, /* rightshift */
1163 2, /* size (0 = byte, 1 = short, 2 = long) */
1164 32, /* bitsize */
1165 TRUE, /* pc_relative */
1166 0, /* bitpos */
1167 complain_overflow_dont,/* complain_on_overflow */
1168 bfd_elf_generic_reloc, /* special_function */
1169 "R_ARM_LDR_SB_G1", /* name */
1170 FALSE, /* partial_inplace */
1171 0xffffffff, /* src_mask */
1172 0xffffffff, /* dst_mask */
1173 TRUE), /* pcrel_offset */
1174
1175 HOWTO (R_ARM_LDR_SB_G2, /* type */
1176 0, /* rightshift */
1177 2, /* size (0 = byte, 1 = short, 2 = long) */
1178 32, /* bitsize */
1179 TRUE, /* pc_relative */
1180 0, /* bitpos */
1181 complain_overflow_dont,/* complain_on_overflow */
1182 bfd_elf_generic_reloc, /* special_function */
1183 "R_ARM_LDR_SB_G2", /* name */
1184 FALSE, /* partial_inplace */
1185 0xffffffff, /* src_mask */
1186 0xffffffff, /* dst_mask */
1187 TRUE), /* pcrel_offset */
1188
1189 HOWTO (R_ARM_LDRS_SB_G0, /* type */
1190 0, /* rightshift */
1191 2, /* size (0 = byte, 1 = short, 2 = long) */
1192 32, /* bitsize */
1193 TRUE, /* pc_relative */
1194 0, /* bitpos */
1195 complain_overflow_dont,/* complain_on_overflow */
1196 bfd_elf_generic_reloc, /* special_function */
1197 "R_ARM_LDRS_SB_G0", /* name */
1198 FALSE, /* partial_inplace */
1199 0xffffffff, /* src_mask */
1200 0xffffffff, /* dst_mask */
1201 TRUE), /* pcrel_offset */
1202
1203 HOWTO (R_ARM_LDRS_SB_G1, /* type */
1204 0, /* rightshift */
1205 2, /* size (0 = byte, 1 = short, 2 = long) */
1206 32, /* bitsize */
1207 TRUE, /* pc_relative */
1208 0, /* bitpos */
1209 complain_overflow_dont,/* complain_on_overflow */
1210 bfd_elf_generic_reloc, /* special_function */
1211 "R_ARM_LDRS_SB_G1", /* name */
1212 FALSE, /* partial_inplace */
1213 0xffffffff, /* src_mask */
1214 0xffffffff, /* dst_mask */
1215 TRUE), /* pcrel_offset */
1216
1217 HOWTO (R_ARM_LDRS_SB_G2, /* type */
1218 0, /* rightshift */
1219 2, /* size (0 = byte, 1 = short, 2 = long) */
1220 32, /* bitsize */
1221 TRUE, /* pc_relative */
1222 0, /* bitpos */
1223 complain_overflow_dont,/* complain_on_overflow */
1224 bfd_elf_generic_reloc, /* special_function */
1225 "R_ARM_LDRS_SB_G2", /* name */
1226 FALSE, /* partial_inplace */
1227 0xffffffff, /* src_mask */
1228 0xffffffff, /* dst_mask */
1229 TRUE), /* pcrel_offset */
1230
1231 HOWTO (R_ARM_LDC_SB_G0, /* type */
1232 0, /* rightshift */
1233 2, /* size (0 = byte, 1 = short, 2 = long) */
1234 32, /* bitsize */
1235 TRUE, /* pc_relative */
1236 0, /* bitpos */
1237 complain_overflow_dont,/* complain_on_overflow */
1238 bfd_elf_generic_reloc, /* special_function */
1239 "R_ARM_LDC_SB_G0", /* name */
1240 FALSE, /* partial_inplace */
1241 0xffffffff, /* src_mask */
1242 0xffffffff, /* dst_mask */
1243 TRUE), /* pcrel_offset */
1244
1245 HOWTO (R_ARM_LDC_SB_G1, /* type */
1246 0, /* rightshift */
1247 2, /* size (0 = byte, 1 = short, 2 = long) */
1248 32, /* bitsize */
1249 TRUE, /* pc_relative */
1250 0, /* bitpos */
1251 complain_overflow_dont,/* complain_on_overflow */
1252 bfd_elf_generic_reloc, /* special_function */
1253 "R_ARM_LDC_SB_G1", /* name */
1254 FALSE, /* partial_inplace */
1255 0xffffffff, /* src_mask */
1256 0xffffffff, /* dst_mask */
1257 TRUE), /* pcrel_offset */
1258
1259 HOWTO (R_ARM_LDC_SB_G2, /* type */
1260 0, /* rightshift */
1261 2, /* size (0 = byte, 1 = short, 2 = long) */
1262 32, /* bitsize */
1263 TRUE, /* pc_relative */
1264 0, /* bitpos */
1265 complain_overflow_dont,/* complain_on_overflow */
1266 bfd_elf_generic_reloc, /* special_function */
1267 "R_ARM_LDC_SB_G2", /* name */
1268 FALSE, /* partial_inplace */
1269 0xffffffff, /* src_mask */
1270 0xffffffff, /* dst_mask */
1271 TRUE), /* pcrel_offset */
1272
1273 /* End of group relocations. */
c19d1205 1274
c19d1205
ZW		 1275 HOWTO (R_ARM_MOVW_BREL_NC, /* type */
1276 0, /* rightshift */
1277 2, /* size (0 = byte, 1 = short, 2 = long) */
1278 16, /* bitsize */
1279 FALSE, /* pc_relative */
1280 0, /* bitpos */
1281 complain_overflow_dont,/* complain_on_overflow */
1282 bfd_elf_generic_reloc, /* special_function */
1283 "R_ARM_MOVW_BREL_NC", /* name */
1284 FALSE, /* partial_inplace */
1285 0x0000ffff, /* src_mask */
1286 0x0000ffff, /* dst_mask */
1287 FALSE), /* pcrel_offset */
1288
1289 HOWTO (R_ARM_MOVT_BREL, /* type */
1290 0, /* rightshift */
1291 2, /* size (0 = byte, 1 = short, 2 = long) */
1292 16, /* bitsize */
1293 FALSE, /* pc_relative */
1294 0, /* bitpos */
1295 complain_overflow_bitfield,/* complain_on_overflow */
1296 bfd_elf_generic_reloc, /* special_function */
1297 "R_ARM_MOVT_BREL", /* name */
1298 FALSE, /* partial_inplace */
1299 0x0000ffff, /* src_mask */
1300 0x0000ffff, /* dst_mask */
1301 FALSE), /* pcrel_offset */
1302
1303 HOWTO (R_ARM_MOVW_BREL, /* type */
1304 0, /* rightshift */
1305 2, /* size (0 = byte, 1 = short, 2 = long) */
1306 16, /* bitsize */
1307 FALSE, /* pc_relative */
1308 0, /* bitpos */
1309 complain_overflow_dont,/* complain_on_overflow */
1310 bfd_elf_generic_reloc, /* special_function */
1311 "R_ARM_MOVW_BREL", /* name */
1312 FALSE, /* partial_inplace */
1313 0x0000ffff, /* src_mask */
1314 0x0000ffff, /* dst_mask */
1315 FALSE), /* pcrel_offset */
1316
1317 HOWTO (R_ARM_THM_MOVW_BREL_NC,/* type */
1318 0, /* rightshift */
1319 2, /* size (0 = byte, 1 = short, 2 = long) */
1320 16, /* bitsize */
1321 FALSE, /* pc_relative */
1322 0, /* bitpos */
1323 complain_overflow_dont,/* complain_on_overflow */
1324 bfd_elf_generic_reloc, /* special_function */
1325 "R_ARM_THM_MOVW_BREL_NC",/* name */
1326 FALSE, /* partial_inplace */
1327 0x040f70ff, /* src_mask */
1328 0x040f70ff, /* dst_mask */
1329 FALSE), /* pcrel_offset */
1330
1331 HOWTO (R_ARM_THM_MOVT_BREL, /* type */
1332 0, /* rightshift */
1333 2, /* size (0 = byte, 1 = short, 2 = long) */
1334 16, /* bitsize */
1335 FALSE, /* pc_relative */
1336 0, /* bitpos */
1337 complain_overflow_bitfield,/* complain_on_overflow */
1338 bfd_elf_generic_reloc, /* special_function */
1339 "R_ARM_THM_MOVT_BREL", /* name */
1340 FALSE, /* partial_inplace */
1341 0x040f70ff, /* src_mask */
1342 0x040f70ff, /* dst_mask */
1343 FALSE), /* pcrel_offset */
1344
1345 HOWTO (R_ARM_THM_MOVW_BREL, /* type */
1346 0, /* rightshift */
1347 2, /* size (0 = byte, 1 = short, 2 = long) */
1348 16, /* bitsize */
1349 FALSE, /* pc_relative */
1350 0, /* bitpos */
1351 complain_overflow_dont,/* complain_on_overflow */
1352 bfd_elf_generic_reloc, /* special_function */
1353 "R_ARM_THM_MOVW_BREL", /* name */
1354 FALSE, /* partial_inplace */
1355 0x040f70ff, /* src_mask */
1356 0x040f70ff, /* dst_mask */
1357 FALSE), /* pcrel_offset */
1358
0855e32b
NS		 1359 HOWTO (R_ARM_TLS_GOTDESC, /* type */
1360 0, /* rightshift */
1361 2, /* size (0 = byte, 1 = short, 2 = long) */
1362 32, /* bitsize */
1363 FALSE, /* pc_relative */
1364 0, /* bitpos */
1365 complain_overflow_bitfield,/* complain_on_overflow */
1366 NULL, /* special_function */
1367 "R_ARM_TLS_GOTDESC", /* name */
1368 TRUE, /* partial_inplace */
1369 0xffffffff, /* src_mask */
1370 0xffffffff, /* dst_mask */
1371 FALSE), /* pcrel_offset */
1372
1373 HOWTO (R_ARM_TLS_CALL, /* type */
1374 0, /* rightshift */
1375 2, /* size (0 = byte, 1 = short, 2 = long) */
1376 24, /* bitsize */
1377 FALSE, /* pc_relative */
1378 0, /* bitpos */
1379 complain_overflow_dont,/* complain_on_overflow */
1380 bfd_elf_generic_reloc, /* special_function */
1381 "R_ARM_TLS_CALL", /* name */
1382 FALSE, /* partial_inplace */
1383 0x00ffffff, /* src_mask */
1384 0x00ffffff, /* dst_mask */
1385 FALSE), /* pcrel_offset */
1386
1387 HOWTO (R_ARM_TLS_DESCSEQ, /* type */
1388 0, /* rightshift */
1389 2, /* size (0 = byte, 1 = short, 2 = long) */
1390 0, /* bitsize */
1391 FALSE, /* pc_relative */
1392 0, /* bitpos */
1393 complain_overflow_bitfield,/* complain_on_overflow */
1394 bfd_elf_generic_reloc, /* special_function */
1395 "R_ARM_TLS_DESCSEQ", /* name */
1396 FALSE, /* partial_inplace */
1397 0x00000000, /* src_mask */
1398 0x00000000, /* dst_mask */
1399 FALSE), /* pcrel_offset */
1400
1401 HOWTO (R_ARM_THM_TLS_CALL, /* type */
1402 0, /* rightshift */
1403 2, /* size (0 = byte, 1 = short, 2 = long) */
1404 24, /* bitsize */
1405 FALSE, /* pc_relative */
1406 0, /* bitpos */
1407 complain_overflow_dont,/* complain_on_overflow */
1408 bfd_elf_generic_reloc, /* special_function */
1409 "R_ARM_THM_TLS_CALL", /* name */
1410 FALSE, /* partial_inplace */
1411 0x07ff07ff, /* src_mask */
1412 0x07ff07ff, /* dst_mask */
1413 FALSE), /* pcrel_offset */
c19d1205
ZW		 1414
1415 HOWTO (R_ARM_PLT32_ABS, /* type */
1416 0, /* rightshift */
1417 2, /* size (0 = byte, 1 = short, 2 = long) */
1418 32, /* bitsize */
1419 FALSE, /* pc_relative */
1420 0, /* bitpos */
1421 complain_overflow_dont,/* complain_on_overflow */
1422 bfd_elf_generic_reloc, /* special_function */
1423 "R_ARM_PLT32_ABS", /* name */
1424 FALSE, /* partial_inplace */
1425 0xffffffff, /* src_mask */
1426 0xffffffff, /* dst_mask */
1427 FALSE), /* pcrel_offset */
1428
1429 HOWTO (R_ARM_GOT_ABS, /* type */
1430 0, /* rightshift */
1431 2, /* size (0 = byte, 1 = short, 2 = long) */
1432 32, /* bitsize */
1433 FALSE, /* pc_relative */
1434 0, /* bitpos */
1435 complain_overflow_dont,/* complain_on_overflow */
1436 bfd_elf_generic_reloc, /* special_function */
1437 "R_ARM_GOT_ABS", /* name */
1438 FALSE, /* partial_inplace */
1439 0xffffffff, /* src_mask */
1440 0xffffffff, /* dst_mask */
1441 FALSE), /* pcrel_offset */
1442
1443 HOWTO (R_ARM_GOT_PREL, /* type */
1444 0, /* rightshift */
1445 2, /* size (0 = byte, 1 = short, 2 = long) */
1446 32, /* bitsize */
1447 TRUE, /* pc_relative */
1448 0, /* bitpos */
1449 complain_overflow_dont, /* complain_on_overflow */
1450 bfd_elf_generic_reloc, /* special_function */
1451 "R_ARM_GOT_PREL", /* name */
1452 FALSE, /* partial_inplace */
1453 0xffffffff, /* src_mask */
1454 0xffffffff, /* dst_mask */
1455 TRUE), /* pcrel_offset */
1456
1457 HOWTO (R_ARM_GOT_BREL12, /* type */
1458 0, /* rightshift */
1459 2, /* size (0 = byte, 1 = short, 2 = long) */
1460 12, /* bitsize */
1461 FALSE, /* pc_relative */
1462 0, /* bitpos */
1463 complain_overflow_bitfield,/* complain_on_overflow */
1464 bfd_elf_generic_reloc, /* special_function */
1465 "R_ARM_GOT_BREL12", /* name */
1466 FALSE, /* partial_inplace */
1467 0x00000fff, /* src_mask */
1468 0x00000fff, /* dst_mask */
1469 FALSE), /* pcrel_offset */
1470
1471 HOWTO (R_ARM_GOTOFF12, /* type */
1472 0, /* rightshift */
1473 2, /* size (0 = byte, 1 = short, 2 = long) */
1474 12, /* bitsize */
1475 FALSE, /* pc_relative */
1476 0, /* bitpos */
1477 complain_overflow_bitfield,/* complain_on_overflow */
1478 bfd_elf_generic_reloc, /* special_function */
1479 "R_ARM_GOTOFF12", /* name */
1480 FALSE, /* partial_inplace */
1481 0x00000fff, /* src_mask */
1482 0x00000fff, /* dst_mask */
1483 FALSE), /* pcrel_offset */
1484
1485 EMPTY_HOWTO (R_ARM_GOTRELAX), /* reserved for future GOT-load optimizations */
1486
1487 /* GNU extension to record C++ vtable member usage */
1488 HOWTO (R_ARM_GNU_VTENTRY, /* type */
99059e56
RM		 1489 0, /* rightshift */
1490 2, /* size (0 = byte, 1 = short, 2 = long) */
1491 0, /* bitsize */
1492 FALSE, /* pc_relative */
1493 0, /* bitpos */
1494 complain_overflow_dont, /* complain_on_overflow */
1495 _bfd_elf_rel_vtable_reloc_fn, /* special_function */
1496 "R_ARM_GNU_VTENTRY", /* name */
1497 FALSE, /* partial_inplace */
1498 0, /* src_mask */
1499 0, /* dst_mask */
1500 FALSE), /* pcrel_offset */
c19d1205
ZW		 1501
1502 /* GNU extension to record C++ vtable hierarchy */
1503 HOWTO (R_ARM_GNU_VTINHERIT, /* type */
99059e56
RM		 1504 0, /* rightshift */
1505 2, /* size (0 = byte, 1 = short, 2 = long) */
1506 0, /* bitsize */
1507 FALSE, /* pc_relative */
1508 0, /* bitpos */
1509 complain_overflow_dont, /* complain_on_overflow */
1510 NULL, /* special_function */
1511 "R_ARM_GNU_VTINHERIT", /* name */
1512 FALSE, /* partial_inplace */
1513 0, /* src_mask */
1514 0, /* dst_mask */
1515 FALSE), /* pcrel_offset */
c19d1205
ZW		 1516
1517 HOWTO (R_ARM_THM_JUMP11, /* type */
1518 1, /* rightshift */
1519 1, /* size (0 = byte, 1 = short, 2 = long) */
1520 11, /* bitsize */
1521 TRUE, /* pc_relative */
1522 0, /* bitpos */
1523 complain_overflow_signed, /* complain_on_overflow */
1524 bfd_elf_generic_reloc, /* special_function */
1525 "R_ARM_THM_JUMP11", /* name */
1526 FALSE, /* partial_inplace */
1527 0x000007ff, /* src_mask */
1528 0x000007ff, /* dst_mask */
1529 TRUE), /* pcrel_offset */
1530
1531 HOWTO (R_ARM_THM_JUMP8, /* type */
1532 1, /* rightshift */
1533 1, /* size (0 = byte, 1 = short, 2 = long) */
1534 8, /* bitsize */
1535 TRUE, /* pc_relative */
1536 0, /* bitpos */
1537 complain_overflow_signed, /* complain_on_overflow */
1538 bfd_elf_generic_reloc, /* special_function */
1539 "R_ARM_THM_JUMP8", /* name */
1540 FALSE, /* partial_inplace */
1541 0x000000ff, /* src_mask */
1542 0x000000ff, /* dst_mask */
1543 TRUE), /* pcrel_offset */
ba93b8ac 1544
c19d1205
ZW		 1545 /* TLS relocations */
1546 HOWTO (R_ARM_TLS_GD32, /* type */
99059e56
RM		 1547 0, /* rightshift */
1548 2, /* size (0 = byte, 1 = short, 2 = long) */
1549 32, /* bitsize */
1550 FALSE, /* pc_relative */
1551 0, /* bitpos */
1552 complain_overflow_bitfield,/* complain_on_overflow */
1553 NULL, /* special_function */
1554 "R_ARM_TLS_GD32", /* name */
1555 TRUE, /* partial_inplace */
1556 0xffffffff, /* src_mask */
1557 0xffffffff, /* dst_mask */
1558 FALSE), /* pcrel_offset */
ba93b8ac 1559
ba93b8ac 1560 HOWTO (R_ARM_TLS_LDM32, /* type */
99059e56
RM		 1561 0, /* rightshift */
1562 2, /* size (0 = byte, 1 = short, 2 = long) */
1563 32, /* bitsize */
1564 FALSE, /* pc_relative */
1565 0, /* bitpos */
1566 complain_overflow_bitfield,/* complain_on_overflow */
1567 bfd_elf_generic_reloc, /* special_function */
1568 "R_ARM_TLS_LDM32", /* name */
1569 TRUE, /* partial_inplace */
1570 0xffffffff, /* src_mask */
1571 0xffffffff, /* dst_mask */
1572 FALSE), /* pcrel_offset */
ba93b8ac 1573
c19d1205 1574 HOWTO (R_ARM_TLS_LDO32, /* type */
99059e56
RM		 1575 0, /* rightshift */
1576 2, /* size (0 = byte, 1 = short, 2 = long) */
1577 32, /* bitsize */
1578 FALSE, /* pc_relative */
1579 0, /* bitpos */
1580 complain_overflow_bitfield,/* complain_on_overflow */
1581 bfd_elf_generic_reloc, /* special_function */
1582 "R_ARM_TLS_LDO32", /* name */
1583 TRUE, /* partial_inplace */
1584 0xffffffff, /* src_mask */
1585 0xffffffff, /* dst_mask */
1586 FALSE), /* pcrel_offset */
ba93b8ac 1587
ba93b8ac 1588 HOWTO (R_ARM_TLS_IE32, /* type */
99059e56
RM		 1589 0, /* rightshift */
1590 2, /* size (0 = byte, 1 = short, 2 = long) */
1591 32, /* bitsize */
1592 FALSE, /* pc_relative */
1593 0, /* bitpos */
1594 complain_overflow_bitfield,/* complain_on_overflow */
1595 NULL, /* special_function */
1596 "R_ARM_TLS_IE32", /* name */
1597 TRUE, /* partial_inplace */
1598 0xffffffff, /* src_mask */
1599 0xffffffff, /* dst_mask */
1600 FALSE), /* pcrel_offset */
7f266840 1601
c19d1205 1602 HOWTO (R_ARM_TLS_LE32, /* type */
99059e56
RM		 1603 0, /* rightshift */
1604 2, /* size (0 = byte, 1 = short, 2 = long) */
1605 32, /* bitsize */
1606 FALSE, /* pc_relative */
1607 0, /* bitpos */
1608 complain_overflow_bitfield,/* complain_on_overflow */
75c11999 1609 NULL, /* special_function */
99059e56
RM		 1610 "R_ARM_TLS_LE32", /* name */
1611 TRUE, /* partial_inplace */
1612 0xffffffff, /* src_mask */
1613 0xffffffff, /* dst_mask */
1614 FALSE), /* pcrel_offset */
7f266840 1615
c19d1205
ZW		 1616 HOWTO (R_ARM_TLS_LDO12, /* type */
1617 0, /* rightshift */
1618 2, /* size (0 = byte, 1 = short, 2 = long) */
1619 12, /* bitsize */
1620 FALSE, /* pc_relative */
7f266840 1621 0, /* bitpos */
c19d1205 1622 complain_overflow_bitfield,/* complain_on_overflow */
7f266840 1623 bfd_elf_generic_reloc, /* special_function */
c19d1205 1624 "R_ARM_TLS_LDO12", /* name */
7f266840 1625 FALSE, /* partial_inplace */
c19d1205
ZW		 1626 0x00000fff, /* src_mask */
1627 0x00000fff, /* dst_mask */
1628 FALSE), /* pcrel_offset */
7f266840 1629
c19d1205
ZW		 1630 HOWTO (R_ARM_TLS_LE12, /* type */
1631 0, /* rightshift */
1632 2, /* size (0 = byte, 1 = short, 2 = long) */
1633 12, /* bitsize */
1634 FALSE, /* pc_relative */
7f266840 1635 0, /* bitpos */
c19d1205 1636 complain_overflow_bitfield,/* complain_on_overflow */
7f266840 1637 bfd_elf_generic_reloc, /* special_function */
c19d1205 1638 "R_ARM_TLS_LE12", /* name */
7f266840 1639 FALSE, /* partial_inplace */
c19d1205
ZW		 1640 0x00000fff, /* src_mask */
1641 0x00000fff, /* dst_mask */
1642 FALSE), /* pcrel_offset */
7f266840 1643
c19d1205 1644 HOWTO (R_ARM_TLS_IE12GP, /* type */
7f266840
DJ		 1645 0, /* rightshift */
1646 2, /* size (0 = byte, 1 = short, 2 = long) */
c19d1205
ZW		 1647 12, /* bitsize */
1648 FALSE, /* pc_relative */
7f266840 1649 0, /* bitpos */
c19d1205 1650 complain_overflow_bitfield,/* complain_on_overflow */
7f266840 1651 bfd_elf_generic_reloc, /* special_function */
c19d1205 1652 "R_ARM_TLS_IE12GP", /* name */
7f266840 1653 FALSE, /* partial_inplace */
c19d1205
ZW		 1654 0x00000fff, /* src_mask */
1655 0x00000fff, /* dst_mask */
1656 FALSE), /* pcrel_offset */
0855e32b 1657
34e77a92 1658 /* 112-127 private relocations. */
0855e32b
NS		 1659 EMPTY_HOWTO (112),
1660 EMPTY_HOWTO (113),
1661 EMPTY_HOWTO (114),
1662 EMPTY_HOWTO (115),
1663 EMPTY_HOWTO (116),
1664 EMPTY_HOWTO (117),
1665 EMPTY_HOWTO (118),
1666 EMPTY_HOWTO (119),
1667 EMPTY_HOWTO (120),
1668 EMPTY_HOWTO (121),
1669 EMPTY_HOWTO (122),
1670 EMPTY_HOWTO (123),
1671 EMPTY_HOWTO (124),
1672 EMPTY_HOWTO (125),
1673 EMPTY_HOWTO (126),
1674 EMPTY_HOWTO (127),
34e77a92
RS		 1675
1676 /* R_ARM_ME_TOO, obsolete. */
0855e32b
NS		 1677 EMPTY_HOWTO (128),
1678
1679 HOWTO (R_ARM_THM_TLS_DESCSEQ, /* type */
1680 0, /* rightshift */
1681 1, /* size (0 = byte, 1 = short, 2 = long) */
1682 0, /* bitsize */
1683 FALSE, /* pc_relative */
1684 0, /* bitpos */
1685 complain_overflow_bitfield,/* complain_on_overflow */
1686 bfd_elf_generic_reloc, /* special_function */
1687 "R_ARM_THM_TLS_DESCSEQ",/* name */
1688 FALSE, /* partial_inplace */
1689 0x00000000, /* src_mask */
1690 0x00000000, /* dst_mask */
1691 FALSE), /* pcrel_offset */
72d98d16
MG		 1692 EMPTY_HOWTO (130),
1693 EMPTY_HOWTO (131),
1694 HOWTO (R_ARM_THM_ALU_ABS_G0_NC,/* type. */
1695 0, /* rightshift. */
1696 1, /* size (0 = byte, 1 = short, 2 = long). */
1697 16, /* bitsize. */
1698 FALSE, /* pc_relative. */
1699 0, /* bitpos. */
1700 complain_overflow_bitfield,/* complain_on_overflow. */
1701 bfd_elf_generic_reloc, /* special_function. */
1702 "R_ARM_THM_ALU_ABS_G0_NC",/* name. */
1703 FALSE, /* partial_inplace. */
1704 0x00000000, /* src_mask. */
1705 0x00000000, /* dst_mask. */
1706 FALSE), /* pcrel_offset. */
1707 HOWTO (R_ARM_THM_ALU_ABS_G1_NC,/* type. */
1708 0, /* rightshift. */
1709 1, /* size (0 = byte, 1 = short, 2 = long). */
1710 16, /* bitsize. */
1711 FALSE, /* pc_relative. */
1712 0, /* bitpos. */
1713 complain_overflow_bitfield,/* complain_on_overflow. */
1714 bfd_elf_generic_reloc, /* special_function. */
1715 "R_ARM_THM_ALU_ABS_G1_NC",/* name. */
1716 FALSE, /* partial_inplace. */
1717 0x00000000, /* src_mask. */
1718 0x00000000, /* dst_mask. */
1719 FALSE), /* pcrel_offset. */
1720 HOWTO (R_ARM_THM_ALU_ABS_G2_NC,/* type. */
1721 0, /* rightshift. */
1722 1, /* size (0 = byte, 1 = short, 2 = long). */
1723 16, /* bitsize. */
1724 FALSE, /* pc_relative. */
1725 0, /* bitpos. */
1726 complain_overflow_bitfield,/* complain_on_overflow. */
1727 bfd_elf_generic_reloc, /* special_function. */
1728 "R_ARM_THM_ALU_ABS_G2_NC",/* name. */
1729 FALSE, /* partial_inplace. */
1730 0x00000000, /* src_mask. */
1731 0x00000000, /* dst_mask. */
1732 FALSE), /* pcrel_offset. */
1733 HOWTO (R_ARM_THM_ALU_ABS_G3_NC,/* type. */
1734 0, /* rightshift. */
1735 1, /* size (0 = byte, 1 = short, 2 = long). */
1736 16, /* bitsize. */
1737 FALSE, /* pc_relative. */
1738 0, /* bitpos. */
1739 complain_overflow_bitfield,/* complain_on_overflow. */
1740 bfd_elf_generic_reloc, /* special_function. */
1741 "R_ARM_THM_ALU_ABS_G3_NC",/* name. */
1742 FALSE, /* partial_inplace. */
1743 0x00000000, /* src_mask. */
1744 0x00000000, /* dst_mask. */
1745 FALSE), /* pcrel_offset. */
c19d1205
ZW		 1746};
1747
34e77a92
RS		 1748/* 160 onwards: */
1749static reloc_howto_type elf32_arm_howto_table_2[1] =
1750{
1751 HOWTO (R_ARM_IRELATIVE, /* type */
99059e56
RM		 1752 0, /* rightshift */
1753 2, /* size (0 = byte, 1 = short, 2 = long) */
1754 32, /* bitsize */
1755 FALSE, /* pc_relative */
1756 0, /* bitpos */
1757 complain_overflow_bitfield,/* complain_on_overflow */
1758 bfd_elf_generic_reloc, /* special_function */
1759 "R_ARM_IRELATIVE", /* name */
1760 TRUE, /* partial_inplace */
1761 0xffffffff, /* src_mask */
1762 0xffffffff, /* dst_mask */
1763 FALSE) /* pcrel_offset */
34e77a92 1764};
c19d1205 1765
34e77a92
RS		 1766/* 249-255 extended, currently unused, relocations: */
1767static reloc_howto_type elf32_arm_howto_table_3[4] =
7f266840
DJ		 1768{
1769 HOWTO (R_ARM_RREL32, /* type */
1770 0, /* rightshift */
1771 0, /* size (0 = byte, 1 = short, 2 = long) */
1772 0, /* bitsize */
1773 FALSE, /* pc_relative */
1774 0, /* bitpos */
1775 complain_overflow_dont,/* complain_on_overflow */
1776 bfd_elf_generic_reloc, /* special_function */
1777 "R_ARM_RREL32", /* name */
1778 FALSE, /* partial_inplace */
1779 0, /* src_mask */
1780 0, /* dst_mask */
1781 FALSE), /* pcrel_offset */
1782
1783 HOWTO (R_ARM_RABS32, /* type */
1784 0, /* rightshift */
1785 0, /* size (0 = byte, 1 = short, 2 = long) */
1786 0, /* bitsize */
1787 FALSE, /* pc_relative */
1788 0, /* bitpos */
1789 complain_overflow_dont,/* complain_on_overflow */
1790 bfd_elf_generic_reloc, /* special_function */
1791 "R_ARM_RABS32", /* name */
1792 FALSE, /* partial_inplace */
1793 0, /* src_mask */
1794 0, /* dst_mask */
1795 FALSE), /* pcrel_offset */
1796
1797 HOWTO (R_ARM_RPC24, /* type */
1798 0, /* rightshift */
1799 0, /* size (0 = byte, 1 = short, 2 = long) */
1800 0, /* bitsize */
1801 FALSE, /* pc_relative */
1802 0, /* bitpos */
1803 complain_overflow_dont,/* complain_on_overflow */
1804 bfd_elf_generic_reloc, /* special_function */
1805 "R_ARM_RPC24", /* name */
1806 FALSE, /* partial_inplace */
1807 0, /* src_mask */
1808 0, /* dst_mask */
1809 FALSE), /* pcrel_offset */
1810
1811 HOWTO (R_ARM_RBASE, /* type */
1812 0, /* rightshift */
1813 0, /* size (0 = byte, 1 = short, 2 = long) */
1814 0, /* bitsize */
1815 FALSE, /* pc_relative */
1816 0, /* bitpos */
1817 complain_overflow_dont,/* complain_on_overflow */
1818 bfd_elf_generic_reloc, /* special_function */
1819 "R_ARM_RBASE", /* name */
1820 FALSE, /* partial_inplace */
1821 0, /* src_mask */
1822 0, /* dst_mask */
1823 FALSE) /* pcrel_offset */
1824};
1825
1826static reloc_howto_type *
1827elf32_arm_howto_from_type (unsigned int r_type)
1828{
906e58ca 1829 if (r_type < ARRAY_SIZE (elf32_arm_howto_table_1))
c19d1205 1830 return &elf32_arm_howto_table_1[r_type];
ba93b8ac 1831
34e77a92
RS		 1832 if (r_type == R_ARM_IRELATIVE)
1833 return &elf32_arm_howto_table_2[r_type - R_ARM_IRELATIVE];
1834
c19d1205 1835 if (r_type >= R_ARM_RREL32
34e77a92
RS		 1836 && r_type < R_ARM_RREL32 + ARRAY_SIZE (elf32_arm_howto_table_3))
1837 return &elf32_arm_howto_table_3[r_type - R_ARM_RREL32];
7f266840 1838
c19d1205 1839 return NULL;
7f266840
DJ		 1840}
1841
1842static void
1843elf32_arm_info_to_howto (bfd * abfd ATTRIBUTE_UNUSED, arelent * bfd_reloc,
1844 Elf_Internal_Rela * elf_reloc)
1845{
1846 unsigned int r_type;
1847
1848 r_type = ELF32_R_TYPE (elf_reloc->r_info);
1849 bfd_reloc->howto = elf32_arm_howto_from_type (r_type);
1850}
1851
1852struct elf32_arm_reloc_map
1853 {
1854 bfd_reloc_code_real_type bfd_reloc_val;
1855 unsigned char elf_reloc_val;
1856 };
1857
1858/* All entries in this list must also be present in elf32_arm_howto_table. */
1859static const struct elf32_arm_reloc_map elf32_arm_reloc_map[] =
1860 {
1861 {BFD_RELOC_NONE, R_ARM_NONE},
1862 {BFD_RELOC_ARM_PCREL_BRANCH, R_ARM_PC24},
39b41c9c
PB		 1863 {BFD_RELOC_ARM_PCREL_CALL, R_ARM_CALL},
1864 {BFD_RELOC_ARM_PCREL_JUMP, R_ARM_JUMP24},
7f266840
DJ		 1865 {BFD_RELOC_ARM_PCREL_BLX, R_ARM_XPC25},
1866 {BFD_RELOC_THUMB_PCREL_BLX, R_ARM_THM_XPC22},
1867 {BFD_RELOC_32, R_ARM_ABS32},
1868 {BFD_RELOC_32_PCREL, R_ARM_REL32},
1869 {BFD_RELOC_8, R_ARM_ABS8},
1870 {BFD_RELOC_16, R_ARM_ABS16},
1871 {BFD_RELOC_ARM_OFFSET_IMM, R_ARM_ABS12},
1872 {BFD_RELOC_ARM_THUMB_OFFSET, R_ARM_THM_ABS5},
c19d1205
ZW		 1873 {BFD_RELOC_THUMB_PCREL_BRANCH25, R_ARM_THM_JUMP24},
1874 {BFD_RELOC_THUMB_PCREL_BRANCH23, R_ARM_THM_CALL},
1875 {BFD_RELOC_THUMB_PCREL_BRANCH12, R_ARM_THM_JUMP11},
1876 {BFD_RELOC_THUMB_PCREL_BRANCH20, R_ARM_THM_JUMP19},
1877 {BFD_RELOC_THUMB_PCREL_BRANCH9, R_ARM_THM_JUMP8},
1878 {BFD_RELOC_THUMB_PCREL_BRANCH7, R_ARM_THM_JUMP6},
7f266840
DJ		 1879 {BFD_RELOC_ARM_GLOB_DAT, R_ARM_GLOB_DAT},
1880 {BFD_RELOC_ARM_JUMP_SLOT, R_ARM_JUMP_SLOT},
1881 {BFD_RELOC_ARM_RELATIVE, R_ARM_RELATIVE},
c19d1205 1882 {BFD_RELOC_ARM_GOTOFF, R_ARM_GOTOFF32},
7f266840 1883 {BFD_RELOC_ARM_GOTPC, R_ARM_GOTPC},
b43420e6 1884 {BFD_RELOC_ARM_GOT_PREL, R_ARM_GOT_PREL},
7f266840
DJ		 1885 {BFD_RELOC_ARM_GOT32, R_ARM_GOT32},
1886 {BFD_RELOC_ARM_PLT32, R_ARM_PLT32},
1887 {BFD_RELOC_ARM_TARGET1, R_ARM_TARGET1},
1888 {BFD_RELOC_ARM_ROSEGREL32, R_ARM_ROSEGREL32},
1889 {BFD_RELOC_ARM_SBREL32, R_ARM_SBREL32},
1890 {BFD_RELOC_ARM_PREL31, R_ARM_PREL31},
ba93b8ac
DJ		 1891 {BFD_RELOC_ARM_TARGET2, R_ARM_TARGET2},
1892 {BFD_RELOC_ARM_PLT32, R_ARM_PLT32},
0855e32b
NS		 1893 {BFD_RELOC_ARM_TLS_GOTDESC, R_ARM_TLS_GOTDESC},
1894 {BFD_RELOC_ARM_TLS_CALL, R_ARM_TLS_CALL},
1895 {BFD_RELOC_ARM_THM_TLS_CALL, R_ARM_THM_TLS_CALL},
1896 {BFD_RELOC_ARM_TLS_DESCSEQ, R_ARM_TLS_DESCSEQ},
1897 {BFD_RELOC_ARM_THM_TLS_DESCSEQ, R_ARM_THM_TLS_DESCSEQ},
1898 {BFD_RELOC_ARM_TLS_DESC, R_ARM_TLS_DESC},
ba93b8ac
DJ		 1899 {BFD_RELOC_ARM_TLS_GD32, R_ARM_TLS_GD32},
1900 {BFD_RELOC_ARM_TLS_LDO32, R_ARM_TLS_LDO32},
1901 {BFD_RELOC_ARM_TLS_LDM32, R_ARM_TLS_LDM32},
1902 {BFD_RELOC_ARM_TLS_DTPMOD32, R_ARM_TLS_DTPMOD32},
1903 {BFD_RELOC_ARM_TLS_DTPOFF32, R_ARM_TLS_DTPOFF32},
1904 {BFD_RELOC_ARM_TLS_TPOFF32, R_ARM_TLS_TPOFF32},
1905 {BFD_RELOC_ARM_TLS_IE32, R_ARM_TLS_IE32},
1906 {BFD_RELOC_ARM_TLS_LE32, R_ARM_TLS_LE32},
34e77a92 1907 {BFD_RELOC_ARM_IRELATIVE, R_ARM_IRELATIVE},
c19d1205
ZW		 1908 {BFD_RELOC_VTABLE_INHERIT, R_ARM_GNU_VTINHERIT},
1909 {BFD_RELOC_VTABLE_ENTRY, R_ARM_GNU_VTENTRY},
b6895b4f
PB		 1910 {BFD_RELOC_ARM_MOVW, R_ARM_MOVW_ABS_NC},
1911 {BFD_RELOC_ARM_MOVT, R_ARM_MOVT_ABS},
1912 {BFD_RELOC_ARM_MOVW_PCREL, R_ARM_MOVW_PREL_NC},
1913 {BFD_RELOC_ARM_MOVT_PCREL, R_ARM_MOVT_PREL},
1914 {BFD_RELOC_ARM_THUMB_MOVW, R_ARM_THM_MOVW_ABS_NC},
1915 {BFD_RELOC_ARM_THUMB_MOVT, R_ARM_THM_MOVT_ABS},
1916 {BFD_RELOC_ARM_THUMB_MOVW_PCREL, R_ARM_THM_MOVW_PREL_NC},
1917 {BFD_RELOC_ARM_THUMB_MOVT_PCREL, R_ARM_THM_MOVT_PREL},
4962c51a
MS		 1918 {BFD_RELOC_ARM_ALU_PC_G0_NC, R_ARM_ALU_PC_G0_NC},
1919 {BFD_RELOC_ARM_ALU_PC_G0, R_ARM_ALU_PC_G0},
1920 {BFD_RELOC_ARM_ALU_PC_G1_NC, R_ARM_ALU_PC_G1_NC},
1921 {BFD_RELOC_ARM_ALU_PC_G1, R_ARM_ALU_PC_G1},
1922 {BFD_RELOC_ARM_ALU_PC_G2, R_ARM_ALU_PC_G2},
1923 {BFD_RELOC_ARM_LDR_PC_G0, R_ARM_LDR_PC_G0},
1924 {BFD_RELOC_ARM_LDR_PC_G1, R_ARM_LDR_PC_G1},
1925 {BFD_RELOC_ARM_LDR_PC_G2, R_ARM_LDR_PC_G2},
1926 {BFD_RELOC_ARM_LDRS_PC_G0, R_ARM_LDRS_PC_G0},
1927 {BFD_RELOC_ARM_LDRS_PC_G1, R_ARM_LDRS_PC_G1},
1928 {BFD_RELOC_ARM_LDRS_PC_G2, R_ARM_LDRS_PC_G2},
1929 {BFD_RELOC_ARM_LDC_PC_G0, R_ARM_LDC_PC_G0},
1930 {BFD_RELOC_ARM_LDC_PC_G1, R_ARM_LDC_PC_G1},
1931 {BFD_RELOC_ARM_LDC_PC_G2, R_ARM_LDC_PC_G2},
1932 {BFD_RELOC_ARM_ALU_SB_G0_NC, R_ARM_ALU_SB_G0_NC},
1933 {BFD_RELOC_ARM_ALU_SB_G0, R_ARM_ALU_SB_G0},
1934 {BFD_RELOC_ARM_ALU_SB_G1_NC, R_ARM_ALU_SB_G1_NC},
1935 {BFD_RELOC_ARM_ALU_SB_G1, R_ARM_ALU_SB_G1},
1936 {BFD_RELOC_ARM_ALU_SB_G2, R_ARM_ALU_SB_G2},
1937 {BFD_RELOC_ARM_LDR_SB_G0, R_ARM_LDR_SB_G0},
1938 {BFD_RELOC_ARM_LDR_SB_G1, R_ARM_LDR_SB_G1},
1939 {BFD_RELOC_ARM_LDR_SB_G2, R_ARM_LDR_SB_G2},
1940 {BFD_RELOC_ARM_LDRS_SB_G0, R_ARM_LDRS_SB_G0},
1941 {BFD_RELOC_ARM_LDRS_SB_G1, R_ARM_LDRS_SB_G1},
1942 {BFD_RELOC_ARM_LDRS_SB_G2, R_ARM_LDRS_SB_G2},
1943 {BFD_RELOC_ARM_LDC_SB_G0, R_ARM_LDC_SB_G0},
1944 {BFD_RELOC_ARM_LDC_SB_G1, R_ARM_LDC_SB_G1},
845b51d6 1945 {BFD_RELOC_ARM_LDC_SB_G2, R_ARM_LDC_SB_G2},
72d98d16
MG		 1946 {BFD_RELOC_ARM_V4BX, R_ARM_V4BX},
1947 {BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC, R_ARM_THM_ALU_ABS_G3_NC},
1948 {BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC, R_ARM_THM_ALU_ABS_G2_NC},
1949 {BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC, R_ARM_THM_ALU_ABS_G1_NC},
1950 {BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC, R_ARM_THM_ALU_ABS_G0_NC}
7f266840
DJ		 1951 };
1952
1953static reloc_howto_type *
f1c71a59
ZW		 1954elf32_arm_reloc_type_lookup (bfd *abfd ATTRIBUTE_UNUSED,
1955 bfd_reloc_code_real_type code)
7f266840
DJ		 1956{
1957 unsigned int i;
8029a119 1958
906e58ca 1959 for (i = 0; i < ARRAY_SIZE (elf32_arm_reloc_map); i ++)
c19d1205
ZW		 1960 if (elf32_arm_reloc_map[i].bfd_reloc_val == code)
1961 return elf32_arm_howto_from_type (elf32_arm_reloc_map[i].elf_reloc_val);
7f266840 1962
c19d1205 1963 return NULL;
7f266840
DJ		 1964}
1965
157090f7
AM		 1966static reloc_howto_type *
1967elf32_arm_reloc_name_lookup (bfd *abfd ATTRIBUTE_UNUSED,
1968 const char *r_name)
1969{
1970 unsigned int i;
1971
906e58ca 1972 for (i = 0; i < ARRAY_SIZE (elf32_arm_howto_table_1); i++)
157090f7
AM		 1973 if (elf32_arm_howto_table_1[i].name != NULL
1974 && strcasecmp (elf32_arm_howto_table_1[i].name, r_name) == 0)
1975 return &elf32_arm_howto_table_1[i];
1976
906e58ca 1977 for (i = 0; i < ARRAY_SIZE (elf32_arm_howto_table_2); i++)
157090f7
AM		 1978 if (elf32_arm_howto_table_2[i].name != NULL
1979 && strcasecmp (elf32_arm_howto_table_2[i].name, r_name) == 0)
1980 return &elf32_arm_howto_table_2[i];
1981
34e77a92
RS		 1982 for (i = 0; i < ARRAY_SIZE (elf32_arm_howto_table_3); i++)
1983 if (elf32_arm_howto_table_3[i].name != NULL
1984 && strcasecmp (elf32_arm_howto_table_3[i].name, r_name) == 0)
1985 return &elf32_arm_howto_table_3[i];
1986
157090f7
AM		 1987 return NULL;
1988}
1989
906e58ca
NC		 1990/* Support for core dump NOTE sections. */
1991
7f266840 1992static bfd_boolean
f1c71a59 1993elf32_arm_nabi_grok_prstatus (bfd *abfd, Elf_Internal_Note *note)
7f266840
DJ		 1994{
1995 int offset;
1996 size_t size;
1997
1998 switch (note->descsz)
1999 {
2000 default:
2001 return FALSE;
2002
8029a119 2003 case 148: /* Linux/ARM 32-bit. */
7f266840 2004 /* pr_cursig */
228e534f 2005 elf_tdata (abfd)->core->signal = bfd_get_16 (abfd, note->descdata + 12);
7f266840
DJ		 2006
2007 /* pr_pid */
228e534f 2008 elf_tdata (abfd)->core->lwpid = bfd_get_32 (abfd, note->descdata + 24);
7f266840
DJ		 2009
2010 /* pr_reg */
2011 offset = 72;
2012 size = 72;
2013
2014 break;
2015 }
2016
2017 /* Make a ".reg/999" section. */
2018 return _bfd_elfcore_make_pseudosection (abfd, ".reg",
2019 size, note->descpos + offset);
2020}
2021
2022static bfd_boolean
f1c71a59 2023elf32_arm_nabi_grok_psinfo (bfd *abfd, Elf_Internal_Note *note)
7f266840
DJ		 2024{
2025 switch (note->descsz)
2026 {
2027 default:
2028 return FALSE;
2029
8029a119 2030 case 124: /* Linux/ARM elf_prpsinfo. */
228e534f 2031 elf_tdata (abfd)->core->pid
4395ee08 2032 = bfd_get_32 (abfd, note->descdata + 12);
228e534f 2033 elf_tdata (abfd)->core->program
7f266840 2034 = _bfd_elfcore_strndup (abfd, note->descdata + 28, 16);
228e534f 2035 elf_tdata (abfd)->core->command
7f266840
DJ		 2036 = _bfd_elfcore_strndup (abfd, note->descdata + 44, 80);
2037 }
2038
2039 /* Note that for some reason, a spurious space is tacked
2040 onto the end of the args in some (at least one anyway)
2041 implementations, so strip it off if it exists. */
7f266840 2042 {
228e534f 2043 char *command = elf_tdata (abfd)->core->command;
7f266840
DJ		 2044 int n = strlen (command);
2045
2046 if (0 < n && command[n - 1] == ' ')
2047 command[n - 1] = '\0';
2048 }
2049
2050 return TRUE;
2051}
2052
1f20dca5
UW		 2053static char *
2054elf32_arm_nabi_write_core_note (bfd *abfd, char *buf, int *bufsiz,
2055 int note_type, ...)
2056{
2057 switch (note_type)
2058 {
2059 default:
2060 return NULL;
2061
2062 case NT_PRPSINFO:
2063 {
2064 char data[124];
2065 va_list ap;
2066
2067 va_start (ap, note_type);
2068 memset (data, 0, sizeof (data));
2069 strncpy (data + 28, va_arg (ap, const char *), 16);
2070 strncpy (data + 44, va_arg (ap, const char *), 80);
2071 va_end (ap);
2072
2073 return elfcore_write_note (abfd, buf, bufsiz,
2074 "CORE", note_type, data, sizeof (data));
2075 }
2076
2077 case NT_PRSTATUS:
2078 {
2079 char data[148];
2080 va_list ap;
2081 long pid;
2082 int cursig;
2083 const void *greg;
2084
2085 va_start (ap, note_type);
2086 memset (data, 0, sizeof (data));
2087 pid = va_arg (ap, long);
2088 bfd_put_32 (abfd, pid, data + 24);
2089 cursig = va_arg (ap, int);
2090 bfd_put_16 (abfd, cursig, data + 12);
2091 greg = va_arg (ap, const void *);
2092 memcpy (data + 72, greg, 72);
2093 va_end (ap);
2094
2095 return elfcore_write_note (abfd, buf, bufsiz,
2096 "CORE", note_type, data, sizeof (data));
2097 }
2098 }
2099}
2100
6d00b590 2101#define TARGET_LITTLE_SYM arm_elf32_le_vec
7f266840 2102#define TARGET_LITTLE_NAME "elf32-littlearm"
6d00b590 2103#define TARGET_BIG_SYM arm_elf32_be_vec
7f266840
DJ		 2104#define TARGET_BIG_NAME "elf32-bigarm"
2105
2106#define elf_backend_grok_prstatus elf32_arm_nabi_grok_prstatus
2107#define elf_backend_grok_psinfo elf32_arm_nabi_grok_psinfo
1f20dca5 2108#define elf_backend_write_core_note elf32_arm_nabi_write_core_note
7f266840 2109
252b5132
RH		 2110typedef unsigned long int insn32;
2111typedef unsigned short int insn16;
2112
3a4a14e9
PB		 2113/* In lieu of proper flags, assume all EABIv4 or later objects are
2114 interworkable. */
57e8b36a 2115#define INTERWORK_FLAG(abfd) \
3a4a14e9 2116 (EF_ARM_EABI_VERSION (elf_elfheader (abfd)->e_flags) >= EF_ARM_EABI_VER4 \
3e6b1042
DJ		 2117 || (elf_elfheader (abfd)->e_flags & EF_ARM_INTERWORK) \
2118 || ((abfd)->flags & BFD_LINKER_CREATED))
9b485d32 2119
252b5132
RH		 2120/* The linker script knows the section names for placement.
2121 The entry_names are used to do simple name mangling on the stubs.
2122 Given a function name, and its type, the stub can be found. The
9b485d32 2123 name can be changed. The only requirement is the %s be present. */
252b5132
RH		 2124#define THUMB2ARM_GLUE_SECTION_NAME ".glue_7t"
2125#define THUMB2ARM_GLUE_ENTRY_NAME "__%s_from_thumb"
2126
2127#define ARM2THUMB_GLUE_SECTION_NAME ".glue_7"
2128#define ARM2THUMB_GLUE_ENTRY_NAME "__%s_from_arm"
2129
c7b8f16e
JB		 2130#define VFP11_ERRATUM_VENEER_SECTION_NAME ".vfp11_veneer"
2131#define VFP11_ERRATUM_VENEER_ENTRY_NAME "__vfp11_veneer_%x"
2132
a504d23a
LA		 2133#define STM32L4XX_ERRATUM_VENEER_SECTION_NAME ".text.stm32l4xx_veneer"
2134#define STM32L4XX_ERRATUM_VENEER_ENTRY_NAME "__stm32l4xx_veneer_%x"
2135
845b51d6
PB		 2136#define ARM_BX_GLUE_SECTION_NAME ".v4_bx"
2137#define ARM_BX_GLUE_ENTRY_NAME "__bx_r%d"
2138
7413f23f
DJ		 2139#define STUB_ENTRY_NAME "__%s_veneer"
2140
4ba2ef8f
TP		 2141#define CMSE_PREFIX "__acle_se_"
2142
252b5132
RH		 2143/* The name of the dynamic interpreter. This is put in the .interp
2144 section. */
2145#define ELF_DYNAMIC_INTERPRETER "/usr/lib/ld.so.1"
2146
0855e32b 2147static const unsigned long tls_trampoline [] =
b38cadfb
NC		 2148{
2149 0xe08e0000, /* add r0, lr, r0 */
2150 0xe5901004, /* ldr r1, [r0,#4] */
2151 0xe12fff11, /* bx r1 */
2152};
0855e32b
NS		 2153
2154static const unsigned long dl_tlsdesc_lazy_trampoline [] =
b38cadfb
NC		 2155{
2156 0xe52d2004, /* push {r2} */
2157 0xe59f200c, /* ldr r2, [pc, #3f - . - 8] */
2158 0xe59f100c, /* ldr r1, [pc, #4f - . - 8] */
2159 0xe79f2002, /* 1: ldr r2, [pc, r2] */
2160 0xe081100f, /* 2: add r1, pc */
2161 0xe12fff12, /* bx r2 */
2162 0x00000014, /* 3: .word _GLOBAL_OFFSET_TABLE_ - 1b - 8
99059e56 2163 + dl_tlsdesc_lazy_resolver(GOT) */
b38cadfb
NC		 2164 0x00000018, /* 4: .word _GLOBAL_OFFSET_TABLE_ - 2b - 8 */
2165};
0855e32b 2166
5e681ec4
PB		 2167#ifdef FOUR_WORD_PLT
2168
252b5132
RH		 2169/* The first entry in a procedure linkage table looks like
2170 this. It is set up so that any shared library function that is
59f2c4e7 2171 called before the relocation has been set up calls the dynamic
9b485d32 2172 linker first. */
e5a52504 2173static const bfd_vma elf32_arm_plt0_entry [] =
b38cadfb
NC		 2174{
2175 0xe52de004, /* str lr, [sp, #-4]! */
2176 0xe59fe010, /* ldr lr, [pc, #16] */
2177 0xe08fe00e, /* add lr, pc, lr */
2178 0xe5bef008, /* ldr pc, [lr, #8]! */
2179};
5e681ec4
PB		 2180
2181/* Subsequent entries in a procedure linkage table look like
2182 this. */
e5a52504 2183static const bfd_vma elf32_arm_plt_entry [] =
b38cadfb
NC		 2184{
2185 0xe28fc600, /* add ip, pc, #NN */
2186 0xe28cca00, /* add ip, ip, #NN */
2187 0xe5bcf000, /* ldr pc, [ip, #NN]! */
2188 0x00000000, /* unused */
2189};
5e681ec4 2190
eed94f8f 2191#else /* not FOUR_WORD_PLT */
5e681ec4 2192
5e681ec4
PB		 2193/* The first entry in a procedure linkage table looks like
2194 this. It is set up so that any shared library function that is
2195 called before the relocation has been set up calls the dynamic
2196 linker first. */
e5a52504 2197static const bfd_vma elf32_arm_plt0_entry [] =
b38cadfb
NC		 2198{
2199 0xe52de004, /* str lr, [sp, #-4]! */
2200 0xe59fe004, /* ldr lr, [pc, #4] */
2201 0xe08fe00e, /* add lr, pc, lr */
2202 0xe5bef008, /* ldr pc, [lr, #8]! */
2203 0x00000000, /* &GOT[0] - . */
2204};
252b5132 2205
1db37fe6
YG		 2206/* By default subsequent entries in a procedure linkage table look like
2207 this. Offsets that don't fit into 28 bits will cause link error. */
2208static const bfd_vma elf32_arm_plt_entry_short [] =
b38cadfb
NC		 2209{
2210 0xe28fc600, /* add ip, pc, #0xNN00000 */
2211 0xe28cca00, /* add ip, ip, #0xNN000 */
2212 0xe5bcf000, /* ldr pc, [ip, #0xNNN]! */
2213};
5e681ec4 2214
1db37fe6
YG		 2215/* When explicitly asked, we'll use this "long" entry format
2216 which can cope with arbitrary displacements. */
2217static const bfd_vma elf32_arm_plt_entry_long [] =
2218{
2219 0xe28fc200, /* add ip, pc, #0xN0000000 */
2220 0xe28cc600, /* add ip, ip, #0xNN00000 */
2221 0xe28cca00, /* add ip, ip, #0xNN000 */
2222 0xe5bcf000, /* ldr pc, [ip, #0xNNN]! */
2223};
2224
2225static bfd_boolean elf32_arm_use_long_plt_entry = FALSE;
2226
eed94f8f
NC		 2227#endif /* not FOUR_WORD_PLT */
2228
2229/* The first entry in a procedure linkage table looks like this.
2230 It is set up so that any shared library function that is called before the
2231 relocation has been set up calls the dynamic linker first. */
2232static const bfd_vma elf32_thumb2_plt0_entry [] =
2233{
2234 /* NOTE: As this is a mixture of 16-bit and 32-bit instructions,
2235 an instruction maybe encoded to one or two array elements. */
2236 0xf8dfb500, /* push {lr} */
2237 0x44fee008, /* ldr.w lr, [pc, #8] */
469a3493 2238 /* add lr, pc */
eed94f8f
NC		 2239 0xff08f85e, /* ldr.w pc, [lr, #8]! */
2240 0x00000000, /* &GOT[0] - . */
2241};
2242
2243/* Subsequent entries in a procedure linkage table for thumb only target
2244 look like this. */
2245static const bfd_vma elf32_thumb2_plt_entry [] =
2246{
2247 /* NOTE: As this is a mixture of 16-bit and 32-bit instructions,
2248 an instruction maybe encoded to one or two array elements. */
2249 0x0c00f240, /* movw ip, #0xNNNN */
2250 0x0c00f2c0, /* movt ip, #0xNNNN */
2251 0xf8dc44fc, /* add ip, pc */
2252 0xbf00f000 /* ldr.w pc, [ip] */
469a3493 2253 /* nop */
eed94f8f 2254};
252b5132 2255
00a97672
RS		 2256/* The format of the first entry in the procedure linkage table
2257 for a VxWorks executable. */
2258static const bfd_vma elf32_arm_vxworks_exec_plt0_entry[] =
b38cadfb
NC		 2259{
2260 0xe52dc008, /* str ip,[sp,#-8]! */
2261 0xe59fc000, /* ldr ip,[pc] */
2262 0xe59cf008, /* ldr pc,[ip,#8] */
2263 0x00000000, /* .long _GLOBAL_OFFSET_TABLE_ */
2264};
00a97672
RS		 2265
2266/* The format of subsequent entries in a VxWorks executable. */
2267static const bfd_vma elf32_arm_vxworks_exec_plt_entry[] =
b38cadfb
NC		 2268{
2269 0xe59fc000, /* ldr ip,[pc] */
2270 0xe59cf000, /* ldr pc,[ip] */
2271 0x00000000, /* .long @got */
2272 0xe59fc000, /* ldr ip,[pc] */
2273 0xea000000, /* b _PLT */
2274 0x00000000, /* .long @pltindex*sizeof(Elf32_Rela) */
2275};
00a97672
RS		 2276
2277/* The format of entries in a VxWorks shared library. */
2278static const bfd_vma elf32_arm_vxworks_shared_plt_entry[] =
b38cadfb
NC		 2279{
2280 0xe59fc000, /* ldr ip,[pc] */
2281 0xe79cf009, /* ldr pc,[ip,r9] */
2282 0x00000000, /* .long @got */
2283 0xe59fc000, /* ldr ip,[pc] */
2284 0xe599f008, /* ldr pc,[r9,#8] */
2285 0x00000000, /* .long @pltindex*sizeof(Elf32_Rela) */
2286};
00a97672 2287
b7693d02
DJ		 2288/* An initial stub used if the PLT entry is referenced from Thumb code. */
2289#define PLT_THUMB_STUB_SIZE 4
2290static const bfd_vma elf32_arm_plt_thumb_stub [] =
b38cadfb
NC		 2291{
2292 0x4778, /* bx pc */
2293 0x46c0 /* nop */
2294};
b7693d02 2295
e5a52504
MM		 2296/* The entries in a PLT when using a DLL-based target with multiple
2297 address spaces. */
906e58ca 2298static const bfd_vma elf32_arm_symbian_plt_entry [] =
b38cadfb
NC		 2299{
2300 0xe51ff004, /* ldr pc, [pc, #-4] */
2301 0x00000000, /* dcd R_ARM_GLOB_DAT(X) */
2302};
2303
2304/* The first entry in a procedure linkage table looks like
2305 this. It is set up so that any shared library function that is
2306 called before the relocation has been set up calls the dynamic
2307 linker first. */
2308static const bfd_vma elf32_arm_nacl_plt0_entry [] =
2309{
2310 /* First bundle: */
2311 0xe300c000, /* movw ip, #:lower16:&GOT[2]-.+8 */
2312 0xe340c000, /* movt ip, #:upper16:&GOT[2]-.+8 */
2313 0xe08cc00f, /* add ip, ip, pc */
2314 0xe52dc008, /* str ip, [sp, #-8]! */
2315 /* Second bundle: */
edccdf7c
RM		 2316 0xe3ccc103, /* bic ip, ip, #0xc0000000 */
2317 0xe59cc000, /* ldr ip, [ip] */
b38cadfb 2318 0xe3ccc13f, /* bic ip, ip, #0xc000000f */
edccdf7c 2319 0xe12fff1c, /* bx ip */
b38cadfb 2320 /* Third bundle: */
edccdf7c
RM		 2321 0xe320f000, /* nop */
2322 0xe320f000, /* nop */
2323 0xe320f000, /* nop */
b38cadfb
NC		 2324 /* .Lplt_tail: */
2325 0xe50dc004, /* str ip, [sp, #-4] */
2326 /* Fourth bundle: */
edccdf7c
RM		 2327 0xe3ccc103, /* bic ip, ip, #0xc0000000 */
2328 0xe59cc000, /* ldr ip, [ip] */
b38cadfb 2329 0xe3ccc13f, /* bic ip, ip, #0xc000000f */
edccdf7c 2330 0xe12fff1c, /* bx ip */
b38cadfb
NC		 2331};
2332#define ARM_NACL_PLT_TAIL_OFFSET (11 * 4)
2333
2334/* Subsequent entries in a procedure linkage table look like this. */
2335static const bfd_vma elf32_arm_nacl_plt_entry [] =
2336{
2337 0xe300c000, /* movw ip, #:lower16:&GOT[n]-.+8 */
2338 0xe340c000, /* movt ip, #:upper16:&GOT[n]-.+8 */
2339 0xe08cc00f, /* add ip, ip, pc */
2340 0xea000000, /* b .Lplt_tail */
2341};
e5a52504 2342
906e58ca
NC		 2343#define ARM_MAX_FWD_BRANCH_OFFSET ((((1 << 23) - 1) << 2) + 8)
2344#define ARM_MAX_BWD_BRANCH_OFFSET ((-((1 << 23) << 2)) + 8)
2345#define THM_MAX_FWD_BRANCH_OFFSET ((1 << 22) -2 + 4)
2346#define THM_MAX_BWD_BRANCH_OFFSET (-(1 << 22) + 4)
2347#define THM2_MAX_FWD_BRANCH_OFFSET (((1 << 24) - 2) + 4)
2348#define THM2_MAX_BWD_BRANCH_OFFSET (-(1 << 24) + 4)
c5423981
TG		 2349#define THM2_MAX_FWD_COND_BRANCH_OFFSET (((1 << 20) -2) + 4)
2350#define THM2_MAX_BWD_COND_BRANCH_OFFSET (-(1 << 20) + 4)
906e58ca 2351
461a49ca 2352enum stub_insn_type
b38cadfb
NC		 2353{
2354 THUMB16_TYPE = 1,
2355 THUMB32_TYPE,
2356 ARM_TYPE,
2357 DATA_TYPE
2358};
461a49ca 2359
48229727
JB		 2360#define THUMB16_INSN(X) {(X), THUMB16_TYPE, R_ARM_NONE, 0}
2361/* A bit of a hack. A Thumb conditional branch, in which the proper condition
2362 is inserted in arm_build_one_stub(). */
2363#define THUMB16_BCOND_INSN(X) {(X), THUMB16_TYPE, R_ARM_NONE, 1}
2364#define THUMB32_INSN(X) {(X), THUMB32_TYPE, R_ARM_NONE, 0}
d5a67c02
AV		 2365#define THUMB32_MOVT(X) {(X), THUMB32_TYPE, R_ARM_THM_MOVT_ABS, 0}
2366#define THUMB32_MOVW(X) {(X), THUMB32_TYPE, R_ARM_THM_MOVW_ABS_NC, 0}
48229727
JB		 2367#define THUMB32_B_INSN(X, Z) {(X), THUMB32_TYPE, R_ARM_THM_JUMP24, (Z)}
2368#define ARM_INSN(X) {(X), ARM_TYPE, R_ARM_NONE, 0}
2369#define ARM_REL_INSN(X, Z) {(X), ARM_TYPE, R_ARM_JUMP24, (Z)}
2370#define DATA_WORD(X,Y,Z) {(X), DATA_TYPE, (Y), (Z)}
461a49ca
DJ		 2371
2372typedef struct
2373{
b38cadfb
NC		 2374 bfd_vma data;
2375 enum stub_insn_type type;
2376 unsigned int r_type;
2377 int reloc_addend;
461a49ca
DJ		 2378} insn_sequence;
2379
fea2b4d6
CL		 2380/* Arm/Thumb -> Arm/Thumb long branch stub. On V5T and above, use blx
2381 to reach the stub if necessary. */
461a49ca 2382static const insn_sequence elf32_arm_stub_long_branch_any_any[] =
b38cadfb
NC		 2383{
2384 ARM_INSN (0xe51ff004), /* ldr pc, [pc, #-4] */
2385 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(X) */
2386};
906e58ca 2387
fea2b4d6
CL		 2388/* V4T Arm -> Thumb long branch stub. Used on V4T where blx is not
2389 available. */
461a49ca 2390static const insn_sequence elf32_arm_stub_long_branch_v4t_arm_thumb[] =
b38cadfb
NC		 2391{
2392 ARM_INSN (0xe59fc000), /* ldr ip, [pc, #0] */
2393 ARM_INSN (0xe12fff1c), /* bx ip */
2394 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(X) */
2395};
906e58ca 2396
d3626fb0 2397/* Thumb -> Thumb long branch stub. Used on M-profile architectures. */
461a49ca 2398static const insn_sequence elf32_arm_stub_long_branch_thumb_only[] =
b38cadfb
NC		 2399{
2400 THUMB16_INSN (0xb401), /* push {r0} */
2401 THUMB16_INSN (0x4802), /* ldr r0, [pc, #8] */
2402 THUMB16_INSN (0x4684), /* mov ip, r0 */
2403 THUMB16_INSN (0xbc01), /* pop {r0} */
2404 THUMB16_INSN (0x4760), /* bx ip */
2405 THUMB16_INSN (0xbf00), /* nop */
2406 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(X) */
2407};
906e58ca 2408
80c135e5
TP		 2409/* Thumb -> Thumb long branch stub in thumb2 encoding. Used on armv7. */
2410static const insn_sequence elf32_arm_stub_long_branch_thumb2_only[] =
2411{
2412 THUMB32_INSN (0xf85ff000), /* ldr.w pc, [pc, #-0] */
2413 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(x) */
2414};
2415
d5a67c02
AV		 2416/* Thumb -> Thumb long branch stub. Used for PureCode sections on Thumb2
2417 M-profile architectures. */
2418static const insn_sequence elf32_arm_stub_long_branch_thumb2_only_pure[] =
2419{
2420 THUMB32_MOVW (0xf2400c00), /* mov.w ip, R_ARM_MOVW_ABS_NC */
2421 THUMB32_MOVT (0xf2c00c00), /* movt ip, R_ARM_MOVT_ABS << 16 */
2422 THUMB16_INSN (0x4760), /* bx ip */
2423};
2424
d3626fb0
CL		 2425/* V4T Thumb -> Thumb long branch stub. Using the stack is not
2426 allowed. */
2427static const insn_sequence elf32_arm_stub_long_branch_v4t_thumb_thumb[] =
b38cadfb
NC		 2428{
2429 THUMB16_INSN (0x4778), /* bx pc */
2430 THUMB16_INSN (0x46c0), /* nop */
2431 ARM_INSN (0xe59fc000), /* ldr ip, [pc, #0] */
2432 ARM_INSN (0xe12fff1c), /* bx ip */
2433 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(X) */
2434};
d3626fb0 2435
fea2b4d6
CL		 2436/* V4T Thumb -> ARM long branch stub. Used on V4T where blx is not
2437 available. */
461a49ca 2438static const insn_sequence elf32_arm_stub_long_branch_v4t_thumb_arm[] =
b38cadfb
NC		 2439{
2440 THUMB16_INSN (0x4778), /* bx pc */
2441 THUMB16_INSN (0x46c0), /* nop */
2442 ARM_INSN (0xe51ff004), /* ldr pc, [pc, #-4] */
2443 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(X) */
2444};
906e58ca 2445
fea2b4d6
CL		 2446/* V4T Thumb -> ARM short branch stub. Shorter variant of the above
2447 one, when the destination is close enough. */
461a49ca 2448static const insn_sequence elf32_arm_stub_short_branch_v4t_thumb_arm[] =
b38cadfb
NC		 2449{
2450 THUMB16_INSN (0x4778), /* bx pc */
2451 THUMB16_INSN (0x46c0), /* nop */
2452 ARM_REL_INSN (0xea000000, -8), /* b (X-8) */
2453};
c820be07 2454
cf3eccff 2455/* ARM/Thumb -> ARM long branch stub, PIC. On V5T and above, use
fea2b4d6 2456 blx to reach the stub if necessary. */
cf3eccff 2457static const insn_sequence elf32_arm_stub_long_branch_any_arm_pic[] =
b38cadfb
NC		 2458{
2459 ARM_INSN (0xe59fc000), /* ldr ip, [pc] */
2460 ARM_INSN (0xe08ff00c), /* add pc, pc, ip */
2461 DATA_WORD (0, R_ARM_REL32, -4), /* dcd R_ARM_REL32(X-4) */
2462};
906e58ca 2463
cf3eccff
DJ		 2464/* ARM/Thumb -> Thumb long branch stub, PIC. On V5T and above, use
2465 blx to reach the stub if necessary. We can not add into pc;
2466 it is not guaranteed to mode switch (different in ARMv6 and
2467 ARMv7). */
2468static const insn_sequence elf32_arm_stub_long_branch_any_thumb_pic[] =
b38cadfb
NC		 2469{
2470 ARM_INSN (0xe59fc004), /* ldr ip, [pc, #4] */
2471 ARM_INSN (0xe08fc00c), /* add ip, pc, ip */
2472 ARM_INSN (0xe12fff1c), /* bx ip */
2473 DATA_WORD (0, R_ARM_REL32, 0), /* dcd R_ARM_REL32(X) */
2474};
cf3eccff 2475
ebe24dd4
CL		 2476/* V4T ARM -> ARM long branch stub, PIC. */
2477static const insn_sequence elf32_arm_stub_long_branch_v4t_arm_thumb_pic[] =
b38cadfb
NC		 2478{
2479 ARM_INSN (0xe59fc004), /* ldr ip, [pc, #4] */
2480 ARM_INSN (0xe08fc00c), /* add ip, pc, ip */
2481 ARM_INSN (0xe12fff1c), /* bx ip */
2482 DATA_WORD (0, R_ARM_REL32, 0), /* dcd R_ARM_REL32(X) */
2483};
ebe24dd4
CL		 2484
2485/* V4T Thumb -> ARM long branch stub, PIC. */
2486static const insn_sequence elf32_arm_stub_long_branch_v4t_thumb_arm_pic[] =
b38cadfb
NC		 2487{
2488 THUMB16_INSN (0x4778), /* bx pc */
2489 THUMB16_INSN (0x46c0), /* nop */
2490 ARM_INSN (0xe59fc000), /* ldr ip, [pc, #0] */
2491 ARM_INSN (0xe08cf00f), /* add pc, ip, pc */
2492 DATA_WORD (0, R_ARM_REL32, -4), /* dcd R_ARM_REL32(X) */
2493};
ebe24dd4 2494
d3626fb0
CL		 2495/* Thumb -> Thumb long branch stub, PIC. Used on M-profile
2496 architectures. */
ebe24dd4 2497static const insn_sequence elf32_arm_stub_long_branch_thumb_only_pic[] =
b38cadfb
NC		 2498{
2499 THUMB16_INSN (0xb401), /* push {r0} */
2500 THUMB16_INSN (0x4802), /* ldr r0, [pc, #8] */
2501 THUMB16_INSN (0x46fc), /* mov ip, pc */
2502 THUMB16_INSN (0x4484), /* add ip, r0 */
2503 THUMB16_INSN (0xbc01), /* pop {r0} */
2504 THUMB16_INSN (0x4760), /* bx ip */
2505 DATA_WORD (0, R_ARM_REL32, 4), /* dcd R_ARM_REL32(X) */
2506};
ebe24dd4 2507
d3626fb0
CL		 2508/* V4T Thumb -> Thumb long branch stub, PIC. Using the stack is not
2509 allowed. */
2510static const insn_sequence elf32_arm_stub_long_branch_v4t_thumb_thumb_pic[] =
b38cadfb
NC		 2511{
2512 THUMB16_INSN (0x4778), /* bx pc */
2513 THUMB16_INSN (0x46c0), /* nop */
2514 ARM_INSN (0xe59fc004), /* ldr ip, [pc, #4] */
2515 ARM_INSN (0xe08fc00c), /* add ip, pc, ip */
2516 ARM_INSN (0xe12fff1c), /* bx ip */
2517 DATA_WORD (0, R_ARM_REL32, 0), /* dcd R_ARM_REL32(X) */
2518};
d3626fb0 2519
0855e32b
NS		 2520/* Thumb2/ARM -> TLS trampoline. Lowest common denominator, which is a
2521 long PIC stub. We can use r1 as a scratch -- and cannot use ip. */
2522static const insn_sequence elf32_arm_stub_long_branch_any_tls_pic[] =
2523{
b38cadfb
NC		 2524 ARM_INSN (0xe59f1000), /* ldr r1, [pc] */
2525 ARM_INSN (0xe08ff001), /* add pc, pc, r1 */
2526 DATA_WORD (0, R_ARM_REL32, -4), /* dcd R_ARM_REL32(X-4) */
0855e32b
NS		 2527};
2528
2529/* V4T Thumb -> TLS trampoline. lowest common denominator, which is a
2530 long PIC stub. We can use r1 as a scratch -- and cannot use ip. */
2531static const insn_sequence elf32_arm_stub_long_branch_v4t_thumb_tls_pic[] =
2532{
b38cadfb
NC		 2533 THUMB16_INSN (0x4778), /* bx pc */
2534 THUMB16_INSN (0x46c0), /* nop */
2535 ARM_INSN (0xe59f1000), /* ldr r1, [pc, #0] */
2536 ARM_INSN (0xe081f00f), /* add pc, r1, pc */
2537 DATA_WORD (0, R_ARM_REL32, -4), /* dcd R_ARM_REL32(X) */
0855e32b
NS		 2538};
2539
7a89b94e
NC		 2540/* NaCl ARM -> ARM long branch stub. */
2541static const insn_sequence elf32_arm_stub_long_branch_arm_nacl[] =
2542{
2543 ARM_INSN (0xe59fc00c), /* ldr ip, [pc, #12] */
2544 ARM_INSN (0xe3ccc13f), /* bic ip, ip, #0xc000000f */
2545 ARM_INSN (0xe12fff1c), /* bx ip */
2546 ARM_INSN (0xe320f000), /* nop */
2547 ARM_INSN (0xe125be70), /* bkpt 0x5be0 */
2548 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(X) */
2549 DATA_WORD (0, R_ARM_NONE, 0), /* .word 0 */
2550 DATA_WORD (0, R_ARM_NONE, 0), /* .word 0 */
2551};
2552
2553/* NaCl ARM -> ARM long branch stub, PIC. */
2554static const insn_sequence elf32_arm_stub_long_branch_arm_nacl_pic[] =
2555{
2556 ARM_INSN (0xe59fc00c), /* ldr ip, [pc, #12] */
2557 ARM_INSN (0xe08cc00f), /* add ip, ip, pc */
2558 ARM_INSN (0xe3ccc13f), /* bic ip, ip, #0xc000000f */
2559 ARM_INSN (0xe12fff1c), /* bx ip */
2560 ARM_INSN (0xe125be70), /* bkpt 0x5be0 */
2561 DATA_WORD (0, R_ARM_REL32, 8), /* dcd R_ARM_REL32(X+8) */
2562 DATA_WORD (0, R_ARM_NONE, 0), /* .word 0 */
2563 DATA_WORD (0, R_ARM_NONE, 0), /* .word 0 */
2564};
2565
4ba2ef8f
TP		 2566/* Stub used for transition to secure state (aka SG veneer). */
2567static const insn_sequence elf32_arm_stub_cmse_branch_thumb_only[] =
2568{
2569 THUMB32_INSN (0xe97fe97f), /* sg. */
2570 THUMB32_B_INSN (0xf000b800, -4), /* b.w original_branch_dest. */
2571};
2572
7a89b94e 2573
48229727
JB		 2574/* Cortex-A8 erratum-workaround stubs. */
2575
2576/* Stub used for conditional branches (which may be beyond +/-1MB away, so we
2577 can't use a conditional branch to reach this stub). */
2578
2579static const insn_sequence elf32_arm_stub_a8_veneer_b_cond[] =
b38cadfb
NC		 2580{
2581 THUMB16_BCOND_INSN (0xd001), /* b<cond>.n true. */
2582 THUMB32_B_INSN (0xf000b800, -4), /* b.w insn_after_original_branch. */
2583 THUMB32_B_INSN (0xf000b800, -4) /* true: b.w original_branch_dest. */
2584};
48229727
JB		 2585
2586/* Stub used for b.w and bl.w instructions. */
2587
2588static const insn_sequence elf32_arm_stub_a8_veneer_b[] =
b38cadfb
NC		 2589{
2590 THUMB32_B_INSN (0xf000b800, -4) /* b.w original_branch_dest. */
2591};
48229727
JB		 2592
2593static const insn_sequence elf32_arm_stub_a8_veneer_bl[] =
b38cadfb
NC		 2594{
2595 THUMB32_B_INSN (0xf000b800, -4) /* b.w original_branch_dest. */
2596};
48229727
JB		 2597
2598/* Stub used for Thumb-2 blx.w instructions. We modified the original blx.w
2599 instruction (which switches to ARM mode) to point to this stub. Jump to the
2600 real destination using an ARM-mode branch. */
2601
2602static const insn_sequence elf32_arm_stub_a8_veneer_blx[] =
b38cadfb
NC		 2603{
2604 ARM_REL_INSN (0xea000000, -8) /* b original_branch_dest. */
2605};
48229727 2606
9553db3c
NC		 2607/* For each section group there can be a specially created linker section
2608 to hold the stubs for that group. The name of the stub section is based
2609 upon the name of another section within that group with the suffix below
2610 applied.
2611
2612 PR 13049: STUB_SUFFIX used to be ".stub", but this allowed the user to
2613 create what appeared to be a linker stub section when it actually
2614 contained user code/data. For example, consider this fragment:
b38cadfb 2615
9553db3c
NC		 2616 const char * stubborn_problems[] = { "np" };
2617
2618 If this is compiled with "-fPIC -fdata-sections" then gcc produces a
2619 section called:
2620
2621 .data.rel.local.stubborn_problems
2622
2623 This then causes problems in arm32_arm_build_stubs() as it triggers:
2624
2625 // Ignore non-stub sections.
2626 if (!strstr (stub_sec->name, STUB_SUFFIX))
2627 continue;
2628
2629 And so the section would be ignored instead of being processed. Hence
2630 the change in definition of STUB_SUFFIX to a name that cannot be a valid
2631 C identifier. */
2632#define STUB_SUFFIX ".__stub"
906e58ca 2633
738a79f6
CL		 2634/* One entry per long/short branch stub defined above. */
2635#define DEF_STUBS \
2636 DEF_STUB(long_branch_any_any) \
2637 DEF_STUB(long_branch_v4t_arm_thumb) \
2638 DEF_STUB(long_branch_thumb_only) \
2639 DEF_STUB(long_branch_v4t_thumb_thumb) \
2640 DEF_STUB(long_branch_v4t_thumb_arm) \
2641 DEF_STUB(short_branch_v4t_thumb_arm) \
2642 DEF_STUB(long_branch_any_arm_pic) \
2643 DEF_STUB(long_branch_any_thumb_pic) \
2644 DEF_STUB(long_branch_v4t_thumb_thumb_pic) \
2645 DEF_STUB(long_branch_v4t_arm_thumb_pic) \
2646 DEF_STUB(long_branch_v4t_thumb_arm_pic) \
48229727 2647 DEF_STUB(long_branch_thumb_only_pic) \
0855e32b
NS		 2648 DEF_STUB(long_branch_any_tls_pic) \
2649 DEF_STUB(long_branch_v4t_thumb_tls_pic) \
7a89b94e
NC		 2650 DEF_STUB(long_branch_arm_nacl) \
2651 DEF_STUB(long_branch_arm_nacl_pic) \
4ba2ef8f 2652 DEF_STUB(cmse_branch_thumb_only) \
48229727
JB		 2653 DEF_STUB(a8_veneer_b_cond) \
2654 DEF_STUB(a8_veneer_b) \
2655 DEF_STUB(a8_veneer_bl) \
80c135e5
TP		 2656 DEF_STUB(a8_veneer_blx) \
2657 DEF_STUB(long_branch_thumb2_only) \
d5a67c02 2658 DEF_STUB(long_branch_thumb2_only_pure)
738a79f6
CL		 2659
2660#define DEF_STUB(x) arm_stub_##x,
b38cadfb
NC		 2661enum elf32_arm_stub_type
2662{
906e58ca 2663 arm_stub_none,
738a79f6 2664 DEF_STUBS
4f4faa4d 2665 max_stub_type
738a79f6
CL		 2666};
2667#undef DEF_STUB
2668
8d9d9490
TP		 2669/* Note the first a8_veneer type. */
2670const unsigned arm_stub_a8_veneer_lwm = arm_stub_a8_veneer_b_cond;
2671
738a79f6
CL		 2672typedef struct
2673{
d3ce72d0 2674 const insn_sequence* template_sequence;
738a79f6
CL		 2675 int template_size;
2676} stub_def;
2677
2678#define DEF_STUB(x) {elf32_arm_stub_##x, ARRAY_SIZE(elf32_arm_stub_##x)},
b38cadfb
NC		 2679static const stub_def stub_definitions[] =
2680{
738a79f6
CL		 2681 {NULL, 0},
2682 DEF_STUBS
906e58ca
NC		 2683};
2684
2685struct elf32_arm_stub_hash_entry
2686{
2687 /* Base hash table entry structure. */
2688 struct bfd_hash_entry root;
2689
2690 /* The stub section. */
2691 asection *stub_sec;
2692
2693 /* Offset within stub_sec of the beginning of this stub. */
2694 bfd_vma stub_offset;
2695
2696 /* Given the symbol's value and its section we can determine its final
2697 value when building the stubs (so the stub knows where to jump). */
2698 bfd_vma target_value;
2699 asection *target_section;
2700
8d9d9490
TP		 2701 /* Same as above but for the source of the branch to the stub. Used for
2702 Cortex-A8 erratum workaround to patch it to branch to the stub. As
2703 such, source section does not need to be recorded since Cortex-A8 erratum
2704 workaround stubs are only generated when both source and target are in the
2705 same section. */
2706 bfd_vma source_value;
48229727
JB		 2707
2708 /* The instruction which caused this stub to be generated (only valid for
2709 Cortex-A8 erratum workaround stubs at present). */
2710 unsigned long orig_insn;
2711
461a49ca 2712 /* The stub type. */
906e58ca 2713 enum elf32_arm_stub_type stub_type;
461a49ca
DJ		 2714 /* Its encoding size in bytes. */
2715 int stub_size;
2716 /* Its template. */
2717 const insn_sequence *stub_template;
2718 /* The size of the template (number of entries). */
2719 int stub_template_size;
906e58ca
NC		 2720
2721 /* The symbol table entry, if any, that this was derived from. */
2722 struct elf32_arm_link_hash_entry *h;
2723
35fc36a8
RS		 2724 /* Type of branch. */
2725 enum arm_st_branch_type branch_type;
906e58ca
NC		 2726
2727 /* Where this stub is being called from, or, in the case of combined
2728 stub sections, the first input section in the group. */
2729 asection *id_sec;
7413f23f
DJ		 2730
2731 /* The name for the local symbol at the start of this stub. The
2732 stub name in the hash table has to be unique; this does not, so
2733 it can be friendlier. */
2734 char *output_name;
906e58ca
NC		 2735};
2736
e489d0ae
PB		 2737/* Used to build a map of a section. This is required for mixed-endian
2738 code/data. */
2739
2740typedef struct elf32_elf_section_map
2741{
2742 bfd_vma vma;
2743 char type;
2744}
2745elf32_arm_section_map;
2746
c7b8f16e
JB		 2747/* Information about a VFP11 erratum veneer, or a branch to such a veneer. */
2748
2749typedef enum
2750{
2751 VFP11_ERRATUM_BRANCH_TO_ARM_VENEER,
2752 VFP11_ERRATUM_BRANCH_TO_THUMB_VENEER,
2753 VFP11_ERRATUM_ARM_VENEER,
2754 VFP11_ERRATUM_THUMB_VENEER
2755}
2756elf32_vfp11_erratum_type;
2757
2758typedef struct elf32_vfp11_erratum_list
2759{
2760 struct elf32_vfp11_erratum_list *next;
2761 bfd_vma vma;
2762 union
2763 {
2764 struct
2765 {
2766 struct elf32_vfp11_erratum_list *veneer;
2767 unsigned int vfp_insn;
2768 } b;
2769 struct
2770 {
2771 struct elf32_vfp11_erratum_list *branch;
2772 unsigned int id;
2773 } v;
2774 } u;
2775 elf32_vfp11_erratum_type type;
2776}
2777elf32_vfp11_erratum_list;
2778
a504d23a
LA		 2779/* Information about a STM32L4XX erratum veneer, or a branch to such a
2780 veneer. */
2781typedef enum
2782{
2783 STM32L4XX_ERRATUM_BRANCH_TO_VENEER,
2784 STM32L4XX_ERRATUM_VENEER
2785}
2786elf32_stm32l4xx_erratum_type;
2787
2788typedef struct elf32_stm32l4xx_erratum_list
2789{
2790 struct elf32_stm32l4xx_erratum_list *next;
2791 bfd_vma vma;
2792 union
2793 {
2794 struct
2795 {
2796 struct elf32_stm32l4xx_erratum_list *veneer;
2797 unsigned int insn;
2798 } b;
2799 struct
2800 {
2801 struct elf32_stm32l4xx_erratum_list *branch;
2802 unsigned int id;
2803 } v;
2804 } u;
2805 elf32_stm32l4xx_erratum_type type;
2806}
2807elf32_stm32l4xx_erratum_list;
2808
2468f9c9
PB		 2809typedef enum
2810{
2811 DELETE_EXIDX_ENTRY,
2812 INSERT_EXIDX_CANTUNWIND_AT_END
2813}
2814arm_unwind_edit_type;
2815
2816/* A (sorted) list of edits to apply to an unwind table. */
2817typedef struct arm_unwind_table_edit
2818{
2819 arm_unwind_edit_type type;
2820 /* Note: we sometimes want to insert an unwind entry corresponding to a
2821 section different from the one we're currently writing out, so record the
2822 (text) section this edit relates to here. */
2823 asection *linked_section;
2824 unsigned int index;
2825 struct arm_unwind_table_edit *next;
2826}
2827arm_unwind_table_edit;
2828
8e3de13a 2829typedef struct _arm_elf_section_data
e489d0ae 2830{
2468f9c9 2831 /* Information about mapping symbols. */
e489d0ae 2832 struct bfd_elf_section_data elf;
8e3de13a 2833 unsigned int mapcount;
c7b8f16e 2834 unsigned int mapsize;
e489d0ae 2835 elf32_arm_section_map *map;
2468f9c9 2836 /* Information about CPU errata. */
c7b8f16e
JB		 2837 unsigned int erratumcount;
2838 elf32_vfp11_erratum_list *erratumlist;
a504d23a
LA		 2839 unsigned int stm32l4xx_erratumcount;
2840 elf32_stm32l4xx_erratum_list *stm32l4xx_erratumlist;
491d01d3 2841 unsigned int additional_reloc_count;
2468f9c9
PB		 2842 /* Information about unwind tables. */
2843 union
2844 {
2845 /* Unwind info attached to a text section. */
2846 struct
2847 {
2848 asection *arm_exidx_sec;
2849 } text;
2850
2851 /* Unwind info attached to an .ARM.exidx section. */
2852 struct
2853 {
2854 arm_unwind_table_edit *unwind_edit_list;
2855 arm_unwind_table_edit *unwind_edit_tail;
2856 } exidx;
2857 } u;
8e3de13a
NC		 2858}
2859_arm_elf_section_data;
e489d0ae
PB		 2860
2861#define elf32_arm_section_data(sec) \
8e3de13a 2862 ((_arm_elf_section_data *) elf_section_data (sec))
e489d0ae 2863
48229727
JB		 2864/* A fix which might be required for Cortex-A8 Thumb-2 branch/TLB erratum.
2865 These fixes are subject to a relaxation procedure (in elf32_arm_size_stubs),
2866 so may be created multiple times: we use an array of these entries whilst
2867 relaxing which we can refresh easily, then create stubs for each potentially
2868 erratum-triggering instruction once we've settled on a solution. */
2869
b38cadfb
NC		 2870struct a8_erratum_fix
2871{
48229727
JB		 2872 bfd *input_bfd;
2873 asection *section;
2874 bfd_vma offset;
8d9d9490 2875 bfd_vma target_offset;
48229727
JB		 2876 unsigned long orig_insn;
2877 char *stub_name;
2878 enum elf32_arm_stub_type stub_type;
35fc36a8 2879 enum arm_st_branch_type branch_type;
48229727
JB		 2880};
2881
2882/* A table of relocs applied to branches which might trigger Cortex-A8
2883 erratum. */
2884
b38cadfb
NC		 2885struct a8_erratum_reloc
2886{
48229727
JB		 2887 bfd_vma from;
2888 bfd_vma destination;
92750f34
DJ		 2889 struct elf32_arm_link_hash_entry *hash;
2890 const char *sym_name;
48229727 2891 unsigned int r_type;
35fc36a8 2892 enum arm_st_branch_type branch_type;
48229727
JB		 2893 bfd_boolean non_a8_stub;
2894};
2895
ba93b8ac
DJ		 2896/* The size of the thread control block. */
2897#define TCB_SIZE 8
2898
34e77a92
RS		 2899/* ARM-specific information about a PLT entry, over and above the usual
2900 gotplt_union. */
b38cadfb
NC		 2901struct arm_plt_info
2902{
34e77a92
RS		 2903 /* We reference count Thumb references to a PLT entry separately,
2904 so that we can emit the Thumb trampoline only if needed. */
2905 bfd_signed_vma thumb_refcount;
2906
2907 /* Some references from Thumb code may be eliminated by BL->BLX
2908 conversion, so record them separately. */
2909 bfd_signed_vma maybe_thumb_refcount;
2910
2911 /* How many of the recorded PLT accesses were from non-call relocations.
2912 This information is useful when deciding whether anything takes the
2913 address of an STT_GNU_IFUNC PLT. A value of 0 means that all
2914 non-call references to the function should resolve directly to the
2915 real runtime target. */
2916 unsigned int noncall_refcount;
2917
2918 /* Since PLT entries have variable size if the Thumb prologue is
2919 used, we need to record the index into .got.plt instead of
2920 recomputing it from the PLT offset. */
2921 bfd_signed_vma got_offset;
2922};
2923
2924/* Information about an .iplt entry for a local STT_GNU_IFUNC symbol. */
b38cadfb
NC		 2925struct arm_local_iplt_info
2926{
34e77a92
RS		 2927 /* The information that is usually found in the generic ELF part of
2928 the hash table entry. */
2929 union gotplt_union root;
2930
2931 /* The information that is usually found in the ARM-specific part of
2932 the hash table entry. */
2933 struct arm_plt_info arm;
2934
2935 /* A list of all potential dynamic relocations against this symbol. */
2936 struct elf_dyn_relocs *dyn_relocs;
2937};
2938
0ffa91dd 2939struct elf_arm_obj_tdata
ba93b8ac
DJ		 2940{
2941 struct elf_obj_tdata root;
2942
2943 /* tls_type for each local got entry. */
2944 char *local_got_tls_type;
ee065d83 2945
0855e32b
NS		 2946 /* GOTPLT entries for TLS descriptors. */
2947 bfd_vma *local_tlsdesc_gotent;
2948
34e77a92
RS		 2949 /* Information for local symbols that need entries in .iplt. */
2950 struct arm_local_iplt_info **local_iplt;
2951
bf21ed78
MS		 2952 /* Zero to warn when linking objects with incompatible enum sizes. */
2953 int no_enum_size_warning;
a9dc9481
JM		 2954
2955 /* Zero to warn when linking objects with incompatible wchar_t sizes. */
2956 int no_wchar_size_warning;
ba93b8ac
DJ		 2957};
2958
0ffa91dd
NC		 2959#define elf_arm_tdata(bfd) \
2960 ((struct elf_arm_obj_tdata *) (bfd)->tdata.any)
ba93b8ac 2961
0ffa91dd
NC		 2962#define elf32_arm_local_got_tls_type(bfd) \
2963 (elf_arm_tdata (bfd)->local_got_tls_type)
2964
0855e32b
NS		 2965#define elf32_arm_local_tlsdesc_gotent(bfd) \
2966 (elf_arm_tdata (bfd)->local_tlsdesc_gotent)
2967
34e77a92
RS		 2968#define elf32_arm_local_iplt(bfd) \
2969 (elf_arm_tdata (bfd)->local_iplt)
2970
0ffa91dd
NC		 2971#define is_arm_elf(bfd) \
2972 (bfd_get_flavour (bfd) == bfd_target_elf_flavour \
2973 && elf_tdata (bfd) != NULL \
4dfe6ac6 2974 && elf_object_id (bfd) == ARM_ELF_DATA)
ba93b8ac
DJ		 2975
2976static bfd_boolean
2977elf32_arm_mkobject (bfd *abfd)
2978{
0ffa91dd 2979 return bfd_elf_allocate_object (abfd, sizeof (struct elf_arm_obj_tdata),
4dfe6ac6 2980 ARM_ELF_DATA);
ba93b8ac
DJ		 2981}
2982
ba93b8ac
DJ		 2983#define elf32_arm_hash_entry(ent) ((struct elf32_arm_link_hash_entry *)(ent))
2984
ba96a88f 2985/* Arm ELF linker hash entry. */
252b5132 2986struct elf32_arm_link_hash_entry
b38cadfb
NC		 2987{
2988 struct elf_link_hash_entry root;
252b5132 2989
b38cadfb
NC		 2990 /* Track dynamic relocs copied for this symbol. */
2991 struct elf_dyn_relocs *dyn_relocs;
b7693d02 2992
b38cadfb
NC		 2993 /* ARM-specific PLT information. */
2994 struct arm_plt_info plt;
ba93b8ac
DJ		 2995
2996#define GOT_UNKNOWN 0
2997#define GOT_NORMAL 1
2998#define GOT_TLS_GD 2
2999#define GOT_TLS_IE 4
0855e32b
NS		 3000#define GOT_TLS_GDESC 8
3001#define GOT_TLS_GD_ANY_P(type) ((type & GOT_TLS_GD) || (type & GOT_TLS_GDESC))
b38cadfb 3002 unsigned int tls_type : 8;
34e77a92 3003
b38cadfb
NC		 3004 /* True if the symbol's PLT entry is in .iplt rather than .plt. */
3005 unsigned int is_iplt : 1;
34e77a92 3006
b38cadfb 3007 unsigned int unused : 23;
a4fd1a8e 3008
b38cadfb
NC		 3009 /* Offset of the GOTPLT entry reserved for the TLS descriptor,
3010 starting at the end of the jump table. */
3011 bfd_vma tlsdesc_got;
0855e32b 3012
b38cadfb
NC		 3013 /* The symbol marking the real symbol location for exported thumb
3014 symbols with Arm stubs. */
3015 struct elf_link_hash_entry *export_glue;
906e58ca 3016
b38cadfb 3017 /* A pointer to the most recently used stub hash entry against this
8029a119 3018 symbol. */
b38cadfb
NC		 3019 struct elf32_arm_stub_hash_entry *stub_cache;
3020};
252b5132 3021
252b5132 3022/* Traverse an arm ELF linker hash table. */
252b5132
RH		 3023#define elf32_arm_link_hash_traverse(table, func, info) \
3024 (elf_link_hash_traverse \
3025 (&(table)->root, \
b7693d02 3026 (bfd_boolean (*) (struct elf_link_hash_entry *, void *)) (func), \
252b5132
RH		 3027 (info)))
3028
3029/* Get the ARM elf linker hash table from a link_info structure. */
3030#define elf32_arm_hash_table(info) \
4dfe6ac6
NC		 3031 (elf_hash_table_id ((struct elf_link_hash_table *) ((info)->hash)) \
3032 == ARM_ELF_DATA ? ((struct elf32_arm_link_hash_table *) ((info)->hash)) : NULL)
252b5132 3033
906e58ca
NC		 3034#define arm_stub_hash_lookup(table, string, create, copy) \
3035 ((struct elf32_arm_stub_hash_entry *) \
3036 bfd_hash_lookup ((table), (string), (create), (copy)))
3037
21d799b5
NC		 3038/* Array to keep track of which stub sections have been created, and
3039 information on stub grouping. */
3040struct map_stub
3041{
3042 /* This is the section to which stubs in the group will be
3043 attached. */
3044 asection *link_sec;
3045 /* The stub section. */
3046 asection *stub_sec;
3047};
3048
0855e32b
NS		 3049#define elf32_arm_compute_jump_table_size(htab) \
3050 ((htab)->next_tls_desc_index * 4)
3051
9b485d32 3052/* ARM ELF linker hash table. */
252b5132 3053struct elf32_arm_link_hash_table
906e58ca
NC		 3054{
3055 /* The main hash table. */
3056 struct elf_link_hash_table root;
252b5132 3057
906e58ca
NC		 3058 /* The size in bytes of the section containing the Thumb-to-ARM glue. */
3059 bfd_size_type thumb_glue_size;
252b5132 3060
906e58ca
NC		 3061 /* The size in bytes of the section containing the ARM-to-Thumb glue. */
3062 bfd_size_type arm_glue_size;
252b5132 3063
906e58ca
NC		 3064 /* The size in bytes of section containing the ARMv4 BX veneers. */
3065 bfd_size_type bx_glue_size;
845b51d6 3066
906e58ca
NC		 3067 /* Offsets of ARMv4 BX veneers. Bit1 set if present, and Bit0 set when
3068 veneer has been populated. */
3069 bfd_vma bx_glue_offset[15];
845b51d6 3070
906e58ca
NC		 3071 /* The size in bytes of the section containing glue for VFP11 erratum
3072 veneers. */
3073 bfd_size_type vfp11_erratum_glue_size;
c7b8f16e 3074
a504d23a
LA		 3075 /* The size in bytes of the section containing glue for STM32L4XX erratum
3076 veneers. */
3077 bfd_size_type stm32l4xx_erratum_glue_size;
3078
48229727
JB		 3079 /* A table of fix locations for Cortex-A8 Thumb-2 branch/TLB erratum. This
3080 holds Cortex-A8 erratum fix locations between elf32_arm_size_stubs() and
3081 elf32_arm_write_section(). */
3082 struct a8_erratum_fix *a8_erratum_fixes;
3083 unsigned int num_a8_erratum_fixes;
3084
906e58ca
NC		 3085 /* An arbitrary input BFD chosen to hold the glue sections. */
3086 bfd * bfd_of_glue_owner;
ba96a88f 3087
906e58ca
NC		 3088 /* Nonzero to output a BE8 image. */
3089 int byteswap_code;
e489d0ae 3090
906e58ca
NC		 3091 /* Zero if R_ARM_TARGET1 means R_ARM_ABS32.
3092 Nonzero if R_ARM_TARGET1 means R_ARM_REL32. */
3093 int target1_is_rel;
9c504268 3094
906e58ca
NC		 3095 /* The relocation to use for R_ARM_TARGET2 relocations. */
3096 int target2_reloc;
eb043451 3097
906e58ca
NC		 3098 /* 0 = Ignore R_ARM_V4BX.
3099 1 = Convert BX to MOV PC.
3100 2 = Generate v4 interworing stubs. */
3101 int fix_v4bx;
319850b4 3102
48229727
JB		 3103 /* Whether we should fix the Cortex-A8 Thumb-2 branch/TLB erratum. */
3104 int fix_cortex_a8;
3105
2de70689
MGD		 3106 /* Whether we should fix the ARM1176 BLX immediate issue. */
3107 int fix_arm1176;
3108
906e58ca
NC		 3109 /* Nonzero if the ARM/Thumb BLX instructions are available for use. */
3110 int use_blx;
33bfe774 3111
906e58ca
NC		 3112 /* What sort of code sequences we should look for which may trigger the
3113 VFP11 denorm erratum. */
3114 bfd_arm_vfp11_fix vfp11_fix;
c7b8f16e 3115
906e58ca
NC		 3116 /* Global counter for the number of fixes we have emitted. */
3117 int num_vfp11_fixes;
c7b8f16e 3118
a504d23a
LA		 3119 /* What sort of code sequences we should look for which may trigger the
3120 STM32L4XX erratum. */
3121 bfd_arm_stm32l4xx_fix stm32l4xx_fix;
3122
3123 /* Global counter for the number of fixes we have emitted. */
3124 int num_stm32l4xx_fixes;
3125
906e58ca
NC		 3126 /* Nonzero to force PIC branch veneers. */
3127 int pic_veneer;
27e55c4d 3128
906e58ca
NC		 3129 /* The number of bytes in the initial entry in the PLT. */
3130 bfd_size_type plt_header_size;
e5a52504 3131
906e58ca
NC		 3132 /* The number of bytes in the subsequent PLT etries. */
3133 bfd_size_type plt_entry_size;
e5a52504 3134
906e58ca
NC		 3135 /* True if the target system is VxWorks. */
3136 int vxworks_p;
00a97672 3137
906e58ca
NC		 3138 /* True if the target system is Symbian OS. */
3139 int symbian_p;
e5a52504 3140
b38cadfb
NC		 3141 /* True if the target system is Native Client. */
3142 int nacl_p;
3143
906e58ca
NC		 3144 /* True if the target uses REL relocations. */
3145 int use_rel;
4e7fd91e 3146
54ddd295
TP		 3147 /* Nonzero if import library must be a secure gateway import library
3148 as per ARMv8-M Security Extensions. */
3149 int cmse_implib;
3150
0955507f
TP		 3151 /* The import library whose symbols' address must remain stable in
3152 the import library generated. */
3153 bfd *in_implib_bfd;
3154
0855e32b
NS		 3155 /* The index of the next unused R_ARM_TLS_DESC slot in .rel.plt. */
3156 bfd_vma next_tls_desc_index;
3157
3158 /* How many R_ARM_TLS_DESC relocations were generated so far. */
3159 bfd_vma num_tls_desc;
3160
906e58ca
NC		 3161 /* The (unloaded but important) VxWorks .rela.plt.unloaded section. */
3162 asection *srelplt2;
00a97672 3163
0855e32b
NS		 3164 /* The offset into splt of the PLT entry for the TLS descriptor
3165 resolver. Special values are 0, if not necessary (or not found
3166 to be necessary yet), and -1 if needed but not determined
3167 yet. */
3168 bfd_vma dt_tlsdesc_plt;
3169
3170 /* The offset into sgot of the GOT entry used by the PLT entry
3171 above. */
b38cadfb 3172 bfd_vma dt_tlsdesc_got;
0855e32b
NS		 3173
3174 /* Offset in .plt section of tls_arm_trampoline. */
3175 bfd_vma tls_trampoline;
3176
906e58ca
NC		 3177 /* Data for R_ARM_TLS_LDM32 relocations. */
3178 union
3179 {
3180 bfd_signed_vma refcount;
3181 bfd_vma offset;
3182 } tls_ldm_got;
b7693d02 3183
87d72d41
AM		 3184 /* Small local sym cache. */
3185 struct sym_cache sym_cache;
906e58ca
NC		 3186
3187 /* For convenience in allocate_dynrelocs. */
3188 bfd * obfd;
3189
0855e32b
NS		 3190 /* The amount of space used by the reserved portion of the sgotplt
3191 section, plus whatever space is used by the jump slots. */
3192 bfd_vma sgotplt_jump_table_size;
3193
906e58ca
NC		 3194 /* The stub hash table. */
3195 struct bfd_hash_table stub_hash_table;
3196
3197 /* Linker stub bfd. */
3198 bfd *stub_bfd;
3199
3200 /* Linker call-backs. */
6bde4c52
TP		 3201 asection * (*add_stub_section) (const char *, asection *, asection *,
3202 unsigned int);
906e58ca
NC		 3203 void (*layout_sections_again) (void);
3204
3205 /* Array to keep track of which stub sections have been created, and
3206 information on stub grouping. */
21d799b5 3207 struct map_stub *stub_group;
906e58ca 3208
4ba2ef8f
TP		 3209 /* Input stub section holding secure gateway veneers. */
3210 asection *cmse_stub_sec;
3211
0955507f
TP		 3212 /* Offset in cmse_stub_sec where new SG veneers (not in input import library)
3213 start to be allocated. */
3214 bfd_vma new_cmse_stub_offset;
3215
fe33d2fa 3216 /* Number of elements in stub_group. */
7292b3ac 3217 unsigned int top_id;
fe33d2fa 3218
906e58ca
NC		 3219 /* Assorted information used by elf32_arm_size_stubs. */
3220 unsigned int bfd_count;
7292b3ac 3221 unsigned int top_index;
906e58ca
NC		 3222 asection **input_list;
3223};
252b5132 3224
a504d23a
LA		 3225static inline int
3226ctz (unsigned int mask)
3227{
3228#if GCC_VERSION >= 3004
3229 return __builtin_ctz (mask);
3230#else
3231 unsigned int i;
3232
3233 for (i = 0; i < 8 * sizeof (mask); i++)
3234 {
3235 if (mask & 0x1)
3236 break;
3237 mask = (mask >> 1);
3238 }
3239 return i;
3240#endif
3241}
3242
3243static inline int
b25e998d 3244elf32_arm_popcount (unsigned int mask)
a504d23a
LA		 3245{
3246#if GCC_VERSION >= 3004
3247 return __builtin_popcount (mask);
3248#else
b25e998d
CG		 3249 unsigned int i;
3250 int sum = 0;
a504d23a
LA		 3251
3252 for (i = 0; i < 8 * sizeof (mask); i++)
3253 {
3254 if (mask & 0x1)
3255 sum++;
3256 mask = (mask >> 1);
3257 }
3258 return sum;
3259#endif
3260}
3261
780a67af
NC		 3262/* Create an entry in an ARM ELF linker hash table. */
3263
3264static struct bfd_hash_entry *
57e8b36a 3265elf32_arm_link_hash_newfunc (struct bfd_hash_entry * entry,
99059e56
RM		 3266 struct bfd_hash_table * table,
3267 const char * string)
780a67af
NC		 3268{
3269 struct elf32_arm_link_hash_entry * ret =
3270 (struct elf32_arm_link_hash_entry *) entry;
3271
3272 /* Allocate the structure if it has not already been allocated by a
3273 subclass. */
906e58ca 3274 if (ret == NULL)
21d799b5 3275 ret = (struct elf32_arm_link_hash_entry *)
99059e56 3276 bfd_hash_allocate (table, sizeof (struct elf32_arm_link_hash_entry));
57e8b36a 3277 if (ret == NULL)
780a67af
NC		 3278 return (struct bfd_hash_entry *) ret;
3279
3280 /* Call the allocation method of the superclass. */
3281 ret = ((struct elf32_arm_link_hash_entry *)
3282 _bfd_elf_link_hash_newfunc ((struct bfd_hash_entry *) ret,
3283 table, string));
57e8b36a 3284 if (ret != NULL)
b7693d02 3285 {
0bdcacaf 3286 ret->dyn_relocs = NULL;
ba93b8ac 3287 ret->tls_type = GOT_UNKNOWN;
0855e32b 3288 ret->tlsdesc_got = (bfd_vma) -1;
34e77a92
RS		 3289 ret->plt.thumb_refcount = 0;
3290 ret->plt.maybe_thumb_refcount = 0;
3291 ret->plt.noncall_refcount = 0;
3292 ret->plt.got_offset = -1;
3293 ret->is_iplt = FALSE;
a4fd1a8e 3294 ret->export_glue = NULL;
906e58ca
NC		 3295
3296 ret->stub_cache = NULL;
b7693d02 3297 }
780a67af
NC		 3298
3299 return (struct bfd_hash_entry *) ret;
3300}
3301
34e77a92
RS		 3302/* Ensure that we have allocated bookkeeping structures for ABFD's local
3303 symbols. */
3304
3305static bfd_boolean
3306elf32_arm_allocate_local_sym_info (bfd *abfd)
3307{
3308 if (elf_local_got_refcounts (abfd) == NULL)
3309 {
3310 bfd_size_type num_syms;
3311 bfd_size_type size;
3312 char *data;
3313
3314 num_syms = elf_tdata (abfd)->symtab_hdr.sh_info;
3315 size = num_syms * (sizeof (bfd_signed_vma)
3316 + sizeof (struct arm_local_iplt_info *)
3317 + sizeof (bfd_vma)
3318 + sizeof (char));
3319 data = bfd_zalloc (abfd, size);
3320 if (data == NULL)
3321 return FALSE;
3322
3323 elf_local_got_refcounts (abfd) = (bfd_signed_vma *) data;
3324 data += num_syms * sizeof (bfd_signed_vma);
3325
3326 elf32_arm_local_iplt (abfd) = (struct arm_local_iplt_info **) data;
3327 data += num_syms * sizeof (struct arm_local_iplt_info *);
3328
3329 elf32_arm_local_tlsdesc_gotent (abfd) = (bfd_vma *) data;
3330 data += num_syms * sizeof (bfd_vma);
3331
3332 elf32_arm_local_got_tls_type (abfd) = data;
3333 }
3334 return TRUE;
3335}
3336
3337/* Return the .iplt information for local symbol R_SYMNDX, which belongs
3338 to input bfd ABFD. Create the information if it doesn't already exist.
3339 Return null if an allocation fails. */
3340
3341static struct arm_local_iplt_info *
3342elf32_arm_create_local_iplt (bfd *abfd, unsigned long r_symndx)
3343{
3344 struct arm_local_iplt_info **ptr;
3345
3346 if (!elf32_arm_allocate_local_sym_info (abfd))
3347 return NULL;
3348
3349 BFD_ASSERT (r_symndx < elf_tdata (abfd)->symtab_hdr.sh_info);
3350 ptr = &elf32_arm_local_iplt (abfd)[r_symndx];
3351 if (*ptr == NULL)
3352 *ptr = bfd_zalloc (abfd, sizeof (**ptr));
3353 return *ptr;
3354}
3355
3356/* Try to obtain PLT information for the symbol with index R_SYMNDX
3357 in ABFD's symbol table. If the symbol is global, H points to its
3358 hash table entry, otherwise H is null.
3359
3360 Return true if the symbol does have PLT information. When returning
3361 true, point *ROOT_PLT at the target-independent reference count/offset
3362 union and *ARM_PLT at the ARM-specific information. */
3363
3364static bfd_boolean
4ba2ef8f
TP		 3365elf32_arm_get_plt_info (bfd *abfd, struct elf32_arm_link_hash_table *globals,
3366 struct elf32_arm_link_hash_entry *h,
34e77a92
RS		 3367 unsigned long r_symndx, union gotplt_union **root_plt,
3368 struct arm_plt_info **arm_plt)
3369{
3370 struct arm_local_iplt_info *local_iplt;
3371
4ba2ef8f
TP		 3372 if (globals->root.splt == NULL && globals->root.iplt == NULL)
3373 return FALSE;
3374
34e77a92
RS		 3375 if (h != NULL)
3376 {
3377 *root_plt = &h->root.plt;
3378 *arm_plt = &h->plt;
3379 return TRUE;
3380 }
3381
3382 if (elf32_arm_local_iplt (abfd) == NULL)
3383 return FALSE;
3384
3385 local_iplt = elf32_arm_local_iplt (abfd)[r_symndx];
3386 if (local_iplt == NULL)
3387 return FALSE;
3388
3389 *root_plt = &local_iplt->root;
3390 *arm_plt = &local_iplt->arm;
3391 return TRUE;
3392}
3393
3394/* Return true if the PLT described by ARM_PLT requires a Thumb stub
3395 before it. */
3396
3397static bfd_boolean
3398elf32_arm_plt_needs_thumb_stub_p (struct bfd_link_info *info,
3399 struct arm_plt_info *arm_plt)
3400{
3401 struct elf32_arm_link_hash_table *htab;
3402
3403 htab = elf32_arm_hash_table (info);
3404 return (arm_plt->thumb_refcount != 0
3405 || (!htab->use_blx && arm_plt->maybe_thumb_refcount != 0));
3406}
3407
3408/* Return a pointer to the head of the dynamic reloc list that should
3409 be used for local symbol ISYM, which is symbol number R_SYMNDX in
3410 ABFD's symbol table. Return null if an error occurs. */
3411
3412static struct elf_dyn_relocs **
3413elf32_arm_get_local_dynreloc_list (bfd *abfd, unsigned long r_symndx,
3414 Elf_Internal_Sym *isym)
3415{
3416 if (ELF32_ST_TYPE (isym->st_info) == STT_GNU_IFUNC)
3417 {
3418 struct arm_local_iplt_info *local_iplt;
3419
3420 local_iplt = elf32_arm_create_local_iplt (abfd, r_symndx);
3421 if (local_iplt == NULL)
3422 return NULL;
3423 return &local_iplt->dyn_relocs;
3424 }
3425 else
3426 {
3427 /* Track dynamic relocs needed for local syms too.
3428 We really need local syms available to do this
3429 easily. Oh well. */
3430 asection *s;
3431 void *vpp;
3432
3433 s = bfd_section_from_elf_index (abfd, isym->st_shndx);
3434 if (s == NULL)
3435 abort ();
3436
3437 vpp = &elf_section_data (s)->local_dynrel;
3438 return (struct elf_dyn_relocs **) vpp;
3439 }
3440}
3441
906e58ca
NC		 3442/* Initialize an entry in the stub hash table. */
3443
3444static struct bfd_hash_entry *
3445stub_hash_newfunc (struct bfd_hash_entry *entry,
3446 struct bfd_hash_table *table,
3447 const char *string)
3448{
3449 /* Allocate the structure if it has not already been allocated by a
3450 subclass. */
3451 if (entry == NULL)
3452 {
21d799b5 3453 entry = (struct bfd_hash_entry *)
99059e56 3454 bfd_hash_allocate (table, sizeof (struct elf32_arm_stub_hash_entry));
906e58ca
NC		 3455 if (entry == NULL)
3456 return entry;
3457 }
3458
3459 /* Call the allocation method of the superclass. */
3460 entry = bfd_hash_newfunc (entry, table, string);
3461 if (entry != NULL)
3462 {
3463 struct elf32_arm_stub_hash_entry *eh;
3464
3465 /* Initialize the local fields. */
3466 eh = (struct elf32_arm_stub_hash_entry *) entry;
3467 eh->stub_sec = NULL;
0955507f 3468 eh->stub_offset = (bfd_vma) -1;
8d9d9490 3469 eh->source_value = 0;
906e58ca
NC		 3470 eh->target_value = 0;
3471 eh->target_section = NULL;
cedfb179 3472 eh->orig_insn = 0;
906e58ca 3473 eh->stub_type = arm_stub_none;
461a49ca
DJ		 3474 eh->stub_size = 0;
3475 eh->stub_template = NULL;
0955507f 3476 eh->stub_template_size = -1;
906e58ca
NC		 3477 eh->h = NULL;
3478 eh->id_sec = NULL;
d8d2f433 3479 eh->output_name = NULL;
906e58ca
NC		 3480 }
3481
3482 return entry;
3483}
3484
00a97672 3485/* Create .got, .gotplt, and .rel(a).got sections in DYNOBJ, and set up
5e681ec4
PB		 3486 shortcuts to them in our hash table. */
3487
3488static bfd_boolean
57e8b36a 3489create_got_section (bfd *dynobj, struct bfd_link_info *info)
5e681ec4
PB		 3490{
3491 struct elf32_arm_link_hash_table *htab;
3492
e5a52504 3493 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 3494 if (htab == NULL)
3495 return FALSE;
3496
e5a52504
MM		 3497 /* BPABI objects never have a GOT, or associated sections. */
3498 if (htab->symbian_p)
3499 return TRUE;
3500
5e681ec4
PB		 3501 if (! _bfd_elf_create_got_section (dynobj, info))
3502 return FALSE;
3503
5e681ec4
PB		 3504 return TRUE;
3505}
3506
34e77a92
RS		 3507/* Create the .iplt, .rel(a).iplt and .igot.plt sections. */
3508
3509static bfd_boolean
3510create_ifunc_sections (struct bfd_link_info *info)
3511{
3512 struct elf32_arm_link_hash_table *htab;
3513 const struct elf_backend_data *bed;
3514 bfd *dynobj;
3515 asection *s;
3516 flagword flags;
b38cadfb 3517
34e77a92
RS		 3518 htab = elf32_arm_hash_table (info);
3519 dynobj = htab->root.dynobj;
3520 bed = get_elf_backend_data (dynobj);
3521 flags = bed->dynamic_sec_flags;
3522
3523 if (htab->root.iplt == NULL)
3524 {
3d4d4302
AM		 3525 s = bfd_make_section_anyway_with_flags (dynobj, ".iplt",
3526 flags | SEC_READONLY | SEC_CODE);
34e77a92 3527 if (s == NULL
a0f49396 3528 || !bfd_set_section_alignment (dynobj, s, bed->plt_alignment))
34e77a92
RS		 3529 return FALSE;
3530 htab->root.iplt = s;
3531 }
3532
3533 if (htab->root.irelplt == NULL)
3534 {
3d4d4302
AM		 3535 s = bfd_make_section_anyway_with_flags (dynobj,
3536 RELOC_SECTION (htab, ".iplt"),
3537 flags | SEC_READONLY);
34e77a92 3538 if (s == NULL
a0f49396 3539 || !bfd_set_section_alignment (dynobj, s, bed->s->log_file_align))
34e77a92
RS		 3540 return FALSE;
3541 htab->root.irelplt = s;
3542 }
3543
3544 if (htab->root.igotplt == NULL)
3545 {
3d4d4302 3546 s = bfd_make_section_anyway_with_flags (dynobj, ".igot.plt", flags);
34e77a92
RS		 3547 if (s == NULL
3548 || !bfd_set_section_alignment (dynobj, s, bed->s->log_file_align))
3549 return FALSE;
3550 htab->root.igotplt = s;
3551 }
3552 return TRUE;
3553}
3554
eed94f8f
NC		 3555/* Determine if we're dealing with a Thumb only architecture. */
3556
3557static bfd_boolean
3558using_thumb_only (struct elf32_arm_link_hash_table *globals)
3559{
2fd158eb
TP		 3560 int arch;
3561 int profile = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC,
3562 Tag_CPU_arch_profile);
eed94f8f 3563
2fd158eb
TP		 3564 if (profile)
3565 return profile == 'M';
eed94f8f 3566
2fd158eb 3567 arch = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC, Tag_CPU_arch);
eed94f8f 3568
60a019a0 3569 /* Force return logic to be reviewed for each new architecture. */
bff0500d 3570 BFD_ASSERT (arch <= TAG_CPU_ARCH_V8M_MAIN);
60a019a0 3571
2fd158eb
TP		 3572 if (arch == TAG_CPU_ARCH_V6_M
3573 || arch == TAG_CPU_ARCH_V6S_M
3574 || arch == TAG_CPU_ARCH_V7E_M
3575 || arch == TAG_CPU_ARCH_V8M_BASE
3576 || arch == TAG_CPU_ARCH_V8M_MAIN)
3577 return TRUE;
eed94f8f 3578
2fd158eb 3579 return FALSE;
eed94f8f
NC		 3580}
3581
3582/* Determine if we're dealing with a Thumb-2 object. */
3583
3584static bfd_boolean
3585using_thumb2 (struct elf32_arm_link_hash_table *globals)
3586{
60a019a0
TP		 3587 int arch;
3588 int thumb_isa = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC,
3589 Tag_THUMB_ISA_use);
3590
3591 if (thumb_isa)
3592 return thumb_isa == 2;
3593
3594 arch = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC, Tag_CPU_arch);
3595
3596 /* Force return logic to be reviewed for each new architecture. */
bff0500d 3597 BFD_ASSERT (arch <= TAG_CPU_ARCH_V8M_MAIN);
60a019a0
TP		 3598
3599 return (arch == TAG_CPU_ARCH_V6T2
3600 || arch == TAG_CPU_ARCH_V7
3601 || arch == TAG_CPU_ARCH_V7E_M
3602 || arch == TAG_CPU_ARCH_V8
bff0500d 3603 || arch == TAG_CPU_ARCH_V8R
60a019a0 3604 || arch == TAG_CPU_ARCH_V8M_MAIN);
eed94f8f
NC		 3605}
3606
5e866f5a
TP		 3607/* Determine whether Thumb-2 BL instruction is available. */
3608
3609static bfd_boolean
3610using_thumb2_bl (struct elf32_arm_link_hash_table *globals)
3611{
3612 int arch =
3613 bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC, Tag_CPU_arch);
3614
3615 /* Force return logic to be reviewed for each new architecture. */
bff0500d 3616 BFD_ASSERT (arch <= TAG_CPU_ARCH_V8M_MAIN);
5e866f5a
TP		 3617
3618 /* Architecture was introduced after ARMv6T2 (eg. ARMv6-M). */
3619 return (arch == TAG_CPU_ARCH_V6T2
3620 || arch >= TAG_CPU_ARCH_V7);
3621}
3622
00a97672
RS		 3623/* Create .plt, .rel(a).plt, .got, .got.plt, .rel(a).got, .dynbss, and
3624 .rel(a).bss sections in DYNOBJ, and set up shortcuts to them in our
5e681ec4
PB		 3625 hash table. */
3626
3627static bfd_boolean
57e8b36a 3628elf32_arm_create_dynamic_sections (bfd *dynobj, struct bfd_link_info *info)
5e681ec4
PB		 3629{
3630 struct elf32_arm_link_hash_table *htab;
3631
3632 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 3633 if (htab == NULL)
3634 return FALSE;
3635
362d30a1 3636 if (!htab->root.sgot && !create_got_section (dynobj, info))
5e681ec4
PB		 3637 return FALSE;
3638
3639 if (!_bfd_elf_create_dynamic_sections (dynobj, info))
3640 return FALSE;
3641
00a97672
RS		 3642 if (htab->vxworks_p)
3643 {
3644 if (!elf_vxworks_create_dynamic_sections (dynobj, info, &htab->srelplt2))
3645 return FALSE;
3646
0e1862bb 3647 if (bfd_link_pic (info))
00a97672
RS		 3648 {
3649 htab->plt_header_size = 0;
3650 htab->plt_entry_size
3651 = 4 * ARRAY_SIZE (elf32_arm_vxworks_shared_plt_entry);
3652 }
3653 else
3654 {
3655 htab->plt_header_size
3656 = 4 * ARRAY_SIZE (elf32_arm_vxworks_exec_plt0_entry);
3657 htab->plt_entry_size
3658 = 4 * ARRAY_SIZE (elf32_arm_vxworks_exec_plt_entry);
3659 }
aebf9be7
NC		 3660
3661 if (elf_elfheader (dynobj))
3662 elf_elfheader (dynobj)->e_ident[EI_CLASS] = ELFCLASS32;
00a97672 3663 }
eed94f8f
NC		 3664 else
3665 {
3666 /* PR ld/16017
3667 Test for thumb only architectures. Note - we cannot just call
3668 using_thumb_only() as the attributes in the output bfd have not been
3669 initialised at this point, so instead we use the input bfd. */
3670 bfd * saved_obfd = htab->obfd;
3671
3672 htab->obfd = dynobj;
3673 if (using_thumb_only (htab))
3674 {
3675 htab->plt_header_size = 4 * ARRAY_SIZE (elf32_thumb2_plt0_entry);
3676 htab->plt_entry_size = 4 * ARRAY_SIZE (elf32_thumb2_plt_entry);
3677 }
3678 htab->obfd = saved_obfd;
3679 }
5e681ec4 3680
362d30a1
RS		 3681 if (!htab->root.splt
3682 || !htab->root.srelplt
9d19e4fd
AM		 3683 || !htab->root.sdynbss
3684 || (!bfd_link_pic (info) && !htab->root.srelbss))
5e681ec4
PB		 3685 abort ();
3686
3687 return TRUE;
3688}
3689
906e58ca
NC		 3690/* Copy the extra info we tack onto an elf_link_hash_entry. */
3691
3692static void
3693elf32_arm_copy_indirect_symbol (struct bfd_link_info *info,
3694 struct elf_link_hash_entry *dir,
3695 struct elf_link_hash_entry *ind)
3696{
3697 struct elf32_arm_link_hash_entry *edir, *eind;
3698
3699 edir = (struct elf32_arm_link_hash_entry *) dir;
3700 eind = (struct elf32_arm_link_hash_entry *) ind;
3701
0bdcacaf 3702 if (eind->dyn_relocs != NULL)
906e58ca 3703 {
0bdcacaf 3704 if (edir->dyn_relocs != NULL)
906e58ca 3705 {
0bdcacaf
RS		 3706 struct elf_dyn_relocs **pp;
3707 struct elf_dyn_relocs *p;
906e58ca
NC		 3708
3709 /* Add reloc counts against the indirect sym to the direct sym
3710 list. Merge any entries against the same section. */
0bdcacaf 3711 for (pp = &eind->dyn_relocs; (p = *pp) != NULL; )
906e58ca 3712 {
0bdcacaf 3713 struct elf_dyn_relocs *q;
906e58ca 3714
0bdcacaf
RS		 3715 for (q = edir->dyn_relocs; q != NULL; q = q->next)
3716 if (q->sec == p->sec)
906e58ca
NC		 3717 {
3718 q->pc_count += p->pc_count;
3719 q->count += p->count;
3720 *pp = p->next;
3721 break;
3722 }
3723 if (q == NULL)
3724 pp = &p->next;
3725 }
0bdcacaf 3726 *pp = edir->dyn_relocs;
906e58ca
NC		 3727 }
3728
0bdcacaf
RS		 3729 edir->dyn_relocs = eind->dyn_relocs;
3730 eind->dyn_relocs = NULL;
906e58ca
NC		 3731 }
3732
3733 if (ind->root.type == bfd_link_hash_indirect)
3734 {
3735 /* Copy over PLT info. */
34e77a92
RS		 3736 edir->plt.thumb_refcount += eind->plt.thumb_refcount;
3737 eind->plt.thumb_refcount = 0;
3738 edir->plt.maybe_thumb_refcount += eind->plt.maybe_thumb_refcount;
3739 eind->plt.maybe_thumb_refcount = 0;
3740 edir->plt.noncall_refcount += eind->plt.noncall_refcount;
3741 eind->plt.noncall_refcount = 0;
3742
3743 /* We should only allocate a function to .iplt once the final
3744 symbol information is known. */
3745 BFD_ASSERT (!eind->is_iplt);
906e58ca
NC		 3746
3747 if (dir->got.refcount <= 0)
3748 {
3749 edir->tls_type = eind->tls_type;
3750 eind->tls_type = GOT_UNKNOWN;
3751 }
3752 }
3753
3754 _bfd_elf_link_hash_copy_indirect (info, dir, ind);
3755}
3756
68faa637
AM		 3757/* Destroy an ARM elf linker hash table. */
3758
3759static void
d495ab0d 3760elf32_arm_link_hash_table_free (bfd *obfd)
68faa637
AM		 3761{
3762 struct elf32_arm_link_hash_table *ret
d495ab0d 3763 = (struct elf32_arm_link_hash_table *) obfd->link.hash;
68faa637
AM		 3764
3765 bfd_hash_table_free (&ret->stub_hash_table);
d495ab0d 3766 _bfd_elf_link_hash_table_free (obfd);
68faa637
AM		 3767}
3768
906e58ca
NC		 3769/* Create an ARM elf linker hash table. */
3770
3771static struct bfd_link_hash_table *
3772elf32_arm_link_hash_table_create (bfd *abfd)
3773{
3774 struct elf32_arm_link_hash_table *ret;
3775 bfd_size_type amt = sizeof (struct elf32_arm_link_hash_table);
3776
7bf52ea2 3777 ret = (struct elf32_arm_link_hash_table *) bfd_zmalloc (amt);
906e58ca
NC		 3778 if (ret == NULL)
3779 return NULL;
3780
3781 if (!_bfd_elf_link_hash_table_init (& ret->root, abfd,
3782 elf32_arm_link_hash_newfunc,
4dfe6ac6
NC		 3783 sizeof (struct elf32_arm_link_hash_entry),
3784 ARM_ELF_DATA))
906e58ca
NC		 3785 {
3786 free (ret);
3787 return NULL;
3788 }
3789
906e58ca 3790 ret->vfp11_fix = BFD_ARM_VFP11_FIX_NONE;
a504d23a 3791 ret->stm32l4xx_fix = BFD_ARM_STM32L4XX_FIX_NONE;
906e58ca
NC		 3792#ifdef FOUR_WORD_PLT
3793 ret->plt_header_size = 16;
3794 ret->plt_entry_size = 16;
3795#else
3796 ret->plt_header_size = 20;
1db37fe6 3797 ret->plt_entry_size = elf32_arm_use_long_plt_entry ? 16 : 12;
906e58ca 3798#endif
906e58ca 3799 ret->use_rel = 1;
906e58ca 3800 ret->obfd = abfd;
906e58ca
NC		 3801
3802 if (!bfd_hash_table_init (&ret->stub_hash_table, stub_hash_newfunc,
3803 sizeof (struct elf32_arm_stub_hash_entry)))
3804 {
d495ab0d 3805 _bfd_elf_link_hash_table_free (abfd);
906e58ca
NC		 3806 return NULL;
3807 }
d495ab0d 3808 ret->root.root.hash_table_free = elf32_arm_link_hash_table_free;
906e58ca
NC		 3809
3810 return &ret->root.root;
3811}
3812
cd1dac3d
DG		 3813/* Determine what kind of NOPs are available. */
3814
3815static bfd_boolean
3816arch_has_arm_nop (struct elf32_arm_link_hash_table *globals)
3817{
3818 const int arch = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC,
3819 Tag_CPU_arch);
cd1dac3d 3820
60a019a0 3821 /* Force return logic to be reviewed for each new architecture. */
bff0500d 3822 BFD_ASSERT (arch <= TAG_CPU_ARCH_V8M_MAIN);
60a019a0
TP		 3823
3824 return (arch == TAG_CPU_ARCH_V6T2
3825 || arch == TAG_CPU_ARCH_V6K
3826 || arch == TAG_CPU_ARCH_V7
bff0500d
TP		 3827 || arch == TAG_CPU_ARCH_V8
3828 || arch == TAG_CPU_ARCH_V8R);
cd1dac3d
DG		 3829}
3830
f4ac8484
DJ		 3831static bfd_boolean
3832arm_stub_is_thumb (enum elf32_arm_stub_type stub_type)
3833{
3834 switch (stub_type)
3835 {
fea2b4d6 3836 case arm_stub_long_branch_thumb_only:
80c135e5 3837 case arm_stub_long_branch_thumb2_only:
d5a67c02 3838 case arm_stub_long_branch_thumb2_only_pure:
fea2b4d6
CL		 3839 case arm_stub_long_branch_v4t_thumb_arm:
3840 case arm_stub_short_branch_v4t_thumb_arm:
ebe24dd4 3841 case arm_stub_long_branch_v4t_thumb_arm_pic:
12352d3f 3842 case arm_stub_long_branch_v4t_thumb_tls_pic:
ebe24dd4 3843 case arm_stub_long_branch_thumb_only_pic:
4ba2ef8f 3844 case arm_stub_cmse_branch_thumb_only:
f4ac8484
DJ		 3845 return TRUE;
3846 case arm_stub_none:
3847 BFD_FAIL ();
3848 return FALSE;
3849 break;
3850 default:
3851 return FALSE;
3852 }
3853}
3854
906e58ca
NC		 3855/* Determine the type of stub needed, if any, for a call. */
3856
3857static enum elf32_arm_stub_type
3858arm_type_of_stub (struct bfd_link_info *info,
3859 asection *input_sec,
3860 const Elf_Internal_Rela *rel,
34e77a92 3861 unsigned char st_type,
35fc36a8 3862 enum arm_st_branch_type *actual_branch_type,
906e58ca 3863 struct elf32_arm_link_hash_entry *hash,
c820be07
NC		 3864 bfd_vma destination,
3865 asection *sym_sec,
3866 bfd *input_bfd,
3867 const char *name)
906e58ca
NC		 3868{
3869 bfd_vma location;
3870 bfd_signed_vma branch_offset;
3871 unsigned int r_type;
3872 struct elf32_arm_link_hash_table * globals;
5e866f5a 3873 bfd_boolean thumb2, thumb2_bl, thumb_only;
906e58ca 3874 enum elf32_arm_stub_type stub_type = arm_stub_none;
5fa9e92f 3875 int use_plt = 0;
35fc36a8 3876 enum arm_st_branch_type branch_type = *actual_branch_type;
34e77a92
RS		 3877 union gotplt_union *root_plt;
3878 struct arm_plt_info *arm_plt;
d5a67c02
AV		 3879 int arch;
3880 int thumb2_movw;
906e58ca 3881
35fc36a8 3882 if (branch_type == ST_BRANCH_LONG)
da5938a2
NC		 3883 return stub_type;
3884
906e58ca 3885 globals = elf32_arm_hash_table (info);
4dfe6ac6
NC		 3886 if (globals == NULL)
3887 return stub_type;
906e58ca
NC		 3888
3889 thumb_only = using_thumb_only (globals);
906e58ca 3890 thumb2 = using_thumb2 (globals);
5e866f5a 3891 thumb2_bl = using_thumb2_bl (globals);
906e58ca 3892
d5a67c02
AV		 3893 arch = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC, Tag_CPU_arch);
3894
3895 /* True for architectures that implement the thumb2 movw instruction. */
3896 thumb2_movw = thumb2 || (arch == TAG_CPU_ARCH_V8M_BASE);
3897
906e58ca
NC		 3898 /* Determine where the call point is. */
3899 location = (input_sec->output_offset
3900 + input_sec->output_section->vma
3901 + rel->r_offset);
3902
906e58ca
NC		 3903 r_type = ELF32_R_TYPE (rel->r_info);
3904
39f21624
NC		 3905 /* ST_BRANCH_TO_ARM is nonsense to thumb-only targets when we
3906 are considering a function call relocation. */
c5423981
TG		 3907 if (thumb_only && (r_type == R_ARM_THM_CALL || r_type == R_ARM_THM_JUMP24
3908 || r_type == R_ARM_THM_JUMP19)
39f21624
NC		 3909 && branch_type == ST_BRANCH_TO_ARM)
3910 branch_type = ST_BRANCH_TO_THUMB;
3911
34e77a92
RS		 3912 /* For TLS call relocs, it is the caller's responsibility to provide
3913 the address of the appropriate trampoline. */
3914 if (r_type != R_ARM_TLS_CALL
3915 && r_type != R_ARM_THM_TLS_CALL
4ba2ef8f
TP		 3916 && elf32_arm_get_plt_info (input_bfd, globals, hash,
3917 ELF32_R_SYM (rel->r_info), &root_plt,
3918 &arm_plt)
34e77a92 3919 && root_plt->offset != (bfd_vma) -1)
5fa9e92f 3920 {
34e77a92 3921 asection *splt;
fe33d2fa 3922
34e77a92
RS		 3923 if (hash == NULL || hash->is_iplt)
3924 splt = globals->root.iplt;
3925 else
3926 splt = globals->root.splt;
3927 if (splt != NULL)
b38cadfb 3928 {
34e77a92
RS		 3929 use_plt = 1;
3930
3931 /* Note when dealing with PLT entries: the main PLT stub is in
3932 ARM mode, so if the branch is in Thumb mode, another
3933 Thumb->ARM stub will be inserted later just before the ARM
2df2751d
CL		 3934 PLT stub. If a long branch stub is needed, we'll add a
3935 Thumb->Arm one and branch directly to the ARM PLT entry.
3936 Here, we have to check if a pre-PLT Thumb->ARM stub
3937 is needed and if it will be close enough. */
34e77a92
RS		 3938
3939 destination = (splt->output_section->vma
3940 + splt->output_offset
3941 + root_plt->offset);
3942 st_type = STT_FUNC;
2df2751d
CL		 3943
3944 /* Thumb branch/call to PLT: it can become a branch to ARM
3945 or to Thumb. We must perform the same checks and
3946 corrections as in elf32_arm_final_link_relocate. */
3947 if ((r_type == R_ARM_THM_CALL)
3948 || (r_type == R_ARM_THM_JUMP24))
3949 {
3950 if (globals->use_blx
3951 && r_type == R_ARM_THM_CALL
3952 && !thumb_only)
3953 {
3954 /* If the Thumb BLX instruction is available, convert
3955 the BL to a BLX instruction to call the ARM-mode
3956 PLT entry. */
3957 branch_type = ST_BRANCH_TO_ARM;
3958 }
3959 else
3960 {
3961 if (!thumb_only)
3962 /* Target the Thumb stub before the ARM PLT entry. */
3963 destination -= PLT_THUMB_STUB_SIZE;
3964 branch_type = ST_BRANCH_TO_THUMB;
3965 }
3966 }
3967 else
3968 {
3969 branch_type = ST_BRANCH_TO_ARM;
3970 }
34e77a92 3971 }
5fa9e92f 3972 }
34e77a92
RS		 3973 /* Calls to STT_GNU_IFUNC symbols should go through a PLT. */
3974 BFD_ASSERT (st_type != STT_GNU_IFUNC);
906e58ca 3975
fe33d2fa
CL		 3976 branch_offset = (bfd_signed_vma)(destination - location);
3977
0855e32b 3978 if (r_type == R_ARM_THM_CALL || r_type == R_ARM_THM_JUMP24
c5423981 3979 || r_type == R_ARM_THM_TLS_CALL || r_type == R_ARM_THM_JUMP19)
906e58ca 3980 {
5fa9e92f
CL		 3981 /* Handle cases where:
3982 - this call goes too far (different Thumb/Thumb2 max
99059e56 3983 distance)
155d87d7 3984 - it's a Thumb->Arm call and blx is not available, or it's a
99059e56
RM		 3985 Thumb->Arm branch (not bl). A stub is needed in this case,
3986 but only if this call is not through a PLT entry. Indeed,
695344c0 3987 PLT stubs handle mode switching already. */
5e866f5a 3988 if ((!thumb2_bl
906e58ca
NC		 3989 && (branch_offset > THM_MAX_FWD_BRANCH_OFFSET
3990 || (branch_offset < THM_MAX_BWD_BRANCH_OFFSET)))
5e866f5a 3991 || (thumb2_bl
906e58ca
NC		 3992 && (branch_offset > THM2_MAX_FWD_BRANCH_OFFSET
3993 || (branch_offset < THM2_MAX_BWD_BRANCH_OFFSET)))
c5423981
TG		 3994 || (thumb2
3995 && (branch_offset > THM2_MAX_FWD_COND_BRANCH_OFFSET
3996 || (branch_offset < THM2_MAX_BWD_COND_BRANCH_OFFSET))
3997 && (r_type == R_ARM_THM_JUMP19))
35fc36a8 3998 || (branch_type == ST_BRANCH_TO_ARM
0855e32b
NS		 3999 && (((r_type == R_ARM_THM_CALL
4000 || r_type == R_ARM_THM_TLS_CALL) && !globals->use_blx)
c5423981
TG		 4001 || (r_type == R_ARM_THM_JUMP24)
4002 || (r_type == R_ARM_THM_JUMP19))
5fa9e92f 4003 && !use_plt))
906e58ca 4004 {
2df2751d
CL		 4005 /* If we need to insert a Thumb-Thumb long branch stub to a
4006 PLT, use one that branches directly to the ARM PLT
4007 stub. If we pretended we'd use the pre-PLT Thumb->ARM
4008 stub, undo this now. */
695344c0
NC		 4009 if ((branch_type == ST_BRANCH_TO_THUMB) && use_plt && !thumb_only)
4010 {
4011 branch_type = ST_BRANCH_TO_ARM;
4012 branch_offset += PLT_THUMB_STUB_SIZE;
4013 }
2df2751d 4014
35fc36a8 4015 if (branch_type == ST_BRANCH_TO_THUMB)
906e58ca
NC		 4016 {
4017 /* Thumb to thumb. */
4018 if (!thumb_only)
4019 {
d5a67c02 4020 if (input_sec->flags & SEC_ELF_PURECODE)
10463f39
AM		 4021 _bfd_error_handler
4022 (_("%B(%A): warning: long branch veneers used in"
4023 " section with SHF_ARM_PURECODE section"
4024 " attribute is only supported for M-profile"
4025 " targets that implement the movw instruction."),
4026 input_bfd, input_sec);
d5a67c02 4027
0e1862bb 4028 stub_type = (bfd_link_pic (info) | globals->pic_veneer)
c2b4a39d 4029 /* PIC stubs. */
155d87d7 4030 ? ((globals->use_blx
9553db3c 4031 && (r_type == R_ARM_THM_CALL))
155d87d7
CL		 4032 /* V5T and above. Stub starts with ARM code, so
4033 we must be able to switch mode before
4034 reaching it, which is only possible for 'bl'
4035 (ie R_ARM_THM_CALL relocation). */
cf3eccff 4036 ? arm_stub_long_branch_any_thumb_pic
ebe24dd4 4037 /* On V4T, use Thumb code only. */
d3626fb0 4038 : arm_stub_long_branch_v4t_thumb_thumb_pic)
c2b4a39d
CL		 4039
4040 /* non-PIC stubs. */
155d87d7 4041 : ((globals->use_blx
9553db3c 4042 && (r_type == R_ARM_THM_CALL))
c2b4a39d
CL		 4043 /* V5T and above. */
4044 ? arm_stub_long_branch_any_any
4045 /* V4T. */
d3626fb0 4046 : arm_stub_long_branch_v4t_thumb_thumb);
906e58ca
NC		 4047 }
4048 else
4049 {
d5a67c02
AV		 4050 if (thumb2_movw && (input_sec->flags & SEC_ELF_PURECODE))
4051 stub_type = arm_stub_long_branch_thumb2_only_pure;
4052 else
4053 {
4054 if (input_sec->flags & SEC_ELF_PURECODE)
10463f39
AM		 4055 _bfd_error_handler
4056 (_("%B(%A): warning: long branch veneers used in"
4057 " section with SHF_ARM_PURECODE section"
4058 " attribute is only supported for M-profile"
4059 " targets that implement the movw instruction."),
4060 input_bfd, input_sec);
d5a67c02
AV		 4061
4062 stub_type = (bfd_link_pic (info) | globals->pic_veneer)
4063 /* PIC stub. */
4064 ? arm_stub_long_branch_thumb_only_pic
4065 /* non-PIC stub. */
4066 : (thumb2 ? arm_stub_long_branch_thumb2_only
4067 : arm_stub_long_branch_thumb_only);
4068 }
906e58ca
NC		 4069 }
4070 }
4071 else
4072 {
d5a67c02 4073 if (input_sec->flags & SEC_ELF_PURECODE)
10463f39
AM		 4074 _bfd_error_handler
4075 (_("%B(%A): warning: long branch veneers used in"
4076 " section with SHF_ARM_PURECODE section"
4077 " attribute is only supported" " for M-profile"
4078 " targets that implement the movw instruction."),
4079 input_bfd, input_sec);
d5a67c02 4080
906e58ca 4081 /* Thumb to arm. */
c820be07
NC		 4082 if (sym_sec != NULL
4083 && sym_sec->owner != NULL
4084 && !INTERWORK_FLAG (sym_sec->owner))
4085 {
4eca0228 4086 _bfd_error_handler
c820be07
NC		 4087 (_("%B(%s): warning: interworking not enabled.\n"
4088 " first occurrence: %B: Thumb call to ARM"),
c08bb8dd 4089 sym_sec->owner, name, input_bfd);
c820be07
NC		 4090 }
4091
0855e32b 4092 stub_type =
0e1862bb 4093 (bfd_link_pic (info) | globals->pic_veneer)
c2b4a39d 4094 /* PIC stubs. */
0855e32b 4095 ? (r_type == R_ARM_THM_TLS_CALL
6a631e86 4096 /* TLS PIC stubs. */
0855e32b
NS		 4097 ? (globals->use_blx ? arm_stub_long_branch_any_tls_pic
4098 : arm_stub_long_branch_v4t_thumb_tls_pic)
4099 : ((globals->use_blx && r_type == R_ARM_THM_CALL)
4100 /* V5T PIC and above. */
4101 ? arm_stub_long_branch_any_arm_pic
4102 /* V4T PIC stub. */
4103 : arm_stub_long_branch_v4t_thumb_arm_pic))
c2b4a39d
CL		 4104
4105 /* non-PIC stubs. */
0855e32b 4106 : ((globals->use_blx && r_type == R_ARM_THM_CALL)
c2b4a39d
CL		 4107 /* V5T and above. */
4108 ? arm_stub_long_branch_any_any
4109 /* V4T. */
4110 : arm_stub_long_branch_v4t_thumb_arm);
c820be07
NC		 4111
4112 /* Handle v4t short branches. */
fea2b4d6 4113 if ((stub_type == arm_stub_long_branch_v4t_thumb_arm)
c820be07
NC		 4114 && (branch_offset <= THM_MAX_FWD_BRANCH_OFFSET)
4115 && (branch_offset >= THM_MAX_BWD_BRANCH_OFFSET))
fea2b4d6 4116 stub_type = arm_stub_short_branch_v4t_thumb_arm;
906e58ca
NC		 4117 }
4118 }
4119 }
fe33d2fa
CL		 4120 else if (r_type == R_ARM_CALL
4121 || r_type == R_ARM_JUMP24
0855e32b
NS		 4122 || r_type == R_ARM_PLT32
4123 || r_type == R_ARM_TLS_CALL)
906e58ca 4124 {
d5a67c02 4125 if (input_sec->flags & SEC_ELF_PURECODE)
10463f39
AM		 4126 _bfd_error_handler
4127 (_("%B(%A): warning: long branch veneers used in"
4128 " section with SHF_ARM_PURECODE section"
4129 " attribute is only supported for M-profile"
4130 " targets that implement the movw instruction."),
4131 input_bfd, input_sec);
35fc36a8 4132 if (branch_type == ST_BRANCH_TO_THUMB)
906e58ca
NC		 4133 {
4134 /* Arm to thumb. */
c820be07
NC		 4135
4136 if (sym_sec != NULL
4137 && sym_sec->owner != NULL
4138 && !INTERWORK_FLAG (sym_sec->owner))
4139 {
4eca0228 4140 _bfd_error_handler
c820be07 4141 (_("%B(%s): warning: interworking not enabled.\n"
c2b4a39d 4142 " first occurrence: %B: ARM call to Thumb"),
c820be07
NC		 4143 sym_sec->owner, input_bfd, name);
4144 }
4145
4146 /* We have an extra 2-bytes reach because of
4147 the mode change (bit 24 (H) of BLX encoding). */
4116d8d7
PB		 4148 if (branch_offset > (ARM_MAX_FWD_BRANCH_OFFSET + 2)
4149 || (branch_offset < ARM_MAX_BWD_BRANCH_OFFSET)
0855e32b 4150 || (r_type == R_ARM_CALL && !globals->use_blx)
4116d8d7
PB		 4151 || (r_type == R_ARM_JUMP24)
4152 || (r_type == R_ARM_PLT32))
906e58ca 4153 {
0e1862bb 4154 stub_type = (bfd_link_pic (info) | globals->pic_veneer)
c2b4a39d 4155 /* PIC stubs. */
ebe24dd4
CL		 4156 ? ((globals->use_blx)
4157 /* V5T and above. */
4158 ? arm_stub_long_branch_any_thumb_pic
4159 /* V4T stub. */
4160 : arm_stub_long_branch_v4t_arm_thumb_pic)
4161
c2b4a39d
CL		 4162 /* non-PIC stubs. */
4163 : ((globals->use_blx)
4164 /* V5T and above. */
4165 ? arm_stub_long_branch_any_any
4166 /* V4T. */
4167 : arm_stub_long_branch_v4t_arm_thumb);
906e58ca
NC		 4168 }
4169 }
4170 else
4171 {
4172 /* Arm to arm. */
4173 if (branch_offset > ARM_MAX_FWD_BRANCH_OFFSET
4174 || (branch_offset < ARM_MAX_BWD_BRANCH_OFFSET))
4175 {
0855e32b 4176 stub_type =
0e1862bb 4177 (bfd_link_pic (info) | globals->pic_veneer)
c2b4a39d 4178 /* PIC stubs. */
0855e32b 4179 ? (r_type == R_ARM_TLS_CALL
6a631e86 4180 /* TLS PIC Stub. */
0855e32b 4181 ? arm_stub_long_branch_any_tls_pic
7a89b94e
NC		 4182 : (globals->nacl_p
4183 ? arm_stub_long_branch_arm_nacl_pic
4184 : arm_stub_long_branch_any_arm_pic))
c2b4a39d 4185 /* non-PIC stubs. */
7a89b94e
NC		 4186 : (globals->nacl_p
4187 ? arm_stub_long_branch_arm_nacl
4188 : arm_stub_long_branch_any_any);
906e58ca
NC		 4189 }
4190 }
4191 }
4192
fe33d2fa
CL		 4193 /* If a stub is needed, record the actual destination type. */
4194 if (stub_type != arm_stub_none)
35fc36a8 4195 *actual_branch_type = branch_type;
fe33d2fa 4196
906e58ca
NC		 4197 return stub_type;
4198}
4199
4200/* Build a name for an entry in the stub hash table. */
4201
4202static char *
4203elf32_arm_stub_name (const asection *input_section,
4204 const asection *sym_sec,
4205 const struct elf32_arm_link_hash_entry *hash,
fe33d2fa
CL		 4206 const Elf_Internal_Rela *rel,
4207 enum elf32_arm_stub_type stub_type)
906e58ca
NC		 4208{
4209 char *stub_name;
4210 bfd_size_type len;
4211
4212 if (hash)
4213 {
fe33d2fa 4214 len = 8 + 1 + strlen (hash->root.root.root.string) + 1 + 8 + 1 + 2 + 1;
21d799b5 4215 stub_name = (char *) bfd_malloc (len);
906e58ca 4216 if (stub_name != NULL)
fe33d2fa 4217 sprintf (stub_name, "%08x_%s+%x_%d",
906e58ca
NC		 4218 input_section->id & 0xffffffff,
4219 hash->root.root.root.string,
fe33d2fa
CL		 4220 (int) rel->r_addend & 0xffffffff,
4221 (int) stub_type);
906e58ca
NC		 4222 }
4223 else
4224 {
fe33d2fa 4225 len = 8 + 1 + 8 + 1 + 8 + 1 + 8 + 1 + 2 + 1;
21d799b5 4226 stub_name = (char *) bfd_malloc (len);
906e58ca 4227 if (stub_name != NULL)
fe33d2fa 4228 sprintf (stub_name, "%08x_%x:%x+%x_%d",
906e58ca
NC		 4229 input_section->id & 0xffffffff,
4230 sym_sec->id & 0xffffffff,
0855e32b
NS		 4231 ELF32_R_TYPE (rel->r_info) == R_ARM_TLS_CALL
4232 || ELF32_R_TYPE (rel->r_info) == R_ARM_THM_TLS_CALL
4233 ? 0 : (int) ELF32_R_SYM (rel->r_info) & 0xffffffff,
fe33d2fa
CL		 4234 (int) rel->r_addend & 0xffffffff,
4235 (int) stub_type);
906e58ca
NC		 4236 }
4237
4238 return stub_name;
4239}
4240
4241/* Look up an entry in the stub hash. Stub entries are cached because
4242 creating the stub name takes a bit of time. */
4243
4244static struct elf32_arm_stub_hash_entry *
4245elf32_arm_get_stub_entry (const asection *input_section,
4246 const asection *sym_sec,
4247 struct elf_link_hash_entry *hash,
4248 const Elf_Internal_Rela *rel,
fe33d2fa
CL		 4249 struct elf32_arm_link_hash_table *htab,
4250 enum elf32_arm_stub_type stub_type)
906e58ca
NC		 4251{
4252 struct elf32_arm_stub_hash_entry *stub_entry;
4253 struct elf32_arm_link_hash_entry *h = (struct elf32_arm_link_hash_entry *) hash;
4254 const asection *id_sec;
4255
4256 if ((input_section->flags & SEC_CODE) == 0)
4257 return NULL;
4258
4259 /* If this input section is part of a group of sections sharing one
4260 stub section, then use the id of the first section in the group.
4261 Stub names need to include a section id, as there may well be
4262 more than one stub used to reach say, printf, and we need to
4263 distinguish between them. */
c2abbbeb 4264 BFD_ASSERT (input_section->id <= htab->top_id);
906e58ca
NC		 4265 id_sec = htab->stub_group[input_section->id].link_sec;
4266
4267 if (h != NULL && h->stub_cache != NULL
4268 && h->stub_cache->h == h
fe33d2fa
CL		 4269 && h->stub_cache->id_sec == id_sec
4270 && h->stub_cache->stub_type == stub_type)
906e58ca
NC		 4271 {
4272 stub_entry = h->stub_cache;
4273 }
4274 else
4275 {
4276 char *stub_name;
4277
fe33d2fa 4278 stub_name = elf32_arm_stub_name (id_sec, sym_sec, h, rel, stub_type);
906e58ca
NC		 4279 if (stub_name == NULL)
4280 return NULL;
4281
4282 stub_entry = arm_stub_hash_lookup (&htab->stub_hash_table,
4283 stub_name, FALSE, FALSE);
4284 if (h != NULL)
4285 h->stub_cache = stub_entry;
4286
4287 free (stub_name);
4288 }
4289
4290 return stub_entry;
4291}
4292
daa4adae
TP		 4293/* Whether veneers of type STUB_TYPE require to be in a dedicated output
4294 section. */
4295
4296static bfd_boolean
4297arm_dedicated_stub_output_section_required (enum elf32_arm_stub_type stub_type)
4298{
4299 if (stub_type >= max_stub_type)
4300 abort (); /* Should be unreachable. */
4301
4ba2ef8f
TP		 4302 switch (stub_type)
4303 {
4304 case arm_stub_cmse_branch_thumb_only:
4305 return TRUE;
4306
4307 default:
4308 return FALSE;
4309 }
4310
4311 abort (); /* Should be unreachable. */
daa4adae
TP		 4312}
4313
4314/* Required alignment (as a power of 2) for the dedicated section holding
4315 veneers of type STUB_TYPE, or 0 if veneers of this type are interspersed
4316 with input sections. */
4317
4318static int
4319arm_dedicated_stub_output_section_required_alignment
4320 (enum elf32_arm_stub_type stub_type)
4321{
4322 if (stub_type >= max_stub_type)
4323 abort (); /* Should be unreachable. */
4324
4ba2ef8f
TP		 4325 switch (stub_type)
4326 {
4327 /* Vectors of Secure Gateway veneers must be aligned on 32byte
4328 boundary. */
4329 case arm_stub_cmse_branch_thumb_only:
4330 return 5;
4331
4332 default:
4333 BFD_ASSERT (!arm_dedicated_stub_output_section_required (stub_type));
4334 return 0;
4335 }
4336
4337 abort (); /* Should be unreachable. */
daa4adae
TP		 4338}
4339
4340/* Name of the dedicated output section to put veneers of type STUB_TYPE, or
4341 NULL if veneers of this type are interspersed with input sections. */
4342
4343static const char *
4344arm_dedicated_stub_output_section_name (enum elf32_arm_stub_type stub_type)
4345{
4346 if (stub_type >= max_stub_type)
4347 abort (); /* Should be unreachable. */
4348
4ba2ef8f
TP		 4349 switch (stub_type)
4350 {
4351 case arm_stub_cmse_branch_thumb_only:
4352 return ".gnu.sgstubs";
4353
4354 default:
4355 BFD_ASSERT (!arm_dedicated_stub_output_section_required (stub_type));
4356 return NULL;
4357 }
4358
4359 abort (); /* Should be unreachable. */
daa4adae
TP		 4360}
4361
4362/* If veneers of type STUB_TYPE should go in a dedicated output section,
4363 returns the address of the hash table field in HTAB holding a pointer to the
4364 corresponding input section. Otherwise, returns NULL. */
4365
4366static asection **
4ba2ef8f
TP		 4367arm_dedicated_stub_input_section_ptr (struct elf32_arm_link_hash_table *htab,
4368 enum elf32_arm_stub_type stub_type)
daa4adae
TP		 4369{
4370 if (stub_type >= max_stub_type)
4371 abort (); /* Should be unreachable. */
4372
4ba2ef8f
TP		 4373 switch (stub_type)
4374 {
4375 case arm_stub_cmse_branch_thumb_only:
4376 return &htab->cmse_stub_sec;
4377
4378 default:
4379 BFD_ASSERT (!arm_dedicated_stub_output_section_required (stub_type));
4380 return NULL;
4381 }
4382
4383 abort (); /* Should be unreachable. */
daa4adae
TP		 4384}
4385
4386/* Find or create a stub section to contain a stub of type STUB_TYPE. SECTION
4387 is the section that branch into veneer and can be NULL if stub should go in
4388 a dedicated output section. Returns a pointer to the stub section, and the
4389 section to which the stub section will be attached (in *LINK_SEC_P).
48229727 4390 LINK_SEC_P may be NULL. */
906e58ca 4391
48229727
JB		 4392static asection *
4393elf32_arm_create_or_find_stub_sec (asection **link_sec_p, asection *section,
daa4adae
TP		 4394 struct elf32_arm_link_hash_table *htab,
4395 enum elf32_arm_stub_type stub_type)
906e58ca 4396{
daa4adae
TP		 4397 asection *link_sec, *out_sec, **stub_sec_p;
4398 const char *stub_sec_prefix;
4399 bfd_boolean dedicated_output_section =
4400 arm_dedicated_stub_output_section_required (stub_type);
4401 int align;
906e58ca 4402
daa4adae 4403 if (dedicated_output_section)
906e58ca 4404 {
daa4adae
TP		 4405 bfd *output_bfd = htab->obfd;
4406 const char *out_sec_name =
4407 arm_dedicated_stub_output_section_name (stub_type);
4408 link_sec = NULL;
4409 stub_sec_p = arm_dedicated_stub_input_section_ptr (htab, stub_type);
4410 stub_sec_prefix = out_sec_name;
4411 align = arm_dedicated_stub_output_section_required_alignment (stub_type);
4412 out_sec = bfd_get_section_by_name (output_bfd, out_sec_name);
4413 if (out_sec == NULL)
906e58ca 4414 {
4eca0228
AM		 4415 _bfd_error_handler (_("No address assigned to the veneers output "
4416 "section %s"), out_sec_name);
daa4adae 4417 return NULL;
906e58ca 4418 }
daa4adae
TP		 4419 }
4420 else
4421 {
c2abbbeb 4422 BFD_ASSERT (section->id <= htab->top_id);
daa4adae
TP		 4423 link_sec = htab->stub_group[section->id].link_sec;
4424 BFD_ASSERT (link_sec != NULL);
4425 stub_sec_p = &htab->stub_group[section->id].stub_sec;
4426 if (*stub_sec_p == NULL)
4427 stub_sec_p = &htab->stub_group[link_sec->id].stub_sec;
4428 stub_sec_prefix = link_sec->name;
4429 out_sec = link_sec->output_section;
4430 align = htab->nacl_p ? 4 : 3;
906e58ca 4431 }
b38cadfb 4432
daa4adae
TP		 4433 if (*stub_sec_p == NULL)
4434 {
4435 size_t namelen;
4436 bfd_size_type len;
4437 char *s_name;
4438
4439 namelen = strlen (stub_sec_prefix);
4440 len = namelen + sizeof (STUB_SUFFIX);
4441 s_name = (char *) bfd_alloc (htab->stub_bfd, len);
4442 if (s_name == NULL)
4443 return NULL;
4444
4445 memcpy (s_name, stub_sec_prefix, namelen);
4446 memcpy (s_name + namelen, STUB_SUFFIX, sizeof (STUB_SUFFIX));
4447 *stub_sec_p = (*htab->add_stub_section) (s_name, out_sec, link_sec,
4448 align);
4449 if (*stub_sec_p == NULL)
4450 return NULL;
4451
4452 out_sec->flags |= SEC_ALLOC | SEC_LOAD | SEC_READONLY | SEC_CODE
4453 | SEC_HAS_CONTENTS | SEC_RELOC | SEC_IN_MEMORY
4454 | SEC_KEEP;
4455 }
4456
4457 if (!dedicated_output_section)
4458 htab->stub_group[section->id].stub_sec = *stub_sec_p;
4459
48229727
JB		 4460 if (link_sec_p)
4461 *link_sec_p = link_sec;
b38cadfb 4462
daa4adae 4463 return *stub_sec_p;
48229727
JB		 4464}
4465
4466/* Add a new stub entry to the stub hash. Not all fields of the new
4467 stub entry are initialised. */
4468
4469static struct elf32_arm_stub_hash_entry *
daa4adae
TP		 4470elf32_arm_add_stub (const char *stub_name, asection *section,
4471 struct elf32_arm_link_hash_table *htab,
4472 enum elf32_arm_stub_type stub_type)
48229727
JB		 4473{
4474 asection *link_sec;
4475 asection *stub_sec;
4476 struct elf32_arm_stub_hash_entry *stub_entry;
4477
daa4adae
TP		 4478 stub_sec = elf32_arm_create_or_find_stub_sec (&link_sec, section, htab,
4479 stub_type);
48229727
JB		 4480 if (stub_sec == NULL)
4481 return NULL;
906e58ca
NC		 4482
4483 /* Enter this entry into the linker stub hash table. */
4484 stub_entry = arm_stub_hash_lookup (&htab->stub_hash_table, stub_name,
4485 TRUE, FALSE);
4486 if (stub_entry == NULL)
4487 {
6bde4c52
TP		 4488 if (section == NULL)
4489 section = stub_sec;
dae82561 4490 _bfd_error_handler (_("%B: cannot create stub entry %s"),
4eca0228 4491 section->owner, stub_name);
906e58ca
NC		 4492 return NULL;
4493 }
4494
4495 stub_entry->stub_sec = stub_sec;
0955507f 4496 stub_entry->stub_offset = (bfd_vma) -1;
906e58ca
NC		 4497 stub_entry->id_sec = link_sec;
4498
906e58ca
NC		 4499 return stub_entry;
4500}
4501
4502/* Store an Arm insn into an output section not processed by
4503 elf32_arm_write_section. */
4504
4505static void
8029a119
NC		 4506put_arm_insn (struct elf32_arm_link_hash_table * htab,
4507 bfd * output_bfd, bfd_vma val, void * ptr)
906e58ca
NC		 4508{
4509 if (htab->byteswap_code != bfd_little_endian (output_bfd))
4510 bfd_putl32 (val, ptr);
4511 else
4512 bfd_putb32 (val, ptr);
4513}
4514
4515/* Store a 16-bit Thumb insn into an output section not processed by
4516 elf32_arm_write_section. */
4517
4518static void
8029a119
NC		 4519put_thumb_insn (struct elf32_arm_link_hash_table * htab,
4520 bfd * output_bfd, bfd_vma val, void * ptr)
906e58ca
NC		 4521{
4522 if (htab->byteswap_code != bfd_little_endian (output_bfd))
4523 bfd_putl16 (val, ptr);
4524 else
4525 bfd_putb16 (val, ptr);
4526}
4527
a504d23a
LA		 4528/* Store a Thumb2 insn into an output section not processed by
4529 elf32_arm_write_section. */
4530
4531static void
4532put_thumb2_insn (struct elf32_arm_link_hash_table * htab,
b98e6871 4533 bfd * output_bfd, bfd_vma val, bfd_byte * ptr)
a504d23a
LA		 4534{
4535 /* T2 instructions are 16-bit streamed. */
4536 if (htab->byteswap_code != bfd_little_endian (output_bfd))
4537 {
4538 bfd_putl16 ((val >> 16) & 0xffff, ptr);
4539 bfd_putl16 ((val & 0xffff), ptr + 2);
4540 }
4541 else
4542 {
4543 bfd_putb16 ((val >> 16) & 0xffff, ptr);
4544 bfd_putb16 ((val & 0xffff), ptr + 2);
4545 }
4546}
4547
0855e32b
NS		 4548/* If it's possible to change R_TYPE to a more efficient access
4549 model, return the new reloc type. */
4550
4551static unsigned
b38cadfb 4552elf32_arm_tls_transition (struct bfd_link_info *info, int r_type,
0855e32b
NS		 4553 struct elf_link_hash_entry *h)
4554{
4555 int is_local = (h == NULL);
4556
0e1862bb
L		 4557 if (bfd_link_pic (info)
4558 || (h && h->root.type == bfd_link_hash_undefweak))
0855e32b
NS		 4559 return r_type;
4560
b38cadfb 4561 /* We do not support relaxations for Old TLS models. */
0855e32b
NS		 4562 switch (r_type)
4563 {
4564 case R_ARM_TLS_GOTDESC:
4565 case R_ARM_TLS_CALL:
4566 case R_ARM_THM_TLS_CALL:
4567 case R_ARM_TLS_DESCSEQ:
4568 case R_ARM_THM_TLS_DESCSEQ:
4569 return is_local ? R_ARM_TLS_LE32 : R_ARM_TLS_IE32;
4570 }
4571
4572 return r_type;
4573}
4574
48229727
JB		 4575static bfd_reloc_status_type elf32_arm_final_link_relocate
4576 (reloc_howto_type *, bfd *, bfd *, asection *, bfd_byte *,
4577 Elf_Internal_Rela *, bfd_vma, struct bfd_link_info *, asection *,
34e77a92
RS		 4578 const char *, unsigned char, enum arm_st_branch_type,
4579 struct elf_link_hash_entry *, bfd_boolean *, char **);
48229727 4580
4563a860
JB		 4581static unsigned int
4582arm_stub_required_alignment (enum elf32_arm_stub_type stub_type)
4583{
4584 switch (stub_type)
4585 {
4586 case arm_stub_a8_veneer_b_cond:
4587 case arm_stub_a8_veneer_b:
4588 case arm_stub_a8_veneer_bl:
4589 return 2;
4590
4591 case arm_stub_long_branch_any_any:
4592 case arm_stub_long_branch_v4t_arm_thumb:
4593 case arm_stub_long_branch_thumb_only:
80c135e5 4594 case arm_stub_long_branch_thumb2_only:
d5a67c02 4595 case arm_stub_long_branch_thumb2_only_pure:
4563a860
JB		 4596 case arm_stub_long_branch_v4t_thumb_thumb:
4597 case arm_stub_long_branch_v4t_thumb_arm:
4598 case arm_stub_short_branch_v4t_thumb_arm:
4599 case arm_stub_long_branch_any_arm_pic:
4600 case arm_stub_long_branch_any_thumb_pic:
4601 case arm_stub_long_branch_v4t_thumb_thumb_pic:
4602 case arm_stub_long_branch_v4t_arm_thumb_pic:
4603 case arm_stub_long_branch_v4t_thumb_arm_pic:
4604 case arm_stub_long_branch_thumb_only_pic:
0855e32b
NS		 4605 case arm_stub_long_branch_any_tls_pic:
4606 case arm_stub_long_branch_v4t_thumb_tls_pic:
4ba2ef8f 4607 case arm_stub_cmse_branch_thumb_only:
4563a860
JB		 4608 case arm_stub_a8_veneer_blx:
4609 return 4;
b38cadfb 4610
7a89b94e
NC		 4611 case arm_stub_long_branch_arm_nacl:
4612 case arm_stub_long_branch_arm_nacl_pic:
4613 return 16;
4614
4563a860
JB		 4615 default:
4616 abort (); /* Should be unreachable. */
4617 }
4618}
4619
4f4faa4d
TP		 4620/* Returns whether stubs of type STUB_TYPE take over the symbol they are
4621 veneering (TRUE) or have their own symbol (FALSE). */
4622
4623static bfd_boolean
4624arm_stub_sym_claimed (enum elf32_arm_stub_type stub_type)
4625{
4626 if (stub_type >= max_stub_type)
4627 abort (); /* Should be unreachable. */
4628
4ba2ef8f
TP		 4629 switch (stub_type)
4630 {
4631 case arm_stub_cmse_branch_thumb_only:
4632 return TRUE;
4633
4634 default:
4635 return FALSE;
4636 }
4637
4638 abort (); /* Should be unreachable. */
4f4faa4d
TP		 4639}
4640
d7c5bd02
TP		 4641/* Returns the padding needed for the dedicated section used stubs of type
4642 STUB_TYPE. */
4643
4644static int
4645arm_dedicated_stub_section_padding (enum elf32_arm_stub_type stub_type)
4646{
4647 if (stub_type >= max_stub_type)
4648 abort (); /* Should be unreachable. */
4649
4ba2ef8f
TP		 4650 switch (stub_type)
4651 {
4652 case arm_stub_cmse_branch_thumb_only:
4653 return 32;
4654
4655 default:
4656 return 0;
4657 }
4658
4659 abort (); /* Should be unreachable. */
d7c5bd02
TP		 4660}
4661
0955507f
TP		 4662/* If veneers of type STUB_TYPE should go in a dedicated output section,
4663 returns the address of the hash table field in HTAB holding the offset at
4664 which new veneers should be layed out in the stub section. */
4665
4666static bfd_vma*
4667arm_new_stubs_start_offset_ptr (struct elf32_arm_link_hash_table *htab,
4668 enum elf32_arm_stub_type stub_type)
4669{
4670 switch (stub_type)
4671 {
4672 case arm_stub_cmse_branch_thumb_only:
4673 return &htab->new_cmse_stub_offset;
4674
4675 default:
4676 BFD_ASSERT (!arm_dedicated_stub_output_section_required (stub_type));
4677 return NULL;
4678 }
4679}
4680
906e58ca
NC		 4681static bfd_boolean
4682arm_build_one_stub (struct bfd_hash_entry *gen_entry,
4683 void * in_arg)
4684{
7a89b94e 4685#define MAXRELOCS 3
0955507f 4686 bfd_boolean removed_sg_veneer;
906e58ca 4687 struct elf32_arm_stub_hash_entry *stub_entry;
4dfe6ac6 4688 struct elf32_arm_link_hash_table *globals;
906e58ca 4689 struct bfd_link_info *info;
906e58ca
NC		 4690 asection *stub_sec;
4691 bfd *stub_bfd;
906e58ca
NC		 4692 bfd_byte *loc;
4693 bfd_vma sym_value;
4694 int template_size;
4695 int size;
d3ce72d0 4696 const insn_sequence *template_sequence;
906e58ca 4697 int i;
48229727
JB		 4698 int stub_reloc_idx[MAXRELOCS] = {-1, -1};
4699 int stub_reloc_offset[MAXRELOCS] = {0, 0};
4700 int nrelocs = 0;
0955507f 4701 int just_allocated = 0;
906e58ca
NC		 4702
4703 /* Massage our args to the form they really have. */
4704 stub_entry = (struct elf32_arm_stub_hash_entry *) gen_entry;
4705 info = (struct bfd_link_info *) in_arg;
4706
4707 globals = elf32_arm_hash_table (info);
4dfe6ac6
NC		 4708 if (globals == NULL)
4709 return FALSE;
906e58ca 4710
906e58ca
NC		 4711 stub_sec = stub_entry->stub_sec;
4712
4dfe6ac6 4713 if ((globals->fix_cortex_a8 < 0)
4563a860
JB		 4714 != (arm_stub_required_alignment (stub_entry->stub_type) == 2))
4715 /* We have to do less-strictly-aligned fixes last. */
eb7c4339 4716 return TRUE;
fe33d2fa 4717
0955507f
TP		 4718 /* Assign a slot at the end of section if none assigned yet. */
4719 if (stub_entry->stub_offset == (bfd_vma) -1)
4720 {
4721 stub_entry->stub_offset = stub_sec->size;
4722 just_allocated = 1;
4723 }
906e58ca
NC		 4724 loc = stub_sec->contents + stub_entry->stub_offset;
4725
4726 stub_bfd = stub_sec->owner;
4727
906e58ca
NC		 4728 /* This is the address of the stub destination. */
4729 sym_value = (stub_entry->target_value
4730 + stub_entry->target_section->output_offset
4731 + stub_entry->target_section->output_section->vma);
4732
d3ce72d0 4733 template_sequence = stub_entry->stub_template;
461a49ca 4734 template_size = stub_entry->stub_template_size;
906e58ca
NC		 4735
4736 size = 0;
461a49ca 4737 for (i = 0; i < template_size; i++)
906e58ca 4738 {
d3ce72d0 4739 switch (template_sequence[i].type)
461a49ca
DJ		 4740 {
4741 case THUMB16_TYPE:
48229727 4742 {
d3ce72d0
NC		 4743 bfd_vma data = (bfd_vma) template_sequence[i].data;
4744 if (template_sequence[i].reloc_addend != 0)
48229727 4745 {
99059e56
RM		 4746 /* We've borrowed the reloc_addend field to mean we should
4747 insert a condition code into this (Thumb-1 branch)
4748 instruction. See THUMB16_BCOND_INSN. */
4749 BFD_ASSERT ((data & 0xff00) == 0xd000);
4750 data |= ((stub_entry->orig_insn >> 22) & 0xf) << 8;
48229727 4751 }
fe33d2fa 4752 bfd_put_16 (stub_bfd, data, loc + size);
48229727
JB		 4753 size += 2;
4754 }
461a49ca 4755 break;
906e58ca 4756
48229727 4757 case THUMB32_TYPE:
fe33d2fa
CL		 4758 bfd_put_16 (stub_bfd,
4759 (template_sequence[i].data >> 16) & 0xffff,
4760 loc + size);
4761 bfd_put_16 (stub_bfd, template_sequence[i].data & 0xffff,
4762 loc + size + 2);
99059e56
RM		 4763 if (template_sequence[i].r_type != R_ARM_NONE)
4764 {
4765 stub_reloc_idx[nrelocs] = i;
4766 stub_reloc_offset[nrelocs++] = size;
4767 }
4768 size += 4;
4769 break;
48229727 4770
461a49ca 4771 case ARM_TYPE:
fe33d2fa
CL		 4772 bfd_put_32 (stub_bfd, template_sequence[i].data,
4773 loc + size);
461a49ca
DJ		 4774 /* Handle cases where the target is encoded within the
4775 instruction. */
d3ce72d0 4776 if (template_sequence[i].r_type == R_ARM_JUMP24)
461a49ca 4777 {
48229727
JB		 4778 stub_reloc_idx[nrelocs] = i;
4779 stub_reloc_offset[nrelocs++] = size;
461a49ca
DJ		 4780 }
4781 size += 4;
4782 break;
4783
4784 case DATA_TYPE:
d3ce72d0 4785 bfd_put_32 (stub_bfd, template_sequence[i].data, loc + size);
48229727
JB		 4786 stub_reloc_idx[nrelocs] = i;
4787 stub_reloc_offset[nrelocs++] = size;
461a49ca
DJ		 4788 size += 4;
4789 break;
4790
4791 default:
4792 BFD_FAIL ();
4793 return FALSE;
4794 }
906e58ca 4795 }
461a49ca 4796
0955507f
TP		 4797 if (just_allocated)
4798 stub_sec->size += size;
906e58ca 4799
461a49ca
DJ		 4800 /* Stub size has already been computed in arm_size_one_stub. Check
4801 consistency. */
4802 BFD_ASSERT (size == stub_entry->stub_size);
4803
906e58ca 4804 /* Destination is Thumb. Force bit 0 to 1 to reflect this. */
35fc36a8 4805 if (stub_entry->branch_type == ST_BRANCH_TO_THUMB)
906e58ca
NC		 4806 sym_value |= 1;
4807
0955507f
TP		 4808 /* Assume non empty slots have at least one and at most MAXRELOCS entries
4809 to relocate in each stub. */
4810 removed_sg_veneer =
4811 (size == 0 && stub_entry->stub_type == arm_stub_cmse_branch_thumb_only);
4812 BFD_ASSERT (removed_sg_veneer || (nrelocs != 0 && nrelocs <= MAXRELOCS));
c820be07 4813
48229727 4814 for (i = 0; i < nrelocs; i++)
8d9d9490
TP		 4815 {
4816 Elf_Internal_Rela rel;
4817 bfd_boolean unresolved_reloc;
4818 char *error_message;
4819 bfd_vma points_to =
4820 sym_value + template_sequence[stub_reloc_idx[i]].reloc_addend;
4821
4822 rel.r_offset = stub_entry->stub_offset + stub_reloc_offset[i];
4823 rel.r_info = ELF32_R_INFO (0,
4824 template_sequence[stub_reloc_idx[i]].r_type);
4825 rel.r_addend = 0;
4826
4827 if (stub_entry->stub_type == arm_stub_a8_veneer_b_cond && i == 0)
4828 /* The first relocation in the elf32_arm_stub_a8_veneer_b_cond[]
4829 template should refer back to the instruction after the original
4830 branch. We use target_section as Cortex-A8 erratum workaround stubs
4831 are only generated when both source and target are in the same
4832 section. */
4833 points_to = stub_entry->target_section->output_section->vma
4834 + stub_entry->target_section->output_offset
4835 + stub_entry->source_value;
4836
4837 elf32_arm_final_link_relocate (elf32_arm_howto_from_type
4838 (template_sequence[stub_reloc_idx[i]].r_type),
4839 stub_bfd, info->output_bfd, stub_sec, stub_sec->contents, &rel,
4840 points_to, info, stub_entry->target_section, "", STT_FUNC,
4841 stub_entry->branch_type,
4842 (struct elf_link_hash_entry *) stub_entry->h, &unresolved_reloc,
4843 &error_message);
4844 }
906e58ca
NC		 4845
4846 return TRUE;
48229727 4847#undef MAXRELOCS
906e58ca
NC		 4848}
4849
48229727
JB		 4850/* Calculate the template, template size and instruction size for a stub.
4851 Return value is the instruction size. */
906e58ca 4852
48229727
JB		 4853static unsigned int
4854find_stub_size_and_template (enum elf32_arm_stub_type stub_type,
4855 const insn_sequence **stub_template,
4856 int *stub_template_size)
906e58ca 4857{
d3ce72d0 4858 const insn_sequence *template_sequence = NULL;
48229727
JB		 4859 int template_size = 0, i;
4860 unsigned int size;
906e58ca 4861
d3ce72d0 4862 template_sequence = stub_definitions[stub_type].template_sequence;
2a229407
AM		 4863 if (stub_template)
4864 *stub_template = template_sequence;
4865
48229727 4866 template_size = stub_definitions[stub_type].template_size;
2a229407
AM		 4867 if (stub_template_size)
4868 *stub_template_size = template_size;
906e58ca
NC		 4869
4870 size = 0;
461a49ca
DJ		 4871 for (i = 0; i < template_size; i++)
4872 {
d3ce72d0 4873 switch (template_sequence[i].type)
461a49ca
DJ		 4874 {
4875 case THUMB16_TYPE:
4876 size += 2;
4877 break;
4878
4879 case ARM_TYPE:
48229727 4880 case THUMB32_TYPE:
461a49ca
DJ		 4881 case DATA_TYPE:
4882 size += 4;
4883 break;
4884
4885 default:
4886 BFD_FAIL ();
2a229407 4887 return 0;
461a49ca
DJ		 4888 }
4889 }
4890
48229727
JB		 4891 return size;
4892}
4893
4894/* As above, but don't actually build the stub. Just bump offset so
4895 we know stub section sizes. */
4896
4897static bfd_boolean
4898arm_size_one_stub (struct bfd_hash_entry *gen_entry,
c7e2358a 4899 void *in_arg ATTRIBUTE_UNUSED)
48229727
JB		 4900{
4901 struct elf32_arm_stub_hash_entry *stub_entry;
d3ce72d0 4902 const insn_sequence *template_sequence;
48229727
JB		 4903 int template_size, size;
4904
4905 /* Massage our args to the form they really have. */
4906 stub_entry = (struct elf32_arm_stub_hash_entry *) gen_entry;
48229727
JB		 4907
4908 BFD_ASSERT((stub_entry->stub_type > arm_stub_none)
4909 && stub_entry->stub_type < ARRAY_SIZE(stub_definitions));
4910
d3ce72d0 4911 size = find_stub_size_and_template (stub_entry->stub_type, &template_sequence,
48229727
JB		 4912 &template_size);
4913
0955507f
TP		 4914 /* Initialized to -1. Null size indicates an empty slot full of zeros. */
4915 if (stub_entry->stub_template_size)
4916 {
4917 stub_entry->stub_size = size;
4918 stub_entry->stub_template = template_sequence;
4919 stub_entry->stub_template_size = template_size;
4920 }
4921
4922 /* Already accounted for. */
4923 if (stub_entry->stub_offset != (bfd_vma) -1)
4924 return TRUE;
461a49ca 4925
906e58ca
NC		 4926 size = (size + 7) & ~7;
4927 stub_entry->stub_sec->size += size;
461a49ca 4928
906e58ca
NC		 4929 return TRUE;
4930}
4931
4932/* External entry points for sizing and building linker stubs. */
4933
4934/* Set up various things so that we can make a list of input sections
4935 for each output section included in the link. Returns -1 on error,
4936 0 when no stubs will be needed, and 1 on success. */
4937
4938int
4939elf32_arm_setup_section_lists (bfd *output_bfd,
4940 struct bfd_link_info *info)
4941{
4942 bfd *input_bfd;
4943 unsigned int bfd_count;
7292b3ac 4944 unsigned int top_id, top_index;
906e58ca
NC		 4945 asection *section;
4946 asection **input_list, **list;
4947 bfd_size_type amt;
4948 struct elf32_arm_link_hash_table *htab = elf32_arm_hash_table (info);
4949
4dfe6ac6
NC		 4950 if (htab == NULL)
4951 return 0;
906e58ca
NC		 4952 if (! is_elf_hash_table (htab))
4953 return 0;
4954
4955 /* Count the number of input BFDs and find the top input section id. */
4956 for (input_bfd = info->input_bfds, bfd_count = 0, top_id = 0;
4957 input_bfd != NULL;
c72f2fb2 4958 input_bfd = input_bfd->link.next)
906e58ca
NC		 4959 {
4960 bfd_count += 1;
4961 for (section = input_bfd->sections;
4962 section != NULL;
4963 section = section->next)
4964 {
4965 if (top_id < section->id)
4966 top_id = section->id;
4967 }
4968 }
4969 htab->bfd_count = bfd_count;
4970
4971 amt = sizeof (struct map_stub) * (top_id + 1);
21d799b5 4972 htab->stub_group = (struct map_stub *) bfd_zmalloc (amt);
906e58ca
NC		 4973 if (htab->stub_group == NULL)
4974 return -1;
fe33d2fa 4975 htab->top_id = top_id;
906e58ca
NC		 4976
4977 /* We can't use output_bfd->section_count here to find the top output
4978 section index as some sections may have been removed, and
4979 _bfd_strip_section_from_output doesn't renumber the indices. */
4980 for (section = output_bfd->sections, top_index = 0;
4981 section != NULL;
4982 section = section->next)
4983 {
4984 if (top_index < section->index)
4985 top_index = section->index;
4986 }
4987
4988 htab->top_index = top_index;
4989 amt = sizeof (asection *) * (top_index + 1);
21d799b5 4990 input_list = (asection **) bfd_malloc (amt);
906e58ca
NC		 4991 htab->input_list = input_list;
4992 if (input_list == NULL)
4993 return -1;
4994
4995 /* For sections we aren't interested in, mark their entries with a
4996 value we can check later. */
4997 list = input_list + top_index;
4998 do
4999 *list = bfd_abs_section_ptr;
5000 while (list-- != input_list);
5001
5002 for (section = output_bfd->sections;
5003 section != NULL;
5004 section = section->next)
5005 {
5006 if ((section->flags & SEC_CODE) != 0)
5007 input_list[section->index] = NULL;
5008 }
5009
5010 return 1;
5011}
5012
5013/* The linker repeatedly calls this function for each input section,
5014 in the order that input sections are linked into output sections.
5015 Build lists of input sections to determine groupings between which
5016 we may insert linker stubs. */
5017
5018void
5019elf32_arm_next_input_section (struct bfd_link_info *info,
5020 asection *isec)
5021{
5022 struct elf32_arm_link_hash_table *htab = elf32_arm_hash_table (info);
5023
4dfe6ac6
NC		 5024 if (htab == NULL)
5025 return;
5026
906e58ca
NC		 5027 if (isec->output_section->index <= htab->top_index)
5028 {
5029 asection **list = htab->input_list + isec->output_section->index;
5030
a7470592 5031 if (*list != bfd_abs_section_ptr && (isec->flags & SEC_CODE) != 0)
906e58ca
NC		 5032 {
5033 /* Steal the link_sec pointer for our list. */
5034#define PREV_SEC(sec) (htab->stub_group[(sec)->id].link_sec)
5035 /* This happens to make the list in reverse order,
07d72278 5036 which we reverse later. */
906e58ca
NC		 5037 PREV_SEC (isec) = *list;
5038 *list = isec;
5039 }
5040 }
5041}
5042
5043/* See whether we can group stub sections together. Grouping stub
5044 sections may result in fewer stubs. More importantly, we need to
07d72278 5045 put all .init* and .fini* stubs at the end of the .init or
906e58ca
NC		 5046 .fini output sections respectively, because glibc splits the
5047 _init and _fini functions into multiple parts. Putting a stub in
5048 the middle of a function is not a good idea. */
5049
5050static void
5051group_sections (struct elf32_arm_link_hash_table *htab,
5052 bfd_size_type stub_group_size,
07d72278 5053 bfd_boolean stubs_always_after_branch)
906e58ca 5054{
07d72278 5055 asection **list = htab->input_list;
906e58ca
NC		 5056
5057 do
5058 {
5059 asection *tail = *list;
07d72278 5060 asection *head;
906e58ca
NC		 5061
5062 if (tail == bfd_abs_section_ptr)
5063 continue;
5064
07d72278
DJ		 5065 /* Reverse the list: we must avoid placing stubs at the
5066 beginning of the section because the beginning of the text
5067 section may be required for an interrupt vector in bare metal
5068 code. */
5069#define NEXT_SEC PREV_SEC
e780aef2
CL		 5070 head = NULL;
5071 while (tail != NULL)
99059e56
RM		 5072 {
5073 /* Pop from tail. */
5074 asection *item = tail;
5075 tail = PREV_SEC (item);
e780aef2 5076
99059e56
RM		 5077 /* Push on head. */
5078 NEXT_SEC (item) = head;
5079 head = item;
5080 }
07d72278
DJ		 5081
5082 while (head != NULL)
906e58ca
NC		 5083 {
5084 asection *curr;
07d72278 5085 asection *next;
e780aef2
CL		 5086 bfd_vma stub_group_start = head->output_offset;
5087 bfd_vma end_of_next;
906e58ca 5088
07d72278 5089 curr = head;
e780aef2 5090 while (NEXT_SEC (curr) != NULL)
8cd931b7 5091 {
e780aef2
CL		 5092 next = NEXT_SEC (curr);
5093 end_of_next = next->output_offset + next->size;
5094 if (end_of_next - stub_group_start >= stub_group_size)
5095 /* End of NEXT is too far from start, so stop. */
8cd931b7 5096 break;
e780aef2
CL		 5097 /* Add NEXT to the group. */
5098 curr = next;
8cd931b7 5099 }
906e58ca 5100
07d72278 5101 /* OK, the size from the start to the start of CURR is less
906e58ca 5102 than stub_group_size and thus can be handled by one stub
07d72278 5103 section. (Or the head section is itself larger than
906e58ca
NC		 5104 stub_group_size, in which case we may be toast.)
5105 We should really be keeping track of the total size of
5106 stubs added here, as stubs contribute to the final output
7fb9f789 5107 section size. */
906e58ca
NC		 5108 do
5109 {
07d72278 5110 next = NEXT_SEC (head);
906e58ca 5111 /* Set up this stub group. */
07d72278 5112 htab->stub_group[head->id].link_sec = curr;
906e58ca 5113 }
07d72278 5114 while (head != curr && (head = next) != NULL);
906e58ca
NC		 5115
5116 /* But wait, there's more! Input sections up to stub_group_size
07d72278
DJ		 5117 bytes after the stub section can be handled by it too. */
5118 if (!stubs_always_after_branch)
906e58ca 5119 {
e780aef2
CL		 5120 stub_group_start = curr->output_offset + curr->size;
5121
8cd931b7 5122 while (next != NULL)
906e58ca 5123 {
e780aef2
CL		 5124 end_of_next = next->output_offset + next->size;
5125 if (end_of_next - stub_group_start >= stub_group_size)
5126 /* End of NEXT is too far from stubs, so stop. */
8cd931b7 5127 break;
e780aef2 5128 /* Add NEXT to the stub group. */
07d72278
DJ		 5129 head = next;
5130 next = NEXT_SEC (head);
5131 htab->stub_group[head->id].link_sec = curr;
906e58ca
NC		 5132 }
5133 }
07d72278 5134 head = next;
906e58ca
NC		 5135 }
5136 }
07d72278 5137 while (list++ != htab->input_list + htab->top_index);
906e58ca
NC		 5138
5139 free (htab->input_list);
5140#undef PREV_SEC
07d72278 5141#undef NEXT_SEC
906e58ca
NC		 5142}
5143
48229727
JB		 5144/* Comparison function for sorting/searching relocations relating to Cortex-A8
5145 erratum fix. */
5146
5147static int
5148a8_reloc_compare (const void *a, const void *b)
5149{
21d799b5
NC		 5150 const struct a8_erratum_reloc *ra = (const struct a8_erratum_reloc *) a;
5151 const struct a8_erratum_reloc *rb = (const struct a8_erratum_reloc *) b;
48229727
JB		 5152
5153 if (ra->from < rb->from)
5154 return -1;
5155 else if (ra->from > rb->from)
5156 return 1;
5157 else
5158 return 0;
5159}
5160
5161static struct elf_link_hash_entry *find_thumb_glue (struct bfd_link_info *,
5162 const char *, char **);
5163
5164/* Helper function to scan code for sequences which might trigger the Cortex-A8
5165 branch/TLB erratum. Fill in the table described by A8_FIXES_P,
81694485 5166 NUM_A8_FIXES_P, A8_FIX_TABLE_SIZE_P. Returns true if an error occurs, false
48229727
JB		 5167 otherwise. */
5168
81694485
NC		 5169static bfd_boolean
5170cortex_a8_erratum_scan (bfd *input_bfd,
5171 struct bfd_link_info *info,
48229727
JB		 5172 struct a8_erratum_fix **a8_fixes_p,
5173 unsigned int *num_a8_fixes_p,
5174 unsigned int *a8_fix_table_size_p,
5175 struct a8_erratum_reloc *a8_relocs,
eb7c4339
NS		 5176 unsigned int num_a8_relocs,
5177 unsigned prev_num_a8_fixes,
5178 bfd_boolean *stub_changed_p)
48229727
JB		 5179{
5180 asection *section;
5181 struct elf32_arm_link_hash_table *htab = elf32_arm_hash_table (info);
5182 struct a8_erratum_fix *a8_fixes = *a8_fixes_p;
5183 unsigned int num_a8_fixes = *num_a8_fixes_p;
5184 unsigned int a8_fix_table_size = *a8_fix_table_size_p;
5185
4dfe6ac6
NC		 5186 if (htab == NULL)
5187 return FALSE;
5188
48229727
JB		 5189 for (section = input_bfd->sections;
5190 section != NULL;
5191 section = section->next)
5192 {
5193 bfd_byte *contents = NULL;
5194 struct _arm_elf_section_data *sec_data;
5195 unsigned int span;
5196 bfd_vma base_vma;
5197
5198 if (elf_section_type (section) != SHT_PROGBITS
99059e56
RM		 5199 || (elf_section_flags (section) & SHF_EXECINSTR) == 0
5200 || (section->flags & SEC_EXCLUDE) != 0
5201 || (section->sec_info_type == SEC_INFO_TYPE_JUST_SYMS)
5202 || (section->output_section == bfd_abs_section_ptr))
5203 continue;
48229727
JB		 5204
5205 base_vma = section->output_section->vma + section->output_offset;
5206
5207 if (elf_section_data (section)->this_hdr.contents != NULL)
99059e56 5208 contents = elf_section_data (section)->this_hdr.contents;
48229727 5209 else if (! bfd_malloc_and_get_section (input_bfd, section, &contents))
99059e56 5210 return TRUE;
48229727
JB		 5211
5212 sec_data = elf32_arm_section_data (section);
5213
5214 for (span = 0; span < sec_data->mapcount; span++)
99059e56
RM		 5215 {
5216 unsigned int span_start = sec_data->map[span].vma;
5217 unsigned int span_end = (span == sec_data->mapcount - 1)
5218 ? section->size : sec_data->map[span + 1].vma;
5219 unsigned int i;
5220 char span_type = sec_data->map[span].type;
5221 bfd_boolean last_was_32bit = FALSE, last_was_branch = FALSE;
5222
5223 if (span_type != 't')
5224 continue;
5225
5226 /* Span is entirely within a single 4KB region: skip scanning. */
5227 if (((base_vma + span_start) & ~0xfff)
48229727 5228 == ((base_vma + span_end) & ~0xfff))
99059e56
RM		 5229 continue;
5230
5231 /* Scan for 32-bit Thumb-2 branches which span two 4K regions, where:
5232
5233 * The opcode is BLX.W, BL.W, B.W, Bcc.W
5234 * The branch target is in the same 4KB region as the
5235 first half of the branch.
5236 * The instruction before the branch is a 32-bit
5237 length non-branch instruction. */
5238 for (i = span_start; i < span_end;)
5239 {
5240 unsigned int insn = bfd_getl16 (&contents[i]);
5241 bfd_boolean insn_32bit = FALSE, is_blx = FALSE, is_b = FALSE;
48229727
JB		 5242 bfd_boolean is_bl = FALSE, is_bcc = FALSE, is_32bit_branch;
5243
99059e56
RM		 5244 if ((insn & 0xe000) == 0xe000 && (insn & 0x1800) != 0x0000)
5245 insn_32bit = TRUE;
48229727
JB		 5246
5247 if (insn_32bit)
99059e56
RM		 5248 {
5249 /* Load the rest of the insn (in manual-friendly order). */
5250 insn = (insn << 16) | bfd_getl16 (&contents[i + 2]);
5251
5252 /* Encoding T4: B<c>.W. */
5253 is_b = (insn & 0xf800d000) == 0xf0009000;
5254 /* Encoding T1: BL<c>.W. */
5255 is_bl = (insn & 0xf800d000) == 0xf000d000;
5256 /* Encoding T2: BLX<c>.W. */
5257 is_blx = (insn & 0xf800d000) == 0xf000c000;
48229727
JB		 5258 /* Encoding T3: B<c>.W (not permitted in IT block). */
5259 is_bcc = (insn & 0xf800d000) == 0xf0008000
5260 && (insn & 0x07f00000) != 0x03800000;
5261 }
5262
5263 is_32bit_branch = is_b || is_bl || is_blx || is_bcc;
fe33d2fa 5264
99059e56 5265 if (((base_vma + i) & 0xfff) == 0xffe
81694485
NC		 5266 && insn_32bit
5267 && is_32bit_branch
5268 && last_was_32bit
5269 && ! last_was_branch)
99059e56
RM		 5270 {
5271 bfd_signed_vma offset = 0;
5272 bfd_boolean force_target_arm = FALSE;
48229727 5273 bfd_boolean force_target_thumb = FALSE;
99059e56
RM		 5274 bfd_vma target;
5275 enum elf32_arm_stub_type stub_type = arm_stub_none;
5276 struct a8_erratum_reloc key, *found;
5277 bfd_boolean use_plt = FALSE;
48229727 5278
99059e56
RM		 5279 key.from = base_vma + i;
5280 found = (struct a8_erratum_reloc *)
5281 bsearch (&key, a8_relocs, num_a8_relocs,
5282 sizeof (struct a8_erratum_reloc),
5283 &a8_reloc_compare);
48229727
JB		 5284
5285 if (found)
5286 {
5287 char *error_message = NULL;
5288 struct elf_link_hash_entry *entry;
5289
5290 /* We don't care about the error returned from this
99059e56 5291 function, only if there is glue or not. */
48229727
JB		 5292 entry = find_thumb_glue (info, found->sym_name,
5293 &error_message);
5294
5295 if (entry)
5296 found->non_a8_stub = TRUE;
5297
92750f34 5298 /* Keep a simpler condition, for the sake of clarity. */
362d30a1 5299 if (htab->root.splt != NULL && found->hash != NULL
92750f34
DJ		 5300 && found->hash->root.plt.offset != (bfd_vma) -1)
5301 use_plt = TRUE;
5302
5303 if (found->r_type == R_ARM_THM_CALL)
5304 {
35fc36a8
RS		 5305 if (found->branch_type == ST_BRANCH_TO_ARM
5306 || use_plt)
92750f34
DJ		 5307 force_target_arm = TRUE;
5308 else
5309 force_target_thumb = TRUE;
5310 }
48229727
JB		 5311 }
5312
99059e56 5313 /* Check if we have an offending branch instruction. */
48229727
JB		 5314
5315 if (found && found->non_a8_stub)
5316 /* We've already made a stub for this instruction, e.g.
5317 it's a long branch or a Thumb->ARM stub. Assume that
5318 stub will suffice to work around the A8 erratum (see
5319 setting of always_after_branch above). */
5320 ;
99059e56
RM		 5321 else if (is_bcc)
5322 {
5323 offset = (insn & 0x7ff) << 1;
5324 offset |= (insn & 0x3f0000) >> 4;
5325 offset |= (insn & 0x2000) ? 0x40000 : 0;
5326 offset |= (insn & 0x800) ? 0x80000 : 0;
5327 offset |= (insn & 0x4000000) ? 0x100000 : 0;
5328 if (offset & 0x100000)
5329 offset |= ~ ((bfd_signed_vma) 0xfffff);
5330 stub_type = arm_stub_a8_veneer_b_cond;
5331 }
5332 else if (is_b || is_bl || is_blx)
5333 {
5334 int s = (insn & 0x4000000) != 0;
5335 int j1 = (insn & 0x2000) != 0;
5336 int j2 = (insn & 0x800) != 0;
5337 int i1 = !(j1 ^ s);
5338 int i2 = !(j2 ^ s);
5339
5340 offset = (insn & 0x7ff) << 1;
5341 offset |= (insn & 0x3ff0000) >> 4;
5342 offset |= i2 << 22;
5343 offset |= i1 << 23;
5344 offset |= s << 24;
5345 if (offset & 0x1000000)
5346 offset |= ~ ((bfd_signed_vma) 0xffffff);
5347
5348 if (is_blx)
5349 offset &= ~ ((bfd_signed_vma) 3);
5350
5351 stub_type = is_blx ? arm_stub_a8_veneer_blx :
5352 is_bl ? arm_stub_a8_veneer_bl : arm_stub_a8_veneer_b;
5353 }
5354
5355 if (stub_type != arm_stub_none)
5356 {
5357 bfd_vma pc_for_insn = base_vma + i + 4;
48229727
JB		 5358
5359 /* The original instruction is a BL, but the target is
99059e56 5360 an ARM instruction. If we were not making a stub,
48229727
JB		 5361 the BL would have been converted to a BLX. Use the
5362 BLX stub instead in that case. */
5363 if (htab->use_blx && force_target_arm
5364 && stub_type == arm_stub_a8_veneer_bl)
5365 {
5366 stub_type = arm_stub_a8_veneer_blx;
5367 is_blx = TRUE;
5368 is_bl = FALSE;
5369 }
5370 /* Conversely, if the original instruction was
5371 BLX but the target is Thumb mode, use the BL
5372 stub. */
5373 else if (force_target_thumb
5374 && stub_type == arm_stub_a8_veneer_blx)
5375 {
5376 stub_type = arm_stub_a8_veneer_bl;
5377 is_blx = FALSE;
5378 is_bl = TRUE;
5379 }
5380
99059e56
RM		 5381 if (is_blx)
5382 pc_for_insn &= ~ ((bfd_vma) 3);
48229727 5383
99059e56
RM		 5384 /* If we found a relocation, use the proper destination,
5385 not the offset in the (unrelocated) instruction.
48229727
JB		 5386 Note this is always done if we switched the stub type
5387 above. */
99059e56
RM		 5388 if (found)
5389 offset =
81694485 5390 (bfd_signed_vma) (found->destination - pc_for_insn);
48229727 5391
99059e56
RM		 5392 /* If the stub will use a Thumb-mode branch to a
5393 PLT target, redirect it to the preceding Thumb
5394 entry point. */
5395 if (stub_type != arm_stub_a8_veneer_blx && use_plt)
5396 offset -= PLT_THUMB_STUB_SIZE;
7d24e6a6 5397
99059e56 5398 target = pc_for_insn + offset;
48229727 5399
99059e56
RM		 5400 /* The BLX stub is ARM-mode code. Adjust the offset to
5401 take the different PC value (+8 instead of +4) into
48229727 5402 account. */
99059e56
RM		 5403 if (stub_type == arm_stub_a8_veneer_blx)
5404 offset += 4;
5405
5406 if (((base_vma + i) & ~0xfff) == (target & ~0xfff))
5407 {
5408 char *stub_name = NULL;
5409
5410 if (num_a8_fixes == a8_fix_table_size)
5411 {
5412 a8_fix_table_size *= 2;
5413 a8_fixes = (struct a8_erratum_fix *)
5414 bfd_realloc (a8_fixes,
5415 sizeof (struct a8_erratum_fix)
5416 * a8_fix_table_size);
5417 }
48229727 5418
eb7c4339
NS		 5419 if (num_a8_fixes < prev_num_a8_fixes)
5420 {
5421 /* If we're doing a subsequent scan,
5422 check if we've found the same fix as
5423 before, and try and reuse the stub
5424 name. */
5425 stub_name = a8_fixes[num_a8_fixes].stub_name;
5426 if ((a8_fixes[num_a8_fixes].section != section)
5427 || (a8_fixes[num_a8_fixes].offset != i))
5428 {
5429 free (stub_name);
5430 stub_name = NULL;
5431 *stub_changed_p = TRUE;
5432 }
5433 }
5434
5435 if (!stub_name)
5436 {
21d799b5 5437 stub_name = (char *) bfd_malloc (8 + 1 + 8 + 1);
eb7c4339
NS		 5438 if (stub_name != NULL)
5439 sprintf (stub_name, "%x:%x", section->id, i);
5440 }
48229727 5441
99059e56
RM		 5442 a8_fixes[num_a8_fixes].input_bfd = input_bfd;
5443 a8_fixes[num_a8_fixes].section = section;
5444 a8_fixes[num_a8_fixes].offset = i;
8d9d9490
TP		 5445 a8_fixes[num_a8_fixes].target_offset =
5446 target - base_vma;
99059e56
RM		 5447 a8_fixes[num_a8_fixes].orig_insn = insn;
5448 a8_fixes[num_a8_fixes].stub_name = stub_name;
5449 a8_fixes[num_a8_fixes].stub_type = stub_type;
5450 a8_fixes[num_a8_fixes].branch_type =
35fc36a8 5451 is_blx ? ST_BRANCH_TO_ARM : ST_BRANCH_TO_THUMB;
48229727 5452
99059e56
RM		 5453 num_a8_fixes++;
5454 }
5455 }
5456 }
48229727 5457
99059e56
RM		 5458 i += insn_32bit ? 4 : 2;
5459 last_was_32bit = insn_32bit;
48229727 5460 last_was_branch = is_32bit_branch;
99059e56
RM		 5461 }
5462 }
48229727
JB		 5463
5464 if (elf_section_data (section)->this_hdr.contents == NULL)
99059e56 5465 free (contents);
48229727 5466 }
fe33d2fa 5467
48229727
JB		 5468 *a8_fixes_p = a8_fixes;
5469 *num_a8_fixes_p = num_a8_fixes;
5470 *a8_fix_table_size_p = a8_fix_table_size;
fe33d2fa 5471
81694485 5472 return FALSE;
48229727
JB		 5473}
5474
b715f643
TP		 5475/* Create or update a stub entry depending on whether the stub can already be
5476 found in HTAB. The stub is identified by:
5477 - its type STUB_TYPE
5478 - its source branch (note that several can share the same stub) whose
5479 section and relocation (if any) are given by SECTION and IRELA
5480 respectively
5481 - its target symbol whose input section, hash, name, value and branch type
5482 are given in SYM_SEC, HASH, SYM_NAME, SYM_VALUE and BRANCH_TYPE
5483 respectively
5484
5485 If found, the value of the stub's target symbol is updated from SYM_VALUE
5486 and *NEW_STUB is set to FALSE. Otherwise, *NEW_STUB is set to
5487 TRUE and the stub entry is initialized.
5488
0955507f
TP		 5489 Returns the stub that was created or updated, or NULL if an error
5490 occurred. */
b715f643 5491
0955507f 5492static struct elf32_arm_stub_hash_entry *
b715f643
TP		 5493elf32_arm_create_stub (struct elf32_arm_link_hash_table *htab,
5494 enum elf32_arm_stub_type stub_type, asection *section,
5495 Elf_Internal_Rela *irela, asection *sym_sec,
5496 struct elf32_arm_link_hash_entry *hash, char *sym_name,
5497 bfd_vma sym_value, enum arm_st_branch_type branch_type,
5498 bfd_boolean *new_stub)
5499{
5500 const asection *id_sec;
5501 char *stub_name;
5502 struct elf32_arm_stub_hash_entry *stub_entry;
5503 unsigned int r_type;
4f4faa4d 5504 bfd_boolean sym_claimed = arm_stub_sym_claimed (stub_type);
b715f643
TP		 5505
5506 BFD_ASSERT (stub_type != arm_stub_none);
5507 *new_stub = FALSE;
5508
4f4faa4d
TP		 5509 if (sym_claimed)
5510 stub_name = sym_name;
5511 else
5512 {
5513 BFD_ASSERT (irela);
5514 BFD_ASSERT (section);
c2abbbeb 5515 BFD_ASSERT (section->id <= htab->top_id);
b715f643 5516
4f4faa4d
TP		 5517 /* Support for grouping stub sections. */
5518 id_sec = htab->stub_group[section->id].link_sec;
b715f643 5519
4f4faa4d
TP		 5520 /* Get the name of this stub. */
5521 stub_name = elf32_arm_stub_name (id_sec, sym_sec, hash, irela,
5522 stub_type);
5523 if (!stub_name)
0955507f 5524 return NULL;
4f4faa4d 5525 }
b715f643
TP		 5526
5527 stub_entry = arm_stub_hash_lookup (&htab->stub_hash_table, stub_name, FALSE,
5528 FALSE);
5529 /* The proper stub has already been created, just update its value. */
5530 if (stub_entry != NULL)
5531 {
4f4faa4d
TP		 5532 if (!sym_claimed)
5533 free (stub_name);
b715f643 5534 stub_entry->target_value = sym_value;
0955507f 5535 return stub_entry;
b715f643
TP		 5536 }
5537
daa4adae 5538 stub_entry = elf32_arm_add_stub (stub_name, section, htab, stub_type);
b715f643
TP		 5539 if (stub_entry == NULL)
5540 {
4f4faa4d
TP		 5541 if (!sym_claimed)
5542 free (stub_name);
0955507f 5543 return NULL;
b715f643
TP		 5544 }
5545
5546 stub_entry->target_value = sym_value;
5547 stub_entry->target_section = sym_sec;
5548 stub_entry->stub_type = stub_type;
5549 stub_entry->h = hash;
5550 stub_entry->branch_type = branch_type;
5551
4f4faa4d
TP		 5552 if (sym_claimed)
5553 stub_entry->output_name = sym_name;
5554 else
b715f643 5555 {
4f4faa4d
TP		 5556 if (sym_name == NULL)
5557 sym_name = "unnamed";
5558 stub_entry->output_name = (char *)
5559 bfd_alloc (htab->stub_bfd, sizeof (THUMB2ARM_GLUE_ENTRY_NAME)
5560 + strlen (sym_name));
5561 if (stub_entry->output_name == NULL)
5562 {
5563 free (stub_name);
0955507f 5564 return NULL;
4f4faa4d 5565 }
b715f643 5566
4f4faa4d
TP		 5567 /* For historical reasons, use the existing names for ARM-to-Thumb and
5568 Thumb-to-ARM stubs. */
5569 r_type = ELF32_R_TYPE (irela->r_info);
5570 if ((r_type == (unsigned int) R_ARM_THM_CALL
5571 || r_type == (unsigned int) R_ARM_THM_JUMP24
5572 || r_type == (unsigned int) R_ARM_THM_JUMP19)
5573 && branch_type == ST_BRANCH_TO_ARM)
5574 sprintf (stub_entry->output_name, THUMB2ARM_GLUE_ENTRY_NAME, sym_name);
5575 else if ((r_type == (unsigned int) R_ARM_CALL
5576 || r_type == (unsigned int) R_ARM_JUMP24)
5577 && branch_type == ST_BRANCH_TO_THUMB)
5578 sprintf (stub_entry->output_name, ARM2THUMB_GLUE_ENTRY_NAME, sym_name);
5579 else
5580 sprintf (stub_entry->output_name, STUB_ENTRY_NAME, sym_name);
5581 }
b715f643
TP		 5582
5583 *new_stub = TRUE;
0955507f 5584 return stub_entry;
b715f643
TP		 5585}
5586
4ba2ef8f
TP		 5587/* Scan symbols in INPUT_BFD to identify secure entry functions needing a
5588 gateway veneer to transition from non secure to secure state and create them
5589 accordingly.
5590
5591 "ARMv8-M Security Extensions: Requirements on Development Tools" document
5592 defines the conditions that govern Secure Gateway veneer creation for a
5593 given symbol <SYM> as follows:
5594 - it has function type
5595 - it has non local binding
5596 - a symbol named __acle_se_<SYM> (called special symbol) exists with the
5597 same type, binding and value as <SYM> (called normal symbol).
5598 An entry function can handle secure state transition itself in which case
5599 its special symbol would have a different value from the normal symbol.
5600
5601 OUT_ATTR gives the output attributes, SYM_HASHES the symbol index to hash
5602 entry mapping while HTAB gives the name to hash entry mapping.
0955507f
TP		 5603 *CMSE_STUB_CREATED is increased by the number of secure gateway veneer
5604 created.
4ba2ef8f 5605
0955507f 5606 The return value gives whether a stub failed to be allocated. */
4ba2ef8f
TP		 5607
5608static bfd_boolean
5609cmse_scan (bfd *input_bfd, struct elf32_arm_link_hash_table *htab,
5610 obj_attribute *out_attr, struct elf_link_hash_entry **sym_hashes,
0955507f 5611 int *cmse_stub_created)
4ba2ef8f
TP		 5612{
5613 const struct elf_backend_data *bed;
5614 Elf_Internal_Shdr *symtab_hdr;
5615 unsigned i, j, sym_count, ext_start;
5616 Elf_Internal_Sym *cmse_sym, *local_syms;
5617 struct elf32_arm_link_hash_entry *hash, *cmse_hash = NULL;
5618 enum arm_st_branch_type branch_type;
5619 char *sym_name, *lsym_name;
5620 bfd_vma sym_value;
5621 asection *section;
0955507f
TP		 5622 struct elf32_arm_stub_hash_entry *stub_entry;
5623 bfd_boolean is_v8m, new_stub, cmse_invalid, ret = TRUE;
4ba2ef8f
TP		 5624
5625 bed = get_elf_backend_data (input_bfd);
5626 symtab_hdr = &elf_tdata (input_bfd)->symtab_hdr;
5627 sym_count = symtab_hdr->sh_size / bed->s->sizeof_sym;
5628 ext_start = symtab_hdr->sh_info;
5629 is_v8m = (out_attr[Tag_CPU_arch].i >= TAG_CPU_ARCH_V8M_BASE
5630 && out_attr[Tag_CPU_arch_profile].i == 'M');
5631
5632 local_syms = (Elf_Internal_Sym *) symtab_hdr->contents;
5633 if (local_syms == NULL)
5634 local_syms = bfd_elf_get_elf_syms (input_bfd, symtab_hdr,
5635 symtab_hdr->sh_info, 0, NULL, NULL,
5636 NULL);
5637 if (symtab_hdr->sh_info && local_syms == NULL)
5638 return FALSE;
5639
5640 /* Scan symbols. */
5641 for (i = 0; i < sym_count; i++)
5642 {
5643 cmse_invalid = FALSE;
5644
5645 if (i < ext_start)
5646 {
5647 cmse_sym = &local_syms[i];
5648 /* Not a special symbol. */
5649 if (!ARM_GET_SYM_CMSE_SPCL (cmse_sym->st_target_internal))
5650 continue;
5651 sym_name = bfd_elf_string_from_elf_section (input_bfd,
5652 symtab_hdr->sh_link,
5653 cmse_sym->st_name);
5654 /* Special symbol with local binding. */
5655 cmse_invalid = TRUE;
5656 }
5657 else
5658 {
5659 cmse_hash = elf32_arm_hash_entry (sym_hashes[i - ext_start]);
5660 sym_name = (char *) cmse_hash->root.root.root.string;
5661
5662 /* Not a special symbol. */
5663 if (!ARM_GET_SYM_CMSE_SPCL (cmse_hash->root.target_internal))
5664 continue;
5665
5666 /* Special symbol has incorrect binding or type. */
5667 if ((cmse_hash->root.root.type != bfd_link_hash_defined
5668 && cmse_hash->root.root.type != bfd_link_hash_defweak)
5669 || cmse_hash->root.type != STT_FUNC)
5670 cmse_invalid = TRUE;
5671 }
5672
5673 if (!is_v8m)
5674 {
4eca0228
AM		 5675 _bfd_error_handler (_("%B: Special symbol `%s' only allowed for "
5676 "ARMv8-M architecture or later."),
5677 input_bfd, sym_name);
4ba2ef8f
TP		 5678 is_v8m = TRUE; /* Avoid multiple warning. */
5679 ret = FALSE;
5680 }
5681
5682 if (cmse_invalid)
5683 {
4eca0228
AM		 5684 _bfd_error_handler (_("%B: invalid special symbol `%s'."),
5685 input_bfd, sym_name);
5686 _bfd_error_handler (_("It must be a global or weak function "
5687 "symbol."));
4ba2ef8f
TP		 5688 ret = FALSE;
5689 if (i < ext_start)
5690 continue;
5691 }
5692
5693 sym_name += strlen (CMSE_PREFIX);
5694 hash = (struct elf32_arm_link_hash_entry *)
5695 elf_link_hash_lookup (&(htab)->root, sym_name, FALSE, FALSE, TRUE);
5696
5697 /* No associated normal symbol or it is neither global nor weak. */
5698 if (!hash
5699 || (hash->root.root.type != bfd_link_hash_defined
5700 && hash->root.root.type != bfd_link_hash_defweak)
5701 || hash->root.type != STT_FUNC)
5702 {
5703 /* Initialize here to avoid warning about use of possibly
5704 uninitialized variable. */
5705 j = 0;
5706
5707 if (!hash)
5708 {
5709 /* Searching for a normal symbol with local binding. */
5710 for (; j < ext_start; j++)
5711 {
5712 lsym_name =
5713 bfd_elf_string_from_elf_section (input_bfd,
5714 symtab_hdr->sh_link,
5715 local_syms[j].st_name);
5716 if (!strcmp (sym_name, lsym_name))
5717 break;
5718 }
5719 }
5720
5721 if (hash || j < ext_start)
5722 {
4eca0228 5723 _bfd_error_handler
4ba2ef8f 5724 (_("%B: invalid standard symbol `%s'."), input_bfd, sym_name);
4eca0228 5725 _bfd_error_handler
4ba2ef8f
TP		 5726 (_("It must be a global or weak function symbol."));
5727 }
5728 else
4eca0228 5729 _bfd_error_handler
4ba2ef8f
TP		 5730 (_("%B: absent standard symbol `%s'."), input_bfd, sym_name);
5731 ret = FALSE;
5732 if (!hash)
5733 continue;
5734 }
5735
5736 sym_value = hash->root.root.u.def.value;
5737 section = hash->root.root.u.def.section;
5738
5739 if (cmse_hash->root.root.u.def.section != section)
5740 {
4eca0228 5741 _bfd_error_handler
4ba2ef8f
TP		 5742 (_("%B: `%s' and its special symbol are in different sections."),
5743 input_bfd, sym_name);
5744 ret = FALSE;
5745 }
5746 if (cmse_hash->root.root.u.def.value != sym_value)
5747 continue; /* Ignore: could be an entry function starting with SG. */
5748
5749 /* If this section is a link-once section that will be discarded, then
5750 don't create any stubs. */
5751 if (section->output_section == NULL)
5752 {
4eca0228 5753 _bfd_error_handler
4ba2ef8f
TP		 5754 (_("%B: entry function `%s' not output."), input_bfd, sym_name);
5755 continue;
5756 }
5757
5758 if (hash->root.size == 0)
5759 {
4eca0228 5760 _bfd_error_handler
4ba2ef8f
TP		 5761 (_("%B: entry function `%s' is empty."), input_bfd, sym_name);
5762 ret = FALSE;
5763 }
5764
5765 if (!ret)
5766 continue;
5767 branch_type = ARM_GET_SYM_BRANCH_TYPE (hash->root.target_internal);
0955507f 5768 stub_entry
4ba2ef8f
TP		 5769 = elf32_arm_create_stub (htab, arm_stub_cmse_branch_thumb_only,
5770 NULL, NULL, section, hash, sym_name,
5771 sym_value, branch_type, &new_stub);
5772
0955507f 5773 if (stub_entry == NULL)
4ba2ef8f
TP		 5774 ret = FALSE;
5775 else
5776 {
5777 BFD_ASSERT (new_stub);
0955507f 5778 (*cmse_stub_created)++;
4ba2ef8f
TP		 5779 }
5780 }
5781
5782 if (!symtab_hdr->contents)
5783 free (local_syms);
5784 return ret;
5785}
5786
0955507f
TP		 5787/* Return TRUE iff a symbol identified by its linker HASH entry is a secure
5788 code entry function, ie can be called from non secure code without using a
5789 veneer. */
5790
5791static bfd_boolean
5792cmse_entry_fct_p (struct elf32_arm_link_hash_entry *hash)
5793{
42484486 5794 bfd_byte contents[4];
0955507f
TP		 5795 uint32_t first_insn;
5796 asection *section;
5797 file_ptr offset;
5798 bfd *abfd;
5799
5800 /* Defined symbol of function type. */
5801 if (hash->root.root.type != bfd_link_hash_defined
5802 && hash->root.root.type != bfd_link_hash_defweak)
5803 return FALSE;
5804 if (hash->root.type != STT_FUNC)
5805 return FALSE;
5806
5807 /* Read first instruction. */
5808 section = hash->root.root.u.def.section;
5809 abfd = section->owner;
5810 offset = hash->root.root.u.def.value - section->vma;
42484486
TP		 5811 if (!bfd_get_section_contents (abfd, section, contents, offset,
5812 sizeof (contents)))
0955507f
TP		 5813 return FALSE;
5814
42484486
TP		 5815 first_insn = bfd_get_32 (abfd, contents);
5816
5817 /* Starts by SG instruction. */
0955507f
TP		 5818 return first_insn == 0xe97fe97f;
5819}
5820
5821/* Output the name (in symbol table) of the veneer GEN_ENTRY if it is a new
5822 secure gateway veneers (ie. the veneers was not in the input import library)
5823 and there is no output import library (GEN_INFO->out_implib_bfd is NULL. */
5824
5825static bfd_boolean
5826arm_list_new_cmse_stub (struct bfd_hash_entry *gen_entry, void *gen_info)
5827{
5828 struct elf32_arm_stub_hash_entry *stub_entry;
5829 struct bfd_link_info *info;
5830
5831 /* Massage our args to the form they really have. */
5832 stub_entry = (struct elf32_arm_stub_hash_entry *) gen_entry;
5833 info = (struct bfd_link_info *) gen_info;
5834
5835 if (info->out_implib_bfd)
5836 return TRUE;
5837
5838 if (stub_entry->stub_type != arm_stub_cmse_branch_thumb_only)
5839 return TRUE;
5840
5841 if (stub_entry->stub_offset == (bfd_vma) -1)
4eca0228 5842 _bfd_error_handler (" %s", stub_entry->output_name);
0955507f
TP		 5843
5844 return TRUE;
5845}
5846
5847/* Set offset of each secure gateway veneers so that its address remain
5848 identical to the one in the input import library referred by
5849 HTAB->in_implib_bfd. A warning is issued for veneers that disappeared
5850 (present in input import library but absent from the executable being
5851 linked) or if new veneers appeared and there is no output import library
5852 (INFO->out_implib_bfd is NULL and *CMSE_STUB_CREATED is bigger than the
5853 number of secure gateway veneers found in the input import library.
5854
5855 The function returns whether an error occurred. If no error occurred,
5856 *CMSE_STUB_CREATED gives the number of SG veneers created by both cmse_scan
5857 and this function and HTAB->new_cmse_stub_offset is set to the biggest
5858 veneer observed set for new veneers to be layed out after. */
5859
5860static bfd_boolean
5861set_cmse_veneer_addr_from_implib (struct bfd_link_info *info,
5862 struct elf32_arm_link_hash_table *htab,
5863 int *cmse_stub_created)
5864{
5865 long symsize;
5866 char *sym_name;
5867 flagword flags;
5868 long i, symcount;
5869 bfd *in_implib_bfd;
5870 asection *stub_out_sec;
5871 bfd_boolean ret = TRUE;
5872 Elf_Internal_Sym *intsym;
5873 const char *out_sec_name;
5874 bfd_size_type cmse_stub_size;
5875 asymbol **sympp = NULL, *sym;
5876 struct elf32_arm_link_hash_entry *hash;
5877 const insn_sequence *cmse_stub_template;
5878 struct elf32_arm_stub_hash_entry *stub_entry;
5879 int cmse_stub_template_size, new_cmse_stubs_created = *cmse_stub_created;
5880 bfd_vma veneer_value, stub_offset, next_cmse_stub_offset;
5881 bfd_vma cmse_stub_array_start = (bfd_vma) -1, cmse_stub_sec_vma = 0;
5882
5883 /* No input secure gateway import library. */
5884 if (!htab->in_implib_bfd)
5885 return TRUE;
5886
5887 in_implib_bfd = htab->in_implib_bfd;
5888 if (!htab->cmse_implib)
5889 {
4eca0228
AM		 5890 _bfd_error_handler (_("%B: --in-implib only supported for Secure "
5891 "Gateway import libraries."), in_implib_bfd);
0955507f
TP		 5892 return FALSE;
5893 }
5894
5895 /* Get symbol table size. */
5896 symsize = bfd_get_symtab_upper_bound (in_implib_bfd);
5897 if (symsize < 0)
5898 return FALSE;
5899
5900 /* Read in the input secure gateway import library's symbol table. */
5901 sympp = (asymbol **) xmalloc (symsize);
5902 symcount = bfd_canonicalize_symtab (in_implib_bfd, sympp);
5903 if (symcount < 0)
5904 {
5905 ret = FALSE;
5906 goto free_sym_buf;
5907 }
5908
5909 htab->new_cmse_stub_offset = 0;
5910 cmse_stub_size =
5911 find_stub_size_and_template (arm_stub_cmse_branch_thumb_only,
5912 &cmse_stub_template,
5913 &cmse_stub_template_size);
5914 out_sec_name =
5915 arm_dedicated_stub_output_section_name (arm_stub_cmse_branch_thumb_only);
5916 stub_out_sec =
5917 bfd_get_section_by_name (htab->obfd, out_sec_name);
5918 if (stub_out_sec != NULL)
5919 cmse_stub_sec_vma = stub_out_sec->vma;
5920
5921 /* Set addresses of veneers mentionned in input secure gateway import
5922 library's symbol table. */
5923 for (i = 0; i < symcount; i++)
5924 {
5925 sym = sympp[i];
5926 flags = sym->flags;
5927 sym_name = (char *) bfd_asymbol_name (sym);
5928 intsym = &((elf_symbol_type *) sym)->internal_elf_sym;
5929
5930 if (sym->section != bfd_abs_section_ptr
5931 || !(flags & (BSF_GLOBAL | BSF_WEAK))
5932 || (flags & BSF_FUNCTION) != BSF_FUNCTION
5933 || (ARM_GET_SYM_BRANCH_TYPE (intsym->st_target_internal)
5934 != ST_BRANCH_TO_THUMB))
5935 {
4eca0228
AM		 5936 _bfd_error_handler (_("%B: invalid import library entry: `%s'."),
5937 in_implib_bfd, sym_name);
5938 _bfd_error_handler (_("Symbol should be absolute, global and "
5939 "refer to Thumb functions."));
0955507f
TP		 5940 ret = FALSE;
5941 continue;
5942 }
5943
5944 veneer_value = bfd_asymbol_value (sym);
5945 stub_offset = veneer_value - cmse_stub_sec_vma;
5946 stub_entry = arm_stub_hash_lookup (&htab->stub_hash_table, sym_name,
5947 FALSE, FALSE);
5948 hash = (struct elf32_arm_link_hash_entry *)
5949 elf_link_hash_lookup (&(htab)->root, sym_name, FALSE, FALSE, TRUE);
5950
5951 /* Stub entry should have been created by cmse_scan or the symbol be of
5952 a secure function callable from non secure code. */
5953 if (!stub_entry && !hash)
5954 {
5955 bfd_boolean new_stub;
5956
4eca0228 5957 _bfd_error_handler
0955507f
TP		 5958 (_("Entry function `%s' disappeared from secure code."), sym_name);
5959 hash = (struct elf32_arm_link_hash_entry *)
5960 elf_link_hash_lookup (&(htab)->root, sym_name, TRUE, TRUE, TRUE);
5961 stub_entry
5962 = elf32_arm_create_stub (htab, arm_stub_cmse_branch_thumb_only,
5963 NULL, NULL, bfd_abs_section_ptr, hash,
5964 sym_name, veneer_value,
5965 ST_BRANCH_TO_THUMB, &new_stub);
5966 if (stub_entry == NULL)
5967 ret = FALSE;
5968 else
5969 {
5970 BFD_ASSERT (new_stub);
5971 new_cmse_stubs_created++;
5972 (*cmse_stub_created)++;
5973 }
5974 stub_entry->stub_template_size = stub_entry->stub_size = 0;
5975 stub_entry->stub_offset = stub_offset;
5976 }
5977 /* Symbol found is not callable from non secure code. */
5978 else if (!stub_entry)
5979 {
5980 if (!cmse_entry_fct_p (hash))
5981 {
4eca0228
AM		 5982 _bfd_error_handler (_("`%s' refers to a non entry function."),
5983 sym_name);
0955507f
TP		 5984 ret = FALSE;
5985 }
5986 continue;
5987 }
5988 else
5989 {
5990 /* Only stubs for SG veneers should have been created. */
5991 BFD_ASSERT (stub_entry->stub_type == arm_stub_cmse_branch_thumb_only);
5992
5993 /* Check visibility hasn't changed. */
5994 if (!!(flags & BSF_GLOBAL)
5995 != (hash->root.root.type == bfd_link_hash_defined))
4eca0228 5996 _bfd_error_handler
0955507f
TP		 5997 (_("%B: visibility of symbol `%s' has changed."), in_implib_bfd,
5998 sym_name);
5999
6000 stub_entry->stub_offset = stub_offset;
6001 }
6002
6003 /* Size should match that of a SG veneer. */
6004 if (intsym->st_size != cmse_stub_size)
6005 {
4eca0228
AM		 6006 _bfd_error_handler (_("%B: incorrect size for symbol `%s'."),
6007 in_implib_bfd, sym_name);
0955507f
TP		 6008 ret = FALSE;
6009 }
6010
6011 /* Previous veneer address is before current SG veneer section. */
6012 if (veneer_value < cmse_stub_sec_vma)
6013 {
6014 /* Avoid offset underflow. */
6015 if (stub_entry)
6016 stub_entry->stub_offset = 0;
6017 stub_offset = 0;
6018 ret = FALSE;
6019 }
6020
6021 /* Complain if stub offset not a multiple of stub size. */
6022 if (stub_offset % cmse_stub_size)
6023 {
4eca0228 6024 _bfd_error_handler
0955507f
TP		 6025 (_("Offset of veneer for entry function `%s' not a multiple of "
6026 "its size."), sym_name);
6027 ret = FALSE;
6028 }
6029
6030 if (!ret)
6031 continue;
6032
6033 new_cmse_stubs_created--;
6034 if (veneer_value < cmse_stub_array_start)
6035 cmse_stub_array_start = veneer_value;
6036 next_cmse_stub_offset = stub_offset + ((cmse_stub_size + 7) & ~7);
6037 if (next_cmse_stub_offset > htab->new_cmse_stub_offset)
6038 htab->new_cmse_stub_offset = next_cmse_stub_offset;
6039 }
6040
6041 if (!info->out_implib_bfd && new_cmse_stubs_created != 0)
6042 {
6043 BFD_ASSERT (new_cmse_stubs_created > 0);
4eca0228 6044 _bfd_error_handler
0955507f
TP		 6045 (_("new entry function(s) introduced but no output import library "
6046 "specified:"));
6047 bfd_hash_traverse (&htab->stub_hash_table, arm_list_new_cmse_stub, info);
6048 }
6049
6050 if (cmse_stub_array_start != cmse_stub_sec_vma)
6051 {
4eca0228 6052 _bfd_error_handler
0955507f
TP		 6053 (_("Start address of `%s' is different from previous link."),
6054 out_sec_name);
6055 ret = FALSE;
6056 }
6057
6058free_sym_buf:
6059 free (sympp);
6060 return ret;
6061}
6062
906e58ca
NC		 6063/* Determine and set the size of the stub section for a final link.
6064
6065 The basic idea here is to examine all the relocations looking for
6066 PC-relative calls to a target that is unreachable with a "bl"
6067 instruction. */
6068
6069bfd_boolean
6070elf32_arm_size_stubs (bfd *output_bfd,
6071 bfd *stub_bfd,
6072 struct bfd_link_info *info,
6073 bfd_signed_vma group_size,
7a89b94e 6074 asection * (*add_stub_section) (const char *, asection *,
6bde4c52 6075 asection *,
7a89b94e 6076 unsigned int),
906e58ca
NC		 6077 void (*layout_sections_again) (void))
6078{
0955507f 6079 bfd_boolean ret = TRUE;
4ba2ef8f 6080 obj_attribute *out_attr;
0955507f 6081 int cmse_stub_created = 0;
906e58ca 6082 bfd_size_type stub_group_size;
4ba2ef8f 6083 bfd_boolean m_profile, stubs_always_after_branch, first_veneer_scan = TRUE;
906e58ca 6084 struct elf32_arm_link_hash_table *htab = elf32_arm_hash_table (info);
48229727 6085 struct a8_erratum_fix *a8_fixes = NULL;
eb7c4339 6086 unsigned int num_a8_fixes = 0, a8_fix_table_size = 10;
48229727
JB		 6087 struct a8_erratum_reloc *a8_relocs = NULL;
6088 unsigned int num_a8_relocs = 0, a8_reloc_table_size = 10, i;
6089
4dfe6ac6
NC		 6090 if (htab == NULL)
6091 return FALSE;
6092
48229727
JB		 6093 if (htab->fix_cortex_a8)
6094 {
21d799b5 6095 a8_fixes = (struct a8_erratum_fix *)
99059e56 6096 bfd_zmalloc (sizeof (struct a8_erratum_fix) * a8_fix_table_size);
21d799b5 6097 a8_relocs = (struct a8_erratum_reloc *)
99059e56 6098 bfd_zmalloc (sizeof (struct a8_erratum_reloc) * a8_reloc_table_size);
48229727 6099 }
906e58ca
NC		 6100
6101 /* Propagate mach to stub bfd, because it may not have been
6102 finalized when we created stub_bfd. */
6103 bfd_set_arch_mach (stub_bfd, bfd_get_arch (output_bfd),
6104 bfd_get_mach (output_bfd));
6105
6106 /* Stash our params away. */
6107 htab->stub_bfd = stub_bfd;
6108 htab->add_stub_section = add_stub_section;
6109 htab->layout_sections_again = layout_sections_again;
07d72278 6110 stubs_always_after_branch = group_size < 0;
48229727 6111
4ba2ef8f
TP		 6112 out_attr = elf_known_obj_attributes_proc (output_bfd);
6113 m_profile = out_attr[Tag_CPU_arch_profile].i == 'M';
0955507f 6114
48229727
JB		 6115 /* The Cortex-A8 erratum fix depends on stubs not being in the same 4K page
6116 as the first half of a 32-bit branch straddling two 4K pages. This is a
6117 crude way of enforcing that. */
6118 if (htab->fix_cortex_a8)
6119 stubs_always_after_branch = 1;
6120
906e58ca
NC		 6121 if (group_size < 0)
6122 stub_group_size = -group_size;
6123 else
6124 stub_group_size = group_size;
6125
6126 if (stub_group_size == 1)
6127 {
6128 /* Default values. */
6129 /* Thumb branch range is +-4MB has to be used as the default
6130 maximum size (a given section can contain both ARM and Thumb
6131 code, so the worst case has to be taken into account).
6132
6133 This value is 24K less than that, which allows for 2025
6134 12-byte stubs. If we exceed that, then we will fail to link.
6135 The user will have to relink with an explicit group size
6136 option. */
6137 stub_group_size = 4170000;
6138 }
6139
07d72278 6140 group_sections (htab, stub_group_size, stubs_always_after_branch);
906e58ca 6141
3ae046cc
NS		 6142 /* If we're applying the cortex A8 fix, we need to determine the
6143 program header size now, because we cannot change it later --
6144 that could alter section placements. Notice the A8 erratum fix
6145 ends up requiring the section addresses to remain unchanged
6146 modulo the page size. That's something we cannot represent
6147 inside BFD, and we don't want to force the section alignment to
6148 be the page size. */
6149 if (htab->fix_cortex_a8)
6150 (*htab->layout_sections_again) ();
6151
906e58ca
NC		 6152 while (1)
6153 {
6154 bfd *input_bfd;
6155 unsigned int bfd_indx;
6156 asection *stub_sec;
d7c5bd02 6157 enum elf32_arm_stub_type stub_type;
eb7c4339
NS		 6158 bfd_boolean stub_changed = FALSE;
6159 unsigned prev_num_a8_fixes = num_a8_fixes;
906e58ca 6160
48229727 6161 num_a8_fixes = 0;
906e58ca
NC		 6162 for (input_bfd = info->input_bfds, bfd_indx = 0;
6163 input_bfd != NULL;
c72f2fb2 6164 input_bfd = input_bfd->link.next, bfd_indx++)
906e58ca
NC		 6165 {
6166 Elf_Internal_Shdr *symtab_hdr;
6167 asection *section;
6168 Elf_Internal_Sym *local_syms = NULL;
6169
99059e56
RM		 6170 if (!is_arm_elf (input_bfd))
6171 continue;
adbcc655 6172
48229727
JB		 6173 num_a8_relocs = 0;
6174
906e58ca
NC		 6175 /* We'll need the symbol table in a second. */
6176 symtab_hdr = &elf_tdata (input_bfd)->symtab_hdr;
6177 if (symtab_hdr->sh_info == 0)
6178 continue;
6179
4ba2ef8f
TP		 6180 /* Limit scan of symbols to object file whose profile is
6181 Microcontroller to not hinder performance in the general case. */
6182 if (m_profile && first_veneer_scan)
6183 {
6184 struct elf_link_hash_entry **sym_hashes;
6185
6186 sym_hashes = elf_sym_hashes (input_bfd);
6187 if (!cmse_scan (input_bfd, htab, out_attr, sym_hashes,
0955507f 6188 &cmse_stub_created))
4ba2ef8f 6189 goto error_ret_free_local;
0955507f
TP		 6190
6191 if (cmse_stub_created != 0)
6192 stub_changed = TRUE;
4ba2ef8f
TP		 6193 }
6194
906e58ca
NC		 6195 /* Walk over each section attached to the input bfd. */
6196 for (section = input_bfd->sections;
6197 section != NULL;
6198 section = section->next)
6199 {
6200 Elf_Internal_Rela *internal_relocs, *irelaend, *irela;
6201
6202 /* If there aren't any relocs, then there's nothing more
6203 to do. */
6204 if ((section->flags & SEC_RELOC) == 0
6205 || section->reloc_count == 0
6206 || (section->flags & SEC_CODE) == 0)
6207 continue;
6208
6209 /* If this section is a link-once section that will be
6210 discarded, then don't create any stubs. */
6211 if (section->output_section == NULL
6212 || section->output_section->owner != output_bfd)
6213 continue;
6214
6215 /* Get the relocs. */
6216 internal_relocs
6217 = _bfd_elf_link_read_relocs (input_bfd, section, NULL,
6218 NULL, info->keep_memory);
6219 if (internal_relocs == NULL)
6220 goto error_ret_free_local;
6221
6222 /* Now examine each relocation. */
6223 irela = internal_relocs;
6224 irelaend = irela + section->reloc_count;
6225 for (; irela < irelaend; irela++)
6226 {
6227 unsigned int r_type, r_indx;
906e58ca
NC		 6228 asection *sym_sec;
6229 bfd_vma sym_value;
6230 bfd_vma destination;
6231 struct elf32_arm_link_hash_entry *hash;
7413f23f 6232 const char *sym_name;
34e77a92 6233 unsigned char st_type;
35fc36a8 6234 enum arm_st_branch_type branch_type;
48229727 6235 bfd_boolean created_stub = FALSE;
906e58ca
NC		 6236
6237 r_type = ELF32_R_TYPE (irela->r_info);
6238 r_indx = ELF32_R_SYM (irela->r_info);
6239
6240 if (r_type >= (unsigned int) R_ARM_max)
6241 {
6242 bfd_set_error (bfd_error_bad_value);
6243 error_ret_free_internal:
6244 if (elf_section_data (section)->relocs == NULL)
6245 free (internal_relocs);
15dd01b1
TP		 6246 /* Fall through. */
6247 error_ret_free_local:
6248 if (local_syms != NULL
6249 && (symtab_hdr->contents
6250 != (unsigned char *) local_syms))
6251 free (local_syms);
6252 return FALSE;
906e58ca 6253 }
b38cadfb 6254
0855e32b
NS		 6255 hash = NULL;
6256 if (r_indx >= symtab_hdr->sh_info)
6257 hash = elf32_arm_hash_entry
6258 (elf_sym_hashes (input_bfd)
6259 [r_indx - symtab_hdr->sh_info]);
b38cadfb 6260
0855e32b
NS		 6261 /* Only look for stubs on branch instructions, or
6262 non-relaxed TLSCALL */
906e58ca 6263 if ((r_type != (unsigned int) R_ARM_CALL)
155d87d7
CL		 6264 && (r_type != (unsigned int) R_ARM_THM_CALL)
6265 && (r_type != (unsigned int) R_ARM_JUMP24)
48229727
JB		 6266 && (r_type != (unsigned int) R_ARM_THM_JUMP19)
6267 && (r_type != (unsigned int) R_ARM_THM_XPC22)
155d87d7 6268 && (r_type != (unsigned int) R_ARM_THM_JUMP24)
0855e32b
NS		 6269 && (r_type != (unsigned int) R_ARM_PLT32)
6270 && !((r_type == (unsigned int) R_ARM_TLS_CALL
6271 || r_type == (unsigned int) R_ARM_THM_TLS_CALL)
6272 && r_type == elf32_arm_tls_transition
6273 (info, r_type, &hash->root)
6274 && ((hash ? hash->tls_type
6275 : (elf32_arm_local_got_tls_type
6276 (input_bfd)[r_indx]))
6277 & GOT_TLS_GDESC) != 0))
906e58ca
NC		 6278 continue;
6279
6280 /* Now determine the call target, its name, value,
6281 section. */
6282 sym_sec = NULL;
6283 sym_value = 0;
6284 destination = 0;
7413f23f 6285 sym_name = NULL;
b38cadfb 6286
0855e32b
NS		 6287 if (r_type == (unsigned int) R_ARM_TLS_CALL
6288 || r_type == (unsigned int) R_ARM_THM_TLS_CALL)
6289 {
6290 /* A non-relaxed TLS call. The target is the
6291 plt-resident trampoline and nothing to do
6292 with the symbol. */
6293 BFD_ASSERT (htab->tls_trampoline > 0);
6294 sym_sec = htab->root.splt;
6295 sym_value = htab->tls_trampoline;
6296 hash = 0;
34e77a92 6297 st_type = STT_FUNC;
35fc36a8 6298 branch_type = ST_BRANCH_TO_ARM;
0855e32b
NS		 6299 }
6300 else if (!hash)
906e58ca
NC		 6301 {
6302 /* It's a local symbol. */
6303 Elf_Internal_Sym *sym;
906e58ca
NC		 6304
6305 if (local_syms == NULL)
6306 {
6307 local_syms
6308 = (Elf_Internal_Sym *) symtab_hdr->contents;
6309 if (local_syms == NULL)
6310 local_syms
6311 = bfd_elf_get_elf_syms (input_bfd, symtab_hdr,
6312 symtab_hdr->sh_info, 0,
6313 NULL, NULL, NULL);
6314 if (local_syms == NULL)
6315 goto error_ret_free_internal;
6316 }
6317
6318 sym = local_syms + r_indx;
f6d250ce
TS		 6319 if (sym->st_shndx == SHN_UNDEF)
6320 sym_sec = bfd_und_section_ptr;
6321 else if (sym->st_shndx == SHN_ABS)
6322 sym_sec = bfd_abs_section_ptr;
6323 else if (sym->st_shndx == SHN_COMMON)
6324 sym_sec = bfd_com_section_ptr;
6325 else
6326 sym_sec =
6327 bfd_section_from_elf_index (input_bfd, sym->st_shndx);
6328
ffcb4889
NS		 6329 if (!sym_sec)
6330 /* This is an undefined symbol. It can never
6a631e86 6331 be resolved. */
ffcb4889 6332 continue;
fe33d2fa 6333
906e58ca
NC		 6334 if (ELF_ST_TYPE (sym->st_info) != STT_SECTION)
6335 sym_value = sym->st_value;
6336 destination = (sym_value + irela->r_addend
6337 + sym_sec->output_offset
6338 + sym_sec->output_section->vma);
34e77a92 6339 st_type = ELF_ST_TYPE (sym->st_info);
39d911fc
TP		 6340 branch_type =
6341 ARM_GET_SYM_BRANCH_TYPE (sym->st_target_internal);
7413f23f
DJ		 6342 sym_name
6343 = bfd_elf_string_from_elf_section (input_bfd,
6344 symtab_hdr->sh_link,
6345 sym->st_name);
906e58ca
NC		 6346 }
6347 else
6348 {
6349 /* It's an external symbol. */
906e58ca
NC		 6350 while (hash->root.root.type == bfd_link_hash_indirect
6351 || hash->root.root.type == bfd_link_hash_warning)
6352 hash = ((struct elf32_arm_link_hash_entry *)
6353 hash->root.root.u.i.link);
6354
6355 if (hash->root.root.type == bfd_link_hash_defined
6356 || hash->root.root.type == bfd_link_hash_defweak)
6357 {
6358 sym_sec = hash->root.root.u.def.section;
6359 sym_value = hash->root.root.u.def.value;
022f8312
CL		 6360
6361 struct elf32_arm_link_hash_table *globals =
6362 elf32_arm_hash_table (info);
6363
6364 /* For a destination in a shared library,
6365 use the PLT stub as target address to
6366 decide whether a branch stub is
6367 needed. */
4dfe6ac6 6368 if (globals != NULL
362d30a1 6369 && globals->root.splt != NULL
4dfe6ac6 6370 && hash != NULL
022f8312
CL		 6371 && hash->root.plt.offset != (bfd_vma) -1)
6372 {
362d30a1 6373 sym_sec = globals->root.splt;
022f8312
CL		 6374 sym_value = hash->root.plt.offset;
6375 if (sym_sec->output_section != NULL)
6376 destination = (sym_value
6377 + sym_sec->output_offset
6378 + sym_sec->output_section->vma);
6379 }
6380 else if (sym_sec->output_section != NULL)
906e58ca
NC		 6381 destination = (sym_value + irela->r_addend
6382 + sym_sec->output_offset
6383 + sym_sec->output_section->vma);
6384 }
69c5861e
CL		 6385 else if ((hash->root.root.type == bfd_link_hash_undefined)
6386 || (hash->root.root.type == bfd_link_hash_undefweak))
6387 {
6388 /* For a shared library, use the PLT stub as
6389 target address to decide whether a long
6390 branch stub is needed.
6391 For absolute code, they cannot be handled. */
6392 struct elf32_arm_link_hash_table *globals =
6393 elf32_arm_hash_table (info);
6394
4dfe6ac6 6395 if (globals != NULL
362d30a1 6396 && globals->root.splt != NULL
4dfe6ac6 6397 && hash != NULL
69c5861e
CL		 6398 && hash->root.plt.offset != (bfd_vma) -1)
6399 {
362d30a1 6400 sym_sec = globals->root.splt;
69c5861e
CL		 6401 sym_value = hash->root.plt.offset;
6402 if (sym_sec->output_section != NULL)
6403 destination = (sym_value
6404 + sym_sec->output_offset
6405 + sym_sec->output_section->vma);
6406 }
6407 else
6408 continue;
6409 }
906e58ca
NC		 6410 else
6411 {
6412 bfd_set_error (bfd_error_bad_value);
6413 goto error_ret_free_internal;
6414 }
34e77a92 6415 st_type = hash->root.type;
39d911fc
TP		 6416 branch_type =
6417 ARM_GET_SYM_BRANCH_TYPE (hash->root.target_internal);
7413f23f 6418 sym_name = hash->root.root.root.string;
906e58ca
NC		 6419 }
6420
48229727 6421 do
7413f23f 6422 {
b715f643 6423 bfd_boolean new_stub;
0955507f 6424 struct elf32_arm_stub_hash_entry *stub_entry;
b715f643 6425
48229727
JB		 6426 /* Determine what (if any) linker stub is needed. */
6427 stub_type = arm_type_of_stub (info, section, irela,
34e77a92
RS		 6428 st_type, &branch_type,
6429 hash, destination, sym_sec,
48229727
JB		 6430 input_bfd, sym_name);
6431 if (stub_type == arm_stub_none)
6432 break;
6433
48229727
JB		 6434 /* We've either created a stub for this reloc already,
6435 or we are about to. */
0955507f 6436 stub_entry =
b715f643
TP		 6437 elf32_arm_create_stub (htab, stub_type, section, irela,
6438 sym_sec, hash,
6439 (char *) sym_name, sym_value,
6440 branch_type, &new_stub);
7413f23f 6441
0955507f 6442 created_stub = stub_entry != NULL;
b715f643
TP		 6443 if (!created_stub)
6444 goto error_ret_free_internal;
6445 else if (!new_stub)
6446 break;
99059e56 6447 else
b715f643 6448 stub_changed = TRUE;
99059e56
RM		 6449 }
6450 while (0);
6451
6452 /* Look for relocations which might trigger Cortex-A8
6453 erratum. */
6454 if (htab->fix_cortex_a8
6455 && (r_type == (unsigned int) R_ARM_THM_JUMP24
6456 || r_type == (unsigned int) R_ARM_THM_JUMP19
6457 || r_type == (unsigned int) R_ARM_THM_CALL
6458 || r_type == (unsigned int) R_ARM_THM_XPC22))
6459 {
6460 bfd_vma from = section->output_section->vma
6461 + section->output_offset
6462 + irela->r_offset;
6463
6464 if ((from & 0xfff) == 0xffe)
6465 {
6466 /* Found a candidate. Note we haven't checked the
6467 destination is within 4K here: if we do so (and
6468 don't create an entry in a8_relocs) we can't tell
6469 that a branch should have been relocated when
6470 scanning later. */
6471 if (num_a8_relocs == a8_reloc_table_size)
6472 {
6473 a8_reloc_table_size *= 2;
6474 a8_relocs = (struct a8_erratum_reloc *)
6475 bfd_realloc (a8_relocs,
6476 sizeof (struct a8_erratum_reloc)
6477 * a8_reloc_table_size);
6478 }
6479
6480 a8_relocs[num_a8_relocs].from = from;
6481 a8_relocs[num_a8_relocs].destination = destination;
6482 a8_relocs[num_a8_relocs].r_type = r_type;
6483 a8_relocs[num_a8_relocs].branch_type = branch_type;
6484 a8_relocs[num_a8_relocs].sym_name = sym_name;
6485 a8_relocs[num_a8_relocs].non_a8_stub = created_stub;
6486 a8_relocs[num_a8_relocs].hash = hash;
6487
6488 num_a8_relocs++;
6489 }
6490 }
906e58ca
NC		 6491 }
6492
99059e56
RM		 6493 /* We're done with the internal relocs, free them. */
6494 if (elf_section_data (section)->relocs == NULL)
6495 free (internal_relocs);
6496 }
48229727 6497
99059e56 6498 if (htab->fix_cortex_a8)
48229727 6499 {
99059e56
RM		 6500 /* Sort relocs which might apply to Cortex-A8 erratum. */
6501 qsort (a8_relocs, num_a8_relocs,
eb7c4339 6502 sizeof (struct a8_erratum_reloc),
99059e56 6503 &a8_reloc_compare);
48229727 6504
99059e56
RM		 6505 /* Scan for branches which might trigger Cortex-A8 erratum. */
6506 if (cortex_a8_erratum_scan (input_bfd, info, &a8_fixes,
48229727 6507 &num_a8_fixes, &a8_fix_table_size,
eb7c4339
NS		 6508 a8_relocs, num_a8_relocs,
6509 prev_num_a8_fixes, &stub_changed)
6510 != 0)
48229727 6511 goto error_ret_free_local;
5e681ec4 6512 }
7f991970
AM		 6513
6514 if (local_syms != NULL
6515 && symtab_hdr->contents != (unsigned char *) local_syms)
6516 {
6517 if (!info->keep_memory)
6518 free (local_syms);
6519 else
6520 symtab_hdr->contents = (unsigned char *) local_syms;
6521 }
5e681ec4
PB		 6522 }
6523
0955507f
TP		 6524 if (first_veneer_scan
6525 && !set_cmse_veneer_addr_from_implib (info, htab,
6526 &cmse_stub_created))
6527 ret = FALSE;
6528
eb7c4339 6529 if (prev_num_a8_fixes != num_a8_fixes)
99059e56 6530 stub_changed = TRUE;
48229727 6531
906e58ca
NC		 6532 if (!stub_changed)
6533 break;
5e681ec4 6534
906e58ca
NC		 6535 /* OK, we've added some stubs. Find out the new size of the
6536 stub sections. */
6537 for (stub_sec = htab->stub_bfd->sections;
6538 stub_sec != NULL;
6539 stub_sec = stub_sec->next)
3e6b1042
DJ		 6540 {
6541 /* Ignore non-stub sections. */
6542 if (!strstr (stub_sec->name, STUB_SUFFIX))
6543 continue;
6544
6545 stub_sec->size = 0;
6546 }
b34b2d70 6547
0955507f
TP		 6548 /* Add new SG veneers after those already in the input import
6549 library. */
6550 for (stub_type = arm_stub_none + 1; stub_type < max_stub_type;
6551 stub_type++)
6552 {
6553 bfd_vma *start_offset_p;
6554 asection **stub_sec_p;
6555
6556 start_offset_p = arm_new_stubs_start_offset_ptr (htab, stub_type);
6557 stub_sec_p = arm_dedicated_stub_input_section_ptr (htab, stub_type);
6558 if (start_offset_p == NULL)
6559 continue;
6560
6561 BFD_ASSERT (stub_sec_p != NULL);
6562 if (*stub_sec_p != NULL)
6563 (*stub_sec_p)->size = *start_offset_p;
6564 }
6565
d7c5bd02 6566 /* Compute stub section size, considering padding. */
906e58ca 6567 bfd_hash_traverse (&htab->stub_hash_table, arm_size_one_stub, htab);
d7c5bd02
TP		 6568 for (stub_type = arm_stub_none + 1; stub_type < max_stub_type;
6569 stub_type++)
6570 {
6571 int size, padding;
6572 asection **stub_sec_p;
6573
6574 padding = arm_dedicated_stub_section_padding (stub_type);
6575 stub_sec_p = arm_dedicated_stub_input_section_ptr (htab, stub_type);
6576 /* Skip if no stub input section or no stub section padding
6577 required. */
6578 if ((stub_sec_p != NULL && *stub_sec_p == NULL) || padding == 0)
6579 continue;
6580 /* Stub section padding required but no dedicated section. */
6581 BFD_ASSERT (stub_sec_p);
6582
6583 size = (*stub_sec_p)->size;
6584 size = (size + padding - 1) & ~(padding - 1);
6585 (*stub_sec_p)->size = size;
6586 }
906e58ca 6587
48229727
JB		 6588 /* Add Cortex-A8 erratum veneers to stub section sizes too. */
6589 if (htab->fix_cortex_a8)
99059e56
RM		 6590 for (i = 0; i < num_a8_fixes; i++)
6591 {
48229727 6592 stub_sec = elf32_arm_create_or_find_stub_sec (NULL,
daa4adae 6593 a8_fixes[i].section, htab, a8_fixes[i].stub_type);
48229727
JB		 6594
6595 if (stub_sec == NULL)
7f991970 6596 return FALSE;
48229727 6597
99059e56
RM		 6598 stub_sec->size
6599 += find_stub_size_and_template (a8_fixes[i].stub_type, NULL,
6600 NULL);
6601 }
48229727
JB		 6602
6603
906e58ca
NC		 6604 /* Ask the linker to do its stuff. */
6605 (*htab->layout_sections_again) ();
4ba2ef8f 6606 first_veneer_scan = FALSE;
ba93b8ac
DJ		 6607 }
6608
48229727
JB		 6609 /* Add stubs for Cortex-A8 erratum fixes now. */
6610 if (htab->fix_cortex_a8)
6611 {
6612 for (i = 0; i < num_a8_fixes; i++)
99059e56
RM		 6613 {
6614 struct elf32_arm_stub_hash_entry *stub_entry;
6615 char *stub_name = a8_fixes[i].stub_name;
6616 asection *section = a8_fixes[i].section;
6617 unsigned int section_id = a8_fixes[i].section->id;
6618 asection *link_sec = htab->stub_group[section_id].link_sec;
6619 asection *stub_sec = htab->stub_group[section_id].stub_sec;
6620 const insn_sequence *template_sequence;
6621 int template_size, size = 0;
6622
6623 stub_entry = arm_stub_hash_lookup (&htab->stub_hash_table, stub_name,
6624 TRUE, FALSE);
6625 if (stub_entry == NULL)
6626 {
dae82561 6627 _bfd_error_handler (_("%B: cannot create stub entry %s"),
4eca0228 6628 section->owner, stub_name);
99059e56
RM		 6629 return FALSE;
6630 }
6631
6632 stub_entry->stub_sec = stub_sec;
0955507f 6633 stub_entry->stub_offset = (bfd_vma) -1;
99059e56
RM		 6634 stub_entry->id_sec = link_sec;
6635 stub_entry->stub_type = a8_fixes[i].stub_type;
8d9d9490 6636 stub_entry->source_value = a8_fixes[i].offset;
99059e56 6637 stub_entry->target_section = a8_fixes[i].section;
8d9d9490 6638 stub_entry->target_value = a8_fixes[i].target_offset;
99059e56 6639 stub_entry->orig_insn = a8_fixes[i].orig_insn;
35fc36a8 6640 stub_entry->branch_type = a8_fixes[i].branch_type;
48229727 6641
99059e56
RM		 6642 size = find_stub_size_and_template (a8_fixes[i].stub_type,
6643 &template_sequence,
6644 &template_size);
48229727 6645
99059e56
RM		 6646 stub_entry->stub_size = size;
6647 stub_entry->stub_template = template_sequence;
6648 stub_entry->stub_template_size = template_size;
6649 }
48229727
JB		 6650
6651 /* Stash the Cortex-A8 erratum fix array for use later in
99059e56 6652 elf32_arm_write_section(). */
48229727
JB		 6653 htab->a8_erratum_fixes = a8_fixes;
6654 htab->num_a8_erratum_fixes = num_a8_fixes;
6655 }
6656 else
6657 {
6658 htab->a8_erratum_fixes = NULL;
6659 htab->num_a8_erratum_fixes = 0;
6660 }
0955507f 6661 return ret;
5e681ec4
PB		 6662}
6663
906e58ca
NC		 6664/* Build all the stubs associated with the current output file. The
6665 stubs are kept in a hash table attached to the main linker hash
6666 table. We also set up the .plt entries for statically linked PIC
6667 functions here. This function is called via arm_elf_finish in the
6668 linker. */
252b5132 6669
906e58ca
NC		 6670bfd_boolean
6671elf32_arm_build_stubs (struct bfd_link_info *info)
252b5132 6672{
906e58ca
NC		 6673 asection *stub_sec;
6674 struct bfd_hash_table *table;
0955507f 6675 enum elf32_arm_stub_type stub_type;
906e58ca 6676 struct elf32_arm_link_hash_table *htab;
252b5132 6677
906e58ca 6678 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 6679 if (htab == NULL)
6680 return FALSE;
252b5132 6681
906e58ca
NC		 6682 for (stub_sec = htab->stub_bfd->sections;
6683 stub_sec != NULL;
6684 stub_sec = stub_sec->next)
252b5132 6685 {
906e58ca
NC		 6686 bfd_size_type size;
6687
8029a119 6688 /* Ignore non-stub sections. */
906e58ca
NC		 6689 if (!strstr (stub_sec->name, STUB_SUFFIX))
6690 continue;
6691
d7c5bd02 6692 /* Allocate memory to hold the linker stubs. Zeroing the stub sections
0955507f
TP		 6693 must at least be done for stub section requiring padding and for SG
6694 veneers to ensure that a non secure code branching to a removed SG
6695 veneer causes an error. */
906e58ca 6696 size = stub_sec->size;
21d799b5 6697 stub_sec->contents = (unsigned char *) bfd_zalloc (htab->stub_bfd, size);
906e58ca
NC		 6698 if (stub_sec->contents == NULL && size != 0)
6699 return FALSE;
0955507f 6700
906e58ca 6701 stub_sec->size = 0;
252b5132
RH		 6702 }
6703
0955507f
TP		 6704 /* Add new SG veneers after those already in the input import library. */
6705 for (stub_type = arm_stub_none + 1; stub_type < max_stub_type; stub_type++)
6706 {
6707 bfd_vma *start_offset_p;
6708 asection **stub_sec_p;
6709
6710 start_offset_p = arm_new_stubs_start_offset_ptr (htab, stub_type);
6711 stub_sec_p = arm_dedicated_stub_input_section_ptr (htab, stub_type);
6712 if (start_offset_p == NULL)
6713 continue;
6714
6715 BFD_ASSERT (stub_sec_p != NULL);
6716 if (*stub_sec_p != NULL)
6717 (*stub_sec_p)->size = *start_offset_p;
6718 }
6719
906e58ca
NC		 6720 /* Build the stubs as directed by the stub hash table. */
6721 table = &htab->stub_hash_table;
6722 bfd_hash_traverse (table, arm_build_one_stub, info);
eb7c4339
NS		 6723 if (htab->fix_cortex_a8)
6724 {
6725 /* Place the cortex a8 stubs last. */
6726 htab->fix_cortex_a8 = -1;
6727 bfd_hash_traverse (table, arm_build_one_stub, info);
6728 }
252b5132 6729
906e58ca 6730 return TRUE;
252b5132
RH		 6731}
6732
9b485d32
NC		 6733/* Locate the Thumb encoded calling stub for NAME. */
6734
252b5132 6735static struct elf_link_hash_entry *
57e8b36a
NC		 6736find_thumb_glue (struct bfd_link_info *link_info,
6737 const char *name,
f2a9dd69 6738 char **error_message)
252b5132
RH		 6739{
6740 char *tmp_name;
6741 struct elf_link_hash_entry *hash;
6742 struct elf32_arm_link_hash_table *hash_table;
6743
6744 /* We need a pointer to the armelf specific hash table. */
6745 hash_table = elf32_arm_hash_table (link_info);
4dfe6ac6
NC		 6746 if (hash_table == NULL)
6747 return NULL;
252b5132 6748
21d799b5 6749 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen (name)
99059e56 6750 + strlen (THUMB2ARM_GLUE_ENTRY_NAME) + 1);
252b5132
RH		 6751
6752 BFD_ASSERT (tmp_name);
6753
6754 sprintf (tmp_name, THUMB2ARM_GLUE_ENTRY_NAME, name);
6755
6756 hash = elf_link_hash_lookup
b34976b6 6757 (&(hash_table)->root, tmp_name, FALSE, FALSE, TRUE);
252b5132 6758
b1657152
AM		 6759 if (hash == NULL
6760 && asprintf (error_message, _("unable to find THUMB glue '%s' for '%s'"),
6761 tmp_name, name) == -1)
6762 *error_message = (char *) bfd_errmsg (bfd_error_system_call);
252b5132
RH		 6763
6764 free (tmp_name);
6765
6766 return hash;
6767}
6768
9b485d32
NC		 6769/* Locate the ARM encoded calling stub for NAME. */
6770
252b5132 6771static struct elf_link_hash_entry *
57e8b36a
NC		 6772find_arm_glue (struct bfd_link_info *link_info,
6773 const char *name,
f2a9dd69 6774 char **error_message)
252b5132
RH		 6775{
6776 char *tmp_name;
6777 struct elf_link_hash_entry *myh;
6778 struct elf32_arm_link_hash_table *hash_table;
6779
6780 /* We need a pointer to the elfarm specific hash table. */
6781 hash_table = elf32_arm_hash_table (link_info);
4dfe6ac6
NC		 6782 if (hash_table == NULL)
6783 return NULL;
252b5132 6784
21d799b5 6785 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen (name)
99059e56 6786 + strlen (ARM2THUMB_GLUE_ENTRY_NAME) + 1);
252b5132
RH		 6787
6788 BFD_ASSERT (tmp_name);
6789
6790 sprintf (tmp_name, ARM2THUMB_GLUE_ENTRY_NAME, name);
6791
6792 myh = elf_link_hash_lookup
b34976b6 6793 (&(hash_table)->root, tmp_name, FALSE, FALSE, TRUE);
252b5132 6794
b1657152
AM		 6795 if (myh == NULL
6796 && asprintf (error_message, _("unable to find ARM glue '%s' for '%s'"),
6797 tmp_name, name) == -1)
6798 *error_message = (char *) bfd_errmsg (bfd_error_system_call);
252b5132
RH		 6799
6800 free (tmp_name);
6801
6802 return myh;
6803}
6804
8f6277f5 6805/* ARM->Thumb glue (static images):
252b5132
RH		 6806
6807 .arm
6808 __func_from_arm:
6809 ldr r12, __func_addr
6810 bx r12
6811 __func_addr:
906e58ca 6812 .word func @ behave as if you saw a ARM_32 reloc.
252b5132 6813
26079076
PB		 6814 (v5t static images)
6815 .arm
6816 __func_from_arm:
6817 ldr pc, __func_addr
6818 __func_addr:
906e58ca 6819 .word func @ behave as if you saw a ARM_32 reloc.
26079076 6820
8f6277f5
PB		 6821 (relocatable images)
6822 .arm
6823 __func_from_arm:
6824 ldr r12, __func_offset
6825 add r12, r12, pc
6826 bx r12
6827 __func_offset:
8029a119 6828 .word func - . */
8f6277f5
PB		 6829
6830#define ARM2THUMB_STATIC_GLUE_SIZE 12
252b5132
RH		 6831static const insn32 a2t1_ldr_insn = 0xe59fc000;
6832static const insn32 a2t2_bx_r12_insn = 0xe12fff1c;
6833static const insn32 a2t3_func_addr_insn = 0x00000001;
6834
26079076
PB		 6835#define ARM2THUMB_V5_STATIC_GLUE_SIZE 8
6836static const insn32 a2t1v5_ldr_insn = 0xe51ff004;
6837static const insn32 a2t2v5_func_addr_insn = 0x00000001;
6838
8f6277f5
PB		 6839#define ARM2THUMB_PIC_GLUE_SIZE 16
6840static const insn32 a2t1p_ldr_insn = 0xe59fc004;
6841static const insn32 a2t2p_add_pc_insn = 0xe08cc00f;
6842static const insn32 a2t3p_bx_r12_insn = 0xe12fff1c;
6843
9b485d32 6844/* Thumb->ARM: Thumb->(non-interworking aware) ARM
252b5132 6845
8029a119
NC		 6846 .thumb .thumb
6847 .align 2 .align 2
6848 __func_from_thumb: __func_from_thumb:
6849 bx pc push {r6, lr}
6850 nop ldr r6, __func_addr
6851 .arm mov lr, pc
6852 b func bx r6
99059e56
RM		 6853 .arm
6854 ;; back_to_thumb
6855 ldmia r13! {r6, lr}
6856 bx lr
6857 __func_addr:
6858 .word func */
252b5132
RH		 6859
6860#define THUMB2ARM_GLUE_SIZE 8
6861static const insn16 t2a1_bx_pc_insn = 0x4778;
6862static const insn16 t2a2_noop_insn = 0x46c0;
6863static const insn32 t2a3_b_insn = 0xea000000;
6864
c7b8f16e 6865#define VFP11_ERRATUM_VENEER_SIZE 8
a504d23a
LA		 6866#define STM32L4XX_ERRATUM_LDM_VENEER_SIZE 16
6867#define STM32L4XX_ERRATUM_VLDM_VENEER_SIZE 24
c7b8f16e 6868
845b51d6
PB		 6869#define ARM_BX_VENEER_SIZE 12
6870static const insn32 armbx1_tst_insn = 0xe3100001;
6871static const insn32 armbx2_moveq_insn = 0x01a0f000;
6872static const insn32 armbx3_bx_insn = 0xe12fff10;
6873
7e392df6 6874#ifndef ELFARM_NABI_C_INCLUDED
8029a119
NC		 6875static void
6876arm_allocate_glue_section_space (bfd * abfd, bfd_size_type size, const char * name)
252b5132
RH		 6877{
6878 asection * s;
8029a119 6879 bfd_byte * contents;
252b5132 6880
8029a119 6881 if (size == 0)
3e6b1042
DJ		 6882 {
6883 /* Do not include empty glue sections in the output. */
6884 if (abfd != NULL)
6885 {
3d4d4302 6886 s = bfd_get_linker_section (abfd, name);
3e6b1042
DJ		 6887 if (s != NULL)
6888 s->flags |= SEC_EXCLUDE;
6889 }
6890 return;
6891 }
252b5132 6892
8029a119 6893 BFD_ASSERT (abfd != NULL);
252b5132 6894
3d4d4302 6895 s = bfd_get_linker_section (abfd, name);
8029a119 6896 BFD_ASSERT (s != NULL);
252b5132 6897
21d799b5 6898 contents = (bfd_byte *) bfd_alloc (abfd, size);
252b5132 6899
8029a119
NC		 6900 BFD_ASSERT (s->size == size);
6901 s->contents = contents;
6902}
906e58ca 6903
8029a119
NC		 6904bfd_boolean
6905bfd_elf32_arm_allocate_interworking_sections (struct bfd_link_info * info)
6906{
6907 struct elf32_arm_link_hash_table * globals;
906e58ca 6908
8029a119
NC		 6909 globals = elf32_arm_hash_table (info);
6910 BFD_ASSERT (globals != NULL);
906e58ca 6911
8029a119
NC		 6912 arm_allocate_glue_section_space (globals->bfd_of_glue_owner,
6913 globals->arm_glue_size,
6914 ARM2THUMB_GLUE_SECTION_NAME);
906e58ca 6915
8029a119
NC		 6916 arm_allocate_glue_section_space (globals->bfd_of_glue_owner,
6917 globals->thumb_glue_size,
6918 THUMB2ARM_GLUE_SECTION_NAME);
252b5132 6919
8029a119
NC		 6920 arm_allocate_glue_section_space (globals->bfd_of_glue_owner,
6921 globals->vfp11_erratum_glue_size,
6922 VFP11_ERRATUM_VENEER_SECTION_NAME);
845b51d6 6923
a504d23a
LA		 6924 arm_allocate_glue_section_space (globals->bfd_of_glue_owner,
6925 globals->stm32l4xx_erratum_glue_size,
6926 STM32L4XX_ERRATUM_VENEER_SECTION_NAME);
6927
8029a119
NC		 6928 arm_allocate_glue_section_space (globals->bfd_of_glue_owner,
6929 globals->bx_glue_size,
845b51d6
PB		 6930 ARM_BX_GLUE_SECTION_NAME);
6931
b34976b6 6932 return TRUE;
252b5132
RH		 6933}
6934
a4fd1a8e 6935/* Allocate space and symbols for calling a Thumb function from Arm mode.
906e58ca
NC		 6936 returns the symbol identifying the stub. */
6937
a4fd1a8e 6938static struct elf_link_hash_entry *
57e8b36a
NC		 6939record_arm_to_thumb_glue (struct bfd_link_info * link_info,
6940 struct elf_link_hash_entry * h)
252b5132
RH		 6941{
6942 const char * name = h->root.root.string;
63b0f745 6943 asection * s;
252b5132
RH		 6944 char * tmp_name;
6945 struct elf_link_hash_entry * myh;
14a793b2 6946 struct bfd_link_hash_entry * bh;
252b5132 6947 struct elf32_arm_link_hash_table * globals;
dc810e39 6948 bfd_vma val;
2f475487 6949 bfd_size_type size;
252b5132
RH		 6950
6951 globals = elf32_arm_hash_table (link_info);
252b5132
RH		 6952 BFD_ASSERT (globals != NULL);
6953 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
6954
3d4d4302 6955 s = bfd_get_linker_section
252b5132
RH		 6956 (globals->bfd_of_glue_owner, ARM2THUMB_GLUE_SECTION_NAME);
6957
252b5132
RH		 6958 BFD_ASSERT (s != NULL);
6959
21d799b5 6960 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen (name)
99059e56 6961 + strlen (ARM2THUMB_GLUE_ENTRY_NAME) + 1);
252b5132
RH		 6962
6963 BFD_ASSERT (tmp_name);
6964
6965 sprintf (tmp_name, ARM2THUMB_GLUE_ENTRY_NAME, name);
6966
6967 myh = elf_link_hash_lookup
b34976b6 6968 (&(globals)->root, tmp_name, FALSE, FALSE, TRUE);
252b5132
RH		 6969
6970 if (myh != NULL)
6971 {
9b485d32 6972 /* We've already seen this guy. */
252b5132 6973 free (tmp_name);
a4fd1a8e 6974 return myh;
252b5132
RH		 6975 }
6976
57e8b36a
NC		 6977 /* The only trick here is using hash_table->arm_glue_size as the value.
6978 Even though the section isn't allocated yet, this is where we will be
3dccd7b7
DJ		 6979 putting it. The +1 on the value marks that the stub has not been
6980 output yet - not that it is a Thumb function. */
14a793b2 6981 bh = NULL;
dc810e39
AM		 6982 val = globals->arm_glue_size + 1;
6983 _bfd_generic_link_add_one_symbol (link_info, globals->bfd_of_glue_owner,
6984 tmp_name, BSF_GLOBAL, s, val,
b34976b6 6985 NULL, TRUE, FALSE, &bh);
252b5132 6986
b7693d02
DJ		 6987 myh = (struct elf_link_hash_entry *) bh;
6988 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
6989 myh->forced_local = 1;
6990
252b5132
RH		 6991 free (tmp_name);
6992
0e1862bb
L		 6993 if (bfd_link_pic (link_info)
6994 || globals->root.is_relocatable_executable
27e55c4d 6995 || globals->pic_veneer)
2f475487 6996 size = ARM2THUMB_PIC_GLUE_SIZE;
26079076
PB		 6997 else if (globals->use_blx)
6998 size = ARM2THUMB_V5_STATIC_GLUE_SIZE;
8f6277f5 6999 else
2f475487
AM		 7000 size = ARM2THUMB_STATIC_GLUE_SIZE;
7001
7002 s->size += size;
7003 globals->arm_glue_size += size;
252b5132 7004
a4fd1a8e 7005 return myh;
252b5132
RH		 7006}
7007
845b51d6
PB		 7008/* Allocate space for ARMv4 BX veneers. */
7009
7010static void
7011record_arm_bx_glue (struct bfd_link_info * link_info, int reg)
7012{
7013 asection * s;
7014 struct elf32_arm_link_hash_table *globals;
7015 char *tmp_name;
7016 struct elf_link_hash_entry *myh;
7017 struct bfd_link_hash_entry *bh;
7018 bfd_vma val;
7019
7020 /* BX PC does not need a veneer. */
7021 if (reg == 15)
7022 return;
7023
7024 globals = elf32_arm_hash_table (link_info);
845b51d6
PB		 7025 BFD_ASSERT (globals != NULL);
7026 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
7027
7028 /* Check if this veneer has already been allocated. */
7029 if (globals->bx_glue_offset[reg])
7030 return;
7031
3d4d4302 7032 s = bfd_get_linker_section
845b51d6
PB		 7033 (globals->bfd_of_glue_owner, ARM_BX_GLUE_SECTION_NAME);
7034
7035 BFD_ASSERT (s != NULL);
7036
7037 /* Add symbol for veneer. */
21d799b5
NC		 7038 tmp_name = (char *)
7039 bfd_malloc ((bfd_size_type) strlen (ARM_BX_GLUE_ENTRY_NAME) + 1);
906e58ca 7040
845b51d6 7041 BFD_ASSERT (tmp_name);
906e58ca 7042
845b51d6 7043 sprintf (tmp_name, ARM_BX_GLUE_ENTRY_NAME, reg);
906e58ca 7044
845b51d6
PB		 7045 myh = elf_link_hash_lookup
7046 (&(globals)->root, tmp_name, FALSE, FALSE, FALSE);
906e58ca 7047
845b51d6 7048 BFD_ASSERT (myh == NULL);
906e58ca 7049
845b51d6
PB		 7050 bh = NULL;
7051 val = globals->bx_glue_size;
7052 _bfd_generic_link_add_one_symbol (link_info, globals->bfd_of_glue_owner,
99059e56
RM		 7053 tmp_name, BSF_FUNCTION | BSF_LOCAL, s, val,
7054 NULL, TRUE, FALSE, &bh);
845b51d6
PB		 7055
7056 myh = (struct elf_link_hash_entry *) bh;
7057 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
7058 myh->forced_local = 1;
7059
7060 s->size += ARM_BX_VENEER_SIZE;
7061 globals->bx_glue_offset[reg] = globals->bx_glue_size | 2;
7062 globals->bx_glue_size += ARM_BX_VENEER_SIZE;
7063}
7064
7065
c7b8f16e
JB		 7066/* Add an entry to the code/data map for section SEC. */
7067
7068static void
7069elf32_arm_section_map_add (asection *sec, char type, bfd_vma vma)
7070{
7071 struct _arm_elf_section_data *sec_data = elf32_arm_section_data (sec);
7072 unsigned int newidx;
906e58ca 7073
c7b8f16e
JB		 7074 if (sec_data->map == NULL)
7075 {
21d799b5 7076 sec_data->map = (elf32_arm_section_map *)
99059e56 7077 bfd_malloc (sizeof (elf32_arm_section_map));
c7b8f16e
JB		 7078 sec_data->mapcount = 0;
7079 sec_data->mapsize = 1;
7080 }
906e58ca 7081
c7b8f16e 7082 newidx = sec_data->mapcount++;
906e58ca 7083
c7b8f16e
JB		 7084 if (sec_data->mapcount > sec_data->mapsize)
7085 {
7086 sec_data->mapsize *= 2;
21d799b5 7087 sec_data->map = (elf32_arm_section_map *)
99059e56
RM		 7088 bfd_realloc_or_free (sec_data->map, sec_data->mapsize
7089 * sizeof (elf32_arm_section_map));
515ef31d
NC		 7090 }
7091
7092 if (sec_data->map)
7093 {
7094 sec_data->map[newidx].vma = vma;
7095 sec_data->map[newidx].type = type;
c7b8f16e 7096 }
c7b8f16e
JB		 7097}
7098
7099
7100/* Record information about a VFP11 denorm-erratum veneer. Only ARM-mode
7101 veneers are handled for now. */
7102
7103static bfd_vma
7104record_vfp11_erratum_veneer (struct bfd_link_info *link_info,
99059e56
RM		 7105 elf32_vfp11_erratum_list *branch,
7106 bfd *branch_bfd,
7107 asection *branch_sec,
7108 unsigned int offset)
c7b8f16e
JB		 7109{
7110 asection *s;
7111 struct elf32_arm_link_hash_table *hash_table;
7112 char *tmp_name;
7113 struct elf_link_hash_entry *myh;
7114 struct bfd_link_hash_entry *bh;
7115 bfd_vma val;
7116 struct _arm_elf_section_data *sec_data;
c7b8f16e 7117 elf32_vfp11_erratum_list *newerr;
906e58ca 7118
c7b8f16e 7119 hash_table = elf32_arm_hash_table (link_info);
c7b8f16e
JB		 7120 BFD_ASSERT (hash_table != NULL);
7121 BFD_ASSERT (hash_table->bfd_of_glue_owner != NULL);
906e58ca 7122
3d4d4302 7123 s = bfd_get_linker_section
c7b8f16e 7124 (hash_table->bfd_of_glue_owner, VFP11_ERRATUM_VENEER_SECTION_NAME);
906e58ca 7125
c7b8f16e 7126 sec_data = elf32_arm_section_data (s);
906e58ca 7127
c7b8f16e 7128 BFD_ASSERT (s != NULL);
906e58ca 7129
21d799b5 7130 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen
99059e56 7131 (VFP11_ERRATUM_VENEER_ENTRY_NAME) + 10);
906e58ca 7132
c7b8f16e 7133 BFD_ASSERT (tmp_name);
906e58ca 7134
c7b8f16e
JB		 7135 sprintf (tmp_name, VFP11_ERRATUM_VENEER_ENTRY_NAME,
7136 hash_table->num_vfp11_fixes);
906e58ca 7137
c7b8f16e
JB		 7138 myh = elf_link_hash_lookup
7139 (&(hash_table)->root, tmp_name, FALSE, FALSE, FALSE);
906e58ca 7140
c7b8f16e 7141 BFD_ASSERT (myh == NULL);
906e58ca 7142
c7b8f16e
JB		 7143 bh = NULL;
7144 val = hash_table->vfp11_erratum_glue_size;
7145 _bfd_generic_link_add_one_symbol (link_info, hash_table->bfd_of_glue_owner,
99059e56
RM		 7146 tmp_name, BSF_FUNCTION | BSF_LOCAL, s, val,
7147 NULL, TRUE, FALSE, &bh);
c7b8f16e
JB		 7148
7149 myh = (struct elf_link_hash_entry *) bh;
7150 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
7151 myh->forced_local = 1;
7152
7153 /* Link veneer back to calling location. */
c7e2358a 7154 sec_data->erratumcount += 1;
21d799b5
NC		 7155 newerr = (elf32_vfp11_erratum_list *)
7156 bfd_zmalloc (sizeof (elf32_vfp11_erratum_list));
906e58ca 7157
c7b8f16e
JB		 7158 newerr->type = VFP11_ERRATUM_ARM_VENEER;
7159 newerr->vma = -1;
7160 newerr->u.v.branch = branch;
7161 newerr->u.v.id = hash_table->num_vfp11_fixes;
7162 branch->u.b.veneer = newerr;
7163
7164 newerr->next = sec_data->erratumlist;
7165 sec_data->erratumlist = newerr;
7166
7167 /* A symbol for the return from the veneer. */
7168 sprintf (tmp_name, VFP11_ERRATUM_VENEER_ENTRY_NAME "_r",
7169 hash_table->num_vfp11_fixes);
7170
7171 myh = elf_link_hash_lookup
7172 (&(hash_table)->root, tmp_name, FALSE, FALSE, FALSE);
906e58ca 7173
c7b8f16e
JB		 7174 if (myh != NULL)
7175 abort ();
7176
7177 bh = NULL;
7178 val = offset + 4;
7179 _bfd_generic_link_add_one_symbol (link_info, branch_bfd, tmp_name, BSF_LOCAL,
7180 branch_sec, val, NULL, TRUE, FALSE, &bh);
906e58ca 7181
c7b8f16e
JB		 7182 myh = (struct elf_link_hash_entry *) bh;
7183 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
7184 myh->forced_local = 1;
7185
7186 free (tmp_name);
906e58ca 7187
c7b8f16e
JB		 7188 /* Generate a mapping symbol for the veneer section, and explicitly add an
7189 entry for that symbol to the code/data map for the section. */
7190 if (hash_table->vfp11_erratum_glue_size == 0)
7191 {
7192 bh = NULL;
7193 /* FIXME: Creates an ARM symbol. Thumb mode will need attention if it
99059e56 7194 ever requires this erratum fix. */
c7b8f16e
JB		 7195 _bfd_generic_link_add_one_symbol (link_info,
7196 hash_table->bfd_of_glue_owner, "$a",
7197 BSF_LOCAL, s, 0, NULL,
99059e56 7198 TRUE, FALSE, &bh);
c7b8f16e
JB		 7199
7200 myh = (struct elf_link_hash_entry *) bh;
7201 myh->type = ELF_ST_INFO (STB_LOCAL, STT_NOTYPE);
7202 myh->forced_local = 1;
906e58ca 7203
c7b8f16e 7204 /* The elf32_arm_init_maps function only cares about symbols from input
99059e56
RM		 7205 BFDs. We must make a note of this generated mapping symbol
7206 ourselves so that code byteswapping works properly in
7207 elf32_arm_write_section. */
c7b8f16e
JB		 7208 elf32_arm_section_map_add (s, 'a', 0);
7209 }
906e58ca 7210
c7b8f16e
JB		 7211 s->size += VFP11_ERRATUM_VENEER_SIZE;
7212 hash_table->vfp11_erratum_glue_size += VFP11_ERRATUM_VENEER_SIZE;
7213 hash_table->num_vfp11_fixes++;
906e58ca 7214
c7b8f16e
JB		 7215 /* The offset of the veneer. */
7216 return val;
7217}
7218
a504d23a
LA		 7219/* Record information about a STM32L4XX STM erratum veneer. Only THUMB-mode
7220 veneers need to be handled because used only in Cortex-M. */
7221
7222static bfd_vma
7223record_stm32l4xx_erratum_veneer (struct bfd_link_info *link_info,
7224 elf32_stm32l4xx_erratum_list *branch,
7225 bfd *branch_bfd,
7226 asection *branch_sec,
7227 unsigned int offset,
7228 bfd_size_type veneer_size)
7229{
7230 asection *s;
7231 struct elf32_arm_link_hash_table *hash_table;
7232 char *tmp_name;
7233 struct elf_link_hash_entry *myh;
7234 struct bfd_link_hash_entry *bh;
7235 bfd_vma val;
7236 struct _arm_elf_section_data *sec_data;
7237 elf32_stm32l4xx_erratum_list *newerr;
7238
7239 hash_table = elf32_arm_hash_table (link_info);
7240 BFD_ASSERT (hash_table != NULL);
7241 BFD_ASSERT (hash_table->bfd_of_glue_owner != NULL);
7242
7243 s = bfd_get_linker_section
7244 (hash_table->bfd_of_glue_owner, STM32L4XX_ERRATUM_VENEER_SECTION_NAME);
7245
7246 BFD_ASSERT (s != NULL);
7247
7248 sec_data = elf32_arm_section_data (s);
7249
7250 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen
7251 (STM32L4XX_ERRATUM_VENEER_ENTRY_NAME) + 10);
7252
7253 BFD_ASSERT (tmp_name);
7254
7255 sprintf (tmp_name, STM32L4XX_ERRATUM_VENEER_ENTRY_NAME,
7256 hash_table->num_stm32l4xx_fixes);
7257
7258 myh = elf_link_hash_lookup
7259 (&(hash_table)->root, tmp_name, FALSE, FALSE, FALSE);
7260
7261 BFD_ASSERT (myh == NULL);
7262
7263 bh = NULL;
7264 val = hash_table->stm32l4xx_erratum_glue_size;
7265 _bfd_generic_link_add_one_symbol (link_info, hash_table->bfd_of_glue_owner,
7266 tmp_name, BSF_FUNCTION | BSF_LOCAL, s, val,
7267 NULL, TRUE, FALSE, &bh);
7268
7269 myh = (struct elf_link_hash_entry *) bh;
7270 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
7271 myh->forced_local = 1;
7272
7273 /* Link veneer back to calling location. */
7274 sec_data->stm32l4xx_erratumcount += 1;
7275 newerr = (elf32_stm32l4xx_erratum_list *)
7276 bfd_zmalloc (sizeof (elf32_stm32l4xx_erratum_list));
7277
7278 newerr->type = STM32L4XX_ERRATUM_VENEER;
7279 newerr->vma = -1;
7280 newerr->u.v.branch = branch;
7281 newerr->u.v.id = hash_table->num_stm32l4xx_fixes;
7282 branch->u.b.veneer = newerr;
7283
7284 newerr->next = sec_data->stm32l4xx_erratumlist;
7285 sec_data->stm32l4xx_erratumlist = newerr;
7286
7287 /* A symbol for the return from the veneer. */
7288 sprintf (tmp_name, STM32L4XX_ERRATUM_VENEER_ENTRY_NAME "_r",
7289 hash_table->num_stm32l4xx_fixes);
7290
7291 myh = elf_link_hash_lookup
7292 (&(hash_table)->root, tmp_name, FALSE, FALSE, FALSE);
7293
7294 if (myh != NULL)
7295 abort ();
7296
7297 bh = NULL;
7298 val = offset + 4;
7299 _bfd_generic_link_add_one_symbol (link_info, branch_bfd, tmp_name, BSF_LOCAL,
7300 branch_sec, val, NULL, TRUE, FALSE, &bh);
7301
7302 myh = (struct elf_link_hash_entry *) bh;
7303 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
7304 myh->forced_local = 1;
7305
7306 free (tmp_name);
7307
7308 /* Generate a mapping symbol for the veneer section, and explicitly add an
7309 entry for that symbol to the code/data map for the section. */
7310 if (hash_table->stm32l4xx_erratum_glue_size == 0)
7311 {
7312 bh = NULL;
7313 /* Creates a THUMB symbol since there is no other choice. */
7314 _bfd_generic_link_add_one_symbol (link_info,
7315 hash_table->bfd_of_glue_owner, "$t",
7316 BSF_LOCAL, s, 0, NULL,
7317 TRUE, FALSE, &bh);
7318
7319 myh = (struct elf_link_hash_entry *) bh;
7320 myh->type = ELF_ST_INFO (STB_LOCAL, STT_NOTYPE);
7321 myh->forced_local = 1;
7322
7323 /* The elf32_arm_init_maps function only cares about symbols from input
7324 BFDs. We must make a note of this generated mapping symbol
7325 ourselves so that code byteswapping works properly in
7326 elf32_arm_write_section. */
7327 elf32_arm_section_map_add (s, 't', 0);
7328 }
7329
7330 s->size += veneer_size;
7331 hash_table->stm32l4xx_erratum_glue_size += veneer_size;
7332 hash_table->num_stm32l4xx_fixes++;
7333
7334 /* The offset of the veneer. */
7335 return val;
7336}
7337
8029a119 7338#define ARM_GLUE_SECTION_FLAGS \
3e6b1042
DJ		 7339 (SEC_ALLOC | SEC_LOAD | SEC_HAS_CONTENTS | SEC_IN_MEMORY | SEC_CODE \
7340 | SEC_READONLY | SEC_LINKER_CREATED)
8029a119
NC		 7341
7342/* Create a fake section for use by the ARM backend of the linker. */
7343
7344static bfd_boolean
7345arm_make_glue_section (bfd * abfd, const char * name)
7346{
7347 asection * sec;
7348
3d4d4302 7349 sec = bfd_get_linker_section (abfd, name);
8029a119
NC		 7350 if (sec != NULL)
7351 /* Already made. */
7352 return TRUE;
7353
3d4d4302 7354 sec = bfd_make_section_anyway_with_flags (abfd, name, ARM_GLUE_SECTION_FLAGS);
8029a119
NC		 7355
7356 if (sec == NULL
7357 || !bfd_set_section_alignment (abfd, sec, 2))
7358 return FALSE;
7359
7360 /* Set the gc mark to prevent the section from being removed by garbage
7361 collection, despite the fact that no relocs refer to this section. */
7362 sec->gc_mark = 1;
7363
7364 return TRUE;
7365}
7366
1db37fe6
YG		 7367/* Set size of .plt entries. This function is called from the
7368 linker scripts in ld/emultempl/{armelf}.em. */
7369
7370void
7371bfd_elf32_arm_use_long_plt (void)
7372{
7373 elf32_arm_use_long_plt_entry = TRUE;
7374}
7375
8afb0e02
NC		 7376/* Add the glue sections to ABFD. This function is called from the
7377 linker scripts in ld/emultempl/{armelf}.em. */
9b485d32 7378
b34976b6 7379bfd_boolean
57e8b36a
NC		 7380bfd_elf32_arm_add_glue_sections_to_bfd (bfd *abfd,
7381 struct bfd_link_info *info)
252b5132 7382{
a504d23a
LA		 7383 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (info);
7384 bfd_boolean dostm32l4xx = globals
7385 && globals->stm32l4xx_fix != BFD_ARM_STM32L4XX_FIX_NONE;
7386 bfd_boolean addglue;
7387
8afb0e02
NC		 7388 /* If we are only performing a partial
7389 link do not bother adding the glue. */
0e1862bb 7390 if (bfd_link_relocatable (info))
b34976b6 7391 return TRUE;
252b5132 7392
a504d23a 7393 addglue = arm_make_glue_section (abfd, ARM2THUMB_GLUE_SECTION_NAME)
8029a119
NC		 7394 && arm_make_glue_section (abfd, THUMB2ARM_GLUE_SECTION_NAME)
7395 && arm_make_glue_section (abfd, VFP11_ERRATUM_VENEER_SECTION_NAME)
7396 && arm_make_glue_section (abfd, ARM_BX_GLUE_SECTION_NAME);
a504d23a
LA		 7397
7398 if (!dostm32l4xx)
7399 return addglue;
7400
7401 return addglue
7402 && arm_make_glue_section (abfd, STM32L4XX_ERRATUM_VENEER_SECTION_NAME);
8afb0e02
NC		 7403}
7404
daa4adae
TP		 7405/* Mark output sections of veneers needing a dedicated one with SEC_KEEP. This
7406 ensures they are not marked for deletion by
7407 strip_excluded_output_sections () when veneers are going to be created
7408 later. Not doing so would trigger assert on empty section size in
7409 lang_size_sections_1 (). */
7410
7411void
7412bfd_elf32_arm_keep_private_stub_output_sections (struct bfd_link_info *info)
7413{
7414 enum elf32_arm_stub_type stub_type;
7415
7416 /* If we are only performing a partial
7417 link do not bother adding the glue. */
7418 if (bfd_link_relocatable (info))
7419 return;
7420
7421 for (stub_type = arm_stub_none + 1; stub_type < max_stub_type; stub_type++)
7422 {
7423 asection *out_sec;
7424 const char *out_sec_name;
7425
7426 if (!arm_dedicated_stub_output_section_required (stub_type))
7427 continue;
7428
7429 out_sec_name = arm_dedicated_stub_output_section_name (stub_type);
7430 out_sec = bfd_get_section_by_name (info->output_bfd, out_sec_name);
7431 if (out_sec != NULL)
7432 out_sec->flags |= SEC_KEEP;
7433 }
7434}
7435
8afb0e02
NC		 7436/* Select a BFD to be used to hold the sections used by the glue code.
7437 This function is called from the linker scripts in ld/emultempl/
8029a119 7438 {armelf/pe}.em. */
8afb0e02 7439
b34976b6 7440bfd_boolean
57e8b36a 7441bfd_elf32_arm_get_bfd_for_interworking (bfd *abfd, struct bfd_link_info *info)
8afb0e02
NC		 7442{
7443 struct elf32_arm_link_hash_table *globals;
7444
7445 /* If we are only performing a partial link
7446 do not bother getting a bfd to hold the glue. */
0e1862bb 7447 if (bfd_link_relocatable (info))
b34976b6 7448 return TRUE;
8afb0e02 7449
b7693d02
DJ		 7450 /* Make sure we don't attach the glue sections to a dynamic object. */
7451 BFD_ASSERT (!(abfd->flags & DYNAMIC));
7452
8afb0e02 7453 globals = elf32_arm_hash_table (info);
8afb0e02
NC		 7454 BFD_ASSERT (globals != NULL);
7455
7456 if (globals->bfd_of_glue_owner != NULL)
b34976b6 7457 return TRUE;
8afb0e02 7458
252b5132
RH		 7459 /* Save the bfd for later use. */
7460 globals->bfd_of_glue_owner = abfd;
cedb70c5 7461
b34976b6 7462 return TRUE;
252b5132
RH		 7463}
7464
906e58ca
NC		 7465static void
7466check_use_blx (struct elf32_arm_link_hash_table *globals)
39b41c9c 7467{
2de70689
MGD		 7468 int cpu_arch;
7469
b38cadfb 7470 cpu_arch = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC,
2de70689
MGD		 7471 Tag_CPU_arch);
7472
7473 if (globals->fix_arm1176)
7474 {
7475 if (cpu_arch == TAG_CPU_ARCH_V6T2 || cpu_arch > TAG_CPU_ARCH_V6K)
7476 globals->use_blx = 1;
7477 }
7478 else
7479 {
7480 if (cpu_arch > TAG_CPU_ARCH_V4T)
7481 globals->use_blx = 1;
7482 }
39b41c9c
PB		 7483}
7484
b34976b6 7485bfd_boolean
57e8b36a 7486bfd_elf32_arm_process_before_allocation (bfd *abfd,
d504ffc8 7487 struct bfd_link_info *link_info)
252b5132
RH		 7488{
7489 Elf_Internal_Shdr *symtab_hdr;
6cdc0ccc 7490 Elf_Internal_Rela *internal_relocs = NULL;
252b5132
RH		 7491 Elf_Internal_Rela *irel, *irelend;
7492 bfd_byte *contents = NULL;
252b5132
RH		 7493
7494 asection *sec;
7495 struct elf32_arm_link_hash_table *globals;
7496
7497 /* If we are only performing a partial link do not bother
7498 to construct any glue. */
0e1862bb 7499 if (bfd_link_relocatable (link_info))
b34976b6 7500 return TRUE;
252b5132 7501
39ce1a6a
NC		 7502 /* Here we have a bfd that is to be included on the link. We have a
7503 hook to do reloc rummaging, before section sizes are nailed down. */
252b5132 7504 globals = elf32_arm_hash_table (link_info);
252b5132 7505 BFD_ASSERT (globals != NULL);
39ce1a6a
NC		 7506
7507 check_use_blx (globals);
252b5132 7508
d504ffc8 7509 if (globals->byteswap_code && !bfd_big_endian (abfd))
e489d0ae 7510 {
d003868e
AM		 7511 _bfd_error_handler (_("%B: BE8 images only valid in big-endian mode."),
7512 abfd);
e489d0ae
PB		 7513 return FALSE;
7514 }
f21f3fe0 7515
39ce1a6a
NC		 7516 /* PR 5398: If we have not decided to include any loadable sections in
7517 the output then we will not have a glue owner bfd. This is OK, it
7518 just means that there is nothing else for us to do here. */
7519 if (globals->bfd_of_glue_owner == NULL)
7520 return TRUE;
7521
252b5132
RH		 7522 /* Rummage around all the relocs and map the glue vectors. */
7523 sec = abfd->sections;
7524
7525 if (sec == NULL)
b34976b6 7526 return TRUE;
252b5132
RH		 7527
7528 for (; sec != NULL; sec = sec->next)
7529 {
7530 if (sec->reloc_count == 0)
7531 continue;
7532
2f475487
AM		 7533 if ((sec->flags & SEC_EXCLUDE) != 0)
7534 continue;
7535
0ffa91dd 7536 symtab_hdr = & elf_symtab_hdr (abfd);
252b5132 7537
9b485d32 7538 /* Load the relocs. */
6cdc0ccc 7539 internal_relocs
906e58ca 7540 = _bfd_elf_link_read_relocs (abfd, sec, NULL, NULL, FALSE);
252b5132 7541
6cdc0ccc
AM		 7542 if (internal_relocs == NULL)
7543 goto error_return;
252b5132 7544
6cdc0ccc
AM		 7545 irelend = internal_relocs + sec->reloc_count;
7546 for (irel = internal_relocs; irel < irelend; irel++)
252b5132
RH		 7547 {
7548 long r_type;
7549 unsigned long r_index;
252b5132
RH		 7550
7551 struct elf_link_hash_entry *h;
7552
7553 r_type = ELF32_R_TYPE (irel->r_info);
7554 r_index = ELF32_R_SYM (irel->r_info);
7555
9b485d32 7556 /* These are the only relocation types we care about. */
ba96a88f 7557 if ( r_type != R_ARM_PC24
845b51d6 7558 && (r_type != R_ARM_V4BX || globals->fix_v4bx < 2))
252b5132
RH		 7559 continue;
7560
7561 /* Get the section contents if we haven't done so already. */
7562 if (contents == NULL)
7563 {
7564 /* Get cached copy if it exists. */
7565 if (elf_section_data (sec)->this_hdr.contents != NULL)
7566 contents = elf_section_data (sec)->this_hdr.contents;
7567 else
7568 {
7569 /* Go get them off disk. */
57e8b36a 7570 if (! bfd_malloc_and_get_section (abfd, sec, &contents))
252b5132
RH		 7571 goto error_return;
7572 }
7573 }
7574
845b51d6
PB		 7575 if (r_type == R_ARM_V4BX)
7576 {
7577 int reg;
7578
7579 reg = bfd_get_32 (abfd, contents + irel->r_offset) & 0xf;
7580 record_arm_bx_glue (link_info, reg);
7581 continue;
7582 }
7583
a7c10850 7584 /* If the relocation is not against a symbol it cannot concern us. */
252b5132
RH		 7585 h = NULL;
7586
9b485d32 7587 /* We don't care about local symbols. */
252b5132
RH		 7588 if (r_index < symtab_hdr->sh_info)
7589 continue;
7590
9b485d32 7591 /* This is an external symbol. */
252b5132
RH		 7592 r_index -= symtab_hdr->sh_info;
7593 h = (struct elf_link_hash_entry *)
7594 elf_sym_hashes (abfd)[r_index];
7595
7596 /* If the relocation is against a static symbol it must be within
7597 the current section and so cannot be a cross ARM/Thumb relocation. */
7598 if (h == NULL)
7599 continue;
7600
d504ffc8
DJ		 7601 /* If the call will go through a PLT entry then we do not need
7602 glue. */
362d30a1 7603 if (globals->root.splt != NULL && h->plt.offset != (bfd_vma) -1)
b7693d02
DJ		 7604 continue;
7605
252b5132
RH		 7606 switch (r_type)
7607 {
7608 case R_ARM_PC24:
7609 /* This one is a call from arm code. We need to look up
99059e56
RM		 7610 the target of the call. If it is a thumb target, we
7611 insert glue. */
39d911fc
TP		 7612 if (ARM_GET_SYM_BRANCH_TYPE (h->target_internal)
7613 == ST_BRANCH_TO_THUMB)
252b5132
RH		 7614 record_arm_to_thumb_glue (link_info, h);
7615 break;
7616
252b5132 7617 default:
c6596c5e 7618 abort ();
252b5132
RH		 7619 }
7620 }
6cdc0ccc
AM		 7621
7622 if (contents != NULL
7623 && elf_section_data (sec)->this_hdr.contents != contents)
7624 free (contents);
7625 contents = NULL;
7626
7627 if (internal_relocs != NULL
7628 && elf_section_data (sec)->relocs != internal_relocs)
7629 free (internal_relocs);
7630 internal_relocs = NULL;
252b5132
RH		 7631 }
7632
b34976b6 7633 return TRUE;
9a5aca8c 7634
252b5132 7635error_return:
6cdc0ccc
AM		 7636 if (contents != NULL
7637 && elf_section_data (sec)->this_hdr.contents != contents)
7638 free (contents);
7639 if (internal_relocs != NULL
7640 && elf_section_data (sec)->relocs != internal_relocs)
7641 free (internal_relocs);
9a5aca8c 7642
b34976b6 7643 return FALSE;
252b5132 7644}
7e392df6 7645#endif
252b5132 7646
eb043451 7647
c7b8f16e
JB		 7648/* Initialise maps of ARM/Thumb/data for input BFDs. */
7649
7650void
7651bfd_elf32_arm_init_maps (bfd *abfd)
7652{
7653 Elf_Internal_Sym *isymbuf;
7654 Elf_Internal_Shdr *hdr;
7655 unsigned int i, localsyms;
7656
af1f4419
NC		 7657 /* PR 7093: Make sure that we are dealing with an arm elf binary. */
7658 if (! is_arm_elf (abfd))
7659 return;
7660
c7b8f16e
JB		 7661 if ((abfd->flags & DYNAMIC) != 0)
7662 return;
7663
0ffa91dd 7664 hdr = & elf_symtab_hdr (abfd);
c7b8f16e
JB		 7665 localsyms = hdr->sh_info;
7666
7667 /* Obtain a buffer full of symbols for this BFD. The hdr->sh_info field
7668 should contain the number of local symbols, which should come before any
7669 global symbols. Mapping symbols are always local. */
7670 isymbuf = bfd_elf_get_elf_syms (abfd, hdr, localsyms, 0, NULL, NULL,
7671 NULL);
7672
7673 /* No internal symbols read? Skip this BFD. */
7674 if (isymbuf == NULL)
7675 return;
7676
7677 for (i = 0; i < localsyms; i++)
7678 {
7679 Elf_Internal_Sym *isym = &isymbuf[i];
7680 asection *sec = bfd_section_from_elf_index (abfd, isym->st_shndx);
7681 const char *name;
906e58ca 7682
c7b8f16e 7683 if (sec != NULL
99059e56
RM		 7684 && ELF_ST_BIND (isym->st_info) == STB_LOCAL)
7685 {
7686 name = bfd_elf_string_from_elf_section (abfd,
7687 hdr->sh_link, isym->st_name);
906e58ca 7688
99059e56 7689 if (bfd_is_arm_special_symbol_name (name,
c7b8f16e 7690 BFD_ARM_SPECIAL_SYM_TYPE_MAP))
99059e56
RM		 7691 elf32_arm_section_map_add (sec, name[1], isym->st_value);
7692 }
c7b8f16e
JB		 7693 }
7694}
7695
7696
48229727
JB		 7697/* Auto-select enabling of Cortex-A8 erratum fix if the user didn't explicitly
7698 say what they wanted. */
7699
7700void
7701bfd_elf32_arm_set_cortex_a8_fix (bfd *obfd, struct bfd_link_info *link_info)
7702{
7703 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (link_info);
7704 obj_attribute *out_attr = elf_known_obj_attributes_proc (obfd);
7705
4dfe6ac6
NC		 7706 if (globals == NULL)
7707 return;
7708
48229727
JB		 7709 if (globals->fix_cortex_a8 == -1)
7710 {
7711 /* Turn on Cortex-A8 erratum workaround for ARMv7-A. */
7712 if (out_attr[Tag_CPU_arch].i == TAG_CPU_ARCH_V7
7713 && (out_attr[Tag_CPU_arch_profile].i == 'A'
7714 || out_attr[Tag_CPU_arch_profile].i == 0))
7715 globals->fix_cortex_a8 = 1;
7716 else
7717 globals->fix_cortex_a8 = 0;
7718 }
7719}
7720
7721
c7b8f16e
JB		 7722void
7723bfd_elf32_arm_set_vfp11_fix (bfd *obfd, struct bfd_link_info *link_info)
7724{
7725 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (link_info);
104d59d1 7726 obj_attribute *out_attr = elf_known_obj_attributes_proc (obfd);
906e58ca 7727
4dfe6ac6
NC		 7728 if (globals == NULL)
7729 return;
c7b8f16e
JB		 7730 /* We assume that ARMv7+ does not need the VFP11 denorm erratum fix. */
7731 if (out_attr[Tag_CPU_arch].i >= TAG_CPU_ARCH_V7)
7732 {
7733 switch (globals->vfp11_fix)
99059e56
RM		 7734 {
7735 case BFD_ARM_VFP11_FIX_DEFAULT:
7736 case BFD_ARM_VFP11_FIX_NONE:
7737 globals->vfp11_fix = BFD_ARM_VFP11_FIX_NONE;
7738 break;
7739
7740 default:
7741 /* Give a warning, but do as the user requests anyway. */
4eca0228 7742 _bfd_error_handler (_("%B: warning: selected VFP11 erratum "
99059e56
RM		 7743 "workaround is not necessary for target architecture"), obfd);
7744 }
c7b8f16e
JB		 7745 }
7746 else if (globals->vfp11_fix == BFD_ARM_VFP11_FIX_DEFAULT)
7747 /* For earlier architectures, we might need the workaround, but do not
7748 enable it by default. If users is running with broken hardware, they
7749 must enable the erratum fix explicitly. */
7750 globals->vfp11_fix = BFD_ARM_VFP11_FIX_NONE;
7751}
7752
a504d23a
LA		 7753void
7754bfd_elf32_arm_set_stm32l4xx_fix (bfd *obfd, struct bfd_link_info *link_info)
7755{
7756 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (link_info);
7757 obj_attribute *out_attr = elf_known_obj_attributes_proc (obfd);
7758
7759 if (globals == NULL)
7760 return;
7761
7762 /* We assume only Cortex-M4 may require the fix. */
7763 if (out_attr[Tag_CPU_arch].i != TAG_CPU_ARCH_V7E_M
7764 || out_attr[Tag_CPU_arch_profile].i != 'M')
7765 {
7766 if (globals->stm32l4xx_fix != BFD_ARM_STM32L4XX_FIX_NONE)
7767 /* Give a warning, but do as the user requests anyway. */
4eca0228 7768 _bfd_error_handler
a504d23a
LA		 7769 (_("%B: warning: selected STM32L4XX erratum "
7770 "workaround is not necessary for target architecture"), obfd);
7771 }
7772}
c7b8f16e 7773
906e58ca
NC		 7774enum bfd_arm_vfp11_pipe
7775{
c7b8f16e
JB		 7776 VFP11_FMAC,
7777 VFP11_LS,
7778 VFP11_DS,
7779 VFP11_BAD
7780};
7781
7782/* Return a VFP register number. This is encoded as RX:X for single-precision
7783 registers, or X:RX for double-precision registers, where RX is the group of
7784 four bits in the instruction encoding and X is the single extension bit.
7785 RX and X fields are specified using their lowest (starting) bit. The return
7786 value is:
7787
7788 0...31: single-precision registers s0...s31
7789 32...63: double-precision registers d0...d31.
906e58ca 7790
c7b8f16e
JB		 7791 Although X should be zero for VFP11 (encoding d0...d15 only), we might
7792 encounter VFP3 instructions, so we allow the full range for DP registers. */
906e58ca 7793
c7b8f16e
JB		 7794static unsigned int
7795bfd_arm_vfp11_regno (unsigned int insn, bfd_boolean is_double, unsigned int rx,
99059e56 7796 unsigned int x)
c7b8f16e
JB		 7797{
7798 if (is_double)
7799 return (((insn >> rx) & 0xf) | (((insn >> x) & 1) << 4)) + 32;
7800 else
7801 return (((insn >> rx) & 0xf) << 1) | ((insn >> x) & 1);
7802}
7803
7804/* Set bits in *WMASK according to a register number REG as encoded by
7805 bfd_arm_vfp11_regno(). Ignore d16-d31. */
7806
7807static void
7808bfd_arm_vfp11_write_mask (unsigned int *wmask, unsigned int reg)
7809{
7810 if (reg < 32)
7811 *wmask |= 1 << reg;
7812 else if (reg < 48)
7813 *wmask |= 3 << ((reg - 32) * 2);
7814}
7815
7816/* Return TRUE if WMASK overwrites anything in REGS. */
7817
7818static bfd_boolean
7819bfd_arm_vfp11_antidependency (unsigned int wmask, int *regs, int numregs)
7820{
7821 int i;
906e58ca 7822
c7b8f16e
JB		 7823 for (i = 0; i < numregs; i++)
7824 {
7825 unsigned int reg = regs[i];
7826
7827 if (reg < 32 && (wmask & (1 << reg)) != 0)
99059e56 7828 return TRUE;
906e58ca 7829
c7b8f16e
JB		 7830 reg -= 32;
7831
7832 if (reg >= 16)
99059e56 7833 continue;
906e58ca 7834
c7b8f16e 7835 if ((wmask & (3 << (reg * 2))) != 0)
99059e56 7836 return TRUE;
c7b8f16e 7837 }
906e58ca 7838
c7b8f16e
JB		 7839 return FALSE;
7840}
7841
7842/* In this function, we're interested in two things: finding input registers
7843 for VFP data-processing instructions, and finding the set of registers which
7844 arbitrary VFP instructions may write to. We use a 32-bit unsigned int to
7845 hold the written set, so FLDM etc. are easy to deal with (we're only
7846 interested in 32 SP registers or 16 dp registers, due to the VFP version
7847 implemented by the chip in question). DP registers are marked by setting
7848 both SP registers in the write mask). */
7849
7850static enum bfd_arm_vfp11_pipe
7851bfd_arm_vfp11_insn_decode (unsigned int insn, unsigned int *destmask, int *regs,
99059e56 7852 int *numregs)
c7b8f16e 7853{
91d6fa6a 7854 enum bfd_arm_vfp11_pipe vpipe = VFP11_BAD;
c7b8f16e
JB		 7855 bfd_boolean is_double = ((insn & 0xf00) == 0xb00) ? 1 : 0;
7856
7857 if ((insn & 0x0f000e10) == 0x0e000a00) /* A data-processing insn. */
7858 {
7859 unsigned int pqrs;
7860 unsigned int fd = bfd_arm_vfp11_regno (insn, is_double, 12, 22);
7861 unsigned int fm = bfd_arm_vfp11_regno (insn, is_double, 0, 5);
7862
7863 pqrs = ((insn & 0x00800000) >> 20)
99059e56
RM		 7864 | ((insn & 0x00300000) >> 19)
7865 | ((insn & 0x00000040) >> 6);
c7b8f16e
JB		 7866
7867 switch (pqrs)
99059e56
RM		 7868 {
7869 case 0: /* fmac[sd]. */
7870 case 1: /* fnmac[sd]. */
7871 case 2: /* fmsc[sd]. */
7872 case 3: /* fnmsc[sd]. */
7873 vpipe = VFP11_FMAC;
7874 bfd_arm_vfp11_write_mask (destmask, fd);
7875 regs[0] = fd;
7876 regs[1] = bfd_arm_vfp11_regno (insn, is_double, 16, 7); /* Fn. */
7877 regs[2] = fm;
7878 *numregs = 3;
7879 break;
7880
7881 case 4: /* fmul[sd]. */
7882 case 5: /* fnmul[sd]. */
7883 case 6: /* fadd[sd]. */
7884 case 7: /* fsub[sd]. */
7885 vpipe = VFP11_FMAC;
7886 goto vfp_binop;
7887
7888 case 8: /* fdiv[sd]. */
7889 vpipe = VFP11_DS;
7890 vfp_binop:
7891 bfd_arm_vfp11_write_mask (destmask, fd);
7892 regs[0] = bfd_arm_vfp11_regno (insn, is_double, 16, 7); /* Fn. */
7893 regs[1] = fm;
7894 *numregs = 2;
7895 break;
7896
7897 case 15: /* extended opcode. */
7898 {
7899 unsigned int extn = ((insn >> 15) & 0x1e)
7900 | ((insn >> 7) & 1);
7901
7902 switch (extn)
7903 {
7904 case 0: /* fcpy[sd]. */
7905 case 1: /* fabs[sd]. */
7906 case 2: /* fneg[sd]. */
7907 case 8: /* fcmp[sd]. */
7908 case 9: /* fcmpe[sd]. */
7909 case 10: /* fcmpz[sd]. */
7910 case 11: /* fcmpez[sd]. */
7911 case 16: /* fuito[sd]. */
7912 case 17: /* fsito[sd]. */
7913 case 24: /* ftoui[sd]. */
7914 case 25: /* ftouiz[sd]. */
7915 case 26: /* ftosi[sd]. */
7916 case 27: /* ftosiz[sd]. */
7917 /* These instructions will not bounce due to underflow. */
7918 *numregs = 0;
7919 vpipe = VFP11_FMAC;
7920 break;
7921
7922 case 3: /* fsqrt[sd]. */
7923 /* fsqrt cannot underflow, but it can (perhaps) overwrite
7924 registers to cause the erratum in previous instructions. */
7925 bfd_arm_vfp11_write_mask (destmask, fd);
7926 vpipe = VFP11_DS;
7927 break;
7928
7929 case 15: /* fcvt{ds,sd}. */
7930 {
7931 int rnum = 0;
7932
7933 bfd_arm_vfp11_write_mask (destmask, fd);
c7b8f16e
JB		 7934
7935 /* Only FCVTSD can underflow. */
99059e56
RM		 7936 if ((insn & 0x100) != 0)
7937 regs[rnum++] = fm;
c7b8f16e 7938
99059e56 7939 *numregs = rnum;
c7b8f16e 7940
99059e56
RM		 7941 vpipe = VFP11_FMAC;
7942 }
7943 break;
c7b8f16e 7944
99059e56
RM		 7945 default:
7946 return VFP11_BAD;
7947 }
7948 }
7949 break;
c7b8f16e 7950
99059e56
RM		 7951 default:
7952 return VFP11_BAD;
7953 }
c7b8f16e
JB		 7954 }
7955 /* Two-register transfer. */
7956 else if ((insn & 0x0fe00ed0) == 0x0c400a10)
7957 {
7958 unsigned int fm = bfd_arm_vfp11_regno (insn, is_double, 0, 5);
906e58ca 7959
c7b8f16e
JB		 7960 if ((insn & 0x100000) == 0)
7961 {
99059e56
RM		 7962 if (is_double)
7963 bfd_arm_vfp11_write_mask (destmask, fm);
7964 else
7965 {
7966 bfd_arm_vfp11_write_mask (destmask, fm);
7967 bfd_arm_vfp11_write_mask (destmask, fm + 1);
7968 }
c7b8f16e
JB		 7969 }
7970
91d6fa6a 7971 vpipe = VFP11_LS;
c7b8f16e
JB		 7972 }
7973 else if ((insn & 0x0e100e00) == 0x0c100a00) /* A load insn. */
7974 {
7975 int fd = bfd_arm_vfp11_regno (insn, is_double, 12, 22);
7976 unsigned int puw = ((insn >> 21) & 0x1) | (((insn >> 23) & 3) << 1);
906e58ca 7977
c7b8f16e 7978 switch (puw)
99059e56
RM		 7979 {
7980 case 0: /* Two-reg transfer. We should catch these above. */
7981 abort ();
906e58ca 7982
99059e56
RM		 7983 case 2: /* fldm[sdx]. */
7984 case 3:
7985 case 5:
7986 {
7987 unsigned int i, offset = insn & 0xff;
c7b8f16e 7988
99059e56
RM		 7989 if (is_double)
7990 offset >>= 1;
c7b8f16e 7991
99059e56
RM		 7992 for (i = fd; i < fd + offset; i++)
7993 bfd_arm_vfp11_write_mask (destmask, i);
7994 }
7995 break;
906e58ca 7996
99059e56
RM		 7997 case 4: /* fld[sd]. */
7998 case 6:
7999 bfd_arm_vfp11_write_mask (destmask, fd);
8000 break;
906e58ca 8001
99059e56
RM		 8002 default:
8003 return VFP11_BAD;
8004 }
c7b8f16e 8005
91d6fa6a 8006 vpipe = VFP11_LS;
c7b8f16e
JB		 8007 }
8008 /* Single-register transfer. Note L==0. */
8009 else if ((insn & 0x0f100e10) == 0x0e000a10)
8010 {
8011 unsigned int opcode = (insn >> 21) & 7;
8012 unsigned int fn = bfd_arm_vfp11_regno (insn, is_double, 16, 7);
8013
8014 switch (opcode)
99059e56
RM		 8015 {
8016 case 0: /* fmsr/fmdlr. */
8017 case 1: /* fmdhr. */
8018 /* Mark fmdhr and fmdlr as writing to the whole of the DP
8019 destination register. I don't know if this is exactly right,
8020 but it is the conservative choice. */
8021 bfd_arm_vfp11_write_mask (destmask, fn);
8022 break;
8023
8024 case 7: /* fmxr. */
8025 break;
8026 }
c7b8f16e 8027
91d6fa6a 8028 vpipe = VFP11_LS;
c7b8f16e
JB		 8029 }
8030
91d6fa6a 8031 return vpipe;
c7b8f16e
JB		 8032}
8033
8034
8035static int elf32_arm_compare_mapping (const void * a, const void * b);
8036
8037
8038/* Look for potentially-troublesome code sequences which might trigger the
8039 VFP11 denormal/antidependency erratum. See, e.g., the ARM1136 errata sheet
8040 (available from ARM) for details of the erratum. A short version is
8041 described in ld.texinfo. */
8042
8043bfd_boolean
8044bfd_elf32_arm_vfp11_erratum_scan (bfd *abfd, struct bfd_link_info *link_info)
8045{
8046 asection *sec;
8047 bfd_byte *contents = NULL;
8048 int state = 0;
8049 int regs[3], numregs = 0;
8050 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (link_info);
8051 int use_vector = (globals->vfp11_fix == BFD_ARM_VFP11_FIX_VECTOR);
906e58ca 8052
4dfe6ac6
NC		 8053 if (globals == NULL)
8054 return FALSE;
8055
c7b8f16e
JB		 8056 /* We use a simple FSM to match troublesome VFP11 instruction sequences.
8057 The states transition as follows:
906e58ca 8058
c7b8f16e 8059 0 -> 1 (vector) or 0 -> 2 (scalar)
99059e56
RM		 8060 A VFP FMAC-pipeline instruction has been seen. Fill
8061 regs[0]..regs[numregs-1] with its input operands. Remember this
8062 instruction in 'first_fmac'.
c7b8f16e
JB		 8063
8064 1 -> 2
99059e56
RM		 8065 Any instruction, except for a VFP instruction which overwrites
8066 regs[*].
906e58ca 8067
c7b8f16e
JB		 8068 1 -> 3 [ -> 0 ] or
8069 2 -> 3 [ -> 0 ]
99059e56
RM		 8070 A VFP instruction has been seen which overwrites any of regs[*].
8071 We must make a veneer! Reset state to 0 before examining next
8072 instruction.
906e58ca 8073
c7b8f16e 8074 2 -> 0
99059e56
RM		 8075 If we fail to match anything in state 2, reset to state 0 and reset
8076 the instruction pointer to the instruction after 'first_fmac'.
c7b8f16e
JB		 8077
8078 If the VFP11 vector mode is in use, there must be at least two unrelated
8079 instructions between anti-dependent VFP11 instructions to properly avoid
906e58ca 8080 triggering the erratum, hence the use of the extra state 1. */
c7b8f16e
JB		 8081
8082 /* If we are only performing a partial link do not bother
8083 to construct any glue. */
0e1862bb 8084 if (bfd_link_relocatable (link_info))
c7b8f16e
JB		 8085 return TRUE;
8086
0ffa91dd
NC		 8087 /* Skip if this bfd does not correspond to an ELF image. */
8088 if (! is_arm_elf (abfd))
8089 return TRUE;
906e58ca 8090
c7b8f16e
JB		 8091 /* We should have chosen a fix type by the time we get here. */
8092 BFD_ASSERT (globals->vfp11_fix != BFD_ARM_VFP11_FIX_DEFAULT);
8093
8094 if (globals->vfp11_fix == BFD_ARM_VFP11_FIX_NONE)
8095 return TRUE;
2e6030b9 8096
33a7ffc2
JM		 8097 /* Skip this BFD if it corresponds to an executable or dynamic object. */
8098 if ((abfd->flags & (EXEC_P | DYNAMIC)) != 0)
8099 return TRUE;
8100
c7b8f16e
JB		 8101 for (sec = abfd->sections; sec != NULL; sec = sec->next)
8102 {
8103 unsigned int i, span, first_fmac = 0, veneer_of_insn = 0;
8104 struct _arm_elf_section_data *sec_data;
8105
8106 /* If we don't have executable progbits, we're not interested in this
99059e56 8107 section. Also skip if section is to be excluded. */
c7b8f16e 8108 if (elf_section_type (sec) != SHT_PROGBITS
99059e56
RM		 8109 || (elf_section_flags (sec) & SHF_EXECINSTR) == 0
8110 || (sec->flags & SEC_EXCLUDE) != 0
dbaa2011 8111 || sec->sec_info_type == SEC_INFO_TYPE_JUST_SYMS
33a7ffc2 8112 || sec->output_section == bfd_abs_section_ptr
99059e56
RM		 8113 || strcmp (sec->name, VFP11_ERRATUM_VENEER_SECTION_NAME) == 0)
8114 continue;
c7b8f16e
JB		 8115
8116 sec_data = elf32_arm_section_data (sec);
906e58ca 8117
c7b8f16e 8118 if (sec_data->mapcount == 0)
99059e56 8119 continue;
906e58ca 8120
c7b8f16e
JB		 8121 if (elf_section_data (sec)->this_hdr.contents != NULL)
8122 contents = elf_section_data (sec)->this_hdr.contents;
8123 else if (! bfd_malloc_and_get_section (abfd, sec, &contents))
8124 goto error_return;
8125
8126 qsort (sec_data->map, sec_data->mapcount, sizeof (elf32_arm_section_map),
8127 elf32_arm_compare_mapping);
8128
8129 for (span = 0; span < sec_data->mapcount; span++)
99059e56
RM		 8130 {
8131 unsigned int span_start = sec_data->map[span].vma;
8132 unsigned int span_end = (span == sec_data->mapcount - 1)
c7b8f16e 8133 ? sec->size : sec_data->map[span + 1].vma;
99059e56
RM		 8134 char span_type = sec_data->map[span].type;
8135
8136 /* FIXME: Only ARM mode is supported at present. We may need to
8137 support Thumb-2 mode also at some point. */
8138 if (span_type != 'a')
8139 continue;
8140
8141 for (i = span_start; i < span_end;)
8142 {
8143 unsigned int next_i = i + 4;
8144 unsigned int insn = bfd_big_endian (abfd)
8145 ? (contents[i] << 24)
8146 | (contents[i + 1] << 16)
8147 | (contents[i + 2] << 8)
8148 | contents[i + 3]
8149 : (contents[i + 3] << 24)
8150 | (contents[i + 2] << 16)
8151 | (contents[i + 1] << 8)
8152 | contents[i];
8153 unsigned int writemask = 0;
8154 enum bfd_arm_vfp11_pipe vpipe;
8155
8156 switch (state)
8157 {
8158 case 0:
8159 vpipe = bfd_arm_vfp11_insn_decode (insn, &writemask, regs,
8160 &numregs);
8161 /* I'm assuming the VFP11 erratum can trigger with denorm
8162 operands on either the FMAC or the DS pipeline. This might
8163 lead to slightly overenthusiastic veneer insertion. */
8164 if (vpipe == VFP11_FMAC || vpipe == VFP11_DS)
8165 {
8166 state = use_vector ? 1 : 2;
8167 first_fmac = i;
8168 veneer_of_insn = insn;
8169 }
8170 break;
8171
8172 case 1:
8173 {
8174 int other_regs[3], other_numregs;
8175 vpipe = bfd_arm_vfp11_insn_decode (insn, &writemask,
c7b8f16e 8176 other_regs,
99059e56
RM		 8177 &other_numregs);
8178 if (vpipe != VFP11_BAD
8179 && bfd_arm_vfp11_antidependency (writemask, regs,
c7b8f16e 8180 numregs))
99059e56
RM		 8181 state = 3;
8182 else
8183 state = 2;
8184 }
8185 break;
8186
8187 case 2:
8188 {
8189 int other_regs[3], other_numregs;
8190 vpipe = bfd_arm_vfp11_insn_decode (insn, &writemask,
c7b8f16e 8191 other_regs,
99059e56
RM		 8192 &other_numregs);
8193 if (vpipe != VFP11_BAD
8194 && bfd_arm_vfp11_antidependency (writemask, regs,
c7b8f16e 8195 numregs))
99059e56
RM		 8196 state = 3;
8197 else
8198 {
8199 state = 0;
8200 next_i = first_fmac + 4;
8201 }
8202 }
8203 break;
8204
8205 case 3:
8206 abort (); /* Should be unreachable. */
8207 }
8208
8209 if (state == 3)
8210 {
8211 elf32_vfp11_erratum_list *newerr =(elf32_vfp11_erratum_list *)
8212 bfd_zmalloc (sizeof (elf32_vfp11_erratum_list));
8213
8214 elf32_arm_section_data (sec)->erratumcount += 1;
8215
8216 newerr->u.b.vfp_insn = veneer_of_insn;
8217
8218 switch (span_type)
8219 {
8220 case 'a':
8221 newerr->type = VFP11_ERRATUM_BRANCH_TO_ARM_VENEER;
8222 break;
8223
8224 default:
8225 abort ();
8226 }
8227
8228 record_vfp11_erratum_veneer (link_info, newerr, abfd, sec,
c7b8f16e
JB		 8229 first_fmac);
8230
99059e56 8231 newerr->vma = -1;
c7b8f16e 8232
99059e56
RM		 8233 newerr->next = sec_data->erratumlist;
8234 sec_data->erratumlist = newerr;
c7b8f16e 8235
99059e56
RM		 8236 state = 0;
8237 }
c7b8f16e 8238
99059e56
RM		 8239 i = next_i;
8240 }
8241 }
906e58ca 8242
c7b8f16e 8243 if (contents != NULL
99059e56
RM		 8244 && elf_section_data (sec)->this_hdr.contents != contents)
8245 free (contents);
c7b8f16e
JB		 8246 contents = NULL;
8247 }
8248
8249 return TRUE;
8250
8251error_return:
8252 if (contents != NULL
8253 && elf_section_data (sec)->this_hdr.contents != contents)
8254 free (contents);
906e58ca 8255
c7b8f16e
JB		 8256 return FALSE;
8257}
8258
8259/* Find virtual-memory addresses for VFP11 erratum veneers and return locations
8260 after sections have been laid out, using specially-named symbols. */
8261
8262void
8263bfd_elf32_arm_vfp11_fix_veneer_locations (bfd *abfd,
8264 struct bfd_link_info *link_info)
8265{
8266 asection *sec;
8267 struct elf32_arm_link_hash_table *globals;
8268 char *tmp_name;
906e58ca 8269
0e1862bb 8270 if (bfd_link_relocatable (link_info))
c7b8f16e 8271 return;
2e6030b9
MS		 8272
8273 /* Skip if this bfd does not correspond to an ELF image. */
0ffa91dd 8274 if (! is_arm_elf (abfd))
2e6030b9
MS		 8275 return;
8276
c7b8f16e 8277 globals = elf32_arm_hash_table (link_info);
4dfe6ac6
NC		 8278 if (globals == NULL)
8279 return;
906e58ca 8280
21d799b5 8281 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen
99059e56 8282 (VFP11_ERRATUM_VENEER_ENTRY_NAME) + 10);
c7b8f16e
JB		 8283
8284 for (sec = abfd->sections; sec != NULL; sec = sec->next)
8285 {
8286 struct _arm_elf_section_data *sec_data = elf32_arm_section_data (sec);
8287 elf32_vfp11_erratum_list *errnode = sec_data->erratumlist;
906e58ca 8288
c7b8f16e 8289 for (; errnode != NULL; errnode = errnode->next)
99059e56
RM		 8290 {
8291 struct elf_link_hash_entry *myh;
8292 bfd_vma vma;
8293
8294 switch (errnode->type)
8295 {
8296 case VFP11_ERRATUM_BRANCH_TO_ARM_VENEER:
8297 case VFP11_ERRATUM_BRANCH_TO_THUMB_VENEER:
8298 /* Find veneer symbol. */
8299 sprintf (tmp_name, VFP11_ERRATUM_VENEER_ENTRY_NAME,
c7b8f16e
JB		 8300 errnode->u.b.veneer->u.v.id);
8301
99059e56
RM		 8302 myh = elf_link_hash_lookup
8303 (&(globals)->root, tmp_name, FALSE, FALSE, TRUE);
c7b8f16e 8304
a504d23a 8305 if (myh == NULL)
4eca0228
AM		 8306 _bfd_error_handler (_("%B: unable to find VFP11 veneer "
8307 "`%s'"), abfd, tmp_name);
a504d23a
LA		 8308
8309 vma = myh->root.u.def.section->output_section->vma
8310 + myh->root.u.def.section->output_offset
8311 + myh->root.u.def.value;
8312
8313 errnode->u.b.veneer->vma = vma;
8314 break;
8315
8316 case VFP11_ERRATUM_ARM_VENEER:
8317 case VFP11_ERRATUM_THUMB_VENEER:
8318 /* Find return location. */
8319 sprintf (tmp_name, VFP11_ERRATUM_VENEER_ENTRY_NAME "_r",
8320 errnode->u.v.id);
8321
8322 myh = elf_link_hash_lookup
8323 (&(globals)->root, tmp_name, FALSE, FALSE, TRUE);
8324
8325 if (myh == NULL)
4eca0228
AM		 8326 _bfd_error_handler (_("%B: unable to find VFP11 veneer "
8327 "`%s'"), abfd, tmp_name);
a504d23a
LA		 8328
8329 vma = myh->root.u.def.section->output_section->vma
8330 + myh->root.u.def.section->output_offset
8331 + myh->root.u.def.value;
8332
8333 errnode->u.v.branch->vma = vma;
8334 break;
8335
8336 default:
8337 abort ();
8338 }
8339 }
8340 }
8341
8342 free (tmp_name);
8343}
8344
8345/* Find virtual-memory addresses for STM32L4XX erratum veneers and
8346 return locations after sections have been laid out, using
8347 specially-named symbols. */
8348
8349void
8350bfd_elf32_arm_stm32l4xx_fix_veneer_locations (bfd *abfd,
8351 struct bfd_link_info *link_info)
8352{
8353 asection *sec;
8354 struct elf32_arm_link_hash_table *globals;
8355 char *tmp_name;
8356
8357 if (bfd_link_relocatable (link_info))
8358 return;
8359
8360 /* Skip if this bfd does not correspond to an ELF image. */
8361 if (! is_arm_elf (abfd))
8362 return;
8363
8364 globals = elf32_arm_hash_table (link_info);
8365 if (globals == NULL)
8366 return;
8367
8368 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen
8369 (STM32L4XX_ERRATUM_VENEER_ENTRY_NAME) + 10);
8370
8371 for (sec = abfd->sections; sec != NULL; sec = sec->next)
8372 {
8373 struct _arm_elf_section_data *sec_data = elf32_arm_section_data (sec);
8374 elf32_stm32l4xx_erratum_list *errnode = sec_data->stm32l4xx_erratumlist;
8375
8376 for (; errnode != NULL; errnode = errnode->next)
8377 {
8378 struct elf_link_hash_entry *myh;
8379 bfd_vma vma;
8380
8381 switch (errnode->type)
8382 {
8383 case STM32L4XX_ERRATUM_BRANCH_TO_VENEER:
8384 /* Find veneer symbol. */
8385 sprintf (tmp_name, STM32L4XX_ERRATUM_VENEER_ENTRY_NAME,
8386 errnode->u.b.veneer->u.v.id);
8387
8388 myh = elf_link_hash_lookup
8389 (&(globals)->root, tmp_name, FALSE, FALSE, TRUE);
8390
8391 if (myh == NULL)
4eca0228
AM		 8392 _bfd_error_handler (_("%B: unable to find STM32L4XX veneer "
8393 "`%s'"), abfd, tmp_name);
a504d23a
LA		 8394
8395 vma = myh->root.u.def.section->output_section->vma
8396 + myh->root.u.def.section->output_offset
8397 + myh->root.u.def.value;
8398
8399 errnode->u.b.veneer->vma = vma;
8400 break;
8401
8402 case STM32L4XX_ERRATUM_VENEER:
8403 /* Find return location. */
8404 sprintf (tmp_name, STM32L4XX_ERRATUM_VENEER_ENTRY_NAME "_r",
8405 errnode->u.v.id);
8406
8407 myh = elf_link_hash_lookup
8408 (&(globals)->root, tmp_name, FALSE, FALSE, TRUE);
8409
8410 if (myh == NULL)
4eca0228
AM		 8411 _bfd_error_handler (_("%B: unable to find STM32L4XX veneer "
8412 "`%s'"), abfd, tmp_name);
a504d23a
LA		 8413
8414 vma = myh->root.u.def.section->output_section->vma
8415 + myh->root.u.def.section->output_offset
8416 + myh->root.u.def.value;
8417
8418 errnode->u.v.branch->vma = vma;
8419 break;
8420
8421 default:
8422 abort ();
8423 }
8424 }
8425 }
8426
8427 free (tmp_name);
8428}
8429
8430static inline bfd_boolean
8431is_thumb2_ldmia (const insn32 insn)
8432{
8433 /* Encoding T2: LDM<c>.W <Rn>{!},<registers>
8434 1110 - 1000 - 10W1 - rrrr - PM (0) l - llll - llll - llll. */
8435 return (insn & 0xffd02000) == 0xe8900000;
8436}
8437
8438static inline bfd_boolean
8439is_thumb2_ldmdb (const insn32 insn)
8440{
8441 /* Encoding T1: LDMDB<c> <Rn>{!},<registers>
8442 1110 - 1001 - 00W1 - rrrr - PM (0) l - llll - llll - llll. */
8443 return (insn & 0xffd02000) == 0xe9100000;
8444}
8445
8446static inline bfd_boolean
8447is_thumb2_vldm (const insn32 insn)
8448{
8449 /* A6.5 Extension register load or store instruction
8450 A7.7.229
9239bbd3
CM		 8451 We look for SP 32-bit and DP 64-bit registers.
8452 Encoding T1 VLDM{mode}<c> <Rn>{!}, <list>
8453 <list> is consecutive 64-bit registers
8454 1110 - 110P - UDW1 - rrrr - vvvv - 1011 - iiii - iiii
a504d23a
LA		 8455 Encoding T2 VLDM{mode}<c> <Rn>{!}, <list>
8456 <list> is consecutive 32-bit registers
8457 1110 - 110P - UDW1 - rrrr - vvvv - 1010 - iiii - iiii
8458 if P==0 && U==1 && W==1 && Rn=1101 VPOP
8459 if PUW=010 || PUW=011 || PUW=101 VLDM. */
8460 return
9239bbd3
CM		 8461 (((insn & 0xfe100f00) == 0xec100b00) ||
8462 ((insn & 0xfe100f00) == 0xec100a00))
a504d23a
LA		 8463 && /* (IA without !). */
8464 (((((insn << 7) >> 28) & 0xd) == 0x4)
9239bbd3 8465 /* (IA with !), includes VPOP (when reg number is SP). */
a504d23a
LA		 8466 || ((((insn << 7) >> 28) & 0xd) == 0x5)
8467 /* (DB with !). */
8468 || ((((insn << 7) >> 28) & 0xd) == 0x9));
8469}
8470
8471/* STM STM32L4XX erratum : This function assumes that it receives an LDM or
8472 VLDM opcode and:
8473 - computes the number and the mode of memory accesses
8474 - decides if the replacement should be done:
8475 . replaces only if > 8-word accesses
8476 . or (testing purposes only) replaces all accesses. */
8477
8478static bfd_boolean
8479stm32l4xx_need_create_replacing_stub (const insn32 insn,
8480 bfd_arm_stm32l4xx_fix stm32l4xx_fix)
8481{
9239bbd3 8482 int nb_words = 0;
a504d23a
LA		 8483
8484 /* The field encoding the register list is the same for both LDMIA
8485 and LDMDB encodings. */
8486 if (is_thumb2_ldmia (insn) || is_thumb2_ldmdb (insn))
b25e998d 8487 nb_words = elf32_arm_popcount (insn & 0x0000ffff);
a504d23a 8488 else if (is_thumb2_vldm (insn))
9239bbd3 8489 nb_words = (insn & 0xff);
a504d23a
LA		 8490
8491 /* DEFAULT mode accounts for the real bug condition situation,
8492 ALL mode inserts stubs for each LDM/VLDM instruction (testing). */
8493 return
9239bbd3 8494 (stm32l4xx_fix == BFD_ARM_STM32L4XX_FIX_DEFAULT) ? nb_words > 8 :
a504d23a
LA		 8495 (stm32l4xx_fix == BFD_ARM_STM32L4XX_FIX_ALL) ? TRUE : FALSE;
8496}
8497
8498/* Look for potentially-troublesome code sequences which might trigger
8499 the STM STM32L4XX erratum. */
8500
8501bfd_boolean
8502bfd_elf32_arm_stm32l4xx_erratum_scan (bfd *abfd,
8503 struct bfd_link_info *link_info)
8504{
8505 asection *sec;
8506 bfd_byte *contents = NULL;
8507 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (link_info);
8508
8509 if (globals == NULL)
8510 return FALSE;
8511
8512 /* If we are only performing a partial link do not bother
8513 to construct any glue. */
8514 if (bfd_link_relocatable (link_info))
8515 return TRUE;
8516
8517 /* Skip if this bfd does not correspond to an ELF image. */
8518 if (! is_arm_elf (abfd))
8519 return TRUE;
8520
8521 if (globals->stm32l4xx_fix == BFD_ARM_STM32L4XX_FIX_NONE)
8522 return TRUE;
8523
8524 /* Skip this BFD if it corresponds to an executable or dynamic object. */
8525 if ((abfd->flags & (EXEC_P | DYNAMIC)) != 0)
8526 return TRUE;
8527
8528 for (sec = abfd->sections; sec != NULL; sec = sec->next)
8529 {
8530 unsigned int i, span;
8531 struct _arm_elf_section_data *sec_data;
8532
8533 /* If we don't have executable progbits, we're not interested in this
8534 section. Also skip if section is to be excluded. */
8535 if (elf_section_type (sec) != SHT_PROGBITS
8536 || (elf_section_flags (sec) & SHF_EXECINSTR) == 0
8537 || (sec->flags & SEC_EXCLUDE) != 0
8538 || sec->sec_info_type == SEC_INFO_TYPE_JUST_SYMS
8539 || sec->output_section == bfd_abs_section_ptr
8540 || strcmp (sec->name, STM32L4XX_ERRATUM_VENEER_SECTION_NAME) == 0)
8541 continue;
8542
8543 sec_data = elf32_arm_section_data (sec);
c7b8f16e 8544
a504d23a
LA		 8545 if (sec_data->mapcount == 0)
8546 continue;
c7b8f16e 8547
a504d23a
LA		 8548 if (elf_section_data (sec)->this_hdr.contents != NULL)
8549 contents = elf_section_data (sec)->this_hdr.contents;
8550 else if (! bfd_malloc_and_get_section (abfd, sec, &contents))
8551 goto error_return;
c7b8f16e 8552
a504d23a
LA		 8553 qsort (sec_data->map, sec_data->mapcount, sizeof (elf32_arm_section_map),
8554 elf32_arm_compare_mapping);
c7b8f16e 8555
a504d23a
LA		 8556 for (span = 0; span < sec_data->mapcount; span++)
8557 {
8558 unsigned int span_start = sec_data->map[span].vma;
8559 unsigned int span_end = (span == sec_data->mapcount - 1)
8560 ? sec->size : sec_data->map[span + 1].vma;
8561 char span_type = sec_data->map[span].type;
8562 int itblock_current_pos = 0;
c7b8f16e 8563
a504d23a
LA		 8564 /* Only Thumb2 mode need be supported with this CM4 specific
8565 code, we should not encounter any arm mode eg span_type
8566 != 'a'. */
8567 if (span_type != 't')
8568 continue;
c7b8f16e 8569
a504d23a
LA		 8570 for (i = span_start; i < span_end;)
8571 {
8572 unsigned int insn = bfd_get_16 (abfd, &contents[i]);
8573 bfd_boolean insn_32bit = FALSE;
8574 bfd_boolean is_ldm = FALSE;
8575 bfd_boolean is_vldm = FALSE;
8576 bfd_boolean is_not_last_in_it_block = FALSE;
8577
8578 /* The first 16-bits of all 32-bit thumb2 instructions start
8579 with opcode[15..13]=0b111 and the encoded op1 can be anything
8580 except opcode[12..11]!=0b00.
8581 See 32-bit Thumb instruction encoding. */
8582 if ((insn & 0xe000) == 0xe000 && (insn & 0x1800) != 0x0000)
8583 insn_32bit = TRUE;
c7b8f16e 8584
a504d23a
LA		 8585 /* Compute the predicate that tells if the instruction
8586 is concerned by the IT block
8587 - Creates an error if there is a ldm that is not
8588 last in the IT block thus cannot be replaced
8589 - Otherwise we can create a branch at the end of the
8590 IT block, it will be controlled naturally by IT
8591 with the proper pseudo-predicate
8592 - So the only interesting predicate is the one that
8593 tells that we are not on the last item of an IT
8594 block. */
8595 if (itblock_current_pos != 0)
8596 is_not_last_in_it_block = !!--itblock_current_pos;
906e58ca 8597
a504d23a
LA		 8598 if (insn_32bit)
8599 {
8600 /* Load the rest of the insn (in manual-friendly order). */
8601 insn = (insn << 16) | bfd_get_16 (abfd, &contents[i + 2]);
8602 is_ldm = is_thumb2_ldmia (insn) || is_thumb2_ldmdb (insn);
8603 is_vldm = is_thumb2_vldm (insn);
8604
8605 /* Veneers are created for (v)ldm depending on
8606 option flags and memory accesses conditions; but
8607 if the instruction is not the last instruction of
8608 an IT block, we cannot create a jump there, so we
8609 bail out. */
5025eb7c
AO		 8610 if ((is_ldm || is_vldm)
8611 && stm32l4xx_need_create_replacing_stub
a504d23a
LA		 8612 (insn, globals->stm32l4xx_fix))
8613 {
8614 if (is_not_last_in_it_block)
8615 {
4eca0228 8616 _bfd_error_handler
695344c0 8617 /* xgettext:c-format */
63a5468a
AM		 8618 (_("%B(%A+0x%lx): error: multiple load detected"
8619 " in non-last IT block instruction :"
8620 " STM32L4XX veneer cannot be generated.\n"
8621 "Use gcc option -mrestrict-it to generate"
8622 " only one instruction per IT block.\n"),
695344c0 8623 abfd, sec, (long) i);
a504d23a
LA		 8624 }
8625 else
8626 {
8627 elf32_stm32l4xx_erratum_list *newerr =
8628 (elf32_stm32l4xx_erratum_list *)
8629 bfd_zmalloc
8630 (sizeof (elf32_stm32l4xx_erratum_list));
8631
8632 elf32_arm_section_data (sec)
8633 ->stm32l4xx_erratumcount += 1;
8634 newerr->u.b.insn = insn;
8635 /* We create only thumb branches. */
8636 newerr->type =
8637 STM32L4XX_ERRATUM_BRANCH_TO_VENEER;
8638 record_stm32l4xx_erratum_veneer
8639 (link_info, newerr, abfd, sec,
8640 i,
8641 is_ldm ?
8642 STM32L4XX_ERRATUM_LDM_VENEER_SIZE:
8643 STM32L4XX_ERRATUM_VLDM_VENEER_SIZE);
8644 newerr->vma = -1;
8645 newerr->next = sec_data->stm32l4xx_erratumlist;
8646 sec_data->stm32l4xx_erratumlist = newerr;
8647 }
8648 }
8649 }
8650 else
8651 {
8652 /* A7.7.37 IT p208
8653 IT blocks are only encoded in T1
8654 Encoding T1: IT{x{y{z}}} <firstcond>
8655 1 0 1 1 - 1 1 1 1 - firstcond - mask
8656 if mask = '0000' then see 'related encodings'
8657 We don't deal with UNPREDICTABLE, just ignore these.
8658 There can be no nested IT blocks so an IT block
8659 is naturally a new one for which it is worth
8660 computing its size. */
5025eb7c
AO		 8661 bfd_boolean is_newitblock = ((insn & 0xff00) == 0xbf00)
8662 && ((insn & 0x000f) != 0x0000);
a504d23a
LA		 8663 /* If we have a new IT block we compute its size. */
8664 if (is_newitblock)
8665 {
8666 /* Compute the number of instructions controlled
8667 by the IT block, it will be used to decide
8668 whether we are inside an IT block or not. */
8669 unsigned int mask = insn & 0x000f;
8670 itblock_current_pos = 4 - ctz (mask);
8671 }
8672 }
8673
8674 i += insn_32bit ? 4 : 2;
99059e56
RM		 8675 }
8676 }
a504d23a
LA		 8677
8678 if (contents != NULL
8679 && elf_section_data (sec)->this_hdr.contents != contents)
8680 free (contents);
8681 contents = NULL;
c7b8f16e 8682 }
906e58ca 8683
a504d23a
LA		 8684 return TRUE;
8685
8686error_return:
8687 if (contents != NULL
8688 && elf_section_data (sec)->this_hdr.contents != contents)
8689 free (contents);
c7b8f16e 8690
a504d23a
LA		 8691 return FALSE;
8692}
c7b8f16e 8693
eb043451
PB		 8694/* Set target relocation values needed during linking. */
8695
8696void
68c39892 8697bfd_elf32_arm_set_target_params (struct bfd *output_bfd,
bf21ed78 8698 struct bfd_link_info *link_info,
68c39892 8699 struct elf32_arm_params *params)
eb043451
PB		 8700{
8701 struct elf32_arm_link_hash_table *globals;
8702
8703 globals = elf32_arm_hash_table (link_info);
4dfe6ac6
NC		 8704 if (globals == NULL)
8705 return;
eb043451 8706
68c39892
TP		 8707 globals->target1_is_rel = params->target1_is_rel;
8708 if (strcmp (params->target2_type, "rel") == 0)
eb043451 8709 globals->target2_reloc = R_ARM_REL32;
68c39892 8710 else if (strcmp (params->target2_type, "abs") == 0)
eeac373a 8711 globals->target2_reloc = R_ARM_ABS32;
68c39892 8712 else if (strcmp (params->target2_type, "got-rel") == 0)
eb043451
PB		 8713 globals->target2_reloc = R_ARM_GOT_PREL;
8714 else
8715 {
8716 _bfd_error_handler (_("Invalid TARGET2 relocation type '%s'."),
68c39892 8717 params->target2_type);
eb043451 8718 }
68c39892
TP		 8719 globals->fix_v4bx = params->fix_v4bx;
8720 globals->use_blx |= params->use_blx;
8721 globals->vfp11_fix = params->vfp11_denorm_fix;
8722 globals->stm32l4xx_fix = params->stm32l4xx_fix;
8723 globals->pic_veneer = params->pic_veneer;
8724 globals->fix_cortex_a8 = params->fix_cortex_a8;
8725 globals->fix_arm1176 = params->fix_arm1176;
8726 globals->cmse_implib = params->cmse_implib;
8727 globals->in_implib_bfd = params->in_implib_bfd;
bf21ed78 8728
0ffa91dd 8729 BFD_ASSERT (is_arm_elf (output_bfd));
68c39892
TP		 8730 elf_arm_tdata (output_bfd)->no_enum_size_warning
8731 = params->no_enum_size_warning;
8732 elf_arm_tdata (output_bfd)->no_wchar_size_warning
8733 = params->no_wchar_size_warning;
eb043451 8734}
eb043451 8735
12a0a0fd 8736/* Replace the target offset of a Thumb bl or b.w instruction. */
252b5132 8737
12a0a0fd
PB		 8738static void
8739insert_thumb_branch (bfd *abfd, long int offset, bfd_byte *insn)
8740{
8741 bfd_vma upper;
8742 bfd_vma lower;
8743 int reloc_sign;
8744
8745 BFD_ASSERT ((offset & 1) == 0);
8746
8747 upper = bfd_get_16 (abfd, insn);
8748 lower = bfd_get_16 (abfd, insn + 2);
8749 reloc_sign = (offset < 0) ? 1 : 0;
8750 upper = (upper & ~(bfd_vma) 0x7ff)
8751 | ((offset >> 12) & 0x3ff)
8752 | (reloc_sign << 10);
906e58ca 8753 lower = (lower & ~(bfd_vma) 0x2fff)
12a0a0fd
PB		 8754 | (((!((offset >> 23) & 1)) ^ reloc_sign) << 13)
8755 | (((!((offset >> 22) & 1)) ^ reloc_sign) << 11)
8756 | ((offset >> 1) & 0x7ff);
8757 bfd_put_16 (abfd, upper, insn);
8758 bfd_put_16 (abfd, lower, insn + 2);
252b5132
RH		 8759}
8760
9b485d32
NC		 8761/* Thumb code calling an ARM function. */
8762
252b5132 8763static int
57e8b36a
NC		 8764elf32_thumb_to_arm_stub (struct bfd_link_info * info,
8765 const char * name,
8766 bfd * input_bfd,
8767 bfd * output_bfd,
8768 asection * input_section,
8769 bfd_byte * hit_data,
8770 asection * sym_sec,
8771 bfd_vma offset,
8772 bfd_signed_vma addend,
f2a9dd69
DJ		 8773 bfd_vma val,
8774 char **error_message)
252b5132 8775{
bcbdc74c 8776 asection * s = 0;
dc810e39 8777 bfd_vma my_offset;
252b5132 8778 long int ret_offset;
bcbdc74c
NC		 8779 struct elf_link_hash_entry * myh;
8780 struct elf32_arm_link_hash_table * globals;
252b5132 8781
f2a9dd69 8782 myh = find_thumb_glue (info, name, error_message);
252b5132 8783 if (myh == NULL)
b34976b6 8784 return FALSE;
252b5132
RH		 8785
8786 globals = elf32_arm_hash_table (info);
252b5132
RH		 8787 BFD_ASSERT (globals != NULL);
8788 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
8789
8790 my_offset = myh->root.u.def.value;
8791
3d4d4302
AM		 8792 s = bfd_get_linker_section (globals->bfd_of_glue_owner,
8793 THUMB2ARM_GLUE_SECTION_NAME);
252b5132
RH		 8794
8795 BFD_ASSERT (s != NULL);
8796 BFD_ASSERT (s->contents != NULL);
8797 BFD_ASSERT (s->output_section != NULL);
8798
8799 if ((my_offset & 0x01) == 0x01)
8800 {
8801 if (sym_sec != NULL
8802 && sym_sec->owner != NULL
8803 && !INTERWORK_FLAG (sym_sec->owner))
8804 {
4eca0228 8805 _bfd_error_handler
d003868e 8806 (_("%B(%s): warning: interworking not enabled.\n"
3aaeb7d3 8807 " first occurrence: %B: Thumb call to ARM"),
c08bb8dd 8808 sym_sec->owner, name, input_bfd);
252b5132 8809
b34976b6 8810 return FALSE;
252b5132
RH		 8811 }
8812
8813 --my_offset;
8814 myh->root.u.def.value = my_offset;
8815
52ab56c2
PB		 8816 put_thumb_insn (globals, output_bfd, (bfd_vma) t2a1_bx_pc_insn,
8817 s->contents + my_offset);
252b5132 8818
52ab56c2
PB		 8819 put_thumb_insn (globals, output_bfd, (bfd_vma) t2a2_noop_insn,
8820 s->contents + my_offset + 2);
252b5132
RH		 8821
8822 ret_offset =
9b485d32
NC		 8823 /* Address of destination of the stub. */
8824 ((bfd_signed_vma) val)
252b5132 8825 - ((bfd_signed_vma)
57e8b36a
NC		 8826 /* Offset from the start of the current section
8827 to the start of the stubs. */
9b485d32
NC		 8828 (s->output_offset
8829 /* Offset of the start of this stub from the start of the stubs. */
8830 + my_offset
8831 /* Address of the start of the current section. */
8832 + s->output_section->vma)
8833 /* The branch instruction is 4 bytes into the stub. */
8834 + 4
8835 /* ARM branches work from the pc of the instruction + 8. */
8836 + 8);
252b5132 8837
52ab56c2
PB		 8838 put_arm_insn (globals, output_bfd,
8839 (bfd_vma) t2a3_b_insn | ((ret_offset >> 2) & 0x00FFFFFF),
8840 s->contents + my_offset + 4);
252b5132
RH		 8841 }
8842
8843 BFD_ASSERT (my_offset <= globals->thumb_glue_size);
8844
427bfd90
NC		 8845 /* Now go back and fix up the original BL insn to point to here. */
8846 ret_offset =
8847 /* Address of where the stub is located. */
8848 (s->output_section->vma + s->output_offset + my_offset)
8849 /* Address of where the BL is located. */
57e8b36a
NC		 8850 - (input_section->output_section->vma + input_section->output_offset
8851 + offset)
427bfd90
NC		 8852 /* Addend in the relocation. */
8853 - addend
8854 /* Biassing for PC-relative addressing. */
8855 - 8;
252b5132 8856
12a0a0fd 8857 insert_thumb_branch (input_bfd, ret_offset, hit_data - input_section->vma);
252b5132 8858
b34976b6 8859 return TRUE;
252b5132
RH		 8860}
8861
a4fd1a8e 8862/* Populate an Arm to Thumb stub. Returns the stub symbol. */
9b485d32 8863
a4fd1a8e
PB		 8864static struct elf_link_hash_entry *
8865elf32_arm_create_thumb_stub (struct bfd_link_info * info,
8866 const char * name,
8867 bfd * input_bfd,
8868 bfd * output_bfd,
8869 asection * sym_sec,
8870 bfd_vma val,
8029a119
NC		 8871 asection * s,
8872 char ** error_message)
252b5132 8873{
dc810e39 8874 bfd_vma my_offset;
252b5132 8875 long int ret_offset;
bcbdc74c
NC		 8876 struct elf_link_hash_entry * myh;
8877 struct elf32_arm_link_hash_table * globals;
252b5132 8878
f2a9dd69 8879 myh = find_arm_glue (info, name, error_message);
252b5132 8880 if (myh == NULL)
a4fd1a8e 8881 return NULL;
252b5132
RH		 8882
8883 globals = elf32_arm_hash_table (info);
252b5132
RH		 8884 BFD_ASSERT (globals != NULL);
8885 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
8886
8887 my_offset = myh->root.u.def.value;
252b5132
RH		 8888
8889 if ((my_offset & 0x01) == 0x01)
8890 {
8891 if (sym_sec != NULL
8892 && sym_sec->owner != NULL
8893 && !INTERWORK_FLAG (sym_sec->owner))
8894 {
4eca0228 8895 _bfd_error_handler
d003868e
AM		 8896 (_("%B(%s): warning: interworking not enabled.\n"
8897 " first occurrence: %B: arm call to thumb"),
c08bb8dd 8898 sym_sec->owner, name, input_bfd);
252b5132 8899 }
9b485d32 8900
252b5132
RH		 8901 --my_offset;
8902 myh->root.u.def.value = my_offset;
8903
0e1862bb
L		 8904 if (bfd_link_pic (info)
8905 || globals->root.is_relocatable_executable
27e55c4d 8906 || globals->pic_veneer)
8f6277f5
PB		 8907 {
8908 /* For relocatable objects we can't use absolute addresses,
8909 so construct the address from a relative offset. */
8910 /* TODO: If the offset is small it's probably worth
8911 constructing the address with adds. */
52ab56c2
PB		 8912 put_arm_insn (globals, output_bfd, (bfd_vma) a2t1p_ldr_insn,
8913 s->contents + my_offset);
8914 put_arm_insn (globals, output_bfd, (bfd_vma) a2t2p_add_pc_insn,
8915 s->contents + my_offset + 4);
8916 put_arm_insn (globals, output_bfd, (bfd_vma) a2t3p_bx_r12_insn,
8917 s->contents + my_offset + 8);
8f6277f5
PB		 8918 /* Adjust the offset by 4 for the position of the add,
8919 and 8 for the pipeline offset. */
8920 ret_offset = (val - (s->output_offset
8921 + s->output_section->vma
8922 + my_offset + 12))
8923 | 1;
8924 bfd_put_32 (output_bfd, ret_offset,
8925 s->contents + my_offset + 12);
8926 }
26079076
PB		 8927 else if (globals->use_blx)
8928 {
8929 put_arm_insn (globals, output_bfd, (bfd_vma) a2t1v5_ldr_insn,
8930 s->contents + my_offset);
8931
8932 /* It's a thumb address. Add the low order bit. */
8933 bfd_put_32 (output_bfd, val | a2t2v5_func_addr_insn,
8934 s->contents + my_offset + 4);
8935 }
8f6277f5
PB		 8936 else
8937 {
52ab56c2
PB		 8938 put_arm_insn (globals, output_bfd, (bfd_vma) a2t1_ldr_insn,
8939 s->contents + my_offset);
252b5132 8940
52ab56c2
PB		 8941 put_arm_insn (globals, output_bfd, (bfd_vma) a2t2_bx_r12_insn,
8942 s->contents + my_offset + 4);
252b5132 8943
8f6277f5
PB		 8944 /* It's a thumb address. Add the low order bit. */
8945 bfd_put_32 (output_bfd, val | a2t3_func_addr_insn,
8946 s->contents + my_offset + 8);
8029a119
NC		 8947
8948 my_offset += 12;
8f6277f5 8949 }
252b5132
RH		 8950 }
8951
8952 BFD_ASSERT (my_offset <= globals->arm_glue_size);
8953
a4fd1a8e
PB		 8954 return myh;
8955}
8956
8957/* Arm code calling a Thumb function. */
8958
8959static int
8960elf32_arm_to_thumb_stub (struct bfd_link_info * info,
8961 const char * name,
8962 bfd * input_bfd,
8963 bfd * output_bfd,
8964 asection * input_section,
8965 bfd_byte * hit_data,
8966 asection * sym_sec,
8967 bfd_vma offset,
8968 bfd_signed_vma addend,
f2a9dd69
DJ		 8969 bfd_vma val,
8970 char **error_message)
a4fd1a8e
PB		 8971{
8972 unsigned long int tmp;
8973 bfd_vma my_offset;
8974 asection * s;
8975 long int ret_offset;
8976 struct elf_link_hash_entry * myh;
8977 struct elf32_arm_link_hash_table * globals;
8978
8979 globals = elf32_arm_hash_table (info);
a4fd1a8e
PB		 8980 BFD_ASSERT (globals != NULL);
8981 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
8982
3d4d4302
AM		 8983 s = bfd_get_linker_section (globals->bfd_of_glue_owner,
8984 ARM2THUMB_GLUE_SECTION_NAME);
a4fd1a8e
PB		 8985 BFD_ASSERT (s != NULL);
8986 BFD_ASSERT (s->contents != NULL);
8987 BFD_ASSERT (s->output_section != NULL);
8988
8989 myh = elf32_arm_create_thumb_stub (info, name, input_bfd, output_bfd,
f2a9dd69 8990 sym_sec, val, s, error_message);
a4fd1a8e
PB		 8991 if (!myh)
8992 return FALSE;
8993
8994 my_offset = myh->root.u.def.value;
252b5132
RH		 8995 tmp = bfd_get_32 (input_bfd, hit_data);
8996 tmp = tmp & 0xFF000000;
8997
9b485d32 8998 /* Somehow these are both 4 too far, so subtract 8. */
dc810e39
AM		 8999 ret_offset = (s->output_offset
9000 + my_offset
9001 + s->output_section->vma
9002 - (input_section->output_offset
9003 + input_section->output_section->vma
9004 + offset + addend)
9005 - 8);
9a5aca8c 9006
252b5132
RH		 9007 tmp = tmp | ((ret_offset >> 2) & 0x00FFFFFF);
9008
dc810e39 9009 bfd_put_32 (output_bfd, (bfd_vma) tmp, hit_data - input_section->vma);
252b5132 9010
b34976b6 9011 return TRUE;
252b5132
RH		 9012}
9013
a4fd1a8e
PB		 9014/* Populate Arm stub for an exported Thumb function. */
9015
9016static bfd_boolean
9017elf32_arm_to_thumb_export_stub (struct elf_link_hash_entry *h, void * inf)
9018{
9019 struct bfd_link_info * info = (struct bfd_link_info *) inf;
9020 asection * s;
9021 struct elf_link_hash_entry * myh;
9022 struct elf32_arm_link_hash_entry *eh;
9023 struct elf32_arm_link_hash_table * globals;
9024 asection *sec;
9025 bfd_vma val;
f2a9dd69 9026 char *error_message;
a4fd1a8e 9027
906e58ca 9028 eh = elf32_arm_hash_entry (h);
a4fd1a8e
PB		 9029 /* Allocate stubs for exported Thumb functions on v4t. */
9030 if (eh->export_glue == NULL)
9031 return TRUE;
9032
9033 globals = elf32_arm_hash_table (info);
a4fd1a8e
PB		 9034 BFD_ASSERT (globals != NULL);
9035 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
9036
3d4d4302
AM		 9037 s = bfd_get_linker_section (globals->bfd_of_glue_owner,
9038 ARM2THUMB_GLUE_SECTION_NAME);
a4fd1a8e
PB		 9039 BFD_ASSERT (s != NULL);
9040 BFD_ASSERT (s->contents != NULL);
9041 BFD_ASSERT (s->output_section != NULL);
9042
9043 sec = eh->export_glue->root.u.def.section;
0eaedd0e
PB		 9044
9045 BFD_ASSERT (sec->output_section != NULL);
9046
a4fd1a8e
PB		 9047 val = eh->export_glue->root.u.def.value + sec->output_offset
9048 + sec->output_section->vma;
8029a119 9049
a4fd1a8e
PB		 9050 myh = elf32_arm_create_thumb_stub (info, h->root.root.string,
9051 h->root.u.def.section->owner,
f2a9dd69
DJ		 9052 globals->obfd, sec, val, s,
9053 &error_message);
a4fd1a8e
PB		 9054 BFD_ASSERT (myh);
9055 return TRUE;
9056}
9057
845b51d6
PB		 9058/* Populate ARMv4 BX veneers. Returns the absolute adress of the veneer. */
9059
9060static bfd_vma
9061elf32_arm_bx_glue (struct bfd_link_info * info, int reg)
9062{
9063 bfd_byte *p;
9064 bfd_vma glue_addr;
9065 asection *s;
9066 struct elf32_arm_link_hash_table *globals;
9067
9068 globals = elf32_arm_hash_table (info);
845b51d6
PB		 9069 BFD_ASSERT (globals != NULL);
9070 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
9071
3d4d4302
AM		 9072 s = bfd_get_linker_section (globals->bfd_of_glue_owner,
9073 ARM_BX_GLUE_SECTION_NAME);
845b51d6
PB		 9074 BFD_ASSERT (s != NULL);
9075 BFD_ASSERT (s->contents != NULL);
9076 BFD_ASSERT (s->output_section != NULL);
9077
9078 BFD_ASSERT (globals->bx_glue_offset[reg] & 2);
9079
9080 glue_addr = globals->bx_glue_offset[reg] & ~(bfd_vma)3;
9081
9082 if ((globals->bx_glue_offset[reg] & 1) == 0)
9083 {
9084 p = s->contents + glue_addr;
9085 bfd_put_32 (globals->obfd, armbx1_tst_insn + (reg << 16), p);
9086 bfd_put_32 (globals->obfd, armbx2_moveq_insn + reg, p + 4);
9087 bfd_put_32 (globals->obfd, armbx3_bx_insn + reg, p + 8);
9088 globals->bx_glue_offset[reg] |= 1;
9089 }
9090
9091 return glue_addr + s->output_section->vma + s->output_offset;
9092}
9093
a4fd1a8e
PB		 9094/* Generate Arm stubs for exported Thumb symbols. */
9095static void
906e58ca 9096elf32_arm_begin_write_processing (bfd *abfd ATTRIBUTE_UNUSED,
a4fd1a8e
PB		 9097 struct bfd_link_info *link_info)
9098{
9099 struct elf32_arm_link_hash_table * globals;
9100
8029a119
NC		 9101 if (link_info == NULL)
9102 /* Ignore this if we are not called by the ELF backend linker. */
a4fd1a8e
PB		 9103 return;
9104
9105 globals = elf32_arm_hash_table (link_info);
4dfe6ac6
NC		 9106 if (globals == NULL)
9107 return;
9108
84c08195
PB		 9109 /* If blx is available then exported Thumb symbols are OK and there is
9110 nothing to do. */
a4fd1a8e
PB		 9111 if (globals->use_blx)
9112 return;
9113
9114 elf_link_hash_traverse (&globals->root, elf32_arm_to_thumb_export_stub,
9115 link_info);
9116}
9117
47beaa6a
RS		 9118/* Reserve space for COUNT dynamic relocations in relocation selection
9119 SRELOC. */
9120
9121static void
9122elf32_arm_allocate_dynrelocs (struct bfd_link_info *info, asection *sreloc,
9123 bfd_size_type count)
9124{
9125 struct elf32_arm_link_hash_table *htab;
9126
9127 htab = elf32_arm_hash_table (info);
9128 BFD_ASSERT (htab->root.dynamic_sections_created);
9129 if (sreloc == NULL)
9130 abort ();
9131 sreloc->size += RELOC_SIZE (htab) * count;
9132}
9133
34e77a92
RS		 9134/* Reserve space for COUNT R_ARM_IRELATIVE relocations. If the link is
9135 dynamic, the relocations should go in SRELOC, otherwise they should
9136 go in the special .rel.iplt section. */
9137
9138static void
9139elf32_arm_allocate_irelocs (struct bfd_link_info *info, asection *sreloc,
9140 bfd_size_type count)
9141{
9142 struct elf32_arm_link_hash_table *htab;
9143
9144 htab = elf32_arm_hash_table (info);
9145 if (!htab->root.dynamic_sections_created)
9146 htab->root.irelplt->size += RELOC_SIZE (htab) * count;
9147 else
9148 {
9149 BFD_ASSERT (sreloc != NULL);
9150 sreloc->size += RELOC_SIZE (htab) * count;
9151 }
9152}
9153
47beaa6a
RS		 9154/* Add relocation REL to the end of relocation section SRELOC. */
9155
9156static void
9157elf32_arm_add_dynreloc (bfd *output_bfd, struct bfd_link_info *info,
9158 asection *sreloc, Elf_Internal_Rela *rel)
9159{
9160 bfd_byte *loc;
9161 struct elf32_arm_link_hash_table *htab;
9162
9163 htab = elf32_arm_hash_table (info);
34e77a92
RS		 9164 if (!htab->root.dynamic_sections_created
9165 && ELF32_R_TYPE (rel->r_info) == R_ARM_IRELATIVE)
9166 sreloc = htab->root.irelplt;
47beaa6a
RS		 9167 if (sreloc == NULL)
9168 abort ();
9169 loc = sreloc->contents;
9170 loc += sreloc->reloc_count++ * RELOC_SIZE (htab);
9171 if (sreloc->reloc_count * RELOC_SIZE (htab) > sreloc->size)
9172 abort ();
9173 SWAP_RELOC_OUT (htab) (output_bfd, rel, loc);
9174}
9175
34e77a92
RS		 9176/* Allocate room for a PLT entry described by ROOT_PLT and ARM_PLT.
9177 IS_IPLT_ENTRY says whether the entry belongs to .iplt rather than
9178 to .plt. */
9179
9180static void
9181elf32_arm_allocate_plt_entry (struct bfd_link_info *info,
9182 bfd_boolean is_iplt_entry,
9183 union gotplt_union *root_plt,
9184 struct arm_plt_info *arm_plt)
9185{
9186 struct elf32_arm_link_hash_table *htab;
9187 asection *splt;
9188 asection *sgotplt;
9189
9190 htab = elf32_arm_hash_table (info);
9191
9192 if (is_iplt_entry)
9193 {
9194 splt = htab->root.iplt;
9195 sgotplt = htab->root.igotplt;
9196
99059e56
RM		 9197 /* NaCl uses a special first entry in .iplt too. */
9198 if (htab->nacl_p && splt->size == 0)
9199 splt->size += htab->plt_header_size;
9200
34e77a92
RS		 9201 /* Allocate room for an R_ARM_IRELATIVE relocation in .rel.iplt. */
9202 elf32_arm_allocate_irelocs (info, htab->root.irelplt, 1);
9203 }
9204 else
9205 {
9206 splt = htab->root.splt;
9207 sgotplt = htab->root.sgotplt;
9208
9209 /* Allocate room for an R_JUMP_SLOT relocation in .rel.plt. */
9210 elf32_arm_allocate_dynrelocs (info, htab->root.srelplt, 1);
9211
9212 /* If this is the first .plt entry, make room for the special
9213 first entry. */
9214 if (splt->size == 0)
9215 splt->size += htab->plt_header_size;
9f19ab6d
WN		 9216
9217 htab->next_tls_desc_index++;
34e77a92
RS		 9218 }
9219
9220 /* Allocate the PLT entry itself, including any leading Thumb stub. */
9221 if (elf32_arm_plt_needs_thumb_stub_p (info, arm_plt))
9222 splt->size += PLT_THUMB_STUB_SIZE;
9223 root_plt->offset = splt->size;
9224 splt->size += htab->plt_entry_size;
9225
9226 if (!htab->symbian_p)
9227 {
9228 /* We also need to make an entry in the .got.plt section, which
9229 will be placed in the .got section by the linker script. */
9f19ab6d
WN		 9230 if (is_iplt_entry)
9231 arm_plt->got_offset = sgotplt->size;
9232 else
9233 arm_plt->got_offset = sgotplt->size - 8 * htab->num_tls_desc;
34e77a92
RS		 9234 sgotplt->size += 4;
9235 }
9236}
9237
b38cadfb
NC		 9238static bfd_vma
9239arm_movw_immediate (bfd_vma value)
9240{
9241 return (value & 0x00000fff) | ((value & 0x0000f000) << 4);
9242}
9243
9244static bfd_vma
9245arm_movt_immediate (bfd_vma value)
9246{
9247 return ((value & 0x0fff0000) >> 16) | ((value & 0xf0000000) >> 12);
9248}
9249
34e77a92
RS		 9250/* Fill in a PLT entry and its associated GOT slot. If DYNINDX == -1,
9251 the entry lives in .iplt and resolves to (*SYM_VALUE)().
9252 Otherwise, DYNINDX is the index of the symbol in the dynamic
9253 symbol table and SYM_VALUE is undefined.
9254
9255 ROOT_PLT points to the offset of the PLT entry from the start of its
9256 section (.iplt or .plt). ARM_PLT points to the symbol's ARM-specific
57460bcf 9257 bookkeeping information.
34e77a92 9258
57460bcf
NC		 9259 Returns FALSE if there was a problem. */
9260
9261static bfd_boolean
34e77a92
RS		 9262elf32_arm_populate_plt_entry (bfd *output_bfd, struct bfd_link_info *info,
9263 union gotplt_union *root_plt,
9264 struct arm_plt_info *arm_plt,
9265 int dynindx, bfd_vma sym_value)
9266{
9267 struct elf32_arm_link_hash_table *htab;
9268 asection *sgot;
9269 asection *splt;
9270 asection *srel;
9271 bfd_byte *loc;
9272 bfd_vma plt_index;
9273 Elf_Internal_Rela rel;
9274 bfd_vma plt_header_size;
9275 bfd_vma got_header_size;
9276
9277 htab = elf32_arm_hash_table (info);
9278
9279 /* Pick the appropriate sections and sizes. */
9280 if (dynindx == -1)
9281 {
9282 splt = htab->root.iplt;
9283 sgot = htab->root.igotplt;
9284 srel = htab->root.irelplt;
9285
9286 /* There are no reserved entries in .igot.plt, and no special
9287 first entry in .iplt. */
9288 got_header_size = 0;
9289 plt_header_size = 0;
9290 }
9291 else
9292 {
9293 splt = htab->root.splt;
9294 sgot = htab->root.sgotplt;
9295 srel = htab->root.srelplt;
9296
9297 got_header_size = get_elf_backend_data (output_bfd)->got_header_size;
9298 plt_header_size = htab->plt_header_size;
9299 }
9300 BFD_ASSERT (splt != NULL && srel != NULL);
9301
9302 /* Fill in the entry in the procedure linkage table. */
9303 if (htab->symbian_p)
9304 {
9305 BFD_ASSERT (dynindx >= 0);
9306 put_arm_insn (htab, output_bfd,
9307 elf32_arm_symbian_plt_entry[0],
9308 splt->contents + root_plt->offset);
9309 bfd_put_32 (output_bfd,
9310 elf32_arm_symbian_plt_entry[1],
9311 splt->contents + root_plt->offset + 4);
9312
9313 /* Fill in the entry in the .rel.plt section. */
9314 rel.r_offset = (splt->output_section->vma
9315 + splt->output_offset
9316 + root_plt->offset + 4);
9317 rel.r_info = ELF32_R_INFO (dynindx, R_ARM_GLOB_DAT);
9318
9319 /* Get the index in the procedure linkage table which
9320 corresponds to this symbol. This is the index of this symbol
9321 in all the symbols for which we are making plt entries. The
9322 first entry in the procedure linkage table is reserved. */
9323 plt_index = ((root_plt->offset - plt_header_size)
9324 / htab->plt_entry_size);
9325 }
9326 else
9327 {
9328 bfd_vma got_offset, got_address, plt_address;
9329 bfd_vma got_displacement, initial_got_entry;
9330 bfd_byte * ptr;
9331
9332 BFD_ASSERT (sgot != NULL);
9333
9334 /* Get the offset into the .(i)got.plt table of the entry that
9335 corresponds to this function. */
9336 got_offset = (arm_plt->got_offset & -2);
9337
9338 /* Get the index in the procedure linkage table which
9339 corresponds to this symbol. This is the index of this symbol
9340 in all the symbols for which we are making plt entries.
9341 After the reserved .got.plt entries, all symbols appear in
9342 the same order as in .plt. */
9343 plt_index = (got_offset - got_header_size) / 4;
9344
9345 /* Calculate the address of the GOT entry. */
9346 got_address = (sgot->output_section->vma
9347 + sgot->output_offset
9348 + got_offset);
9349
9350 /* ...and the address of the PLT entry. */
9351 plt_address = (splt->output_section->vma
9352 + splt->output_offset
9353 + root_plt->offset);
9354
9355 ptr = splt->contents + root_plt->offset;
0e1862bb 9356 if (htab->vxworks_p && bfd_link_pic (info))
34e77a92
RS		 9357 {
9358 unsigned int i;
9359 bfd_vma val;
9360
9361 for (i = 0; i != htab->plt_entry_size / 4; i++, ptr += 4)
9362 {
9363 val = elf32_arm_vxworks_shared_plt_entry[i];
9364 if (i == 2)
9365 val |= got_address - sgot->output_section->vma;
9366 if (i == 5)
9367 val |= plt_index * RELOC_SIZE (htab);
9368 if (i == 2 || i == 5)
9369 bfd_put_32 (output_bfd, val, ptr);
9370 else
9371 put_arm_insn (htab, output_bfd, val, ptr);
9372 }
9373 }
9374 else if (htab->vxworks_p)
9375 {
9376 unsigned int i;
9377 bfd_vma val;
9378
9379 for (i = 0; i != htab->plt_entry_size / 4; i++, ptr += 4)
9380 {
9381 val = elf32_arm_vxworks_exec_plt_entry[i];
9382 if (i == 2)
9383 val |= got_address;
9384 if (i == 4)
9385 val |= 0xffffff & -((root_plt->offset + i * 4 + 8) >> 2);
9386 if (i == 5)
9387 val |= plt_index * RELOC_SIZE (htab);
9388 if (i == 2 || i == 5)
9389 bfd_put_32 (output_bfd, val, ptr);
9390 else
9391 put_arm_insn (htab, output_bfd, val, ptr);
9392 }
9393
9394 loc = (htab->srelplt2->contents
9395 + (plt_index * 2 + 1) * RELOC_SIZE (htab));
9396
9397 /* Create the .rela.plt.unloaded R_ARM_ABS32 relocation
9398 referencing the GOT for this PLT entry. */
9399 rel.r_offset = plt_address + 8;
9400 rel.r_info = ELF32_R_INFO (htab->root.hgot->indx, R_ARM_ABS32);
9401 rel.r_addend = got_offset;
9402 SWAP_RELOC_OUT (htab) (output_bfd, &rel, loc);
9403 loc += RELOC_SIZE (htab);
9404
9405 /* Create the R_ARM_ABS32 relocation referencing the
9406 beginning of the PLT for this GOT entry. */
9407 rel.r_offset = got_address;
9408 rel.r_info = ELF32_R_INFO (htab->root.hplt->indx, R_ARM_ABS32);
9409 rel.r_addend = 0;
9410 SWAP_RELOC_OUT (htab) (output_bfd, &rel, loc);
9411 }
b38cadfb
NC		 9412 else if (htab->nacl_p)
9413 {
9414 /* Calculate the displacement between the PLT slot and the
9415 common tail that's part of the special initial PLT slot. */
6034aab8 9416 int32_t tail_displacement
b38cadfb
NC		 9417 = ((splt->output_section->vma + splt->output_offset
9418 + ARM_NACL_PLT_TAIL_OFFSET)
9419 - (plt_address + htab->plt_entry_size + 4));
9420 BFD_ASSERT ((tail_displacement & 3) == 0);
9421 tail_displacement >>= 2;
9422
9423 BFD_ASSERT ((tail_displacement & 0xff000000) == 0
9424 || (-tail_displacement & 0xff000000) == 0);
9425
9426 /* Calculate the displacement between the PLT slot and the entry
9427 in the GOT. The offset accounts for the value produced by
9428 adding to pc in the penultimate instruction of the PLT stub. */
6034aab8 9429 got_displacement = (got_address
99059e56 9430 - (plt_address + htab->plt_entry_size));
b38cadfb
NC		 9431
9432 /* NaCl does not support interworking at all. */
9433 BFD_ASSERT (!elf32_arm_plt_needs_thumb_stub_p (info, arm_plt));
9434
9435 put_arm_insn (htab, output_bfd,
9436 elf32_arm_nacl_plt_entry[0]
9437 | arm_movw_immediate (got_displacement),
9438 ptr + 0);
9439 put_arm_insn (htab, output_bfd,
9440 elf32_arm_nacl_plt_entry[1]
9441 | arm_movt_immediate (got_displacement),
9442 ptr + 4);
9443 put_arm_insn (htab, output_bfd,
9444 elf32_arm_nacl_plt_entry[2],
9445 ptr + 8);
9446 put_arm_insn (htab, output_bfd,
9447 elf32_arm_nacl_plt_entry[3]
9448 | (tail_displacement & 0x00ffffff),
9449 ptr + 12);
9450 }
57460bcf
NC		 9451 else if (using_thumb_only (htab))
9452 {
eed94f8f 9453 /* PR ld/16017: Generate thumb only PLT entries. */
469a3493 9454 if (!using_thumb2 (htab))
eed94f8f
NC		 9455 {
9456 /* FIXME: We ought to be able to generate thumb-1 PLT
9457 instructions... */
9458 _bfd_error_handler (_("%B: Warning: thumb-1 mode PLT generation not currently supported"),
9459 output_bfd);
9460 return FALSE;
9461 }
57460bcf 9462
eed94f8f
NC		 9463 /* Calculate the displacement between the PLT slot and the entry in
9464 the GOT. The 12-byte offset accounts for the value produced by
9465 adding to pc in the 3rd instruction of the PLT stub. */
9466 got_displacement = got_address - (plt_address + 12);
9467
9468 /* As we are using 32 bit instructions we have to use 'put_arm_insn'
9469 instead of 'put_thumb_insn'. */
9470 put_arm_insn (htab, output_bfd,
9471 elf32_thumb2_plt_entry[0]
9472 | ((got_displacement & 0x000000ff) << 16)
9473 | ((got_displacement & 0x00000700) << 20)
9474 | ((got_displacement & 0x00000800) >> 1)
9475 | ((got_displacement & 0x0000f000) >> 12),
9476 ptr + 0);
9477 put_arm_insn (htab, output_bfd,
9478 elf32_thumb2_plt_entry[1]
9479 | ((got_displacement & 0x00ff0000) )
9480 | ((got_displacement & 0x07000000) << 4)
9481 | ((got_displacement & 0x08000000) >> 17)
9482 | ((got_displacement & 0xf0000000) >> 28),
9483 ptr + 4);
9484 put_arm_insn (htab, output_bfd,
9485 elf32_thumb2_plt_entry[2],
9486 ptr + 8);
9487 put_arm_insn (htab, output_bfd,
9488 elf32_thumb2_plt_entry[3],
9489 ptr + 12);
57460bcf 9490 }
34e77a92
RS		 9491 else
9492 {
9493 /* Calculate the displacement between the PLT slot and the
9494 entry in the GOT. The eight-byte offset accounts for the
9495 value produced by adding to pc in the first instruction
9496 of the PLT stub. */
9497 got_displacement = got_address - (plt_address + 8);
9498
34e77a92
RS		 9499 if (elf32_arm_plt_needs_thumb_stub_p (info, arm_plt))
9500 {
9501 put_thumb_insn (htab, output_bfd,
9502 elf32_arm_plt_thumb_stub[0], ptr - 4);
9503 put_thumb_insn (htab, output_bfd,
9504 elf32_arm_plt_thumb_stub[1], ptr - 2);
9505 }
9506
1db37fe6
YG		 9507 if (!elf32_arm_use_long_plt_entry)
9508 {
9509 BFD_ASSERT ((got_displacement & 0xf0000000) == 0);
9510
9511 put_arm_insn (htab, output_bfd,
9512 elf32_arm_plt_entry_short[0]
9513 | ((got_displacement & 0x0ff00000) >> 20),
9514 ptr + 0);
9515 put_arm_insn (htab, output_bfd,
9516 elf32_arm_plt_entry_short[1]
9517 | ((got_displacement & 0x000ff000) >> 12),
9518 ptr+ 4);
9519 put_arm_insn (htab, output_bfd,
9520 elf32_arm_plt_entry_short[2]
9521 | (got_displacement & 0x00000fff),
9522 ptr + 8);
34e77a92 9523#ifdef FOUR_WORD_PLT
1db37fe6 9524 bfd_put_32 (output_bfd, elf32_arm_plt_entry_short[3], ptr + 12);
34e77a92 9525#endif
1db37fe6
YG		 9526 }
9527 else
9528 {
9529 put_arm_insn (htab, output_bfd,
9530 elf32_arm_plt_entry_long[0]
9531 | ((got_displacement & 0xf0000000) >> 28),
9532 ptr + 0);
9533 put_arm_insn (htab, output_bfd,
9534 elf32_arm_plt_entry_long[1]
9535 | ((got_displacement & 0x0ff00000) >> 20),
9536 ptr + 4);
9537 put_arm_insn (htab, output_bfd,
9538 elf32_arm_plt_entry_long[2]
9539 | ((got_displacement & 0x000ff000) >> 12),
9540 ptr+ 8);
9541 put_arm_insn (htab, output_bfd,
9542 elf32_arm_plt_entry_long[3]
9543 | (got_displacement & 0x00000fff),
9544 ptr + 12);
9545 }
34e77a92
RS		 9546 }
9547
9548 /* Fill in the entry in the .rel(a).(i)plt section. */
9549 rel.r_offset = got_address;
9550 rel.r_addend = 0;
9551 if (dynindx == -1)
9552 {
9553 /* .igot.plt entries use IRELATIVE relocations against SYM_VALUE.
9554 The dynamic linker or static executable then calls SYM_VALUE
9555 to determine the correct run-time value of the .igot.plt entry. */
9556 rel.r_info = ELF32_R_INFO (0, R_ARM_IRELATIVE);
9557 initial_got_entry = sym_value;
9558 }
9559 else
9560 {
9561 rel.r_info = ELF32_R_INFO (dynindx, R_ARM_JUMP_SLOT);
9562 initial_got_entry = (splt->output_section->vma
9563 + splt->output_offset);
9564 }
9565
9566 /* Fill in the entry in the global offset table. */
9567 bfd_put_32 (output_bfd, initial_got_entry,
9568 sgot->contents + got_offset);
9569 }
9570
aba8c3de
WN		 9571 if (dynindx == -1)
9572 elf32_arm_add_dynreloc (output_bfd, info, srel, &rel);
9573 else
9574 {
9575 loc = srel->contents + plt_index * RELOC_SIZE (htab);
9576 SWAP_RELOC_OUT (htab) (output_bfd, &rel, loc);
9577 }
57460bcf
NC		 9578
9579 return TRUE;
34e77a92
RS		 9580}
9581
eb043451
PB		 9582/* Some relocations map to different relocations depending on the
9583 target. Return the real relocation. */
8029a119 9584
eb043451
PB		 9585static int
9586arm_real_reloc_type (struct elf32_arm_link_hash_table * globals,
9587 int r_type)
9588{
9589 switch (r_type)
9590 {
9591 case R_ARM_TARGET1:
9592 if (globals->target1_is_rel)
9593 return R_ARM_REL32;
9594 else
9595 return R_ARM_ABS32;
9596
9597 case R_ARM_TARGET2:
9598 return globals->target2_reloc;
9599
9600 default:
9601 return r_type;
9602 }
9603}
eb043451 9604
ba93b8ac
DJ		 9605/* Return the base VMA address which should be subtracted from real addresses
9606 when resolving @dtpoff relocation.
9607 This is PT_TLS segment p_vaddr. */
9608
9609static bfd_vma
9610dtpoff_base (struct bfd_link_info *info)
9611{
9612 /* If tls_sec is NULL, we should have signalled an error already. */
9613 if (elf_hash_table (info)->tls_sec == NULL)
9614 return 0;
9615 return elf_hash_table (info)->tls_sec->vma;
9616}
9617
9618/* Return the relocation value for @tpoff relocation
9619 if STT_TLS virtual address is ADDRESS. */
9620
9621static bfd_vma
9622tpoff (struct bfd_link_info *info, bfd_vma address)
9623{
9624 struct elf_link_hash_table *htab = elf_hash_table (info);
9625 bfd_vma base;
9626
9627 /* If tls_sec is NULL, we should have signalled an error already. */
9628 if (htab->tls_sec == NULL)
9629 return 0;
9630 base = align_power ((bfd_vma) TCB_SIZE, htab->tls_sec->alignment_power);
9631 return address - htab->tls_sec->vma + base;
9632}
9633
00a97672
RS		 9634/* Perform an R_ARM_ABS12 relocation on the field pointed to by DATA.
9635 VALUE is the relocation value. */
9636
9637static bfd_reloc_status_type
9638elf32_arm_abs12_reloc (bfd *abfd, void *data, bfd_vma value)
9639{
9640 if (value > 0xfff)
9641 return bfd_reloc_overflow;
9642
9643 value |= bfd_get_32 (abfd, data) & 0xfffff000;
9644 bfd_put_32 (abfd, value, data);
9645 return bfd_reloc_ok;
9646}
9647
0855e32b
NS		 9648/* Handle TLS relaxations. Relaxing is possible for symbols that use
9649 R_ARM_GOTDESC, R_ARM_{,THM_}TLS_CALL or
9650 R_ARM_{,THM_}TLS_DESCSEQ relocations, during a static link.
9651
9652 Return bfd_reloc_ok if we're done, bfd_reloc_continue if the caller
9653 is to then call final_link_relocate. Return other values in the
62672b10
NS		 9654 case of error.
9655
9656 FIXME:When --emit-relocs is in effect, we'll emit relocs describing
9657 the pre-relaxed code. It would be nice if the relocs were updated
9658 to match the optimization. */
0855e32b 9659
b38cadfb 9660static bfd_reloc_status_type
0855e32b 9661elf32_arm_tls_relax (struct elf32_arm_link_hash_table *globals,
b38cadfb 9662 bfd *input_bfd, asection *input_sec, bfd_byte *contents,
0855e32b
NS		 9663 Elf_Internal_Rela *rel, unsigned long is_local)
9664{
9665 unsigned long insn;
b38cadfb 9666
0855e32b
NS		 9667 switch (ELF32_R_TYPE (rel->r_info))
9668 {
9669 default:
9670 return bfd_reloc_notsupported;
b38cadfb 9671
0855e32b
NS		 9672 case R_ARM_TLS_GOTDESC:
9673 if (is_local)
9674 insn = 0;
9675 else
9676 {
9677 insn = bfd_get_32 (input_bfd, contents + rel->r_offset);
9678 if (insn & 1)
9679 insn -= 5; /* THUMB */
9680 else
9681 insn -= 8; /* ARM */
9682 }
9683 bfd_put_32 (input_bfd, insn, contents + rel->r_offset);
9684 return bfd_reloc_continue;
9685
9686 case R_ARM_THM_TLS_DESCSEQ:
9687 /* Thumb insn. */
9688 insn = bfd_get_16 (input_bfd, contents + rel->r_offset);
9689 if ((insn & 0xff78) == 0x4478) /* add rx, pc */
9690 {
9691 if (is_local)
9692 /* nop */
9693 bfd_put_16 (input_bfd, 0x46c0, contents + rel->r_offset);
9694 }
9695 else if ((insn & 0xffc0) == 0x6840) /* ldr rx,[ry,#4] */
9696 {
9697 if (is_local)
9698 /* nop */
9699 bfd_put_16 (input_bfd, 0x46c0, contents + rel->r_offset);
9700 else
9701 /* ldr rx,[ry] */
9702 bfd_put_16 (input_bfd, insn & 0xf83f, contents + rel->r_offset);
9703 }
9704 else if ((insn & 0xff87) == 0x4780) /* blx rx */
9705 {
9706 if (is_local)
9707 /* nop */
9708 bfd_put_16 (input_bfd, 0x46c0, contents + rel->r_offset);
9709 else
9710 /* mov r0, rx */
9711 bfd_put_16 (input_bfd, 0x4600 | (insn & 0x78),
9712 contents + rel->r_offset);
9713 }
9714 else
9715 {
9716 if ((insn & 0xf000) == 0xf000 || (insn & 0xf800) == 0xe800)
9717 /* It's a 32 bit instruction, fetch the rest of it for
9718 error generation. */
9719 insn = (insn << 16)
9720 | bfd_get_16 (input_bfd, contents + rel->r_offset + 2);
4eca0228 9721 _bfd_error_handler
695344c0
NC		 9722 /* xgettext:c-format */
9723 (_("%B(%A+0x%lx): unexpected Thumb instruction '0x%x' in TLS trampoline"),
0855e32b
NS		 9724 input_bfd, input_sec, (unsigned long)rel->r_offset, insn);
9725 return bfd_reloc_notsupported;
9726 }
9727 break;
b38cadfb 9728
0855e32b
NS		 9729 case R_ARM_TLS_DESCSEQ:
9730 /* arm insn. */
9731 insn = bfd_get_32 (input_bfd, contents + rel->r_offset);
9732 if ((insn & 0xffff0ff0) == 0xe08f0000) /* add rx,pc,ry */
9733 {
9734 if (is_local)
9735 /* mov rx, ry */
9736 bfd_put_32 (input_bfd, 0xe1a00000 | (insn & 0xffff),
9737 contents + rel->r_offset);
9738 }
9739 else if ((insn & 0xfff00fff) == 0xe5900004) /* ldr rx,[ry,#4]*/
9740 {
9741 if (is_local)
9742 /* nop */
9743 bfd_put_32 (input_bfd, 0xe1a00000, contents + rel->r_offset);
9744 else
9745 /* ldr rx,[ry] */
9746 bfd_put_32 (input_bfd, insn & 0xfffff000,
9747 contents + rel->r_offset);
9748 }
9749 else if ((insn & 0xfffffff0) == 0xe12fff30) /* blx rx */
9750 {
9751 if (is_local)
9752 /* nop */
9753 bfd_put_32 (input_bfd, 0xe1a00000, contents + rel->r_offset);
9754 else
9755 /* mov r0, rx */
9756 bfd_put_32 (input_bfd, 0xe1a00000 | (insn & 0xf),
9757 contents + rel->r_offset);
9758 }
9759 else
9760 {
4eca0228 9761 _bfd_error_handler
695344c0
NC		 9762 /* xgettext:c-format */
9763 (_("%B(%A+0x%lx): unexpected ARM instruction '0x%x' in TLS trampoline"),
0855e32b
NS		 9764 input_bfd, input_sec, (unsigned long)rel->r_offset, insn);
9765 return bfd_reloc_notsupported;
9766 }
9767 break;
9768
9769 case R_ARM_TLS_CALL:
9770 /* GD->IE relaxation, turn the instruction into 'nop' or
9771 'ldr r0, [pc,r0]' */
9772 insn = is_local ? 0xe1a00000 : 0xe79f0000;
9773 bfd_put_32 (input_bfd, insn, contents + rel->r_offset);
9774 break;
b38cadfb 9775
0855e32b 9776 case R_ARM_THM_TLS_CALL:
6a631e86 9777 /* GD->IE relaxation. */
0855e32b
NS		 9778 if (!is_local)
9779 /* add r0,pc; ldr r0, [r0] */
9780 insn = 0x44786800;
60a019a0 9781 else if (using_thumb2 (globals))
0855e32b
NS		 9782 /* nop.w */
9783 insn = 0xf3af8000;
9784 else
9785 /* nop; nop */
9786 insn = 0xbf00bf00;
b38cadfb 9787
0855e32b
NS		 9788 bfd_put_16 (input_bfd, insn >> 16, contents + rel->r_offset);
9789 bfd_put_16 (input_bfd, insn & 0xffff, contents + rel->r_offset + 2);
9790 break;
9791 }
9792 return bfd_reloc_ok;
9793}
9794
4962c51a
MS		 9795/* For a given value of n, calculate the value of G_n as required to
9796 deal with group relocations. We return it in the form of an
9797 encoded constant-and-rotation, together with the final residual. If n is
9798 specified as less than zero, then final_residual is filled with the
9799 input value and no further action is performed. */
9800
9801static bfd_vma
9802calculate_group_reloc_mask (bfd_vma value, int n, bfd_vma *final_residual)
9803{
9804 int current_n;
9805 bfd_vma g_n;
9806 bfd_vma encoded_g_n = 0;
9807 bfd_vma residual = value; /* Also known as Y_n. */
9808
9809 for (current_n = 0; current_n <= n; current_n++)
9810 {
9811 int shift;
9812
9813 /* Calculate which part of the value to mask. */
9814 if (residual == 0)
99059e56 9815 shift = 0;
4962c51a 9816 else
99059e56
RM		 9817 {
9818 int msb;
9819
9820 /* Determine the most significant bit in the residual and
9821 align the resulting value to a 2-bit boundary. */
9822 for (msb = 30; msb >= 0; msb -= 2)
9823 if (residual & (3 << msb))
9824 break;
9825
9826 /* The desired shift is now (msb - 6), or zero, whichever
9827 is the greater. */
9828 shift = msb - 6;
9829 if (shift < 0)
9830 shift = 0;
9831 }
4962c51a
MS		 9832
9833 /* Calculate g_n in 32-bit as well as encoded constant+rotation form. */
9834 g_n = residual & (0xff << shift);
9835 encoded_g_n = (g_n >> shift)
99059e56 9836 | ((g_n <= 0xff ? 0 : (32 - shift) / 2) << 8);
4962c51a
MS		 9837
9838 /* Calculate the residual for the next time around. */
9839 residual &= ~g_n;
9840 }
9841
9842 *final_residual = residual;
9843
9844 return encoded_g_n;
9845}
9846
9847/* Given an ARM instruction, determine whether it is an ADD or a SUB.
9848 Returns 1 if it is an ADD, -1 if it is a SUB, and 0 otherwise. */
906e58ca 9849
4962c51a 9850static int
906e58ca 9851identify_add_or_sub (bfd_vma insn)
4962c51a
MS		 9852{
9853 int opcode = insn & 0x1e00000;
9854
9855 if (opcode == 1 << 23) /* ADD */
9856 return 1;
9857
9858 if (opcode == 1 << 22) /* SUB */
9859 return -1;
9860
9861 return 0;
9862}
9863
252b5132 9864/* Perform a relocation as part of a final link. */
9b485d32 9865
252b5132 9866static bfd_reloc_status_type
57e8b36a
NC		 9867elf32_arm_final_link_relocate (reloc_howto_type * howto,
9868 bfd * input_bfd,
9869 bfd * output_bfd,
9870 asection * input_section,
9871 bfd_byte * contents,
9872 Elf_Internal_Rela * rel,
9873 bfd_vma value,
9874 struct bfd_link_info * info,
9875 asection * sym_sec,
9876 const char * sym_name,
34e77a92
RS		 9877 unsigned char st_type,
9878 enum arm_st_branch_type branch_type,
0945cdfd 9879 struct elf_link_hash_entry * h,
f2a9dd69 9880 bfd_boolean * unresolved_reloc_p,
8029a119 9881 char ** error_message)
252b5132
RH		 9882{
9883 unsigned long r_type = howto->type;
9884 unsigned long r_symndx;
9885 bfd_byte * hit_data = contents + rel->r_offset;
252b5132 9886 bfd_vma * local_got_offsets;
0855e32b 9887 bfd_vma * local_tlsdesc_gotents;
34e77a92
RS		 9888 asection * sgot;
9889 asection * splt;
252b5132 9890 asection * sreloc = NULL;
362d30a1 9891 asection * srelgot;
252b5132 9892 bfd_vma addend;
ba96a88f 9893 bfd_signed_vma signed_addend;
34e77a92
RS		 9894 unsigned char dynreloc_st_type;
9895 bfd_vma dynreloc_value;
ba96a88f 9896 struct elf32_arm_link_hash_table * globals;
34e77a92
RS		 9897 struct elf32_arm_link_hash_entry *eh;
9898 union gotplt_union *root_plt;
9899 struct arm_plt_info *arm_plt;
9900 bfd_vma plt_offset;
9901 bfd_vma gotplt_offset;
9902 bfd_boolean has_iplt_entry;
f21f3fe0 9903
9c504268 9904 globals = elf32_arm_hash_table (info);
4dfe6ac6
NC		 9905 if (globals == NULL)
9906 return bfd_reloc_notsupported;
9c504268 9907
0ffa91dd
NC		 9908 BFD_ASSERT (is_arm_elf (input_bfd));
9909
9910 /* Some relocation types map to different relocations depending on the
9c504268 9911 target. We pick the right one here. */
eb043451 9912 r_type = arm_real_reloc_type (globals, r_type);
0855e32b
NS		 9913
9914 /* It is possible to have linker relaxations on some TLS access
9915 models. Update our information here. */
9916 r_type = elf32_arm_tls_transition (info, r_type, h);
9917
eb043451
PB		 9918 if (r_type != howto->type)
9919 howto = elf32_arm_howto_from_type (r_type);
9c504268 9920
34e77a92 9921 eh = (struct elf32_arm_link_hash_entry *) h;
362d30a1 9922 sgot = globals->root.sgot;
252b5132 9923 local_got_offsets = elf_local_got_offsets (input_bfd);
0855e32b
NS		 9924 local_tlsdesc_gotents = elf32_arm_local_tlsdesc_gotent (input_bfd);
9925
34e77a92
RS		 9926 if (globals->root.dynamic_sections_created)
9927 srelgot = globals->root.srelgot;
9928 else
9929 srelgot = NULL;
9930
252b5132
RH		 9931 r_symndx = ELF32_R_SYM (rel->r_info);
9932
4e7fd91e 9933 if (globals->use_rel)
ba96a88f 9934 {
4e7fd91e
PB		 9935 addend = bfd_get_32 (input_bfd, hit_data) & howto->src_mask;
9936
9937 if (addend & ((howto->src_mask + 1) >> 1))
9938 {
9939 signed_addend = -1;
9940 signed_addend &= ~ howto->src_mask;
9941 signed_addend |= addend;
9942 }
9943 else
9944 signed_addend = addend;
ba96a88f
NC		 9945 }
9946 else
4e7fd91e 9947 addend = signed_addend = rel->r_addend;
f21f3fe0 9948
39f21624
NC		 9949 /* ST_BRANCH_TO_ARM is nonsense to thumb-only targets when we
9950 are resolving a function call relocation. */
9951 if (using_thumb_only (globals)
9952 && (r_type == R_ARM_THM_CALL
9953 || r_type == R_ARM_THM_JUMP24)
9954 && branch_type == ST_BRANCH_TO_ARM)
9955 branch_type = ST_BRANCH_TO_THUMB;
9956
34e77a92
RS		 9957 /* Record the symbol information that should be used in dynamic
9958 relocations. */
9959 dynreloc_st_type = st_type;
9960 dynreloc_value = value;
9961 if (branch_type == ST_BRANCH_TO_THUMB)
9962 dynreloc_value |= 1;
9963
9964 /* Find out whether the symbol has a PLT. Set ST_VALUE, BRANCH_TYPE and
9965 VALUE appropriately for relocations that we resolve at link time. */
9966 has_iplt_entry = FALSE;
4ba2ef8f
TP		 9967 if (elf32_arm_get_plt_info (input_bfd, globals, eh, r_symndx, &root_plt,
9968 &arm_plt)
34e77a92
RS		 9969 && root_plt->offset != (bfd_vma) -1)
9970 {
9971 plt_offset = root_plt->offset;
9972 gotplt_offset = arm_plt->got_offset;
9973
9974 if (h == NULL || eh->is_iplt)
9975 {
9976 has_iplt_entry = TRUE;
9977 splt = globals->root.iplt;
9978
9979 /* Populate .iplt entries here, because not all of them will
9980 be seen by finish_dynamic_symbol. The lower bit is set if
9981 we have already populated the entry. */
9982 if (plt_offset & 1)
9983 plt_offset--;
9984 else
9985 {
57460bcf
NC		 9986 if (elf32_arm_populate_plt_entry (output_bfd, info, root_plt, arm_plt,
9987 -1, dynreloc_value))
9988 root_plt->offset |= 1;
9989 else
9990 return bfd_reloc_notsupported;
34e77a92
RS		 9991 }
9992
9993 /* Static relocations always resolve to the .iplt entry. */
9994 st_type = STT_FUNC;
9995 value = (splt->output_section->vma
9996 + splt->output_offset
9997 + plt_offset);
9998 branch_type = ST_BRANCH_TO_ARM;
9999
10000 /* If there are non-call relocations that resolve to the .iplt
10001 entry, then all dynamic ones must too. */
10002 if (arm_plt->noncall_refcount != 0)
10003 {
10004 dynreloc_st_type = st_type;
10005 dynreloc_value = value;
10006 }
10007 }
10008 else
10009 /* We populate the .plt entry in finish_dynamic_symbol. */
10010 splt = globals->root.splt;
10011 }
10012 else
10013 {
10014 splt = NULL;
10015 plt_offset = (bfd_vma) -1;
10016 gotplt_offset = (bfd_vma) -1;
10017 }
10018
252b5132
RH		 10019 switch (r_type)
10020 {
10021 case R_ARM_NONE:
28a094c2
DJ		 10022 /* We don't need to find a value for this symbol. It's just a
10023 marker. */
10024 *unresolved_reloc_p = FALSE;
252b5132
RH		 10025 return bfd_reloc_ok;
10026
00a97672
RS		 10027 case R_ARM_ABS12:
10028 if (!globals->vxworks_p)
10029 return elf32_arm_abs12_reloc (input_bfd, hit_data, value + addend);
1a0670f3 10030 /* Fall through. */
00a97672 10031
252b5132
RH		 10032 case R_ARM_PC24:
10033 case R_ARM_ABS32:
bb224fc3 10034 case R_ARM_ABS32_NOI:
252b5132 10035 case R_ARM_REL32:
bb224fc3 10036 case R_ARM_REL32_NOI:
5b5bb741
PB		 10037 case R_ARM_CALL:
10038 case R_ARM_JUMP24:
dfc5f959 10039 case R_ARM_XPC25:
eb043451 10040 case R_ARM_PREL31:
7359ea65 10041 case R_ARM_PLT32:
7359ea65
DJ		 10042 /* Handle relocations which should use the PLT entry. ABS32/REL32
10043 will use the symbol's value, which may point to a PLT entry, but we
10044 don't need to handle that here. If we created a PLT entry, all
5fa9e92f
CL		 10045 branches in this object should go to it, except if the PLT is too
10046 far away, in which case a long branch stub should be inserted. */
bb224fc3 10047 if ((r_type != R_ARM_ABS32 && r_type != R_ARM_REL32
99059e56 10048 && r_type != R_ARM_ABS32_NOI && r_type != R_ARM_REL32_NOI
155d87d7
CL		 10049 && r_type != R_ARM_CALL
10050 && r_type != R_ARM_JUMP24
10051 && r_type != R_ARM_PLT32)
34e77a92 10052 && plt_offset != (bfd_vma) -1)
7359ea65 10053 {
34e77a92
RS		 10054 /* If we've created a .plt section, and assigned a PLT entry
10055 to this function, it must either be a STT_GNU_IFUNC reference
10056 or not be known to bind locally. In other cases, we should
10057 have cleared the PLT entry by now. */
10058 BFD_ASSERT (has_iplt_entry || !SYMBOL_CALLS_LOCAL (info, h));
7359ea65
DJ		 10059
10060 value = (splt->output_section->vma
10061 + splt->output_offset
34e77a92 10062 + plt_offset);
0945cdfd 10063 *unresolved_reloc_p = FALSE;
7359ea65
DJ		 10064 return _bfd_final_link_relocate (howto, input_bfd, input_section,
10065 contents, rel->r_offset, value,
00a97672 10066 rel->r_addend);
7359ea65
DJ		 10067 }
10068
67687978
PB		 10069 /* When generating a shared object or relocatable executable, these
10070 relocations are copied into the output file to be resolved at
10071 run time. */
0e1862bb
L		 10072 if ((bfd_link_pic (info)
10073 || globals->root.is_relocatable_executable)
7359ea65 10074 && (input_section->flags & SEC_ALLOC)
4dfe6ac6 10075 && !(globals->vxworks_p
3348747a
NS		 10076 && strcmp (input_section->output_section->name,
10077 ".tls_vars") == 0)
bb224fc3 10078 && ((r_type != R_ARM_REL32 && r_type != R_ARM_REL32_NOI)
ee06dc07 10079 || !SYMBOL_CALLS_LOCAL (info, h))
ca6b5f82
AM		 10080 && !(input_bfd == globals->stub_bfd
10081 && strstr (input_section->name, STUB_SUFFIX))
7359ea65
DJ		 10082 && (h == NULL
10083 || ELF_ST_VISIBILITY (h->other) == STV_DEFAULT
10084 || h->root.type != bfd_link_hash_undefweak)
10085 && r_type != R_ARM_PC24
5b5bb741
PB		 10086 && r_type != R_ARM_CALL
10087 && r_type != R_ARM_JUMP24
ee06dc07 10088 && r_type != R_ARM_PREL31
7359ea65 10089 && r_type != R_ARM_PLT32)
252b5132 10090 {
947216bf 10091 Elf_Internal_Rela outrel;
b34976b6 10092 bfd_boolean skip, relocate;
f21f3fe0 10093
52db4ec2
JW		 10094 if ((r_type == R_ARM_REL32 || r_type == R_ARM_REL32_NOI)
10095 && !h->def_regular)
10096 {
10097 char *v = _("shared object");
10098
0e1862bb 10099 if (bfd_link_executable (info))
52db4ec2
JW		 10100 v = _("PIE executable");
10101
4eca0228 10102 _bfd_error_handler
52db4ec2
JW		 10103 (_("%B: relocation %s against external or undefined symbol `%s'"
10104 " can not be used when making a %s; recompile with -fPIC"), input_bfd,
10105 elf32_arm_howto_table_1[r_type].name, h->root.root.string, v);
10106 return bfd_reloc_notsupported;
10107 }
10108
0945cdfd
DJ		 10109 *unresolved_reloc_p = FALSE;
10110
34e77a92 10111 if (sreloc == NULL && globals->root.dynamic_sections_created)
252b5132 10112 {
83bac4b0
NC		 10113 sreloc = _bfd_elf_get_dynamic_reloc_section (input_bfd, input_section,
10114 ! globals->use_rel);
f21f3fe0 10115
83bac4b0 10116 if (sreloc == NULL)
252b5132 10117 return bfd_reloc_notsupported;
252b5132 10118 }
f21f3fe0 10119
b34976b6
AM		 10120 skip = FALSE;
10121 relocate = FALSE;
f21f3fe0 10122
00a97672 10123 outrel.r_addend = addend;
c629eae0
JJ		 10124 outrel.r_offset =
10125 _bfd_elf_section_offset (output_bfd, info, input_section,
10126 rel->r_offset);
10127 if (outrel.r_offset == (bfd_vma) -1)
b34976b6 10128 skip = TRUE;
0bb2d96a 10129 else if (outrel.r_offset == (bfd_vma) -2)
b34976b6 10130 skip = TRUE, relocate = TRUE;
252b5132
RH		 10131 outrel.r_offset += (input_section->output_section->vma
10132 + input_section->output_offset);
f21f3fe0 10133
252b5132 10134 if (skip)
0bb2d96a 10135 memset (&outrel, 0, sizeof outrel);
5e681ec4
PB		 10136 else if (h != NULL
10137 && h->dynindx != -1
0e1862bb 10138 && (!bfd_link_pic (info)
1dcb9720
JW		 10139 || !(bfd_link_pie (info)
10140 || SYMBOLIC_BIND (info, h))
f5385ebf 10141 || !h->def_regular))
5e681ec4 10142 outrel.r_info = ELF32_R_INFO (h->dynindx, r_type);
252b5132
RH		 10143 else
10144 {
a16385dc
MM		 10145 int symbol;
10146
5e681ec4 10147 /* This symbol is local, or marked to become local. */
34e77a92 10148 BFD_ASSERT (r_type == R_ARM_ABS32 || r_type == R_ARM_ABS32_NOI);
a16385dc 10149 if (globals->symbian_p)
6366ff1e 10150 {
74541ad4
AM		 10151 asection *osec;
10152
6366ff1e
MM		 10153 /* On Symbian OS, the data segment and text segement
10154 can be relocated independently. Therefore, we
10155 must indicate the segment to which this
10156 relocation is relative. The BPABI allows us to
10157 use any symbol in the right segment; we just use
10158 the section symbol as it is convenient. (We
10159 cannot use the symbol given by "h" directly as it
74541ad4
AM		 10160 will not appear in the dynamic symbol table.)
10161
10162 Note that the dynamic linker ignores the section
10163 symbol value, so we don't subtract osec->vma
10164 from the emitted reloc addend. */
10dbd1f3 10165 if (sym_sec)
74541ad4 10166 osec = sym_sec->output_section;
10dbd1f3 10167 else
74541ad4
AM		 10168 osec = input_section->output_section;
10169 symbol = elf_section_data (osec)->dynindx;
10170 if (symbol == 0)
10171 {
10172 struct elf_link_hash_table *htab = elf_hash_table (info);
10173
10174 if ((osec->flags & SEC_READONLY) == 0
10175 && htab->data_index_section != NULL)
10176 osec = htab->data_index_section;
10177 else
10178 osec = htab->text_index_section;
10179 symbol = elf_section_data (osec)->dynindx;
10180 }
6366ff1e
MM		 10181 BFD_ASSERT (symbol != 0);
10182 }
a16385dc
MM		 10183 else
10184 /* On SVR4-ish systems, the dynamic loader cannot
10185 relocate the text and data segments independently,
10186 so the symbol does not matter. */
10187 symbol = 0;
34e77a92
RS		 10188 if (dynreloc_st_type == STT_GNU_IFUNC)
10189 /* We have an STT_GNU_IFUNC symbol that doesn't resolve
10190 to the .iplt entry. Instead, every non-call reference
10191 must use an R_ARM_IRELATIVE relocation to obtain the
10192 correct run-time address. */
10193 outrel.r_info = ELF32_R_INFO (symbol, R_ARM_IRELATIVE);
10194 else
10195 outrel.r_info = ELF32_R_INFO (symbol, R_ARM_RELATIVE);
00a97672
RS		 10196 if (globals->use_rel)
10197 relocate = TRUE;
10198 else
34e77a92 10199 outrel.r_addend += dynreloc_value;
252b5132 10200 }
f21f3fe0 10201
47beaa6a 10202 elf32_arm_add_dynreloc (output_bfd, info, sreloc, &outrel);
9a5aca8c 10203
f21f3fe0 10204 /* If this reloc is against an external symbol, we do not want to
252b5132 10205 fiddle with the addend. Otherwise, we need to include the symbol
9b485d32 10206 value so that it becomes an addend for the dynamic reloc. */
252b5132
RH		 10207 if (! relocate)
10208 return bfd_reloc_ok;
9a5aca8c 10209
f21f3fe0 10210 return _bfd_final_link_relocate (howto, input_bfd, input_section,
34e77a92
RS		 10211 contents, rel->r_offset,
10212 dynreloc_value, (bfd_vma) 0);
252b5132
RH		 10213 }
10214 else switch (r_type)
10215 {
00a97672
RS		 10216 case R_ARM_ABS12:
10217 return elf32_arm_abs12_reloc (input_bfd, hit_data, value + addend);
10218
dfc5f959 10219 case R_ARM_XPC25: /* Arm BLX instruction. */
5b5bb741
PB		 10220 case R_ARM_CALL:
10221 case R_ARM_JUMP24:
8029a119 10222 case R_ARM_PC24: /* Arm B/BL instruction. */
7359ea65 10223 case R_ARM_PLT32:
906e58ca 10224 {
906e58ca
NC		 10225 struct elf32_arm_stub_hash_entry *stub_entry = NULL;
10226
dfc5f959 10227 if (r_type == R_ARM_XPC25)
252b5132 10228 {
dfc5f959
NC		 10229 /* Check for Arm calling Arm function. */
10230 /* FIXME: Should we translate the instruction into a BL
10231 instruction instead ? */
35fc36a8 10232 if (branch_type != ST_BRANCH_TO_THUMB)
4eca0228 10233 _bfd_error_handler
d003868e
AM		 10234 (_("\%B: Warning: Arm BLX instruction targets Arm function '%s'."),
10235 input_bfd,
10236 h ? h->root.root.string : "(local)");
dfc5f959 10237 }
155d87d7 10238 else if (r_type == R_ARM_PC24)
dfc5f959
NC		 10239 {
10240 /* Check for Arm calling Thumb function. */
35fc36a8 10241 if (branch_type == ST_BRANCH_TO_THUMB)
dfc5f959 10242 {
f2a9dd69
DJ		 10243 if (elf32_arm_to_thumb_stub (info, sym_name, input_bfd,
10244 output_bfd, input_section,
10245 hit_data, sym_sec, rel->r_offset,
10246 signed_addend, value,
10247 error_message))
10248 return bfd_reloc_ok;
10249 else
10250 return bfd_reloc_dangerous;
dfc5f959 10251 }
252b5132 10252 }
ba96a88f 10253
906e58ca 10254 /* Check if a stub has to be inserted because the
8029a119 10255 destination is too far or we are changing mode. */
155d87d7
CL		 10256 if ( r_type == R_ARM_CALL
10257 || r_type == R_ARM_JUMP24
10258 || r_type == R_ARM_PLT32)
906e58ca 10259 {
fe33d2fa
CL		 10260 enum elf32_arm_stub_type stub_type = arm_stub_none;
10261 struct elf32_arm_link_hash_entry *hash;
10262
10263 hash = (struct elf32_arm_link_hash_entry *) h;
10264 stub_type = arm_type_of_stub (info, input_section, rel,
34e77a92
RS		 10265 st_type, &branch_type,
10266 hash, value, sym_sec,
fe33d2fa 10267 input_bfd, sym_name);
5fa9e92f 10268
fe33d2fa 10269 if (stub_type != arm_stub_none)
906e58ca
NC		 10270 {
10271 /* The target is out of reach, so redirect the
10272 branch to the local stub for this function. */
906e58ca
NC		 10273 stub_entry = elf32_arm_get_stub_entry (input_section,
10274 sym_sec, h,
fe33d2fa
CL		 10275 rel, globals,
10276 stub_type);
9cd3e4e5
NC		 10277 {
10278 if (stub_entry != NULL)
10279 value = (stub_entry->stub_offset
10280 + stub_entry->stub_sec->output_offset
10281 + stub_entry->stub_sec->output_section->vma);
10282
10283 if (plt_offset != (bfd_vma) -1)
10284 *unresolved_reloc_p = FALSE;
10285 }
906e58ca 10286 }
fe33d2fa
CL		 10287 else
10288 {
10289 /* If the call goes through a PLT entry, make sure to
10290 check distance to the right destination address. */
34e77a92 10291 if (plt_offset != (bfd_vma) -1)
fe33d2fa
CL		 10292 {
10293 value = (splt->output_section->vma
10294 + splt->output_offset
34e77a92 10295 + plt_offset);
fe33d2fa
CL		 10296 *unresolved_reloc_p = FALSE;
10297 /* The PLT entry is in ARM mode, regardless of the
10298 target function. */
35fc36a8 10299 branch_type = ST_BRANCH_TO_ARM;
fe33d2fa
CL		 10300 }
10301 }
906e58ca
NC		 10302 }
10303
dea514f5
PB		 10304 /* The ARM ELF ABI says that this reloc is computed as: S - P + A
10305 where:
10306 S is the address of the symbol in the relocation.
10307 P is address of the instruction being relocated.
10308 A is the addend (extracted from the instruction) in bytes.
10309
10310 S is held in 'value'.
10311 P is the base address of the section containing the
10312 instruction plus the offset of the reloc into that
10313 section, ie:
10314 (input_section->output_section->vma +
10315 input_section->output_offset +
10316 rel->r_offset).
10317 A is the addend, converted into bytes, ie:
10318 (signed_addend * 4)
10319
10320 Note: None of these operations have knowledge of the pipeline
10321 size of the processor, thus it is up to the assembler to
10322 encode this information into the addend. */
10323 value -= (input_section->output_section->vma
10324 + input_section->output_offset);
10325 value -= rel->r_offset;
4e7fd91e
PB		 10326 if (globals->use_rel)
10327 value += (signed_addend << howto->size);
10328 else
10329 /* RELA addends do not have to be adjusted by howto->size. */
10330 value += signed_addend;
23080146 10331
dcb5e6e6
NC		 10332 signed_addend = value;
10333 signed_addend >>= howto->rightshift;
9a5aca8c 10334
5ab79981 10335 /* A branch to an undefined weak symbol is turned into a jump to
ffcb4889 10336 the next instruction unless a PLT entry will be created.
77b4f08f 10337 Do the same for local undefined symbols (but not for STN_UNDEF).
cd1dac3d
DG		 10338 The jump to the next instruction is optimized as a NOP depending
10339 on the architecture. */
ffcb4889 10340 if (h ? (h->root.type == bfd_link_hash_undefweak
34e77a92 10341 && plt_offset == (bfd_vma) -1)
77b4f08f 10342 : r_symndx != STN_UNDEF && bfd_is_und_section (sym_sec))
5ab79981 10343 {
cd1dac3d
DG		 10344 value = (bfd_get_32 (input_bfd, hit_data) & 0xf0000000);
10345
10346 if (arch_has_arm_nop (globals))
10347 value |= 0x0320f000;
10348 else
10349 value |= 0x01a00000; /* Using pre-UAL nop: mov r0, r0. */
5ab79981
PB		 10350 }
10351 else
59f2c4e7 10352 {
9b485d32 10353 /* Perform a signed range check. */
dcb5e6e6 10354 if ( signed_addend > ((bfd_signed_vma) (howto->dst_mask >> 1))
59f2c4e7
NC		 10355 || signed_addend < - ((bfd_signed_vma) ((howto->dst_mask + 1) >> 1)))
10356 return bfd_reloc_overflow;
9a5aca8c 10357
5ab79981 10358 addend = (value & 2);
39b41c9c 10359
5ab79981
PB		 10360 value = (signed_addend & howto->dst_mask)
10361 | (bfd_get_32 (input_bfd, hit_data) & (~ howto->dst_mask));
39b41c9c 10362
5ab79981
PB		 10363 if (r_type == R_ARM_CALL)
10364 {
155d87d7 10365 /* Set the H bit in the BLX instruction. */
35fc36a8 10366 if (branch_type == ST_BRANCH_TO_THUMB)
155d87d7
CL		 10367 {
10368 if (addend)
10369 value |= (1 << 24);
10370 else
10371 value &= ~(bfd_vma)(1 << 24);
10372 }
10373
5ab79981 10374 /* Select the correct instruction (BL or BLX). */
906e58ca 10375 /* Only if we are not handling a BL to a stub. In this
8029a119 10376 case, mode switching is performed by the stub. */
35fc36a8 10377 if (branch_type == ST_BRANCH_TO_THUMB && !stub_entry)
5ab79981 10378 value |= (1 << 28);
63e1a0fc 10379 else if (stub_entry || branch_type != ST_BRANCH_UNKNOWN)
5ab79981
PB		 10380 {
10381 value &= ~(bfd_vma)(1 << 28);
10382 value |= (1 << 24);
10383 }
39b41c9c
PB		 10384 }
10385 }
906e58ca 10386 }
252b5132 10387 break;
f21f3fe0 10388
252b5132
RH		 10389 case R_ARM_ABS32:
10390 value += addend;
35fc36a8 10391 if (branch_type == ST_BRANCH_TO_THUMB)
252b5132
RH		 10392 value |= 1;
10393 break;
f21f3fe0 10394
bb224fc3
MS		 10395 case R_ARM_ABS32_NOI:
10396 value += addend;
10397 break;
10398
252b5132 10399 case R_ARM_REL32:
a8bc6c78 10400 value += addend;
35fc36a8 10401 if (branch_type == ST_BRANCH_TO_THUMB)
a8bc6c78 10402 value |= 1;
252b5132 10403 value -= (input_section->output_section->vma
62efb346 10404 + input_section->output_offset + rel->r_offset);
252b5132 10405 break;
eb043451 10406
bb224fc3
MS		 10407 case R_ARM_REL32_NOI:
10408 value += addend;
10409 value -= (input_section->output_section->vma
10410 + input_section->output_offset + rel->r_offset);
10411 break;
10412
eb043451
PB		 10413 case R_ARM_PREL31:
10414 value -= (input_section->output_section->vma
10415 + input_section->output_offset + rel->r_offset);
10416 value += signed_addend;
10417 if (! h || h->root.type != bfd_link_hash_undefweak)
10418 {
8029a119 10419 /* Check for overflow. */
eb043451
PB		 10420 if ((value ^ (value >> 1)) & (1 << 30))
10421 return bfd_reloc_overflow;
10422 }
10423 value &= 0x7fffffff;
10424 value |= (bfd_get_32 (input_bfd, hit_data) & 0x80000000);
35fc36a8 10425 if (branch_type == ST_BRANCH_TO_THUMB)
eb043451
PB		 10426 value |= 1;
10427 break;
252b5132 10428 }
f21f3fe0 10429
252b5132
RH		 10430 bfd_put_32 (input_bfd, value, hit_data);
10431 return bfd_reloc_ok;
10432
10433 case R_ARM_ABS8:
fd0fd00c
MJ		 10434 /* PR 16202: Refectch the addend using the correct size. */
10435 if (globals->use_rel)
10436 addend = bfd_get_8 (input_bfd, hit_data);
252b5132 10437 value += addend;
4e67d4ca
DG		 10438
10439 /* There is no way to tell whether the user intended to use a signed or
10440 unsigned addend. When checking for overflow we accept either,
10441 as specified by the AAELF. */
10442 if ((long) value > 0xff || (long) value < -0x80)
252b5132
RH		 10443 return bfd_reloc_overflow;
10444
10445 bfd_put_8 (input_bfd, value, hit_data);
10446 return bfd_reloc_ok;
10447
10448 case R_ARM_ABS16:
fd0fd00c
MJ		 10449 /* PR 16202: Refectch the addend using the correct size. */
10450 if (globals->use_rel)
10451 addend = bfd_get_16 (input_bfd, hit_data);
252b5132
RH		 10452 value += addend;
10453
4e67d4ca
DG		 10454 /* See comment for R_ARM_ABS8. */
10455 if ((long) value > 0xffff || (long) value < -0x8000)
252b5132
RH		 10456 return bfd_reloc_overflow;
10457
10458 bfd_put_16 (input_bfd, value, hit_data);
10459 return bfd_reloc_ok;
10460
252b5132 10461 case R_ARM_THM_ABS5:
9b485d32 10462 /* Support ldr and str instructions for the thumb. */
4e7fd91e
PB		 10463 if (globals->use_rel)
10464 {
10465 /* Need to refetch addend. */
10466 addend = bfd_get_16 (input_bfd, hit_data) & howto->src_mask;
10467 /* ??? Need to determine shift amount from operand size. */
10468 addend >>= howto->rightshift;
10469 }
252b5132
RH		 10470 value += addend;
10471
10472 /* ??? Isn't value unsigned? */
10473 if ((long) value > 0x1f || (long) value < -0x10)
10474 return bfd_reloc_overflow;
10475
10476 /* ??? Value needs to be properly shifted into place first. */
10477 value |= bfd_get_16 (input_bfd, hit_data) & 0xf83f;
10478 bfd_put_16 (input_bfd, value, hit_data);
10479 return bfd_reloc_ok;
10480
2cab6cc3
MS		 10481 case R_ARM_THM_ALU_PREL_11_0:
10482 /* Corresponds to: addw.w reg, pc, #offset (and similarly for subw). */
10483 {
10484 bfd_vma insn;
10485 bfd_signed_vma relocation;
10486
10487 insn = (bfd_get_16 (input_bfd, hit_data) << 16)
99059e56 10488 | bfd_get_16 (input_bfd, hit_data + 2);
2cab6cc3 10489
99059e56
RM		 10490 if (globals->use_rel)
10491 {
10492 signed_addend = (insn & 0xff) | ((insn & 0x7000) >> 4)
10493 | ((insn & (1 << 26)) >> 15);
10494 if (insn & 0xf00000)
10495 signed_addend = -signed_addend;
10496 }
2cab6cc3
MS		 10497
10498 relocation = value + signed_addend;
79f08007 10499 relocation -= Pa (input_section->output_section->vma
99059e56
RM		 10500 + input_section->output_offset
10501 + rel->r_offset);
2cab6cc3 10502
8c65b54f
CS		 10503 /* PR 21523: Use an absolute value. The user of this reloc will
10504 have already selected an ADD or SUB insn appropriately. */
e652757b 10505 value = labs (relocation);
2cab6cc3 10506
99059e56
RM		 10507 if (value >= 0x1000)
10508 return bfd_reloc_overflow;
2cab6cc3 10509
e645cf40
AG		 10510 /* Destination is Thumb. Force bit 0 to 1 to reflect this. */
10511 if (branch_type == ST_BRANCH_TO_THUMB)
10512 value |= 1;
10513
2cab6cc3 10514 insn = (insn & 0xfb0f8f00) | (value & 0xff)
99059e56
RM		 10515 | ((value & 0x700) << 4)
10516 | ((value & 0x800) << 15);
10517 if (relocation < 0)
10518 insn |= 0xa00000;
2cab6cc3
MS		 10519
10520 bfd_put_16 (input_bfd, insn >> 16, hit_data);
10521 bfd_put_16 (input_bfd, insn & 0xffff, hit_data + 2);
10522
99059e56 10523 return bfd_reloc_ok;
2cab6cc3
MS		 10524 }
10525
e1ec24c6
NC		 10526 case R_ARM_THM_PC8:
10527 /* PR 10073: This reloc is not generated by the GNU toolchain,
10528 but it is supported for compatibility with third party libraries
10529 generated by other compilers, specifically the ARM/IAR. */
10530 {
10531 bfd_vma insn;
10532 bfd_signed_vma relocation;
10533
10534 insn = bfd_get_16 (input_bfd, hit_data);
10535
99059e56 10536 if (globals->use_rel)
79f08007 10537 addend = ((((insn & 0x00ff) << 2) + 4) & 0x3ff) -4;
e1ec24c6
NC		 10538
10539 relocation = value + addend;
79f08007 10540 relocation -= Pa (input_section->output_section->vma
99059e56
RM		 10541 + input_section->output_offset
10542 + rel->r_offset);
e1ec24c6 10543
b6518b38 10544 value = relocation;
e1ec24c6
NC		 10545
10546 /* We do not check for overflow of this reloc. Although strictly
10547 speaking this is incorrect, it appears to be necessary in order
10548 to work with IAR generated relocs. Since GCC and GAS do not
10549 generate R_ARM_THM_PC8 relocs, the lack of a check should not be
10550 a problem for them. */
10551 value &= 0x3fc;
10552
10553 insn = (insn & 0xff00) | (value >> 2);
10554
10555 bfd_put_16 (input_bfd, insn, hit_data);
10556
99059e56 10557 return bfd_reloc_ok;
e1ec24c6
NC		 10558 }
10559
2cab6cc3
MS		 10560 case R_ARM_THM_PC12:
10561 /* Corresponds to: ldr.w reg, [pc, #offset]. */
10562 {
10563 bfd_vma insn;
10564 bfd_signed_vma relocation;
10565
10566 insn = (bfd_get_16 (input_bfd, hit_data) << 16)
99059e56 10567 | bfd_get_16 (input_bfd, hit_data + 2);
2cab6cc3 10568
99059e56
RM		 10569 if (globals->use_rel)
10570 {
10571 signed_addend = insn & 0xfff;
10572 if (!(insn & (1 << 23)))
10573 signed_addend = -signed_addend;
10574 }
2cab6cc3
MS		 10575
10576 relocation = value + signed_addend;
79f08007 10577 relocation -= Pa (input_section->output_section->vma
99059e56
RM		 10578 + input_section->output_offset
10579 + rel->r_offset);
2cab6cc3 10580
b6518b38 10581 value = relocation;
2cab6cc3 10582
99059e56
RM		 10583 if (value >= 0x1000)
10584 return bfd_reloc_overflow;
2cab6cc3
MS		 10585
10586 insn = (insn & 0xff7ff000) | value;
99059e56
RM		 10587 if (relocation >= 0)
10588 insn |= (1 << 23);
2cab6cc3
MS		 10589
10590 bfd_put_16 (input_bfd, insn >> 16, hit_data);
10591 bfd_put_16 (input_bfd, insn & 0xffff, hit_data + 2);
10592
99059e56 10593 return bfd_reloc_ok;
2cab6cc3
MS		 10594 }
10595
dfc5f959 10596 case R_ARM_THM_XPC22:
c19d1205 10597 case R_ARM_THM_CALL:
bd97cb95 10598 case R_ARM_THM_JUMP24:
dfc5f959 10599 /* Thumb BL (branch long instruction). */
252b5132 10600 {
b34976b6 10601 bfd_vma relocation;
99059e56 10602 bfd_vma reloc_sign;
b34976b6
AM		 10603 bfd_boolean overflow = FALSE;
10604 bfd_vma upper_insn = bfd_get_16 (input_bfd, hit_data);
10605 bfd_vma lower_insn = bfd_get_16 (input_bfd, hit_data + 2);
e95de063
MS		 10606 bfd_signed_vma reloc_signed_max;
10607 bfd_signed_vma reloc_signed_min;
b34976b6 10608 bfd_vma check;
252b5132 10609 bfd_signed_vma signed_check;
e95de063 10610 int bitsize;
cd1dac3d 10611 const int thumb2 = using_thumb2 (globals);
5e866f5a 10612 const int thumb2_bl = using_thumb2_bl (globals);
252b5132 10613
5ab79981 10614 /* A branch to an undefined weak symbol is turned into a jump to
cd1dac3d
DG		 10615 the next instruction unless a PLT entry will be created.
10616 The jump to the next instruction is optimized as a NOP.W for
10617 Thumb-2 enabled architectures. */
19540007 10618 if (h && h->root.type == bfd_link_hash_undefweak
34e77a92 10619 && plt_offset == (bfd_vma) -1)
5ab79981 10620 {
60a019a0 10621 if (thumb2)
cd1dac3d
DG		 10622 {
10623 bfd_put_16 (input_bfd, 0xf3af, hit_data);
10624 bfd_put_16 (input_bfd, 0x8000, hit_data + 2);
10625 }
10626 else
10627 {
10628 bfd_put_16 (input_bfd, 0xe000, hit_data);
10629 bfd_put_16 (input_bfd, 0xbf00, hit_data + 2);
10630 }
5ab79981
PB		 10631 return bfd_reloc_ok;
10632 }
10633
e95de063 10634 /* Fetch the addend. We use the Thumb-2 encoding (backwards compatible
99059e56 10635 with Thumb-1) involving the J1 and J2 bits. */
4e7fd91e
PB		 10636 if (globals->use_rel)
10637 {
99059e56
RM		 10638 bfd_vma s = (upper_insn & (1 << 10)) >> 10;
10639 bfd_vma upper = upper_insn & 0x3ff;
10640 bfd_vma lower = lower_insn & 0x7ff;
e95de063
MS		 10641 bfd_vma j1 = (lower_insn & (1 << 13)) >> 13;
10642 bfd_vma j2 = (lower_insn & (1 << 11)) >> 11;
99059e56
RM		 10643 bfd_vma i1 = j1 ^ s ? 0 : 1;
10644 bfd_vma i2 = j2 ^ s ? 0 : 1;
e95de063 10645
99059e56
RM		 10646 addend = (i1 << 23) | (i2 << 22) | (upper << 12) | (lower << 1);
10647 /* Sign extend. */
10648 addend = (addend | ((s ? 0 : 1) << 24)) - (1 << 24);
e95de063 10649
4e7fd91e
PB		 10650 signed_addend = addend;
10651 }
cb1afa5c 10652
dfc5f959
NC		 10653 if (r_type == R_ARM_THM_XPC22)
10654 {
10655 /* Check for Thumb to Thumb call. */
10656 /* FIXME: Should we translate the instruction into a BL
10657 instruction instead ? */
35fc36a8 10658 if (branch_type == ST_BRANCH_TO_THUMB)
4eca0228 10659 _bfd_error_handler
d003868e
AM		 10660 (_("%B: Warning: Thumb BLX instruction targets thumb function '%s'."),
10661 input_bfd,
10662 h ? h->root.root.string : "(local)");
dfc5f959
NC		 10663 }
10664 else
252b5132 10665 {
dfc5f959
NC		 10666 /* If it is not a call to Thumb, assume call to Arm.
10667 If it is a call relative to a section name, then it is not a
b7693d02
DJ		 10668 function call at all, but rather a long jump. Calls through
10669 the PLT do not require stubs. */
34e77a92 10670 if (branch_type == ST_BRANCH_TO_ARM && plt_offset == (bfd_vma) -1)
dfc5f959 10671 {
bd97cb95 10672 if (globals->use_blx && r_type == R_ARM_THM_CALL)
39b41c9c
PB		 10673 {
10674 /* Convert BL to BLX. */
10675 lower_insn = (lower_insn & ~0x1000) | 0x0800;
10676 }
155d87d7
CL		 10677 else if (( r_type != R_ARM_THM_CALL)
10678 && (r_type != R_ARM_THM_JUMP24))
8029a119
NC		 10679 {
10680 if (elf32_thumb_to_arm_stub
10681 (info, sym_name, input_bfd, output_bfd, input_section,
10682 hit_data, sym_sec, rel->r_offset, signed_addend, value,
10683 error_message))
10684 return bfd_reloc_ok;
10685 else
10686 return bfd_reloc_dangerous;
10687 }
da5938a2 10688 }
35fc36a8
RS		 10689 else if (branch_type == ST_BRANCH_TO_THUMB
10690 && globals->use_blx
bd97cb95 10691 && r_type == R_ARM_THM_CALL)
39b41c9c
PB		 10692 {
10693 /* Make sure this is a BL. */
10694 lower_insn |= 0x1800;
10695 }
252b5132 10696 }
f21f3fe0 10697
fe33d2fa 10698 enum elf32_arm_stub_type stub_type = arm_stub_none;
155d87d7 10699 if (r_type == R_ARM_THM_CALL || r_type == R_ARM_THM_JUMP24)
906e58ca
NC		 10700 {
10701 /* Check if a stub has to be inserted because the destination
8029a119 10702 is too far. */
fe33d2fa
CL		 10703 struct elf32_arm_stub_hash_entry *stub_entry;
10704 struct elf32_arm_link_hash_entry *hash;
10705
10706 hash = (struct elf32_arm_link_hash_entry *) h;
10707
10708 stub_type = arm_type_of_stub (info, input_section, rel,
34e77a92
RS		 10709 st_type, &branch_type,
10710 hash, value, sym_sec,
fe33d2fa
CL		 10711 input_bfd, sym_name);
10712
10713 if (stub_type != arm_stub_none)
906e58ca
NC		 10714 {
10715 /* The target is out of reach or we are changing modes, so
10716 redirect the branch to the local stub for this
10717 function. */
10718 stub_entry = elf32_arm_get_stub_entry (input_section,
10719 sym_sec, h,
fe33d2fa
CL		 10720 rel, globals,
10721 stub_type);
906e58ca 10722 if (stub_entry != NULL)
9cd3e4e5
NC		 10723 {
10724 value = (stub_entry->stub_offset
10725 + stub_entry->stub_sec->output_offset
10726 + stub_entry->stub_sec->output_section->vma);
10727
10728 if (plt_offset != (bfd_vma) -1)
10729 *unresolved_reloc_p = FALSE;
10730 }
906e58ca 10731
f4ac8484 10732 /* If this call becomes a call to Arm, force BLX. */
155d87d7 10733 if (globals->use_blx && (r_type == R_ARM_THM_CALL))
f4ac8484
DJ		 10734 {
10735 if ((stub_entry
10736 && !arm_stub_is_thumb (stub_entry->stub_type))
35fc36a8 10737 || branch_type != ST_BRANCH_TO_THUMB)
f4ac8484
DJ		 10738 lower_insn = (lower_insn & ~0x1000) | 0x0800;
10739 }
906e58ca
NC		 10740 }
10741 }
10742
fe33d2fa 10743 /* Handle calls via the PLT. */
34e77a92 10744 if (stub_type == arm_stub_none && plt_offset != (bfd_vma) -1)
fe33d2fa
CL		 10745 {
10746 value = (splt->output_section->vma
10747 + splt->output_offset
34e77a92 10748 + plt_offset);
fe33d2fa 10749
eed94f8f
NC		 10750 if (globals->use_blx
10751 && r_type == R_ARM_THM_CALL
10752 && ! using_thumb_only (globals))
fe33d2fa
CL		 10753 {
10754 /* If the Thumb BLX instruction is available, convert
10755 the BL to a BLX instruction to call the ARM-mode
10756 PLT entry. */
10757 lower_insn = (lower_insn & ~0x1000) | 0x0800;
35fc36a8 10758 branch_type = ST_BRANCH_TO_ARM;
fe33d2fa
CL		 10759 }
10760 else
10761 {
eed94f8f
NC		 10762 if (! using_thumb_only (globals))
10763 /* Target the Thumb stub before the ARM PLT entry. */
10764 value -= PLT_THUMB_STUB_SIZE;
35fc36a8 10765 branch_type = ST_BRANCH_TO_THUMB;
fe33d2fa
CL		 10766 }
10767 *unresolved_reloc_p = FALSE;
10768 }
10769
ba96a88f 10770 relocation = value + signed_addend;
f21f3fe0 10771
252b5132 10772 relocation -= (input_section->output_section->vma
ba96a88f
NC		 10773 + input_section->output_offset
10774 + rel->r_offset);
9a5aca8c 10775
252b5132
RH		 10776 check = relocation >> howto->rightshift;
10777
10778 /* If this is a signed value, the rightshift just dropped
10779 leading 1 bits (assuming twos complement). */
10780 if ((bfd_signed_vma) relocation >= 0)
10781 signed_check = check;
10782 else
10783 signed_check = check | ~((bfd_vma) -1 >> howto->rightshift);
10784
e95de063
MS		 10785 /* Calculate the permissable maximum and minimum values for
10786 this relocation according to whether we're relocating for
10787 Thumb-2 or not. */
10788 bitsize = howto->bitsize;
5e866f5a 10789 if (!thumb2_bl)
e95de063 10790 bitsize -= 2;
f6ebfac0 10791 reloc_signed_max = (1 << (bitsize - 1)) - 1;
e95de063
MS		 10792 reloc_signed_min = ~reloc_signed_max;
10793
252b5132 10794 /* Assumes two's complement. */
ba96a88f 10795 if (signed_check > reloc_signed_max || signed_check < reloc_signed_min)
b34976b6 10796 overflow = TRUE;
252b5132 10797
bd97cb95 10798 if ((lower_insn & 0x5000) == 0x4000)
c62e1cc3
NC		 10799 /* For a BLX instruction, make sure that the relocation is rounded up
10800 to a word boundary. This follows the semantics of the instruction
10801 which specifies that bit 1 of the target address will come from bit
10802 1 of the base address. */
10803 relocation = (relocation + 2) & ~ 3;
cb1afa5c 10804
e95de063
MS		 10805 /* Put RELOCATION back into the insn. Assumes two's complement.
10806 We use the Thumb-2 encoding, which is safe even if dealing with
10807 a Thumb-1 instruction by virtue of our overflow check above. */
99059e56 10808 reloc_sign = (signed_check < 0) ? 1 : 0;
e95de063 10809 upper_insn = (upper_insn & ~(bfd_vma) 0x7ff)
99059e56
RM		 10810 | ((relocation >> 12) & 0x3ff)
10811 | (reloc_sign << 10);
906e58ca 10812 lower_insn = (lower_insn & ~(bfd_vma) 0x2fff)
99059e56
RM		 10813 | (((!((relocation >> 23) & 1)) ^ reloc_sign) << 13)
10814 | (((!((relocation >> 22) & 1)) ^ reloc_sign) << 11)
10815 | ((relocation >> 1) & 0x7ff);
c62e1cc3 10816
252b5132
RH		 10817 /* Put the relocated value back in the object file: */
10818 bfd_put_16 (input_bfd, upper_insn, hit_data);
10819 bfd_put_16 (input_bfd, lower_insn, hit_data + 2);
10820
10821 return (overflow ? bfd_reloc_overflow : bfd_reloc_ok);
10822 }
10823 break;
10824
c19d1205
ZW		 10825 case R_ARM_THM_JUMP19:
10826 /* Thumb32 conditional branch instruction. */
10827 {
10828 bfd_vma relocation;
10829 bfd_boolean overflow = FALSE;
10830 bfd_vma upper_insn = bfd_get_16 (input_bfd, hit_data);
10831 bfd_vma lower_insn = bfd_get_16 (input_bfd, hit_data + 2);
a00a1f35
MS		 10832 bfd_signed_vma reloc_signed_max = 0xffffe;
10833 bfd_signed_vma reloc_signed_min = -0x100000;
c19d1205 10834 bfd_signed_vma signed_check;
c5423981
TG		 10835 enum elf32_arm_stub_type stub_type = arm_stub_none;
10836 struct elf32_arm_stub_hash_entry *stub_entry;
10837 struct elf32_arm_link_hash_entry *hash;
c19d1205
ZW		 10838
10839 /* Need to refetch the addend, reconstruct the top three bits,
10840 and squish the two 11 bit pieces together. */
10841 if (globals->use_rel)
10842 {
10843 bfd_vma S = (upper_insn & 0x0400) >> 10;
a00a1f35 10844 bfd_vma upper = (upper_insn & 0x003f);
c19d1205
ZW		 10845 bfd_vma J1 = (lower_insn & 0x2000) >> 13;
10846 bfd_vma J2 = (lower_insn & 0x0800) >> 11;
10847 bfd_vma lower = (lower_insn & 0x07ff);
10848
a00a1f35
MS		 10849 upper |= J1 << 6;
10850 upper |= J2 << 7;
10851 upper |= (!S) << 8;
c19d1205
ZW		 10852 upper -= 0x0100; /* Sign extend. */
10853
10854 addend = (upper << 12) | (lower << 1);
10855 signed_addend = addend;
10856 }
10857
bd97cb95 10858 /* Handle calls via the PLT. */
34e77a92 10859 if (plt_offset != (bfd_vma) -1)
bd97cb95
DJ		 10860 {
10861 value = (splt->output_section->vma
10862 + splt->output_offset
34e77a92 10863 + plt_offset);
bd97cb95
DJ		 10864 /* Target the Thumb stub before the ARM PLT entry. */
10865 value -= PLT_THUMB_STUB_SIZE;
10866 *unresolved_reloc_p = FALSE;
10867 }
10868
c5423981
TG		 10869 hash = (struct elf32_arm_link_hash_entry *)h;
10870
10871 stub_type = arm_type_of_stub (info, input_section, rel,
10872 st_type, &branch_type,
10873 hash, value, sym_sec,
10874 input_bfd, sym_name);
10875 if (stub_type != arm_stub_none)
10876 {
10877 stub_entry = elf32_arm_get_stub_entry (input_section,
10878 sym_sec, h,
10879 rel, globals,
10880 stub_type);
10881 if (stub_entry != NULL)
10882 {
10883 value = (stub_entry->stub_offset
10884 + stub_entry->stub_sec->output_offset
10885 + stub_entry->stub_sec->output_section->vma);
10886 }
10887 }
c19d1205 10888
99059e56 10889 relocation = value + signed_addend;
c19d1205
ZW		 10890 relocation -= (input_section->output_section->vma
10891 + input_section->output_offset
10892 + rel->r_offset);
a00a1f35 10893 signed_check = (bfd_signed_vma) relocation;
c19d1205 10894
c19d1205
ZW		 10895 if (signed_check > reloc_signed_max || signed_check < reloc_signed_min)
10896 overflow = TRUE;
10897
10898 /* Put RELOCATION back into the insn. */
10899 {
10900 bfd_vma S = (relocation & 0x00100000) >> 20;
10901 bfd_vma J2 = (relocation & 0x00080000) >> 19;
10902 bfd_vma J1 = (relocation & 0x00040000) >> 18;
10903 bfd_vma hi = (relocation & 0x0003f000) >> 12;
10904 bfd_vma lo = (relocation & 0x00000ffe) >> 1;
10905
a00a1f35 10906 upper_insn = (upper_insn & 0xfbc0) | (S << 10) | hi;
c19d1205
ZW		 10907 lower_insn = (lower_insn & 0xd000) | (J1 << 13) | (J2 << 11) | lo;
10908 }
10909
10910 /* Put the relocated value back in the object file: */
10911 bfd_put_16 (input_bfd, upper_insn, hit_data);
10912 bfd_put_16 (input_bfd, lower_insn, hit_data + 2);
10913
10914 return (overflow ? bfd_reloc_overflow : bfd_reloc_ok);
10915 }
10916
10917 case R_ARM_THM_JUMP11:
10918 case R_ARM_THM_JUMP8:
10919 case R_ARM_THM_JUMP6:
51c5503b
NC		 10920 /* Thumb B (branch) instruction). */
10921 {
6cf9e9fe 10922 bfd_signed_vma relocation;
51c5503b
NC		 10923 bfd_signed_vma reloc_signed_max = (1 << (howto->bitsize - 1)) - 1;
10924 bfd_signed_vma reloc_signed_min = ~ reloc_signed_max;
51c5503b
NC		 10925 bfd_signed_vma signed_check;
10926
c19d1205
ZW		 10927 /* CZB cannot jump backward. */
10928 if (r_type == R_ARM_THM_JUMP6)
10929 reloc_signed_min = 0;
10930
4e7fd91e 10931 if (globals->use_rel)
6cf9e9fe 10932 {
4e7fd91e
PB		 10933 /* Need to refetch addend. */
10934 addend = bfd_get_16 (input_bfd, hit_data) & howto->src_mask;
10935 if (addend & ((howto->src_mask + 1) >> 1))
10936 {
10937 signed_addend = -1;
10938 signed_addend &= ~ howto->src_mask;
10939 signed_addend |= addend;
10940 }
10941 else
10942 signed_addend = addend;
10943 /* The value in the insn has been right shifted. We need to
10944 undo this, so that we can perform the address calculation
10945 in terms of bytes. */
10946 signed_addend <<= howto->rightshift;
6cf9e9fe 10947 }
6cf9e9fe 10948 relocation = value + signed_addend;
51c5503b
NC		 10949
10950 relocation -= (input_section->output_section->vma
10951 + input_section->output_offset
10952 + rel->r_offset);
10953
6cf9e9fe
NC		 10954 relocation >>= howto->rightshift;
10955 signed_check = relocation;
c19d1205
ZW		 10956
10957 if (r_type == R_ARM_THM_JUMP6)
10958 relocation = ((relocation & 0x0020) << 4) | ((relocation & 0x001f) << 3);
10959 else
10960 relocation &= howto->dst_mask;
51c5503b 10961 relocation |= (bfd_get_16 (input_bfd, hit_data) & (~ howto->dst_mask));
cedb70c5 10962
51c5503b
NC		 10963 bfd_put_16 (input_bfd, relocation, hit_data);
10964
10965 /* Assumes two's complement. */
10966 if (signed_check > reloc_signed_max || signed_check < reloc_signed_min)
10967 return bfd_reloc_overflow;
10968
10969 return bfd_reloc_ok;
10970 }
cedb70c5 10971
8375c36b
PB		 10972 case R_ARM_ALU_PCREL7_0:
10973 case R_ARM_ALU_PCREL15_8:
10974 case R_ARM_ALU_PCREL23_15:
10975 {
10976 bfd_vma insn;
10977 bfd_vma relocation;
10978
10979 insn = bfd_get_32 (input_bfd, hit_data);
4e7fd91e
PB		 10980 if (globals->use_rel)
10981 {
10982 /* Extract the addend. */
10983 addend = (insn & 0xff) << ((insn & 0xf00) >> 7);
10984 signed_addend = addend;
10985 }
8375c36b
PB		 10986 relocation = value + signed_addend;
10987
10988 relocation -= (input_section->output_section->vma
10989 + input_section->output_offset
10990 + rel->r_offset);
10991 insn = (insn & ~0xfff)
10992 | ((howto->bitpos << 7) & 0xf00)
10993 | ((relocation >> howto->bitpos) & 0xff);
10994 bfd_put_32 (input_bfd, value, hit_data);
10995 }
10996 return bfd_reloc_ok;
10997
252b5132
RH		 10998 case R_ARM_GNU_VTINHERIT:
10999 case R_ARM_GNU_VTENTRY:
11000 return bfd_reloc_ok;
11001
c19d1205 11002 case R_ARM_GOTOFF32:
252b5132 11003 /* Relocation is relative to the start of the
99059e56 11004 global offset table. */
252b5132
RH		 11005
11006 BFD_ASSERT (sgot != NULL);
11007 if (sgot == NULL)
99059e56 11008 return bfd_reloc_notsupported;
9a5aca8c 11009
cedb70c5 11010 /* If we are addressing a Thumb function, we need to adjust the
ee29b9fb
RE		 11011 address by one, so that attempts to call the function pointer will
11012 correctly interpret it as Thumb code. */
35fc36a8 11013 if (branch_type == ST_BRANCH_TO_THUMB)
ee29b9fb
RE		 11014 value += 1;
11015
252b5132 11016 /* Note that sgot->output_offset is not involved in this
99059e56
RM		 11017 calculation. We always want the start of .got. If we
11018 define _GLOBAL_OFFSET_TABLE in a different way, as is
11019 permitted by the ABI, we might have to change this
11020 calculation. */
252b5132 11021 value -= sgot->output_section->vma;
f21f3fe0 11022 return _bfd_final_link_relocate (howto, input_bfd, input_section,
99e4ae17 11023 contents, rel->r_offset, value,
00a97672 11024 rel->r_addend);
252b5132
RH		 11025
11026 case R_ARM_GOTPC:
a7c10850 11027 /* Use global offset table as symbol value. */
252b5132 11028 BFD_ASSERT (sgot != NULL);
f21f3fe0 11029
252b5132 11030 if (sgot == NULL)
99059e56 11031 return bfd_reloc_notsupported;
252b5132 11032
0945cdfd 11033 *unresolved_reloc_p = FALSE;
252b5132 11034 value = sgot->output_section->vma;
f21f3fe0 11035 return _bfd_final_link_relocate (howto, input_bfd, input_section,
99e4ae17 11036 contents, rel->r_offset, value,
00a97672 11037 rel->r_addend);
f21f3fe0 11038
252b5132 11039 case R_ARM_GOT32:
eb043451 11040 case R_ARM_GOT_PREL:
252b5132 11041 /* Relocation is to the entry for this symbol in the
99059e56 11042 global offset table. */
252b5132
RH		 11043 if (sgot == NULL)
11044 return bfd_reloc_notsupported;
f21f3fe0 11045
34e77a92
RS		 11046 if (dynreloc_st_type == STT_GNU_IFUNC
11047 && plt_offset != (bfd_vma) -1
11048 && (h == NULL || SYMBOL_REFERENCES_LOCAL (info, h)))
11049 {
11050 /* We have a relocation against a locally-binding STT_GNU_IFUNC
11051 symbol, and the relocation resolves directly to the runtime
11052 target rather than to the .iplt entry. This means that any
11053 .got entry would be the same value as the .igot.plt entry,
11054 so there's no point creating both. */
11055 sgot = globals->root.igotplt;
11056 value = sgot->output_offset + gotplt_offset;
11057 }
11058 else if (h != NULL)
252b5132
RH		 11059 {
11060 bfd_vma off;
f21f3fe0 11061
252b5132
RH		 11062 off = h->got.offset;
11063 BFD_ASSERT (off != (bfd_vma) -1);
b436d854 11064 if ((off & 1) != 0)
252b5132 11065 {
b436d854
RS		 11066 /* We have already processsed one GOT relocation against
11067 this symbol. */
11068 off &= ~1;
11069 if (globals->root.dynamic_sections_created
11070 && !SYMBOL_REFERENCES_LOCAL (info, h))
11071 *unresolved_reloc_p = FALSE;
11072 }
11073 else
11074 {
11075 Elf_Internal_Rela outrel;
11076
6f820c85 11077 if (h->dynindx != -1 && !SYMBOL_REFERENCES_LOCAL (info, h))
b436d854
RS		 11078 {
11079 /* If the symbol doesn't resolve locally in a static
11080 object, we have an undefined reference. If the
11081 symbol doesn't resolve locally in a dynamic object,
11082 it should be resolved by the dynamic linker. */
11083 if (globals->root.dynamic_sections_created)
11084 {
11085 outrel.r_info = ELF32_R_INFO (h->dynindx, R_ARM_GLOB_DAT);
11086 *unresolved_reloc_p = FALSE;
11087 }
11088 else
11089 outrel.r_info = 0;
11090 outrel.r_addend = 0;
11091 }
252b5132
RH		 11092 else
11093 {
34e77a92 11094 if (dynreloc_st_type == STT_GNU_IFUNC)
99059e56 11095 outrel.r_info = ELF32_R_INFO (0, R_ARM_IRELATIVE);
5025eb7c
AO		 11096 else if (bfd_link_pic (info)
11097 && (ELF_ST_VISIBILITY (h->other) == STV_DEFAULT
11098 || h->root.type != bfd_link_hash_undefweak))
99059e56
RM		 11099 outrel.r_info = ELF32_R_INFO (0, R_ARM_RELATIVE);
11100 else
11101 outrel.r_info = 0;
34e77a92 11102 outrel.r_addend = dynreloc_value;
b436d854 11103 }
ee29b9fb 11104
b436d854
RS		 11105 /* The GOT entry is initialized to zero by default.
11106 See if we should install a different value. */
11107 if (outrel.r_addend != 0
11108 && (outrel.r_info == 0 || globals->use_rel))
11109 {
11110 bfd_put_32 (output_bfd, outrel.r_addend,
11111 sgot->contents + off);
11112 outrel.r_addend = 0;
252b5132 11113 }
f21f3fe0 11114
b436d854
RS		 11115 if (outrel.r_info != 0)
11116 {
11117 outrel.r_offset = (sgot->output_section->vma
11118 + sgot->output_offset
11119 + off);
11120 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
11121 }
11122 h->got.offset |= 1;
11123 }
252b5132
RH		 11124 value = sgot->output_offset + off;
11125 }
11126 else
11127 {
11128 bfd_vma off;
f21f3fe0 11129
5025eb7c
AO		 11130 BFD_ASSERT (local_got_offsets != NULL
11131 && local_got_offsets[r_symndx] != (bfd_vma) -1);
f21f3fe0 11132
252b5132 11133 off = local_got_offsets[r_symndx];
f21f3fe0 11134
252b5132
RH		 11135 /* The offset must always be a multiple of 4. We use the
11136 least significant bit to record whether we have already
9b485d32 11137 generated the necessary reloc. */
252b5132
RH		 11138 if ((off & 1) != 0)
11139 off &= ~1;
11140 else
11141 {
00a97672 11142 if (globals->use_rel)
34e77a92 11143 bfd_put_32 (output_bfd, dynreloc_value, sgot->contents + off);
f21f3fe0 11144
0e1862bb 11145 if (bfd_link_pic (info) || dynreloc_st_type == STT_GNU_IFUNC)
252b5132 11146 {
947216bf 11147 Elf_Internal_Rela outrel;
f21f3fe0 11148
34e77a92 11149 outrel.r_addend = addend + dynreloc_value;
252b5132 11150 outrel.r_offset = (sgot->output_section->vma
f21f3fe0 11151 + sgot->output_offset
252b5132 11152 + off);
34e77a92 11153 if (dynreloc_st_type == STT_GNU_IFUNC)
99059e56 11154 outrel.r_info = ELF32_R_INFO (0, R_ARM_IRELATIVE);
34e77a92
RS		 11155 else
11156 outrel.r_info = ELF32_R_INFO (0, R_ARM_RELATIVE);
47beaa6a 11157 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
252b5132 11158 }
f21f3fe0 11159
252b5132
RH		 11160 local_got_offsets[r_symndx] |= 1;
11161 }
f21f3fe0 11162
252b5132
RH		 11163 value = sgot->output_offset + off;
11164 }
eb043451
PB		 11165 if (r_type != R_ARM_GOT32)
11166 value += sgot->output_section->vma;
9a5aca8c 11167
f21f3fe0 11168 return _bfd_final_link_relocate (howto, input_bfd, input_section,
99e4ae17 11169 contents, rel->r_offset, value,
00a97672 11170 rel->r_addend);
f21f3fe0 11171
ba93b8ac
DJ		 11172 case R_ARM_TLS_LDO32:
11173 value = value - dtpoff_base (info);
11174
11175 return _bfd_final_link_relocate (howto, input_bfd, input_section,
00a97672
RS		 11176 contents, rel->r_offset, value,
11177 rel->r_addend);
ba93b8ac
DJ		 11178
11179 case R_ARM_TLS_LDM32:
11180 {
11181 bfd_vma off;
11182
362d30a1 11183 if (sgot == NULL)
ba93b8ac
DJ		 11184 abort ();
11185
11186 off = globals->tls_ldm_got.offset;
11187
11188 if ((off & 1) != 0)
11189 off &= ~1;
11190 else
11191 {
11192 /* If we don't know the module number, create a relocation
11193 for it. */
0e1862bb 11194 if (bfd_link_pic (info))
ba93b8ac
DJ		 11195 {
11196 Elf_Internal_Rela outrel;
ba93b8ac 11197
362d30a1 11198 if (srelgot == NULL)
ba93b8ac
DJ		 11199 abort ();
11200
00a97672 11201 outrel.r_addend = 0;
362d30a1
RS		 11202 outrel.r_offset = (sgot->output_section->vma
11203 + sgot->output_offset + off);
ba93b8ac
DJ		 11204 outrel.r_info = ELF32_R_INFO (0, R_ARM_TLS_DTPMOD32);
11205
00a97672
RS		 11206 if (globals->use_rel)
11207 bfd_put_32 (output_bfd, outrel.r_addend,
362d30a1 11208 sgot->contents + off);
ba93b8ac 11209
47beaa6a 11210 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
ba93b8ac
DJ		 11211 }
11212 else
362d30a1 11213 bfd_put_32 (output_bfd, 1, sgot->contents + off);
ba93b8ac
DJ		 11214
11215 globals->tls_ldm_got.offset |= 1;
11216 }
11217
362d30a1 11218 value = sgot->output_section->vma + sgot->output_offset + off
ba93b8ac
DJ		 11219 - (input_section->output_section->vma + input_section->output_offset + rel->r_offset);
11220
11221 return _bfd_final_link_relocate (howto, input_bfd, input_section,
11222 contents, rel->r_offset, value,
00a97672 11223 rel->r_addend);
ba93b8ac
DJ		 11224 }
11225
0855e32b
NS		 11226 case R_ARM_TLS_CALL:
11227 case R_ARM_THM_TLS_CALL:
ba93b8ac
DJ		 11228 case R_ARM_TLS_GD32:
11229 case R_ARM_TLS_IE32:
0855e32b
NS		 11230 case R_ARM_TLS_GOTDESC:
11231 case R_ARM_TLS_DESCSEQ:
11232 case R_ARM_THM_TLS_DESCSEQ:
ba93b8ac 11233 {
0855e32b
NS		 11234 bfd_vma off, offplt;
11235 int indx = 0;
ba93b8ac
DJ		 11236 char tls_type;
11237
0855e32b 11238 BFD_ASSERT (sgot != NULL);
ba93b8ac 11239
ba93b8ac
DJ		 11240 if (h != NULL)
11241 {
11242 bfd_boolean dyn;
11243 dyn = globals->root.dynamic_sections_created;
0e1862bb
L		 11244 if (WILL_CALL_FINISH_DYNAMIC_SYMBOL (dyn,
11245 bfd_link_pic (info),
11246 h)
11247 && (!bfd_link_pic (info)
ba93b8ac
DJ		 11248 || !SYMBOL_REFERENCES_LOCAL (info, h)))
11249 {
11250 *unresolved_reloc_p = FALSE;
11251 indx = h->dynindx;
11252 }
11253 off = h->got.offset;
0855e32b 11254 offplt = elf32_arm_hash_entry (h)->tlsdesc_got;
ba93b8ac
DJ		 11255 tls_type = ((struct elf32_arm_link_hash_entry *) h)->tls_type;
11256 }
11257 else
11258 {
0855e32b 11259 BFD_ASSERT (local_got_offsets != NULL);
ba93b8ac 11260 off = local_got_offsets[r_symndx];
0855e32b 11261 offplt = local_tlsdesc_gotents[r_symndx];
ba93b8ac
DJ		 11262 tls_type = elf32_arm_local_got_tls_type (input_bfd)[r_symndx];
11263 }
11264
0855e32b 11265 /* Linker relaxations happens from one of the
b38cadfb 11266 R_ARM_{GOTDESC,CALL,DESCSEQ} relocations to IE or LE. */
0855e32b 11267 if (ELF32_R_TYPE(rel->r_info) != r_type)
b38cadfb 11268 tls_type = GOT_TLS_IE;
0855e32b
NS		 11269
11270 BFD_ASSERT (tls_type != GOT_UNKNOWN);
ba93b8ac
DJ		 11271
11272 if ((off & 1) != 0)
11273 off &= ~1;
11274 else
11275 {
11276 bfd_boolean need_relocs = FALSE;
11277 Elf_Internal_Rela outrel;
ba93b8ac
DJ		 11278 int cur_off = off;
11279
11280 /* The GOT entries have not been initialized yet. Do it
11281 now, and emit any relocations. If both an IE GOT and a
11282 GD GOT are necessary, we emit the GD first. */
11283
0e1862bb 11284 if ((bfd_link_pic (info) || indx != 0)
ba93b8ac
DJ		 11285 && (h == NULL
11286 || ELF_ST_VISIBILITY (h->other) == STV_DEFAULT
11287 || h->root.type != bfd_link_hash_undefweak))
11288 {
11289 need_relocs = TRUE;
0855e32b 11290 BFD_ASSERT (srelgot != NULL);
ba93b8ac
DJ		 11291 }
11292
0855e32b
NS		 11293 if (tls_type & GOT_TLS_GDESC)
11294 {
47beaa6a
RS		 11295 bfd_byte *loc;
11296
0855e32b
NS		 11297 /* We should have relaxed, unless this is an undefined
11298 weak symbol. */
11299 BFD_ASSERT ((h && (h->root.type == bfd_link_hash_undefweak))
0e1862bb 11300 || bfd_link_pic (info));
0855e32b 11301 BFD_ASSERT (globals->sgotplt_jump_table_size + offplt + 8
99059e56 11302 <= globals->root.sgotplt->size);
0855e32b
NS		 11303
11304 outrel.r_addend = 0;
11305 outrel.r_offset = (globals->root.sgotplt->output_section->vma
11306 + globals->root.sgotplt->output_offset
11307 + offplt
11308 + globals->sgotplt_jump_table_size);
b38cadfb 11309
0855e32b
NS		 11310 outrel.r_info = ELF32_R_INFO (indx, R_ARM_TLS_DESC);
11311 sreloc = globals->root.srelplt;
11312 loc = sreloc->contents;
11313 loc += globals->next_tls_desc_index++ * RELOC_SIZE (globals);
11314 BFD_ASSERT (loc + RELOC_SIZE (globals)
99059e56 11315 <= sreloc->contents + sreloc->size);
0855e32b
NS		 11316
11317 SWAP_RELOC_OUT (globals) (output_bfd, &outrel, loc);
11318
11319 /* For globals, the first word in the relocation gets
11320 the relocation index and the top bit set, or zero,
11321 if we're binding now. For locals, it gets the
11322 symbol's offset in the tls section. */
99059e56 11323 bfd_put_32 (output_bfd,
0855e32b
NS		 11324 !h ? value - elf_hash_table (info)->tls_sec->vma
11325 : info->flags & DF_BIND_NOW ? 0
11326 : 0x80000000 | ELF32_R_SYM (outrel.r_info),
b38cadfb
NC		 11327 globals->root.sgotplt->contents + offplt
11328 + globals->sgotplt_jump_table_size);
11329
0855e32b 11330 /* Second word in the relocation is always zero. */
99059e56 11331 bfd_put_32 (output_bfd, 0,
b38cadfb
NC		 11332 globals->root.sgotplt->contents + offplt
11333 + globals->sgotplt_jump_table_size + 4);
0855e32b 11334 }
ba93b8ac
DJ		 11335 if (tls_type & GOT_TLS_GD)
11336 {
11337 if (need_relocs)
11338 {
00a97672 11339 outrel.r_addend = 0;
362d30a1
RS		 11340 outrel.r_offset = (sgot->output_section->vma
11341 + sgot->output_offset
00a97672 11342 + cur_off);
ba93b8ac 11343 outrel.r_info = ELF32_R_INFO (indx, R_ARM_TLS_DTPMOD32);
ba93b8ac 11344
00a97672
RS		 11345 if (globals->use_rel)
11346 bfd_put_32 (output_bfd, outrel.r_addend,
362d30a1 11347 sgot->contents + cur_off);
00a97672 11348
47beaa6a 11349 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
ba93b8ac
DJ		 11350
11351 if (indx == 0)
11352 bfd_put_32 (output_bfd, value - dtpoff_base (info),
362d30a1 11353 sgot->contents + cur_off + 4);
ba93b8ac
DJ		 11354 else
11355 {
00a97672 11356 outrel.r_addend = 0;
ba93b8ac
DJ		 11357 outrel.r_info = ELF32_R_INFO (indx,
11358 R_ARM_TLS_DTPOFF32);
11359 outrel.r_offset += 4;
00a97672
RS		 11360
11361 if (globals->use_rel)
11362 bfd_put_32 (output_bfd, outrel.r_addend,
362d30a1 11363 sgot->contents + cur_off + 4);
00a97672 11364
47beaa6a
RS		 11365 elf32_arm_add_dynreloc (output_bfd, info,
11366 srelgot, &outrel);
ba93b8ac
DJ		 11367 }
11368 }
11369 else
11370 {
11371 /* If we are not emitting relocations for a
11372 general dynamic reference, then we must be in a
11373 static link or an executable link with the
11374 symbol binding locally. Mark it as belonging
11375 to module 1, the executable. */
11376 bfd_put_32 (output_bfd, 1,
362d30a1 11377 sgot->contents + cur_off);
ba93b8ac 11378 bfd_put_32 (output_bfd, value - dtpoff_base (info),
362d30a1 11379 sgot->contents + cur_off + 4);
ba93b8ac
DJ		 11380 }
11381
11382 cur_off += 8;
11383 }
11384
11385 if (tls_type & GOT_TLS_IE)
11386 {
11387 if (need_relocs)
11388 {
00a97672
RS		 11389 if (indx == 0)
11390 outrel.r_addend = value - dtpoff_base (info);
11391 else
11392 outrel.r_addend = 0;
362d30a1
RS		 11393 outrel.r_offset = (sgot->output_section->vma
11394 + sgot->output_offset
ba93b8ac
DJ		 11395 + cur_off);
11396 outrel.r_info = ELF32_R_INFO (indx, R_ARM_TLS_TPOFF32);
11397
00a97672
RS		 11398 if (globals->use_rel)
11399 bfd_put_32 (output_bfd, outrel.r_addend,
362d30a1 11400 sgot->contents + cur_off);
ba93b8ac 11401
47beaa6a 11402 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
ba93b8ac
DJ		 11403 }
11404 else
11405 bfd_put_32 (output_bfd, tpoff (info, value),
362d30a1 11406 sgot->contents + cur_off);
ba93b8ac
DJ		 11407 cur_off += 4;
11408 }
11409
11410 if (h != NULL)
11411 h->got.offset |= 1;
11412 else
11413 local_got_offsets[r_symndx] |= 1;
11414 }
11415
11416 if ((tls_type & GOT_TLS_GD) && r_type != R_ARM_TLS_GD32)
11417 off += 8;
0855e32b
NS		 11418 else if (tls_type & GOT_TLS_GDESC)
11419 off = offplt;
11420
11421 if (ELF32_R_TYPE(rel->r_info) == R_ARM_TLS_CALL
11422 || ELF32_R_TYPE(rel->r_info) == R_ARM_THM_TLS_CALL)
11423 {
11424 bfd_signed_vma offset;
12352d3f
PB		 11425 /* TLS stubs are arm mode. The original symbol is a
11426 data object, so branch_type is bogus. */
11427 branch_type = ST_BRANCH_TO_ARM;
0855e32b 11428 enum elf32_arm_stub_type stub_type
34e77a92
RS		 11429 = arm_type_of_stub (info, input_section, rel,
11430 st_type, &branch_type,
0855e32b
NS		 11431 (struct elf32_arm_link_hash_entry *)h,
11432 globals->tls_trampoline, globals->root.splt,
11433 input_bfd, sym_name);
11434
11435 if (stub_type != arm_stub_none)
11436 {
11437 struct elf32_arm_stub_hash_entry *stub_entry
11438 = elf32_arm_get_stub_entry
11439 (input_section, globals->root.splt, 0, rel,
11440 globals, stub_type);
11441 offset = (stub_entry->stub_offset
11442 + stub_entry->stub_sec->output_offset
11443 + stub_entry->stub_sec->output_section->vma);
11444 }
11445 else
11446 offset = (globals->root.splt->output_section->vma
11447 + globals->root.splt->output_offset
11448 + globals->tls_trampoline);
11449
11450 if (ELF32_R_TYPE(rel->r_info) == R_ARM_TLS_CALL)
11451 {
11452 unsigned long inst;
b38cadfb
NC		 11453
11454 offset -= (input_section->output_section->vma
11455 + input_section->output_offset
11456 + rel->r_offset + 8);
0855e32b
NS		 11457
11458 inst = offset >> 2;
11459 inst &= 0x00ffffff;
11460 value = inst | (globals->use_blx ? 0xfa000000 : 0xeb000000);
11461 }
11462 else
11463 {
11464 /* Thumb blx encodes the offset in a complicated
11465 fashion. */
11466 unsigned upper_insn, lower_insn;
11467 unsigned neg;
11468
b38cadfb
NC		 11469 offset -= (input_section->output_section->vma
11470 + input_section->output_offset
0855e32b 11471 + rel->r_offset + 4);
b38cadfb 11472
12352d3f
PB		 11473 if (stub_type != arm_stub_none
11474 && arm_stub_is_thumb (stub_type))
11475 {
11476 lower_insn = 0xd000;
11477 }
11478 else
11479 {
11480 lower_insn = 0xc000;
6a631e86 11481 /* Round up the offset to a word boundary. */
12352d3f
PB		 11482 offset = (offset + 2) & ~2;
11483 }
11484
0855e32b
NS		 11485 neg = offset < 0;
11486 upper_insn = (0xf000
11487 | ((offset >> 12) & 0x3ff)
11488 | (neg << 10));
12352d3f 11489 lower_insn |= (((!((offset >> 23) & 1)) ^ neg) << 13)
0855e32b 11490 | (((!((offset >> 22) & 1)) ^ neg) << 11)
12352d3f 11491 | ((offset >> 1) & 0x7ff);
0855e32b
NS		 11492 bfd_put_16 (input_bfd, upper_insn, hit_data);
11493 bfd_put_16 (input_bfd, lower_insn, hit_data + 2);
11494 return bfd_reloc_ok;
11495 }
11496 }
11497 /* These relocations needs special care, as besides the fact
11498 they point somewhere in .gotplt, the addend must be
11499 adjusted accordingly depending on the type of instruction
6a631e86 11500 we refer to. */
0855e32b
NS		 11501 else if ((r_type == R_ARM_TLS_GOTDESC) && (tls_type & GOT_TLS_GDESC))
11502 {
11503 unsigned long data, insn;
11504 unsigned thumb;
b38cadfb 11505
0855e32b
NS		 11506 data = bfd_get_32 (input_bfd, hit_data);
11507 thumb = data & 1;
11508 data &= ~1u;
b38cadfb 11509
0855e32b
NS		 11510 if (thumb)
11511 {
11512 insn = bfd_get_16 (input_bfd, contents + rel->r_offset - data);
11513 if ((insn & 0xf000) == 0xf000 || (insn & 0xf800) == 0xe800)
11514 insn = (insn << 16)
11515 | bfd_get_16 (input_bfd,
11516 contents + rel->r_offset - data + 2);
11517 if ((insn & 0xf800c000) == 0xf000c000)
11518 /* bl/blx */
11519 value = -6;
11520 else if ((insn & 0xffffff00) == 0x4400)
11521 /* add */
11522 value = -5;
11523 else
11524 {
4eca0228 11525 _bfd_error_handler
695344c0
NC		 11526 /* xgettext:c-format */
11527 (_("%B(%A+0x%lx): unexpected Thumb instruction '0x%x' referenced by TLS_GOTDESC"),
0855e32b
NS		 11528 input_bfd, input_section,
11529 (unsigned long)rel->r_offset, insn);
11530 return bfd_reloc_notsupported;
11531 }
11532 }
11533 else
11534 {
11535 insn = bfd_get_32 (input_bfd, contents + rel->r_offset - data);
11536
11537 switch (insn >> 24)
11538 {
11539 case 0xeb: /* bl */
11540 case 0xfa: /* blx */
11541 value = -4;
11542 break;
11543
11544 case 0xe0: /* add */
11545 value = -8;
11546 break;
b38cadfb 11547
0855e32b 11548 default:
4eca0228 11549 _bfd_error_handler
695344c0
NC		 11550 /* xgettext:c-format */
11551 (_("%B(%A+0x%lx): unexpected ARM instruction '0x%x' referenced by TLS_GOTDESC"),
0855e32b
NS		 11552 input_bfd, input_section,
11553 (unsigned long)rel->r_offset, insn);
11554 return bfd_reloc_notsupported;
11555 }
11556 }
b38cadfb 11557
0855e32b
NS		 11558 value += ((globals->root.sgotplt->output_section->vma
11559 + globals->root.sgotplt->output_offset + off)
11560 - (input_section->output_section->vma
11561 + input_section->output_offset
11562 + rel->r_offset)
11563 + globals->sgotplt_jump_table_size);
11564 }
11565 else
11566 value = ((globals->root.sgot->output_section->vma
11567 + globals->root.sgot->output_offset + off)
11568 - (input_section->output_section->vma
11569 + input_section->output_offset + rel->r_offset));
ba93b8ac
DJ		 11570
11571 return _bfd_final_link_relocate (howto, input_bfd, input_section,
11572 contents, rel->r_offset, value,
00a97672 11573 rel->r_addend);
ba93b8ac
DJ		 11574 }
11575
11576 case R_ARM_TLS_LE32:
3cbc1e5e 11577 if (bfd_link_dll (info))
ba93b8ac 11578 {
4eca0228 11579 _bfd_error_handler
695344c0 11580 /* xgettext:c-format */
ba93b8ac
DJ		 11581 (_("%B(%A+0x%lx): R_ARM_TLS_LE32 relocation not permitted in shared object"),
11582 input_bfd, input_section,
11583 (long) rel->r_offset, howto->name);
46691134 11584 return bfd_reloc_notsupported;
ba93b8ac
DJ		 11585 }
11586 else
11587 value = tpoff (info, value);
906e58ca 11588
ba93b8ac 11589 return _bfd_final_link_relocate (howto, input_bfd, input_section,
00a97672
RS		 11590 contents, rel->r_offset, value,
11591 rel->r_addend);
ba93b8ac 11592
319850b4
JB		 11593 case R_ARM_V4BX:
11594 if (globals->fix_v4bx)
845b51d6
PB		 11595 {
11596 bfd_vma insn = bfd_get_32 (input_bfd, hit_data);
319850b4 11597
845b51d6
PB		 11598 /* Ensure that we have a BX instruction. */
11599 BFD_ASSERT ((insn & 0x0ffffff0) == 0x012fff10);
319850b4 11600
845b51d6
PB		 11601 if (globals->fix_v4bx == 2 && (insn & 0xf) != 0xf)
11602 {
11603 /* Branch to veneer. */
11604 bfd_vma glue_addr;
11605 glue_addr = elf32_arm_bx_glue (info, insn & 0xf);
11606 glue_addr -= input_section->output_section->vma
11607 + input_section->output_offset
11608 + rel->r_offset + 8;
11609 insn = (insn & 0xf0000000) | 0x0a000000
11610 | ((glue_addr >> 2) & 0x00ffffff);
11611 }
11612 else
11613 {
11614 /* Preserve Rm (lowest four bits) and the condition code
11615 (highest four bits). Other bits encode MOV PC,Rm. */
11616 insn = (insn & 0xf000000f) | 0x01a0f000;
11617 }
319850b4 11618
845b51d6
PB		 11619 bfd_put_32 (input_bfd, insn, hit_data);
11620 }
319850b4
JB		 11621 return bfd_reloc_ok;
11622
b6895b4f
PB		 11623 case R_ARM_MOVW_ABS_NC:
11624 case R_ARM_MOVT_ABS:
11625 case R_ARM_MOVW_PREL_NC:
11626 case R_ARM_MOVT_PREL:
92f5d02b
MS		 11627 /* Until we properly support segment-base-relative addressing then
11628 we assume the segment base to be zero, as for the group relocations.
11629 Thus R_ARM_MOVW_BREL_NC has the same semantics as R_ARM_MOVW_ABS_NC
11630 and R_ARM_MOVT_BREL has the same semantics as R_ARM_MOVT_ABS. */
11631 case R_ARM_MOVW_BREL_NC:
11632 case R_ARM_MOVW_BREL:
11633 case R_ARM_MOVT_BREL:
b6895b4f
PB		 11634 {
11635 bfd_vma insn = bfd_get_32 (input_bfd, hit_data);
11636
11637 if (globals->use_rel)
11638 {
11639 addend = ((insn >> 4) & 0xf000) | (insn & 0xfff);
39623e12 11640 signed_addend = (addend ^ 0x8000) - 0x8000;
b6895b4f 11641 }
92f5d02b 11642
b6895b4f 11643 value += signed_addend;
b6895b4f
PB		 11644
11645 if (r_type == R_ARM_MOVW_PREL_NC || r_type == R_ARM_MOVT_PREL)
11646 value -= (input_section->output_section->vma
11647 + input_section->output_offset + rel->r_offset);
11648
92f5d02b 11649 if (r_type == R_ARM_MOVW_BREL && value >= 0x10000)
99059e56 11650 return bfd_reloc_overflow;
92f5d02b 11651
35fc36a8 11652 if (branch_type == ST_BRANCH_TO_THUMB)
92f5d02b
MS		 11653 value |= 1;
11654
11655 if (r_type == R_ARM_MOVT_ABS || r_type == R_ARM_MOVT_PREL
99059e56 11656 || r_type == R_ARM_MOVT_BREL)
b6895b4f
PB		 11657 value >>= 16;
11658
11659 insn &= 0xfff0f000;
11660 insn |= value & 0xfff;
11661 insn |= (value & 0xf000) << 4;
11662 bfd_put_32 (input_bfd, insn, hit_data);
11663 }
11664 return bfd_reloc_ok;
11665
11666 case R_ARM_THM_MOVW_ABS_NC:
11667 case R_ARM_THM_MOVT_ABS:
11668 case R_ARM_THM_MOVW_PREL_NC:
11669 case R_ARM_THM_MOVT_PREL:
92f5d02b
MS		 11670 /* Until we properly support segment-base-relative addressing then
11671 we assume the segment base to be zero, as for the above relocations.
11672 Thus R_ARM_THM_MOVW_BREL_NC has the same semantics as
11673 R_ARM_THM_MOVW_ABS_NC and R_ARM_THM_MOVT_BREL has the same semantics
11674 as R_ARM_THM_MOVT_ABS. */
11675 case R_ARM_THM_MOVW_BREL_NC:
11676 case R_ARM_THM_MOVW_BREL:
11677 case R_ARM_THM_MOVT_BREL:
b6895b4f
PB		 11678 {
11679 bfd_vma insn;
906e58ca 11680
b6895b4f
PB		 11681 insn = bfd_get_16 (input_bfd, hit_data) << 16;
11682 insn |= bfd_get_16 (input_bfd, hit_data + 2);
11683
11684 if (globals->use_rel)
11685 {
11686 addend = ((insn >> 4) & 0xf000)
11687 | ((insn >> 15) & 0x0800)
11688 | ((insn >> 4) & 0x0700)
11689 | (insn & 0x00ff);
39623e12 11690 signed_addend = (addend ^ 0x8000) - 0x8000;
b6895b4f 11691 }
92f5d02b 11692
b6895b4f 11693 value += signed_addend;
b6895b4f
PB		 11694
11695 if (r_type == R_ARM_THM_MOVW_PREL_NC || r_type == R_ARM_THM_MOVT_PREL)
11696 value -= (input_section->output_section->vma
11697 + input_section->output_offset + rel->r_offset);
11698
92f5d02b 11699 if (r_type == R_ARM_THM_MOVW_BREL && value >= 0x10000)
99059e56 11700 return bfd_reloc_overflow;
92f5d02b 11701
35fc36a8 11702 if (branch_type == ST_BRANCH_TO_THUMB)
92f5d02b
MS		 11703 value |= 1;
11704
11705 if (r_type == R_ARM_THM_MOVT_ABS || r_type == R_ARM_THM_MOVT_PREL
99059e56 11706 || r_type == R_ARM_THM_MOVT_BREL)
b6895b4f
PB		 11707 value >>= 16;
11708
11709 insn &= 0xfbf08f00;
11710 insn |= (value & 0xf000) << 4;
11711 insn |= (value & 0x0800) << 15;
11712 insn |= (value & 0x0700) << 4;
11713 insn |= (value & 0x00ff);
11714
11715 bfd_put_16 (input_bfd, insn >> 16, hit_data);
11716 bfd_put_16 (input_bfd, insn & 0xffff, hit_data + 2);
11717 }
11718 return bfd_reloc_ok;
11719
4962c51a
MS		 11720 case R_ARM_ALU_PC_G0_NC:
11721 case R_ARM_ALU_PC_G1_NC:
11722 case R_ARM_ALU_PC_G0:
11723 case R_ARM_ALU_PC_G1:
11724 case R_ARM_ALU_PC_G2:
11725 case R_ARM_ALU_SB_G0_NC:
11726 case R_ARM_ALU_SB_G1_NC:
11727 case R_ARM_ALU_SB_G0:
11728 case R_ARM_ALU_SB_G1:
11729 case R_ARM_ALU_SB_G2:
11730 {
11731 bfd_vma insn = bfd_get_32 (input_bfd, hit_data);
99059e56 11732 bfd_vma pc = input_section->output_section->vma
4962c51a 11733 + input_section->output_offset + rel->r_offset;
31a91d61 11734 /* sb is the origin of the *segment* containing the symbol. */
62c34db3 11735 bfd_vma sb = sym_sec ? sym_sec->output_section->vma : 0;
99059e56
RM		 11736 bfd_vma residual;
11737 bfd_vma g_n;
4962c51a 11738 bfd_signed_vma signed_value;
99059e56
RM		 11739 int group = 0;
11740
11741 /* Determine which group of bits to select. */
11742 switch (r_type)
11743 {
11744 case R_ARM_ALU_PC_G0_NC:
11745 case R_ARM_ALU_PC_G0:
11746 case R_ARM_ALU_SB_G0_NC:
11747 case R_ARM_ALU_SB_G0:
11748 group = 0;
11749 break;
11750
11751 case R_ARM_ALU_PC_G1_NC:
11752 case R_ARM_ALU_PC_G1:
11753 case R_ARM_ALU_SB_G1_NC:
11754 case R_ARM_ALU_SB_G1:
11755 group = 1;
11756 break;
11757
11758 case R_ARM_ALU_PC_G2:
11759 case R_ARM_ALU_SB_G2:
11760 group = 2;
11761 break;
11762
11763 default:
11764 abort ();
11765 }
11766
11767 /* If REL, extract the addend from the insn. If RELA, it will
11768 have already been fetched for us. */
4962c51a 11769 if (globals->use_rel)
99059e56
RM		 11770 {
11771 int negative;
11772 bfd_vma constant = insn & 0xff;
11773 bfd_vma rotation = (insn & 0xf00) >> 8;
11774
11775 if (rotation == 0)
11776 signed_addend = constant;
11777 else
11778 {
11779 /* Compensate for the fact that in the instruction, the
11780 rotation is stored in multiples of 2 bits. */
11781 rotation *= 2;
11782
11783 /* Rotate "constant" right by "rotation" bits. */
11784 signed_addend = (constant >> rotation) |
11785 (constant << (8 * sizeof (bfd_vma) - rotation));
11786 }
11787
11788 /* Determine if the instruction is an ADD or a SUB.
11789 (For REL, this determines the sign of the addend.) */
11790 negative = identify_add_or_sub (insn);
11791 if (negative == 0)
11792 {
4eca0228 11793 _bfd_error_handler
695344c0 11794 /* xgettext:c-format */
99059e56
RM		 11795 (_("%B(%A+0x%lx): Only ADD or SUB instructions are allowed for ALU group relocations"),
11796 input_bfd, input_section,
11797 (long) rel->r_offset, howto->name);
11798 return bfd_reloc_overflow;
11799 }
11800
11801 signed_addend *= negative;
11802 }
4962c51a
MS		 11803
11804 /* Compute the value (X) to go in the place. */
99059e56
RM		 11805 if (r_type == R_ARM_ALU_PC_G0_NC
11806 || r_type == R_ARM_ALU_PC_G1_NC
11807 || r_type == R_ARM_ALU_PC_G0
11808 || r_type == R_ARM_ALU_PC_G1
11809 || r_type == R_ARM_ALU_PC_G2)
11810 /* PC relative. */
11811 signed_value = value - pc + signed_addend;
11812 else
11813 /* Section base relative. */
11814 signed_value = value - sb + signed_addend;
11815
11816 /* If the target symbol is a Thumb function, then set the
11817 Thumb bit in the address. */
35fc36a8 11818 if (branch_type == ST_BRANCH_TO_THUMB)
4962c51a
MS		 11819 signed_value |= 1;
11820
99059e56
RM		 11821 /* Calculate the value of the relevant G_n, in encoded
11822 constant-with-rotation format. */
b6518b38
NC		 11823 g_n = calculate_group_reloc_mask (signed_value < 0 ? - signed_value : signed_value,
11824 group, &residual);
99059e56
RM		 11825
11826 /* Check for overflow if required. */
11827 if ((r_type == R_ARM_ALU_PC_G0
11828 || r_type == R_ARM_ALU_PC_G1
11829 || r_type == R_ARM_ALU_PC_G2
11830 || r_type == R_ARM_ALU_SB_G0
11831 || r_type == R_ARM_ALU_SB_G1
11832 || r_type == R_ARM_ALU_SB_G2) && residual != 0)
11833 {
4eca0228 11834 _bfd_error_handler
695344c0 11835 /* xgettext:c-format */
99059e56
RM		 11836 (_("%B(%A+0x%lx): Overflow whilst splitting 0x%lx for group relocation %s"),
11837 input_bfd, input_section,
b6518b38
NC		 11838 (long) rel->r_offset, signed_value < 0 ? - signed_value : signed_value,
11839 howto->name);
99059e56
RM		 11840 return bfd_reloc_overflow;
11841 }
11842
11843 /* Mask out the value and the ADD/SUB part of the opcode; take care
11844 not to destroy the S bit. */
11845 insn &= 0xff1ff000;
11846
11847 /* Set the opcode according to whether the value to go in the
11848 place is negative. */
11849 if (signed_value < 0)
11850 insn |= 1 << 22;
11851 else
11852 insn |= 1 << 23;
11853
11854 /* Encode the offset. */
11855 insn |= g_n;
4962c51a
MS		 11856
11857 bfd_put_32 (input_bfd, insn, hit_data);
11858 }
11859 return bfd_reloc_ok;
11860
11861 case R_ARM_LDR_PC_G0:
11862 case R_ARM_LDR_PC_G1:
11863 case R_ARM_LDR_PC_G2:
11864 case R_ARM_LDR_SB_G0:
11865 case R_ARM_LDR_SB_G1:
11866 case R_ARM_LDR_SB_G2:
11867 {
11868 bfd_vma insn = bfd_get_32 (input_bfd, hit_data);
99059e56 11869 bfd_vma pc = input_section->output_section->vma
4962c51a 11870 + input_section->output_offset + rel->r_offset;
31a91d61 11871 /* sb is the origin of the *segment* containing the symbol. */
62c34db3 11872 bfd_vma sb = sym_sec ? sym_sec->output_section->vma : 0;
99059e56 11873 bfd_vma residual;
4962c51a 11874 bfd_signed_vma signed_value;
99059e56
RM		 11875 int group = 0;
11876
11877 /* Determine which groups of bits to calculate. */
11878 switch (r_type)
11879 {
11880 case R_ARM_LDR_PC_G0:
11881 case R_ARM_LDR_SB_G0:
11882 group = 0;
11883 break;
11884
11885 case R_ARM_LDR_PC_G1:
11886 case R_ARM_LDR_SB_G1:
11887 group = 1;
11888 break;
11889
11890 case R_ARM_LDR_PC_G2:
11891 case R_ARM_LDR_SB_G2:
11892 group = 2;
11893 break;
11894
11895 default:
11896 abort ();
11897 }
11898
11899 /* If REL, extract the addend from the insn. If RELA, it will
11900 have already been fetched for us. */
4962c51a 11901 if (globals->use_rel)
99059e56
RM		 11902 {
11903 int negative = (insn & (1 << 23)) ? 1 : -1;
11904 signed_addend = negative * (insn & 0xfff);
11905 }
4962c51a
MS		 11906
11907 /* Compute the value (X) to go in the place. */
99059e56
RM		 11908 if (r_type == R_ARM_LDR_PC_G0
11909 || r_type == R_ARM_LDR_PC_G1
11910 || r_type == R_ARM_LDR_PC_G2)
11911 /* PC relative. */
11912 signed_value = value - pc + signed_addend;
11913 else
11914 /* Section base relative. */
11915 signed_value = value - sb + signed_addend;
11916
11917 /* Calculate the value of the relevant G_{n-1} to obtain
11918 the residual at that stage. */
b6518b38
NC		 11919 calculate_group_reloc_mask (signed_value < 0 ? - signed_value : signed_value,
11920 group - 1, &residual);
99059e56
RM		 11921
11922 /* Check for overflow. */
11923 if (residual >= 0x1000)
11924 {
4eca0228 11925 _bfd_error_handler
695344c0 11926 /* xgettext:c-format */
99059e56 11927 (_("%B(%A+0x%lx): Overflow whilst splitting 0x%lx for group relocation %s"),
b6518b38
NC		 11928 input_bfd, input_section,
11929 (long) rel->r_offset, labs (signed_value), howto->name);
99059e56
RM		 11930 return bfd_reloc_overflow;
11931 }
11932
11933 /* Mask out the value and U bit. */
11934 insn &= 0xff7ff000;
11935
11936 /* Set the U bit if the value to go in the place is non-negative. */
11937 if (signed_value >= 0)
11938 insn |= 1 << 23;
11939
11940 /* Encode the offset. */
11941 insn |= residual;
4962c51a
MS		 11942
11943 bfd_put_32 (input_bfd, insn, hit_data);
11944 }
11945 return bfd_reloc_ok;
11946
11947 case R_ARM_LDRS_PC_G0:
11948 case R_ARM_LDRS_PC_G1:
11949 case R_ARM_LDRS_PC_G2:
11950 case R_ARM_LDRS_SB_G0:
11951 case R_ARM_LDRS_SB_G1:
11952 case R_ARM_LDRS_SB_G2:
11953 {
11954 bfd_vma insn = bfd_get_32 (input_bfd, hit_data);
99059e56 11955 bfd_vma pc = input_section->output_section->vma
4962c51a 11956 + input_section->output_offset + rel->r_offset;
31a91d61 11957 /* sb is the origin of the *segment* containing the symbol. */
62c34db3 11958 bfd_vma sb = sym_sec ? sym_sec->output_section->vma : 0;
99059e56 11959 bfd_vma residual;
4962c51a 11960 bfd_signed_vma signed_value;
99059e56
RM		 11961 int group = 0;
11962
11963 /* Determine which groups of bits to calculate. */
11964 switch (r_type)
11965 {
11966 case R_ARM_LDRS_PC_G0:
11967 case R_ARM_LDRS_SB_G0:
11968 group = 0;
11969 break;
11970
11971 case R_ARM_LDRS_PC_G1:
11972 case R_ARM_LDRS_SB_G1:
11973 group = 1;
11974 break;
11975
11976 case R_ARM_LDRS_PC_G2:
11977 case R_ARM_LDRS_SB_G2:
11978 group = 2;
11979 break;
11980
11981 default:
11982 abort ();
11983 }
11984
11985 /* If REL, extract the addend from the insn. If RELA, it will
11986 have already been fetched for us. */
4962c51a 11987 if (globals->use_rel)
99059e56
RM		 11988 {
11989 int negative = (insn & (1 << 23)) ? 1 : -1;
11990 signed_addend = negative * (((insn & 0xf00) >> 4) + (insn & 0xf));
11991 }
4962c51a
MS		 11992
11993 /* Compute the value (X) to go in the place. */
99059e56
RM		 11994 if (r_type == R_ARM_LDRS_PC_G0
11995 || r_type == R_ARM_LDRS_PC_G1
11996 || r_type == R_ARM_LDRS_PC_G2)
11997 /* PC relative. */
11998 signed_value = value - pc + signed_addend;
11999 else
12000 /* Section base relative. */
12001 signed_value = value - sb + signed_addend;
12002
12003 /* Calculate the value of the relevant G_{n-1} to obtain
12004 the residual at that stage. */
b6518b38
NC		 12005 calculate_group_reloc_mask (signed_value < 0 ? - signed_value : signed_value,
12006 group - 1, &residual);
99059e56
RM		 12007
12008 /* Check for overflow. */
12009 if (residual >= 0x100)
12010 {
4eca0228 12011 _bfd_error_handler
695344c0 12012 /* xgettext:c-format */
99059e56 12013 (_("%B(%A+0x%lx): Overflow whilst splitting 0x%lx for group relocation %s"),
b6518b38
NC		 12014 input_bfd, input_section,
12015 (long) rel->r_offset, labs (signed_value), howto->name);
99059e56
RM		 12016 return bfd_reloc_overflow;
12017 }
12018
12019 /* Mask out the value and U bit. */
12020 insn &= 0xff7ff0f0;
12021
12022 /* Set the U bit if the value to go in the place is non-negative. */
12023 if (signed_value >= 0)
12024 insn |= 1 << 23;
12025
12026 /* Encode the offset. */
12027 insn |= ((residual & 0xf0) << 4) | (residual & 0xf);
4962c51a
MS		 12028
12029 bfd_put_32 (input_bfd, insn, hit_data);
12030 }
12031 return bfd_reloc_ok;
12032
12033 case R_ARM_LDC_PC_G0:
12034 case R_ARM_LDC_PC_G1:
12035 case R_ARM_LDC_PC_G2:
12036 case R_ARM_LDC_SB_G0:
12037 case R_ARM_LDC_SB_G1:
12038 case R_ARM_LDC_SB_G2:
12039 {
12040 bfd_vma insn = bfd_get_32 (input_bfd, hit_data);
99059e56 12041 bfd_vma pc = input_section->output_section->vma
4962c51a 12042 + input_section->output_offset + rel->r_offset;
31a91d61 12043 /* sb is the origin of the *segment* containing the symbol. */
62c34db3 12044 bfd_vma sb = sym_sec ? sym_sec->output_section->vma : 0;
99059e56 12045 bfd_vma residual;
4962c51a 12046 bfd_signed_vma signed_value;
99059e56
RM		 12047 int group = 0;
12048
12049 /* Determine which groups of bits to calculate. */
12050 switch (r_type)
12051 {
12052 case R_ARM_LDC_PC_G0:
12053 case R_ARM_LDC_SB_G0:
12054 group = 0;
12055 break;
12056
12057 case R_ARM_LDC_PC_G1:
12058 case R_ARM_LDC_SB_G1:
12059 group = 1;
12060 break;
12061
12062 case R_ARM_LDC_PC_G2:
12063 case R_ARM_LDC_SB_G2:
12064 group = 2;
12065 break;
12066
12067 default:
12068 abort ();
12069 }
12070
12071 /* If REL, extract the addend from the insn. If RELA, it will
12072 have already been fetched for us. */
4962c51a 12073 if (globals->use_rel)
99059e56
RM		 12074 {
12075 int negative = (insn & (1 << 23)) ? 1 : -1;
12076 signed_addend = negative * ((insn & 0xff) << 2);
12077 }
4962c51a
MS		 12078
12079 /* Compute the value (X) to go in the place. */
99059e56
RM		 12080 if (r_type == R_ARM_LDC_PC_G0
12081 || r_type == R_ARM_LDC_PC_G1
12082 || r_type == R_ARM_LDC_PC_G2)
12083 /* PC relative. */
12084 signed_value = value - pc + signed_addend;
12085 else
12086 /* Section base relative. */
12087 signed_value = value - sb + signed_addend;
12088
12089 /* Calculate the value of the relevant G_{n-1} to obtain
12090 the residual at that stage. */
b6518b38
NC		 12091 calculate_group_reloc_mask (signed_value < 0 ? - signed_value : signed_value,
12092 group - 1, &residual);
99059e56
RM		 12093
12094 /* Check for overflow. (The absolute value to go in the place must be
12095 divisible by four and, after having been divided by four, must
12096 fit in eight bits.) */
12097 if ((residual & 0x3) != 0 || residual >= 0x400)
12098 {
4eca0228 12099 _bfd_error_handler
695344c0 12100 /* xgettext:c-format */
99059e56
RM		 12101 (_("%B(%A+0x%lx): Overflow whilst splitting 0x%lx for group relocation %s"),
12102 input_bfd, input_section,
b6518b38 12103 (long) rel->r_offset, labs (signed_value), howto->name);
99059e56
RM		 12104 return bfd_reloc_overflow;
12105 }
12106
12107 /* Mask out the value and U bit. */
12108 insn &= 0xff7fff00;
12109
12110 /* Set the U bit if the value to go in the place is non-negative. */
12111 if (signed_value >= 0)
12112 insn |= 1 << 23;
12113
12114 /* Encode the offset. */
12115 insn |= residual >> 2;
4962c51a
MS		 12116
12117 bfd_put_32 (input_bfd, insn, hit_data);
12118 }
12119 return bfd_reloc_ok;
12120
72d98d16
MG		 12121 case R_ARM_THM_ALU_ABS_G0_NC:
12122 case R_ARM_THM_ALU_ABS_G1_NC:
12123 case R_ARM_THM_ALU_ABS_G2_NC:
12124 case R_ARM_THM_ALU_ABS_G3_NC:
12125 {
12126 const int shift_array[4] = {0, 8, 16, 24};
12127 bfd_vma insn = bfd_get_16 (input_bfd, hit_data);
12128 bfd_vma addr = value;
12129 int shift = shift_array[r_type - R_ARM_THM_ALU_ABS_G0_NC];
12130
12131 /* Compute address. */
12132 if (globals->use_rel)
12133 signed_addend = insn & 0xff;
12134 addr += signed_addend;
12135 if (branch_type == ST_BRANCH_TO_THUMB)
12136 addr |= 1;
12137 /* Clean imm8 insn. */
12138 insn &= 0xff00;
12139 /* And update with correct part of address. */
12140 insn |= (addr >> shift) & 0xff;
12141 /* Update insn. */
12142 bfd_put_16 (input_bfd, insn, hit_data);
12143 }
12144
12145 *unresolved_reloc_p = FALSE;
12146 return bfd_reloc_ok;
12147
252b5132
RH		 12148 default:
12149 return bfd_reloc_notsupported;
12150 }
12151}
12152
98c1d4aa
NC		 12153/* Add INCREMENT to the reloc (of type HOWTO) at ADDRESS. */
12154static void
57e8b36a
NC		 12155arm_add_to_rel (bfd * abfd,
12156 bfd_byte * address,
12157 reloc_howto_type * howto,
12158 bfd_signed_vma increment)
98c1d4aa 12159{
98c1d4aa
NC		 12160 bfd_signed_vma addend;
12161
bd97cb95
DJ		 12162 if (howto->type == R_ARM_THM_CALL
12163 || howto->type == R_ARM_THM_JUMP24)
98c1d4aa 12164 {
9a5aca8c
AM		 12165 int upper_insn, lower_insn;
12166 int upper, lower;
98c1d4aa 12167
9a5aca8c
AM		 12168 upper_insn = bfd_get_16 (abfd, address);
12169 lower_insn = bfd_get_16 (abfd, address + 2);
12170 upper = upper_insn & 0x7ff;
12171 lower = lower_insn & 0x7ff;
12172
12173 addend = (upper << 12) | (lower << 1);
ddda4409 12174 addend += increment;
9a5aca8c 12175 addend >>= 1;
98c1d4aa 12176
9a5aca8c
AM		 12177 upper_insn = (upper_insn & 0xf800) | ((addend >> 11) & 0x7ff);
12178 lower_insn = (lower_insn & 0xf800) | (addend & 0x7ff);
12179
dc810e39
AM		 12180 bfd_put_16 (abfd, (bfd_vma) upper_insn, address);
12181 bfd_put_16 (abfd, (bfd_vma) lower_insn, address + 2);
9a5aca8c
AM		 12182 }
12183 else
12184 {
12185 bfd_vma contents;
12186
12187 contents = bfd_get_32 (abfd, address);
12188
12189 /* Get the (signed) value from the instruction. */
12190 addend = contents & howto->src_mask;
12191 if (addend & ((howto->src_mask + 1) >> 1))
12192 {
12193 bfd_signed_vma mask;
12194
12195 mask = -1;
12196 mask &= ~ howto->src_mask;
12197 addend |= mask;
12198 }
12199
12200 /* Add in the increment, (which is a byte value). */
12201 switch (howto->type)
12202 {
12203 default:
12204 addend += increment;
12205 break;
12206
12207 case R_ARM_PC24:
c6596c5e 12208 case R_ARM_PLT32:
5b5bb741
PB		 12209 case R_ARM_CALL:
12210 case R_ARM_JUMP24:
9a5aca8c 12211 addend <<= howto->size;
dc810e39 12212 addend += increment;
9a5aca8c
AM		 12213
12214 /* Should we check for overflow here ? */
12215
12216 /* Drop any undesired bits. */
12217 addend >>= howto->rightshift;
12218 break;
12219 }
12220
12221 contents = (contents & ~ howto->dst_mask) | (addend & howto->dst_mask);
12222
12223 bfd_put_32 (abfd, contents, address);
ddda4409 12224 }
98c1d4aa 12225}
252b5132 12226
ba93b8ac
DJ		 12227#define IS_ARM_TLS_RELOC(R_TYPE) \
12228 ((R_TYPE) == R_ARM_TLS_GD32 \
12229 || (R_TYPE) == R_ARM_TLS_LDO32 \
12230 || (R_TYPE) == R_ARM_TLS_LDM32 \
12231 || (R_TYPE) == R_ARM_TLS_DTPOFF32 \
12232 || (R_TYPE) == R_ARM_TLS_DTPMOD32 \
12233 || (R_TYPE) == R_ARM_TLS_TPOFF32 \
12234 || (R_TYPE) == R_ARM_TLS_LE32 \
0855e32b
NS		 12235 || (R_TYPE) == R_ARM_TLS_IE32 \
12236 || IS_ARM_TLS_GNU_RELOC (R_TYPE))
12237
12238/* Specific set of relocations for the gnu tls dialect. */
12239#define IS_ARM_TLS_GNU_RELOC(R_TYPE) \
12240 ((R_TYPE) == R_ARM_TLS_GOTDESC \
12241 || (R_TYPE) == R_ARM_TLS_CALL \
12242 || (R_TYPE) == R_ARM_THM_TLS_CALL \
12243 || (R_TYPE) == R_ARM_TLS_DESCSEQ \
12244 || (R_TYPE) == R_ARM_THM_TLS_DESCSEQ)
ba93b8ac 12245
252b5132 12246/* Relocate an ARM ELF section. */
906e58ca 12247
b34976b6 12248static bfd_boolean
57e8b36a
NC		 12249elf32_arm_relocate_section (bfd * output_bfd,
12250 struct bfd_link_info * info,
12251 bfd * input_bfd,
12252 asection * input_section,
12253 bfd_byte * contents,
12254 Elf_Internal_Rela * relocs,
12255 Elf_Internal_Sym * local_syms,
12256 asection ** local_sections)
252b5132 12257{
b34976b6
AM		 12258 Elf_Internal_Shdr *symtab_hdr;
12259 struct elf_link_hash_entry **sym_hashes;
12260 Elf_Internal_Rela *rel;
12261 Elf_Internal_Rela *relend;
12262 const char *name;
b32d3aa2 12263 struct elf32_arm_link_hash_table * globals;
252b5132 12264
4e7fd91e 12265 globals = elf32_arm_hash_table (info);
4dfe6ac6
NC		 12266 if (globals == NULL)
12267 return FALSE;
b491616a 12268
0ffa91dd 12269 symtab_hdr = & elf_symtab_hdr (input_bfd);
252b5132
RH		 12270 sym_hashes = elf_sym_hashes (input_bfd);
12271
12272 rel = relocs;
12273 relend = relocs + input_section->reloc_count;
12274 for (; rel < relend; rel++)
12275 {
ba96a88f
NC		 12276 int r_type;
12277 reloc_howto_type * howto;
12278 unsigned long r_symndx;
12279 Elf_Internal_Sym * sym;
12280 asection * sec;
252b5132 12281 struct elf_link_hash_entry * h;
ba96a88f
NC		 12282 bfd_vma relocation;
12283 bfd_reloc_status_type r;
12284 arelent bfd_reloc;
ba93b8ac 12285 char sym_type;
0945cdfd 12286 bfd_boolean unresolved_reloc = FALSE;
f2a9dd69 12287 char *error_message = NULL;
f21f3fe0 12288
252b5132 12289 r_symndx = ELF32_R_SYM (rel->r_info);
ba96a88f 12290 r_type = ELF32_R_TYPE (rel->r_info);
b32d3aa2 12291 r_type = arm_real_reloc_type (globals, r_type);
252b5132 12292
ba96a88f 12293 if ( r_type == R_ARM_GNU_VTENTRY
99059e56
RM		 12294 || r_type == R_ARM_GNU_VTINHERIT)
12295 continue;
252b5132 12296
b32d3aa2 12297 bfd_reloc.howto = elf32_arm_howto_from_type (r_type);
ba96a88f 12298 howto = bfd_reloc.howto;
252b5132 12299
252b5132
RH		 12300 h = NULL;
12301 sym = NULL;
12302 sec = NULL;
9b485d32 12303
252b5132
RH		 12304 if (r_symndx < symtab_hdr->sh_info)
12305 {
12306 sym = local_syms + r_symndx;
ba93b8ac 12307 sym_type = ELF32_ST_TYPE (sym->st_info);
252b5132 12308 sec = local_sections[r_symndx];
ffcb4889
NS		 12309
12310 /* An object file might have a reference to a local
12311 undefined symbol. This is a daft object file, but we
12312 should at least do something about it. V4BX & NONE
12313 relocations do not use the symbol and are explicitly
77b4f08f
TS		 12314 allowed to use the undefined symbol, so allow those.
12315 Likewise for relocations against STN_UNDEF. */
ffcb4889
NS		 12316 if (r_type != R_ARM_V4BX
12317 && r_type != R_ARM_NONE
77b4f08f 12318 && r_symndx != STN_UNDEF
ffcb4889
NS		 12319 && bfd_is_und_section (sec)
12320 && ELF_ST_BIND (sym->st_info) != STB_WEAK)
1a72702b
AM		 12321 (*info->callbacks->undefined_symbol)
12322 (info, bfd_elf_string_from_elf_section
12323 (input_bfd, symtab_hdr->sh_link, sym->st_name),
12324 input_bfd, input_section,
12325 rel->r_offset, TRUE);
b38cadfb 12326
4e7fd91e 12327 if (globals->use_rel)
f8df10f4 12328 {
4e7fd91e
PB		 12329 relocation = (sec->output_section->vma
12330 + sec->output_offset
12331 + sym->st_value);
0e1862bb 12332 if (!bfd_link_relocatable (info)
ab96bf03
AM		 12333 && (sec->flags & SEC_MERGE)
12334 && ELF_ST_TYPE (sym->st_info) == STT_SECTION)
f8df10f4 12335 {
4e7fd91e
PB		 12336 asection *msec;
12337 bfd_vma addend, value;
12338
39623e12 12339 switch (r_type)
4e7fd91e 12340 {
39623e12
PB		 12341 case R_ARM_MOVW_ABS_NC:
12342 case R_ARM_MOVT_ABS:
12343 value = bfd_get_32 (input_bfd, contents + rel->r_offset);
12344 addend = ((value & 0xf0000) >> 4) | (value & 0xfff);
12345 addend = (addend ^ 0x8000) - 0x8000;
12346 break;
f8df10f4 12347
39623e12
PB		 12348 case R_ARM_THM_MOVW_ABS_NC:
12349 case R_ARM_THM_MOVT_ABS:
12350 value = bfd_get_16 (input_bfd, contents + rel->r_offset)
12351 << 16;
12352 value |= bfd_get_16 (input_bfd,
12353 contents + rel->r_offset + 2);
12354 addend = ((value & 0xf7000) >> 4) | (value & 0xff)
12355 | ((value & 0x04000000) >> 15);
12356 addend = (addend ^ 0x8000) - 0x8000;
12357 break;
f8df10f4 12358
39623e12
PB		 12359 default:
12360 if (howto->rightshift
12361 || (howto->src_mask & (howto->src_mask + 1)))
12362 {
4eca0228 12363 _bfd_error_handler
695344c0 12364 /* xgettext:c-format */
39623e12
PB		 12365 (_("%B(%A+0x%lx): %s relocation against SEC_MERGE section"),
12366 input_bfd, input_section,
12367 (long) rel->r_offset, howto->name);
12368 return FALSE;
12369 }
12370
12371 value = bfd_get_32 (input_bfd, contents + rel->r_offset);
12372
12373 /* Get the (signed) value from the instruction. */
12374 addend = value & howto->src_mask;
12375 if (addend & ((howto->src_mask + 1) >> 1))
12376 {
12377 bfd_signed_vma mask;
12378
12379 mask = -1;
12380 mask &= ~ howto->src_mask;
12381 addend |= mask;
12382 }
12383 break;
4e7fd91e 12384 }
39623e12 12385
4e7fd91e
PB		 12386 msec = sec;
12387 addend =
12388 _bfd_elf_rel_local_sym (output_bfd, sym, &msec, addend)
12389 - relocation;
12390 addend += msec->output_section->vma + msec->output_offset;
39623e12 12391
cc643b88 12392 /* Cases here must match those in the preceding
39623e12
PB		 12393 switch statement. */
12394 switch (r_type)
12395 {
12396 case R_ARM_MOVW_ABS_NC:
12397 case R_ARM_MOVT_ABS:
12398 value = (value & 0xfff0f000) | ((addend & 0xf000) << 4)
12399 | (addend & 0xfff);
12400 bfd_put_32 (input_bfd, value, contents + rel->r_offset);
12401 break;
12402
12403 case R_ARM_THM_MOVW_ABS_NC:
12404 case R_ARM_THM_MOVT_ABS:
12405 value = (value & 0xfbf08f00) | ((addend & 0xf700) << 4)
12406 | (addend & 0xff) | ((addend & 0x0800) << 15);
12407 bfd_put_16 (input_bfd, value >> 16,
12408 contents + rel->r_offset);
12409 bfd_put_16 (input_bfd, value,
12410 contents + rel->r_offset + 2);
12411 break;
12412
12413 default:
12414 value = (value & ~ howto->dst_mask)
12415 | (addend & howto->dst_mask);
12416 bfd_put_32 (input_bfd, value, contents + rel->r_offset);
12417 break;
12418 }
f8df10f4 12419 }
f8df10f4 12420 }
4e7fd91e
PB		 12421 else
12422 relocation = _bfd_elf_rela_local_sym (output_bfd, sym, &sec, rel);
252b5132
RH		 12423 }
12424 else
12425 {
62d887d4 12426 bfd_boolean warned, ignored;
560e09e9 12427
b2a8e766
AM		 12428 RELOC_FOR_GLOBAL_SYMBOL (info, input_bfd, input_section, rel,
12429 r_symndx, symtab_hdr, sym_hashes,
12430 h, sec, relocation,
62d887d4 12431 unresolved_reloc, warned, ignored);
ba93b8ac
DJ		 12432
12433 sym_type = h->type;
252b5132
RH		 12434 }
12435
dbaa2011 12436 if (sec != NULL && discarded_section (sec))
e4067dbb 12437 RELOC_AGAINST_DISCARDED_SECTION (info, input_bfd, input_section,
545fd46b 12438 rel, 1, relend, howto, 0, contents);
ab96bf03 12439
0e1862bb 12440 if (bfd_link_relocatable (info))
ab96bf03
AM		 12441 {
12442 /* This is a relocatable link. We don't have to change
12443 anything, unless the reloc is against a section symbol,
12444 in which case we have to adjust according to where the
12445 section symbol winds up in the output section. */
12446 if (sym != NULL && ELF_ST_TYPE (sym->st_info) == STT_SECTION)
12447 {
12448 if (globals->use_rel)
12449 arm_add_to_rel (input_bfd, contents + rel->r_offset,
12450 howto, (bfd_signed_vma) sec->output_offset);
12451 else
12452 rel->r_addend += sec->output_offset;
12453 }
12454 continue;
12455 }
12456
252b5132
RH		 12457 if (h != NULL)
12458 name = h->root.root.string;
12459 else
12460 {
12461 name = (bfd_elf_string_from_elf_section
12462 (input_bfd, symtab_hdr->sh_link, sym->st_name));
12463 if (name == NULL || *name == '\0')
12464 name = bfd_section_name (input_bfd, sec);
12465 }
f21f3fe0 12466
cf35638d 12467 if (r_symndx != STN_UNDEF
ba93b8ac
DJ		 12468 && r_type != R_ARM_NONE
12469 && (h == NULL
12470 || h->root.type == bfd_link_hash_defined
12471 || h->root.type == bfd_link_hash_defweak)
12472 && IS_ARM_TLS_RELOC (r_type) != (sym_type == STT_TLS))
12473 {
4eca0228 12474 _bfd_error_handler
ba93b8ac 12475 ((sym_type == STT_TLS
695344c0 12476 /* xgettext:c-format */
ba93b8ac 12477 ? _("%B(%A+0x%lx): %s used with TLS symbol %s")
695344c0 12478 /* xgettext:c-format */
ba93b8ac
DJ		 12479 : _("%B(%A+0x%lx): %s used with non-TLS symbol %s")),
12480 input_bfd,
12481 input_section,
12482 (long) rel->r_offset,
12483 howto->name,
12484 name);
12485 }
12486
0855e32b 12487 /* We call elf32_arm_final_link_relocate unless we're completely
99059e56
RM		 12488 done, i.e., the relaxation produced the final output we want,
12489 and we won't let anybody mess with it. Also, we have to do
12490 addend adjustments in case of a R_ARM_TLS_GOTDESC relocation
6a631e86 12491 both in relaxed and non-relaxed cases. */
39d911fc
TP		 12492 if ((elf32_arm_tls_transition (info, r_type, h) != (unsigned)r_type)
12493 || (IS_ARM_TLS_GNU_RELOC (r_type)
12494 && !((h ? elf32_arm_hash_entry (h)->tls_type :
12495 elf32_arm_local_got_tls_type (input_bfd)[r_symndx])
12496 & GOT_TLS_GDESC)))
12497 {
12498 r = elf32_arm_tls_relax (globals, input_bfd, input_section,
12499 contents, rel, h == NULL);
12500 /* This may have been marked unresolved because it came from
12501 a shared library. But we've just dealt with that. */
12502 unresolved_reloc = 0;
12503 }
12504 else
12505 r = bfd_reloc_continue;
b38cadfb 12506
39d911fc
TP		 12507 if (r == bfd_reloc_continue)
12508 {
12509 unsigned char branch_type =
12510 h ? ARM_GET_SYM_BRANCH_TYPE (h->target_internal)
12511 : ARM_GET_SYM_BRANCH_TYPE (sym->st_target_internal);
12512
12513 r = elf32_arm_final_link_relocate (howto, input_bfd, output_bfd,
12514 input_section, contents, rel,
12515 relocation, info, sec, name,
12516 sym_type, branch_type, h,
12517 &unresolved_reloc,
12518 &error_message);
12519 }
0945cdfd
DJ		 12520
12521 /* Dynamic relocs are not propagated for SEC_DEBUGGING sections
12522 because such sections are not SEC_ALLOC and thus ld.so will
12523 not process them. */
12524 if (unresolved_reloc
99059e56
RM		 12525 && !((input_section->flags & SEC_DEBUGGING) != 0
12526 && h->def_dynamic)
1d5316ab
AM		 12527 && _bfd_elf_section_offset (output_bfd, info, input_section,
12528 rel->r_offset) != (bfd_vma) -1)
0945cdfd 12529 {
4eca0228 12530 _bfd_error_handler
695344c0 12531 /* xgettext:c-format */
843fe662
L		 12532 (_("%B(%A+0x%lx): unresolvable %s relocation against symbol `%s'"),
12533 input_bfd,
12534 input_section,
12535 (long) rel->r_offset,
12536 howto->name,
12537 h->root.root.string);
0945cdfd
DJ		 12538 return FALSE;
12539 }
252b5132
RH		 12540
12541 if (r != bfd_reloc_ok)
12542 {
252b5132
RH		 12543 switch (r)
12544 {
12545 case bfd_reloc_overflow:
cf919dfd
PB		 12546 /* If the overflowing reloc was to an undefined symbol,
12547 we have already printed one error message and there
12548 is no point complaining again. */
1a72702b
AM		 12549 if (!h || h->root.type != bfd_link_hash_undefined)
12550 (*info->callbacks->reloc_overflow)
12551 (info, (h ? &h->root : NULL), name, howto->name,
12552 (bfd_vma) 0, input_bfd, input_section, rel->r_offset);
252b5132
RH		 12553 break;
12554
12555 case bfd_reloc_undefined:
1a72702b
AM		 12556 (*info->callbacks->undefined_symbol)
12557 (info, name, input_bfd, input_section, rel->r_offset, TRUE);
252b5132
RH		 12558 break;
12559
12560 case bfd_reloc_outofrange:
f2a9dd69 12561 error_message = _("out of range");
252b5132
RH		 12562 goto common_error;
12563
12564 case bfd_reloc_notsupported:
f2a9dd69 12565 error_message = _("unsupported relocation");
252b5132
RH		 12566 goto common_error;
12567
12568 case bfd_reloc_dangerous:
f2a9dd69 12569 /* error_message should already be set. */
252b5132
RH		 12570 goto common_error;
12571
12572 default:
f2a9dd69 12573 error_message = _("unknown error");
8029a119 12574 /* Fall through. */
252b5132
RH		 12575
12576 common_error:
f2a9dd69 12577 BFD_ASSERT (error_message != NULL);
1a72702b
AM		 12578 (*info->callbacks->reloc_dangerous)
12579 (info, error_message, input_bfd, input_section, rel->r_offset);
252b5132
RH		 12580 break;
12581 }
12582 }
12583 }
12584
b34976b6 12585 return TRUE;
252b5132
RH		 12586}
12587
91d6fa6a 12588/* Add a new unwind edit to the list described by HEAD, TAIL. If TINDEX is zero,
2468f9c9 12589 adds the edit to the start of the list. (The list must be built in order of
91d6fa6a 12590 ascending TINDEX: the function's callers are primarily responsible for
2468f9c9
PB		 12591 maintaining that condition). */
12592
12593static void
12594add_unwind_table_edit (arm_unwind_table_edit **head,
12595 arm_unwind_table_edit **tail,
12596 arm_unwind_edit_type type,
12597 asection *linked_section,
91d6fa6a 12598 unsigned int tindex)
2468f9c9 12599{
21d799b5
NC		 12600 arm_unwind_table_edit *new_edit = (arm_unwind_table_edit *)
12601 xmalloc (sizeof (arm_unwind_table_edit));
b38cadfb 12602
2468f9c9
PB		 12603 new_edit->type = type;
12604 new_edit->linked_section = linked_section;
91d6fa6a 12605 new_edit->index = tindex;
b38cadfb 12606
91d6fa6a 12607 if (tindex > 0)
2468f9c9
PB		 12608 {
12609 new_edit->next = NULL;
12610
12611 if (*tail)
12612 (*tail)->next = new_edit;
12613
12614 (*tail) = new_edit;
12615
12616 if (!*head)
12617 (*head) = new_edit;
12618 }
12619 else
12620 {
12621 new_edit->next = *head;
12622
12623 if (!*tail)
12624 *tail = new_edit;
12625
12626 *head = new_edit;
12627 }
12628}
12629
12630static _arm_elf_section_data *get_arm_elf_section_data (asection *);
12631
12632/* Increase the size of EXIDX_SEC by ADJUST bytes. ADJUST mau be negative. */
12633static void
12634adjust_exidx_size(asection *exidx_sec, int adjust)
12635{
12636 asection *out_sec;
12637
12638 if (!exidx_sec->rawsize)
12639 exidx_sec->rawsize = exidx_sec->size;
12640
12641 bfd_set_section_size (exidx_sec->owner, exidx_sec, exidx_sec->size + adjust);
12642 out_sec = exidx_sec->output_section;
12643 /* Adjust size of output section. */
12644 bfd_set_section_size (out_sec->owner, out_sec, out_sec->size +adjust);
12645}
12646
12647/* Insert an EXIDX_CANTUNWIND marker at the end of a section. */
12648static void
12649insert_cantunwind_after(asection *text_sec, asection *exidx_sec)
12650{
12651 struct _arm_elf_section_data *exidx_arm_data;
12652
12653 exidx_arm_data = get_arm_elf_section_data (exidx_sec);
12654 add_unwind_table_edit (
12655 &exidx_arm_data->u.exidx.unwind_edit_list,
12656 &exidx_arm_data->u.exidx.unwind_edit_tail,
12657 INSERT_EXIDX_CANTUNWIND_AT_END, text_sec, UINT_MAX);
12658
491d01d3
YU		 12659 exidx_arm_data->additional_reloc_count++;
12660
2468f9c9
PB		 12661 adjust_exidx_size(exidx_sec, 8);
12662}
12663
12664/* Scan .ARM.exidx tables, and create a list describing edits which should be
12665 made to those tables, such that:
b38cadfb 12666
2468f9c9
PB		 12667 1. Regions without unwind data are marked with EXIDX_CANTUNWIND entries.
12668 2. Duplicate entries are merged together (EXIDX_CANTUNWIND, or unwind
99059e56 12669 codes which have been inlined into the index).
2468f9c9 12670
85fdf906
AH		 12671 If MERGE_EXIDX_ENTRIES is false, duplicate entries are not merged.
12672
2468f9c9 12673 The edits are applied when the tables are written
b38cadfb 12674 (in elf32_arm_write_section). */
2468f9c9
PB		 12675
12676bfd_boolean
12677elf32_arm_fix_exidx_coverage (asection **text_section_order,
12678 unsigned int num_text_sections,
85fdf906
AH		 12679 struct bfd_link_info *info,
12680 bfd_boolean merge_exidx_entries)
2468f9c9
PB		 12681{
12682 bfd *inp;
12683 unsigned int last_second_word = 0, i;
12684 asection *last_exidx_sec = NULL;
12685 asection *last_text_sec = NULL;
12686 int last_unwind_type = -1;
12687
12688 /* Walk over all EXIDX sections, and create backlinks from the corrsponding
12689 text sections. */
c72f2fb2 12690 for (inp = info->input_bfds; inp != NULL; inp = inp->link.next)
2468f9c9
PB		 12691 {
12692 asection *sec;
b38cadfb 12693
2468f9c9 12694 for (sec = inp->sections; sec != NULL; sec = sec->next)
99059e56 12695 {
2468f9c9
PB		 12696 struct bfd_elf_section_data *elf_sec = elf_section_data (sec);
12697 Elf_Internal_Shdr *hdr = &elf_sec->this_hdr;
b38cadfb 12698
dec9d5df 12699 if (!hdr || hdr->sh_type != SHT_ARM_EXIDX)
2468f9c9 12700 continue;
b38cadfb 12701
2468f9c9
PB		 12702 if (elf_sec->linked_to)
12703 {
12704 Elf_Internal_Shdr *linked_hdr
99059e56 12705 = &elf_section_data (elf_sec->linked_to)->this_hdr;
2468f9c9 12706 struct _arm_elf_section_data *linked_sec_arm_data
99059e56 12707 = get_arm_elf_section_data (linked_hdr->bfd_section);
2468f9c9
PB		 12708
12709 if (linked_sec_arm_data == NULL)
99059e56 12710 continue;
2468f9c9
PB		 12711
12712 /* Link this .ARM.exidx section back from the text section it
99059e56 12713 describes. */
2468f9c9
PB		 12714 linked_sec_arm_data->u.text.arm_exidx_sec = sec;
12715 }
12716 }
12717 }
12718
12719 /* Walk all text sections in order of increasing VMA. Eilminate duplicate
12720 index table entries (EXIDX_CANTUNWIND and inlined unwind opcodes),
91d6fa6a 12721 and add EXIDX_CANTUNWIND entries for sections with no unwind table data. */
2468f9c9
PB		 12722
12723 for (i = 0; i < num_text_sections; i++)
12724 {
12725 asection *sec = text_section_order[i];
12726 asection *exidx_sec;
12727 struct _arm_elf_section_data *arm_data = get_arm_elf_section_data (sec);
12728 struct _arm_elf_section_data *exidx_arm_data;
12729 bfd_byte *contents = NULL;
12730 int deleted_exidx_bytes = 0;
12731 bfd_vma j;
12732 arm_unwind_table_edit *unwind_edit_head = NULL;
12733 arm_unwind_table_edit *unwind_edit_tail = NULL;
12734 Elf_Internal_Shdr *hdr;
12735 bfd *ibfd;
12736
12737 if (arm_data == NULL)
99059e56 12738 continue;
2468f9c9
PB		 12739
12740 exidx_sec = arm_data->u.text.arm_exidx_sec;
12741 if (exidx_sec == NULL)
12742 {
12743 /* Section has no unwind data. */
12744 if (last_unwind_type == 0 || !last_exidx_sec)
12745 continue;
12746
12747 /* Ignore zero sized sections. */
12748 if (sec->size == 0)
12749 continue;
12750
12751 insert_cantunwind_after(last_text_sec, last_exidx_sec);
12752 last_unwind_type = 0;
12753 continue;
12754 }
12755
22a8f80e
PB		 12756 /* Skip /DISCARD/ sections. */
12757 if (bfd_is_abs_section (exidx_sec->output_section))
12758 continue;
12759
2468f9c9
PB		 12760 hdr = &elf_section_data (exidx_sec)->this_hdr;
12761 if (hdr->sh_type != SHT_ARM_EXIDX)
99059e56 12762 continue;
b38cadfb 12763
2468f9c9
PB		 12764 exidx_arm_data = get_arm_elf_section_data (exidx_sec);
12765 if (exidx_arm_data == NULL)
99059e56 12766 continue;
b38cadfb 12767
2468f9c9 12768 ibfd = exidx_sec->owner;
b38cadfb 12769
2468f9c9
PB		 12770 if (hdr->contents != NULL)
12771 contents = hdr->contents;
12772 else if (! bfd_malloc_and_get_section (ibfd, exidx_sec, &contents))
12773 /* An error? */
12774 continue;
12775
ac06903d
YU		 12776 if (last_unwind_type > 0)
12777 {
12778 unsigned int first_word = bfd_get_32 (ibfd, contents);
12779 /* Add cantunwind if first unwind item does not match section
12780 start. */
12781 if (first_word != sec->vma)
12782 {
12783 insert_cantunwind_after (last_text_sec, last_exidx_sec);
12784 last_unwind_type = 0;
12785 }
12786 }
12787
2468f9c9
PB		 12788 for (j = 0; j < hdr->sh_size; j += 8)
12789 {
12790 unsigned int second_word = bfd_get_32 (ibfd, contents + j + 4);
12791 int unwind_type;
12792 int elide = 0;
12793
12794 /* An EXIDX_CANTUNWIND entry. */
12795 if (second_word == 1)
12796 {
12797 if (last_unwind_type == 0)
12798 elide = 1;
12799 unwind_type = 0;
12800 }
12801 /* Inlined unwinding data. Merge if equal to previous. */
12802 else if ((second_word & 0x80000000) != 0)
12803 {
85fdf906
AH		 12804 if (merge_exidx_entries
12805 && last_second_word == second_word && last_unwind_type == 1)
2468f9c9
PB		 12806 elide = 1;
12807 unwind_type = 1;
12808 last_second_word = second_word;
12809 }
12810 /* Normal table entry. In theory we could merge these too,
12811 but duplicate entries are likely to be much less common. */
12812 else
12813 unwind_type = 2;
12814
491d01d3 12815 if (elide && !bfd_link_relocatable (info))
2468f9c9
PB		 12816 {
12817 add_unwind_table_edit (&unwind_edit_head, &unwind_edit_tail,
12818 DELETE_EXIDX_ENTRY, NULL, j / 8);
12819
12820 deleted_exidx_bytes += 8;
12821 }
12822
12823 last_unwind_type = unwind_type;
12824 }
12825
12826 /* Free contents if we allocated it ourselves. */
12827 if (contents != hdr->contents)
99059e56 12828 free (contents);
2468f9c9
PB		 12829
12830 /* Record edits to be applied later (in elf32_arm_write_section). */
12831 exidx_arm_data->u.exidx.unwind_edit_list = unwind_edit_head;
12832 exidx_arm_data->u.exidx.unwind_edit_tail = unwind_edit_tail;
b38cadfb 12833
2468f9c9
PB		 12834 if (deleted_exidx_bytes > 0)
12835 adjust_exidx_size(exidx_sec, -deleted_exidx_bytes);
12836
12837 last_exidx_sec = exidx_sec;
12838 last_text_sec = sec;
12839 }
12840
12841 /* Add terminating CANTUNWIND entry. */
491d01d3
YU		 12842 if (!bfd_link_relocatable (info) && last_exidx_sec
12843 && last_unwind_type != 0)
2468f9c9
PB		 12844 insert_cantunwind_after(last_text_sec, last_exidx_sec);
12845
12846 return TRUE;
12847}
12848
3e6b1042
DJ		 12849static bfd_boolean
12850elf32_arm_output_glue_section (struct bfd_link_info *info, bfd *obfd,
12851 bfd *ibfd, const char *name)
12852{
12853 asection *sec, *osec;
12854
3d4d4302 12855 sec = bfd_get_linker_section (ibfd, name);
3e6b1042
DJ		 12856 if (sec == NULL || (sec->flags & SEC_EXCLUDE) != 0)
12857 return TRUE;
12858
12859 osec = sec->output_section;
12860 if (elf32_arm_write_section (obfd, info, sec, sec->contents))
12861 return TRUE;
12862
12863 if (! bfd_set_section_contents (obfd, osec, sec->contents,
12864 sec->output_offset, sec->size))
12865 return FALSE;
12866
12867 return TRUE;
12868}
12869
12870static bfd_boolean
12871elf32_arm_final_link (bfd *abfd, struct bfd_link_info *info)
12872{
12873 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (info);
fe33d2fa 12874 asection *sec, *osec;
3e6b1042 12875
4dfe6ac6
NC		 12876 if (globals == NULL)
12877 return FALSE;
12878
3e6b1042
DJ		 12879 /* Invoke the regular ELF backend linker to do all the work. */
12880 if (!bfd_elf_final_link (abfd, info))
12881 return FALSE;
12882
fe33d2fa
CL		 12883 /* Process stub sections (eg BE8 encoding, ...). */
12884 struct elf32_arm_link_hash_table *htab = elf32_arm_hash_table (info);
7292b3ac 12885 unsigned int i;
cdb21a0a
NS		 12886 for (i=0; i<htab->top_id; i++)
12887 {
12888 sec = htab->stub_group[i].stub_sec;
12889 /* Only process it once, in its link_sec slot. */
12890 if (sec && i == htab->stub_group[i].link_sec->id)
12891 {
12892 osec = sec->output_section;
12893 elf32_arm_write_section (abfd, info, sec, sec->contents);
12894 if (! bfd_set_section_contents (abfd, osec, sec->contents,
12895 sec->output_offset, sec->size))
12896 return FALSE;
12897 }
fe33d2fa 12898 }
fe33d2fa 12899
3e6b1042
DJ		 12900 /* Write out any glue sections now that we have created all the
12901 stubs. */
12902 if (globals->bfd_of_glue_owner != NULL)
12903 {
12904 if (! elf32_arm_output_glue_section (info, abfd,
12905 globals->bfd_of_glue_owner,
12906 ARM2THUMB_GLUE_SECTION_NAME))
12907 return FALSE;
12908
12909 if (! elf32_arm_output_glue_section (info, abfd,
12910 globals->bfd_of_glue_owner,
12911 THUMB2ARM_GLUE_SECTION_NAME))
12912 return FALSE;
12913
12914 if (! elf32_arm_output_glue_section (info, abfd,
12915 globals->bfd_of_glue_owner,
12916 VFP11_ERRATUM_VENEER_SECTION_NAME))
12917 return FALSE;
12918
a504d23a
LA		 12919 if (! elf32_arm_output_glue_section (info, abfd,
12920 globals->bfd_of_glue_owner,
12921 STM32L4XX_ERRATUM_VENEER_SECTION_NAME))
12922 return FALSE;
12923
3e6b1042
DJ		 12924 if (! elf32_arm_output_glue_section (info, abfd,
12925 globals->bfd_of_glue_owner,
12926 ARM_BX_GLUE_SECTION_NAME))
12927 return FALSE;
12928 }
12929
12930 return TRUE;
12931}
12932
5968a7b8
NC		 12933/* Return a best guess for the machine number based on the attributes. */
12934
12935static unsigned int
12936bfd_arm_get_mach_from_attributes (bfd * abfd)
12937{
12938 int arch = bfd_elf_get_obj_attr_int (abfd, OBJ_ATTR_PROC, Tag_CPU_arch);
12939
12940 switch (arch)
12941 {
12942 case TAG_CPU_ARCH_V4: return bfd_mach_arm_4;
12943 case TAG_CPU_ARCH_V4T: return bfd_mach_arm_4T;
12944 case TAG_CPU_ARCH_V5T: return bfd_mach_arm_5T;
12945
12946 case TAG_CPU_ARCH_V5TE:
12947 {
12948 char * name;
12949
12950 BFD_ASSERT (Tag_CPU_name < NUM_KNOWN_OBJ_ATTRIBUTES);
12951 name = elf_known_obj_attributes (abfd) [OBJ_ATTR_PROC][Tag_CPU_name].s;
12952
12953 if (name)
12954 {
12955 if (strcmp (name, "IWMMXT2") == 0)
12956 return bfd_mach_arm_iWMMXt2;
12957
12958 if (strcmp (name, "IWMMXT") == 0)
6034aab8 12959 return bfd_mach_arm_iWMMXt;
088ca6c1
NC		 12960
12961 if (strcmp (name, "XSCALE") == 0)
12962 {
12963 int wmmx;
12964
12965 BFD_ASSERT (Tag_WMMX_arch < NUM_KNOWN_OBJ_ATTRIBUTES);
12966 wmmx = elf_known_obj_attributes (abfd) [OBJ_ATTR_PROC][Tag_WMMX_arch].i;
12967 switch (wmmx)
12968 {
12969 case 1: return bfd_mach_arm_iWMMXt;
12970 case 2: return bfd_mach_arm_iWMMXt2;
12971 default: return bfd_mach_arm_XScale;
12972 }
12973 }
5968a7b8
NC		 12974 }
12975
12976 return bfd_mach_arm_5TE;
12977 }
12978
12979 default:
12980 return bfd_mach_arm_unknown;
12981 }
12982}
12983
c178919b
NC		 12984/* Set the right machine number. */
12985
12986static bfd_boolean
57e8b36a 12987elf32_arm_object_p (bfd *abfd)
c178919b 12988{
5a6c6817 12989 unsigned int mach;
57e8b36a 12990
5a6c6817 12991 mach = bfd_arm_get_mach_from_notes (abfd, ARM_NOTE_SECTION);
c178919b 12992
5968a7b8
NC		 12993 if (mach == bfd_mach_arm_unknown)
12994 {
12995 if (elf_elfheader (abfd)->e_flags & EF_ARM_MAVERICK_FLOAT)
12996 mach = bfd_mach_arm_ep9312;
12997 else
12998 mach = bfd_arm_get_mach_from_attributes (abfd);
12999 }
c178919b 13000
5968a7b8 13001 bfd_default_set_arch_mach (abfd, bfd_arch_arm, mach);
c178919b
NC		 13002 return TRUE;
13003}
13004
fc830a83 13005/* Function to keep ARM specific flags in the ELF header. */
3c9458e9 13006
b34976b6 13007static bfd_boolean
57e8b36a 13008elf32_arm_set_private_flags (bfd *abfd, flagword flags)
252b5132
RH		 13009{
13010 if (elf_flags_init (abfd)
13011 && elf_elfheader (abfd)->e_flags != flags)
13012 {
fc830a83
NC		 13013 if (EF_ARM_EABI_VERSION (flags) == EF_ARM_EABI_UNKNOWN)
13014 {
fd2ec330 13015 if (flags & EF_ARM_INTERWORK)
4eca0228 13016 _bfd_error_handler
d003868e
AM		 13017 (_("Warning: Not setting interworking flag of %B since it has already been specified as non-interworking"),
13018 abfd);
fc830a83 13019 else
d003868e
AM		 13020 _bfd_error_handler
13021 (_("Warning: Clearing the interworking flag of %B due to outside request"),
13022 abfd);
fc830a83 13023 }
252b5132
RH		 13024 }
13025 else
13026 {
13027 elf_elfheader (abfd)->e_flags = flags;
b34976b6 13028 elf_flags_init (abfd) = TRUE;
252b5132
RH		 13029 }
13030
b34976b6 13031 return TRUE;
252b5132
RH		 13032}
13033
fc830a83 13034/* Copy backend specific data from one object module to another. */
9b485d32 13035
b34976b6 13036static bfd_boolean
57e8b36a 13037elf32_arm_copy_private_bfd_data (bfd *ibfd, bfd *obfd)
252b5132
RH		 13038{
13039 flagword in_flags;
13040 flagword out_flags;
13041
0ffa91dd 13042 if (! is_arm_elf (ibfd) || ! is_arm_elf (obfd))
b34976b6 13043 return TRUE;
252b5132 13044
fc830a83 13045 in_flags = elf_elfheader (ibfd)->e_flags;
252b5132
RH		 13046 out_flags = elf_elfheader (obfd)->e_flags;
13047
fc830a83
NC		 13048 if (elf_flags_init (obfd)
13049 && EF_ARM_EABI_VERSION (out_flags) == EF_ARM_EABI_UNKNOWN
13050 && in_flags != out_flags)
252b5132 13051 {
252b5132 13052 /* Cannot mix APCS26 and APCS32 code. */
fd2ec330 13053 if ((in_flags & EF_ARM_APCS_26) != (out_flags & EF_ARM_APCS_26))
b34976b6 13054 return FALSE;
252b5132
RH		 13055
13056 /* Cannot mix float APCS and non-float APCS code. */
fd2ec330 13057 if ((in_flags & EF_ARM_APCS_FLOAT) != (out_flags & EF_ARM_APCS_FLOAT))
b34976b6 13058 return FALSE;
252b5132
RH		 13059
13060 /* If the src and dest have different interworking flags
99059e56 13061 then turn off the interworking bit. */
fd2ec330 13062 if ((in_flags & EF_ARM_INTERWORK) != (out_flags & EF_ARM_INTERWORK))
252b5132 13063 {
fd2ec330 13064 if (out_flags & EF_ARM_INTERWORK)
d003868e
AM		 13065 _bfd_error_handler
13066 (_("Warning: Clearing the interworking flag of %B because non-interworking code in %B has been linked with it"),
13067 obfd, ibfd);
252b5132 13068
fd2ec330 13069 in_flags &= ~EF_ARM_INTERWORK;
252b5132 13070 }
1006ba19
PB		 13071
13072 /* Likewise for PIC, though don't warn for this case. */
fd2ec330
PB		 13073 if ((in_flags & EF_ARM_PIC) != (out_flags & EF_ARM_PIC))
13074 in_flags &= ~EF_ARM_PIC;
252b5132
RH		 13075 }
13076
13077 elf_elfheader (obfd)->e_flags = in_flags;
b34976b6 13078 elf_flags_init (obfd) = TRUE;
252b5132 13079
e2349352 13080 return _bfd_elf_copy_private_bfd_data (ibfd, obfd);
ee065d83
PB		 13081}
13082
13083/* Values for Tag_ABI_PCS_R9_use. */
13084enum
13085{
13086 AEABI_R9_V6,
13087 AEABI_R9_SB,
13088 AEABI_R9_TLS,
13089 AEABI_R9_unused
13090};
13091
13092/* Values for Tag_ABI_PCS_RW_data. */
13093enum
13094{
13095 AEABI_PCS_RW_data_absolute,
13096 AEABI_PCS_RW_data_PCrel,
13097 AEABI_PCS_RW_data_SBrel,
13098 AEABI_PCS_RW_data_unused
13099};
13100
13101/* Values for Tag_ABI_enum_size. */
13102enum
13103{
13104 AEABI_enum_unused,
13105 AEABI_enum_short,
13106 AEABI_enum_wide,
13107 AEABI_enum_forced_wide
13108};
13109
104d59d1
JM		 13110/* Determine whether an object attribute tag takes an integer, a
13111 string or both. */
906e58ca 13112
104d59d1
JM		 13113static int
13114elf32_arm_obj_attrs_arg_type (int tag)
13115{
13116 if (tag == Tag_compatibility)
3483fe2e 13117 return ATTR_TYPE_FLAG_INT_VAL | ATTR_TYPE_FLAG_STR_VAL;
2d0bb761 13118 else if (tag == Tag_nodefaults)
3483fe2e
AS		 13119 return ATTR_TYPE_FLAG_INT_VAL | ATTR_TYPE_FLAG_NO_DEFAULT;
13120 else if (tag == Tag_CPU_raw_name || tag == Tag_CPU_name)
13121 return ATTR_TYPE_FLAG_STR_VAL;
104d59d1 13122 else if (tag < 32)
3483fe2e 13123 return ATTR_TYPE_FLAG_INT_VAL;
104d59d1 13124 else
3483fe2e 13125 return (tag & 1) != 0 ? ATTR_TYPE_FLAG_STR_VAL : ATTR_TYPE_FLAG_INT_VAL;
104d59d1
JM		 13126}
13127
5aa6ff7c
AS		 13128/* The ABI defines that Tag_conformance should be emitted first, and that
13129 Tag_nodefaults should be second (if either is defined). This sets those
13130 two positions, and bumps up the position of all the remaining tags to
13131 compensate. */
13132static int
13133elf32_arm_obj_attrs_order (int num)
13134{
3de4a297 13135 if (num == LEAST_KNOWN_OBJ_ATTRIBUTE)
5aa6ff7c 13136 return Tag_conformance;
3de4a297 13137 if (num == LEAST_KNOWN_OBJ_ATTRIBUTE + 1)
5aa6ff7c
AS		 13138 return Tag_nodefaults;
13139 if ((num - 2) < Tag_nodefaults)
13140 return num - 2;
13141 if ((num - 1) < Tag_conformance)
13142 return num - 1;
13143 return num;
13144}
13145
e8b36cd1
JM		 13146/* Attribute numbers >=64 (mod 128) can be safely ignored. */
13147static bfd_boolean
13148elf32_arm_obj_attrs_handle_unknown (bfd *abfd, int tag)
13149{
13150 if ((tag & 127) < 64)
13151 {
13152 _bfd_error_handler
13153 (_("%B: Unknown mandatory EABI object attribute %d"),
13154 abfd, tag);
13155 bfd_set_error (bfd_error_bad_value);
13156 return FALSE;
13157 }
13158 else
13159 {
13160 _bfd_error_handler
13161 (_("Warning: %B: Unknown EABI object attribute %d"),
13162 abfd, tag);
13163 return TRUE;
13164 }
13165}
13166
91e22acd
AS		 13167/* Read the architecture from the Tag_also_compatible_with attribute, if any.
13168 Returns -1 if no architecture could be read. */
13169
13170static int
13171get_secondary_compatible_arch (bfd *abfd)
13172{
13173 obj_attribute *attr =
13174 &elf_known_obj_attributes_proc (abfd)[Tag_also_compatible_with];
13175
13176 /* Note: the tag and its argument below are uleb128 values, though
13177 currently-defined values fit in one byte for each. */
13178 if (attr->s
13179 && attr->s[0] == Tag_CPU_arch
13180 && (attr->s[1] & 128) != 128
13181 && attr->s[2] == 0)
13182 return attr->s[1];
13183
13184 /* This tag is "safely ignorable", so don't complain if it looks funny. */
13185 return -1;
13186}
13187
13188/* Set, or unset, the architecture of the Tag_also_compatible_with attribute.
13189 The tag is removed if ARCH is -1. */
13190
8e79c3df 13191static void
91e22acd 13192set_secondary_compatible_arch (bfd *abfd, int arch)
8e79c3df 13193{
91e22acd
AS		 13194 obj_attribute *attr =
13195 &elf_known_obj_attributes_proc (abfd)[Tag_also_compatible_with];
8e79c3df 13196
91e22acd
AS		 13197 if (arch == -1)
13198 {
13199 attr->s = NULL;
13200 return;
8e79c3df 13201 }
91e22acd
AS		 13202
13203 /* Note: the tag and its argument below are uleb128 values, though
13204 currently-defined values fit in one byte for each. */
13205 if (!attr->s)
21d799b5 13206 attr->s = (char *) bfd_alloc (abfd, 3);
91e22acd
AS		 13207 attr->s[0] = Tag_CPU_arch;
13208 attr->s[1] = arch;
13209 attr->s[2] = '\0';
8e79c3df
CM		 13210}
13211
91e22acd
AS		 13212/* Combine two values for Tag_CPU_arch, taking secondary compatibility tags
13213 into account. */
13214
13215static int
13216tag_cpu_arch_combine (bfd *ibfd, int oldtag, int *secondary_compat_out,
13217 int newtag, int secondary_compat)
8e79c3df 13218{
91e22acd
AS		 13219#define T(X) TAG_CPU_ARCH_##X
13220 int tagl, tagh, result;
13221 const int v6t2[] =
13222 {
13223 T(V6T2), /* PRE_V4. */
13224 T(V6T2), /* V4. */
13225 T(V6T2), /* V4T. */
13226 T(V6T2), /* V5T. */
13227 T(V6T2), /* V5TE. */
13228 T(V6T2), /* V5TEJ. */
13229 T(V6T2), /* V6. */
13230 T(V7), /* V6KZ. */
13231 T(V6T2) /* V6T2. */
13232 };
13233 const int v6k[] =
13234 {
13235 T(V6K), /* PRE_V4. */
13236 T(V6K), /* V4. */
13237 T(V6K), /* V4T. */
13238 T(V6K), /* V5T. */
13239 T(V6K), /* V5TE. */
13240 T(V6K), /* V5TEJ. */
13241 T(V6K), /* V6. */
13242 T(V6KZ), /* V6KZ. */
13243 T(V7), /* V6T2. */
13244 T(V6K) /* V6K. */
13245 };
13246 const int v7[] =
13247 {
13248 T(V7), /* PRE_V4. */
13249 T(V7), /* V4. */
13250 T(V7), /* V4T. */
13251 T(V7), /* V5T. */
13252 T(V7), /* V5TE. */
13253 T(V7), /* V5TEJ. */
13254 T(V7), /* V6. */
13255 T(V7), /* V6KZ. */
13256 T(V7), /* V6T2. */
13257 T(V7), /* V6K. */
13258 T(V7) /* V7. */
13259 };
13260 const int v6_m[] =
13261 {
13262 -1, /* PRE_V4. */
13263 -1, /* V4. */
13264 T(V6K), /* V4T. */
13265 T(V6K), /* V5T. */
13266 T(V6K), /* V5TE. */
13267 T(V6K), /* V5TEJ. */
13268 T(V6K), /* V6. */
13269 T(V6KZ), /* V6KZ. */
13270 T(V7), /* V6T2. */
13271 T(V6K), /* V6K. */
13272 T(V7), /* V7. */
13273 T(V6_M) /* V6_M. */
13274 };
13275 const int v6s_m[] =
13276 {
13277 -1, /* PRE_V4. */
13278 -1, /* V4. */
13279 T(V6K), /* V4T. */
13280 T(V6K), /* V5T. */
13281 T(V6K), /* V5TE. */
13282 T(V6K), /* V5TEJ. */
13283 T(V6K), /* V6. */
13284 T(V6KZ), /* V6KZ. */
13285 T(V7), /* V6T2. */
13286 T(V6K), /* V6K. */
13287 T(V7), /* V7. */
13288 T(V6S_M), /* V6_M. */
13289 T(V6S_M) /* V6S_M. */
13290 };
9e3c6df6
PB		 13291 const int v7e_m[] =
13292 {
13293 -1, /* PRE_V4. */
13294 -1, /* V4. */
13295 T(V7E_M), /* V4T. */
13296 T(V7E_M), /* V5T. */
13297 T(V7E_M), /* V5TE. */
13298 T(V7E_M), /* V5TEJ. */
13299 T(V7E_M), /* V6. */
13300 T(V7E_M), /* V6KZ. */
13301 T(V7E_M), /* V6T2. */
13302 T(V7E_M), /* V6K. */
13303 T(V7E_M), /* V7. */
13304 T(V7E_M), /* V6_M. */
13305 T(V7E_M), /* V6S_M. */
13306 T(V7E_M) /* V7E_M. */
13307 };
bca38921
MGD		 13308 const int v8[] =
13309 {
13310 T(V8), /* PRE_V4. */
13311 T(V8), /* V4. */
13312 T(V8), /* V4T. */
13313 T(V8), /* V5T. */
13314 T(V8), /* V5TE. */
13315 T(V8), /* V5TEJ. */
13316 T(V8), /* V6. */
13317 T(V8), /* V6KZ. */
13318 T(V8), /* V6T2. */
13319 T(V8), /* V6K. */
13320 T(V8), /* V7. */
13321 T(V8), /* V6_M. */
13322 T(V8), /* V6S_M. */
13323 T(V8), /* V7E_M. */
13324 T(V8) /* V8. */
13325 };
bff0500d
TP		 13326 const int v8r[] =
13327 {
13328 T(V8R), /* PRE_V4. */
13329 T(V8R), /* V4. */
13330 T(V8R), /* V4T. */
13331 T(V8R), /* V5T. */
13332 T(V8R), /* V5TE. */
13333 T(V8R), /* V5TEJ. */
13334 T(V8R), /* V6. */
13335 T(V8R), /* V6KZ. */
13336 T(V8R), /* V6T2. */
13337 T(V8R), /* V6K. */
13338 T(V8R), /* V7. */
13339 T(V8R), /* V6_M. */
13340 T(V8R), /* V6S_M. */
13341 T(V8R), /* V7E_M. */
13342 T(V8), /* V8. */
13343 T(V8R), /* V8R. */
13344 };
2fd158eb
TP		 13345 const int v8m_baseline[] =
13346 {
13347 -1, /* PRE_V4. */
13348 -1, /* V4. */
13349 -1, /* V4T. */
13350 -1, /* V5T. */
13351 -1, /* V5TE. */
13352 -1, /* V5TEJ. */
13353 -1, /* V6. */
13354 -1, /* V6KZ. */
13355 -1, /* V6T2. */
13356 -1, /* V6K. */
13357 -1, /* V7. */
13358 T(V8M_BASE), /* V6_M. */
13359 T(V8M_BASE), /* V6S_M. */
13360 -1, /* V7E_M. */
13361 -1, /* V8. */
bff0500d 13362 -1, /* V8R. */
2fd158eb
TP		 13363 T(V8M_BASE) /* V8-M BASELINE. */
13364 };
13365 const int v8m_mainline[] =
13366 {
13367 -1, /* PRE_V4. */
13368 -1, /* V4. */
13369 -1, /* V4T. */
13370 -1, /* V5T. */
13371 -1, /* V5TE. */
13372 -1, /* V5TEJ. */
13373 -1, /* V6. */
13374 -1, /* V6KZ. */
13375 -1, /* V6T2. */
13376 -1, /* V6K. */
13377 T(V8M_MAIN), /* V7. */
13378 T(V8M_MAIN), /* V6_M. */
13379 T(V8M_MAIN), /* V6S_M. */
13380 T(V8M_MAIN), /* V7E_M. */
13381 -1, /* V8. */
bff0500d 13382 -1, /* V8R. */
2fd158eb
TP		 13383 T(V8M_MAIN), /* V8-M BASELINE. */
13384 T(V8M_MAIN) /* V8-M MAINLINE. */
13385 };
91e22acd
AS		 13386 const int v4t_plus_v6_m[] =
13387 {
13388 -1, /* PRE_V4. */
13389 -1, /* V4. */
13390 T(V4T), /* V4T. */
13391 T(V5T), /* V5T. */
13392 T(V5TE), /* V5TE. */
13393 T(V5TEJ), /* V5TEJ. */
13394 T(V6), /* V6. */
13395 T(V6KZ), /* V6KZ. */
13396 T(V6T2), /* V6T2. */
13397 T(V6K), /* V6K. */
13398 T(V7), /* V7. */
13399 T(V6_M), /* V6_M. */
13400 T(V6S_M), /* V6S_M. */
9e3c6df6 13401 T(V7E_M), /* V7E_M. */
bca38921 13402 T(V8), /* V8. */
bff0500d 13403 -1, /* V8R. */
2fd158eb
TP		 13404 T(V8M_BASE), /* V8-M BASELINE. */
13405 T(V8M_MAIN), /* V8-M MAINLINE. */
91e22acd
AS		 13406 T(V4T_PLUS_V6_M) /* V4T plus V6_M. */
13407 };
13408 const int *comb[] =
13409 {
13410 v6t2,
13411 v6k,
13412 v7,
13413 v6_m,
13414 v6s_m,
9e3c6df6 13415 v7e_m,
bca38921 13416 v8,
bff0500d 13417 v8r,
2fd158eb
TP		 13418 v8m_baseline,
13419 v8m_mainline,
91e22acd
AS		 13420 /* Pseudo-architecture. */
13421 v4t_plus_v6_m
13422 };
13423
13424 /* Check we've not got a higher architecture than we know about. */
13425
9e3c6df6 13426 if (oldtag > MAX_TAG_CPU_ARCH || newtag > MAX_TAG_CPU_ARCH)
91e22acd 13427 {
3895f852 13428 _bfd_error_handler (_("error: %B: Unknown CPU architecture"), ibfd);
91e22acd
AS		 13429 return -1;
13430 }
13431
13432 /* Override old tag if we have a Tag_also_compatible_with on the output. */
13433
13434 if ((oldtag == T(V6_M) && *secondary_compat_out == T(V4T))
13435 || (oldtag == T(V4T) && *secondary_compat_out == T(V6_M)))
13436 oldtag = T(V4T_PLUS_V6_M);
13437
13438 /* And override the new tag if we have a Tag_also_compatible_with on the
13439 input. */
13440
13441 if ((newtag == T(V6_M) && secondary_compat == T(V4T))
13442 || (newtag == T(V4T) && secondary_compat == T(V6_M)))
13443 newtag = T(V4T_PLUS_V6_M);
13444
13445 tagl = (oldtag < newtag) ? oldtag : newtag;
13446 result = tagh = (oldtag > newtag) ? oldtag : newtag;
13447
13448 /* Architectures before V6KZ add features monotonically. */
13449 if (tagh <= TAG_CPU_ARCH_V6KZ)
13450 return result;
13451
4ed7ed8d 13452 result = comb[tagh - T(V6T2)] ? comb[tagh - T(V6T2)][tagl] : -1;
91e22acd
AS		 13453
13454 /* Use Tag_CPU_arch == V4T and Tag_also_compatible_with (Tag_CPU_arch V6_M)
13455 as the canonical version. */
13456 if (result == T(V4T_PLUS_V6_M))
13457 {
13458 result = T(V4T);
13459 *secondary_compat_out = T(V6_M);
13460 }
13461 else
13462 *secondary_compat_out = -1;
13463
13464 if (result == -1)
13465 {
3895f852 13466 _bfd_error_handler (_("error: %B: Conflicting CPU architectures %d/%d"),
91e22acd
AS		 13467 ibfd, oldtag, newtag);
13468 return -1;
13469 }
13470
13471 return result;
13472#undef T
8e79c3df
CM		 13473}
13474
ac56ee8f
MGD		 13475/* Query attributes object to see if integer divide instructions may be
13476 present in an object. */
13477static bfd_boolean
13478elf32_arm_attributes_accept_div (const obj_attribute *attr)
13479{
13480 int arch = attr[Tag_CPU_arch].i;
13481 int profile = attr[Tag_CPU_arch_profile].i;
13482
13483 switch (attr[Tag_DIV_use].i)
13484 {
13485 case 0:
13486 /* Integer divide allowed if instruction contained in archetecture. */
13487 if (arch == TAG_CPU_ARCH_V7 && (profile == 'R' || profile == 'M'))
13488 return TRUE;
13489 else if (arch >= TAG_CPU_ARCH_V7E_M)
13490 return TRUE;
13491 else
13492 return FALSE;
13493
13494 case 1:
13495 /* Integer divide explicitly prohibited. */
13496 return FALSE;
13497
13498 default:
13499 /* Unrecognised case - treat as allowing divide everywhere. */
13500 case 2:
13501 /* Integer divide allowed in ARM state. */
13502 return TRUE;
13503 }
13504}
13505
13506/* Query attributes object to see if integer divide instructions are
13507 forbidden to be in the object. This is not the inverse of
13508 elf32_arm_attributes_accept_div. */
13509static bfd_boolean
13510elf32_arm_attributes_forbid_div (const obj_attribute *attr)
13511{
13512 return attr[Tag_DIV_use].i == 1;
13513}
13514
ee065d83
PB		 13515/* Merge EABI object attributes from IBFD into OBFD. Raise an error if there
13516 are conflicting attributes. */
906e58ca 13517
ee065d83 13518static bfd_boolean
50e03d47 13519elf32_arm_merge_eabi_attributes (bfd *ibfd, struct bfd_link_info *info)
ee065d83 13520{
50e03d47 13521 bfd *obfd = info->output_bfd;
104d59d1
JM		 13522 obj_attribute *in_attr;
13523 obj_attribute *out_attr;
ee065d83
PB		 13524 /* Some tags have 0 = don't care, 1 = strong requirement,
13525 2 = weak requirement. */
91e22acd 13526 static const int order_021[3] = {0, 2, 1};
ee065d83 13527 int i;
91e22acd 13528 bfd_boolean result = TRUE;
9274e9de 13529 const char *sec_name = get_elf_backend_data (ibfd)->obj_attrs_section;
ee065d83 13530
3e6b1042
DJ		 13531 /* Skip the linker stubs file. This preserves previous behavior
13532 of accepting unknown attributes in the first input file - but
13533 is that a bug? */
13534 if (ibfd->flags & BFD_LINKER_CREATED)
13535 return TRUE;
13536
9274e9de
TG		 13537 /* Skip any input that hasn't attribute section.
13538 This enables to link object files without attribute section with
13539 any others. */
13540 if (bfd_get_section_by_name (ibfd, sec_name) == NULL)
13541 return TRUE;
13542
104d59d1 13543 if (!elf_known_obj_attributes_proc (obfd)[0].i)
ee065d83
PB		 13544 {
13545 /* This is the first object. Copy the attributes. */
104d59d1 13546 _bfd_elf_copy_obj_attributes (ibfd, obfd);
004ae526 13547
cd21e546
MGD		 13548 out_attr = elf_known_obj_attributes_proc (obfd);
13549
004ae526
PB		 13550 /* Use the Tag_null value to indicate the attributes have been
13551 initialized. */
cd21e546 13552 out_attr[0].i = 1;
004ae526 13553
cd21e546
MGD		 13554 /* We do not output objects with Tag_MPextension_use_legacy - we move
13555 the attribute's value to Tag_MPextension_use. */
13556 if (out_attr[Tag_MPextension_use_legacy].i != 0)
13557 {
13558 if (out_attr[Tag_MPextension_use].i != 0
13559 && out_attr[Tag_MPextension_use_legacy].i
99059e56 13560 != out_attr[Tag_MPextension_use].i)
cd21e546
MGD		 13561 {
13562 _bfd_error_handler
13563 (_("Error: %B has both the current and legacy "
13564 "Tag_MPextension_use attributes"), ibfd);
13565 result = FALSE;
13566 }
13567
13568 out_attr[Tag_MPextension_use] =
13569 out_attr[Tag_MPextension_use_legacy];
13570 out_attr[Tag_MPextension_use_legacy].type = 0;
13571 out_attr[Tag_MPextension_use_legacy].i = 0;
13572 }
13573
13574 return result;
ee065d83
PB		 13575 }
13576
104d59d1
JM		 13577 in_attr = elf_known_obj_attributes_proc (ibfd);
13578 out_attr = elf_known_obj_attributes_proc (obfd);
ee065d83
PB		 13579 /* This needs to happen before Tag_ABI_FP_number_model is merged. */
13580 if (in_attr[Tag_ABI_VFP_args].i != out_attr[Tag_ABI_VFP_args].i)
13581 {
5c294fee
TG		 13582 /* Ignore mismatches if the object doesn't use floating point or is
13583 floating point ABI independent. */
13584 if (out_attr[Tag_ABI_FP_number_model].i == AEABI_FP_number_model_none
13585 || (in_attr[Tag_ABI_FP_number_model].i != AEABI_FP_number_model_none
13586 && out_attr[Tag_ABI_VFP_args].i == AEABI_VFP_args_compatible))
ee065d83 13587 out_attr[Tag_ABI_VFP_args].i = in_attr[Tag_ABI_VFP_args].i;
5c294fee
TG		 13588 else if (in_attr[Tag_ABI_FP_number_model].i != AEABI_FP_number_model_none
13589 && in_attr[Tag_ABI_VFP_args].i != AEABI_VFP_args_compatible)
ee065d83
PB		 13590 {
13591 _bfd_error_handler
3895f852 13592 (_("error: %B uses VFP register arguments, %B does not"),
deddc40b
NS		 13593 in_attr[Tag_ABI_VFP_args].i ? ibfd : obfd,
13594 in_attr[Tag_ABI_VFP_args].i ? obfd : ibfd);
91e22acd 13595 result = FALSE;
ee065d83
PB		 13596 }
13597 }
13598
3de4a297 13599 for (i = LEAST_KNOWN_OBJ_ATTRIBUTE; i < NUM_KNOWN_OBJ_ATTRIBUTES; i++)
ee065d83
PB		 13600 {
13601 /* Merge this attribute with existing attributes. */
13602 switch (i)
13603 {
13604 case Tag_CPU_raw_name:
13605 case Tag_CPU_name:
6a631e86 13606 /* These are merged after Tag_CPU_arch. */
ee065d83
PB		 13607 break;
13608
13609 case Tag_ABI_optimization_goals:
13610 case Tag_ABI_FP_optimization_goals:
13611 /* Use the first value seen. */
13612 break;
13613
13614 case Tag_CPU_arch:
91e22acd
AS		 13615 {
13616 int secondary_compat = -1, secondary_compat_out = -1;
13617 unsigned int saved_out_attr = out_attr[i].i;
70e99720
TG		 13618 int arch_attr;
13619 static const char *name_table[] =
13620 {
91e22acd
AS		 13621 /* These aren't real CPU names, but we can't guess
13622 that from the architecture version alone. */
13623 "Pre v4",
13624 "ARM v4",
13625 "ARM v4T",
13626 "ARM v5T",
13627 "ARM v5TE",
13628 "ARM v5TEJ",
13629 "ARM v6",
13630 "ARM v6KZ",
13631 "ARM v6T2",
13632 "ARM v6K",
13633 "ARM v7",
13634 "ARM v6-M",
bca38921 13635 "ARM v6S-M",
2fd158eb
TP		 13636 "ARM v8",
13637 "",
13638 "ARM v8-M.baseline",
13639 "ARM v8-M.mainline",
91e22acd
AS		 13640 };
13641
13642 /* Merge Tag_CPU_arch and Tag_also_compatible_with. */
13643 secondary_compat = get_secondary_compatible_arch (ibfd);
13644 secondary_compat_out = get_secondary_compatible_arch (obfd);
70e99720
TG		 13645 arch_attr = tag_cpu_arch_combine (ibfd, out_attr[i].i,
13646 &secondary_compat_out,
13647 in_attr[i].i,
13648 secondary_compat);
13649
13650 /* Return with error if failed to merge. */
13651 if (arch_attr == -1)
13652 return FALSE;
13653
13654 out_attr[i].i = arch_attr;
13655
91e22acd
AS		 13656 set_secondary_compatible_arch (obfd, secondary_compat_out);
13657
13658 /* Merge Tag_CPU_name and Tag_CPU_raw_name. */
13659 if (out_attr[i].i == saved_out_attr)
13660 ; /* Leave the names alone. */
13661 else if (out_attr[i].i == in_attr[i].i)
13662 {
13663 /* The output architecture has been changed to match the
13664 input architecture. Use the input names. */
13665 out_attr[Tag_CPU_name].s = in_attr[Tag_CPU_name].s
13666 ? _bfd_elf_attr_strdup (obfd, in_attr[Tag_CPU_name].s)
13667 : NULL;
13668 out_attr[Tag_CPU_raw_name].s = in_attr[Tag_CPU_raw_name].s
13669 ? _bfd_elf_attr_strdup (obfd, in_attr[Tag_CPU_raw_name].s)
13670 : NULL;
13671 }
13672 else
13673 {
13674 out_attr[Tag_CPU_name].s = NULL;
13675 out_attr[Tag_CPU_raw_name].s = NULL;
13676 }
13677
13678 /* If we still don't have a value for Tag_CPU_name,
13679 make one up now. Tag_CPU_raw_name remains blank. */
13680 if (out_attr[Tag_CPU_name].s == NULL
13681 && out_attr[i].i < ARRAY_SIZE (name_table))
13682 out_attr[Tag_CPU_name].s =
13683 _bfd_elf_attr_strdup (obfd, name_table[out_attr[i].i]);
13684 }
13685 break;
13686
ee065d83
PB		 13687 case Tag_ARM_ISA_use:
13688 case Tag_THUMB_ISA_use:
ee065d83 13689 case Tag_WMMX_arch:
91e22acd
AS		 13690 case Tag_Advanced_SIMD_arch:
13691 /* ??? Do Advanced_SIMD (NEON) and WMMX conflict? */
ee065d83 13692 case Tag_ABI_FP_rounding:
ee065d83
PB		 13693 case Tag_ABI_FP_exceptions:
13694 case Tag_ABI_FP_user_exceptions:
13695 case Tag_ABI_FP_number_model:
75375b3e 13696 case Tag_FP_HP_extension:
91e22acd
AS		 13697 case Tag_CPU_unaligned_access:
13698 case Tag_T2EE_use:
91e22acd 13699 case Tag_MPextension_use:
ee065d83
PB		 13700 /* Use the largest value specified. */
13701 if (in_attr[i].i > out_attr[i].i)
13702 out_attr[i].i = in_attr[i].i;
13703 break;
13704
75375b3e 13705 case Tag_ABI_align_preserved:
91e22acd
AS		 13706 case Tag_ABI_PCS_RO_data:
13707 /* Use the smallest value specified. */
13708 if (in_attr[i].i < out_attr[i].i)
13709 out_attr[i].i = in_attr[i].i;
13710 break;
13711
75375b3e 13712 case Tag_ABI_align_needed:
91e22acd 13713 if ((in_attr[i].i > 0 || out_attr[i].i > 0)
75375b3e
MGD		 13714 && (in_attr[Tag_ABI_align_preserved].i == 0
13715 || out_attr[Tag_ABI_align_preserved].i == 0))
ee065d83 13716 {
91e22acd
AS		 13717 /* This error message should be enabled once all non-conformant
13718 binaries in the toolchain have had the attributes set
13719 properly.
ee065d83 13720 _bfd_error_handler
3895f852 13721 (_("error: %B: 8-byte data alignment conflicts with %B"),
91e22acd
AS		 13722 obfd, ibfd);
13723 result = FALSE; */
ee065d83 13724 }
91e22acd
AS		 13725 /* Fall through. */
13726 case Tag_ABI_FP_denormal:
13727 case Tag_ABI_PCS_GOT_use:
13728 /* Use the "greatest" from the sequence 0, 2, 1, or the largest
13729 value if greater than 2 (for future-proofing). */
13730 if ((in_attr[i].i > 2 && in_attr[i].i > out_attr[i].i)
13731 || (in_attr[i].i <= 2 && out_attr[i].i <= 2
13732 && order_021[in_attr[i].i] > order_021[out_attr[i].i]))
ee065d83
PB		 13733 out_attr[i].i = in_attr[i].i;
13734 break;
91e22acd 13735
75375b3e
MGD		 13736 case Tag_Virtualization_use:
13737 /* The virtualization tag effectively stores two bits of
13738 information: the intended use of TrustZone (in bit 0), and the
13739 intended use of Virtualization (in bit 1). */
13740 if (out_attr[i].i == 0)
13741 out_attr[i].i = in_attr[i].i;
13742 else if (in_attr[i].i != 0
13743 && in_attr[i].i != out_attr[i].i)
13744 {
13745 if (in_attr[i].i <= 3 && out_attr[i].i <= 3)
13746 out_attr[i].i = 3;
13747 else
13748 {
13749 _bfd_error_handler
13750 (_("error: %B: unable to merge virtualization attributes "
13751 "with %B"),
13752 obfd, ibfd);
13753 result = FALSE;
13754 }
13755 }
13756 break;
91e22acd
AS		 13757
13758 case Tag_CPU_arch_profile:
13759 if (out_attr[i].i != in_attr[i].i)
13760 {
13761 /* 0 will merge with anything.
13762 'A' and 'S' merge to 'A'.
13763 'R' and 'S' merge to 'R'.
99059e56 13764 'M' and 'A|R|S' is an error. */
91e22acd
AS		 13765 if (out_attr[i].i == 0
13766 || (out_attr[i].i == 'S'
13767 && (in_attr[i].i == 'A' || in_attr[i].i == 'R')))
13768 out_attr[i].i = in_attr[i].i;
13769 else if (in_attr[i].i == 0
13770 || (in_attr[i].i == 'S'
13771 && (out_attr[i].i == 'A' || out_attr[i].i == 'R')))
6a631e86 13772 ; /* Do nothing. */
91e22acd
AS		 13773 else
13774 {
13775 _bfd_error_handler
3895f852 13776 (_("error: %B: Conflicting architecture profiles %c/%c"),
91e22acd
AS		 13777 ibfd,
13778 in_attr[i].i ? in_attr[i].i : '0',
13779 out_attr[i].i ? out_attr[i].i : '0');
13780 result = FALSE;
13781 }
13782 }
13783 break;
15afaa63
TP		 13784
13785 case Tag_DSP_extension:
13786 /* No need to change output value if any of:
13787 - pre (<=) ARMv5T input architecture (do not have DSP)
13788 - M input profile not ARMv7E-M and do not have DSP. */
13789 if (in_attr[Tag_CPU_arch].i <= 3
13790 || (in_attr[Tag_CPU_arch_profile].i == 'M'
13791 && in_attr[Tag_CPU_arch].i != 13
13792 && in_attr[i].i == 0))
13793 ; /* Do nothing. */
13794 /* Output value should be 0 if DSP part of architecture, ie.
13795 - post (>=) ARMv5te architecture output
13796 - A, R or S profile output or ARMv7E-M output architecture. */
13797 else if (out_attr[Tag_CPU_arch].i >= 4
13798 && (out_attr[Tag_CPU_arch_profile].i == 'A'
13799 || out_attr[Tag_CPU_arch_profile].i == 'R'
13800 || out_attr[Tag_CPU_arch_profile].i == 'S'
13801 || out_attr[Tag_CPU_arch].i == 13))
13802 out_attr[i].i = 0;
13803 /* Otherwise, DSP instructions are added and not part of output
13804 architecture. */
13805 else
13806 out_attr[i].i = 1;
13807 break;
13808
75375b3e 13809 case Tag_FP_arch:
62f3b8c8 13810 {
4547cb56
NC		 13811 /* Tag_ABI_HardFP_use is handled along with Tag_FP_arch since
13812 the meaning of Tag_ABI_HardFP_use depends on Tag_FP_arch
13813 when it's 0. It might mean absence of FP hardware if
99654aaf 13814 Tag_FP_arch is zero. */
4547cb56 13815
a715796b 13816#define VFP_VERSION_COUNT 9
62f3b8c8
PB		 13817 static const struct
13818 {
13819 int ver;
13820 int regs;
bca38921 13821 } vfp_versions[VFP_VERSION_COUNT] =
62f3b8c8
PB		 13822 {
13823 {0, 0},
13824 {1, 16},
13825 {2, 16},
13826 {3, 32},
13827 {3, 16},
13828 {4, 32},
bca38921 13829 {4, 16},
a715796b
TG		 13830 {8, 32},
13831 {8, 16}
62f3b8c8
PB		 13832 };
13833 int ver;
13834 int regs;
13835 int newval;
13836
4547cb56
NC		 13837 /* If the output has no requirement about FP hardware,
13838 follow the requirement of the input. */
13839 if (out_attr[i].i == 0)
13840 {
4ec192e6
RE		 13841 /* This assert is still reasonable, we shouldn't
13842 produce the suspicious build attribute
13843 combination (See below for in_attr). */
4547cb56
NC		 13844 BFD_ASSERT (out_attr[Tag_ABI_HardFP_use].i == 0);
13845 out_attr[i].i = in_attr[i].i;
13846 out_attr[Tag_ABI_HardFP_use].i
13847 = in_attr[Tag_ABI_HardFP_use].i;
13848 break;
13849 }
13850 /* If the input has no requirement about FP hardware, do
13851 nothing. */
13852 else if (in_attr[i].i == 0)
13853 {
4ec192e6
RE		 13854 /* We used to assert that Tag_ABI_HardFP_use was
13855 zero here, but we should never assert when
13856 consuming an object file that has suspicious
13857 build attributes. The single precision variant
13858 of 'no FP architecture' is still 'no FP
13859 architecture', so we just ignore the tag in this
13860 case. */
4547cb56
NC		 13861 break;
13862 }
13863
13864 /* Both the input and the output have nonzero Tag_FP_arch.
99654aaf 13865 So Tag_ABI_HardFP_use is implied by Tag_FP_arch when it's zero. */
4547cb56
NC		 13866
13867 /* If both the input and the output have zero Tag_ABI_HardFP_use,
13868 do nothing. */
13869 if (in_attr[Tag_ABI_HardFP_use].i == 0
13870 && out_attr[Tag_ABI_HardFP_use].i == 0)
13871 ;
13872 /* If the input and the output have different Tag_ABI_HardFP_use,
99654aaf 13873 the combination of them is 0 (implied by Tag_FP_arch). */
4547cb56
NC		 13874 else if (in_attr[Tag_ABI_HardFP_use].i
13875 != out_attr[Tag_ABI_HardFP_use].i)
99654aaf 13876 out_attr[Tag_ABI_HardFP_use].i = 0;
4547cb56
NC		 13877
13878 /* Now we can handle Tag_FP_arch. */
13879
bca38921
MGD		 13880 /* Values of VFP_VERSION_COUNT or more aren't defined, so just
13881 pick the biggest. */
13882 if (in_attr[i].i >= VFP_VERSION_COUNT
13883 && in_attr[i].i > out_attr[i].i)
62f3b8c8
PB		 13884 {
13885 out_attr[i] = in_attr[i];
13886 break;
13887 }
13888 /* The output uses the superset of input features
13889 (ISA version) and registers. */
13890 ver = vfp_versions[in_attr[i].i].ver;
13891 if (ver < vfp_versions[out_attr[i].i].ver)
13892 ver = vfp_versions[out_attr[i].i].ver;
13893 regs = vfp_versions[in_attr[i].i].regs;
13894 if (regs < vfp_versions[out_attr[i].i].regs)
13895 regs = vfp_versions[out_attr[i].i].regs;
13896 /* This assumes all possible supersets are also a valid
99059e56 13897 options. */
bca38921 13898 for (newval = VFP_VERSION_COUNT - 1; newval > 0; newval--)
62f3b8c8
PB		 13899 {
13900 if (regs == vfp_versions[newval].regs
13901 && ver == vfp_versions[newval].ver)
13902 break;
13903 }
13904 out_attr[i].i = newval;
13905 }
b1cc4aeb 13906 break;
ee065d83
PB		 13907 case Tag_PCS_config:
13908 if (out_attr[i].i == 0)
13909 out_attr[i].i = in_attr[i].i;
b6009aca 13910 else if (in_attr[i].i != 0 && out_attr[i].i != in_attr[i].i)
ee065d83
PB		 13911 {
13912 /* It's sometimes ok to mix different configs, so this is only
99059e56 13913 a warning. */
ee065d83
PB		 13914 _bfd_error_handler
13915 (_("Warning: %B: Conflicting platform configuration"), ibfd);
13916 }
13917 break;
13918 case Tag_ABI_PCS_R9_use:
004ae526
PB		 13919 if (in_attr[i].i != out_attr[i].i
13920 && out_attr[i].i != AEABI_R9_unused
ee065d83
PB		 13921 && in_attr[i].i != AEABI_R9_unused)
13922 {
13923 _bfd_error_handler
3895f852 13924 (_("error: %B: Conflicting use of R9"), ibfd);
91e22acd 13925 result = FALSE;
ee065d83
PB		 13926 }
13927 if (out_attr[i].i == AEABI_R9_unused)
13928 out_attr[i].i = in_attr[i].i;
13929 break;
13930 case Tag_ABI_PCS_RW_data:
13931 if (in_attr[i].i == AEABI_PCS_RW_data_SBrel
13932 && out_attr[Tag_ABI_PCS_R9_use].i != AEABI_R9_SB
13933 && out_attr[Tag_ABI_PCS_R9_use].i != AEABI_R9_unused)
13934 {
13935 _bfd_error_handler
3895f852 13936 (_("error: %B: SB relative addressing conflicts with use of R9"),
ee065d83 13937 ibfd);
91e22acd 13938 result = FALSE;
ee065d83
PB		 13939 }
13940 /* Use the smallest value specified. */
13941 if (in_attr[i].i < out_attr[i].i)
13942 out_attr[i].i = in_attr[i].i;
13943 break;
ee065d83 13944 case Tag_ABI_PCS_wchar_t:
a9dc9481
JM		 13945 if (out_attr[i].i && in_attr[i].i && out_attr[i].i != in_attr[i].i
13946 && !elf_arm_tdata (obfd)->no_wchar_size_warning)
ee065d83
PB		 13947 {
13948 _bfd_error_handler
a9dc9481
JM		 13949 (_("warning: %B uses %u-byte wchar_t yet the output is to use %u-byte wchar_t; use of wchar_t values across objects may fail"),
13950 ibfd, in_attr[i].i, out_attr[i].i);
ee065d83 13951 }
a9dc9481 13952 else if (in_attr[i].i && !out_attr[i].i)
ee065d83
PB		 13953 out_attr[i].i = in_attr[i].i;
13954 break;
ee065d83
PB		 13955 case Tag_ABI_enum_size:
13956 if (in_attr[i].i != AEABI_enum_unused)
13957 {
13958 if (out_attr[i].i == AEABI_enum_unused
13959 || out_attr[i].i == AEABI_enum_forced_wide)
13960 {
13961 /* The existing object is compatible with anything.
13962 Use whatever requirements the new object has. */
13963 out_attr[i].i = in_attr[i].i;
13964 }
13965 else if (in_attr[i].i != AEABI_enum_forced_wide
bf21ed78 13966 && out_attr[i].i != in_attr[i].i
0ffa91dd 13967 && !elf_arm_tdata (obfd)->no_enum_size_warning)
ee065d83 13968 {
91e22acd 13969 static const char *aeabi_enum_names[] =
bf21ed78 13970 { "", "variable-size", "32-bit", "" };
91e22acd
AS		 13971 const char *in_name =
13972 in_attr[i].i < ARRAY_SIZE(aeabi_enum_names)
13973 ? aeabi_enum_names[in_attr[i].i]
13974 : "<unknown>";
13975 const char *out_name =
13976 out_attr[i].i < ARRAY_SIZE(aeabi_enum_names)
13977 ? aeabi_enum_names[out_attr[i].i]
13978 : "<unknown>";
ee065d83 13979 _bfd_error_handler
bf21ed78 13980 (_("warning: %B uses %s enums yet the output is to use %s enums; use of enum values across objects may fail"),
91e22acd 13981 ibfd, in_name, out_name);
ee065d83
PB		 13982 }
13983 }
13984 break;
13985 case Tag_ABI_VFP_args:
13986 /* Aready done. */
13987 break;
13988 case Tag_ABI_WMMX_args:
13989 if (in_attr[i].i != out_attr[i].i)
13990 {
13991 _bfd_error_handler
3895f852 13992 (_("error: %B uses iWMMXt register arguments, %B does not"),
ee065d83 13993 ibfd, obfd);
91e22acd 13994 result = FALSE;
ee065d83
PB		 13995 }
13996 break;
7b86a9fa
AS		 13997 case Tag_compatibility:
13998 /* Merged in target-independent code. */
13999 break;
91e22acd 14000 case Tag_ABI_HardFP_use:
4547cb56 14001 /* This is handled along with Tag_FP_arch. */
91e22acd
AS		 14002 break;
14003 case Tag_ABI_FP_16bit_format:
14004 if (in_attr[i].i != 0 && out_attr[i].i != 0)
14005 {
14006 if (in_attr[i].i != out_attr[i].i)
14007 {
14008 _bfd_error_handler
3895f852 14009 (_("error: fp16 format mismatch between %B and %B"),
91e22acd
AS		 14010 ibfd, obfd);
14011 result = FALSE;
14012 }
14013 }
14014 if (in_attr[i].i != 0)
14015 out_attr[i].i = in_attr[i].i;
14016 break;
7b86a9fa 14017
cd21e546 14018 case Tag_DIV_use:
ac56ee8f
MGD		 14019 /* A value of zero on input means that the divide instruction may
14020 be used if available in the base architecture as specified via
14021 Tag_CPU_arch and Tag_CPU_arch_profile. A value of 1 means that
14022 the user did not want divide instructions. A value of 2
14023 explicitly means that divide instructions were allowed in ARM
14024 and Thumb state. */
14025 if (in_attr[i].i == out_attr[i].i)
14026 /* Do nothing. */ ;
14027 else if (elf32_arm_attributes_forbid_div (in_attr)
14028 && !elf32_arm_attributes_accept_div (out_attr))
14029 out_attr[i].i = 1;
14030 else if (elf32_arm_attributes_forbid_div (out_attr)
14031 && elf32_arm_attributes_accept_div (in_attr))
14032 out_attr[i].i = in_attr[i].i;
14033 else if (in_attr[i].i == 2)
14034 out_attr[i].i = in_attr[i].i;
cd21e546
MGD		 14035 break;
14036
14037 case Tag_MPextension_use_legacy:
14038 /* We don't output objects with Tag_MPextension_use_legacy - we
14039 move the value to Tag_MPextension_use. */
14040 if (in_attr[i].i != 0 && in_attr[Tag_MPextension_use].i != 0)
14041 {
14042 if (in_attr[Tag_MPextension_use].i != in_attr[i].i)
14043 {
14044 _bfd_error_handler
14045 (_("%B has has both the current and legacy "
b38cadfb 14046 "Tag_MPextension_use attributes"),
cd21e546
MGD		 14047 ibfd);
14048 result = FALSE;
14049 }
14050 }
14051
14052 if (in_attr[i].i > out_attr[Tag_MPextension_use].i)
14053 out_attr[Tag_MPextension_use] = in_attr[i];
14054
14055 break;
14056
91e22acd 14057 case Tag_nodefaults:
2d0bb761
AS		 14058 /* This tag is set if it exists, but the value is unused (and is
14059 typically zero). We don't actually need to do anything here -
14060 the merge happens automatically when the type flags are merged
14061 below. */
91e22acd
AS		 14062 break;
14063 case Tag_also_compatible_with:
14064 /* Already done in Tag_CPU_arch. */
14065 break;
14066 case Tag_conformance:
14067 /* Keep the attribute if it matches. Throw it away otherwise.
14068 No attribute means no claim to conform. */
14069 if (!in_attr[i].s || !out_attr[i].s
14070 || strcmp (in_attr[i].s, out_attr[i].s) != 0)
14071 out_attr[i].s = NULL;
14072 break;
3cfad14c 14073
91e22acd 14074 default:
e8b36cd1
JM		 14075 result
14076 = result && _bfd_elf_merge_unknown_attribute_low (ibfd, obfd, i);
91e22acd
AS		 14077 }
14078
14079 /* If out_attr was copied from in_attr then it won't have a type yet. */
14080 if (in_attr[i].type && !out_attr[i].type)
14081 out_attr[i].type = in_attr[i].type;
ee065d83
PB		 14082 }
14083
104d59d1 14084 /* Merge Tag_compatibility attributes and any common GNU ones. */
50e03d47 14085 if (!_bfd_elf_merge_object_attributes (ibfd, info))
5488d830 14086 return FALSE;
ee065d83 14087
104d59d1 14088 /* Check for any attributes not known on ARM. */
e8b36cd1 14089 result &= _bfd_elf_merge_unknown_attribute_list (ibfd, obfd);
91e22acd 14090
91e22acd 14091 return result;
252b5132
RH		 14092}
14093
3a4a14e9
PB		 14094
14095/* Return TRUE if the two EABI versions are incompatible. */
14096
14097static bfd_boolean
14098elf32_arm_versions_compatible (unsigned iver, unsigned over)
14099{
14100 /* v4 and v5 are the same spec before and after it was released,
14101 so allow mixing them. */
14102 if ((iver == EF_ARM_EABI_VER4 && over == EF_ARM_EABI_VER5)
14103 || (iver == EF_ARM_EABI_VER5 && over == EF_ARM_EABI_VER4))
14104 return TRUE;
14105
14106 return (iver == over);
14107}
14108
252b5132
RH		 14109/* Merge backend specific data from an object file to the output
14110 object file when linking. */
9b485d32 14111
b34976b6 14112static bfd_boolean
50e03d47 14113elf32_arm_merge_private_bfd_data (bfd *, struct bfd_link_info *);
252b5132 14114
9b485d32
NC		 14115/* Display the flags field. */
14116
b34976b6 14117static bfd_boolean
57e8b36a 14118elf32_arm_print_private_bfd_data (bfd *abfd, void * ptr)
252b5132 14119{
fc830a83
NC		 14120 FILE * file = (FILE *) ptr;
14121 unsigned long flags;
252b5132
RH		 14122
14123 BFD_ASSERT (abfd != NULL && ptr != NULL);
14124
14125 /* Print normal ELF private data. */
14126 _bfd_elf_print_private_bfd_data (abfd, ptr);
14127
fc830a83 14128 flags = elf_elfheader (abfd)->e_flags;
9b485d32
NC		 14129 /* Ignore init flag - it may not be set, despite the flags field
14130 containing valid data. */
252b5132 14131
9b485d32 14132 fprintf (file, _("private flags = %lx:"), elf_elfheader (abfd)->e_flags);
252b5132 14133
fc830a83
NC		 14134 switch (EF_ARM_EABI_VERSION (flags))
14135 {
14136 case EF_ARM_EABI_UNKNOWN:
4cc11e76 14137 /* The following flag bits are GNU extensions and not part of the
fc830a83
NC		 14138 official ARM ELF extended ABI. Hence they are only decoded if
14139 the EABI version is not set. */
fd2ec330 14140 if (flags & EF_ARM_INTERWORK)
9b485d32 14141 fprintf (file, _(" [interworking enabled]"));
9a5aca8c 14142
fd2ec330 14143 if (flags & EF_ARM_APCS_26)
6c571f00 14144 fprintf (file, " [APCS-26]");
fc830a83 14145 else
6c571f00 14146 fprintf (file, " [APCS-32]");
9a5aca8c 14147
96a846ea
RE		 14148 if (flags & EF_ARM_VFP_FLOAT)
14149 fprintf (file, _(" [VFP float format]"));
fde78edd
NC		 14150 else if (flags & EF_ARM_MAVERICK_FLOAT)
14151 fprintf (file, _(" [Maverick float format]"));
96a846ea
RE		 14152 else
14153 fprintf (file, _(" [FPA float format]"));
14154
fd2ec330 14155 if (flags & EF_ARM_APCS_FLOAT)
9b485d32 14156 fprintf (file, _(" [floats passed in float registers]"));
9a5aca8c 14157
fd2ec330 14158 if (flags & EF_ARM_PIC)
9b485d32 14159 fprintf (file, _(" [position independent]"));
fc830a83 14160
fd2ec330 14161 if (flags & EF_ARM_NEW_ABI)
9b485d32 14162 fprintf (file, _(" [new ABI]"));
9a5aca8c 14163
fd2ec330 14164 if (flags & EF_ARM_OLD_ABI)
9b485d32 14165 fprintf (file, _(" [old ABI]"));
9a5aca8c 14166
fd2ec330 14167 if (flags & EF_ARM_SOFT_FLOAT)
9b485d32 14168 fprintf (file, _(" [software FP]"));
9a5aca8c 14169
96a846ea
RE		 14170 flags &= ~(EF_ARM_INTERWORK | EF_ARM_APCS_26 | EF_ARM_APCS_FLOAT
14171 | EF_ARM_PIC | EF_ARM_NEW_ABI | EF_ARM_OLD_ABI
fde78edd
NC		 14172 | EF_ARM_SOFT_FLOAT | EF_ARM_VFP_FLOAT
14173 | EF_ARM_MAVERICK_FLOAT);
fc830a83 14174 break;
9a5aca8c 14175
fc830a83 14176 case EF_ARM_EABI_VER1:
9b485d32 14177 fprintf (file, _(" [Version1 EABI]"));
9a5aca8c 14178
fc830a83 14179 if (flags & EF_ARM_SYMSARESORTED)
9b485d32 14180 fprintf (file, _(" [sorted symbol table]"));
fc830a83 14181 else
9b485d32 14182 fprintf (file, _(" [unsorted symbol table]"));
9a5aca8c 14183
fc830a83
NC		 14184 flags &= ~ EF_ARM_SYMSARESORTED;
14185 break;
9a5aca8c 14186
fd2ec330
PB		 14187 case EF_ARM_EABI_VER2:
14188 fprintf (file, _(" [Version2 EABI]"));
14189
14190 if (flags & EF_ARM_SYMSARESORTED)
14191 fprintf (file, _(" [sorted symbol table]"));
14192 else
14193 fprintf (file, _(" [unsorted symbol table]"));
14194
14195 if (flags & EF_ARM_DYNSYMSUSESEGIDX)
14196 fprintf (file, _(" [dynamic symbols use segment index]"));
14197
14198 if (flags & EF_ARM_MAPSYMSFIRST)
14199 fprintf (file, _(" [mapping symbols precede others]"));
14200
99e4ae17 14201 flags &= ~(EF_ARM_SYMSARESORTED | EF_ARM_DYNSYMSUSESEGIDX
fd2ec330
PB		 14202 | EF_ARM_MAPSYMSFIRST);
14203 break;
14204
d507cf36
PB		 14205 case EF_ARM_EABI_VER3:
14206 fprintf (file, _(" [Version3 EABI]"));
8cb51566
PB		 14207 break;
14208
14209 case EF_ARM_EABI_VER4:
14210 fprintf (file, _(" [Version4 EABI]"));
3a4a14e9 14211 goto eabi;
d507cf36 14212
3a4a14e9
PB		 14213 case EF_ARM_EABI_VER5:
14214 fprintf (file, _(" [Version5 EABI]"));
3bfcb652
NC		 14215
14216 if (flags & EF_ARM_ABI_FLOAT_SOFT)
14217 fprintf (file, _(" [soft-float ABI]"));
14218
14219 if (flags & EF_ARM_ABI_FLOAT_HARD)
14220 fprintf (file, _(" [hard-float ABI]"));
14221
14222 flags &= ~(EF_ARM_ABI_FLOAT_SOFT | EF_ARM_ABI_FLOAT_HARD);
14223
3a4a14e9 14224 eabi:
d507cf36
PB		 14225 if (flags & EF_ARM_BE8)
14226 fprintf (file, _(" [BE8]"));
14227
14228 if (flags & EF_ARM_LE8)
14229 fprintf (file, _(" [LE8]"));
14230
14231 flags &= ~(EF_ARM_LE8 | EF_ARM_BE8);
14232 break;
14233
fc830a83 14234 default:
9b485d32 14235 fprintf (file, _(" <EABI version unrecognised>"));
fc830a83
NC		 14236 break;
14237 }
252b5132 14238
fc830a83 14239 flags &= ~ EF_ARM_EABIMASK;
252b5132 14240
fc830a83 14241 if (flags & EF_ARM_RELEXEC)
9b485d32 14242 fprintf (file, _(" [relocatable executable]"));
252b5132 14243
a5721edd 14244 flags &= ~EF_ARM_RELEXEC;
fc830a83
NC		 14245
14246 if (flags)
9b485d32 14247 fprintf (file, _("<Unrecognised flag bits set>"));
9a5aca8c 14248
252b5132
RH		 14249 fputc ('\n', file);
14250
b34976b6 14251 return TRUE;
252b5132
RH		 14252}
14253
14254static int
57e8b36a 14255elf32_arm_get_symbol_type (Elf_Internal_Sym * elf_sym, int type)
252b5132 14256{
2f0ca46a
NC		 14257 switch (ELF_ST_TYPE (elf_sym->st_info))
14258 {
14259 case STT_ARM_TFUNC:
14260 return ELF_ST_TYPE (elf_sym->st_info);
ce855c42 14261
2f0ca46a
NC		 14262 case STT_ARM_16BIT:
14263 /* If the symbol is not an object, return the STT_ARM_16BIT flag.
14264 This allows us to distinguish between data used by Thumb instructions
14265 and non-data (which is probably code) inside Thumb regions of an
14266 executable. */
1a0eb693 14267 if (type != STT_OBJECT && type != STT_TLS)
2f0ca46a
NC		 14268 return ELF_ST_TYPE (elf_sym->st_info);
14269 break;
9a5aca8c 14270
ce855c42
NC		 14271 default:
14272 break;
2f0ca46a
NC		 14273 }
14274
14275 return type;
252b5132 14276}
f21f3fe0 14277
252b5132 14278static asection *
07adf181
AM		 14279elf32_arm_gc_mark_hook (asection *sec,
14280 struct bfd_link_info *info,
14281 Elf_Internal_Rela *rel,
14282 struct elf_link_hash_entry *h,
14283 Elf_Internal_Sym *sym)
252b5132
RH		 14284{
14285 if (h != NULL)
07adf181 14286 switch (ELF32_R_TYPE (rel->r_info))
252b5132
RH		 14287 {
14288 case R_ARM_GNU_VTINHERIT:
14289 case R_ARM_GNU_VTENTRY:
07adf181
AM		 14290 return NULL;
14291 }
9ad5cbcf 14292
07adf181 14293 return _bfd_elf_gc_mark_hook (sec, info, rel, h, sym);
252b5132
RH		 14294}
14295
780a67af
NC		 14296/* Update the got entry reference counts for the section being removed. */
14297
b34976b6 14298static bfd_boolean
ba93b8ac
DJ		 14299elf32_arm_gc_sweep_hook (bfd * abfd,
14300 struct bfd_link_info * info,
14301 asection * sec,
14302 const Elf_Internal_Rela * relocs)
252b5132 14303{
5e681ec4
PB		 14304 Elf_Internal_Shdr *symtab_hdr;
14305 struct elf_link_hash_entry **sym_hashes;
14306 bfd_signed_vma *local_got_refcounts;
14307 const Elf_Internal_Rela *rel, *relend;
eb043451
PB		 14308 struct elf32_arm_link_hash_table * globals;
14309
0e1862bb 14310 if (bfd_link_relocatable (info))
7dda2462
TG		 14311 return TRUE;
14312
eb043451 14313 globals = elf32_arm_hash_table (info);
4dfe6ac6
NC		 14314 if (globals == NULL)
14315 return FALSE;
5e681ec4
PB		 14316
14317 elf_section_data (sec)->local_dynrel = NULL;
14318
0ffa91dd 14319 symtab_hdr = & elf_symtab_hdr (abfd);
5e681ec4
PB		 14320 sym_hashes = elf_sym_hashes (abfd);
14321 local_got_refcounts = elf_local_got_refcounts (abfd);
14322
906e58ca 14323 check_use_blx (globals);
bd97cb95 14324
5e681ec4
PB		 14325 relend = relocs + sec->reloc_count;
14326 for (rel = relocs; rel < relend; rel++)
eb043451 14327 {
3eb128b2
AM		 14328 unsigned long r_symndx;
14329 struct elf_link_hash_entry *h = NULL;
f6e32f6d 14330 struct elf32_arm_link_hash_entry *eh;
eb043451 14331 int r_type;
34e77a92 14332 bfd_boolean call_reloc_p;
f6e32f6d
RS		 14333 bfd_boolean may_become_dynamic_p;
14334 bfd_boolean may_need_local_target_p;
34e77a92
RS		 14335 union gotplt_union *root_plt;
14336 struct arm_plt_info *arm_plt;
5e681ec4 14337
3eb128b2
AM		 14338 r_symndx = ELF32_R_SYM (rel->r_info);
14339 if (r_symndx >= symtab_hdr->sh_info)
14340 {
14341 h = sym_hashes[r_symndx - symtab_hdr->sh_info];
14342 while (h->root.type == bfd_link_hash_indirect
14343 || h->root.type == bfd_link_hash_warning)
14344 h = (struct elf_link_hash_entry *) h->root.u.i.link;
14345 }
f6e32f6d
RS		 14346 eh = (struct elf32_arm_link_hash_entry *) h;
14347
34e77a92 14348 call_reloc_p = FALSE;
f6e32f6d
RS		 14349 may_become_dynamic_p = FALSE;
14350 may_need_local_target_p = FALSE;
3eb128b2 14351
eb043451 14352 r_type = ELF32_R_TYPE (rel->r_info);
eb043451 14353 r_type = arm_real_reloc_type (globals, r_type);
eb043451
PB		 14354 switch (r_type)
14355 {
14356 case R_ARM_GOT32:
eb043451 14357 case R_ARM_GOT_PREL:
ba93b8ac
DJ		 14358 case R_ARM_TLS_GD32:
14359 case R_ARM_TLS_IE32:
3eb128b2 14360 if (h != NULL)
eb043451 14361 {
eb043451
PB		 14362 if (h->got.refcount > 0)
14363 h->got.refcount -= 1;
14364 }
14365 else if (local_got_refcounts != NULL)
14366 {
14367 if (local_got_refcounts[r_symndx] > 0)
14368 local_got_refcounts[r_symndx] -= 1;
14369 }
14370 break;
14371
ba93b8ac 14372 case R_ARM_TLS_LDM32:
4dfe6ac6 14373 globals->tls_ldm_got.refcount -= 1;
ba93b8ac
DJ		 14374 break;
14375
eb043451
PB		 14376 case R_ARM_PC24:
14377 case R_ARM_PLT32:
5b5bb741
PB		 14378 case R_ARM_CALL:
14379 case R_ARM_JUMP24:
eb043451 14380 case R_ARM_PREL31:
c19d1205 14381 case R_ARM_THM_CALL:
bd97cb95
DJ		 14382 case R_ARM_THM_JUMP24:
14383 case R_ARM_THM_JUMP19:
34e77a92 14384 call_reloc_p = TRUE;
f6e32f6d
RS		 14385 may_need_local_target_p = TRUE;
14386 break;
14387
14388 case R_ARM_ABS12:
14389 if (!globals->vxworks_p)
14390 {
14391 may_need_local_target_p = TRUE;
14392 break;
14393 }
14394 /* Fall through. */
14395 case R_ARM_ABS32:
14396 case R_ARM_ABS32_NOI:
14397 case R_ARM_REL32:
14398 case R_ARM_REL32_NOI:
b6895b4f
PB		 14399 case R_ARM_MOVW_ABS_NC:
14400 case R_ARM_MOVT_ABS:
14401 case R_ARM_MOVW_PREL_NC:
14402 case R_ARM_MOVT_PREL:
14403 case R_ARM_THM_MOVW_ABS_NC:
14404 case R_ARM_THM_MOVT_ABS:
14405 case R_ARM_THM_MOVW_PREL_NC:
14406 case R_ARM_THM_MOVT_PREL:
b7693d02 14407 /* Should the interworking branches be here also? */
0e1862bb 14408 if ((bfd_link_pic (info) || globals->root.is_relocatable_executable)
34e77a92
RS		 14409 && (sec->flags & SEC_ALLOC) != 0)
14410 {
14411 if (h == NULL
469a3493 14412 && elf32_arm_howto_from_type (r_type)->pc_relative)
34e77a92
RS		 14413 {
14414 call_reloc_p = TRUE;
14415 may_need_local_target_p = TRUE;
14416 }
14417 else
14418 may_become_dynamic_p = TRUE;
14419 }
f6e32f6d
RS		 14420 else
14421 may_need_local_target_p = TRUE;
14422 break;
b7693d02 14423
f6e32f6d
RS		 14424 default:
14425 break;
14426 }
5e681ec4 14427
34e77a92 14428 if (may_need_local_target_p
4ba2ef8f
TP		 14429 && elf32_arm_get_plt_info (abfd, globals, eh, r_symndx, &root_plt,
14430 &arm_plt))
f6e32f6d 14431 {
27586251
HPN		 14432 /* If PLT refcount book-keeping is wrong and too low, we'll
14433 see a zero value (going to -1) for the root PLT reference
14434 count. */
14435 if (root_plt->refcount >= 0)
14436 {
14437 BFD_ASSERT (root_plt->refcount != 0);
14438 root_plt->refcount -= 1;
14439 }
14440 else
14441 /* A value of -1 means the symbol has become local, forced
14442 or seeing a hidden definition. Any other negative value
14443 is an error. */
14444 BFD_ASSERT (root_plt->refcount == -1);
34e77a92
RS		 14445
14446 if (!call_reloc_p)
14447 arm_plt->noncall_refcount--;
5e681ec4 14448
f6e32f6d 14449 if (r_type == R_ARM_THM_CALL)
34e77a92 14450 arm_plt->maybe_thumb_refcount--;
bd97cb95 14451
f6e32f6d
RS		 14452 if (r_type == R_ARM_THM_JUMP24
14453 || r_type == R_ARM_THM_JUMP19)
34e77a92 14454 arm_plt->thumb_refcount--;
f6e32f6d 14455 }
5e681ec4 14456
34e77a92 14457 if (may_become_dynamic_p)
f6e32f6d
RS		 14458 {
14459 struct elf_dyn_relocs **pp;
14460 struct elf_dyn_relocs *p;
5e681ec4 14461
34e77a92 14462 if (h != NULL)
9c489990 14463 pp = &(eh->dyn_relocs);
34e77a92
RS		 14464 else
14465 {
14466 Elf_Internal_Sym *isym;
14467
14468 isym = bfd_sym_from_r_symndx (&globals->sym_cache,
14469 abfd, r_symndx);
14470 if (isym == NULL)
14471 return FALSE;
14472 pp = elf32_arm_get_local_dynreloc_list (abfd, r_symndx, isym);
14473 if (pp == NULL)
14474 return FALSE;
14475 }
9c489990 14476 for (; (p = *pp) != NULL; pp = &p->next)
f6e32f6d
RS		 14477 if (p->sec == sec)
14478 {
14479 /* Everything must go for SEC. */
14480 *pp = p->next;
14481 break;
14482 }
eb043451
PB		 14483 }
14484 }
5e681ec4 14485
b34976b6 14486 return TRUE;
252b5132
RH		 14487}
14488
780a67af
NC		 14489/* Look through the relocs for a section during the first phase. */
14490
b34976b6 14491static bfd_boolean
57e8b36a
NC		 14492elf32_arm_check_relocs (bfd *abfd, struct bfd_link_info *info,
14493 asection *sec, const Elf_Internal_Rela *relocs)
252b5132 14494{
b34976b6
AM		 14495 Elf_Internal_Shdr *symtab_hdr;
14496 struct elf_link_hash_entry **sym_hashes;
b34976b6
AM		 14497 const Elf_Internal_Rela *rel;
14498 const Elf_Internal_Rela *rel_end;
14499 bfd *dynobj;
5e681ec4 14500 asection *sreloc;
5e681ec4 14501 struct elf32_arm_link_hash_table *htab;
f6e32f6d
RS		 14502 bfd_boolean call_reloc_p;
14503 bfd_boolean may_become_dynamic_p;
14504 bfd_boolean may_need_local_target_p;
ce98a316 14505 unsigned long nsyms;
9a5aca8c 14506
0e1862bb 14507 if (bfd_link_relocatable (info))
b34976b6 14508 return TRUE;
9a5aca8c 14509
0ffa91dd
NC		 14510 BFD_ASSERT (is_arm_elf (abfd));
14511
5e681ec4 14512 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 14513 if (htab == NULL)
14514 return FALSE;
14515
5e681ec4 14516 sreloc = NULL;
9a5aca8c 14517
67687978
PB		 14518 /* Create dynamic sections for relocatable executables so that we can
14519 copy relocations. */
14520 if (htab->root.is_relocatable_executable
14521 && ! htab->root.dynamic_sections_created)
14522 {
14523 if (! _bfd_elf_link_create_dynamic_sections (abfd, info))
14524 return FALSE;
14525 }
14526
cbc704f3
RS		 14527 if (htab->root.dynobj == NULL)
14528 htab->root.dynobj = abfd;
34e77a92
RS		 14529 if (!create_ifunc_sections (info))
14530 return FALSE;
cbc704f3
RS		 14531
14532 dynobj = htab->root.dynobj;
14533
0ffa91dd 14534 symtab_hdr = & elf_symtab_hdr (abfd);
252b5132 14535 sym_hashes = elf_sym_hashes (abfd);
ce98a316 14536 nsyms = NUM_SHDR_ENTRIES (symtab_hdr);
b38cadfb 14537
252b5132
RH		 14538 rel_end = relocs + sec->reloc_count;
14539 for (rel = relocs; rel < rel_end; rel++)
14540 {
34e77a92 14541 Elf_Internal_Sym *isym;
252b5132 14542 struct elf_link_hash_entry *h;
b7693d02 14543 struct elf32_arm_link_hash_entry *eh;
252b5132 14544 unsigned long r_symndx;
eb043451 14545 int r_type;
9a5aca8c 14546
252b5132 14547 r_symndx = ELF32_R_SYM (rel->r_info);
eb043451 14548 r_type = ELF32_R_TYPE (rel->r_info);
eb043451 14549 r_type = arm_real_reloc_type (htab, r_type);
ba93b8ac 14550
ce98a316
NC		 14551 if (r_symndx >= nsyms
14552 /* PR 9934: It is possible to have relocations that do not
14553 refer to symbols, thus it is also possible to have an
14554 object file containing relocations but no symbol table. */
cf35638d 14555 && (r_symndx > STN_UNDEF || nsyms > 0))
ba93b8ac 14556 {
4eca0228
AM		 14557 _bfd_error_handler (_("%B: bad symbol index: %d"), abfd,
14558 r_symndx);
ba93b8ac
DJ		 14559 return FALSE;
14560 }
14561
34e77a92
RS		 14562 h = NULL;
14563 isym = NULL;
14564 if (nsyms > 0)
973a3492 14565 {
34e77a92
RS		 14566 if (r_symndx < symtab_hdr->sh_info)
14567 {
14568 /* A local symbol. */
14569 isym = bfd_sym_from_r_symndx (&htab->sym_cache,
14570 abfd, r_symndx);
14571 if (isym == NULL)
14572 return FALSE;
14573 }
14574 else
14575 {
14576 h = sym_hashes[r_symndx - symtab_hdr->sh_info];
14577 while (h->root.type == bfd_link_hash_indirect
14578 || h->root.type == bfd_link_hash_warning)
14579 h = (struct elf_link_hash_entry *) h->root.u.i.link;
81fbe831
AM		 14580
14581 /* PR15323, ref flags aren't set for references in the
14582 same object. */
bc4e12de 14583 h->root.non_ir_ref_regular = 1;
34e77a92 14584 }
973a3492 14585 }
9a5aca8c 14586
b7693d02
DJ		 14587 eh = (struct elf32_arm_link_hash_entry *) h;
14588
f6e32f6d
RS		 14589 call_reloc_p = FALSE;
14590 may_become_dynamic_p = FALSE;
14591 may_need_local_target_p = FALSE;
14592
0855e32b
NS		 14593 /* Could be done earlier, if h were already available. */
14594 r_type = elf32_arm_tls_transition (info, r_type, h);
eb043451 14595 switch (r_type)
99059e56 14596 {
5e681ec4 14597 case R_ARM_GOT32:
eb043451 14598 case R_ARM_GOT_PREL:
ba93b8ac
DJ		 14599 case R_ARM_TLS_GD32:
14600 case R_ARM_TLS_IE32:
0855e32b
NS		 14601 case R_ARM_TLS_GOTDESC:
14602 case R_ARM_TLS_DESCSEQ:
14603 case R_ARM_THM_TLS_DESCSEQ:
14604 case R_ARM_TLS_CALL:
14605 case R_ARM_THM_TLS_CALL:
5e681ec4 14606 /* This symbol requires a global offset table entry. */
ba93b8ac
DJ		 14607 {
14608 int tls_type, old_tls_type;
5e681ec4 14609
ba93b8ac
DJ		 14610 switch (r_type)
14611 {
14612 case R_ARM_TLS_GD32: tls_type = GOT_TLS_GD; break;
b38cadfb 14613
ba93b8ac 14614 case R_ARM_TLS_IE32: tls_type = GOT_TLS_IE; break;
b38cadfb 14615
0855e32b
NS		 14616 case R_ARM_TLS_GOTDESC:
14617 case R_ARM_TLS_CALL: case R_ARM_THM_TLS_CALL:
14618 case R_ARM_TLS_DESCSEQ: case R_ARM_THM_TLS_DESCSEQ:
14619 tls_type = GOT_TLS_GDESC; break;
b38cadfb 14620
ba93b8ac
DJ		 14621 default: tls_type = GOT_NORMAL; break;
14622 }
252b5132 14623
0e1862bb 14624 if (!bfd_link_executable (info) && (tls_type & GOT_TLS_IE))
eea6dad2
KM		 14625 info->flags |= DF_STATIC_TLS;
14626
ba93b8ac
DJ		 14627 if (h != NULL)
14628 {
14629 h->got.refcount++;
14630 old_tls_type = elf32_arm_hash_entry (h)->tls_type;
14631 }
14632 else
14633 {
ba93b8ac 14634 /* This is a global offset table entry for a local symbol. */
34e77a92
RS		 14635 if (!elf32_arm_allocate_local_sym_info (abfd))
14636 return FALSE;
14637 elf_local_got_refcounts (abfd)[r_symndx] += 1;
ba93b8ac
DJ		 14638 old_tls_type = elf32_arm_local_got_tls_type (abfd) [r_symndx];
14639 }
14640
0855e32b 14641 /* If a variable is accessed with both tls methods, two
99059e56 14642 slots may be created. */
0855e32b
NS		 14643 if (GOT_TLS_GD_ANY_P (old_tls_type)
14644 && GOT_TLS_GD_ANY_P (tls_type))
14645 tls_type |= old_tls_type;
14646
14647 /* We will already have issued an error message if there
14648 is a TLS/non-TLS mismatch, based on the symbol
14649 type. So just combine any TLS types needed. */
ba93b8ac
DJ		 14650 if (old_tls_type != GOT_UNKNOWN && old_tls_type != GOT_NORMAL
14651 && tls_type != GOT_NORMAL)
14652 tls_type |= old_tls_type;
14653
0855e32b 14654 /* If the symbol is accessed in both IE and GDESC
99059e56
RM		 14655 method, we're able to relax. Turn off the GDESC flag,
14656 without messing up with any other kind of tls types
6a631e86 14657 that may be involved. */
0855e32b
NS		 14658 if ((tls_type & GOT_TLS_IE) && (tls_type & GOT_TLS_GDESC))
14659 tls_type &= ~GOT_TLS_GDESC;
14660
ba93b8ac
DJ		 14661 if (old_tls_type != tls_type)
14662 {
14663 if (h != NULL)
14664 elf32_arm_hash_entry (h)->tls_type = tls_type;
14665 else
14666 elf32_arm_local_got_tls_type (abfd) [r_symndx] = tls_type;
14667 }
14668 }
8029a119 14669 /* Fall through. */
ba93b8ac
DJ		 14670
14671 case R_ARM_TLS_LDM32:
14672 if (r_type == R_ARM_TLS_LDM32)
14673 htab->tls_ldm_got.refcount++;
8029a119 14674 /* Fall through. */
252b5132 14675
c19d1205 14676 case R_ARM_GOTOFF32:
5e681ec4 14677 case R_ARM_GOTPC:
cbc704f3
RS		 14678 if (htab->root.sgot == NULL
14679 && !create_got_section (htab->root.dynobj, info))
14680 return FALSE;
252b5132
RH		 14681 break;
14682
252b5132 14683 case R_ARM_PC24:
7359ea65 14684 case R_ARM_PLT32:
5b5bb741
PB		 14685 case R_ARM_CALL:
14686 case R_ARM_JUMP24:
eb043451 14687 case R_ARM_PREL31:
c19d1205 14688 case R_ARM_THM_CALL:
bd97cb95
DJ		 14689 case R_ARM_THM_JUMP24:
14690 case R_ARM_THM_JUMP19:
f6e32f6d
RS		 14691 call_reloc_p = TRUE;
14692 may_need_local_target_p = TRUE;
14693 break;
14694
14695 case R_ARM_ABS12:
14696 /* VxWorks uses dynamic R_ARM_ABS12 relocations for
14697 ldr __GOTT_INDEX__ offsets. */
14698 if (!htab->vxworks_p)
14699 {
14700 may_need_local_target_p = TRUE;
14701 break;
14702 }
aebf9be7 14703 else goto jump_over;
9eaff861 14704
f6e32f6d 14705 /* Fall through. */
39623e12 14706
96c23d59
JM		 14707 case R_ARM_MOVW_ABS_NC:
14708 case R_ARM_MOVT_ABS:
14709 case R_ARM_THM_MOVW_ABS_NC:
14710 case R_ARM_THM_MOVT_ABS:
0e1862bb 14711 if (bfd_link_pic (info))
96c23d59 14712 {
4eca0228 14713 _bfd_error_handler
96c23d59
JM		 14714 (_("%B: relocation %s against `%s' can not be used when making a shared object; recompile with -fPIC"),
14715 abfd, elf32_arm_howto_table_1[r_type].name,
14716 (h) ? h->root.root.string : "a local symbol");
14717 bfd_set_error (bfd_error_bad_value);
14718 return FALSE;
14719 }
14720
14721 /* Fall through. */
39623e12
PB		 14722 case R_ARM_ABS32:
14723 case R_ARM_ABS32_NOI:
aebf9be7 14724 jump_over:
0e1862bb 14725 if (h != NULL && bfd_link_executable (info))
97323ad1
WN		 14726 {
14727 h->pointer_equality_needed = 1;
14728 }
14729 /* Fall through. */
39623e12
PB		 14730 case R_ARM_REL32:
14731 case R_ARM_REL32_NOI:
b6895b4f
PB		 14732 case R_ARM_MOVW_PREL_NC:
14733 case R_ARM_MOVT_PREL:
b6895b4f
PB		 14734 case R_ARM_THM_MOVW_PREL_NC:
14735 case R_ARM_THM_MOVT_PREL:
39623e12 14736
b7693d02 14737 /* Should the interworking branches be listed here? */
0e1862bb 14738 if ((bfd_link_pic (info) || htab->root.is_relocatable_executable)
34e77a92
RS		 14739 && (sec->flags & SEC_ALLOC) != 0)
14740 {
14741 if (h == NULL
469a3493 14742 && elf32_arm_howto_from_type (r_type)->pc_relative)
34e77a92
RS		 14743 {
14744 /* In shared libraries and relocatable executables,
14745 we treat local relative references as calls;
14746 see the related SYMBOL_CALLS_LOCAL code in
14747 allocate_dynrelocs. */
14748 call_reloc_p = TRUE;
14749 may_need_local_target_p = TRUE;
14750 }
14751 else
14752 /* We are creating a shared library or relocatable
14753 executable, and this is a reloc against a global symbol,
14754 or a non-PC-relative reloc against a local symbol.
14755 We may need to copy the reloc into the output. */
14756 may_become_dynamic_p = TRUE;
14757 }
f6e32f6d
RS		 14758 else
14759 may_need_local_target_p = TRUE;
252b5132
RH		 14760 break;
14761
99059e56
RM		 14762 /* This relocation describes the C++ object vtable hierarchy.
14763 Reconstruct it for later use during GC. */
14764 case R_ARM_GNU_VTINHERIT:
14765 if (!bfd_elf_gc_record_vtinherit (abfd, sec, h, rel->r_offset))
14766 return FALSE;
14767 break;
14768
14769 /* This relocation describes which C++ vtable entries are actually
14770 used. Record for later use during GC. */
14771 case R_ARM_GNU_VTENTRY:
14772 BFD_ASSERT (h != NULL);
14773 if (h != NULL
14774 && !bfd_elf_gc_record_vtentry (abfd, sec, h, rel->r_offset))
14775 return FALSE;
14776 break;
14777 }
f6e32f6d
RS		 14778
14779 if (h != NULL)
14780 {
14781 if (call_reloc_p)
14782 /* We may need a .plt entry if the function this reloc
14783 refers to is in a different object, regardless of the
14784 symbol's type. We can't tell for sure yet, because
14785 something later might force the symbol local. */
14786 h->needs_plt = 1;
14787 else if (may_need_local_target_p)
14788 /* If this reloc is in a read-only section, we might
14789 need a copy reloc. We can't check reliably at this
14790 stage whether the section is read-only, as input
14791 sections have not yet been mapped to output sections.
14792 Tentatively set the flag for now, and correct in
14793 adjust_dynamic_symbol. */
14794 h->non_got_ref = 1;
14795 }
14796
34e77a92
RS		 14797 if (may_need_local_target_p
14798 && (h != NULL || ELF32_ST_TYPE (isym->st_info) == STT_GNU_IFUNC))
f6e32f6d 14799 {
34e77a92
RS		 14800 union gotplt_union *root_plt;
14801 struct arm_plt_info *arm_plt;
14802 struct arm_local_iplt_info *local_iplt;
14803
14804 if (h != NULL)
14805 {
14806 root_plt = &h->plt;
14807 arm_plt = &eh->plt;
14808 }
14809 else
14810 {
14811 local_iplt = elf32_arm_create_local_iplt (abfd, r_symndx);
14812 if (local_iplt == NULL)
14813 return FALSE;
14814 root_plt = &local_iplt->root;
14815 arm_plt = &local_iplt->arm;
14816 }
14817
f6e32f6d
RS		 14818 /* If the symbol is a function that doesn't bind locally,
14819 this relocation will need a PLT entry. */
a8c887dd
NC		 14820 if (root_plt->refcount != -1)
14821 root_plt->refcount += 1;
34e77a92
RS		 14822
14823 if (!call_reloc_p)
14824 arm_plt->noncall_refcount++;
f6e32f6d
RS		 14825
14826 /* It's too early to use htab->use_blx here, so we have to
14827 record possible blx references separately from
14828 relocs that definitely need a thumb stub. */
14829
14830 if (r_type == R_ARM_THM_CALL)
34e77a92 14831 arm_plt->maybe_thumb_refcount += 1;
f6e32f6d
RS		 14832
14833 if (r_type == R_ARM_THM_JUMP24
14834 || r_type == R_ARM_THM_JUMP19)
34e77a92 14835 arm_plt->thumb_refcount += 1;
f6e32f6d
RS		 14836 }
14837
14838 if (may_become_dynamic_p)
14839 {
14840 struct elf_dyn_relocs *p, **head;
14841
14842 /* Create a reloc section in dynobj. */
14843 if (sreloc == NULL)
14844 {
14845 sreloc = _bfd_elf_make_dynamic_reloc_section
14846 (sec, dynobj, 2, abfd, ! htab->use_rel);
14847
14848 if (sreloc == NULL)
14849 return FALSE;
14850
14851 /* BPABI objects never have dynamic relocations mapped. */
14852 if (htab->symbian_p)
14853 {
14854 flagword flags;
14855
14856 flags = bfd_get_section_flags (dynobj, sreloc);
14857 flags &= ~(SEC_LOAD | SEC_ALLOC);
14858 bfd_set_section_flags (dynobj, sreloc, flags);
14859 }
14860 }
14861
14862 /* If this is a global symbol, count the number of
14863 relocations we need for this symbol. */
14864 if (h != NULL)
14865 head = &((struct elf32_arm_link_hash_entry *) h)->dyn_relocs;
14866 else
14867 {
34e77a92
RS		 14868 head = elf32_arm_get_local_dynreloc_list (abfd, r_symndx, isym);
14869 if (head == NULL)
f6e32f6d 14870 return FALSE;
f6e32f6d
RS		 14871 }
14872
14873 p = *head;
14874 if (p == NULL || p->sec != sec)
14875 {
14876 bfd_size_type amt = sizeof *p;
14877
14878 p = (struct elf_dyn_relocs *) bfd_alloc (htab->root.dynobj, amt);
14879 if (p == NULL)
14880 return FALSE;
14881 p->next = *head;
14882 *head = p;
14883 p->sec = sec;
14884 p->count = 0;
14885 p->pc_count = 0;
14886 }
14887
469a3493 14888 if (elf32_arm_howto_from_type (r_type)->pc_relative)
f6e32f6d
RS		 14889 p->pc_count += 1;
14890 p->count += 1;
14891 }
252b5132 14892 }
f21f3fe0 14893
b34976b6 14894 return TRUE;
252b5132
RH		 14895}
14896
9eaff861
AO		 14897static void
14898elf32_arm_update_relocs (asection *o,
14899 struct bfd_elf_section_reloc_data *reldata)
14900{
14901 void (*swap_in) (bfd *, const bfd_byte *, Elf_Internal_Rela *);
14902 void (*swap_out) (bfd *, const Elf_Internal_Rela *, bfd_byte *);
14903 const struct elf_backend_data *bed;
14904 _arm_elf_section_data *eado;
14905 struct bfd_link_order *p;
14906 bfd_byte *erela_head, *erela;
14907 Elf_Internal_Rela *irela_head, *irela;
14908 Elf_Internal_Shdr *rel_hdr;
14909 bfd *abfd;
14910 unsigned int count;
14911
14912 eado = get_arm_elf_section_data (o);
14913
14914 if (!eado || eado->elf.this_hdr.sh_type != SHT_ARM_EXIDX)
14915 return;
14916
14917 abfd = o->owner;
14918 bed = get_elf_backend_data (abfd);
14919 rel_hdr = reldata->hdr;
14920
14921 if (rel_hdr->sh_entsize == bed->s->sizeof_rel)
14922 {
14923 swap_in = bed->s->swap_reloc_in;
14924 swap_out = bed->s->swap_reloc_out;
14925 }
14926 else if (rel_hdr->sh_entsize == bed->s->sizeof_rela)
14927 {
14928 swap_in = bed->s->swap_reloca_in;
14929 swap_out = bed->s->swap_reloca_out;
14930 }
14931 else
14932 abort ();
14933
14934 erela_head = rel_hdr->contents;
14935 irela_head = (Elf_Internal_Rela *) bfd_zmalloc
14936 ((NUM_SHDR_ENTRIES (rel_hdr) + 1) * sizeof (*irela_head));
14937
14938 erela = erela_head;
14939 irela = irela_head;
14940 count = 0;
14941
14942 for (p = o->map_head.link_order; p; p = p->next)
14943 {
14944 if (p->type == bfd_section_reloc_link_order
14945 || p->type == bfd_symbol_reloc_link_order)
14946 {
14947 (*swap_in) (abfd, erela, irela);
14948 erela += rel_hdr->sh_entsize;
14949 irela++;
14950 count++;
14951 }
14952 else if (p->type == bfd_indirect_link_order)
14953 {
14954 struct bfd_elf_section_reloc_data *input_reldata;
14955 arm_unwind_table_edit *edit_list, *edit_tail;
14956 _arm_elf_section_data *eadi;
14957 bfd_size_type j;
14958 bfd_vma offset;
14959 asection *i;
14960
14961 i = p->u.indirect.section;
14962
14963 eadi = get_arm_elf_section_data (i);
14964 edit_list = eadi->u.exidx.unwind_edit_list;
14965 edit_tail = eadi->u.exidx.unwind_edit_tail;
14966 offset = o->vma + i->output_offset;
14967
14968 if (eadi->elf.rel.hdr &&
14969 eadi->elf.rel.hdr->sh_entsize == rel_hdr->sh_entsize)
14970 input_reldata = &eadi->elf.rel;
14971 else if (eadi->elf.rela.hdr &&
14972 eadi->elf.rela.hdr->sh_entsize == rel_hdr->sh_entsize)
14973 input_reldata = &eadi->elf.rela;
14974 else
14975 abort ();
14976
14977 if (edit_list)
14978 {
14979 for (j = 0; j < NUM_SHDR_ENTRIES (input_reldata->hdr); j++)
14980 {
14981 arm_unwind_table_edit *edit_node, *edit_next;
14982 bfd_vma bias;
c48182bf 14983 bfd_vma reloc_index;
9eaff861
AO		 14984
14985 (*swap_in) (abfd, erela, irela);
c48182bf 14986 reloc_index = (irela->r_offset - offset) / 8;
9eaff861
AO		 14987
14988 bias = 0;
14989 edit_node = edit_list;
14990 for (edit_next = edit_list;
c48182bf 14991 edit_next && edit_next->index <= reloc_index;
9eaff861
AO		 14992 edit_next = edit_node->next)
14993 {
14994 bias++;
14995 edit_node = edit_next;
14996 }
14997
14998 if (edit_node->type != DELETE_EXIDX_ENTRY
c48182bf 14999 || edit_node->index != reloc_index)
9eaff861
AO		 15000 {
15001 irela->r_offset -= bias * 8;
15002 irela++;
15003 count++;
15004 }
15005
15006 erela += rel_hdr->sh_entsize;
15007 }
15008
15009 if (edit_tail->type == INSERT_EXIDX_CANTUNWIND_AT_END)
15010 {
15011 /* New relocation entity. */
15012 asection *text_sec = edit_tail->linked_section;
15013 asection *text_out = text_sec->output_section;
15014 bfd_vma exidx_offset = offset + i->size - 8;
15015
15016 irela->r_addend = 0;
15017 irela->r_offset = exidx_offset;
15018 irela->r_info = ELF32_R_INFO
15019 (text_out->target_index, R_ARM_PREL31);
15020 irela++;
15021 count++;
15022 }
15023 }
15024 else
15025 {
15026 for (j = 0; j < NUM_SHDR_ENTRIES (input_reldata->hdr); j++)
15027 {
15028 (*swap_in) (abfd, erela, irela);
15029 erela += rel_hdr->sh_entsize;
15030 irela++;
15031 }
15032
15033 count += NUM_SHDR_ENTRIES (input_reldata->hdr);
15034 }
15035 }
15036 }
15037
15038 reldata->count = count;
15039 rel_hdr->sh_size = count * rel_hdr->sh_entsize;
15040
15041 erela = erela_head;
15042 irela = irela_head;
15043 while (count > 0)
15044 {
15045 (*swap_out) (abfd, irela, erela);
15046 erela += rel_hdr->sh_entsize;
15047 irela++;
15048 count--;
15049 }
15050
15051 free (irela_head);
15052
15053 /* Hashes are no longer valid. */
15054 free (reldata->hashes);
15055 reldata->hashes = NULL;
15056}
15057
6a5bb875 15058/* Unwinding tables are not referenced directly. This pass marks them as
4ba2ef8f
TP		 15059 required if the corresponding code section is marked. Similarly, ARMv8-M
15060 secure entry functions can only be referenced by SG veneers which are
15061 created after the GC process. They need to be marked in case they reside in
15062 their own section (as would be the case if code was compiled with
15063 -ffunction-sections). */
6a5bb875
PB		 15064
15065static bfd_boolean
906e58ca
NC		 15066elf32_arm_gc_mark_extra_sections (struct bfd_link_info *info,
15067 elf_gc_mark_hook_fn gc_mark_hook)
6a5bb875
PB		 15068{
15069 bfd *sub;
15070 Elf_Internal_Shdr **elf_shdrp;
4ba2ef8f
TP		 15071 asection *cmse_sec;
15072 obj_attribute *out_attr;
15073 Elf_Internal_Shdr *symtab_hdr;
15074 unsigned i, sym_count, ext_start;
15075 const struct elf_backend_data *bed;
15076 struct elf_link_hash_entry **sym_hashes;
15077 struct elf32_arm_link_hash_entry *cmse_hash;
15078 bfd_boolean again, is_v8m, first_bfd_browse = TRUE;
6a5bb875 15079
7f6ab9f8
AM		 15080 _bfd_elf_gc_mark_extra_sections (info, gc_mark_hook);
15081
4ba2ef8f
TP		 15082 out_attr = elf_known_obj_attributes_proc (info->output_bfd);
15083 is_v8m = out_attr[Tag_CPU_arch].i >= TAG_CPU_ARCH_V8M_BASE
15084 && out_attr[Tag_CPU_arch_profile].i == 'M';
15085
6a5bb875
PB		 15086 /* Marking EH data may cause additional code sections to be marked,
15087 requiring multiple passes. */
15088 again = TRUE;
15089 while (again)
15090 {
15091 again = FALSE;
c72f2fb2 15092 for (sub = info->input_bfds; sub != NULL; sub = sub->link.next)
6a5bb875
PB		 15093 {
15094 asection *o;
15095
0ffa91dd 15096 if (! is_arm_elf (sub))
6a5bb875
PB		 15097 continue;
15098
15099 elf_shdrp = elf_elfsections (sub);
15100 for (o = sub->sections; o != NULL; o = o->next)
15101 {
15102 Elf_Internal_Shdr *hdr;
0ffa91dd 15103
6a5bb875 15104 hdr = &elf_section_data (o)->this_hdr;
4fbb74a6
AM		 15105 if (hdr->sh_type == SHT_ARM_EXIDX
15106 && hdr->sh_link
15107 && hdr->sh_link < elf_numsections (sub)
6a5bb875
PB		 15108 && !o->gc_mark
15109 && elf_shdrp[hdr->sh_link]->bfd_section->gc_mark)
15110 {
15111 again = TRUE;
15112 if (!_bfd_elf_gc_mark (info, o, gc_mark_hook))
15113 return FALSE;
15114 }
15115 }
4ba2ef8f
TP		 15116
15117 /* Mark section holding ARMv8-M secure entry functions. We mark all
15118 of them so no need for a second browsing. */
15119 if (is_v8m && first_bfd_browse)
15120 {
15121 sym_hashes = elf_sym_hashes (sub);
15122 bed = get_elf_backend_data (sub);
15123 symtab_hdr = &elf_tdata (sub)->symtab_hdr;
15124 sym_count = symtab_hdr->sh_size / bed->s->sizeof_sym;
15125 ext_start = symtab_hdr->sh_info;
15126
15127 /* Scan symbols. */
15128 for (i = ext_start; i < sym_count; i++)
15129 {
15130 cmse_hash = elf32_arm_hash_entry (sym_hashes[i - ext_start]);
15131
15132 /* Assume it is a special symbol. If not, cmse_scan will
15133 warn about it and user can do something about it. */
15134 if (ARM_GET_SYM_CMSE_SPCL (cmse_hash->root.target_internal))
15135 {
15136 cmse_sec = cmse_hash->root.root.u.def.section;
5025eb7c
AO		 15137 if (!cmse_sec->gc_mark
15138 && !_bfd_elf_gc_mark (info, cmse_sec, gc_mark_hook))
4ba2ef8f
TP		 15139 return FALSE;
15140 }
15141 }
15142 }
6a5bb875 15143 }
4ba2ef8f 15144 first_bfd_browse = FALSE;
6a5bb875
PB		 15145 }
15146
15147 return TRUE;
15148}
15149
3c9458e9
NC		 15150/* Treat mapping symbols as special target symbols. */
15151
15152static bfd_boolean
15153elf32_arm_is_target_special_symbol (bfd * abfd ATTRIBUTE_UNUSED, asymbol * sym)
15154{
b0796911
PB		 15155 return bfd_is_arm_special_symbol_name (sym->name,
15156 BFD_ARM_SPECIAL_SYM_TYPE_ANY);
3c9458e9
NC		 15157}
15158
0367ecfb
NC		 15159/* This is a copy of elf_find_function() from elf.c except that
15160 ARM mapping symbols are ignored when looking for function names
15161 and STT_ARM_TFUNC is considered to a function type. */
252b5132 15162
0367ecfb
NC		 15163static bfd_boolean
15164arm_elf_find_function (bfd * abfd ATTRIBUTE_UNUSED,
0367ecfb 15165 asymbol ** symbols,
fb167eb2 15166 asection * section,
0367ecfb
NC		 15167 bfd_vma offset,
15168 const char ** filename_ptr,
15169 const char ** functionname_ptr)
15170{
15171 const char * filename = NULL;
15172 asymbol * func = NULL;
15173 bfd_vma low_func = 0;
15174 asymbol ** p;
252b5132
RH		 15175
15176 for (p = symbols; *p != NULL; p++)
15177 {
15178 elf_symbol_type *q;
15179
15180 q = (elf_symbol_type *) *p;
15181
252b5132
RH		 15182 switch (ELF_ST_TYPE (q->internal_elf_sym.st_info))
15183 {
15184 default:
15185 break;
15186 case STT_FILE:
15187 filename = bfd_asymbol_name (&q->symbol);
15188 break;
252b5132
RH		 15189 case STT_FUNC:
15190 case STT_ARM_TFUNC:
9d2da7ca 15191 case STT_NOTYPE:
b0796911 15192 /* Skip mapping symbols. */
0367ecfb 15193 if ((q->symbol.flags & BSF_LOCAL)
b0796911
PB		 15194 && bfd_is_arm_special_symbol_name (q->symbol.name,
15195 BFD_ARM_SPECIAL_SYM_TYPE_ANY))
0367ecfb
NC		 15196 continue;
15197 /* Fall through. */
6b40fcba 15198 if (bfd_get_section (&q->symbol) == section
252b5132
RH		 15199 && q->symbol.value >= low_func
15200 && q->symbol.value <= offset)
15201 {
15202 func = (asymbol *) q;
15203 low_func = q->symbol.value;
15204 }
15205 break;
15206 }
15207 }
15208
15209 if (func == NULL)
b34976b6 15210 return FALSE;
252b5132 15211
0367ecfb
NC		 15212 if (filename_ptr)
15213 *filename_ptr = filename;
15214 if (functionname_ptr)
15215 *functionname_ptr = bfd_asymbol_name (func);
15216
15217 return TRUE;
906e58ca 15218}
0367ecfb
NC		 15219
15220
15221/* Find the nearest line to a particular section and offset, for error
15222 reporting. This code is a duplicate of the code in elf.c, except
15223 that it uses arm_elf_find_function. */
15224
15225static bfd_boolean
15226elf32_arm_find_nearest_line (bfd * abfd,
0367ecfb 15227 asymbol ** symbols,
fb167eb2 15228 asection * section,
0367ecfb
NC		 15229 bfd_vma offset,
15230 const char ** filename_ptr,
15231 const char ** functionname_ptr,
fb167eb2
AM		 15232 unsigned int * line_ptr,
15233 unsigned int * discriminator_ptr)
0367ecfb
NC		 15234{
15235 bfd_boolean found = FALSE;
15236
fb167eb2 15237 if (_bfd_dwarf2_find_nearest_line (abfd, symbols, NULL, section, offset,
0367ecfb 15238 filename_ptr, functionname_ptr,
fb167eb2
AM		 15239 line_ptr, discriminator_ptr,
15240 dwarf_debug_sections, 0,
0367ecfb
NC		 15241 & elf_tdata (abfd)->dwarf2_find_line_info))
15242 {
15243 if (!*functionname_ptr)
fb167eb2 15244 arm_elf_find_function (abfd, symbols, section, offset,
0367ecfb
NC		 15245 *filename_ptr ? NULL : filename_ptr,
15246 functionname_ptr);
f21f3fe0 15247
0367ecfb
NC		 15248 return TRUE;
15249 }
15250
fb167eb2
AM		 15251 /* Skip _bfd_dwarf1_find_nearest_line since no known ARM toolchain
15252 uses DWARF1. */
15253
0367ecfb
NC		 15254 if (! _bfd_stab_section_find_nearest_line (abfd, symbols, section, offset,
15255 & found, filename_ptr,
15256 functionname_ptr, line_ptr,
15257 & elf_tdata (abfd)->line_info))
15258 return FALSE;
15259
15260 if (found && (*functionname_ptr || *line_ptr))
15261 return TRUE;
15262
15263 if (symbols == NULL)
15264 return FALSE;
15265
fb167eb2 15266 if (! arm_elf_find_function (abfd, symbols, section, offset,
0367ecfb
NC		 15267 filename_ptr, functionname_ptr))
15268 return FALSE;
15269
15270 *line_ptr = 0;
b34976b6 15271 return TRUE;
252b5132
RH		 15272}
15273
4ab527b0
FF		 15274static bfd_boolean
15275elf32_arm_find_inliner_info (bfd * abfd,
15276 const char ** filename_ptr,
15277 const char ** functionname_ptr,
15278 unsigned int * line_ptr)
15279{
15280 bfd_boolean found;
15281 found = _bfd_dwarf2_find_inliner_info (abfd, filename_ptr,
15282 functionname_ptr, line_ptr,
15283 & elf_tdata (abfd)->dwarf2_find_line_info);
15284 return found;
15285}
15286
252b5132
RH		 15287/* Adjust a symbol defined by a dynamic object and referenced by a
15288 regular object. The current definition is in some section of the
15289 dynamic object, but we're not including those sections. We have to
15290 change the definition to something the rest of the link can
15291 understand. */
15292
b34976b6 15293static bfd_boolean
57e8b36a
NC		 15294elf32_arm_adjust_dynamic_symbol (struct bfd_link_info * info,
15295 struct elf_link_hash_entry * h)
252b5132
RH		 15296{
15297 bfd * dynobj;
5474d94f 15298 asection *s, *srel;
b7693d02 15299 struct elf32_arm_link_hash_entry * eh;
67687978 15300 struct elf32_arm_link_hash_table *globals;
252b5132 15301
67687978 15302 globals = elf32_arm_hash_table (info);
4dfe6ac6
NC		 15303 if (globals == NULL)
15304 return FALSE;
15305
252b5132
RH		 15306 dynobj = elf_hash_table (info)->dynobj;
15307
15308 /* Make sure we know what is going on here. */
15309 BFD_ASSERT (dynobj != NULL
f5385ebf 15310 && (h->needs_plt
34e77a92 15311 || h->type == STT_GNU_IFUNC
f6e332e6 15312 || h->u.weakdef != NULL
f5385ebf
AM		 15313 || (h->def_dynamic
15314 && h->ref_regular
15315 && !h->def_regular)));
252b5132 15316
b7693d02
DJ		 15317 eh = (struct elf32_arm_link_hash_entry *) h;
15318
252b5132
RH		 15319 /* If this is a function, put it in the procedure linkage table. We
15320 will fill in the contents of the procedure linkage table later,
15321 when we know the address of the .got section. */
34e77a92 15322 if (h->type == STT_FUNC || h->type == STT_GNU_IFUNC || h->needs_plt)
252b5132 15323 {
34e77a92
RS		 15324 /* Calls to STT_GNU_IFUNC symbols always use a PLT, even if the
15325 symbol binds locally. */
5e681ec4 15326 if (h->plt.refcount <= 0
34e77a92
RS		 15327 || (h->type != STT_GNU_IFUNC
15328 && (SYMBOL_CALLS_LOCAL (info, h)
15329 || (ELF_ST_VISIBILITY (h->other) != STV_DEFAULT
15330 && h->root.type == bfd_link_hash_undefweak))))
252b5132
RH		 15331 {
15332 /* This case can occur if we saw a PLT32 reloc in an input
5e681ec4
PB		 15333 file, but the symbol was never referred to by a dynamic
15334 object, or if all references were garbage collected. In
15335 such a case, we don't actually need to build a procedure
15336 linkage table, and we can just do a PC24 reloc instead. */
15337 h->plt.offset = (bfd_vma) -1;
34e77a92
RS		 15338 eh->plt.thumb_refcount = 0;
15339 eh->plt.maybe_thumb_refcount = 0;
15340 eh->plt.noncall_refcount = 0;
f5385ebf 15341 h->needs_plt = 0;
252b5132
RH		 15342 }
15343
b34976b6 15344 return TRUE;
252b5132 15345 }
5e681ec4 15346 else
b7693d02
DJ		 15347 {
15348 /* It's possible that we incorrectly decided a .plt reloc was
15349 needed for an R_ARM_PC24 or similar reloc to a non-function sym
15350 in check_relocs. We can't decide accurately between function
15351 and non-function syms in check-relocs; Objects loaded later in
15352 the link may change h->type. So fix it now. */
15353 h->plt.offset = (bfd_vma) -1;
34e77a92
RS		 15354 eh->plt.thumb_refcount = 0;
15355 eh->plt.maybe_thumb_refcount = 0;
15356 eh->plt.noncall_refcount = 0;
b7693d02 15357 }
252b5132
RH		 15358
15359 /* If this is a weak symbol, and there is a real definition, the
15360 processor independent code will have arranged for us to see the
15361 real definition first, and we can just use the same value. */
f6e332e6 15362 if (h->u.weakdef != NULL)
252b5132 15363 {
f6e332e6
AM		 15364 BFD_ASSERT (h->u.weakdef->root.type == bfd_link_hash_defined
15365 || h->u.weakdef->root.type == bfd_link_hash_defweak);
15366 h->root.u.def.section = h->u.weakdef->root.u.def.section;
15367 h->root.u.def.value = h->u.weakdef->root.u.def.value;
b34976b6 15368 return TRUE;
252b5132
RH		 15369 }
15370
ba93b8ac
DJ		 15371 /* If there are no non-GOT references, we do not need a copy
15372 relocation. */
15373 if (!h->non_got_ref)
15374 return TRUE;
15375
252b5132
RH		 15376 /* This is a reference to a symbol defined by a dynamic object which
15377 is not a function. */
15378
15379 /* If we are creating a shared library, we must presume that the
15380 only references to the symbol are via the global offset table.
15381 For such cases we need not do anything here; the relocations will
67687978
PB		 15382 be handled correctly by relocate_section. Relocatable executables
15383 can reference data in shared objects directly, so we don't need to
15384 do anything here. */
0e1862bb 15385 if (bfd_link_pic (info) || globals->root.is_relocatable_executable)
b34976b6 15386 return TRUE;
252b5132
RH		 15387
15388 /* We must allocate the symbol in our .dynbss section, which will
15389 become part of the .bss section of the executable. There will be
15390 an entry for this symbol in the .dynsym section. The dynamic
15391 object will contain position independent code, so all references
15392 from the dynamic object to this symbol will go through the global
15393 offset table. The dynamic linker will use the .dynsym entry to
15394 determine the address it must put in the global offset table, so
15395 both the dynamic object and the regular object will refer to the
15396 same memory location for the variable. */
5522f910
NC		 15397 /* If allowed, we must generate a R_ARM_COPY reloc to tell the dynamic
15398 linker to copy the initial value out of the dynamic object and into
15399 the runtime process image. We need to remember the offset into the
00a97672 15400 .rel(a).bss section we are going to use. */
5474d94f
AM		 15401 if ((h->root.u.def.section->flags & SEC_READONLY) != 0)
15402 {
15403 s = globals->root.sdynrelro;
15404 srel = globals->root.sreldynrelro;
15405 }
15406 else
15407 {
15408 s = globals->root.sdynbss;
15409 srel = globals->root.srelbss;
15410 }
5522f910
NC		 15411 if (info->nocopyreloc == 0
15412 && (h->root.u.def.section->flags & SEC_ALLOC) != 0
5522f910 15413 && h->size != 0)
252b5132 15414 {
47beaa6a 15415 elf32_arm_allocate_dynrelocs (info, srel, 1);
f5385ebf 15416 h->needs_copy = 1;
252b5132
RH		 15417 }
15418
6cabe1ea 15419 return _bfd_elf_adjust_dynamic_copy (info, h, s);
252b5132
RH		 15420}
15421
5e681ec4
PB		 15422/* Allocate space in .plt, .got and associated reloc sections for
15423 dynamic relocs. */
15424
15425static bfd_boolean
47beaa6a 15426allocate_dynrelocs_for_symbol (struct elf_link_hash_entry *h, void * inf)
5e681ec4
PB		 15427{
15428 struct bfd_link_info *info;
15429 struct elf32_arm_link_hash_table *htab;
15430 struct elf32_arm_link_hash_entry *eh;
0bdcacaf 15431 struct elf_dyn_relocs *p;
5e681ec4
PB		 15432
15433 if (h->root.type == bfd_link_hash_indirect)
15434 return TRUE;
15435
e6a6bb22
AM		 15436 eh = (struct elf32_arm_link_hash_entry *) h;
15437
5e681ec4
PB		 15438 info = (struct bfd_link_info *) inf;
15439 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 15440 if (htab == NULL)
15441 return FALSE;
5e681ec4 15442
34e77a92 15443 if ((htab->root.dynamic_sections_created || h->type == STT_GNU_IFUNC)
5e681ec4
PB		 15444 && h->plt.refcount > 0)
15445 {
15446 /* Make sure this symbol is output as a dynamic symbol.
15447 Undefined weak syms won't yet be marked as dynamic. */
15448 if (h->dynindx == -1
f5385ebf 15449 && !h->forced_local)
5e681ec4 15450 {
c152c796 15451 if (! bfd_elf_link_record_dynamic_symbol (info, h))
5e681ec4
PB		 15452 return FALSE;
15453 }
15454
34e77a92
RS		 15455 /* If the call in the PLT entry binds locally, the associated
15456 GOT entry should use an R_ARM_IRELATIVE relocation instead of
15457 the usual R_ARM_JUMP_SLOT. Put it in the .iplt section rather
15458 than the .plt section. */
15459 if (h->type == STT_GNU_IFUNC && SYMBOL_CALLS_LOCAL (info, h))
15460 {
15461 eh->is_iplt = 1;
15462 if (eh->plt.noncall_refcount == 0
15463 && SYMBOL_REFERENCES_LOCAL (info, h))
15464 /* All non-call references can be resolved directly.
15465 This means that they can (and in some cases, must)
15466 resolve directly to the run-time target, rather than
15467 to the PLT. That in turns means that any .got entry
15468 would be equal to the .igot.plt entry, so there's
15469 no point having both. */
15470 h->got.refcount = 0;
15471 }
15472
0e1862bb 15473 if (bfd_link_pic (info)
34e77a92 15474 || eh->is_iplt
7359ea65 15475 || WILL_CALL_FINISH_DYNAMIC_SYMBOL (1, 0, h))
5e681ec4 15476 {
34e77a92 15477 elf32_arm_allocate_plt_entry (info, eh->is_iplt, &h->plt, &eh->plt);
b7693d02 15478
5e681ec4
PB		 15479 /* If this symbol is not defined in a regular file, and we are
15480 not generating a shared library, then set the symbol to this
15481 location in the .plt. This is required to make function
15482 pointers compare as equal between the normal executable and
15483 the shared library. */
0e1862bb 15484 if (! bfd_link_pic (info)
f5385ebf 15485 && !h->def_regular)
5e681ec4 15486 {
34e77a92 15487 h->root.u.def.section = htab->root.splt;
5e681ec4 15488 h->root.u.def.value = h->plt.offset;
5e681ec4 15489
67d74e43
DJ		 15490 /* Make sure the function is not marked as Thumb, in case
15491 it is the target of an ABS32 relocation, which will
15492 point to the PLT entry. */
39d911fc 15493 ARM_SET_SYM_BRANCH_TYPE (h->target_internal, ST_BRANCH_TO_ARM);
67d74e43 15494 }
022f8312 15495
00a97672
RS		 15496 /* VxWorks executables have a second set of relocations for
15497 each PLT entry. They go in a separate relocation section,
15498 which is processed by the kernel loader. */
0e1862bb 15499 if (htab->vxworks_p && !bfd_link_pic (info))
00a97672
RS		 15500 {
15501 /* There is a relocation for the initial PLT entry:
15502 an R_ARM_32 relocation for _GLOBAL_OFFSET_TABLE_. */
15503 if (h->plt.offset == htab->plt_header_size)
47beaa6a 15504 elf32_arm_allocate_dynrelocs (info, htab->srelplt2, 1);
00a97672
RS		 15505
15506 /* There are two extra relocations for each subsequent
15507 PLT entry: an R_ARM_32 relocation for the GOT entry,
15508 and an R_ARM_32 relocation for the PLT entry. */
47beaa6a 15509 elf32_arm_allocate_dynrelocs (info, htab->srelplt2, 2);
00a97672 15510 }
5e681ec4
PB		 15511 }
15512 else
15513 {
15514 h->plt.offset = (bfd_vma) -1;
f5385ebf 15515 h->needs_plt = 0;
5e681ec4
PB		 15516 }
15517 }
15518 else
15519 {
15520 h->plt.offset = (bfd_vma) -1;
f5385ebf 15521 h->needs_plt = 0;
5e681ec4
PB		 15522 }
15523
0855e32b
NS		 15524 eh = (struct elf32_arm_link_hash_entry *) h;
15525 eh->tlsdesc_got = (bfd_vma) -1;
15526
5e681ec4
PB		 15527 if (h->got.refcount > 0)
15528 {
15529 asection *s;
15530 bfd_boolean dyn;
ba93b8ac
DJ		 15531 int tls_type = elf32_arm_hash_entry (h)->tls_type;
15532 int indx;
5e681ec4
PB		 15533
15534 /* Make sure this symbol is output as a dynamic symbol.
15535 Undefined weak syms won't yet be marked as dynamic. */
15536 if (h->dynindx == -1
f5385ebf 15537 && !h->forced_local)
5e681ec4 15538 {
c152c796 15539 if (! bfd_elf_link_record_dynamic_symbol (info, h))
5e681ec4
PB		 15540 return FALSE;
15541 }
15542
e5a52504
MM		 15543 if (!htab->symbian_p)
15544 {
362d30a1 15545 s = htab->root.sgot;
e5a52504 15546 h->got.offset = s->size;
ba93b8ac
DJ		 15547
15548 if (tls_type == GOT_UNKNOWN)
15549 abort ();
15550
15551 if (tls_type == GOT_NORMAL)
15552 /* Non-TLS symbols need one GOT slot. */
15553 s->size += 4;
15554 else
15555 {
99059e56
RM		 15556 if (tls_type & GOT_TLS_GDESC)
15557 {
0855e32b 15558 /* R_ARM_TLS_DESC needs 2 GOT slots. */
99059e56 15559 eh->tlsdesc_got
0855e32b
NS		 15560 = (htab->root.sgotplt->size
15561 - elf32_arm_compute_jump_table_size (htab));
99059e56
RM		 15562 htab->root.sgotplt->size += 8;
15563 h->got.offset = (bfd_vma) -2;
34e77a92 15564 /* plt.got_offset needs to know there's a TLS_DESC
0855e32b 15565 reloc in the middle of .got.plt. */
99059e56
RM		 15566 htab->num_tls_desc++;
15567 }
0855e32b 15568
ba93b8ac 15569 if (tls_type & GOT_TLS_GD)
0855e32b
NS		 15570 {
15571 /* R_ARM_TLS_GD32 needs 2 consecutive GOT slots. If
15572 the symbol is both GD and GDESC, got.offset may
15573 have been overwritten. */
15574 h->got.offset = s->size;
15575 s->size += 8;
15576 }
15577
ba93b8ac
DJ		 15578 if (tls_type & GOT_TLS_IE)
15579 /* R_ARM_TLS_IE32 needs one GOT slot. */
15580 s->size += 4;
15581 }
15582
e5a52504 15583 dyn = htab->root.dynamic_sections_created;
ba93b8ac
DJ		 15584
15585 indx = 0;
0e1862bb
L		 15586 if (WILL_CALL_FINISH_DYNAMIC_SYMBOL (dyn,
15587 bfd_link_pic (info),
15588 h)
15589 && (!bfd_link_pic (info)
ba93b8ac
DJ		 15590 || !SYMBOL_REFERENCES_LOCAL (info, h)))
15591 indx = h->dynindx;
15592
15593 if (tls_type != GOT_NORMAL
0e1862bb 15594 && (bfd_link_pic (info) || indx != 0)
ba93b8ac
DJ		 15595 && (ELF_ST_VISIBILITY (h->other) == STV_DEFAULT
15596 || h->root.type != bfd_link_hash_undefweak))
15597 {
15598 if (tls_type & GOT_TLS_IE)
47beaa6a 15599 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
ba93b8ac
DJ		 15600
15601 if (tls_type & GOT_TLS_GD)
47beaa6a 15602 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
ba93b8ac 15603
b38cadfb 15604 if (tls_type & GOT_TLS_GDESC)
0855e32b 15605 {
47beaa6a 15606 elf32_arm_allocate_dynrelocs (info, htab->root.srelplt, 1);
0855e32b
NS		 15607 /* GDESC needs a trampoline to jump to. */
15608 htab->tls_trampoline = -1;
15609 }
15610
15611 /* Only GD needs it. GDESC just emits one relocation per
15612 2 entries. */
b38cadfb 15613 if ((tls_type & GOT_TLS_GD) && indx != 0)
47beaa6a 15614 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
ba93b8ac 15615 }
6f820c85 15616 else if (indx != -1 && !SYMBOL_REFERENCES_LOCAL (info, h))
b436d854
RS		 15617 {
15618 if (htab->root.dynamic_sections_created)
15619 /* Reserve room for the GOT entry's R_ARM_GLOB_DAT relocation. */
15620 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
15621 }
34e77a92
RS		 15622 else if (h->type == STT_GNU_IFUNC
15623 && eh->plt.noncall_refcount == 0)
15624 /* No non-call references resolve the STT_GNU_IFUNC's PLT entry;
15625 they all resolve dynamically instead. Reserve room for the
15626 GOT entry's R_ARM_IRELATIVE relocation. */
15627 elf32_arm_allocate_irelocs (info, htab->root.srelgot, 1);
0e1862bb
L		 15628 else if (bfd_link_pic (info)
15629 && (ELF_ST_VISIBILITY (h->other) == STV_DEFAULT
15630 || h->root.type != bfd_link_hash_undefweak))
b436d854 15631 /* Reserve room for the GOT entry's R_ARM_RELATIVE relocation. */
47beaa6a 15632 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
e5a52504 15633 }
5e681ec4
PB		 15634 }
15635 else
15636 h->got.offset = (bfd_vma) -1;
15637
a4fd1a8e
PB		 15638 /* Allocate stubs for exported Thumb functions on v4t. */
15639 if (!htab->use_blx && h->dynindx != -1
0eaedd0e 15640 && h->def_regular
39d911fc 15641 && ARM_GET_SYM_BRANCH_TYPE (h->target_internal) == ST_BRANCH_TO_THUMB
a4fd1a8e
PB		 15642 && ELF_ST_VISIBILITY (h->other) == STV_DEFAULT)
15643 {
15644 struct elf_link_hash_entry * th;
15645 struct bfd_link_hash_entry * bh;
15646 struct elf_link_hash_entry * myh;
15647 char name[1024];
15648 asection *s;
15649 bh = NULL;
15650 /* Create a new symbol to regist the real location of the function. */
15651 s = h->root.u.def.section;
906e58ca 15652 sprintf (name, "__real_%s", h->root.root.string);
a4fd1a8e
PB		 15653 _bfd_generic_link_add_one_symbol (info, s->owner,
15654 name, BSF_GLOBAL, s,
15655 h->root.u.def.value,
15656 NULL, TRUE, FALSE, &bh);
15657
15658 myh = (struct elf_link_hash_entry *) bh;
35fc36a8 15659 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
a4fd1a8e 15660 myh->forced_local = 1;
39d911fc 15661 ARM_SET_SYM_BRANCH_TYPE (myh->target_internal, ST_BRANCH_TO_THUMB);
a4fd1a8e
PB		 15662 eh->export_glue = myh;
15663 th = record_arm_to_thumb_glue (info, h);
15664 /* Point the symbol at the stub. */
15665 h->type = ELF_ST_INFO (ELF_ST_BIND (h->type), STT_FUNC);
39d911fc 15666 ARM_SET_SYM_BRANCH_TYPE (h->target_internal, ST_BRANCH_TO_ARM);
a4fd1a8e
PB		 15667 h->root.u.def.section = th->root.u.def.section;
15668 h->root.u.def.value = th->root.u.def.value & ~1;
15669 }
15670
0bdcacaf 15671 if (eh->dyn_relocs == NULL)
5e681ec4
PB		 15672 return TRUE;
15673
15674 /* In the shared -Bsymbolic case, discard space allocated for
15675 dynamic pc-relative relocs against symbols which turn out to be
15676 defined in regular objects. For the normal shared case, discard
15677 space for pc-relative relocs that have become local due to symbol
15678 visibility changes. */
15679
0e1862bb 15680 if (bfd_link_pic (info) || htab->root.is_relocatable_executable)
5e681ec4 15681 {
469a3493
RM		 15682 /* Relocs that use pc_count are PC-relative forms, which will appear
15683 on something like ".long foo - ." or "movw REG, foo - .". We want
15684 calls to protected symbols to resolve directly to the function
15685 rather than going via the plt. If people want function pointer
15686 comparisons to work as expected then they should avoid writing
15687 assembly like ".long foo - .". */
ba93b8ac
DJ		 15688 if (SYMBOL_CALLS_LOCAL (info, h))
15689 {
0bdcacaf 15690 struct elf_dyn_relocs **pp;
ba93b8ac 15691
0bdcacaf 15692 for (pp = &eh->dyn_relocs; (p = *pp) != NULL; )
ba93b8ac
DJ		 15693 {
15694 p->count -= p->pc_count;
15695 p->pc_count = 0;
15696 if (p->count == 0)
15697 *pp = p->next;
15698 else
15699 pp = &p->next;
15700 }
15701 }
15702
4dfe6ac6 15703 if (htab->vxworks_p)
3348747a 15704 {
0bdcacaf 15705 struct elf_dyn_relocs **pp;
3348747a 15706
0bdcacaf 15707 for (pp = &eh->dyn_relocs; (p = *pp) != NULL; )
3348747a 15708 {
0bdcacaf 15709 if (strcmp (p->sec->output_section->name, ".tls_vars") == 0)
3348747a
NS		 15710 *pp = p->next;
15711 else
15712 pp = &p->next;
15713 }
15714 }
15715
ba93b8ac 15716 /* Also discard relocs on undefined weak syms with non-default
99059e56 15717 visibility. */
0bdcacaf 15718 if (eh->dyn_relocs != NULL
5e681ec4 15719 && h->root.type == bfd_link_hash_undefweak)
22d606e9
AM		 15720 {
15721 if (ELF_ST_VISIBILITY (h->other) != STV_DEFAULT)
0bdcacaf 15722 eh->dyn_relocs = NULL;
22d606e9
AM		 15723
15724 /* Make sure undefined weak symbols are output as a dynamic
15725 symbol in PIEs. */
15726 else if (h->dynindx == -1
15727 && !h->forced_local)
15728 {
15729 if (! bfd_elf_link_record_dynamic_symbol (info, h))
15730 return FALSE;
15731 }
15732 }
15733
67687978
PB		 15734 else if (htab->root.is_relocatable_executable && h->dynindx == -1
15735 && h->root.type == bfd_link_hash_new)
15736 {
15737 /* Output absolute symbols so that we can create relocations
15738 against them. For normal symbols we output a relocation
15739 against the section that contains them. */
15740 if (! bfd_elf_link_record_dynamic_symbol (info, h))
15741 return FALSE;
15742 }
15743
5e681ec4
PB		 15744 }
15745 else
15746 {
15747 /* For the non-shared case, discard space for relocs against
15748 symbols which turn out to need copy relocs or are not
15749 dynamic. */
15750
f5385ebf
AM		 15751 if (!h->non_got_ref
15752 && ((h->def_dynamic
15753 && !h->def_regular)
5e681ec4
PB		 15754 || (htab->root.dynamic_sections_created
15755 && (h->root.type == bfd_link_hash_undefweak
15756 || h->root.type == bfd_link_hash_undefined))))
15757 {
15758 /* Make sure this symbol is output as a dynamic symbol.
15759 Undefined weak syms won't yet be marked as dynamic. */
15760 if (h->dynindx == -1
f5385ebf 15761 && !h->forced_local)
5e681ec4 15762 {
c152c796 15763 if (! bfd_elf_link_record_dynamic_symbol (info, h))
5e681ec4
PB		 15764 return FALSE;
15765 }
15766
15767 /* If that succeeded, we know we'll be keeping all the
15768 relocs. */
15769 if (h->dynindx != -1)
15770 goto keep;
15771 }
15772
0bdcacaf 15773 eh->dyn_relocs = NULL;
5e681ec4
PB		 15774
15775 keep: ;
15776 }
15777
15778 /* Finally, allocate space. */
0bdcacaf 15779 for (p = eh->dyn_relocs; p != NULL; p = p->next)
5e681ec4 15780 {
0bdcacaf 15781 asection *sreloc = elf_section_data (p->sec)->sreloc;
34e77a92
RS		 15782 if (h->type == STT_GNU_IFUNC
15783 && eh->plt.noncall_refcount == 0
15784 && SYMBOL_REFERENCES_LOCAL (info, h))
15785 elf32_arm_allocate_irelocs (info, sreloc, p->count);
15786 else
15787 elf32_arm_allocate_dynrelocs (info, sreloc, p->count);
5e681ec4
PB		 15788 }
15789
15790 return TRUE;
15791}
15792
08d1f311
DJ		 15793/* Find any dynamic relocs that apply to read-only sections. */
15794
15795static bfd_boolean
8029a119 15796elf32_arm_readonly_dynrelocs (struct elf_link_hash_entry * h, void * inf)
08d1f311 15797{
8029a119 15798 struct elf32_arm_link_hash_entry * eh;
0bdcacaf 15799 struct elf_dyn_relocs * p;
08d1f311 15800
08d1f311 15801 eh = (struct elf32_arm_link_hash_entry *) h;
0bdcacaf 15802 for (p = eh->dyn_relocs; p != NULL; p = p->next)
08d1f311 15803 {
0bdcacaf 15804 asection *s = p->sec;
08d1f311
DJ		 15805
15806 if (s != NULL && (s->flags & SEC_READONLY) != 0)
15807 {
15808 struct bfd_link_info *info = (struct bfd_link_info *) inf;
15809
15810 info->flags |= DF_TEXTREL;
15811
15812 /* Not an error, just cut short the traversal. */
15813 return FALSE;
15814 }
15815 }
15816 return TRUE;
15817}
15818
d504ffc8
DJ		 15819void
15820bfd_elf32_arm_set_byteswap_code (struct bfd_link_info *info,
15821 int byteswap_code)
15822{
15823 struct elf32_arm_link_hash_table *globals;
15824
15825 globals = elf32_arm_hash_table (info);
4dfe6ac6
NC		 15826 if (globals == NULL)
15827 return;
15828
d504ffc8
DJ		 15829 globals->byteswap_code = byteswap_code;
15830}
15831
252b5132
RH		 15832/* Set the sizes of the dynamic sections. */
15833
b34976b6 15834static bfd_boolean
57e8b36a
NC		 15835elf32_arm_size_dynamic_sections (bfd * output_bfd ATTRIBUTE_UNUSED,
15836 struct bfd_link_info * info)
252b5132
RH		 15837{
15838 bfd * dynobj;
15839 asection * s;
b34976b6
AM		 15840 bfd_boolean plt;
15841 bfd_boolean relocs;
5e681ec4
PB		 15842 bfd *ibfd;
15843 struct elf32_arm_link_hash_table *htab;
252b5132 15844
5e681ec4 15845 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 15846 if (htab == NULL)
15847 return FALSE;
15848
252b5132
RH		 15849 dynobj = elf_hash_table (info)->dynobj;
15850 BFD_ASSERT (dynobj != NULL);
39b41c9c 15851 check_use_blx (htab);
252b5132
RH		 15852
15853 if (elf_hash_table (info)->dynamic_sections_created)
15854 {
15855 /* Set the contents of the .interp section to the interpreter. */
9b8b325a 15856 if (bfd_link_executable (info) && !info->nointerp)
252b5132 15857 {
3d4d4302 15858 s = bfd_get_linker_section (dynobj, ".interp");
252b5132 15859 BFD_ASSERT (s != NULL);
eea6121a 15860 s->size = sizeof ELF_DYNAMIC_INTERPRETER;
252b5132
RH		 15861 s->contents = (unsigned char *) ELF_DYNAMIC_INTERPRETER;
15862 }
15863 }
5e681ec4
PB		 15864
15865 /* Set up .got offsets for local syms, and space for local dynamic
15866 relocs. */
c72f2fb2 15867 for (ibfd = info->input_bfds; ibfd != NULL; ibfd = ibfd->link.next)
252b5132 15868 {
5e681ec4
PB		 15869 bfd_signed_vma *local_got;
15870 bfd_signed_vma *end_local_got;
34e77a92 15871 struct arm_local_iplt_info **local_iplt_ptr, *local_iplt;
5e681ec4 15872 char *local_tls_type;
0855e32b 15873 bfd_vma *local_tlsdesc_gotent;
5e681ec4
PB		 15874 bfd_size_type locsymcount;
15875 Elf_Internal_Shdr *symtab_hdr;
15876 asection *srel;
4dfe6ac6 15877 bfd_boolean is_vxworks = htab->vxworks_p;
34e77a92 15878 unsigned int symndx;
5e681ec4 15879
0ffa91dd 15880 if (! is_arm_elf (ibfd))
5e681ec4
PB		 15881 continue;
15882
15883 for (s = ibfd->sections; s != NULL; s = s->next)
15884 {
0bdcacaf 15885 struct elf_dyn_relocs *p;
5e681ec4 15886
0bdcacaf 15887 for (p = (struct elf_dyn_relocs *)
99059e56 15888 elf_section_data (s)->local_dynrel; p != NULL; p = p->next)
5e681ec4 15889 {
0bdcacaf
RS		 15890 if (!bfd_is_abs_section (p->sec)
15891 && bfd_is_abs_section (p->sec->output_section))
5e681ec4
PB		 15892 {
15893 /* Input section has been discarded, either because
15894 it is a copy of a linkonce section or due to
15895 linker script /DISCARD/, so we'll be discarding
15896 the relocs too. */
15897 }
3348747a 15898 else if (is_vxworks
0bdcacaf 15899 && strcmp (p->sec->output_section->name,
3348747a
NS		 15900 ".tls_vars") == 0)
15901 {
15902 /* Relocations in vxworks .tls_vars sections are
15903 handled specially by the loader. */
15904 }
5e681ec4
PB		 15905 else if (p->count != 0)
15906 {
0bdcacaf 15907 srel = elf_section_data (p->sec)->sreloc;
47beaa6a 15908 elf32_arm_allocate_dynrelocs (info, srel, p->count);
0bdcacaf 15909 if ((p->sec->output_section->flags & SEC_READONLY) != 0)
5e681ec4
PB		 15910 info->flags |= DF_TEXTREL;
15911 }
15912 }
15913 }
15914
15915 local_got = elf_local_got_refcounts (ibfd);
15916 if (!local_got)
15917 continue;
15918
0ffa91dd 15919 symtab_hdr = & elf_symtab_hdr (ibfd);
5e681ec4
PB		 15920 locsymcount = symtab_hdr->sh_info;
15921 end_local_got = local_got + locsymcount;
34e77a92 15922 local_iplt_ptr = elf32_arm_local_iplt (ibfd);
ba93b8ac 15923 local_tls_type = elf32_arm_local_got_tls_type (ibfd);
0855e32b 15924 local_tlsdesc_gotent = elf32_arm_local_tlsdesc_gotent (ibfd);
34e77a92 15925 symndx = 0;
362d30a1
RS		 15926 s = htab->root.sgot;
15927 srel = htab->root.srelgot;
0855e32b 15928 for (; local_got < end_local_got;
34e77a92
RS		 15929 ++local_got, ++local_iplt_ptr, ++local_tls_type,
15930 ++local_tlsdesc_gotent, ++symndx)
5e681ec4 15931 {
0855e32b 15932 *local_tlsdesc_gotent = (bfd_vma) -1;
34e77a92
RS		 15933 local_iplt = *local_iplt_ptr;
15934 if (local_iplt != NULL)
15935 {
15936 struct elf_dyn_relocs *p;
15937
15938 if (local_iplt->root.refcount > 0)
15939 {
15940 elf32_arm_allocate_plt_entry (info, TRUE,
15941 &local_iplt->root,
15942 &local_iplt->arm);
15943 if (local_iplt->arm.noncall_refcount == 0)
15944 /* All references to the PLT are calls, so all
15945 non-call references can resolve directly to the
15946 run-time target. This means that the .got entry
15947 would be the same as the .igot.plt entry, so there's
15948 no point creating both. */
15949 *local_got = 0;
15950 }
15951 else
15952 {
15953 BFD_ASSERT (local_iplt->arm.noncall_refcount == 0);
15954 local_iplt->root.offset = (bfd_vma) -1;
15955 }
15956
15957 for (p = local_iplt->dyn_relocs; p != NULL; p = p->next)
15958 {
15959 asection *psrel;
15960
15961 psrel = elf_section_data (p->sec)->sreloc;
15962 if (local_iplt->arm.noncall_refcount == 0)
15963 elf32_arm_allocate_irelocs (info, psrel, p->count);
15964 else
15965 elf32_arm_allocate_dynrelocs (info, psrel, p->count);
15966 }
15967 }
5e681ec4
PB		 15968 if (*local_got > 0)
15969 {
34e77a92
RS		 15970 Elf_Internal_Sym *isym;
15971
eea6121a 15972 *local_got = s->size;
ba93b8ac
DJ		 15973 if (*local_tls_type & GOT_TLS_GD)
15974 /* TLS_GD relocs need an 8-byte structure in the GOT. */
15975 s->size += 8;
0855e32b
NS		 15976 if (*local_tls_type & GOT_TLS_GDESC)
15977 {
15978 *local_tlsdesc_gotent = htab->root.sgotplt->size
15979 - elf32_arm_compute_jump_table_size (htab);
15980 htab->root.sgotplt->size += 8;
15981 *local_got = (bfd_vma) -2;
34e77a92 15982 /* plt.got_offset needs to know there's a TLS_DESC
0855e32b 15983 reloc in the middle of .got.plt. */
99059e56 15984 htab->num_tls_desc++;
0855e32b 15985 }
ba93b8ac
DJ		 15986 if (*local_tls_type & GOT_TLS_IE)
15987 s->size += 4;
ba93b8ac 15988
0855e32b
NS		 15989 if (*local_tls_type & GOT_NORMAL)
15990 {
15991 /* If the symbol is both GD and GDESC, *local_got
15992 may have been overwritten. */
15993 *local_got = s->size;
15994 s->size += 4;
15995 }
15996
34e77a92
RS		 15997 isym = bfd_sym_from_r_symndx (&htab->sym_cache, ibfd, symndx);
15998 if (isym == NULL)
15999 return FALSE;
16000
16001 /* If all references to an STT_GNU_IFUNC PLT are calls,
16002 then all non-call references, including this GOT entry,
16003 resolve directly to the run-time target. */
16004 if (ELF32_ST_TYPE (isym->st_info) == STT_GNU_IFUNC
16005 && (local_iplt == NULL
16006 || local_iplt->arm.noncall_refcount == 0))
16007 elf32_arm_allocate_irelocs (info, srel, 1);
0e1862bb 16008 else if (bfd_link_pic (info) || output_bfd->flags & DYNAMIC)
0855e32b 16009 {
0e1862bb 16010 if ((bfd_link_pic (info) && !(*local_tls_type & GOT_TLS_GDESC))
3064e1ff
JB		 16011 || *local_tls_type & GOT_TLS_GD)
16012 elf32_arm_allocate_dynrelocs (info, srel, 1);
99059e56 16013
0e1862bb 16014 if (bfd_link_pic (info) && *local_tls_type & GOT_TLS_GDESC)
3064e1ff
JB		 16015 {
16016 elf32_arm_allocate_dynrelocs (info,
16017 htab->root.srelplt, 1);
16018 htab->tls_trampoline = -1;
16019 }
0855e32b 16020 }
5e681ec4
PB		 16021 }
16022 else
16023 *local_got = (bfd_vma) -1;
16024 }
252b5132
RH		 16025 }
16026
ba93b8ac
DJ		 16027 if (htab->tls_ldm_got.refcount > 0)
16028 {
16029 /* Allocate two GOT entries and one dynamic relocation (if necessary)
16030 for R_ARM_TLS_LDM32 relocations. */
362d30a1
RS		 16031 htab->tls_ldm_got.offset = htab->root.sgot->size;
16032 htab->root.sgot->size += 8;
0e1862bb 16033 if (bfd_link_pic (info))
47beaa6a 16034 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
ba93b8ac
DJ		 16035 }
16036 else
16037 htab->tls_ldm_got.offset = -1;
16038
5e681ec4
PB		 16039 /* Allocate global sym .plt and .got entries, and space for global
16040 sym dynamic relocs. */
47beaa6a 16041 elf_link_hash_traverse (& htab->root, allocate_dynrelocs_for_symbol, info);
252b5132 16042
d504ffc8 16043 /* Here we rummage through the found bfds to collect glue information. */
c72f2fb2 16044 for (ibfd = info->input_bfds; ibfd != NULL; ibfd = ibfd->link.next)
c7b8f16e 16045 {
0ffa91dd 16046 if (! is_arm_elf (ibfd))
e44a2c9c
AM		 16047 continue;
16048
c7b8f16e
JB		 16049 /* Initialise mapping tables for code/data. */
16050 bfd_elf32_arm_init_maps (ibfd);
906e58ca 16051
c7b8f16e 16052 if (!bfd_elf32_arm_process_before_allocation (ibfd, info)
a504d23a
LA		 16053 || !bfd_elf32_arm_vfp11_erratum_scan (ibfd, info)
16054 || !bfd_elf32_arm_stm32l4xx_erratum_scan (ibfd, info))
dae82561 16055 _bfd_error_handler (_("Errors encountered processing file %B"), ibfd);
c7b8f16e 16056 }
d504ffc8 16057
3e6b1042
DJ		 16058 /* Allocate space for the glue sections now that we've sized them. */
16059 bfd_elf32_arm_allocate_interworking_sections (info);
16060
0855e32b
NS		 16061 /* For every jump slot reserved in the sgotplt, reloc_count is
16062 incremented. However, when we reserve space for TLS descriptors,
16063 it's not incremented, so in order to compute the space reserved
16064 for them, it suffices to multiply the reloc count by the jump
16065 slot size. */
16066 if (htab->root.srelplt)
16067 htab->sgotplt_jump_table_size = elf32_arm_compute_jump_table_size(htab);
16068
16069 if (htab->tls_trampoline)
16070 {
16071 if (htab->root.splt->size == 0)
16072 htab->root.splt->size += htab->plt_header_size;
b38cadfb 16073
0855e32b
NS		 16074 htab->tls_trampoline = htab->root.splt->size;
16075 htab->root.splt->size += htab->plt_entry_size;
b38cadfb 16076
0855e32b 16077 /* If we're not using lazy TLS relocations, don't generate the
99059e56 16078 PLT and GOT entries they require. */
0855e32b
NS		 16079 if (!(info->flags & DF_BIND_NOW))
16080 {
16081 htab->dt_tlsdesc_got = htab->root.sgot->size;
16082 htab->root.sgot->size += 4;
16083
16084 htab->dt_tlsdesc_plt = htab->root.splt->size;
16085 htab->root.splt->size += 4 * ARRAY_SIZE (dl_tlsdesc_lazy_trampoline);
16086 }
16087 }
16088
252b5132
RH		 16089 /* The check_relocs and adjust_dynamic_symbol entry points have
16090 determined the sizes of the various dynamic sections. Allocate
16091 memory for them. */
b34976b6
AM		 16092 plt = FALSE;
16093 relocs = FALSE;
252b5132
RH		 16094 for (s = dynobj->sections; s != NULL; s = s->next)
16095 {
16096 const char * name;
252b5132
RH		 16097
16098 if ((s->flags & SEC_LINKER_CREATED) == 0)
16099 continue;
16100
16101 /* It's OK to base decisions on the section name, because none
16102 of the dynobj section names depend upon the input files. */
16103 name = bfd_get_section_name (dynobj, s);
16104
34e77a92 16105 if (s == htab->root.splt)
252b5132 16106 {
c456f082
AM		 16107 /* Remember whether there is a PLT. */
16108 plt = s->size != 0;
252b5132 16109 }
0112cd26 16110 else if (CONST_STRNEQ (name, ".rel"))
252b5132 16111 {
c456f082 16112 if (s->size != 0)
252b5132 16113 {
252b5132 16114 /* Remember whether there are any reloc sections other
00a97672 16115 than .rel(a).plt and .rela.plt.unloaded. */
362d30a1 16116 if (s != htab->root.srelplt && s != htab->srelplt2)
b34976b6 16117 relocs = TRUE;
252b5132
RH		 16118
16119 /* We use the reloc_count field as a counter if we need
16120 to copy relocs into the output file. */
16121 s->reloc_count = 0;
16122 }
16123 }
34e77a92
RS		 16124 else if (s != htab->root.sgot
16125 && s != htab->root.sgotplt
16126 && s != htab->root.iplt
16127 && s != htab->root.igotplt
5474d94f
AM		 16128 && s != htab->root.sdynbss
16129 && s != htab->root.sdynrelro)
252b5132
RH		 16130 {
16131 /* It's not one of our sections, so don't allocate space. */
16132 continue;
16133 }
16134
c456f082 16135 if (s->size == 0)
252b5132 16136 {
c456f082 16137 /* If we don't need this section, strip it from the
00a97672
RS		 16138 output file. This is mostly to handle .rel(a).bss and
16139 .rel(a).plt. We must create both sections in
c456f082
AM		 16140 create_dynamic_sections, because they must be created
16141 before the linker maps input sections to output
16142 sections. The linker does that before
16143 adjust_dynamic_symbol is called, and it is that
16144 function which decides whether anything needs to go
16145 into these sections. */
8423293d 16146 s->flags |= SEC_EXCLUDE;
252b5132
RH		 16147 continue;
16148 }
16149
c456f082
AM		 16150 if ((s->flags & SEC_HAS_CONTENTS) == 0)
16151 continue;
16152
252b5132 16153 /* Allocate memory for the section contents. */
21d799b5 16154 s->contents = (unsigned char *) bfd_zalloc (dynobj, s->size);
c456f082 16155 if (s->contents == NULL)
b34976b6 16156 return FALSE;
252b5132
RH		 16157 }
16158
16159 if (elf_hash_table (info)->dynamic_sections_created)
16160 {
16161 /* Add some entries to the .dynamic section. We fill in the
16162 values later, in elf32_arm_finish_dynamic_sections, but we
16163 must add the entries now so that we get the correct size for
16164 the .dynamic section. The DT_DEBUG entry is filled in by the
16165 dynamic linker and used by the debugger. */
dc810e39 16166#define add_dynamic_entry(TAG, VAL) \
5a580b3a 16167 _bfd_elf_add_dynamic_entry (info, TAG, VAL)
dc810e39 16168
0e1862bb 16169 if (bfd_link_executable (info))
252b5132 16170 {
dc810e39 16171 if (!add_dynamic_entry (DT_DEBUG, 0))
b34976b6 16172 return FALSE;
252b5132
RH		 16173 }
16174
16175 if (plt)
16176 {
dc810e39
AM		 16177 if ( !add_dynamic_entry (DT_PLTGOT, 0)
16178 || !add_dynamic_entry (DT_PLTRELSZ, 0)
00a97672
RS		 16179 || !add_dynamic_entry (DT_PLTREL,
16180 htab->use_rel ? DT_REL : DT_RELA)
dc810e39 16181 || !add_dynamic_entry (DT_JMPREL, 0))
b34976b6 16182 return FALSE;
0855e32b 16183
5025eb7c
AO		 16184 if (htab->dt_tlsdesc_plt
16185 && (!add_dynamic_entry (DT_TLSDESC_PLT,0)
16186 || !add_dynamic_entry (DT_TLSDESC_GOT,0)))
b38cadfb 16187 return FALSE;
252b5132
RH		 16188 }
16189
16190 if (relocs)
16191 {
00a97672
RS		 16192 if (htab->use_rel)
16193 {
16194 if (!add_dynamic_entry (DT_REL, 0)
16195 || !add_dynamic_entry (DT_RELSZ, 0)
16196 || !add_dynamic_entry (DT_RELENT, RELOC_SIZE (htab)))
16197 return FALSE;
16198 }
16199 else
16200 {
16201 if (!add_dynamic_entry (DT_RELA, 0)
16202 || !add_dynamic_entry (DT_RELASZ, 0)
16203 || !add_dynamic_entry (DT_RELAENT, RELOC_SIZE (htab)))
16204 return FALSE;
16205 }
252b5132
RH		 16206 }
16207
08d1f311
DJ		 16208 /* If any dynamic relocs apply to a read-only section,
16209 then we need a DT_TEXTREL entry. */
16210 if ((info->flags & DF_TEXTREL) == 0)
8029a119
NC		 16211 elf_link_hash_traverse (& htab->root, elf32_arm_readonly_dynrelocs,
16212 info);
08d1f311 16213
99e4ae17 16214 if ((info->flags & DF_TEXTREL) != 0)
252b5132 16215 {
dc810e39 16216 if (!add_dynamic_entry (DT_TEXTREL, 0))
b34976b6 16217 return FALSE;
252b5132 16218 }
7a2b07ff
NS		 16219 if (htab->vxworks_p
16220 && !elf_vxworks_add_dynamic_entries (output_bfd, info))
16221 return FALSE;
252b5132 16222 }
8532796c 16223#undef add_dynamic_entry
252b5132 16224
b34976b6 16225 return TRUE;
252b5132
RH		 16226}
16227
0855e32b
NS		 16228/* Size sections even though they're not dynamic. We use it to setup
16229 _TLS_MODULE_BASE_, if needed. */
16230
16231static bfd_boolean
16232elf32_arm_always_size_sections (bfd *output_bfd,
99059e56 16233 struct bfd_link_info *info)
0855e32b
NS		 16234{
16235 asection *tls_sec;
16236
0e1862bb 16237 if (bfd_link_relocatable (info))
0855e32b
NS		 16238 return TRUE;
16239
16240 tls_sec = elf_hash_table (info)->tls_sec;
16241
16242 if (tls_sec)
16243 {
16244 struct elf_link_hash_entry *tlsbase;
16245
16246 tlsbase = elf_link_hash_lookup
16247 (elf_hash_table (info), "_TLS_MODULE_BASE_", TRUE, TRUE, FALSE);
16248
16249 if (tlsbase)
99059e56
RM		 16250 {
16251 struct bfd_link_hash_entry *bh = NULL;
0855e32b 16252 const struct elf_backend_data *bed
99059e56 16253 = get_elf_backend_data (output_bfd);
0855e32b 16254
99059e56 16255 if (!(_bfd_generic_link_add_one_symbol
0855e32b
NS		 16256 (info, output_bfd, "_TLS_MODULE_BASE_", BSF_LOCAL,
16257 tls_sec, 0, NULL, FALSE,
16258 bed->collect, &bh)))
16259 return FALSE;
b38cadfb 16260
99059e56
RM		 16261 tlsbase->type = STT_TLS;
16262 tlsbase = (struct elf_link_hash_entry *)bh;
16263 tlsbase->def_regular = 1;
16264 tlsbase->other = STV_HIDDEN;
16265 (*bed->elf_backend_hide_symbol) (info, tlsbase, TRUE);
0855e32b
NS		 16266 }
16267 }
16268 return TRUE;
16269}
16270
252b5132
RH		 16271/* Finish up dynamic symbol handling. We set the contents of various
16272 dynamic sections here. */
16273
b34976b6 16274static bfd_boolean
906e58ca
NC		 16275elf32_arm_finish_dynamic_symbol (bfd * output_bfd,
16276 struct bfd_link_info * info,
16277 struct elf_link_hash_entry * h,
16278 Elf_Internal_Sym * sym)
252b5132 16279{
e5a52504 16280 struct elf32_arm_link_hash_table *htab;
b7693d02 16281 struct elf32_arm_link_hash_entry *eh;
252b5132 16282
e5a52504 16283 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 16284 if (htab == NULL)
16285 return FALSE;
16286
b7693d02 16287 eh = (struct elf32_arm_link_hash_entry *) h;
252b5132
RH		 16288
16289 if (h->plt.offset != (bfd_vma) -1)
16290 {
34e77a92 16291 if (!eh->is_iplt)
e5a52504 16292 {
34e77a92 16293 BFD_ASSERT (h->dynindx != -1);
57460bcf
NC		 16294 if (! elf32_arm_populate_plt_entry (output_bfd, info, &h->plt, &eh->plt,
16295 h->dynindx, 0))
16296 return FALSE;
e5a52504 16297 }
57e8b36a 16298
f5385ebf 16299 if (!h->def_regular)
252b5132
RH		 16300 {
16301 /* Mark the symbol as undefined, rather than as defined in
3a635617 16302 the .plt section. */
252b5132 16303 sym->st_shndx = SHN_UNDEF;
3a635617 16304 /* If the symbol is weak we need to clear the value.
d982ba73
PB		 16305 Otherwise, the PLT entry would provide a definition for
16306 the symbol even if the symbol wasn't defined anywhere,
3a635617
WN		 16307 and so the symbol would never be NULL. Leave the value if
16308 there were any relocations where pointer equality matters
16309 (this is a clue for the dynamic linker, to make function
16310 pointer comparisons work between an application and shared
16311 library). */
97323ad1 16312 if (!h->ref_regular_nonweak || !h->pointer_equality_needed)
d982ba73 16313 sym->st_value = 0;
252b5132 16314 }
34e77a92
RS		 16315 else if (eh->is_iplt && eh->plt.noncall_refcount != 0)
16316 {
16317 /* At least one non-call relocation references this .iplt entry,
16318 so the .iplt entry is the function's canonical address. */
16319 sym->st_info = ELF_ST_INFO (ELF_ST_BIND (sym->st_info), STT_FUNC);
39d911fc 16320 ARM_SET_SYM_BRANCH_TYPE (sym->st_target_internal, ST_BRANCH_TO_ARM);
34e77a92
RS		 16321 sym->st_shndx = (_bfd_elf_section_from_bfd_section
16322 (output_bfd, htab->root.iplt->output_section));
16323 sym->st_value = (h->plt.offset
16324 + htab->root.iplt->output_section->vma
16325 + htab->root.iplt->output_offset);
16326 }
252b5132
RH		 16327 }
16328
f5385ebf 16329 if (h->needs_copy)
252b5132
RH		 16330 {
16331 asection * s;
947216bf 16332 Elf_Internal_Rela rel;
252b5132
RH		 16333
16334 /* This symbol needs a copy reloc. Set it up. */
252b5132
RH		 16335 BFD_ASSERT (h->dynindx != -1
16336 && (h->root.type == bfd_link_hash_defined
16337 || h->root.type == bfd_link_hash_defweak));
16338
00a97672 16339 rel.r_addend = 0;
252b5132
RH		 16340 rel.r_offset = (h->root.u.def.value
16341 + h->root.u.def.section->output_section->vma
16342 + h->root.u.def.section->output_offset);
16343 rel.r_info = ELF32_R_INFO (h->dynindx, R_ARM_COPY);
afbf7e8e 16344 if (h->root.u.def.section == htab->root.sdynrelro)
5474d94f
AM		 16345 s = htab->root.sreldynrelro;
16346 else
16347 s = htab->root.srelbss;
47beaa6a 16348 elf32_arm_add_dynreloc (output_bfd, info, s, &rel);
252b5132
RH		 16349 }
16350
00a97672
RS		 16351 /* Mark _DYNAMIC and _GLOBAL_OFFSET_TABLE_ as absolute. On VxWorks,
16352 the _GLOBAL_OFFSET_TABLE_ symbol is not absolute: it is relative
16353 to the ".got" section. */
9637f6ef 16354 if (h == htab->root.hdynamic
00a97672 16355 || (!htab->vxworks_p && h == htab->root.hgot))
252b5132
RH		 16356 sym->st_shndx = SHN_ABS;
16357
b34976b6 16358 return TRUE;
252b5132
RH		 16359}
16360
0855e32b
NS		 16361static void
16362arm_put_trampoline (struct elf32_arm_link_hash_table *htab, bfd *output_bfd,
16363 void *contents,
16364 const unsigned long *template, unsigned count)
16365{
16366 unsigned ix;
b38cadfb 16367
0855e32b
NS		 16368 for (ix = 0; ix != count; ix++)
16369 {
16370 unsigned long insn = template[ix];
16371
16372 /* Emit mov pc,rx if bx is not permitted. */
16373 if (htab->fix_v4bx == 1 && (insn & 0x0ffffff0) == 0x012fff10)
16374 insn = (insn & 0xf000000f) | 0x01a0f000;
16375 put_arm_insn (htab, output_bfd, insn, (char *)contents + ix*4);
16376 }
16377}
16378
99059e56
RM		 16379/* Install the special first PLT entry for elf32-arm-nacl. Unlike
16380 other variants, NaCl needs this entry in a static executable's
16381 .iplt too. When we're handling that case, GOT_DISPLACEMENT is
16382 zero. For .iplt really only the last bundle is useful, and .iplt
16383 could have a shorter first entry, with each individual PLT entry's
16384 relative branch calculated differently so it targets the last
16385 bundle instead of the instruction before it (labelled .Lplt_tail
16386 above). But it's simpler to keep the size and layout of PLT0
16387 consistent with the dynamic case, at the cost of some dead code at
16388 the start of .iplt and the one dead store to the stack at the start
16389 of .Lplt_tail. */
16390static void
16391arm_nacl_put_plt0 (struct elf32_arm_link_hash_table *htab, bfd *output_bfd,
16392 asection *plt, bfd_vma got_displacement)
16393{
16394 unsigned int i;
16395
16396 put_arm_insn (htab, output_bfd,
16397 elf32_arm_nacl_plt0_entry[0]
16398 | arm_movw_immediate (got_displacement),
16399 plt->contents + 0);
16400 put_arm_insn (htab, output_bfd,
16401 elf32_arm_nacl_plt0_entry[1]
16402 | arm_movt_immediate (got_displacement),
16403 plt->contents + 4);
16404
16405 for (i = 2; i < ARRAY_SIZE (elf32_arm_nacl_plt0_entry); ++i)
16406 put_arm_insn (htab, output_bfd,
16407 elf32_arm_nacl_plt0_entry[i],
16408 plt->contents + (i * 4));
16409}
16410
252b5132
RH		 16411/* Finish up the dynamic sections. */
16412
b34976b6 16413static bfd_boolean
57e8b36a 16414elf32_arm_finish_dynamic_sections (bfd * output_bfd, struct bfd_link_info * info)
252b5132
RH		 16415{
16416 bfd * dynobj;
16417 asection * sgot;
16418 asection * sdyn;
4dfe6ac6
NC		 16419 struct elf32_arm_link_hash_table *htab;
16420
16421 htab = elf32_arm_hash_table (info);
16422 if (htab == NULL)
16423 return FALSE;
252b5132
RH		 16424
16425 dynobj = elf_hash_table (info)->dynobj;
16426
362d30a1 16427 sgot = htab->root.sgotplt;
894891db
NC		 16428 /* A broken linker script might have discarded the dynamic sections.
16429 Catch this here so that we do not seg-fault later on. */
16430 if (sgot != NULL && bfd_is_abs_section (sgot->output_section))
16431 return FALSE;
3d4d4302 16432 sdyn = bfd_get_linker_section (dynobj, ".dynamic");
252b5132
RH		 16433
16434 if (elf_hash_table (info)->dynamic_sections_created)
16435 {
16436 asection *splt;
16437 Elf32_External_Dyn *dyncon, *dynconend;
16438
362d30a1 16439 splt = htab->root.splt;
24a1ba0f 16440 BFD_ASSERT (splt != NULL && sdyn != NULL);
cbc704f3 16441 BFD_ASSERT (htab->symbian_p || sgot != NULL);
252b5132
RH		 16442
16443 dyncon = (Elf32_External_Dyn *) sdyn->contents;
eea6121a 16444 dynconend = (Elf32_External_Dyn *) (sdyn->contents + sdyn->size);
9b485d32 16445
252b5132
RH		 16446 for (; dyncon < dynconend; dyncon++)
16447 {
16448 Elf_Internal_Dyn dyn;
16449 const char * name;
16450 asection * s;
16451
16452 bfd_elf32_swap_dyn_in (dynobj, dyncon, &dyn);
16453
16454 switch (dyn.d_tag)
16455 {
229fcec5
MM		 16456 unsigned int type;
16457
252b5132 16458 default:
7a2b07ff
NS		 16459 if (htab->vxworks_p
16460 && elf_vxworks_finish_dynamic_entry (output_bfd, &dyn))
16461 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
252b5132
RH		 16462 break;
16463
229fcec5
MM		 16464 case DT_HASH:
16465 name = ".hash";
16466 goto get_vma_if_bpabi;
16467 case DT_STRTAB:
16468 name = ".dynstr";
16469 goto get_vma_if_bpabi;
16470 case DT_SYMTAB:
16471 name = ".dynsym";
16472 goto get_vma_if_bpabi;
c0042f5d
MM		 16473 case DT_VERSYM:
16474 name = ".gnu.version";
16475 goto get_vma_if_bpabi;
16476 case DT_VERDEF:
16477 name = ".gnu.version_d";
16478 goto get_vma_if_bpabi;
16479 case DT_VERNEED:
16480 name = ".gnu.version_r";
16481 goto get_vma_if_bpabi;
16482
252b5132 16483 case DT_PLTGOT:
4ade44b7 16484 name = htab->symbian_p ? ".got" : ".got.plt";
252b5132
RH		 16485 goto get_vma;
16486 case DT_JMPREL:
00a97672 16487 name = RELOC_SECTION (htab, ".plt");
252b5132 16488 get_vma:
4ade44b7 16489 s = bfd_get_linker_section (dynobj, name);
05456594
NC		 16490 if (s == NULL)
16491 {
4eca0228 16492 _bfd_error_handler
4ade44b7 16493 (_("could not find section %s"), name);
05456594
NC		 16494 bfd_set_error (bfd_error_invalid_operation);
16495 return FALSE;
16496 }
229fcec5 16497 if (!htab->symbian_p)
4ade44b7 16498 dyn.d_un.d_ptr = s->output_section->vma + s->output_offset;
229fcec5
MM		 16499 else
16500 /* In the BPABI, tags in the PT_DYNAMIC section point
16501 at the file offset, not the memory address, for the
16502 convenience of the post linker. */
4ade44b7 16503 dyn.d_un.d_ptr = s->output_section->filepos + s->output_offset;
252b5132
RH		 16504 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
16505 break;
16506
229fcec5
MM		 16507 get_vma_if_bpabi:
16508 if (htab->symbian_p)
16509 goto get_vma;
16510 break;
16511
252b5132 16512 case DT_PLTRELSZ:
362d30a1 16513 s = htab->root.srelplt;
252b5132 16514 BFD_ASSERT (s != NULL);
eea6121a 16515 dyn.d_un.d_val = s->size;
252b5132
RH		 16516 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
16517 break;
906e58ca 16518
252b5132 16519 case DT_RELSZ:
00a97672 16520 case DT_RELASZ:
229fcec5
MM		 16521 case DT_REL:
16522 case DT_RELA:
229fcec5
MM		 16523 /* In the BPABI, the DT_REL tag must point at the file
16524 offset, not the VMA, of the first relocation
16525 section. So, we use code similar to that in
16526 elflink.c, but do not check for SHF_ALLOC on the
64f52338
AM		 16527 relocation section, since relocation sections are
16528 never allocated under the BPABI. PLT relocs are also
16529 included. */
229fcec5
MM		 16530 if (htab->symbian_p)
16531 {
16532 unsigned int i;
16533 type = ((dyn.d_tag == DT_REL || dyn.d_tag == DT_RELSZ)
16534 ? SHT_REL : SHT_RELA);
16535 dyn.d_un.d_val = 0;
16536 for (i = 1; i < elf_numsections (output_bfd); i++)
16537 {
906e58ca 16538 Elf_Internal_Shdr *hdr
229fcec5
MM		 16539 = elf_elfsections (output_bfd)[i];
16540 if (hdr->sh_type == type)
16541 {
906e58ca 16542 if (dyn.d_tag == DT_RELSZ
229fcec5
MM		 16543 || dyn.d_tag == DT_RELASZ)
16544 dyn.d_un.d_val += hdr->sh_size;
de52dba4
AM		 16545 else if ((ufile_ptr) hdr->sh_offset
16546 <= dyn.d_un.d_val - 1)
229fcec5
MM		 16547 dyn.d_un.d_val = hdr->sh_offset;
16548 }
16549 }
16550 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
16551 }
252b5132 16552 break;
88f7bcd5 16553
0855e32b 16554 case DT_TLSDESC_PLT:
99059e56 16555 s = htab->root.splt;
0855e32b
NS		 16556 dyn.d_un.d_ptr = (s->output_section->vma + s->output_offset
16557 + htab->dt_tlsdesc_plt);
16558 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
16559 break;
16560
16561 case DT_TLSDESC_GOT:
99059e56 16562 s = htab->root.sgot;
0855e32b 16563 dyn.d_un.d_ptr = (s->output_section->vma + s->output_offset
99059e56 16564 + htab->dt_tlsdesc_got);
0855e32b
NS		 16565 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
16566 break;
16567
88f7bcd5
NC		 16568 /* Set the bottom bit of DT_INIT/FINI if the
16569 corresponding function is Thumb. */
16570 case DT_INIT:
16571 name = info->init_function;
16572 goto get_sym;
16573 case DT_FINI:
16574 name = info->fini_function;
16575 get_sym:
16576 /* If it wasn't set by elf_bfd_final_link
4cc11e76 16577 then there is nothing to adjust. */
88f7bcd5
NC		 16578 if (dyn.d_un.d_val != 0)
16579 {
16580 struct elf_link_hash_entry * eh;
16581
16582 eh = elf_link_hash_lookup (elf_hash_table (info), name,
b34976b6 16583 FALSE, FALSE, TRUE);
39d911fc
TP		 16584 if (eh != NULL
16585 && ARM_GET_SYM_BRANCH_TYPE (eh->target_internal)
16586 == ST_BRANCH_TO_THUMB)
88f7bcd5
NC		 16587 {
16588 dyn.d_un.d_val |= 1;
b34976b6 16589 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
88f7bcd5
NC		 16590 }
16591 }
16592 break;
252b5132
RH		 16593 }
16594 }
16595
24a1ba0f 16596 /* Fill in the first entry in the procedure linkage table. */
4dfe6ac6 16597 if (splt->size > 0 && htab->plt_header_size)
f7a74f8c 16598 {
00a97672
RS		 16599 const bfd_vma *plt0_entry;
16600 bfd_vma got_address, plt_address, got_displacement;
16601
16602 /* Calculate the addresses of the GOT and PLT. */
16603 got_address = sgot->output_section->vma + sgot->output_offset;
16604 plt_address = splt->output_section->vma + splt->output_offset;
16605
16606 if (htab->vxworks_p)
16607 {
16608 /* The VxWorks GOT is relocated by the dynamic linker.
16609 Therefore, we must emit relocations rather than simply
16610 computing the values now. */
16611 Elf_Internal_Rela rel;
16612
16613 plt0_entry = elf32_arm_vxworks_exec_plt0_entry;
52ab56c2
PB		 16614 put_arm_insn (htab, output_bfd, plt0_entry[0],
16615 splt->contents + 0);
16616 put_arm_insn (htab, output_bfd, plt0_entry[1],
16617 splt->contents + 4);
16618 put_arm_insn (htab, output_bfd, plt0_entry[2],
16619 splt->contents + 8);
00a97672
RS		 16620 bfd_put_32 (output_bfd, got_address, splt->contents + 12);
16621
8029a119 16622 /* Generate a relocation for _GLOBAL_OFFSET_TABLE_. */
00a97672
RS		 16623 rel.r_offset = plt_address + 12;
16624 rel.r_info = ELF32_R_INFO (htab->root.hgot->indx, R_ARM_ABS32);
16625 rel.r_addend = 0;
16626 SWAP_RELOC_OUT (htab) (output_bfd, &rel,
16627 htab->srelplt2->contents);
16628 }
b38cadfb 16629 else if (htab->nacl_p)
99059e56
RM		 16630 arm_nacl_put_plt0 (htab, output_bfd, splt,
16631 got_address + 8 - (plt_address + 16));
eed94f8f
NC		 16632 else if (using_thumb_only (htab))
16633 {
16634 got_displacement = got_address - (plt_address + 12);
16635
16636 plt0_entry = elf32_thumb2_plt0_entry;
16637 put_arm_insn (htab, output_bfd, plt0_entry[0],
16638 splt->contents + 0);
16639 put_arm_insn (htab, output_bfd, plt0_entry[1],
16640 splt->contents + 4);
16641 put_arm_insn (htab, output_bfd, plt0_entry[2],
16642 splt->contents + 8);
16643
16644 bfd_put_32 (output_bfd, got_displacement, splt->contents + 12);
16645 }
00a97672
RS		 16646 else
16647 {
16648 got_displacement = got_address - (plt_address + 16);
16649
16650 plt0_entry = elf32_arm_plt0_entry;
52ab56c2
PB		 16651 put_arm_insn (htab, output_bfd, plt0_entry[0],
16652 splt->contents + 0);
16653 put_arm_insn (htab, output_bfd, plt0_entry[1],
16654 splt->contents + 4);
16655 put_arm_insn (htab, output_bfd, plt0_entry[2],
16656 splt->contents + 8);
16657 put_arm_insn (htab, output_bfd, plt0_entry[3],
16658 splt->contents + 12);
5e681ec4 16659
5e681ec4 16660#ifdef FOUR_WORD_PLT
00a97672
RS		 16661 /* The displacement value goes in the otherwise-unused
16662 last word of the second entry. */
16663 bfd_put_32 (output_bfd, got_displacement, splt->contents + 28);
5e681ec4 16664#else
00a97672 16665 bfd_put_32 (output_bfd, got_displacement, splt->contents + 16);
5e681ec4 16666#endif
00a97672 16667 }
f7a74f8c 16668 }
252b5132
RH		 16669
16670 /* UnixWare sets the entsize of .plt to 4, although that doesn't
16671 really seem like the right value. */
74541ad4
AM		 16672 if (splt->output_section->owner == output_bfd)
16673 elf_section_data (splt->output_section)->this_hdr.sh_entsize = 4;
00a97672 16674
0855e32b
NS		 16675 if (htab->dt_tlsdesc_plt)
16676 {
16677 bfd_vma got_address
16678 = sgot->output_section->vma + sgot->output_offset;
16679 bfd_vma gotplt_address = (htab->root.sgot->output_section->vma
16680 + htab->root.sgot->output_offset);
16681 bfd_vma plt_address
16682 = splt->output_section->vma + splt->output_offset;
16683
b38cadfb 16684 arm_put_trampoline (htab, output_bfd,
0855e32b
NS		 16685 splt->contents + htab->dt_tlsdesc_plt,
16686 dl_tlsdesc_lazy_trampoline, 6);
16687
16688 bfd_put_32 (output_bfd,
16689 gotplt_address + htab->dt_tlsdesc_got
16690 - (plt_address + htab->dt_tlsdesc_plt)
16691 - dl_tlsdesc_lazy_trampoline[6],
16692 splt->contents + htab->dt_tlsdesc_plt + 24);
16693 bfd_put_32 (output_bfd,
16694 got_address - (plt_address + htab->dt_tlsdesc_plt)
16695 - dl_tlsdesc_lazy_trampoline[7],
16696 splt->contents + htab->dt_tlsdesc_plt + 24 + 4);
16697 }
16698
16699 if (htab->tls_trampoline)
16700 {
b38cadfb 16701 arm_put_trampoline (htab, output_bfd,
0855e32b
NS		 16702 splt->contents + htab->tls_trampoline,
16703 tls_trampoline, 3);
16704#ifdef FOUR_WORD_PLT
16705 bfd_put_32 (output_bfd, 0x00000000,
16706 splt->contents + htab->tls_trampoline + 12);
b38cadfb 16707#endif
0855e32b
NS		 16708 }
16709
0e1862bb
L		 16710 if (htab->vxworks_p
16711 && !bfd_link_pic (info)
16712 && htab->root.splt->size > 0)
00a97672
RS		 16713 {
16714 /* Correct the .rel(a).plt.unloaded relocations. They will have
16715 incorrect symbol indexes. */
16716 int num_plts;
eed62c48 16717 unsigned char *p;
00a97672 16718
362d30a1 16719 num_plts = ((htab->root.splt->size - htab->plt_header_size)
00a97672
RS		 16720 / htab->plt_entry_size);
16721 p = htab->srelplt2->contents + RELOC_SIZE (htab);
16722
16723 for (; num_plts; num_plts--)
16724 {
16725 Elf_Internal_Rela rel;
16726
16727 SWAP_RELOC_IN (htab) (output_bfd, p, &rel);
16728 rel.r_info = ELF32_R_INFO (htab->root.hgot->indx, R_ARM_ABS32);
16729 SWAP_RELOC_OUT (htab) (output_bfd, &rel, p);
16730 p += RELOC_SIZE (htab);
16731
16732 SWAP_RELOC_IN (htab) (output_bfd, p, &rel);
16733 rel.r_info = ELF32_R_INFO (htab->root.hplt->indx, R_ARM_ABS32);
16734 SWAP_RELOC_OUT (htab) (output_bfd, &rel, p);
16735 p += RELOC_SIZE (htab);
16736 }
16737 }
252b5132
RH		 16738 }
16739
99059e56
RM		 16740 if (htab->nacl_p && htab->root.iplt != NULL && htab->root.iplt->size > 0)
16741 /* NaCl uses a special first entry in .iplt too. */
16742 arm_nacl_put_plt0 (htab, output_bfd, htab->root.iplt, 0);
16743
252b5132 16744 /* Fill in the first three entries in the global offset table. */
229fcec5 16745 if (sgot)
252b5132 16746 {
229fcec5
MM		 16747 if (sgot->size > 0)
16748 {
16749 if (sdyn == NULL)
16750 bfd_put_32 (output_bfd, (bfd_vma) 0, sgot->contents);
16751 else
16752 bfd_put_32 (output_bfd,
16753 sdyn->output_section->vma + sdyn->output_offset,
16754 sgot->contents);
16755 bfd_put_32 (output_bfd, (bfd_vma) 0, sgot->contents + 4);
16756 bfd_put_32 (output_bfd, (bfd_vma) 0, sgot->contents + 8);
16757 }
252b5132 16758
229fcec5
MM		 16759 elf_section_data (sgot->output_section)->this_hdr.sh_entsize = 4;
16760 }
252b5132 16761
b34976b6 16762 return TRUE;
252b5132
RH		 16763}
16764
ba96a88f 16765static void
57e8b36a 16766elf32_arm_post_process_headers (bfd * abfd, struct bfd_link_info * link_info ATTRIBUTE_UNUSED)
ba96a88f 16767{
9b485d32 16768 Elf_Internal_Ehdr * i_ehdrp; /* ELF file header, internal form. */
e489d0ae 16769 struct elf32_arm_link_hash_table *globals;
ac4c9b04 16770 struct elf_segment_map *m;
ba96a88f
NC		 16771
16772 i_ehdrp = elf_elfheader (abfd);
16773
94a3258f
PB		 16774 if (EF_ARM_EABI_VERSION (i_ehdrp->e_flags) == EF_ARM_EABI_UNKNOWN)
16775 i_ehdrp->e_ident[EI_OSABI] = ELFOSABI_ARM;
16776 else
7394f108 16777 _bfd_elf_post_process_headers (abfd, link_info);
ba96a88f 16778 i_ehdrp->e_ident[EI_ABIVERSION] = ARM_ELF_ABI_VERSION;
e489d0ae 16779
93204d3a
PB		 16780 if (link_info)
16781 {
16782 globals = elf32_arm_hash_table (link_info);
4dfe6ac6 16783 if (globals != NULL && globals->byteswap_code)
93204d3a
PB		 16784 i_ehdrp->e_flags |= EF_ARM_BE8;
16785 }
3bfcb652
NC		 16786
16787 if (EF_ARM_EABI_VERSION (i_ehdrp->e_flags) == EF_ARM_EABI_VER5
16788 && ((i_ehdrp->e_type == ET_DYN) || (i_ehdrp->e_type == ET_EXEC)))
16789 {
16790 int abi = bfd_elf_get_obj_attr_int (abfd, OBJ_ATTR_PROC, Tag_ABI_VFP_args);
5c294fee 16791 if (abi == AEABI_VFP_args_vfp)
3bfcb652
NC		 16792 i_ehdrp->e_flags |= EF_ARM_ABI_FLOAT_HARD;
16793 else
16794 i_ehdrp->e_flags |= EF_ARM_ABI_FLOAT_SOFT;
16795 }
ac4c9b04
MG		 16796
16797 /* Scan segment to set p_flags attribute if it contains only sections with
f0728ee3 16798 SHF_ARM_PURECODE flag. */
ac4c9b04
MG		 16799 for (m = elf_seg_map (abfd); m != NULL; m = m->next)
16800 {
16801 unsigned int j;
16802
16803 if (m->count == 0)
16804 continue;
16805 for (j = 0; j < m->count; j++)
16806 {
f0728ee3 16807 if (!(elf_section_flags (m->sections[j]) & SHF_ARM_PURECODE))
ac4c9b04
MG		 16808 break;
16809 }
16810 if (j == m->count)
16811 {
16812 m->p_flags = PF_X;
16813 m->p_flags_valid = 1;
16814 }
16815 }
ba96a88f
NC		 16816}
16817
99e4ae17 16818static enum elf_reloc_type_class
7e612e98
AM		 16819elf32_arm_reloc_type_class (const struct bfd_link_info *info ATTRIBUTE_UNUSED,
16820 const asection *rel_sec ATTRIBUTE_UNUSED,
16821 const Elf_Internal_Rela *rela)
99e4ae17 16822{
f51e552e 16823 switch ((int) ELF32_R_TYPE (rela->r_info))
99e4ae17
AJ		 16824 {
16825 case R_ARM_RELATIVE:
16826 return reloc_class_relative;
16827 case R_ARM_JUMP_SLOT:
16828 return reloc_class_plt;
16829 case R_ARM_COPY:
16830 return reloc_class_copy;
109575d7
JW		 16831 case R_ARM_IRELATIVE:
16832 return reloc_class_ifunc;
99e4ae17
AJ		 16833 default:
16834 return reloc_class_normal;
16835 }
16836}
16837
e489d0ae 16838static void
57e8b36a 16839elf32_arm_final_write_processing (bfd *abfd, bfd_boolean linker ATTRIBUTE_UNUSED)
e16bb312 16840{
5a6c6817 16841 bfd_arm_update_notes (abfd, ARM_NOTE_SECTION);
e16bb312
NC		 16842}
16843
40a18ebd
NC		 16844/* Return TRUE if this is an unwinding table entry. */
16845
16846static bfd_boolean
16847is_arm_elf_unwind_section_name (bfd * abfd ATTRIBUTE_UNUSED, const char * name)
16848{
0112cd26
NC		 16849 return (CONST_STRNEQ (name, ELF_STRING_ARM_unwind)
16850 || CONST_STRNEQ (name, ELF_STRING_ARM_unwind_once));
40a18ebd
NC		 16851}
16852
16853
16854/* Set the type and flags for an ARM section. We do this by
16855 the section name, which is a hack, but ought to work. */
16856
16857static bfd_boolean
16858elf32_arm_fake_sections (bfd * abfd, Elf_Internal_Shdr * hdr, asection * sec)
16859{
16860 const char * name;
16861
16862 name = bfd_get_section_name (abfd, sec);
16863
16864 if (is_arm_elf_unwind_section_name (abfd, name))
16865 {
16866 hdr->sh_type = SHT_ARM_EXIDX;
16867 hdr->sh_flags |= SHF_LINK_ORDER;
16868 }
ac4c9b04 16869
f0728ee3
AV		 16870 if (sec->flags & SEC_ELF_PURECODE)
16871 hdr->sh_flags |= SHF_ARM_PURECODE;
ac4c9b04 16872
40a18ebd
NC		 16873 return TRUE;
16874}
16875
6dc132d9
L		 16876/* Handle an ARM specific section when reading an object file. This is
16877 called when bfd_section_from_shdr finds a section with an unknown
16878 type. */
40a18ebd
NC		 16879
16880static bfd_boolean
16881elf32_arm_section_from_shdr (bfd *abfd,
16882 Elf_Internal_Shdr * hdr,
6dc132d9
L		 16883 const char *name,
16884 int shindex)
40a18ebd
NC		 16885{
16886 /* There ought to be a place to keep ELF backend specific flags, but
16887 at the moment there isn't one. We just keep track of the
16888 sections by their name, instead. Fortunately, the ABI gives
16889 names for all the ARM specific sections, so we will probably get
16890 away with this. */
16891 switch (hdr->sh_type)
16892 {
16893 case SHT_ARM_EXIDX:
0951f019
RE		 16894 case SHT_ARM_PREEMPTMAP:
16895 case SHT_ARM_ATTRIBUTES:
40a18ebd
NC		 16896 break;
16897
16898 default:
16899 return FALSE;
16900 }
16901
6dc132d9 16902 if (! _bfd_elf_make_section_from_shdr (abfd, hdr, name, shindex))
40a18ebd
NC		 16903 return FALSE;
16904
16905 return TRUE;
16906}
e489d0ae 16907
44444f50
NC		 16908static _arm_elf_section_data *
16909get_arm_elf_section_data (asection * sec)
16910{
47b2e99c
JZ		 16911 if (sec && sec->owner && is_arm_elf (sec->owner))
16912 return elf32_arm_section_data (sec);
44444f50
NC		 16913 else
16914 return NULL;
8e3de13a
NC		 16915}
16916
4e617b1e
PB		 16917typedef struct
16918{
57402f1e 16919 void *flaginfo;
4e617b1e 16920 struct bfd_link_info *info;
91a5743d
PB		 16921 asection *sec;
16922 int sec_shndx;
6e0b88f1
AM		 16923 int (*func) (void *, const char *, Elf_Internal_Sym *,
16924 asection *, struct elf_link_hash_entry *);
4e617b1e
PB		 16925} output_arch_syminfo;
16926
16927enum map_symbol_type
16928{
16929 ARM_MAP_ARM,
16930 ARM_MAP_THUMB,
16931 ARM_MAP_DATA
16932};
16933
16934
7413f23f 16935/* Output a single mapping symbol. */
4e617b1e
PB		 16936
16937static bfd_boolean
7413f23f
DJ		 16938elf32_arm_output_map_sym (output_arch_syminfo *osi,
16939 enum map_symbol_type type,
16940 bfd_vma offset)
4e617b1e
PB		 16941{
16942 static const char *names[3] = {"$a", "$t", "$d"};
4e617b1e
PB		 16943 Elf_Internal_Sym sym;
16944
91a5743d
PB		 16945 sym.st_value = osi->sec->output_section->vma
16946 + osi->sec->output_offset
16947 + offset;
4e617b1e
PB		 16948 sym.st_size = 0;
16949 sym.st_other = 0;
16950 sym.st_info = ELF_ST_INFO (STB_LOCAL, STT_NOTYPE);
91a5743d 16951 sym.st_shndx = osi->sec_shndx;
35fc36a8 16952 sym.st_target_internal = 0;
fe33d2fa 16953 elf32_arm_section_map_add (osi->sec, names[type][1], offset);
57402f1e 16954 return osi->func (osi->flaginfo, names[type], &sym, osi->sec, NULL) == 1;
4e617b1e
PB		 16955}
16956
34e77a92
RS		 16957/* Output mapping symbols for the PLT entry described by ROOT_PLT and ARM_PLT.
16958 IS_IPLT_ENTRY_P says whether the PLT is in .iplt rather than .plt. */
4e617b1e
PB		 16959
16960static bfd_boolean
34e77a92
RS		 16961elf32_arm_output_plt_map_1 (output_arch_syminfo *osi,
16962 bfd_boolean is_iplt_entry_p,
16963 union gotplt_union *root_plt,
16964 struct arm_plt_info *arm_plt)
4e617b1e 16965{
4e617b1e 16966 struct elf32_arm_link_hash_table *htab;
34e77a92 16967 bfd_vma addr, plt_header_size;
4e617b1e 16968
34e77a92 16969 if (root_plt->offset == (bfd_vma) -1)
4e617b1e
PB		 16970 return TRUE;
16971
4dfe6ac6
NC		 16972 htab = elf32_arm_hash_table (osi->info);
16973 if (htab == NULL)
16974 return FALSE;
16975
34e77a92
RS		 16976 if (is_iplt_entry_p)
16977 {
16978 osi->sec = htab->root.iplt;
16979 plt_header_size = 0;
16980 }
16981 else
16982 {
16983 osi->sec = htab->root.splt;
16984 plt_header_size = htab->plt_header_size;
16985 }
16986 osi->sec_shndx = (_bfd_elf_section_from_bfd_section
16987 (osi->info->output_bfd, osi->sec->output_section));
16988
16989 addr = root_plt->offset & -2;
4e617b1e
PB		 16990 if (htab->symbian_p)
16991 {
7413f23f 16992 if (!elf32_arm_output_map_sym (osi, ARM_MAP_ARM, addr))
4e617b1e 16993 return FALSE;
7413f23f 16994 if (!elf32_arm_output_map_sym (osi, ARM_MAP_DATA, addr + 4))
4e617b1e
PB		 16995 return FALSE;
16996 }
16997 else if (htab->vxworks_p)
16998 {
7413f23f 16999 if (!elf32_arm_output_map_sym (osi, ARM_MAP_ARM, addr))
4e617b1e 17000 return FALSE;
7413f23f 17001 if (!elf32_arm_output_map_sym (osi, ARM_MAP_DATA, addr + 8))
4e617b1e 17002 return FALSE;
7413f23f 17003 if (!elf32_arm_output_map_sym (osi, ARM_MAP_ARM, addr + 12))
4e617b1e 17004 return FALSE;
7413f23f 17005 if (!elf32_arm_output_map_sym (osi, ARM_MAP_DATA, addr + 20))
4e617b1e
PB		 17006 return FALSE;
17007 }
b38cadfb
NC		 17008 else if (htab->nacl_p)
17009 {
17010 if (!elf32_arm_output_map_sym (osi, ARM_MAP_ARM, addr))
17011 return FALSE;
17012 }
eed94f8f
NC		 17013 else if (using_thumb_only (htab))
17014 {
17015 if (!elf32_arm_output_map_sym (osi, ARM_MAP_THUMB, addr))
17016 return FALSE;
6a631e86 17017 }
4e617b1e
PB		 17018 else
17019 {
34e77a92 17020 bfd_boolean thumb_stub_p;
bd97cb95 17021
34e77a92
RS		 17022 thumb_stub_p = elf32_arm_plt_needs_thumb_stub_p (osi->info, arm_plt);
17023 if (thumb_stub_p)
4e617b1e 17024 {
7413f23f 17025 if (!elf32_arm_output_map_sym (osi, ARM_MAP_THUMB, addr - 4))
4e617b1e
PB		 17026 return FALSE;
17027 }
17028#ifdef FOUR_WORD_PLT
7413f23f 17029 if (!elf32_arm_output_map_sym (osi, ARM_MAP_ARM, addr))
4e617b1e 17030 return FALSE;
7413f23f 17031 if (!elf32_arm_output_map_sym (osi, ARM_MAP_DATA, addr + 12))
4e617b1e
PB		 17032 return FALSE;
17033#else
906e58ca 17034 /* A three-word PLT with no Thumb thunk contains only Arm code,
4e617b1e
PB		 17035 so only need to output a mapping symbol for the first PLT entry and
17036 entries with thumb thunks. */
34e77a92 17037 if (thumb_stub_p || addr == plt_header_size)
4e617b1e 17038 {
7413f23f 17039 if (!elf32_arm_output_map_sym (osi, ARM_MAP_ARM, addr))
4e617b1e
PB		 17040 return FALSE;
17041 }
17042#endif
17043 }
17044
17045 return TRUE;
17046}
17047
34e77a92
RS		 17048/* Output mapping symbols for PLT entries associated with H. */
17049
17050static bfd_boolean
17051elf32_arm_output_plt_map (struct elf_link_hash_entry *h, void *inf)
17052{
17053 output_arch_syminfo *osi = (output_arch_syminfo *) inf;
17054 struct elf32_arm_link_hash_entry *eh;
17055
17056 if (h->root.type == bfd_link_hash_indirect)
17057 return TRUE;
17058
17059 if (h->root.type == bfd_link_hash_warning)
17060 /* When warning symbols are created, they **replace** the "real"
17061 entry in the hash table, thus we never get to see the real
17062 symbol in a hash traversal. So look at it now. */
17063 h = (struct elf_link_hash_entry *) h->root.u.i.link;
17064
17065 eh = (struct elf32_arm_link_hash_entry *) h;
17066 return elf32_arm_output_plt_map_1 (osi, SYMBOL_CALLS_LOCAL (osi->info, h),
17067 &h->plt, &eh->plt);
17068}
17069
4f4faa4d
TP		 17070/* Bind a veneered symbol to its veneer identified by its hash entry
17071 STUB_ENTRY. The veneered location thus loose its symbol. */
17072
17073static void
17074arm_stub_claim_sym (struct elf32_arm_stub_hash_entry *stub_entry)
17075{
17076 struct elf32_arm_link_hash_entry *hash = stub_entry->h;
17077
17078 BFD_ASSERT (hash);
17079 hash->root.root.u.def.section = stub_entry->stub_sec;
17080 hash->root.root.u.def.value = stub_entry->stub_offset;
17081 hash->root.size = stub_entry->stub_size;
17082}
17083
7413f23f
DJ		 17084/* Output a single local symbol for a generated stub. */
17085
17086static bfd_boolean
17087elf32_arm_output_stub_sym (output_arch_syminfo *osi, const char *name,
17088 bfd_vma offset, bfd_vma size)
17089{
7413f23f
DJ		 17090 Elf_Internal_Sym sym;
17091
7413f23f
DJ		 17092 sym.st_value = osi->sec->output_section->vma
17093 + osi->sec->output_offset
17094 + offset;
17095 sym.st_size = size;
17096 sym.st_other = 0;
17097 sym.st_info = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
17098 sym.st_shndx = osi->sec_shndx;
35fc36a8 17099 sym.st_target_internal = 0;
57402f1e 17100 return osi->func (osi->flaginfo, name, &sym, osi->sec, NULL) == 1;
7413f23f 17101}
4e617b1e 17102
da5938a2 17103static bfd_boolean
8029a119
NC		 17104arm_map_one_stub (struct bfd_hash_entry * gen_entry,
17105 void * in_arg)
da5938a2
NC		 17106{
17107 struct elf32_arm_stub_hash_entry *stub_entry;
da5938a2
NC		 17108 asection *stub_sec;
17109 bfd_vma addr;
7413f23f 17110 char *stub_name;
9a008db3 17111 output_arch_syminfo *osi;
d3ce72d0 17112 const insn_sequence *template_sequence;
461a49ca
DJ		 17113 enum stub_insn_type prev_type;
17114 int size;
17115 int i;
17116 enum map_symbol_type sym_type;
da5938a2
NC		 17117
17118 /* Massage our args to the form they really have. */
17119 stub_entry = (struct elf32_arm_stub_hash_entry *) gen_entry;
9a008db3 17120 osi = (output_arch_syminfo *) in_arg;
da5938a2 17121
da5938a2
NC		 17122 stub_sec = stub_entry->stub_sec;
17123
17124 /* Ensure this stub is attached to the current section being
7413f23f 17125 processed. */
da5938a2
NC		 17126 if (stub_sec != osi->sec)
17127 return TRUE;
17128
7413f23f 17129 addr = (bfd_vma) stub_entry->stub_offset;
d3ce72d0 17130 template_sequence = stub_entry->stub_template;
4f4faa4d
TP		 17131
17132 if (arm_stub_sym_claimed (stub_entry->stub_type))
17133 arm_stub_claim_sym (stub_entry);
17134 else
7413f23f 17135 {
4f4faa4d
TP		 17136 stub_name = stub_entry->output_name;
17137 switch (template_sequence[0].type)
17138 {
17139 case ARM_TYPE:
17140 if (!elf32_arm_output_stub_sym (osi, stub_name, addr,
17141 stub_entry->stub_size))
17142 return FALSE;
17143 break;
17144 case THUMB16_TYPE:
17145 case THUMB32_TYPE:
17146 if (!elf32_arm_output_stub_sym (osi, stub_name, addr | 1,
17147 stub_entry->stub_size))
17148 return FALSE;
17149 break;
17150 default:
17151 BFD_FAIL ();
17152 return 0;
17153 }
7413f23f 17154 }
da5938a2 17155
461a49ca
DJ		 17156 prev_type = DATA_TYPE;
17157 size = 0;
17158 for (i = 0; i < stub_entry->stub_template_size; i++)
17159 {
d3ce72d0 17160 switch (template_sequence[i].type)
461a49ca
DJ		 17161 {
17162 case ARM_TYPE:
17163 sym_type = ARM_MAP_ARM;
17164 break;
17165
17166 case THUMB16_TYPE:
48229727 17167 case THUMB32_TYPE:
461a49ca
DJ		 17168 sym_type = ARM_MAP_THUMB;
17169 break;
17170
17171 case DATA_TYPE:
17172 sym_type = ARM_MAP_DATA;
17173 break;
17174
17175 default:
17176 BFD_FAIL ();
4e31c731 17177 return FALSE;
461a49ca
DJ		 17178 }
17179
d3ce72d0 17180 if (template_sequence[i].type != prev_type)
461a49ca 17181 {
d3ce72d0 17182 prev_type = template_sequence[i].type;
461a49ca
DJ		 17183 if (!elf32_arm_output_map_sym (osi, sym_type, addr + size))
17184 return FALSE;
17185 }
17186
d3ce72d0 17187 switch (template_sequence[i].type)
461a49ca
DJ		 17188 {
17189 case ARM_TYPE:
48229727 17190 case THUMB32_TYPE:
461a49ca
DJ		 17191 size += 4;
17192 break;
17193
17194 case THUMB16_TYPE:
17195 size += 2;
17196 break;
17197
17198 case DATA_TYPE:
17199 size += 4;
17200 break;
17201
17202 default:
17203 BFD_FAIL ();
4e31c731 17204 return FALSE;
461a49ca
DJ		 17205 }
17206 }
17207
da5938a2
NC		 17208 return TRUE;
17209}
17210
33811162
DG		 17211/* Output mapping symbols for linker generated sections,
17212 and for those data-only sections that do not have a
17213 $d. */
4e617b1e
PB		 17214
17215static bfd_boolean
17216elf32_arm_output_arch_local_syms (bfd *output_bfd,
906e58ca 17217 struct bfd_link_info *info,
57402f1e 17218 void *flaginfo,
6e0b88f1
AM		 17219 int (*func) (void *, const char *,
17220 Elf_Internal_Sym *,
17221 asection *,
17222 struct elf_link_hash_entry *))
4e617b1e
PB		 17223{
17224 output_arch_syminfo osi;
17225 struct elf32_arm_link_hash_table *htab;
91a5743d
PB		 17226 bfd_vma offset;
17227 bfd_size_type size;
33811162 17228 bfd *input_bfd;
4e617b1e
PB		 17229
17230 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 17231 if (htab == NULL)
17232 return FALSE;
17233
906e58ca 17234 check_use_blx (htab);
91a5743d 17235
57402f1e 17236 osi.flaginfo = flaginfo;
4e617b1e
PB		 17237 osi.info = info;
17238 osi.func = func;
906e58ca 17239
33811162
DG		 17240 /* Add a $d mapping symbol to data-only sections that
17241 don't have any mapping symbol. This may result in (harmless) redundant
17242 mapping symbols. */
17243 for (input_bfd = info->input_bfds;
17244 input_bfd != NULL;
c72f2fb2 17245 input_bfd = input_bfd->link.next)
33811162
DG		 17246 {
17247 if ((input_bfd->flags & (BFD_LINKER_CREATED | HAS_SYMS)) == HAS_SYMS)
17248 for (osi.sec = input_bfd->sections;
17249 osi.sec != NULL;
17250 osi.sec = osi.sec->next)
17251 {
17252 if (osi.sec->output_section != NULL
f7dd8c79
DJ		 17253 && ((osi.sec->output_section->flags & (SEC_ALLOC | SEC_CODE))
17254 != 0)
33811162
DG		 17255 && (osi.sec->flags & (SEC_HAS_CONTENTS | SEC_LINKER_CREATED))
17256 == SEC_HAS_CONTENTS
17257 && get_arm_elf_section_data (osi.sec) != NULL
501abfe0 17258 && get_arm_elf_section_data (osi.sec)->mapcount == 0
7d500b83
CL		 17259 && osi.sec->size > 0
17260 && (osi.sec->flags & SEC_EXCLUDE) == 0)
33811162
DG		 17261 {
17262 osi.sec_shndx = _bfd_elf_section_from_bfd_section
17263 (output_bfd, osi.sec->output_section);
17264 if (osi.sec_shndx != (int)SHN_BAD)
17265 elf32_arm_output_map_sym (&osi, ARM_MAP_DATA, 0);
17266 }
17267 }
17268 }
17269
91a5743d
PB		 17270 /* ARM->Thumb glue. */
17271 if (htab->arm_glue_size > 0)
17272 {
3d4d4302
AM		 17273 osi.sec = bfd_get_linker_section (htab->bfd_of_glue_owner,
17274 ARM2THUMB_GLUE_SECTION_NAME);
91a5743d
PB		 17275
17276 osi.sec_shndx = _bfd_elf_section_from_bfd_section
17277 (output_bfd, osi.sec->output_section);
0e1862bb 17278 if (bfd_link_pic (info) || htab->root.is_relocatable_executable
91a5743d
PB		 17279 || htab->pic_veneer)
17280 size = ARM2THUMB_PIC_GLUE_SIZE;
17281 else if (htab->use_blx)
17282 size = ARM2THUMB_V5_STATIC_GLUE_SIZE;
17283 else
17284 size = ARM2THUMB_STATIC_GLUE_SIZE;
4e617b1e 17285
91a5743d
PB		 17286 for (offset = 0; offset < htab->arm_glue_size; offset += size)
17287 {
7413f23f
DJ		 17288 elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, offset);
17289 elf32_arm_output_map_sym (&osi, ARM_MAP_DATA, offset + size - 4);
91a5743d
PB		 17290 }
17291 }
17292
17293 /* Thumb->ARM glue. */
17294 if (htab->thumb_glue_size > 0)
17295 {
3d4d4302
AM		 17296 osi.sec = bfd_get_linker_section (htab->bfd_of_glue_owner,
17297 THUMB2ARM_GLUE_SECTION_NAME);
91a5743d
PB		 17298
17299 osi.sec_shndx = _bfd_elf_section_from_bfd_section
17300 (output_bfd, osi.sec->output_section);
17301 size = THUMB2ARM_GLUE_SIZE;
17302
17303 for (offset = 0; offset < htab->thumb_glue_size; offset += size)
17304 {
7413f23f
DJ		 17305 elf32_arm_output_map_sym (&osi, ARM_MAP_THUMB, offset);
17306 elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, offset + 4);
91a5743d
PB		 17307 }
17308 }
17309
845b51d6
PB		 17310 /* ARMv4 BX veneers. */
17311 if (htab->bx_glue_size > 0)
17312 {
3d4d4302
AM		 17313 osi.sec = bfd_get_linker_section (htab->bfd_of_glue_owner,
17314 ARM_BX_GLUE_SECTION_NAME);
845b51d6
PB		 17315
17316 osi.sec_shndx = _bfd_elf_section_from_bfd_section
17317 (output_bfd, osi.sec->output_section);
17318
7413f23f 17319 elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, 0);
845b51d6
PB		 17320 }
17321
8029a119
NC		 17322 /* Long calls stubs. */
17323 if (htab->stub_bfd && htab->stub_bfd->sections)
17324 {
da5938a2 17325 asection* stub_sec;
8029a119 17326
da5938a2
NC		 17327 for (stub_sec = htab->stub_bfd->sections;
17328 stub_sec != NULL;
8029a119
NC		 17329 stub_sec = stub_sec->next)
17330 {
17331 /* Ignore non-stub sections. */
17332 if (!strstr (stub_sec->name, STUB_SUFFIX))
17333 continue;
da5938a2 17334
8029a119 17335 osi.sec = stub_sec;
da5938a2 17336
8029a119
NC		 17337 osi.sec_shndx = _bfd_elf_section_from_bfd_section
17338 (output_bfd, osi.sec->output_section);
da5938a2 17339
8029a119
NC		 17340 bfd_hash_traverse (&htab->stub_hash_table, arm_map_one_stub, &osi);
17341 }
17342 }
da5938a2 17343
91a5743d 17344 /* Finally, output mapping symbols for the PLT. */
34e77a92 17345 if (htab->root.splt && htab->root.splt->size > 0)
4e617b1e 17346 {
34e77a92
RS		 17347 osi.sec = htab->root.splt;
17348 osi.sec_shndx = (_bfd_elf_section_from_bfd_section
17349 (output_bfd, osi.sec->output_section));
17350
17351 /* Output mapping symbols for the plt header. SymbianOS does not have a
17352 plt header. */
17353 if (htab->vxworks_p)
17354 {
17355 /* VxWorks shared libraries have no PLT header. */
0e1862bb 17356 if (!bfd_link_pic (info))
34e77a92
RS		 17357 {
17358 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, 0))
17359 return FALSE;
17360 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_DATA, 12))
17361 return FALSE;
17362 }
17363 }
b38cadfb
NC		 17364 else if (htab->nacl_p)
17365 {
17366 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, 0))
17367 return FALSE;
17368 }
eed94f8f
NC		 17369 else if (using_thumb_only (htab))
17370 {
17371 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_THUMB, 0))
17372 return FALSE;
17373 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_DATA, 12))
17374 return FALSE;
17375 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_THUMB, 16))
17376 return FALSE;
17377 }
34e77a92 17378 else if (!htab->symbian_p)
4e617b1e 17379 {
7413f23f 17380 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, 0))
4e617b1e 17381 return FALSE;
34e77a92
RS		 17382#ifndef FOUR_WORD_PLT
17383 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_DATA, 16))
4e617b1e 17384 return FALSE;
34e77a92 17385#endif
4e617b1e
PB		 17386 }
17387 }
99059e56
RM		 17388 if (htab->nacl_p && htab->root.iplt && htab->root.iplt->size > 0)
17389 {
17390 /* NaCl uses a special first entry in .iplt too. */
17391 osi.sec = htab->root.iplt;
17392 osi.sec_shndx = (_bfd_elf_section_from_bfd_section
17393 (output_bfd, osi.sec->output_section));
17394 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, 0))
17395 return FALSE;
17396 }
34e77a92
RS		 17397 if ((htab->root.splt && htab->root.splt->size > 0)
17398 || (htab->root.iplt && htab->root.iplt->size > 0))
4e617b1e 17399 {
34e77a92
RS		 17400 elf_link_hash_traverse (&htab->root, elf32_arm_output_plt_map, &osi);
17401 for (input_bfd = info->input_bfds;
17402 input_bfd != NULL;
c72f2fb2 17403 input_bfd = input_bfd->link.next)
34e77a92
RS		 17404 {
17405 struct arm_local_iplt_info **local_iplt;
17406 unsigned int i, num_syms;
4e617b1e 17407
34e77a92
RS		 17408 local_iplt = elf32_arm_local_iplt (input_bfd);
17409 if (local_iplt != NULL)
17410 {
17411 num_syms = elf_symtab_hdr (input_bfd).sh_info;
17412 for (i = 0; i < num_syms; i++)
17413 if (local_iplt[i] != NULL
17414 && !elf32_arm_output_plt_map_1 (&osi, TRUE,
17415 &local_iplt[i]->root,
17416 &local_iplt[i]->arm))
17417 return FALSE;
17418 }
17419 }
17420 }
0855e32b
NS		 17421 if (htab->dt_tlsdesc_plt != 0)
17422 {
17423 /* Mapping symbols for the lazy tls trampoline. */
17424 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, htab->dt_tlsdesc_plt))
17425 return FALSE;
b38cadfb 17426
0855e32b
NS		 17427 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_DATA,
17428 htab->dt_tlsdesc_plt + 24))
17429 return FALSE;
17430 }
17431 if (htab->tls_trampoline != 0)
17432 {
17433 /* Mapping symbols for the tls trampoline. */
17434 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, htab->tls_trampoline))
17435 return FALSE;
17436#ifdef FOUR_WORD_PLT
17437 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_DATA,
17438 htab->tls_trampoline + 12))
17439 return FALSE;
b38cadfb 17440#endif
0855e32b 17441 }
b38cadfb 17442
4e617b1e
PB		 17443 return TRUE;
17444}
17445
54ddd295
TP		 17446/* Filter normal symbols of CMSE entry functions of ABFD to include in
17447 the import library. All SYMCOUNT symbols of ABFD can be examined
17448 from their pointers in SYMS. Pointers of symbols to keep should be
17449 stored continuously at the beginning of that array.
17450
17451 Returns the number of symbols to keep. */
17452
17453static unsigned int
17454elf32_arm_filter_cmse_symbols (bfd *abfd ATTRIBUTE_UNUSED,
17455 struct bfd_link_info *info,
17456 asymbol **syms, long symcount)
17457{
17458 size_t maxnamelen;
17459 char *cmse_name;
17460 long src_count, dst_count = 0;
17461 struct elf32_arm_link_hash_table *htab;
17462
17463 htab = elf32_arm_hash_table (info);
17464 if (!htab->stub_bfd || !htab->stub_bfd->sections)
17465 symcount = 0;
17466
17467 maxnamelen = 128;
17468 cmse_name = (char *) bfd_malloc (maxnamelen);
17469 for (src_count = 0; src_count < symcount; src_count++)
17470 {
17471 struct elf32_arm_link_hash_entry *cmse_hash;
17472 asymbol *sym;
17473 flagword flags;
17474 char *name;
17475 size_t namelen;
17476
17477 sym = syms[src_count];
17478 flags = sym->flags;
17479 name = (char *) bfd_asymbol_name (sym);
17480
17481 if ((flags & BSF_FUNCTION) != BSF_FUNCTION)
17482 continue;
17483 if (!(flags & (BSF_GLOBAL | BSF_WEAK)))
17484 continue;
17485
17486 namelen = strlen (name) + sizeof (CMSE_PREFIX) + 1;
17487 if (namelen > maxnamelen)
17488 {
17489 cmse_name = (char *)
17490 bfd_realloc (cmse_name, namelen);
17491 maxnamelen = namelen;
17492 }
17493 snprintf (cmse_name, maxnamelen, "%s%s", CMSE_PREFIX, name);
17494 cmse_hash = (struct elf32_arm_link_hash_entry *)
17495 elf_link_hash_lookup (&(htab)->root, cmse_name, FALSE, FALSE, TRUE);
17496
17497 if (!cmse_hash
17498 || (cmse_hash->root.root.type != bfd_link_hash_defined
17499 && cmse_hash->root.root.type != bfd_link_hash_defweak)
17500 || cmse_hash->root.type != STT_FUNC)
17501 continue;
17502
17503 if (!ARM_GET_SYM_CMSE_SPCL (cmse_hash->root.target_internal))
17504 continue;
17505
17506 syms[dst_count++] = sym;
17507 }
17508 free (cmse_name);
17509
17510 syms[dst_count] = NULL;
17511
17512 return dst_count;
17513}
17514
17515/* Filter symbols of ABFD to include in the import library. All
17516 SYMCOUNT symbols of ABFD can be examined from their pointers in
17517 SYMS. Pointers of symbols to keep should be stored continuously at
17518 the beginning of that array.
17519
17520 Returns the number of symbols to keep. */
17521
17522static unsigned int
17523elf32_arm_filter_implib_symbols (bfd *abfd ATTRIBUTE_UNUSED,
17524 struct bfd_link_info *info,
17525 asymbol **syms, long symcount)
17526{
17527 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (info);
17528
046734ff
TP		 17529 /* Requirement 8 of "ARM v8-M Security Extensions: Requirements on
17530 Development Tools" (ARM-ECM-0359818) mandates Secure Gateway import
17531 library to be a relocatable object file. */
17532 BFD_ASSERT (!(bfd_get_file_flags (info->out_implib_bfd) & EXEC_P));
54ddd295
TP		 17533 if (globals->cmse_implib)
17534 return elf32_arm_filter_cmse_symbols (abfd, info, syms, symcount);
17535 else
17536 return _bfd_elf_filter_global_symbols (abfd, info, syms, symcount);
17537}
17538
e489d0ae
PB		 17539/* Allocate target specific section data. */
17540
17541static bfd_boolean
17542elf32_arm_new_section_hook (bfd *abfd, asection *sec)
17543{
f592407e
AM		 17544 if (!sec->used_by_bfd)
17545 {
17546 _arm_elf_section_data *sdata;
17547 bfd_size_type amt = sizeof (*sdata);
e489d0ae 17548
21d799b5 17549 sdata = (_arm_elf_section_data *) bfd_zalloc (abfd, amt);
f592407e
AM		 17550 if (sdata == NULL)
17551 return FALSE;
17552 sec->used_by_bfd = sdata;
17553 }
e489d0ae
PB		 17554
17555 return _bfd_elf_new_section_hook (abfd, sec);
17556}
17557
17558
17559/* Used to order a list of mapping symbols by address. */
17560
17561static int
17562elf32_arm_compare_mapping (const void * a, const void * b)
17563{
7f6a71ff
JM		 17564 const elf32_arm_section_map *amap = (const elf32_arm_section_map *) a;
17565 const elf32_arm_section_map *bmap = (const elf32_arm_section_map *) b;
17566
17567 if (amap->vma > bmap->vma)
17568 return 1;
17569 else if (amap->vma < bmap->vma)
17570 return -1;
17571 else if (amap->type > bmap->type)
17572 /* Ensure results do not depend on the host qsort for objects with
17573 multiple mapping symbols at the same address by sorting on type
17574 after vma. */
17575 return 1;
17576 else if (amap->type < bmap->type)
17577 return -1;
17578 else
17579 return 0;
e489d0ae
PB		 17580}
17581
2468f9c9
PB		 17582/* Add OFFSET to lower 31 bits of ADDR, leaving other bits unmodified. */
17583
17584static unsigned long
17585offset_prel31 (unsigned long addr, bfd_vma offset)
17586{
17587 return (addr & ~0x7ffffffful) | ((addr + offset) & 0x7ffffffful);
17588}
17589
17590/* Copy an .ARM.exidx table entry, adding OFFSET to (applied) PREL31
17591 relocations. */
17592
17593static void
17594copy_exidx_entry (bfd *output_bfd, bfd_byte *to, bfd_byte *from, bfd_vma offset)
17595{
17596 unsigned long first_word = bfd_get_32 (output_bfd, from);
17597 unsigned long second_word = bfd_get_32 (output_bfd, from + 4);
b38cadfb 17598
2468f9c9
PB		 17599 /* High bit of first word is supposed to be zero. */
17600 if ((first_word & 0x80000000ul) == 0)
17601 first_word = offset_prel31 (first_word, offset);
b38cadfb 17602
2468f9c9
PB		 17603 /* If the high bit of the first word is clear, and the bit pattern is not 0x1
17604 (EXIDX_CANTUNWIND), this is an offset to an .ARM.extab entry. */
17605 if ((second_word != 0x1) && ((second_word & 0x80000000ul) == 0))
17606 second_word = offset_prel31 (second_word, offset);
b38cadfb 17607
2468f9c9
PB		 17608 bfd_put_32 (output_bfd, first_word, to);
17609 bfd_put_32 (output_bfd, second_word, to + 4);
17610}
e489d0ae 17611
48229727
JB		 17612/* Data for make_branch_to_a8_stub(). */
17613
b38cadfb
NC		 17614struct a8_branch_to_stub_data
17615{
48229727
JB		 17616 asection *writing_section;
17617 bfd_byte *contents;
17618};
17619
17620
17621/* Helper to insert branches to Cortex-A8 erratum stubs in the right
17622 places for a particular section. */
17623
17624static bfd_boolean
17625make_branch_to_a8_stub (struct bfd_hash_entry *gen_entry,
99059e56 17626 void *in_arg)
48229727
JB		 17627{
17628 struct elf32_arm_stub_hash_entry *stub_entry;
17629 struct a8_branch_to_stub_data *data;
17630 bfd_byte *contents;
17631 unsigned long branch_insn;
17632 bfd_vma veneered_insn_loc, veneer_entry_loc;
17633 bfd_signed_vma branch_offset;
17634 bfd *abfd;
8d9d9490 17635 unsigned int loc;
48229727
JB		 17636
17637 stub_entry = (struct elf32_arm_stub_hash_entry *) gen_entry;
17638 data = (struct a8_branch_to_stub_data *) in_arg;
17639
17640 if (stub_entry->target_section != data->writing_section
4563a860 17641 || stub_entry->stub_type < arm_stub_a8_veneer_lwm)
48229727
JB		 17642 return TRUE;
17643
17644 contents = data->contents;
17645
8d9d9490
TP		 17646 /* We use target_section as Cortex-A8 erratum workaround stubs are only
17647 generated when both source and target are in the same section. */
48229727
JB		 17648 veneered_insn_loc = stub_entry->target_section->output_section->vma
17649 + stub_entry->target_section->output_offset
8d9d9490 17650 + stub_entry->source_value;
48229727
JB		 17651
17652 veneer_entry_loc = stub_entry->stub_sec->output_section->vma
17653 + stub_entry->stub_sec->output_offset
17654 + stub_entry->stub_offset;
17655
17656 if (stub_entry->stub_type == arm_stub_a8_veneer_blx)
17657 veneered_insn_loc &= ~3u;
17658
17659 branch_offset = veneer_entry_loc - veneered_insn_loc - 4;
17660
17661 abfd = stub_entry->target_section->owner;
8d9d9490 17662 loc = stub_entry->source_value;
48229727
JB		 17663
17664 /* We attempt to avoid this condition by setting stubs_always_after_branch
17665 in elf32_arm_size_stubs if we've enabled the Cortex-A8 erratum workaround.
17666 This check is just to be on the safe side... */
17667 if ((veneered_insn_loc & ~0xfff) == (veneer_entry_loc & ~0xfff))
17668 {
4eca0228
AM		 17669 _bfd_error_handler (_("%B: error: Cortex-A8 erratum stub is "
17670 "allocated in unsafe location"), abfd);
48229727
JB		 17671 return FALSE;
17672 }
17673
17674 switch (stub_entry->stub_type)
17675 {
17676 case arm_stub_a8_veneer_b:
17677 case arm_stub_a8_veneer_b_cond:
17678 branch_insn = 0xf0009000;
17679 goto jump24;
17680
17681 case arm_stub_a8_veneer_blx:
17682 branch_insn = 0xf000e800;
17683 goto jump24;
17684
17685 case arm_stub_a8_veneer_bl:
17686 {
17687 unsigned int i1, j1, i2, j2, s;
17688
17689 branch_insn = 0xf000d000;
17690
17691 jump24:
17692 if (branch_offset < -16777216 || branch_offset > 16777214)
17693 {
17694 /* There's not much we can do apart from complain if this
17695 happens. */
4eca0228
AM		 17696 _bfd_error_handler (_("%B: error: Cortex-A8 erratum stub out "
17697 "of range (input file too large)"), abfd);
48229727
JB		 17698 return FALSE;
17699 }
17700
17701 /* i1 = not(j1 eor s), so:
17702 not i1 = j1 eor s
17703 j1 = (not i1) eor s. */
17704
17705 branch_insn |= (branch_offset >> 1) & 0x7ff;
17706 branch_insn |= ((branch_offset >> 12) & 0x3ff) << 16;
17707 i2 = (branch_offset >> 22) & 1;
17708 i1 = (branch_offset >> 23) & 1;
17709 s = (branch_offset >> 24) & 1;
17710 j1 = (!i1) ^ s;
17711 j2 = (!i2) ^ s;
17712 branch_insn |= j2 << 11;
17713 branch_insn |= j1 << 13;
17714 branch_insn |= s << 26;
17715 }
17716 break;
17717
17718 default:
17719 BFD_FAIL ();
17720 return FALSE;
17721 }
17722
8d9d9490
TP		 17723 bfd_put_16 (abfd, (branch_insn >> 16) & 0xffff, &contents[loc]);
17724 bfd_put_16 (abfd, branch_insn & 0xffff, &contents[loc + 2]);
48229727
JB		 17725
17726 return TRUE;
17727}
17728
a504d23a
LA		 17729/* Beginning of stm32l4xx work-around. */
17730
17731/* Functions encoding instructions necessary for the emission of the
17732 fix-stm32l4xx-629360.
17733 Encoding is extracted from the
17734 ARM (C) Architecture Reference Manual
17735 ARMv7-A and ARMv7-R edition
17736 ARM DDI 0406C.b (ID072512). */
17737
17738static inline bfd_vma
82188b29 17739create_instruction_branch_absolute (int branch_offset)
a504d23a
LA		 17740{
17741 /* A8.8.18 B (A8-334)
17742 B target_address (Encoding T4). */
17743 /* 1111 - 0Sii - iiii - iiii - 10J1 - Jiii - iiii - iiii. */
17744 /* jump offset is: S:I1:I2:imm10:imm11:0. */
17745 /* with : I1 = NOT (J1 EOR S) I2 = NOT (J2 EOR S). */
17746
a504d23a
LA		 17747 int s = ((branch_offset & 0x1000000) >> 24);
17748 int j1 = s ^ !((branch_offset & 0x800000) >> 23);
17749 int j2 = s ^ !((branch_offset & 0x400000) >> 22);
17750
17751 if (branch_offset < -(1 << 24) || branch_offset >= (1 << 24))
17752 BFD_ASSERT (0 && "Error: branch out of range. Cannot create branch.");
17753
17754 bfd_vma patched_inst = 0xf0009000
17755 | s << 26 /* S. */
17756 | (((unsigned long) (branch_offset) >> 12) & 0x3ff) << 16 /* imm10. */
17757 | j1 << 13 /* J1. */
17758 | j2 << 11 /* J2. */
17759 | (((unsigned long) (branch_offset) >> 1) & 0x7ff); /* imm11. */
17760
17761 return patched_inst;
17762}
17763
17764static inline bfd_vma
17765create_instruction_ldmia (int base_reg, int wback, int reg_mask)
17766{
17767 /* A8.8.57 LDM/LDMIA/LDMFD (A8-396)
17768 LDMIA Rn!, {Ra, Rb, Rc, ...} (Encoding T2). */
17769 bfd_vma patched_inst = 0xe8900000
17770 | (/*W=*/wback << 21)
17771 | (base_reg << 16)
17772 | (reg_mask & 0x0000ffff);
17773
17774 return patched_inst;
17775}
17776
17777static inline bfd_vma
17778create_instruction_ldmdb (int base_reg, int wback, int reg_mask)
17779{
17780 /* A8.8.60 LDMDB/LDMEA (A8-402)
17781 LDMDB Rn!, {Ra, Rb, Rc, ...} (Encoding T1). */
17782 bfd_vma patched_inst = 0xe9100000
17783 | (/*W=*/wback << 21)
17784 | (base_reg << 16)
17785 | (reg_mask & 0x0000ffff);
17786
17787 return patched_inst;
17788}
17789
17790static inline bfd_vma
17791create_instruction_mov (int target_reg, int source_reg)
17792{
17793 /* A8.8.103 MOV (register) (A8-486)
17794 MOV Rd, Rm (Encoding T1). */
17795 bfd_vma patched_inst = 0x4600
17796 | (target_reg & 0x7)
17797 | ((target_reg & 0x8) >> 3) << 7
17798 | (source_reg << 3);
17799
17800 return patched_inst;
17801}
17802
17803static inline bfd_vma
17804create_instruction_sub (int target_reg, int source_reg, int value)
17805{
17806 /* A8.8.221 SUB (immediate) (A8-708)
17807 SUB Rd, Rn, #value (Encoding T3). */
17808 bfd_vma patched_inst = 0xf1a00000
17809 | (target_reg << 8)
17810 | (source_reg << 16)
17811 | (/*S=*/0 << 20)
17812 | ((value & 0x800) >> 11) << 26
17813 | ((value & 0x700) >> 8) << 12
17814 | (value & 0x0ff);
17815
17816 return patched_inst;
17817}
17818
17819static inline bfd_vma
9239bbd3 17820create_instruction_vldmia (int base_reg, int is_dp, int wback, int num_words,
a504d23a
LA		 17821 int first_reg)
17822{
17823 /* A8.8.332 VLDM (A8-922)
9239bbd3
CM		 17824 VLMD{MODE} Rn{!}, {list} (Encoding T1 or T2). */
17825 bfd_vma patched_inst = (is_dp ? 0xec900b00 : 0xec900a00)
a504d23a
LA		 17826 | (/*W=*/wback << 21)
17827 | (base_reg << 16)
9239bbd3
CM		 17828 | (num_words & 0x000000ff)
17829 | (((unsigned)first_reg >> 1) & 0x0000000f) << 12
a504d23a
LA		 17830 | (first_reg & 0x00000001) << 22;
17831
17832 return patched_inst;
17833}
17834
17835static inline bfd_vma
9239bbd3
CM		 17836create_instruction_vldmdb (int base_reg, int is_dp, int num_words,
17837 int first_reg)
a504d23a
LA		 17838{
17839 /* A8.8.332 VLDM (A8-922)
9239bbd3
CM		 17840 VLMD{MODE} Rn!, {} (Encoding T1 or T2). */
17841 bfd_vma patched_inst = (is_dp ? 0xed300b00 : 0xed300a00)
a504d23a 17842 | (base_reg << 16)
9239bbd3
CM		 17843 | (num_words & 0x000000ff)
17844 | (((unsigned)first_reg >>1 ) & 0x0000000f) << 12
a504d23a
LA		 17845 | (first_reg & 0x00000001) << 22;
17846
17847 return patched_inst;
17848}
17849
17850static inline bfd_vma
17851create_instruction_udf_w (int value)
17852{
17853 /* A8.8.247 UDF (A8-758)
17854 Undefined (Encoding T2). */
17855 bfd_vma patched_inst = 0xf7f0a000
17856 | (value & 0x00000fff)
17857 | (value & 0x000f0000) << 16;
17858
17859 return patched_inst;
17860}
17861
17862static inline bfd_vma
17863create_instruction_udf (int value)
17864{
17865 /* A8.8.247 UDF (A8-758)
17866 Undefined (Encoding T1). */
17867 bfd_vma patched_inst = 0xde00
17868 | (value & 0xff);
17869
17870 return patched_inst;
17871}
17872
17873/* Functions writing an instruction in memory, returning the next
17874 memory position to write to. */
17875
17876static inline bfd_byte *
17877push_thumb2_insn32 (struct elf32_arm_link_hash_table * htab,
17878 bfd * output_bfd, bfd_byte *pt, insn32 insn)
17879{
17880 put_thumb2_insn (htab, output_bfd, insn, pt);
17881 return pt + 4;
17882}
17883
17884static inline bfd_byte *
17885push_thumb2_insn16 (struct elf32_arm_link_hash_table * htab,
17886 bfd * output_bfd, bfd_byte *pt, insn32 insn)
17887{
17888 put_thumb_insn (htab, output_bfd, insn, pt);
17889 return pt + 2;
17890}
17891
17892/* Function filling up a region in memory with T1 and T2 UDFs taking
17893 care of alignment. */
17894
17895static bfd_byte *
17896stm32l4xx_fill_stub_udf (struct elf32_arm_link_hash_table * htab,
17897 bfd * output_bfd,
17898 const bfd_byte * const base_stub_contents,
17899 bfd_byte * const from_stub_contents,
17900 const bfd_byte * const end_stub_contents)
17901{
17902 bfd_byte *current_stub_contents = from_stub_contents;
17903
17904 /* Fill the remaining of the stub with deterministic contents : UDF
17905 instructions.
17906 Check if realignment is needed on modulo 4 frontier using T1, to
17907 further use T2. */
17908 if ((current_stub_contents < end_stub_contents)
17909 && !((current_stub_contents - base_stub_contents) % 2)
17910 && ((current_stub_contents - base_stub_contents) % 4))
17911 current_stub_contents =
17912 push_thumb2_insn16 (htab, output_bfd, current_stub_contents,
17913 create_instruction_udf (0));
17914
17915 for (; current_stub_contents < end_stub_contents;)
17916 current_stub_contents =
17917 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
17918 create_instruction_udf_w (0));
17919
17920 return current_stub_contents;
17921}
17922
17923/* Functions writing the stream of instructions equivalent to the
17924 derived sequence for ldmia, ldmdb, vldm respectively. */
17925
17926static void
17927stm32l4xx_create_replacing_stub_ldmia (struct elf32_arm_link_hash_table * htab,
17928 bfd * output_bfd,
17929 const insn32 initial_insn,
17930 const bfd_byte *const initial_insn_addr,
17931 bfd_byte *const base_stub_contents)
17932{
17933 int wback = (initial_insn & 0x00200000) >> 21;
17934 int ri, rn = (initial_insn & 0x000F0000) >> 16;
17935 int insn_all_registers = initial_insn & 0x0000ffff;
17936 int insn_low_registers, insn_high_registers;
17937 int usable_register_mask;
b25e998d 17938 int nb_registers = elf32_arm_popcount (insn_all_registers);
a504d23a
LA		 17939 int restore_pc = (insn_all_registers & (1 << 15)) ? 1 : 0;
17940 int restore_rn = (insn_all_registers & (1 << rn)) ? 1 : 0;
17941 bfd_byte *current_stub_contents = base_stub_contents;
17942
17943 BFD_ASSERT (is_thumb2_ldmia (initial_insn));
17944
17945 /* In BFD_ARM_STM32L4XX_FIX_ALL mode we may have to deal with
17946 smaller than 8 registers load sequences that do not cause the
17947 hardware issue. */
17948 if (nb_registers <= 8)
17949 {
17950 /* UNTOUCHED : LDMIA Rn{!}, {R-all-register-list}. */
17951 current_stub_contents =
17952 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
17953 initial_insn);
17954
17955 /* B initial_insn_addr+4. */
17956 if (!restore_pc)
17957 current_stub_contents =
17958 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
17959 create_instruction_branch_absolute
82188b29 17960 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 17961
17962 /* Fill the remaining of the stub with deterministic contents. */
17963 current_stub_contents =
17964 stm32l4xx_fill_stub_udf (htab, output_bfd,
17965 base_stub_contents, current_stub_contents,
17966 base_stub_contents +
17967 STM32L4XX_ERRATUM_LDM_VENEER_SIZE);
17968
17969 return;
17970 }
17971
17972 /* - reg_list[13] == 0. */
17973 BFD_ASSERT ((insn_all_registers & (1 << 13))==0);
17974
17975 /* - reg_list[14] & reg_list[15] != 1. */
17976 BFD_ASSERT ((insn_all_registers & 0xC000) != 0xC000);
17977
17978 /* - if (wback==1) reg_list[rn] == 0. */
17979 BFD_ASSERT (!wback || !restore_rn);
17980
17981 /* - nb_registers > 8. */
b25e998d 17982 BFD_ASSERT (elf32_arm_popcount (insn_all_registers) > 8);
a504d23a
LA		 17983
17984 /* At this point, LDMxx initial insn loads between 9 and 14 registers. */
17985
17986 /* In the following algorithm, we split this wide LDM using 2 LDM insns:
17987 - One with the 7 lowest registers (register mask 0x007F)
17988 This LDM will finally contain between 2 and 7 registers
17989 - One with the 7 highest registers (register mask 0xDF80)
17990 This ldm will finally contain between 2 and 7 registers. */
17991 insn_low_registers = insn_all_registers & 0x007F;
17992 insn_high_registers = insn_all_registers & 0xDF80;
17993
17994 /* A spare register may be needed during this veneer to temporarily
17995 handle the base register. This register will be restored with the
17996 last LDM operation.
17997 The usable register may be any general purpose register (that
17998 excludes PC, SP, LR : register mask is 0x1FFF). */
17999 usable_register_mask = 0x1FFF;
18000
18001 /* Generate the stub function. */
18002 if (wback)
18003 {
18004 /* LDMIA Rn!, {R-low-register-list} : (Encoding T2). */
18005 current_stub_contents =
18006 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18007 create_instruction_ldmia
18008 (rn, /*wback=*/1, insn_low_registers));
18009
18010 /* LDMIA Rn!, {R-high-register-list} : (Encoding T2). */
18011 current_stub_contents =
18012 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18013 create_instruction_ldmia
18014 (rn, /*wback=*/1, insn_high_registers));
18015 if (!restore_pc)
18016 {
18017 /* B initial_insn_addr+4. */
18018 current_stub_contents =
18019 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18020 create_instruction_branch_absolute
82188b29 18021 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 18022 }
18023 }
18024 else /* if (!wback). */
18025 {
18026 ri = rn;
18027
18028 /* If Rn is not part of the high-register-list, move it there. */
18029 if (!(insn_high_registers & (1 << rn)))
18030 {
18031 /* Choose a Ri in the high-register-list that will be restored. */
18032 ri = ctz (insn_high_registers & usable_register_mask & ~(1 << rn));
18033
18034 /* MOV Ri, Rn. */
18035 current_stub_contents =
18036 push_thumb2_insn16 (htab, output_bfd, current_stub_contents,
18037 create_instruction_mov (ri, rn));
18038 }
18039
18040 /* LDMIA Ri!, {R-low-register-list} : (Encoding T2). */
18041 current_stub_contents =
18042 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18043 create_instruction_ldmia
18044 (ri, /*wback=*/1, insn_low_registers));
18045
18046 /* LDMIA Ri, {R-high-register-list} : (Encoding T2). */
18047 current_stub_contents =
18048 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18049 create_instruction_ldmia
18050 (ri, /*wback=*/0, insn_high_registers));
18051
18052 if (!restore_pc)
18053 {
18054 /* B initial_insn_addr+4. */
18055 current_stub_contents =
18056 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18057 create_instruction_branch_absolute
82188b29 18058 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 18059 }
18060 }
18061
18062 /* Fill the remaining of the stub with deterministic contents. */
18063 current_stub_contents =
18064 stm32l4xx_fill_stub_udf (htab, output_bfd,
18065 base_stub_contents, current_stub_contents,
18066 base_stub_contents +
18067 STM32L4XX_ERRATUM_LDM_VENEER_SIZE);
18068}
18069
18070static void
18071stm32l4xx_create_replacing_stub_ldmdb (struct elf32_arm_link_hash_table * htab,
18072 bfd * output_bfd,
18073 const insn32 initial_insn,
18074 const bfd_byte *const initial_insn_addr,
18075 bfd_byte *const base_stub_contents)
18076{
18077 int wback = (initial_insn & 0x00200000) >> 21;
18078 int ri, rn = (initial_insn & 0x000f0000) >> 16;
18079 int insn_all_registers = initial_insn & 0x0000ffff;
18080 int insn_low_registers, insn_high_registers;
18081 int usable_register_mask;
18082 int restore_pc = (insn_all_registers & (1 << 15)) ? 1 : 0;
18083 int restore_rn = (insn_all_registers & (1 << rn)) ? 1 : 0;
b25e998d 18084 int nb_registers = elf32_arm_popcount (insn_all_registers);
a504d23a
LA		 18085 bfd_byte *current_stub_contents = base_stub_contents;
18086
18087 BFD_ASSERT (is_thumb2_ldmdb (initial_insn));
18088
18089 /* In BFD_ARM_STM32L4XX_FIX_ALL mode we may have to deal with
18090 smaller than 8 registers load sequences that do not cause the
18091 hardware issue. */
18092 if (nb_registers <= 8)
18093 {
18094 /* UNTOUCHED : LDMIA Rn{!}, {R-all-register-list}. */
18095 current_stub_contents =
18096 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18097 initial_insn);
18098
18099 /* B initial_insn_addr+4. */
18100 current_stub_contents =
18101 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18102 create_instruction_branch_absolute
82188b29 18103 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 18104
18105 /* Fill the remaining of the stub with deterministic contents. */
18106 current_stub_contents =
18107 stm32l4xx_fill_stub_udf (htab, output_bfd,
18108 base_stub_contents, current_stub_contents,
18109 base_stub_contents +
18110 STM32L4XX_ERRATUM_LDM_VENEER_SIZE);
18111
18112 return;
18113 }
18114
18115 /* - reg_list[13] == 0. */
18116 BFD_ASSERT ((insn_all_registers & (1 << 13)) == 0);
18117
18118 /* - reg_list[14] & reg_list[15] != 1. */
18119 BFD_ASSERT ((insn_all_registers & 0xC000) != 0xC000);
18120
18121 /* - if (wback==1) reg_list[rn] == 0. */
18122 BFD_ASSERT (!wback || !restore_rn);
18123
18124 /* - nb_registers > 8. */
b25e998d 18125 BFD_ASSERT (elf32_arm_popcount (insn_all_registers) > 8);
a504d23a
LA		 18126
18127 /* At this point, LDMxx initial insn loads between 9 and 14 registers. */
18128
18129 /* In the following algorithm, we split this wide LDM using 2 LDM insn:
18130 - One with the 7 lowest registers (register mask 0x007F)
18131 This LDM will finally contain between 2 and 7 registers
18132 - One with the 7 highest registers (register mask 0xDF80)
18133 This ldm will finally contain between 2 and 7 registers. */
18134 insn_low_registers = insn_all_registers & 0x007F;
18135 insn_high_registers = insn_all_registers & 0xDF80;
18136
18137 /* A spare register may be needed during this veneer to temporarily
18138 handle the base register. This register will be restored with
18139 the last LDM operation.
18140 The usable register may be any general purpose register (that excludes
18141 PC, SP, LR : register mask is 0x1FFF). */
18142 usable_register_mask = 0x1FFF;
18143
18144 /* Generate the stub function. */
18145 if (!wback && !restore_pc && !restore_rn)
18146 {
18147 /* Choose a Ri in the low-register-list that will be restored. */
18148 ri = ctz (insn_low_registers & usable_register_mask & ~(1 << rn));
18149
18150 /* MOV Ri, Rn. */
18151 current_stub_contents =
18152 push_thumb2_insn16 (htab, output_bfd, current_stub_contents,
18153 create_instruction_mov (ri, rn));
18154
18155 /* LDMDB Ri!, {R-high-register-list}. */
18156 current_stub_contents =
18157 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18158 create_instruction_ldmdb
18159 (ri, /*wback=*/1, insn_high_registers));
18160
18161 /* LDMDB Ri, {R-low-register-list}. */
18162 current_stub_contents =
18163 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18164 create_instruction_ldmdb
18165 (ri, /*wback=*/0, insn_low_registers));
18166
18167 /* B initial_insn_addr+4. */
18168 current_stub_contents =
18169 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18170 create_instruction_branch_absolute
82188b29 18171 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 18172 }
18173 else if (wback && !restore_pc && !restore_rn)
18174 {
18175 /* LDMDB Rn!, {R-high-register-list}. */
18176 current_stub_contents =
18177 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18178 create_instruction_ldmdb
18179 (rn, /*wback=*/1, insn_high_registers));
18180
18181 /* LDMDB Rn!, {R-low-register-list}. */
18182 current_stub_contents =
18183 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18184 create_instruction_ldmdb
18185 (rn, /*wback=*/1, insn_low_registers));
18186
18187 /* B initial_insn_addr+4. */
18188 current_stub_contents =
18189 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18190 create_instruction_branch_absolute
82188b29 18191 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 18192 }
18193 else if (!wback && restore_pc && !restore_rn)
18194 {
18195 /* Choose a Ri in the high-register-list that will be restored. */
18196 ri = ctz (insn_high_registers & usable_register_mask & ~(1 << rn));
18197
18198 /* SUB Ri, Rn, #(4*nb_registers). */
18199 current_stub_contents =
18200 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18201 create_instruction_sub (ri, rn, (4 * nb_registers)));
18202
18203 /* LDMIA Ri!, {R-low-register-list}. */
18204 current_stub_contents =
18205 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18206 create_instruction_ldmia
18207 (ri, /*wback=*/1, insn_low_registers));
18208
18209 /* LDMIA Ri, {R-high-register-list}. */
18210 current_stub_contents =
18211 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18212 create_instruction_ldmia
18213 (ri, /*wback=*/0, insn_high_registers));
18214 }
18215 else if (wback && restore_pc && !restore_rn)
18216 {
18217 /* Choose a Ri in the high-register-list that will be restored. */
18218 ri = ctz (insn_high_registers & usable_register_mask & ~(1 << rn));
18219
18220 /* SUB Rn, Rn, #(4*nb_registers) */
18221 current_stub_contents =
18222 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18223 create_instruction_sub (rn, rn, (4 * nb_registers)));
18224
18225 /* MOV Ri, Rn. */
18226 current_stub_contents =
18227 push_thumb2_insn16 (htab, output_bfd, current_stub_contents,
18228 create_instruction_mov (ri, rn));
18229
18230 /* LDMIA Ri!, {R-low-register-list}. */
18231 current_stub_contents =
18232 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18233 create_instruction_ldmia
18234 (ri, /*wback=*/1, insn_low_registers));
18235
18236 /* LDMIA Ri, {R-high-register-list}. */
18237 current_stub_contents =
18238 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18239 create_instruction_ldmia
18240 (ri, /*wback=*/0, insn_high_registers));
18241 }
18242 else if (!wback && !restore_pc && restore_rn)
18243 {
18244 ri = rn;
18245 if (!(insn_low_registers & (1 << rn)))
18246 {
18247 /* Choose a Ri in the low-register-list that will be restored. */
18248 ri = ctz (insn_low_registers & usable_register_mask & ~(1 << rn));
18249
18250 /* MOV Ri, Rn. */
18251 current_stub_contents =
18252 push_thumb2_insn16 (htab, output_bfd, current_stub_contents,
18253 create_instruction_mov (ri, rn));
18254 }
18255
18256 /* LDMDB Ri!, {R-high-register-list}. */
18257 current_stub_contents =
18258 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18259 create_instruction_ldmdb
18260 (ri, /*wback=*/1, insn_high_registers));
18261
18262 /* LDMDB Ri, {R-low-register-list}. */
18263 current_stub_contents =
18264 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18265 create_instruction_ldmdb
18266 (ri, /*wback=*/0, insn_low_registers));
18267
18268 /* B initial_insn_addr+4. */
18269 current_stub_contents =
18270 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18271 create_instruction_branch_absolute
82188b29 18272 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 18273 }
18274 else if (!wback && restore_pc && restore_rn)
18275 {
18276 ri = rn;
18277 if (!(insn_high_registers & (1 << rn)))
18278 {
18279 /* Choose a Ri in the high-register-list that will be restored. */
18280 ri = ctz (insn_high_registers & usable_register_mask & ~(1 << rn));
18281 }
18282
18283 /* SUB Ri, Rn, #(4*nb_registers). */
18284 current_stub_contents =
18285 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18286 create_instruction_sub (ri, rn, (4 * nb_registers)));
18287
18288 /* LDMIA Ri!, {R-low-register-list}. */
18289 current_stub_contents =
18290 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18291 create_instruction_ldmia
18292 (ri, /*wback=*/1, insn_low_registers));
18293
18294 /* LDMIA Ri, {R-high-register-list}. */
18295 current_stub_contents =
18296 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18297 create_instruction_ldmia
18298 (ri, /*wback=*/0, insn_high_registers));
18299 }
18300 else if (wback && restore_rn)
18301 {
18302 /* The assembler should not have accepted to encode this. */
18303 BFD_ASSERT (0 && "Cannot patch an instruction that has an "
18304 "undefined behavior.\n");
18305 }
18306
18307 /* Fill the remaining of the stub with deterministic contents. */
18308 current_stub_contents =
18309 stm32l4xx_fill_stub_udf (htab, output_bfd,
18310 base_stub_contents, current_stub_contents,
18311 base_stub_contents +
18312 STM32L4XX_ERRATUM_LDM_VENEER_SIZE);
18313
18314}
18315
18316static void
18317stm32l4xx_create_replacing_stub_vldm (struct elf32_arm_link_hash_table * htab,
18318 bfd * output_bfd,
18319 const insn32 initial_insn,
18320 const bfd_byte *const initial_insn_addr,
18321 bfd_byte *const base_stub_contents)
18322{
9239bbd3 18323 int num_words = ((unsigned int) initial_insn << 24) >> 24;
a504d23a
LA		 18324 bfd_byte *current_stub_contents = base_stub_contents;
18325
18326 BFD_ASSERT (is_thumb2_vldm (initial_insn));
18327
18328 /* In BFD_ARM_STM32L4XX_FIX_ALL mode we may have to deal with
9239bbd3 18329 smaller than 8 words load sequences that do not cause the
a504d23a 18330 hardware issue. */
9239bbd3 18331 if (num_words <= 8)
a504d23a
LA		 18332 {
18333 /* Untouched instruction. */
18334 current_stub_contents =
18335 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18336 initial_insn);
18337
18338 /* B initial_insn_addr+4. */
18339 current_stub_contents =
18340 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18341 create_instruction_branch_absolute
82188b29 18342 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 18343 }
18344 else
18345 {
9eaff861 18346 bfd_boolean is_dp = /* DP encoding. */
9239bbd3 18347 (initial_insn & 0xfe100f00) == 0xec100b00;
a504d23a
LA		 18348 bfd_boolean is_ia_nobang = /* (IA without !). */
18349 (((initial_insn << 7) >> 28) & 0xd) == 0x4;
18350 bfd_boolean is_ia_bang = /* (IA with !) - includes VPOP. */
18351 (((initial_insn << 7) >> 28) & 0xd) == 0x5;
18352 bfd_boolean is_db_bang = /* (DB with !). */
18353 (((initial_insn << 7) >> 28) & 0xd) == 0x9;
9239bbd3 18354 int base_reg = ((unsigned int) initial_insn << 12) >> 28;
a504d23a 18355 /* d = UInt (Vd:D);. */
9239bbd3 18356 int first_reg = ((((unsigned int) initial_insn << 16) >> 28) << 1)
a504d23a
LA		 18357 | (((unsigned int)initial_insn << 9) >> 31);
18358
9239bbd3
CM		 18359 /* Compute the number of 8-words chunks needed to split. */
18360 int chunks = (num_words % 8) ? (num_words / 8 + 1) : (num_words / 8);
a504d23a
LA		 18361 int chunk;
18362
18363 /* The test coverage has been done assuming the following
18364 hypothesis that exactly one of the previous is_ predicates is
18365 true. */
9239bbd3
CM		 18366 BFD_ASSERT ( (is_ia_nobang ^ is_ia_bang ^ is_db_bang)
18367 && !(is_ia_nobang & is_ia_bang & is_db_bang));
a504d23a 18368
9239bbd3 18369 /* We treat the cutting of the words in one pass for all
a504d23a
LA		 18370 cases, then we emit the adjustments:
18371
18372 vldm rx, {...}
18373 -> vldm rx!, {8_words_or_less} for each needed 8_word
18374 -> sub rx, rx, #size (list)
18375
18376 vldm rx!, {...}
18377 -> vldm rx!, {8_words_or_less} for each needed 8_word
18378 This also handles vpop instruction (when rx is sp)
18379
18380 vldmd rx!, {...}
18381 -> vldmb rx!, {8_words_or_less} for each needed 8_word. */
9239bbd3 18382 for (chunk = 0; chunk < chunks; ++chunk)
a504d23a 18383 {
9239bbd3
CM		 18384 bfd_vma new_insn = 0;
18385
a504d23a
LA		 18386 if (is_ia_nobang || is_ia_bang)
18387 {
9239bbd3
CM		 18388 new_insn = create_instruction_vldmia
18389 (base_reg,
18390 is_dp,
18391 /*wback= . */1,
18392 chunks - (chunk + 1) ?
18393 8 : num_words - chunk * 8,
18394 first_reg + chunk * 8);
a504d23a
LA		 18395 }
18396 else if (is_db_bang)
18397 {
9239bbd3
CM		 18398 new_insn = create_instruction_vldmdb
18399 (base_reg,
18400 is_dp,
18401 chunks - (chunk + 1) ?
18402 8 : num_words - chunk * 8,
18403 first_reg + chunk * 8);
a504d23a 18404 }
9239bbd3
CM		 18405
18406 if (new_insn)
18407 current_stub_contents =
18408 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18409 new_insn);
a504d23a
LA		 18410 }
18411
18412 /* Only this case requires the base register compensation
18413 subtract. */
18414 if (is_ia_nobang)
18415 {
18416 current_stub_contents =
18417 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18418 create_instruction_sub
9239bbd3 18419 (base_reg, base_reg, 4*num_words));
a504d23a
LA		 18420 }
18421
18422 /* B initial_insn_addr+4. */
18423 current_stub_contents =
18424 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18425 create_instruction_branch_absolute
82188b29 18426 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 18427 }
18428
18429 /* Fill the remaining of the stub with deterministic contents. */
18430 current_stub_contents =
18431 stm32l4xx_fill_stub_udf (htab, output_bfd,
18432 base_stub_contents, current_stub_contents,
18433 base_stub_contents +
18434 STM32L4XX_ERRATUM_VLDM_VENEER_SIZE);
18435}
18436
18437static void
18438stm32l4xx_create_replacing_stub (struct elf32_arm_link_hash_table * htab,
18439 bfd * output_bfd,
18440 const insn32 wrong_insn,
18441 const bfd_byte *const wrong_insn_addr,
18442 bfd_byte *const stub_contents)
18443{
18444 if (is_thumb2_ldmia (wrong_insn))
18445 stm32l4xx_create_replacing_stub_ldmia (htab, output_bfd,
18446 wrong_insn, wrong_insn_addr,
18447 stub_contents);
18448 else if (is_thumb2_ldmdb (wrong_insn))
18449 stm32l4xx_create_replacing_stub_ldmdb (htab, output_bfd,
18450 wrong_insn, wrong_insn_addr,
18451 stub_contents);
18452 else if (is_thumb2_vldm (wrong_insn))
18453 stm32l4xx_create_replacing_stub_vldm (htab, output_bfd,
18454 wrong_insn, wrong_insn_addr,
18455 stub_contents);
18456}
18457
18458/* End of stm32l4xx work-around. */
18459
18460
e489d0ae
PB		 18461/* Do code byteswapping. Return FALSE afterwards so that the section is
18462 written out as normal. */
18463
18464static bfd_boolean
c7b8f16e 18465elf32_arm_write_section (bfd *output_bfd,
8029a119
NC		 18466 struct bfd_link_info *link_info,
18467 asection *sec,
e489d0ae
PB		 18468 bfd_byte *contents)
18469{
48229727 18470 unsigned int mapcount, errcount;
8e3de13a 18471 _arm_elf_section_data *arm_data;
c7b8f16e 18472 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (link_info);
e489d0ae 18473 elf32_arm_section_map *map;
c7b8f16e 18474 elf32_vfp11_erratum_list *errnode;
a504d23a 18475 elf32_stm32l4xx_erratum_list *stm32l4xx_errnode;
e489d0ae
PB		 18476 bfd_vma ptr;
18477 bfd_vma end;
c7b8f16e 18478 bfd_vma offset = sec->output_section->vma + sec->output_offset;
e489d0ae 18479 bfd_byte tmp;
48229727 18480 unsigned int i;
57e8b36a 18481
4dfe6ac6
NC		 18482 if (globals == NULL)
18483 return FALSE;
18484
8e3de13a
NC		 18485 /* If this section has not been allocated an _arm_elf_section_data
18486 structure then we cannot record anything. */
18487 arm_data = get_arm_elf_section_data (sec);
18488 if (arm_data == NULL)
18489 return FALSE;
18490
18491 mapcount = arm_data->mapcount;
18492 map = arm_data->map;
c7b8f16e
JB		 18493 errcount = arm_data->erratumcount;
18494
18495 if (errcount != 0)
18496 {
18497 unsigned int endianflip = bfd_big_endian (output_bfd) ? 3 : 0;
18498
18499 for (errnode = arm_data->erratumlist; errnode != 0;
99059e56
RM		 18500 errnode = errnode->next)
18501 {
18502 bfd_vma target = errnode->vma - offset;
18503
18504 switch (errnode->type)
18505 {
18506 case VFP11_ERRATUM_BRANCH_TO_ARM_VENEER:
18507 {
18508 bfd_vma branch_to_veneer;
18509 /* Original condition code of instruction, plus bit mask for
18510 ARM B instruction. */
18511 unsigned int insn = (errnode->u.b.vfp_insn & 0xf0000000)
18512 | 0x0a000000;
c7b8f16e
JB		 18513
18514 /* The instruction is before the label. */
91d6fa6a 18515 target -= 4;
c7b8f16e
JB		 18516
18517 /* Above offset included in -4 below. */
18518 branch_to_veneer = errnode->u.b.veneer->vma
99059e56 18519 - errnode->vma - 4;
c7b8f16e
JB		 18520
18521 if ((signed) branch_to_veneer < -(1 << 25)
18522 || (signed) branch_to_veneer >= (1 << 25))
4eca0228
AM		 18523 _bfd_error_handler (_("%B: error: VFP11 veneer out of "
18524 "range"), output_bfd);
c7b8f16e 18525
99059e56
RM		 18526 insn |= (branch_to_veneer >> 2) & 0xffffff;
18527 contents[endianflip ^ target] = insn & 0xff;
18528 contents[endianflip ^ (target + 1)] = (insn >> 8) & 0xff;
18529 contents[endianflip ^ (target + 2)] = (insn >> 16) & 0xff;
18530 contents[endianflip ^ (target + 3)] = (insn >> 24) & 0xff;
18531 }
18532 break;
c7b8f16e
JB		 18533
18534 case VFP11_ERRATUM_ARM_VENEER:
99059e56
RM		 18535 {
18536 bfd_vma branch_from_veneer;
18537 unsigned int insn;
c7b8f16e 18538
99059e56
RM		 18539 /* Take size of veneer into account. */
18540 branch_from_veneer = errnode->u.v.branch->vma
18541 - errnode->vma - 12;
c7b8f16e
JB		 18542
18543 if ((signed) branch_from_veneer < -(1 << 25)
18544 || (signed) branch_from_veneer >= (1 << 25))
4eca0228
AM		 18545 _bfd_error_handler (_("%B: error: VFP11 veneer out of "
18546 "range"), output_bfd);
c7b8f16e 18547
99059e56
RM		 18548 /* Original instruction. */
18549 insn = errnode->u.v.branch->u.b.vfp_insn;
18550 contents[endianflip ^ target] = insn & 0xff;
18551 contents[endianflip ^ (target + 1)] = (insn >> 8) & 0xff;
18552 contents[endianflip ^ (target + 2)] = (insn >> 16) & 0xff;
18553 contents[endianflip ^ (target + 3)] = (insn >> 24) & 0xff;
18554
18555 /* Branch back to insn after original insn. */
18556 insn = 0xea000000 | ((branch_from_veneer >> 2) & 0xffffff);
18557 contents[endianflip ^ (target + 4)] = insn & 0xff;
18558 contents[endianflip ^ (target + 5)] = (insn >> 8) & 0xff;
18559 contents[endianflip ^ (target + 6)] = (insn >> 16) & 0xff;
18560 contents[endianflip ^ (target + 7)] = (insn >> 24) & 0xff;
18561 }
18562 break;
c7b8f16e 18563
99059e56
RM		 18564 default:
18565 abort ();
18566 }
18567 }
c7b8f16e 18568 }
e489d0ae 18569
a504d23a
LA		 18570 if (arm_data->stm32l4xx_erratumcount != 0)
18571 {
18572 for (stm32l4xx_errnode = arm_data->stm32l4xx_erratumlist;
18573 stm32l4xx_errnode != 0;
18574 stm32l4xx_errnode = stm32l4xx_errnode->next)
18575 {
18576 bfd_vma target = stm32l4xx_errnode->vma - offset;
18577
18578 switch (stm32l4xx_errnode->type)
18579 {
18580 case STM32L4XX_ERRATUM_BRANCH_TO_VENEER:
18581 {
18582 unsigned int insn;
18583 bfd_vma branch_to_veneer =
18584 stm32l4xx_errnode->u.b.veneer->vma - stm32l4xx_errnode->vma;
18585
18586 if ((signed) branch_to_veneer < -(1 << 24)
18587 || (signed) branch_to_veneer >= (1 << 24))
18588 {
18589 bfd_vma out_of_range =
18590 ((signed) branch_to_veneer < -(1 << 24)) ?
18591 - branch_to_veneer - (1 << 24) :
18592 ((signed) branch_to_veneer >= (1 << 24)) ?
18593 branch_to_veneer - (1 << 24) : 0;
18594
4eca0228 18595 _bfd_error_handler
a504d23a 18596 (_("%B(%#x): error: Cannot create STM32L4XX veneer. "
eee926f2 18597 "Jump out of range by %ld bytes. "
a504d23a
LA		 18598 "Cannot encode branch instruction. "),
18599 output_bfd,
eee926f2 18600 (long) (stm32l4xx_errnode->vma - 4),
a504d23a
LA		 18601 out_of_range);
18602 continue;
18603 }
18604
18605 insn = create_instruction_branch_absolute
82188b29 18606 (stm32l4xx_errnode->u.b.veneer->vma - stm32l4xx_errnode->vma);
a504d23a
LA		 18607
18608 /* The instruction is before the label. */
18609 target -= 4;
18610
18611 put_thumb2_insn (globals, output_bfd,
18612 (bfd_vma) insn, contents + target);
18613 }
18614 break;
18615
18616 case STM32L4XX_ERRATUM_VENEER:
18617 {
82188b29
NC		 18618 bfd_byte * veneer;
18619 bfd_byte * veneer_r;
a504d23a
LA		 18620 unsigned int insn;
18621
82188b29
NC		 18622 veneer = contents + target;
18623 veneer_r = veneer
18624 + stm32l4xx_errnode->u.b.veneer->vma
18625 - stm32l4xx_errnode->vma - 4;
a504d23a
LA		 18626
18627 if ((signed) (veneer_r - veneer -
18628 STM32L4XX_ERRATUM_VLDM_VENEER_SIZE >
18629 STM32L4XX_ERRATUM_LDM_VENEER_SIZE ?
18630 STM32L4XX_ERRATUM_VLDM_VENEER_SIZE :
18631 STM32L4XX_ERRATUM_LDM_VENEER_SIZE) < -(1 << 24)
18632 || (signed) (veneer_r - veneer) >= (1 << 24))
18633 {
4eca0228
AM		 18634 _bfd_error_handler (_("%B: error: Cannot create STM32L4XX "
18635 "veneer."), output_bfd);
a504d23a
LA		 18636 continue;
18637 }
18638
18639 /* Original instruction. */
18640 insn = stm32l4xx_errnode->u.v.branch->u.b.insn;
18641
18642 stm32l4xx_create_replacing_stub
18643 (globals, output_bfd, insn, (void*)veneer_r, (void*)veneer);
18644 }
18645 break;
18646
18647 default:
18648 abort ();
18649 }
18650 }
18651 }
18652
2468f9c9
PB		 18653 if (arm_data->elf.this_hdr.sh_type == SHT_ARM_EXIDX)
18654 {
18655 arm_unwind_table_edit *edit_node
99059e56 18656 = arm_data->u.exidx.unwind_edit_list;
2468f9c9 18657 /* Now, sec->size is the size of the section we will write. The original
99059e56 18658 size (before we merged duplicate entries and inserted EXIDX_CANTUNWIND
2468f9c9
PB		 18659 markers) was sec->rawsize. (This isn't the case if we perform no
18660 edits, then rawsize will be zero and we should use size). */
21d799b5 18661 bfd_byte *edited_contents = (bfd_byte *) bfd_malloc (sec->size);
2468f9c9
PB		 18662 unsigned int input_size = sec->rawsize ? sec->rawsize : sec->size;
18663 unsigned int in_index, out_index;
18664 bfd_vma add_to_offsets = 0;
18665
18666 for (in_index = 0, out_index = 0; in_index * 8 < input_size || edit_node;)
99059e56 18667 {
2468f9c9
PB		 18668 if (edit_node)
18669 {
18670 unsigned int edit_index = edit_node->index;
b38cadfb 18671
2468f9c9 18672 if (in_index < edit_index && in_index * 8 < input_size)
99059e56 18673 {
2468f9c9
PB		 18674 copy_exidx_entry (output_bfd, edited_contents + out_index * 8,
18675 contents + in_index * 8, add_to_offsets);
18676 out_index++;
18677 in_index++;
18678 }
18679 else if (in_index == edit_index
18680 || (in_index * 8 >= input_size
18681 && edit_index == UINT_MAX))
99059e56 18682 {
2468f9c9
PB		 18683 switch (edit_node->type)
18684 {
18685 case DELETE_EXIDX_ENTRY:
18686 in_index++;
18687 add_to_offsets += 8;
18688 break;
b38cadfb 18689
2468f9c9
PB		 18690 case INSERT_EXIDX_CANTUNWIND_AT_END:
18691 {
99059e56 18692 asection *text_sec = edit_node->linked_section;
2468f9c9
PB		 18693 bfd_vma text_offset = text_sec->output_section->vma
18694 + text_sec->output_offset
18695 + text_sec->size;
18696 bfd_vma exidx_offset = offset + out_index * 8;
99059e56 18697 unsigned long prel31_offset;
2468f9c9
PB		 18698
18699 /* Note: this is meant to be equivalent to an
18700 R_ARM_PREL31 relocation. These synthetic
18701 EXIDX_CANTUNWIND markers are not relocated by the
18702 usual BFD method. */
18703 prel31_offset = (text_offset - exidx_offset)
18704 & 0x7ffffffful;
491d01d3
YU		 18705 if (bfd_link_relocatable (link_info))
18706 {
18707 /* Here relocation for new EXIDX_CANTUNWIND is
18708 created, so there is no need to
18709 adjust offset by hand. */
18710 prel31_offset = text_sec->output_offset
18711 + text_sec->size;
491d01d3 18712 }
2468f9c9
PB		 18713
18714 /* First address we can't unwind. */
18715 bfd_put_32 (output_bfd, prel31_offset,
18716 &edited_contents[out_index * 8]);
18717
18718 /* Code for EXIDX_CANTUNWIND. */
18719 bfd_put_32 (output_bfd, 0x1,
18720 &edited_contents[out_index * 8 + 4]);
18721
18722 out_index++;
18723 add_to_offsets -= 8;
18724 }
18725 break;
18726 }
b38cadfb 18727
2468f9c9
PB		 18728 edit_node = edit_node->next;
18729 }
18730 }
18731 else
18732 {
18733 /* No more edits, copy remaining entries verbatim. */
18734 copy_exidx_entry (output_bfd, edited_contents + out_index * 8,
18735 contents + in_index * 8, add_to_offsets);
18736 out_index++;
18737 in_index++;
18738 }
18739 }
18740
18741 if (!(sec->flags & SEC_EXCLUDE) && !(sec->flags & SEC_NEVER_LOAD))
18742 bfd_set_section_contents (output_bfd, sec->output_section,
18743 edited_contents,
18744 (file_ptr) sec->output_offset, sec->size);
18745
18746 return TRUE;
18747 }
18748
48229727
JB		 18749 /* Fix code to point to Cortex-A8 erratum stubs. */
18750 if (globals->fix_cortex_a8)
18751 {
18752 struct a8_branch_to_stub_data data;
18753
18754 data.writing_section = sec;
18755 data.contents = contents;
18756
a504d23a
LA		 18757 bfd_hash_traverse (& globals->stub_hash_table, make_branch_to_a8_stub,
18758 & data);
48229727
JB		 18759 }
18760
e489d0ae
PB		 18761 if (mapcount == 0)
18762 return FALSE;
18763
c7b8f16e 18764 if (globals->byteswap_code)
e489d0ae 18765 {
c7b8f16e 18766 qsort (map, mapcount, sizeof (* map), elf32_arm_compare_mapping);
57e8b36a 18767
c7b8f16e
JB		 18768 ptr = map[0].vma;
18769 for (i = 0; i < mapcount; i++)
99059e56
RM		 18770 {
18771 if (i == mapcount - 1)
c7b8f16e 18772 end = sec->size;
99059e56
RM		 18773 else
18774 end = map[i + 1].vma;
e489d0ae 18775
99059e56 18776 switch (map[i].type)
e489d0ae 18777 {
c7b8f16e
JB		 18778 case 'a':
18779 /* Byte swap code words. */
18780 while (ptr + 3 < end)
99059e56
RM		 18781 {
18782 tmp = contents[ptr];
18783 contents[ptr] = contents[ptr + 3];
18784 contents[ptr + 3] = tmp;
18785 tmp = contents[ptr + 1];
18786 contents[ptr + 1] = contents[ptr + 2];
18787 contents[ptr + 2] = tmp;
18788 ptr += 4;
18789 }
c7b8f16e 18790 break;
e489d0ae 18791
c7b8f16e
JB		 18792 case 't':
18793 /* Byte swap code halfwords. */
18794 while (ptr + 1 < end)
99059e56
RM		 18795 {
18796 tmp = contents[ptr];
18797 contents[ptr] = contents[ptr + 1];
18798 contents[ptr + 1] = tmp;
18799 ptr += 2;
18800 }
c7b8f16e
JB		 18801 break;
18802
18803 case 'd':
18804 /* Leave data alone. */
18805 break;
18806 }
99059e56
RM		 18807 ptr = end;
18808 }
e489d0ae 18809 }
8e3de13a 18810
93204d3a 18811 free (map);
47b2e99c 18812 arm_data->mapcount = -1;
c7b8f16e 18813 arm_data->mapsize = 0;
8e3de13a 18814 arm_data->map = NULL;
8e3de13a 18815
e489d0ae
PB		 18816 return FALSE;
18817}
18818
0beaef2b
PB		 18819/* Mangle thumb function symbols as we read them in. */
18820
8384fb8f 18821static bfd_boolean
0beaef2b
PB		 18822elf32_arm_swap_symbol_in (bfd * abfd,
18823 const void *psrc,
18824 const void *pshn,
18825 Elf_Internal_Sym *dst)
18826{
4ba2ef8f
TP		 18827 Elf_Internal_Shdr *symtab_hdr;
18828 const char *name = NULL;
18829
8384fb8f
AM		 18830 if (!bfd_elf32_swap_symbol_in (abfd, psrc, pshn, dst))
18831 return FALSE;
39d911fc 18832 dst->st_target_internal = 0;
0beaef2b
PB		 18833
18834 /* New EABI objects mark thumb function symbols by setting the low bit of
35fc36a8 18835 the address. */
63e1a0fc
PB		 18836 if (ELF_ST_TYPE (dst->st_info) == STT_FUNC
18837 || ELF_ST_TYPE (dst->st_info) == STT_GNU_IFUNC)
0beaef2b 18838 {
63e1a0fc
PB		 18839 if (dst->st_value & 1)
18840 {
18841 dst->st_value &= ~(bfd_vma) 1;
39d911fc
TP		 18842 ARM_SET_SYM_BRANCH_TYPE (dst->st_target_internal,
18843 ST_BRANCH_TO_THUMB);
63e1a0fc
PB		 18844 }
18845 else
39d911fc 18846 ARM_SET_SYM_BRANCH_TYPE (dst->st_target_internal, ST_BRANCH_TO_ARM);
35fc36a8
RS		 18847 }
18848 else if (ELF_ST_TYPE (dst->st_info) == STT_ARM_TFUNC)
18849 {
18850 dst->st_info = ELF_ST_INFO (ELF_ST_BIND (dst->st_info), STT_FUNC);
39d911fc 18851 ARM_SET_SYM_BRANCH_TYPE (dst->st_target_internal, ST_BRANCH_TO_THUMB);
0beaef2b 18852 }
35fc36a8 18853 else if (ELF_ST_TYPE (dst->st_info) == STT_SECTION)
39d911fc 18854 ARM_SET_SYM_BRANCH_TYPE (dst->st_target_internal, ST_BRANCH_LONG);
35fc36a8 18855 else
39d911fc 18856 ARM_SET_SYM_BRANCH_TYPE (dst->st_target_internal, ST_BRANCH_UNKNOWN);
35fc36a8 18857
4ba2ef8f
TP		 18858 /* Mark CMSE special symbols. */
18859 symtab_hdr = & elf_symtab_hdr (abfd);
18860 if (symtab_hdr->sh_size)
18861 name = bfd_elf_sym_name (abfd, symtab_hdr, dst, NULL);
18862 if (name && CONST_STRNEQ (name, CMSE_PREFIX))
18863 ARM_SET_SYM_CMSE_SPCL (dst->st_target_internal);
18864
8384fb8f 18865 return TRUE;
0beaef2b
PB		 18866}
18867
18868
18869/* Mangle thumb function symbols as we write them out. */
18870
18871static void
18872elf32_arm_swap_symbol_out (bfd *abfd,
18873 const Elf_Internal_Sym *src,
18874 void *cdst,
18875 void *shndx)
18876{
18877 Elf_Internal_Sym newsym;
18878
18879 /* We convert STT_ARM_TFUNC symbols into STT_FUNC with the low bit
18880 of the address set, as per the new EABI. We do this unconditionally
18881 because objcopy does not set the elf header flags until after
18882 it writes out the symbol table. */
39d911fc 18883 if (ARM_GET_SYM_BRANCH_TYPE (src->st_target_internal) == ST_BRANCH_TO_THUMB)
0beaef2b
PB		 18884 {
18885 newsym = *src;
34e77a92
RS		 18886 if (ELF_ST_TYPE (src->st_info) != STT_GNU_IFUNC)
18887 newsym.st_info = ELF_ST_INFO (ELF_ST_BIND (src->st_info), STT_FUNC);
0fa3dcad 18888 if (newsym.st_shndx != SHN_UNDEF)
99059e56
RM		 18889 {
18890 /* Do this only for defined symbols. At link type, the static
18891 linker will simulate the work of dynamic linker of resolving
18892 symbols and will carry over the thumbness of found symbols to
18893 the output symbol table. It's not clear how it happens, but
18894 the thumbness of undefined symbols can well be different at
18895 runtime, and writing '1' for them will be confusing for users
18896 and possibly for dynamic linker itself.
18897 */
18898 newsym.st_value |= 1;
18899 }
906e58ca 18900
0beaef2b
PB		 18901 src = &newsym;
18902 }
18903 bfd_elf32_swap_symbol_out (abfd, src, cdst, shndx);
18904}
18905
b294bdf8
MM		 18906/* Add the PT_ARM_EXIDX program header. */
18907
18908static bfd_boolean
906e58ca 18909elf32_arm_modify_segment_map (bfd *abfd,
b294bdf8
MM		 18910 struct bfd_link_info *info ATTRIBUTE_UNUSED)
18911{
18912 struct elf_segment_map *m;
18913 asection *sec;
18914
18915 sec = bfd_get_section_by_name (abfd, ".ARM.exidx");
18916 if (sec != NULL && (sec->flags & SEC_LOAD) != 0)
18917 {
18918 /* If there is already a PT_ARM_EXIDX header, then we do not
18919 want to add another one. This situation arises when running
18920 "strip"; the input binary already has the header. */
12bd6957 18921 m = elf_seg_map (abfd);
b294bdf8
MM		 18922 while (m && m->p_type != PT_ARM_EXIDX)
18923 m = m->next;
18924 if (!m)
18925 {
21d799b5 18926 m = (struct elf_segment_map *)
99059e56 18927 bfd_zalloc (abfd, sizeof (struct elf_segment_map));
b294bdf8
MM		 18928 if (m == NULL)
18929 return FALSE;
18930 m->p_type = PT_ARM_EXIDX;
18931 m->count = 1;
18932 m->sections[0] = sec;
18933
12bd6957
AM		 18934 m->next = elf_seg_map (abfd);
18935 elf_seg_map (abfd) = m;
b294bdf8
MM		 18936 }
18937 }
18938
18939 return TRUE;
18940}
18941
18942/* We may add a PT_ARM_EXIDX program header. */
18943
18944static int
a6b96beb
AM		 18945elf32_arm_additional_program_headers (bfd *abfd,
18946 struct bfd_link_info *info ATTRIBUTE_UNUSED)
b294bdf8
MM		 18947{
18948 asection *sec;
18949
18950 sec = bfd_get_section_by_name (abfd, ".ARM.exidx");
18951 if (sec != NULL && (sec->flags & SEC_LOAD) != 0)
18952 return 1;
18953 else
18954 return 0;
18955}
18956
34e77a92
RS		 18957/* Hook called by the linker routine which adds symbols from an object
18958 file. */
18959
18960static bfd_boolean
18961elf32_arm_add_symbol_hook (bfd *abfd, struct bfd_link_info *info,
18962 Elf_Internal_Sym *sym, const char **namep,
18963 flagword *flagsp, asection **secp, bfd_vma *valp)
18964{
a43942db 18965 if (ELF_ST_TYPE (sym->st_info) == STT_GNU_IFUNC
f1885d1e
AM		 18966 && (abfd->flags & DYNAMIC) == 0
18967 && bfd_get_flavour (info->output_bfd) == bfd_target_elf_flavour)
a43942db 18968 elf_tdata (info->output_bfd)->has_gnu_symbols |= elf_gnu_symbol_ifunc;
34e77a92 18969
c792917c
NC		 18970 if (elf32_arm_hash_table (info) == NULL)
18971 return FALSE;
18972
34e77a92
RS		 18973 if (elf32_arm_hash_table (info)->vxworks_p
18974 && !elf_vxworks_add_symbol_hook (abfd, info, sym, namep,
18975 flagsp, secp, valp))
18976 return FALSE;
18977
18978 return TRUE;
18979}
18980
0beaef2b 18981/* We use this to override swap_symbol_in and swap_symbol_out. */
906e58ca
NC		 18982const struct elf_size_info elf32_arm_size_info =
18983{
0beaef2b
PB		 18984 sizeof (Elf32_External_Ehdr),
18985 sizeof (Elf32_External_Phdr),
18986 sizeof (Elf32_External_Shdr),
18987 sizeof (Elf32_External_Rel),
18988 sizeof (Elf32_External_Rela),
18989 sizeof (Elf32_External_Sym),
18990 sizeof (Elf32_External_Dyn),
18991 sizeof (Elf_External_Note),
18992 4,
18993 1,
18994 32, 2,
18995 ELFCLASS32, EV_CURRENT,
18996 bfd_elf32_write_out_phdrs,
18997 bfd_elf32_write_shdrs_and_ehdr,
1489a3a0 18998 bfd_elf32_checksum_contents,
0beaef2b
PB		 18999 bfd_elf32_write_relocs,
19000 elf32_arm_swap_symbol_in,
19001 elf32_arm_swap_symbol_out,
19002 bfd_elf32_slurp_reloc_table,
19003 bfd_elf32_slurp_symbol_table,
19004 bfd_elf32_swap_dyn_in,
19005 bfd_elf32_swap_dyn_out,
19006 bfd_elf32_swap_reloc_in,
19007 bfd_elf32_swap_reloc_out,
19008 bfd_elf32_swap_reloca_in,
19009 bfd_elf32_swap_reloca_out
19010};
19011
685e70ae
VK		 19012static bfd_vma
19013read_code32 (const bfd *abfd, const bfd_byte *addr)
19014{
19015 /* V7 BE8 code is always little endian. */
19016 if ((elf_elfheader (abfd)->e_flags & EF_ARM_BE8) != 0)
19017 return bfd_getl32 (addr);
19018
19019 return bfd_get_32 (abfd, addr);
19020}
19021
19022static bfd_vma
19023read_code16 (const bfd *abfd, const bfd_byte *addr)
19024{
19025 /* V7 BE8 code is always little endian. */
19026 if ((elf_elfheader (abfd)->e_flags & EF_ARM_BE8) != 0)
19027 return bfd_getl16 (addr);
19028
19029 return bfd_get_16 (abfd, addr);
19030}
19031
6a631e86
YG		 19032/* Return size of plt0 entry starting at ADDR
19033 or (bfd_vma) -1 if size can not be determined. */
19034
19035static bfd_vma
19036elf32_arm_plt0_size (const bfd *abfd, const bfd_byte *addr)
19037{
19038 bfd_vma first_word;
19039 bfd_vma plt0_size;
19040
685e70ae 19041 first_word = read_code32 (abfd, addr);
6a631e86
YG		 19042
19043 if (first_word == elf32_arm_plt0_entry[0])
19044 plt0_size = 4 * ARRAY_SIZE (elf32_arm_plt0_entry);
19045 else if (first_word == elf32_thumb2_plt0_entry[0])
19046 plt0_size = 4 * ARRAY_SIZE (elf32_thumb2_plt0_entry);
19047 else
19048 /* We don't yet handle this PLT format. */
19049 return (bfd_vma) -1;
19050
19051 return plt0_size;
19052}
19053
19054/* Return size of plt entry starting at offset OFFSET
19055 of plt section located at address START
19056 or (bfd_vma) -1 if size can not be determined. */
19057
19058static bfd_vma
19059elf32_arm_plt_size (const bfd *abfd, const bfd_byte *start, bfd_vma offset)
19060{
19061 bfd_vma first_insn;
19062 bfd_vma plt_size = 0;
19063 const bfd_byte *addr = start + offset;
19064
19065 /* PLT entry size if fixed on Thumb-only platforms. */
685e70ae 19066 if (read_code32 (abfd, start) == elf32_thumb2_plt0_entry[0])
6a631e86
YG		 19067 return 4 * ARRAY_SIZE (elf32_thumb2_plt_entry);
19068
19069 /* Respect Thumb stub if necessary. */
685e70ae 19070 if (read_code16 (abfd, addr) == elf32_arm_plt_thumb_stub[0])
6a631e86
YG		 19071 {
19072 plt_size += 2 * ARRAY_SIZE(elf32_arm_plt_thumb_stub);
19073 }
19074
19075 /* Strip immediate from first add. */
685e70ae 19076 first_insn = read_code32 (abfd, addr + plt_size) & 0xffffff00;
6a631e86
YG		 19077
19078#ifdef FOUR_WORD_PLT
19079 if (first_insn == elf32_arm_plt_entry[0])
19080 plt_size += 4 * ARRAY_SIZE (elf32_arm_plt_entry);
19081#else
19082 if (first_insn == elf32_arm_plt_entry_long[0])
19083 plt_size += 4 * ARRAY_SIZE (elf32_arm_plt_entry_long);
19084 else if (first_insn == elf32_arm_plt_entry_short[0])
19085 plt_size += 4 * ARRAY_SIZE (elf32_arm_plt_entry_short);
19086#endif
19087 else
19088 /* We don't yet handle this PLT format. */
19089 return (bfd_vma) -1;
19090
19091 return plt_size;
19092}
19093
19094/* Implementation is shamelessly borrowed from _bfd_elf_get_synthetic_symtab. */
19095
19096static long
19097elf32_arm_get_synthetic_symtab (bfd *abfd,
19098 long symcount ATTRIBUTE_UNUSED,
19099 asymbol **syms ATTRIBUTE_UNUSED,
19100 long dynsymcount,
19101 asymbol **dynsyms,
19102 asymbol **ret)
19103{
19104 asection *relplt;
19105 asymbol *s;
19106 arelent *p;
19107 long count, i, n;
19108 size_t size;
19109 Elf_Internal_Shdr *hdr;
19110 char *names;
19111 asection *plt;
19112 bfd_vma offset;
19113 bfd_byte *data;
19114
19115 *ret = NULL;
19116
19117 if ((abfd->flags & (DYNAMIC | EXEC_P)) == 0)
19118 return 0;
19119
19120 if (dynsymcount <= 0)
19121 return 0;
19122
19123 relplt = bfd_get_section_by_name (abfd, ".rel.plt");
19124 if (relplt == NULL)
19125 return 0;
19126
19127 hdr = &elf_section_data (relplt)->this_hdr;
19128 if (hdr->sh_link != elf_dynsymtab (abfd)
19129 || (hdr->sh_type != SHT_REL && hdr->sh_type != SHT_RELA))
19130 return 0;
19131
19132 plt = bfd_get_section_by_name (abfd, ".plt");
19133 if (plt == NULL)
19134 return 0;
19135
19136 if (!elf32_arm_size_info.slurp_reloc_table (abfd, relplt, dynsyms, TRUE))
19137 return -1;
19138
19139 data = plt->contents;
19140 if (data == NULL)
19141 {
19142 if (!bfd_get_full_section_contents(abfd, (asection *) plt, &data) || data == NULL)
19143 return -1;
19144 bfd_cache_section_contents((asection *) plt, data);
19145 }
19146
19147 count = relplt->size / hdr->sh_entsize;
19148 size = count * sizeof (asymbol);
19149 p = relplt->relocation;
19150 for (i = 0; i < count; i++, p += elf32_arm_size_info.int_rels_per_ext_rel)
19151 {
19152 size += strlen ((*p->sym_ptr_ptr)->name) + sizeof ("@plt");
19153 if (p->addend != 0)
19154 size += sizeof ("+0x") - 1 + 8;
19155 }
19156
19157 s = *ret = (asymbol *) bfd_malloc (size);
19158 if (s == NULL)
19159 return -1;
19160
19161 offset = elf32_arm_plt0_size (abfd, data);
19162 if (offset == (bfd_vma) -1)
19163 return -1;
19164
19165 names = (char *) (s + count);
19166 p = relplt->relocation;
19167 n = 0;
19168 for (i = 0; i < count; i++, p += elf32_arm_size_info.int_rels_per_ext_rel)
19169 {
19170 size_t len;
19171
19172 bfd_vma plt_size = elf32_arm_plt_size (abfd, data, offset);
19173 if (plt_size == (bfd_vma) -1)
19174 break;
19175
19176 *s = **p->sym_ptr_ptr;
19177 /* Undefined syms won't have BSF_LOCAL or BSF_GLOBAL set. Since
19178 we are defining a symbol, ensure one of them is set. */
19179 if ((s->flags & BSF_LOCAL) == 0)
19180 s->flags |= BSF_GLOBAL;
19181 s->flags |= BSF_SYNTHETIC;
19182 s->section = plt;
19183 s->value = offset;
19184 s->name = names;
19185 s->udata.p = NULL;
19186 len = strlen ((*p->sym_ptr_ptr)->name);
19187 memcpy (names, (*p->sym_ptr_ptr)->name, len);
19188 names += len;
19189 if (p->addend != 0)
19190 {
19191 char buf[30], *a;
19192
19193 memcpy (names, "+0x", sizeof ("+0x") - 1);
19194 names += sizeof ("+0x") - 1;
19195 bfd_sprintf_vma (abfd, buf, p->addend);
19196 for (a = buf; *a == '0'; ++a)
19197 ;
19198 len = strlen (a);
19199 memcpy (names, a, len);
19200 names += len;
19201 }
19202 memcpy (names, "@plt", sizeof ("@plt"));
19203 names += sizeof ("@plt");
19204 ++s, ++n;
19205 offset += plt_size;
19206 }
19207
19208 return n;
19209}
19210
ac4c9b04
MG		 19211static bfd_boolean
19212elf32_arm_section_flags (flagword *flags, const Elf_Internal_Shdr * hdr)
19213{
f0728ee3
AV		 19214 if (hdr->sh_flags & SHF_ARM_PURECODE)
19215 *flags |= SEC_ELF_PURECODE;
ac4c9b04
MG		 19216 return TRUE;
19217}
19218
19219static flagword
19220elf32_arm_lookup_section_flags (char *flag_name)
19221{
f0728ee3
AV		 19222 if (!strcmp (flag_name, "SHF_ARM_PURECODE"))
19223 return SHF_ARM_PURECODE;
ac4c9b04
MG		 19224
19225 return SEC_NO_FLAGS;
19226}
19227
491d01d3
YU		 19228static unsigned int
19229elf32_arm_count_additional_relocs (asection *sec)
19230{
19231 struct _arm_elf_section_data *arm_data;
19232 arm_data = get_arm_elf_section_data (sec);
5025eb7c 19233
6342be70 19234 return arm_data == NULL ? 0 : arm_data->additional_reloc_count;
491d01d3
YU		 19235}
19236
5522f910 19237/* Called to set the sh_flags, sh_link and sh_info fields of OSECTION which
9eaff861 19238 has a type >= SHT_LOOS. Returns TRUE if these fields were initialised
5522f910
NC		 19239 FALSE otherwise. ISECTION is the best guess matching section from the
19240 input bfd IBFD, but it might be NULL. */
19241
19242static bfd_boolean
19243elf32_arm_copy_special_section_fields (const bfd *ibfd ATTRIBUTE_UNUSED,
19244 bfd *obfd ATTRIBUTE_UNUSED,
19245 const Elf_Internal_Shdr *isection ATTRIBUTE_UNUSED,
19246 Elf_Internal_Shdr *osection)
19247{
19248 switch (osection->sh_type)
19249 {
19250 case SHT_ARM_EXIDX:
19251 {
19252 Elf_Internal_Shdr **oheaders = elf_elfsections (obfd);
19253 Elf_Internal_Shdr **iheaders = elf_elfsections (ibfd);
19254 unsigned i = 0;
19255
19256 osection->sh_flags = SHF_ALLOC | SHF_LINK_ORDER;
19257 osection->sh_info = 0;
19258
19259 /* The sh_link field must be set to the text section associated with
19260 this index section. Unfortunately the ARM EHABI does not specify
19261 exactly how to determine this association. Our caller does try
19262 to match up OSECTION with its corresponding input section however
19263 so that is a good first guess. */
19264 if (isection != NULL
19265 && osection->bfd_section != NULL
19266 && isection->bfd_section != NULL
19267 && isection->bfd_section->output_section != NULL
19268 && isection->bfd_section->output_section == osection->bfd_section
19269 && iheaders != NULL
19270 && isection->sh_link > 0
19271 && isection->sh_link < elf_numsections (ibfd)
19272 && iheaders[isection->sh_link]->bfd_section != NULL
19273 && iheaders[isection->sh_link]->bfd_section->output_section != NULL
19274 )
19275 {
19276 for (i = elf_numsections (obfd); i-- > 0;)
19277 if (oheaders[i]->bfd_section
19278 == iheaders[isection->sh_link]->bfd_section->output_section)
19279 break;
19280 }
9eaff861 19281
5522f910
NC		 19282 if (i == 0)
19283 {
19284 /* Failing that we have to find a matching section ourselves. If
19285 we had the output section name available we could compare that
19286 with input section names. Unfortunately we don't. So instead
19287 we use a simple heuristic and look for the nearest executable
19288 section before this one. */
19289 for (i = elf_numsections (obfd); i-- > 0;)
19290 if (oheaders[i] == osection)
19291 break;
19292 if (i == 0)
19293 break;
19294
19295 while (i-- > 0)
19296 if (oheaders[i]->sh_type == SHT_PROGBITS
19297 && (oheaders[i]->sh_flags & (SHF_ALLOC | SHF_EXECINSTR))
19298 == (SHF_ALLOC | SHF_EXECINSTR))
19299 break;
19300 }
19301
19302 if (i)
19303 {
19304 osection->sh_link = i;
19305 /* If the text section was part of a group
19306 then the index section should be too. */
19307 if (oheaders[i]->sh_flags & SHF_GROUP)
19308 osection->sh_flags |= SHF_GROUP;
19309 return TRUE;
19310 }
19311 }
19312 break;
19313
19314 case SHT_ARM_PREEMPTMAP:
19315 osection->sh_flags = SHF_ALLOC;
19316 break;
19317
19318 case SHT_ARM_ATTRIBUTES:
19319 case SHT_ARM_DEBUGOVERLAY:
19320 case SHT_ARM_OVERLAYSECTION:
19321 default:
19322 break;
19323 }
19324
19325 return FALSE;
19326}
19327
d691934d
NC		 19328/* Returns TRUE if NAME is an ARM mapping symbol.
19329 Traditionally the symbols $a, $d and $t have been used.
19330 The ARM ELF standard also defines $x (for A64 code). It also allows a
19331 period initiated suffix to be added to the symbol: "$[adtx]\.[:sym_char]+".
19332 Other tools might also produce $b (Thumb BL), $f, $p, $m and $v, but we do
19333 not support them here. $t.x indicates the start of ThumbEE instructions. */
19334
19335static bfd_boolean
19336is_arm_mapping_symbol (const char * name)
19337{
19338 return name != NULL /* Paranoia. */
19339 && name[0] == '$' /* Note: if objcopy --prefix-symbols has been used then
19340 the mapping symbols could have acquired a prefix.
19341 We do not support this here, since such symbols no
19342 longer conform to the ARM ELF ABI. */
19343 && (name[1] == 'a' || name[1] == 'd' || name[1] == 't' || name[1] == 'x')
19344 && (name[2] == 0 || name[2] == '.');
19345 /* FIXME: Strictly speaking the symbol is only a valid mapping symbol if
19346 any characters that follow the period are legal characters for the body
19347 of a symbol's name. For now we just assume that this is the case. */
19348}
19349
fca2a38f
NC		 19350/* Make sure that mapping symbols in object files are not removed via the
19351 "strip --strip-unneeded" tool. These symbols are needed in order to
19352 correctly generate interworking veneers, and for byte swapping code
19353 regions. Once an object file has been linked, it is safe to remove the
19354 symbols as they will no longer be needed. */
19355
19356static void
19357elf32_arm_backend_symbol_processing (bfd *abfd, asymbol *sym)
19358{
19359 if (((abfd->flags & (EXEC_P | DYNAMIC)) == 0)
fca2a38f 19360 && sym->section != bfd_abs_section_ptr
d691934d 19361 && is_arm_mapping_symbol (sym->name))
fca2a38f
NC		 19362 sym->flags |= BSF_KEEP;
19363}
19364
5522f910
NC		 19365#undef elf_backend_copy_special_section_fields
19366#define elf_backend_copy_special_section_fields elf32_arm_copy_special_section_fields
19367
252b5132 19368#define ELF_ARCH bfd_arch_arm
ae95ffa6 19369#define ELF_TARGET_ID ARM_ELF_DATA
252b5132 19370#define ELF_MACHINE_CODE EM_ARM
d0facd1b
NC		 19371#ifdef __QNXTARGET__
19372#define ELF_MAXPAGESIZE 0x1000
19373#else
7572ca89 19374#define ELF_MAXPAGESIZE 0x10000
d0facd1b 19375#endif
b1342370 19376#define ELF_MINPAGESIZE 0x1000
24718e3b 19377#define ELF_COMMONPAGESIZE 0x1000
252b5132 19378
ba93b8ac
DJ		 19379#define bfd_elf32_mkobject elf32_arm_mkobject
19380
99e4ae17
AJ		 19381#define bfd_elf32_bfd_copy_private_bfd_data elf32_arm_copy_private_bfd_data
19382#define bfd_elf32_bfd_merge_private_bfd_data elf32_arm_merge_private_bfd_data
252b5132
RH		 19383#define bfd_elf32_bfd_set_private_flags elf32_arm_set_private_flags
19384#define bfd_elf32_bfd_print_private_bfd_data elf32_arm_print_private_bfd_data
19385#define bfd_elf32_bfd_link_hash_table_create elf32_arm_link_hash_table_create
dc810e39 19386#define bfd_elf32_bfd_reloc_type_lookup elf32_arm_reloc_type_lookup
b38cadfb 19387#define bfd_elf32_bfd_reloc_name_lookup elf32_arm_reloc_name_lookup
252b5132 19388#define bfd_elf32_find_nearest_line elf32_arm_find_nearest_line
4ab527b0 19389#define bfd_elf32_find_inliner_info elf32_arm_find_inliner_info
e489d0ae 19390#define bfd_elf32_new_section_hook elf32_arm_new_section_hook
3c9458e9 19391#define bfd_elf32_bfd_is_target_special_symbol elf32_arm_is_target_special_symbol
3e6b1042 19392#define bfd_elf32_bfd_final_link elf32_arm_final_link
6a631e86 19393#define bfd_elf32_get_synthetic_symtab elf32_arm_get_synthetic_symtab
252b5132
RH		 19394
19395#define elf_backend_get_symbol_type elf32_arm_get_symbol_type
19396#define elf_backend_gc_mark_hook elf32_arm_gc_mark_hook
6a5bb875 19397#define elf_backend_gc_mark_extra_sections elf32_arm_gc_mark_extra_sections
252b5132
RH		 19398#define elf_backend_gc_sweep_hook elf32_arm_gc_sweep_hook
19399#define elf_backend_check_relocs elf32_arm_check_relocs
9eaff861 19400#define elf_backend_update_relocs elf32_arm_update_relocs
dc810e39 19401#define elf_backend_relocate_section elf32_arm_relocate_section
e489d0ae 19402#define elf_backend_write_section elf32_arm_write_section
252b5132 19403#define elf_backend_adjust_dynamic_symbol elf32_arm_adjust_dynamic_symbol
5e681ec4 19404#define elf_backend_create_dynamic_sections elf32_arm_create_dynamic_sections
252b5132
RH		 19405#define elf_backend_finish_dynamic_symbol elf32_arm_finish_dynamic_symbol
19406#define elf_backend_finish_dynamic_sections elf32_arm_finish_dynamic_sections
19407#define elf_backend_size_dynamic_sections elf32_arm_size_dynamic_sections
0855e32b 19408#define elf_backend_always_size_sections elf32_arm_always_size_sections
74541ad4 19409#define elf_backend_init_index_section _bfd_elf_init_2_index_sections
ba96a88f 19410#define elf_backend_post_process_headers elf32_arm_post_process_headers
99e4ae17 19411#define elf_backend_reloc_type_class elf32_arm_reloc_type_class
c178919b 19412#define elf_backend_object_p elf32_arm_object_p
40a18ebd
NC		 19413#define elf_backend_fake_sections elf32_arm_fake_sections
19414#define elf_backend_section_from_shdr elf32_arm_section_from_shdr
e16bb312 19415#define elf_backend_final_write_processing elf32_arm_final_write_processing
5e681ec4 19416#define elf_backend_copy_indirect_symbol elf32_arm_copy_indirect_symbol
0beaef2b 19417#define elf_backend_size_info elf32_arm_size_info
b294bdf8 19418#define elf_backend_modify_segment_map elf32_arm_modify_segment_map
906e58ca
NC		 19419#define elf_backend_additional_program_headers elf32_arm_additional_program_headers
19420#define elf_backend_output_arch_local_syms elf32_arm_output_arch_local_syms
54ddd295 19421#define elf_backend_filter_implib_symbols elf32_arm_filter_implib_symbols
906e58ca 19422#define elf_backend_begin_write_processing elf32_arm_begin_write_processing
34e77a92 19423#define elf_backend_add_symbol_hook elf32_arm_add_symbol_hook
491d01d3 19424#define elf_backend_count_additional_relocs elf32_arm_count_additional_relocs
fca2a38f 19425#define elf_backend_symbol_processing elf32_arm_backend_symbol_processing
906e58ca
NC		 19426
19427#define elf_backend_can_refcount 1
19428#define elf_backend_can_gc_sections 1
19429#define elf_backend_plt_readonly 1
19430#define elf_backend_want_got_plt 1
19431#define elf_backend_want_plt_sym 0
5474d94f 19432#define elf_backend_want_dynrelro 1
906e58ca
NC		 19433#define elf_backend_may_use_rel_p 1
19434#define elf_backend_may_use_rela_p 0
4e7fd91e 19435#define elf_backend_default_use_rela_p 0
64f52338 19436#define elf_backend_dtrel_excludes_plt 1
252b5132 19437
04f7c78d 19438#define elf_backend_got_header_size 12
b68a20d6 19439#define elf_backend_extern_protected_data 1
04f7c78d 19440
906e58ca
NC		 19441#undef elf_backend_obj_attrs_vendor
19442#define elf_backend_obj_attrs_vendor "aeabi"
19443#undef elf_backend_obj_attrs_section
19444#define elf_backend_obj_attrs_section ".ARM.attributes"
19445#undef elf_backend_obj_attrs_arg_type
19446#define elf_backend_obj_attrs_arg_type elf32_arm_obj_attrs_arg_type
19447#undef elf_backend_obj_attrs_section_type
104d59d1 19448#define elf_backend_obj_attrs_section_type SHT_ARM_ATTRIBUTES
b38cadfb
NC		 19449#define elf_backend_obj_attrs_order elf32_arm_obj_attrs_order
19450#define elf_backend_obj_attrs_handle_unknown elf32_arm_obj_attrs_handle_unknown
104d59d1 19451
5025eb7c 19452#undef elf_backend_section_flags
ac4c9b04 19453#define elf_backend_section_flags elf32_arm_section_flags
5025eb7c 19454#undef elf_backend_lookup_section_flags_hook
ac4c9b04
MG		 19455#define elf_backend_lookup_section_flags_hook elf32_arm_lookup_section_flags
19456
252b5132 19457#include "elf32-target.h"
7f266840 19458
b38cadfb
NC		 19459/* Native Client targets. */
19460
19461#undef TARGET_LITTLE_SYM
6d00b590 19462#define TARGET_LITTLE_SYM arm_elf32_nacl_le_vec
b38cadfb
NC		 19463#undef TARGET_LITTLE_NAME
19464#define TARGET_LITTLE_NAME "elf32-littlearm-nacl"
19465#undef TARGET_BIG_SYM
6d00b590 19466#define TARGET_BIG_SYM arm_elf32_nacl_be_vec
b38cadfb
NC		 19467#undef TARGET_BIG_NAME
19468#define TARGET_BIG_NAME "elf32-bigarm-nacl"
19469
19470/* Like elf32_arm_link_hash_table_create -- but overrides
19471 appropriately for NaCl. */
19472
19473static struct bfd_link_hash_table *
19474elf32_arm_nacl_link_hash_table_create (bfd *abfd)
19475{
19476 struct bfd_link_hash_table *ret;
19477
19478 ret = elf32_arm_link_hash_table_create (abfd);
19479 if (ret)
19480 {
19481 struct elf32_arm_link_hash_table *htab
19482 = (struct elf32_arm_link_hash_table *) ret;
19483
19484 htab->nacl_p = 1;
19485
19486 htab->plt_header_size = 4 * ARRAY_SIZE (elf32_arm_nacl_plt0_entry);
19487 htab->plt_entry_size = 4 * ARRAY_SIZE (elf32_arm_nacl_plt_entry);
19488 }
19489 return ret;
19490}
19491
19492/* Since NaCl doesn't use the ARM-specific unwind format, we don't
19493 really need to use elf32_arm_modify_segment_map. But we do it
19494 anyway just to reduce gratuitous differences with the stock ARM backend. */
19495
19496static bfd_boolean
19497elf32_arm_nacl_modify_segment_map (bfd *abfd, struct bfd_link_info *info)
19498{
19499 return (elf32_arm_modify_segment_map (abfd, info)
19500 && nacl_modify_segment_map (abfd, info));
19501}
19502
887badb3
RM		 19503static void
19504elf32_arm_nacl_final_write_processing (bfd *abfd, bfd_boolean linker)
19505{
19506 elf32_arm_final_write_processing (abfd, linker);
19507 nacl_final_write_processing (abfd, linker);
19508}
19509
6a631e86
YG		 19510static bfd_vma
19511elf32_arm_nacl_plt_sym_val (bfd_vma i, const asection *plt,
19512 const arelent *rel ATTRIBUTE_UNUSED)
19513{
19514 return plt->vma
19515 + 4 * (ARRAY_SIZE (elf32_arm_nacl_plt0_entry) +
19516 i * ARRAY_SIZE (elf32_arm_nacl_plt_entry));
19517}
887badb3 19518
b38cadfb 19519#undef elf32_bed
6a631e86 19520#define elf32_bed elf32_arm_nacl_bed
b38cadfb
NC		 19521#undef bfd_elf32_bfd_link_hash_table_create
19522#define bfd_elf32_bfd_link_hash_table_create \
19523 elf32_arm_nacl_link_hash_table_create
19524#undef elf_backend_plt_alignment
6a631e86 19525#define elf_backend_plt_alignment 4
b38cadfb
NC		 19526#undef elf_backend_modify_segment_map
19527#define elf_backend_modify_segment_map elf32_arm_nacl_modify_segment_map
19528#undef elf_backend_modify_program_headers
19529#define elf_backend_modify_program_headers nacl_modify_program_headers
887badb3
RM		 19530#undef elf_backend_final_write_processing
19531#define elf_backend_final_write_processing elf32_arm_nacl_final_write_processing
6a631e86
YG		 19532#undef bfd_elf32_get_synthetic_symtab
19533#undef elf_backend_plt_sym_val
19534#define elf_backend_plt_sym_val elf32_arm_nacl_plt_sym_val
5522f910 19535#undef elf_backend_copy_special_section_fields
b38cadfb 19536
887badb3
RM		 19537#undef ELF_MINPAGESIZE
19538#undef ELF_COMMONPAGESIZE
19539
b38cadfb
NC		 19540
19541#include "elf32-target.h"
19542
19543/* Reset to defaults. */
19544#undef elf_backend_plt_alignment
19545#undef elf_backend_modify_segment_map
19546#define elf_backend_modify_segment_map elf32_arm_modify_segment_map
19547#undef elf_backend_modify_program_headers
887badb3
RM		 19548#undef elf_backend_final_write_processing
19549#define elf_backend_final_write_processing elf32_arm_final_write_processing
19550#undef ELF_MINPAGESIZE
19551#define ELF_MINPAGESIZE 0x1000
19552#undef ELF_COMMONPAGESIZE
19553#define ELF_COMMONPAGESIZE 0x1000
19554
b38cadfb 19555
906e58ca 19556/* VxWorks Targets. */
4e7fd91e 19557
906e58ca 19558#undef TARGET_LITTLE_SYM
6d00b590 19559#define TARGET_LITTLE_SYM arm_elf32_vxworks_le_vec
906e58ca 19560#undef TARGET_LITTLE_NAME
4e7fd91e 19561#define TARGET_LITTLE_NAME "elf32-littlearm-vxworks"
906e58ca 19562#undef TARGET_BIG_SYM
6d00b590 19563#define TARGET_BIG_SYM arm_elf32_vxworks_be_vec
906e58ca 19564#undef TARGET_BIG_NAME
4e7fd91e
PB		 19565#define TARGET_BIG_NAME "elf32-bigarm-vxworks"
19566
19567/* Like elf32_arm_link_hash_table_create -- but overrides
19568 appropriately for VxWorks. */
906e58ca 19569
4e7fd91e
PB		 19570static struct bfd_link_hash_table *
19571elf32_arm_vxworks_link_hash_table_create (bfd *abfd)
19572{
19573 struct bfd_link_hash_table *ret;
19574
19575 ret = elf32_arm_link_hash_table_create (abfd);
19576 if (ret)
19577 {
19578 struct elf32_arm_link_hash_table *htab
00a97672 19579 = (struct elf32_arm_link_hash_table *) ret;
4e7fd91e 19580 htab->use_rel = 0;
00a97672 19581 htab->vxworks_p = 1;
4e7fd91e
PB		 19582 }
19583 return ret;
906e58ca 19584}
4e7fd91e 19585
00a97672
RS		 19586static void
19587elf32_arm_vxworks_final_write_processing (bfd *abfd, bfd_boolean linker)
19588{
19589 elf32_arm_final_write_processing (abfd, linker);
19590 elf_vxworks_final_write_processing (abfd, linker);
19591}
19592
906e58ca 19593#undef elf32_bed
4e7fd91e
PB		 19594#define elf32_bed elf32_arm_vxworks_bed
19595
906e58ca
NC		 19596#undef bfd_elf32_bfd_link_hash_table_create
19597#define bfd_elf32_bfd_link_hash_table_create elf32_arm_vxworks_link_hash_table_create
906e58ca
NC		 19598#undef elf_backend_final_write_processing
19599#define elf_backend_final_write_processing elf32_arm_vxworks_final_write_processing
19600#undef elf_backend_emit_relocs
9eaff861 19601#define elf_backend_emit_relocs elf_vxworks_emit_relocs
4e7fd91e 19602
906e58ca 19603#undef elf_backend_may_use_rel_p
00a97672 19604#define elf_backend_may_use_rel_p 0
906e58ca 19605#undef elf_backend_may_use_rela_p
00a97672 19606#define elf_backend_may_use_rela_p 1
906e58ca 19607#undef elf_backend_default_use_rela_p
00a97672 19608#define elf_backend_default_use_rela_p 1
906e58ca 19609#undef elf_backend_want_plt_sym
00a97672 19610#define elf_backend_want_plt_sym 1
906e58ca 19611#undef ELF_MAXPAGESIZE
00a97672 19612#define ELF_MAXPAGESIZE 0x1000
4e7fd91e
PB		 19613
19614#include "elf32-target.h"
19615
19616
21d799b5
NC		 19617/* Merge backend specific data from an object file to the output
19618 object file when linking. */
19619
19620static bfd_boolean
50e03d47 19621elf32_arm_merge_private_bfd_data (bfd *ibfd, struct bfd_link_info *info)
21d799b5 19622{
50e03d47 19623 bfd *obfd = info->output_bfd;
21d799b5
NC		 19624 flagword out_flags;
19625 flagword in_flags;
19626 bfd_boolean flags_compatible = TRUE;
19627 asection *sec;
19628
cc643b88 19629 /* Check if we have the same endianness. */
50e03d47 19630 if (! _bfd_generic_verify_endian_match (ibfd, info))
21d799b5
NC		 19631 return FALSE;
19632
19633 if (! is_arm_elf (ibfd) || ! is_arm_elf (obfd))
19634 return TRUE;
19635
50e03d47 19636 if (!elf32_arm_merge_eabi_attributes (ibfd, info))
21d799b5
NC		 19637 return FALSE;
19638
19639 /* The input BFD must have had its flags initialised. */
19640 /* The following seems bogus to me -- The flags are initialized in
19641 the assembler but I don't think an elf_flags_init field is
19642 written into the object. */
19643 /* BFD_ASSERT (elf_flags_init (ibfd)); */
19644
19645 in_flags = elf_elfheader (ibfd)->e_flags;
19646 out_flags = elf_elfheader (obfd)->e_flags;
19647
19648 /* In theory there is no reason why we couldn't handle this. However
19649 in practice it isn't even close to working and there is no real
19650 reason to want it. */
19651 if (EF_ARM_EABI_VERSION (in_flags) >= EF_ARM_EABI_VER4
19652 && !(ibfd->flags & DYNAMIC)
19653 && (in_flags & EF_ARM_BE8))
19654 {
19655 _bfd_error_handler (_("error: %B is already in final BE8 format"),
19656 ibfd);
19657 return FALSE;
19658 }
19659
19660 if (!elf_flags_init (obfd))
19661 {
19662 /* If the input is the default architecture and had the default
19663 flags then do not bother setting the flags for the output
19664 architecture, instead allow future merges to do this. If no
19665 future merges ever set these flags then they will retain their
99059e56
RM		 19666 uninitialised values, which surprise surprise, correspond
19667 to the default values. */
21d799b5
NC		 19668 if (bfd_get_arch_info (ibfd)->the_default
19669 && elf_elfheader (ibfd)->e_flags == 0)
19670 return TRUE;
19671
19672 elf_flags_init (obfd) = TRUE;
19673 elf_elfheader (obfd)->e_flags = in_flags;
19674
19675 if (bfd_get_arch (obfd) == bfd_get_arch (ibfd)
19676 && bfd_get_arch_info (obfd)->the_default)
19677 return bfd_set_arch_mach (obfd, bfd_get_arch (ibfd), bfd_get_mach (ibfd));
19678
19679 return TRUE;
19680 }
19681
19682 /* Determine what should happen if the input ARM architecture
19683 does not match the output ARM architecture. */
19684 if (! bfd_arm_merge_machines (ibfd, obfd))
19685 return FALSE;
19686
19687 /* Identical flags must be compatible. */
19688 if (in_flags == out_flags)
19689 return TRUE;
19690
19691 /* Check to see if the input BFD actually contains any sections. If
19692 not, its flags may not have been initialised either, but it
19693 cannot actually cause any incompatiblity. Do not short-circuit
19694 dynamic objects; their section list may be emptied by
19695 elf_link_add_object_symbols.
19696
19697 Also check to see if there are no code sections in the input.
19698 In this case there is no need to check for code specific flags.
19699 XXX - do we need to worry about floating-point format compatability
19700 in data sections ? */
19701 if (!(ibfd->flags & DYNAMIC))
19702 {
19703 bfd_boolean null_input_bfd = TRUE;
19704 bfd_boolean only_data_sections = TRUE;
19705
19706 for (sec = ibfd->sections; sec != NULL; sec = sec->next)
19707 {
19708 /* Ignore synthetic glue sections. */
19709 if (strcmp (sec->name, ".glue_7")
19710 && strcmp (sec->name, ".glue_7t"))
19711 {
19712 if ((bfd_get_section_flags (ibfd, sec)
19713 & (SEC_LOAD | SEC_CODE | SEC_HAS_CONTENTS))
19714 == (SEC_LOAD | SEC_CODE | SEC_HAS_CONTENTS))
99059e56 19715 only_data_sections = FALSE;
21d799b5
NC		 19716
19717 null_input_bfd = FALSE;
19718 break;
19719 }
19720 }
19721
19722 if (null_input_bfd || only_data_sections)
19723 return TRUE;
19724 }
19725
19726 /* Complain about various flag mismatches. */
19727 if (!elf32_arm_versions_compatible (EF_ARM_EABI_VERSION (in_flags),
19728 EF_ARM_EABI_VERSION (out_flags)))
19729 {
19730 _bfd_error_handler
19731 (_("error: Source object %B has EABI version %d, but target %B has EABI version %d"),
c08bb8dd
AM		 19732 ibfd, (in_flags & EF_ARM_EABIMASK) >> 24,
19733 obfd, (out_flags & EF_ARM_EABIMASK) >> 24);
21d799b5
NC		 19734 return FALSE;
19735 }
19736
19737 /* Not sure what needs to be checked for EABI versions >= 1. */
19738 /* VxWorks libraries do not use these flags. */
19739 if (get_elf_backend_data (obfd) != &elf32_arm_vxworks_bed
19740 && get_elf_backend_data (ibfd) != &elf32_arm_vxworks_bed
19741 && EF_ARM_EABI_VERSION (in_flags) == EF_ARM_EABI_UNKNOWN)
19742 {
19743 if ((in_flags & EF_ARM_APCS_26) != (out_flags & EF_ARM_APCS_26))
19744 {
19745 _bfd_error_handler
19746 (_("error: %B is compiled for APCS-%d, whereas target %B uses APCS-%d"),
c08bb8dd
AM		 19747 ibfd, in_flags & EF_ARM_APCS_26 ? 26 : 32,
19748 obfd, out_flags & EF_ARM_APCS_26 ? 26 : 32);
21d799b5
NC		 19749 flags_compatible = FALSE;
19750 }
19751
19752 if ((in_flags & EF_ARM_APCS_FLOAT) != (out_flags & EF_ARM_APCS_FLOAT))
19753 {
19754 if (in_flags & EF_ARM_APCS_FLOAT)
19755 _bfd_error_handler
19756 (_("error: %B passes floats in float registers, whereas %B passes them in integer registers"),
19757 ibfd, obfd);
19758 else
19759 _bfd_error_handler
19760 (_("error: %B passes floats in integer registers, whereas %B passes them in float registers"),
19761 ibfd, obfd);
19762
19763 flags_compatible = FALSE;
19764 }
19765
19766 if ((in_flags & EF_ARM_VFP_FLOAT) != (out_flags & EF_ARM_VFP_FLOAT))
19767 {
19768 if (in_flags & EF_ARM_VFP_FLOAT)
19769 _bfd_error_handler
19770 (_("error: %B uses VFP instructions, whereas %B does not"),
19771 ibfd, obfd);
19772 else
19773 _bfd_error_handler
19774 (_("error: %B uses FPA instructions, whereas %B does not"),
19775 ibfd, obfd);
19776
19777 flags_compatible = FALSE;
19778 }
19779
19780 if ((in_flags & EF_ARM_MAVERICK_FLOAT) != (out_flags & EF_ARM_MAVERICK_FLOAT))
19781 {
19782 if (in_flags & EF_ARM_MAVERICK_FLOAT)
19783 _bfd_error_handler
19784 (_("error: %B uses Maverick instructions, whereas %B does not"),
19785 ibfd, obfd);
19786 else
19787 _bfd_error_handler
19788 (_("error: %B does not use Maverick instructions, whereas %B does"),
19789 ibfd, obfd);
19790
19791 flags_compatible = FALSE;
19792 }
19793
19794#ifdef EF_ARM_SOFT_FLOAT
19795 if ((in_flags & EF_ARM_SOFT_FLOAT) != (out_flags & EF_ARM_SOFT_FLOAT))
19796 {
19797 /* We can allow interworking between code that is VFP format
19798 layout, and uses either soft float or integer regs for
19799 passing floating point arguments and results. We already
19800 know that the APCS_FLOAT flags match; similarly for VFP
19801 flags. */
19802 if ((in_flags & EF_ARM_APCS_FLOAT) != 0
19803 || (in_flags & EF_ARM_VFP_FLOAT) == 0)
19804 {
19805 if (in_flags & EF_ARM_SOFT_FLOAT)
19806 _bfd_error_handler
19807 (_("error: %B uses software FP, whereas %B uses hardware FP"),
19808 ibfd, obfd);
19809 else
19810 _bfd_error_handler
19811 (_("error: %B uses hardware FP, whereas %B uses software FP"),
19812 ibfd, obfd);
19813
19814 flags_compatible = FALSE;
19815 }
19816 }
19817#endif
19818
19819 /* Interworking mismatch is only a warning. */
19820 if ((in_flags & EF_ARM_INTERWORK) != (out_flags & EF_ARM_INTERWORK))
19821 {
19822 if (in_flags & EF_ARM_INTERWORK)
19823 {
19824 _bfd_error_handler
19825 (_("Warning: %B supports interworking, whereas %B does not"),
19826 ibfd, obfd);
19827 }
19828 else
19829 {
19830 _bfd_error_handler
19831 (_("Warning: %B does not support interworking, whereas %B does"),
19832 ibfd, obfd);
19833 }
19834 }
19835 }
19836
19837 return flags_compatible;
19838}
19839
19840
906e58ca 19841/* Symbian OS Targets. */
7f266840 19842
906e58ca 19843#undef TARGET_LITTLE_SYM
6d00b590 19844#define TARGET_LITTLE_SYM arm_elf32_symbian_le_vec
906e58ca 19845#undef TARGET_LITTLE_NAME
7f266840 19846#define TARGET_LITTLE_NAME "elf32-littlearm-symbian"
906e58ca 19847#undef TARGET_BIG_SYM
6d00b590 19848#define TARGET_BIG_SYM arm_elf32_symbian_be_vec
906e58ca 19849#undef TARGET_BIG_NAME
7f266840
DJ		 19850#define TARGET_BIG_NAME "elf32-bigarm-symbian"
19851
19852/* Like elf32_arm_link_hash_table_create -- but overrides
19853 appropriately for Symbian OS. */
906e58ca 19854
7f266840
DJ		 19855static struct bfd_link_hash_table *
19856elf32_arm_symbian_link_hash_table_create (bfd *abfd)
19857{
19858 struct bfd_link_hash_table *ret;
19859
19860 ret = elf32_arm_link_hash_table_create (abfd);
19861 if (ret)
19862 {
19863 struct elf32_arm_link_hash_table *htab
19864 = (struct elf32_arm_link_hash_table *)ret;
19865 /* There is no PLT header for Symbian OS. */
19866 htab->plt_header_size = 0;
95720a86
DJ		 19867 /* The PLT entries are each one instruction and one word. */
19868 htab->plt_entry_size = 4 * ARRAY_SIZE (elf32_arm_symbian_plt_entry);
7f266840 19869 htab->symbian_p = 1;
33bfe774
JB		 19870 /* Symbian uses armv5t or above, so use_blx is always true. */
19871 htab->use_blx = 1;
67687978 19872 htab->root.is_relocatable_executable = 1;
7f266840
DJ		 19873 }
19874 return ret;
906e58ca 19875}
7f266840 19876
b35d266b 19877static const struct bfd_elf_special_section
551b43fd 19878elf32_arm_symbian_special_sections[] =
7f266840 19879{
5cd3778d
MM		 19880 /* In a BPABI executable, the dynamic linking sections do not go in
19881 the loadable read-only segment. The post-linker may wish to
19882 refer to these sections, but they are not part of the final
19883 program image. */
0112cd26
NC		 19884 { STRING_COMMA_LEN (".dynamic"), 0, SHT_DYNAMIC, 0 },
19885 { STRING_COMMA_LEN (".dynstr"), 0, SHT_STRTAB, 0 },
19886 { STRING_COMMA_LEN (".dynsym"), 0, SHT_DYNSYM, 0 },
19887 { STRING_COMMA_LEN (".got"), 0, SHT_PROGBITS, 0 },
19888 { STRING_COMMA_LEN (".hash"), 0, SHT_HASH, 0 },
5cd3778d
MM		 19889 /* These sections do not need to be writable as the SymbianOS
19890 postlinker will arrange things so that no dynamic relocation is
19891 required. */
0112cd26
NC		 19892 { STRING_COMMA_LEN (".init_array"), 0, SHT_INIT_ARRAY, SHF_ALLOC },
19893 { STRING_COMMA_LEN (".fini_array"), 0, SHT_FINI_ARRAY, SHF_ALLOC },
19894 { STRING_COMMA_LEN (".preinit_array"), 0, SHT_PREINIT_ARRAY, SHF_ALLOC },
19895 { NULL, 0, 0, 0, 0 }
7f266840
DJ		 19896};
19897
c3c76620 19898static void
906e58ca 19899elf32_arm_symbian_begin_write_processing (bfd *abfd,
a4fd1a8e 19900 struct bfd_link_info *link_info)
c3c76620
MM		 19901{
19902 /* BPABI objects are never loaded directly by an OS kernel; they are
19903 processed by a postlinker first, into an OS-specific format. If
19904 the D_PAGED bit is set on the file, BFD will align segments on
19905 page boundaries, so that an OS can directly map the file. With
19906 BPABI objects, that just results in wasted space. In addition,
19907 because we clear the D_PAGED bit, map_sections_to_segments will
19908 recognize that the program headers should not be mapped into any
19909 loadable segment. */
19910 abfd->flags &= ~D_PAGED;
906e58ca 19911 elf32_arm_begin_write_processing (abfd, link_info);
c3c76620 19912}
7f266840
DJ		 19913
19914static bfd_boolean
906e58ca 19915elf32_arm_symbian_modify_segment_map (bfd *abfd,
b294bdf8 19916 struct bfd_link_info *info)
7f266840
DJ		 19917{
19918 struct elf_segment_map *m;
19919 asection *dynsec;
19920
7f266840
DJ		 19921 /* BPABI shared libraries and executables should have a PT_DYNAMIC
19922 segment. However, because the .dynamic section is not marked
19923 with SEC_LOAD, the generic ELF code will not create such a
19924 segment. */
19925 dynsec = bfd_get_section_by_name (abfd, ".dynamic");
19926 if (dynsec)
19927 {
12bd6957 19928 for (m = elf_seg_map (abfd); m != NULL; m = m->next)
8ded5a0f
AM		 19929 if (m->p_type == PT_DYNAMIC)
19930 break;
19931
19932 if (m == NULL)
19933 {
19934 m = _bfd_elf_make_dynamic_segment (abfd, dynsec);
12bd6957
AM		 19935 m->next = elf_seg_map (abfd);
19936 elf_seg_map (abfd) = m;
8ded5a0f 19937 }
7f266840
DJ		 19938 }
19939
b294bdf8
MM		 19940 /* Also call the generic arm routine. */
19941 return elf32_arm_modify_segment_map (abfd, info);
7f266840
DJ		 19942}
19943
95720a86
DJ		 19944/* Return address for Ith PLT stub in section PLT, for relocation REL
19945 or (bfd_vma) -1 if it should not be included. */
19946
19947static bfd_vma
19948elf32_arm_symbian_plt_sym_val (bfd_vma i, const asection *plt,
19949 const arelent *rel ATTRIBUTE_UNUSED)
19950{
19951 return plt->vma + 4 * ARRAY_SIZE (elf32_arm_symbian_plt_entry) * i;
19952}
19953
8029a119 19954#undef elf32_bed
7f266840
DJ		 19955#define elf32_bed elf32_arm_symbian_bed
19956
19957/* The dynamic sections are not allocated on SymbianOS; the postlinker
19958 will process them and then discard them. */
906e58ca 19959#undef ELF_DYNAMIC_SEC_FLAGS
7f266840
DJ		 19960#define ELF_DYNAMIC_SEC_FLAGS \
19961 (SEC_HAS_CONTENTS | SEC_IN_MEMORY | SEC_LINKER_CREATED)
19962
9eaff861 19963#undef elf_backend_emit_relocs
c3c76620 19964
906e58ca
NC		 19965#undef bfd_elf32_bfd_link_hash_table_create
19966#define bfd_elf32_bfd_link_hash_table_create elf32_arm_symbian_link_hash_table_create
19967#undef elf_backend_special_sections
19968#define elf_backend_special_sections elf32_arm_symbian_special_sections
19969#undef elf_backend_begin_write_processing
19970#define elf_backend_begin_write_processing elf32_arm_symbian_begin_write_processing
19971#undef elf_backend_final_write_processing
19972#define elf_backend_final_write_processing elf32_arm_final_write_processing
19973
19974#undef elf_backend_modify_segment_map
7f266840
DJ		 19975#define elf_backend_modify_segment_map elf32_arm_symbian_modify_segment_map
19976
19977/* There is no .got section for BPABI objects, and hence no header. */
906e58ca 19978#undef elf_backend_got_header_size
7f266840
DJ		 19979#define elf_backend_got_header_size 0
19980
19981/* Similarly, there is no .got.plt section. */
906e58ca 19982#undef elf_backend_want_got_plt
7f266840
DJ		 19983#define elf_backend_want_got_plt 0
19984
906e58ca 19985#undef elf_backend_plt_sym_val
95720a86
DJ		 19986#define elf_backend_plt_sym_val elf32_arm_symbian_plt_sym_val
19987
906e58ca 19988#undef elf_backend_may_use_rel_p
00a97672 19989#define elf_backend_may_use_rel_p 1
906e58ca 19990#undef elf_backend_may_use_rela_p
00a97672 19991#define elf_backend_may_use_rela_p 0
906e58ca 19992#undef elf_backend_default_use_rela_p
00a97672 19993#define elf_backend_default_use_rela_p 0
906e58ca 19994#undef elf_backend_want_plt_sym
00a97672 19995#define elf_backend_want_plt_sym 0
64f52338
AM		 19996#undef elf_backend_dtrel_excludes_plt
19997#define elf_backend_dtrel_excludes_plt 0
906e58ca 19998#undef ELF_MAXPAGESIZE
00a97672 19999#define ELF_MAXPAGESIZE 0x8000
4e7fd91e 20000
7f266840 20001#include "elf32-target.h"
GDB Binutils - Deliverables
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