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ld -z combreloc elf_link_sort_relocs
[deliverable/binutils-gdb.git] / bfd / elf32-arm.c
CommitLineData
252b5132 1/* 32-bit ELF support for ARM
6f2750fe 2 Copyright (C) 1998-2016 Free Software Foundation, Inc.
252b5132
RH		 3
4 This file is part of BFD, the Binary File Descriptor library.
5
6 This program is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
cd123cb7 8 the Free Software Foundation; either version 3 of the License, or
252b5132
RH		 9 (at your option) any later version.
10
11 This program is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
15
16 You should have received a copy of the GNU General Public License
17 along with this program; if not, write to the Free Software
cd123cb7
NC		 18 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
19 MA 02110-1301, USA. */
252b5132 20
6e6718a3 21#include "sysdep.h"
2468f9c9
PB		 22#include <limits.h>
23
3db64b00 24#include "bfd.h"
6034aab8 25#include "bfd_stdint.h"
00a97672 26#include "libiberty.h"
7f266840
DJ		 27#include "libbfd.h"
28#include "elf-bfd.h"
b38cadfb 29#include "elf-nacl.h"
00a97672 30#include "elf-vxworks.h"
ee065d83 31#include "elf/arm.h"
7f266840 32
00a97672
RS		 33/* Return the relocation section associated with NAME. HTAB is the
34 bfd's elf32_arm_link_hash_entry. */
35#define RELOC_SECTION(HTAB, NAME) \
36 ((HTAB)->use_rel ? ".rel" NAME : ".rela" NAME)
37
38/* Return size of a relocation entry. HTAB is the bfd's
39 elf32_arm_link_hash_entry. */
40#define RELOC_SIZE(HTAB) \
41 ((HTAB)->use_rel \
42 ? sizeof (Elf32_External_Rel) \
43 : sizeof (Elf32_External_Rela))
44
45/* Return function to swap relocations in. HTAB is the bfd's
46 elf32_arm_link_hash_entry. */
47#define SWAP_RELOC_IN(HTAB) \
48 ((HTAB)->use_rel \
49 ? bfd_elf32_swap_reloc_in \
50 : bfd_elf32_swap_reloca_in)
51
52/* Return function to swap relocations out. HTAB is the bfd's
53 elf32_arm_link_hash_entry. */
54#define SWAP_RELOC_OUT(HTAB) \
55 ((HTAB)->use_rel \
56 ? bfd_elf32_swap_reloc_out \
57 : bfd_elf32_swap_reloca_out)
58
7f266840
DJ		 59#define elf_info_to_howto 0
60#define elf_info_to_howto_rel elf32_arm_info_to_howto
61
62#define ARM_ELF_ABI_VERSION 0
63#define ARM_ELF_OS_ABI_VERSION ELFOSABI_ARM
64
79f08007
YZ		 65/* The Adjusted Place, as defined by AAELF. */
66#define Pa(X) ((X) & 0xfffffffc)
67
3e6b1042
DJ		 68static bfd_boolean elf32_arm_write_section (bfd *output_bfd,
69 struct bfd_link_info *link_info,
70 asection *sec,
71 bfd_byte *contents);
72
7f266840
DJ		 73/* Note: code such as elf32_arm_reloc_type_lookup expect to use e.g.
74 R_ARM_PC24 as an index into this, and find the R_ARM_PC24 HOWTO
75 in that slot. */
76
c19d1205 77static reloc_howto_type elf32_arm_howto_table_1[] =
7f266840 78{
8029a119 79 /* No relocation. */
7f266840
DJ		 80 HOWTO (R_ARM_NONE, /* type */
81 0, /* rightshift */
6346d5ca 82 3, /* size (0 = byte, 1 = short, 2 = long) */
7f266840
DJ		 83 0, /* bitsize */
84 FALSE, /* pc_relative */
85 0, /* bitpos */
86 complain_overflow_dont,/* complain_on_overflow */
87 bfd_elf_generic_reloc, /* special_function */
88 "R_ARM_NONE", /* name */
89 FALSE, /* partial_inplace */
90 0, /* src_mask */
91 0, /* dst_mask */
92 FALSE), /* pcrel_offset */
93
94 HOWTO (R_ARM_PC24, /* type */
95 2, /* rightshift */
96 2, /* size (0 = byte, 1 = short, 2 = long) */
97 24, /* bitsize */
98 TRUE, /* pc_relative */
99 0, /* bitpos */
100 complain_overflow_signed,/* complain_on_overflow */
101 bfd_elf_generic_reloc, /* special_function */
102 "R_ARM_PC24", /* name */
103 FALSE, /* partial_inplace */
104 0x00ffffff, /* src_mask */
105 0x00ffffff, /* dst_mask */
106 TRUE), /* pcrel_offset */
107
108 /* 32 bit absolute */
109 HOWTO (R_ARM_ABS32, /* type */
110 0, /* rightshift */
111 2, /* size (0 = byte, 1 = short, 2 = long) */
112 32, /* bitsize */
113 FALSE, /* pc_relative */
114 0, /* bitpos */
115 complain_overflow_bitfield,/* complain_on_overflow */
116 bfd_elf_generic_reloc, /* special_function */
117 "R_ARM_ABS32", /* name */
118 FALSE, /* partial_inplace */
119 0xffffffff, /* src_mask */
120 0xffffffff, /* dst_mask */
121 FALSE), /* pcrel_offset */
122
123 /* standard 32bit pc-relative reloc */
124 HOWTO (R_ARM_REL32, /* type */
125 0, /* rightshift */
126 2, /* size (0 = byte, 1 = short, 2 = long) */
127 32, /* bitsize */
128 TRUE, /* pc_relative */
129 0, /* bitpos */
130 complain_overflow_bitfield,/* complain_on_overflow */
131 bfd_elf_generic_reloc, /* special_function */
132 "R_ARM_REL32", /* name */
133 FALSE, /* partial_inplace */
134 0xffffffff, /* src_mask */
135 0xffffffff, /* dst_mask */
136 TRUE), /* pcrel_offset */
137
c19d1205 138 /* 8 bit absolute - R_ARM_LDR_PC_G0 in AAELF */
4962c51a 139 HOWTO (R_ARM_LDR_PC_G0, /* type */
7f266840
DJ		 140 0, /* rightshift */
141 0, /* size (0 = byte, 1 = short, 2 = long) */
4962c51a
MS		 142 32, /* bitsize */
143 TRUE, /* pc_relative */
7f266840 144 0, /* bitpos */
4962c51a 145 complain_overflow_dont,/* complain_on_overflow */
7f266840 146 bfd_elf_generic_reloc, /* special_function */
4962c51a 147 "R_ARM_LDR_PC_G0", /* name */
7f266840 148 FALSE, /* partial_inplace */
4962c51a
MS		 149 0xffffffff, /* src_mask */
150 0xffffffff, /* dst_mask */
151 TRUE), /* pcrel_offset */
7f266840
DJ		 152
153 /* 16 bit absolute */
154 HOWTO (R_ARM_ABS16, /* type */
155 0, /* rightshift */
156 1, /* size (0 = byte, 1 = short, 2 = long) */
157 16, /* bitsize */
158 FALSE, /* pc_relative */
159 0, /* bitpos */
160 complain_overflow_bitfield,/* complain_on_overflow */
161 bfd_elf_generic_reloc, /* special_function */
162 "R_ARM_ABS16", /* name */
163 FALSE, /* partial_inplace */
164 0x0000ffff, /* src_mask */
165 0x0000ffff, /* dst_mask */
166 FALSE), /* pcrel_offset */
167
168 /* 12 bit absolute */
169 HOWTO (R_ARM_ABS12, /* type */
170 0, /* rightshift */
171 2, /* size (0 = byte, 1 = short, 2 = long) */
172 12, /* bitsize */
173 FALSE, /* pc_relative */
174 0, /* bitpos */
175 complain_overflow_bitfield,/* complain_on_overflow */
176 bfd_elf_generic_reloc, /* special_function */
177 "R_ARM_ABS12", /* name */
178 FALSE, /* partial_inplace */
00a97672
RS		 179 0x00000fff, /* src_mask */
180 0x00000fff, /* dst_mask */
7f266840
DJ		 181 FALSE), /* pcrel_offset */
182
183 HOWTO (R_ARM_THM_ABS5, /* type */
184 6, /* rightshift */
185 1, /* size (0 = byte, 1 = short, 2 = long) */
186 5, /* bitsize */
187 FALSE, /* pc_relative */
188 0, /* bitpos */
189 complain_overflow_bitfield,/* complain_on_overflow */
190 bfd_elf_generic_reloc, /* special_function */
191 "R_ARM_THM_ABS5", /* name */
192 FALSE, /* partial_inplace */
193 0x000007e0, /* src_mask */
194 0x000007e0, /* dst_mask */
195 FALSE), /* pcrel_offset */
196
197 /* 8 bit absolute */
198 HOWTO (R_ARM_ABS8, /* type */
199 0, /* rightshift */
200 0, /* size (0 = byte, 1 = short, 2 = long) */
201 8, /* bitsize */
202 FALSE, /* pc_relative */
203 0, /* bitpos */
204 complain_overflow_bitfield,/* complain_on_overflow */
205 bfd_elf_generic_reloc, /* special_function */
206 "R_ARM_ABS8", /* name */
207 FALSE, /* partial_inplace */
208 0x000000ff, /* src_mask */
209 0x000000ff, /* dst_mask */
210 FALSE), /* pcrel_offset */
211
212 HOWTO (R_ARM_SBREL32, /* type */
213 0, /* rightshift */
214 2, /* size (0 = byte, 1 = short, 2 = long) */
215 32, /* bitsize */
216 FALSE, /* pc_relative */
217 0, /* bitpos */
218 complain_overflow_dont,/* complain_on_overflow */
219 bfd_elf_generic_reloc, /* special_function */
220 "R_ARM_SBREL32", /* name */
221 FALSE, /* partial_inplace */
222 0xffffffff, /* src_mask */
223 0xffffffff, /* dst_mask */
224 FALSE), /* pcrel_offset */
225
c19d1205 226 HOWTO (R_ARM_THM_CALL, /* type */
7f266840
DJ		 227 1, /* rightshift */
228 2, /* size (0 = byte, 1 = short, 2 = long) */
f6ebfac0 229 24, /* bitsize */
7f266840
DJ		 230 TRUE, /* pc_relative */
231 0, /* bitpos */
232 complain_overflow_signed,/* complain_on_overflow */
233 bfd_elf_generic_reloc, /* special_function */
c19d1205 234 "R_ARM_THM_CALL", /* name */
7f266840 235 FALSE, /* partial_inplace */
7f6ab9f8
AM		 236 0x07ff2fff, /* src_mask */
237 0x07ff2fff, /* dst_mask */
7f266840
DJ		 238 TRUE), /* pcrel_offset */
239
240 HOWTO (R_ARM_THM_PC8, /* type */
241 1, /* rightshift */
242 1, /* size (0 = byte, 1 = short, 2 = long) */
243 8, /* bitsize */
244 TRUE, /* pc_relative */
245 0, /* bitpos */
246 complain_overflow_signed,/* complain_on_overflow */
247 bfd_elf_generic_reloc, /* special_function */
248 "R_ARM_THM_PC8", /* name */
249 FALSE, /* partial_inplace */
250 0x000000ff, /* src_mask */
251 0x000000ff, /* dst_mask */
252 TRUE), /* pcrel_offset */
253
c19d1205 254 HOWTO (R_ARM_BREL_ADJ, /* type */
7f266840
DJ		 255 1, /* rightshift */
256 1, /* size (0 = byte, 1 = short, 2 = long) */
c19d1205
ZW		 257 32, /* bitsize */
258 FALSE, /* pc_relative */
7f266840
DJ		 259 0, /* bitpos */
260 complain_overflow_signed,/* complain_on_overflow */
261 bfd_elf_generic_reloc, /* special_function */
c19d1205 262 "R_ARM_BREL_ADJ", /* name */
7f266840 263 FALSE, /* partial_inplace */
c19d1205
ZW		 264 0xffffffff, /* src_mask */
265 0xffffffff, /* dst_mask */
266 FALSE), /* pcrel_offset */
7f266840 267
0855e32b 268 HOWTO (R_ARM_TLS_DESC, /* type */
7f266840 269 0, /* rightshift */
0855e32b
NS		 270 2, /* size (0 = byte, 1 = short, 2 = long) */
271 32, /* bitsize */
7f266840
DJ		 272 FALSE, /* pc_relative */
273 0, /* bitpos */
0855e32b 274 complain_overflow_bitfield,/* complain_on_overflow */
7f266840 275 bfd_elf_generic_reloc, /* special_function */
0855e32b 276 "R_ARM_TLS_DESC", /* name */
7f266840 277 FALSE, /* partial_inplace */
0855e32b
NS		 278 0xffffffff, /* src_mask */
279 0xffffffff, /* dst_mask */
7f266840
DJ		 280 FALSE), /* pcrel_offset */
281
282 HOWTO (R_ARM_THM_SWI8, /* type */
283 0, /* rightshift */
284 0, /* size (0 = byte, 1 = short, 2 = long) */
285 0, /* bitsize */
286 FALSE, /* pc_relative */
287 0, /* bitpos */
288 complain_overflow_signed,/* complain_on_overflow */
289 bfd_elf_generic_reloc, /* special_function */
290 "R_ARM_SWI8", /* name */
291 FALSE, /* partial_inplace */
292 0x00000000, /* src_mask */
293 0x00000000, /* dst_mask */
294 FALSE), /* pcrel_offset */
295
296 /* BLX instruction for the ARM. */
297 HOWTO (R_ARM_XPC25, /* type */
298 2, /* rightshift */
299 2, /* size (0 = byte, 1 = short, 2 = long) */
7f6ab9f8 300 24, /* bitsize */
7f266840
DJ		 301 TRUE, /* pc_relative */
302 0, /* bitpos */
303 complain_overflow_signed,/* complain_on_overflow */
304 bfd_elf_generic_reloc, /* special_function */
305 "R_ARM_XPC25", /* name */
306 FALSE, /* partial_inplace */
307 0x00ffffff, /* src_mask */
308 0x00ffffff, /* dst_mask */
309 TRUE), /* pcrel_offset */
310
311 /* BLX instruction for the Thumb. */
312 HOWTO (R_ARM_THM_XPC22, /* type */
313 2, /* rightshift */
314 2, /* size (0 = byte, 1 = short, 2 = long) */
7f6ab9f8 315 24, /* bitsize */
7f266840
DJ		 316 TRUE, /* pc_relative */
317 0, /* bitpos */
318 complain_overflow_signed,/* complain_on_overflow */
319 bfd_elf_generic_reloc, /* special_function */
320 "R_ARM_THM_XPC22", /* name */
321 FALSE, /* partial_inplace */
7f6ab9f8
AM		 322 0x07ff2fff, /* src_mask */
323 0x07ff2fff, /* dst_mask */
7f266840
DJ		 324 TRUE), /* pcrel_offset */
325
ba93b8ac 326 /* Dynamic TLS relocations. */
7f266840 327
ba93b8ac 328 HOWTO (R_ARM_TLS_DTPMOD32, /* type */
99059e56
RM		 329 0, /* rightshift */
330 2, /* size (0 = byte, 1 = short, 2 = long) */
331 32, /* bitsize */
332 FALSE, /* pc_relative */
333 0, /* bitpos */
334 complain_overflow_bitfield,/* complain_on_overflow */
335 bfd_elf_generic_reloc, /* special_function */
336 "R_ARM_TLS_DTPMOD32", /* name */
337 TRUE, /* partial_inplace */
338 0xffffffff, /* src_mask */
339 0xffffffff, /* dst_mask */
340 FALSE), /* pcrel_offset */
7f266840 341
ba93b8ac 342 HOWTO (R_ARM_TLS_DTPOFF32, /* type */
99059e56
RM		 343 0, /* rightshift */
344 2, /* size (0 = byte, 1 = short, 2 = long) */
345 32, /* bitsize */
346 FALSE, /* pc_relative */
347 0, /* bitpos */
348 complain_overflow_bitfield,/* complain_on_overflow */
349 bfd_elf_generic_reloc, /* special_function */
350 "R_ARM_TLS_DTPOFF32", /* name */
351 TRUE, /* partial_inplace */
352 0xffffffff, /* src_mask */
353 0xffffffff, /* dst_mask */
354 FALSE), /* pcrel_offset */
7f266840 355
ba93b8ac 356 HOWTO (R_ARM_TLS_TPOFF32, /* type */
99059e56
RM		 357 0, /* rightshift */
358 2, /* size (0 = byte, 1 = short, 2 = long) */
359 32, /* bitsize */
360 FALSE, /* pc_relative */
361 0, /* bitpos */
362 complain_overflow_bitfield,/* complain_on_overflow */
363 bfd_elf_generic_reloc, /* special_function */
364 "R_ARM_TLS_TPOFF32", /* name */
365 TRUE, /* partial_inplace */
366 0xffffffff, /* src_mask */
367 0xffffffff, /* dst_mask */
368 FALSE), /* pcrel_offset */
7f266840
DJ		 369
370 /* Relocs used in ARM Linux */
371
372 HOWTO (R_ARM_COPY, /* type */
99059e56
RM		 373 0, /* rightshift */
374 2, /* size (0 = byte, 1 = short, 2 = long) */
375 32, /* bitsize */
376 FALSE, /* pc_relative */
377 0, /* bitpos */
378 complain_overflow_bitfield,/* complain_on_overflow */
379 bfd_elf_generic_reloc, /* special_function */
380 "R_ARM_COPY", /* name */
381 TRUE, /* partial_inplace */
382 0xffffffff, /* src_mask */
383 0xffffffff, /* dst_mask */
384 FALSE), /* pcrel_offset */
7f266840
DJ		 385
386 HOWTO (R_ARM_GLOB_DAT, /* type */
99059e56
RM		 387 0, /* rightshift */
388 2, /* size (0 = byte, 1 = short, 2 = long) */
389 32, /* bitsize */
390 FALSE, /* pc_relative */
391 0, /* bitpos */
392 complain_overflow_bitfield,/* complain_on_overflow */
393 bfd_elf_generic_reloc, /* special_function */
394 "R_ARM_GLOB_DAT", /* name */
395 TRUE, /* partial_inplace */
396 0xffffffff, /* src_mask */
397 0xffffffff, /* dst_mask */
398 FALSE), /* pcrel_offset */
7f266840
DJ		 399
400 HOWTO (R_ARM_JUMP_SLOT, /* type */
99059e56
RM		 401 0, /* rightshift */
402 2, /* size (0 = byte, 1 = short, 2 = long) */
403 32, /* bitsize */
404 FALSE, /* pc_relative */
405 0, /* bitpos */
406 complain_overflow_bitfield,/* complain_on_overflow */
407 bfd_elf_generic_reloc, /* special_function */
408 "R_ARM_JUMP_SLOT", /* name */
409 TRUE, /* partial_inplace */
410 0xffffffff, /* src_mask */
411 0xffffffff, /* dst_mask */
412 FALSE), /* pcrel_offset */
7f266840
DJ		 413
414 HOWTO (R_ARM_RELATIVE, /* type */
99059e56
RM		 415 0, /* rightshift */
416 2, /* size (0 = byte, 1 = short, 2 = long) */
417 32, /* bitsize */
418 FALSE, /* pc_relative */
419 0, /* bitpos */
420 complain_overflow_bitfield,/* complain_on_overflow */
421 bfd_elf_generic_reloc, /* special_function */
422 "R_ARM_RELATIVE", /* name */
423 TRUE, /* partial_inplace */
424 0xffffffff, /* src_mask */
425 0xffffffff, /* dst_mask */
426 FALSE), /* pcrel_offset */
7f266840 427
c19d1205 428 HOWTO (R_ARM_GOTOFF32, /* type */
99059e56
RM		 429 0, /* rightshift */
430 2, /* size (0 = byte, 1 = short, 2 = long) */
431 32, /* bitsize */
432 FALSE, /* pc_relative */
433 0, /* bitpos */
434 complain_overflow_bitfield,/* complain_on_overflow */
435 bfd_elf_generic_reloc, /* special_function */
436 "R_ARM_GOTOFF32", /* name */
437 TRUE, /* partial_inplace */
438 0xffffffff, /* src_mask */
439 0xffffffff, /* dst_mask */
440 FALSE), /* pcrel_offset */
7f266840
DJ		 441
442 HOWTO (R_ARM_GOTPC, /* type */
99059e56
RM		 443 0, /* rightshift */
444 2, /* size (0 = byte, 1 = short, 2 = long) */
445 32, /* bitsize */
446 TRUE, /* pc_relative */
447 0, /* bitpos */
448 complain_overflow_bitfield,/* complain_on_overflow */
449 bfd_elf_generic_reloc, /* special_function */
450 "R_ARM_GOTPC", /* name */
451 TRUE, /* partial_inplace */
452 0xffffffff, /* src_mask */
453 0xffffffff, /* dst_mask */
454 TRUE), /* pcrel_offset */
7f266840
DJ		 455
456 HOWTO (R_ARM_GOT32, /* type */
99059e56
RM		 457 0, /* rightshift */
458 2, /* size (0 = byte, 1 = short, 2 = long) */
459 32, /* bitsize */
460 FALSE, /* pc_relative */
461 0, /* bitpos */
462 complain_overflow_bitfield,/* complain_on_overflow */
463 bfd_elf_generic_reloc, /* special_function */
464 "R_ARM_GOT32", /* name */
465 TRUE, /* partial_inplace */
466 0xffffffff, /* src_mask */
467 0xffffffff, /* dst_mask */
468 FALSE), /* pcrel_offset */
7f266840
DJ		 469
470 HOWTO (R_ARM_PLT32, /* type */
99059e56
RM		 471 2, /* rightshift */
472 2, /* size (0 = byte, 1 = short, 2 = long) */
473 24, /* bitsize */
474 TRUE, /* pc_relative */
475 0, /* bitpos */
476 complain_overflow_bitfield,/* complain_on_overflow */
477 bfd_elf_generic_reloc, /* special_function */
478 "R_ARM_PLT32", /* name */
479 FALSE, /* partial_inplace */
480 0x00ffffff, /* src_mask */
481 0x00ffffff, /* dst_mask */
482 TRUE), /* pcrel_offset */
7f266840
DJ		 483
484 HOWTO (R_ARM_CALL, /* type */
485 2, /* rightshift */
486 2, /* size (0 = byte, 1 = short, 2 = long) */
487 24, /* bitsize */
488 TRUE, /* pc_relative */
489 0, /* bitpos */
490 complain_overflow_signed,/* complain_on_overflow */
491 bfd_elf_generic_reloc, /* special_function */
492 "R_ARM_CALL", /* name */
493 FALSE, /* partial_inplace */
494 0x00ffffff, /* src_mask */
495 0x00ffffff, /* dst_mask */
496 TRUE), /* pcrel_offset */
497
498 HOWTO (R_ARM_JUMP24, /* type */
499 2, /* rightshift */
500 2, /* size (0 = byte, 1 = short, 2 = long) */
501 24, /* bitsize */
502 TRUE, /* pc_relative */
503 0, /* bitpos */
504 complain_overflow_signed,/* complain_on_overflow */
505 bfd_elf_generic_reloc, /* special_function */
506 "R_ARM_JUMP24", /* name */
507 FALSE, /* partial_inplace */
508 0x00ffffff, /* src_mask */
509 0x00ffffff, /* dst_mask */
510 TRUE), /* pcrel_offset */
511
c19d1205
ZW		 512 HOWTO (R_ARM_THM_JUMP24, /* type */
513 1, /* rightshift */
514 2, /* size (0 = byte, 1 = short, 2 = long) */
515 24, /* bitsize */
516 TRUE, /* pc_relative */
7f266840 517 0, /* bitpos */
c19d1205 518 complain_overflow_signed,/* complain_on_overflow */
7f266840 519 bfd_elf_generic_reloc, /* special_function */
c19d1205 520 "R_ARM_THM_JUMP24", /* name */
7f266840 521 FALSE, /* partial_inplace */
c19d1205
ZW		 522 0x07ff2fff, /* src_mask */
523 0x07ff2fff, /* dst_mask */
524 TRUE), /* pcrel_offset */
7f266840 525
c19d1205 526 HOWTO (R_ARM_BASE_ABS, /* type */
7f266840 527 0, /* rightshift */
c19d1205
ZW		 528 2, /* size (0 = byte, 1 = short, 2 = long) */
529 32, /* bitsize */
7f266840
DJ		 530 FALSE, /* pc_relative */
531 0, /* bitpos */
532 complain_overflow_dont,/* complain_on_overflow */
533 bfd_elf_generic_reloc, /* special_function */
c19d1205 534 "R_ARM_BASE_ABS", /* name */
7f266840 535 FALSE, /* partial_inplace */
c19d1205
ZW		 536 0xffffffff, /* src_mask */
537 0xffffffff, /* dst_mask */
7f266840
DJ		 538 FALSE), /* pcrel_offset */
539
540 HOWTO (R_ARM_ALU_PCREL7_0, /* type */
541 0, /* rightshift */
542 2, /* size (0 = byte, 1 = short, 2 = long) */
543 12, /* bitsize */
544 TRUE, /* pc_relative */
545 0, /* bitpos */
546 complain_overflow_dont,/* complain_on_overflow */
547 bfd_elf_generic_reloc, /* special_function */
548 "R_ARM_ALU_PCREL_7_0", /* name */
549 FALSE, /* partial_inplace */
550 0x00000fff, /* src_mask */
551 0x00000fff, /* dst_mask */
552 TRUE), /* pcrel_offset */
553
554 HOWTO (R_ARM_ALU_PCREL15_8, /* type */
555 0, /* rightshift */
556 2, /* size (0 = byte, 1 = short, 2 = long) */
557 12, /* bitsize */
558 TRUE, /* pc_relative */
559 8, /* bitpos */
560 complain_overflow_dont,/* complain_on_overflow */
561 bfd_elf_generic_reloc, /* special_function */
562 "R_ARM_ALU_PCREL_15_8",/* name */
563 FALSE, /* partial_inplace */
564 0x00000fff, /* src_mask */
565 0x00000fff, /* dst_mask */
566 TRUE), /* pcrel_offset */
567
568 HOWTO (R_ARM_ALU_PCREL23_15, /* type */
569 0, /* rightshift */
570 2, /* size (0 = byte, 1 = short, 2 = long) */
571 12, /* bitsize */
572 TRUE, /* pc_relative */
573 16, /* bitpos */
574 complain_overflow_dont,/* complain_on_overflow */
575 bfd_elf_generic_reloc, /* special_function */
576 "R_ARM_ALU_PCREL_23_15",/* name */
577 FALSE, /* partial_inplace */
578 0x00000fff, /* src_mask */
579 0x00000fff, /* dst_mask */
580 TRUE), /* pcrel_offset */
581
582 HOWTO (R_ARM_LDR_SBREL_11_0, /* type */
583 0, /* rightshift */
584 2, /* size (0 = byte, 1 = short, 2 = long) */
585 12, /* bitsize */
586 FALSE, /* pc_relative */
587 0, /* bitpos */
588 complain_overflow_dont,/* complain_on_overflow */
589 bfd_elf_generic_reloc, /* special_function */
590 "R_ARM_LDR_SBREL_11_0",/* name */
591 FALSE, /* partial_inplace */
592 0x00000fff, /* src_mask */
593 0x00000fff, /* dst_mask */
594 FALSE), /* pcrel_offset */
595
596 HOWTO (R_ARM_ALU_SBREL_19_12, /* type */
597 0, /* rightshift */
598 2, /* size (0 = byte, 1 = short, 2 = long) */
599 8, /* bitsize */
600 FALSE, /* pc_relative */
601 12, /* bitpos */
602 complain_overflow_dont,/* complain_on_overflow */
603 bfd_elf_generic_reloc, /* special_function */
604 "R_ARM_ALU_SBREL_19_12",/* name */
605 FALSE, /* partial_inplace */
606 0x000ff000, /* src_mask */
607 0x000ff000, /* dst_mask */
608 FALSE), /* pcrel_offset */
609
610 HOWTO (R_ARM_ALU_SBREL_27_20, /* type */
611 0, /* rightshift */
612 2, /* size (0 = byte, 1 = short, 2 = long) */
613 8, /* bitsize */
614 FALSE, /* pc_relative */
615 20, /* bitpos */
616 complain_overflow_dont,/* complain_on_overflow */
617 bfd_elf_generic_reloc, /* special_function */
618 "R_ARM_ALU_SBREL_27_20",/* name */
619 FALSE, /* partial_inplace */
620 0x0ff00000, /* src_mask */
621 0x0ff00000, /* dst_mask */
622 FALSE), /* pcrel_offset */
623
624 HOWTO (R_ARM_TARGET1, /* type */
625 0, /* rightshift */
626 2, /* size (0 = byte, 1 = short, 2 = long) */
627 32, /* bitsize */
628 FALSE, /* pc_relative */
629 0, /* bitpos */
630 complain_overflow_dont,/* complain_on_overflow */
631 bfd_elf_generic_reloc, /* special_function */
632 "R_ARM_TARGET1", /* name */
633 FALSE, /* partial_inplace */
634 0xffffffff, /* src_mask */
635 0xffffffff, /* dst_mask */
636 FALSE), /* pcrel_offset */
637
638 HOWTO (R_ARM_ROSEGREL32, /* type */
639 0, /* rightshift */
640 2, /* size (0 = byte, 1 = short, 2 = long) */
641 32, /* bitsize */
642 FALSE, /* pc_relative */
643 0, /* bitpos */
644 complain_overflow_dont,/* complain_on_overflow */
645 bfd_elf_generic_reloc, /* special_function */
646 "R_ARM_ROSEGREL32", /* name */
647 FALSE, /* partial_inplace */
648 0xffffffff, /* src_mask */
649 0xffffffff, /* dst_mask */
650 FALSE), /* pcrel_offset */
651
652 HOWTO (R_ARM_V4BX, /* type */
653 0, /* rightshift */
654 2, /* size (0 = byte, 1 = short, 2 = long) */
655 32, /* bitsize */
656 FALSE, /* pc_relative */
657 0, /* bitpos */
658 complain_overflow_dont,/* complain_on_overflow */
659 bfd_elf_generic_reloc, /* special_function */
660 "R_ARM_V4BX", /* name */
661 FALSE, /* partial_inplace */
662 0xffffffff, /* src_mask */
663 0xffffffff, /* dst_mask */
664 FALSE), /* pcrel_offset */
665
666 HOWTO (R_ARM_TARGET2, /* type */
667 0, /* rightshift */
668 2, /* size (0 = byte, 1 = short, 2 = long) */
669 32, /* bitsize */
670 FALSE, /* pc_relative */
671 0, /* bitpos */
672 complain_overflow_signed,/* complain_on_overflow */
673 bfd_elf_generic_reloc, /* special_function */
674 "R_ARM_TARGET2", /* name */
675 FALSE, /* partial_inplace */
676 0xffffffff, /* src_mask */
677 0xffffffff, /* dst_mask */
678 TRUE), /* pcrel_offset */
679
680 HOWTO (R_ARM_PREL31, /* type */
681 0, /* rightshift */
682 2, /* size (0 = byte, 1 = short, 2 = long) */
683 31, /* bitsize */
684 TRUE, /* pc_relative */
685 0, /* bitpos */
686 complain_overflow_signed,/* complain_on_overflow */
687 bfd_elf_generic_reloc, /* special_function */
688 "R_ARM_PREL31", /* name */
689 FALSE, /* partial_inplace */
690 0x7fffffff, /* src_mask */
691 0x7fffffff, /* dst_mask */
692 TRUE), /* pcrel_offset */
c19d1205
ZW		 693
694 HOWTO (R_ARM_MOVW_ABS_NC, /* type */
695 0, /* rightshift */
696 2, /* size (0 = byte, 1 = short, 2 = long) */
697 16, /* bitsize */
698 FALSE, /* pc_relative */
699 0, /* bitpos */
700 complain_overflow_dont,/* complain_on_overflow */
701 bfd_elf_generic_reloc, /* special_function */
702 "R_ARM_MOVW_ABS_NC", /* name */
703 FALSE, /* partial_inplace */
39623e12
PB		 704 0x000f0fff, /* src_mask */
705 0x000f0fff, /* dst_mask */
c19d1205
ZW		 706 FALSE), /* pcrel_offset */
707
708 HOWTO (R_ARM_MOVT_ABS, /* type */
709 0, /* rightshift */
710 2, /* size (0 = byte, 1 = short, 2 = long) */
711 16, /* bitsize */
712 FALSE, /* pc_relative */
713 0, /* bitpos */
714 complain_overflow_bitfield,/* complain_on_overflow */
715 bfd_elf_generic_reloc, /* special_function */
716 "R_ARM_MOVT_ABS", /* name */
717 FALSE, /* partial_inplace */
39623e12
PB		 718 0x000f0fff, /* src_mask */
719 0x000f0fff, /* dst_mask */
c19d1205
ZW		 720 FALSE), /* pcrel_offset */
721
722 HOWTO (R_ARM_MOVW_PREL_NC, /* type */
723 0, /* rightshift */
724 2, /* size (0 = byte, 1 = short, 2 = long) */
725 16, /* bitsize */
726 TRUE, /* pc_relative */
727 0, /* bitpos */
728 complain_overflow_dont,/* complain_on_overflow */
729 bfd_elf_generic_reloc, /* special_function */
730 "R_ARM_MOVW_PREL_NC", /* name */
731 FALSE, /* partial_inplace */
39623e12
PB		 732 0x000f0fff, /* src_mask */
733 0x000f0fff, /* dst_mask */
c19d1205
ZW		 734 TRUE), /* pcrel_offset */
735
736 HOWTO (R_ARM_MOVT_PREL, /* type */
737 0, /* rightshift */
738 2, /* size (0 = byte, 1 = short, 2 = long) */
739 16, /* bitsize */
740 TRUE, /* pc_relative */
741 0, /* bitpos */
742 complain_overflow_bitfield,/* complain_on_overflow */
743 bfd_elf_generic_reloc, /* special_function */
744 "R_ARM_MOVT_PREL", /* name */
745 FALSE, /* partial_inplace */
39623e12
PB		 746 0x000f0fff, /* src_mask */
747 0x000f0fff, /* dst_mask */
c19d1205
ZW		 748 TRUE), /* pcrel_offset */
749
750 HOWTO (R_ARM_THM_MOVW_ABS_NC, /* type */
751 0, /* rightshift */
752 2, /* size (0 = byte, 1 = short, 2 = long) */
753 16, /* bitsize */
754 FALSE, /* pc_relative */
755 0, /* bitpos */
756 complain_overflow_dont,/* complain_on_overflow */
757 bfd_elf_generic_reloc, /* special_function */
758 "R_ARM_THM_MOVW_ABS_NC",/* name */
759 FALSE, /* partial_inplace */
760 0x040f70ff, /* src_mask */
761 0x040f70ff, /* dst_mask */
762 FALSE), /* pcrel_offset */
763
764 HOWTO (R_ARM_THM_MOVT_ABS, /* type */
765 0, /* rightshift */
766 2, /* size (0 = byte, 1 = short, 2 = long) */
767 16, /* bitsize */
768 FALSE, /* pc_relative */
769 0, /* bitpos */
770 complain_overflow_bitfield,/* complain_on_overflow */
771 bfd_elf_generic_reloc, /* special_function */
772 "R_ARM_THM_MOVT_ABS", /* name */
773 FALSE, /* partial_inplace */
774 0x040f70ff, /* src_mask */
775 0x040f70ff, /* dst_mask */
776 FALSE), /* pcrel_offset */
777
778 HOWTO (R_ARM_THM_MOVW_PREL_NC,/* type */
779 0, /* rightshift */
780 2, /* size (0 = byte, 1 = short, 2 = long) */
781 16, /* bitsize */
782 TRUE, /* pc_relative */
783 0, /* bitpos */
784 complain_overflow_dont,/* complain_on_overflow */
785 bfd_elf_generic_reloc, /* special_function */
786 "R_ARM_THM_MOVW_PREL_NC",/* name */
787 FALSE, /* partial_inplace */
788 0x040f70ff, /* src_mask */
789 0x040f70ff, /* dst_mask */
790 TRUE), /* pcrel_offset */
791
792 HOWTO (R_ARM_THM_MOVT_PREL, /* type */
793 0, /* rightshift */
794 2, /* size (0 = byte, 1 = short, 2 = long) */
795 16, /* bitsize */
796 TRUE, /* pc_relative */
797 0, /* bitpos */
798 complain_overflow_bitfield,/* complain_on_overflow */
799 bfd_elf_generic_reloc, /* special_function */
800 "R_ARM_THM_MOVT_PREL", /* name */
801 FALSE, /* partial_inplace */
802 0x040f70ff, /* src_mask */
803 0x040f70ff, /* dst_mask */
804 TRUE), /* pcrel_offset */
805
806 HOWTO (R_ARM_THM_JUMP19, /* type */
807 1, /* rightshift */
808 2, /* size (0 = byte, 1 = short, 2 = long) */
809 19, /* bitsize */
810 TRUE, /* pc_relative */
811 0, /* bitpos */
812 complain_overflow_signed,/* complain_on_overflow */
813 bfd_elf_generic_reloc, /* special_function */
814 "R_ARM_THM_JUMP19", /* name */
815 FALSE, /* partial_inplace */
816 0x043f2fff, /* src_mask */
817 0x043f2fff, /* dst_mask */
818 TRUE), /* pcrel_offset */
819
820 HOWTO (R_ARM_THM_JUMP6, /* type */
821 1, /* rightshift */
822 1, /* size (0 = byte, 1 = short, 2 = long) */
823 6, /* bitsize */
824 TRUE, /* pc_relative */
825 0, /* bitpos */
826 complain_overflow_unsigned,/* complain_on_overflow */
827 bfd_elf_generic_reloc, /* special_function */
828 "R_ARM_THM_JUMP6", /* name */
829 FALSE, /* partial_inplace */
830 0x02f8, /* src_mask */
831 0x02f8, /* dst_mask */
832 TRUE), /* pcrel_offset */
833
834 /* These are declared as 13-bit signed relocations because we can
835 address -4095 .. 4095(base) by altering ADDW to SUBW or vice
836 versa. */
837 HOWTO (R_ARM_THM_ALU_PREL_11_0,/* type */
838 0, /* rightshift */
839 2, /* size (0 = byte, 1 = short, 2 = long) */
840 13, /* bitsize */
841 TRUE, /* pc_relative */
842 0, /* bitpos */
2cab6cc3 843 complain_overflow_dont,/* complain_on_overflow */
c19d1205
ZW		 844 bfd_elf_generic_reloc, /* special_function */
845 "R_ARM_THM_ALU_PREL_11_0",/* name */
846 FALSE, /* partial_inplace */
2cab6cc3
MS		 847 0xffffffff, /* src_mask */
848 0xffffffff, /* dst_mask */
c19d1205
ZW		 849 TRUE), /* pcrel_offset */
850
851 HOWTO (R_ARM_THM_PC12, /* type */
852 0, /* rightshift */
853 2, /* size (0 = byte, 1 = short, 2 = long) */
854 13, /* bitsize */
855 TRUE, /* pc_relative */
856 0, /* bitpos */
2cab6cc3 857 complain_overflow_dont,/* complain_on_overflow */
c19d1205
ZW		 858 bfd_elf_generic_reloc, /* special_function */
859 "R_ARM_THM_PC12", /* name */
860 FALSE, /* partial_inplace */
2cab6cc3
MS		 861 0xffffffff, /* src_mask */
862 0xffffffff, /* dst_mask */
c19d1205
ZW		 863 TRUE), /* pcrel_offset */
864
865 HOWTO (R_ARM_ABS32_NOI, /* type */
866 0, /* rightshift */
867 2, /* size (0 = byte, 1 = short, 2 = long) */
868 32, /* bitsize */
869 FALSE, /* pc_relative */
870 0, /* bitpos */
871 complain_overflow_dont,/* complain_on_overflow */
872 bfd_elf_generic_reloc, /* special_function */
873 "R_ARM_ABS32_NOI", /* name */
874 FALSE, /* partial_inplace */
875 0xffffffff, /* src_mask */
876 0xffffffff, /* dst_mask */
877 FALSE), /* pcrel_offset */
878
879 HOWTO (R_ARM_REL32_NOI, /* type */
880 0, /* rightshift */
881 2, /* size (0 = byte, 1 = short, 2 = long) */
882 32, /* bitsize */
883 TRUE, /* pc_relative */
884 0, /* bitpos */
885 complain_overflow_dont,/* complain_on_overflow */
886 bfd_elf_generic_reloc, /* special_function */
887 "R_ARM_REL32_NOI", /* name */
888 FALSE, /* partial_inplace */
889 0xffffffff, /* src_mask */
890 0xffffffff, /* dst_mask */
891 FALSE), /* pcrel_offset */
7f266840 892
4962c51a
MS		 893 /* Group relocations. */
894
895 HOWTO (R_ARM_ALU_PC_G0_NC, /* type */
896 0, /* rightshift */
897 2, /* size (0 = byte, 1 = short, 2 = long) */
898 32, /* bitsize */
899 TRUE, /* pc_relative */
900 0, /* bitpos */
901 complain_overflow_dont,/* complain_on_overflow */
902 bfd_elf_generic_reloc, /* special_function */
903 "R_ARM_ALU_PC_G0_NC", /* name */
904 FALSE, /* partial_inplace */
905 0xffffffff, /* src_mask */
906 0xffffffff, /* dst_mask */
907 TRUE), /* pcrel_offset */
908
909 HOWTO (R_ARM_ALU_PC_G0, /* type */
910 0, /* rightshift */
911 2, /* size (0 = byte, 1 = short, 2 = long) */
912 32, /* bitsize */
913 TRUE, /* pc_relative */
914 0, /* bitpos */
915 complain_overflow_dont,/* complain_on_overflow */
916 bfd_elf_generic_reloc, /* special_function */
917 "R_ARM_ALU_PC_G0", /* name */
918 FALSE, /* partial_inplace */
919 0xffffffff, /* src_mask */
920 0xffffffff, /* dst_mask */
921 TRUE), /* pcrel_offset */
922
923 HOWTO (R_ARM_ALU_PC_G1_NC, /* type */
924 0, /* rightshift */
925 2, /* size (0 = byte, 1 = short, 2 = long) */
926 32, /* bitsize */
927 TRUE, /* pc_relative */
928 0, /* bitpos */
929 complain_overflow_dont,/* complain_on_overflow */
930 bfd_elf_generic_reloc, /* special_function */
931 "R_ARM_ALU_PC_G1_NC", /* name */
932 FALSE, /* partial_inplace */
933 0xffffffff, /* src_mask */
934 0xffffffff, /* dst_mask */
935 TRUE), /* pcrel_offset */
936
937 HOWTO (R_ARM_ALU_PC_G1, /* type */
938 0, /* rightshift */
939 2, /* size (0 = byte, 1 = short, 2 = long) */
940 32, /* bitsize */
941 TRUE, /* pc_relative */
942 0, /* bitpos */
943 complain_overflow_dont,/* complain_on_overflow */
944 bfd_elf_generic_reloc, /* special_function */
945 "R_ARM_ALU_PC_G1", /* name */
946 FALSE, /* partial_inplace */
947 0xffffffff, /* src_mask */
948 0xffffffff, /* dst_mask */
949 TRUE), /* pcrel_offset */
950
951 HOWTO (R_ARM_ALU_PC_G2, /* type */
952 0, /* rightshift */
953 2, /* size (0 = byte, 1 = short, 2 = long) */
954 32, /* bitsize */
955 TRUE, /* pc_relative */
956 0, /* bitpos */
957 complain_overflow_dont,/* complain_on_overflow */
958 bfd_elf_generic_reloc, /* special_function */
959 "R_ARM_ALU_PC_G2", /* name */
960 FALSE, /* partial_inplace */
961 0xffffffff, /* src_mask */
962 0xffffffff, /* dst_mask */
963 TRUE), /* pcrel_offset */
964
965 HOWTO (R_ARM_LDR_PC_G1, /* type */
966 0, /* rightshift */
967 2, /* size (0 = byte, 1 = short, 2 = long) */
968 32, /* bitsize */
969 TRUE, /* pc_relative */
970 0, /* bitpos */
971 complain_overflow_dont,/* complain_on_overflow */
972 bfd_elf_generic_reloc, /* special_function */
973 "R_ARM_LDR_PC_G1", /* name */
974 FALSE, /* partial_inplace */
975 0xffffffff, /* src_mask */
976 0xffffffff, /* dst_mask */
977 TRUE), /* pcrel_offset */
978
979 HOWTO (R_ARM_LDR_PC_G2, /* type */
980 0, /* rightshift */
981 2, /* size (0 = byte, 1 = short, 2 = long) */
982 32, /* bitsize */
983 TRUE, /* pc_relative */
984 0, /* bitpos */
985 complain_overflow_dont,/* complain_on_overflow */
986 bfd_elf_generic_reloc, /* special_function */
987 "R_ARM_LDR_PC_G2", /* name */
988 FALSE, /* partial_inplace */
989 0xffffffff, /* src_mask */
990 0xffffffff, /* dst_mask */
991 TRUE), /* pcrel_offset */
992
993 HOWTO (R_ARM_LDRS_PC_G0, /* type */
994 0, /* rightshift */
995 2, /* size (0 = byte, 1 = short, 2 = long) */
996 32, /* bitsize */
997 TRUE, /* pc_relative */
998 0, /* bitpos */
999 complain_overflow_dont,/* complain_on_overflow */
1000 bfd_elf_generic_reloc, /* special_function */
1001 "R_ARM_LDRS_PC_G0", /* name */
1002 FALSE, /* partial_inplace */
1003 0xffffffff, /* src_mask */
1004 0xffffffff, /* dst_mask */
1005 TRUE), /* pcrel_offset */
1006
1007 HOWTO (R_ARM_LDRS_PC_G1, /* type */
1008 0, /* rightshift */
1009 2, /* size (0 = byte, 1 = short, 2 = long) */
1010 32, /* bitsize */
1011 TRUE, /* pc_relative */
1012 0, /* bitpos */
1013 complain_overflow_dont,/* complain_on_overflow */
1014 bfd_elf_generic_reloc, /* special_function */
1015 "R_ARM_LDRS_PC_G1", /* name */
1016 FALSE, /* partial_inplace */
1017 0xffffffff, /* src_mask */
1018 0xffffffff, /* dst_mask */
1019 TRUE), /* pcrel_offset */
1020
1021 HOWTO (R_ARM_LDRS_PC_G2, /* type */
1022 0, /* rightshift */
1023 2, /* size (0 = byte, 1 = short, 2 = long) */
1024 32, /* bitsize */
1025 TRUE, /* pc_relative */
1026 0, /* bitpos */
1027 complain_overflow_dont,/* complain_on_overflow */
1028 bfd_elf_generic_reloc, /* special_function */
1029 "R_ARM_LDRS_PC_G2", /* name */
1030 FALSE, /* partial_inplace */
1031 0xffffffff, /* src_mask */
1032 0xffffffff, /* dst_mask */
1033 TRUE), /* pcrel_offset */
1034
1035 HOWTO (R_ARM_LDC_PC_G0, /* type */
1036 0, /* rightshift */
1037 2, /* size (0 = byte, 1 = short, 2 = long) */
1038 32, /* bitsize */
1039 TRUE, /* pc_relative */
1040 0, /* bitpos */
1041 complain_overflow_dont,/* complain_on_overflow */
1042 bfd_elf_generic_reloc, /* special_function */
1043 "R_ARM_LDC_PC_G0", /* name */
1044 FALSE, /* partial_inplace */
1045 0xffffffff, /* src_mask */
1046 0xffffffff, /* dst_mask */
1047 TRUE), /* pcrel_offset */
1048
1049 HOWTO (R_ARM_LDC_PC_G1, /* type */
1050 0, /* rightshift */
1051 2, /* size (0 = byte, 1 = short, 2 = long) */
1052 32, /* bitsize */
1053 TRUE, /* pc_relative */
1054 0, /* bitpos */
1055 complain_overflow_dont,/* complain_on_overflow */
1056 bfd_elf_generic_reloc, /* special_function */
1057 "R_ARM_LDC_PC_G1", /* name */
1058 FALSE, /* partial_inplace */
1059 0xffffffff, /* src_mask */
1060 0xffffffff, /* dst_mask */
1061 TRUE), /* pcrel_offset */
1062
1063 HOWTO (R_ARM_LDC_PC_G2, /* type */
1064 0, /* rightshift */
1065 2, /* size (0 = byte, 1 = short, 2 = long) */
1066 32, /* bitsize */
1067 TRUE, /* pc_relative */
1068 0, /* bitpos */
1069 complain_overflow_dont,/* complain_on_overflow */
1070 bfd_elf_generic_reloc, /* special_function */
1071 "R_ARM_LDC_PC_G2", /* name */
1072 FALSE, /* partial_inplace */
1073 0xffffffff, /* src_mask */
1074 0xffffffff, /* dst_mask */
1075 TRUE), /* pcrel_offset */
1076
1077 HOWTO (R_ARM_ALU_SB_G0_NC, /* type */
1078 0, /* rightshift */
1079 2, /* size (0 = byte, 1 = short, 2 = long) */
1080 32, /* bitsize */
1081 TRUE, /* pc_relative */
1082 0, /* bitpos */
1083 complain_overflow_dont,/* complain_on_overflow */
1084 bfd_elf_generic_reloc, /* special_function */
1085 "R_ARM_ALU_SB_G0_NC", /* name */
1086 FALSE, /* partial_inplace */
1087 0xffffffff, /* src_mask */
1088 0xffffffff, /* dst_mask */
1089 TRUE), /* pcrel_offset */
1090
1091 HOWTO (R_ARM_ALU_SB_G0, /* type */
1092 0, /* rightshift */
1093 2, /* size (0 = byte, 1 = short, 2 = long) */
1094 32, /* bitsize */
1095 TRUE, /* pc_relative */
1096 0, /* bitpos */
1097 complain_overflow_dont,/* complain_on_overflow */
1098 bfd_elf_generic_reloc, /* special_function */
1099 "R_ARM_ALU_SB_G0", /* name */
1100 FALSE, /* partial_inplace */
1101 0xffffffff, /* src_mask */
1102 0xffffffff, /* dst_mask */
1103 TRUE), /* pcrel_offset */
1104
1105 HOWTO (R_ARM_ALU_SB_G1_NC, /* type */
1106 0, /* rightshift */
1107 2, /* size (0 = byte, 1 = short, 2 = long) */
1108 32, /* bitsize */
1109 TRUE, /* pc_relative */
1110 0, /* bitpos */
1111 complain_overflow_dont,/* complain_on_overflow */
1112 bfd_elf_generic_reloc, /* special_function */
1113 "R_ARM_ALU_SB_G1_NC", /* name */
1114 FALSE, /* partial_inplace */
1115 0xffffffff, /* src_mask */
1116 0xffffffff, /* dst_mask */
1117 TRUE), /* pcrel_offset */
1118
1119 HOWTO (R_ARM_ALU_SB_G1, /* type */
1120 0, /* rightshift */
1121 2, /* size (0 = byte, 1 = short, 2 = long) */
1122 32, /* bitsize */
1123 TRUE, /* pc_relative */
1124 0, /* bitpos */
1125 complain_overflow_dont,/* complain_on_overflow */
1126 bfd_elf_generic_reloc, /* special_function */
1127 "R_ARM_ALU_SB_G1", /* name */
1128 FALSE, /* partial_inplace */
1129 0xffffffff, /* src_mask */
1130 0xffffffff, /* dst_mask */
1131 TRUE), /* pcrel_offset */
1132
1133 HOWTO (R_ARM_ALU_SB_G2, /* type */
1134 0, /* rightshift */
1135 2, /* size (0 = byte, 1 = short, 2 = long) */
1136 32, /* bitsize */
1137 TRUE, /* pc_relative */
1138 0, /* bitpos */
1139 complain_overflow_dont,/* complain_on_overflow */
1140 bfd_elf_generic_reloc, /* special_function */
1141 "R_ARM_ALU_SB_G2", /* name */
1142 FALSE, /* partial_inplace */
1143 0xffffffff, /* src_mask */
1144 0xffffffff, /* dst_mask */
1145 TRUE), /* pcrel_offset */
1146
1147 HOWTO (R_ARM_LDR_SB_G0, /* type */
1148 0, /* rightshift */
1149 2, /* size (0 = byte, 1 = short, 2 = long) */
1150 32, /* bitsize */
1151 TRUE, /* pc_relative */
1152 0, /* bitpos */
1153 complain_overflow_dont,/* complain_on_overflow */
1154 bfd_elf_generic_reloc, /* special_function */
1155 "R_ARM_LDR_SB_G0", /* name */
1156 FALSE, /* partial_inplace */
1157 0xffffffff, /* src_mask */
1158 0xffffffff, /* dst_mask */
1159 TRUE), /* pcrel_offset */
1160
1161 HOWTO (R_ARM_LDR_SB_G1, /* type */
1162 0, /* rightshift */
1163 2, /* size (0 = byte, 1 = short, 2 = long) */
1164 32, /* bitsize */
1165 TRUE, /* pc_relative */
1166 0, /* bitpos */
1167 complain_overflow_dont,/* complain_on_overflow */
1168 bfd_elf_generic_reloc, /* special_function */
1169 "R_ARM_LDR_SB_G1", /* name */
1170 FALSE, /* partial_inplace */
1171 0xffffffff, /* src_mask */
1172 0xffffffff, /* dst_mask */
1173 TRUE), /* pcrel_offset */
1174
1175 HOWTO (R_ARM_LDR_SB_G2, /* type */
1176 0, /* rightshift */
1177 2, /* size (0 = byte, 1 = short, 2 = long) */
1178 32, /* bitsize */
1179 TRUE, /* pc_relative */
1180 0, /* bitpos */
1181 complain_overflow_dont,/* complain_on_overflow */
1182 bfd_elf_generic_reloc, /* special_function */
1183 "R_ARM_LDR_SB_G2", /* name */
1184 FALSE, /* partial_inplace */
1185 0xffffffff, /* src_mask */
1186 0xffffffff, /* dst_mask */
1187 TRUE), /* pcrel_offset */
1188
1189 HOWTO (R_ARM_LDRS_SB_G0, /* type */
1190 0, /* rightshift */
1191 2, /* size (0 = byte, 1 = short, 2 = long) */
1192 32, /* bitsize */
1193 TRUE, /* pc_relative */
1194 0, /* bitpos */
1195 complain_overflow_dont,/* complain_on_overflow */
1196 bfd_elf_generic_reloc, /* special_function */
1197 "R_ARM_LDRS_SB_G0", /* name */
1198 FALSE, /* partial_inplace */
1199 0xffffffff, /* src_mask */
1200 0xffffffff, /* dst_mask */
1201 TRUE), /* pcrel_offset */
1202
1203 HOWTO (R_ARM_LDRS_SB_G1, /* type */
1204 0, /* rightshift */
1205 2, /* size (0 = byte, 1 = short, 2 = long) */
1206 32, /* bitsize */
1207 TRUE, /* pc_relative */
1208 0, /* bitpos */
1209 complain_overflow_dont,/* complain_on_overflow */
1210 bfd_elf_generic_reloc, /* special_function */
1211 "R_ARM_LDRS_SB_G1", /* name */
1212 FALSE, /* partial_inplace */
1213 0xffffffff, /* src_mask */
1214 0xffffffff, /* dst_mask */
1215 TRUE), /* pcrel_offset */
1216
1217 HOWTO (R_ARM_LDRS_SB_G2, /* type */
1218 0, /* rightshift */
1219 2, /* size (0 = byte, 1 = short, 2 = long) */
1220 32, /* bitsize */
1221 TRUE, /* pc_relative */
1222 0, /* bitpos */
1223 complain_overflow_dont,/* complain_on_overflow */
1224 bfd_elf_generic_reloc, /* special_function */
1225 "R_ARM_LDRS_SB_G2", /* name */
1226 FALSE, /* partial_inplace */
1227 0xffffffff, /* src_mask */
1228 0xffffffff, /* dst_mask */
1229 TRUE), /* pcrel_offset */
1230
1231 HOWTO (R_ARM_LDC_SB_G0, /* type */
1232 0, /* rightshift */
1233 2, /* size (0 = byte, 1 = short, 2 = long) */
1234 32, /* bitsize */
1235 TRUE, /* pc_relative */
1236 0, /* bitpos */
1237 complain_overflow_dont,/* complain_on_overflow */
1238 bfd_elf_generic_reloc, /* special_function */
1239 "R_ARM_LDC_SB_G0", /* name */
1240 FALSE, /* partial_inplace */
1241 0xffffffff, /* src_mask */
1242 0xffffffff, /* dst_mask */
1243 TRUE), /* pcrel_offset */
1244
1245 HOWTO (R_ARM_LDC_SB_G1, /* type */
1246 0, /* rightshift */
1247 2, /* size (0 = byte, 1 = short, 2 = long) */
1248 32, /* bitsize */
1249 TRUE, /* pc_relative */
1250 0, /* bitpos */
1251 complain_overflow_dont,/* complain_on_overflow */
1252 bfd_elf_generic_reloc, /* special_function */
1253 "R_ARM_LDC_SB_G1", /* name */
1254 FALSE, /* partial_inplace */
1255 0xffffffff, /* src_mask */
1256 0xffffffff, /* dst_mask */
1257 TRUE), /* pcrel_offset */
1258
1259 HOWTO (R_ARM_LDC_SB_G2, /* type */
1260 0, /* rightshift */
1261 2, /* size (0 = byte, 1 = short, 2 = long) */
1262 32, /* bitsize */
1263 TRUE, /* pc_relative */
1264 0, /* bitpos */
1265 complain_overflow_dont,/* complain_on_overflow */
1266 bfd_elf_generic_reloc, /* special_function */
1267 "R_ARM_LDC_SB_G2", /* name */
1268 FALSE, /* partial_inplace */
1269 0xffffffff, /* src_mask */
1270 0xffffffff, /* dst_mask */
1271 TRUE), /* pcrel_offset */
1272
1273 /* End of group relocations. */
c19d1205 1274
c19d1205
ZW		 1275 HOWTO (R_ARM_MOVW_BREL_NC, /* type */
1276 0, /* rightshift */
1277 2, /* size (0 = byte, 1 = short, 2 = long) */
1278 16, /* bitsize */
1279 FALSE, /* pc_relative */
1280 0, /* bitpos */
1281 complain_overflow_dont,/* complain_on_overflow */
1282 bfd_elf_generic_reloc, /* special_function */
1283 "R_ARM_MOVW_BREL_NC", /* name */
1284 FALSE, /* partial_inplace */
1285 0x0000ffff, /* src_mask */
1286 0x0000ffff, /* dst_mask */
1287 FALSE), /* pcrel_offset */
1288
1289 HOWTO (R_ARM_MOVT_BREL, /* type */
1290 0, /* rightshift */
1291 2, /* size (0 = byte, 1 = short, 2 = long) */
1292 16, /* bitsize */
1293 FALSE, /* pc_relative */
1294 0, /* bitpos */
1295 complain_overflow_bitfield,/* complain_on_overflow */
1296 bfd_elf_generic_reloc, /* special_function */
1297 "R_ARM_MOVT_BREL", /* name */
1298 FALSE, /* partial_inplace */
1299 0x0000ffff, /* src_mask */
1300 0x0000ffff, /* dst_mask */
1301 FALSE), /* pcrel_offset */
1302
1303 HOWTO (R_ARM_MOVW_BREL, /* type */
1304 0, /* rightshift */
1305 2, /* size (0 = byte, 1 = short, 2 = long) */
1306 16, /* bitsize */
1307 FALSE, /* pc_relative */
1308 0, /* bitpos */
1309 complain_overflow_dont,/* complain_on_overflow */
1310 bfd_elf_generic_reloc, /* special_function */
1311 "R_ARM_MOVW_BREL", /* name */
1312 FALSE, /* partial_inplace */
1313 0x0000ffff, /* src_mask */
1314 0x0000ffff, /* dst_mask */
1315 FALSE), /* pcrel_offset */
1316
1317 HOWTO (R_ARM_THM_MOVW_BREL_NC,/* type */
1318 0, /* rightshift */
1319 2, /* size (0 = byte, 1 = short, 2 = long) */
1320 16, /* bitsize */
1321 FALSE, /* pc_relative */
1322 0, /* bitpos */
1323 complain_overflow_dont,/* complain_on_overflow */
1324 bfd_elf_generic_reloc, /* special_function */
1325 "R_ARM_THM_MOVW_BREL_NC",/* name */
1326 FALSE, /* partial_inplace */
1327 0x040f70ff, /* src_mask */
1328 0x040f70ff, /* dst_mask */
1329 FALSE), /* pcrel_offset */
1330
1331 HOWTO (R_ARM_THM_MOVT_BREL, /* type */
1332 0, /* rightshift */
1333 2, /* size (0 = byte, 1 = short, 2 = long) */
1334 16, /* bitsize */
1335 FALSE, /* pc_relative */
1336 0, /* bitpos */
1337 complain_overflow_bitfield,/* complain_on_overflow */
1338 bfd_elf_generic_reloc, /* special_function */
1339 "R_ARM_THM_MOVT_BREL", /* name */
1340 FALSE, /* partial_inplace */
1341 0x040f70ff, /* src_mask */
1342 0x040f70ff, /* dst_mask */
1343 FALSE), /* pcrel_offset */
1344
1345 HOWTO (R_ARM_THM_MOVW_BREL, /* type */
1346 0, /* rightshift */
1347 2, /* size (0 = byte, 1 = short, 2 = long) */
1348 16, /* bitsize */
1349 FALSE, /* pc_relative */
1350 0, /* bitpos */
1351 complain_overflow_dont,/* complain_on_overflow */
1352 bfd_elf_generic_reloc, /* special_function */
1353 "R_ARM_THM_MOVW_BREL", /* name */
1354 FALSE, /* partial_inplace */
1355 0x040f70ff, /* src_mask */
1356 0x040f70ff, /* dst_mask */
1357 FALSE), /* pcrel_offset */
1358
0855e32b
NS		 1359 HOWTO (R_ARM_TLS_GOTDESC, /* type */
1360 0, /* rightshift */
1361 2, /* size (0 = byte, 1 = short, 2 = long) */
1362 32, /* bitsize */
1363 FALSE, /* pc_relative */
1364 0, /* bitpos */
1365 complain_overflow_bitfield,/* complain_on_overflow */
1366 NULL, /* special_function */
1367 "R_ARM_TLS_GOTDESC", /* name */
1368 TRUE, /* partial_inplace */
1369 0xffffffff, /* src_mask */
1370 0xffffffff, /* dst_mask */
1371 FALSE), /* pcrel_offset */
1372
1373 HOWTO (R_ARM_TLS_CALL, /* type */
1374 0, /* rightshift */
1375 2, /* size (0 = byte, 1 = short, 2 = long) */
1376 24, /* bitsize */
1377 FALSE, /* pc_relative */
1378 0, /* bitpos */
1379 complain_overflow_dont,/* complain_on_overflow */
1380 bfd_elf_generic_reloc, /* special_function */
1381 "R_ARM_TLS_CALL", /* name */
1382 FALSE, /* partial_inplace */
1383 0x00ffffff, /* src_mask */
1384 0x00ffffff, /* dst_mask */
1385 FALSE), /* pcrel_offset */
1386
1387 HOWTO (R_ARM_TLS_DESCSEQ, /* type */
1388 0, /* rightshift */
1389 2, /* size (0 = byte, 1 = short, 2 = long) */
1390 0, /* bitsize */
1391 FALSE, /* pc_relative */
1392 0, /* bitpos */
1393 complain_overflow_bitfield,/* complain_on_overflow */
1394 bfd_elf_generic_reloc, /* special_function */
1395 "R_ARM_TLS_DESCSEQ", /* name */
1396 FALSE, /* partial_inplace */
1397 0x00000000, /* src_mask */
1398 0x00000000, /* dst_mask */
1399 FALSE), /* pcrel_offset */
1400
1401 HOWTO (R_ARM_THM_TLS_CALL, /* type */
1402 0, /* rightshift */
1403 2, /* size (0 = byte, 1 = short, 2 = long) */
1404 24, /* bitsize */
1405 FALSE, /* pc_relative */
1406 0, /* bitpos */
1407 complain_overflow_dont,/* complain_on_overflow */
1408 bfd_elf_generic_reloc, /* special_function */
1409 "R_ARM_THM_TLS_CALL", /* name */
1410 FALSE, /* partial_inplace */
1411 0x07ff07ff, /* src_mask */
1412 0x07ff07ff, /* dst_mask */
1413 FALSE), /* pcrel_offset */
c19d1205
ZW		 1414
1415 HOWTO (R_ARM_PLT32_ABS, /* type */
1416 0, /* rightshift */
1417 2, /* size (0 = byte, 1 = short, 2 = long) */
1418 32, /* bitsize */
1419 FALSE, /* pc_relative */
1420 0, /* bitpos */
1421 complain_overflow_dont,/* complain_on_overflow */
1422 bfd_elf_generic_reloc, /* special_function */
1423 "R_ARM_PLT32_ABS", /* name */
1424 FALSE, /* partial_inplace */
1425 0xffffffff, /* src_mask */
1426 0xffffffff, /* dst_mask */
1427 FALSE), /* pcrel_offset */
1428
1429 HOWTO (R_ARM_GOT_ABS, /* type */
1430 0, /* rightshift */
1431 2, /* size (0 = byte, 1 = short, 2 = long) */
1432 32, /* bitsize */
1433 FALSE, /* pc_relative */
1434 0, /* bitpos */
1435 complain_overflow_dont,/* complain_on_overflow */
1436 bfd_elf_generic_reloc, /* special_function */
1437 "R_ARM_GOT_ABS", /* name */
1438 FALSE, /* partial_inplace */
1439 0xffffffff, /* src_mask */
1440 0xffffffff, /* dst_mask */
1441 FALSE), /* pcrel_offset */
1442
1443 HOWTO (R_ARM_GOT_PREL, /* type */
1444 0, /* rightshift */
1445 2, /* size (0 = byte, 1 = short, 2 = long) */
1446 32, /* bitsize */
1447 TRUE, /* pc_relative */
1448 0, /* bitpos */
1449 complain_overflow_dont, /* complain_on_overflow */
1450 bfd_elf_generic_reloc, /* special_function */
1451 "R_ARM_GOT_PREL", /* name */
1452 FALSE, /* partial_inplace */
1453 0xffffffff, /* src_mask */
1454 0xffffffff, /* dst_mask */
1455 TRUE), /* pcrel_offset */
1456
1457 HOWTO (R_ARM_GOT_BREL12, /* type */
1458 0, /* rightshift */
1459 2, /* size (0 = byte, 1 = short, 2 = long) */
1460 12, /* bitsize */
1461 FALSE, /* pc_relative */
1462 0, /* bitpos */
1463 complain_overflow_bitfield,/* complain_on_overflow */
1464 bfd_elf_generic_reloc, /* special_function */
1465 "R_ARM_GOT_BREL12", /* name */
1466 FALSE, /* partial_inplace */
1467 0x00000fff, /* src_mask */
1468 0x00000fff, /* dst_mask */
1469 FALSE), /* pcrel_offset */
1470
1471 HOWTO (R_ARM_GOTOFF12, /* type */
1472 0, /* rightshift */
1473 2, /* size (0 = byte, 1 = short, 2 = long) */
1474 12, /* bitsize */
1475 FALSE, /* pc_relative */
1476 0, /* bitpos */
1477 complain_overflow_bitfield,/* complain_on_overflow */
1478 bfd_elf_generic_reloc, /* special_function */
1479 "R_ARM_GOTOFF12", /* name */
1480 FALSE, /* partial_inplace */
1481 0x00000fff, /* src_mask */
1482 0x00000fff, /* dst_mask */
1483 FALSE), /* pcrel_offset */
1484
1485 EMPTY_HOWTO (R_ARM_GOTRELAX), /* reserved for future GOT-load optimizations */
1486
1487 /* GNU extension to record C++ vtable member usage */
1488 HOWTO (R_ARM_GNU_VTENTRY, /* type */
99059e56
RM		 1489 0, /* rightshift */
1490 2, /* size (0 = byte, 1 = short, 2 = long) */
1491 0, /* bitsize */
1492 FALSE, /* pc_relative */
1493 0, /* bitpos */
1494 complain_overflow_dont, /* complain_on_overflow */
1495 _bfd_elf_rel_vtable_reloc_fn, /* special_function */
1496 "R_ARM_GNU_VTENTRY", /* name */
1497 FALSE, /* partial_inplace */
1498 0, /* src_mask */
1499 0, /* dst_mask */
1500 FALSE), /* pcrel_offset */
c19d1205
ZW		 1501
1502 /* GNU extension to record C++ vtable hierarchy */
1503 HOWTO (R_ARM_GNU_VTINHERIT, /* type */
99059e56
RM		 1504 0, /* rightshift */
1505 2, /* size (0 = byte, 1 = short, 2 = long) */
1506 0, /* bitsize */
1507 FALSE, /* pc_relative */
1508 0, /* bitpos */
1509 complain_overflow_dont, /* complain_on_overflow */
1510 NULL, /* special_function */
1511 "R_ARM_GNU_VTINHERIT", /* name */
1512 FALSE, /* partial_inplace */
1513 0, /* src_mask */
1514 0, /* dst_mask */
1515 FALSE), /* pcrel_offset */
c19d1205
ZW		 1516
1517 HOWTO (R_ARM_THM_JUMP11, /* type */
1518 1, /* rightshift */
1519 1, /* size (0 = byte, 1 = short, 2 = long) */
1520 11, /* bitsize */
1521 TRUE, /* pc_relative */
1522 0, /* bitpos */
1523 complain_overflow_signed, /* complain_on_overflow */
1524 bfd_elf_generic_reloc, /* special_function */
1525 "R_ARM_THM_JUMP11", /* name */
1526 FALSE, /* partial_inplace */
1527 0x000007ff, /* src_mask */
1528 0x000007ff, /* dst_mask */
1529 TRUE), /* pcrel_offset */
1530
1531 HOWTO (R_ARM_THM_JUMP8, /* type */
1532 1, /* rightshift */
1533 1, /* size (0 = byte, 1 = short, 2 = long) */
1534 8, /* bitsize */
1535 TRUE, /* pc_relative */
1536 0, /* bitpos */
1537 complain_overflow_signed, /* complain_on_overflow */
1538 bfd_elf_generic_reloc, /* special_function */
1539 "R_ARM_THM_JUMP8", /* name */
1540 FALSE, /* partial_inplace */
1541 0x000000ff, /* src_mask */
1542 0x000000ff, /* dst_mask */
1543 TRUE), /* pcrel_offset */
ba93b8ac 1544
c19d1205
ZW		 1545 /* TLS relocations */
1546 HOWTO (R_ARM_TLS_GD32, /* type */
99059e56
RM		 1547 0, /* rightshift */
1548 2, /* size (0 = byte, 1 = short, 2 = long) */
1549 32, /* bitsize */
1550 FALSE, /* pc_relative */
1551 0, /* bitpos */
1552 complain_overflow_bitfield,/* complain_on_overflow */
1553 NULL, /* special_function */
1554 "R_ARM_TLS_GD32", /* name */
1555 TRUE, /* partial_inplace */
1556 0xffffffff, /* src_mask */
1557 0xffffffff, /* dst_mask */
1558 FALSE), /* pcrel_offset */
ba93b8ac 1559
ba93b8ac 1560 HOWTO (R_ARM_TLS_LDM32, /* type */
99059e56
RM		 1561 0, /* rightshift */
1562 2, /* size (0 = byte, 1 = short, 2 = long) */
1563 32, /* bitsize */
1564 FALSE, /* pc_relative */
1565 0, /* bitpos */
1566 complain_overflow_bitfield,/* complain_on_overflow */
1567 bfd_elf_generic_reloc, /* special_function */
1568 "R_ARM_TLS_LDM32", /* name */
1569 TRUE, /* partial_inplace */
1570 0xffffffff, /* src_mask */
1571 0xffffffff, /* dst_mask */
1572 FALSE), /* pcrel_offset */
ba93b8ac 1573
c19d1205 1574 HOWTO (R_ARM_TLS_LDO32, /* type */
99059e56
RM		 1575 0, /* rightshift */
1576 2, /* size (0 = byte, 1 = short, 2 = long) */
1577 32, /* bitsize */
1578 FALSE, /* pc_relative */
1579 0, /* bitpos */
1580 complain_overflow_bitfield,/* complain_on_overflow */
1581 bfd_elf_generic_reloc, /* special_function */
1582 "R_ARM_TLS_LDO32", /* name */
1583 TRUE, /* partial_inplace */
1584 0xffffffff, /* src_mask */
1585 0xffffffff, /* dst_mask */
1586 FALSE), /* pcrel_offset */
ba93b8ac 1587
ba93b8ac 1588 HOWTO (R_ARM_TLS_IE32, /* type */
99059e56
RM		 1589 0, /* rightshift */
1590 2, /* size (0 = byte, 1 = short, 2 = long) */
1591 32, /* bitsize */
1592 FALSE, /* pc_relative */
1593 0, /* bitpos */
1594 complain_overflow_bitfield,/* complain_on_overflow */
1595 NULL, /* special_function */
1596 "R_ARM_TLS_IE32", /* name */
1597 TRUE, /* partial_inplace */
1598 0xffffffff, /* src_mask */
1599 0xffffffff, /* dst_mask */
1600 FALSE), /* pcrel_offset */
7f266840 1601
c19d1205 1602 HOWTO (R_ARM_TLS_LE32, /* type */
99059e56
RM		 1603 0, /* rightshift */
1604 2, /* size (0 = byte, 1 = short, 2 = long) */
1605 32, /* bitsize */
1606 FALSE, /* pc_relative */
1607 0, /* bitpos */
1608 complain_overflow_bitfield,/* complain_on_overflow */
75c11999 1609 NULL, /* special_function */
99059e56
RM		 1610 "R_ARM_TLS_LE32", /* name */
1611 TRUE, /* partial_inplace */
1612 0xffffffff, /* src_mask */
1613 0xffffffff, /* dst_mask */
1614 FALSE), /* pcrel_offset */
7f266840 1615
c19d1205
ZW		 1616 HOWTO (R_ARM_TLS_LDO12, /* type */
1617 0, /* rightshift */
1618 2, /* size (0 = byte, 1 = short, 2 = long) */
1619 12, /* bitsize */
1620 FALSE, /* pc_relative */
7f266840 1621 0, /* bitpos */
c19d1205 1622 complain_overflow_bitfield,/* complain_on_overflow */
7f266840 1623 bfd_elf_generic_reloc, /* special_function */
c19d1205 1624 "R_ARM_TLS_LDO12", /* name */
7f266840 1625 FALSE, /* partial_inplace */
c19d1205
ZW		 1626 0x00000fff, /* src_mask */
1627 0x00000fff, /* dst_mask */
1628 FALSE), /* pcrel_offset */
7f266840 1629
c19d1205
ZW		 1630 HOWTO (R_ARM_TLS_LE12, /* type */
1631 0, /* rightshift */
1632 2, /* size (0 = byte, 1 = short, 2 = long) */
1633 12, /* bitsize */
1634 FALSE, /* pc_relative */
7f266840 1635 0, /* bitpos */
c19d1205 1636 complain_overflow_bitfield,/* complain_on_overflow */
7f266840 1637 bfd_elf_generic_reloc, /* special_function */
c19d1205 1638 "R_ARM_TLS_LE12", /* name */
7f266840 1639 FALSE, /* partial_inplace */
c19d1205
ZW		 1640 0x00000fff, /* src_mask */
1641 0x00000fff, /* dst_mask */
1642 FALSE), /* pcrel_offset */
7f266840 1643
c19d1205 1644 HOWTO (R_ARM_TLS_IE12GP, /* type */
7f266840
DJ		 1645 0, /* rightshift */
1646 2, /* size (0 = byte, 1 = short, 2 = long) */
c19d1205
ZW		 1647 12, /* bitsize */
1648 FALSE, /* pc_relative */
7f266840 1649 0, /* bitpos */
c19d1205 1650 complain_overflow_bitfield,/* complain_on_overflow */
7f266840 1651 bfd_elf_generic_reloc, /* special_function */
c19d1205 1652 "R_ARM_TLS_IE12GP", /* name */
7f266840 1653 FALSE, /* partial_inplace */
c19d1205
ZW		 1654 0x00000fff, /* src_mask */
1655 0x00000fff, /* dst_mask */
1656 FALSE), /* pcrel_offset */
0855e32b 1657
34e77a92 1658 /* 112-127 private relocations. */
0855e32b
NS		 1659 EMPTY_HOWTO (112),
1660 EMPTY_HOWTO (113),
1661 EMPTY_HOWTO (114),
1662 EMPTY_HOWTO (115),
1663 EMPTY_HOWTO (116),
1664 EMPTY_HOWTO (117),
1665 EMPTY_HOWTO (118),
1666 EMPTY_HOWTO (119),
1667 EMPTY_HOWTO (120),
1668 EMPTY_HOWTO (121),
1669 EMPTY_HOWTO (122),
1670 EMPTY_HOWTO (123),
1671 EMPTY_HOWTO (124),
1672 EMPTY_HOWTO (125),
1673 EMPTY_HOWTO (126),
1674 EMPTY_HOWTO (127),
34e77a92
RS		 1675
1676 /* R_ARM_ME_TOO, obsolete. */
0855e32b
NS		 1677 EMPTY_HOWTO (128),
1678
1679 HOWTO (R_ARM_THM_TLS_DESCSEQ, /* type */
1680 0, /* rightshift */
1681 1, /* size (0 = byte, 1 = short, 2 = long) */
1682 0, /* bitsize */
1683 FALSE, /* pc_relative */
1684 0, /* bitpos */
1685 complain_overflow_bitfield,/* complain_on_overflow */
1686 bfd_elf_generic_reloc, /* special_function */
1687 "R_ARM_THM_TLS_DESCSEQ",/* name */
1688 FALSE, /* partial_inplace */
1689 0x00000000, /* src_mask */
1690 0x00000000, /* dst_mask */
1691 FALSE), /* pcrel_offset */
72d98d16
MG		 1692 EMPTY_HOWTO (130),
1693 EMPTY_HOWTO (131),
1694 HOWTO (R_ARM_THM_ALU_ABS_G0_NC,/* type. */
1695 0, /* rightshift. */
1696 1, /* size (0 = byte, 1 = short, 2 = long). */
1697 16, /* bitsize. */
1698 FALSE, /* pc_relative. */
1699 0, /* bitpos. */
1700 complain_overflow_bitfield,/* complain_on_overflow. */
1701 bfd_elf_generic_reloc, /* special_function. */
1702 "R_ARM_THM_ALU_ABS_G0_NC",/* name. */
1703 FALSE, /* partial_inplace. */
1704 0x00000000, /* src_mask. */
1705 0x00000000, /* dst_mask. */
1706 FALSE), /* pcrel_offset. */
1707 HOWTO (R_ARM_THM_ALU_ABS_G1_NC,/* type. */
1708 0, /* rightshift. */
1709 1, /* size (0 = byte, 1 = short, 2 = long). */
1710 16, /* bitsize. */
1711 FALSE, /* pc_relative. */
1712 0, /* bitpos. */
1713 complain_overflow_bitfield,/* complain_on_overflow. */
1714 bfd_elf_generic_reloc, /* special_function. */
1715 "R_ARM_THM_ALU_ABS_G1_NC",/* name. */
1716 FALSE, /* partial_inplace. */
1717 0x00000000, /* src_mask. */
1718 0x00000000, /* dst_mask. */
1719 FALSE), /* pcrel_offset. */
1720 HOWTO (R_ARM_THM_ALU_ABS_G2_NC,/* type. */
1721 0, /* rightshift. */
1722 1, /* size (0 = byte, 1 = short, 2 = long). */
1723 16, /* bitsize. */
1724 FALSE, /* pc_relative. */
1725 0, /* bitpos. */
1726 complain_overflow_bitfield,/* complain_on_overflow. */
1727 bfd_elf_generic_reloc, /* special_function. */
1728 "R_ARM_THM_ALU_ABS_G2_NC",/* name. */
1729 FALSE, /* partial_inplace. */
1730 0x00000000, /* src_mask. */
1731 0x00000000, /* dst_mask. */
1732 FALSE), /* pcrel_offset. */
1733 HOWTO (R_ARM_THM_ALU_ABS_G3_NC,/* type. */
1734 0, /* rightshift. */
1735 1, /* size (0 = byte, 1 = short, 2 = long). */
1736 16, /* bitsize. */
1737 FALSE, /* pc_relative. */
1738 0, /* bitpos. */
1739 complain_overflow_bitfield,/* complain_on_overflow. */
1740 bfd_elf_generic_reloc, /* special_function. */
1741 "R_ARM_THM_ALU_ABS_G3_NC",/* name. */
1742 FALSE, /* partial_inplace. */
1743 0x00000000, /* src_mask. */
1744 0x00000000, /* dst_mask. */
1745 FALSE), /* pcrel_offset. */
c19d1205
ZW		 1746};
1747
34e77a92
RS		 1748/* 160 onwards: */
1749static reloc_howto_type elf32_arm_howto_table_2[1] =
1750{
1751 HOWTO (R_ARM_IRELATIVE, /* type */
99059e56
RM		 1752 0, /* rightshift */
1753 2, /* size (0 = byte, 1 = short, 2 = long) */
1754 32, /* bitsize */
1755 FALSE, /* pc_relative */
1756 0, /* bitpos */
1757 complain_overflow_bitfield,/* complain_on_overflow */
1758 bfd_elf_generic_reloc, /* special_function */
1759 "R_ARM_IRELATIVE", /* name */
1760 TRUE, /* partial_inplace */
1761 0xffffffff, /* src_mask */
1762 0xffffffff, /* dst_mask */
1763 FALSE) /* pcrel_offset */
34e77a92 1764};
c19d1205 1765
34e77a92
RS		 1766/* 249-255 extended, currently unused, relocations: */
1767static reloc_howto_type elf32_arm_howto_table_3[4] =
7f266840
DJ		 1768{
1769 HOWTO (R_ARM_RREL32, /* type */
1770 0, /* rightshift */
1771 0, /* size (0 = byte, 1 = short, 2 = long) */
1772 0, /* bitsize */
1773 FALSE, /* pc_relative */
1774 0, /* bitpos */
1775 complain_overflow_dont,/* complain_on_overflow */
1776 bfd_elf_generic_reloc, /* special_function */
1777 "R_ARM_RREL32", /* name */
1778 FALSE, /* partial_inplace */
1779 0, /* src_mask */
1780 0, /* dst_mask */
1781 FALSE), /* pcrel_offset */
1782
1783 HOWTO (R_ARM_RABS32, /* type */
1784 0, /* rightshift */
1785 0, /* size (0 = byte, 1 = short, 2 = long) */
1786 0, /* bitsize */
1787 FALSE, /* pc_relative */
1788 0, /* bitpos */
1789 complain_overflow_dont,/* complain_on_overflow */
1790 bfd_elf_generic_reloc, /* special_function */
1791 "R_ARM_RABS32", /* name */
1792 FALSE, /* partial_inplace */
1793 0, /* src_mask */
1794 0, /* dst_mask */
1795 FALSE), /* pcrel_offset */
1796
1797 HOWTO (R_ARM_RPC24, /* type */
1798 0, /* rightshift */
1799 0, /* size (0 = byte, 1 = short, 2 = long) */
1800 0, /* bitsize */
1801 FALSE, /* pc_relative */
1802 0, /* bitpos */
1803 complain_overflow_dont,/* complain_on_overflow */
1804 bfd_elf_generic_reloc, /* special_function */
1805 "R_ARM_RPC24", /* name */
1806 FALSE, /* partial_inplace */
1807 0, /* src_mask */
1808 0, /* dst_mask */
1809 FALSE), /* pcrel_offset */
1810
1811 HOWTO (R_ARM_RBASE, /* type */
1812 0, /* rightshift */
1813 0, /* size (0 = byte, 1 = short, 2 = long) */
1814 0, /* bitsize */
1815 FALSE, /* pc_relative */
1816 0, /* bitpos */
1817 complain_overflow_dont,/* complain_on_overflow */
1818 bfd_elf_generic_reloc, /* special_function */
1819 "R_ARM_RBASE", /* name */
1820 FALSE, /* partial_inplace */
1821 0, /* src_mask */
1822 0, /* dst_mask */
1823 FALSE) /* pcrel_offset */
1824};
1825
1826static reloc_howto_type *
1827elf32_arm_howto_from_type (unsigned int r_type)
1828{
906e58ca 1829 if (r_type < ARRAY_SIZE (elf32_arm_howto_table_1))
c19d1205 1830 return &elf32_arm_howto_table_1[r_type];
ba93b8ac 1831
34e77a92
RS		 1832 if (r_type == R_ARM_IRELATIVE)
1833 return &elf32_arm_howto_table_2[r_type - R_ARM_IRELATIVE];
1834
c19d1205 1835 if (r_type >= R_ARM_RREL32
34e77a92
RS		 1836 && r_type < R_ARM_RREL32 + ARRAY_SIZE (elf32_arm_howto_table_3))
1837 return &elf32_arm_howto_table_3[r_type - R_ARM_RREL32];
7f266840 1838
c19d1205 1839 return NULL;
7f266840
DJ		 1840}
1841
1842static void
1843elf32_arm_info_to_howto (bfd * abfd ATTRIBUTE_UNUSED, arelent * bfd_reloc,
1844 Elf_Internal_Rela * elf_reloc)
1845{
1846 unsigned int r_type;
1847
1848 r_type = ELF32_R_TYPE (elf_reloc->r_info);
1849 bfd_reloc->howto = elf32_arm_howto_from_type (r_type);
1850}
1851
1852struct elf32_arm_reloc_map
1853 {
1854 bfd_reloc_code_real_type bfd_reloc_val;
1855 unsigned char elf_reloc_val;
1856 };
1857
1858/* All entries in this list must also be present in elf32_arm_howto_table. */
1859static const struct elf32_arm_reloc_map elf32_arm_reloc_map[] =
1860 {
1861 {BFD_RELOC_NONE, R_ARM_NONE},
1862 {BFD_RELOC_ARM_PCREL_BRANCH, R_ARM_PC24},
39b41c9c
PB		 1863 {BFD_RELOC_ARM_PCREL_CALL, R_ARM_CALL},
1864 {BFD_RELOC_ARM_PCREL_JUMP, R_ARM_JUMP24},
7f266840
DJ		 1865 {BFD_RELOC_ARM_PCREL_BLX, R_ARM_XPC25},
1866 {BFD_RELOC_THUMB_PCREL_BLX, R_ARM_THM_XPC22},
1867 {BFD_RELOC_32, R_ARM_ABS32},
1868 {BFD_RELOC_32_PCREL, R_ARM_REL32},
1869 {BFD_RELOC_8, R_ARM_ABS8},
1870 {BFD_RELOC_16, R_ARM_ABS16},
1871 {BFD_RELOC_ARM_OFFSET_IMM, R_ARM_ABS12},
1872 {BFD_RELOC_ARM_THUMB_OFFSET, R_ARM_THM_ABS5},
c19d1205
ZW		 1873 {BFD_RELOC_THUMB_PCREL_BRANCH25, R_ARM_THM_JUMP24},
1874 {BFD_RELOC_THUMB_PCREL_BRANCH23, R_ARM_THM_CALL},
1875 {BFD_RELOC_THUMB_PCREL_BRANCH12, R_ARM_THM_JUMP11},
1876 {BFD_RELOC_THUMB_PCREL_BRANCH20, R_ARM_THM_JUMP19},
1877 {BFD_RELOC_THUMB_PCREL_BRANCH9, R_ARM_THM_JUMP8},
1878 {BFD_RELOC_THUMB_PCREL_BRANCH7, R_ARM_THM_JUMP6},
7f266840
DJ		 1879 {BFD_RELOC_ARM_GLOB_DAT, R_ARM_GLOB_DAT},
1880 {BFD_RELOC_ARM_JUMP_SLOT, R_ARM_JUMP_SLOT},
1881 {BFD_RELOC_ARM_RELATIVE, R_ARM_RELATIVE},
c19d1205 1882 {BFD_RELOC_ARM_GOTOFF, R_ARM_GOTOFF32},
7f266840 1883 {BFD_RELOC_ARM_GOTPC, R_ARM_GOTPC},
b43420e6 1884 {BFD_RELOC_ARM_GOT_PREL, R_ARM_GOT_PREL},
7f266840
DJ		 1885 {BFD_RELOC_ARM_GOT32, R_ARM_GOT32},
1886 {BFD_RELOC_ARM_PLT32, R_ARM_PLT32},
1887 {BFD_RELOC_ARM_TARGET1, R_ARM_TARGET1},
1888 {BFD_RELOC_ARM_ROSEGREL32, R_ARM_ROSEGREL32},
1889 {BFD_RELOC_ARM_SBREL32, R_ARM_SBREL32},
1890 {BFD_RELOC_ARM_PREL31, R_ARM_PREL31},
ba93b8ac
DJ		 1891 {BFD_RELOC_ARM_TARGET2, R_ARM_TARGET2},
1892 {BFD_RELOC_ARM_PLT32, R_ARM_PLT32},
0855e32b
NS		 1893 {BFD_RELOC_ARM_TLS_GOTDESC, R_ARM_TLS_GOTDESC},
1894 {BFD_RELOC_ARM_TLS_CALL, R_ARM_TLS_CALL},
1895 {BFD_RELOC_ARM_THM_TLS_CALL, R_ARM_THM_TLS_CALL},
1896 {BFD_RELOC_ARM_TLS_DESCSEQ, R_ARM_TLS_DESCSEQ},
1897 {BFD_RELOC_ARM_THM_TLS_DESCSEQ, R_ARM_THM_TLS_DESCSEQ},
1898 {BFD_RELOC_ARM_TLS_DESC, R_ARM_TLS_DESC},
ba93b8ac
DJ		 1899 {BFD_RELOC_ARM_TLS_GD32, R_ARM_TLS_GD32},
1900 {BFD_RELOC_ARM_TLS_LDO32, R_ARM_TLS_LDO32},
1901 {BFD_RELOC_ARM_TLS_LDM32, R_ARM_TLS_LDM32},
1902 {BFD_RELOC_ARM_TLS_DTPMOD32, R_ARM_TLS_DTPMOD32},
1903 {BFD_RELOC_ARM_TLS_DTPOFF32, R_ARM_TLS_DTPOFF32},
1904 {BFD_RELOC_ARM_TLS_TPOFF32, R_ARM_TLS_TPOFF32},
1905 {BFD_RELOC_ARM_TLS_IE32, R_ARM_TLS_IE32},
1906 {BFD_RELOC_ARM_TLS_LE32, R_ARM_TLS_LE32},
34e77a92 1907 {BFD_RELOC_ARM_IRELATIVE, R_ARM_IRELATIVE},
c19d1205
ZW		 1908 {BFD_RELOC_VTABLE_INHERIT, R_ARM_GNU_VTINHERIT},
1909 {BFD_RELOC_VTABLE_ENTRY, R_ARM_GNU_VTENTRY},
b6895b4f
PB		 1910 {BFD_RELOC_ARM_MOVW, R_ARM_MOVW_ABS_NC},
1911 {BFD_RELOC_ARM_MOVT, R_ARM_MOVT_ABS},
1912 {BFD_RELOC_ARM_MOVW_PCREL, R_ARM_MOVW_PREL_NC},
1913 {BFD_RELOC_ARM_MOVT_PCREL, R_ARM_MOVT_PREL},
1914 {BFD_RELOC_ARM_THUMB_MOVW, R_ARM_THM_MOVW_ABS_NC},
1915 {BFD_RELOC_ARM_THUMB_MOVT, R_ARM_THM_MOVT_ABS},
1916 {BFD_RELOC_ARM_THUMB_MOVW_PCREL, R_ARM_THM_MOVW_PREL_NC},
1917 {BFD_RELOC_ARM_THUMB_MOVT_PCREL, R_ARM_THM_MOVT_PREL},
4962c51a
MS		 1918 {BFD_RELOC_ARM_ALU_PC_G0_NC, R_ARM_ALU_PC_G0_NC},
1919 {BFD_RELOC_ARM_ALU_PC_G0, R_ARM_ALU_PC_G0},
1920 {BFD_RELOC_ARM_ALU_PC_G1_NC, R_ARM_ALU_PC_G1_NC},
1921 {BFD_RELOC_ARM_ALU_PC_G1, R_ARM_ALU_PC_G1},
1922 {BFD_RELOC_ARM_ALU_PC_G2, R_ARM_ALU_PC_G2},
1923 {BFD_RELOC_ARM_LDR_PC_G0, R_ARM_LDR_PC_G0},
1924 {BFD_RELOC_ARM_LDR_PC_G1, R_ARM_LDR_PC_G1},
1925 {BFD_RELOC_ARM_LDR_PC_G2, R_ARM_LDR_PC_G2},
1926 {BFD_RELOC_ARM_LDRS_PC_G0, R_ARM_LDRS_PC_G0},
1927 {BFD_RELOC_ARM_LDRS_PC_G1, R_ARM_LDRS_PC_G1},
1928 {BFD_RELOC_ARM_LDRS_PC_G2, R_ARM_LDRS_PC_G2},
1929 {BFD_RELOC_ARM_LDC_PC_G0, R_ARM_LDC_PC_G0},
1930 {BFD_RELOC_ARM_LDC_PC_G1, R_ARM_LDC_PC_G1},
1931 {BFD_RELOC_ARM_LDC_PC_G2, R_ARM_LDC_PC_G2},
1932 {BFD_RELOC_ARM_ALU_SB_G0_NC, R_ARM_ALU_SB_G0_NC},
1933 {BFD_RELOC_ARM_ALU_SB_G0, R_ARM_ALU_SB_G0},
1934 {BFD_RELOC_ARM_ALU_SB_G1_NC, R_ARM_ALU_SB_G1_NC},
1935 {BFD_RELOC_ARM_ALU_SB_G1, R_ARM_ALU_SB_G1},
1936 {BFD_RELOC_ARM_ALU_SB_G2, R_ARM_ALU_SB_G2},
1937 {BFD_RELOC_ARM_LDR_SB_G0, R_ARM_LDR_SB_G0},
1938 {BFD_RELOC_ARM_LDR_SB_G1, R_ARM_LDR_SB_G1},
1939 {BFD_RELOC_ARM_LDR_SB_G2, R_ARM_LDR_SB_G2},
1940 {BFD_RELOC_ARM_LDRS_SB_G0, R_ARM_LDRS_SB_G0},
1941 {BFD_RELOC_ARM_LDRS_SB_G1, R_ARM_LDRS_SB_G1},
1942 {BFD_RELOC_ARM_LDRS_SB_G2, R_ARM_LDRS_SB_G2},
1943 {BFD_RELOC_ARM_LDC_SB_G0, R_ARM_LDC_SB_G0},
1944 {BFD_RELOC_ARM_LDC_SB_G1, R_ARM_LDC_SB_G1},
845b51d6 1945 {BFD_RELOC_ARM_LDC_SB_G2, R_ARM_LDC_SB_G2},
72d98d16
MG		 1946 {BFD_RELOC_ARM_V4BX, R_ARM_V4BX},
1947 {BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC, R_ARM_THM_ALU_ABS_G3_NC},
1948 {BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC, R_ARM_THM_ALU_ABS_G2_NC},
1949 {BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC, R_ARM_THM_ALU_ABS_G1_NC},
1950 {BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC, R_ARM_THM_ALU_ABS_G0_NC}
7f266840
DJ		 1951 };
1952
1953static reloc_howto_type *
f1c71a59
ZW		 1954elf32_arm_reloc_type_lookup (bfd *abfd ATTRIBUTE_UNUSED,
1955 bfd_reloc_code_real_type code)
7f266840
DJ		 1956{
1957 unsigned int i;
8029a119 1958
906e58ca 1959 for (i = 0; i < ARRAY_SIZE (elf32_arm_reloc_map); i ++)
c19d1205
ZW		 1960 if (elf32_arm_reloc_map[i].bfd_reloc_val == code)
1961 return elf32_arm_howto_from_type (elf32_arm_reloc_map[i].elf_reloc_val);
7f266840 1962
c19d1205 1963 return NULL;
7f266840
DJ		 1964}
1965
157090f7
AM		 1966static reloc_howto_type *
1967elf32_arm_reloc_name_lookup (bfd *abfd ATTRIBUTE_UNUSED,
1968 const char *r_name)
1969{
1970 unsigned int i;
1971
906e58ca 1972 for (i = 0; i < ARRAY_SIZE (elf32_arm_howto_table_1); i++)
157090f7
AM		 1973 if (elf32_arm_howto_table_1[i].name != NULL
1974 && strcasecmp (elf32_arm_howto_table_1[i].name, r_name) == 0)
1975 return &elf32_arm_howto_table_1[i];
1976
906e58ca 1977 for (i = 0; i < ARRAY_SIZE (elf32_arm_howto_table_2); i++)
157090f7
AM		 1978 if (elf32_arm_howto_table_2[i].name != NULL
1979 && strcasecmp (elf32_arm_howto_table_2[i].name, r_name) == 0)
1980 return &elf32_arm_howto_table_2[i];
1981
34e77a92
RS		 1982 for (i = 0; i < ARRAY_SIZE (elf32_arm_howto_table_3); i++)
1983 if (elf32_arm_howto_table_3[i].name != NULL
1984 && strcasecmp (elf32_arm_howto_table_3[i].name, r_name) == 0)
1985 return &elf32_arm_howto_table_3[i];
1986
157090f7
AM		 1987 return NULL;
1988}
1989
906e58ca
NC		 1990/* Support for core dump NOTE sections. */
1991
7f266840 1992static bfd_boolean
f1c71a59 1993elf32_arm_nabi_grok_prstatus (bfd *abfd, Elf_Internal_Note *note)
7f266840
DJ		 1994{
1995 int offset;
1996 size_t size;
1997
1998 switch (note->descsz)
1999 {
2000 default:
2001 return FALSE;
2002
8029a119 2003 case 148: /* Linux/ARM 32-bit. */
7f266840 2004 /* pr_cursig */
228e534f 2005 elf_tdata (abfd)->core->signal = bfd_get_16 (abfd, note->descdata + 12);
7f266840
DJ		 2006
2007 /* pr_pid */
228e534f 2008 elf_tdata (abfd)->core->lwpid = bfd_get_32 (abfd, note->descdata + 24);
7f266840
DJ		 2009
2010 /* pr_reg */
2011 offset = 72;
2012 size = 72;
2013
2014 break;
2015 }
2016
2017 /* Make a ".reg/999" section. */
2018 return _bfd_elfcore_make_pseudosection (abfd, ".reg",
2019 size, note->descpos + offset);
2020}
2021
2022static bfd_boolean
f1c71a59 2023elf32_arm_nabi_grok_psinfo (bfd *abfd, Elf_Internal_Note *note)
7f266840
DJ		 2024{
2025 switch (note->descsz)
2026 {
2027 default:
2028 return FALSE;
2029
8029a119 2030 case 124: /* Linux/ARM elf_prpsinfo. */
228e534f 2031 elf_tdata (abfd)->core->pid
4395ee08 2032 = bfd_get_32 (abfd, note->descdata + 12);
228e534f 2033 elf_tdata (abfd)->core->program
7f266840 2034 = _bfd_elfcore_strndup (abfd, note->descdata + 28, 16);
228e534f 2035 elf_tdata (abfd)->core->command
7f266840
DJ		 2036 = _bfd_elfcore_strndup (abfd, note->descdata + 44, 80);
2037 }
2038
2039 /* Note that for some reason, a spurious space is tacked
2040 onto the end of the args in some (at least one anyway)
2041 implementations, so strip it off if it exists. */
7f266840 2042 {
228e534f 2043 char *command = elf_tdata (abfd)->core->command;
7f266840
DJ		 2044 int n = strlen (command);
2045
2046 if (0 < n && command[n - 1] == ' ')
2047 command[n - 1] = '\0';
2048 }
2049
2050 return TRUE;
2051}
2052
1f20dca5
UW		 2053static char *
2054elf32_arm_nabi_write_core_note (bfd *abfd, char *buf, int *bufsiz,
2055 int note_type, ...)
2056{
2057 switch (note_type)
2058 {
2059 default:
2060 return NULL;
2061
2062 case NT_PRPSINFO:
2063 {
2064 char data[124];
2065 va_list ap;
2066
2067 va_start (ap, note_type);
2068 memset (data, 0, sizeof (data));
2069 strncpy (data + 28, va_arg (ap, const char *), 16);
2070 strncpy (data + 44, va_arg (ap, const char *), 80);
2071 va_end (ap);
2072
2073 return elfcore_write_note (abfd, buf, bufsiz,
2074 "CORE", note_type, data, sizeof (data));
2075 }
2076
2077 case NT_PRSTATUS:
2078 {
2079 char data[148];
2080 va_list ap;
2081 long pid;
2082 int cursig;
2083 const void *greg;
2084
2085 va_start (ap, note_type);
2086 memset (data, 0, sizeof (data));
2087 pid = va_arg (ap, long);
2088 bfd_put_32 (abfd, pid, data + 24);
2089 cursig = va_arg (ap, int);
2090 bfd_put_16 (abfd, cursig, data + 12);
2091 greg = va_arg (ap, const void *);
2092 memcpy (data + 72, greg, 72);
2093 va_end (ap);
2094
2095 return elfcore_write_note (abfd, buf, bufsiz,
2096 "CORE", note_type, data, sizeof (data));
2097 }
2098 }
2099}
2100
6d00b590 2101#define TARGET_LITTLE_SYM arm_elf32_le_vec
7f266840 2102#define TARGET_LITTLE_NAME "elf32-littlearm"
6d00b590 2103#define TARGET_BIG_SYM arm_elf32_be_vec
7f266840
DJ		 2104#define TARGET_BIG_NAME "elf32-bigarm"
2105
2106#define elf_backend_grok_prstatus elf32_arm_nabi_grok_prstatus
2107#define elf_backend_grok_psinfo elf32_arm_nabi_grok_psinfo
1f20dca5 2108#define elf_backend_write_core_note elf32_arm_nabi_write_core_note
7f266840 2109
252b5132
RH		 2110typedef unsigned long int insn32;
2111typedef unsigned short int insn16;
2112
3a4a14e9
PB		 2113/* In lieu of proper flags, assume all EABIv4 or later objects are
2114 interworkable. */
57e8b36a 2115#define INTERWORK_FLAG(abfd) \
3a4a14e9 2116 (EF_ARM_EABI_VERSION (elf_elfheader (abfd)->e_flags) >= EF_ARM_EABI_VER4 \
3e6b1042
DJ		 2117 || (elf_elfheader (abfd)->e_flags & EF_ARM_INTERWORK) \
2118 || ((abfd)->flags & BFD_LINKER_CREATED))
9b485d32 2119
252b5132
RH		 2120/* The linker script knows the section names for placement.
2121 The entry_names are used to do simple name mangling on the stubs.
2122 Given a function name, and its type, the stub can be found. The
9b485d32 2123 name can be changed. The only requirement is the %s be present. */
252b5132
RH		 2124#define THUMB2ARM_GLUE_SECTION_NAME ".glue_7t"
2125#define THUMB2ARM_GLUE_ENTRY_NAME "__%s_from_thumb"
2126
2127#define ARM2THUMB_GLUE_SECTION_NAME ".glue_7"
2128#define ARM2THUMB_GLUE_ENTRY_NAME "__%s_from_arm"
2129
c7b8f16e
JB		 2130#define VFP11_ERRATUM_VENEER_SECTION_NAME ".vfp11_veneer"
2131#define VFP11_ERRATUM_VENEER_ENTRY_NAME "__vfp11_veneer_%x"
2132
a504d23a
LA		 2133#define STM32L4XX_ERRATUM_VENEER_SECTION_NAME ".text.stm32l4xx_veneer"
2134#define STM32L4XX_ERRATUM_VENEER_ENTRY_NAME "__stm32l4xx_veneer_%x"
2135
845b51d6
PB		 2136#define ARM_BX_GLUE_SECTION_NAME ".v4_bx"
2137#define ARM_BX_GLUE_ENTRY_NAME "__bx_r%d"
2138
7413f23f
DJ		 2139#define STUB_ENTRY_NAME "__%s_veneer"
2140
252b5132
RH		 2141/* The name of the dynamic interpreter. This is put in the .interp
2142 section. */
2143#define ELF_DYNAMIC_INTERPRETER "/usr/lib/ld.so.1"
2144
0855e32b 2145static const unsigned long tls_trampoline [] =
b38cadfb
NC		 2146{
2147 0xe08e0000, /* add r0, lr, r0 */
2148 0xe5901004, /* ldr r1, [r0,#4] */
2149 0xe12fff11, /* bx r1 */
2150};
0855e32b
NS		 2151
2152static const unsigned long dl_tlsdesc_lazy_trampoline [] =
b38cadfb
NC		 2153{
2154 0xe52d2004, /* push {r2} */
2155 0xe59f200c, /* ldr r2, [pc, #3f - . - 8] */
2156 0xe59f100c, /* ldr r1, [pc, #4f - . - 8] */
2157 0xe79f2002, /* 1: ldr r2, [pc, r2] */
2158 0xe081100f, /* 2: add r1, pc */
2159 0xe12fff12, /* bx r2 */
2160 0x00000014, /* 3: .word _GLOBAL_OFFSET_TABLE_ - 1b - 8
99059e56 2161 + dl_tlsdesc_lazy_resolver(GOT) */
b38cadfb
NC		 2162 0x00000018, /* 4: .word _GLOBAL_OFFSET_TABLE_ - 2b - 8 */
2163};
0855e32b 2164
5e681ec4
PB		 2165#ifdef FOUR_WORD_PLT
2166
252b5132
RH		 2167/* The first entry in a procedure linkage table looks like
2168 this. It is set up so that any shared library function that is
59f2c4e7 2169 called before the relocation has been set up calls the dynamic
9b485d32 2170 linker first. */
e5a52504 2171static const bfd_vma elf32_arm_plt0_entry [] =
b38cadfb
NC		 2172{
2173 0xe52de004, /* str lr, [sp, #-4]! */
2174 0xe59fe010, /* ldr lr, [pc, #16] */
2175 0xe08fe00e, /* add lr, pc, lr */
2176 0xe5bef008, /* ldr pc, [lr, #8]! */
2177};
5e681ec4
PB		 2178
2179/* Subsequent entries in a procedure linkage table look like
2180 this. */
e5a52504 2181static const bfd_vma elf32_arm_plt_entry [] =
b38cadfb
NC		 2182{
2183 0xe28fc600, /* add ip, pc, #NN */
2184 0xe28cca00, /* add ip, ip, #NN */
2185 0xe5bcf000, /* ldr pc, [ip, #NN]! */
2186 0x00000000, /* unused */
2187};
5e681ec4 2188
eed94f8f 2189#else /* not FOUR_WORD_PLT */
5e681ec4 2190
5e681ec4
PB		 2191/* The first entry in a procedure linkage table looks like
2192 this. It is set up so that any shared library function that is
2193 called before the relocation has been set up calls the dynamic
2194 linker first. */
e5a52504 2195static const bfd_vma elf32_arm_plt0_entry [] =
b38cadfb
NC		 2196{
2197 0xe52de004, /* str lr, [sp, #-4]! */
2198 0xe59fe004, /* ldr lr, [pc, #4] */
2199 0xe08fe00e, /* add lr, pc, lr */
2200 0xe5bef008, /* ldr pc, [lr, #8]! */
2201 0x00000000, /* &GOT[0] - . */
2202};
252b5132 2203
1db37fe6
YG		 2204/* By default subsequent entries in a procedure linkage table look like
2205 this. Offsets that don't fit into 28 bits will cause link error. */
2206static const bfd_vma elf32_arm_plt_entry_short [] =
b38cadfb
NC		 2207{
2208 0xe28fc600, /* add ip, pc, #0xNN00000 */
2209 0xe28cca00, /* add ip, ip, #0xNN000 */
2210 0xe5bcf000, /* ldr pc, [ip, #0xNNN]! */
2211};
5e681ec4 2212
1db37fe6
YG		 2213/* When explicitly asked, we'll use this "long" entry format
2214 which can cope with arbitrary displacements. */
2215static const bfd_vma elf32_arm_plt_entry_long [] =
2216{
2217 0xe28fc200, /* add ip, pc, #0xN0000000 */
2218 0xe28cc600, /* add ip, ip, #0xNN00000 */
2219 0xe28cca00, /* add ip, ip, #0xNN000 */
2220 0xe5bcf000, /* ldr pc, [ip, #0xNNN]! */
2221};
2222
2223static bfd_boolean elf32_arm_use_long_plt_entry = FALSE;
2224
eed94f8f
NC		 2225#endif /* not FOUR_WORD_PLT */
2226
2227/* The first entry in a procedure linkage table looks like this.
2228 It is set up so that any shared library function that is called before the
2229 relocation has been set up calls the dynamic linker first. */
2230static const bfd_vma elf32_thumb2_plt0_entry [] =
2231{
2232 /* NOTE: As this is a mixture of 16-bit and 32-bit instructions,
2233 an instruction maybe encoded to one or two array elements. */
2234 0xf8dfb500, /* push {lr} */
2235 0x44fee008, /* ldr.w lr, [pc, #8] */
469a3493 2236 /* add lr, pc */
eed94f8f
NC		 2237 0xff08f85e, /* ldr.w pc, [lr, #8]! */
2238 0x00000000, /* &GOT[0] - . */
2239};
2240
2241/* Subsequent entries in a procedure linkage table for thumb only target
2242 look like this. */
2243static const bfd_vma elf32_thumb2_plt_entry [] =
2244{
2245 /* NOTE: As this is a mixture of 16-bit and 32-bit instructions,
2246 an instruction maybe encoded to one or two array elements. */
2247 0x0c00f240, /* movw ip, #0xNNNN */
2248 0x0c00f2c0, /* movt ip, #0xNNNN */
2249 0xf8dc44fc, /* add ip, pc */
2250 0xbf00f000 /* ldr.w pc, [ip] */
469a3493 2251 /* nop */
eed94f8f 2252};
252b5132 2253
00a97672
RS		 2254/* The format of the first entry in the procedure linkage table
2255 for a VxWorks executable. */
2256static const bfd_vma elf32_arm_vxworks_exec_plt0_entry[] =
b38cadfb
NC		 2257{
2258 0xe52dc008, /* str ip,[sp,#-8]! */
2259 0xe59fc000, /* ldr ip,[pc] */
2260 0xe59cf008, /* ldr pc,[ip,#8] */
2261 0x00000000, /* .long _GLOBAL_OFFSET_TABLE_ */
2262};
00a97672
RS		 2263
2264/* The format of subsequent entries in a VxWorks executable. */
2265static const bfd_vma elf32_arm_vxworks_exec_plt_entry[] =
b38cadfb
NC		 2266{
2267 0xe59fc000, /* ldr ip,[pc] */
2268 0xe59cf000, /* ldr pc,[ip] */
2269 0x00000000, /* .long @got */
2270 0xe59fc000, /* ldr ip,[pc] */
2271 0xea000000, /* b _PLT */
2272 0x00000000, /* .long @pltindex*sizeof(Elf32_Rela) */
2273};
00a97672
RS		 2274
2275/* The format of entries in a VxWorks shared library. */
2276static const bfd_vma elf32_arm_vxworks_shared_plt_entry[] =
b38cadfb
NC		 2277{
2278 0xe59fc000, /* ldr ip,[pc] */
2279 0xe79cf009, /* ldr pc,[ip,r9] */
2280 0x00000000, /* .long @got */
2281 0xe59fc000, /* ldr ip,[pc] */
2282 0xe599f008, /* ldr pc,[r9,#8] */
2283 0x00000000, /* .long @pltindex*sizeof(Elf32_Rela) */
2284};
00a97672 2285
b7693d02
DJ		 2286/* An initial stub used if the PLT entry is referenced from Thumb code. */
2287#define PLT_THUMB_STUB_SIZE 4
2288static const bfd_vma elf32_arm_plt_thumb_stub [] =
b38cadfb
NC		 2289{
2290 0x4778, /* bx pc */
2291 0x46c0 /* nop */
2292};
b7693d02 2293
e5a52504
MM		 2294/* The entries in a PLT when using a DLL-based target with multiple
2295 address spaces. */
906e58ca 2296static const bfd_vma elf32_arm_symbian_plt_entry [] =
b38cadfb
NC		 2297{
2298 0xe51ff004, /* ldr pc, [pc, #-4] */
2299 0x00000000, /* dcd R_ARM_GLOB_DAT(X) */
2300};
2301
2302/* The first entry in a procedure linkage table looks like
2303 this. It is set up so that any shared library function that is
2304 called before the relocation has been set up calls the dynamic
2305 linker first. */
2306static const bfd_vma elf32_arm_nacl_plt0_entry [] =
2307{
2308 /* First bundle: */
2309 0xe300c000, /* movw ip, #:lower16:&GOT[2]-.+8 */
2310 0xe340c000, /* movt ip, #:upper16:&GOT[2]-.+8 */
2311 0xe08cc00f, /* add ip, ip, pc */
2312 0xe52dc008, /* str ip, [sp, #-8]! */
2313 /* Second bundle: */
edccdf7c
RM		 2314 0xe3ccc103, /* bic ip, ip, #0xc0000000 */
2315 0xe59cc000, /* ldr ip, [ip] */
b38cadfb 2316 0xe3ccc13f, /* bic ip, ip, #0xc000000f */
edccdf7c 2317 0xe12fff1c, /* bx ip */
b38cadfb 2318 /* Third bundle: */
edccdf7c
RM		 2319 0xe320f000, /* nop */
2320 0xe320f000, /* nop */
2321 0xe320f000, /* nop */
b38cadfb
NC		 2322 /* .Lplt_tail: */
2323 0xe50dc004, /* str ip, [sp, #-4] */
2324 /* Fourth bundle: */
edccdf7c
RM		 2325 0xe3ccc103, /* bic ip, ip, #0xc0000000 */
2326 0xe59cc000, /* ldr ip, [ip] */
b38cadfb 2327 0xe3ccc13f, /* bic ip, ip, #0xc000000f */
edccdf7c 2328 0xe12fff1c, /* bx ip */
b38cadfb
NC		 2329};
2330#define ARM_NACL_PLT_TAIL_OFFSET (11 * 4)
2331
2332/* Subsequent entries in a procedure linkage table look like this. */
2333static const bfd_vma elf32_arm_nacl_plt_entry [] =
2334{
2335 0xe300c000, /* movw ip, #:lower16:&GOT[n]-.+8 */
2336 0xe340c000, /* movt ip, #:upper16:&GOT[n]-.+8 */
2337 0xe08cc00f, /* add ip, ip, pc */
2338 0xea000000, /* b .Lplt_tail */
2339};
e5a52504 2340
906e58ca
NC		 2341#define ARM_MAX_FWD_BRANCH_OFFSET ((((1 << 23) - 1) << 2) + 8)
2342#define ARM_MAX_BWD_BRANCH_OFFSET ((-((1 << 23) << 2)) + 8)
2343#define THM_MAX_FWD_BRANCH_OFFSET ((1 << 22) -2 + 4)
2344#define THM_MAX_BWD_BRANCH_OFFSET (-(1 << 22) + 4)
2345#define THM2_MAX_FWD_BRANCH_OFFSET (((1 << 24) - 2) + 4)
2346#define THM2_MAX_BWD_BRANCH_OFFSET (-(1 << 24) + 4)
c5423981
TG		 2347#define THM2_MAX_FWD_COND_BRANCH_OFFSET (((1 << 20) -2) + 4)
2348#define THM2_MAX_BWD_COND_BRANCH_OFFSET (-(1 << 20) + 4)
906e58ca 2349
461a49ca 2350enum stub_insn_type
b38cadfb
NC		 2351{
2352 THUMB16_TYPE = 1,
2353 THUMB32_TYPE,
2354 ARM_TYPE,
2355 DATA_TYPE
2356};
461a49ca 2357
48229727
JB		 2358#define THUMB16_INSN(X) {(X), THUMB16_TYPE, R_ARM_NONE, 0}
2359/* A bit of a hack. A Thumb conditional branch, in which the proper condition
2360 is inserted in arm_build_one_stub(). */
2361#define THUMB16_BCOND_INSN(X) {(X), THUMB16_TYPE, R_ARM_NONE, 1}
2362#define THUMB32_INSN(X) {(X), THUMB32_TYPE, R_ARM_NONE, 0}
2363#define THUMB32_B_INSN(X, Z) {(X), THUMB32_TYPE, R_ARM_THM_JUMP24, (Z)}
2364#define ARM_INSN(X) {(X), ARM_TYPE, R_ARM_NONE, 0}
2365#define ARM_REL_INSN(X, Z) {(X), ARM_TYPE, R_ARM_JUMP24, (Z)}
2366#define DATA_WORD(X,Y,Z) {(X), DATA_TYPE, (Y), (Z)}
461a49ca
DJ		 2367
2368typedef struct
2369{
b38cadfb
NC		 2370 bfd_vma data;
2371 enum stub_insn_type type;
2372 unsigned int r_type;
2373 int reloc_addend;
461a49ca
DJ		 2374} insn_sequence;
2375
fea2b4d6
CL		 2376/* Arm/Thumb -> Arm/Thumb long branch stub. On V5T and above, use blx
2377 to reach the stub if necessary. */
461a49ca 2378static const insn_sequence elf32_arm_stub_long_branch_any_any[] =
b38cadfb
NC		 2379{
2380 ARM_INSN (0xe51ff004), /* ldr pc, [pc, #-4] */
2381 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(X) */
2382};
906e58ca 2383
fea2b4d6
CL		 2384/* V4T Arm -> Thumb long branch stub. Used on V4T where blx is not
2385 available. */
461a49ca 2386static const insn_sequence elf32_arm_stub_long_branch_v4t_arm_thumb[] =
b38cadfb
NC		 2387{
2388 ARM_INSN (0xe59fc000), /* ldr ip, [pc, #0] */
2389 ARM_INSN (0xe12fff1c), /* bx ip */
2390 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(X) */
2391};
906e58ca 2392
d3626fb0 2393/* Thumb -> Thumb long branch stub. Used on M-profile architectures. */
461a49ca 2394static const insn_sequence elf32_arm_stub_long_branch_thumb_only[] =
b38cadfb
NC		 2395{
2396 THUMB16_INSN (0xb401), /* push {r0} */
2397 THUMB16_INSN (0x4802), /* ldr r0, [pc, #8] */
2398 THUMB16_INSN (0x4684), /* mov ip, r0 */
2399 THUMB16_INSN (0xbc01), /* pop {r0} */
2400 THUMB16_INSN (0x4760), /* bx ip */
2401 THUMB16_INSN (0xbf00), /* nop */
2402 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(X) */
2403};
906e58ca 2404
d3626fb0
CL		 2405/* V4T Thumb -> Thumb long branch stub. Using the stack is not
2406 allowed. */
2407static const insn_sequence elf32_arm_stub_long_branch_v4t_thumb_thumb[] =
b38cadfb
NC		 2408{
2409 THUMB16_INSN (0x4778), /* bx pc */
2410 THUMB16_INSN (0x46c0), /* nop */
2411 ARM_INSN (0xe59fc000), /* ldr ip, [pc, #0] */
2412 ARM_INSN (0xe12fff1c), /* bx ip */
2413 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(X) */
2414};
d3626fb0 2415
fea2b4d6
CL		 2416/* V4T Thumb -> ARM long branch stub. Used on V4T where blx is not
2417 available. */
461a49ca 2418static const insn_sequence elf32_arm_stub_long_branch_v4t_thumb_arm[] =
b38cadfb
NC		 2419{
2420 THUMB16_INSN (0x4778), /* bx pc */
2421 THUMB16_INSN (0x46c0), /* nop */
2422 ARM_INSN (0xe51ff004), /* ldr pc, [pc, #-4] */
2423 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(X) */
2424};
906e58ca 2425
fea2b4d6
CL		 2426/* V4T Thumb -> ARM short branch stub. Shorter variant of the above
2427 one, when the destination is close enough. */
461a49ca 2428static const insn_sequence elf32_arm_stub_short_branch_v4t_thumb_arm[] =
b38cadfb
NC		 2429{
2430 THUMB16_INSN (0x4778), /* bx pc */
2431 THUMB16_INSN (0x46c0), /* nop */
2432 ARM_REL_INSN (0xea000000, -8), /* b (X-8) */
2433};
c820be07 2434
cf3eccff 2435/* ARM/Thumb -> ARM long branch stub, PIC. On V5T and above, use
fea2b4d6 2436 blx to reach the stub if necessary. */
cf3eccff 2437static const insn_sequence elf32_arm_stub_long_branch_any_arm_pic[] =
b38cadfb
NC		 2438{
2439 ARM_INSN (0xe59fc000), /* ldr ip, [pc] */
2440 ARM_INSN (0xe08ff00c), /* add pc, pc, ip */
2441 DATA_WORD (0, R_ARM_REL32, -4), /* dcd R_ARM_REL32(X-4) */
2442};
906e58ca 2443
cf3eccff
DJ		 2444/* ARM/Thumb -> Thumb long branch stub, PIC. On V5T and above, use
2445 blx to reach the stub if necessary. We can not add into pc;
2446 it is not guaranteed to mode switch (different in ARMv6 and
2447 ARMv7). */
2448static const insn_sequence elf32_arm_stub_long_branch_any_thumb_pic[] =
b38cadfb
NC		 2449{
2450 ARM_INSN (0xe59fc004), /* ldr ip, [pc, #4] */
2451 ARM_INSN (0xe08fc00c), /* add ip, pc, ip */
2452 ARM_INSN (0xe12fff1c), /* bx ip */
2453 DATA_WORD (0, R_ARM_REL32, 0), /* dcd R_ARM_REL32(X) */
2454};
cf3eccff 2455
ebe24dd4
CL		 2456/* V4T ARM -> ARM long branch stub, PIC. */
2457static const insn_sequence elf32_arm_stub_long_branch_v4t_arm_thumb_pic[] =
b38cadfb
NC		 2458{
2459 ARM_INSN (0xe59fc004), /* ldr ip, [pc, #4] */
2460 ARM_INSN (0xe08fc00c), /* add ip, pc, ip */
2461 ARM_INSN (0xe12fff1c), /* bx ip */
2462 DATA_WORD (0, R_ARM_REL32, 0), /* dcd R_ARM_REL32(X) */
2463};
ebe24dd4
CL		 2464
2465/* V4T Thumb -> ARM long branch stub, PIC. */
2466static const insn_sequence elf32_arm_stub_long_branch_v4t_thumb_arm_pic[] =
b38cadfb
NC		 2467{
2468 THUMB16_INSN (0x4778), /* bx pc */
2469 THUMB16_INSN (0x46c0), /* nop */
2470 ARM_INSN (0xe59fc000), /* ldr ip, [pc, #0] */
2471 ARM_INSN (0xe08cf00f), /* add pc, ip, pc */
2472 DATA_WORD (0, R_ARM_REL32, -4), /* dcd R_ARM_REL32(X) */
2473};
ebe24dd4 2474
d3626fb0
CL		 2475/* Thumb -> Thumb long branch stub, PIC. Used on M-profile
2476 architectures. */
ebe24dd4 2477static const insn_sequence elf32_arm_stub_long_branch_thumb_only_pic[] =
b38cadfb
NC		 2478{
2479 THUMB16_INSN (0xb401), /* push {r0} */
2480 THUMB16_INSN (0x4802), /* ldr r0, [pc, #8] */
2481 THUMB16_INSN (0x46fc), /* mov ip, pc */
2482 THUMB16_INSN (0x4484), /* add ip, r0 */
2483 THUMB16_INSN (0xbc01), /* pop {r0} */
2484 THUMB16_INSN (0x4760), /* bx ip */
2485 DATA_WORD (0, R_ARM_REL32, 4), /* dcd R_ARM_REL32(X) */
2486};
ebe24dd4 2487
d3626fb0
CL		 2488/* V4T Thumb -> Thumb long branch stub, PIC. Using the stack is not
2489 allowed. */
2490static const insn_sequence elf32_arm_stub_long_branch_v4t_thumb_thumb_pic[] =
b38cadfb
NC		 2491{
2492 THUMB16_INSN (0x4778), /* bx pc */
2493 THUMB16_INSN (0x46c0), /* nop */
2494 ARM_INSN (0xe59fc004), /* ldr ip, [pc, #4] */
2495 ARM_INSN (0xe08fc00c), /* add ip, pc, ip */
2496 ARM_INSN (0xe12fff1c), /* bx ip */
2497 DATA_WORD (0, R_ARM_REL32, 0), /* dcd R_ARM_REL32(X) */
2498};
d3626fb0 2499
0855e32b
NS		 2500/* Thumb2/ARM -> TLS trampoline. Lowest common denominator, which is a
2501 long PIC stub. We can use r1 as a scratch -- and cannot use ip. */
2502static const insn_sequence elf32_arm_stub_long_branch_any_tls_pic[] =
2503{
b38cadfb
NC		 2504 ARM_INSN (0xe59f1000), /* ldr r1, [pc] */
2505 ARM_INSN (0xe08ff001), /* add pc, pc, r1 */
2506 DATA_WORD (0, R_ARM_REL32, -4), /* dcd R_ARM_REL32(X-4) */
0855e32b
NS		 2507};
2508
2509/* V4T Thumb -> TLS trampoline. lowest common denominator, which is a
2510 long PIC stub. We can use r1 as a scratch -- and cannot use ip. */
2511static const insn_sequence elf32_arm_stub_long_branch_v4t_thumb_tls_pic[] =
2512{
b38cadfb
NC		 2513 THUMB16_INSN (0x4778), /* bx pc */
2514 THUMB16_INSN (0x46c0), /* nop */
2515 ARM_INSN (0xe59f1000), /* ldr r1, [pc, #0] */
2516 ARM_INSN (0xe081f00f), /* add pc, r1, pc */
2517 DATA_WORD (0, R_ARM_REL32, -4), /* dcd R_ARM_REL32(X) */
0855e32b
NS		 2518};
2519
7a89b94e
NC		 2520/* NaCl ARM -> ARM long branch stub. */
2521static const insn_sequence elf32_arm_stub_long_branch_arm_nacl[] =
2522{
2523 ARM_INSN (0xe59fc00c), /* ldr ip, [pc, #12] */
2524 ARM_INSN (0xe3ccc13f), /* bic ip, ip, #0xc000000f */
2525 ARM_INSN (0xe12fff1c), /* bx ip */
2526 ARM_INSN (0xe320f000), /* nop */
2527 ARM_INSN (0xe125be70), /* bkpt 0x5be0 */
2528 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(X) */
2529 DATA_WORD (0, R_ARM_NONE, 0), /* .word 0 */
2530 DATA_WORD (0, R_ARM_NONE, 0), /* .word 0 */
2531};
2532
2533/* NaCl ARM -> ARM long branch stub, PIC. */
2534static const insn_sequence elf32_arm_stub_long_branch_arm_nacl_pic[] =
2535{
2536 ARM_INSN (0xe59fc00c), /* ldr ip, [pc, #12] */
2537 ARM_INSN (0xe08cc00f), /* add ip, ip, pc */
2538 ARM_INSN (0xe3ccc13f), /* bic ip, ip, #0xc000000f */
2539 ARM_INSN (0xe12fff1c), /* bx ip */
2540 ARM_INSN (0xe125be70), /* bkpt 0x5be0 */
2541 DATA_WORD (0, R_ARM_REL32, 8), /* dcd R_ARM_REL32(X+8) */
2542 DATA_WORD (0, R_ARM_NONE, 0), /* .word 0 */
2543 DATA_WORD (0, R_ARM_NONE, 0), /* .word 0 */
2544};
2545
2546
48229727
JB		 2547/* Cortex-A8 erratum-workaround stubs. */
2548
2549/* Stub used for conditional branches (which may be beyond +/-1MB away, so we
2550 can't use a conditional branch to reach this stub). */
2551
2552static const insn_sequence elf32_arm_stub_a8_veneer_b_cond[] =
b38cadfb
NC		 2553{
2554 THUMB16_BCOND_INSN (0xd001), /* b<cond>.n true. */
2555 THUMB32_B_INSN (0xf000b800, -4), /* b.w insn_after_original_branch. */
2556 THUMB32_B_INSN (0xf000b800, -4) /* true: b.w original_branch_dest. */
2557};
48229727
JB		 2558
2559/* Stub used for b.w and bl.w instructions. */
2560
2561static const insn_sequence elf32_arm_stub_a8_veneer_b[] =
b38cadfb
NC		 2562{
2563 THUMB32_B_INSN (0xf000b800, -4) /* b.w original_branch_dest. */
2564};
48229727
JB		 2565
2566static const insn_sequence elf32_arm_stub_a8_veneer_bl[] =
b38cadfb
NC		 2567{
2568 THUMB32_B_INSN (0xf000b800, -4) /* b.w original_branch_dest. */
2569};
48229727
JB		 2570
2571/* Stub used for Thumb-2 blx.w instructions. We modified the original blx.w
2572 instruction (which switches to ARM mode) to point to this stub. Jump to the
2573 real destination using an ARM-mode branch. */
2574
2575static const insn_sequence elf32_arm_stub_a8_veneer_blx[] =
b38cadfb
NC		 2576{
2577 ARM_REL_INSN (0xea000000, -8) /* b original_branch_dest. */
2578};
48229727 2579
9553db3c
NC		 2580/* For each section group there can be a specially created linker section
2581 to hold the stubs for that group. The name of the stub section is based
2582 upon the name of another section within that group with the suffix below
2583 applied.
2584
2585 PR 13049: STUB_SUFFIX used to be ".stub", but this allowed the user to
2586 create what appeared to be a linker stub section when it actually
2587 contained user code/data. For example, consider this fragment:
b38cadfb 2588
9553db3c
NC		 2589 const char * stubborn_problems[] = { "np" };
2590
2591 If this is compiled with "-fPIC -fdata-sections" then gcc produces a
2592 section called:
2593
2594 .data.rel.local.stubborn_problems
2595
2596 This then causes problems in arm32_arm_build_stubs() as it triggers:
2597
2598 // Ignore non-stub sections.
2599 if (!strstr (stub_sec->name, STUB_SUFFIX))
2600 continue;
2601
2602 And so the section would be ignored instead of being processed. Hence
2603 the change in definition of STUB_SUFFIX to a name that cannot be a valid
2604 C identifier. */
2605#define STUB_SUFFIX ".__stub"
906e58ca 2606
738a79f6
CL		 2607/* One entry per long/short branch stub defined above. */
2608#define DEF_STUBS \
2609 DEF_STUB(long_branch_any_any) \
2610 DEF_STUB(long_branch_v4t_arm_thumb) \
2611 DEF_STUB(long_branch_thumb_only) \
2612 DEF_STUB(long_branch_v4t_thumb_thumb) \
2613 DEF_STUB(long_branch_v4t_thumb_arm) \
2614 DEF_STUB(short_branch_v4t_thumb_arm) \
2615 DEF_STUB(long_branch_any_arm_pic) \
2616 DEF_STUB(long_branch_any_thumb_pic) \
2617 DEF_STUB(long_branch_v4t_thumb_thumb_pic) \
2618 DEF_STUB(long_branch_v4t_arm_thumb_pic) \
2619 DEF_STUB(long_branch_v4t_thumb_arm_pic) \
48229727 2620 DEF_STUB(long_branch_thumb_only_pic) \
0855e32b
NS		 2621 DEF_STUB(long_branch_any_tls_pic) \
2622 DEF_STUB(long_branch_v4t_thumb_tls_pic) \
7a89b94e
NC		 2623 DEF_STUB(long_branch_arm_nacl) \
2624 DEF_STUB(long_branch_arm_nacl_pic) \
48229727
JB		 2625 DEF_STUB(a8_veneer_b_cond) \
2626 DEF_STUB(a8_veneer_b) \
2627 DEF_STUB(a8_veneer_bl) \
2628 DEF_STUB(a8_veneer_blx)
738a79f6
CL		 2629
2630#define DEF_STUB(x) arm_stub_##x,
b38cadfb
NC		 2631enum elf32_arm_stub_type
2632{
906e58ca 2633 arm_stub_none,
738a79f6 2634 DEF_STUBS
4f4faa4d 2635 max_stub_type
738a79f6
CL		 2636};
2637#undef DEF_STUB
2638
8d9d9490
TP		 2639/* Note the first a8_veneer type. */
2640const unsigned arm_stub_a8_veneer_lwm = arm_stub_a8_veneer_b_cond;
2641
738a79f6
CL		 2642typedef struct
2643{
d3ce72d0 2644 const insn_sequence* template_sequence;
738a79f6
CL		 2645 int template_size;
2646} stub_def;
2647
2648#define DEF_STUB(x) {elf32_arm_stub_##x, ARRAY_SIZE(elf32_arm_stub_##x)},
b38cadfb
NC		 2649static const stub_def stub_definitions[] =
2650{
738a79f6
CL		 2651 {NULL, 0},
2652 DEF_STUBS
906e58ca
NC		 2653};
2654
2655struct elf32_arm_stub_hash_entry
2656{
2657 /* Base hash table entry structure. */
2658 struct bfd_hash_entry root;
2659
2660 /* The stub section. */
2661 asection *stub_sec;
2662
2663 /* Offset within stub_sec of the beginning of this stub. */
2664 bfd_vma stub_offset;
2665
2666 /* Given the symbol's value and its section we can determine its final
2667 value when building the stubs (so the stub knows where to jump). */
2668 bfd_vma target_value;
2669 asection *target_section;
2670
8d9d9490
TP		 2671 /* Same as above but for the source of the branch to the stub. Used for
2672 Cortex-A8 erratum workaround to patch it to branch to the stub. As
2673 such, source section does not need to be recorded since Cortex-A8 erratum
2674 workaround stubs are only generated when both source and target are in the
2675 same section. */
2676 bfd_vma source_value;
48229727
JB		 2677
2678 /* The instruction which caused this stub to be generated (only valid for
2679 Cortex-A8 erratum workaround stubs at present). */
2680 unsigned long orig_insn;
2681
461a49ca 2682 /* The stub type. */
906e58ca 2683 enum elf32_arm_stub_type stub_type;
461a49ca
DJ		 2684 /* Its encoding size in bytes. */
2685 int stub_size;
2686 /* Its template. */
2687 const insn_sequence *stub_template;
2688 /* The size of the template (number of entries). */
2689 int stub_template_size;
906e58ca
NC		 2690
2691 /* The symbol table entry, if any, that this was derived from. */
2692 struct elf32_arm_link_hash_entry *h;
2693
35fc36a8
RS		 2694 /* Type of branch. */
2695 enum arm_st_branch_type branch_type;
906e58ca
NC		 2696
2697 /* Where this stub is being called from, or, in the case of combined
2698 stub sections, the first input section in the group. */
2699 asection *id_sec;
7413f23f
DJ		 2700
2701 /* The name for the local symbol at the start of this stub. The
2702 stub name in the hash table has to be unique; this does not, so
2703 it can be friendlier. */
2704 char *output_name;
906e58ca
NC		 2705};
2706
e489d0ae
PB		 2707/* Used to build a map of a section. This is required for mixed-endian
2708 code/data. */
2709
2710typedef struct elf32_elf_section_map
2711{
2712 bfd_vma vma;
2713 char type;
2714}
2715elf32_arm_section_map;
2716
c7b8f16e
JB		 2717/* Information about a VFP11 erratum veneer, or a branch to such a veneer. */
2718
2719typedef enum
2720{
2721 VFP11_ERRATUM_BRANCH_TO_ARM_VENEER,
2722 VFP11_ERRATUM_BRANCH_TO_THUMB_VENEER,
2723 VFP11_ERRATUM_ARM_VENEER,
2724 VFP11_ERRATUM_THUMB_VENEER
2725}
2726elf32_vfp11_erratum_type;
2727
2728typedef struct elf32_vfp11_erratum_list
2729{
2730 struct elf32_vfp11_erratum_list *next;
2731 bfd_vma vma;
2732 union
2733 {
2734 struct
2735 {
2736 struct elf32_vfp11_erratum_list *veneer;
2737 unsigned int vfp_insn;
2738 } b;
2739 struct
2740 {
2741 struct elf32_vfp11_erratum_list *branch;
2742 unsigned int id;
2743 } v;
2744 } u;
2745 elf32_vfp11_erratum_type type;
2746}
2747elf32_vfp11_erratum_list;
2748
a504d23a
LA		 2749/* Information about a STM32L4XX erratum veneer, or a branch to such a
2750 veneer. */
2751typedef enum
2752{
2753 STM32L4XX_ERRATUM_BRANCH_TO_VENEER,
2754 STM32L4XX_ERRATUM_VENEER
2755}
2756elf32_stm32l4xx_erratum_type;
2757
2758typedef struct elf32_stm32l4xx_erratum_list
2759{
2760 struct elf32_stm32l4xx_erratum_list *next;
2761 bfd_vma vma;
2762 union
2763 {
2764 struct
2765 {
2766 struct elf32_stm32l4xx_erratum_list *veneer;
2767 unsigned int insn;
2768 } b;
2769 struct
2770 {
2771 struct elf32_stm32l4xx_erratum_list *branch;
2772 unsigned int id;
2773 } v;
2774 } u;
2775 elf32_stm32l4xx_erratum_type type;
2776}
2777elf32_stm32l4xx_erratum_list;
2778
2468f9c9
PB		 2779typedef enum
2780{
2781 DELETE_EXIDX_ENTRY,
2782 INSERT_EXIDX_CANTUNWIND_AT_END
2783}
2784arm_unwind_edit_type;
2785
2786/* A (sorted) list of edits to apply to an unwind table. */
2787typedef struct arm_unwind_table_edit
2788{
2789 arm_unwind_edit_type type;
2790 /* Note: we sometimes want to insert an unwind entry corresponding to a
2791 section different from the one we're currently writing out, so record the
2792 (text) section this edit relates to here. */
2793 asection *linked_section;
2794 unsigned int index;
2795 struct arm_unwind_table_edit *next;
2796}
2797arm_unwind_table_edit;
2798
8e3de13a 2799typedef struct _arm_elf_section_data
e489d0ae 2800{
2468f9c9 2801 /* Information about mapping symbols. */
e489d0ae 2802 struct bfd_elf_section_data elf;
8e3de13a 2803 unsigned int mapcount;
c7b8f16e 2804 unsigned int mapsize;
e489d0ae 2805 elf32_arm_section_map *map;
2468f9c9 2806 /* Information about CPU errata. */
c7b8f16e
JB		 2807 unsigned int erratumcount;
2808 elf32_vfp11_erratum_list *erratumlist;
a504d23a
LA		 2809 unsigned int stm32l4xx_erratumcount;
2810 elf32_stm32l4xx_erratum_list *stm32l4xx_erratumlist;
491d01d3 2811 unsigned int additional_reloc_count;
2468f9c9
PB		 2812 /* Information about unwind tables. */
2813 union
2814 {
2815 /* Unwind info attached to a text section. */
2816 struct
2817 {
2818 asection *arm_exidx_sec;
2819 } text;
2820
2821 /* Unwind info attached to an .ARM.exidx section. */
2822 struct
2823 {
2824 arm_unwind_table_edit *unwind_edit_list;
2825 arm_unwind_table_edit *unwind_edit_tail;
2826 } exidx;
2827 } u;
8e3de13a
NC		 2828}
2829_arm_elf_section_data;
e489d0ae
PB		 2830
2831#define elf32_arm_section_data(sec) \
8e3de13a 2832 ((_arm_elf_section_data *) elf_section_data (sec))
e489d0ae 2833
48229727
JB		 2834/* A fix which might be required for Cortex-A8 Thumb-2 branch/TLB erratum.
2835 These fixes are subject to a relaxation procedure (in elf32_arm_size_stubs),
2836 so may be created multiple times: we use an array of these entries whilst
2837 relaxing which we can refresh easily, then create stubs for each potentially
2838 erratum-triggering instruction once we've settled on a solution. */
2839
b38cadfb
NC		 2840struct a8_erratum_fix
2841{
48229727
JB		 2842 bfd *input_bfd;
2843 asection *section;
2844 bfd_vma offset;
8d9d9490 2845 bfd_vma target_offset;
48229727
JB		 2846 unsigned long orig_insn;
2847 char *stub_name;
2848 enum elf32_arm_stub_type stub_type;
35fc36a8 2849 enum arm_st_branch_type branch_type;
48229727
JB		 2850};
2851
2852/* A table of relocs applied to branches which might trigger Cortex-A8
2853 erratum. */
2854
b38cadfb
NC		 2855struct a8_erratum_reloc
2856{
48229727
JB		 2857 bfd_vma from;
2858 bfd_vma destination;
92750f34
DJ		 2859 struct elf32_arm_link_hash_entry *hash;
2860 const char *sym_name;
48229727 2861 unsigned int r_type;
35fc36a8 2862 enum arm_st_branch_type branch_type;
48229727
JB		 2863 bfd_boolean non_a8_stub;
2864};
2865
ba93b8ac
DJ		 2866/* The size of the thread control block. */
2867#define TCB_SIZE 8
2868
34e77a92
RS		 2869/* ARM-specific information about a PLT entry, over and above the usual
2870 gotplt_union. */
b38cadfb
NC		 2871struct arm_plt_info
2872{
34e77a92
RS		 2873 /* We reference count Thumb references to a PLT entry separately,
2874 so that we can emit the Thumb trampoline only if needed. */
2875 bfd_signed_vma thumb_refcount;
2876
2877 /* Some references from Thumb code may be eliminated by BL->BLX
2878 conversion, so record them separately. */
2879 bfd_signed_vma maybe_thumb_refcount;
2880
2881 /* How many of the recorded PLT accesses were from non-call relocations.
2882 This information is useful when deciding whether anything takes the
2883 address of an STT_GNU_IFUNC PLT. A value of 0 means that all
2884 non-call references to the function should resolve directly to the
2885 real runtime target. */
2886 unsigned int noncall_refcount;
2887
2888 /* Since PLT entries have variable size if the Thumb prologue is
2889 used, we need to record the index into .got.plt instead of
2890 recomputing it from the PLT offset. */
2891 bfd_signed_vma got_offset;
2892};
2893
2894/* Information about an .iplt entry for a local STT_GNU_IFUNC symbol. */
b38cadfb
NC		 2895struct arm_local_iplt_info
2896{
34e77a92
RS		 2897 /* The information that is usually found in the generic ELF part of
2898 the hash table entry. */
2899 union gotplt_union root;
2900
2901 /* The information that is usually found in the ARM-specific part of
2902 the hash table entry. */
2903 struct arm_plt_info arm;
2904
2905 /* A list of all potential dynamic relocations against this symbol. */
2906 struct elf_dyn_relocs *dyn_relocs;
2907};
2908
0ffa91dd 2909struct elf_arm_obj_tdata
ba93b8ac
DJ		 2910{
2911 struct elf_obj_tdata root;
2912
2913 /* tls_type for each local got entry. */
2914 char *local_got_tls_type;
ee065d83 2915
0855e32b
NS		 2916 /* GOTPLT entries for TLS descriptors. */
2917 bfd_vma *local_tlsdesc_gotent;
2918
34e77a92
RS		 2919 /* Information for local symbols that need entries in .iplt. */
2920 struct arm_local_iplt_info **local_iplt;
2921
bf21ed78
MS		 2922 /* Zero to warn when linking objects with incompatible enum sizes. */
2923 int no_enum_size_warning;
a9dc9481
JM		 2924
2925 /* Zero to warn when linking objects with incompatible wchar_t sizes. */
2926 int no_wchar_size_warning;
ba93b8ac
DJ		 2927};
2928
0ffa91dd
NC		 2929#define elf_arm_tdata(bfd) \
2930 ((struct elf_arm_obj_tdata *) (bfd)->tdata.any)
ba93b8ac 2931
0ffa91dd
NC		 2932#define elf32_arm_local_got_tls_type(bfd) \
2933 (elf_arm_tdata (bfd)->local_got_tls_type)
2934
0855e32b
NS		 2935#define elf32_arm_local_tlsdesc_gotent(bfd) \
2936 (elf_arm_tdata (bfd)->local_tlsdesc_gotent)
2937
34e77a92
RS		 2938#define elf32_arm_local_iplt(bfd) \
2939 (elf_arm_tdata (bfd)->local_iplt)
2940
0ffa91dd
NC		 2941#define is_arm_elf(bfd) \
2942 (bfd_get_flavour (bfd) == bfd_target_elf_flavour \
2943 && elf_tdata (bfd) != NULL \
4dfe6ac6 2944 && elf_object_id (bfd) == ARM_ELF_DATA)
ba93b8ac
DJ		 2945
2946static bfd_boolean
2947elf32_arm_mkobject (bfd *abfd)
2948{
0ffa91dd 2949 return bfd_elf_allocate_object (abfd, sizeof (struct elf_arm_obj_tdata),
4dfe6ac6 2950 ARM_ELF_DATA);
ba93b8ac
DJ		 2951}
2952
ba93b8ac
DJ		 2953#define elf32_arm_hash_entry(ent) ((struct elf32_arm_link_hash_entry *)(ent))
2954
ba96a88f 2955/* Arm ELF linker hash entry. */
252b5132 2956struct elf32_arm_link_hash_entry
b38cadfb
NC		 2957{
2958 struct elf_link_hash_entry root;
252b5132 2959
b38cadfb
NC		 2960 /* Track dynamic relocs copied for this symbol. */
2961 struct elf_dyn_relocs *dyn_relocs;
b7693d02 2962
b38cadfb
NC		 2963 /* ARM-specific PLT information. */
2964 struct arm_plt_info plt;
ba93b8ac
DJ		 2965
2966#define GOT_UNKNOWN 0
2967#define GOT_NORMAL 1
2968#define GOT_TLS_GD 2
2969#define GOT_TLS_IE 4
0855e32b
NS		 2970#define GOT_TLS_GDESC 8
2971#define GOT_TLS_GD_ANY_P(type) ((type & GOT_TLS_GD) || (type & GOT_TLS_GDESC))
b38cadfb 2972 unsigned int tls_type : 8;
34e77a92 2973
b38cadfb
NC		 2974 /* True if the symbol's PLT entry is in .iplt rather than .plt. */
2975 unsigned int is_iplt : 1;
34e77a92 2976
b38cadfb 2977 unsigned int unused : 23;
a4fd1a8e 2978
b38cadfb
NC		 2979 /* Offset of the GOTPLT entry reserved for the TLS descriptor,
2980 starting at the end of the jump table. */
2981 bfd_vma tlsdesc_got;
0855e32b 2982
b38cadfb
NC		 2983 /* The symbol marking the real symbol location for exported thumb
2984 symbols with Arm stubs. */
2985 struct elf_link_hash_entry *export_glue;
906e58ca 2986
b38cadfb 2987 /* A pointer to the most recently used stub hash entry against this
8029a119 2988 symbol. */
b38cadfb
NC		 2989 struct elf32_arm_stub_hash_entry *stub_cache;
2990};
252b5132 2991
252b5132 2992/* Traverse an arm ELF linker hash table. */
252b5132
RH		 2993#define elf32_arm_link_hash_traverse(table, func, info) \
2994 (elf_link_hash_traverse \
2995 (&(table)->root, \
b7693d02 2996 (bfd_boolean (*) (struct elf_link_hash_entry *, void *)) (func), \
252b5132
RH		 2997 (info)))
2998
2999/* Get the ARM elf linker hash table from a link_info structure. */
3000#define elf32_arm_hash_table(info) \
4dfe6ac6
NC		 3001 (elf_hash_table_id ((struct elf_link_hash_table *) ((info)->hash)) \
3002 == ARM_ELF_DATA ? ((struct elf32_arm_link_hash_table *) ((info)->hash)) : NULL)
252b5132 3003
906e58ca
NC		 3004#define arm_stub_hash_lookup(table, string, create, copy) \
3005 ((struct elf32_arm_stub_hash_entry *) \
3006 bfd_hash_lookup ((table), (string), (create), (copy)))
3007
21d799b5
NC		 3008/* Array to keep track of which stub sections have been created, and
3009 information on stub grouping. */
3010struct map_stub
3011{
3012 /* This is the section to which stubs in the group will be
3013 attached. */
3014 asection *link_sec;
3015 /* The stub section. */
3016 asection *stub_sec;
3017};
3018
0855e32b
NS		 3019#define elf32_arm_compute_jump_table_size(htab) \
3020 ((htab)->next_tls_desc_index * 4)
3021
9b485d32 3022/* ARM ELF linker hash table. */
252b5132 3023struct elf32_arm_link_hash_table
906e58ca
NC		 3024{
3025 /* The main hash table. */
3026 struct elf_link_hash_table root;
252b5132 3027
906e58ca
NC		 3028 /* The size in bytes of the section containing the Thumb-to-ARM glue. */
3029 bfd_size_type thumb_glue_size;
252b5132 3030
906e58ca
NC		 3031 /* The size in bytes of the section containing the ARM-to-Thumb glue. */
3032 bfd_size_type arm_glue_size;
252b5132 3033
906e58ca
NC		 3034 /* The size in bytes of section containing the ARMv4 BX veneers. */
3035 bfd_size_type bx_glue_size;
845b51d6 3036
906e58ca
NC		 3037 /* Offsets of ARMv4 BX veneers. Bit1 set if present, and Bit0 set when
3038 veneer has been populated. */
3039 bfd_vma bx_glue_offset[15];
845b51d6 3040
906e58ca
NC		 3041 /* The size in bytes of the section containing glue for VFP11 erratum
3042 veneers. */
3043 bfd_size_type vfp11_erratum_glue_size;
c7b8f16e 3044
a504d23a
LA		 3045 /* The size in bytes of the section containing glue for STM32L4XX erratum
3046 veneers. */
3047 bfd_size_type stm32l4xx_erratum_glue_size;
3048
48229727
JB		 3049 /* A table of fix locations for Cortex-A8 Thumb-2 branch/TLB erratum. This
3050 holds Cortex-A8 erratum fix locations between elf32_arm_size_stubs() and
3051 elf32_arm_write_section(). */
3052 struct a8_erratum_fix *a8_erratum_fixes;
3053 unsigned int num_a8_erratum_fixes;
3054
906e58ca
NC		 3055 /* An arbitrary input BFD chosen to hold the glue sections. */
3056 bfd * bfd_of_glue_owner;
ba96a88f 3057
906e58ca
NC		 3058 /* Nonzero to output a BE8 image. */
3059 int byteswap_code;
e489d0ae 3060
906e58ca
NC		 3061 /* Zero if R_ARM_TARGET1 means R_ARM_ABS32.
3062 Nonzero if R_ARM_TARGET1 means R_ARM_REL32. */
3063 int target1_is_rel;
9c504268 3064
906e58ca
NC		 3065 /* The relocation to use for R_ARM_TARGET2 relocations. */
3066 int target2_reloc;
eb043451 3067
906e58ca
NC		 3068 /* 0 = Ignore R_ARM_V4BX.
3069 1 = Convert BX to MOV PC.
3070 2 = Generate v4 interworing stubs. */
3071 int fix_v4bx;
319850b4 3072
48229727
JB		 3073 /* Whether we should fix the Cortex-A8 Thumb-2 branch/TLB erratum. */
3074 int fix_cortex_a8;
3075
2de70689
MGD		 3076 /* Whether we should fix the ARM1176 BLX immediate issue. */
3077 int fix_arm1176;
3078
906e58ca
NC		 3079 /* Nonzero if the ARM/Thumb BLX instructions are available for use. */
3080 int use_blx;
33bfe774 3081
906e58ca
NC		 3082 /* What sort of code sequences we should look for which may trigger the
3083 VFP11 denorm erratum. */
3084 bfd_arm_vfp11_fix vfp11_fix;
c7b8f16e 3085
906e58ca
NC		 3086 /* Global counter for the number of fixes we have emitted. */
3087 int num_vfp11_fixes;
c7b8f16e 3088
a504d23a
LA		 3089 /* What sort of code sequences we should look for which may trigger the
3090 STM32L4XX erratum. */
3091 bfd_arm_stm32l4xx_fix stm32l4xx_fix;
3092
3093 /* Global counter for the number of fixes we have emitted. */
3094 int num_stm32l4xx_fixes;
3095
906e58ca
NC		 3096 /* Nonzero to force PIC branch veneers. */
3097 int pic_veneer;
27e55c4d 3098
906e58ca
NC		 3099 /* The number of bytes in the initial entry in the PLT. */
3100 bfd_size_type plt_header_size;
e5a52504 3101
906e58ca
NC		 3102 /* The number of bytes in the subsequent PLT etries. */
3103 bfd_size_type plt_entry_size;
e5a52504 3104
906e58ca
NC		 3105 /* True if the target system is VxWorks. */
3106 int vxworks_p;
00a97672 3107
906e58ca
NC		 3108 /* True if the target system is Symbian OS. */
3109 int symbian_p;
e5a52504 3110
b38cadfb
NC		 3111 /* True if the target system is Native Client. */
3112 int nacl_p;
3113
906e58ca
NC		 3114 /* True if the target uses REL relocations. */
3115 int use_rel;
4e7fd91e 3116
0855e32b
NS		 3117 /* The index of the next unused R_ARM_TLS_DESC slot in .rel.plt. */
3118 bfd_vma next_tls_desc_index;
3119
3120 /* How many R_ARM_TLS_DESC relocations were generated so far. */
3121 bfd_vma num_tls_desc;
3122
906e58ca 3123 /* Short-cuts to get to dynamic linker sections. */
906e58ca
NC		 3124 asection *sdynbss;
3125 asection *srelbss;
5e681ec4 3126
906e58ca
NC		 3127 /* The (unloaded but important) VxWorks .rela.plt.unloaded section. */
3128 asection *srelplt2;
00a97672 3129
0855e32b
NS		 3130 /* The offset into splt of the PLT entry for the TLS descriptor
3131 resolver. Special values are 0, if not necessary (or not found
3132 to be necessary yet), and -1 if needed but not determined
3133 yet. */
3134 bfd_vma dt_tlsdesc_plt;
3135
3136 /* The offset into sgot of the GOT entry used by the PLT entry
3137 above. */
b38cadfb 3138 bfd_vma dt_tlsdesc_got;
0855e32b
NS		 3139
3140 /* Offset in .plt section of tls_arm_trampoline. */
3141 bfd_vma tls_trampoline;
3142
906e58ca
NC		 3143 /* Data for R_ARM_TLS_LDM32 relocations. */
3144 union
3145 {
3146 bfd_signed_vma refcount;
3147 bfd_vma offset;
3148 } tls_ldm_got;
b7693d02 3149
87d72d41
AM		 3150 /* Small local sym cache. */
3151 struct sym_cache sym_cache;
906e58ca
NC		 3152
3153 /* For convenience in allocate_dynrelocs. */
3154 bfd * obfd;
3155
0855e32b
NS		 3156 /* The amount of space used by the reserved portion of the sgotplt
3157 section, plus whatever space is used by the jump slots. */
3158 bfd_vma sgotplt_jump_table_size;
3159
906e58ca
NC		 3160 /* The stub hash table. */
3161 struct bfd_hash_table stub_hash_table;
3162
3163 /* Linker stub bfd. */
3164 bfd *stub_bfd;
3165
3166 /* Linker call-backs. */
6bde4c52
TP		 3167 asection * (*add_stub_section) (const char *, asection *, asection *,
3168 unsigned int);
906e58ca
NC		 3169 void (*layout_sections_again) (void);
3170
3171 /* Array to keep track of which stub sections have been created, and
3172 information on stub grouping. */
21d799b5 3173 struct map_stub *stub_group;
906e58ca 3174
fe33d2fa 3175 /* Number of elements in stub_group. */
7292b3ac 3176 unsigned int top_id;
fe33d2fa 3177
906e58ca
NC		 3178 /* Assorted information used by elf32_arm_size_stubs. */
3179 unsigned int bfd_count;
7292b3ac 3180 unsigned int top_index;
906e58ca
NC		 3181 asection **input_list;
3182};
252b5132 3183
a504d23a
LA		 3184static inline int
3185ctz (unsigned int mask)
3186{
3187#if GCC_VERSION >= 3004
3188 return __builtin_ctz (mask);
3189#else
3190 unsigned int i;
3191
3192 for (i = 0; i < 8 * sizeof (mask); i++)
3193 {
3194 if (mask & 0x1)
3195 break;
3196 mask = (mask >> 1);
3197 }
3198 return i;
3199#endif
3200}
3201
3202static inline int
3203popcount (unsigned int mask)
3204{
3205#if GCC_VERSION >= 3004
3206 return __builtin_popcount (mask);
3207#else
3208 unsigned int i, sum = 0;
3209
3210 for (i = 0; i < 8 * sizeof (mask); i++)
3211 {
3212 if (mask & 0x1)
3213 sum++;
3214 mask = (mask >> 1);
3215 }
3216 return sum;
3217#endif
3218}
3219
780a67af
NC		 3220/* Create an entry in an ARM ELF linker hash table. */
3221
3222static struct bfd_hash_entry *
57e8b36a 3223elf32_arm_link_hash_newfunc (struct bfd_hash_entry * entry,
99059e56
RM		 3224 struct bfd_hash_table * table,
3225 const char * string)
780a67af
NC		 3226{
3227 struct elf32_arm_link_hash_entry * ret =
3228 (struct elf32_arm_link_hash_entry *) entry;
3229
3230 /* Allocate the structure if it has not already been allocated by a
3231 subclass. */
906e58ca 3232 if (ret == NULL)
21d799b5 3233 ret = (struct elf32_arm_link_hash_entry *)
99059e56 3234 bfd_hash_allocate (table, sizeof (struct elf32_arm_link_hash_entry));
57e8b36a 3235 if (ret == NULL)
780a67af
NC		 3236 return (struct bfd_hash_entry *) ret;
3237
3238 /* Call the allocation method of the superclass. */
3239 ret = ((struct elf32_arm_link_hash_entry *)
3240 _bfd_elf_link_hash_newfunc ((struct bfd_hash_entry *) ret,
3241 table, string));
57e8b36a 3242 if (ret != NULL)
b7693d02 3243 {
0bdcacaf 3244 ret->dyn_relocs = NULL;
ba93b8ac 3245 ret->tls_type = GOT_UNKNOWN;
0855e32b 3246 ret->tlsdesc_got = (bfd_vma) -1;
34e77a92
RS		 3247 ret->plt.thumb_refcount = 0;
3248 ret->plt.maybe_thumb_refcount = 0;
3249 ret->plt.noncall_refcount = 0;
3250 ret->plt.got_offset = -1;
3251 ret->is_iplt = FALSE;
a4fd1a8e 3252 ret->export_glue = NULL;
906e58ca
NC		 3253
3254 ret->stub_cache = NULL;
b7693d02 3255 }
780a67af
NC		 3256
3257 return (struct bfd_hash_entry *) ret;
3258}
3259
34e77a92
RS		 3260/* Ensure that we have allocated bookkeeping structures for ABFD's local
3261 symbols. */
3262
3263static bfd_boolean
3264elf32_arm_allocate_local_sym_info (bfd *abfd)
3265{
3266 if (elf_local_got_refcounts (abfd) == NULL)
3267 {
3268 bfd_size_type num_syms;
3269 bfd_size_type size;
3270 char *data;
3271
3272 num_syms = elf_tdata (abfd)->symtab_hdr.sh_info;
3273 size = num_syms * (sizeof (bfd_signed_vma)
3274 + sizeof (struct arm_local_iplt_info *)
3275 + sizeof (bfd_vma)
3276 + sizeof (char));
3277 data = bfd_zalloc (abfd, size);
3278 if (data == NULL)
3279 return FALSE;
3280
3281 elf_local_got_refcounts (abfd) = (bfd_signed_vma *) data;
3282 data += num_syms * sizeof (bfd_signed_vma);
3283
3284 elf32_arm_local_iplt (abfd) = (struct arm_local_iplt_info **) data;
3285 data += num_syms * sizeof (struct arm_local_iplt_info *);
3286
3287 elf32_arm_local_tlsdesc_gotent (abfd) = (bfd_vma *) data;
3288 data += num_syms * sizeof (bfd_vma);
3289
3290 elf32_arm_local_got_tls_type (abfd) = data;
3291 }
3292 return TRUE;
3293}
3294
3295/* Return the .iplt information for local symbol R_SYMNDX, which belongs
3296 to input bfd ABFD. Create the information if it doesn't already exist.
3297 Return null if an allocation fails. */
3298
3299static struct arm_local_iplt_info *
3300elf32_arm_create_local_iplt (bfd *abfd, unsigned long r_symndx)
3301{
3302 struct arm_local_iplt_info **ptr;
3303
3304 if (!elf32_arm_allocate_local_sym_info (abfd))
3305 return NULL;
3306
3307 BFD_ASSERT (r_symndx < elf_tdata (abfd)->symtab_hdr.sh_info);
3308 ptr = &elf32_arm_local_iplt (abfd)[r_symndx];
3309 if (*ptr == NULL)
3310 *ptr = bfd_zalloc (abfd, sizeof (**ptr));
3311 return *ptr;
3312}
3313
3314/* Try to obtain PLT information for the symbol with index R_SYMNDX
3315 in ABFD's symbol table. If the symbol is global, H points to its
3316 hash table entry, otherwise H is null.
3317
3318 Return true if the symbol does have PLT information. When returning
3319 true, point *ROOT_PLT at the target-independent reference count/offset
3320 union and *ARM_PLT at the ARM-specific information. */
3321
3322static bfd_boolean
3323elf32_arm_get_plt_info (bfd *abfd, struct elf32_arm_link_hash_entry *h,
3324 unsigned long r_symndx, union gotplt_union **root_plt,
3325 struct arm_plt_info **arm_plt)
3326{
3327 struct arm_local_iplt_info *local_iplt;
3328
3329 if (h != NULL)
3330 {
3331 *root_plt = &h->root.plt;
3332 *arm_plt = &h->plt;
3333 return TRUE;
3334 }
3335
3336 if (elf32_arm_local_iplt (abfd) == NULL)
3337 return FALSE;
3338
3339 local_iplt = elf32_arm_local_iplt (abfd)[r_symndx];
3340 if (local_iplt == NULL)
3341 return FALSE;
3342
3343 *root_plt = &local_iplt->root;
3344 *arm_plt = &local_iplt->arm;
3345 return TRUE;
3346}
3347
3348/* Return true if the PLT described by ARM_PLT requires a Thumb stub
3349 before it. */
3350
3351static bfd_boolean
3352elf32_arm_plt_needs_thumb_stub_p (struct bfd_link_info *info,
3353 struct arm_plt_info *arm_plt)
3354{
3355 struct elf32_arm_link_hash_table *htab;
3356
3357 htab = elf32_arm_hash_table (info);
3358 return (arm_plt->thumb_refcount != 0
3359 || (!htab->use_blx && arm_plt->maybe_thumb_refcount != 0));
3360}
3361
3362/* Return a pointer to the head of the dynamic reloc list that should
3363 be used for local symbol ISYM, which is symbol number R_SYMNDX in
3364 ABFD's symbol table. Return null if an error occurs. */
3365
3366static struct elf_dyn_relocs **
3367elf32_arm_get_local_dynreloc_list (bfd *abfd, unsigned long r_symndx,
3368 Elf_Internal_Sym *isym)
3369{
3370 if (ELF32_ST_TYPE (isym->st_info) == STT_GNU_IFUNC)
3371 {
3372 struct arm_local_iplt_info *local_iplt;
3373
3374 local_iplt = elf32_arm_create_local_iplt (abfd, r_symndx);
3375 if (local_iplt == NULL)
3376 return NULL;
3377 return &local_iplt->dyn_relocs;
3378 }
3379 else
3380 {
3381 /* Track dynamic relocs needed for local syms too.
3382 We really need local syms available to do this
3383 easily. Oh well. */
3384 asection *s;
3385 void *vpp;
3386
3387 s = bfd_section_from_elf_index (abfd, isym->st_shndx);
3388 if (s == NULL)
3389 abort ();
3390
3391 vpp = &elf_section_data (s)->local_dynrel;
3392 return (struct elf_dyn_relocs **) vpp;
3393 }
3394}
3395
906e58ca
NC		 3396/* Initialize an entry in the stub hash table. */
3397
3398static struct bfd_hash_entry *
3399stub_hash_newfunc (struct bfd_hash_entry *entry,
3400 struct bfd_hash_table *table,
3401 const char *string)
3402{
3403 /* Allocate the structure if it has not already been allocated by a
3404 subclass. */
3405 if (entry == NULL)
3406 {
21d799b5 3407 entry = (struct bfd_hash_entry *)
99059e56 3408 bfd_hash_allocate (table, sizeof (struct elf32_arm_stub_hash_entry));
906e58ca
NC		 3409 if (entry == NULL)
3410 return entry;
3411 }
3412
3413 /* Call the allocation method of the superclass. */
3414 entry = bfd_hash_newfunc (entry, table, string);
3415 if (entry != NULL)
3416 {
3417 struct elf32_arm_stub_hash_entry *eh;
3418
3419 /* Initialize the local fields. */
3420 eh = (struct elf32_arm_stub_hash_entry *) entry;
3421 eh->stub_sec = NULL;
3422 eh->stub_offset = 0;
8d9d9490 3423 eh->source_value = 0;
906e58ca
NC		 3424 eh->target_value = 0;
3425 eh->target_section = NULL;
cedfb179 3426 eh->orig_insn = 0;
906e58ca 3427 eh->stub_type = arm_stub_none;
461a49ca
DJ		 3428 eh->stub_size = 0;
3429 eh->stub_template = NULL;
3430 eh->stub_template_size = 0;
906e58ca
NC		 3431 eh->h = NULL;
3432 eh->id_sec = NULL;
d8d2f433 3433 eh->output_name = NULL;
906e58ca
NC		 3434 }
3435
3436 return entry;
3437}
3438
00a97672 3439/* Create .got, .gotplt, and .rel(a).got sections in DYNOBJ, and set up
5e681ec4
PB		 3440 shortcuts to them in our hash table. */
3441
3442static bfd_boolean
57e8b36a 3443create_got_section (bfd *dynobj, struct bfd_link_info *info)
5e681ec4
PB		 3444{
3445 struct elf32_arm_link_hash_table *htab;
3446
e5a52504 3447 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 3448 if (htab == NULL)
3449 return FALSE;
3450
e5a52504
MM		 3451 /* BPABI objects never have a GOT, or associated sections. */
3452 if (htab->symbian_p)
3453 return TRUE;
3454
5e681ec4
PB		 3455 if (! _bfd_elf_create_got_section (dynobj, info))
3456 return FALSE;
3457
5e681ec4
PB		 3458 return TRUE;
3459}
3460
34e77a92
RS		 3461/* Create the .iplt, .rel(a).iplt and .igot.plt sections. */
3462
3463static bfd_boolean
3464create_ifunc_sections (struct bfd_link_info *info)
3465{
3466 struct elf32_arm_link_hash_table *htab;
3467 const struct elf_backend_data *bed;
3468 bfd *dynobj;
3469 asection *s;
3470 flagword flags;
b38cadfb 3471
34e77a92
RS		 3472 htab = elf32_arm_hash_table (info);
3473 dynobj = htab->root.dynobj;
3474 bed = get_elf_backend_data (dynobj);
3475 flags = bed->dynamic_sec_flags;
3476
3477 if (htab->root.iplt == NULL)
3478 {
3d4d4302
AM		 3479 s = bfd_make_section_anyway_with_flags (dynobj, ".iplt",
3480 flags | SEC_READONLY | SEC_CODE);
34e77a92 3481 if (s == NULL
a0f49396 3482 || !bfd_set_section_alignment (dynobj, s, bed->plt_alignment))
34e77a92
RS		 3483 return FALSE;
3484 htab->root.iplt = s;
3485 }
3486
3487 if (htab->root.irelplt == NULL)
3488 {
3d4d4302
AM		 3489 s = bfd_make_section_anyway_with_flags (dynobj,
3490 RELOC_SECTION (htab, ".iplt"),
3491 flags | SEC_READONLY);
34e77a92 3492 if (s == NULL
a0f49396 3493 || !bfd_set_section_alignment (dynobj, s, bed->s->log_file_align))
34e77a92
RS		 3494 return FALSE;
3495 htab->root.irelplt = s;
3496 }
3497
3498 if (htab->root.igotplt == NULL)
3499 {
3d4d4302 3500 s = bfd_make_section_anyway_with_flags (dynobj, ".igot.plt", flags);
34e77a92
RS		 3501 if (s == NULL
3502 || !bfd_set_section_alignment (dynobj, s, bed->s->log_file_align))
3503 return FALSE;
3504 htab->root.igotplt = s;
3505 }
3506 return TRUE;
3507}
3508
eed94f8f
NC		 3509/* Determine if we're dealing with a Thumb only architecture. */
3510
3511static bfd_boolean
3512using_thumb_only (struct elf32_arm_link_hash_table *globals)
3513{
2fd158eb
TP		 3514 int arch;
3515 int profile = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC,
3516 Tag_CPU_arch_profile);
eed94f8f 3517
2fd158eb
TP		 3518 if (profile)
3519 return profile == 'M';
eed94f8f 3520
2fd158eb 3521 arch = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC, Tag_CPU_arch);
eed94f8f 3522
2fd158eb
TP		 3523 if (arch == TAG_CPU_ARCH_V6_M
3524 || arch == TAG_CPU_ARCH_V6S_M
3525 || arch == TAG_CPU_ARCH_V7E_M
3526 || arch == TAG_CPU_ARCH_V8M_BASE
3527 || arch == TAG_CPU_ARCH_V8M_MAIN)
3528 return TRUE;
eed94f8f 3529
2fd158eb 3530 return FALSE;
eed94f8f
NC		 3531}
3532
3533/* Determine if we're dealing with a Thumb-2 object. */
3534
3535static bfd_boolean
3536using_thumb2 (struct elf32_arm_link_hash_table *globals)
3537{
3538 int arch = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC,
3539 Tag_CPU_arch);
3540 return arch == TAG_CPU_ARCH_V6T2 || arch >= TAG_CPU_ARCH_V7;
3541}
3542
00a97672
RS		 3543/* Create .plt, .rel(a).plt, .got, .got.plt, .rel(a).got, .dynbss, and
3544 .rel(a).bss sections in DYNOBJ, and set up shortcuts to them in our
5e681ec4
PB		 3545 hash table. */
3546
3547static bfd_boolean
57e8b36a 3548elf32_arm_create_dynamic_sections (bfd *dynobj, struct bfd_link_info *info)
5e681ec4
PB		 3549{
3550 struct elf32_arm_link_hash_table *htab;
3551
3552 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 3553 if (htab == NULL)
3554 return FALSE;
3555
362d30a1 3556 if (!htab->root.sgot && !create_got_section (dynobj, info))
5e681ec4
PB		 3557 return FALSE;
3558
3559 if (!_bfd_elf_create_dynamic_sections (dynobj, info))
3560 return FALSE;
3561
3d4d4302 3562 htab->sdynbss = bfd_get_linker_section (dynobj, ".dynbss");
0e1862bb 3563 if (!bfd_link_pic (info))
3d4d4302
AM		 3564 htab->srelbss = bfd_get_linker_section (dynobj,
3565 RELOC_SECTION (htab, ".bss"));
00a97672
RS		 3566
3567 if (htab->vxworks_p)
3568 {
3569 if (!elf_vxworks_create_dynamic_sections (dynobj, info, &htab->srelplt2))
3570 return FALSE;
3571
0e1862bb 3572 if (bfd_link_pic (info))
00a97672
RS		 3573 {
3574 htab->plt_header_size = 0;
3575 htab->plt_entry_size
3576 = 4 * ARRAY_SIZE (elf32_arm_vxworks_shared_plt_entry);
3577 }
3578 else
3579 {
3580 htab->plt_header_size
3581 = 4 * ARRAY_SIZE (elf32_arm_vxworks_exec_plt0_entry);
3582 htab->plt_entry_size
3583 = 4 * ARRAY_SIZE (elf32_arm_vxworks_exec_plt_entry);
3584 }
aebf9be7
NC		 3585
3586 if (elf_elfheader (dynobj))
3587 elf_elfheader (dynobj)->e_ident[EI_CLASS] = ELFCLASS32;
00a97672 3588 }
eed94f8f
NC		 3589 else
3590 {
3591 /* PR ld/16017
3592 Test for thumb only architectures. Note - we cannot just call
3593 using_thumb_only() as the attributes in the output bfd have not been
3594 initialised at this point, so instead we use the input bfd. */
3595 bfd * saved_obfd = htab->obfd;
3596
3597 htab->obfd = dynobj;
3598 if (using_thumb_only (htab))
3599 {
3600 htab->plt_header_size = 4 * ARRAY_SIZE (elf32_thumb2_plt0_entry);
3601 htab->plt_entry_size = 4 * ARRAY_SIZE (elf32_thumb2_plt_entry);
3602 }
3603 htab->obfd = saved_obfd;
3604 }
5e681ec4 3605
362d30a1
RS		 3606 if (!htab->root.splt
3607 || !htab->root.srelplt
e5a52504 3608 || !htab->sdynbss
0e1862bb 3609 || (!bfd_link_pic (info) && !htab->srelbss))
5e681ec4
PB		 3610 abort ();
3611
3612 return TRUE;
3613}
3614
906e58ca
NC		 3615/* Copy the extra info we tack onto an elf_link_hash_entry. */
3616
3617static void
3618elf32_arm_copy_indirect_symbol (struct bfd_link_info *info,
3619 struct elf_link_hash_entry *dir,
3620 struct elf_link_hash_entry *ind)
3621{
3622 struct elf32_arm_link_hash_entry *edir, *eind;
3623
3624 edir = (struct elf32_arm_link_hash_entry *) dir;
3625 eind = (struct elf32_arm_link_hash_entry *) ind;
3626
0bdcacaf 3627 if (eind->dyn_relocs != NULL)
906e58ca 3628 {
0bdcacaf 3629 if (edir->dyn_relocs != NULL)
906e58ca 3630 {
0bdcacaf
RS		 3631 struct elf_dyn_relocs **pp;
3632 struct elf_dyn_relocs *p;
906e58ca
NC		 3633
3634 /* Add reloc counts against the indirect sym to the direct sym
3635 list. Merge any entries against the same section. */
0bdcacaf 3636 for (pp = &eind->dyn_relocs; (p = *pp) != NULL; )
906e58ca 3637 {
0bdcacaf 3638 struct elf_dyn_relocs *q;
906e58ca 3639
0bdcacaf
RS		 3640 for (q = edir->dyn_relocs; q != NULL; q = q->next)
3641 if (q->sec == p->sec)
906e58ca
NC		 3642 {
3643 q->pc_count += p->pc_count;
3644 q->count += p->count;
3645 *pp = p->next;
3646 break;
3647 }
3648 if (q == NULL)
3649 pp = &p->next;
3650 }
0bdcacaf 3651 *pp = edir->dyn_relocs;
906e58ca
NC		 3652 }
3653
0bdcacaf
RS		 3654 edir->dyn_relocs = eind->dyn_relocs;
3655 eind->dyn_relocs = NULL;
906e58ca
NC		 3656 }
3657
3658 if (ind->root.type == bfd_link_hash_indirect)
3659 {
3660 /* Copy over PLT info. */
34e77a92
RS		 3661 edir->plt.thumb_refcount += eind->plt.thumb_refcount;
3662 eind->plt.thumb_refcount = 0;
3663 edir->plt.maybe_thumb_refcount += eind->plt.maybe_thumb_refcount;
3664 eind->plt.maybe_thumb_refcount = 0;
3665 edir->plt.noncall_refcount += eind->plt.noncall_refcount;
3666 eind->plt.noncall_refcount = 0;
3667
3668 /* We should only allocate a function to .iplt once the final
3669 symbol information is known. */
3670 BFD_ASSERT (!eind->is_iplt);
906e58ca
NC		 3671
3672 if (dir->got.refcount <= 0)
3673 {
3674 edir->tls_type = eind->tls_type;
3675 eind->tls_type = GOT_UNKNOWN;
3676 }
3677 }
3678
3679 _bfd_elf_link_hash_copy_indirect (info, dir, ind);
3680}
3681
68faa637
AM		 3682/* Destroy an ARM elf linker hash table. */
3683
3684static void
d495ab0d 3685elf32_arm_link_hash_table_free (bfd *obfd)
68faa637
AM		 3686{
3687 struct elf32_arm_link_hash_table *ret
d495ab0d 3688 = (struct elf32_arm_link_hash_table *) obfd->link.hash;
68faa637
AM		 3689
3690 bfd_hash_table_free (&ret->stub_hash_table);
d495ab0d 3691 _bfd_elf_link_hash_table_free (obfd);
68faa637
AM		 3692}
3693
906e58ca
NC		 3694/* Create an ARM elf linker hash table. */
3695
3696static struct bfd_link_hash_table *
3697elf32_arm_link_hash_table_create (bfd *abfd)
3698{
3699 struct elf32_arm_link_hash_table *ret;
3700 bfd_size_type amt = sizeof (struct elf32_arm_link_hash_table);
3701
7bf52ea2 3702 ret = (struct elf32_arm_link_hash_table *) bfd_zmalloc (amt);
906e58ca
NC		 3703 if (ret == NULL)
3704 return NULL;
3705
3706 if (!_bfd_elf_link_hash_table_init (& ret->root, abfd,
3707 elf32_arm_link_hash_newfunc,
4dfe6ac6
NC		 3708 sizeof (struct elf32_arm_link_hash_entry),
3709 ARM_ELF_DATA))
906e58ca
NC		 3710 {
3711 free (ret);
3712 return NULL;
3713 }
3714
906e58ca 3715 ret->vfp11_fix = BFD_ARM_VFP11_FIX_NONE;
a504d23a 3716 ret->stm32l4xx_fix = BFD_ARM_STM32L4XX_FIX_NONE;
906e58ca
NC		 3717#ifdef FOUR_WORD_PLT
3718 ret->plt_header_size = 16;
3719 ret->plt_entry_size = 16;
3720#else
3721 ret->plt_header_size = 20;
1db37fe6 3722 ret->plt_entry_size = elf32_arm_use_long_plt_entry ? 16 : 12;
906e58ca 3723#endif
906e58ca 3724 ret->use_rel = 1;
906e58ca 3725 ret->obfd = abfd;
906e58ca
NC		 3726
3727 if (!bfd_hash_table_init (&ret->stub_hash_table, stub_hash_newfunc,
3728 sizeof (struct elf32_arm_stub_hash_entry)))
3729 {
d495ab0d 3730 _bfd_elf_link_hash_table_free (abfd);
906e58ca
NC		 3731 return NULL;
3732 }
d495ab0d 3733 ret->root.root.hash_table_free = elf32_arm_link_hash_table_free;
906e58ca
NC		 3734
3735 return &ret->root.root;
3736}
3737
cd1dac3d
DG		 3738/* Determine what kind of NOPs are available. */
3739
3740static bfd_boolean
3741arch_has_arm_nop (struct elf32_arm_link_hash_table *globals)
3742{
3743 const int arch = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC,
3744 Tag_CPU_arch);
3745 return arch == TAG_CPU_ARCH_V6T2
3746 || arch == TAG_CPU_ARCH_V6K
9e3c6df6
PB		 3747 || arch == TAG_CPU_ARCH_V7
3748 || arch == TAG_CPU_ARCH_V7E_M;
cd1dac3d
DG		 3749}
3750
3751static bfd_boolean
3752arch_has_thumb2_nop (struct elf32_arm_link_hash_table *globals)
3753{
3754 const int arch = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC,
3755 Tag_CPU_arch);
9e3c6df6
PB		 3756 return (arch == TAG_CPU_ARCH_V6T2 || arch == TAG_CPU_ARCH_V7
3757 || arch == TAG_CPU_ARCH_V7E_M);
cd1dac3d
DG		 3758}
3759
f4ac8484
DJ		 3760static bfd_boolean
3761arm_stub_is_thumb (enum elf32_arm_stub_type stub_type)
3762{
3763 switch (stub_type)
3764 {
fea2b4d6
CL		 3765 case arm_stub_long_branch_thumb_only:
3766 case arm_stub_long_branch_v4t_thumb_arm:
3767 case arm_stub_short_branch_v4t_thumb_arm:
ebe24dd4 3768 case arm_stub_long_branch_v4t_thumb_arm_pic:
12352d3f 3769 case arm_stub_long_branch_v4t_thumb_tls_pic:
ebe24dd4 3770 case arm_stub_long_branch_thumb_only_pic:
f4ac8484
DJ		 3771 return TRUE;
3772 case arm_stub_none:
3773 BFD_FAIL ();
3774 return FALSE;
3775 break;
3776 default:
3777 return FALSE;
3778 }
3779}
3780
906e58ca
NC		 3781/* Determine the type of stub needed, if any, for a call. */
3782
3783static enum elf32_arm_stub_type
3784arm_type_of_stub (struct bfd_link_info *info,
3785 asection *input_sec,
3786 const Elf_Internal_Rela *rel,
34e77a92 3787 unsigned char st_type,
35fc36a8 3788 enum arm_st_branch_type *actual_branch_type,
906e58ca 3789 struct elf32_arm_link_hash_entry *hash,
c820be07
NC		 3790 bfd_vma destination,
3791 asection *sym_sec,
3792 bfd *input_bfd,
3793 const char *name)
906e58ca
NC		 3794{
3795 bfd_vma location;
3796 bfd_signed_vma branch_offset;
3797 unsigned int r_type;
3798 struct elf32_arm_link_hash_table * globals;
3799 int thumb2;
3800 int thumb_only;
3801 enum elf32_arm_stub_type stub_type = arm_stub_none;
5fa9e92f 3802 int use_plt = 0;
35fc36a8 3803 enum arm_st_branch_type branch_type = *actual_branch_type;
34e77a92
RS		 3804 union gotplt_union *root_plt;
3805 struct arm_plt_info *arm_plt;
906e58ca 3806
35fc36a8 3807 if (branch_type == ST_BRANCH_LONG)
da5938a2
NC		 3808 return stub_type;
3809
906e58ca 3810 globals = elf32_arm_hash_table (info);
4dfe6ac6
NC		 3811 if (globals == NULL)
3812 return stub_type;
906e58ca
NC		 3813
3814 thumb_only = using_thumb_only (globals);
3815
3816 thumb2 = using_thumb2 (globals);
3817
3818 /* Determine where the call point is. */
3819 location = (input_sec->output_offset
3820 + input_sec->output_section->vma
3821 + rel->r_offset);
3822
906e58ca
NC		 3823 r_type = ELF32_R_TYPE (rel->r_info);
3824
39f21624
NC		 3825 /* ST_BRANCH_TO_ARM is nonsense to thumb-only targets when we
3826 are considering a function call relocation. */
c5423981
TG		 3827 if (thumb_only && (r_type == R_ARM_THM_CALL || r_type == R_ARM_THM_JUMP24
3828 || r_type == R_ARM_THM_JUMP19)
39f21624
NC		 3829 && branch_type == ST_BRANCH_TO_ARM)
3830 branch_type = ST_BRANCH_TO_THUMB;
3831
34e77a92
RS		 3832 /* For TLS call relocs, it is the caller's responsibility to provide
3833 the address of the appropriate trampoline. */
3834 if (r_type != R_ARM_TLS_CALL
3835 && r_type != R_ARM_THM_TLS_CALL
3836 && elf32_arm_get_plt_info (input_bfd, hash, ELF32_R_SYM (rel->r_info),
3837 &root_plt, &arm_plt)
3838 && root_plt->offset != (bfd_vma) -1)
5fa9e92f 3839 {
34e77a92 3840 asection *splt;
fe33d2fa 3841
34e77a92
RS		 3842 if (hash == NULL || hash->is_iplt)
3843 splt = globals->root.iplt;
3844 else
3845 splt = globals->root.splt;
3846 if (splt != NULL)
b38cadfb 3847 {
34e77a92
RS		 3848 use_plt = 1;
3849
3850 /* Note when dealing with PLT entries: the main PLT stub is in
3851 ARM mode, so if the branch is in Thumb mode, another
3852 Thumb->ARM stub will be inserted later just before the ARM
3853 PLT stub. We don't take this extra distance into account
3854 here, because if a long branch stub is needed, we'll add a
3855 Thumb->Arm one and branch directly to the ARM PLT entry
3856 because it avoids spreading offset corrections in several
3857 places. */
3858
3859 destination = (splt->output_section->vma
3860 + splt->output_offset
3861 + root_plt->offset);
3862 st_type = STT_FUNC;
3863 branch_type = ST_BRANCH_TO_ARM;
3864 }
5fa9e92f 3865 }
34e77a92
RS		 3866 /* Calls to STT_GNU_IFUNC symbols should go through a PLT. */
3867 BFD_ASSERT (st_type != STT_GNU_IFUNC);
906e58ca 3868
fe33d2fa
CL		 3869 branch_offset = (bfd_signed_vma)(destination - location);
3870
0855e32b 3871 if (r_type == R_ARM_THM_CALL || r_type == R_ARM_THM_JUMP24
c5423981 3872 || r_type == R_ARM_THM_TLS_CALL || r_type == R_ARM_THM_JUMP19)
906e58ca 3873 {
5fa9e92f
CL		 3874 /* Handle cases where:
3875 - this call goes too far (different Thumb/Thumb2 max
99059e56 3876 distance)
155d87d7 3877 - it's a Thumb->Arm call and blx is not available, or it's a
99059e56
RM		 3878 Thumb->Arm branch (not bl). A stub is needed in this case,
3879 but only if this call is not through a PLT entry. Indeed,
3880 PLT stubs handle mode switching already.
5fa9e92f 3881 */
906e58ca
NC		 3882 if ((!thumb2
3883 && (branch_offset > THM_MAX_FWD_BRANCH_OFFSET
3884 || (branch_offset < THM_MAX_BWD_BRANCH_OFFSET)))
3885 || (thumb2
3886 && (branch_offset > THM2_MAX_FWD_BRANCH_OFFSET
3887 || (branch_offset < THM2_MAX_BWD_BRANCH_OFFSET)))
c5423981
TG		 3888 || (thumb2
3889 && (branch_offset > THM2_MAX_FWD_COND_BRANCH_OFFSET
3890 || (branch_offset < THM2_MAX_BWD_COND_BRANCH_OFFSET))
3891 && (r_type == R_ARM_THM_JUMP19))
35fc36a8 3892 || (branch_type == ST_BRANCH_TO_ARM
0855e32b
NS		 3893 && (((r_type == R_ARM_THM_CALL
3894 || r_type == R_ARM_THM_TLS_CALL) && !globals->use_blx)
c5423981
TG		 3895 || (r_type == R_ARM_THM_JUMP24)
3896 || (r_type == R_ARM_THM_JUMP19))
5fa9e92f 3897 && !use_plt))
906e58ca 3898 {
35fc36a8 3899 if (branch_type == ST_BRANCH_TO_THUMB)
906e58ca
NC		 3900 {
3901 /* Thumb to thumb. */
3902 if (!thumb_only)
3903 {
0e1862bb 3904 stub_type = (bfd_link_pic (info) | globals->pic_veneer)
c2b4a39d 3905 /* PIC stubs. */
155d87d7 3906 ? ((globals->use_blx
9553db3c 3907 && (r_type == R_ARM_THM_CALL))
155d87d7
CL		 3908 /* V5T and above. Stub starts with ARM code, so
3909 we must be able to switch mode before
3910 reaching it, which is only possible for 'bl'
3911 (ie R_ARM_THM_CALL relocation). */
cf3eccff 3912 ? arm_stub_long_branch_any_thumb_pic
ebe24dd4 3913 /* On V4T, use Thumb code only. */
d3626fb0 3914 : arm_stub_long_branch_v4t_thumb_thumb_pic)
c2b4a39d
CL		 3915
3916 /* non-PIC stubs. */
155d87d7 3917 : ((globals->use_blx
9553db3c 3918 && (r_type == R_ARM_THM_CALL))
c2b4a39d
CL		 3919 /* V5T and above. */
3920 ? arm_stub_long_branch_any_any
3921 /* V4T. */
d3626fb0 3922 : arm_stub_long_branch_v4t_thumb_thumb);
906e58ca
NC		 3923 }
3924 else
3925 {
0e1862bb 3926 stub_type = (bfd_link_pic (info) | globals->pic_veneer)
ebe24dd4
CL		 3927 /* PIC stub. */
3928 ? arm_stub_long_branch_thumb_only_pic
c2b4a39d
CL		 3929 /* non-PIC stub. */
3930 : arm_stub_long_branch_thumb_only;
906e58ca
NC		 3931 }
3932 }
3933 else
3934 {
3935 /* Thumb to arm. */
c820be07
NC		 3936 if (sym_sec != NULL
3937 && sym_sec->owner != NULL
3938 && !INTERWORK_FLAG (sym_sec->owner))
3939 {
3940 (*_bfd_error_handler)
3941 (_("%B(%s): warning: interworking not enabled.\n"
3942 " first occurrence: %B: Thumb call to ARM"),
3943 sym_sec->owner, input_bfd, name);
3944 }
3945
0855e32b 3946 stub_type =
0e1862bb 3947 (bfd_link_pic (info) | globals->pic_veneer)
c2b4a39d 3948 /* PIC stubs. */
0855e32b 3949 ? (r_type == R_ARM_THM_TLS_CALL
6a631e86 3950 /* TLS PIC stubs. */
0855e32b
NS		 3951 ? (globals->use_blx ? arm_stub_long_branch_any_tls_pic
3952 : arm_stub_long_branch_v4t_thumb_tls_pic)
3953 : ((globals->use_blx && r_type == R_ARM_THM_CALL)
3954 /* V5T PIC and above. */
3955 ? arm_stub_long_branch_any_arm_pic
3956 /* V4T PIC stub. */
3957 : arm_stub_long_branch_v4t_thumb_arm_pic))
c2b4a39d
CL		 3958
3959 /* non-PIC stubs. */
0855e32b 3960 : ((globals->use_blx && r_type == R_ARM_THM_CALL)
c2b4a39d
CL		 3961 /* V5T and above. */
3962 ? arm_stub_long_branch_any_any
3963 /* V4T. */
3964 : arm_stub_long_branch_v4t_thumb_arm);
c820be07
NC		 3965
3966 /* Handle v4t short branches. */
fea2b4d6 3967 if ((stub_type == arm_stub_long_branch_v4t_thumb_arm)
c820be07
NC		 3968 && (branch_offset <= THM_MAX_FWD_BRANCH_OFFSET)
3969 && (branch_offset >= THM_MAX_BWD_BRANCH_OFFSET))
fea2b4d6 3970 stub_type = arm_stub_short_branch_v4t_thumb_arm;
906e58ca
NC		 3971 }
3972 }
3973 }
fe33d2fa
CL		 3974 else if (r_type == R_ARM_CALL
3975 || r_type == R_ARM_JUMP24
0855e32b
NS		 3976 || r_type == R_ARM_PLT32
3977 || r_type == R_ARM_TLS_CALL)
906e58ca 3978 {
35fc36a8 3979 if (branch_type == ST_BRANCH_TO_THUMB)
906e58ca
NC		 3980 {
3981 /* Arm to thumb. */
c820be07
NC		 3982
3983 if (sym_sec != NULL
3984 && sym_sec->owner != NULL
3985 && !INTERWORK_FLAG (sym_sec->owner))
3986 {
3987 (*_bfd_error_handler)
3988 (_("%B(%s): warning: interworking not enabled.\n"
c2b4a39d 3989 " first occurrence: %B: ARM call to Thumb"),
c820be07
NC		 3990 sym_sec->owner, input_bfd, name);
3991 }
3992
3993 /* We have an extra 2-bytes reach because of
3994 the mode change (bit 24 (H) of BLX encoding). */
4116d8d7
PB		 3995 if (branch_offset > (ARM_MAX_FWD_BRANCH_OFFSET + 2)
3996 || (branch_offset < ARM_MAX_BWD_BRANCH_OFFSET)
0855e32b 3997 || (r_type == R_ARM_CALL && !globals->use_blx)
4116d8d7
PB		 3998 || (r_type == R_ARM_JUMP24)
3999 || (r_type == R_ARM_PLT32))
906e58ca 4000 {
0e1862bb 4001 stub_type = (bfd_link_pic (info) | globals->pic_veneer)
c2b4a39d 4002 /* PIC stubs. */
ebe24dd4
CL		 4003 ? ((globals->use_blx)
4004 /* V5T and above. */
4005 ? arm_stub_long_branch_any_thumb_pic
4006 /* V4T stub. */
4007 : arm_stub_long_branch_v4t_arm_thumb_pic)
4008
c2b4a39d
CL		 4009 /* non-PIC stubs. */
4010 : ((globals->use_blx)
4011 /* V5T and above. */
4012 ? arm_stub_long_branch_any_any
4013 /* V4T. */
4014 : arm_stub_long_branch_v4t_arm_thumb);
906e58ca
NC		 4015 }
4016 }
4017 else
4018 {
4019 /* Arm to arm. */
4020 if (branch_offset > ARM_MAX_FWD_BRANCH_OFFSET
4021 || (branch_offset < ARM_MAX_BWD_BRANCH_OFFSET))
4022 {
0855e32b 4023 stub_type =
0e1862bb 4024 (bfd_link_pic (info) | globals->pic_veneer)
c2b4a39d 4025 /* PIC stubs. */
0855e32b 4026 ? (r_type == R_ARM_TLS_CALL
6a631e86 4027 /* TLS PIC Stub. */
0855e32b 4028 ? arm_stub_long_branch_any_tls_pic
7a89b94e
NC		 4029 : (globals->nacl_p
4030 ? arm_stub_long_branch_arm_nacl_pic
4031 : arm_stub_long_branch_any_arm_pic))
c2b4a39d 4032 /* non-PIC stubs. */
7a89b94e
NC		 4033 : (globals->nacl_p
4034 ? arm_stub_long_branch_arm_nacl
4035 : arm_stub_long_branch_any_any);
906e58ca
NC		 4036 }
4037 }
4038 }
4039
fe33d2fa
CL		 4040 /* If a stub is needed, record the actual destination type. */
4041 if (stub_type != arm_stub_none)
35fc36a8 4042 *actual_branch_type = branch_type;
fe33d2fa 4043
906e58ca
NC		 4044 return stub_type;
4045}
4046
4047/* Build a name for an entry in the stub hash table. */
4048
4049static char *
4050elf32_arm_stub_name (const asection *input_section,
4051 const asection *sym_sec,
4052 const struct elf32_arm_link_hash_entry *hash,
fe33d2fa
CL		 4053 const Elf_Internal_Rela *rel,
4054 enum elf32_arm_stub_type stub_type)
906e58ca
NC		 4055{
4056 char *stub_name;
4057 bfd_size_type len;
4058
4059 if (hash)
4060 {
fe33d2fa 4061 len = 8 + 1 + strlen (hash->root.root.root.string) + 1 + 8 + 1 + 2 + 1;
21d799b5 4062 stub_name = (char *) bfd_malloc (len);
906e58ca 4063 if (stub_name != NULL)
fe33d2fa 4064 sprintf (stub_name, "%08x_%s+%x_%d",
906e58ca
NC		 4065 input_section->id & 0xffffffff,
4066 hash->root.root.root.string,
fe33d2fa
CL		 4067 (int) rel->r_addend & 0xffffffff,
4068 (int) stub_type);
906e58ca
NC		 4069 }
4070 else
4071 {
fe33d2fa 4072 len = 8 + 1 + 8 + 1 + 8 + 1 + 8 + 1 + 2 + 1;
21d799b5 4073 stub_name = (char *) bfd_malloc (len);
906e58ca 4074 if (stub_name != NULL)
fe33d2fa 4075 sprintf (stub_name, "%08x_%x:%x+%x_%d",
906e58ca
NC		 4076 input_section->id & 0xffffffff,
4077 sym_sec->id & 0xffffffff,
0855e32b
NS		 4078 ELF32_R_TYPE (rel->r_info) == R_ARM_TLS_CALL
4079 || ELF32_R_TYPE (rel->r_info) == R_ARM_THM_TLS_CALL
4080 ? 0 : (int) ELF32_R_SYM (rel->r_info) & 0xffffffff,
fe33d2fa
CL		 4081 (int) rel->r_addend & 0xffffffff,
4082 (int) stub_type);
906e58ca
NC		 4083 }
4084
4085 return stub_name;
4086}
4087
4088/* Look up an entry in the stub hash. Stub entries are cached because
4089 creating the stub name takes a bit of time. */
4090
4091static struct elf32_arm_stub_hash_entry *
4092elf32_arm_get_stub_entry (const asection *input_section,
4093 const asection *sym_sec,
4094 struct elf_link_hash_entry *hash,
4095 const Elf_Internal_Rela *rel,
fe33d2fa
CL		 4096 struct elf32_arm_link_hash_table *htab,
4097 enum elf32_arm_stub_type stub_type)
906e58ca
NC		 4098{
4099 struct elf32_arm_stub_hash_entry *stub_entry;
4100 struct elf32_arm_link_hash_entry *h = (struct elf32_arm_link_hash_entry *) hash;
4101 const asection *id_sec;
4102
4103 if ((input_section->flags & SEC_CODE) == 0)
4104 return NULL;
4105
4106 /* If this input section is part of a group of sections sharing one
4107 stub section, then use the id of the first section in the group.
4108 Stub names need to include a section id, as there may well be
4109 more than one stub used to reach say, printf, and we need to
4110 distinguish between them. */
4111 id_sec = htab->stub_group[input_section->id].link_sec;
4112
4113 if (h != NULL && h->stub_cache != NULL
4114 && h->stub_cache->h == h
fe33d2fa
CL		 4115 && h->stub_cache->id_sec == id_sec
4116 && h->stub_cache->stub_type == stub_type)
906e58ca
NC		 4117 {
4118 stub_entry = h->stub_cache;
4119 }
4120 else
4121 {
4122 char *stub_name;
4123
fe33d2fa 4124 stub_name = elf32_arm_stub_name (id_sec, sym_sec, h, rel, stub_type);
906e58ca
NC		 4125 if (stub_name == NULL)
4126 return NULL;
4127
4128 stub_entry = arm_stub_hash_lookup (&htab->stub_hash_table,
4129 stub_name, FALSE, FALSE);
4130 if (h != NULL)
4131 h->stub_cache = stub_entry;
4132
4133 free (stub_name);
4134 }
4135
4136 return stub_entry;
4137}
4138
48229727 4139/* Find or create a stub section. Returns a pointer to the stub section, and
b38cadfb 4140 the section to which the stub section will be attached (in *LINK_SEC_P).
48229727 4141 LINK_SEC_P may be NULL. */
906e58ca 4142
48229727
JB		 4143static asection *
4144elf32_arm_create_or_find_stub_sec (asection **link_sec_p, asection *section,
4145 struct elf32_arm_link_hash_table *htab)
906e58ca
NC		 4146{
4147 asection *link_sec;
4148 asection *stub_sec;
6bde4c52 4149 asection *out_sec;
906e58ca
NC		 4150
4151 link_sec = htab->stub_group[section->id].link_sec;
9553db3c 4152 BFD_ASSERT (link_sec != NULL);
906e58ca 4153 stub_sec = htab->stub_group[section->id].stub_sec;
9553db3c 4154
906e58ca
NC		 4155 if (stub_sec == NULL)
4156 {
4157 stub_sec = htab->stub_group[link_sec->id].stub_sec;
4158 if (stub_sec == NULL)
4159 {
4160 size_t namelen;
4161 bfd_size_type len;
4162 char *s_name;
4163
4164 namelen = strlen (link_sec->name);
4165 len = namelen + sizeof (STUB_SUFFIX);
21d799b5 4166 s_name = (char *) bfd_alloc (htab->stub_bfd, len);
906e58ca
NC		 4167 if (s_name == NULL)
4168 return NULL;
4169
4170 memcpy (s_name, link_sec->name, namelen);
4171 memcpy (s_name + namelen, STUB_SUFFIX, sizeof (STUB_SUFFIX));
6bde4c52
TP		 4172 out_sec = link_sec->output_section;
4173 stub_sec = (*htab->add_stub_section) (s_name, out_sec, link_sec,
7a89b94e 4174 htab->nacl_p ? 4 : 3);
906e58ca
NC		 4175 if (stub_sec == NULL)
4176 return NULL;
4177 htab->stub_group[link_sec->id].stub_sec = stub_sec;
4178 }
4179 htab->stub_group[section->id].stub_sec = stub_sec;
4180 }
b38cadfb 4181
48229727
JB		 4182 if (link_sec_p)
4183 *link_sec_p = link_sec;
b38cadfb 4184
48229727
JB		 4185 return stub_sec;
4186}
4187
4188/* Add a new stub entry to the stub hash. Not all fields of the new
4189 stub entry are initialised. */
4190
4191static struct elf32_arm_stub_hash_entry *
4192elf32_arm_add_stub (const char *stub_name,
4193 asection *section,
4194 struct elf32_arm_link_hash_table *htab)
4195{
4196 asection *link_sec;
4197 asection *stub_sec;
4198 struct elf32_arm_stub_hash_entry *stub_entry;
4199
4200 stub_sec = elf32_arm_create_or_find_stub_sec (&link_sec, section, htab);
4201 if (stub_sec == NULL)
4202 return NULL;
906e58ca
NC		 4203
4204 /* Enter this entry into the linker stub hash table. */
4205 stub_entry = arm_stub_hash_lookup (&htab->stub_hash_table, stub_name,
4206 TRUE, FALSE);
4207 if (stub_entry == NULL)
4208 {
6bde4c52
TP		 4209 if (section == NULL)
4210 section = stub_sec;
906e58ca
NC		 4211 (*_bfd_error_handler) (_("%s: cannot create stub entry %s"),
4212 section->owner,
4213 stub_name);
4214 return NULL;
4215 }
4216
4217 stub_entry->stub_sec = stub_sec;
4218 stub_entry->stub_offset = 0;
4219 stub_entry->id_sec = link_sec;
4220
906e58ca
NC		 4221 return stub_entry;
4222}
4223
4224/* Store an Arm insn into an output section not processed by
4225 elf32_arm_write_section. */
4226
4227static void
8029a119
NC		 4228put_arm_insn (struct elf32_arm_link_hash_table * htab,
4229 bfd * output_bfd, bfd_vma val, void * ptr)
906e58ca
NC		 4230{
4231 if (htab->byteswap_code != bfd_little_endian (output_bfd))
4232 bfd_putl32 (val, ptr);
4233 else
4234 bfd_putb32 (val, ptr);
4235}
4236
4237/* Store a 16-bit Thumb insn into an output section not processed by
4238 elf32_arm_write_section. */
4239
4240static void
8029a119
NC		 4241put_thumb_insn (struct elf32_arm_link_hash_table * htab,
4242 bfd * output_bfd, bfd_vma val, void * ptr)
906e58ca
NC		 4243{
4244 if (htab->byteswap_code != bfd_little_endian (output_bfd))
4245 bfd_putl16 (val, ptr);
4246 else
4247 bfd_putb16 (val, ptr);
4248}
4249
a504d23a
LA		 4250/* Store a Thumb2 insn into an output section not processed by
4251 elf32_arm_write_section. */
4252
4253static void
4254put_thumb2_insn (struct elf32_arm_link_hash_table * htab,
b98e6871 4255 bfd * output_bfd, bfd_vma val, bfd_byte * ptr)
a504d23a
LA		 4256{
4257 /* T2 instructions are 16-bit streamed. */
4258 if (htab->byteswap_code != bfd_little_endian (output_bfd))
4259 {
4260 bfd_putl16 ((val >> 16) & 0xffff, ptr);
4261 bfd_putl16 ((val & 0xffff), ptr + 2);
4262 }
4263 else
4264 {
4265 bfd_putb16 ((val >> 16) & 0xffff, ptr);
4266 bfd_putb16 ((val & 0xffff), ptr + 2);
4267 }
4268}
4269
0855e32b
NS		 4270/* If it's possible to change R_TYPE to a more efficient access
4271 model, return the new reloc type. */
4272
4273static unsigned
b38cadfb 4274elf32_arm_tls_transition (struct bfd_link_info *info, int r_type,
0855e32b
NS		 4275 struct elf_link_hash_entry *h)
4276{
4277 int is_local = (h == NULL);
4278
0e1862bb
L		 4279 if (bfd_link_pic (info)
4280 || (h && h->root.type == bfd_link_hash_undefweak))
0855e32b
NS		 4281 return r_type;
4282
b38cadfb 4283 /* We do not support relaxations for Old TLS models. */
0855e32b
NS		 4284 switch (r_type)
4285 {
4286 case R_ARM_TLS_GOTDESC:
4287 case R_ARM_TLS_CALL:
4288 case R_ARM_THM_TLS_CALL:
4289 case R_ARM_TLS_DESCSEQ:
4290 case R_ARM_THM_TLS_DESCSEQ:
4291 return is_local ? R_ARM_TLS_LE32 : R_ARM_TLS_IE32;
4292 }
4293
4294 return r_type;
4295}
4296
48229727
JB		 4297static bfd_reloc_status_type elf32_arm_final_link_relocate
4298 (reloc_howto_type *, bfd *, bfd *, asection *, bfd_byte *,
4299 Elf_Internal_Rela *, bfd_vma, struct bfd_link_info *, asection *,
34e77a92
RS		 4300 const char *, unsigned char, enum arm_st_branch_type,
4301 struct elf_link_hash_entry *, bfd_boolean *, char **);
48229727 4302
4563a860
JB		 4303static unsigned int
4304arm_stub_required_alignment (enum elf32_arm_stub_type stub_type)
4305{
4306 switch (stub_type)
4307 {
4308 case arm_stub_a8_veneer_b_cond:
4309 case arm_stub_a8_veneer_b:
4310 case arm_stub_a8_veneer_bl:
4311 return 2;
4312
4313 case arm_stub_long_branch_any_any:
4314 case arm_stub_long_branch_v4t_arm_thumb:
4315 case arm_stub_long_branch_thumb_only:
4316 case arm_stub_long_branch_v4t_thumb_thumb:
4317 case arm_stub_long_branch_v4t_thumb_arm:
4318 case arm_stub_short_branch_v4t_thumb_arm:
4319 case arm_stub_long_branch_any_arm_pic:
4320 case arm_stub_long_branch_any_thumb_pic:
4321 case arm_stub_long_branch_v4t_thumb_thumb_pic:
4322 case arm_stub_long_branch_v4t_arm_thumb_pic:
4323 case arm_stub_long_branch_v4t_thumb_arm_pic:
4324 case arm_stub_long_branch_thumb_only_pic:
0855e32b
NS		 4325 case arm_stub_long_branch_any_tls_pic:
4326 case arm_stub_long_branch_v4t_thumb_tls_pic:
4563a860
JB		 4327 case arm_stub_a8_veneer_blx:
4328 return 4;
b38cadfb 4329
7a89b94e
NC		 4330 case arm_stub_long_branch_arm_nacl:
4331 case arm_stub_long_branch_arm_nacl_pic:
4332 return 16;
4333
4563a860
JB		 4334 default:
4335 abort (); /* Should be unreachable. */
4336 }
4337}
4338
4f4faa4d
TP		 4339/* Returns whether stubs of type STUB_TYPE take over the symbol they are
4340 veneering (TRUE) or have their own symbol (FALSE). */
4341
4342static bfd_boolean
4343arm_stub_sym_claimed (enum elf32_arm_stub_type stub_type)
4344{
4345 if (stub_type >= max_stub_type)
4346 abort (); /* Should be unreachable. */
4347
4348 return FALSE;
4349}
4350
906e58ca
NC		 4351static bfd_boolean
4352arm_build_one_stub (struct bfd_hash_entry *gen_entry,
4353 void * in_arg)
4354{
7a89b94e 4355#define MAXRELOCS 3
906e58ca 4356 struct elf32_arm_stub_hash_entry *stub_entry;
4dfe6ac6 4357 struct elf32_arm_link_hash_table *globals;
906e58ca 4358 struct bfd_link_info *info;
906e58ca
NC		 4359 asection *stub_sec;
4360 bfd *stub_bfd;
906e58ca
NC		 4361 bfd_byte *loc;
4362 bfd_vma sym_value;
4363 int template_size;
4364 int size;
d3ce72d0 4365 const insn_sequence *template_sequence;
906e58ca 4366 int i;
48229727
JB		 4367 int stub_reloc_idx[MAXRELOCS] = {-1, -1};
4368 int stub_reloc_offset[MAXRELOCS] = {0, 0};
4369 int nrelocs = 0;
906e58ca
NC		 4370
4371 /* Massage our args to the form they really have. */
4372 stub_entry = (struct elf32_arm_stub_hash_entry *) gen_entry;
4373 info = (struct bfd_link_info *) in_arg;
4374
4375 globals = elf32_arm_hash_table (info);
4dfe6ac6
NC		 4376 if (globals == NULL)
4377 return FALSE;
906e58ca 4378
906e58ca
NC		 4379 stub_sec = stub_entry->stub_sec;
4380
4dfe6ac6 4381 if ((globals->fix_cortex_a8 < 0)
4563a860
JB		 4382 != (arm_stub_required_alignment (stub_entry->stub_type) == 2))
4383 /* We have to do less-strictly-aligned fixes last. */
eb7c4339 4384 return TRUE;
fe33d2fa 4385
906e58ca
NC		 4386 /* Make a note of the offset within the stubs for this entry. */
4387 stub_entry->stub_offset = stub_sec->size;
4388 loc = stub_sec->contents + stub_entry->stub_offset;
4389
4390 stub_bfd = stub_sec->owner;
4391
906e58ca
NC		 4392 /* This is the address of the stub destination. */
4393 sym_value = (stub_entry->target_value
4394 + stub_entry->target_section->output_offset
4395 + stub_entry->target_section->output_section->vma);
4396
d3ce72d0 4397 template_sequence = stub_entry->stub_template;
461a49ca 4398 template_size = stub_entry->stub_template_size;
906e58ca
NC		 4399
4400 size = 0;
461a49ca 4401 for (i = 0; i < template_size; i++)
906e58ca 4402 {
d3ce72d0 4403 switch (template_sequence[i].type)
461a49ca
DJ		 4404 {
4405 case THUMB16_TYPE:
48229727 4406 {
d3ce72d0
NC		 4407 bfd_vma data = (bfd_vma) template_sequence[i].data;
4408 if (template_sequence[i].reloc_addend != 0)
48229727 4409 {
99059e56
RM		 4410 /* We've borrowed the reloc_addend field to mean we should
4411 insert a condition code into this (Thumb-1 branch)
4412 instruction. See THUMB16_BCOND_INSN. */
4413 BFD_ASSERT ((data & 0xff00) == 0xd000);
4414 data |= ((stub_entry->orig_insn >> 22) & 0xf) << 8;
48229727 4415 }
fe33d2fa 4416 bfd_put_16 (stub_bfd, data, loc + size);
48229727
JB		 4417 size += 2;
4418 }
461a49ca 4419 break;
906e58ca 4420
48229727 4421 case THUMB32_TYPE:
fe33d2fa
CL		 4422 bfd_put_16 (stub_bfd,
4423 (template_sequence[i].data >> 16) & 0xffff,
4424 loc + size);
4425 bfd_put_16 (stub_bfd, template_sequence[i].data & 0xffff,
4426 loc + size + 2);
99059e56
RM		 4427 if (template_sequence[i].r_type != R_ARM_NONE)
4428 {
4429 stub_reloc_idx[nrelocs] = i;
4430 stub_reloc_offset[nrelocs++] = size;
4431 }
4432 size += 4;
4433 break;
48229727 4434
461a49ca 4435 case ARM_TYPE:
fe33d2fa
CL		 4436 bfd_put_32 (stub_bfd, template_sequence[i].data,
4437 loc + size);
461a49ca
DJ		 4438 /* Handle cases where the target is encoded within the
4439 instruction. */
d3ce72d0 4440 if (template_sequence[i].r_type == R_ARM_JUMP24)
461a49ca 4441 {
48229727
JB		 4442 stub_reloc_idx[nrelocs] = i;
4443 stub_reloc_offset[nrelocs++] = size;
461a49ca
DJ		 4444 }
4445 size += 4;
4446 break;
4447
4448 case DATA_TYPE:
d3ce72d0 4449 bfd_put_32 (stub_bfd, template_sequence[i].data, loc + size);
48229727
JB		 4450 stub_reloc_idx[nrelocs] = i;
4451 stub_reloc_offset[nrelocs++] = size;
461a49ca
DJ		 4452 size += 4;
4453 break;
4454
4455 default:
4456 BFD_FAIL ();
4457 return FALSE;
4458 }
906e58ca 4459 }
461a49ca 4460
906e58ca
NC		 4461 stub_sec->size += size;
4462
461a49ca
DJ		 4463 /* Stub size has already been computed in arm_size_one_stub. Check
4464 consistency. */
4465 BFD_ASSERT (size == stub_entry->stub_size);
4466
906e58ca 4467 /* Destination is Thumb. Force bit 0 to 1 to reflect this. */
35fc36a8 4468 if (stub_entry->branch_type == ST_BRANCH_TO_THUMB)
906e58ca
NC		 4469 sym_value |= 1;
4470
48229727
JB		 4471 /* Assume there is at least one and at most MAXRELOCS entries to relocate
4472 in each stub. */
4473 BFD_ASSERT (nrelocs != 0 && nrelocs <= MAXRELOCS);
c820be07 4474
48229727 4475 for (i = 0; i < nrelocs; i++)
8d9d9490
TP		 4476 {
4477 Elf_Internal_Rela rel;
4478 bfd_boolean unresolved_reloc;
4479 char *error_message;
4480 bfd_vma points_to =
4481 sym_value + template_sequence[stub_reloc_idx[i]].reloc_addend;
4482
4483 rel.r_offset = stub_entry->stub_offset + stub_reloc_offset[i];
4484 rel.r_info = ELF32_R_INFO (0,
4485 template_sequence[stub_reloc_idx[i]].r_type);
4486 rel.r_addend = 0;
4487
4488 if (stub_entry->stub_type == arm_stub_a8_veneer_b_cond && i == 0)
4489 /* The first relocation in the elf32_arm_stub_a8_veneer_b_cond[]
4490 template should refer back to the instruction after the original
4491 branch. We use target_section as Cortex-A8 erratum workaround stubs
4492 are only generated when both source and target are in the same
4493 section. */
4494 points_to = stub_entry->target_section->output_section->vma
4495 + stub_entry->target_section->output_offset
4496 + stub_entry->source_value;
4497
4498 elf32_arm_final_link_relocate (elf32_arm_howto_from_type
4499 (template_sequence[stub_reloc_idx[i]].r_type),
4500 stub_bfd, info->output_bfd, stub_sec, stub_sec->contents, &rel,
4501 points_to, info, stub_entry->target_section, "", STT_FUNC,
4502 stub_entry->branch_type,
4503 (struct elf_link_hash_entry *) stub_entry->h, &unresolved_reloc,
4504 &error_message);
4505 }
906e58ca
NC		 4506
4507 return TRUE;
48229727 4508#undef MAXRELOCS
906e58ca
NC		 4509}
4510
48229727
JB		 4511/* Calculate the template, template size and instruction size for a stub.
4512 Return value is the instruction size. */
906e58ca 4513
48229727
JB		 4514static unsigned int
4515find_stub_size_and_template (enum elf32_arm_stub_type stub_type,
4516 const insn_sequence **stub_template,
4517 int *stub_template_size)
906e58ca 4518{
d3ce72d0 4519 const insn_sequence *template_sequence = NULL;
48229727
JB		 4520 int template_size = 0, i;
4521 unsigned int size;
906e58ca 4522
d3ce72d0 4523 template_sequence = stub_definitions[stub_type].template_sequence;
2a229407
AM		 4524 if (stub_template)
4525 *stub_template = template_sequence;
4526
48229727 4527 template_size = stub_definitions[stub_type].template_size;
2a229407
AM		 4528 if (stub_template_size)
4529 *stub_template_size = template_size;
906e58ca
NC		 4530
4531 size = 0;
461a49ca
DJ		 4532 for (i = 0; i < template_size; i++)
4533 {
d3ce72d0 4534 switch (template_sequence[i].type)
461a49ca
DJ		 4535 {
4536 case THUMB16_TYPE:
4537 size += 2;
4538 break;
4539
4540 case ARM_TYPE:
48229727 4541 case THUMB32_TYPE:
461a49ca
DJ		 4542 case DATA_TYPE:
4543 size += 4;
4544 break;
4545
4546 default:
4547 BFD_FAIL ();
2a229407 4548 return 0;
461a49ca
DJ		 4549 }
4550 }
4551
48229727
JB		 4552 return size;
4553}
4554
4555/* As above, but don't actually build the stub. Just bump offset so
4556 we know stub section sizes. */
4557
4558static bfd_boolean
4559arm_size_one_stub (struct bfd_hash_entry *gen_entry,
c7e2358a 4560 void *in_arg ATTRIBUTE_UNUSED)
48229727
JB		 4561{
4562 struct elf32_arm_stub_hash_entry *stub_entry;
d3ce72d0 4563 const insn_sequence *template_sequence;
48229727
JB		 4564 int template_size, size;
4565
4566 /* Massage our args to the form they really have. */
4567 stub_entry = (struct elf32_arm_stub_hash_entry *) gen_entry;
48229727
JB		 4568
4569 BFD_ASSERT((stub_entry->stub_type > arm_stub_none)
4570 && stub_entry->stub_type < ARRAY_SIZE(stub_definitions));
4571
d3ce72d0 4572 size = find_stub_size_and_template (stub_entry->stub_type, &template_sequence,
48229727
JB		 4573 &template_size);
4574
461a49ca 4575 stub_entry->stub_size = size;
d3ce72d0 4576 stub_entry->stub_template = template_sequence;
461a49ca
DJ		 4577 stub_entry->stub_template_size = template_size;
4578
906e58ca
NC		 4579 size = (size + 7) & ~7;
4580 stub_entry->stub_sec->size += size;
461a49ca 4581
906e58ca
NC		 4582 return TRUE;
4583}
4584
4585/* External entry points for sizing and building linker stubs. */
4586
4587/* Set up various things so that we can make a list of input sections
4588 for each output section included in the link. Returns -1 on error,
4589 0 when no stubs will be needed, and 1 on success. */
4590
4591int
4592elf32_arm_setup_section_lists (bfd *output_bfd,
4593 struct bfd_link_info *info)
4594{
4595 bfd *input_bfd;
4596 unsigned int bfd_count;
7292b3ac 4597 unsigned int top_id, top_index;
906e58ca
NC		 4598 asection *section;
4599 asection **input_list, **list;
4600 bfd_size_type amt;
4601 struct elf32_arm_link_hash_table *htab = elf32_arm_hash_table (info);
4602
4dfe6ac6
NC		 4603 if (htab == NULL)
4604 return 0;
906e58ca
NC		 4605 if (! is_elf_hash_table (htab))
4606 return 0;
4607
4608 /* Count the number of input BFDs and find the top input section id. */
4609 for (input_bfd = info->input_bfds, bfd_count = 0, top_id = 0;
4610 input_bfd != NULL;
c72f2fb2 4611 input_bfd = input_bfd->link.next)
906e58ca
NC		 4612 {
4613 bfd_count += 1;
4614 for (section = input_bfd->sections;
4615 section != NULL;
4616 section = section->next)
4617 {
4618 if (top_id < section->id)
4619 top_id = section->id;
4620 }
4621 }
4622 htab->bfd_count = bfd_count;
4623
4624 amt = sizeof (struct map_stub) * (top_id + 1);
21d799b5 4625 htab->stub_group = (struct map_stub *) bfd_zmalloc (amt);
906e58ca
NC		 4626 if (htab->stub_group == NULL)
4627 return -1;
fe33d2fa 4628 htab->top_id = top_id;
906e58ca
NC		 4629
4630 /* We can't use output_bfd->section_count here to find the top output
4631 section index as some sections may have been removed, and
4632 _bfd_strip_section_from_output doesn't renumber the indices. */
4633 for (section = output_bfd->sections, top_index = 0;
4634 section != NULL;
4635 section = section->next)
4636 {
4637 if (top_index < section->index)
4638 top_index = section->index;
4639 }
4640
4641 htab->top_index = top_index;
4642 amt = sizeof (asection *) * (top_index + 1);
21d799b5 4643 input_list = (asection **) bfd_malloc (amt);
906e58ca
NC		 4644 htab->input_list = input_list;
4645 if (input_list == NULL)
4646 return -1;
4647
4648 /* For sections we aren't interested in, mark their entries with a
4649 value we can check later. */
4650 list = input_list + top_index;
4651 do
4652 *list = bfd_abs_section_ptr;
4653 while (list-- != input_list);
4654
4655 for (section = output_bfd->sections;
4656 section != NULL;
4657 section = section->next)
4658 {
4659 if ((section->flags & SEC_CODE) != 0)
4660 input_list[section->index] = NULL;
4661 }
4662
4663 return 1;
4664}
4665
4666/* The linker repeatedly calls this function for each input section,
4667 in the order that input sections are linked into output sections.
4668 Build lists of input sections to determine groupings between which
4669 we may insert linker stubs. */
4670
4671void
4672elf32_arm_next_input_section (struct bfd_link_info *info,
4673 asection *isec)
4674{
4675 struct elf32_arm_link_hash_table *htab = elf32_arm_hash_table (info);
4676
4dfe6ac6
NC		 4677 if (htab == NULL)
4678 return;
4679
906e58ca
NC		 4680 if (isec->output_section->index <= htab->top_index)
4681 {
4682 asection **list = htab->input_list + isec->output_section->index;
4683
a7470592 4684 if (*list != bfd_abs_section_ptr && (isec->flags & SEC_CODE) != 0)
906e58ca
NC		 4685 {
4686 /* Steal the link_sec pointer for our list. */
4687#define PREV_SEC(sec) (htab->stub_group[(sec)->id].link_sec)
4688 /* This happens to make the list in reverse order,
07d72278 4689 which we reverse later. */
906e58ca
NC		 4690 PREV_SEC (isec) = *list;
4691 *list = isec;
4692 }
4693 }
4694}
4695
4696/* See whether we can group stub sections together. Grouping stub
4697 sections may result in fewer stubs. More importantly, we need to
07d72278 4698 put all .init* and .fini* stubs at the end of the .init or
906e58ca
NC		 4699 .fini output sections respectively, because glibc splits the
4700 _init and _fini functions into multiple parts. Putting a stub in
4701 the middle of a function is not a good idea. */
4702
4703static void
4704group_sections (struct elf32_arm_link_hash_table *htab,
4705 bfd_size_type stub_group_size,
07d72278 4706 bfd_boolean stubs_always_after_branch)
906e58ca 4707{
07d72278 4708 asection **list = htab->input_list;
906e58ca
NC		 4709
4710 do
4711 {
4712 asection *tail = *list;
07d72278 4713 asection *head;
906e58ca
NC		 4714
4715 if (tail == bfd_abs_section_ptr)
4716 continue;
4717
07d72278
DJ		 4718 /* Reverse the list: we must avoid placing stubs at the
4719 beginning of the section because the beginning of the text
4720 section may be required for an interrupt vector in bare metal
4721 code. */
4722#define NEXT_SEC PREV_SEC
e780aef2
CL		 4723 head = NULL;
4724 while (tail != NULL)
99059e56
RM		 4725 {
4726 /* Pop from tail. */
4727 asection *item = tail;
4728 tail = PREV_SEC (item);
e780aef2 4729
99059e56
RM		 4730 /* Push on head. */
4731 NEXT_SEC (item) = head;
4732 head = item;
4733 }
07d72278
DJ		 4734
4735 while (head != NULL)
906e58ca
NC		 4736 {
4737 asection *curr;
07d72278 4738 asection *next;
e780aef2
CL		 4739 bfd_vma stub_group_start = head->output_offset;
4740 bfd_vma end_of_next;
906e58ca 4741
07d72278 4742 curr = head;
e780aef2 4743 while (NEXT_SEC (curr) != NULL)
8cd931b7 4744 {
e780aef2
CL		 4745 next = NEXT_SEC (curr);
4746 end_of_next = next->output_offset + next->size;
4747 if (end_of_next - stub_group_start >= stub_group_size)
4748 /* End of NEXT is too far from start, so stop. */
8cd931b7 4749 break;
e780aef2
CL		 4750 /* Add NEXT to the group. */
4751 curr = next;
8cd931b7 4752 }
906e58ca 4753
07d72278 4754 /* OK, the size from the start to the start of CURR is less
906e58ca 4755 than stub_group_size and thus can be handled by one stub
07d72278 4756 section. (Or the head section is itself larger than
906e58ca
NC		 4757 stub_group_size, in which case we may be toast.)
4758 We should really be keeping track of the total size of
4759 stubs added here, as stubs contribute to the final output
7fb9f789 4760 section size. */
906e58ca
NC		 4761 do
4762 {
07d72278 4763 next = NEXT_SEC (head);
906e58ca 4764 /* Set up this stub group. */
07d72278 4765 htab->stub_group[head->id].link_sec = curr;
906e58ca 4766 }
07d72278 4767 while (head != curr && (head = next) != NULL);
906e58ca
NC		 4768
4769 /* But wait, there's more! Input sections up to stub_group_size
07d72278
DJ		 4770 bytes after the stub section can be handled by it too. */
4771 if (!stubs_always_after_branch)
906e58ca 4772 {
e780aef2
CL		 4773 stub_group_start = curr->output_offset + curr->size;
4774
8cd931b7 4775 while (next != NULL)
906e58ca 4776 {
e780aef2
CL		 4777 end_of_next = next->output_offset + next->size;
4778 if (end_of_next - stub_group_start >= stub_group_size)
4779 /* End of NEXT is too far from stubs, so stop. */
8cd931b7 4780 break;
e780aef2 4781 /* Add NEXT to the stub group. */
07d72278
DJ		 4782 head = next;
4783 next = NEXT_SEC (head);
4784 htab->stub_group[head->id].link_sec = curr;
906e58ca
NC		 4785 }
4786 }
07d72278 4787 head = next;
906e58ca
NC		 4788 }
4789 }
07d72278 4790 while (list++ != htab->input_list + htab->top_index);
906e58ca
NC		 4791
4792 free (htab->input_list);
4793#undef PREV_SEC
07d72278 4794#undef NEXT_SEC
906e58ca
NC		 4795}
4796
48229727
JB		 4797/* Comparison function for sorting/searching relocations relating to Cortex-A8
4798 erratum fix. */
4799
4800static int
4801a8_reloc_compare (const void *a, const void *b)
4802{
21d799b5
NC		 4803 const struct a8_erratum_reloc *ra = (const struct a8_erratum_reloc *) a;
4804 const struct a8_erratum_reloc *rb = (const struct a8_erratum_reloc *) b;
48229727
JB		 4805
4806 if (ra->from < rb->from)
4807 return -1;
4808 else if (ra->from > rb->from)
4809 return 1;
4810 else
4811 return 0;
4812}
4813
4814static struct elf_link_hash_entry *find_thumb_glue (struct bfd_link_info *,
4815 const char *, char **);
4816
4817/* Helper function to scan code for sequences which might trigger the Cortex-A8
4818 branch/TLB erratum. Fill in the table described by A8_FIXES_P,
81694485 4819 NUM_A8_FIXES_P, A8_FIX_TABLE_SIZE_P. Returns true if an error occurs, false
48229727
JB		 4820 otherwise. */
4821
81694485
NC		 4822static bfd_boolean
4823cortex_a8_erratum_scan (bfd *input_bfd,
4824 struct bfd_link_info *info,
48229727
JB		 4825 struct a8_erratum_fix **a8_fixes_p,
4826 unsigned int *num_a8_fixes_p,
4827 unsigned int *a8_fix_table_size_p,
4828 struct a8_erratum_reloc *a8_relocs,
eb7c4339
NS		 4829 unsigned int num_a8_relocs,
4830 unsigned prev_num_a8_fixes,
4831 bfd_boolean *stub_changed_p)
48229727
JB		 4832{
4833 asection *section;
4834 struct elf32_arm_link_hash_table *htab = elf32_arm_hash_table (info);
4835 struct a8_erratum_fix *a8_fixes = *a8_fixes_p;
4836 unsigned int num_a8_fixes = *num_a8_fixes_p;
4837 unsigned int a8_fix_table_size = *a8_fix_table_size_p;
4838
4dfe6ac6
NC		 4839 if (htab == NULL)
4840 return FALSE;
4841
48229727
JB		 4842 for (section = input_bfd->sections;
4843 section != NULL;
4844 section = section->next)
4845 {
4846 bfd_byte *contents = NULL;
4847 struct _arm_elf_section_data *sec_data;
4848 unsigned int span;
4849 bfd_vma base_vma;
4850
4851 if (elf_section_type (section) != SHT_PROGBITS
99059e56
RM		 4852 || (elf_section_flags (section) & SHF_EXECINSTR) == 0
4853 || (section->flags & SEC_EXCLUDE) != 0
4854 || (section->sec_info_type == SEC_INFO_TYPE_JUST_SYMS)
4855 || (section->output_section == bfd_abs_section_ptr))
4856 continue;
48229727
JB		 4857
4858 base_vma = section->output_section->vma + section->output_offset;
4859
4860 if (elf_section_data (section)->this_hdr.contents != NULL)
99059e56 4861 contents = elf_section_data (section)->this_hdr.contents;
48229727 4862 else if (! bfd_malloc_and_get_section (input_bfd, section, &contents))
99059e56 4863 return TRUE;
48229727
JB		 4864
4865 sec_data = elf32_arm_section_data (section);
4866
4867 for (span = 0; span < sec_data->mapcount; span++)
99059e56
RM		 4868 {
4869 unsigned int span_start = sec_data->map[span].vma;
4870 unsigned int span_end = (span == sec_data->mapcount - 1)
4871 ? section->size : sec_data->map[span + 1].vma;
4872 unsigned int i;
4873 char span_type = sec_data->map[span].type;
4874 bfd_boolean last_was_32bit = FALSE, last_was_branch = FALSE;
4875
4876 if (span_type != 't')
4877 continue;
4878
4879 /* Span is entirely within a single 4KB region: skip scanning. */
4880 if (((base_vma + span_start) & ~0xfff)
48229727 4881 == ((base_vma + span_end) & ~0xfff))
99059e56
RM		 4882 continue;
4883
4884 /* Scan for 32-bit Thumb-2 branches which span two 4K regions, where:
4885
4886 * The opcode is BLX.W, BL.W, B.W, Bcc.W
4887 * The branch target is in the same 4KB region as the
4888 first half of the branch.
4889 * The instruction before the branch is a 32-bit
4890 length non-branch instruction. */
4891 for (i = span_start; i < span_end;)
4892 {
4893 unsigned int insn = bfd_getl16 (&contents[i]);
4894 bfd_boolean insn_32bit = FALSE, is_blx = FALSE, is_b = FALSE;
48229727
JB		 4895 bfd_boolean is_bl = FALSE, is_bcc = FALSE, is_32bit_branch;
4896
99059e56
RM		 4897 if ((insn & 0xe000) == 0xe000 && (insn & 0x1800) != 0x0000)
4898 insn_32bit = TRUE;
48229727
JB		 4899
4900 if (insn_32bit)
99059e56
RM		 4901 {
4902 /* Load the rest of the insn (in manual-friendly order). */
4903 insn = (insn << 16) | bfd_getl16 (&contents[i + 2]);
4904
4905 /* Encoding T4: B<c>.W. */
4906 is_b = (insn & 0xf800d000) == 0xf0009000;
4907 /* Encoding T1: BL<c>.W. */
4908 is_bl = (insn & 0xf800d000) == 0xf000d000;
4909 /* Encoding T2: BLX<c>.W. */
4910 is_blx = (insn & 0xf800d000) == 0xf000c000;
48229727
JB		 4911 /* Encoding T3: B<c>.W (not permitted in IT block). */
4912 is_bcc = (insn & 0xf800d000) == 0xf0008000
4913 && (insn & 0x07f00000) != 0x03800000;
4914 }
4915
4916 is_32bit_branch = is_b || is_bl || is_blx || is_bcc;
fe33d2fa 4917
99059e56 4918 if (((base_vma + i) & 0xfff) == 0xffe
81694485
NC		 4919 && insn_32bit
4920 && is_32bit_branch
4921 && last_was_32bit
4922 && ! last_was_branch)
99059e56
RM		 4923 {
4924 bfd_signed_vma offset = 0;
4925 bfd_boolean force_target_arm = FALSE;
48229727 4926 bfd_boolean force_target_thumb = FALSE;
99059e56
RM		 4927 bfd_vma target;
4928 enum elf32_arm_stub_type stub_type = arm_stub_none;
4929 struct a8_erratum_reloc key, *found;
4930 bfd_boolean use_plt = FALSE;
48229727 4931
99059e56
RM		 4932 key.from = base_vma + i;
4933 found = (struct a8_erratum_reloc *)
4934 bsearch (&key, a8_relocs, num_a8_relocs,
4935 sizeof (struct a8_erratum_reloc),
4936 &a8_reloc_compare);
48229727
JB		 4937
4938 if (found)
4939 {
4940 char *error_message = NULL;
4941 struct elf_link_hash_entry *entry;
4942
4943 /* We don't care about the error returned from this
99059e56 4944 function, only if there is glue or not. */
48229727
JB		 4945 entry = find_thumb_glue (info, found->sym_name,
4946 &error_message);
4947
4948 if (entry)
4949 found->non_a8_stub = TRUE;
4950
92750f34 4951 /* Keep a simpler condition, for the sake of clarity. */
362d30a1 4952 if (htab->root.splt != NULL && found->hash != NULL
92750f34
DJ		 4953 && found->hash->root.plt.offset != (bfd_vma) -1)
4954 use_plt = TRUE;
4955
4956 if (found->r_type == R_ARM_THM_CALL)
4957 {
35fc36a8
RS		 4958 if (found->branch_type == ST_BRANCH_TO_ARM
4959 || use_plt)
92750f34
DJ		 4960 force_target_arm = TRUE;
4961 else
4962 force_target_thumb = TRUE;
4963 }
48229727
JB		 4964 }
4965
99059e56 4966 /* Check if we have an offending branch instruction. */
48229727
JB		 4967
4968 if (found && found->non_a8_stub)
4969 /* We've already made a stub for this instruction, e.g.
4970 it's a long branch or a Thumb->ARM stub. Assume that
4971 stub will suffice to work around the A8 erratum (see
4972 setting of always_after_branch above). */
4973 ;
99059e56
RM		 4974 else if (is_bcc)
4975 {
4976 offset = (insn & 0x7ff) << 1;
4977 offset |= (insn & 0x3f0000) >> 4;
4978 offset |= (insn & 0x2000) ? 0x40000 : 0;
4979 offset |= (insn & 0x800) ? 0x80000 : 0;
4980 offset |= (insn & 0x4000000) ? 0x100000 : 0;
4981 if (offset & 0x100000)
4982 offset |= ~ ((bfd_signed_vma) 0xfffff);
4983 stub_type = arm_stub_a8_veneer_b_cond;
4984 }
4985 else if (is_b || is_bl || is_blx)
4986 {
4987 int s = (insn & 0x4000000) != 0;
4988 int j1 = (insn & 0x2000) != 0;
4989 int j2 = (insn & 0x800) != 0;
4990 int i1 = !(j1 ^ s);
4991 int i2 = !(j2 ^ s);
4992
4993 offset = (insn & 0x7ff) << 1;
4994 offset |= (insn & 0x3ff0000) >> 4;
4995 offset |= i2 << 22;
4996 offset |= i1 << 23;
4997 offset |= s << 24;
4998 if (offset & 0x1000000)
4999 offset |= ~ ((bfd_signed_vma) 0xffffff);
5000
5001 if (is_blx)
5002 offset &= ~ ((bfd_signed_vma) 3);
5003
5004 stub_type = is_blx ? arm_stub_a8_veneer_blx :
5005 is_bl ? arm_stub_a8_veneer_bl : arm_stub_a8_veneer_b;
5006 }
5007
5008 if (stub_type != arm_stub_none)
5009 {
5010 bfd_vma pc_for_insn = base_vma + i + 4;
48229727
JB		 5011
5012 /* The original instruction is a BL, but the target is
99059e56 5013 an ARM instruction. If we were not making a stub,
48229727
JB		 5014 the BL would have been converted to a BLX. Use the
5015 BLX stub instead in that case. */
5016 if (htab->use_blx && force_target_arm
5017 && stub_type == arm_stub_a8_veneer_bl)
5018 {
5019 stub_type = arm_stub_a8_veneer_blx;
5020 is_blx = TRUE;
5021 is_bl = FALSE;
5022 }
5023 /* Conversely, if the original instruction was
5024 BLX but the target is Thumb mode, use the BL
5025 stub. */
5026 else if (force_target_thumb
5027 && stub_type == arm_stub_a8_veneer_blx)
5028 {
5029 stub_type = arm_stub_a8_veneer_bl;
5030 is_blx = FALSE;
5031 is_bl = TRUE;
5032 }
5033
99059e56
RM		 5034 if (is_blx)
5035 pc_for_insn &= ~ ((bfd_vma) 3);
48229727 5036
99059e56
RM		 5037 /* If we found a relocation, use the proper destination,
5038 not the offset in the (unrelocated) instruction.
48229727
JB		 5039 Note this is always done if we switched the stub type
5040 above. */
99059e56
RM		 5041 if (found)
5042 offset =
81694485 5043 (bfd_signed_vma) (found->destination - pc_for_insn);
48229727 5044
99059e56
RM		 5045 /* If the stub will use a Thumb-mode branch to a
5046 PLT target, redirect it to the preceding Thumb
5047 entry point. */
5048 if (stub_type != arm_stub_a8_veneer_blx && use_plt)
5049 offset -= PLT_THUMB_STUB_SIZE;
7d24e6a6 5050
99059e56 5051 target = pc_for_insn + offset;
48229727 5052
99059e56
RM		 5053 /* The BLX stub is ARM-mode code. Adjust the offset to
5054 take the different PC value (+8 instead of +4) into
48229727 5055 account. */
99059e56
RM		 5056 if (stub_type == arm_stub_a8_veneer_blx)
5057 offset += 4;
5058
5059 if (((base_vma + i) & ~0xfff) == (target & ~0xfff))
5060 {
5061 char *stub_name = NULL;
5062
5063 if (num_a8_fixes == a8_fix_table_size)
5064 {
5065 a8_fix_table_size *= 2;
5066 a8_fixes = (struct a8_erratum_fix *)
5067 bfd_realloc (a8_fixes,
5068 sizeof (struct a8_erratum_fix)
5069 * a8_fix_table_size);
5070 }
48229727 5071
eb7c4339
NS		 5072 if (num_a8_fixes < prev_num_a8_fixes)
5073 {
5074 /* If we're doing a subsequent scan,
5075 check if we've found the same fix as
5076 before, and try and reuse the stub
5077 name. */
5078 stub_name = a8_fixes[num_a8_fixes].stub_name;
5079 if ((a8_fixes[num_a8_fixes].section != section)
5080 || (a8_fixes[num_a8_fixes].offset != i))
5081 {
5082 free (stub_name);
5083 stub_name = NULL;
5084 *stub_changed_p = TRUE;
5085 }
5086 }
5087
5088 if (!stub_name)
5089 {
21d799b5 5090 stub_name = (char *) bfd_malloc (8 + 1 + 8 + 1);
eb7c4339
NS		 5091 if (stub_name != NULL)
5092 sprintf (stub_name, "%x:%x", section->id, i);
5093 }
48229727 5094
99059e56
RM		 5095 a8_fixes[num_a8_fixes].input_bfd = input_bfd;
5096 a8_fixes[num_a8_fixes].section = section;
5097 a8_fixes[num_a8_fixes].offset = i;
8d9d9490
TP		 5098 a8_fixes[num_a8_fixes].target_offset =
5099 target - base_vma;
99059e56
RM		 5100 a8_fixes[num_a8_fixes].orig_insn = insn;
5101 a8_fixes[num_a8_fixes].stub_name = stub_name;
5102 a8_fixes[num_a8_fixes].stub_type = stub_type;
5103 a8_fixes[num_a8_fixes].branch_type =
35fc36a8 5104 is_blx ? ST_BRANCH_TO_ARM : ST_BRANCH_TO_THUMB;
48229727 5105
99059e56
RM		 5106 num_a8_fixes++;
5107 }
5108 }
5109 }
48229727 5110
99059e56
RM		 5111 i += insn_32bit ? 4 : 2;
5112 last_was_32bit = insn_32bit;
48229727 5113 last_was_branch = is_32bit_branch;
99059e56
RM		 5114 }
5115 }
48229727
JB		 5116
5117 if (elf_section_data (section)->this_hdr.contents == NULL)
99059e56 5118 free (contents);
48229727 5119 }
fe33d2fa 5120
48229727
JB		 5121 *a8_fixes_p = a8_fixes;
5122 *num_a8_fixes_p = num_a8_fixes;
5123 *a8_fix_table_size_p = a8_fix_table_size;
fe33d2fa 5124
81694485 5125 return FALSE;
48229727
JB		 5126}
5127
b715f643
TP		 5128/* Create or update a stub entry depending on whether the stub can already be
5129 found in HTAB. The stub is identified by:
5130 - its type STUB_TYPE
5131 - its source branch (note that several can share the same stub) whose
5132 section and relocation (if any) are given by SECTION and IRELA
5133 respectively
5134 - its target symbol whose input section, hash, name, value and branch type
5135 are given in SYM_SEC, HASH, SYM_NAME, SYM_VALUE and BRANCH_TYPE
5136 respectively
5137
5138 If found, the value of the stub's target symbol is updated from SYM_VALUE
5139 and *NEW_STUB is set to FALSE. Otherwise, *NEW_STUB is set to
5140 TRUE and the stub entry is initialized.
5141
5142 Returns whether the stub could be successfully created or updated, or FALSE
5143 if an error occured. */
5144
5145static bfd_boolean
5146elf32_arm_create_stub (struct elf32_arm_link_hash_table *htab,
5147 enum elf32_arm_stub_type stub_type, asection *section,
5148 Elf_Internal_Rela *irela, asection *sym_sec,
5149 struct elf32_arm_link_hash_entry *hash, char *sym_name,
5150 bfd_vma sym_value, enum arm_st_branch_type branch_type,
5151 bfd_boolean *new_stub)
5152{
5153 const asection *id_sec;
5154 char *stub_name;
5155 struct elf32_arm_stub_hash_entry *stub_entry;
5156 unsigned int r_type;
4f4faa4d 5157 bfd_boolean sym_claimed = arm_stub_sym_claimed (stub_type);
b715f643
TP		 5158
5159 BFD_ASSERT (stub_type != arm_stub_none);
5160 *new_stub = FALSE;
5161
4f4faa4d
TP		 5162 if (sym_claimed)
5163 stub_name = sym_name;
5164 else
5165 {
5166 BFD_ASSERT (irela);
5167 BFD_ASSERT (section);
b715f643 5168
4f4faa4d
TP		 5169 /* Support for grouping stub sections. */
5170 id_sec = htab->stub_group[section->id].link_sec;
b715f643 5171
4f4faa4d
TP		 5172 /* Get the name of this stub. */
5173 stub_name = elf32_arm_stub_name (id_sec, sym_sec, hash, irela,
5174 stub_type);
5175 if (!stub_name)
5176 return FALSE;
5177 }
b715f643
TP		 5178
5179 stub_entry = arm_stub_hash_lookup (&htab->stub_hash_table, stub_name, FALSE,
5180 FALSE);
5181 /* The proper stub has already been created, just update its value. */
5182 if (stub_entry != NULL)
5183 {
4f4faa4d
TP		 5184 if (!sym_claimed)
5185 free (stub_name);
b715f643
TP		 5186 stub_entry->target_value = sym_value;
5187 return TRUE;
5188 }
5189
5190 stub_entry = elf32_arm_add_stub (stub_name, section, htab);
5191 if (stub_entry == NULL)
5192 {
4f4faa4d
TP		 5193 if (!sym_claimed)
5194 free (stub_name);
b715f643
TP		 5195 return FALSE;
5196 }
5197
5198 stub_entry->target_value = sym_value;
5199 stub_entry->target_section = sym_sec;
5200 stub_entry->stub_type = stub_type;
5201 stub_entry->h = hash;
5202 stub_entry->branch_type = branch_type;
5203
4f4faa4d
TP		 5204 if (sym_claimed)
5205 stub_entry->output_name = sym_name;
5206 else
b715f643 5207 {
4f4faa4d
TP		 5208 if (sym_name == NULL)
5209 sym_name = "unnamed";
5210 stub_entry->output_name = (char *)
5211 bfd_alloc (htab->stub_bfd, sizeof (THUMB2ARM_GLUE_ENTRY_NAME)
5212 + strlen (sym_name));
5213 if (stub_entry->output_name == NULL)
5214 {
5215 free (stub_name);
5216 return FALSE;
5217 }
b715f643 5218
4f4faa4d
TP		 5219 /* For historical reasons, use the existing names for ARM-to-Thumb and
5220 Thumb-to-ARM stubs. */
5221 r_type = ELF32_R_TYPE (irela->r_info);
5222 if ((r_type == (unsigned int) R_ARM_THM_CALL
5223 || r_type == (unsigned int) R_ARM_THM_JUMP24
5224 || r_type == (unsigned int) R_ARM_THM_JUMP19)
5225 && branch_type == ST_BRANCH_TO_ARM)
5226 sprintf (stub_entry->output_name, THUMB2ARM_GLUE_ENTRY_NAME, sym_name);
5227 else if ((r_type == (unsigned int) R_ARM_CALL
5228 || r_type == (unsigned int) R_ARM_JUMP24)
5229 && branch_type == ST_BRANCH_TO_THUMB)
5230 sprintf (stub_entry->output_name, ARM2THUMB_GLUE_ENTRY_NAME, sym_name);
5231 else
5232 sprintf (stub_entry->output_name, STUB_ENTRY_NAME, sym_name);
5233 }
b715f643
TP		 5234
5235 *new_stub = TRUE;
5236 return TRUE;
5237}
5238
906e58ca
NC		 5239/* Determine and set the size of the stub section for a final link.
5240
5241 The basic idea here is to examine all the relocations looking for
5242 PC-relative calls to a target that is unreachable with a "bl"
5243 instruction. */
5244
5245bfd_boolean
5246elf32_arm_size_stubs (bfd *output_bfd,
5247 bfd *stub_bfd,
5248 struct bfd_link_info *info,
5249 bfd_signed_vma group_size,
7a89b94e 5250 asection * (*add_stub_section) (const char *, asection *,
6bde4c52 5251 asection *,
7a89b94e 5252 unsigned int),
906e58ca
NC		 5253 void (*layout_sections_again) (void))
5254{
5255 bfd_size_type stub_group_size;
07d72278 5256 bfd_boolean stubs_always_after_branch;
906e58ca 5257 struct elf32_arm_link_hash_table *htab = elf32_arm_hash_table (info);
48229727 5258 struct a8_erratum_fix *a8_fixes = NULL;
eb7c4339 5259 unsigned int num_a8_fixes = 0, a8_fix_table_size = 10;
48229727
JB		 5260 struct a8_erratum_reloc *a8_relocs = NULL;
5261 unsigned int num_a8_relocs = 0, a8_reloc_table_size = 10, i;
5262
4dfe6ac6
NC		 5263 if (htab == NULL)
5264 return FALSE;
5265
48229727
JB		 5266 if (htab->fix_cortex_a8)
5267 {
21d799b5 5268 a8_fixes = (struct a8_erratum_fix *)
99059e56 5269 bfd_zmalloc (sizeof (struct a8_erratum_fix) * a8_fix_table_size);
21d799b5 5270 a8_relocs = (struct a8_erratum_reloc *)
99059e56 5271 bfd_zmalloc (sizeof (struct a8_erratum_reloc) * a8_reloc_table_size);
48229727 5272 }
906e58ca
NC		 5273
5274 /* Propagate mach to stub bfd, because it may not have been
5275 finalized when we created stub_bfd. */
5276 bfd_set_arch_mach (stub_bfd, bfd_get_arch (output_bfd),
5277 bfd_get_mach (output_bfd));
5278
5279 /* Stash our params away. */
5280 htab->stub_bfd = stub_bfd;
5281 htab->add_stub_section = add_stub_section;
5282 htab->layout_sections_again = layout_sections_again;
07d72278 5283 stubs_always_after_branch = group_size < 0;
48229727
JB		 5284
5285 /* The Cortex-A8 erratum fix depends on stubs not being in the same 4K page
5286 as the first half of a 32-bit branch straddling two 4K pages. This is a
5287 crude way of enforcing that. */
5288 if (htab->fix_cortex_a8)
5289 stubs_always_after_branch = 1;
5290
906e58ca
NC		 5291 if (group_size < 0)
5292 stub_group_size = -group_size;
5293 else
5294 stub_group_size = group_size;
5295
5296 if (stub_group_size == 1)
5297 {
5298 /* Default values. */
5299 /* Thumb branch range is +-4MB has to be used as the default
5300 maximum size (a given section can contain both ARM and Thumb
5301 code, so the worst case has to be taken into account).
5302
5303 This value is 24K less than that, which allows for 2025
5304 12-byte stubs. If we exceed that, then we will fail to link.
5305 The user will have to relink with an explicit group size
5306 option. */
5307 stub_group_size = 4170000;
5308 }
5309
07d72278 5310 group_sections (htab, stub_group_size, stubs_always_after_branch);
906e58ca 5311
3ae046cc
NS		 5312 /* If we're applying the cortex A8 fix, we need to determine the
5313 program header size now, because we cannot change it later --
5314 that could alter section placements. Notice the A8 erratum fix
5315 ends up requiring the section addresses to remain unchanged
5316 modulo the page size. That's something we cannot represent
5317 inside BFD, and we don't want to force the section alignment to
5318 be the page size. */
5319 if (htab->fix_cortex_a8)
5320 (*htab->layout_sections_again) ();
5321
906e58ca
NC		 5322 while (1)
5323 {
5324 bfd *input_bfd;
5325 unsigned int bfd_indx;
5326 asection *stub_sec;
eb7c4339
NS		 5327 bfd_boolean stub_changed = FALSE;
5328 unsigned prev_num_a8_fixes = num_a8_fixes;
906e58ca 5329
48229727 5330 num_a8_fixes = 0;
906e58ca
NC		 5331 for (input_bfd = info->input_bfds, bfd_indx = 0;
5332 input_bfd != NULL;
c72f2fb2 5333 input_bfd = input_bfd->link.next, bfd_indx++)
906e58ca
NC		 5334 {
5335 Elf_Internal_Shdr *symtab_hdr;
5336 asection *section;
5337 Elf_Internal_Sym *local_syms = NULL;
5338
99059e56
RM		 5339 if (!is_arm_elf (input_bfd))
5340 continue;
adbcc655 5341
48229727
JB		 5342 num_a8_relocs = 0;
5343
906e58ca
NC		 5344 /* We'll need the symbol table in a second. */
5345 symtab_hdr = &elf_tdata (input_bfd)->symtab_hdr;
5346 if (symtab_hdr->sh_info == 0)
5347 continue;
5348
5349 /* Walk over each section attached to the input bfd. */
5350 for (section = input_bfd->sections;
5351 section != NULL;
5352 section = section->next)
5353 {
5354 Elf_Internal_Rela *internal_relocs, *irelaend, *irela;
5355
5356 /* If there aren't any relocs, then there's nothing more
5357 to do. */
5358 if ((section->flags & SEC_RELOC) == 0
5359 || section->reloc_count == 0
5360 || (section->flags & SEC_CODE) == 0)
5361 continue;
5362
5363 /* If this section is a link-once section that will be
5364 discarded, then don't create any stubs. */
5365 if (section->output_section == NULL
5366 || section->output_section->owner != output_bfd)
5367 continue;
5368
5369 /* Get the relocs. */
5370 internal_relocs
5371 = _bfd_elf_link_read_relocs (input_bfd, section, NULL,
5372 NULL, info->keep_memory);
5373 if (internal_relocs == NULL)
5374 goto error_ret_free_local;
5375
5376 /* Now examine each relocation. */
5377 irela = internal_relocs;
5378 irelaend = irela + section->reloc_count;
5379 for (; irela < irelaend; irela++)
5380 {
5381 unsigned int r_type, r_indx;
5382 enum elf32_arm_stub_type stub_type;
906e58ca
NC		 5383 asection *sym_sec;
5384 bfd_vma sym_value;
5385 bfd_vma destination;
5386 struct elf32_arm_link_hash_entry *hash;
7413f23f 5387 const char *sym_name;
34e77a92 5388 unsigned char st_type;
35fc36a8 5389 enum arm_st_branch_type branch_type;
48229727 5390 bfd_boolean created_stub = FALSE;
906e58ca
NC		 5391
5392 r_type = ELF32_R_TYPE (irela->r_info);
5393 r_indx = ELF32_R_SYM (irela->r_info);
5394
5395 if (r_type >= (unsigned int) R_ARM_max)
5396 {
5397 bfd_set_error (bfd_error_bad_value);
5398 error_ret_free_internal:
5399 if (elf_section_data (section)->relocs == NULL)
5400 free (internal_relocs);
15dd01b1
TP		 5401 /* Fall through. */
5402 error_ret_free_local:
5403 if (local_syms != NULL
5404 && (symtab_hdr->contents
5405 != (unsigned char *) local_syms))
5406 free (local_syms);
5407 return FALSE;
906e58ca 5408 }
b38cadfb 5409
0855e32b
NS		 5410 hash = NULL;
5411 if (r_indx >= symtab_hdr->sh_info)
5412 hash = elf32_arm_hash_entry
5413 (elf_sym_hashes (input_bfd)
5414 [r_indx - symtab_hdr->sh_info]);
b38cadfb 5415
0855e32b
NS		 5416 /* Only look for stubs on branch instructions, or
5417 non-relaxed TLSCALL */
906e58ca 5418 if ((r_type != (unsigned int) R_ARM_CALL)
155d87d7
CL		 5419 && (r_type != (unsigned int) R_ARM_THM_CALL)
5420 && (r_type != (unsigned int) R_ARM_JUMP24)
48229727
JB		 5421 && (r_type != (unsigned int) R_ARM_THM_JUMP19)
5422 && (r_type != (unsigned int) R_ARM_THM_XPC22)
155d87d7 5423 && (r_type != (unsigned int) R_ARM_THM_JUMP24)
0855e32b
NS		 5424 && (r_type != (unsigned int) R_ARM_PLT32)
5425 && !((r_type == (unsigned int) R_ARM_TLS_CALL
5426 || r_type == (unsigned int) R_ARM_THM_TLS_CALL)
5427 && r_type == elf32_arm_tls_transition
5428 (info, r_type, &hash->root)
5429 && ((hash ? hash->tls_type
5430 : (elf32_arm_local_got_tls_type
5431 (input_bfd)[r_indx]))
5432 & GOT_TLS_GDESC) != 0))
906e58ca
NC		 5433 continue;
5434
5435 /* Now determine the call target, its name, value,
5436 section. */
5437 sym_sec = NULL;
5438 sym_value = 0;
5439 destination = 0;
7413f23f 5440 sym_name = NULL;
b38cadfb 5441
0855e32b
NS		 5442 if (r_type == (unsigned int) R_ARM_TLS_CALL
5443 || r_type == (unsigned int) R_ARM_THM_TLS_CALL)
5444 {
5445 /* A non-relaxed TLS call. The target is the
5446 plt-resident trampoline and nothing to do
5447 with the symbol. */
5448 BFD_ASSERT (htab->tls_trampoline > 0);
5449 sym_sec = htab->root.splt;
5450 sym_value = htab->tls_trampoline;
5451 hash = 0;
34e77a92 5452 st_type = STT_FUNC;
35fc36a8 5453 branch_type = ST_BRANCH_TO_ARM;
0855e32b
NS		 5454 }
5455 else if (!hash)
906e58ca
NC		 5456 {
5457 /* It's a local symbol. */
5458 Elf_Internal_Sym *sym;
906e58ca
NC		 5459
5460 if (local_syms == NULL)
5461 {
5462 local_syms
5463 = (Elf_Internal_Sym *) symtab_hdr->contents;
5464 if (local_syms == NULL)
5465 local_syms
5466 = bfd_elf_get_elf_syms (input_bfd, symtab_hdr,
5467 symtab_hdr->sh_info, 0,
5468 NULL, NULL, NULL);
5469 if (local_syms == NULL)
5470 goto error_ret_free_internal;
5471 }
5472
5473 sym = local_syms + r_indx;
f6d250ce
TS		 5474 if (sym->st_shndx == SHN_UNDEF)
5475 sym_sec = bfd_und_section_ptr;
5476 else if (sym->st_shndx == SHN_ABS)
5477 sym_sec = bfd_abs_section_ptr;
5478 else if (sym->st_shndx == SHN_COMMON)
5479 sym_sec = bfd_com_section_ptr;
5480 else
5481 sym_sec =
5482 bfd_section_from_elf_index (input_bfd, sym->st_shndx);
5483
ffcb4889
NS		 5484 if (!sym_sec)
5485 /* This is an undefined symbol. It can never
6a631e86 5486 be resolved. */
ffcb4889 5487 continue;
fe33d2fa 5488
906e58ca
NC		 5489 if (ELF_ST_TYPE (sym->st_info) != STT_SECTION)
5490 sym_value = sym->st_value;
5491 destination = (sym_value + irela->r_addend
5492 + sym_sec->output_offset
5493 + sym_sec->output_section->vma);
34e77a92 5494 st_type = ELF_ST_TYPE (sym->st_info);
39d911fc
TP		 5495 branch_type =
5496 ARM_GET_SYM_BRANCH_TYPE (sym->st_target_internal);
7413f23f
DJ		 5497 sym_name
5498 = bfd_elf_string_from_elf_section (input_bfd,
5499 symtab_hdr->sh_link,
5500 sym->st_name);
906e58ca
NC		 5501 }
5502 else
5503 {
5504 /* It's an external symbol. */
906e58ca
NC		 5505 while (hash->root.root.type == bfd_link_hash_indirect
5506 || hash->root.root.type == bfd_link_hash_warning)
5507 hash = ((struct elf32_arm_link_hash_entry *)
5508 hash->root.root.u.i.link);
5509
5510 if (hash->root.root.type == bfd_link_hash_defined
5511 || hash->root.root.type == bfd_link_hash_defweak)
5512 {
5513 sym_sec = hash->root.root.u.def.section;
5514 sym_value = hash->root.root.u.def.value;
022f8312
CL		 5515
5516 struct elf32_arm_link_hash_table *globals =
5517 elf32_arm_hash_table (info);
5518
5519 /* For a destination in a shared library,
5520 use the PLT stub as target address to
5521 decide whether a branch stub is
5522 needed. */
4dfe6ac6 5523 if (globals != NULL
362d30a1 5524 && globals->root.splt != NULL
4dfe6ac6 5525 && hash != NULL
022f8312
CL		 5526 && hash->root.plt.offset != (bfd_vma) -1)
5527 {
362d30a1 5528 sym_sec = globals->root.splt;
022f8312
CL		 5529 sym_value = hash->root.plt.offset;
5530 if (sym_sec->output_section != NULL)
5531 destination = (sym_value
5532 + sym_sec->output_offset
5533 + sym_sec->output_section->vma);
5534 }
5535 else if (sym_sec->output_section != NULL)
906e58ca
NC		 5536 destination = (sym_value + irela->r_addend
5537 + sym_sec->output_offset
5538 + sym_sec->output_section->vma);
5539 }
69c5861e
CL		 5540 else if ((hash->root.root.type == bfd_link_hash_undefined)
5541 || (hash->root.root.type == bfd_link_hash_undefweak))
5542 {
5543 /* For a shared library, use the PLT stub as
5544 target address to decide whether a long
5545 branch stub is needed.
5546 For absolute code, they cannot be handled. */
5547 struct elf32_arm_link_hash_table *globals =
5548 elf32_arm_hash_table (info);
5549
4dfe6ac6 5550 if (globals != NULL
362d30a1 5551 && globals->root.splt != NULL
4dfe6ac6 5552 && hash != NULL
69c5861e
CL		 5553 && hash->root.plt.offset != (bfd_vma) -1)
5554 {
362d30a1 5555 sym_sec = globals->root.splt;
69c5861e
CL		 5556 sym_value = hash->root.plt.offset;
5557 if (sym_sec->output_section != NULL)
5558 destination = (sym_value
5559 + sym_sec->output_offset
5560 + sym_sec->output_section->vma);
5561 }
5562 else
5563 continue;
5564 }
906e58ca
NC		 5565 else
5566 {
5567 bfd_set_error (bfd_error_bad_value);
5568 goto error_ret_free_internal;
5569 }
34e77a92 5570 st_type = hash->root.type;
39d911fc
TP		 5571 branch_type =
5572 ARM_GET_SYM_BRANCH_TYPE (hash->root.target_internal);
7413f23f 5573 sym_name = hash->root.root.root.string;
906e58ca
NC		 5574 }
5575
48229727 5576 do
7413f23f 5577 {
b715f643
TP		 5578 bfd_boolean new_stub;
5579
48229727
JB		 5580 /* Determine what (if any) linker stub is needed. */
5581 stub_type = arm_type_of_stub (info, section, irela,
34e77a92
RS		 5582 st_type, &branch_type,
5583 hash, destination, sym_sec,
48229727
JB		 5584 input_bfd, sym_name);
5585 if (stub_type == arm_stub_none)
5586 break;
5587
48229727
JB		 5588 /* We've either created a stub for this reloc already,
5589 or we are about to. */
b715f643
TP		 5590 created_stub =
5591 elf32_arm_create_stub (htab, stub_type, section, irela,
5592 sym_sec, hash,
5593 (char *) sym_name, sym_value,
5594 branch_type, &new_stub);
7413f23f 5595
b715f643
TP		 5596 if (!created_stub)
5597 goto error_ret_free_internal;
5598 else if (!new_stub)
5599 break;
99059e56 5600 else
b715f643 5601 stub_changed = TRUE;
99059e56
RM		 5602 }
5603 while (0);
5604
5605 /* Look for relocations which might trigger Cortex-A8
5606 erratum. */
5607 if (htab->fix_cortex_a8
5608 && (r_type == (unsigned int) R_ARM_THM_JUMP24
5609 || r_type == (unsigned int) R_ARM_THM_JUMP19
5610 || r_type == (unsigned int) R_ARM_THM_CALL
5611 || r_type == (unsigned int) R_ARM_THM_XPC22))
5612 {
5613 bfd_vma from = section->output_section->vma
5614 + section->output_offset
5615 + irela->r_offset;
5616
5617 if ((from & 0xfff) == 0xffe)
5618 {
5619 /* Found a candidate. Note we haven't checked the
5620 destination is within 4K here: if we do so (and
5621 don't create an entry in a8_relocs) we can't tell
5622 that a branch should have been relocated when
5623 scanning later. */
5624 if (num_a8_relocs == a8_reloc_table_size)
5625 {
5626 a8_reloc_table_size *= 2;
5627 a8_relocs = (struct a8_erratum_reloc *)
5628 bfd_realloc (a8_relocs,
5629 sizeof (struct a8_erratum_reloc)
5630 * a8_reloc_table_size);
5631 }
5632
5633 a8_relocs[num_a8_relocs].from = from;
5634 a8_relocs[num_a8_relocs].destination = destination;
5635 a8_relocs[num_a8_relocs].r_type = r_type;
5636 a8_relocs[num_a8_relocs].branch_type = branch_type;
5637 a8_relocs[num_a8_relocs].sym_name = sym_name;
5638 a8_relocs[num_a8_relocs].non_a8_stub = created_stub;
5639 a8_relocs[num_a8_relocs].hash = hash;
5640
5641 num_a8_relocs++;
5642 }
5643 }
906e58ca
NC		 5644 }
5645
99059e56
RM		 5646 /* We're done with the internal relocs, free them. */
5647 if (elf_section_data (section)->relocs == NULL)
5648 free (internal_relocs);
5649 }
48229727 5650
99059e56 5651 if (htab->fix_cortex_a8)
48229727 5652 {
99059e56
RM		 5653 /* Sort relocs which might apply to Cortex-A8 erratum. */
5654 qsort (a8_relocs, num_a8_relocs,
eb7c4339 5655 sizeof (struct a8_erratum_reloc),
99059e56 5656 &a8_reloc_compare);
48229727 5657
99059e56
RM		 5658 /* Scan for branches which might trigger Cortex-A8 erratum. */
5659 if (cortex_a8_erratum_scan (input_bfd, info, &a8_fixes,
48229727 5660 &num_a8_fixes, &a8_fix_table_size,
eb7c4339
NS		 5661 a8_relocs, num_a8_relocs,
5662 prev_num_a8_fixes, &stub_changed)
5663 != 0)
48229727 5664 goto error_ret_free_local;
5e681ec4 5665 }
5e681ec4
PB		 5666 }
5667
eb7c4339 5668 if (prev_num_a8_fixes != num_a8_fixes)
99059e56 5669 stub_changed = TRUE;
48229727 5670
906e58ca
NC		 5671 if (!stub_changed)
5672 break;
5e681ec4 5673
906e58ca
NC		 5674 /* OK, we've added some stubs. Find out the new size of the
5675 stub sections. */
5676 for (stub_sec = htab->stub_bfd->sections;
5677 stub_sec != NULL;
5678 stub_sec = stub_sec->next)
3e6b1042
DJ		 5679 {
5680 /* Ignore non-stub sections. */
5681 if (!strstr (stub_sec->name, STUB_SUFFIX))
5682 continue;
5683
5684 stub_sec->size = 0;
5685 }
b34b2d70 5686
906e58ca
NC		 5687 bfd_hash_traverse (&htab->stub_hash_table, arm_size_one_stub, htab);
5688
48229727
JB		 5689 /* Add Cortex-A8 erratum veneers to stub section sizes too. */
5690 if (htab->fix_cortex_a8)
99059e56
RM		 5691 for (i = 0; i < num_a8_fixes; i++)
5692 {
48229727
JB		 5693 stub_sec = elf32_arm_create_or_find_stub_sec (NULL,
5694 a8_fixes[i].section, htab);
5695
5696 if (stub_sec == NULL)
5697 goto error_ret_free_local;
5698
99059e56
RM		 5699 stub_sec->size
5700 += find_stub_size_and_template (a8_fixes[i].stub_type, NULL,
5701 NULL);
5702 }
48229727
JB		 5703
5704
906e58ca
NC		 5705 /* Ask the linker to do its stuff. */
5706 (*htab->layout_sections_again) ();
ba93b8ac
DJ		 5707 }
5708
48229727
JB		 5709 /* Add stubs for Cortex-A8 erratum fixes now. */
5710 if (htab->fix_cortex_a8)
5711 {
5712 for (i = 0; i < num_a8_fixes; i++)
99059e56
RM		 5713 {
5714 struct elf32_arm_stub_hash_entry *stub_entry;
5715 char *stub_name = a8_fixes[i].stub_name;
5716 asection *section = a8_fixes[i].section;
5717 unsigned int section_id = a8_fixes[i].section->id;
5718 asection *link_sec = htab->stub_group[section_id].link_sec;
5719 asection *stub_sec = htab->stub_group[section_id].stub_sec;
5720 const insn_sequence *template_sequence;
5721 int template_size, size = 0;
5722
5723 stub_entry = arm_stub_hash_lookup (&htab->stub_hash_table, stub_name,
5724 TRUE, FALSE);
5725 if (stub_entry == NULL)
5726 {
5727 (*_bfd_error_handler) (_("%s: cannot create stub entry %s"),
5728 section->owner,
5729 stub_name);
5730 return FALSE;
5731 }
5732
5733 stub_entry->stub_sec = stub_sec;
5734 stub_entry->stub_offset = 0;
5735 stub_entry->id_sec = link_sec;
5736 stub_entry->stub_type = a8_fixes[i].stub_type;
8d9d9490 5737 stub_entry->source_value = a8_fixes[i].offset;
99059e56 5738 stub_entry->target_section = a8_fixes[i].section;
8d9d9490 5739 stub_entry->target_value = a8_fixes[i].target_offset;
99059e56 5740 stub_entry->orig_insn = a8_fixes[i].orig_insn;
35fc36a8 5741 stub_entry->branch_type = a8_fixes[i].branch_type;
48229727 5742
99059e56
RM		 5743 size = find_stub_size_and_template (a8_fixes[i].stub_type,
5744 &template_sequence,
5745 &template_size);
48229727 5746
99059e56
RM		 5747 stub_entry->stub_size = size;
5748 stub_entry->stub_template = template_sequence;
5749 stub_entry->stub_template_size = template_size;
5750 }
48229727
JB		 5751
5752 /* Stash the Cortex-A8 erratum fix array for use later in
99059e56 5753 elf32_arm_write_section(). */
48229727
JB		 5754 htab->a8_erratum_fixes = a8_fixes;
5755 htab->num_a8_erratum_fixes = num_a8_fixes;
5756 }
5757 else
5758 {
5759 htab->a8_erratum_fixes = NULL;
5760 htab->num_a8_erratum_fixes = 0;
5761 }
906e58ca 5762 return TRUE;
5e681ec4
PB		 5763}
5764
906e58ca
NC		 5765/* Build all the stubs associated with the current output file. The
5766 stubs are kept in a hash table attached to the main linker hash
5767 table. We also set up the .plt entries for statically linked PIC
5768 functions here. This function is called via arm_elf_finish in the
5769 linker. */
252b5132 5770
906e58ca
NC		 5771bfd_boolean
5772elf32_arm_build_stubs (struct bfd_link_info *info)
252b5132 5773{
906e58ca
NC		 5774 asection *stub_sec;
5775 struct bfd_hash_table *table;
5776 struct elf32_arm_link_hash_table *htab;
252b5132 5777
906e58ca 5778 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 5779 if (htab == NULL)
5780 return FALSE;
252b5132 5781
906e58ca
NC		 5782 for (stub_sec = htab->stub_bfd->sections;
5783 stub_sec != NULL;
5784 stub_sec = stub_sec->next)
252b5132 5785 {
906e58ca
NC		 5786 bfd_size_type size;
5787
8029a119 5788 /* Ignore non-stub sections. */
906e58ca
NC		 5789 if (!strstr (stub_sec->name, STUB_SUFFIX))
5790 continue;
5791
5792 /* Allocate memory to hold the linker stubs. */
5793 size = stub_sec->size;
21d799b5 5794 stub_sec->contents = (unsigned char *) bfd_zalloc (htab->stub_bfd, size);
906e58ca
NC		 5795 if (stub_sec->contents == NULL && size != 0)
5796 return FALSE;
5797 stub_sec->size = 0;
252b5132
RH		 5798 }
5799
906e58ca
NC		 5800 /* Build the stubs as directed by the stub hash table. */
5801 table = &htab->stub_hash_table;
5802 bfd_hash_traverse (table, arm_build_one_stub, info);
eb7c4339
NS		 5803 if (htab->fix_cortex_a8)
5804 {
5805 /* Place the cortex a8 stubs last. */
5806 htab->fix_cortex_a8 = -1;
5807 bfd_hash_traverse (table, arm_build_one_stub, info);
5808 }
252b5132 5809
906e58ca 5810 return TRUE;
252b5132
RH		 5811}
5812
9b485d32
NC		 5813/* Locate the Thumb encoded calling stub for NAME. */
5814
252b5132 5815static struct elf_link_hash_entry *
57e8b36a
NC		 5816find_thumb_glue (struct bfd_link_info *link_info,
5817 const char *name,
f2a9dd69 5818 char **error_message)
252b5132
RH		 5819{
5820 char *tmp_name;
5821 struct elf_link_hash_entry *hash;
5822 struct elf32_arm_link_hash_table *hash_table;
5823
5824 /* We need a pointer to the armelf specific hash table. */
5825 hash_table = elf32_arm_hash_table (link_info);
4dfe6ac6
NC		 5826 if (hash_table == NULL)
5827 return NULL;
252b5132 5828
21d799b5 5829 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen (name)
99059e56 5830 + strlen (THUMB2ARM_GLUE_ENTRY_NAME) + 1);
252b5132
RH		 5831
5832 BFD_ASSERT (tmp_name);
5833
5834 sprintf (tmp_name, THUMB2ARM_GLUE_ENTRY_NAME, name);
5835
5836 hash = elf_link_hash_lookup
b34976b6 5837 (&(hash_table)->root, tmp_name, FALSE, FALSE, TRUE);
252b5132 5838
b1657152
AM		 5839 if (hash == NULL
5840 && asprintf (error_message, _("unable to find THUMB glue '%s' for '%s'"),
5841 tmp_name, name) == -1)
5842 *error_message = (char *) bfd_errmsg (bfd_error_system_call);
252b5132
RH		 5843
5844 free (tmp_name);
5845
5846 return hash;
5847}
5848
9b485d32
NC		 5849/* Locate the ARM encoded calling stub for NAME. */
5850
252b5132 5851static struct elf_link_hash_entry *
57e8b36a
NC		 5852find_arm_glue (struct bfd_link_info *link_info,
5853 const char *name,
f2a9dd69 5854 char **error_message)
252b5132
RH		 5855{
5856 char *tmp_name;
5857 struct elf_link_hash_entry *myh;
5858 struct elf32_arm_link_hash_table *hash_table;
5859
5860 /* We need a pointer to the elfarm specific hash table. */
5861 hash_table = elf32_arm_hash_table (link_info);
4dfe6ac6
NC		 5862 if (hash_table == NULL)
5863 return NULL;
252b5132 5864
21d799b5 5865 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen (name)
99059e56 5866 + strlen (ARM2THUMB_GLUE_ENTRY_NAME) + 1);
252b5132
RH		 5867
5868 BFD_ASSERT (tmp_name);
5869
5870 sprintf (tmp_name, ARM2THUMB_GLUE_ENTRY_NAME, name);
5871
5872 myh = elf_link_hash_lookup
b34976b6 5873 (&(hash_table)->root, tmp_name, FALSE, FALSE, TRUE);
252b5132 5874
b1657152
AM		 5875 if (myh == NULL
5876 && asprintf (error_message, _("unable to find ARM glue '%s' for '%s'"),
5877 tmp_name, name) == -1)
5878 *error_message = (char *) bfd_errmsg (bfd_error_system_call);
252b5132
RH		 5879
5880 free (tmp_name);
5881
5882 return myh;
5883}
5884
8f6277f5 5885/* ARM->Thumb glue (static images):
252b5132
RH		 5886
5887 .arm
5888 __func_from_arm:
5889 ldr r12, __func_addr
5890 bx r12
5891 __func_addr:
906e58ca 5892 .word func @ behave as if you saw a ARM_32 reloc.
252b5132 5893
26079076
PB		 5894 (v5t static images)
5895 .arm
5896 __func_from_arm:
5897 ldr pc, __func_addr
5898 __func_addr:
906e58ca 5899 .word func @ behave as if you saw a ARM_32 reloc.
26079076 5900
8f6277f5
PB		 5901 (relocatable images)
5902 .arm
5903 __func_from_arm:
5904 ldr r12, __func_offset
5905 add r12, r12, pc
5906 bx r12
5907 __func_offset:
8029a119 5908 .word func - . */
8f6277f5
PB		 5909
5910#define ARM2THUMB_STATIC_GLUE_SIZE 12
252b5132
RH		 5911static const insn32 a2t1_ldr_insn = 0xe59fc000;
5912static const insn32 a2t2_bx_r12_insn = 0xe12fff1c;
5913static const insn32 a2t3_func_addr_insn = 0x00000001;
5914
26079076
PB		 5915#define ARM2THUMB_V5_STATIC_GLUE_SIZE 8
5916static const insn32 a2t1v5_ldr_insn = 0xe51ff004;
5917static const insn32 a2t2v5_func_addr_insn = 0x00000001;
5918
8f6277f5
PB		 5919#define ARM2THUMB_PIC_GLUE_SIZE 16
5920static const insn32 a2t1p_ldr_insn = 0xe59fc004;
5921static const insn32 a2t2p_add_pc_insn = 0xe08cc00f;
5922static const insn32 a2t3p_bx_r12_insn = 0xe12fff1c;
5923
9b485d32 5924/* Thumb->ARM: Thumb->(non-interworking aware) ARM
252b5132 5925
8029a119
NC		 5926 .thumb .thumb
5927 .align 2 .align 2
5928 __func_from_thumb: __func_from_thumb:
5929 bx pc push {r6, lr}
5930 nop ldr r6, __func_addr
5931 .arm mov lr, pc
5932 b func bx r6
99059e56
RM		 5933 .arm
5934 ;; back_to_thumb
5935 ldmia r13! {r6, lr}
5936 bx lr
5937 __func_addr:
5938 .word func */
252b5132
RH		 5939
5940#define THUMB2ARM_GLUE_SIZE 8
5941static const insn16 t2a1_bx_pc_insn = 0x4778;
5942static const insn16 t2a2_noop_insn = 0x46c0;
5943static const insn32 t2a3_b_insn = 0xea000000;
5944
c7b8f16e 5945#define VFP11_ERRATUM_VENEER_SIZE 8
a504d23a
LA		 5946#define STM32L4XX_ERRATUM_LDM_VENEER_SIZE 16
5947#define STM32L4XX_ERRATUM_VLDM_VENEER_SIZE 24
c7b8f16e 5948
845b51d6
PB		 5949#define ARM_BX_VENEER_SIZE 12
5950static const insn32 armbx1_tst_insn = 0xe3100001;
5951static const insn32 armbx2_moveq_insn = 0x01a0f000;
5952static const insn32 armbx3_bx_insn = 0xe12fff10;
5953
7e392df6 5954#ifndef ELFARM_NABI_C_INCLUDED
8029a119
NC		 5955static void
5956arm_allocate_glue_section_space (bfd * abfd, bfd_size_type size, const char * name)
252b5132
RH		 5957{
5958 asection * s;
8029a119 5959 bfd_byte * contents;
252b5132 5960
8029a119 5961 if (size == 0)
3e6b1042
DJ		 5962 {
5963 /* Do not include empty glue sections in the output. */
5964 if (abfd != NULL)
5965 {
3d4d4302 5966 s = bfd_get_linker_section (abfd, name);
3e6b1042
DJ		 5967 if (s != NULL)
5968 s->flags |= SEC_EXCLUDE;
5969 }
5970 return;
5971 }
252b5132 5972
8029a119 5973 BFD_ASSERT (abfd != NULL);
252b5132 5974
3d4d4302 5975 s = bfd_get_linker_section (abfd, name);
8029a119 5976 BFD_ASSERT (s != NULL);
252b5132 5977
21d799b5 5978 contents = (bfd_byte *) bfd_alloc (abfd, size);
252b5132 5979
8029a119
NC		 5980 BFD_ASSERT (s->size == size);
5981 s->contents = contents;
5982}
906e58ca 5983
8029a119
NC		 5984bfd_boolean
5985bfd_elf32_arm_allocate_interworking_sections (struct bfd_link_info * info)
5986{
5987 struct elf32_arm_link_hash_table * globals;
906e58ca 5988
8029a119
NC		 5989 globals = elf32_arm_hash_table (info);
5990 BFD_ASSERT (globals != NULL);
906e58ca 5991
8029a119
NC		 5992 arm_allocate_glue_section_space (globals->bfd_of_glue_owner,
5993 globals->arm_glue_size,
5994 ARM2THUMB_GLUE_SECTION_NAME);
906e58ca 5995
8029a119
NC		 5996 arm_allocate_glue_section_space (globals->bfd_of_glue_owner,
5997 globals->thumb_glue_size,
5998 THUMB2ARM_GLUE_SECTION_NAME);
252b5132 5999
8029a119
NC		 6000 arm_allocate_glue_section_space (globals->bfd_of_glue_owner,
6001 globals->vfp11_erratum_glue_size,
6002 VFP11_ERRATUM_VENEER_SECTION_NAME);
845b51d6 6003
a504d23a
LA		 6004 arm_allocate_glue_section_space (globals->bfd_of_glue_owner,
6005 globals->stm32l4xx_erratum_glue_size,
6006 STM32L4XX_ERRATUM_VENEER_SECTION_NAME);
6007
8029a119
NC		 6008 arm_allocate_glue_section_space (globals->bfd_of_glue_owner,
6009 globals->bx_glue_size,
845b51d6
PB		 6010 ARM_BX_GLUE_SECTION_NAME);
6011
b34976b6 6012 return TRUE;
252b5132
RH		 6013}
6014
a4fd1a8e 6015/* Allocate space and symbols for calling a Thumb function from Arm mode.
906e58ca
NC		 6016 returns the symbol identifying the stub. */
6017
a4fd1a8e 6018static struct elf_link_hash_entry *
57e8b36a
NC		 6019record_arm_to_thumb_glue (struct bfd_link_info * link_info,
6020 struct elf_link_hash_entry * h)
252b5132
RH		 6021{
6022 const char * name = h->root.root.string;
63b0f745 6023 asection * s;
252b5132
RH		 6024 char * tmp_name;
6025 struct elf_link_hash_entry * myh;
14a793b2 6026 struct bfd_link_hash_entry * bh;
252b5132 6027 struct elf32_arm_link_hash_table * globals;
dc810e39 6028 bfd_vma val;
2f475487 6029 bfd_size_type size;
252b5132
RH		 6030
6031 globals = elf32_arm_hash_table (link_info);
252b5132
RH		 6032 BFD_ASSERT (globals != NULL);
6033 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
6034
3d4d4302 6035 s = bfd_get_linker_section
252b5132
RH		 6036 (globals->bfd_of_glue_owner, ARM2THUMB_GLUE_SECTION_NAME);
6037
252b5132
RH		 6038 BFD_ASSERT (s != NULL);
6039
21d799b5 6040 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen (name)
99059e56 6041 + strlen (ARM2THUMB_GLUE_ENTRY_NAME) + 1);
252b5132
RH		 6042
6043 BFD_ASSERT (tmp_name);
6044
6045 sprintf (tmp_name, ARM2THUMB_GLUE_ENTRY_NAME, name);
6046
6047 myh = elf_link_hash_lookup
b34976b6 6048 (&(globals)->root, tmp_name, FALSE, FALSE, TRUE);
252b5132
RH		 6049
6050 if (myh != NULL)
6051 {
9b485d32 6052 /* We've already seen this guy. */
252b5132 6053 free (tmp_name);
a4fd1a8e 6054 return myh;
252b5132
RH		 6055 }
6056
57e8b36a
NC		 6057 /* The only trick here is using hash_table->arm_glue_size as the value.
6058 Even though the section isn't allocated yet, this is where we will be
3dccd7b7
DJ		 6059 putting it. The +1 on the value marks that the stub has not been
6060 output yet - not that it is a Thumb function. */
14a793b2 6061 bh = NULL;
dc810e39
AM		 6062 val = globals->arm_glue_size + 1;
6063 _bfd_generic_link_add_one_symbol (link_info, globals->bfd_of_glue_owner,
6064 tmp_name, BSF_GLOBAL, s, val,
b34976b6 6065 NULL, TRUE, FALSE, &bh);
252b5132 6066
b7693d02
DJ		 6067 myh = (struct elf_link_hash_entry *) bh;
6068 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
6069 myh->forced_local = 1;
6070
252b5132
RH		 6071 free (tmp_name);
6072
0e1862bb
L		 6073 if (bfd_link_pic (link_info)
6074 || globals->root.is_relocatable_executable
27e55c4d 6075 || globals->pic_veneer)
2f475487 6076 size = ARM2THUMB_PIC_GLUE_SIZE;
26079076
PB		 6077 else if (globals->use_blx)
6078 size = ARM2THUMB_V5_STATIC_GLUE_SIZE;
8f6277f5 6079 else
2f475487
AM		 6080 size = ARM2THUMB_STATIC_GLUE_SIZE;
6081
6082 s->size += size;
6083 globals->arm_glue_size += size;
252b5132 6084
a4fd1a8e 6085 return myh;
252b5132
RH		 6086}
6087
845b51d6
PB		 6088/* Allocate space for ARMv4 BX veneers. */
6089
6090static void
6091record_arm_bx_glue (struct bfd_link_info * link_info, int reg)
6092{
6093 asection * s;
6094 struct elf32_arm_link_hash_table *globals;
6095 char *tmp_name;
6096 struct elf_link_hash_entry *myh;
6097 struct bfd_link_hash_entry *bh;
6098 bfd_vma val;
6099
6100 /* BX PC does not need a veneer. */
6101 if (reg == 15)
6102 return;
6103
6104 globals = elf32_arm_hash_table (link_info);
845b51d6
PB		 6105 BFD_ASSERT (globals != NULL);
6106 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
6107
6108 /* Check if this veneer has already been allocated. */
6109 if (globals->bx_glue_offset[reg])
6110 return;
6111
3d4d4302 6112 s = bfd_get_linker_section
845b51d6
PB		 6113 (globals->bfd_of_glue_owner, ARM_BX_GLUE_SECTION_NAME);
6114
6115 BFD_ASSERT (s != NULL);
6116
6117 /* Add symbol for veneer. */
21d799b5
NC		 6118 tmp_name = (char *)
6119 bfd_malloc ((bfd_size_type) strlen (ARM_BX_GLUE_ENTRY_NAME) + 1);
906e58ca 6120
845b51d6 6121 BFD_ASSERT (tmp_name);
906e58ca 6122
845b51d6 6123 sprintf (tmp_name, ARM_BX_GLUE_ENTRY_NAME, reg);
906e58ca 6124
845b51d6
PB		 6125 myh = elf_link_hash_lookup
6126 (&(globals)->root, tmp_name, FALSE, FALSE, FALSE);
906e58ca 6127
845b51d6 6128 BFD_ASSERT (myh == NULL);
906e58ca 6129
845b51d6
PB		 6130 bh = NULL;
6131 val = globals->bx_glue_size;
6132 _bfd_generic_link_add_one_symbol (link_info, globals->bfd_of_glue_owner,
99059e56
RM		 6133 tmp_name, BSF_FUNCTION | BSF_LOCAL, s, val,
6134 NULL, TRUE, FALSE, &bh);
845b51d6
PB		 6135
6136 myh = (struct elf_link_hash_entry *) bh;
6137 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
6138 myh->forced_local = 1;
6139
6140 s->size += ARM_BX_VENEER_SIZE;
6141 globals->bx_glue_offset[reg] = globals->bx_glue_size | 2;
6142 globals->bx_glue_size += ARM_BX_VENEER_SIZE;
6143}
6144
6145
c7b8f16e
JB		 6146/* Add an entry to the code/data map for section SEC. */
6147
6148static void
6149elf32_arm_section_map_add (asection *sec, char type, bfd_vma vma)
6150{
6151 struct _arm_elf_section_data *sec_data = elf32_arm_section_data (sec);
6152 unsigned int newidx;
906e58ca 6153
c7b8f16e
JB		 6154 if (sec_data->map == NULL)
6155 {
21d799b5 6156 sec_data->map = (elf32_arm_section_map *)
99059e56 6157 bfd_malloc (sizeof (elf32_arm_section_map));
c7b8f16e
JB		 6158 sec_data->mapcount = 0;
6159 sec_data->mapsize = 1;
6160 }
906e58ca 6161
c7b8f16e 6162 newidx = sec_data->mapcount++;
906e58ca 6163
c7b8f16e
JB		 6164 if (sec_data->mapcount > sec_data->mapsize)
6165 {
6166 sec_data->mapsize *= 2;
21d799b5 6167 sec_data->map = (elf32_arm_section_map *)
99059e56
RM		 6168 bfd_realloc_or_free (sec_data->map, sec_data->mapsize
6169 * sizeof (elf32_arm_section_map));
515ef31d
NC		 6170 }
6171
6172 if (sec_data->map)
6173 {
6174 sec_data->map[newidx].vma = vma;
6175 sec_data->map[newidx].type = type;
c7b8f16e 6176 }
c7b8f16e
JB		 6177}
6178
6179
6180/* Record information about a VFP11 denorm-erratum veneer. Only ARM-mode
6181 veneers are handled for now. */
6182
6183static bfd_vma
6184record_vfp11_erratum_veneer (struct bfd_link_info *link_info,
99059e56
RM		 6185 elf32_vfp11_erratum_list *branch,
6186 bfd *branch_bfd,
6187 asection *branch_sec,
6188 unsigned int offset)
c7b8f16e
JB		 6189{
6190 asection *s;
6191 struct elf32_arm_link_hash_table *hash_table;
6192 char *tmp_name;
6193 struct elf_link_hash_entry *myh;
6194 struct bfd_link_hash_entry *bh;
6195 bfd_vma val;
6196 struct _arm_elf_section_data *sec_data;
c7b8f16e 6197 elf32_vfp11_erratum_list *newerr;
906e58ca 6198
c7b8f16e 6199 hash_table = elf32_arm_hash_table (link_info);
c7b8f16e
JB		 6200 BFD_ASSERT (hash_table != NULL);
6201 BFD_ASSERT (hash_table->bfd_of_glue_owner != NULL);
906e58ca 6202
3d4d4302 6203 s = bfd_get_linker_section
c7b8f16e 6204 (hash_table->bfd_of_glue_owner, VFP11_ERRATUM_VENEER_SECTION_NAME);
906e58ca 6205
c7b8f16e 6206 sec_data = elf32_arm_section_data (s);
906e58ca 6207
c7b8f16e 6208 BFD_ASSERT (s != NULL);
906e58ca 6209
21d799b5 6210 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen
99059e56 6211 (VFP11_ERRATUM_VENEER_ENTRY_NAME) + 10);
906e58ca 6212
c7b8f16e 6213 BFD_ASSERT (tmp_name);
906e58ca 6214
c7b8f16e
JB		 6215 sprintf (tmp_name, VFP11_ERRATUM_VENEER_ENTRY_NAME,
6216 hash_table->num_vfp11_fixes);
906e58ca 6217
c7b8f16e
JB		 6218 myh = elf_link_hash_lookup
6219 (&(hash_table)->root, tmp_name, FALSE, FALSE, FALSE);
906e58ca 6220
c7b8f16e 6221 BFD_ASSERT (myh == NULL);
906e58ca 6222
c7b8f16e
JB		 6223 bh = NULL;
6224 val = hash_table->vfp11_erratum_glue_size;
6225 _bfd_generic_link_add_one_symbol (link_info, hash_table->bfd_of_glue_owner,
99059e56
RM		 6226 tmp_name, BSF_FUNCTION | BSF_LOCAL, s, val,
6227 NULL, TRUE, FALSE, &bh);
c7b8f16e
JB		 6228
6229 myh = (struct elf_link_hash_entry *) bh;
6230 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
6231 myh->forced_local = 1;
6232
6233 /* Link veneer back to calling location. */
c7e2358a 6234 sec_data->erratumcount += 1;
21d799b5
NC		 6235 newerr = (elf32_vfp11_erratum_list *)
6236 bfd_zmalloc (sizeof (elf32_vfp11_erratum_list));
906e58ca 6237
c7b8f16e
JB		 6238 newerr->type = VFP11_ERRATUM_ARM_VENEER;
6239 newerr->vma = -1;
6240 newerr->u.v.branch = branch;
6241 newerr->u.v.id = hash_table->num_vfp11_fixes;
6242 branch->u.b.veneer = newerr;
6243
6244 newerr->next = sec_data->erratumlist;
6245 sec_data->erratumlist = newerr;
6246
6247 /* A symbol for the return from the veneer. */
6248 sprintf (tmp_name, VFP11_ERRATUM_VENEER_ENTRY_NAME "_r",
6249 hash_table->num_vfp11_fixes);
6250
6251 myh = elf_link_hash_lookup
6252 (&(hash_table)->root, tmp_name, FALSE, FALSE, FALSE);
906e58ca 6253
c7b8f16e
JB		 6254 if (myh != NULL)
6255 abort ();
6256
6257 bh = NULL;
6258 val = offset + 4;
6259 _bfd_generic_link_add_one_symbol (link_info, branch_bfd, tmp_name, BSF_LOCAL,
6260 branch_sec, val, NULL, TRUE, FALSE, &bh);
906e58ca 6261
c7b8f16e
JB		 6262 myh = (struct elf_link_hash_entry *) bh;
6263 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
6264 myh->forced_local = 1;
6265
6266 free (tmp_name);
906e58ca 6267
c7b8f16e
JB		 6268 /* Generate a mapping symbol for the veneer section, and explicitly add an
6269 entry for that symbol to the code/data map for the section. */
6270 if (hash_table->vfp11_erratum_glue_size == 0)
6271 {
6272 bh = NULL;
6273 /* FIXME: Creates an ARM symbol. Thumb mode will need attention if it
99059e56 6274 ever requires this erratum fix. */
c7b8f16e
JB		 6275 _bfd_generic_link_add_one_symbol (link_info,
6276 hash_table->bfd_of_glue_owner, "$a",
6277 BSF_LOCAL, s, 0, NULL,
99059e56 6278 TRUE, FALSE, &bh);
c7b8f16e
JB		 6279
6280 myh = (struct elf_link_hash_entry *) bh;
6281 myh->type = ELF_ST_INFO (STB_LOCAL, STT_NOTYPE);
6282 myh->forced_local = 1;
906e58ca 6283
c7b8f16e 6284 /* The elf32_arm_init_maps function only cares about symbols from input
99059e56
RM		 6285 BFDs. We must make a note of this generated mapping symbol
6286 ourselves so that code byteswapping works properly in
6287 elf32_arm_write_section. */
c7b8f16e
JB		 6288 elf32_arm_section_map_add (s, 'a', 0);
6289 }
906e58ca 6290
c7b8f16e
JB		 6291 s->size += VFP11_ERRATUM_VENEER_SIZE;
6292 hash_table->vfp11_erratum_glue_size += VFP11_ERRATUM_VENEER_SIZE;
6293 hash_table->num_vfp11_fixes++;
906e58ca 6294
c7b8f16e
JB		 6295 /* The offset of the veneer. */
6296 return val;
6297}
6298
a504d23a
LA		 6299/* Record information about a STM32L4XX STM erratum veneer. Only THUMB-mode
6300 veneers need to be handled because used only in Cortex-M. */
6301
6302static bfd_vma
6303record_stm32l4xx_erratum_veneer (struct bfd_link_info *link_info,
6304 elf32_stm32l4xx_erratum_list *branch,
6305 bfd *branch_bfd,
6306 asection *branch_sec,
6307 unsigned int offset,
6308 bfd_size_type veneer_size)
6309{
6310 asection *s;
6311 struct elf32_arm_link_hash_table *hash_table;
6312 char *tmp_name;
6313 struct elf_link_hash_entry *myh;
6314 struct bfd_link_hash_entry *bh;
6315 bfd_vma val;
6316 struct _arm_elf_section_data *sec_data;
6317 elf32_stm32l4xx_erratum_list *newerr;
6318
6319 hash_table = elf32_arm_hash_table (link_info);
6320 BFD_ASSERT (hash_table != NULL);
6321 BFD_ASSERT (hash_table->bfd_of_glue_owner != NULL);
6322
6323 s = bfd_get_linker_section
6324 (hash_table->bfd_of_glue_owner, STM32L4XX_ERRATUM_VENEER_SECTION_NAME);
6325
6326 BFD_ASSERT (s != NULL);
6327
6328 sec_data = elf32_arm_section_data (s);
6329
6330 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen
6331 (STM32L4XX_ERRATUM_VENEER_ENTRY_NAME) + 10);
6332
6333 BFD_ASSERT (tmp_name);
6334
6335 sprintf (tmp_name, STM32L4XX_ERRATUM_VENEER_ENTRY_NAME,
6336 hash_table->num_stm32l4xx_fixes);
6337
6338 myh = elf_link_hash_lookup
6339 (&(hash_table)->root, tmp_name, FALSE, FALSE, FALSE);
6340
6341 BFD_ASSERT (myh == NULL);
6342
6343 bh = NULL;
6344 val = hash_table->stm32l4xx_erratum_glue_size;
6345 _bfd_generic_link_add_one_symbol (link_info, hash_table->bfd_of_glue_owner,
6346 tmp_name, BSF_FUNCTION | BSF_LOCAL, s, val,
6347 NULL, TRUE, FALSE, &bh);
6348
6349 myh = (struct elf_link_hash_entry *) bh;
6350 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
6351 myh->forced_local = 1;
6352
6353 /* Link veneer back to calling location. */
6354 sec_data->stm32l4xx_erratumcount += 1;
6355 newerr = (elf32_stm32l4xx_erratum_list *)
6356 bfd_zmalloc (sizeof (elf32_stm32l4xx_erratum_list));
6357
6358 newerr->type = STM32L4XX_ERRATUM_VENEER;
6359 newerr->vma = -1;
6360 newerr->u.v.branch = branch;
6361 newerr->u.v.id = hash_table->num_stm32l4xx_fixes;
6362 branch->u.b.veneer = newerr;
6363
6364 newerr->next = sec_data->stm32l4xx_erratumlist;
6365 sec_data->stm32l4xx_erratumlist = newerr;
6366
6367 /* A symbol for the return from the veneer. */
6368 sprintf (tmp_name, STM32L4XX_ERRATUM_VENEER_ENTRY_NAME "_r",
6369 hash_table->num_stm32l4xx_fixes);
6370
6371 myh = elf_link_hash_lookup
6372 (&(hash_table)->root, tmp_name, FALSE, FALSE, FALSE);
6373
6374 if (myh != NULL)
6375 abort ();
6376
6377 bh = NULL;
6378 val = offset + 4;
6379 _bfd_generic_link_add_one_symbol (link_info, branch_bfd, tmp_name, BSF_LOCAL,
6380 branch_sec, val, NULL, TRUE, FALSE, &bh);
6381
6382 myh = (struct elf_link_hash_entry *) bh;
6383 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
6384 myh->forced_local = 1;
6385
6386 free (tmp_name);
6387
6388 /* Generate a mapping symbol for the veneer section, and explicitly add an
6389 entry for that symbol to the code/data map for the section. */
6390 if (hash_table->stm32l4xx_erratum_glue_size == 0)
6391 {
6392 bh = NULL;
6393 /* Creates a THUMB symbol since there is no other choice. */
6394 _bfd_generic_link_add_one_symbol (link_info,
6395 hash_table->bfd_of_glue_owner, "$t",
6396 BSF_LOCAL, s, 0, NULL,
6397 TRUE, FALSE, &bh);
6398
6399 myh = (struct elf_link_hash_entry *) bh;
6400 myh->type = ELF_ST_INFO (STB_LOCAL, STT_NOTYPE);
6401 myh->forced_local = 1;
6402
6403 /* The elf32_arm_init_maps function only cares about symbols from input
6404 BFDs. We must make a note of this generated mapping symbol
6405 ourselves so that code byteswapping works properly in
6406 elf32_arm_write_section. */
6407 elf32_arm_section_map_add (s, 't', 0);
6408 }
6409
6410 s->size += veneer_size;
6411 hash_table->stm32l4xx_erratum_glue_size += veneer_size;
6412 hash_table->num_stm32l4xx_fixes++;
6413
6414 /* The offset of the veneer. */
6415 return val;
6416}
6417
8029a119 6418#define ARM_GLUE_SECTION_FLAGS \
3e6b1042
DJ		 6419 (SEC_ALLOC | SEC_LOAD | SEC_HAS_CONTENTS | SEC_IN_MEMORY | SEC_CODE \
6420 | SEC_READONLY | SEC_LINKER_CREATED)
8029a119
NC		 6421
6422/* Create a fake section for use by the ARM backend of the linker. */
6423
6424static bfd_boolean
6425arm_make_glue_section (bfd * abfd, const char * name)
6426{
6427 asection * sec;
6428
3d4d4302 6429 sec = bfd_get_linker_section (abfd, name);
8029a119
NC		 6430 if (sec != NULL)
6431 /* Already made. */
6432 return TRUE;
6433
3d4d4302 6434 sec = bfd_make_section_anyway_with_flags (abfd, name, ARM_GLUE_SECTION_FLAGS);
8029a119
NC		 6435
6436 if (sec == NULL
6437 || !bfd_set_section_alignment (abfd, sec, 2))
6438 return FALSE;
6439
6440 /* Set the gc mark to prevent the section from being removed by garbage
6441 collection, despite the fact that no relocs refer to this section. */
6442 sec->gc_mark = 1;
6443
6444 return TRUE;
6445}
6446
1db37fe6
YG		 6447/* Set size of .plt entries. This function is called from the
6448 linker scripts in ld/emultempl/{armelf}.em. */
6449
6450void
6451bfd_elf32_arm_use_long_plt (void)
6452{
6453 elf32_arm_use_long_plt_entry = TRUE;
6454}
6455
8afb0e02
NC		 6456/* Add the glue sections to ABFD. This function is called from the
6457 linker scripts in ld/emultempl/{armelf}.em. */
9b485d32 6458
b34976b6 6459bfd_boolean
57e8b36a
NC		 6460bfd_elf32_arm_add_glue_sections_to_bfd (bfd *abfd,
6461 struct bfd_link_info *info)
252b5132 6462{
a504d23a
LA		 6463 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (info);
6464 bfd_boolean dostm32l4xx = globals
6465 && globals->stm32l4xx_fix != BFD_ARM_STM32L4XX_FIX_NONE;
6466 bfd_boolean addglue;
6467
8afb0e02
NC		 6468 /* If we are only performing a partial
6469 link do not bother adding the glue. */
0e1862bb 6470 if (bfd_link_relocatable (info))
b34976b6 6471 return TRUE;
252b5132 6472
a504d23a 6473 addglue = arm_make_glue_section (abfd, ARM2THUMB_GLUE_SECTION_NAME)
8029a119
NC		 6474 && arm_make_glue_section (abfd, THUMB2ARM_GLUE_SECTION_NAME)
6475 && arm_make_glue_section (abfd, VFP11_ERRATUM_VENEER_SECTION_NAME)
6476 && arm_make_glue_section (abfd, ARM_BX_GLUE_SECTION_NAME);
a504d23a
LA		 6477
6478 if (!dostm32l4xx)
6479 return addglue;
6480
6481 return addglue
6482 && arm_make_glue_section (abfd, STM32L4XX_ERRATUM_VENEER_SECTION_NAME);
8afb0e02
NC		 6483}
6484
6485/* Select a BFD to be used to hold the sections used by the glue code.
6486 This function is called from the linker scripts in ld/emultempl/
8029a119 6487 {armelf/pe}.em. */
8afb0e02 6488
b34976b6 6489bfd_boolean
57e8b36a 6490bfd_elf32_arm_get_bfd_for_interworking (bfd *abfd, struct bfd_link_info *info)
8afb0e02
NC		 6491{
6492 struct elf32_arm_link_hash_table *globals;
6493
6494 /* If we are only performing a partial link
6495 do not bother getting a bfd to hold the glue. */
0e1862bb 6496 if (bfd_link_relocatable (info))
b34976b6 6497 return TRUE;
8afb0e02 6498
b7693d02
DJ		 6499 /* Make sure we don't attach the glue sections to a dynamic object. */
6500 BFD_ASSERT (!(abfd->flags & DYNAMIC));
6501
8afb0e02 6502 globals = elf32_arm_hash_table (info);
8afb0e02
NC		 6503 BFD_ASSERT (globals != NULL);
6504
6505 if (globals->bfd_of_glue_owner != NULL)
b34976b6 6506 return TRUE;
8afb0e02 6507
252b5132
RH		 6508 /* Save the bfd for later use. */
6509 globals->bfd_of_glue_owner = abfd;
cedb70c5 6510
b34976b6 6511 return TRUE;
252b5132
RH		 6512}
6513
906e58ca
NC		 6514static void
6515check_use_blx (struct elf32_arm_link_hash_table *globals)
39b41c9c 6516{
2de70689
MGD		 6517 int cpu_arch;
6518
b38cadfb 6519 cpu_arch = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC,
2de70689
MGD		 6520 Tag_CPU_arch);
6521
6522 if (globals->fix_arm1176)
6523 {
6524 if (cpu_arch == TAG_CPU_ARCH_V6T2 || cpu_arch > TAG_CPU_ARCH_V6K)
6525 globals->use_blx = 1;
6526 }
6527 else
6528 {
6529 if (cpu_arch > TAG_CPU_ARCH_V4T)
6530 globals->use_blx = 1;
6531 }
39b41c9c
PB		 6532}
6533
b34976b6 6534bfd_boolean
57e8b36a 6535bfd_elf32_arm_process_before_allocation (bfd *abfd,
d504ffc8 6536 struct bfd_link_info *link_info)
252b5132
RH		 6537{
6538 Elf_Internal_Shdr *symtab_hdr;
6cdc0ccc 6539 Elf_Internal_Rela *internal_relocs = NULL;
252b5132
RH		 6540 Elf_Internal_Rela *irel, *irelend;
6541 bfd_byte *contents = NULL;
252b5132
RH		 6542
6543 asection *sec;
6544 struct elf32_arm_link_hash_table *globals;
6545
6546 /* If we are only performing a partial link do not bother
6547 to construct any glue. */
0e1862bb 6548 if (bfd_link_relocatable (link_info))
b34976b6 6549 return TRUE;
252b5132 6550
39ce1a6a
NC		 6551 /* Here we have a bfd that is to be included on the link. We have a
6552 hook to do reloc rummaging, before section sizes are nailed down. */
252b5132 6553 globals = elf32_arm_hash_table (link_info);
252b5132 6554 BFD_ASSERT (globals != NULL);
39ce1a6a
NC		 6555
6556 check_use_blx (globals);
252b5132 6557
d504ffc8 6558 if (globals->byteswap_code && !bfd_big_endian (abfd))
e489d0ae 6559 {
d003868e
AM		 6560 _bfd_error_handler (_("%B: BE8 images only valid in big-endian mode."),
6561 abfd);
e489d0ae
PB		 6562 return FALSE;
6563 }
f21f3fe0 6564
39ce1a6a
NC		 6565 /* PR 5398: If we have not decided to include any loadable sections in
6566 the output then we will not have a glue owner bfd. This is OK, it
6567 just means that there is nothing else for us to do here. */
6568 if (globals->bfd_of_glue_owner == NULL)
6569 return TRUE;
6570
252b5132
RH		 6571 /* Rummage around all the relocs and map the glue vectors. */
6572 sec = abfd->sections;
6573
6574 if (sec == NULL)
b34976b6 6575 return TRUE;
252b5132
RH		 6576
6577 for (; sec != NULL; sec = sec->next)
6578 {
6579 if (sec->reloc_count == 0)
6580 continue;
6581
2f475487
AM		 6582 if ((sec->flags & SEC_EXCLUDE) != 0)
6583 continue;
6584
0ffa91dd 6585 symtab_hdr = & elf_symtab_hdr (abfd);
252b5132 6586
9b485d32 6587 /* Load the relocs. */
6cdc0ccc 6588 internal_relocs
906e58ca 6589 = _bfd_elf_link_read_relocs (abfd, sec, NULL, NULL, FALSE);
252b5132 6590
6cdc0ccc
AM		 6591 if (internal_relocs == NULL)
6592 goto error_return;
252b5132 6593
6cdc0ccc
AM		 6594 irelend = internal_relocs + sec->reloc_count;
6595 for (irel = internal_relocs; irel < irelend; irel++)
252b5132
RH		 6596 {
6597 long r_type;
6598 unsigned long r_index;
252b5132
RH		 6599
6600 struct elf_link_hash_entry *h;
6601
6602 r_type = ELF32_R_TYPE (irel->r_info);
6603 r_index = ELF32_R_SYM (irel->r_info);
6604
9b485d32 6605 /* These are the only relocation types we care about. */
ba96a88f 6606 if ( r_type != R_ARM_PC24
845b51d6 6607 && (r_type != R_ARM_V4BX || globals->fix_v4bx < 2))
252b5132
RH		 6608 continue;
6609
6610 /* Get the section contents if we haven't done so already. */
6611 if (contents == NULL)
6612 {
6613 /* Get cached copy if it exists. */
6614 if (elf_section_data (sec)->this_hdr.contents != NULL)
6615 contents = elf_section_data (sec)->this_hdr.contents;
6616 else
6617 {
6618 /* Go get them off disk. */
57e8b36a 6619 if (! bfd_malloc_and_get_section (abfd, sec, &contents))
252b5132
RH		 6620 goto error_return;
6621 }
6622 }
6623
845b51d6
PB		 6624 if (r_type == R_ARM_V4BX)
6625 {
6626 int reg;
6627
6628 reg = bfd_get_32 (abfd, contents + irel->r_offset) & 0xf;
6629 record_arm_bx_glue (link_info, reg);
6630 continue;
6631 }
6632
a7c10850 6633 /* If the relocation is not against a symbol it cannot concern us. */
252b5132
RH		 6634 h = NULL;
6635
9b485d32 6636 /* We don't care about local symbols. */
252b5132
RH		 6637 if (r_index < symtab_hdr->sh_info)
6638 continue;
6639
9b485d32 6640 /* This is an external symbol. */
252b5132
RH		 6641 r_index -= symtab_hdr->sh_info;
6642 h = (struct elf_link_hash_entry *)
6643 elf_sym_hashes (abfd)[r_index];
6644
6645 /* If the relocation is against a static symbol it must be within
6646 the current section and so cannot be a cross ARM/Thumb relocation. */
6647 if (h == NULL)
6648 continue;
6649
d504ffc8
DJ		 6650 /* If the call will go through a PLT entry then we do not need
6651 glue. */
362d30a1 6652 if (globals->root.splt != NULL && h->plt.offset != (bfd_vma) -1)
b7693d02
DJ		 6653 continue;
6654
252b5132
RH		 6655 switch (r_type)
6656 {
6657 case R_ARM_PC24:
6658 /* This one is a call from arm code. We need to look up
99059e56
RM		 6659 the target of the call. If it is a thumb target, we
6660 insert glue. */
39d911fc
TP		 6661 if (ARM_GET_SYM_BRANCH_TYPE (h->target_internal)
6662 == ST_BRANCH_TO_THUMB)
252b5132
RH		 6663 record_arm_to_thumb_glue (link_info, h);
6664 break;
6665
252b5132 6666 default:
c6596c5e 6667 abort ();
252b5132
RH		 6668 }
6669 }
6cdc0ccc
AM		 6670
6671 if (contents != NULL
6672 && elf_section_data (sec)->this_hdr.contents != contents)
6673 free (contents);
6674 contents = NULL;
6675
6676 if (internal_relocs != NULL
6677 && elf_section_data (sec)->relocs != internal_relocs)
6678 free (internal_relocs);
6679 internal_relocs = NULL;
252b5132
RH		 6680 }
6681
b34976b6 6682 return TRUE;
9a5aca8c 6683
252b5132 6684error_return:
6cdc0ccc
AM		 6685 if (contents != NULL
6686 && elf_section_data (sec)->this_hdr.contents != contents)
6687 free (contents);
6688 if (internal_relocs != NULL
6689 && elf_section_data (sec)->relocs != internal_relocs)
6690 free (internal_relocs);
9a5aca8c 6691
b34976b6 6692 return FALSE;
252b5132 6693}
7e392df6 6694#endif
252b5132 6695
eb043451 6696
c7b8f16e
JB		 6697/* Initialise maps of ARM/Thumb/data for input BFDs. */
6698
6699void
6700bfd_elf32_arm_init_maps (bfd *abfd)
6701{
6702 Elf_Internal_Sym *isymbuf;
6703 Elf_Internal_Shdr *hdr;
6704 unsigned int i, localsyms;
6705
af1f4419
NC		 6706 /* PR 7093: Make sure that we are dealing with an arm elf binary. */
6707 if (! is_arm_elf (abfd))
6708 return;
6709
c7b8f16e
JB		 6710 if ((abfd->flags & DYNAMIC) != 0)
6711 return;
6712
0ffa91dd 6713 hdr = & elf_symtab_hdr (abfd);
c7b8f16e
JB		 6714 localsyms = hdr->sh_info;
6715
6716 /* Obtain a buffer full of symbols for this BFD. The hdr->sh_info field
6717 should contain the number of local symbols, which should come before any
6718 global symbols. Mapping symbols are always local. */
6719 isymbuf = bfd_elf_get_elf_syms (abfd, hdr, localsyms, 0, NULL, NULL,
6720 NULL);
6721
6722 /* No internal symbols read? Skip this BFD. */
6723 if (isymbuf == NULL)
6724 return;
6725
6726 for (i = 0; i < localsyms; i++)
6727 {
6728 Elf_Internal_Sym *isym = &isymbuf[i];
6729 asection *sec = bfd_section_from_elf_index (abfd, isym->st_shndx);
6730 const char *name;
906e58ca 6731
c7b8f16e 6732 if (sec != NULL
99059e56
RM		 6733 && ELF_ST_BIND (isym->st_info) == STB_LOCAL)
6734 {
6735 name = bfd_elf_string_from_elf_section (abfd,
6736 hdr->sh_link, isym->st_name);
906e58ca 6737
99059e56 6738 if (bfd_is_arm_special_symbol_name (name,
c7b8f16e 6739 BFD_ARM_SPECIAL_SYM_TYPE_MAP))
99059e56
RM		 6740 elf32_arm_section_map_add (sec, name[1], isym->st_value);
6741 }
c7b8f16e
JB		 6742 }
6743}
6744
6745
48229727
JB		 6746/* Auto-select enabling of Cortex-A8 erratum fix if the user didn't explicitly
6747 say what they wanted. */
6748
6749void
6750bfd_elf32_arm_set_cortex_a8_fix (bfd *obfd, struct bfd_link_info *link_info)
6751{
6752 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (link_info);
6753 obj_attribute *out_attr = elf_known_obj_attributes_proc (obfd);
6754
4dfe6ac6
NC		 6755 if (globals == NULL)
6756 return;
6757
48229727
JB		 6758 if (globals->fix_cortex_a8 == -1)
6759 {
6760 /* Turn on Cortex-A8 erratum workaround for ARMv7-A. */
6761 if (out_attr[Tag_CPU_arch].i == TAG_CPU_ARCH_V7
6762 && (out_attr[Tag_CPU_arch_profile].i == 'A'
6763 || out_attr[Tag_CPU_arch_profile].i == 0))
6764 globals->fix_cortex_a8 = 1;
6765 else
6766 globals->fix_cortex_a8 = 0;
6767 }
6768}
6769
6770
c7b8f16e
JB		 6771void
6772bfd_elf32_arm_set_vfp11_fix (bfd *obfd, struct bfd_link_info *link_info)
6773{
6774 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (link_info);
104d59d1 6775 obj_attribute *out_attr = elf_known_obj_attributes_proc (obfd);
906e58ca 6776
4dfe6ac6
NC		 6777 if (globals == NULL)
6778 return;
c7b8f16e
JB		 6779 /* We assume that ARMv7+ does not need the VFP11 denorm erratum fix. */
6780 if (out_attr[Tag_CPU_arch].i >= TAG_CPU_ARCH_V7)
6781 {
6782 switch (globals->vfp11_fix)
99059e56
RM		 6783 {
6784 case BFD_ARM_VFP11_FIX_DEFAULT:
6785 case BFD_ARM_VFP11_FIX_NONE:
6786 globals->vfp11_fix = BFD_ARM_VFP11_FIX_NONE;
6787 break;
6788
6789 default:
6790 /* Give a warning, but do as the user requests anyway. */
6791 (*_bfd_error_handler) (_("%B: warning: selected VFP11 erratum "
6792 "workaround is not necessary for target architecture"), obfd);
6793 }
c7b8f16e
JB		 6794 }
6795 else if (globals->vfp11_fix == BFD_ARM_VFP11_FIX_DEFAULT)
6796 /* For earlier architectures, we might need the workaround, but do not
6797 enable it by default. If users is running with broken hardware, they
6798 must enable the erratum fix explicitly. */
6799 globals->vfp11_fix = BFD_ARM_VFP11_FIX_NONE;
6800}
6801
a504d23a
LA		 6802void
6803bfd_elf32_arm_set_stm32l4xx_fix (bfd *obfd, struct bfd_link_info *link_info)
6804{
6805 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (link_info);
6806 obj_attribute *out_attr = elf_known_obj_attributes_proc (obfd);
6807
6808 if (globals == NULL)
6809 return;
6810
6811 /* We assume only Cortex-M4 may require the fix. */
6812 if (out_attr[Tag_CPU_arch].i != TAG_CPU_ARCH_V7E_M
6813 || out_attr[Tag_CPU_arch_profile].i != 'M')
6814 {
6815 if (globals->stm32l4xx_fix != BFD_ARM_STM32L4XX_FIX_NONE)
6816 /* Give a warning, but do as the user requests anyway. */
6817 (*_bfd_error_handler)
6818 (_("%B: warning: selected STM32L4XX erratum "
6819 "workaround is not necessary for target architecture"), obfd);
6820 }
6821}
c7b8f16e 6822
906e58ca
NC		 6823enum bfd_arm_vfp11_pipe
6824{
c7b8f16e
JB		 6825 VFP11_FMAC,
6826 VFP11_LS,
6827 VFP11_DS,
6828 VFP11_BAD
6829};
6830
6831/* Return a VFP register number. This is encoded as RX:X for single-precision
6832 registers, or X:RX for double-precision registers, where RX is the group of
6833 four bits in the instruction encoding and X is the single extension bit.
6834 RX and X fields are specified using their lowest (starting) bit. The return
6835 value is:
6836
6837 0...31: single-precision registers s0...s31
6838 32...63: double-precision registers d0...d31.
906e58ca 6839
c7b8f16e
JB		 6840 Although X should be zero for VFP11 (encoding d0...d15 only), we might
6841 encounter VFP3 instructions, so we allow the full range for DP registers. */
906e58ca 6842
c7b8f16e
JB		 6843static unsigned int
6844bfd_arm_vfp11_regno (unsigned int insn, bfd_boolean is_double, unsigned int rx,
99059e56 6845 unsigned int x)
c7b8f16e
JB		 6846{
6847 if (is_double)
6848 return (((insn >> rx) & 0xf) | (((insn >> x) & 1) << 4)) + 32;
6849 else
6850 return (((insn >> rx) & 0xf) << 1) | ((insn >> x) & 1);
6851}
6852
6853/* Set bits in *WMASK according to a register number REG as encoded by
6854 bfd_arm_vfp11_regno(). Ignore d16-d31. */
6855
6856static void
6857bfd_arm_vfp11_write_mask (unsigned int *wmask, unsigned int reg)
6858{
6859 if (reg < 32)
6860 *wmask |= 1 << reg;
6861 else if (reg < 48)
6862 *wmask |= 3 << ((reg - 32) * 2);
6863}
6864
6865/* Return TRUE if WMASK overwrites anything in REGS. */
6866
6867static bfd_boolean
6868bfd_arm_vfp11_antidependency (unsigned int wmask, int *regs, int numregs)
6869{
6870 int i;
906e58ca 6871
c7b8f16e
JB		 6872 for (i = 0; i < numregs; i++)
6873 {
6874 unsigned int reg = regs[i];
6875
6876 if (reg < 32 && (wmask & (1 << reg)) != 0)
99059e56 6877 return TRUE;
906e58ca 6878
c7b8f16e
JB		 6879 reg -= 32;
6880
6881 if (reg >= 16)
99059e56 6882 continue;
906e58ca 6883
c7b8f16e 6884 if ((wmask & (3 << (reg * 2))) != 0)
99059e56 6885 return TRUE;
c7b8f16e 6886 }
906e58ca 6887
c7b8f16e
JB		 6888 return FALSE;
6889}
6890
6891/* In this function, we're interested in two things: finding input registers
6892 for VFP data-processing instructions, and finding the set of registers which
6893 arbitrary VFP instructions may write to. We use a 32-bit unsigned int to
6894 hold the written set, so FLDM etc. are easy to deal with (we're only
6895 interested in 32 SP registers or 16 dp registers, due to the VFP version
6896 implemented by the chip in question). DP registers are marked by setting
6897 both SP registers in the write mask). */
6898
6899static enum bfd_arm_vfp11_pipe
6900bfd_arm_vfp11_insn_decode (unsigned int insn, unsigned int *destmask, int *regs,
99059e56 6901 int *numregs)
c7b8f16e 6902{
91d6fa6a 6903 enum bfd_arm_vfp11_pipe vpipe = VFP11_BAD;
c7b8f16e
JB		 6904 bfd_boolean is_double = ((insn & 0xf00) == 0xb00) ? 1 : 0;
6905
6906 if ((insn & 0x0f000e10) == 0x0e000a00) /* A data-processing insn. */
6907 {
6908 unsigned int pqrs;
6909 unsigned int fd = bfd_arm_vfp11_regno (insn, is_double, 12, 22);
6910 unsigned int fm = bfd_arm_vfp11_regno (insn, is_double, 0, 5);
6911
6912 pqrs = ((insn & 0x00800000) >> 20)
99059e56
RM		 6913 | ((insn & 0x00300000) >> 19)
6914 | ((insn & 0x00000040) >> 6);
c7b8f16e
JB		 6915
6916 switch (pqrs)
99059e56
RM		 6917 {
6918 case 0: /* fmac[sd]. */
6919 case 1: /* fnmac[sd]. */
6920 case 2: /* fmsc[sd]. */
6921 case 3: /* fnmsc[sd]. */
6922 vpipe = VFP11_FMAC;
6923 bfd_arm_vfp11_write_mask (destmask, fd);
6924 regs[0] = fd;
6925 regs[1] = bfd_arm_vfp11_regno (insn, is_double, 16, 7); /* Fn. */
6926 regs[2] = fm;
6927 *numregs = 3;
6928 break;
6929
6930 case 4: /* fmul[sd]. */
6931 case 5: /* fnmul[sd]. */
6932 case 6: /* fadd[sd]. */
6933 case 7: /* fsub[sd]. */
6934 vpipe = VFP11_FMAC;
6935 goto vfp_binop;
6936
6937 case 8: /* fdiv[sd]. */
6938 vpipe = VFP11_DS;
6939 vfp_binop:
6940 bfd_arm_vfp11_write_mask (destmask, fd);
6941 regs[0] = bfd_arm_vfp11_regno (insn, is_double, 16, 7); /* Fn. */
6942 regs[1] = fm;
6943 *numregs = 2;
6944 break;
6945
6946 case 15: /* extended opcode. */
6947 {
6948 unsigned int extn = ((insn >> 15) & 0x1e)
6949 | ((insn >> 7) & 1);
6950
6951 switch (extn)
6952 {
6953 case 0: /* fcpy[sd]. */
6954 case 1: /* fabs[sd]. */
6955 case 2: /* fneg[sd]. */
6956 case 8: /* fcmp[sd]. */
6957 case 9: /* fcmpe[sd]. */
6958 case 10: /* fcmpz[sd]. */
6959 case 11: /* fcmpez[sd]. */
6960 case 16: /* fuito[sd]. */
6961 case 17: /* fsito[sd]. */
6962 case 24: /* ftoui[sd]. */
6963 case 25: /* ftouiz[sd]. */
6964 case 26: /* ftosi[sd]. */
6965 case 27: /* ftosiz[sd]. */
6966 /* These instructions will not bounce due to underflow. */
6967 *numregs = 0;
6968 vpipe = VFP11_FMAC;
6969 break;
6970
6971 case 3: /* fsqrt[sd]. */
6972 /* fsqrt cannot underflow, but it can (perhaps) overwrite
6973 registers to cause the erratum in previous instructions. */
6974 bfd_arm_vfp11_write_mask (destmask, fd);
6975 vpipe = VFP11_DS;
6976 break;
6977
6978 case 15: /* fcvt{ds,sd}. */
6979 {
6980 int rnum = 0;
6981
6982 bfd_arm_vfp11_write_mask (destmask, fd);
c7b8f16e
JB		 6983
6984 /* Only FCVTSD can underflow. */
99059e56
RM		 6985 if ((insn & 0x100) != 0)
6986 regs[rnum++] = fm;
c7b8f16e 6987
99059e56 6988 *numregs = rnum;
c7b8f16e 6989
99059e56
RM		 6990 vpipe = VFP11_FMAC;
6991 }
6992 break;
c7b8f16e 6993
99059e56
RM		 6994 default:
6995 return VFP11_BAD;
6996 }
6997 }
6998 break;
c7b8f16e 6999
99059e56
RM		 7000 default:
7001 return VFP11_BAD;
7002 }
c7b8f16e
JB		 7003 }
7004 /* Two-register transfer. */
7005 else if ((insn & 0x0fe00ed0) == 0x0c400a10)
7006 {
7007 unsigned int fm = bfd_arm_vfp11_regno (insn, is_double, 0, 5);
906e58ca 7008
c7b8f16e
JB		 7009 if ((insn & 0x100000) == 0)
7010 {
99059e56
RM		 7011 if (is_double)
7012 bfd_arm_vfp11_write_mask (destmask, fm);
7013 else
7014 {
7015 bfd_arm_vfp11_write_mask (destmask, fm);
7016 bfd_arm_vfp11_write_mask (destmask, fm + 1);
7017 }
c7b8f16e
JB		 7018 }
7019
91d6fa6a 7020 vpipe = VFP11_LS;
c7b8f16e
JB		 7021 }
7022 else if ((insn & 0x0e100e00) == 0x0c100a00) /* A load insn. */
7023 {
7024 int fd = bfd_arm_vfp11_regno (insn, is_double, 12, 22);
7025 unsigned int puw = ((insn >> 21) & 0x1) | (((insn >> 23) & 3) << 1);
906e58ca 7026
c7b8f16e 7027 switch (puw)
99059e56
RM		 7028 {
7029 case 0: /* Two-reg transfer. We should catch these above. */
7030 abort ();
906e58ca 7031
99059e56
RM		 7032 case 2: /* fldm[sdx]. */
7033 case 3:
7034 case 5:
7035 {
7036 unsigned int i, offset = insn & 0xff;
c7b8f16e 7037
99059e56
RM		 7038 if (is_double)
7039 offset >>= 1;
c7b8f16e 7040
99059e56
RM		 7041 for (i = fd; i < fd + offset; i++)
7042 bfd_arm_vfp11_write_mask (destmask, i);
7043 }
7044 break;
906e58ca 7045
99059e56
RM		 7046 case 4: /* fld[sd]. */
7047 case 6:
7048 bfd_arm_vfp11_write_mask (destmask, fd);
7049 break;
906e58ca 7050
99059e56
RM		 7051 default:
7052 return VFP11_BAD;
7053 }
c7b8f16e 7054
91d6fa6a 7055 vpipe = VFP11_LS;
c7b8f16e
JB		 7056 }
7057 /* Single-register transfer. Note L==0. */
7058 else if ((insn & 0x0f100e10) == 0x0e000a10)
7059 {
7060 unsigned int opcode = (insn >> 21) & 7;
7061 unsigned int fn = bfd_arm_vfp11_regno (insn, is_double, 16, 7);
7062
7063 switch (opcode)
99059e56
RM		 7064 {
7065 case 0: /* fmsr/fmdlr. */
7066 case 1: /* fmdhr. */
7067 /* Mark fmdhr and fmdlr as writing to the whole of the DP
7068 destination register. I don't know if this is exactly right,
7069 but it is the conservative choice. */
7070 bfd_arm_vfp11_write_mask (destmask, fn);
7071 break;
7072
7073 case 7: /* fmxr. */
7074 break;
7075 }
c7b8f16e 7076
91d6fa6a 7077 vpipe = VFP11_LS;
c7b8f16e
JB		 7078 }
7079
91d6fa6a 7080 return vpipe;
c7b8f16e
JB		 7081}
7082
7083
7084static int elf32_arm_compare_mapping (const void * a, const void * b);
7085
7086
7087/* Look for potentially-troublesome code sequences which might trigger the
7088 VFP11 denormal/antidependency erratum. See, e.g., the ARM1136 errata sheet
7089 (available from ARM) for details of the erratum. A short version is
7090 described in ld.texinfo. */
7091
7092bfd_boolean
7093bfd_elf32_arm_vfp11_erratum_scan (bfd *abfd, struct bfd_link_info *link_info)
7094{
7095 asection *sec;
7096 bfd_byte *contents = NULL;
7097 int state = 0;
7098 int regs[3], numregs = 0;
7099 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (link_info);
7100 int use_vector = (globals->vfp11_fix == BFD_ARM_VFP11_FIX_VECTOR);
906e58ca 7101
4dfe6ac6
NC		 7102 if (globals == NULL)
7103 return FALSE;
7104
c7b8f16e
JB		 7105 /* We use a simple FSM to match troublesome VFP11 instruction sequences.
7106 The states transition as follows:
906e58ca 7107
c7b8f16e 7108 0 -> 1 (vector) or 0 -> 2 (scalar)
99059e56
RM		 7109 A VFP FMAC-pipeline instruction has been seen. Fill
7110 regs[0]..regs[numregs-1] with its input operands. Remember this
7111 instruction in 'first_fmac'.
c7b8f16e
JB		 7112
7113 1 -> 2
99059e56
RM		 7114 Any instruction, except for a VFP instruction which overwrites
7115 regs[*].
906e58ca 7116
c7b8f16e
JB		 7117 1 -> 3 [ -> 0 ] or
7118 2 -> 3 [ -> 0 ]
99059e56
RM		 7119 A VFP instruction has been seen which overwrites any of regs[*].
7120 We must make a veneer! Reset state to 0 before examining next
7121 instruction.
906e58ca 7122
c7b8f16e 7123 2 -> 0
99059e56
RM		 7124 If we fail to match anything in state 2, reset to state 0 and reset
7125 the instruction pointer to the instruction after 'first_fmac'.
c7b8f16e
JB		 7126
7127 If the VFP11 vector mode is in use, there must be at least two unrelated
7128 instructions between anti-dependent VFP11 instructions to properly avoid
906e58ca 7129 triggering the erratum, hence the use of the extra state 1. */
c7b8f16e
JB		 7130
7131 /* If we are only performing a partial link do not bother
7132 to construct any glue. */
0e1862bb 7133 if (bfd_link_relocatable (link_info))
c7b8f16e
JB		 7134 return TRUE;
7135
0ffa91dd
NC		 7136 /* Skip if this bfd does not correspond to an ELF image. */
7137 if (! is_arm_elf (abfd))
7138 return TRUE;
906e58ca 7139
c7b8f16e
JB		 7140 /* We should have chosen a fix type by the time we get here. */
7141 BFD_ASSERT (globals->vfp11_fix != BFD_ARM_VFP11_FIX_DEFAULT);
7142
7143 if (globals->vfp11_fix == BFD_ARM_VFP11_FIX_NONE)
7144 return TRUE;
2e6030b9 7145
33a7ffc2
JM		 7146 /* Skip this BFD if it corresponds to an executable or dynamic object. */
7147 if ((abfd->flags & (EXEC_P | DYNAMIC)) != 0)
7148 return TRUE;
7149
c7b8f16e
JB		 7150 for (sec = abfd->sections; sec != NULL; sec = sec->next)
7151 {
7152 unsigned int i, span, first_fmac = 0, veneer_of_insn = 0;
7153 struct _arm_elf_section_data *sec_data;
7154
7155 /* If we don't have executable progbits, we're not interested in this
99059e56 7156 section. Also skip if section is to be excluded. */
c7b8f16e 7157 if (elf_section_type (sec) != SHT_PROGBITS
99059e56
RM		 7158 || (elf_section_flags (sec) & SHF_EXECINSTR) == 0
7159 || (sec->flags & SEC_EXCLUDE) != 0
dbaa2011 7160 || sec->sec_info_type == SEC_INFO_TYPE_JUST_SYMS
33a7ffc2 7161 || sec->output_section == bfd_abs_section_ptr
99059e56
RM		 7162 || strcmp (sec->name, VFP11_ERRATUM_VENEER_SECTION_NAME) == 0)
7163 continue;
c7b8f16e
JB		 7164
7165 sec_data = elf32_arm_section_data (sec);
906e58ca 7166
c7b8f16e 7167 if (sec_data->mapcount == 0)
99059e56 7168 continue;
906e58ca 7169
c7b8f16e
JB		 7170 if (elf_section_data (sec)->this_hdr.contents != NULL)
7171 contents = elf_section_data (sec)->this_hdr.contents;
7172 else if (! bfd_malloc_and_get_section (abfd, sec, &contents))
7173 goto error_return;
7174
7175 qsort (sec_data->map, sec_data->mapcount, sizeof (elf32_arm_section_map),
7176 elf32_arm_compare_mapping);
7177
7178 for (span = 0; span < sec_data->mapcount; span++)
99059e56
RM		 7179 {
7180 unsigned int span_start = sec_data->map[span].vma;
7181 unsigned int span_end = (span == sec_data->mapcount - 1)
c7b8f16e 7182 ? sec->size : sec_data->map[span + 1].vma;
99059e56
RM		 7183 char span_type = sec_data->map[span].type;
7184
7185 /* FIXME: Only ARM mode is supported at present. We may need to
7186 support Thumb-2 mode also at some point. */
7187 if (span_type != 'a')
7188 continue;
7189
7190 for (i = span_start; i < span_end;)
7191 {
7192 unsigned int next_i = i + 4;
7193 unsigned int insn = bfd_big_endian (abfd)
7194 ? (contents[i] << 24)
7195 | (contents[i + 1] << 16)
7196 | (contents[i + 2] << 8)
7197 | contents[i + 3]
7198 : (contents[i + 3] << 24)
7199 | (contents[i + 2] << 16)
7200 | (contents[i + 1] << 8)
7201 | contents[i];
7202 unsigned int writemask = 0;
7203 enum bfd_arm_vfp11_pipe vpipe;
7204
7205 switch (state)
7206 {
7207 case 0:
7208 vpipe = bfd_arm_vfp11_insn_decode (insn, &writemask, regs,
7209 &numregs);
7210 /* I'm assuming the VFP11 erratum can trigger with denorm
7211 operands on either the FMAC or the DS pipeline. This might
7212 lead to slightly overenthusiastic veneer insertion. */
7213 if (vpipe == VFP11_FMAC || vpipe == VFP11_DS)
7214 {
7215 state = use_vector ? 1 : 2;
7216 first_fmac = i;
7217 veneer_of_insn = insn;
7218 }
7219 break;
7220
7221 case 1:
7222 {
7223 int other_regs[3], other_numregs;
7224 vpipe = bfd_arm_vfp11_insn_decode (insn, &writemask,
c7b8f16e 7225 other_regs,
99059e56
RM		 7226 &other_numregs);
7227 if (vpipe != VFP11_BAD
7228 && bfd_arm_vfp11_antidependency (writemask, regs,
c7b8f16e 7229 numregs))
99059e56
RM		 7230 state = 3;
7231 else
7232 state = 2;
7233 }
7234 break;
7235
7236 case 2:
7237 {
7238 int other_regs[3], other_numregs;
7239 vpipe = bfd_arm_vfp11_insn_decode (insn, &writemask,
c7b8f16e 7240 other_regs,
99059e56
RM		 7241 &other_numregs);
7242 if (vpipe != VFP11_BAD
7243 && bfd_arm_vfp11_antidependency (writemask, regs,
c7b8f16e 7244 numregs))
99059e56
RM		 7245 state = 3;
7246 else
7247 {
7248 state = 0;
7249 next_i = first_fmac + 4;
7250 }
7251 }
7252 break;
7253
7254 case 3:
7255 abort (); /* Should be unreachable. */
7256 }
7257
7258 if (state == 3)
7259 {
7260 elf32_vfp11_erratum_list *newerr =(elf32_vfp11_erratum_list *)
7261 bfd_zmalloc (sizeof (elf32_vfp11_erratum_list));
7262
7263 elf32_arm_section_data (sec)->erratumcount += 1;
7264
7265 newerr->u.b.vfp_insn = veneer_of_insn;
7266
7267 switch (span_type)
7268 {
7269 case 'a':
7270 newerr->type = VFP11_ERRATUM_BRANCH_TO_ARM_VENEER;
7271 break;
7272
7273 default:
7274 abort ();
7275 }
7276
7277 record_vfp11_erratum_veneer (link_info, newerr, abfd, sec,
c7b8f16e
JB		 7278 first_fmac);
7279
99059e56 7280 newerr->vma = -1;
c7b8f16e 7281
99059e56
RM		 7282 newerr->next = sec_data->erratumlist;
7283 sec_data->erratumlist = newerr;
c7b8f16e 7284
99059e56
RM		 7285 state = 0;
7286 }
c7b8f16e 7287
99059e56
RM		 7288 i = next_i;
7289 }
7290 }
906e58ca 7291
c7b8f16e 7292 if (contents != NULL
99059e56
RM		 7293 && elf_section_data (sec)->this_hdr.contents != contents)
7294 free (contents);
c7b8f16e
JB		 7295 contents = NULL;
7296 }
7297
7298 return TRUE;
7299
7300error_return:
7301 if (contents != NULL
7302 && elf_section_data (sec)->this_hdr.contents != contents)
7303 free (contents);
906e58ca 7304
c7b8f16e
JB		 7305 return FALSE;
7306}
7307
7308/* Find virtual-memory addresses for VFP11 erratum veneers and return locations
7309 after sections have been laid out, using specially-named symbols. */
7310
7311void
7312bfd_elf32_arm_vfp11_fix_veneer_locations (bfd *abfd,
7313 struct bfd_link_info *link_info)
7314{
7315 asection *sec;
7316 struct elf32_arm_link_hash_table *globals;
7317 char *tmp_name;
906e58ca 7318
0e1862bb 7319 if (bfd_link_relocatable (link_info))
c7b8f16e 7320 return;
2e6030b9
MS		 7321
7322 /* Skip if this bfd does not correspond to an ELF image. */
0ffa91dd 7323 if (! is_arm_elf (abfd))
2e6030b9
MS		 7324 return;
7325
c7b8f16e 7326 globals = elf32_arm_hash_table (link_info);
4dfe6ac6
NC		 7327 if (globals == NULL)
7328 return;
906e58ca 7329
21d799b5 7330 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen
99059e56 7331 (VFP11_ERRATUM_VENEER_ENTRY_NAME) + 10);
c7b8f16e
JB		 7332
7333 for (sec = abfd->sections; sec != NULL; sec = sec->next)
7334 {
7335 struct _arm_elf_section_data *sec_data = elf32_arm_section_data (sec);
7336 elf32_vfp11_erratum_list *errnode = sec_data->erratumlist;
906e58ca 7337
c7b8f16e 7338 for (; errnode != NULL; errnode = errnode->next)
99059e56
RM		 7339 {
7340 struct elf_link_hash_entry *myh;
7341 bfd_vma vma;
7342
7343 switch (errnode->type)
7344 {
7345 case VFP11_ERRATUM_BRANCH_TO_ARM_VENEER:
7346 case VFP11_ERRATUM_BRANCH_TO_THUMB_VENEER:
7347 /* Find veneer symbol. */
7348 sprintf (tmp_name, VFP11_ERRATUM_VENEER_ENTRY_NAME,
c7b8f16e
JB		 7349 errnode->u.b.veneer->u.v.id);
7350
99059e56
RM		 7351 myh = elf_link_hash_lookup
7352 (&(globals)->root, tmp_name, FALSE, FALSE, TRUE);
c7b8f16e 7353
a504d23a
LA		 7354 if (myh == NULL)
7355 (*_bfd_error_handler) (_("%B: unable to find VFP11 veneer "
7356 "`%s'"), abfd, tmp_name);
7357
7358 vma = myh->root.u.def.section->output_section->vma
7359 + myh->root.u.def.section->output_offset
7360 + myh->root.u.def.value;
7361
7362 errnode->u.b.veneer->vma = vma;
7363 break;
7364
7365 case VFP11_ERRATUM_ARM_VENEER:
7366 case VFP11_ERRATUM_THUMB_VENEER:
7367 /* Find return location. */
7368 sprintf (tmp_name, VFP11_ERRATUM_VENEER_ENTRY_NAME "_r",
7369 errnode->u.v.id);
7370
7371 myh = elf_link_hash_lookup
7372 (&(globals)->root, tmp_name, FALSE, FALSE, TRUE);
7373
7374 if (myh == NULL)
7375 (*_bfd_error_handler) (_("%B: unable to find VFP11 veneer "
7376 "`%s'"), abfd, tmp_name);
7377
7378 vma = myh->root.u.def.section->output_section->vma
7379 + myh->root.u.def.section->output_offset
7380 + myh->root.u.def.value;
7381
7382 errnode->u.v.branch->vma = vma;
7383 break;
7384
7385 default:
7386 abort ();
7387 }
7388 }
7389 }
7390
7391 free (tmp_name);
7392}
7393
7394/* Find virtual-memory addresses for STM32L4XX erratum veneers and
7395 return locations after sections have been laid out, using
7396 specially-named symbols. */
7397
7398void
7399bfd_elf32_arm_stm32l4xx_fix_veneer_locations (bfd *abfd,
7400 struct bfd_link_info *link_info)
7401{
7402 asection *sec;
7403 struct elf32_arm_link_hash_table *globals;
7404 char *tmp_name;
7405
7406 if (bfd_link_relocatable (link_info))
7407 return;
7408
7409 /* Skip if this bfd does not correspond to an ELF image. */
7410 if (! is_arm_elf (abfd))
7411 return;
7412
7413 globals = elf32_arm_hash_table (link_info);
7414 if (globals == NULL)
7415 return;
7416
7417 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen
7418 (STM32L4XX_ERRATUM_VENEER_ENTRY_NAME) + 10);
7419
7420 for (sec = abfd->sections; sec != NULL; sec = sec->next)
7421 {
7422 struct _arm_elf_section_data *sec_data = elf32_arm_section_data (sec);
7423 elf32_stm32l4xx_erratum_list *errnode = sec_data->stm32l4xx_erratumlist;
7424
7425 for (; errnode != NULL; errnode = errnode->next)
7426 {
7427 struct elf_link_hash_entry *myh;
7428 bfd_vma vma;
7429
7430 switch (errnode->type)
7431 {
7432 case STM32L4XX_ERRATUM_BRANCH_TO_VENEER:
7433 /* Find veneer symbol. */
7434 sprintf (tmp_name, STM32L4XX_ERRATUM_VENEER_ENTRY_NAME,
7435 errnode->u.b.veneer->u.v.id);
7436
7437 myh = elf_link_hash_lookup
7438 (&(globals)->root, tmp_name, FALSE, FALSE, TRUE);
7439
7440 if (myh == NULL)
7441 (*_bfd_error_handler) (_("%B: unable to find STM32L4XX veneer "
7442 "`%s'"), abfd, tmp_name);
7443
7444 vma = myh->root.u.def.section->output_section->vma
7445 + myh->root.u.def.section->output_offset
7446 + myh->root.u.def.value;
7447
7448 errnode->u.b.veneer->vma = vma;
7449 break;
7450
7451 case STM32L4XX_ERRATUM_VENEER:
7452 /* Find return location. */
7453 sprintf (tmp_name, STM32L4XX_ERRATUM_VENEER_ENTRY_NAME "_r",
7454 errnode->u.v.id);
7455
7456 myh = elf_link_hash_lookup
7457 (&(globals)->root, tmp_name, FALSE, FALSE, TRUE);
7458
7459 if (myh == NULL)
7460 (*_bfd_error_handler) (_("%B: unable to find STM32L4XX veneer "
7461 "`%s'"), abfd, tmp_name);
7462
7463 vma = myh->root.u.def.section->output_section->vma
7464 + myh->root.u.def.section->output_offset
7465 + myh->root.u.def.value;
7466
7467 errnode->u.v.branch->vma = vma;
7468 break;
7469
7470 default:
7471 abort ();
7472 }
7473 }
7474 }
7475
7476 free (tmp_name);
7477}
7478
7479static inline bfd_boolean
7480is_thumb2_ldmia (const insn32 insn)
7481{
7482 /* Encoding T2: LDM<c>.W <Rn>{!},<registers>
7483 1110 - 1000 - 10W1 - rrrr - PM (0) l - llll - llll - llll. */
7484 return (insn & 0xffd02000) == 0xe8900000;
7485}
7486
7487static inline bfd_boolean
7488is_thumb2_ldmdb (const insn32 insn)
7489{
7490 /* Encoding T1: LDMDB<c> <Rn>{!},<registers>
7491 1110 - 1001 - 00W1 - rrrr - PM (0) l - llll - llll - llll. */
7492 return (insn & 0xffd02000) == 0xe9100000;
7493}
7494
7495static inline bfd_boolean
7496is_thumb2_vldm (const insn32 insn)
7497{
7498 /* A6.5 Extension register load or store instruction
7499 A7.7.229
9239bbd3
CM		 7500 We look for SP 32-bit and DP 64-bit registers.
7501 Encoding T1 VLDM{mode}<c> <Rn>{!}, <list>
7502 <list> is consecutive 64-bit registers
7503 1110 - 110P - UDW1 - rrrr - vvvv - 1011 - iiii - iiii
a504d23a
LA		 7504 Encoding T2 VLDM{mode}<c> <Rn>{!}, <list>
7505 <list> is consecutive 32-bit registers
7506 1110 - 110P - UDW1 - rrrr - vvvv - 1010 - iiii - iiii
7507 if P==0 && U==1 && W==1 && Rn=1101 VPOP
7508 if PUW=010 || PUW=011 || PUW=101 VLDM. */
7509 return
9239bbd3
CM		 7510 (((insn & 0xfe100f00) == 0xec100b00) ||
7511 ((insn & 0xfe100f00) == 0xec100a00))
a504d23a
LA		 7512 && /* (IA without !). */
7513 (((((insn << 7) >> 28) & 0xd) == 0x4)
9239bbd3 7514 /* (IA with !), includes VPOP (when reg number is SP). */
a504d23a
LA		 7515 || ((((insn << 7) >> 28) & 0xd) == 0x5)
7516 /* (DB with !). */
7517 || ((((insn << 7) >> 28) & 0xd) == 0x9));
7518}
7519
7520/* STM STM32L4XX erratum : This function assumes that it receives an LDM or
7521 VLDM opcode and:
7522 - computes the number and the mode of memory accesses
7523 - decides if the replacement should be done:
7524 . replaces only if > 8-word accesses
7525 . or (testing purposes only) replaces all accesses. */
7526
7527static bfd_boolean
7528stm32l4xx_need_create_replacing_stub (const insn32 insn,
7529 bfd_arm_stm32l4xx_fix stm32l4xx_fix)
7530{
9239bbd3 7531 int nb_words = 0;
a504d23a
LA		 7532
7533 /* The field encoding the register list is the same for both LDMIA
7534 and LDMDB encodings. */
7535 if (is_thumb2_ldmia (insn) || is_thumb2_ldmdb (insn))
9239bbd3 7536 nb_words = popcount (insn & 0x0000ffff);
a504d23a 7537 else if (is_thumb2_vldm (insn))
9239bbd3 7538 nb_words = (insn & 0xff);
a504d23a
LA		 7539
7540 /* DEFAULT mode accounts for the real bug condition situation,
7541 ALL mode inserts stubs for each LDM/VLDM instruction (testing). */
7542 return
9239bbd3 7543 (stm32l4xx_fix == BFD_ARM_STM32L4XX_FIX_DEFAULT) ? nb_words > 8 :
a504d23a
LA		 7544 (stm32l4xx_fix == BFD_ARM_STM32L4XX_FIX_ALL) ? TRUE : FALSE;
7545}
7546
7547/* Look for potentially-troublesome code sequences which might trigger
7548 the STM STM32L4XX erratum. */
7549
7550bfd_boolean
7551bfd_elf32_arm_stm32l4xx_erratum_scan (bfd *abfd,
7552 struct bfd_link_info *link_info)
7553{
7554 asection *sec;
7555 bfd_byte *contents = NULL;
7556 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (link_info);
7557
7558 if (globals == NULL)
7559 return FALSE;
7560
7561 /* If we are only performing a partial link do not bother
7562 to construct any glue. */
7563 if (bfd_link_relocatable (link_info))
7564 return TRUE;
7565
7566 /* Skip if this bfd does not correspond to an ELF image. */
7567 if (! is_arm_elf (abfd))
7568 return TRUE;
7569
7570 if (globals->stm32l4xx_fix == BFD_ARM_STM32L4XX_FIX_NONE)
7571 return TRUE;
7572
7573 /* Skip this BFD if it corresponds to an executable or dynamic object. */
7574 if ((abfd->flags & (EXEC_P | DYNAMIC)) != 0)
7575 return TRUE;
7576
7577 for (sec = abfd->sections; sec != NULL; sec = sec->next)
7578 {
7579 unsigned int i, span;
7580 struct _arm_elf_section_data *sec_data;
7581
7582 /* If we don't have executable progbits, we're not interested in this
7583 section. Also skip if section is to be excluded. */
7584 if (elf_section_type (sec) != SHT_PROGBITS
7585 || (elf_section_flags (sec) & SHF_EXECINSTR) == 0
7586 || (sec->flags & SEC_EXCLUDE) != 0
7587 || sec->sec_info_type == SEC_INFO_TYPE_JUST_SYMS
7588 || sec->output_section == bfd_abs_section_ptr
7589 || strcmp (sec->name, STM32L4XX_ERRATUM_VENEER_SECTION_NAME) == 0)
7590 continue;
7591
7592 sec_data = elf32_arm_section_data (sec);
c7b8f16e 7593
a504d23a
LA		 7594 if (sec_data->mapcount == 0)
7595 continue;
c7b8f16e 7596
a504d23a
LA		 7597 if (elf_section_data (sec)->this_hdr.contents != NULL)
7598 contents = elf_section_data (sec)->this_hdr.contents;
7599 else if (! bfd_malloc_and_get_section (abfd, sec, &contents))
7600 goto error_return;
c7b8f16e 7601
a504d23a
LA		 7602 qsort (sec_data->map, sec_data->mapcount, sizeof (elf32_arm_section_map),
7603 elf32_arm_compare_mapping);
c7b8f16e 7604
a504d23a
LA		 7605 for (span = 0; span < sec_data->mapcount; span++)
7606 {
7607 unsigned int span_start = sec_data->map[span].vma;
7608 unsigned int span_end = (span == sec_data->mapcount - 1)
7609 ? sec->size : sec_data->map[span + 1].vma;
7610 char span_type = sec_data->map[span].type;
7611 int itblock_current_pos = 0;
c7b8f16e 7612
a504d23a
LA		 7613 /* Only Thumb2 mode need be supported with this CM4 specific
7614 code, we should not encounter any arm mode eg span_type
7615 != 'a'. */
7616 if (span_type != 't')
7617 continue;
c7b8f16e 7618
a504d23a
LA		 7619 for (i = span_start; i < span_end;)
7620 {
7621 unsigned int insn = bfd_get_16 (abfd, &contents[i]);
7622 bfd_boolean insn_32bit = FALSE;
7623 bfd_boolean is_ldm = FALSE;
7624 bfd_boolean is_vldm = FALSE;
7625 bfd_boolean is_not_last_in_it_block = FALSE;
7626
7627 /* The first 16-bits of all 32-bit thumb2 instructions start
7628 with opcode[15..13]=0b111 and the encoded op1 can be anything
7629 except opcode[12..11]!=0b00.
7630 See 32-bit Thumb instruction encoding. */
7631 if ((insn & 0xe000) == 0xe000 && (insn & 0x1800) != 0x0000)
7632 insn_32bit = TRUE;
c7b8f16e 7633
a504d23a
LA		 7634 /* Compute the predicate that tells if the instruction
7635 is concerned by the IT block
7636 - Creates an error if there is a ldm that is not
7637 last in the IT block thus cannot be replaced
7638 - Otherwise we can create a branch at the end of the
7639 IT block, it will be controlled naturally by IT
7640 with the proper pseudo-predicate
7641 - So the only interesting predicate is the one that
7642 tells that we are not on the last item of an IT
7643 block. */
7644 if (itblock_current_pos != 0)
7645 is_not_last_in_it_block = !!--itblock_current_pos;
906e58ca 7646
a504d23a
LA		 7647 if (insn_32bit)
7648 {
7649 /* Load the rest of the insn (in manual-friendly order). */
7650 insn = (insn << 16) | bfd_get_16 (abfd, &contents[i + 2]);
7651 is_ldm = is_thumb2_ldmia (insn) || is_thumb2_ldmdb (insn);
7652 is_vldm = is_thumb2_vldm (insn);
7653
7654 /* Veneers are created for (v)ldm depending on
7655 option flags and memory accesses conditions; but
7656 if the instruction is not the last instruction of
7657 an IT block, we cannot create a jump there, so we
7658 bail out. */
7659 if ((is_ldm || is_vldm) &&
7660 stm32l4xx_need_create_replacing_stub
7661 (insn, globals->stm32l4xx_fix))
7662 {
7663 if (is_not_last_in_it_block)
7664 {
7665 (*_bfd_error_handler)
7666 /* Note - overlong line used here to allow for translation. */
7667 (_("\
7668%B(%A+0x%lx): error: multiple load detected in non-last IT block instruction : STM32L4XX veneer cannot be generated.\n"
7669 "Use gcc option -mrestrict-it to generate only one instruction per IT block.\n"),
7670 abfd, sec, (long)i);
7671 }
7672 else
7673 {
7674 elf32_stm32l4xx_erratum_list *newerr =
7675 (elf32_stm32l4xx_erratum_list *)
7676 bfd_zmalloc
7677 (sizeof (elf32_stm32l4xx_erratum_list));
7678
7679 elf32_arm_section_data (sec)
7680 ->stm32l4xx_erratumcount += 1;
7681 newerr->u.b.insn = insn;
7682 /* We create only thumb branches. */
7683 newerr->type =
7684 STM32L4XX_ERRATUM_BRANCH_TO_VENEER;
7685 record_stm32l4xx_erratum_veneer
7686 (link_info, newerr, abfd, sec,
7687 i,
7688 is_ldm ?
7689 STM32L4XX_ERRATUM_LDM_VENEER_SIZE:
7690 STM32L4XX_ERRATUM_VLDM_VENEER_SIZE);
7691 newerr->vma = -1;
7692 newerr->next = sec_data->stm32l4xx_erratumlist;
7693 sec_data->stm32l4xx_erratumlist = newerr;
7694 }
7695 }
7696 }
7697 else
7698 {
7699 /* A7.7.37 IT p208
7700 IT blocks are only encoded in T1
7701 Encoding T1: IT{x{y{z}}} <firstcond>
7702 1 0 1 1 - 1 1 1 1 - firstcond - mask
7703 if mask = '0000' then see 'related encodings'
7704 We don't deal with UNPREDICTABLE, just ignore these.
7705 There can be no nested IT blocks so an IT block
7706 is naturally a new one for which it is worth
7707 computing its size. */
7708 bfd_boolean is_newitblock = ((insn & 0xff00) == 0xbf00) &&
7709 ((insn & 0x000f) != 0x0000);
7710 /* If we have a new IT block we compute its size. */
7711 if (is_newitblock)
7712 {
7713 /* Compute the number of instructions controlled
7714 by the IT block, it will be used to decide
7715 whether we are inside an IT block or not. */
7716 unsigned int mask = insn & 0x000f;
7717 itblock_current_pos = 4 - ctz (mask);
7718 }
7719 }
7720
7721 i += insn_32bit ? 4 : 2;
99059e56
RM		 7722 }
7723 }
a504d23a
LA		 7724
7725 if (contents != NULL
7726 && elf_section_data (sec)->this_hdr.contents != contents)
7727 free (contents);
7728 contents = NULL;
c7b8f16e 7729 }
906e58ca 7730
a504d23a
LA		 7731 return TRUE;
7732
7733error_return:
7734 if (contents != NULL
7735 && elf_section_data (sec)->this_hdr.contents != contents)
7736 free (contents);
c7b8f16e 7737
a504d23a
LA		 7738 return FALSE;
7739}
c7b8f16e 7740
eb043451
PB		 7741/* Set target relocation values needed during linking. */
7742
7743void
bf21ed78
MS		 7744bfd_elf32_arm_set_target_relocs (struct bfd *output_bfd,
7745 struct bfd_link_info *link_info,
eb043451 7746 int target1_is_rel,
319850b4 7747 char * target2_type,
99059e56 7748 int fix_v4bx,
c7b8f16e 7749 int use_blx,
99059e56 7750 bfd_arm_vfp11_fix vfp11_fix,
a504d23a 7751 bfd_arm_stm32l4xx_fix stm32l4xx_fix,
a9dc9481 7752 int no_enum_warn, int no_wchar_warn,
2de70689
MGD		 7753 int pic_veneer, int fix_cortex_a8,
7754 int fix_arm1176)
eb043451
PB		 7755{
7756 struct elf32_arm_link_hash_table *globals;
7757
7758 globals = elf32_arm_hash_table (link_info);
4dfe6ac6
NC		 7759 if (globals == NULL)
7760 return;
eb043451
PB		 7761
7762 globals->target1_is_rel = target1_is_rel;
7763 if (strcmp (target2_type, "rel") == 0)
7764 globals->target2_reloc = R_ARM_REL32;
eeac373a
PB		 7765 else if (strcmp (target2_type, "abs") == 0)
7766 globals->target2_reloc = R_ARM_ABS32;
eb043451
PB		 7767 else if (strcmp (target2_type, "got-rel") == 0)
7768 globals->target2_reloc = R_ARM_GOT_PREL;
7769 else
7770 {
7771 _bfd_error_handler (_("Invalid TARGET2 relocation type '%s'."),
7772 target2_type);
7773 }
319850b4 7774 globals->fix_v4bx = fix_v4bx;
33bfe774 7775 globals->use_blx |= use_blx;
c7b8f16e 7776 globals->vfp11_fix = vfp11_fix;
a504d23a 7777 globals->stm32l4xx_fix = stm32l4xx_fix;
27e55c4d 7778 globals->pic_veneer = pic_veneer;
48229727 7779 globals->fix_cortex_a8 = fix_cortex_a8;
2de70689 7780 globals->fix_arm1176 = fix_arm1176;
bf21ed78 7781
0ffa91dd
NC		 7782 BFD_ASSERT (is_arm_elf (output_bfd));
7783 elf_arm_tdata (output_bfd)->no_enum_size_warning = no_enum_warn;
a9dc9481 7784 elf_arm_tdata (output_bfd)->no_wchar_size_warning = no_wchar_warn;
eb043451 7785}
eb043451 7786
12a0a0fd 7787/* Replace the target offset of a Thumb bl or b.w instruction. */
252b5132 7788
12a0a0fd
PB		 7789static void
7790insert_thumb_branch (bfd *abfd, long int offset, bfd_byte *insn)
7791{
7792 bfd_vma upper;
7793 bfd_vma lower;
7794 int reloc_sign;
7795
7796 BFD_ASSERT ((offset & 1) == 0);
7797
7798 upper = bfd_get_16 (abfd, insn);
7799 lower = bfd_get_16 (abfd, insn + 2);
7800 reloc_sign = (offset < 0) ? 1 : 0;
7801 upper = (upper & ~(bfd_vma) 0x7ff)
7802 | ((offset >> 12) & 0x3ff)
7803 | (reloc_sign << 10);
906e58ca 7804 lower = (lower & ~(bfd_vma) 0x2fff)
12a0a0fd
PB		 7805 | (((!((offset >> 23) & 1)) ^ reloc_sign) << 13)
7806 | (((!((offset >> 22) & 1)) ^ reloc_sign) << 11)
7807 | ((offset >> 1) & 0x7ff);
7808 bfd_put_16 (abfd, upper, insn);
7809 bfd_put_16 (abfd, lower, insn + 2);
252b5132
RH		 7810}
7811
9b485d32
NC		 7812/* Thumb code calling an ARM function. */
7813
252b5132 7814static int
57e8b36a
NC		 7815elf32_thumb_to_arm_stub (struct bfd_link_info * info,
7816 const char * name,
7817 bfd * input_bfd,
7818 bfd * output_bfd,
7819 asection * input_section,
7820 bfd_byte * hit_data,
7821 asection * sym_sec,
7822 bfd_vma offset,
7823 bfd_signed_vma addend,
f2a9dd69
DJ		 7824 bfd_vma val,
7825 char **error_message)
252b5132 7826{
bcbdc74c 7827 asection * s = 0;
dc810e39 7828 bfd_vma my_offset;
252b5132 7829 long int ret_offset;
bcbdc74c
NC		 7830 struct elf_link_hash_entry * myh;
7831 struct elf32_arm_link_hash_table * globals;
252b5132 7832
f2a9dd69 7833 myh = find_thumb_glue (info, name, error_message);
252b5132 7834 if (myh == NULL)
b34976b6 7835 return FALSE;
252b5132
RH		 7836
7837 globals = elf32_arm_hash_table (info);
252b5132
RH		 7838 BFD_ASSERT (globals != NULL);
7839 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
7840
7841 my_offset = myh->root.u.def.value;
7842
3d4d4302
AM		 7843 s = bfd_get_linker_section (globals->bfd_of_glue_owner,
7844 THUMB2ARM_GLUE_SECTION_NAME);
252b5132
RH		 7845
7846 BFD_ASSERT (s != NULL);
7847 BFD_ASSERT (s->contents != NULL);
7848 BFD_ASSERT (s->output_section != NULL);
7849
7850 if ((my_offset & 0x01) == 0x01)
7851 {
7852 if (sym_sec != NULL
7853 && sym_sec->owner != NULL
7854 && !INTERWORK_FLAG (sym_sec->owner))
7855 {
8f615d07 7856 (*_bfd_error_handler)
d003868e 7857 (_("%B(%s): warning: interworking not enabled.\n"
3aaeb7d3 7858 " first occurrence: %B: Thumb call to ARM"),
d003868e 7859 sym_sec->owner, input_bfd, name);
252b5132 7860
b34976b6 7861 return FALSE;
252b5132
RH		 7862 }
7863
7864 --my_offset;
7865 myh->root.u.def.value = my_offset;
7866
52ab56c2
PB		 7867 put_thumb_insn (globals, output_bfd, (bfd_vma) t2a1_bx_pc_insn,
7868 s->contents + my_offset);
252b5132 7869
52ab56c2
PB		 7870 put_thumb_insn (globals, output_bfd, (bfd_vma) t2a2_noop_insn,
7871 s->contents + my_offset + 2);
252b5132
RH		 7872
7873 ret_offset =
9b485d32
NC		 7874 /* Address of destination of the stub. */
7875 ((bfd_signed_vma) val)
252b5132 7876 - ((bfd_signed_vma)
57e8b36a
NC		 7877 /* Offset from the start of the current section
7878 to the start of the stubs. */
9b485d32
NC		 7879 (s->output_offset
7880 /* Offset of the start of this stub from the start of the stubs. */
7881 + my_offset
7882 /* Address of the start of the current section. */
7883 + s->output_section->vma)
7884 /* The branch instruction is 4 bytes into the stub. */
7885 + 4
7886 /* ARM branches work from the pc of the instruction + 8. */
7887 + 8);
252b5132 7888
52ab56c2
PB		 7889 put_arm_insn (globals, output_bfd,
7890 (bfd_vma) t2a3_b_insn | ((ret_offset >> 2) & 0x00FFFFFF),
7891 s->contents + my_offset + 4);
252b5132
RH		 7892 }
7893
7894 BFD_ASSERT (my_offset <= globals->thumb_glue_size);
7895
427bfd90
NC		 7896 /* Now go back and fix up the original BL insn to point to here. */
7897 ret_offset =
7898 /* Address of where the stub is located. */
7899 (s->output_section->vma + s->output_offset + my_offset)
7900 /* Address of where the BL is located. */
57e8b36a
NC		 7901 - (input_section->output_section->vma + input_section->output_offset
7902 + offset)
427bfd90
NC		 7903 /* Addend in the relocation. */
7904 - addend
7905 /* Biassing for PC-relative addressing. */
7906 - 8;
252b5132 7907
12a0a0fd 7908 insert_thumb_branch (input_bfd, ret_offset, hit_data - input_section->vma);
252b5132 7909
b34976b6 7910 return TRUE;
252b5132
RH		 7911}
7912
a4fd1a8e 7913/* Populate an Arm to Thumb stub. Returns the stub symbol. */
9b485d32 7914
a4fd1a8e
PB		 7915static struct elf_link_hash_entry *
7916elf32_arm_create_thumb_stub (struct bfd_link_info * info,
7917 const char * name,
7918 bfd * input_bfd,
7919 bfd * output_bfd,
7920 asection * sym_sec,
7921 bfd_vma val,
8029a119
NC		 7922 asection * s,
7923 char ** error_message)
252b5132 7924{
dc810e39 7925 bfd_vma my_offset;
252b5132 7926 long int ret_offset;
bcbdc74c
NC		 7927 struct elf_link_hash_entry * myh;
7928 struct elf32_arm_link_hash_table * globals;
252b5132 7929
f2a9dd69 7930 myh = find_arm_glue (info, name, error_message);
252b5132 7931 if (myh == NULL)
a4fd1a8e 7932 return NULL;
252b5132
RH		 7933
7934 globals = elf32_arm_hash_table (info);
252b5132
RH		 7935 BFD_ASSERT (globals != NULL);
7936 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
7937
7938 my_offset = myh->root.u.def.value;
252b5132
RH		 7939
7940 if ((my_offset & 0x01) == 0x01)
7941 {
7942 if (sym_sec != NULL
7943 && sym_sec->owner != NULL
7944 && !INTERWORK_FLAG (sym_sec->owner))
7945 {
8f615d07 7946 (*_bfd_error_handler)
d003868e
AM		 7947 (_("%B(%s): warning: interworking not enabled.\n"
7948 " first occurrence: %B: arm call to thumb"),
7949 sym_sec->owner, input_bfd, name);
252b5132 7950 }
9b485d32 7951
252b5132
RH		 7952 --my_offset;
7953 myh->root.u.def.value = my_offset;
7954
0e1862bb
L		 7955 if (bfd_link_pic (info)
7956 || globals->root.is_relocatable_executable
27e55c4d 7957 || globals->pic_veneer)
8f6277f5
PB		 7958 {
7959 /* For relocatable objects we can't use absolute addresses,
7960 so construct the address from a relative offset. */
7961 /* TODO: If the offset is small it's probably worth
7962 constructing the address with adds. */
52ab56c2
PB		 7963 put_arm_insn (globals, output_bfd, (bfd_vma) a2t1p_ldr_insn,
7964 s->contents + my_offset);
7965 put_arm_insn (globals, output_bfd, (bfd_vma) a2t2p_add_pc_insn,
7966 s->contents + my_offset + 4);
7967 put_arm_insn (globals, output_bfd, (bfd_vma) a2t3p_bx_r12_insn,
7968 s->contents + my_offset + 8);
8f6277f5
PB		 7969 /* Adjust the offset by 4 for the position of the add,
7970 and 8 for the pipeline offset. */
7971 ret_offset = (val - (s->output_offset
7972 + s->output_section->vma
7973 + my_offset + 12))
7974 | 1;
7975 bfd_put_32 (output_bfd, ret_offset,
7976 s->contents + my_offset + 12);
7977 }
26079076
PB		 7978 else if (globals->use_blx)
7979 {
7980 put_arm_insn (globals, output_bfd, (bfd_vma) a2t1v5_ldr_insn,
7981 s->contents + my_offset);
7982
7983 /* It's a thumb address. Add the low order bit. */
7984 bfd_put_32 (output_bfd, val | a2t2v5_func_addr_insn,
7985 s->contents + my_offset + 4);
7986 }
8f6277f5
PB		 7987 else
7988 {
52ab56c2
PB		 7989 put_arm_insn (globals, output_bfd, (bfd_vma) a2t1_ldr_insn,
7990 s->contents + my_offset);
252b5132 7991
52ab56c2
PB		 7992 put_arm_insn (globals, output_bfd, (bfd_vma) a2t2_bx_r12_insn,
7993 s->contents + my_offset + 4);
252b5132 7994
8f6277f5
PB		 7995 /* It's a thumb address. Add the low order bit. */
7996 bfd_put_32 (output_bfd, val | a2t3_func_addr_insn,
7997 s->contents + my_offset + 8);
8029a119
NC		 7998
7999 my_offset += 12;
8f6277f5 8000 }
252b5132
RH		 8001 }
8002
8003 BFD_ASSERT (my_offset <= globals->arm_glue_size);
8004
a4fd1a8e
PB		 8005 return myh;
8006}
8007
8008/* Arm code calling a Thumb function. */
8009
8010static int
8011elf32_arm_to_thumb_stub (struct bfd_link_info * info,
8012 const char * name,
8013 bfd * input_bfd,
8014 bfd * output_bfd,
8015 asection * input_section,
8016 bfd_byte * hit_data,
8017 asection * sym_sec,
8018 bfd_vma offset,
8019 bfd_signed_vma addend,
f2a9dd69
DJ		 8020 bfd_vma val,
8021 char **error_message)
a4fd1a8e
PB		 8022{
8023 unsigned long int tmp;
8024 bfd_vma my_offset;
8025 asection * s;
8026 long int ret_offset;
8027 struct elf_link_hash_entry * myh;
8028 struct elf32_arm_link_hash_table * globals;
8029
8030 globals = elf32_arm_hash_table (info);
a4fd1a8e
PB		 8031 BFD_ASSERT (globals != NULL);
8032 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
8033
3d4d4302
AM		 8034 s = bfd_get_linker_section (globals->bfd_of_glue_owner,
8035 ARM2THUMB_GLUE_SECTION_NAME);
a4fd1a8e
PB		 8036 BFD_ASSERT (s != NULL);
8037 BFD_ASSERT (s->contents != NULL);
8038 BFD_ASSERT (s->output_section != NULL);
8039
8040 myh = elf32_arm_create_thumb_stub (info, name, input_bfd, output_bfd,
f2a9dd69 8041 sym_sec, val, s, error_message);
a4fd1a8e
PB		 8042 if (!myh)
8043 return FALSE;
8044
8045 my_offset = myh->root.u.def.value;
252b5132
RH		 8046 tmp = bfd_get_32 (input_bfd, hit_data);
8047 tmp = tmp & 0xFF000000;
8048
9b485d32 8049 /* Somehow these are both 4 too far, so subtract 8. */
dc810e39
AM		 8050 ret_offset = (s->output_offset
8051 + my_offset
8052 + s->output_section->vma
8053 - (input_section->output_offset
8054 + input_section->output_section->vma
8055 + offset + addend)
8056 - 8);
9a5aca8c 8057
252b5132
RH		 8058 tmp = tmp | ((ret_offset >> 2) & 0x00FFFFFF);
8059
dc810e39 8060 bfd_put_32 (output_bfd, (bfd_vma) tmp, hit_data - input_section->vma);
252b5132 8061
b34976b6 8062 return TRUE;
252b5132
RH		 8063}
8064
a4fd1a8e
PB		 8065/* Populate Arm stub for an exported Thumb function. */
8066
8067static bfd_boolean
8068elf32_arm_to_thumb_export_stub (struct elf_link_hash_entry *h, void * inf)
8069{
8070 struct bfd_link_info * info = (struct bfd_link_info *) inf;
8071 asection * s;
8072 struct elf_link_hash_entry * myh;
8073 struct elf32_arm_link_hash_entry *eh;
8074 struct elf32_arm_link_hash_table * globals;
8075 asection *sec;
8076 bfd_vma val;
f2a9dd69 8077 char *error_message;
a4fd1a8e 8078
906e58ca 8079 eh = elf32_arm_hash_entry (h);
a4fd1a8e
PB		 8080 /* Allocate stubs for exported Thumb functions on v4t. */
8081 if (eh->export_glue == NULL)
8082 return TRUE;
8083
8084 globals = elf32_arm_hash_table (info);
a4fd1a8e
PB		 8085 BFD_ASSERT (globals != NULL);
8086 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
8087
3d4d4302
AM		 8088 s = bfd_get_linker_section (globals->bfd_of_glue_owner,
8089 ARM2THUMB_GLUE_SECTION_NAME);
a4fd1a8e
PB		 8090 BFD_ASSERT (s != NULL);
8091 BFD_ASSERT (s->contents != NULL);
8092 BFD_ASSERT (s->output_section != NULL);
8093
8094 sec = eh->export_glue->root.u.def.section;
0eaedd0e
PB		 8095
8096 BFD_ASSERT (sec->output_section != NULL);
8097
a4fd1a8e
PB		 8098 val = eh->export_glue->root.u.def.value + sec->output_offset
8099 + sec->output_section->vma;
8029a119 8100
a4fd1a8e
PB		 8101 myh = elf32_arm_create_thumb_stub (info, h->root.root.string,
8102 h->root.u.def.section->owner,
f2a9dd69
DJ		 8103 globals->obfd, sec, val, s,
8104 &error_message);
a4fd1a8e
PB		 8105 BFD_ASSERT (myh);
8106 return TRUE;
8107}
8108
845b51d6
PB		 8109/* Populate ARMv4 BX veneers. Returns the absolute adress of the veneer. */
8110
8111static bfd_vma
8112elf32_arm_bx_glue (struct bfd_link_info * info, int reg)
8113{
8114 bfd_byte *p;
8115 bfd_vma glue_addr;
8116 asection *s;
8117 struct elf32_arm_link_hash_table *globals;
8118
8119 globals = elf32_arm_hash_table (info);
845b51d6
PB		 8120 BFD_ASSERT (globals != NULL);
8121 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
8122
3d4d4302
AM		 8123 s = bfd_get_linker_section (globals->bfd_of_glue_owner,
8124 ARM_BX_GLUE_SECTION_NAME);
845b51d6
PB		 8125 BFD_ASSERT (s != NULL);
8126 BFD_ASSERT (s->contents != NULL);
8127 BFD_ASSERT (s->output_section != NULL);
8128
8129 BFD_ASSERT (globals->bx_glue_offset[reg] & 2);
8130
8131 glue_addr = globals->bx_glue_offset[reg] & ~(bfd_vma)3;
8132
8133 if ((globals->bx_glue_offset[reg] & 1) == 0)
8134 {
8135 p = s->contents + glue_addr;
8136 bfd_put_32 (globals->obfd, armbx1_tst_insn + (reg << 16), p);
8137 bfd_put_32 (globals->obfd, armbx2_moveq_insn + reg, p + 4);
8138 bfd_put_32 (globals->obfd, armbx3_bx_insn + reg, p + 8);
8139 globals->bx_glue_offset[reg] |= 1;
8140 }
8141
8142 return glue_addr + s->output_section->vma + s->output_offset;
8143}
8144
a4fd1a8e
PB		 8145/* Generate Arm stubs for exported Thumb symbols. */
8146static void
906e58ca 8147elf32_arm_begin_write_processing (bfd *abfd ATTRIBUTE_UNUSED,
a4fd1a8e
PB		 8148 struct bfd_link_info *link_info)
8149{
8150 struct elf32_arm_link_hash_table * globals;
8151
8029a119
NC		 8152 if (link_info == NULL)
8153 /* Ignore this if we are not called by the ELF backend linker. */
a4fd1a8e
PB		 8154 return;
8155
8156 globals = elf32_arm_hash_table (link_info);
4dfe6ac6
NC		 8157 if (globals == NULL)
8158 return;
8159
84c08195
PB		 8160 /* If blx is available then exported Thumb symbols are OK and there is
8161 nothing to do. */
a4fd1a8e
PB		 8162 if (globals->use_blx)
8163 return;
8164
8165 elf_link_hash_traverse (&globals->root, elf32_arm_to_thumb_export_stub,
8166 link_info);
8167}
8168
47beaa6a
RS		 8169/* Reserve space for COUNT dynamic relocations in relocation selection
8170 SRELOC. */
8171
8172static void
8173elf32_arm_allocate_dynrelocs (struct bfd_link_info *info, asection *sreloc,
8174 bfd_size_type count)
8175{
8176 struct elf32_arm_link_hash_table *htab;
8177
8178 htab = elf32_arm_hash_table (info);
8179 BFD_ASSERT (htab->root.dynamic_sections_created);
8180 if (sreloc == NULL)
8181 abort ();
8182 sreloc->size += RELOC_SIZE (htab) * count;
8183}
8184
34e77a92
RS		 8185/* Reserve space for COUNT R_ARM_IRELATIVE relocations. If the link is
8186 dynamic, the relocations should go in SRELOC, otherwise they should
8187 go in the special .rel.iplt section. */
8188
8189static void
8190elf32_arm_allocate_irelocs (struct bfd_link_info *info, asection *sreloc,
8191 bfd_size_type count)
8192{
8193 struct elf32_arm_link_hash_table *htab;
8194
8195 htab = elf32_arm_hash_table (info);
8196 if (!htab->root.dynamic_sections_created)
8197 htab->root.irelplt->size += RELOC_SIZE (htab) * count;
8198 else
8199 {
8200 BFD_ASSERT (sreloc != NULL);
8201 sreloc->size += RELOC_SIZE (htab) * count;
8202 }
8203}
8204
47beaa6a
RS		 8205/* Add relocation REL to the end of relocation section SRELOC. */
8206
8207static void
8208elf32_arm_add_dynreloc (bfd *output_bfd, struct bfd_link_info *info,
8209 asection *sreloc, Elf_Internal_Rela *rel)
8210{
8211 bfd_byte *loc;
8212 struct elf32_arm_link_hash_table *htab;
8213
8214 htab = elf32_arm_hash_table (info);
34e77a92
RS		 8215 if (!htab->root.dynamic_sections_created
8216 && ELF32_R_TYPE (rel->r_info) == R_ARM_IRELATIVE)
8217 sreloc = htab->root.irelplt;
47beaa6a
RS		 8218 if (sreloc == NULL)
8219 abort ();
8220 loc = sreloc->contents;
8221 loc += sreloc->reloc_count++ * RELOC_SIZE (htab);
8222 if (sreloc->reloc_count * RELOC_SIZE (htab) > sreloc->size)
8223 abort ();
8224 SWAP_RELOC_OUT (htab) (output_bfd, rel, loc);
8225}
8226
34e77a92
RS		 8227/* Allocate room for a PLT entry described by ROOT_PLT and ARM_PLT.
8228 IS_IPLT_ENTRY says whether the entry belongs to .iplt rather than
8229 to .plt. */
8230
8231static void
8232elf32_arm_allocate_plt_entry (struct bfd_link_info *info,
8233 bfd_boolean is_iplt_entry,
8234 union gotplt_union *root_plt,
8235 struct arm_plt_info *arm_plt)
8236{
8237 struct elf32_arm_link_hash_table *htab;
8238 asection *splt;
8239 asection *sgotplt;
8240
8241 htab = elf32_arm_hash_table (info);
8242
8243 if (is_iplt_entry)
8244 {
8245 splt = htab->root.iplt;
8246 sgotplt = htab->root.igotplt;
8247
99059e56
RM		 8248 /* NaCl uses a special first entry in .iplt too. */
8249 if (htab->nacl_p && splt->size == 0)
8250 splt->size += htab->plt_header_size;
8251
34e77a92
RS		 8252 /* Allocate room for an R_ARM_IRELATIVE relocation in .rel.iplt. */
8253 elf32_arm_allocate_irelocs (info, htab->root.irelplt, 1);
8254 }
8255 else
8256 {
8257 splt = htab->root.splt;
8258 sgotplt = htab->root.sgotplt;
8259
8260 /* Allocate room for an R_JUMP_SLOT relocation in .rel.plt. */
8261 elf32_arm_allocate_dynrelocs (info, htab->root.srelplt, 1);
8262
8263 /* If this is the first .plt entry, make room for the special
8264 first entry. */
8265 if (splt->size == 0)
8266 splt->size += htab->plt_header_size;
9f19ab6d
WN		 8267
8268 htab->next_tls_desc_index++;
34e77a92
RS		 8269 }
8270
8271 /* Allocate the PLT entry itself, including any leading Thumb stub. */
8272 if (elf32_arm_plt_needs_thumb_stub_p (info, arm_plt))
8273 splt->size += PLT_THUMB_STUB_SIZE;
8274 root_plt->offset = splt->size;
8275 splt->size += htab->plt_entry_size;
8276
8277 if (!htab->symbian_p)
8278 {
8279 /* We also need to make an entry in the .got.plt section, which
8280 will be placed in the .got section by the linker script. */
9f19ab6d
WN		 8281 if (is_iplt_entry)
8282 arm_plt->got_offset = sgotplt->size;
8283 else
8284 arm_plt->got_offset = sgotplt->size - 8 * htab->num_tls_desc;
34e77a92
RS		 8285 sgotplt->size += 4;
8286 }
8287}
8288
b38cadfb
NC		 8289static bfd_vma
8290arm_movw_immediate (bfd_vma value)
8291{
8292 return (value & 0x00000fff) | ((value & 0x0000f000) << 4);
8293}
8294
8295static bfd_vma
8296arm_movt_immediate (bfd_vma value)
8297{
8298 return ((value & 0x0fff0000) >> 16) | ((value & 0xf0000000) >> 12);
8299}
8300
34e77a92
RS		 8301/* Fill in a PLT entry and its associated GOT slot. If DYNINDX == -1,
8302 the entry lives in .iplt and resolves to (*SYM_VALUE)().
8303 Otherwise, DYNINDX is the index of the symbol in the dynamic
8304 symbol table and SYM_VALUE is undefined.
8305
8306 ROOT_PLT points to the offset of the PLT entry from the start of its
8307 section (.iplt or .plt). ARM_PLT points to the symbol's ARM-specific
57460bcf 8308 bookkeeping information.
34e77a92 8309
57460bcf
NC		 8310 Returns FALSE if there was a problem. */
8311
8312static bfd_boolean
34e77a92
RS		 8313elf32_arm_populate_plt_entry (bfd *output_bfd, struct bfd_link_info *info,
8314 union gotplt_union *root_plt,
8315 struct arm_plt_info *arm_plt,
8316 int dynindx, bfd_vma sym_value)
8317{
8318 struct elf32_arm_link_hash_table *htab;
8319 asection *sgot;
8320 asection *splt;
8321 asection *srel;
8322 bfd_byte *loc;
8323 bfd_vma plt_index;
8324 Elf_Internal_Rela rel;
8325 bfd_vma plt_header_size;
8326 bfd_vma got_header_size;
8327
8328 htab = elf32_arm_hash_table (info);
8329
8330 /* Pick the appropriate sections and sizes. */
8331 if (dynindx == -1)
8332 {
8333 splt = htab->root.iplt;
8334 sgot = htab->root.igotplt;
8335 srel = htab->root.irelplt;
8336
8337 /* There are no reserved entries in .igot.plt, and no special
8338 first entry in .iplt. */
8339 got_header_size = 0;
8340 plt_header_size = 0;
8341 }
8342 else
8343 {
8344 splt = htab->root.splt;
8345 sgot = htab->root.sgotplt;
8346 srel = htab->root.srelplt;
8347
8348 got_header_size = get_elf_backend_data (output_bfd)->got_header_size;
8349 plt_header_size = htab->plt_header_size;
8350 }
8351 BFD_ASSERT (splt != NULL && srel != NULL);
8352
8353 /* Fill in the entry in the procedure linkage table. */
8354 if (htab->symbian_p)
8355 {
8356 BFD_ASSERT (dynindx >= 0);
8357 put_arm_insn (htab, output_bfd,
8358 elf32_arm_symbian_plt_entry[0],
8359 splt->contents + root_plt->offset);
8360 bfd_put_32 (output_bfd,
8361 elf32_arm_symbian_plt_entry[1],
8362 splt->contents + root_plt->offset + 4);
8363
8364 /* Fill in the entry in the .rel.plt section. */
8365 rel.r_offset = (splt->output_section->vma
8366 + splt->output_offset
8367 + root_plt->offset + 4);
8368 rel.r_info = ELF32_R_INFO (dynindx, R_ARM_GLOB_DAT);
8369
8370 /* Get the index in the procedure linkage table which
8371 corresponds to this symbol. This is the index of this symbol
8372 in all the symbols for which we are making plt entries. The
8373 first entry in the procedure linkage table is reserved. */
8374 plt_index = ((root_plt->offset - plt_header_size)
8375 / htab->plt_entry_size);
8376 }
8377 else
8378 {
8379 bfd_vma got_offset, got_address, plt_address;
8380 bfd_vma got_displacement, initial_got_entry;
8381 bfd_byte * ptr;
8382
8383 BFD_ASSERT (sgot != NULL);
8384
8385 /* Get the offset into the .(i)got.plt table of the entry that
8386 corresponds to this function. */
8387 got_offset = (arm_plt->got_offset & -2);
8388
8389 /* Get the index in the procedure linkage table which
8390 corresponds to this symbol. This is the index of this symbol
8391 in all the symbols for which we are making plt entries.
8392 After the reserved .got.plt entries, all symbols appear in
8393 the same order as in .plt. */
8394 plt_index = (got_offset - got_header_size) / 4;
8395
8396 /* Calculate the address of the GOT entry. */
8397 got_address = (sgot->output_section->vma
8398 + sgot->output_offset
8399 + got_offset);
8400
8401 /* ...and the address of the PLT entry. */
8402 plt_address = (splt->output_section->vma
8403 + splt->output_offset
8404 + root_plt->offset);
8405
8406 ptr = splt->contents + root_plt->offset;
0e1862bb 8407 if (htab->vxworks_p && bfd_link_pic (info))
34e77a92
RS		 8408 {
8409 unsigned int i;
8410 bfd_vma val;
8411
8412 for (i = 0; i != htab->plt_entry_size / 4; i++, ptr += 4)
8413 {
8414 val = elf32_arm_vxworks_shared_plt_entry[i];
8415 if (i == 2)
8416 val |= got_address - sgot->output_section->vma;
8417 if (i == 5)
8418 val |= plt_index * RELOC_SIZE (htab);
8419 if (i == 2 || i == 5)
8420 bfd_put_32 (output_bfd, val, ptr);
8421 else
8422 put_arm_insn (htab, output_bfd, val, ptr);
8423 }
8424 }
8425 else if (htab->vxworks_p)
8426 {
8427 unsigned int i;
8428 bfd_vma val;
8429
8430 for (i = 0; i != htab->plt_entry_size / 4; i++, ptr += 4)
8431 {
8432 val = elf32_arm_vxworks_exec_plt_entry[i];
8433 if (i == 2)
8434 val |= got_address;
8435 if (i == 4)
8436 val |= 0xffffff & -((root_plt->offset + i * 4 + 8) >> 2);
8437 if (i == 5)
8438 val |= plt_index * RELOC_SIZE (htab);
8439 if (i == 2 || i == 5)
8440 bfd_put_32 (output_bfd, val, ptr);
8441 else
8442 put_arm_insn (htab, output_bfd, val, ptr);
8443 }
8444
8445 loc = (htab->srelplt2->contents
8446 + (plt_index * 2 + 1) * RELOC_SIZE (htab));
8447
8448 /* Create the .rela.plt.unloaded R_ARM_ABS32 relocation
8449 referencing the GOT for this PLT entry. */
8450 rel.r_offset = plt_address + 8;
8451 rel.r_info = ELF32_R_INFO (htab->root.hgot->indx, R_ARM_ABS32);
8452 rel.r_addend = got_offset;
8453 SWAP_RELOC_OUT (htab) (output_bfd, &rel, loc);
8454 loc += RELOC_SIZE (htab);
8455
8456 /* Create the R_ARM_ABS32 relocation referencing the
8457 beginning of the PLT for this GOT entry. */
8458 rel.r_offset = got_address;
8459 rel.r_info = ELF32_R_INFO (htab->root.hplt->indx, R_ARM_ABS32);
8460 rel.r_addend = 0;
8461 SWAP_RELOC_OUT (htab) (output_bfd, &rel, loc);
8462 }
b38cadfb
NC		 8463 else if (htab->nacl_p)
8464 {
8465 /* Calculate the displacement between the PLT slot and the
8466 common tail that's part of the special initial PLT slot. */
6034aab8 8467 int32_t tail_displacement
b38cadfb
NC		 8468 = ((splt->output_section->vma + splt->output_offset
8469 + ARM_NACL_PLT_TAIL_OFFSET)
8470 - (plt_address + htab->plt_entry_size + 4));
8471 BFD_ASSERT ((tail_displacement & 3) == 0);
8472 tail_displacement >>= 2;
8473
8474 BFD_ASSERT ((tail_displacement & 0xff000000) == 0
8475 || (-tail_displacement & 0xff000000) == 0);
8476
8477 /* Calculate the displacement between the PLT slot and the entry
8478 in the GOT. The offset accounts for the value produced by
8479 adding to pc in the penultimate instruction of the PLT stub. */
6034aab8 8480 got_displacement = (got_address
99059e56 8481 - (plt_address + htab->plt_entry_size));
b38cadfb
NC		 8482
8483 /* NaCl does not support interworking at all. */
8484 BFD_ASSERT (!elf32_arm_plt_needs_thumb_stub_p (info, arm_plt));
8485
8486 put_arm_insn (htab, output_bfd,
8487 elf32_arm_nacl_plt_entry[0]
8488 | arm_movw_immediate (got_displacement),
8489 ptr + 0);
8490 put_arm_insn (htab, output_bfd,
8491 elf32_arm_nacl_plt_entry[1]
8492 | arm_movt_immediate (got_displacement),
8493 ptr + 4);
8494 put_arm_insn (htab, output_bfd,
8495 elf32_arm_nacl_plt_entry[2],
8496 ptr + 8);
8497 put_arm_insn (htab, output_bfd,
8498 elf32_arm_nacl_plt_entry[3]
8499 | (tail_displacement & 0x00ffffff),
8500 ptr + 12);
8501 }
57460bcf
NC		 8502 else if (using_thumb_only (htab))
8503 {
eed94f8f 8504 /* PR ld/16017: Generate thumb only PLT entries. */
469a3493 8505 if (!using_thumb2 (htab))
eed94f8f
NC		 8506 {
8507 /* FIXME: We ought to be able to generate thumb-1 PLT
8508 instructions... */
8509 _bfd_error_handler (_("%B: Warning: thumb-1 mode PLT generation not currently supported"),
8510 output_bfd);
8511 return FALSE;
8512 }
57460bcf 8513
eed94f8f
NC		 8514 /* Calculate the displacement between the PLT slot and the entry in
8515 the GOT. The 12-byte offset accounts for the value produced by
8516 adding to pc in the 3rd instruction of the PLT stub. */
8517 got_displacement = got_address - (plt_address + 12);
8518
8519 /* As we are using 32 bit instructions we have to use 'put_arm_insn'
8520 instead of 'put_thumb_insn'. */
8521 put_arm_insn (htab, output_bfd,
8522 elf32_thumb2_plt_entry[0]
8523 | ((got_displacement & 0x000000ff) << 16)
8524 | ((got_displacement & 0x00000700) << 20)
8525 | ((got_displacement & 0x00000800) >> 1)
8526 | ((got_displacement & 0x0000f000) >> 12),
8527 ptr + 0);
8528 put_arm_insn (htab, output_bfd,
8529 elf32_thumb2_plt_entry[1]
8530 | ((got_displacement & 0x00ff0000) )
8531 | ((got_displacement & 0x07000000) << 4)
8532 | ((got_displacement & 0x08000000) >> 17)
8533 | ((got_displacement & 0xf0000000) >> 28),
8534 ptr + 4);
8535 put_arm_insn (htab, output_bfd,
8536 elf32_thumb2_plt_entry[2],
8537 ptr + 8);
8538 put_arm_insn (htab, output_bfd,
8539 elf32_thumb2_plt_entry[3],
8540 ptr + 12);
57460bcf 8541 }
34e77a92
RS		 8542 else
8543 {
8544 /* Calculate the displacement between the PLT slot and the
8545 entry in the GOT. The eight-byte offset accounts for the
8546 value produced by adding to pc in the first instruction
8547 of the PLT stub. */
8548 got_displacement = got_address - (plt_address + 8);
8549
34e77a92
RS		 8550 if (elf32_arm_plt_needs_thumb_stub_p (info, arm_plt))
8551 {
8552 put_thumb_insn (htab, output_bfd,
8553 elf32_arm_plt_thumb_stub[0], ptr - 4);
8554 put_thumb_insn (htab, output_bfd,
8555 elf32_arm_plt_thumb_stub[1], ptr - 2);
8556 }
8557
1db37fe6
YG		 8558 if (!elf32_arm_use_long_plt_entry)
8559 {
8560 BFD_ASSERT ((got_displacement & 0xf0000000) == 0);
8561
8562 put_arm_insn (htab, output_bfd,
8563 elf32_arm_plt_entry_short[0]
8564 | ((got_displacement & 0x0ff00000) >> 20),
8565 ptr + 0);
8566 put_arm_insn (htab, output_bfd,
8567 elf32_arm_plt_entry_short[1]
8568 | ((got_displacement & 0x000ff000) >> 12),
8569 ptr+ 4);
8570 put_arm_insn (htab, output_bfd,
8571 elf32_arm_plt_entry_short[2]
8572 | (got_displacement & 0x00000fff),
8573 ptr + 8);
34e77a92 8574#ifdef FOUR_WORD_PLT
1db37fe6 8575 bfd_put_32 (output_bfd, elf32_arm_plt_entry_short[3], ptr + 12);
34e77a92 8576#endif
1db37fe6
YG		 8577 }
8578 else
8579 {
8580 put_arm_insn (htab, output_bfd,
8581 elf32_arm_plt_entry_long[0]
8582 | ((got_displacement & 0xf0000000) >> 28),
8583 ptr + 0);
8584 put_arm_insn (htab, output_bfd,
8585 elf32_arm_plt_entry_long[1]
8586 | ((got_displacement & 0x0ff00000) >> 20),
8587 ptr + 4);
8588 put_arm_insn (htab, output_bfd,
8589 elf32_arm_plt_entry_long[2]
8590 | ((got_displacement & 0x000ff000) >> 12),
8591 ptr+ 8);
8592 put_arm_insn (htab, output_bfd,
8593 elf32_arm_plt_entry_long[3]
8594 | (got_displacement & 0x00000fff),
8595 ptr + 12);
8596 }
34e77a92
RS		 8597 }
8598
8599 /* Fill in the entry in the .rel(a).(i)plt section. */
8600 rel.r_offset = got_address;
8601 rel.r_addend = 0;
8602 if (dynindx == -1)
8603 {
8604 /* .igot.plt entries use IRELATIVE relocations against SYM_VALUE.
8605 The dynamic linker or static executable then calls SYM_VALUE
8606 to determine the correct run-time value of the .igot.plt entry. */
8607 rel.r_info = ELF32_R_INFO (0, R_ARM_IRELATIVE);
8608 initial_got_entry = sym_value;
8609 }
8610 else
8611 {
8612 rel.r_info = ELF32_R_INFO (dynindx, R_ARM_JUMP_SLOT);
8613 initial_got_entry = (splt->output_section->vma
8614 + splt->output_offset);
8615 }
8616
8617 /* Fill in the entry in the global offset table. */
8618 bfd_put_32 (output_bfd, initial_got_entry,
8619 sgot->contents + got_offset);
8620 }
8621
aba8c3de
WN		 8622 if (dynindx == -1)
8623 elf32_arm_add_dynreloc (output_bfd, info, srel, &rel);
8624 else
8625 {
8626 loc = srel->contents + plt_index * RELOC_SIZE (htab);
8627 SWAP_RELOC_OUT (htab) (output_bfd, &rel, loc);
8628 }
57460bcf
NC		 8629
8630 return TRUE;
34e77a92
RS		 8631}
8632
eb043451
PB		 8633/* Some relocations map to different relocations depending on the
8634 target. Return the real relocation. */
8029a119 8635
eb043451
PB		 8636static int
8637arm_real_reloc_type (struct elf32_arm_link_hash_table * globals,
8638 int r_type)
8639{
8640 switch (r_type)
8641 {
8642 case R_ARM_TARGET1:
8643 if (globals->target1_is_rel)
8644 return R_ARM_REL32;
8645 else
8646 return R_ARM_ABS32;
8647
8648 case R_ARM_TARGET2:
8649 return globals->target2_reloc;
8650
8651 default:
8652 return r_type;
8653 }
8654}
eb043451 8655
ba93b8ac
DJ		 8656/* Return the base VMA address which should be subtracted from real addresses
8657 when resolving @dtpoff relocation.
8658 This is PT_TLS segment p_vaddr. */
8659
8660static bfd_vma
8661dtpoff_base (struct bfd_link_info *info)
8662{
8663 /* If tls_sec is NULL, we should have signalled an error already. */
8664 if (elf_hash_table (info)->tls_sec == NULL)
8665 return 0;
8666 return elf_hash_table (info)->tls_sec->vma;
8667}
8668
8669/* Return the relocation value for @tpoff relocation
8670 if STT_TLS virtual address is ADDRESS. */
8671
8672static bfd_vma
8673tpoff (struct bfd_link_info *info, bfd_vma address)
8674{
8675 struct elf_link_hash_table *htab = elf_hash_table (info);
8676 bfd_vma base;
8677
8678 /* If tls_sec is NULL, we should have signalled an error already. */
8679 if (htab->tls_sec == NULL)
8680 return 0;
8681 base = align_power ((bfd_vma) TCB_SIZE, htab->tls_sec->alignment_power);
8682 return address - htab->tls_sec->vma + base;
8683}
8684
00a97672
RS		 8685/* Perform an R_ARM_ABS12 relocation on the field pointed to by DATA.
8686 VALUE is the relocation value. */
8687
8688static bfd_reloc_status_type
8689elf32_arm_abs12_reloc (bfd *abfd, void *data, bfd_vma value)
8690{
8691 if (value > 0xfff)
8692 return bfd_reloc_overflow;
8693
8694 value |= bfd_get_32 (abfd, data) & 0xfffff000;
8695 bfd_put_32 (abfd, value, data);
8696 return bfd_reloc_ok;
8697}
8698
0855e32b
NS		 8699/* Handle TLS relaxations. Relaxing is possible for symbols that use
8700 R_ARM_GOTDESC, R_ARM_{,THM_}TLS_CALL or
8701 R_ARM_{,THM_}TLS_DESCSEQ relocations, during a static link.
8702
8703 Return bfd_reloc_ok if we're done, bfd_reloc_continue if the caller
8704 is to then call final_link_relocate. Return other values in the
62672b10
NS		 8705 case of error.
8706
8707 FIXME:When --emit-relocs is in effect, we'll emit relocs describing
8708 the pre-relaxed code. It would be nice if the relocs were updated
8709 to match the optimization. */
0855e32b 8710
b38cadfb 8711static bfd_reloc_status_type
0855e32b 8712elf32_arm_tls_relax (struct elf32_arm_link_hash_table *globals,
b38cadfb 8713 bfd *input_bfd, asection *input_sec, bfd_byte *contents,
0855e32b
NS		 8714 Elf_Internal_Rela *rel, unsigned long is_local)
8715{
8716 unsigned long insn;
b38cadfb 8717
0855e32b
NS		 8718 switch (ELF32_R_TYPE (rel->r_info))
8719 {
8720 default:
8721 return bfd_reloc_notsupported;
b38cadfb 8722
0855e32b
NS		 8723 case R_ARM_TLS_GOTDESC:
8724 if (is_local)
8725 insn = 0;
8726 else
8727 {
8728 insn = bfd_get_32 (input_bfd, contents + rel->r_offset);
8729 if (insn & 1)
8730 insn -= 5; /* THUMB */
8731 else
8732 insn -= 8; /* ARM */
8733 }
8734 bfd_put_32 (input_bfd, insn, contents + rel->r_offset);
8735 return bfd_reloc_continue;
8736
8737 case R_ARM_THM_TLS_DESCSEQ:
8738 /* Thumb insn. */
8739 insn = bfd_get_16 (input_bfd, contents + rel->r_offset);
8740 if ((insn & 0xff78) == 0x4478) /* add rx, pc */
8741 {
8742 if (is_local)
8743 /* nop */
8744 bfd_put_16 (input_bfd, 0x46c0, contents + rel->r_offset);
8745 }
8746 else if ((insn & 0xffc0) == 0x6840) /* ldr rx,[ry,#4] */
8747 {
8748 if (is_local)
8749 /* nop */
8750 bfd_put_16 (input_bfd, 0x46c0, contents + rel->r_offset);
8751 else
8752 /* ldr rx,[ry] */
8753 bfd_put_16 (input_bfd, insn & 0xf83f, contents + rel->r_offset);
8754 }
8755 else if ((insn & 0xff87) == 0x4780) /* blx rx */
8756 {
8757 if (is_local)
8758 /* nop */
8759 bfd_put_16 (input_bfd, 0x46c0, contents + rel->r_offset);
8760 else
8761 /* mov r0, rx */
8762 bfd_put_16 (input_bfd, 0x4600 | (insn & 0x78),
8763 contents + rel->r_offset);
8764 }
8765 else
8766 {
8767 if ((insn & 0xf000) == 0xf000 || (insn & 0xf800) == 0xe800)
8768 /* It's a 32 bit instruction, fetch the rest of it for
8769 error generation. */
8770 insn = (insn << 16)
8771 | bfd_get_16 (input_bfd, contents + rel->r_offset + 2);
8772 (*_bfd_error_handler)
8773 (_("%B(%A+0x%lx):unexpected Thumb instruction '0x%x' in TLS trampoline"),
8774 input_bfd, input_sec, (unsigned long)rel->r_offset, insn);
8775 return bfd_reloc_notsupported;
8776 }
8777 break;
b38cadfb 8778
0855e32b
NS		 8779 case R_ARM_TLS_DESCSEQ:
8780 /* arm insn. */
8781 insn = bfd_get_32 (input_bfd, contents + rel->r_offset);
8782 if ((insn & 0xffff0ff0) == 0xe08f0000) /* add rx,pc,ry */
8783 {
8784 if (is_local)
8785 /* mov rx, ry */
8786 bfd_put_32 (input_bfd, 0xe1a00000 | (insn & 0xffff),
8787 contents + rel->r_offset);
8788 }
8789 else if ((insn & 0xfff00fff) == 0xe5900004) /* ldr rx,[ry,#4]*/
8790 {
8791 if (is_local)
8792 /* nop */
8793 bfd_put_32 (input_bfd, 0xe1a00000, contents + rel->r_offset);
8794 else
8795 /* ldr rx,[ry] */
8796 bfd_put_32 (input_bfd, insn & 0xfffff000,
8797 contents + rel->r_offset);
8798 }
8799 else if ((insn & 0xfffffff0) == 0xe12fff30) /* blx rx */
8800 {
8801 if (is_local)
8802 /* nop */
8803 bfd_put_32 (input_bfd, 0xe1a00000, contents + rel->r_offset);
8804 else
8805 /* mov r0, rx */
8806 bfd_put_32 (input_bfd, 0xe1a00000 | (insn & 0xf),
8807 contents + rel->r_offset);
8808 }
8809 else
8810 {
8811 (*_bfd_error_handler)
8812 (_("%B(%A+0x%lx):unexpected ARM instruction '0x%x' in TLS trampoline"),
8813 input_bfd, input_sec, (unsigned long)rel->r_offset, insn);
8814 return bfd_reloc_notsupported;
8815 }
8816 break;
8817
8818 case R_ARM_TLS_CALL:
8819 /* GD->IE relaxation, turn the instruction into 'nop' or
8820 'ldr r0, [pc,r0]' */
8821 insn = is_local ? 0xe1a00000 : 0xe79f0000;
8822 bfd_put_32 (input_bfd, insn, contents + rel->r_offset);
8823 break;
b38cadfb 8824
0855e32b 8825 case R_ARM_THM_TLS_CALL:
6a631e86 8826 /* GD->IE relaxation. */
0855e32b
NS		 8827 if (!is_local)
8828 /* add r0,pc; ldr r0, [r0] */
8829 insn = 0x44786800;
8830 else if (arch_has_thumb2_nop (globals))
8831 /* nop.w */
8832 insn = 0xf3af8000;
8833 else
8834 /* nop; nop */
8835 insn = 0xbf00bf00;
b38cadfb 8836
0855e32b
NS		 8837 bfd_put_16 (input_bfd, insn >> 16, contents + rel->r_offset);
8838 bfd_put_16 (input_bfd, insn & 0xffff, contents + rel->r_offset + 2);
8839 break;
8840 }
8841 return bfd_reloc_ok;
8842}
8843
4962c51a
MS		 8844/* For a given value of n, calculate the value of G_n as required to
8845 deal with group relocations. We return it in the form of an
8846 encoded constant-and-rotation, together with the final residual. If n is
8847 specified as less than zero, then final_residual is filled with the
8848 input value and no further action is performed. */
8849
8850static bfd_vma
8851calculate_group_reloc_mask (bfd_vma value, int n, bfd_vma *final_residual)
8852{
8853 int current_n;
8854 bfd_vma g_n;
8855 bfd_vma encoded_g_n = 0;
8856 bfd_vma residual = value; /* Also known as Y_n. */
8857
8858 for (current_n = 0; current_n <= n; current_n++)
8859 {
8860 int shift;
8861
8862 /* Calculate which part of the value to mask. */
8863 if (residual == 0)
99059e56 8864 shift = 0;
4962c51a 8865 else
99059e56
RM		 8866 {
8867 int msb;
8868
8869 /* Determine the most significant bit in the residual and
8870 align the resulting value to a 2-bit boundary. */
8871 for (msb = 30; msb >= 0; msb -= 2)
8872 if (residual & (3 << msb))
8873 break;
8874
8875 /* The desired shift is now (msb - 6), or zero, whichever
8876 is the greater. */
8877 shift = msb - 6;
8878 if (shift < 0)
8879 shift = 0;
8880 }
4962c51a
MS		 8881
8882 /* Calculate g_n in 32-bit as well as encoded constant+rotation form. */
8883 g_n = residual & (0xff << shift);
8884 encoded_g_n = (g_n >> shift)
99059e56 8885 | ((g_n <= 0xff ? 0 : (32 - shift) / 2) << 8);
4962c51a
MS		 8886
8887 /* Calculate the residual for the next time around. */
8888 residual &= ~g_n;
8889 }
8890
8891 *final_residual = residual;
8892
8893 return encoded_g_n;
8894}
8895
8896/* Given an ARM instruction, determine whether it is an ADD or a SUB.
8897 Returns 1 if it is an ADD, -1 if it is a SUB, and 0 otherwise. */
906e58ca 8898
4962c51a 8899static int
906e58ca 8900identify_add_or_sub (bfd_vma insn)
4962c51a
MS		 8901{
8902 int opcode = insn & 0x1e00000;
8903
8904 if (opcode == 1 << 23) /* ADD */
8905 return 1;
8906
8907 if (opcode == 1 << 22) /* SUB */
8908 return -1;
8909
8910 return 0;
8911}
8912
252b5132 8913/* Perform a relocation as part of a final link. */
9b485d32 8914
252b5132 8915static bfd_reloc_status_type
57e8b36a
NC		 8916elf32_arm_final_link_relocate (reloc_howto_type * howto,
8917 bfd * input_bfd,
8918 bfd * output_bfd,
8919 asection * input_section,
8920 bfd_byte * contents,
8921 Elf_Internal_Rela * rel,
8922 bfd_vma value,
8923 struct bfd_link_info * info,
8924 asection * sym_sec,
8925 const char * sym_name,
34e77a92
RS		 8926 unsigned char st_type,
8927 enum arm_st_branch_type branch_type,
0945cdfd 8928 struct elf_link_hash_entry * h,
f2a9dd69 8929 bfd_boolean * unresolved_reloc_p,
8029a119 8930 char ** error_message)
252b5132
RH		 8931{
8932 unsigned long r_type = howto->type;
8933 unsigned long r_symndx;
8934 bfd_byte * hit_data = contents + rel->r_offset;
252b5132 8935 bfd_vma * local_got_offsets;
0855e32b 8936 bfd_vma * local_tlsdesc_gotents;
34e77a92
RS		 8937 asection * sgot;
8938 asection * splt;
252b5132 8939 asection * sreloc = NULL;
362d30a1 8940 asection * srelgot;
252b5132 8941 bfd_vma addend;
ba96a88f 8942 bfd_signed_vma signed_addend;
34e77a92
RS		 8943 unsigned char dynreloc_st_type;
8944 bfd_vma dynreloc_value;
ba96a88f 8945 struct elf32_arm_link_hash_table * globals;
34e77a92
RS		 8946 struct elf32_arm_link_hash_entry *eh;
8947 union gotplt_union *root_plt;
8948 struct arm_plt_info *arm_plt;
8949 bfd_vma plt_offset;
8950 bfd_vma gotplt_offset;
8951 bfd_boolean has_iplt_entry;
f21f3fe0 8952
9c504268 8953 globals = elf32_arm_hash_table (info);
4dfe6ac6
NC		 8954 if (globals == NULL)
8955 return bfd_reloc_notsupported;
9c504268 8956
0ffa91dd
NC		 8957 BFD_ASSERT (is_arm_elf (input_bfd));
8958
8959 /* Some relocation types map to different relocations depending on the
9c504268 8960 target. We pick the right one here. */
eb043451 8961 r_type = arm_real_reloc_type (globals, r_type);
0855e32b
NS		 8962
8963 /* It is possible to have linker relaxations on some TLS access
8964 models. Update our information here. */
8965 r_type = elf32_arm_tls_transition (info, r_type, h);
8966
eb043451
PB		 8967 if (r_type != howto->type)
8968 howto = elf32_arm_howto_from_type (r_type);
9c504268 8969
34e77a92 8970 eh = (struct elf32_arm_link_hash_entry *) h;
362d30a1 8971 sgot = globals->root.sgot;
252b5132 8972 local_got_offsets = elf_local_got_offsets (input_bfd);
0855e32b
NS		 8973 local_tlsdesc_gotents = elf32_arm_local_tlsdesc_gotent (input_bfd);
8974
34e77a92
RS		 8975 if (globals->root.dynamic_sections_created)
8976 srelgot = globals->root.srelgot;
8977 else
8978 srelgot = NULL;
8979
252b5132
RH		 8980 r_symndx = ELF32_R_SYM (rel->r_info);
8981
4e7fd91e 8982 if (globals->use_rel)
ba96a88f 8983 {
4e7fd91e
PB		 8984 addend = bfd_get_32 (input_bfd, hit_data) & howto->src_mask;
8985
8986 if (addend & ((howto->src_mask + 1) >> 1))
8987 {
8988 signed_addend = -1;
8989 signed_addend &= ~ howto->src_mask;
8990 signed_addend |= addend;
8991 }
8992 else
8993 signed_addend = addend;
ba96a88f
NC		 8994 }
8995 else
4e7fd91e 8996 addend = signed_addend = rel->r_addend;
f21f3fe0 8997
39f21624
NC		 8998 /* ST_BRANCH_TO_ARM is nonsense to thumb-only targets when we
8999 are resolving a function call relocation. */
9000 if (using_thumb_only (globals)
9001 && (r_type == R_ARM_THM_CALL
9002 || r_type == R_ARM_THM_JUMP24)
9003 && branch_type == ST_BRANCH_TO_ARM)
9004 branch_type = ST_BRANCH_TO_THUMB;
9005
34e77a92
RS		 9006 /* Record the symbol information that should be used in dynamic
9007 relocations. */
9008 dynreloc_st_type = st_type;
9009 dynreloc_value = value;
9010 if (branch_type == ST_BRANCH_TO_THUMB)
9011 dynreloc_value |= 1;
9012
9013 /* Find out whether the symbol has a PLT. Set ST_VALUE, BRANCH_TYPE and
9014 VALUE appropriately for relocations that we resolve at link time. */
9015 has_iplt_entry = FALSE;
9016 if (elf32_arm_get_plt_info (input_bfd, eh, r_symndx, &root_plt, &arm_plt)
9017 && root_plt->offset != (bfd_vma) -1)
9018 {
9019 plt_offset = root_plt->offset;
9020 gotplt_offset = arm_plt->got_offset;
9021
9022 if (h == NULL || eh->is_iplt)
9023 {
9024 has_iplt_entry = TRUE;
9025 splt = globals->root.iplt;
9026
9027 /* Populate .iplt entries here, because not all of them will
9028 be seen by finish_dynamic_symbol. The lower bit is set if
9029 we have already populated the entry. */
9030 if (plt_offset & 1)
9031 plt_offset--;
9032 else
9033 {
57460bcf
NC		 9034 if (elf32_arm_populate_plt_entry (output_bfd, info, root_plt, arm_plt,
9035 -1, dynreloc_value))
9036 root_plt->offset |= 1;
9037 else
9038 return bfd_reloc_notsupported;
34e77a92
RS		 9039 }
9040
9041 /* Static relocations always resolve to the .iplt entry. */
9042 st_type = STT_FUNC;
9043 value = (splt->output_section->vma
9044 + splt->output_offset
9045 + plt_offset);
9046 branch_type = ST_BRANCH_TO_ARM;
9047
9048 /* If there are non-call relocations that resolve to the .iplt
9049 entry, then all dynamic ones must too. */
9050 if (arm_plt->noncall_refcount != 0)
9051 {
9052 dynreloc_st_type = st_type;
9053 dynreloc_value = value;
9054 }
9055 }
9056 else
9057 /* We populate the .plt entry in finish_dynamic_symbol. */
9058 splt = globals->root.splt;
9059 }
9060 else
9061 {
9062 splt = NULL;
9063 plt_offset = (bfd_vma) -1;
9064 gotplt_offset = (bfd_vma) -1;
9065 }
9066
252b5132
RH		 9067 switch (r_type)
9068 {
9069 case R_ARM_NONE:
28a094c2
DJ		 9070 /* We don't need to find a value for this symbol. It's just a
9071 marker. */
9072 *unresolved_reloc_p = FALSE;
252b5132
RH		 9073 return bfd_reloc_ok;
9074
00a97672
RS		 9075 case R_ARM_ABS12:
9076 if (!globals->vxworks_p)
9077 return elf32_arm_abs12_reloc (input_bfd, hit_data, value + addend);
9078
252b5132
RH		 9079 case R_ARM_PC24:
9080 case R_ARM_ABS32:
bb224fc3 9081 case R_ARM_ABS32_NOI:
252b5132 9082 case R_ARM_REL32:
bb224fc3 9083 case R_ARM_REL32_NOI:
5b5bb741
PB		 9084 case R_ARM_CALL:
9085 case R_ARM_JUMP24:
dfc5f959 9086 case R_ARM_XPC25:
eb043451 9087 case R_ARM_PREL31:
7359ea65 9088 case R_ARM_PLT32:
7359ea65
DJ		 9089 /* Handle relocations which should use the PLT entry. ABS32/REL32
9090 will use the symbol's value, which may point to a PLT entry, but we
9091 don't need to handle that here. If we created a PLT entry, all
5fa9e92f
CL		 9092 branches in this object should go to it, except if the PLT is too
9093 far away, in which case a long branch stub should be inserted. */
bb224fc3 9094 if ((r_type != R_ARM_ABS32 && r_type != R_ARM_REL32
99059e56 9095 && r_type != R_ARM_ABS32_NOI && r_type != R_ARM_REL32_NOI
155d87d7
CL		 9096 && r_type != R_ARM_CALL
9097 && r_type != R_ARM_JUMP24
9098 && r_type != R_ARM_PLT32)
34e77a92 9099 && plt_offset != (bfd_vma) -1)
7359ea65 9100 {
34e77a92
RS		 9101 /* If we've created a .plt section, and assigned a PLT entry
9102 to this function, it must either be a STT_GNU_IFUNC reference
9103 or not be known to bind locally. In other cases, we should
9104 have cleared the PLT entry by now. */
9105 BFD_ASSERT (has_iplt_entry || !SYMBOL_CALLS_LOCAL (info, h));
7359ea65
DJ		 9106
9107 value = (splt->output_section->vma
9108 + splt->output_offset
34e77a92 9109 + plt_offset);
0945cdfd 9110 *unresolved_reloc_p = FALSE;
7359ea65
DJ		 9111 return _bfd_final_link_relocate (howto, input_bfd, input_section,
9112 contents, rel->r_offset, value,
00a97672 9113 rel->r_addend);
7359ea65
DJ		 9114 }
9115
67687978
PB		 9116 /* When generating a shared object or relocatable executable, these
9117 relocations are copied into the output file to be resolved at
9118 run time. */
0e1862bb
L		 9119 if ((bfd_link_pic (info)
9120 || globals->root.is_relocatable_executable)
7359ea65 9121 && (input_section->flags & SEC_ALLOC)
4dfe6ac6 9122 && !(globals->vxworks_p
3348747a
NS		 9123 && strcmp (input_section->output_section->name,
9124 ".tls_vars") == 0)
bb224fc3 9125 && ((r_type != R_ARM_REL32 && r_type != R_ARM_REL32_NOI)
ee06dc07 9126 || !SYMBOL_CALLS_LOCAL (info, h))
ca6b5f82
AM		 9127 && !(input_bfd == globals->stub_bfd
9128 && strstr (input_section->name, STUB_SUFFIX))
7359ea65
DJ		 9129 && (h == NULL
9130 || ELF_ST_VISIBILITY (h->other) == STV_DEFAULT
9131 || h->root.type != bfd_link_hash_undefweak)
9132 && r_type != R_ARM_PC24
5b5bb741
PB		 9133 && r_type != R_ARM_CALL
9134 && r_type != R_ARM_JUMP24
ee06dc07 9135 && r_type != R_ARM_PREL31
7359ea65 9136 && r_type != R_ARM_PLT32)
252b5132 9137 {
947216bf 9138 Elf_Internal_Rela outrel;
b34976b6 9139 bfd_boolean skip, relocate;
f21f3fe0 9140
52db4ec2
JW		 9141 if ((r_type == R_ARM_REL32 || r_type == R_ARM_REL32_NOI)
9142 && !h->def_regular)
9143 {
9144 char *v = _("shared object");
9145
0e1862bb 9146 if (bfd_link_executable (info))
52db4ec2
JW		 9147 v = _("PIE executable");
9148
9149 (*_bfd_error_handler)
9150 (_("%B: relocation %s against external or undefined symbol `%s'"
9151 " can not be used when making a %s; recompile with -fPIC"), input_bfd,
9152 elf32_arm_howto_table_1[r_type].name, h->root.root.string, v);
9153 return bfd_reloc_notsupported;
9154 }
9155
0945cdfd
DJ		 9156 *unresolved_reloc_p = FALSE;
9157
34e77a92 9158 if (sreloc == NULL && globals->root.dynamic_sections_created)
252b5132 9159 {
83bac4b0
NC		 9160 sreloc = _bfd_elf_get_dynamic_reloc_section (input_bfd, input_section,
9161 ! globals->use_rel);
f21f3fe0 9162
83bac4b0 9163 if (sreloc == NULL)
252b5132 9164 return bfd_reloc_notsupported;
252b5132 9165 }
f21f3fe0 9166
b34976b6
AM		 9167 skip = FALSE;
9168 relocate = FALSE;
f21f3fe0 9169
00a97672 9170 outrel.r_addend = addend;
c629eae0
JJ		 9171 outrel.r_offset =
9172 _bfd_elf_section_offset (output_bfd, info, input_section,
9173 rel->r_offset);
9174 if (outrel.r_offset == (bfd_vma) -1)
b34976b6 9175 skip = TRUE;
0bb2d96a 9176 else if (outrel.r_offset == (bfd_vma) -2)
b34976b6 9177 skip = TRUE, relocate = TRUE;
252b5132
RH		 9178 outrel.r_offset += (input_section->output_section->vma
9179 + input_section->output_offset);
f21f3fe0 9180
252b5132 9181 if (skip)
0bb2d96a 9182 memset (&outrel, 0, sizeof outrel);
5e681ec4
PB		 9183 else if (h != NULL
9184 && h->dynindx != -1
0e1862bb 9185 && (!bfd_link_pic (info)
a496fbc8 9186 || !SYMBOLIC_BIND (info, h)
f5385ebf 9187 || !h->def_regular))
5e681ec4 9188 outrel.r_info = ELF32_R_INFO (h->dynindx, r_type);
252b5132
RH		 9189 else
9190 {
a16385dc
MM		 9191 int symbol;
9192
5e681ec4 9193 /* This symbol is local, or marked to become local. */
34e77a92 9194 BFD_ASSERT (r_type == R_ARM_ABS32 || r_type == R_ARM_ABS32_NOI);
a16385dc 9195 if (globals->symbian_p)
6366ff1e 9196 {
74541ad4
AM		 9197 asection *osec;
9198
6366ff1e
MM		 9199 /* On Symbian OS, the data segment and text segement
9200 can be relocated independently. Therefore, we
9201 must indicate the segment to which this
9202 relocation is relative. The BPABI allows us to
9203 use any symbol in the right segment; we just use
9204 the section symbol as it is convenient. (We
9205 cannot use the symbol given by "h" directly as it
74541ad4
AM		 9206 will not appear in the dynamic symbol table.)
9207
9208 Note that the dynamic linker ignores the section
9209 symbol value, so we don't subtract osec->vma
9210 from the emitted reloc addend. */
10dbd1f3 9211 if (sym_sec)
74541ad4 9212 osec = sym_sec->output_section;
10dbd1f3 9213 else
74541ad4
AM		 9214 osec = input_section->output_section;
9215 symbol = elf_section_data (osec)->dynindx;
9216 if (symbol == 0)
9217 {
9218 struct elf_link_hash_table *htab = elf_hash_table (info);
9219
9220 if ((osec->flags & SEC_READONLY) == 0
9221 && htab->data_index_section != NULL)
9222 osec = htab->data_index_section;
9223 else
9224 osec = htab->text_index_section;
9225 symbol = elf_section_data (osec)->dynindx;
9226 }
6366ff1e
MM		 9227 BFD_ASSERT (symbol != 0);
9228 }
a16385dc
MM		 9229 else
9230 /* On SVR4-ish systems, the dynamic loader cannot
9231 relocate the text and data segments independently,
9232 so the symbol does not matter. */
9233 symbol = 0;
34e77a92
RS		 9234 if (dynreloc_st_type == STT_GNU_IFUNC)
9235 /* We have an STT_GNU_IFUNC symbol that doesn't resolve
9236 to the .iplt entry. Instead, every non-call reference
9237 must use an R_ARM_IRELATIVE relocation to obtain the
9238 correct run-time address. */
9239 outrel.r_info = ELF32_R_INFO (symbol, R_ARM_IRELATIVE);
9240 else
9241 outrel.r_info = ELF32_R_INFO (symbol, R_ARM_RELATIVE);
00a97672
RS		 9242 if (globals->use_rel)
9243 relocate = TRUE;
9244 else
34e77a92 9245 outrel.r_addend += dynreloc_value;
252b5132 9246 }
f21f3fe0 9247
47beaa6a 9248 elf32_arm_add_dynreloc (output_bfd, info, sreloc, &outrel);
9a5aca8c 9249
f21f3fe0 9250 /* If this reloc is against an external symbol, we do not want to
252b5132 9251 fiddle with the addend. Otherwise, we need to include the symbol
9b485d32 9252 value so that it becomes an addend for the dynamic reloc. */
252b5132
RH		 9253 if (! relocate)
9254 return bfd_reloc_ok;
9a5aca8c 9255
f21f3fe0 9256 return _bfd_final_link_relocate (howto, input_bfd, input_section,
34e77a92
RS		 9257 contents, rel->r_offset,
9258 dynreloc_value, (bfd_vma) 0);
252b5132
RH		 9259 }
9260 else switch (r_type)
9261 {
00a97672
RS		 9262 case R_ARM_ABS12:
9263 return elf32_arm_abs12_reloc (input_bfd, hit_data, value + addend);
9264
dfc5f959 9265 case R_ARM_XPC25: /* Arm BLX instruction. */
5b5bb741
PB		 9266 case R_ARM_CALL:
9267 case R_ARM_JUMP24:
8029a119 9268 case R_ARM_PC24: /* Arm B/BL instruction. */
7359ea65 9269 case R_ARM_PLT32:
906e58ca 9270 {
906e58ca
NC		 9271 struct elf32_arm_stub_hash_entry *stub_entry = NULL;
9272
dfc5f959 9273 if (r_type == R_ARM_XPC25)
252b5132 9274 {
dfc5f959
NC		 9275 /* Check for Arm calling Arm function. */
9276 /* FIXME: Should we translate the instruction into a BL
9277 instruction instead ? */
35fc36a8 9278 if (branch_type != ST_BRANCH_TO_THUMB)
d003868e
AM		 9279 (*_bfd_error_handler)
9280 (_("\%B: Warning: Arm BLX instruction targets Arm function '%s'."),
9281 input_bfd,
9282 h ? h->root.root.string : "(local)");
dfc5f959 9283 }
155d87d7 9284 else if (r_type == R_ARM_PC24)
dfc5f959
NC		 9285 {
9286 /* Check for Arm calling Thumb function. */
35fc36a8 9287 if (branch_type == ST_BRANCH_TO_THUMB)
dfc5f959 9288 {
f2a9dd69
DJ		 9289 if (elf32_arm_to_thumb_stub (info, sym_name, input_bfd,
9290 output_bfd, input_section,
9291 hit_data, sym_sec, rel->r_offset,
9292 signed_addend, value,
9293 error_message))
9294 return bfd_reloc_ok;
9295 else
9296 return bfd_reloc_dangerous;
dfc5f959 9297 }
252b5132 9298 }
ba96a88f 9299
906e58ca 9300 /* Check if a stub has to be inserted because the
8029a119 9301 destination is too far or we are changing mode. */
155d87d7
CL		 9302 if ( r_type == R_ARM_CALL
9303 || r_type == R_ARM_JUMP24
9304 || r_type == R_ARM_PLT32)
906e58ca 9305 {
fe33d2fa
CL		 9306 enum elf32_arm_stub_type stub_type = arm_stub_none;
9307 struct elf32_arm_link_hash_entry *hash;
9308
9309 hash = (struct elf32_arm_link_hash_entry *) h;
9310 stub_type = arm_type_of_stub (info, input_section, rel,
34e77a92
RS		 9311 st_type, &branch_type,
9312 hash, value, sym_sec,
fe33d2fa 9313 input_bfd, sym_name);
5fa9e92f 9314
fe33d2fa 9315 if (stub_type != arm_stub_none)
906e58ca
NC		 9316 {
9317 /* The target is out of reach, so redirect the
9318 branch to the local stub for this function. */
906e58ca
NC		 9319 stub_entry = elf32_arm_get_stub_entry (input_section,
9320 sym_sec, h,
fe33d2fa
CL		 9321 rel, globals,
9322 stub_type);
9cd3e4e5
NC		 9323 {
9324 if (stub_entry != NULL)
9325 value = (stub_entry->stub_offset
9326 + stub_entry->stub_sec->output_offset
9327 + stub_entry->stub_sec->output_section->vma);
9328
9329 if (plt_offset != (bfd_vma) -1)
9330 *unresolved_reloc_p = FALSE;
9331 }
906e58ca 9332 }
fe33d2fa
CL		 9333 else
9334 {
9335 /* If the call goes through a PLT entry, make sure to
9336 check distance to the right destination address. */
34e77a92 9337 if (plt_offset != (bfd_vma) -1)
fe33d2fa
CL		 9338 {
9339 value = (splt->output_section->vma
9340 + splt->output_offset
34e77a92 9341 + plt_offset);
fe33d2fa
CL		 9342 *unresolved_reloc_p = FALSE;
9343 /* The PLT entry is in ARM mode, regardless of the
9344 target function. */
35fc36a8 9345 branch_type = ST_BRANCH_TO_ARM;
fe33d2fa
CL		 9346 }
9347 }
906e58ca
NC		 9348 }
9349
dea514f5
PB		 9350 /* The ARM ELF ABI says that this reloc is computed as: S - P + A
9351 where:
9352 S is the address of the symbol in the relocation.
9353 P is address of the instruction being relocated.
9354 A is the addend (extracted from the instruction) in bytes.
9355
9356 S is held in 'value'.
9357 P is the base address of the section containing the
9358 instruction plus the offset of the reloc into that
9359 section, ie:
9360 (input_section->output_section->vma +
9361 input_section->output_offset +
9362 rel->r_offset).
9363 A is the addend, converted into bytes, ie:
9364 (signed_addend * 4)
9365
9366 Note: None of these operations have knowledge of the pipeline
9367 size of the processor, thus it is up to the assembler to
9368 encode this information into the addend. */
9369 value -= (input_section->output_section->vma
9370 + input_section->output_offset);
9371 value -= rel->r_offset;
4e7fd91e
PB		 9372 if (globals->use_rel)
9373 value += (signed_addend << howto->size);
9374 else
9375 /* RELA addends do not have to be adjusted by howto->size. */
9376 value += signed_addend;
23080146 9377
dcb5e6e6
NC		 9378 signed_addend = value;
9379 signed_addend >>= howto->rightshift;
9a5aca8c 9380
5ab79981 9381 /* A branch to an undefined weak symbol is turned into a jump to
ffcb4889 9382 the next instruction unless a PLT entry will be created.
77b4f08f 9383 Do the same for local undefined symbols (but not for STN_UNDEF).
cd1dac3d
DG		 9384 The jump to the next instruction is optimized as a NOP depending
9385 on the architecture. */
ffcb4889 9386 if (h ? (h->root.type == bfd_link_hash_undefweak
34e77a92 9387 && plt_offset == (bfd_vma) -1)
77b4f08f 9388 : r_symndx != STN_UNDEF && bfd_is_und_section (sym_sec))
5ab79981 9389 {
cd1dac3d
DG		 9390 value = (bfd_get_32 (input_bfd, hit_data) & 0xf0000000);
9391
9392 if (arch_has_arm_nop (globals))
9393 value |= 0x0320f000;
9394 else
9395 value |= 0x01a00000; /* Using pre-UAL nop: mov r0, r0. */
5ab79981
PB		 9396 }
9397 else
59f2c4e7 9398 {
9b485d32 9399 /* Perform a signed range check. */
dcb5e6e6 9400 if ( signed_addend > ((bfd_signed_vma) (howto->dst_mask >> 1))
59f2c4e7
NC		 9401 || signed_addend < - ((bfd_signed_vma) ((howto->dst_mask + 1) >> 1)))
9402 return bfd_reloc_overflow;
9a5aca8c 9403
5ab79981 9404 addend = (value & 2);
39b41c9c 9405
5ab79981
PB		 9406 value = (signed_addend & howto->dst_mask)
9407 | (bfd_get_32 (input_bfd, hit_data) & (~ howto->dst_mask));
39b41c9c 9408
5ab79981
PB		 9409 if (r_type == R_ARM_CALL)
9410 {
155d87d7 9411 /* Set the H bit in the BLX instruction. */
35fc36a8 9412 if (branch_type == ST_BRANCH_TO_THUMB)
155d87d7
CL		 9413 {
9414 if (addend)
9415 value |= (1 << 24);
9416 else
9417 value &= ~(bfd_vma)(1 << 24);
9418 }
9419
5ab79981 9420 /* Select the correct instruction (BL or BLX). */
906e58ca 9421 /* Only if we are not handling a BL to a stub. In this
8029a119 9422 case, mode switching is performed by the stub. */
35fc36a8 9423 if (branch_type == ST_BRANCH_TO_THUMB && !stub_entry)
5ab79981 9424 value |= (1 << 28);
63e1a0fc 9425 else if (stub_entry || branch_type != ST_BRANCH_UNKNOWN)
5ab79981
PB		 9426 {
9427 value &= ~(bfd_vma)(1 << 28);
9428 value |= (1 << 24);
9429 }
39b41c9c
PB		 9430 }
9431 }
906e58ca 9432 }
252b5132 9433 break;
f21f3fe0 9434
252b5132
RH		 9435 case R_ARM_ABS32:
9436 value += addend;
35fc36a8 9437 if (branch_type == ST_BRANCH_TO_THUMB)
252b5132
RH		 9438 value |= 1;
9439 break;
f21f3fe0 9440
bb224fc3
MS		 9441 case R_ARM_ABS32_NOI:
9442 value += addend;
9443 break;
9444
252b5132 9445 case R_ARM_REL32:
a8bc6c78 9446 value += addend;
35fc36a8 9447 if (branch_type == ST_BRANCH_TO_THUMB)
a8bc6c78 9448 value |= 1;
252b5132 9449 value -= (input_section->output_section->vma
62efb346 9450 + input_section->output_offset + rel->r_offset);
252b5132 9451 break;
eb043451 9452
bb224fc3
MS		 9453 case R_ARM_REL32_NOI:
9454 value += addend;
9455 value -= (input_section->output_section->vma
9456 + input_section->output_offset + rel->r_offset);
9457 break;
9458
eb043451
PB		 9459 case R_ARM_PREL31:
9460 value -= (input_section->output_section->vma
9461 + input_section->output_offset + rel->r_offset);
9462 value += signed_addend;
9463 if (! h || h->root.type != bfd_link_hash_undefweak)
9464 {
8029a119 9465 /* Check for overflow. */
eb043451
PB		 9466 if ((value ^ (value >> 1)) & (1 << 30))
9467 return bfd_reloc_overflow;
9468 }
9469 value &= 0x7fffffff;
9470 value |= (bfd_get_32 (input_bfd, hit_data) & 0x80000000);
35fc36a8 9471 if (branch_type == ST_BRANCH_TO_THUMB)
eb043451
PB		 9472 value |= 1;
9473 break;
252b5132 9474 }
f21f3fe0 9475
252b5132
RH		 9476 bfd_put_32 (input_bfd, value, hit_data);
9477 return bfd_reloc_ok;
9478
9479 case R_ARM_ABS8:
fd0fd00c
MJ		 9480 /* PR 16202: Refectch the addend using the correct size. */
9481 if (globals->use_rel)
9482 addend = bfd_get_8 (input_bfd, hit_data);
252b5132 9483 value += addend;
4e67d4ca
DG		 9484
9485 /* There is no way to tell whether the user intended to use a signed or
9486 unsigned addend. When checking for overflow we accept either,
9487 as specified by the AAELF. */
9488 if ((long) value > 0xff || (long) value < -0x80)
252b5132
RH		 9489 return bfd_reloc_overflow;
9490
9491 bfd_put_8 (input_bfd, value, hit_data);
9492 return bfd_reloc_ok;
9493
9494 case R_ARM_ABS16:
fd0fd00c
MJ		 9495 /* PR 16202: Refectch the addend using the correct size. */
9496 if (globals->use_rel)
9497 addend = bfd_get_16 (input_bfd, hit_data);
252b5132
RH		 9498 value += addend;
9499
4e67d4ca
DG		 9500 /* See comment for R_ARM_ABS8. */
9501 if ((long) value > 0xffff || (long) value < -0x8000)
252b5132
RH		 9502 return bfd_reloc_overflow;
9503
9504 bfd_put_16 (input_bfd, value, hit_data);
9505 return bfd_reloc_ok;
9506
252b5132 9507 case R_ARM_THM_ABS5:
9b485d32 9508 /* Support ldr and str instructions for the thumb. */
4e7fd91e
PB		 9509 if (globals->use_rel)
9510 {
9511 /* Need to refetch addend. */
9512 addend = bfd_get_16 (input_bfd, hit_data) & howto->src_mask;
9513 /* ??? Need to determine shift amount from operand size. */
9514 addend >>= howto->rightshift;
9515 }
252b5132
RH		 9516 value += addend;
9517
9518 /* ??? Isn't value unsigned? */
9519 if ((long) value > 0x1f || (long) value < -0x10)
9520 return bfd_reloc_overflow;
9521
9522 /* ??? Value needs to be properly shifted into place first. */
9523 value |= bfd_get_16 (input_bfd, hit_data) & 0xf83f;
9524 bfd_put_16 (input_bfd, value, hit_data);
9525 return bfd_reloc_ok;
9526
2cab6cc3
MS		 9527 case R_ARM_THM_ALU_PREL_11_0:
9528 /* Corresponds to: addw.w reg, pc, #offset (and similarly for subw). */
9529 {
9530 bfd_vma insn;
9531 bfd_signed_vma relocation;
9532
9533 insn = (bfd_get_16 (input_bfd, hit_data) << 16)
99059e56 9534 | bfd_get_16 (input_bfd, hit_data + 2);
2cab6cc3 9535
99059e56
RM		 9536 if (globals->use_rel)
9537 {
9538 signed_addend = (insn & 0xff) | ((insn & 0x7000) >> 4)
9539 | ((insn & (1 << 26)) >> 15);
9540 if (insn & 0xf00000)
9541 signed_addend = -signed_addend;
9542 }
2cab6cc3
MS		 9543
9544 relocation = value + signed_addend;
79f08007 9545 relocation -= Pa (input_section->output_section->vma
99059e56
RM		 9546 + input_section->output_offset
9547 + rel->r_offset);
2cab6cc3 9548
b6518b38 9549 value = relocation;
2cab6cc3 9550
99059e56
RM		 9551 if (value >= 0x1000)
9552 return bfd_reloc_overflow;
2cab6cc3
MS		 9553
9554 insn = (insn & 0xfb0f8f00) | (value & 0xff)
99059e56
RM		 9555 | ((value & 0x700) << 4)
9556 | ((value & 0x800) << 15);
9557 if (relocation < 0)
9558 insn |= 0xa00000;
2cab6cc3
MS		 9559
9560 bfd_put_16 (input_bfd, insn >> 16, hit_data);
9561 bfd_put_16 (input_bfd, insn & 0xffff, hit_data + 2);
9562
99059e56 9563 return bfd_reloc_ok;
2cab6cc3
MS		 9564 }
9565
e1ec24c6
NC		 9566 case R_ARM_THM_PC8:
9567 /* PR 10073: This reloc is not generated by the GNU toolchain,
9568 but it is supported for compatibility with third party libraries
9569 generated by other compilers, specifically the ARM/IAR. */
9570 {
9571 bfd_vma insn;
9572 bfd_signed_vma relocation;
9573
9574 insn = bfd_get_16 (input_bfd, hit_data);
9575
99059e56 9576 if (globals->use_rel)
79f08007 9577 addend = ((((insn & 0x00ff) << 2) + 4) & 0x3ff) -4;
e1ec24c6
NC		 9578
9579 relocation = value + addend;
79f08007 9580 relocation -= Pa (input_section->output_section->vma
99059e56
RM		 9581 + input_section->output_offset
9582 + rel->r_offset);
e1ec24c6 9583
b6518b38 9584 value = relocation;
e1ec24c6
NC		 9585
9586 /* We do not check for overflow of this reloc. Although strictly
9587 speaking this is incorrect, it appears to be necessary in order
9588 to work with IAR generated relocs. Since GCC and GAS do not
9589 generate R_ARM_THM_PC8 relocs, the lack of a check should not be
9590 a problem for them. */
9591 value &= 0x3fc;
9592
9593 insn = (insn & 0xff00) | (value >> 2);
9594
9595 bfd_put_16 (input_bfd, insn, hit_data);
9596
99059e56 9597 return bfd_reloc_ok;
e1ec24c6
NC		 9598 }
9599
2cab6cc3
MS		 9600 case R_ARM_THM_PC12:
9601 /* Corresponds to: ldr.w reg, [pc, #offset]. */
9602 {
9603 bfd_vma insn;
9604 bfd_signed_vma relocation;
9605
9606 insn = (bfd_get_16 (input_bfd, hit_data) << 16)
99059e56 9607 | bfd_get_16 (input_bfd, hit_data + 2);
2cab6cc3 9608
99059e56
RM		 9609 if (globals->use_rel)
9610 {
9611 signed_addend = insn & 0xfff;
9612 if (!(insn & (1 << 23)))
9613 signed_addend = -signed_addend;
9614 }
2cab6cc3
MS		 9615
9616 relocation = value + signed_addend;
79f08007 9617 relocation -= Pa (input_section->output_section->vma
99059e56
RM		 9618 + input_section->output_offset
9619 + rel->r_offset);
2cab6cc3 9620
b6518b38 9621 value = relocation;
2cab6cc3 9622
99059e56
RM		 9623 if (value >= 0x1000)
9624 return bfd_reloc_overflow;
2cab6cc3
MS		 9625
9626 insn = (insn & 0xff7ff000) | value;
99059e56
RM		 9627 if (relocation >= 0)
9628 insn |= (1 << 23);
2cab6cc3
MS		 9629
9630 bfd_put_16 (input_bfd, insn >> 16, hit_data);
9631 bfd_put_16 (input_bfd, insn & 0xffff, hit_data + 2);
9632
99059e56 9633 return bfd_reloc_ok;
2cab6cc3
MS		 9634 }
9635
dfc5f959 9636 case R_ARM_THM_XPC22:
c19d1205 9637 case R_ARM_THM_CALL:
bd97cb95 9638 case R_ARM_THM_JUMP24:
dfc5f959 9639 /* Thumb BL (branch long instruction). */
252b5132 9640 {
b34976b6 9641 bfd_vma relocation;
99059e56 9642 bfd_vma reloc_sign;
b34976b6
AM		 9643 bfd_boolean overflow = FALSE;
9644 bfd_vma upper_insn = bfd_get_16 (input_bfd, hit_data);
9645 bfd_vma lower_insn = bfd_get_16 (input_bfd, hit_data + 2);
e95de063
MS		 9646 bfd_signed_vma reloc_signed_max;
9647 bfd_signed_vma reloc_signed_min;
b34976b6 9648 bfd_vma check;
252b5132 9649 bfd_signed_vma signed_check;
e95de063 9650 int bitsize;
cd1dac3d 9651 const int thumb2 = using_thumb2 (globals);
252b5132 9652
5ab79981 9653 /* A branch to an undefined weak symbol is turned into a jump to
cd1dac3d
DG		 9654 the next instruction unless a PLT entry will be created.
9655 The jump to the next instruction is optimized as a NOP.W for
9656 Thumb-2 enabled architectures. */
19540007 9657 if (h && h->root.type == bfd_link_hash_undefweak
34e77a92 9658 && plt_offset == (bfd_vma) -1)
5ab79981 9659 {
cd1dac3d
DG		 9660 if (arch_has_thumb2_nop (globals))
9661 {
9662 bfd_put_16 (input_bfd, 0xf3af, hit_data);
9663 bfd_put_16 (input_bfd, 0x8000, hit_data + 2);
9664 }
9665 else
9666 {
9667 bfd_put_16 (input_bfd, 0xe000, hit_data);
9668 bfd_put_16 (input_bfd, 0xbf00, hit_data + 2);
9669 }
5ab79981
PB		 9670 return bfd_reloc_ok;
9671 }
9672
e95de063 9673 /* Fetch the addend. We use the Thumb-2 encoding (backwards compatible
99059e56 9674 with Thumb-1) involving the J1 and J2 bits. */
4e7fd91e
PB		 9675 if (globals->use_rel)
9676 {
99059e56
RM		 9677 bfd_vma s = (upper_insn & (1 << 10)) >> 10;
9678 bfd_vma upper = upper_insn & 0x3ff;
9679 bfd_vma lower = lower_insn & 0x7ff;
e95de063
MS		 9680 bfd_vma j1 = (lower_insn & (1 << 13)) >> 13;
9681 bfd_vma j2 = (lower_insn & (1 << 11)) >> 11;
99059e56
RM		 9682 bfd_vma i1 = j1 ^ s ? 0 : 1;
9683 bfd_vma i2 = j2 ^ s ? 0 : 1;
e95de063 9684
99059e56
RM		 9685 addend = (i1 << 23) | (i2 << 22) | (upper << 12) | (lower << 1);
9686 /* Sign extend. */
9687 addend = (addend | ((s ? 0 : 1) << 24)) - (1 << 24);
e95de063 9688
4e7fd91e
PB		 9689 signed_addend = addend;
9690 }
cb1afa5c 9691
dfc5f959
NC		 9692 if (r_type == R_ARM_THM_XPC22)
9693 {
9694 /* Check for Thumb to Thumb call. */
9695 /* FIXME: Should we translate the instruction into a BL
9696 instruction instead ? */
35fc36a8 9697 if (branch_type == ST_BRANCH_TO_THUMB)
d003868e
AM		 9698 (*_bfd_error_handler)
9699 (_("%B: Warning: Thumb BLX instruction targets thumb function '%s'."),
9700 input_bfd,
9701 h ? h->root.root.string : "(local)");
dfc5f959
NC		 9702 }
9703 else
252b5132 9704 {
dfc5f959
NC		 9705 /* If it is not a call to Thumb, assume call to Arm.
9706 If it is a call relative to a section name, then it is not a
b7693d02
DJ		 9707 function call at all, but rather a long jump. Calls through
9708 the PLT do not require stubs. */
34e77a92 9709 if (branch_type == ST_BRANCH_TO_ARM && plt_offset == (bfd_vma) -1)
dfc5f959 9710 {
bd97cb95 9711 if (globals->use_blx && r_type == R_ARM_THM_CALL)
39b41c9c
PB		 9712 {
9713 /* Convert BL to BLX. */
9714 lower_insn = (lower_insn & ~0x1000) | 0x0800;
9715 }
155d87d7
CL		 9716 else if (( r_type != R_ARM_THM_CALL)
9717 && (r_type != R_ARM_THM_JUMP24))
8029a119
NC		 9718 {
9719 if (elf32_thumb_to_arm_stub
9720 (info, sym_name, input_bfd, output_bfd, input_section,
9721 hit_data, sym_sec, rel->r_offset, signed_addend, value,
9722 error_message))
9723 return bfd_reloc_ok;
9724 else
9725 return bfd_reloc_dangerous;
9726 }
da5938a2 9727 }
35fc36a8
RS		 9728 else if (branch_type == ST_BRANCH_TO_THUMB
9729 && globals->use_blx
bd97cb95 9730 && r_type == R_ARM_THM_CALL)
39b41c9c
PB		 9731 {
9732 /* Make sure this is a BL. */
9733 lower_insn |= 0x1800;
9734 }
252b5132 9735 }
f21f3fe0 9736
fe33d2fa 9737 enum elf32_arm_stub_type stub_type = arm_stub_none;
155d87d7 9738 if (r_type == R_ARM_THM_CALL || r_type == R_ARM_THM_JUMP24)
906e58ca
NC		 9739 {
9740 /* Check if a stub has to be inserted because the destination
8029a119 9741 is too far. */
fe33d2fa
CL		 9742 struct elf32_arm_stub_hash_entry *stub_entry;
9743 struct elf32_arm_link_hash_entry *hash;
9744
9745 hash = (struct elf32_arm_link_hash_entry *) h;
9746
9747 stub_type = arm_type_of_stub (info, input_section, rel,
34e77a92
RS		 9748 st_type, &branch_type,
9749 hash, value, sym_sec,
fe33d2fa
CL		 9750 input_bfd, sym_name);
9751
9752 if (stub_type != arm_stub_none)
906e58ca
NC		 9753 {
9754 /* The target is out of reach or we are changing modes, so
9755 redirect the branch to the local stub for this
9756 function. */
9757 stub_entry = elf32_arm_get_stub_entry (input_section,
9758 sym_sec, h,
fe33d2fa
CL		 9759 rel, globals,
9760 stub_type);
906e58ca 9761 if (stub_entry != NULL)
9cd3e4e5
NC		 9762 {
9763 value = (stub_entry->stub_offset
9764 + stub_entry->stub_sec->output_offset
9765 + stub_entry->stub_sec->output_section->vma);
9766
9767 if (plt_offset != (bfd_vma) -1)
9768 *unresolved_reloc_p = FALSE;
9769 }
906e58ca 9770
f4ac8484 9771 /* If this call becomes a call to Arm, force BLX. */
155d87d7 9772 if (globals->use_blx && (r_type == R_ARM_THM_CALL))
f4ac8484
DJ		 9773 {
9774 if ((stub_entry
9775 && !arm_stub_is_thumb (stub_entry->stub_type))
35fc36a8 9776 || branch_type != ST_BRANCH_TO_THUMB)
f4ac8484
DJ		 9777 lower_insn = (lower_insn & ~0x1000) | 0x0800;
9778 }
906e58ca
NC		 9779 }
9780 }
9781
fe33d2fa 9782 /* Handle calls via the PLT. */
34e77a92 9783 if (stub_type == arm_stub_none && plt_offset != (bfd_vma) -1)
fe33d2fa
CL		 9784 {
9785 value = (splt->output_section->vma
9786 + splt->output_offset
34e77a92 9787 + plt_offset);
fe33d2fa 9788
eed94f8f
NC		 9789 if (globals->use_blx
9790 && r_type == R_ARM_THM_CALL
9791 && ! using_thumb_only (globals))
fe33d2fa
CL		 9792 {
9793 /* If the Thumb BLX instruction is available, convert
9794 the BL to a BLX instruction to call the ARM-mode
9795 PLT entry. */
9796 lower_insn = (lower_insn & ~0x1000) | 0x0800;
35fc36a8 9797 branch_type = ST_BRANCH_TO_ARM;
fe33d2fa
CL		 9798 }
9799 else
9800 {
eed94f8f
NC		 9801 if (! using_thumb_only (globals))
9802 /* Target the Thumb stub before the ARM PLT entry. */
9803 value -= PLT_THUMB_STUB_SIZE;
35fc36a8 9804 branch_type = ST_BRANCH_TO_THUMB;
fe33d2fa
CL		 9805 }
9806 *unresolved_reloc_p = FALSE;
9807 }
9808
ba96a88f 9809 relocation = value + signed_addend;
f21f3fe0 9810
252b5132 9811 relocation -= (input_section->output_section->vma
ba96a88f
NC		 9812 + input_section->output_offset
9813 + rel->r_offset);
9a5aca8c 9814
252b5132
RH		 9815 check = relocation >> howto->rightshift;
9816
9817 /* If this is a signed value, the rightshift just dropped
9818 leading 1 bits (assuming twos complement). */
9819 if ((bfd_signed_vma) relocation >= 0)
9820 signed_check = check;
9821 else
9822 signed_check = check | ~((bfd_vma) -1 >> howto->rightshift);
9823
e95de063
MS		 9824 /* Calculate the permissable maximum and minimum values for
9825 this relocation according to whether we're relocating for
9826 Thumb-2 or not. */
9827 bitsize = howto->bitsize;
9828 if (!thumb2)
9829 bitsize -= 2;
f6ebfac0 9830 reloc_signed_max = (1 << (bitsize - 1)) - 1;
e95de063
MS		 9831 reloc_signed_min = ~reloc_signed_max;
9832
252b5132 9833 /* Assumes two's complement. */
ba96a88f 9834 if (signed_check > reloc_signed_max || signed_check < reloc_signed_min)
b34976b6 9835 overflow = TRUE;
252b5132 9836
bd97cb95 9837 if ((lower_insn & 0x5000) == 0x4000)
c62e1cc3
NC		 9838 /* For a BLX instruction, make sure that the relocation is rounded up
9839 to a word boundary. This follows the semantics of the instruction
9840 which specifies that bit 1 of the target address will come from bit
9841 1 of the base address. */
9842 relocation = (relocation + 2) & ~ 3;
cb1afa5c 9843
e95de063
MS		 9844 /* Put RELOCATION back into the insn. Assumes two's complement.
9845 We use the Thumb-2 encoding, which is safe even if dealing with
9846 a Thumb-1 instruction by virtue of our overflow check above. */
99059e56 9847 reloc_sign = (signed_check < 0) ? 1 : 0;
e95de063 9848 upper_insn = (upper_insn & ~(bfd_vma) 0x7ff)
99059e56
RM		 9849 | ((relocation >> 12) & 0x3ff)
9850 | (reloc_sign << 10);
906e58ca 9851 lower_insn = (lower_insn & ~(bfd_vma) 0x2fff)
99059e56
RM		 9852 | (((!((relocation >> 23) & 1)) ^ reloc_sign) << 13)
9853 | (((!((relocation >> 22) & 1)) ^ reloc_sign) << 11)
9854 | ((relocation >> 1) & 0x7ff);
c62e1cc3 9855
252b5132
RH		 9856 /* Put the relocated value back in the object file: */
9857 bfd_put_16 (input_bfd, upper_insn, hit_data);
9858 bfd_put_16 (input_bfd, lower_insn, hit_data + 2);
9859
9860 return (overflow ? bfd_reloc_overflow : bfd_reloc_ok);
9861 }
9862 break;
9863
c19d1205
ZW		 9864 case R_ARM_THM_JUMP19:
9865 /* Thumb32 conditional branch instruction. */
9866 {
9867 bfd_vma relocation;
9868 bfd_boolean overflow = FALSE;
9869 bfd_vma upper_insn = bfd_get_16 (input_bfd, hit_data);
9870 bfd_vma lower_insn = bfd_get_16 (input_bfd, hit_data + 2);
a00a1f35
MS		 9871 bfd_signed_vma reloc_signed_max = 0xffffe;
9872 bfd_signed_vma reloc_signed_min = -0x100000;
c19d1205 9873 bfd_signed_vma signed_check;
c5423981
TG		 9874 enum elf32_arm_stub_type stub_type = arm_stub_none;
9875 struct elf32_arm_stub_hash_entry *stub_entry;
9876 struct elf32_arm_link_hash_entry *hash;
c19d1205
ZW		 9877
9878 /* Need to refetch the addend, reconstruct the top three bits,
9879 and squish the two 11 bit pieces together. */
9880 if (globals->use_rel)
9881 {
9882 bfd_vma S = (upper_insn & 0x0400) >> 10;
a00a1f35 9883 bfd_vma upper = (upper_insn & 0x003f);
c19d1205
ZW		 9884 bfd_vma J1 = (lower_insn & 0x2000) >> 13;
9885 bfd_vma J2 = (lower_insn & 0x0800) >> 11;
9886 bfd_vma lower = (lower_insn & 0x07ff);
9887
a00a1f35
MS		 9888 upper |= J1 << 6;
9889 upper |= J2 << 7;
9890 upper |= (!S) << 8;
c19d1205
ZW		 9891 upper -= 0x0100; /* Sign extend. */
9892
9893 addend = (upper << 12) | (lower << 1);
9894 signed_addend = addend;
9895 }
9896
bd97cb95 9897 /* Handle calls via the PLT. */
34e77a92 9898 if (plt_offset != (bfd_vma) -1)
bd97cb95
DJ		 9899 {
9900 value = (splt->output_section->vma
9901 + splt->output_offset
34e77a92 9902 + plt_offset);
bd97cb95
DJ		 9903 /* Target the Thumb stub before the ARM PLT entry. */
9904 value -= PLT_THUMB_STUB_SIZE;
9905 *unresolved_reloc_p = FALSE;
9906 }
9907
c5423981
TG		 9908 hash = (struct elf32_arm_link_hash_entry *)h;
9909
9910 stub_type = arm_type_of_stub (info, input_section, rel,
9911 st_type, &branch_type,
9912 hash, value, sym_sec,
9913 input_bfd, sym_name);
9914 if (stub_type != arm_stub_none)
9915 {
9916 stub_entry = elf32_arm_get_stub_entry (input_section,
9917 sym_sec, h,
9918 rel, globals,
9919 stub_type);
9920 if (stub_entry != NULL)
9921 {
9922 value = (stub_entry->stub_offset
9923 + stub_entry->stub_sec->output_offset
9924 + stub_entry->stub_sec->output_section->vma);
9925 }
9926 }
c19d1205 9927
99059e56 9928 relocation = value + signed_addend;
c19d1205
ZW		 9929 relocation -= (input_section->output_section->vma
9930 + input_section->output_offset
9931 + rel->r_offset);
a00a1f35 9932 signed_check = (bfd_signed_vma) relocation;
c19d1205 9933
c19d1205
ZW		 9934 if (signed_check > reloc_signed_max || signed_check < reloc_signed_min)
9935 overflow = TRUE;
9936
9937 /* Put RELOCATION back into the insn. */
9938 {
9939 bfd_vma S = (relocation & 0x00100000) >> 20;
9940 bfd_vma J2 = (relocation & 0x00080000) >> 19;
9941 bfd_vma J1 = (relocation & 0x00040000) >> 18;
9942 bfd_vma hi = (relocation & 0x0003f000) >> 12;
9943 bfd_vma lo = (relocation & 0x00000ffe) >> 1;
9944
a00a1f35 9945 upper_insn = (upper_insn & 0xfbc0) | (S << 10) | hi;
c19d1205
ZW		 9946 lower_insn = (lower_insn & 0xd000) | (J1 << 13) | (J2 << 11) | lo;
9947 }
9948
9949 /* Put the relocated value back in the object file: */
9950 bfd_put_16 (input_bfd, upper_insn, hit_data);
9951 bfd_put_16 (input_bfd, lower_insn, hit_data + 2);
9952
9953 return (overflow ? bfd_reloc_overflow : bfd_reloc_ok);
9954 }
9955
9956 case R_ARM_THM_JUMP11:
9957 case R_ARM_THM_JUMP8:
9958 case R_ARM_THM_JUMP6:
51c5503b
NC		 9959 /* Thumb B (branch) instruction). */
9960 {
6cf9e9fe 9961 bfd_signed_vma relocation;
51c5503b
NC		 9962 bfd_signed_vma reloc_signed_max = (1 << (howto->bitsize - 1)) - 1;
9963 bfd_signed_vma reloc_signed_min = ~ reloc_signed_max;
51c5503b
NC		 9964 bfd_signed_vma signed_check;
9965
c19d1205
ZW		 9966 /* CZB cannot jump backward. */
9967 if (r_type == R_ARM_THM_JUMP6)
9968 reloc_signed_min = 0;
9969
4e7fd91e 9970 if (globals->use_rel)
6cf9e9fe 9971 {
4e7fd91e
PB		 9972 /* Need to refetch addend. */
9973 addend = bfd_get_16 (input_bfd, hit_data) & howto->src_mask;
9974 if (addend & ((howto->src_mask + 1) >> 1))
9975 {
9976 signed_addend = -1;
9977 signed_addend &= ~ howto->src_mask;
9978 signed_addend |= addend;
9979 }
9980 else
9981 signed_addend = addend;
9982 /* The value in the insn has been right shifted. We need to
9983 undo this, so that we can perform the address calculation
9984 in terms of bytes. */
9985 signed_addend <<= howto->rightshift;
6cf9e9fe 9986 }
6cf9e9fe 9987 relocation = value + signed_addend;
51c5503b
NC		 9988
9989 relocation -= (input_section->output_section->vma
9990 + input_section->output_offset
9991 + rel->r_offset);
9992
6cf9e9fe
NC		 9993 relocation >>= howto->rightshift;
9994 signed_check = relocation;
c19d1205
ZW		 9995
9996 if (r_type == R_ARM_THM_JUMP6)
9997 relocation = ((relocation & 0x0020) << 4) | ((relocation & 0x001f) << 3);
9998 else
9999 relocation &= howto->dst_mask;
51c5503b 10000 relocation |= (bfd_get_16 (input_bfd, hit_data) & (~ howto->dst_mask));
cedb70c5 10001
51c5503b
NC		 10002 bfd_put_16 (input_bfd, relocation, hit_data);
10003
10004 /* Assumes two's complement. */
10005 if (signed_check > reloc_signed_max || signed_check < reloc_signed_min)
10006 return bfd_reloc_overflow;
10007
10008 return bfd_reloc_ok;
10009 }
cedb70c5 10010
8375c36b
PB		 10011 case R_ARM_ALU_PCREL7_0:
10012 case R_ARM_ALU_PCREL15_8:
10013 case R_ARM_ALU_PCREL23_15:
10014 {
10015 bfd_vma insn;
10016 bfd_vma relocation;
10017
10018 insn = bfd_get_32 (input_bfd, hit_data);
4e7fd91e
PB		 10019 if (globals->use_rel)
10020 {
10021 /* Extract the addend. */
10022 addend = (insn & 0xff) << ((insn & 0xf00) >> 7);
10023 signed_addend = addend;
10024 }
8375c36b
PB		 10025 relocation = value + signed_addend;
10026
10027 relocation -= (input_section->output_section->vma
10028 + input_section->output_offset
10029 + rel->r_offset);
10030 insn = (insn & ~0xfff)
10031 | ((howto->bitpos << 7) & 0xf00)
10032 | ((relocation >> howto->bitpos) & 0xff);
10033 bfd_put_32 (input_bfd, value, hit_data);
10034 }
10035 return bfd_reloc_ok;
10036
252b5132
RH		 10037 case R_ARM_GNU_VTINHERIT:
10038 case R_ARM_GNU_VTENTRY:
10039 return bfd_reloc_ok;
10040
c19d1205 10041 case R_ARM_GOTOFF32:
252b5132 10042 /* Relocation is relative to the start of the
99059e56 10043 global offset table. */
252b5132
RH		 10044
10045 BFD_ASSERT (sgot != NULL);
10046 if (sgot == NULL)
99059e56 10047 return bfd_reloc_notsupported;
9a5aca8c 10048
cedb70c5 10049 /* If we are addressing a Thumb function, we need to adjust the
ee29b9fb
RE		 10050 address by one, so that attempts to call the function pointer will
10051 correctly interpret it as Thumb code. */
35fc36a8 10052 if (branch_type == ST_BRANCH_TO_THUMB)
ee29b9fb
RE		 10053 value += 1;
10054
252b5132 10055 /* Note that sgot->output_offset is not involved in this
99059e56
RM		 10056 calculation. We always want the start of .got. If we
10057 define _GLOBAL_OFFSET_TABLE in a different way, as is
10058 permitted by the ABI, we might have to change this
10059 calculation. */
252b5132 10060 value -= sgot->output_section->vma;
f21f3fe0 10061 return _bfd_final_link_relocate (howto, input_bfd, input_section,
99e4ae17 10062 contents, rel->r_offset, value,
00a97672 10063 rel->r_addend);
252b5132
RH		 10064
10065 case R_ARM_GOTPC:
a7c10850 10066 /* Use global offset table as symbol value. */
252b5132 10067 BFD_ASSERT (sgot != NULL);
f21f3fe0 10068
252b5132 10069 if (sgot == NULL)
99059e56 10070 return bfd_reloc_notsupported;
252b5132 10071
0945cdfd 10072 *unresolved_reloc_p = FALSE;
252b5132 10073 value = sgot->output_section->vma;
f21f3fe0 10074 return _bfd_final_link_relocate (howto, input_bfd, input_section,
99e4ae17 10075 contents, rel->r_offset, value,
00a97672 10076 rel->r_addend);
f21f3fe0 10077
252b5132 10078 case R_ARM_GOT32:
eb043451 10079 case R_ARM_GOT_PREL:
252b5132 10080 /* Relocation is to the entry for this symbol in the
99059e56 10081 global offset table. */
252b5132
RH		 10082 if (sgot == NULL)
10083 return bfd_reloc_notsupported;
f21f3fe0 10084
34e77a92
RS		 10085 if (dynreloc_st_type == STT_GNU_IFUNC
10086 && plt_offset != (bfd_vma) -1
10087 && (h == NULL || SYMBOL_REFERENCES_LOCAL (info, h)))
10088 {
10089 /* We have a relocation against a locally-binding STT_GNU_IFUNC
10090 symbol, and the relocation resolves directly to the runtime
10091 target rather than to the .iplt entry. This means that any
10092 .got entry would be the same value as the .igot.plt entry,
10093 so there's no point creating both. */
10094 sgot = globals->root.igotplt;
10095 value = sgot->output_offset + gotplt_offset;
10096 }
10097 else if (h != NULL)
252b5132
RH		 10098 {
10099 bfd_vma off;
f21f3fe0 10100
252b5132
RH		 10101 off = h->got.offset;
10102 BFD_ASSERT (off != (bfd_vma) -1);
b436d854 10103 if ((off & 1) != 0)
252b5132 10104 {
b436d854
RS		 10105 /* We have already processsed one GOT relocation against
10106 this symbol. */
10107 off &= ~1;
10108 if (globals->root.dynamic_sections_created
10109 && !SYMBOL_REFERENCES_LOCAL (info, h))
10110 *unresolved_reloc_p = FALSE;
10111 }
10112 else
10113 {
10114 Elf_Internal_Rela outrel;
10115
6f820c85 10116 if (h->dynindx != -1 && !SYMBOL_REFERENCES_LOCAL (info, h))
b436d854
RS		 10117 {
10118 /* If the symbol doesn't resolve locally in a static
10119 object, we have an undefined reference. If the
10120 symbol doesn't resolve locally in a dynamic object,
10121 it should be resolved by the dynamic linker. */
10122 if (globals->root.dynamic_sections_created)
10123 {
10124 outrel.r_info = ELF32_R_INFO (h->dynindx, R_ARM_GLOB_DAT);
10125 *unresolved_reloc_p = FALSE;
10126 }
10127 else
10128 outrel.r_info = 0;
10129 outrel.r_addend = 0;
10130 }
252b5132
RH		 10131 else
10132 {
34e77a92 10133 if (dynreloc_st_type == STT_GNU_IFUNC)
99059e56 10134 outrel.r_info = ELF32_R_INFO (0, R_ARM_IRELATIVE);
0e1862bb 10135 else if (bfd_link_pic (info) &&
31943882
WN		 10136 (ELF_ST_VISIBILITY (h->other) == STV_DEFAULT
10137 || h->root.type != bfd_link_hash_undefweak))
99059e56
RM		 10138 outrel.r_info = ELF32_R_INFO (0, R_ARM_RELATIVE);
10139 else
10140 outrel.r_info = 0;
34e77a92 10141 outrel.r_addend = dynreloc_value;
b436d854 10142 }
ee29b9fb 10143
b436d854
RS		 10144 /* The GOT entry is initialized to zero by default.
10145 See if we should install a different value. */
10146 if (outrel.r_addend != 0
10147 && (outrel.r_info == 0 || globals->use_rel))
10148 {
10149 bfd_put_32 (output_bfd, outrel.r_addend,
10150 sgot->contents + off);
10151 outrel.r_addend = 0;
252b5132 10152 }
f21f3fe0 10153
b436d854
RS		 10154 if (outrel.r_info != 0)
10155 {
10156 outrel.r_offset = (sgot->output_section->vma
10157 + sgot->output_offset
10158 + off);
10159 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
10160 }
10161 h->got.offset |= 1;
10162 }
252b5132
RH		 10163 value = sgot->output_offset + off;
10164 }
10165 else
10166 {
10167 bfd_vma off;
f21f3fe0 10168
252b5132
RH		 10169 BFD_ASSERT (local_got_offsets != NULL &&
10170 local_got_offsets[r_symndx] != (bfd_vma) -1);
f21f3fe0 10171
252b5132 10172 off = local_got_offsets[r_symndx];
f21f3fe0 10173
252b5132
RH		 10174 /* The offset must always be a multiple of 4. We use the
10175 least significant bit to record whether we have already
9b485d32 10176 generated the necessary reloc. */
252b5132
RH		 10177 if ((off & 1) != 0)
10178 off &= ~1;
10179 else
10180 {
00a97672 10181 if (globals->use_rel)
34e77a92 10182 bfd_put_32 (output_bfd, dynreloc_value, sgot->contents + off);
f21f3fe0 10183
0e1862bb 10184 if (bfd_link_pic (info) || dynreloc_st_type == STT_GNU_IFUNC)
252b5132 10185 {
947216bf 10186 Elf_Internal_Rela outrel;
f21f3fe0 10187
34e77a92 10188 outrel.r_addend = addend + dynreloc_value;
252b5132 10189 outrel.r_offset = (sgot->output_section->vma
f21f3fe0 10190 + sgot->output_offset
252b5132 10191 + off);
34e77a92 10192 if (dynreloc_st_type == STT_GNU_IFUNC)
99059e56 10193 outrel.r_info = ELF32_R_INFO (0, R_ARM_IRELATIVE);
34e77a92
RS		 10194 else
10195 outrel.r_info = ELF32_R_INFO (0, R_ARM_RELATIVE);
47beaa6a 10196 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
252b5132 10197 }
f21f3fe0 10198
252b5132
RH		 10199 local_got_offsets[r_symndx] |= 1;
10200 }
f21f3fe0 10201
252b5132
RH		 10202 value = sgot->output_offset + off;
10203 }
eb043451
PB		 10204 if (r_type != R_ARM_GOT32)
10205 value += sgot->output_section->vma;
9a5aca8c 10206
f21f3fe0 10207 return _bfd_final_link_relocate (howto, input_bfd, input_section,
99e4ae17 10208 contents, rel->r_offset, value,
00a97672 10209 rel->r_addend);
f21f3fe0 10210
ba93b8ac
DJ		 10211 case R_ARM_TLS_LDO32:
10212 value = value - dtpoff_base (info);
10213
10214 return _bfd_final_link_relocate (howto, input_bfd, input_section,
00a97672
RS		 10215 contents, rel->r_offset, value,
10216 rel->r_addend);
ba93b8ac
DJ		 10217
10218 case R_ARM_TLS_LDM32:
10219 {
10220 bfd_vma off;
10221
362d30a1 10222 if (sgot == NULL)
ba93b8ac
DJ		 10223 abort ();
10224
10225 off = globals->tls_ldm_got.offset;
10226
10227 if ((off & 1) != 0)
10228 off &= ~1;
10229 else
10230 {
10231 /* If we don't know the module number, create a relocation
10232 for it. */
0e1862bb 10233 if (bfd_link_pic (info))
ba93b8ac
DJ		 10234 {
10235 Elf_Internal_Rela outrel;
ba93b8ac 10236
362d30a1 10237 if (srelgot == NULL)
ba93b8ac
DJ		 10238 abort ();
10239
00a97672 10240 outrel.r_addend = 0;
362d30a1
RS		 10241 outrel.r_offset = (sgot->output_section->vma
10242 + sgot->output_offset + off);
ba93b8ac
DJ		 10243 outrel.r_info = ELF32_R_INFO (0, R_ARM_TLS_DTPMOD32);
10244
00a97672
RS		 10245 if (globals->use_rel)
10246 bfd_put_32 (output_bfd, outrel.r_addend,
362d30a1 10247 sgot->contents + off);
ba93b8ac 10248
47beaa6a 10249 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
ba93b8ac
DJ		 10250 }
10251 else
362d30a1 10252 bfd_put_32 (output_bfd, 1, sgot->contents + off);
ba93b8ac
DJ		 10253
10254 globals->tls_ldm_got.offset |= 1;
10255 }
10256
362d30a1 10257 value = sgot->output_section->vma + sgot->output_offset + off
ba93b8ac
DJ		 10258 - (input_section->output_section->vma + input_section->output_offset + rel->r_offset);
10259
10260 return _bfd_final_link_relocate (howto, input_bfd, input_section,
10261 contents, rel->r_offset, value,
00a97672 10262 rel->r_addend);
ba93b8ac
DJ		 10263 }
10264
0855e32b
NS		 10265 case R_ARM_TLS_CALL:
10266 case R_ARM_THM_TLS_CALL:
ba93b8ac
DJ		 10267 case R_ARM_TLS_GD32:
10268 case R_ARM_TLS_IE32:
0855e32b
NS		 10269 case R_ARM_TLS_GOTDESC:
10270 case R_ARM_TLS_DESCSEQ:
10271 case R_ARM_THM_TLS_DESCSEQ:
ba93b8ac 10272 {
0855e32b
NS		 10273 bfd_vma off, offplt;
10274 int indx = 0;
ba93b8ac
DJ		 10275 char tls_type;
10276
0855e32b 10277 BFD_ASSERT (sgot != NULL);
ba93b8ac 10278
ba93b8ac
DJ		 10279 if (h != NULL)
10280 {
10281 bfd_boolean dyn;
10282 dyn = globals->root.dynamic_sections_created;
0e1862bb
L		 10283 if (WILL_CALL_FINISH_DYNAMIC_SYMBOL (dyn,
10284 bfd_link_pic (info),
10285 h)
10286 && (!bfd_link_pic (info)
ba93b8ac
DJ		 10287 || !SYMBOL_REFERENCES_LOCAL (info, h)))
10288 {
10289 *unresolved_reloc_p = FALSE;
10290 indx = h->dynindx;
10291 }
10292 off = h->got.offset;
0855e32b 10293 offplt = elf32_arm_hash_entry (h)->tlsdesc_got;
ba93b8ac
DJ		 10294 tls_type = ((struct elf32_arm_link_hash_entry *) h)->tls_type;
10295 }
10296 else
10297 {
0855e32b 10298 BFD_ASSERT (local_got_offsets != NULL);
ba93b8ac 10299 off = local_got_offsets[r_symndx];
0855e32b 10300 offplt = local_tlsdesc_gotents[r_symndx];
ba93b8ac
DJ		 10301 tls_type = elf32_arm_local_got_tls_type (input_bfd)[r_symndx];
10302 }
10303
0855e32b 10304 /* Linker relaxations happens from one of the
b38cadfb 10305 R_ARM_{GOTDESC,CALL,DESCSEQ} relocations to IE or LE. */
0855e32b 10306 if (ELF32_R_TYPE(rel->r_info) != r_type)
b38cadfb 10307 tls_type = GOT_TLS_IE;
0855e32b
NS		 10308
10309 BFD_ASSERT (tls_type != GOT_UNKNOWN);
ba93b8ac
DJ		 10310
10311 if ((off & 1) != 0)
10312 off &= ~1;
10313 else
10314 {
10315 bfd_boolean need_relocs = FALSE;
10316 Elf_Internal_Rela outrel;
ba93b8ac
DJ		 10317 int cur_off = off;
10318
10319 /* The GOT entries have not been initialized yet. Do it
10320 now, and emit any relocations. If both an IE GOT and a
10321 GD GOT are necessary, we emit the GD first. */
10322
0e1862bb 10323 if ((bfd_link_pic (info) || indx != 0)
ba93b8ac
DJ		 10324 && (h == NULL
10325 || ELF_ST_VISIBILITY (h->other) == STV_DEFAULT
10326 || h->root.type != bfd_link_hash_undefweak))
10327 {
10328 need_relocs = TRUE;
0855e32b 10329 BFD_ASSERT (srelgot != NULL);
ba93b8ac
DJ		 10330 }
10331
0855e32b
NS		 10332 if (tls_type & GOT_TLS_GDESC)
10333 {
47beaa6a
RS		 10334 bfd_byte *loc;
10335
0855e32b
NS		 10336 /* We should have relaxed, unless this is an undefined
10337 weak symbol. */
10338 BFD_ASSERT ((h && (h->root.type == bfd_link_hash_undefweak))
0e1862bb 10339 || bfd_link_pic (info));
0855e32b 10340 BFD_ASSERT (globals->sgotplt_jump_table_size + offplt + 8
99059e56 10341 <= globals->root.sgotplt->size);
0855e32b
NS		 10342
10343 outrel.r_addend = 0;
10344 outrel.r_offset = (globals->root.sgotplt->output_section->vma
10345 + globals->root.sgotplt->output_offset
10346 + offplt
10347 + globals->sgotplt_jump_table_size);
b38cadfb 10348
0855e32b
NS		 10349 outrel.r_info = ELF32_R_INFO (indx, R_ARM_TLS_DESC);
10350 sreloc = globals->root.srelplt;
10351 loc = sreloc->contents;
10352 loc += globals->next_tls_desc_index++ * RELOC_SIZE (globals);
10353 BFD_ASSERT (loc + RELOC_SIZE (globals)
99059e56 10354 <= sreloc->contents + sreloc->size);
0855e32b
NS		 10355
10356 SWAP_RELOC_OUT (globals) (output_bfd, &outrel, loc);
10357
10358 /* For globals, the first word in the relocation gets
10359 the relocation index and the top bit set, or zero,
10360 if we're binding now. For locals, it gets the
10361 symbol's offset in the tls section. */
99059e56 10362 bfd_put_32 (output_bfd,
0855e32b
NS		 10363 !h ? value - elf_hash_table (info)->tls_sec->vma
10364 : info->flags & DF_BIND_NOW ? 0
10365 : 0x80000000 | ELF32_R_SYM (outrel.r_info),
b38cadfb
NC		 10366 globals->root.sgotplt->contents + offplt
10367 + globals->sgotplt_jump_table_size);
10368
0855e32b 10369 /* Second word in the relocation is always zero. */
99059e56 10370 bfd_put_32 (output_bfd, 0,
b38cadfb
NC		 10371 globals->root.sgotplt->contents + offplt
10372 + globals->sgotplt_jump_table_size + 4);
0855e32b 10373 }
ba93b8ac
DJ		 10374 if (tls_type & GOT_TLS_GD)
10375 {
10376 if (need_relocs)
10377 {
00a97672 10378 outrel.r_addend = 0;
362d30a1
RS		 10379 outrel.r_offset = (sgot->output_section->vma
10380 + sgot->output_offset
00a97672 10381 + cur_off);
ba93b8ac 10382 outrel.r_info = ELF32_R_INFO (indx, R_ARM_TLS_DTPMOD32);
ba93b8ac 10383
00a97672
RS		 10384 if (globals->use_rel)
10385 bfd_put_32 (output_bfd, outrel.r_addend,
362d30a1 10386 sgot->contents + cur_off);
00a97672 10387
47beaa6a 10388 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
ba93b8ac
DJ		 10389
10390 if (indx == 0)
10391 bfd_put_32 (output_bfd, value - dtpoff_base (info),
362d30a1 10392 sgot->contents + cur_off + 4);
ba93b8ac
DJ		 10393 else
10394 {
00a97672 10395 outrel.r_addend = 0;
ba93b8ac
DJ		 10396 outrel.r_info = ELF32_R_INFO (indx,
10397 R_ARM_TLS_DTPOFF32);
10398 outrel.r_offset += 4;
00a97672
RS		 10399
10400 if (globals->use_rel)
10401 bfd_put_32 (output_bfd, outrel.r_addend,
362d30a1 10402 sgot->contents + cur_off + 4);
00a97672 10403
47beaa6a
RS		 10404 elf32_arm_add_dynreloc (output_bfd, info,
10405 srelgot, &outrel);
ba93b8ac
DJ		 10406 }
10407 }
10408 else
10409 {
10410 /* If we are not emitting relocations for a
10411 general dynamic reference, then we must be in a
10412 static link or an executable link with the
10413 symbol binding locally. Mark it as belonging
10414 to module 1, the executable. */
10415 bfd_put_32 (output_bfd, 1,
362d30a1 10416 sgot->contents + cur_off);
ba93b8ac 10417 bfd_put_32 (output_bfd, value - dtpoff_base (info),
362d30a1 10418 sgot->contents + cur_off + 4);
ba93b8ac
DJ		 10419 }
10420
10421 cur_off += 8;
10422 }
10423
10424 if (tls_type & GOT_TLS_IE)
10425 {
10426 if (need_relocs)
10427 {
00a97672
RS		 10428 if (indx == 0)
10429 outrel.r_addend = value - dtpoff_base (info);
10430 else
10431 outrel.r_addend = 0;
362d30a1
RS		 10432 outrel.r_offset = (sgot->output_section->vma
10433 + sgot->output_offset
ba93b8ac
DJ		 10434 + cur_off);
10435 outrel.r_info = ELF32_R_INFO (indx, R_ARM_TLS_TPOFF32);
10436
00a97672
RS		 10437 if (globals->use_rel)
10438 bfd_put_32 (output_bfd, outrel.r_addend,
362d30a1 10439 sgot->contents + cur_off);
ba93b8ac 10440
47beaa6a 10441 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
ba93b8ac
DJ		 10442 }
10443 else
10444 bfd_put_32 (output_bfd, tpoff (info, value),
362d30a1 10445 sgot->contents + cur_off);
ba93b8ac
DJ		 10446 cur_off += 4;
10447 }
10448
10449 if (h != NULL)
10450 h->got.offset |= 1;
10451 else
10452 local_got_offsets[r_symndx] |= 1;
10453 }
10454
10455 if ((tls_type & GOT_TLS_GD) && r_type != R_ARM_TLS_GD32)
10456 off += 8;
0855e32b
NS		 10457 else if (tls_type & GOT_TLS_GDESC)
10458 off = offplt;
10459
10460 if (ELF32_R_TYPE(rel->r_info) == R_ARM_TLS_CALL
10461 || ELF32_R_TYPE(rel->r_info) == R_ARM_THM_TLS_CALL)
10462 {
10463 bfd_signed_vma offset;
12352d3f
PB		 10464 /* TLS stubs are arm mode. The original symbol is a
10465 data object, so branch_type is bogus. */
10466 branch_type = ST_BRANCH_TO_ARM;
0855e32b 10467 enum elf32_arm_stub_type stub_type
34e77a92
RS		 10468 = arm_type_of_stub (info, input_section, rel,
10469 st_type, &branch_type,
0855e32b
NS		 10470 (struct elf32_arm_link_hash_entry *)h,
10471 globals->tls_trampoline, globals->root.splt,
10472 input_bfd, sym_name);
10473
10474 if (stub_type != arm_stub_none)
10475 {
10476 struct elf32_arm_stub_hash_entry *stub_entry
10477 = elf32_arm_get_stub_entry
10478 (input_section, globals->root.splt, 0, rel,
10479 globals, stub_type);
10480 offset = (stub_entry->stub_offset
10481 + stub_entry->stub_sec->output_offset
10482 + stub_entry->stub_sec->output_section->vma);
10483 }
10484 else
10485 offset = (globals->root.splt->output_section->vma
10486 + globals->root.splt->output_offset
10487 + globals->tls_trampoline);
10488
10489 if (ELF32_R_TYPE(rel->r_info) == R_ARM_TLS_CALL)
10490 {
10491 unsigned long inst;
b38cadfb
NC		 10492
10493 offset -= (input_section->output_section->vma
10494 + input_section->output_offset
10495 + rel->r_offset + 8);
0855e32b
NS		 10496
10497 inst = offset >> 2;
10498 inst &= 0x00ffffff;
10499 value = inst | (globals->use_blx ? 0xfa000000 : 0xeb000000);
10500 }
10501 else
10502 {
10503 /* Thumb blx encodes the offset in a complicated
10504 fashion. */
10505 unsigned upper_insn, lower_insn;
10506 unsigned neg;
10507
b38cadfb
NC		 10508 offset -= (input_section->output_section->vma
10509 + input_section->output_offset
0855e32b 10510 + rel->r_offset + 4);
b38cadfb 10511
12352d3f
PB		 10512 if (stub_type != arm_stub_none
10513 && arm_stub_is_thumb (stub_type))
10514 {
10515 lower_insn = 0xd000;
10516 }
10517 else
10518 {
10519 lower_insn = 0xc000;
6a631e86 10520 /* Round up the offset to a word boundary. */
12352d3f
PB		 10521 offset = (offset + 2) & ~2;
10522 }
10523
0855e32b
NS		 10524 neg = offset < 0;
10525 upper_insn = (0xf000
10526 | ((offset >> 12) & 0x3ff)
10527 | (neg << 10));
12352d3f 10528 lower_insn |= (((!((offset >> 23) & 1)) ^ neg) << 13)
0855e32b 10529 | (((!((offset >> 22) & 1)) ^ neg) << 11)
12352d3f 10530 | ((offset >> 1) & 0x7ff);
0855e32b
NS		 10531 bfd_put_16 (input_bfd, upper_insn, hit_data);
10532 bfd_put_16 (input_bfd, lower_insn, hit_data + 2);
10533 return bfd_reloc_ok;
10534 }
10535 }
10536 /* These relocations needs special care, as besides the fact
10537 they point somewhere in .gotplt, the addend must be
10538 adjusted accordingly depending on the type of instruction
6a631e86 10539 we refer to. */
0855e32b
NS		 10540 else if ((r_type == R_ARM_TLS_GOTDESC) && (tls_type & GOT_TLS_GDESC))
10541 {
10542 unsigned long data, insn;
10543 unsigned thumb;
b38cadfb 10544
0855e32b
NS		 10545 data = bfd_get_32 (input_bfd, hit_data);
10546 thumb = data & 1;
10547 data &= ~1u;
b38cadfb 10548
0855e32b
NS		 10549 if (thumb)
10550 {
10551 insn = bfd_get_16 (input_bfd, contents + rel->r_offset - data);
10552 if ((insn & 0xf000) == 0xf000 || (insn & 0xf800) == 0xe800)
10553 insn = (insn << 16)
10554 | bfd_get_16 (input_bfd,
10555 contents + rel->r_offset - data + 2);
10556 if ((insn & 0xf800c000) == 0xf000c000)
10557 /* bl/blx */
10558 value = -6;
10559 else if ((insn & 0xffffff00) == 0x4400)
10560 /* add */
10561 value = -5;
10562 else
10563 {
10564 (*_bfd_error_handler)
10565 (_("%B(%A+0x%lx):unexpected Thumb instruction '0x%x' referenced by TLS_GOTDESC"),
10566 input_bfd, input_section,
10567 (unsigned long)rel->r_offset, insn);
10568 return bfd_reloc_notsupported;
10569 }
10570 }
10571 else
10572 {
10573 insn = bfd_get_32 (input_bfd, contents + rel->r_offset - data);
10574
10575 switch (insn >> 24)
10576 {
10577 case 0xeb: /* bl */
10578 case 0xfa: /* blx */
10579 value = -4;
10580 break;
10581
10582 case 0xe0: /* add */
10583 value = -8;
10584 break;
b38cadfb 10585
0855e32b
NS		 10586 default:
10587 (*_bfd_error_handler)
10588 (_("%B(%A+0x%lx):unexpected ARM instruction '0x%x' referenced by TLS_GOTDESC"),
10589 input_bfd, input_section,
10590 (unsigned long)rel->r_offset, insn);
10591 return bfd_reloc_notsupported;
10592 }
10593 }
b38cadfb 10594
0855e32b
NS		 10595 value += ((globals->root.sgotplt->output_section->vma
10596 + globals->root.sgotplt->output_offset + off)
10597 - (input_section->output_section->vma
10598 + input_section->output_offset
10599 + rel->r_offset)
10600 + globals->sgotplt_jump_table_size);
10601 }
10602 else
10603 value = ((globals->root.sgot->output_section->vma
10604 + globals->root.sgot->output_offset + off)
10605 - (input_section->output_section->vma
10606 + input_section->output_offset + rel->r_offset));
ba93b8ac
DJ		 10607
10608 return _bfd_final_link_relocate (howto, input_bfd, input_section,
10609 contents, rel->r_offset, value,
00a97672 10610 rel->r_addend);
ba93b8ac
DJ		 10611 }
10612
10613 case R_ARM_TLS_LE32:
3cbc1e5e 10614 if (bfd_link_dll (info))
ba93b8ac
DJ		 10615 {
10616 (*_bfd_error_handler)
10617 (_("%B(%A+0x%lx): R_ARM_TLS_LE32 relocation not permitted in shared object"),
10618 input_bfd, input_section,
10619 (long) rel->r_offset, howto->name);
46691134 10620 return bfd_reloc_notsupported;
ba93b8ac
DJ		 10621 }
10622 else
10623 value = tpoff (info, value);
906e58ca 10624
ba93b8ac 10625 return _bfd_final_link_relocate (howto, input_bfd, input_section,
00a97672
RS		 10626 contents, rel->r_offset, value,
10627 rel->r_addend);
ba93b8ac 10628
319850b4
JB		 10629 case R_ARM_V4BX:
10630 if (globals->fix_v4bx)
845b51d6
PB		 10631 {
10632 bfd_vma insn = bfd_get_32 (input_bfd, hit_data);
319850b4 10633
845b51d6
PB		 10634 /* Ensure that we have a BX instruction. */
10635 BFD_ASSERT ((insn & 0x0ffffff0) == 0x012fff10);
319850b4 10636
845b51d6
PB		 10637 if (globals->fix_v4bx == 2 && (insn & 0xf) != 0xf)
10638 {
10639 /* Branch to veneer. */
10640 bfd_vma glue_addr;
10641 glue_addr = elf32_arm_bx_glue (info, insn & 0xf);
10642 glue_addr -= input_section->output_section->vma
10643 + input_section->output_offset
10644 + rel->r_offset + 8;
10645 insn = (insn & 0xf0000000) | 0x0a000000
10646 | ((glue_addr >> 2) & 0x00ffffff);
10647 }
10648 else
10649 {
10650 /* Preserve Rm (lowest four bits) and the condition code
10651 (highest four bits). Other bits encode MOV PC,Rm. */
10652 insn = (insn & 0xf000000f) | 0x01a0f000;
10653 }
319850b4 10654
845b51d6
PB		 10655 bfd_put_32 (input_bfd, insn, hit_data);
10656 }
319850b4
JB		 10657 return bfd_reloc_ok;
10658
b6895b4f
PB		 10659 case R_ARM_MOVW_ABS_NC:
10660 case R_ARM_MOVT_ABS:
10661 case R_ARM_MOVW_PREL_NC:
10662 case R_ARM_MOVT_PREL:
92f5d02b
MS		 10663 /* Until we properly support segment-base-relative addressing then
10664 we assume the segment base to be zero, as for the group relocations.
10665 Thus R_ARM_MOVW_BREL_NC has the same semantics as R_ARM_MOVW_ABS_NC
10666 and R_ARM_MOVT_BREL has the same semantics as R_ARM_MOVT_ABS. */
10667 case R_ARM_MOVW_BREL_NC:
10668 case R_ARM_MOVW_BREL:
10669 case R_ARM_MOVT_BREL:
b6895b4f
PB		 10670 {
10671 bfd_vma insn = bfd_get_32 (input_bfd, hit_data);
10672
10673 if (globals->use_rel)
10674 {
10675 addend = ((insn >> 4) & 0xf000) | (insn & 0xfff);
39623e12 10676 signed_addend = (addend ^ 0x8000) - 0x8000;
b6895b4f 10677 }
92f5d02b 10678
b6895b4f 10679 value += signed_addend;
b6895b4f
PB		 10680
10681 if (r_type == R_ARM_MOVW_PREL_NC || r_type == R_ARM_MOVT_PREL)
10682 value -= (input_section->output_section->vma
10683 + input_section->output_offset + rel->r_offset);
10684
92f5d02b 10685 if (r_type == R_ARM_MOVW_BREL && value >= 0x10000)
99059e56 10686 return bfd_reloc_overflow;
92f5d02b 10687
35fc36a8 10688 if (branch_type == ST_BRANCH_TO_THUMB)
92f5d02b
MS		 10689 value |= 1;
10690
10691 if (r_type == R_ARM_MOVT_ABS || r_type == R_ARM_MOVT_PREL
99059e56 10692 || r_type == R_ARM_MOVT_BREL)
b6895b4f
PB		 10693 value >>= 16;
10694
10695 insn &= 0xfff0f000;
10696 insn |= value & 0xfff;
10697 insn |= (value & 0xf000) << 4;
10698 bfd_put_32 (input_bfd, insn, hit_data);
10699 }
10700 return bfd_reloc_ok;
10701
10702 case R_ARM_THM_MOVW_ABS_NC:
10703 case R_ARM_THM_MOVT_ABS:
10704 case R_ARM_THM_MOVW_PREL_NC:
10705 case R_ARM_THM_MOVT_PREL:
92f5d02b
MS		 10706 /* Until we properly support segment-base-relative addressing then
10707 we assume the segment base to be zero, as for the above relocations.
10708 Thus R_ARM_THM_MOVW_BREL_NC has the same semantics as
10709 R_ARM_THM_MOVW_ABS_NC and R_ARM_THM_MOVT_BREL has the same semantics
10710 as R_ARM_THM_MOVT_ABS. */
10711 case R_ARM_THM_MOVW_BREL_NC:
10712 case R_ARM_THM_MOVW_BREL:
10713 case R_ARM_THM_MOVT_BREL:
b6895b4f
PB		 10714 {
10715 bfd_vma insn;
906e58ca 10716
b6895b4f
PB		 10717 insn = bfd_get_16 (input_bfd, hit_data) << 16;
10718 insn |= bfd_get_16 (input_bfd, hit_data + 2);
10719
10720 if (globals->use_rel)
10721 {
10722 addend = ((insn >> 4) & 0xf000)
10723 | ((insn >> 15) & 0x0800)
10724 | ((insn >> 4) & 0x0700)
10725 | (insn & 0x00ff);
39623e12 10726 signed_addend = (addend ^ 0x8000) - 0x8000;
b6895b4f 10727 }
92f5d02b 10728
b6895b4f 10729 value += signed_addend;
b6895b4f
PB		 10730
10731 if (r_type == R_ARM_THM_MOVW_PREL_NC || r_type == R_ARM_THM_MOVT_PREL)
10732 value -= (input_section->output_section->vma
10733 + input_section->output_offset + rel->r_offset);
10734
92f5d02b 10735 if (r_type == R_ARM_THM_MOVW_BREL && value >= 0x10000)
99059e56 10736 return bfd_reloc_overflow;
92f5d02b 10737
35fc36a8 10738 if (branch_type == ST_BRANCH_TO_THUMB)
92f5d02b
MS		 10739 value |= 1;
10740
10741 if (r_type == R_ARM_THM_MOVT_ABS || r_type == R_ARM_THM_MOVT_PREL
99059e56 10742 || r_type == R_ARM_THM_MOVT_BREL)
b6895b4f
PB		 10743 value >>= 16;
10744
10745 insn &= 0xfbf08f00;
10746 insn |= (value & 0xf000) << 4;
10747 insn |= (value & 0x0800) << 15;
10748 insn |= (value & 0x0700) << 4;
10749 insn |= (value & 0x00ff);
10750
10751 bfd_put_16 (input_bfd, insn >> 16, hit_data);
10752 bfd_put_16 (input_bfd, insn & 0xffff, hit_data + 2);
10753 }
10754 return bfd_reloc_ok;
10755
4962c51a
MS		 10756 case R_ARM_ALU_PC_G0_NC:
10757 case R_ARM_ALU_PC_G1_NC:
10758 case R_ARM_ALU_PC_G0:
10759 case R_ARM_ALU_PC_G1:
10760 case R_ARM_ALU_PC_G2:
10761 case R_ARM_ALU_SB_G0_NC:
10762 case R_ARM_ALU_SB_G1_NC:
10763 case R_ARM_ALU_SB_G0:
10764 case R_ARM_ALU_SB_G1:
10765 case R_ARM_ALU_SB_G2:
10766 {
10767 bfd_vma insn = bfd_get_32 (input_bfd, hit_data);
99059e56 10768 bfd_vma pc = input_section->output_section->vma
4962c51a 10769 + input_section->output_offset + rel->r_offset;
31a91d61 10770 /* sb is the origin of the *segment* containing the symbol. */
62c34db3 10771 bfd_vma sb = sym_sec ? sym_sec->output_section->vma : 0;
99059e56
RM		 10772 bfd_vma residual;
10773 bfd_vma g_n;
4962c51a 10774 bfd_signed_vma signed_value;
99059e56
RM		 10775 int group = 0;
10776
10777 /* Determine which group of bits to select. */
10778 switch (r_type)
10779 {
10780 case R_ARM_ALU_PC_G0_NC:
10781 case R_ARM_ALU_PC_G0:
10782 case R_ARM_ALU_SB_G0_NC:
10783 case R_ARM_ALU_SB_G0:
10784 group = 0;
10785 break;
10786
10787 case R_ARM_ALU_PC_G1_NC:
10788 case R_ARM_ALU_PC_G1:
10789 case R_ARM_ALU_SB_G1_NC:
10790 case R_ARM_ALU_SB_G1:
10791 group = 1;
10792 break;
10793
10794 case R_ARM_ALU_PC_G2:
10795 case R_ARM_ALU_SB_G2:
10796 group = 2;
10797 break;
10798
10799 default:
10800 abort ();
10801 }
10802
10803 /* If REL, extract the addend from the insn. If RELA, it will
10804 have already been fetched for us. */
4962c51a 10805 if (globals->use_rel)
99059e56
RM		 10806 {
10807 int negative;
10808 bfd_vma constant = insn & 0xff;
10809 bfd_vma rotation = (insn & 0xf00) >> 8;
10810
10811 if (rotation == 0)
10812 signed_addend = constant;
10813 else
10814 {
10815 /* Compensate for the fact that in the instruction, the
10816 rotation is stored in multiples of 2 bits. */
10817 rotation *= 2;
10818
10819 /* Rotate "constant" right by "rotation" bits. */
10820 signed_addend = (constant >> rotation) |
10821 (constant << (8 * sizeof (bfd_vma) - rotation));
10822 }
10823
10824 /* Determine if the instruction is an ADD or a SUB.
10825 (For REL, this determines the sign of the addend.) */
10826 negative = identify_add_or_sub (insn);
10827 if (negative == 0)
10828 {
10829 (*_bfd_error_handler)
10830 (_("%B(%A+0x%lx): Only ADD or SUB instructions are allowed for ALU group relocations"),
10831 input_bfd, input_section,
10832 (long) rel->r_offset, howto->name);
10833 return bfd_reloc_overflow;
10834 }
10835
10836 signed_addend *= negative;
10837 }
4962c51a
MS		 10838
10839 /* Compute the value (X) to go in the place. */
99059e56
RM		 10840 if (r_type == R_ARM_ALU_PC_G0_NC
10841 || r_type == R_ARM_ALU_PC_G1_NC
10842 || r_type == R_ARM_ALU_PC_G0
10843 || r_type == R_ARM_ALU_PC_G1
10844 || r_type == R_ARM_ALU_PC_G2)
10845 /* PC relative. */
10846 signed_value = value - pc + signed_addend;
10847 else
10848 /* Section base relative. */
10849 signed_value = value - sb + signed_addend;
10850
10851 /* If the target symbol is a Thumb function, then set the
10852 Thumb bit in the address. */
35fc36a8 10853 if (branch_type == ST_BRANCH_TO_THUMB)
4962c51a
MS		 10854 signed_value |= 1;
10855
99059e56
RM		 10856 /* Calculate the value of the relevant G_n, in encoded
10857 constant-with-rotation format. */
b6518b38
NC		 10858 g_n = calculate_group_reloc_mask (signed_value < 0 ? - signed_value : signed_value,
10859 group, &residual);
99059e56
RM		 10860
10861 /* Check for overflow if required. */
10862 if ((r_type == R_ARM_ALU_PC_G0
10863 || r_type == R_ARM_ALU_PC_G1
10864 || r_type == R_ARM_ALU_PC_G2
10865 || r_type == R_ARM_ALU_SB_G0
10866 || r_type == R_ARM_ALU_SB_G1
10867 || r_type == R_ARM_ALU_SB_G2) && residual != 0)
10868 {
10869 (*_bfd_error_handler)
10870 (_("%B(%A+0x%lx): Overflow whilst splitting 0x%lx for group relocation %s"),
10871 input_bfd, input_section,
b6518b38
NC		 10872 (long) rel->r_offset, signed_value < 0 ? - signed_value : signed_value,
10873 howto->name);
99059e56
RM		 10874 return bfd_reloc_overflow;
10875 }
10876
10877 /* Mask out the value and the ADD/SUB part of the opcode; take care
10878 not to destroy the S bit. */
10879 insn &= 0xff1ff000;
10880
10881 /* Set the opcode according to whether the value to go in the
10882 place is negative. */
10883 if (signed_value < 0)
10884 insn |= 1 << 22;
10885 else
10886 insn |= 1 << 23;
10887
10888 /* Encode the offset. */
10889 insn |= g_n;
4962c51a
MS		 10890
10891 bfd_put_32 (input_bfd, insn, hit_data);
10892 }
10893 return bfd_reloc_ok;
10894
10895 case R_ARM_LDR_PC_G0:
10896 case R_ARM_LDR_PC_G1:
10897 case R_ARM_LDR_PC_G2:
10898 case R_ARM_LDR_SB_G0:
10899 case R_ARM_LDR_SB_G1:
10900 case R_ARM_LDR_SB_G2:
10901 {
10902 bfd_vma insn = bfd_get_32 (input_bfd, hit_data);
99059e56 10903 bfd_vma pc = input_section->output_section->vma
4962c51a 10904 + input_section->output_offset + rel->r_offset;
31a91d61 10905 /* sb is the origin of the *segment* containing the symbol. */
62c34db3 10906 bfd_vma sb = sym_sec ? sym_sec->output_section->vma : 0;
99059e56 10907 bfd_vma residual;
4962c51a 10908 bfd_signed_vma signed_value;
99059e56
RM		 10909 int group = 0;
10910
10911 /* Determine which groups of bits to calculate. */
10912 switch (r_type)
10913 {
10914 case R_ARM_LDR_PC_G0:
10915 case R_ARM_LDR_SB_G0:
10916 group = 0;
10917 break;
10918
10919 case R_ARM_LDR_PC_G1:
10920 case R_ARM_LDR_SB_G1:
10921 group = 1;
10922 break;
10923
10924 case R_ARM_LDR_PC_G2:
10925 case R_ARM_LDR_SB_G2:
10926 group = 2;
10927 break;
10928
10929 default:
10930 abort ();
10931 }
10932
10933 /* If REL, extract the addend from the insn. If RELA, it will
10934 have already been fetched for us. */
4962c51a 10935 if (globals->use_rel)
99059e56
RM		 10936 {
10937 int negative = (insn & (1 << 23)) ? 1 : -1;
10938 signed_addend = negative * (insn & 0xfff);
10939 }
4962c51a
MS		 10940
10941 /* Compute the value (X) to go in the place. */
99059e56
RM		 10942 if (r_type == R_ARM_LDR_PC_G0
10943 || r_type == R_ARM_LDR_PC_G1
10944 || r_type == R_ARM_LDR_PC_G2)
10945 /* PC relative. */
10946 signed_value = value - pc + signed_addend;
10947 else
10948 /* Section base relative. */
10949 signed_value = value - sb + signed_addend;
10950
10951 /* Calculate the value of the relevant G_{n-1} to obtain
10952 the residual at that stage. */
b6518b38
NC		 10953 calculate_group_reloc_mask (signed_value < 0 ? - signed_value : signed_value,
10954 group - 1, &residual);
99059e56
RM		 10955
10956 /* Check for overflow. */
10957 if (residual >= 0x1000)
10958 {
10959 (*_bfd_error_handler)
10960 (_("%B(%A+0x%lx): Overflow whilst splitting 0x%lx for group relocation %s"),
b6518b38
NC		 10961 input_bfd, input_section,
10962 (long) rel->r_offset, labs (signed_value), howto->name);
99059e56
RM		 10963 return bfd_reloc_overflow;
10964 }
10965
10966 /* Mask out the value and U bit. */
10967 insn &= 0xff7ff000;
10968
10969 /* Set the U bit if the value to go in the place is non-negative. */
10970 if (signed_value >= 0)
10971 insn |= 1 << 23;
10972
10973 /* Encode the offset. */
10974 insn |= residual;
4962c51a
MS		 10975
10976 bfd_put_32 (input_bfd, insn, hit_data);
10977 }
10978 return bfd_reloc_ok;
10979
10980 case R_ARM_LDRS_PC_G0:
10981 case R_ARM_LDRS_PC_G1:
10982 case R_ARM_LDRS_PC_G2:
10983 case R_ARM_LDRS_SB_G0:
10984 case R_ARM_LDRS_SB_G1:
10985 case R_ARM_LDRS_SB_G2:
10986 {
10987 bfd_vma insn = bfd_get_32 (input_bfd, hit_data);
99059e56 10988 bfd_vma pc = input_section->output_section->vma
4962c51a 10989 + input_section->output_offset + rel->r_offset;
31a91d61 10990 /* sb is the origin of the *segment* containing the symbol. */
62c34db3 10991 bfd_vma sb = sym_sec ? sym_sec->output_section->vma : 0;
99059e56 10992 bfd_vma residual;
4962c51a 10993 bfd_signed_vma signed_value;
99059e56
RM		 10994 int group = 0;
10995
10996 /* Determine which groups of bits to calculate. */
10997 switch (r_type)
10998 {
10999 case R_ARM_LDRS_PC_G0:
11000 case R_ARM_LDRS_SB_G0:
11001 group = 0;
11002 break;
11003
11004 case R_ARM_LDRS_PC_G1:
11005 case R_ARM_LDRS_SB_G1:
11006 group = 1;
11007 break;
11008
11009 case R_ARM_LDRS_PC_G2:
11010 case R_ARM_LDRS_SB_G2:
11011 group = 2;
11012 break;
11013
11014 default:
11015 abort ();
11016 }
11017
11018 /* If REL, extract the addend from the insn. If RELA, it will
11019 have already been fetched for us. */
4962c51a 11020 if (globals->use_rel)
99059e56
RM		 11021 {
11022 int negative = (insn & (1 << 23)) ? 1 : -1;
11023 signed_addend = negative * (((insn & 0xf00) >> 4) + (insn & 0xf));
11024 }
4962c51a
MS		 11025
11026 /* Compute the value (X) to go in the place. */
99059e56
RM		 11027 if (r_type == R_ARM_LDRS_PC_G0
11028 || r_type == R_ARM_LDRS_PC_G1
11029 || r_type == R_ARM_LDRS_PC_G2)
11030 /* PC relative. */
11031 signed_value = value - pc + signed_addend;
11032 else
11033 /* Section base relative. */
11034 signed_value = value - sb + signed_addend;
11035
11036 /* Calculate the value of the relevant G_{n-1} to obtain
11037 the residual at that stage. */
b6518b38
NC		 11038 calculate_group_reloc_mask (signed_value < 0 ? - signed_value : signed_value,
11039 group - 1, &residual);
99059e56
RM		 11040
11041 /* Check for overflow. */
11042 if (residual >= 0x100)
11043 {
11044 (*_bfd_error_handler)
11045 (_("%B(%A+0x%lx): Overflow whilst splitting 0x%lx for group relocation %s"),
b6518b38
NC		 11046 input_bfd, input_section,
11047 (long) rel->r_offset, labs (signed_value), howto->name);
99059e56
RM		 11048 return bfd_reloc_overflow;
11049 }
11050
11051 /* Mask out the value and U bit. */
11052 insn &= 0xff7ff0f0;
11053
11054 /* Set the U bit if the value to go in the place is non-negative. */
11055 if (signed_value >= 0)
11056 insn |= 1 << 23;
11057
11058 /* Encode the offset. */
11059 insn |= ((residual & 0xf0) << 4) | (residual & 0xf);
4962c51a
MS		 11060
11061 bfd_put_32 (input_bfd, insn, hit_data);
11062 }
11063 return bfd_reloc_ok;
11064
11065 case R_ARM_LDC_PC_G0:
11066 case R_ARM_LDC_PC_G1:
11067 case R_ARM_LDC_PC_G2:
11068 case R_ARM_LDC_SB_G0:
11069 case R_ARM_LDC_SB_G1:
11070 case R_ARM_LDC_SB_G2:
11071 {
11072 bfd_vma insn = bfd_get_32 (input_bfd, hit_data);
99059e56 11073 bfd_vma pc = input_section->output_section->vma
4962c51a 11074 + input_section->output_offset + rel->r_offset;
31a91d61 11075 /* sb is the origin of the *segment* containing the symbol. */
62c34db3 11076 bfd_vma sb = sym_sec ? sym_sec->output_section->vma : 0;
99059e56 11077 bfd_vma residual;
4962c51a 11078 bfd_signed_vma signed_value;
99059e56
RM		 11079 int group = 0;
11080
11081 /* Determine which groups of bits to calculate. */
11082 switch (r_type)
11083 {
11084 case R_ARM_LDC_PC_G0:
11085 case R_ARM_LDC_SB_G0:
11086 group = 0;
11087 break;
11088
11089 case R_ARM_LDC_PC_G1:
11090 case R_ARM_LDC_SB_G1:
11091 group = 1;
11092 break;
11093
11094 case R_ARM_LDC_PC_G2:
11095 case R_ARM_LDC_SB_G2:
11096 group = 2;
11097 break;
11098
11099 default:
11100 abort ();
11101 }
11102
11103 /* If REL, extract the addend from the insn. If RELA, it will
11104 have already been fetched for us. */
4962c51a 11105 if (globals->use_rel)
99059e56
RM		 11106 {
11107 int negative = (insn & (1 << 23)) ? 1 : -1;
11108 signed_addend = negative * ((insn & 0xff) << 2);
11109 }
4962c51a
MS		 11110
11111 /* Compute the value (X) to go in the place. */
99059e56
RM		 11112 if (r_type == R_ARM_LDC_PC_G0
11113 || r_type == R_ARM_LDC_PC_G1
11114 || r_type == R_ARM_LDC_PC_G2)
11115 /* PC relative. */
11116 signed_value = value - pc + signed_addend;
11117 else
11118 /* Section base relative. */
11119 signed_value = value - sb + signed_addend;
11120
11121 /* Calculate the value of the relevant G_{n-1} to obtain
11122 the residual at that stage. */
b6518b38
NC		 11123 calculate_group_reloc_mask (signed_value < 0 ? - signed_value : signed_value,
11124 group - 1, &residual);
99059e56
RM		 11125
11126 /* Check for overflow. (The absolute value to go in the place must be
11127 divisible by four and, after having been divided by four, must
11128 fit in eight bits.) */
11129 if ((residual & 0x3) != 0 || residual >= 0x400)
11130 {
11131 (*_bfd_error_handler)
11132 (_("%B(%A+0x%lx): Overflow whilst splitting 0x%lx for group relocation %s"),
11133 input_bfd, input_section,
b6518b38 11134 (long) rel->r_offset, labs (signed_value), howto->name);
99059e56
RM		 11135 return bfd_reloc_overflow;
11136 }
11137
11138 /* Mask out the value and U bit. */
11139 insn &= 0xff7fff00;
11140
11141 /* Set the U bit if the value to go in the place is non-negative. */
11142 if (signed_value >= 0)
11143 insn |= 1 << 23;
11144
11145 /* Encode the offset. */
11146 insn |= residual >> 2;
4962c51a
MS		 11147
11148 bfd_put_32 (input_bfd, insn, hit_data);
11149 }
11150 return bfd_reloc_ok;
11151
72d98d16
MG		 11152 case R_ARM_THM_ALU_ABS_G0_NC:
11153 case R_ARM_THM_ALU_ABS_G1_NC:
11154 case R_ARM_THM_ALU_ABS_G2_NC:
11155 case R_ARM_THM_ALU_ABS_G3_NC:
11156 {
11157 const int shift_array[4] = {0, 8, 16, 24};
11158 bfd_vma insn = bfd_get_16 (input_bfd, hit_data);
11159 bfd_vma addr = value;
11160 int shift = shift_array[r_type - R_ARM_THM_ALU_ABS_G0_NC];
11161
11162 /* Compute address. */
11163 if (globals->use_rel)
11164 signed_addend = insn & 0xff;
11165 addr += signed_addend;
11166 if (branch_type == ST_BRANCH_TO_THUMB)
11167 addr |= 1;
11168 /* Clean imm8 insn. */
11169 insn &= 0xff00;
11170 /* And update with correct part of address. */
11171 insn |= (addr >> shift) & 0xff;
11172 /* Update insn. */
11173 bfd_put_16 (input_bfd, insn, hit_data);
11174 }
11175
11176 *unresolved_reloc_p = FALSE;
11177 return bfd_reloc_ok;
11178
252b5132
RH		 11179 default:
11180 return bfd_reloc_notsupported;
11181 }
11182}
11183
98c1d4aa
NC		 11184/* Add INCREMENT to the reloc (of type HOWTO) at ADDRESS. */
11185static void
57e8b36a
NC		 11186arm_add_to_rel (bfd * abfd,
11187 bfd_byte * address,
11188 reloc_howto_type * howto,
11189 bfd_signed_vma increment)
98c1d4aa 11190{
98c1d4aa
NC		 11191 bfd_signed_vma addend;
11192
bd97cb95
DJ		 11193 if (howto->type == R_ARM_THM_CALL
11194 || howto->type == R_ARM_THM_JUMP24)
98c1d4aa 11195 {
9a5aca8c
AM		 11196 int upper_insn, lower_insn;
11197 int upper, lower;
98c1d4aa 11198
9a5aca8c
AM		 11199 upper_insn = bfd_get_16 (abfd, address);
11200 lower_insn = bfd_get_16 (abfd, address + 2);
11201 upper = upper_insn & 0x7ff;
11202 lower = lower_insn & 0x7ff;
11203
11204 addend = (upper << 12) | (lower << 1);
ddda4409 11205 addend += increment;
9a5aca8c 11206 addend >>= 1;
98c1d4aa 11207
9a5aca8c
AM		 11208 upper_insn = (upper_insn & 0xf800) | ((addend >> 11) & 0x7ff);
11209 lower_insn = (lower_insn & 0xf800) | (addend & 0x7ff);
11210
dc810e39
AM		 11211 bfd_put_16 (abfd, (bfd_vma) upper_insn, address);
11212 bfd_put_16 (abfd, (bfd_vma) lower_insn, address + 2);
9a5aca8c
AM		 11213 }
11214 else
11215 {
11216 bfd_vma contents;
11217
11218 contents = bfd_get_32 (abfd, address);
11219
11220 /* Get the (signed) value from the instruction. */
11221 addend = contents & howto->src_mask;
11222 if (addend & ((howto->src_mask + 1) >> 1))
11223 {
11224 bfd_signed_vma mask;
11225
11226 mask = -1;
11227 mask &= ~ howto->src_mask;
11228 addend |= mask;
11229 }
11230
11231 /* Add in the increment, (which is a byte value). */
11232 switch (howto->type)
11233 {
11234 default:
11235 addend += increment;
11236 break;
11237
11238 case R_ARM_PC24:
c6596c5e 11239 case R_ARM_PLT32:
5b5bb741
PB		 11240 case R_ARM_CALL:
11241 case R_ARM_JUMP24:
9a5aca8c 11242 addend <<= howto->size;
dc810e39 11243 addend += increment;
9a5aca8c
AM		 11244
11245 /* Should we check for overflow here ? */
11246
11247 /* Drop any undesired bits. */
11248 addend >>= howto->rightshift;
11249 break;
11250 }
11251
11252 contents = (contents & ~ howto->dst_mask) | (addend & howto->dst_mask);
11253
11254 bfd_put_32 (abfd, contents, address);
ddda4409 11255 }
98c1d4aa 11256}
252b5132 11257
ba93b8ac
DJ		 11258#define IS_ARM_TLS_RELOC(R_TYPE) \
11259 ((R_TYPE) == R_ARM_TLS_GD32 \
11260 || (R_TYPE) == R_ARM_TLS_LDO32 \
11261 || (R_TYPE) == R_ARM_TLS_LDM32 \
11262 || (R_TYPE) == R_ARM_TLS_DTPOFF32 \
11263 || (R_TYPE) == R_ARM_TLS_DTPMOD32 \
11264 || (R_TYPE) == R_ARM_TLS_TPOFF32 \
11265 || (R_TYPE) == R_ARM_TLS_LE32 \
0855e32b
NS		 11266 || (R_TYPE) == R_ARM_TLS_IE32 \
11267 || IS_ARM_TLS_GNU_RELOC (R_TYPE))
11268
11269/* Specific set of relocations for the gnu tls dialect. */
11270#define IS_ARM_TLS_GNU_RELOC(R_TYPE) \
11271 ((R_TYPE) == R_ARM_TLS_GOTDESC \
11272 || (R_TYPE) == R_ARM_TLS_CALL \
11273 || (R_TYPE) == R_ARM_THM_TLS_CALL \
11274 || (R_TYPE) == R_ARM_TLS_DESCSEQ \
11275 || (R_TYPE) == R_ARM_THM_TLS_DESCSEQ)
ba93b8ac 11276
252b5132 11277/* Relocate an ARM ELF section. */
906e58ca 11278
b34976b6 11279static bfd_boolean
57e8b36a
NC		 11280elf32_arm_relocate_section (bfd * output_bfd,
11281 struct bfd_link_info * info,
11282 bfd * input_bfd,
11283 asection * input_section,
11284 bfd_byte * contents,
11285 Elf_Internal_Rela * relocs,
11286 Elf_Internal_Sym * local_syms,
11287 asection ** local_sections)
252b5132 11288{
b34976b6
AM		 11289 Elf_Internal_Shdr *symtab_hdr;
11290 struct elf_link_hash_entry **sym_hashes;
11291 Elf_Internal_Rela *rel;
11292 Elf_Internal_Rela *relend;
11293 const char *name;
b32d3aa2 11294 struct elf32_arm_link_hash_table * globals;
252b5132 11295
4e7fd91e 11296 globals = elf32_arm_hash_table (info);
4dfe6ac6
NC		 11297 if (globals == NULL)
11298 return FALSE;
b491616a 11299
0ffa91dd 11300 symtab_hdr = & elf_symtab_hdr (input_bfd);
252b5132
RH		 11301 sym_hashes = elf_sym_hashes (input_bfd);
11302
11303 rel = relocs;
11304 relend = relocs + input_section->reloc_count;
11305 for (; rel < relend; rel++)
11306 {
ba96a88f
NC		 11307 int r_type;
11308 reloc_howto_type * howto;
11309 unsigned long r_symndx;
11310 Elf_Internal_Sym * sym;
11311 asection * sec;
252b5132 11312 struct elf_link_hash_entry * h;
ba96a88f
NC		 11313 bfd_vma relocation;
11314 bfd_reloc_status_type r;
11315 arelent bfd_reloc;
ba93b8ac 11316 char sym_type;
0945cdfd 11317 bfd_boolean unresolved_reloc = FALSE;
f2a9dd69 11318 char *error_message = NULL;
f21f3fe0 11319
252b5132 11320 r_symndx = ELF32_R_SYM (rel->r_info);
ba96a88f 11321 r_type = ELF32_R_TYPE (rel->r_info);
b32d3aa2 11322 r_type = arm_real_reloc_type (globals, r_type);
252b5132 11323
ba96a88f 11324 if ( r_type == R_ARM_GNU_VTENTRY
99059e56
RM		 11325 || r_type == R_ARM_GNU_VTINHERIT)
11326 continue;
252b5132 11327
b32d3aa2 11328 bfd_reloc.howto = elf32_arm_howto_from_type (r_type);
ba96a88f 11329 howto = bfd_reloc.howto;
252b5132 11330
252b5132
RH		 11331 h = NULL;
11332 sym = NULL;
11333 sec = NULL;
9b485d32 11334
252b5132
RH		 11335 if (r_symndx < symtab_hdr->sh_info)
11336 {
11337 sym = local_syms + r_symndx;
ba93b8ac 11338 sym_type = ELF32_ST_TYPE (sym->st_info);
252b5132 11339 sec = local_sections[r_symndx];
ffcb4889
NS		 11340
11341 /* An object file might have a reference to a local
11342 undefined symbol. This is a daft object file, but we
11343 should at least do something about it. V4BX & NONE
11344 relocations do not use the symbol and are explicitly
77b4f08f
TS		 11345 allowed to use the undefined symbol, so allow those.
11346 Likewise for relocations against STN_UNDEF. */
ffcb4889
NS		 11347 if (r_type != R_ARM_V4BX
11348 && r_type != R_ARM_NONE
77b4f08f 11349 && r_symndx != STN_UNDEF
ffcb4889
NS		 11350 && bfd_is_und_section (sec)
11351 && ELF_ST_BIND (sym->st_info) != STB_WEAK)
11352 {
11353 if (!info->callbacks->undefined_symbol
11354 (info, bfd_elf_string_from_elf_section
11355 (input_bfd, symtab_hdr->sh_link, sym->st_name),
11356 input_bfd, input_section,
11357 rel->r_offset, TRUE))
11358 return FALSE;
11359 }
b38cadfb 11360
4e7fd91e 11361 if (globals->use_rel)
f8df10f4 11362 {
4e7fd91e
PB		 11363 relocation = (sec->output_section->vma
11364 + sec->output_offset
11365 + sym->st_value);
0e1862bb 11366 if (!bfd_link_relocatable (info)
ab96bf03
AM		 11367 && (sec->flags & SEC_MERGE)
11368 && ELF_ST_TYPE (sym->st_info) == STT_SECTION)
f8df10f4 11369 {
4e7fd91e
PB		 11370 asection *msec;
11371 bfd_vma addend, value;
11372
39623e12 11373 switch (r_type)
4e7fd91e 11374 {
39623e12
PB		 11375 case R_ARM_MOVW_ABS_NC:
11376 case R_ARM_MOVT_ABS:
11377 value = bfd_get_32 (input_bfd, contents + rel->r_offset);
11378 addend = ((value & 0xf0000) >> 4) | (value & 0xfff);
11379 addend = (addend ^ 0x8000) - 0x8000;
11380 break;
f8df10f4 11381
39623e12
PB		 11382 case R_ARM_THM_MOVW_ABS_NC:
11383 case R_ARM_THM_MOVT_ABS:
11384 value = bfd_get_16 (input_bfd, contents + rel->r_offset)
11385 << 16;
11386 value |= bfd_get_16 (input_bfd,
11387 contents + rel->r_offset + 2);
11388 addend = ((value & 0xf7000) >> 4) | (value & 0xff)
11389 | ((value & 0x04000000) >> 15);
11390 addend = (addend ^ 0x8000) - 0x8000;
11391 break;
f8df10f4 11392
39623e12
PB		 11393 default:
11394 if (howto->rightshift
11395 || (howto->src_mask & (howto->src_mask + 1)))
11396 {
11397 (*_bfd_error_handler)
11398 (_("%B(%A+0x%lx): %s relocation against SEC_MERGE section"),
11399 input_bfd, input_section,
11400 (long) rel->r_offset, howto->name);
11401 return FALSE;
11402 }
11403
11404 value = bfd_get_32 (input_bfd, contents + rel->r_offset);
11405
11406 /* Get the (signed) value from the instruction. */
11407 addend = value & howto->src_mask;
11408 if (addend & ((howto->src_mask + 1) >> 1))
11409 {
11410 bfd_signed_vma mask;
11411
11412 mask = -1;
11413 mask &= ~ howto->src_mask;
11414 addend |= mask;
11415 }
11416 break;
4e7fd91e 11417 }
39623e12 11418
4e7fd91e
PB		 11419 msec = sec;
11420 addend =
11421 _bfd_elf_rel_local_sym (output_bfd, sym, &msec, addend)
11422 - relocation;
11423 addend += msec->output_section->vma + msec->output_offset;
39623e12 11424
cc643b88 11425 /* Cases here must match those in the preceding
39623e12
PB		 11426 switch statement. */
11427 switch (r_type)
11428 {
11429 case R_ARM_MOVW_ABS_NC:
11430 case R_ARM_MOVT_ABS:
11431 value = (value & 0xfff0f000) | ((addend & 0xf000) << 4)
11432 | (addend & 0xfff);
11433 bfd_put_32 (input_bfd, value, contents + rel->r_offset);
11434 break;
11435
11436 case R_ARM_THM_MOVW_ABS_NC:
11437 case R_ARM_THM_MOVT_ABS:
11438 value = (value & 0xfbf08f00) | ((addend & 0xf700) << 4)
11439 | (addend & 0xff) | ((addend & 0x0800) << 15);
11440 bfd_put_16 (input_bfd, value >> 16,
11441 contents + rel->r_offset);
11442 bfd_put_16 (input_bfd, value,
11443 contents + rel->r_offset + 2);
11444 break;
11445
11446 default:
11447 value = (value & ~ howto->dst_mask)
11448 | (addend & howto->dst_mask);
11449 bfd_put_32 (input_bfd, value, contents + rel->r_offset);
11450 break;
11451 }
f8df10f4 11452 }
f8df10f4 11453 }
4e7fd91e
PB		 11454 else
11455 relocation = _bfd_elf_rela_local_sym (output_bfd, sym, &sec, rel);
252b5132
RH		 11456 }
11457 else
11458 {
62d887d4 11459 bfd_boolean warned, ignored;
560e09e9 11460
b2a8e766
AM		 11461 RELOC_FOR_GLOBAL_SYMBOL (info, input_bfd, input_section, rel,
11462 r_symndx, symtab_hdr, sym_hashes,
11463 h, sec, relocation,
62d887d4 11464 unresolved_reloc, warned, ignored);
ba93b8ac
DJ		 11465
11466 sym_type = h->type;
252b5132
RH		 11467 }
11468
dbaa2011 11469 if (sec != NULL && discarded_section (sec))
e4067dbb 11470 RELOC_AGAINST_DISCARDED_SECTION (info, input_bfd, input_section,
545fd46b 11471 rel, 1, relend, howto, 0, contents);
ab96bf03 11472
0e1862bb 11473 if (bfd_link_relocatable (info))
ab96bf03
AM		 11474 {
11475 /* This is a relocatable link. We don't have to change
11476 anything, unless the reloc is against a section symbol,
11477 in which case we have to adjust according to where the
11478 section symbol winds up in the output section. */
11479 if (sym != NULL && ELF_ST_TYPE (sym->st_info) == STT_SECTION)
11480 {
11481 if (globals->use_rel)
11482 arm_add_to_rel (input_bfd, contents + rel->r_offset,
11483 howto, (bfd_signed_vma) sec->output_offset);
11484 else
11485 rel->r_addend += sec->output_offset;
11486 }
11487 continue;
11488 }
11489
252b5132
RH		 11490 if (h != NULL)
11491 name = h->root.root.string;
11492 else
11493 {
11494 name = (bfd_elf_string_from_elf_section
11495 (input_bfd, symtab_hdr->sh_link, sym->st_name));
11496 if (name == NULL || *name == '\0')
11497 name = bfd_section_name (input_bfd, sec);
11498 }
f21f3fe0 11499
cf35638d 11500 if (r_symndx != STN_UNDEF
ba93b8ac
DJ		 11501 && r_type != R_ARM_NONE
11502 && (h == NULL
11503 || h->root.type == bfd_link_hash_defined
11504 || h->root.type == bfd_link_hash_defweak)
11505 && IS_ARM_TLS_RELOC (r_type) != (sym_type == STT_TLS))
11506 {
11507 (*_bfd_error_handler)
11508 ((sym_type == STT_TLS
11509 ? _("%B(%A+0x%lx): %s used with TLS symbol %s")
11510 : _("%B(%A+0x%lx): %s used with non-TLS symbol %s")),
11511 input_bfd,
11512 input_section,
11513 (long) rel->r_offset,
11514 howto->name,
11515 name);
11516 }
11517
0855e32b 11518 /* We call elf32_arm_final_link_relocate unless we're completely
99059e56
RM		 11519 done, i.e., the relaxation produced the final output we want,
11520 and we won't let anybody mess with it. Also, we have to do
11521 addend adjustments in case of a R_ARM_TLS_GOTDESC relocation
6a631e86 11522 both in relaxed and non-relaxed cases. */
39d911fc
TP		 11523 if ((elf32_arm_tls_transition (info, r_type, h) != (unsigned)r_type)
11524 || (IS_ARM_TLS_GNU_RELOC (r_type)
11525 && !((h ? elf32_arm_hash_entry (h)->tls_type :
11526 elf32_arm_local_got_tls_type (input_bfd)[r_symndx])
11527 & GOT_TLS_GDESC)))
11528 {
11529 r = elf32_arm_tls_relax (globals, input_bfd, input_section,
11530 contents, rel, h == NULL);
11531 /* This may have been marked unresolved because it came from
11532 a shared library. But we've just dealt with that. */
11533 unresolved_reloc = 0;
11534 }
11535 else
11536 r = bfd_reloc_continue;
b38cadfb 11537
39d911fc
TP		 11538 if (r == bfd_reloc_continue)
11539 {
11540 unsigned char branch_type =
11541 h ? ARM_GET_SYM_BRANCH_TYPE (h->target_internal)
11542 : ARM_GET_SYM_BRANCH_TYPE (sym->st_target_internal);
11543
11544 r = elf32_arm_final_link_relocate (howto, input_bfd, output_bfd,
11545 input_section, contents, rel,
11546 relocation, info, sec, name,
11547 sym_type, branch_type, h,
11548 &unresolved_reloc,
11549 &error_message);
11550 }
0945cdfd
DJ		 11551
11552 /* Dynamic relocs are not propagated for SEC_DEBUGGING sections
11553 because such sections are not SEC_ALLOC and thus ld.so will
11554 not process them. */
11555 if (unresolved_reloc
99059e56
RM		 11556 && !((input_section->flags & SEC_DEBUGGING) != 0
11557 && h->def_dynamic)
1d5316ab
AM		 11558 && _bfd_elf_section_offset (output_bfd, info, input_section,
11559 rel->r_offset) != (bfd_vma) -1)
0945cdfd
DJ		 11560 {
11561 (*_bfd_error_handler)
843fe662
L		 11562 (_("%B(%A+0x%lx): unresolvable %s relocation against symbol `%s'"),
11563 input_bfd,
11564 input_section,
11565 (long) rel->r_offset,
11566 howto->name,
11567 h->root.root.string);
0945cdfd
DJ		 11568 return FALSE;
11569 }
252b5132
RH		 11570
11571 if (r != bfd_reloc_ok)
11572 {
252b5132
RH		 11573 switch (r)
11574 {
11575 case bfd_reloc_overflow:
cf919dfd
PB		 11576 /* If the overflowing reloc was to an undefined symbol,
11577 we have already printed one error message and there
11578 is no point complaining again. */
11579 if ((! h ||
11580 h->root.type != bfd_link_hash_undefined)
11581 && (!((*info->callbacks->reloc_overflow)
dfeffb9f
L		 11582 (info, (h ? &h->root : NULL), name, howto->name,
11583 (bfd_vma) 0, input_bfd, input_section,
11584 rel->r_offset))))
b34976b6 11585 return FALSE;
252b5132
RH		 11586 break;
11587
11588 case bfd_reloc_undefined:
11589 if (!((*info->callbacks->undefined_symbol)
11590 (info, name, input_bfd, input_section,
b34976b6
AM		 11591 rel->r_offset, TRUE)))
11592 return FALSE;
252b5132
RH		 11593 break;
11594
11595 case bfd_reloc_outofrange:
f2a9dd69 11596 error_message = _("out of range");
252b5132
RH		 11597 goto common_error;
11598
11599 case bfd_reloc_notsupported:
f2a9dd69 11600 error_message = _("unsupported relocation");
252b5132
RH		 11601 goto common_error;
11602
11603 case bfd_reloc_dangerous:
f2a9dd69 11604 /* error_message should already be set. */
252b5132
RH		 11605 goto common_error;
11606
11607 default:
f2a9dd69 11608 error_message = _("unknown error");
8029a119 11609 /* Fall through. */
252b5132
RH		 11610
11611 common_error:
f2a9dd69
DJ		 11612 BFD_ASSERT (error_message != NULL);
11613 if (!((*info->callbacks->reloc_dangerous)
11614 (info, error_message, input_bfd, input_section,
252b5132 11615 rel->r_offset)))
b34976b6 11616 return FALSE;
252b5132
RH		 11617 break;
11618 }
11619 }
11620 }
11621
b34976b6 11622 return TRUE;
252b5132
RH		 11623}
11624
91d6fa6a 11625/* Add a new unwind edit to the list described by HEAD, TAIL. If TINDEX is zero,
2468f9c9 11626 adds the edit to the start of the list. (The list must be built in order of
91d6fa6a 11627 ascending TINDEX: the function's callers are primarily responsible for
2468f9c9
PB		 11628 maintaining that condition). */
11629
11630static void
11631add_unwind_table_edit (arm_unwind_table_edit **head,
11632 arm_unwind_table_edit **tail,
11633 arm_unwind_edit_type type,
11634 asection *linked_section,
91d6fa6a 11635 unsigned int tindex)
2468f9c9 11636{
21d799b5
NC		 11637 arm_unwind_table_edit *new_edit = (arm_unwind_table_edit *)
11638 xmalloc (sizeof (arm_unwind_table_edit));
b38cadfb 11639
2468f9c9
PB		 11640 new_edit->type = type;
11641 new_edit->linked_section = linked_section;
91d6fa6a 11642 new_edit->index = tindex;
b38cadfb 11643
91d6fa6a 11644 if (tindex > 0)
2468f9c9
PB		 11645 {
11646 new_edit->next = NULL;
11647
11648 if (*tail)
11649 (*tail)->next = new_edit;
11650
11651 (*tail) = new_edit;
11652
11653 if (!*head)
11654 (*head) = new_edit;
11655 }
11656 else
11657 {
11658 new_edit->next = *head;
11659
11660 if (!*tail)
11661 *tail = new_edit;
11662
11663 *head = new_edit;
11664 }
11665}
11666
11667static _arm_elf_section_data *get_arm_elf_section_data (asection *);
11668
11669/* Increase the size of EXIDX_SEC by ADJUST bytes. ADJUST mau be negative. */
11670static void
11671adjust_exidx_size(asection *exidx_sec, int adjust)
11672{
11673 asection *out_sec;
11674
11675 if (!exidx_sec->rawsize)
11676 exidx_sec->rawsize = exidx_sec->size;
11677
11678 bfd_set_section_size (exidx_sec->owner, exidx_sec, exidx_sec->size + adjust);
11679 out_sec = exidx_sec->output_section;
11680 /* Adjust size of output section. */
11681 bfd_set_section_size (out_sec->owner, out_sec, out_sec->size +adjust);
11682}
11683
11684/* Insert an EXIDX_CANTUNWIND marker at the end of a section. */
11685static void
11686insert_cantunwind_after(asection *text_sec, asection *exidx_sec)
11687{
11688 struct _arm_elf_section_data *exidx_arm_data;
11689
11690 exidx_arm_data = get_arm_elf_section_data (exidx_sec);
11691 add_unwind_table_edit (
11692 &exidx_arm_data->u.exidx.unwind_edit_list,
11693 &exidx_arm_data->u.exidx.unwind_edit_tail,
11694 INSERT_EXIDX_CANTUNWIND_AT_END, text_sec, UINT_MAX);
11695
491d01d3
YU		 11696 exidx_arm_data->additional_reloc_count++;
11697
2468f9c9
PB		 11698 adjust_exidx_size(exidx_sec, 8);
11699}
11700
11701/* Scan .ARM.exidx tables, and create a list describing edits which should be
11702 made to those tables, such that:
b38cadfb 11703
2468f9c9
PB		 11704 1. Regions without unwind data are marked with EXIDX_CANTUNWIND entries.
11705 2. Duplicate entries are merged together (EXIDX_CANTUNWIND, or unwind
99059e56 11706 codes which have been inlined into the index).
2468f9c9 11707
85fdf906
AH		 11708 If MERGE_EXIDX_ENTRIES is false, duplicate entries are not merged.
11709
2468f9c9 11710 The edits are applied when the tables are written
b38cadfb 11711 (in elf32_arm_write_section). */
2468f9c9
PB		 11712
11713bfd_boolean
11714elf32_arm_fix_exidx_coverage (asection **text_section_order,
11715 unsigned int num_text_sections,
85fdf906
AH		 11716 struct bfd_link_info *info,
11717 bfd_boolean merge_exidx_entries)
2468f9c9
PB		 11718{
11719 bfd *inp;
11720 unsigned int last_second_word = 0, i;
11721 asection *last_exidx_sec = NULL;
11722 asection *last_text_sec = NULL;
11723 int last_unwind_type = -1;
11724
11725 /* Walk over all EXIDX sections, and create backlinks from the corrsponding
11726 text sections. */
c72f2fb2 11727 for (inp = info->input_bfds; inp != NULL; inp = inp->link.next)
2468f9c9
PB		 11728 {
11729 asection *sec;
b38cadfb 11730
2468f9c9 11731 for (sec = inp->sections; sec != NULL; sec = sec->next)
99059e56 11732 {
2468f9c9
PB		 11733 struct bfd_elf_section_data *elf_sec = elf_section_data (sec);
11734 Elf_Internal_Shdr *hdr = &elf_sec->this_hdr;
b38cadfb 11735
dec9d5df 11736 if (!hdr || hdr->sh_type != SHT_ARM_EXIDX)
2468f9c9 11737 continue;
b38cadfb 11738
2468f9c9
PB		 11739 if (elf_sec->linked_to)
11740 {
11741 Elf_Internal_Shdr *linked_hdr
99059e56 11742 = &elf_section_data (elf_sec->linked_to)->this_hdr;
2468f9c9 11743 struct _arm_elf_section_data *linked_sec_arm_data
99059e56 11744 = get_arm_elf_section_data (linked_hdr->bfd_section);
2468f9c9
PB		 11745
11746 if (linked_sec_arm_data == NULL)
99059e56 11747 continue;
2468f9c9
PB		 11748
11749 /* Link this .ARM.exidx section back from the text section it
99059e56 11750 describes. */
2468f9c9
PB		 11751 linked_sec_arm_data->u.text.arm_exidx_sec = sec;
11752 }
11753 }
11754 }
11755
11756 /* Walk all text sections in order of increasing VMA. Eilminate duplicate
11757 index table entries (EXIDX_CANTUNWIND and inlined unwind opcodes),
91d6fa6a 11758 and add EXIDX_CANTUNWIND entries for sections with no unwind table data. */
2468f9c9
PB		 11759
11760 for (i = 0; i < num_text_sections; i++)
11761 {
11762 asection *sec = text_section_order[i];
11763 asection *exidx_sec;
11764 struct _arm_elf_section_data *arm_data = get_arm_elf_section_data (sec);
11765 struct _arm_elf_section_data *exidx_arm_data;
11766 bfd_byte *contents = NULL;
11767 int deleted_exidx_bytes = 0;
11768 bfd_vma j;
11769 arm_unwind_table_edit *unwind_edit_head = NULL;
11770 arm_unwind_table_edit *unwind_edit_tail = NULL;
11771 Elf_Internal_Shdr *hdr;
11772 bfd *ibfd;
11773
11774 if (arm_data == NULL)
99059e56 11775 continue;
2468f9c9
PB		 11776
11777 exidx_sec = arm_data->u.text.arm_exidx_sec;
11778 if (exidx_sec == NULL)
11779 {
11780 /* Section has no unwind data. */
11781 if (last_unwind_type == 0 || !last_exidx_sec)
11782 continue;
11783
11784 /* Ignore zero sized sections. */
11785 if (sec->size == 0)
11786 continue;
11787
11788 insert_cantunwind_after(last_text_sec, last_exidx_sec);
11789 last_unwind_type = 0;
11790 continue;
11791 }
11792
22a8f80e
PB		 11793 /* Skip /DISCARD/ sections. */
11794 if (bfd_is_abs_section (exidx_sec->output_section))
11795 continue;
11796
2468f9c9
PB		 11797 hdr = &elf_section_data (exidx_sec)->this_hdr;
11798 if (hdr->sh_type != SHT_ARM_EXIDX)
99059e56 11799 continue;
b38cadfb 11800
2468f9c9
PB		 11801 exidx_arm_data = get_arm_elf_section_data (exidx_sec);
11802 if (exidx_arm_data == NULL)
99059e56 11803 continue;
b38cadfb 11804
2468f9c9 11805 ibfd = exidx_sec->owner;
b38cadfb 11806
2468f9c9
PB		 11807 if (hdr->contents != NULL)
11808 contents = hdr->contents;
11809 else if (! bfd_malloc_and_get_section (ibfd, exidx_sec, &contents))
11810 /* An error? */
11811 continue;
11812
ac06903d
YU		 11813 if (last_unwind_type > 0)
11814 {
11815 unsigned int first_word = bfd_get_32 (ibfd, contents);
11816 /* Add cantunwind if first unwind item does not match section
11817 start. */
11818 if (first_word != sec->vma)
11819 {
11820 insert_cantunwind_after (last_text_sec, last_exidx_sec);
11821 last_unwind_type = 0;
11822 }
11823 }
11824
2468f9c9
PB		 11825 for (j = 0; j < hdr->sh_size; j += 8)
11826 {
11827 unsigned int second_word = bfd_get_32 (ibfd, contents + j + 4);
11828 int unwind_type;
11829 int elide = 0;
11830
11831 /* An EXIDX_CANTUNWIND entry. */
11832 if (second_word == 1)
11833 {
11834 if (last_unwind_type == 0)
11835 elide = 1;
11836 unwind_type = 0;
11837 }
11838 /* Inlined unwinding data. Merge if equal to previous. */
11839 else if ((second_word & 0x80000000) != 0)
11840 {
85fdf906
AH		 11841 if (merge_exidx_entries
11842 && last_second_word == second_word && last_unwind_type == 1)
2468f9c9
PB		 11843 elide = 1;
11844 unwind_type = 1;
11845 last_second_word = second_word;
11846 }
11847 /* Normal table entry. In theory we could merge these too,
11848 but duplicate entries are likely to be much less common. */
11849 else
11850 unwind_type = 2;
11851
491d01d3 11852 if (elide && !bfd_link_relocatable (info))
2468f9c9
PB		 11853 {
11854 add_unwind_table_edit (&unwind_edit_head, &unwind_edit_tail,
11855 DELETE_EXIDX_ENTRY, NULL, j / 8);
11856
11857 deleted_exidx_bytes += 8;
11858 }
11859
11860 last_unwind_type = unwind_type;
11861 }
11862
11863 /* Free contents if we allocated it ourselves. */
11864 if (contents != hdr->contents)
99059e56 11865 free (contents);
2468f9c9
PB		 11866
11867 /* Record edits to be applied later (in elf32_arm_write_section). */
11868 exidx_arm_data->u.exidx.unwind_edit_list = unwind_edit_head;
11869 exidx_arm_data->u.exidx.unwind_edit_tail = unwind_edit_tail;
b38cadfb 11870
2468f9c9
PB		 11871 if (deleted_exidx_bytes > 0)
11872 adjust_exidx_size(exidx_sec, -deleted_exidx_bytes);
11873
11874 last_exidx_sec = exidx_sec;
11875 last_text_sec = sec;
11876 }
11877
11878 /* Add terminating CANTUNWIND entry. */
491d01d3
YU		 11879 if (!bfd_link_relocatable (info) && last_exidx_sec
11880 && last_unwind_type != 0)
2468f9c9
PB		 11881 insert_cantunwind_after(last_text_sec, last_exidx_sec);
11882
11883 return TRUE;
11884}
11885
3e6b1042
DJ		 11886static bfd_boolean
11887elf32_arm_output_glue_section (struct bfd_link_info *info, bfd *obfd,
11888 bfd *ibfd, const char *name)
11889{
11890 asection *sec, *osec;
11891
3d4d4302 11892 sec = bfd_get_linker_section (ibfd, name);
3e6b1042
DJ		 11893 if (sec == NULL || (sec->flags & SEC_EXCLUDE) != 0)
11894 return TRUE;
11895
11896 osec = sec->output_section;
11897 if (elf32_arm_write_section (obfd, info, sec, sec->contents))
11898 return TRUE;
11899
11900 if (! bfd_set_section_contents (obfd, osec, sec->contents,
11901 sec->output_offset, sec->size))
11902 return FALSE;
11903
11904 return TRUE;
11905}
11906
11907static bfd_boolean
11908elf32_arm_final_link (bfd *abfd, struct bfd_link_info *info)
11909{
11910 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (info);
fe33d2fa 11911 asection *sec, *osec;
3e6b1042 11912
4dfe6ac6
NC		 11913 if (globals == NULL)
11914 return FALSE;
11915
3e6b1042
DJ		 11916 /* Invoke the regular ELF backend linker to do all the work. */
11917 if (!bfd_elf_final_link (abfd, info))
11918 return FALSE;
11919
fe33d2fa
CL		 11920 /* Process stub sections (eg BE8 encoding, ...). */
11921 struct elf32_arm_link_hash_table *htab = elf32_arm_hash_table (info);
7292b3ac 11922 unsigned int i;
cdb21a0a
NS		 11923 for (i=0; i<htab->top_id; i++)
11924 {
11925 sec = htab->stub_group[i].stub_sec;
11926 /* Only process it once, in its link_sec slot. */
11927 if (sec && i == htab->stub_group[i].link_sec->id)
11928 {
11929 osec = sec->output_section;
11930 elf32_arm_write_section (abfd, info, sec, sec->contents);
11931 if (! bfd_set_section_contents (abfd, osec, sec->contents,
11932 sec->output_offset, sec->size))
11933 return FALSE;
11934 }
fe33d2fa 11935 }
fe33d2fa 11936
3e6b1042
DJ		 11937 /* Write out any glue sections now that we have created all the
11938 stubs. */
11939 if (globals->bfd_of_glue_owner != NULL)
11940 {
11941 if (! elf32_arm_output_glue_section (info, abfd,
11942 globals->bfd_of_glue_owner,
11943 ARM2THUMB_GLUE_SECTION_NAME))
11944 return FALSE;
11945
11946 if (! elf32_arm_output_glue_section (info, abfd,
11947 globals->bfd_of_glue_owner,
11948 THUMB2ARM_GLUE_SECTION_NAME))
11949 return FALSE;
11950
11951 if (! elf32_arm_output_glue_section (info, abfd,
11952 globals->bfd_of_glue_owner,
11953 VFP11_ERRATUM_VENEER_SECTION_NAME))
11954 return FALSE;
11955
a504d23a
LA		 11956 if (! elf32_arm_output_glue_section (info, abfd,
11957 globals->bfd_of_glue_owner,
11958 STM32L4XX_ERRATUM_VENEER_SECTION_NAME))
11959 return FALSE;
11960
3e6b1042
DJ		 11961 if (! elf32_arm_output_glue_section (info, abfd,
11962 globals->bfd_of_glue_owner,
11963 ARM_BX_GLUE_SECTION_NAME))
11964 return FALSE;
11965 }
11966
11967 return TRUE;
11968}
11969
5968a7b8
NC		 11970/* Return a best guess for the machine number based on the attributes. */
11971
11972static unsigned int
11973bfd_arm_get_mach_from_attributes (bfd * abfd)
11974{
11975 int arch = bfd_elf_get_obj_attr_int (abfd, OBJ_ATTR_PROC, Tag_CPU_arch);
11976
11977 switch (arch)
11978 {
11979 case TAG_CPU_ARCH_V4: return bfd_mach_arm_4;
11980 case TAG_CPU_ARCH_V4T: return bfd_mach_arm_4T;
11981 case TAG_CPU_ARCH_V5T: return bfd_mach_arm_5T;
11982
11983 case TAG_CPU_ARCH_V5TE:
11984 {
11985 char * name;
11986
11987 BFD_ASSERT (Tag_CPU_name < NUM_KNOWN_OBJ_ATTRIBUTES);
11988 name = elf_known_obj_attributes (abfd) [OBJ_ATTR_PROC][Tag_CPU_name].s;
11989
11990 if (name)
11991 {
11992 if (strcmp (name, "IWMMXT2") == 0)
11993 return bfd_mach_arm_iWMMXt2;
11994
11995 if (strcmp (name, "IWMMXT") == 0)
6034aab8 11996 return bfd_mach_arm_iWMMXt;
088ca6c1
NC		 11997
11998 if (strcmp (name, "XSCALE") == 0)
11999 {
12000 int wmmx;
12001
12002 BFD_ASSERT (Tag_WMMX_arch < NUM_KNOWN_OBJ_ATTRIBUTES);
12003 wmmx = elf_known_obj_attributes (abfd) [OBJ_ATTR_PROC][Tag_WMMX_arch].i;
12004 switch (wmmx)
12005 {
12006 case 1: return bfd_mach_arm_iWMMXt;
12007 case 2: return bfd_mach_arm_iWMMXt2;
12008 default: return bfd_mach_arm_XScale;
12009 }
12010 }
5968a7b8
NC		 12011 }
12012
12013 return bfd_mach_arm_5TE;
12014 }
12015
12016 default:
12017 return bfd_mach_arm_unknown;
12018 }
12019}
12020
c178919b
NC		 12021/* Set the right machine number. */
12022
12023static bfd_boolean
57e8b36a 12024elf32_arm_object_p (bfd *abfd)
c178919b 12025{
5a6c6817 12026 unsigned int mach;
57e8b36a 12027
5a6c6817 12028 mach = bfd_arm_get_mach_from_notes (abfd, ARM_NOTE_SECTION);
c178919b 12029
5968a7b8
NC		 12030 if (mach == bfd_mach_arm_unknown)
12031 {
12032 if (elf_elfheader (abfd)->e_flags & EF_ARM_MAVERICK_FLOAT)
12033 mach = bfd_mach_arm_ep9312;
12034 else
12035 mach = bfd_arm_get_mach_from_attributes (abfd);
12036 }
c178919b 12037
5968a7b8 12038 bfd_default_set_arch_mach (abfd, bfd_arch_arm, mach);
c178919b
NC		 12039 return TRUE;
12040}
12041
fc830a83 12042/* Function to keep ARM specific flags in the ELF header. */
3c9458e9 12043
b34976b6 12044static bfd_boolean
57e8b36a 12045elf32_arm_set_private_flags (bfd *abfd, flagword flags)
252b5132
RH		 12046{
12047 if (elf_flags_init (abfd)
12048 && elf_elfheader (abfd)->e_flags != flags)
12049 {
fc830a83
NC		 12050 if (EF_ARM_EABI_VERSION (flags) == EF_ARM_EABI_UNKNOWN)
12051 {
fd2ec330 12052 if (flags & EF_ARM_INTERWORK)
d003868e
AM		 12053 (*_bfd_error_handler)
12054 (_("Warning: Not setting interworking flag of %B since it has already been specified as non-interworking"),
12055 abfd);
fc830a83 12056 else
d003868e
AM		 12057 _bfd_error_handler
12058 (_("Warning: Clearing the interworking flag of %B due to outside request"),
12059 abfd);
fc830a83 12060 }
252b5132
RH		 12061 }
12062 else
12063 {
12064 elf_elfheader (abfd)->e_flags = flags;
b34976b6 12065 elf_flags_init (abfd) = TRUE;
252b5132
RH		 12066 }
12067
b34976b6 12068 return TRUE;
252b5132
RH		 12069}
12070
fc830a83 12071/* Copy backend specific data from one object module to another. */
9b485d32 12072
b34976b6 12073static bfd_boolean
57e8b36a 12074elf32_arm_copy_private_bfd_data (bfd *ibfd, bfd *obfd)
252b5132
RH		 12075{
12076 flagword in_flags;
12077 flagword out_flags;
12078
0ffa91dd 12079 if (! is_arm_elf (ibfd) || ! is_arm_elf (obfd))
b34976b6 12080 return TRUE;
252b5132 12081
fc830a83 12082 in_flags = elf_elfheader (ibfd)->e_flags;
252b5132
RH		 12083 out_flags = elf_elfheader (obfd)->e_flags;
12084
fc830a83
NC		 12085 if (elf_flags_init (obfd)
12086 && EF_ARM_EABI_VERSION (out_flags) == EF_ARM_EABI_UNKNOWN
12087 && in_flags != out_flags)
252b5132 12088 {
252b5132 12089 /* Cannot mix APCS26 and APCS32 code. */
fd2ec330 12090 if ((in_flags & EF_ARM_APCS_26) != (out_flags & EF_ARM_APCS_26))
b34976b6 12091 return FALSE;
252b5132
RH		 12092
12093 /* Cannot mix float APCS and non-float APCS code. */
fd2ec330 12094 if ((in_flags & EF_ARM_APCS_FLOAT) != (out_flags & EF_ARM_APCS_FLOAT))
b34976b6 12095 return FALSE;
252b5132
RH		 12096
12097 /* If the src and dest have different interworking flags
99059e56 12098 then turn off the interworking bit. */
fd2ec330 12099 if ((in_flags & EF_ARM_INTERWORK) != (out_flags & EF_ARM_INTERWORK))
252b5132 12100 {
fd2ec330 12101 if (out_flags & EF_ARM_INTERWORK)
d003868e
AM		 12102 _bfd_error_handler
12103 (_("Warning: Clearing the interworking flag of %B because non-interworking code in %B has been linked with it"),
12104 obfd, ibfd);
252b5132 12105
fd2ec330 12106 in_flags &= ~EF_ARM_INTERWORK;
252b5132 12107 }
1006ba19
PB		 12108
12109 /* Likewise for PIC, though don't warn for this case. */
fd2ec330
PB		 12110 if ((in_flags & EF_ARM_PIC) != (out_flags & EF_ARM_PIC))
12111 in_flags &= ~EF_ARM_PIC;
252b5132
RH		 12112 }
12113
12114 elf_elfheader (obfd)->e_flags = in_flags;
b34976b6 12115 elf_flags_init (obfd) = TRUE;
252b5132 12116
e2349352 12117 return _bfd_elf_copy_private_bfd_data (ibfd, obfd);
ee065d83
PB		 12118}
12119
12120/* Values for Tag_ABI_PCS_R9_use. */
12121enum
12122{
12123 AEABI_R9_V6,
12124 AEABI_R9_SB,
12125 AEABI_R9_TLS,
12126 AEABI_R9_unused
12127};
12128
12129/* Values for Tag_ABI_PCS_RW_data. */
12130enum
12131{
12132 AEABI_PCS_RW_data_absolute,
12133 AEABI_PCS_RW_data_PCrel,
12134 AEABI_PCS_RW_data_SBrel,
12135 AEABI_PCS_RW_data_unused
12136};
12137
12138/* Values for Tag_ABI_enum_size. */
12139enum
12140{
12141 AEABI_enum_unused,
12142 AEABI_enum_short,
12143 AEABI_enum_wide,
12144 AEABI_enum_forced_wide
12145};
12146
104d59d1
JM		 12147/* Determine whether an object attribute tag takes an integer, a
12148 string or both. */
906e58ca 12149
104d59d1
JM		 12150static int
12151elf32_arm_obj_attrs_arg_type (int tag)
12152{
12153 if (tag == Tag_compatibility)
3483fe2e 12154 return ATTR_TYPE_FLAG_INT_VAL | ATTR_TYPE_FLAG_STR_VAL;
2d0bb761 12155 else if (tag == Tag_nodefaults)
3483fe2e
AS		 12156 return ATTR_TYPE_FLAG_INT_VAL | ATTR_TYPE_FLAG_NO_DEFAULT;
12157 else if (tag == Tag_CPU_raw_name || tag == Tag_CPU_name)
12158 return ATTR_TYPE_FLAG_STR_VAL;
104d59d1 12159 else if (tag < 32)
3483fe2e 12160 return ATTR_TYPE_FLAG_INT_VAL;
104d59d1 12161 else
3483fe2e 12162 return (tag & 1) != 0 ? ATTR_TYPE_FLAG_STR_VAL : ATTR_TYPE_FLAG_INT_VAL;
104d59d1
JM		 12163}
12164
5aa6ff7c
AS		 12165/* The ABI defines that Tag_conformance should be emitted first, and that
12166 Tag_nodefaults should be second (if either is defined). This sets those
12167 two positions, and bumps up the position of all the remaining tags to
12168 compensate. */
12169static int
12170elf32_arm_obj_attrs_order (int num)
12171{
3de4a297 12172 if (num == LEAST_KNOWN_OBJ_ATTRIBUTE)
5aa6ff7c 12173 return Tag_conformance;
3de4a297 12174 if (num == LEAST_KNOWN_OBJ_ATTRIBUTE + 1)
5aa6ff7c
AS		 12175 return Tag_nodefaults;
12176 if ((num - 2) < Tag_nodefaults)
12177 return num - 2;
12178 if ((num - 1) < Tag_conformance)
12179 return num - 1;
12180 return num;
12181}
12182
e8b36cd1
JM		 12183/* Attribute numbers >=64 (mod 128) can be safely ignored. */
12184static bfd_boolean
12185elf32_arm_obj_attrs_handle_unknown (bfd *abfd, int tag)
12186{
12187 if ((tag & 127) < 64)
12188 {
12189 _bfd_error_handler
12190 (_("%B: Unknown mandatory EABI object attribute %d"),
12191 abfd, tag);
12192 bfd_set_error (bfd_error_bad_value);
12193 return FALSE;
12194 }
12195 else
12196 {
12197 _bfd_error_handler
12198 (_("Warning: %B: Unknown EABI object attribute %d"),
12199 abfd, tag);
12200 return TRUE;
12201 }
12202}
12203
91e22acd
AS		 12204/* Read the architecture from the Tag_also_compatible_with attribute, if any.
12205 Returns -1 if no architecture could be read. */
12206
12207static int
12208get_secondary_compatible_arch (bfd *abfd)
12209{
12210 obj_attribute *attr =
12211 &elf_known_obj_attributes_proc (abfd)[Tag_also_compatible_with];
12212
12213 /* Note: the tag and its argument below are uleb128 values, though
12214 currently-defined values fit in one byte for each. */
12215 if (attr->s
12216 && attr->s[0] == Tag_CPU_arch
12217 && (attr->s[1] & 128) != 128
12218 && attr->s[2] == 0)
12219 return attr->s[1];
12220
12221 /* This tag is "safely ignorable", so don't complain if it looks funny. */
12222 return -1;
12223}
12224
12225/* Set, or unset, the architecture of the Tag_also_compatible_with attribute.
12226 The tag is removed if ARCH is -1. */
12227
8e79c3df 12228static void
91e22acd 12229set_secondary_compatible_arch (bfd *abfd, int arch)
8e79c3df 12230{
91e22acd
AS		 12231 obj_attribute *attr =
12232 &elf_known_obj_attributes_proc (abfd)[Tag_also_compatible_with];
8e79c3df 12233
91e22acd
AS		 12234 if (arch == -1)
12235 {
12236 attr->s = NULL;
12237 return;
8e79c3df 12238 }
91e22acd
AS		 12239
12240 /* Note: the tag and its argument below are uleb128 values, though
12241 currently-defined values fit in one byte for each. */
12242 if (!attr->s)
21d799b5 12243 attr->s = (char *) bfd_alloc (abfd, 3);
91e22acd
AS		 12244 attr->s[0] = Tag_CPU_arch;
12245 attr->s[1] = arch;
12246 attr->s[2] = '\0';
8e79c3df
CM		 12247}
12248
91e22acd
AS		 12249/* Combine two values for Tag_CPU_arch, taking secondary compatibility tags
12250 into account. */
12251
12252static int
12253tag_cpu_arch_combine (bfd *ibfd, int oldtag, int *secondary_compat_out,
12254 int newtag, int secondary_compat)
8e79c3df 12255{
91e22acd
AS		 12256#define T(X) TAG_CPU_ARCH_##X
12257 int tagl, tagh, result;
12258 const int v6t2[] =
12259 {
12260 T(V6T2), /* PRE_V4. */
12261 T(V6T2), /* V4. */
12262 T(V6T2), /* V4T. */
12263 T(V6T2), /* V5T. */
12264 T(V6T2), /* V5TE. */
12265 T(V6T2), /* V5TEJ. */
12266 T(V6T2), /* V6. */
12267 T(V7), /* V6KZ. */
12268 T(V6T2) /* V6T2. */
12269 };
12270 const int v6k[] =
12271 {
12272 T(V6K), /* PRE_V4. */
12273 T(V6K), /* V4. */
12274 T(V6K), /* V4T. */
12275 T(V6K), /* V5T. */
12276 T(V6K), /* V5TE. */
12277 T(V6K), /* V5TEJ. */
12278 T(V6K), /* V6. */
12279 T(V6KZ), /* V6KZ. */
12280 T(V7), /* V6T2. */
12281 T(V6K) /* V6K. */
12282 };
12283 const int v7[] =
12284 {
12285 T(V7), /* PRE_V4. */
12286 T(V7), /* V4. */
12287 T(V7), /* V4T. */
12288 T(V7), /* V5T. */
12289 T(V7), /* V5TE. */
12290 T(V7), /* V5TEJ. */
12291 T(V7), /* V6. */
12292 T(V7), /* V6KZ. */
12293 T(V7), /* V6T2. */
12294 T(V7), /* V6K. */
12295 T(V7) /* V7. */
12296 };
12297 const int v6_m[] =
12298 {
12299 -1, /* PRE_V4. */
12300 -1, /* V4. */
12301 T(V6K), /* V4T. */
12302 T(V6K), /* V5T. */
12303 T(V6K), /* V5TE. */
12304 T(V6K), /* V5TEJ. */
12305 T(V6K), /* V6. */
12306 T(V6KZ), /* V6KZ. */
12307 T(V7), /* V6T2. */
12308 T(V6K), /* V6K. */
12309 T(V7), /* V7. */
12310 T(V6_M) /* V6_M. */
12311 };
12312 const int v6s_m[] =
12313 {
12314 -1, /* PRE_V4. */
12315 -1, /* V4. */
12316 T(V6K), /* V4T. */
12317 T(V6K), /* V5T. */
12318 T(V6K), /* V5TE. */
12319 T(V6K), /* V5TEJ. */
12320 T(V6K), /* V6. */
12321 T(V6KZ), /* V6KZ. */
12322 T(V7), /* V6T2. */
12323 T(V6K), /* V6K. */
12324 T(V7), /* V7. */
12325 T(V6S_M), /* V6_M. */
12326 T(V6S_M) /* V6S_M. */
12327 };
9e3c6df6
PB		 12328 const int v7e_m[] =
12329 {
12330 -1, /* PRE_V4. */
12331 -1, /* V4. */
12332 T(V7E_M), /* V4T. */
12333 T(V7E_M), /* V5T. */
12334 T(V7E_M), /* V5TE. */
12335 T(V7E_M), /* V5TEJ. */
12336 T(V7E_M), /* V6. */
12337 T(V7E_M), /* V6KZ. */
12338 T(V7E_M), /* V6T2. */
12339 T(V7E_M), /* V6K. */
12340 T(V7E_M), /* V7. */
12341 T(V7E_M), /* V6_M. */
12342 T(V7E_M), /* V6S_M. */
12343 T(V7E_M) /* V7E_M. */
12344 };
bca38921
MGD		 12345 const int v8[] =
12346 {
12347 T(V8), /* PRE_V4. */
12348 T(V8), /* V4. */
12349 T(V8), /* V4T. */
12350 T(V8), /* V5T. */
12351 T(V8), /* V5TE. */
12352 T(V8), /* V5TEJ. */
12353 T(V8), /* V6. */
12354 T(V8), /* V6KZ. */
12355 T(V8), /* V6T2. */
12356 T(V8), /* V6K. */
12357 T(V8), /* V7. */
12358 T(V8), /* V6_M. */
12359 T(V8), /* V6S_M. */
12360 T(V8), /* V7E_M. */
12361 T(V8) /* V8. */
12362 };
2fd158eb
TP		 12363 const int v8m_baseline[] =
12364 {
12365 -1, /* PRE_V4. */
12366 -1, /* V4. */
12367 -1, /* V4T. */
12368 -1, /* V5T. */
12369 -1, /* V5TE. */
12370 -1, /* V5TEJ. */
12371 -1, /* V6. */
12372 -1, /* V6KZ. */
12373 -1, /* V6T2. */
12374 -1, /* V6K. */
12375 -1, /* V7. */
12376 T(V8M_BASE), /* V6_M. */
12377 T(V8M_BASE), /* V6S_M. */
12378 -1, /* V7E_M. */
12379 -1, /* V8. */
12380 -1,
12381 T(V8M_BASE) /* V8-M BASELINE. */
12382 };
12383 const int v8m_mainline[] =
12384 {
12385 -1, /* PRE_V4. */
12386 -1, /* V4. */
12387 -1, /* V4T. */
12388 -1, /* V5T. */
12389 -1, /* V5TE. */
12390 -1, /* V5TEJ. */
12391 -1, /* V6. */
12392 -1, /* V6KZ. */
12393 -1, /* V6T2. */
12394 -1, /* V6K. */
12395 T(V8M_MAIN), /* V7. */
12396 T(V8M_MAIN), /* V6_M. */
12397 T(V8M_MAIN), /* V6S_M. */
12398 T(V8M_MAIN), /* V7E_M. */
12399 -1, /* V8. */
12400 -1,
12401 T(V8M_MAIN), /* V8-M BASELINE. */
12402 T(V8M_MAIN) /* V8-M MAINLINE. */
12403 };
91e22acd
AS		 12404 const int v4t_plus_v6_m[] =
12405 {
12406 -1, /* PRE_V4. */
12407 -1, /* V4. */
12408 T(V4T), /* V4T. */
12409 T(V5T), /* V5T. */
12410 T(V5TE), /* V5TE. */
12411 T(V5TEJ), /* V5TEJ. */
12412 T(V6), /* V6. */
12413 T(V6KZ), /* V6KZ. */
12414 T(V6T2), /* V6T2. */
12415 T(V6K), /* V6K. */
12416 T(V7), /* V7. */
12417 T(V6_M), /* V6_M. */
12418 T(V6S_M), /* V6S_M. */
9e3c6df6 12419 T(V7E_M), /* V7E_M. */
bca38921 12420 T(V8), /* V8. */
4ed7ed8d 12421 -1, /* Unused. */
2fd158eb
TP		 12422 T(V8M_BASE), /* V8-M BASELINE. */
12423 T(V8M_MAIN), /* V8-M MAINLINE. */
91e22acd
AS		 12424 T(V4T_PLUS_V6_M) /* V4T plus V6_M. */
12425 };
12426 const int *comb[] =
12427 {
12428 v6t2,
12429 v6k,
12430 v7,
12431 v6_m,
12432 v6s_m,
9e3c6df6 12433 v7e_m,
bca38921 12434 v8,
4ed7ed8d 12435 NULL,
2fd158eb
TP		 12436 v8m_baseline,
12437 v8m_mainline,
91e22acd
AS		 12438 /* Pseudo-architecture. */
12439 v4t_plus_v6_m
12440 };
12441
12442 /* Check we've not got a higher architecture than we know about. */
12443
9e3c6df6 12444 if (oldtag > MAX_TAG_CPU_ARCH || newtag > MAX_TAG_CPU_ARCH)
91e22acd 12445 {
3895f852 12446 _bfd_error_handler (_("error: %B: Unknown CPU architecture"), ibfd);
91e22acd
AS		 12447 return -1;
12448 }
12449
12450 /* Override old tag if we have a Tag_also_compatible_with on the output. */
12451
12452 if ((oldtag == T(V6_M) && *secondary_compat_out == T(V4T))
12453 || (oldtag == T(V4T) && *secondary_compat_out == T(V6_M)))
12454 oldtag = T(V4T_PLUS_V6_M);
12455
12456 /* And override the new tag if we have a Tag_also_compatible_with on the
12457 input. */
12458
12459 if ((newtag == T(V6_M) && secondary_compat == T(V4T))
12460 || (newtag == T(V4T) && secondary_compat == T(V6_M)))
12461 newtag = T(V4T_PLUS_V6_M);
12462
12463 tagl = (oldtag < newtag) ? oldtag : newtag;
12464 result = tagh = (oldtag > newtag) ? oldtag : newtag;
12465
12466 /* Architectures before V6KZ add features monotonically. */
12467 if (tagh <= TAG_CPU_ARCH_V6KZ)
12468 return result;
12469
4ed7ed8d 12470 result = comb[tagh - T(V6T2)] ? comb[tagh - T(V6T2)][tagl] : -1;
91e22acd
AS		 12471
12472 /* Use Tag_CPU_arch == V4T and Tag_also_compatible_with (Tag_CPU_arch V6_M)
12473 as the canonical version. */
12474 if (result == T(V4T_PLUS_V6_M))
12475 {
12476 result = T(V4T);
12477 *secondary_compat_out = T(V6_M);
12478 }
12479 else
12480 *secondary_compat_out = -1;
12481
12482 if (result == -1)
12483 {
3895f852 12484 _bfd_error_handler (_("error: %B: Conflicting CPU architectures %d/%d"),
91e22acd
AS		 12485 ibfd, oldtag, newtag);
12486 return -1;
12487 }
12488
12489 return result;
12490#undef T
8e79c3df
CM		 12491}
12492
ac56ee8f
MGD		 12493/* Query attributes object to see if integer divide instructions may be
12494 present in an object. */
12495static bfd_boolean
12496elf32_arm_attributes_accept_div (const obj_attribute *attr)
12497{
12498 int arch = attr[Tag_CPU_arch].i;
12499 int profile = attr[Tag_CPU_arch_profile].i;
12500
12501 switch (attr[Tag_DIV_use].i)
12502 {
12503 case 0:
12504 /* Integer divide allowed if instruction contained in archetecture. */
12505 if (arch == TAG_CPU_ARCH_V7 && (profile == 'R' || profile == 'M'))
12506 return TRUE;
12507 else if (arch >= TAG_CPU_ARCH_V7E_M)
12508 return TRUE;
12509 else
12510 return FALSE;
12511
12512 case 1:
12513 /* Integer divide explicitly prohibited. */
12514 return FALSE;
12515
12516 default:
12517 /* Unrecognised case - treat as allowing divide everywhere. */
12518 case 2:
12519 /* Integer divide allowed in ARM state. */
12520 return TRUE;
12521 }
12522}
12523
12524/* Query attributes object to see if integer divide instructions are
12525 forbidden to be in the object. This is not the inverse of
12526 elf32_arm_attributes_accept_div. */
12527static bfd_boolean
12528elf32_arm_attributes_forbid_div (const obj_attribute *attr)
12529{
12530 return attr[Tag_DIV_use].i == 1;
12531}
12532
ee065d83
PB		 12533/* Merge EABI object attributes from IBFD into OBFD. Raise an error if there
12534 are conflicting attributes. */
906e58ca 12535
ee065d83
PB		 12536static bfd_boolean
12537elf32_arm_merge_eabi_attributes (bfd *ibfd, bfd *obfd)
12538{
104d59d1
JM		 12539 obj_attribute *in_attr;
12540 obj_attribute *out_attr;
ee065d83
PB		 12541 /* Some tags have 0 = don't care, 1 = strong requirement,
12542 2 = weak requirement. */
91e22acd 12543 static const int order_021[3] = {0, 2, 1};
ee065d83 12544 int i;
91e22acd 12545 bfd_boolean result = TRUE;
9274e9de 12546 const char *sec_name = get_elf_backend_data (ibfd)->obj_attrs_section;
ee065d83 12547
3e6b1042
DJ		 12548 /* Skip the linker stubs file. This preserves previous behavior
12549 of accepting unknown attributes in the first input file - but
12550 is that a bug? */
12551 if (ibfd->flags & BFD_LINKER_CREATED)
12552 return TRUE;
12553
9274e9de
TG		 12554 /* Skip any input that hasn't attribute section.
12555 This enables to link object files without attribute section with
12556 any others. */
12557 if (bfd_get_section_by_name (ibfd, sec_name) == NULL)
12558 return TRUE;
12559
104d59d1 12560 if (!elf_known_obj_attributes_proc (obfd)[0].i)
ee065d83
PB		 12561 {
12562 /* This is the first object. Copy the attributes. */
104d59d1 12563 _bfd_elf_copy_obj_attributes (ibfd, obfd);
004ae526 12564
cd21e546
MGD		 12565 out_attr = elf_known_obj_attributes_proc (obfd);
12566
004ae526
PB		 12567 /* Use the Tag_null value to indicate the attributes have been
12568 initialized. */
cd21e546 12569 out_attr[0].i = 1;
004ae526 12570
cd21e546
MGD		 12571 /* We do not output objects with Tag_MPextension_use_legacy - we move
12572 the attribute's value to Tag_MPextension_use. */
12573 if (out_attr[Tag_MPextension_use_legacy].i != 0)
12574 {
12575 if (out_attr[Tag_MPextension_use].i != 0
12576 && out_attr[Tag_MPextension_use_legacy].i
99059e56 12577 != out_attr[Tag_MPextension_use].i)
cd21e546
MGD		 12578 {
12579 _bfd_error_handler
12580 (_("Error: %B has both the current and legacy "
12581 "Tag_MPextension_use attributes"), ibfd);
12582 result = FALSE;
12583 }
12584
12585 out_attr[Tag_MPextension_use] =
12586 out_attr[Tag_MPextension_use_legacy];
12587 out_attr[Tag_MPextension_use_legacy].type = 0;
12588 out_attr[Tag_MPextension_use_legacy].i = 0;
12589 }
12590
12591 return result;
ee065d83
PB		 12592 }
12593
104d59d1
JM		 12594 in_attr = elf_known_obj_attributes_proc (ibfd);
12595 out_attr = elf_known_obj_attributes_proc (obfd);
ee065d83
PB		 12596 /* This needs to happen before Tag_ABI_FP_number_model is merged. */
12597 if (in_attr[Tag_ABI_VFP_args].i != out_attr[Tag_ABI_VFP_args].i)
12598 {
5c294fee
TG		 12599 /* Ignore mismatches if the object doesn't use floating point or is
12600 floating point ABI independent. */
12601 if (out_attr[Tag_ABI_FP_number_model].i == AEABI_FP_number_model_none
12602 || (in_attr[Tag_ABI_FP_number_model].i != AEABI_FP_number_model_none
12603 && out_attr[Tag_ABI_VFP_args].i == AEABI_VFP_args_compatible))
ee065d83 12604 out_attr[Tag_ABI_VFP_args].i = in_attr[Tag_ABI_VFP_args].i;
5c294fee
TG		 12605 else if (in_attr[Tag_ABI_FP_number_model].i != AEABI_FP_number_model_none
12606 && in_attr[Tag_ABI_VFP_args].i != AEABI_VFP_args_compatible)
ee065d83
PB		 12607 {
12608 _bfd_error_handler
3895f852 12609 (_("error: %B uses VFP register arguments, %B does not"),
deddc40b
NS		 12610 in_attr[Tag_ABI_VFP_args].i ? ibfd : obfd,
12611 in_attr[Tag_ABI_VFP_args].i ? obfd : ibfd);
91e22acd 12612 result = FALSE;
ee065d83
PB		 12613 }
12614 }
12615
3de4a297 12616 for (i = LEAST_KNOWN_OBJ_ATTRIBUTE; i < NUM_KNOWN_OBJ_ATTRIBUTES; i++)
ee065d83
PB		 12617 {
12618 /* Merge this attribute with existing attributes. */
12619 switch (i)
12620 {
12621 case Tag_CPU_raw_name:
12622 case Tag_CPU_name:
6a631e86 12623 /* These are merged after Tag_CPU_arch. */
ee065d83
PB		 12624 break;
12625
12626 case Tag_ABI_optimization_goals:
12627 case Tag_ABI_FP_optimization_goals:
12628 /* Use the first value seen. */
12629 break;
12630
12631 case Tag_CPU_arch:
91e22acd
AS		 12632 {
12633 int secondary_compat = -1, secondary_compat_out = -1;
12634 unsigned int saved_out_attr = out_attr[i].i;
70e99720
TG		 12635 int arch_attr;
12636 static const char *name_table[] =
12637 {
91e22acd
AS		 12638 /* These aren't real CPU names, but we can't guess
12639 that from the architecture version alone. */
12640 "Pre v4",
12641 "ARM v4",
12642 "ARM v4T",
12643 "ARM v5T",
12644 "ARM v5TE",
12645 "ARM v5TEJ",
12646 "ARM v6",
12647 "ARM v6KZ",
12648 "ARM v6T2",
12649 "ARM v6K",
12650 "ARM v7",
12651 "ARM v6-M",
bca38921 12652 "ARM v6S-M",
2fd158eb
TP		 12653 "ARM v8",
12654 "",
12655 "ARM v8-M.baseline",
12656 "ARM v8-M.mainline",
91e22acd
AS		 12657 };
12658
12659 /* Merge Tag_CPU_arch and Tag_also_compatible_with. */
12660 secondary_compat = get_secondary_compatible_arch (ibfd);
12661 secondary_compat_out = get_secondary_compatible_arch (obfd);
70e99720
TG		 12662 arch_attr = tag_cpu_arch_combine (ibfd, out_attr[i].i,
12663 &secondary_compat_out,
12664 in_attr[i].i,
12665 secondary_compat);
12666
12667 /* Return with error if failed to merge. */
12668 if (arch_attr == -1)
12669 return FALSE;
12670
12671 out_attr[i].i = arch_attr;
12672
91e22acd
AS		 12673 set_secondary_compatible_arch (obfd, secondary_compat_out);
12674
12675 /* Merge Tag_CPU_name and Tag_CPU_raw_name. */
12676 if (out_attr[i].i == saved_out_attr)
12677 ; /* Leave the names alone. */
12678 else if (out_attr[i].i == in_attr[i].i)
12679 {
12680 /* The output architecture has been changed to match the
12681 input architecture. Use the input names. */
12682 out_attr[Tag_CPU_name].s = in_attr[Tag_CPU_name].s
12683 ? _bfd_elf_attr_strdup (obfd, in_attr[Tag_CPU_name].s)
12684 : NULL;
12685 out_attr[Tag_CPU_raw_name].s = in_attr[Tag_CPU_raw_name].s
12686 ? _bfd_elf_attr_strdup (obfd, in_attr[Tag_CPU_raw_name].s)
12687 : NULL;
12688 }
12689 else
12690 {
12691 out_attr[Tag_CPU_name].s = NULL;
12692 out_attr[Tag_CPU_raw_name].s = NULL;
12693 }
12694
12695 /* If we still don't have a value for Tag_CPU_name,
12696 make one up now. Tag_CPU_raw_name remains blank. */
12697 if (out_attr[Tag_CPU_name].s == NULL
12698 && out_attr[i].i < ARRAY_SIZE (name_table))
12699 out_attr[Tag_CPU_name].s =
12700 _bfd_elf_attr_strdup (obfd, name_table[out_attr[i].i]);
12701 }
12702 break;
12703
ee065d83
PB		 12704 case Tag_ARM_ISA_use:
12705 case Tag_THUMB_ISA_use:
ee065d83 12706 case Tag_WMMX_arch:
91e22acd
AS		 12707 case Tag_Advanced_SIMD_arch:
12708 /* ??? Do Advanced_SIMD (NEON) and WMMX conflict? */
ee065d83 12709 case Tag_ABI_FP_rounding:
ee065d83
PB		 12710 case Tag_ABI_FP_exceptions:
12711 case Tag_ABI_FP_user_exceptions:
12712 case Tag_ABI_FP_number_model:
75375b3e 12713 case Tag_FP_HP_extension:
91e22acd
AS		 12714 case Tag_CPU_unaligned_access:
12715 case Tag_T2EE_use:
91e22acd 12716 case Tag_MPextension_use:
ee065d83
PB		 12717 /* Use the largest value specified. */
12718 if (in_attr[i].i > out_attr[i].i)
12719 out_attr[i].i = in_attr[i].i;
12720 break;
12721
75375b3e 12722 case Tag_ABI_align_preserved:
91e22acd
AS		 12723 case Tag_ABI_PCS_RO_data:
12724 /* Use the smallest value specified. */
12725 if (in_attr[i].i < out_attr[i].i)
12726 out_attr[i].i = in_attr[i].i;
12727 break;
12728
75375b3e 12729 case Tag_ABI_align_needed:
91e22acd 12730 if ((in_attr[i].i > 0 || out_attr[i].i > 0)
75375b3e
MGD		 12731 && (in_attr[Tag_ABI_align_preserved].i == 0
12732 || out_attr[Tag_ABI_align_preserved].i == 0))
ee065d83 12733 {
91e22acd
AS		 12734 /* This error message should be enabled once all non-conformant
12735 binaries in the toolchain have had the attributes set
12736 properly.
ee065d83 12737 _bfd_error_handler
3895f852 12738 (_("error: %B: 8-byte data alignment conflicts with %B"),
91e22acd
AS		 12739 obfd, ibfd);
12740 result = FALSE; */
ee065d83 12741 }
91e22acd
AS		 12742 /* Fall through. */
12743 case Tag_ABI_FP_denormal:
12744 case Tag_ABI_PCS_GOT_use:
12745 /* Use the "greatest" from the sequence 0, 2, 1, or the largest
12746 value if greater than 2 (for future-proofing). */
12747 if ((in_attr[i].i > 2 && in_attr[i].i > out_attr[i].i)
12748 || (in_attr[i].i <= 2 && out_attr[i].i <= 2
12749 && order_021[in_attr[i].i] > order_021[out_attr[i].i]))
ee065d83
PB		 12750 out_attr[i].i = in_attr[i].i;
12751 break;
91e22acd 12752
75375b3e
MGD		 12753 case Tag_Virtualization_use:
12754 /* The virtualization tag effectively stores two bits of
12755 information: the intended use of TrustZone (in bit 0), and the
12756 intended use of Virtualization (in bit 1). */
12757 if (out_attr[i].i == 0)
12758 out_attr[i].i = in_attr[i].i;
12759 else if (in_attr[i].i != 0
12760 && in_attr[i].i != out_attr[i].i)
12761 {
12762 if (in_attr[i].i <= 3 && out_attr[i].i <= 3)
12763 out_attr[i].i = 3;
12764 else
12765 {
12766 _bfd_error_handler
12767 (_("error: %B: unable to merge virtualization attributes "
12768 "with %B"),
12769 obfd, ibfd);
12770 result = FALSE;
12771 }
12772 }
12773 break;
91e22acd
AS		 12774
12775 case Tag_CPU_arch_profile:
12776 if (out_attr[i].i != in_attr[i].i)
12777 {
12778 /* 0 will merge with anything.
12779 'A' and 'S' merge to 'A'.
12780 'R' and 'S' merge to 'R'.
99059e56 12781 'M' and 'A|R|S' is an error. */
91e22acd
AS		 12782 if (out_attr[i].i == 0
12783 || (out_attr[i].i == 'S'
12784 && (in_attr[i].i == 'A' || in_attr[i].i == 'R')))
12785 out_attr[i].i = in_attr[i].i;
12786 else if (in_attr[i].i == 0
12787 || (in_attr[i].i == 'S'
12788 && (out_attr[i].i == 'A' || out_attr[i].i == 'R')))
6a631e86 12789 ; /* Do nothing. */
91e22acd
AS		 12790 else
12791 {
12792 _bfd_error_handler
3895f852 12793 (_("error: %B: Conflicting architecture profiles %c/%c"),
91e22acd
AS		 12794 ibfd,
12795 in_attr[i].i ? in_attr[i].i : '0',
12796 out_attr[i].i ? out_attr[i].i : '0');
12797 result = FALSE;
12798 }
12799 }
12800 break;
15afaa63
TP		 12801
12802 case Tag_DSP_extension:
12803 /* No need to change output value if any of:
12804 - pre (<=) ARMv5T input architecture (do not have DSP)
12805 - M input profile not ARMv7E-M and do not have DSP. */
12806 if (in_attr[Tag_CPU_arch].i <= 3
12807 || (in_attr[Tag_CPU_arch_profile].i == 'M'
12808 && in_attr[Tag_CPU_arch].i != 13
12809 && in_attr[i].i == 0))
12810 ; /* Do nothing. */
12811 /* Output value should be 0 if DSP part of architecture, ie.
12812 - post (>=) ARMv5te architecture output
12813 - A, R or S profile output or ARMv7E-M output architecture. */
12814 else if (out_attr[Tag_CPU_arch].i >= 4
12815 && (out_attr[Tag_CPU_arch_profile].i == 'A'
12816 || out_attr[Tag_CPU_arch_profile].i == 'R'
12817 || out_attr[Tag_CPU_arch_profile].i == 'S'
12818 || out_attr[Tag_CPU_arch].i == 13))
12819 out_attr[i].i = 0;
12820 /* Otherwise, DSP instructions are added and not part of output
12821 architecture. */
12822 else
12823 out_attr[i].i = 1;
12824 break;
12825
75375b3e 12826 case Tag_FP_arch:
62f3b8c8 12827 {
4547cb56
NC		 12828 /* Tag_ABI_HardFP_use is handled along with Tag_FP_arch since
12829 the meaning of Tag_ABI_HardFP_use depends on Tag_FP_arch
12830 when it's 0. It might mean absence of FP hardware if
99654aaf 12831 Tag_FP_arch is zero. */
4547cb56 12832
a715796b 12833#define VFP_VERSION_COUNT 9
62f3b8c8
PB		 12834 static const struct
12835 {
12836 int ver;
12837 int regs;
bca38921 12838 } vfp_versions[VFP_VERSION_COUNT] =
62f3b8c8
PB		 12839 {
12840 {0, 0},
12841 {1, 16},
12842 {2, 16},
12843 {3, 32},
12844 {3, 16},
12845 {4, 32},
bca38921 12846 {4, 16},
a715796b
TG		 12847 {8, 32},
12848 {8, 16}
62f3b8c8
PB		 12849 };
12850 int ver;
12851 int regs;
12852 int newval;
12853
4547cb56
NC		 12854 /* If the output has no requirement about FP hardware,
12855 follow the requirement of the input. */
12856 if (out_attr[i].i == 0)
12857 {
12858 BFD_ASSERT (out_attr[Tag_ABI_HardFP_use].i == 0);
12859 out_attr[i].i = in_attr[i].i;
12860 out_attr[Tag_ABI_HardFP_use].i
12861 = in_attr[Tag_ABI_HardFP_use].i;
12862 break;
12863 }
12864 /* If the input has no requirement about FP hardware, do
12865 nothing. */
12866 else if (in_attr[i].i == 0)
12867 {
12868 BFD_ASSERT (in_attr[Tag_ABI_HardFP_use].i == 0);
12869 break;
12870 }
12871
12872 /* Both the input and the output have nonzero Tag_FP_arch.
99654aaf 12873 So Tag_ABI_HardFP_use is implied by Tag_FP_arch when it's zero. */
4547cb56
NC		 12874
12875 /* If both the input and the output have zero Tag_ABI_HardFP_use,
12876 do nothing. */
12877 if (in_attr[Tag_ABI_HardFP_use].i == 0
12878 && out_attr[Tag_ABI_HardFP_use].i == 0)
12879 ;
12880 /* If the input and the output have different Tag_ABI_HardFP_use,
99654aaf 12881 the combination of them is 0 (implied by Tag_FP_arch). */
4547cb56
NC		 12882 else if (in_attr[Tag_ABI_HardFP_use].i
12883 != out_attr[Tag_ABI_HardFP_use].i)
99654aaf 12884 out_attr[Tag_ABI_HardFP_use].i = 0;
4547cb56
NC		 12885
12886 /* Now we can handle Tag_FP_arch. */
12887
bca38921
MGD		 12888 /* Values of VFP_VERSION_COUNT or more aren't defined, so just
12889 pick the biggest. */
12890 if (in_attr[i].i >= VFP_VERSION_COUNT
12891 && in_attr[i].i > out_attr[i].i)
62f3b8c8
PB		 12892 {
12893 out_attr[i] = in_attr[i];
12894 break;
12895 }
12896 /* The output uses the superset of input features
12897 (ISA version) and registers. */
12898 ver = vfp_versions[in_attr[i].i].ver;
12899 if (ver < vfp_versions[out_attr[i].i].ver)
12900 ver = vfp_versions[out_attr[i].i].ver;
12901 regs = vfp_versions[in_attr[i].i].regs;
12902 if (regs < vfp_versions[out_attr[i].i].regs)
12903 regs = vfp_versions[out_attr[i].i].regs;
12904 /* This assumes all possible supersets are also a valid
99059e56 12905 options. */
bca38921 12906 for (newval = VFP_VERSION_COUNT - 1; newval > 0; newval--)
62f3b8c8
PB		 12907 {
12908 if (regs == vfp_versions[newval].regs
12909 && ver == vfp_versions[newval].ver)
12910 break;
12911 }
12912 out_attr[i].i = newval;
12913 }
b1cc4aeb 12914 break;
ee065d83
PB		 12915 case Tag_PCS_config:
12916 if (out_attr[i].i == 0)
12917 out_attr[i].i = in_attr[i].i;
b6009aca 12918 else if (in_attr[i].i != 0 && out_attr[i].i != in_attr[i].i)
ee065d83
PB		 12919 {
12920 /* It's sometimes ok to mix different configs, so this is only
99059e56 12921 a warning. */
ee065d83
PB		 12922 _bfd_error_handler
12923 (_("Warning: %B: Conflicting platform configuration"), ibfd);
12924 }
12925 break;
12926 case Tag_ABI_PCS_R9_use:
004ae526
PB		 12927 if (in_attr[i].i != out_attr[i].i
12928 && out_attr[i].i != AEABI_R9_unused
ee065d83
PB		 12929 && in_attr[i].i != AEABI_R9_unused)
12930 {
12931 _bfd_error_handler
3895f852 12932 (_("error: %B: Conflicting use of R9"), ibfd);
91e22acd 12933 result = FALSE;
ee065d83
PB		 12934 }
12935 if (out_attr[i].i == AEABI_R9_unused)
12936 out_attr[i].i = in_attr[i].i;
12937 break;
12938 case Tag_ABI_PCS_RW_data:
12939 if (in_attr[i].i == AEABI_PCS_RW_data_SBrel
12940 && out_attr[Tag_ABI_PCS_R9_use].i != AEABI_R9_SB
12941 && out_attr[Tag_ABI_PCS_R9_use].i != AEABI_R9_unused)
12942 {
12943 _bfd_error_handler
3895f852 12944 (_("error: %B: SB relative addressing conflicts with use of R9"),
ee065d83 12945 ibfd);
91e22acd 12946 result = FALSE;
ee065d83
PB		 12947 }
12948 /* Use the smallest value specified. */
12949 if (in_attr[i].i < out_attr[i].i)
12950 out_attr[i].i = in_attr[i].i;
12951 break;
ee065d83 12952 case Tag_ABI_PCS_wchar_t:
a9dc9481
JM		 12953 if (out_attr[i].i && in_attr[i].i && out_attr[i].i != in_attr[i].i
12954 && !elf_arm_tdata (obfd)->no_wchar_size_warning)
ee065d83
PB		 12955 {
12956 _bfd_error_handler
a9dc9481
JM		 12957 (_("warning: %B uses %u-byte wchar_t yet the output is to use %u-byte wchar_t; use of wchar_t values across objects may fail"),
12958 ibfd, in_attr[i].i, out_attr[i].i);
ee065d83 12959 }
a9dc9481 12960 else if (in_attr[i].i && !out_attr[i].i)
ee065d83
PB		 12961 out_attr[i].i = in_attr[i].i;
12962 break;
ee065d83
PB		 12963 case Tag_ABI_enum_size:
12964 if (in_attr[i].i != AEABI_enum_unused)
12965 {
12966 if (out_attr[i].i == AEABI_enum_unused
12967 || out_attr[i].i == AEABI_enum_forced_wide)
12968 {
12969 /* The existing object is compatible with anything.
12970 Use whatever requirements the new object has. */
12971 out_attr[i].i = in_attr[i].i;
12972 }
12973 else if (in_attr[i].i != AEABI_enum_forced_wide
bf21ed78 12974 && out_attr[i].i != in_attr[i].i
0ffa91dd 12975 && !elf_arm_tdata (obfd)->no_enum_size_warning)
ee065d83 12976 {
91e22acd 12977 static const char *aeabi_enum_names[] =
bf21ed78 12978 { "", "variable-size", "32-bit", "" };
91e22acd
AS		 12979 const char *in_name =
12980 in_attr[i].i < ARRAY_SIZE(aeabi_enum_names)
12981 ? aeabi_enum_names[in_attr[i].i]
12982 : "<unknown>";
12983 const char *out_name =
12984 out_attr[i].i < ARRAY_SIZE(aeabi_enum_names)
12985 ? aeabi_enum_names[out_attr[i].i]
12986 : "<unknown>";
ee065d83 12987 _bfd_error_handler
bf21ed78 12988 (_("warning: %B uses %s enums yet the output is to use %s enums; use of enum values across objects may fail"),
91e22acd 12989 ibfd, in_name, out_name);
ee065d83
PB		 12990 }
12991 }
12992 break;
12993 case Tag_ABI_VFP_args:
12994 /* Aready done. */
12995 break;
12996 case Tag_ABI_WMMX_args:
12997 if (in_attr[i].i != out_attr[i].i)
12998 {
12999 _bfd_error_handler
3895f852 13000 (_("error: %B uses iWMMXt register arguments, %B does not"),
ee065d83 13001 ibfd, obfd);
91e22acd 13002 result = FALSE;
ee065d83
PB		 13003 }
13004 break;
7b86a9fa
AS		 13005 case Tag_compatibility:
13006 /* Merged in target-independent code. */
13007 break;
91e22acd 13008 case Tag_ABI_HardFP_use:
4547cb56 13009 /* This is handled along with Tag_FP_arch. */
91e22acd
AS		 13010 break;
13011 case Tag_ABI_FP_16bit_format:
13012 if (in_attr[i].i != 0 && out_attr[i].i != 0)
13013 {
13014 if (in_attr[i].i != out_attr[i].i)
13015 {
13016 _bfd_error_handler
3895f852 13017 (_("error: fp16 format mismatch between %B and %B"),
91e22acd
AS		 13018 ibfd, obfd);
13019 result = FALSE;
13020 }
13021 }
13022 if (in_attr[i].i != 0)
13023 out_attr[i].i = in_attr[i].i;
13024 break;
7b86a9fa 13025
cd21e546 13026 case Tag_DIV_use:
ac56ee8f
MGD		 13027 /* A value of zero on input means that the divide instruction may
13028 be used if available in the base architecture as specified via
13029 Tag_CPU_arch and Tag_CPU_arch_profile. A value of 1 means that
13030 the user did not want divide instructions. A value of 2
13031 explicitly means that divide instructions were allowed in ARM
13032 and Thumb state. */
13033 if (in_attr[i].i == out_attr[i].i)
13034 /* Do nothing. */ ;
13035 else if (elf32_arm_attributes_forbid_div (in_attr)
13036 && !elf32_arm_attributes_accept_div (out_attr))
13037 out_attr[i].i = 1;
13038 else if (elf32_arm_attributes_forbid_div (out_attr)
13039 && elf32_arm_attributes_accept_div (in_attr))
13040 out_attr[i].i = in_attr[i].i;
13041 else if (in_attr[i].i == 2)
13042 out_attr[i].i = in_attr[i].i;
cd21e546
MGD		 13043 break;
13044
13045 case Tag_MPextension_use_legacy:
13046 /* We don't output objects with Tag_MPextension_use_legacy - we
13047 move the value to Tag_MPextension_use. */
13048 if (in_attr[i].i != 0 && in_attr[Tag_MPextension_use].i != 0)
13049 {
13050 if (in_attr[Tag_MPextension_use].i != in_attr[i].i)
13051 {
13052 _bfd_error_handler
13053 (_("%B has has both the current and legacy "
b38cadfb 13054 "Tag_MPextension_use attributes"),
cd21e546
MGD		 13055 ibfd);
13056 result = FALSE;
13057 }
13058 }
13059
13060 if (in_attr[i].i > out_attr[Tag_MPextension_use].i)
13061 out_attr[Tag_MPextension_use] = in_attr[i];
13062
13063 break;
13064
91e22acd 13065 case Tag_nodefaults:
2d0bb761
AS		 13066 /* This tag is set if it exists, but the value is unused (and is
13067 typically zero). We don't actually need to do anything here -
13068 the merge happens automatically when the type flags are merged
13069 below. */
91e22acd
AS		 13070 break;
13071 case Tag_also_compatible_with:
13072 /* Already done in Tag_CPU_arch. */
13073 break;
13074 case Tag_conformance:
13075 /* Keep the attribute if it matches. Throw it away otherwise.
13076 No attribute means no claim to conform. */
13077 if (!in_attr[i].s || !out_attr[i].s
13078 || strcmp (in_attr[i].s, out_attr[i].s) != 0)
13079 out_attr[i].s = NULL;
13080 break;
3cfad14c 13081
91e22acd 13082 default:
e8b36cd1
JM		 13083 result
13084 = result && _bfd_elf_merge_unknown_attribute_low (ibfd, obfd, i);
91e22acd
AS		 13085 }
13086
13087 /* If out_attr was copied from in_attr then it won't have a type yet. */
13088 if (in_attr[i].type && !out_attr[i].type)
13089 out_attr[i].type = in_attr[i].type;
ee065d83
PB		 13090 }
13091
104d59d1 13092 /* Merge Tag_compatibility attributes and any common GNU ones. */
5488d830
MGD		 13093 if (!_bfd_elf_merge_object_attributes (ibfd, obfd))
13094 return FALSE;
ee065d83 13095
104d59d1 13096 /* Check for any attributes not known on ARM. */
e8b36cd1 13097 result &= _bfd_elf_merge_unknown_attribute_list (ibfd, obfd);
91e22acd 13098
91e22acd 13099 return result;
252b5132
RH		 13100}
13101
3a4a14e9
PB		 13102
13103/* Return TRUE if the two EABI versions are incompatible. */
13104
13105static bfd_boolean
13106elf32_arm_versions_compatible (unsigned iver, unsigned over)
13107{
13108 /* v4 and v5 are the same spec before and after it was released,
13109 so allow mixing them. */
13110 if ((iver == EF_ARM_EABI_VER4 && over == EF_ARM_EABI_VER5)
13111 || (iver == EF_ARM_EABI_VER5 && over == EF_ARM_EABI_VER4))
13112 return TRUE;
13113
13114 return (iver == over);
13115}
13116
252b5132
RH		 13117/* Merge backend specific data from an object file to the output
13118 object file when linking. */
9b485d32 13119
b34976b6 13120static bfd_boolean
21d799b5 13121elf32_arm_merge_private_bfd_data (bfd * ibfd, bfd * obfd);
252b5132 13122
9b485d32
NC		 13123/* Display the flags field. */
13124
b34976b6 13125static bfd_boolean
57e8b36a 13126elf32_arm_print_private_bfd_data (bfd *abfd, void * ptr)
252b5132 13127{
fc830a83
NC		 13128 FILE * file = (FILE *) ptr;
13129 unsigned long flags;
252b5132
RH		 13130
13131 BFD_ASSERT (abfd != NULL && ptr != NULL);
13132
13133 /* Print normal ELF private data. */
13134 _bfd_elf_print_private_bfd_data (abfd, ptr);
13135
fc830a83 13136 flags = elf_elfheader (abfd)->e_flags;
9b485d32
NC		 13137 /* Ignore init flag - it may not be set, despite the flags field
13138 containing valid data. */
252b5132
RH		 13139
13140 /* xgettext:c-format */
9b485d32 13141 fprintf (file, _("private flags = %lx:"), elf_elfheader (abfd)->e_flags);
252b5132 13142
fc830a83
NC		 13143 switch (EF_ARM_EABI_VERSION (flags))
13144 {
13145 case EF_ARM_EABI_UNKNOWN:
4cc11e76 13146 /* The following flag bits are GNU extensions and not part of the
fc830a83
NC		 13147 official ARM ELF extended ABI. Hence they are only decoded if
13148 the EABI version is not set. */
fd2ec330 13149 if (flags & EF_ARM_INTERWORK)
9b485d32 13150 fprintf (file, _(" [interworking enabled]"));
9a5aca8c 13151
fd2ec330 13152 if (flags & EF_ARM_APCS_26)
6c571f00 13153 fprintf (file, " [APCS-26]");
fc830a83 13154 else
6c571f00 13155 fprintf (file, " [APCS-32]");
9a5aca8c 13156
96a846ea
RE		 13157 if (flags & EF_ARM_VFP_FLOAT)
13158 fprintf (file, _(" [VFP float format]"));
fde78edd
NC		 13159 else if (flags & EF_ARM_MAVERICK_FLOAT)
13160 fprintf (file, _(" [Maverick float format]"));
96a846ea
RE		 13161 else
13162 fprintf (file, _(" [FPA float format]"));
13163
fd2ec330 13164 if (flags & EF_ARM_APCS_FLOAT)
9b485d32 13165 fprintf (file, _(" [floats passed in float registers]"));
9a5aca8c 13166
fd2ec330 13167 if (flags & EF_ARM_PIC)
9b485d32 13168 fprintf (file, _(" [position independent]"));
fc830a83 13169
fd2ec330 13170 if (flags & EF_ARM_NEW_ABI)
9b485d32 13171 fprintf (file, _(" [new ABI]"));
9a5aca8c 13172
fd2ec330 13173 if (flags & EF_ARM_OLD_ABI)
9b485d32 13174 fprintf (file, _(" [old ABI]"));
9a5aca8c 13175
fd2ec330 13176 if (flags & EF_ARM_SOFT_FLOAT)
9b485d32 13177 fprintf (file, _(" [software FP]"));
9a5aca8c 13178
96a846ea
RE		 13179 flags &= ~(EF_ARM_INTERWORK | EF_ARM_APCS_26 | EF_ARM_APCS_FLOAT
13180 | EF_ARM_PIC | EF_ARM_NEW_ABI | EF_ARM_OLD_ABI
fde78edd
NC		 13181 | EF_ARM_SOFT_FLOAT | EF_ARM_VFP_FLOAT
13182 | EF_ARM_MAVERICK_FLOAT);
fc830a83 13183 break;
9a5aca8c 13184
fc830a83 13185 case EF_ARM_EABI_VER1:
9b485d32 13186 fprintf (file, _(" [Version1 EABI]"));
9a5aca8c 13187
fc830a83 13188 if (flags & EF_ARM_SYMSARESORTED)
9b485d32 13189 fprintf (file, _(" [sorted symbol table]"));
fc830a83 13190 else
9b485d32 13191 fprintf (file, _(" [unsorted symbol table]"));
9a5aca8c 13192
fc830a83
NC		 13193 flags &= ~ EF_ARM_SYMSARESORTED;
13194 break;
9a5aca8c 13195
fd2ec330
PB		 13196 case EF_ARM_EABI_VER2:
13197 fprintf (file, _(" [Version2 EABI]"));
13198
13199 if (flags & EF_ARM_SYMSARESORTED)
13200 fprintf (file, _(" [sorted symbol table]"));
13201 else
13202 fprintf (file, _(" [unsorted symbol table]"));
13203
13204 if (flags & EF_ARM_DYNSYMSUSESEGIDX)
13205 fprintf (file, _(" [dynamic symbols use segment index]"));
13206
13207 if (flags & EF_ARM_MAPSYMSFIRST)
13208 fprintf (file, _(" [mapping symbols precede others]"));
13209
99e4ae17 13210 flags &= ~(EF_ARM_SYMSARESORTED | EF_ARM_DYNSYMSUSESEGIDX
fd2ec330
PB		 13211 | EF_ARM_MAPSYMSFIRST);
13212 break;
13213
d507cf36
PB		 13214 case EF_ARM_EABI_VER3:
13215 fprintf (file, _(" [Version3 EABI]"));
8cb51566
PB		 13216 break;
13217
13218 case EF_ARM_EABI_VER4:
13219 fprintf (file, _(" [Version4 EABI]"));
3a4a14e9 13220 goto eabi;
d507cf36 13221
3a4a14e9
PB		 13222 case EF_ARM_EABI_VER5:
13223 fprintf (file, _(" [Version5 EABI]"));
3bfcb652
NC		 13224
13225 if (flags & EF_ARM_ABI_FLOAT_SOFT)
13226 fprintf (file, _(" [soft-float ABI]"));
13227
13228 if (flags & EF_ARM_ABI_FLOAT_HARD)
13229 fprintf (file, _(" [hard-float ABI]"));
13230
13231 flags &= ~(EF_ARM_ABI_FLOAT_SOFT | EF_ARM_ABI_FLOAT_HARD);
13232
3a4a14e9 13233 eabi:
d507cf36
PB		 13234 if (flags & EF_ARM_BE8)
13235 fprintf (file, _(" [BE8]"));
13236
13237 if (flags & EF_ARM_LE8)
13238 fprintf (file, _(" [LE8]"));
13239
13240 flags &= ~(EF_ARM_LE8 | EF_ARM_BE8);
13241 break;
13242
fc830a83 13243 default:
9b485d32 13244 fprintf (file, _(" <EABI version unrecognised>"));
fc830a83
NC		 13245 break;
13246 }
252b5132 13247
fc830a83 13248 flags &= ~ EF_ARM_EABIMASK;
252b5132 13249
fc830a83 13250 if (flags & EF_ARM_RELEXEC)
9b485d32 13251 fprintf (file, _(" [relocatable executable]"));
252b5132 13252
a5721edd 13253 flags &= ~EF_ARM_RELEXEC;
fc830a83
NC		 13254
13255 if (flags)
9b485d32 13256 fprintf (file, _("<Unrecognised flag bits set>"));
9a5aca8c 13257
252b5132
RH		 13258 fputc ('\n', file);
13259
b34976b6 13260 return TRUE;
252b5132
RH		 13261}
13262
13263static int
57e8b36a 13264elf32_arm_get_symbol_type (Elf_Internal_Sym * elf_sym, int type)
252b5132 13265{
2f0ca46a
NC		 13266 switch (ELF_ST_TYPE (elf_sym->st_info))
13267 {
13268 case STT_ARM_TFUNC:
13269 return ELF_ST_TYPE (elf_sym->st_info);
ce855c42 13270
2f0ca46a
NC		 13271 case STT_ARM_16BIT:
13272 /* If the symbol is not an object, return the STT_ARM_16BIT flag.
13273 This allows us to distinguish between data used by Thumb instructions
13274 and non-data (which is probably code) inside Thumb regions of an
13275 executable. */
1a0eb693 13276 if (type != STT_OBJECT && type != STT_TLS)
2f0ca46a
NC		 13277 return ELF_ST_TYPE (elf_sym->st_info);
13278 break;
9a5aca8c 13279
ce855c42
NC		 13280 default:
13281 break;
2f0ca46a
NC		 13282 }
13283
13284 return type;
252b5132 13285}
f21f3fe0 13286
252b5132 13287static asection *
07adf181
AM		 13288elf32_arm_gc_mark_hook (asection *sec,
13289 struct bfd_link_info *info,
13290 Elf_Internal_Rela *rel,
13291 struct elf_link_hash_entry *h,
13292 Elf_Internal_Sym *sym)
252b5132
RH		 13293{
13294 if (h != NULL)
07adf181 13295 switch (ELF32_R_TYPE (rel->r_info))
252b5132
RH		 13296 {
13297 case R_ARM_GNU_VTINHERIT:
13298 case R_ARM_GNU_VTENTRY:
07adf181
AM		 13299 return NULL;
13300 }
9ad5cbcf 13301
07adf181 13302 return _bfd_elf_gc_mark_hook (sec, info, rel, h, sym);
252b5132
RH		 13303}
13304
780a67af
NC		 13305/* Update the got entry reference counts for the section being removed. */
13306
b34976b6 13307static bfd_boolean
ba93b8ac
DJ		 13308elf32_arm_gc_sweep_hook (bfd * abfd,
13309 struct bfd_link_info * info,
13310 asection * sec,
13311 const Elf_Internal_Rela * relocs)
252b5132 13312{
5e681ec4
PB		 13313 Elf_Internal_Shdr *symtab_hdr;
13314 struct elf_link_hash_entry **sym_hashes;
13315 bfd_signed_vma *local_got_refcounts;
13316 const Elf_Internal_Rela *rel, *relend;
eb043451
PB		 13317 struct elf32_arm_link_hash_table * globals;
13318
0e1862bb 13319 if (bfd_link_relocatable (info))
7dda2462
TG		 13320 return TRUE;
13321
eb043451 13322 globals = elf32_arm_hash_table (info);
4dfe6ac6
NC		 13323 if (globals == NULL)
13324 return FALSE;
5e681ec4
PB		 13325
13326 elf_section_data (sec)->local_dynrel = NULL;
13327
0ffa91dd 13328 symtab_hdr = & elf_symtab_hdr (abfd);
5e681ec4
PB		 13329 sym_hashes = elf_sym_hashes (abfd);
13330 local_got_refcounts = elf_local_got_refcounts (abfd);
13331
906e58ca 13332 check_use_blx (globals);
bd97cb95 13333
5e681ec4
PB		 13334 relend = relocs + sec->reloc_count;
13335 for (rel = relocs; rel < relend; rel++)
eb043451 13336 {
3eb128b2
AM		 13337 unsigned long r_symndx;
13338 struct elf_link_hash_entry *h = NULL;
f6e32f6d 13339 struct elf32_arm_link_hash_entry *eh;
eb043451 13340 int r_type;
34e77a92 13341 bfd_boolean call_reloc_p;
f6e32f6d
RS		 13342 bfd_boolean may_become_dynamic_p;
13343 bfd_boolean may_need_local_target_p;
34e77a92
RS		 13344 union gotplt_union *root_plt;
13345 struct arm_plt_info *arm_plt;
5e681ec4 13346
3eb128b2
AM		 13347 r_symndx = ELF32_R_SYM (rel->r_info);
13348 if (r_symndx >= symtab_hdr->sh_info)
13349 {
13350 h = sym_hashes[r_symndx - symtab_hdr->sh_info];
13351 while (h->root.type == bfd_link_hash_indirect
13352 || h->root.type == bfd_link_hash_warning)
13353 h = (struct elf_link_hash_entry *) h->root.u.i.link;
13354 }
f6e32f6d
RS		 13355 eh = (struct elf32_arm_link_hash_entry *) h;
13356
34e77a92 13357 call_reloc_p = FALSE;
f6e32f6d
RS		 13358 may_become_dynamic_p = FALSE;
13359 may_need_local_target_p = FALSE;
3eb128b2 13360
eb043451 13361 r_type = ELF32_R_TYPE (rel->r_info);
eb043451 13362 r_type = arm_real_reloc_type (globals, r_type);
eb043451
PB		 13363 switch (r_type)
13364 {
13365 case R_ARM_GOT32:
eb043451 13366 case R_ARM_GOT_PREL:
ba93b8ac
DJ		 13367 case R_ARM_TLS_GD32:
13368 case R_ARM_TLS_IE32:
3eb128b2 13369 if (h != NULL)
eb043451 13370 {
eb043451
PB		 13371 if (h->got.refcount > 0)
13372 h->got.refcount -= 1;
13373 }
13374 else if (local_got_refcounts != NULL)
13375 {
13376 if (local_got_refcounts[r_symndx] > 0)
13377 local_got_refcounts[r_symndx] -= 1;
13378 }
13379 break;
13380
ba93b8ac 13381 case R_ARM_TLS_LDM32:
4dfe6ac6 13382 globals->tls_ldm_got.refcount -= 1;
ba93b8ac
DJ		 13383 break;
13384
eb043451
PB		 13385 case R_ARM_PC24:
13386 case R_ARM_PLT32:
5b5bb741
PB		 13387 case R_ARM_CALL:
13388 case R_ARM_JUMP24:
eb043451 13389 case R_ARM_PREL31:
c19d1205 13390 case R_ARM_THM_CALL:
bd97cb95
DJ		 13391 case R_ARM_THM_JUMP24:
13392 case R_ARM_THM_JUMP19:
34e77a92 13393 call_reloc_p = TRUE;
f6e32f6d
RS		 13394 may_need_local_target_p = TRUE;
13395 break;
13396
13397 case R_ARM_ABS12:
13398 if (!globals->vxworks_p)
13399 {
13400 may_need_local_target_p = TRUE;
13401 break;
13402 }
13403 /* Fall through. */
13404 case R_ARM_ABS32:
13405 case R_ARM_ABS32_NOI:
13406 case R_ARM_REL32:
13407 case R_ARM_REL32_NOI:
b6895b4f
PB		 13408 case R_ARM_MOVW_ABS_NC:
13409 case R_ARM_MOVT_ABS:
13410 case R_ARM_MOVW_PREL_NC:
13411 case R_ARM_MOVT_PREL:
13412 case R_ARM_THM_MOVW_ABS_NC:
13413 case R_ARM_THM_MOVT_ABS:
13414 case R_ARM_THM_MOVW_PREL_NC:
13415 case R_ARM_THM_MOVT_PREL:
b7693d02 13416 /* Should the interworking branches be here also? */
0e1862bb 13417 if ((bfd_link_pic (info) || globals->root.is_relocatable_executable)
34e77a92
RS		 13418 && (sec->flags & SEC_ALLOC) != 0)
13419 {
13420 if (h == NULL
469a3493 13421 && elf32_arm_howto_from_type (r_type)->pc_relative)
34e77a92
RS		 13422 {
13423 call_reloc_p = TRUE;
13424 may_need_local_target_p = TRUE;
13425 }
13426 else
13427 may_become_dynamic_p = TRUE;
13428 }
f6e32f6d
RS		 13429 else
13430 may_need_local_target_p = TRUE;
13431 break;
b7693d02 13432
f6e32f6d
RS		 13433 default:
13434 break;
13435 }
5e681ec4 13436
34e77a92
RS		 13437 if (may_need_local_target_p
13438 && elf32_arm_get_plt_info (abfd, eh, r_symndx, &root_plt, &arm_plt))
f6e32f6d 13439 {
27586251
HPN		 13440 /* If PLT refcount book-keeping is wrong and too low, we'll
13441 see a zero value (going to -1) for the root PLT reference
13442 count. */
13443 if (root_plt->refcount >= 0)
13444 {
13445 BFD_ASSERT (root_plt->refcount != 0);
13446 root_plt->refcount -= 1;
13447 }
13448 else
13449 /* A value of -1 means the symbol has become local, forced
13450 or seeing a hidden definition. Any other negative value
13451 is an error. */
13452 BFD_ASSERT (root_plt->refcount == -1);
34e77a92
RS		 13453
13454 if (!call_reloc_p)
13455 arm_plt->noncall_refcount--;
5e681ec4 13456
f6e32f6d 13457 if (r_type == R_ARM_THM_CALL)
34e77a92 13458 arm_plt->maybe_thumb_refcount--;
bd97cb95 13459
f6e32f6d
RS		 13460 if (r_type == R_ARM_THM_JUMP24
13461 || r_type == R_ARM_THM_JUMP19)
34e77a92 13462 arm_plt->thumb_refcount--;
f6e32f6d 13463 }
5e681ec4 13464
34e77a92 13465 if (may_become_dynamic_p)
f6e32f6d
RS		 13466 {
13467 struct elf_dyn_relocs **pp;
13468 struct elf_dyn_relocs *p;
5e681ec4 13469
34e77a92 13470 if (h != NULL)
9c489990 13471 pp = &(eh->dyn_relocs);
34e77a92
RS		 13472 else
13473 {
13474 Elf_Internal_Sym *isym;
13475
13476 isym = bfd_sym_from_r_symndx (&globals->sym_cache,
13477 abfd, r_symndx);
13478 if (isym == NULL)
13479 return FALSE;
13480 pp = elf32_arm_get_local_dynreloc_list (abfd, r_symndx, isym);
13481 if (pp == NULL)
13482 return FALSE;
13483 }
9c489990 13484 for (; (p = *pp) != NULL; pp = &p->next)
f6e32f6d
RS		 13485 if (p->sec == sec)
13486 {
13487 /* Everything must go for SEC. */
13488 *pp = p->next;
13489 break;
13490 }
eb043451
PB		 13491 }
13492 }
5e681ec4 13493
b34976b6 13494 return TRUE;
252b5132
RH		 13495}
13496
780a67af
NC		 13497/* Look through the relocs for a section during the first phase. */
13498
b34976b6 13499static bfd_boolean
57e8b36a
NC		 13500elf32_arm_check_relocs (bfd *abfd, struct bfd_link_info *info,
13501 asection *sec, const Elf_Internal_Rela *relocs)
252b5132 13502{
b34976b6
AM		 13503 Elf_Internal_Shdr *symtab_hdr;
13504 struct elf_link_hash_entry **sym_hashes;
b34976b6
AM		 13505 const Elf_Internal_Rela *rel;
13506 const Elf_Internal_Rela *rel_end;
13507 bfd *dynobj;
5e681ec4 13508 asection *sreloc;
5e681ec4 13509 struct elf32_arm_link_hash_table *htab;
f6e32f6d
RS		 13510 bfd_boolean call_reloc_p;
13511 bfd_boolean may_become_dynamic_p;
13512 bfd_boolean may_need_local_target_p;
ce98a316 13513 unsigned long nsyms;
9a5aca8c 13514
0e1862bb 13515 if (bfd_link_relocatable (info))
b34976b6 13516 return TRUE;
9a5aca8c 13517
0ffa91dd
NC		 13518 BFD_ASSERT (is_arm_elf (abfd));
13519
5e681ec4 13520 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 13521 if (htab == NULL)
13522 return FALSE;
13523
5e681ec4 13524 sreloc = NULL;
9a5aca8c 13525
67687978
PB		 13526 /* Create dynamic sections for relocatable executables so that we can
13527 copy relocations. */
13528 if (htab->root.is_relocatable_executable
13529 && ! htab->root.dynamic_sections_created)
13530 {
13531 if (! _bfd_elf_link_create_dynamic_sections (abfd, info))
13532 return FALSE;
13533 }
13534
cbc704f3
RS		 13535 if (htab->root.dynobj == NULL)
13536 htab->root.dynobj = abfd;
34e77a92
RS		 13537 if (!create_ifunc_sections (info))
13538 return FALSE;
cbc704f3
RS		 13539
13540 dynobj = htab->root.dynobj;
13541
0ffa91dd 13542 symtab_hdr = & elf_symtab_hdr (abfd);
252b5132 13543 sym_hashes = elf_sym_hashes (abfd);
ce98a316 13544 nsyms = NUM_SHDR_ENTRIES (symtab_hdr);
b38cadfb 13545
252b5132
RH		 13546 rel_end = relocs + sec->reloc_count;
13547 for (rel = relocs; rel < rel_end; rel++)
13548 {
34e77a92 13549 Elf_Internal_Sym *isym;
252b5132 13550 struct elf_link_hash_entry *h;
b7693d02 13551 struct elf32_arm_link_hash_entry *eh;
252b5132 13552 unsigned long r_symndx;
eb043451 13553 int r_type;
9a5aca8c 13554
252b5132 13555 r_symndx = ELF32_R_SYM (rel->r_info);
eb043451 13556 r_type = ELF32_R_TYPE (rel->r_info);
eb043451 13557 r_type = arm_real_reloc_type (htab, r_type);
ba93b8ac 13558
ce98a316
NC		 13559 if (r_symndx >= nsyms
13560 /* PR 9934: It is possible to have relocations that do not
13561 refer to symbols, thus it is also possible to have an
13562 object file containing relocations but no symbol table. */
cf35638d 13563 && (r_symndx > STN_UNDEF || nsyms > 0))
ba93b8ac
DJ		 13564 {
13565 (*_bfd_error_handler) (_("%B: bad symbol index: %d"), abfd,
ce98a316 13566 r_symndx);
ba93b8ac
DJ		 13567 return FALSE;
13568 }
13569
34e77a92
RS		 13570 h = NULL;
13571 isym = NULL;
13572 if (nsyms > 0)
973a3492 13573 {
34e77a92
RS		 13574 if (r_symndx < symtab_hdr->sh_info)
13575 {
13576 /* A local symbol. */
13577 isym = bfd_sym_from_r_symndx (&htab->sym_cache,
13578 abfd, r_symndx);
13579 if (isym == NULL)
13580 return FALSE;
13581 }
13582 else
13583 {
13584 h = sym_hashes[r_symndx - symtab_hdr->sh_info];
13585 while (h->root.type == bfd_link_hash_indirect
13586 || h->root.type == bfd_link_hash_warning)
13587 h = (struct elf_link_hash_entry *) h->root.u.i.link;
81fbe831
AM		 13588
13589 /* PR15323, ref flags aren't set for references in the
13590 same object. */
13591 h->root.non_ir_ref = 1;
34e77a92 13592 }
973a3492 13593 }
9a5aca8c 13594
b7693d02
DJ		 13595 eh = (struct elf32_arm_link_hash_entry *) h;
13596
f6e32f6d
RS		 13597 call_reloc_p = FALSE;
13598 may_become_dynamic_p = FALSE;
13599 may_need_local_target_p = FALSE;
13600
0855e32b
NS		 13601 /* Could be done earlier, if h were already available. */
13602 r_type = elf32_arm_tls_transition (info, r_type, h);
eb043451 13603 switch (r_type)
99059e56 13604 {
5e681ec4 13605 case R_ARM_GOT32:
eb043451 13606 case R_ARM_GOT_PREL:
ba93b8ac
DJ		 13607 case R_ARM_TLS_GD32:
13608 case R_ARM_TLS_IE32:
0855e32b
NS		 13609 case R_ARM_TLS_GOTDESC:
13610 case R_ARM_TLS_DESCSEQ:
13611 case R_ARM_THM_TLS_DESCSEQ:
13612 case R_ARM_TLS_CALL:
13613 case R_ARM_THM_TLS_CALL:
5e681ec4 13614 /* This symbol requires a global offset table entry. */
ba93b8ac
DJ		 13615 {
13616 int tls_type, old_tls_type;
5e681ec4 13617
ba93b8ac
DJ		 13618 switch (r_type)
13619 {
13620 case R_ARM_TLS_GD32: tls_type = GOT_TLS_GD; break;
b38cadfb 13621
ba93b8ac 13622 case R_ARM_TLS_IE32: tls_type = GOT_TLS_IE; break;
b38cadfb 13623
0855e32b
NS		 13624 case R_ARM_TLS_GOTDESC:
13625 case R_ARM_TLS_CALL: case R_ARM_THM_TLS_CALL:
13626 case R_ARM_TLS_DESCSEQ: case R_ARM_THM_TLS_DESCSEQ:
13627 tls_type = GOT_TLS_GDESC; break;
b38cadfb 13628
ba93b8ac
DJ		 13629 default: tls_type = GOT_NORMAL; break;
13630 }
252b5132 13631
0e1862bb 13632 if (!bfd_link_executable (info) && (tls_type & GOT_TLS_IE))
eea6dad2
KM		 13633 info->flags |= DF_STATIC_TLS;
13634
ba93b8ac
DJ		 13635 if (h != NULL)
13636 {
13637 h->got.refcount++;
13638 old_tls_type = elf32_arm_hash_entry (h)->tls_type;
13639 }
13640 else
13641 {
ba93b8ac 13642 /* This is a global offset table entry for a local symbol. */
34e77a92
RS		 13643 if (!elf32_arm_allocate_local_sym_info (abfd))
13644 return FALSE;
13645 elf_local_got_refcounts (abfd)[r_symndx] += 1;
ba93b8ac
DJ		 13646 old_tls_type = elf32_arm_local_got_tls_type (abfd) [r_symndx];
13647 }
13648
0855e32b 13649 /* If a variable is accessed with both tls methods, two
99059e56 13650 slots may be created. */
0855e32b
NS		 13651 if (GOT_TLS_GD_ANY_P (old_tls_type)
13652 && GOT_TLS_GD_ANY_P (tls_type))
13653 tls_type |= old_tls_type;
13654
13655 /* We will already have issued an error message if there
13656 is a TLS/non-TLS mismatch, based on the symbol
13657 type. So just combine any TLS types needed. */
ba93b8ac
DJ		 13658 if (old_tls_type != GOT_UNKNOWN && old_tls_type != GOT_NORMAL
13659 && tls_type != GOT_NORMAL)
13660 tls_type |= old_tls_type;
13661
0855e32b 13662 /* If the symbol is accessed in both IE and GDESC
99059e56
RM		 13663 method, we're able to relax. Turn off the GDESC flag,
13664 without messing up with any other kind of tls types
6a631e86 13665 that may be involved. */
0855e32b
NS		 13666 if ((tls_type & GOT_TLS_IE) && (tls_type & GOT_TLS_GDESC))
13667 tls_type &= ~GOT_TLS_GDESC;
13668
ba93b8ac
DJ		 13669 if (old_tls_type != tls_type)
13670 {
13671 if (h != NULL)
13672 elf32_arm_hash_entry (h)->tls_type = tls_type;
13673 else
13674 elf32_arm_local_got_tls_type (abfd) [r_symndx] = tls_type;
13675 }
13676 }
8029a119 13677 /* Fall through. */
ba93b8ac
DJ		 13678
13679 case R_ARM_TLS_LDM32:
13680 if (r_type == R_ARM_TLS_LDM32)
13681 htab->tls_ldm_got.refcount++;
8029a119 13682 /* Fall through. */
252b5132 13683
c19d1205 13684 case R_ARM_GOTOFF32:
5e681ec4 13685 case R_ARM_GOTPC:
cbc704f3
RS		 13686 if (htab->root.sgot == NULL
13687 && !create_got_section (htab->root.dynobj, info))
13688 return FALSE;
252b5132
RH		 13689 break;
13690
252b5132 13691 case R_ARM_PC24:
7359ea65 13692 case R_ARM_PLT32:
5b5bb741
PB		 13693 case R_ARM_CALL:
13694 case R_ARM_JUMP24:
eb043451 13695 case R_ARM_PREL31:
c19d1205 13696 case R_ARM_THM_CALL:
bd97cb95
DJ		 13697 case R_ARM_THM_JUMP24:
13698 case R_ARM_THM_JUMP19:
f6e32f6d
RS		 13699 call_reloc_p = TRUE;
13700 may_need_local_target_p = TRUE;
13701 break;
13702
13703 case R_ARM_ABS12:
13704 /* VxWorks uses dynamic R_ARM_ABS12 relocations for
13705 ldr __GOTT_INDEX__ offsets. */
13706 if (!htab->vxworks_p)
13707 {
13708 may_need_local_target_p = TRUE;
13709 break;
13710 }
aebf9be7
NC		 13711 else goto jump_over;
13712
f6e32f6d 13713 /* Fall through. */
39623e12 13714
96c23d59
JM		 13715 case R_ARM_MOVW_ABS_NC:
13716 case R_ARM_MOVT_ABS:
13717 case R_ARM_THM_MOVW_ABS_NC:
13718 case R_ARM_THM_MOVT_ABS:
0e1862bb 13719 if (bfd_link_pic (info))
96c23d59
JM		 13720 {
13721 (*_bfd_error_handler)
13722 (_("%B: relocation %s against `%s' can not be used when making a shared object; recompile with -fPIC"),
13723 abfd, elf32_arm_howto_table_1[r_type].name,
13724 (h) ? h->root.root.string : "a local symbol");
13725 bfd_set_error (bfd_error_bad_value);
13726 return FALSE;
13727 }
13728
13729 /* Fall through. */
39623e12
PB		 13730 case R_ARM_ABS32:
13731 case R_ARM_ABS32_NOI:
aebf9be7 13732 jump_over:
0e1862bb 13733 if (h != NULL && bfd_link_executable (info))
97323ad1
WN		 13734 {
13735 h->pointer_equality_needed = 1;
13736 }
13737 /* Fall through. */
39623e12
PB		 13738 case R_ARM_REL32:
13739 case R_ARM_REL32_NOI:
b6895b4f
PB		 13740 case R_ARM_MOVW_PREL_NC:
13741 case R_ARM_MOVT_PREL:
b6895b4f
PB		 13742 case R_ARM_THM_MOVW_PREL_NC:
13743 case R_ARM_THM_MOVT_PREL:
39623e12 13744
b7693d02 13745 /* Should the interworking branches be listed here? */
0e1862bb 13746 if ((bfd_link_pic (info) || htab->root.is_relocatable_executable)
34e77a92
RS		 13747 && (sec->flags & SEC_ALLOC) != 0)
13748 {
13749 if (h == NULL
469a3493 13750 && elf32_arm_howto_from_type (r_type)->pc_relative)
34e77a92
RS		 13751 {
13752 /* In shared libraries and relocatable executables,
13753 we treat local relative references as calls;
13754 see the related SYMBOL_CALLS_LOCAL code in
13755 allocate_dynrelocs. */
13756 call_reloc_p = TRUE;
13757 may_need_local_target_p = TRUE;
13758 }
13759 else
13760 /* We are creating a shared library or relocatable
13761 executable, and this is a reloc against a global symbol,
13762 or a non-PC-relative reloc against a local symbol.
13763 We may need to copy the reloc into the output. */
13764 may_become_dynamic_p = TRUE;
13765 }
f6e32f6d
RS		 13766 else
13767 may_need_local_target_p = TRUE;
252b5132
RH		 13768 break;
13769
99059e56
RM		 13770 /* This relocation describes the C++ object vtable hierarchy.
13771 Reconstruct it for later use during GC. */
13772 case R_ARM_GNU_VTINHERIT:
13773 if (!bfd_elf_gc_record_vtinherit (abfd, sec, h, rel->r_offset))
13774 return FALSE;
13775 break;
13776
13777 /* This relocation describes which C++ vtable entries are actually
13778 used. Record for later use during GC. */
13779 case R_ARM_GNU_VTENTRY:
13780 BFD_ASSERT (h != NULL);
13781 if (h != NULL
13782 && !bfd_elf_gc_record_vtentry (abfd, sec, h, rel->r_offset))
13783 return FALSE;
13784 break;
13785 }
f6e32f6d
RS		 13786
13787 if (h != NULL)
13788 {
13789 if (call_reloc_p)
13790 /* We may need a .plt entry if the function this reloc
13791 refers to is in a different object, regardless of the
13792 symbol's type. We can't tell for sure yet, because
13793 something later might force the symbol local. */
13794 h->needs_plt = 1;
13795 else if (may_need_local_target_p)
13796 /* If this reloc is in a read-only section, we might
13797 need a copy reloc. We can't check reliably at this
13798 stage whether the section is read-only, as input
13799 sections have not yet been mapped to output sections.
13800 Tentatively set the flag for now, and correct in
13801 adjust_dynamic_symbol. */
13802 h->non_got_ref = 1;
13803 }
13804
34e77a92
RS		 13805 if (may_need_local_target_p
13806 && (h != NULL || ELF32_ST_TYPE (isym->st_info) == STT_GNU_IFUNC))
f6e32f6d 13807 {
34e77a92
RS		 13808 union gotplt_union *root_plt;
13809 struct arm_plt_info *arm_plt;
13810 struct arm_local_iplt_info *local_iplt;
13811
13812 if (h != NULL)
13813 {
13814 root_plt = &h->plt;
13815 arm_plt = &eh->plt;
13816 }
13817 else
13818 {
13819 local_iplt = elf32_arm_create_local_iplt (abfd, r_symndx);
13820 if (local_iplt == NULL)
13821 return FALSE;
13822 root_plt = &local_iplt->root;
13823 arm_plt = &local_iplt->arm;
13824 }
13825
f6e32f6d
RS		 13826 /* If the symbol is a function that doesn't bind locally,
13827 this relocation will need a PLT entry. */
a8c887dd
NC		 13828 if (root_plt->refcount != -1)
13829 root_plt->refcount += 1;
34e77a92
RS		 13830
13831 if (!call_reloc_p)
13832 arm_plt->noncall_refcount++;
f6e32f6d
RS		 13833
13834 /* It's too early to use htab->use_blx here, so we have to
13835 record possible blx references separately from
13836 relocs that definitely need a thumb stub. */
13837
13838 if (r_type == R_ARM_THM_CALL)
34e77a92 13839 arm_plt->maybe_thumb_refcount += 1;
f6e32f6d
RS		 13840
13841 if (r_type == R_ARM_THM_JUMP24
13842 || r_type == R_ARM_THM_JUMP19)
34e77a92 13843 arm_plt->thumb_refcount += 1;
f6e32f6d
RS		 13844 }
13845
13846 if (may_become_dynamic_p)
13847 {
13848 struct elf_dyn_relocs *p, **head;
13849
13850 /* Create a reloc section in dynobj. */
13851 if (sreloc == NULL)
13852 {
13853 sreloc = _bfd_elf_make_dynamic_reloc_section
13854 (sec, dynobj, 2, abfd, ! htab->use_rel);
13855
13856 if (sreloc == NULL)
13857 return FALSE;
13858
13859 /* BPABI objects never have dynamic relocations mapped. */
13860 if (htab->symbian_p)
13861 {
13862 flagword flags;
13863
13864 flags = bfd_get_section_flags (dynobj, sreloc);
13865 flags &= ~(SEC_LOAD | SEC_ALLOC);
13866 bfd_set_section_flags (dynobj, sreloc, flags);
13867 }
13868 }
13869
13870 /* If this is a global symbol, count the number of
13871 relocations we need for this symbol. */
13872 if (h != NULL)
13873 head = &((struct elf32_arm_link_hash_entry *) h)->dyn_relocs;
13874 else
13875 {
34e77a92
RS		 13876 head = elf32_arm_get_local_dynreloc_list (abfd, r_symndx, isym);
13877 if (head == NULL)
f6e32f6d 13878 return FALSE;
f6e32f6d
RS		 13879 }
13880
13881 p = *head;
13882 if (p == NULL || p->sec != sec)
13883 {
13884 bfd_size_type amt = sizeof *p;
13885
13886 p = (struct elf_dyn_relocs *) bfd_alloc (htab->root.dynobj, amt);
13887 if (p == NULL)
13888 return FALSE;
13889 p->next = *head;
13890 *head = p;
13891 p->sec = sec;
13892 p->count = 0;
13893 p->pc_count = 0;
13894 }
13895
469a3493 13896 if (elf32_arm_howto_from_type (r_type)->pc_relative)
f6e32f6d
RS		 13897 p->pc_count += 1;
13898 p->count += 1;
13899 }
252b5132 13900 }
f21f3fe0 13901
b34976b6 13902 return TRUE;
252b5132
RH		 13903}
13904
6a5bb875
PB		 13905/* Unwinding tables are not referenced directly. This pass marks them as
13906 required if the corresponding code section is marked. */
13907
13908static bfd_boolean
906e58ca
NC		 13909elf32_arm_gc_mark_extra_sections (struct bfd_link_info *info,
13910 elf_gc_mark_hook_fn gc_mark_hook)
6a5bb875
PB		 13911{
13912 bfd *sub;
13913 Elf_Internal_Shdr **elf_shdrp;
13914 bfd_boolean again;
13915
7f6ab9f8
AM		 13916 _bfd_elf_gc_mark_extra_sections (info, gc_mark_hook);
13917
6a5bb875
PB		 13918 /* Marking EH data may cause additional code sections to be marked,
13919 requiring multiple passes. */
13920 again = TRUE;
13921 while (again)
13922 {
13923 again = FALSE;
c72f2fb2 13924 for (sub = info->input_bfds; sub != NULL; sub = sub->link.next)
6a5bb875
PB		 13925 {
13926 asection *o;
13927
0ffa91dd 13928 if (! is_arm_elf (sub))
6a5bb875
PB		 13929 continue;
13930
13931 elf_shdrp = elf_elfsections (sub);
13932 for (o = sub->sections; o != NULL; o = o->next)
13933 {
13934 Elf_Internal_Shdr *hdr;
0ffa91dd 13935
6a5bb875 13936 hdr = &elf_section_data (o)->this_hdr;
4fbb74a6
AM		 13937 if (hdr->sh_type == SHT_ARM_EXIDX
13938 && hdr->sh_link
13939 && hdr->sh_link < elf_numsections (sub)
6a5bb875
PB		 13940 && !o->gc_mark
13941 && elf_shdrp[hdr->sh_link]->bfd_section->gc_mark)
13942 {
13943 again = TRUE;
13944 if (!_bfd_elf_gc_mark (info, o, gc_mark_hook))
13945 return FALSE;
13946 }
13947 }
13948 }
13949 }
13950
13951 return TRUE;
13952}
13953
3c9458e9
NC		 13954/* Treat mapping symbols as special target symbols. */
13955
13956static bfd_boolean
13957elf32_arm_is_target_special_symbol (bfd * abfd ATTRIBUTE_UNUSED, asymbol * sym)
13958{
b0796911
PB		 13959 return bfd_is_arm_special_symbol_name (sym->name,
13960 BFD_ARM_SPECIAL_SYM_TYPE_ANY);
3c9458e9
NC		 13961}
13962
0367ecfb
NC		 13963/* This is a copy of elf_find_function() from elf.c except that
13964 ARM mapping symbols are ignored when looking for function names
13965 and STT_ARM_TFUNC is considered to a function type. */
252b5132 13966
0367ecfb
NC		 13967static bfd_boolean
13968arm_elf_find_function (bfd * abfd ATTRIBUTE_UNUSED,
0367ecfb 13969 asymbol ** symbols,
fb167eb2 13970 asection * section,
0367ecfb
NC		 13971 bfd_vma offset,
13972 const char ** filename_ptr,
13973 const char ** functionname_ptr)
13974{
13975 const char * filename = NULL;
13976 asymbol * func = NULL;
13977 bfd_vma low_func = 0;
13978 asymbol ** p;
252b5132
RH		 13979
13980 for (p = symbols; *p != NULL; p++)
13981 {
13982 elf_symbol_type *q;
13983
13984 q = (elf_symbol_type *) *p;
13985
252b5132
RH		 13986 switch (ELF_ST_TYPE (q->internal_elf_sym.st_info))
13987 {
13988 default:
13989 break;
13990 case STT_FILE:
13991 filename = bfd_asymbol_name (&q->symbol);
13992 break;
252b5132
RH		 13993 case STT_FUNC:
13994 case STT_ARM_TFUNC:
9d2da7ca 13995 case STT_NOTYPE:
b0796911 13996 /* Skip mapping symbols. */
0367ecfb 13997 if ((q->symbol.flags & BSF_LOCAL)
b0796911
PB		 13998 && bfd_is_arm_special_symbol_name (q->symbol.name,
13999 BFD_ARM_SPECIAL_SYM_TYPE_ANY))
0367ecfb
NC		 14000 continue;
14001 /* Fall through. */
6b40fcba 14002 if (bfd_get_section (&q->symbol) == section
252b5132
RH		 14003 && q->symbol.value >= low_func
14004 && q->symbol.value <= offset)
14005 {
14006 func = (asymbol *) q;
14007 low_func = q->symbol.value;
14008 }
14009 break;
14010 }
14011 }
14012
14013 if (func == NULL)
b34976b6 14014 return FALSE;
252b5132 14015
0367ecfb
NC		 14016 if (filename_ptr)
14017 *filename_ptr = filename;
14018 if (functionname_ptr)
14019 *functionname_ptr = bfd_asymbol_name (func);
14020
14021 return TRUE;
906e58ca 14022}
0367ecfb
NC		 14023
14024
14025/* Find the nearest line to a particular section and offset, for error
14026 reporting. This code is a duplicate of the code in elf.c, except
14027 that it uses arm_elf_find_function. */
14028
14029static bfd_boolean
14030elf32_arm_find_nearest_line (bfd * abfd,
0367ecfb 14031 asymbol ** symbols,
fb167eb2 14032 asection * section,
0367ecfb
NC		 14033 bfd_vma offset,
14034 const char ** filename_ptr,
14035 const char ** functionname_ptr,
fb167eb2
AM		 14036 unsigned int * line_ptr,
14037 unsigned int * discriminator_ptr)
0367ecfb
NC		 14038{
14039 bfd_boolean found = FALSE;
14040
fb167eb2 14041 if (_bfd_dwarf2_find_nearest_line (abfd, symbols, NULL, section, offset,
0367ecfb 14042 filename_ptr, functionname_ptr,
fb167eb2
AM		 14043 line_ptr, discriminator_ptr,
14044 dwarf_debug_sections, 0,
0367ecfb
NC		 14045 & elf_tdata (abfd)->dwarf2_find_line_info))
14046 {
14047 if (!*functionname_ptr)
fb167eb2 14048 arm_elf_find_function (abfd, symbols, section, offset,
0367ecfb
NC		 14049 *filename_ptr ? NULL : filename_ptr,
14050 functionname_ptr);
f21f3fe0 14051
0367ecfb
NC		 14052 return TRUE;
14053 }
14054
fb167eb2
AM		 14055 /* Skip _bfd_dwarf1_find_nearest_line since no known ARM toolchain
14056 uses DWARF1. */
14057
0367ecfb
NC		 14058 if (! _bfd_stab_section_find_nearest_line (abfd, symbols, section, offset,
14059 & found, filename_ptr,
14060 functionname_ptr, line_ptr,
14061 & elf_tdata (abfd)->line_info))
14062 return FALSE;
14063
14064 if (found && (*functionname_ptr || *line_ptr))
14065 return TRUE;
14066
14067 if (symbols == NULL)
14068 return FALSE;
14069
fb167eb2 14070 if (! arm_elf_find_function (abfd, symbols, section, offset,
0367ecfb
NC		 14071 filename_ptr, functionname_ptr))
14072 return FALSE;
14073
14074 *line_ptr = 0;
b34976b6 14075 return TRUE;
252b5132
RH		 14076}
14077
4ab527b0
FF		 14078static bfd_boolean
14079elf32_arm_find_inliner_info (bfd * abfd,
14080 const char ** filename_ptr,
14081 const char ** functionname_ptr,
14082 unsigned int * line_ptr)
14083{
14084 bfd_boolean found;
14085 found = _bfd_dwarf2_find_inliner_info (abfd, filename_ptr,
14086 functionname_ptr, line_ptr,
14087 & elf_tdata (abfd)->dwarf2_find_line_info);
14088 return found;
14089}
14090
252b5132
RH		 14091/* Adjust a symbol defined by a dynamic object and referenced by a
14092 regular object. The current definition is in some section of the
14093 dynamic object, but we're not including those sections. We have to
14094 change the definition to something the rest of the link can
14095 understand. */
14096
b34976b6 14097static bfd_boolean
57e8b36a
NC		 14098elf32_arm_adjust_dynamic_symbol (struct bfd_link_info * info,
14099 struct elf_link_hash_entry * h)
252b5132
RH		 14100{
14101 bfd * dynobj;
14102 asection * s;
b7693d02 14103 struct elf32_arm_link_hash_entry * eh;
67687978 14104 struct elf32_arm_link_hash_table *globals;
252b5132 14105
67687978 14106 globals = elf32_arm_hash_table (info);
4dfe6ac6
NC		 14107 if (globals == NULL)
14108 return FALSE;
14109
252b5132
RH		 14110 dynobj = elf_hash_table (info)->dynobj;
14111
14112 /* Make sure we know what is going on here. */
14113 BFD_ASSERT (dynobj != NULL
f5385ebf 14114 && (h->needs_plt
34e77a92 14115 || h->type == STT_GNU_IFUNC
f6e332e6 14116 || h->u.weakdef != NULL
f5385ebf
AM		 14117 || (h->def_dynamic
14118 && h->ref_regular
14119 && !h->def_regular)));
252b5132 14120
b7693d02
DJ		 14121 eh = (struct elf32_arm_link_hash_entry *) h;
14122
252b5132
RH		 14123 /* If this is a function, put it in the procedure linkage table. We
14124 will fill in the contents of the procedure linkage table later,
14125 when we know the address of the .got section. */
34e77a92 14126 if (h->type == STT_FUNC || h->type == STT_GNU_IFUNC || h->needs_plt)
252b5132 14127 {
34e77a92
RS		 14128 /* Calls to STT_GNU_IFUNC symbols always use a PLT, even if the
14129 symbol binds locally. */
5e681ec4 14130 if (h->plt.refcount <= 0
34e77a92
RS		 14131 || (h->type != STT_GNU_IFUNC
14132 && (SYMBOL_CALLS_LOCAL (info, h)
14133 || (ELF_ST_VISIBILITY (h->other) != STV_DEFAULT
14134 && h->root.type == bfd_link_hash_undefweak))))
252b5132
RH		 14135 {
14136 /* This case can occur if we saw a PLT32 reloc in an input
5e681ec4
PB		 14137 file, but the symbol was never referred to by a dynamic
14138 object, or if all references were garbage collected. In
14139 such a case, we don't actually need to build a procedure
14140 linkage table, and we can just do a PC24 reloc instead. */
14141 h->plt.offset = (bfd_vma) -1;
34e77a92
RS		 14142 eh->plt.thumb_refcount = 0;
14143 eh->plt.maybe_thumb_refcount = 0;
14144 eh->plt.noncall_refcount = 0;
f5385ebf 14145 h->needs_plt = 0;
252b5132
RH		 14146 }
14147
b34976b6 14148 return TRUE;
252b5132 14149 }
5e681ec4 14150 else
b7693d02
DJ		 14151 {
14152 /* It's possible that we incorrectly decided a .plt reloc was
14153 needed for an R_ARM_PC24 or similar reloc to a non-function sym
14154 in check_relocs. We can't decide accurately between function
14155 and non-function syms in check-relocs; Objects loaded later in
14156 the link may change h->type. So fix it now. */
14157 h->plt.offset = (bfd_vma) -1;
34e77a92
RS		 14158 eh->plt.thumb_refcount = 0;
14159 eh->plt.maybe_thumb_refcount = 0;
14160 eh->plt.noncall_refcount = 0;
b7693d02 14161 }
252b5132
RH		 14162
14163 /* If this is a weak symbol, and there is a real definition, the
14164 processor independent code will have arranged for us to see the
14165 real definition first, and we can just use the same value. */
f6e332e6 14166 if (h->u.weakdef != NULL)
252b5132 14167 {
f6e332e6
AM		 14168 BFD_ASSERT (h->u.weakdef->root.type == bfd_link_hash_defined
14169 || h->u.weakdef->root.type == bfd_link_hash_defweak);
14170 h->root.u.def.section = h->u.weakdef->root.u.def.section;
14171 h->root.u.def.value = h->u.weakdef->root.u.def.value;
b34976b6 14172 return TRUE;
252b5132
RH		 14173 }
14174
ba93b8ac
DJ		 14175 /* If there are no non-GOT references, we do not need a copy
14176 relocation. */
14177 if (!h->non_got_ref)
14178 return TRUE;
14179
252b5132
RH		 14180 /* This is a reference to a symbol defined by a dynamic object which
14181 is not a function. */
14182
14183 /* If we are creating a shared library, we must presume that the
14184 only references to the symbol are via the global offset table.
14185 For such cases we need not do anything here; the relocations will
67687978
PB		 14186 be handled correctly by relocate_section. Relocatable executables
14187 can reference data in shared objects directly, so we don't need to
14188 do anything here. */
0e1862bb 14189 if (bfd_link_pic (info) || globals->root.is_relocatable_executable)
b34976b6 14190 return TRUE;
252b5132
RH		 14191
14192 /* We must allocate the symbol in our .dynbss section, which will
14193 become part of the .bss section of the executable. There will be
14194 an entry for this symbol in the .dynsym section. The dynamic
14195 object will contain position independent code, so all references
14196 from the dynamic object to this symbol will go through the global
14197 offset table. The dynamic linker will use the .dynsym entry to
14198 determine the address it must put in the global offset table, so
14199 both the dynamic object and the regular object will refer to the
14200 same memory location for the variable. */
3d4d4302 14201 s = bfd_get_linker_section (dynobj, ".dynbss");
252b5132
RH		 14202 BFD_ASSERT (s != NULL);
14203
5522f910
NC		 14204 /* If allowed, we must generate a R_ARM_COPY reloc to tell the dynamic
14205 linker to copy the initial value out of the dynamic object and into
14206 the runtime process image. We need to remember the offset into the
00a97672 14207 .rel(a).bss section we are going to use. */
5522f910
NC		 14208 if (info->nocopyreloc == 0
14209 && (h->root.u.def.section->flags & SEC_ALLOC) != 0
5522f910 14210 && h->size != 0)
252b5132
RH		 14211 {
14212 asection *srel;
14213
3d4d4302 14214 srel = bfd_get_linker_section (dynobj, RELOC_SECTION (globals, ".bss"));
47beaa6a 14215 elf32_arm_allocate_dynrelocs (info, srel, 1);
f5385ebf 14216 h->needs_copy = 1;
252b5132
RH		 14217 }
14218
6cabe1ea 14219 return _bfd_elf_adjust_dynamic_copy (info, h, s);
252b5132
RH		 14220}
14221
5e681ec4
PB		 14222/* Allocate space in .plt, .got and associated reloc sections for
14223 dynamic relocs. */
14224
14225static bfd_boolean
47beaa6a 14226allocate_dynrelocs_for_symbol (struct elf_link_hash_entry *h, void * inf)
5e681ec4
PB		 14227{
14228 struct bfd_link_info *info;
14229 struct elf32_arm_link_hash_table *htab;
14230 struct elf32_arm_link_hash_entry *eh;
0bdcacaf 14231 struct elf_dyn_relocs *p;
5e681ec4
PB		 14232
14233 if (h->root.type == bfd_link_hash_indirect)
14234 return TRUE;
14235
e6a6bb22
AM		 14236 eh = (struct elf32_arm_link_hash_entry *) h;
14237
5e681ec4
PB		 14238 info = (struct bfd_link_info *) inf;
14239 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 14240 if (htab == NULL)
14241 return FALSE;
5e681ec4 14242
34e77a92 14243 if ((htab->root.dynamic_sections_created || h->type == STT_GNU_IFUNC)
5e681ec4
PB		 14244 && h->plt.refcount > 0)
14245 {
14246 /* Make sure this symbol is output as a dynamic symbol.
14247 Undefined weak syms won't yet be marked as dynamic. */
14248 if (h->dynindx == -1
f5385ebf 14249 && !h->forced_local)
5e681ec4 14250 {
c152c796 14251 if (! bfd_elf_link_record_dynamic_symbol (info, h))
5e681ec4
PB		 14252 return FALSE;
14253 }
14254
34e77a92
RS		 14255 /* If the call in the PLT entry binds locally, the associated
14256 GOT entry should use an R_ARM_IRELATIVE relocation instead of
14257 the usual R_ARM_JUMP_SLOT. Put it in the .iplt section rather
14258 than the .plt section. */
14259 if (h->type == STT_GNU_IFUNC && SYMBOL_CALLS_LOCAL (info, h))
14260 {
14261 eh->is_iplt = 1;
14262 if (eh->plt.noncall_refcount == 0
14263 && SYMBOL_REFERENCES_LOCAL (info, h))
14264 /* All non-call references can be resolved directly.
14265 This means that they can (and in some cases, must)
14266 resolve directly to the run-time target, rather than
14267 to the PLT. That in turns means that any .got entry
14268 would be equal to the .igot.plt entry, so there's
14269 no point having both. */
14270 h->got.refcount = 0;
14271 }
14272
0e1862bb 14273 if (bfd_link_pic (info)
34e77a92 14274 || eh->is_iplt
7359ea65 14275 || WILL_CALL_FINISH_DYNAMIC_SYMBOL (1, 0, h))
5e681ec4 14276 {
34e77a92 14277 elf32_arm_allocate_plt_entry (info, eh->is_iplt, &h->plt, &eh->plt);
b7693d02 14278
5e681ec4
PB		 14279 /* If this symbol is not defined in a regular file, and we are
14280 not generating a shared library, then set the symbol to this
14281 location in the .plt. This is required to make function
14282 pointers compare as equal between the normal executable and
14283 the shared library. */
0e1862bb 14284 if (! bfd_link_pic (info)
f5385ebf 14285 && !h->def_regular)
5e681ec4 14286 {
34e77a92 14287 h->root.u.def.section = htab->root.splt;
5e681ec4 14288 h->root.u.def.value = h->plt.offset;
5e681ec4 14289
67d74e43
DJ		 14290 /* Make sure the function is not marked as Thumb, in case
14291 it is the target of an ABS32 relocation, which will
14292 point to the PLT entry. */
39d911fc 14293 ARM_SET_SYM_BRANCH_TYPE (h->target_internal, ST_BRANCH_TO_ARM);
67d74e43 14294 }
022f8312 14295
00a97672
RS		 14296 /* VxWorks executables have a second set of relocations for
14297 each PLT entry. They go in a separate relocation section,
14298 which is processed by the kernel loader. */
0e1862bb 14299 if (htab->vxworks_p && !bfd_link_pic (info))
00a97672
RS		 14300 {
14301 /* There is a relocation for the initial PLT entry:
14302 an R_ARM_32 relocation for _GLOBAL_OFFSET_TABLE_. */
14303 if (h->plt.offset == htab->plt_header_size)
47beaa6a 14304 elf32_arm_allocate_dynrelocs (info, htab->srelplt2, 1);
00a97672
RS		 14305
14306 /* There are two extra relocations for each subsequent
14307 PLT entry: an R_ARM_32 relocation for the GOT entry,
14308 and an R_ARM_32 relocation for the PLT entry. */
47beaa6a 14309 elf32_arm_allocate_dynrelocs (info, htab->srelplt2, 2);
00a97672 14310 }
5e681ec4
PB		 14311 }
14312 else
14313 {
14314 h->plt.offset = (bfd_vma) -1;
f5385ebf 14315 h->needs_plt = 0;
5e681ec4
PB		 14316 }
14317 }
14318 else
14319 {
14320 h->plt.offset = (bfd_vma) -1;
f5385ebf 14321 h->needs_plt = 0;
5e681ec4
PB		 14322 }
14323
0855e32b
NS		 14324 eh = (struct elf32_arm_link_hash_entry *) h;
14325 eh->tlsdesc_got = (bfd_vma) -1;
14326
5e681ec4
PB		 14327 if (h->got.refcount > 0)
14328 {
14329 asection *s;
14330 bfd_boolean dyn;
ba93b8ac
DJ		 14331 int tls_type = elf32_arm_hash_entry (h)->tls_type;
14332 int indx;
5e681ec4
PB		 14333
14334 /* Make sure this symbol is output as a dynamic symbol.
14335 Undefined weak syms won't yet be marked as dynamic. */
14336 if (h->dynindx == -1
f5385ebf 14337 && !h->forced_local)
5e681ec4 14338 {
c152c796 14339 if (! bfd_elf_link_record_dynamic_symbol (info, h))
5e681ec4
PB		 14340 return FALSE;
14341 }
14342
e5a52504
MM		 14343 if (!htab->symbian_p)
14344 {
362d30a1 14345 s = htab->root.sgot;
e5a52504 14346 h->got.offset = s->size;
ba93b8ac
DJ		 14347
14348 if (tls_type == GOT_UNKNOWN)
14349 abort ();
14350
14351 if (tls_type == GOT_NORMAL)
14352 /* Non-TLS symbols need one GOT slot. */
14353 s->size += 4;
14354 else
14355 {
99059e56
RM		 14356 if (tls_type & GOT_TLS_GDESC)
14357 {
0855e32b 14358 /* R_ARM_TLS_DESC needs 2 GOT slots. */
99059e56 14359 eh->tlsdesc_got
0855e32b
NS		 14360 = (htab->root.sgotplt->size
14361 - elf32_arm_compute_jump_table_size (htab));
99059e56
RM		 14362 htab->root.sgotplt->size += 8;
14363 h->got.offset = (bfd_vma) -2;
34e77a92 14364 /* plt.got_offset needs to know there's a TLS_DESC
0855e32b 14365 reloc in the middle of .got.plt. */
99059e56
RM		 14366 htab->num_tls_desc++;
14367 }
0855e32b 14368
ba93b8ac 14369 if (tls_type & GOT_TLS_GD)
0855e32b
NS		 14370 {
14371 /* R_ARM_TLS_GD32 needs 2 consecutive GOT slots. If
14372 the symbol is both GD and GDESC, got.offset may
14373 have been overwritten. */
14374 h->got.offset = s->size;
14375 s->size += 8;
14376 }
14377
ba93b8ac
DJ		 14378 if (tls_type & GOT_TLS_IE)
14379 /* R_ARM_TLS_IE32 needs one GOT slot. */
14380 s->size += 4;
14381 }
14382
e5a52504 14383 dyn = htab->root.dynamic_sections_created;
ba93b8ac
DJ		 14384
14385 indx = 0;
0e1862bb
L		 14386 if (WILL_CALL_FINISH_DYNAMIC_SYMBOL (dyn,
14387 bfd_link_pic (info),
14388 h)
14389 && (!bfd_link_pic (info)
ba93b8ac
DJ		 14390 || !SYMBOL_REFERENCES_LOCAL (info, h)))
14391 indx = h->dynindx;
14392
14393 if (tls_type != GOT_NORMAL
0e1862bb 14394 && (bfd_link_pic (info) || indx != 0)
ba93b8ac
DJ		 14395 && (ELF_ST_VISIBILITY (h->other) == STV_DEFAULT
14396 || h->root.type != bfd_link_hash_undefweak))
14397 {
14398 if (tls_type & GOT_TLS_IE)
47beaa6a 14399 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
ba93b8ac
DJ		 14400
14401 if (tls_type & GOT_TLS_GD)
47beaa6a 14402 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
ba93b8ac 14403
b38cadfb 14404 if (tls_type & GOT_TLS_GDESC)
0855e32b 14405 {
47beaa6a 14406 elf32_arm_allocate_dynrelocs (info, htab->root.srelplt, 1);
0855e32b
NS		 14407 /* GDESC needs a trampoline to jump to. */
14408 htab->tls_trampoline = -1;
14409 }
14410
14411 /* Only GD needs it. GDESC just emits one relocation per
14412 2 entries. */
b38cadfb 14413 if ((tls_type & GOT_TLS_GD) && indx != 0)
47beaa6a 14414 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
ba93b8ac 14415 }
6f820c85 14416 else if (indx != -1 && !SYMBOL_REFERENCES_LOCAL (info, h))
b436d854
RS		 14417 {
14418 if (htab->root.dynamic_sections_created)
14419 /* Reserve room for the GOT entry's R_ARM_GLOB_DAT relocation. */
14420 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
14421 }
34e77a92
RS		 14422 else if (h->type == STT_GNU_IFUNC
14423 && eh->plt.noncall_refcount == 0)
14424 /* No non-call references resolve the STT_GNU_IFUNC's PLT entry;
14425 they all resolve dynamically instead. Reserve room for the
14426 GOT entry's R_ARM_IRELATIVE relocation. */
14427 elf32_arm_allocate_irelocs (info, htab->root.srelgot, 1);
0e1862bb
L		 14428 else if (bfd_link_pic (info)
14429 && (ELF_ST_VISIBILITY (h->other) == STV_DEFAULT
14430 || h->root.type != bfd_link_hash_undefweak))
b436d854 14431 /* Reserve room for the GOT entry's R_ARM_RELATIVE relocation. */
47beaa6a 14432 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
e5a52504 14433 }
5e681ec4
PB		 14434 }
14435 else
14436 h->got.offset = (bfd_vma) -1;
14437
a4fd1a8e
PB		 14438 /* Allocate stubs for exported Thumb functions on v4t. */
14439 if (!htab->use_blx && h->dynindx != -1
0eaedd0e 14440 && h->def_regular
39d911fc 14441 && ARM_GET_SYM_BRANCH_TYPE (h->target_internal) == ST_BRANCH_TO_THUMB
a4fd1a8e
PB		 14442 && ELF_ST_VISIBILITY (h->other) == STV_DEFAULT)
14443 {
14444 struct elf_link_hash_entry * th;
14445 struct bfd_link_hash_entry * bh;
14446 struct elf_link_hash_entry * myh;
14447 char name[1024];
14448 asection *s;
14449 bh = NULL;
14450 /* Create a new symbol to regist the real location of the function. */
14451 s = h->root.u.def.section;
906e58ca 14452 sprintf (name, "__real_%s", h->root.root.string);
a4fd1a8e
PB		 14453 _bfd_generic_link_add_one_symbol (info, s->owner,
14454 name, BSF_GLOBAL, s,
14455 h->root.u.def.value,
14456 NULL, TRUE, FALSE, &bh);
14457
14458 myh = (struct elf_link_hash_entry *) bh;
35fc36a8 14459 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
a4fd1a8e 14460 myh->forced_local = 1;
39d911fc 14461 ARM_SET_SYM_BRANCH_TYPE (myh->target_internal, ST_BRANCH_TO_THUMB);
a4fd1a8e
PB		 14462 eh->export_glue = myh;
14463 th = record_arm_to_thumb_glue (info, h);
14464 /* Point the symbol at the stub. */
14465 h->type = ELF_ST_INFO (ELF_ST_BIND (h->type), STT_FUNC);
39d911fc 14466 ARM_SET_SYM_BRANCH_TYPE (h->target_internal, ST_BRANCH_TO_ARM);
a4fd1a8e
PB		 14467 h->root.u.def.section = th->root.u.def.section;
14468 h->root.u.def.value = th->root.u.def.value & ~1;
14469 }
14470
0bdcacaf 14471 if (eh->dyn_relocs == NULL)
5e681ec4
PB		 14472 return TRUE;
14473
14474 /* In the shared -Bsymbolic case, discard space allocated for
14475 dynamic pc-relative relocs against symbols which turn out to be
14476 defined in regular objects. For the normal shared case, discard
14477 space for pc-relative relocs that have become local due to symbol
14478 visibility changes. */
14479
0e1862bb 14480 if (bfd_link_pic (info) || htab->root.is_relocatable_executable)
5e681ec4 14481 {
469a3493
RM		 14482 /* Relocs that use pc_count are PC-relative forms, which will appear
14483 on something like ".long foo - ." or "movw REG, foo - .". We want
14484 calls to protected symbols to resolve directly to the function
14485 rather than going via the plt. If people want function pointer
14486 comparisons to work as expected then they should avoid writing
14487 assembly like ".long foo - .". */
ba93b8ac
DJ		 14488 if (SYMBOL_CALLS_LOCAL (info, h))
14489 {
0bdcacaf 14490 struct elf_dyn_relocs **pp;
ba93b8ac 14491
0bdcacaf 14492 for (pp = &eh->dyn_relocs; (p = *pp) != NULL; )
ba93b8ac
DJ		 14493 {
14494 p->count -= p->pc_count;
14495 p->pc_count = 0;
14496 if (p->count == 0)
14497 *pp = p->next;
14498 else
14499 pp = &p->next;
14500 }
14501 }
14502
4dfe6ac6 14503 if (htab->vxworks_p)
3348747a 14504 {
0bdcacaf 14505 struct elf_dyn_relocs **pp;
3348747a 14506
0bdcacaf 14507 for (pp = &eh->dyn_relocs; (p = *pp) != NULL; )
3348747a 14508 {
0bdcacaf 14509 if (strcmp (p->sec->output_section->name, ".tls_vars") == 0)
3348747a
NS		 14510 *pp = p->next;
14511 else
14512 pp = &p->next;
14513 }
14514 }
14515
ba93b8ac 14516 /* Also discard relocs on undefined weak syms with non-default
99059e56 14517 visibility. */
0bdcacaf 14518 if (eh->dyn_relocs != NULL
5e681ec4 14519 && h->root.type == bfd_link_hash_undefweak)
22d606e9
AM		 14520 {
14521 if (ELF_ST_VISIBILITY (h->other) != STV_DEFAULT)
0bdcacaf 14522 eh->dyn_relocs = NULL;
22d606e9
AM		 14523
14524 /* Make sure undefined weak symbols are output as a dynamic
14525 symbol in PIEs. */
14526 else if (h->dynindx == -1
14527 && !h->forced_local)
14528 {
14529 if (! bfd_elf_link_record_dynamic_symbol (info, h))
14530 return FALSE;
14531 }
14532 }
14533
67687978
PB		 14534 else if (htab->root.is_relocatable_executable && h->dynindx == -1
14535 && h->root.type == bfd_link_hash_new)
14536 {
14537 /* Output absolute symbols so that we can create relocations
14538 against them. For normal symbols we output a relocation
14539 against the section that contains them. */
14540 if (! bfd_elf_link_record_dynamic_symbol (info, h))
14541 return FALSE;
14542 }
14543
5e681ec4
PB		 14544 }
14545 else
14546 {
14547 /* For the non-shared case, discard space for relocs against
14548 symbols which turn out to need copy relocs or are not
14549 dynamic. */
14550
f5385ebf
AM		 14551 if (!h->non_got_ref
14552 && ((h->def_dynamic
14553 && !h->def_regular)
5e681ec4
PB		 14554 || (htab->root.dynamic_sections_created
14555 && (h->root.type == bfd_link_hash_undefweak
14556 || h->root.type == bfd_link_hash_undefined))))
14557 {
14558 /* Make sure this symbol is output as a dynamic symbol.
14559 Undefined weak syms won't yet be marked as dynamic. */
14560 if (h->dynindx == -1
f5385ebf 14561 && !h->forced_local)
5e681ec4 14562 {
c152c796 14563 if (! bfd_elf_link_record_dynamic_symbol (info, h))
5e681ec4
PB		 14564 return FALSE;
14565 }
14566
14567 /* If that succeeded, we know we'll be keeping all the
14568 relocs. */
14569 if (h->dynindx != -1)
14570 goto keep;
14571 }
14572
0bdcacaf 14573 eh->dyn_relocs = NULL;
5e681ec4
PB		 14574
14575 keep: ;
14576 }
14577
14578 /* Finally, allocate space. */
0bdcacaf 14579 for (p = eh->dyn_relocs; p != NULL; p = p->next)
5e681ec4 14580 {
0bdcacaf 14581 asection *sreloc = elf_section_data (p->sec)->sreloc;
34e77a92
RS		 14582 if (h->type == STT_GNU_IFUNC
14583 && eh->plt.noncall_refcount == 0
14584 && SYMBOL_REFERENCES_LOCAL (info, h))
14585 elf32_arm_allocate_irelocs (info, sreloc, p->count);
14586 else
14587 elf32_arm_allocate_dynrelocs (info, sreloc, p->count);
5e681ec4
PB		 14588 }
14589
14590 return TRUE;
14591}
14592
08d1f311
DJ		 14593/* Find any dynamic relocs that apply to read-only sections. */
14594
14595static bfd_boolean
8029a119 14596elf32_arm_readonly_dynrelocs (struct elf_link_hash_entry * h, void * inf)
08d1f311 14597{
8029a119 14598 struct elf32_arm_link_hash_entry * eh;
0bdcacaf 14599 struct elf_dyn_relocs * p;
08d1f311 14600
08d1f311 14601 eh = (struct elf32_arm_link_hash_entry *) h;
0bdcacaf 14602 for (p = eh->dyn_relocs; p != NULL; p = p->next)
08d1f311 14603 {
0bdcacaf 14604 asection *s = p->sec;
08d1f311
DJ		 14605
14606 if (s != NULL && (s->flags & SEC_READONLY) != 0)
14607 {
14608 struct bfd_link_info *info = (struct bfd_link_info *) inf;
14609
14610 info->flags |= DF_TEXTREL;
14611
14612 /* Not an error, just cut short the traversal. */
14613 return FALSE;
14614 }
14615 }
14616 return TRUE;
14617}
14618
d504ffc8
DJ		 14619void
14620bfd_elf32_arm_set_byteswap_code (struct bfd_link_info *info,
14621 int byteswap_code)
14622{
14623 struct elf32_arm_link_hash_table *globals;
14624
14625 globals = elf32_arm_hash_table (info);
4dfe6ac6
NC		 14626 if (globals == NULL)
14627 return;
14628
d504ffc8
DJ		 14629 globals->byteswap_code = byteswap_code;
14630}
14631
252b5132
RH		 14632/* Set the sizes of the dynamic sections. */
14633
b34976b6 14634static bfd_boolean
57e8b36a
NC		 14635elf32_arm_size_dynamic_sections (bfd * output_bfd ATTRIBUTE_UNUSED,
14636 struct bfd_link_info * info)
252b5132
RH		 14637{
14638 bfd * dynobj;
14639 asection * s;
b34976b6
AM		 14640 bfd_boolean plt;
14641 bfd_boolean relocs;
5e681ec4
PB		 14642 bfd *ibfd;
14643 struct elf32_arm_link_hash_table *htab;
252b5132 14644
5e681ec4 14645 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 14646 if (htab == NULL)
14647 return FALSE;
14648
252b5132
RH		 14649 dynobj = elf_hash_table (info)->dynobj;
14650 BFD_ASSERT (dynobj != NULL);
39b41c9c 14651 check_use_blx (htab);
252b5132
RH		 14652
14653 if (elf_hash_table (info)->dynamic_sections_created)
14654 {
14655 /* Set the contents of the .interp section to the interpreter. */
9b8b325a 14656 if (bfd_link_executable (info) && !info->nointerp)
252b5132 14657 {
3d4d4302 14658 s = bfd_get_linker_section (dynobj, ".interp");
252b5132 14659 BFD_ASSERT (s != NULL);
eea6121a 14660 s->size = sizeof ELF_DYNAMIC_INTERPRETER;
252b5132
RH		 14661 s->contents = (unsigned char *) ELF_DYNAMIC_INTERPRETER;
14662 }
14663 }
5e681ec4
PB		 14664
14665 /* Set up .got offsets for local syms, and space for local dynamic
14666 relocs. */
c72f2fb2 14667 for (ibfd = info->input_bfds; ibfd != NULL; ibfd = ibfd->link.next)
252b5132 14668 {
5e681ec4
PB		 14669 bfd_signed_vma *local_got;
14670 bfd_signed_vma *end_local_got;
34e77a92 14671 struct arm_local_iplt_info **local_iplt_ptr, *local_iplt;
5e681ec4 14672 char *local_tls_type;
0855e32b 14673 bfd_vma *local_tlsdesc_gotent;
5e681ec4
PB		 14674 bfd_size_type locsymcount;
14675 Elf_Internal_Shdr *symtab_hdr;
14676 asection *srel;
4dfe6ac6 14677 bfd_boolean is_vxworks = htab->vxworks_p;
34e77a92 14678 unsigned int symndx;
5e681ec4 14679
0ffa91dd 14680 if (! is_arm_elf (ibfd))
5e681ec4
PB		 14681 continue;
14682
14683 for (s = ibfd->sections; s != NULL; s = s->next)
14684 {
0bdcacaf 14685 struct elf_dyn_relocs *p;
5e681ec4 14686
0bdcacaf 14687 for (p = (struct elf_dyn_relocs *)
99059e56 14688 elf_section_data (s)->local_dynrel; p != NULL; p = p->next)
5e681ec4 14689 {
0bdcacaf
RS		 14690 if (!bfd_is_abs_section (p->sec)
14691 && bfd_is_abs_section (p->sec->output_section))
5e681ec4
PB		 14692 {
14693 /* Input section has been discarded, either because
14694 it is a copy of a linkonce section or due to
14695 linker script /DISCARD/, so we'll be discarding
14696 the relocs too. */
14697 }
3348747a 14698 else if (is_vxworks
0bdcacaf 14699 && strcmp (p->sec->output_section->name,
3348747a
NS		 14700 ".tls_vars") == 0)
14701 {
14702 /* Relocations in vxworks .tls_vars sections are
14703 handled specially by the loader. */
14704 }
5e681ec4
PB		 14705 else if (p->count != 0)
14706 {
0bdcacaf 14707 srel = elf_section_data (p->sec)->sreloc;
47beaa6a 14708 elf32_arm_allocate_dynrelocs (info, srel, p->count);
0bdcacaf 14709 if ((p->sec->output_section->flags & SEC_READONLY) != 0)
5e681ec4
PB		 14710 info->flags |= DF_TEXTREL;
14711 }
14712 }
14713 }
14714
14715 local_got = elf_local_got_refcounts (ibfd);
14716 if (!local_got)
14717 continue;
14718
0ffa91dd 14719 symtab_hdr = & elf_symtab_hdr (ibfd);
5e681ec4
PB		 14720 locsymcount = symtab_hdr->sh_info;
14721 end_local_got = local_got + locsymcount;
34e77a92 14722 local_iplt_ptr = elf32_arm_local_iplt (ibfd);
ba93b8ac 14723 local_tls_type = elf32_arm_local_got_tls_type (ibfd);
0855e32b 14724 local_tlsdesc_gotent = elf32_arm_local_tlsdesc_gotent (ibfd);
34e77a92 14725 symndx = 0;
362d30a1
RS		 14726 s = htab->root.sgot;
14727 srel = htab->root.srelgot;
0855e32b 14728 for (; local_got < end_local_got;
34e77a92
RS		 14729 ++local_got, ++local_iplt_ptr, ++local_tls_type,
14730 ++local_tlsdesc_gotent, ++symndx)
5e681ec4 14731 {
0855e32b 14732 *local_tlsdesc_gotent = (bfd_vma) -1;
34e77a92
RS		 14733 local_iplt = *local_iplt_ptr;
14734 if (local_iplt != NULL)
14735 {
14736 struct elf_dyn_relocs *p;
14737
14738 if (local_iplt->root.refcount > 0)
14739 {
14740 elf32_arm_allocate_plt_entry (info, TRUE,
14741 &local_iplt->root,
14742 &local_iplt->arm);
14743 if (local_iplt->arm.noncall_refcount == 0)
14744 /* All references to the PLT are calls, so all
14745 non-call references can resolve directly to the
14746 run-time target. This means that the .got entry
14747 would be the same as the .igot.plt entry, so there's
14748 no point creating both. */
14749 *local_got = 0;
14750 }
14751 else
14752 {
14753 BFD_ASSERT (local_iplt->arm.noncall_refcount == 0);
14754 local_iplt->root.offset = (bfd_vma) -1;
14755 }
14756
14757 for (p = local_iplt->dyn_relocs; p != NULL; p = p->next)
14758 {
14759 asection *psrel;
14760
14761 psrel = elf_section_data (p->sec)->sreloc;
14762 if (local_iplt->arm.noncall_refcount == 0)
14763 elf32_arm_allocate_irelocs (info, psrel, p->count);
14764 else
14765 elf32_arm_allocate_dynrelocs (info, psrel, p->count);
14766 }
14767 }
5e681ec4
PB		 14768 if (*local_got > 0)
14769 {
34e77a92
RS		 14770 Elf_Internal_Sym *isym;
14771
eea6121a 14772 *local_got = s->size;
ba93b8ac
DJ		 14773 if (*local_tls_type & GOT_TLS_GD)
14774 /* TLS_GD relocs need an 8-byte structure in the GOT. */
14775 s->size += 8;
0855e32b
NS		 14776 if (*local_tls_type & GOT_TLS_GDESC)
14777 {
14778 *local_tlsdesc_gotent = htab->root.sgotplt->size
14779 - elf32_arm_compute_jump_table_size (htab);
14780 htab->root.sgotplt->size += 8;
14781 *local_got = (bfd_vma) -2;
34e77a92 14782 /* plt.got_offset needs to know there's a TLS_DESC
0855e32b 14783 reloc in the middle of .got.plt. */
99059e56 14784 htab->num_tls_desc++;
0855e32b 14785 }
ba93b8ac
DJ		 14786 if (*local_tls_type & GOT_TLS_IE)
14787 s->size += 4;
ba93b8ac 14788
0855e32b
NS		 14789 if (*local_tls_type & GOT_NORMAL)
14790 {
14791 /* If the symbol is both GD and GDESC, *local_got
14792 may have been overwritten. */
14793 *local_got = s->size;
14794 s->size += 4;
14795 }
14796
34e77a92
RS		 14797 isym = bfd_sym_from_r_symndx (&htab->sym_cache, ibfd, symndx);
14798 if (isym == NULL)
14799 return FALSE;
14800
14801 /* If all references to an STT_GNU_IFUNC PLT are calls,
14802 then all non-call references, including this GOT entry,
14803 resolve directly to the run-time target. */
14804 if (ELF32_ST_TYPE (isym->st_info) == STT_GNU_IFUNC
14805 && (local_iplt == NULL
14806 || local_iplt->arm.noncall_refcount == 0))
14807 elf32_arm_allocate_irelocs (info, srel, 1);
0e1862bb 14808 else if (bfd_link_pic (info) || output_bfd->flags & DYNAMIC)
0855e32b 14809 {
0e1862bb 14810 if ((bfd_link_pic (info) && !(*local_tls_type & GOT_TLS_GDESC))
3064e1ff
JB		 14811 || *local_tls_type & GOT_TLS_GD)
14812 elf32_arm_allocate_dynrelocs (info, srel, 1);
99059e56 14813
0e1862bb 14814 if (bfd_link_pic (info) && *local_tls_type & GOT_TLS_GDESC)
3064e1ff
JB		 14815 {
14816 elf32_arm_allocate_dynrelocs (info,
14817 htab->root.srelplt, 1);
14818 htab->tls_trampoline = -1;
14819 }
0855e32b 14820 }
5e681ec4
PB		 14821 }
14822 else
14823 *local_got = (bfd_vma) -1;
14824 }
252b5132
RH		 14825 }
14826
ba93b8ac
DJ		 14827 if (htab->tls_ldm_got.refcount > 0)
14828 {
14829 /* Allocate two GOT entries and one dynamic relocation (if necessary)
14830 for R_ARM_TLS_LDM32 relocations. */
362d30a1
RS		 14831 htab->tls_ldm_got.offset = htab->root.sgot->size;
14832 htab->root.sgot->size += 8;
0e1862bb 14833 if (bfd_link_pic (info))
47beaa6a 14834 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
ba93b8ac
DJ		 14835 }
14836 else
14837 htab->tls_ldm_got.offset = -1;
14838
5e681ec4
PB		 14839 /* Allocate global sym .plt and .got entries, and space for global
14840 sym dynamic relocs. */
47beaa6a 14841 elf_link_hash_traverse (& htab->root, allocate_dynrelocs_for_symbol, info);
252b5132 14842
d504ffc8 14843 /* Here we rummage through the found bfds to collect glue information. */
c72f2fb2 14844 for (ibfd = info->input_bfds; ibfd != NULL; ibfd = ibfd->link.next)
c7b8f16e 14845 {
0ffa91dd 14846 if (! is_arm_elf (ibfd))
e44a2c9c
AM		 14847 continue;
14848
c7b8f16e
JB		 14849 /* Initialise mapping tables for code/data. */
14850 bfd_elf32_arm_init_maps (ibfd);
906e58ca 14851
c7b8f16e 14852 if (!bfd_elf32_arm_process_before_allocation (ibfd, info)
a504d23a
LA		 14853 || !bfd_elf32_arm_vfp11_erratum_scan (ibfd, info)
14854 || !bfd_elf32_arm_stm32l4xx_erratum_scan (ibfd, info))
99059e56
RM		 14855 /* xgettext:c-format */
14856 _bfd_error_handler (_("Errors encountered processing file %s"),
c7b8f16e
JB		 14857 ibfd->filename);
14858 }
d504ffc8 14859
3e6b1042
DJ		 14860 /* Allocate space for the glue sections now that we've sized them. */
14861 bfd_elf32_arm_allocate_interworking_sections (info);
14862
0855e32b
NS		 14863 /* For every jump slot reserved in the sgotplt, reloc_count is
14864 incremented. However, when we reserve space for TLS descriptors,
14865 it's not incremented, so in order to compute the space reserved
14866 for them, it suffices to multiply the reloc count by the jump
14867 slot size. */
14868 if (htab->root.srelplt)
14869 htab->sgotplt_jump_table_size = elf32_arm_compute_jump_table_size(htab);
14870
14871 if (htab->tls_trampoline)
14872 {
14873 if (htab->root.splt->size == 0)
14874 htab->root.splt->size += htab->plt_header_size;
b38cadfb 14875
0855e32b
NS		 14876 htab->tls_trampoline = htab->root.splt->size;
14877 htab->root.splt->size += htab->plt_entry_size;
b38cadfb 14878
0855e32b 14879 /* If we're not using lazy TLS relocations, don't generate the
99059e56 14880 PLT and GOT entries they require. */
0855e32b
NS		 14881 if (!(info->flags & DF_BIND_NOW))
14882 {
14883 htab->dt_tlsdesc_got = htab->root.sgot->size;
14884 htab->root.sgot->size += 4;
14885
14886 htab->dt_tlsdesc_plt = htab->root.splt->size;
14887 htab->root.splt->size += 4 * ARRAY_SIZE (dl_tlsdesc_lazy_trampoline);
14888 }
14889 }
14890
252b5132
RH		 14891 /* The check_relocs and adjust_dynamic_symbol entry points have
14892 determined the sizes of the various dynamic sections. Allocate
14893 memory for them. */
b34976b6
AM		 14894 plt = FALSE;
14895 relocs = FALSE;
252b5132
RH		 14896 for (s = dynobj->sections; s != NULL; s = s->next)
14897 {
14898 const char * name;
252b5132
RH		 14899
14900 if ((s->flags & SEC_LINKER_CREATED) == 0)
14901 continue;
14902
14903 /* It's OK to base decisions on the section name, because none
14904 of the dynobj section names depend upon the input files. */
14905 name = bfd_get_section_name (dynobj, s);
14906
34e77a92 14907 if (s == htab->root.splt)
252b5132 14908 {
c456f082
AM		 14909 /* Remember whether there is a PLT. */
14910 plt = s->size != 0;
252b5132 14911 }
0112cd26 14912 else if (CONST_STRNEQ (name, ".rel"))
252b5132 14913 {
c456f082 14914 if (s->size != 0)
252b5132 14915 {
252b5132 14916 /* Remember whether there are any reloc sections other
00a97672 14917 than .rel(a).plt and .rela.plt.unloaded. */
362d30a1 14918 if (s != htab->root.srelplt && s != htab->srelplt2)
b34976b6 14919 relocs = TRUE;
252b5132
RH		 14920
14921 /* We use the reloc_count field as a counter if we need
14922 to copy relocs into the output file. */
14923 s->reloc_count = 0;
14924 }
14925 }
34e77a92
RS		 14926 else if (s != htab->root.sgot
14927 && s != htab->root.sgotplt
14928 && s != htab->root.iplt
14929 && s != htab->root.igotplt
14930 && s != htab->sdynbss)
252b5132
RH		 14931 {
14932 /* It's not one of our sections, so don't allocate space. */
14933 continue;
14934 }
14935
c456f082 14936 if (s->size == 0)
252b5132 14937 {
c456f082 14938 /* If we don't need this section, strip it from the
00a97672
RS		 14939 output file. This is mostly to handle .rel(a).bss and
14940 .rel(a).plt. We must create both sections in
c456f082
AM		 14941 create_dynamic_sections, because they must be created
14942 before the linker maps input sections to output
14943 sections. The linker does that before
14944 adjust_dynamic_symbol is called, and it is that
14945 function which decides whether anything needs to go
14946 into these sections. */
8423293d 14947 s->flags |= SEC_EXCLUDE;
252b5132
RH		 14948 continue;
14949 }
14950
c456f082
AM		 14951 if ((s->flags & SEC_HAS_CONTENTS) == 0)
14952 continue;
14953
252b5132 14954 /* Allocate memory for the section contents. */
21d799b5 14955 s->contents = (unsigned char *) bfd_zalloc (dynobj, s->size);
c456f082 14956 if (s->contents == NULL)
b34976b6 14957 return FALSE;
252b5132
RH		 14958 }
14959
14960 if (elf_hash_table (info)->dynamic_sections_created)
14961 {
14962 /* Add some entries to the .dynamic section. We fill in the
14963 values later, in elf32_arm_finish_dynamic_sections, but we
14964 must add the entries now so that we get the correct size for
14965 the .dynamic section. The DT_DEBUG entry is filled in by the
14966 dynamic linker and used by the debugger. */
dc810e39 14967#define add_dynamic_entry(TAG, VAL) \
5a580b3a 14968 _bfd_elf_add_dynamic_entry (info, TAG, VAL)
dc810e39 14969
0e1862bb 14970 if (bfd_link_executable (info))
252b5132 14971 {
dc810e39 14972 if (!add_dynamic_entry (DT_DEBUG, 0))
b34976b6 14973 return FALSE;
252b5132
RH		 14974 }
14975
14976 if (plt)
14977 {
dc810e39
AM		 14978 if ( !add_dynamic_entry (DT_PLTGOT, 0)
14979 || !add_dynamic_entry (DT_PLTRELSZ, 0)
00a97672
RS		 14980 || !add_dynamic_entry (DT_PLTREL,
14981 htab->use_rel ? DT_REL : DT_RELA)
dc810e39 14982 || !add_dynamic_entry (DT_JMPREL, 0))
b34976b6 14983 return FALSE;
0855e32b
NS		 14984
14985 if (htab->dt_tlsdesc_plt &&
b38cadfb 14986 (!add_dynamic_entry (DT_TLSDESC_PLT,0)
0855e32b 14987 || !add_dynamic_entry (DT_TLSDESC_GOT,0)))
b38cadfb 14988 return FALSE;
252b5132
RH		 14989 }
14990
14991 if (relocs)
14992 {
00a97672
RS		 14993 if (htab->use_rel)
14994 {
14995 if (!add_dynamic_entry (DT_REL, 0)
14996 || !add_dynamic_entry (DT_RELSZ, 0)
14997 || !add_dynamic_entry (DT_RELENT, RELOC_SIZE (htab)))
14998 return FALSE;
14999 }
15000 else
15001 {
15002 if (!add_dynamic_entry (DT_RELA, 0)
15003 || !add_dynamic_entry (DT_RELASZ, 0)
15004 || !add_dynamic_entry (DT_RELAENT, RELOC_SIZE (htab)))
15005 return FALSE;
15006 }
252b5132
RH		 15007 }
15008
08d1f311
DJ		 15009 /* If any dynamic relocs apply to a read-only section,
15010 then we need a DT_TEXTREL entry. */
15011 if ((info->flags & DF_TEXTREL) == 0)
8029a119
NC		 15012 elf_link_hash_traverse (& htab->root, elf32_arm_readonly_dynrelocs,
15013 info);
08d1f311 15014
99e4ae17 15015 if ((info->flags & DF_TEXTREL) != 0)
252b5132 15016 {
dc810e39 15017 if (!add_dynamic_entry (DT_TEXTREL, 0))
b34976b6 15018 return FALSE;
252b5132 15019 }
7a2b07ff
NS		 15020 if (htab->vxworks_p
15021 && !elf_vxworks_add_dynamic_entries (output_bfd, info))
15022 return FALSE;
252b5132 15023 }
8532796c 15024#undef add_dynamic_entry
252b5132 15025
b34976b6 15026 return TRUE;
252b5132
RH		 15027}
15028
0855e32b
NS		 15029/* Size sections even though they're not dynamic. We use it to setup
15030 _TLS_MODULE_BASE_, if needed. */
15031
15032static bfd_boolean
15033elf32_arm_always_size_sections (bfd *output_bfd,
99059e56 15034 struct bfd_link_info *info)
0855e32b
NS		 15035{
15036 asection *tls_sec;
15037
0e1862bb 15038 if (bfd_link_relocatable (info))
0855e32b
NS		 15039 return TRUE;
15040
15041 tls_sec = elf_hash_table (info)->tls_sec;
15042
15043 if (tls_sec)
15044 {
15045 struct elf_link_hash_entry *tlsbase;
15046
15047 tlsbase = elf_link_hash_lookup
15048 (elf_hash_table (info), "_TLS_MODULE_BASE_", TRUE, TRUE, FALSE);
15049
15050 if (tlsbase)
99059e56
RM		 15051 {
15052 struct bfd_link_hash_entry *bh = NULL;
0855e32b 15053 const struct elf_backend_data *bed
99059e56 15054 = get_elf_backend_data (output_bfd);
0855e32b 15055
99059e56 15056 if (!(_bfd_generic_link_add_one_symbol
0855e32b
NS		 15057 (info, output_bfd, "_TLS_MODULE_BASE_", BSF_LOCAL,
15058 tls_sec, 0, NULL, FALSE,
15059 bed->collect, &bh)))
15060 return FALSE;
b38cadfb 15061
99059e56
RM		 15062 tlsbase->type = STT_TLS;
15063 tlsbase = (struct elf_link_hash_entry *)bh;
15064 tlsbase->def_regular = 1;
15065 tlsbase->other = STV_HIDDEN;
15066 (*bed->elf_backend_hide_symbol) (info, tlsbase, TRUE);
0855e32b
NS		 15067 }
15068 }
15069 return TRUE;
15070}
15071
252b5132
RH		 15072/* Finish up dynamic symbol handling. We set the contents of various
15073 dynamic sections here. */
15074
b34976b6 15075static bfd_boolean
906e58ca
NC		 15076elf32_arm_finish_dynamic_symbol (bfd * output_bfd,
15077 struct bfd_link_info * info,
15078 struct elf_link_hash_entry * h,
15079 Elf_Internal_Sym * sym)
252b5132 15080{
e5a52504 15081 struct elf32_arm_link_hash_table *htab;
b7693d02 15082 struct elf32_arm_link_hash_entry *eh;
252b5132 15083
e5a52504 15084 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 15085 if (htab == NULL)
15086 return FALSE;
15087
b7693d02 15088 eh = (struct elf32_arm_link_hash_entry *) h;
252b5132
RH		 15089
15090 if (h->plt.offset != (bfd_vma) -1)
15091 {
34e77a92 15092 if (!eh->is_iplt)
e5a52504 15093 {
34e77a92 15094 BFD_ASSERT (h->dynindx != -1);
57460bcf
NC		 15095 if (! elf32_arm_populate_plt_entry (output_bfd, info, &h->plt, &eh->plt,
15096 h->dynindx, 0))
15097 return FALSE;
e5a52504 15098 }
57e8b36a 15099
f5385ebf 15100 if (!h->def_regular)
252b5132
RH		 15101 {
15102 /* Mark the symbol as undefined, rather than as defined in
3a635617 15103 the .plt section. */
252b5132 15104 sym->st_shndx = SHN_UNDEF;
3a635617 15105 /* If the symbol is weak we need to clear the value.
d982ba73
PB		 15106 Otherwise, the PLT entry would provide a definition for
15107 the symbol even if the symbol wasn't defined anywhere,
3a635617
WN		 15108 and so the symbol would never be NULL. Leave the value if
15109 there were any relocations where pointer equality matters
15110 (this is a clue for the dynamic linker, to make function
15111 pointer comparisons work between an application and shared
15112 library). */
97323ad1 15113 if (!h->ref_regular_nonweak || !h->pointer_equality_needed)
d982ba73 15114 sym->st_value = 0;
252b5132 15115 }
34e77a92
RS		 15116 else if (eh->is_iplt && eh->plt.noncall_refcount != 0)
15117 {
15118 /* At least one non-call relocation references this .iplt entry,
15119 so the .iplt entry is the function's canonical address. */
15120 sym->st_info = ELF_ST_INFO (ELF_ST_BIND (sym->st_info), STT_FUNC);
39d911fc 15121 ARM_SET_SYM_BRANCH_TYPE (sym->st_target_internal, ST_BRANCH_TO_ARM);
34e77a92
RS		 15122 sym->st_shndx = (_bfd_elf_section_from_bfd_section
15123 (output_bfd, htab->root.iplt->output_section));
15124 sym->st_value = (h->plt.offset
15125 + htab->root.iplt->output_section->vma
15126 + htab->root.iplt->output_offset);
15127 }
252b5132
RH		 15128 }
15129
f5385ebf 15130 if (h->needs_copy)
252b5132
RH		 15131 {
15132 asection * s;
947216bf 15133 Elf_Internal_Rela rel;
252b5132
RH		 15134
15135 /* This symbol needs a copy reloc. Set it up. */
252b5132
RH		 15136 BFD_ASSERT (h->dynindx != -1
15137 && (h->root.type == bfd_link_hash_defined
15138 || h->root.type == bfd_link_hash_defweak));
15139
362d30a1 15140 s = htab->srelbss;
252b5132
RH		 15141 BFD_ASSERT (s != NULL);
15142
00a97672 15143 rel.r_addend = 0;
252b5132
RH		 15144 rel.r_offset = (h->root.u.def.value
15145 + h->root.u.def.section->output_section->vma
15146 + h->root.u.def.section->output_offset);
15147 rel.r_info = ELF32_R_INFO (h->dynindx, R_ARM_COPY);
47beaa6a 15148 elf32_arm_add_dynreloc (output_bfd, info, s, &rel);
252b5132
RH		 15149 }
15150
00a97672
RS		 15151 /* Mark _DYNAMIC and _GLOBAL_OFFSET_TABLE_ as absolute. On VxWorks,
15152 the _GLOBAL_OFFSET_TABLE_ symbol is not absolute: it is relative
15153 to the ".got" section. */
9637f6ef 15154 if (h == htab->root.hdynamic
00a97672 15155 || (!htab->vxworks_p && h == htab->root.hgot))
252b5132
RH		 15156 sym->st_shndx = SHN_ABS;
15157
b34976b6 15158 return TRUE;
252b5132
RH		 15159}
15160
0855e32b
NS		 15161static void
15162arm_put_trampoline (struct elf32_arm_link_hash_table *htab, bfd *output_bfd,
15163 void *contents,
15164 const unsigned long *template, unsigned count)
15165{
15166 unsigned ix;
b38cadfb 15167
0855e32b
NS		 15168 for (ix = 0; ix != count; ix++)
15169 {
15170 unsigned long insn = template[ix];
15171
15172 /* Emit mov pc,rx if bx is not permitted. */
15173 if (htab->fix_v4bx == 1 && (insn & 0x0ffffff0) == 0x012fff10)
15174 insn = (insn & 0xf000000f) | 0x01a0f000;
15175 put_arm_insn (htab, output_bfd, insn, (char *)contents + ix*4);
15176 }
15177}
15178
99059e56
RM		 15179/* Install the special first PLT entry for elf32-arm-nacl. Unlike
15180 other variants, NaCl needs this entry in a static executable's
15181 .iplt too. When we're handling that case, GOT_DISPLACEMENT is
15182 zero. For .iplt really only the last bundle is useful, and .iplt
15183 could have a shorter first entry, with each individual PLT entry's
15184 relative branch calculated differently so it targets the last
15185 bundle instead of the instruction before it (labelled .Lplt_tail
15186 above). But it's simpler to keep the size and layout of PLT0
15187 consistent with the dynamic case, at the cost of some dead code at
15188 the start of .iplt and the one dead store to the stack at the start
15189 of .Lplt_tail. */
15190static void
15191arm_nacl_put_plt0 (struct elf32_arm_link_hash_table *htab, bfd *output_bfd,
15192 asection *plt, bfd_vma got_displacement)
15193{
15194 unsigned int i;
15195
15196 put_arm_insn (htab, output_bfd,
15197 elf32_arm_nacl_plt0_entry[0]
15198 | arm_movw_immediate (got_displacement),
15199 plt->contents + 0);
15200 put_arm_insn (htab, output_bfd,
15201 elf32_arm_nacl_plt0_entry[1]
15202 | arm_movt_immediate (got_displacement),
15203 plt->contents + 4);
15204
15205 for (i = 2; i < ARRAY_SIZE (elf32_arm_nacl_plt0_entry); ++i)
15206 put_arm_insn (htab, output_bfd,
15207 elf32_arm_nacl_plt0_entry[i],
15208 plt->contents + (i * 4));
15209}
15210
252b5132
RH		 15211/* Finish up the dynamic sections. */
15212
b34976b6 15213static bfd_boolean
57e8b36a 15214elf32_arm_finish_dynamic_sections (bfd * output_bfd, struct bfd_link_info * info)
252b5132
RH		 15215{
15216 bfd * dynobj;
15217 asection * sgot;
15218 asection * sdyn;
4dfe6ac6
NC		 15219 struct elf32_arm_link_hash_table *htab;
15220
15221 htab = elf32_arm_hash_table (info);
15222 if (htab == NULL)
15223 return FALSE;
252b5132
RH		 15224
15225 dynobj = elf_hash_table (info)->dynobj;
15226
362d30a1 15227 sgot = htab->root.sgotplt;
894891db
NC		 15228 /* A broken linker script might have discarded the dynamic sections.
15229 Catch this here so that we do not seg-fault later on. */
15230 if (sgot != NULL && bfd_is_abs_section (sgot->output_section))
15231 return FALSE;
3d4d4302 15232 sdyn = bfd_get_linker_section (dynobj, ".dynamic");
252b5132
RH		 15233
15234 if (elf_hash_table (info)->dynamic_sections_created)
15235 {
15236 asection *splt;
15237 Elf32_External_Dyn *dyncon, *dynconend;
15238
362d30a1 15239 splt = htab->root.splt;
24a1ba0f 15240 BFD_ASSERT (splt != NULL && sdyn != NULL);
cbc704f3 15241 BFD_ASSERT (htab->symbian_p || sgot != NULL);
252b5132
RH		 15242
15243 dyncon = (Elf32_External_Dyn *) sdyn->contents;
eea6121a 15244 dynconend = (Elf32_External_Dyn *) (sdyn->contents + sdyn->size);
9b485d32 15245
252b5132
RH		 15246 for (; dyncon < dynconend; dyncon++)
15247 {
15248 Elf_Internal_Dyn dyn;
15249 const char * name;
15250 asection * s;
15251
15252 bfd_elf32_swap_dyn_in (dynobj, dyncon, &dyn);
15253
15254 switch (dyn.d_tag)
15255 {
229fcec5
MM		 15256 unsigned int type;
15257
252b5132 15258 default:
7a2b07ff
NS		 15259 if (htab->vxworks_p
15260 && elf_vxworks_finish_dynamic_entry (output_bfd, &dyn))
15261 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
252b5132
RH		 15262 break;
15263
229fcec5
MM		 15264 case DT_HASH:
15265 name = ".hash";
15266 goto get_vma_if_bpabi;
15267 case DT_STRTAB:
15268 name = ".dynstr";
15269 goto get_vma_if_bpabi;
15270 case DT_SYMTAB:
15271 name = ".dynsym";
15272 goto get_vma_if_bpabi;
c0042f5d
MM		 15273 case DT_VERSYM:
15274 name = ".gnu.version";
15275 goto get_vma_if_bpabi;
15276 case DT_VERDEF:
15277 name = ".gnu.version_d";
15278 goto get_vma_if_bpabi;
15279 case DT_VERNEED:
15280 name = ".gnu.version_r";
15281 goto get_vma_if_bpabi;
15282
252b5132
RH		 15283 case DT_PLTGOT:
15284 name = ".got";
15285 goto get_vma;
15286 case DT_JMPREL:
00a97672 15287 name = RELOC_SECTION (htab, ".plt");
252b5132
RH		 15288 get_vma:
15289 s = bfd_get_section_by_name (output_bfd, name);
05456594
NC		 15290 if (s == NULL)
15291 {
15292 /* PR ld/14397: Issue an error message if a required section is missing. */
15293 (*_bfd_error_handler)
15294 (_("error: required section '%s' not found in the linker script"), name);
15295 bfd_set_error (bfd_error_invalid_operation);
15296 return FALSE;
15297 }
229fcec5
MM		 15298 if (!htab->symbian_p)
15299 dyn.d_un.d_ptr = s->vma;
15300 else
15301 /* In the BPABI, tags in the PT_DYNAMIC section point
15302 at the file offset, not the memory address, for the
15303 convenience of the post linker. */
15304 dyn.d_un.d_ptr = s->filepos;
252b5132
RH		 15305 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
15306 break;
15307
229fcec5
MM		 15308 get_vma_if_bpabi:
15309 if (htab->symbian_p)
15310 goto get_vma;
15311 break;
15312
252b5132 15313 case DT_PLTRELSZ:
362d30a1 15314 s = htab->root.srelplt;
252b5132 15315 BFD_ASSERT (s != NULL);
eea6121a 15316 dyn.d_un.d_val = s->size;
252b5132
RH		 15317 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
15318 break;
906e58ca 15319
252b5132 15320 case DT_RELSZ:
00a97672 15321 case DT_RELASZ:
229fcec5
MM		 15322 if (!htab->symbian_p)
15323 {
15324 /* My reading of the SVR4 ABI indicates that the
15325 procedure linkage table relocs (DT_JMPREL) should be
15326 included in the overall relocs (DT_REL). This is
15327 what Solaris does. However, UnixWare can not handle
15328 that case. Therefore, we override the DT_RELSZ entry
15329 here to make it not include the JMPREL relocs. Since
00a97672 15330 the linker script arranges for .rel(a).plt to follow all
229fcec5
MM		 15331 other relocation sections, we don't have to worry
15332 about changing the DT_REL entry. */
362d30a1 15333 s = htab->root.srelplt;
229fcec5
MM		 15334 if (s != NULL)
15335 dyn.d_un.d_val -= s->size;
15336 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
15337 break;
15338 }
8029a119 15339 /* Fall through. */
229fcec5
MM		 15340
15341 case DT_REL:
15342 case DT_RELA:
229fcec5
MM		 15343 /* In the BPABI, the DT_REL tag must point at the file
15344 offset, not the VMA, of the first relocation
15345 section. So, we use code similar to that in
15346 elflink.c, but do not check for SHF_ALLOC on the
15347 relcoation section, since relocations sections are
15348 never allocated under the BPABI. The comments above
15349 about Unixware notwithstanding, we include all of the
15350 relocations here. */
15351 if (htab->symbian_p)
15352 {
15353 unsigned int i;
15354 type = ((dyn.d_tag == DT_REL || dyn.d_tag == DT_RELSZ)
15355 ? SHT_REL : SHT_RELA);
15356 dyn.d_un.d_val = 0;
15357 for (i = 1; i < elf_numsections (output_bfd); i++)
15358 {
906e58ca 15359 Elf_Internal_Shdr *hdr
229fcec5
MM		 15360 = elf_elfsections (output_bfd)[i];
15361 if (hdr->sh_type == type)
15362 {
906e58ca 15363 if (dyn.d_tag == DT_RELSZ
229fcec5
MM		 15364 || dyn.d_tag == DT_RELASZ)
15365 dyn.d_un.d_val += hdr->sh_size;
de52dba4
AM		 15366 else if ((ufile_ptr) hdr->sh_offset
15367 <= dyn.d_un.d_val - 1)
229fcec5
MM		 15368 dyn.d_un.d_val = hdr->sh_offset;
15369 }
15370 }
15371 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
15372 }
252b5132 15373 break;
88f7bcd5 15374
0855e32b 15375 case DT_TLSDESC_PLT:
99059e56 15376 s = htab->root.splt;
0855e32b
NS		 15377 dyn.d_un.d_ptr = (s->output_section->vma + s->output_offset
15378 + htab->dt_tlsdesc_plt);
15379 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
15380 break;
15381
15382 case DT_TLSDESC_GOT:
99059e56 15383 s = htab->root.sgot;
0855e32b 15384 dyn.d_un.d_ptr = (s->output_section->vma + s->output_offset
99059e56 15385 + htab->dt_tlsdesc_got);
0855e32b
NS		 15386 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
15387 break;
15388
88f7bcd5
NC		 15389 /* Set the bottom bit of DT_INIT/FINI if the
15390 corresponding function is Thumb. */
15391 case DT_INIT:
15392 name = info->init_function;
15393 goto get_sym;
15394 case DT_FINI:
15395 name = info->fini_function;
15396 get_sym:
15397 /* If it wasn't set by elf_bfd_final_link
4cc11e76 15398 then there is nothing to adjust. */
88f7bcd5
NC		 15399 if (dyn.d_un.d_val != 0)
15400 {
15401 struct elf_link_hash_entry * eh;
15402
15403 eh = elf_link_hash_lookup (elf_hash_table (info), name,
b34976b6 15404 FALSE, FALSE, TRUE);
39d911fc
TP		 15405 if (eh != NULL
15406 && ARM_GET_SYM_BRANCH_TYPE (eh->target_internal)
15407 == ST_BRANCH_TO_THUMB)
88f7bcd5
NC		 15408 {
15409 dyn.d_un.d_val |= 1;
b34976b6 15410 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
88f7bcd5
NC		 15411 }
15412 }
15413 break;
252b5132
RH		 15414 }
15415 }
15416
24a1ba0f 15417 /* Fill in the first entry in the procedure linkage table. */
4dfe6ac6 15418 if (splt->size > 0 && htab->plt_header_size)
f7a74f8c 15419 {
00a97672
RS		 15420 const bfd_vma *plt0_entry;
15421 bfd_vma got_address, plt_address, got_displacement;
15422
15423 /* Calculate the addresses of the GOT and PLT. */
15424 got_address = sgot->output_section->vma + sgot->output_offset;
15425 plt_address = splt->output_section->vma + splt->output_offset;
15426
15427 if (htab->vxworks_p)
15428 {
15429 /* The VxWorks GOT is relocated by the dynamic linker.
15430 Therefore, we must emit relocations rather than simply
15431 computing the values now. */
15432 Elf_Internal_Rela rel;
15433
15434 plt0_entry = elf32_arm_vxworks_exec_plt0_entry;
52ab56c2
PB		 15435 put_arm_insn (htab, output_bfd, plt0_entry[0],
15436 splt->contents + 0);
15437 put_arm_insn (htab, output_bfd, plt0_entry[1],
15438 splt->contents + 4);
15439 put_arm_insn (htab, output_bfd, plt0_entry[2],
15440 splt->contents + 8);
00a97672
RS		 15441 bfd_put_32 (output_bfd, got_address, splt->contents + 12);
15442
8029a119 15443 /* Generate a relocation for _GLOBAL_OFFSET_TABLE_. */
00a97672
RS		 15444 rel.r_offset = plt_address + 12;
15445 rel.r_info = ELF32_R_INFO (htab->root.hgot->indx, R_ARM_ABS32);
15446 rel.r_addend = 0;
15447 SWAP_RELOC_OUT (htab) (output_bfd, &rel,
15448 htab->srelplt2->contents);
15449 }
b38cadfb 15450 else if (htab->nacl_p)
99059e56
RM		 15451 arm_nacl_put_plt0 (htab, output_bfd, splt,
15452 got_address + 8 - (plt_address + 16));
eed94f8f
NC		 15453 else if (using_thumb_only (htab))
15454 {
15455 got_displacement = got_address - (plt_address + 12);
15456
15457 plt0_entry = elf32_thumb2_plt0_entry;
15458 put_arm_insn (htab, output_bfd, plt0_entry[0],
15459 splt->contents + 0);
15460 put_arm_insn (htab, output_bfd, plt0_entry[1],
15461 splt->contents + 4);
15462 put_arm_insn (htab, output_bfd, plt0_entry[2],
15463 splt->contents + 8);
15464
15465 bfd_put_32 (output_bfd, got_displacement, splt->contents + 12);
15466 }
00a97672
RS		 15467 else
15468 {
15469 got_displacement = got_address - (plt_address + 16);
15470
15471 plt0_entry = elf32_arm_plt0_entry;
52ab56c2
PB		 15472 put_arm_insn (htab, output_bfd, plt0_entry[0],
15473 splt->contents + 0);
15474 put_arm_insn (htab, output_bfd, plt0_entry[1],
15475 splt->contents + 4);
15476 put_arm_insn (htab, output_bfd, plt0_entry[2],
15477 splt->contents + 8);
15478 put_arm_insn (htab, output_bfd, plt0_entry[3],
15479 splt->contents + 12);
5e681ec4 15480
5e681ec4 15481#ifdef FOUR_WORD_PLT
00a97672
RS		 15482 /* The displacement value goes in the otherwise-unused
15483 last word of the second entry. */
15484 bfd_put_32 (output_bfd, got_displacement, splt->contents + 28);
5e681ec4 15485#else
00a97672 15486 bfd_put_32 (output_bfd, got_displacement, splt->contents + 16);
5e681ec4 15487#endif
00a97672 15488 }
f7a74f8c 15489 }
252b5132
RH		 15490
15491 /* UnixWare sets the entsize of .plt to 4, although that doesn't
15492 really seem like the right value. */
74541ad4
AM		 15493 if (splt->output_section->owner == output_bfd)
15494 elf_section_data (splt->output_section)->this_hdr.sh_entsize = 4;
00a97672 15495
0855e32b
NS		 15496 if (htab->dt_tlsdesc_plt)
15497 {
15498 bfd_vma got_address
15499 = sgot->output_section->vma + sgot->output_offset;
15500 bfd_vma gotplt_address = (htab->root.sgot->output_section->vma
15501 + htab->root.sgot->output_offset);
15502 bfd_vma plt_address
15503 = splt->output_section->vma + splt->output_offset;
15504
b38cadfb 15505 arm_put_trampoline (htab, output_bfd,
0855e32b
NS		 15506 splt->contents + htab->dt_tlsdesc_plt,
15507 dl_tlsdesc_lazy_trampoline, 6);
15508
15509 bfd_put_32 (output_bfd,
15510 gotplt_address + htab->dt_tlsdesc_got
15511 - (plt_address + htab->dt_tlsdesc_plt)
15512 - dl_tlsdesc_lazy_trampoline[6],
15513 splt->contents + htab->dt_tlsdesc_plt + 24);
15514 bfd_put_32 (output_bfd,
15515 got_address - (plt_address + htab->dt_tlsdesc_plt)
15516 - dl_tlsdesc_lazy_trampoline[7],
15517 splt->contents + htab->dt_tlsdesc_plt + 24 + 4);
15518 }
15519
15520 if (htab->tls_trampoline)
15521 {
b38cadfb 15522 arm_put_trampoline (htab, output_bfd,
0855e32b
NS		 15523 splt->contents + htab->tls_trampoline,
15524 tls_trampoline, 3);
15525#ifdef FOUR_WORD_PLT
15526 bfd_put_32 (output_bfd, 0x00000000,
15527 splt->contents + htab->tls_trampoline + 12);
b38cadfb 15528#endif
0855e32b
NS		 15529 }
15530
0e1862bb
L		 15531 if (htab->vxworks_p
15532 && !bfd_link_pic (info)
15533 && htab->root.splt->size > 0)
00a97672
RS		 15534 {
15535 /* Correct the .rel(a).plt.unloaded relocations. They will have
15536 incorrect symbol indexes. */
15537 int num_plts;
eed62c48 15538 unsigned char *p;
00a97672 15539
362d30a1 15540 num_plts = ((htab->root.splt->size - htab->plt_header_size)
00a97672
RS		 15541 / htab->plt_entry_size);
15542 p = htab->srelplt2->contents + RELOC_SIZE (htab);
15543
15544 for (; num_plts; num_plts--)
15545 {
15546 Elf_Internal_Rela rel;
15547
15548 SWAP_RELOC_IN (htab) (output_bfd, p, &rel);
15549 rel.r_info = ELF32_R_INFO (htab->root.hgot->indx, R_ARM_ABS32);
15550 SWAP_RELOC_OUT (htab) (output_bfd, &rel, p);
15551 p += RELOC_SIZE (htab);
15552
15553 SWAP_RELOC_IN (htab) (output_bfd, p, &rel);
15554 rel.r_info = ELF32_R_INFO (htab->root.hplt->indx, R_ARM_ABS32);
15555 SWAP_RELOC_OUT (htab) (output_bfd, &rel, p);
15556 p += RELOC_SIZE (htab);
15557 }
15558 }
252b5132
RH		 15559 }
15560
99059e56
RM		 15561 if (htab->nacl_p && htab->root.iplt != NULL && htab->root.iplt->size > 0)
15562 /* NaCl uses a special first entry in .iplt too. */
15563 arm_nacl_put_plt0 (htab, output_bfd, htab->root.iplt, 0);
15564
252b5132 15565 /* Fill in the first three entries in the global offset table. */
229fcec5 15566 if (sgot)
252b5132 15567 {
229fcec5
MM		 15568 if (sgot->size > 0)
15569 {
15570 if (sdyn == NULL)
15571 bfd_put_32 (output_bfd, (bfd_vma) 0, sgot->contents);
15572 else
15573 bfd_put_32 (output_bfd,
15574 sdyn->output_section->vma + sdyn->output_offset,
15575 sgot->contents);
15576 bfd_put_32 (output_bfd, (bfd_vma) 0, sgot->contents + 4);
15577 bfd_put_32 (output_bfd, (bfd_vma) 0, sgot->contents + 8);
15578 }
252b5132 15579
229fcec5
MM		 15580 elf_section_data (sgot->output_section)->this_hdr.sh_entsize = 4;
15581 }
252b5132 15582
b34976b6 15583 return TRUE;
252b5132
RH		 15584}
15585
ba96a88f 15586static void
57e8b36a 15587elf32_arm_post_process_headers (bfd * abfd, struct bfd_link_info * link_info ATTRIBUTE_UNUSED)
ba96a88f 15588{
9b485d32 15589 Elf_Internal_Ehdr * i_ehdrp; /* ELF file header, internal form. */
e489d0ae 15590 struct elf32_arm_link_hash_table *globals;
ac4c9b04 15591 struct elf_segment_map *m;
ba96a88f
NC		 15592
15593 i_ehdrp = elf_elfheader (abfd);
15594
94a3258f
PB		 15595 if (EF_ARM_EABI_VERSION (i_ehdrp->e_flags) == EF_ARM_EABI_UNKNOWN)
15596 i_ehdrp->e_ident[EI_OSABI] = ELFOSABI_ARM;
15597 else
7394f108 15598 _bfd_elf_post_process_headers (abfd, link_info);
ba96a88f 15599 i_ehdrp->e_ident[EI_ABIVERSION] = ARM_ELF_ABI_VERSION;
e489d0ae 15600
93204d3a
PB		 15601 if (link_info)
15602 {
15603 globals = elf32_arm_hash_table (link_info);
4dfe6ac6 15604 if (globals != NULL && globals->byteswap_code)
93204d3a
PB		 15605 i_ehdrp->e_flags |= EF_ARM_BE8;
15606 }
3bfcb652
NC		 15607
15608 if (EF_ARM_EABI_VERSION (i_ehdrp->e_flags) == EF_ARM_EABI_VER5
15609 && ((i_ehdrp->e_type == ET_DYN) || (i_ehdrp->e_type == ET_EXEC)))
15610 {
15611 int abi = bfd_elf_get_obj_attr_int (abfd, OBJ_ATTR_PROC, Tag_ABI_VFP_args);
5c294fee 15612 if (abi == AEABI_VFP_args_vfp)
3bfcb652
NC		 15613 i_ehdrp->e_flags |= EF_ARM_ABI_FLOAT_HARD;
15614 else
15615 i_ehdrp->e_flags |= EF_ARM_ABI_FLOAT_SOFT;
15616 }
ac4c9b04
MG		 15617
15618 /* Scan segment to set p_flags attribute if it contains only sections with
15619 SHF_ARM_NOREAD flag. */
15620 for (m = elf_seg_map (abfd); m != NULL; m = m->next)
15621 {
15622 unsigned int j;
15623
15624 if (m->count == 0)
15625 continue;
15626 for (j = 0; j < m->count; j++)
15627 {
15628 if (!(elf_section_flags (m->sections[j]) & SHF_ARM_NOREAD))
15629 break;
15630 }
15631 if (j == m->count)
15632 {
15633 m->p_flags = PF_X;
15634 m->p_flags_valid = 1;
15635 }
15636 }
ba96a88f
NC		 15637}
15638
99e4ae17 15639static enum elf_reloc_type_class
7e612e98
AM		 15640elf32_arm_reloc_type_class (const struct bfd_link_info *info ATTRIBUTE_UNUSED,
15641 const asection *rel_sec ATTRIBUTE_UNUSED,
15642 const Elf_Internal_Rela *rela)
99e4ae17 15643{
f51e552e 15644 switch ((int) ELF32_R_TYPE (rela->r_info))
99e4ae17
AJ		 15645 {
15646 case R_ARM_RELATIVE:
15647 return reloc_class_relative;
15648 case R_ARM_JUMP_SLOT:
15649 return reloc_class_plt;
15650 case R_ARM_COPY:
15651 return reloc_class_copy;
109575d7
JW		 15652 case R_ARM_IRELATIVE:
15653 return reloc_class_ifunc;
99e4ae17
AJ		 15654 default:
15655 return reloc_class_normal;
15656 }
15657}
15658
e489d0ae 15659static void
57e8b36a 15660elf32_arm_final_write_processing (bfd *abfd, bfd_boolean linker ATTRIBUTE_UNUSED)
e16bb312 15661{
5a6c6817 15662 bfd_arm_update_notes (abfd, ARM_NOTE_SECTION);
e16bb312
NC		 15663}
15664
40a18ebd
NC		 15665/* Return TRUE if this is an unwinding table entry. */
15666
15667static bfd_boolean
15668is_arm_elf_unwind_section_name (bfd * abfd ATTRIBUTE_UNUSED, const char * name)
15669{
0112cd26
NC		 15670 return (CONST_STRNEQ (name, ELF_STRING_ARM_unwind)
15671 || CONST_STRNEQ (name, ELF_STRING_ARM_unwind_once));
40a18ebd
NC		 15672}
15673
15674
15675/* Set the type and flags for an ARM section. We do this by
15676 the section name, which is a hack, but ought to work. */
15677
15678static bfd_boolean
15679elf32_arm_fake_sections (bfd * abfd, Elf_Internal_Shdr * hdr, asection * sec)
15680{
15681 const char * name;
15682
15683 name = bfd_get_section_name (abfd, sec);
15684
15685 if (is_arm_elf_unwind_section_name (abfd, name))
15686 {
15687 hdr->sh_type = SHT_ARM_EXIDX;
15688 hdr->sh_flags |= SHF_LINK_ORDER;
15689 }
ac4c9b04
MG		 15690
15691 if (sec->flags & SEC_ELF_NOREAD)
15692 hdr->sh_flags |= SHF_ARM_NOREAD;
15693
40a18ebd
NC		 15694 return TRUE;
15695}
15696
6dc132d9
L		 15697/* Handle an ARM specific section when reading an object file. This is
15698 called when bfd_section_from_shdr finds a section with an unknown
15699 type. */
40a18ebd
NC		 15700
15701static bfd_boolean
15702elf32_arm_section_from_shdr (bfd *abfd,
15703 Elf_Internal_Shdr * hdr,
6dc132d9
L		 15704 const char *name,
15705 int shindex)
40a18ebd
NC		 15706{
15707 /* There ought to be a place to keep ELF backend specific flags, but
15708 at the moment there isn't one. We just keep track of the
15709 sections by their name, instead. Fortunately, the ABI gives
15710 names for all the ARM specific sections, so we will probably get
15711 away with this. */
15712 switch (hdr->sh_type)
15713 {
15714 case SHT_ARM_EXIDX:
0951f019
RE		 15715 case SHT_ARM_PREEMPTMAP:
15716 case SHT_ARM_ATTRIBUTES:
40a18ebd
NC		 15717 break;
15718
15719 default:
15720 return FALSE;
15721 }
15722
6dc132d9 15723 if (! _bfd_elf_make_section_from_shdr (abfd, hdr, name, shindex))
40a18ebd
NC		 15724 return FALSE;
15725
15726 return TRUE;
15727}
e489d0ae 15728
44444f50
NC		 15729static _arm_elf_section_data *
15730get_arm_elf_section_data (asection * sec)
15731{
47b2e99c
JZ		 15732 if (sec && sec->owner && is_arm_elf (sec->owner))
15733 return elf32_arm_section_data (sec);
44444f50
NC		 15734 else
15735 return NULL;
8e3de13a
NC		 15736}
15737
4e617b1e
PB		 15738typedef struct
15739{
57402f1e 15740 void *flaginfo;
4e617b1e 15741 struct bfd_link_info *info;
91a5743d
PB		 15742 asection *sec;
15743 int sec_shndx;
6e0b88f1
AM		 15744 int (*func) (void *, const char *, Elf_Internal_Sym *,
15745 asection *, struct elf_link_hash_entry *);
4e617b1e
PB		 15746} output_arch_syminfo;
15747
15748enum map_symbol_type
15749{
15750 ARM_MAP_ARM,
15751 ARM_MAP_THUMB,
15752 ARM_MAP_DATA
15753};
15754
15755
7413f23f 15756/* Output a single mapping symbol. */
4e617b1e
PB		 15757
15758static bfd_boolean
7413f23f
DJ		 15759elf32_arm_output_map_sym (output_arch_syminfo *osi,
15760 enum map_symbol_type type,
15761 bfd_vma offset)
4e617b1e
PB		 15762{
15763 static const char *names[3] = {"$a", "$t", "$d"};
4e617b1e
PB		 15764 Elf_Internal_Sym sym;
15765
91a5743d
PB		 15766 sym.st_value = osi->sec->output_section->vma
15767 + osi->sec->output_offset
15768 + offset;
4e617b1e
PB		 15769 sym.st_size = 0;
15770 sym.st_other = 0;
15771 sym.st_info = ELF_ST_INFO (STB_LOCAL, STT_NOTYPE);
91a5743d 15772 sym.st_shndx = osi->sec_shndx;
35fc36a8 15773 sym.st_target_internal = 0;
fe33d2fa 15774 elf32_arm_section_map_add (osi->sec, names[type][1], offset);
57402f1e 15775 return osi->func (osi->flaginfo, names[type], &sym, osi->sec, NULL) == 1;
4e617b1e
PB		 15776}
15777
34e77a92
RS		 15778/* Output mapping symbols for the PLT entry described by ROOT_PLT and ARM_PLT.
15779 IS_IPLT_ENTRY_P says whether the PLT is in .iplt rather than .plt. */
4e617b1e
PB		 15780
15781static bfd_boolean
34e77a92
RS		 15782elf32_arm_output_plt_map_1 (output_arch_syminfo *osi,
15783 bfd_boolean is_iplt_entry_p,
15784 union gotplt_union *root_plt,
15785 struct arm_plt_info *arm_plt)
4e617b1e 15786{
4e617b1e 15787 struct elf32_arm_link_hash_table *htab;
34e77a92 15788 bfd_vma addr, plt_header_size;
4e617b1e 15789
34e77a92 15790 if (root_plt->offset == (bfd_vma) -1)
4e617b1e
PB		 15791 return TRUE;
15792
4dfe6ac6
NC		 15793 htab = elf32_arm_hash_table (osi->info);
15794 if (htab == NULL)
15795 return FALSE;
15796
34e77a92
RS		 15797 if (is_iplt_entry_p)
15798 {
15799 osi->sec = htab->root.iplt;
15800 plt_header_size = 0;
15801 }
15802 else
15803 {
15804 osi->sec = htab->root.splt;
15805 plt_header_size = htab->plt_header_size;
15806 }
15807 osi->sec_shndx = (_bfd_elf_section_from_bfd_section
15808 (osi->info->output_bfd, osi->sec->output_section));
15809
15810 addr = root_plt->offset & -2;
4e617b1e
PB		 15811 if (htab->symbian_p)
15812 {
7413f23f 15813 if (!elf32_arm_output_map_sym (osi, ARM_MAP_ARM, addr))
4e617b1e 15814 return FALSE;
7413f23f 15815 if (!elf32_arm_output_map_sym (osi, ARM_MAP_DATA, addr + 4))
4e617b1e
PB		 15816 return FALSE;
15817 }
15818 else if (htab->vxworks_p)
15819 {
7413f23f 15820 if (!elf32_arm_output_map_sym (osi, ARM_MAP_ARM, addr))
4e617b1e 15821 return FALSE;
7413f23f 15822 if (!elf32_arm_output_map_sym (osi, ARM_MAP_DATA, addr + 8))
4e617b1e 15823 return FALSE;
7413f23f 15824 if (!elf32_arm_output_map_sym (osi, ARM_MAP_ARM, addr + 12))
4e617b1e 15825 return FALSE;
7413f23f 15826 if (!elf32_arm_output_map_sym (osi, ARM_MAP_DATA, addr + 20))
4e617b1e
PB		 15827 return FALSE;
15828 }
b38cadfb
NC		 15829 else if (htab->nacl_p)
15830 {
15831 if (!elf32_arm_output_map_sym (osi, ARM_MAP_ARM, addr))
15832 return FALSE;
15833 }
eed94f8f
NC		 15834 else if (using_thumb_only (htab))
15835 {
15836 if (!elf32_arm_output_map_sym (osi, ARM_MAP_THUMB, addr))
15837 return FALSE;
6a631e86 15838 }
4e617b1e
PB		 15839 else
15840 {
34e77a92 15841 bfd_boolean thumb_stub_p;
bd97cb95 15842
34e77a92
RS		 15843 thumb_stub_p = elf32_arm_plt_needs_thumb_stub_p (osi->info, arm_plt);
15844 if (thumb_stub_p)
4e617b1e 15845 {
7413f23f 15846 if (!elf32_arm_output_map_sym (osi, ARM_MAP_THUMB, addr - 4))
4e617b1e
PB		 15847 return FALSE;
15848 }
15849#ifdef FOUR_WORD_PLT
7413f23f 15850 if (!elf32_arm_output_map_sym (osi, ARM_MAP_ARM, addr))
4e617b1e 15851 return FALSE;
7413f23f 15852 if (!elf32_arm_output_map_sym (osi, ARM_MAP_DATA, addr + 12))
4e617b1e
PB		 15853 return FALSE;
15854#else
906e58ca 15855 /* A three-word PLT with no Thumb thunk contains only Arm code,
4e617b1e
PB		 15856 so only need to output a mapping symbol for the first PLT entry and
15857 entries with thumb thunks. */
34e77a92 15858 if (thumb_stub_p || addr == plt_header_size)
4e617b1e 15859 {
7413f23f 15860 if (!elf32_arm_output_map_sym (osi, ARM_MAP_ARM, addr))
4e617b1e
PB		 15861 return FALSE;
15862 }
15863#endif
15864 }
15865
15866 return TRUE;
15867}
15868
34e77a92
RS		 15869/* Output mapping symbols for PLT entries associated with H. */
15870
15871static bfd_boolean
15872elf32_arm_output_plt_map (struct elf_link_hash_entry *h, void *inf)
15873{
15874 output_arch_syminfo *osi = (output_arch_syminfo *) inf;
15875 struct elf32_arm_link_hash_entry *eh;
15876
15877 if (h->root.type == bfd_link_hash_indirect)
15878 return TRUE;
15879
15880 if (h->root.type == bfd_link_hash_warning)
15881 /* When warning symbols are created, they **replace** the "real"
15882 entry in the hash table, thus we never get to see the real
15883 symbol in a hash traversal. So look at it now. */
15884 h = (struct elf_link_hash_entry *) h->root.u.i.link;
15885
15886 eh = (struct elf32_arm_link_hash_entry *) h;
15887 return elf32_arm_output_plt_map_1 (osi, SYMBOL_CALLS_LOCAL (osi->info, h),
15888 &h->plt, &eh->plt);
15889}
15890
4f4faa4d
TP		 15891/* Bind a veneered symbol to its veneer identified by its hash entry
15892 STUB_ENTRY. The veneered location thus loose its symbol. */
15893
15894static void
15895arm_stub_claim_sym (struct elf32_arm_stub_hash_entry *stub_entry)
15896{
15897 struct elf32_arm_link_hash_entry *hash = stub_entry->h;
15898
15899 BFD_ASSERT (hash);
15900 hash->root.root.u.def.section = stub_entry->stub_sec;
15901 hash->root.root.u.def.value = stub_entry->stub_offset;
15902 hash->root.size = stub_entry->stub_size;
15903}
15904
7413f23f
DJ		 15905/* Output a single local symbol for a generated stub. */
15906
15907static bfd_boolean
15908elf32_arm_output_stub_sym (output_arch_syminfo *osi, const char *name,
15909 bfd_vma offset, bfd_vma size)
15910{
7413f23f
DJ		 15911 Elf_Internal_Sym sym;
15912
7413f23f
DJ		 15913 sym.st_value = osi->sec->output_section->vma
15914 + osi->sec->output_offset
15915 + offset;
15916 sym.st_size = size;
15917 sym.st_other = 0;
15918 sym.st_info = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
15919 sym.st_shndx = osi->sec_shndx;
35fc36a8 15920 sym.st_target_internal = 0;
57402f1e 15921 return osi->func (osi->flaginfo, name, &sym, osi->sec, NULL) == 1;
7413f23f 15922}
4e617b1e 15923
da5938a2 15924static bfd_boolean
8029a119
NC		 15925arm_map_one_stub (struct bfd_hash_entry * gen_entry,
15926 void * in_arg)
da5938a2
NC		 15927{
15928 struct elf32_arm_stub_hash_entry *stub_entry;
da5938a2
NC		 15929 asection *stub_sec;
15930 bfd_vma addr;
7413f23f 15931 char *stub_name;
9a008db3 15932 output_arch_syminfo *osi;
d3ce72d0 15933 const insn_sequence *template_sequence;
461a49ca
DJ		 15934 enum stub_insn_type prev_type;
15935 int size;
15936 int i;
15937 enum map_symbol_type sym_type;
da5938a2
NC		 15938
15939 /* Massage our args to the form they really have. */
15940 stub_entry = (struct elf32_arm_stub_hash_entry *) gen_entry;
9a008db3 15941 osi = (output_arch_syminfo *) in_arg;
da5938a2 15942
da5938a2
NC		 15943 stub_sec = stub_entry->stub_sec;
15944
15945 /* Ensure this stub is attached to the current section being
7413f23f 15946 processed. */
da5938a2
NC		 15947 if (stub_sec != osi->sec)
15948 return TRUE;
15949
7413f23f 15950 addr = (bfd_vma) stub_entry->stub_offset;
d3ce72d0 15951 template_sequence = stub_entry->stub_template;
4f4faa4d
TP		 15952
15953 if (arm_stub_sym_claimed (stub_entry->stub_type))
15954 arm_stub_claim_sym (stub_entry);
15955 else
7413f23f 15956 {
4f4faa4d
TP		 15957 stub_name = stub_entry->output_name;
15958 switch (template_sequence[0].type)
15959 {
15960 case ARM_TYPE:
15961 if (!elf32_arm_output_stub_sym (osi, stub_name, addr,
15962 stub_entry->stub_size))
15963 return FALSE;
15964 break;
15965 case THUMB16_TYPE:
15966 case THUMB32_TYPE:
15967 if (!elf32_arm_output_stub_sym (osi, stub_name, addr | 1,
15968 stub_entry->stub_size))
15969 return FALSE;
15970 break;
15971 default:
15972 BFD_FAIL ();
15973 return 0;
15974 }
7413f23f 15975 }
da5938a2 15976
461a49ca
DJ		 15977 prev_type = DATA_TYPE;
15978 size = 0;
15979 for (i = 0; i < stub_entry->stub_template_size; i++)
15980 {
d3ce72d0 15981 switch (template_sequence[i].type)
461a49ca
DJ		 15982 {
15983 case ARM_TYPE:
15984 sym_type = ARM_MAP_ARM;
15985 break;
15986
15987 case THUMB16_TYPE:
48229727 15988 case THUMB32_TYPE:
461a49ca
DJ		 15989 sym_type = ARM_MAP_THUMB;
15990 break;
15991
15992 case DATA_TYPE:
15993 sym_type = ARM_MAP_DATA;
15994 break;
15995
15996 default:
15997 BFD_FAIL ();
4e31c731 15998 return FALSE;
461a49ca
DJ		 15999 }
16000
d3ce72d0 16001 if (template_sequence[i].type != prev_type)
461a49ca 16002 {
d3ce72d0 16003 prev_type = template_sequence[i].type;
461a49ca
DJ		 16004 if (!elf32_arm_output_map_sym (osi, sym_type, addr + size))
16005 return FALSE;
16006 }
16007
d3ce72d0 16008 switch (template_sequence[i].type)
461a49ca
DJ		 16009 {
16010 case ARM_TYPE:
48229727 16011 case THUMB32_TYPE:
461a49ca
DJ		 16012 size += 4;
16013 break;
16014
16015 case THUMB16_TYPE:
16016 size += 2;
16017 break;
16018
16019 case DATA_TYPE:
16020 size += 4;
16021 break;
16022
16023 default:
16024 BFD_FAIL ();
4e31c731 16025 return FALSE;
461a49ca
DJ		 16026 }
16027 }
16028
da5938a2
NC		 16029 return TRUE;
16030}
16031
33811162
DG		 16032/* Output mapping symbols for linker generated sections,
16033 and for those data-only sections that do not have a
16034 $d. */
4e617b1e
PB		 16035
16036static bfd_boolean
16037elf32_arm_output_arch_local_syms (bfd *output_bfd,
906e58ca 16038 struct bfd_link_info *info,
57402f1e 16039 void *flaginfo,
6e0b88f1
AM		 16040 int (*func) (void *, const char *,
16041 Elf_Internal_Sym *,
16042 asection *,
16043 struct elf_link_hash_entry *))
4e617b1e
PB		 16044{
16045 output_arch_syminfo osi;
16046 struct elf32_arm_link_hash_table *htab;
91a5743d
PB		 16047 bfd_vma offset;
16048 bfd_size_type size;
33811162 16049 bfd *input_bfd;
4e617b1e
PB		 16050
16051 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 16052 if (htab == NULL)
16053 return FALSE;
16054
906e58ca 16055 check_use_blx (htab);
91a5743d 16056
57402f1e 16057 osi.flaginfo = flaginfo;
4e617b1e
PB		 16058 osi.info = info;
16059 osi.func = func;
906e58ca 16060
33811162
DG		 16061 /* Add a $d mapping symbol to data-only sections that
16062 don't have any mapping symbol. This may result in (harmless) redundant
16063 mapping symbols. */
16064 for (input_bfd = info->input_bfds;
16065 input_bfd != NULL;
c72f2fb2 16066 input_bfd = input_bfd->link.next)
33811162
DG		 16067 {
16068 if ((input_bfd->flags & (BFD_LINKER_CREATED | HAS_SYMS)) == HAS_SYMS)
16069 for (osi.sec = input_bfd->sections;
16070 osi.sec != NULL;
16071 osi.sec = osi.sec->next)
16072 {
16073 if (osi.sec->output_section != NULL
f7dd8c79
DJ		 16074 && ((osi.sec->output_section->flags & (SEC_ALLOC | SEC_CODE))
16075 != 0)
33811162
DG		 16076 && (osi.sec->flags & (SEC_HAS_CONTENTS | SEC_LINKER_CREATED))
16077 == SEC_HAS_CONTENTS
16078 && get_arm_elf_section_data (osi.sec) != NULL
501abfe0 16079 && get_arm_elf_section_data (osi.sec)->mapcount == 0
7d500b83
CL		 16080 && osi.sec->size > 0
16081 && (osi.sec->flags & SEC_EXCLUDE) == 0)
33811162
DG		 16082 {
16083 osi.sec_shndx = _bfd_elf_section_from_bfd_section
16084 (output_bfd, osi.sec->output_section);
16085 if (osi.sec_shndx != (int)SHN_BAD)
16086 elf32_arm_output_map_sym (&osi, ARM_MAP_DATA, 0);
16087 }
16088 }
16089 }
16090
91a5743d
PB		 16091 /* ARM->Thumb glue. */
16092 if (htab->arm_glue_size > 0)
16093 {
3d4d4302
AM		 16094 osi.sec = bfd_get_linker_section (htab->bfd_of_glue_owner,
16095 ARM2THUMB_GLUE_SECTION_NAME);
91a5743d
PB		 16096
16097 osi.sec_shndx = _bfd_elf_section_from_bfd_section
16098 (output_bfd, osi.sec->output_section);
0e1862bb 16099 if (bfd_link_pic (info) || htab->root.is_relocatable_executable
91a5743d
PB		 16100 || htab->pic_veneer)
16101 size = ARM2THUMB_PIC_GLUE_SIZE;
16102 else if (htab->use_blx)
16103 size = ARM2THUMB_V5_STATIC_GLUE_SIZE;
16104 else
16105 size = ARM2THUMB_STATIC_GLUE_SIZE;
4e617b1e 16106
91a5743d
PB		 16107 for (offset = 0; offset < htab->arm_glue_size; offset += size)
16108 {
7413f23f
DJ		 16109 elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, offset);
16110 elf32_arm_output_map_sym (&osi, ARM_MAP_DATA, offset + size - 4);
91a5743d
PB		 16111 }
16112 }
16113
16114 /* Thumb->ARM glue. */
16115 if (htab->thumb_glue_size > 0)
16116 {
3d4d4302
AM		 16117 osi.sec = bfd_get_linker_section (htab->bfd_of_glue_owner,
16118 THUMB2ARM_GLUE_SECTION_NAME);
91a5743d
PB		 16119
16120 osi.sec_shndx = _bfd_elf_section_from_bfd_section
16121 (output_bfd, osi.sec->output_section);
16122 size = THUMB2ARM_GLUE_SIZE;
16123
16124 for (offset = 0; offset < htab->thumb_glue_size; offset += size)
16125 {
7413f23f
DJ		 16126 elf32_arm_output_map_sym (&osi, ARM_MAP_THUMB, offset);
16127 elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, offset + 4);
91a5743d
PB		 16128 }
16129 }
16130
845b51d6
PB		 16131 /* ARMv4 BX veneers. */
16132 if (htab->bx_glue_size > 0)
16133 {
3d4d4302
AM		 16134 osi.sec = bfd_get_linker_section (htab->bfd_of_glue_owner,
16135 ARM_BX_GLUE_SECTION_NAME);
845b51d6
PB		 16136
16137 osi.sec_shndx = _bfd_elf_section_from_bfd_section
16138 (output_bfd, osi.sec->output_section);
16139
7413f23f 16140 elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, 0);
845b51d6
PB		 16141 }
16142
8029a119
NC		 16143 /* Long calls stubs. */
16144 if (htab->stub_bfd && htab->stub_bfd->sections)
16145 {
da5938a2 16146 asection* stub_sec;
8029a119 16147
da5938a2
NC		 16148 for (stub_sec = htab->stub_bfd->sections;
16149 stub_sec != NULL;
8029a119
NC		 16150 stub_sec = stub_sec->next)
16151 {
16152 /* Ignore non-stub sections. */
16153 if (!strstr (stub_sec->name, STUB_SUFFIX))
16154 continue;
da5938a2 16155
8029a119 16156 osi.sec = stub_sec;
da5938a2 16157
8029a119
NC		 16158 osi.sec_shndx = _bfd_elf_section_from_bfd_section
16159 (output_bfd, osi.sec->output_section);
da5938a2 16160
8029a119
NC		 16161 bfd_hash_traverse (&htab->stub_hash_table, arm_map_one_stub, &osi);
16162 }
16163 }
da5938a2 16164
91a5743d 16165 /* Finally, output mapping symbols for the PLT. */
34e77a92 16166 if (htab->root.splt && htab->root.splt->size > 0)
4e617b1e 16167 {
34e77a92
RS		 16168 osi.sec = htab->root.splt;
16169 osi.sec_shndx = (_bfd_elf_section_from_bfd_section
16170 (output_bfd, osi.sec->output_section));
16171
16172 /* Output mapping symbols for the plt header. SymbianOS does not have a
16173 plt header. */
16174 if (htab->vxworks_p)
16175 {
16176 /* VxWorks shared libraries have no PLT header. */
0e1862bb 16177 if (!bfd_link_pic (info))
34e77a92
RS		 16178 {
16179 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, 0))
16180 return FALSE;
16181 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_DATA, 12))
16182 return FALSE;
16183 }
16184 }
b38cadfb
NC		 16185 else if (htab->nacl_p)
16186 {
16187 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, 0))
16188 return FALSE;
16189 }
eed94f8f
NC		 16190 else if (using_thumb_only (htab))
16191 {
16192 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_THUMB, 0))
16193 return FALSE;
16194 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_DATA, 12))
16195 return FALSE;
16196 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_THUMB, 16))
16197 return FALSE;
16198 }
34e77a92 16199 else if (!htab->symbian_p)
4e617b1e 16200 {
7413f23f 16201 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, 0))
4e617b1e 16202 return FALSE;
34e77a92
RS		 16203#ifndef FOUR_WORD_PLT
16204 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_DATA, 16))
4e617b1e 16205 return FALSE;
34e77a92 16206#endif
4e617b1e
PB		 16207 }
16208 }
99059e56
RM		 16209 if (htab->nacl_p && htab->root.iplt && htab->root.iplt->size > 0)
16210 {
16211 /* NaCl uses a special first entry in .iplt too. */
16212 osi.sec = htab->root.iplt;
16213 osi.sec_shndx = (_bfd_elf_section_from_bfd_section
16214 (output_bfd, osi.sec->output_section));
16215 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, 0))
16216 return FALSE;
16217 }
34e77a92
RS		 16218 if ((htab->root.splt && htab->root.splt->size > 0)
16219 || (htab->root.iplt && htab->root.iplt->size > 0))
4e617b1e 16220 {
34e77a92
RS		 16221 elf_link_hash_traverse (&htab->root, elf32_arm_output_plt_map, &osi);
16222 for (input_bfd = info->input_bfds;
16223 input_bfd != NULL;
c72f2fb2 16224 input_bfd = input_bfd->link.next)
34e77a92
RS		 16225 {
16226 struct arm_local_iplt_info **local_iplt;
16227 unsigned int i, num_syms;
4e617b1e 16228
34e77a92
RS		 16229 local_iplt = elf32_arm_local_iplt (input_bfd);
16230 if (local_iplt != NULL)
16231 {
16232 num_syms = elf_symtab_hdr (input_bfd).sh_info;
16233 for (i = 0; i < num_syms; i++)
16234 if (local_iplt[i] != NULL
16235 && !elf32_arm_output_plt_map_1 (&osi, TRUE,
16236 &local_iplt[i]->root,
16237 &local_iplt[i]->arm))
16238 return FALSE;
16239 }
16240 }
16241 }
0855e32b
NS		 16242 if (htab->dt_tlsdesc_plt != 0)
16243 {
16244 /* Mapping symbols for the lazy tls trampoline. */
16245 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, htab->dt_tlsdesc_plt))
16246 return FALSE;
b38cadfb 16247
0855e32b
NS		 16248 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_DATA,
16249 htab->dt_tlsdesc_plt + 24))
16250 return FALSE;
16251 }
16252 if (htab->tls_trampoline != 0)
16253 {
16254 /* Mapping symbols for the tls trampoline. */
16255 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, htab->tls_trampoline))
16256 return FALSE;
16257#ifdef FOUR_WORD_PLT
16258 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_DATA,
16259 htab->tls_trampoline + 12))
16260 return FALSE;
b38cadfb 16261#endif
0855e32b 16262 }
b38cadfb 16263
4e617b1e
PB		 16264 return TRUE;
16265}
16266
e489d0ae
PB		 16267/* Allocate target specific section data. */
16268
16269static bfd_boolean
16270elf32_arm_new_section_hook (bfd *abfd, asection *sec)
16271{
f592407e
AM		 16272 if (!sec->used_by_bfd)
16273 {
16274 _arm_elf_section_data *sdata;
16275 bfd_size_type amt = sizeof (*sdata);
e489d0ae 16276
21d799b5 16277 sdata = (_arm_elf_section_data *) bfd_zalloc (abfd, amt);
f592407e
AM		 16278 if (sdata == NULL)
16279 return FALSE;
16280 sec->used_by_bfd = sdata;
16281 }
e489d0ae
PB		 16282
16283 return _bfd_elf_new_section_hook (abfd, sec);
16284}
16285
16286
16287/* Used to order a list of mapping symbols by address. */
16288
16289static int
16290elf32_arm_compare_mapping (const void * a, const void * b)
16291{
7f6a71ff
JM		 16292 const elf32_arm_section_map *amap = (const elf32_arm_section_map *) a;
16293 const elf32_arm_section_map *bmap = (const elf32_arm_section_map *) b;
16294
16295 if (amap->vma > bmap->vma)
16296 return 1;
16297 else if (amap->vma < bmap->vma)
16298 return -1;
16299 else if (amap->type > bmap->type)
16300 /* Ensure results do not depend on the host qsort for objects with
16301 multiple mapping symbols at the same address by sorting on type
16302 after vma. */
16303 return 1;
16304 else if (amap->type < bmap->type)
16305 return -1;
16306 else
16307 return 0;
e489d0ae
PB		 16308}
16309
2468f9c9
PB		 16310/* Add OFFSET to lower 31 bits of ADDR, leaving other bits unmodified. */
16311
16312static unsigned long
16313offset_prel31 (unsigned long addr, bfd_vma offset)
16314{
16315 return (addr & ~0x7ffffffful) | ((addr + offset) & 0x7ffffffful);
16316}
16317
16318/* Copy an .ARM.exidx table entry, adding OFFSET to (applied) PREL31
16319 relocations. */
16320
16321static void
16322copy_exidx_entry (bfd *output_bfd, bfd_byte *to, bfd_byte *from, bfd_vma offset)
16323{
16324 unsigned long first_word = bfd_get_32 (output_bfd, from);
16325 unsigned long second_word = bfd_get_32 (output_bfd, from + 4);
b38cadfb 16326
2468f9c9
PB		 16327 /* High bit of first word is supposed to be zero. */
16328 if ((first_word & 0x80000000ul) == 0)
16329 first_word = offset_prel31 (first_word, offset);
b38cadfb 16330
2468f9c9
PB		 16331 /* If the high bit of the first word is clear, and the bit pattern is not 0x1
16332 (EXIDX_CANTUNWIND), this is an offset to an .ARM.extab entry. */
16333 if ((second_word != 0x1) && ((second_word & 0x80000000ul) == 0))
16334 second_word = offset_prel31 (second_word, offset);
b38cadfb 16335
2468f9c9
PB		 16336 bfd_put_32 (output_bfd, first_word, to);
16337 bfd_put_32 (output_bfd, second_word, to + 4);
16338}
e489d0ae 16339
48229727
JB		 16340/* Data for make_branch_to_a8_stub(). */
16341
b38cadfb
NC		 16342struct a8_branch_to_stub_data
16343{
48229727
JB		 16344 asection *writing_section;
16345 bfd_byte *contents;
16346};
16347
16348
16349/* Helper to insert branches to Cortex-A8 erratum stubs in the right
16350 places for a particular section. */
16351
16352static bfd_boolean
16353make_branch_to_a8_stub (struct bfd_hash_entry *gen_entry,
99059e56 16354 void *in_arg)
48229727
JB		 16355{
16356 struct elf32_arm_stub_hash_entry *stub_entry;
16357 struct a8_branch_to_stub_data *data;
16358 bfd_byte *contents;
16359 unsigned long branch_insn;
16360 bfd_vma veneered_insn_loc, veneer_entry_loc;
16361 bfd_signed_vma branch_offset;
16362 bfd *abfd;
8d9d9490 16363 unsigned int loc;
48229727
JB		 16364
16365 stub_entry = (struct elf32_arm_stub_hash_entry *) gen_entry;
16366 data = (struct a8_branch_to_stub_data *) in_arg;
16367
16368 if (stub_entry->target_section != data->writing_section
4563a860 16369 || stub_entry->stub_type < arm_stub_a8_veneer_lwm)
48229727
JB		 16370 return TRUE;
16371
16372 contents = data->contents;
16373
8d9d9490
TP		 16374 /* We use target_section as Cortex-A8 erratum workaround stubs are only
16375 generated when both source and target are in the same section. */
48229727
JB		 16376 veneered_insn_loc = stub_entry->target_section->output_section->vma
16377 + stub_entry->target_section->output_offset
8d9d9490 16378 + stub_entry->source_value;
48229727
JB		 16379
16380 veneer_entry_loc = stub_entry->stub_sec->output_section->vma
16381 + stub_entry->stub_sec->output_offset
16382 + stub_entry->stub_offset;
16383
16384 if (stub_entry->stub_type == arm_stub_a8_veneer_blx)
16385 veneered_insn_loc &= ~3u;
16386
16387 branch_offset = veneer_entry_loc - veneered_insn_loc - 4;
16388
16389 abfd = stub_entry->target_section->owner;
8d9d9490 16390 loc = stub_entry->source_value;
48229727
JB		 16391
16392 /* We attempt to avoid this condition by setting stubs_always_after_branch
16393 in elf32_arm_size_stubs if we've enabled the Cortex-A8 erratum workaround.
16394 This check is just to be on the safe side... */
16395 if ((veneered_insn_loc & ~0xfff) == (veneer_entry_loc & ~0xfff))
16396 {
16397 (*_bfd_error_handler) (_("%B: error: Cortex-A8 erratum stub is "
16398 "allocated in unsafe location"), abfd);
16399 return FALSE;
16400 }
16401
16402 switch (stub_entry->stub_type)
16403 {
16404 case arm_stub_a8_veneer_b:
16405 case arm_stub_a8_veneer_b_cond:
16406 branch_insn = 0xf0009000;
16407 goto jump24;
16408
16409 case arm_stub_a8_veneer_blx:
16410 branch_insn = 0xf000e800;
16411 goto jump24;
16412
16413 case arm_stub_a8_veneer_bl:
16414 {
16415 unsigned int i1, j1, i2, j2, s;
16416
16417 branch_insn = 0xf000d000;
16418
16419 jump24:
16420 if (branch_offset < -16777216 || branch_offset > 16777214)
16421 {
16422 /* There's not much we can do apart from complain if this
16423 happens. */
16424 (*_bfd_error_handler) (_("%B: error: Cortex-A8 erratum stub out "
16425 "of range (input file too large)"), abfd);
16426 return FALSE;
16427 }
16428
16429 /* i1 = not(j1 eor s), so:
16430 not i1 = j1 eor s
16431 j1 = (not i1) eor s. */
16432
16433 branch_insn |= (branch_offset >> 1) & 0x7ff;
16434 branch_insn |= ((branch_offset >> 12) & 0x3ff) << 16;
16435 i2 = (branch_offset >> 22) & 1;
16436 i1 = (branch_offset >> 23) & 1;
16437 s = (branch_offset >> 24) & 1;
16438 j1 = (!i1) ^ s;
16439 j2 = (!i2) ^ s;
16440 branch_insn |= j2 << 11;
16441 branch_insn |= j1 << 13;
16442 branch_insn |= s << 26;
16443 }
16444 break;
16445
16446 default:
16447 BFD_FAIL ();
16448 return FALSE;
16449 }
16450
8d9d9490
TP		 16451 bfd_put_16 (abfd, (branch_insn >> 16) & 0xffff, &contents[loc]);
16452 bfd_put_16 (abfd, branch_insn & 0xffff, &contents[loc + 2]);
48229727
JB		 16453
16454 return TRUE;
16455}
16456
a504d23a
LA		 16457/* Beginning of stm32l4xx work-around. */
16458
16459/* Functions encoding instructions necessary for the emission of the
16460 fix-stm32l4xx-629360.
16461 Encoding is extracted from the
16462 ARM (C) Architecture Reference Manual
16463 ARMv7-A and ARMv7-R edition
16464 ARM DDI 0406C.b (ID072512). */
16465
16466static inline bfd_vma
82188b29 16467create_instruction_branch_absolute (int branch_offset)
a504d23a
LA		 16468{
16469 /* A8.8.18 B (A8-334)
16470 B target_address (Encoding T4). */
16471 /* 1111 - 0Sii - iiii - iiii - 10J1 - Jiii - iiii - iiii. */
16472 /* jump offset is: S:I1:I2:imm10:imm11:0. */
16473 /* with : I1 = NOT (J1 EOR S) I2 = NOT (J2 EOR S). */
16474
a504d23a
LA		 16475 int s = ((branch_offset & 0x1000000) >> 24);
16476 int j1 = s ^ !((branch_offset & 0x800000) >> 23);
16477 int j2 = s ^ !((branch_offset & 0x400000) >> 22);
16478
16479 if (branch_offset < -(1 << 24) || branch_offset >= (1 << 24))
16480 BFD_ASSERT (0 && "Error: branch out of range. Cannot create branch.");
16481
16482 bfd_vma patched_inst = 0xf0009000
16483 | s << 26 /* S. */
16484 | (((unsigned long) (branch_offset) >> 12) & 0x3ff) << 16 /* imm10. */
16485 | j1 << 13 /* J1. */
16486 | j2 << 11 /* J2. */
16487 | (((unsigned long) (branch_offset) >> 1) & 0x7ff); /* imm11. */
16488
16489 return patched_inst;
16490}
16491
16492static inline bfd_vma
16493create_instruction_ldmia (int base_reg, int wback, int reg_mask)
16494{
16495 /* A8.8.57 LDM/LDMIA/LDMFD (A8-396)
16496 LDMIA Rn!, {Ra, Rb, Rc, ...} (Encoding T2). */
16497 bfd_vma patched_inst = 0xe8900000
16498 | (/*W=*/wback << 21)
16499 | (base_reg << 16)
16500 | (reg_mask & 0x0000ffff);
16501
16502 return patched_inst;
16503}
16504
16505static inline bfd_vma
16506create_instruction_ldmdb (int base_reg, int wback, int reg_mask)
16507{
16508 /* A8.8.60 LDMDB/LDMEA (A8-402)
16509 LDMDB Rn!, {Ra, Rb, Rc, ...} (Encoding T1). */
16510 bfd_vma patched_inst = 0xe9100000
16511 | (/*W=*/wback << 21)
16512 | (base_reg << 16)
16513 | (reg_mask & 0x0000ffff);
16514
16515 return patched_inst;
16516}
16517
16518static inline bfd_vma
16519create_instruction_mov (int target_reg, int source_reg)
16520{
16521 /* A8.8.103 MOV (register) (A8-486)
16522 MOV Rd, Rm (Encoding T1). */
16523 bfd_vma patched_inst = 0x4600
16524 | (target_reg & 0x7)
16525 | ((target_reg & 0x8) >> 3) << 7
16526 | (source_reg << 3);
16527
16528 return patched_inst;
16529}
16530
16531static inline bfd_vma
16532create_instruction_sub (int target_reg, int source_reg, int value)
16533{
16534 /* A8.8.221 SUB (immediate) (A8-708)
16535 SUB Rd, Rn, #value (Encoding T3). */
16536 bfd_vma patched_inst = 0xf1a00000
16537 | (target_reg << 8)
16538 | (source_reg << 16)
16539 | (/*S=*/0 << 20)
16540 | ((value & 0x800) >> 11) << 26
16541 | ((value & 0x700) >> 8) << 12
16542 | (value & 0x0ff);
16543
16544 return patched_inst;
16545}
16546
16547static inline bfd_vma
9239bbd3 16548create_instruction_vldmia (int base_reg, int is_dp, int wback, int num_words,
a504d23a
LA		 16549 int first_reg)
16550{
16551 /* A8.8.332 VLDM (A8-922)
9239bbd3
CM		 16552 VLMD{MODE} Rn{!}, {list} (Encoding T1 or T2). */
16553 bfd_vma patched_inst = (is_dp ? 0xec900b00 : 0xec900a00)
a504d23a
LA		 16554 | (/*W=*/wback << 21)
16555 | (base_reg << 16)
9239bbd3
CM		 16556 | (num_words & 0x000000ff)
16557 | (((unsigned)first_reg >> 1) & 0x0000000f) << 12
a504d23a
LA		 16558 | (first_reg & 0x00000001) << 22;
16559
16560 return patched_inst;
16561}
16562
16563static inline bfd_vma
9239bbd3
CM		 16564create_instruction_vldmdb (int base_reg, int is_dp, int num_words,
16565 int first_reg)
a504d23a
LA		 16566{
16567 /* A8.8.332 VLDM (A8-922)
9239bbd3
CM		 16568 VLMD{MODE} Rn!, {} (Encoding T1 or T2). */
16569 bfd_vma patched_inst = (is_dp ? 0xed300b00 : 0xed300a00)
a504d23a 16570 | (base_reg << 16)
9239bbd3
CM		 16571 | (num_words & 0x000000ff)
16572 | (((unsigned)first_reg >>1 ) & 0x0000000f) << 12
a504d23a
LA		 16573 | (first_reg & 0x00000001) << 22;
16574
16575 return patched_inst;
16576}
16577
16578static inline bfd_vma
16579create_instruction_udf_w (int value)
16580{
16581 /* A8.8.247 UDF (A8-758)
16582 Undefined (Encoding T2). */
16583 bfd_vma patched_inst = 0xf7f0a000
16584 | (value & 0x00000fff)
16585 | (value & 0x000f0000) << 16;
16586
16587 return patched_inst;
16588}
16589
16590static inline bfd_vma
16591create_instruction_udf (int value)
16592{
16593 /* A8.8.247 UDF (A8-758)
16594 Undefined (Encoding T1). */
16595 bfd_vma patched_inst = 0xde00
16596 | (value & 0xff);
16597
16598 return patched_inst;
16599}
16600
16601/* Functions writing an instruction in memory, returning the next
16602 memory position to write to. */
16603
16604static inline bfd_byte *
16605push_thumb2_insn32 (struct elf32_arm_link_hash_table * htab,
16606 bfd * output_bfd, bfd_byte *pt, insn32 insn)
16607{
16608 put_thumb2_insn (htab, output_bfd, insn, pt);
16609 return pt + 4;
16610}
16611
16612static inline bfd_byte *
16613push_thumb2_insn16 (struct elf32_arm_link_hash_table * htab,
16614 bfd * output_bfd, bfd_byte *pt, insn32 insn)
16615{
16616 put_thumb_insn (htab, output_bfd, insn, pt);
16617 return pt + 2;
16618}
16619
16620/* Function filling up a region in memory with T1 and T2 UDFs taking
16621 care of alignment. */
16622
16623static bfd_byte *
16624stm32l4xx_fill_stub_udf (struct elf32_arm_link_hash_table * htab,
16625 bfd * output_bfd,
16626 const bfd_byte * const base_stub_contents,
16627 bfd_byte * const from_stub_contents,
16628 const bfd_byte * const end_stub_contents)
16629{
16630 bfd_byte *current_stub_contents = from_stub_contents;
16631
16632 /* Fill the remaining of the stub with deterministic contents : UDF
16633 instructions.
16634 Check if realignment is needed on modulo 4 frontier using T1, to
16635 further use T2. */
16636 if ((current_stub_contents < end_stub_contents)
16637 && !((current_stub_contents - base_stub_contents) % 2)
16638 && ((current_stub_contents - base_stub_contents) % 4))
16639 current_stub_contents =
16640 push_thumb2_insn16 (htab, output_bfd, current_stub_contents,
16641 create_instruction_udf (0));
16642
16643 for (; current_stub_contents < end_stub_contents;)
16644 current_stub_contents =
16645 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
16646 create_instruction_udf_w (0));
16647
16648 return current_stub_contents;
16649}
16650
16651/* Functions writing the stream of instructions equivalent to the
16652 derived sequence for ldmia, ldmdb, vldm respectively. */
16653
16654static void
16655stm32l4xx_create_replacing_stub_ldmia (struct elf32_arm_link_hash_table * htab,
16656 bfd * output_bfd,
16657 const insn32 initial_insn,
16658 const bfd_byte *const initial_insn_addr,
16659 bfd_byte *const base_stub_contents)
16660{
16661 int wback = (initial_insn & 0x00200000) >> 21;
16662 int ri, rn = (initial_insn & 0x000F0000) >> 16;
16663 int insn_all_registers = initial_insn & 0x0000ffff;
16664 int insn_low_registers, insn_high_registers;
16665 int usable_register_mask;
16666 int nb_registers = popcount (insn_all_registers);
16667 int restore_pc = (insn_all_registers & (1 << 15)) ? 1 : 0;
16668 int restore_rn = (insn_all_registers & (1 << rn)) ? 1 : 0;
16669 bfd_byte *current_stub_contents = base_stub_contents;
16670
16671 BFD_ASSERT (is_thumb2_ldmia (initial_insn));
16672
16673 /* In BFD_ARM_STM32L4XX_FIX_ALL mode we may have to deal with
16674 smaller than 8 registers load sequences that do not cause the
16675 hardware issue. */
16676 if (nb_registers <= 8)
16677 {
16678 /* UNTOUCHED : LDMIA Rn{!}, {R-all-register-list}. */
16679 current_stub_contents =
16680 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
16681 initial_insn);
16682
16683 /* B initial_insn_addr+4. */
16684 if (!restore_pc)
16685 current_stub_contents =
16686 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
16687 create_instruction_branch_absolute
82188b29
NC		 16688 (initial_insn_addr - current_stub_contents));
16689
a504d23a
LA		 16690
16691 /* Fill the remaining of the stub with deterministic contents. */
16692 current_stub_contents =
16693 stm32l4xx_fill_stub_udf (htab, output_bfd,
16694 base_stub_contents, current_stub_contents,
16695 base_stub_contents +
16696 STM32L4XX_ERRATUM_LDM_VENEER_SIZE);
16697
16698 return;
16699 }
16700
16701 /* - reg_list[13] == 0. */
16702 BFD_ASSERT ((insn_all_registers & (1 << 13))==0);
16703
16704 /* - reg_list[14] & reg_list[15] != 1. */
16705 BFD_ASSERT ((insn_all_registers & 0xC000) != 0xC000);
16706
16707 /* - if (wback==1) reg_list[rn] == 0. */
16708 BFD_ASSERT (!wback || !restore_rn);
16709
16710 /* - nb_registers > 8. */
16711 BFD_ASSERT (popcount (insn_all_registers) > 8);
16712
16713 /* At this point, LDMxx initial insn loads between 9 and 14 registers. */
16714
16715 /* In the following algorithm, we split this wide LDM using 2 LDM insns:
16716 - One with the 7 lowest registers (register mask 0x007F)
16717 This LDM will finally contain between 2 and 7 registers
16718 - One with the 7 highest registers (register mask 0xDF80)
16719 This ldm will finally contain between 2 and 7 registers. */
16720 insn_low_registers = insn_all_registers & 0x007F;
16721 insn_high_registers = insn_all_registers & 0xDF80;
16722
16723 /* A spare register may be needed during this veneer to temporarily
16724 handle the base register. This register will be restored with the
16725 last LDM operation.
16726 The usable register may be any general purpose register (that
16727 excludes PC, SP, LR : register mask is 0x1FFF). */
16728 usable_register_mask = 0x1FFF;
16729
16730 /* Generate the stub function. */
16731 if (wback)
16732 {
16733 /* LDMIA Rn!, {R-low-register-list} : (Encoding T2). */
16734 current_stub_contents =
16735 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
16736 create_instruction_ldmia
16737 (rn, /*wback=*/1, insn_low_registers));
16738
16739 /* LDMIA Rn!, {R-high-register-list} : (Encoding T2). */
16740 current_stub_contents =
16741 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
16742 create_instruction_ldmia
16743 (rn, /*wback=*/1, insn_high_registers));
16744 if (!restore_pc)
16745 {
16746 /* B initial_insn_addr+4. */
16747 current_stub_contents =
16748 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
16749 create_instruction_branch_absolute
82188b29 16750 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 16751 }
16752 }
16753 else /* if (!wback). */
16754 {
16755 ri = rn;
16756
16757 /* If Rn is not part of the high-register-list, move it there. */
16758 if (!(insn_high_registers & (1 << rn)))
16759 {
16760 /* Choose a Ri in the high-register-list that will be restored. */
16761 ri = ctz (insn_high_registers & usable_register_mask & ~(1 << rn));
16762
16763 /* MOV Ri, Rn. */
16764 current_stub_contents =
16765 push_thumb2_insn16 (htab, output_bfd, current_stub_contents,
16766 create_instruction_mov (ri, rn));
16767 }
16768
16769 /* LDMIA Ri!, {R-low-register-list} : (Encoding T2). */
16770 current_stub_contents =
16771 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
16772 create_instruction_ldmia
16773 (ri, /*wback=*/1, insn_low_registers));
16774
16775 /* LDMIA Ri, {R-high-register-list} : (Encoding T2). */
16776 current_stub_contents =
16777 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
16778 create_instruction_ldmia
16779 (ri, /*wback=*/0, insn_high_registers));
16780
16781 if (!restore_pc)
16782 {
16783 /* B initial_insn_addr+4. */
16784 current_stub_contents =
16785 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
16786 create_instruction_branch_absolute
82188b29 16787 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 16788 }
16789 }
16790
16791 /* Fill the remaining of the stub with deterministic contents. */
16792 current_stub_contents =
16793 stm32l4xx_fill_stub_udf (htab, output_bfd,
16794 base_stub_contents, current_stub_contents,
16795 base_stub_contents +
16796 STM32L4XX_ERRATUM_LDM_VENEER_SIZE);
16797}
16798
16799static void
16800stm32l4xx_create_replacing_stub_ldmdb (struct elf32_arm_link_hash_table * htab,
16801 bfd * output_bfd,
16802 const insn32 initial_insn,
16803 const bfd_byte *const initial_insn_addr,
16804 bfd_byte *const base_stub_contents)
16805{
16806 int wback = (initial_insn & 0x00200000) >> 21;
16807 int ri, rn = (initial_insn & 0x000f0000) >> 16;
16808 int insn_all_registers = initial_insn & 0x0000ffff;
16809 int insn_low_registers, insn_high_registers;
16810 int usable_register_mask;
16811 int restore_pc = (insn_all_registers & (1 << 15)) ? 1 : 0;
16812 int restore_rn = (insn_all_registers & (1 << rn)) ? 1 : 0;
16813 int nb_registers = popcount (insn_all_registers);
16814 bfd_byte *current_stub_contents = base_stub_contents;
16815
16816 BFD_ASSERT (is_thumb2_ldmdb (initial_insn));
16817
16818 /* In BFD_ARM_STM32L4XX_FIX_ALL mode we may have to deal with
16819 smaller than 8 registers load sequences that do not cause the
16820 hardware issue. */
16821 if (nb_registers <= 8)
16822 {
16823 /* UNTOUCHED : LDMIA Rn{!}, {R-all-register-list}. */
16824 current_stub_contents =
16825 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
16826 initial_insn);
16827
16828 /* B initial_insn_addr+4. */
16829 current_stub_contents =
16830 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
16831 create_instruction_branch_absolute
82188b29 16832 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 16833
16834 /* Fill the remaining of the stub with deterministic contents. */
16835 current_stub_contents =
16836 stm32l4xx_fill_stub_udf (htab, output_bfd,
16837 base_stub_contents, current_stub_contents,
16838 base_stub_contents +
16839 STM32L4XX_ERRATUM_LDM_VENEER_SIZE);
16840
16841 return;
16842 }
16843
16844 /* - reg_list[13] == 0. */
16845 BFD_ASSERT ((insn_all_registers & (1 << 13)) == 0);
16846
16847 /* - reg_list[14] & reg_list[15] != 1. */
16848 BFD_ASSERT ((insn_all_registers & 0xC000) != 0xC000);
16849
16850 /* - if (wback==1) reg_list[rn] == 0. */
16851 BFD_ASSERT (!wback || !restore_rn);
16852
16853 /* - nb_registers > 8. */
16854 BFD_ASSERT (popcount (insn_all_registers) > 8);
16855
16856 /* At this point, LDMxx initial insn loads between 9 and 14 registers. */
16857
16858 /* In the following algorithm, we split this wide LDM using 2 LDM insn:
16859 - One with the 7 lowest registers (register mask 0x007F)
16860 This LDM will finally contain between 2 and 7 registers
16861 - One with the 7 highest registers (register mask 0xDF80)
16862 This ldm will finally contain between 2 and 7 registers. */
16863 insn_low_registers = insn_all_registers & 0x007F;
16864 insn_high_registers = insn_all_registers & 0xDF80;
16865
16866 /* A spare register may be needed during this veneer to temporarily
16867 handle the base register. This register will be restored with
16868 the last LDM operation.
16869 The usable register may be any general purpose register (that excludes
16870 PC, SP, LR : register mask is 0x1FFF). */
16871 usable_register_mask = 0x1FFF;
16872
16873 /* Generate the stub function. */
16874 if (!wback && !restore_pc && !restore_rn)
16875 {
16876 /* Choose a Ri in the low-register-list that will be restored. */
16877 ri = ctz (insn_low_registers & usable_register_mask & ~(1 << rn));
16878
16879 /* MOV Ri, Rn. */
16880 current_stub_contents =
16881 push_thumb2_insn16 (htab, output_bfd, current_stub_contents,
16882 create_instruction_mov (ri, rn));
16883
16884 /* LDMDB Ri!, {R-high-register-list}. */
16885 current_stub_contents =
16886 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
16887 create_instruction_ldmdb
16888 (ri, /*wback=*/1, insn_high_registers));
16889
16890 /* LDMDB Ri, {R-low-register-list}. */
16891 current_stub_contents =
16892 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
16893 create_instruction_ldmdb
16894 (ri, /*wback=*/0, insn_low_registers));
16895
16896 /* B initial_insn_addr+4. */
16897 current_stub_contents =
16898 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
16899 create_instruction_branch_absolute
82188b29 16900 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 16901 }
16902 else if (wback && !restore_pc && !restore_rn)
16903 {
16904 /* LDMDB Rn!, {R-high-register-list}. */
16905 current_stub_contents =
16906 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
16907 create_instruction_ldmdb
16908 (rn, /*wback=*/1, insn_high_registers));
16909
16910 /* LDMDB Rn!, {R-low-register-list}. */
16911 current_stub_contents =
16912 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
16913 create_instruction_ldmdb
16914 (rn, /*wback=*/1, insn_low_registers));
16915
16916 /* B initial_insn_addr+4. */
16917 current_stub_contents =
16918 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
16919 create_instruction_branch_absolute
82188b29 16920 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 16921 }
16922 else if (!wback && restore_pc && !restore_rn)
16923 {
16924 /* Choose a Ri in the high-register-list that will be restored. */
16925 ri = ctz (insn_high_registers & usable_register_mask & ~(1 << rn));
16926
16927 /* SUB Ri, Rn, #(4*nb_registers). */
16928 current_stub_contents =
16929 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
16930 create_instruction_sub (ri, rn, (4 * nb_registers)));
16931
16932 /* LDMIA Ri!, {R-low-register-list}. */
16933 current_stub_contents =
16934 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
16935 create_instruction_ldmia
16936 (ri, /*wback=*/1, insn_low_registers));
16937
16938 /* LDMIA Ri, {R-high-register-list}. */
16939 current_stub_contents =
16940 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
16941 create_instruction_ldmia
16942 (ri, /*wback=*/0, insn_high_registers));
16943 }
16944 else if (wback && restore_pc && !restore_rn)
16945 {
16946 /* Choose a Ri in the high-register-list that will be restored. */
16947 ri = ctz (insn_high_registers & usable_register_mask & ~(1 << rn));
16948
16949 /* SUB Rn, Rn, #(4*nb_registers) */
16950 current_stub_contents =
16951 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
16952 create_instruction_sub (rn, rn, (4 * nb_registers)));
16953
16954 /* MOV Ri, Rn. */
16955 current_stub_contents =
16956 push_thumb2_insn16 (htab, output_bfd, current_stub_contents,
16957 create_instruction_mov (ri, rn));
16958
16959 /* LDMIA Ri!, {R-low-register-list}. */
16960 current_stub_contents =
16961 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
16962 create_instruction_ldmia
16963 (ri, /*wback=*/1, insn_low_registers));
16964
16965 /* LDMIA Ri, {R-high-register-list}. */
16966 current_stub_contents =
16967 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
16968 create_instruction_ldmia
16969 (ri, /*wback=*/0, insn_high_registers));
16970 }
16971 else if (!wback && !restore_pc && restore_rn)
16972 {
16973 ri = rn;
16974 if (!(insn_low_registers & (1 << rn)))
16975 {
16976 /* Choose a Ri in the low-register-list that will be restored. */
16977 ri = ctz (insn_low_registers & usable_register_mask & ~(1 << rn));
16978
16979 /* MOV Ri, Rn. */
16980 current_stub_contents =
16981 push_thumb2_insn16 (htab, output_bfd, current_stub_contents,
16982 create_instruction_mov (ri, rn));
16983 }
16984
16985 /* LDMDB Ri!, {R-high-register-list}. */
16986 current_stub_contents =
16987 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
16988 create_instruction_ldmdb
16989 (ri, /*wback=*/1, insn_high_registers));
16990
16991 /* LDMDB Ri, {R-low-register-list}. */
16992 current_stub_contents =
16993 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
16994 create_instruction_ldmdb
16995 (ri, /*wback=*/0, insn_low_registers));
16996
16997 /* B initial_insn_addr+4. */
16998 current_stub_contents =
16999 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
17000 create_instruction_branch_absolute
82188b29 17001 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 17002 }
17003 else if (!wback && restore_pc && restore_rn)
17004 {
17005 ri = rn;
17006 if (!(insn_high_registers & (1 << rn)))
17007 {
17008 /* Choose a Ri in the high-register-list that will be restored. */
17009 ri = ctz (insn_high_registers & usable_register_mask & ~(1 << rn));
17010 }
17011
17012 /* SUB Ri, Rn, #(4*nb_registers). */
17013 current_stub_contents =
17014 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
17015 create_instruction_sub (ri, rn, (4 * nb_registers)));
17016
17017 /* LDMIA Ri!, {R-low-register-list}. */
17018 current_stub_contents =
17019 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
17020 create_instruction_ldmia
17021 (ri, /*wback=*/1, insn_low_registers));
17022
17023 /* LDMIA Ri, {R-high-register-list}. */
17024 current_stub_contents =
17025 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
17026 create_instruction_ldmia
17027 (ri, /*wback=*/0, insn_high_registers));
17028 }
17029 else if (wback && restore_rn)
17030 {
17031 /* The assembler should not have accepted to encode this. */
17032 BFD_ASSERT (0 && "Cannot patch an instruction that has an "
17033 "undefined behavior.\n");
17034 }
17035
17036 /* Fill the remaining of the stub with deterministic contents. */
17037 current_stub_contents =
17038 stm32l4xx_fill_stub_udf (htab, output_bfd,
17039 base_stub_contents, current_stub_contents,
17040 base_stub_contents +
17041 STM32L4XX_ERRATUM_LDM_VENEER_SIZE);
17042
17043}
17044
17045static void
17046stm32l4xx_create_replacing_stub_vldm (struct elf32_arm_link_hash_table * htab,
17047 bfd * output_bfd,
17048 const insn32 initial_insn,
17049 const bfd_byte *const initial_insn_addr,
17050 bfd_byte *const base_stub_contents)
17051{
9239bbd3 17052 int num_words = ((unsigned int) initial_insn << 24) >> 24;
a504d23a
LA		 17053 bfd_byte *current_stub_contents = base_stub_contents;
17054
17055 BFD_ASSERT (is_thumb2_vldm (initial_insn));
17056
17057 /* In BFD_ARM_STM32L4XX_FIX_ALL mode we may have to deal with
9239bbd3 17058 smaller than 8 words load sequences that do not cause the
a504d23a 17059 hardware issue. */
9239bbd3 17060 if (num_words <= 8)
a504d23a
LA		 17061 {
17062 /* Untouched instruction. */
17063 current_stub_contents =
17064 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
17065 initial_insn);
17066
17067 /* B initial_insn_addr+4. */
17068 current_stub_contents =
17069 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
17070 create_instruction_branch_absolute
82188b29 17071 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 17072 }
17073 else
17074 {
9239bbd3
CM		 17075 bfd_boolean is_dp = /* DP encoding. */
17076 (initial_insn & 0xfe100f00) == 0xec100b00;
a504d23a
LA		 17077 bfd_boolean is_ia_nobang = /* (IA without !). */
17078 (((initial_insn << 7) >> 28) & 0xd) == 0x4;
17079 bfd_boolean is_ia_bang = /* (IA with !) - includes VPOP. */
17080 (((initial_insn << 7) >> 28) & 0xd) == 0x5;
17081 bfd_boolean is_db_bang = /* (DB with !). */
17082 (((initial_insn << 7) >> 28) & 0xd) == 0x9;
9239bbd3 17083 int base_reg = ((unsigned int) initial_insn << 12) >> 28;
a504d23a 17084 /* d = UInt (Vd:D);. */
9239bbd3 17085 int first_reg = ((((unsigned int) initial_insn << 16) >> 28) << 1)
a504d23a
LA		 17086 | (((unsigned int)initial_insn << 9) >> 31);
17087
9239bbd3
CM		 17088 /* Compute the number of 8-words chunks needed to split. */
17089 int chunks = (num_words % 8) ? (num_words / 8 + 1) : (num_words / 8);
a504d23a
LA		 17090 int chunk;
17091
17092 /* The test coverage has been done assuming the following
17093 hypothesis that exactly one of the previous is_ predicates is
17094 true. */
9239bbd3
CM		 17095 BFD_ASSERT ( (is_ia_nobang ^ is_ia_bang ^ is_db_bang)
17096 && !(is_ia_nobang & is_ia_bang & is_db_bang));
a504d23a 17097
9239bbd3 17098 /* We treat the cutting of the words in one pass for all
a504d23a
LA		 17099 cases, then we emit the adjustments:
17100
17101 vldm rx, {...}
17102 -> vldm rx!, {8_words_or_less} for each needed 8_word
17103 -> sub rx, rx, #size (list)
17104
17105 vldm rx!, {...}
17106 -> vldm rx!, {8_words_or_less} for each needed 8_word
17107 This also handles vpop instruction (when rx is sp)
17108
17109 vldmd rx!, {...}
17110 -> vldmb rx!, {8_words_or_less} for each needed 8_word. */
9239bbd3 17111 for (chunk = 0; chunk < chunks; ++chunk)
a504d23a 17112 {
9239bbd3
CM		 17113 bfd_vma new_insn = 0;
17114
a504d23a
LA		 17115 if (is_ia_nobang || is_ia_bang)
17116 {
9239bbd3
CM		 17117 new_insn = create_instruction_vldmia
17118 (base_reg,
17119 is_dp,
17120 /*wback= . */1,
17121 chunks - (chunk + 1) ?
17122 8 : num_words - chunk * 8,
17123 first_reg + chunk * 8);
a504d23a
LA		 17124 }
17125 else if (is_db_bang)
17126 {
9239bbd3
CM		 17127 new_insn = create_instruction_vldmdb
17128 (base_reg,
17129 is_dp,
17130 chunks - (chunk + 1) ?
17131 8 : num_words - chunk * 8,
17132 first_reg + chunk * 8);
a504d23a 17133 }
9239bbd3
CM		 17134
17135 if (new_insn)
17136 current_stub_contents =
17137 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
17138 new_insn);
a504d23a
LA		 17139 }
17140
17141 /* Only this case requires the base register compensation
17142 subtract. */
17143 if (is_ia_nobang)
17144 {
17145 current_stub_contents =
17146 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
17147 create_instruction_sub
9239bbd3 17148 (base_reg, base_reg, 4*num_words));
a504d23a
LA		 17149 }
17150
17151 /* B initial_insn_addr+4. */
17152 current_stub_contents =
17153 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
17154 create_instruction_branch_absolute
82188b29 17155 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 17156 }
17157
17158 /* Fill the remaining of the stub with deterministic contents. */
17159 current_stub_contents =
17160 stm32l4xx_fill_stub_udf (htab, output_bfd,
17161 base_stub_contents, current_stub_contents,
17162 base_stub_contents +
17163 STM32L4XX_ERRATUM_VLDM_VENEER_SIZE);
17164}
17165
17166static void
17167stm32l4xx_create_replacing_stub (struct elf32_arm_link_hash_table * htab,
17168 bfd * output_bfd,
17169 const insn32 wrong_insn,
17170 const bfd_byte *const wrong_insn_addr,
17171 bfd_byte *const stub_contents)
17172{
17173 if (is_thumb2_ldmia (wrong_insn))
17174 stm32l4xx_create_replacing_stub_ldmia (htab, output_bfd,
17175 wrong_insn, wrong_insn_addr,
17176 stub_contents);
17177 else if (is_thumb2_ldmdb (wrong_insn))
17178 stm32l4xx_create_replacing_stub_ldmdb (htab, output_bfd,
17179 wrong_insn, wrong_insn_addr,
17180 stub_contents);
17181 else if (is_thumb2_vldm (wrong_insn))
17182 stm32l4xx_create_replacing_stub_vldm (htab, output_bfd,
17183 wrong_insn, wrong_insn_addr,
17184 stub_contents);
17185}
17186
17187/* End of stm32l4xx work-around. */
17188
17189
491d01d3
YU		 17190static void
17191elf32_arm_add_relocation (bfd *output_bfd, struct bfd_link_info *info,
17192 asection *output_sec, Elf_Internal_Rela *rel)
17193{
17194 BFD_ASSERT (output_sec && rel);
17195 struct bfd_elf_section_reloc_data *output_reldata;
17196 struct elf32_arm_link_hash_table *htab;
17197 struct bfd_elf_section_data *oesd = elf_section_data (output_sec);
17198 Elf_Internal_Shdr *rel_hdr;
17199
17200
17201 if (oesd->rel.hdr)
17202 {
17203 rel_hdr = oesd->rel.hdr;
17204 output_reldata = &(oesd->rel);
17205 }
17206 else if (oesd->rela.hdr)
17207 {
17208 rel_hdr = oesd->rela.hdr;
17209 output_reldata = &(oesd->rela);
17210 }
17211 else
17212 {
17213 abort ();
17214 }
17215
17216 bfd_byte *erel = rel_hdr->contents;
17217 erel += output_reldata->count * rel_hdr->sh_entsize;
17218 htab = elf32_arm_hash_table (info);
17219 SWAP_RELOC_OUT (htab) (output_bfd, rel, erel);
17220 output_reldata->count++;
17221}
17222
e489d0ae
PB		 17223/* Do code byteswapping. Return FALSE afterwards so that the section is
17224 written out as normal. */
17225
17226static bfd_boolean
c7b8f16e 17227elf32_arm_write_section (bfd *output_bfd,
8029a119
NC		 17228 struct bfd_link_info *link_info,
17229 asection *sec,
e489d0ae
PB		 17230 bfd_byte *contents)
17231{
48229727 17232 unsigned int mapcount, errcount;
8e3de13a 17233 _arm_elf_section_data *arm_data;
c7b8f16e 17234 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (link_info);
e489d0ae 17235 elf32_arm_section_map *map;
c7b8f16e 17236 elf32_vfp11_erratum_list *errnode;
a504d23a 17237 elf32_stm32l4xx_erratum_list *stm32l4xx_errnode;
e489d0ae
PB		 17238 bfd_vma ptr;
17239 bfd_vma end;
c7b8f16e 17240 bfd_vma offset = sec->output_section->vma + sec->output_offset;
e489d0ae 17241 bfd_byte tmp;
48229727 17242 unsigned int i;
57e8b36a 17243
4dfe6ac6
NC		 17244 if (globals == NULL)
17245 return FALSE;
17246
8e3de13a
NC		 17247 /* If this section has not been allocated an _arm_elf_section_data
17248 structure then we cannot record anything. */
17249 arm_data = get_arm_elf_section_data (sec);
17250 if (arm_data == NULL)
17251 return FALSE;
17252
17253 mapcount = arm_data->mapcount;
17254 map = arm_data->map;
c7b8f16e
JB		 17255 errcount = arm_data->erratumcount;
17256
17257 if (errcount != 0)
17258 {
17259 unsigned int endianflip = bfd_big_endian (output_bfd) ? 3 : 0;
17260
17261 for (errnode = arm_data->erratumlist; errnode != 0;
99059e56
RM		 17262 errnode = errnode->next)
17263 {
17264 bfd_vma target = errnode->vma - offset;
17265
17266 switch (errnode->type)
17267 {
17268 case VFP11_ERRATUM_BRANCH_TO_ARM_VENEER:
17269 {
17270 bfd_vma branch_to_veneer;
17271 /* Original condition code of instruction, plus bit mask for
17272 ARM B instruction. */
17273 unsigned int insn = (errnode->u.b.vfp_insn & 0xf0000000)
17274 | 0x0a000000;
c7b8f16e
JB		 17275
17276 /* The instruction is before the label. */
91d6fa6a 17277 target -= 4;
c7b8f16e
JB		 17278
17279 /* Above offset included in -4 below. */
17280 branch_to_veneer = errnode->u.b.veneer->vma
99059e56 17281 - errnode->vma - 4;
c7b8f16e
JB		 17282
17283 if ((signed) branch_to_veneer < -(1 << 25)
17284 || (signed) branch_to_veneer >= (1 << 25))
17285 (*_bfd_error_handler) (_("%B: error: VFP11 veneer out of "
17286 "range"), output_bfd);
17287
99059e56
RM		 17288 insn |= (branch_to_veneer >> 2) & 0xffffff;
17289 contents[endianflip ^ target] = insn & 0xff;
17290 contents[endianflip ^ (target + 1)] = (insn >> 8) & 0xff;
17291 contents[endianflip ^ (target + 2)] = (insn >> 16) & 0xff;
17292 contents[endianflip ^ (target + 3)] = (insn >> 24) & 0xff;
17293 }
17294 break;
c7b8f16e
JB		 17295
17296 case VFP11_ERRATUM_ARM_VENEER:
99059e56
RM		 17297 {
17298 bfd_vma branch_from_veneer;
17299 unsigned int insn;
c7b8f16e 17300
99059e56
RM		 17301 /* Take size of veneer into account. */
17302 branch_from_veneer = errnode->u.v.branch->vma
17303 - errnode->vma - 12;
c7b8f16e
JB		 17304
17305 if ((signed) branch_from_veneer < -(1 << 25)
17306 || (signed) branch_from_veneer >= (1 << 25))
17307 (*_bfd_error_handler) (_("%B: error: VFP11 veneer out of "
17308 "range"), output_bfd);
17309
99059e56
RM		 17310 /* Original instruction. */
17311 insn = errnode->u.v.branch->u.b.vfp_insn;
17312 contents[endianflip ^ target] = insn & 0xff;
17313 contents[endianflip ^ (target + 1)] = (insn >> 8) & 0xff;
17314 contents[endianflip ^ (target + 2)] = (insn >> 16) & 0xff;
17315 contents[endianflip ^ (target + 3)] = (insn >> 24) & 0xff;
17316
17317 /* Branch back to insn after original insn. */
17318 insn = 0xea000000 | ((branch_from_veneer >> 2) & 0xffffff);
17319 contents[endianflip ^ (target + 4)] = insn & 0xff;
17320 contents[endianflip ^ (target + 5)] = (insn >> 8) & 0xff;
17321 contents[endianflip ^ (target + 6)] = (insn >> 16) & 0xff;
17322 contents[endianflip ^ (target + 7)] = (insn >> 24) & 0xff;
17323 }
17324 break;
c7b8f16e 17325
99059e56
RM		 17326 default:
17327 abort ();
17328 }
17329 }
c7b8f16e 17330 }
e489d0ae 17331
a504d23a
LA		 17332 if (arm_data->stm32l4xx_erratumcount != 0)
17333 {
17334 for (stm32l4xx_errnode = arm_data->stm32l4xx_erratumlist;
17335 stm32l4xx_errnode != 0;
17336 stm32l4xx_errnode = stm32l4xx_errnode->next)
17337 {
17338 bfd_vma target = stm32l4xx_errnode->vma - offset;
17339
17340 switch (stm32l4xx_errnode->type)
17341 {
17342 case STM32L4XX_ERRATUM_BRANCH_TO_VENEER:
17343 {
17344 unsigned int insn;
17345 bfd_vma branch_to_veneer =
17346 stm32l4xx_errnode->u.b.veneer->vma - stm32l4xx_errnode->vma;
17347
17348 if ((signed) branch_to_veneer < -(1 << 24)
17349 || (signed) branch_to_veneer >= (1 << 24))
17350 {
17351 bfd_vma out_of_range =
17352 ((signed) branch_to_veneer < -(1 << 24)) ?
17353 - branch_to_veneer - (1 << 24) :
17354 ((signed) branch_to_veneer >= (1 << 24)) ?
17355 branch_to_veneer - (1 << 24) : 0;
17356
17357 (*_bfd_error_handler)
17358 (_("%B(%#x): error: Cannot create STM32L4XX veneer. "
eee926f2 17359 "Jump out of range by %ld bytes. "
a504d23a
LA		 17360 "Cannot encode branch instruction. "),
17361 output_bfd,
eee926f2 17362 (long) (stm32l4xx_errnode->vma - 4),
a504d23a
LA		 17363 out_of_range);
17364 continue;
17365 }
17366
17367 insn = create_instruction_branch_absolute
82188b29 17368 (stm32l4xx_errnode->u.b.veneer->vma - stm32l4xx_errnode->vma);
a504d23a
LA		 17369
17370 /* The instruction is before the label. */
17371 target -= 4;
17372
17373 put_thumb2_insn (globals, output_bfd,
17374 (bfd_vma) insn, contents + target);
17375 }
17376 break;
17377
17378 case STM32L4XX_ERRATUM_VENEER:
17379 {
82188b29
NC		 17380 bfd_byte * veneer;
17381 bfd_byte * veneer_r;
a504d23a
LA		 17382 unsigned int insn;
17383
82188b29
NC		 17384 veneer = contents + target;
17385 veneer_r = veneer
17386 + stm32l4xx_errnode->u.b.veneer->vma
17387 - stm32l4xx_errnode->vma - 4;
a504d23a
LA		 17388
17389 if ((signed) (veneer_r - veneer -
17390 STM32L4XX_ERRATUM_VLDM_VENEER_SIZE >
17391 STM32L4XX_ERRATUM_LDM_VENEER_SIZE ?
17392 STM32L4XX_ERRATUM_VLDM_VENEER_SIZE :
17393 STM32L4XX_ERRATUM_LDM_VENEER_SIZE) < -(1 << 24)
17394 || (signed) (veneer_r - veneer) >= (1 << 24))
17395 {
17396 (*_bfd_error_handler) (_("%B: error: Cannot create STM32L4XX "
17397 "veneer."), output_bfd);
17398 continue;
17399 }
17400
17401 /* Original instruction. */
17402 insn = stm32l4xx_errnode->u.v.branch->u.b.insn;
17403
17404 stm32l4xx_create_replacing_stub
17405 (globals, output_bfd, insn, (void*)veneer_r, (void*)veneer);
17406 }
17407 break;
17408
17409 default:
17410 abort ();
17411 }
17412 }
17413 }
17414
2468f9c9
PB		 17415 if (arm_data->elf.this_hdr.sh_type == SHT_ARM_EXIDX)
17416 {
17417 arm_unwind_table_edit *edit_node
99059e56 17418 = arm_data->u.exidx.unwind_edit_list;
2468f9c9 17419 /* Now, sec->size is the size of the section we will write. The original
99059e56 17420 size (before we merged duplicate entries and inserted EXIDX_CANTUNWIND
2468f9c9
PB		 17421 markers) was sec->rawsize. (This isn't the case if we perform no
17422 edits, then rawsize will be zero and we should use size). */
21d799b5 17423 bfd_byte *edited_contents = (bfd_byte *) bfd_malloc (sec->size);
2468f9c9
PB		 17424 unsigned int input_size = sec->rawsize ? sec->rawsize : sec->size;
17425 unsigned int in_index, out_index;
17426 bfd_vma add_to_offsets = 0;
17427
17428 for (in_index = 0, out_index = 0; in_index * 8 < input_size || edit_node;)
99059e56 17429 {
2468f9c9
PB		 17430 if (edit_node)
17431 {
17432 unsigned int edit_index = edit_node->index;
b38cadfb 17433
2468f9c9 17434 if (in_index < edit_index && in_index * 8 < input_size)
99059e56 17435 {
2468f9c9
PB		 17436 copy_exidx_entry (output_bfd, edited_contents + out_index * 8,
17437 contents + in_index * 8, add_to_offsets);
17438 out_index++;
17439 in_index++;
17440 }
17441 else if (in_index == edit_index
17442 || (in_index * 8 >= input_size
17443 && edit_index == UINT_MAX))
99059e56 17444 {
2468f9c9
PB		 17445 switch (edit_node->type)
17446 {
17447 case DELETE_EXIDX_ENTRY:
17448 in_index++;
17449 add_to_offsets += 8;
17450 break;
b38cadfb 17451
2468f9c9
PB		 17452 case INSERT_EXIDX_CANTUNWIND_AT_END:
17453 {
99059e56 17454 asection *text_sec = edit_node->linked_section;
2468f9c9
PB		 17455 bfd_vma text_offset = text_sec->output_section->vma
17456 + text_sec->output_offset
17457 + text_sec->size;
17458 bfd_vma exidx_offset = offset + out_index * 8;
99059e56 17459 unsigned long prel31_offset;
2468f9c9
PB		 17460
17461 /* Note: this is meant to be equivalent to an
17462 R_ARM_PREL31 relocation. These synthetic
17463 EXIDX_CANTUNWIND markers are not relocated by the
17464 usual BFD method. */
17465 prel31_offset = (text_offset - exidx_offset)
17466 & 0x7ffffffful;
491d01d3
YU		 17467 if (bfd_link_relocatable (link_info))
17468 {
17469 /* Here relocation for new EXIDX_CANTUNWIND is
17470 created, so there is no need to
17471 adjust offset by hand. */
17472 prel31_offset = text_sec->output_offset
17473 + text_sec->size;
17474
17475 /* New relocation entity. */
17476 asection *text_out = text_sec->output_section;
17477 Elf_Internal_Rela rel;
17478 rel.r_addend = 0;
17479 rel.r_offset = exidx_offset;
17480 rel.r_info = ELF32_R_INFO (text_out->target_index,
17481 R_ARM_PREL31);
17482
17483 elf32_arm_add_relocation (output_bfd, link_info,
17484 sec->output_section,
17485 &rel);
17486 }
2468f9c9
PB		 17487
17488 /* First address we can't unwind. */
17489 bfd_put_32 (output_bfd, prel31_offset,
17490 &edited_contents[out_index * 8]);
17491
17492 /* Code for EXIDX_CANTUNWIND. */
17493 bfd_put_32 (output_bfd, 0x1,
17494 &edited_contents[out_index * 8 + 4]);
17495
17496 out_index++;
17497 add_to_offsets -= 8;
17498 }
17499 break;
17500 }
b38cadfb 17501
2468f9c9
PB		 17502 edit_node = edit_node->next;
17503 }
17504 }
17505 else
17506 {
17507 /* No more edits, copy remaining entries verbatim. */
17508 copy_exidx_entry (output_bfd, edited_contents + out_index * 8,
17509 contents + in_index * 8, add_to_offsets);
17510 out_index++;
17511 in_index++;
17512 }
17513 }
17514
17515 if (!(sec->flags & SEC_EXCLUDE) && !(sec->flags & SEC_NEVER_LOAD))
17516 bfd_set_section_contents (output_bfd, sec->output_section,
17517 edited_contents,
17518 (file_ptr) sec->output_offset, sec->size);
17519
17520 return TRUE;
17521 }
17522
48229727
JB		 17523 /* Fix code to point to Cortex-A8 erratum stubs. */
17524 if (globals->fix_cortex_a8)
17525 {
17526 struct a8_branch_to_stub_data data;
17527
17528 data.writing_section = sec;
17529 data.contents = contents;
17530
a504d23a
LA		 17531 bfd_hash_traverse (& globals->stub_hash_table, make_branch_to_a8_stub,
17532 & data);
48229727
JB		 17533 }
17534
e489d0ae
PB		 17535 if (mapcount == 0)
17536 return FALSE;
17537
c7b8f16e 17538 if (globals->byteswap_code)
e489d0ae 17539 {
c7b8f16e 17540 qsort (map, mapcount, sizeof (* map), elf32_arm_compare_mapping);
57e8b36a 17541
c7b8f16e
JB		 17542 ptr = map[0].vma;
17543 for (i = 0; i < mapcount; i++)
99059e56
RM		 17544 {
17545 if (i == mapcount - 1)
c7b8f16e 17546 end = sec->size;
99059e56
RM		 17547 else
17548 end = map[i + 1].vma;
e489d0ae 17549
99059e56 17550 switch (map[i].type)
e489d0ae 17551 {
c7b8f16e
JB		 17552 case 'a':
17553 /* Byte swap code words. */
17554 while (ptr + 3 < end)
99059e56
RM		 17555 {
17556 tmp = contents[ptr];
17557 contents[ptr] = contents[ptr + 3];
17558 contents[ptr + 3] = tmp;
17559 tmp = contents[ptr + 1];
17560 contents[ptr + 1] = contents[ptr + 2];
17561 contents[ptr + 2] = tmp;
17562 ptr += 4;
17563 }
c7b8f16e 17564 break;
e489d0ae 17565
c7b8f16e
JB		 17566 case 't':
17567 /* Byte swap code halfwords. */
17568 while (ptr + 1 < end)
99059e56
RM		 17569 {
17570 tmp = contents[ptr];
17571 contents[ptr] = contents[ptr + 1];
17572 contents[ptr + 1] = tmp;
17573 ptr += 2;
17574 }
c7b8f16e
JB		 17575 break;
17576
17577 case 'd':
17578 /* Leave data alone. */
17579 break;
17580 }
99059e56
RM		 17581 ptr = end;
17582 }
e489d0ae 17583 }
8e3de13a 17584
93204d3a 17585 free (map);
47b2e99c 17586 arm_data->mapcount = -1;
c7b8f16e 17587 arm_data->mapsize = 0;
8e3de13a 17588 arm_data->map = NULL;
8e3de13a 17589
e489d0ae
PB		 17590 return FALSE;
17591}
17592
0beaef2b
PB		 17593/* Mangle thumb function symbols as we read them in. */
17594
8384fb8f 17595static bfd_boolean
0beaef2b
PB		 17596elf32_arm_swap_symbol_in (bfd * abfd,
17597 const void *psrc,
17598 const void *pshn,
17599 Elf_Internal_Sym *dst)
17600{
8384fb8f
AM		 17601 if (!bfd_elf32_swap_symbol_in (abfd, psrc, pshn, dst))
17602 return FALSE;
39d911fc 17603 dst->st_target_internal = 0;
0beaef2b
PB		 17604
17605 /* New EABI objects mark thumb function symbols by setting the low bit of
35fc36a8 17606 the address. */
63e1a0fc
PB		 17607 if (ELF_ST_TYPE (dst->st_info) == STT_FUNC
17608 || ELF_ST_TYPE (dst->st_info) == STT_GNU_IFUNC)
0beaef2b 17609 {
63e1a0fc
PB		 17610 if (dst->st_value & 1)
17611 {
17612 dst->st_value &= ~(bfd_vma) 1;
39d911fc
TP		 17613 ARM_SET_SYM_BRANCH_TYPE (dst->st_target_internal,
17614 ST_BRANCH_TO_THUMB);
63e1a0fc
PB		 17615 }
17616 else
39d911fc 17617 ARM_SET_SYM_BRANCH_TYPE (dst->st_target_internal, ST_BRANCH_TO_ARM);
35fc36a8
RS		 17618 }
17619 else if (ELF_ST_TYPE (dst->st_info) == STT_ARM_TFUNC)
17620 {
17621 dst->st_info = ELF_ST_INFO (ELF_ST_BIND (dst->st_info), STT_FUNC);
39d911fc 17622 ARM_SET_SYM_BRANCH_TYPE (dst->st_target_internal, ST_BRANCH_TO_THUMB);
0beaef2b 17623 }
35fc36a8 17624 else if (ELF_ST_TYPE (dst->st_info) == STT_SECTION)
39d911fc 17625 ARM_SET_SYM_BRANCH_TYPE (dst->st_target_internal, ST_BRANCH_LONG);
35fc36a8 17626 else
39d911fc 17627 ARM_SET_SYM_BRANCH_TYPE (dst->st_target_internal, ST_BRANCH_UNKNOWN);
35fc36a8 17628
8384fb8f 17629 return TRUE;
0beaef2b
PB		 17630}
17631
17632
17633/* Mangle thumb function symbols as we write them out. */
17634
17635static void
17636elf32_arm_swap_symbol_out (bfd *abfd,
17637 const Elf_Internal_Sym *src,
17638 void *cdst,
17639 void *shndx)
17640{
17641 Elf_Internal_Sym newsym;
17642
17643 /* We convert STT_ARM_TFUNC symbols into STT_FUNC with the low bit
17644 of the address set, as per the new EABI. We do this unconditionally
17645 because objcopy does not set the elf header flags until after
17646 it writes out the symbol table. */
39d911fc 17647 if (ARM_GET_SYM_BRANCH_TYPE (src->st_target_internal) == ST_BRANCH_TO_THUMB)
0beaef2b
PB		 17648 {
17649 newsym = *src;
34e77a92
RS		 17650 if (ELF_ST_TYPE (src->st_info) != STT_GNU_IFUNC)
17651 newsym.st_info = ELF_ST_INFO (ELF_ST_BIND (src->st_info), STT_FUNC);
0fa3dcad 17652 if (newsym.st_shndx != SHN_UNDEF)
99059e56
RM		 17653 {
17654 /* Do this only for defined symbols. At link type, the static
17655 linker will simulate the work of dynamic linker of resolving
17656 symbols and will carry over the thumbness of found symbols to
17657 the output symbol table. It's not clear how it happens, but
17658 the thumbness of undefined symbols can well be different at
17659 runtime, and writing '1' for them will be confusing for users
17660 and possibly for dynamic linker itself.
17661 */
17662 newsym.st_value |= 1;
17663 }
906e58ca 17664
0beaef2b
PB		 17665 src = &newsym;
17666 }
17667 bfd_elf32_swap_symbol_out (abfd, src, cdst, shndx);
17668}
17669
b294bdf8
MM		 17670/* Add the PT_ARM_EXIDX program header. */
17671
17672static bfd_boolean
906e58ca 17673elf32_arm_modify_segment_map (bfd *abfd,
b294bdf8
MM		 17674 struct bfd_link_info *info ATTRIBUTE_UNUSED)
17675{
17676 struct elf_segment_map *m;
17677 asection *sec;
17678
17679 sec = bfd_get_section_by_name (abfd, ".ARM.exidx");
17680 if (sec != NULL && (sec->flags & SEC_LOAD) != 0)
17681 {
17682 /* If there is already a PT_ARM_EXIDX header, then we do not
17683 want to add another one. This situation arises when running
17684 "strip"; the input binary already has the header. */
12bd6957 17685 m = elf_seg_map (abfd);
b294bdf8
MM		 17686 while (m && m->p_type != PT_ARM_EXIDX)
17687 m = m->next;
17688 if (!m)
17689 {
21d799b5 17690 m = (struct elf_segment_map *)
99059e56 17691 bfd_zalloc (abfd, sizeof (struct elf_segment_map));
b294bdf8
MM		 17692 if (m == NULL)
17693 return FALSE;
17694 m->p_type = PT_ARM_EXIDX;
17695 m->count = 1;
17696 m->sections[0] = sec;
17697
12bd6957
AM		 17698 m->next = elf_seg_map (abfd);
17699 elf_seg_map (abfd) = m;
b294bdf8
MM		 17700 }
17701 }
17702
17703 return TRUE;
17704}
17705
17706/* We may add a PT_ARM_EXIDX program header. */
17707
17708static int
a6b96beb
AM		 17709elf32_arm_additional_program_headers (bfd *abfd,
17710 struct bfd_link_info *info ATTRIBUTE_UNUSED)
b294bdf8
MM		 17711{
17712 asection *sec;
17713
17714 sec = bfd_get_section_by_name (abfd, ".ARM.exidx");
17715 if (sec != NULL && (sec->flags & SEC_LOAD) != 0)
17716 return 1;
17717 else
17718 return 0;
17719}
17720
34e77a92
RS		 17721/* Hook called by the linker routine which adds symbols from an object
17722 file. */
17723
17724static bfd_boolean
17725elf32_arm_add_symbol_hook (bfd *abfd, struct bfd_link_info *info,
17726 Elf_Internal_Sym *sym, const char **namep,
17727 flagword *flagsp, asection **secp, bfd_vma *valp)
17728{
f1885d1e
AM		 17729 if ((ELF_ST_TYPE (sym->st_info) == STT_GNU_IFUNC
17730 || ELF_ST_BIND (sym->st_info) == STB_GNU_UNIQUE)
17731 && (abfd->flags & DYNAMIC) == 0
17732 && bfd_get_flavour (info->output_bfd) == bfd_target_elf_flavour)
13a2df29 17733 elf_tdata (info->output_bfd)->has_gnu_symbols = elf_gnu_symbol_any;
34e77a92 17734
c792917c
NC		 17735 if (elf32_arm_hash_table (info) == NULL)
17736 return FALSE;
17737
34e77a92
RS		 17738 if (elf32_arm_hash_table (info)->vxworks_p
17739 && !elf_vxworks_add_symbol_hook (abfd, info, sym, namep,
17740 flagsp, secp, valp))
17741 return FALSE;
17742
17743 return TRUE;
17744}
17745
0beaef2b 17746/* We use this to override swap_symbol_in and swap_symbol_out. */
906e58ca
NC		 17747const struct elf_size_info elf32_arm_size_info =
17748{
0beaef2b
PB		 17749 sizeof (Elf32_External_Ehdr),
17750 sizeof (Elf32_External_Phdr),
17751 sizeof (Elf32_External_Shdr),
17752 sizeof (Elf32_External_Rel),
17753 sizeof (Elf32_External_Rela),
17754 sizeof (Elf32_External_Sym),
17755 sizeof (Elf32_External_Dyn),
17756 sizeof (Elf_External_Note),
17757 4,
17758 1,
17759 32, 2,
17760 ELFCLASS32, EV_CURRENT,
17761 bfd_elf32_write_out_phdrs,
17762 bfd_elf32_write_shdrs_and_ehdr,
1489a3a0 17763 bfd_elf32_checksum_contents,
0beaef2b
PB		 17764 bfd_elf32_write_relocs,
17765 elf32_arm_swap_symbol_in,
17766 elf32_arm_swap_symbol_out,
17767 bfd_elf32_slurp_reloc_table,
17768 bfd_elf32_slurp_symbol_table,
17769 bfd_elf32_swap_dyn_in,
17770 bfd_elf32_swap_dyn_out,
17771 bfd_elf32_swap_reloc_in,
17772 bfd_elf32_swap_reloc_out,
17773 bfd_elf32_swap_reloca_in,
17774 bfd_elf32_swap_reloca_out
17775};
17776
685e70ae
VK		 17777static bfd_vma
17778read_code32 (const bfd *abfd, const bfd_byte *addr)
17779{
17780 /* V7 BE8 code is always little endian. */
17781 if ((elf_elfheader (abfd)->e_flags & EF_ARM_BE8) != 0)
17782 return bfd_getl32 (addr);
17783
17784 return bfd_get_32 (abfd, addr);
17785}
17786
17787static bfd_vma
17788read_code16 (const bfd *abfd, const bfd_byte *addr)
17789{
17790 /* V7 BE8 code is always little endian. */
17791 if ((elf_elfheader (abfd)->e_flags & EF_ARM_BE8) != 0)
17792 return bfd_getl16 (addr);
17793
17794 return bfd_get_16 (abfd, addr);
17795}
17796
6a631e86
YG		 17797/* Return size of plt0 entry starting at ADDR
17798 or (bfd_vma) -1 if size can not be determined. */
17799
17800static bfd_vma
17801elf32_arm_plt0_size (const bfd *abfd, const bfd_byte *addr)
17802{
17803 bfd_vma first_word;
17804 bfd_vma plt0_size;
17805
685e70ae 17806 first_word = read_code32 (abfd, addr);
6a631e86
YG		 17807
17808 if (first_word == elf32_arm_plt0_entry[0])
17809 plt0_size = 4 * ARRAY_SIZE (elf32_arm_plt0_entry);
17810 else if (first_word == elf32_thumb2_plt0_entry[0])
17811 plt0_size = 4 * ARRAY_SIZE (elf32_thumb2_plt0_entry);
17812 else
17813 /* We don't yet handle this PLT format. */
17814 return (bfd_vma) -1;
17815
17816 return plt0_size;
17817}
17818
17819/* Return size of plt entry starting at offset OFFSET
17820 of plt section located at address START
17821 or (bfd_vma) -1 if size can not be determined. */
17822
17823static bfd_vma
17824elf32_arm_plt_size (const bfd *abfd, const bfd_byte *start, bfd_vma offset)
17825{
17826 bfd_vma first_insn;
17827 bfd_vma plt_size = 0;
17828 const bfd_byte *addr = start + offset;
17829
17830 /* PLT entry size if fixed on Thumb-only platforms. */
685e70ae 17831 if (read_code32 (abfd, start) == elf32_thumb2_plt0_entry[0])
6a631e86
YG		 17832 return 4 * ARRAY_SIZE (elf32_thumb2_plt_entry);
17833
17834 /* Respect Thumb stub if necessary. */
685e70ae 17835 if (read_code16 (abfd, addr) == elf32_arm_plt_thumb_stub[0])
6a631e86
YG		 17836 {
17837 plt_size += 2 * ARRAY_SIZE(elf32_arm_plt_thumb_stub);
17838 }
17839
17840 /* Strip immediate from first add. */
685e70ae 17841 first_insn = read_code32 (abfd, addr + plt_size) & 0xffffff00;
6a631e86
YG		 17842
17843#ifdef FOUR_WORD_PLT
17844 if (first_insn == elf32_arm_plt_entry[0])
17845 plt_size += 4 * ARRAY_SIZE (elf32_arm_plt_entry);
17846#else
17847 if (first_insn == elf32_arm_plt_entry_long[0])
17848 plt_size += 4 * ARRAY_SIZE (elf32_arm_plt_entry_long);
17849 else if (first_insn == elf32_arm_plt_entry_short[0])
17850 plt_size += 4 * ARRAY_SIZE (elf32_arm_plt_entry_short);
17851#endif
17852 else
17853 /* We don't yet handle this PLT format. */
17854 return (bfd_vma) -1;
17855
17856 return plt_size;
17857}
17858
17859/* Implementation is shamelessly borrowed from _bfd_elf_get_synthetic_symtab. */
17860
17861static long
17862elf32_arm_get_synthetic_symtab (bfd *abfd,
17863 long symcount ATTRIBUTE_UNUSED,
17864 asymbol **syms ATTRIBUTE_UNUSED,
17865 long dynsymcount,
17866 asymbol **dynsyms,
17867 asymbol **ret)
17868{
17869 asection *relplt;
17870 asymbol *s;
17871 arelent *p;
17872 long count, i, n;
17873 size_t size;
17874 Elf_Internal_Shdr *hdr;
17875 char *names;
17876 asection *plt;
17877 bfd_vma offset;
17878 bfd_byte *data;
17879
17880 *ret = NULL;
17881
17882 if ((abfd->flags & (DYNAMIC | EXEC_P)) == 0)
17883 return 0;
17884
17885 if (dynsymcount <= 0)
17886 return 0;
17887
17888 relplt = bfd_get_section_by_name (abfd, ".rel.plt");
17889 if (relplt == NULL)
17890 return 0;
17891
17892 hdr = &elf_section_data (relplt)->this_hdr;
17893 if (hdr->sh_link != elf_dynsymtab (abfd)
17894 || (hdr->sh_type != SHT_REL && hdr->sh_type != SHT_RELA))
17895 return 0;
17896
17897 plt = bfd_get_section_by_name (abfd, ".plt");
17898 if (plt == NULL)
17899 return 0;
17900
17901 if (!elf32_arm_size_info.slurp_reloc_table (abfd, relplt, dynsyms, TRUE))
17902 return -1;
17903
17904 data = plt->contents;
17905 if (data == NULL)
17906 {
17907 if (!bfd_get_full_section_contents(abfd, (asection *) plt, &data) || data == NULL)
17908 return -1;
17909 bfd_cache_section_contents((asection *) plt, data);
17910 }
17911
17912 count = relplt->size / hdr->sh_entsize;
17913 size = count * sizeof (asymbol);
17914 p = relplt->relocation;
17915 for (i = 0; i < count; i++, p += elf32_arm_size_info.int_rels_per_ext_rel)
17916 {
17917 size += strlen ((*p->sym_ptr_ptr)->name) + sizeof ("@plt");
17918 if (p->addend != 0)
17919 size += sizeof ("+0x") - 1 + 8;
17920 }
17921
17922 s = *ret = (asymbol *) bfd_malloc (size);
17923 if (s == NULL)
17924 return -1;
17925
17926 offset = elf32_arm_plt0_size (abfd, data);
17927 if (offset == (bfd_vma) -1)
17928 return -1;
17929
17930 names = (char *) (s + count);
17931 p = relplt->relocation;
17932 n = 0;
17933 for (i = 0; i < count; i++, p += elf32_arm_size_info.int_rels_per_ext_rel)
17934 {
17935 size_t len;
17936
17937 bfd_vma plt_size = elf32_arm_plt_size (abfd, data, offset);
17938 if (plt_size == (bfd_vma) -1)
17939 break;
17940
17941 *s = **p->sym_ptr_ptr;
17942 /* Undefined syms won't have BSF_LOCAL or BSF_GLOBAL set. Since
17943 we are defining a symbol, ensure one of them is set. */
17944 if ((s->flags & BSF_LOCAL) == 0)
17945 s->flags |= BSF_GLOBAL;
17946 s->flags |= BSF_SYNTHETIC;
17947 s->section = plt;
17948 s->value = offset;
17949 s->name = names;
17950 s->udata.p = NULL;
17951 len = strlen ((*p->sym_ptr_ptr)->name);
17952 memcpy (names, (*p->sym_ptr_ptr)->name, len);
17953 names += len;
17954 if (p->addend != 0)
17955 {
17956 char buf[30], *a;
17957
17958 memcpy (names, "+0x", sizeof ("+0x") - 1);
17959 names += sizeof ("+0x") - 1;
17960 bfd_sprintf_vma (abfd, buf, p->addend);
17961 for (a = buf; *a == '0'; ++a)
17962 ;
17963 len = strlen (a);
17964 memcpy (names, a, len);
17965 names += len;
17966 }
17967 memcpy (names, "@plt", sizeof ("@plt"));
17968 names += sizeof ("@plt");
17969 ++s, ++n;
17970 offset += plt_size;
17971 }
17972
17973 return n;
17974}
17975
ac4c9b04
MG		 17976static bfd_boolean
17977elf32_arm_section_flags (flagword *flags, const Elf_Internal_Shdr * hdr)
17978{
17979 if (hdr->sh_flags & SHF_ARM_NOREAD)
17980 *flags |= SEC_ELF_NOREAD;
17981 return TRUE;
17982}
17983
17984static flagword
17985elf32_arm_lookup_section_flags (char *flag_name)
17986{
17987 if (!strcmp (flag_name, "SHF_ARM_NOREAD"))
17988 return SHF_ARM_NOREAD;
17989
17990 return SEC_NO_FLAGS;
17991}
17992
491d01d3
YU		 17993static unsigned int
17994elf32_arm_count_additional_relocs (asection *sec)
17995{
17996 struct _arm_elf_section_data *arm_data;
17997 arm_data = get_arm_elf_section_data (sec);
17998 return arm_data->additional_reloc_count;
17999}
18000
5522f910
NC		 18001/* Called to set the sh_flags, sh_link and sh_info fields of OSECTION which
18002 has a type >= SHT_LOOS. Returns TRUE if these fields were initialised
18003 FALSE otherwise. ISECTION is the best guess matching section from the
18004 input bfd IBFD, but it might be NULL. */
18005
18006static bfd_boolean
18007elf32_arm_copy_special_section_fields (const bfd *ibfd ATTRIBUTE_UNUSED,
18008 bfd *obfd ATTRIBUTE_UNUSED,
18009 const Elf_Internal_Shdr *isection ATTRIBUTE_UNUSED,
18010 Elf_Internal_Shdr *osection)
18011{
18012 switch (osection->sh_type)
18013 {
18014 case SHT_ARM_EXIDX:
18015 {
18016 Elf_Internal_Shdr **oheaders = elf_elfsections (obfd);
18017 Elf_Internal_Shdr **iheaders = elf_elfsections (ibfd);
18018 unsigned i = 0;
18019
18020 osection->sh_flags = SHF_ALLOC | SHF_LINK_ORDER;
18021 osection->sh_info = 0;
18022
18023 /* The sh_link field must be set to the text section associated with
18024 this index section. Unfortunately the ARM EHABI does not specify
18025 exactly how to determine this association. Our caller does try
18026 to match up OSECTION with its corresponding input section however
18027 so that is a good first guess. */
18028 if (isection != NULL
18029 && osection->bfd_section != NULL
18030 && isection->bfd_section != NULL
18031 && isection->bfd_section->output_section != NULL
18032 && isection->bfd_section->output_section == osection->bfd_section
18033 && iheaders != NULL
18034 && isection->sh_link > 0
18035 && isection->sh_link < elf_numsections (ibfd)
18036 && iheaders[isection->sh_link]->bfd_section != NULL
18037 && iheaders[isection->sh_link]->bfd_section->output_section != NULL
18038 )
18039 {
18040 for (i = elf_numsections (obfd); i-- > 0;)
18041 if (oheaders[i]->bfd_section
18042 == iheaders[isection->sh_link]->bfd_section->output_section)
18043 break;
18044 }
18045
18046 if (i == 0)
18047 {
18048 /* Failing that we have to find a matching section ourselves. If
18049 we had the output section name available we could compare that
18050 with input section names. Unfortunately we don't. So instead
18051 we use a simple heuristic and look for the nearest executable
18052 section before this one. */
18053 for (i = elf_numsections (obfd); i-- > 0;)
18054 if (oheaders[i] == osection)
18055 break;
18056 if (i == 0)
18057 break;
18058
18059 while (i-- > 0)
18060 if (oheaders[i]->sh_type == SHT_PROGBITS
18061 && (oheaders[i]->sh_flags & (SHF_ALLOC | SHF_EXECINSTR))
18062 == (SHF_ALLOC | SHF_EXECINSTR))
18063 break;
18064 }
18065
18066 if (i)
18067 {
18068 osection->sh_link = i;
18069 /* If the text section was part of a group
18070 then the index section should be too. */
18071 if (oheaders[i]->sh_flags & SHF_GROUP)
18072 osection->sh_flags |= SHF_GROUP;
18073 return TRUE;
18074 }
18075 }
18076 break;
18077
18078 case SHT_ARM_PREEMPTMAP:
18079 osection->sh_flags = SHF_ALLOC;
18080 break;
18081
18082 case SHT_ARM_ATTRIBUTES:
18083 case SHT_ARM_DEBUGOVERLAY:
18084 case SHT_ARM_OVERLAYSECTION:
18085 default:
18086 break;
18087 }
18088
18089 return FALSE;
18090}
18091
18092#undef elf_backend_copy_special_section_fields
18093#define elf_backend_copy_special_section_fields elf32_arm_copy_special_section_fields
18094
252b5132 18095#define ELF_ARCH bfd_arch_arm
ae95ffa6 18096#define ELF_TARGET_ID ARM_ELF_DATA
252b5132 18097#define ELF_MACHINE_CODE EM_ARM
d0facd1b
NC		 18098#ifdef __QNXTARGET__
18099#define ELF_MAXPAGESIZE 0x1000
18100#else
7572ca89 18101#define ELF_MAXPAGESIZE 0x10000
d0facd1b 18102#endif
b1342370 18103#define ELF_MINPAGESIZE 0x1000
24718e3b 18104#define ELF_COMMONPAGESIZE 0x1000
252b5132 18105
ba93b8ac
DJ		 18106#define bfd_elf32_mkobject elf32_arm_mkobject
18107
99e4ae17
AJ		 18108#define bfd_elf32_bfd_copy_private_bfd_data elf32_arm_copy_private_bfd_data
18109#define bfd_elf32_bfd_merge_private_bfd_data elf32_arm_merge_private_bfd_data
252b5132
RH		 18110#define bfd_elf32_bfd_set_private_flags elf32_arm_set_private_flags
18111#define bfd_elf32_bfd_print_private_bfd_data elf32_arm_print_private_bfd_data
18112#define bfd_elf32_bfd_link_hash_table_create elf32_arm_link_hash_table_create
dc810e39 18113#define bfd_elf32_bfd_reloc_type_lookup elf32_arm_reloc_type_lookup
b38cadfb 18114#define bfd_elf32_bfd_reloc_name_lookup elf32_arm_reloc_name_lookup
252b5132 18115#define bfd_elf32_find_nearest_line elf32_arm_find_nearest_line
4ab527b0 18116#define bfd_elf32_find_inliner_info elf32_arm_find_inliner_info
e489d0ae 18117#define bfd_elf32_new_section_hook elf32_arm_new_section_hook
3c9458e9 18118#define bfd_elf32_bfd_is_target_special_symbol elf32_arm_is_target_special_symbol
3e6b1042 18119#define bfd_elf32_bfd_final_link elf32_arm_final_link
6a631e86 18120#define bfd_elf32_get_synthetic_symtab elf32_arm_get_synthetic_symtab
252b5132
RH		 18121
18122#define elf_backend_get_symbol_type elf32_arm_get_symbol_type
18123#define elf_backend_gc_mark_hook elf32_arm_gc_mark_hook
6a5bb875 18124#define elf_backend_gc_mark_extra_sections elf32_arm_gc_mark_extra_sections
252b5132
RH		 18125#define elf_backend_gc_sweep_hook elf32_arm_gc_sweep_hook
18126#define elf_backend_check_relocs elf32_arm_check_relocs
dc810e39 18127#define elf_backend_relocate_section elf32_arm_relocate_section
e489d0ae 18128#define elf_backend_write_section elf32_arm_write_section
252b5132 18129#define elf_backend_adjust_dynamic_symbol elf32_arm_adjust_dynamic_symbol
5e681ec4 18130#define elf_backend_create_dynamic_sections elf32_arm_create_dynamic_sections
252b5132
RH		 18131#define elf_backend_finish_dynamic_symbol elf32_arm_finish_dynamic_symbol
18132#define elf_backend_finish_dynamic_sections elf32_arm_finish_dynamic_sections
18133#define elf_backend_size_dynamic_sections elf32_arm_size_dynamic_sections
0855e32b 18134#define elf_backend_always_size_sections elf32_arm_always_size_sections
74541ad4 18135#define elf_backend_init_index_section _bfd_elf_init_2_index_sections
ba96a88f 18136#define elf_backend_post_process_headers elf32_arm_post_process_headers
99e4ae17 18137#define elf_backend_reloc_type_class elf32_arm_reloc_type_class
c178919b 18138#define elf_backend_object_p elf32_arm_object_p
40a18ebd
NC		 18139#define elf_backend_fake_sections elf32_arm_fake_sections
18140#define elf_backend_section_from_shdr elf32_arm_section_from_shdr
e16bb312 18141#define elf_backend_final_write_processing elf32_arm_final_write_processing
5e681ec4 18142#define elf_backend_copy_indirect_symbol elf32_arm_copy_indirect_symbol
0beaef2b 18143#define elf_backend_size_info elf32_arm_size_info
b294bdf8 18144#define elf_backend_modify_segment_map elf32_arm_modify_segment_map
906e58ca
NC		 18145#define elf_backend_additional_program_headers elf32_arm_additional_program_headers
18146#define elf_backend_output_arch_local_syms elf32_arm_output_arch_local_syms
18147#define elf_backend_begin_write_processing elf32_arm_begin_write_processing
34e77a92 18148#define elf_backend_add_symbol_hook elf32_arm_add_symbol_hook
491d01d3 18149#define elf_backend_count_additional_relocs elf32_arm_count_additional_relocs
906e58ca
NC		 18150
18151#define elf_backend_can_refcount 1
18152#define elf_backend_can_gc_sections 1
18153#define elf_backend_plt_readonly 1
18154#define elf_backend_want_got_plt 1
18155#define elf_backend_want_plt_sym 0
18156#define elf_backend_may_use_rel_p 1
18157#define elf_backend_may_use_rela_p 0
4e7fd91e 18158#define elf_backend_default_use_rela_p 0
252b5132 18159
04f7c78d 18160#define elf_backend_got_header_size 12
b68a20d6 18161#define elf_backend_extern_protected_data 1
04f7c78d 18162
906e58ca
NC		 18163#undef elf_backend_obj_attrs_vendor
18164#define elf_backend_obj_attrs_vendor "aeabi"
18165#undef elf_backend_obj_attrs_section
18166#define elf_backend_obj_attrs_section ".ARM.attributes"
18167#undef elf_backend_obj_attrs_arg_type
18168#define elf_backend_obj_attrs_arg_type elf32_arm_obj_attrs_arg_type
18169#undef elf_backend_obj_attrs_section_type
104d59d1 18170#define elf_backend_obj_attrs_section_type SHT_ARM_ATTRIBUTES
b38cadfb
NC		 18171#define elf_backend_obj_attrs_order elf32_arm_obj_attrs_order
18172#define elf_backend_obj_attrs_handle_unknown elf32_arm_obj_attrs_handle_unknown
104d59d1 18173
ac4c9b04
MG		 18174#undef elf_backend_section_flags
18175#define elf_backend_section_flags elf32_arm_section_flags
18176#undef elf_backend_lookup_section_flags_hook
18177#define elf_backend_lookup_section_flags_hook elf32_arm_lookup_section_flags
18178
252b5132 18179#include "elf32-target.h"
7f266840 18180
b38cadfb
NC		 18181/* Native Client targets. */
18182
18183#undef TARGET_LITTLE_SYM
6d00b590 18184#define TARGET_LITTLE_SYM arm_elf32_nacl_le_vec
b38cadfb
NC		 18185#undef TARGET_LITTLE_NAME
18186#define TARGET_LITTLE_NAME "elf32-littlearm-nacl"
18187#undef TARGET_BIG_SYM
6d00b590 18188#define TARGET_BIG_SYM arm_elf32_nacl_be_vec
b38cadfb
NC		 18189#undef TARGET_BIG_NAME
18190#define TARGET_BIG_NAME "elf32-bigarm-nacl"
18191
18192/* Like elf32_arm_link_hash_table_create -- but overrides
18193 appropriately for NaCl. */
18194
18195static struct bfd_link_hash_table *
18196elf32_arm_nacl_link_hash_table_create (bfd *abfd)
18197{
18198 struct bfd_link_hash_table *ret;
18199
18200 ret = elf32_arm_link_hash_table_create (abfd);
18201 if (ret)
18202 {
18203 struct elf32_arm_link_hash_table *htab
18204 = (struct elf32_arm_link_hash_table *) ret;
18205
18206 htab->nacl_p = 1;
18207
18208 htab->plt_header_size = 4 * ARRAY_SIZE (elf32_arm_nacl_plt0_entry);
18209 htab->plt_entry_size = 4 * ARRAY_SIZE (elf32_arm_nacl_plt_entry);
18210 }
18211 return ret;
18212}
18213
18214/* Since NaCl doesn't use the ARM-specific unwind format, we don't
18215 really need to use elf32_arm_modify_segment_map. But we do it
18216 anyway just to reduce gratuitous differences with the stock ARM backend. */
18217
18218static bfd_boolean
18219elf32_arm_nacl_modify_segment_map (bfd *abfd, struct bfd_link_info *info)
18220{
18221 return (elf32_arm_modify_segment_map (abfd, info)
18222 && nacl_modify_segment_map (abfd, info));
18223}
18224
887badb3
RM		 18225static void
18226elf32_arm_nacl_final_write_processing (bfd *abfd, bfd_boolean linker)
18227{
18228 elf32_arm_final_write_processing (abfd, linker);
18229 nacl_final_write_processing (abfd, linker);
18230}
18231
6a631e86
YG		 18232static bfd_vma
18233elf32_arm_nacl_plt_sym_val (bfd_vma i, const asection *plt,
18234 const arelent *rel ATTRIBUTE_UNUSED)
18235{
18236 return plt->vma
18237 + 4 * (ARRAY_SIZE (elf32_arm_nacl_plt0_entry) +
18238 i * ARRAY_SIZE (elf32_arm_nacl_plt_entry));
18239}
887badb3 18240
b38cadfb 18241#undef elf32_bed
6a631e86 18242#define elf32_bed elf32_arm_nacl_bed
b38cadfb
NC		 18243#undef bfd_elf32_bfd_link_hash_table_create
18244#define bfd_elf32_bfd_link_hash_table_create \
18245 elf32_arm_nacl_link_hash_table_create
18246#undef elf_backend_plt_alignment
6a631e86 18247#define elf_backend_plt_alignment 4
b38cadfb
NC		 18248#undef elf_backend_modify_segment_map
18249#define elf_backend_modify_segment_map elf32_arm_nacl_modify_segment_map
18250#undef elf_backend_modify_program_headers
18251#define elf_backend_modify_program_headers nacl_modify_program_headers
887badb3
RM		 18252#undef elf_backend_final_write_processing
18253#define elf_backend_final_write_processing elf32_arm_nacl_final_write_processing
6a631e86
YG		 18254#undef bfd_elf32_get_synthetic_symtab
18255#undef elf_backend_plt_sym_val
18256#define elf_backend_plt_sym_val elf32_arm_nacl_plt_sym_val
5522f910 18257#undef elf_backend_copy_special_section_fields
b38cadfb 18258
887badb3
RM		 18259#undef ELF_MINPAGESIZE
18260#undef ELF_COMMONPAGESIZE
18261
b38cadfb
NC		 18262
18263#include "elf32-target.h"
18264
18265/* Reset to defaults. */
18266#undef elf_backend_plt_alignment
18267#undef elf_backend_modify_segment_map
18268#define elf_backend_modify_segment_map elf32_arm_modify_segment_map
18269#undef elf_backend_modify_program_headers
887badb3
RM		 18270#undef elf_backend_final_write_processing
18271#define elf_backend_final_write_processing elf32_arm_final_write_processing
18272#undef ELF_MINPAGESIZE
18273#define ELF_MINPAGESIZE 0x1000
18274#undef ELF_COMMONPAGESIZE
18275#define ELF_COMMONPAGESIZE 0x1000
18276
b38cadfb 18277
906e58ca 18278/* VxWorks Targets. */
4e7fd91e 18279
906e58ca 18280#undef TARGET_LITTLE_SYM
6d00b590 18281#define TARGET_LITTLE_SYM arm_elf32_vxworks_le_vec
906e58ca 18282#undef TARGET_LITTLE_NAME
4e7fd91e 18283#define TARGET_LITTLE_NAME "elf32-littlearm-vxworks"
906e58ca 18284#undef TARGET_BIG_SYM
6d00b590 18285#define TARGET_BIG_SYM arm_elf32_vxworks_be_vec
906e58ca 18286#undef TARGET_BIG_NAME
4e7fd91e
PB		 18287#define TARGET_BIG_NAME "elf32-bigarm-vxworks"
18288
18289/* Like elf32_arm_link_hash_table_create -- but overrides
18290 appropriately for VxWorks. */
906e58ca 18291
4e7fd91e
PB		 18292static struct bfd_link_hash_table *
18293elf32_arm_vxworks_link_hash_table_create (bfd *abfd)
18294{
18295 struct bfd_link_hash_table *ret;
18296
18297 ret = elf32_arm_link_hash_table_create (abfd);
18298 if (ret)
18299 {
18300 struct elf32_arm_link_hash_table *htab
00a97672 18301 = (struct elf32_arm_link_hash_table *) ret;
4e7fd91e 18302 htab->use_rel = 0;
00a97672 18303 htab->vxworks_p = 1;
4e7fd91e
PB		 18304 }
18305 return ret;
906e58ca 18306}
4e7fd91e 18307
00a97672
RS		 18308static void
18309elf32_arm_vxworks_final_write_processing (bfd *abfd, bfd_boolean linker)
18310{
18311 elf32_arm_final_write_processing (abfd, linker);
18312 elf_vxworks_final_write_processing (abfd, linker);
18313}
18314
906e58ca 18315#undef elf32_bed
4e7fd91e
PB		 18316#define elf32_bed elf32_arm_vxworks_bed
18317
906e58ca
NC		 18318#undef bfd_elf32_bfd_link_hash_table_create
18319#define bfd_elf32_bfd_link_hash_table_create elf32_arm_vxworks_link_hash_table_create
906e58ca
NC		 18320#undef elf_backend_final_write_processing
18321#define elf_backend_final_write_processing elf32_arm_vxworks_final_write_processing
18322#undef elf_backend_emit_relocs
18323#define elf_backend_emit_relocs elf_vxworks_emit_relocs
4e7fd91e 18324
906e58ca 18325#undef elf_backend_may_use_rel_p
00a97672 18326#define elf_backend_may_use_rel_p 0
906e58ca 18327#undef elf_backend_may_use_rela_p
00a97672 18328#define elf_backend_may_use_rela_p 1
906e58ca 18329#undef elf_backend_default_use_rela_p
00a97672 18330#define elf_backend_default_use_rela_p 1
906e58ca 18331#undef elf_backend_want_plt_sym
00a97672 18332#define elf_backend_want_plt_sym 1
906e58ca 18333#undef ELF_MAXPAGESIZE
00a97672 18334#define ELF_MAXPAGESIZE 0x1000
4e7fd91e
PB		 18335
18336#include "elf32-target.h"
18337
18338
21d799b5
NC		 18339/* Merge backend specific data from an object file to the output
18340 object file when linking. */
18341
18342static bfd_boolean
18343elf32_arm_merge_private_bfd_data (bfd * ibfd, bfd * obfd)
18344{
18345 flagword out_flags;
18346 flagword in_flags;
18347 bfd_boolean flags_compatible = TRUE;
18348 asection *sec;
18349
cc643b88 18350 /* Check if we have the same endianness. */
21d799b5
NC		 18351 if (! _bfd_generic_verify_endian_match (ibfd, obfd))
18352 return FALSE;
18353
18354 if (! is_arm_elf (ibfd) || ! is_arm_elf (obfd))
18355 return TRUE;
18356
18357 if (!elf32_arm_merge_eabi_attributes (ibfd, obfd))
18358 return FALSE;
18359
18360 /* The input BFD must have had its flags initialised. */
18361 /* The following seems bogus to me -- The flags are initialized in
18362 the assembler but I don't think an elf_flags_init field is
18363 written into the object. */
18364 /* BFD_ASSERT (elf_flags_init (ibfd)); */
18365
18366 in_flags = elf_elfheader (ibfd)->e_flags;
18367 out_flags = elf_elfheader (obfd)->e_flags;
18368
18369 /* In theory there is no reason why we couldn't handle this. However
18370 in practice it isn't even close to working and there is no real
18371 reason to want it. */
18372 if (EF_ARM_EABI_VERSION (in_flags) >= EF_ARM_EABI_VER4
18373 && !(ibfd->flags & DYNAMIC)
18374 && (in_flags & EF_ARM_BE8))
18375 {
18376 _bfd_error_handler (_("error: %B is already in final BE8 format"),
18377 ibfd);
18378 return FALSE;
18379 }
18380
18381 if (!elf_flags_init (obfd))
18382 {
18383 /* If the input is the default architecture and had the default
18384 flags then do not bother setting the flags for the output
18385 architecture, instead allow future merges to do this. If no
18386 future merges ever set these flags then they will retain their
99059e56
RM		 18387 uninitialised values, which surprise surprise, correspond
18388 to the default values. */
21d799b5
NC		 18389 if (bfd_get_arch_info (ibfd)->the_default
18390 && elf_elfheader (ibfd)->e_flags == 0)
18391 return TRUE;
18392
18393 elf_flags_init (obfd) = TRUE;
18394 elf_elfheader (obfd)->e_flags = in_flags;
18395
18396 if (bfd_get_arch (obfd) == bfd_get_arch (ibfd)
18397 && bfd_get_arch_info (obfd)->the_default)
18398 return bfd_set_arch_mach (obfd, bfd_get_arch (ibfd), bfd_get_mach (ibfd));
18399
18400 return TRUE;
18401 }
18402
18403 /* Determine what should happen if the input ARM architecture
18404 does not match the output ARM architecture. */
18405 if (! bfd_arm_merge_machines (ibfd, obfd))
18406 return FALSE;
18407
18408 /* Identical flags must be compatible. */
18409 if (in_flags == out_flags)
18410 return TRUE;
18411
18412 /* Check to see if the input BFD actually contains any sections. If
18413 not, its flags may not have been initialised either, but it
18414 cannot actually cause any incompatiblity. Do not short-circuit
18415 dynamic objects; their section list may be emptied by
18416 elf_link_add_object_symbols.
18417
18418 Also check to see if there are no code sections in the input.
18419 In this case there is no need to check for code specific flags.
18420 XXX - do we need to worry about floating-point format compatability
18421 in data sections ? */
18422 if (!(ibfd->flags & DYNAMIC))
18423 {
18424 bfd_boolean null_input_bfd = TRUE;
18425 bfd_boolean only_data_sections = TRUE;
18426
18427 for (sec = ibfd->sections; sec != NULL; sec = sec->next)
18428 {
18429 /* Ignore synthetic glue sections. */
18430 if (strcmp (sec->name, ".glue_7")
18431 && strcmp (sec->name, ".glue_7t"))
18432 {
18433 if ((bfd_get_section_flags (ibfd, sec)
18434 & (SEC_LOAD | SEC_CODE | SEC_HAS_CONTENTS))
18435 == (SEC_LOAD | SEC_CODE | SEC_HAS_CONTENTS))
99059e56 18436 only_data_sections = FALSE;
21d799b5
NC		 18437
18438 null_input_bfd = FALSE;
18439 break;
18440 }
18441 }
18442
18443 if (null_input_bfd || only_data_sections)
18444 return TRUE;
18445 }
18446
18447 /* Complain about various flag mismatches. */
18448 if (!elf32_arm_versions_compatible (EF_ARM_EABI_VERSION (in_flags),
18449 EF_ARM_EABI_VERSION (out_flags)))
18450 {
18451 _bfd_error_handler
18452 (_("error: Source object %B has EABI version %d, but target %B has EABI version %d"),
18453 ibfd, obfd,
18454 (in_flags & EF_ARM_EABIMASK) >> 24,
18455 (out_flags & EF_ARM_EABIMASK) >> 24);
18456 return FALSE;
18457 }
18458
18459 /* Not sure what needs to be checked for EABI versions >= 1. */
18460 /* VxWorks libraries do not use these flags. */
18461 if (get_elf_backend_data (obfd) != &elf32_arm_vxworks_bed
18462 && get_elf_backend_data (ibfd) != &elf32_arm_vxworks_bed
18463 && EF_ARM_EABI_VERSION (in_flags) == EF_ARM_EABI_UNKNOWN)
18464 {
18465 if ((in_flags & EF_ARM_APCS_26) != (out_flags & EF_ARM_APCS_26))
18466 {
18467 _bfd_error_handler
18468 (_("error: %B is compiled for APCS-%d, whereas target %B uses APCS-%d"),
18469 ibfd, obfd,
18470 in_flags & EF_ARM_APCS_26 ? 26 : 32,
18471 out_flags & EF_ARM_APCS_26 ? 26 : 32);
18472 flags_compatible = FALSE;
18473 }
18474
18475 if ((in_flags & EF_ARM_APCS_FLOAT) != (out_flags & EF_ARM_APCS_FLOAT))
18476 {
18477 if (in_flags & EF_ARM_APCS_FLOAT)
18478 _bfd_error_handler
18479 (_("error: %B passes floats in float registers, whereas %B passes them in integer registers"),
18480 ibfd, obfd);
18481 else
18482 _bfd_error_handler
18483 (_("error: %B passes floats in integer registers, whereas %B passes them in float registers"),
18484 ibfd, obfd);
18485
18486 flags_compatible = FALSE;
18487 }
18488
18489 if ((in_flags & EF_ARM_VFP_FLOAT) != (out_flags & EF_ARM_VFP_FLOAT))
18490 {
18491 if (in_flags & EF_ARM_VFP_FLOAT)
18492 _bfd_error_handler
18493 (_("error: %B uses VFP instructions, whereas %B does not"),
18494 ibfd, obfd);
18495 else
18496 _bfd_error_handler
18497 (_("error: %B uses FPA instructions, whereas %B does not"),
18498 ibfd, obfd);
18499
18500 flags_compatible = FALSE;
18501 }
18502
18503 if ((in_flags & EF_ARM_MAVERICK_FLOAT) != (out_flags & EF_ARM_MAVERICK_FLOAT))
18504 {
18505 if (in_flags & EF_ARM_MAVERICK_FLOAT)
18506 _bfd_error_handler
18507 (_("error: %B uses Maverick instructions, whereas %B does not"),
18508 ibfd, obfd);
18509 else
18510 _bfd_error_handler
18511 (_("error: %B does not use Maverick instructions, whereas %B does"),
18512 ibfd, obfd);
18513
18514 flags_compatible = FALSE;
18515 }
18516
18517#ifdef EF_ARM_SOFT_FLOAT
18518 if ((in_flags & EF_ARM_SOFT_FLOAT) != (out_flags & EF_ARM_SOFT_FLOAT))
18519 {
18520 /* We can allow interworking between code that is VFP format
18521 layout, and uses either soft float or integer regs for
18522 passing floating point arguments and results. We already
18523 know that the APCS_FLOAT flags match; similarly for VFP
18524 flags. */
18525 if ((in_flags & EF_ARM_APCS_FLOAT) != 0
18526 || (in_flags & EF_ARM_VFP_FLOAT) == 0)
18527 {
18528 if (in_flags & EF_ARM_SOFT_FLOAT)
18529 _bfd_error_handler
18530 (_("error: %B uses software FP, whereas %B uses hardware FP"),
18531 ibfd, obfd);
18532 else
18533 _bfd_error_handler
18534 (_("error: %B uses hardware FP, whereas %B uses software FP"),
18535 ibfd, obfd);
18536
18537 flags_compatible = FALSE;
18538 }
18539 }
18540#endif
18541
18542 /* Interworking mismatch is only a warning. */
18543 if ((in_flags & EF_ARM_INTERWORK) != (out_flags & EF_ARM_INTERWORK))
18544 {
18545 if (in_flags & EF_ARM_INTERWORK)
18546 {
18547 _bfd_error_handler
18548 (_("Warning: %B supports interworking, whereas %B does not"),
18549 ibfd, obfd);
18550 }
18551 else
18552 {
18553 _bfd_error_handler
18554 (_("Warning: %B does not support interworking, whereas %B does"),
18555 ibfd, obfd);
18556 }
18557 }
18558 }
18559
18560 return flags_compatible;
18561}
18562
18563
906e58ca 18564/* Symbian OS Targets. */
7f266840 18565
906e58ca 18566#undef TARGET_LITTLE_SYM
6d00b590 18567#define TARGET_LITTLE_SYM arm_elf32_symbian_le_vec
906e58ca 18568#undef TARGET_LITTLE_NAME
7f266840 18569#define TARGET_LITTLE_NAME "elf32-littlearm-symbian"
906e58ca 18570#undef TARGET_BIG_SYM
6d00b590 18571#define TARGET_BIG_SYM arm_elf32_symbian_be_vec
906e58ca 18572#undef TARGET_BIG_NAME
7f266840
DJ		 18573#define TARGET_BIG_NAME "elf32-bigarm-symbian"
18574
18575/* Like elf32_arm_link_hash_table_create -- but overrides
18576 appropriately for Symbian OS. */
906e58ca 18577
7f266840
DJ		 18578static struct bfd_link_hash_table *
18579elf32_arm_symbian_link_hash_table_create (bfd *abfd)
18580{
18581 struct bfd_link_hash_table *ret;
18582
18583 ret = elf32_arm_link_hash_table_create (abfd);
18584 if (ret)
18585 {
18586 struct elf32_arm_link_hash_table *htab
18587 = (struct elf32_arm_link_hash_table *)ret;
18588 /* There is no PLT header for Symbian OS. */
18589 htab->plt_header_size = 0;
95720a86
DJ		 18590 /* The PLT entries are each one instruction and one word. */
18591 htab->plt_entry_size = 4 * ARRAY_SIZE (elf32_arm_symbian_plt_entry);
7f266840 18592 htab->symbian_p = 1;
33bfe774
JB		 18593 /* Symbian uses armv5t or above, so use_blx is always true. */
18594 htab->use_blx = 1;
67687978 18595 htab->root.is_relocatable_executable = 1;
7f266840
DJ		 18596 }
18597 return ret;
906e58ca 18598}
7f266840 18599
b35d266b 18600static const struct bfd_elf_special_section
551b43fd 18601elf32_arm_symbian_special_sections[] =
7f266840 18602{
5cd3778d
MM		 18603 /* In a BPABI executable, the dynamic linking sections do not go in
18604 the loadable read-only segment. The post-linker may wish to
18605 refer to these sections, but they are not part of the final
18606 program image. */
0112cd26
NC		 18607 { STRING_COMMA_LEN (".dynamic"), 0, SHT_DYNAMIC, 0 },
18608 { STRING_COMMA_LEN (".dynstr"), 0, SHT_STRTAB, 0 },
18609 { STRING_COMMA_LEN (".dynsym"), 0, SHT_DYNSYM, 0 },
18610 { STRING_COMMA_LEN (".got"), 0, SHT_PROGBITS, 0 },
18611 { STRING_COMMA_LEN (".hash"), 0, SHT_HASH, 0 },
5cd3778d
MM		 18612 /* These sections do not need to be writable as the SymbianOS
18613 postlinker will arrange things so that no dynamic relocation is
18614 required. */
0112cd26
NC		 18615 { STRING_COMMA_LEN (".init_array"), 0, SHT_INIT_ARRAY, SHF_ALLOC },
18616 { STRING_COMMA_LEN (".fini_array"), 0, SHT_FINI_ARRAY, SHF_ALLOC },
18617 { STRING_COMMA_LEN (".preinit_array"), 0, SHT_PREINIT_ARRAY, SHF_ALLOC },
18618 { NULL, 0, 0, 0, 0 }
7f266840
DJ		 18619};
18620
c3c76620 18621static void
906e58ca 18622elf32_arm_symbian_begin_write_processing (bfd *abfd,
a4fd1a8e 18623 struct bfd_link_info *link_info)
c3c76620
MM		 18624{
18625 /* BPABI objects are never loaded directly by an OS kernel; they are
18626 processed by a postlinker first, into an OS-specific format. If
18627 the D_PAGED bit is set on the file, BFD will align segments on
18628 page boundaries, so that an OS can directly map the file. With
18629 BPABI objects, that just results in wasted space. In addition,
18630 because we clear the D_PAGED bit, map_sections_to_segments will
18631 recognize that the program headers should not be mapped into any
18632 loadable segment. */
18633 abfd->flags &= ~D_PAGED;
906e58ca 18634 elf32_arm_begin_write_processing (abfd, link_info);
c3c76620 18635}
7f266840
DJ		 18636
18637static bfd_boolean
906e58ca 18638elf32_arm_symbian_modify_segment_map (bfd *abfd,
b294bdf8 18639 struct bfd_link_info *info)
7f266840
DJ		 18640{
18641 struct elf_segment_map *m;
18642 asection *dynsec;
18643
7f266840
DJ		 18644 /* BPABI shared libraries and executables should have a PT_DYNAMIC
18645 segment. However, because the .dynamic section is not marked
18646 with SEC_LOAD, the generic ELF code will not create such a
18647 segment. */
18648 dynsec = bfd_get_section_by_name (abfd, ".dynamic");
18649 if (dynsec)
18650 {
12bd6957 18651 for (m = elf_seg_map (abfd); m != NULL; m = m->next)
8ded5a0f
AM		 18652 if (m->p_type == PT_DYNAMIC)
18653 break;
18654
18655 if (m == NULL)
18656 {
18657 m = _bfd_elf_make_dynamic_segment (abfd, dynsec);
12bd6957
AM		 18658 m->next = elf_seg_map (abfd);
18659 elf_seg_map (abfd) = m;
8ded5a0f 18660 }
7f266840
DJ		 18661 }
18662
b294bdf8
MM		 18663 /* Also call the generic arm routine. */
18664 return elf32_arm_modify_segment_map (abfd, info);
7f266840
DJ		 18665}
18666
95720a86
DJ		 18667/* Return address for Ith PLT stub in section PLT, for relocation REL
18668 or (bfd_vma) -1 if it should not be included. */
18669
18670static bfd_vma
18671elf32_arm_symbian_plt_sym_val (bfd_vma i, const asection *plt,
18672 const arelent *rel ATTRIBUTE_UNUSED)
18673{
18674 return plt->vma + 4 * ARRAY_SIZE (elf32_arm_symbian_plt_entry) * i;
18675}
18676
8029a119 18677#undef elf32_bed
7f266840
DJ		 18678#define elf32_bed elf32_arm_symbian_bed
18679
18680/* The dynamic sections are not allocated on SymbianOS; the postlinker
18681 will process them and then discard them. */
906e58ca 18682#undef ELF_DYNAMIC_SEC_FLAGS
7f266840
DJ		 18683#define ELF_DYNAMIC_SEC_FLAGS \
18684 (SEC_HAS_CONTENTS | SEC_IN_MEMORY | SEC_LINKER_CREATED)
18685
00a97672 18686#undef elf_backend_emit_relocs
c3c76620 18687
906e58ca
NC		 18688#undef bfd_elf32_bfd_link_hash_table_create
18689#define bfd_elf32_bfd_link_hash_table_create elf32_arm_symbian_link_hash_table_create
18690#undef elf_backend_special_sections
18691#define elf_backend_special_sections elf32_arm_symbian_special_sections
18692#undef elf_backend_begin_write_processing
18693#define elf_backend_begin_write_processing elf32_arm_symbian_begin_write_processing
18694#undef elf_backend_final_write_processing
18695#define elf_backend_final_write_processing elf32_arm_final_write_processing
18696
18697#undef elf_backend_modify_segment_map
7f266840
DJ		 18698#define elf_backend_modify_segment_map elf32_arm_symbian_modify_segment_map
18699
18700/* There is no .got section for BPABI objects, and hence no header. */
906e58ca 18701#undef elf_backend_got_header_size
7f266840
DJ		 18702#define elf_backend_got_header_size 0
18703
18704/* Similarly, there is no .got.plt section. */
906e58ca 18705#undef elf_backend_want_got_plt
7f266840
DJ		 18706#define elf_backend_want_got_plt 0
18707
906e58ca 18708#undef elf_backend_plt_sym_val
95720a86
DJ		 18709#define elf_backend_plt_sym_val elf32_arm_symbian_plt_sym_val
18710
906e58ca 18711#undef elf_backend_may_use_rel_p
00a97672 18712#define elf_backend_may_use_rel_p 1
906e58ca 18713#undef elf_backend_may_use_rela_p
00a97672 18714#define elf_backend_may_use_rela_p 0
906e58ca 18715#undef elf_backend_default_use_rela_p
00a97672 18716#define elf_backend_default_use_rela_p 0
906e58ca 18717#undef elf_backend_want_plt_sym
00a97672 18718#define elf_backend_want_plt_sym 0
906e58ca 18719#undef ELF_MAXPAGESIZE
00a97672 18720#define ELF_MAXPAGESIZE 0x8000
4e7fd91e 18721
7f266840 18722#include "elf32-target.h"
GDB Binutils - Deliverables
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