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unrecognized/unsupported reloc message
[deliverable/binutils-gdb.git] / bfd / elf32-m68hc11.c
CommitLineData
60bcf0fa 1/* Motorola 68HC11-specific support for 32-bit ELF
219d1afa 2 Copyright (C) 1999-2018 Free Software Foundation, Inc.
dae78fb0 3 Contributed by Stephane Carrez (stcarrez@nerim.fr)
60bcf0fa
NC		 4 (Heavily copied from the D10V port by Martin Hunt (hunt@cygnus.com))
5
cd123cb7 6 This file is part of BFD, the Binary File Descriptor library.
60bcf0fa 7
cd123cb7
NC		 8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the License, or
11 (at your option) any later version.
60bcf0fa 12
cd123cb7
NC		 13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
60bcf0fa 17
cd123cb7
NC		 18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software
20 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
21 MA 02110-1301, USA. */
60bcf0fa 22
60bcf0fa 23#include "sysdep.h"
3db64b00 24#include "bfd.h"
1fd03b5a 25#include "bfdlink.h"
60bcf0fa
NC		 26#include "libbfd.h"
27#include "elf-bfd.h"
3a65329d 28#include "elf32-m68hc1x.h"
60bcf0fa 29#include "elf/m68hc11.h"
3a65329d 30#include "opcode/m68hc11.h"
60bcf0fa 31
3a65329d 32/* Relocation functions. */
60bcf0fa 33static reloc_howto_type *bfd_elf32_bfd_reloc_type_lookup
0a6a3ebe 34 (bfd *, bfd_reloc_code_real_type);
60bcf0fa 35static void m68hc11_info_to_howto_rel
0a6a3ebe 36 (bfd *, arelent *, Elf_Internal_Rela *);
60bcf0fa 37
3a65329d
SC		 38/* Trampoline generation. */
39static bfd_boolean m68hc11_elf_size_one_stub
0a6a3ebe 40 (struct bfd_hash_entry *gen_entry, void *in_arg);
3a65329d 41static bfd_boolean m68hc11_elf_build_one_stub
0a6a3ebe 42 (struct bfd_hash_entry *gen_entry, void *in_arg);
3a65329d 43static struct bfd_link_hash_table* m68hc11_elf_bfd_link_hash_table_create
0a6a3ebe 44 (bfd* abfd);
3a65329d
SC		 45
46/* Linker relaxation. */
b34976b6 47static bfd_boolean m68hc11_elf_relax_section
0a6a3ebe 48 (bfd *, asection *, struct bfd_link_info *, bfd_boolean *);
1fd03b5a 49static void m68hc11_elf_relax_delete_bytes
0a6a3ebe 50 (bfd *, asection *, bfd_vma, int);
1fd03b5a 51static void m68hc11_relax_group
0a6a3ebe
SC		 52 (bfd *, asection *, bfd_byte *, unsigned, unsigned long, unsigned long);
53static int compare_reloc (const void *, const void *);
1fd03b5a 54
60bcf0fa 55/* Use REL instead of RELA to save space */
acf8aed4 56#define USE_REL 1
60bcf0fa 57
3a65329d
SC		 58/* The Motorola 68HC11 microcontroller only addresses 64Kb but we also
59 support a memory bank switching mechanism similar to 68HC12.
60bcf0fa 60 We must handle 8 and 16-bit relocations. The 32-bit relocation
3a65329d
SC		 61 are used for debugging sections (DWARF2) to represent a virtual
62 address.
60bcf0fa
NC		 63 The 3-bit and 16-bit PC rel relocation is only used by 68HC12. */
64static reloc_howto_type elf_m68hc11_howto_table[] = {
65 /* This reloc does nothing. */
66 HOWTO (R_M68HC11_NONE, /* type */
67 0, /* rightshift */
6346d5ca
AM		 68 3, /* size (0 = byte, 1 = short, 2 = long) */
69 0, /* bitsize */
b34976b6 70 FALSE, /* pc_relative */
60bcf0fa 71 0, /* bitpos */
7a897be4 72 complain_overflow_dont,/* complain_on_overflow */
60bcf0fa
NC		 73 bfd_elf_generic_reloc, /* special_function */
74 "R_M68HC11_NONE", /* name */
b34976b6 75 FALSE, /* partial_inplace */
60bcf0fa
NC		 76 0, /* src_mask */
77 0, /* dst_mask */
b34976b6 78 FALSE), /* pcrel_offset */
60bcf0fa
NC		 79
80 /* A 8 bit absolute relocation */
81 HOWTO (R_M68HC11_8, /* type */
82 0, /* rightshift */
83 0, /* size (0 = byte, 1 = short, 2 = long) */
84 8, /* bitsize */
b34976b6 85 FALSE, /* pc_relative */
60bcf0fa
NC		 86 0, /* bitpos */
87 complain_overflow_bitfield, /* complain_on_overflow */
88 bfd_elf_generic_reloc, /* special_function */
89 "R_M68HC11_8", /* name */
b34976b6 90 FALSE, /* partial_inplace */
60bcf0fa
NC		 91 0x00ff, /* src_mask */
92 0x00ff, /* dst_mask */
b34976b6 93 FALSE), /* pcrel_offset */
60bcf0fa
NC		 94
95 /* A 8 bit absolute relocation (upper address) */
96 HOWTO (R_M68HC11_HI8, /* type */
97 8, /* rightshift */
98 0, /* size (0 = byte, 1 = short, 2 = long) */
99 8, /* bitsize */
b34976b6 100 FALSE, /* pc_relative */
60bcf0fa
NC		 101 0, /* bitpos */
102 complain_overflow_bitfield, /* complain_on_overflow */
103 bfd_elf_generic_reloc, /* special_function */
104 "R_M68HC11_HI8", /* name */
b34976b6 105 FALSE, /* partial_inplace */
60bcf0fa
NC		 106 0x00ff, /* src_mask */
107 0x00ff, /* dst_mask */
b34976b6 108 FALSE), /* pcrel_offset */
60bcf0fa
NC		 109
110 /* A 8 bit absolute relocation (upper address) */
111 HOWTO (R_M68HC11_LO8, /* type */
112 0, /* rightshift */
113 0, /* size (0 = byte, 1 = short, 2 = long) */
114 8, /* bitsize */
b34976b6 115 FALSE, /* pc_relative */
60bcf0fa
NC		 116 0, /* bitpos */
117 complain_overflow_dont, /* complain_on_overflow */
118 bfd_elf_generic_reloc, /* special_function */
119 "R_M68HC11_LO8", /* name */
b34976b6 120 FALSE, /* partial_inplace */
60bcf0fa
NC		 121 0x00ff, /* src_mask */
122 0x00ff, /* dst_mask */
b34976b6 123 FALSE), /* pcrel_offset */
60bcf0fa
NC		 124
125 /* A 8 bit PC-rel relocation */
126 HOWTO (R_M68HC11_PCREL_8, /* type */
127 0, /* rightshift */
128 0, /* size (0 = byte, 1 = short, 2 = long) */
129 8, /* bitsize */
b34976b6 130 TRUE, /* pc_relative */
60bcf0fa
NC		 131 0, /* bitpos */
132 complain_overflow_bitfield, /* complain_on_overflow */
133 bfd_elf_generic_reloc, /* special_function */
134 "R_M68HC11_PCREL_8", /* name */
b34976b6 135 FALSE, /* partial_inplace */
dae78fb0 136 0x00ff, /* src_mask */
60bcf0fa 137 0x00ff, /* dst_mask */
07d6d2b8 138 TRUE), /* pcrel_offset */
60bcf0fa
NC		 139
140 /* A 16 bit absolute relocation */
141 HOWTO (R_M68HC11_16, /* type */
142 0, /* rightshift */
143 1, /* size (0 = byte, 1 = short, 2 = long) */
144 16, /* bitsize */
b34976b6 145 FALSE, /* pc_relative */
60bcf0fa
NC		 146 0, /* bitpos */
147 complain_overflow_dont /*bitfield */ , /* complain_on_overflow */
148 bfd_elf_generic_reloc, /* special_function */
149 "R_M68HC11_16", /* name */
b34976b6 150 FALSE, /* partial_inplace */
60bcf0fa
NC		 151 0xffff, /* src_mask */
152 0xffff, /* dst_mask */
b34976b6 153 FALSE), /* pcrel_offset */
60bcf0fa
NC		 154
155 /* A 32 bit absolute relocation. This one is never used for the
156 code relocation. It's used by gas for -gstabs generation. */
157 HOWTO (R_M68HC11_32, /* type */
158 0, /* rightshift */
159 2, /* size (0 = byte, 1 = short, 2 = long) */
160 32, /* bitsize */
b34976b6 161 FALSE, /* pc_relative */
60bcf0fa
NC		 162 0, /* bitpos */
163 complain_overflow_bitfield, /* complain_on_overflow */
164 bfd_elf_generic_reloc, /* special_function */
165 "R_M68HC11_32", /* name */
b34976b6 166 FALSE, /* partial_inplace */
60bcf0fa
NC		 167 0xffffffff, /* src_mask */
168 0xffffffff, /* dst_mask */
b34976b6 169 FALSE), /* pcrel_offset */
60bcf0fa
NC		 170
171 /* A 3 bit absolute relocation */
172 HOWTO (R_M68HC11_3B, /* type */
173 0, /* rightshift */
174 0, /* size (0 = byte, 1 = short, 2 = long) */
175 3, /* bitsize */
b34976b6 176 FALSE, /* pc_relative */
60bcf0fa
NC		 177 0, /* bitpos */
178 complain_overflow_bitfield, /* complain_on_overflow */
179 bfd_elf_generic_reloc, /* special_function */
180 "R_M68HC11_4B", /* name */
b34976b6 181 FALSE, /* partial_inplace */
60bcf0fa
NC		 182 0x003, /* src_mask */
183 0x003, /* dst_mask */
b34976b6 184 FALSE), /* pcrel_offset */
60bcf0fa
NC		 185
186 /* A 16 bit PC-rel relocation */
187 HOWTO (R_M68HC11_PCREL_16, /* type */
188 0, /* rightshift */
189 1, /* size (0 = byte, 1 = short, 2 = long) */
190 16, /* bitsize */
b34976b6 191 TRUE, /* pc_relative */
60bcf0fa
NC		 192 0, /* bitpos */
193 complain_overflow_dont, /* complain_on_overflow */
194 bfd_elf_generic_reloc, /* special_function */
195 "R_M68HC11_PCREL_16", /* name */
b34976b6 196 FALSE, /* partial_inplace */
dae78fb0 197 0xffff, /* src_mask */
60bcf0fa 198 0xffff, /* dst_mask */
07d6d2b8 199 TRUE), /* pcrel_offset */
60bcf0fa
NC		 200
201 /* GNU extension to record C++ vtable hierarchy */
202 HOWTO (R_M68HC11_GNU_VTINHERIT, /* type */
203 0, /* rightshift */
204 1, /* size (0 = byte, 1 = short, 2 = long) */
205 0, /* bitsize */
b34976b6 206 FALSE, /* pc_relative */
60bcf0fa
NC		 207 0, /* bitpos */
208 complain_overflow_dont, /* complain_on_overflow */
209 NULL, /* special_function */
210 "R_M68HC11_GNU_VTINHERIT", /* name */
b34976b6 211 FALSE, /* partial_inplace */
60bcf0fa
NC		 212 0, /* src_mask */
213 0, /* dst_mask */
b34976b6 214 FALSE), /* pcrel_offset */
60bcf0fa
NC		 215
216 /* GNU extension to record C++ vtable member usage */
217 HOWTO (R_M68HC11_GNU_VTENTRY, /* type */
218 0, /* rightshift */
219 1, /* size (0 = byte, 1 = short, 2 = long) */
220 0, /* bitsize */
b34976b6 221 FALSE, /* pc_relative */
60bcf0fa
NC		 222 0, /* bitpos */
223 complain_overflow_dont, /* complain_on_overflow */
224 _bfd_elf_rel_vtable_reloc_fn, /* special_function */
225 "R_M68HC11_GNU_VTENTRY", /* name */
b34976b6 226 FALSE, /* partial_inplace */
60bcf0fa
NC		 227 0, /* src_mask */
228 0, /* dst_mask */
b34976b6 229 FALSE), /* pcrel_offset */
dae78fb0 230
7a897be4 231 /* A 24 bit relocation */
07d6d2b8 232 HOWTO (R_M68HC11_24, /* type */
7a897be4
SC		 233 0, /* rightshift */
234 1, /* size (0 = byte, 1 = short, 2 = long) */
235 24, /* bitsize */
b34976b6 236 FALSE, /* pc_relative */
7a897be4
SC		 237 0, /* bitpos */
238 complain_overflow_bitfield, /* complain_on_overflow */
239 bfd_elf_generic_reloc, /* special_function */
240 "R_M68HC11_24", /* name */
b34976b6 241 FALSE, /* partial_inplace */
196486be
SC		 242 0xffffff, /* src_mask */
243 0xffffff, /* dst_mask */
b34976b6
AM		 244 FALSE), /* pcrel_offset */
245
7a897be4 246 /* A 16-bit low relocation */
07d6d2b8 247 HOWTO (R_M68HC11_LO16, /* type */
7a897be4
SC		 248 0, /* rightshift */
249 1, /* size (0 = byte, 1 = short, 2 = long) */
250 16, /* bitsize */
b34976b6 251 FALSE, /* pc_relative */
7a897be4
SC		 252 0, /* bitpos */
253 complain_overflow_bitfield, /* complain_on_overflow */
254 bfd_elf_generic_reloc, /* special_function */
255 "R_M68HC11_LO16", /* name */
b34976b6 256 FALSE, /* partial_inplace */
7a897be4
SC		 257 0xffff, /* src_mask */
258 0xffff, /* dst_mask */
b34976b6 259 FALSE), /* pcrel_offset */
7a897be4
SC		 260
261 /* A page relocation */
07d6d2b8 262 HOWTO (R_M68HC11_PAGE, /* type */
7a897be4
SC		 263 0, /* rightshift */
264 0, /* size (0 = byte, 1 = short, 2 = long) */
265 8, /* bitsize */
b34976b6 266 FALSE, /* pc_relative */
7a897be4
SC		 267 0, /* bitpos */
268 complain_overflow_bitfield, /* complain_on_overflow */
269 bfd_elf_generic_reloc, /* special_function */
270 "R_M68HC11_PAGE", /* name */
b34976b6 271 FALSE, /* partial_inplace */
7a897be4
SC		 272 0x00ff, /* src_mask */
273 0x00ff, /* dst_mask */
b34976b6 274 FALSE), /* pcrel_offset */
7a897be4 275
dae78fb0
SC		 276 EMPTY_HOWTO (14),
277 EMPTY_HOWTO (15),
278 EMPTY_HOWTO (16),
279 EMPTY_HOWTO (17),
280 EMPTY_HOWTO (18),
281 EMPTY_HOWTO (19),
b34976b6 282
dae78fb0
SC		 283 /* Mark beginning of a jump instruction (any form). */
284 HOWTO (R_M68HC11_RL_JUMP, /* type */
285 0, /* rightshift */
286 1, /* size (0 = byte, 1 = short, 2 = long) */
287 0, /* bitsize */
b34976b6 288 FALSE, /* pc_relative */
dae78fb0
SC		 289 0, /* bitpos */
290 complain_overflow_dont, /* complain_on_overflow */
291 m68hc11_elf_ignore_reloc, /* special_function */
292 "R_M68HC11_RL_JUMP", /* name */
b34976b6 293 TRUE, /* partial_inplace */
dae78fb0
SC		 294 0, /* src_mask */
295 0, /* dst_mask */
07d6d2b8 296 TRUE), /* pcrel_offset */
dae78fb0
SC		 297
298 /* Mark beginning of Gcc relaxation group instruction. */
299 HOWTO (R_M68HC11_RL_GROUP, /* type */
300 0, /* rightshift */
301 1, /* size (0 = byte, 1 = short, 2 = long) */
302 0, /* bitsize */
b34976b6 303 FALSE, /* pc_relative */
dae78fb0
SC		 304 0, /* bitpos */
305 complain_overflow_dont, /* complain_on_overflow */
306 m68hc11_elf_ignore_reloc, /* special_function */
307 "R_M68HC11_RL_GROUP", /* name */
b34976b6 308 TRUE, /* partial_inplace */
dae78fb0
SC		 309 0, /* src_mask */
310 0, /* dst_mask */
07d6d2b8 311 TRUE), /* pcrel_offset */
60bcf0fa
NC		 312};
313
314/* Map BFD reloc types to M68HC11 ELF reloc types. */
315
316struct m68hc11_reloc_map
317{
318 bfd_reloc_code_real_type bfd_reloc_val;
319 unsigned char elf_reloc_val;
320};
321
322static const struct m68hc11_reloc_map m68hc11_reloc_map[] = {
323 {BFD_RELOC_NONE, R_M68HC11_NONE,},
324 {BFD_RELOC_8, R_M68HC11_8},
325 {BFD_RELOC_M68HC11_HI8, R_M68HC11_HI8},
326 {BFD_RELOC_M68HC11_LO8, R_M68HC11_LO8},
327 {BFD_RELOC_8_PCREL, R_M68HC11_PCREL_8},
328 {BFD_RELOC_16_PCREL, R_M68HC11_PCREL_16},
329 {BFD_RELOC_16, R_M68HC11_16},
330 {BFD_RELOC_32, R_M68HC11_32},
331 {BFD_RELOC_M68HC11_3B, R_M68HC11_3B},
332
60bcf0fa
NC		 333 {BFD_RELOC_VTABLE_INHERIT, R_M68HC11_GNU_VTINHERIT},
334 {BFD_RELOC_VTABLE_ENTRY, R_M68HC11_GNU_VTENTRY},
dae78fb0 335
7a897be4
SC		 336 {BFD_RELOC_M68HC11_LO16, R_M68HC11_LO16},
337 {BFD_RELOC_M68HC11_PAGE, R_M68HC11_PAGE},
338 {BFD_RELOC_M68HC11_24, R_M68HC11_24},
339
dae78fb0
SC		 340 {BFD_RELOC_M68HC11_RL_JUMP, R_M68HC11_RL_JUMP},
341 {BFD_RELOC_M68HC11_RL_GROUP, R_M68HC11_RL_GROUP},
60bcf0fa
NC		 342};
343
344static reloc_howto_type *
0a6a3ebe 345bfd_elf32_bfd_reloc_type_lookup (bfd *abfd ATTRIBUTE_UNUSED,
07d6d2b8 346 bfd_reloc_code_real_type code)
60bcf0fa
NC		 347{
348 unsigned int i;
349
350 for (i = 0;
351 i < sizeof (m68hc11_reloc_map) / sizeof (struct m68hc11_reloc_map);
352 i++)
353 {
354 if (m68hc11_reloc_map[i].bfd_reloc_val == code)
355 return &elf_m68hc11_howto_table[m68hc11_reloc_map[i].elf_reloc_val];
356 }
357
358 return NULL;
359}
360
157090f7
AM		 361static reloc_howto_type *
362bfd_elf32_bfd_reloc_name_lookup (bfd *abfd ATTRIBUTE_UNUSED,
363 const char *r_name)
364{
365 unsigned int i;
366
367 for (i = 0;
368 i < (sizeof (elf_m68hc11_howto_table)
369 / sizeof (elf_m68hc11_howto_table[0]));
370 i++)
371 if (elf_m68hc11_howto_table[i].name != NULL
372 && strcasecmp (elf_m68hc11_howto_table[i].name, r_name) == 0)
373 return &elf_m68hc11_howto_table[i];
374
375 return NULL;
376}
377
60bcf0fa
NC		 378/* Set the howto pointer for an M68HC11 ELF reloc. */
379
380static void
0aa13fee 381m68hc11_info_to_howto_rel (bfd *abfd,
07d6d2b8 382 arelent *cache_ptr, Elf_Internal_Rela *dst)
60bcf0fa
NC		 383{
384 unsigned int r_type;
385
386 r_type = ELF32_R_TYPE (dst->r_info);
5860e3f8
NC		 387 if (r_type >= (unsigned int) R_M68HC11_max)
388 {
695344c0 389 /* xgettext:c-format */
0aa13fee
AM		 390 _bfd_error_handler (_("%pB: unsupported relocation type %#x"),
391 abfd, r_type);
5860e3f8
NC		 392 r_type = 0;
393 }
60bcf0fa
NC		 394 cache_ptr->howto = &elf_m68hc11_howto_table[r_type];
395}
396
3a65329d
SC		 397\f
398/* Far trampoline generation. */
9b701e44 399
3a65329d
SC		 400/* Build a 68HC11 trampoline stub. */
401static bfd_boolean
0a6a3ebe 402m68hc11_elf_build_one_stub (struct bfd_hash_entry *gen_entry, void *in_arg)
3a65329d
SC		 403{
404 struct elf32_m68hc11_stub_hash_entry *stub_entry;
405 struct bfd_link_info *info;
406 struct m68hc11_elf_link_hash_table *htab;
407 asection *stub_sec;
408 bfd *stub_bfd;
409 bfd_byte *loc;
410 bfd_vma sym_value, phys_page, phys_addr;
411
412 /* Massage our args to the form they really have. */
413 stub_entry = (struct elf32_m68hc11_stub_hash_entry *) gen_entry;
414 info = (struct bfd_link_info *) in_arg;
415
416 htab = m68hc11_elf_hash_table (info);
4dfe6ac6
NC		 417 if (htab == NULL)
418 return FALSE;
3a65329d
SC		 419
420 stub_sec = stub_entry->stub_sec;
421
422 /* Make a note of the offset within the stubs for this entry. */
eea6121a
AM		 423 stub_entry->stub_offset = stub_sec->size;
424 stub_sec->size += 10;
3a65329d
SC		 425 loc = stub_sec->contents + stub_entry->stub_offset;
426
427 stub_bfd = stub_sec->owner;
428
429 /* Create the trampoline call stub:
430
431 pshb
432 ldab #%page(symbol)
433 ldy #%addr(symbol)
434 jmp __trampoline
435
436 */
437 sym_value = (stub_entry->target_value
07d6d2b8
AM		 438 + stub_entry->target_section->output_offset
439 + stub_entry->target_section->output_section->vma);
3a65329d
SC		 440 phys_addr = m68hc11_phys_addr (&htab->pinfo, sym_value);
441 phys_page = m68hc11_phys_page (&htab->pinfo, sym_value);
442
443 /* pshb; ldab #%page(sym) */
444 bfd_put_8 (stub_bfd, 0x37, loc);
445 bfd_put_8 (stub_bfd, 0xC6, loc + 1);
446 bfd_put_8 (stub_bfd, phys_page, loc + 2);
447 loc += 3;
448
449 /* ldy #%addr(sym) */
450 bfd_put_8 (stub_bfd, 0x18, loc);
451 bfd_put_8 (stub_bfd, 0xCE, loc + 1);
452 bfd_put_16 (stub_bfd, phys_addr, loc + 2);
453 loc += 4;
454
455 /* jmp __trampoline */
456 bfd_put_8 (stub_bfd, 0x7E, loc);
457 bfd_put_16 (stub_bfd, htab->pinfo.trampoline_addr, loc + 1);
56780f18 458
3a65329d 459 return TRUE;
9b701e44
SC		 460}
461
3a65329d
SC		 462/* As above, but don't actually build the stub. Just bump offset so
463 we know stub section sizes. */
464
b34976b6 465static bfd_boolean
0a6a3ebe 466m68hc11_elf_size_one_stub (struct bfd_hash_entry *gen_entry,
07d6d2b8 467 void *in_arg ATTRIBUTE_UNUSED)
9b701e44 468{
3a65329d
SC		 469 struct elf32_m68hc11_stub_hash_entry *stub_entry;
470
471 /* Massage our args to the form they really have. */
472 stub_entry = (struct elf32_m68hc11_stub_hash_entry *) gen_entry;
473
eea6121a 474 stub_entry->stub_sec->size += 10;
b34976b6 475 return TRUE;
9b701e44
SC		 476}
477
3a65329d
SC		 478/* Create a 68HC11 ELF linker hash table. */
479
480static struct bfd_link_hash_table *
0a6a3ebe 481m68hc11_elf_bfd_link_hash_table_create (bfd *abfd)
3a65329d
SC		 482{
483 struct m68hc11_elf_link_hash_table *ret;
484
485 ret = m68hc11_elf_hash_table_create (abfd);
486 if (ret == (struct m68hc11_elf_link_hash_table *) NULL)
487 return NULL;
488
489 ret->size_one_stub = m68hc11_elf_size_one_stub;
490 ret->build_one_stub = m68hc11_elf_build_one_stub;
491
492 return &ret->root.root;
493}
494
196486be
SC		 495\f
496/* 68HC11 Linker Relaxation. */
497
b34976b6 498struct m68hc11_direct_relax
1fd03b5a
SC		 499{
500 const char *name;
501 unsigned char code;
502 unsigned char direct_code;
503} m68hc11_direct_relax_table[] = {
504 { "adca", 0xB9, 0x99 },
505 { "adcb", 0xF9, 0xD9 },
506 { "adda", 0xBB, 0x9B },
507 { "addb", 0xFB, 0xDB },
508 { "addd", 0xF3, 0xD3 },
509 { "anda", 0xB4, 0x94 },
510 { "andb", 0xF4, 0xD4 },
511 { "cmpa", 0xB1, 0x91 },
512 { "cmpb", 0xF1, 0xD1 },
513 { "cpd", 0xB3, 0x93 },
514 { "cpxy", 0xBC, 0x9C },
515/* { "cpy", 0xBC, 0x9C }, */
516 { "eora", 0xB8, 0x98 },
517 { "eorb", 0xF8, 0xD8 },
518 { "jsr", 0xBD, 0x9D },
519 { "ldaa", 0xB6, 0x96 },
520 { "ldab", 0xF6, 0xD6 },
521 { "ldd", 0xFC, 0xDC },
522 { "lds", 0xBE, 0x9E },
523 { "ldxy", 0xFE, 0xDE },
524 /* { "ldy", 0xFE, 0xDE },*/
525 { "oraa", 0xBA, 0x9A },
526 { "orab", 0xFA, 0xDA },
527 { "sbca", 0xB2, 0x92 },
528 { "sbcb", 0xF2, 0xD2 },
529 { "staa", 0xB7, 0x97 },
530 { "stab", 0xF7, 0xD7 },
531 { "std", 0xFD, 0xDD },
532 { "sts", 0xBF, 0x9F },
533 { "stxy", 0xFF, 0xDF },
534 /* { "sty", 0xFF, 0xDF },*/
535 { "suba", 0xB0, 0x90 },
536 { "subb", 0xF0, 0xD0 },
537 { "subd", 0xB3, 0x93 },
538 { 0, 0, 0 }
539};
540
541static struct m68hc11_direct_relax *
542find_relaxable_insn (unsigned char code)
543{
544 int i;
545
546 for (i = 0; m68hc11_direct_relax_table[i].name; i++)
547 if (m68hc11_direct_relax_table[i].code == code)
548 return &m68hc11_direct_relax_table[i];
549
550 return 0;
551}
552
553static int
0a6a3ebe 554compare_reloc (const void *e1, const void *e2)
1fd03b5a
SC		 555{
556 const Elf_Internal_Rela *i1 = (const Elf_Internal_Rela *) e1;
557 const Elf_Internal_Rela *i2 = (const Elf_Internal_Rela *) e2;
558
559 if (i1->r_offset == i2->r_offset)
560 return 0;
561 else
562 return i1->r_offset < i2->r_offset ? -1 : 1;
563}
564
565#define M6811_OP_LDX_IMMEDIATE (0xCE)
566
567static void
0a6a3ebe 568m68hc11_relax_group (bfd *abfd, asection *sec, bfd_byte *contents,
07d6d2b8
AM		 569 unsigned value, unsigned long offset,
570 unsigned long end_group)
1fd03b5a
SC		 571{
572 unsigned char code;
573 unsigned long start_offset;
574 unsigned long ldx_offset = offset;
575 unsigned long ldx_size;
576 int can_delete_ldx;
577 int relax_ldy = 0;
578
579 /* First instruction of the relax group must be a
580 LDX #value or LDY #value. If this is not the case,
581 ignore the relax group. */
582 code = bfd_get_8 (abfd, contents + offset);
583 if (code == 0x18)
584 {
585 relax_ldy++;
586 offset++;
587 code = bfd_get_8 (abfd, contents + offset);
588 }
589 ldx_size = offset - ldx_offset + 3;
590 offset += 3;
591 if (code != M6811_OP_LDX_IMMEDIATE || offset >= end_group)
592 return;
593
594
595 /* We can remove the LDX/LDY only when all bset/brclr instructions
596 of the relax group have been converted to use direct addressing
597 mode. */
598 can_delete_ldx = 1;
599 while (offset < end_group)
600 {
601 unsigned isize;
602 unsigned new_value;
603 int bset_use_y;
604
605 bset_use_y = 0;
606 start_offset = offset;
607 code = bfd_get_8 (abfd, contents + offset);
608 if (code == 0x18)
07d6d2b8
AM		 609 {
610 bset_use_y++;
611 offset++;
612 code = bfd_get_8 (abfd, contents + offset);
613 }
1fd03b5a
SC		 614
615 /* Check the instruction and translate to use direct addressing mode. */
616 switch (code)
07d6d2b8
AM		 617 {
618 /* bset */
619 case 0x1C:
620 code = 0x14;
621 isize = 3;
622 break;
623
624 /* brclr */
625 case 0x1F:
626 code = 0x13;
627 isize = 4;
628 break;
629
630 /* brset */
631 case 0x1E:
632 code = 0x12;
633 isize = 4;
634 break;
635
636 /* bclr */
637 case 0x1D:
638 code = 0x15;
639 isize = 3;
640 break;
641
642 /* This instruction is not recognized and we are not
643 at end of the relax group. Ignore and don't remove
644 the first LDX (we don't know what it is used for...). */
645 default:
646 return;
647 }
1fd03b5a
SC		 648 new_value = (unsigned) bfd_get_8 (abfd, contents + offset + 1);
649 new_value += value;
650 if ((new_value & 0xff00) == 0 && bset_use_y == relax_ldy)
07d6d2b8
AM		 651 {
652 bfd_put_8 (abfd, code, contents + offset);
653 bfd_put_8 (abfd, new_value, contents + offset + 1);
654 if (start_offset != offset)
655 {
656 m68hc11_elf_relax_delete_bytes (abfd, sec, start_offset,
657 offset - start_offset);
658 end_group--;
659 }
660 }
1fd03b5a 661 else
07d6d2b8
AM		 662 {
663 can_delete_ldx = 0;
664 }
1fd03b5a
SC		 665 offset = start_offset + isize;
666 }
667 if (can_delete_ldx)
668 {
669 /* Remove the move instruction (3 or 4 bytes win). */
670 m68hc11_elf_relax_delete_bytes (abfd, sec, ldx_offset, ldx_size);
671 }
672}
673
674/* This function handles relaxing for the 68HC11.
675
b34976b6 676
1fd03b5a
SC		 677 and somewhat more difficult to support. */
678
b34976b6 679static bfd_boolean
0a6a3ebe 680m68hc11_elf_relax_section (bfd *abfd, asection *sec,
07d6d2b8 681 struct bfd_link_info *link_info, bfd_boolean *again)
1fd03b5a
SC		 682{
683 Elf_Internal_Shdr *symtab_hdr;
1fd03b5a
SC		 684 Elf_Internal_Rela *internal_relocs;
685 Elf_Internal_Rela *free_relocs = NULL;
686 Elf_Internal_Rela *irel, *irelend;
687 bfd_byte *contents = NULL;
688 bfd_byte *free_contents = NULL;
1fd03b5a
SC		 689 Elf32_External_Sym *free_extsyms = NULL;
690 Elf_Internal_Rela *prev_insn_branch = NULL;
691 Elf_Internal_Rela *prev_insn_group = NULL;
692 unsigned insn_group_value = 0;
1f4c5b47 693 Elf_Internal_Sym *isymbuf = NULL;
1fd03b5a
SC		 694
695 /* Assume nothing changes. */
b34976b6 696 *again = FALSE;
1fd03b5a 697
1049f94e 698 /* We don't have to do anything for a relocatable link, if
1fd03b5a
SC		 699 this section does not have relocs, or if this is not a
700 code section. */
0e1862bb 701 if (bfd_link_relocatable (link_info)
1fd03b5a
SC		 702 || (sec->flags & SEC_RELOC) == 0
703 || sec->reloc_count == 0
704 || (sec->flags & SEC_CODE) == 0)
b34976b6 705 return TRUE;
1fd03b5a 706
1fd03b5a 707 symtab_hdr = &elf_tdata (abfd)->symtab_hdr;
1fd03b5a
SC		 708
709 /* Get a copy of the native relocations. */
45d6a902 710 internal_relocs = (_bfd_elf_link_read_relocs
2c3fc389 711 (abfd, sec, NULL, (Elf_Internal_Rela *) NULL,
1fd03b5a
SC		 712 link_info->keep_memory));
713 if (internal_relocs == NULL)
714 goto error_return;
715 if (! link_info->keep_memory)
716 free_relocs = internal_relocs;
717
718 /* Checking for branch relaxation relies on the relocations to
719 be sorted on 'r_offset'. This is not guaranteed so we must sort. */
720 qsort (internal_relocs, sec->reloc_count, sizeof (Elf_Internal_Rela),
07d6d2b8 721 compare_reloc);
1fd03b5a
SC		 722
723 /* Walk through them looking for relaxing opportunities. */
724 irelend = internal_relocs + sec->reloc_count;
725 for (irel = internal_relocs; irel < irelend; irel++)
726 {
727 bfd_vma symval;
728 bfd_vma value;
1f4c5b47 729 Elf_Internal_Sym *isym;
9b691193 730 asection *sym_sec;
196486be 731 int is_far = 0;
1fd03b5a
SC		 732
733 /* If this isn't something that can be relaxed, then ignore
734 this reloc. */
735 if (ELF32_R_TYPE (irel->r_info) != (int) R_M68HC11_16
07d6d2b8
AM		 736 && ELF32_R_TYPE (irel->r_info) != (int) R_M68HC11_RL_JUMP
737 && ELF32_R_TYPE (irel->r_info) != (int) R_M68HC11_RL_GROUP)
738 {
739 prev_insn_branch = 0;
740 prev_insn_group = 0;
741 continue;
742 }
1fd03b5a
SC		 743
744 /* Get the section contents if we haven't done so already. */
745 if (contents == NULL)
746 {
747 /* Get cached copy if it exists. */
748 if (elf_section_data (sec)->this_hdr.contents != NULL)
749 contents = elf_section_data (sec)->this_hdr.contents;
750 else
751 {
752 /* Go get them off disk. */
eea6121a 753 if (!bfd_malloc_and_get_section (abfd, sec, &contents))
1fd03b5a
SC		 754 goto error_return;
755 }
756 }
757
758 /* Try to eliminate an unconditional 8 bit pc-relative branch
759 which immediately follows a conditional 8 bit pc-relative
760 branch around the unconditional branch.
761
762 original: new:
763 bCC lab1 bCC' lab2
764 bra lab2
765 lab1: lab1:
766
767 This happens when the bCC can't reach lab2 at assembly time,
768 but due to other relaxations it can reach at link time. */
769 if (ELF32_R_TYPE (irel->r_info) == (int) R_M68HC11_RL_JUMP)
770 {
771 Elf_Internal_Rela *nrel;
772 unsigned char code;
07d6d2b8 773 unsigned char roffset;
1fd03b5a 774
07d6d2b8
AM		 775 prev_insn_branch = 0;
776 prev_insn_group = 0;
b34976b6 777
1fd03b5a 778 /* Do nothing if this reloc is the last byte in the section. */
eea6121a 779 if (irel->r_offset + 2 >= sec->size)
1fd03b5a
SC		 780 continue;
781
782 /* See if the next instruction is an unconditional pc-relative
783 branch, more often than not this test will fail, so we
784 test it first to speed things up. */
785 code = bfd_get_8 (abfd, contents + irel->r_offset + 2);
786 if (code != 0x7e)
787 continue;
788
789 /* Also make sure the next relocation applies to the next
790 instruction and that it's a pc-relative 8 bit branch. */
791 nrel = irel + 1;
792 if (nrel == irelend
793 || irel->r_offset + 3 != nrel->r_offset
794 || ELF32_R_TYPE (nrel->r_info) != (int) R_M68HC11_16)
795 continue;
796
797 /* Make sure our destination immediately follows the
798 unconditional branch. */
07d6d2b8
AM		 799 roffset = bfd_get_8 (abfd, contents + irel->r_offset + 1);
800 if (roffset != 3)
801 continue;
1fd03b5a 802
07d6d2b8
AM		 803 prev_insn_branch = irel;
804 prev_insn_group = 0;
805 continue;
806 }
1fd03b5a
SC		 807
808 /* Read this BFD's symbols if we haven't done so already. */
1f4c5b47 809 if (isymbuf == NULL && symtab_hdr->sh_info != 0)
1fd03b5a 810 {
1f4c5b47
SC		 811 isymbuf = (Elf_Internal_Sym *) symtab_hdr->contents;
812 if (isymbuf == NULL)
813 isymbuf = bfd_elf_get_elf_syms (abfd, symtab_hdr,
814 symtab_hdr->sh_info, 0,
815 NULL, NULL, NULL);
816 if (isymbuf == NULL)
817 goto error_return;
1fd03b5a
SC		 818 }
819
820 /* Get the value of the symbol referred to by the reloc. */
821 if (ELF32_R_SYM (irel->r_info) < symtab_hdr->sh_info)
822 {
1fd03b5a 823 /* A local symbol. */
1f4c5b47 824 isym = isymbuf + ELF32_R_SYM (irel->r_info);
07d6d2b8
AM		 825 is_far = isym->st_other & STO_M68HC12_FAR;
826 sym_sec = bfd_section_from_elf_index (abfd, isym->st_shndx);
1f4c5b47 827 symval = (isym->st_value
1fd03b5a
SC		 828 + sym_sec->output_section->vma
829 + sym_sec->output_offset);
830 }
831 else
832 {
833 unsigned long indx;
834 struct elf_link_hash_entry *h;
835
836 /* An external symbol. */
837 indx = ELF32_R_SYM (irel->r_info) - symtab_hdr->sh_info;
838 h = elf_sym_hashes (abfd)[indx];
839 BFD_ASSERT (h != NULL);
840 if (h->root.type != bfd_link_hash_defined
841 && h->root.type != bfd_link_hash_defweak)
842 {
843 /* This appears to be a reference to an undefined
07d6d2b8
AM		 844 symbol. Just ignore it--it will be caught by the
845 regular reloc processing. */
846 prev_insn_branch = 0;
847 prev_insn_group = 0;
1fd03b5a
SC		 848 continue;
849 }
850
07d6d2b8
AM		 851 is_far = h->other & STO_M68HC12_FAR;
852 isym = 0;
853 sym_sec = h->root.u.def.section;
1fd03b5a 854 symval = (h->root.u.def.value
9b691193
SC		 855 + sym_sec->output_section->vma
856 + sym_sec->output_offset);
1fd03b5a
SC		 857 }
858
859 if (ELF32_R_TYPE (irel->r_info) == (int) R_M68HC11_RL_GROUP)
860 {
07d6d2b8
AM		 861 prev_insn_branch = 0;
862 prev_insn_group = 0;
b34976b6 863
1fd03b5a 864 /* Do nothing if this reloc is the last byte in the section. */
eea6121a 865 if (irel->r_offset == sec->size)
1fd03b5a
SC		 866 continue;
867
07d6d2b8
AM		 868 prev_insn_group = irel;
869 insn_group_value = isym->st_value;
870 continue;
871 }
1fd03b5a 872
9b691193 873 /* When we relax some bytes, the size of our section changes.
07d6d2b8
AM		 874 This affects the layout of next input sections that go in our
875 output section. When the symbol is part of another section that
876 will go in the same output section as the current one, it's
877 final address may now be incorrect (too far). We must let the
878 linker re-compute all section offsets before processing this
879 reloc. Code example:
880
881 Initial Final
882 .sect .text section size = 6 section size = 4
883 jmp foo
884 jmp bar
885 .sect .text.foo_bar output_offset = 6 output_offset = 4
886 foo: rts
887 bar: rts
888
889 If we process the reloc now, the jmp bar is replaced by a
890 relative branch to the initial bar address (output_offset 6). */
9b691193 891 if (*again && sym_sec != sec
07d6d2b8
AM		 892 && sym_sec->output_section == sec->output_section)
893 {
894 prev_insn_group = 0;
895 prev_insn_branch = 0;
896 continue;
897 }
b34976b6 898
1fd03b5a
SC		 899 value = symval;
900 /* Try to turn a far branch to a near branch. */
901 if (ELF32_R_TYPE (irel->r_info) == (int) R_M68HC11_16
07d6d2b8
AM		 902 && prev_insn_branch)
903 {
904 bfd_vma offset;
905 unsigned char code;
906
907 offset = value - (prev_insn_branch->r_offset
908 + sec->output_section->vma
909 + sec->output_offset + 2);
910
911 /* If the offset is still out of -128..+127 range,
912 leave that far branch unchanged. */
913 if ((offset & 0xff80) != 0 && (offset & 0xff80) != 0xff80)
914 {
915 prev_insn_branch = 0;
916 continue;
917 }
918
919 /* Shrink the branch. */
920 code = bfd_get_8 (abfd, contents + prev_insn_branch->r_offset);
921 if (code == 0x7e)
922 {
923 code = 0x20;
924 bfd_put_8 (abfd, code, contents + prev_insn_branch->r_offset);
925 bfd_put_8 (abfd, 0xff,
926 contents + prev_insn_branch->r_offset + 1);
927 irel->r_offset = prev_insn_branch->r_offset + 1;
928 irel->r_info = ELF32_R_INFO (ELF32_R_SYM (irel->r_info),
929 R_M68HC11_PCREL_8);
930 m68hc11_elf_relax_delete_bytes (abfd, sec,
931 irel->r_offset + 1, 1);
932 }
933 else
934 {
935 code ^= 0x1;
936 bfd_put_8 (abfd, code, contents + prev_insn_branch->r_offset);
937 bfd_put_8 (abfd, 0xff,
938 contents + prev_insn_branch->r_offset + 1);
939 irel->r_offset = prev_insn_branch->r_offset + 1;
940 irel->r_info = ELF32_R_INFO (ELF32_R_SYM (irel->r_info),
941 R_M68HC11_PCREL_8);
942 m68hc11_elf_relax_delete_bytes (abfd, sec,
943 irel->r_offset + 1, 3);
944 }
945 prev_insn_branch = 0;
946 *again = TRUE;
947 }
1fd03b5a
SC		 948
949 /* Try to turn a 16 bit address into a 8 bit page0 address. */
950 else if (ELF32_R_TYPE (irel->r_info) == (int) R_M68HC11_16
07d6d2b8 951 && (value & 0xff00) == 0)
1fd03b5a 952 {
07d6d2b8
AM		 953 unsigned char code;
954 unsigned short offset;
955 struct m68hc11_direct_relax *rinfo;
956
957 prev_insn_branch = 0;
958 offset = bfd_get_16 (abfd, contents + irel->r_offset);
959 offset += value;
960 if ((offset & 0xff00) != 0)
961 {
962 prev_insn_group = 0;
963 continue;
964 }
965
966 if (prev_insn_group)
967 {
968 unsigned long old_sec_size = sec->size;
969
970 /* Note that we've changed the relocation contents, etc. */
971 elf_section_data (sec)->relocs = internal_relocs;
972 free_relocs = NULL;
973
974 elf_section_data (sec)->this_hdr.contents = contents;
975 free_contents = NULL;
976
977 symtab_hdr->contents = (bfd_byte *) isymbuf;
978 free_extsyms = NULL;
979
980 m68hc11_relax_group (abfd, sec, contents, offset,
981 prev_insn_group->r_offset,
982 insn_group_value);
983 irel = prev_insn_group;
984 prev_insn_group = 0;
985 irel->r_info = ELF32_R_INFO (ELF32_R_SYM (irel->r_info),
986 R_M68HC11_NONE);
987 if (sec->size != old_sec_size)
988 *again = TRUE;
989 continue;
990 }
991
992 /* Get the opcode. */
993 code = bfd_get_8 (abfd, contents + irel->r_offset - 1);
994 rinfo = find_relaxable_insn (code);
995 if (rinfo == 0)
996 {
997 prev_insn_group = 0;
998 continue;
999 }
1000
1001 /* Note that we've changed the relocation contents, etc. */
1002 elf_section_data (sec)->relocs = internal_relocs;
1003 free_relocs = NULL;
1004
1005 elf_section_data (sec)->this_hdr.contents = contents;
1006 free_contents = NULL;
1007
1008 symtab_hdr->contents = (bfd_byte *) isymbuf;
1009 free_extsyms = NULL;
1010
1011 /* Fix the opcode. */
1012 /* printf ("A relaxable case : 0x%02x (%s)\n",
1013 code, rinfo->name); */
1014 bfd_put_8 (abfd, rinfo->direct_code,
1015 contents + irel->r_offset - 1);
1016
1017 /* Delete one byte of data (upper byte of address). */
1018 m68hc11_elf_relax_delete_bytes (abfd, sec, irel->r_offset, 1);
1019
1020 /* Fix the relocation's type. */
1021 irel->r_info = ELF32_R_INFO (ELF32_R_SYM (irel->r_info),
1022 R_M68HC11_8);
1023
1024 /* That will change things, so, we should relax again. */
1025 *again = TRUE;
1026 }
196486be 1027 else if (ELF32_R_TYPE (irel->r_info) == R_M68HC11_16 && !is_far)
07d6d2b8
AM		 1028 {
1029 unsigned char code;
1030 bfd_vma offset;
1031
1032 prev_insn_branch = 0;
1033 code = bfd_get_8 (abfd, contents + irel->r_offset - 1);
1034 if (code == 0x7e || code == 0xbd)
1035 {
1036 offset = value - (irel->r_offset
1037 + sec->output_section->vma
1038 + sec->output_offset + 1);
1039 offset += bfd_get_16 (abfd, contents + irel->r_offset);
1040
1041 /* If the offset is still out of -128..+127 range,
1042 leave that far branch unchanged. */
1043 if ((offset & 0xff80) == 0 || (offset & 0xff80) == 0xff80)
1044 {
1045
1046 /* Note that we've changed the relocation contents, etc. */
1047 elf_section_data (sec)->relocs = internal_relocs;
1048 free_relocs = NULL;
1049
1050 elf_section_data (sec)->this_hdr.contents = contents;
1051 free_contents = NULL;
1052
1053 symtab_hdr->contents = (bfd_byte *) isymbuf;
1054 free_extsyms = NULL;
1055
1056 /* Shrink the branch. */
1057 code = (code == 0x7e) ? 0x20 : 0x8d;
1058 bfd_put_8 (abfd, code,
1059 contents + irel->r_offset - 1);
1060 bfd_put_8 (abfd, 0xff,
1061 contents + irel->r_offset);
1062 irel->r_info = ELF32_R_INFO (ELF32_R_SYM (irel->r_info),
1063 R_M68HC11_PCREL_8);
1064 m68hc11_elf_relax_delete_bytes (abfd, sec,
1065 irel->r_offset + 1, 1);
1066 /* That will change things, so, we should relax again. */
1067 *again = TRUE;
1068 }
1069 }
1070 }
1fd03b5a 1071 prev_insn_branch = 0;
d204f4c0 1072 prev_insn_group = 0;
1fd03b5a
SC		 1073 }
1074
1075 if (free_relocs != NULL)
1076 {
1077 free (free_relocs);
1078 free_relocs = NULL;
1079 }
1080
1081 if (free_contents != NULL)
1082 {
1083 if (! link_info->keep_memory)
1084 free (free_contents);
1085 else
1086 {
1087 /* Cache the section contents for elf_link_input_bfd. */
1088 elf_section_data (sec)->this_hdr.contents = contents;
1089 }
1090 free_contents = NULL;
1091 }
1092
1093 if (free_extsyms != NULL)
1094 {
1095 if (! link_info->keep_memory)
1096 free (free_extsyms);
1097 else
1098 {
1099 /* Cache the symbols for elf_link_input_bfd. */
1f4c5b47 1100 symtab_hdr->contents = (unsigned char *) isymbuf;
1fd03b5a
SC		 1101 }
1102 free_extsyms = NULL;
1103 }
1104
b34976b6 1105 return TRUE;
1fd03b5a
SC		 1106
1107 error_return:
1108 if (free_relocs != NULL)
1109 free (free_relocs);
1110 if (free_contents != NULL)
1111 free (free_contents);
1112 if (free_extsyms != NULL)
1113 free (free_extsyms);
b34976b6 1114 return FALSE;
1fd03b5a
SC		 1115}
1116
1117/* Delete some bytes from a section while relaxing. */
1118
1119static void
0a6a3ebe 1120m68hc11_elf_relax_delete_bytes (bfd *abfd, asection *sec,
07d6d2b8 1121 bfd_vma addr, int count)
1fd03b5a
SC		 1122{
1123 Elf_Internal_Shdr *symtab_hdr;
1fd03b5a 1124 unsigned int sec_shndx;
1fd03b5a
SC		 1125 bfd_byte *contents;
1126 Elf_Internal_Rela *irel, *irelend;
1127 bfd_vma toaddr;
1f4c5b47 1128 Elf_Internal_Sym *isymbuf, *isym, *isymend;
1fd03b5a
SC		 1129 struct elf_link_hash_entry **sym_hashes;
1130 struct elf_link_hash_entry **end_hashes;
1131 unsigned int symcount;
1132
1133 symtab_hdr = &elf_tdata (abfd)->symtab_hdr;
1f4c5b47 1134 isymbuf = (Elf_Internal_Sym *) symtab_hdr->contents;
1fd03b5a
SC		 1135
1136 sec_shndx = _bfd_elf_section_from_bfd_section (abfd, sec);
1137
1138 contents = elf_section_data (sec)->this_hdr.contents;
1139
eea6121a 1140 toaddr = sec->size;
1fd03b5a
SC		 1141
1142 irel = elf_section_data (sec)->relocs;
1143 irelend = irel + sec->reloc_count;
1144
1145 /* Actually delete the bytes. */
1146 memmove (contents + addr, contents + addr + count,
1147 (size_t) (toaddr - addr - count));
1fd03b5a 1148
eea6121a 1149 sec->size -= count;
b34976b6 1150
1fd03b5a
SC		 1151 /* Adjust all the relocs. */
1152 for (irel = elf_section_data (sec)->relocs; irel < irelend; irel++)
1153 {
1154 unsigned char code;
1155 unsigned char offset;
1156 unsigned short raddr;
1157 unsigned long old_offset;
1158 int branch_pos;
1159
1160 old_offset = irel->r_offset;
1161
1162 /* See if this reloc was for the bytes we have deleted, in which
1163 case we no longer care about it. Don't delete relocs which
1164 represent addresses, though. */
1165 if (ELF32_R_TYPE (irel->r_info) != R_M68HC11_RL_JUMP
07d6d2b8
AM		 1166 && irel->r_offset >= addr && irel->r_offset < addr + count)
1167 irel->r_info = ELF32_R_INFO (ELF32_R_SYM (irel->r_info),
1168 R_M68HC11_NONE);
1fd03b5a
SC		 1169
1170 if (ELF32_R_TYPE (irel->r_info) == R_M68HC11_NONE)
07d6d2b8 1171 continue;
1fd03b5a
SC		 1172
1173 /* Get the new reloc address. */
1174 if ((irel->r_offset > addr
1175 && irel->r_offset < toaddr))
1176 irel->r_offset -= count;
1177
1178 /* If this is a PC relative reloc, see if the range it covers
07d6d2b8 1179 includes the bytes we have deleted. */
1fd03b5a
SC		 1180 switch (ELF32_R_TYPE (irel->r_info))
1181 {
1182 default:
1183 break;
1184
1185 case R_M68HC11_RL_JUMP:
07d6d2b8
AM		 1186 code = bfd_get_8 (abfd, contents + irel->r_offset);
1187 switch (code)
1188 {
1189 /* jsr and jmp instruction are also marked with RL_JUMP
1190 relocs but no adjustment must be made. */
1191 case 0x7e:
1192 case 0x9d:
1193 case 0xbd:
1194 continue;
1195
1196 case 0x12:
1197 case 0x13:
1198 branch_pos = 3;
1199 raddr = 4;
1200
1201 /* Special case when we translate a brclr N,y into brclr *<addr>
1202 In this case, the 0x18 page2 prefix is removed.
1203 The reloc offset is not modified but the instruction
1204 size is reduced by 1. */
1205 if (old_offset == addr)
1206 raddr++;
1207 break;
1208
1209 case 0x1e:
1210 case 0x1f:
1211 branch_pos = 3;
1212 raddr = 4;
1213 break;
1214
1215 case 0x18:
1216 branch_pos = 4;
1217 raddr = 5;
1218 break;
1219
1220 default:
1221 branch_pos = 1;
1222 raddr = 2;
1223 break;
1224 }
1225 offset = bfd_get_8 (abfd, contents + irel->r_offset + branch_pos);
1226 raddr += old_offset;
1227 raddr += ((unsigned short) offset | ((offset & 0x80) ? 0xff00 : 0));
1228 if (irel->r_offset < addr && raddr > addr)
1229 {
1230 offset -= count;
1231 bfd_put_8 (abfd, offset, contents + irel->r_offset + branch_pos);
1232 }
1233 else if (irel->r_offset >= addr && raddr <= addr)
1234 {
1235 offset += count;
1236 bfd_put_8 (abfd, offset, contents + irel->r_offset + branch_pos);
1237 }
1238 else
1239 {
1240 /*printf ("Not adjusted 0x%04x [0x%4x 0x%4x]\n", raddr,
1241 irel->r_offset, addr);*/
1242 }
1243
1244 break;
1fd03b5a
SC		 1245 }
1246 }
1247
1248 /* Adjust the local symbols defined in this section. */
1f4c5b47
SC		 1249 isymend = isymbuf + symtab_hdr->sh_info;
1250 for (isym = isymbuf; isym < isymend; isym++)
1fd03b5a 1251 {
1f4c5b47
SC		 1252 if (isym->st_shndx == sec_shndx
1253 && isym->st_value > addr
196486be 1254 && isym->st_value <= toaddr)
1f4c5b47 1255 isym->st_value -= count;
1fd03b5a
SC		 1256 }
1257
1258 /* Now adjust the global symbols defined in this section. */
1259 symcount = (symtab_hdr->sh_size / sizeof (Elf32_External_Sym)
1260 - symtab_hdr->sh_info);
1261 sym_hashes = elf_sym_hashes (abfd);
1262 end_hashes = sym_hashes + symcount;
1263 for (; sym_hashes < end_hashes; sym_hashes++)
1264 {
1265 struct elf_link_hash_entry *sym_hash = *sym_hashes;
1266 if ((sym_hash->root.type == bfd_link_hash_defined
1267 || sym_hash->root.type == bfd_link_hash_defweak)
1268 && sym_hash->root.u.def.section == sec
1269 && sym_hash->root.u.def.value > addr
196486be 1270 && sym_hash->root.u.def.value <= toaddr)
1fd03b5a
SC		 1271 {
1272 sym_hash->root.u.def.value -= count;
1273 }
1274 }
1275}
1276
2f89ff8d
L		 1277/* Specific sections:
1278 - The .page0 is a data section that is mapped in [0x0000..0x00FF].
1279 Page0 accesses are faster on the M68HC11. Soft registers used by GCC-m6811
1280 are located in .page0.
3f533aa9 1281 - The .vectors is the section that represents the interrupt
2f89ff8d 1282 vectors. */
b35d266b 1283static const struct bfd_elf_special_section elf32_m68hc11_special_sections[] =
2f89ff8d 1284{
0112cd26
NC		 1285 { STRING_COMMA_LEN (".eeprom"), 0, SHT_PROGBITS, SHF_ALLOC + SHF_WRITE },
1286 { STRING_COMMA_LEN (".page0"), 0, SHT_PROGBITS, SHF_ALLOC + SHF_WRITE },
1287 { STRING_COMMA_LEN (".softregs"), 0, SHT_NOBITS, SHF_ALLOC + SHF_WRITE },
1288 { STRING_COMMA_LEN (".vectors"), 0, SHT_PROGBITS, SHF_ALLOC },
07d6d2b8 1289 { NULL, 0, 0, 0, 0 }
7f4d3958 1290};
96405e3c 1291\f
60bcf0fa 1292#define ELF_ARCH bfd_arch_m68hc11
ae95ffa6 1293#define ELF_TARGET_ID M68HC11_ELF_DATA
60bcf0fa
NC		 1294#define ELF_MACHINE_CODE EM_68HC11
1295#define ELF_MAXPAGESIZE 0x1000
1296
07d6d2b8 1297#define TARGET_BIG_SYM m68hc11_elf32_vec
60bcf0fa
NC		 1298#define TARGET_BIG_NAME "elf32-m68hc11"
1299
1300#define elf_info_to_howto 0
1301#define elf_info_to_howto_rel m68hc11_info_to_howto_rel
1fd03b5a 1302#define bfd_elf32_bfd_relax_section m68hc11_elf_relax_section
1fd03b5a
SC		 1303#define elf_backend_check_relocs elf32_m68hc11_check_relocs
1304#define elf_backend_relocate_section elf32_m68hc11_relocate_section
3a65329d 1305#define elf_backend_add_symbol_hook elf32_m68hc11_add_symbol_hook
60bcf0fa
NC		 1306#define elf_backend_object_p 0
1307#define elf_backend_final_write_processing 0
9b701e44 1308#define elf_backend_can_gc_sections 1
29ef7005 1309#define elf_backend_special_sections elf32_m68hc11_special_sections
5efbbc43 1310#define elf_backend_merge_symbol_attribute elf32_m68hc11_merge_symbol_attribute
3a65329d
SC		 1311
1312#define bfd_elf32_bfd_link_hash_table_create \
07d6d2b8 1313 m68hc11_elf_bfd_link_hash_table_create
96405e3c
SC		 1314#define bfd_elf32_bfd_merge_private_bfd_data \
1315 _bfd_m68hc11_elf_merge_private_bfd_data
1316#define bfd_elf32_bfd_set_private_flags _bfd_m68hc11_elf_set_private_flags
1317#define bfd_elf32_bfd_print_private_bfd_data \
1318 _bfd_m68hc11_elf_print_private_bfd_data
1319
60bcf0fa 1320#include "elf32-target.h"
GDB Binutils - Deliverables
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