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[deliverable/binutils-gdb.git] / bfd / elf32-msp430.c
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2469cfa2 1/* MSP430-specific support for 32-bit ELF
2571583a 2 Copyright (C) 2002-2017 Free Software Foundation, Inc.
2469cfa2
NC		 3 Contributed by Dmitry Diky <diwil@mail.ru>
4
5 This file is part of BFD, the Binary File Descriptor library.
6
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
cd123cb7 9 the Free Software Foundation; either version 3 of the License, or
2469cfa2
NC		 10 (at your option) any later version.
11
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
cd123cb7
NC		 19 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
20 MA 02110-1301, USA. */
2469cfa2 21
2469cfa2 22#include "sysdep.h"
3db64b00 23#include "bfd.h"
2469cfa2
NC		 24#include "libiberty.h"
25#include "libbfd.h"
26#include "elf-bfd.h"
27#include "elf/msp430.h"
28
1ade7175
NC		 29static bfd_reloc_status_type
30rl78_sym_diff_handler (bfd * abfd,
31 arelent * reloc,
32 asymbol * sym ATTRIBUTE_UNUSED,
33 void * addr ATTRIBUTE_UNUSED,
34 asection * input_sec,
35 bfd * out_bfd ATTRIBUTE_UNUSED,
36 char ** error_message ATTRIBUTE_UNUSED)
37{
38 bfd_size_type octets;
39 octets = reloc->address * bfd_octets_per_byte (abfd);
40
41 /* Catch the case where bfd_install_relocation would return
42 bfd_reloc_outofrange because the SYM_DIFF reloc is being used in a very
43 small section. It does not actually matter if this happens because all
44 that SYM_DIFF does is compute a (4-byte) value. A second reloc then uses
45 this value, and it is that reloc that must fit into the section.
46
47 This happens in eg, gcc/testsuite/gcc.c-torture/compile/labels-3.c. */
48 if ((octets + bfd_get_reloc_size (reloc->howto))
49 > bfd_get_section_limit_octets (abfd, input_sec))
50 return bfd_reloc_ok;
51 return bfd_reloc_continue;
52}
53
2469cfa2
NC		 54static reloc_howto_type elf_msp430_howto_table[] =
55{
56 HOWTO (R_MSP430_NONE, /* type */
57 0, /* rightshift */
6346d5ca
AM		 58 3, /* size (0 = byte, 1 = short, 2 = long) */
59 0, /* bitsize */
2469cfa2
NC		 60 FALSE, /* pc_relative */
61 0, /* bitpos */
6346d5ca 62 complain_overflow_dont,/* complain_on_overflow */
2469cfa2
NC		 63 bfd_elf_generic_reloc, /* special_function */
64 "R_MSP430_NONE", /* name */
65 FALSE, /* partial_inplace */
66 0, /* src_mask */
67 0, /* dst_mask */
68 FALSE), /* pcrel_offset */
69
70 HOWTO (R_MSP430_32, /* type */
71 0, /* rightshift */
72 2, /* size (0 = byte, 1 = short, 2 = long) */
73 32, /* bitsize */
74 FALSE, /* pc_relative */
75 0, /* bitpos */
b18c562e 76 complain_overflow_bitfield,/* complain_on_overflow */
2469cfa2
NC		 77 bfd_elf_generic_reloc, /* special_function */
78 "R_MSP430_32", /* name */
79 FALSE, /* partial_inplace */
80 0xffffffff, /* src_mask */
81 0xffffffff, /* dst_mask */
82 FALSE), /* pcrel_offset */
83
df301bfc 84 /* A 10 bit PC relative relocation. */
2469cfa2
NC		 85 HOWTO (R_MSP430_10_PCREL, /* type */
86 1, /* rightshift */
87 1, /* size (0 = byte, 1 = short, 2 = long) */
88 10, /* bitsize */
89 TRUE, /* pc_relative */
90 0, /* bitpos */
b18c562e 91 complain_overflow_bitfield,/* complain_on_overflow */
2469cfa2 92 bfd_elf_generic_reloc, /* special_function */
13761a11 93 "R_MSP430_10_PCREL", /* name */
2469cfa2 94 FALSE, /* partial_inplace */
df301bfc
NC		 95 0x3ff, /* src_mask */
96 0x3ff, /* dst_mask */
2469cfa2
NC		 97 TRUE), /* pcrel_offset */
98
99 /* A 16 bit absolute relocation. */
100 HOWTO (R_MSP430_16, /* type */
101 0, /* rightshift */
102 1, /* size (0 = byte, 1 = short, 2 = long) */
103 16, /* bitsize */
104 FALSE, /* pc_relative */
105 0, /* bitpos */
106 complain_overflow_dont,/* complain_on_overflow */
107 bfd_elf_generic_reloc, /* special_function */
108 "R_MSP430_16", /* name */
109 FALSE, /* partial_inplace */
b18c562e 110 0, /* src_mask */
2469cfa2
NC		 111 0xffff, /* dst_mask */
112 FALSE), /* pcrel_offset */
113
13761a11 114 /* A 16 bit PC relative relocation for command address. */
2469cfa2
NC		 115 HOWTO (R_MSP430_16_PCREL, /* type */
116 1, /* rightshift */
117 1, /* size (0 = byte, 1 = short, 2 = long) */
118 16, /* bitsize */
119 TRUE, /* pc_relative */
120 0, /* bitpos */
121 complain_overflow_dont,/* complain_on_overflow */
122 bfd_elf_generic_reloc, /* special_function */
123 "R_MSP430_16_PCREL", /* name */
124 FALSE, /* partial_inplace */
b18c562e 125 0, /* src_mask */
2469cfa2
NC		 126 0xffff, /* dst_mask */
127 TRUE), /* pcrel_offset */
128
129 /* A 16 bit absolute relocation, byte operations. */
130 HOWTO (R_MSP430_16_BYTE, /* type */
131 0, /* rightshift */
132 1, /* size (0 = byte, 1 = short, 2 = long) */
133 16, /* bitsize */
134 FALSE, /* pc_relative */
135 0, /* bitpos */
136 complain_overflow_dont,/* complain_on_overflow */
137 bfd_elf_generic_reloc, /* special_function */
138 "R_MSP430_16_BYTE", /* name */
139 FALSE, /* partial_inplace */
140 0xffff, /* src_mask */
141 0xffff, /* dst_mask */
142 FALSE), /* pcrel_offset */
143
144 /* A 16 bit absolute relocation for command address. */
145 HOWTO (R_MSP430_16_PCREL_BYTE,/* type */
146 1, /* rightshift */
147 1, /* size (0 = byte, 1 = short, 2 = long) */
148 16, /* bitsize */
149 TRUE, /* pc_relative */
150 0, /* bitpos */
151 complain_overflow_dont,/* complain_on_overflow */
152 bfd_elf_generic_reloc, /* special_function */
b18c562e 153 "R_MSP430_16_PCREL_BYTE",/* name */
2469cfa2
NC		 154 FALSE, /* partial_inplace */
155 0xffff, /* src_mask */
156 0xffff, /* dst_mask */
b18c562e
NC		 157 TRUE), /* pcrel_offset */
158
df301bfc 159 /* A 10 bit PC relative relocation for complicated polymorphs. */
b18c562e
NC		 160 HOWTO (R_MSP430_2X_PCREL, /* type */
161 1, /* rightshift */
162 2, /* size (0 = byte, 1 = short, 2 = long) */
163 10, /* bitsize */
164 TRUE, /* pc_relative */
165 0, /* bitpos */
166 complain_overflow_bitfield,/* complain_on_overflow */
167 bfd_elf_generic_reloc, /* special_function */
168 "R_MSP430_2X_PCREL", /* name */
169 FALSE, /* partial_inplace */
df301bfc
NC		 170 0x3ff, /* src_mask */
171 0x3ff, /* dst_mask */
b18c562e
NC		 172 TRUE), /* pcrel_offset */
173
174 /* A 16 bit relaxable relocation for command address. */
175 HOWTO (R_MSP430_RL_PCREL, /* type */
176 1, /* rightshift */
177 1, /* size (0 = byte, 1 = short, 2 = long) */
178 16, /* bitsize */
179 TRUE, /* pc_relative */
180 0, /* bitpos */
181 complain_overflow_dont,/* complain_on_overflow */
182 bfd_elf_generic_reloc, /* special_function */
183 "R_MSP430_RL_PCREL", /* name */
184 FALSE, /* partial_inplace */
185 0, /* src_mask */
186 0xffff, /* dst_mask */
2469cfa2 187 TRUE) /* pcrel_offset */
13761a11
NC		 188
189 /* A 8-bit absolute relocation. */
190 , HOWTO (R_MSP430_8, /* type */
191 0, /* rightshift */
192 0, /* size (0 = byte, 1 = short, 2 = long) */
193 8, /* bitsize */
194 FALSE, /* pc_relative */
195 0, /* bitpos */
196 complain_overflow_dont,/* complain_on_overflow */
197 bfd_elf_generic_reloc, /* special_function */
198 "R_MSP430_8", /* name */
199 FALSE, /* partial_inplace */
200 0, /* src_mask */
201 0xffff, /* dst_mask */
202 FALSE), /* pcrel_offset */
203
204 /* Together with a following reloc, allows for the difference
205 between two symbols to be the real addend of the second reloc. */
206 HOWTO (R_MSP430_SYM_DIFF, /* type */
207 0, /* rightshift */
208 2, /* size (0 = byte, 1 = short, 2 = long) */
209 32, /* bitsize */
210 FALSE, /* pc_relative */
211 0, /* bitpos */
212 complain_overflow_dont,/* complain_on_overflow */
1ade7175 213 rl78_sym_diff_handler, /* special handler. */
13761a11
NC		 214 "R_MSP430_SYM_DIFF", /* name */
215 FALSE, /* partial_inplace */
216 0xffffffff, /* src_mask */
217 0xffffffff, /* dst_mask */
1b786873 218 FALSE) /* pcrel_offset */
13761a11
NC		 219};
220
221static reloc_howto_type elf_msp430x_howto_table[] =
222{
223 HOWTO (R_MSP430_NONE, /* type */
224 0, /* rightshift */
6346d5ca
AM		 225 3, /* size (0 = byte, 1 = short, 2 = long) */
226 0, /* bitsize */
13761a11
NC		 227 FALSE, /* pc_relative */
228 0, /* bitpos */
6346d5ca 229 complain_overflow_dont,/* complain_on_overflow */
13761a11
NC		 230 bfd_elf_generic_reloc, /* special_function */
231 "R_MSP430_NONE", /* name */
232 FALSE, /* partial_inplace */
233 0, /* src_mask */
234 0, /* dst_mask */
235 FALSE), /* pcrel_offset */
236
237 HOWTO (R_MSP430_ABS32, /* type */
238 0, /* rightshift */
239 2, /* size (0 = byte, 1 = short, 2 = long) */
240 32, /* bitsize */
241 FALSE, /* pc_relative */
242 0, /* bitpos */
243 complain_overflow_bitfield,/* complain_on_overflow */
244 bfd_elf_generic_reloc, /* special_function */
245 "R_MSP430_ABS32", /* name */
246 FALSE, /* partial_inplace */
247 0xffffffff, /* src_mask */
248 0xffffffff, /* dst_mask */
249 FALSE), /* pcrel_offset */
250
251 HOWTO (R_MSP430_ABS16, /* type */
252 0, /* rightshift */
253 1, /* size (0 = byte, 1 = short, 2 = long) */
254 16, /* bitsize */
255 FALSE, /* pc_relative */
256 0, /* bitpos */
257 complain_overflow_dont,/* complain_on_overflow */
258 bfd_elf_generic_reloc, /* special_function */
259 "R_MSP430_ABS16", /* name */
260 FALSE, /* partial_inplace */
261 0, /* src_mask */
262 0xffff, /* dst_mask */
263 FALSE), /* pcrel_offset */
264
265 HOWTO (R_MSP430_ABS8, /* type */
266 0, /* rightshift */
267 0, /* size (0 = byte, 1 = short, 2 = long) */
268 8, /* bitsize */
269 FALSE, /* pc_relative */
270 0, /* bitpos */
271 complain_overflow_bitfield,/* complain_on_overflow */
272 bfd_elf_generic_reloc, /* special_function */
273 "R_MSP430_ABS8", /* name */
274 FALSE, /* partial_inplace */
275 0xff, /* src_mask */
276 0xff, /* dst_mask */
277 FALSE), /* pcrel_offset */
278
279 HOWTO (R_MSP430_PCR16, /* type */
280 1, /* rightshift */
281 1, /* size (0 = byte, 1 = short, 2 = long) */
282 16, /* bitsize */
283 TRUE, /* pc_relative */
284 0, /* bitpos */
285 complain_overflow_dont,/* complain_on_overflow */
286 bfd_elf_generic_reloc, /* special_function */
287 "R_MSP430_PCR16", /* name */
288 FALSE, /* partial_inplace */
289 0, /* src_mask */
290 0xffff, /* dst_mask */
291 TRUE), /* pcrel_offset */
292
293 HOWTO (R_MSP430X_PCR20_EXT_SRC,/* type */
294 0, /* rightshift */
295 2, /* size (0 = byte, 1 = short, 2 = long) */
296 32, /* bitsize */
297 TRUE, /* pc_relative */
298 0, /* bitpos */
299 complain_overflow_dont,/* complain_on_overflow */
300 bfd_elf_generic_reloc, /* special_function */
301 "R_MSP430X_PCR20_EXT_SRC",/* name */
302 FALSE, /* partial_inplace */
303 0, /* src_mask */
304 0xffff, /* dst_mask */
305 TRUE), /* pcrel_offset */
306
307 HOWTO (R_MSP430X_PCR20_EXT_DST,/* type */
308 0, /* rightshift */
309 2, /* size (0 = byte, 1 = short, 2 = long) */
310 32, /* bitsize */
311 TRUE, /* pc_relative */
312 0, /* bitpos */
313 complain_overflow_dont,/* complain_on_overflow */
314 bfd_elf_generic_reloc, /* special_function */
315 "R_MSP430X_PCR20_EXT_DST",/* name */
316 FALSE, /* partial_inplace */
317 0, /* src_mask */
318 0xffff, /* dst_mask */
319 TRUE), /* pcrel_offset */
320
321 HOWTO (R_MSP430X_PCR20_EXT_ODST,/* type */
322 0, /* rightshift */
323 2, /* size (0 = byte, 1 = short, 2 = long) */
324 32, /* bitsize */
325 TRUE, /* pc_relative */
326 0, /* bitpos */
327 complain_overflow_dont,/* complain_on_overflow */
328 bfd_elf_generic_reloc, /* special_function */
329 "R_MSP430X_PCR20_EXT_ODST",/* name */
330 FALSE, /* partial_inplace */
331 0, /* src_mask */
332 0xffff, /* dst_mask */
333 TRUE), /* pcrel_offset */
334
335 HOWTO (R_MSP430X_ABS20_EXT_SRC,/* type */
336 0, /* rightshift */
337 2, /* size (0 = byte, 1 = short, 2 = long) */
338 32, /* bitsize */
339 TRUE, /* pc_relative */
340 0, /* bitpos */
341 complain_overflow_dont,/* complain_on_overflow */
342 bfd_elf_generic_reloc, /* special_function */
343 "R_MSP430X_ABS20_EXT_SRC",/* name */
344 FALSE, /* partial_inplace */
345 0, /* src_mask */
346 0xffff, /* dst_mask */
347 TRUE), /* pcrel_offset */
348
349 HOWTO (R_MSP430X_ABS20_EXT_DST,/* type */
350 0, /* rightshift */
351 2, /* size (0 = byte, 1 = short, 2 = long) */
352 32, /* bitsize */
353 TRUE, /* pc_relative */
354 0, /* bitpos */
355 complain_overflow_dont,/* complain_on_overflow */
356 bfd_elf_generic_reloc, /* special_function */
357 "R_MSP430X_ABS20_EXT_DST",/* name */
358 FALSE, /* partial_inplace */
359 0, /* src_mask */
360 0xffff, /* dst_mask */
361 TRUE), /* pcrel_offset */
362
363 HOWTO (R_MSP430X_ABS20_EXT_ODST,/* type */
364 0, /* rightshift */
365 2, /* size (0 = byte, 1 = short, 2 = long) */
366 32, /* bitsize */
367 TRUE, /* pc_relative */
368 0, /* bitpos */
369 complain_overflow_dont,/* complain_on_overflow */
370 bfd_elf_generic_reloc, /* special_function */
371 "R_MSP430X_ABS20_EXT_ODST",/* name */
372 FALSE, /* partial_inplace */
373 0, /* src_mask */
374 0xffff, /* dst_mask */
375 TRUE), /* pcrel_offset */
376
377 HOWTO (R_MSP430X_ABS20_ADR_SRC,/* type */
378 0, /* rightshift */
379 2, /* size (0 = byte, 1 = short, 2 = long) */
380 32, /* bitsize */
381 TRUE, /* pc_relative */
382 0, /* bitpos */
383 complain_overflow_dont,/* complain_on_overflow */
384 bfd_elf_generic_reloc, /* special_function */
385 "R_MSP430X_ABS20_ADR_SRC",/* name */
386 FALSE, /* partial_inplace */
387 0, /* src_mask */
388 0xffff, /* dst_mask */
389 TRUE), /* pcrel_offset */
390
391 HOWTO (R_MSP430X_ABS20_ADR_DST,/* type */
392 0, /* rightshift */
393 2, /* size (0 = byte, 1 = short, 2 = long) */
394 32, /* bitsize */
395 TRUE, /* pc_relative */
396 0, /* bitpos */
397 complain_overflow_dont,/* complain_on_overflow */
398 bfd_elf_generic_reloc, /* special_function */
399 "R_MSP430X_ABS20_ADR_DST",/* name */
400 FALSE, /* partial_inplace */
401 0, /* src_mask */
402 0xffff, /* dst_mask */
403 TRUE), /* pcrel_offset */
404
405 HOWTO (R_MSP430X_PCR16, /* type */
406 0, /* rightshift */
407 2, /* size (0 = byte, 1 = short, 2 = long) */
408 32, /* bitsize */
409 TRUE, /* pc_relative */
410 0, /* bitpos */
411 complain_overflow_dont,/* complain_on_overflow */
412 bfd_elf_generic_reloc, /* special_function */
413 "R_MSP430X_PCR16", /* name */
414 FALSE, /* partial_inplace */
415 0, /* src_mask */
416 0xffff, /* dst_mask */
417 TRUE), /* pcrel_offset */
418
419 HOWTO (R_MSP430X_PCR20_CALL, /* type */
420 0, /* rightshift */
421 2, /* size (0 = byte, 1 = short, 2 = long) */
422 32, /* bitsize */
423 TRUE, /* pc_relative */
424 0, /* bitpos */
425 complain_overflow_dont,/* complain_on_overflow */
426 bfd_elf_generic_reloc, /* special_function */
427 "R_MSP430X_PCR20_CALL",/* name */
428 FALSE, /* partial_inplace */
429 0, /* src_mask */
430 0xffff, /* dst_mask */
431 TRUE), /* pcrel_offset */
432
433 HOWTO (R_MSP430X_ABS16, /* type */
434 0, /* rightshift */
435 2, /* size (0 = byte, 1 = short, 2 = long) */
436 32, /* bitsize */
437 TRUE, /* pc_relative */
438 0, /* bitpos */
439 complain_overflow_dont,/* complain_on_overflow */
440 bfd_elf_generic_reloc, /* special_function */
441 "R_MSP430X_ABS16", /* name */
442 FALSE, /* partial_inplace */
443 0, /* src_mask */
444 0xffff, /* dst_mask */
445 TRUE), /* pcrel_offset */
446
447 HOWTO (R_MSP430_ABS_HI16, /* type */
448 0, /* rightshift */
449 2, /* size (0 = byte, 1 = short, 2 = long) */
450 32, /* bitsize */
451 TRUE, /* pc_relative */
452 0, /* bitpos */
453 complain_overflow_dont,/* complain_on_overflow */
454 bfd_elf_generic_reloc, /* special_function */
455 "R_MSP430_ABS_HI16", /* name */
456 FALSE, /* partial_inplace */
457 0, /* src_mask */
458 0xffff, /* dst_mask */
459 TRUE), /* pcrel_offset */
460
461 HOWTO (R_MSP430_PREL31, /* type */
462 0, /* rightshift */
463 2, /* size (0 = byte, 1 = short, 2 = long) */
464 32, /* bitsize */
465 TRUE, /* pc_relative */
466 0, /* bitpos */
467 complain_overflow_dont,/* complain_on_overflow */
468 bfd_elf_generic_reloc, /* special_function */
469 "R_MSP430_PREL31", /* name */
470 FALSE, /* partial_inplace */
471 0, /* src_mask */
472 0xffff, /* dst_mask */
473 TRUE), /* pcrel_offset */
474
475 EMPTY_HOWTO (R_MSP430_EHTYPE),
1b786873 476
df301bfc 477 /* A 10 bit PC relative relocation. */
13761a11
NC		 478 HOWTO (R_MSP430X_10_PCREL, /* type */
479 1, /* rightshift */
480 1, /* size (0 = byte, 1 = short, 2 = long) */
481 10, /* bitsize */
482 TRUE, /* pc_relative */
483 0, /* bitpos */
484 complain_overflow_bitfield,/* complain_on_overflow */
485 bfd_elf_generic_reloc, /* special_function */
486 "R_MSP430X_10_PCREL", /* name */
487 FALSE, /* partial_inplace */
df301bfc
NC		 488 0x3ff, /* src_mask */
489 0x3ff, /* dst_mask */
13761a11
NC		 490 TRUE), /* pcrel_offset */
491
df301bfc 492 /* A 10 bit PC relative relocation for complicated polymorphs. */
13761a11
NC		 493 HOWTO (R_MSP430X_2X_PCREL, /* type */
494 1, /* rightshift */
495 2, /* size (0 = byte, 1 = short, 2 = long) */
496 10, /* bitsize */
497 TRUE, /* pc_relative */
498 0, /* bitpos */
499 complain_overflow_bitfield,/* complain_on_overflow */
500 bfd_elf_generic_reloc, /* special_function */
501 "R_MSP430X_2X_PCREL", /* name */
502 FALSE, /* partial_inplace */
df301bfc
NC		 503 0x3ff, /* src_mask */
504 0x3ff, /* dst_mask */
13761a11
NC		 505 TRUE), /* pcrel_offset */
506
507 /* Together with a following reloc, allows for the difference
508 between two symbols to be the real addend of the second reloc. */
509 HOWTO (R_MSP430X_SYM_DIFF, /* type */
510 0, /* rightshift */
511 2, /* size (0 = byte, 1 = short, 2 = long) */
512 32, /* bitsize */
513 FALSE, /* pc_relative */
514 0, /* bitpos */
515 complain_overflow_dont,/* complain_on_overflow */
1ade7175 516 rl78_sym_diff_handler, /* special handler. */
13761a11
NC		 517 "R_MSP430X_SYM_DIFF", /* name */
518 FALSE, /* partial_inplace */
519 0xffffffff, /* src_mask */
520 0xffffffff, /* dst_mask */
1b786873 521 FALSE) /* pcrel_offset */
2469cfa2
NC		 522};
523
524/* Map BFD reloc types to MSP430 ELF reloc types. */
525
526struct msp430_reloc_map
527{
528 bfd_reloc_code_real_type bfd_reloc_val;
529 unsigned int elf_reloc_val;
530};
531
532static const struct msp430_reloc_map msp430_reloc_map[] =
13761a11
NC		 533{
534 {BFD_RELOC_NONE, R_MSP430_NONE},
535 {BFD_RELOC_32, R_MSP430_32},
536 {BFD_RELOC_MSP430_10_PCREL, R_MSP430_10_PCREL},
537 {BFD_RELOC_16, R_MSP430_16_BYTE},
538 {BFD_RELOC_MSP430_16_PCREL, R_MSP430_16_PCREL},
539 {BFD_RELOC_MSP430_16, R_MSP430_16},
540 {BFD_RELOC_MSP430_16_PCREL_BYTE, R_MSP430_16_PCREL_BYTE},
541 {BFD_RELOC_MSP430_16_BYTE, R_MSP430_16_BYTE},
542 {BFD_RELOC_MSP430_2X_PCREL, R_MSP430_2X_PCREL},
543 {BFD_RELOC_MSP430_RL_PCREL, R_MSP430_RL_PCREL},
544 {BFD_RELOC_8, R_MSP430_8},
545 {BFD_RELOC_MSP430_SYM_DIFF, R_MSP430_SYM_DIFF}
546};
547
548static const struct msp430_reloc_map msp430x_reloc_map[] =
549{
550 {BFD_RELOC_NONE, R_MSP430_NONE},
551 {BFD_RELOC_32, R_MSP430_ABS32},
552 {BFD_RELOC_16, R_MSP430_ABS16},
553 {BFD_RELOC_8, R_MSP430_ABS8},
554 {BFD_RELOC_MSP430_ABS8, R_MSP430_ABS8},
555 {BFD_RELOC_MSP430X_PCR20_EXT_SRC, R_MSP430X_PCR20_EXT_SRC},
556 {BFD_RELOC_MSP430X_PCR20_EXT_DST, R_MSP430X_PCR20_EXT_DST},
557 {BFD_RELOC_MSP430X_PCR20_EXT_ODST, R_MSP430X_PCR20_EXT_ODST},
558 {BFD_RELOC_MSP430X_ABS20_EXT_SRC, R_MSP430X_ABS20_EXT_SRC},
559 {BFD_RELOC_MSP430X_ABS20_EXT_DST, R_MSP430X_ABS20_EXT_DST},
560 {BFD_RELOC_MSP430X_ABS20_EXT_ODST, R_MSP430X_ABS20_EXT_ODST},
561 {BFD_RELOC_MSP430X_ABS20_ADR_SRC, R_MSP430X_ABS20_ADR_SRC},
562 {BFD_RELOC_MSP430X_ABS20_ADR_DST, R_MSP430X_ABS20_ADR_DST},
563 {BFD_RELOC_MSP430X_PCR16, R_MSP430X_PCR16},
564 {BFD_RELOC_MSP430X_PCR20_CALL, R_MSP430X_PCR20_CALL},
565 {BFD_RELOC_MSP430X_ABS16, R_MSP430X_ABS16},
566 {BFD_RELOC_MSP430_ABS_HI16, R_MSP430_ABS_HI16},
567 {BFD_RELOC_MSP430_PREL31, R_MSP430_PREL31},
568 {BFD_RELOC_MSP430_10_PCREL, R_MSP430X_10_PCREL},
569 {BFD_RELOC_MSP430_2X_PCREL, R_MSP430X_2X_PCREL},
570 {BFD_RELOC_MSP430_RL_PCREL, R_MSP430X_PCR16},
571 {BFD_RELOC_MSP430_SYM_DIFF, R_MSP430X_SYM_DIFF}
572};
573
574static inline bfd_boolean
575uses_msp430x_relocs (bfd * abfd)
576{
6d00b590 577 extern const bfd_target msp430_elf32_ti_vec;
13761a11
NC		 578
579 return bfd_get_mach (abfd) == bfd_mach_msp430x
6d00b590 580 || abfd->xvec == & msp430_elf32_ti_vec;
13761a11 581}
2469cfa2
NC		 582
583static reloc_howto_type *
b18c562e
NC		 584bfd_elf32_bfd_reloc_type_lookup (bfd * abfd ATTRIBUTE_UNUSED,
585 bfd_reloc_code_real_type code)
2469cfa2
NC		 586{
587 unsigned int i;
588
13761a11
NC		 589 if (uses_msp430x_relocs (abfd))
590 {
591 for (i = ARRAY_SIZE (msp430x_reloc_map); i--;)
592 if (msp430x_reloc_map[i].bfd_reloc_val == code)
593 return elf_msp430x_howto_table + msp430x_reloc_map[i].elf_reloc_val;
594 }
595 else
596 {
597 for (i = 0; i < ARRAY_SIZE (msp430_reloc_map); i++)
598 if (msp430_reloc_map[i].bfd_reloc_val == code)
599 return &elf_msp430_howto_table[msp430_reloc_map[i].elf_reloc_val];
600 }
2469cfa2
NC		 601
602 return NULL;
603}
604
157090f7
AM		 605static reloc_howto_type *
606bfd_elf32_bfd_reloc_name_lookup (bfd *abfd ATTRIBUTE_UNUSED,
607 const char *r_name)
608{
609 unsigned int i;
610
13761a11
NC		 611 if (uses_msp430x_relocs (abfd))
612 {
613 for (i = ARRAY_SIZE (elf_msp430x_howto_table); i--;)
614 if (elf_msp430x_howto_table[i].name != NULL
615 && strcasecmp (elf_msp430x_howto_table[i].name, r_name) == 0)
616 return elf_msp430x_howto_table + i;
617 }
618 else
619 {
620 for (i = 0;
621 i < (sizeof (elf_msp430_howto_table)
622 / sizeof (elf_msp430_howto_table[0]));
623 i++)
624 if (elf_msp430_howto_table[i].name != NULL
625 && strcasecmp (elf_msp430_howto_table[i].name, r_name) == 0)
626 return &elf_msp430_howto_table[i];
627 }
157090f7
AM		 628
629 return NULL;
630}
631
2469cfa2
NC		 632/* Set the howto pointer for an MSP430 ELF reloc. */
633
634static void
b18c562e
NC		 635msp430_info_to_howto_rela (bfd * abfd ATTRIBUTE_UNUSED,
636 arelent * cache_ptr,
637 Elf_Internal_Rela * dst)
2469cfa2
NC		 638{
639 unsigned int r_type;
640
641 r_type = ELF32_R_TYPE (dst->r_info);
13761a11
NC		 642
643 if (uses_msp430x_relocs (abfd))
644 {
5860e3f8
NC		 645 if (r_type >= (unsigned int) R_MSP430x_max)
646 {
695344c0 647 /* xgettext:c-format */
64d29018 648 _bfd_error_handler (_("%B: invalid MSP430X reloc number: %d"), abfd, r_type);
5860e3f8
NC		 649 r_type = 0;
650 }
13761a11
NC		 651 cache_ptr->howto = elf_msp430x_howto_table + r_type;
652 return;
653 }
654
5860e3f8
NC		 655 if (r_type >= (unsigned int) R_MSP430_max)
656 {
695344c0 657 /* xgettext:c-format */
64d29018 658 _bfd_error_handler (_("%B: invalid MSP430 reloc number: %d"), abfd, r_type);
5860e3f8
NC		 659 r_type = 0;
660 }
2469cfa2
NC		 661 cache_ptr->howto = &elf_msp430_howto_table[r_type];
662}
663
2469cfa2
NC		 664/* Look through the relocs for a section during the first phase.
665 Since we don't do .gots or .plts, we just need to consider the
666 virtual table relocs for gc. */
667
668static bfd_boolean
b18c562e
NC		 669elf32_msp430_check_relocs (bfd * abfd, struct bfd_link_info * info,
670 asection * sec, const Elf_Internal_Rela * relocs)
2469cfa2
NC		 671{
672 Elf_Internal_Shdr *symtab_hdr;
5582a088 673 struct elf_link_hash_entry **sym_hashes;
2469cfa2
NC		 674 const Elf_Internal_Rela *rel;
675 const Elf_Internal_Rela *rel_end;
676
0e1862bb 677 if (bfd_link_relocatable (info))
2469cfa2
NC		 678 return TRUE;
679
680 symtab_hdr = &elf_tdata (abfd)->symtab_hdr;
681 sym_hashes = elf_sym_hashes (abfd);
2469cfa2
NC		 682
683 rel_end = relocs + sec->reloc_count;
684 for (rel = relocs; rel < rel_end; rel++)
685 {
686 struct elf_link_hash_entry *h;
687 unsigned long r_symndx;
688
689 r_symndx = ELF32_R_SYM (rel->r_info);
690 if (r_symndx < symtab_hdr->sh_info)
691 h = NULL;
692 else
973a3492
L		 693 {
694 h = sym_hashes[r_symndx - symtab_hdr->sh_info];
695 while (h->root.type == bfd_link_hash_indirect
696 || h->root.type == bfd_link_hash_warning)
697 h = (struct elf_link_hash_entry *) h->root.u.i.link;
81fbe831
AM		 698
699 /* PR15323, ref flags aren't set for references in the same
700 object. */
701 h->root.non_ir_ref = 1;
973a3492 702 }
2469cfa2
NC		 703 }
704
705 return TRUE;
706}
707
708/* Perform a single relocation. By default we use the standard BFD
709 routines, but a few relocs, we have to do them ourselves. */
710
711static bfd_reloc_status_type
13761a11
NC		 712msp430_final_link_relocate (reloc_howto_type * howto,
713 bfd * input_bfd,
714 asection * input_section,
715 bfd_byte * contents,
716 Elf_Internal_Rela * rel,
717 bfd_vma relocation,
718 struct bfd_link_info * info)
2469cfa2 719{
13761a11
NC		 720 static asection * sym_diff_section;
721 static bfd_vma sym_diff_value;
722
723 struct bfd_elf_section_data * esd = elf_section_data (input_section);
2469cfa2
NC		 724 bfd_reloc_status_type r = bfd_reloc_ok;
725 bfd_vma x;
726 bfd_signed_vma srel;
13761a11
NC		 727 bfd_boolean is_rel_reloc = FALSE;
728
729 if (uses_msp430x_relocs (input_bfd))
730 {
731 /* See if we have a REL type relocation. */
732 is_rel_reloc = (esd->rel.hdr != NULL);
733 /* Sanity check - only one type of relocation per section.
734 FIXME: Theoretically it is possible to have both types,
735 but if that happens how can we distinguish between the two ? */
736 BFD_ASSERT (! is_rel_reloc || ! esd->rela.hdr);
737 /* If we are using a REL relocation then the addend should be empty. */
738 BFD_ASSERT (! is_rel_reloc || rel->r_addend == 0);
739 }
2469cfa2 740
13761a11 741 if (sym_diff_section != NULL)
2469cfa2 742 {
13761a11 743 BFD_ASSERT (sym_diff_section == input_section);
1b786873 744
13761a11
NC		 745 if (uses_msp430x_relocs (input_bfd))
746 switch (howto->type)
747 {
748 case R_MSP430_ABS32:
749 /* If we are computing a 32-bit value for the location lists
750 and the result is 0 then we add one to the value. A zero
751 value can result because of linker relaxation deleteing
752 prologue instructions and using a value of 1 (for the begin
753 and end offsets in the location list entry) results in a
754 nul entry which does not prevent the following entries from
755 being parsed. */
756 if (relocation == sym_diff_value
757 && strcmp (input_section->name, ".debug_loc") == 0)
758 ++ relocation;
759 /* Fall through. */
760 case R_MSP430_ABS16:
761 case R_MSP430X_ABS16:
762 case R_MSP430_ABS8:
763 BFD_ASSERT (! is_rel_reloc);
764 relocation -= sym_diff_value;
765 break;
766
767 default:
768 return bfd_reloc_dangerous;
769 }
770 else
771 switch (howto->type)
772 {
773 case R_MSP430_32:
774 case R_MSP430_16:
775 case R_MSP430_16_BYTE:
776 case R_MSP430_8:
777 relocation -= sym_diff_value;
778 break;
779
780 default:
781 return bfd_reloc_dangerous;
782 }
1b786873 783
13761a11
NC		 784 sym_diff_section = NULL;
785 }
786
787 if (uses_msp430x_relocs (input_bfd))
788 switch (howto->type)
789 {
790 case R_MSP430X_SYM_DIFF:
791 /* Cache the input section and value.
792 The offset is unreliable, since relaxation may
793 have reduced the following reloc's offset. */
794 BFD_ASSERT (! is_rel_reloc);
795 sym_diff_section = input_section;
796 sym_diff_value = relocation;
797 return bfd_reloc_ok;
798
799 case R_MSP430_ABS16:
800 contents += rel->r_offset;
801 srel = (bfd_signed_vma) relocation;
802 if (is_rel_reloc)
803 srel += bfd_get_16 (input_bfd, contents);
804 else
805 srel += rel->r_addend;
806 bfd_put_16 (input_bfd, srel & 0xffff, contents);
807 break;
808
809 case R_MSP430X_10_PCREL:
810 contents += rel->r_offset;
811 srel = (bfd_signed_vma) relocation;
812 if (is_rel_reloc)
813 srel += bfd_get_16 (input_bfd, contents) & 0x3ff;
814 else
815 srel += rel->r_addend;
816 srel -= rel->r_offset;
817 srel -= 2; /* Branch instructions add 2 to the PC... */
818 srel -= (input_section->output_section->vma +
819 input_section->output_offset);
820 if (srel & 1)
821 return bfd_reloc_outofrange;
822
823 /* MSP430 addresses commands as words. */
824 srel >>= 1;
825
826 /* Check for an overflow. */
827 if (srel < -512 || srel > 511)
828 {
829 if (info->disable_target_specific_optimizations < 0)
830 {
831 static bfd_boolean warned = FALSE;
832 if (! warned)
833 {
834 info->callbacks->warning
835 (info,
836 _("Try enabling relaxation to avoid relocation truncations"),
837 NULL, input_bfd, input_section, relocation);
838 warned = TRUE;
839 }
840 }
841 return bfd_reloc_overflow;
842 }
843
844 x = bfd_get_16 (input_bfd, contents);
845 x = (x & 0xfc00) | (srel & 0x3ff);
846 bfd_put_16 (input_bfd, x, contents);
847 break;
848
849 case R_MSP430X_PCR20_EXT_ODST:
3f307074 850 /* [0,4]+[48,16] = ---F ---- ---- FFFF */
13761a11
NC		 851 contents += rel->r_offset;
852 srel = (bfd_signed_vma) relocation;
853 if (is_rel_reloc)
854 {
855 bfd_vma addend;
856 addend = (bfd_get_16 (input_bfd, contents) & 0xf) << 16;
3f307074 857 addend |= bfd_get_16 (input_bfd, contents + 6);
13761a11 858 srel += addend;
1b786873 859
13761a11
NC		 860 }
861 else
862 srel += rel->r_addend;
863 srel -= rel->r_offset;
864 srel -= (input_section->output_section->vma +
865 input_section->output_offset);
866 bfd_put_16 (input_bfd, (srel & 0xffff), contents + 6);
867 x = bfd_get_16 (input_bfd, contents);
868 x = (x & 0xfff0) | ((srel >> 16) & 0xf);
869 bfd_put_16 (input_bfd, x, contents);
870 break;
871
872 case R_MSP430X_ABS20_EXT_SRC:
3f307074 873 /* [7,4]+[32,16] = -78- ---- FFFF */
13761a11
NC		 874 contents += rel->r_offset;
875 srel = (bfd_signed_vma) relocation;
876 if (is_rel_reloc)
877 {
878 bfd_vma addend;
879 addend = (bfd_get_16 (input_bfd, contents) & 0x0780) << 9;
3f307074 880 addend |= bfd_get_16 (input_bfd, contents + 4);
13761a11
NC		 881 srel += addend;
882 }
883 else
884 srel += rel->r_addend;
885 bfd_put_16 (input_bfd, (srel & 0xffff), contents + 4);
886 srel >>= 16;
887 x = bfd_get_16 (input_bfd, contents);
888 x = (x & 0xf87f) | ((srel << 7) & 0x0780);
889 bfd_put_16 (input_bfd, x, contents);
890 break;
891
892 case R_MSP430_16_PCREL:
893 contents += rel->r_offset;
894 srel = (bfd_signed_vma) relocation;
895 if (is_rel_reloc)
896 srel += bfd_get_16 (input_bfd, contents);
897 else
898 srel += rel->r_addend;
899 srel -= rel->r_offset;
900 /* Only branch instructions add 2 to the PC... */
901 srel -= (input_section->output_section->vma +
902 input_section->output_offset);
903 if (srel & 1)
904 return bfd_reloc_outofrange;
905 bfd_put_16 (input_bfd, srel & 0xffff, contents);
906 break;
907
908 case R_MSP430X_PCR20_EXT_DST:
3f307074 909 /* [0,4]+[32,16] = ---F ---- FFFF */
13761a11
NC		 910 contents += rel->r_offset;
911 srel = (bfd_signed_vma) relocation;
912 if (is_rel_reloc)
913 {
914 bfd_vma addend;
915 addend = (bfd_get_16 (input_bfd, contents) & 0xf) << 16;
3f307074 916 addend |= bfd_get_16 (input_bfd, contents + 4);
13761a11
NC		 917 srel += addend;
918 }
919 else
920 srel += rel->r_addend;
921 srel -= rel->r_offset;
922 srel -= (input_section->output_section->vma +
923 input_section->output_offset);
924 bfd_put_16 (input_bfd, (srel & 0xffff), contents + 4);
925 srel >>= 16;
926 x = bfd_get_16 (input_bfd, contents);
927 x = (x & 0xfff0) | (srel & 0xf);
928 bfd_put_16 (input_bfd, x, contents);
929 break;
930
931 case R_MSP430X_PCR20_EXT_SRC:
3f307074 932 /* [7,4]+[32,16] = -78- ---- FFFF */
13761a11
NC		 933 contents += rel->r_offset;
934 srel = (bfd_signed_vma) relocation;
935 if (is_rel_reloc)
936 {
937 bfd_vma addend;
938 addend = ((bfd_get_16 (input_bfd, contents) & 0x0780) << 9);
3f307074 939 addend |= bfd_get_16 (input_bfd, contents + 4);
13761a11
NC		 940 srel += addend;;
941 }
942 else
943 srel += rel->r_addend;
944 srel -= rel->r_offset;
945 /* Only branch instructions add 2 to the PC... */
946 srel -= (input_section->output_section->vma +
947 input_section->output_offset);
948 bfd_put_16 (input_bfd, (srel & 0xffff), contents + 4);
949 srel >>= 16;
950 x = bfd_get_16 (input_bfd, contents);
951 x = (x & 0xf87f) | ((srel << 7) & 0x0780);
952 bfd_put_16 (input_bfd, x, contents);
953 break;
954
955 case R_MSP430_ABS8:
956 contents += rel->r_offset;
957 srel = (bfd_signed_vma) relocation;
958 if (is_rel_reloc)
959 srel += bfd_get_8 (input_bfd, contents);
960 else
961 srel += rel->r_addend;
962 bfd_put_8 (input_bfd, srel & 0xff, contents);
963 break;
964
965 case R_MSP430X_ABS20_EXT_DST:
3f307074 966 /* [0,4]+[32,16] = ---F ---- FFFF */
13761a11
NC		 967 contents += rel->r_offset;
968 srel = (bfd_signed_vma) relocation;
969 if (is_rel_reloc)
3f307074
DD		 970 {
971 bfd_vma addend;
972 addend = (bfd_get_16 (input_bfd, contents) & 0xf) << 16;
973 addend |= bfd_get_16 (input_bfd, contents + 4);
974 srel += addend;
975 }
13761a11
NC		 976 else
977 srel += rel->r_addend;
978 bfd_put_16 (input_bfd, (srel & 0xffff), contents + 4);
979 srel >>= 16;
980 x = bfd_get_16 (input_bfd, contents);
981 x = (x & 0xfff0) | (srel & 0xf);
982 bfd_put_16 (input_bfd, x, contents);
983 break;
984
985 case R_MSP430X_ABS20_EXT_ODST:
3f307074 986 /* [0,4]+[48,16] = ---F ---- ---- FFFF */
13761a11
NC		 987 contents += rel->r_offset;
988 srel = (bfd_signed_vma) relocation;
989 if (is_rel_reloc)
990 {
991 bfd_vma addend;
992 addend = (bfd_get_16 (input_bfd, contents) & 0xf) << 16;
3f307074 993 addend |= bfd_get_16 (input_bfd, contents + 6);
13761a11
NC		 994 srel += addend;
995 }
996 else
997 srel += rel->r_addend;
998 bfd_put_16 (input_bfd, (srel & 0xffff), contents + 6);
999 srel >>= 16;
1000 x = bfd_get_16 (input_bfd, contents);
1001 x = (x & 0xfff0) | (srel & 0xf);
1002 bfd_put_16 (input_bfd, x, contents);
1003 break;
1004
1005 case R_MSP430X_ABS20_ADR_SRC:
3f307074 1006 /* [8,4]+[16,16] = -F-- FFFF */
13761a11
NC		 1007 contents += rel->r_offset;
1008 srel = (bfd_signed_vma) relocation;
1009 if (is_rel_reloc)
1010 {
1011 bfd_vma addend;
1012
1013 addend = ((bfd_get_16 (input_bfd, contents) & 0xf00) << 8);
3f307074 1014 addend |= bfd_get_16 (input_bfd, contents + 2);
13761a11
NC		 1015 srel += addend;
1016 }
1017 else
1018 srel += rel->r_addend;
1019 bfd_put_16 (input_bfd, (srel & 0xffff), contents + 2);
1020 srel >>= 16;
1021 x = bfd_get_16 (input_bfd, contents);
1022 x = (x & 0xf0ff) | ((srel << 8) & 0x0f00);
1023 bfd_put_16 (input_bfd, x, contents);
1024 break;
1025
1026 case R_MSP430X_ABS20_ADR_DST:
3f307074 1027 /* [0,4]+[16,16] = ---F FFFF */
13761a11
NC		 1028 contents += rel->r_offset;
1029 srel = (bfd_signed_vma) relocation;
1030 if (is_rel_reloc)
1031 {
1032 bfd_vma addend;
1033 addend = ((bfd_get_16 (input_bfd, contents) & 0xf) << 16);
3f307074 1034 addend |= bfd_get_16 (input_bfd, contents + 2);
13761a11
NC		 1035 srel += addend;
1036 }
1037 else
1038 srel += rel->r_addend;
1039 bfd_put_16 (input_bfd, (srel & 0xffff), contents + 2);
1040 srel >>= 16;
1041 x = bfd_get_16 (input_bfd, contents);
1042 x = (x & 0xfff0) | (srel & 0xf);
1043 bfd_put_16 (input_bfd, x, contents);
1044 break;
1045
1046 case R_MSP430X_ABS16:
1047 contents += rel->r_offset;
1048 srel = (bfd_signed_vma) relocation;
1049 if (is_rel_reloc)
1050 srel += bfd_get_16 (input_bfd, contents);
1051 else
1052 srel += rel->r_addend;
1053 x = srel;
1054 if (x > 0xffff)
1b786873 1055 return bfd_reloc_overflow;
13761a11
NC		 1056 bfd_put_16 (input_bfd, srel & 0xffff, contents);
1057 break;
1058
1059 case R_MSP430_ABS_HI16:
1060 /* The EABI specifies that this must be a RELA reloc. */
1061 BFD_ASSERT (! is_rel_reloc);
1062 contents += rel->r_offset;
1063 srel = (bfd_signed_vma) relocation;
1064 srel += rel->r_addend;
1065 bfd_put_16 (input_bfd, (srel >> 16) & 0xffff, contents);
1066 break;
1b786873 1067
13761a11 1068 case R_MSP430X_PCR20_CALL:
3f307074 1069 /* [0,4]+[16,16] = ---F FFFF*/
13761a11
NC		 1070 contents += rel->r_offset;
1071 srel = (bfd_signed_vma) relocation;
1072 if (is_rel_reloc)
1073 {
1074 bfd_vma addend;
1075 addend = (bfd_get_16 (input_bfd, contents) & 0xf) << 16;
3f307074 1076 addend |= bfd_get_16 (input_bfd, contents + 2);
13761a11
NC		 1077 srel += addend;
1078 }
1079 else
1080 srel += rel->r_addend;
1081 srel -= rel->r_offset;
1082 srel -= (input_section->output_section->vma +
1083 input_section->output_offset);
1084 bfd_put_16 (input_bfd, srel & 0xffff, contents + 2);
1085 srel >>= 16;
1086 x = bfd_get_16 (input_bfd, contents);
1087 x = (x & 0xfff0) | (srel & 0xf);
1088 bfd_put_16 (input_bfd, x, contents);
1089 break;
1b786873 1090
13761a11
NC		 1091 case R_MSP430X_PCR16:
1092 contents += rel->r_offset;
1093 srel = (bfd_signed_vma) relocation;
1094 if (is_rel_reloc)
1095 srel += bfd_get_16 (input_bfd, contents);
1096 else
1097 srel += rel->r_addend;
1098 srel -= rel->r_offset;
1099 srel -= (input_section->output_section->vma +
1100 input_section->output_offset);
1101 bfd_put_16 (input_bfd, srel & 0xffff, contents);
1102 break;
1b786873 1103
13761a11
NC		 1104 case R_MSP430_PREL31:
1105 contents += rel->r_offset;
1106 srel = (bfd_signed_vma) relocation;
1107 if (is_rel_reloc)
1108 srel += (bfd_get_32 (input_bfd, contents) & 0x7fffffff);
1109 else
1110 srel += rel->r_addend;
1111 srel += rel->r_addend;
1112 x = bfd_get_32 (input_bfd, contents);
1113 x = (x & 0x80000000) | ((srel >> 31) & 0x7fffffff);
1114 bfd_put_32 (input_bfd, x, contents);
1115 break;
1b786873 1116
13761a11
NC		 1117 default:
1118 r = _bfd_final_link_relocate (howto, input_bfd, input_section,
1119 contents, rel->r_offset,
1120 relocation, rel->r_addend);
1121 }
1122 else
1123 switch (howto->type)
1124 {
2469cfa2
NC		 1125 case R_MSP430_10_PCREL:
1126 contents += rel->r_offset;
1127 srel = (bfd_signed_vma) relocation;
1128 srel += rel->r_addend;
1129 srel -= rel->r_offset;
1130 srel -= 2; /* Branch instructions add 2 to the PC... */
1131 srel -= (input_section->output_section->vma +
1132 input_section->output_offset);
1133
1134 if (srel & 1)
1135 return bfd_reloc_outofrange;
1136
1137 /* MSP430 addresses commands as words. */
1138 srel >>= 1;
1139
1140 /* Check for an overflow. */
1141 if (srel < -512 || srel > 511)
13761a11
NC		 1142 {
1143 if (info->disable_target_specific_optimizations < 0)
1144 {
1145 static bfd_boolean warned = FALSE;
1146 if (! warned)
1147 {
1148 info->callbacks->warning
1149 (info,
1150 _("Try enabling relaxation to avoid relocation truncations"),
1151 NULL, input_bfd, input_section, relocation);
1152 warned = TRUE;
1153 }
1154 }
1155 return bfd_reloc_overflow;
1156 }
1b786873 1157
2469cfa2
NC		 1158 x = bfd_get_16 (input_bfd, contents);
1159 x = (x & 0xfc00) | (srel & 0x3ff);
1160 bfd_put_16 (input_bfd, x, contents);
1161 break;
1162
b18c562e
NC		 1163 case R_MSP430_2X_PCREL:
1164 contents += rel->r_offset;
1165 srel = (bfd_signed_vma) relocation;
1166 srel += rel->r_addend;
1167 srel -= rel->r_offset;
1168 srel -= 2; /* Branch instructions add 2 to the PC... */
1169 srel -= (input_section->output_section->vma +
1170 input_section->output_offset);
1171
1172 if (srel & 1)
1173 return bfd_reloc_outofrange;
1174
1175 /* MSP430 addresses commands as words. */
1176 srel >>= 1;
1177
1178 /* Check for an overflow. */
1179 if (srel < -512 || srel > 511)
1180 return bfd_reloc_overflow;
1181
1182 x = bfd_get_16 (input_bfd, contents);
1183 x = (x & 0xfc00) | (srel & 0x3ff);
1184 bfd_put_16 (input_bfd, x, contents);
1185 /* Handle second jump instruction. */
1186 x = bfd_get_16 (input_bfd, contents - 2);
1187 srel += 1;
1188 x = (x & 0xfc00) | (srel & 0x3ff);
1189 bfd_put_16 (input_bfd, x, contents - 2);
1190 break;
1191
b18c562e 1192 case R_MSP430_RL_PCREL:
77bf820f 1193 case R_MSP430_16_PCREL:
2469cfa2
NC		 1194 contents += rel->r_offset;
1195 srel = (bfd_signed_vma) relocation;
1196 srel += rel->r_addend;
1197 srel -= rel->r_offset;
1198 /* Only branch instructions add 2 to the PC... */
1199 srel -= (input_section->output_section->vma +
1200 input_section->output_offset);
1201
1202 if (srel & 1)
1203 return bfd_reloc_outofrange;
1204
1205 bfd_put_16 (input_bfd, srel & 0xffff, contents);
1206 break;
1207
1208 case R_MSP430_16_PCREL_BYTE:
1209 contents += rel->r_offset;
1210 srel = (bfd_signed_vma) relocation;
1211 srel += rel->r_addend;
1212 srel -= rel->r_offset;
1213 /* Only branch instructions add 2 to the PC... */
1214 srel -= (input_section->output_section->vma +
1215 input_section->output_offset);
1216
1217 bfd_put_16 (input_bfd, srel & 0xffff, contents);
1218 break;
1219
1220 case R_MSP430_16_BYTE:
1221 contents += rel->r_offset;
1222 srel = (bfd_signed_vma) relocation;
1223 srel += rel->r_addend;
1224 bfd_put_16 (input_bfd, srel & 0xffff, contents);
1225 break;
1226
1227 case R_MSP430_16:
1228 contents += rel->r_offset;
1229 srel = (bfd_signed_vma) relocation;
1230 srel += rel->r_addend;
1231
1232 if (srel & 1)
1233 return bfd_reloc_notsupported;
1234
1235 bfd_put_16 (input_bfd, srel & 0xffff, contents);
1236 break;
1237
13761a11
NC		 1238 case R_MSP430_8:
1239 contents += rel->r_offset;
1240 srel = (bfd_signed_vma) relocation;
1241 srel += rel->r_addend;
1242
1243 bfd_put_8 (input_bfd, srel & 0xff, contents);
1244 break;
1b786873 1245
13761a11
NC		 1246 case R_MSP430_SYM_DIFF:
1247 /* Cache the input section and value.
1248 The offset is unreliable, since relaxation may
1249 have reduced the following reloc's offset. */
1250 sym_diff_section = input_section;
1251 sym_diff_value = relocation;
1252 return bfd_reloc_ok;
1253
1254 default:
1255 r = _bfd_final_link_relocate (howto, input_bfd, input_section,
1256 contents, rel->r_offset,
1257 relocation, rel->r_addend);
1258 }
2469cfa2
NC		 1259
1260 return r;
1261}
1262
1263/* Relocate an MSP430 ELF section. */
1264
1265static bfd_boolean
b18c562e
NC		 1266elf32_msp430_relocate_section (bfd * output_bfd ATTRIBUTE_UNUSED,
1267 struct bfd_link_info * info,
1268 bfd * input_bfd,
1269 asection * input_section,
1270 bfd_byte * contents,
1271 Elf_Internal_Rela * relocs,
1272 Elf_Internal_Sym * local_syms,
1273 asection ** local_sections)
2469cfa2
NC		 1274{
1275 Elf_Internal_Shdr *symtab_hdr;
1276 struct elf_link_hash_entry **sym_hashes;
1277 Elf_Internal_Rela *rel;
1278 Elf_Internal_Rela *relend;
1279
1280 symtab_hdr = &elf_tdata (input_bfd)->symtab_hdr;
1281 sym_hashes = elf_sym_hashes (input_bfd);
1282 relend = relocs + input_section->reloc_count;
1283
1284 for (rel = relocs; rel < relend; rel++)
1285 {
1286 reloc_howto_type *howto;
1287 unsigned long r_symndx;
1288 Elf_Internal_Sym *sym;
1289 asection *sec;
1290 struct elf_link_hash_entry *h;
1291 bfd_vma relocation;
1292 bfd_reloc_status_type r;
1293 const char *name = NULL;
1294 int r_type;
1295
2469cfa2
NC		 1296 r_type = ELF32_R_TYPE (rel->r_info);
1297 r_symndx = ELF32_R_SYM (rel->r_info);
13761a11
NC		 1298
1299 if (uses_msp430x_relocs (input_bfd))
1300 howto = elf_msp430x_howto_table + r_type;
1301 else
1302 howto = elf_msp430_howto_table + r_type;
1303
2469cfa2
NC		 1304 h = NULL;
1305 sym = NULL;
1306 sec = NULL;
1307
1308 if (r_symndx < symtab_hdr->sh_info)
1309 {
1310 sym = local_syms + r_symndx;
1311 sec = local_sections[r_symndx];
8517fae7 1312 relocation = _bfd_elf_rela_local_sym (output_bfd, sym, &sec, rel);
2469cfa2
NC		 1313
1314 name = bfd_elf_string_from_elf_section
1315 (input_bfd, symtab_hdr->sh_link, sym->st_name);
13761a11 1316 name = (name == NULL || * name == 0) ? bfd_section_name (input_bfd, sec) : name;
2469cfa2
NC		 1317 }
1318 else
1319 {
62d887d4 1320 bfd_boolean unresolved_reloc, warned, ignored;
2469cfa2 1321
b2a8e766
AM		 1322 RELOC_FOR_GLOBAL_SYMBOL (info, input_bfd, input_section, rel,
1323 r_symndx, symtab_hdr, sym_hashes,
1324 h, sec, relocation,
62d887d4 1325 unresolved_reloc, warned, ignored);
13761a11 1326 name = h->root.root.string;
2469cfa2
NC		 1327 }
1328
dbaa2011 1329 if (sec != NULL && discarded_section (sec))
e4067dbb 1330 RELOC_AGAINST_DISCARDED_SECTION (info, input_bfd, input_section,
545fd46b 1331 rel, 1, relend, howto, 0, contents);
ab96bf03 1332
0e1862bb 1333 if (bfd_link_relocatable (info))
ab96bf03
AM		 1334 continue;
1335
2469cfa2 1336 r = msp430_final_link_relocate (howto, input_bfd, input_section,
13761a11 1337 contents, rel, relocation, info);
2469cfa2
NC		 1338
1339 if (r != bfd_reloc_ok)
1340 {
1341 const char *msg = (const char *) NULL;
1342
1343 switch (r)
1344 {
1345 case bfd_reloc_overflow:
1a72702b 1346 (*info->callbacks->reloc_overflow)
13761a11 1347 (info, (h ? &h->root : NULL), name, howto->name,
1a72702b 1348 (bfd_vma) 0, input_bfd, input_section, rel->r_offset);
2469cfa2
NC		 1349 break;
1350
1351 case bfd_reloc_undefined:
1a72702b
AM		 1352 (*info->callbacks->undefined_symbol)
1353 (info, name, input_bfd, input_section, rel->r_offset, TRUE);
2469cfa2
NC		 1354 break;
1355
1356 case bfd_reloc_outofrange:
13761a11 1357 msg = _("internal error: branch/jump to an odd address detected");
2469cfa2
NC		 1358 break;
1359
1360 case bfd_reloc_notsupported:
1361 msg = _("internal error: unsupported relocation error");
1362 break;
1363
1364 case bfd_reloc_dangerous:
1365 msg = _("internal error: dangerous relocation");
1366 break;
1367
1368 default:
1369 msg = _("internal error: unknown error");
1370 break;
1371 }
1372
1373 if (msg)
1a72702b
AM		 1374 (*info->callbacks->warning) (info, msg, name, input_bfd,
1375 input_section, rel->r_offset);
2469cfa2
NC		 1376 }
1377
1378 }
1379
1380 return TRUE;
1381}
1382
1383/* The final processing done just before writing out a MSP430 ELF object
1384 file. This gets the MSP430 architecture right based on the machine
1385 number. */
1386
1387static void
b18c562e
NC		 1388bfd_elf_msp430_final_write_processing (bfd * abfd,
1389 bfd_boolean linker ATTRIBUTE_UNUSED)
2469cfa2
NC		 1390{
1391 unsigned long val;
1392
1393 switch (bfd_get_mach (abfd))
1394 {
1395 default:
13761a11
NC		 1396 case bfd_mach_msp110: val = E_MSP430_MACH_MSP430x11x1; break;
1397 case bfd_mach_msp11: val = E_MSP430_MACH_MSP430x11; break;
1398 case bfd_mach_msp12: val = E_MSP430_MACH_MSP430x12; break;
1399 case bfd_mach_msp13: val = E_MSP430_MACH_MSP430x13; break;
1400 case bfd_mach_msp14: val = E_MSP430_MACH_MSP430x14; break;
1401 case bfd_mach_msp15: val = E_MSP430_MACH_MSP430x15; break;
1402 case bfd_mach_msp16: val = E_MSP430_MACH_MSP430x16; break;
1403 case bfd_mach_msp31: val = E_MSP430_MACH_MSP430x31; break;
1404 case bfd_mach_msp32: val = E_MSP430_MACH_MSP430x32; break;
1405 case bfd_mach_msp33: val = E_MSP430_MACH_MSP430x33; break;
1406 case bfd_mach_msp41: val = E_MSP430_MACH_MSP430x41; break;
1407 case bfd_mach_msp42: val = E_MSP430_MACH_MSP430x42; break;
1408 case bfd_mach_msp43: val = E_MSP430_MACH_MSP430x43; break;
1409 case bfd_mach_msp44: val = E_MSP430_MACH_MSP430x44; break;
1410 case bfd_mach_msp20: val = E_MSP430_MACH_MSP430x20; break;
1411 case bfd_mach_msp22: val = E_MSP430_MACH_MSP430x22; break;
1412 case bfd_mach_msp23: val = E_MSP430_MACH_MSP430x23; break;
1413 case bfd_mach_msp24: val = E_MSP430_MACH_MSP430x24; break;
1414 case bfd_mach_msp26: val = E_MSP430_MACH_MSP430x26; break;
1415 case bfd_mach_msp46: val = E_MSP430_MACH_MSP430x46; break;
1416 case bfd_mach_msp47: val = E_MSP430_MACH_MSP430x47; break;
1417 case bfd_mach_msp54: val = E_MSP430_MACH_MSP430x54; break;
1418 case bfd_mach_msp430x: val = E_MSP430_MACH_MSP430X; break;
2469cfa2
NC		 1419 }
1420
1421 elf_elfheader (abfd)->e_machine = EM_MSP430;
1422 elf_elfheader (abfd)->e_flags &= ~EF_MSP430_MACH;
1423 elf_elfheader (abfd)->e_flags |= val;
1424}
1425
1426/* Set the right machine number. */
1427
1428static bfd_boolean
b18c562e 1429elf32_msp430_object_p (bfd * abfd)
2469cfa2
NC		 1430{
1431 int e_set = bfd_mach_msp14;
1432
1433 if (elf_elfheader (abfd)->e_machine == EM_MSP430
1434 || elf_elfheader (abfd)->e_machine == EM_MSP430_OLD)
1435 {
1436 int e_mach = elf_elfheader (abfd)->e_flags & EF_MSP430_MACH;
1437
1438 switch (e_mach)
1439 {
1440 default:
13761a11
NC		 1441 case E_MSP430_MACH_MSP430x11: e_set = bfd_mach_msp11; break;
1442 case E_MSP430_MACH_MSP430x11x1: e_set = bfd_mach_msp110; break;
1443 case E_MSP430_MACH_MSP430x12: e_set = bfd_mach_msp12; break;
1444 case E_MSP430_MACH_MSP430x13: e_set = bfd_mach_msp13; break;
1445 case E_MSP430_MACH_MSP430x14: e_set = bfd_mach_msp14; break;
1446 case E_MSP430_MACH_MSP430x15: e_set = bfd_mach_msp15; break;
1447 case E_MSP430_MACH_MSP430x16: e_set = bfd_mach_msp16; break;
1448 case E_MSP430_MACH_MSP430x31: e_set = bfd_mach_msp31; break;
1449 case E_MSP430_MACH_MSP430x32: e_set = bfd_mach_msp32; break;
1450 case E_MSP430_MACH_MSP430x33: e_set = bfd_mach_msp33; break;
1451 case E_MSP430_MACH_MSP430x41: e_set = bfd_mach_msp41; break;
1452 case E_MSP430_MACH_MSP430x42: e_set = bfd_mach_msp42; break;
1453 case E_MSP430_MACH_MSP430x43: e_set = bfd_mach_msp43; break;
1454 case E_MSP430_MACH_MSP430x44: e_set = bfd_mach_msp44; break;
1455 case E_MSP430_MACH_MSP430x20: e_set = bfd_mach_msp20; break;
1456 case E_MSP430_MACH_MSP430x22: e_set = bfd_mach_msp22; break;
1457 case E_MSP430_MACH_MSP430x23: e_set = bfd_mach_msp23; break;
1458 case E_MSP430_MACH_MSP430x24: e_set = bfd_mach_msp24; break;
1459 case E_MSP430_MACH_MSP430x26: e_set = bfd_mach_msp26; break;
1460 case E_MSP430_MACH_MSP430x46: e_set = bfd_mach_msp46; break;
1461 case E_MSP430_MACH_MSP430x47: e_set = bfd_mach_msp47; break;
1462 case E_MSP430_MACH_MSP430x54: e_set = bfd_mach_msp54; break;
1463 case E_MSP430_MACH_MSP430X: e_set = bfd_mach_msp430x; break;
2469cfa2
NC		 1464 }
1465 }
1b786873 1466
2469cfa2
NC		 1467 return bfd_default_set_arch_mach (abfd, bfd_arch_msp430, e_set);
1468}
1469
b18c562e
NC		 1470/* These functions handle relaxing for the msp430.
1471 Relaxation required only in two cases:
1472 - Bad hand coding like jumps from one section to another or
1473 from file to file.
77bf820f 1474 - Sibling calls. This will affect only 'jump label' polymorph. Without
b18c562e
NC		 1475 relaxing this enlarges code by 2 bytes. Sibcalls implemented but
1476 do not work in gcc's port by the reason I do not know.
13761a11
NC		 1477 - To convert out of range conditional jump instructions (found inside
1478 a function) into inverted jumps over an unconditional branch instruction.
b18c562e
NC		 1479 Anyway, if a relaxation required, user should pass -relax option to the
1480 linker.
1481
1482 There are quite a few relaxing opportunities available on the msp430:
1483
1484 ================================================================
1485
1486 1. 3 words -> 1 word
1487
1488 eq == jeq label jne +4; br lab
1489 ne != jne label jeq +4; br lab
1490 lt < jl label jge +4; br lab
1491 ltu < jlo label lhs +4; br lab
1492 ge >= jge label jl +4; br lab
1493 geu >= jhs label jlo +4; br lab
1494
1495 2. 4 words -> 1 word
1496
1497 ltn < jn jn +2; jmp +4; br lab
1498
1499 3. 4 words -> 2 words
1500
1501 gt > jeq +2; jge label jeq +6; jl +4; br label
1502 gtu > jeq +2; jhs label jeq +6; jlo +4; br label
1503
1504 4. 4 words -> 2 words and 2 labels
1505
1506 leu <= jeq label; jlo label jeq +2; jhs +4; br label
1507 le <= jeq label; jl label jeq +2; jge +4; br label
1508 =================================================================
1509
1510 codemap for first cases is (labels masked ):
1511 eq: 0x2002,0x4010,0x0000 -> 0x2400
1512 ne: 0x2402,0x4010,0x0000 -> 0x2000
1513 lt: 0x3402,0x4010,0x0000 -> 0x3800
1514 ltu: 0x2c02,0x4010,0x0000 -> 0x2800
1515 ge: 0x3802,0x4010,0x0000 -> 0x3400
1516 geu: 0x2802,0x4010,0x0000 -> 0x2c00
1517
1518 second case:
1519 ltn: 0x3001,0x3c02,0x4010,0x0000 -> 0x3000
1520
1521 third case:
1522 gt: 0x2403,0x3802,0x4010,0x0000 -> 0x2401,0x3400
1523 gtu: 0x2403,0x2802,0x4010,0x0000 -> 0x2401,0x2c00
1524
1525 fourth case:
1526 leu: 0x2401,0x2c02,0x4010,0x0000 -> 0x2400,0x2800
1527 le: 0x2401,0x3402,0x4010,0x0000 -> 0x2400,0x3800
1528
1529 Unspecified case :)
1530 jump: 0x4010,0x0000 -> 0x3c00. */
1531
1532#define NUMB_RELAX_CODES 12
1533static struct rcodes_s
1534{
1535 int f0, f1; /* From code. */
1536 int t0, t1; /* To code. */
1537 int labels; /* Position of labels: 1 - one label at first
1538 word, 2 - one at second word, 3 - two
1539 labels at both. */
1540 int cdx; /* Words to match. */
1541 int bs; /* Shrink bytes. */
1542 int off; /* Offset from old label for new code. */
1543 int ncl; /* New code length. */
1544} rcode[] =
1545{/* lab,cdx,bs,off,ncl */
1546 { 0x0000, 0x0000, 0x3c00, 0x0000, 1, 0, 2, 2, 2}, /* jump */
1547 { 0x0000, 0x2002, 0x2400, 0x0000, 1, 1, 4, 4, 2}, /* eq */
1548 { 0x0000, 0x2402, 0x2000, 0x0000, 1, 1, 4, 4, 2}, /* ne */
1549 { 0x0000, 0x3402, 0x3800, 0x0000, 1, 1, 4, 4, 2}, /* lt */
1550 { 0x0000, 0x2c02, 0x2800, 0x0000, 1, 1, 4, 4, 2}, /* ltu */
1551 { 0x0000, 0x3802, 0x3400, 0x0000, 1, 1, 4, 4, 2}, /* ge */
1552 { 0x0000, 0x2802, 0x2c00, 0x0000, 1, 1, 4, 4, 2}, /* geu */
1553 { 0x3001, 0x3c02, 0x3000, 0x0000, 1, 2, 6, 6, 2}, /* ltn */
1554 { 0x2403, 0x3802, 0x2401, 0x3400, 2, 2, 4, 6, 4}, /* gt */
1555 { 0x2403, 0x2802, 0x2401, 0x2c00, 2, 2, 4, 6, 4}, /* gtu */
1556 { 0x2401, 0x2c02, 0x2400, 0x2800, 3, 2, 4, 6, 4}, /* leu , 2 labels */
1557 { 0x2401, 0x2c02, 0x2400, 0x2800, 3, 2, 4, 6, 4}, /* le , 2 labels */
1558 { 0, 0, 0, 0, 0, 0, 0, 0, 0}
1559};
1560
1561/* Return TRUE if a symbol exists at the given address. */
1562
1563static bfd_boolean
1564msp430_elf_symbol_address_p (bfd * abfd,
1565 asection * sec,
1566 Elf_Internal_Sym * isym,
1567 bfd_vma addr)
1568{
1569 Elf_Internal_Shdr *symtab_hdr;
1570 unsigned int sec_shndx;
1571 Elf_Internal_Sym *isymend;
1572 struct elf_link_hash_entry **sym_hashes;
1573 struct elf_link_hash_entry **end_hashes;
1574 unsigned int symcount;
1575
1576 sec_shndx = _bfd_elf_section_from_bfd_section (abfd, sec);
1577
1578 /* Examine all the local symbols. */
1579 symtab_hdr = &elf_tdata (abfd)->symtab_hdr;
1580 for (isymend = isym + symtab_hdr->sh_info; isym < isymend; isym++)
1581 if (isym->st_shndx == sec_shndx && isym->st_value == addr)
1582 return TRUE;
1583
1584 symcount = (symtab_hdr->sh_size / sizeof (Elf32_External_Sym)
1585 - symtab_hdr->sh_info);
1586 sym_hashes = elf_sym_hashes (abfd);
1587 end_hashes = sym_hashes + symcount;
1588 for (; sym_hashes < end_hashes; sym_hashes++)
1589 {
1590 struct elf_link_hash_entry *sym_hash = *sym_hashes;
1591
1592 if ((sym_hash->root.type == bfd_link_hash_defined
1593 || sym_hash->root.type == bfd_link_hash_defweak)
1594 && sym_hash->root.u.def.section == sec
1595 && sym_hash->root.u.def.value == addr)
1596 return TRUE;
1597 }
1598
1599 return FALSE;
1600}
1601
13761a11
NC		 1602/* Adjust all local symbols defined as '.section + 0xXXXX' (.section has
1603 sec_shndx) referenced from current and other sections. */
1604
046aeb74 1605static bfd_boolean
13761a11
NC		 1606msp430_elf_relax_adjust_locals (bfd * abfd, asection * sec, bfd_vma addr,
1607 int count, unsigned int sec_shndx,
1608 bfd_vma toaddr)
046aeb74
DD		 1609{
1610 Elf_Internal_Shdr *symtab_hdr;
1611 Elf_Internal_Rela *irel;
1612 Elf_Internal_Rela *irelend;
1613 Elf_Internal_Sym *isym;
1614
1615 irel = elf_section_data (sec)->relocs;
13761a11
NC		 1616 if (irel == NULL)
1617 return TRUE;
1618
046aeb74
DD		 1619 irelend = irel + sec->reloc_count;
1620 symtab_hdr = & elf_tdata (abfd)->symtab_hdr;
1621 isym = (Elf_Internal_Sym *) symtab_hdr->contents;
bceec4b9 1622
13761a11 1623 for (;irel < irelend; irel++)
046aeb74 1624 {
bceec4b9 1625 unsigned int sidx = ELF32_R_SYM(irel->r_info);
046aeb74 1626 Elf_Internal_Sym *lsym = isym + sidx;
bceec4b9 1627
1ade7175 1628 /* Adjust symbols referenced by .sec+0xXX. */
bceec4b9
DD		 1629 if (irel->r_addend > addr && irel->r_addend < toaddr
1630 && sidx < symtab_hdr->sh_info
046aeb74
DD		 1631 && lsym->st_shndx == sec_shndx)
1632 irel->r_addend -= count;
1633 }
1b786873 1634
046aeb74
DD		 1635 return TRUE;
1636}
1637
b18c562e
NC		 1638/* Delete some bytes from a section while relaxing. */
1639
1640static bfd_boolean
1641msp430_elf_relax_delete_bytes (bfd * abfd, asection * sec, bfd_vma addr,
1642 int count)
1643{
1644 Elf_Internal_Shdr *symtab_hdr;
1645 unsigned int sec_shndx;
1646 bfd_byte *contents;
1647 Elf_Internal_Rela *irel;
1648 Elf_Internal_Rela *irelend;
b18c562e
NC		 1649 bfd_vma toaddr;
1650 Elf_Internal_Sym *isym;
1651 Elf_Internal_Sym *isymend;
1652 struct elf_link_hash_entry **sym_hashes;
1653 struct elf_link_hash_entry **end_hashes;
1654 unsigned int symcount;
046aeb74 1655 asection *p;
b18c562e
NC		 1656
1657 sec_shndx = _bfd_elf_section_from_bfd_section (abfd, sec);
1658
1659 contents = elf_section_data (sec)->this_hdr.contents;
1660
b18c562e
NC		 1661 toaddr = sec->size;
1662
1663 irel = elf_section_data (sec)->relocs;
1664 irelend = irel + sec->reloc_count;
1665
1666 /* Actually delete the bytes. */
1667 memmove (contents + addr, contents + addr + count,
1668 (size_t) (toaddr - addr - count));
1669 sec->size -= count;
1670
1671 /* Adjust all the relocs. */
fa9ee72b
DD		 1672 symtab_hdr = & elf_tdata (abfd)->symtab_hdr;
1673 isym = (Elf_Internal_Sym *) symtab_hdr->contents;
13761a11 1674 for (; irel < irelend; irel++)
fa9ee72b 1675 {
fa9ee72b
DD		 1676 /* Get the new reloc address. */
1677 if ((irel->r_offset > addr && irel->r_offset < toaddr))
1678 irel->r_offset -= count;
fa9ee72b 1679 }
b18c562e 1680
046aeb74 1681 for (p = abfd->sections; p != NULL; p = p->next)
13761a11 1682 msp430_elf_relax_adjust_locals (abfd,p,addr,count,sec_shndx,toaddr);
1b786873 1683
b18c562e
NC		 1684 /* Adjust the local symbols defined in this section. */
1685 symtab_hdr = & elf_tdata (abfd)->symtab_hdr;
1686 isym = (Elf_Internal_Sym *) symtab_hdr->contents;
1687 for (isymend = isym + symtab_hdr->sh_info; isym < isymend; isym++)
0f8f0c57
NC		 1688 {
1689 const char * name;
1690
1691 name = bfd_elf_string_from_elf_section
1692 (abfd, symtab_hdr->sh_link, isym->st_name);
1693 name = (name == NULL || * name == 0) ? bfd_section_name (abfd, sec) : name;
1694
1695 if (isym->st_shndx != sec_shndx)
1696 continue;
1b786873 1697
0f8f0c57
NC		 1698 if (isym->st_value > addr
1699 && (isym->st_value < toaddr
1700 /* We also adjust a symbol at the end of the section if its name is
1701 on the list below. These symbols are used for debug info
1702 generation and they refer to the end of the current section, not
1703 the start of the next section. */
1704 || (isym->st_value == toaddr
1705 && name != NULL
1706 && (CONST_STRNEQ (name, ".Letext")
1707 || CONST_STRNEQ (name, ".LFE")))))
1708 {
1709 if (isym->st_value < addr + count)
1710 isym->st_value = addr;
1711 else
1712 isym->st_value -= count;
1713 }
1714 /* Adjust the function symbol's size as well. */
1715 else if (ELF_ST_TYPE (isym->st_info) == STT_FUNC
1716 && isym->st_value + isym->st_size > addr
1717 && isym->st_value + isym->st_size < toaddr)
1718 isym->st_size -= count;
1719 }
b18c562e
NC		 1720
1721 /* Now adjust the global symbols defined in this section. */
1722 symcount = (symtab_hdr->sh_size / sizeof (Elf32_External_Sym)
1723 - symtab_hdr->sh_info);
1724 sym_hashes = elf_sym_hashes (abfd);
1725 end_hashes = sym_hashes + symcount;
1726 for (; sym_hashes < end_hashes; sym_hashes++)
1727 {
1728 struct elf_link_hash_entry *sym_hash = *sym_hashes;
1729
1730 if ((sym_hash->root.type == bfd_link_hash_defined
1731 || sym_hash->root.type == bfd_link_hash_defweak)
1732 && sym_hash->root.u.def.section == sec
1733 && sym_hash->root.u.def.value > addr
1734 && sym_hash->root.u.def.value < toaddr)
0f8f0c57
NC		 1735 {
1736 if (sym_hash->root.u.def.value < addr + count)
1737 sym_hash->root.u.def.value = addr;
1738 else
1739 sym_hash->root.u.def.value -= count;
1740 }
1741 /* Adjust the function symbol's size as well. */
1742 else if (sym_hash->root.type == bfd_link_hash_defined
1743 && sym_hash->root.u.def.section == sec
1744 && sym_hash->type == STT_FUNC
1745 && sym_hash->root.u.def.value + sym_hash->size > addr
1746 && sym_hash->root.u.def.value + sym_hash->size < toaddr)
1747 sym_hash->size -= count;
b18c562e
NC		 1748 }
1749
1750 return TRUE;
1751}
1752
13761a11
NC		 1753/* Insert two words into a section whilst relaxing. */
1754
1755static bfd_byte *
1756msp430_elf_relax_add_two_words (bfd * abfd, asection * sec, bfd_vma addr,
1757 int word1, int word2)
1758{
1759 Elf_Internal_Shdr *symtab_hdr;
1760 unsigned int sec_shndx;
1761 bfd_byte *contents;
1762 Elf_Internal_Rela *irel;
1763 Elf_Internal_Rela *irelend;
1764 Elf_Internal_Sym *isym;
1765 Elf_Internal_Sym *isymend;
1766 struct elf_link_hash_entry **sym_hashes;
1767 struct elf_link_hash_entry **end_hashes;
1768 unsigned int symcount;
1769 bfd_vma sec_end;
1770 asection *p;
1771
1772 contents = elf_section_data (sec)->this_hdr.contents;
1773 sec_end = sec->size;
1774
1775 /* Make space for the new words. */
1776 contents = bfd_realloc (contents, sec_end + 4);
1777 memmove (contents + addr + 4, contents + addr, sec_end - addr);
1778
1779 /* Insert the new words. */
1780 bfd_put_16 (abfd, word1, contents + addr);
1781 bfd_put_16 (abfd, word2, contents + addr + 2);
1782
1783 /* Update the section information. */
1784 sec->size += 4;
1b786873 1785 elf_section_data (sec)->this_hdr.contents = contents;
13761a11
NC		 1786
1787 /* Adjust all the relocs. */
1788 irel = elf_section_data (sec)->relocs;
1789 irelend = irel + sec->reloc_count;
1790
1791 for (; irel < irelend; irel++)
1792 if ((irel->r_offset >= addr && irel->r_offset < sec_end))
1793 irel->r_offset += 4;
1794
1795 /* Adjust the local symbols defined in this section. */
1796 sec_shndx = _bfd_elf_section_from_bfd_section (abfd, sec);
1797 for (p = abfd->sections; p != NULL; p = p->next)
1798 msp430_elf_relax_adjust_locals (abfd, p, addr, -4,
1799 sec_shndx, sec_end);
1800
1801 /* Adjust the global symbols affected by the move. */
1802 symtab_hdr = & elf_tdata (abfd)->symtab_hdr;
1803 isym = (Elf_Internal_Sym *) symtab_hdr->contents;
1804 for (isymend = isym + symtab_hdr->sh_info; isym < isymend; isym++)
1805 if (isym->st_shndx == sec_shndx
1806 && isym->st_value >= addr && isym->st_value < sec_end)
1807 isym->st_value += 4;
1808
1809 /* Now adjust the global symbols defined in this section. */
1810 symcount = (symtab_hdr->sh_size / sizeof (Elf32_External_Sym)
1811 - symtab_hdr->sh_info);
1812 sym_hashes = elf_sym_hashes (abfd);
1813 end_hashes = sym_hashes + symcount;
1814 for (; sym_hashes < end_hashes; sym_hashes++)
1815 {
1816 struct elf_link_hash_entry *sym_hash = *sym_hashes;
1817
1818 if ((sym_hash->root.type == bfd_link_hash_defined
1819 || sym_hash->root.type == bfd_link_hash_defweak)
1820 && sym_hash->root.u.def.section == sec
1821 && sym_hash->root.u.def.value >= addr
1822 && sym_hash->root.u.def.value < sec_end)
1823 sym_hash->root.u.def.value += 4;
1824 }
1825
1826 return contents;
1827}
1b786873 1828
b18c562e
NC		 1829static bfd_boolean
1830msp430_elf_relax_section (bfd * abfd, asection * sec,
1831 struct bfd_link_info * link_info,
1832 bfd_boolean * again)
1833{
1834 Elf_Internal_Shdr * symtab_hdr;
1835 Elf_Internal_Rela * internal_relocs;
1836 Elf_Internal_Rela * irel;
1837 Elf_Internal_Rela * irelend;
1838 bfd_byte * contents = NULL;
1839 Elf_Internal_Sym * isymbuf = NULL;
1840
1841 /* Assume nothing changes. */
1842 *again = FALSE;
1843
1844 /* We don't have to do anything for a relocatable link, if
1845 this section does not have relocs, or if this is not a
1846 code section. */
0e1862bb 1847 if (bfd_link_relocatable (link_info)
13761a11
NC		 1848 || (sec->flags & SEC_RELOC) == 0
1849 || sec->reloc_count == 0 || (sec->flags & SEC_CODE) == 0)
b18c562e
NC		 1850 return TRUE;
1851
1852 symtab_hdr = & elf_tdata (abfd)->symtab_hdr;
1853
1854 /* Get a copy of the native relocations. */
1855 internal_relocs =
1856 _bfd_elf_link_read_relocs (abfd, sec, NULL, NULL, link_info->keep_memory);
1857 if (internal_relocs == NULL)
1858 goto error_return;
1859
1860 /* Walk through them looking for relaxing opportunities. */
1861 irelend = internal_relocs + sec->reloc_count;
13761a11
NC		 1862
1863 /* Do code size growing relocs first. */
b18c562e
NC		 1864 for (irel = internal_relocs; irel < irelend; irel++)
1865 {
1866 bfd_vma symval;
1867
1868 /* If this isn't something that can be relaxed, then ignore
1869 this reloc. */
13761a11
NC		 1870 if (uses_msp430x_relocs (abfd)
1871 && ELF32_R_TYPE (irel->r_info) == (int) R_MSP430X_10_PCREL)
1872 ;
1873 else if (! uses_msp430x_relocs (abfd)
1874 && ELF32_R_TYPE (irel->r_info) == (int) R_MSP430_10_PCREL)
1875 ;
1876 else
b18c562e
NC		 1877 continue;
1878
1879 /* Get the section contents if we haven't done so already. */
1880 if (contents == NULL)
1881 {
1882 /* Get cached copy if it exists. */
1883 if (elf_section_data (sec)->this_hdr.contents != NULL)
1884 contents = elf_section_data (sec)->this_hdr.contents;
1885 else if (! bfd_malloc_and_get_section (abfd, sec, &contents))
1886 goto error_return;
1887 }
1888
1889 /* Read this BFD's local symbols if we haven't done so already. */
1890 if (isymbuf == NULL && symtab_hdr->sh_info != 0)
1891 {
1892 isymbuf = (Elf_Internal_Sym *) symtab_hdr->contents;
1893 if (isymbuf == NULL)
1894 isymbuf = bfd_elf_get_elf_syms (abfd, symtab_hdr,
1895 symtab_hdr->sh_info, 0,
1896 NULL, NULL, NULL);
1897 if (isymbuf == NULL)
1898 goto error_return;
1899 }
1900
1901 /* Get the value of the symbol referred to by the reloc. */
1902 if (ELF32_R_SYM (irel->r_info) < symtab_hdr->sh_info)
1903 {
1904 /* A local symbol. */
1905 Elf_Internal_Sym *isym;
1906 asection *sym_sec;
1907
1908 isym = isymbuf + ELF32_R_SYM (irel->r_info);
1909 if (isym->st_shndx == SHN_UNDEF)
1910 sym_sec = bfd_und_section_ptr;
1911 else if (isym->st_shndx == SHN_ABS)
1912 sym_sec = bfd_abs_section_ptr;
1913 else if (isym->st_shndx == SHN_COMMON)
1914 sym_sec = bfd_com_section_ptr;
1915 else
1916 sym_sec = bfd_section_from_elf_index (abfd, isym->st_shndx);
1917 symval = (isym->st_value
1918 + sym_sec->output_section->vma + sym_sec->output_offset);
1919 }
1920 else
1921 {
1922 unsigned long indx;
1923 struct elf_link_hash_entry *h;
1924
1925 /* An external symbol. */
1926 indx = ELF32_R_SYM (irel->r_info) - symtab_hdr->sh_info;
1927 h = elf_sym_hashes (abfd)[indx];
1928 BFD_ASSERT (h != NULL);
1929
1930 if (h->root.type != bfd_link_hash_defined
1931 && h->root.type != bfd_link_hash_defweak)
1932 /* This appears to be a reference to an undefined
1933 symbol. Just ignore it--it will be caught by the
1934 regular reloc processing. */
1935 continue;
1936
1937 symval = (h->root.u.def.value
1938 + h->root.u.def.section->output_section->vma
1939 + h->root.u.def.section->output_offset);
1940 }
1941
1942 /* For simplicity of coding, we are going to modify the section
1943 contents, the section relocs, and the BFD symbol table. We
1944 must tell the rest of the code not to free up this
1945 information. It would be possible to instead create a table
1946 of changes which have to be made, as is done in coff-mips.c;
1947 that would be more work, but would require less memory when
1948 the linker is run. */
1949
13761a11
NC		 1950 bfd_signed_vma value = symval;
1951 int opcode;
b18c562e 1952
13761a11
NC		 1953 /* Compute the value that will be relocated. */
1954 value += irel->r_addend;
1955 /* Convert to PC relative. */
1956 value -= (sec->output_section->vma + sec->output_offset);
1957 value -= irel->r_offset;
1958 value -= 2;
1959 /* Scale. */
1960 value >>= 1;
b18c562e 1961
13761a11
NC		 1962 /* If it is in range then no modifications are needed. */
1963 if (value >= -512 && value <= 511)
1964 continue;
b18c562e 1965
13761a11
NC		 1966 /* Get the opcode. */
1967 opcode = bfd_get_16 (abfd, contents + irel->r_offset);
1b786873 1968
13761a11
NC		 1969 /* Compute the new opcode. We are going to convert:
1970 J<cond> label
1971 into:
1972 J<inv-cond> 1f
1973 BR[A] #label
1974 1: */
1975 switch (opcode & 0xfc00)
1976 {
1b786873 1977 case 0x3800: opcode = 0x3402; break; /* Jl -> Jge +2 */
13761a11
NC		 1978 case 0x3400: opcode = 0x3802; break; /* Jge -> Jl +2 */
1979 case 0x2c00: opcode = 0x2802; break; /* Jhs -> Jlo +2 */
1980 case 0x2800: opcode = 0x2c02; break; /* Jlo -> Jhs +2 */
1981 case 0x2400: opcode = 0x2002; break; /* Jeq -> Jne +2 */
1982 case 0x2000: opcode = 0x2402; break; /* jne -> Jeq +2 */
1983 case 0x3000: /* jn */
1984 /* There is no direct inverse of the Jn insn.
1985 FIXME: we could do this as:
1986 Jn 1f
1987 br 2f
1988 1: br label
1989 2: */
1990 continue;
1991 default:
1992 /* Not a conditional branch instruction. */
1993 /* fprintf (stderr, "unrecog: %x\n", opcode); */
2d071cfc 1994 continue;
13761a11 1995 }
b18c562e 1996
13761a11
NC		 1997 /* Note that we've changed the relocs, section contents, etc. */
1998 elf_section_data (sec)->relocs = internal_relocs;
1999 elf_section_data (sec)->this_hdr.contents = contents;
2000 symtab_hdr->contents = (unsigned char *) isymbuf;
b18c562e 2001
13761a11
NC		 2002 /* Install the new opcode. */
2003 bfd_put_16 (abfd, opcode, contents + irel->r_offset);
b18c562e 2004
13761a11
NC		 2005 /* Insert the new branch instruction. */
2006 if (uses_msp430x_relocs (abfd))
2007 {
1b786873 2008 /* Insert an absolute branch (aka MOVA) instruction. */
13761a11
NC		 2009 contents = msp430_elf_relax_add_two_words
2010 (abfd, sec, irel->r_offset + 2, 0x0080, 0x0000);
2011
2012 /* Update the relocation to point to the inserted branch
2013 instruction. Note - we are changing a PC-relative reloc
2014 into an absolute reloc, but this is OK because we have
2015 arranged with the assembler to have the reloc's value be
2016 a (local) symbol, not a section+offset value. */
2017 irel->r_offset += 2;
2018 irel->r_info = ELF32_R_INFO (ELF32_R_SYM (irel->r_info),
2019 R_MSP430X_ABS20_ADR_SRC);
2020 }
2021 else
2022 {
2023 contents = msp430_elf_relax_add_two_words
2024 (abfd, sec, irel->r_offset + 2, 0x4030, 0x0000);
2025
2026 /* See comment above about converting a 10-bit PC-rel
2027 relocation into a 16-bit absolute relocation. */
2028 irel->r_offset += 4;
2029 irel->r_info = ELF32_R_INFO (ELF32_R_SYM (irel->r_info),
2030 R_MSP430_16);
2031 }
b18c562e 2032
13761a11
NC		 2033 /* Growing the section may mean that other
2034 conditional branches need to be fixed. */
2035 *again = TRUE;
2036 }
b18c562e 2037
13761a11
NC		 2038 for (irel = internal_relocs; irel < irelend; irel++)
2039 {
2040 bfd_vma symval;
2041
2042 /* Get the section contents if we haven't done so already. */
2043 if (contents == NULL)
2044 {
2045 /* Get cached copy if it exists. */
2046 if (elf_section_data (sec)->this_hdr.contents != NULL)
2047 contents = elf_section_data (sec)->this_hdr.contents;
2048 else if (! bfd_malloc_and_get_section (abfd, sec, &contents))
2049 goto error_return;
2050 }
2051
2052 /* Read this BFD's local symbols if we haven't done so already. */
2053 if (isymbuf == NULL && symtab_hdr->sh_info != 0)
2054 {
2055 isymbuf = (Elf_Internal_Sym *) symtab_hdr->contents;
2056 if (isymbuf == NULL)
2057 isymbuf = bfd_elf_get_elf_syms (abfd, symtab_hdr,
2058 symtab_hdr->sh_info, 0,
2059 NULL, NULL, NULL);
2060 if (isymbuf == NULL)
2061 goto error_return;
2062 }
2063
2064 /* Get the value of the symbol referred to by the reloc. */
2065 if (ELF32_R_SYM (irel->r_info) < symtab_hdr->sh_info)
2066 {
2067 /* A local symbol. */
2068 Elf_Internal_Sym *isym;
2069 asection *sym_sec;
2070
2071 isym = isymbuf + ELF32_R_SYM (irel->r_info);
2072 if (isym->st_shndx == SHN_UNDEF)
2073 sym_sec = bfd_und_section_ptr;
2074 else if (isym->st_shndx == SHN_ABS)
2075 sym_sec = bfd_abs_section_ptr;
2076 else if (isym->st_shndx == SHN_COMMON)
2077 sym_sec = bfd_com_section_ptr;
2078 else
2079 sym_sec = bfd_section_from_elf_index (abfd, isym->st_shndx);
2080 symval = (isym->st_value
2081 + sym_sec->output_section->vma + sym_sec->output_offset);
2082 }
2083 else
2084 {
2085 unsigned long indx;
2086 struct elf_link_hash_entry *h;
2087
2088 /* An external symbol. */
2089 indx = ELF32_R_SYM (irel->r_info) - symtab_hdr->sh_info;
2090 h = elf_sym_hashes (abfd)[indx];
2091 BFD_ASSERT (h != NULL);
2092
2093 if (h->root.type != bfd_link_hash_defined
2094 && h->root.type != bfd_link_hash_defweak)
2095 /* This appears to be a reference to an undefined
2096 symbol. Just ignore it--it will be caught by the
2097 regular reloc processing. */
2098 continue;
2099
2100 symval = (h->root.u.def.value
2101 + h->root.u.def.section->output_section->vma
2102 + h->root.u.def.section->output_offset);
2103 }
2104
2105 /* For simplicity of coding, we are going to modify the section
2106 contents, the section relocs, and the BFD symbol table. We
2107 must tell the rest of the code not to free up this
2108 information. It would be possible to instead create a table
2109 of changes which have to be made, as is done in coff-mips.c;
2110 that would be more work, but would require less memory when
2111 the linker is run. */
2112
2113 /* Try to turn a 16bit pc-relative branch into a 10bit pc-relative
2114 branch. */
1b786873 2115 /* Paranoia? paranoia... */
23d4663e
NC		 2116 if (! uses_msp430x_relocs (abfd)
2117 && ELF32_R_TYPE (irel->r_info) == (int) R_MSP430_RL_PCREL)
13761a11
NC		 2118 {
2119 bfd_vma value = symval;
2120
2121 /* Deal with pc-relative gunk. */
2122 value -= (sec->output_section->vma + sec->output_offset);
2123 value -= irel->r_offset;
2124 value += irel->r_addend;
2125
2126 /* See if the value will fit in 10 bits, note the high value is
2127 1016 as the target will be two bytes closer if we are
2128 able to relax. */
2129 if ((long) value < 1016 && (long) value > -1016)
2130 {
2131 int code0 = 0, code1 = 0, code2 = 0;
2132 int i;
2133 struct rcodes_s *rx;
2134
2135 /* Get the opcode. */
2136 if (irel->r_offset >= 6)
2137 code0 = bfd_get_16 (abfd, contents + irel->r_offset - 6);
2138
2139 if (irel->r_offset >= 4)
2140 code1 = bfd_get_16 (abfd, contents + irel->r_offset - 4);
2141
2142 code2 = bfd_get_16 (abfd, contents + irel->r_offset - 2);
2143
2144 if (code2 != 0x4010)
2145 continue;
2146
2147 /* Check r4 and r3. */
2148 for (i = NUMB_RELAX_CODES - 1; i >= 0; i--)
2149 {
2150 rx = &rcode[i];
2151 if (rx->cdx == 2 && rx->f0 == code0 && rx->f1 == code1)
2152 break;
2153 else if (rx->cdx == 1 && rx->f1 == code1)
2154 break;
2155 else if (rx->cdx == 0) /* This is an unconditional jump. */
2156 break;
2157 }
2158
2159 /* Check labels:
b18c562e 2160 .Label0: ; we do not care about this label
13761a11 2161 jeq +6
b18c562e 2162 .Label1: ; make sure there is no label here
13761a11 2163 jl +4
b18c562e 2164 .Label2: ; make sure there is no label here
13761a11
NC		 2165 br .Label_dst
2166
2167 So, if there is .Label1 or .Label2 we cannot relax this code.
2168 This actually should not happen, cause for relaxable
2169 instructions we use RL_PCREL reloc instead of 16_PCREL.
2170 Will change this in the future. */
2171
2172 if (rx->cdx > 0
2173 && msp430_elf_symbol_address_p (abfd, sec, isymbuf,
2174 irel->r_offset - 2))
2175 continue;
2176 if (rx->cdx > 1
2177 && msp430_elf_symbol_address_p (abfd, sec, isymbuf,
2178 irel->r_offset - 4))
2179 continue;
2180
2181 /* Note that we've changed the relocs, section contents, etc. */
2182 elf_section_data (sec)->relocs = internal_relocs;
2183 elf_section_data (sec)->this_hdr.contents = contents;
2184 symtab_hdr->contents = (unsigned char *) isymbuf;
2185
2186 /* Fix the relocation's type. */
2187 if (uses_msp430x_relocs (abfd))
2188 {
2189 if (rx->labels == 3) /* Handle special cases. */
2190 irel->r_info = ELF32_R_INFO (ELF32_R_SYM (irel->r_info),
2191 R_MSP430X_2X_PCREL);
2192 else
2193 irel->r_info = ELF32_R_INFO (ELF32_R_SYM (irel->r_info),
2194 R_MSP430X_10_PCREL);
2195 }
2196 else
2197 {
2198 if (rx->labels == 3) /* Handle special cases. */
2199 irel->r_info = ELF32_R_INFO (ELF32_R_SYM (irel->r_info),
2200 R_MSP430_2X_PCREL);
2201 else
2202 irel->r_info = ELF32_R_INFO (ELF32_R_SYM (irel->r_info),
2203 R_MSP430_10_PCREL);
2204 }
2205
2206 /* Fix the opcode right way. */
2207 bfd_put_16 (abfd, rx->t0, contents + irel->r_offset - rx->off);
2208 if (rx->t1)
2209 bfd_put_16 (abfd, rx->t1,
2210 contents + irel->r_offset - rx->off + 2);
2211
2212 /* Delete bytes. */
2213 if (!msp430_elf_relax_delete_bytes (abfd, sec,
2214 irel->r_offset - rx->off +
2215 rx->ncl, rx->bs))
2216 goto error_return;
2217
2218 /* Handle unconditional jumps. */
2219 if (rx->cdx == 0)
2220 irel->r_offset -= 2;
2221
2222 /* That will change things, so, we should relax again.
2223 Note that this is not required, and it may be slow. */
2224 *again = TRUE;
2225 }
2226 }
23d4663e
NC		 2227
2228 /* Try to turn a 16-bit absolute branch into a 10-bit pc-relative
2229 branch. */
2230 if (uses_msp430x_relocs (abfd)
2231 && ELF32_R_TYPE (irel->r_info) == R_MSP430X_ABS16)
2232 {
2233 bfd_vma value = symval;
2234
2d071cfc 2235 value -= (sec->output_section->vma + sec->output_offset);
23d4663e
NC		 2236 value -= irel->r_offset;
2237 value += irel->r_addend;
1b786873 2238
23d4663e
NC		 2239 /* See if the value will fit in 10 bits, note the high value is
2240 1016 as the target will be two bytes closer if we are
2241 able to relax. */
2242 if ((long) value < 1016 && (long) value > -1016)
2243 {
2244 int code2;
2245
2246 /* Get the opcode. */
2247 code2 = bfd_get_16 (abfd, contents + irel->r_offset - 2);
2248 if (code2 != 0x4030)
2249 continue;
2250 /* FIXME: check r4 and r3 ? */
2251 /* FIXME: Handle 0x4010 as well ? */
2252
2253 /* Note that we've changed the relocs, section contents, etc. */
2254 elf_section_data (sec)->relocs = internal_relocs;
2255 elf_section_data (sec)->this_hdr.contents = contents;
2256 symtab_hdr->contents = (unsigned char *) isymbuf;
2257
2258 /* Fix the relocation's type. */
2259 if (uses_msp430x_relocs (abfd))
2260 {
2261 irel->r_info = ELF32_R_INFO (ELF32_R_SYM (irel->r_info),
2262 R_MSP430X_10_PCREL);
2263 }
2264 else
2265 {
2266 irel->r_info = ELF32_R_INFO (ELF32_R_SYM (irel->r_info),
2267 R_MSP430_10_PCREL);
2268 }
2269
2270 /* Fix the opcode right way. */
2271 bfd_put_16 (abfd, 0x3c00, contents + irel->r_offset - 2);
2272 irel->r_offset -= 2;
2273
2274 /* Delete bytes. */
2275 if (!msp430_elf_relax_delete_bytes (abfd, sec,
2276 irel->r_offset + 2, 2))
2277 goto error_return;
2278
2279 /* That will change things, so, we should relax again.
2280 Note that this is not required, and it may be slow. */
2281 *again = TRUE;
2282 }
2283 }
13761a11 2284 }
b18c562e
NC		 2285
2286 if (isymbuf != NULL && symtab_hdr->contents != (unsigned char *) isymbuf)
2287 {
2288 if (!link_info->keep_memory)
2289 free (isymbuf);
2290 else
2291 {
2292 /* Cache the symbols for elf_link_input_bfd. */
2293 symtab_hdr->contents = (unsigned char *) isymbuf;
2294 }
2295 }
2296
2297 if (contents != NULL
2298 && elf_section_data (sec)->this_hdr.contents != contents)
2299 {
2300 if (!link_info->keep_memory)
2301 free (contents);
2302 else
2303 {
2304 /* Cache the section contents for elf_link_input_bfd. */
2305 elf_section_data (sec)->this_hdr.contents = contents;
2306 }
2307 }
2308
2309 if (internal_relocs != NULL
2310 && elf_section_data (sec)->relocs != internal_relocs)
2311 free (internal_relocs);
2312
2313 return TRUE;
2314
2315error_return:
2316 if (isymbuf != NULL && symtab_hdr->contents != (unsigned char *) isymbuf)
2317 free (isymbuf);
2318 if (contents != NULL
2319 && elf_section_data (sec)->this_hdr.contents != contents)
2320 free (contents);
2321 if (internal_relocs != NULL
2322 && elf_section_data (sec)->relocs != internal_relocs)
2323 free (internal_relocs);
2324
2325 return FALSE;
2326}
2327
13761a11
NC		 2328/* Handle an MSP430 specific section when reading an object file.
2329 This is called when bfd_section_from_shdr finds a section with
2330 an unknown type. */
2331
2332static bfd_boolean
2333elf32_msp430_section_from_shdr (bfd *abfd,
2334 Elf_Internal_Shdr * hdr,
2335 const char *name,
2336 int shindex)
2337{
2338 switch (hdr->sh_type)
2339 {
2340 case SHT_MSP430_SEC_FLAGS:
2341 case SHT_MSP430_SYM_ALIASES:
2342 case SHT_MSP430_ATTRIBUTES:
2343 return _bfd_elf_make_section_from_shdr (abfd, hdr, name, shindex);
2344 default:
2345 return FALSE;
2346 }
2347}
2348
2349static bfd_boolean
2350elf32_msp430_obj_attrs_handle_unknown (bfd *abfd, int tag)
2351{
2352 _bfd_error_handler
695344c0 2353 /* xgettext:c-format */
13761a11
NC		 2354 (_("Warning: %B: Unknown MSPABI object attribute %d"),
2355 abfd, tag);
2356 return TRUE;
2357}
2358
2359/* Determine whether an object attribute tag takes an integer, a
2360 string or both. */
2361
2362static int
2363elf32_msp430_obj_attrs_arg_type (int tag)
2364{
2365 if (tag == Tag_compatibility)
2366 return ATTR_TYPE_FLAG_INT_VAL | ATTR_TYPE_FLAG_STR_VAL;
2367
2368 if (tag < 32)
2369 return ATTR_TYPE_FLAG_INT_VAL;
2370
2371 return (tag & 1) != 0 ? ATTR_TYPE_FLAG_STR_VAL : ATTR_TYPE_FLAG_INT_VAL;
2372}
2373
2374static inline const char *
2375isa_type (int isa)
2376{
2377 switch (isa)
2378 {
2379 case 1: return "MSP430";
2380 case 2: return "MSP430X";
2381 default: return "unknown";
2382 }
2383}
2384
2385static inline const char *
2386code_model (int model)
2387{
2388 switch (model)
2389 {
2390 case 1: return "small";
2391 case 2: return "large";
2392 default: return "unknown";
2393 }
2394}
2395
2396static inline const char *
2397data_model (int model)
2398{
2399 switch (model)
2400 {
2401 case 1: return "small";
2402 case 2: return "large";
2403 case 3: return "restricted large";
2404 default: return "unknown";
2405 }
2406}
2407
2408/* Merge MSPABI object attributes from IBFD into OBFD.
2409 Raise an error if there are conflicting attributes. */
2410
2411static bfd_boolean
50e03d47 2412elf32_msp430_merge_mspabi_attributes (bfd *ibfd, struct bfd_link_info *info)
13761a11 2413{
50e03d47 2414 bfd *obfd = info->output_bfd;
13761a11
NC		 2415 obj_attribute *in_attr;
2416 obj_attribute *out_attr;
2417 bfd_boolean result = TRUE;
2418 static bfd * first_input_bfd = NULL;
2419
2420 /* Skip linker created files. */
2421 if (ibfd->flags & BFD_LINKER_CREATED)
2422 return TRUE;
2423
2424 /* If this is the first real object just copy the attributes. */
2425 if (!elf_known_obj_attributes_proc (obfd)[0].i)
2426 {
2427 _bfd_elf_copy_obj_attributes (ibfd, obfd);
2428
2429 out_attr = elf_known_obj_attributes_proc (obfd);
2430
2431 /* Use the Tag_null value to indicate that
2432 the attributes have been initialized. */
2433 out_attr[0].i = 1;
2434
2435 first_input_bfd = ibfd;
2436 return TRUE;
2437 }
2438
2439 in_attr = elf_known_obj_attributes_proc (ibfd);
2440 out_attr = elf_known_obj_attributes_proc (obfd);
2441
2442 /* The ISAs must be the same. */
2443 if (in_attr[OFBA_MSPABI_Tag_ISA].i != out_attr[OFBA_MSPABI_Tag_ISA].i)
2444 {
2445 _bfd_error_handler
695344c0 2446 /* xgettext:c-format */
13761a11
NC		 2447 (_("error: %B uses %s instructions but %B uses %s"),
2448 ibfd, first_input_bfd,
2449 isa_type (in_attr[OFBA_MSPABI_Tag_ISA].i),
2450 isa_type (out_attr[OFBA_MSPABI_Tag_ISA].i));
2451 result = FALSE;
2452 }
2453
2454 /* The code models must be the same. */
2455 if (in_attr[OFBA_MSPABI_Tag_Code_Model].i !=
2456 out_attr[OFBA_MSPABI_Tag_Code_Model].i)
2457 {
2458 _bfd_error_handler
695344c0 2459 /* xgettext:c-format */
13761a11
NC		 2460 (_("error: %B uses the %s code model whereas %B uses the %s code model"),
2461 ibfd, first_input_bfd,
2462 code_model (in_attr[OFBA_MSPABI_Tag_Code_Model].i),
2463 code_model (out_attr[OFBA_MSPABI_Tag_Code_Model].i));
2464 result = FALSE;
2465 }
2466
2467 /* The large code model is only supported by the MSP430X. */
2468 if (in_attr[OFBA_MSPABI_Tag_Code_Model].i == 2
2469 && out_attr[OFBA_MSPABI_Tag_ISA].i != 2)
2470 {
2471 _bfd_error_handler
695344c0 2472 /* xgettext:c-format */
13761a11
NC		 2473 (_("error: %B uses the large code model but %B uses MSP430 instructions"),
2474 ibfd, first_input_bfd);
2475 result = FALSE;
2476 }
2477
2478 /* The data models must be the same. */
2479 if (in_attr[OFBA_MSPABI_Tag_Data_Model].i !=
2480 out_attr[OFBA_MSPABI_Tag_Data_Model].i)
2481 {
2482 _bfd_error_handler
695344c0 2483 /* xgettext:c-format */
13761a11
NC		 2484 (_("error: %B uses the %s data model whereas %B uses the %s data model"),
2485 ibfd, first_input_bfd,
2486 data_model (in_attr[OFBA_MSPABI_Tag_Data_Model].i),
2487 data_model (out_attr[OFBA_MSPABI_Tag_Data_Model].i));
2488 result = FALSE;
2489 }
2490
2491 /* The small code model requires the use of the small data model. */
2492 if (in_attr[OFBA_MSPABI_Tag_Code_Model].i == 1
2493 && out_attr[OFBA_MSPABI_Tag_Data_Model].i != 1)
2494 {
2495 _bfd_error_handler
695344c0 2496 /* xgettext:c-format */
13761a11
NC		 2497 (_("error: %B uses the small code model but %B uses the %s data model"),
2498 ibfd, first_input_bfd,
2499 data_model (out_attr[OFBA_MSPABI_Tag_Data_Model].i));
2500 result = FALSE;
2501 }
2502
2503 /* The large data models are only supported by the MSP430X. */
2504 if (in_attr[OFBA_MSPABI_Tag_Data_Model].i > 1
2505 && out_attr[OFBA_MSPABI_Tag_ISA].i != 2)
2506 {
2507 _bfd_error_handler
695344c0 2508 /* xgettext:c-format */
13761a11
NC		 2509 (_("error: %B uses the %s data model but %B only uses MSP430 instructions"),
2510 ibfd, first_input_bfd,
2511 data_model (in_attr[OFBA_MSPABI_Tag_Data_Model].i));
2512 result = FALSE;
2513 }
1b786873 2514
13761a11
NC		 2515 return result;
2516}
2517
2518/* Merge backend specific data from an object file to the output
2519 object file when linking. */
2520
2521static bfd_boolean
50e03d47 2522elf32_msp430_merge_private_bfd_data (bfd *ibfd, struct bfd_link_info *info)
13761a11 2523{
50e03d47 2524 bfd *obfd = info->output_bfd;
13761a11
NC		 2525 /* Make sure that the machine number reflects the most
2526 advanced version of the MSP architecture required. */
2527#define max(a,b) ((a) > (b) ? (a) : (b))
2528 if (bfd_get_mach (ibfd) != bfd_get_mach (obfd))
2529 bfd_default_set_arch_mach (obfd, bfd_get_arch (obfd),
2530 max (bfd_get_mach (ibfd), bfd_get_mach (obfd)));
2531#undef max
2532
50e03d47 2533 return elf32_msp430_merge_mspabi_attributes (ibfd, info);
13761a11
NC		 2534}
2535
13761a11
NC		 2536static bfd_boolean
2537msp430_elf_is_target_special_symbol (bfd *abfd, asymbol *sym)
2538{
2539 return _bfd_elf_is_local_label_name (abfd, sym->name);
2540}
2541
79559014
NC		 2542static bfd_boolean
2543uses_large_model (bfd *abfd)
2544{
2545 obj_attribute * attr;
2546
2547 if (abfd->flags & BFD_LINKER_CREATED)
2548 return FALSE;
2549
2550 attr = elf_known_obj_attributes_proc (abfd);
2551 if (attr == NULL)
2552 return FALSE;
2553
2554 return attr[OFBA_MSPABI_Tag_Code_Model].i == 2;
2555}
2556
2557static unsigned int
2558elf32_msp430_eh_frame_address_size (bfd *abfd, asection *sec ATTRIBUTE_UNUSED)
2559{
2560 return uses_large_model (abfd) ? 4 : 2;
2561}
2562
13761a11
NC		 2563/* This is gross. The MSP430 EABI says that (sec 11.5):
2564
2565 "An implementation may choose to use Rel or Rela
2566 type relocations for other relocations."
2567
2568 But it also says that:
1b786873 2569
13761a11
NC		 2570 "Certain relocations are identified as Rela only. [snip]
2571 Where Rela is specified, an implementation must honor
2572 this requirement."
2573
2574 There is one relocation marked as requiring RELA - R_MSP430_ABS_HI16 - but
2575 to keep things simple we choose to use RELA relocations throughout. The
2576 problem is that the TI compiler generates REL relocations, so we have to
2577 be able to accept those as well. */
2578
2579#define elf_backend_may_use_rel_p 1
2580#define elf_backend_may_use_rela_p 1
2581#define elf_backend_default_use_rela_p 1
2582
2583#undef elf_backend_obj_attrs_vendor
2584#define elf_backend_obj_attrs_vendor "mspabi"
2585#undef elf_backend_obj_attrs_section
2586#define elf_backend_obj_attrs_section ".MSP430.attributes"
2587#undef elf_backend_obj_attrs_section_type
2588#define elf_backend_obj_attrs_section_type SHT_MSP430_ATTRIBUTES
2589#define elf_backend_section_from_shdr elf32_msp430_section_from_shdr
2590#define elf_backend_obj_attrs_handle_unknown elf32_msp430_obj_attrs_handle_unknown
2591#undef elf_backend_obj_attrs_arg_type
2592#define elf_backend_obj_attrs_arg_type elf32_msp430_obj_attrs_arg_type
13761a11 2593#define bfd_elf32_bfd_merge_private_bfd_data elf32_msp430_merge_private_bfd_data
79559014 2594#define elf_backend_eh_frame_address_size elf32_msp430_eh_frame_address_size
2469cfa2
NC		 2595
2596#define ELF_ARCH bfd_arch_msp430
2597#define ELF_MACHINE_CODE EM_MSP430
2598#define ELF_MACHINE_ALT1 EM_MSP430_OLD
13761a11 2599#define ELF_MAXPAGESIZE 4
d1036acb 2600#define ELF_OSABI ELFOSABI_STANDALONE
2469cfa2 2601
6d00b590 2602#define TARGET_LITTLE_SYM msp430_elf32_vec
2469cfa2
NC		 2603#define TARGET_LITTLE_NAME "elf32-msp430"
2604
2605#define elf_info_to_howto msp430_info_to_howto_rela
2606#define elf_info_to_howto_rel NULL
2607#define elf_backend_relocate_section elf32_msp430_relocate_section
2469cfa2
NC		 2608#define elf_backend_check_relocs elf32_msp430_check_relocs
2609#define elf_backend_can_gc_sections 1
2610#define elf_backend_final_write_processing bfd_elf_msp430_final_write_processing
2611#define elf_backend_object_p elf32_msp430_object_p
b18c562e 2612#define bfd_elf32_bfd_relax_section msp430_elf_relax_section
13761a11
NC		 2613#define bfd_elf32_bfd_is_target_special_symbol msp430_elf_is_target_special_symbol
2614
2615#undef elf32_bed
2616#define elf32_bed elf32_msp430_bed
2617
2618#include "elf32-target.h"
2619
2620/* The TI compiler sets the OSABI field to ELFOSABI_NONE. */
2621#undef TARGET_LITTLE_SYM
6d00b590 2622#define TARGET_LITTLE_SYM msp430_elf32_ti_vec
13761a11
NC		 2623
2624#undef elf32_bed
2625#define elf32_bed elf32_msp430_ti_bed
2626
1b786873 2627#undef ELF_OSABI
13761a11
NC		 2628#define ELF_OSABI ELFOSABI_NONE
2629
2630static const struct bfd_elf_special_section msp430_ti_elf_special_sections[] =
2631{
2632 /* prefix, prefix_length, suffix_len, type, attributes. */
2633 { STRING_COMMA_LEN (".TI.symbol.alias"), 0, SHT_MSP430_SYM_ALIASES, 0 },
2634 { STRING_COMMA_LEN (".TI.section.flags"), 0, SHT_MSP430_SEC_FLAGS, 0 },
2635 { STRING_COMMA_LEN ("_TI_build_attrib"), 0, SHT_MSP430_ATTRIBUTES, 0 },
2636 { NULL, 0, 0, 0, 0 }
2637};
2469cfa2 2638
b6518b38
NC		 2639#undef elf_backend_special_sections
2640#define elf_backend_special_sections msp430_ti_elf_special_sections
2641
2469cfa2 2642#include "elf32-target.h"
GDB Binutils - Deliverables
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