projects / deliverable / binutils-gdb.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
*** empty log message ***
[deliverable/binutils-gdb.git] / cpu / epiphany.cpu
CommitLineData
cfb8c092 1; Adapteva EPIPHANY CPU description. -*- Scheme -*-
926e2094 2; Copyright 1998, 1999, 2000, 2001, 2003, 2006, 2007, 2008, 2009, 2010, 2011
cfb8c092
NC		 3; Free Software Foundation, Inc.
4;
5; Contributed by Embecosm on behalf of Adapteva, Inc.
6; This file is part of the GNU Binutils and of GDB.
7;
8; This program is free software; you can redistribute it and/or modify
9; it under the terms of the GNU General Public License as published by
10; the Free Software Foundation; either version 3 of the License, or
11; (at your option) any later version.
12;
13; This program is distributed in the hope that it will be useful,
14; but WITHOUT ANY WARRANTY; without even the implied warranty of
15; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16; GNU General Public License for more details.
17;
18; You should have received a copy of the GNU General Public License
19; along with this program; if not, write to the Free Software
20; Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
21; MA 02110-1301, USA.
22
23(include "simplify.inc")
24 ; define-arch must appear first
25
26(define-arch
27 (name epiphany) ; name of cpu family
28 (comment "Adapteva, Inc. EPIPHANY family")
29 (default-alignment aligned)
30 (insn-lsb0? #t)
31
32 ; - a 16/32 bit instruction machine (the default)
33
34 (machs epiphany32)
35 (isas epiphany)
36 )
37
38 ; Attributes.
39
40(define-attr
41 (for insn)
42 (type boolean)
43 (name SHORT-INSN)
44 (comment "instruction is a 16 bit form")
45 )
46
47;; 3 bit add/sub immediate forms - useful for relaxing into 11 bit form
48(define-attr
49 (for insn)
50 (type boolean)
51 (name IMM3)
52 (comment "instruction has a 3 bit immediate form")
53 )
54
55;; 8 bit mov immediate forms - useful for relaxing into 16 bit form
56(define-attr
57 (for insn)
58 (type boolean)
59 (name IMM8)
60 (comment "instruction has a 8 bit immediate form")
61 )
62
63 ; Instruction set parameters.
64
65(define-isa
66 (name epiphany)
67 (comment "Adapteva, Inc. EPIPHANY32 ISA")
68
69 (default-insn-word-bitsize 32)
70 (default-insn-bitsize 32)
71 (base-insn-bitsize 32)
72 (decode-assist (3 2 1 0)) ; CGEN can figure this out
73 (liw-insns 1) ; # instructions fetched at once
74 )
75
76 ; Cpu family definitions.
77
78
79(define-cpu
80 ; cpu names must be distinct from the architecture name and machine names.
81 (name epiphanybf)
82 (comment "Adapteva, Inc. EPIPHANY Family")
83 (endian little)
84 (word-bitsize 32)
85 )
86
87(define-cpu
88 (name epiphanymf)
89 (comment "Adapteva, Inc. EPIPHANY Family")
90 (endian little)
91 (word-bitsize 32)
92 )
93
94
95(define-mach
96 (name epiphany32)
97 (comment "Adapteva EPIPHANY")
98 (cpu epiphanybf)
99 )
100
101
102 ; Model descriptions.
103
104(define-model
105 (name epiphany32) (comment "Adapteva EPIPHANY 32/16") (attrs)
106 (mach epiphany32)
107
108 (unit u-exec "Execution Unit" ()
109 1 1 ; issue done
110 () ; state
111 () ; inputs
112 () ; outputs
113 () ; profile action (default)
114 )
115 )
116
117
118
119 ; Instruction fields.
120 ;
121 ; Attributes:
122 ; XXX: what EPIPHANY attrs
123 ; PCREL-ADDR: pc relative value (for reloc and disassembly purposes)
124 ; ABS-ADDR: absolute address (for reloc and disassembly purposes?)
125 ; RESERVED: bits are not used to decode insn, must be all 0
126 ; RELOC: there is a relocation associated with this field
127
128(define-attr
129 (for ifield operand)
130 (type boolean)
131 (name RELOC)
132 (comment "there is a reloc associated with this field (experiment)")
133 )
134
135;; define the fields of the instruction.
136;; name description ATTR MSB LEN
137(dnf f-opc "primary opcode" () 3 4)
138(dnf f-opc-4-1 "secondary opcode" () 4 1)
139(dnf f-opc-6-3 "secondary opcode" () 6 3) ;;
140(dnf f-opc-8-5 "tertiary opcode" () 8 5) ;;
141(dnf f-opc-19-4 "additional opcode bits" () 19 4)
142(dnf f-condcode "condition codes" () 7 4)
143(dnf f-secondary-ccs "flag for secondary ccs" () 7 1)
144(dnf f-shift "shift amount" () 9 5)
145(dnf f-wordsize "load/store size" () 6 2)
146(dnf f-store "load/store flag" () 4 1) ;; 0==load,1==store
147(dnf f-opc-8-1 "opcode bits" () 8 1)
148(dnf f-opc-31-32 "all opcode set" () 31 32)
149
150(df f-simm8 "branch displacement" (PCREL-ADDR RELOC) 15 8 INT
151 ((value pc) (sra SI (sub SI value pc) 1))
152 ((value pc) (add SI (sll SI value 1) pc)))
153
154(df f-simm24 "branch displacement" (PCREL-ADDR RELOC) 31 24 INT
155 ((value pc) (sra SI (sub SI value pc) 1))
156 ((value pc) (add SI (sll SI value 1) pc)))
157
158(df f-sdisp3 "signed immediate 3 bit" () 9 3 INT #f #f)
159
160(dnf f-disp3 "address offset" () 9 3)
161(dnf f-disp8 "address offset" () 23 8)
162
163(dnf f-imm8 "move/add/sub imm8" () 12 8)
164(dnf f-imm-27-8 "move/add/sub imm16" () 27 8)
165(dnf f-addsubx "+/- index address" () 20 1)
166(dnf f-subd "+/- displ address" () 24 1)
167(dnf f-pm "post-modify immediate" () 25 1)
168
169(dnf f-rm "short rm" () 9 3) ;; RM
170(dnf f-rn "short rn" () 12 3) ;; RN
171(dnf f-rd "short rd" () 15 3) ;; RD
172
173(dnf f-rm-x "extension rm" () 25 3) ;; RM
174(dnf f-rn-x "extension rn" () 28 3) ;; RN
175(dnf f-rd-x "extension rd" () 31 3) ;; RD
176
177(dnf f-dc-9-1 "DC" (RESERVED) 9 1)
178
179(dnf f-sn "short sn" () 12 3) ;; SN
180(dnf f-sd "short sd" () 15 3) ;; SD
181
182(dnf f-sn-x "extension sn" () 28 3) ;; SN
183(dnf f-sd-x "extension sd" () 31 3) ;; SD
184
185
186
187(dnf f-dc-7-4 "movts zeros" () 7 4)
188(dnf f-trap-swi-9-1 "trap or swi" () 9 1)
189(dnf f-gien-gidis-9-1 "gien or gidis" () 9 1)
190
191
192(dnf f-dc-15-3 "DC" (RESERVED) 15 3)
193(dnf f-dc-15-7 "DC" (RESERVED) 15 7)
194(dnf f-dc-15-6 "DC" () 15 6)
195(dnf f-trap-num "trap number" () 15 6)
196
197(dnf f-dc-20-1 "DC" (RESERVED) 20 1)
198
199(dnf f-dc-21-1 "DC" (RESERVED) 21 1)
200(dnf f-dc-21-2 "DC" (RESERVED) 21 2)
201
202(dnf f-dc-22-3 "DC" (RESERVED) 22 3)
203(dnf f-dc-22-2 "DC" (RESERVED) 22 2)
204(dnf f-dc-22-1 "DC" (RESERVED) 22 1)
205
206(dnf f-dc-25-6 "DC" (RESERVED) 25 6)
207(dnf f-dc-25-4 "DC" (RESERVED) 25 4)
208(dnf f-dc-25-2 "DC" (RESERVED) 25 2)
209(dnf f-dc-25-1 "DC" (RESERVED) 25 1)
210
211(dnf f-dc-28-1 "DC" (RESERVED) 28 1)
212(dnf f-dc-31-3 "DC" (RESERVED) 31 3)
213
214(dnmf f-disp11 "Unsigned offset for load/store" () UINT (f-disp3 f-disp8)
215 (sequence ()
216 (set (ifield f-disp8) (and (srl (ifield f-disp11) 3) (const 255)))
217 (set (ifield f-disp3) (and (ifield f-disp11) 7)))
218 (sequence ()
219 (set (ifield f-disp11) (or (sll (ifield f-disp8) 3)
220 (ifield f-disp3)))
221 )
222 )
223
224
225(dnmf f-sdisp11 "Signed offset for load/store" () INT (f-disp3 f-disp8)
226 (sequence () ;encode
227 (set (ifield f-disp8) (and #xff (srl SI (ifield f-sdisp11) 3)))
228 (set (ifield f-disp3) (and SI (ifield f-sdisp11) 7)))
229 (sequence () ;decode
230 (set (ifield f-sdisp11)
231 (sra SI (sll SI (or SI (sll (ifield f-disp8) 3)
232 (ifield f-disp3))
233 21)
234 21)))
235 )
236
237(dnmf f-imm16 "Short immediate for move/add/sub" () UINT (f-imm8 f-imm-27-8)
238 (sequence ()
239 (set (ifield f-imm8) (and (ifield f-imm16) #xff))
240 (set (ifield f-imm-27-8) (srl (ifield f-imm16) 8)))
241 (sequence ()
242 (set (ifield f-imm16) (or (sll (ifield f-imm-27-8) 8)
243 (ifield f-imm8))))
244 )
245
246
247;; 32 bit instructions have the register number broken into two non-contiguous fields
248
249(define-pmacro (x-reg-field reg)
250 (define-multi-ifield
251 (name (.sym "f-" reg "6"))
252 (mode UINT)
253 (subfields (.sym "f-" reg "-x") (.sym "f-" reg))
254 (insert (sequence ()
255 (set (ifield (.sym "f-" reg)) (and (ifield (.sym "f-" reg "6"))
256 (const 7)))
257 (set (ifield (.sym "f-" reg "-x")) (srl (ifield (.sym "f-" reg "6"))
258 (const 3)))
259 ))
260 (extract (sequence ()
261 (set (ifield (.sym "f-" reg "6")) (or (sll (ifield (.sym "f-" reg "-x"))
262 (const 3))
263 (ifield (.sym "f-" reg))))
264 ))
265 )
266 )
267
268(x-reg-field rd) ; f-rd6
269(x-reg-field rn) ; f-rn6
270(x-reg-field rm) ; f-rm6
271(x-reg-field sd) ; f-sd6
272(x-reg-field sn) ; f-sn6
273
274
275;;;;;;;;;;
276 ; Enums. ;
277;;;;;;;;;;
278
279 ; insn-opc: bits 3..0 - major family selector
280(define-normal-insn-enum insn-opc "opc enums" () OP4_ f-opc
281 (
282 BRANCH16 ;; 0000
283 LDSTR16X ;; 0001
284 FLOW16 ;; 0010
285 IMM16 ;; 0011
286 LDSTR16D ;; 0100
287 LDSTR16P ;; 0101
288 LSHIFT16 ;; 0110 - logical shift
289 DSP16 ;; 0111 - 3 reg DSP 16 bit insns
290 BRANCH ;; 1000
291 LDSTRX ;; 1001
292 ALU16 ;; 1010 - 3 reg 16 bit
293 IMM32 ;; 1011
294 LDSTRD ;; 1100
295 LDSTRP ;; 1101
296 ASHIFT16 ;; 1110 ASR, BITR
297 MISC ;; 1111 - 32 bit shifts, 3 reg ALU, 3 reg DSP, FLOW, BITR
298 )
299 )
300
301(define-normal-insn-enum insn-wordsize "memory access width" () OPW_ f-wordsize
302 ; specifies the size of a memory load/store operation
303 (BYTE SHORT WORD DOUBLE)
304 )
305
306(define-normal-insn-enum insn-memory-access "memory access direction" () OP_ f-store
307 ; load=0, store=1
308 (LOAD STORE)
309 )
310
311 ; enum for trap codes used by simulator
312(define-normal-insn-enum trap-codes "trap instruction dispatch code" () TRAP_ f-trap-num
313 (write read open exit pass fail close other)
314 )
315
316 ; cond branch: bits 7..4
317 ;
318(define-normal-insn-enum insn-cond "branch conditions" () OPC_ f-condcode
319 (EQ NE GTU GTEU LTEU LTU GT GTE LT LTE BEQ BNE BLT BLTE B BL))
320
321 ; dsp 3 operand opcodes
322(define-normal-insn-enum insn-bop "binary operator subcodes" () OPB_ f-opc-6-3
323 (EOR ADD LSL SUB LSR AND ASR ORR))
324
325 ; dsp 3 operand opcodes
326(define-normal-insn-enum insn-bopext "binary operator subcodes" () OPBE_ f-opc-6-3
327 (FEXT FDEP LFSR - - - - -))
328
329
330(define-normal-insn-enum insn-fop "floating operators" () OPF_ f-opc-6-3
331 (ADD SUB MUL MADD MSUB FLOAT FIX FABS))
332
333(define-normal-insn-enum insn-fopexn "extended floating operators" () OPF_ f-opc-6-3
334 (FRECIP FSQRT - - - - - -))
335
336
337
338
339; Immediate operation secondary opcodes
340(define-normal-insn-enum insn-immop "immediate operators" () OPI_ f-opc-6-3
341 (- ADD - SUB - - - TRAP) ; TRAP is special extension for simulator
342 )
343
344 ; don't care fields
345(define-normal-insn-enum insn-dc-25-2 "don't cares" () OPI_25_2_ f-dc-25-2
346 (MBZ))
347
348; General Register keyword names.
349(define-keyword
350 (name gr-names)
351 (print-name h-registers)
352 (prefix "")
353 (values
354; some preferred aliases
355 (sb 9) (sl 10) (fp 11) (ip 12) (sp 13) (lr 14)
356; the default register names
357 (r0 0) (r1 1) (r2 2) (r3 3) (r4 4) (r5 5) (r6 6) (r7 7)
358 (r8 8) (r9 9) (r10 10) (r11 11) (r12 12) (r13 13) (r14 14) (r15 15)
359 (r16 16) (r17 17) (r18 18) (r19 19) (r20 20) (r21 21) (r22 22) (r23 23)
360 (r24 24) (r25 25) (r26 26) (r27 27) (r28 28) (r29 29) (r30 30) (r31 31)
361 (r32 32) (r33 33) (r34 34) (r35 35) (r36 36) (r37 37) (r38 38) (r39 39)
362 (r40 40) (r41 41) (r42 42) (r43 43) (r44 44) (r45 45) (r46 46) (r47 47)
363 (r48 48) (r49 49) (r50 50) (r51 51) (r52 52) (r53 53) (r54 54) (r55 55)
364 (r56 56) (r57 57) (r58 58) (r59 59) (r60 60) (r61 61) (r62 62) (r63 63)
365; some less popular aliases
366 (a1 0) (a2 1) (a3 2) (a4 3) (v1 4) (v2 5) (v3 6) (v4 7)
367 (v5 8) (v6 9) (v7 10) (v8 11)
368 )
369 )
370
371(define-normal-insn-enum post-index "+/- index register" () DIR_ f-addsubx (POSTINC POSTDEC))
372
373(define-normal-insn-enum disp-post-modify "postmodify displacement" () PMOD_ f-pm (DISP POST))
374\f
375;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
376 ; Hardware pieces.
377;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
378
379;; 64 general-purpose registers
380(define-hardware
381 (name h-registers)
382 (comment "all addressable registers")
383 (type register SI (64))
384 (attrs PROFILE CACHE-ADDR)
385 (indices extern-keyword gr-names)
386 )
387
388
389
390;; Same 64 registers as floating point registers
391(define-hardware
392 (name h-fpregisters)
393 (comment "all GPRs as float values")
394 (type register SF (64))
395 (attrs PROFILE VIRTUAL)
396 (indices extern-keyword gr-names)
397 (get (index) (subword SF (reg h-registers index) 0))
398 (set (index newval) (set (reg h-registers index) (subword SI newval 0)))
399 )
400
401;; define processor status bits as physical hardware
402
403(define-pmacro (psw-h-bit name cmt)
404 (dsh name cmt () (register BI)))
405
406(psw-h-bit h-zbit "integer zero bit")
407(psw-h-bit h-nbit "integer neg bit")
408(psw-h-bit h-cbit "integer carry bit")
409(psw-h-bit h-vbit "integer overflow bit")
410(psw-h-bit h-vsbit "integer overflow sticky")
411
412
413(psw-h-bit h-bzbit "floating point zero bit")
414(psw-h-bit h-bnbit "floating point neg bit")
415(psw-h-bit h-bvbit "floating point ovfl bit")
416(psw-h-bit h-bubit "floating point underfl bit")
417(psw-h-bit h-bibit "floating point invalid bit")
418(psw-h-bit h-bcbit "floating point carry bit")
419
420(psw-h-bit h-bvsbit "floating point overflow sticky")
421(psw-h-bit h-bisbit "floating point invalid sticky")
422(psw-h-bit h-busbit "floating point underflow sticky")
423
424(psw-h-bit h-expcause0bit "exceprion cause bit0")
425(psw-h-bit h-expcause1bit "exceprion cause bit1")
426(psw-h-bit h-expcause2bit "external load stalled bit")
427(psw-h-bit h-extFstallbit "external fetch stalled bit")
428
429(psw-h-bit h-trmbit "0=round to nearest, 1=trunacte select bit")
430(psw-h-bit h-invExcEnbit "invalid exception enable bit")
431(psw-h-bit h-ovfExcEnbit "overflow exception enable bit")
432(psw-h-bit h-unExcEnbit "underflow exception enablebit ")
433
434(psw-h-bit h-timer0bit0 "timer 0 mode selection 0")
435(psw-h-bit h-timer0bit1 "timer 0 mode selection 1")
436(psw-h-bit h-timer0bit2 "timer 0 mode selection 2")
437(psw-h-bit h-timer0bit3 "timer 0 mode selection 3")
438(psw-h-bit h-timer1bit0 "timer 1 mode selection 0")
439(psw-h-bit h-timer1bit1 "timer 1 mode selection 1")
440(psw-h-bit h-timer1bit2 "timer 1 mode selection 2")
441(psw-h-bit h-timer1bit3 "timer 1 mode selection 3")
442
443(psw-h-bit h-mbkptEnbit "multicore bkpt enable")
444(psw-h-bit h-clockGateEnbit "clock gating enable bkpt enable")
445
446
447(psw-h-bit h-coreCfgResBit12 "core config bit 12")
448(psw-h-bit h-coreCfgResBit13 "core config bit 13")
449(psw-h-bit h-coreCfgResBit14 "core config bit 14")
450(psw-h-bit h-coreCfgResBit15 "core config bit 15")
451(psw-h-bit h-coreCfgResBit16 "core config bit 16")
452
453
454(psw-h-bit h-coreCfgResBit20 "core config bit 20")
455(psw-h-bit h-coreCfgResBit21 "core config bit 21")
456
457(psw-h-bit h-coreCfgResBit24 "core config bit 24")
458(psw-h-bit h-coreCfgResBit25 "core config bit 25")
459(psw-h-bit h-coreCfgResBit26 "core config bit 26")
460(psw-h-bit h-coreCfgResBit27 "core config bit 27")
461(psw-h-bit h-coreCfgResBit28 "core config bit 28")
462(psw-h-bit h-coreCfgResBit29 "core config bit 29")
463(psw-h-bit h-coreCfgResBit30 "core config bit 30")
464(psw-h-bit h-coreCfgResBit31 "core config bit 31")
465
466
467(psw-h-bit h-arithmetic-modebit0 "arithmetic mode bit0")
468(psw-h-bit h-arithmetic-modebit1 "arithmetic mode bit1")
469(psw-h-bit h-arithmetic-modebit2 "arithmetic mode bit2")
470
471
472(psw-h-bit h-gidisablebit "global interrupt disable bit")
473(psw-h-bit h-kmbit "kernel mode bit")
474(psw-h-bit h-caibit "core active indicator mode bit")
475(psw-h-bit h-sflagbit "sflag bit")
476
477
478 ; Define operands for each of the physical bits
479(define-pmacro (psw-bit name hname cmt)
480 (dnop name cmt (SEM-ONLY) hname f-nil)
481 )
482
483(psw-bit zbit h-zbit "integer zero bit")
484(psw-bit nbit h-nbit "integer neg bit")
485(psw-bit cbit h-cbit "integer carry bit")
486(psw-bit vbit h-vbit "integer overflow bit")
487
488(psw-bit bzbit h-bzbit "floating point zero bit")
489(psw-bit bnbit h-bnbit "floating point neg bit")
490(psw-bit bvbit h-bvbit "floating point ovfl bit")
491(psw-bit bcbit h-bcbit "floating point carry bit")
492
493(psw-bit bubit h-bubit "floating point underfl bit")
494(psw-bit bibit h-bibit "floating point invalid bit")
495
496
497(psw-bit vsbit h-vsbit "integer overflow sticky")
498(psw-bit bvsbit h-bvsbit "floating point overflow sticky")
499(psw-bit bisbit h-bisbit "floating point invalid sticky")
500(psw-bit busbit h-busbit "floating point underflow sticky")
501(psw-bit expcause0bit h-expcause0bit "exceprion cause bit0")
502(psw-bit expcause1bit h-expcause1bit "exceprion cause bit1")
503
504
505(psw-bit expcause2bit h-expcause2bit "external load stalled bit")
506(psw-bit extFstallbit h-extFstallbit "external fetch stalled bit")
507
508(psw-bit trmbit h-trmbit "0=round to nearest, 1=trunacte selct bit")
509(psw-bit invExcEnbit h-invExcEnbit "invalid exception enable bit")
510(psw-bit ovfExcEnbit h-ovfExcEnbit "overflow exception enable bit")
511(psw-bit unExcEnbit h-unExcEnbit "underflow exception enable bit")
512
513(psw-bit timer0bit0 h-timer0bit0 "timer 0 mode selection 0")
514(psw-bit timer0bit1 h-timer0bit1 "timer 0 mode selection 1")
515(psw-bit timer0bit2 h-timer0bit2 "timer 0 mode selection 2")
516(psw-bit timer0bit3 h-timer0bit3 "timer 0 mode selection 3")
517
518(psw-bit timer1bit0 h-timer1bit0 "timer 1 mode selection 0")
519(psw-bit timer1bit1 h-timer1bit1 "timer 1 mode selection 1")
520(psw-bit timer1bit2 h-timer1bit2 "timer 1 mode selection 2")
521(psw-bit timer1bit3 h-timer1bit3 "timer 1 mode selection 3")
522
523(psw-bit mbkptEnbit h-mbkptEnbit "multicore bkpt enable")
524(psw-bit clockGateEnbit h-clockGateEnbit "clock gate enable enable")
525
526(psw-bit arithmetic-modebit0 h-arithmetic-modebit0 "arithmetic mode bit0")
527(psw-bit arithmetic-modebit1 h-arithmetic-modebit1 "arithmetic mode bit1")
528(psw-bit arithmetic-modebit2 h-arithmetic-modebit2 "arithmetic mode bit2")
529
530(psw-bit coreCfgResBit12 h-coreCfgResBit12 "core config bit 12")
531(psw-bit coreCfgResBit13 h-coreCfgResBit13 "core config bit 13")
532(psw-bit coreCfgResBit14 h-coreCfgResBit14 "core config bit 14")
533(psw-bit coreCfgResBit15 h-coreCfgResBit15 "core config bit 15")
534(psw-bit coreCfgResBit16 h-coreCfgResBit16 "core config bit 16")
535
536(psw-bit coreCfgResBit20 h-coreCfgResBit20 "core config bit 20")
537(psw-bit coreCfgResBit21 h-coreCfgResBit21 "core config bit 21")
538
539(psw-bit coreCfgResBit24 h-coreCfgResBit24 "core config bit 24")
540(psw-bit coreCfgResBit25 h-coreCfgResBit25 "core config bit 25")
541(psw-bit coreCfgResBit26 h-coreCfgResBit26 "core config bit 26")
542(psw-bit coreCfgResBit27 h-coreCfgResBit27 "core config bit 27")
543(psw-bit coreCfgResBit28 h-coreCfgResBit28 "core config bit 28")
544(psw-bit coreCfgResBit29 h-coreCfgResBit29 "core config bit 29")
545(psw-bit coreCfgResBit30 h-coreCfgResBit30 "core config bit 30")
546(psw-bit coreCfgResBit31 h-coreCfgResBit31 "core config bit 31")
547
548
549(psw-bit gidisablebit h-gidisablebit "global interrupt disable bit")
550(psw-bit kmbit h-kmbit "kernel mode bit")
551(psw-bit caibit h-caibit "core actibe indicator bit")
552(psw-bit sflagbit h-sflagbit "sflag bit")
553
554
555
556
557;; Special registers - accessed via MOVTS and MOVFS.
558;;
559;; "Core control and status" in group MR0=0, MR1=0
560
561(define-keyword
562 (name cr-names)
563 (print-name h-core-registers)
564 (prefix "")
565 (values (config 0)
566 (status 1) ; unified condition codes
567 (pc 2) ; virtualized PC
568 (debug 3);
569 (iab 4)
570 (lc 5);loop counter Not impemented
571 (ls 6);loop start address Not impemented
572 (le 7);loop end address Not impemented
573 (iret 8)
574 (imask 9)
575 (ilat 10)
576 (ilatst 11)
577 (ilatcl 12)
578 (ipend 13)
579 (ctimer0 14)
580 (ctimer1 15)
581 (hstatus 16)
582 )
583 )
584;; DMA registers in group MR0=1, MR1=0
585
586(define-keyword
587 (name crdma-names)
588 (print-name h-coredma-registers)
589 (prefix "")
590 (values
591
592
593 (dma0config 0)
594 (dma0stride 1)
595 (dma0count 2)
596
597 (dma0srcaddr 3)
598 (dma0dstaddr 4)
599
600 (dma0auto0 5)
601 (dma0auto1 6)
602
603 (dma0status 7)
604
605 (dma1config 8)
606 (dma1stride 9)
607 (dma1count 10)
608
609 (dma1srcaddr 11)
610 (dma1dstaddr 12)
611
612 (dma1auto0 13)
613 (dma1auto1 14)
614
615 (dma1status 15)
616
617 )
618 )
619;; mem configuration registers in group MR0=0, MR1=1
620
621(define-keyword
622 (name crmem-names)
623 (print-name h-coremem-registers)
624 (prefix "")
625 (values
626 (memconfig 0)
627 (memstatus 1)
628 (memprotect 2)
629 (memreserve 3)
630 )
631 )
632
633;; mesh configuration registers in group MR0=1, MR1=1
634
635(define-keyword
636 (name crmesh-names)
637 (print-name h-coremesh-registers)
638 (prefix "")
639
640 (values
641
642
643 (meshconfig 0)
644 (coreid 1)
645 (meshmulticast 2)
646 (swreset 3)
647 )
648 )
649
650
651
652
653;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
654 ; PC is a byte-addressed register
655;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
656
657(dnh h-pc "program counter" (PC PROFILE) (pc) () () ())
658
659;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
660 ; Memory Effective Address wants to be visible
661;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
662
663(dnh h-memaddr "memory effective address" (PROFILE) (register SI) () () ())
664(dnop memaddr "memory effective address" (SEM-ONLY) h-memaddr f-nil)
665
666;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
667 ; Special Core Registers
668;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
669;; STATUS
670;; [0]=core active indicator
671;; [1]=global interrupt disable
672;; [2]=processor mode(1=user mode, 0=kernel mode)
673;; [3]=wired AND global flag
674
675;; [4]=integer zero zbit
676;; [5]=integer negative nbit
677;; [6]=integer carry cbit
678;; [7]=integer overflow vbit
679
680;; [8]=fpu zero flag bzbit
681;; [9]=fpu negative flag bnbit
682;; [10]=fpu overflow flag bvbit
683;; [11]=fpu carry flag(not used) bcbit
684
685;; [12]=ialu overflow flag(sticky) vsbit
686;; [13]=fpu invalid flag(sticky) bisbit
687;; [14]=fpu overflow flag(sticky) bvsbit
688;; [15]=fpu underflow flag(sticky) busbit
689
690;; [17:16]=exception cause 00=no exception 01=load-store exception 10=fpu exception 11=unimplemented instruction
691;; expcause1bit
692;; expcause0bit
693
694;; [18]=external load stalled expcause2bit
695;; [19]=external fetch stalled extFstallbit
696
697;; [31:20]=RESERVED
698
699
700
701
702
703(define-hardware
704 (name h-core-registers)
705 (comment "Special Core Registers")
706 (type register USI (17))
707 (attrs)
708 (indices extern-keyword cr-names)
709 (get (index)
710 (cond USI
711 ((eq index (const 1)) ; STATUS reg ?
712 (or (or (or (or (sll USI kmbit (const 2))
713 (sll USI gidisablebit (const 1)))
714 (or (or (sll USI expcause1bit (const 17))
715 (sll USI expcause0bit (const 16)))
716 (or (sll USI expcause2bit (const 18))
717 (sll USI extFstallbit (const 19)))))
718 (or (or (or (sll USI busbit (const 15))
719 (sll USI bisbit (const 13)))
720 (or (sll USI bvsbit (const 14))
721 (sll USI vsbit (const 12))))
722 (or (or (sll USI bvbit (const 10))
723 (sll USI bcbit (const 11)))
724 (or (sll USI bnbit (const 9))
725 (sll USI bzbit (const 8))))))
726 (or (or (or (sll USI vbit (const 7))
727 (sll USI cbit (const 6)))
728 (or (sll USI nbit (const 5))
729 (sll USI zbit (const 4))))
730 (or (sll USI sflagbit (const 3))
731 (sll USI (const 1) (const 0)))))) ;caibit
732 ((eq index (const 0)) ; Config reg ?
733 (or (or (or (or (or (or (sll USI timer0bit2 (const 6))
734 (sll USI timer0bit3 (const 7)))
735 (or (or (sll USI coreCfgResBit28 (const 28))
736 (sll USI coreCfgResBit29 (const 29)))
737 (or (sll USI coreCfgResBit30 (const 30))
738 (sll USI coreCfgResBit31 (const 31)))))
739 (or (or (sll USI coreCfgResBit24 (const 24))
740 (sll USI coreCfgResBit25 (const 25)))
741 (or (sll USI coreCfgResBit26 (const 26))
742 (sll USI coreCfgResBit27 (const 27)))))
743 (or (or (sll USI timer0bit0 (const 4))
744 (sll USI timer0bit1 (const 5)))
745 (or (sll USI coreCfgResBit14 (const 14))
746 (sll USI coreCfgResBit15 (const 15)))))
747 (or (or (or (or (sll USI timer1bit2 (const 10))
748 (sll USI timer1bit3 (const 11)))
749 (or (sll USI coreCfgResBit12 (const 12))
750 (sll USI coreCfgResBit13 (const 13))))
751 (or (sll USI clockGateEnbit (const 22))
752 (sll USI mbkptEnbit (const 23))))
753 (or (or (sll USI timer1bit0 (const 8))
754 (sll USI timer1bit1 (const 9)))
755 (or (sll USI coreCfgResBit20 (const 20))
756 (sll USI coreCfgResBit21 (const 21))))))
757 (or (or (sll USI invExcEnbit (const 1))
758 (sll USI ovfExcEnbit (const 2)))
759 (or (or (sll USI trmbit (const 0))
760 (sll USI unExcEnbit (const 3)))
761 (or (or (sll USI arithmetic-modebit0 (const 17))
762 (sll USI arithmetic-modebit1 (const 18)))
763 (or (sll USI arithmetic-modebit2 (const 19))
764 (sll USI coreCfgResBit16 (const 16)))))))) ;config reg
765
766 ((eq index (const 2)) (raw-reg USI h-pc)) ;PC reg
767
768 (else (raw-reg USI h-core-registers index))))
769
770 (set (index val)
771 (cond VOID
772 ((eq index (const 0)) ; CONFIG reg
773 (sequence ()
774 (set trmbit (and (const 1) (srl val (const 0))))
775 (set invExcEnbit (and (const 1) (srl val (const 1))))
776 (set ovfExcEnbit (and (const 1) (srl val (const 2))))
777 (set unExcEnbit (and (const 1) (srl val (const 3))))
778 (set timer0bit0 (and (const 1) (srl val (const 4))))
779 (set timer0bit1 (and (const 1) (srl val (const 5))))
780 (set timer0bit2 (and (const 1) (srl val (const 6))))
781 (set timer0bit3 (and (const 1) (srl val (const 7))))
782 (set timer1bit0 (and (const 1) (srl val (const 8))))
783 (set timer1bit1 (and (const 1) (srl val (const 9))))
784 (set timer1bit2 (and (const 1) (srl val (const 10))))
785 (set timer1bit3 (and (const 1) (srl val (const 11))))
786
787 (set coreCfgResBit12 (and (const 1) (srl val (const 12))))
788 (set coreCfgResBit13 (and (const 1) (srl val (const 13))))
789 (set coreCfgResBit14 (and (const 1) (srl val (const 14))))
790 (set coreCfgResBit15 (and (const 1) (srl val (const 15))))
791 (set coreCfgResBit16 (and (const 1) (srl val (const 16))))
792
793 (set arithmetic-modebit0 (and (const 1) (srl val (const 17))))
794 (set arithmetic-modebit1 (and (const 1) (srl val (const 18))))
795 (set arithmetic-modebit2 (and (const 1) (srl val (const 19))))
796
797 (set coreCfgResBit20 (and (const 1) (srl val (const 20))))
798 (set coreCfgResBit21 (and (const 1) (srl val (const 21))))
799
800 (set clockGateEnbit (and (const 1) (srl val (const 22))))
801 (set mbkptEnbit (and (const 1) (srl val (const 23))))
802
803 (set coreCfgResBit24 (and (const 1) (srl val (const 24))))
804 (set coreCfgResBit25 (and (const 1) (srl val (const 25))))
805 (set coreCfgResBit26 (and (const 1) (srl val (const 26))))
806 (set coreCfgResBit27 (and (const 1) (srl val (const 27))))
807 (set coreCfgResBit28 (and (const 1) (srl val (const 28))))
808 (set coreCfgResBit29 (and (const 1) (srl val (const 29))))
809 (set coreCfgResBit30 (and (const 1) (srl val (const 30))))
810 (set coreCfgResBit31 (and (const 1) (srl val (const 31))))
811
812 (set (raw-reg USI h-core-registers index) val)
813 ;; check LSB of CONFIG for rounding mode
814 (c-call "epiphany_set_rounding_mode" val)
815 )
816 )
817 ((eq index (const 1)) ;STATUS reg ; TODO check which bits can be set or clear
818 (sequence ((USI newval))
819 (set newval (and val (const #xfff2)))
820 (set extFstallbit (and (const 1) (srl newval (const 19))))
821 (set expcause2bit (and (const 1) (srl newval (const 18))))
822 (set expcause1bit (and (const 1) (srl newval (const 17))))
823 (set expcause0bit (and (const 1) (srl newval (const 16))))
824 (set busbit (and (const 1) (srl newval (const 15))))
825 (set bisbit (and (const 1) (srl newval (const 13))))
826 (set bvsbit (and (const 1) (srl newval (const 14))))
827 (set vsbit (and (const 1) (srl newval (const 12))))
828 (set bvbit (and (const 1) (srl newval (const 10))))
829 (set bcbit (and (const 1) (srl newval (const 11))))
830 (set bnbit (and (const 1) (srl newval (const 9))))
831 (set bzbit (and (const 1) (srl newval (const 8))))
832 (set vbit (and (const 1) (srl newval (const 7))))
833 (set cbit (and (const 1) (srl newval (const 6))))
834 (set nbit (and (const 1) (srl newval (const 5))))
835 (set zbit (and (const 1) (srl newval (const 4))))
836 (set sflagbit (and (const 1) (srl newval (const 3))))
837 (set kmbit (and (const 1) (srl newval (const 2))))
838 ;;(set gie (and (const 1) (srl newval (const 1))))
839 (set (raw-reg SI h-core-registers (const 1)) newval)
840 ))
841 ;; causes simulator errors
842 ;; ((eq index (const 2)) ;PC reg
843 ;; (set pc val))
844
845 (else (set (raw-reg USI h-core-registers index) val))
846 ))
847)
848 ; (define-pmacro (hcr-config) (reg h-core-registers 0)) etc.
849(.splice begin (.unsplice (.map
850 (.pmacro (xname xnum)
851 (define-pmacro ((.sym hcr- xname)) (reg h-core-registers xnum)))
852
853 (
854 config
855 status
856 pc
857 debug
858 iab
859 lc
860 ls
861 le
862 iret
863 imask
864 ilat
865 ilatst
866 ilatcl
867 ipend
868 ctimer0
869 ctimer1
870 hstatus
871
872
873
874 )
875
876 (0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
877 )
878 )))
879
880
881
882;; DMA registers in MMR space
883(define-hardware
884 (name h-coredma-registers)
885 (comment "DMA registers in MMR space")
886 (type register USI (16))
887 (attrs)
888 (indices extern-keyword crdma-names)
889 )
890
891;; MEM registers in MMR space
892(define-hardware
893 (name h-coremem-registers)
894 (comment "MEM registers in MMR space")
895 (type register USI (4))
896 (attrs)
897 (indices extern-keyword crmem-names)
898 )
899
900;; MEM registers in MMR space
901(define-hardware
902 (name h-coremesh-registers)
903 (comment "MESH registers in MMR space")
904 (type register USI (4))
905 (attrs)
906 (indices extern-keyword crmesh-names)
907 )
908
909
910
911 ; Operands
912
913 ; Branch displacements
914(define-operand
915 (name simm24)
916 (comment "branch address pc-relative")
917 (attrs RELAX)
918 (type h-iaddr)
919 (index f-simm24)
920 (handlers (parse "branch_addr")))
921
922(define-operand
923 (name simm8)
924 (comment "branch address pc-relative")
925 (attrs RELAX)
926 (type h-iaddr)
927 (index f-simm8)
928 (handlers (parse "branch_addr")))
929
930
931;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
932 ; Register operands
933;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
934
935(define-pmacro (short-regs nm group hw cmt)
936 (define-operand
937 (name nm)
938 (comment cmt)
939 (attrs)
940 (type hw)
941 (index (.sym "f-r" group))
942 (handlers (parse "shortregs") (print "keyword"))
943 )
944 )
945
946(define-pmacro (short-regs-core nm group hw cmt)
947 (define-operand
948 (name nm)
949 (comment cmt)
950 (attrs)
951 (type hw)
952 (index (.sym "f-s" group))
953 (handlers (parse "shortregs") (print "keyword"))
954 )
955 )
956
957
958 ; short regs (0-7)
959(short-regs rd d h-registers "destination register")
960(short-regs rn n h-registers "source register")
961(short-regs rm m h-registers "source register")
962
963(short-regs frd d h-fpregisters "fp destination register")
964(short-regs frn n h-fpregisters "fp source register")
965(short-regs frm m h-fpregisters "fp source register")
966
967 ; long regs (0-63)
968(dnop rd6 "destination register" () h-registers f-rd6)
969(dnop rn6 "source register" () h-registers f-rn6)
970(dnop rm6 "source register" () h-registers f-rm6)
971
972(dnop frd6 "fp destination register" () h-fpregisters f-rd6)
973(dnop frn6 "fp source register" () h-fpregisters f-rn6)
974(dnop frm6 "fp source register" () h-fpregisters f-rm6)
975
976 ; special regs (0-7)
977(short-regs-core sd d h-core-registers "special destination")
978(short-regs-core sn n h-core-registers "special source")
979
980 ; special regs (long form)
981(dnop sd6 "special destination register" () h-core-registers f-sd6)
982(dnop sn6 "special source register" () h-core-registers f-sn6)
983
984(dnop sddma "dma register" () h-coredma-registers f-sd6)
985(dnop sndma "dma register" () h-coredma-registers f-sn6)
986(dnop sdmem "mem register" () h-coremem-registers f-sd6)
987(dnop snmem "mem register" () h-coremem-registers f-sn6)
988(dnop sdmesh "mesh register" () h-coremesh-registers f-sd6)
989(dnop snmesh "mesh register" () h-coremesh-registers f-sn6)
990
991 ; Immediate literals - but don't allow register names!
992(define-pmacro (dimmop nm cmt hwtype idx)
993 (define-operand (name nm) (comment cmt) (type hwtype) (index idx)
994 (attrs RELAX)
995 (handlers (parse "simm_not_reg")
996 (print "simm_not_reg")))
997 )
998
999(dimmop simm3 "signed 3-bit literal" h-sint f-sdisp3)
1000(dimmop simm11 "signed 11-bit literal" h-sint f-sdisp11)
1001(dnop disp3 "short data displacement" () h-uint f-disp3)
1002(dnop trapnum6 "parameter for swi or trap" () h-uint f-trap-num)
1003
1004(define-pmacro (duimmop nm cmt hwtype idx)
1005 (define-operand (name nm) (comment cmt) (type hwtype) (index idx)
1006 (attrs)
1007 (handlers (parse "uimm_not_reg")
1008 (print "uimm_not_reg")))
1009 )
1010
1011(duimmop swi_num "unsigned 6-bit swi#" h-uint f-trap-num)
1012(duimmop disp11 "sign-magnitude data displacement" h-uint f-disp11)
1013
1014(dnop shift "immediate shift amount" () h-uint f-shift)
1015
1016(define-operand (name imm16) (comment "16-bit unsigned literal") (attrs RELAX)
1017 (type h-addr) (index f-imm16) (handlers (parse "imm16")))
1018(define-operand (name imm8) (comment "8-bit unsigned literal") (attrs RELAX)
1019 (type h-addr) (index f-imm8) (handlers (parse "imm8")))
1020
1021(define-operand
1022 (name direction)
1023 (comment "+/- indexing")
1024 (attrs)
1025 (type h-uint)
1026 (index f-addsubx)
1027 (handlers (parse "postindex")
1028 (print "postindex")))
1029
1030(define-operand
1031 (name dpmi)
1032 (comment "+/- magnitude immediate displacement")
1033 (attrs)
1034 (type h-uint)
1035 (index f-subd)
1036 (handlers (parse "postindex")
1037 (print "postindex")))
1038
1039
1040
1041;; call exception macro - no check for imask
1042(define-pmacro (call-exception vaddr bit-in-ilat)
1043 (if (eq gidisablebit 0)
1044 (if (eq (and (hcr-imask) bit-in-ilat) 0)
1045 (sequence ()
1046 (set kmbit 1)
1047 (set gidisablebit 1)
1048 (set (hcr-iret) (add pc (const 2)))
1049 (set (hcr-ipend) (or (hcr-ipend) (const bit-in-ilat)))
1050 (set pc (const vaddr))
1051
1052 )
1053 ;; schedule interrupt
1054 (set (hcr-ilat) (or (hcr-ilat) (const bit-in-ilat)))
1055 )
1056 )
1057 )
1058
1059
1060;; (lc 5);loop counter Not impemented
1061;; (ls 6);loop start address Not impemented
1062;; (le 7);loop end address Not impemented
1063
1064;;have callback to adjust pc in case od events ( HW loops ... )
1065(define-pmacro (dni_wrapper isnid stdrdesc attr_ strassembl iopcode proceed null_b)
1066 (begin
1067 (dni isnid stdrdesc attr_ strassembl iopcode
1068 (sequence () proceed
1069 (sequence ((USI tmpPC))
1070 ;;(set tmpPC (c-call USI "epiphany_post_isn_callback" pc))
1071
1072 (if (eq pc (hcr-le))
1073 (set (hcr-lc) (sub (hcr-lc) #x1)))
1074 (if (and
1075 (eq pc (hcr-le))
1076 (not (eq (hcr-lc) #x0)))
1077 (set pc (hcr-ls)))
1078 )
1079 )
1080 null_b)
1081 )
1082 )
1083
1084
1085
1086
1087
1088;; Some handy macros
1089;;
1090
1091;; define instructions
1092;; Short (16 bit forms) must appear first so that instruction
1093;; selection can reject them and match long forms when registers
1094;; or immediates exceed the values in the 16 bit instructions
1095
1096
1097;; B<COND> SIMM8
1098;; B<COND> SIMM24
1099
1100(define-pmacro (br-insn name cond g-op)
1101 (begin
1102 ; the 16-bit versions of branch
1103 (dni (.sym "b" name "16")
1104 (.str "Conditional Branch - 16 bit" name)
1105 (COND-CTI SHORT-INSN)
1106 (.str "b" name ".s $simm8")
1107 (+ OP4_BRANCH16 (.sym "OPC_" cond) simm8)
1108 (if (g-op)
1109 (set pc simm8)
1110 )
1111 ()
1112 )
1113
1114 (dnmi (.sym "b" name "16r") "relaxable conditional branch"
1115 (COND-CTI RELAXABLE)
1116 (.str "b" name " $simm8")
1117 (emit (.sym "b" name "16") simm8)
1118 )
1119
1120 (dni (.sym "b" name)
1121 (.str "Conditional Branch " name)
1122 (COND-CTI)
1123 (.str "b" name ".l $simm24")
1124 (+ OP4_BRANCH (.sym "OPC_" cond) simm24)
1125 (if (g-op)
1126 (set pc simm24)
1127 )
1128 ()
1129 )
1130
1131 (dnmi (.sym "b" name "32r") "relaxable conditional branch"
1132 (COND-CTI RELAXED)
1133 (.str "b" name " $simm24")
1134 (emit (.sym "b" name) simm24)
1135 )
1136 )
1137 )
1138
1139
1140 ; basic conditional branches for integer arithmetic
1141(br-insn "eq" EQ (.pmacro () (eq zbit #x1)))
1142(br-insn "ne" NE (.pmacro () (eq zbit #x0)))
1143(br-insn "gtu" GTU (.pmacro () (and BI cbit (not BI zbit))))
1144(br-insn "gteu" GTEU (.pmacro () (eq cbit #x1)))
1145(br-insn "lteu" LTEU (.pmacro () (or BI (not BI cbit) zbit)))
1146(br-insn "ltu" LTU (.pmacro () (eq cbit #x0)))
1147(br-insn "gt" GT (.pmacro () (and BI (not BI zbit) (eq vbit nbit))))
1148(br-insn "gte" GTE (.pmacro () (eq vbit nbit)))
1149(br-insn "lt" LT (.pmacro () (xor BI vbit nbit)))
1150(br-insn "lte" LTE (.pmacro () (or BI zbit (xor vbit nbit))))
1151
1152
1153 ; floating point condition codes (floating point instructions)
1154(br-insn "beq" BEQ (.pmacro () (or BI bzbit bzbit)))
1155(br-insn "bne" BNE (.pmacro () (not BI bzbit)))
1156(br-insn "blt" BLT (.pmacro () (and BI bnbit (not bzbit))))
1157(br-insn "blte" BLTE (.pmacro () (or BI bnbit bzbit)))
1158
1159 ; unconditional branches
1160(dni b16 "short unconditional branch" (UNCOND-CTI SHORT-INSN)
1161 "b.s $simm8"
1162 (+ OP4_BRANCH16 OPC_B simm8)
1163 (set pc simm8)
1164 ()
1165 )
1166
1167(dnmi b16r "relaxable b16"
1168 (UNCOND-CTI RELAXABLE)
1169 "b $simm8"
1170 (emit b16 simm8)
1171 )
1172
1173(dni b "long unconditional branch" (UNCOND-CTI)
1174 "b.l $simm24"
1175 (+ OP4_BRANCH OPC_B simm24)
1176 (set pc simm24)
1177 ()
1178 )
1179
1180(dnmi b32r "relaxable b"
1181 (UNCOND-CTI RELAXED)
1182 "b $simm24"
1183 (emit b simm24))
1184
1185;; BL R,ADDR
1186
1187(dni bl16 "branch and link"
1188 (UNCOND-CTI SHORT-INSN)
1189 ("bl.s $simm8")
1190 (+ OP4_BRANCH16 OPC_BL simm8)
1191 (sequence ()
1192 (set (reg h-registers 14) (add pc (const 2)))
1193 (set pc simm8))
1194 ()
1195 )
1196
1197(dnmi bl16r "bl16 relaxable"
1198 (UNCOND-CTI RELAXABLE)
1199 "bl $simm8"
1200 (emit bl16 simm8))
1201
1202(dni bl "branch and link"
1203 (UNCOND-CTI)
1204 ("bl.l $simm24")
1205 (+ OP4_BRANCH OPC_BL simm24)
1206 (sequence ()
1207 (set (reg h-registers 14) (add pc (const 4)))
1208 (set pc simm24))
1209 ()
1210 )
1211
1212(dnmi blr "bl relaxable"
1213 (UNCOND-CTI RELAXED)
1214 "bl $simm24"
1215 (emit bl simm24))
1216
1217;; JUMP <RN>
1218(dni jr16 "unconditional jump 16"
1219 (UNCOND-CTI SHORT-INSN)
1220 ("jr $rn")
1221 (+ OP4_FLOW16 (f-opc-8-5 #x14) (f-dc-15-3 #x0) (f-dc-9-1 #x0) rn)
1222 (set pc rn)
1223 ()
1224 )
1225
1226;; RTS / JR
1227;; ??? Putting a constant into a multi-ifield does not work -
1228;; the constant gets inserted in full into each part.
1229 ;(dnmi rts "return from subroutine"
1230 ; (UNCOND-CTI)
1231 ; ("rts")
1232 ; (emit jr (rn6 14)) ; jr lr / jr r14
1233 ;)
1234;; RTS / JR
1235(dni rts "return from subroutine"
1236 (ALIAS UNCOND-CTI)
1237 ("rts")
1238 (+ OP4_MISC (f-opc-8-5 #x14) (f-opc-19-4 #x2) (f-rn 6) (f-rn-x 1)
1239 (f-dc-9-1 #x0)
1240 (f-dc-15-3 #x0)
1241 (f-dc-25-6 #x0)
1242 (f-dc-31-3 #x0)
1243 )
1244 (set pc (reg h-registers 14))
1245 ()
1246 )
1247
1248(dni jr "unconditional jump"
1249 (UNCOND-CTI)
1250 ("jr $rn6")
1251 (+ OP4_MISC (f-opc-8-5 #x14) (f-opc-19-4 #x2) rn6
1252 (f-dc-9-1 #x0)
1253 (f-dc-15-3 #x0)
1254 (f-dc-25-6 #x0)
1255 (f-dc-31-3 #x0)
1256 )
1257 (set pc rn6)
1258 ()
1259 )
1260
1261
1262;; JALR <RN>
1263(dni jalr16 "jump and link register"
1264 (UNCOND-CTI SHORT-INSN)
1265 ("jalr $rn")
1266 (+ OP4_FLOW16 (f-opc-8-5 #x15) (f-dc-15-3 #x0) (f-dc-9-1 #x0) rn)
1267 (sequence ()
1268 (set (reg h-registers 14) (add pc (const 2)))
1269 (set pc rn)
1270 )
1271 ()
1272 )
1273
1274(dni jalr "jump and link register"
1275 (UNCOND-CTI)
1276 ("jalr $rn6")
1277 (+ OP4_MISC
1278 (f-opc-8-5 #x15)
1279 (f-opc-19-4 #x2)
1280 rn6
1281 (f-dc-9-1 #x0)
1282 (f-dc-15-3 #x0)
1283 (f-dc-25-6 #x0)
1284 (f-dc-31-3 #x0)
1285
1286 )
1287 (sequence ()
1288 (set (reg h-registers 14) (add pc (const 4)))
1289 (set pc rn6))
1290 ()
1291 )
1292
1293\f
1294;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
1295 ; Load/Store Memory Instructions
1296;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
1297
1298
1299(define-pmacro (callMisaligmentExceptionIfNeeded sel addr isAligmentAccess)
1300 (sequence ((BI scale))
1301 (set isAligmentAccess
1302 (case BI sel
1303 ((OPW_BYTE) (eq (and addr #x0) #x0))
1304 ((OPW_SHORT) (eq (and addr #x1) #x0))
1305 ((OPW_WORD) (eq (and addr #x3) #x0))
1306 (else (eq (and addr #x7) #x0))))
1307 (if (not BI isAligmentAccess)
1308 (call-exception #x4 #x2))
1309 )
1310)
1311
1312
1313
1314;; helper to convert size selector OPW_<mode> into a literal scale factor
1315(define-pmacro (ConvertSelectorToShift sel scale)
1316 (set scale
1317 (case SI sel
1318 ((OPW_BYTE) (const 0))
1319 ((OPW_SHORT) (const 1))
1320 ((OPW_WORD) (const 2))
1321 (else (const 3))))
1322)
1323
1324;; common load macros from effective address, handling 8/16/32/64 bits
1325(define-pmacro (load-double-from-ea regnum eff-addr mode sel)
1326 (sequence ((SI loadaddr) (BI isAligmentAccess))
1327 (set loadaddr eff-addr)
1328 (callMisaligmentExceptionIfNeeded sel loadaddr isAligmentAccess)
1329
1330 (if (not (not BI isAligmentAccess))
1331 (sequence ()
1332 (set memaddr loadaddr)
1333 (set regnum (mem SI loadaddr))
1334 (set loadaddr (add loadaddr (const 4)))
1335 (set memaddr loadaddr)
1336 (set (reg h-registers
1337 (add (index-of regnum)
1338 (const 1)))
1339 (mem SI loadaddr))
1340
1341 )
1342 )
1343 )
1344 )
1345
1346(define-pmacro (load-from-ea regnum eff-addr mode sel)
1347 (sequence ((BI isAligmentAccess))
1348
1349 (callMisaligmentExceptionIfNeeded sel eff-addr isAligmentAccess)
1350 (if (not (not BI isAligmentAccess))
1351 (sequence ()
1352 (set memaddr eff-addr)
1353 (set regnum (zext SI (mem mode eff-addr)))
1354 )
1355 )
1356 )
1357 ) ;; 8/16/32 bit cases
1358
1359
1360;; common store to effective address, handling 8/16/32/64 bit data
1361(define-pmacro (store-double-to-ea eff-addr regnum mode sel)
1362 (sequence ((SI storeaddr) (BI isAligmentAccess))
1363 (set storeaddr eff-addr)
1364 (callMisaligmentExceptionIfNeeded sel storeaddr isAligmentAccess)
1365 (if (not (not BI isAligmentAccess))
1366 (sequence ()
1367 (set memaddr storeaddr)
1368 (set (mem SI storeaddr) regnum)
1369 (set storeaddr (add storeaddr (const 4)))
1370 (set memaddr storeaddr)
1371 (set (mem SI storeaddr)
1372 (reg h-registers (add (index-of regnum) (const 1))))
1373 )
1374 )
1375 )
1376 )
1377
1378(define-pmacro (store-to-ea eff-addr regnum mode sel)
1379 (sequence ((BI isAligmentAccess))
1380 (callMisaligmentExceptionIfNeeded sel eff-addr isAligmentAccess)
1381 (if (not (not BI isAligmentAccess))
1382 (sequence ()
1383 (set memaddr eff-addr)
1384 (set (mem mode eff-addr) regnum)
1385 )
1386 )
1387 )
1388 ) ;8/16/32 bit cases
1389
1390
1391(define-pmacro (load-insn name mode sel sem-op)
1392 (begin
1393 (dni_wrapper (.sym name "x16.s")
1394 (.str "load " mode " indexed")
1395 (SHORT-INSN)
1396 (.str name " $rd,[$rn,$rm]")
1397 (+ OP4_LDSTR16X sel OP_LOAD rd rn rm)
1398 (sequence ()
1399 (sem-op rd (add rn rm) mode sel))
1400 ()
1401 )
1402
1403
1404 (dni_wrapper (.sym name "p16.s")
1405 (.str "load " mode " postmodify")
1406 (SHORT-INSN)
1407 (.str name " $rd,[$rn],$rm")
1408 (+ OP4_LDSTR16P sel OP_LOAD rd rn rm)
1409 (sequence ((SI tmprm))
1410 (set tmprm rm)
1411 (sem-op rd rn mode sel)
1412 (set rn (add rn tmprm)))
1413 ()
1414 )
1415
1416
1417 (dni_wrapper (.sym name "x.l")
1418 (.str "load " mode " indexed")
1419 ()
1420 (.str name " $rd6,[$rn6,$direction$rm6]")
1421 (+ OP4_LDSTRX sel OP_LOAD (f-opc-19-4 #x0) (f-dc-22-1 #x0) (f-dc-21-1 #x0) rd6 rn6 direction rm6)
1422 (sequence ()
1423 (if (ifield f-addsubx)
1424 (sem-op rd6 (sub rn6 rm6) mode sel)
1425 (sem-op rd6 (add rn6 rm6) mode sel)))
1426 ()
1427 )
1428
1429 (dnmi (.sym name "x")
1430 (.str "load " mode " indexed")
1431 ()
1432 (.str name ".l $rd6,[$rn6,$direction$rm6]")
1433 (emit (.sym name "x.l") rd6 rn6 direction rm6)
1434 )
1435
1436
1437
1438 (dni_wrapper (.sym name "p.l")
1439 (.str "load " mode " postmodify")
1440 ()
1441 (.str name " $rd6,[$rn6],$direction$rm6")
1442 (+ OP4_LDSTRP sel OP_LOAD (f-opc-19-4 #x0) (f-dc-22-2 #x0) rd6 rn6 direction rm6)
1443 (sequence ((SI tmprm))
1444 (set tmprm rm6)
1445 (sem-op rd6 rn6 mode sel)
1446 (if (ifield f-addsubx)
1447 (set rn6 (sub rn6 tmprm))
1448 (set rn6 (add rn6 tmprm)))
1449 )
1450 ()
1451 )
1452
1453
1454 (dnmi (.sym name "p")
1455 (.str "load " mode " postmodify")
1456 ()
1457 (.str name ".l $rd6,[$rn6],$direction$rm6")
1458 (emit (.sym name "p.l") rd6 rn6 direction rm6)
1459 )
1460
1461
1462 ;;immediate modes last so reg forms found first.
1463 (dni_wrapper (.sym name "d16.s")
1464 (.str "load " mode " displacement")
1465 (SHORT-INSN IMM3)
1466 (.str name " $rd,[$rn,$disp3]")
1467 (+ OP4_LDSTR16D sel OP_LOAD rd rn disp3) ;; convert size to 'B'
1468 (sequence ((SI effa)
1469 (SI scale))
1470 (ConvertSelectorToShift sel scale)
1471 (set effa (add rn (sll disp3 scale)))
1472 (sem-op rd effa mode sel)
1473 )
1474 ()
1475 )
1476
1477
1478 (dni_wrapper (.sym name "d.l")
1479 (.str "load " mode " displacement")
1480 ()
1481 (.str name " $rd6,[$rn6,$dpmi$disp11]")
1482 (+ OP4_LDSTRD sel OP_LOAD PMOD_DISP rd6 rn6 dpmi disp11)
1483 (sequence ((SI effa)
1484 (SI scale))
1485 (ConvertSelectorToShift sel scale)
1486 (if dpmi
1487 (set effa (sub rn6 (sll disp11 scale)))
1488 (set effa (add rn6 (sll disp11 scale)))
1489 )
1490 (sem-op rd6 effa mode sel)
1491 )
1492 ()
1493 )
1494
1495 (dnmi (.sym name "d")
1496 (.str "load " mode " displacement")
1497 ()
1498 (.str name ".l $rd6,[$rn6,$dpmi$disp11]")
1499 (emit (.sym name "d.l") rd6 rn6 dpmi disp11)
1500 )
1501
1502
1503
1504 (dni_wrapper (.sym name "dpm.l")
1505 (.str "load " mode " displacement post-modify")
1506 ()
1507 (.str name " $rd6,[$rn6],$dpmi$disp11")
1508 (+ OP4_LDSTRD sel OP_LOAD PMOD_POST rd6 rn6 dpmi disp11)
1509 (sequence ((SI scale))
1510 (ConvertSelectorToShift sel scale)
1511 (sem-op rd6 rn6 mode sel)
1512 (if dpmi
1513 (set rn6 (sub rn6 (sll disp11 scale)))
1514 (set rn6 (add rn6 (sll disp11 scale)))
1515 )
1516 )
1517 ()
1518 )
1519
1520 (dnmi (.sym name "dpm")
1521 (.str "load " mode " displacement post-modify")
1522 ()
1523 (.str name ".l $rd6,[$rn6],$dpmi$disp11")
1524 (emit (.sym name "dpm.l") rd6 rn6 dpmi disp11)
1525 )
1526
1527
1528 ;; ;; macro form with a zero displacement
1529 (dnmi (.sym name "ds0") "load with 0 disp"
1530 (SHORT-INSN IMM3)
1531 (.str name " $rd,[$rn]")
1532 (emit (.sym name "d16.s") rd rn (disp3 0))
1533 )
1534 (dnmi (.sym name "dl0") "load with 0 disp"
1535 ()
1536 (.str name " $rd6,[$rn6]")
1537 (emit (.sym name "d.l") rd6 rn6 (dpmi 0) (disp11 0))
1538 )
1539 (dnmi (.sym name "dl0.l") "load with 0 disp"
1540 ()
1541 (.str name ".l $rd6,[$rn6]")
1542 (emit (.sym name "d.l") rd6 rn6 (dpmi 0) (disp11 0))
1543 )
1544
1545
1546 )
1547 )
1548
1549(load-insn ldrb QI OPW_BYTE load-from-ea)
1550(load-insn ldrh HI OPW_SHORT load-from-ea)
1551(load-insn ldr SI OPW_WORD load-from-ea)
1552(load-insn ldrd DI OPW_DOUBLE load-double-from-ea)
1553
1554
1555
1556
1557;; TMP = MEM[RD+RM]; /* Copy content of memory to tmp. */
1558;; if (~TMP) /* Check if memory location is zero. */
1559;; MEM[RD+RM] = RD; /* If zero, write RD to memory. */
1560;; RD = TMP; /* Always write tmp into RD (NOTE it's destructive). */
1561
1562
1563(define-pmacro (testset-insn name mode sel)
1564 (begin
1565
1566
1567 (dni_wrapper (.sym name "t")
1568 (.str "testset " mode " indexed")
1569 ()
1570 (.str name " $rd6,[$rn6,$direction$rm6]")
1571 (+ OP4_LDSTRX sel OP_LOAD (f-opc-19-4 #x0) (f-dc-22-1 #x0) (f-dc-21-1 #x1)
1572 rd6 rn6 direction rm6)
1573 (sequence ((SI tmemaddr) (SI tmpValReg))
1574
1575 ;;back up register
1576 (set tmpValReg rd6)
1577
1578 (if (ifield f-addsubx)
1579 (set tmemaddr (sub rn6 rm6))
1580 (set tmemaddr (add rn6 rm6))
1581 )
1582 ;;always update rd
1583 (load-from-ea rd6 tmemaddr mode sel)
1584 ;;if zero
1585 (if rd6
1586 (nop)
1587 (set (mem mode tmemaddr) tmpValReg)
1588 )
1589
1590 )
1591 ()
1592 )
1593
1594
1595 (dnmi (.sym name "t.l")
1596 (.str "testset " mode ".l indexed")
1597 ()
1598 (.str name ".l $rd6,[$rn6,$direction$rm6]")
1599 (emit (.sym name "t") rd6 rn6 direction rm6)
1600 )
1601
1602
1603 )
1604 )
1605
1606(testset-insn testsetb QI OPW_BYTE)
1607(testset-insn testseth HI OPW_SHORT)
1608(testset-insn testset SI OPW_WORD)
1609;;no double mode support, since we have to send the src address, data
1610;;(testset-insn testsetd DI OPW_DOUBLE load-double-from-ea)
1611
1612
1613
1614;; need 16 bit forms too
1615(define-pmacro (store-insn name mode sel sem-op)
1616 (begin
1617 (dni_wrapper (.sym name "x16")
1618 (.str "store" mode " indexed")
1619 (SHORT-INSN)
1620 (.str name " $rd,[$rn,$rm]")
1621 (+ OP4_LDSTR16X sel OP_STORE rd rn rm)
1622 (sequence ()
1623 (sem-op (add rn rm) rd mode sel)
1624 )
1625 ()
1626 )
1627
1628 (dni_wrapper (.sym name "x")
1629 (.str "store" mode " indexed")
1630 ()
1631 (.str name " $rd6,[$rn6,$direction$rm6]")
1632 (+ OP4_LDSTRX sel OP_STORE (f-opc-19-4 #x0) (f-dc-22-1 #x0) (f-dc-21-1 #x0) rd6 rn6 direction rm6)
1633 (sequence ()
1634 (if (ifield f-addsubx)
1635 (sem-op (sub rn6 rm6) rd6 mode sel)
1636 (sem-op (add rn6 rm6) rd6 mode sel)
1637 ))
1638 ()
1639 )
1640
1641 (dnmi (.sym name "x.l")
1642 (.str "store" mode " indexed")
1643 ()
1644 (.str name ".l $rd6,[$rn6,$direction$rm6]")
1645 (emit (.sym name "x") rd6 rn6 direction rm6)
1646 )
1647
1648
1649
1650
1651
1652 (dni_wrapper (.sym name "p16")
1653 (.str "store " mode " postmodify")
1654 (SHORT-INSN)
1655 (.str name " $rd,[$rn],$rm")
1656 (+ OP4_LDSTR16P sel OP_STORE rd rn rm)
1657 (sequence ()
1658 (sem-op rn rd mode sel)
1659 (set rn (add rn rm))
1660 )
1661 ()
1662 )
1663
1664 (dni_wrapper (.sym name "p")
1665 (.str "store " mode " postmodify")
1666 ()
1667 (.str name " $rd6,[$rn6],$direction$rm6")
1668 (+ OP4_LDSTRP sel OP_STORE (f-opc-19-4 #x0) (f-dc-22-2 #x0) rd6 rn6 direction rm6)
1669 (sequence ()
1670 (sem-op rn6 rd6 mode sel)
1671 (if (ifield f-addsubx)
1672 (set rn6 (sub rn6 rm6))
1673 (set rn6 (add rn6 rm6)))
1674 )
1675 ()
1676 )
1677 (dnmi (.sym name "p.l")
1678 (.str "store " mode " postmodify")
1679 ()
1680 (.str name ".l $rd6,[$rn6],$direction$rm6")
1681 (emit (.sym name "p") rd6 rn6 direction rm6)
1682 )
1683
1684 (dni_wrapper (.sym name "d16")
1685 (.str "store " mode " displacement")
1686 (SHORT-INSN IMM3)
1687 (.str name " $rd,[$rn,$disp3]")
1688 (+ OP4_LDSTR16D sel OP_STORE rd rn disp3) ;; convert size to 'B'
1689 (sequence ((SI effa)
1690 (SI scale))
1691 (ConvertSelectorToShift sel scale)
1692 (set effa (add rn (sll disp3 scale)))
1693 (sem-op effa rd mode sel)
1694 )
1695 ()
1696 )
1697
1698 (dni_wrapper (.sym name "d")
1699 (.str "store " mode " displacement")
1700 ()
1701 (.str name " $rd6,[$rn6,$dpmi$disp11]")
1702 (+ OP4_LDSTRD sel OP_STORE PMOD_DISP rd6 rn6 dpmi disp11)
1703 (sequence ((SI effa)
1704 (SI scale))
1705 (ConvertSelectorToShift sel scale)
1706 (if dpmi
1707 (set effa (sub rn6 (sll disp11 scale)))
1708 (set effa (add rn6 (sll disp11 scale)))
1709 )
1710 (sem-op effa rd6 mode sel)
1711 )
1712 ()
1713 )
1714
1715 (dnmi (.sym name "d.l")
1716 (.str "store " mode " displacement")
1717 ()
1718 (.str name ".l $rd6,[$rn6,$dpmi$disp11]")
1719 (emit (.sym name "d") rd6 rn6 dpmi disp11)
1720 )
1721
1722
1723 (dni_wrapper (.sym name "dpm")
1724 (.str "store " mode " displacement post-modify")
1725 ()
1726 (.str name " $rd6,[$rn6],$dpmi$disp11")
1727 (+ OP4_LDSTRD sel OP_STORE PMOD_POST rd6 rn6 dpmi disp11) ;; convert size to 'B'
1728 (sequence ((SI scale))
1729 (ConvertSelectorToShift sel scale)
1730 (sem-op rn6 rd6 mode sel)
1731 (if dpmi
1732 (set rn6 (sub rn6 (sll disp11 scale)))
1733 (set rn6 (add rn6 (sll disp11 scale)))
1734 )
1735 )
1736 ()
1737 )
1738 (dnmi (.sym name "dpm.l")
1739 (.str "store " mode " displacement post-modify")
1740 ()
1741 (.str name ".l $rd6,[$rn6],$dpmi$disp11")
1742 (emit (.sym name "dpm") rd6 rn6 dpmi disp11)
1743 )
1744
1745 ;; macro form with a zero displacement
1746 (dnmi (.sym name "ds0") "store w 0 disp"
1747 (SHORT-INSN IMM3)
1748 (.str name " $rd,[$rn]")
1749 (emit (.sym name "d16") rd rn (disp3 0))
1750 )
1751
1752 (dnmi (.sym name "dl0") "store w 0 disp"
1753 ()
1754 (.str name " $rd6,[$rn6]")
1755 (emit (.sym name "d") rd6 rn6 (dpmi 0) (disp11 0))
1756 )
1757
1758 (dnmi (.sym name "dl0.l") "store w 0 disp"
1759 ()
1760 (.str name ".l $rd6,[$rn6]")
1761 (emit (.sym name "d") rd6 rn6 (dpmi 0) (disp11 0))
1762 )
1763
1764
1765
1766 )
1767 )
1768
1769(store-insn strb QI OPW_BYTE store-to-ea)
1770(store-insn strh HI OPW_SHORT store-to-ea)
1771(store-insn str SI OPW_WORD store-to-ea)
1772(store-insn strd DI OPW_DOUBLE store-double-to-ea)
1773\f
1774;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
1775;; MOV<COND> RD,RN
1776;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
1777
1778(define-pmacro (move-insns name cond g-op)
1779 (begin
1780 (dni_wrapper (.sym "cmov16" cond)
1781 (.str "move register " cond)
1782 (SHORT-INSN)
1783 (.str "mov" name " $rd,$rn")
1784 (+ OP4_FLOW16 (.sym "OPC_" cond) (f-opc-8-1 #x0) (f-dc-9-1 #x0) rd rn)
1785 (if (g-op)
1786 (set rd rn))
1787 ()
1788 )
1789
1790 (dni_wrapper (.sym "cmov" cond)
1791 (.str "move register " cond)
1792 ()
1793 (.str "mov" name " $rd6,$rn6")
1794 (+ OP4_MISC (.sym "OPC_" cond) (f-opc-8-1 #x0) (f-dc-9-1 #x0) (f-opc-19-4 #x2) (f-dc-25-6 #x0) rd6 rn6)
1795 (if (g-op)
1796 (set rd6 rn6))
1797 ()
1798 )
1799 (dnmi (.sym "cmov.l" cond)
1800 (.str "move register " cond)
1801 ()
1802 (.str "mov" name ".l $rd6,$rn6")
1803 (emit (.sym "cmov" cond) rd6 rn6)
1804 )
1805
1806
1807
1808 )
1809 )
1810
1811 ; basic conditional moves
1812(move-insns "eq" EQ (.pmacro () (eq zbit #x1)))
1813(move-insns "ne" NE (.pmacro () (eq zbit #x0)))
1814(move-insns "gtu" GTU (.pmacro () (and BI cbit (not BI zbit))))
1815(move-insns "gteu" GTEU (.pmacro () (eq cbit #x1)))
1816(move-insns "lteu" LTEU (.pmacro () (or BI (not BI cbit) zbit)))
1817(move-insns "ltu" LTU (.pmacro () (eq cbit #x0)))
1818(move-insns "gt" GT (.pmacro () (and BI (not BI zbit) (eq vbit nbit))))
1819(move-insns "gte" GTE (.pmacro () (eq vbit nbit)))
1820(move-insns "lt" LT (.pmacro () (xor BI vbit nbit)))
1821(move-insns "lte" LTE (.pmacro () (or BI zbit (xor vbit nbit))))
1822
1823 ; unconditional move
1824(move-insns "" B (.pmacro () #x1))
1825
1826
1827 ; floating point condition codes (floating point instructions)
1828(move-insns "beq" BEQ (.pmacro () (or BI bzbit bzbit)))
1829(move-insns "bne" BNE (.pmacro () (not BI bzbit)))
1830(move-insns "blt" BLT (.pmacro () (and BI bnbit (not bzbit))))
1831(move-insns "blte" BLTE (.pmacro () (or BI bnbit bzbit)))
1832
1833;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
1834;; MOVTS RD,RN
1835;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
1836
1837;; 16 bits form exists for group zero ( M1 and M0 equals to zero ) only
1838
1839(dni_wrapper movts16
1840 "move to special reg"
1841 (SHORT-INSN)
1842 "movts $sn,$rd"
1843 (+ OP4_FLOW16 (f-opc-8-5 #x10) (f-dc-9-1 #x0) rd sn) ;; rd is source for movts
1844 (set sn rd)
1845 ()
1846 )
1847
1848(define-pmacro (op-mmr-movts name sdreg code)
1849 (begin
1850
1851 (dni_wrapper (.sym "movts" name)
1852 (.str "move to " name)
1853 ()
1854 (.str "movts $" sdreg ",$rd6")
1855 (+ OP4_MISC (f-dc-7-4 #x0) (f-opc-8-1 #x1) (f-dc-9-1 #x0) (f-opc-19-4 #x2) (f-dc-25-4 #x0) (f-dc-21-2 code) sdreg rd6);; rd is source for movts
1856 (set sdreg rd6)
1857 ()
1858 )
1859
1860 (dnmi (.sym "movts.l" name)
1861 (.str "move to " name)
1862 ()
1863 (.str "movts.l $" sdreg ",$rd6")
1864 (emit (.sym "movts" name) sdreg rd6)
1865 )
1866
1867
1868
1869
1870 )
1871 )
1872
1873(op-mmr-movts 6 sn6 #x0)
1874(op-mmr-movts dma sndma #x1)
1875(op-mmr-movts mem snmem #x2)
1876(op-mmr-movts mesh snmesh #x3)
1877
1878;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
1879;; MOVFS
1880;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
1881(dni_wrapper movfs16
1882 "move from special register"
1883 (SHORT-INSN)
1884 "movfs $rd,$sn"
1885 (+ OP4_FLOW16 (f-opc-8-5 #x11) (f-dc-9-1 #x0) rd sn)
1886 (set rd sn)
1887 ()
1888 )
1889
1890
1891
1892(define-pmacro (op-mmr-movfs name snreg code)
1893 (begin
1894
1895 (dni_wrapper (.sym "movfs" name)
1896 (.str "move from " name)
1897 ()
1898 (.str "movfs $rd6,$" snreg)
1899 (+ OP4_MISC (f-dc-7-4 #x1) (f-opc-8-1 #x1) (f-dc-9-1 #x0) (f-opc-19-4 #x2) (f-dc-25-4 #x0) (f-dc-21-2 code) rd6 snreg)
1900 (set rd6 snreg)
1901 ()
1902 )
1903
1904 (dnmi (.sym "movfs.l" name)
1905 (.str "move from " name)
1906 ()
1907 (.str "movfs.l $rd6,$" snreg)
1908 (emit (.sym "movfs" name) rd6 snreg)
1909 )
1910
1911
1912
1913 )
1914 )
1915
1916(op-mmr-movfs 6 sn6 #x0)
1917(op-mmr-movfs dma sndma #x1)
1918(op-mmr-movfs mem snmem #x2)
1919(op-mmr-movfs mesh snmesh #x3)
1920
1921
1922
1923
1924
1925;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
1926;; NOP 0x1a2
1927;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
1928(dni_wrapper nop
1929 "no-operation"
1930 (SHORT-INSN)
1931 "nop"
1932 (+ OP4_FLOW16 (f-opc-8-5 #x1a) (f-dc-15-7 #x0))
1933 (nop)
1934 ()
1935 )
1936
1937
1938;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
1939;; SNOP 0x3a2
1940;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
1941(dni_wrapper snop
1942 "no-operation"
1943 (SHORT-INSN)
1944 "snop"
1945 (+ OP4_FLOW16 (f-opc-8-5 #x3a) (f-dc-15-7 #x0))
1946 (nop)
1947 ()
1948 )
1949
1950
1951;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
1952;; UNIMPL
1953;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
1954(dni_wrapper unimpl
1955 "not-implemented"
1956 ()
1957 "unimpl"
1958 (+ (f-opc-31-32 #x000F000F))
1959 (nop)
1960 ()
1961 )
1962
1963;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
1964;; IDLE
1965;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
1966
1967(dni idle "idle until interrupt" () "idle"
1968 (+ OP4_FLOW16 (f-opc-8-5 #x1b) (f-dc-15-7 #x0))
1969 ;; (set pc pc) ;; should branch to self until interrupt, but not modeling interrupts
1970 (sequence ()
1971 (set caibit 0)
1972 (c-code "sim_engine_halt (CPU_STATE (current_cpu), current_cpu, NULL, \
1973 pc, sim_exited, 0);"))
1974 ()
1975 )
1976
1977;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
1978;; BKPT
1979;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
1980
1981(dni bkpt
1982 "breakpoint"
1983 (SHORT-INSN)
1984 "bkpt"
1985 (+ OP4_FLOW16 (f-opc-8-5 #x1c) (f-dc-15-7 #x0))
1986 (sequence ()
1987 (c-call "epiphany_break" pc)
1988 (set pc pc)
1989 )
1990 ()
1991 )
1992
1993;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
1994;; MBKPT
1995;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
1996
1997(dni mbkpt
1998 "multicorebreakpoint"
1999 (SHORT-INSN)
2000 "mbkpt"
2001 (+ OP4_FLOW16 (f-opc-8-5 #x1c) (f-dc-15-7 #x1))
2002 ;;;(c-call "epiphany_break" pc)
2003 (nop) ;; ignore the multi core break point in the simulator
2004 ()
2005 )
2006
2007;;;;;;;;;;;;;;;;
2008;; RTI
2009;;;;;;;;;;;;;;;;
2010
2011(dni rti "return from interrupt" (SHORT-INSN UNCOND-CTI)
2012 "rti"
2013 (+ OP4_FLOW16 (f-opc-8-5 #x1d) (f-dc-15-7 #x0))
2014 (sequence ()
2015 ;; (set (hcr-ipend)
2016 ;; (xor (hcr-ipend)
2017 ;; (sll (const 1)
2018 ;; (sub (c-raw-call SI "ffs" (and (hcr-ipend) (not (hcr-imask))))
2019 ;; (const 1)))))
2020
2021 (set (hcr-ipend)
2022 (c-call SI "epiphany_rti" (hcr-ipend) (hcr-imask)))
2023 (set gidisablebit 0)
2024 (set kmbit 0)
2025 ;(set caibit 1)
2026 (set pc (hcr-iret)))
2027 ()
2028 )
2029;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2030;; WAND is a wired flag that runs around the chip
2031;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2032(dni_wrapper wand "wand"
2033 (SHORT-INSN)
2034 "wand"
2035 (+ OP4_FLOW16 (f-opc-8-5 #x18) (f-dc-15-7 #x0))
2036 (set sflagbit 1)
2037 ()
2038 )
2039
2040;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2041;; Sync likes wand, but wired OR
2042;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2043(dni_wrapper sync "sync"
2044 (SHORT-INSN)
2045 "sync"
2046 (+ OP4_FLOW16 (f-opc-8-5 #x1f) (f-dc-15-7 #x0))
2047 (nop);;TODO
2048 ()
2049 )
2050
2051;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2052;; GIE
2053;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2054(dni_wrapper gien "global interrupt enable"
2055 (SHORT-INSN)
2056 "gie"
2057 (+ OP4_FLOW16 (f-gien-gidis-9-1 #x0) (f-opc-8-5 #x19) (f-dc-15-6 #x0))
2058 (set gidisablebit 0)
2059 ()
2060 )
2061
2062;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2063;; GIDIS
2064;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2065(dni_wrapper gidis "global interrupt disable"
2066 (SHORT-INSN)
2067 "gid"
2068 (+ OP4_FLOW16 (f-gien-gidis-9-1 #x1) (f-opc-8-5 #x19) (f-dc-15-6 #x0))
2069 (set gidisablebit 1)
2070 ()
2071 )
2072
2073
2074
2075;;;;;;;;;;;;;;;;
2076;; SWI
2077;;;;;;;;;;;;;;;;
2078
2079;; Model only immediate 'fire' exception, if gien cleared or masked don't fire and don't check later - no ilat like behavior
2080(dni swi_num "software interrupt" (SHORT-INSN UNCOND-CTI)
2081 "swi $swi_num"
2082 (+ OP4_FLOW16 (f-opc-8-5 #x1e) (f-trap-swi-9-1 #x0) swi_num)
2083 (sequence () (call-exception #x24 #x80))
2084 ;; (if (eq gie 1)
2085 ;; (sequence ()
2086 ;; (set kmbit 1)
2087 ;; (set gie 0)
2088 ;; (set (hcr-iret) (add pc (const 2)))
2089 ;; (set (hcr-ipend) (or (hcr-ipend) (const #x80)))
2090 ;; (set pc (const #x1c))
2091
2092 ;; )
2093 ;; ;; schedule interrupt
2094 ;; (set (hcr-ilat) (or (hcr-ilat) (const #x80)))
2095 ;; )
2096 ()
2097 )
2098(dni swi "software interrupt" (ALIAS SHORT-INSN UNCOND-CTI)
2099 "swi"
2100 (+ OP4_FLOW16 (f-opc-8-5 #x1e) (f-trap-swi-9-1 #x0) (f-dc-15-6 #x0))
2101 (sequence () (call-exception #x24 #x80))
2102 ()
2103 )
2104
2105
2106;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2107;; TRAP #disp3 - simulator only and chip as well - make the same grouop as swi
2108;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2109
2110;; Only defining 16-bit form of this instruction. It exists to support the
2111;; simulator, by giving us a simple input/output mechanism beyond returning values
2112;; in registers or memory.
2113;; TRAP #N - special sw trap for simulator support; allows simple i/o using fixed arguments
2114;; TRAP #0 - write (r0=i/o channel, r1=addr, r2=len) returns status in r0
2115;; TRAP #1 - read (r0=i/o channel, r1=addr, r2=len) returns length or -<code> on error
2116;; TRAP #2 - open (r0=string path, r1=mode) returns channel# or -<code> on error
2117;; TRAP #3 - exit (r0=status code) never returns.
2118;; TRAP #4 - print "pass\n" and exit
2119;; TRAP #5 - print "fail\n" and exit
2120;; TRAP #6 - close (r0=i/o channel)
2121
2122(dni trap16 "trap to simulator"
2123 (SHORT-INSN UNCOND-CTI)
2124 "trap $trapnum6"
2125 (+ OP4_FLOW16 (f-opc-8-5 #x1e) (f-trap-swi-9-1 #x1) trapnum6) ;; (+ OP4_IMM16 OPI_TRAP (f-rd 0) (f-rn 0) disp3)
2126 (set (reg SI h-registers 0) (c-call SI "epiphany_trap" pc trapnum6))
2127 ()
2128 )
2129
2130\f
2131;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2132;; Integer arithmetic instructions 3 address forms
2133;; both 16 and 32 bit forms
2134;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2135
2136(define-pmacro (op-rrr name sem-op cond-op)
2137 (begin
2138 (dni_wrapper (.sym name "16")
2139 (.str name)
2140 (SHORT-INSN)
2141 (.str name " $rd,$rn,$rm")
2142 (+ OP4_ALU16 (.sym "OPB_" (.upcase (.str name))) rd rn rm)
2143 (sequence ()
2144 (cond-op rn rm)
2145 (set rd (sem-op SI rn rm))
2146 (set zbit (zflag rd))
2147 (set nbit (nflag rd))
2148 )
2149 ()
2150 )
2151
2152 (dni_wrapper (.sym name)
2153 (.str name)
2154 ()
2155 (.str name " $rd6,$rn6,$rm6")
2156 (+ OP4_MISC (.sym "OPB_" (.upcase (.str name))) (f-opc-19-4 #xa) (f-dc-22-3 #x0) rd6 rn6 rm6)
2157 (sequence ()
2158 (cond-op rn6 rm6)
2159 (set rd6 (sem-op SI rn6 rm6))
2160 (set zbit (zflag rd6))
2161 (set nbit (nflag rd6))
2162 )
2163 ()
2164 )
2165
2166 (dnmi (.sym name ".l")
2167 (.str name)
2168 ()
2169 (.str name ".l $rd6,$rn6,$rm6")
2170 (emit (.sym name) rd6 rn6 rm6)
2171 )
2172
2173
2174
2175 )
2176 )
2177
2178;; submacros to set condition codes
2179;; NZ are always set to reflect the sign and value of the result
2180;; CV are a function of the operator
2181(define-pmacro (add-vc a b) (sequence ()
2182 (set cbit (add-cflag SI a b 0))
2183 (set vbit (add-oflag SI a b 0))
2184 (set vsbit (or BI vsbit vbit))
2185 ))
2186
2187(define-pmacro (sub-vc a b) (sequence ()
2188 (set cbit (not (sub-cflag SI a b 0)))
2189 (set vbit (sub-oflag SI a b 0))
2190 (set vsbit (or vsbit vbit))
2191 ))
2192
2193(define-pmacro (logic-vc a b) (sequence ()
2194 (set cbit 0)
2195 (set vbit 0)
2196 ))
2197
2198(op-rrr add add add-vc)
2199(op-rrr sub sub sub-vc)
2200(op-rrr and and logic-vc)
2201(op-rrr orr or logic-vc)
2202(op-rrr eor xor logic-vc)
2203
2204;; Integer arithmetic immediate forms
2205
2206(define-pmacro (op-rri name code cond-op)
2207 (begin
2208 (dni_wrapper (.sym name "i16")
2209 (.str name)
2210 (SHORT-INSN IMM3)
2211 (.str name ".s $rd,$rn,$simm3")
2212 (+ OP4_IMM16 code rd rn simm3)
2213 (sequence ()
2214 (cond-op rn simm3)
2215 (set rd (name SI rn simm3))
2216 (set zbit (zflag rd))
2217 (set nbit (nflag rd))
2218 )
2219 ()
2220 )
2221
2222
2223 (dni_wrapper (.sym name "i")
2224 (.str name)
2225 ()
2226 (.str name ".l $rd6,$rn6,$simm11")
2227 (+ OP4_IMM32 code OPI_25_2_MBZ rd6 rn6 simm11)
2228 (sequence ()
2229 (cond-op rn6 simm11)
2230 (set rd6 (name SI rn6 simm11))
2231 (set zbit (zflag rd6))
2232 (set nbit (nflag rd6))
2233 )
2234 ()
2235 )
2236
2237 ;; (dnmi (.sym name "ri") "relaxed arithmetic immediate" (RELAXED)
2238 ;; (.str name " $rd6,$rn6,$simm11")
2239 ;; (emit (.sym name "i") rd6 rn6 simm11))
2240 )
2241 )
2242
2243(op-rri add OPI_ADD add-vc)
2244(op-rri sub OPI_SUB sub-vc)
2245
2246(dnmi addir "relaxable short immediate add" (RELAXABLE IMM3)
2247 "add $rd,$rn,$simm3"
2248 (emit addi16 rd rn simm3))
2249
2250(dnmi addi32r "relaxed long immediate add" (RELAXED)
2251 "add $rd6,$rn6,$simm11"
2252 (emit addi rd6 rn6 simm11))
2253
2254;; Again, but not relaxable so that full sized registers are handled
2255(dnmi addi32m "relaxed long immediate add" ()
2256 "add $rd6,$rn6,$simm11"
2257 (emit addi rd6 rn6 simm11))
2258
2259
2260(dnmi subir "relaxable short immediate sub" (RELAXABLE IMM3)
2261 "sub $rd,$rn,$simm3"
2262 (emit subi16 rd rn simm3))
2263
2264(dnmi subi32r "relaxed long immediate sub" (RELAXED)
2265 "sub $rd6,$rn6,$simm11"
2266 (emit subi rd6 rn6 simm11))
2267
2268(dnmi subi32m "relaxed long immediate sub" ()
2269 "sub $rd6,$rn6,$simm11"
2270 (emit subi rd6 rn6 simm11))
2271
2272
2273;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2274;; Shift instructions 3 address forms
2275;; both 16 and 32 bit forms
2276;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2277
2278(define-pmacro (shift-rrr name sem-op)
2279 (begin
2280 (dni_wrapper (.sym name "16")
2281 (.str name)
2282 (SHORT-INSN)
2283 (.str name " $rd,$rn,$rm")
2284 (+ OP4_ALU16 (.sym "OPB_" (.upcase (.str name))) rd rn rm)
2285 (sequence ()
2286 (logic-vc rn rm)
2287 (set rd (sem-op SI rn (and rm (const 31))))
2288 (set zbit (zflag rd))
2289 (set nbit (nflag rd))
2290 )
2291 ()
2292 )
2293
2294 (dni_wrapper (.sym name)
2295 (.str name)
2296 ()
2297 (.str name " $rd6,$rn6,$rm6")
2298 (+ OP4_MISC (.sym "OPB_" (.upcase (.str name))) (f-opc-19-4 #xa) (f-dc-22-3 #x0) rd6 rn6 rm6)
2299 (sequence ()
2300 (logic-vc rn6 rm6)
2301 (set rd6 (sem-op SI rn6 (and rm6 (const 31))))
2302 (set zbit (zflag rd6))
2303 (set nbit (nflag rd6))
2304 )
2305 ()
2306 )
2307
2308 (dnmi (.sym name ".l")
2309 (.str name)
2310 ()
2311 (.str name ".l $rd6,$rn6,$rm6")
2312 (emit (.sym name) rd6 rn6 rm6)
2313 )
2314 )
2315 )
2316
2317(shift-rrr asr sra)
2318(shift-rrr lsr srl)
2319(shift-rrr lsl sll)
2320
2321(define-pmacro (op-shift-rri name shortcode f5 longcode sem-op)
2322 (begin
2323 (dni_wrapper (.sym name "i16")
2324 (.str name)
2325 (SHORT-INSN)
2326 (.str name " $rd,$rn,$shift")
2327 (+ shortcode (f-opc-4-1 f5) rd rn shift)
2328 (sequence ()
2329 (logic-vc rn shift)
2330 (set rd (sem-op SI rn shift))
2331 (set zbit (zflag rd))
2332 (set nbit (nflag rd))
2333 )
2334 ()
2335 )
2336 (dni_wrapper (.sym name "i32")
2337 (.str name)
2338 ()
2339 (.str name " $rd6,$rn6,$shift")
2340 (+ OP4_MISC (f-opc-4-1 f5) (f-opc-19-4 longcode) (f-dc-25-6 0) rd6 rn6 shift)
2341 (sequence ()
2342 (logic-vc rn6 shift)
2343 (set rd6 (sem-op SI rn6 shift))
2344 (set zbit (zflag rd6))
2345 (set nbit (nflag rd6))
2346 )
2347 ()
2348 )
2349
2350 (dnmi (.sym name "i32.l")
2351 (.str name)
2352 ()
2353 (.str name ".l $rd6,$rn6,$shift")
2354 (emit (.sym name "i32") rd6 rn6 shift)
2355 )
2356
2357
2358 )
2359 )
2360
2361(op-shift-rri lsr OP4_LSHIFT16 0 #x6 srl)
2362(op-shift-rri lsl OP4_LSHIFT16 1 #x6 sll)
2363(op-shift-rri asr OP4_ASHIFT16 0 #xe sra)
2364
2365;; BITR - bitreversal (FFT)
2366;;
2367;; From Dr Dobbs et al.
2368;;
2369;; unsigned int v;
2370;; v = ((v >> 1) & 0x55555555) | ((v & 0x55555555) << 1); ;; swap odd-even bits
2371;; v = ((v >> 2) & 0x33333333) | ((v & 0x33333333) << 2); ;; swap pairs
2372;; v = ((v >> 4) & 0x0f0f0f0f) | ((v & 0x0f0f0f0f) << 4); ;; swap nibbles
2373;; v = ((v >> 8) & 0x00ff00ff) | ((v & 0x00ff00ff) << 8); ;; swap bytes
2374;; v = (v >> 16) | (v << 16); ;; swap halves
2375(define-pmacro (bit-reversal dest src)
2376 (sequence ((SI v))
2377 (set v src)
2378 (set v (or (and (srl v 1) #x55555555) (sll (and v #x55555555) 1)))
2379 (set v (or (and (srl v 2) #x33333333) (sll (and v #x33333333) 2)))
2380 (set v (or (and (srl v 4) #x0f0f0f0f) (sll (and v #x0f0f0f0f) 4)))
2381 (set v (or (and (srl v 8) #x00ff00ff) (sll (and v #x00ff00ff) 8)))
2382 (set v (or (srl v 16) (sll v 16)))
2383 (set dest v)
2384 ))
2385
2386(dni_wrapper bitr16 "bit reverse short"
2387 (SHORT-INSN)
2388 ("bitr $rd,$rn")
2389 (+ OP4_ASHIFT16 (f-opc-4-1 1) rd rn (f-shift 0))
2390 (sequence ()
2391 (bit-reversal rd rn)
2392 (set zbit (zflag rd))
2393 (set nbit (nflag rd))
2394 (set cbit 0)
2395 (set vbit 0)
2396 )
2397 ()
2398 )
2399
2400(dni_wrapper bitr "bit reverse"
2401 ()
2402 ("bitr $rd6,$rn6")
2403 (+ OP4_MISC (f-opc-4-1 1) (f-opc-19-4 #xe) (f-dc-25-6 0) rd6 rn6 (f-shift 0))
2404 (sequence ()
2405 (bit-reversal rd6 rn6)
2406 (set zbit (zflag rd6))
2407 (set nbit (nflag rd6))
2408 (set cbit 0)
2409 (set vbit 0)
2410 )
2411 ()
2412 )
2413(dnmi bitrl "bit reverse l"
2414 ()
2415 ("bitr.l $rd6,$rn6")
2416 (emit bitr rd6 rn6)
2417 )
2418
2419;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2420;; Integer arithmetic instructions
2421;; Extended operation
2422;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2423
2424(define-pmacro (op-iextrrr name cond-op)
2425 (begin
2426
2427 (dni_wrapper (.sym name)
2428 (.str name)
2429 ()
2430 (.str name " $rd6,$rn6,$rm6")
2431 (+ OP4_MISC (.sym "OPBE_" (.upcase (.str name))) (f-opc-19-4 #xa) (f-dc-22-2 #x0) (f-dc-20-1 #x1)
2432 rd6 rn6 rm6)
2433 (sequence ()
2434 ;; TODO cond operation (cond-op rn6 rm6)
2435 ;;(set rd6 (sem-op SI rn6 rm6))
2436 (set zbit (zflag rd6))
2437 (set nbit (nflag rd6))
2438 )
2439 ()
2440 )
2441
2442 (dnmi (.sym name ".l")
2443 (.str name)
2444 ()
2445 (.str name ".l $rd6,$rn6,$rm6")
2446 (emit (.sym name) rd6 rn6 rm6)
2447 )
2448 )
2449 )
2450
2451(op-iextrrr fext sub-vc)
2452(op-iextrrr fdep sub-vc)
2453(op-iextrrr lfsr sub-vc)
2454
2455
2456
2457;; Immediate moves. The 8 bit form is relaxed if it doesn't fit or is external
2458;; Move RD,#IMM
2459(dni_wrapper mov8
2460 "mov imm8"
2461 (SHORT-INSN)
2462 "mov.b $rd,$imm8"
2463 (+ OP4_IMM16 (f-opc-4-1 #x0) rd imm8)
2464 (set rd (zext SI imm8))
2465 ()
2466 )
2467
2468(dnmi mov8r "mov imm8 relaxable"
2469 (RELAXABLE)
2470 "mov $rd,$imm8"
2471 (emit mov8 rd imm8))
2472
2473(dni_wrapper mov16
2474 "mov imm16"
2475 ()
2476 "mov.l $rd6,$imm16"
2477 (+ OP4_IMM32 (f-opc-4-1 #x0) (f-opc-19-4 #x2) (f-dc-28-1 #x0) rd6 imm16)
2478 (set rd6 (zext SI imm16))
2479 ()
2480 )
2481
2482(dnmi mov16r "mov imm16 relaxable"
2483 ()
2484 "mov $rd6,$imm16"
2485 (emit mov16 rd6 imm16))
2486
2487;; MOVE TO HIGH WORD
2488(dni_wrapper movt
2489 "movt imm16"
2490 ()
2491 "movt $rd6,$imm16"
2492 (+ OP4_IMM32 (f-opc-4-1 #x0) (f-opc-19-4 #x2) (f-dc-28-1 #x1) rd6 imm16)
2493 (set rd6 (or (and SI rd6 (const #xffff)) ; keep low bits of rd
2494 (sll SI imm16 (const 16)))) ; replacing just high bits
2495 ()
2496 )
2497(dnmi movtl
2498 "movt imm16"
2499 ()
2500 "movt.l $rd6,$imm16"
2501 (emit movt rd6 imm16)
2502 )
2503
2504
2505
2506;; FLOATING POINT OPERATIONS
2507;; TWO operands
2508(define-pmacro (op-two_operands-float name code)
2509 (begin
2510 (dni_wrapper
2511 (.sym "f_" name "f16")
2512 (.str "f_" name)
2513 (SHORT-INSN)
2514 (.str "f" name " $rd,$rn,$rm")
2515 (+ OP4_DSP16 code rd rn rm)
2516 (sequence ()
2517 (if
2518 (eq arithmetic-modebit2 0)
2519 (sequence ((SF fptemp) (SI sdtmp))
2520 (set sdtmp (c-call SI (.str "epiphany_f" name) rd rn rm))
2521
2522 ;;All bits are calculated in C
2523 (set bzbit (c-call BI "get_epiphany_fzeroflag" sdtmp))
2524 (set bnbit (c-call BI "get_epiphany_fnegativeflag" sdtmp))
2525 (set bvbit (c-call BI "get_epiphany_foverflowflag" sdtmp))
2526 (set bubit (c-call BI "get_epiphany_funderflowflag" sdtmp))
2527 (set bibit (c-call BI "get_epiphany_finvalidflag" sdtmp))
2528 (set bvsbit (or bvsbit bvbit))
2529 (set busbit (or busbit bubit))
2530 (set bisbit (or bisbit bibit))
2531 (set rd sdtmp)
2532 (if (or (and invExcEnbit bisbit)
2533 (or (and ovfExcEnbit bvsbit) (and unExcEnbit busbit)))
2534 (sequence ()
2535 (set expcause0bit (const 1))
2536 (set expcause1bit (const 1))
2537 (call-exception #x4 #x2)))
2538 ))
2539 (if (eq arithmetic-modebit2 1)
2540 (sequence ((SI sdtmp))
2541 (set sdtmp (c-call SI (.str "epiphany_i" name) rd rn rm))
2542 ;; carry is not connected inb the design (set bcbit bcbit)
2543 (set bzbit (zflag sdtmp))
2544 (set bnbit (nflag sdtmp))
2545 (set rd sdtmp)))
2546 )
2547
2548 ()
2549 )
2550 (dnmi (.sym "i_" name "f16")
2551 (.str "i_" name)
2552 (SHORT-INSN NO-DIS)
2553 (.str "i" name " $rd,$rn,$rm")
2554 (emit (.sym "f_" name "f16") rd rn rm)
2555 )
2556
2557
2558 (dni_wrapper
2559 (.sym "f_" name "f32")
2560 (.str "f_" name)
2561 ()
2562 (.str "f" name " $rd6,$rn6,$rm6")
2563 (+ OP4_MISC code (f-opc-19-4 #x7) (f-dc-22-3 #x0) rd6 rn6 rm6)
2564 (sequence ()
2565 (if
2566 (eq arithmetic-modebit2 0)
2567 (sequence ((SF fptemp) (SI sdtmp))
2568 (set sdtmp (c-call SI (.str "epiphany_f" name) rd6 rn6 rm6))
2569
2570 ;;All bits are calculated in C
2571 (set bzbit (c-call BI "get_epiphany_fzeroflag" sdtmp))
2572 (set bnbit (c-call BI "get_epiphany_fnegativeflag" sdtmp))
2573 (set bvbit (c-call BI "get_epiphany_foverflowflag" sdtmp))
2574 (set bubit (c-call BI "get_epiphany_funderflowflag" sdtmp))
2575 (set bibit (c-call BI "get_epiphany_finvalidflag" sdtmp))
2576 (set bvsbit (or bvsbit bvbit))
2577 (set busbit (or busbit bubit))
2578 (set bisbit (or bisbit bibit))
2579
2580 (set rd6 sdtmp)
2581
2582 (if (or (and invExcEnbit bisbit)
2583 (or (and ovfExcEnbit bvsbit) (and unExcEnbit busbit)))
2584 (sequence ()
2585 (set expcause0bit (const 1))
2586 (set expcause1bit (const 1))
2587 (call-exception #x4 #x2)))
2588 )
2589 )
2590 (if (eq arithmetic-modebit2 1)
2591 (sequence ((SI sdtmp))
2592 (set sdtmp (c-call SI (.str "epiphany_i" name) rd6 rn6 rm6))
2593 ;; carry is not connected inb the design (set bcbit bcbit)
2594 (set bzbit (zflag sdtmp))
2595 (set bnbit (nflag sdtmp))
2596 (set rd6 sdtmp)
2597 )
2598 )
2599 )
2600 ()
2601 )
2602
2603 (dnmi (.sym "f_" name "f32.l")
2604 (.str "f_" name)
2605 ()
2606 (.str "f" name ".l $rd6,$rn6,$rm6")
2607 (emit (.sym "f_" name "f32") rd6 rn6 rm6)
2608 )
2609 (dnmi (.sym "i_" name "f32")
2610 (.str "i_" name)
2611 (NO-DIS)
2612 (.str "i" name " $rd6,$rn6,$rm6")
2613 (emit (.sym "f_" name "f32") rd6 rn6 rm6)
2614 )
2615 (dnmi (.sym "i_" name "f32.l")
2616 (.str "i_" name)
2617 (NO-DIS)
2618 (.str "i" name ".l $rd6,$rn6,$rm6")
2619 (emit (.sym "f_" name "f32") rd6 rn6 rm6)
2620 )
2621
2622
2623
2624 )
2625 )
2626
2627(op-two_operands-float add OPF_ADD)
2628(op-two_operands-float sub OPF_SUB)
2629(op-two_operands-float mul OPF_MUL)
2630(op-two_operands-float madd OPF_MADD)
2631(op-two_operands-float msub OPF_MSUB)
2632
2633;; ONE operands
2634;; FABS
2635(define-pmacro (op-fabs-float name code)
2636 (begin
2637 (dni_wrapper (.sym "f_" name "f16")
2638 (.str "f_" name)
2639 (SHORT-INSN)
2640 (.str "f" name " rd,rn")
2641 (+ OP4_DSP16 code rd rn rn)
2642 (sequence ((SF fptemp) (SI sdtmp))
2643
2644 ;(set sdtmp (and rn #x7fffffff))
2645 (set sdtmp (c-call SI (.str "epiphany_fabs") rd rn rn))
2646
2647
2648 (set bnbit (const SI 0))
2649 (set bzbit (eq SI sdtmp (const SI 0)))
2650
2651 ;;TODO subnormal ??
2652 (set bvsbit (or bvsbit bvbit))
2653 (set busbit (or busbit bubit))
2654 (set bisbit (or bisbit bibit))
2655
2656 (set rd sdtmp)
2657 )
2658 ()
2659 )
2660
2661 (dni_wrapper (.sym "f_" name "f32")
2662 (.str "f_" name)
2663 ()
2664 (.str "f" name " $rd6,$rn6")
2665 (+ OP4_MISC code (f-opc-19-4 #x7) (f-dc-22-3 #x0) rd6 rn6 rn6)
2666 (sequence ((SF fptemp) (SI sdtmp))
2667
2668
2669 ;(set sdtmp (and rn6 #x7fffffff))
2670
2671 (set sdtmp (c-call SI (.str "epiphany_fabs") rd6 rn6 rn6))
2672
2673
2674 (set bnbit (const SI 0))
2675 (set bzbit (eq SI sdtmp (const SI 0)))
2676
2677 (set bvsbit (or bvsbit bvbit))
2678 (set busbit (or busbit bubit))
2679 (set bisbit (or bisbit bibit))
2680
2681 (set rd6 sdtmp)
2682
2683 )
2684 ()
2685 )
2686
2687 (dnmi (.sym "f_" name "f32.l")
2688 (.str "f_" name)
2689 ()
2690 (.str "f" name ".l $rd6,$rn6")
2691 (emit (.sym "f_" name "f32") rd6 rn6)
2692 )
2693
2694
2695 )
2696 )
2697
2698(op-fabs-float abs OPF_FABS)
2699
2700
2701(define-pmacro (op-fix2float-float name code)
2702 (begin
2703 (dni_wrapper (.sym "f_" name "f16")
2704 (.str "f_" name)
2705 (SHORT-INSN)
2706 (.str "f" name " $rd,$rn")
2707 (+ OP4_DSP16 code frd frn frn)
2708 (sequence ((SF fptemp) (SI sdtmp))
2709
2710 (set sdtmp (c-call SI (.str "epiphany_f" name) rd rn rn))
2711
2712 (set bnbit (lt SI sdtmp (const SI 0)))
2713 (set bzbit (eq SI sdtmp (const SI 0)))
2714
2715 (set bvsbit (or bvsbit bvbit))
2716 (set busbit (or busbit bubit))
2717 (set bisbit (or bisbit bibit))
2718
2719 (set rd sdtmp)
2720 )
2721 ()
2722 )
2723
2724
2725 (dni_wrapper (.sym "f_" name "f32")
2726 (.str "f_" name)
2727 ()
2728 (.str "f" name " $rd6,$rn6")
2729 (+ OP4_MISC code (f-opc-19-4 #x7) (f-dc-22-3 #x0) rd6 rn6 rn6)
2730 (sequence ((SF fptemp) (SI sdtmp))
2731
2732 (set sdtmp (c-call SI (.str "epiphany_f" name) rd6 rn6 rn6))
2733
2734 (set bnbit (lt SI sdtmp (const SI 0)))
2735 (set bzbit (eq SI sdtmp (const SI 0)))
2736
2737 (set bvsbit (or bvsbit bvbit))
2738 (set busbit (or busbit bubit))
2739 (set bisbit (or bisbit bibit))
2740
2741 (set rd6 sdtmp)
2742
2743 )
2744 ()
2745 )
2746
2747 (dnmi (.sym "f_" name "f32.l")
2748 (.str "f_" name)
2749 ()
2750 (.str "f" name ".l $rd6,$rn6")
2751 (emit (.sym "f_" name "f32") rd6 rn6)
2752 )
2753 )
2754 )
2755
2756(op-fix2float-float loat OPF_FLOAT)
2757
2758(define-pmacro (op-float2fix-float name code)
2759 (begin
2760 (dni_wrapper (.sym "f_" name "f16")
2761 (.str "f_" name)
2762 (SHORT-INSN)
2763 (.str "f" name " $rd,$rn")
2764 (+ OP4_DSP16 code rd rn rn)
2765 (sequence ((SF fptemp) (SI sdtmp))
2766
2767 (set sdtmp (c-call SI (.str "epiphany_f" name) rd rn rn))
2768
2769 (set bzbit (zflag sdtmp))
2770 (set bnbit (nflag sdtmp))
2771
2772 (set bvbit (c-call BI "get_epiphany_foverflowflag" sdtmp))
2773 (set bubit (c-call BI "get_epiphany_funderflowflag" sdtmp))
2774 (set bibit (c-call BI "get_epiphany_finvalidflag" sdtmp))
2775
2776 (set bvsbit (or bvsbit bvbit))
2777 (set busbit (or busbit bubit))
2778 (set bisbit (or bisbit bibit))
2779
2780 (set rd6 sdtmp)
2781
2782 (if (or (and invExcEnbit bisbit)
2783 (or (and ovfExcEnbit busbit)
2784 (and unExcEnbit bvsbit)))
2785 (sequence ()
2786 (set expcause0bit (const 1))
2787 (set expcause1bit (const 1))
2788 (call-exception #x4 #x2)))
2789 (set rd sdtmp)
2790 )
2791 ()
2792 )
2793
2794
2795
2796 (dni_wrapper (.sym "f_" name "f32")
2797 (.str "f_" name)
2798 ()
2799 (.str "f" name " $rd6,$rn6")
2800 (+ OP4_MISC code (f-opc-19-4 #x7) (f-dc-22-3 #x0) rd6 rn6 rn6)
2801 (sequence ((SF fptemp) (SI sdtmp))
2802
2803 (set sdtmp (c-call SI (.str "epiphany_f" name) rd6 rn6 rm6))
2804
2805 (set bzbit (zflag sdtmp))
2806 (set bnbit (nflag sdtmp))
2807
2808 (set bvbit (c-call BI "get_epiphany_foverflowflag" sdtmp))
2809 (set bubit (c-call BI "get_epiphany_funderflowflag" sdtmp))
2810 (set bibit (c-call BI "get_epiphany_finvalidflag" sdtmp))
2811
2812 (set bvsbit (or bvsbit bvbit))
2813 (set busbit (or busbit bubit))
2814 (set bisbit (or bisbit bibit))
2815
2816 (set rd6 sdtmp)
2817
2818 (if (or (and invExcEnbit bisbit)
2819 (or (and ovfExcEnbit busbit)
2820 (and unExcEnbit bvsbit)))
2821 (sequence ()
2822 (set expcause0bit (const 1))
2823 (set expcause1bit (const 1))
2824 (call-exception #x4 #x2))
2825 )
2826
2827 )
2828 ()
2829 )
2830
2831 (dnmi (.sym "f_" name "f32.l")
2832 (.str "f_" name)
2833 ()
2834 (.str "f" name ".l $rd6,$rn6")
2835 (emit (.sym "f_" name "f32") rd6 rn6)
2836 )
2837
2838
2839 )
2840 )
2841
2842
2843
2844
2845
2846(op-float2fix-float ix OPF_FIX)
2847
2848;; MAC (Multiply and Accumulate Instructions
2849;; (define-pmacro (op-mac-float name code)
2850;; (begin
2851;; (dni_wrapper (.sym "fm" name "f16")
2852;; (.str "fm" name)
2853;; (SHORT-INSN)
2854;; (.str "fm" name " $frd,$frn,$frm")
2855;; (+ OP4_DSP16 code frd frn frm)
2856;; (sequence ((SF fptemp))
2857;; (set bvbit 0)
2858;; (set busbit 0)
2859;; (set fptemp (c-call SF (.str "epiphany_fm" name) frd frm frn))
2860;; (set bnbit (lt SF fptemp (const SF 0)))
2861;; (set bzbit (eq SF fptemp (const SF 0)))
2862;; (set bvsbit (or bvsbit bvbit))
2863;; (set frd fptemp)
2864;; ; (set rd (subword SI frd 0))
2865;; )
2866;; ()
2867;; )
2868
2869;; (dni_wrapper (.sym "fm" name "f32")
2870;; (.str "fm" name)
2871;; ()
2872;; (.str "fm" name " $frd6,$frn6,$frm6")
2873;; (+ OP4_MISC code (f-opc-19-4 #x7) (f-dc-22-3 #x0) frd6 frn6 frm6)
2874;; (sequence ((SF fptemp))
2875;; (set bvbit 0)
2876;; (set busbit 0)
2877;; (set fptemp (c-call SF (.str "epiphany_fm" name) frd6 frm6 frn6))
2878;; (set bnbit (lt SF fptemp (const SF 0)))
2879;; (set bzbit (eq SF fptemp (const SF 0)))
2880;; (set bvsbit (or bvsbit bvbit))
2881;; (set frd6 fptemp)
2882;; ; (set rd6 (subword SI frd6 0))
2883;; )
2884;; ()
2885;; )
2886;; )
2887;; )
2888
2889
2890
2891
2892
2893
2894
2895 ; extended floating point operation
2896
2897
2898(define-pmacro (op-fextop-float name code)
2899 (begin
2900
2901 (dni_wrapper (.sym "f_" name "f32")
2902 (.str "f_" name)
2903 ()
2904 (.str "f" name " $frd6,$frn6")
2905 (+ OP4_MISC code (f-opc-19-4 #x7) (f-dc-22-2 #x0) (f-dc-20-1 #x1) frd6 frn6 frn6)
2906 (sequence ((SF fptemp))
2907 (set bvbit 0)
2908 (set busbit 0)
2909 (set fptemp (c-call SF (.str "epiphany_f" name) frn6))
2910 (set bnbit (lt SF fptemp (const SF 0)))
2911 (set bzbit (eq SF fptemp (const SF 0)))
2912 (set bvsbit (or bvsbit bvbit))
2913 (set frd6 fptemp)
2914
2915 )
2916 ()
2917 )
2918
2919
2920 (dnmi (.sym "f_" name "f32.l")
2921 (.str "f_" name)
2922 ()
2923 (.str "f" name ".l $frd6,$frn6")
2924 (emit (.sym "f_" name "f32") frd6 frn6)
2925 )
2926 )
2927 )
2928
2929(op-fextop-float recip OPF_FRECIP)
2930(op-fextop-float sqrt OPF_FSQRT)
2931
2932
2933
2934
2935
GDB Binutils - Deliverables
This page took 0.170774 seconds and 4 git commands to generate.