projects / deliverable / binutils-gdb.git / blame
| Commit | Line | Data |
|---|---|---|
| 539ee71a | 1 | ; IQ2000/IQ10 Common CPU description. -*- Scheme -*- |
| aa820537 | 2 | ; Copyright 2001, 2002, 2007, 2009 Free Software Foundation, Inc. |
| 9b201bb5 NC |
3 | ; |
| 4 | ; Contributed by Red Hat Inc; developed under contract from Fujitsu. | |
| 5 | ; | |
| 6 | ; This file is part of the GNU Binutils. | |
| 7 | ; | |
| 8 | ; This program is free software; you can redistribute it and/or modify | |
| 9 | ; it under the terms of the GNU General Public License as published by | |
| 10 | ; the Free Software Foundation; either version 3 of the License, or | |
| 11 | ; (at your option) any later version. | |
| 12 | ; | |
| 13 | ; This program is distributed in the hope that it will be useful, | |
| 14 | ; but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 15 | ; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 16 | ; GNU General Public License for more details. | |
| 17 | ; | |
| 18 | ; You should have received a copy of the GNU General Public License | |
| 19 | ; along with this program; if not, write to the Free Software | |
| 20 | ; Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, | |
| 21 | ; MA 02110-1301, USA. | |
| 539ee71a AC |
22 | |
| 23 | (include "simplify.inc") | |
| 24 | ||
| 25 | (define-arch | |
| 26 | (name iq2000) | |
| 27 | (comment "IQ2000 architecture") | |
| 28 | (insn-lsb0? #t) | |
| 29 | (machs iq2000 iq10) | |
| 30 | (isas iq2000) | |
| 31 | ) | |
| 32 | ||
| 33 | (define-isa | |
| 34 | (name iq2000) | |
| 35 | (comment "Basic IQ2000 instruction set") | |
| 36 | (default-insn-word-bitsize 32) | |
| 37 | (default-insn-bitsize 32) | |
| 38 | (base-insn-bitsize 32) | |
| 39 | (decode-assist (31 30 29 28 27 26)) | |
| 40 | ) | |
| 41 | ||
| 42 | (define-cpu | |
| 43 | (name iq2000bf) | |
| 44 | (comment "IQ2000 family") | |
| 45 | (endian big) | |
| 46 | (word-bitsize 32) | |
| 47 | (file-transform "") | |
| 48 | ) | |
| 49 | ||
| 50 | (define-cpu | |
| 51 | (name iq10bf) | |
| 52 | (comment "IQ10 coprocessor family") | |
| 53 | (endian big) | |
| 54 | (word-bitsize 32) | |
| 55 | (file-transform "") | |
| 56 | ||
| 57 | ) | |
| 58 | ||
| 59 | (define-mach | |
| 60 | (name iq2000) | |
| 61 | (comment "IQ2000 packet processing engine") | |
| 62 | (cpu iq2000bf) | |
| 63 | (isas iq2000) | |
| 64 | ) | |
| 65 | ||
| 66 | (define-mach | |
| 67 | (name iq10) | |
| 68 | (comment "IQ10 coprocessor") | |
| 69 | (cpu iq10bf) | |
| 70 | (isas iq2000) | |
| 71 | ) | |
| 72 | ||
| 73 | (define-model | |
| 74 | (name iq2000) | |
| 75 | (comment "IQ2000 microprocessor") | |
| 76 | (mach iq2000) | |
| 77 | (unit u-exec "Execution Unit" () | |
| 78 | 1 1 ; issue done | |
| 79 | () () () ()) | |
| 80 | ) | |
| 81 | ||
| 82 | (define-model | |
| 83 | (name iq10) | |
| 84 | (comment "IQ10 coprocessor") | |
| 85 | (mach iq10) | |
| 86 | (unit u-exec "Execution Unit" () | |
| 87 | 1 1 ; issue done | |
| 88 | () () () ()) | |
| 89 | ) | |
| 90 | ||
| 91 | ; Macros to simplify MACH attribute specification. | |
| 92 | ||
| 93 | (define-pmacro MACH2000 (MACH iq2000)) | |
| 94 | (define-pmacro MACH10 (MACH iq10)) | |
| 95 | ||
| 96 | \f | |
| 97 | ; Hardware elements. | |
| 98 | ||
| 99 | (define-hardware | |
| 100 | (name h-pc) | |
| 101 | (comment "program counter") | |
| 102 | (attrs PC PROFILE (ISA iq2000)) | |
| 103 | (type pc) | |
| 104 | (get () (c-call USI "get_h_pc")) | |
| 105 | (set (newval) (c-call VOID "set_h_pc" newval)) | |
| 106 | ) | |
| 107 | ; FIXME: it would be nice if the hardwired zero in R0 could be | |
| 108 | ; specified as a virtual hardware element, with one less register in | |
| 109 | ; the register file proper. | |
| 110 | ||
| 111 | (define-keyword | |
| 112 | (name gr-names) | |
| 113 | (print-name h-gr) | |
| 114 | (values (r0 0) (%0 0) (r1 1) (%1 1) (r2 2) (%2 2) (r3 3) (%3 3) | |
| 115 | (r4 4) (%4 4) (r5 5) (%5 5) (r6 6) (%6 6) (r7 7) (%7 7) | |
| 116 | (r8 8) (%8 8) (r9 9) (%9 9) (r10 10) (%10 10) (r11 11) (%11 11) | |
| 117 | (r12 12) (%12 12) (r13 13) (%13 13) (r14 14) (%14 14) (r15 15) (%15 15) | |
| 118 | (r16 16) (%16 16) (r17 17) (%17 17) (r18 18) (%18 18) (r19 19) (%19 19) | |
| 119 | (r20 20) (%20 20) (r21 21) (%21 21) (r22 22) (%22 22) (r23 23) (%23 23) | |
| 120 | (r24 24) (%24 24) (r25 25) (%25 25) (r26 26) (%26 26) (r27 27) (%27 27) | |
| 121 | (r28 28) (%28 28) (r29 29) (%29 29) (r30 30) (%30 30) (r31 31) (%31 31)) | |
| 122 | ) | |
| 123 | ||
| 124 | (define-hardware | |
| 125 | (name h-gr) | |
| 126 | (comment "General purpose registers") | |
| 127 | ; (attrs (ISA iq2000) CACHE-ADDR) | |
| 128 | (type register SI (32)) | |
| 129 | (indices extern-keyword gr-names) | |
| 130 | (get (idx) | |
| 131 | (cond SI | |
| 132 | ((eq idx 0) (const 0)) | |
| 133 | (else (raw-reg h-gr idx)))) | |
| 134 | (set (idx newval) | |
| 135 | (cond VOID | |
| 136 | ((eq idx 0) (nop)) | |
| 137 | (else (set (raw-reg h-gr idx) newval)))) | |
| 138 | ) | |
| 139 | ||
| 140 | \f | |
| 141 | ; Instruction fields. | |
| 142 | ||
| 143 | (dnf f-opcode "opcode field" () 31 6) | |
| 144 | (dnf f-rs "register field Rs" () 25 5) | |
| 145 | (dnf f-rt "register field Rt" () 20 5) | |
| 146 | (dnf f-rd "register field Rd" () 15 5) | |
| 147 | (dnf f-shamt "shift amount field" () 10 5) | |
| 148 | (dnf f-cp-op "coprocessor op field" () 10 3) | |
| 149 | (dnf f-cp-op-10 "coprocessor op field for CAM" () 10 5) | |
| 150 | (dnf f-cp-grp "coprocessor group field" () 7 2) | |
| 151 | (dnf f-func "function field" () 5 6) | |
| 152 | (dnf f-imm "immediate field" () 15 16) | |
| 153 | ||
| 154 | (define-multi-ifield | |
| 155 | (name f-rd-rs) | |
| 156 | (comment "register Rd implied from Rs") | |
| 157 | (attrs) | |
| 158 | (mode UINT) | |
| 159 | (subfields f-rd f-rs) | |
| 160 | (insert (sequence () | |
| 161 | (set (ifield f-rd) (ifield f-rd-rs)) | |
| 162 | (set (ifield f-rs) (ifield f-rd-rs)) | |
| 163 | )) | |
| 164 | (extract (sequence () | |
| 165 | (set (ifield f-rd-rs) (ifield f-rs)) | |
| 166 | )) | |
| 167 | ) | |
| 168 | ||
| 169 | (define-multi-ifield | |
| 170 | (name f-rd-rt) | |
| 171 | (comment "register Rd implied from Rt") | |
| 172 | (attrs) | |
| 173 | (mode UINT) | |
| 174 | (subfields f-rd f-rt) | |
| 175 | (insert (sequence () | |
| 176 | (set (ifield f-rd) (ifield f-rd-rt)) | |
| 177 | (set (ifield f-rt) (ifield f-rd-rt)) | |
| 178 | )) | |
| 179 | (extract (sequence () | |
| 180 | (set (ifield f-rd-rt) (ifield f-rt)) | |
| 181 | )) | |
| 182 | ) | |
| 183 | ||
| 184 | (define-multi-ifield | |
| 185 | (name f-rt-rs) | |
| 186 | (comment "register Rt implied from Rs") | |
| 187 | (attrs) | |
| 188 | (mode UINT) | |
| 189 | (subfields f-rt f-rs) | |
| 190 | (insert (sequence () | |
| 191 | (set (ifield f-rt) (ifield f-rt-rs)) | |
| 192 | (set (ifield f-rs) (ifield f-rt-rs)) | |
| 193 | )) | |
| 194 | (extract (sequence () | |
| 195 | (set (ifield f-rd-rs) (ifield f-rs)) | |
| 196 | )) | |
| 197 | ) | |
| 198 | ||
| 199 | (df f-jtarg "jump target field" (ABS-ADDR) 15 16 UINT | |
| 200 | ((value pc) (srl USI (and USI value #x03FFFF) 2)) | |
| 201 | ((value pc) (or USI (and USI pc #xF0000000) (sll USI value 2)))) | |
| 202 | ||
| 203 | (df f-jtargq10 "iq10 jump target field" (ABS-ADDR) 20 21 UINT | |
| 204 | ((value pc) (srl SI (and SI value #x7FFFFF) 2)) | |
| 205 | ((value pc) (or SI (and SI pc #xF0000000) (sll SI value 2)))) | |
| 206 | ||
| 207 | (df f-offset "pc offset field" (PCREL-ADDR) 15 16 INT | |
| 208 | ; Actually, this is relative to the address of the delay slot. | |
| 209 | ((value pc) (sra SI (sub SI value pc) 2)) | |
| 210 | ((value pc) (add SI (sll SI value 2) (add pc 4)))) | |
| 211 | ||
| 212 | ; Instruction fields that scarcely appear in instructions. | |
| 213 | ||
| 214 | (dnf f-count "count field" () 15 7) | |
| 215 | (dnf f-bytecount "byte count field" () 7 8) | |
| 216 | (dnf f-index "index field" () 8 9) | |
| 217 | (dnf f-mask "mask field" () 9 4) | |
| 218 | (dnf f-maskq10 "iq10 mask field" () 10 5) | |
| 219 | (dnf f-maskl "mask left field" () 4 5) | |
| 220 | (dnf f-excode "execcode field" () 25 20) | |
| 221 | (dnf f-rsrvd "reserved field" () 25 10) | |
| 222 | (dnf f-10-11 "bits 10:0" () 10 11) | |
| 223 | (dnf f-24-19 "bits 24:6" () 24 19) | |
| 224 | (dnf f-5 "bit 5" () 5 1) | |
| 225 | (dnf f-10 "bit 10" () 10 1) | |
| 226 | (dnf f-25 "bit 25" () 25 1) | |
| 227 | (dnf f-cam-z "cam global mask z" () 5 3) | |
| 228 | (dnf f-cam-y "cam operation y" () 2 3) | |
| 229 | (dnf f-cm-3func "CM 3 bit fn field" () 5 3) | |
| 230 | (dnf f-cm-4func "CM 4 bit fn field" () 5 4) | |
| 231 | (dnf f-cm-3z "CM 3Z field" () 1 2) | |
| 232 | (dnf f-cm-4z "CM 4Z field" () 2 3) | |
| 233 | ||
| 234 | \f | |
| 235 | ; Enumerations. | |
| 236 | ||
| 237 | (define-normal-insn-enum | |
| 238 | opcodes "primary opcodes" () OP_ f-opcode | |
| 239 | (("SPECIAL" 0) ("REGIMM" 1) ("J" 2) ("JAL" 3) ("BEQ" 4) ("BNE" 5) ("BLEZ" 6) ("BGTZ" 7) | |
| 240 | ("ADDI" 8) ("ADDIU" 9) ("SLTI" 10) ("SLTIU" 11) ("ANDI" 12) ("ORI" 13) ("XORI" 14) ("LUI" 15) | |
| 241 | ("COP0" 16) ("COP1" 17) ("COP2" 18) ("COP3" 19) ("BEQL" 20) ("BNEL" 21) ("BLEZL" 22) ("BGTZL" 23) | |
| 242 | ("BMB0" 24) ("BMB1" 25) ("BMB2" 26) ("BMB3" 27) ("BBI" 28) ("BBV" 29) ("BBIN" 30) ("BBVN" 31) | |
| 243 | ("LB" 32) ("LH" 33) ("LW" 35) ("LBU" 36) ("LHU" 37) ("RAM" 39) | |
| 244 | ("SB" 40) ("SH" 41) ("SW" 43) ("ANDOI" 44) ("BMB" 45) ("ORUI" 47) | |
| 245 | ("LDW" 48) | |
| 246 | ("SDW" 56) ("ANDOUI" 63)) | |
| 247 | ) | |
| 248 | ||
| 249 | (define-normal-insn-enum | |
| 250 | q10_opcodes "iq10-only primary opcodes" () OP10_ f-opcode | |
| 251 | (("BMB" 6) ("ORUI" 15) ("BMBL" 22) ("ANDOUI" 47) ("BBIL" 60) ("BBVL" 61) ("BBINL" 62) ("BBVNL" 63)) | |
| 252 | ) | |
| 253 | ||
| 254 | (define-normal-insn-enum | |
| 255 | regimm-functions "branch sub-opcodes" () FUNC_ f-rt | |
| 256 | (("BLTZ" 0) ("BGEZ" 1) ("BLTZL" 2) ("BGEZL" 3) ("BLEZ" 4) ("BGTZ" 5) ("BLEZL" 6) ("BGTZL" 7) | |
| 257 | ("BRI" 8) ("BRV" 9) ("BCTX" 12) | |
| 258 | ("BLTZAL" 16) ("BGEZAL" 17) ("BLTZALL" 18) ("BGEZALL" 19) ("BLEZAL" 20) ("BGTZAL" 21) ("BLEZALL" 22) ("BGTZALL" 23)) | |
| 259 | ) | |
| 260 | ||
| 261 | (define-normal-insn-enum | |
| 262 | functions "function sub-opcodes" () FUNC_ f-func | |
| 263 | (("SLL" 0) ("SLMV" 1) ("SRL" 2) ("SRA" 3) ("SLLV" 4) ("SRMV" 5) ("SRLV" 6) ("SRAV" 7) | |
| 264 | ("JR" 8) ("JALR" 9) ("JCR" 10) ("SYSCALL" 12) ("BREAK" 13) ("SLEEP" 14) | |
| 265 | ("ADD" 32) ("ADDU" 33) ("SUB" 34) ("SUBU" 35) ("AND" 36) ("OR" 37) ("XOR" 38) ("NOR" 39) | |
| 266 | ("ADO16" 41) ("SLT" 42) ("SLTU" 43) ("MRGB" 45)) | |
| 267 | ) | |
| 268 | ||
| 269 | ; iq10 special function sub-opcodes | |
| 270 | (define-normal-insn-enum | |
| 271 | q10s_functions "iq10-only special function sub-opcodes" () FUNC10_ f-func | |
| 272 | (("YIELD" 14) ("CNT1S" 46)) | |
| 273 | ) | |
| 274 | ||
| 275 | ; coprocessor opcodes in concert with f-cp-grp | |
| 276 | (define-normal-insn-enum | |
| 277 | cop_functions "iq10 function sub-opcodes" () FUNC10_ f-func | |
| 278 | (("CFC" 0) ("LOCK" 1) ("CTC" 2) ("UNLK" 3) ("SWRD" 4) ("SWRDL" 5) ("SWWR" 6) ("SWWRU" 7) | |
| 279 | ("RBA" 8) ("RBAL" 9) ("RBAR" 10) ("DWRD" 12) ("DWRDL" 13) | |
| 280 | ("WBA" 16) ("WBAU" 17) ("WBAC" 18) ("CRC32" 20) ("CRC32B" 21) | |
| 281 | ("MCID" 32) ("DBD" 33) ("DBA" 34) ("DPWT" 35) ("AVAIL" 36) ("FREE" 37) ("CHKHDR" 38) ("TSTOD" 39) | |
| 282 | ("PKRLA" 40) ("PKRLAU" 41) ("PKRLAH" 42) ("PKRLAC" 43) ("CMPHDR" 44) | |
| 283 | ||
| 284 | ("CM64RS" 0) ("CM64RD" 1) ("CM64RI" 4) ("CM64CLR" 5) | |
| 285 | ("CM64SS" 8) ("CM64SD" 9) ("CM64SI" 12) | |
| 286 | ("CM64RA" 16) ("CM64RIA2" 20) ("CM128RIA2" 21) | |
| 287 | ("CM64SA" 24) ("CM64SIA2" 28) ("CM128SIA2" 29) | |
| 288 | ("CM32RS" 32) ("CM32RD" 33) ("CM32XOR" 34) ("CM32ANDN" 35) ("CM32RI" 36) ("CM128VSA" 38) | |
| 289 | ("CM32SS" 40) ("CM32SD" 41) ("CM32OR" 42) ("CM32AND" 43) ("CM32SI" 44) | |
| 290 | ("CM32RA" 48) | |
| 291 | ("CM32SA" 56) ) | |
| 292 | ) | |
| 293 | ||
| 294 | ; coprocessor opcodes in concert with f-cp-grp | |
| 295 | (define-normal-insn-enum | |
| 296 | cop_cm128_4functions "iq10 function sub-opcodes" () FUNC10_ f-cm-4func | |
| 297 | (("CM128RIA3" 4) ("CM128SIA3" 6)) | |
| 298 | ) | |
| 299 | ||
| 300 | (define-normal-insn-enum | |
| 301 | cop_cm128_3functions "iq10 function sub-opcodes" () FUNC10_ f-cm-3func | |
| 302 | (("CM128RIA4" 6) ("CM128SIA4" 7)) | |
| 303 | ) | |
| 304 | ||
| 305 | (define-normal-insn-enum | |
| 306 | cop2_functions "iq10 coprocessor sub-opcodes" () FUNC10_ f-cp-op | |
| 307 | (("PKRLI" 0) ("PKRLIU" 1) ("PKRLIH" 2) ("PKRLIC" 3) ("RBIR" 1) ("RBI" 2) ("RBIL" 3) ("WBIC" 5) ("WBI" 6) ("WBIU" 7)) | |
| 308 | ) | |
| 309 | ||
| 310 | (define-normal-insn-enum | |
| 311 | cop3_cam_functions "iq10 coprocessor cam sub-opcodes" () FUNC10_ f-cp-op-10 | |
| 312 | (("CAM36" 16) ("CAM72" 17) ("CAM144" 18) ("CAM288" 19)) | |
| 313 | ) | |
| 314 | ||
| 315 | \f | |
| 316 | ; Attributes. | |
| 317 | ||
| 318 | (define-attr | |
| 319 | (for insn) | |
| 320 | (type boolean) | |
| 321 | (name YIELD-INSN) | |
| 322 | (comment "insn generates a context yield") | |
| 323 | ) | |
| 324 | ||
| 325 | (define-attr | |
| 326 | (for insn) | |
| 327 | (type boolean) | |
| 328 | (name LOAD-DELAY) | |
| 329 | (comment "insn has a load delay") | |
| 330 | ) | |
| 331 | ||
| 332 | (define-attr | |
| 333 | (for insn) | |
| 334 | (type boolean) | |
| 335 | (name EVEN-REG-NUM) | |
| 336 | (comment "insn requires an even numbered register in rt(2000) or rd(10)") | |
| 337 | ) | |
| 338 | ||
| 339 | (define-attr | |
| 340 | (for insn) | |
| 341 | (type boolean) | |
| 342 | (name UNSUPPORTED) | |
| 343 | (comment "insn is unsupported") | |
| 344 | ) | |
| 345 | ||
| 346 | (define-pmacro (define-reg-use-attr regfield) | |
| 347 | (define-attr | |
| 348 | (for insn) | |
| 349 | (type boolean) | |
| 350 | (name (.sym USES- (.upcase regfield))) | |
| 351 | (comment ("insn accesses register operand " regfield)))) | |
| 352 | ||
| 4bd1d37b NC |
353 | (define-reg-use-attr "rd") |
| 354 | (define-reg-use-attr "rs") | |
| 355 | (define-reg-use-attr "rt") | |
| 356 | (define-reg-use-attr "r31") | |
| 539ee71a AC |
357 | |
| 358 | \f | |
| 359 | ; Operands. | |
| 360 | ||
| 361 | (dnop rs "register Rs" () h-gr f-rs) | |
| 362 | (dnop rt "register Rt" () h-gr f-rt) | |
| 363 | (dnop rd "register Rd" () h-gr f-rd) | |
| 364 | (dnop rd-rs "register Rd from Rs" () h-gr f-rd-rs) | |
| 365 | (dnop rd-rt "register Rd from Rt" () h-gr f-rd-rt) | |
| 366 | (dnop rt-rs "register Rt from Rs" () h-gr f-rt-rs) | |
| 367 | (dnop shamt "shift amount" () h-uint f-shamt) | |
| 368 | (define-operand (name imm) (comment "immediate") (attrs) | |
| 369 | (type h-uint) (index f-imm) (handlers (parse "imm"))) | |
| 370 | (dnop offset "pc-relative offset" () h-iaddr f-offset) | |
| 371 | (dnop baseoff "base register offset" () h-iaddr f-imm) | |
| 372 | (dnop jmptarg "jump target" () h-iaddr f-jtarg) | |
| 373 | (dnop mask "mask" () h-uint f-mask) | |
| 374 | (dnop maskq10 "iq10 mask" () h-uint f-maskq10) | |
| 375 | (dnop maskl "mask left" () h-uint f-maskl) | |
| 376 | (dnop count "count" () h-uint f-count) | |
| 4030fa5a | 377 | (dnop _index "index" () h-uint f-index) |
| 539ee71a AC |
378 | (dnop execode "execcode" () h-uint f-excode) |
| 379 | (dnop bytecount "byte count" () h-uint f-bytecount) | |
| 380 | (dnop cam-y "cam global opn y" () h-uint f-cam-y) | |
| 381 | (dnop cam-z "cam global mask z" () h-uint f-cam-z) | |
| 382 | (dnop cm-3func "CM 3 bit fn field" () h-uint f-cm-3func) | |
| 383 | (dnop cm-4func "CM 4 bit fn field" () h-uint f-cm-4func) | |
| 384 | (dnop cm-3z "CM 3 bit Z field" () h-uint f-cm-3z) | |
| 385 | (dnop cm-4z "CM 4 bit Z field" () h-uint f-cm-4z) | |
| 386 | ||
| 387 | ; Aliases for the rs and rt operands. This just makes the load/store | |
| 388 | ; insns easier to compare with the instruction set documentation. | |
| 389 | ||
| 390 | (dnop base "base register" () h-gr f-rs) | |
| 391 | (dnop maskr "mask right" () h-uint f-rs) | |
| 392 | (dnop bitnum "bit number" () h-uint f-rt) | |
| 393 | ||
| 394 | ; For high(foo). | |
| 395 | (define-operand | |
| 396 | (name hi16) | |
| 397 | (comment "high 16 bit immediate") | |
| 398 | (attrs) | |
| 399 | (type h-uint) | |
| 400 | (index f-imm) | |
| 401 | (handlers (parse "hi16")) | |
| 402 | ) | |
| 403 | ||
| 404 | ; For low(foo). | |
| 405 | (define-operand | |
| 406 | (name lo16) | |
| 407 | (comment "16 bit signed immediate, for low") | |
| 408 | (attrs) | |
| 409 | (type h-uint) | |
| 410 | (index f-imm) | |
| 411 | (handlers (parse "lo16")) | |
| 412 | ) | |
| 413 | ||
| 414 | ; For negated imm. | |
| 415 | (define-operand | |
| 416 | (name mlo16) | |
| 417 | (comment "negated 16 bit signed immediate") | |
| 418 | (attrs) | |
| 419 | (type h-uint) | |
| 420 | (index f-imm) | |
| 421 | (handlers (parse "mlo16")) | |
| 422 | ) | |
| 423 | ||
| 424 | ; For iq10 jmps | |
| 425 | ; In the future, we'll want the j & jal to use the 21 bit target, with | |
| 426 | ; the upper five bits shifted up. For now, don't use this. | |
| 427 | (define-operand | |
| 428 | (name jmptargq10) | |
| 429 | (comment "iq10 21-bit jump offset") | |
| 430 | (attrs) | |
| 431 | (type h-iaddr) | |
| 432 | (index f-jtargq10) | |
| 433 | (handlers (parse "jtargq10")) | |
| 434 | ) | |
| 435 | ||
| 436 | \f | |
| 437 | ; Instructions. | |
| 438 | ||
| 439 | ; A pmacro for use in semantic bodies of unimplemented insns. | |
| 440 | (define-pmacro (unimp mnemonic) (nop)) | |
| 441 | ||
| 442 | (define-pmacro (bitset? value bit-num) | |
| 443 | (and value (sll 1 bit-num))) | |
| 444 | ||
| 445 | (define-pmacro (bitclear? value bit-num) | |
| 446 | (not (bitset? value bit-num))) | |
| 447 | ||
| 448 | ; Arithmetic/logic instructions. | |
| 449 | ||
| 450 | (dni add2 "add registers" (ALIAS NO-DIS USES-RD USES-RS USES-RT) | |
| 451 | "add ${rd-rs},$rt" | |
| 452 | (+ OP_SPECIAL rt rd-rs (f-shamt 0) FUNC_ADD) | |
| 453 | (set rd-rs (add rt rd-rs)) | |
| 454 | ()) | |
| 455 | ||
| 456 | (dni add "add registers" (USES-RD USES-RS USES-RT) | |
| 457 | "add $rd,$rs,$rt" | |
| 458 | (+ OP_SPECIAL rs rt rd (f-shamt 0) FUNC_ADD) | |
| 459 | (set rd (add rs rt)) | |
| 460 | ()) | |
| 461 | ||
| 462 | ||
| 463 | (dni addi2 "add immediate" (ALIAS NO-DIS USES-RS USES-RT) | |
| 464 | "addi ${rt-rs},$lo16" | |
| 465 | (+ OP_ADDI rt-rs lo16) | |
| 466 | (set rt-rs (add rt-rs (ext SI (trunc HI lo16)))) | |
| 467 | ()) | |
| 468 | ||
| 469 | (dni addi "add immediate" (USES-RS USES-RT) | |
| 470 | "addi $rt,$rs,$lo16" | |
| 471 | (+ OP_ADDI rs rt lo16) | |
| 472 | (set rt (add rs (ext SI (trunc HI lo16)))) | |
| 473 | ()) | |
| 474 | ||
| 475 | (dni addiu2 "add immediate unsigned" (ALIAS NO-DIS USES-RS USES-RT) | |
| 476 | "addiu ${rt-rs},$lo16" | |
| 477 | (+ OP_ADDIU rt-rs lo16) | |
| 478 | (set rt-rs (add rt-rs (ext SI (trunc HI lo16)))) | |
| 479 | ()) | |
| 480 | ||
| 481 | (dni addiu "add immediate unsigned" (USES-RS USES-RT) | |
| 482 | "addiu $rt,$rs,$lo16" | |
| 483 | (+ OP_ADDIU rs rt lo16) | |
| 484 | (set rt (add rs (ext SI (trunc HI lo16)))) | |
| 485 | ()) | |
| 486 | ||
| 487 | (dni addu2 "add unsigned" (ALIAS NO-DIS USES-RD USES-RS USES-RT) | |
| 488 | "addu ${rd-rs},$rt" | |
| 489 | (+ OP_SPECIAL rd-rs rt (f-shamt 0) FUNC_ADDU) | |
| 490 | (set rd-rs (add rd-rs rt)) | |
| 491 | ()) | |
| 492 | ||
| 493 | (dni addu "add unsigned" (USES-RD USES-RS USES-RT) | |
| 494 | "addu $rd,$rs,$rt" | |
| 495 | (+ OP_SPECIAL rs rt rd (f-shamt 0) FUNC_ADDU) | |
| 496 | (set rd (add rs rt)) | |
| 497 | ()) | |
| 498 | ||
| 499 | (dni ado162 "add 16, ones complement" (ALIAS NO-DIS USES-RD USES-RS USES-RT) | |
| 500 | "ado16 ${rd-rs},$rt" | |
| 501 | (+ OP_SPECIAL rd-rs rt (f-shamt 0) FUNC_ADO16) | |
| 502 | (sequence ((HI high) (HI low)) | |
| 503 | (set low (add HI (and HI rd-rs #xFFFF) (and HI rt #xFFFF))) | |
| 504 | (set high (add HI (srl rd-rs 16) (srl rt 16))) | |
| 505 | (set rd-rs (or SI (sll SI high 16) low))) | |
| 506 | ()) | |
| 507 | ||
| 508 | (dni ado16 "add 16, ones complement" (USES-RD USES-RS USES-RT) | |
| 509 | "ado16 $rd,$rs,$rt" | |
| 510 | (+ OP_SPECIAL rs rt rd (f-shamt 0) FUNC_ADO16) | |
| 511 | (sequence ((HI high) (HI low)) | |
| 512 | (set low (add HI (and HI rs #xFFFF) (and HI rt #xFFFF))) | |
| 513 | (set high (add HI (srl rs 16) (srl rt 16))) | |
| 514 | (set rd (or SI (sll SI high 16) low))) | |
| 515 | ()) | |
| 516 | ||
| 517 | (dni and2 "and register" (ALIAS NO-DIS USES-RD USES-RS USES-RT) | |
| 518 | "and ${rd-rs},$rt" | |
| 519 | (+ OP_SPECIAL rd-rs rt (f-shamt 0) FUNC_AND) | |
| 520 | (set rd-rs (and rd-rs rt)) | |
| 521 | ()) | |
| 522 | ||
| 523 | (dni and "and register" (USES-RD USES-RS USES-RT) | |
| 524 | "and $rd,$rs,$rt" | |
| 525 | (+ OP_SPECIAL rs rt rd (f-shamt 0) FUNC_AND) | |
| 526 | (set rd (and rs rt)) | |
| 527 | ()) | |
| 528 | ||
| 529 | (dni andi2 "and immediate" (ALIAS NO-DIS USES-RS USES-RT) | |
| 530 | "andi ${rt-rs},$lo16" | |
| 531 | (+ OP_ANDI rt-rs lo16) | |
| 532 | (set rt-rs (and rt-rs (zext SI lo16))) | |
| 533 | ()) | |
| 534 | ||
| 535 | (dni andi "and immediate" (USES-RS USES-RT) | |
| 536 | "andi $rt,$rs,$lo16" | |
| 537 | (+ OP_ANDI rs rt lo16) | |
| 538 | (set rt (and rs (zext SI lo16))) | |
| 539 | ()) | |
| 540 | ||
| 541 | (dni andoi2 "and ones immediate" (ALIAS NO-DIS USES-RS USES-RT) | |
| 542 | "andoi ${rt-rs},$lo16" | |
| 543 | (+ OP_ANDOI rt-rs lo16) | |
| 544 | (set rt-rs (and rt-rs (or #xFFFF0000 (ext SI (trunc HI lo16))))) | |
| 545 | ()) | |
| 546 | ||
| 547 | (dni andoi "and ones immediate" (USES-RS USES-RT) | |
| 548 | "andoi $rt,$rs,$lo16" | |
| 549 | (+ OP_ANDOI rs rt lo16) | |
| 550 | (set rt (and rs (or #xFFFF0000 (ext SI (trunc HI lo16))))) | |
| 551 | ()) | |
| 552 | ||
| 553 | (dni nor2 "nor" (ALIAS NO-DIS USES-RD USES-RS USES-RT) | |
| 554 | "nor ${rd-rs},$rt" | |
| 555 | (+ OP_SPECIAL rd-rs rt (f-shamt 0) FUNC_NOR) | |
| 556 | (set rd-rs (inv (or rd-rs rt))) | |
| 557 | ()) | |
| 558 | ||
| 559 | (dni nor "nor" (USES-RD USES-RS USES-RT) | |
| 560 | "nor $rd,$rs,$rt" | |
| 561 | (+ OP_SPECIAL rs rt rd (f-shamt 0) FUNC_NOR) | |
| 562 | (set rd (inv (or rs rt))) | |
| 563 | ()) | |
| 564 | ||
| 565 | (dni or2 "or" (ALIAS NO-DIS USES-RD USES-RS USES-RT) | |
| 566 | "or ${rd-rs},$rt" | |
| 567 | (+ OP_SPECIAL rd-rs rt (f-shamt 0) FUNC_OR) | |
| 568 | (set rd-rs (or rd-rs rt)) | |
| 569 | ()) | |
| 570 | ||
| 571 | (dni or "or" (USES-RD USES-RS USES-RT) | |
| 572 | "or $rd,$rs,$rt" | |
| 573 | (+ OP_SPECIAL rs rt rd (f-shamt 0) FUNC_OR) | |
| 574 | (set rd (or rs rt)) | |
| 575 | ()) | |
| 576 | ||
| 577 | (dni ori2 "or immediate" (ALIAS NO-DIS USES-RS USES-RT) | |
| 578 | "ori ${rt-rs},$lo16" | |
| 579 | (+ OP_ORI rt-rs lo16) | |
| 580 | (set rt-rs (or rt-rs (zext SI lo16))) | |
| 581 | ()) | |
| 582 | ||
| 583 | (dni ori "or immediate" (USES-RS USES-RT) | |
| 584 | "ori $rt,$rs,$lo16" | |
| 585 | (+ OP_ORI rs rt lo16) | |
| 586 | (set rt (or rs (zext SI lo16))) | |
| 587 | ()) | |
| 588 | ||
| 589 | (dni ram "rotate and mask" (USES-RD USES-RT) | |
| 590 | "ram $rd,$rt,$shamt,$maskl,$maskr" | |
| 591 | (+ OP_RAM maskr rt rd shamt (f-5 0) maskl) | |
| 592 | (sequence () | |
| 593 | (set rd (ror rt shamt)) | |
| 594 | (set rd (and rd (srl #xFFFFFFFF maskl))) | |
| 595 | (set rd (and rd (sll #xFFFFFFFF maskr)))) | |
| 596 | ()) | |
| 597 | ||
| 598 | (dni sll "shift left logical" (USES-RD USES-RT) | |
| 599 | "sll $rd,$rt,$shamt" | |
| 600 | (+ OP_SPECIAL (f-rs 0) rt rd shamt (f-func 0)) | |
| 601 | (set rd (sll rt shamt)) | |
| 602 | ()) | |
| 603 | ||
| 604 | (dni sllv2 "shift left logical variable" (ALIAS NO-DIS USES-RD USES-RS USES-RT) | |
| 605 | "sllv ${rd-rt},$rs" | |
| 606 | (+ OP_SPECIAL rs rd-rt (f-shamt 0) FUNC_SLLV) | |
| 607 | (set rd-rt (sll rd-rt (and rs #x1F))) | |
| 608 | ()) | |
| 609 | ||
| 610 | (dni sllv "shift left logical variable" (USES-RD USES-RS USES-RT) | |
| 611 | "sllv $rd,$rt,$rs" | |
| 612 | (+ OP_SPECIAL rs rt rd (f-shamt 0) FUNC_SLLV) | |
| 613 | (set rd (sll rt (and rs #x1F))) | |
| 614 | ()) | |
| 615 | ||
| 616 | (dni slmv2 "shift left and mask variable" (ALIAS NO-DIS USES-RD USES-RS USES-RT) | |
| 617 | "slmv ${rd-rt},$rs,$shamt" | |
| 618 | (+ OP_SPECIAL rs rd-rt shamt FUNC_SLMV) | |
| 619 | (set rd-rt (and (sll rd-rt shamt) (srl #xFFFFFFFF rs))) | |
| 620 | ()) | |
| 621 | ||
| 622 | (dni slmv "shift left and mask variable" (USES-RD USES-RS USES-RT) | |
| 623 | "slmv $rd,$rt,$rs,$shamt" | |
| 624 | (+ OP_SPECIAL rs rt rd shamt FUNC_SLMV) | |
| 625 | (set rd (and (sll rt shamt) (srl #xFFFFFFFF rs))) | |
| 626 | ()) | |
| 627 | ||
| 628 | (dni slt2 "set if less than" (ALIAS NO-DIS USES-RD USES-RS USES-RT) | |
| 629 | "slt ${rd-rs},$rt" | |
| 630 | (+ OP_SPECIAL rt rd-rs (f-shamt 0) FUNC_SLT) | |
| 631 | (if (lt rd-rs rt) | |
| 632 | (set rd-rs 1) | |
| 633 | (set rd-rs 0)) | |
| 634 | ()) | |
| 635 | ||
| 636 | (dni slt "set if less than" (USES-RD USES-RS USES-RT) | |
| 637 | "slt $rd,$rs,$rt" | |
| 638 | (+ OP_SPECIAL rs rt rd (f-shamt 0) FUNC_SLT) | |
| 639 | (if (lt rs rt) | |
| 640 | (set rd 1) | |
| 641 | (set rd 0)) | |
| 642 | ()) | |
| 643 | ||
| 644 | (dni slti2 "set if less than immediate" (ALIAS NO-DIS USES-RS USES-RT) | |
| 645 | "slti ${rt-rs},$imm" | |
| 646 | (+ OP_SLTI rt-rs imm) | |
| 647 | (if (lt rt-rs (ext SI (trunc HI imm))) | |
| 648 | (set rt-rs 1) | |
| 649 | (set rt-rs 0)) | |
| 650 | ()) | |
| 651 | ||
| 652 | (dni slti "set if less than immediate" (USES-RS USES-RT) | |
| 653 | "slti $rt,$rs,$imm" | |
| 654 | (+ OP_SLTI rs rt imm) | |
| 655 | (if (lt rs (ext SI (trunc HI imm))) | |
| 656 | (set rt 1) | |
| 657 | (set rt 0)) | |
| 658 | ()) | |
| 659 | ||
| 660 | (dni sltiu2 "set if less than immediate unsigned" (ALIAS NO-DIS USES-RS USES-RT) | |
| 661 | "sltiu ${rt-rs},$imm" | |
| 662 | (+ OP_SLTIU rt-rs imm) | |
| 663 | (if (ltu rt-rs (ext SI (trunc HI imm))) | |
| 664 | (set rt-rs 1) | |
| 665 | (set rt-rs 0)) | |
| 666 | ()) | |
| 667 | ||
| 668 | (dni sltiu "set if less than immediate unsigned" (USES-RS USES-RT) | |
| 669 | "sltiu $rt,$rs,$imm" | |
| 670 | (+ OP_SLTIU rs rt imm) | |
| 671 | (if (ltu rs (ext SI (trunc HI imm))) | |
| 672 | (set rt 1) | |
| 673 | (set rt 0)) | |
| 674 | ()) | |
| 675 | ||
| 676 | (dni sltu2 "set if less than unsigned" (ALIAS NO-DIS USES-RD USES-RS USES-RT) | |
| 677 | "sltu ${rd-rs},$rt" | |
| 678 | (+ OP_SPECIAL rd-rs rt (f-shamt 0) FUNC_SLTU) | |
| 679 | (if (ltu rd-rs rt) | |
| 680 | (set rd-rs 1) | |
| 681 | (set rd-rs 0)) | |
| 682 | ()) | |
| 683 | ||
| 684 | (dni sltu "set if less than unsigned" (USES-RD USES-RS USES-RT) | |
| 685 | "sltu $rd,$rs,$rt" | |
| 686 | (+ OP_SPECIAL rs rt rd (f-shamt 0) FUNC_SLTU) | |
| 687 | (if (ltu rs rt) | |
| 688 | (set rd 1) | |
| 689 | (set rd 0)) | |
| 690 | ()) | |
| 691 | ||
| 692 | (dni sra2 "shift right arithmetic" (ALIAS NO-DIS USES-RD USES-RT) | |
| 693 | "sra ${rd-rt},$shamt" | |
| 694 | (+ OP_SPECIAL (f-rs 0) rd-rt shamt FUNC_SRA) | |
| 695 | (set rd-rt (sra rd-rt shamt)) | |
| 696 | ()) | |
| 697 | ||
| 698 | (dni sra "shift right arithmetic" (USES-RD USES-RT) | |
| 699 | "sra $rd,$rt,$shamt" | |
| 700 | (+ OP_SPECIAL (f-rs 0) rt rd shamt FUNC_SRA) | |
| 701 | (set rd (sra rt shamt)) | |
| 702 | ()) | |
| 703 | ||
| 704 | (dni srav2 "shift right arithmetic variable" (ALIAS NO-DIS USES-RD USES-RS USES-RT) | |
| 705 | "srav ${rd-rt},$rs" | |
| 706 | (+ OP_SPECIAL rs rd-rt (f-shamt 0) FUNC_SRAV) | |
| 707 | (set rd-rt (sra rd-rt (and rs #x1F))) | |
| 708 | ()) | |
| 709 | ||
| 710 | (dni srav "shift right arithmetic variable" (USES-RD USES-RS USES-RT) | |
| 711 | "srav $rd,$rt,$rs" | |
| 712 | (+ OP_SPECIAL rs rt rd (f-shamt 0) FUNC_SRAV) | |
| 713 | (set rd (sra rt (and rs #x1F))) | |
| 714 | ()) | |
| 715 | ||
| 716 | (dni srl "shift right logical" (USES-RD USES-RT) | |
| 717 | "srl $rd,$rt,$shamt" | |
| 718 | (+ OP_SPECIAL (f-rs 0) rt rd shamt FUNC_SRL) | |
| 719 | (set rd (srl rt shamt)) | |
| 720 | ()) | |
| 721 | ||
| 722 | (dni srlv2 "shift right logical variable" (ALIAS NO-DIS USES-RD USES-RS USES-RT) | |
| 723 | "srlv ${rd-rt},$rs" | |
| 724 | (+ OP_SPECIAL rs rd-rt (f-shamt 0) FUNC_SRLV) | |
| 725 | (set rd-rt (srl rd-rt (and rs #x1F))) | |
| 726 | ()) | |
| 727 | ||
| 728 | (dni srlv "shift right logical variable" (USES-RD USES-RS USES-RT) | |
| 729 | "srlv $rd,$rt,$rs" | |
| 730 | (+ OP_SPECIAL rs rt rd (f-shamt 0) FUNC_SRLV) | |
| 731 | (set rd (srl rt (and rs #x1F))) | |
| 732 | ()) | |
| 733 | ||
| 734 | (dni srmv2 "shift right and mask variable" (ALIAS NO-DIS USES-RD USES-RS USES-RT) | |
| 735 | "srmv ${rd-rt},$rs,$shamt" | |
| 736 | (+ OP_SPECIAL rs rd-rt shamt FUNC_SRMV) | |
| 737 | (set rd-rt (and (srl rd-rt shamt) (sll #xFFFFFFFF rs))) | |
| 738 | ()) | |
| 739 | ||
| 740 | (dni srmv "shift right and mask variable" (USES-RD USES-RS USES-RT) | |
| 741 | "srmv $rd,$rt,$rs,$shamt" | |
| 742 | (+ OP_SPECIAL rs rt rd shamt FUNC_SRMV) | |
| 743 | (set rd (and (srl rt shamt) (sll #xFFFFFFFF rs))) | |
| 744 | ()) | |
| 745 | ||
| 746 | (dni sub2 "subtract" (ALIAS NO-DIS USES-RD USES-RS USES-RT) | |
| 747 | "sub ${rd-rs},$rt" | |
| 748 | (+ OP_SPECIAL rt rd-rs (f-shamt 0) FUNC_SUB) | |
| 749 | (set rd-rs (sub rd-rs rt)) | |
| 750 | ()) | |
| 751 | ||
| 752 | (dni sub "subtract" (USES-RD USES-RS USES-RT) | |
| 753 | "sub $rd,$rs,$rt" | |
| 754 | (+ OP_SPECIAL rs rt rd (f-shamt 0) FUNC_SUB) | |
| 755 | (set rd (sub rs rt)) | |
| 756 | ()) | |
| 757 | ||
| 758 | (dni subu2 "subtract unsigned" (ALIAS NO-DIS USES-RD USES-RS USES-RT) | |
| 759 | "subu ${rd-rs},$rt" | |
| 760 | (+ OP_SPECIAL rt rd-rs (f-shamt 0) FUNC_SUBU) | |
| 761 | (set rd-rs (sub rd-rs rt)) | |
| 762 | ()) | |
| 763 | ||
| 764 | (dni subu "subtract unsigned" (USES-RD USES-RS USES-RT) | |
| 765 | "subu $rd,$rs,$rt" | |
| 766 | (+ OP_SPECIAL rs rt rd (f-shamt 0) FUNC_SUBU) | |
| 767 | (set rd (sub rs rt)) | |
| 768 | ()) | |
| 769 | ||
| 770 | (dni xor2 "exclusive or" (ALIAS NO-DIS USES-RD USES-RS USES-RT) | |
| 771 | "xor ${rd-rs},$rt" | |
| 772 | (+ OP_SPECIAL rt rd-rs (f-shamt 0) FUNC_XOR) | |
| 773 | (set rd-rs (xor rd-rs rt)) | |
| 774 | ()) | |
| 775 | ||
| 776 | (dni xor "exclusive or" (USES-RD USES-RS USES-RT) | |
| 777 | "xor $rd,$rs,$rt" | |
| 778 | (+ OP_SPECIAL rs rt rd (f-shamt 0) FUNC_XOR) | |
| 779 | (set rd (xor rs rt)) | |
| 780 | ()) | |
| 781 | ||
| 782 | (dni xori2 "exclusive or immediate" (ALIAS NO-DIS USES-RS USES-RT) | |
| 783 | "xori ${rt-rs},$lo16" | |
| 784 | (+ OP_XORI rt-rs lo16) | |
| 785 | (set rt-rs (xor rt-rs (zext SI lo16))) | |
| 786 | ()) | |
| 787 | ||
| 788 | (dni xori "exclusive or immediate" (USES-RS USES-RT) | |
| 789 | "xori $rt,$rs,$lo16" | |
| 790 | (+ OP_XORI rs rt lo16) | |
| 791 | (set rt (xor rs (zext SI lo16))) | |
| 792 | ()) | |
| 793 | ||
| 794 | \f | |
| 795 | ; Branch instructions. | |
| 796 | ||
| 797 | (dni bbi "branch bit immediate" (USES-RS) | |
| 798 | "bbi $rs($bitnum),$offset" | |
| 799 | (+ OP_BBI rs bitnum offset) | |
| 800 | (if (bitset? rs bitnum) | |
| 801 | (delay 1 (set pc offset))) | |
| 802 | ()) | |
| 803 | ||
| 804 | (dni bbin "branch bit immediate negated" (USES-RS) | |
| 805 | "bbin $rs($bitnum),$offset" | |
| 806 | (+ OP_BBIN rs bitnum offset) | |
| 807 | (if (bitclear? rs bitnum) | |
| 808 | (delay 1 (set pc offset))) | |
| 809 | ()) | |
| 810 | ||
| 811 | (dni bbv "branch bit variable" (USES-RS USES-RT) | |
| 812 | "bbv $rs,$rt,$offset" | |
| 813 | (+ OP_BBV rs rt offset) | |
| 814 | (if (bitset? rs (and rt #x1F)) | |
| 815 | (delay 1 (set pc offset))) | |
| 816 | ()) | |
| 817 | ||
| 818 | (dni bbvn "branch bit variable negated" (USES-RS USES-RT) | |
| 819 | "bbvn $rs,$rt,$offset" | |
| 820 | (+ OP_BBVN rs rt offset) | |
| 821 | (if (bitclear? rs (and rt #x1F)) | |
| 822 | (delay 1 (set pc offset))) | |
| 823 | ()) | |
| 824 | ||
| 825 | (dni beq "branch if equal" (USES-RS USES-RT) | |
| 826 | "beq $rs,$rt,$offset" | |
| 827 | (+ OP_BEQ rs rt offset) | |
| 828 | (if (eq rs rt) | |
| 829 | (delay 1 (set pc offset))) | |
| 830 | ()) | |
| 831 | ||
| 832 | (dni beql "branch if equal likely" (USES-RS USES-RT) | |
| 833 | "beql $rs,$rt,$offset" | |
| 834 | (+ OP_BEQL rs rt offset) | |
| 835 | (if (eq rs rt) | |
| 836 | (delay 1 (set pc offset)) | |
| 837 | (skip 1)) | |
| 838 | ()) | |
| 839 | ||
| 840 | (dni bgez "branch if greater than or equal to zero" (USES-RS) | |
| 841 | "bgez $rs,$offset" | |
| 842 | (+ OP_REGIMM rs FUNC_BGEZ offset) | |
| 843 | (if (ge rs 0) | |
| 844 | (delay 1 (set pc offset))) | |
| 845 | ()) | |
| 846 | ||
| 847 | (dni bgezal "branch if greater than or equal to zero and link" (USES-RS USES-R31) | |
| 848 | "bgezal $rs,$offset" | |
| 849 | (+ OP_REGIMM rs FUNC_BGEZAL offset) | |
| 850 | (if (ge rs 0) | |
| 851 | (sequence () | |
| 852 | (set (reg h-gr 31) (add pc 8)) | |
| 853 | (delay 1 (set pc offset)))) | |
| 854 | ()) | |
| 855 | ||
| 856 | (dni bgezall | |
| 857 | "branch if greater than equal to zero and link likely" (USES-RS USES-R31) | |
| 858 | "bgezall $rs,$offset" | |
| 859 | (+ OP_REGIMM rs FUNC_BGEZALL offset) | |
| 860 | (if (ge rs 0) | |
| 861 | (sequence () | |
| 862 | (set (reg h-gr 31) (add pc 8)) | |
| 863 | (delay 1 (set pc offset))) | |
| 864 | (skip 1)) | |
| 865 | ()) | |
| 866 | ||
| 867 | (dni bgezl "branch if greater or equal to zero likely" (USES-RS) | |
| 868 | "bgezl $rs,$offset" | |
| 869 | (+ OP_REGIMM rs FUNC_BGEZL offset) | |
| 870 | (if (ge rs 0) | |
| 871 | (delay 1 (set pc offset)) | |
| 872 | (skip 1)) | |
| 873 | ()) | |
| 874 | ||
| 875 | (dni bltz "branch if less than zero" (USES-RS) | |
| 876 | "bltz $rs,$offset" | |
| 877 | (+ OP_REGIMM rs FUNC_BLTZ offset) | |
| 878 | (if (lt rs 0) | |
| 879 | (delay 1 (set pc offset))) | |
| 880 | ()) | |
| 881 | ||
| 882 | (dni bltzl "branch if less than zero likely" (USES-RS) | |
| 883 | "bltzl $rs,$offset" | |
| 884 | (+ OP_REGIMM rs FUNC_BLTZL offset) | |
| 885 | (if (lt rs 0) | |
| 886 | (delay 1 (set pc offset)) | |
| 887 | (skip 1)) | |
| 888 | ()) | |
| 889 | ||
| 890 | (dni bltzal "branch if less than zero and link" (USES-RS USES-R31) | |
| 891 | "bltzal $rs,$offset" | |
| 892 | (+ OP_REGIMM rs FUNC_BLTZAL offset) | |
| 893 | (if (lt rs 0) | |
| 894 | (sequence () | |
| 895 | (set (reg h-gr 31) (add pc 8)) | |
| 896 | (delay 1 (set pc offset)))) | |
| 897 | ()) | |
| 898 | ||
| 899 | (dni bltzall "branch if less than zero and link likely" (USES-RS USES-R31) | |
| 900 | "bltzall $rs,$offset" | |
| 901 | (+ OP_REGIMM rs FUNC_BLTZALL offset) | |
| 902 | (if (lt rs 0) | |
| 903 | (sequence () | |
| 904 | (set (reg h-gr 31) (add pc 8)) | |
| 905 | (delay 1 (set pc offset))) | |
| 906 | (skip 1)) | |
| 907 | ()) | |
| 908 | ||
| 909 | (dni bmb0 "branch if matching byte-lane 0" (USES-RS USES-RT) | |
| 910 | "bmb0 $rs,$rt,$offset" | |
| 911 | (+ OP_BMB0 rs rt offset) | |
| 912 | (if (eq (and rs #xFF) (and rt #xFF)) | |
| 913 | (delay 1 (set pc offset))) | |
| 914 | ()) | |
| 915 | ||
| 916 | (dni bmb1 "branch if matching byte-lane 1" (USES-RS USES-RT) | |
| 917 | "bmb1 $rs,$rt,$offset" | |
| 918 | (+ OP_BMB1 rs rt offset) | |
| 919 | (if (eq (and rs #xFF00) (and rt #xFF00)) | |
| 920 | (delay 1 (set pc offset))) | |
| 921 | ()) | |
| 922 | ||
| 923 | (dni bmb2 "branch if matching byte-lane 2" (USES-RS USES-RT) | |
| 924 | "bmb2 $rs,$rt,$offset" | |
| 925 | (+ OP_BMB2 rs rt offset) | |
| 926 | (if (eq (and rs #xFF0000) (and rt #xFF0000)) | |
| 927 | (delay 1 (set pc offset))) | |
| 928 | ()) | |
| 929 | ||
| 930 | (dni bmb3 "branch if matching byte-lane 3" (USES-RS USES-RT) | |
| 931 | "bmb3 $rs,$rt,$offset" | |
| 932 | (+ OP_BMB3 rs rt offset) | |
| 933 | (if (eq (and rs #xFF000000) (and rt #xFF000000)) | |
| 934 | (delay 1 (set pc offset))) | |
| 935 | ()) | |
| 936 | ||
| 937 | (dni bne "branch if not equal" (USES-RS USES-RT) | |
| 938 | "bne $rs,$rt,$offset" | |
| 939 | (+ OP_BNE rs rt offset) | |
| 940 | (if (ne rs rt) | |
| 941 | (delay 1 (set pc offset))) | |
| 942 | ()) | |
| 943 | ||
| 944 | (dni bnel "branch if not equal likely" (USES-RS USES-RT) | |
| 945 | "bnel $rs,$rt,$offset" | |
| 946 | (+ OP_BNEL rs rt offset) | |
| 947 | (if (ne rs rt) | |
| 948 | (delay 1 (set pc offset)) | |
| 949 | (skip 1)) | |
| 950 | ()) | |
| 951 | ||
| 952 | \f | |
| 953 | ||
| 954 | \f | |
| 955 | ; Jump instructions. | |
| 956 | ; Might as well jump! | |
| 957 | ||
| 958 | (dni jalr "jump and link register" (USES-RD USES-RS) | |
| 959 | "jalr $rd,$rs" | |
| 960 | (+ OP_SPECIAL rs (f-rt 0) rd (f-shamt 0) FUNC_JALR) | |
| 961 | (delay 1 | |
| 962 | (sequence () | |
| 963 | (set rd (add pc 8)) | |
| 964 | (set pc rs))) | |
| 965 | ()) | |
| 966 | ||
| 967 | (dni jr "jump register" (USES-RS) | |
| 968 | "jr $rs" | |
| 969 | (+ OP_SPECIAL rs (f-rt 0) (f-rd 0) (f-shamt 0) FUNC_JR) | |
| 970 | (delay 1 (set pc rs)) | |
| 971 | ()) | |
| 972 | ||
| 973 | \f | |
| 974 | ; Load instructions. | |
| 975 | ||
| 976 | (dni lb "load byte" (LOAD-DELAY USES-RS USES-RT) | |
| 977 | "lb $rt,$lo16($base)" | |
| 978 | (+ OP_LB base rt lo16) | |
| 979 | (set rt (ext WI (mem QI (add base (ext SI (trunc HI lo16)))))) | |
| 980 | ; (sequence ((SI addr) (SI word)) | |
| 981 | ; (set addr (add base lo16)) | |
| 982 | ; (set word (mem SI (and addr (inv 3)))) | |
| 983 | ; (set word (srl word (sll (and addr 2) 3))) | |
| 984 | ; (set rt (ext SI word))) | |
| 985 | ()) | |
| 986 | ||
| 987 | (dni lbu "load byte unsigned" (LOAD-DELAY USES-RS USES-RT) | |
| 988 | "lbu $rt,$lo16($base)" | |
| 989 | (+ OP_LBU base rt lo16) | |
| 990 | (set rt (zext WI (mem QI (add base (ext SI (trunc HI lo16)))))) | |
| 991 | ; (sequence ((SI addr) (SI word)) | |
| 992 | ; (set addr (add base lo16)) | |
| 993 | ; (set word (mem SI (and addr (inv 3)))) | |
| 994 | ; (set rt (srl word (sll (and addr 2) 3)))) | |
| 995 | ()) | |
| 996 | ||
| 997 | (dni lh "load half word" (LOAD-DELAY USES-RS USES-RT) | |
| 998 | "lh $rt,$lo16($base)" | |
| 999 | (+ OP_LH base rt lo16) | |
| 1000 | (set rt (ext WI (mem HI (add base (ext SI (trunc HI lo16)))))) | |
| 1001 | ; (sequence ((SI addr) (HI word)) | |
| 1002 | ; (set addr (add base lo16)) | |
| 1003 | ; (set word (mem SI (and addr (inv 3)))) | |
| 1004 | ; (set word (srl word (sll (and addr 1) 4))) | |
| 1005 | ; (set rt (ext SI word))) | |
| 1006 | ()) | |
| 1007 | ||
| 1008 | (dni lhu "load half word unsigned" (LOAD-DELAY USES-RS USES-RT) | |
| 1009 | "lhu $rt,$lo16($base)" | |
| 1010 | (+ OP_LHU base rt lo16) | |
| 1011 | (set rt (zext WI (mem HI (add base (ext SI (trunc HI lo16)))))) | |
| 1012 | ; (sequence ((SI addr) (SI word)) | |
| 1013 | ; (set addr (add base lo16)) | |
| 1014 | ; (set word (mem SI (and addr (inv 3)))) | |
| 1015 | ; (set rt (srl word (sll (and addr 1) 4)))) | |
| 1016 | ()) | |
| 1017 | ||
| 1018 | (dni lui "load upper immediate" (USES-RT) | |
| 1019 | "lui $rt,$hi16" | |
| 1020 | (+ OP_LUI (f-rs 0) rt hi16) | |
| 1021 | (set rt (sll hi16 16)) | |
| 1022 | ()) | |
| 1023 | ||
| 1024 | (dni lw "load word" (LOAD-DELAY USES-RS USES-RT) | |
| 1025 | "lw $rt,$lo16($base)" | |
| 1026 | (+ OP_LW base rt lo16) | |
| 1027 | (set rt (mem SI (add base (ext SI (trunc HI lo16))))) | |
| 1028 | ()) | |
| 1029 | ||
| 1030 | \f | |
| 1031 | ; Store instructions. | |
| 1032 | ||
| 1033 | (dni sb "store byte" (USES-RS USES-RT) | |
| 1034 | "sb $rt,$lo16($base)" | |
| 1035 | (+ OP_SB base rt lo16) | |
| 1036 | (set (mem QI (add base (ext SI (trunc HI lo16)))) (and QI rt #xFF)) | |
| 1037 | ()) | |
| 1038 | ||
| 1039 | (dni sh "store half word" (USES-RS USES-RT) | |
| 1040 | "sh $rt,$lo16($base)" | |
| 1041 | (+ OP_SH base rt lo16) | |
| 1042 | (set (mem HI (add base (ext SI (trunc HI lo16)))) (and HI rt #xFFFF)) | |
| 1043 | ()) | |
| 1044 | ||
| 1045 | (dni sw "store word" (USES-RS USES-RT) | |
| 1046 | "sw $rt,$lo16($base)" | |
| 1047 | (+ OP_SW base rt lo16) | |
| 1048 | (set (mem SI (add base (ext SI (trunc HI lo16)))) rt) | |
| 1049 | ()) | |
| 1050 | ||
| 1051 | \f | |
| 1052 | ; Special instructions for simulation/debugging | |
| 1053 | (dni break "breakpoint" () | |
| 1054 | "break" | |
| 1055 | (+ OP_SPECIAL (f-rs 0) (f-rt 0) (f-rd 0) (f-shamt 0) FUNC_BREAK) | |
| 1056 | (c-call VOID "do_break" pc) | |
| 1057 | ()) | |
| 1058 | ||
| 1059 | (dni syscall "system call" (YIELD-INSN) | |
| 1060 | "syscall" | |
| 1061 | (+ OP_SPECIAL execode (f-func 12)) | |
| 1062 | (c-call VOID "do_syscall") | |
| 1063 | ()) | |
| 1064 | ||
| 1065 | ; Macro instructions, common to iq10 & iq2000 | |
| 1066 | ||
| 1067 | (dnmi nop "nop" () | |
| 1068 | "nop" | |
| 1069 | (emit sll (rd 0) (rt 0) (shamt 0)) | |
| 1070 | ) | |
| 1071 | ||
| 1072 | (dnmi li "load immediate" (USES-RS NO-DIS) | |
| 1073 | "li $rs,$imm" | |
| 1074 | (emit ori (rt 0) rs imm) | |
| 1075 | ) | |
| 1076 | ||
| 1077 | (dnmi move "move" (USES-RD USES-RT NO-DIS) | |
| 1078 | "move $rd,$rt" | |
| 1079 | (emit or rd (rs 0) rt) | |
| 1080 | ) | |
| 1081 | ||
| 1082 | (dnmi lb-base-0 "load byte - implied base 0" (USES-RT NO-DIS) | |
| 1083 | "lb $rt,$lo16" | |
| 1084 | (emit lb rt lo16 (base 0)) | |
| 1085 | ) | |
| 1086 | ||
| 1087 | (dnmi lbu-base-0 "load byte unsigned - implied base 0" (USES-RT NO-DIS) | |
| 1088 | "lbu $rt,$lo16" | |
| 1089 | (emit lbu rt lo16 (base 0)) | |
| 1090 | ) | |
| 1091 | ||
| 1092 | (dnmi lh-base-0 "load half - implied base 0" (USES-RT NO-DIS) | |
| 1093 | "lh $rt,$lo16" | |
| 1094 | (emit lh rt lo16 (base 0)) | |
| 1095 | ) | |
| 1096 | ||
| 1097 | (dnmi lw-base-0 "load word - implied base 0" (USES-RT NO-DIS) | |
| 1098 | "lw $rt,$lo16" | |
| 1099 | (emit lw rt lo16 (base 0)) | |
| 1100 | ) | |
| 1101 | ||
| 1102 | (dnmi m-add "add immediate" (USES-RS USES-RT NO-DIS) | |
| 1103 | "add $rt,$rs,$lo16" | |
| 1104 | (emit addi rt rs lo16)) | |
| 1105 | ||
| 1106 | (dnmi m-addu "add immediate unsigned" (USES-RS USES-RT NO-DIS) | |
| 1107 | "addu $rt,$rs,$lo16" | |
| 1108 | (emit addiu rt rs lo16) | |
| 1109 | ) | |
| 1110 | ||
| 1111 | (dnmi m-and "and immediate" (USES-RS USES-RT NO-DIS) | |
| 1112 | "and $rt,$rs,$lo16" | |
| 1113 | (emit andi rt rs lo16) | |
| 1114 | ) | |
| 1115 | ||
| 1116 | (dnmi m-j "jump register" (USES-RS NO-DIS) | |
| 1117 | "j $rs" | |
| 1118 | (emit jr rs) | |
| 1119 | ) | |
| 1120 | ||
| 1121 | (dnmi m-or "or immediate" (USES-RS USES-RT NO-DIS) | |
| 1122 | "or $rt,$rs,$lo16" | |
| 1123 | (emit ori rt rs lo16) | |
| 1124 | ) | |
| 1125 | ||
| 1126 | (dnmi m-sll "shift left logical" (USES-RD USES-RT USES-RS NO-DIS) | |
| 1127 | "sll $rd,$rt,$rs" | |
| 1128 | (emit sllv rd rt rs) | |
| 1129 | ) | |
| 1130 | ||
| 1131 | (dnmi m-slt "slt immediate" (USES-RS USES-RT NO-DIS) | |
| 1132 | "slt $rt,$rs,$imm" | |
| 1133 | (emit slti rt rs imm) | |
| 1134 | ) | |
| 1135 | ||
| 1136 | (dnmi m-sltu "sltu immediate" (USES-RS USES-RT NO-DIS) | |
| 1137 | "sltu $rt,$rs,$imm" | |
| 1138 | (emit sltiu rt rs imm) | |
| 1139 | ) | |
| 1140 | ||
| 1141 | (dnmi m-sra "shift right arithmetic" (USES-RD USES-RT USES-RS NO-DIS) | |
| 1142 | "sra $rd,$rt,$rs" | |
| 1143 | (emit srav rd rt rs) | |
| 1144 | ) | |
| 1145 | ||
| 1146 | (dnmi m-srl "shift right logical" (USES-RD USES-RT USES-RS NO-DIS) | |
| 1147 | "srl $rd,$rt,$rs" | |
| 1148 | (emit srlv rd rt rs) | |
| 1149 | ) | |
| 1150 | ||
| 1151 | (dnmi not "not" (USES-RD USES-RT NO-DIS) | |
| 1152 | "not $rd,$rt" | |
| 1153 | (emit nor rd (rs 0) rt) | |
| 1154 | ) | |
| 1155 | ||
| 1156 | (dnmi subi "sub immediate" (USES-RS USES-RT NO-DIS) | |
| 1157 | "subi $rt,$rs,$mlo16" | |
| 1158 | (emit addiu rt rs mlo16) | |
| 1159 | ) | |
| 1160 | ||
| 1161 | (dnmi m-sub "subtract immediate" (USES-RS USES-RT NO-DIS) | |
| 1162 | "sub $rt,$rs,$mlo16" | |
| 1163 | (emit addiu rt rs mlo16) | |
| 1164 | ) | |
| 1165 | ||
| 1166 | (dnmi m-subu "subtract unsigned" (USES-RS USES-RT NO-DIS) | |
| 1167 | "subu $rt,$rs,$mlo16" | |
| 1168 | (emit addiu rt rs mlo16) | |
| 1169 | ) | |
| 1170 | ||
| 1171 | (dnmi sb-base-0 "store byte - implied base 0" (USES-RT NO-DIS) | |
| 1172 | "sb $rt,$lo16" | |
| 1173 | (emit sb rt lo16 (base 0)) | |
| 1174 | ) | |
| 1175 | ||
| 1176 | (dnmi sh-base-0 "store half - implied base 0" (USES-RT NO-DIS) | |
| 1177 | "sh $rt,$lo16" | |
| 1178 | (emit sh rt lo16 (base 0)) | |
| 1179 | ) | |
| 1180 | ||
| 1181 | (dnmi sw-base-0 "store word - implied base 0" (USES-RT NO-DIS) | |
| 1182 | "sw $rt,$lo16" | |
| 1183 | (emit sw rt lo16 (base 0)) | |
| 1184 | ) | |
| 1185 | ||
| 1186 | (dnmi m-xor "xor immediate" (USES-RS USES-RT NO-DIS) | |
| 1187 | "xor $rt,$rs,$lo16" | |
| 1188 | (emit xori rt rs lo16) | |
| 1189 | ) | |
| 1190 | ||
| 1191 | ||
| 1192 | (if (keep-mach? (iq2000)) | |
| b497d0b0 | 1193 | (include "iq2000m.cpu")) |
| 539ee71a AC |
1194 | |
| 1195 | (if (keep-mach? (iq10)) | |
| b497d0b0 | 1196 | (include "iq10.cpu")) |