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[deliverable/binutils-gdb.git] / cpu / m32c.cpu
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49f58d10 1; Renesas M32C CPU description. -*- Scheme -*-
0a665bfd 2;
6772dd07 3; Copyright 2005, 2006 Free Software Foundation, Inc.
0a665bfd
JB		 4;
5; Contributed by Red Hat Inc; developed under contract from Renesas.
6;
7; This file is part of the GNU Binutils.
8;
9; This program is free software; you can redistribute it and/or modify
10; it under the terms of the GNU General Public License as published by
11; the Free Software Foundation; either version 2 of the License, or
12; (at your option) any later version.
13;
14; This program is distributed in the hope that it will be useful,
15; but WITHOUT ANY WARRANTY; without even the implied warranty of
16; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17; GNU General Public License for more details.
18;
19; You should have received a copy of the GNU General Public License
20; along with this program; if not, write to the Free Software
21; Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
49f58d10
JB		 22
23(include "simplify.inc")
24
25(define-arch
26 (name m32c)
27 (comment "Renesas M32C")
28 (default-alignment forced)
29 (insn-lsb0? #f)
30 (machs m16c m32c)
31 (isas m16c m32c)
32)
33
34(define-isa
35 (name m16c)
36
37 (default-insn-bitsize 32)
38
39 ; Number of bytes of insn we can initially fetch.
40 (base-insn-bitsize 32)
41
42 ; Used in computing bit numbers.
43 (default-insn-word-bitsize 32)
44
45 (decode-assist (0 1 2 3 4 5 6 7)) ; Initial bitnumbers to decode insns by.
46
47 ; fetches 1 insn at a time.
48 (liw-insns 1)
49
50 ; executes 1 insn at a time.
51 (parallel-insns 1)
52 )
53
54(define-isa
55 (name m32c)
56
57 (default-insn-bitsize 32)
58
59 ; Number of bytes of insn we can initially fetch.
60 (base-insn-bitsize 32)
61
62 ; Used in computing bit numbers.
63 (default-insn-word-bitsize 32)
64
65 (decode-assist (0 1 2 3 4 5 6 7)) ; Initial bitnumbers to decode insns by.
66
67 ; fetches 1 insn at a time.
68 (liw-insns 1)
69
70 ; executes 1 insn at a time.
71 (parallel-insns 1)
72 )
73
74(define-cpu
75 ; cpu names must be distinct from the architecture name and machine names.
76 ; The "b" suffix stands for "base" and is the convention.
77 ; The "f" suffix stands for "family" and is the convention.
78 (name m16cbf)
79 (comment "Renesas M16C base family")
80 (insn-endian big)
81 (data-endian little)
82 (word-bitsize 16)
83)
84
85(define-cpu
86 ; cpu names must be distinct from the architecture name and machine names.
87 ; The "b" suffix stands for "base" and is the convention.
88 ; The "f" suffix stands for "family" and is the convention.
89 (name m32cbf)
90 (comment "Renesas M32C base family")
91 (insn-endian big)
92 (data-endian little)
93 (word-bitsize 16)
94)
95
96(define-mach
97 (name m16c)
98 (comment "Generic M16C cpu")
99 (cpu m32cbf)
100)
101
102(define-mach
103 (name m32c)
104 (comment "Generic M32C cpu")
105 (cpu m32cbf)
106)
107
108; Model descriptions.
109
110(define-model
111 (name m16c)
112 (comment "m16c") (attrs)
113 (mach m16c)
114
115 ; `state' is a list of variables for recording model state
116 ; (state)
117 (unit u-exec "Execution Unit" ()
118 1 1 ; issue done
119 () ; state
120 () ; inputs
121 () ; outputs
122 () ; profile action (default)
123 )
124)
125
126(define-model
127 (name m32c)
128 (comment "m32c") (attrs)
129 (mach m32c)
130
131 ; `state' is a list of variables for recording model state
132 ; (state)
133 (unit u-exec "Execution Unit" ()
134 1 1 ; issue done
135 () ; state
136 () ; inputs
137 () ; outputs
138 () ; profile action (default)
139 )
140)
141
6772dd07
DD		 142(define-attr
143 (type enum)
144 (name RL_TYPE)
145 (values NONE JUMP 1ADDR 2ADDR)
146 (default NONE)
147 )
148
49f58d10
JB		 149; Macros to simplify MACH attribute specification.
150
151(define-pmacro all-isas () (ISA m16c,m32c))
152(define-pmacro m16c-isa () (ISA m16c))
153(define-pmacro m32c-isa () (ISA m32c))
154
155(define-pmacro MACH16 (MACH m16c))
156(define-pmacro MACH32 (MACH m32c))
157
158(define-pmacro (machine size)
159 (MACH (.sym m size c)) (ISA (.sym m size c)))
6772dd07
DD		 160
161(define-pmacro RL_JUMP (RL_TYPE JUMP))
162(define-pmacro RL_1ADDR (RL_TYPE 1ADDR))
163(define-pmacro RL_2ADDR (RL_TYPE 2ADDR))
164
49f58d10
JB		 165\f
166;=============================================================
167; Fields
168;-------------------------------------------------------------
169; Main opcodes
170;
171(dnf f-0-1 "opcode" (all-isas) 0 1)
172(dnf f-0-2 "opcode" (all-isas) 0 2)
173(dnf f-0-3 "opcode" (all-isas) 0 3)
174(dnf f-0-4 "opcode" (all-isas) 0 4)
175(dnf f-1-3 "opcode" (all-isas) 1 3)
176(dnf f-2-2 "opcode" (all-isas) 2 2)
177(dnf f-3-4 "opcode" (all-isas) 3 4)
178(dnf f-3-1 "opcode" (all-isas) 3 1)
179(dnf f-4-1 "opcode" (all-isas) 4 1)
180(dnf f-4-3 "opcode" (all-isas) 4 3)
181(dnf f-4-4 "opcode" (all-isas) 4 4)
182(dnf f-4-6 "opcode" (all-isas) 4 6)
183(dnf f-5-1 "opcode" (all-isas) 5 1)
184(dnf f-5-3 "opcode" (all-isas) 5 3)
185(dnf f-6-2 "opcode" (all-isas) 6 2)
186(dnf f-7-1 "opcode" (all-isas) 7 1)
187(dnf f-8-1 "opcode" (all-isas) 8 1)
188(dnf f-8-2 "opcode" (all-isas) 8 2)
189(dnf f-8-3 "opcode" (all-isas) 8 3)
190(dnf f-8-4 "opcode" (all-isas) 8 4)
191(dnf f-8-8 "opcode" (all-isas) 8 8)
192(dnf f-9-3 "opcode" (all-isas) 9 3)
193(dnf f-9-1 "opcode" (all-isas) 9 1)
194(dnf f-10-1 "opcode" (all-isas) 10 1)
195(dnf f-10-2 "opcode" (all-isas) 10 2)
196(dnf f-10-3 "opcode" (all-isas) 10 3)
197(dnf f-11-1 "opcode" (all-isas) 11 1)
198(dnf f-12-1 "opcode" (all-isas) 12 1)
199(dnf f-12-2 "opcode" (all-isas) 12 2)
200(dnf f-12-3 "opcode" (all-isas) 12 3)
201(dnf f-12-4 "opcode" (all-isas) 12 4)
202(dnf f-12-6 "opcode" (all-isas) 12 6)
203(dnf f-13-3 "opcode" (all-isas) 13 3)
204(dnf f-14-1 "opcode" (all-isas) 14 1)
205(dnf f-14-2 "opcode" (all-isas) 14 2)
206(dnf f-15-1 "opcode" (all-isas) 15 1)
207(dnf f-16-1 "opcode" (all-isas) 16 1)
208(dnf f-16-2 "opcode" (all-isas) 16 2)
209(dnf f-16-4 "opcode" (all-isas) 16 4)
e729279b 210(dnf f-16-8 "opcode" (all-isas) 16 8)
49f58d10
JB		 211(dnf f-18-1 "opcode" (all-isas) 18 1)
212(dnf f-18-2 "opcode" (all-isas) 18 2)
213(dnf f-18-3 "opcode" (all-isas) 18 3)
214(dnf f-20-1 "opcode" (all-isas) 20 1)
215(dnf f-20-3 "opcode" (all-isas) 20 3)
216(dnf f-20-2 "opcode" (all-isas) 20 2)
217(dnf f-20-4 "opcode" (all-isas) 20 4)
218(dnf f-21-3 "opcode" (all-isas) 21 3)
219(dnf f-24-2 "opcode" (all-isas) 24 2)
e729279b
NC		 220(dnf f-24-8 "opcode" (all-isas) 24 8)
221(dnf f-32-16 "opcode" (all-isas) 32 16)
49f58d10
JB		 222
223;-------------------------------------------------------------
224; Registers
225;-------------------------------------------------------------
226
227(dnf f-src16-rn "source Rn for m16c" (MACH16 m16c-isa) 10 2)
228(dnf f-src16-an "source An for m16c" (MACH16 m16c-isa) 11 1)
229
230(dnf f-src32-an-unprefixed "destination An for m32c" (MACH32 m32c-isa) 11 1)
231(dnf f-src32-an-prefixed "destination An for m32c" (MACH32 m32c-isa) 19 1)
232
233; QI mode gr encoding for m32c is different than for m16c. The hardware
234; is indexed using the m16c encoding, so perform the transformation here.
235; register m16c m32c
236; ----------------------
237; r0l 00'b 10'b
238; r0h 01'b 00'b
239; r1l 10'b 11'b
240; r1h 11'b 01'b
241(df f-src32-rn-unprefixed-QI "source Rn QI for m32c" (MACH32 m32c-isa) 10 2 UINT
242 ((value pc) (or USI (and (sll (inv value) 1) 2) (and (srl value 1) 1))) ; insert
243 ((value pc) (or USI (and (inv (srl value 1)) 1) (and (sll value 1) 2))) ; extract
244)
245; QI mode gr encoding for m32c is different than for m16c. The hardware
246; is indexed using the m16c encoding, so perform the transformation here.
247; register m16c m32c
248; ----------------------
249; r0l 00'b 10'b
250; r0h 01'b 00'b
251; r1l 10'b 11'b
252; r1h 11'b 01'b
253(df f-src32-rn-prefixed-QI "source Rn QI for m32c" (MACH32 m32c-isa) 18 2 UINT
254 ((value pc) (or USI (and (sll (inv value) 1) 2) (and (srl value 1) 1))) ; insert
255 ((value pc) (or USI (and (inv (srl value 1)) 1) (and (sll value 1) 2))) ; extract
256)
257; HI mode gr encoding for m32c is different than for m16c. The hardware
258; is indexed using the m16c encoding, so perform the transformation here.
259; register m16c m32c
260; ----------------------
261; r0 00'b 10'b
262; r1 01'b 11'b
263; r2 10'b 00'b
264; r3 11'b 01'b
265(df f-src32-rn-unprefixed-HI "source Rn HI for m32c" (MACH32 m32c-isa) 10 2 UINT
266 ((value pc) (mod USI (add value 2) 4)) ; insert
267 ((value pc) (mod USI (add value 2) 4)) ; extract
268)
269
270; HI mode gr encoding for m32c is different than for m16c. The hardware
271; is indexed using the m16c encoding, so perform the transformation here.
272; register m16c m32c
273; ----------------------
274; r0 00'b 10'b
275; r1 01'b 11'b
276; r2 10'b 00'b
277; r3 11'b 01'b
278(df f-src32-rn-prefixed-HI "source Rn HI for m32c" (MACH32 m32c-isa) 18 2 UINT
279 ((value pc) (mod USI (add value 2) 4)) ; insert
280 ((value pc) (mod USI (add value 2) 4)) ; extract
281)
282
283; SI mode gr encoding for m32c is as follows:
284; register encoding index
285; -------------------------
286; r2r0 10'b 0
287; r3r1 11'b 1
288(df f-src32-rn-unprefixed-SI "source Rn SI for m32c" (MACH32 m32c-isa) 10 2 UINT
289 ((value pc) (add USI value 2)) ; insert
290 ((value pc) (sub USI value 2)) ; extract
291)
292(df f-src32-rn-prefixed-SI "source Rn SI for m32c" (MACH32 m32c-isa) 18 2 UINT
293 ((value pc) (add USI value 2)) ; insert
294 ((value pc) (sub USI value 2)) ; extract
295)
296
297(dnf f-dst32-rn-ext-unprefixed "destination Rn for m32c" (MACH32 m32c-isa) 9 1)
298
299(dnf f-dst16-rn "destination Rn for m16c" (MACH16 m16c-isa) 14 2)
300(dnf f-dst16-rn-ext "destination Rn for m16c" (MACH16 m16c-isa) 14 1)
301(dnf f-dst16-rn-QI-s "destination Rn for m16c" (MACH16 m16c-isa) 5 1)
302
303(dnf f-dst16-an "destination An for m16c" (MACH16 m16c-isa) 15 1)
304(dnf f-dst16-an-s "destination An for m16c" (MACH16 m16c-isa) 4 1)
305
306(dnf f-dst32-an-unprefixed "destination An for m32c" (MACH32 m32c-isa) 9 1)
307(dnf f-dst32-an-prefixed "destination An for m32c" (MACH32 m32c-isa) 17 1)
308
309; QI mode gr encoding for m32c is different than for m16c. The hardware
310; is indexed using the m16c encoding, so perform the transformation here.
311; register m16c m32c
312; ----------------------
313; r0l 00'b 10'b
314; r0h 01'b 00'b
315; r1l 10'b 11'b
316; r1h 11'b 01'b
317(df f-dst32-rn-unprefixed-QI "destination Rn QI for m32c" (MACH32 m32c-isa) 8 2 UINT
318 ((value pc) (or USI (and (sll (inv value) 1) 2) (and (srl value 1) 1))) ; insert
319 ((value pc) (or USI (and (inv (srl value 1)) 1) (and (sll value 1) 2))) ; extract
320)
321(df f-dst32-rn-prefixed-QI "destination Rn QI for m32c" (MACH32 m32c-isa) 16 2 UINT
322 ((value pc) (or USI (and (sll (inv value) 1) 2) (and (srl value 1) 1))) ; insert
323 ((value pc) (or USI (and (inv (srl value 1)) 1) (and (sll value 1) 2))) ; extract
324)
325; HI mode gr encoding for m32c is different than for m16c. The hardware
326; is indexed using the m16c encoding, so perform the transformation here.
327; register m16c m32c
328; ----------------------
329; r0 00'b 10'b
330; r1 01'b 11'b
331; r2 10'b 00'b
332; r3 11'b 01'b
333(df f-dst32-rn-unprefixed-HI "destination Rn HI for m32c" (MACH32 m32c-isa) 8 2 UINT
334 ((value pc) (mod USI (add value 2) 4)) ; insert
335 ((value pc) (mod USI (add value 2) 4)) ; extract
336)
337(df f-dst32-rn-prefixed-HI "destination Rn HI for m32c" (MACH32 m32c-isa) 16 2 UINT
338 ((value pc) (mod USI (add value 2) 4)) ; insert
339 ((value pc) (mod USI (add value 2) 4)) ; extract
340)
341; SI mode gr encoding for m32c is as follows:
342; register encoding index
343; -------------------------
344; r2r0 10'b 0
345; r3r1 11'b 1
346(df f-dst32-rn-unprefixed-SI "destination Rn SI for m32c" (MACH32 m32c-isa) 8 2 UINT
347 ((value pc) (add USI value 2)) ; insert
348 ((value pc) (sub USI value 2)) ; extract
349)
350(df f-dst32-rn-prefixed-SI "destination Rn SI for m32c" (MACH32 m32c-isa) 16 2 UINT
351 ((value pc) (add USI value 2)) ; insert
352 ((value pc) (sub USI value 2)) ; extract
353)
354
355(dnf f-dst16-1-S "destination R0[hl] for m16c" (MACH16 m16c-isa) 5 1)
356
357;-------------------------------------------------------------
358; Immediates embedded in the base insn
359;-------------------------------------------------------------
360
361(df f-imm-8-s4 "4 bit signed" (all-isas) 8 4 INT #f #f)
362(df f-imm-12-s4 "4 bit signed" (all-isas) 12 4 INT #f #f)
363(df f-imm-13-u3 "3 bit unsigned" (all-isas) 13 3 UINT #f #f)
364(df f-imm-20-s4 "4 bit signed" (all-isas) 20 4 INT #f #f)
365
366(df f-imm1-S "1 bit immediate for short format binary insns" (MACH32 m32c-isa) 2 1 UINT
367 ((value pc) (sub USI value 1)) ; insert
368 ((value pc) (add USI value 1)) ; extract
369)
370
371(dnmf f-imm3-S "3 bit unsigned for short format insns" (all-isas) UINT
372 (f-2-2 f-7-1)
373 (sequence () ; insert
374 (set (ifield f-7-1) (and (sub (ifield f-imm3-S) 1) 1))
375 (set (ifield f-2-2) (and (srl (sub (ifield f-imm3-S) 1) 1) #x3))
376 )
377 (sequence () ; extract
378 (set (ifield f-imm3-S) (add (or (sll (ifield f-2-2) 1)
379 (ifield f-7-1))
380 1))
381 )
382)
383
384;-------------------------------------------------------------
385; Immediates and displacements beyond the base insn
386;-------------------------------------------------------------
387
388(df f-dsp-8-u6 "6 bit unsigned" (all-isas) 8 6 UINT #f #f)
389(df f-dsp-8-u8 "8 bit unsigned" (all-isas) 8 8 UINT #f #f)
390(df f-dsp-8-s8 "8 bit signed" (all-isas) 8 8 INT #f #f)
391(df f-dsp-10-u6 "6 bit unsigned" (all-isas) 10 6 UINT #f #f)
392(df f-dsp-16-u8 "8 bit unsigned" (all-isas) 16 8 UINT #f #f)
393(df f-dsp-16-s8 "8 bit signed" (all-isas) 16 8 INT #f #f)
394(df f-dsp-24-u8 "8 bit unsigned" (all-isas) 24 8 UINT #f #f)
395(df f-dsp-24-s8 "8 bit signed" (all-isas) 24 8 INT #f #f)
396(df f-dsp-32-u8 "8 bit unsigned" (all-isas) 32 8 UINT #f #f)
397(df f-dsp-32-s8 "8 bit signed" (all-isas) 32 8 INT #f #f)
398(df f-dsp-40-u8 "8 bit unsigned" (all-isas) 40 8 UINT #f #f)
399(df f-dsp-40-s8 "8 bit signed" (all-isas) 40 8 INT #f #f)
400(df f-dsp-48-u8 "8 bit unsigned" (all-isas) 48 8 UINT #f #f)
401(df f-dsp-48-s8 "8 bit signed" (all-isas) 48 8 INT #f #f)
402(df f-dsp-56-u8 "8 bit unsigned" (all-isas) 56 8 UINT #f #f)
403(df f-dsp-56-s8 "8 bit signed" (all-isas) 56 8 INT #f #f)
404(df f-dsp-64-u8 "8 bit unsigned" (all-isas) 64 8 UINT #f #f)
405(df f-dsp-64-s8 "8 bit signed" (all-isas) 64 8 INT #f #f)
406
407; Insn opcode endianness is big, but the immediate fields are stored
408; in little endian. Handle this here at the field level for all immediate
409; fields longer that 1 byte.
410;
411; CGEN can't handle a field which spans a 32 bit word boundary, so
412; handle those as multi ifields.
413;
414; Take care in expressions using 'srl' or 'sll' as part of some larger
415; expression meant to yield sign-extended values. CGEN translates
416; uses of those operators into C expressions whose type is 'unsigned
417; int', which tends to make the whole expression 'unsigned int'.
418; Expressions like (set (ifield foo) X), however, just take X and
419; store it in some member of 'struct cgen_fields', all of whose
420; members are 'long'. On machines where 'long' is larger than
421; 'unsigned int', assigning a "sign-extended" unsigned int to a long
422; just produces a very large positive value. insert_normal will
423; range-check the field's value and produce odd error messages like
424; this:
425;
426; Error: operand out of range (4160684031 not between -2147483648 and 2147483647) `add.l #-265,-270[fb]'
427;
428; Annoyingly, the code will work fine on machines where 'long' and
429; 'unsigned int' are the same size: the assignment will produce a
430; negative number.
431;
432; Just tell yourself over and over: overflow detection is expensive,
433; and you're glad C doesn't do it, because it never happens in real
434; life.
435
436(df f-dsp-8-u16 "16 bit unsigned" (all-isas) 8 16 UINT
437 ((value pc) (or UHI
438 (and (srl value 8) #x00ff)
439 (and (sll value 8) #xff00))) ; insert
440 ((value pc) (or UHI
441 (and UHI (srl UHI value 8) #x00ff)
442 (and UHI (sll UHI value 8) #xff00))) ; extract
443)
444
445(df f-dsp-8-s16 "8 bit signed" (all-isas) 8 16 INT
446 ((value pc) (ext INT
447 (trunc HI
448 (or (and (srl value 8) #x00ff)
449 (and (sll value 8) #xff00))))) ; insert
450 ((value pc) (ext INT
451 (trunc HI
452 (or (and (srl value 8) #x00ff)
453 (and (sll value 8) #xff00))))) ; extract
454)
455
456(df f-dsp-16-u16 "16 bit unsigned" (all-isas) 16 16 UINT
457 ((value pc) (or UHI
458 (and (srl value 8) #x00ff)
459 (and (sll value 8) #xff00))) ; insert
460 ((value pc) (or UHI
461 (and UHI (srl UHI value 8) #x00ff)
462 (and UHI (sll UHI value 8) #xff00))) ; extract
463)
464
465(df f-dsp-16-s16 "16 bit signed" (all-isas) 16 16 INT
466 ((value pc) (ext INT
467 (trunc HI
468 (or (and (srl value 8) #x00ff)
469 (and (sll value 8) #xff00))))) ; insert
470 ((value pc) (ext INT
471 (trunc HI
472 (or (and (srl value 8) #x00ff)
473 (and (sll value 8) #xff00))))) ; extract
474)
475
476(dnmf f-dsp-24-u16 "16 bit unsigned" (all-isas) UINT
477 (f-dsp-24-u8 f-dsp-32-u8)
478 (sequence () ; insert
479 (set (ifield f-dsp-24-u8) (and (ifield f-dsp-24-u16) #xff))
480 (set (ifield f-dsp-32-u8) (and (srl (ifield f-dsp-24-u16) 8) #xff))
481 )
482 (sequence () ; extract
483 (set (ifield f-dsp-24-u16) (or (sll (ifield f-dsp-32-u8) 8)
484 (ifield f-dsp-24-u8)))
485 )
486)
487
488(dnmf f-dsp-24-s16 "16 bit signed" (all-isas) INT
489 (f-dsp-24-u8 f-dsp-32-u8)
490 (sequence () ; insert
491 (set (ifield f-dsp-24-u8)
492 (and (ifield f-dsp-24-s16) #xff))
493 (set (ifield f-dsp-32-u8)
494 (and (srl (ifield f-dsp-24-s16) 8) #xff))
495 )
496 (sequence () ; extract
497 (set (ifield f-dsp-24-s16)
498 (ext INT
499 (trunc HI (or (sll (ifield f-dsp-32-u8) 8)
500 (ifield f-dsp-24-u8)))))
501 )
502)
503
504(df f-dsp-32-u16 "16 bit unsigned" (all-isas) 32 16 UINT
505 ((value pc) (or UHI
506 (and (srl value 8) #x00ff)
507 (and (sll value 8) #xff00))) ; insert
508 ((value pc) (or UHI
509 (and UHI (srl UHI value 8) #x00ff)
510 (and UHI (sll UHI value 8) #xff00))) ; extract
511)
512
513(df f-dsp-32-s16 "16 bit signed" (all-isas) 32 16 INT
514 ((value pc) (ext INT
515 (trunc HI
516 (or (and (srl value 8) #x00ff)
517 (and (sll value 8) #xff00))))) ; insert
518 ((value pc) (ext INT
519 (trunc HI
520 (or (and (srl value 8) #x00ff)
521 (and (sll value 8) #xff00))))) ; extract
522)
523
524(df f-dsp-40-u16 "16 bit unsigned" (all-isas) 40 16 UINT
525 ((value pc) (or UHI
526 (and (srl value 8) #x00ff)
527 (and (sll value 8) #xff00))) ; insert
528 ((value pc) (or UHI
529 (and UHI (srl UHI value 8) #x00ff)
530 (and UHI (sll UHI value 8) #xff00))) ; extract
531)
532
533(df f-dsp-40-s16 "16 bit signed" (all-isas) 40 16 INT
534 ((value pc) (ext INT
535 (trunc HI
536 (or (and (srl value 8) #x00ff)
537 (and (sll value 8) #xff00))))) ; insert
538 ((value pc) (ext INT
539 (trunc HI
540 (or (and (srl value 8) #x00ff)
541 (and (sll value 8) #xff00))))) ; extract
542)
543
544(df f-dsp-48-u16 "16 bit unsigned" (all-isas) 48 16 UINT
545 ((value pc) (or UHI
546 (and (srl value 8) #x00ff)
547 (and (sll value 8) #xff00))) ; insert
548 ((value pc) (or UHI
549 (and UHI (srl UHI value 8) #x00ff)
550 (and UHI (sll UHI value 8) #xff00))) ; extract
551)
552
553(df f-dsp-48-s16 "16 bit signed" (all-isas) 48 16 INT
554 ((value pc) (ext INT
555 (trunc HI
556 (or (and (srl value 8) #x00ff)
557 (and (sll value 8) #xff00))))) ; insert
558 ((value pc) (ext INT
559 (trunc HI
560 (or (and (srl value 8) #x00ff)
561 (and (sll value 8) #xff00))))) ; extract
562)
563
564(df f-dsp-64-u16 "16 bit unsigned" (all-isas) 64 16 UINT
565 ((value pc) (or UHI
566 (and (srl value 8) #x00ff)
567 (and (sll value 8) #xff00))) ; insert
568 ((value pc) (or UHI
569 (and UHI (srl UHI value 8) #x00ff)
570 (and UHI (sll UHI value 8) #xff00))) ; extract
571)
f75eb1c0
DD		 572(df f-dsp-8-s24 "24 bit signed" (all-isas) 8 24 INT
573 ((value pc) (or SI
574 (or (srl value 16) (and value #xff00))
575 (sll (ext INT (trunc QI (and value #xff))) 16)))
576 ((value pc) (or SI
577 (or (srl value 16) (and value #xff00))
578 (sll (ext INT (trunc QI (and value #xff))) 16)))
579 )
580
e729279b
NC		 581(df f-dsp-8-u24 "24 bit unsigned" (all-isas) 8 24 UINT
582 ((value pc) (or SI
583 (or (srl value 16) (and value #xff00))
584 (sll (and value #xff) 16)))
585 ((value pc) (or SI
586 (or (srl value 16) (and value #xff00))
587 (sll (and value #xff) 16)))
588 )
49f58d10
JB		 589
590(dnmf f-dsp-16-u24 "24 bit unsigned" (all-isas) UINT
591 (f-dsp-16-u16 f-dsp-32-u8)
592 (sequence () ; insert
593 (set (ifield f-dsp-16-u16) (and (ifield f-dsp-16-u24) #xffff))
594 (set (ifield f-dsp-32-u8) (and (srl (ifield f-dsp-16-u24) 16) #xff))
595 )
596 (sequence () ; extract
597 (set (ifield f-dsp-16-u24) (or (sll (ifield f-dsp-32-u8) 16)
598 (ifield f-dsp-16-u16)))
599 )
600)
601
602(dnmf f-dsp-24-u24 "24 bit unsigned" (all-isas) UINT
603 (f-dsp-24-u8 f-dsp-32-u16)
604 (sequence () ; insert
605 (set (ifield f-dsp-24-u8) (and (ifield f-dsp-24-u24) #xff))
606 (set (ifield f-dsp-32-u16) (and (srl (ifield f-dsp-24-u24) 8) #xffff))
607 )
608 (sequence () ; extract
609 (set (ifield f-dsp-24-u24) (or (sll (ifield f-dsp-32-u16) 8)
610 (ifield f-dsp-24-u8)))
611 )
612)
613
614(df f-dsp-32-u24 "24 bit unsigned" (all-isas) 32 24 UINT
615 ((value pc) (or USI
616 (or USI
617 (and (srl value 16) #x0000ff)
618 (and value #x00ff00))
619 (and (sll value 16) #xff0000))) ; insert
620 ((value pc) (or USI
621 (or USI
622 (and USI (srl UHI value 16) #x0000ff)
623 (and USI value #x00ff00))
624 (and USI (sll UHI value 16) #xff0000))) ; extract
625)
626
75b06e7b
DD		 627(df f-dsp-40-u20 "20 bit unsigned" (all-isas) 40 20 UINT
628 ((value pc) (or USI
629 (or USI
630 (and (srl value 16) #x0000ff)
631 (and value #x00ff00))
632 (and (sll value 16) #x0f0000))) ; insert
633 ((value pc) (or USI
634 (or USI
635 (and USI (srl UHI value 16) #x0000ff)
636 (and USI value #x00ff00))
637 (and USI (sll UHI value 16) #x0f0000))) ; extract
638)
49f58d10
JB		 639(df f-dsp-40-u24 "24 bit unsigned" (all-isas) 40 24 UINT
640 ((value pc) (or USI
641 (or USI
642 (and (srl value 16) #x0000ff)
643 (and value #x00ff00))
644 (and (sll value 16) #xff0000))) ; insert
645 ((value pc) (or USI
646 (or USI
647 (and USI (srl UHI value 16) #x0000ff)
648 (and USI value #x00ff00))
649 (and USI (sll UHI value 16) #xff0000))) ; extract
650)
651
652(dnmf f-dsp-40-s32 "32 bit signed" (all-isas) INT
653 (f-dsp-40-u24 f-dsp-64-u8)
654 (sequence () ; insert
655 (set (ifield f-dsp-64-u8) (and (srl (ifield f-dsp-40-s32) 24) #xff))
656 (set (ifield f-dsp-40-u24) (and (ifield f-dsp-40-s32) #xffffff))
657 )
658 (sequence () ; extract
659 (set (ifield f-dsp-40-s32) (or (and (ifield f-dsp-40-u24) #xffffff)
660 (and (sll (ifield f-dsp-64-u8) 24) #xff000000)))
661 )
662)
663
75b06e7b
DD		 664(dnmf f-dsp-48-u20 "20 bit unsigned" (all-isas) UINT
665 (f-dsp-48-u16 f-dsp-64-u8)
666 (sequence () ; insert
667 (set (ifield f-dsp-64-u8) (and (srl (ifield f-dsp-48-u20) 16) #x0f))
668 (set (ifield f-dsp-48-u16) (and (ifield f-dsp-48-u20) #xffff))
669 )
670 (sequence () ; extract
671 (set (ifield f-dsp-48-u20) (or (and (ifield f-dsp-48-u16) #xffff)
672 (and (sll (ifield f-dsp-64-u8) 16) #x0f0000)))
673 )
674)
49f58d10
JB		 675(dnmf f-dsp-48-u24 "24 bit unsigned" (all-isas) UINT
676 (f-dsp-48-u16 f-dsp-64-u8)
677 (sequence () ; insert
678 (set (ifield f-dsp-64-u8) (and (srl (ifield f-dsp-48-u24) 16) #xff))
679 (set (ifield f-dsp-48-u16) (and (ifield f-dsp-48-u24) #xffff))
680 )
681 (sequence () ; extract
682 (set (ifield f-dsp-48-u24) (or (and (ifield f-dsp-48-u16) #xffff)
683 (and (sll (ifield f-dsp-64-u8) 16) #xff0000)))
684 )
685)
686
687(dnmf f-dsp-16-s32 "32 bit signed" (all-isas) INT
688 (f-dsp-16-u16 f-dsp-32-u16)
689 (sequence () ; insert
690 (set (ifield f-dsp-32-u16) (and (srl (ifield f-dsp-16-s32) 16) #xffff))
691 (set (ifield f-dsp-16-u16) (and (ifield f-dsp-16-s32) #xffff))
692 )
693 (sequence () ; extract
694 (set (ifield f-dsp-16-s32) (or (and (ifield f-dsp-16-u16) #xffff)
695 (and (sll (ifield f-dsp-32-u16) 16) #xffff0000)))
696 )
697)
698
699(dnmf f-dsp-24-s32 "32 bit signed" (all-isas) INT
700 (f-dsp-24-u8 f-dsp-32-u24)
701 (sequence () ; insert
702 (set (ifield f-dsp-32-u24) (and (srl (ifield f-dsp-24-s32) 8) #xffffff))
703 (set (ifield f-dsp-24-u8) (and (ifield f-dsp-24-s32) #xff))
704 )
705 (sequence () ; extract
706 (set (ifield f-dsp-24-s32) (or (and (ifield f-dsp-24-u8) #xff)
707 (and (sll (ifield f-dsp-32-u24) 8) #xffffff00)))
708 )
709)
710
711(df f-dsp-32-s32 "32 bit signed" (all-isas) 32 32 INT
712 ((value pc)
713
714 ;; insert
715 (ext INT
716 (or SI
717 (or SI
718 (and (srl value 24) #x000000ff)
719 (and (srl value 8) #x0000ff00))
720 (or SI
721 (and (sll value 8) #x00ff0000)
722 (and (sll value 24) #xff000000)))))
723
724 ;; extract
725 ((value pc)
726 (ext INT
727 (or SI
728 (or SI
729 (and (srl value 24) #x000000ff)
730 (and (srl value 8) #x0000ff00))
731 (or SI
732 (and (sll value 8) #x00ff0000)
733 (and (sll value 24) #xff000000)))))
734)
735
736(dnmf f-dsp-48-u32 "32 bit unsigned" (all-isas) UINT
737 (f-dsp-48-u16 f-dsp-64-u16)
738 (sequence () ; insert
739 (set (ifield f-dsp-64-u16) (and (srl (ifield f-dsp-48-u32) 16) #xffff))
740 (set (ifield f-dsp-48-u16) (and (ifield f-dsp-48-u32) #xffff))
741 )
742 (sequence () ; extract
743 (set (ifield f-dsp-48-u32) (or (and (ifield f-dsp-48-u16) #xffff)
744 (and (sll (ifield f-dsp-64-u16) 16) #xffff0000)))
745 )
746)
747
748(dnmf f-dsp-48-s32 "32 bit signed" (all-isas) INT
749 (f-dsp-48-u16 f-dsp-64-u16)
750 (sequence () ; insert
751 (set (ifield f-dsp-64-u16) (and (srl (ifield f-dsp-48-s32) 16) #xffff))
752 (set (ifield f-dsp-48-u16) (and (ifield f-dsp-48-s32) #xffff))
753 )
754 (sequence () ; extract
755 (set (ifield f-dsp-48-s32) (or (and (ifield f-dsp-48-u16) #xffff)
756 (and (sll (ifield f-dsp-64-u16) 16) #xffff0000)))
757 )
758)
759
760(dnmf f-dsp-56-s16 "16 bit signed" (all-isas) INT
761 (f-dsp-56-u8 f-dsp-64-u8)
762 (sequence () ; insert
763 (set (ifield f-dsp-56-u8)
764 (and (ifield f-dsp-56-s16) #xff))
765 (set (ifield f-dsp-64-u8)
766 (and (srl (ifield f-dsp-56-s16) 8) #xff))
767 )
768 (sequence () ; extract
769 (set (ifield f-dsp-56-s16)
770 (ext INT
771 (trunc HI (or (sll (ifield f-dsp-64-u8) 8)
772 (ifield f-dsp-56-u8)))))
773 )
774)
775
776(df f-dsp-64-s16 " 16 bit signed" (all-isas) 64 16 INT
777 ((value pc) (ext INT
778 (trunc HI
779 (or (and (srl value 8) #x00ff)
780 (and (sll value 8) #xff00))))) ; insert
781 ((value pc) (ext INT
782 (trunc HI
783 (or (and (srl value 8) #x00ff)
784 (and (sll value 8) #xff00))))) ; extract
785)
786
787;-------------------------------------------------------------
788; Bit indices
789;-------------------------------------------------------------
790
791(dnf f-bitno16-S "bit index for m16c" (all-isas) 5 3)
792(dnf f-bitno32-prefixed "bit index for m32c" (all-isas) 21 3)
793(dnf f-bitno32-unprefixed "bit index for m32c" (all-isas) 13 3)
794
795(dnmf f-bitbase16-u11-S "unsigned bit,base:11" (all-isas) UINT
796 (f-bitno16-S f-dsp-8-u8)
797 (sequence () ; insert
798 (set (ifield f-bitno16-S) (and f-bitbase16-u11-S #x7))
799 (set (ifield f-dsp-8-u8) (and (srl (ifield f-bitbase16-u11-S) 3) #xff))
800 )
801 (sequence () ; extract
802 (set (ifield f-bitbase16-u11-S) (or (sll (ifield f-dsp-8-u8) 3)
803 (ifield f-bitno16-S)))
804 )
805)
806
807(dnmf f-bitbase32-16-u11-unprefixed "unsigned bit,base:11" (all-isas) UINT
808 (f-bitno32-unprefixed f-dsp-16-u8)
809 (sequence () ; insert
810 (set (ifield f-bitno32-unprefixed) (and f-bitbase32-16-u11-unprefixed #x7))
811 (set (ifield f-dsp-16-u8) (and (srl (ifield f-bitbase32-16-u11-unprefixed) 3) #xff))
812 )
813 (sequence () ; extract
814 (set (ifield f-bitbase32-16-u11-unprefixed) (or (sll (ifield f-dsp-16-u8) 3)
815 (ifield f-bitno32-unprefixed)))
816 )
817)
818(dnmf f-bitbase32-16-s11-unprefixed "signed bit,base:11" (all-isas) INT
819 (f-bitno32-unprefixed f-dsp-16-s8)
820 (sequence () ; insert
821 (set (ifield f-bitno32-unprefixed) (and f-bitbase32-16-s11-unprefixed #x7))
822 (set (ifield f-dsp-16-s8) (sra INT (ifield f-bitbase32-16-s11-unprefixed) 3))
823 )
824 (sequence () ; extract
825 (set (ifield f-bitbase32-16-s11-unprefixed) (or (sll (ifield f-dsp-16-s8) 3)
826 (ifield f-bitno32-unprefixed)))
827 )
828)
829(dnmf f-bitbase32-16-u19-unprefixed "unsigned bit,base:19" (all-isas) UINT
830 (f-bitno32-unprefixed f-dsp-16-u16)
831 (sequence () ; insert
832 (set (ifield f-bitno32-unprefixed) (and f-bitbase32-16-u19-unprefixed #x7))
833 (set (ifield f-dsp-16-u16) (and (srl (ifield f-bitbase32-16-u19-unprefixed) 3) #xffff))
834 )
835 (sequence () ; extract
836 (set (ifield f-bitbase32-16-u19-unprefixed) (or (sll (ifield f-dsp-16-u16) 3)
837 (ifield f-bitno32-unprefixed)))
838 )
839)
840(dnmf f-bitbase32-16-s19-unprefixed "signed bit,base:11" (all-isas) INT
841 (f-bitno32-unprefixed f-dsp-16-s16)
842 (sequence () ; insert
843 (set (ifield f-bitno32-unprefixed) (and f-bitbase32-16-s19-unprefixed #x7))
844 (set (ifield f-dsp-16-s16) (sra INT (ifield f-bitbase32-16-s19-unprefixed) 3))
845 )
846 (sequence () ; extract
847 (set (ifield f-bitbase32-16-s19-unprefixed) (or (sll (ifield f-dsp-16-s16) 3)
848 (ifield f-bitno32-unprefixed)))
849 )
850)
851; SID decoder doesn't handle multi-ifield referencing another multi-ifield :-(
852(dnmf f-bitbase32-16-u27-unprefixed "unsigned bit,base:27" (all-isas) UINT
853 (f-bitno32-unprefixed f-dsp-16-u16 f-dsp-32-u8)
854 (sequence () ; insert
855 (set (ifield f-bitno32-unprefixed) (and f-bitbase32-16-u27-unprefixed #x7))
856 (set (ifield f-dsp-16-u16) (and (srl (ifield f-bitbase32-16-u27-unprefixed) 3) #xffff))
857 (set (ifield f-dsp-32-u8) (and (srl (ifield f-bitbase32-16-u27-unprefixed) 19) #xff))
858 )
859 (sequence () ; extract
860 (set (ifield f-bitbase32-16-u27-unprefixed) (or (sll (ifield f-dsp-16-u16) 3)
861 (or (sll (ifield f-dsp-32-u8) 19)
862 (ifield f-bitno32-unprefixed))))
863 )
864)
865(dnmf f-bitbase32-24-u11-prefixed "unsigned bit,base:11" (all-isas) UINT
866 (f-bitno32-prefixed f-dsp-24-u8)
867 (sequence () ; insert
868 (set (ifield f-bitno32-prefixed) (and f-bitbase32-24-u11-prefixed #x7))
869 (set (ifield f-dsp-24-u8) (and (srl (ifield f-bitbase32-24-u11-prefixed) 3) #xff))
870 )
871 (sequence () ; extract
872 (set (ifield f-bitbase32-24-u11-prefixed) (or (sll (ifield f-dsp-24-u8) 3)
873 (ifield f-bitno32-prefixed)))
874 )
875)
876(dnmf f-bitbase32-24-s11-prefixed "signed bit,base:11" (all-isas) INT
877 (f-bitno32-prefixed f-dsp-24-s8)
878 (sequence () ; insert
879 (set (ifield f-bitno32-prefixed) (and f-bitbase32-24-s11-prefixed #x7))
880 (set (ifield f-dsp-24-s8) (sra INT (ifield f-bitbase32-24-s11-prefixed) 3))
881 )
882 (sequence () ; extract
883 (set (ifield f-bitbase32-24-s11-prefixed) (or (sll (ifield f-dsp-24-s8) 3)
884 (ifield f-bitno32-prefixed)))
885 )
886)
887; SID decoder doesn't handle multi-ifield referencing another multi-ifield :-(
888(dnmf f-bitbase32-24-u19-prefixed "unsigned bit,base:19" (all-isas) UINT
889 (f-bitno32-prefixed f-dsp-24-u8 f-dsp-32-u8)
890 (sequence () ; insert
891 (set (ifield f-bitno32-prefixed) (and f-bitbase32-24-u19-prefixed #x7))
892 (set (ifield f-dsp-24-u8) (and (srl (ifield f-bitbase32-24-u19-prefixed) 3) #xff))
893 (set (ifield f-dsp-32-u8) (and (srl (ifield f-bitbase32-24-u19-prefixed) 11) #xff))
894 )
895 (sequence () ; extract
896 (set (ifield f-bitbase32-24-u19-prefixed) (or (sll (ifield f-dsp-24-u8) 3)
897 (or (sll (ifield f-dsp-32-u8) 11)
898 (ifield f-bitno32-prefixed))))
899 )
900)
901; SID decoder doesn't handle multi-ifield referencing another multi-ifield :-(
902(dnmf f-bitbase32-24-s19-prefixed "signed bit,base:11" (all-isas) INT
903 (f-bitno32-prefixed f-dsp-24-u8 f-dsp-32-s8)
904 (sequence () ; insert
905 (set (ifield f-bitno32-prefixed) (and f-bitbase32-24-s19-prefixed #x7))
906 (set (ifield f-dsp-24-u8) (and (srl (ifield f-bitbase32-24-s19-prefixed) 3) #xff))
907 (set (ifield f-dsp-32-s8) (sra INT (ifield f-bitbase32-24-s19-prefixed) 11))
908 )
909 (sequence () ; extract
910 (set (ifield f-bitbase32-24-s19-prefixed) (or (sll (ifield f-dsp-24-u8) 3)
911 (or (sll (ifield f-dsp-32-s8) 11)
912 (ifield f-bitno32-prefixed))))
913 )
914)
915; SID decoder doesn't handle multi-ifield referencing another multi-ifield :-(
916(dnmf f-bitbase32-24-u27-prefixed "unsigned bit,base:27" (all-isas) UINT
917 (f-bitno32-prefixed f-dsp-24-u8 f-dsp-32-u16)
918 (sequence () ; insert
919 (set (ifield f-bitno32-prefixed) (and f-bitbase32-24-u27-prefixed #x7))
920 (set (ifield f-dsp-24-u8) (and (srl (ifield f-bitbase32-24-u27-prefixed) 3) #xff))
921 (set (ifield f-dsp-32-u16) (and (srl (ifield f-bitbase32-24-u27-prefixed) 11) #xffff))
922 )
923 (sequence () ; extract
924 (set (ifield f-bitbase32-24-u27-prefixed) (or (sll (ifield f-dsp-24-u8) 3)
925 (or (sll (ifield f-dsp-32-u16) 11)
926 (ifield f-bitno32-prefixed))))
927 )
928)
929
930;-------------------------------------------------------------
931; Labels
932;-------------------------------------------------------------
933
e729279b 934(df f-lab-5-3 "3 bit pc relative unsigned offset" (PCREL-ADDR all-isas) 5 3 UINT
49f58d10
JB		 935 ((value pc) (sub SI value (add SI pc 2))) ; insert
936 ((value pc) (add SI value (add SI pc 2))) ; extract
937)
938(dnmf f-lab32-jmp-s "unsigned 3 bit pc relative offset" (PCREL-ADDR all-isas) UINT
939 (f-2-2 f-7-1)
e729279b
NC		 940 (sequence ((SI val)) ; insert
941 (set val (sub (sub (ifield f-lab32-jmp-s) pc) 2))
942 (set (ifield f-7-1) (and val #x1))
943 (set (ifield f-2-2) (srl val 1))
49f58d10
JB		 944 )
945 (sequence () ; extract
946 (set (ifield f-lab32-jmp-s) (add pc (add (or (sll (ifield f-2-2) 1)
947 (ifield f-7-1))
948 2)))
949 )
950)
951(df f-lab-8-8 "8 bit pc relative signed offset" (PCREL-ADDR all-isas) 8 8 INT
952 ((value pc) (sub SI value (add SI pc 1))) ; insert
953 ((value pc) (add SI value (add SI pc 1))) ; extract
954)
955(df f-lab-8-16 "16 bit pc relative signed offset" (PCREL-ADDR SIGN-OPT all-isas) 8 16 UINT
956 ((value pc) (or SI (sll (and (sub value (add pc 1)) #xff) 8)
957 (srl (and (sub value (add pc 1)) #xffff) 8)))
958 ((value pc) (add SI (or (srl (and value #xffff) 8)
959 (sra (sll (and value #xff) 24) 16)) (add pc 1)))
960 )
961(df f-lab-8-24 "24 bit absolute" (all-isas ABS-ADDR) 8 24 UINT
962 ((value pc) (or SI
963 (or (srl value 16) (and value #xff00))
964 (sll (and value #xff) 16)))
965 ((value pc) (or SI
966 (or (srl value 16) (and value #xff00))
967 (sll (and value #xff) 16)))
968 )
969(df f-lab-16-8 "8 bit pc relative signed offset" (PCREL-ADDR all-isas) 16 8 INT
970 ((value pc) (sub SI value (add SI pc 2))) ; insert
971 ((value pc) (add SI value (add SI pc 2))) ; extract
972)
973(df f-lab-24-8 "8 bit pc relative signed offset" (PCREL-ADDR all-isas) 24 8 INT
974 ((value pc) (sub SI value (add SI pc 2))) ; insert
975 ((value pc) (add SI value (add SI pc 2))) ; extract
976)
977(df f-lab-32-8 "8 bit pc relative signed offset" (PCREL-ADDR all-isas) 32 8 INT
978 ((value pc) (sub SI value (add SI pc 2))) ; insert
979 ((value pc) (add SI value (add SI pc 2))) ; extract
980)
981(df f-lab-40-8 "8 bit pc relative signed offset" (PCREL-ADDR all-isas) 40 8 INT
982 ((value pc) (sub SI value (add SI pc 2))) ; insert
983 ((value pc) (add SI value (add SI pc 2))) ; extract
984)
985
986;-------------------------------------------------------------
987; Condition codes
988;-------------------------------------------------------------
989
990(dnf f-cond16 "condition code" (all-isas) 12 4)
991(dnf f-cond16j-5 "condition code" (all-isas) 5 3)
992
993(dnmf f-cond32 "condition code" (all-isas) UINT
994 (f-9-1 f-13-3)
995 (sequence () ; insert
996 (set (ifield f-9-1) (and (srl (ifield f-cond32) 3) 1))
997 (set (ifield f-13-3) (and (ifield f-cond32) #x7))
998 )
999 (sequence () ; extract
1000 (set (ifield f-cond32) (or (sll (ifield f-9-1) 3)
1001 (ifield f-13-3)))
1002 )
1003)
1004
1005(dnmf f-cond32j "condition code" (all-isas) UINT
1006 (f-1-3 f-7-1)
1007 (sequence () ; insert
1008 (set (ifield f-1-3) (and (srl (ifield f-cond32j) 1) #x7))
1009 (set (ifield f-7-1) (and (ifield f-cond32j) #x1))
1010 )
1011 (sequence () ; extract
1012 (set (ifield f-cond32j) (or (sll (ifield f-1-3) 1)
1013 (ifield f-7-1)))
1014 )
1015)
1016\f
1017;=============================================================
1018; Hardware
1019;
1020(dnh h-pc "program counter" (PC all-isas) (pc USI) () () ())
1021
1022;-------------------------------------------------------------
1023; General registers
1024; The actual registers are 16 bits
1025;-------------------------------------------------------------
1026
1027(define-hardware
1028 (name h-gr)
1029 (comment "general 16 bit registers")
1030 (attrs all-isas CACHE-ADDR)
1031 (type register HI (4))
1032 (indices keyword "" (("r0" 0) ("r1" 1) ("r2" 2) ("r3" 3))))
1033
1034; Define different views of the grs as VIRTUAL with getter/setter specs
1035;
1036(define-hardware
1037 (name h-gr-QI)
1038 (comment "general 8 bit registers")
1039 (attrs all-isas VIRTUAL)
1040 (type register QI (4))
1041 (indices keyword "" (("r0l" 0) ("r0h" 1) ("r1l" 2) ("r1h" 3)))
1042 (get (index) (and (if SI (mod index 2)
1043 (srl (reg h-gr (div index 2)) 8)
1044 (reg h-gr (div index 2)))
1045 #xff))
1046 (set (index newval) (set (reg h-gr (div index 2))
1047 (if SI (mod index 2)
1048 (or (and (reg h-gr (div index 2)) #xff)
1049 (sll (and newval #xff) 8))
1050 (or (and (reg h-gr (div index 2)) #xff00)
1051 (and newval #xff))))))
1052
1053(define-hardware
1054 (name h-gr-HI)
1055 (comment "general 16 bit registers")
1056 (attrs all-isas VIRTUAL)
1057 (type register HI (4))
1058 (indices keyword "" (("r0" 0) ("r1" 1) ("r2" 2) ("r3" 3)))
1059 (get (index) (reg h-gr index))
1060 (set (index newval) (set (reg h-gr index) newval)))
1061
1062(define-hardware
1063 (name h-gr-SI)
1064 (comment "general 32 bit registers")
1065 (attrs all-isas VIRTUAL)
1066 (type register SI (2))
1067 (indices keyword "" (("r2r0" 0) ("r3r1" 1)))
1068 (get (index) (or SI
1069 (and (reg h-gr index) #xffff)
1070 (and (sll (reg h-gr (add index 2)) 16) #xffff0000)))
1071 (set (index newval) (sequence ()
1072 (set (reg h-gr index) (and newval #xffff))
1073 (set (reg h-gr (add index 2)) (srl newval 16)))))
1074
1075(define-hardware
1076 (name h-gr-ext-QI)
1077 (comment "general 16 bit registers")
1078 (attrs all-isas VIRTUAL)
1079 (type register HI (2))
1080 (indices keyword "" (("r0l" 0) ("r1l" 1)))
1081 (get (index) (reg h-gr-QI (mul index 2)))
1082 (set (index newval) (set (reg h-gr (mul index 2)) newval)))
1083
1084(define-hardware
1085 (name h-gr-ext-HI)
1086 (comment "general 16 bit registers")
1087 (attrs all-isas VIRTUAL)
1088 (type register SI (2))
1089 (indices keyword "" (("r0" 0) ("r1" 1)))
1090 (get (index) (reg h-gr (mul index 2)))
1091 (set (index newval) (set (reg h-gr-SI index) newval)))
1092
1093(define-hardware
1094 (name h-r0l)
1095 (comment "r0l register")
1096 (attrs all-isas VIRTUAL)
1097 (type register QI)
1098 (indices keyword "" (("r0l" 0)))
1099 (get () (reg h-gr-QI 0))
1100 (set (newval) (set (reg h-gr-QI 0) newval)))
1101
1102(define-hardware
1103 (name h-r0h)
1104 (comment "r0h register")
1105 (attrs all-isas VIRTUAL)
1106 (type register QI)
1107 (indices keyword "" (("r0h" 0)))
1108 (get () (reg h-gr-QI 1))
1109 (set (newval) (set (reg h-gr-QI 1) newval)))
1110
1111(define-hardware
1112 (name h-r1l)
1113 (comment "r1l register")
1114 (attrs all-isas VIRTUAL)
1115 (type register QI)
1116 (indices keyword "" (("r1l" 0)))
1117 (get () (reg h-gr-QI 2))
1118 (set (newval) (set (reg h-gr-QI 2) newval)))
1119
1120(define-hardware
1121 (name h-r1h)
1122 (comment "r1h register")
1123 (attrs all-isas VIRTUAL)
1124 (type register QI)
1125 (indices keyword "" (("r1h" 0)))
1126 (get () (reg h-gr-QI 3))
1127 (set (newval) (set (reg h-gr-QI 3) newval)))
1128
1129(define-hardware
1130 (name h-r0)
1131 (comment "r0 register")
1132 (attrs all-isas VIRTUAL)
1133 (type register HI)
1134 (indices keyword "" (("r0" 0)))
1135 (get () (reg h-gr 0))
1136 (set (newval) (set (reg h-gr 0) newval)))
1137
1138(define-hardware
1139 (name h-r1)
1140 (comment "r1 register")
1141 (attrs all-isas VIRTUAL)
1142 (type register HI)
1143 (indices keyword "" (("r1" 0)))
1144 (get () (reg h-gr 1))
1145 (set (newval) (set (reg h-gr 1) newval)))
1146
1147(define-hardware
1148 (name h-r2)
1149 (comment "r2 register")
1150 (attrs all-isas VIRTUAL)
1151 (type register HI)
1152 (indices keyword "" (("r2" 0)))
1153 (get () (reg h-gr 2))
1154 (set (newval) (set (reg h-gr 2) newval)))
1155
1156(define-hardware
1157 (name h-r3)
1158 (comment "r3 register")
1159 (attrs all-isas VIRTUAL)
1160 (type register HI)
1161 (indices keyword "" (("r3" 0)))
1162 (get () (reg h-gr 3))
1163 (set (newval) (set (reg h-gr 3) newval)))
1164
1165(define-hardware
1166 (name h-r0l-r0h)
1167 (comment "r0l or r0h")
1168 (attrs all-isas VIRTUAL)
1169 (type register QI (2))
1170 (indices keyword "" (("r0l" 0) ("r0h" 1)))
1171 (get (index) (reg h-gr-QI index))
1172 (set (index newval) (set (reg h-gr-QI index) newval)))
1173
1174(define-hardware
1175 (name h-r2r0)
1176 (comment "r2r0 register")
1177 (attrs all-isas VIRTUAL)
1178 (type register SI)
1179 (indices keyword "" (("r2r0" 0)))
1180 (get () (or (sll (reg h-gr 2) 16) (reg h-gr 0)))
1181 (set (newval)
1182 (sequence ()
1183 (set (reg h-gr 0) newval)
1184 (set (reg h-gr 2) (sra newval 16)))))
1185
1186(define-hardware
1187 (name h-r3r1)
1188 (comment "r3r1 register")
1189 (attrs all-isas VIRTUAL)
1190 (type register SI)
1191 (indices keyword "" (("r3r1" 0)))
1192 (get () (or (sll (reg h-gr 3) 16) (reg h-gr 1)))
1193 (set (newval)
1194 (sequence ()
1195 (set (reg h-gr 1) newval)
1196 (set (reg h-gr 3) (sra newval 16)))))
1197
1198(define-hardware
1199 (name h-r1r2r0)
1200 (comment "r1r2r0 register")
1201 (attrs all-isas VIRTUAL)
1202 (type register DI)
1203 (indices keyword "" (("r1r2r0" 0)))
1204 (get () (or DI (sll DI (reg h-gr 1) 32) (or (sll (reg h-gr 2) 16) (reg h-gr 0))))
1205 (set (newval)
1206 (sequence ()
1207 (set (reg h-gr 0) newval)
1208 (set (reg h-gr 2) (sra newval 16))
1209 (set (reg h-gr 1) (sra newval 32)))))
1210
1211;-------------------------------------------------------------
1212; Address registers
1213;-------------------------------------------------------------
1214
1215(define-hardware
1216 (name h-ar)
1217 (comment "address registers")
1218 (attrs all-isas)
1219 (type register USI (2))
1220 (indices keyword "" (("a0" 0) ("a1" 1)))
1221 (get (index) (c-call USI "h_ar_get_handler" index))
1222 (set (index newval) (c-call VOID "h_ar_set_handler" index newval)))
1223
1224; Define different views of the ars as VIRTUAL with getter/setter specs
1225(define-hardware
1226 (name h-ar-QI)
1227 (comment "8 bit view of address register")
1228 (attrs all-isas VIRTUAL)
1229 (type register QI (2))
1230 (indices keyword "" (("a0" 0) ("a1" 1)))
1231 (get (index) (reg h-ar index))
1232 (set (index newval) (set (reg h-ar index) newval)))
1233
1234(define-hardware
1235 (name h-ar-HI)
1236 (comment "16 bit view of address register")
1237 (attrs all-isas VIRTUAL)
1238 (type register HI (2))
1239 (indices keyword "" (("a0" 0) ("a1" 1)))
1240 (get (index) (reg h-ar index))
1241 (set (index newval) (set (reg h-ar index) newval)))
1242
1243(define-hardware
1244 (name h-ar-SI)
1245 (comment "32 bit view of address register")
1246 (attrs all-isas VIRTUAL)
1247 (type register SI)
1248 (indices keyword "" (("a1a0" 0)))
1249 (get () (or SI (sll SI (ext SI (reg h-ar 1)) 16) (ext SI (reg h-ar 0))))
1250 (set (newval) (sequence ()
1251 (set (reg h-ar 0) (and newval #xffff))
1252 (set (reg h-ar 1) (and (srl newval 16) #xffff)))))
1253
1254(define-hardware
1255 (name h-a0)
1256 (comment "16 bit view of address register")
1257 (attrs all-isas VIRTUAL)
1258 (type register HI)
1259 (indices keyword "" (("a0" 0)))
1260 (get () (reg h-ar 0))
1261 (set (newval) (set (reg h-ar 0) newval)))
1262
1263(define-hardware
1264 (name h-a1)
1265 (comment "16 bit view of address register")
1266 (attrs all-isas VIRTUAL)
1267 (type register HI)
1268 (indices keyword "" (("a1" 1)))
1269 (get () (reg h-ar 1))
1270 (set (newval) (set (reg h-ar 1) newval)))
1271
1272; SB Register
1273(define-hardware
1274 (name h-sb)
1275 (comment "SB register")
1276 (attrs all-isas)
1277 (type register USI)
1278 (get () (c-call USI "h_sb_get_handler"))
1279 (set (newval) (c-call VOID "h_sb_set_handler" newval))
1280)
1281
1282; FB Register
1283(define-hardware
1284 (name h-fb)
1285 (comment "FB register")
1286 (attrs all-isas)
1287 (type register USI)
1288 (get () (c-call USI "h_fb_get_handler"))
1289 (set (newval) (c-call VOID "h_fb_set_handler" newval))
1290)
1291
1292; SP Register
1293(define-hardware
1294 (name h-sp)
1295 (comment "SP register")
1296 (attrs all-isas)
1297 (type register USI)
1298 (get () (c-call USI "h_sp_get_handler"))
1299 (set (newval) (c-call VOID "h_sp_set_handler" newval))
1300)
1301
1302;-------------------------------------------------------------
1303; condition-code bits
1304;-------------------------------------------------------------
1305
1306(define-hardware
1307 (name h-sbit)
1308 (comment "sign bit")
1309 (attrs all-isas)
1310 (type register BI)
1311)
1312
1313(define-hardware
1314 (name h-zbit)
1315 (comment "zero bit")
1316 (attrs all-isas)
1317 (type register BI)
1318)
1319
1320(define-hardware
1321 (name h-obit)
1322 (comment "overflow bit")
1323 (attrs all-isas)
1324 (type register BI)
1325)
1326
1327(define-hardware
1328 (name h-cbit)
1329 (comment "carry bit")
1330 (attrs all-isas)
1331 (type register BI)
1332)
1333
1334(define-hardware
1335 (name h-ubit)
1336 (comment "stack pointer select bit")
1337 (attrs all-isas)
1338 (type register BI)
1339)
1340
1341(define-hardware
1342 (name h-ibit)
1343 (comment "interrupt enable bit")
1344 (attrs all-isas)
1345 (type register BI)
1346)
1347
1348(define-hardware
1349 (name h-bbit)
1350 (comment "register bank select bit")
1351 (attrs all-isas)
1352 (type register BI)
1353)
1354
1355(define-hardware
1356 (name h-dbit)
1357 (comment "debug bit")
1358 (attrs all-isas)
1359 (type register BI)
1360)
1361
1362(define-hardware
1363 (name h-dct0)
1364 (comment "dma transfer count 000")
1365 (attrs all-isas)
1366 (type register UHI)
1367)
1368(define-hardware
1369 (name h-dct1)
1370 (comment "dma transfer count 001")
1371 (attrs all-isas)
1372 (type register UHI)
1373)
1374(define-hardware
1375 (name h-svf)
1376 (comment "save flag 011")
1377 (attrs all-isas)
1378 (type register UHI)
1379)
1380(define-hardware
1381 (name h-drc0)
1382 (comment "dma transfer count reload 100")
1383 (attrs all-isas)
1384 (type register UHI)
1385)
1386(define-hardware
1387 (name h-drc1)
1388 (comment "dma transfer count reload 101")
1389 (attrs all-isas)
1390 (type register UHI)
1391)
1392(define-hardware
1393 (name h-dmd0)
1394 (comment "dma mode 110")
1395 (attrs all-isas)
1396 (type register UQI)
1397)
1398(define-hardware
1399 (name h-dmd1)
1400 (comment "dma mode 111")
1401 (attrs all-isas)
1402 (type register UQI)
1403)
1404(define-hardware
1405 (name h-intb)
1406 (comment "interrupt table 000")
1407 (attrs all-isas)
1408 (type register USI)
1409)
1410(define-hardware
1411 (name h-svp)
1412 (comment "save pc 100")
1413 (attrs all-isas)
1414 (type register UHI)
1415)
1416(define-hardware
1417 (name h-vct)
1418 (comment "vector 101")
1419 (attrs all-isas)
1420 (type register USI)
1421)
1422(define-hardware
1423 (name h-isp)
1424 (comment "interrupt stack ptr 111")
1425 (attrs all-isas)
1426 (type register USI)
1427)
1428(define-hardware
1429 (name h-dma0)
1430 (comment "dma mem addr 010")
1431 (attrs all-isas)
1432 (type register USI)
1433)
1434(define-hardware
1435 (name h-dma1)
1436 (comment "dma mem addr 011")
1437 (attrs all-isas)
1438 (type register USI)
1439)
1440(define-hardware
1441 (name h-dra0)
1442 (comment "dma mem addr reload 100")
1443 (attrs all-isas)
1444 (type register USI)
1445)
1446(define-hardware
1447 (name h-dra1)
1448 (comment "dma mem addr reload 101")
1449 (attrs all-isas)
1450 (type register USI)
1451)
1452(define-hardware
1453 (name h-dsa0)
1454 (comment "dma sfr addr 110")
1455 (attrs all-isas)
1456 (type register USI)
1457)
1458(define-hardware
1459 (name h-dsa1)
1460 (comment "dma sfr addr 111")
1461 (attrs all-isas)
1462 (type register USI)
1463)
1464
1465;-------------------------------------------------------------
1466; Condition code operand hardware
1467;-------------------------------------------------------------
1468
1469(define-hardware
1470 (name h-cond16)
1471 (comment "condition code hardware for m16c")
1472 (attrs m16c-isa MACH16)
1473 (type immediate UQI)
1474 (values keyword ""
1475 (("geu" #x00) ("c" #x00)
1476 ("gtu" #x01)
1477 ("eq" #x02) ("z" #x02)
1478 ("n" #x03)
1479 ("le" #x04)
1480 ("o" #x05)
1481 ("ge" #x06)
1482 ("ltu" #xf8) ("nc" #xf8)
1483 ("leu" #xf9)
1484 ("ne" #xfa) ("nz" #xfa)
1485 ("pz" #xfb)
1486 ("gt" #xfc)
1487 ("no" #xfd)
1488 ("lt" #xfe)
1489 )
1490 )
1491)
1492(define-hardware
1493 (name h-cond16c)
1494 (comment "condition code hardware for m16c")
1495 (attrs m16c-isa MACH16)
1496 (type immediate UQI)
1497 (values keyword ""
1498 (("geu" #x00) ("c" #x00)
1499 ("gtu" #x01)
1500 ("eq" #x02) ("z" #x02)
1501 ("n" #x03)
1502 ("ltu" #x04) ("nc" #x04)
1503 ("leu" #x05)
1504 ("ne" #x06) ("nz" #x06)
1505 ("pz" #x07)
1506 ("le" #x08)
1507 ("o" #x09)
1508 ("ge" #x0a)
1509 ("gt" #x0c)
1510 ("no" #x0d)
1511 ("lt" #x0e)
1512 )
1513 )
1514)
1515(define-hardware
1516 (name h-cond16j)
1517 (comment "condition code hardware for m16c")
1518 (attrs m16c-isa MACH16)
1519 (type immediate UQI)
1520 (values keyword ""
1521 (("le" #x08)
1522 ("o" #x09)
1523 ("ge" #x0a)
1524 ("gt" #x0c)
1525 ("no" #x0d)
1526 ("lt" #x0e)
1527 )
1528 )
1529)
1530(define-hardware
1531 (name h-cond16j-5)
1532 (comment "condition code hardware for m16c")
1533 (attrs m16c-isa MACH16)
1534 (type immediate UQI)
1535 (values keyword ""
1536 (("geu" #x00) ("c" #x00)
1537 ("gtu" #x01)
1538 ("eq" #x02) ("z" #x02)
1539 ("n" #x03)
1540 ("ltu" #x04) ("nc" #x04)
1541 ("leu" #x05)
1542 ("ne" #x06) ("nz" #x06)
1543 ("pz" #x07)
1544 )
1545 )
1546)
1547
1548(define-hardware
1549 (name h-cond32)
1550 (comment "condition code hardware for m32c")
1551 (attrs m32c-isa MACH32)
1552 (type immediate UQI)
1553 (values keyword ""
1554 (("ltu" #x00) ("nc" #x00)
1555 ("leu" #x01)
1556 ("ne" #x02) ("nz" #x02)
1557 ("pz" #x03)
1558 ("no" #x04)
1559 ("gt" #x05)
1560 ("ge" #x06)
1561 ("geu" #x08) ("c" #x08)
1562 ("gtu" #x09)
1563 ("eq" #x0a) ("z" #x0a)
1564 ("n" #x0b)
1565 ("o" #x0c)
1566 ("le" #x0d)
1567 ("lt" #x0e)
1568 )
1569 )
1570)
1571
1572(define-hardware
1573 (name h-cr1-32)
1574 (comment "control registers")
1575 (attrs m32c-isa MACH32)
1576 (type immediate UQI)
1577 (values keyword "" (("dct0" 0) ("dct1" 1) ("flg" 2) ("svf" 3) ("drc0" 4)
1578 ("drc1" 5) ("dmd0" 6) ("dmd1" 7))))
1579(define-hardware
1580 (name h-cr2-32)
1581 (comment "control registers")
1582 (attrs m32c-isa MACH32)
1583 (type immediate UQI)
1584 (values keyword "" (("intb" 0) ("sp" 1) ("sb" 2) ("fb" 3) ("svp" 4)
1585 ("vct" 5) ("isp" 7))))
1586
1587(define-hardware
1588 (name h-cr3-32)
1589 (comment "control registers")
1590 (attrs m32c-isa MACH32)
1591 (type immediate UQI)
1592 (values keyword "" (("dma0" 2) ("dma1" 3) ("dra0" 4)
1593 ("dra1" 5) ("dsa0" 6) ("dsa1" 7))))
1594(define-hardware
1595 (name h-cr-16)
1596 (comment "control registers")
1597 (attrs m16c-isa MACH16)
1598 (type immediate UQI)
1599 (values keyword "" (("intbl" 1) ("intbh" 2) ("flg" 3) ("isp" 4)
1600 ("sp" 5) ("sb" 6) ("fb" 7))))
1601
1602(define-hardware
1603 (name h-flags)
1604 (comment "flag hardware for m32c")
1605 (attrs all-isas)
1606 (type immediate UQI)
1607 (values keyword ""
1608 (("c" #x0)
1609 ("d" #x1)
1610 ("z" #x2)
1611 ("s" #x3)
1612 ("b" #x4)
1613 ("o" #x5)
1614 ("i" #x6)
1615 ("u" #x7)
1616 )
1617 )
1618)
1619
1620;-------------------------------------------------------------
1621; Misc helper hardware
1622;-------------------------------------------------------------
1623
1624(define-hardware
1625 (name h-shimm)
1626 (comment "shift immediate")
1627 (attrs all-isas)
1628 (type immediate (INT 4))
1629 (values keyword "" (("1" 0) ("2" 1) ("3" 2) ("4" 3) ("5" 4) ("6" 5) ("7" 6)
1630 ("8" 7) ("-1" -8) ("-2" -7) ("-3" -6) ("-4" -5) ("-5" -4)
1631 ("-6" -3) ("-7" -2) ("-8" -1)
1632 )))
1633(define-hardware
1634 (name h-bit-index)
1635 (comment "bit index for the next insn")
1636 (attrs m32c-isa MACH32)
1637 (type register UHI)
1638)
1639(define-hardware
1640 (name h-src-index)
1641 (comment "source index for the next insn")
1642 (attrs m32c-isa MACH32)
1643 (type register UHI)
1644)
1645(define-hardware
1646 (name h-dst-index)
1647 (comment "destination index for the next insn")
1648 (attrs m32c-isa MACH32)
1649 (type register UHI)
1650)
1651(define-hardware
1652 (name h-src-indirect)
1653 (comment "indirect src for the next insn")
1654 (attrs all-isas)
1655 (type register UHI)
1656)
1657(define-hardware
1658 (name h-dst-indirect)
1659 (comment "indirect dst for the next insn")
1660 (attrs all-isas)
1661 (type register UHI)
1662)
1663(define-hardware
1664 (name h-none)
1665 (comment "for storing unused values")
1666 (attrs m32c-isa MACH32)
1667 (type register SI)
1668)
1669\f
1670;=============================================================
1671; Operands
1672;-------------------------------------------------------------
1673; Source Registers
1674;-------------------------------------------------------------
1675
1676(dnop Src16RnQI "general register QI view" (MACH16 m16c-isa) h-gr-QI f-src16-rn)
1677(dnop Src16RnHI "general register QH view" (MACH16 m16c-isa) h-gr-HI f-src16-rn)
1678
1679(dnop Src32RnUnprefixedQI "general register QI view" (MACH32 m32c-isa) h-gr-QI f-src32-rn-unprefixed-QI)
1680(dnop Src32RnUnprefixedHI "general register HI view" (MACH32 m32c-isa) h-gr-HI f-src32-rn-unprefixed-HI)
1681(dnop Src32RnUnprefixedSI "general register SI view" (MACH32 m32c-isa) h-gr-SI f-src32-rn-unprefixed-SI)
1682
1683(dnop Src32RnPrefixedQI "general register QI view" (MACH32 m32c-isa) h-gr-QI f-src32-rn-prefixed-QI)
1684(dnop Src32RnPrefixedHI "general register HI view" (MACH32 m32c-isa) h-gr-HI f-src32-rn-prefixed-HI)
1685(dnop Src32RnPrefixedSI "general register SI view" (MACH32 m32c-isa) h-gr-SI f-src32-rn-prefixed-SI)
1686
1687(dnop Src16An "address register" (MACH16 m16c-isa) h-ar f-src16-an)
1688(dnop Src16AnQI "address register QI view" (MACH16 m16c-isa) h-ar-QI f-src16-an)
1689(dnop Src16AnHI "address register HI view" (MACH16 m16c-isa) h-ar-HI f-src16-an)
1690
1691(dnop Src32AnUnprefixed "address register" (MACH32 m32c-isa) h-ar f-src32-an-unprefixed)
1692(dnop Src32AnUnprefixedQI "address register QI view" (MACH32 m32c-isa) h-ar-QI f-src32-an-unprefixed)
1693(dnop Src32AnUnprefixedHI "address register HI view" (MACH32 m32c-isa) h-ar-HI f-src32-an-unprefixed)
1694(dnop Src32AnUnprefixedSI "address register SI view" (MACH32 m32c-isa) h-ar f-src32-an-unprefixed)
1695
1696(dnop Src32AnPrefixed "address register" (MACH32 m32c-isa) h-ar f-src32-an-prefixed)
1697(dnop Src32AnPrefixedQI "address register QI view" (MACH32 m32c-isa) h-ar-QI f-src32-an-prefixed)
1698(dnop Src32AnPrefixedHI "address register HI view" (MACH32 m32c-isa) h-ar-HI f-src32-an-prefixed)
1699(dnop Src32AnPrefixedSI "address register SI view" (MACH32 m32c-isa) h-ar f-src32-an-prefixed)
1700
1701; Destination Registers
1702;
1703(dnop Dst16RnQI "general register QI view" (MACH16 m16c-isa) h-gr-QI f-dst16-rn)
1704(dnop Dst16RnHI "general register HI view" (MACH16 m16c-isa) h-gr-HI f-dst16-rn)
1705(dnop Dst16RnSI "general register SI view" (MACH16 m16c-isa) h-gr-SI f-dst16-rn)
1706(dnop Dst16RnExtQI "general register QI/HI view for 'ext' insns" (MACH16 m16c-isa) h-gr-ext-QI f-dst16-rn-ext)
1707
1708(dnop Dst32R0QI-S "general register QI view" (MACH32 m32c-isa) h-r0l f-nil)
1709(dnop Dst32R0HI-S "general register HI view" (MACH32 m32c-isa) h-r0 f-nil)
1710
1711(dnop Dst32RnUnprefixedQI "general register QI view" (MACH32 m32c-isa) h-gr-QI f-dst32-rn-unprefixed-QI)
1712(dnop Dst32RnUnprefixedHI "general register HI view" (MACH32 m32c-isa) h-gr-HI f-dst32-rn-unprefixed-HI)
1713(dnop Dst32RnUnprefixedSI "general register SI view" (MACH32 m32c-isa) h-gr-SI f-dst32-rn-unprefixed-SI)
1714(dnop Dst32RnExtUnprefixedQI "general register QI view" (MACH32 m32c-isa) h-gr-ext-QI f-dst32-rn-ext-unprefixed)
1715(dnop Dst32RnExtUnprefixedHI "general register HI view" (MACH32 m32c-isa) h-gr-ext-HI f-dst32-rn-ext-unprefixed)
1716
1717(dnop Dst32RnPrefixedQI "general register QI view" (MACH32 m32c-isa) h-gr-QI f-dst32-rn-prefixed-QI)
1718(dnop Dst32RnPrefixedHI "general register HI view" (MACH32 m32c-isa) h-gr-HI f-dst32-rn-prefixed-HI)
1719(dnop Dst32RnPrefixedSI "general register SI view" (MACH32 m32c-isa) h-gr-SI f-dst32-rn-prefixed-SI)
1720
1721(dnop Dst16RnQI-S "general register QI view" (MACH16 m16c-isa) h-r0l-r0h f-dst16-rn-QI-s)
1722
1723(dnop Dst16AnQI-S "address register QI view" (MACH16 m16c-isa) h-ar-QI f-dst16-rn-QI-s)
1724
1725(dnop Bit16Rn "general register bit view" (MACH16 m16c-isa) h-gr-HI f-dst16-rn)
1726
1727(dnop Bit32RnPrefixed "general register bit view" (MACH32 m32c-isa) h-gr-QI f-dst32-rn-prefixed-QI)
1728(dnop Bit32RnUnprefixed "general register bit view" (MACH32 m32c-isa) h-gr-QI f-dst32-rn-unprefixed-QI)
1729
1730(dnop R0 "r0" (all-isas) h-r0 f-nil)
1731(dnop R1 "r1" (all-isas) h-r1 f-nil)
1732(dnop R2 "r2" (all-isas) h-r2 f-nil)
1733(dnop R3 "r3" (all-isas) h-r3 f-nil)
1734(dnop R0l "r0l" (all-isas) h-r0l f-nil)
1735(dnop R0h "r0h" (all-isas) h-r0h f-nil)
1736(dnop R2R0 "r2r0" (all-isas) h-r2r0 f-nil)
1737(dnop R3R1 "r3r1" (all-isas) h-r3r1 f-nil)
1738(dnop R1R2R0 "r1r2r0" (all-isas) h-r1r2r0 f-nil)
1739
1740(dnop Dst16An "address register" (MACH16 m16c-isa) h-ar f-dst16-an)
1741(dnop Dst16AnQI "address register QI view" (MACH16 m16c-isa) h-ar-QI f-dst16-an)
1742(dnop Dst16AnHI "address register HI view" (MACH16 m16c-isa) h-ar-HI f-dst16-an)
1743(dnop Dst16AnSI "address register SI view" (MACH16 m16c-isa) h-ar-SI f-dst16-an)
1744(dnop Dst16An-S "address register HI view" (MACH16 m16c-isa) h-ar-HI f-dst16-an-s)
1745
1746(dnop Dst32AnUnprefixed "address register" (MACH32 m32c-isa) h-ar f-dst32-an-unprefixed)
1747(dnop Dst32AnUnprefixedQI "address register QI view" (MACH32 m32c-isa) h-ar-QI f-dst32-an-unprefixed)
1748(dnop Dst32AnUnprefixedHI "address register HI view" (MACH32 m32c-isa) h-ar-HI f-dst32-an-unprefixed)
1749(dnop Dst32AnUnprefixedSI "address register SI view" (MACH32 m32c-isa) h-ar f-dst32-an-unprefixed)
1750
1751(dnop Dst32AnExtUnprefixed "address register" (MACH32 m32c-isa) h-ar f-dst32-an-unprefixed)
1752
1753(dnop Dst32AnPrefixed "address register" (MACH32 m32c-isa) h-ar f-dst32-an-prefixed)
1754(dnop Dst32AnPrefixedQI "address register QI view" (MACH32 m32c-isa) h-ar-QI f-dst32-an-prefixed)
1755(dnop Dst32AnPrefixedHI "address register HI view" (MACH32 m32c-isa) h-ar-HI f-dst32-an-prefixed)
1756(dnop Dst32AnPrefixedSI "address register SI view" (MACH32 m32c-isa) h-ar f-dst32-an-prefixed)
1757
1758(dnop Bit16An "address register bit view" (MACH16 m16c-isa) h-ar f-dst16-an)
1759
1760(dnop Bit32AnPrefixed "address register bit" (MACH32 m32c-isa) h-ar f-dst32-an-prefixed)
1761(dnop Bit32AnUnprefixed "address register bit" (MACH32 m32c-isa) h-ar f-dst32-an-unprefixed)
1762
1763(dnop A0 "a0" (all-isas) h-a0 f-nil)
1764(dnop A1 "a1" (all-isas) h-a1 f-nil)
1765
1766(dnop sb "SB register" (all-isas SEM-ONLY) h-sb f-nil)
1767(dnop fb "FB register" (all-isas SEM-ONLY) h-fb f-nil)
1768(dnop sp "SP register" (all-isas SEM-ONLY) h-sp f-nil)
1769
1770(define-full-operand SrcDst16-r0l-r0h-S-normal "r0l/r0h pair" (MACH16 m16c-isa)
1771 h-sint DFLT f-5-1
1772 ((parse "r0l_r0h") (print "r0l_r0h")) () ()
1773)
1774
1775(define-full-operand Regsetpop "popm regset" (all-isas) h-uint
1776 DFLT f-8-8 ((parse "pop_regset") (print "pop_regset")) () ())
1777(define-full-operand Regsetpush "pushm regset" (all-isas) h-uint
1778 DFLT f-8-8 ((parse "push_regset") (print "push_regset")) () ())
1779
1780(dnop Rn16-push-S "r0[lh]" (MACH16 m16c-isa) h-gr-QI f-4-1)
1781(dnop An16-push-S "a[01]" (MACH16 m16c-isa) h-ar-HI f-4-1)
1782
1783;-------------------------------------------------------------
1784; Offsets and absolutes
1785;-------------------------------------------------------------
1786
1787(define-full-operand Dsp-8-u6 "unsigned 6 bit displacement at offset 8 bits" (all-isas)
1788 h-uint DFLT f-dsp-8-u6
1789 ((parse "unsigned6")) () ()
1790)
1791(define-full-operand Dsp-8-u8 "unsigned 8 bit displacement at offset 8 bits" (all-isas)
1792 h-uint DFLT f-dsp-8-u8
1793 ((parse "unsigned8")) () ()
1794)
1795(define-full-operand Dsp-8-u16 "unsigned 16 bit displacement at offset 8 bits" (all-isas)
1796 h-uint DFLT f-dsp-8-u16
1797 ((parse "unsigned16")) () ()
1798)
1799(define-full-operand Dsp-8-s8 "signed 8 bit displacement at offset 8 bits" (all-isas)
1800 h-sint DFLT f-dsp-8-s8
1801 ((parse "signed8")) () ()
1802)
f75eb1c0
DD		 1803(define-full-operand Dsp-8-s24 "signed 24 bit displacement at offset 8 bits" (all-isas)
1804 h-sint DFLT f-dsp-8-s24
1805 ((parse "signed24")) () ()
1806)
e729279b
NC		 1807(define-full-operand Dsp-8-u24 "unsigned 24 bit displacement at offset 8 bits" (all-isas)
1808 h-uint DFLT f-dsp-8-u24
1809 ((parse "unsigned24")) () ()
1810)
49f58d10
JB		 1811(define-full-operand Dsp-10-u6 "unsigned 6 bit displacement at offset 10 bits" (all-isas)
1812 h-uint DFLT f-dsp-10-u6
1813 ((parse "unsigned6")) () ()
1814)
1815(define-full-operand Dsp-16-u8 "unsigned 8 bit displacement at offset 16 bits" (all-isas)
1816 h-uint DFLT f-dsp-16-u8
1817 ((parse "unsigned8")) () ()
1818)
1819(define-full-operand Dsp-16-u16 "unsigned 16 bit displacement at offset 16 bits" (all-isas)
1820 h-uint DFLT f-dsp-16-u16
1821 ((parse "unsigned16")) () ()
1822)
1823(define-full-operand Dsp-16-u20 "unsigned 20 bit displacement at offset 16 bits" (all-isas)
1824 h-uint DFLT f-dsp-16-u24
1825 ((parse "unsigned20")) () ()
1826)
1827(define-full-operand Dsp-16-u24 "unsigned 24 bit displacement at offset 16 bits" (all-isas)
1828 h-uint DFLT f-dsp-16-u24
1829 ((parse "unsigned24")) () ()
1830)
1831(define-full-operand Dsp-16-s8 "signed 8 bit displacement at offset 16 bits" (all-isas)
1832 h-sint DFLT f-dsp-16-s8
1833 ((parse "signed8")) () ()
1834)
1835(define-full-operand Dsp-16-s16 "signed 16 bit displacement at offset 16 bits" (all-isas)
1836 h-sint DFLT f-dsp-16-s16
1837 ((parse "signed16")) () ()
1838)
1839(define-full-operand Dsp-24-u8 "unsigned 8 bit displacement at offset 24 bits" (all-isas)
1840 h-uint DFLT f-dsp-24-u8
1841 ((parse "unsigned8")) () ()
1842)
1843(define-full-operand Dsp-24-u16 "unsigned 16 bit displacement at offset 24 bits" (all-isas)
1844 h-uint DFLT f-dsp-24-u16
1845 ((parse "unsigned16")) () ()
1846)
1847(define-full-operand Dsp-24-u20 "unsigned 20 bit displacement at offset 24 bits" (all-isas)
1848 h-uint DFLT f-dsp-24-u24
1849 ((parse "unsigned20")) () ()
1850)
1851(define-full-operand Dsp-24-u24 "unsigned 24 bit displacement at offset 24 bits" (all-isas)
1852 h-uint DFLT f-dsp-24-u24
1853 ((parse "unsigned24")) () ()
1854)
1855(define-full-operand Dsp-24-s8 "signed 8 bit displacement at offset 24 bits" (all-isas)
1856 h-sint DFLT f-dsp-24-s8
1857 ((parse "signed8")) () ()
1858)
1859(define-full-operand Dsp-24-s16 "signed 16 bit displacement at offset 24 bits" (all-isas)
1860 h-sint DFLT f-dsp-24-s16
1861 ((parse "signed16")) () ()
1862)
1863(define-full-operand Dsp-32-u8 "unsigned 8 bit displacement at offset 32 bits" (all-isas)
1864 h-uint DFLT f-dsp-32-u8
1865 ((parse "unsigned8")) () ()
1866)
1867(define-full-operand Dsp-32-u16 "unsigned 16 bit displacement at offset 32 bits" (all-isas)
1868 h-uint DFLT f-dsp-32-u16
1869 ((parse "unsigned16")) () ()
1870)
1871(define-full-operand Dsp-32-u24 "unsigned 24 bit displacement at offset 32 bits" (all-isas)
1872 h-uint DFLT f-dsp-32-u24
1873 ((parse "unsigned24")) () ()
1874)
1875(define-full-operand Dsp-32-u20 "unsigned 20 bit displacement at offset 32 bits" (all-isas)
1876 h-uint DFLT f-dsp-32-u24
1877 ((parse "unsigned20")) () ()
1878)
1879(define-full-operand Dsp-32-s8 "signed 8 bit displacement at offset 32 bits" (all-isas)
1880 h-sint DFLT f-dsp-32-s8
1881 ((parse "signed8")) () ()
1882)
1883(define-full-operand Dsp-32-s16 "signed 16 bit displacement at offset 32 bits" (all-isas)
1884 h-sint DFLT f-dsp-32-s16
1885 ((parse "signed16")) () ()
1886)
1887(define-full-operand Dsp-40-u8 "unsigned 8 bit displacement at offset 40 bits" (all-isas)
1888 h-uint DFLT f-dsp-40-u8
1889 ((parse "unsigned8")) () ()
1890)
1891(define-full-operand Dsp-40-s8 "signed 8 bit displacement at offset 40 bits" (all-isas)
e729279b 1892 h-sint DFLT f-dsp-40-s8
49f58d10
JB		 1893 ((parse "signed8")) () ()
1894)
1895(define-full-operand Dsp-40-u16 "unsigned 16 bit displacement at offset 40 bits" (all-isas)
1896 h-uint DFLT f-dsp-40-u16
1897 ((parse "unsigned16")) () ()
1898)
1899(define-full-operand Dsp-40-s16 "signed 16 bit displacement at offset 40 bits" (all-isas)
e729279b 1900 h-sint DFLT f-dsp-40-s16
49f58d10
JB		 1901 ((parse "signed16")) () ()
1902)
75b06e7b
DD		 1903(define-full-operand Dsp-40-u20 "unsigned 20 bit displacement at offset 40 bits" (all-isas)
1904 h-uint DFLT f-dsp-40-u20
1905 ((parse "unsigned20")) () ()
1906)
49f58d10
JB		 1907(define-full-operand Dsp-40-u24 "unsigned 24 bit displacement at offset 40 bits" (all-isas)
1908 h-uint DFLT f-dsp-40-u24
1909 ((parse "unsigned24")) () ()
1910)
1911(define-full-operand Dsp-48-u8 "unsigned 8 bit displacement at offset 48 bits" (all-isas)
1912 h-uint DFLT f-dsp-48-u8
1913 ((parse "unsigned8")) () ()
1914)
1915(define-full-operand Dsp-48-s8 "signed 8 bit displacement at offset 48 bits" (all-isas)
e729279b 1916 h-sint DFLT f-dsp-48-s8
49f58d10
JB		 1917 ((parse "signed8")) () ()
1918)
1919(define-full-operand Dsp-48-u16 "unsigned 16 bit displacement at offset 48 bits" (all-isas)
1920 h-uint DFLT f-dsp-48-u16
1921 ((parse "unsigned16")) () ()
1922)
1923(define-full-operand Dsp-48-s16 "signed 16 bit displacement at offset 48 bits" (all-isas)
e729279b 1924 h-sint DFLT f-dsp-48-s16
49f58d10
JB		 1925 ((parse "signed16")) () ()
1926)
75b06e7b
DD		 1927(define-full-operand Dsp-48-u20 "unsigned 24 bit displacement at offset 40 bits" (all-isas)
1928 h-uint DFLT f-dsp-48-u20
1929 ((parse "unsigned24")) () ()
1930)
49f58d10
JB		 1931(define-full-operand Dsp-48-u24 "unsigned 24 bit displacement at offset 48 bits" (all-isas)
1932 h-uint DFLT f-dsp-48-u24
1933 ((parse "unsigned24")) () ()
1934)
1935
1936(define-full-operand Imm-8-s4 "signed 4 bit immediate at offset 8 bits" (all-isas)
1937 h-sint DFLT f-imm-8-s4
1938 ((parse "signed4")) () ()
1939)
c6552317
DD		 1940(define-full-operand Imm-8-s4n "negated 4 bit immediate at offset 8 bits" (all-isas)
1941 h-sint DFLT f-imm-8-s4
144f4bc6 1942 ((parse "signed4n") (print "signed4n")) () ()
c6552317 1943)
49f58d10
JB		 1944(define-full-operand Imm-sh-8-s4 "signed 4 bit shift immediate at offset 8 bits" (all-isas)
1945 h-shimm DFLT f-imm-8-s4
1946 () () ()
1947)
1948(define-full-operand Imm-8-QI "signed 8 bit immediate at offset 8 bits" (all-isas)
1949 h-sint DFLT f-dsp-8-s8
1950 ((parse "signed8")) () ()
1951)
1952(define-full-operand Imm-8-HI "signed 16 bit immediate at offset 8 bits" (all-isas)
1953 h-sint DFLT f-dsp-8-s16
1954 ((parse "signed16")) () ()
1955)
1956(define-full-operand Imm-12-s4 "signed 4 bit immediate at offset 12 bits" (all-isas)
1957 h-sint DFLT f-imm-12-s4
1958 ((parse "signed4")) () ()
1959)
c6552317
DD		 1960(define-full-operand Imm-12-s4n "negated 4 bit immediate at offset 12 bits" (all-isas)
1961 h-sint DFLT f-imm-12-s4
1962 ((parse "signed4n") (print "signed4n")) () ()
1963)
49f58d10
JB		 1964(define-full-operand Imm-sh-12-s4 "signed 4 bit shift immediate at offset 12 bits" (all-isas)
1965 h-shimm DFLT f-imm-12-s4
1966 () () ()
1967)
1968(define-full-operand Imm-13-u3 "signed 3 bit immediate at offset 13 bits" (all-isas)
e729279b 1969 h-sint DFLT f-imm-13-u3
49f58d10
JB		 1970 ((parse "signed4")) () ()
1971)
1972(define-full-operand Imm-20-s4 "signed 4 bit immediate at offset 20 bits" (all-isas)
1973 h-sint DFLT f-imm-20-s4
1974 ((parse "signed4")) () ()
1975)
1976(define-full-operand Imm-sh-20-s4 "signed 4 bit shift immediate at offset 12 bits" (all-isas)
1977 h-shimm DFLT f-imm-20-s4
1978 () () ()
1979)
1980(define-full-operand Imm-16-QI "signed 8 bit immediate at offset 16 bits" (all-isas)
1981 h-sint DFLT f-dsp-16-s8
1982 ((parse "signed8")) () ()
1983)
1984(define-full-operand Imm-16-HI "signed 16 bit immediate at offset 16 bits" (all-isas)
1985 h-sint DFLT f-dsp-16-s16
1986 ((parse "signed16")) () ()
1987)
1988(define-full-operand Imm-16-SI "signed 32 bit immediate at offset 16 bits" (all-isas)
1989 h-sint DFLT f-dsp-16-s32
1990 ((parse "signed32")) () ()
1991)
1992(define-full-operand Imm-24-QI "signed 8 bit immediate at offset 24 bits" (all-isas)
1993 h-sint DFLT f-dsp-24-s8
1994 ((parse "signed8")) () ()
1995)
1996(define-full-operand Imm-24-HI "signed 16 bit immediate at offset 24 bits" (all-isas)
1997 h-sint DFLT f-dsp-24-s16
1998 ((parse "signed16")) () ()
1999)
2000(define-full-operand Imm-24-SI "signed 32 bit immediate at offset 24 bits" (all-isas)
2001 h-sint DFLT f-dsp-24-s32
2002 ((parse "signed32")) () ()
2003)
2004(define-full-operand Imm-32-QI "signed 8 bit immediate at offset 32 bits" (all-isas)
2005 h-sint DFLT f-dsp-32-s8
2006 ((parse "signed8")) () ()
2007)
2008(define-full-operand Imm-32-SI "signed 32 bit immediate at offset 32 bits" (all-isas)
2009 h-sint DFLT f-dsp-32-s32
2010 ((parse "signed32")) () ()
2011)
2012(define-full-operand Imm-32-HI "signed 16 bit immediate at offset 32 bits" (all-isas)
2013 h-sint DFLT f-dsp-32-s16
2014 ((parse "signed16")) () ()
2015)
2016(define-full-operand Imm-40-QI "signed 8 bit immediate at offset 40 bits" (all-isas)
2017 h-sint DFLT f-dsp-40-s8
2018 ((parse "signed8")) () ()
2019)
2020(define-full-operand Imm-40-HI "signed 16 bit immediate at offset 40 bits" (all-isas)
2021 h-sint DFLT f-dsp-40-s16
2022 ((parse "signed16")) () ()
2023)
2024(define-full-operand Imm-40-SI "signed 32 bit immediate at offset 40 bits" (all-isas)
2025 h-sint DFLT f-dsp-40-s32
2026 ((parse "signed32")) () ()
2027)
2028(define-full-operand Imm-48-QI "signed 8 bit immediate at offset 48 bits" (all-isas)
2029 h-sint DFLT f-dsp-48-s8
2030 ((parse "signed8")) () ()
2031)
2032(define-full-operand Imm-48-HI "signed 16 bit immediate at offset 48 bits" (all-isas)
2033 h-sint DFLT f-dsp-48-s16
2034 ((parse "signed16")) () ()
2035)
2036(define-full-operand Imm-48-SI "signed 32 bit immediate at offset 48 bits" (all-isas)
2037 h-sint DFLT f-dsp-48-s32
2038 ((parse "signed32")) () ()
2039)
2040(define-full-operand Imm-56-QI "signed 8 bit immediate at offset 56 bits" (all-isas)
2041 h-sint DFLT f-dsp-56-s8
2042 ((parse "signed8")) () ()
2043)
2044(define-full-operand Imm-56-HI "signed 16 bit immediate at offset 56 bits" (all-isas)
2045 h-sint DFLT f-dsp-56-s16
2046 ((parse "signed16")) () ()
2047)
2048(define-full-operand Imm-64-HI "signed 16 bit immediate at offset 64 bits" (all-isas)
2049 h-sint DFLT f-dsp-64-s16
2050 ((parse "signed16")) () ()
2051)
2052(define-full-operand Imm1-S "signed 1 bit immediate for short format binary insns" (m32c-isa)
2053 h-sint DFLT f-imm1-S
2054 ((parse "imm1_S")) () ()
2055)
2056(define-full-operand Imm3-S "signed 3 bit immediate for short format binary insns" (m32c-isa)
2057 h-sint DFLT f-imm3-S
2058 ((parse "imm3_S")) () ()
2059)
43aa3bb1
DD		 2060(define-full-operand Bit3-S "3 bit bit number" (m32c-isa)
2061 h-sint DFLT f-imm3-S
2062 ((parse "bit3_S")) () ()
2063)
49f58d10
JB		 2064
2065;-------------------------------------------------------------
2066; Bit numbers
2067;-------------------------------------------------------------
2068
2069(define-full-operand Bitno16R "bit number for indexing registers" (m16c-isa)
2070 h-uint DFLT f-dsp-16-u8
2071 ((parse "Bitno16R")) () ()
2072)
2073(dnop Bitno32Prefixed "bit number for indexing objects" (m32c-isa) h-uint f-bitno32-prefixed)
2074(dnop Bitno32Unprefixed "bit number for indexing objects" (m32c-isa) h-uint f-bitno32-unprefixed)
2075
2076(define-full-operand BitBase16-16-u8 "unsigned bit,base:8 at offset 16for m16c" (m16c-isa)
2077 h-uint DFLT f-dsp-16-u8
2078 ((parse "unsigned_bitbase8") (print "unsigned_bitbase")) () ()
2079)
2080(define-full-operand BitBase16-16-s8 "signed bit,base:8 at offset 16for m16c" (m16c-isa)
e729279b 2081 h-sint DFLT f-dsp-16-s8
49f58d10
JB		 2082 ((parse "signed_bitbase8") (print "signed_bitbase")) () ()
2083)
2084(define-full-operand BitBase16-16-u16 "unsigned bit,base:16 at offset 16 for m16c" (m16c-isa)
2085 h-uint DFLT f-dsp-16-u16
2086 ((parse "unsigned_bitbase16") (print "unsigned_bitbase")) () ()
2087)
2088(define-full-operand BitBase16-8-u11-S "signed bit,base:11 at offset 16 for m16c" (m16c-isa)
e729279b 2089 h-uint DFLT f-bitbase16-u11-S
49f58d10
JB		 2090 ((parse "unsigned_bitbase11") (print "unsigned_bitbase")) () ()
2091)
2092
2093(define-full-operand BitBase32-16-u11-Unprefixed "unsigned bit,base:11 at offset 16 for m32c" (m32c-isa)
2094 h-uint DFLT f-bitbase32-16-u11-unprefixed
2095 ((parse "unsigned_bitbase11") (print "unsigned_bitbase")) () ()
2096)
2097(define-full-operand BitBase32-16-s11-Unprefixed "signed bit,base:11 at offset 16 for m32c" (m32c-isa)
2098 h-sint DFLT f-bitbase32-16-s11-unprefixed
2099 ((parse "signed_bitbase11") (print "signed_bitbase")) () ()
2100)
2101(define-full-operand BitBase32-16-u19-Unprefixed "unsigned bit,base:19 at offset 16 for m32c" (m32c-isa)
2102 h-uint DFLT f-bitbase32-16-u19-unprefixed
2103 ((parse "unsigned_bitbase19") (print "unsigned_bitbase")) () ()
2104)
2105(define-full-operand BitBase32-16-s19-Unprefixed "signed bit,base:19 at offset 16 for m32c" (m32c-isa)
2106 h-sint DFLT f-bitbase32-16-s19-unprefixed
2107 ((parse "signed_bitbase19") (print "signed_bitbase")) () ()
2108)
2109(define-full-operand BitBase32-16-u27-Unprefixed "unsigned bit,base:27 at offset 16 for m32c" (m32c-isa)
2110 h-uint DFLT f-bitbase32-16-u27-unprefixed
2111 ((parse "unsigned_bitbase27") (print "unsigned_bitbase")) () ()
2112)
2113(define-full-operand BitBase32-24-u11-Prefixed "unsigned bit,base:11 at offset 24 for m32c" (m32c-isa)
2114 h-uint DFLT f-bitbase32-24-u11-prefixed
2115 ((parse "unsigned_bitbase11") (print "unsigned_bitbase")) () ()
2116)
2117(define-full-operand BitBase32-24-s11-Prefixed "signed bit,base:11 at offset 24 for m32c" (m32c-isa)
2118 h-sint DFLT f-bitbase32-24-s11-prefixed
2119 ((parse "signed_bitbase11") (print "signed_bitbase")) () ()
2120)
2121(define-full-operand BitBase32-24-u19-Prefixed "unsigned bit,base:19 at offset 24 for m32c" (m32c-isa)
2122 h-uint DFLT f-bitbase32-24-u19-prefixed
2123 ((parse "unsigned_bitbase19") (print "unsigned_bitbase")) () ()
2124)
2125(define-full-operand BitBase32-24-s19-Prefixed "signed bit,base:19 at offset 24 for m32c" (m32c-isa)
2126 h-sint DFLT f-bitbase32-24-s19-prefixed
2127 ((parse "signed_bitbase19") (print "signed_bitbase")) () ()
2128)
2129(define-full-operand BitBase32-24-u27-Prefixed "unsigned bit,base:27 at offset 24 for m32c" (m32c-isa)
2130 h-uint DFLT f-bitbase32-24-u27-prefixed
2131 ((parse "unsigned_bitbase27") (print "unsigned_bitbase")) () ()
2132)
2133;-------------------------------------------------------------
2134; Labels
2135;-------------------------------------------------------------
2136
e729279b
NC		 2137(define-full-operand Lab-5-3 "3 bit label" (all-isas RELAX)
2138 h-iaddr DFLT f-lab-5-3
2139 ((parse "lab_5_3")) () () )
2140
2141(define-full-operand Lab32-jmp-s "3 bit label" (all-isas RELAX)
2142 h-iaddr DFLT f-lab32-jmp-s
2143 ((parse "lab_5_3")) () () )
2144
2145(dnop Lab-8-8 "8 bit label" (all-isas RELAX) h-iaddr f-lab-8-8)
2146(dnop Lab-8-16 "16 bit label" (all-isas RELAX) h-iaddr f-lab-8-16)
6772dd07 2147(dnop Lab-8-24 "24 bit label" (all-isas RELAX) h-iaddr f-lab-8-24)
e729279b 2148(dnop Lab-16-8 "8 bit label" (all-isas RELAX) h-iaddr f-lab-16-8)
144f4bc6
DD		 2149(dnop Lab-24-8 "8 bit label" (all-isas RELAX) h-iaddr f-lab-24-8)
2150(dnop Lab-32-8 "8 bit label" (all-isas RELAX) h-iaddr f-lab-32-8)
2151(dnop Lab-40-8 "8 bit label" (all-isas RELAX) h-iaddr f-lab-40-8)
49f58d10
JB		 2152
2153;-------------------------------------------------------------
2154; Condition code bits
2155;-------------------------------------------------------------
2156
2157(dnop sbit "negative bit" (SEM-ONLY all-isas) h-sbit f-nil)
2158(dnop obit "overflow bit" (SEM-ONLY all-isas) h-obit f-nil)
2159(dnop zbit "zero bit" (SEM-ONLY all-isas) h-zbit f-nil)
2160(dnop cbit "carry bit" (SEM-ONLY all-isas) h-cbit f-nil)
2161(dnop ubit "stack ptr select bit" (SEM-ONLY all-isas) h-ubit f-nil)
2162(dnop ibit "interrupt enable bit" (SEM-ONLY all-isas) h-ibit f-nil)
2163(dnop bbit "reg bank select bit" (SEM-ONLY all-isas) h-bbit f-nil)
2164(dnop dbit "debug bit" (SEM-ONLY all-isas) h-dbit f-nil)
2165
2166;-------------------------------------------------------------
2167; Condition operands
2168;-------------------------------------------------------------
2169
2170(define-pmacro (cond-operand mach offset)
2171 (dnop (.sym cond mach - offset) "condition" ((.sym m mach c-isa)) (.sym h-cond mach) (.sym f-dsp- offset -u8))
2172)
2173
2174(cond-operand 16 16)
2175(cond-operand 16 24)
2176(cond-operand 16 32)
2177(cond-operand 32 16)
2178(cond-operand 32 24)
2179(cond-operand 32 32)
2180(cond-operand 32 40)
2181
2182(dnop cond16c "condition" (m16c-isa) h-cond16c f-cond16)
2183(dnop cond16j "condition" (m16c-isa) h-cond16j f-cond16)
2184(dnop cond16j5 "condition" (m16c-isa) h-cond16j-5 f-cond16j-5)
2185(dnop cond32 "condition" (m32c-isa) h-cond32 f-cond32)
2186(dnop cond32j "condition" (m32c-isa) h-cond32 f-cond32j)
2187(dnop sccond32 "scCND condition" (m32c-isa) h-cond32 f-cond16)
2188(dnop flags16 "flags" (m16c-isa) h-flags f-9-3)
2189(dnop flags32 "flags" (m32c-isa) h-flags f-13-3)
2190(dnop cr16 "control" (m16c-isa) h-cr-16 f-9-3)
2191(dnop cr1-Unprefixed-32 "control" (m32c-isa) h-cr1-32 f-13-3)
2192(dnop cr1-Prefixed-32 "control" (m32c-isa) h-cr1-32 f-21-3)
2193(dnop cr2-32 "control" (m32c-isa) h-cr2-32 f-13-3)
2194(dnop cr3-Unprefixed-32 "control" (m32c-isa) h-cr3-32 f-13-3)
2195(dnop cr3-Prefixed-32 "control" (m32c-isa) h-cr3-32 f-21-3)
2196
2197;-------------------------------------------------------------
2198; Suffixes
2199;-------------------------------------------------------------
2200
2201(define-full-operand Z "Suffix for zero format insns" (all-isas)
2202 h-sint DFLT f-nil
2203 ((parse "Z") (print "Z")) () ()
2204)
2205(define-full-operand S "Suffix for short format insns" (all-isas)
2206 h-sint DFLT f-nil
2207 ((parse "S") (print "S")) () ()
2208)
2209(define-full-operand Q "Suffix for quick format insns" (all-isas)
2210 h-sint DFLT f-nil
2211 ((parse "Q") (print "Q")) () ()
2212)
2213(define-full-operand G "Suffix for general format insns" (all-isas)
2214 h-sint DFLT f-nil
2215 ((parse "G") (print "G")) () ()
2216)
2217(define-full-operand X "Empty suffix" (all-isas)
2218 h-sint DFLT f-nil
2219 ((parse "X") (print "X")) () ()
2220)
2221(define-full-operand size "any size specifier" (all-isas)
2222 h-sint DFLT f-nil
2223 ((parse "size") (print "size")) () ()
2224)
2225;-------------------------------------------------------------
2226; Misc
2227;-------------------------------------------------------------
2228
2229(dnop BitIndex "Bit Index for the next insn" (SEM-ONLY MACH32 m32c-isa) h-bit-index f-nil)
2230(dnop SrcIndex "Source Index for the next insn" (SEM-ONLY MACH32 m32c-isa) h-src-index f-nil)
2231(dnop DstIndex "Destination Index for the next insn" (SEM-ONLY MACH32 m32c-isa) h-dst-index f-nil)
2232(dnop NoRemainder "Place holder for when the remainder is not kept" (SEM-ONLY MACH32 m32c-isa) h-none f-nil)
2233\f
2234;=============================================================
2235; Derived Operands
2236
2237; Memory reference macros that clip addresses appropriately. Refer to
2238; memory at ADDRESS in MODE, clipped appropriately for either the m16c
2239; or m32c.
2240(define-pmacro (mem16 mode address)
2241 (mem mode (and #xffff address)))
2242
75b06e7b
DD		 2243(define-pmacro (mem20 mode address)
2244 (mem mode (and #xfffff address)))
2245
49f58d10
JB		 2246(define-pmacro (mem32 mode address)
2247 (mem mode (and #xffffff address)))
2248
2249; Like mem16 and mem32, but takes MACH as a parameter. MACH must be
2250; either 16 or 32.
2251(define-pmacro (mem-mach mach mode address)
2252 ((.sym mem mach) mode address))
2253
2254;-------------------------------------------------------------
2255; Source
2256;-------------------------------------------------------------
2257; Rn direct
2258;-------------------------------------------------------------
2259
2260(define-pmacro (src16-Rn-direct-operand xmode)
2261 (begin
2262 (define-derived-operand
2263 (name (.sym src16-Rn-direct- xmode))
2264 (comment (.str "m16c Rn direct source " xmode))
2265 (attrs (machine 16))
2266 (mode xmode)
2267 (args ((.sym Src16Rn xmode)))
2268 (syntax (.str "$Src16Rn" xmode))
2269 (base-ifield f-8-4)
2270 (encoding (+ (f-8-2 0) (.sym Src16Rn xmode)))
2271 (ifield-assertion (eq f-8-2 0))
2272 (getter (trunc xmode (.sym Src16Rn xmode)))
2273 (setter (set (.sym Src16Rn xmode) newval))
2274 )
2275 )
2276)
2277(src16-Rn-direct-operand QI)
2278(src16-Rn-direct-operand HI)
2279
2280(define-pmacro (src32-Rn-direct-operand group base xmode)
2281 (begin
2282 (define-derived-operand
2283 (name (.sym src32-Rn-direct- group - xmode))
2284 (comment (.str "m32c Rn direct source " xmode))
2285 (attrs (machine 32))
2286 (mode xmode)
2287 (args ((.sym Src32Rn group xmode)))
2288 (syntax (.str "$Src32Rn" group xmode))
2289 (base-ifield (.sym f- base -11))
2290 (encoding (+ ((.sym f- base -3) 4) (.sym Src32Rn group xmode)))
2291 (ifield-assertion (eq (.sym f- base -3) 4))
2292 (getter (trunc xmode (.sym Src32Rn group xmode)))
2293 (setter (set (.sym Src32Rn group xmode) newval))
2294 )
2295 )
2296)
2297
2298(src32-Rn-direct-operand Unprefixed 1 QI)
2299(src32-Rn-direct-operand Prefixed 9 QI)
2300(src32-Rn-direct-operand Unprefixed 1 HI)
2301(src32-Rn-direct-operand Prefixed 9 HI)
2302(src32-Rn-direct-operand Unprefixed 1 SI)
2303(src32-Rn-direct-operand Prefixed 9 SI)
2304
2305;-------------------------------------------------------------
2306; An direct
2307;-------------------------------------------------------------
2308
2309(define-pmacro (src16-An-direct-operand xmode)
2310 (begin
2311 (define-derived-operand
2312 (name (.sym src16-An-direct- xmode))
2313 (comment (.str "m16c An direct destination " xmode))
2314 (attrs (machine 16))
2315 (mode xmode)
2316 (args ((.sym Src16An xmode)))
2317 (syntax (.str "$Src16An" xmode))
2318 (base-ifield f-8-4)
2319 (encoding (+ (f-8-2 1) (f-10-1 0) (.sym Src16An xmode)))
2320 (ifield-assertion (andif (eq f-8-2 1) (eq f-10-1 0)))
2321 (getter (trunc xmode (.sym Src16An xmode)))
2322 (setter (set (.sym Src16An xmode) newval))
2323 )
2324 )
2325)
2326(src16-An-direct-operand QI)
2327(src16-An-direct-operand HI)
2328
2329(define-pmacro (src32-An-direct-operand group base1 base2 xmode)
2330 (begin
2331 (define-derived-operand
2332 (name (.sym src32-An-direct- group - xmode))
2333 (comment (.str "m32c An direct destination " xmode))
2334 (attrs (machine 32))
2335 (mode xmode)
2336 (args ((.sym Src32An group xmode)))
2337 (syntax (.str "$Src32An" group xmode))
2338 (base-ifield (.sym f- base1 -11))
2339 (encoding (+ ((.sym f- base1 -3) 0) ((.sym f- base2 -1) 1) (.sym Src32An group xmode)))
2340 (ifield-assertion (andif (eq (.sym f- base1 -3) 0) (eq (.sym f- base2 -1) 1)))
2341 (getter (trunc xmode (.sym Src32An group xmode)))
2342 (setter (set (.sym Src32An group xmode) newval))
2343 )
2344 )
2345)
2346
2347(src32-An-direct-operand Unprefixed 1 10 QI)
2348(src32-An-direct-operand Unprefixed 1 10 HI)
2349(src32-An-direct-operand Unprefixed 1 10 SI)
2350(src32-An-direct-operand Prefixed 9 18 QI)
2351(src32-An-direct-operand Prefixed 9 18 HI)
2352(src32-An-direct-operand Prefixed 9 18 SI)
2353
2354;-------------------------------------------------------------
2355; An indirect
2356;-------------------------------------------------------------
2357
2358(define-pmacro (src16-An-indirect-operand xmode)
2359 (begin
2360 (define-derived-operand
2361 (name (.sym src16-An-indirect- xmode))
2362 (comment (.str "m16c An indirect destination " xmode))
2363 (attrs (machine 16))
2364 (mode xmode)
2365 (args (Src16An))
2366 (syntax "[$Src16An]")
2367 (base-ifield f-8-4)
2368 (encoding (+ (f-8-2 1) (f-10-1 1) Src16An))
2369 (ifield-assertion (andif (eq f-8-2 1) (eq f-10-1 1)))
2370 (getter (mem16 xmode Src16An))
2371 (setter (set (mem16 xmode Src16An) newval))
2372 )
2373 )
2374)
2375(src16-An-indirect-operand QI)
2376(src16-An-indirect-operand HI)
2377
2378(define-pmacro (src32-An-indirect-operand group base1 base2 xmode)
2379 (begin
2380 (define-derived-operand
2381 (name (.sym src32-An-indirect- group - xmode))
2382 (comment (.str "m32c An indirect destination " xmode))
2383 (attrs (machine 32))
2384 (mode xmode)
2385 (args ((.sym Src32An group)))
2386 (syntax (.str "[$Src32An" group "]"))
2387 (base-ifield (.sym f- base1 -11))
2388 (encoding (+ ((.sym f- base1 -3) 0) ((.sym f- base2 -1) 0) (.sym Src32An group)))
2389 (ifield-assertion (andif (eq (.sym f- base1 -3) 0) (eq (.sym f- base2 -1) 0)))
2390 (getter (c-call xmode (.str "operand_getter_" xmode) (.sym Src32An group)
2391 (const 0)))
2392 (setter (c-call DFLT (.str "operand_setter_" xmode) newval
2393 (.sym Src32An group) (const 0)))
2394; (getter (mem32 xmode (.sym Src32An group)))
2395; (setter (set (mem32 xmode (.sym Src32An group)) newval))
2396 )
2397 )
2398)
2399
2400(src32-An-indirect-operand Unprefixed 1 10 QI)
2401(src32-An-indirect-operand Unprefixed 1 10 HI)
2402(src32-An-indirect-operand Unprefixed 1 10 SI)
2403(src32-An-indirect-operand Prefixed 9 18 QI)
2404(src32-An-indirect-operand Prefixed 9 18 HI)
2405(src32-An-indirect-operand Prefixed 9 18 SI)
2406
2407;-------------------------------------------------------------
2408; dsp:d[r] relative
2409;-------------------------------------------------------------
2410
2411(define-pmacro (src16-relative-operand xmode)
2412 (begin
2413 (define-derived-operand
2414 (name (.sym src16-16-8-SB-relative- xmode))
2415 (comment (.str "m16c dsp:8[sb] relative destination " xmode))
2416 (attrs (machine 16))
2417 (mode xmode)
2418 (args (Dsp-16-u8))
2419 (syntax "${Dsp-16-u8}[sb]")
2420 (base-ifield f-8-4)
2421 (encoding (+ (f-8-4 #xA) Dsp-16-u8))
2422 (ifield-assertion (eq f-8-4 #xA))
2423 (getter (mem16 xmode (add Dsp-16-u8 (reg h-sb))))
2424 (setter (set (mem16 xmode (add Dsp-16-u8 (reg h-sb))) newval))
2425 )
2426 (define-derived-operand
2427 (name (.sym src16-16-16-SB-relative- xmode))
2428 (comment (.str "m16c dsp:16[sb] relative destination " xmode))
2429 (attrs (machine 16))
2430 (mode xmode)
2431 (args (Dsp-16-u16))
2432 (syntax "${Dsp-16-u16}[sb]")
2433 (base-ifield f-8-4)
2434 (encoding (+ (f-8-4 #xE) Dsp-16-u16))
2435 (ifield-assertion (eq f-8-4 #xE))
2436 (getter (mem16 xmode (add Dsp-16-u16 (reg h-sb))))
2437 (setter (set (mem16 xmode (add Dsp-16-u16 (reg h-sb))) newval))
2438 )
2439 (define-derived-operand
2440 (name (.sym src16-16-8-FB-relative- xmode))
2441 (comment (.str "m16c dsp:8[fb] relative destination " xmode))
2442 (attrs (machine 16))
2443 (mode xmode)
2444 (args (Dsp-16-s8))
2445 (syntax "${Dsp-16-s8}[fb]")
2446 (base-ifield f-8-4)
2447 (encoding (+ (f-8-4 #xB) Dsp-16-s8))
2448 (ifield-assertion (eq f-8-4 #xB))
2449 (getter (mem16 xmode (add Dsp-16-s8 (reg h-fb))))
2450 (setter (set (mem16 xmode (add Dsp-16-s8 (reg h-fb))) newval))
2451 )
2452 (define-derived-operand
2453 (name (.sym src16-16-8-An-relative- xmode))
2454 (comment (.str "m16c dsp:8[An] relative destination " xmode))
2455 (attrs (machine 16))
2456 (mode xmode)
2457 (args (Src16An Dsp-16-u8))
2458 (syntax "${Dsp-16-u8}[$Src16An]")
2459 (base-ifield f-8-4)
2460 (encoding (+ (f-8-2 2) (f-10-1 0) Dsp-16-u8 Src16An))
2461 (ifield-assertion (andif (eq f-8-2 2) (eq f-10-1 0)))
2462 (getter (mem16 xmode (add Dsp-16-u8 Src16An)))
2463 (setter (set (mem16 xmode (add Dsp-16-u8 Src16An)) newval))
2464 )
2465 (define-derived-operand
2466 (name (.sym src16-16-16-An-relative- xmode))
2467 (comment (.str "m16c dsp:16[An] relative destination " xmode))
2468 (attrs (machine 16))
2469 (mode xmode)
2470 (args (Src16An Dsp-16-u16))
2471 (syntax "${Dsp-16-u16}[$Src16An]")
2472 (base-ifield f-8-4)
2473 (encoding (+ (f-8-2 3) (f-10-1 0) Dsp-16-u16 Src16An))
2474 (ifield-assertion (andif (eq f-8-2 3) (eq f-10-1 0)))
2475 (getter (mem16 xmode (add Dsp-16-u16 Src16An)))
2476 (setter (set (mem16 xmode (add Dsp-16-u16 Src16An)) newval))
2477 )
75b06e7b
DD		 2478 (define-derived-operand
2479 (name (.sym src16-16-20-An-relative- xmode))
2480 (comment (.str "m16c dsp:20[An] relative destination " xmode))
2481 (attrs (machine 16))
2482 (mode xmode)
2483 (args (Src16An Dsp-16-u20))
2484 (syntax "${Dsp-16-u20}[$Src16An]")
2485 (base-ifield f-8-4)
2486 (encoding (+ (f-8-2 3) (f-10-1 0) Dsp-16-u20 Src16An))
2487 (ifield-assertion (andif (eq f-8-2 3) (eq f-10-1 0)))
2488 (getter (mem20 xmode (add Dsp-16-u20 Src16An)))
2489 (setter (set (mem20 xmode (add Dsp-16-u20 Src16An)) newval))
2490 )
49f58d10
JB		 2491 )
2492)
2493
2494(src16-relative-operand QI)
2495(src16-relative-operand HI)
2496
2497(define-pmacro (src32-relative-operand offset group base1 base2 xmode)
2498 (begin
2499 (define-derived-operand
2500 (name (.sym src32- offset -8-SB-relative- group - xmode))
2501 (comment (.str "m32c dsp:8[sb] relative destination " xmode))
2502 (attrs (machine 32))
2503 (mode xmode)
2504 (args ((.sym Dsp- offset -u8)))
2505 (syntax (.str "${Dsp-" offset "-u8}[sb]"))
2506 (base-ifield (.sym f- base1 -11))
2507 (encoding (+ ((.sym f- base1 -3) 1) ((.sym f- base2 -2) 2) (.sym Dsp- offset -u8)))
2508 (ifield-assertion (andif (eq (.sym f- base1 -3) 1) (eq (.sym f- base2 -2) 2)))
2509 (getter (c-call xmode (.str "operand_getter_" xmode) sb (.sym Dsp- offset -u8)))
2510 (setter (c-call DFLT (.str "operand_setter_" xmode) newval sb (.sym Dsp- offset -u8)))
2511; (getter (mem32 xmode (add (.sym Dsp- offset -u8) (reg h-sb))))
2512; (setter (set (mem32 xmode (add (.sym Dsp- offset -u8) (reg h-sb))) newval))
2513 )
2514 (define-derived-operand
2515 (name (.sym src32- offset -16-SB-relative- group - xmode))
2516 (comment (.str "m32c dsp:16[sb] relative destination " xmode))
2517 (attrs (machine 32))
2518 (mode xmode)
2519 (args ((.sym Dsp- offset -u16)))
2520 (syntax (.str "${Dsp-" offset "-u16}[sb]"))
2521 (base-ifield (.sym f- base1 -11))
2522 (encoding (+ ((.sym f- base1 -3) 2) ((.sym f- base2 -2) 2) (.sym Dsp- offset -u16)))
2523 (ifield-assertion (andif (eq (.sym f- base1 -3) 2) (eq (.sym f- base2 -2) 2)))
2524 (getter (c-call xmode (.str "operand_getter_" xmode) sb (.sym Dsp- offset -u16)))
2525 (setter (c-call DFLT (.str "operand_setter_" xmode) newval sb (.sym Dsp- offset -u16)))
2526; (getter (mem32 xmode (add (.sym Dsp- offset -u16) (reg h-sb))))
2527; (setter (set (mem32 xmode (add (.sym Dsp- offset -u16) (reg h-sb))) newval))
2528 )
2529 (define-derived-operand
2530 (name (.sym src32- offset -8-FB-relative- group - xmode))
2531 (comment (.str "m32c dsp:8[fb] relative destination " xmode))
2532 (attrs (machine 32))
2533 (mode xmode)
2534 (args ((.sym Dsp- offset -s8)))
2535 (syntax (.str "${Dsp-" offset "-s8}[fb]"))
2536 (base-ifield (.sym f- base1 -11))
2537 (encoding (+ ((.sym f- base1 -3) 1) ((.sym f- base2 -2) 3) (.sym Dsp- offset -s8)))
2538 (ifield-assertion (andif (eq (.sym f- base1 -3) 1) (eq (.sym f- base2 -2) 3)))
2539 (getter (c-call xmode (.str "operand_getter_" xmode) fb (.sym Dsp- offset -s8)))
2540 (setter (c-call DFLT (.str "operand_setter_" xmode) newval fb (.sym Dsp- offset -s8)))
2541; (getter (mem32 xmode (add (.sym Dsp- offset -s8) (reg h-fb))))
2542; (setter (set (mem32 xmode (add (.sym Dsp- offset -s8) (reg h-fb))) newval))
2543 )
2544 (define-derived-operand
2545 (name (.sym src32- offset -16-FB-relative- group - xmode))
2546 (comment (.str "m32c dsp:16[fb] relative destination " xmode))
2547 (attrs (machine 32))
2548 (mode xmode)
2549 (args ((.sym Dsp- offset -s16)))
2550 (syntax (.str "${Dsp-" offset "-s16}[fb]"))
2551 (base-ifield (.sym f- base1 -11))
2552 (encoding (+ ((.sym f- base1 -3) 2) ((.sym f- base2 -2) 3) (.sym Dsp- offset -s16)))
2553 (ifield-assertion (andif (eq (.sym f- base1 -3) 2) (eq (.sym f- base2 -2) 3)))
2554 (getter (c-call xmode (.str "operand_getter_" xmode) fb (.sym Dsp- offset -s16)))
2555 (setter (c-call DFLT (.str "operand_setter_" xmode) newval fb (.sym Dsp- offset -s16)))
2556; (getter (mem32 xmode (add (.sym Dsp- offset -s16) (reg h-fb))))
2557; (setter (set (mem32 xmode (add (.sym Dsp- offset -s16) (reg h-fb))) newval))
2558 )
2559 (define-derived-operand
2560 (name (.sym src32- offset -8-An-relative- group - xmode))
2561 (comment (.str "m32c dsp:8[An] relative destination " xmode))
2562 (attrs (machine 32))
2563 (mode xmode)
2564 (args ((.sym Src32An group) (.sym Dsp- offset -u8)))
2565 (syntax (.str "${Dsp-" offset "-u8}[$Src32An" group "]"))
2566 (base-ifield (.sym f- base1 -11))
2567 (encoding (+ ((.sym f- base1 -3) 1) ((.sym f- base2 -1) 0) (.sym Dsp- offset -u8) (.sym Src32An group)))
2568 (ifield-assertion (andif (eq (.sym f- base1 -3) 1) (eq (.sym f- base2 -1) 0)))
2569 (getter (c-call xmode (.str "operand_getter_" xmode) (.sym Src32An group) (.sym Dsp- offset -u8)))
2570 (setter (c-call DFLT (.str "operand_setter_" xmode) newval (.sym Src32An group) (.sym Dsp- offset -u8)))
2571; (getter (mem32 xmode (add (.sym Dsp- offset -u8) (.sym Src32An group))))
2572; (setter (set (mem32 xmode (add (.sym Dsp- offset -u8) (.sym Src32An group))) newval))
2573 )
2574 (define-derived-operand
2575 (name (.sym src32- offset -16-An-relative- group - xmode))
2576 (comment (.str "m32c dsp:16[An] relative destination " xmode))
2577 (attrs (machine 32))
2578 (mode xmode)
2579 (args ((.sym Src32An group) (.sym Dsp- offset -u16)))
2580 (syntax (.str "${Dsp-" offset "-u16}[$Src32An" group "]"))
2581 (base-ifield (.sym f- base1 -11))
2582 (encoding (+ ((.sym f- base1 -3) 2) ((.sym f- base2 -1) 0) (.sym Dsp- offset -u16) (.sym Src32An group)))
2583 (ifield-assertion (andif (eq (.sym f- base1 -3) 2) (eq (.sym f- base2 -1) 0)))
2584 (getter (c-call xmode (.str "operand_getter_" xmode) (.sym Src32An group) (.sym Dsp- offset -u16)))
2585 (setter (c-call DFLT (.str "operand_setter_" xmode) newval (.sym Src32An group) (.sym Dsp- offset -u16)))
2586; (getter (mem32 xmode (add (.sym Dsp- offset -u16) (.sym Src32An group))))
2587; (setter (set (mem32 xmode (add (.sym Dsp- offset -u16) (.sym Src32An group))) newval))
2588 )
2589 (define-derived-operand
2590 (name (.sym src32- offset -24-An-relative- group - xmode))
2591 (comment (.str "m32c dsp:16[An] relative destination " xmode))
2592 (attrs (machine 32))
2593 (mode xmode)
2594 (args ((.sym Src32An group) (.sym Dsp- offset -u24)))
2595 (syntax (.str "${Dsp-" offset "-u24}[$Src32An" group "]"))
2596 (base-ifield (.sym f- base1 -11))
2597 (encoding (+ ((.sym f- base1 -3) 3) ((.sym f- base2 -1) 0) (.sym Dsp- offset -u24) (.sym Src32An group)))
2598 (ifield-assertion (andif (eq (.sym f- base1 -3) 3) (eq (.sym f- base2 -1) 0)))
2599 (getter (c-call xmode (.str "operand_getter_" xmode) (.sym Src32An group) (.sym Dsp- offset -u24) ))
2600 (setter (c-call DFLT (.str "operand_setter_" xmode) newval (.sym Src32An group) (.sym Dsp- offset -u24)))
2601; (getter (mem32 xmode (add (.sym Dsp- offset -u24) (.sym Src32An group))))
2602; (setter (set (mem32 xmode (add (.sym Dsp- offset -u24) (.sym Src32An group))) newval))
2603 )
2604 )
2605)
2606
2607(src32-relative-operand 16 Unprefixed 1 10 QI)
2608(src32-relative-operand 16 Unprefixed 1 10 HI)
2609(src32-relative-operand 16 Unprefixed 1 10 SI)
2610(src32-relative-operand 24 Prefixed 9 18 QI)
2611(src32-relative-operand 24 Prefixed 9 18 HI)
2612(src32-relative-operand 24 Prefixed 9 18 SI)
2613
2614;-------------------------------------------------------------
2615; Absolute address
2616;-------------------------------------------------------------
2617
2618(define-pmacro (src16-absolute xmode)
2619 (begin
2620 (define-derived-operand
2621 (name (.sym src16-16-16-absolute- xmode))
2622 (comment (.str "m16c absolute address " xmode))
2623 (attrs (machine 16))
2624 (mode xmode)
2625 (args (Dsp-16-u16))
2626 (syntax (.str "${Dsp-16-u16}"))
2627 (base-ifield f-8-4)
2628 (encoding (+ (f-8-4 #xF) Dsp-16-u16))
2629 (ifield-assertion (eq f-8-4 #xF))
2630 (getter (mem16 xmode Dsp-16-u16))
2631 (setter (set (mem16 xmode Dsp-16-u16) newval))
2632 )
2633 )
2634)
2635
2636(src16-absolute QI)
2637(src16-absolute HI)
2638
2639(define-pmacro (src32-absolute offset group base1 base2 xmode)
2640 (begin
2641 (define-derived-operand
2642 (name (.sym src32- offset -16-absolute- group - xmode))
2643 (comment (.str "m32c absolute address " xmode))
2644 (attrs (machine 32))
2645 (mode xmode)
2646 (args ((.sym Dsp- offset -u16)))
2647 (syntax (.str "${Dsp-" offset "-u16}"))
2648 (base-ifield (.sym f- base1 -11))
2649 (encoding (+ ((.sym f- base1 -3) 3) ((.sym f- base2 -2) 3) (.sym Dsp- offset -u16)))
2650 (ifield-assertion (andif (eq (.sym f- base1 -3) 3) (eq (.sym f- base2 -2) 3)))
2651 (getter (c-call xmode (.str "operand_getter_" xmode) (const 0) (.sym Dsp- offset -u16)))
2652 (setter (c-call DFLT (.str "operand_setter_" xmode) newval (const 0) (.sym Dsp- offset -u16)))
2653; (getter (mem32 xmode (.sym Dsp- offset -u16)))
2654; (setter (set (mem32 xmode (.sym Dsp- offset -u16)) newval))
2655 )
2656 (define-derived-operand
2657 (name (.sym src32- offset -24-absolute- group - xmode))
2658 (comment (.str "m32c absolute address " xmode))
2659 (attrs (machine 32))
2660 (mode xmode)
2661 (args ((.sym Dsp- offset -u24)))
2662 (syntax (.str "${Dsp-" offset "-u24}"))
2663 (base-ifield (.sym f- base1 -11))
2664 (encoding (+ ((.sym f- base1 -3) 3) ((.sym f- base2 -2) 2) (.sym Dsp- offset -u24)))
2665 (ifield-assertion (andif (eq (.sym f- base1 -3) 3) (eq (.sym f- base2 -2) 2)))
2666 (getter (c-call xmode (.str "operand_getter_" xmode) (const 0) (.sym Dsp- offset -u24)))
2667 (setter (c-call DFLT (.str "operand_setter_" xmode) newval (const 0) (.sym Dsp- offset -u24)))
2668; (getter (mem32 xmode (.sym Dsp- offset -u24)))
2669; (setter (set (mem32 xmode (.sym Dsp- offset -u24)) newval))
2670 )
2671 )
2672)
2673
2674(src32-absolute 16 Unprefixed 1 10 QI)
2675(src32-absolute 16 Unprefixed 1 10 HI)
2676(src32-absolute 16 Unprefixed 1 10 SI)
2677(src32-absolute 24 Prefixed 9 18 QI)
2678(src32-absolute 24 Prefixed 9 18 HI)
2679(src32-absolute 24 Prefixed 9 18 SI)
2680
2681;-------------------------------------------------------------
2682; An indirect indirect
2683;
2684; Double indirect addressing uses the lower 3 bytes of the value stored
2685; at the address referenced by 'op' as the effective address.
2686;-------------------------------------------------------------
2687
2688(define-pmacro (indirect-addr op) (and USI (mem32 USI op) #x00ffffff))
2689
2690; (define-pmacro (src-An-indirect-indirect-operand xmode)
2691; (define-derived-operand
2692; (name (.sym src32-An-indirect-indirect- xmode))
2693; (comment (.str "m32c An indirect indirect destination " xmode))
2694; (attrs (machine 32))
2695; (mode xmode)
2696; (args (Src32AnPrefixed))
2697; (syntax (.str "[[$Src32AnPrefixed]]"))
2698; (base-ifield f-9-11)
2699; (encoding (+ (f-9-3 0) (f-18-1 0) Src32AnPrefixed))
2700; (ifield-assertion (andif (eq f-9-3 0) (eq f-18-1 0)))
2701; (getter (mem32 xmode (indirect-addr Src32AnPrefixed)))
2702; (setter (set (mem32 xmode (indirect-addr Src32AnPrefixed)) newval))
2703; )
2704; )
2705
2706; (src-An-indirect-indirect-operand QI)
2707; (src-An-indirect-indirect-operand HI)
2708; (src-An-indirect-indirect-operand SI)
2709
2710;-------------------------------------------------------------
2711; Relative indirect
2712;-------------------------------------------------------------
2713
2714(define-pmacro (src-relative-indirect-operand xmode)
2715 (begin
2716; (define-derived-operand
2717; (name (.sym src32-24-8-SB-relative-indirect- xmode))
2718; (comment (.str "m32c dsp:8[sb] relative source " xmode))
2719; (attrs (machine 32))
2720; (mode xmode)
2721; (args (Dsp-24-u8))
2722; (syntax "[${Dsp-24-u8}[sb]]")
2723; (base-ifield f-9-11)
2724; (encoding (+ (f-9-3 1) (f-18-2 2) Dsp-24-u8))
2725; (ifield-assertion (andif (eq f-9-3 1) (eq f-18-2 2)))
2726; (getter (mem32 xmode (indirect-addr (add Dsp-24-u8 (reg h-sb)))))
2727; (setter (set (mem32 xmode (indirect-addr (add Dsp-24-u8 (reg h-sb)))) newval))
2728; )
2729; (define-derived-operand
2730; (name (.sym src32-24-16-SB-relative-indirect- xmode))
2731; (comment (.str "m32c dsp:16[sb] relative source " xmode))
2732; (attrs (machine 32))
2733; (mode xmode)
2734; (args (Dsp-24-u16))
2735; (syntax "[${Dsp-24-u16}[sb]]")
2736; (base-ifield f-9-11)
2737; (encoding (+ (f-9-3 2) (f-18-2 2) Dsp-24-u16))
2738; (ifield-assertion (andif (eq f-9-3 2) (eq f-18-2 2)))
2739; (getter (mem32 xmode (indirect-addr (add Dsp-24-u16 (reg h-sb)))))
2740; (setter (set (mem32 xmode (indirect-addr (add Dsp-24-u16 (reg h-sb)))) newval))
2741; )
2742; (define-derived-operand
2743; (name (.sym src32-24-8-FB-relative-indirect- xmode))
2744; (comment (.str "m32c dsp:8[fb] relative source " xmode))
2745; (attrs (machine 32))
2746; (mode xmode)
2747; (args (Dsp-24-s8))
2748; (syntax "[${Dsp-24-s8}[fb]]")
2749; (base-ifield f-9-11)
2750; (encoding (+ (f-9-3 1) (f-18-2 3) Dsp-24-s8))
2751; (ifield-assertion (andif (eq f-9-3 1) (eq f-18-2 3)))
2752; (getter (mem32 xmode (indirect-addr (add Dsp-24-s8 (reg h-fb)))))
2753; (setter (set (mem32 xmode (indirect-addr (add Dsp-24-s8 (reg h-fb)))) newval))
2754; )
2755; (define-derived-operand
2756; (name (.sym src32-24-16-FB-relative-indirect- xmode))
2757; (comment (.str "m32c dsp:16[fb] relative source " xmode))
2758; (attrs (machine 32))
2759; (mode xmode)
2760; (args (Dsp-24-s16))
2761; (syntax "[${Dsp-24-s16}[fb]]")
2762; (base-ifield f-9-11)
2763; (encoding (+ (f-9-3 2) (f-18-2 3) Dsp-24-s16))
2764; (ifield-assertion (andif (eq f-9-3 2) (eq f-18-2 3)))
2765; (getter (mem32 xmode (indirect-addr (add Dsp-24-s16 (reg h-fb)))))
2766; (setter (set (mem32 xmode (indirect-addr (add Dsp-24-s16 (reg h-fb)))) newval))
2767; )
2768; (define-derived-operand
2769; (name (.sym src32-24-8-An-relative-indirect- xmode))
2770; (comment (.str "m32c dsp:8[An] relative indirect source " xmode))
2771; (attrs (machine 32))
2772; (mode xmode)
2773; (args (Src32AnPrefixed Dsp-24-u8))
2774; (syntax "[${Dsp-24-u8}[$Src32AnPrefixed]]")
2775; (base-ifield f-9-11)
2776; (encoding (+ (f-9-3 1) (f-18-1 0) Dsp-24-u8 Src32AnPrefixed))
2777; (ifield-assertion (andif (eq f-9-3 1) (eq f-18-1 0)))
2778; (getter (mem32 xmode (indirect-addr (add Dsp-24-u8 Src32AnPrefixed))))
2779; (setter (set (mem32 xmode (indirect-addr (add Dsp-24-u8 Src32AnPrefixed))) newval))
2780; )
2781; (define-derived-operand
2782; (name (.sym src32-24-16-An-relative-indirect- xmode))
2783; (comment (.str "m32c dsp:16[An] relative source " xmode))
2784; (attrs (machine 32))
2785; (mode xmode)
2786; (args (Src32AnPrefixed Dsp-24-u16))
2787; (syntax "[${Dsp-24-u16}[$Src32AnPrefixed]]")
2788; (base-ifield f-9-11)
2789; (encoding (+ (f-9-3 2) (f-18-1 0) Dsp-24-u16 Src32AnPrefixed))
2790; (ifield-assertion (andif (eq f-9-3 2) (eq f-18-1 0)))
2791; (getter (mem32 xmode (indirect-addr (add Dsp-24-u16 Src32AnPrefixed))))
2792; (setter (set (mem32 xmode (indirect-addr (add Dsp-24-u16 Src32AnPrefixed))) newval))
2793; )
2794; (define-derived-operand
2795; (name (.sym src32-24-24-An-relative-indirect- xmode))
2796; (comment (.str "m32c dsp:24[An] relative source " xmode))
2797; (attrs (machine 32))
2798; (mode xmode)
2799; (args (Src32AnPrefixed Dsp-24-u24))
2800; (syntax "[${Dsp-24-u24}[$Src32AnPrefixed]]")
2801; (base-ifield f-9-11)
2802; (encoding (+ (f-9-3 3) (f-18-1 0) Dsp-24-u24 Src32AnPrefixed))
2803; (ifield-assertion (andif (eq f-9-3 3) (eq f-18-1 0)))
2804; (getter (mem32 xmode (indirect-addr (add Dsp-24-u24 Src32AnPrefixed))))
2805; (setter (set (mem32 xmode (indirect-addr (add Dsp-24-u24 Src32AnPrefixed))) newval))
2806; )
2807 )
2808)
2809
2810; (src-relative-indirect-operand QI)
2811; (src-relative-indirect-operand HI)
2812; (src-relative-indirect-operand SI)
2813
2814;-------------------------------------------------------------
2815; Absolute Indirect address
2816;-------------------------------------------------------------
2817
2818(define-pmacro (src32-absolute-indirect offset base1 base2 xmode)
2819 (begin
2820; (define-derived-operand
2821; (name (.sym src32- offset -16-absolute-indirect-derived- xmode))
2822; (comment (.str "m32c absolute indirect address " xmode))
2823; (attrs (machine 32))
2824; (mode xmode)
2825; (args ((.sym Dsp- offset -u16)))
2826; (syntax (.str "[${Dsp-" offset "-u16}]"))
2827; (base-ifield (.sym f- base1 -11))
2828; (encoding (+ ((.sym f- base1 -3) 3) ((.sym f- base2 -2) 3) (.sym Dsp- offset -u16)))
2829; (ifield-assertion (andif (eq (.sym f- base1 -3) 3) (eq (.sym f- base2 -2) 3)))
2830; (getter (mem32 xmode (indirect-addr (.sym Dsp- offset -u16))))
2831; (setter (set (mem32 xmode (indirect-addr (.sym Dsp- offset -u16))) newval))
2832; )
2833; (define-derived-operand
2834; (name (.sym src32- offset -24-absolute-indirect-derived- xmode))
2835; (comment (.str "m32c absolute indirect address " xmode))
2836; (attrs (machine 32))
2837; (mode xmode)
2838; (args ((.sym Dsp- offset -u24)))
2839; (syntax (.str "[${Dsp-" offset "-u24}]"))
2840; (base-ifield (.sym f- base1 -11))
2841; (encoding (+ ((.sym f- base1 -3) 3) ((.sym f- base2 -2) 2) (.sym Dsp- offset -u24)))
2842; (ifield-assertion (andif (eq (.sym f- base1 -3) 3) (eq (.sym f- base2 -2) 2)))
2843; (getter (mem32 xmode (indirect-addr (.sym Dsp- offset -u24))))
2844; (setter (set (mem32 xmode (indirect-addr (.sym Dsp- offset -u24))) newval))
2845; )
2846 )
2847)
2848
2849(src32-absolute-indirect 24 9 18 QI)
2850(src32-absolute-indirect 24 9 18 HI)
2851(src32-absolute-indirect 24 9 18 SI)
2852
2853;-------------------------------------------------------------
2854; Register relative source operands for short format insns
2855;-------------------------------------------------------------
2856
2857(define-pmacro (src-2-S-operands mach xmode base opc1 opc2 opc3)
2858 (begin
2859 (define-derived-operand
2860 (name (.sym src mach -2-S-8-SB-relative- xmode))
2861 (comment (.str "m" mach "c SB relative address"))
2862 (attrs (machine mach))
2863 (mode xmode)
2864 (args (Dsp-8-u8))
2865 (syntax "${Dsp-8-u8}[sb]")
2866 (base-ifield (.sym f- base -2))
2867 (encoding (+ ((.sym f- base -2) opc1) Dsp-8-u8))
2868 (ifield-assertion (eq (.sym f- base -2) opc1))
2869 (getter (c-call xmode (.str "operand_getter_" xmode) sb Dsp-8-u8))
2870 (setter (c-call DFLT (.str "operand_setter_" xmode) newval sb Dsp-8-u8))
2871; (getter (mem-mach mach xmode (indirect-addr (add (reg h-sb) Dsp-8-u8))))
2872; (setter (set (mem-mach mach xmode (indirect-addr (add (reg h-sb) Dsp-8-u8))) newval))
2873 )
2874 (define-derived-operand
2875 (name (.sym src mach -2-S-8-FB-relative- xmode))
2876 (comment (.str "m" mach "c FB relative address"))
2877 (attrs (machine mach))
2878 (mode xmode)
2879 (args (Dsp-8-s8))
2880 (syntax "${Dsp-8-s8}[fb]")
2881 (base-ifield (.sym f- base -2))
2882 (encoding (+ ((.sym f- base -2) opc2) Dsp-8-s8))
2883 (ifield-assertion (eq (.sym f- base -2) opc2))
2884 (getter (c-call xmode (.str "operand_getter_" xmode) fb Dsp-8-s8))
2885 (setter (c-call DFLT (.str "operand_setter_" xmode) newval fb Dsp-8-s8))
2886; (getter (mem-mach mach xmode (indirect-addr (add (reg h-fb) Dsp-8-s8))))
2887; (setter (set (mem-mach mach xmode (indirect-addr (add (reg h-fb) Dsp-8-s8))) newval))
2888 )
2889 (define-derived-operand
2890 (name (.sym src mach -2-S-16-absolute- xmode))
2891 (comment (.str "m" mach "c absolute address"))
2892 (attrs (machine mach))
2893 (mode xmode)
2894 (args (Dsp-8-u16))
2895 (syntax "${Dsp-8-u16}")
2896 (base-ifield (.sym f- base -2))
2897 (encoding (+ ((.sym f- base -2) opc3) Dsp-8-u16))
2898 (ifield-assertion (eq (.sym f- base -2) opc3))
2899 (getter (c-call xmode (.str "operand_getter_" xmode) (const 0) Dsp-8-u16))
2900 (setter (c-call DFLT (.str "operand_setter_" xmode) newval (const 0) Dsp-8-u16))
2901; (getter (mem-mach mach xmode Dsp-8-u16))
2902; (setter (set (mem-mach mach xmode Dsp-8-u16) newval))
2903 )
2904 )
2905)
2906
2907(src-2-S-operands 16 QI 6 1 2 3)
2908(src-2-S-operands 32 QI 2 2 3 1)
2909(src-2-S-operands 32 HI 2 2 3 1)
2910
2911;=============================================================
2912; Derived Operands
2913;-------------------------------------------------------------
2914; Destination
2915;-------------------------------------------------------------
2916; Rn direct
2917;-------------------------------------------------------------
2918
2919(define-pmacro (dst16-Rn-direct-operand xmode)
2920 (begin
2921 (define-derived-operand
2922 (name (.sym dst16-Rn-direct- xmode))
2923 (comment (.str "m16c Rn direct destination " xmode))
2924 (attrs (machine 16))
2925 (mode xmode)
2926 (args ((.sym Dst16Rn xmode)))
2927 (syntax (.str "$Dst16Rn" xmode))
2928 (base-ifield f-12-4)
2929 (encoding (+ (f-12-2 0) (.sym Dst16Rn xmode)))
2930 (ifield-assertion (eq f-12-2 0))
2931 (getter (trunc xmode (.sym Dst16Rn xmode)))
2932 (setter (set (.sym Dst16Rn xmode) newval))
2933 )
2934 )
2935)
2936
2937(dst16-Rn-direct-operand QI)
2938(dst16-Rn-direct-operand HI)
2939(dst16-Rn-direct-operand SI)
2940
2941(define-derived-operand
2942 (name dst16-Rn-direct-Ext-QI)
2943 (comment "m16c Rn direct destination QI")
2944 (attrs (machine 16))
2945 (mode HI)
2946 (args (Dst16RnExtQI))
2947 (syntax "$Dst16RnExtQI")
2948 (base-ifield f-12-4)
2949 (encoding (+ (f-12-2 0) Dst16RnExtQI (f-15-1 0)))
2950 (ifield-assertion (andif (eq f-12-2 0) (eq f-15-1 0)))
2951 (getter (trunc QI (.sym Dst16RnExtQI)))
2952 (setter (set Dst16RnExtQI newval))
2953)
2954
2955(define-pmacro (dst32-Rn-direct-operand group base xmode)
2956 (begin
2957 (define-derived-operand
2958 (name (.sym dst32-Rn-direct- group - xmode))
2959 (comment (.str "m32c Rn direct destination " xmode))
2960 (attrs (machine 32))
2961 (mode xmode)
2962 (args ((.sym Dst32Rn group xmode)))
2963 (syntax (.str "$Dst32Rn" group xmode))
2964 (base-ifield (.sym f- base -6))
2965 (encoding (+ ((.sym f- base -3) 4) (.sym Dst32Rn group xmode)))
2966 (ifield-assertion (eq (.sym f- base -3) 4))
2967 (getter (trunc xmode (.sym Dst32Rn group xmode)))
2968 (setter (set (.sym Dst32Rn group xmode) newval))
2969 )
2970 )
2971)
2972
2973(dst32-Rn-direct-operand Unprefixed 4 QI)
2974(dst32-Rn-direct-operand Prefixed 12 QI)
2975(dst32-Rn-direct-operand Unprefixed 4 HI)
2976(dst32-Rn-direct-operand Prefixed 12 HI)
2977(dst32-Rn-direct-operand Unprefixed 4 SI)
2978(dst32-Rn-direct-operand Prefixed 12 SI)
2979
2980(define-pmacro (dst32-Rn-direct-Ext-operand group base1 base2 smode dmode)
2981 (begin
2982 (define-derived-operand
2983 (name (.sym dst32-Rn-direct- group - smode))
2984 (comment (.str "m32c Rn direct destination " smode))
2985 (attrs (machine 32))
2986 (mode dmode)
2987 (args ((.sym Dst32Rn group smode)))
2988 (syntax (.str "$Dst32Rn" group smode))
2989 (base-ifield (.sym f- base1 -6))
2990 (encoding (+ ((.sym f- base1 -3) 4) ((.sym f- base2 -1) 1) (.sym Dst32Rn group smode)))
2991 (ifield-assertion (andif (eq (.sym f- base1 -3) 4) (eq (.sym f- base2 -1) 1)))
2992 (getter (trunc smode (.sym Dst32Rn group smode)))
2993 (setter (set (.sym Dst32Rn group smode) newval))
2994 )
2995 )
2996)
2997
2998(dst32-Rn-direct-Ext-operand ExtUnprefixed 4 8 QI HI)
2999(dst32-Rn-direct-Ext-operand ExtUnprefixed 4 8 HI SI)
3000
3001(define-derived-operand
3002 (name dst32-R3-direct-Unprefixed-HI)
3003 (comment "m32c R3 direct HI")
3004 (attrs (machine 32))
3005 (mode HI)
3006 (args (R3))
3007 (syntax "$R3")
3008 (base-ifield f-4-6)
3009 (encoding (+ (f-4-3 4) (f-8-2 #x1)))
3010 (ifield-assertion (andif (eq f-4-3 4) (eq f-8-2 #x1)))
3011 (getter (trunc HI R3))
3012 (setter (set R3 newval))
3013)
3014;-------------------------------------------------------------
3015; An direct
3016;-------------------------------------------------------------
3017
3018(define-pmacro (dst16-An-direct-operand xmode)
3019 (begin
3020 (define-derived-operand
3021 (name (.sym dst16-An-direct- xmode))
3022 (comment (.str "m16c An direct destination " xmode))
3023 (attrs (machine 16))
3024 (mode xmode)
3025 (args ((.sym Dst16An xmode)))
3026 (syntax (.str "$Dst16An" xmode))
3027 (base-ifield f-12-4)
3028 (encoding (+ (f-12-2 1) (f-14-1 0) (.sym Dst16An xmode)))
3029 (ifield-assertion (andif (eq f-12-2 1) (eq f-14-1 0)))
3030 (getter (trunc xmode (.sym Dst16An xmode)))
3031 (setter (set (.sym Dst16An xmode) newval))
3032 )
3033 )
3034)
3035
3036(dst16-An-direct-operand QI)
3037(dst16-An-direct-operand HI)
3038(dst16-An-direct-operand SI)
3039
3040(define-pmacro (dst32-An-direct-operand group base1 base2 xmode)
3041 (begin
3042 (define-derived-operand
3043 (name (.sym dst32-An-direct- group - xmode))
3044 (comment (.str "m32c An direct destination " xmode))
3045 (attrs (machine 32))
3046 (mode xmode)
3047 (args ((.sym Dst32An group xmode)))
3048 (syntax (.str "$Dst32An" group xmode))
3049 (base-ifield (.sym f- base1 -6))
3050 (encoding (+ ((.sym f- base1 -3) 0) ((.sym f- base2 -1) 1) (.sym Dst32An group xmode)))
3051 (ifield-assertion (andif (eq (.sym f- base1 -3) 0) (eq (.sym f- base2 -1) 1)))
3052 (getter (trunc xmode (.sym Dst32An group xmode)))
3053 (setter (set (.sym Dst32An group xmode) newval))
3054 )
3055 )
3056)
3057
3058(dst32-An-direct-operand Unprefixed 4 8 QI)
3059(dst32-An-direct-operand Prefixed 12 16 QI)
3060(dst32-An-direct-operand Unprefixed 4 8 HI)
3061(dst32-An-direct-operand Prefixed 12 16 HI)
3062(dst32-An-direct-operand Unprefixed 4 8 SI)
3063(dst32-An-direct-operand Prefixed 12 16 SI)
3064
3065;-------------------------------------------------------------
3066; An indirect
3067;-------------------------------------------------------------
3068
3069(define-pmacro (dst16-An-indirect-operand xmode)
3070 (begin
3071 (define-derived-operand
3072 (name (.sym dst16-An-indirect- xmode))
3073 (comment (.str "m16c An indirect destination " xmode))
3074 (attrs (machine 16))
3075 (mode xmode)
3076 (args (Dst16An))
3077 (syntax "[$Dst16An]")
3078 (base-ifield f-12-4)
3079 (encoding (+ (f-12-2 1) (f-14-1 1) Dst16An))
3080 (ifield-assertion (andif (eq f-12-2 1) (eq f-14-1 1)))
3081 (getter (mem16 xmode Dst16An))
3082 (setter (set (mem16 xmode Dst16An) newval))
3083 )
3084 )
3085)
3086
3087(dst16-An-indirect-operand QI)
3088(dst16-An-indirect-operand HI)
3089(dst16-An-indirect-operand SI)
3090
3091(define-derived-operand
3092 (name dst16-An-indirect-Ext-QI)
3093 (comment "m16c An indirect destination QI")
3094 (attrs (machine 16))
3095 (mode HI)
3096 (args (Dst16An))
3097 (syntax "[$Dst16An]")
3098 (base-ifield f-12-4)
3099 (encoding (+ (f-12-2 1) (f-14-1 1) Dst16An))
3100 (ifield-assertion (andif (eq f-12-2 1) (eq f-14-1 1)))
3101 (getter (mem16 QI Dst16An))
3102 (setter (set (mem16 HI Dst16An) newval))
3103)
3104
3105(define-pmacro (dst32-An-indirect-operand group base1 base2 smode dmode)
3106 (begin
3107 (define-derived-operand
3108 (name (.sym dst32-An-indirect- group - smode))
3109 (comment (.str "m32c An indirect destination " smode))
3110 (attrs (machine 32))
3111 (mode dmode)
3112 (args ((.sym Dst32An group)))
3113 (syntax (.str "[$Dst32An" group "]"))
3114 (base-ifield (.sym f- base1 -6))
3115 (encoding (+ ((.sym f- base1 -3) 0) ((.sym f- base2 -1) 0) (.sym Dst32An group)))
3116 (ifield-assertion (andif (eq (.sym f- base1 -3) 0) (eq (.sym f- base2 -1) 0)))
3117 (getter (c-call dmode (.str "operand_getter_" dmode) (.sym Dst32An group)
3118 (const 0)))
3119 (setter (c-call DFLT (.str "operand_setter_" dmode) newval
3120 (.sym Dst32An group) (const 0)))
3121; (getter (mem32 smode (.sym Dst32An group)))
3122; (setter (set (mem32 dmode (.sym Dst32An group)) newval))
3123 )
3124 )
3125)
3126
3127(dst32-An-indirect-operand Unprefixed 4 8 QI QI)
3128(dst32-An-indirect-operand Prefixed 12 16 QI QI)
3129(dst32-An-indirect-operand Unprefixed 4 8 HI HI)
3130(dst32-An-indirect-operand Prefixed 12 16 HI HI)
3131(dst32-An-indirect-operand Unprefixed 4 8 SI SI)
3132(dst32-An-indirect-operand Prefixed 12 16 SI SI)
3133(dst32-An-indirect-operand ExtUnprefixed 4 8 QI HI)
3134(dst32-An-indirect-operand ExtUnprefixed 4 8 HI SI)
3135
3136;-------------------------------------------------------------
3137; dsp:d[r] relative
3138;-------------------------------------------------------------
3139
3140(define-pmacro (dst16-relative-operand offset xmode)
3141 (begin
3142 (define-derived-operand
3143 (name (.sym dst16- offset -8-SB-relative- xmode))
3144 (comment (.str "m16c dsp:8[sb] relative destination " xmode))
3145 (attrs (machine 16))
3146 (mode xmode)
3147 (args ((.sym Dsp- offset -u8)))
3148 (syntax (.str "${Dsp-" offset "-u8}[sb]"))
3149 (base-ifield f-12-4)
3150 (encoding (+ (f-12-4 #xA) (.sym Dsp- offset -u8)))
3151 (ifield-assertion (eq f-12-4 #xA))
3152 (getter (mem16 xmode (add (.sym Dsp- offset -u8) (reg h-sb))))
3153 (setter (set (mem16 xmode (add (.sym Dsp- offset -u8) (reg h-sb))) newval))
3154 )
3155 (define-derived-operand
3156 (name (.sym dst16- offset -16-SB-relative- xmode))
3157 (comment (.str "m16c dsp:16[sb] relative destination " xmode))
3158 (attrs (machine 16))
3159 (mode xmode)
3160 (args ((.sym Dsp- offset -u16)))
3161 (syntax (.str "${Dsp-" offset "-u16}[sb]"))
3162 (base-ifield f-12-4)
3163 (encoding (+ (f-12-4 #xE) (.sym Dsp- offset -u16)))
3164 (ifield-assertion (eq f-12-4 #xE))
3165 (getter (mem16 xmode (add (.sym Dsp- offset -u16) (reg h-sb))))
3166 (setter (set (mem16 xmode (add (.sym Dsp- offset -u16) (reg h-sb))) newval))
3167 )
3168 (define-derived-operand
3169 (name (.sym dst16- offset -8-FB-relative- xmode))
3170 (comment (.str "m16c dsp:8[fb] relative destination " xmode))
3171 (attrs (machine 16))
3172 (mode xmode)
3173 (args ((.sym Dsp- offset -s8)))
3174 (syntax (.str "${Dsp-" offset "-s8}[fb]"))
3175 (base-ifield f-12-4)
3176 (encoding (+ (f-12-4 #xB) (.sym Dsp- offset -s8)))
3177 (ifield-assertion (eq f-12-4 #xB))
3178 (getter (mem16 xmode (add (.sym Dsp- offset -s8) (reg h-fb))))
3179 (setter (set (mem16 xmode (add (.sym Dsp- offset -s8) (reg h-fb))) newval))
3180 )
3181 (define-derived-operand
3182 (name (.sym dst16- offset -8-An-relative- xmode))
3183 (comment (.str "m16c dsp:8[An] relative destination " xmode))
3184 (attrs (machine 16))
3185 (mode xmode)
3186 (args (Dst16An (.sym Dsp- offset -u8)))
3187 (syntax (.str "${Dsp-" offset "-u8}[$Dst16An]"))
3188 (base-ifield f-12-4)
3189 (encoding (+ (f-12-2 2) (f-14-1 0) (.sym Dsp- offset -u8) Dst16An))
3190 (ifield-assertion (andif (eq f-12-2 2) (eq f-14-1 0)))
3191 (getter (mem16 xmode (add (.sym Dsp- offset -u8) Dst16An)))
3192 (setter (set (mem16 xmode (add (.sym Dsp- offset -u8) Dst16An)) newval))
3193 )
3194 (define-derived-operand
3195 (name (.sym dst16- offset -16-An-relative- xmode))
3196 (comment (.str "m16c dsp:16[An] relative destination " xmode))
3197 (attrs (machine 16))
3198 (mode xmode)
3199 (args (Dst16An (.sym Dsp- offset -u16)))
3200 (syntax (.str "${Dsp-" offset "-u16}[$Dst16An]"))
3201 (base-ifield f-12-4)
3202 (encoding (+ (f-12-2 3) (f-14-1 0) (.sym Dsp- offset -u16) Dst16An))
3203 (ifield-assertion (andif (eq f-12-2 3) (eq f-14-1 0)))
3204 (getter (mem16 xmode (add (.sym Dsp- offset -u16) Dst16An)))
3205 (setter (set (mem16 xmode (add (.sym Dsp- offset -u16) Dst16An)) newval))
3206 )
75b06e7b
DD		 3207 (define-derived-operand
3208 (name (.sym dst16- offset -20-An-relative- xmode))
3209 (comment (.str "m16c dsp:20[An] relative destination " xmode))
3210 (attrs (machine 16))
3211 (mode xmode)
3212 (args (Dst16An (.sym Dsp- offset -u20)))
3213 (syntax (.str "${Dsp-" offset "-u20}[$Dst16An]"))
3214 (base-ifield f-12-4)
3215 (encoding (+ (f-12-2 3) (f-14-1 0) (.sym Dsp- offset -u20) Dst16An))
3216 (ifield-assertion (andif (eq f-12-2 3) (eq f-14-1 0)))
3217 (getter (mem16 xmode (add (.sym Dsp- offset -u20) Dst16An)))
3218 (setter (set (mem16 xmode (add (.sym Dsp- offset -u20) Dst16An)) newval))
3219 )
49f58d10
JB		 3220 )
3221)
3222
3223(dst16-relative-operand 16 QI)
3224(dst16-relative-operand 24 QI)
3225(dst16-relative-operand 32 QI)
3226(dst16-relative-operand 40 QI)
3227(dst16-relative-operand 48 QI)
3228(dst16-relative-operand 16 HI)
3229(dst16-relative-operand 24 HI)
3230(dst16-relative-operand 32 HI)
3231(dst16-relative-operand 40 HI)
3232(dst16-relative-operand 48 HI)
3233(dst16-relative-operand 16 SI)
3234(dst16-relative-operand 24 SI)
3235(dst16-relative-operand 32 SI)
3236(dst16-relative-operand 40 SI)
3237(dst16-relative-operand 48 SI)
3238
3239(define-pmacro (dst16-relative-Ext-operand offset smode dmode)
3240 (begin
3241 (define-derived-operand
3242 (name (.sym dst16- offset -8-SB-relative-Ext- smode))
3243 (comment (.str "m16c dsp:8[sb] relative destination " smode))
3244 (attrs (machine 16))
3245 (mode dmode)
3246 (args ((.sym Dsp- offset -u8)))
3247 (syntax (.str "${Dsp-" offset "-u8}[sb]"))
3248 (base-ifield f-12-4)
3249 (encoding (+ (f-12-4 #xA) (.sym Dsp- offset -u8)))
3250 (ifield-assertion (eq f-12-4 #xA))
3251 (getter (mem16 smode (add (.sym Dsp- offset -u8) (reg h-sb))))
3252 (setter (set (mem16 dmode (add (.sym Dsp- offset -u8) (reg h-sb))) newval))
3253 )
3254 (define-derived-operand
3255 (name (.sym dst16- offset -16-SB-relative-Ext- smode))
3256 (comment (.str "m16c dsp:16[sb] relative destination " smode))
3257 (attrs (machine 16))
3258 (mode dmode)
3259 (args ((.sym Dsp- offset -u16)))
3260 (syntax (.str "${Dsp-" offset "-u16}[sb]"))
3261 (base-ifield f-12-4)
3262 (encoding (+ (f-12-4 #xE) (.sym Dsp- offset -u16)))
3263 (ifield-assertion (eq f-12-4 #xE))
3264 (getter (mem16 smode (add (.sym Dsp- offset -u16) (reg h-sb))))
3265 (setter (set (mem16 dmode (add (.sym Dsp- offset -u16) (reg h-sb))) newval))
3266 )
3267 (define-derived-operand
3268 (name (.sym dst16- offset -8-FB-relative-Ext- smode))
3269 (comment (.str "m16c dsp:8[fb] relative destination " smode))
3270 (attrs (machine 16))
3271 (mode dmode)
3272 (args ((.sym Dsp- offset -s8)))
3273 (syntax (.str "${Dsp-" offset "-s8}[fb]"))
3274 (base-ifield f-12-4)
3275 (encoding (+ (f-12-4 #xB) (.sym Dsp- offset -s8)))
3276 (ifield-assertion (eq f-12-4 #xB))
3277 (getter (mem16 smode (add (.sym Dsp- offset -s8) (reg h-fb))))
3278 (setter (set (mem16 dmode (add (.sym Dsp- offset -s8) (reg h-fb))) newval))
3279 )
3280 (define-derived-operand
3281 (name (.sym dst16- offset -8-An-relative-Ext- smode))
3282 (comment (.str "m16c dsp:8[An] relative destination " smode))
3283 (attrs (machine 16))
3284 (mode dmode)
3285 (args (Dst16An (.sym Dsp- offset -u8)))
3286 (syntax (.str "${Dsp-" offset "-u8}[$Dst16An]"))
3287 (base-ifield f-12-4)
3288 (encoding (+ (f-12-2 2) (f-14-1 0) (.sym Dsp- offset -u8) Dst16An))
3289 (ifield-assertion (andif (eq f-12-2 2) (eq f-14-1 0)))
3290 (getter (mem16 smode (add (.sym Dsp- offset -u8) Dst16An)))
3291 (setter (set (mem16 dmode (add (.sym Dsp- offset -u8) Dst16An)) newval))
3292 )
3293 (define-derived-operand
3294 (name (.sym dst16- offset -16-An-relative-Ext- smode))
3295 (comment (.str "m16c dsp:16[An] relative destination " smode))
3296 (attrs (machine 16))
3297 (mode dmode)
3298 (args (Dst16An (.sym Dsp- offset -u16)))
3299 (syntax (.str "${Dsp-" offset "-u16}[$Dst16An]"))
3300 (base-ifield f-12-4)
3301 (encoding (+ (f-12-2 3) (f-14-1 0) (.sym Dsp- offset -u16) Dst16An))
3302 (ifield-assertion (andif (eq f-12-2 3) (eq f-14-1 0)))
3303 (getter (mem16 smode (add (.sym Dsp- offset -u16) Dst16An)))
3304 (setter (set (mem16 dmode (add (.sym Dsp- offset -u16) Dst16An)) newval))
3305 )
3306 )
3307)
3308
3309(dst16-relative-Ext-operand 16 QI HI)
3310
3311(define-pmacro (dst32-relative-operand offset group base1 base2 smode dmode)
3312 (begin
3313 (define-derived-operand
3314 (name (.sym dst32- offset -8-SB-relative- group - smode))
3315 (comment (.str "m32c dsp:8[sb] relative destination " smode))
3316 (attrs (machine 32))
3317 (mode dmode)
3318 (args ((.sym Dsp- offset -u8)))
3319 (syntax (.str "${Dsp-" offset "-u8}[sb]"))
3320 (base-ifield (.sym f- base1 -6))
3321 (encoding (+ ((.sym f- base1 -3) 1) ((.sym f- base2 -2) 2) (.sym Dsp- offset -u8)))
3322 (ifield-assertion (andif (eq (.sym f- base1 -3) 1) (eq (.sym f- base2 -2) 2)))
3323 (getter (c-call dmode (.str "operand_getter_" dmode) sb (.sym Dsp- offset -u8)))
3324 (setter (c-call DFLT (.str "operand_setter_" dmode) newval sb (.sym Dsp- offset -u8)))
3325; (getter (mem32 smode (add (.sym Dsp- offset -u8) (reg h-sb))))
3326; (setter (set (mem32 dmode (add (.sym Dsp- offset -u8) (reg h-sb))) newval))
3327 )
3328 (define-derived-operand
3329 (name (.sym dst32- offset -16-SB-relative- group - smode))
3330 (comment (.str "m32c dsp:16[sb] relative destination " smode))
3331 (attrs (machine 32))
3332 (mode dmode)
3333 (args ((.sym Dsp- offset -u16)))
3334 (syntax (.str "${Dsp-" offset "-u16}[sb]"))
3335 (base-ifield (.sym f- base1 -6))
3336 (encoding (+ ((.sym f- base1 -3) 2) ((.sym f- base2 -2) 2) (.sym Dsp- offset -u16)))
3337 (ifield-assertion (andif (eq (.sym f- base1 -3) 2) (eq (.sym f- base2 -2) 2)))
3338 (getter (c-call dmode (.str "operand_getter_" dmode) sb (.sym Dsp- offset -u16)))
3339 (setter (c-call DFLT (.str "operand_setter_" dmode) newval sb (.sym Dsp- offset -u16)))
3340; (getter (mem32 smode (add (.sym Dsp- offset -u16) (reg h-sb))))
3341; (setter (set (mem32 dmode (add (.sym Dsp- offset -u16) (reg h-sb))) newval))
3342 )
3343 (define-derived-operand
3344 (name (.sym dst32- offset -8-FB-relative- group - smode))
3345 (comment (.str "m32c dsp:8[fb] relative destination " smode))
3346 (attrs (machine 32))
3347 (mode dmode)
3348 (args ((.sym Dsp- offset -s8)))
3349 (syntax (.str "${Dsp-" offset "-s8}[fb]"))
3350 (base-ifield (.sym f- base1 -6))
3351 (encoding (+ ((.sym f- base1 -3) 1) ((.sym f- base2 -2) 3) (.sym Dsp- offset -s8)))
3352 (ifield-assertion (andif (eq (.sym f- base1 -3) 1) (eq (.sym f- base2 -2) 3)))
3353 (getter (c-call dmode (.str "operand_getter_" dmode) fb (.sym Dsp- offset -s8)))
3354 (setter (c-call DFLT (.str "operand_setter_" dmode) newval fb (.sym Dsp- offset -s8)))
3355; (getter (mem32 smode (add (.sym Dsp- offset -s8) (reg h-fb))))
3356; (setter (set (mem32 dmode (add (.sym Dsp- offset -s8) (reg h-fb))) newval))
3357 )
3358 (define-derived-operand
3359 (name (.sym dst32- offset -16-FB-relative- group - smode))
3360 (comment (.str "m32c dsp:16[fb] relative destination " smode))
3361 (attrs (machine 32))
3362 (mode dmode)
3363 (args ((.sym Dsp- offset -s16)))
3364 (syntax (.str "${Dsp-" offset "-s16}[fb]"))
3365 (base-ifield (.sym f- base1 -6))
3366 (encoding (+ ((.sym f- base1 -3) 2) ((.sym f- base2 -2) 3) (.sym Dsp- offset -s16)))
3367 (ifield-assertion (andif (eq (.sym f- base1 -3) 2) (eq (.sym f- base2 -2) 3)))
3368 (getter (c-call dmode (.str "operand_getter_" dmode) fb (.sym Dsp- offset -s16)))
3369 (setter (c-call DFLT (.str "operand_setter_" dmode) newval fb (.sym Dsp- offset -s16)))
3370; (getter (mem32 smode (add (.sym Dsp- offset -s16) (reg h-fb))))
3371; (setter (set (mem32 dmode (add (.sym Dsp- offset -s16) (reg h-fb))) newval))
3372 )
3373 (define-derived-operand
3374 (name (.sym dst32- offset -8-An-relative- group - smode))
3375 (comment (.str "m32c dsp:8[An] relative destination " smode))
3376 (attrs (machine 32))
3377 (mode dmode)
3378 (args ((.sym Dst32An group) (.sym Dsp- offset -u8)))
3379 (syntax (.str "${Dsp-" offset "-u8}[$Dst32An" group "]"))
3380 (base-ifield (.sym f- base1 -6))
3381 (encoding (+ ((.sym f- base1 -3) 1) ((.sym f- base2 -1) 0) (.sym Dsp- offset -u8) (.sym Dst32An group)))
3382 (ifield-assertion (andif (eq (.sym f- base1 -3) 1) (eq (.sym f- base2 -1) 0)))
3383 (getter (c-call dmode (.str "operand_getter_" dmode) (.sym Dst32An group) (.sym Dsp- offset -u8)))
3384 (setter (c-call DFLT (.str "operand_setter_" dmode) newval (.sym Dst32An group) (.sym Dsp- offset -u8)))
3385; (getter (mem32 smode (add (.sym Dsp- offset -u8) (.sym Dst32An group))))
3386; (setter (set (mem32 dmode (add (.sym Dsp- offset -u8) (.sym Dst32An group))) newval))
3387 )
3388 (define-derived-operand
3389 (name (.sym dst32- offset -16-An-relative- group - smode))
3390 (comment (.str "m32c dsp:16[An] relative destination " smode))
3391 (attrs (machine 32))
3392 (mode dmode)
3393 (args ((.sym Dst32An group) (.sym Dsp- offset -u16)))
3394 (syntax (.str "${Dsp-" offset "-u16}[$Dst32An" group "]"))
3395 (base-ifield (.sym f- base1 -6))
3396 (encoding (+ ((.sym f- base1 -3) 2) ((.sym f- base2 -1) 0) (.sym Dsp- offset -u16) (.sym Dst32An group)))
3397 (ifield-assertion (andif (eq (.sym f- base1 -3) 2) (eq (.sym f- base2 -1) 0)))
3398 (getter (c-call dmode (.str "operand_getter_" dmode) (.sym Dst32An group) (.sym Dsp- offset -u16)))
3399 (setter (c-call DFLT (.str "operand_setter_" dmode) newval (.sym Dst32An group) (.sym Dsp- offset -u16)))
3400; (getter (mem32 smode (add (.sym Dsp- offset -u16) (.sym Dst32An group))))
3401; (setter (set (mem32 dmode (add (.sym Dsp- offset -u16) (.sym Dst32An group))) newval))
3402 )
3403 (define-derived-operand
3404 (name (.sym dst32- offset -24-An-relative- group - smode))
3405 (comment (.str "m32c dsp:16[An] relative destination " smode))
3406 (attrs (machine 32))
3407 (mode dmode)
3408 (args ((.sym Dst32An group) (.sym Dsp- offset -u24)))
3409 (syntax (.str "${Dsp-" offset "-u24}[$Dst32An" group "]"))
3410 (base-ifield (.sym f- base1 -6))
3411 (encoding (+ ((.sym f- base1 -3) 3) ((.sym f- base2 -1) 0) (.sym Dsp- offset -u24) (.sym Dst32An group)))
3412 (ifield-assertion (andif (eq (.sym f- base1 -3) 3) (eq (.sym f- base2 -1) 0)))
3413 (getter (c-call dmode (.str "operand_getter_" dmode) (.sym Dst32An group) (.sym Dsp- offset -u24)))
3414 (setter (c-call DFLT (.str "operand_setter_" dmode) newval (.sym Dst32An group) (.sym Dsp- offset -u24)))
3415; (getter (mem32 smode (add (.sym Dsp- offset -u24) (.sym Dst32An group))))
3416; (setter (set (mem32 dmode (add (.sym Dsp- offset -u24) (.sym Dst32An group))) newval))
3417 )
3418 )
3419)
3420
3421(dst32-relative-operand 16 Unprefixed 4 8 QI QI)
3422(dst32-relative-operand 24 Unprefixed 4 8 QI QI)
3423(dst32-relative-operand 32 Unprefixed 4 8 QI QI)
3424(dst32-relative-operand 40 Unprefixed 4 8 QI QI)
3425(dst32-relative-operand 16 Unprefixed 4 8 HI HI)
3426(dst32-relative-operand 24 Unprefixed 4 8 HI HI)
3427(dst32-relative-operand 32 Unprefixed 4 8 HI HI)
3428(dst32-relative-operand 40 Unprefixed 4 8 HI HI)
3429(dst32-relative-operand 16 Unprefixed 4 8 SI SI)
3430(dst32-relative-operand 24 Unprefixed 4 8 SI SI)
3431(dst32-relative-operand 32 Unprefixed 4 8 SI SI)
3432(dst32-relative-operand 40 Unprefixed 4 8 SI SI)
3433
3434(dst32-relative-operand 24 Prefixed 12 16 QI QI)
3435(dst32-relative-operand 32 Prefixed 12 16 QI QI)
3436(dst32-relative-operand 40 Prefixed 12 16 QI QI)
3437(dst32-relative-operand 48 Prefixed 12 16 QI QI)
3438(dst32-relative-operand 24 Prefixed 12 16 HI HI)
3439(dst32-relative-operand 32 Prefixed 12 16 HI HI)
3440(dst32-relative-operand 40 Prefixed 12 16 HI HI)
3441(dst32-relative-operand 48 Prefixed 12 16 HI HI)
3442(dst32-relative-operand 24 Prefixed 12 16 SI SI)
3443(dst32-relative-operand 32 Prefixed 12 16 SI SI)
3444(dst32-relative-operand 40 Prefixed 12 16 SI SI)
3445(dst32-relative-operand 48 Prefixed 12 16 SI SI)
3446
3447(dst32-relative-operand 16 ExtUnprefixed 4 8 QI HI)
3448(dst32-relative-operand 16 ExtUnprefixed 4 8 HI SI)
3449
3450;-------------------------------------------------------------
3451; Absolute address
3452;-------------------------------------------------------------
3453
3454(define-pmacro (dst16-absolute offset xmode)
3455 (begin
3456 (define-derived-operand
3457 (name (.sym dst16- offset -16-absolute- xmode))
3458 (comment (.str "m16c absolute address " xmode))
3459 (attrs (machine 16))
3460 (mode xmode)
3461 (args ((.sym Dsp- offset -u16)))
3462 (syntax (.str "${Dsp-" offset "-u16}"))
3463 (base-ifield f-12-4)
3464 (encoding (+ (f-12-4 #xF) (.sym Dsp- offset -u16)))
3465 (ifield-assertion (eq f-12-4 #xF))
3466 (getter (mem16 xmode (.sym Dsp- offset -u16)))
3467 (setter (set (mem16 xmode (.sym Dsp- offset -u16)) newval))
3468 )
3469 )
3470)
3471
3472(dst16-absolute 16 QI)
3473(dst16-absolute 24 QI)
3474(dst16-absolute 32 QI)
3475(dst16-absolute 40 QI)
3476(dst16-absolute 48 QI)
3477(dst16-absolute 16 HI)
3478(dst16-absolute 24 HI)
3479(dst16-absolute 32 HI)
3480(dst16-absolute 40 HI)
3481(dst16-absolute 48 HI)
3482(dst16-absolute 16 SI)
3483(dst16-absolute 24 SI)
3484(dst16-absolute 32 SI)
3485(dst16-absolute 40 SI)
3486(dst16-absolute 48 SI)
3487
3488(define-derived-operand
3489 (name dst16-16-16-absolute-Ext-QI)
3490 (comment "m16c absolute address QI")
3491 (attrs (machine 16))
3492 (mode HI)
3493 (args (Dsp-16-u16))
3494 (syntax "${Dsp-16-u16}")
3495 (base-ifield f-12-4)
3496 (encoding (+ (f-12-4 #xF) Dsp-16-u16))
3497 (ifield-assertion (eq f-12-4 #xF))
3498 (getter (mem16 QI Dsp-16-u16))
3499 (setter (set (mem16 HI Dsp-16-u16) newval))
3500)
3501
3502(define-pmacro (dst32-absolute offset group base1 base2 smode dmode)
3503 (begin
3504 (define-derived-operand
3505 (name (.sym dst32- offset -16-absolute- group - smode))
3506 (comment (.str "m32c absolute address " smode))
3507 (attrs (machine 32))
3508 (mode dmode)
3509 (args ((.sym Dsp- offset -u16)))
3510 (syntax (.str "${Dsp-" offset "-u16}"))
3511 (base-ifield (.sym f- base1 -6))
3512 (encoding (+ ((.sym f- base1 -3) 3) ((.sym f- base2 -2) 3) (.sym Dsp- offset -u16)))
3513 (ifield-assertion (andif (eq (.sym f- base1 -3) 3) (eq (.sym f- base2 -2) 3)))
3514 (getter (c-call smode (.str "operand_getter_" smode) (const 0) (.sym Dsp- offset -u16)))
3515 (setter (c-call DFLT (.str "operand_setter_" dmode) newval (const 0) (.sym Dsp- offset -u16)))
3516; (getter (mem32 smode (.sym Dsp- offset -u16)))
3517; (setter (set (mem32 dmode (.sym Dsp- offset -u16)) newval))
3518 )
3519 (define-derived-operand
3520 (name (.sym dst32- offset -24-absolute- group - smode))
3521 (comment (.str "m32c absolute address " smode))
3522 (attrs (machine 32))
3523 (mode dmode)
3524 (args ((.sym Dsp- offset -u24)))
3525 (syntax (.str "${Dsp-" offset "-u24}"))
3526 (base-ifield (.sym f- base1 -6))
3527 (encoding (+ ((.sym f- base1 -3) 3) ((.sym f- base2 -2) 2) (.sym Dsp- offset -u24)))
3528 (ifield-assertion (andif (eq (.sym f- base1 -3) 3) (eq (.sym f- base2 -2) 2)))
3529 (getter (c-call smode (.str "operand_getter_" smode) (const 0) (.sym Dsp- offset -u24)))
3530 (setter (c-call DFLT (.str "operand_setter_" dmode) newval (const 0) (.sym Dsp- offset -u24)))
3531; (getter (mem32 smode (.sym Dsp- offset -u24)))
3532; (setter (set (mem32 dmode (.sym Dsp- offset -u24)) newval))
3533 )
3534 )
3535)
3536
3537(dst32-absolute 16 Unprefixed 4 8 QI QI)
3538(dst32-absolute 24 Unprefixed 4 8 QI QI)
3539(dst32-absolute 32 Unprefixed 4 8 QI QI)
3540(dst32-absolute 40 Unprefixed 4 8 QI QI)
3541(dst32-absolute 16 Unprefixed 4 8 HI HI)
3542(dst32-absolute 24 Unprefixed 4 8 HI HI)
3543(dst32-absolute 32 Unprefixed 4 8 HI HI)
3544(dst32-absolute 40 Unprefixed 4 8 HI HI)
3545(dst32-absolute 16 Unprefixed 4 8 SI SI)
3546(dst32-absolute 24 Unprefixed 4 8 SI SI)
3547(dst32-absolute 32 Unprefixed 4 8 SI SI)
3548(dst32-absolute 40 Unprefixed 4 8 SI SI)
3549
3550(dst32-absolute 24 Prefixed 12 16 QI QI)
3551(dst32-absolute 32 Prefixed 12 16 QI QI)
3552(dst32-absolute 40 Prefixed 12 16 QI QI)
3553(dst32-absolute 48 Prefixed 12 16 QI QI)
3554(dst32-absolute 24 Prefixed 12 16 HI HI)
3555(dst32-absolute 32 Prefixed 12 16 HI HI)
3556(dst32-absolute 40 Prefixed 12 16 HI HI)
3557(dst32-absolute 48 Prefixed 12 16 HI HI)
3558(dst32-absolute 24 Prefixed 12 16 SI SI)
3559(dst32-absolute 32 Prefixed 12 16 SI SI)
3560(dst32-absolute 40 Prefixed 12 16 SI SI)
3561(dst32-absolute 48 Prefixed 12 16 SI SI)
3562
3563(dst32-absolute 16 ExtUnprefixed 4 8 QI HI)
3564(dst32-absolute 16 ExtUnprefixed 4 8 HI SI)
3565
3566;-------------------------------------------------------------
3567; An indirect indirect
3568;-------------------------------------------------------------
3569
3570;(define-pmacro (dst-An-indirect-indirect-operand xmode)
3571; (define-derived-operand
3572; (name (.sym dst32-An-indirect-indirect- xmode))
3573; (comment (.str "m32c An indirect indirect destination " xmode))
3574; (attrs (machine 32))
3575; (mode xmode)
3576; (args (Dst32AnPrefixed))
3577; (syntax (.str "[[$Dst32AnPrefixed]]"))
3578; (base-ifield f-12-6)
3579; (encoding (+ (f-12-3 0) (f-16-1 0) Dst32AnPrefixed))
3580; (ifield-assertion (andif (eq f-12-3 0) (eq f-16-1 0)))
3581; (getter (mem32 xmode (indirect-addr Dst32AnPrefixed)))
3582; (setter (set (mem32 xmode (indirect-addr Dst32AnPrefixed)) newval))
3583; )
3584;)
3585
3586; (dst-An-indirect-indirect-operand QI)
3587; (dst-An-indirect-indirect-operand HI)
3588; (dst-An-indirect-indirect-operand SI)
3589
3590;-------------------------------------------------------------
3591; Relative indirect
3592;-------------------------------------------------------------
3593
3594(define-pmacro (dst-relative-indirect-operand offset xmode)
3595 (begin
3596; (define-derived-operand
3597; (name (.sym dst32- offset -8-SB-relative-indirect- xmode))
3598; (comment (.str "m32c dsp:8[sb] relative destination " xmode))
3599; (attrs (machine 32))
3600; (mode xmode)
3601; (args ((.sym Dsp- offset -u8)))
3602; (syntax (.str "[${Dsp-" offset "-u8}[sb]]"))
3603; (base-ifield f-12-6)
3604; (encoding (+ (f-12-3 1) (f-16-2 2) (.sym Dsp- offset -u8)))
3605; (ifield-assertion (andif (eq f-12-3 1) (eq f-16-2 2)))
3606; (getter (mem32 xmode (indirect-addr (add (.sym Dsp- offset -u8) (reg h-sb)))))
3607; (setter (set (mem32 xmode (indirect-addr (add (.sym Dsp- offset -u8) (reg h-sb)))) newval))
3608; )
3609; (define-derived-operand
3610; (name (.sym dst32- offset -16-SB-relative-indirect- xmode))
3611; (comment (.str "m32c dsp:16[sb] relative destination " xmode))
3612; (attrs (machine 32))
3613; (mode xmode)
3614; (args ((.sym Dsp- offset -u16)))
3615; (syntax (.str "[${Dsp-" offset "-u16}[sb]]"))
3616; (base-ifield f-12-6)
3617; (encoding (+ (f-12-3 2) (f-16-2 2) (.sym Dsp- offset -u16)))
3618; (ifield-assertion (andif (eq f-12-3 2) (eq f-16-2 2)))
3619; (getter (mem32 xmode (indirect-addr (add (.sym Dsp- offset -u16) (reg h-sb)))))
3620; (setter (set (mem32 xmode (indirect-addr (add (.sym Dsp- offset -u16) (reg h-sb)))) newval))
3621; )
3622; (define-derived-operand
3623; (name (.sym dst32- offset -8-FB-relative-indirect- xmode))
3624; (comment (.str "m32c dsp:8[fb] relative destination " xmode))
3625; (attrs (machine 32))
3626; (mode xmode)
3627; (args ((.sym Dsp- offset -s8)))
3628; (syntax (.str "[${Dsp-" offset "-s8}[fb]]"))
3629; (base-ifield f-12-6)
3630; (encoding (+ (f-12-3 1) (f-16-2 3) (.sym Dsp- offset -s8)))
3631; (ifield-assertion (andif (eq f-12-3 1) (eq f-16-2 3)))
3632; (getter (mem32 xmode (indirect-addr (add (.sym Dsp- offset -s8) (reg h-fb)))))
3633; (setter (set (mem32 xmode (indirect-addr (add (.sym Dsp- offset -s8) (reg h-fb)))) newval))
3634; )
3635; (define-derived-operand
3636; (name (.sym dst32- offset -16-FB-relative-indirect- xmode))
3637; (comment (.str "m32c dsp:16[fb] relative destination " xmode))
3638; (attrs (machine 32))
3639; (mode xmode)
3640; (args ((.sym Dsp- offset -s16)))
3641; (syntax (.str "[${Dsp-" offset "-s16}[fb]]"))
3642; (base-ifield f-12-6)
3643; (encoding (+ (f-12-3 2) (f-16-2 3) (.sym Dsp- offset -s16)))
3644; (ifield-assertion (andif (eq f-12-3 2) (eq f-16-2 3)))
3645; (getter (mem32 xmode (indirect-addr (add (.sym Dsp- offset -s16) (reg h-fb)))))
3646; (setter (set (mem32 xmode (indirect-addr (add (.sym Dsp- offset -s16) (reg h-fb)))) newval))
3647; )
3648; (define-derived-operand
3649; (name (.sym dst32- offset -8-An-relative-indirect- xmode))
3650; (comment (.str "m32c dsp:8[An] relative indirect destination " xmode))
3651; (attrs (machine 32))
3652; (mode xmode)
3653; (args (Dst32AnPrefixed (.sym Dsp- offset -u8)))
3654; (syntax (.str "[${Dsp-" offset "-u8}[$Dst32AnPrefixed]]"))
3655; (base-ifield f-12-6)
3656; (encoding (+ (f-12-3 1) (f-16-1 0) (.sym Dsp- offset -u8) Dst32AnPrefixed))
3657; (ifield-assertion (andif (eq f-12-3 1) (eq f-16-1 0)))
3658; (getter (mem32 xmode (indirect-addr (add (.sym Dsp- offset -u8) Dst32AnPrefixed))))
3659; (setter (set (mem32 xmode (indirect-addr (add (.sym Dsp- offset -u8) Dst32AnPrefixed))) newval))
3660; )
3661; (define-derived-operand
3662; (name (.sym dst32- offset -16-An-relative-indirect- xmode))
3663; (comment (.str "m32c dsp:16[An] relative destination " xmode))
3664; (attrs (machine 32))
3665; (mode xmode)
3666; (args (Dst32AnPrefixed (.sym Dsp- offset -u16)))
3667; (syntax (.str "[${Dsp-" offset "-u16}[$Dst32AnPrefixed]]"))
3668; (base-ifield f-12-6)
3669; (encoding (+ (f-12-3 2) (f-16-1 0) (.sym Dsp- offset -u16) Dst32AnPrefixed))
3670; (ifield-assertion (andif (eq f-12-3 2) (eq f-16-1 0)))
3671; (getter (mem32 xmode (indirect-addr (add (.sym Dsp- offset -u16) Dst32AnPrefixed))))
3672; (setter (set (mem32 xmode (indirect-addr (add (.sym Dsp- offset -u16) Dst32AnPrefixed))) newval))
3673; )
3674; (define-derived-operand
3675; (name (.sym dst32- offset -24-An-relative-indirect- xmode))
3676; (comment (.str "m32c dsp:24[An] relative destination " xmode))
3677; (attrs (machine 32))
3678; (mode xmode)
3679; (args (Dst32AnPrefixed (.sym Dsp- offset -u24)))
3680; (syntax (.str "[${Dsp-" offset "-u24}[$Dst32AnPrefixed]]"))
3681; (base-ifield f-12-6)
3682; (encoding (+ (f-12-3 3) (f-16-1 0) (.sym Dsp- offset -u24) Dst32AnPrefixed))
3683; (ifield-assertion (andif (eq f-12-3 3) (eq f-16-1 0)))
3684; (getter (mem32 xmode (indirect-addr (add (.sym Dsp- offset -u24) Dst32AnPrefixed))))
3685; (setter (set (mem32 xmode (indirect-addr (add (.sym Dsp- offset -u24) Dst32AnPrefixed))) newval))
3686; )
3687 )
3688)
3689
3690; (dst-relative-indirect-operand 24 QI)
3691; (dst-relative-indirect-operand 32 QI)
3692; (dst-relative-indirect-operand 40 QI)
3693; (dst-relative-indirect-operand 48 QI)
3694; (dst-relative-indirect-operand 24 HI)
3695; (dst-relative-indirect-operand 32 HI)
3696; (dst-relative-indirect-operand 40 HI)
3697; (dst-relative-indirect-operand 48 HI)
3698; (dst-relative-indirect-operand 24 SI)
3699; (dst-relative-indirect-operand 32 SI)
3700; (dst-relative-indirect-operand 40 SI)
3701; (dst-relative-indirect-operand 48 SI)
3702
3703;-------------------------------------------------------------
3704; Absolute indirect
3705;-------------------------------------------------------------
3706
3707(define-pmacro (dst-absolute-indirect offset xmode)
3708 (begin
3709; (define-derived-operand
3710; (name (.sym dst32- offset -16-absolute-indirect-derived- xmode))
3711; (comment (.str "m32c absolute indirect address " xmode))
3712; (attrs (machine 32))
3713; (mode xmode)
3714; (args ((.sym Dsp- offset -u16)))
3715; (syntax (.str "[${Dsp-" offset "-u16}]"))
3716; (base-ifield f-12-6)
3717; (encoding (+ (f-12-3 3) (f-16-2 3) (.sym Dsp- offset -u16)))
3718; (ifield-assertion (andif (eq f-12-3 3) (eq f-16-2 3)))
3719; (getter (mem32 xmode (indirect-addr (.sym Dsp- offset -u16))))
3720; (setter (set (mem32 xmode (indirect-addr (.sym Dsp- offset -u16))) newval))
3721; )
3722; (define-derived-operand
3723; (name (.sym dst32- offset -24-absolute-indirect-derived- xmode))
3724; (comment (.str "m32c absolute indirect address " xmode))
3725; (attrs (machine 32))
3726; (mode xmode)
3727; (args ((.sym Dsp- offset -u24)))
3728; (syntax (.str "[${Dsp-" offset "-u24}]"))
3729; (base-ifield f-12-6)
3730; (encoding (+ (f-12-3 3) (f-16-2 2) (.sym Dsp- offset -u24)))
3731; (ifield-assertion (andif (eq f-12-3 3) (eq f-16-2 2)))
3732; (getter (mem32 xmode (indirect-addr (.sym Dsp- offset -u24))))
3733; (setter (set (mem32 xmode (indirect-addr (.sym Dsp- offset -u24))) newval))
3734; )
3735 )
3736)
3737
3738(dst-absolute-indirect 24 QI)
3739(dst-absolute-indirect 32 QI)
3740(dst-absolute-indirect 40 QI)
3741(dst-absolute-indirect 48 QI)
3742(dst-absolute-indirect 24 HI)
3743(dst-absolute-indirect 32 HI)
3744(dst-absolute-indirect 40 HI)
3745(dst-absolute-indirect 48 HI)
3746(dst-absolute-indirect 24 SI)
3747(dst-absolute-indirect 32 SI)
3748(dst-absolute-indirect 40 SI)
3749(dst-absolute-indirect 48 SI)
3750
3751;-------------------------------------------------------------
3752; Bit operands
3753;-------------------------------------------------------------
3754(define-pmacro (get-register-bit reg bitno)
3755 (and (srl reg bitno) 1)
3756)
3757
3758(define-pmacro (set-register-bit reg bitno value)
3759 (set reg (or (and reg (inv (sll 1 bitno)))
3760 (sll (and QI value 1) bitno)))
3761)
3762
3763(define-pmacro (get-memory-bit mach base bitno)
3764 (and (srl (mem-mach mach QI (add base (div bitno 8)))
3765 (mod bitno 8))
3766 1)
3767)
3768
3769(define-pmacro (set-memory-bit mach base bitno value)
3770 (sequence ((USI addr))
3771 (set addr (add base (div bitno 8)))
3772 (set (mem-mach mach QI addr)
3773 (or (and (mem-mach mach QI addr)
3774 (inv (sll 1 (mod bitno 8))))
3775 (sll (and QI value 1) (mod bitno 8)))))
3776)
3777
3778;-------------------------------------------------------------
3779; Rn direct
3780;-------------------------------------------------------------
3781
3782(define-derived-operand
3783 (name bit16-Rn-direct)
3784 (comment "m16c Rn direct bit")
3785 (attrs (machine 16))
3786 (mode BI)
3787 (args (Bitno16R Bit16Rn))
3788 (syntax "$Bitno16R,$Bit16Rn")
3789 (base-ifield f-12-4)
3790 (encoding (+ (f-12-2 0) Bit16Rn Bitno16R))
3791 (ifield-assertion (eq f-12-2 0))
3792 (getter (get-register-bit Bit16Rn Bitno16R))
3793 (setter (set-register-bit Bit16Rn Bitno16R newval))
3794)
3795
3796(define-pmacro (bit32-Rn-direct-operand group base)
3797 (begin
3798 (define-derived-operand
3799 (name (.sym bit32-Rn-direct- group))
3800 (comment "m32c Rn direct bit")
3801 (attrs (machine 32))
3802 (mode BI)
3803 (args ((.sym Bitno32 group) (.sym Bit32Rn group)))
3804 (syntax (.str "$Bitno32" group ",$Bit32Rn" group))
3805 (base-ifield (.sym f- base -6))
3806 (encoding (+ ((.sym f- base -3) 4) (.sym Bit32Rn group) (.sym Bitno32 group)))
3807 (ifield-assertion (eq (.sym f- base -3) 4))
3808 (getter (get-register-bit (.sym Bit32Rn group) (.sym Bitno32 group)))
3809 (setter (set-register-bit (.sym Bit32Rn group) (.sym Bitno32 group) newval))
3810 )
3811 )
3812)
3813
3814(bit32-Rn-direct-operand Unprefixed 4)
3815(bit32-Rn-direct-operand Prefixed 12)
3816
3817;-------------------------------------------------------------
3818; An direct
3819;-------------------------------------------------------------
3820
3821(define-derived-operand
3822 (name bit16-An-direct)
3823 (comment "m16c An direct bit")
3824 (attrs (machine 16))
3825 (mode BI)
3826 (args (Bitno16R Bit16An))
3827 (syntax "$Bitno16R,$Bit16An")
3828 (base-ifield f-12-4)
3829 (encoding (+ (f-12-2 1) (f-14-1 0) Bit16An Bitno16R))
3830 (ifield-assertion (andif (eq f-12-2 1) (eq f-14-1 0)))
3831 (getter (get-register-bit Bit16An Bitno16R))
3832 (setter (set-register-bit Bit16An Bitno16R newval))
3833)
3834
3835(define-pmacro (bit32-An-direct-operand group base1 base2)
3836 (begin
3837 (define-derived-operand
3838 (name (.sym bit32-An-direct- group))
3839 (comment "m32c An direct bit")
3840 (attrs (machine 32))
3841 (mode BI)
3842 (args ((.sym Bitno32 group) (.sym Bit32An group)))
3843 (syntax (.str "$Bitno32" group ",$Bit32An" group))
3844 (base-ifield (.sym f- base1 -6))
3845 (encoding (+ ((.sym f- base1 -3) 0) ((.sym f- base2 -1) 1) (.sym Bit32An group) (.sym Bitno32 group)))
3846 (ifield-assertion (andif (eq (.sym f- base1 -3) 0) (eq (.sym f- base2 -1) 1)))
3847 (getter (get-register-bit (.sym Bit32An group) (.sym Bitno32 group)))
3848 (setter (set-register-bit (.sym Bit32An group) (.sym Bitno32 group) newval))
3849 )
3850 )
3851)
3852
3853(bit32-An-direct-operand Unprefixed 4 8)
3854(bit32-An-direct-operand Prefixed 12 16)
3855
3856;-------------------------------------------------------------
3857; An indirect
3858;-------------------------------------------------------------
3859
3860(define-derived-operand
3861 (name bit16-An-indirect)
3862 (comment "m16c An indirect bit")
3863 (attrs (machine 16))
3864 (mode BI)
3865 (args (Bit16An))
3866 (syntax "[$Bit16An]")
3867 (base-ifield f-12-4)
3868 (encoding (+ (f-12-2 1) (f-14-1 1) Bit16An))
3869 (ifield-assertion (andif (eq f-12-2 1) (eq f-14-1 1)))
3870 (getter (get-memory-bit 16 0 Bit16An))
3871 (setter (set-memory-bit 16 0 Bit16An newval))
3872)
3873
3874(define-pmacro (bit32-An-indirect-operand group base1 base2)
3875 (begin
3876 (define-derived-operand
3877 (name (.sym bit32-An-indirect- group))
3878 (comment "m32c An indirect destination ")
3879 (attrs (machine 32))
3880 (mode BI)
3881 (args ((.sym Bitno32 group) (.sym Bit32An group)))
3882 (syntax (.str "$Bitno32" group ",[$Bit32An" group "]"))
3883 (base-ifield (.sym f- base1 -6))
3884 (encoding (+ ((.sym f- base1 -3) 0) ((.sym f- base2 -1) 0) (.sym Bit32An group) (.sym Bitno32 group)))
3885 (ifield-assertion (andif (eq (.sym f- base1 -3) 0) (eq (.sym f- base2 -1) 0)))
3886 (getter (get-memory-bit 32 (.sym Bit32An group) (.sym Bitno32 group)))
3887 (setter (set-memory-bit 32 (.sym Bit32An group) (.sym Bitno32 group) newval))
3888 )
3889 )
3890)
3891
3892(bit32-An-indirect-operand Unprefixed 4 8)
3893(bit32-An-indirect-operand Prefixed 12 16)
3894
3895;-------------------------------------------------------------
3896; dsp:d[r] relative
3897;-------------------------------------------------------------
3898
3899(define-pmacro (bit16-relative-operand offset)
3900 (begin
3901 (define-derived-operand
3902 (name (.sym bit16- offset -8-SB-relative))
3903 (comment (.str "m16c dsp:8[sb] relative bit " xmode))
3904 (attrs (machine 16))
3905 (mode BI)
3906 (args ((.sym BitBase16- offset -u8)))
3907 (syntax (.str "${BitBase16-" offset "-u8}[sb]"))
3908 (base-ifield f-12-4)
3909 (encoding (+ (f-12-4 #xA) (.sym BitBase16- offset -u8)))
3910 (ifield-assertion (eq f-12-4 #xA))
3911 (getter (get-memory-bit 16 (reg h-sb) (.sym BitBase16- offset -u8)))
3912 (setter (set-memory-bit 16 (reg h-sb) (.sym BitBase16- offset -u8) newval))
3913 )
3914 (define-derived-operand
3915 (name (.sym bit16- offset -16-SB-relative))
3916 (comment (.str "m16c dsp:16[sb] relative bit " xmode))
3917 (attrs (machine 16))
3918 (mode BI)
3919 (args ((.sym BitBase16- offset -u16)))
3920 (syntax (.str "${BitBase16-" offset "-u16}[sb]"))
3921 (base-ifield f-12-4)
3922 (encoding (+ (f-12-4 #xE) (.sym BitBase16- offset -u16)))
3923 (ifield-assertion (eq f-12-4 #xE))
3924 (getter (get-memory-bit 16 (reg h-sb) (.sym BitBase16- offset -u16)))
3925 (setter (set-memory-bit 16 (reg h-sb) (.sym BitBase16- offset -u16) newval))
3926 )
3927 (define-derived-operand
3928 (name (.sym bit16- offset -8-FB-relative))
3929 (comment (.str "m16c dsp:8[fb] relative bit " xmode))
3930 (attrs (machine 16))
3931 (mode BI)
3932 (args ((.sym BitBase16- offset -s8)))
3933 (syntax (.str "${BitBase16-" offset "-s8}[fb]"))
3934 (base-ifield f-12-4)
3935 (encoding (+ (f-12-4 #xB) (.sym BitBase16- offset -s8)))
3936 (ifield-assertion (eq f-12-4 #xB))
3937 (getter (get-memory-bit 16 (reg h-fb) (.sym BitBase16- offset -s8)))
3938 (setter (set-memory-bit 16 (reg h-fb) (.sym BitBase16- offset -s8) newval))
3939 )
3940 (define-derived-operand
3941 (name (.sym bit16- offset -8-An-relative))
3942 (comment (.str "m16c dsp:8[An] relative bit " xmode))
3943 (attrs (machine 16))
3944 (mode BI)
3945 (args (Bit16An (.sym Dsp- offset -u8)))
3946 (syntax (.str "${Dsp-" offset "-u8}[$Bit16An]"))
3947 (base-ifield f-12-4)
3948 (encoding (+ (f-12-2 2) (f-14-1 0) (.sym Dsp- offset -u8) Bit16An))
3949 (ifield-assertion (andif (eq f-12-2 2) (eq f-14-1 0)))
3950 (getter (get-memory-bit 16 (.sym Dsp- offset -u8) Bit16An))
3951 (setter (set-memory-bit 16 (.sym Dsp- offset -u8) Bit16An newval))
3952 )
3953 (define-derived-operand
3954 (name (.sym bit16- offset -16-An-relative))
3955 (comment (.str "m16c dsp:16[An] relative bit " xmode))
3956 (attrs (machine 16))
3957 (mode BI)
3958 (args (Bit16An (.sym Dsp- offset -u16)))
3959 (syntax (.str "${Dsp-" offset "-u16}[$Bit16An]"))
3960 (base-ifield f-12-4)
3961 (encoding (+ (f-12-2 3) (f-14-1 0) (.sym Dsp- offset -u16) Bit16An))
3962 (ifield-assertion (andif (eq f-12-2 3) (eq f-14-1 0)))
3963 (getter (get-memory-bit 16 (.sym Dsp- offset -u16) Bit16An))
3964 (setter (set-memory-bit 16 (.sym Dsp- offset -u16) Bit16An newval))
3965 )
3966 )
3967)
3968
3969(bit16-relative-operand 16)
3970
3971(define-pmacro (bit32-relative-operand offset group base1 base2)
3972 (begin
3973 (define-derived-operand
3974 (name (.sym bit32- offset -11-SB-relative- group))
3975 (comment "m32c bit,base:11[sb] relative bit")
3976 (attrs (machine 32))
3977 (mode BI)
3978 (args ((.sym BitBase32- offset -u11- group)))
3979 (syntax (.str "${BitBase32-" offset "-u11-" group "}[sb]"))
3980 (base-ifield (.sym f- base1 -12))
3981 (encoding (+ ((.sym f- base1 -3) 1) ((.sym f- base2 -2) 2) (.sym BitBase32- offset -u11- group)))
3982 (ifield-assertion (andif (eq (.sym f- base1 -3) 1) (eq (.sym f- base2 -2) 2)))
3983 (getter (get-memory-bit 32 (reg h-sb) (.sym BitBase32- offset -u11- group)))
3984 (setter (set-memory-bit 32 (reg h-sb) (.sym BitBase32- offset -u11- group) newval))
3985 )
3986 (define-derived-operand
3987 (name (.sym bit32- offset -19-SB-relative- group))
3988 (comment "m32c bit,base:19[sb] relative bit")
3989 (attrs (machine 32))
3990 (mode BI)
3991 (args ((.sym BitBase32- offset -u19- group)))
3992 (syntax (.str "${BitBase32-" offset "-u19-" group "}[sb]"))
3993 (base-ifield (.sym f- base1 -12))
3994 (encoding (+ ((.sym f- base1 -3) 2) ((.sym f- base2 -2) 2) (.sym BitBase32- offset -u19- group)))
3995 (ifield-assertion (andif (eq (.sym f- base1 -3) 2) (eq (.sym f- base2 -2) 2)))
3996 (getter (get-memory-bit 32 (reg h-sb) (.sym BitBase32- offset -u19- group)))
3997 (setter (set-memory-bit 32 (reg h-sb) (.sym BitBase32- offset -u19- group) newval))
3998 )
3999 (define-derived-operand
4000 (name (.sym bit32- offset -11-FB-relative- group))
4001 (comment "m32c bit,base:11[fb] relative bit")
4002 (attrs (machine 32))
4003 (mode BI)
4004 (args ((.sym BitBase32- offset -s11- group)))
4005 (syntax (.str "${BitBase32-" offset "-s11-" group "}[fb]"))
4006 (base-ifield (.sym f- base1 -12))
4007 (encoding (+ ((.sym f- base1 -3) 1) ((.sym f- base2 -2) 3) (.sym BitBase32- offset -s11- group)))
4008 (ifield-assertion (andif (eq (.sym f- base1 -3) 1) (eq (.sym f- base2 -2) 3)))
4009 (getter (get-memory-bit 32 (reg h-fb) (.sym BitBase32- offset -s11- group)))
4010 (setter (set-memory-bit 32 (reg h-fb) (.sym BitBase32- offset -s11- group) newval))
4011 )
4012 (define-derived-operand
4013 (name (.sym bit32- offset -19-FB-relative- group))
4014 (comment "m32c bit,base:19[fb] relative bit")
4015 (attrs (machine 32))
4016 (mode BI)
4017 (args ((.sym BitBase32- offset -s19- group)))
4018 (syntax (.str "${BitBase32-" offset "-s19-" group "}[fb]"))
4019 (base-ifield (.sym f- base1 -12))
4020 (encoding (+ ((.sym f- base1 -3) 2) ((.sym f- base2 -2) 3) (.sym BitBase32- offset -s19- group)))
4021 (ifield-assertion (andif (eq (.sym f- base1 -3) 2) (eq (.sym f- base2 -2) 3)))
4022 (getter (get-memory-bit 32 (reg h-fb) (.sym BitBase32- offset -s19- group)))
4023 (setter (set-memory-bit 32 (reg h-fb) (.sym BitBase32- offset -s19- group) newval))
4024 )
4025 (define-derived-operand
4026 (name (.sym bit32- offset -11-An-relative- group))
4027 (comment "m32c bit,base:11[An] relative bit")
4028 (attrs (machine 32))
4029 (mode BI)
4030 (args ((.sym BitBase32- offset -u11- group) (.sym Bit32An group)))
4031 (syntax (.str "${BitBase32-" offset "-u11-" group "}[$Bit32An" group "]"))
4032 (base-ifield (.sym f- base1 -12))
4033 (encoding (+ ((.sym f- base1 -3) 1) ((.sym f- base2 -1) 0) (.sym BitBase32- offset -u11- group) (.sym Bit32An group)))
4034 (ifield-assertion (andif (eq (.sym f- base1 -3) 1) (eq (.sym f- base2 -1) 0)))
4035 (getter (get-memory-bit 32 (.sym Bit32An group) (.sym BitBase32- offset -u11- group)))
4036 (setter (set-memory-bit 32 (.sym Bit32An group) (.sym BitBase32- offset -u11- group) newval))
4037 )
4038 (define-derived-operand
4039 (name (.sym bit32- offset -19-An-relative- group))
4040 (comment "m32c bit,base:19[An] relative bit")
4041 (attrs (machine 32))
4042 (mode BI)
4043 (args ((.sym BitBase32- offset -u19- group) (.sym Bit32An group)))
4044 (syntax (.str "${BitBase32-" offset "-u19-" group "}[$Bit32An" group "]"))
4045 (base-ifield (.sym f- base1 -12))
4046 (encoding (+ ((.sym f- base1 -3) 2) ((.sym f- base2 -1) 0) (.sym BitBase32- offset -u19- group) (.sym Bit32An group)))
4047 (ifield-assertion (andif (eq (.sym f- base1 -3) 2) (eq (.sym f- base2 -1) 0)))
4048 (getter (get-memory-bit 32 (.sym Bit32An group) (.sym BitBase32- offset -u19- group)))
4049 (setter (set-memory-bit 32 (.sym Bit32An group) (.sym BitBase32- offset -u19- group) newval))
4050 )
4051 (define-derived-operand
4052 (name (.sym bit32- offset -27-An-relative- group))
4053 (comment "m32c bit,base:27[An] relative bit")
4054 (attrs (machine 32))
4055 (mode BI)
4056 (args ((.sym BitBase32- offset -u27- group) (.sym Bit32An group)))
4057 (syntax (.str "${BitBase32-" offset "-u27-" group "}[$Bit32An" group "]"))
4058 (base-ifield (.sym f- base1 -12))
4059 (encoding (+ ((.sym f- base1 -3) 3) ((.sym f- base2 -1) 0) (.sym BitBase32- offset -u27- group) (.sym Bit32An group)))
4060 (ifield-assertion (andif (eq (.sym f- base1 -3) 3) (eq (.sym f- base2 -1) 0)))
4061 (getter (get-memory-bit 32 (.sym Bit32An group) (.sym BitBase32- offset -u27- group)))
4062 (setter (set-memory-bit 32 (.sym Bit32An group) (.sym BitBase32- offset -u27- group) newval))
4063 )
4064 )
4065)
4066
4067(bit32-relative-operand 16 Unprefixed 4 8)
4068(bit32-relative-operand 24 Prefixed 12 16)
4069
4070(define-derived-operand
4071 (name bit16-11-SB-relative-S)
4072 (comment "m16c bit,base:11[sb] relative bit")
4073 (attrs (machine 16))
4074 (mode BI)
4075 (args (BitBase16-8-u11-S))
4076 (syntax "${BitBase16-8-u11-S}[sb]")
4077 (base-ifield (.sym f-5-3))
4078 (encoding (+ BitBase16-8-u11-S))
4079; (ifield-assertion (#t))
4080 (getter (get-memory-bit 16 (reg h-sb) BitBase16-8-u11-S))
4081 (setter (set-memory-bit 16 (reg h-sb) BitBase16-8-u11-S newval))
4082)
4083
4084(define-derived-operand
4085 (name Rn16-push-S-derived)
4086 (comment "m16c r0[lh] for push,pop short version")
4087 (attrs (machine 16))
4088 (mode QI)
4089 (args (Rn16-push-S))
4090 (syntax "${Rn16-push-S}")
4091 (base-ifield (.sym f-4-1))
4092 (encoding (+ Rn16-push-S))
4093; (ifield-assertion (#t))
4094 (getter (trunc QI Rn16-push-S))
4095 (setter (set Rn16-push-S newval))
4096)
4097
4098(define-derived-operand
4099 (name An16-push-S-derived)
4100 (comment "m16c r0[lh] for push,pop short version")
4101 (attrs (machine 16))
4102 (mode HI)
4103 (args (An16-push-S))
4104 (syntax "${An16-push-S}")
4105 (base-ifield (.sym f-4-1))
4106 (encoding (+ An16-push-S))
4107; (ifield-assertion (#t))
4108 (getter (trunc QI An16-push-S))
4109 (setter (set An16-push-S newval))
4110)
4111
4112;-------------------------------------------------------------
4113; Absolute address
4114;-------------------------------------------------------------
4115
4116(define-pmacro (bit16-absolute offset)
4117 (begin
4118 (define-derived-operand
4119 (name (.sym bit16- offset -16-absolute))
4120 (comment "m16c absolute address")
4121 (attrs (machine 16))
4122 (mode BI)
4123 (args ((.sym BitBase16- offset -u16)))
4124 (syntax (.str "${BitBase16-" offset "-u16}"))
4125 (base-ifield f-12-4)
4126 (encoding (+ (f-12-4 #xF) (.sym BitBase16- offset -u16)))
4127 (ifield-assertion (eq f-12-4 #xF))
4128 (getter (get-memory-bit 16 0 (.sym BitBase16- offset -u16)))
4129 (setter (set-memory-bit 16 0 (.sym BitBase16- offset -u16) newval))
4130 )
4131 )
4132)
4133
4134(bit16-absolute 16)
4135
4136(define-pmacro (bit32-absolute offset group base1 base2)
4137 (begin
4138 (define-derived-operand
4139 (name (.sym bit32- offset -19-absolute- group))
4140 (comment "m32c absolute address bit")
4141 (attrs (machine 32))
4142 (mode BI)
4143 (args ((.sym BitBase32- offset -u19- group)))
4144 (syntax (.str "${BitBase32-" offset "-u19-" group "}"))
4145 (base-ifield (.sym f- base1 -12))
4146 (encoding (+ ((.sym f- base1 -3) 3) ((.sym f- base2 -2) 3) (.sym BitBase32- offset -u19- group)))
4147 (ifield-assertion (andif (eq (.sym f- base1 -3) 3) (eq (.sym f- base2 -2) 3)))
4148 (getter (get-memory-bit 32 0 (.sym BitBase32- offset -u19- group)))
4149 (setter (set-memory-bit 32 0 (.sym BitBase32- offset -u19- group) newval))
4150 )
4151 (define-derived-operand
4152 (name (.sym bit32- offset -27-absolute- group))
4153 (comment "m32c absolute address bit")
4154 (attrs (machine 32))
4155 (mode BI)
4156 (args ((.sym BitBase32- offset -u27- group)))
4157 (syntax (.str "${BitBase32-" offset "-u27-" group "}"))
4158 (base-ifield (.sym f- base1 -12))
4159 (encoding (+ ((.sym f- base1 -3) 3) ((.sym f- base2 -2) 2) (.sym BitBase32- offset -u27- group)))
4160 (ifield-assertion (andif (eq (.sym f- base1 -3) 3) (eq (.sym f- base2 -2) 2)))
4161 (getter (get-memory-bit 32 0 (.sym BitBase32- offset -u27- group)))
4162 (setter (set-memory-bit 32 0 (.sym BitBase32- offset -u27- group) newval))
4163 )
4164 )
4165)
4166
4167(bit32-absolute 16 Unprefixed 4 8)
4168(bit32-absolute 24 Prefixed 12 16)
4169
4170;-------------------------------------------------------------
4171; Destination operands for short fomat insns
4172;-------------------------------------------------------------
4173
4174(define-derived-operand
4175 (name dst16-3-S-R0l-direct-QI)
4176 (comment "m16c R0l direct QI")
4177 (attrs (machine 16))
4178 (mode QI)
4179 (args (R0l))
4180 (syntax "r0l")
4181 (base-ifield f-5-3)
4182 (encoding (+ (f-5-3 4)))
4183 (ifield-assertion (eq f-5-3 4))
4184 (getter (trunc QI R0l))
4185 (setter (set R0l newval))
4186)
4187(define-derived-operand
4188 (name dst16-3-S-R0h-direct-QI)
4189 (comment "m16c R0h direct QI")
4190 (attrs (machine 16))
4191 (mode QI)
4192 (args (R0h))
4193 (syntax "r0h")
4194 (base-ifield f-5-3)
4195 (encoding (+ (f-5-3 3)))
4196 (ifield-assertion (eq f-5-3 3))
4197 (getter (trunc QI R0h))
4198 (setter (set R0h newval))
4199)
4200(define-derived-operand
4201 (name dst16-3-S-8-8-SB-relative-QI)
4202 (comment "m16c SB relative QI")
4203 (attrs (machine 16))
4204 (mode QI)
4205 (args (Dsp-8-u8))
4206 (syntax "${Dsp-8-u8}[sb]")
4207 (base-ifield f-5-3)
4208 (encoding (+ (f-5-3 5) Dsp-8-u8))
4209 (ifield-assertion (eq f-5-3 5))
4210 (getter (mem16 QI (add Dsp-8-u8 (reg h-sb))))
4211 (setter (set (mem16 QI (add Dsp-8-u8 (reg h-sb))) newval))
4212)
4213(define-derived-operand
4214 (name dst16-3-S-8-8-FB-relative-QI)
4215 (comment "m16c FB relative QI")
4216 (attrs (machine 16))
4217 (mode QI)
4218 (args (Dsp-8-s8))
4219 (syntax "${Dsp-8-s8}[fb]")
4220 (base-ifield f-5-3)
4221 (encoding (+ (f-5-3 6) Dsp-8-s8))
4222 (ifield-assertion (eq f-5-3 6))
4223 (getter (mem16 QI (add Dsp-8-s8 (reg h-fb))))
4224 (setter (set (mem16 QI (add Dsp-8-s8 (reg h-fb))) newval))
4225)
4226(define-derived-operand
4227 (name dst16-3-S-8-16-absolute-QI)
4228 (comment "m16c absolute address QI")
4229 (attrs (machine 16))
4230 (mode QI)
4231 (args (Dsp-8-u16))
4232 (syntax "${Dsp-8-u16}")
4233 (base-ifield f-5-3)
4234 (encoding (+ (f-5-3 7) Dsp-8-u16))
4235 (ifield-assertion (eq f-5-3 7))
4236 (getter (mem16 QI Dsp-8-u16))
4237 (setter (set (mem16 QI Dsp-8-u16) newval))
4238)
4239(define-derived-operand
4240 (name dst16-3-S-16-8-SB-relative-QI)
4241 (comment "m16c SB relative QI")
4242 (attrs (machine 16))
4243 (mode QI)
4244 (args (Dsp-16-u8))
4245 (syntax "${Dsp-16-u8}[sb]")
4246 (base-ifield f-5-3)
4247 (encoding (+ (f-5-3 5) Dsp-16-u8))
4248 (ifield-assertion (eq f-5-3 5))
4249 (getter (mem16 QI (add Dsp-16-u8 (reg h-sb))))
4250 (setter (set (mem16 QI (add Dsp-16-u8 (reg h-sb))) newval))
4251)
4252(define-derived-operand
4253 (name dst16-3-S-16-8-FB-relative-QI)
4254 (comment "m16c FB relative QI")
4255 (attrs (machine 16))
4256 (mode QI)
4257 (args (Dsp-16-s8))
4258 (syntax "${Dsp-16-s8}[fb]")
4259 (base-ifield f-5-3)
4260 (encoding (+ (f-5-3 6) Dsp-16-s8))
4261 (ifield-assertion (eq f-5-3 6))
4262 (getter (mem16 QI (add Dsp-16-s8 (reg h-fb))))
4263 (setter (set (mem16 QI (add Dsp-16-s8 (reg h-fb))) newval))
4264)
4265(define-derived-operand
4266 (name dst16-3-S-16-16-absolute-QI)
4267 (comment "m16c absolute address QI")
4268 (attrs (machine 16))
4269 (mode QI)
4270 (args (Dsp-16-u16))
4271 (syntax "${Dsp-16-u16}")
4272 (base-ifield f-5-3)
4273 (encoding (+ (f-5-3 7) Dsp-16-u16))
4274 (ifield-assertion (eq f-5-3 7))
4275 (getter (mem16 QI Dsp-16-u16))
4276 (setter (set (mem16 QI Dsp-16-u16) newval))
4277)
4278(define-derived-operand
4279 (name srcdst16-r0l-r0h-S-derived)
4280 (comment "m16c r0l/r0h operand for short format insns")
4281 (attrs (machine 16))
4282 (mode SI)
4283 (args (SrcDst16-r0l-r0h-S-normal))
4284 (syntax "${SrcDst16-r0l-r0h-S-normal}")
4285 (base-ifield f-6-3)
4286 (encoding (+ (f-6-2 0) SrcDst16-r0l-r0h-S-normal))
4287 (ifield-assertion (eq f-6-2 0))
4288 (getter (trunc SI SrcDst16-r0l-r0h-S-normal))
4289 (setter ()) ; no setter
4290)
4291(define-derived-operand
4292 (name dst32-2-S-R0l-direct-QI)
4293 (comment "m32c R0l direct QI")
4294 (attrs (machine 32))
4295 (mode QI)
4296 (args (R0l))
4297 (syntax "r0l")
4298 (base-ifield f-2-2)
4299 (encoding (+ (f-2-2 0)))
4300 (ifield-assertion (eq f-2-2 0))
4301 (getter (trunc QI R0l))
4302 (setter (set R0l newval))
4303)
4304(define-derived-operand
4305 (name dst32-2-S-R0-direct-HI)
4306 (comment "m32c R0 direct HI")
4307 (attrs (machine 32))
4308 (mode HI)
4309 (args (R0))
4310 (syntax "r0")
4311 (base-ifield f-2-2)
4312 (encoding (+ (f-2-2 0)))
4313 (ifield-assertion (eq f-2-2 0))
4314 (getter (trunc HI R0))
4315 (setter (set R0 newval))
4316)
4317(define-derived-operand
4318 (name dst32-1-S-A0-direct-HI)
4319 (comment "m32c A0 direct HI")
4320 (attrs (machine 32))
4321 (mode HI)
4322 (args (A0))
4323 (syntax "a0")
4324 (base-ifield f-7-1)
4325 (encoding (+ (f-7-1 0)))
4326 (ifield-assertion (eq f-7-1 0))
4327 (getter (trunc HI A0))
4328 (setter (set A0 newval))
4329)
4330(define-derived-operand
4331 (name dst32-1-S-A1-direct-HI)
4332 (comment "m32c A1 direct HI")
4333 (attrs (machine 32))
4334 (mode HI)
4335 (args (A1))
4336 (syntax "a1")
4337 (base-ifield f-7-1)
4338 (encoding (+ (f-7-1 1)))
4339 (ifield-assertion (eq f-7-1 1))
4340 (getter (trunc HI A1))
4341 (setter (set A1 newval))
4342)
4343(define-pmacro (dst32-2-S-operands xmode)
4344 (begin
4345 (define-derived-operand
4346 (name (.sym dst32-2-S-8-SB-relative- xmode))
4347 (comment "m32c SB relative for short binary insns")
4348 (attrs (machine 32))
4349 (mode xmode)
4350 (args (Dsp-8-u8))
4351 (syntax "${Dsp-8-u8}[sb]")
4352 (base-ifield f-2-2)
4353 (encoding (+ (f-2-2 2) Dsp-8-u8))
4354 (ifield-assertion (eq f-2-2 2))
4355 (getter (c-call xmode (.str "operand_getter_" xmode) sb Dsp-8-u8))
4356 (setter (c-call DFLT (.str "operand_setter_" xmode) newval sb Dsp-8-u8))
4357; (getter (mem32 xmode (add Dsp-8-u8 (reg h-sb))))
4358; (setter (set (mem32 xmode (add Dsp-8-u8 (reg h-sb))) newval))
4359 )
4360 (define-derived-operand
4361 (name (.sym dst32-2-S-8-FB-relative- xmode))
4362 (comment "m32c FB relative for short binary insns")
4363 (attrs (machine 32))
4364 (mode xmode)
4365 (args (Dsp-8-s8))
4366 (syntax "${Dsp-8-s8}[fb]")
4367 (base-ifield f-2-2)
4368 (encoding (+ (f-2-2 3) Dsp-8-s8))
4369 (ifield-assertion (eq f-2-2 3))
4370 (getter (c-call xmode (.str "operand_getter_" xmode) fb Dsp-8-s8))
4371 (setter (c-call DFLT (.str "operand_setter_" xmode) newval fb Dsp-8-s8))
4372; (getter (mem32 xmode (add Dsp-8-s8 (reg h-fb))))
4373; (setter (set (mem32 xmode (add Dsp-8-s8 (reg h-fb))) newval))
4374 )
4375 (define-derived-operand
4376 (name (.sym dst32-2-S-16-absolute- xmode))
4377 (comment "m32c absolute address for short binary insns")
4378 (attrs (machine 32))
4379 (mode xmode)
4380 (args (Dsp-8-u16))
4381 (syntax "${Dsp-8-u16}")
4382 (base-ifield f-2-2)
4383 (encoding (+ (f-2-2 1) Dsp-8-u16))
4384 (ifield-assertion (eq f-2-2 1))
4385 (getter (c-call xmode (.str "operand_getter_" xmode) (const 0) Dsp-8-u16))
4386 (setter (c-call DFLT (.str "operand_setter_" xmode) newval (const 0) Dsp-8-u16))
4387; (getter (mem32 xmode Dsp-8-u16))
4388; (setter (set (mem32 xmode Dsp-8-u16) newval))
4389 )
4390; (define-derived-operand
4391; (name (.sym dst32-2-S-8-SB-relative-indirect- xmode))
4392; (comment "m32c SB relative for short binary insns")
4393; (attrs (machine 32))
4394; (mode xmode)
4395; (args (Dsp-16-u8))
4396; (syntax "[${Dsp-16-u8}[sb]]")
4397; (base-ifield f-10-2)
4398; (encoding (+ (f-10-2 2) Dsp-16-u8))
4399; (ifield-assertion (eq f-10-2 2))
4400; (getter (mem32 xmode (indirect-addr (add Dsp-16-u8 (reg h-sb)))))
4401; (setter (set (mem32 xmode (indirect-addr (add Dsp-16-u8 (reg h-sb)))) newval))
4402; )
4403; (define-derived-operand
4404; (name (.sym dst32-2-S-8-FB-relative-indirect- xmode))
4405; (comment "m32c FB relative for short binary insns")
4406; (attrs (machine 32))
4407; (mode xmode)
4408; (args (Dsp-16-s8))
4409; (syntax "[${Dsp-16-s8}[fb]]")
4410; (base-ifield f-10-2)
4411; (encoding (+ (f-10-2 3) Dsp-16-s8))
4412; (ifield-assertion (eq f-10-2 3))
4413; (getter (mem32 xmode (indirect-addr (add Dsp-16-s8 (reg h-fb)))))
4414; (setter (set (mem32 xmode (indirect-addr (add Dsp-16-s8 (reg h-fb)))) newval))
4415; )
4416; (define-derived-operand
4417; (name (.sym dst32-2-S-16-absolute-indirect- xmode))
4418; (comment "m32c absolute address for short binary insns")
4419; (attrs (machine 32))
4420; (mode xmode)
4421; (args (Dsp-16-u16))
4422; (syntax "[${Dsp-16-u16}]")
4423; (base-ifield f-10-2)
4424; (encoding (+ (f-10-2 1) Dsp-16-u16))
4425; (ifield-assertion (eq f-10-2 1))
4426; (getter (mem32 xmode (indirect-addr Dsp-16-u16)))
4427; (setter (set (mem32 xmode (indirect-addr Dsp-16-u16)) newval))
4428; )
4429 )
4430)
4431
4432(dst32-2-S-operands QI)
4433(dst32-2-S-operands HI)
4434(dst32-2-S-operands SI)
4435
4436;=============================================================
4437; Anyof operands
4438;-------------------------------------------------------------
4439; Source operands with no additional fields
4440;-------------------------------------------------------------
4441
4442(define-pmacro (src16-basic-operand xmode)
4443 (begin
4444 (define-anyof-operand
4445 (name (.sym src16-basic- xmode))
4446 (comment (.str "m16c source operand of size " xmode " with no additional fields"))
4447 (attrs (machine 16))
4448 (mode xmode)
4449 (choices
4450 (.sym src16-Rn-direct- xmode)
4451 (.sym src16-An-direct- xmode)
4452 (.sym src16-An-indirect- xmode)
4453 )
4454 )
4455 )
4456)
4457(src16-basic-operand QI)
4458(src16-basic-operand HI)
4459
4460(define-pmacro (src32-basic-operand xmode)
4461 (begin
4462 (define-anyof-operand
4463 (name (.sym src32-basic-Unprefixed- xmode))
4464 (comment (.str "m32c destination operand of size " xmode " with no additional fields"))
4465 (attrs (machine 32))
4466 (mode xmode)
4467 (choices
4468 (.sym src32-Rn-direct-Unprefixed- xmode)
4469 (.sym src32-An-direct-Unprefixed- xmode)
4470 (.sym src32-An-indirect-Unprefixed- xmode)
4471 )
4472 )
4473 (define-anyof-operand
4474 (name (.sym src32-basic-Prefixed- xmode))
4475 (comment (.str "m32c destination operand of size " xmode " with no additional fields"))
4476 (attrs (machine 32))
4477 (mode xmode)
4478 (choices
4479 (.sym src32-Rn-direct-Prefixed- xmode)
4480 (.sym src32-An-direct-Prefixed- xmode)
4481 (.sym src32-An-indirect-Prefixed- xmode)
4482 )
4483 )
4484; (define-anyof-operand
4485; (name (.sym src32-basic-indirect- xmode))
4486; (comment (.str "m32c destination operand of size " xmode " indirect with no additional fields"))
4487; (attrs (machine 32))
4488; (mode xmode)
4489; (choices
4490; (.sym src32-An-indirect-indirect- xmode)
4491; )
4492; )
4493 )
4494)
4495
4496(src32-basic-operand QI)
4497(src32-basic-operand HI)
4498(src32-basic-operand SI)
4499
4500(define-anyof-operand
4501 (name src32-basic-ExtPrefixed-QI)
4502 (comment "m32c source operand of size QI with no additional fields")
4503 (attrs (machine 32))
4504 (mode QI)
4505 (choices
4506 src32-Rn-direct-Prefixed-QI
4507 src32-An-indirect-Prefixed-QI
4508 )
4509)
4510
4511;-------------------------------------------------------------
4512; Source operands with additional fields at offset 16 bits
4513;-------------------------------------------------------------
4514
4515(define-pmacro (src16-16-operand xmode)
4516 (begin
4517 (define-anyof-operand
4518 (name (.sym src16-16-8- xmode))
4519 (comment (.str "m16c source operand of size " xmode " with additional 8 bit fields at offset 16"))
4520 (attrs (machine 16))
4521 (mode xmode)
4522 (choices
4523 (.sym src16-16-8-An-relative- xmode)
4524 (.sym src16-16-8-SB-relative- xmode)
4525 (.sym src16-16-8-FB-relative- xmode)
4526 )
4527 )
4528 (define-anyof-operand
4529 (name (.sym src16-16-16- xmode))
4530 (comment (.str "m16c source operand of size " xmode " with additional 16 bit fields at offset 16"))
4531 (attrs (machine 16))
4532 (mode xmode)
4533 (choices
4534 (.sym src16-16-16-An-relative- xmode)
4535 (.sym src16-16-16-SB-relative- xmode)
4536 (.sym src16-16-16-absolute- xmode)
4537 )
4538 )
4539 )
4540)
4541(src16-16-operand QI)
4542(src16-16-operand HI)
4543
4544(define-pmacro (src32-16-operand xmode)
4545 (begin
4546 (define-anyof-operand
4547 (name (.sym src32-16-8-Unprefixed- xmode))
4548 (comment (.str "m32c source operand of size " xmode " with additional 8 bit fields at offset 16"))
4549 (attrs (machine 32))
4550 (mode xmode)
4551 (choices
4552 (.sym src32-16-8-An-relative-Unprefixed- xmode)
4553 (.sym src32-16-8-SB-relative-Unprefixed- xmode)
4554 (.sym src32-16-8-FB-relative-Unprefixed- xmode)
4555 )
4556 )
4557 (define-anyof-operand
4558 (name (.sym src32-16-16-Unprefixed- xmode))
4559 (comment (.str "m32c source operand of size " xmode " with additional 16 bit fields at offset 16"))
4560 (attrs (machine 32))
4561 (mode xmode)
4562 (choices
4563 (.sym src32-16-16-An-relative-Unprefixed- xmode)
4564 (.sym src32-16-16-SB-relative-Unprefixed- xmode)
4565 (.sym src32-16-16-FB-relative-Unprefixed- xmode)
4566 (.sym src32-16-16-absolute-Unprefixed- xmode)
4567 )
4568 )
4569 (define-anyof-operand
4570 (name (.sym src32-16-24-Unprefixed- xmode))
4571 (comment (.str "m32c source operand of size " xmode " with additional 24 bit fields at offset 16"))
4572 (attrs (machine 32))
4573 (mode xmode)
4574 (choices
4575 (.sym src32-16-24-An-relative-Unprefixed- xmode)
4576 (.sym src32-16-24-absolute-Unprefixed- xmode)
4577 )
4578 )
4579 )
4580)
4581
4582(src32-16-operand QI)
4583(src32-16-operand HI)
4584(src32-16-operand SI)
4585
4586;-------------------------------------------------------------
4587; Source operands with additional fields at offset 24 bits
4588;-------------------------------------------------------------
4589
4590(define-pmacro (src-24-operand group xmode)
4591 (begin
4592 (define-anyof-operand
4593 (name (.sym src32-24-8- group - xmode))
4594 (comment (.str "m32c source operand of size " xmode " with additional 8 bit fields at offset 24"))
4595 (attrs (machine 32))
4596 (mode xmode)
4597 (choices
4598 (.sym src32-24-8-An-relative- group - xmode)
4599 (.sym src32-24-8-SB-relative- group - xmode)
4600 (.sym src32-24-8-FB-relative- group - xmode)
4601 )
4602 )
4603 (define-anyof-operand
4604 (name (.sym src32-24-16- group - xmode))
4605 (comment (.str "m32c source operand of size " xmode " with additional 16 bit fields at offset 16"))
4606 (attrs (machine 32))
4607 (mode xmode)
4608 (choices
4609 (.sym src32-24-16-An-relative- group - xmode)
4610 (.sym src32-24-16-SB-relative- group - xmode)
4611 (.sym src32-24-16-FB-relative- group - xmode)
4612 (.sym src32-24-16-absolute- group - xmode)
4613 )
4614 )
4615 (define-anyof-operand
4616 (name (.sym src32-24-24- group - xmode))
4617 (comment (.str "m32c source operand of size " xmode " with additional 24 bit fields at offset 16"))
4618 (attrs (machine 32))
4619 (mode xmode)
4620 (choices
4621 (.sym src32-24-24-An-relative- group - xmode)
4622 (.sym src32-24-24-absolute- group - xmode)
4623 )
4624 )
4625 )
4626)
4627
4628(src-24-operand Prefixed QI)
4629(src-24-operand Prefixed HI)
4630(src-24-operand Prefixed SI)
4631
4632(define-pmacro (src-24-indirect-operand xmode)
4633 (begin
4634; (define-anyof-operand
4635; (name (.sym src32-24-8-indirect- xmode))
4636; (comment (.str "m32c destination operand of size " xmode " with additional fields at offset 24"))
4637; (attrs (machine 32))
4638; (mode xmode)
4639; (choices
4640; (.sym src32-24-8-An-relative-indirect- xmode)
4641; (.sym src32-24-8-SB-relative-indirect- xmode)
4642; (.sym src32-24-8-FB-relative-indirect- xmode)
4643; )
4644; )
4645; (define-anyof-operand
4646; (name (.sym src32-24-16-indirect- xmode))
4647; (comment (.str "m32c destination operand of size " xmode " with additional fields at offset 24"))
4648; (attrs (machine 32))
4649; (mode xmode)
4650; (choices
4651; (.sym src32-24-16-An-relative-indirect- xmode)
4652; (.sym src32-24-16-SB-relative-indirect- xmode)
4653; (.sym src32-24-16-FB-relative-indirect- xmode)
4654; )
4655; )
4656; (define-anyof-operand
4657; (name (.sym src32-24-24-indirect- xmode))
4658; (comment (.str "m32c destination operand of size " xmode " with additional fields at offset 24"))
4659; (attrs (machine 32))
4660; (mode xmode)
4661; (choices
4662; (.sym src32-24-24-An-relative-indirect- xmode)
4663; )
4664; )
4665; (define-anyof-operand
4666; (name (.sym src32-24-16-absolute-indirect- xmode))
4667; (comment (.str "m32c source operand of size " xmode " 16 bit absolute indirect"))
4668; (attrs (machine 32))
4669; (mode xmode)
4670; (choices
4671; (.sym src32-24-16-absolute-indirect-derived- xmode)
4672; )
4673; )
4674; (define-anyof-operand
4675; (name (.sym src32-24-24-absolute-indirect- xmode))
4676; (comment (.str "m32c source operand of size " xmode " 24 bit absolute indirect"))
4677; (attrs (machine 32))
4678; (mode xmode)
4679; (choices
4680; (.sym src32-24-24-absolute-indirect-derived- xmode)
4681; )
4682; )
4683 )
4684)
4685
4686; (src-24-indirect-operand QI)
4687; (src-24-indirect-operand HI)
4688; (src-24-indirect-operand SI)
4689
4690;-------------------------------------------------------------
4691; Destination operands with no additional fields
4692;-------------------------------------------------------------
4693
4694(define-pmacro (dst16-basic-operand xmode)
4695 (begin
4696 (define-anyof-operand
4697 (name (.sym dst16-basic- xmode))
4698 (comment (.str "m16c destination operand of size " xmode " with no additional fields"))
4699 (attrs (machine 16))
4700 (mode xmode)
4701 (choices
4702 (.sym dst16-Rn-direct- xmode)
4703 (.sym dst16-An-direct- xmode)
4704 (.sym dst16-An-indirect- xmode)
4705 )
4706 )
4707 )
4708)
4709
4710(dst16-basic-operand QI)
4711(dst16-basic-operand HI)
4712(dst16-basic-operand SI)
4713
4714(define-pmacro (dst32-basic-operand xmode)
4715 (begin
4716 (define-anyof-operand
4717 (name (.sym dst32-basic-Unprefixed- xmode))
4718 (comment (.str "m32c destination operand of size " xmode " with no additional fields"))
4719 (attrs (machine 32))
4720 (mode xmode)
4721 (choices
4722 (.sym dst32-Rn-direct-Unprefixed- xmode)
4723 (.sym dst32-An-direct-Unprefixed- xmode)
4724 (.sym dst32-An-indirect-Unprefixed- xmode)
4725 )
4726 )
4727 (define-anyof-operand
4728 (name (.sym dst32-basic-Prefixed- xmode))
4729 (comment (.str "m32c destination operand of size " xmode " with no additional fields"))
4730 (attrs (machine 32))
4731 (mode xmode)
4732 (choices
4733 (.sym dst32-Rn-direct-Prefixed- xmode)
4734 (.sym dst32-An-direct-Prefixed- xmode)
4735 (.sym dst32-An-indirect-Prefixed- xmode)
4736 )
4737 )
4738 )
4739)
4740
4741(dst32-basic-operand QI)
4742(dst32-basic-operand HI)
4743(dst32-basic-operand SI)
4744
4745;-------------------------------------------------------------
4746; Destination operands with possible additional fields at offset 16 bits
4747;-------------------------------------------------------------
4748
4749(define-pmacro (dst16-16-operand xmode)
4750 (begin
4751 (define-anyof-operand
4752 (name (.sym dst16-16- xmode))
4753 (comment (.str "m16c destination operand of size " xmode " with additional fields at offset 16"))
4754 (attrs (machine 16))
4755 (mode xmode)
4756 (choices
4757 (.sym dst16-Rn-direct- xmode)
4758 (.sym dst16-An-direct- xmode)
4759 (.sym dst16-An-indirect- xmode)
4760 (.sym dst16-16-8-An-relative- xmode)
4761 (.sym dst16-16-16-An-relative- xmode)
4762 (.sym dst16-16-8-SB-relative- xmode)
4763 (.sym dst16-16-16-SB-relative- xmode)
4764 (.sym dst16-16-8-FB-relative- xmode)
4765 (.sym dst16-16-16-absolute- xmode)
4766 )
4767 )
4768 (define-anyof-operand
4769 (name (.sym dst16-16-8- xmode))
4770 (comment (.str "m16c destination operand of size " xmode " with additional fields at offset 16"))
4771 (attrs (machine 16))
4772 (mode xmode)
4773 (choices
4774 (.sym dst16-16-8-An-relative- xmode)
4775 (.sym dst16-16-8-SB-relative- xmode)
4776 (.sym dst16-16-8-FB-relative- xmode)
4777 )
4778 )
4779 (define-anyof-operand
4780 (name (.sym dst16-16-16- xmode))
4781 (comment (.str "m16c destination operand of size " xmode " with additional fields at offset 16"))
4782 (attrs (machine 16))
4783 (mode xmode)
4784 (choices
4785 (.sym dst16-16-16-An-relative- xmode)
4786 (.sym dst16-16-16-SB-relative- xmode)
4787 (.sym dst16-16-16-absolute- xmode)
4788 )
4789 )
75b06e7b
DD		 4790 (define-anyof-operand
4791 (name (.sym dst16-16-16sa- xmode))
4792 (comment (.str "m16c destination operand of size " xmode " with additional fields at offset 16"))
4793 (attrs (machine 16))
4794 (mode xmode)
4795 (choices
4796 (.sym dst16-16-16-SB-relative- xmode)
4797 (.sym dst16-16-16-absolute- xmode)
4798 )
4799 )
4800 (define-anyof-operand
4801 (name (.sym dst16-16-20ar- xmode))
4802 (comment (.str "m16c destination operand of size " xmode " with additional fields at offset 16"))
4803 (attrs (machine 16))
4804 (mode xmode)
4805 (choices
4806 (.sym dst16-16-20-An-relative- xmode)
4807 )
4808 )
49f58d10
JB		 4809 )
4810)
4811
4812(dst16-16-operand QI)
4813(dst16-16-operand HI)
4814(dst16-16-operand SI)
4815
4816(define-anyof-operand
4817 (name dst16-16-Ext-QI)
4818 (comment "m16c destination operand of size QI for 'ext' insns with additional fields at offset 16")
4819 (attrs (machine 16))
4820 (mode QI)
4821 (choices
4822 dst16-Rn-direct-Ext-QI
4823 dst16-An-indirect-Ext-QI
4824 dst16-16-8-An-relative-Ext-QI
4825 dst16-16-16-An-relative-Ext-QI
4826 dst16-16-8-SB-relative-Ext-QI
4827 dst16-16-16-SB-relative-Ext-QI
4828 dst16-16-8-FB-relative-Ext-QI
4829 dst16-16-16-absolute-Ext-QI
4830 )
4831)
4832
4833(define-derived-operand
4834 (name dst16-An-indirect-Mova-HI)
4835 (comment "m16c addressof An indirect destination HI")
4836 (attrs (ISA m16c))
4837 (mode HI)
4838 (args (Dst16An))
4839 (syntax "[$Dst16An]")
4840 (base-ifield f-12-4)
4841 (encoding (+ (f-12-2 1) (f-14-1 1) Dst16An))
4842 (ifield-assertion
4843 (andif (eq f-12-2 1) (eq f-14-1 1)))
4844 (getter Dst16An)
4845 (setter (nop))
4846 )
4847
4848(define-derived-operand
4849 (name dst16-16-8-An-relative-Mova-HI)
4850 (comment
4851 "m16c addressof dsp:8[An] relative destination HI")
4852 (attrs (ISA m16c))
4853 (mode HI)
4854 (args (Dst16An Dsp-16-u8))
4855 (syntax "${Dsp-16-u8}[$Dst16An]")
4856 (base-ifield f-12-4)
4857 (encoding
4858 (+ (f-12-2 2) (f-14-1 0) Dsp-16-u8 Dst16An))
4859 (ifield-assertion
4860 (andif (eq f-12-2 2) (eq f-14-1 0)))
4861 (getter (add Dsp-16-u8 Dst16An))
4862 (setter (nop))
4863)
4864(define-derived-operand
4865 (name dst16-16-16-An-relative-Mova-HI)
4866 (comment
4867 "m16c addressof dsp:16[An] relative destination HI")
4868 (attrs (ISA m16c))
4869 (mode HI)
4870 (args (Dst16An Dsp-16-u16))
4871 (syntax "${Dsp-16-u16}[$Dst16An]")
4872 (base-ifield f-12-4)
4873 (encoding
4874 (+ (f-12-2 3) (f-14-1 0) Dsp-16-u16 Dst16An))
4875 (ifield-assertion
4876 (andif (eq f-12-2 3) (eq f-14-1 0)))
4877 (getter (add Dsp-16-u16 Dst16An))
4878 (setter (nop))
4879 )
4880(define-derived-operand
4881 (name dst16-16-8-SB-relative-Mova-HI)
4882 (comment
4883 "m16c addressof dsp:8[sb] relative destination HI")
4884 (attrs (ISA m16c))
4885 (mode HI)
4886 (args (Dsp-16-u8))
4887 (syntax "${Dsp-16-u8}[sb]")
4888 (base-ifield f-12-4)
4889 (encoding (+ (f-12-4 10) Dsp-16-u8))
4890 (ifield-assertion (eq f-12-4 10))
4891 (getter (add Dsp-16-u8 (reg h-sb)))
4892 (setter (nop))
4893)
4894(define-derived-operand
4895 (name dst16-16-16-SB-relative-Mova-HI)
4896 (comment
4897 "m16c addressof dsp:16[sb] relative destination HI")
4898 (attrs (ISA m16c))
4899 (mode HI)
4900 (args (Dsp-16-u16))
4901 (syntax "${Dsp-16-u16}[sb]")
4902 (base-ifield f-12-4)
4903 (encoding (+ (f-12-4 14) Dsp-16-u16))
4904 (ifield-assertion (eq f-12-4 14))
4905 (getter (add Dsp-16-u16 (reg h-sb)))
4906 (setter (nop))
4907 )
4908(define-derived-operand
4909 (name dst16-16-8-FB-relative-Mova-HI)
4910 (comment
4911 "m16c addressof dsp:8[fb] relative destination HI")
4912 (attrs (ISA m16c))
4913 (mode HI)
4914 (args (Dsp-16-s8))
4915 (syntax "${Dsp-16-s8}[fb]")
4916 (base-ifield f-12-4)
4917 (encoding (+ (f-12-4 11) Dsp-16-s8))
4918 (ifield-assertion (eq f-12-4 11))
4919 (getter (add Dsp-16-s8 (reg h-fb)))
4920 (setter (nop))
4921 )
4922(define-derived-operand
4923 (name dst16-16-16-absolute-Mova-HI)
4924 (comment "m16c addressof absolute address HI")
4925 (attrs (ISA m16c))
4926 (mode HI)
4927 (args (Dsp-16-u16))
4928 (syntax "${Dsp-16-u16}")
4929 (base-ifield f-12-4)
4930 (encoding (+ (f-12-4 15) Dsp-16-u16))
4931 (ifield-assertion (eq f-12-4 15))
4932 (getter Dsp-16-u16)
4933 (setter (nop))
4934 )
4935
4936(define-anyof-operand
4937 (name dst16-16-Mova-HI)
4938 (comment "m16c addressof destination operand of size HI with additional fields at offset 16")
4939 (attrs (machine 16))
4940 (mode HI)
4941 (choices
4942 dst16-An-indirect-Mova-HI
4943 dst16-16-8-An-relative-Mova-HI
4944 dst16-16-16-An-relative-Mova-HI
4945 dst16-16-8-SB-relative-Mova-HI
4946 dst16-16-16-SB-relative-Mova-HI
4947 dst16-16-8-FB-relative-Mova-HI
4948 dst16-16-16-absolute-Mova-HI
4949 )
4950)
4951
4952(define-derived-operand
4953 (name dst32-An-indirect-Unprefixed-Mova-SI)
4954 (comment "m32c addressof An indirect destination SI")
4955 (attrs (ISA m32c))
4956 (mode SI)
4957 (args (Dst32AnUnprefixed))
4958 (syntax "[$Dst32AnUnprefixed]")
4959 (base-ifield f-4-6)
4960 (encoding
4961 (+ (f-4-3 0) (f-8-1 0) Dst32AnUnprefixed))
4962 (ifield-assertion
4963 (andif (eq f-4-3 0) (eq f-8-1 0)))
4964 (getter Dst32AnUnprefixed)
4965 (setter (nop))
4966 )
4967
4968(define-derived-operand
4969 (name dst32-16-8-An-relative-Unprefixed-Mova-SI)
4970 (comment "m32c addressof dsp:8[An] relative destination SI")
4971 (attrs (ISA m32c))
4972 (mode SI)
4973 (args (Dst32AnUnprefixed Dsp-16-u8))
4974 (syntax "${Dsp-16-u8}[$Dst32AnUnprefixed]")
4975 (base-ifield f-4-6)
4976 (encoding
4977 (+ (f-4-3 1)
4978 (f-8-1 0)
4979 Dsp-16-u8
4980 Dst32AnUnprefixed))
4981 (ifield-assertion
4982 (andif (eq f-4-3 1) (eq f-8-1 0)))
4983 (getter (add Dsp-16-u8 Dst32AnUnprefixed))
4984 (setter (nop))
4985)
4986
4987(define-derived-operand
4988 (name dst32-16-16-An-relative-Unprefixed-Mova-SI)
4989 (comment
4990 "m32c addressof dsp:16[An] relative destination SI")
4991 (attrs (ISA m32c))
4992 (mode SI)
4993 (args (Dst32AnUnprefixed Dsp-16-u16))
4994 (syntax "${Dsp-16-u16}[$Dst32AnUnprefixed]")
4995 (base-ifield f-4-6)
4996 (encoding
4997 (+ (f-4-3 2)
4998 (f-8-1 0)
4999 Dsp-16-u16
5000 Dst32AnUnprefixed))
5001 (ifield-assertion
5002 (andif (eq f-4-3 2) (eq f-8-1 0)))
5003 (getter (add Dsp-16-u16 Dst32AnUnprefixed))
5004 (setter (nop))
5005 )
5006
5007(define-derived-operand
5008 (name dst32-16-24-An-relative-Unprefixed-Mova-SI)
5009 (comment "addressof m32c dsp:16[An] relative destination SI")
5010 (attrs (ISA m32c))
5011 (mode SI)
5012 (args (Dst32AnUnprefixed Dsp-16-u24))
5013 (syntax "${Dsp-16-u24}[$Dst32AnUnprefixed]")
5014 (base-ifield f-4-6)
5015 (encoding
5016 (+ (f-4-3 3)
5017 (f-8-1 0)
5018 Dsp-16-u24
5019 Dst32AnUnprefixed))
5020 (ifield-assertion
5021 (andif (eq f-4-3 3) (eq f-8-1 0)))
5022 (getter (add Dsp-16-u24 Dst32AnUnprefixed))
5023 (setter (nop))
5024 )
5025
5026(define-derived-operand
5027 (name dst32-16-8-SB-relative-Unprefixed-Mova-SI)
5028 (comment "m32c addressof dsp:8[sb] relative destination SI")
5029 (attrs (ISA m32c))
5030 (mode SI)
5031 (args (Dsp-16-u8))
5032 (syntax "${Dsp-16-u8}[sb]")
5033 (base-ifield f-4-6)
5034 (encoding (+ (f-4-3 1) (f-8-2 2) Dsp-16-u8))
5035 (ifield-assertion
5036 (andif (eq f-4-3 1) (eq f-8-2 2)))
5037 (getter (add Dsp-16-u8 (reg h-sb)))
5038 (setter (nop))
5039 )
5040
5041(define-derived-operand
5042 (name dst32-16-16-SB-relative-Unprefixed-Mova-SI)
5043 (comment "m32c addressof dsp:16[sb] relative destination SI")
5044 (attrs (ISA m32c))
5045 (mode SI)
5046 (args (Dsp-16-u16))
5047 (syntax "${Dsp-16-u16}[sb]")
5048 (base-ifield f-4-6)
5049 (encoding (+ (f-4-3 2) (f-8-2 2) Dsp-16-u16))
5050 (ifield-assertion
5051 (andif (eq f-4-3 2) (eq f-8-2 2)))
5052 (getter (add Dsp-16-u16 (reg h-sb)))
5053 (setter (nop))
5054 )
5055
5056(define-derived-operand
5057 (name dst32-16-8-FB-relative-Unprefixed-Mova-SI)
5058 (comment "m32c addressof dsp:8[fb] relative destination SI")
5059 (attrs (ISA m32c))
5060 (mode SI)
5061 (args (Dsp-16-s8))
5062 (syntax "${Dsp-16-s8}[fb]")
5063 (base-ifield f-4-6)
5064 (encoding (+ (f-4-3 1) (f-8-2 3) Dsp-16-s8))
5065 (ifield-assertion
5066 (andif (eq f-4-3 1) (eq f-8-2 3)))
5067 (getter (add Dsp-16-s8 (reg h-fb)))
5068 (setter (nop))
5069 )
5070
5071(define-derived-operand
5072 (name dst32-16-16-FB-relative-Unprefixed-Mova-SI)
5073 (comment "m32c addressof dsp:16[fb] relative destination SI")
5074 (attrs (ISA m32c))
5075 (mode SI)
5076 (args (Dsp-16-s16))
5077 (syntax "${Dsp-16-s16}[fb]")
5078 (base-ifield f-4-6)
5079 (encoding (+ (f-4-3 2) (f-8-2 3) Dsp-16-s16))
5080 (ifield-assertion
5081 (andif (eq f-4-3 2) (eq f-8-2 3)))
5082 (getter (add Dsp-16-s16 (reg h-fb)))
5083 (setter (nop))
5084 )
5085
5086(define-derived-operand
5087 (name dst32-16-16-absolute-Unprefixed-Mova-SI)
5088 (comment "m32c addressof absolute address SI") (attrs (ISA m32c))
5089 (mode SI)
5090 (args (Dsp-16-u16))
5091 (syntax "${Dsp-16-u16}")
5092 (base-ifield f-4-6)
5093 (encoding (+ (f-4-3 3) (f-8-2 3) Dsp-16-u16))
5094 (ifield-assertion
5095 (andif (eq f-4-3 3) (eq f-8-2 3)))
5096 (getter Dsp-16-u16)
5097 (setter (nop))
5098 )
5099
5100(define-derived-operand
5101 (name dst32-16-24-absolute-Unprefixed-Mova-SI)
5102 (comment "m32c addressof absolute address SI") (attrs (ISA m32c))
5103 (mode SI)
5104 (args (Dsp-16-u24))
5105 (syntax "${Dsp-16-u24}")
5106 (base-ifield f-4-6)
5107 (encoding (+ (f-4-3 3) (f-8-2 2) Dsp-16-u24))
5108 (ifield-assertion
5109 (andif (eq f-4-3 3) (eq f-8-2 2)))
5110 (getter Dsp-16-u24)
5111 (setter (nop))
5112 )
5113
5114(define-anyof-operand
5115 (name dst32-16-Unprefixed-Mova-SI)
5116 (comment
5117 "m32c addressof destination operand of size SI with additional fields at offset 16")
5118 (attrs (ISA m32c))
5119 (mode SI)
5120 (choices
5121 dst32-An-indirect-Unprefixed-Mova-SI
5122 dst32-16-8-An-relative-Unprefixed-Mova-SI
5123 dst32-16-16-An-relative-Unprefixed-Mova-SI
5124 dst32-16-24-An-relative-Unprefixed-Mova-SI
5125 dst32-16-8-SB-relative-Unprefixed-Mova-SI
5126 dst32-16-16-SB-relative-Unprefixed-Mova-SI
5127 dst32-16-8-FB-relative-Unprefixed-Mova-SI
5128 dst32-16-16-FB-relative-Unprefixed-Mova-SI
5129 dst32-16-16-absolute-Unprefixed-Mova-SI
5130 dst32-16-24-absolute-Unprefixed-Mova-SI))
5131
5132(define-pmacro (dst32-16-operand xmode)
5133 (begin
5134 (define-anyof-operand
5135 (name (.sym dst32-16-Unprefixed- xmode))
5136 (comment (.str "m32c destination operand of size " xmode " with additional fields at offset 16"))
5137 (attrs (machine 32))
5138 (mode xmode)
5139 (choices
5140 (.sym dst32-Rn-direct-Unprefixed- xmode)
5141 (.sym dst32-An-direct-Unprefixed- xmode)
5142 (.sym dst32-An-indirect-Unprefixed- xmode)
5143 (.sym dst32-16-8-An-relative-Unprefixed- xmode)
5144 (.sym dst32-16-16-An-relative-Unprefixed- xmode)
5145 (.sym dst32-16-24-An-relative-Unprefixed- xmode)
5146 (.sym dst32-16-8-SB-relative-Unprefixed- xmode)
5147 (.sym dst32-16-16-SB-relative-Unprefixed- xmode)
5148 (.sym dst32-16-8-FB-relative-Unprefixed- xmode)
5149 (.sym dst32-16-16-FB-relative-Unprefixed- xmode)
5150 (.sym dst32-16-16-absolute-Unprefixed- xmode)
5151 (.sym dst32-16-24-absolute-Unprefixed- xmode)
5152 )
5153 )
5154 (define-anyof-operand
5155 (name (.sym dst32-16-8-Unprefixed- xmode))
5156 (comment (.str "m32c destination operand of size " xmode " with additional fields at offset 16"))
5157 (attrs (machine 32))
5158 (mode xmode)
5159 (choices
5160 (.sym dst32-16-8-An-relative-Unprefixed- xmode)
5161 (.sym dst32-16-8-SB-relative-Unprefixed- xmode)
5162 (.sym dst32-16-8-FB-relative-Unprefixed- xmode)
5163 )
5164 )
5165 (define-anyof-operand
5166 (name (.sym dst32-16-16-Unprefixed- xmode))
5167 (comment (.str "m32c destination operand of size " xmode " with additional fields at offset 16"))
5168 (attrs (machine 32))
5169 (mode xmode)
5170 (choices
5171 (.sym dst32-16-16-An-relative-Unprefixed- xmode)
5172 (.sym dst32-16-16-SB-relative-Unprefixed- xmode)
5173 (.sym dst32-16-16-FB-relative-Unprefixed- xmode)
5174 (.sym dst32-16-16-absolute-Unprefixed- xmode)
5175 )
5176 )
75b06e7b
DD		 5177 (define-anyof-operand
5178 (name (.sym dst32-16-16sa-Unprefixed- xmode))
5179 (comment (.str "m32c destination operand of size " xmode " with additional fields at offset 16"))
5180 (attrs (machine 32))
5181 (mode xmode)
5182 (choices
5183 (.sym dst32-16-16-SB-relative-Unprefixed- xmode)
5184 (.sym dst32-16-16-FB-relative-Unprefixed- xmode)
5185 (.sym dst32-16-16-absolute-Unprefixed- xmode)
5186 )
5187 )
49f58d10
JB		 5188 (define-anyof-operand
5189 (name (.sym dst32-16-24-Unprefixed- xmode))
5190 (comment (.str "m32c destination operand of size " xmode " with additional fields at offset 16"))
5191 (attrs (machine 32))
5192 (mode xmode)
5193 (choices
5194 (.sym dst32-16-24-An-relative-Unprefixed- xmode)
5195 (.sym dst32-16-24-absolute-Unprefixed- xmode)
5196 )
5197 )
5198 )
5199)
5200
5201(dst32-16-operand QI)
5202(dst32-16-operand HI)
5203(dst32-16-operand SI)
5204
5205(define-pmacro (dst32-16-Ext-operand smode dmode)
5206 (begin
5207 (define-anyof-operand
5208 (name (.sym dst32-16-ExtUnprefixed- smode))
5209 (comment (.str "m32c destination operand of size " smode " with additional fields at offset 16"))
5210 (attrs (machine 32))
5211 (mode dmode)
5212 (choices
5213 (.sym dst32-Rn-direct-ExtUnprefixed- smode)
5214 (.sym dst32-An-direct-Unprefixed- dmode) ; ExtUnprefixed mode not required for this operand -- use the normal dmode version
5215 (.sym dst32-An-indirect-ExtUnprefixed- smode)
5216 (.sym dst32-16-8-An-relative-ExtUnprefixed- smode)
5217 (.sym dst32-16-16-An-relative-ExtUnprefixed- smode)
5218 (.sym dst32-16-24-An-relative-ExtUnprefixed- smode)
5219 (.sym dst32-16-8-SB-relative-ExtUnprefixed- smode)
5220 (.sym dst32-16-16-SB-relative-ExtUnprefixed- smode)
5221 (.sym dst32-16-8-FB-relative-ExtUnprefixed- smode)
5222 (.sym dst32-16-16-FB-relative-ExtUnprefixed- smode)
5223 (.sym dst32-16-16-absolute-ExtUnprefixed- smode)
5224 (.sym dst32-16-24-absolute-ExtUnprefixed- smode)
5225 )
5226 )
5227 )
5228)
5229
5230(dst32-16-Ext-operand QI HI)
5231(dst32-16-Ext-operand HI SI)
5232
5233(define-anyof-operand
5234 (name dst32-16-Unprefixed-Mulex-HI)
5235 (comment "m32c destination operand of size HI with additional fields at offset 16")
5236 (attrs (machine 32))
5237 (mode HI)
5238 (choices
5239 dst32-R3-direct-Unprefixed-HI
5240 dst32-An-direct-Unprefixed-HI
5241 dst32-An-indirect-Unprefixed-HI
5242 dst32-16-8-An-relative-Unprefixed-HI
5243 dst32-16-16-An-relative-Unprefixed-HI
5244 dst32-16-24-An-relative-Unprefixed-HI
5245 dst32-16-8-SB-relative-Unprefixed-HI
5246 dst32-16-16-SB-relative-Unprefixed-HI
5247 dst32-16-8-FB-relative-Unprefixed-HI
5248 dst32-16-16-FB-relative-Unprefixed-HI
5249 dst32-16-16-absolute-Unprefixed-HI
5250 dst32-16-24-absolute-Unprefixed-HI
5251 )
5252)
5253;-------------------------------------------------------------
5254; Destination operands with possible additional fields at offset 24 bits
5255;-------------------------------------------------------------
5256
5257(define-pmacro (dst16-24-operand xmode)
5258 (begin
5259 (define-anyof-operand
5260 (name (.sym dst16-24- xmode))
5261 (comment (.str "m16c destination operand of size " xmode " with additional fields at offset 24"))
5262 (attrs (machine 16))
5263 (mode xmode)
5264 (choices
5265 (.sym dst16-Rn-direct- xmode)
5266 (.sym dst16-An-direct- xmode)
5267 (.sym dst16-An-indirect- xmode)
5268 (.sym dst16-24-8-An-relative- xmode)
5269 (.sym dst16-24-16-An-relative- xmode)
5270 (.sym dst16-24-8-SB-relative- xmode)
5271 (.sym dst16-24-16-SB-relative- xmode)
5272 (.sym dst16-24-8-FB-relative- xmode)
5273 (.sym dst16-24-16-absolute- xmode)
5274 )
5275 )
5276 )
5277)
5278
5279(dst16-24-operand QI)
5280(dst16-24-operand HI)
5281
5282(define-pmacro (dst32-24-operand xmode)
5283 (begin
5284 (define-anyof-operand
5285 (name (.sym dst32-24-Unprefixed- xmode))
5286 (comment (.str "m32c destination operand of size " xmode " with additional fields at offset 24"))
5287 (attrs (machine 32))
5288 (mode xmode)
5289 (choices
5290 (.sym dst32-Rn-direct-Unprefixed- xmode)
5291 (.sym dst32-An-direct-Unprefixed- xmode)
5292 (.sym dst32-An-indirect-Unprefixed- xmode)
5293 (.sym dst32-24-8-An-relative-Unprefixed- xmode)
5294 (.sym dst32-24-16-An-relative-Unprefixed- xmode)
5295 (.sym dst32-24-24-An-relative-Unprefixed- xmode)
5296 (.sym dst32-24-8-SB-relative-Unprefixed- xmode)
5297 (.sym dst32-24-16-SB-relative-Unprefixed- xmode)
5298 (.sym dst32-24-8-FB-relative-Unprefixed- xmode)
5299 (.sym dst32-24-16-FB-relative-Unprefixed- xmode)
5300 (.sym dst32-24-16-absolute-Unprefixed- xmode)
5301 (.sym dst32-24-24-absolute-Unprefixed- xmode)
5302 )
5303 )
5304 (define-anyof-operand
5305 (name (.sym dst32-24-Prefixed- xmode))
5306 (comment (.str "m32c destination operand of size " xmode " with additional fields at offset 24"))
5307 (attrs (machine 32))
5308 (mode xmode)
5309 (choices
5310 (.sym dst32-Rn-direct-Prefixed- xmode)
5311 (.sym dst32-An-direct-Prefixed- xmode)
5312 (.sym dst32-An-indirect-Prefixed- xmode)
5313 (.sym dst32-24-8-An-relative-Prefixed- xmode)
5314 (.sym dst32-24-16-An-relative-Prefixed- xmode)
5315 (.sym dst32-24-24-An-relative-Prefixed- xmode)
5316 (.sym dst32-24-8-SB-relative-Prefixed- xmode)
5317 (.sym dst32-24-16-SB-relative-Prefixed- xmode)
5318 (.sym dst32-24-8-FB-relative-Prefixed- xmode)
5319 (.sym dst32-24-16-FB-relative-Prefixed- xmode)
5320 (.sym dst32-24-16-absolute-Prefixed- xmode)
5321 (.sym dst32-24-24-absolute-Prefixed- xmode)
5322 )
5323 )
5324 (define-anyof-operand
5325 (name (.sym dst32-24-8-Prefixed- xmode))
5326 (comment (.str "m32c destination operand of size " xmode " with additional fields at offset 24"))
5327 (attrs (machine 32))
5328 (mode xmode)
5329 (choices
5330 (.sym dst32-24-8-An-relative-Prefixed- xmode)
5331 (.sym dst32-24-8-SB-relative-Prefixed- xmode)
5332 (.sym dst32-24-8-FB-relative-Prefixed- xmode)
5333 )
5334 )
5335 (define-anyof-operand
5336 (name (.sym dst32-24-16-Prefixed- xmode))
5337 (comment (.str "m32c destination operand of size " xmode " with additional fields at offset 24"))
5338 (attrs (machine 32))
5339 (mode xmode)
5340 (choices
5341 (.sym dst32-24-16-An-relative-Prefixed- xmode)
5342 (.sym dst32-24-16-SB-relative-Prefixed- xmode)
5343 (.sym dst32-24-16-FB-relative-Prefixed- xmode)
5344 (.sym dst32-24-16-absolute-Prefixed- xmode)
5345 )
5346 )
5347 (define-anyof-operand
5348 (name (.sym dst32-24-24-Prefixed- xmode))
5349 (comment (.str "m32c destination operand of size " xmode " with additional fields at offset 24"))
5350 (attrs (machine 32))
5351 (mode xmode)
5352 (choices
5353 (.sym dst32-24-24-An-relative-Prefixed- xmode)
5354 (.sym dst32-24-24-absolute-Prefixed- xmode)
5355 )
5356 )
5357; (define-anyof-operand
5358; (name (.sym dst32-24-indirect- xmode))
5359; (comment (.str "m32c destination operand of size " xmode " with additional fields at offset 24"))
5360; (attrs (machine 32))
5361; (mode xmode)
5362; (choices
5363; (.sym dst32-An-indirect-indirect- xmode)
5364; (.sym dst32-24-8-An-relative-indirect- xmode)
5365; (.sym dst32-24-16-An-relative-indirect- xmode)
5366; (.sym dst32-24-24-An-relative-indirect- xmode)
5367; (.sym dst32-24-8-SB-relative-indirect- xmode)
5368; (.sym dst32-24-16-SB-relative-indirect- xmode)
5369; (.sym dst32-24-8-FB-relative-indirect- xmode)
5370; (.sym dst32-24-16-FB-relative-indirect- xmode)
5371; )
5372; )
5373; (define-anyof-operand
5374; (name (.sym dst32-basic-indirect- xmode))
5375; (comment (.str "m32c destination operand of size " xmode " with no additional fields"))
5376; (attrs (machine 32))
5377; (mode xmode)
5378; (choices
5379; (.sym dst32-An-indirect-indirect- xmode)
5380; )
5381; )
5382; (define-anyof-operand
5383; (name (.sym dst32-24-8-indirect- xmode))
5384; (comment (.str "m32c destination operand of size " xmode " with additional fields at offset 24"))
5385; (attrs (machine 32))
5386; (mode xmode)
5387; (choices
5388; (.sym dst32-24-8-An-relative-indirect- xmode)
5389; (.sym dst32-24-8-SB-relative-indirect- xmode)
5390; (.sym dst32-24-8-FB-relative-indirect- xmode)
5391; )
5392; )
5393; (define-anyof-operand
5394; (name (.sym dst32-24-16-indirect- xmode))
5395; (comment (.str "m32c destination operand of size " xmode " with additional fields at offset 24"))
5396; (attrs (machine 32))
5397; (mode xmode)
5398; (choices
5399; (.sym dst32-24-16-An-relative-indirect- xmode)
5400; (.sym dst32-24-16-SB-relative-indirect- xmode)
5401; (.sym dst32-24-16-FB-relative-indirect- xmode)
5402; )
5403; )
5404; (define-anyof-operand
5405; (name (.sym dst32-24-24-indirect- xmode))
5406; (comment (.str "m32c destination operand of size " xmode " with additional fields at offset 24"))
5407; (attrs (machine 32))
5408; (mode xmode)
5409; (choices
5410; (.sym dst32-24-24-An-relative-indirect- xmode)
5411; )
5412; )
5413; (define-anyof-operand
5414; (name (.sym dst32-24-absolute-indirect- xmode))
5415; (comment (.str "m32c destination operand of size " xmode " absolute indirect"))
5416; (attrs (machine 32))
5417; (mode xmode)
5418; (choices
5419; (.sym dst32-24-16-absolute-indirect-derived- xmode)
5420; (.sym dst32-24-24-absolute-indirect-derived- xmode)
5421; )
5422; )
5423; (define-anyof-operand
5424; (name (.sym dst32-24-16-absolute-indirect- xmode))
5425; (comment (.str "m32c destination operand of size " xmode " absolute indirect"))
5426; (attrs (machine 32))
5427; (mode xmode)
5428; (choices
5429; (.sym dst32-24-16-absolute-indirect-derived- xmode)
5430; )
5431; )
5432; (define-anyof-operand
5433; (name (.sym dst32-24-24-absolute-indirect- xmode))
5434; (comment (.str "m32c destination operand of size " xmode " absolute indirect"))
5435; (attrs (machine 32))
5436; (mode xmode)
5437; (choices
5438; (.sym dst32-24-24-absolute-indirect-derived- xmode)
5439; )
5440; )
5441 )
5442)
5443
5444(dst32-24-operand QI)
5445(dst32-24-operand HI)
5446(dst32-24-operand SI)
5447
5448;-------------------------------------------------------------
5449; Destination operands with possible additional fields at offset 32 bits
5450;-------------------------------------------------------------
5451
5452(define-pmacro (dst16-32-operand xmode)
5453 (begin
5454 (define-anyof-operand
5455 (name (.sym dst16-32- xmode))
5456 (comment (.str "m16c destination operand of size " xmode " with additional fields at offset 32"))
5457 (attrs (machine 16))
5458 (mode xmode)
5459 (choices
5460 (.sym dst16-Rn-direct- xmode)
5461 (.sym dst16-An-direct- xmode)
5462 (.sym dst16-An-indirect- xmode)
5463 (.sym dst16-32-8-An-relative- xmode)
5464 (.sym dst16-32-16-An-relative- xmode)
5465 (.sym dst16-32-8-SB-relative- xmode)
5466 (.sym dst16-32-16-SB-relative- xmode)
5467 (.sym dst16-32-8-FB-relative- xmode)
5468 (.sym dst16-32-16-absolute- xmode)
5469 )
5470 )
5471 )
5472)
5473(dst16-32-operand QI)
5474(dst16-32-operand HI)
5475
5476; This macro actually handles operands at offset 32, 40 and 48 bits
5477(define-pmacro (dst32-32plus-operand offset xmode)
5478 (begin
5479 (define-anyof-operand
5480 (name (.sym dst32- offset -Unprefixed- xmode))
5481 (comment (.str "m32c destination operand of size " xmode " with additional fields at offset 32"))
5482 (attrs (machine 32))
5483 (mode xmode)
5484 (choices
5485 (.sym dst32-Rn-direct-Unprefixed- xmode)
5486 (.sym dst32-An-direct-Unprefixed- xmode)
5487 (.sym dst32-An-indirect-Unprefixed- xmode)
5488 (.sym dst32- offset -8-An-relative-Unprefixed- xmode)
5489 (.sym dst32- offset -16-An-relative-Unprefixed- xmode)
5490 (.sym dst32- offset -24-An-relative-Unprefixed- xmode)
5491 (.sym dst32- offset -8-SB-relative-Unprefixed- xmode)
5492 (.sym dst32- offset -16-SB-relative-Unprefixed- xmode)
5493 (.sym dst32- offset -8-FB-relative-Unprefixed- xmode)
5494 (.sym dst32- offset -16-FB-relative-Unprefixed- xmode)
5495 (.sym dst32- offset -16-absolute-Unprefixed- xmode)
5496 (.sym dst32- offset -24-absolute-Unprefixed- xmode)
5497 )
5498 )
5499 (define-anyof-operand
5500 (name (.sym dst32- offset -Prefixed- xmode))
5501 (comment (.str "m32c destination operand of size " xmode " with additional fields at offset 32"))
5502 (attrs (machine 32))
5503 (mode xmode)
5504 (choices
5505 (.sym dst32-Rn-direct-Prefixed- xmode)
5506 (.sym dst32-An-direct-Prefixed- xmode)
5507 (.sym dst32-An-indirect-Prefixed- xmode)
5508 (.sym dst32- offset -8-An-relative-Prefixed- xmode)
5509 (.sym dst32- offset -16-An-relative-Prefixed- xmode)
5510 (.sym dst32- offset -24-An-relative-Prefixed- xmode)
5511 (.sym dst32- offset -8-SB-relative-Prefixed- xmode)
5512 (.sym dst32- offset -16-SB-relative-Prefixed- xmode)
5513 (.sym dst32- offset -8-FB-relative-Prefixed- xmode)
5514 (.sym dst32- offset -16-FB-relative-Prefixed- xmode)
5515 (.sym dst32- offset -16-absolute-Prefixed- xmode)
5516 (.sym dst32- offset -24-absolute-Prefixed- xmode)
5517 )
5518 )
5519; (define-anyof-operand
5520; (name (.sym dst32- offset -indirect- xmode))
5521; (comment (.str "m32c destination operand of size " xmode " with additional fields at offset 32"))
5522; (attrs (machine 32))
5523; (mode xmode)
5524; (choices
5525; (.sym dst32-An-indirect-indirect- xmode)
5526; (.sym dst32- offset -8-An-relative-indirect- xmode)
5527; (.sym dst32- offset -16-An-relative-indirect- xmode)
5528; (.sym dst32- offset -24-An-relative-indirect- xmode)
5529; (.sym dst32- offset -8-SB-relative-indirect- xmode)
5530; (.sym dst32- offset -16-SB-relative-indirect- xmode)
5531; (.sym dst32- offset -8-FB-relative-indirect- xmode)
5532; (.sym dst32- offset -16-FB-relative-indirect- xmode)
5533; )
5534; )
5535; (define-anyof-operand
5536; (name (.sym dst32- offset -absolute-indirect- xmode))
5537; (comment (.str "m32c destination operand of size " xmode " absolute indirect"))
5538; (attrs (machine 32))
5539; (mode xmode)
5540; (choices
5541; (.sym dst32- offset -16-absolute-indirect-derived- xmode)
5542; (.sym dst32- offset -24-absolute-indirect-derived- xmode)
5543; )
5544; )
5545 )
5546)
5547
5548(dst32-32plus-operand 32 QI)
5549(dst32-32plus-operand 32 HI)
5550(dst32-32plus-operand 32 SI)
5551(dst32-32plus-operand 40 QI)
5552(dst32-32plus-operand 40 HI)
5553(dst32-32plus-operand 40 SI)
5554
5555;-------------------------------------------------------------
5556; Destination operands with possible additional fields at offset 48 bits
5557;-------------------------------------------------------------
5558
5559(define-pmacro (dst32-48-operand offset xmode)
5560 (begin
5561 (define-anyof-operand
5562 (name (.sym dst32- offset -Prefixed- xmode))
5563 (comment (.str "m32c destination operand of size " xmode " with additional fields at offset 32"))
5564 (attrs (machine 32))
5565 (mode xmode)
5566 (choices
5567 (.sym dst32-Rn-direct-Prefixed- xmode)
5568 (.sym dst32-An-direct-Prefixed- xmode)
5569 (.sym dst32-An-indirect-Prefixed- xmode)
5570 (.sym dst32- offset -8-An-relative-Prefixed- xmode)
5571 (.sym dst32- offset -16-An-relative-Prefixed- xmode)
5572 (.sym dst32- offset -24-An-relative-Prefixed- xmode)
5573 (.sym dst32- offset -8-SB-relative-Prefixed- xmode)
5574 (.sym dst32- offset -16-SB-relative-Prefixed- xmode)
5575 (.sym dst32- offset -8-FB-relative-Prefixed- xmode)
5576 (.sym dst32- offset -16-FB-relative-Prefixed- xmode)
5577 (.sym dst32- offset -16-absolute-Prefixed- xmode)
5578 (.sym dst32- offset -24-absolute-Prefixed- xmode)
5579 )
5580 )
5581; (define-anyof-operand
5582; (name (.sym dst32- offset -indirect- xmode))
5583; (comment (.str "m32c destination operand of size " xmode " with additional fields at offset 32"))
5584; (attrs (machine 32))
5585; (mode xmode)
5586; (choices
5587; (.sym dst32-An-indirect-indirect- xmode)
5588; (.sym dst32- offset -8-An-relative-indirect- xmode)
5589; (.sym dst32- offset -16-An-relative-indirect- xmode)
5590; (.sym dst32- offset -24-An-relative-indirect- xmode)
5591; (.sym dst32- offset -8-SB-relative-indirect- xmode)
5592; (.sym dst32- offset -16-SB-relative-indirect- xmode)
5593; (.sym dst32- offset -8-FB-relative-indirect- xmode)
5594; (.sym dst32- offset -16-FB-relative-indirect- xmode)
5595; )
5596; )
5597; (define-anyof-operand
5598; (name (.sym dst32- offset -absolute-indirect- xmode))
5599; (comment (.str "m32c destination operand of size " xmode " absolute indirect"))
5600; (attrs (machine 32))
5601; (mode xmode)
5602; (choices
5603; (.sym dst32- offset -16-absolute-indirect-derived- xmode)
5604; (.sym dst32- offset -24-absolute-indirect-derived- xmode)
5605; )
5606; )
5607 )
5608)
5609
5610(dst32-48-operand 48 QI)
5611(dst32-48-operand 48 HI)
5612(dst32-48-operand 48 SI)
5613
5614;-------------------------------------------------------------
5615; Bit operands for m16c
5616;-------------------------------------------------------------
5617
5618(define-pmacro (bit16-operand offset)
5619 (begin
5620 (define-anyof-operand
5621 (name (.sym bit16- offset))
5622 (comment (.str "m16c bit operand with possible additional fields at offset 24"))
5623 (attrs (machine 16))
5624 (mode BI)
5625 (choices
5626 bit16-Rn-direct
5627 bit16-An-direct
5628 bit16-An-indirect
5629 (.sym bit16- offset -8-An-relative)
5630 (.sym bit16- offset -16-An-relative)
5631 (.sym bit16- offset -8-SB-relative)
5632 (.sym bit16- offset -16-SB-relative)
5633 (.sym bit16- offset -8-FB-relative)
5634 (.sym bit16- offset -16-absolute)
5635 )
5636 )
5637 (define-anyof-operand
5638 (name (.sym bit16- offset -basic))
5639 (comment (.str "m16c bit operand with no additional fields"))
5640 (attrs (machine 16))
5641 (mode BI)
5642 (choices
5643 bit16-An-indirect
5644 )
5645 )
5646 (define-anyof-operand
5647 (name (.sym bit16- offset -8))
5648 (comment (.str "m16c bit operand with possible additional fields at offset 24"))
5649 (attrs (machine 16))
5650 (mode BI)
5651 (choices
5652 bit16-Rn-direct
5653 bit16-An-direct
5654 (.sym bit16- offset -8-An-relative)
5655 (.sym bit16- offset -8-SB-relative)
5656 (.sym bit16- offset -8-FB-relative)
5657 )
5658 )
5659 (define-anyof-operand
5660 (name (.sym bit16- offset -16))
5661 (comment (.str "m16c bit operand with possible additional fields at offset 24"))
5662 (attrs (machine 16))
5663 (mode BI)
5664 (choices
5665 (.sym bit16- offset -16-An-relative)
5666 (.sym bit16- offset -16-SB-relative)
5667 (.sym bit16- offset -16-absolute)
5668 )
5669 )
5670 )
5671)
5672
5673(bit16-operand 16)
5674
5675;-------------------------------------------------------------
5676; Bit operands for m32c
5677;-------------------------------------------------------------
5678
5679(define-pmacro (bit32-operand offset group)
5680 (begin
5681 (define-anyof-operand
5682 (name (.sym bit32- offset - group))
5683 (comment (.str "m32c bit operand with possible additional fields at offset 24"))
5684 (attrs (machine 32))
5685 (mode BI)
5686 (choices
5687 (.sym bit32-Rn-direct- group)
5688 (.sym bit32-An-direct- group)
5689 (.sym bit32-An-indirect- group)
5690 (.sym bit32- offset -11-An-relative- group)
5691 (.sym bit32- offset -19-An-relative- group)
5692 (.sym bit32- offset -27-An-relative- group)
5693 (.sym bit32- offset -11-SB-relative- group)
5694 (.sym bit32- offset -19-SB-relative- group)
5695 (.sym bit32- offset -11-FB-relative- group)
5696 (.sym bit32- offset -19-FB-relative- group)
5697 (.sym bit32- offset -19-absolute- group)
5698 (.sym bit32- offset -27-absolute- group)
5699 )
5700 )
5701 )
5702)
5703
5704(bit32-operand 16 Unprefixed)
5705(bit32-operand 24 Prefixed)
5706
5707(define-anyof-operand
5708 (name bit32-basic-Unprefixed)
5709 (comment "m32c bit operand with no additional fields")
5710 (attrs (machine 32))
5711 (mode BI)
5712 (choices
5713 bit32-Rn-direct-Unprefixed
5714 bit32-An-direct-Unprefixed
5715 bit32-An-indirect-Unprefixed
5716 )
5717)
5718
5719(define-anyof-operand
5720 (name bit32-16-8-Unprefixed)
5721 (comment "m32c bit operand with 8 bit additional fields")
5722 (attrs (machine 32))
5723 (mode BI)
5724 (choices
5725 bit32-16-11-An-relative-Unprefixed
5726 bit32-16-11-SB-relative-Unprefixed
5727 bit32-16-11-FB-relative-Unprefixed
5728 )
5729)
5730
5731(define-anyof-operand
5732 (name bit32-16-16-Unprefixed)
5733 (comment "m32c bit operand with 16 bit additional fields")
5734 (attrs (machine 32))
5735 (mode BI)
5736 (choices
5737 bit32-16-19-An-relative-Unprefixed
5738 bit32-16-19-SB-relative-Unprefixed
5739 bit32-16-19-FB-relative-Unprefixed
5740 bit32-16-19-absolute-Unprefixed
5741 )
5742)
5743
5744(define-anyof-operand
5745 (name bit32-16-24-Unprefixed)
5746 (comment "m32c bit operand with 24 bit additional fields")
5747 (attrs (machine 32))
5748 (mode BI)
5749 (choices
5750 bit32-16-27-An-relative-Unprefixed
5751 bit32-16-27-absolute-Unprefixed
5752 )
5753)
5754
5755;-------------------------------------------------------------
5756; Operands for short format binary insns
5757;-------------------------------------------------------------
5758
5759(define-anyof-operand
5760 (name src16-2-S)
5761 (comment "m16c source operand of size QI for short format insns")
5762 (attrs (machine 16))
5763 (mode QI)
5764 (choices
5765 src16-2-S-8-SB-relative-QI
5766 src16-2-S-8-FB-relative-QI
5767 src16-2-S-16-absolute-QI
5768 )
5769)
5770
5771(define-anyof-operand
5772 (name src32-2-S-QI)
5773 (comment "m32c source operand of size QI for short format insns")
5774 (attrs (machine 32))
5775 (mode QI)
5776 (choices
5777 src32-2-S-8-SB-relative-QI
5778 src32-2-S-8-FB-relative-QI
5779 src32-2-S-16-absolute-QI
5780 )
5781)
5782
5783(define-anyof-operand
5784 (name src32-2-S-HI)
5785 (comment "m32c source operand of size QI for short format insns")
5786 (attrs (machine 32))
5787 (mode HI)
5788 (choices
5789 src32-2-S-8-SB-relative-HI
5790 src32-2-S-8-FB-relative-HI
5791 src32-2-S-16-absolute-HI
5792 )
5793)
5794
5795(define-anyof-operand
5796 (name Dst16-3-S-8)
5797 (comment "m16c destination operand of size QI for short format insns")
5798 (attrs (machine 16))
5799 (mode QI)
5800 (choices
5801 dst16-3-S-R0l-direct-QI
5802 dst16-3-S-R0h-direct-QI
5803 dst16-3-S-8-8-SB-relative-QI
5804 dst16-3-S-8-8-FB-relative-QI
5805 dst16-3-S-8-16-absolute-QI
5806 )
5807)
5808
5809(define-anyof-operand
5810 (name Dst16-3-S-16)
5811 (comment "m16c destination operand of size QI for short format insns")
5812 (attrs (machine 16))
5813 (mode QI)
5814 (choices
5815 dst16-3-S-R0l-direct-QI
5816 dst16-3-S-R0h-direct-QI
5817 dst16-3-S-16-8-SB-relative-QI
5818 dst16-3-S-16-8-FB-relative-QI
5819 dst16-3-S-16-16-absolute-QI
5820 )
5821)
5822
5823(define-anyof-operand
5824 (name srcdst16-r0l-r0h-S)
5825 (comment "m16c r0l/r0h operand of size QI for short format insns")
5826 (attrs (machine 16))
5827 (mode SI)
5828 (choices
5829 srcdst16-r0l-r0h-S-derived
5830 )
5831)
5832
5833(define-anyof-operand
5834 (name dst32-2-S-basic-QI)
5835 (comment "m32c r0l operand of size QI for short format binary insns")
5836 (attrs (machine 32))
5837 (mode QI)
5838 (choices
5839 dst32-2-S-R0l-direct-QI
5840 )
5841)
5842
5843(define-anyof-operand
5844 (name dst32-2-S-basic-HI)
5845 (comment "m32c r0 operand of size HI for short format binary insns")
5846 (attrs (machine 32))
5847 (mode HI)
5848 (choices
5849 dst32-2-S-R0-direct-HI
5850 )
5851)
5852
5853(define-pmacro (dst32-2-S-operands xmode)
5854 (begin
5855 (define-anyof-operand
5856 (name (.sym dst32-2-S-8- xmode))
5857 (comment "m32c operand of size " xmode " for short format binary insns")
5858 (attrs (machine 32))
5859 (mode xmode)
5860 (choices
5861 (.sym dst32-2-S-8-SB-relative- xmode)
5862 (.sym dst32-2-S-8-FB-relative- xmode)
5863 )
5864 )
5865 (define-anyof-operand
5866 (name (.sym dst32-2-S-16- xmode))
5867 (comment "m32c operand of size " xmode " for short format binary insns")
5868 (attrs (machine 32))
5869 (mode xmode)
5870 (choices
5871 (.sym dst32-2-S-16-absolute- xmode)
5872 )
5873 )
5874; (define-anyof-operand
5875; (name (.sym dst32-2-S-8-indirect- xmode))
5876; (comment "m32c operand of size " xmode " for short format binary insns")
5877; (attrs (machine 32))
5878; (mode xmode)
5879; (choices
5880; (.sym dst32-2-S-8-SB-relative-indirect- xmode)
5881; (.sym dst32-2-S-8-FB-relative-indirect- xmode)
5882; )
5883; )
5884; (define-anyof-operand
5885; (name (.sym dst32-2-S-absolute-indirect- xmode))
5886; (comment "m32c operand of size " xmode " for short format binary insns")
5887; (attrs (machine 32))
5888; (mode xmode)
5889; (choices
5890; (.sym dst32-2-S-16-absolute-indirect- xmode)
5891; )
5892; )
5893 )
5894)
5895
5896(dst32-2-S-operands QI)
5897(dst32-2-S-operands HI)
5898(dst32-2-S-operands SI)
5899
5900(define-anyof-operand
5901 (name dst32-an-S)
5902 (comment "m32c An operand for short format binary insns")
5903 (attrs (machine 32))
5904 (mode HI)
5905 (choices
5906 dst32-1-S-A0-direct-HI
5907 dst32-1-S-A1-direct-HI
5908 )
5909)
5910
5911(define-anyof-operand
5912 (name bit16-11-S)
5913 (comment "m16c bit operand for short format insns")
5914 (attrs (machine 16))
5915 (mode BI)
5916 (choices
5917 bit16-11-SB-relative-S
5918 )
5919)
5920
5921(define-anyof-operand
5922 (name Rn16-push-S-anyof)
5923 (comment "m16c bit operand for short format insns")
5924 (attrs (machine 16))
5925 (mode QI)
5926 (choices
5927 Rn16-push-S-derived
5928 )
5929)
5930
5931(define-anyof-operand
5932 (name An16-push-S-anyof)
5933 (comment "m16c bit operand for short format insns")
5934 (attrs (machine 16))
5935 (mode HI)
5936 (choices
5937 An16-push-S-derived
5938 )
5939)
5940
5941;=============================================================
5942; Common macros for instruction definitions
5943;
5944(define-pmacro (set-z x)
5945 (sequence ()
5946 (set zbit (zflag x)))
5947
5948)
5949
5950(define-pmacro (set-s x)
5951 (sequence ()
5952 (set sbit (nflag x)))
5953)
5954
5955(define-pmacro (set-z-and-s x)
5956 (sequence ()
5957 (set-z x)
5958 (set-s x))
5959)
5960\f
5961;=============================================================
5962; Unary insn macros
5963;-------------------------------------------------------------
5964
c6552317 5965(define-pmacro (unary-insn-defn-g mach group mode wstr op encoding sem opg)
49f58d10 5966 (dni (.sym op mach wstr - group)
c6552317 5967 (.str op wstr opg " dst" mach "-" group "-" mode)
6772dd07 5968 ((machine mach) RL_1ADDR)
c6552317 5969 (.str op wstr opg " ${dst" mach "-" group "-" mode "}")
49f58d10
JB		 5970 encoding
5971 (sem mode (.sym dst mach - group - mode))
5972 ())
5973)
5974
c6552317
DD		 5975(define-pmacro (unary-insn-defn mach group mode wstr op encoding sem)
5976 (unary-insn-defn-g mach group mode wstr op encoding sem "")
5977)
5978
49f58d10 5979
c6552317
DD		 5980(define-pmacro (unary16-defn-g mode wstr wbit op opc1 opc2 opc3 sem opg)
5981 (unary-insn-defn-g 16 16 mode wstr op
5982 (+ opc1 opc2 (f-7-1 wbit) opc3 (.sym dst16-16- mode))
5983 sem opg)
5984)
49f58d10 5985(define-pmacro (unary16-defn mode wstr wbit op opc1 opc2 opc3 sem)
c6552317 5986 (unary-16-defn-g mode wstr wbit op opc1 opc2 opc3 sem "")
49f58d10
JB		 5987)
5988
c6552317 5989(define-pmacro (unary32-defn-g mode wstr wbit op opc1 opc2 opc3 sem opg)
49f58d10
JB		 5990 (begin
5991 ; Multi insns are tried for assembly in the reverse order in which they appear here, so
5992 ; define the absolute-indirect insns first in order to prevent them from being selected
5993 ; when the mode is register-indirect
5994; (unary-insn-defn 32 24-absolute-indirect mode wstr op
5995; (+ (f-0-4 0) (f-4-4 9) (f-8-4 opc1) (f-15-1 wbit) (.sym dst32-24-absolute-indirect- mode) (f-18-2 opc2) (f-20-4 opc3))
5996; sem)
c6552317
DD		 5997 (unary-insn-defn-g 32 16-Unprefixed mode wstr op
5998 (+ (f-0-4 opc1) (f-7-1 wbit) (.sym dst32-16-Unprefixed- mode) (f-10-2 opc2) (f-12-4 opc3))
5999 sem opg)
49f58d10
JB		 6000; (unary-insn-defn 32 24-indirect mode wstr op
6001; (+ (f-0-4 0) (f-4-4 9) (f-8-4 opc1) (f-15-1 wbit) (.sym dst32-24-indirect- mode) (f-18-2 opc2) (f-20-4 opc3))
6002; sem)
6003 )
6004)
c6552317
DD		 6005(define-pmacro (unary32-defn mode wstr wbit op opc1 opc2 opc3 sem)
6006 (unary32-defn-g mode wstr wbit op opc1 opc2 opc3 sem "")
6007)
49f58d10 6008
c6552317 6009(define-pmacro (unary-insn-mach-g mach op opc1 opc2 opc3 sem opg)
49f58d10 6010 (begin
c6552317
DD		 6011 (.apply (.sym unary mach -defn-g) (QI .b 0 op opc1 opc2 opc3 sem opg))
6012 (.apply (.sym unary mach -defn-g) (HI .w 1 op opc1 opc2 opc3 sem opg))
49f58d10
JB		 6013 )
6014)
c6552317
DD		 6015(define-pmacro (unary-insn-mach mach op opc1 opc2 opc3 sem)
6016 (unary-insn-mach-g mach op opc1 opc2 opc3 sem "")
6017)
49f58d10
JB		 6018
6019(define-pmacro (unary-insn op opc16-1 opc16-2 opc16-3 opc32-1 opc32-2 opc32-3 sem)
6020 (begin
c6552317
DD		 6021 (unary-insn-mach-g 16 op opc16-1 opc16-2 opc16-3 sem "")
6022 (unary-insn-mach-g 32 op opc32-1 opc32-2 opc32-3 sem "")
6023 )
6024)
6025
6026(define-pmacro (unary-insn-g op opc16-1 opc16-2 opc16-3 opc32-1 opc32-2 opc32-3 sem)
6027 (begin
6028 (unary-insn-mach-g 16 op opc16-1 opc16-2 opc16-3 sem "$G")
6029 (unary-insn-mach-g 32 op opc32-1 opc32-2 opc32-3 sem "$G")
49f58d10
JB		 6030 )
6031)
6032
6033;-------------------------------------------------------------
6034; Sign/zero extension macros
6035;-------------------------------------------------------------
6036
6037(define-pmacro (ext-insn-defn mach group smode dmode wstr op encoding sem)
6038 (dni (.sym op mach wstr - group)
6039 (.str op wstr " dst" mach "-" group "-" smode)
6040 ((machine mach))
6041 (.str op wstr " ${dst" mach "-" group "-" smode "}")
6042 encoding
6043 (sem smode dmode (.sym dst mach - group - smode) (.sym dst mach - group - smode))
6044 ())
6045)
6046
6047(define-pmacro (ext16-defn smode dmode wstr wbit op opc1 opc2 opc3 sem)
6048 (ext-insn-defn 16 16-Ext smode dmode wstr op
6049 (+ opc1 opc2 (f-7-1 wbit) opc3 (.sym dst16-16-Ext- smode))
6050 sem)
6051)
6052
6053(define-pmacro (ext32-defn smode dmode wstr wbit op opc1 opc2 opc3 sem)
6054 (ext-insn-defn 32 16-ExtUnprefixed smode dmode wstr op
6055 (+ opc1 opc2 (f-7-1 wbit) opc3 (.sym dst32-16-ExtUnprefixed- smode))
6056 sem)
6057)
6058
6059(define-pmacro (ext32-binary-insn src-group dst-group op wstr encoding sem)
6060 (dni (.sym op 32 wstr - src-group - dst-group)
6061 (.str op 32 wstr " src32-" src-group "-QI,dst32-" dst-group "-HI")
6062 ((machine 32))
6063 (.str op wstr " ${src32-" src-group "-QI},${dst32-" dst-group "-HI}")
6064 encoding
6065 (sem QI HI (.sym src32- src-group -QI) (.sym dst32 - dst-group -HI))
6066 ())
6067)
6068
6069(define-pmacro (ext32-binary-defn op wstr opc1 opc2 sem)
6070 (begin
6071 (ext32-binary-insn basic-ExtPrefixed 24-Prefixed op wstr
6072 (+ (f-0-4 0) (f-4-4 1) (f-8-1 opc1) (f-15-1 0) src32-basic-ExtPrefixed-QI dst32-24-Prefixed-HI (f-20-4 opc2))
6073 sem)
6074 (ext32-binary-insn 24-24-Prefixed 48-Prefixed op wstr
6075 (+ (f-0-4 0) (f-4-4 1) (f-8-1 opc1) (f-15-1 0) src32-24-24-Prefixed-QI dst32-48-Prefixed-HI (f-20-4 opc2))
6076 sem)
6077 (ext32-binary-insn 24-16-Prefixed 40-Prefixed op wstr
6078 (+ (f-0-4 0) (f-4-4 1) (f-8-1 opc1) (f-15-1 0) src32-24-16-Prefixed-QI dst32-40-Prefixed-HI (f-20-4 opc2))
6079 sem)
6080 (ext32-binary-insn 24-8-Prefixed 32-Prefixed op wstr
6081 (+ (f-0-4 0) (f-4-4 1) (f-8-1 opc1) (f-15-1 0) src32-24-8-Prefixed-QI dst32-32-Prefixed-HI (f-20-4 opc2))
6082 sem)
6083 )
6084)
6085
6086;=============================================================
6087; Binary Arithmetic macros
6088;
6089;-------------------------------------------------------------
6090;<arith>.size:S src2,r0[l] -- for m32c
6091;-------------------------------------------------------------
6092
6093(define-pmacro (binary-arith32-S-src2 op xmode wstr wbit opc1 opc2 sem)
6094 (dni (.sym op 32 wstr .S-src2-r0- xmode)
6095 (.str op 32 wstr ":S src2,r0[l]")
6096 ((machine 32))
6097 (.str op wstr"$S ${src32-2-S-" xmode "},${Dst32R0" xmode "-S}")
6098 (+ opc1 opc2 (.sym src32-2-S- xmode) (f-7-1 wbit))
6099 (sem xmode (.sym src32-2-S- xmode) (.sym Dst32R0 xmode -S))
6100 ())
6101)
6102
6103;-------------------------------------------------------------
6104;<arith>.b:S src2,r0l/r0h -- for m16c
6105;-------------------------------------------------------------
6106
6107(define-pmacro (binary-arith16-b-S-src2 op opc1 opc2 sem)
6108 (begin
6109 (dni (.sym op 16 .b.S-src2)
6110 (.str op ".b:S src2,r0[lh]")
6111 ((machine 16))
6112 (.str op ".b$S ${src16-2-S},${Dst16RnQI-S}")
6113 (+ opc1 opc2 Dst16RnQI-S src16-2-S)
6114 (sem QI src16-2-S Dst16RnQI-S)
6115 ())
6116 (dni (.sym op 16 .b.S-r0l-r0h)
6117 (.str op ".b:S r0l/r0h")
6118 ((machine 16))
6119 (.str op ".b$S ${srcdst16-r0l-r0h-S}")
6120 (+ opc1 opc2 srcdst16-r0l-r0h-S)
6121 (if (eq srcdst16-r0l-r0h-S 0)
6122 (sem QI R0h R0l)
6123 (sem QI R0l R0h))
6124 ())
6125 )
6126)
6127
6128;-------------------------------------------------------------
6129;<arith>.b:S #imm8,dst3 -- for m16c
6130;-------------------------------------------------------------
6131
6132(define-pmacro (binary-arith16-b-S-imm8-dst3 op sz opc1 opc2 sem)
6133 (dni (.sym op 16 .b.S-imm8-dst3)
6134 (.str op sz ":S imm8,dst3")
6135 ((machine 16))
6136 (.str op sz "$S #${Imm-8-QI},${Dst16-3-S-16}")
6137 (+ opc1 opc2 Dst16-3-S-16 Imm-8-QI)
6138 (sem QI Imm-8-QI Dst16-3-S-16)
6139 ())
6140)
6141
6142;-------------------------------------------------------------
6143;<arith>.size:Q #imm4,sp -- for m16c
6144;-------------------------------------------------------------
6145
6146(define-pmacro (binary-arith16-Q-sp op opc1 opc2 opc3 sem)
92e0a941
DD		 6147 (dni (.sym op 16 -wQ-sp)
6148 (.str op ".w:q #imm4,sp")
49f58d10 6149 ((machine 16))
92e0a941 6150 (.str op ".w$Q #${Imm-12-s4},sp")
49f58d10
JB		 6151 (+ opc1 opc2 opc3 Imm-12-s4)
6152 (sem QI Imm-12-s4 sp)
6153 ())
6154)
6155
6156;-------------------------------------------------------------
6157;<arith>.size:G #imm,sp -- for m16c
6158;-------------------------------------------------------------
6159
6160(define-pmacro (binary-arith16-G-sp-defn mode wstr wbit op opc1 opc2 opc3 opc4 sem)
6161 (dni (.sym op 16 wstr - G-sp)
6162 (.str op wstr " imm-sp " mode)
6163 ((machine 16))
6164 (.str op wstr "$G #${Imm-16-" mode "},sp")
6165 (+ opc1 opc2 (f-7-1 wbit) opc3 opc4 (.sym Imm-16- mode))
6166 (sem mode (.sym Imm-16- mode) sp)
6167 ())
6168)
6169
6170(define-pmacro (binary-arith16-G-sp op opc1 opc2 opc3 opc4 sem)
6171 (begin
6172 (binary-arith16-G-sp-defn QI .b 0 op opc1 opc2 opc3 opc4 sem)
6173 (binary-arith16-G-sp-defn HI .w 1 op opc1 opc2 opc3 opc4 sem)
6174 )
6175)
6176
6177;-------------------------------------------------------------
6178;<arith>.size:G #imm,dst -- for m16c and m32c
6179;-------------------------------------------------------------
6180
6181(define-pmacro (binary-arith-imm-dst-defn mach src dstgroup dmode wstr op suffix encoding sem)
6182 (dni (.sym op mach wstr - imm-G - dstgroup)
6183 (.str op wstr " " mach "-imm-G-" dstgroup "-" dmode)
6772dd07 6184 ((machine mach) RL_1ADDR)
49f58d10
JB		 6185 (.str op wstr "$"suffix " #${" src "},${dst" mach "-" dstgroup "-" dmode "}")
6186 encoding
6187 (sem dmode src (.sym dst mach - dstgroup - dmode))
6188 ())
6189)
6190
6191; m16c variants
6192(define-pmacro (binary-arith16-imm-dst-defn smode dmode wstr wbit op suffix opc1 opc2 opc3 sem)
6193 (begin
6194 (binary-arith-imm-dst-defn 16 (.sym Imm-32- smode) 16-16 dmode wstr op suffix
6195 (+ opc1 opc2 (f-7-1 wbit) opc3 (.sym dst16-16-16- dmode) (.sym Imm-32- smode))
6196 sem)
6197 (binary-arith-imm-dst-defn 16 (.sym Imm-24- smode) 16-8 dmode wstr op suffix
6198 (+ opc1 opc2 (f-7-1 wbit) opc3 (.sym dst16-16-8- dmode) (.sym Imm-24- smode))
6199 sem)
6200 (binary-arith-imm-dst-defn 16 (.sym Imm-16- smode) basic dmode wstr op suffix
6201 (+ opc1 opc2 (f-7-1 wbit) opc3 (.sym dst16-basic- dmode) (.sym Imm-16- smode))
6202 sem)
6203 )
6204)
6205
6206; m32c Unprefixed variants
6207(define-pmacro (binary-arith32-imm-dst-Unprefixed smode dmode wstr wbit op suffix opc1 opc2 opc3 sem)
6208 (begin
6209 (binary-arith-imm-dst-defn 32 (.sym Imm-40- smode) 16-24-Unprefixed dmode wstr op suffix
6210 (+ (f-0-4 opc1) (f-10-2 opc2) (f-7-1 wbit) (f-12-4 opc3) (.sym dst32-16-24-Unprefixed- dmode) (.sym Imm-40- smode))
6211 sem)
6212 (binary-arith-imm-dst-defn 32 (.sym Imm-32- smode) 16-16-Unprefixed dmode wstr op suffix
6213 (+ (f-0-4 opc1) (f-10-2 opc2) (f-7-1 wbit) (f-12-4 opc3) (.sym dst32-16-16-Unprefixed- dmode) (.sym Imm-32- smode))
6214 sem)
6215 (binary-arith-imm-dst-defn 32 (.sym Imm-24- smode) 16-8-Unprefixed dmode wstr op suffix
6216 (+ (f-0-4 opc1) (f-10-2 opc2) (f-7-1 wbit) (f-12-4 opc3) (.sym dst32-16-8-Unprefixed- dmode) (.sym Imm-24- smode))
6217 sem)
6218 (binary-arith-imm-dst-defn 32 (.sym Imm-16- smode) basic-Unprefixed dmode wstr op suffix
6219 (+ (f-0-4 opc1) (f-10-2 opc2) (f-7-1 wbit) (f-12-4 opc3) (.sym dst32-basic-Unprefixed- dmode) (.sym Imm-16- smode))
6220 sem)
6221 )
6222)
6223
6224; m32c Prefixed variants
6225(define-pmacro (binary-arith32-imm-dst-Prefixed smode dmode wstr wbit op suffix opc1 opc2 opc3 sem)
6226 (begin
6227 (binary-arith-imm-dst-defn 32 (.sym Imm-48- smode) 24-24-Prefixed dmode wstr op suffix
6228 (+ (f-0-4 0) (f-4-4 1) (f-8-4 opc1) (f-18-2 opc2) (f-15-1 wbit) (f-20-4 opc3) (.sym dst32-24-24-Prefixed- dmode) (.sym Imm-48- smode))
6229 sem)
6230 (binary-arith-imm-dst-defn 32 (.sym Imm-40- smode) 24-16-Prefixed dmode wstr op suffix
6231 (+ (f-0-4 0) (f-4-4 1) (f-8-4 opc1) (f-18-2 opc2) (f-15-1 wbit) (f-20-4 opc3) (.sym dst32-24-16-Prefixed- dmode) (.sym Imm-40- smode))
6232 sem)
6233 (binary-arith-imm-dst-defn 32 (.sym Imm-32- smode) 24-8-Prefixed dmode wstr op suffix
6234 (+ (f-0-4 0) (f-4-4 1) (f-8-4 opc1) (f-18-2 opc2) (f-15-1 wbit) (f-20-4 opc3) (.sym dst32-24-8-Prefixed- dmode) (.sym Imm-32- smode))
6235 sem)
6236 (binary-arith-imm-dst-defn 32 (.sym Imm-24- smode) basic-Prefixed dmode wstr op suffix
6237 (+ (f-0-4 0) (f-4-4 1) (f-8-4 opc1) (f-18-2 opc2) (f-15-1 wbit) (f-20-4 opc3) (.sym dst32-basic-Prefixed- dmode) (.sym Imm-24- smode))
6238 sem)
6239 )
6240)
6241
6242; All m32c variants
6243(define-pmacro (binary-arith32-imm-dst-defn smode dmode wstr wbit op suffix opc1 opc2 opc3 sem)
6244 (begin
6245 ; Multi insns are tried for assembly in the reverse order in which they appear here, so
6246 ; define the absolute-indirect insns first in order to prevent them from being selected
6247 ; when the mode is register-indirect
6248; (binary-arith-imm-dst-defn 32 (.sym Imm-48- smode) 24-24-absolute-indirect dmode wstr op suffix
6249; (+ (f-0-4 0) (f-4-4 9) (f-8-4 opc1) (f-18-2 opc2) (f-15-1 wbit) (f-20-4 opc3) (.sym dst32-24-24-absolute-indirect- dmode) (.sym Imm-48- smode))
6250; sem)
6251; (binary-arith-imm-dst-defn 32 (.sym Imm-40- smode) 24-16-absolute-indirect dmode wstr op suffix
6252; (+ (f-0-4 0) (f-4-4 9) (f-8-4 opc1) (f-18-2 opc2) (f-15-1 wbit) (f-20-4 opc3) (.sym dst32-24-16-absolute-indirect- dmode) (.sym Imm-40- smode))
6253; sem)
6254 ; Unprefixed modes next
6255 (binary-arith32-imm-dst-Unprefixed smode dmode wstr wbit op suffix opc1 opc2 opc3 sem)
6256
6257 ; Remaining indirect modes
6258; (binary-arith-imm-dst-defn 32 (.sym Imm-24- smode) basic-indirect dmode wstr op suffix
6259; (+ (f-0-4 0) (f-4-4 9) (f-8-4 opc1) (f-18-2 opc2) (f-15-1 wbit) (f-20-4 opc3) (.sym dst32-basic-indirect- dmode) (.sym Imm-24- smode))
6260; sem)
6261; (binary-arith-imm-dst-defn 32 (.sym Imm-48- smode) 24-24-indirect dmode wstr op suffix
6262; (+ (f-0-4 0) (f-4-4 9) (f-8-4 opc1) (f-18-2 opc2) (f-15-1 wbit) (f-20-4 opc3) (.sym dst32-24-24-indirect- dmode) (.sym Imm-48- smode))
6263; sem)
6264; (binary-arith-imm-dst-defn 32 (.sym Imm-40- smode) 24-16-indirect dmode wstr op suffix
6265; (+ (f-0-4 0) (f-4-4 9) (f-8-4 opc1) (f-18-2 opc2) (f-15-1 wbit) (f-20-4 opc3) (.sym dst32-24-16-indirect- dmode) (.sym Imm-40- smode))
6266; sem)
6267; (binary-arith-imm-dst-defn 32 (.sym Imm-32- smode) 24-8-indirect dmode wstr op suffix
6268; (+ (f-0-4 0) (f-4-4 9) (f-8-4 opc1) (f-18-2 opc2) (f-15-1 wbit) (f-20-4 opc3) (.sym dst32-24-8-indirect- dmode) (.sym Imm-32- smode))
6269; sem)
6270 )
6271)
6272
6273(define-pmacro (binary-arith-imm-dst-mach mach op suffix opc1 opc2 opc3 sem)
6274 (begin
6275 (.apply (.sym binary-arith mach -imm-dst-defn) (QI QI .b 0 op suffix opc1 opc2 opc3 sem))
6276 (.apply (.sym binary-arith mach -imm-dst-defn) (HI HI .w 1 op suffix opc1 opc2 opc3 sem))
6277 )
6278)
6279
6280(define-pmacro (binary-arith-imm-dst op suffix opc16-1 opc16-2 opc16-3 opc32-1 opc32-2 opc32-3 sem)
6281 (begin
6282 (binary-arith-imm-dst-mach 16 op suffix opc16-1 opc16-2 opc16-3 sem)
6283 (binary-arith-imm-dst-mach 32 op suffix opc32-1 opc32-2 opc32-3 sem)
6284 )
6285)
6286
6287;-------------------------------------------------------------
6288;<arith>.size:Q #imm4,dst -- for m16c and m32c
6289;-------------------------------------------------------------
6290
6291(define-pmacro (binary-arith-imm4-dst-defn mach src dstgroup mode wstr op encoding sem)
6292 (dni (.sym op mach wstr - imm4-Q - dstgroup)
6293 (.str op wstr " " mach "-imm4-Q-" dstgroup "-" mode)
6772dd07 6294 ((machine mach) RL_1ADDR)
49f58d10
JB		 6295 (.str op wstr "$Q #${" src "},${dst" mach "-" dstgroup "-" mode "}")
6296 encoding
6297 (sem mode src (.sym dst mach - dstgroup - mode))
6298 ())
6299)
6300
6301; m16c variants
6302(define-pmacro (binary-arith16-imm4-dst-defn mode wstr wbit1 wbit2 op opc1 opc2 sem)
6303 (binary-arith-imm4-dst-defn 16 Imm-8-s4 16 mode wstr op
6304 (+ opc1 opc2 (f-7-1 wbit2) Imm-8-s4 (.sym dst16-16- mode))
6305 sem)
6306)
6307
6308(define-pmacro (binary-arith16-shimm4-dst-defn mode wstr wbit1 wbit2 op opc1 opc2 sem)
6309 (binary-arith-imm4-dst-defn 16 Imm-sh-8-s4 16 mode wstr op
6310 (+ opc1 opc2 (f-7-1 wbit2) Imm-sh-8-s4 (.sym dst16-16- mode))
6311 sem)
6312)
6313
6314; m32c variants
6315(define-pmacro (binary-arith32-imm4-dst-defn mode wstr wbit1 wbit2 op opc1 opc2 sem)
6316 (begin
6317 ; Multi insns are tried for assembly in the reverse order in which they appear here, so
6318 ; define the absolute-indirect insns first in order to prevent them from being selected
6319 ; when the mode is register-indirect
6320; (binary-arith-imm4-dst-defn 32 Imm-20-s4 24-absolute-indirect mode wstr op
6321; (+ (f-0-4 0) (f-4-4 9) (f-8-3 opc1) (f-11-1 wbit1) (f-15-1 wbit2) (.sym dst32-24-absolute-indirect- mode) (f-18-2 opc2) Imm-20-s4)
6322; sem)
6323 (binary-arith-imm4-dst-defn 32 Imm-12-s4 16-Unprefixed mode wstr op
6324 (+ (f-0-3 opc1) (f-3-1 wbit1) (f-7-1 wbit2) (.sym dst32-16-Unprefixed- mode) (f-10-2 opc2) Imm-12-s4)
6325 sem)
6326; (binary-arith-imm4-dst-defn 32 Imm-20-s4 24-indirect mode wstr op
6327; (+ (f-0-4 0) (f-4-4 9) (f-8-3 opc1) (f-11-1 wbit1) (f-15-1 wbit2) (.sym dst32-24-indirect- mode) (f-18-2 opc2) Imm-20-s4)
6328; sem)
6329 )
6330)
6331
6332(define-pmacro (binary-arith32-shimm4-dst-defn mode wstr wbit1 wbit2 op opc1 opc2 sem)
6333 (begin
6334 ; Multi insns are tried for assembly in the reverse order in which they appear here, so
6335 ; define the absolute-indirect insns first in order to prevent them from being selected
6336 ; when the mode is register-indirect
6337; (binary-arith-imm4-dst-defn 32 Imm-sh-20-s4 24-absolute-indirect mode wstr op
6338; (+ (f-0-4 0) (f-4-4 9) (f-8-3 opc1) (f-11-1 wbit1) (f-15-1 wbit2) (.sym dst32-24-absolute-indirect- mode) (f-18-2 opc2) Imm-sh-20-s4)
6339; sem)
6340 (binary-arith-imm4-dst-defn 32 Imm-sh-12-s4 16-Unprefixed mode wstr op
6341 (+ (f-0-3 opc1) (f-3-1 wbit1) (f-7-1 wbit2) (.sym dst32-16-Unprefixed- mode) (f-10-2 opc2) Imm-sh-12-s4)
6342 sem)
6343; (binary-arith-imm4-dst-defn 32 Imm-sh-20-s4 24-indirect mode wstr op
6344; (+ (f-0-4 0) (f-4-4 9) (f-8-3 opc1) (f-11-1 wbit1) (f-15-1 wbit2) (.sym dst32-24-indirect- mode) (f-18-2 opc2) Imm-sh-20-s4)
6345; sem)
6346 )
6347)
6348
6349(define-pmacro (binary-arith-imm4-dst-mach mach op opc1 opc2 sem)
6350 (begin
6351 (.apply (.sym binary-arith mach -imm4-dst-defn) (QI .b 0 0 op opc1 opc2 sem))
6352 (.apply (.sym binary-arith mach -imm4-dst-defn) (HI .w 0 1 op opc1 opc2 sem))
6353 )
6354)
6355
6356(define-pmacro (binary-arith-imm4-dst op opc16-1 opc16-2 opc32-1 opc32-2 sem)
6357 (begin
6358 (binary-arith-imm4-dst-mach 16 op opc16-1 opc16-2 sem)
6359 (binary-arith-imm4-dst-mach 32 op opc32-1 opc32-2 sem)
6360 )
6361)
6362
6363;-------------------------------------------------------------
6364;<arith>.size:G src,dst -- for m16c and m32c
6365;-------------------------------------------------------------
6366
6367(define-pmacro (binary-arith-src-dst-defn mach srcgroup dstgroup smode dmode wstr op suffix encoding sem)
6368 (dni (.sym op mach wstr - srcgroup - dstgroup)
6369 (.str op wstr " dst" mach "-" srcgroup "-" dstgroup "-" dmode)
6772dd07 6370 ((machine mach) RL_2ADDR)
49f58d10
JB		 6371 (.str op wstr "$" suffix " ${src" mach "-" srcgroup "-" smode "},${dst" mach "-" dstgroup "-" dmode "}")
6372 encoding
6373 (sem dmode (.sym src mach - srcgroup - smode) (.sym dst mach - dstgroup - dmode))
6374 ())
6375)
6376
6377; m16c variants
6378(define-pmacro (binary-arith16-src-dst-defn smode dmode wstr wbit op suffix opc1 opc2 sem)
6379 (begin
6380 (binary-arith-src-dst-defn 16 basic 16 smode dmode wstr op suffix
6381 (+ opc1 opc2 (f-7-1 wbit) (.sym src16-basic- smode) (.sym dst16-16- dmode))
6382 sem)
6383 (binary-arith-src-dst-defn 16 16-16 32 smode dmode wstr op suffix
6384 (+ opc1 opc2 (f-7-1 wbit) (.sym src16-16-16- smode) (.sym dst16-32- dmode))
6385 sem)
6386 (binary-arith-src-dst-defn 16 16-8 24 smode dmode wstr op suffix
6387 (+ opc1 opc2 (f-7-1 wbit) (.sym src16-16-8- smode) (.sym dst16-24- dmode))
6388 sem)
6389 )
6390)
6391
6392; m32c Prefixed variants
6393(define-pmacro (binary-arith32-src-dst-Prefixed smode dmode wstr wbit op suffix opc1 opc2 sem)
6394 (begin
6395 (binary-arith-src-dst-defn 32 basic-Prefixed 24-Prefixed smode dmode wstr op suffix
6396 (+ (f-0-4 0) (f-4-4 1) (f-8-1 opc1) (f-15-1 wbit) (.sym src32-basic-Prefixed- smode) (.sym dst32-24-Prefixed- dmode) (f-20-4 opc2))
6397 sem)
6398 (binary-arith-src-dst-defn 32 24-24-Prefixed 48-Prefixed smode dmode wstr op suffix
6399 (+ (f-0-4 0) (f-4-4 1) (f-8-1 opc1) (f-15-1 wbit) (.sym src32-24-24-Prefixed- smode) (.sym dst32-48-Prefixed- dmode) (f-20-4 opc2))
6400 sem)
6401 (binary-arith-src-dst-defn 32 24-16-Prefixed 40-Prefixed smode dmode wstr op suffix
6402 (+ (f-0-4 0) (f-4-4 1) (f-8-1 opc1) (f-15-1 wbit) (.sym src32-24-16-Prefixed- smode) (.sym dst32-40-Prefixed- dmode) (f-20-4 opc2))
6403 sem)
6404 (binary-arith-src-dst-defn 32 24-8-Prefixed 32-Prefixed smode dmode wstr op suffix
6405 (+ (f-0-4 0) (f-4-4 1) (f-8-1 opc1) (f-15-1 wbit) (.sym src32-24-8-Prefixed- smode) (.sym dst32-32-Prefixed- dmode) (f-20-4 opc2))
6406 sem)
6407 )
6408)
6409
6410; all m32c variants
6411(define-pmacro (binary-arith32-src-dst-defn smode dmode wstr wbit op suffix opc1 opc2 sem)
6412 (begin
6413 ; Multi insns are tried for assembly in the reverse order in which they appear here, so
6414 ; define the absolute-indirect insns first in order to prevent them from being selected
6415 ; when the mode is register-indirect
6416; (binary-arith-src-dst-defn 32 24-24-absolute-indirect 48-absolute-indirect smode dmode wstr op suffix
6417; (+ (f-0-4 4) (f-4-4 9) (f-8-1 opc1) (f-15-1 wbit)
6418; (.sym src32-24-24-absolute-indirect- smode) (.sym dst32-48-absolute-indirect- dmode) (f-20-4 opc2))
6419; sem)
6420; (binary-arith-src-dst-defn 32 24-16-absolute-indirect 40-absolute-indirect smode dmode wstr op suffix
6421; (+ (f-0-4 4) (f-4-4 9) (f-8-1 opc1) (f-15-1 wbit)
6422; (.sym src32-24-16-absolute-indirect- smode) (.sym dst32-40-absolute-indirect- dmode) (f-20-4 opc2))
6423; sem)
6424; (binary-arith-src-dst-defn 32 24-24-absolute-indirect 48-Prefixed smode dmode wstr op suffix
6425; (+ (f-0-4 4) (f-4-4 1) (f-8-1 opc1) (f-15-1 wbit)
6426; (.sym src32-24-24-absolute-indirect- smode) (.sym dst32-48-Prefixed- dmode) (f-20-4 opc2))
6427; sem)
6428; (binary-arith-src-dst-defn 32 24-16-absolute-indirect 40-Prefixed smode dmode wstr op suffix
6429; (+ (f-0-4 4) (f-4-4 1) (f-8-1 opc1) (f-15-1 wbit)
6430; (.sym src32-24-16-absolute-indirect- smode) (.sym dst32-40-Prefixed- dmode) (f-20-4 opc2))
6431; sem)
6432; (binary-arith-src-dst-defn 32 24-24-absolute-indirect 48-indirect smode dmode wstr op suffix
6433; (+ (f-0-4 4) (f-4-4 9) (f-8-1 opc1) (f-15-1 wbit)
6434; (.sym src32-24-24-absolute-indirect- smode) (.sym dst32-48-indirect- dmode) (f-20-4 opc2))
6435; sem)
6436; (binary-arith-src-dst-defn 32 24-16-absolute-indirect 40-indirect smode dmode wstr op suffix
6437; (+ (f-0-4 4) (f-4-4 9) (f-8-1 opc1) (f-15-1 wbit)
6438; (.sym src32-24-16-absolute-indirect- smode) (.sym dst32-40-indirect- dmode) (f-20-4 opc2))
6439; sem)
6440; (binary-arith-src-dst-defn 32 basic-Prefixed 24-absolute-indirect smode dmode wstr op suffix
6441; (+ (f-0-4 0) (f-4-4 9) (f-8-1 opc1) (f-15-1 wbit)
6442; (.sym src32-basic-Prefixed- smode) (.sym dst32-24-absolute-indirect- dmode) (f-20-4 opc2))
6443; sem)
6444; (binary-arith-src-dst-defn 32 24-24-Prefixed 48-absolute-indirect smode dmode wstr op suffix
6445; (+ (f-0-4 0) (f-4-4 9) (f-8-1 opc1) (f-15-1 wbit)
6446; (.sym src32-24-24-Prefixed- smode) (.sym dst32-48-absolute-indirect- dmode) (f-20-4 opc2))
6447; sem)
6448; (binary-arith-src-dst-defn 32 24-16-Prefixed 40-absolute-indirect smode dmode wstr op suffix
6449; (+ (f-0-4 0) (f-4-4 9) (f-8-1 opc1) (f-15-1 wbit)
6450; (.sym src32-24-16-Prefixed- smode) (.sym dst32-40-absolute-indirect- dmode) (f-20-4 opc2))
6451; sem)
6452; (binary-arith-src-dst-defn 32 24-8-Prefixed 32-absolute-indirect smode dmode wstr op suffix
6453; (+ (f-0-4 0) (f-4-4 9) (f-8-1 opc1) (f-15-1 wbit)
6454; (.sym src32-24-8-Prefixed- smode) (.sym dst32-32-absolute-indirect- dmode) (f-20-4 opc2))
6455; sem)
6456; (binary-arith-src-dst-defn 32 basic-indirect 24-absolute-indirect smode dmode wstr op suffix
6457; (+ (f-0-4 4) (f-4-4 9) (f-8-1 opc1) (f-15-1 wbit)
6458; (.sym src32-basic-indirect- smode) (.sym dst32-24-absolute-indirect- dmode) (f-20-4 opc2))
6459; sem)
6460; (binary-arith-src-dst-defn 32 24-24-indirect 48-absolute-indirect smode dmode wstr op suffix
6461; (+ (f-0-4 4) (f-4-4 9) (f-8-1 opc1) (f-15-1 wbit)
6462; (.sym src32-24-24-indirect- smode) (.sym dst32-48-absolute-indirect- dmode) (f-20-4 opc2))
6463; sem)
6464; (binary-arith-src-dst-defn 32 24-16-indirect 40-absolute-indirect smode dmode wstr op suffix
6465; (+ (f-0-4 4) (f-4-4 9) (f-8-1 opc1) (f-15-1 wbit)
6466; (.sym src32-24-16-indirect- smode) (.sym dst32-40-absolute-indirect- dmode) (f-20-4 opc2))
6467; sem)
6468; (binary-arith-src-dst-defn 32 24-8-indirect 32-absolute-indirect smode dmode wstr op suffix
6469; (+ (f-0-4 4) (f-4-4 9) (f-8-1 opc1) (f-15-1 wbit)
6470; (.sym src32-24-8-indirect- smode) (.sym dst32-32-absolute-indirect- dmode) (f-20-4 opc2))
6471; sem)
6472 (binary-arith-src-dst-defn 32 basic-Unprefixed 16-Unprefixed smode dmode wstr op suffix
6473 (+ (f-0-1 opc1) (f-7-1 wbit) (.sym src32-basic-Unprefixed- smode) (.sym dst32-16-Unprefixed- dmode) (f-12-4 opc2))
6474 sem)
6475 (binary-arith-src-dst-defn 32 16-24-Unprefixed 40-Unprefixed smode dmode wstr op suffix
6476 (+ (f-0-1 opc1) (f-7-1 wbit) (.sym src32-16-24-Unprefixed- smode) (.sym dst32-40-Unprefixed- dmode) (f-12-4 opc2))
6477 sem)
6478 (binary-arith-src-dst-defn 32 16-16-Unprefixed 32-Unprefixed smode dmode wstr op suffix
6479 (+ (f-0-1 opc1) (f-7-1 wbit) (.sym src32-16-16-Unprefixed- smode) (.sym dst32-32-Unprefixed- dmode) (f-12-4 opc2))
6480 sem)
6481 (binary-arith-src-dst-defn 32 16-8-Unprefixed 24-Unprefixed smode dmode wstr op suffix
6482 (+ (f-0-1 opc1) (f-7-1 wbit) (.sym src32-16-8-Unprefixed- smode) (.sym dst32-24-Unprefixed- dmode) (f-12-4 opc2))
6483 sem)
6484; (binary-arith-src-dst-defn 32 basic-indirect 24-Prefixed smode dmode wstr op suffix
6485; (+ (f-0-4 4) (f-4-4 1) (f-8-1 opc1) (f-15-1 wbit)
6486; (.sym src32-basic-indirect- smode) (.sym dst32-24-Prefixed- dmode) (f-20-4 opc2))
6487; sem)
6488; (binary-arith-src-dst-defn 32 24-24-indirect 48-Prefixed smode dmode wstr op suffix
6489; (+ (f-0-4 4) (f-4-4 1) (f-8-1 opc1) (f-15-1 wbit)
6490; (.sym src32-24-24-indirect- smode) (.sym dst32-48-Prefixed- dmode) (f-20-4 opc2))
6491; sem)
6492; (binary-arith-src-dst-defn 32 24-16-indirect 40-Prefixed smode dmode wstr op suffix
6493; (+ (f-0-4 4) (f-4-4 1) (f-8-1 opc1) (f-15-1 wbit)
6494; (.sym src32-24-16-indirect- smode) (.sym dst32-40-Prefixed- dmode) (f-20-4 opc2))
6495; sem)
6496; (binary-arith-src-dst-defn 32 24-8-indirect 32-Prefixed smode dmode wstr op suffix
6497; (+ (f-0-4 4) (f-4-4 1) (f-8-1 opc1) (f-15-1 wbit)
6498; (.sym src32-24-8-indirect- smode) (.sym dst32-32-Prefixed- dmode) (f-20-4 opc2))
6499; sem)
6500; (binary-arith-src-dst-defn 32 basic-Prefixed 24-indirect smode dmode wstr op suffix
6501; (+ (f-0-4 0) (f-4-4 9) (f-8-1 opc1) (f-15-1 wbit)
6502; (.sym src32-basic-Prefixed- smode) (.sym dst32-24-indirect- dmode) (f-20-4 opc2))
6503; sem)
6504; (binary-arith-src-dst-defn 32 24-24-Prefixed 48-indirect smode dmode wstr op suffix
6505; (+ (f-0-4 0) (f-4-4 9) (f-8-1 opc1) (f-15-1 wbit)
6506; (.sym src32-24-24-Prefixed- smode) (.sym dst32-48-indirect- dmode) (f-20-4 opc2))
6507; sem)
6508; (binary-arith-src-dst-defn 32 24-16-Prefixed 40-indirect smode dmode wstr op suffix
6509; (+ (f-0-4 0) (f-4-4 9) (f-8-1 opc1) (f-15-1 wbit)
6510; (.sym src32-24-16-Prefixed- smode) (.sym dst32-40-indirect- dmode) (f-20-4 opc2))
6511; sem)
6512; (binary-arith-src-dst-defn 32 24-8-Prefixed 32-indirect smode dmode wstr op suffix
6513; (+ (f-0-4 0) (f-4-4 9) (f-8-1 opc1) (f-15-1 wbit)
6514; (.sym src32-24-8-Prefixed- smode) (.sym dst32-32-indirect- dmode) (f-20-4 opc2))
6515; sem)
6516; (binary-arith-src-dst-defn 32 basic-indirect 24-indirect smode dmode wstr op suffix
6517; (+ (f-0-4 4) (f-4-4 9) (f-8-1 opc1) (f-15-1 wbit)
6518; (.sym src32-basic-indirect- smode) (.sym dst32-24-indirect- dmode) (f-20-4 opc2))
6519; sem)
6520; (binary-arith-src-dst-defn 32 24-24-indirect 48-indirect smode dmode wstr op suffix
6521; (+ (f-0-4 4) (f-4-4 9) (f-8-1 opc1) (f-15-1 wbit)
6522; (.sym src32-24-24-indirect- smode) (.sym dst32-48-indirect- dmode) (f-20-4 opc2))
6523; sem)
6524; (binary-arith-src-dst-defn 32 24-16-indirect 40-indirect smode dmode wstr op suffix
6525; (+ (f-0-4 4) (f-4-4 9) (f-8-1 opc1) (f-15-1 wbit)
6526; (.sym src32-24-16-indirect- smode) (.sym dst32-40-indirect- dmode) (f-20-4 opc2))
6527; sem)
6528; (binary-arith-src-dst-defn 32 24-8-indirect 32-indirect smode dmode wstr op suffix
6529; (+ (f-0-4 4) (f-4-4 9) (f-8-1 opc1) (f-15-1 wbit)
6530; (.sym src32-24-8-indirect- smode) (.sym dst32-32-indirect- dmode) (f-20-4 opc2))
6531; sem)
6532 )
6533)
6534
6535(define-pmacro (binary-arith-src-dst-mach mach op suffix opc1 opc2 sem)
6536 (begin
6537 (.apply (.sym binary-arith mach -src-dst-defn) (QI QI .b 0 op suffix opc1 opc2 sem))
6538 (.apply (.sym binary-arith mach -src-dst-defn) (HI HI .w 1 op suffix opc1 opc2 sem))
6539 )
6540)
6541
6542(define-pmacro (binary-arith-src-dst op suffix opc16-1 opc16-2 opc32-1 opc32-2 sem)
6543 (begin
6544 (binary-arith-src-dst-mach 16 op suffix opc16-1 opc16-2 sem)
6545 (binary-arith-src-dst-mach 32 op suffix opc32-1 opc32-2 sem)
6546 )
6547)
6548
6549;-------------------------------------------------------------
6550;<arith>.size:S #imm,dst -- for m32c
6551;-------------------------------------------------------------
6552
6553(define-pmacro (binary-arith32-s-imm-dst-defn src dstgroup mode wstr op encoding sem)
6554 (dni (.sym op 32 wstr - imm-S - dstgroup)
6555 (.str op wstr " 32-imm-S-" dstgroup "-" mode)
6556 ((machine 32))
6557 (.str op wstr "$S #${" src "},${dst32-" dstgroup "-" mode "}")
6558 encoding
6559 (sem mode src (.sym dst32- dstgroup - mode))
6560 ())
6561)
6562
6563(define-pmacro (binary-arith32-z-imm-dst-defn src dstgroup mode wstr op encoding sem)
6564 (dni (.sym op 32 wstr - imm-Z - dstgroup)
6565 (.str op wstr " 32-imm-Z-" dstgroup "-" mode)
6566 ((machine 32))
6567 (.str op wstr "$Z #0,${dst32-" dstgroup "-" mode "}")
6568 encoding
6569 (sem mode (const 0) (.sym dst32- dstgroup - mode))
6570 ())
6571)
6572
6573(define-pmacro (binary-arith32-s-imm-dst mode wstr wbit op opc1 opc2 sem)
6574 (begin
6575; (binary-arith32-s-imm-dst-defn (.sym Imm-32- mode) 2-S-absolute-indirect mode wstr op
6576; (+ (f-0-4 0) (f-4-4 9) (f-8-2 opc1) (.sym dst32-2-S-absolute-indirect- mode) (f-12-3 opc2) (f-15-1 wbit) (.sym Imm-32- mode))
6577; sem)
6578 (binary-arith32-s-imm-dst-defn (.sym Imm-8- mode) 2-S-basic mode wstr op
6579 (+ (f-0-2 opc1) (.sym dst32-2-S-basic- mode) (f-4-3 opc2) (f-7-1 wbit) (.sym Imm-8- mode))
6580 sem)
6581 (binary-arith32-s-imm-dst-defn (.sym Imm-24- mode) 2-S-16 mode wstr op
6582 (+ (f-0-2 opc1) (.sym dst32-2-S-16- mode) (f-4-3 opc2) (f-7-1 wbit) (.sym Imm-24- mode))
6583 sem)
6584 (binary-arith32-s-imm-dst-defn (.sym Imm-16- mode) 2-S-8 mode wstr op
6585 (+ (f-0-2 opc1) (.sym dst32-2-S-8- mode) (f-4-3 opc2) (f-7-1 wbit) (.sym Imm-16- mode))
6586 sem)
6587; (binary-arith32-s-imm-dst-defn (.sym Imm-24- mode) 2-S-8-indirect mode wstr op
6588; (+ (f-0-4 0) (f-4-4 9) (f-8-2 opc1) (.sym dst32-2-S-8-indirect- mode) (f-12-3 opc2) (f-15-1 wbit) (.sym Imm-24- mode))
6589; sem)
6590 )
6591)
6592
6593(define-pmacro (binary-arith32-z-imm-dst mode wstr wbit op opc1 opc2 sem)
6594 (begin
6595; (binary-arith32-z-imm-dst-defn (.sym Imm-32- mode) 2-S-absolute-indirect mode wstr op
6596; (+ (f-0-4 0) (f-4-4 9) (f-8-2 opc1) (.sym dst32-2-S-absolute-indirect- mode) (f-12-3 opc2) (f-15-1 wbit) (.sym Imm-32- mode))
6597; sem)
6598 (binary-arith32-z-imm-dst-defn (.sym Imm-8- mode) 2-S-basic mode wstr op
6599 (+ (f-0-2 opc1) (.sym dst32-2-S-basic- mode) (f-4-3 opc2) (f-7-1 wbit))
6600 sem)
6601 (binary-arith32-z-imm-dst-defn (.sym Imm-24- mode) 2-S-16 mode wstr op
6602 (+ (f-0-2 opc1) (.sym dst32-2-S-16- mode) (f-4-3 opc2) (f-7-1 wbit))
6603 sem)
6604 (binary-arith32-z-imm-dst-defn (.sym Imm-16- mode) 2-S-8 mode wstr op
6605 (+ (f-0-2 opc1) (.sym dst32-2-S-8- mode) (f-4-3 opc2) (f-7-1 wbit))
6606 sem)
6607; (binary-arith32-z-imm-dst-defn (.sym Imm-24- mode) 2-S-8-indirect mode wstr op
6608; (+ (f-0-4 0) (f-4-4 9) (f-8-2 opc1) (.sym dst32-2-S-8-indirect- mode) (f-12-3 opc2) (f-15-1 wbit) (.sym Imm-24- mode))
6609; sem)
6610 )
6611)
6612
6613;-------------------------------------------------------------
6614;<arith>.L:S #imm1,An -- for m32c
6615;-------------------------------------------------------------
6616
6617(define-pmacro (binary-arith32-l-s-imm1-an op opc1 opc2 sem)
6618 (begin
6619 (dni (.sym op 32.l-s-imm1-S-an)
6620 (.str op ".l 32-imm1-S-an")
6621 ((machine 32))
6622 (.str op ".l$S #${Imm1-S},${dst32-an-S}")
6623 (+ opc1 Imm1-S opc2 dst32-an-S)
6624 (sem SI Imm1-S dst32-an-S)
6625 ())
6626 )
6627)
6628
6629;-------------------------------------------------------------
6630;<arith>.L:Q #imm3,sp -- for m32c
6631;-------------------------------------------------------------
6632
6633(define-pmacro (binary-arith32-l-q-imm3-sp op opc1 opc2 sem)
6634 (begin
6635 (dni (.sym op 32.l-imm3-Q)
6636 (.str op ".l 32-imm3-Q")
6637 ((machine 32))
6638 (.str op ".l$Q #${Imm3-S},sp")
6639 (+ opc1 Imm3-S opc2)
6640 (sem SI Imm3-S sp)
6641 ())
6642 )
6643)
6644
6645;-------------------------------------------------------------
6646;<arith>.L:S #imm8,sp -- for m32c
6647;-------------------------------------------------------------
6648
6649(define-pmacro (binary-arith32-l-s-imm8-sp op opc1 opc2 opc3 opc4 sem)
6650 (begin
6651 (dni (.sym op 32.l-imm8-S)
6652 (.str op ".l 32-imm8-S")
6653 ((machine 32))
6654 (.str op ".l$S #${Imm-16-QI},sp")
6655 (+ opc1 opc2 opc3 opc4 Imm-16-QI)
6656 (sem SI Imm-16-QI sp)
6657 ())
6658 )
6659)
6660
6661;-------------------------------------------------------------
6662;<arith>.L:G #imm16,sp -- for m32c
6663;-------------------------------------------------------------
6664
6665(define-pmacro (binary-arith32-l-g-imm16-sp op opc1 opc2 opc3 opc4 sem)
6666 (begin
6667 (dni (.sym op 32.l-imm16-G)
6668 (.str op ".l 32-imm16-G")
6669 ((machine 32))
6670 (.str op ".l$G #${Imm-16-HI},sp")
6671 (+ opc1 opc2 opc3 opc4 Imm-16-HI)
6672 (sem SI Imm-16-HI sp)
6673 ())
6674 )
6675)
6676
6677;-------------------------------------------------------------
6678;<arith>jnz.size #imm4,dst,label -- for m16c and m32c
6679;-------------------------------------------------------------
6680
6681(define-pmacro (arith-jnz-imm4-dst-defn mach src dstgroup label mode wstr op encoding sem)
6682 (dni (.sym op mach wstr - imm4 - dstgroup)
6683 (.str op wstr " " mach "-imm4-" dstgroup "-" label "-" mode)
144f4bc6 6684 (RL_JUMP RELAXABLE (machine mach))
49f58d10
JB		 6685 (.str op wstr " #${" src "},${dst" mach "-" dstgroup "-" mode "},${" label "}")
6686 encoding
6687 (sem mode src (.sym dst mach - dstgroup - mode) label)
6688 ())
6689)
6690
6691; m16c variants
c6552317 6692(define-pmacro (arith-jnz16-imm4-dst-defn mode wstr wbit op i4n opc1 opc2 sem)
49f58d10 6693 (begin
c6552317
DD		 6694 (arith-jnz-imm4-dst-defn 16 (.sym Imm-8- i4n) basic Lab-16-8 mode wstr op
6695 (+ opc1 opc2 (f-7-1 wbit) (.sym Imm-8- i4n) (.sym dst16-basic- mode) Lab-16-8)
49f58d10 6696 sem)
c6552317 6697 (arith-jnz-imm4-dst-defn 16 (.sym Imm-8- i4n) 16-16 Lab-32-8 mode wstr op
144f4bc6 6698 (+ opc1 opc2 (f-7-1 wbit) (.sym Imm-8- i4n) (.sym dst16-16-16- mode) Lab-32-8)
49f58d10 6699 sem)
c6552317 6700 (arith-jnz-imm4-dst-defn 16 (.sym Imm-8- i4n) 16-8 Lab-24-8 mode wstr op
144f4bc6 6701 (+ opc1 opc2 (f-7-1 wbit) (.sym Imm-8- i4n) (.sym dst16-16-8- mode) Lab-24-8)
49f58d10
JB		 6702 sem)
6703 )
6704)
6705
6706; m32c variants
c6552317 6707(define-pmacro (arith-jnz32-imm4-dst-defn mode wstr wbit op i4n opc1 opc2 sem)
49f58d10 6708 (begin
c6552317
DD		 6709 (arith-jnz-imm4-dst-defn 32 (.sym Imm-12- i4n) basic-Unprefixed Lab-16-8 mode wstr op
6710 (+ (f-0-4 opc1) (f-7-1 wbit) (.sym dst32-basic-Unprefixed- mode) (f-10-2 opc2) (.sym Imm-12- i4n) Lab-16-8)
49f58d10 6711 sem)
c6552317
DD		 6712 (arith-jnz-imm4-dst-defn 32 (.sym Imm-12- i4n) 16-24-Unprefixed Lab-40-8 mode wstr op
6713 (+ (f-0-4 opc1) (f-7-1 wbit) (.sym dst32-16-24-Unprefixed- mode) (f-10-2 opc2) (.sym Imm-12- i4n) Lab-40-8)
49f58d10 6714 sem)
c6552317
DD		 6715 (arith-jnz-imm4-dst-defn 32 (.sym Imm-12- i4n) 16-16-Unprefixed Lab-32-8 mode wstr op
6716 (+ (f-0-4 opc1) (f-7-1 wbit) (.sym dst32-16-16-Unprefixed- mode) (f-10-2 opc2) (.sym Imm-12- i4n) Lab-32-8)
49f58d10 6717 sem)
c6552317
DD		 6718 (arith-jnz-imm4-dst-defn 32 (.sym Imm-12- i4n) 16-8-Unprefixed Lab-24-8 mode wstr op
6719 (+ (f-0-4 opc1) (f-7-1 wbit) (.sym dst32-16-8-Unprefixed- mode) (f-10-2 opc2) (.sym Imm-12- i4n) Lab-24-8)
49f58d10
JB		 6720 sem)
6721 )
6722)
6723
c6552317 6724(define-pmacro (arith-jnz-imm4-dst-mach mach op i4n opc1 opc2 sem)
49f58d10 6725 (begin
c6552317
DD		 6726 (.apply (.sym arith-jnz mach -imm4-dst-defn) (QI .b 0 op i4n opc1 opc2 sem))
6727 (.apply (.sym arith-jnz mach -imm4-dst-defn) (HI .w 1 op i4n opc1 opc2 sem))
49f58d10
JB		 6728 )
6729)
6730
c6552317 6731(define-pmacro (arith-jnz-imm4-dst op i4n opc16-1 opc16-2 opc32-1 opc32-2 sem)
49f58d10 6732 (begin
c6552317
DD		 6733 (arith-jnz-imm4-dst-mach 16 op i4n opc16-1 opc16-2 sem)
6734 (arith-jnz-imm4-dst-mach 32 op i4n opc32-1 opc32-2 sem)
49f58d10
JB		 6735 )
6736)
6737
6738;-------------------------------------------------------------
6739;mov.size dsp8[sp],dst -- for m16c and m32c
6740;-------------------------------------------------------------
6741(define-pmacro (mov-dspsp-dst-defn mach dstgroup dsp mode wstr op encoding sem)
6742 (dni (.sym op mach wstr -dspsp-dst- dstgroup)
6743 (.str op wstr " " mach "-dsp[sp]-" dstgroup "-" dsp "-" mode)
6744 ((machine mach))
f75eb1c0 6745 (.str op wstr "$G ${" dsp "}[sp],${dst" mach "-" dstgroup "-" mode "}")
49f58d10
JB		 6746 encoding
6747 (sem mach mode dsp (.sym dst mach - dstgroup - mode))
6748 ())
6749)
6750(define-pmacro (mov-src-dspsp-defn mach dstgroup dsp mode wstr op encoding sem)
6751 (dni (.sym op mach wstr -dst-dspsp- dstgroup)
6752 (.str op wstr " " mach "-dsp[sp]-" dstgroup "-" dsp "-" mode)
6753 ((machine mach))
f75eb1c0 6754 (.str op wstr "$G ${dst" mach "-" dstgroup "-" mode "},${" dsp "}[sp]")
49f58d10
JB		 6755 encoding
6756 (sem mach mode (.sym dst mach - dstgroup - mode) dsp)
6757 ())
6758)
6759
6760; m16c variants
6761(define-pmacro (mov16-dspsp-dst-defn mode wstr wbit op opc1 opc2 opc3 sem)
6762 (begin
f75eb1c0
DD		 6763 (mov-dspsp-dst-defn 16 basic Dsp-16-s8 mode wstr op
6764 (+ opc1 opc2 (f-7-1 wbit) opc3 (.sym dst16-basic- mode) Dsp-16-s8)
49f58d10 6765 sem)
f75eb1c0
DD		 6766 (mov-dspsp-dst-defn 16 16-16 Dsp-32-s8 mode wstr op
6767 (+ opc1 opc2 (f-7-1 wbit) opc3 (.sym dst16-16-16- mode) Dsp-32-s8)
49f58d10 6768 sem)
f75eb1c0
DD		 6769 (mov-dspsp-dst-defn 16 16-8 Dsp-24-s8 mode wstr op
6770 (+ opc1 opc2 (f-7-1 wbit) opc3 (.sym dst16-16-8- mode) Dsp-24-s8)
49f58d10
JB		 6771 sem)
6772 )
6773)
6774
6775(define-pmacro (mov16-src-dspsp-defn mode wstr wbit op opc1 opc2 opc3 sem)
6776 (begin
f75eb1c0
DD		 6777 (mov-src-dspsp-defn 16 basic Dsp-16-s8 mode wstr op
6778 (+ opc1 opc2 (f-7-1 wbit) opc3 (.sym dst16-basic- mode) Dsp-16-s8)
49f58d10 6779 sem)
f75eb1c0
DD		 6780 (mov-src-dspsp-defn 16 16-16 Dsp-32-s8 mode wstr op
6781 (+ opc1 opc2 (f-7-1 wbit) opc3 (.sym dst16-16-16- mode) Dsp-32-s8)
49f58d10 6782 sem)
f75eb1c0
DD		 6783 (mov-src-dspsp-defn 16 16-8 Dsp-24-s8 mode wstr op
6784 (+ opc1 opc2 (f-7-1 wbit) opc3 (.sym dst16-16-8- mode) Dsp-24-s8)
49f58d10
JB		 6785 sem)
6786 )
6787)
6788
6789; m32c variants
6790(define-pmacro (mov32-dspsp-dst-defn mode wstr wbit op opc1 opc2 opc3 sem)
6791 (begin
f75eb1c0
DD		 6792 (mov-dspsp-dst-defn 32 basic-Unprefixed Dsp-16-s8 mode wstr op
6793 (+ (f-0-4 opc1) (f-7-1 wbit) (.sym dst32-basic-Unprefixed- mode) (f-10-2 opc2) (f-12-4 opc3) Dsp-16-s8)
49f58d10 6794 sem)
f75eb1c0
DD		 6795 (mov-dspsp-dst-defn 32 16-24-Unprefixed Dsp-40-s8 mode wstr op
6796 (+ (f-0-4 opc1) (f-7-1 wbit) (.sym dst32-16-24-Unprefixed- mode) (f-10-2 opc2) (f-12-4 opc3) Dsp-40-s8)
49f58d10 6797 sem)
f75eb1c0
DD		 6798 (mov-dspsp-dst-defn 32 16-16-Unprefixed Dsp-32-s8 mode wstr op
6799 (+ (f-0-4 opc1) (f-7-1 wbit) (.sym dst32-16-16-Unprefixed- mode) (f-10-2 opc2) (f-12-4 opc3) Dsp-32-s8)
49f58d10 6800 sem)
f75eb1c0
DD		 6801 (mov-dspsp-dst-defn 32 16-8-Unprefixed Dsp-24-s8 mode wstr op
6802 (+ (f-0-4 opc1) (f-7-1 wbit) (.sym dst32-16-8-Unprefixed- mode) (f-10-2 opc2) (f-12-4 opc3) Dsp-24-s8)
49f58d10
JB		 6803 sem)
6804 )
6805)
6806(define-pmacro (mov32-src-dspsp-defn mode wstr wbit op opc1 opc2 opc3 sem)
6807 (begin
f75eb1c0
DD		 6808 (mov-src-dspsp-defn 32 basic-Unprefixed Dsp-16-s8 mode wstr op
6809 (+ (f-0-4 opc1) (f-7-1 wbit) (.sym dst32-basic-Unprefixed- mode) (f-10-2 opc2) (f-12-4 opc3) Dsp-16-s8)
49f58d10 6810 sem)
f75eb1c0
DD		 6811 (mov-src-dspsp-defn 32 16-24-Unprefixed Dsp-40-s8 mode wstr op
6812 (+ (f-0-4 opc1) (f-7-1 wbit) (.sym dst32-16-24-Unprefixed- mode) (f-10-2 opc2) (f-12-4 opc3) Dsp-40-s8)
49f58d10 6813 sem)
f75eb1c0
DD		 6814 (mov-src-dspsp-defn 32 16-16-Unprefixed Dsp-32-s8 mode wstr op
6815 (+ (f-0-4 opc1) (f-7-1 wbit) (.sym dst32-16-16-Unprefixed- mode) (f-10-2 opc2) (f-12-4 opc3) Dsp-32-s8)
49f58d10 6816 sem)
f75eb1c0
DD		 6817 (mov-src-dspsp-defn 32 16-8-Unprefixed Dsp-24-s8 mode wstr op
6818 (+ (f-0-4 opc1) (f-7-1 wbit) (.sym dst32-16-8-Unprefixed- mode) (f-10-2 opc2) (f-12-4 opc3) Dsp-24-s8)
49f58d10
JB		 6819 sem)
6820 )
6821)
6822
6823(define-pmacro (mov-src-dspsp-mach mach op opc1 opc2 opc3 sem)
6824 (begin
6825 (.apply (.sym mov mach -src-dspsp-defn) (QI .b 0 op opc1 opc2 opc3 sem))
6826 (.apply (.sym mov mach -src-dspsp-defn) (HI .w 1 op opc1 opc2 opc3 sem))
6827 )
6828)
6829
6830(define-pmacro (mov-dspsp-dst-mach mach op opc1 opc2 opc3 sem)
6831 (begin
6832 (.apply (.sym mov mach -dspsp-dst-defn) (QI .b 0 op opc1 opc2 opc3 sem))
6833 (.apply (.sym mov mach -dspsp-dst-defn) (HI .w 1 op opc1 opc2 opc3 sem))
6834 )
6835)
6836
6837(define-pmacro (mov-dspsp-dst op opc16-1 opc16-2 opc16-3 opc32-1 opc32-2 opc32-3 sem)
6838 (begin
6839 (mov-dspsp-dst-mach 16 op opc16-1 opc16-2 opc16-3 sem)
6840 (mov-dspsp-dst-mach 32 op opc32-1 opc32-2 opc32-3 sem)
6841 )
6842)
6843(define-pmacro (mov-src-dspsp op opc16-1 opc16-2 opc16-3 opc32-1 opc32-2 opc32-3 sem)
6844 (begin
6845 (mov-src-dspsp-mach 16 op opc16-1 opc16-2 opc16-3 sem)
6846 (mov-src-dspsp-mach 32 op opc32-1 opc32-2 opc32-3 sem)
6847 )
6848)
6849
6850;-------------------------------------------------------------
6851; lde dsp24,dst -- for m16c
49f58d10
JB		 6852;-------------------------------------------------------------
6853
a1a280bb
DD		 6854(define-pmacro (lde-dst-dsp mode wstr wbit dstgroup srcdisp)
6855 (begin
6856
6857 (dni (.sym lde wstr - dstgroup -u20)
6858 (.str "lde" wstr "-" dstgroup "-u20")
6859 ((machine 16))
6860 (.str "lde" wstr " ${" srcdisp "},${dst16-" dstgroup "-" mode "}")
6861 (+ (f-0-4 #x7) (f-4-3 #x2) (f-7-1 wbit) (f-8-4 #x8)
6862 (.sym dst16- dstgroup - mode) srcdisp)
6863 (nop)
6864 ())
49f58d10 6865
a1a280bb
DD		 6866 (dni (.sym lde wstr - dstgroup -u20a0)
6867 (.str "lde" wstr "-" dstgroup "-u20a0")
6868 ((machine 16))
6869 (.str "lde" wstr " ${" srcdisp "}[a0],${dst16-" dstgroup "-" mode "}")
6870 (+ (f-0-4 #x7) (f-4-3 #x2) (f-7-1 wbit) (f-8-4 #x9)
6871 (.sym dst16- dstgroup - mode) srcdisp)
6872 (nop)
6873 ())
6874
6875 (dni (.sym lde wstr - dstgroup -a1a0)
6876 (.str "lde" wstr "-" dstgroup "-a1a0")
6877 ((machine 16))
6878 (.str "lde" wstr " [a1a0],${dst16-" dstgroup "-" mode "}")
6879 (+ (f-0-4 #x7) (f-4-3 #x2) (f-7-1 wbit) (f-8-4 #xa)
6880 (.sym dst16- dstgroup - mode))
6881 (nop)
6882 ())
6883 )
6884 )
6885
6886(define-pmacro (lde-dst mode wstr wbit)
49f58d10 6887 (begin
a1a280bb
DD		 6888 ; like: QI .b 0
6889 (lde-dst-dsp mode wstr wbit basic Dsp-16-u20)
6890 (lde-dst-dsp mode wstr wbit 16-8 Dsp-24-u20)
6891 (lde-dst-dsp mode wstr wbit 16-16 Dsp-32-u20)
49f58d10
JB		 6892 )
6893)
6894
6895;-------------------------------------------------------------
a1a280bb 6896; ste dst,dsp24 -- for m16c
49f58d10
JB		 6897;-------------------------------------------------------------
6898
a1a280bb
DD		 6899(define-pmacro (ste-dst-dsp mode wstr wbit dstgroup srcdisp)
6900 (begin
6901
6902 (dni (.sym ste wstr - dstgroup -u20)
6903 (.str "ste" wstr "-" dstgroup "-u20")
6904 ((machine 16))
6905 (.str "ste" wstr " ${dst16-" dstgroup "-" mode "},${" srcdisp "}")
6906 (+ (f-0-4 #x7) (f-4-3 #x2) (f-7-1 wbit) (f-8-4 #x0)
6907 (.sym dst16- dstgroup - mode) srcdisp)
6908 (nop)
6909 ())
6910
6911 (dni (.sym ste wstr - dstgroup -u20a0)
6912 (.str "ste" wstr "-" dstgroup "-u20a0")
6913 ((machine 16))
6914 (.str "ste" wstr " ${dst16-" dstgroup "-" mode "},${" srcdisp "}[a0]")
6915 (+ (f-0-4 #x7) (f-4-3 #x2) (f-7-1 wbit) (f-8-4 #x1)
6916 (.sym dst16- dstgroup - mode) srcdisp)
6917 (nop)
6918 ())
49f58d10 6919
a1a280bb
DD		 6920 (dni (.sym ste wstr - dstgroup -a1a0)
6921 (.str "ste" wstr "-" dstgroup "-a1a0")
6922 ((machine 16))
6923 (.str "ste" wstr " ${dst16-" dstgroup "-" mode "},[a1a0]")
6924 (+ (f-0-4 #x7) (f-4-3 #x2) (f-7-1 wbit) (f-8-4 #x2)
6925 (.sym dst16- dstgroup - mode))
6926 (nop)
6927 ())
6928 )
6929 )
6930
6931(define-pmacro (ste-dst mode wstr wbit)
49f58d10 6932 (begin
a1a280bb
DD		 6933 ; like: QI .b 0
6934 (ste-dst-dsp mode wstr wbit basic Dsp-16-u20)
6935 (ste-dst-dsp mode wstr wbit 16-8 Dsp-24-u20)
6936 (ste-dst-dsp mode wstr wbit 16-16 Dsp-32-u20)
49f58d10
JB		 6937 )
6938)
6939
6940;=============================================================
6941; Division
6942;-------------------------------------------------------------
6943
6944(define-pmacro (div-sem divop modop opmode reg src quot rem max min)
6945 (sequence ()
6946 (if (eq src 0)
6947 (set obit (const BI 1))
6948 (sequence ((opmode quot-result) (opmode rem-result))
6949 (set quot-result (divop opmode (ext opmode reg) src))
6950 (set rem-result (modop opmode (ext opmode reg) src))
6951 (set obit (orif (gt opmode quot-result max)
6952 (lt opmode quot-result min)))
6953 (set quot quot-result)
6954 (set rem rem-result))))
6955)
6956
6957;<divop>.size #imm -- for m16c and m32c
6958(define-pmacro (div-imm-defn mach wstr op src encoding divop modop opmode reg quot rem max min sem)
6959 (dni (.sym op mach wstr - src)
6960 (.str op mach wstr "-" src)
6961 ((machine mach))
6962 (.str op wstr " #${" src "}")
6963 encoding
6964 (sem divop modop opmode reg src quot rem max min)
6965 ())
6966)
6967(define-pmacro (div16-imm-defn smode wstr wbit op divop modop opmode reg quot rem max min opc1 opc2 opc3 opc4 sem)
6968 (div-imm-defn 16 wstr op (.sym Imm-16 - smode)
6969 (+ opc1 opc2 (f-7-1 wbit) opc3 opc4 (.sym Imm-16 - smode))
6970 divop modop opmode reg quot rem max min
6971 sem)
6972)
6973(define-pmacro (div32-imm-defn smode wstr wbit op divop modop opmode reg quot rem max min opc1 opc2 opc3 opc4 sem)
6974 (div-imm-defn 32 wstr op (.sym Imm-16 - smode)
6975 (+ (f-0-4 opc1) (f-4-4 opc2) (f-8-3 opc3) (f-11-1 wbit) (f-12-4 opc4) (.sym Imm-16 - smode))
6976 divop modop opmode reg quot rem max min
6977 sem)
6978)
6979(define-pmacro (div-imm-mach mach op divop modop opmode max-QI min-QI max-HI min-HI opc1 opc2 opc3 opc4 sem)
6980 (begin
6981 (.apply (.sym div mach -imm-defn) (QI .b 0 op divop modop opmode R0 R0l R0h max-QI min-QI opc1 opc2 opc3 opc4 sem))
6982 (.apply (.sym div mach -imm-defn) (HI .w 1 op divop modop opmode R2R0 R0 R2 max-HI min-HI opc1 opc2 opc3 opc4 sem))
6983 )
6984)
6985(define-pmacro (div-imm op divop modop opmode max-QI min-QI max-HI min-HI opc16-1 opc16-2 opc16-3 opc16-4 opc32-1 opc32-2 opc32-3 opc32-4 sem)
6986 (begin
6987 (div-imm-mach 16 op divop modop opmode max-QI min-QI max-HI min-HI opc16-1 opc16-2 opc16-3 opc16-4 sem)
6988 (div-imm-mach 32 op divop modop opmode max-QI min-QI max-HI min-HI opc32-1 opc32-2 opc32-3 opc32-4 sem)
6989 )
6990)
6991
6992;<divop>.size src -- for m16c and m32c
6993(define-pmacro (div-src-defn mach wstr op src encoding divop modop opmode reg quot rem max min sem)
6994 (dni (.sym op mach wstr - src)
6995 (.str op mach wstr "-" src)
6996 ((machine mach))
6997 (.str op wstr " ${" src "}")
6998 encoding
6999 (sem divop modop opmode reg src quot rem max min)
7000 ())
7001)
7002(define-pmacro (div16-src-defn smode wstr wbit op divop modop opmode reg quot rem max min opc1 opc2 opc3 sem)
7003 (div-src-defn 16 wstr op (.sym dst16-16 - smode)
7004 (+ opc1 opc2 (f-7-1 wbit) opc3 (.sym dst16-16 - smode))
7005 divop modop opmode reg quot rem max min
7006 sem)
7007)
7008(define-pmacro (div32-src-defn smode wstr wbit op divop modop opmode reg quot rem max min opc1 opc2 opc3 sem)
7009 (begin
7010 ; Multi insns are tried for assembly in the reverse order in which they appear here, so
7011 ; define the absolute-indirect insns first in order to prevent them from being selected
7012 ; when the mode is register-indirect
7013; (div-src-defn 32 wstr op (.sym dst32-24-absolute-indirect- smode)
7014; (+ (f-0-4 0) (f-4-4 9) (f-8-4 opc1) (f-15-1 wbit) (f-18-2 opc2) (f-20-4 opc3) (.sym dst32-24-absolute-indirect - smode))
7015; divop modop opmode reg quot rem max min
7016; sem)
7017 (div-src-defn 32 wstr op (.sym dst32-16-Unprefixed- smode)
7018 (+ (f-0-4 opc1) (f-7-1 wbit) (f-10-2 opc2) (f-12-4 opc3) (.sym dst32-16-Unprefixed- smode))
7019 divop modop opmode reg quot rem max min
7020 sem)
7021; (div-src-defn 32 wstr op (.sym dst32-24-indirect- smode)
7022; (+ (f-0-4 0) (f-4-4 9) (f-8-4 opc1) (f-15-1 wbit) (f-18-2 opc2) (f-20-4 opc3) (.sym dst32-24-indirect - smode))
7023; divop modop opmode reg quot rem max min
7024; sem)
7025 )
7026)
7027(define-pmacro (div-src-mach mach op divop modop opmode max-QI min-QI max-HI min-HI opc1 opc2 opc3 sem)
7028 (begin
7029 (.apply (.sym div mach -src-defn) (QI .b 0 op divop modop opmode R0 R0l R0h max-QI min-QI opc1 opc2 opc3 sem))
7030 (.apply (.sym div mach -src-defn) (HI .w 1 op divop modop opmode R2R0 R0 R2 max-HI min-HI opc1 opc2 opc3 sem))
7031 )
7032)
7033(define-pmacro (div-src op divop modop opmode max-QI min-QI max-HI min-HI opc16-1 opc16-2 opc16-3 opc32-1 opc32-2 opc32-3 sem)
7034 (begin
7035 (div-src-mach 16 op divop modop opmode max-QI min-QI max-HI min-HI opc16-1 opc16-2 opc16-3 sem)
7036 (div-src-mach 32 op divop modop opmode max-QI min-QI max-HI min-HI opc32-1 opc32-2 opc32-3 sem)
7037 )
7038)
7039
7040;=============================================================
7041; Bit manipulation
7042;
7043(define-pmacro (bit-insn-defn mach op suffix opnd encoding sem)
7044 (dni (.sym op mach - suffix - opnd)
7045 (.str op mach ":" suffix " " opnd)
7046 ((machine mach))
7047 (.str op "$" suffix " ${" opnd "}")
7048 encoding
7049 (sem opnd)
7050 ())
7051)
7052
7053(define-pmacro (bitsrc16-defn op opc1 opc2 opc3 sem)
7054 (bit-insn-defn 16 op X bit16-16
7055 (+ opc1 opc2 opc3 bit16-16)
7056 sem)
7057)
7058
7059(define-pmacro (bitsrc32-defn op opc1 opc2 opc3 sem)
7060 (begin
7061 (bit-insn-defn 32 op X bit32-24-Prefixed
7062 (+ (f-0-4 0) (f-4-4 1) (f-8-4 opc1) bit32-24-Prefixed (f-15-1 opc2) (f-18-3 opc3))
7063 sem)
7064 )
7065)
7066
7067(define-pmacro (bitsrc-insn op opc16-1 opc16-2 opc16-3 opc32-1 opc32-2 opc32-3 sem)
7068 (begin
7069 (bitsrc16-defn op opc16-1 opc16-2 opc16-3 sem)
7070 (bitsrc32-defn op opc32-1 opc32-2 opc32-3 sem)
7071 )
7072)
7073
7074(define-pmacro (bitdst16-defn op opc1 opc2 opc3 opc4 opc5 opc6 sem)
7075 (begin
7076 (bit-insn-defn 16 op G bit16-16-basic (+ opc1 opc2 opc3 bit16-16-basic) sem)
7077 (bit-insn-defn 16 op G bit16-16-16 (+ opc1 opc2 opc3 bit16-16-16) sem)
7078 (bit-insn-defn 16 op S bit16-11-S (+ opc4 opc5 opc6 bit16-11-S) sem)
7079 (bit-insn-defn 16 op G bit16-16-8 (+ opc1 opc2 opc3 bit16-16-8) sem)
7080 )
7081)
7082
7083(define-pmacro (bitdst32-defn op opc1 opc2 opc3 sem)
7084 (begin
7085 (bit-insn-defn 32 op X bit32-16-Unprefixed
7086 (+ (f-0-4 opc1) bit32-16-Unprefixed (f-7-1 opc2) (f-10-3 opc3))
7087 sem)
7088 )
7089)
7090
7091(define-pmacro (bitdstnos-insn op opc16-1 opc16-2 opc16-3 opc32-1 opc32-2 opc32-3 sem)
7092 (begin
7093 (bitsrc16-defn op opc16-1 opc16-2 opc16-3 sem)
7094 (bitdst32-defn op opc32-1 opc32-2 opc32-3 sem)
7095 )
7096)
7097
7098(define-pmacro (bitdst-insn op opc16-1 opc16-2 opc16-3 opc16-4 opc16-5 opc16-6 opc32-1 opc32-2 opc32-3 sem)
7099 (begin
7100 (bitdst16-defn op opc16-1 opc16-2 opc16-3 opc16-4 opc16-5 opc16-6 sem)
7101 (bitdst32-defn op opc32-1 opc32-2 opc32-3 sem)
7102 )
7103)
7104
7105;=============================================================
7106; Bit condition
7107;
7108(define-pmacro (bitcond-insn-defn mach op bit-opnd cond-opnd encoding sem)
7109 (dni (.sym op mach - bit-opnd - cond-opnd)
7110 (.str op mach " " bit-opnd " " cond-opnd)
7111 ((machine mach))
7112 (.str op "${" cond-opnd "} ${" bit-opnd "}")
7113 encoding
7114 (sem mach bit-opnd cond-opnd)
7115 ())
7116)
7117
7118(define-pmacro (bitcond16-defn op opc1 opc2 opc3 sem)
7119 (begin
7120 (bitcond-insn-defn 16 op bit16-16-basic cond16-16 (+ opc1 opc2 opc3 bit16-16-basic cond16-16) sem)
7121 (bitcond-insn-defn 16 op bit16-16-16 cond16-32 (+ opc1 opc2 opc3 bit16-16-16 cond16-32) sem)
7122 (bitcond-insn-defn 16 op bit16-16-8 cond16-24 (+ opc1 opc2 opc3 bit16-16-8 cond16-24) sem)
7123 )
7124)
7125
7126(define-pmacro (bitcond32-defn op opc1 opc2 opc3 sem)
7127 (begin
7128 (bitcond-insn-defn 32 op bit32-16-24-Unprefixed cond32-40
7129 (+ (f-0-4 opc1) bit32-16-24-Unprefixed (f-7-1 opc2) (f-10-3 opc3) cond32-40)
7130 sem)
7131 (bitcond-insn-defn 32 op bit32-16-16-Unprefixed cond32-32
7132 (+ (f-0-4 opc1) bit32-16-16-Unprefixed (f-7-1 opc2) (f-10-3 opc3) cond32-32)
7133 sem)
7134 (bitcond-insn-defn 32 op bit32-16-8-Unprefixed cond32-24
7135 (+ (f-0-4 opc1) bit32-16-8-Unprefixed (f-7-1 opc2) (f-10-3 opc3) cond32-24)
7136 sem)
7137 (bitcond-insn-defn 32 op bit32-basic-Unprefixed cond32-16
7138 (+ (f-0-4 opc1) bit32-basic-Unprefixed (f-7-1 opc2) (f-10-3 opc3) cond32-16)
7139 sem)
7140 )
7141)
7142
7143(define-pmacro (bitcond-insn op opc16-1 opc16-2 opc16-3 opc32-1 opc32-2 opc32-3 sem)
7144 (begin
7145 (bitcond16-defn op opc16-1 opc16-2 opc16-3 sem)
7146 (bitcond32-defn op opc32-1 opc32-2 opc32-3 sem)
7147 )
7148)
7149
7150;=============================================================
7151;<insn>.size #imm1,#imm2,dst -- for m32c
7152;
7153(define-pmacro (insn-imm1-imm2-dst-defn src1 src2 dstgroup xmode wstr op encoding sem)
7154 (dni (.sym op 32 wstr - src1 - src2 - dstgroup)
7155 (.str op 32 wstr "-" src1 "-" src2 "-" dstgroup "-" xmode)
7156 ((machine 32))
7157 (.str op wstr " #${" src1 "},#${" src2 "},${dst32-" dstgroup "-" xmode "}")
7158 encoding
7159 (sem xmode src1 src2 (.sym dst32- dstgroup - xmode))
7160 ())
7161)
7162
7163; m32c Prefixed variants
7164(define-pmacro (insn32-imm1-imm2-dst-Prefixed-defn xmode wstr wbit base1 base2 base3 base4 op opc1 opc2 opc3 sem)
7165 (begin
7166 (insn-imm1-imm2-dst-defn (.sym Imm-48- xmode) (.sym Imm- base4 - xmode) 24-24-Prefixed xmode wstr op
7167 (+ (f-0-4 0) (f-4-4 1) (f-8-4 opc1) (f-18-2 opc2) (f-15-1 wbit) (f-20-4 opc3)
7168 (.sym dst32-24-24-Prefixed- xmode) (.sym Imm-48- xmode) (.sym Imm- base4 - xmode))
7169 sem)
7170 (insn-imm1-imm2-dst-defn (.sym Imm-40- xmode) (.sym Imm- base3 - xmode) 24-16-Prefixed xmode wstr op
7171 (+ (f-0-4 0) (f-4-4 1) (f-8-4 opc1) (f-18-2 opc2) (f-15-1 wbit) (f-20-4 opc3)
7172 (.sym dst32-24-16-Prefixed- xmode) (.sym Imm-40- xmode) (.sym Imm- base3 - xmode))
7173 sem)
7174 (insn-imm1-imm2-dst-defn (.sym Imm-32- xmode) (.sym Imm- base2 - xmode) 24-8-Prefixed xmode wstr op
7175 (+ (f-0-4 0) (f-4-4 1) (f-8-4 opc1) (f-18-2 opc2) (f-15-1 wbit) (f-20-4 opc3)
7176 (.sym dst32-24-8-Prefixed- xmode) (.sym Imm-32- xmode) (.sym Imm- base2 - xmode))
7177 sem)
7178 (insn-imm1-imm2-dst-defn (.sym Imm-24- xmode) (.sym Imm- base1 - xmode) basic-Prefixed xmode wstr op
7179 (+ (f-0-4 0) (f-4-4 1) (f-8-4 opc1) (f-18-2 opc2) (f-15-1 wbit) (f-20-4 opc3)
7180 (.sym dst32-basic-Prefixed- xmode) (.sym Imm-24- xmode) (.sym Imm- base1 - xmode))
7181 sem)
7182 )
7183)
7184
7185; m32c Unprefixed variants
7186(define-pmacro (insn32-imm1-imm2-dst-Unprefixed-defn xmode wstr wbit base1 base2 base3 base4 op opc1 opc2 opc3 sem)
7187 (begin
7188 (insn-imm1-imm2-dst-defn (.sym Imm-40- xmode) (.sym Imm- base4 - xmode) 16-24-Unprefixed xmode wstr op
7189 (+ (f-0-4 opc1) (f-10-2 opc2) (f-7-1 wbit) (f-12-4 opc3)
7190 (.sym dst32-16-24-Unprefixed- xmode) (.sym Imm-40- xmode) (.sym Imm- base4 - xmode))
7191 sem)
7192 (insn-imm1-imm2-dst-defn (.sym Imm-32- xmode) (.sym Imm- base3 - xmode) 16-16-Unprefixed xmode wstr op
7193 (+ (f-0-4 opc1) (f-10-2 opc2) (f-7-1 wbit) (f-12-4 opc3)
7194 (.sym dst32-16-16-Unprefixed- xmode) (.sym Imm-32- xmode) (.sym Imm- base3 - xmode))
7195 sem)
7196 (insn-imm1-imm2-dst-defn (.sym Imm-24- xmode) (.sym Imm- base2 - xmode) 16-8-Unprefixed xmode wstr op
7197 (+ (f-0-4 opc1) (f-10-2 opc2) (f-7-1 wbit) (f-12-4 opc3)
7198 (.sym dst32-16-8-Unprefixed- xmode) (.sym Imm-24- xmode) (.sym Imm- base2 - xmode))
7199 sem)
7200 (insn-imm1-imm2-dst-defn (.sym Imm-16- xmode) (.sym Imm- base1 - xmode) basic-Unprefixed xmode wstr op
7201 (+ (f-0-4 opc1) (f-10-2 opc2) (f-7-1 wbit) (f-12-4 opc3)
7202 (.sym dst32-basic-Unprefixed- xmode) (.sym Imm-16- xmode) (.sym Imm- base1 - xmode))
7203 sem)
7204 )
7205)
7206
7207(define-pmacro (insn-imm1-imm2-dst-Prefixed op opc32-1 opc32-2 opc32-3 sem)
7208 (begin
7209 (insn32-imm1-imm2-dst-Prefixed-defn QI .b 0 32 40 48 56 op opc32-1 opc32-2 opc32-3 sem)
7210 (insn32-imm1-imm2-dst-Prefixed-defn HI .w 1 40 48 56 64 op opc32-1 opc32-2 opc32-3 sem)
7211 )
7212)
7213(define-pmacro (insn-imm1-imm2-dst-Unprefixed op opc32-1 opc32-2 opc32-3 sem)
7214 (begin
7215 (insn32-imm1-imm2-dst-Unprefixed-defn QI .b 0 24 32 40 48 op opc32-1 opc32-2 opc32-3 sem)
7216 (insn32-imm1-imm2-dst-Unprefixed-defn HI .w 1 32 40 48 56 op opc32-1 opc32-2 opc32-3 sem)
7217 )
7218)
7219\f
7220;=============================================================
7221; Insn definitions
7222;-------------------------------------------------------------
7223; abs - absolute
7224;-------------------------------------------------------------
7225
7226(define-pmacro (abs-sem mode dst)
7227 (sequence ((mode result))
7228 (set result (abs mode dst))
7229 (set obit (eq result dst))
7230 (set-z-and-s result)
7231 (set dst result))
7232)
7233(unary-insn abs (f-0-4 7) (f-4-3 3) (f-8-4 #xF) #xA #x1 #xF abs-sem)
7234
7235;-------------------------------------------------------------
7236; adcf - addition carry flag
7237;-------------------------------------------------------------
7238
7239(define-pmacro (adcf-sem mode dst)
7240 (sequence ((mode result))
7241 (set result (addc mode dst 0 cbit))
7242 (set obit (add-oflag mode dst 0 cbit))
7243 (set cbit (add-cflag mode dst 0 cbit))
7244 (set-z-and-s result)
7245 (set dst result))
7246)
7247(unary-insn adcf (f-0-4 7) (f-4-3 3) (f-8-4 #xE) #xB #x1 #xE adcf-sem)
7248
7249;-------------------------------------------------------------
7250; add - binary addition
7251;-------------------------------------------------------------
7252
7253(define-pmacro (add-sem mode src1 dst)
7254 (sequence ((mode result))
7255 (set result (add mode src1 dst))
7256 (set obit (add-oflag mode src1 dst 0))
7257 (set cbit (add-cflag mode src1 dst 0))
7258 (set-z-and-s result)
7259 (set dst result))
7260)
7261
7262; add.L:G #imm32,dst (m32 #2)
7263(binary-arith32-imm-dst-defn SI SI .l 0 add G #x8 #x3 #x1 add-sem)
7264; add.size:G #imm,dst (m16 #1 m32 #1)
7265(binary-arith-imm-dst add G (f-0-4 7) (f-4-3 3) (f-8-4 4) #x8 #x2 #xE add-sem)
7266; add.size:Q #imm4,dst (m16 #2 m32 #3)
7267(binary-arith-imm4-dst add (f-0-4 #xC) (f-4-3 4) #x7 #x3 add-sem)
7268(binary-arith32-imm4-dst-defn SI .l 1 0 add #x7 #x3 add-sem)
7269; add.b:S #imm8,dst3 (m16 #3)
7270(binary-arith16-b-S-imm8-dst3 add ".b" (f-0-4 8) (f-4-1 0) add-sem)
7271; add.BW:Q #imm4,sp (m16 #7)
7272(binary-arith16-Q-sp add (f-0-4 7) (f-4-4 #xD) (f-8-4 #xB) add-sem)
92e0a941
DD		 7273(dnmi add16-bQ-sp "add16-bQ-sp" ()
7274 "add.b:q #${Imm-12-s4},sp"
7275 (emit add16-wQ-sp Imm-12-s4))
49f58d10
JB		 7276; add.BW:G #imm,sp (m16 #6)
7277(binary-arith16-G-sp add (f-0-4 7) (f-4-3 6) (f-8-4 #xE) (f-12-4 #xB) add-sem)
7278; add.BW:G src,dst (m16 #4 m32 #6)
7279(binary-arith-src-dst add G (f-0-4 #xA) (f-4-3 0) #x1 #x8 add-sem)
7280; add.B.S src2,r0l/r0h (m16 #5)
7281(binary-arith16-b-S-src2 add (f-0-4 2) (f-4-1 0) add-sem)
7282; add.L:G src,dst (m32 #7)
7283(binary-arith32-src-dst-defn SI SI .l 1 add G #x1 #x2 add-sem)
7284; add.L:S #imm{1,2},A0/A1 (m32 #5)
7285(binary-arith32-l-s-imm1-an add (f-0-2 2) (f-3-4 6) add-sem)
7286; add.L:Q #imm3,sp (m32 #9)
7287(binary-arith32-l-q-imm3-sp add (f-0-2 1) (f-4-3 1) add-sem)
7288; add.L:S #imm8,sp (m32 #10)
7289(binary-arith32-l-s-imm8-sp add (f-0-4 #xb) (f-4-4 6) (f-8-4 0) (f-12-4 3) add-sem)
7290; add.L:G #imm16,sp (m32 #8)
7291(binary-arith32-l-g-imm16-sp add (f-0-4 #xb) (f-4-4 6) (f-8-4 1) (f-12-4 3) add-sem)
7292; add.BW:S #imm,dst2 (m32 #4)
7293(binary-arith32-s-imm-dst QI .b 0 add #x0 #x3 add-sem)
7294(binary-arith32-s-imm-dst HI .w 1 add #x0 #x3 add-sem)
7295
7296;-------------------------------------------------------------
7297; adc - binary add with carry
7298;-------------------------------------------------------------
7299
7300(define-pmacro (addc-sem mode src dst)
7301 (sequence ((mode result))
7302 (set result (addc mode src dst cbit))
7303 (set obit (add-oflag mode src dst cbit))
7304 (set cbit (add-cflag mode src dst cbit))
7305 (set-z-and-s result)
7306 (set dst result))
7307)
7308
7309; adc.size:G #imm,dst
7310(binary-arith16-imm-dst-defn QI QI .b 0 adc X (f-0-4 7) (f-4-3 3) (f-8-4 6) addc-sem)
7311(binary-arith16-imm-dst-defn HI HI .w 1 adc X (f-0-4 7) (f-4-3 3) (f-8-4 6) addc-sem)
7312(binary-arith32-imm-dst-Prefixed QI QI .b 0 adc X #x8 #x2 #xE addc-sem)
7313(binary-arith32-imm-dst-Prefixed HI HI .w 1 adc X #x8 #x2 #xE addc-sem)
7314
7315; adc.BW:G src,dst
7316(binary-arith16-src-dst-defn QI QI .b 0 adc X (f-0-4 #xB) (f-4-3 0) addc-sem)
7317(binary-arith16-src-dst-defn HI HI .w 1 adc X (f-0-4 #xB) (f-4-3 0) addc-sem)
7318(binary-arith32-src-dst-Prefixed QI QI .b 0 adc X #x1 #x4 addc-sem)
7319(binary-arith32-src-dst-Prefixed HI HI .w 1 adc X #x1 #x4 addc-sem)
7320
7321;-------------------------------------------------------------
7322; dadc - decimal add with carry
7323; dadd - decimal addition
7324;-------------------------------------------------------------
7325
7326(define-pmacro (dadc-sem mode src dst)
7327 (sequence ((mode result))
7328 (set result (subc mode dst src (not cbit)))
7329 (set cbit (sub-cflag mode dst src (not cbit)))
7330 (set-z-and-s result)
7331 (set dst result))
7332)
7333
7334(define-pmacro (decimal-subtraction16-insn op opc1 opc2)
7335 (begin
7336 ; op.b #imm8,r0l
7337 (dni (.sym op 16.b-imm8)
7338 (.str op ".b #imm8")
7339 ((machine 16))
8d0e2679 7340 (.str op ".b #${Imm-16-QI},r0l")
49f58d10
JB		 7341 (+ (f-0-4 #x7) (f-4-4 #xC) (f-8-4 #xE) (f-12-4 opc1) Imm-16-QI)
7342 ((.sym op -sem) QI Imm-16-QI R0l)
7343 ())
7344 ; op.w #imm16,r0
7345 (dni (.sym op 16.w-imm16)
7346 (.str op ".b #imm16")
7347 ((machine 16))
8d0e2679 7348 (.str op ".w #${Imm-16-HI},r0")
49f58d10
JB		 7349 (+ (f-0-4 #x7) (f-4-4 #xD) (f-8-4 #xE) (f-12-4 opc1) Imm-16-HI)
7350 ((.sym op -sem) HI Imm-16-HI R0)
7351 ())
7352 ; op.b #r0h,r0l
7353 (dni (.sym op 16.b-r0h-r0l)
7354 (.str op ".b r0h,r0l")
7355 ((machine 16))
7356 (.str op ".b r0h,r0l")
7357 (+ (f-0-4 #x7) (f-4-4 #xC) (f-8-4 #xE) (f-12-4 opc2))
7358 ((.sym op -sem) QI R0h R0l)
7359 ())
7360 ; op.w #r1,r0
7361 (dni (.sym op 16.w-r1-r0)
7362 (.str op ".b r1,r0")
7363 ((machine 16))
7364 (.str op ".w r1,r0")
7365 (+ (f-0-4 #x7) (f-4-4 #xD) (f-8-4 #xE) (f-12-4 opc2))
7366 ((.sym op -sem) HI R1 R0)
7367 ())
7368 )
7369)
7370
7371; dadc for m16c
7372(decimal-subtraction16-insn dadc #xE #x6 )
7373
7374; dadc.size #imm,dst
7375(binary-arith32-imm-dst-Prefixed QI QI .b 0 dadc X #x8 #x0 #xE dadc-sem)
7376(binary-arith32-imm-dst-Prefixed HI HI .w 1 dadc X #x8 #x0 #xE dadc-sem)
7377; dadc.BW src,dst
7378(binary-arith32-src-dst-Prefixed QI QI .b 0 dadc X #x1 #x8 dadc-sem)
7379(binary-arith32-src-dst-Prefixed HI HI .w 1 dadc X #x1 #x8 dadc-sem)
7380
7381(define-pmacro (dadd-sem mode src dst)
7382 (sequence ((mode result))
7383 (set result (subc mode dst src 0))
7384 (set cbit (sub-cflag mode dst src 0))
7385 (set-z-and-s result)
7386 (set dst result))
7387)
7388
7389; dadd for m16c
7390(decimal-subtraction16-insn dadd #xC #x4)
7391
7392; dadd.size #imm,dst
7393(binary-arith32-imm-dst-Prefixed QI QI .b 0 dadd X #x8 #x1 #xE dadd-sem)
7394(binary-arith32-imm-dst-Prefixed HI HI .w 1 dadd X #x8 #x1 #xE dadd-sem)
7395; dadd.BW src,dst
7396(binary-arith32-src-dst-Prefixed QI QI .b 0 dadd X #x1 #x0 dadd-sem)
7397(binary-arith32-src-dst-Prefixed HI HI .w 1 dadd X #x1 #x0 dadd-sem)
7398
7399;-------------------------------------------------------------;
7400; addx - Add extend sign with no carry
7401;-------------------------------------------------------------;
7402
7403(define-pmacro (addx-sem mode src dst)
7404 (sequence ((SI source) (SI result))
7405 (set source (zext SI (trunc QI src)))
7406 (set result (add SI source dst))
7407 (set obit (add-oflag SI source dst 0))
7408 (set cbit (add-cflag SI source dst 0))
7409 (set-z-and-s result)
7410 (set dst result))
7411)
7412
7413; addx #imm,dst
7414(binary-arith32-imm-dst-defn QI SI "" 0 addx X #x8 #x1 #x1 addx-sem)
7415; addx src,dst
7416(binary-arith32-src-dst-defn QI SI "" 0 addx X #x1 #x2 addx-sem)
7417
7418;-------------------------------------------------------------
7419; adjnz - Add/Sub and branch if not zero
7420;-------------------------------------------------------------
7421
7422(define-pmacro (arith-jnz-sem mode src dst label)
7423 (sequence ((mode result))
7424 (set result (add mode src dst))
7425 (set dst result)
7426 (if (ne result 0)
7427 (set pc label)))
7428)
7429
7430; adjnz.size #imm4,dst,label
c6552317 7431(arith-jnz-imm4-dst adjnz s4 (f-0-4 #xF) (f-4-3 4) #xf #x1 arith-jnz-sem)
49f58d10
JB		 7432
7433;-------------------------------------------------------------
7434; and - binary and
7435;-------------------------------------------------------------
7436
7437(define-pmacro (and-sem mode src1 dst)
7438 (sequence ((mode result))
7439 (set result (and mode src1 dst))
7440 (set-z-and-s result)
7441 (set dst result))
7442)
7443
7444; and.size:G #imm,dst (m16 #1 m32 #1)
7445(binary-arith-imm-dst and G (f-0-4 7) (f-4-3 3) (f-8-4 2) #x8 #x3 #xF and-sem)
7446; and.b:S #imm8,dst3 (m16 #2)
7447(binary-arith16-b-S-imm8-dst3 and ".b" (f-0-4 9) (f-4-1 0) and-sem)
7448; and.BW:G src,dst (m16 #3 m32 #3)
7449(binary-arith-src-dst and G (f-0-4 #x9) (f-4-3 0) #x1 #xD and-sem)
7450; and.B.S src2,r0l/r0h (m16 #4)
7451(binary-arith16-b-S-src2 and (f-0-4 1) (f-4-1 0) and-sem)
7452; and.BW:S #imm,dst2 (m32 #2)
7453(binary-arith32-s-imm-dst QI .b 0 and #x1 #x6 and-sem)
7454(binary-arith32-s-imm-dst HI .w 1 and #x1 #x6 and-sem)
7455
7456;-------------------------------------------------------------
7457; band - bit and
7458;-------------------------------------------------------------
7459
7460(define-pmacro (band-sem src)
7461 (set cbit (and src cbit))
7462)
7463(bitsrc-insn band (f-0-4 7) (f-4-4 #xE) (f-8-4 4) #xD #x0 #x1 band-sem)
7464
7465;-------------------------------------------------------------
7466; bclr - bit clear
7467;-------------------------------------------------------------
7468
7469(define-pmacro (bclr-sem dst)
7470 (set dst 0)
7471)
7472(bitdst-insn bclr (f-0-4 7) (f-4-4 #xE) (f-8-4 8) (f-0-2 1) (f-2-2 0) (f-4-1 0) #xD #x0 #x6 bclr-sem)
7473
7474;-------------------------------------------------------------
7475; bitindex - bit index
7476;-------------------------------------------------------------
7477
7478(define-pmacro (bitindex-sem mode dst)
7479 (set BitIndex dst)
7480)
7481(unary-insn-defn 32 16-Unprefixed QI .b bitindex
7482 (+ (f-0-4 #xC) (f-7-1 0) dst32-16-Unprefixed-QI (f-10-2 #x2) (f-12-4 #xE))
7483 bitindex-sem)
7484(unary-insn-defn 32 16-Unprefixed HI .w bitindex
7485 (+ (f-0-4 #xC) (f-7-1 1) dst32-16-Unprefixed-HI (f-10-2 #x2) (f-12-4 #xE))
7486 bitindex-sem)
7487
7488;-------------------------------------------------------------
7489; bmCnd - bit move condition
7490;-------------------------------------------------------------
7491
7492(define-pmacro (test-condition16 cond)
7493 (case UQI cond
7494 ((#x00) (trunc BI cbit))
7495 ((#x01) (not (or cbit zbit)))
7496 ((#x02) (trunc BI zbit))
7497 ((#x03) (trunc BI sbit))
7498 ((#x04) (or zbit (xor sbit obit)))
7499 ((#x05) (trunc BI obit))
7500 ((#x06) (xor sbit obit))
7501 ((#xf8) (not cbit))
7502 ((#xf9) (or cbit zbit))
7503 ((#xfa) (not zbit))
7504 ((#xfb) (not sbit))
7505 ((#xfc) (not (or zbit (xor sbit obit))))
7506 ((#xfd) (not obit))
7507 ((#xfe) (not (xor sbit obit)))
7508 (else (const BI 0))
7509 )
7510)
7511
7512(define-pmacro (test-condition32 cond)
7513 (case UQI cond
7514 ((#x00) (not cbit))
7515 ((#x01) (or cbit zbit))
7516 ((#x02) (not zbit))
7517 ((#x03) (not sbit))
7518 ((#x04) (not obit))
7519 ((#x05) (not (or zbit (xor sbit obit))))
7520 ((#x06) (not (xor sbit obit)))
7521 ((#x08) (trunc BI cbit))
7522 ((#x09) (not (or cbit zbit)))
7523 ((#x0a) (trunc BI zbit))
7524 ((#x0b) (trunc BI sbit))
7525 ((#x0c) (trunc BI obit))
7526 ((#x0d) (or zbit (xor sbit obit)))
7527 ((#x0e) (xor sbit obit))
7528 (else (const BI 0))
7529 )
7530)
7531
7532(define-pmacro (bitcond-sem mach op cond)
7533 (if ((.sym test-condition mach) cond)
7534 (set op 1)
7535 (set op 0))
7536)
7537(bitcond-insn bm (f-0-4 7) (f-4-4 #xE) (f-8-4 2) #xD #x0 #x2 bitcond-sem)
7538
7539(dni bm16-c
7540 "bm16 C"
7541 ((machine 16))
7542 "bm$cond16c c"
7543 (+ (f-0-4 #x7) (f-4-4 #xD) (f-8-4 #xD) cond16c)
7544 (bitcond-sem 16 cbit cond16c)
7545 ())
7546
7547(dni bm32-c
7548 "bm32 C"
7549 ((machine 32))
7550 "bm$cond32 c"
7551 (+ (f-0-4 #xD) (f-4-4 #x9) (f-8-1 0) (f-10-3 5) cond32)
7552 (bitcond-sem 32 cbit cond32)
7553 ())
7554
7555;-------------------------------------------------------------
7556; bnand
7557;-------------------------------------------------------------
7558
7559(define-pmacro (bnand-sem src)
7560 (set cbit (and (inv src) cbit))
7561)
7562(bitsrc-insn bnand (f-0-4 7) (f-4-4 #xE) (f-8-4 5) #xD #x0 #x3 bnand-sem)
7563
7564;-------------------------------------------------------------
7565; bnor
7566;-------------------------------------------------------------
7567
7568(define-pmacro (bnor-sem src)
7569 (set cbit (or (inv src) cbit))
7570)
7571(bitsrc-insn bnor (f-0-4 7) (f-4-4 #xE) (f-8-4 7) #xD #x0 #x6 bnor-sem)
7572
7573;-------------------------------------------------------------
7574; bnot
7575;-------------------------------------------------------------
7576
7577(define-pmacro (bnot-sem dst)
7578 (set dst (inv dst))
7579)
7580(bitdst-insn bnot (f-0-4 7) (f-4-4 #xE) (f-8-4 #xA) (f-0-2 1) (f-2-2 1) (f-4-1 0) #xD #x0 #x3 bnot-sem)
7581
7582;-------------------------------------------------------------
7583; bntst
7584;-------------------------------------------------------------
7585
7586(define-pmacro (bntst-sem src)
7587 (set cbit (inv src))
7588 (set zbit (inv src))
7589)
7590(bitsrc-insn bntst (f-0-4 7) (f-4-4 #xE) (f-8-4 3) #xD #x0 #x0 bntst-sem)
7591
7592;-------------------------------------------------------------
7593; bnxor
7594;-------------------------------------------------------------
7595
7596(define-pmacro (bnxor-sem src)
7597 (set cbit (xor (inv src) cbit))
7598)
7599(bitsrc-insn bnxor (f-0-4 7) (f-4-4 #xE) (f-8-4 #xD) #xD #x0 #x7 bnxor-sem)
7600
7601;-------------------------------------------------------------
7602; bor
7603;-------------------------------------------------------------
7604
7605(define-pmacro (bor-sem src)
7606 (set cbit (or src cbit))
7607)
7608(bitsrc-insn bor (f-0-4 7) (f-4-4 #xE) (f-8-4 #x6) #xD #x0 #x4 bor-sem)
7609
7610;-------------------------------------------------------------
7611; brk
7612;-------------------------------------------------------------
7613
7614(dni brk16
7615 "brk"
7616 ((machine 16))
7617 "brk"
7618 (+ (f-0-4 #x0) (f-4-4 #x0))
7619 (nop)
7620 ())
7621
7622(dni brk32
7623 "brk"
7624 ((machine 32))
7625 "brk"
7626 (+ (f-0-4 #x0) (f-4-4 #x0))
7627 (nop)
7628 ())
7629
7630;-------------------------------------------------------------
7631; brk2
7632;-------------------------------------------------------------
7633
7634(dni brk232
7635 "brk2"
7636 ((machine 32))
7637 "brk2"
7638 (+ (f-0-4 #x0) (f-4-4 #x8))
7639 (nop)
7640 ())
7641
7642;-------------------------------------------------------------
7643; bset
7644;-------------------------------------------------------------
7645
7646(define-pmacro (bset-sem dst)
7647 (set dst 1)
7648)
7649(bitdst-insn bset (f-0-4 7) (f-4-4 #xE) (f-8-4 9) (f-0-2 1) (f-2-2 0) (f-4-1 1) #xD #x0 #x7 bset-sem)
7650
7651;-------------------------------------------------------------
7652; btst
7653;-------------------------------------------------------------
7654
7655(define-pmacro (btst-sem dst)
7656 (set zbit (inv dst))
7657 (set cbit dst)
7658)
8d0e2679
DD		 7659(bitdst16-defn btst (f-0-4 7) (f-4-4 #xE) (f-8-4 #xB) (f-0-2 1) (f-2-2 1) (f-4-1 1) btst-sem)
7660
7661(bit-insn-defn 32 btst G bit32-16-Unprefixed
7662 (+ (f-0-4 #xD) bit32-16-Unprefixed (f-7-1 #x0) (f-10-3 #x0))
7663 btst-sem)
7664
43aa3bb1
DD		 7665(dni btst.s "btst:s" ((machine 32))
7666 "btst:s ${Bit3-S},${Dsp-8-u16}"
7667 (+ (f-0-2 #x0) (f-4-3 #x5) Bit3-S Dsp-8-u16)
7668 () ())
49f58d10
JB		 7669
7670;-------------------------------------------------------------
7671; btstc
7672;-------------------------------------------------------------
7673
7674(define-pmacro (btstc-sem dst)
7675 (set zbit (inv dst))
7676 (set cbit dst)
7677 (set dst (const 0))
7678)
7679(bitdstnos-insn btstc (f-0-4 7) (f-4-4 #xE) (f-8-4 #x0) #xD #x0 #x4 btstc-sem)
7680
7681;-------------------------------------------------------------
7682; btsts
7683;-------------------------------------------------------------
7684
7685(define-pmacro (btsts-sem dst)
7686 (set zbit (inv dst))
7687 (set cbit dst)
7688 (set dst (const 0))
7689)
7690(bitdstnos-insn btsts (f-0-4 7) (f-4-4 #xE) (f-8-4 #x1) #xD #x0 #x5 btsts-sem)
7691
7692;-------------------------------------------------------------
7693; bxor
7694;-------------------------------------------------------------
7695
7696(define-pmacro (bxor-sem src)
7697 (set cbit (xor src cbit))
7698)
7699(bitsrc-insn bxor (f-0-4 7) (f-4-4 #xE) (f-8-4 #xC) #xD #x0 #x5 bxor-sem)
7700
7701;-------------------------------------------------------------
7702; clip
7703;-------------------------------------------------------------
7704
7705(define-pmacro (clip-sem mode imm1 imm2 dest)
7706 (sequence ()
7707 (if (gt mode imm1 dest)
7708 (set dest imm1))
7709 (if (lt mode imm2 dest)
7710 (set dest imm2)))
7711)
7712
7713(insn-imm1-imm2-dst-Prefixed clip #x8 #x3 #xE clip-sem)
7714
7715;-------------------------------------------------------------
7716; cmp - binary compare
7717;-------------------------------------------------------------
7718
7719(define-pmacro (cmp-sem mode src1 dst)
7720 (sequence ((mode result))
7721 (set result (sub mode dst src1))
7722 (set obit (sub-oflag mode dst src1 0))
7723 (set cbit (not (sub-cflag mode dst src1 0)))
7724 (set-z-and-s result))
7725)
7726
7727; cmp.L:G #imm32,dst (m32 #2)
7728(binary-arith32-imm-dst-defn SI SI .l 0 cmp G #xA #x3 #x1 cmp-sem)
7729; cmp.size:G #imm,dst (m16 #1 m32 #1)
7730(binary-arith-imm-dst cmp G (f-0-4 7) (f-4-3 3) (f-8-4 8) #x9 #x2 #xE cmp-sem)
7731; cmp.size:Q #imm4,dst (m16 #2 m32 #3)
7732(binary-arith-imm4-dst cmp (f-0-4 #xD) (f-4-3 0) #x7 #x1 cmp-sem)
7733; cmp.b:S #imm8,dst3 (m16 #3)
7734(binary-arith16-b-S-imm8-dst3 cmp ".b" (f-0-4 #xE) (f-4-1 0) cmp-sem)
7735; cmp.BW:G src,dst (m16 #4 m32 #5)
7736(binary-arith-src-dst cmp G (f-0-4 #xC) (f-4-3 0) #x1 #x6 cmp-sem)
7737; cmp.B.S src2,r0l/r0h (m16 #5)
7738(binary-arith16-b-S-src2 cmp (f-0-4 3) (f-4-1 1) cmp-sem)
7739; cmp.L:G src,dst (m32 #6)
7740(binary-arith32-src-dst-defn SI SI .l 1 cmp G #x1 #x1 cmp-sem)
7741; cmp.BW:S #imm,dst2 (m32 #4)
7742(binary-arith32-s-imm-dst QI .b 0 cmp #x1 #x3 cmp-sem)
7743(binary-arith32-s-imm-dst HI .w 1 cmp #x1 #x3 cmp-sem)
7744; cmp.BW:s src2,r0[l] (m32 #7)
7745(binary-arith32-S-src2 cmp QI .b 0 (f-0-2 1) (f-4-3 0) cmp-sem)
7746(binary-arith32-S-src2 cmp HI .w 1 (f-0-2 1) (f-4-3 0) cmp-sem)
7747
7748;-------------------------------------------------------------
7749; cmpx - binary compare extend sign
7750;-------------------------------------------------------------
7751
7752(define-pmacro (cmpx-sem mode src1 dst)
7753 (sequence ((mode result))
7754 (set result (sub mode dst (ext mode src1)))
7755 (set obit (sub-oflag mode dst (ext mode src1) 0))
7756 (set cbit (sub-cflag mode dst (ext mode src1) 0))
7757 (set-z-and-s result))
7758)
7759
7760(binary-arith32-imm-dst-defn QI SI "" 0 cmpx X #xA #x1 #x1 cmpx-sem)
7761
7762;-------------------------------------------------------------
7763; dec - decrement
7764;-------------------------------------------------------------
7765
7766(define-pmacro (dec-sem mode dest)
7767 (sequence ((mode result))
7768 (set result (sub mode dest 1))
7769 (set-z-and-s result)
7770 (set dest result))
7771)
7772
7773(dni dec16.b
7774 "dec.b Dst16-3-S-8"
7775 ((machine 16))
7776 "dec.b ${Dst16-3-S-8}"
7777 (+ (f-0-4 #xA) (f-4-1 #x1) Dst16-3-S-8)
7778 (dec-sem QI Dst16-3-S-8)
7779 ())
7780
7781(dni dec16.w
7782 "dec.w Dst16An-S"
7783 ((machine 16))
7784 "dec.w ${Dst16An-S}"
7785 (+ (f-0-4 #xF) (f-5-3 #x2) Dst16An-S)
7786 (dec-sem HI Dst16An-S)
7787 ())
7788
7789(unary32-defn QI .b 0 dec #xB #x0 #xE dec-sem)
7790(unary32-defn HI .w 1 dec #xB #x0 #xE dec-sem)
7791
7792;-------------------------------------------------------------
7793; div - divide
7794; divu - divide unsigned
7795; divx - divide extension
7796;-------------------------------------------------------------
7797
7798; div.BW #imm
7799(div-imm div div mod SI 127 -128 32767 -32768 (f-0-4 #x7) (f-4-3 6) (f-8-4 #xE) (f-12-4 #x1) #xB #x0 #x2 #x3 div-sem)
7800(div-imm divu udiv umod USI 255 0 65535 0 (f-0-4 #x7) (f-4-3 6) (f-8-4 #xE) (f-12-4 #x0) #xB #x0 #x0 #x3 div-sem)
7801(div-imm divx div mod SI 127 -128 32767 -32768 (f-0-4 #x7) (f-4-3 6) (f-8-4 #xE) (f-12-4 #x3) #xB #x2 #x2 #x3 div-sem)
7802; div.BW src
7803(div-src div div mod SI 127 -128 32767 -32768 (f-0-4 #x7) (f-4-3 3) (f-8-4 #xD) #x8 #x1 #xE div-sem)
7804(div-src divu udiv umod USI 255 0 65535 0 (f-0-4 #x7) (f-4-3 3) (f-8-4 #xC) #x8 #x0 #xE div-sem)
7805(div-src divx div mod SI 127 -128 32767 -32768 (f-0-4 #x7) (f-4-3 3) (f-8-4 #x9) #x9 #x1 #xE div-sem)
7806
7807(div-src-defn 32 .l div dst32-24-Prefixed-SI
7808 (+ (f-0-4 0) (f-4-4 1) (f-8-4 #xA) (f-15-1 1) (f-18-2 #x1) (f-20-4 #xf) dst32-24-Prefixed-SI)
7809 div mod SI R2R0 R2R0 NoRemainder #x7fffffff (neg SI #x80000000)
7810 div-sem)
7811(div-src-defn 32 .l divu dst32-24-Prefixed-SI
7812 (+ (f-0-4 0) (f-4-4 1) (f-8-4 #xA) (f-15-1 1) (f-18-2 #x0) (f-20-4 #xf) dst32-24-Prefixed-SI)
7813 udiv umod USI R2R0 R2R0 NoRemainder #x80000000 0
7814 div-sem)
7815(div-src-defn 32 .l divx dst32-24-Prefixed-SI
7816 (+ (f-0-4 0) (f-4-4 1) (f-8-4 #xA) (f-15-1 1) (f-18-2 #x2) (f-20-4 #xf) dst32-24-Prefixed-SI)
7817 div mod SI R2R0 R2R0 NoRemainder #x7fffffff (neg SI #x80000000)
7818 div-sem)
7819
7820;-------------------------------------------------------------
7821; dsbb - decimal subtraction with borrow
7822; dsub - decimal subtraction
7823;-------------------------------------------------------------
7824
7825(define-pmacro (dsbb-sem mode src dst)
7826 (sequence ((mode result))
7827 (set result (subc mode dst src (not cbit)))
7828 (set cbit (sub-cflag mode dst src (not cbit)))
7829 (set-z-and-s result)
7830 (set dst result))
7831)
7832
7833; dsbb for m16c
7834(decimal-subtraction16-insn dsbb #xF #x7)
7835
7836; dsbb.size #imm,dst
7837(binary-arith32-imm-dst-Prefixed QI QI .b 0 dsbb X #x9 #x0 #xE dsbb-sem)
7838(binary-arith32-imm-dst-Prefixed HI HI .w 1 dsbb X #x9 #x0 #xE dsbb-sem)
7839; dsbb.BW src,dst
7840(binary-arith32-src-dst-Prefixed QI QI .b 0 dsbb X #x1 #xA dsbb-sem)
7841(binary-arith32-src-dst-Prefixed HI HI .w 1 dsbb X #x1 #xA dsbb-sem)
7842
7843(define-pmacro (dsub-sem mode src dst)
7844 (sequence ((mode result))
7845 (set result (subc mode dst src 0))
7846 (set cbit (sub-cflag mode dst src 0))
7847 (set-z-and-s result)
7848 (set dst result))
7849)
7850
7851; dsub for m16c
7852(decimal-subtraction16-insn dsub #xD #x5)
7853
7854; dsub.size #imm,dst
7855(binary-arith32-imm-dst-Prefixed QI QI .b 0 dsub X #x9 #x1 #xE dsub-sem)
7856(binary-arith32-imm-dst-Prefixed HI HI .w 1 dsub X #x9 #x1 #xE dsub-sem)
7857; dsub.BW src,dst
7858(binary-arith32-src-dst-Prefixed QI QI .b 0 dsub X #x1 #x2 dsub-sem)
7859(binary-arith32-src-dst-Prefixed HI HI .w 1 dsub X #x1 #x2 dsub-sem)
7860
7861;-------------------------------------------------------------
7862; sub - binary subtraction
7863;-------------------------------------------------------------
7864
7865(define-pmacro (sub-sem mode src1 dst)
7866 (sequence ((mode result))
7867 (set result (sub mode dst src1))
7868 (set obit (sub-oflag mode dst src1 0))
7869 (set cbit (sub-cflag mode dst src1 0))
7870 (set dst result)
7871 (set-z-and-s result)))
7872
7873; sub.size:G #imm,dst (m16 #1 m32 #1)
7874(binary-arith-imm-dst sub G (f-0-4 7) (f-4-3 3) (f-8-4 5) #x8 #x3 #xE sub-sem)
7875; sub.b:S #imm8,dst3 (m16 #2)
7876(binary-arith16-b-S-imm8-dst3 sub ".b" (f-0-4 8) (f-4-1 1) sub-sem)
7877; sub.BW:G src,dst (m16 #3 m32 #4)
7878(binary-arith-src-dst sub G (f-0-4 #xA) (f-4-3 4) #x1 #xA sub-sem)
7879; sub.B.S src2,r0l/r0h (m16 #4)
7880(binary-arith16-b-S-src2 sub (f-0-4 2) (f-4-1 1) sub-sem)
7881; sub.L:G #imm32,dst (m32 #2)
7882(binary-arith32-imm-dst-defn SI SI .l 0 sub G #x9 #x3 #x1 sub-sem)
7883; sub.BW:S #imm,dst2 (m32 #3)
7884(binary-arith32-s-imm-dst QI .b 0 sub #x0 #x7 sub-sem)
7885(binary-arith32-s-imm-dst HI .w 1 sub #x0 #x7 sub-sem)
7886; sub.L:G src,dst (m32 #5)
7887(binary-arith32-src-dst-defn SI SI .l 1 sub G #x1 #x0 sub-sem)
7888
7889;-------------------------------------------------------------
7890; enter - enter function
7891; exitd - exit and deallocate stack frame
7892;-------------------------------------------------------------
7893
7894(define-pmacro (enter16-sem mach amt)
7895 (sequence ()
7896 (set (reg h-sp) (sub (reg h-sp) 2))
7897 (set (mem16 HI (reg h-sp)) (reg h-fb))
7898 (set (reg h-fb) (reg h-sp))
7899 (set (reg h-sp) (sub (reg h-sp) amt))))
7900
7901(define-pmacro (exit16-sem mach)
7902 (sequence ((SI newpc))
7903 (set (reg h-sp) (reg h-fb))
7904 (set (reg h-fb) (mem16 HI (reg h-sp)))
7905 (set (reg h-sp) (add (reg h-sp) 2))
7906 (set newpc (mem16 HI (reg h-sp)))
7907 (set (reg h-sp) (add (reg h-sp) 2))
7908 (set newpc (or newpc (sll (mem16 QI (reg h-sp)) (const 16))))
7909 (set (reg h-sp) (add (reg h-sp) 1))
7910 (set pc newpc)))
7911
7912(define-pmacro (enter32-sem mach amt)
7913 (sequence ()
7914 (set (reg h-sp) (sub (reg h-sp) 4))
7915 (set (mem32 SI (reg h-sp)) (reg h-fb))
7916 (set (reg h-fb) (reg h-sp))
7917 (set (reg h-sp) (sub (reg h-sp) amt))))
7918
7919(define-pmacro (exit32-sem mach)
7920 (sequence ((SI newpc))
7921 (set (reg h-sp) (reg h-fb))
7922 (set (reg h-fb) (mem32 SI (reg h-sp)))
7923 (set (reg h-sp) (add (reg h-sp) 4))
7924 (set newpc (mem32 SI (reg h-sp)))
7925 (set (reg h-sp) (add (reg h-sp) 4))
7926 (set pc newpc)))
7927
7928(dni enter16 "enter #Imm-16-QI" ((machine 16))
7929 ("enter #${Dsp-16-u8}")
7930 (+ (f-0-4 7) (f-4-4 #xC) (f-8-4 #xF) (f-12-4 2) Dsp-16-u8)
7931 (enter16-sem 16 Dsp-16-u8)
7932 ())
7933
7934(dni exitd16 "exitd" ((machine 16))
7935 ("exitd")
7936 (+ (f-0-4 7) (f-4-4 #xD) (f-8-4 #xF) (f-12-4 2))
7937 (exit16-sem 16)
7938 ())
7939
7940(dni enter32 "enter #Imm-8-QI" ((machine 32))
7941 ("enter #${Dsp-8-u8}")
7942 (+ (f-0-4 #xE) (f-4-4 #xC) Dsp-8-u8)
7943 (enter32-sem 32 Dsp-8-u8)
7944 ())
7945
7946(dni exitd32 "exitd" ((machine 32))
7947 ("exitd")
7948 (+ (f-0-4 #xF) (f-4-4 #xC))
7949 (exit32-sem 32)
7950 ())
7951
7952;-------------------------------------------------------------
7953; fclr - flag register clear
7954; fset - flag register set
7955;-------------------------------------------------------------
7956
7957(define-pmacro (set-flags-sem flag)
7958 (sequence ((SI tmp))
7959 (case DFLT flag
7960 ((#x0) (set cbit 1))
7961 ((#x1) (set dbit 1))
7962 ((#x2) (set zbit 1))
7963 ((#x3) (set sbit 1))
7964 ((#x4) (set bbit 1))
7965 ((#x5) (set obit 1))
7966 ((#x6) (set ibit 1))
7967 ((#x7) (set ubit 1)))
7968 )
7969 )
7970
7971(define-pmacro (clear-flags-sem flag)
7972 (sequence ((SI tmp))
7973 (case DFLT flag
7974 ((#x0) (set cbit 0))
7975 ((#x1) (set dbit 0))
7976 ((#x2) (set zbit 0))
7977 ((#x3) (set sbit 0))
7978 ((#x4) (set bbit 0))
7979 ((#x5) (set obit 0))
7980 ((#x6) (set ibit 0))
7981 ((#x7) (set ubit 0)))
7982 )
7983 )
7984
7985(dni fclr16 "fclr flag" ((machine 16))
7986 ("fclr ${flags16}")
7987 (+ (f-0-4 #xE) (f-4-4 #xB) (f-8-1 0) flags16 (f-12-4 5))
7988 (clear-flags-sem flags16)
7989 ())
7990
7991(dni fset16 "fset flag" ((machine 16))
7992 ("fset ${flags16}")
7993 (+ (f-0-4 #xE) (f-4-4 #xB) (f-8-1 0) flags16 (f-12-4 4))
7994 (set-flags-sem flags16)
7995 ())
7996
7997(dni fclr "fclr" ((machine 32))
7998 ("fclr ${flags32}")
7999 (+ (f-0-4 #xD) (f-4-4 3) (f-8-4 #xE) (f-12-1 1) flags32)
8000 (clear-flags-sem flags32)
8001 ())
8002
8003(dni fset "fset" ((machine 32))
8004 ("fset ${flags32}")
8005 (+ (f-0-4 #xD) (f-4-4 1) (f-8-4 #xE) (f-12-1 1) flags32)
8006 (set-flags-sem flags32)
8007 ())
8008
8009;-------------------------------------------------------------
8010; inc - increment
8011;-------------------------------------------------------------
8012
8013(define-pmacro (inc-sem mode dest)
8014 (sequence ((mode result))
8015 (set result (add mode dest 1))
8016 (set-z-and-s result)
8017 (set dest result))
8018)
8019
8020(dni inc16.b
8021 "inc.b Dst16-3-S-8"
8022 ((machine 16))
8023 "inc.b ${Dst16-3-S-8}"
8024 (+ (f-0-4 #xA) (f-4-1 #x0) Dst16-3-S-8)
8025 (inc-sem QI Dst16-3-S-8)
8026 ())
8027
8028(dni inc16.w
8029 "inc.w Dst16An-S"
8030 ((machine 16))
8031 "inc.w ${Dst16An-S}"
8032 (+ (f-0-4 #xB) (f-5-3 #x2) Dst16An-S)
8033 (inc-sem HI Dst16An-S)
8034 ())
8035
8036(unary32-defn QI .b 0 inc #xA #x0 #xE inc-sem)
8037(unary32-defn HI .w 1 inc #xA #x0 #xE inc-sem)
8038
8039;-------------------------------------------------------------
8040; freit - fast return from interrupt (m32)
8041; int - interrupt
8042; into - interrupt on overflow
8043;-------------------------------------------------------------
8044
8045; ??? semantics
8046(dni freit32 "FREIT" ((machine 32))
8047 ("freit")
8048 (+ (f-0-4 9) (f-4-4 #xF))
8049 (nop)
8050 ())
8051
8052(dni int16 "int Dsp-10-u6" ((machine 16))
8053 ("int #${Dsp-10-u6}")
8054 (+ (f-0-4 #xE) (f-4-4 #xB) (f-8-2 3) Dsp-10-u6)
8055 (c-call VOID "do_int" pc Dsp-10-u6)
8056 ())
8057
8058(dni into16 "into" ((machine 16))
8059 ("into")
8060 (+ (f-0-4 #xF) (f-4-4 6))
8061 (nop)
8062 ())
8063
8064(dni int32 "int Dsp-8-u6" ((machine 32))
8065 ("int #${Dsp-8-u6}")
8066 (+ (f-0-4 #xB) (f-4-4 #xE) Dsp-8-u6 (f-14-2 0))
8067 (c-call VOID "do_int" pc Dsp-8-u6)
8068 ())
8069
8070(dni into32 "into" ((machine 32))
8071 ("into")
8072 (+ (f-0-4 #xB) (f-4-4 #xF))
8073 (nop)
8074 ())
8075
8076;-------------------------------------------------------------
8077; index (m32c)
8078;-------------------------------------------------------------
8079
8080; TODO add support to insns allowing index
8081(define-pmacro (indexb-sem mode d) (set SrcIndex d) (set DstIndex d))
8082(define-pmacro (indexbd-sem mode d) (set SrcIndex (const 0)) (set DstIndex d))
8083(define-pmacro (indexbs-sem mode d) (set SrcIndex d) (set DstIndex (const 0)))
8084(define-pmacro (indexw-sem mode d)
8085 (set SrcIndex (sll d (const 2))) (set DstIndex (sll d (const 2))))
8086(define-pmacro (indexwd-sem mode d)
8087 (set SrcIndex (const 0)) (set DstIndex (sll d (const 2))))
8088(define-pmacro (indexws-sem mode d)
8089 (set SrcIndex (sll d (const 2))) (set DstIndex (const 0)))
8090(define-pmacro (indexl-sem mode d)
8091 (set SrcIndex d) (set DstIndex (sll d (const 2))))
8092(define-pmacro (indexld-sem mode d)
8093 (set SrcIndex (const 0)) (set DstIndex (sll d (const 2))))
8094(define-pmacro (indexls-sem mode d)
8095 (set SrcIndex (sll d (const 2))) (set DstIndex (const 0)))
8096
eda87aba
DD		 8097; Note that "wbit" not where the size bit goes here, hence, it's
8098; always 0 in these calls but op2 differs instead.
8099
49f58d10
JB		 8100; indexb src (index byte)
8101(unary32-defn QI .b 0 indexb #x8 0 #x3 indexb-sem)
eda87aba 8102(unary32-defn HI .w 0 indexb #x8 1 #x3 indexb-sem)
49f58d10
JB		 8103; indexbd src (index byte dest)
8104(unary32-defn QI .b 0 indexbd #xA 0 3 indexbd-sem)
eda87aba 8105(unary32-defn HI .w 0 indexbd #xA 1 3 indexbd-sem)
49f58d10
JB		 8106; indexbs src (index byte src)
8107(unary32-defn QI .b 0 indexbs #xC 0 3 indexbs-sem)
eda87aba 8108(unary32-defn HI .w 0 indexbs #xC 1 3 indexbs-sem)
49f58d10
JB		 8109; indexl src (index long)
8110(unary32-defn QI .b 0 indexl 9 2 3 indexl-sem)
eda87aba 8111(unary32-defn HI .w 0 indexl 9 3 3 indexl-sem)
49f58d10
JB		 8112; indexld src (index long dest)
8113(unary32-defn QI .b 0 indexld #xB 2 3 indexld-sem)
eda87aba 8114(unary32-defn HI .w 0 indexld #xB 3 3 indexld-sem)
49f58d10
JB		 8115; indexls src (index long src)
8116(unary32-defn QI .b 0 indexls 9 0 3 indexls-sem)
eda87aba 8117(unary32-defn HI .w 0 indexls 9 1 3 indexls-sem)
49f58d10
JB		 8118; indexw src (index word)
8119(unary32-defn QI .b 0 indexw 8 2 3 indexw-sem)
eda87aba 8120(unary32-defn HI .w 0 indexw 8 3 3 indexw-sem)
49f58d10
JB		 8121; indexwd src (index word dest)
8122(unary32-defn QI .b 0 indexwd #xA 2 3 indexwd-sem)
eda87aba 8123(unary32-defn HI .w 0 indexwd #xA 3 3 indexwd-sem)
49f58d10
JB		 8124; indexws (index word src)
8125(unary32-defn QI .b 0 indexws #xC 2 3 indexws-sem)
eda87aba 8126(unary32-defn HI .w 0 indexws #xC 3 3 indexws-sem)
49f58d10
JB		 8127
8128;-------------------------------------------------------------
8129; jcc - jump on condition
8130;-------------------------------------------------------------
8131
8132(define-pmacro (jcnd32-sem cnd label)
8133 (sequence ()
8134 (case DFLT cnd
8135 ((#x00) (if (not cbit) (set pc label))) ;ltu nc
8136 ((#x01) (if (not (and cbit (not zbit))) (set pc label))) ;leu
8137 ((#x02) (if (not zbit) (set pc label))) ;ne nz
8138 ((#x03) (if (not sbit) (set pc label))) ;pz
8139 ((#x04) (if (not obit) (set pc label))) ;no
8140 ((#x05) (if (not (or zbit (xor sbit obit))) (set pc label))) ;gt
8141 ((#x06) (if (not (xor sbit obit)) (set pc label))) ;ge
8142 ((#x08) (if (trunc BI cbit) (set pc label))) ;geu c
8143 ((#x09) (if (and cbit (not zbit)) (set pc label))) ;gtu
8144 ((#x0a) (if (trunc BI zbit) (set pc label))) ;eq z
8145 ((#x0b) (if (trunc BI sbit) (set pc label))) ;n
8146 ((#x0c) (if (trunc BI obit) (set pc label))) ;o
8147 ((#x0d) (if (or zbit (xor sbit obit)) (set pc label))) ;le
8148 ((#x0e) (if (xor sbit obit) (set pc label))) ;lt
8149 )
8150 )
8151 )
8152
8153(define-pmacro (jcnd16-sem cnd label)
8154 (sequence ()
8155 (case DFLT cnd
8156 ((#x00) (if (trunc BI cbit) (set pc label))) ;geu c
8157 ((#x01) (if (and cbit (not zbit)) (set pc label))) ;gtu
8158 ((#x02) (if (trunc BI zbit) (set pc label))) ;eq z
8159 ((#x03) (if (trunc BI sbit) (set pc label))) ;n
8160 ((#x04) (if (not cbit) (set pc label))) ;ltu nc
8161 ((#x05) (if (not (and cbit (not zbit))) (set pc label))) ;leu
8162 ((#x06) (if (not zbit) (set pc label))) ;ne nz
8163 ((#x07) (if (not sbit) (set pc label))) ;pz
8164 ((#x08) (if (or zbit (xor sbit obit)) (set pc label))) ;le
8165 ((#x09) (if (trunc BI obit) (set pc label))) ;o
8166 ((#x0a) (if (not (xor sbit obit)) (set pc label))) ;ge
8167 ((#x0c) (if (not (or zbit (xor sbit obit))) (set pc label))) ;gt
8168 ((#x0d) (if (not obit) (set pc label))) ;no
8169 ((#x0e) (if (xor sbit obit) (set pc label))) ;lt
8170 )
8171 )
8172 )
8173
8174(dni jcnd16-5
8175 "jCnd label"
6772dd07 8176 (RL_JUMP RELAXABLE (machine 16))
49f58d10
JB		 8177 "j$cond16j5 ${Lab-8-8}"
8178 (+ (f-0-4 #x6) (f-4-1 1) cond16j5 Lab-8-8)
8179 (jcnd16-sem cond16j5 Lab-8-8)
8180 ()
8181)
8182
8183(dni jcnd16
8184 "jCnd label"
6772dd07 8185 (RL_JUMP RELAXABLE (machine 16))
49f58d10
JB		 8186 "j$cond16j ${Lab-16-8}"
8187 (+ (f-0-4 #x7) (f-4-4 #xD) (f-8-4 #xC) cond16j Lab-16-8)
8188 (jcnd16-sem cond16j Lab-16-8)
8189 ()
8190)
8191
8192(dni jcnd32
8193 "jCnd label"
6772dd07 8194 (RL_JUMP RELAXABLE (machine 32))
49f58d10
JB		 8195 "j$cond32j ${Lab-8-8}"
8196 (+ (f-0-1 1) (f-4-3 5) cond32j Lab-8-8)
8197 (jcnd32-sem cond32j Lab-8-8)
8198 ()
8199)
8200
8201;-------------------------------------------------------------
8202; jmp - jump
8203;-------------------------------------------------------------
8204
8205; jmp.s label3 (m16 #1)
6772dd07 8206(dni jmp16.s "jmp.s Lab-5-3" (RL_JUMP RELAXABLE (machine 16))
49f58d10
JB		 8207 ("jmp.s ${Lab-5-3}")
8208 (+ (f-0-4 6) (f-4-1 0) Lab-5-3)
8209 (sequence () (set pc Lab-5-3))
8210 ())
8211; jmp.b label8 (m16 #2)
6772dd07 8212(dni jmp16.b "jmp.b Lab-8-8" (RL_JUMP RELAXABLE (machine 16))
49f58d10
JB		 8213 ("jmp.b ${Lab-8-8}")
8214 (+ (f-0-4 #xF) (f-4-4 #xE) Lab-8-8)
8215 (sequence () (set pc Lab-8-8))
8216 ())
8217; jmp.w label16 (m16 #3)
6772dd07 8218(dni jmp16.w "jmp.w Lab-8-16" (RL_JUMP RELAXABLE (machine 16))
49f58d10
JB		 8219 ("jmp.w ${Lab-8-16}")
8220 (+ (f-0-4 #xF) (f-4-4 4) Lab-8-16)
8221 (sequence () (set pc Lab-8-16))
8222 ())
8223; jmp.a label24 (m16 #4)
6772dd07 8224(dni jmp16.a "jmp.a Lab-8-24" (RL_JUMP RELAXABLE (machine 16))
49f58d10
JB		 8225 ("jmp.a ${Lab-8-24}")
8226 (+ (f-0-4 #xF) (f-4-4 #xC) Lab-8-24)
8227 (sequence () (set pc Lab-8-24))
8228 ())
8229
8230(define-pmacro (jmp16-sem mode dst)
8231 (set pc (and dst #xfffff))
8232)
8233(define-pmacro (jmp32-sem mode dst)
8234 (set pc dst)
8235)
8236; jmpi.w dst (m16 #1 m32 #2)
8237(unary-insn-defn 16 16 HI .w jmpi (+ (f-0-4 7) (f-4-4 #xD) (f-8-4 2) dst16-16-HI) jmp16-sem)
8238(unary-insn-defn 32 16-Unprefixed HI .w jmpi (+ (f-0-4 #xC) (f-7-1 1) dst32-16-Unprefixed-HI (f-10-2 #x0) (f-12-4 #xF)) jmp32-sem)
8239; jmpi.a dst (m16 #2 m32 #2)
8240(unary-insn-defn 16 16 SI .a jmpi (+ (f-0-4 7) (f-4-4 #xD) (f-8-4 0) dst16-16-SI) jmp16-sem)
8241(unary-insn-defn 32 16-Unprefixed SI .a jmpi (+ (f-0-4 #x8) (f-7-1 0) dst32-16-Unprefixed-SI (f-10-2 #x0) (f-12-4 1)) jmp32-sem)
8242; jmps imm8 (m16 #1)
8243(dni jmps16 "jmps Imm-8-QI" ((machine 16))
8244 ("jmps #${Imm-8-QI}")
8245 (+ (f-0-4 #xE) (f-4-4 #xE) Imm-8-QI)
8246 (sequence () (set pc Imm-8-QI))
8247 ())
8248; jmp.s label3 (m32 #1)
8249(dni jmp32.s
8250 "jmp.s label"
6772dd07 8251 (RL_JUMP RELAXABLE (machine 32))
49f58d10
JB		 8252 "jmp.s ${Lab32-jmp-s}"
8253 (+ (f-0-2 1) (f-4-3 5) Lab32-jmp-s)
8254 (set pc Lab32-jmp-s)
8255 ()
8256)
8257; jmp.b label8 (m32 #2)
6772dd07 8258(dni jmp32.b "jmp.b Lab-8-8" (RL_JUMP RELAXABLE (machine 32))
49f58d10
JB		 8259 ("jmp.b ${Lab-8-8}")
8260 (+ (f-0-4 #xB) (f-4-4 #xB) Lab-8-8)
8261 (set pc Lab-8-8)
8262 ())
8263; jmp.w label16 (m32 #3)
6772dd07 8264(dni jmp32.w "jmp.w Lab-8-16" (RL_JUMP RELAXABLE (machine 32))
49f58d10
JB		 8265 ("jmp.w ${Lab-8-16}")
8266 (+ (f-0-4 #xC) (f-4-4 #xE) Lab-8-16)
8267 (set pc Lab-8-16)
8268 ())
8269; jmp.a label24 (m32 #4)
6772dd07 8270(dni jmp32.a "jmp.a Lab-8-24" (RL_JUMP RELAXABLE (machine 32))
49f58d10
JB		 8271 ("jmp.a ${Lab-8-24}")
8272 (+ (f-0-4 #xC) (f-4-4 #xC) Lab-8-24)
8273 (set pc Lab-8-24)
8274 ())
8275; jmp.s imm8 (m32 #1)
6772dd07 8276(dni jmps32 "jmps Imm-8-QI" (RL_JUMP (machine 32))
49f58d10
JB		 8277 ("jmps #${Imm-8-QI}")
8278 (+ (f-0-4 #xD) (f-4-4 #xC) Imm-8-QI)
8279 (set pc Imm-8-QI)
8280 ())
8281
8282;-------------------------------------------------------------
8283; jsr jump subroutine
8284;-------------------------------------------------------------
8285
8286(define-pmacro (jsr16-sem length dst)
8287 (sequence ((SI tpc))
8288 (set tpc (add pc length))
8289 (set (reg h-sp) (sub (reg h-sp) 2))
8290 (set (mem16 HI (reg h-sp)) (srl (and tpc #xffff00) 8))
8291 (set (reg h-sp) (sub (reg h-sp) 1))
8292 (set (mem16 QI (reg h-sp)) (and tpc #xff))
8293 (set pc dst)
8294 )
8295)
8296(define-pmacro (jsr32-sem length dst)
8297 (sequence ((SI tpc))
8298 (set tpc (add pc length))
8299 (set (reg h-sp) (sub (reg h-sp) 2))
8300 (set (mem32 HI (reg h-sp)) (srl (and tpc #xffff0000) 16))
8301 (set (reg h-sp) (sub (reg h-sp) 2))
8302 (set (mem32 HI (reg h-sp)) (and tpc #xffff))
8303 (set pc dst)
8304 )
8305)
8306
8307; jsr.w label16 (m16 #1)
6772dd07 8308(dni jsr16.w "jsr.w Lab-8-16" (RL_JUMP RELAXABLE (machine 16))
49f58d10
JB		 8309 ("jsr.w ${Lab-8-16}")
8310 (+ (f-0-4 #xF) (f-4-4 5) Lab-8-16)
8311 (jsr16-sem 3 Lab-8-16)
8312 ())
8313; jsr.a label24 (m16 #2)
6772dd07 8314(dni jsr16.a "jsr.a Lab-8-24" (RL_JUMP RELAXABLE (machine 16))
49f58d10
JB		 8315 ("jsr.a ${Lab-8-24}")
8316 (+ (f-0-4 #xF) (f-4-4 #xD) Lab-8-24)
8317 (jsr16-sem 4 Lab-8-24)
8318 ())
8319(define-pmacro (jsri-defn mode op16 op16-1 op16-2 op16-3 op16-sem
8320 op32 op32-1 op32-2 op32-3 op32-4 op32-sem len)
8321 (begin
8322 (dni (.sym jsri16 mode - op16)
8323 (.str "jsri." mode " " op16)
6772dd07 8324 (RL_1ADDR (machine 16))
49f58d10
JB		 8325 (.str "jsri." mode " ${" op16 "}")
8326 (+ op16-1 op16-2 op16-3 op16)
8327 (op16-sem len op16)
8328 ())
8329 (dni (.sym jsri32 mode - op32)
8330 (.str "jsri." mode " " op32)
6772dd07 8331 (RL_1ADDR (machine 32))
49f58d10
JB		 8332 (.str "jsri." mode " ${" op32 "}")
8333 (+ op32-1 op32-2 op32-3 op32-4 op32)
8334 (op32-sem len op32)
8335 ())
8336 )
8337 )
8338; jsri.w dst (m16 #1 m32 #1))
75b06e7b
DD		 8339(jsri-defn w dst16-16-20ar-HI (f-0-4 #x7) (f-4-4 #xD) (f-8-4 #x3) jsr16-sem
8340 dst32-16-24-Unprefixed-HI (f-0-4 #xC) (f-7-1 1) (f-10-2 #x1) (f-12-4 #xF) jsr32-sem 4)
8341(jsri-defn w dst16-16-16sa-HI (f-0-4 #x7) (f-4-4 #xD) (f-8-4 #x3) jsr16-sem
8342 dst32-16-16sa-Unprefixed-HI (f-0-4 #xC) (f-7-1 1) (f-10-2 #x1) (f-12-4 #xF) jsr32-sem 4)
49f58d10
JB		 8343(jsri-defn w dst16-16-8-HI (f-0-4 #x7) (f-4-4 #xD) (f-8-4 #x3) jsr16-sem
8344 dst32-16-8-Unprefixed-HI (f-0-4 #xC) (f-7-1 1) (f-10-2 #x1) (f-12-4 #xF) jsr32-sem 3)
eda87aba
DD		 8345(jsri-defn w dst16-basic-HI (f-0-4 #x7) (f-4-4 #xD) (f-8-4 #x3) jsr16-sem
8346 dst32-basic-Unprefixed-HI (f-0-4 #xC) (f-7-1 1) (f-10-2 #x1) (f-12-4 #xF) jsr32-sem 2)
49f58d10
JB		 8347
8348; jsri.a (m16 #2 m32 #2)
75b06e7b
DD		 8349(jsri-defn a dst16-16-20ar-SI (f-0-4 #x7) (f-4-4 #xD) (f-8-4 #x1) jsr16-sem
8350 dst32-16-24-Unprefixed-SI (f-0-4 #x9) (f-7-1 0) (f-10-2 #x0) (f-12-4 #x1) jsr32-sem 4)
49f58d10
JB		 8351(jsri-defn a dst16-16-8-SI (f-0-4 #x7) (f-4-4 #xD) (f-8-4 #x1) jsr16-sem
8352 dst32-16-8-Unprefixed-SI (f-0-4 #x9) (f-7-1 0) (f-10-2 #x0) (f-12-4 #x1) jsr32-sem 3)
75b06e7b
DD		 8353(jsri-defn a dst16-16-16sa-SI (f-0-4 #x7) (f-4-4 #xD) (f-8-4 #x1) jsr16-sem
8354 dst32-16-16sa-Unprefixed-SI (f-0-4 #x9) (f-7-1 0) (f-10-2 #x0) (f-12-4 #x1) jsr32-sem 4)
eda87aba
DD		 8355(jsri-defn a dst16-basic-SI (f-0-4 #x7) (f-4-4 #xD) (f-8-4 #x1) jsr16-sem
8356 dst32-basic-Unprefixed-SI (f-0-4 #x9) (f-7-1 0) (f-10-2 #x0) (f-12-4 #x1) jsr32-sem 2)
8357
6772dd07 8358(dni jsri32.a "jsr.w dst32-16-24-Unprefixed-HI" (RL_1ADDR (machine 32))
75b06e7b 8359 ("jsri.a ${dst32-16-24-Unprefixed-SI}")
49f58d10
JB		 8360 (+ (f-0-4 #x9) (f-7-1 0) dst32-16-24-Unprefixed-SI (f-10-2 #x0) (f-12-4 #x1))
8361 (jsr32-sem 6 dst32-16-24-Unprefixed-SI)
8362 ())
8363; jsr.w label16 (m32 #1)
6772dd07 8364(dni jsr32.w "jsr.w label" (RL_JUMP RELAXABLE (machine 32))
49f58d10
JB		 8365 ("jsr.w ${Lab-8-16}")
8366 (+ (f-0-4 #xC) (f-4-4 #xF) Lab-8-16)
8367 (jsr32-sem 3 Lab-8-16)
8368 ())
8369; jsr.a label16 (m32 #2)
6772dd07 8370(dni jsr32.a "jsr.a label" (RL_JUMP (machine 32))
49f58d10
JB		 8371 ("jsr.a ${Lab-8-24}")
8372 (+ (f-0-4 #xC) (f-4-4 #xD) Lab-8-24)
8373 (jsr32-sem 4 Lab-8-24)
8374 ())
8375; jsrs imm8 (m16 #1)
8376(dni jsrs16 "jsrs Imm-8-QI" ((machine 16))
8377 ("jsrs #${Imm-8-QI}")
8378 (+ (f-0-4 #xE) (f-4-4 #xF) Imm-8-QI)
8379 (jsr16-sem 2 Imm-8-QI)
8380 ())
8381; jsrs imm8 (m32 #1)
8382(dni jsrs "jsrs #Imm-8-QI" ((machine 32))
8383 ("jsrs #${Imm-8-QI}")
8384 (+ (f-0-4 #xD) (f-4-4 #xD) Imm-8-QI)
8385 (jsr32-sem 2 Imm-8-QI)
8386 ())
8387
8388;-------------------------------------------------------------
8389; ldc - load control register
8390; stc - store control register
8391;-------------------------------------------------------------
8392
8393(define-pmacro (ldc32-cr1-sem src dst)
8394 (sequence ()
8395 (case DFLT dst
8396 ((#x0) (set (reg h-dct0) src))
8397 ((#x1) (set (reg h-dct1) src))
8398 ((#x2) (sequence ((HI tflag))
8399 (set tflag src)
8400 (if (and tflag #x1) (set cbit 1))
8401 (if (and tflag #x2) (set dbit 1))
8402 (if (and tflag #x4) (set zbit 1))
8403 (if (and tflag #x8) (set sbit 1))
8404 (if (and tflag #x10) (set bbit 1))
8405 (if (and tflag #x20) (set obit 1))
8406 (if (and tflag #x40) (set ibit 1))
8407 (if (and tflag #x80) (set ubit 1))))
8408 ((#x3) (set (reg h-svf) src))
8409 ((#x4) (set (reg h-drc0) src))
8410 ((#x5) (set (reg h-drc1) src))
8411 ((#x6) (set (reg h-dmd0) src))
8412 ((#x7) (set (reg h-dmd1) src))
8413 )
8414 )
8415)
8416(define-pmacro (ldc32-cr2-sem src dst)
8417 (sequence ()
8418 (case DFLT dst
8419 ((#x0) (set (reg h-intb) src))
8420 ((#x1) (set (reg h-sp) src))
8421 ((#x2) (set (reg h-sb) src))
8422 ((#x3) (set (reg h-fb) src))
8423 ((#x4) (set (reg h-svp) src))
8424 ((#x5) (set (reg h-vct) src))
8425 ((#x7) (set (reg h-isp) src))
8426 )
8427 )
8428)
8429(define-pmacro (ldc32-cr3-sem src dst)
8430 (sequence ()
8431 (case DFLT dst
8432 ((#x2) (set (reg h-dma0) src))
8433 ((#x3) (set (reg h-dma1) src))
8434 ((#x4) (set (reg h-dra0) src))
8435 ((#x5) (set (reg h-dra1) src))
8436 ((#x6) (set (reg h-dsa0) src))
8437 ((#x7) (set (reg h-dsa1) src))
8438 )
8439 )
8440)
8441(define-pmacro (ldc16-sem src dst)
8442 (sequence ()
8443 (case DFLT dst
8444 ((#x1) (set (reg h-intb) src))
8445 ((#x2) (set (reg h-intb) (or (reg h-intb) (sll src (const 16)))))
8446 ((#x3) (sequence ((HI tflag))
8447 (set tflag src)
8448 (if (and tflag #x1) (set cbit 1))
8449 (if (and tflag #x2) (set dbit 1))
8450 (if (and tflag #x4) (set zbit 1))
8451 (if (and tflag #x8) (set sbit 1))
8452 (if (and tflag #x10) (set bbit 1))
8453 (if (and tflag #x20) (set obit 1))
8454 (if (and tflag #x40) (set ibit 1))
8455 (if (and tflag #x80) (set ubit 1))))
8456 ((#x4) (set (reg h-isp) src))
8457 ((#x5) (set (reg h-sp) src))
8458 ((#x6) (set (reg h-sb) src))
8459 ((#x7) (set (reg h-fb) src))
8460 )
8461 )
8462)
8463
8464(define-pmacro (stc32-cr1-sem src dst)
8465 (sequence ()
8466 (case DFLT src
8467 ((#x0) (set dst (reg h-dct0)))
8468 ((#x1) (set dst (reg h-dct1)))
8469 ((#x2) (sequence ((HI tflag))
8470 (set tflag 0)
8471 (if (eq cbit 1) (set tflag (or tflag #x1)))
8472 (if (eq dbit 1) (set tflag (or tflag #x2)))
8473 (if (eq zbit 1) (set tflag (or tflag #x4)))
8474 (if (eq sbit 1) (set tflag (or tflag #x8)))
8475 (if (eq bbit 1) (set tflag (or tflag #x10)))
8476 (if (eq obit 1) (set tflag (or tflag #x20)))
8477 (if (eq ibit 1) (set tflag (or tflag #x40)))
8478 (if (eq ubit 1) (set tflag (or tflag #x80)))
8479 (set dst tflag)))
8480 ((#x3) (set dst (reg h-svf)))
8481 ((#x4) (set dst (reg h-drc0)))
8482 ((#x5) (set dst (reg h-drc1)))
8483 ((#x6) (set dst (reg h-dmd0)))
8484 ((#x7) (set dst (reg h-dmd1)))
8485 )
8486 )
8487)
8488(define-pmacro (stc32-cr2-sem src dst)
8489 (sequence ()
8490 (case DFLT src
8491 ((#x0) (set dst (reg h-intb)))
8492 ((#x1) (set dst (reg h-sp)))
8493 ((#x2) (set dst (reg h-sb)))
8494 ((#x3) (set dst (reg h-fb)))
8495 ((#x4) (set dst (reg h-svp)))
8496 ((#x5) (set dst (reg h-vct)))
8497 ((#x7) (set dst (reg h-isp)))
8498 )
8499 )
8500)
8501(define-pmacro (stc32-cr3-sem src dst)
8502 (sequence ()
8503 (case DFLT src
8504 ((#x2) (set dst (reg h-dma0)))
8505 ((#x3) (set dst (reg h-dma1)))
8506 ((#x4) (set dst (reg h-dra0)))
8507 ((#x5) (set dst (reg h-dra1)))
8508 ((#x6) (set dst (reg h-dsa0)))
8509 ((#x7) (set dst (reg h-dsa1)))
8510 )
8511 )
8512)
8513(define-pmacro (stc16-sem src dst)
8514 (sequence ()
8515 (case DFLT src
8516 ((#x1) (set dst (and (reg h-intb) (const #xffff))))
8517 ((#x2) (set dst (srl (reg h-intb) (const 16))))
8518 ((#x3) (sequence ((HI tflag))
8519 (set tflag 0)
8520 (if (eq cbit 1) (set tflag (or tflag #x1)))
8521 (if (eq dbit 1) (set tflag (or tflag #x2)))
8522 (if (eq zbit 1) (set tflag (or tflag #x4)))
8523 (if (eq sbit 1) (set tflag (or tflag #x8)))
8524 (if (eq bbit 1) (set tflag (or tflag #x10)))
8525 (if (eq obit 1) (set tflag (or tflag #x20)))
8526 (if (eq ibit 1) (set tflag (or tflag #x40)))
8527 (if (eq ubit 1) (set tflag (or tflag #x80)))
8528 (set dst tflag)))
8529 ((#x4) (set dst (reg h-isp)))
8530 ((#x5) (set dst (reg h-sp)))
8531 ((#x6) (set dst (reg h-sb)))
8532 ((#x7) (set dst (reg h-fb)))
8533 )
8534 )
8535)
8536
8537(dni ldc16.imm16 "ldc #imm,dst" ((machine 16))
8538 ("ldc #${Imm-16-HI},${cr16}")
8539 (+ (f-0-4 #xE) (f-4-4 #xB) (f-8-1 0) (f-12-4 0) cr16 Imm-16-HI)
8540 (ldc16-sem Imm-16-HI cr16)
8541 ())
8542
8543(dni ldc16.dst "ldc src,dest" ((machine 16))
8544 ("ldc ${dst16-16-HI},${cr16}")
8545 (+ (f-0-4 7) (f-4-4 #xA) (f-8-1 1) cr16 dst16-16-HI)
8546 (ldc16-sem dst16-16-HI cr16)
8547 ())
8548; ldc src,dest (m32c #4)
8549(dni ldc32.src-cr1 "ldc src,dst" ((machine 32))
8550 ("ldc ${dst32-24-Prefixed-HI},${cr1-Prefixed-32}")
8551 (+ (f-0-4 0) (f-4-4 1) (f-8-4 #xD) dst32-24-Prefixed-HI (f-15-1 1) (f-18-2 0) (f-20-1 1) cr1-Prefixed-32)
8552 (ldc32-cr1-sem dst32-24-Prefixed-HI cr1-Prefixed-32)
8553 ())
8554; ldc src,dest (m32c #5)
8555(dni ldc32.src-cr2 "ldc src,dest" ((machine 32))
8556 ("ldc ${dst32-16-Unprefixed-SI},${cr2-32}")
8557 (+ (f-0-4 #xD) dst32-16-Unprefixed-SI (f-7-1 1) (f-10-2 0) (f-12-1 0) cr2-32)
8558 (ldc32-cr2-sem dst32-16-Unprefixed-SI cr2-32)
8559 ())
8560; ldc src,dest (m32c #6)
8561(dni ldc32.src-cr3 "ldc src,dst" ((machine 32))
8562 ("ldc ${dst32-24-Prefixed-SI},${cr3-Prefixed-32}")
8563 (+ (f-0-4 0) (f-4-4 1) (f-8-4 #xD) dst32-24-Prefixed-SI (f-15-1 1) (f-18-2 0) (f-20-1 0) cr3-Prefixed-32)
8564 (ldc32-cr3-sem dst32-24-Prefixed-SI cr3-Prefixed-32)
8565 ())
8566; ldc src,dest (m32c #1)
8567(dni ldc32.imm16-cr1 "ldc #imm,dst" ((machine 32))
8568 ("ldc #${Imm-16-HI},${cr1-Unprefixed-32}")
8569 (+ (f-0-4 #xD) (f-4-4 5) (f-8-4 #xA) (f-12-1 1) cr1-Unprefixed-32 Imm-16-HI)
8570 (ldc32-cr1-sem Imm-16-HI cr1-Unprefixed-32)
8571 ())
8572; ldc src,dest (m32c #2)
8573(dni ldc32.imm16-cr2 "ldc #imm,dst" ((machine 32))
8574 ("ldc #${Dsp-16-u24},${cr2-32}")
8575 (+ (f-0-4 #xD) (f-4-4 5) (f-8-4 2) (f-12-1 1) cr2-32 Dsp-16-u24)
8576 (ldc32-cr2-sem Dsp-16-u24 cr2-32)
8577 ())
8578; ldc src,dest (m32c #3)
8579(dni ldc32.imm16-cr3 "ldc #imm,dst" ((machine 32))
8580 ("ldc #${Dsp-16-u24},${cr3-Unprefixed-32}")
8581 (+ (f-0-4 #xD) (f-4-4 5) (f-8-4 6) (f-12-1 1) cr3-Unprefixed-32 Dsp-16-u24)
8582 (ldc32-cr3-sem Dsp-16-u24 cr3-Unprefixed-32)
8583 ())
8584
8585(dni stc16.src "stc src,dest" ((machine 16))
8586 ("stc ${cr16},${dst16-16-HI}")
8587 (+ (f-0-4 7) (f-4-4 #xB) (f-8-1 1) cr16 dst16-16-HI)
8588 (stc16-sem cr16 dst16-16-HI )
8589 ())
8590
8591(dni stc16.pc "stc pc,dest" ((machine 16))
8592 ("stc pc,${dst16-16-HI}")
8593 (+ (f-0-4 7) (f-4-4 #xC) (f-8-4 #xC) dst16-16-HI)
8594 (sequence () (set dst16-16-HI (reg h-pc)))
8595 ())
8596
8597(dni stc32.src-cr1 "stc src,dst" ((machine 32))
8598 ("stc ${cr1-Prefixed-32},${dst32-24-Prefixed-HI}")
8599 (+ (f-0-4 0) (f-4-4 1) (f-8-4 #xD) dst32-24-Prefixed-HI (f-15-1 1) (f-18-2 1) (f-20-1 1) cr1-Prefixed-32)
8600 (stc32-cr1-sem cr1-Prefixed-32 dst32-24-Prefixed-HI )
8601 ())
8602
8603(dni stc32.src-cr2 "stc src,dest" ((machine 32))
8604 ("stc ${cr2-32},${dst32-16-Unprefixed-SI}")
8605 (+ (f-0-4 #xD) dst32-16-Unprefixed-SI (f-7-1 1) (f-10-2 0) (f-12-1 2) cr2-32)
8606 (stc32-cr2-sem cr2-32 dst32-16-Unprefixed-SI )
8607 ())
8608
8609(dni stc32.src-cr3 "stc src,dst" ((machine 32))
8610 ("stc ${cr3-Prefixed-32},${dst32-24-Prefixed-SI}")
8611 (+ (f-0-4 0) (f-4-4 1) (f-8-4 #xD) dst32-24-Prefixed-SI (f-15-1 1) (f-18-2 1) (f-20-1 0) cr3-Prefixed-32)
8612 (stc32-cr3-sem cr3-Prefixed-32 dst32-24-Prefixed-SI )
8613 ())
8614
8615;-------------------------------------------------------------
8616; ldctx - load context
8617; stctx - store context
8618;-------------------------------------------------------------
8619
8620; ??? semantics
8621(dni ldctx16 "ldctx abs16,abs24" ((machine 16))
8622 ("ldctx ${Dsp-16-u16},${Dsp-32-u24}")
8623 (+ (f-0-4 #x7) (f-4-4 #xC) (f-8-4 #xF) (f-12-4 #x0) Dsp-16-u16 Dsp-32-u24)
8624 (nop)
8625 ())
8626(dni ldctx32 "ldctx abs16,abs24" ((machine 32))
8627 ("ldctx ${Dsp-16-u16},${Dsp-32-u24}")
8628 (+ (f-0-4 #xB) (f-4-4 #x6) (f-8-4 #xC) (f-12-4 #x3) Dsp-16-u16 Dsp-32-u24)
8629 (nop)
8630 ())
8631(dni stctx16 "stctx abs16,abs24" ((machine 16))
8632 ("stctx ${Dsp-16-u16},${Dsp-32-u24}")
8633 (+ (f-0-4 #x7) (f-4-4 #xD) (f-8-4 #xF) (f-12-4 #x0) Dsp-16-u16 Dsp-32-u24)
8634 (nop)
8635 ())
8636(dni stctx32 "stctx abs16,abs24" ((machine 32))
8637 ("stctx ${Dsp-16-u16},${Dsp-32-u24}")
8638 (+ (f-0-4 #xB) (f-4-4 #x6) (f-8-4 #xD) (f-12-4 #x3) Dsp-16-u16 Dsp-32-u24)
8639 (nop)
8640 ())
8641
8642;-------------------------------------------------------------
8643; lde - load from extra far data area (m16)
8644; ste - store to extra far data area (m16)
8645;-------------------------------------------------------------
8646
a1a280bb
DD		 8647(lde-dst QI .b 0)
8648(lde-dst HI .w 1)
49f58d10 8649
a1a280bb
DD		 8650(ste-dst QI .b 0)
8651(ste-dst HI .w 1)
49f58d10
JB		 8652
8653;-------------------------------------------------------------
8654; ldipl - load interrupt permission level
8655;-------------------------------------------------------------
8656
8657; ??? semantics
8658; ldintb <==> ldc #imm,intbh ; ldc #imm,intbl
8d0e2679 8659
49f58d10
JB		 8660(dni ldipl16.imm "ldipl #imm" ((machine 16))
8661 ("ldipl #${Imm-13-u3}")
8662 (+ (f-0-4 #x7) (f-4-4 #xD) (f-8-4 #xA) (f-12-1 0) Imm-13-u3)
8663 (nop)
8664 ())
8665(dni ldipl32.imm "ldipl #imm" ((machine 32))
8666 ("ldipl #${Imm-13-u3}")
8667 (+ (f-0-4 #xD) (f-4-4 5) (f-8-4 #xE) (f-12-1 1) Imm-13-u3)
8668 (nop)
8669 ())
8670
8671
8672;-------------------------------------------------------------
8673; max - maximum value
8674;-------------------------------------------------------------
8675
8676; TODO check semantics for min -1,0
8677(define-pmacro (max-sem mode src dst)
8678 (sequence ()
8679 (if (gt mode src dst)
8680 (set mode dst src)))
8681)
8682
8683; max.size:G #imm,dst
8684(binary-arith32-imm-dst-Prefixed QI QI .b 0 max X #x8 #x3 #xF max-sem)
8685(binary-arith32-imm-dst-Prefixed HI HI .w 1 max X #x8 #x3 #xF max-sem)
8686
8687; max.BW:G src,dst
8688(binary-arith32-src-dst-Prefixed QI QI .b 0 max X #x1 #xD max-sem)
8689(binary-arith32-src-dst-Prefixed HI HI .w 1 max X #x1 #xD max-sem)
8690
8691;-------------------------------------------------------------
8692; min - minimum value
8693;-------------------------------------------------------------
8694
8695(define-pmacro (min-sem mode src dst)
8696 (sequence ()
8697 (if (lt mode src dst)
8698 (set mode dst src)))
8699)
8700
8701; min.size:G #imm,dst
8702(binary-arith32-imm-dst-Prefixed QI QI .b 0 min X #x8 #x2 #xF min-sem)
8703(binary-arith32-imm-dst-Prefixed HI HI .w 1 min X #x8 #x2 #xF min-sem)
8704
8705; min.BW:G src,dst
8706(binary-arith32-src-dst-Prefixed QI QI .b 0 min X #x1 #xC min-sem)
8707(binary-arith32-src-dst-Prefixed HI HI .w 1 min X #x1 #xC min-sem)
8708
8709;-------------------------------------------------------------
8710; mov - move
8711;-------------------------------------------------------------
8712
8713(define-pmacro (mov-sem mode src1 dst)
8714 (sequence ((mode result))
8715 (set result src1)
8716 (set-z-and-s result)
8717 (set mode dst src1))
8718)
8719
8720(define-pmacro (mov-dspsp-dst-sem mach mode src1 dst)
8721 (set dst (mem-mach mach mode (add sp src1)))
8722)
8723
8724(define-pmacro (mov-src-dspsp-sem mach mode src dst1)
8725 (set (mem-mach mach mode (add sp dst1)) src)
8726)
8727
8728(define-pmacro (mov16-imm-an-defn size mode imm regn op1 op2)
8729 (dni (.sym mov16. size .S-imm- regn)
8730 (.str "mov." size ":S " imm "," regn)
8731 ((machine 16))
8732 (.str "mov." size "$S #${" imm "}," regn)
8733 (+ op1 op2 imm)
8734 (mov-sem mode imm (reg (.sym h- regn)))
8735 ())
8736)
8737; mov.size:G #imm,dst (m16 #1 m32 #1)
8738(binary-arith-imm-dst mov G (f-0-4 7) (f-4-3 2) (f-8-4 #xC) #x9 #x2 #xF mov-sem)
8739; mov.L:G #imm32,dst (m32 #2)
8740(binary-arith32-imm-dst-defn SI SI .l 0 mov G #xB #x3 #x1 mov-sem)
49f58d10
JB		 8741; mov.BW:S #imm,dst2 (m32 #4)
8742(binary-arith32-s-imm-dst QI .b 0 mov #x0 #x2 mov-sem)
8743(binary-arith32-s-imm-dst HI .w 1 mov #x0 #x2 mov-sem)
8744; mov.b:S #imm8,dst3 (m16 #3)
8745(binary-arith16-b-S-imm8-dst3 mov ".b" (f-0-4 #xC) (f-4-1 0) mov-sem)
8746; mov.b:S #imm8,aN (m16 #4)
8747(mov16-imm-an-defn b QI Imm-8-QI a0 (f-0-4 #xE) (f-4-4 2))
8748(mov16-imm-an-defn b QI Imm-8-QI a1 (f-0-4 #xE) (f-4-4 #xA))
8749(mov16-imm-an-defn w HI Imm-8-HI a0 (f-0-4 #xA) (f-4-4 2))
8750(mov16-imm-an-defn w HI Imm-8-HI a1 (f-0-4 #xA) (f-4-4 #xA))
8751; mov.WL:S #imm,A0/A1 (m32 #5)
8752(define-pmacro (mov32-wl-s-defn mode sz op1 imm regn op2)
8753 (dni (.sym mov32- sz - regn)
8754 (.str "mov." sz ":s" imm "," regn)
8755 ((machine 32))
8756 (.str "mov." sz "$S #${" imm "}," regn)
8757 (+ (f-0-4 op1) (f-4-4 op2) imm)
8758 (mov-sem mode imm (reg (.sym h- regn)))
8759 ())
8760)
8761(mov32-wl-s-defn HI w #x9 Imm-8-HI a0 #xC)
8762(mov32-wl-s-defn HI w #x9 Imm-8-HI a1 #xD)
f75eb1c0
DD		 8763(mov32-wl-s-defn SI l #xB Dsp-8-s24 a0 #xC)
8764(mov32-wl-s-defn SI l #xB Dsp-8-s24 a1 #xD)
e729279b
NC		 8765
8766; mov.size:Q #imm4,dst (m16 #2 m32 #3)
8767(binary-arith16-imm4-dst-defn QI .b 0 0 mov (f-0-4 #xD) (f-4-3 4) mov-sem)
458f7770 8768(binary-arith16-imm4-dst-defn HI .w 0 1 mov (f-0-4 #xD) (f-4-3 4) mov-sem)
e729279b
NC		 8769(binary-arith32-imm4-dst-defn QI .b 1 0 mov #x7 #x2 mov-sem)
8770(binary-arith32-imm4-dst-defn HI .w 1 1 mov #x7 #x2 mov-sem)
49f58d10
JB		 8771
8772; mov.BW:Z #0,dst (m16 #5 m32 #6)
8773(dni mov16.b-Z-imm8-dst3
8774 "mov.b:Z #0,Dst16-3-S-8"
8775 ((machine 16))
8776 "mov.b$Z #0,${Dst16-3-S-8}"
8777 (+ (f-0-4 #xB) (f-4-1 #x0) Dst16-3-S-8)
8778 (mov-sem QI (const 0) Dst16-3-S-8)
8779 ())
8780; (binary-arith16-b-Z-imm8-dst3 mov ".b" (f-0-4 #xB) (f-4-1 0) mov-sem)
8781(binary-arith32-z-imm-dst QI .b 0 mov #x0 #x1 mov-sem)
8782(binary-arith32-z-imm-dst HI .w 1 mov #x0 #x1 mov-sem)
8783; mov.BW:G src,dst (m16 #6 m32 #7)
8784(binary-arith-src-dst mov G (f-0-4 #x7) (f-4-3 1) #x1 #xB mov-sem)
8785; mov.B:S src2,a0/a1 (m16 #7)
8786(dni (.sym mov 16 .b.S-An)
8787 (.str mov ".b:S src2,a[01]")
8788 ((machine 16))
8789 (.str mov ".b$S ${src16-2-S},${Dst16AnQI-S}")
8790 (+ (f-0-4 #x3) (f-4-1 0) Dst16AnQI-S src16-2-S)
8791 (mov-sem QI src16-2-S Dst16AnQI-S)
8792 ())
8793(define-pmacro (mov16-b-s-an-defn op1 op2 op2c)
8794 (dni (.sym mov16.b.S- op1 - op2)
8795 (.str mov ".b:S " op1 "," op2)
8796 ((machine 16))
8797 (.str mov ".b$S " op1 "," op2)
8798 (+ (f-0-4 #x3) op2c)
8799 (mov-sem QI (reg (.sym h- op1)) (reg (.sym h- op2)))
8800 ())
8801 )
8802(mov16-b-s-an-defn r0l a1 (f-4-4 #x4))
8803(mov16-b-s-an-defn r0h a0 (f-4-4 #x0))
8804
8805; mov.L:G src,dst (m32 #8)
8806(binary-arith32-src-dst-defn SI SI .l 1 mov G #x1 #x3 mov-sem)
8807; mov.B:S r0l/r0h,dst2 (m16 #8)
8808(dni (.sym mov 16 .b.S-Rn-An)
8809 (.str mov ".b:S r0[lh],src2")
8810 ((machine 16))
8811 (.str mov ".b$S ${Dst16RnQI-S},${src16-2-S}")
8812 (+ (f-0-4 #x0) (f-4-1 0) Dst16RnQI-S src16-2-S)
8813 (mov-sem QI src16-2-S Dst16RnQI-S)
8814 ())
8815
8816; mov.B.S src2,r0l/r0h (m16 #9)
8817(binary-arith16-b-S-src2 mov (f-0-4 0) (f-4-1 1) mov-sem)
8818
8819; mov.BW:S src2,r0l/r0 (m32 #9)
8820; mov.BW:S src2,r1l/r1 (m32 #10)
8821(define-pmacro (mov32-src-r sz szcode mode src dst opc1 opc2)
8822 (begin
8823 (dni (.sym mov32. sz - src - dst)
8824 (.str "mov." sz "src," dst)
8825 ((machine 32))
8826 (.str "mov." sz "$S ${" (.sym src - mode) "}," dst)
8827 (+ (f-0-2 opc1) (.sym src - mode) (f-4-3 opc2) (f-7-1 szcode))
8828 (mov-sem mode (.sym src - mode) (reg (.sym h- dst)))
8829 ())
8830 )
8831 )
8832(mov32-src-r b 0 QI dst32-2-S-16 r0l 0 4)
8833(mov32-src-r w 1 HI dst32-2-S-16 r0 0 4)
8834(mov32-src-r b 0 QI dst32-2-S-8 r0l 0 4)
8835(mov32-src-r w 1 HI dst32-2-S-8 r0 0 4)
8836(mov32-src-r b 0 QI dst32-2-S-basic r1l 1 7)
f75eb1c0 8837(mov32-src-r w 1 HI dst32-2-S-basic r1 1 7)
49f58d10
JB		 8838(mov32-src-r b 0 QI dst32-2-S-16 r1l 1 7)
8839(mov32-src-r w 1 HI dst32-2-S-16 r1 1 7)
8840(mov32-src-r b 0 QI dst32-2-S-8 r1l 1 7)
8841(mov32-src-r w 1 HI dst32-2-S-8 r1 1 7)
8842
8843; mov.BW:S r0l/r0,dst2 (m32 #11)
8844(define-pmacro (mov32-r-dest sz szcode mode src dst opc1 opc2)
8845 (begin
8846 (dni (.sym mov32. sz - src - dst)
8847 (.str "mov." sz "src," dst)
8848 ((machine 32))
8849 (.str "mov." sz "$S " src ",${" (.sym dst - mode) "}")
8850 (+ (f-0-2 opc1) (.sym dst - mode) (f-4-3 opc2) (f-7-1 szcode))
8851 (mov-sem mode (reg (.sym h- src)) (.sym dst - mode))
8852 ())
8853 )
8854 )
8855(mov32-r-dest b 0 QI r0l dst32-2-S-16 0 0)
8856(mov32-r-dest w 1 HI r0 dst32-2-S-16 0 0)
8857(mov32-r-dest b 0 QI r0l dst32-2-S-8 0 0)
8858(mov32-r-dest w 1 HI r0 dst32-2-S-8 0 0)
8859
8860; mov.L:S src,A0/A1 (m32 #12)
8861(define-pmacro (mov32-src-a src dst dstcode opc1 opc2)
8862 (begin
8863 (dni (.sym mov32. sz - src - dst)
8864 (.str "mov." sz "src," dst)
8865 ((machine 32))
8866 (.str "mov.l" "$S ${" (.sym src - SI) "}," dst)
8867 (+ (f-0-2 opc1) (.sym src - SI) (f-4-3 opc2) (f-7-1 dstcode))
8868 (mov-sem SI (.sym src - SI) (reg (.sym h- dst)))
8869 ())
8870 )
8871 )
8872(mov32-src-a dst32-2-S-16 a0 0 1 4)
8873(mov32-src-a dst32-2-S-16 a1 1 1 4)
8874(mov32-src-a dst32-2-S-8 a0 0 1 4)
8875(mov32-src-a dst32-2-S-8 a1 1 1 4)
8876
8877; mov.BW:G dsp8[sp],dst (m16 #10 m32 #13)
8878; mov.BW:G src,dsp8[sp] (m16 #11 m32 #14)
8879(mov-dspsp-dst mov (f-0-4 #x7) (f-4-3 2) (f-8-4 #xB) #xB #x0 #xF mov-dspsp-dst-sem)
8880(mov-src-dspsp mov (f-0-4 #x7) (f-4-3 2) (f-8-4 #x3) #xA #x0 #xF mov-src-dspsp-sem)
8881
8882;-------------------------------------------------------------
8883; mova - move effective address
8884;-------------------------------------------------------------
8885
8886(define-pmacro (mov16a-defn dst dstop dstcode)
8887 (dni (.sym mova16. src - dst)
8888 (.str "mova src," dst)
8889 ((machine 16))
8890 (.str "mova ${dst16-16-Mova-HI}," dst)
8891 (+ (f-0-4 #xE) (f-4-4 #xB) dst16-16-Mova-HI (f-8-4 dstcode))
8892 (sequence () (set HI (reg dstop) dst16-16-Mova-HI))
8893 ())
8894)
8895(mov16a-defn r0 h-r0 0)
8896(mov16a-defn r1 h-r1 1)
8897(mov16a-defn r2 h-r2 2)
8898(mov16a-defn r3 h-r3 3)
8899(mov16a-defn a0 h-a0 4)
8900(mov16a-defn a1 h-a1 5)
8901
8902(define-pmacro (mov32a-defn dst dstop dstcode)
8903 (dni (.sym mova32. src - dst)
8904 (.str "mova src," dst)
8905 ((machine 32))
8906 (.str "mova ${dst32-16-Unprefixed-Mova-SI}," dst)
8907 (+ (f-0-4 #xD) dst32-16-Unprefixed-Mova-SI (f-7-1 1) (f-10-2 1) (f-12-1 1) (f-13-3 dstcode))
8908 (sequence () (set SI (reg dstop) dst32-16-Unprefixed-Mova-SI))
8909 ())
8910)
8911(mov32a-defn r2r0 h-r2r0 0)
8912(mov32a-defn r3r1 h-r3r1 1)
8913(mov32a-defn a0 h-a0 2)
8914(mov32a-defn a1 h-a1 3)
8915
8916;-------------------------------------------------------------
8917; movDir - move nibble
8918;-------------------------------------------------------------
8919
8920(define-pmacro (movdir-sem nib src dst)
8921 (sequence ((SI tmp))
8922 (case DFLT nib
8923 ((0) (set dst (or (and dst #xf0) (and src #xf))))
8924 ((1) (set dst (or (and dst #x0f) (sll (and src #xf) 4))))
8925 ((2) (set dst (or (and dst #xf0) (srl (and src #xf0) 4))))
8926 ((3) (set dst (or (and dst #x0f) (and src #xf0))))
8927 )
8928 )
8929 )
8930; movDir src,dst
8931(define-pmacro (mov16dir-1-defn nib dircode dir)
8932 (dni (.sym mov nib 16 ".r0l-dst")
8933 (.str "mov" nib " r0l,dst")
8934 ((machine 16))
8935 (.str "mov" nib " r0l,${dst16-16-QI}")
8936 (+ (f-0-4 7) (f-4-4 #xC) (f-8-4 dir) dst16-16-QI)
8937 (movdir-sem dircode (reg h-r0l) dst16-16-QI)
8938 ())
8939)
8940(mov16dir-1-defn ll 0 8)
8941(mov16dir-1-defn lh 1 #xA)
8942(mov16dir-1-defn hl 2 9)
8943(mov16dir-1-defn hh 3 #xB)
8944(define-pmacro (mov16dir-2-defn nib dircode dir)
8945 (dni (.sym mov nib 16 ".src-r0l")
8946 (.str "mov" nib " src,r0l")
8947 ((machine 16))
8948 (.str "mov" nib " ${dst16-16-QI},r0l")
8949 (+ (f-0-4 7) (f-4-4 #xC) (f-8-4 dir) dst16-16-QI)
8950 (movdir-sem dircode dst16-16-QI (reg h-r0l))
8951 ())
8952)
8953(mov16dir-2-defn ll 0 0)
8954(mov16dir-2-defn lh 1 2)
8955(mov16dir-2-defn hl 2 1)
8956(mov16dir-2-defn hh 3 3)
8957
8958(define-pmacro (mov32dir-1-defn nib o1o0)
8959 (dni (.sym mov nib 32 ".r0l-dst")
8960 (.str "mov" nib " r0l,dst")
8961 ((machine 32))
8962 (.str "mov" nib " r0l,${dst32-24-Prefixed-QI}")
8963 (+ (f-0-4 #x0) (f-4-4 #x1) (f-8-4 #xB) dst32-24-Prefixed-QI (f-15-1 0) (f-18-2 o1o0) (f-20-4 #xE))
8964 (movdir-sem o1o0 (reg h-r0l) dst32-24-Prefixed-QI)
8965 ())
8966)
8967(mov32dir-1-defn ll 0)
8968(mov32dir-1-defn lh 1)
8969(mov32dir-1-defn hl 2)
8970(mov32dir-1-defn hh 3)
8971(define-pmacro (mov32dir-2-defn nib o1o0)
8972 (dni (.sym mov nib 32 ".src-r0l")
8973 (.str "mov" nib " src,r0l")
8974 ((machine 32))
8975 (.str "mov" nib " ${dst32-24-Prefixed-QI},r0l")
8976 (+ (f-0-4 #x0) (f-4-4 #x1) (f-8-4 #xA) dst32-24-Prefixed-QI (f-15-1 0) (f-18-2 o1o0) (f-20-4 #xE))
8977 (movdir-sem o1o0 dst32-24-Prefixed-QI (reg h-r0l))
8978 ())
8979)
8980(mov32dir-2-defn ll 0)
8981(mov32dir-2-defn lh 1)
8982(mov32dir-2-defn hl 2)
8983(mov32dir-2-defn hh 3)
8984
8985;-------------------------------------------------------------
8986; movx - move extend sign (m32)
8987;-------------------------------------------------------------
8988
8989(define-pmacro (movx-sem mode src dst)
8990 (sequence ((SI source) (SI result))
8991 (set SI result src)
8992 (set-z-and-s result)
8993 (set dst result))
8994)
8995
8996; movx #imm,dst
8997(binary-arith32-imm-dst-defn QI SI "" 0 movx X #xB #x1 #x1 movx-sem)
8998
8999;-------------------------------------------------------------
9000; mul - multiply
9001;-------------------------------------------------------------
9002
9003(define-pmacro (mul-sem mode src1 dst)
9004 (sequence ((mode result))
9005 (set obit (add-oflag mode src1 dst 0))
9006 (set result (mul mode src1 dst))
9007 (set dst result))
9008)
9009
9010; mul.BW #imm,dst
9011(binary-arith-imm-dst mul G (f-0-4 7) (f-4-3 6) (f-8-4 5) #x8 #x1 #xF mul-sem)
9012; mul.BW src,dst
9013(binary-arith-src-dst mul G (f-0-4 #x7) (f-4-3 4) #x1 #xC mul-sem)
9014
253d272c
DD		 9015(dni mul_l "mul.l src,r2r0" ((machine 32))
9016 ("mul.l ${dst32-24-Prefixed-SI},r2r0")
9017 (+ (f-0-4 #x0) (f-4-4 #x1) (f-8-4 #x8) (f-15-1 #x1) (f-18-2 #x1) (f-20-4 #xf)
9018 dst32-24-Prefixed-SI)
9019 () ())
9020
9021(dni mulu_l "mulu.l src,r2r0" ((machine 32))
9022 ("mulu.l ${dst32-24-Prefixed-SI},r2r0")
9023 (+ (f-0-4 #x0) (f-4-4 #x1) (f-8-4 #x8) (f-15-1 #x1) (f-18-2 #x0) (f-20-4 #xf)
9024 dst32-24-Prefixed-SI)
9025 () ())
49f58d10
JB		 9026;-------------------------------------------------------------
9027; mulex - multiple extend sign (m32)
9028;-------------------------------------------------------------
9029
9030; mulex src,dst
9031; (dni mulex-absolute-indirect "mulex [src]" ((machine 32))
9032; ("mulex ${dst32-24-absolute-indirect-HI}")
9033; (+ (f-0-4 0) (f-4-4 9) (f-8-4 #xC) dst32-24-absolute-indirect-HI (f-15-1 1) (f-18-2 3) (f-20-4 #xE))
9034; (set R1R2R0 (mul DI (ext DI R2R0) (ext DI dst32-24-absolute-indirect-HI)))
9035; ())
9036(dni mulex "mulex src" ((machine 32))
9037 ("mulex ${dst32-16-Unprefixed-Mulex-HI}")
9038 (+ (f-0-4 #xC) dst32-16-Unprefixed-Mulex-HI (f-7-1 1) (f-10-2 3) (f-12-4 #xE))
9039 (set R1R2R0 (mul DI (ext DI R2R0) (ext DI dst32-16-Unprefixed-Mulex-HI)))
9040 ())
9041; (dni mulex-indirect "mulex [src]" ((machine 32))
9042; ("mulex ${dst32-24-indirect-HI}")
9043; (+ (f-0-4 0) (f-4-4 9) (f-8-4 #xC) dst32-24-indirect-HI (f-15-1 1) (f-18-2 3) (f-20-4 #xE))
9044; (set R1R2R0 (mul DI (ext DI R2R0) (ext DI dst32-24-indirect-HI)))
9045; ())
9046
9047;-------------------------------------------------------------
9048; mulu - multiply unsigned
9049;-------------------------------------------------------------
9050
9051(define-pmacro (mulu-sem mode src1 dst)
9052 (sequence ((mode result))
9053 (set obit (add-oflag mode src1 dst 0))
9054 (set result (mul mode src1 dst))
9055 (set dst result))
9056)
9057
9058; mulu.BW #imm,dst
9059(binary-arith-imm-dst mulu G (f-0-4 7) (f-4-3 6) (f-8-4 4) #x8 #x0 #xF mulu-sem)
9060; mulu.BW src,dst
9061(binary-arith-src-dst mulu G (f-0-4 #x7) (f-4-3 0) #x1 #x4 mulu-sem)
9062
9063;-------------------------------------------------------------
9064; neg - twos complement
9065;-------------------------------------------------------------
9066
9067(define-pmacro (neg-sem mode dst)
9068 (sequence ((mode result))
9069 (set result (neg mode dst))
9070 (set-z-and-s result)
9071 (set dst result))
9072)
9073
9074; neg.BW:G
9075(unary-insn neg (f-0-4 7) (f-4-3 2) (f-8-4 #x5) #xA #x2 #xF neg-sem)
9076
9077;-------------------------------------------------------------
9078; not - twos complement
9079;-------------------------------------------------------------
9080
9081(define-pmacro (not-sem mode dst)
9082 (sequence ((mode result))
9083 (set result (not mode dst))
9084 (set-z-and-s result)
9085 (set dst result))
9086)
9087
9088; not.BW:G
c6552317
DD		 9089(unary-insn-g not (f-0-4 7) (f-4-3 2) (f-8-4 #x7) #xA #x1 #xE not-sem)
9090
9091(dni not16.b.s
9092 "not.b:s Dst16-3-S-8"
9093 ((machine 16))
9094 "not.b:s ${Dst16-3-S-8}"
9095 (+ (f-0-4 #xb) (f-4-1 #x1) Dst16-3-S-8)
9096 (not-sem QI Dst16-3-S-8)
9097 ())
49f58d10
JB		 9098
9099;-------------------------------------------------------------
9100; nop
9101;-------------------------------------------------------------
9102
9103(dni nop16
9104 "nop"
9105 ((machine 16))
9106 "nop"
9107 (+ (f-0-4 #x0) (f-4-4 #x4))
9108 (nop)
9109 ())
9110
9111(dni nop32
9112 "nop"
9113 ((machine 32))
9114 "nop"
9115 (+ (f-0-4 #xD) (f-4-4 #xE))
9116 (nop)
9117 ())
9118
9119;-------------------------------------------------------------
9120; or - logical or
9121;-------------------------------------------------------------
9122
9123(define-pmacro (or-sem mode src1 dst)
9124 (sequence ((mode result))
9125 (set result (or mode src1 dst))
9126 (set-z-and-s result)
9127 (set dst result))
9128)
9129
9130; or.BW #imm,dst (m16 #1 m32 #1)
9131(binary-arith-imm-dst or G (f-0-4 7) (f-4-3 3) (f-8-4 3) #x8 #x2 #xF or-sem)
9132; or.b:S #imm8,dst3 (m16 #2 m32 #2)
9133(binary-arith16-b-S-imm8-dst3 or ".b" (f-0-4 9) (f-4-1 1) or-sem)
9134(binary-arith32-s-imm-dst QI .b 0 or #x1 #x2 or-sem)
9135(binary-arith32-s-imm-dst HI .w 1 or #x1 #x2 or-sem)
9136; or.BW src,dst (m16 #3 m32 #3)
9137(binary-arith-src-dst or G (f-0-4 #x9) (f-4-3 4) #x1 #x5 or-sem)
8d0e2679
DD		 9138; or.b:S src,r0[lh] (m16)
9139(binary-arith16-b-S-src2 or (f-0-4 1) (f-4-1 1) or-sem)
49f58d10
JB		 9140
9141;-------------------------------------------------------------
9142; pop - restore register/memory
9143;-------------------------------------------------------------
9144
9145; TODO future: split this into .b and .w semantics
9146(define-pmacro (pop-sem-mach mach mode dst)
9147 (sequence ((mode b_or_w) (SI length))
9148 (set b_or_w -1)
9149 (set b_or_w (srl b_or_w #x8))
9150 (if (eq b_or_w #x0)
9151 (set length 1) ; .b
9152 (set length 2)) ; .w
9153
9154 (case DFLT length
9155 ((1) (set dst (mem-mach mach QI (reg h-sp))))
9156 ((2) (set dst (mem-mach mach HI (reg h-sp)))))
9157 (set (reg h-sp) (add (reg h-sp) length))
9158 )
9159)
9160
9161(define-pmacro (pop-sem16 mode dest) (pop-sem-mach 16 mode dest))
9162(define-pmacro (pop-sem32 mode dest) (pop-sem-mach 32 mode dest))
9163
9164; pop.BW:G (m16 #1)
8d0e2679 9165(unary-insn-mach-g 16 pop (f-0-4 7) (f-4-3 2) (f-8-4 #xD) pop-sem16 $G)
49f58d10
JB		 9166; pop.BW:G (m32 #1)
9167(unary-insn-mach 32 pop #xB #x2 #xF pop-sem32)
9168
9169; pop.b:S r0l/r0h
9170(dni pop16.b-s-rn "pop.b:S r0[lh]" ((machine 16))
9171 "pop.b$S ${Rn16-push-S-anyof}"
9172 (+ (f-0-4 #x9) Rn16-push-S-anyof (f-5-3 #x2))
9173 (pop-sem16 QI Rn16-push-S-anyof)
9174 ())
9175; pop.w:S a0/a1
9176(dni pop16.b-s-an "pop.w:S a[01]" ((machine 16))
9177 "pop.w$S ${An16-push-S-anyof}"
9178 (+ (f-0-4 #xD) An16-push-S-anyof (f-5-3 #x2))
9179 (pop-sem16 HI An16-push-S-anyof)
9180 ())
9181
9182;-------------------------------------------------------------
9183; popc - pop control register
9184; pushc - push control register
9185;-------------------------------------------------------------
9186
9187(define-pmacro (popc32-cr1-sem mode dst)
9188 (sequence ()
9189 (case DFLT dst
9190 ((#x0) (set (reg h-dct0) (mem32 mode (reg h-sp))))
9191 ((#x1) (set (reg h-dct1) (mem32 mode (reg h-sp))))
9192 ((#x2) (sequence ((HI tflag))
9193 (set tflag (mem32 mode (reg h-sp)))
9194 (if (and tflag #x1) (set cbit 1))
9195 (if (and tflag #x2) (set dbit 1))
9196 (if (and tflag #x4) (set zbit 1))
9197 (if (and tflag #x8) (set sbit 1))
9198 (if (and tflag #x10) (set bbit 1))
9199 (if (and tflag #x20) (set obit 1))
9200 (if (and tflag #x40) (set ibit 1))
9201 (if (and tflag #x80) (set ubit 1))))
9202 ((#x3) (set (reg h-svf) (mem32 mode (reg h-sp))))
9203 ((#x4) (set (reg h-drc0) (mem32 mode (reg h-sp))))
9204 ((#x5) (set (reg h-drc1) (mem32 mode (reg h-sp))))
9205 ((#x6) (set (reg h-dmd0) (mem32 mode (reg h-sp))))
9206 ((#x7) (set (reg h-dmd1) (mem32 mode (reg h-sp))))
9207 )
9208 (set (reg h-sp) (add (reg h-sp) 2))
9209 )
9210)
9211(define-pmacro (popc32-cr2-sem mode dst)
9212 (sequence ()
9213 (case DFLT dst
9214 ((#x0) (set (reg h-intb) (mem32 mode (reg h-sp))))
9215 ((#x1) (set (reg h-sp) (mem32 mode (reg h-sp))))
9216 ((#x2) (set (reg h-sb) (mem32 mode (reg h-sp))))
9217 ((#x3) (set (reg h-fb) (mem32 mode (reg h-sp))))
9218 ((#x7) (set (reg h-isp) (mem32 mode (reg h-sp))))
9219 )
9220 (set (reg h-sp) (add (reg h-sp) 4))
9221 )
9222)
9223(define-pmacro (popc16-sem mode dst)
9224 (sequence ()
9225 (case DFLT dst
9226 ((#x1) (set (reg h-intb) (or (and (reg h-intb) #x0000)
9227 (mem16 mode (reg h-sp)))))
9228 ((#x2) (set (reg h-intb) (or (and (reg h-intb) #xffff0000)
9229 (mem16 mode (reg h-sp)))))
9230 ((#x3) (sequence ((HI tflag))
9231 (set tflag (mem16 mode (reg h-sp)))
9232 (if (and tflag #x1) (set cbit 1))
9233 (if (and tflag #x2) (set dbit 1))
9234 (if (and tflag #x4) (set zbit 1))
9235 (if (and tflag #x8) (set sbit 1))
9236 (if (and tflag #x10) (set bbit 1))
9237 (if (and tflag #x20) (set obit 1))
9238 (if (and tflag #x40) (set ibit 1))
9239 (if (and tflag #x80) (set ubit 1))))
9240 ((#x4) (set (reg h-isp) (mem16 mode (reg h-sp))))
9241 ((#x5) (set (reg h-sp) (mem16 mode (reg h-sp))))
9242 ((#x6) (set (reg h-sb) (mem16 mode (reg h-sp))))
9243 ((#x7) (set (reg h-fb) (mem16 mode (reg h-sp))))
9244 )
9245 (set (reg h-sp) (add (reg h-sp) 2))
9246 )
9247)
9248; popc dest (m16c #1)
9249(dni popc16.imm16 "popc dst" ((machine 16))
9250 ("popc ${cr16}")
9251 (+ (f-0-4 #xE) (f-4-4 #xB) (f-8-1 0) (f-12-4 3) cr16)
9252 (popc16-sem HI cr16)
9253 ())
9254; popc dest (m32c #1)
9255(dni popc32.imm16-cr1 "popc dst" ((machine 32))
9256 ("popc ${cr1-Unprefixed-32}")
9257 (+ (f-0-4 #xD) (f-4-4 3) (f-8-4 #xA) (f-12-1 1) cr1-Unprefixed-32)
9258 (popc32-cr1-sem HI cr1-Unprefixed-32)
9259 ())
9260; popc dest (m32c #2)
9261(dni popc32.imm16-cr2 "popc dst" ((machine 32))
9262 ("popc ${cr2-32}")
9263 (+ (f-0-4 #xD) (f-4-4 3) (f-8-4 2) (f-12-1 1) cr2-32)
9264 (popc32-cr2-sem SI cr2-32)
9265 ())
9266
9267(define-pmacro (pushc32-cr1-sem mode dst)
9268 (sequence ()
9269 (set (reg h-sp) (sub (reg h-sp) 2))
9270 (case DFLT dst
9271 ((#x0) (set (mem32 mode (reg h-sp)) (reg h-dct0)))
9272 ((#x1) (set (mem32 mode (reg h-sp)) (reg h-dct1)))
9273 ((#x2) (sequence ((HI tflag))
9274 (set tflag 0)
9275 (if (eq cbit 1) (set tflag (or tflag #x1)))
9276 (if (eq dbit 1) (set tflag (or tflag #x2)))
9277 (if (eq zbit 1) (set tflag (or tflag #x4)))
9278 (if (eq sbit 1) (set tflag (or tflag #x8)))
9279 (if (eq bbit 1) (set tflag (or tflag #x10)))
9280 (if (eq obit 1) (set tflag (or tflag #x20)))
9281 (if (eq ibit 1) (set tflag (or tflag #x40)))
9282 (if (eq ubit 1) (set tflag (or tflag #x80)))
9283 (set (mem32 mode (reg h-sp)) tflag)))
9284 ((#x3) (set (mem32 mode (reg h-sp)) (reg h-svf)))
9285 ((#x4) (set (mem32 mode (reg h-sp)) (reg h-drc0)))
9286 ((#x5) (set (mem32 mode (reg h-sp)) (reg h-drc1)))
9287 ((#x6) (set (mem32 mode (reg h-sp)) (reg h-dmd0)))
9288 ((#x7) (set (mem32 mode (reg h-sp)) (reg h-dmd1)))
9289 )
9290 )
9291)
9292(define-pmacro (pushc32-cr2-sem mode dst)
9293 (sequence ()
9294 (set (reg h-sp) (sub (reg h-sp) 4))
9295 (case DFLT dst
9296 ((#x0) (set (mem32 mode (reg h-sp)) (reg h-intb)))
9297 ((#x1) (set (mem32 mode (reg h-sp)) (reg h-sp)))
9298 ((#x2) (set (mem32 mode (reg h-sp)) (reg h-sb)))
9299 ((#x3) (set (mem32 mode (reg h-sp)) (reg h-fb)))
9300 ((#x7) (set (mem32 mode (reg h-sp)) (reg h-isp)))
9301 )
9302 )
9303)
9304(define-pmacro (pushc16-sem mode dst)
9305 (sequence ()
9306 (set (reg h-sp) (sub (reg h-sp) 2))
9307 (case DFLT dst
9308 ((#x1) (set (mem16 mode (reg h-sp)) (and (reg h-intb) #xffff)))
9309 ((#x2) (set (mem16 mode (reg h-sp)) (and (reg h-intb) #xffff0000)))
9310 ((#x3) (sequence ((HI tflag))
9311 (if (eq cbit 1) (set tflag (or tflag #x1)))
9312 (if (eq dbit 1) (set tflag (or tflag #x2)))
9313 (if (eq zbit 1) (set tflag (or tflag #x4)))
9314 (if (eq sbit 1) (set tflag (or tflag #x8)))
9315 (if (eq bbit 1) (set tflag (or tflag #x10)))
9316 (if (eq obit 1) (set tflag (or tflag #x20)))
9317 (if (eq ibit 1) (set tflag (or tflag #x40)))
9318 (if (eq ubit 1) (set tflag (or tflag #x80)))
9319 (set (mem16 mode (reg h-sp)) tflag)))
9320
9321 ((#x4) (set (mem16 mode (reg h-sp)) (reg h-isp)))
9322 ((#x5) (set (mem16 mode (reg h-sp)) (reg h-sp)))
9323 ((#x6) (set (mem16 mode (reg h-sp)) (reg h-sb)))
9324 ((#x7) (set (mem16 mode (reg h-sp)) (reg h-fb)))
9325 )
9326 )
9327)
9328; pushc src (m16c)
9329(dni pushc16.imm16 "pushc dst" ((machine 16))
9330 ("pushc ${cr16}")
9331 (+ (f-0-4 #xE) (f-4-4 #xB) (f-8-1 0) (f-12-4 2) cr16)
9332 (pushc16-sem HI cr16)
9333 ())
9334; pushc src (m32c #1)
9335(dni pushc32.imm16-cr1 "pushc dst" ((machine 32))
9336 ("pushc ${cr1-Unprefixed-32}")
9337 (+ (f-0-4 #xD) (f-4-4 1) (f-8-4 #xA) (f-12-1 1) cr1-Unprefixed-32)
9338 (pushc32-cr1-sem HI cr1-Unprefixed-32)
9339 ())
9340; pushc src (m32c #2)
9341(dni pushc32.imm16-cr2 "pushc dst" ((machine 32))
9342 ("pushc ${cr2-32}")
9343 (+ (f-0-4 #xD) (f-4-4 1) (f-8-4 2) (f-12-1 1) cr2-32)
9344 (pushc32-cr2-sem SI cr2-32)
9345 ())
9346
9347;-------------------------------------------------------------
9348; popm - pop multiple
9349; pushm - push multiple
9350;-------------------------------------------------------------
9351
9352(define-pmacro (popm-sem machine dst)
9353 (sequence ((SI addrlen))
9354 (if (eq machine 16)
9355 (set addrlen 2)
9356 (set addrlen 4))
9357 (if (and dst 1)
9358 (sequence () (set R0 (mem-mach machine HI (reg h-sp)))
9359 (set (reg h-sp) (add (reg h-sp) 2))))
9360 (if (and dst 2)
9361 (sequence () (set R1 (mem-mach machine HI (reg h-sp)))
9362 (set (reg h-sp) (add (reg h-sp) 2))))
9363 (if (and dst 4)
9364 (sequence () (set R2 (mem-mach machine HI (reg h-sp)))
9365 (set (reg h-sp) (add (reg h-sp) 2))))
9366 (if (and dst 8)
9367 (sequence () (set R3 (mem-mach machine HI (reg h-sp)))
9368 (set (reg h-sp) (add (reg h-sp) 2))))
9369 (if (and dst 16)
9370 (sequence () (set A0 (mem-mach machine HI (reg h-sp)))
9371 (set (reg h-sp) (add (reg h-sp) addrlen))))
9372 (if (and dst 32)
9373 (sequence () (set A1 (mem-mach machine HI (reg h-sp)))
9374 (set (reg h-sp) (add (reg h-sp) addrlen))))
9375 (if (and dst 64)
9376 (sequence () (set (reg h-sb) (mem-mach machine HI (reg h-sp)))
9377 (set (reg h-sp) (add (reg h-sp) addrlen))))
9378 (if (eq dst 128)
9379 (sequence () (set (reg h-fb) (mem-mach machine HI (reg h-sp)))
9380 (set (reg h-sp) (add (reg h-sp) addrlen))))
9381 )
9382)
9383
9384(define-pmacro (pushm-sem machine dst)
9385 (sequence ((SI count) (SI addrlen))
9386 (if (eq machine 16)
9387 (set addrlen 2)
9388 (set addrlen 4))
9389 (if (eq dst 1)
9390 (sequence () (set (reg h-sp) (sub (reg h-sp) addrlen))
9391 (set (mem-mach machine HI (reg h-sp)) (reg h-fb))))
9392 (if (and dst 2)
9393 (sequence () (set (reg h-sp) (sub (reg h-sp) addrlen))
9394 (set (mem-mach machine HI (reg h-sp)) (reg h-sb))))
9395 (if (and dst 4)
9396 (sequence () (set (reg h-sp) (sub (reg h-sp) addrlen))
9397 (set (mem-mach machine HI (reg h-sp)) A1)))
9398 (if (and dst 8)
9399 (sequence () (set (reg h-sp) (sub (reg h-sp) addrlen))
9400 (set (mem-mach machine HI (reg h-sp)) A0)))
9401 (if (and dst 16)
9402 (sequence () (set (reg h-sp) (sub (reg h-sp) 2))
9403 (set (mem-mach machine HI (reg h-sp)) R3)))
9404 (if (and dst 32)
9405 (sequence () (set (reg h-sp) (sub (reg h-sp) 2))
9406 (set (mem-mach machine HI (reg h-sp)) R2)))
9407 (if (and dst 64)
9408 (sequence () (set (reg h-sp) (sub (reg h-sp) 2))
9409 (set (mem-mach machine HI (reg h-sp)) R1)))
9410 (if (and dst 128)
9411 (sequence () (set (reg h-sp) (sub (reg h-sp) 2))
9412 (set (mem-mach machine HI (reg h-sp)) R0)))
9413 )
9414)
9415
9416(dni popm16 "popm regs" ((machine 16))
9417 ("popm ${Regsetpop}")
9418 (+ (f-0-4 #xE) (f-4-4 #xD) Regsetpop)
9419 (popm-sem 16 Regsetpop)
9420 ())
9421(dni pushm16 "pushm regs" ((machine 16))
9422 ("pushm ${Regsetpush}")
9423 (+ (f-0-4 #xE) (f-4-4 #xC) Regsetpush)
9424 (pushm-sem 16 Regsetpush)
9425 ())
9426(dni popm "popm regs" ((machine 32))
9427 ("popm ${Regsetpop}")
9428 (+ (f-0-4 #x8) (f-4-4 #xE) Regsetpop)
9429 (popm-sem 32 Regsetpop)
9430 ())
9431(dni pushm "pushm regs" ((machine 32))
9432 ("pushm ${Regsetpush}")
9433 (+ (f-0-4 #x8) (f-4-4 #xF) Regsetpush)
9434 (pushm-sem 32 Regsetpush)
9435 ())
9436
9437;-------------------------------------------------------------
9438; push - Save register/memory/immediate data
9439;-------------------------------------------------------------
9440
9441; TODO future: split this into .b and .w semantics
9442(define-pmacro (push-sem-mach mach mode dst)
9443 (sequence ((mode b_or_w) (SI length))
9444 (set b_or_w -1)
9445 (set b_or_w (srl b_or_w #x8))
9446 (if (eq b_or_w #x0)
9447 (set length 1) ; .b
9448 (if (eq b_or_w #xff)
9449 (set length 2) ; .w
9450 (set length 4))) ; .l
9451 (set (reg h-sp) (sub (reg h-sp) length))
9452 (case DFLT length
9453 ((1) (set (mem-mach mach QI (reg h-sp)) dst))
9454 ((2) (set (mem-mach mach HI (reg h-sp)) dst))
9455 ((4) (set (mem-mach mach SI (reg h-sp)) dst)))
9456 )
9457 )
9458
9459(define-pmacro (push-sem16 mode dst) (push-sem-mach 16 mode dst))
9460(define-pmacro (push-sem32 mode dst) (push-sem-mach 32 mode dst))
9461
9462; push.BW:G imm (m16 #1 m32 #1)
9463(dni push16.b.G-imm "push.b:G #Imm-16-QI" ((machine 16))
9464 ("push.b$G #${Imm-16-QI}")
9465 (+ (f-0-4 7) (f-4-4 #xC) (f-8-4 #xE) (f-12-4 2) Imm-16-QI)
9466 (push-sem16 QI Imm-16-QI)
9467 ())
9468
9469(dni push16.w.G-imm "push.w:G #Imm-16-HI" ((machine 16))
9470 ("push.w$G #${Imm-16-HI}")
9471 (+ (f-0-4 7) (f-4-4 #xD) (f-8-4 #xE) (f-12-4 2) Imm-16-HI)
9472 (push-sem16 HI Imm-16-HI)
9473 ())
9474
458f7770 9475(dni push32.b.imm "push.b #Imm-8-QI" ((machine 32))
8d0e2679 9476 ("push.b #${Imm-8-QI}")
49f58d10
JB		 9477 (+ (f-0-4 #xA) (f-4-4 #xE) Imm-8-QI)
9478 (push-sem32 QI Imm-8-QI)
9479 ())
9480
9481(dni push32.w.imm "push.w #Imm-8-HI" ((machine 32))
9482 ("push.w #${Imm-8-HI}")
9483 (+ (f-0-4 #xA) (f-4-4 #xF) Imm-8-HI)
9484 (push-sem32 HI Imm-8-HI)
9485 ())
9486
9487; push.BW:G src (m16 #2)
c6552317 9488(unary-insn-mach-g 16 push (f-0-4 7) (f-4-3 2) (f-8-4 #x4) push-sem16 $G)
49f58d10
JB		 9489; push.BW:G src (m32 #2)
9490(unary-insn-mach 32 push #xC #x0 #xE push-sem32)
9491
9492
9493; push.b:S r0l/r0h (m16 #3)
9494(dni push16.b-s-rn "push.b:S r0[lh]" ((machine 16))
9495 "push.b$S ${Rn16-push-S-anyof}"
9496 (+ (f-0-4 #x8) Rn16-push-S-anyof (f-5-3 #x2))
9497 (push-sem16 QI Rn16-push-S-anyof)
9498 ())
9499; push.w:S a0/a1 (m16 #4)
9500(dni push16.b-s-an "push.w:S a[01]" ((machine 16))
9501 "push.w$S ${An16-push-S-anyof}"
9502 (+ (f-0-4 #xC) An16-push-S-anyof (f-5-3 #x2))
9503 (push-sem16 HI An16-push-S-anyof)
9504 ())
9505
9506; push.l imm32 (m32 #3)
9507(dni push32.l.imm "push.l #Imm-16-SI" ((machine 32))
9508 ("push.l #${Imm-16-SI}")
9509 (+ (f-0-4 #xB) (f-4-4 6) (f-8-4 5) (f-12-4 3) Imm-16-SI)
9510 (push-sem32 SI Imm-16-SI)
9511 ())
9512; push.l src (m32 #4)
9513(unary-insn-defn 32 16-Unprefixed SI .l push (+ (f-0-4 #xA) (f-7-1 0) dst32-16-Unprefixed-SI (f-10-2 0) (f-12-4 1)) push-sem32)
9514
9515;-------------------------------------------------------------
9516; pusha - push effective address
9517;------------------------------------------------------------
9518
9519(define-pmacro (push16a-sem mode dst)
9520 (sequence ()
9521 (set (reg h-sp) (sub (reg h-sp) 2))
9522 (set (mem16 HI (reg h-sp)) dst))
9523)
9524(define-pmacro (push32a-sem mode dst)
9525 (sequence ()
9526 (set (reg h-sp) (sub (reg h-sp) 4))
9527 (set (mem32 SI (reg h-sp)) dst))
9528)
9529(unary-insn-defn 16 16-Mova HI "" pusha (+ (f-0-4 7) (f-4-4 #xD) (f-8-4 9) dst16-16-Mova-HI) push16a-sem)
9530(unary-insn-defn 32 16-Unprefixed-Mova SI "" pusha (+ (f-0-4 #xB) (f-7-1 0) dst32-16-Unprefixed-Mova-SI (f-10-2 0) (f-12-4 1)) push32a-sem)
9531
9532;-------------------------------------------------------------
9533; reit - return from interrupt
9534;-------------------------------------------------------------
9535
9536; ??? semantics
9537(dni reit16 "REIT" ((machine 16))
9538 ("reit")
9539 (+ (f-0-4 #xF) (f-4-4 #xB))
9540 (nop)
9541 ())
9542(dni reit32 "REIT" ((machine 32))
9543 ("reit")
9544 (+ (f-0-4 9) (f-4-4 #xE))
9545 (nop)
9546 ())
9547
9548;-------------------------------------------------------------
9549; rmpa - repeat multiple and addition
9550;-------------------------------------------------------------
9551
9552; TODO semantics
9553(dni rmpa16.b "rmpa.size" ((machine 16))
9554 ("rmpa.b")
9555 (+ (f-0-4 7) (f-4-4 #xC) (f-8-4 #xF) (f-12-4 1))
9556 (nop)
9557 ())
9558(dni rmpa16.w "rmpa.size" ((machine 16))
9559 ("rmpa.w")
9560 (+ (f-0-4 7) (f-4-4 #xD) (f-8-4 #xF) (f-12-4 1))
9561 (nop)
9562 ())
9563(dni rmpa32.b "rmpa.size" ((machine 32))
9564 ("rmpa.b")
9565 (+ (f-0-4 #xB) (f-4-4 8) (f-8-4 4) (f-12-4 3))
9566 (nop)
9567 ())
9568
9569(dni rmpa32.w "rmpa.size" ((machine 32))
9570 ("rmpa.w")
9571 (+ (f-0-4 #xB) (f-4-4 8) (f-8-4 5) (f-12-4 3))
9572 (nop)
9573 ())
9574
9575;-------------------------------------------------------------
9576; rolc - rotate left with carry
9577;-------------------------------------------------------------
9578
9579; TODO check semantics
9580; TODO future: split this into .b and .w semantics
9581(define-pmacro (rolc-sem mode dst)
9582 (sequence ((mode result) (SI ocbit) (mode b_or_w) (USI mask))
9583 (set b_or_w -1)
9584 (set b_or_w (srl b_or_w #x8))
9585 (if (eq b_or_w #x0)
9586 (set mask #x8000) ; .b
9587 (set mask #x80000000)) ; .w
9588 (set ocbit cbit)
9589 (set cbit (and dst mask))
9590 (set result (sll mode dst 1))
9591 (set result (or result ocbit))
9592 (set-z-and-s result)
9593 (set dst result))
9594)
9595; rolc.BW src,dst
9596(unary-insn rolc (f-0-4 7) (f-4-3 3) (f-8-4 #xA) #xB #x2 #xE rolc-sem)
9597
9598;-------------------------------------------------------------
9599; rorc - rotate right with carry
9600;-------------------------------------------------------------
9601
9602; TODO check semantics
9603; TODO future: split this into .b and .w semantics
9604(define-pmacro (rorc-sem mode dst)
9605 (sequence ((mode result) (SI ocbit) (mode b_or_w) (USI mask) (SI shamt))
9606 (set b_or_w -1)
9607 (set b_or_w (srl b_or_w #x8))
9608 (if (eq b_or_w #x0)
9609 (sequence () (set mask #x7fff) (set shamt 15)) ; .b
9610 (sequence () (set mask #x7fffffff) (set shamt 31))) ; .w
9611 (set ocbit cbit)
9612 (set cbit (and dst #x1))
9613 (set result (srl mode dst (const 1)))
9614 (set result (or (and result mask) (sll ocbit shamt)))
9615 (set-z-and-s result)
9616 (set dst result))
9617)
9618; rorc.BW src,dst
9619(unary-insn rorc (f-0-4 7) (f-4-3 3) (f-8-4 #xB) #xA #x2 #xE rorc-sem)
9620
9621;-------------------------------------------------------------
9622; rot - rotate
9623;-------------------------------------------------------------
9624
9625; TODO future: split this into .b and .w semantics
9626(define-pmacro (rot-1-sem mode src1 dst)
9627 (sequence ((mode tmp) (mode b_or_w) (USI mask) (SI shift))
9628 (case DFLT src1
9629 ((#x0) (set shift 1))
9630 ((#x1) (set shift 2))
9631 ((#x2) (set shift 3))
9632 ((#x3) (set shift 4))
9633 ((#x4) (set shift 5))
9634 ((#x5) (set shift 6))
9635 ((#x6) (set shift 7))
9636 ((#x7) (set shift 8))
9637 ((-8) (set shift -1))
9638 ((-7) (set shift -2))
9639 ((-6) (set shift -3))
9640 ((-5) (set shift -4))
9641 ((-4) (set shift -5))
9642 ((-3) (set shift -6))
9643 ((-2) (set shift -7))
9644 ((-1) (set shift -8))
9645 (else (set shift 0))
9646 )
9647 (set b_or_w -1)
9648 (set b_or_w (srl b_or_w #x8))
9649 (if (eq b_or_w #x0)
9650 (set mask #x7fff) ; .b
9651 (set mask #x7fffffff)) ; .w
9652 (set tmp dst)
9653 (if (gt mode shift 0)
9654 (sequence ()
9655 (set tmp (rol mode tmp shift))
9656 (set cbit (and tmp #x1)))
9657 (sequence ()
9658 (set tmp (ror mode tmp (mul shift -1)))
9659 (set cbit (and tmp mask))))
9660 (set-z-and-s tmp)
9661 (set dst tmp))
9662)
9663(define-pmacro (rot-2-sem mode dst)
9664 (sequence ((mode tmp) (mode b_or_w) (USI mask))
9665 (set b_or_w -1)
9666 (set b_or_w (srl b_or_w #x8))
9667 (if (eq b_or_w #x0)
9668 (set mask #x7fff) ; .b
9669 (set mask #x7fffffff)) ; .w
9670 (set tmp dst)
9671 (if (gt mode (reg h-r1h) 0)
9672 (sequence ()
9673 (set tmp (rol mode tmp (reg h-r1h)))
9674 (set cbit (and tmp #x1)))
9675 (sequence ()
9676 (set tmp (ror mode tmp (reg h-r1h)))
9677 (set cbit (and tmp mask))))
9678 (set-z-and-s tmp)
9679 (set dst tmp))
9680)
9681
9682; rot.BW #imm4,dst
9683(binary-arith16-shimm4-dst-defn QI .b 0 0 rot (f-0-4 #xE) (f-4-3 0) rot-1-sem)
9684(binary-arith16-shimm4-dst-defn HI .w 0 1 rot (f-0-4 #xE) (f-4-3 0) rot-1-sem)
9685(binary-arith32-shimm4-dst-defn QI .b 0 0 rot #x7 #x2 rot-1-sem)
9686(binary-arith32-shimm4-dst-defn HI .w 0 1 rot #x7 #x2 rot-1-sem)
9687; rot.BW src,dst
9688
9689(dni rot16.b-dst "rot r1h,dest" ((machine 16))
a1a280bb
DD		 9690 ("rot.b r1h,${dst16-16-QI}")
9691 (+ (f-0-4 7) (f-4-4 #x4) (f-8-4 #x6) dst16-16-QI)
9692 (rot-2-sem QI dst16-16-QI)
49f58d10
JB		 9693 ())
9694(dni rot16.w-dst "rot r1h,dest" ((machine 16))
9695 ("rot.w r1h,${dst16-16-HI}")
9696 (+ (f-0-4 7) (f-4-4 #x5) (f-8-4 #x6) dst16-16-HI)
9697 (rot-2-sem HI dst16-16-HI)
9698 ())
9699
9700(dni rot32.b-dst "rot r1h,dest" ((machine 32))
a1a280bb
DD		 9701 ("rot.b r1h,${dst32-16-Unprefixed-QI}")
9702 (+ (f-0-4 #xA) dst32-16-Unprefixed-QI (f-7-1 0) (f-10-2 3) (f-12-4 #xF))
9703 (rot-2-sem QI dst32-16-Unprefixed-QI)
49f58d10
JB		 9704 ())
9705(dni rot32.w-dst "rot r1h,dest" ((machine 32))
a1a280bb
DD		 9706 ("rot.w r1h,${dst32-16-Unprefixed-HI}")
9707 (+ (f-0-4 #xA) dst32-16-Unprefixed-HI (f-7-1 1) (f-10-2 3) (f-12-4 #xF))
9708 (rot-2-sem HI dst32-16-Unprefixed-HI)
49f58d10
JB		 9709 ())
9710
9711;-------------------------------------------------------------
9712; rts - return from subroutine
9713;-------------------------------------------------------------
9714
9715(define-pmacro (rts16-sem)
9716 (sequence ((SI tpc))
9717 (set tpc (mem16 HI (reg h-sp)))
9718 (set (reg h-sp) (add (reg h-sp) 2))
9719 (set tpc (or tpc (sll (mem16 QI (reg h-sp)) 16)))
9720 (set (reg h-sp) (add (reg h-sp) 1))
9721 (set pc tpc)
9722 )
9723)
9724(define-pmacro (rts32-sem)
9725 (sequence ((SI tpc))
9726 (set tpc (mem32 HI (reg h-sp)))
9727 (set (reg h-sp) (add (reg h-sp) 2))
9728 (set tpc (or tpc (sll (mem32 HI (reg h-sp)) 16)))
9729 (set (reg h-sp) (add (reg h-sp) 2))
9730 (set pc tpc)
9731 )
9732)
9733
9734(dni rts16 "rts" ((machine 16))
9735 ("rts")
9736 (+ (f-0-4 #xF) (f-4-4 3))
9737 (rts16-sem)
9738 ())
9739
9740(dni rts32 "rts" ((machine 32))
9741 ("rts")
9742 (+ (f-0-4 #xD) (f-4-4 #xF))
9743 (rts32-sem)
9744 ())
9745
9746;-------------------------------------------------------------
9747; sbb - subtract with borrow
9748;-------------------------------------------------------------
9749
9750(define-pmacro (sbb-sem mode src dst)
9751 (sequence ((mode result))
9752 (set result (subc mode dst src cbit))
9753 (set obit (add-oflag mode dst src cbit))
9754 (set cbit (add-oflag mode dst src cbit))
9755 (set-z-and-s result)
9756 (set dst result))
9757)
9758
9759; sbb.size:G #imm,dst
9760(binary-arith16-imm-dst-defn QI QI .b 0 sbb X (f-0-4 7) (f-4-3 3) (f-8-4 7) sbb-sem)
9761(binary-arith16-imm-dst-defn HI HI .w 1 sbb X (f-0-4 7) (f-4-3 3) (f-8-4 7) sbb-sem)
9762(binary-arith32-imm-dst-Prefixed QI QI .b 0 sbb X #x9 #x2 #xE sbb-sem)
9763(binary-arith32-imm-dst-Prefixed HI HI .w 1 sbb X #x9 #x2 #xE sbb-sem)
9764
9765; sbb.BW:G src,dst
9766(binary-arith16-src-dst-defn QI QI .b 0 sbb X (f-0-4 #xB) (f-4-3 4) sbb-sem)
9767(binary-arith16-src-dst-defn HI HI .w 1 sbb X (f-0-4 #xB) (f-4-3 4) sbb-sem)
9768(binary-arith32-src-dst-Prefixed QI QI .b 0 sbb X #x1 #x6 sbb-sem)
9769(binary-arith32-src-dst-Prefixed HI HI .w 1 sbb X #x1 #x6 sbb-sem)
9770
9771;-------------------------------------------------------------
9772; sbjnz - subtract then jump on not zero
9773;-------------------------------------------------------------
9774
9775(define-pmacro (sub-jnz-sem mode src dst label)
9776 (sequence ((mode result))
9777 (set result (sub mode dst src))
9778 (set dst result)
9779 (if (ne result 0)
9780 (set pc label)))
9781)
9782
9783; sbjnz.size #imm4,dst,label
c6552317 9784(arith-jnz-imm4-dst sbjnz s4n (f-0-4 #xF) (f-4-3 4) #xf #x1 sub-jnz-sem)
49f58d10
JB		 9785
9786;-------------------------------------------------------------
9787; sccnd - store condition on condition (m32)
9788;-------------------------------------------------------------
9789
9790(define-pmacro (sccnd-sem cnd dst)
9791 (sequence ()
9792 (set dst 0)
9793 (case DFLT cnd
9794 ((#x00) (if (not cbit) (set dst 1))) ;ltu nc
9795 ((#x01) (if (or cbit zbit) (set dst 1))) ;leu
9796 ((#x02) (if (not zbit) (set dst 1))) ;ne nz
9797 ((#x03) (if (not sbit) (set dst 1))) ;pz
9798 ((#x04) (if (not obit) (set dst 1))) ;no
9799 ((#x05) (if (not (or zbit (xor sbit obit))) (set dst 1))) ;gt
9800 ((#x06) (if (xor sbit obit) (set dst 1))) ;ge
9801 ((#x08) (if (trunc BI cbit) (set dst 1))) ;geu c
9802 ((#x09) (if (not (or cbit zbit)) (set dst 1))) ;gtu
9803 ((#x0a) (if (trunc BI zbit) (set dst 1))) ;eq z
9804 ((#x0b) (if (trunc BI sbit) (set dst 1))) ;n
9805 ((#x0c) (if (trunc BI obit) (set dst 1))) ;o
9806 ((#x0d) (if (or zbit (xor sbit obit)) (set dst 1))) ;le
9807 ((#x0e) (if (xor sbit obit) (set dst 1))) ;lt
9808 )
9809 )
9810 )
9811
9812; scCND dst
9813(dni sccnd
9814 "sccnd dst"
9815 ((machine 32))
9816 "sc$sccond32 ${dst32-16-Unprefixed-HI}"
9817 (+ (f-0-4 #xD) dst32-16-Unprefixed-HI (f-7-1 1) (f-10-2 3) sccond32)
9818 (sccnd-sem sccond32 dst32-16-Unprefixed-HI)
9819 ())
9820
9821;-------------------------------------------------------------
9822; scmpu - string compare unequal (m32)
9823;-------------------------------------------------------------
9824
9825; TODO semantics
9826(dni scmpu.b "scmpu.b" ((machine 32))
9827 ("scmpu.b")
9828 (+ (f-0-4 #xB) (f-4-4 8) (f-8-4 #xC) (f-12-4 3))
9829 (c-call VOID "scmpu_QI_semantics")
9830 ())
9831
9832(dni scmpu.w "scmpu.w" ((machine 32))
9833 ("scmpu.w")
9834 (+ (f-0-4 #xB) (f-4-4 8) (f-8-4 #xD) (f-12-4 3))
9835 (c-call VOID "scmpu_HI_semantics")
9836 ())
9837
9838;-------------------------------------------------------------
9839; sha - shift arithmetic
9840;-------------------------------------------------------------
9841
9842; TODO future: split this into .b and .w semantics
9843(define-pmacro (sha-sem mode src1 dst)
9844 (sequence ((mode result)(mode shift)(mode shmode))
9845 (case DFLT src1
9846 ((#x0) (set shift 1))
9847 ((#x1) (set shift 2))
9848 ((#x2) (set shift 3))
9849 ((#x3) (set shift 4))
9850 ((#x4) (set shift 5))
9851 ((#x5) (set shift 6))
9852 ((#x6) (set shift 7))
9853 ((#x7) (set shift 8))
9854 ((-8) (set shift -1))
9855 ((-7) (set shift -2))
9856 ((-6) (set shift -3))
9857 ((-5) (set shift -4))
9858 ((-4) (set shift -5))
9859 ((-3) (set shift -6))
9860 ((-2) (set shift -7))
9861 ((-1) (set shift -8))
9862 (else (set shift 0))
9863 )
9864 (set shmode -1)
9865 (set shmode (srl shmode #x8))
9866 (if (lt mode shift #x0) (set result (sra mode dst (mul shift -1))))
9867 (if (gt mode shift 0) (set result (sll mode dst shift)))
9868 (if (eq shmode #x0) ; QI
9869 (sequence
9870 ((mode cbitamt))
9871 (if (lt mode shift #x0)
9872 (set cbitamt (sub #x8 shift)) ; sra
9873 (set cbitamt (sub shift 1))) ; sll
9874 (set cbit (srl (and (sll dst cbitamt) #x80) #x7))
9875 (set obit (ne (and dst #x80) (and result #x80)))
9876 ))
9877 (if (eq shmode #xff) ; HI
9878 (sequence
9879 ((mode cbitamt))
9880 (if (lt mode shift #x0)
9881 (set cbitamt (sub 16 shift)) ; sra
9882 (set cbitamt (sub shift 1))) ; sll
9883 (set cbit (srl (and (sll dst cbitamt) #x8000) #xf))
9884 (set obit (ne (and dst #x8000) (and result #x8000)))
9885 ))
9886 (set-z-and-s result)
9887 (set dst result))
9888)
9889(define-pmacro (shar1h-sem mode dst)
9890 (sequence ((mode result)(mode shmode))
9891 (set shmode -1)
9892 (set shmode (srl shmode #x8))
9893 (if (lt mode (reg h-r1h) 0) (set result (sra mode dst (reg h-r1h))))
9894 (if (gt mode (reg h-r1h) 0) (set result (sll mode dst (reg h-r1h))))
9895 (if (eq shmode #x0) ; QI
9896 (sequence
9897 ((mode cbitamt))
9898 (if (lt mode (reg h-r1h) #x0)
9899 (set cbitamt (sub #x8 (reg h-r1h))) ; sra
9900 (set cbitamt (sub (reg h-r1h) 1))) ; sll
9901 (set cbit (srl (and (sll dst cbitamt) #x80) #x7))
9902 (set obit (ne (and dst #x80) (and result #x80)))
9903 ))
9904 (if (eq shmode #xff) ; HI
9905 (sequence
9906 ((mode cbitamt))
9907 (if (lt mode (reg h-r1h) #x0)
9908 (set cbitamt (sub 16 (reg h-r1h))) ; sra
9909 (set cbitamt (sub (reg h-r1h) 1))) ; sll
9910 (set cbit (srl (and (sll dst cbitamt) #x8000) #xf))
9911 (set obit (ne (and dst #x8000) (and result #x8000)))
9912 ))
9913 (set-z-and-s result)
9914 (set dst result))
9915)
9916; sha.BW #imm4,dst (m16 #1 m32 #1)
9917(binary-arith16-shimm4-dst-defn QI .b 0 0 sha (f-0-4 #xF) (f-4-3 0) sha-sem)
9918(binary-arith16-shimm4-dst-defn HI .w 0 1 sha (f-0-4 #xF) (f-4-3 0) sha-sem)
9919(binary-arith32-shimm4-dst-defn QI .b 1 0 sha #x7 #x0 sha-sem)
9920(binary-arith32-shimm4-dst-defn HI .w 1 1 sha #x7 #x0 sha-sem)
9921; sha.BW r1h,dst (m16 #2 m32 #3)
9922(dni sha16.b-dst "sha.b r1h,dest" ((machine 16))
9923 ("sha.b r1h,${dst16-16-QI}")
9924 (+ (f-0-4 7) (f-4-4 4) (f-8-4 #xF) dst16-16-QI)
9925 (shar1h-sem HI dst16-16-QI)
9926 ())
9927(dni sha16.w-dst "sha.w r1h,dest" ((machine 16))
9928 ("sha.w r1h,${dst16-16-HI}")
9929 (+ (f-0-4 7) (f-4-4 5) (f-8-4 #xF) dst16-16-HI)
9930 (shar1h-sem HI dst16-16-HI)
9931 ())
9932(dni sha32.b-dst "sha.b r1h,dest" ((machine 32))
9933 ("sha.b r1h,${dst32-16-Unprefixed-QI}")
9934 (+ (f-0-4 #xB) dst32-16-Unprefixed-QI (f-7-1 0) (f-10-2 3) (f-12-4 #xE))
9935 (shar1h-sem QI dst32-16-Unprefixed-QI)
9936 ())
9937(dni sha32.w-dst "sha.w r1h,dest" ((machine 32))
9938 ("sha.w r1h,${dst32-16-Unprefixed-HI}")
9939 (+ (f-0-4 #xB) dst32-16-Unprefixed-HI (f-7-1 1) (f-10-2 3) (f-12-4 #xE))
9940 (shar1h-sem HI dst32-16-Unprefixed-HI)
9941 ())
9942; sha.L #imm,dst (m16 #3)
9943(dni sha16-L-imm-r2r0 "sha.L #Imm-sh-12-s4,r2r0" ((machine 16))
9944 "sha.l #${Imm-sh-12-s4},r2r0"
9945 (+ (f-0-4 #xE) (f-4-4 #xB) (f-8-4 #xA) Imm-sh-12-s4)
9946 (sha-sem SI Imm-sh-12-s4 (reg h-r2r0))
9947 ())
9948(dni sha16-L-imm-r3r1 "sha.L #Imm-sh-12-s4,r3r1" ((machine 16))
9949 "sha.l #${Imm-sh-12-s4},r3r1"
9950 (+ (f-0-4 #xE) (f-4-4 #xB) (f-8-4 #xB) Imm-sh-12-s4)
9951 (sha-sem SI Imm-sh-12-s4 (reg h-r3r1))
9952 ())
9953; sha.L r1h,dst (m16 #4)
9954(dni sha16-L-r1h-r2r0 "sha.L r1h,r2r0" ((machine 16))
9955 "sha.l r1h,r2r0"
9956 (+ (f-0-4 #xE) (f-4-4 #xB) (f-8-4 2) (f-12-4 1))
9957 (sha-sem SI (reg h-r1h) (reg h-r2r0))
9958 ())
9959(dni sha16-L-r1h-r3r1 "sha.L r1h,r3r1" ((machine 16))
9960 "sha.l r1h,r3r1"
9961 (+ (f-0-4 #xE) (f-4-4 #xB) (f-8-4 3) (f-12-4 1))
9962 (sha-sem SI (reg h-r1h) (reg h-r3r1))
9963 ())
9964; sha.L #imm8,dst (m32 #2)
9965(binary-arith32-imm-dst-defn QI SI .l 0 sha X #xA #x2 #x1 sha-sem)
9966; sha.L r1h,dst (m32 #4)
9967(dni sha32.l-dst "sha.l r1h,dest" ((machine 32))
9968 ("sha.l r1h,${dst32-16-Unprefixed-SI}")
9969 (+ (f-0-4 #xC) dst32-16-Unprefixed-SI (f-7-1 0) (f-10-2 1) (f-12-4 1))
9970 (shar1h-sem QI dst32-16-Unprefixed-SI)
9971 ())
9972
9973;-------------------------------------------------------------
9974; shanc - shift arithmetic non carry (m32)
9975;-------------------------------------------------------------
9976
9977; TODO check semantics
9978; shanc.L #imm8,dst
9979(binary-arith32-imm-dst-defn QI SI .l 0 shanc X #xC #x2 #x1 sha-sem)
9980
9981;-------------------------------------------------------------
9982; shl - shift logical
9983;-------------------------------------------------------------
9984
9985; TODO future: split this into .b and .w semantics
9986(define-pmacro (shl-sem mode src1 dst)
9987 (sequence ((mode result)(mode shift)(mode shmode))
9988 (case DFLT src1
9989 ((#x0) (set shift 1))
9990 ((#x1) (set shift 2))
9991 ((#x2) (set shift 3))
9992 ((#x3) (set shift 4))
9993 ((#x4) (set shift 5))
9994 ((#x5) (set shift 6))
9995 ((#x6) (set shift 7))
9996 ((#x7) (set shift 8))
9997 ((-8) (set shift -1))
9998 ((-7) (set shift -2))
9999 ((-6) (set shift -3))
10000 ((-5) (set shift -4))
10001 ((-4) (set shift -5))
10002 ((-3) (set shift -6))
10003 ((-2) (set shift -7))
10004 ((-1) (set shift -8))
10005 (else (set shift 0))
10006 )
10007 (set shmode -1)
10008 (set shmode (srl shmode #x8))
10009 (if (lt mode shift #x0) (set result (srl mode dst (mul shift -1))))
10010 (if (gt mode shift 0) (set result (sll mode dst shift)))
10011 (if (eq shmode #x0) ; QI
10012 (sequence
10013 ((mode cbitamt))
10014 (if (lt mode shift #x0)
10015 (set cbitamt (sub #x8 shift)); srl
10016 (set cbitamt (sub shift 1))) ; sll
10017 (set cbit (srl (and (sll dst cbitamt) #x80) #x7))
10018 (set obit (ne (and dst #x80) (and result #x80)))
10019 ))
10020 (if (eq shmode #xff) ; HI
10021 (sequence
10022 ((mode cbitamt))
10023 (if (lt mode shift #x0)
10024 (set cbitamt (sub 16 shift)) ; srl
10025 (set cbitamt (sub shift 1))) ; sll
10026 (set cbit (srl (and (sll dst cbitamt) #x8000) #xf))
10027 (set obit (ne (and dst #x8000) (and result #x8000)))
10028 ))
10029 (set-z-and-s result)
10030 (set dst result))
10031 )
10032(define-pmacro (shlr1h-sem mode dst)
10033 (sequence ((mode result)(mode shmode))
10034 (set shmode -1)
10035 (set shmode (srl shmode #x8))
10036 (if (lt mode (reg h-r1h) 0) (set result (srl mode dst (reg h-r1h))))
10037 (if (gt mode (reg h-r1h) 0) (set result (sll mode dst (reg h-r1h))))
10038 (if (eq shmode #x0) ; QI
10039 (sequence
10040 ((mode cbitamt))
10041 (if (lt mode (reg h-r1h) #x0)
10042 (set cbitamt (sub #x8 (reg h-r1h))) ; srl
10043 (set cbitamt (sub (reg h-r1h) 1))) ; sll
10044 (set cbit (srl (and (sll dst cbitamt) #x80) #x7))
10045 (set obit (ne (and dst #x80) (and result #x80)))
10046 ))
10047 (if (eq shmode #xff) ; HI
10048 (sequence
10049 ((mode cbitamt))
10050 (if (lt mode (reg h-r1h) #x0)
10051 (set cbitamt (sub 16 (reg h-r1h))) ; srl
10052 (set cbitamt (sub (reg h-r1h) 1))) ; sll
10053 (set cbit (srl (and (sll dst cbitamt) #x8000) #xf))
10054 (set obit (ne (and dst #x8000) (and result #x8000)))
10055 ))
10056 (set-z-and-s result)
10057 (set dst result))
10058 )
10059; shl.BW #imm4,dst (m16 #1 m32 #1)
10060(binary-arith16-shimm4-dst-defn QI .b 0 0 shl (f-0-4 #xE) (f-4-3 4) shl-sem)
10061(binary-arith16-shimm4-dst-defn HI .w 0 1 shl (f-0-4 #xE) (f-4-3 4) shl-sem)
10062(binary-arith32-shimm4-dst-defn QI .b 0 0 shl #x7 #x0 shl-sem)
10063(binary-arith32-shimm4-dst-defn HI .w 0 1 shl #x7 #x0 shl-sem)
10064; shl.BW r1h,dst (m16 #2 m32 #3)
10065(dni shl16.b-dst "shl.b r1h,dest" ((machine 16))
10066 ("shl.b r1h,${dst16-16-QI}")
10067 (+ (f-0-4 7) (f-4-4 4) (f-8-4 #xE) dst16-16-QI)
10068 (shlr1h-sem HI dst16-16-QI)
10069 ())
10070(dni shl16.w-dst "shl.w r1h,dest" ((machine 16))
10071 ("shl.w r1h,${dst16-16-HI}")
10072 (+ (f-0-4 7) (f-4-4 5) (f-8-4 #xE) dst16-16-HI)
10073 (shlr1h-sem HI dst16-16-HI)
10074 ())
10075(dni shl32.b-dst "shl.b r1h,dest" ((machine 32))
10076 ("shl.b r1h,${dst32-16-Unprefixed-QI}")
10077 (+ (f-0-4 #xA) dst32-16-Unprefixed-QI (f-7-1 0) (f-10-2 3) (f-12-4 #xE))
10078 (shlr1h-sem QI dst32-16-Unprefixed-QI)
10079 ())
10080(dni shl32.w-dst "shl.w r1h,dest" ((machine 32))
10081 ("shl.w r1h,${dst32-16-Unprefixed-HI}")
10082 (+ (f-0-4 #xA) dst32-16-Unprefixed-HI (f-7-1 1) (f-10-2 3) (f-12-4 #xE))
10083 (shlr1h-sem HI dst32-16-Unprefixed-HI)
10084 ())
10085; shl.L #imm,dst (m16 #3)
10086(dni shl16-L-imm-r2r0 "shl.L #Imm-sh-12-s4,r2r0" ((machine 16))
10087 "shl.l #${Imm-sh-12-s4},r2r0"
10088 (+ (f-0-4 #xE) (f-4-4 #xB) (f-8-4 #x8) Imm-sh-12-s4)
10089 (shl-sem SI Imm-sh-12-s4 (reg h-r2r0))
10090 ())
10091(dni shl16-L-imm-r3r1 "shl.L #Imm-sh-12-s4,r3r1" ((machine 16))
10092 "shl.l #${Imm-sh-12-s4},r3r1"
10093 (+ (f-0-4 #xE) (f-4-4 #xB) (f-8-4 #x9) Imm-sh-12-s4)
10094 (shl-sem SI Imm-sh-12-s4 (reg h-r3r1))
10095 ())
10096; shl.L r1h,dst (m16 #4)
10097(dni shl16-L-r1h-r2r0 "shl.L r1h,r2r0" ((machine 16))
10098 "shl.l r1h,r2r0"
10099 (+ (f-0-4 #xE) (f-4-4 #xB) (f-8-4 0) (f-12-4 1))
10100 (shl-sem SI (reg h-r1h) (reg h-r2r0))
10101 ())
10102(dni shl16-L-r1h-r3r1 "shl.L r1h,r3r1" ((machine 16))
10103 "shl.l r1h,r3r1"
10104 (+ (f-0-4 #xE) (f-4-4 #xB) (f-8-4 1) (f-12-4 1))
10105 (shl-sem SI (reg h-r1h) (reg h-r3r1))
10106 ())
10107; shl.L #imm8,dst (m32 #2)
10108(binary-arith32-imm-dst-defn QI SI .l 0 shl X #x9 #x2 #x1 shl-sem)
10109; shl.L r1h,dst (m32 #4)
10110(dni shl32.l-dst "shl.l r1h,dest" ((machine 32))
10111 ("shl.l r1h,${dst32-16-Unprefixed-SI}")
10112 (+ (f-0-4 #xC) dst32-16-Unprefixed-SI (f-7-1 0) (f-10-2 0) (f-12-4 1))
10113 (shlr1h-sem QI dst32-16-Unprefixed-SI)
10114 ())
10115
10116;-------------------------------------------------------------
10117; shlnc - shift logical non carry
10118;-------------------------------------------------------------
10119
10120; TODO check semantics
10121; shlnc.L #imm8,dst
10122(binary-arith32-imm-dst-defn QI SI .l 0 shlnc X #x8 #x2 #x1 shl-sem)
10123
10124;-------------------------------------------------------------
10125; sin - string input (m32)
10126;-------------------------------------------------------------
10127
10128; TODO semantics
10129(dni sin32.b "sin" ((machine 32))
10130 ("sin.b")
10131 (+ (f-0-4 #xB) (f-4-4 2) (f-8-4 8) (f-12-4 3))
10132 (c-call VOID "sin_QI_semantics")
10133 ())
10134
10135(dni sin32.w "sin" ((machine 32))
10136 ("sin.w")
10137 (+ (f-0-4 #xB) (f-4-4 2) (f-8-4 9) (f-12-4 3))
10138 (c-call VOID "sin_HI_semantics")
10139 ())
10140
10141;-------------------------------------------------------------
10142; smovb - string move backward
10143;-------------------------------------------------------------
10144
10145; TODO semantics
10146(dni smovb16.b "smovb.b" ((machine 16))
10147 ("smovb.b")
10148 (+ (f-0-4 7) (f-4-4 #xC) (f-8-4 #xE) (f-12-4 9))
10149 (c-call VOID "smovb_QI_semantics")
10150 ())
10151
10152(dni smovb16.w "smovb.w" ((machine 16))
10153 ("smovb.w")
10154 (+ (f-0-4 7) (f-4-4 #xD) (f-8-4 #xE) (f-12-4 9))
10155 (c-call VOID "smovb_HI_semantics")
10156 ())
10157
10158(dni smovb32.b "smovb.b" ((machine 32))
10159 ("smovb.b")
10160 (+ (f-0-4 #xB) (f-4-4 6) (f-8-4 8) (f-12-4 3))
10161 (c-call VOID "smovb_QI_semantics")
10162 ())
10163
10164(dni smovb32.w "smovb.w" ((machine 32))
10165 ("smovb.w")
10166 (+ (f-0-4 #xB) (f-4-4 6) (f-8-4 9) (f-12-4 3))
10167 (c-call VOID "smovb_HI_semantics")
10168 ())
10169
10170;-------------------------------------------------------------
10171; smovf - string move forward (m32)
10172;-------------------------------------------------------------
10173
10174; TODO semantics
10175(dni smovf16.b "smovf.b" ((machine 16))
10176 ("smovf.b")
10177 (+ (f-0-4 7) (f-4-4 #xC) (f-8-4 #xE) (f-12-4 8))
10178 (c-call VOID "smovf_QI_semantics")
10179 ())
10180
10181(dni smovf16.w "smovf.w" ((machine 16))
10182 ("smovf.w")
10183 (+ (f-0-4 7) (f-4-4 #xD) (f-8-4 #xE) (f-12-4 8))
10184 (c-call VOID "smovf_HI_semantics")
10185 ())
10186
10187(dni smovf32.b "smovf.b" ((machine 32))
10188 ("smovf.b")
10189 (+ (f-0-4 #xB) (f-4-4 0) (f-8-4 8) (f-12-4 3))
10190 (c-call VOID "smovf_QI_semantics")
10191 ())
10192
10193(dni smovf32.w "smovf.w" ((machine 32))
10194 ("smovf.w")
10195 (+ (f-0-4 #xB) (f-4-4 0) (f-8-4 9) (f-12-4 3))
10196 (c-call VOID "smovf_HI_semantics")
10197 ())
10198
10199;-------------------------------------------------------------
10200; smovu - string move unequal (m32)
10201;-------------------------------------------------------------
10202
10203; TODO semantics
10204(dni smovu.b "smovu.b" ((machine 32))
10205 ("smovu.b")
10206 (+ (f-0-4 #xB) (f-4-4 8) (f-8-4 8) (f-12-4 3))
10207 (c-call VOID "smovu_QI_semantics")
10208 ())
10209
10210(dni smovu.w "smovu.w" ((machine 32))
10211 ("smovu.w")
10212 (+ (f-0-4 #xB) (f-4-4 8) (f-8-4 9) (f-12-4 3))
10213 (c-call VOID "smovu_HI_semantics")
10214 ())
10215
10216;-------------------------------------------------------------
10217; sout - string output (m32)
10218;-------------------------------------------------------------
10219
10220; TODO semantics
10221(dni sout.b "sout.b" ((machine 32))
10222 ("sout.b")
10223 (+ (f-0-4 #xB) (f-4-4 4) (f-8-4 8) (f-12-4 3))
10224 (c-call VOID "sout_QI_semantics")
10225 ())
10226
10227(dni sout.w "sout" ((machine 32))
10228 ("sout.w")
10229 (+ (f-0-4 #xB) (f-4-4 4) (f-8-4 9) (f-12-4 3))
10230 (c-call VOID "sout_HI_semantics")
10231 ())
10232
10233;-------------------------------------------------------------
10234; sstr - string store
10235;-------------------------------------------------------------
10236
10237; TODO semantics
10238(dni sstr16.b "sstr.b" ((machine 16))
10239 ("sstr.b")
10240 (+ (f-0-4 7) (f-4-4 #xC) (f-8-4 #xE) (f-12-4 #xA))
10241 (c-call VOID "sstr_QI_semantics")
10242 ())
10243
10244(dni sstr16.w "sstr.w" ((machine 16))
10245 ("sstr.w")
10246 (+ (f-0-4 7) (f-4-4 #xD) (f-8-4 #xE) (f-12-4 #xA))
10247 (c-call VOID "sstr_HI_semantics")
10248 ())
10249
10250(dni sstr.b "sstr" ((machine 32))
10251 ("sstr.b")
10252 (+ (f-0-4 #xB) (f-4-4 8) (f-8-4 0) (f-12-4 3))
10253 (c-call VOID "sstr_QI_semantics")
10254 ())
10255
10256(dni sstr.w "sstr" ((machine 32))
10257 ("sstr.w")
10258 (+ (f-0-4 #xB) (f-4-4 8) (f-8-4 1) (f-12-4 3))
10259 (c-call VOID "sstr_HI_semantics")
10260 ())
10261
10262;-------------------------------------------------------------
10263; stnz - store on not zero
10264;-------------------------------------------------------------
10265
10266(define-pmacro (stnz-sem mode src dst)
10267 (sequence ()
10268 (if (ne zbit (const 1))
10269 (set dst src)))
10270)
10271; stnz #imm8,dst3 (m16)
10272(binary-arith16-b-S-imm8-dst3 stnz "" (f-0-4 #xD) (f-4-1 0) stnz-sem)
10273; stnz.BW #imm,dst (m32)
10274(binary-arith32-imm-dst-defn QI QI .b 0 stnz X #x9 #x1 #xF stnz-sem)
10275(binary-arith32-imm-dst-defn HI HI .w 1 stnz X #x9 #x1 #xF stnz-sem)
10276
10277;-------------------------------------------------------------
10278; stz - store on zero
10279;-------------------------------------------------------------
10280
10281(define-pmacro (stz-sem mode src dst)
10282 (sequence ()
10283 (if (eq zbit (const 1))
10284 (set dst src)))
10285)
10286; stz #imm8,dst3 (m16)
10287(binary-arith16-b-S-imm8-dst3 stz "" (f-0-4 #xC) (f-4-1 1) stz-sem)
10288; stz.BW #imm,dst (m32)
10289(binary-arith32-imm-dst-defn QI QI .b 0 stz X #x9 #x0 #xF stz-sem)
10290(binary-arith32-imm-dst-defn HI HI .w 1 stz X #x9 #x0 #xF stz-sem)
10291
10292;-------------------------------------------------------------
10293; stzx - store on zero extention
10294;-------------------------------------------------------------
10295
10296(define-pmacro (stzx-sem mode src1 src2 dst)
10297 (sequence ()
10298 (if (eq zbit (const 1))
10299 (set dst src1)
10300 (set dst src2)))
10301 )
10302; stzx #imm8,dst3 (m16)
10303(dni stzx16-imm8-imm8-r0h "stzx #Imm8,#Imm8,r0h" ((machine 16))
10304 ("stzx #${Imm-8-QI},#${Imm-16-QI},r0h")
10305 (+ (f-0-4 #xD) (f-4-4 #xB) Imm-8-QI Imm-16-QI)
10306 (stzx-sem QI Imm-8-QI Imm-16-QI (reg h-r0h))
10307 ())
10308(dni stzx16-imm8-imm8-r0l "stzx #Imm8,#Imm8,r0l" ((machine 16))
10309 ("stzx #${Imm-8-QI},#${Imm-16-QI},r0l")
10310 (+ (f-0-4 #xD) (f-4-4 #xC) Imm-8-QI Imm-16-QI)
10311 (stzx-sem QI Imm-8-QI Imm-16-QI (reg h-r0l))
10312 ())
10313(dni stzx16-imm8-imm8-dsp8sb "stzx #Imm8,#Imm8,dsp8[sb]" ((machine 16))
c6552317 10314 ("stzx #${Imm-8-QI},#${Imm-24-QI},${Dsp-16-u8}[sb]")
49f58d10
JB		 10315 (+ (f-0-4 #xD) (f-4-4 #xD) Imm-8-QI Dsp-16-u8 Imm-24-QI)
10316 (stzx-sem QI Imm-8-QI Imm-16-QI (mem16 QI (add (reg h-sb) Dsp-24-u8)))
10317 ())
10318(dni stzx16-imm8-imm8-dsp8fb "stzx #Imm8,#Imm8,dsp8[fb]" ((machine 16))
c6552317
DD		 10319 ("stzx #${Imm-8-QI},#${Imm-24-QI},${Dsp-16-s8}[fb]")
10320 (+ (f-0-4 #xD) (f-4-4 #xE) Imm-8-QI Dsp-16-s8 Imm-24-QI)
10321 (stzx-sem QI Imm-8-QI Imm-24-QI (mem16 QI (add (reg h-fb) Dsp-16-s8)))
49f58d10
JB		 10322 ())
10323(dni stzx16-imm8-imm8-abs16 "stzx #Imm8,#Imm8,abs16" ((machine 16))
c6552317 10324 ("stzx #${Imm-8-QI},#${Imm-32-QI},${Dsp-16-u16}")
75b06e7b 10325 (+ (f-0-4 #xD) (f-4-4 #xF) Imm-8-QI Dsp-16-u16 Imm-32-QI)
49f58d10
JB		 10326 (stzx-sem QI Imm-8-QI Imm-32-QI (mem16 QI Dsp-16-u16))
10327 ())
10328; stzx.BW #imm,dst (m32)
10329(insn-imm1-imm2-dst-Unprefixed stzx #x9 #x3 #xF stzx-sem)
10330
10331;-------------------------------------------------------------
10332; subx - subtract extend (m32)
10333;-------------------------------------------------------------
10334
10335(define-pmacro (subx-sem mode src1 dst)
10336 (sequence ((mode result))
10337 (set result (sub mode dst (ext mode src1)))
10338 (set obit (sub-oflag mode dst (ext mode src1) 0))
10339 (set cbit (sub-cflag mode dst (ext mode src1) 0))
10340 (set dst result)
10341 (set-z-and-s result)))
10342; subx #imm8,dst
10343(binary-arith32-imm-dst-defn QI SI "" 0 subx G #x9 #x1 #x1 subx-sem)
10344; subx src,dst
10345(binary-arith32-src-dst-defn QI SI "" 0 subx G #x1 #x0 subx-sem)
10346
10347;-------------------------------------------------------------
10348; tst - test
10349;-------------------------------------------------------------
10350
10351(define-pmacro (tst-sem mode src1 dst)
10352 (sequence ((mode result))
10353 (set result (and mode dst src1))
10354 (set-z-and-s result))
10355)
10356
10357; tst.BW #imm,dst (m16 #1 m32 #1)
f75eb1c0 10358(binary-arith-imm-dst tst G (f-0-4 7) (f-4-3 3) (f-8-4 0) #x9 #x3 #xE tst-sem)
49f58d10
JB		 10359; tst.BW src,dst (m16 #2 m32 #3)
10360(binary-arith16-src-dst-defn QI QI .b 0 tst X (f-0-4 #x8) (f-4-3 0) tst-sem)
10361(binary-arith16-src-dst-defn HI HI .w 1 tst X (f-0-4 #x8) (f-4-3 0) tst-sem)
f75eb1c0
DD		 10362(binary-arith32-src-dst-Prefixed QI QI .b 0 tst G #x1 #x9 tst-sem)
10363(binary-arith32-src-dst-Prefixed HI HI .w 1 tst G #x1 #x9 tst-sem)
49f58d10
JB		 10364; tst.BW:S #imm,dst2 (m32 #2)
10365(binary-arith32-s-imm-dst QI .b 0 tst #x0 #x6 tst-sem)
10366(binary-arith32-s-imm-dst HI .w 1 tst #x0 #x6 tst-sem)
10367
10368;-------------------------------------------------------------
10369; und - undefined
10370;-------------------------------------------------------------
10371
10372(dni und16 "und" ((machine 16))
10373 ("und")
10374 (+ (f-0-4 #xF) (f-4-4 #xF))
10375 (nop)
10376 ())
10377
10378(dni und32 "und" ((machine 32))
10379 ("und")
10380 (+ (f-0-4 #xF) (f-4-4 #xF))
10381 (nop)
10382 ())
10383
10384;-------------------------------------------------------------
10385; wait
10386;-------------------------------------------------------------
10387
10388; ??? semantics
10389(dni wait16 "wait" ((machine 16))
10390 ("wait")
10391 (+ (f-0-4 7) (f-4-4 #xD) (f-8-4 #xF) (f-12-4 3))
10392 (nop)
10393 ())
10394
10395(dni wait "wait" ((machine 32))
10396 ("wait")
10397 (+ (f-0-4 #xB) (f-4-4 2) (f-8-4 0) (f-12-4 3))
10398 (nop)
10399 ())
10400
10401;-------------------------------------------------------------
10402; xchg - exchange
10403;-------------------------------------------------------------
10404
10405(define-pmacro (xchg-sem mode src dst)
10406 (sequence ((mode result))
10407 (set result src)
10408 (set src dst)
10409 (set dst result))
10410 )
10411(define-pmacro (xchg16-defn mode sz szc src srcreg)
10412 (dni (.sym xchg16 sz - srcreg)
10413 (.str "xchg" sz "-" srcreg ",dst16-16-" mode)
10414 ((machine 16))
10415 (.str "xchg." sz " " srcreg ",${dst16-16-" mode "}")
10416 (+ (f-0-4 #x7) (f-4-3 #x5) (f-7-1 szc) (f-8-2 0) (f-10-2 src) (.sym dst16-16- mode))
10417 (xchg-sem mode (reg (.sym h- srcreg)) (.sym dst16-16- mode))
10418 ())
10419)
10420(xchg16-defn QI b 0 0 r0l)
10421(xchg16-defn QI b 0 1 r0h)
10422(xchg16-defn QI b 0 2 r1l)
10423(xchg16-defn QI b 0 3 r1h)
a1a280bb 10424(xchg16-defn HI w 1 0 r0)
49f58d10
JB		 10425(xchg16-defn HI w 1 1 r1)
10426(xchg16-defn HI w 1 2 r2)
10427(xchg16-defn HI w 1 3 r3)
10428(define-pmacro (xchg32-defn mode sz szc src srcreg)
10429 (dni (.sym xchg32 sz - srcreg)
10430 (.str "xchg" sz "-" srcreg ",dst32-16-Unprefixed-" mode)
10431 ((machine 32))
10432 (.str "xchg." sz " " srcreg ",${dst32-16-Unprefixed-" mode "}")
10433 (+ (f-0-4 #xD) (.sym dst32-16-Unprefixed- mode) (f-7-1 szc) (f-10-2 0) (f-12-1 1) (f-13-3 src))
10434 (xchg-sem mode (reg (.sym h- srcreg)) (.sym dst32-16-Unprefixed- mode))
10435 ())
10436)
10437(xchg32-defn QI b 0 0 r0l)
10438(xchg32-defn QI b 0 1 r1l)
10439(xchg32-defn QI b 0 2 a0)
10440(xchg32-defn QI b 0 3 a1)
10441(xchg32-defn QI b 0 4 r0h)
10442(xchg32-defn QI b 0 5 r1h)
10443(xchg32-defn HI w 1 0 r0)
10444(xchg32-defn HI w 1 1 r1)
10445(xchg32-defn HI w 1 2 a0)
10446(xchg32-defn HI w 1 3 a1)
10447(xchg32-defn HI w 1 4 r2)
10448(xchg32-defn HI w 1 5 r3)
10449
10450;-------------------------------------------------------------
10451; xor - exclusive or
10452;-------------------------------------------------------------
10453
10454(define-pmacro (xor-sem mode src1 dst)
10455 (sequence ((mode result))
10456 (set result (xor mode src1 dst))
10457 (set-z-and-s result)
10458 (set dst result))
10459)
10460
10461; xor.BW #imm,dst (m16 #1 m32 #1)
10462(binary-arith-imm-dst xor G (f-0-4 7) (f-4-3 3) (f-8-4 1) #x9 #x0 #xE xor-sem)
10463; xor.BW src,dst (m16 #3 m32 #3)
10464(binary-arith-src-dst xor G (f-0-4 #x8) (f-4-3 4) #x1 #x9 xor-sem)
10465
10466;-------------------------------------------------------------
10467; Widening
10468;-------------------------------------------------------------
10469
10470(define-pmacro (exts-sem smode dmode src dst)
10471 (set dst (ext dmode (trunc smode src)))
10472)
10473(define-pmacro (extz-sem smode dmode src dst)
10474 (set dst (zext dmode (trunc smode src)))
10475)
10476
10477; exts.b dst for m16c
10478(ext16-defn QI HI .b 0 exts (f-0-4 7) (f-4-3 6) (f-8-4 6) exts-sem)
10479
10480; exts.w r0 for m16c
10481(dni exts16.w-r0
10482 "exts.w r0"
10483 ((machine 16))
10484 "exts.w r0"
10485 (+ (f-0-4 #x7) (f-4-4 #xC) (f-8-4 #xF) (f-12-4 3))
10486 (exts-sem HI SI R0 R2R0)
10487 ())
10488
10489; exts.size dst for m32c
10490(ext32-defn QI HI .b 0 exts (f-0-4 #xC) (f-10-2 1) (f-12-4 #xE) exts-sem)
10491(ext32-defn HI SI .w 1 exts (f-0-4 #xC) (f-10-2 1) (f-12-4 #xE) exts-sem)
10492; exts.b src,dst for m32c
10493(ext32-binary-defn exts .b #x1 #x7 exts-sem)
10494
10495; extz.b src,dst for m32c
10496(ext32-binary-defn extz "" #x1 #xB extz-sem)
10497
10498;-------------------------------------------------------------
10499; Indirect
10500;-------------------------------------------------------------
10501
10502; TODO semantics
10503(dni srcind "SRC-INDIRECT" ((machine 32))
10504 ("src-indirect")
10505 (+ (f-0-4 4) (f-4-4 1))
10506 (set (reg h-src-indirect) 1)
10507 ())
10508
10509(dni destind "DEST-INDIRECT" ((machine 32))
10510 ("dest-indirect")
10511 (+ (f-0-4 0) (f-4-4 9))
10512 (set (reg h-dst-indirect) 1)
10513 ())
10514
10515(dni srcdestind "SRC-DEST-INDIRECT" ((machine 32))
10516 ("src-dest-indirect")
10517 (+ (f-0-4 4) (f-4-4 9))
10518 (sequence () (set (reg h-src-indirect) 1) (set (reg h-dst-indirect) 1))
10519 ())
GDB Binutils - Deliverables
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