Commit | Line | Data |
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9bc89cd8 DW |
1 | /* |
2 | * xor offload engine api | |
3 | * | |
4 | * Copyright © 2006, Intel Corporation. | |
5 | * | |
6 | * Dan Williams <dan.j.williams@intel.com> | |
7 | * | |
8 | * with architecture considerations by: | |
9 | * Neil Brown <neilb@suse.de> | |
10 | * Jeff Garzik <jeff@garzik.org> | |
11 | * | |
12 | * This program is free software; you can redistribute it and/or modify it | |
13 | * under the terms and conditions of the GNU General Public License, | |
14 | * version 2, as published by the Free Software Foundation. | |
15 | * | |
16 | * This program is distributed in the hope it will be useful, but WITHOUT | |
17 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
18 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
19 | * more details. | |
20 | * | |
21 | * You should have received a copy of the GNU General Public License along with | |
22 | * this program; if not, write to the Free Software Foundation, Inc., | |
23 | * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. | |
24 | * | |
25 | */ | |
26 | #include <linux/kernel.h> | |
27 | #include <linux/interrupt.h> | |
28 | #include <linux/mm.h> | |
29 | #include <linux/dma-mapping.h> | |
30 | #include <linux/raid/xor.h> | |
31 | #include <linux/async_tx.h> | |
32 | ||
06164f31 DW |
33 | /* do_async_xor - dma map the pages and perform the xor with an engine */ |
34 | static __async_inline struct dma_async_tx_descriptor * | |
1e55db2d | 35 | do_async_xor(struct dma_chan *chan, struct page *dest, struct page **src_list, |
04ce9ab3 | 36 | unsigned int offset, int src_cnt, size_t len, dma_addr_t *dma_src, |
a08abd8c | 37 | struct async_submit_ctl *submit) |
9bc89cd8 | 38 | { |
1e55db2d | 39 | struct dma_device *dma = chan->device; |
1e55db2d DW |
40 | struct dma_async_tx_descriptor *tx = NULL; |
41 | int src_off = 0; | |
9bc89cd8 | 42 | int i; |
a08abd8c DW |
43 | dma_async_tx_callback cb_fn_orig = submit->cb_fn; |
44 | void *cb_param_orig = submit->cb_param; | |
45 | enum async_tx_flags flags_orig = submit->flags; | |
1e55db2d | 46 | enum dma_ctrl_flags dma_flags; |
b2141e69 | 47 | int xor_src_cnt = 0; |
1e55db2d | 48 | dma_addr_t dma_dest; |
9bc89cd8 | 49 | |
a06d568f DW |
50 | /* map the dest bidrectional in case it is re-used as a source */ |
51 | dma_dest = dma_map_page(dma->dev, dest, offset, len, DMA_BIDIRECTIONAL); | |
52 | for (i = 0; i < src_cnt; i++) { | |
53 | /* only map the dest once */ | |
b2141e69 N |
54 | if (!src_list[i]) |
55 | continue; | |
a06d568f | 56 | if (unlikely(src_list[i] == dest)) { |
b2141e69 | 57 | dma_src[xor_src_cnt++] = dma_dest; |
a06d568f DW |
58 | continue; |
59 | } | |
b2141e69 N |
60 | dma_src[xor_src_cnt++] = dma_map_page(dma->dev, src_list[i], offset, |
61 | len, DMA_TO_DEVICE); | |
a06d568f | 62 | } |
b2141e69 | 63 | src_cnt = xor_src_cnt; |
0036731c | 64 | |
1e55db2d | 65 | while (src_cnt) { |
a08abd8c | 66 | submit->flags = flags_orig; |
1e55db2d | 67 | dma_flags = 0; |
b2f46fd8 | 68 | xor_src_cnt = min(src_cnt, (int)dma->max_xor); |
1e55db2d DW |
69 | /* if we are submitting additional xors, leave the chain open, |
70 | * clear the callback parameters, and leave the destination | |
71 | * buffer mapped | |
72 | */ | |
73 | if (src_cnt > xor_src_cnt) { | |
a08abd8c | 74 | submit->flags &= ~ASYNC_TX_ACK; |
0403e382 | 75 | submit->flags |= ASYNC_TX_FENCE; |
1e55db2d | 76 | dma_flags = DMA_COMPL_SKIP_DEST_UNMAP; |
a08abd8c DW |
77 | submit->cb_fn = NULL; |
78 | submit->cb_param = NULL; | |
1e55db2d | 79 | } else { |
a08abd8c DW |
80 | submit->cb_fn = cb_fn_orig; |
81 | submit->cb_param = cb_param_orig; | |
1e55db2d | 82 | } |
a08abd8c | 83 | if (submit->cb_fn) |
1e55db2d | 84 | dma_flags |= DMA_PREP_INTERRUPT; |
0403e382 DW |
85 | if (submit->flags & ASYNC_TX_FENCE) |
86 | dma_flags |= DMA_PREP_FENCE; | |
1e55db2d DW |
87 | /* Since we have clobbered the src_list we are committed |
88 | * to doing this asynchronously. Drivers force forward progress | |
89 | * in case they can not provide a descriptor | |
90 | */ | |
91 | tx = dma->device_prep_dma_xor(chan, dma_dest, &dma_src[src_off], | |
92 | xor_src_cnt, len, dma_flags); | |
93 | ||
669ab0b2 | 94 | if (unlikely(!tx)) |
a08abd8c | 95 | async_tx_quiesce(&submit->depend_tx); |
0036731c | 96 | |
1e55db2d | 97 | /* spin wait for the preceeding transactions to complete */ |
669ab0b2 DW |
98 | while (unlikely(!tx)) { |
99 | dma_async_issue_pending(chan); | |
1e55db2d DW |
100 | tx = dma->device_prep_dma_xor(chan, dma_dest, |
101 | &dma_src[src_off], | |
102 | xor_src_cnt, len, | |
103 | dma_flags); | |
669ab0b2 | 104 | } |
9bc89cd8 | 105 | |
a08abd8c DW |
106 | async_tx_submit(chan, tx, submit); |
107 | submit->depend_tx = tx; | |
1e55db2d DW |
108 | |
109 | if (src_cnt > xor_src_cnt) { | |
110 | /* drop completed sources */ | |
111 | src_cnt -= xor_src_cnt; | |
112 | src_off += xor_src_cnt; | |
113 | ||
114 | /* use the intermediate result a source */ | |
115 | dma_src[--src_off] = dma_dest; | |
116 | src_cnt++; | |
117 | } else | |
118 | break; | |
119 | } | |
0036731c DW |
120 | |
121 | return tx; | |
9bc89cd8 DW |
122 | } |
123 | ||
124 | static void | |
125 | do_sync_xor(struct page *dest, struct page **src_list, unsigned int offset, | |
a08abd8c | 126 | int src_cnt, size_t len, struct async_submit_ctl *submit) |
9bc89cd8 | 127 | { |
9bc89cd8 | 128 | int i; |
b2141e69 | 129 | int xor_src_cnt = 0; |
1e55db2d DW |
130 | int src_off = 0; |
131 | void *dest_buf; | |
04ce9ab3 | 132 | void **srcs; |
9bc89cd8 | 133 | |
04ce9ab3 DW |
134 | if (submit->scribble) |
135 | srcs = submit->scribble; | |
136 | else | |
137 | srcs = (void **) src_list; | |
138 | ||
139 | /* convert to buffer pointers */ | |
9bc89cd8 | 140 | for (i = 0; i < src_cnt; i++) |
b2141e69 N |
141 | if (src_list[i]) |
142 | srcs[xor_src_cnt++] = page_address(src_list[i]) + offset; | |
143 | src_cnt = xor_src_cnt; | |
9bc89cd8 | 144 | /* set destination address */ |
1e55db2d | 145 | dest_buf = page_address(dest) + offset; |
9bc89cd8 | 146 | |
a08abd8c | 147 | if (submit->flags & ASYNC_TX_XOR_ZERO_DST) |
1e55db2d | 148 | memset(dest_buf, 0, len); |
9bc89cd8 | 149 | |
1e55db2d DW |
150 | while (src_cnt > 0) { |
151 | /* process up to 'MAX_XOR_BLOCKS' sources */ | |
152 | xor_src_cnt = min(src_cnt, MAX_XOR_BLOCKS); | |
153 | xor_blocks(xor_src_cnt, len, dest_buf, &srcs[src_off]); | |
154 | ||
155 | /* drop completed sources */ | |
156 | src_cnt -= xor_src_cnt; | |
157 | src_off += xor_src_cnt; | |
158 | } | |
9bc89cd8 | 159 | |
a08abd8c | 160 | async_tx_sync_epilog(submit); |
9bc89cd8 DW |
161 | } |
162 | ||
163 | /** | |
164 | * async_xor - attempt to xor a set of blocks with a dma engine. | |
9bc89cd8 | 165 | * @dest: destination page |
a08abd8c DW |
166 | * @src_list: array of source pages |
167 | * @offset: common src/dst offset to start transaction | |
9bc89cd8 DW |
168 | * @src_cnt: number of source pages |
169 | * @len: length in bytes | |
a08abd8c DW |
170 | * @submit: submission / completion modifiers |
171 | * | |
172 | * honored flags: ASYNC_TX_ACK, ASYNC_TX_XOR_ZERO_DST, ASYNC_TX_XOR_DROP_DST | |
173 | * | |
174 | * xor_blocks always uses the dest as a source so the | |
175 | * ASYNC_TX_XOR_ZERO_DST flag must be set to not include dest data in | |
176 | * the calculation. The assumption with dma eninges is that they only | |
177 | * use the destination buffer as a source when it is explicity specified | |
178 | * in the source list. | |
179 | * | |
180 | * src_list note: if the dest is also a source it must be at index zero. | |
181 | * The contents of this array will be overwritten if a scribble region | |
182 | * is not specified. | |
9bc89cd8 DW |
183 | */ |
184 | struct dma_async_tx_descriptor * | |
185 | async_xor(struct page *dest, struct page **src_list, unsigned int offset, | |
a08abd8c | 186 | int src_cnt, size_t len, struct async_submit_ctl *submit) |
9bc89cd8 | 187 | { |
a08abd8c | 188 | struct dma_chan *chan = async_tx_find_channel(submit, DMA_XOR, |
47437b2c DW |
189 | &dest, 1, src_list, |
190 | src_cnt, len); | |
04ce9ab3 DW |
191 | dma_addr_t *dma_src = NULL; |
192 | ||
9bc89cd8 DW |
193 | BUG_ON(src_cnt <= 1); |
194 | ||
04ce9ab3 DW |
195 | if (submit->scribble) |
196 | dma_src = submit->scribble; | |
197 | else if (sizeof(dma_addr_t) <= sizeof(struct page *)) | |
198 | dma_src = (dma_addr_t *) src_list; | |
199 | ||
83544ae9 | 200 | if (dma_src && chan && is_dma_xor_aligned(chan->device, offset, 0, len)) { |
1e55db2d DW |
201 | /* run the xor asynchronously */ |
202 | pr_debug("%s (async): len: %zu\n", __func__, len); | |
9bc89cd8 | 203 | |
1e55db2d | 204 | return do_async_xor(chan, dest, src_list, offset, src_cnt, len, |
04ce9ab3 | 205 | dma_src, submit); |
1e55db2d DW |
206 | } else { |
207 | /* run the xor synchronously */ | |
208 | pr_debug("%s (sync): len: %zu\n", __func__, len); | |
04ce9ab3 DW |
209 | WARN_ONCE(chan, "%s: no space for dma address conversion\n", |
210 | __func__); | |
9bc89cd8 | 211 | |
1e55db2d DW |
212 | /* in the sync case the dest is an implied source |
213 | * (assumes the dest is the first source) | |
9bc89cd8 | 214 | */ |
a08abd8c | 215 | if (submit->flags & ASYNC_TX_XOR_DROP_DST) { |
1e55db2d DW |
216 | src_cnt--; |
217 | src_list++; | |
218 | } | |
9bc89cd8 | 219 | |
1e55db2d | 220 | /* wait for any prerequisite operations */ |
a08abd8c | 221 | async_tx_quiesce(&submit->depend_tx); |
9bc89cd8 | 222 | |
a08abd8c | 223 | do_sync_xor(dest, src_list, offset, src_cnt, len, submit); |
9bc89cd8 | 224 | |
1e55db2d | 225 | return NULL; |
9bc89cd8 | 226 | } |
9bc89cd8 DW |
227 | } |
228 | EXPORT_SYMBOL_GPL(async_xor); | |
229 | ||
230 | static int page_is_zero(struct page *p, unsigned int offset, size_t len) | |
231 | { | |
232 | char *a = page_address(p) + offset; | |
233 | return ((*(u32 *) a) == 0 && | |
234 | memcmp(a, a + 4, len - 4) == 0); | |
235 | } | |
236 | ||
7b3cc2b1 DW |
237 | static inline struct dma_chan * |
238 | xor_val_chan(struct async_submit_ctl *submit, struct page *dest, | |
239 | struct page **src_list, int src_cnt, size_t len) | |
240 | { | |
241 | #ifdef CONFIG_ASYNC_TX_DISABLE_XOR_VAL_DMA | |
242 | return NULL; | |
243 | #endif | |
244 | return async_tx_find_channel(submit, DMA_XOR_VAL, &dest, 1, src_list, | |
245 | src_cnt, len); | |
246 | } | |
247 | ||
9bc89cd8 | 248 | /** |
099f53cb | 249 | * async_xor_val - attempt a xor parity check with a dma engine. |
9bc89cd8 | 250 | * @dest: destination page used if the xor is performed synchronously |
a08abd8c | 251 | * @src_list: array of source pages |
9bc89cd8 DW |
252 | * @offset: offset in pages to start transaction |
253 | * @src_cnt: number of source pages | |
254 | * @len: length in bytes | |
255 | * @result: 0 if sum == 0 else non-zero | |
a08abd8c DW |
256 | * @submit: submission / completion modifiers |
257 | * | |
258 | * honored flags: ASYNC_TX_ACK | |
259 | * | |
260 | * src_list note: if the dest is also a source it must be at index zero. | |
261 | * The contents of this array will be overwritten if a scribble region | |
262 | * is not specified. | |
9bc89cd8 DW |
263 | */ |
264 | struct dma_async_tx_descriptor * | |
a08abd8c | 265 | async_xor_val(struct page *dest, struct page **src_list, unsigned int offset, |
ad283ea4 | 266 | int src_cnt, size_t len, enum sum_check_flags *result, |
a08abd8c | 267 | struct async_submit_ctl *submit) |
9bc89cd8 | 268 | { |
7b3cc2b1 | 269 | struct dma_chan *chan = xor_val_chan(submit, dest, src_list, src_cnt, len); |
9bc89cd8 | 270 | struct dma_device *device = chan ? chan->device : NULL; |
0036731c | 271 | struct dma_async_tx_descriptor *tx = NULL; |
04ce9ab3 | 272 | dma_addr_t *dma_src = NULL; |
9bc89cd8 DW |
273 | |
274 | BUG_ON(src_cnt <= 1); | |
275 | ||
04ce9ab3 DW |
276 | if (submit->scribble) |
277 | dma_src = submit->scribble; | |
278 | else if (sizeof(dma_addr_t) <= sizeof(struct page *)) | |
279 | dma_src = (dma_addr_t *) src_list; | |
280 | ||
83544ae9 DW |
281 | if (dma_src && device && src_cnt <= device->max_xor && |
282 | is_dma_xor_aligned(device, offset, 0, len)) { | |
0403e382 | 283 | unsigned long dma_prep_flags = 0; |
0036731c | 284 | int i; |
9bc89cd8 | 285 | |
3280ab3e | 286 | pr_debug("%s: (async) len: %zu\n", __func__, len); |
9bc89cd8 | 287 | |
0403e382 DW |
288 | if (submit->cb_fn) |
289 | dma_prep_flags |= DMA_PREP_INTERRUPT; | |
290 | if (submit->flags & ASYNC_TX_FENCE) | |
291 | dma_prep_flags |= DMA_PREP_FENCE; | |
0036731c DW |
292 | for (i = 0; i < src_cnt; i++) |
293 | dma_src[i] = dma_map_page(device->dev, src_list[i], | |
294 | offset, len, DMA_TO_DEVICE); | |
295 | ||
099f53cb DW |
296 | tx = device->device_prep_dma_xor_val(chan, dma_src, src_cnt, |
297 | len, result, | |
298 | dma_prep_flags); | |
669ab0b2 | 299 | if (unlikely(!tx)) { |
a08abd8c | 300 | async_tx_quiesce(&submit->depend_tx); |
0036731c | 301 | |
e34a8ae7 | 302 | while (!tx) { |
669ab0b2 | 303 | dma_async_issue_pending(chan); |
099f53cb | 304 | tx = device->device_prep_dma_xor_val(chan, |
0036731c | 305 | dma_src, src_cnt, len, result, |
d4c56f97 | 306 | dma_prep_flags); |
e34a8ae7 | 307 | } |
9bc89cd8 DW |
308 | } |
309 | ||
a08abd8c | 310 | async_tx_submit(chan, tx, submit); |
9bc89cd8 | 311 | } else { |
a08abd8c | 312 | enum async_tx_flags flags_orig = submit->flags; |
9bc89cd8 | 313 | |
3280ab3e | 314 | pr_debug("%s: (sync) len: %zu\n", __func__, len); |
04ce9ab3 DW |
315 | WARN_ONCE(device && src_cnt <= device->max_xor, |
316 | "%s: no space for dma address conversion\n", | |
317 | __func__); | |
9bc89cd8 | 318 | |
a08abd8c DW |
319 | submit->flags |= ASYNC_TX_XOR_DROP_DST; |
320 | submit->flags &= ~ASYNC_TX_ACK; | |
9bc89cd8 | 321 | |
a08abd8c | 322 | tx = async_xor(dest, src_list, offset, src_cnt, len, submit); |
9bc89cd8 | 323 | |
d2c52b79 | 324 | async_tx_quiesce(&tx); |
9bc89cd8 | 325 | |
ad283ea4 | 326 | *result = !page_is_zero(dest, offset, len) << SUM_CHECK_P; |
9bc89cd8 | 327 | |
a08abd8c DW |
328 | async_tx_sync_epilog(submit); |
329 | submit->flags = flags_orig; | |
9bc89cd8 DW |
330 | } |
331 | ||
332 | return tx; | |
333 | } | |
099f53cb | 334 | EXPORT_SYMBOL_GPL(async_xor_val); |
9bc89cd8 | 335 | |
9bc89cd8 DW |
336 | MODULE_AUTHOR("Intel Corporation"); |
337 | MODULE_DESCRIPTION("asynchronous xor/xor-zero-sum api"); | |
338 | MODULE_LICENSE("GPL"); |