Commit | Line | Data |
---|---|---|
f58b082a RW |
1 | /* |
2 | * ACPI support for Intel Lynxpoint LPSS. | |
3 | * | |
3df2da96 | 4 | * Copyright (C) 2013, Intel Corporation |
f58b082a RW |
5 | * Authors: Mika Westerberg <mika.westerberg@linux.intel.com> |
6 | * Rafael J. Wysocki <rafael.j.wysocki@intel.com> | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License version 2 as | |
10 | * published by the Free Software Foundation. | |
11 | */ | |
12 | ||
13 | #include <linux/acpi.h> | |
f58b082a RW |
14 | #include <linux/clkdev.h> |
15 | #include <linux/clk-provider.h> | |
16 | #include <linux/err.h> | |
17 | #include <linux/io.h> | |
eebb3e8d | 18 | #include <linux/mutex.h> |
f58b082a RW |
19 | #include <linux/platform_device.h> |
20 | #include <linux/platform_data/clk-lpss.h> | |
989561de | 21 | #include <linux/pm_domain.h> |
2e0f8822 | 22 | #include <linux/pm_runtime.h> |
c78b0830 | 23 | #include <linux/delay.h> |
f58b082a RW |
24 | |
25 | #include "internal.h" | |
26 | ||
27 | ACPI_MODULE_NAME("acpi_lpss"); | |
28 | ||
d6ddaaac RW |
29 | #ifdef CONFIG_X86_INTEL_LPSS |
30 | ||
eebb3e8d | 31 | #include <asm/cpu_device_id.h> |
4626d840 | 32 | #include <asm/intel-family.h> |
eebb3e8d AS |
33 | #include <asm/iosf_mbi.h> |
34 | #include <asm/pmc_atom.h> | |
35 | ||
d6ddaaac RW |
36 | #define LPSS_ADDR(desc) ((unsigned long)&desc) |
37 | ||
f58b082a | 38 | #define LPSS_CLK_SIZE 0x04 |
2e0f8822 RW |
39 | #define LPSS_LTR_SIZE 0x18 |
40 | ||
41 | /* Offsets relative to LPSS_PRIVATE_OFFSET */ | |
ed3a872e | 42 | #define LPSS_CLK_DIVIDER_DEF_MASK (BIT(1) | BIT(16)) |
765bdd4e MW |
43 | #define LPSS_RESETS 0x04 |
44 | #define LPSS_RESETS_RESET_FUNC BIT(0) | |
45 | #define LPSS_RESETS_RESET_APB BIT(1) | |
2e0f8822 RW |
46 | #define LPSS_GENERAL 0x08 |
47 | #define LPSS_GENERAL_LTR_MODE_SW BIT(2) | |
088f1fd2 | 48 | #define LPSS_GENERAL_UART_RTS_OVRD BIT(3) |
2e0f8822 RW |
49 | #define LPSS_SW_LTR 0x10 |
50 | #define LPSS_AUTO_LTR 0x14 | |
1a8f8351 RW |
51 | #define LPSS_LTR_SNOOP_REQ BIT(15) |
52 | #define LPSS_LTR_SNOOP_MASK 0x0000FFFF | |
53 | #define LPSS_LTR_SNOOP_LAT_1US 0x800 | |
54 | #define LPSS_LTR_SNOOP_LAT_32US 0xC00 | |
55 | #define LPSS_LTR_SNOOP_LAT_SHIFT 5 | |
56 | #define LPSS_LTR_SNOOP_LAT_CUTOFF 3000 | |
57 | #define LPSS_LTR_MAX_VAL 0x3FF | |
06d86415 HK |
58 | #define LPSS_TX_INT 0x20 |
59 | #define LPSS_TX_INT_MASK BIT(1) | |
f58b082a | 60 | |
c78b0830 HK |
61 | #define LPSS_PRV_REG_COUNT 9 |
62 | ||
ff8c1af5 HK |
63 | /* LPSS Flags */ |
64 | #define LPSS_CLK BIT(0) | |
65 | #define LPSS_CLK_GATE BIT(1) | |
66 | #define LPSS_CLK_DIVIDER BIT(2) | |
67 | #define LPSS_LTR BIT(3) | |
68 | #define LPSS_SAVE_CTX BIT(4) | |
b00855ae | 69 | #define LPSS_NO_D3_DELAY BIT(5) |
f6272170 | 70 | |
06d86415 | 71 | struct lpss_private_data; |
f58b082a RW |
72 | |
73 | struct lpss_device_desc { | |
ff8c1af5 | 74 | unsigned int flags; |
fcf0789a | 75 | const char *clk_con_id; |
2e0f8822 | 76 | unsigned int prv_offset; |
958c4eb2 | 77 | size_t prv_size_override; |
06d86415 | 78 | void (*setup)(struct lpss_private_data *pdata); |
f58b082a RW |
79 | }; |
80 | ||
eebb3e8d | 81 | static const struct lpss_device_desc lpss_dma_desc = { |
3df2da96 | 82 | .flags = LPSS_CLK, |
b59cc200 RW |
83 | }; |
84 | ||
f58b082a RW |
85 | struct lpss_private_data { |
86 | void __iomem *mmio_base; | |
87 | resource_size_t mmio_size; | |
03f09f73 | 88 | unsigned int fixed_clk_rate; |
f58b082a RW |
89 | struct clk *clk; |
90 | const struct lpss_device_desc *dev_desc; | |
c78b0830 | 91 | u32 prv_reg_ctx[LPSS_PRV_REG_COUNT]; |
f58b082a RW |
92 | }; |
93 | ||
eebb3e8d AS |
94 | /* LPSS run time quirks */ |
95 | static unsigned int lpss_quirks; | |
96 | ||
97 | /* | |
98 | * LPSS_QUIRK_ALWAYS_POWER_ON: override power state for LPSS DMA device. | |
99 | * | |
fa9e93b1 | 100 | * The LPSS DMA controller has neither _PS0 nor _PS3 method. Moreover |
eebb3e8d AS |
101 | * it can be powered off automatically whenever the last LPSS device goes down. |
102 | * In case of no power any access to the DMA controller will hang the system. | |
103 | * The behaviour is reproduced on some HP laptops based on Intel BayTrail as | |
104 | * well as on ASuS T100TA transformer. | |
105 | * | |
106 | * This quirk overrides power state of entire LPSS island to keep DMA powered | |
107 | * on whenever we have at least one other device in use. | |
108 | */ | |
109 | #define LPSS_QUIRK_ALWAYS_POWER_ON BIT(0) | |
110 | ||
1f47a77c HK |
111 | /* UART Component Parameter Register */ |
112 | #define LPSS_UART_CPR 0xF4 | |
113 | #define LPSS_UART_CPR_AFCE BIT(4) | |
114 | ||
06d86415 HK |
115 | static void lpss_uart_setup(struct lpss_private_data *pdata) |
116 | { | |
088f1fd2 | 117 | unsigned int offset; |
1f47a77c | 118 | u32 val; |
06d86415 | 119 | |
088f1fd2 | 120 | offset = pdata->dev_desc->prv_offset + LPSS_TX_INT; |
1f47a77c HK |
121 | val = readl(pdata->mmio_base + offset); |
122 | writel(val | LPSS_TX_INT_MASK, pdata->mmio_base + offset); | |
123 | ||
124 | val = readl(pdata->mmio_base + LPSS_UART_CPR); | |
125 | if (!(val & LPSS_UART_CPR_AFCE)) { | |
126 | offset = pdata->dev_desc->prv_offset + LPSS_GENERAL; | |
127 | val = readl(pdata->mmio_base + offset); | |
128 | val |= LPSS_GENERAL_UART_RTS_OVRD; | |
129 | writel(val, pdata->mmio_base + offset); | |
130 | } | |
06d86415 HK |
131 | } |
132 | ||
3095794a | 133 | static void lpss_deassert_reset(struct lpss_private_data *pdata) |
765bdd4e MW |
134 | { |
135 | unsigned int offset; | |
136 | u32 val; | |
137 | ||
138 | offset = pdata->dev_desc->prv_offset + LPSS_RESETS; | |
139 | val = readl(pdata->mmio_base + offset); | |
140 | val |= LPSS_RESETS_RESET_APB | LPSS_RESETS_RESET_FUNC; | |
141 | writel(val, pdata->mmio_base + offset); | |
3095794a MW |
142 | } |
143 | ||
144 | #define LPSS_I2C_ENABLE 0x6c | |
145 | ||
146 | static void byt_i2c_setup(struct lpss_private_data *pdata) | |
147 | { | |
148 | lpss_deassert_reset(pdata); | |
765bdd4e | 149 | |
03f09f73 HK |
150 | if (readl(pdata->mmio_base + pdata->dev_desc->prv_offset)) |
151 | pdata->fixed_clk_rate = 133000000; | |
3293c7b8 MW |
152 | |
153 | writel(0, pdata->mmio_base + LPSS_I2C_ENABLE); | |
765bdd4e | 154 | } |
43218a1b | 155 | |
b2687cd7 | 156 | static const struct lpss_device_desc lpt_dev_desc = { |
ff8c1af5 | 157 | .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_LTR, |
ed3a872e | 158 | .prv_offset = 0x800, |
ed3a872e HK |
159 | }; |
160 | ||
b2687cd7 | 161 | static const struct lpss_device_desc lpt_i2c_dev_desc = { |
ff8c1af5 | 162 | .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_LTR, |
2e0f8822 | 163 | .prv_offset = 0x800, |
2e0f8822 RW |
164 | }; |
165 | ||
b2687cd7 | 166 | static const struct lpss_device_desc lpt_uart_dev_desc = { |
ff8c1af5 | 167 | .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_LTR, |
fcf0789a | 168 | .clk_con_id = "baudclk", |
06d86415 | 169 | .prv_offset = 0x800, |
06d86415 | 170 | .setup = lpss_uart_setup, |
2e0f8822 RW |
171 | }; |
172 | ||
b2687cd7 | 173 | static const struct lpss_device_desc lpt_sdio_dev_desc = { |
ff8c1af5 | 174 | .flags = LPSS_LTR, |
2e0f8822 | 175 | .prv_offset = 0x1000, |
958c4eb2 | 176 | .prv_size_override = 0x1018, |
e1c74817 CCE |
177 | }; |
178 | ||
b2687cd7 | 179 | static const struct lpss_device_desc byt_pwm_dev_desc = { |
3f56bf3e | 180 | .flags = LPSS_SAVE_CTX, |
e1c74817 CCE |
181 | }; |
182 | ||
b00855ae SK |
183 | static const struct lpss_device_desc bsw_pwm_dev_desc = { |
184 | .flags = LPSS_SAVE_CTX | LPSS_NO_D3_DELAY, | |
185 | }; | |
186 | ||
b2687cd7 | 187 | static const struct lpss_device_desc byt_uart_dev_desc = { |
3df2da96 | 188 | .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_SAVE_CTX, |
fcf0789a | 189 | .clk_con_id = "baudclk", |
f6272170 | 190 | .prv_offset = 0x800, |
06d86415 | 191 | .setup = lpss_uart_setup, |
f6272170 MW |
192 | }; |
193 | ||
b00855ae SK |
194 | static const struct lpss_device_desc bsw_uart_dev_desc = { |
195 | .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_SAVE_CTX | |
196 | | LPSS_NO_D3_DELAY, | |
197 | .clk_con_id = "baudclk", | |
198 | .prv_offset = 0x800, | |
199 | .setup = lpss_uart_setup, | |
200 | }; | |
201 | ||
b2687cd7 | 202 | static const struct lpss_device_desc byt_spi_dev_desc = { |
3df2da96 | 203 | .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_SAVE_CTX, |
f6272170 | 204 | .prv_offset = 0x400, |
f6272170 MW |
205 | }; |
206 | ||
b2687cd7 | 207 | static const struct lpss_device_desc byt_sdio_dev_desc = { |
3df2da96 | 208 | .flags = LPSS_CLK, |
f6272170 MW |
209 | }; |
210 | ||
b2687cd7 | 211 | static const struct lpss_device_desc byt_i2c_dev_desc = { |
3df2da96 | 212 | .flags = LPSS_CLK | LPSS_SAVE_CTX, |
f6272170 | 213 | .prv_offset = 0x800, |
03f09f73 | 214 | .setup = byt_i2c_setup, |
1bfbd8eb AC |
215 | }; |
216 | ||
b00855ae SK |
217 | static const struct lpss_device_desc bsw_i2c_dev_desc = { |
218 | .flags = LPSS_CLK | LPSS_SAVE_CTX | LPSS_NO_D3_DELAY, | |
219 | .prv_offset = 0x800, | |
220 | .setup = byt_i2c_setup, | |
221 | }; | |
222 | ||
eebb3e8d | 223 | static const struct lpss_device_desc bsw_spi_dev_desc = { |
b00855ae SK |
224 | .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_SAVE_CTX |
225 | | LPSS_NO_D3_DELAY, | |
3095794a MW |
226 | .prv_offset = 0x400, |
227 | .setup = lpss_deassert_reset, | |
228 | }; | |
229 | ||
eebb3e8d AS |
230 | #define ICPU(model) { X86_VENDOR_INTEL, 6, model, X86_FEATURE_ANY, } |
231 | ||
232 | static const struct x86_cpu_id lpss_cpu_ids[] = { | |
4626d840 DH |
233 | ICPU(INTEL_FAM6_ATOM_SILVERMONT1), /* Valleyview, Bay Trail */ |
234 | ICPU(INTEL_FAM6_ATOM_AIRMONT), /* Braswell, Cherry Trail */ | |
eebb3e8d AS |
235 | {} |
236 | }; | |
237 | ||
d6ddaaac RW |
238 | #else |
239 | ||
240 | #define LPSS_ADDR(desc) (0UL) | |
241 | ||
242 | #endif /* CONFIG_X86_INTEL_LPSS */ | |
243 | ||
f58b082a | 244 | static const struct acpi_device_id acpi_lpss_device_ids[] = { |
b59cc200 | 245 | /* Generic LPSS devices */ |
d6ddaaac | 246 | { "INTL9C60", LPSS_ADDR(lpss_dma_desc) }, |
b59cc200 | 247 | |
f58b082a | 248 | /* Lynxpoint LPSS devices */ |
d6ddaaac RW |
249 | { "INT33C0", LPSS_ADDR(lpt_dev_desc) }, |
250 | { "INT33C1", LPSS_ADDR(lpt_dev_desc) }, | |
251 | { "INT33C2", LPSS_ADDR(lpt_i2c_dev_desc) }, | |
252 | { "INT33C3", LPSS_ADDR(lpt_i2c_dev_desc) }, | |
253 | { "INT33C4", LPSS_ADDR(lpt_uart_dev_desc) }, | |
254 | { "INT33C5", LPSS_ADDR(lpt_uart_dev_desc) }, | |
255 | { "INT33C6", LPSS_ADDR(lpt_sdio_dev_desc) }, | |
f58b082a RW |
256 | { "INT33C7", }, |
257 | ||
f6272170 | 258 | /* BayTrail LPSS devices */ |
d6ddaaac RW |
259 | { "80860F09", LPSS_ADDR(byt_pwm_dev_desc) }, |
260 | { "80860F0A", LPSS_ADDR(byt_uart_dev_desc) }, | |
261 | { "80860F0E", LPSS_ADDR(byt_spi_dev_desc) }, | |
262 | { "80860F14", LPSS_ADDR(byt_sdio_dev_desc) }, | |
263 | { "80860F41", LPSS_ADDR(byt_i2c_dev_desc) }, | |
f6272170 | 264 | { "INT33B2", }, |
20482d32 | 265 | { "INT33FC", }, |
f6272170 | 266 | |
1bfbd8eb | 267 | /* Braswell LPSS devices */ |
b00855ae SK |
268 | { "80862288", LPSS_ADDR(bsw_pwm_dev_desc) }, |
269 | { "8086228A", LPSS_ADDR(bsw_uart_dev_desc) }, | |
3095794a | 270 | { "8086228E", LPSS_ADDR(bsw_spi_dev_desc) }, |
b00855ae | 271 | { "808622C1", LPSS_ADDR(bsw_i2c_dev_desc) }, |
1bfbd8eb | 272 | |
b00855ae | 273 | /* Broadwell LPSS devices */ |
d6ddaaac RW |
274 | { "INT3430", LPSS_ADDR(lpt_dev_desc) }, |
275 | { "INT3431", LPSS_ADDR(lpt_dev_desc) }, | |
276 | { "INT3432", LPSS_ADDR(lpt_i2c_dev_desc) }, | |
277 | { "INT3433", LPSS_ADDR(lpt_i2c_dev_desc) }, | |
278 | { "INT3434", LPSS_ADDR(lpt_uart_dev_desc) }, | |
279 | { "INT3435", LPSS_ADDR(lpt_uart_dev_desc) }, | |
280 | { "INT3436", LPSS_ADDR(lpt_sdio_dev_desc) }, | |
a4d97536 MW |
281 | { "INT3437", }, |
282 | ||
ff8c1af5 HK |
283 | /* Wildcat Point LPSS devices */ |
284 | { "INT3438", LPSS_ADDR(lpt_dev_desc) }, | |
43218a1b | 285 | |
f58b082a RW |
286 | { } |
287 | }; | |
288 | ||
d6ddaaac RW |
289 | #ifdef CONFIG_X86_INTEL_LPSS |
290 | ||
f58b082a RW |
291 | static int is_memory(struct acpi_resource *res, void *not_used) |
292 | { | |
293 | struct resource r; | |
294 | return !acpi_dev_resource_memory(res, &r); | |
295 | } | |
296 | ||
297 | /* LPSS main clock device. */ | |
298 | static struct platform_device *lpss_clk_dev; | |
299 | ||
300 | static inline void lpt_register_clock_device(void) | |
301 | { | |
302 | lpss_clk_dev = platform_device_register_simple("clk-lpt", -1, NULL, 0); | |
303 | } | |
304 | ||
305 | static int register_device_clock(struct acpi_device *adev, | |
306 | struct lpss_private_data *pdata) | |
307 | { | |
308 | const struct lpss_device_desc *dev_desc = pdata->dev_desc; | |
ed3a872e | 309 | const char *devname = dev_name(&adev->dev); |
f6272170 | 310 | struct clk *clk = ERR_PTR(-ENODEV); |
b59cc200 | 311 | struct lpss_clk_data *clk_data; |
ed3a872e HK |
312 | const char *parent, *clk_name; |
313 | void __iomem *prv_base; | |
f58b082a RW |
314 | |
315 | if (!lpss_clk_dev) | |
316 | lpt_register_clock_device(); | |
317 | ||
b59cc200 RW |
318 | clk_data = platform_get_drvdata(lpss_clk_dev); |
319 | if (!clk_data) | |
320 | return -ENODEV; | |
b0d00f8b | 321 | clk = clk_data->clk; |
b59cc200 RW |
322 | |
323 | if (!pdata->mmio_base | |
2e0f8822 | 324 | || pdata->mmio_size < dev_desc->prv_offset + LPSS_CLK_SIZE) |
f58b082a RW |
325 | return -ENODATA; |
326 | ||
f6272170 | 327 | parent = clk_data->name; |
ed3a872e | 328 | prv_base = pdata->mmio_base + dev_desc->prv_offset; |
f6272170 | 329 | |
03f09f73 HK |
330 | if (pdata->fixed_clk_rate) { |
331 | clk = clk_register_fixed_rate(NULL, devname, parent, 0, | |
332 | pdata->fixed_clk_rate); | |
333 | goto out; | |
f6272170 MW |
334 | } |
335 | ||
ff8c1af5 | 336 | if (dev_desc->flags & LPSS_CLK_GATE) { |
ed3a872e HK |
337 | clk = clk_register_gate(NULL, devname, parent, 0, |
338 | prv_base, 0, 0, NULL); | |
339 | parent = devname; | |
340 | } | |
341 | ||
ff8c1af5 | 342 | if (dev_desc->flags & LPSS_CLK_DIVIDER) { |
ed3a872e HK |
343 | /* Prevent division by zero */ |
344 | if (!readl(prv_base)) | |
345 | writel(LPSS_CLK_DIVIDER_DEF_MASK, prv_base); | |
346 | ||
347 | clk_name = kasprintf(GFP_KERNEL, "%s-div", devname); | |
348 | if (!clk_name) | |
349 | return -ENOMEM; | |
350 | clk = clk_register_fractional_divider(NULL, clk_name, parent, | |
351 | 0, prv_base, | |
352 | 1, 15, 16, 15, 0, NULL); | |
353 | parent = clk_name; | |
354 | ||
355 | clk_name = kasprintf(GFP_KERNEL, "%s-update", devname); | |
356 | if (!clk_name) { | |
357 | kfree(parent); | |
358 | return -ENOMEM; | |
359 | } | |
360 | clk = clk_register_gate(NULL, clk_name, parent, | |
361 | CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE, | |
362 | prv_base, 31, 0, NULL); | |
363 | kfree(parent); | |
364 | kfree(clk_name); | |
f6272170 | 365 | } |
03f09f73 | 366 | out: |
f6272170 MW |
367 | if (IS_ERR(clk)) |
368 | return PTR_ERR(clk); | |
f58b082a | 369 | |
ed3a872e | 370 | pdata->clk = clk; |
fcf0789a | 371 | clk_register_clkdev(clk, dev_desc->clk_con_id, devname); |
f58b082a RW |
372 | return 0; |
373 | } | |
374 | ||
375 | static int acpi_lpss_create_device(struct acpi_device *adev, | |
376 | const struct acpi_device_id *id) | |
377 | { | |
b2687cd7 | 378 | const struct lpss_device_desc *dev_desc; |
f58b082a | 379 | struct lpss_private_data *pdata; |
90e97820 | 380 | struct resource_entry *rentry; |
f58b082a | 381 | struct list_head resource_list; |
8ce62f85 | 382 | struct platform_device *pdev; |
f58b082a RW |
383 | int ret; |
384 | ||
b2687cd7 | 385 | dev_desc = (const struct lpss_device_desc *)id->driver_data; |
8ce62f85 RW |
386 | if (!dev_desc) { |
387 | pdev = acpi_create_platform_device(adev); | |
388 | return IS_ERR_OR_NULL(pdev) ? PTR_ERR(pdev) : 1; | |
389 | } | |
f58b082a RW |
390 | pdata = kzalloc(sizeof(*pdata), GFP_KERNEL); |
391 | if (!pdata) | |
392 | return -ENOMEM; | |
393 | ||
394 | INIT_LIST_HEAD(&resource_list); | |
395 | ret = acpi_dev_get_resources(adev, &resource_list, is_memory, NULL); | |
396 | if (ret < 0) | |
397 | goto err_out; | |
398 | ||
399 | list_for_each_entry(rentry, &resource_list, node) | |
90e97820 | 400 | if (resource_type(rentry->res) == IORESOURCE_MEM) { |
958c4eb2 MW |
401 | if (dev_desc->prv_size_override) |
402 | pdata->mmio_size = dev_desc->prv_size_override; | |
403 | else | |
90e97820 JL |
404 | pdata->mmio_size = resource_size(rentry->res); |
405 | pdata->mmio_base = ioremap(rentry->res->start, | |
f58b082a | 406 | pdata->mmio_size); |
f58b082a RW |
407 | break; |
408 | } | |
409 | ||
410 | acpi_dev_free_resource_list(&resource_list); | |
411 | ||
d3e13ff3 RW |
412 | if (!pdata->mmio_base) { |
413 | ret = -ENOMEM; | |
414 | goto err_out; | |
415 | } | |
416 | ||
af65cfe9 MW |
417 | pdata->dev_desc = dev_desc; |
418 | ||
03f09f73 HK |
419 | if (dev_desc->setup) |
420 | dev_desc->setup(pdata); | |
421 | ||
ff8c1af5 | 422 | if (dev_desc->flags & LPSS_CLK) { |
f58b082a RW |
423 | ret = register_device_clock(adev, pdata); |
424 | if (ret) { | |
b9e95fc6 RW |
425 | /* Skip the device, but continue the namespace scan. */ |
426 | ret = 0; | |
427 | goto err_out; | |
f58b082a RW |
428 | } |
429 | } | |
430 | ||
b9e95fc6 RW |
431 | /* |
432 | * This works around a known issue in ACPI tables where LPSS devices | |
433 | * have _PS0 and _PS3 without _PSC (and no power resources), so | |
434 | * acpi_bus_init_power() will assume that the BIOS has put them into D0. | |
435 | */ | |
436 | ret = acpi_device_fix_up_power(adev); | |
437 | if (ret) { | |
438 | /* Skip the device, but continue the namespace scan. */ | |
439 | ret = 0; | |
440 | goto err_out; | |
441 | } | |
442 | ||
f58b082a | 443 | adev->driver_data = pdata; |
8ce62f85 RW |
444 | pdev = acpi_create_platform_device(adev); |
445 | if (!IS_ERR_OR_NULL(pdev)) { | |
8ce62f85 RW |
446 | return 1; |
447 | } | |
f58b082a | 448 | |
8ce62f85 | 449 | ret = PTR_ERR(pdev); |
f58b082a RW |
450 | adev->driver_data = NULL; |
451 | ||
452 | err_out: | |
453 | kfree(pdata); | |
454 | return ret; | |
455 | } | |
456 | ||
1a8f8351 RW |
457 | static u32 __lpss_reg_read(struct lpss_private_data *pdata, unsigned int reg) |
458 | { | |
459 | return readl(pdata->mmio_base + pdata->dev_desc->prv_offset + reg); | |
460 | } | |
461 | ||
462 | static void __lpss_reg_write(u32 val, struct lpss_private_data *pdata, | |
463 | unsigned int reg) | |
464 | { | |
465 | writel(val, pdata->mmio_base + pdata->dev_desc->prv_offset + reg); | |
466 | } | |
467 | ||
2e0f8822 RW |
468 | static int lpss_reg_read(struct device *dev, unsigned int reg, u32 *val) |
469 | { | |
470 | struct acpi_device *adev; | |
471 | struct lpss_private_data *pdata; | |
472 | unsigned long flags; | |
473 | int ret; | |
474 | ||
475 | ret = acpi_bus_get_device(ACPI_HANDLE(dev), &adev); | |
476 | if (WARN_ON(ret)) | |
477 | return ret; | |
478 | ||
479 | spin_lock_irqsave(&dev->power.lock, flags); | |
480 | if (pm_runtime_suspended(dev)) { | |
481 | ret = -EAGAIN; | |
482 | goto out; | |
483 | } | |
484 | pdata = acpi_driver_data(adev); | |
485 | if (WARN_ON(!pdata || !pdata->mmio_base)) { | |
486 | ret = -ENODEV; | |
487 | goto out; | |
488 | } | |
1a8f8351 | 489 | *val = __lpss_reg_read(pdata, reg); |
2e0f8822 RW |
490 | |
491 | out: | |
492 | spin_unlock_irqrestore(&dev->power.lock, flags); | |
493 | return ret; | |
494 | } | |
495 | ||
496 | static ssize_t lpss_ltr_show(struct device *dev, struct device_attribute *attr, | |
497 | char *buf) | |
498 | { | |
499 | u32 ltr_value = 0; | |
500 | unsigned int reg; | |
501 | int ret; | |
502 | ||
503 | reg = strcmp(attr->attr.name, "auto_ltr") ? LPSS_SW_LTR : LPSS_AUTO_LTR; | |
504 | ret = lpss_reg_read(dev, reg, <r_value); | |
505 | if (ret) | |
506 | return ret; | |
507 | ||
508 | return snprintf(buf, PAGE_SIZE, "%08x\n", ltr_value); | |
509 | } | |
510 | ||
511 | static ssize_t lpss_ltr_mode_show(struct device *dev, | |
512 | struct device_attribute *attr, char *buf) | |
513 | { | |
514 | u32 ltr_mode = 0; | |
515 | char *outstr; | |
516 | int ret; | |
517 | ||
518 | ret = lpss_reg_read(dev, LPSS_GENERAL, <r_mode); | |
519 | if (ret) | |
520 | return ret; | |
521 | ||
522 | outstr = (ltr_mode & LPSS_GENERAL_LTR_MODE_SW) ? "sw" : "auto"; | |
523 | return sprintf(buf, "%s\n", outstr); | |
524 | } | |
525 | ||
526 | static DEVICE_ATTR(auto_ltr, S_IRUSR, lpss_ltr_show, NULL); | |
527 | static DEVICE_ATTR(sw_ltr, S_IRUSR, lpss_ltr_show, NULL); | |
528 | static DEVICE_ATTR(ltr_mode, S_IRUSR, lpss_ltr_mode_show, NULL); | |
529 | ||
530 | static struct attribute *lpss_attrs[] = { | |
531 | &dev_attr_auto_ltr.attr, | |
532 | &dev_attr_sw_ltr.attr, | |
533 | &dev_attr_ltr_mode.attr, | |
534 | NULL, | |
535 | }; | |
536 | ||
537 | static struct attribute_group lpss_attr_group = { | |
538 | .attrs = lpss_attrs, | |
539 | .name = "lpss_ltr", | |
540 | }; | |
541 | ||
1a8f8351 RW |
542 | static void acpi_lpss_set_ltr(struct device *dev, s32 val) |
543 | { | |
544 | struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev)); | |
545 | u32 ltr_mode, ltr_val; | |
546 | ||
547 | ltr_mode = __lpss_reg_read(pdata, LPSS_GENERAL); | |
548 | if (val < 0) { | |
549 | if (ltr_mode & LPSS_GENERAL_LTR_MODE_SW) { | |
550 | ltr_mode &= ~LPSS_GENERAL_LTR_MODE_SW; | |
551 | __lpss_reg_write(ltr_mode, pdata, LPSS_GENERAL); | |
552 | } | |
553 | return; | |
554 | } | |
555 | ltr_val = __lpss_reg_read(pdata, LPSS_SW_LTR) & ~LPSS_LTR_SNOOP_MASK; | |
556 | if (val >= LPSS_LTR_SNOOP_LAT_CUTOFF) { | |
557 | ltr_val |= LPSS_LTR_SNOOP_LAT_32US; | |
558 | val = LPSS_LTR_MAX_VAL; | |
559 | } else if (val > LPSS_LTR_MAX_VAL) { | |
560 | ltr_val |= LPSS_LTR_SNOOP_LAT_32US | LPSS_LTR_SNOOP_REQ; | |
561 | val >>= LPSS_LTR_SNOOP_LAT_SHIFT; | |
562 | } else { | |
563 | ltr_val |= LPSS_LTR_SNOOP_LAT_1US | LPSS_LTR_SNOOP_REQ; | |
564 | } | |
565 | ltr_val |= val; | |
566 | __lpss_reg_write(ltr_val, pdata, LPSS_SW_LTR); | |
567 | if (!(ltr_mode & LPSS_GENERAL_LTR_MODE_SW)) { | |
568 | ltr_mode |= LPSS_GENERAL_LTR_MODE_SW; | |
569 | __lpss_reg_write(ltr_mode, pdata, LPSS_GENERAL); | |
570 | } | |
571 | } | |
572 | ||
c78b0830 HK |
573 | #ifdef CONFIG_PM |
574 | /** | |
575 | * acpi_lpss_save_ctx() - Save the private registers of LPSS device | |
576 | * @dev: LPSS device | |
cb39dcdd | 577 | * @pdata: pointer to the private data of the LPSS device |
c78b0830 HK |
578 | * |
579 | * Most LPSS devices have private registers which may loose their context when | |
580 | * the device is powered down. acpi_lpss_save_ctx() saves those registers into | |
581 | * prv_reg_ctx array. | |
582 | */ | |
cb39dcdd AS |
583 | static void acpi_lpss_save_ctx(struct device *dev, |
584 | struct lpss_private_data *pdata) | |
c78b0830 | 585 | { |
c78b0830 HK |
586 | unsigned int i; |
587 | ||
588 | for (i = 0; i < LPSS_PRV_REG_COUNT; i++) { | |
589 | unsigned long offset = i * sizeof(u32); | |
590 | ||
591 | pdata->prv_reg_ctx[i] = __lpss_reg_read(pdata, offset); | |
592 | dev_dbg(dev, "saving 0x%08x from LPSS reg at offset 0x%02lx\n", | |
593 | pdata->prv_reg_ctx[i], offset); | |
594 | } | |
595 | } | |
596 | ||
597 | /** | |
598 | * acpi_lpss_restore_ctx() - Restore the private registers of LPSS device | |
599 | * @dev: LPSS device | |
cb39dcdd | 600 | * @pdata: pointer to the private data of the LPSS device |
c78b0830 HK |
601 | * |
602 | * Restores the registers that were previously stored with acpi_lpss_save_ctx(). | |
603 | */ | |
cb39dcdd AS |
604 | static void acpi_lpss_restore_ctx(struct device *dev, |
605 | struct lpss_private_data *pdata) | |
c78b0830 | 606 | { |
c78b0830 HK |
607 | unsigned int i; |
608 | ||
02b98540 AS |
609 | for (i = 0; i < LPSS_PRV_REG_COUNT; i++) { |
610 | unsigned long offset = i * sizeof(u32); | |
611 | ||
612 | __lpss_reg_write(pdata->prv_reg_ctx[i], pdata, offset); | |
613 | dev_dbg(dev, "restoring 0x%08x to LPSS reg at offset 0x%02lx\n", | |
614 | pdata->prv_reg_ctx[i], offset); | |
615 | } | |
616 | } | |
617 | ||
618 | static void acpi_lpss_d3_to_d0_delay(struct lpss_private_data *pdata) | |
619 | { | |
c78b0830 HK |
620 | /* |
621 | * The following delay is needed or the subsequent write operations may | |
622 | * fail. The LPSS devices are actually PCI devices and the PCI spec | |
623 | * expects 10ms delay before the device can be accessed after D3 to D0 | |
b00855ae | 624 | * transition. However some platforms like BSW does not need this delay. |
c78b0830 | 625 | */ |
b00855ae SK |
626 | unsigned int delay = 10; /* default 10ms delay */ |
627 | ||
628 | if (pdata->dev_desc->flags & LPSS_NO_D3_DELAY) | |
629 | delay = 0; | |
630 | ||
631 | msleep(delay); | |
c78b0830 HK |
632 | } |
633 | ||
c3a49cf3 AS |
634 | static int acpi_lpss_activate(struct device *dev) |
635 | { | |
636 | struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev)); | |
637 | int ret; | |
638 | ||
639 | ret = acpi_dev_runtime_resume(dev); | |
640 | if (ret) | |
641 | return ret; | |
642 | ||
643 | acpi_lpss_d3_to_d0_delay(pdata); | |
644 | ||
645 | /* | |
646 | * This is called only on ->probe() stage where a device is either in | |
647 | * known state defined by BIOS or most likely powered off. Due to this | |
648 | * we have to deassert reset line to be sure that ->probe() will | |
649 | * recognize the device. | |
650 | */ | |
651 | if (pdata->dev_desc->flags & LPSS_SAVE_CTX) | |
652 | lpss_deassert_reset(pdata); | |
653 | ||
654 | return 0; | |
655 | } | |
656 | ||
657 | static void acpi_lpss_dismiss(struct device *dev) | |
658 | { | |
659 | acpi_dev_runtime_suspend(dev); | |
660 | } | |
661 | ||
c78b0830 HK |
662 | #ifdef CONFIG_PM_SLEEP |
663 | static int acpi_lpss_suspend_late(struct device *dev) | |
664 | { | |
cb39dcdd AS |
665 | struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev)); |
666 | int ret; | |
c78b0830 | 667 | |
cb39dcdd | 668 | ret = pm_generic_suspend_late(dev); |
c78b0830 HK |
669 | if (ret) |
670 | return ret; | |
671 | ||
cb39dcdd AS |
672 | if (pdata->dev_desc->flags & LPSS_SAVE_CTX) |
673 | acpi_lpss_save_ctx(dev, pdata); | |
674 | ||
c78b0830 HK |
675 | return acpi_dev_suspend_late(dev); |
676 | } | |
677 | ||
f4168b61 | 678 | static int acpi_lpss_resume_early(struct device *dev) |
c78b0830 | 679 | { |
cb39dcdd AS |
680 | struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev)); |
681 | int ret; | |
c78b0830 | 682 | |
cb39dcdd | 683 | ret = acpi_dev_resume_early(dev); |
c78b0830 HK |
684 | if (ret) |
685 | return ret; | |
686 | ||
02b98540 AS |
687 | acpi_lpss_d3_to_d0_delay(pdata); |
688 | ||
cb39dcdd AS |
689 | if (pdata->dev_desc->flags & LPSS_SAVE_CTX) |
690 | acpi_lpss_restore_ctx(dev, pdata); | |
691 | ||
c78b0830 HK |
692 | return pm_generic_resume_early(dev); |
693 | } | |
694 | #endif /* CONFIG_PM_SLEEP */ | |
695 | ||
eebb3e8d AS |
696 | /* IOSF SB for LPSS island */ |
697 | #define LPSS_IOSF_UNIT_LPIOEP 0xA0 | |
698 | #define LPSS_IOSF_UNIT_LPIO1 0xAB | |
699 | #define LPSS_IOSF_UNIT_LPIO2 0xAC | |
700 | ||
701 | #define LPSS_IOSF_PMCSR 0x84 | |
702 | #define LPSS_PMCSR_D0 0 | |
703 | #define LPSS_PMCSR_D3hot 3 | |
704 | #define LPSS_PMCSR_Dx_MASK GENMASK(1, 0) | |
705 | ||
706 | #define LPSS_IOSF_GPIODEF0 0x154 | |
707 | #define LPSS_GPIODEF0_DMA1_D3 BIT(2) | |
708 | #define LPSS_GPIODEF0_DMA2_D3 BIT(3) | |
709 | #define LPSS_GPIODEF0_DMA_D3_MASK GENMASK(3, 2) | |
710 | ||
711 | static DEFINE_MUTEX(lpss_iosf_mutex); | |
712 | ||
713 | static void lpss_iosf_enter_d3_state(void) | |
714 | { | |
715 | u32 value1 = 0; | |
716 | u32 mask1 = LPSS_GPIODEF0_DMA_D3_MASK; | |
717 | u32 value2 = LPSS_PMCSR_D3hot; | |
718 | u32 mask2 = LPSS_PMCSR_Dx_MASK; | |
719 | /* | |
720 | * PMC provides an information about actual status of the LPSS devices. | |
721 | * Here we read the values related to LPSS power island, i.e. LPSS | |
722 | * devices, excluding both LPSS DMA controllers, along with SCC domain. | |
723 | */ | |
724 | u32 func_dis, d3_sts_0, pmc_status, pmc_mask = 0xfe000ffe; | |
725 | int ret; | |
726 | ||
727 | ret = pmc_atom_read(PMC_FUNC_DIS, &func_dis); | |
728 | if (ret) | |
729 | return; | |
730 | ||
731 | mutex_lock(&lpss_iosf_mutex); | |
732 | ||
733 | ret = pmc_atom_read(PMC_D3_STS_0, &d3_sts_0); | |
734 | if (ret) | |
735 | goto exit; | |
736 | ||
737 | /* | |
738 | * Get the status of entire LPSS power island per device basis. | |
739 | * Shutdown both LPSS DMA controllers if and only if all other devices | |
740 | * are already in D3hot. | |
741 | */ | |
742 | pmc_status = (~(d3_sts_0 | func_dis)) & pmc_mask; | |
743 | if (pmc_status) | |
744 | goto exit; | |
745 | ||
746 | iosf_mbi_modify(LPSS_IOSF_UNIT_LPIO1, MBI_CFG_WRITE, | |
747 | LPSS_IOSF_PMCSR, value2, mask2); | |
748 | ||
749 | iosf_mbi_modify(LPSS_IOSF_UNIT_LPIO2, MBI_CFG_WRITE, | |
750 | LPSS_IOSF_PMCSR, value2, mask2); | |
751 | ||
752 | iosf_mbi_modify(LPSS_IOSF_UNIT_LPIOEP, MBI_CR_WRITE, | |
753 | LPSS_IOSF_GPIODEF0, value1, mask1); | |
754 | exit: | |
755 | mutex_unlock(&lpss_iosf_mutex); | |
756 | } | |
757 | ||
758 | static void lpss_iosf_exit_d3_state(void) | |
759 | { | |
760 | u32 value1 = LPSS_GPIODEF0_DMA1_D3 | LPSS_GPIODEF0_DMA2_D3; | |
761 | u32 mask1 = LPSS_GPIODEF0_DMA_D3_MASK; | |
762 | u32 value2 = LPSS_PMCSR_D0; | |
763 | u32 mask2 = LPSS_PMCSR_Dx_MASK; | |
764 | ||
765 | mutex_lock(&lpss_iosf_mutex); | |
766 | ||
767 | iosf_mbi_modify(LPSS_IOSF_UNIT_LPIOEP, MBI_CR_WRITE, | |
768 | LPSS_IOSF_GPIODEF0, value1, mask1); | |
769 | ||
770 | iosf_mbi_modify(LPSS_IOSF_UNIT_LPIO2, MBI_CFG_WRITE, | |
771 | LPSS_IOSF_PMCSR, value2, mask2); | |
772 | ||
773 | iosf_mbi_modify(LPSS_IOSF_UNIT_LPIO1, MBI_CFG_WRITE, | |
774 | LPSS_IOSF_PMCSR, value2, mask2); | |
775 | ||
776 | mutex_unlock(&lpss_iosf_mutex); | |
777 | } | |
778 | ||
c78b0830 HK |
779 | static int acpi_lpss_runtime_suspend(struct device *dev) |
780 | { | |
cb39dcdd AS |
781 | struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev)); |
782 | int ret; | |
c78b0830 | 783 | |
cb39dcdd | 784 | ret = pm_generic_runtime_suspend(dev); |
c78b0830 HK |
785 | if (ret) |
786 | return ret; | |
787 | ||
cb39dcdd AS |
788 | if (pdata->dev_desc->flags & LPSS_SAVE_CTX) |
789 | acpi_lpss_save_ctx(dev, pdata); | |
790 | ||
eebb3e8d AS |
791 | ret = acpi_dev_runtime_suspend(dev); |
792 | ||
793 | /* | |
794 | * This call must be last in the sequence, otherwise PMC will return | |
795 | * wrong status for devices being about to be powered off. See | |
796 | * lpss_iosf_enter_d3_state() for further information. | |
797 | */ | |
798 | if (lpss_quirks & LPSS_QUIRK_ALWAYS_POWER_ON && iosf_mbi_available()) | |
799 | lpss_iosf_enter_d3_state(); | |
800 | ||
801 | return ret; | |
c78b0830 HK |
802 | } |
803 | ||
804 | static int acpi_lpss_runtime_resume(struct device *dev) | |
805 | { | |
cb39dcdd AS |
806 | struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev)); |
807 | int ret; | |
c78b0830 | 808 | |
eebb3e8d AS |
809 | /* |
810 | * This call is kept first to be in symmetry with | |
811 | * acpi_lpss_runtime_suspend() one. | |
812 | */ | |
813 | if (lpss_quirks & LPSS_QUIRK_ALWAYS_POWER_ON && iosf_mbi_available()) | |
814 | lpss_iosf_exit_d3_state(); | |
815 | ||
cb39dcdd | 816 | ret = acpi_dev_runtime_resume(dev); |
c78b0830 HK |
817 | if (ret) |
818 | return ret; | |
819 | ||
02b98540 AS |
820 | acpi_lpss_d3_to_d0_delay(pdata); |
821 | ||
cb39dcdd AS |
822 | if (pdata->dev_desc->flags & LPSS_SAVE_CTX) |
823 | acpi_lpss_restore_ctx(dev, pdata); | |
824 | ||
c78b0830 HK |
825 | return pm_generic_runtime_resume(dev); |
826 | } | |
c78b0830 HK |
827 | #endif /* CONFIG_PM */ |
828 | ||
829 | static struct dev_pm_domain acpi_lpss_pm_domain = { | |
c3a49cf3 AS |
830 | #ifdef CONFIG_PM |
831 | .activate = acpi_lpss_activate, | |
832 | .dismiss = acpi_lpss_dismiss, | |
833 | #endif | |
c78b0830 | 834 | .ops = { |
5de21bb9 | 835 | #ifdef CONFIG_PM |
c78b0830 | 836 | #ifdef CONFIG_PM_SLEEP |
c78b0830 | 837 | .prepare = acpi_subsys_prepare, |
58a1fbbb | 838 | .complete = pm_complete_with_resume_check, |
c78b0830 | 839 | .suspend = acpi_subsys_suspend, |
f4168b61 FZ |
840 | .suspend_late = acpi_lpss_suspend_late, |
841 | .resume_early = acpi_lpss_resume_early, | |
c78b0830 HK |
842 | .freeze = acpi_subsys_freeze, |
843 | .poweroff = acpi_subsys_suspend, | |
f4168b61 FZ |
844 | .poweroff_late = acpi_lpss_suspend_late, |
845 | .restore_early = acpi_lpss_resume_early, | |
c78b0830 | 846 | #endif |
c78b0830 HK |
847 | .runtime_suspend = acpi_lpss_runtime_suspend, |
848 | .runtime_resume = acpi_lpss_runtime_resume, | |
849 | #endif | |
850 | }, | |
851 | }; | |
852 | ||
2e0f8822 RW |
853 | static int acpi_lpss_platform_notify(struct notifier_block *nb, |
854 | unsigned long action, void *data) | |
855 | { | |
856 | struct platform_device *pdev = to_platform_device(data); | |
857 | struct lpss_private_data *pdata; | |
858 | struct acpi_device *adev; | |
859 | const struct acpi_device_id *id; | |
2e0f8822 RW |
860 | |
861 | id = acpi_match_device(acpi_lpss_device_ids, &pdev->dev); | |
862 | if (!id || !id->driver_data) | |
863 | return 0; | |
864 | ||
865 | if (acpi_bus_get_device(ACPI_HANDLE(&pdev->dev), &adev)) | |
866 | return 0; | |
867 | ||
868 | pdata = acpi_driver_data(adev); | |
cb39dcdd | 869 | if (!pdata) |
2e0f8822 RW |
870 | return 0; |
871 | ||
cb39dcdd AS |
872 | if (pdata->mmio_base && |
873 | pdata->mmio_size < pdata->dev_desc->prv_offset + LPSS_LTR_SIZE) { | |
2e0f8822 RW |
874 | dev_err(&pdev->dev, "MMIO size insufficient to access LTR\n"); |
875 | return 0; | |
876 | } | |
877 | ||
c78b0830 | 878 | switch (action) { |
de16d552 | 879 | case BUS_NOTIFY_BIND_DRIVER: |
989561de | 880 | dev_pm_domain_set(&pdev->dev, &acpi_lpss_pm_domain); |
b5f88dd1 | 881 | break; |
de16d552 | 882 | case BUS_NOTIFY_DRIVER_NOT_BOUND: |
b5f88dd1 | 883 | case BUS_NOTIFY_UNBOUND_DRIVER: |
5be6ada3 | 884 | dev_pm_domain_set(&pdev->dev, NULL); |
b5f88dd1 AS |
885 | break; |
886 | case BUS_NOTIFY_ADD_DEVICE: | |
989561de | 887 | dev_pm_domain_set(&pdev->dev, &acpi_lpss_pm_domain); |
ff8c1af5 | 888 | if (pdata->dev_desc->flags & LPSS_LTR) |
c78b0830 HK |
889 | return sysfs_create_group(&pdev->dev.kobj, |
890 | &lpss_attr_group); | |
01ac170b | 891 | break; |
c78b0830 | 892 | case BUS_NOTIFY_DEL_DEVICE: |
ff8c1af5 | 893 | if (pdata->dev_desc->flags & LPSS_LTR) |
c78b0830 | 894 | sysfs_remove_group(&pdev->dev.kobj, &lpss_attr_group); |
989561de | 895 | dev_pm_domain_set(&pdev->dev, NULL); |
01ac170b | 896 | break; |
c78b0830 HK |
897 | default: |
898 | break; | |
899 | } | |
2e0f8822 | 900 | |
c78b0830 | 901 | return 0; |
2e0f8822 RW |
902 | } |
903 | ||
904 | static struct notifier_block acpi_lpss_nb = { | |
905 | .notifier_call = acpi_lpss_platform_notify, | |
906 | }; | |
907 | ||
1a8f8351 RW |
908 | static void acpi_lpss_bind(struct device *dev) |
909 | { | |
910 | struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev)); | |
911 | ||
ff8c1af5 | 912 | if (!pdata || !pdata->mmio_base || !(pdata->dev_desc->flags & LPSS_LTR)) |
1a8f8351 RW |
913 | return; |
914 | ||
915 | if (pdata->mmio_size >= pdata->dev_desc->prv_offset + LPSS_LTR_SIZE) | |
916 | dev->power.set_latency_tolerance = acpi_lpss_set_ltr; | |
917 | else | |
918 | dev_err(dev, "MMIO size insufficient to access LTR\n"); | |
919 | } | |
920 | ||
921 | static void acpi_lpss_unbind(struct device *dev) | |
922 | { | |
923 | dev->power.set_latency_tolerance = NULL; | |
924 | } | |
925 | ||
f58b082a RW |
926 | static struct acpi_scan_handler lpss_handler = { |
927 | .ids = acpi_lpss_device_ids, | |
928 | .attach = acpi_lpss_create_device, | |
1a8f8351 RW |
929 | .bind = acpi_lpss_bind, |
930 | .unbind = acpi_lpss_unbind, | |
f58b082a RW |
931 | }; |
932 | ||
933 | void __init acpi_lpss_init(void) | |
934 | { | |
eebb3e8d AS |
935 | const struct x86_cpu_id *id; |
936 | int ret; | |
937 | ||
938 | ret = lpt_clk_init(); | |
939 | if (ret) | |
940 | return; | |
941 | ||
942 | id = x86_match_cpu(lpss_cpu_ids); | |
943 | if (id) | |
944 | lpss_quirks |= LPSS_QUIRK_ALWAYS_POWER_ON; | |
945 | ||
946 | bus_register_notifier(&platform_bus_type, &acpi_lpss_nb); | |
947 | acpi_scan_add_handler(&lpss_handler); | |
f58b082a | 948 | } |
d6ddaaac RW |
949 | |
950 | #else | |
951 | ||
952 | static struct acpi_scan_handler lpss_handler = { | |
953 | .ids = acpi_lpss_device_ids, | |
954 | }; | |
955 | ||
956 | void __init acpi_lpss_init(void) | |
957 | { | |
958 | acpi_scan_add_handler(&lpss_handler); | |
959 | } | |
960 | ||
961 | #endif /* CONFIG_X86_INTEL_LPSS */ |