Commit | Line | Data |
---|---|---|
f58b082a RW |
1 | /* |
2 | * ACPI support for Intel Lynxpoint LPSS. | |
3 | * | |
3df2da96 | 4 | * Copyright (C) 2013, Intel Corporation |
f58b082a RW |
5 | * Authors: Mika Westerberg <mika.westerberg@linux.intel.com> |
6 | * Rafael J. Wysocki <rafael.j.wysocki@intel.com> | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License version 2 as | |
10 | * published by the Free Software Foundation. | |
11 | */ | |
12 | ||
13 | #include <linux/acpi.h> | |
f58b082a RW |
14 | #include <linux/clkdev.h> |
15 | #include <linux/clk-provider.h> | |
16 | #include <linux/err.h> | |
17 | #include <linux/io.h> | |
eebb3e8d | 18 | #include <linux/mutex.h> |
f58b082a RW |
19 | #include <linux/platform_device.h> |
20 | #include <linux/platform_data/clk-lpss.h> | |
989561de | 21 | #include <linux/pm_domain.h> |
2e0f8822 | 22 | #include <linux/pm_runtime.h> |
c78b0830 | 23 | #include <linux/delay.h> |
f58b082a RW |
24 | |
25 | #include "internal.h" | |
26 | ||
27 | ACPI_MODULE_NAME("acpi_lpss"); | |
28 | ||
d6ddaaac RW |
29 | #ifdef CONFIG_X86_INTEL_LPSS |
30 | ||
eebb3e8d AS |
31 | #include <asm/cpu_device_id.h> |
32 | #include <asm/iosf_mbi.h> | |
33 | #include <asm/pmc_atom.h> | |
34 | ||
d6ddaaac RW |
35 | #define LPSS_ADDR(desc) ((unsigned long)&desc) |
36 | ||
f58b082a | 37 | #define LPSS_CLK_SIZE 0x04 |
2e0f8822 RW |
38 | #define LPSS_LTR_SIZE 0x18 |
39 | ||
40 | /* Offsets relative to LPSS_PRIVATE_OFFSET */ | |
ed3a872e | 41 | #define LPSS_CLK_DIVIDER_DEF_MASK (BIT(1) | BIT(16)) |
765bdd4e MW |
42 | #define LPSS_RESETS 0x04 |
43 | #define LPSS_RESETS_RESET_FUNC BIT(0) | |
44 | #define LPSS_RESETS_RESET_APB BIT(1) | |
2e0f8822 RW |
45 | #define LPSS_GENERAL 0x08 |
46 | #define LPSS_GENERAL_LTR_MODE_SW BIT(2) | |
088f1fd2 | 47 | #define LPSS_GENERAL_UART_RTS_OVRD BIT(3) |
2e0f8822 RW |
48 | #define LPSS_SW_LTR 0x10 |
49 | #define LPSS_AUTO_LTR 0x14 | |
1a8f8351 RW |
50 | #define LPSS_LTR_SNOOP_REQ BIT(15) |
51 | #define LPSS_LTR_SNOOP_MASK 0x0000FFFF | |
52 | #define LPSS_LTR_SNOOP_LAT_1US 0x800 | |
53 | #define LPSS_LTR_SNOOP_LAT_32US 0xC00 | |
54 | #define LPSS_LTR_SNOOP_LAT_SHIFT 5 | |
55 | #define LPSS_LTR_SNOOP_LAT_CUTOFF 3000 | |
56 | #define LPSS_LTR_MAX_VAL 0x3FF | |
06d86415 HK |
57 | #define LPSS_TX_INT 0x20 |
58 | #define LPSS_TX_INT_MASK BIT(1) | |
f58b082a | 59 | |
c78b0830 HK |
60 | #define LPSS_PRV_REG_COUNT 9 |
61 | ||
ff8c1af5 HK |
62 | /* LPSS Flags */ |
63 | #define LPSS_CLK BIT(0) | |
64 | #define LPSS_CLK_GATE BIT(1) | |
65 | #define LPSS_CLK_DIVIDER BIT(2) | |
66 | #define LPSS_LTR BIT(3) | |
67 | #define LPSS_SAVE_CTX BIT(4) | |
b00855ae | 68 | #define LPSS_NO_D3_DELAY BIT(5) |
f6272170 | 69 | |
06d86415 | 70 | struct lpss_private_data; |
f58b082a RW |
71 | |
72 | struct lpss_device_desc { | |
ff8c1af5 | 73 | unsigned int flags; |
fcf0789a | 74 | const char *clk_con_id; |
2e0f8822 | 75 | unsigned int prv_offset; |
958c4eb2 | 76 | size_t prv_size_override; |
06d86415 | 77 | void (*setup)(struct lpss_private_data *pdata); |
f58b082a RW |
78 | }; |
79 | ||
eebb3e8d | 80 | static const struct lpss_device_desc lpss_dma_desc = { |
3df2da96 | 81 | .flags = LPSS_CLK, |
b59cc200 RW |
82 | }; |
83 | ||
f58b082a RW |
84 | struct lpss_private_data { |
85 | void __iomem *mmio_base; | |
86 | resource_size_t mmio_size; | |
03f09f73 | 87 | unsigned int fixed_clk_rate; |
f58b082a RW |
88 | struct clk *clk; |
89 | const struct lpss_device_desc *dev_desc; | |
c78b0830 | 90 | u32 prv_reg_ctx[LPSS_PRV_REG_COUNT]; |
f58b082a RW |
91 | }; |
92 | ||
eebb3e8d AS |
93 | /* LPSS run time quirks */ |
94 | static unsigned int lpss_quirks; | |
95 | ||
96 | /* | |
97 | * LPSS_QUIRK_ALWAYS_POWER_ON: override power state for LPSS DMA device. | |
98 | * | |
fa9e93b1 | 99 | * The LPSS DMA controller has neither _PS0 nor _PS3 method. Moreover |
eebb3e8d AS |
100 | * it can be powered off automatically whenever the last LPSS device goes down. |
101 | * In case of no power any access to the DMA controller will hang the system. | |
102 | * The behaviour is reproduced on some HP laptops based on Intel BayTrail as | |
103 | * well as on ASuS T100TA transformer. | |
104 | * | |
105 | * This quirk overrides power state of entire LPSS island to keep DMA powered | |
106 | * on whenever we have at least one other device in use. | |
107 | */ | |
108 | #define LPSS_QUIRK_ALWAYS_POWER_ON BIT(0) | |
109 | ||
1f47a77c HK |
110 | /* UART Component Parameter Register */ |
111 | #define LPSS_UART_CPR 0xF4 | |
112 | #define LPSS_UART_CPR_AFCE BIT(4) | |
113 | ||
06d86415 HK |
114 | static void lpss_uart_setup(struct lpss_private_data *pdata) |
115 | { | |
088f1fd2 | 116 | unsigned int offset; |
1f47a77c | 117 | u32 val; |
06d86415 | 118 | |
088f1fd2 | 119 | offset = pdata->dev_desc->prv_offset + LPSS_TX_INT; |
1f47a77c HK |
120 | val = readl(pdata->mmio_base + offset); |
121 | writel(val | LPSS_TX_INT_MASK, pdata->mmio_base + offset); | |
122 | ||
123 | val = readl(pdata->mmio_base + LPSS_UART_CPR); | |
124 | if (!(val & LPSS_UART_CPR_AFCE)) { | |
125 | offset = pdata->dev_desc->prv_offset + LPSS_GENERAL; | |
126 | val = readl(pdata->mmio_base + offset); | |
127 | val |= LPSS_GENERAL_UART_RTS_OVRD; | |
128 | writel(val, pdata->mmio_base + offset); | |
129 | } | |
06d86415 HK |
130 | } |
131 | ||
3095794a | 132 | static void lpss_deassert_reset(struct lpss_private_data *pdata) |
765bdd4e MW |
133 | { |
134 | unsigned int offset; | |
135 | u32 val; | |
136 | ||
137 | offset = pdata->dev_desc->prv_offset + LPSS_RESETS; | |
138 | val = readl(pdata->mmio_base + offset); | |
139 | val |= LPSS_RESETS_RESET_APB | LPSS_RESETS_RESET_FUNC; | |
140 | writel(val, pdata->mmio_base + offset); | |
3095794a MW |
141 | } |
142 | ||
143 | #define LPSS_I2C_ENABLE 0x6c | |
144 | ||
145 | static void byt_i2c_setup(struct lpss_private_data *pdata) | |
146 | { | |
147 | lpss_deassert_reset(pdata); | |
765bdd4e | 148 | |
03f09f73 HK |
149 | if (readl(pdata->mmio_base + pdata->dev_desc->prv_offset)) |
150 | pdata->fixed_clk_rate = 133000000; | |
3293c7b8 MW |
151 | |
152 | writel(0, pdata->mmio_base + LPSS_I2C_ENABLE); | |
765bdd4e | 153 | } |
43218a1b | 154 | |
b2687cd7 | 155 | static const struct lpss_device_desc lpt_dev_desc = { |
ff8c1af5 | 156 | .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_LTR, |
ed3a872e | 157 | .prv_offset = 0x800, |
ed3a872e HK |
158 | }; |
159 | ||
b2687cd7 | 160 | static const struct lpss_device_desc lpt_i2c_dev_desc = { |
ff8c1af5 | 161 | .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_LTR, |
2e0f8822 | 162 | .prv_offset = 0x800, |
2e0f8822 RW |
163 | }; |
164 | ||
b2687cd7 | 165 | static const struct lpss_device_desc lpt_uart_dev_desc = { |
ff8c1af5 | 166 | .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_LTR, |
fcf0789a | 167 | .clk_con_id = "baudclk", |
06d86415 | 168 | .prv_offset = 0x800, |
06d86415 | 169 | .setup = lpss_uart_setup, |
2e0f8822 RW |
170 | }; |
171 | ||
b2687cd7 | 172 | static const struct lpss_device_desc lpt_sdio_dev_desc = { |
ff8c1af5 | 173 | .flags = LPSS_LTR, |
2e0f8822 | 174 | .prv_offset = 0x1000, |
958c4eb2 | 175 | .prv_size_override = 0x1018, |
e1c74817 CCE |
176 | }; |
177 | ||
b2687cd7 | 178 | static const struct lpss_device_desc byt_pwm_dev_desc = { |
3f56bf3e | 179 | .flags = LPSS_SAVE_CTX, |
e1c74817 CCE |
180 | }; |
181 | ||
b00855ae SK |
182 | static const struct lpss_device_desc bsw_pwm_dev_desc = { |
183 | .flags = LPSS_SAVE_CTX | LPSS_NO_D3_DELAY, | |
184 | }; | |
185 | ||
b2687cd7 | 186 | static const struct lpss_device_desc byt_uart_dev_desc = { |
3df2da96 | 187 | .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_SAVE_CTX, |
fcf0789a | 188 | .clk_con_id = "baudclk", |
f6272170 | 189 | .prv_offset = 0x800, |
06d86415 | 190 | .setup = lpss_uart_setup, |
f6272170 MW |
191 | }; |
192 | ||
b00855ae SK |
193 | static const struct lpss_device_desc bsw_uart_dev_desc = { |
194 | .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_SAVE_CTX | |
195 | | LPSS_NO_D3_DELAY, | |
196 | .clk_con_id = "baudclk", | |
197 | .prv_offset = 0x800, | |
198 | .setup = lpss_uart_setup, | |
199 | }; | |
200 | ||
b2687cd7 | 201 | static const struct lpss_device_desc byt_spi_dev_desc = { |
3df2da96 | 202 | .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_SAVE_CTX, |
f6272170 | 203 | .prv_offset = 0x400, |
f6272170 MW |
204 | }; |
205 | ||
b2687cd7 | 206 | static const struct lpss_device_desc byt_sdio_dev_desc = { |
3df2da96 | 207 | .flags = LPSS_CLK, |
f6272170 MW |
208 | }; |
209 | ||
b2687cd7 | 210 | static const struct lpss_device_desc byt_i2c_dev_desc = { |
3df2da96 | 211 | .flags = LPSS_CLK | LPSS_SAVE_CTX, |
f6272170 | 212 | .prv_offset = 0x800, |
03f09f73 | 213 | .setup = byt_i2c_setup, |
1bfbd8eb AC |
214 | }; |
215 | ||
b00855ae SK |
216 | static const struct lpss_device_desc bsw_i2c_dev_desc = { |
217 | .flags = LPSS_CLK | LPSS_SAVE_CTX | LPSS_NO_D3_DELAY, | |
218 | .prv_offset = 0x800, | |
219 | .setup = byt_i2c_setup, | |
220 | }; | |
221 | ||
eebb3e8d | 222 | static const struct lpss_device_desc bsw_spi_dev_desc = { |
b00855ae SK |
223 | .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_SAVE_CTX |
224 | | LPSS_NO_D3_DELAY, | |
3095794a MW |
225 | .prv_offset = 0x400, |
226 | .setup = lpss_deassert_reset, | |
227 | }; | |
228 | ||
eebb3e8d AS |
229 | #define ICPU(model) { X86_VENDOR_INTEL, 6, model, X86_FEATURE_ANY, } |
230 | ||
231 | static const struct x86_cpu_id lpss_cpu_ids[] = { | |
232 | ICPU(0x37), /* Valleyview, Bay Trail */ | |
233 | ICPU(0x4c), /* Braswell, Cherry Trail */ | |
234 | {} | |
235 | }; | |
236 | ||
d6ddaaac RW |
237 | #else |
238 | ||
239 | #define LPSS_ADDR(desc) (0UL) | |
240 | ||
241 | #endif /* CONFIG_X86_INTEL_LPSS */ | |
242 | ||
f58b082a | 243 | static const struct acpi_device_id acpi_lpss_device_ids[] = { |
b59cc200 | 244 | /* Generic LPSS devices */ |
d6ddaaac | 245 | { "INTL9C60", LPSS_ADDR(lpss_dma_desc) }, |
b59cc200 | 246 | |
f58b082a | 247 | /* Lynxpoint LPSS devices */ |
d6ddaaac RW |
248 | { "INT33C0", LPSS_ADDR(lpt_dev_desc) }, |
249 | { "INT33C1", LPSS_ADDR(lpt_dev_desc) }, | |
250 | { "INT33C2", LPSS_ADDR(lpt_i2c_dev_desc) }, | |
251 | { "INT33C3", LPSS_ADDR(lpt_i2c_dev_desc) }, | |
252 | { "INT33C4", LPSS_ADDR(lpt_uart_dev_desc) }, | |
253 | { "INT33C5", LPSS_ADDR(lpt_uart_dev_desc) }, | |
254 | { "INT33C6", LPSS_ADDR(lpt_sdio_dev_desc) }, | |
f58b082a RW |
255 | { "INT33C7", }, |
256 | ||
f6272170 | 257 | /* BayTrail LPSS devices */ |
d6ddaaac RW |
258 | { "80860F09", LPSS_ADDR(byt_pwm_dev_desc) }, |
259 | { "80860F0A", LPSS_ADDR(byt_uart_dev_desc) }, | |
260 | { "80860F0E", LPSS_ADDR(byt_spi_dev_desc) }, | |
261 | { "80860F14", LPSS_ADDR(byt_sdio_dev_desc) }, | |
262 | { "80860F41", LPSS_ADDR(byt_i2c_dev_desc) }, | |
f6272170 | 263 | { "INT33B2", }, |
20482d32 | 264 | { "INT33FC", }, |
f6272170 | 265 | |
1bfbd8eb | 266 | /* Braswell LPSS devices */ |
b00855ae SK |
267 | { "80862288", LPSS_ADDR(bsw_pwm_dev_desc) }, |
268 | { "8086228A", LPSS_ADDR(bsw_uart_dev_desc) }, | |
3095794a | 269 | { "8086228E", LPSS_ADDR(bsw_spi_dev_desc) }, |
b00855ae | 270 | { "808622C1", LPSS_ADDR(bsw_i2c_dev_desc) }, |
1bfbd8eb | 271 | |
b00855ae | 272 | /* Broadwell LPSS devices */ |
d6ddaaac RW |
273 | { "INT3430", LPSS_ADDR(lpt_dev_desc) }, |
274 | { "INT3431", LPSS_ADDR(lpt_dev_desc) }, | |
275 | { "INT3432", LPSS_ADDR(lpt_i2c_dev_desc) }, | |
276 | { "INT3433", LPSS_ADDR(lpt_i2c_dev_desc) }, | |
277 | { "INT3434", LPSS_ADDR(lpt_uart_dev_desc) }, | |
278 | { "INT3435", LPSS_ADDR(lpt_uart_dev_desc) }, | |
279 | { "INT3436", LPSS_ADDR(lpt_sdio_dev_desc) }, | |
a4d97536 MW |
280 | { "INT3437", }, |
281 | ||
ff8c1af5 HK |
282 | /* Wildcat Point LPSS devices */ |
283 | { "INT3438", LPSS_ADDR(lpt_dev_desc) }, | |
43218a1b | 284 | |
f58b082a RW |
285 | { } |
286 | }; | |
287 | ||
d6ddaaac RW |
288 | #ifdef CONFIG_X86_INTEL_LPSS |
289 | ||
f58b082a RW |
290 | static int is_memory(struct acpi_resource *res, void *not_used) |
291 | { | |
292 | struct resource r; | |
293 | return !acpi_dev_resource_memory(res, &r); | |
294 | } | |
295 | ||
296 | /* LPSS main clock device. */ | |
297 | static struct platform_device *lpss_clk_dev; | |
298 | ||
299 | static inline void lpt_register_clock_device(void) | |
300 | { | |
301 | lpss_clk_dev = platform_device_register_simple("clk-lpt", -1, NULL, 0); | |
302 | } | |
303 | ||
304 | static int register_device_clock(struct acpi_device *adev, | |
305 | struct lpss_private_data *pdata) | |
306 | { | |
307 | const struct lpss_device_desc *dev_desc = pdata->dev_desc; | |
ed3a872e | 308 | const char *devname = dev_name(&adev->dev); |
f6272170 | 309 | struct clk *clk = ERR_PTR(-ENODEV); |
b59cc200 | 310 | struct lpss_clk_data *clk_data; |
ed3a872e HK |
311 | const char *parent, *clk_name; |
312 | void __iomem *prv_base; | |
f58b082a RW |
313 | |
314 | if (!lpss_clk_dev) | |
315 | lpt_register_clock_device(); | |
316 | ||
b59cc200 RW |
317 | clk_data = platform_get_drvdata(lpss_clk_dev); |
318 | if (!clk_data) | |
319 | return -ENODEV; | |
b0d00f8b | 320 | clk = clk_data->clk; |
b59cc200 RW |
321 | |
322 | if (!pdata->mmio_base | |
2e0f8822 | 323 | || pdata->mmio_size < dev_desc->prv_offset + LPSS_CLK_SIZE) |
f58b082a RW |
324 | return -ENODATA; |
325 | ||
f6272170 | 326 | parent = clk_data->name; |
ed3a872e | 327 | prv_base = pdata->mmio_base + dev_desc->prv_offset; |
f6272170 | 328 | |
03f09f73 HK |
329 | if (pdata->fixed_clk_rate) { |
330 | clk = clk_register_fixed_rate(NULL, devname, parent, 0, | |
331 | pdata->fixed_clk_rate); | |
332 | goto out; | |
f6272170 MW |
333 | } |
334 | ||
ff8c1af5 | 335 | if (dev_desc->flags & LPSS_CLK_GATE) { |
ed3a872e HK |
336 | clk = clk_register_gate(NULL, devname, parent, 0, |
337 | prv_base, 0, 0, NULL); | |
338 | parent = devname; | |
339 | } | |
340 | ||
ff8c1af5 | 341 | if (dev_desc->flags & LPSS_CLK_DIVIDER) { |
ed3a872e HK |
342 | /* Prevent division by zero */ |
343 | if (!readl(prv_base)) | |
344 | writel(LPSS_CLK_DIVIDER_DEF_MASK, prv_base); | |
345 | ||
346 | clk_name = kasprintf(GFP_KERNEL, "%s-div", devname); | |
347 | if (!clk_name) | |
348 | return -ENOMEM; | |
349 | clk = clk_register_fractional_divider(NULL, clk_name, parent, | |
350 | 0, prv_base, | |
351 | 1, 15, 16, 15, 0, NULL); | |
352 | parent = clk_name; | |
353 | ||
354 | clk_name = kasprintf(GFP_KERNEL, "%s-update", devname); | |
355 | if (!clk_name) { | |
356 | kfree(parent); | |
357 | return -ENOMEM; | |
358 | } | |
359 | clk = clk_register_gate(NULL, clk_name, parent, | |
360 | CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE, | |
361 | prv_base, 31, 0, NULL); | |
362 | kfree(parent); | |
363 | kfree(clk_name); | |
f6272170 | 364 | } |
03f09f73 | 365 | out: |
f6272170 MW |
366 | if (IS_ERR(clk)) |
367 | return PTR_ERR(clk); | |
f58b082a | 368 | |
ed3a872e | 369 | pdata->clk = clk; |
fcf0789a | 370 | clk_register_clkdev(clk, dev_desc->clk_con_id, devname); |
f58b082a RW |
371 | return 0; |
372 | } | |
373 | ||
374 | static int acpi_lpss_create_device(struct acpi_device *adev, | |
375 | const struct acpi_device_id *id) | |
376 | { | |
b2687cd7 | 377 | const struct lpss_device_desc *dev_desc; |
f58b082a | 378 | struct lpss_private_data *pdata; |
90e97820 | 379 | struct resource_entry *rentry; |
f58b082a | 380 | struct list_head resource_list; |
8ce62f85 | 381 | struct platform_device *pdev; |
f58b082a RW |
382 | int ret; |
383 | ||
b2687cd7 | 384 | dev_desc = (const struct lpss_device_desc *)id->driver_data; |
8ce62f85 RW |
385 | if (!dev_desc) { |
386 | pdev = acpi_create_platform_device(adev); | |
387 | return IS_ERR_OR_NULL(pdev) ? PTR_ERR(pdev) : 1; | |
388 | } | |
f58b082a RW |
389 | pdata = kzalloc(sizeof(*pdata), GFP_KERNEL); |
390 | if (!pdata) | |
391 | return -ENOMEM; | |
392 | ||
393 | INIT_LIST_HEAD(&resource_list); | |
394 | ret = acpi_dev_get_resources(adev, &resource_list, is_memory, NULL); | |
395 | if (ret < 0) | |
396 | goto err_out; | |
397 | ||
398 | list_for_each_entry(rentry, &resource_list, node) | |
90e97820 | 399 | if (resource_type(rentry->res) == IORESOURCE_MEM) { |
958c4eb2 MW |
400 | if (dev_desc->prv_size_override) |
401 | pdata->mmio_size = dev_desc->prv_size_override; | |
402 | else | |
90e97820 JL |
403 | pdata->mmio_size = resource_size(rentry->res); |
404 | pdata->mmio_base = ioremap(rentry->res->start, | |
f58b082a | 405 | pdata->mmio_size); |
f58b082a RW |
406 | break; |
407 | } | |
408 | ||
409 | acpi_dev_free_resource_list(&resource_list); | |
410 | ||
d3e13ff3 RW |
411 | if (!pdata->mmio_base) { |
412 | ret = -ENOMEM; | |
413 | goto err_out; | |
414 | } | |
415 | ||
af65cfe9 MW |
416 | pdata->dev_desc = dev_desc; |
417 | ||
03f09f73 HK |
418 | if (dev_desc->setup) |
419 | dev_desc->setup(pdata); | |
420 | ||
ff8c1af5 | 421 | if (dev_desc->flags & LPSS_CLK) { |
f58b082a RW |
422 | ret = register_device_clock(adev, pdata); |
423 | if (ret) { | |
b9e95fc6 RW |
424 | /* Skip the device, but continue the namespace scan. */ |
425 | ret = 0; | |
426 | goto err_out; | |
f58b082a RW |
427 | } |
428 | } | |
429 | ||
b9e95fc6 RW |
430 | /* |
431 | * This works around a known issue in ACPI tables where LPSS devices | |
432 | * have _PS0 and _PS3 without _PSC (and no power resources), so | |
433 | * acpi_bus_init_power() will assume that the BIOS has put them into D0. | |
434 | */ | |
435 | ret = acpi_device_fix_up_power(adev); | |
436 | if (ret) { | |
437 | /* Skip the device, but continue the namespace scan. */ | |
438 | ret = 0; | |
439 | goto err_out; | |
440 | } | |
441 | ||
f58b082a | 442 | adev->driver_data = pdata; |
8ce62f85 RW |
443 | pdev = acpi_create_platform_device(adev); |
444 | if (!IS_ERR_OR_NULL(pdev)) { | |
8ce62f85 RW |
445 | return 1; |
446 | } | |
f58b082a | 447 | |
8ce62f85 | 448 | ret = PTR_ERR(pdev); |
f58b082a RW |
449 | adev->driver_data = NULL; |
450 | ||
451 | err_out: | |
452 | kfree(pdata); | |
453 | return ret; | |
454 | } | |
455 | ||
1a8f8351 RW |
456 | static u32 __lpss_reg_read(struct lpss_private_data *pdata, unsigned int reg) |
457 | { | |
458 | return readl(pdata->mmio_base + pdata->dev_desc->prv_offset + reg); | |
459 | } | |
460 | ||
461 | static void __lpss_reg_write(u32 val, struct lpss_private_data *pdata, | |
462 | unsigned int reg) | |
463 | { | |
464 | writel(val, pdata->mmio_base + pdata->dev_desc->prv_offset + reg); | |
465 | } | |
466 | ||
2e0f8822 RW |
467 | static int lpss_reg_read(struct device *dev, unsigned int reg, u32 *val) |
468 | { | |
469 | struct acpi_device *adev; | |
470 | struct lpss_private_data *pdata; | |
471 | unsigned long flags; | |
472 | int ret; | |
473 | ||
474 | ret = acpi_bus_get_device(ACPI_HANDLE(dev), &adev); | |
475 | if (WARN_ON(ret)) | |
476 | return ret; | |
477 | ||
478 | spin_lock_irqsave(&dev->power.lock, flags); | |
479 | if (pm_runtime_suspended(dev)) { | |
480 | ret = -EAGAIN; | |
481 | goto out; | |
482 | } | |
483 | pdata = acpi_driver_data(adev); | |
484 | if (WARN_ON(!pdata || !pdata->mmio_base)) { | |
485 | ret = -ENODEV; | |
486 | goto out; | |
487 | } | |
1a8f8351 | 488 | *val = __lpss_reg_read(pdata, reg); |
2e0f8822 RW |
489 | |
490 | out: | |
491 | spin_unlock_irqrestore(&dev->power.lock, flags); | |
492 | return ret; | |
493 | } | |
494 | ||
495 | static ssize_t lpss_ltr_show(struct device *dev, struct device_attribute *attr, | |
496 | char *buf) | |
497 | { | |
498 | u32 ltr_value = 0; | |
499 | unsigned int reg; | |
500 | int ret; | |
501 | ||
502 | reg = strcmp(attr->attr.name, "auto_ltr") ? LPSS_SW_LTR : LPSS_AUTO_LTR; | |
503 | ret = lpss_reg_read(dev, reg, <r_value); | |
504 | if (ret) | |
505 | return ret; | |
506 | ||
507 | return snprintf(buf, PAGE_SIZE, "%08x\n", ltr_value); | |
508 | } | |
509 | ||
510 | static ssize_t lpss_ltr_mode_show(struct device *dev, | |
511 | struct device_attribute *attr, char *buf) | |
512 | { | |
513 | u32 ltr_mode = 0; | |
514 | char *outstr; | |
515 | int ret; | |
516 | ||
517 | ret = lpss_reg_read(dev, LPSS_GENERAL, <r_mode); | |
518 | if (ret) | |
519 | return ret; | |
520 | ||
521 | outstr = (ltr_mode & LPSS_GENERAL_LTR_MODE_SW) ? "sw" : "auto"; | |
522 | return sprintf(buf, "%s\n", outstr); | |
523 | } | |
524 | ||
525 | static DEVICE_ATTR(auto_ltr, S_IRUSR, lpss_ltr_show, NULL); | |
526 | static DEVICE_ATTR(sw_ltr, S_IRUSR, lpss_ltr_show, NULL); | |
527 | static DEVICE_ATTR(ltr_mode, S_IRUSR, lpss_ltr_mode_show, NULL); | |
528 | ||
529 | static struct attribute *lpss_attrs[] = { | |
530 | &dev_attr_auto_ltr.attr, | |
531 | &dev_attr_sw_ltr.attr, | |
532 | &dev_attr_ltr_mode.attr, | |
533 | NULL, | |
534 | }; | |
535 | ||
536 | static struct attribute_group lpss_attr_group = { | |
537 | .attrs = lpss_attrs, | |
538 | .name = "lpss_ltr", | |
539 | }; | |
540 | ||
1a8f8351 RW |
541 | static void acpi_lpss_set_ltr(struct device *dev, s32 val) |
542 | { | |
543 | struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev)); | |
544 | u32 ltr_mode, ltr_val; | |
545 | ||
546 | ltr_mode = __lpss_reg_read(pdata, LPSS_GENERAL); | |
547 | if (val < 0) { | |
548 | if (ltr_mode & LPSS_GENERAL_LTR_MODE_SW) { | |
549 | ltr_mode &= ~LPSS_GENERAL_LTR_MODE_SW; | |
550 | __lpss_reg_write(ltr_mode, pdata, LPSS_GENERAL); | |
551 | } | |
552 | return; | |
553 | } | |
554 | ltr_val = __lpss_reg_read(pdata, LPSS_SW_LTR) & ~LPSS_LTR_SNOOP_MASK; | |
555 | if (val >= LPSS_LTR_SNOOP_LAT_CUTOFF) { | |
556 | ltr_val |= LPSS_LTR_SNOOP_LAT_32US; | |
557 | val = LPSS_LTR_MAX_VAL; | |
558 | } else if (val > LPSS_LTR_MAX_VAL) { | |
559 | ltr_val |= LPSS_LTR_SNOOP_LAT_32US | LPSS_LTR_SNOOP_REQ; | |
560 | val >>= LPSS_LTR_SNOOP_LAT_SHIFT; | |
561 | } else { | |
562 | ltr_val |= LPSS_LTR_SNOOP_LAT_1US | LPSS_LTR_SNOOP_REQ; | |
563 | } | |
564 | ltr_val |= val; | |
565 | __lpss_reg_write(ltr_val, pdata, LPSS_SW_LTR); | |
566 | if (!(ltr_mode & LPSS_GENERAL_LTR_MODE_SW)) { | |
567 | ltr_mode |= LPSS_GENERAL_LTR_MODE_SW; | |
568 | __lpss_reg_write(ltr_mode, pdata, LPSS_GENERAL); | |
569 | } | |
570 | } | |
571 | ||
c78b0830 HK |
572 | #ifdef CONFIG_PM |
573 | /** | |
574 | * acpi_lpss_save_ctx() - Save the private registers of LPSS device | |
575 | * @dev: LPSS device | |
cb39dcdd | 576 | * @pdata: pointer to the private data of the LPSS device |
c78b0830 HK |
577 | * |
578 | * Most LPSS devices have private registers which may loose their context when | |
579 | * the device is powered down. acpi_lpss_save_ctx() saves those registers into | |
580 | * prv_reg_ctx array. | |
581 | */ | |
cb39dcdd AS |
582 | static void acpi_lpss_save_ctx(struct device *dev, |
583 | struct lpss_private_data *pdata) | |
c78b0830 | 584 | { |
c78b0830 HK |
585 | unsigned int i; |
586 | ||
587 | for (i = 0; i < LPSS_PRV_REG_COUNT; i++) { | |
588 | unsigned long offset = i * sizeof(u32); | |
589 | ||
590 | pdata->prv_reg_ctx[i] = __lpss_reg_read(pdata, offset); | |
591 | dev_dbg(dev, "saving 0x%08x from LPSS reg at offset 0x%02lx\n", | |
592 | pdata->prv_reg_ctx[i], offset); | |
593 | } | |
594 | } | |
595 | ||
596 | /** | |
597 | * acpi_lpss_restore_ctx() - Restore the private registers of LPSS device | |
598 | * @dev: LPSS device | |
cb39dcdd | 599 | * @pdata: pointer to the private data of the LPSS device |
c78b0830 HK |
600 | * |
601 | * Restores the registers that were previously stored with acpi_lpss_save_ctx(). | |
602 | */ | |
cb39dcdd AS |
603 | static void acpi_lpss_restore_ctx(struct device *dev, |
604 | struct lpss_private_data *pdata) | |
c78b0830 | 605 | { |
c78b0830 HK |
606 | unsigned int i; |
607 | ||
02b98540 AS |
608 | for (i = 0; i < LPSS_PRV_REG_COUNT; i++) { |
609 | unsigned long offset = i * sizeof(u32); | |
610 | ||
611 | __lpss_reg_write(pdata->prv_reg_ctx[i], pdata, offset); | |
612 | dev_dbg(dev, "restoring 0x%08x to LPSS reg at offset 0x%02lx\n", | |
613 | pdata->prv_reg_ctx[i], offset); | |
614 | } | |
615 | } | |
616 | ||
617 | static void acpi_lpss_d3_to_d0_delay(struct lpss_private_data *pdata) | |
618 | { | |
c78b0830 HK |
619 | /* |
620 | * The following delay is needed or the subsequent write operations may | |
621 | * fail. The LPSS devices are actually PCI devices and the PCI spec | |
622 | * expects 10ms delay before the device can be accessed after D3 to D0 | |
b00855ae | 623 | * transition. However some platforms like BSW does not need this delay. |
c78b0830 | 624 | */ |
b00855ae SK |
625 | unsigned int delay = 10; /* default 10ms delay */ |
626 | ||
627 | if (pdata->dev_desc->flags & LPSS_NO_D3_DELAY) | |
628 | delay = 0; | |
629 | ||
630 | msleep(delay); | |
c78b0830 HK |
631 | } |
632 | ||
c3a49cf3 AS |
633 | static int acpi_lpss_activate(struct device *dev) |
634 | { | |
635 | struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev)); | |
636 | int ret; | |
637 | ||
638 | ret = acpi_dev_runtime_resume(dev); | |
639 | if (ret) | |
640 | return ret; | |
641 | ||
642 | acpi_lpss_d3_to_d0_delay(pdata); | |
643 | ||
644 | /* | |
645 | * This is called only on ->probe() stage where a device is either in | |
646 | * known state defined by BIOS or most likely powered off. Due to this | |
647 | * we have to deassert reset line to be sure that ->probe() will | |
648 | * recognize the device. | |
649 | */ | |
650 | if (pdata->dev_desc->flags & LPSS_SAVE_CTX) | |
651 | lpss_deassert_reset(pdata); | |
652 | ||
653 | return 0; | |
654 | } | |
655 | ||
656 | static void acpi_lpss_dismiss(struct device *dev) | |
657 | { | |
658 | acpi_dev_runtime_suspend(dev); | |
659 | } | |
660 | ||
c78b0830 HK |
661 | #ifdef CONFIG_PM_SLEEP |
662 | static int acpi_lpss_suspend_late(struct device *dev) | |
663 | { | |
cb39dcdd AS |
664 | struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev)); |
665 | int ret; | |
c78b0830 | 666 | |
cb39dcdd | 667 | ret = pm_generic_suspend_late(dev); |
c78b0830 HK |
668 | if (ret) |
669 | return ret; | |
670 | ||
cb39dcdd AS |
671 | if (pdata->dev_desc->flags & LPSS_SAVE_CTX) |
672 | acpi_lpss_save_ctx(dev, pdata); | |
673 | ||
c78b0830 HK |
674 | return acpi_dev_suspend_late(dev); |
675 | } | |
676 | ||
f4168b61 | 677 | static int acpi_lpss_resume_early(struct device *dev) |
c78b0830 | 678 | { |
cb39dcdd AS |
679 | struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev)); |
680 | int ret; | |
c78b0830 | 681 | |
cb39dcdd | 682 | ret = acpi_dev_resume_early(dev); |
c78b0830 HK |
683 | if (ret) |
684 | return ret; | |
685 | ||
02b98540 AS |
686 | acpi_lpss_d3_to_d0_delay(pdata); |
687 | ||
cb39dcdd AS |
688 | if (pdata->dev_desc->flags & LPSS_SAVE_CTX) |
689 | acpi_lpss_restore_ctx(dev, pdata); | |
690 | ||
c78b0830 HK |
691 | return pm_generic_resume_early(dev); |
692 | } | |
693 | #endif /* CONFIG_PM_SLEEP */ | |
694 | ||
eebb3e8d AS |
695 | /* IOSF SB for LPSS island */ |
696 | #define LPSS_IOSF_UNIT_LPIOEP 0xA0 | |
697 | #define LPSS_IOSF_UNIT_LPIO1 0xAB | |
698 | #define LPSS_IOSF_UNIT_LPIO2 0xAC | |
699 | ||
700 | #define LPSS_IOSF_PMCSR 0x84 | |
701 | #define LPSS_PMCSR_D0 0 | |
702 | #define LPSS_PMCSR_D3hot 3 | |
703 | #define LPSS_PMCSR_Dx_MASK GENMASK(1, 0) | |
704 | ||
705 | #define LPSS_IOSF_GPIODEF0 0x154 | |
706 | #define LPSS_GPIODEF0_DMA1_D3 BIT(2) | |
707 | #define LPSS_GPIODEF0_DMA2_D3 BIT(3) | |
708 | #define LPSS_GPIODEF0_DMA_D3_MASK GENMASK(3, 2) | |
709 | ||
710 | static DEFINE_MUTEX(lpss_iosf_mutex); | |
711 | ||
712 | static void lpss_iosf_enter_d3_state(void) | |
713 | { | |
714 | u32 value1 = 0; | |
715 | u32 mask1 = LPSS_GPIODEF0_DMA_D3_MASK; | |
716 | u32 value2 = LPSS_PMCSR_D3hot; | |
717 | u32 mask2 = LPSS_PMCSR_Dx_MASK; | |
718 | /* | |
719 | * PMC provides an information about actual status of the LPSS devices. | |
720 | * Here we read the values related to LPSS power island, i.e. LPSS | |
721 | * devices, excluding both LPSS DMA controllers, along with SCC domain. | |
722 | */ | |
723 | u32 func_dis, d3_sts_0, pmc_status, pmc_mask = 0xfe000ffe; | |
724 | int ret; | |
725 | ||
726 | ret = pmc_atom_read(PMC_FUNC_DIS, &func_dis); | |
727 | if (ret) | |
728 | return; | |
729 | ||
730 | mutex_lock(&lpss_iosf_mutex); | |
731 | ||
732 | ret = pmc_atom_read(PMC_D3_STS_0, &d3_sts_0); | |
733 | if (ret) | |
734 | goto exit; | |
735 | ||
736 | /* | |
737 | * Get the status of entire LPSS power island per device basis. | |
738 | * Shutdown both LPSS DMA controllers if and only if all other devices | |
739 | * are already in D3hot. | |
740 | */ | |
741 | pmc_status = (~(d3_sts_0 | func_dis)) & pmc_mask; | |
742 | if (pmc_status) | |
743 | goto exit; | |
744 | ||
745 | iosf_mbi_modify(LPSS_IOSF_UNIT_LPIO1, MBI_CFG_WRITE, | |
746 | LPSS_IOSF_PMCSR, value2, mask2); | |
747 | ||
748 | iosf_mbi_modify(LPSS_IOSF_UNIT_LPIO2, MBI_CFG_WRITE, | |
749 | LPSS_IOSF_PMCSR, value2, mask2); | |
750 | ||
751 | iosf_mbi_modify(LPSS_IOSF_UNIT_LPIOEP, MBI_CR_WRITE, | |
752 | LPSS_IOSF_GPIODEF0, value1, mask1); | |
753 | exit: | |
754 | mutex_unlock(&lpss_iosf_mutex); | |
755 | } | |
756 | ||
757 | static void lpss_iosf_exit_d3_state(void) | |
758 | { | |
759 | u32 value1 = LPSS_GPIODEF0_DMA1_D3 | LPSS_GPIODEF0_DMA2_D3; | |
760 | u32 mask1 = LPSS_GPIODEF0_DMA_D3_MASK; | |
761 | u32 value2 = LPSS_PMCSR_D0; | |
762 | u32 mask2 = LPSS_PMCSR_Dx_MASK; | |
763 | ||
764 | mutex_lock(&lpss_iosf_mutex); | |
765 | ||
766 | iosf_mbi_modify(LPSS_IOSF_UNIT_LPIOEP, MBI_CR_WRITE, | |
767 | LPSS_IOSF_GPIODEF0, value1, mask1); | |
768 | ||
769 | iosf_mbi_modify(LPSS_IOSF_UNIT_LPIO2, MBI_CFG_WRITE, | |
770 | LPSS_IOSF_PMCSR, value2, mask2); | |
771 | ||
772 | iosf_mbi_modify(LPSS_IOSF_UNIT_LPIO1, MBI_CFG_WRITE, | |
773 | LPSS_IOSF_PMCSR, value2, mask2); | |
774 | ||
775 | mutex_unlock(&lpss_iosf_mutex); | |
776 | } | |
777 | ||
c78b0830 HK |
778 | static int acpi_lpss_runtime_suspend(struct device *dev) |
779 | { | |
cb39dcdd AS |
780 | struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev)); |
781 | int ret; | |
c78b0830 | 782 | |
cb39dcdd | 783 | ret = pm_generic_runtime_suspend(dev); |
c78b0830 HK |
784 | if (ret) |
785 | return ret; | |
786 | ||
cb39dcdd AS |
787 | if (pdata->dev_desc->flags & LPSS_SAVE_CTX) |
788 | acpi_lpss_save_ctx(dev, pdata); | |
789 | ||
eebb3e8d AS |
790 | ret = acpi_dev_runtime_suspend(dev); |
791 | ||
792 | /* | |
793 | * This call must be last in the sequence, otherwise PMC will return | |
794 | * wrong status for devices being about to be powered off. See | |
795 | * lpss_iosf_enter_d3_state() for further information. | |
796 | */ | |
797 | if (lpss_quirks & LPSS_QUIRK_ALWAYS_POWER_ON && iosf_mbi_available()) | |
798 | lpss_iosf_enter_d3_state(); | |
799 | ||
800 | return ret; | |
c78b0830 HK |
801 | } |
802 | ||
803 | static int acpi_lpss_runtime_resume(struct device *dev) | |
804 | { | |
cb39dcdd AS |
805 | struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev)); |
806 | int ret; | |
c78b0830 | 807 | |
eebb3e8d AS |
808 | /* |
809 | * This call is kept first to be in symmetry with | |
810 | * acpi_lpss_runtime_suspend() one. | |
811 | */ | |
812 | if (lpss_quirks & LPSS_QUIRK_ALWAYS_POWER_ON && iosf_mbi_available()) | |
813 | lpss_iosf_exit_d3_state(); | |
814 | ||
cb39dcdd | 815 | ret = acpi_dev_runtime_resume(dev); |
c78b0830 HK |
816 | if (ret) |
817 | return ret; | |
818 | ||
02b98540 AS |
819 | acpi_lpss_d3_to_d0_delay(pdata); |
820 | ||
cb39dcdd AS |
821 | if (pdata->dev_desc->flags & LPSS_SAVE_CTX) |
822 | acpi_lpss_restore_ctx(dev, pdata); | |
823 | ||
c78b0830 HK |
824 | return pm_generic_runtime_resume(dev); |
825 | } | |
c78b0830 HK |
826 | #endif /* CONFIG_PM */ |
827 | ||
828 | static struct dev_pm_domain acpi_lpss_pm_domain = { | |
c3a49cf3 AS |
829 | #ifdef CONFIG_PM |
830 | .activate = acpi_lpss_activate, | |
831 | .dismiss = acpi_lpss_dismiss, | |
832 | #endif | |
c78b0830 | 833 | .ops = { |
5de21bb9 | 834 | #ifdef CONFIG_PM |
c78b0830 | 835 | #ifdef CONFIG_PM_SLEEP |
c78b0830 | 836 | .prepare = acpi_subsys_prepare, |
58a1fbbb | 837 | .complete = pm_complete_with_resume_check, |
c78b0830 | 838 | .suspend = acpi_subsys_suspend, |
f4168b61 FZ |
839 | .suspend_late = acpi_lpss_suspend_late, |
840 | .resume_early = acpi_lpss_resume_early, | |
c78b0830 HK |
841 | .freeze = acpi_subsys_freeze, |
842 | .poweroff = acpi_subsys_suspend, | |
f4168b61 FZ |
843 | .poweroff_late = acpi_lpss_suspend_late, |
844 | .restore_early = acpi_lpss_resume_early, | |
c78b0830 | 845 | #endif |
c78b0830 HK |
846 | .runtime_suspend = acpi_lpss_runtime_suspend, |
847 | .runtime_resume = acpi_lpss_runtime_resume, | |
848 | #endif | |
849 | }, | |
850 | }; | |
851 | ||
2e0f8822 RW |
852 | static int acpi_lpss_platform_notify(struct notifier_block *nb, |
853 | unsigned long action, void *data) | |
854 | { | |
855 | struct platform_device *pdev = to_platform_device(data); | |
856 | struct lpss_private_data *pdata; | |
857 | struct acpi_device *adev; | |
858 | const struct acpi_device_id *id; | |
2e0f8822 RW |
859 | |
860 | id = acpi_match_device(acpi_lpss_device_ids, &pdev->dev); | |
861 | if (!id || !id->driver_data) | |
862 | return 0; | |
863 | ||
864 | if (acpi_bus_get_device(ACPI_HANDLE(&pdev->dev), &adev)) | |
865 | return 0; | |
866 | ||
867 | pdata = acpi_driver_data(adev); | |
cb39dcdd | 868 | if (!pdata) |
2e0f8822 RW |
869 | return 0; |
870 | ||
cb39dcdd AS |
871 | if (pdata->mmio_base && |
872 | pdata->mmio_size < pdata->dev_desc->prv_offset + LPSS_LTR_SIZE) { | |
2e0f8822 RW |
873 | dev_err(&pdev->dev, "MMIO size insufficient to access LTR\n"); |
874 | return 0; | |
875 | } | |
876 | ||
c78b0830 | 877 | switch (action) { |
de16d552 | 878 | case BUS_NOTIFY_BIND_DRIVER: |
989561de | 879 | dev_pm_domain_set(&pdev->dev, &acpi_lpss_pm_domain); |
b5f88dd1 | 880 | break; |
de16d552 | 881 | case BUS_NOTIFY_DRIVER_NOT_BOUND: |
b5f88dd1 AS |
882 | case BUS_NOTIFY_UNBOUND_DRIVER: |
883 | pdev->dev.pm_domain = NULL; | |
884 | break; | |
885 | case BUS_NOTIFY_ADD_DEVICE: | |
989561de | 886 | dev_pm_domain_set(&pdev->dev, &acpi_lpss_pm_domain); |
ff8c1af5 | 887 | if (pdata->dev_desc->flags & LPSS_LTR) |
c78b0830 HK |
888 | return sysfs_create_group(&pdev->dev.kobj, |
889 | &lpss_attr_group); | |
01ac170b | 890 | break; |
c78b0830 | 891 | case BUS_NOTIFY_DEL_DEVICE: |
ff8c1af5 | 892 | if (pdata->dev_desc->flags & LPSS_LTR) |
c78b0830 | 893 | sysfs_remove_group(&pdev->dev.kobj, &lpss_attr_group); |
989561de | 894 | dev_pm_domain_set(&pdev->dev, NULL); |
01ac170b | 895 | break; |
c78b0830 HK |
896 | default: |
897 | break; | |
898 | } | |
2e0f8822 | 899 | |
c78b0830 | 900 | return 0; |
2e0f8822 RW |
901 | } |
902 | ||
903 | static struct notifier_block acpi_lpss_nb = { | |
904 | .notifier_call = acpi_lpss_platform_notify, | |
905 | }; | |
906 | ||
1a8f8351 RW |
907 | static void acpi_lpss_bind(struct device *dev) |
908 | { | |
909 | struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev)); | |
910 | ||
ff8c1af5 | 911 | if (!pdata || !pdata->mmio_base || !(pdata->dev_desc->flags & LPSS_LTR)) |
1a8f8351 RW |
912 | return; |
913 | ||
914 | if (pdata->mmio_size >= pdata->dev_desc->prv_offset + LPSS_LTR_SIZE) | |
915 | dev->power.set_latency_tolerance = acpi_lpss_set_ltr; | |
916 | else | |
917 | dev_err(dev, "MMIO size insufficient to access LTR\n"); | |
918 | } | |
919 | ||
920 | static void acpi_lpss_unbind(struct device *dev) | |
921 | { | |
922 | dev->power.set_latency_tolerance = NULL; | |
923 | } | |
924 | ||
f58b082a RW |
925 | static struct acpi_scan_handler lpss_handler = { |
926 | .ids = acpi_lpss_device_ids, | |
927 | .attach = acpi_lpss_create_device, | |
1a8f8351 RW |
928 | .bind = acpi_lpss_bind, |
929 | .unbind = acpi_lpss_unbind, | |
f58b082a RW |
930 | }; |
931 | ||
932 | void __init acpi_lpss_init(void) | |
933 | { | |
eebb3e8d AS |
934 | const struct x86_cpu_id *id; |
935 | int ret; | |
936 | ||
937 | ret = lpt_clk_init(); | |
938 | if (ret) | |
939 | return; | |
940 | ||
941 | id = x86_match_cpu(lpss_cpu_ids); | |
942 | if (id) | |
943 | lpss_quirks |= LPSS_QUIRK_ALWAYS_POWER_ON; | |
944 | ||
945 | bus_register_notifier(&platform_bus_type, &acpi_lpss_nb); | |
946 | acpi_scan_add_handler(&lpss_handler); | |
f58b082a | 947 | } |
d6ddaaac RW |
948 | |
949 | #else | |
950 | ||
951 | static struct acpi_scan_handler lpss_handler = { | |
952 | .ids = acpi_lpss_device_ids, | |
953 | }; | |
954 | ||
955 | void __init acpi_lpss_init(void) | |
956 | { | |
957 | acpi_scan_add_handler(&lpss_handler); | |
958 | } | |
959 | ||
960 | #endif /* CONFIG_X86_INTEL_LPSS */ |