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b94d5230 DW |
1 | /* |
2 | * Copyright(c) 2013-2015 Intel Corporation. All rights reserved. | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify | |
5 | * it under the terms of version 2 of the GNU General Public License as | |
6 | * published by the Free Software Foundation. | |
7 | * | |
8 | * This program is distributed in the hope that it will be useful, but | |
9 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
10 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
11 | * General Public License for more details. | |
12 | */ | |
13 | #include <linux/list_sort.h> | |
14 | #include <linux/libnvdimm.h> | |
15 | #include <linux/module.h> | |
047fc8a1 | 16 | #include <linux/mutex.h> |
62232e45 | 17 | #include <linux/ndctl.h> |
0caeef63 | 18 | #include <linux/delay.h> |
b94d5230 DW |
19 | #include <linux/list.h> |
20 | #include <linux/acpi.h> | |
eaf96153 | 21 | #include <linux/sort.h> |
c2ad2954 | 22 | #include <linux/pmem.h> |
047fc8a1 | 23 | #include <linux/io.h> |
1cf03c00 | 24 | #include <linux/nd.h> |
96601adb | 25 | #include <asm/cacheflush.h> |
b94d5230 DW |
26 | #include "nfit.h" |
27 | ||
047fc8a1 RZ |
28 | /* |
29 | * For readq() and writeq() on 32-bit builds, the hi-lo, lo-hi order is | |
30 | * irrelevant. | |
31 | */ | |
2f8e2c87 | 32 | #include <linux/io-64-nonatomic-hi-lo.h> |
047fc8a1 | 33 | |
4d88a97a DW |
34 | static bool force_enable_dimms; |
35 | module_param(force_enable_dimms, bool, S_IRUGO|S_IWUSR); | |
36 | MODULE_PARM_DESC(force_enable_dimms, "Ignore _STA (ACPI DIMM device) status"); | |
37 | ||
1cf03c00 DW |
38 | static unsigned int scrub_timeout = NFIT_ARS_TIMEOUT; |
39 | module_param(scrub_timeout, uint, S_IRUGO|S_IWUSR); | |
40 | MODULE_PARM_DESC(scrub_timeout, "Initial scrub timeout in seconds"); | |
41 | ||
42 | /* after three payloads of overflow, it's dead jim */ | |
43 | static unsigned int scrub_overflow_abort = 3; | |
44 | module_param(scrub_overflow_abort, uint, S_IRUGO|S_IWUSR); | |
45 | MODULE_PARM_DESC(scrub_overflow_abort, | |
46 | "Number of times we overflow ARS results before abort"); | |
47 | ||
87554098 DW |
48 | static bool disable_vendor_specific; |
49 | module_param(disable_vendor_specific, bool, S_IRUGO); | |
50 | MODULE_PARM_DESC(disable_vendor_specific, | |
51 | "Limit commands to the publicly specified set\n"); | |
52 | ||
7ae0fa43 DW |
53 | static struct workqueue_struct *nfit_wq; |
54 | ||
20985164 VV |
55 | struct nfit_table_prev { |
56 | struct list_head spas; | |
57 | struct list_head memdevs; | |
58 | struct list_head dcrs; | |
59 | struct list_head bdws; | |
60 | struct list_head idts; | |
61 | struct list_head flushes; | |
62 | }; | |
63 | ||
b94d5230 DW |
64 | static u8 nfit_uuid[NFIT_UUID_MAX][16]; |
65 | ||
6bc75619 | 66 | const u8 *to_nfit_uuid(enum nfit_uuids id) |
b94d5230 DW |
67 | { |
68 | return nfit_uuid[id]; | |
69 | } | |
6bc75619 | 70 | EXPORT_SYMBOL(to_nfit_uuid); |
b94d5230 | 71 | |
62232e45 DW |
72 | static struct acpi_nfit_desc *to_acpi_nfit_desc( |
73 | struct nvdimm_bus_descriptor *nd_desc) | |
74 | { | |
75 | return container_of(nd_desc, struct acpi_nfit_desc, nd_desc); | |
76 | } | |
77 | ||
78 | static struct acpi_device *to_acpi_dev(struct acpi_nfit_desc *acpi_desc) | |
79 | { | |
80 | struct nvdimm_bus_descriptor *nd_desc = &acpi_desc->nd_desc; | |
81 | ||
82 | /* | |
83 | * If provider == 'ACPI.NFIT' we can assume 'dev' is a struct | |
84 | * acpi_device. | |
85 | */ | |
86 | if (!nd_desc->provider_name | |
87 | || strcmp(nd_desc->provider_name, "ACPI.NFIT") != 0) | |
88 | return NULL; | |
89 | ||
90 | return to_acpi_device(acpi_desc->dev); | |
91 | } | |
92 | ||
aef25338 DW |
93 | static int xlat_status(void *buf, unsigned int cmd) |
94 | { | |
d4f32367 | 95 | struct nd_cmd_clear_error *clear_err; |
aef25338 DW |
96 | struct nd_cmd_ars_status *ars_status; |
97 | struct nd_cmd_ars_start *ars_start; | |
98 | struct nd_cmd_ars_cap *ars_cap; | |
99 | u16 flags; | |
100 | ||
101 | switch (cmd) { | |
102 | case ND_CMD_ARS_CAP: | |
103 | ars_cap = buf; | |
104 | if ((ars_cap->status & 0xffff) == NFIT_ARS_CAP_NONE) | |
105 | return -ENOTTY; | |
106 | ||
107 | /* Command failed */ | |
108 | if (ars_cap->status & 0xffff) | |
109 | return -EIO; | |
110 | ||
111 | /* No supported scan types for this range */ | |
112 | flags = ND_ARS_PERSISTENT | ND_ARS_VOLATILE; | |
113 | if ((ars_cap->status >> 16 & flags) == 0) | |
114 | return -ENOTTY; | |
115 | break; | |
116 | case ND_CMD_ARS_START: | |
117 | ars_start = buf; | |
118 | /* ARS is in progress */ | |
119 | if ((ars_start->status & 0xffff) == NFIT_ARS_START_BUSY) | |
120 | return -EBUSY; | |
121 | ||
122 | /* Command failed */ | |
123 | if (ars_start->status & 0xffff) | |
124 | return -EIO; | |
125 | break; | |
126 | case ND_CMD_ARS_STATUS: | |
127 | ars_status = buf; | |
128 | /* Command failed */ | |
129 | if (ars_status->status & 0xffff) | |
130 | return -EIO; | |
131 | /* Check extended status (Upper two bytes) */ | |
132 | if (ars_status->status == NFIT_ARS_STATUS_DONE) | |
133 | return 0; | |
134 | ||
135 | /* ARS is in progress */ | |
136 | if (ars_status->status == NFIT_ARS_STATUS_BUSY) | |
137 | return -EBUSY; | |
138 | ||
139 | /* No ARS performed for the current boot */ | |
140 | if (ars_status->status == NFIT_ARS_STATUS_NONE) | |
141 | return -EAGAIN; | |
142 | ||
143 | /* | |
144 | * ARS interrupted, either we overflowed or some other | |
145 | * agent wants the scan to stop. If we didn't overflow | |
146 | * then just continue with the returned results. | |
147 | */ | |
148 | if (ars_status->status == NFIT_ARS_STATUS_INTR) { | |
149 | if (ars_status->flags & NFIT_ARS_F_OVERFLOW) | |
150 | return -ENOSPC; | |
151 | return 0; | |
152 | } | |
153 | ||
154 | /* Unknown status */ | |
155 | if (ars_status->status >> 16) | |
156 | return -EIO; | |
157 | break; | |
d4f32367 DW |
158 | case ND_CMD_CLEAR_ERROR: |
159 | clear_err = buf; | |
160 | if (clear_err->status & 0xffff) | |
161 | return -EIO; | |
162 | if (!clear_err->cleared) | |
163 | return -EIO; | |
164 | if (clear_err->length > clear_err->cleared) | |
165 | return clear_err->cleared; | |
166 | break; | |
aef25338 DW |
167 | default: |
168 | break; | |
169 | } | |
170 | ||
171 | return 0; | |
172 | } | |
173 | ||
b94d5230 DW |
174 | static int acpi_nfit_ctl(struct nvdimm_bus_descriptor *nd_desc, |
175 | struct nvdimm *nvdimm, unsigned int cmd, void *buf, | |
aef25338 | 176 | unsigned int buf_len, int *cmd_rc) |
b94d5230 | 177 | { |
62232e45 | 178 | struct acpi_nfit_desc *acpi_desc = to_acpi_nfit_desc(nd_desc); |
62232e45 | 179 | union acpi_object in_obj, in_buf, *out_obj; |
31eca76b | 180 | const struct nd_cmd_desc *desc = NULL; |
62232e45 | 181 | struct device *dev = acpi_desc->dev; |
31eca76b | 182 | struct nd_cmd_pkg *call_pkg = NULL; |
62232e45 | 183 | const char *cmd_name, *dimm_name; |
31eca76b | 184 | unsigned long cmd_mask, dsm_mask; |
62232e45 | 185 | acpi_handle handle; |
31eca76b | 186 | unsigned int func; |
62232e45 DW |
187 | const u8 *uuid; |
188 | u32 offset; | |
189 | int rc, i; | |
190 | ||
31eca76b DW |
191 | func = cmd; |
192 | if (cmd == ND_CMD_CALL) { | |
193 | call_pkg = buf; | |
194 | func = call_pkg->nd_command; | |
195 | } | |
196 | ||
62232e45 DW |
197 | if (nvdimm) { |
198 | struct nfit_mem *nfit_mem = nvdimm_provider_data(nvdimm); | |
199 | struct acpi_device *adev = nfit_mem->adev; | |
200 | ||
201 | if (!adev) | |
202 | return -ENOTTY; | |
31eca76b DW |
203 | if (call_pkg && nfit_mem->family != call_pkg->nd_family) |
204 | return -ENOTTY; | |
205 | ||
047fc8a1 | 206 | dimm_name = nvdimm_name(nvdimm); |
62232e45 | 207 | cmd_name = nvdimm_cmd_name(cmd); |
e3654eca | 208 | cmd_mask = nvdimm_cmd_mask(nvdimm); |
62232e45 DW |
209 | dsm_mask = nfit_mem->dsm_mask; |
210 | desc = nd_cmd_dimm_desc(cmd); | |
31eca76b | 211 | uuid = to_nfit_uuid(nfit_mem->family); |
62232e45 DW |
212 | handle = adev->handle; |
213 | } else { | |
214 | struct acpi_device *adev = to_acpi_dev(acpi_desc); | |
215 | ||
216 | cmd_name = nvdimm_bus_cmd_name(cmd); | |
e3654eca | 217 | cmd_mask = nd_desc->cmd_mask; |
31eca76b | 218 | dsm_mask = cmd_mask; |
62232e45 DW |
219 | desc = nd_cmd_bus_desc(cmd); |
220 | uuid = to_nfit_uuid(NFIT_DEV_BUS); | |
221 | handle = adev->handle; | |
222 | dimm_name = "bus"; | |
223 | } | |
224 | ||
225 | if (!desc || (cmd && (desc->out_num + desc->in_num == 0))) | |
226 | return -ENOTTY; | |
227 | ||
31eca76b | 228 | if (!test_bit(cmd, &cmd_mask) || !test_bit(func, &dsm_mask)) |
62232e45 DW |
229 | return -ENOTTY; |
230 | ||
231 | in_obj.type = ACPI_TYPE_PACKAGE; | |
232 | in_obj.package.count = 1; | |
233 | in_obj.package.elements = &in_buf; | |
234 | in_buf.type = ACPI_TYPE_BUFFER; | |
235 | in_buf.buffer.pointer = buf; | |
236 | in_buf.buffer.length = 0; | |
237 | ||
238 | /* libnvdimm has already validated the input envelope */ | |
239 | for (i = 0; i < desc->in_num; i++) | |
240 | in_buf.buffer.length += nd_cmd_in_size(nvdimm, cmd, desc, | |
241 | i, buf); | |
242 | ||
31eca76b DW |
243 | if (call_pkg) { |
244 | /* skip over package wrapper */ | |
245 | in_buf.buffer.pointer = (void *) &call_pkg->nd_payload; | |
246 | in_buf.buffer.length = call_pkg->nd_size_in; | |
247 | } | |
248 | ||
62232e45 | 249 | if (IS_ENABLED(CONFIG_ACPI_NFIT_DEBUG)) { |
31eca76b DW |
250 | dev_dbg(dev, "%s:%s cmd: %d: func: %d input length: %d\n", |
251 | __func__, dimm_name, cmd, func, | |
252 | in_buf.buffer.length); | |
253 | print_hex_dump_debug("nvdimm in ", DUMP_PREFIX_OFFSET, 4, 4, | |
254 | in_buf.buffer.pointer, | |
255 | min_t(u32, 256, in_buf.buffer.length), true); | |
62232e45 DW |
256 | } |
257 | ||
31eca76b | 258 | out_obj = acpi_evaluate_dsm(handle, uuid, 1, func, &in_obj); |
62232e45 DW |
259 | if (!out_obj) { |
260 | dev_dbg(dev, "%s:%s _DSM failed cmd: %s\n", __func__, dimm_name, | |
261 | cmd_name); | |
262 | return -EINVAL; | |
263 | } | |
264 | ||
31eca76b DW |
265 | if (call_pkg) { |
266 | call_pkg->nd_fw_size = out_obj->buffer.length; | |
267 | memcpy(call_pkg->nd_payload + call_pkg->nd_size_in, | |
268 | out_obj->buffer.pointer, | |
269 | min(call_pkg->nd_fw_size, call_pkg->nd_size_out)); | |
270 | ||
271 | ACPI_FREE(out_obj); | |
272 | /* | |
273 | * Need to support FW function w/o known size in advance. | |
274 | * Caller can determine required size based upon nd_fw_size. | |
275 | * If we return an error (like elsewhere) then caller wouldn't | |
276 | * be able to rely upon data returned to make calculation. | |
277 | */ | |
278 | return 0; | |
279 | } | |
280 | ||
62232e45 DW |
281 | if (out_obj->package.type != ACPI_TYPE_BUFFER) { |
282 | dev_dbg(dev, "%s:%s unexpected output object type cmd: %s type: %d\n", | |
283 | __func__, dimm_name, cmd_name, out_obj->type); | |
284 | rc = -EINVAL; | |
285 | goto out; | |
286 | } | |
287 | ||
288 | if (IS_ENABLED(CONFIG_ACPI_NFIT_DEBUG)) { | |
289 | dev_dbg(dev, "%s:%s cmd: %s output length: %d\n", __func__, | |
290 | dimm_name, cmd_name, out_obj->buffer.length); | |
291 | print_hex_dump_debug(cmd_name, DUMP_PREFIX_OFFSET, 4, | |
292 | 4, out_obj->buffer.pointer, min_t(u32, 128, | |
293 | out_obj->buffer.length), true); | |
294 | } | |
295 | ||
296 | for (i = 0, offset = 0; i < desc->out_num; i++) { | |
297 | u32 out_size = nd_cmd_out_size(nvdimm, cmd, desc, i, buf, | |
298 | (u32 *) out_obj->buffer.pointer); | |
299 | ||
300 | if (offset + out_size > out_obj->buffer.length) { | |
301 | dev_dbg(dev, "%s:%s output object underflow cmd: %s field: %d\n", | |
302 | __func__, dimm_name, cmd_name, i); | |
303 | break; | |
304 | } | |
305 | ||
306 | if (in_buf.buffer.length + offset + out_size > buf_len) { | |
307 | dev_dbg(dev, "%s:%s output overrun cmd: %s field: %d\n", | |
308 | __func__, dimm_name, cmd_name, i); | |
309 | rc = -ENXIO; | |
310 | goto out; | |
311 | } | |
312 | memcpy(buf + in_buf.buffer.length + offset, | |
313 | out_obj->buffer.pointer + offset, out_size); | |
314 | offset += out_size; | |
315 | } | |
316 | if (offset + in_buf.buffer.length < buf_len) { | |
317 | if (i >= 1) { | |
318 | /* | |
319 | * status valid, return the number of bytes left | |
320 | * unfilled in the output buffer | |
321 | */ | |
322 | rc = buf_len - offset - in_buf.buffer.length; | |
aef25338 DW |
323 | if (cmd_rc) |
324 | *cmd_rc = xlat_status(buf, cmd); | |
62232e45 DW |
325 | } else { |
326 | dev_err(dev, "%s:%s underrun cmd: %s buf_len: %d out_len: %d\n", | |
327 | __func__, dimm_name, cmd_name, buf_len, | |
328 | offset); | |
329 | rc = -ENXIO; | |
330 | } | |
2eea6582 | 331 | } else { |
62232e45 | 332 | rc = 0; |
2eea6582 DW |
333 | if (cmd_rc) |
334 | *cmd_rc = xlat_status(buf, cmd); | |
335 | } | |
62232e45 DW |
336 | |
337 | out: | |
338 | ACPI_FREE(out_obj); | |
339 | ||
340 | return rc; | |
b94d5230 DW |
341 | } |
342 | ||
343 | static const char *spa_type_name(u16 type) | |
344 | { | |
345 | static const char *to_name[] = { | |
346 | [NFIT_SPA_VOLATILE] = "volatile", | |
347 | [NFIT_SPA_PM] = "pmem", | |
348 | [NFIT_SPA_DCR] = "dimm-control-region", | |
349 | [NFIT_SPA_BDW] = "block-data-window", | |
350 | [NFIT_SPA_VDISK] = "volatile-disk", | |
351 | [NFIT_SPA_VCD] = "volatile-cd", | |
352 | [NFIT_SPA_PDISK] = "persistent-disk", | |
353 | [NFIT_SPA_PCD] = "persistent-cd", | |
354 | ||
355 | }; | |
356 | ||
357 | if (type > NFIT_SPA_PCD) | |
358 | return "unknown"; | |
359 | ||
360 | return to_name[type]; | |
361 | } | |
362 | ||
363 | static int nfit_spa_type(struct acpi_nfit_system_address *spa) | |
364 | { | |
365 | int i; | |
366 | ||
367 | for (i = 0; i < NFIT_UUID_MAX; i++) | |
368 | if (memcmp(to_nfit_uuid(i), spa->range_guid, 16) == 0) | |
369 | return i; | |
370 | return -1; | |
371 | } | |
372 | ||
373 | static bool add_spa(struct acpi_nfit_desc *acpi_desc, | |
20985164 | 374 | struct nfit_table_prev *prev, |
b94d5230 DW |
375 | struct acpi_nfit_system_address *spa) |
376 | { | |
826c416f | 377 | size_t length = min_t(size_t, sizeof(*spa), spa->header.length); |
b94d5230 | 378 | struct device *dev = acpi_desc->dev; |
20985164 VV |
379 | struct nfit_spa *nfit_spa; |
380 | ||
381 | list_for_each_entry(nfit_spa, &prev->spas, list) { | |
826c416f | 382 | if (memcmp(nfit_spa->spa, spa, length) == 0) { |
20985164 VV |
383 | list_move_tail(&nfit_spa->list, &acpi_desc->spas); |
384 | return true; | |
385 | } | |
386 | } | |
b94d5230 | 387 | |
20985164 | 388 | nfit_spa = devm_kzalloc(dev, sizeof(*nfit_spa), GFP_KERNEL); |
b94d5230 DW |
389 | if (!nfit_spa) |
390 | return false; | |
391 | INIT_LIST_HEAD(&nfit_spa->list); | |
392 | nfit_spa->spa = spa; | |
393 | list_add_tail(&nfit_spa->list, &acpi_desc->spas); | |
394 | dev_dbg(dev, "%s: spa index: %d type: %s\n", __func__, | |
395 | spa->range_index, | |
396 | spa_type_name(nfit_spa_type(spa))); | |
397 | return true; | |
398 | } | |
399 | ||
400 | static bool add_memdev(struct acpi_nfit_desc *acpi_desc, | |
20985164 | 401 | struct nfit_table_prev *prev, |
b94d5230 DW |
402 | struct acpi_nfit_memory_map *memdev) |
403 | { | |
826c416f | 404 | size_t length = min_t(size_t, sizeof(*memdev), memdev->header.length); |
b94d5230 | 405 | struct device *dev = acpi_desc->dev; |
20985164 | 406 | struct nfit_memdev *nfit_memdev; |
b94d5230 | 407 | |
20985164 | 408 | list_for_each_entry(nfit_memdev, &prev->memdevs, list) |
826c416f | 409 | if (memcmp(nfit_memdev->memdev, memdev, length) == 0) { |
20985164 VV |
410 | list_move_tail(&nfit_memdev->list, &acpi_desc->memdevs); |
411 | return true; | |
412 | } | |
413 | ||
414 | nfit_memdev = devm_kzalloc(dev, sizeof(*nfit_memdev), GFP_KERNEL); | |
b94d5230 DW |
415 | if (!nfit_memdev) |
416 | return false; | |
417 | INIT_LIST_HEAD(&nfit_memdev->list); | |
418 | nfit_memdev->memdev = memdev; | |
419 | list_add_tail(&nfit_memdev->list, &acpi_desc->memdevs); | |
420 | dev_dbg(dev, "%s: memdev handle: %#x spa: %d dcr: %d\n", | |
421 | __func__, memdev->device_handle, memdev->range_index, | |
422 | memdev->region_index); | |
423 | return true; | |
424 | } | |
425 | ||
426 | static bool add_dcr(struct acpi_nfit_desc *acpi_desc, | |
20985164 | 427 | struct nfit_table_prev *prev, |
b94d5230 DW |
428 | struct acpi_nfit_control_region *dcr) |
429 | { | |
826c416f | 430 | size_t length = min_t(size_t, sizeof(*dcr), dcr->header.length); |
b94d5230 | 431 | struct device *dev = acpi_desc->dev; |
20985164 VV |
432 | struct nfit_dcr *nfit_dcr; |
433 | ||
434 | list_for_each_entry(nfit_dcr, &prev->dcrs, list) | |
826c416f | 435 | if (memcmp(nfit_dcr->dcr, dcr, length) == 0) { |
20985164 VV |
436 | list_move_tail(&nfit_dcr->list, &acpi_desc->dcrs); |
437 | return true; | |
438 | } | |
b94d5230 | 439 | |
20985164 | 440 | nfit_dcr = devm_kzalloc(dev, sizeof(*nfit_dcr), GFP_KERNEL); |
b94d5230 DW |
441 | if (!nfit_dcr) |
442 | return false; | |
443 | INIT_LIST_HEAD(&nfit_dcr->list); | |
444 | nfit_dcr->dcr = dcr; | |
445 | list_add_tail(&nfit_dcr->list, &acpi_desc->dcrs); | |
446 | dev_dbg(dev, "%s: dcr index: %d windows: %d\n", __func__, | |
447 | dcr->region_index, dcr->windows); | |
448 | return true; | |
449 | } | |
450 | ||
451 | static bool add_bdw(struct acpi_nfit_desc *acpi_desc, | |
20985164 | 452 | struct nfit_table_prev *prev, |
b94d5230 DW |
453 | struct acpi_nfit_data_region *bdw) |
454 | { | |
826c416f | 455 | size_t length = min_t(size_t, sizeof(*bdw), bdw->header.length); |
b94d5230 | 456 | struct device *dev = acpi_desc->dev; |
20985164 VV |
457 | struct nfit_bdw *nfit_bdw; |
458 | ||
459 | list_for_each_entry(nfit_bdw, &prev->bdws, list) | |
826c416f | 460 | if (memcmp(nfit_bdw->bdw, bdw, length) == 0) { |
20985164 VV |
461 | list_move_tail(&nfit_bdw->list, &acpi_desc->bdws); |
462 | return true; | |
463 | } | |
b94d5230 | 464 | |
20985164 | 465 | nfit_bdw = devm_kzalloc(dev, sizeof(*nfit_bdw), GFP_KERNEL); |
b94d5230 DW |
466 | if (!nfit_bdw) |
467 | return false; | |
468 | INIT_LIST_HEAD(&nfit_bdw->list); | |
469 | nfit_bdw->bdw = bdw; | |
470 | list_add_tail(&nfit_bdw->list, &acpi_desc->bdws); | |
471 | dev_dbg(dev, "%s: bdw dcr: %d windows: %d\n", __func__, | |
472 | bdw->region_index, bdw->windows); | |
473 | return true; | |
474 | } | |
475 | ||
047fc8a1 | 476 | static bool add_idt(struct acpi_nfit_desc *acpi_desc, |
20985164 | 477 | struct nfit_table_prev *prev, |
047fc8a1 RZ |
478 | struct acpi_nfit_interleave *idt) |
479 | { | |
826c416f | 480 | size_t length = min_t(size_t, sizeof(*idt), idt->header.length); |
047fc8a1 | 481 | struct device *dev = acpi_desc->dev; |
20985164 VV |
482 | struct nfit_idt *nfit_idt; |
483 | ||
484 | list_for_each_entry(nfit_idt, &prev->idts, list) | |
826c416f | 485 | if (memcmp(nfit_idt->idt, idt, length) == 0) { |
20985164 VV |
486 | list_move_tail(&nfit_idt->list, &acpi_desc->idts); |
487 | return true; | |
488 | } | |
047fc8a1 | 489 | |
20985164 | 490 | nfit_idt = devm_kzalloc(dev, sizeof(*nfit_idt), GFP_KERNEL); |
047fc8a1 RZ |
491 | if (!nfit_idt) |
492 | return false; | |
493 | INIT_LIST_HEAD(&nfit_idt->list); | |
494 | nfit_idt->idt = idt; | |
495 | list_add_tail(&nfit_idt->list, &acpi_desc->idts); | |
496 | dev_dbg(dev, "%s: idt index: %d num_lines: %d\n", __func__, | |
497 | idt->interleave_index, idt->line_count); | |
498 | return true; | |
499 | } | |
500 | ||
c2ad2954 | 501 | static bool add_flush(struct acpi_nfit_desc *acpi_desc, |
20985164 | 502 | struct nfit_table_prev *prev, |
c2ad2954 RZ |
503 | struct acpi_nfit_flush_address *flush) |
504 | { | |
826c416f | 505 | size_t length = min_t(size_t, sizeof(*flush), flush->header.length); |
c2ad2954 | 506 | struct device *dev = acpi_desc->dev; |
20985164 | 507 | struct nfit_flush *nfit_flush; |
c2ad2954 | 508 | |
20985164 | 509 | list_for_each_entry(nfit_flush, &prev->flushes, list) |
826c416f | 510 | if (memcmp(nfit_flush->flush, flush, length) == 0) { |
20985164 VV |
511 | list_move_tail(&nfit_flush->list, &acpi_desc->flushes); |
512 | return true; | |
513 | } | |
514 | ||
515 | nfit_flush = devm_kzalloc(dev, sizeof(*nfit_flush), GFP_KERNEL); | |
c2ad2954 RZ |
516 | if (!nfit_flush) |
517 | return false; | |
518 | INIT_LIST_HEAD(&nfit_flush->list); | |
519 | nfit_flush->flush = flush; | |
520 | list_add_tail(&nfit_flush->list, &acpi_desc->flushes); | |
521 | dev_dbg(dev, "%s: nfit_flush handle: %d hint_count: %d\n", __func__, | |
522 | flush->device_handle, flush->hint_count); | |
523 | return true; | |
524 | } | |
525 | ||
20985164 VV |
526 | static void *add_table(struct acpi_nfit_desc *acpi_desc, |
527 | struct nfit_table_prev *prev, void *table, const void *end) | |
b94d5230 DW |
528 | { |
529 | struct device *dev = acpi_desc->dev; | |
530 | struct acpi_nfit_header *hdr; | |
531 | void *err = ERR_PTR(-ENOMEM); | |
532 | ||
533 | if (table >= end) | |
534 | return NULL; | |
535 | ||
536 | hdr = table; | |
564d5011 VV |
537 | if (!hdr->length) { |
538 | dev_warn(dev, "found a zero length table '%d' parsing nfit\n", | |
539 | hdr->type); | |
540 | return NULL; | |
541 | } | |
542 | ||
b94d5230 DW |
543 | switch (hdr->type) { |
544 | case ACPI_NFIT_TYPE_SYSTEM_ADDRESS: | |
20985164 | 545 | if (!add_spa(acpi_desc, prev, table)) |
b94d5230 DW |
546 | return err; |
547 | break; | |
548 | case ACPI_NFIT_TYPE_MEMORY_MAP: | |
20985164 | 549 | if (!add_memdev(acpi_desc, prev, table)) |
b94d5230 DW |
550 | return err; |
551 | break; | |
552 | case ACPI_NFIT_TYPE_CONTROL_REGION: | |
20985164 | 553 | if (!add_dcr(acpi_desc, prev, table)) |
b94d5230 DW |
554 | return err; |
555 | break; | |
556 | case ACPI_NFIT_TYPE_DATA_REGION: | |
20985164 | 557 | if (!add_bdw(acpi_desc, prev, table)) |
b94d5230 DW |
558 | return err; |
559 | break; | |
b94d5230 | 560 | case ACPI_NFIT_TYPE_INTERLEAVE: |
20985164 | 561 | if (!add_idt(acpi_desc, prev, table)) |
047fc8a1 | 562 | return err; |
b94d5230 DW |
563 | break; |
564 | case ACPI_NFIT_TYPE_FLUSH_ADDRESS: | |
20985164 | 565 | if (!add_flush(acpi_desc, prev, table)) |
c2ad2954 | 566 | return err; |
b94d5230 DW |
567 | break; |
568 | case ACPI_NFIT_TYPE_SMBIOS: | |
569 | dev_dbg(dev, "%s: smbios\n", __func__); | |
570 | break; | |
571 | default: | |
572 | dev_err(dev, "unknown table '%d' parsing nfit\n", hdr->type); | |
573 | break; | |
574 | } | |
575 | ||
576 | return table + hdr->length; | |
577 | } | |
578 | ||
579 | static void nfit_mem_find_spa_bdw(struct acpi_nfit_desc *acpi_desc, | |
580 | struct nfit_mem *nfit_mem) | |
581 | { | |
582 | u32 device_handle = __to_nfit_memdev(nfit_mem)->device_handle; | |
583 | u16 dcr = nfit_mem->dcr->region_index; | |
584 | struct nfit_spa *nfit_spa; | |
585 | ||
586 | list_for_each_entry(nfit_spa, &acpi_desc->spas, list) { | |
587 | u16 range_index = nfit_spa->spa->range_index; | |
588 | int type = nfit_spa_type(nfit_spa->spa); | |
589 | struct nfit_memdev *nfit_memdev; | |
590 | ||
591 | if (type != NFIT_SPA_BDW) | |
592 | continue; | |
593 | ||
594 | list_for_each_entry(nfit_memdev, &acpi_desc->memdevs, list) { | |
595 | if (nfit_memdev->memdev->range_index != range_index) | |
596 | continue; | |
597 | if (nfit_memdev->memdev->device_handle != device_handle) | |
598 | continue; | |
599 | if (nfit_memdev->memdev->region_index != dcr) | |
600 | continue; | |
601 | ||
602 | nfit_mem->spa_bdw = nfit_spa->spa; | |
603 | return; | |
604 | } | |
605 | } | |
606 | ||
607 | dev_dbg(acpi_desc->dev, "SPA-BDW not found for SPA-DCR %d\n", | |
608 | nfit_mem->spa_dcr->range_index); | |
609 | nfit_mem->bdw = NULL; | |
610 | } | |
611 | ||
6697b2cf | 612 | static void nfit_mem_init_bdw(struct acpi_nfit_desc *acpi_desc, |
b94d5230 DW |
613 | struct nfit_mem *nfit_mem, struct acpi_nfit_system_address *spa) |
614 | { | |
615 | u16 dcr = __to_nfit_memdev(nfit_mem)->region_index; | |
047fc8a1 | 616 | struct nfit_memdev *nfit_memdev; |
b94d5230 | 617 | struct nfit_bdw *nfit_bdw; |
047fc8a1 RZ |
618 | struct nfit_idt *nfit_idt; |
619 | u16 idt_idx, range_index; | |
b94d5230 | 620 | |
b94d5230 DW |
621 | list_for_each_entry(nfit_bdw, &acpi_desc->bdws, list) { |
622 | if (nfit_bdw->bdw->region_index != dcr) | |
623 | continue; | |
624 | nfit_mem->bdw = nfit_bdw->bdw; | |
625 | break; | |
626 | } | |
627 | ||
628 | if (!nfit_mem->bdw) | |
6697b2cf | 629 | return; |
b94d5230 DW |
630 | |
631 | nfit_mem_find_spa_bdw(acpi_desc, nfit_mem); | |
047fc8a1 RZ |
632 | |
633 | if (!nfit_mem->spa_bdw) | |
6697b2cf | 634 | return; |
047fc8a1 RZ |
635 | |
636 | range_index = nfit_mem->spa_bdw->range_index; | |
637 | list_for_each_entry(nfit_memdev, &acpi_desc->memdevs, list) { | |
638 | if (nfit_memdev->memdev->range_index != range_index || | |
639 | nfit_memdev->memdev->region_index != dcr) | |
640 | continue; | |
641 | nfit_mem->memdev_bdw = nfit_memdev->memdev; | |
642 | idt_idx = nfit_memdev->memdev->interleave_index; | |
643 | list_for_each_entry(nfit_idt, &acpi_desc->idts, list) { | |
644 | if (nfit_idt->idt->interleave_index != idt_idx) | |
645 | continue; | |
646 | nfit_mem->idt_bdw = nfit_idt->idt; | |
647 | break; | |
648 | } | |
649 | break; | |
650 | } | |
b94d5230 DW |
651 | } |
652 | ||
653 | static int nfit_mem_dcr_init(struct acpi_nfit_desc *acpi_desc, | |
654 | struct acpi_nfit_system_address *spa) | |
655 | { | |
656 | struct nfit_mem *nfit_mem, *found; | |
657 | struct nfit_memdev *nfit_memdev; | |
658 | int type = nfit_spa_type(spa); | |
b94d5230 DW |
659 | |
660 | switch (type) { | |
661 | case NFIT_SPA_DCR: | |
662 | case NFIT_SPA_PM: | |
663 | break; | |
664 | default: | |
665 | return 0; | |
666 | } | |
667 | ||
668 | list_for_each_entry(nfit_memdev, &acpi_desc->memdevs, list) { | |
ad9ac5e1 | 669 | struct nfit_flush *nfit_flush; |
6697b2cf DW |
670 | struct nfit_dcr *nfit_dcr; |
671 | u32 device_handle; | |
672 | u16 dcr; | |
b94d5230 DW |
673 | |
674 | if (nfit_memdev->memdev->range_index != spa->range_index) | |
675 | continue; | |
676 | found = NULL; | |
677 | dcr = nfit_memdev->memdev->region_index; | |
6697b2cf | 678 | device_handle = nfit_memdev->memdev->device_handle; |
b94d5230 | 679 | list_for_each_entry(nfit_mem, &acpi_desc->dimms, list) |
6697b2cf DW |
680 | if (__to_nfit_memdev(nfit_mem)->device_handle |
681 | == device_handle) { | |
b94d5230 DW |
682 | found = nfit_mem; |
683 | break; | |
684 | } | |
685 | ||
686 | if (found) | |
687 | nfit_mem = found; | |
688 | else { | |
689 | nfit_mem = devm_kzalloc(acpi_desc->dev, | |
690 | sizeof(*nfit_mem), GFP_KERNEL); | |
691 | if (!nfit_mem) | |
692 | return -ENOMEM; | |
693 | INIT_LIST_HEAD(&nfit_mem->list); | |
8cc6ddfc | 694 | nfit_mem->acpi_desc = acpi_desc; |
6697b2cf DW |
695 | list_add(&nfit_mem->list, &acpi_desc->dimms); |
696 | } | |
697 | ||
698 | list_for_each_entry(nfit_dcr, &acpi_desc->dcrs, list) { | |
699 | if (nfit_dcr->dcr->region_index != dcr) | |
700 | continue; | |
701 | /* | |
702 | * Record the control region for the dimm. For | |
703 | * the ACPI 6.1 case, where there are separate | |
704 | * control regions for the pmem vs blk | |
705 | * interfaces, be sure to record the extended | |
706 | * blk details. | |
707 | */ | |
708 | if (!nfit_mem->dcr) | |
709 | nfit_mem->dcr = nfit_dcr->dcr; | |
710 | else if (nfit_mem->dcr->windows == 0 | |
711 | && nfit_dcr->dcr->windows) | |
712 | nfit_mem->dcr = nfit_dcr->dcr; | |
713 | break; | |
714 | } | |
715 | ||
ad9ac5e1 DW |
716 | list_for_each_entry(nfit_flush, &acpi_desc->flushes, list) { |
717 | if (nfit_flush->flush->device_handle != device_handle) | |
718 | continue; | |
719 | nfit_mem->nfit_flush = nfit_flush; | |
720 | break; | |
721 | } | |
722 | ||
6697b2cf DW |
723 | if (dcr && !nfit_mem->dcr) { |
724 | dev_err(acpi_desc->dev, "SPA %d missing DCR %d\n", | |
725 | spa->range_index, dcr); | |
726 | return -ENODEV; | |
b94d5230 DW |
727 | } |
728 | ||
729 | if (type == NFIT_SPA_DCR) { | |
047fc8a1 RZ |
730 | struct nfit_idt *nfit_idt; |
731 | u16 idt_idx; | |
732 | ||
b94d5230 DW |
733 | /* multiple dimms may share a SPA when interleaved */ |
734 | nfit_mem->spa_dcr = spa; | |
735 | nfit_mem->memdev_dcr = nfit_memdev->memdev; | |
047fc8a1 RZ |
736 | idt_idx = nfit_memdev->memdev->interleave_index; |
737 | list_for_each_entry(nfit_idt, &acpi_desc->idts, list) { | |
738 | if (nfit_idt->idt->interleave_index != idt_idx) | |
739 | continue; | |
740 | nfit_mem->idt_dcr = nfit_idt->idt; | |
741 | break; | |
742 | } | |
6697b2cf | 743 | nfit_mem_init_bdw(acpi_desc, nfit_mem, spa); |
b94d5230 DW |
744 | } else { |
745 | /* | |
746 | * A single dimm may belong to multiple SPA-PM | |
747 | * ranges, record at least one in addition to | |
748 | * any SPA-DCR range. | |
749 | */ | |
750 | nfit_mem->memdev_pmem = nfit_memdev->memdev; | |
751 | } | |
b94d5230 DW |
752 | } |
753 | ||
754 | return 0; | |
755 | } | |
756 | ||
757 | static int nfit_mem_cmp(void *priv, struct list_head *_a, struct list_head *_b) | |
758 | { | |
759 | struct nfit_mem *a = container_of(_a, typeof(*a), list); | |
760 | struct nfit_mem *b = container_of(_b, typeof(*b), list); | |
761 | u32 handleA, handleB; | |
762 | ||
763 | handleA = __to_nfit_memdev(a)->device_handle; | |
764 | handleB = __to_nfit_memdev(b)->device_handle; | |
765 | if (handleA < handleB) | |
766 | return -1; | |
767 | else if (handleA > handleB) | |
768 | return 1; | |
769 | return 0; | |
770 | } | |
771 | ||
772 | static int nfit_mem_init(struct acpi_nfit_desc *acpi_desc) | |
773 | { | |
774 | struct nfit_spa *nfit_spa; | |
775 | ||
776 | /* | |
777 | * For each SPA-DCR or SPA-PMEM address range find its | |
778 | * corresponding MEMDEV(s). From each MEMDEV find the | |
779 | * corresponding DCR. Then, if we're operating on a SPA-DCR, | |
780 | * try to find a SPA-BDW and a corresponding BDW that references | |
781 | * the DCR. Throw it all into an nfit_mem object. Note, that | |
782 | * BDWs are optional. | |
783 | */ | |
784 | list_for_each_entry(nfit_spa, &acpi_desc->spas, list) { | |
785 | int rc; | |
786 | ||
787 | rc = nfit_mem_dcr_init(acpi_desc, nfit_spa->spa); | |
788 | if (rc) | |
789 | return rc; | |
790 | } | |
791 | ||
792 | list_sort(NULL, &acpi_desc->dimms, nfit_mem_cmp); | |
793 | ||
794 | return 0; | |
795 | } | |
796 | ||
45def22c DW |
797 | static ssize_t revision_show(struct device *dev, |
798 | struct device_attribute *attr, char *buf) | |
799 | { | |
800 | struct nvdimm_bus *nvdimm_bus = to_nvdimm_bus(dev); | |
801 | struct nvdimm_bus_descriptor *nd_desc = to_nd_desc(nvdimm_bus); | |
802 | struct acpi_nfit_desc *acpi_desc = to_acpi_desc(nd_desc); | |
803 | ||
6b577c9d | 804 | return sprintf(buf, "%d\n", acpi_desc->acpi_header.revision); |
45def22c DW |
805 | } |
806 | static DEVICE_ATTR_RO(revision); | |
807 | ||
808 | static struct attribute *acpi_nfit_attributes[] = { | |
809 | &dev_attr_revision.attr, | |
810 | NULL, | |
811 | }; | |
812 | ||
813 | static struct attribute_group acpi_nfit_attribute_group = { | |
814 | .name = "nfit", | |
815 | .attrs = acpi_nfit_attributes, | |
816 | }; | |
817 | ||
a61fe6f7 | 818 | static const struct attribute_group *acpi_nfit_attribute_groups[] = { |
45def22c DW |
819 | &nvdimm_bus_attribute_group, |
820 | &acpi_nfit_attribute_group, | |
821 | NULL, | |
822 | }; | |
823 | ||
e6dfb2de DW |
824 | static struct acpi_nfit_memory_map *to_nfit_memdev(struct device *dev) |
825 | { | |
826 | struct nvdimm *nvdimm = to_nvdimm(dev); | |
827 | struct nfit_mem *nfit_mem = nvdimm_provider_data(nvdimm); | |
828 | ||
829 | return __to_nfit_memdev(nfit_mem); | |
830 | } | |
831 | ||
832 | static struct acpi_nfit_control_region *to_nfit_dcr(struct device *dev) | |
833 | { | |
834 | struct nvdimm *nvdimm = to_nvdimm(dev); | |
835 | struct nfit_mem *nfit_mem = nvdimm_provider_data(nvdimm); | |
836 | ||
837 | return nfit_mem->dcr; | |
838 | } | |
839 | ||
840 | static ssize_t handle_show(struct device *dev, | |
841 | struct device_attribute *attr, char *buf) | |
842 | { | |
843 | struct acpi_nfit_memory_map *memdev = to_nfit_memdev(dev); | |
844 | ||
845 | return sprintf(buf, "%#x\n", memdev->device_handle); | |
846 | } | |
847 | static DEVICE_ATTR_RO(handle); | |
848 | ||
849 | static ssize_t phys_id_show(struct device *dev, | |
850 | struct device_attribute *attr, char *buf) | |
851 | { | |
852 | struct acpi_nfit_memory_map *memdev = to_nfit_memdev(dev); | |
853 | ||
854 | return sprintf(buf, "%#x\n", memdev->physical_id); | |
855 | } | |
856 | static DEVICE_ATTR_RO(phys_id); | |
857 | ||
858 | static ssize_t vendor_show(struct device *dev, | |
859 | struct device_attribute *attr, char *buf) | |
860 | { | |
861 | struct acpi_nfit_control_region *dcr = to_nfit_dcr(dev); | |
862 | ||
5ad9a7fd | 863 | return sprintf(buf, "0x%04x\n", be16_to_cpu(dcr->vendor_id)); |
e6dfb2de DW |
864 | } |
865 | static DEVICE_ATTR_RO(vendor); | |
866 | ||
867 | static ssize_t rev_id_show(struct device *dev, | |
868 | struct device_attribute *attr, char *buf) | |
869 | { | |
870 | struct acpi_nfit_control_region *dcr = to_nfit_dcr(dev); | |
871 | ||
5ad9a7fd | 872 | return sprintf(buf, "0x%04x\n", be16_to_cpu(dcr->revision_id)); |
e6dfb2de DW |
873 | } |
874 | static DEVICE_ATTR_RO(rev_id); | |
875 | ||
876 | static ssize_t device_show(struct device *dev, | |
877 | struct device_attribute *attr, char *buf) | |
878 | { | |
879 | struct acpi_nfit_control_region *dcr = to_nfit_dcr(dev); | |
880 | ||
5ad9a7fd | 881 | return sprintf(buf, "0x%04x\n", be16_to_cpu(dcr->device_id)); |
e6dfb2de DW |
882 | } |
883 | static DEVICE_ATTR_RO(device); | |
884 | ||
6ca72085 DW |
885 | static ssize_t subsystem_vendor_show(struct device *dev, |
886 | struct device_attribute *attr, char *buf) | |
887 | { | |
888 | struct acpi_nfit_control_region *dcr = to_nfit_dcr(dev); | |
889 | ||
890 | return sprintf(buf, "0x%04x\n", be16_to_cpu(dcr->subsystem_vendor_id)); | |
891 | } | |
892 | static DEVICE_ATTR_RO(subsystem_vendor); | |
893 | ||
894 | static ssize_t subsystem_rev_id_show(struct device *dev, | |
895 | struct device_attribute *attr, char *buf) | |
896 | { | |
897 | struct acpi_nfit_control_region *dcr = to_nfit_dcr(dev); | |
898 | ||
899 | return sprintf(buf, "0x%04x\n", | |
900 | be16_to_cpu(dcr->subsystem_revision_id)); | |
901 | } | |
902 | static DEVICE_ATTR_RO(subsystem_rev_id); | |
903 | ||
904 | static ssize_t subsystem_device_show(struct device *dev, | |
905 | struct device_attribute *attr, char *buf) | |
906 | { | |
907 | struct acpi_nfit_control_region *dcr = to_nfit_dcr(dev); | |
908 | ||
909 | return sprintf(buf, "0x%04x\n", be16_to_cpu(dcr->subsystem_device_id)); | |
910 | } | |
911 | static DEVICE_ATTR_RO(subsystem_device); | |
912 | ||
8cc6ddfc DW |
913 | static int num_nvdimm_formats(struct nvdimm *nvdimm) |
914 | { | |
915 | struct nfit_mem *nfit_mem = nvdimm_provider_data(nvdimm); | |
916 | int formats = 0; | |
917 | ||
918 | if (nfit_mem->memdev_pmem) | |
919 | formats++; | |
920 | if (nfit_mem->memdev_bdw) | |
921 | formats++; | |
922 | return formats; | |
923 | } | |
924 | ||
e6dfb2de DW |
925 | static ssize_t format_show(struct device *dev, |
926 | struct device_attribute *attr, char *buf) | |
927 | { | |
928 | struct acpi_nfit_control_region *dcr = to_nfit_dcr(dev); | |
929 | ||
1b982baf | 930 | return sprintf(buf, "0x%04x\n", be16_to_cpu(dcr->code)); |
e6dfb2de DW |
931 | } |
932 | static DEVICE_ATTR_RO(format); | |
933 | ||
8cc6ddfc DW |
934 | static ssize_t format1_show(struct device *dev, |
935 | struct device_attribute *attr, char *buf) | |
936 | { | |
937 | u32 handle; | |
938 | ssize_t rc = -ENXIO; | |
939 | struct nfit_mem *nfit_mem; | |
940 | struct nfit_memdev *nfit_memdev; | |
941 | struct acpi_nfit_desc *acpi_desc; | |
942 | struct nvdimm *nvdimm = to_nvdimm(dev); | |
943 | struct acpi_nfit_control_region *dcr = to_nfit_dcr(dev); | |
944 | ||
945 | nfit_mem = nvdimm_provider_data(nvdimm); | |
946 | acpi_desc = nfit_mem->acpi_desc; | |
947 | handle = to_nfit_memdev(dev)->device_handle; | |
948 | ||
949 | /* assumes DIMMs have at most 2 published interface codes */ | |
950 | mutex_lock(&acpi_desc->init_mutex); | |
951 | list_for_each_entry(nfit_memdev, &acpi_desc->memdevs, list) { | |
952 | struct acpi_nfit_memory_map *memdev = nfit_memdev->memdev; | |
953 | struct nfit_dcr *nfit_dcr; | |
954 | ||
955 | if (memdev->device_handle != handle) | |
956 | continue; | |
957 | ||
958 | list_for_each_entry(nfit_dcr, &acpi_desc->dcrs, list) { | |
959 | if (nfit_dcr->dcr->region_index != memdev->region_index) | |
960 | continue; | |
961 | if (nfit_dcr->dcr->code == dcr->code) | |
962 | continue; | |
1b982baf DW |
963 | rc = sprintf(buf, "%#x\n", |
964 | be16_to_cpu(nfit_dcr->dcr->code)); | |
8cc6ddfc DW |
965 | break; |
966 | } | |
967 | if (rc != ENXIO) | |
968 | break; | |
969 | } | |
970 | mutex_unlock(&acpi_desc->init_mutex); | |
971 | return rc; | |
972 | } | |
973 | static DEVICE_ATTR_RO(format1); | |
974 | ||
975 | static ssize_t formats_show(struct device *dev, | |
976 | struct device_attribute *attr, char *buf) | |
977 | { | |
978 | struct nvdimm *nvdimm = to_nvdimm(dev); | |
979 | ||
980 | return sprintf(buf, "%d\n", num_nvdimm_formats(nvdimm)); | |
981 | } | |
982 | static DEVICE_ATTR_RO(formats); | |
983 | ||
e6dfb2de DW |
984 | static ssize_t serial_show(struct device *dev, |
985 | struct device_attribute *attr, char *buf) | |
986 | { | |
987 | struct acpi_nfit_control_region *dcr = to_nfit_dcr(dev); | |
988 | ||
5ad9a7fd | 989 | return sprintf(buf, "0x%08x\n", be32_to_cpu(dcr->serial_number)); |
e6dfb2de DW |
990 | } |
991 | static DEVICE_ATTR_RO(serial); | |
992 | ||
a94e3fbe DW |
993 | static ssize_t family_show(struct device *dev, |
994 | struct device_attribute *attr, char *buf) | |
995 | { | |
996 | struct nvdimm *nvdimm = to_nvdimm(dev); | |
997 | struct nfit_mem *nfit_mem = nvdimm_provider_data(nvdimm); | |
998 | ||
999 | if (nfit_mem->family < 0) | |
1000 | return -ENXIO; | |
1001 | return sprintf(buf, "%d\n", nfit_mem->family); | |
1002 | } | |
1003 | static DEVICE_ATTR_RO(family); | |
1004 | ||
1005 | static ssize_t dsm_mask_show(struct device *dev, | |
1006 | struct device_attribute *attr, char *buf) | |
1007 | { | |
1008 | struct nvdimm *nvdimm = to_nvdimm(dev); | |
1009 | struct nfit_mem *nfit_mem = nvdimm_provider_data(nvdimm); | |
1010 | ||
1011 | if (nfit_mem->family < 0) | |
1012 | return -ENXIO; | |
1013 | return sprintf(buf, "%#lx\n", nfit_mem->dsm_mask); | |
1014 | } | |
1015 | static DEVICE_ATTR_RO(dsm_mask); | |
1016 | ||
58138820 DW |
1017 | static ssize_t flags_show(struct device *dev, |
1018 | struct device_attribute *attr, char *buf) | |
1019 | { | |
1020 | u16 flags = to_nfit_memdev(dev)->flags; | |
1021 | ||
1022 | return sprintf(buf, "%s%s%s%s%s\n", | |
402bae59 TK |
1023 | flags & ACPI_NFIT_MEM_SAVE_FAILED ? "save_fail " : "", |
1024 | flags & ACPI_NFIT_MEM_RESTORE_FAILED ? "restore_fail " : "", | |
1025 | flags & ACPI_NFIT_MEM_FLUSH_FAILED ? "flush_fail " : "", | |
ca321d1c | 1026 | flags & ACPI_NFIT_MEM_NOT_ARMED ? "not_armed " : "", |
402bae59 | 1027 | flags & ACPI_NFIT_MEM_HEALTH_OBSERVED ? "smart_event " : ""); |
58138820 DW |
1028 | } |
1029 | static DEVICE_ATTR_RO(flags); | |
1030 | ||
38a879ba TK |
1031 | static ssize_t id_show(struct device *dev, |
1032 | struct device_attribute *attr, char *buf) | |
1033 | { | |
1034 | struct acpi_nfit_control_region *dcr = to_nfit_dcr(dev); | |
1035 | ||
1036 | if (dcr->valid_fields & ACPI_NFIT_CONTROL_MFG_INFO_VALID) | |
1037 | return sprintf(buf, "%04x-%02x-%04x-%08x\n", | |
1038 | be16_to_cpu(dcr->vendor_id), | |
1039 | dcr->manufacturing_location, | |
1040 | be16_to_cpu(dcr->manufacturing_date), | |
1041 | be32_to_cpu(dcr->serial_number)); | |
1042 | else | |
1043 | return sprintf(buf, "%04x-%08x\n", | |
1044 | be16_to_cpu(dcr->vendor_id), | |
1045 | be32_to_cpu(dcr->serial_number)); | |
1046 | } | |
1047 | static DEVICE_ATTR_RO(id); | |
1048 | ||
e6dfb2de DW |
1049 | static struct attribute *acpi_nfit_dimm_attributes[] = { |
1050 | &dev_attr_handle.attr, | |
1051 | &dev_attr_phys_id.attr, | |
1052 | &dev_attr_vendor.attr, | |
1053 | &dev_attr_device.attr, | |
6ca72085 DW |
1054 | &dev_attr_rev_id.attr, |
1055 | &dev_attr_subsystem_vendor.attr, | |
1056 | &dev_attr_subsystem_device.attr, | |
1057 | &dev_attr_subsystem_rev_id.attr, | |
e6dfb2de | 1058 | &dev_attr_format.attr, |
8cc6ddfc DW |
1059 | &dev_attr_formats.attr, |
1060 | &dev_attr_format1.attr, | |
e6dfb2de | 1061 | &dev_attr_serial.attr, |
58138820 | 1062 | &dev_attr_flags.attr, |
38a879ba | 1063 | &dev_attr_id.attr, |
a94e3fbe DW |
1064 | &dev_attr_family.attr, |
1065 | &dev_attr_dsm_mask.attr, | |
e6dfb2de DW |
1066 | NULL, |
1067 | }; | |
1068 | ||
1069 | static umode_t acpi_nfit_dimm_attr_visible(struct kobject *kobj, | |
1070 | struct attribute *a, int n) | |
1071 | { | |
1072 | struct device *dev = container_of(kobj, struct device, kobj); | |
8cc6ddfc | 1073 | struct nvdimm *nvdimm = to_nvdimm(dev); |
e6dfb2de | 1074 | |
8cc6ddfc DW |
1075 | if (!to_nfit_dcr(dev)) |
1076 | return 0; | |
1077 | if (a == &dev_attr_format1.attr && num_nvdimm_formats(nvdimm) <= 1) | |
e6dfb2de | 1078 | return 0; |
8cc6ddfc | 1079 | return a->mode; |
e6dfb2de DW |
1080 | } |
1081 | ||
1082 | static struct attribute_group acpi_nfit_dimm_attribute_group = { | |
1083 | .name = "nfit", | |
1084 | .attrs = acpi_nfit_dimm_attributes, | |
1085 | .is_visible = acpi_nfit_dimm_attr_visible, | |
1086 | }; | |
1087 | ||
1088 | static const struct attribute_group *acpi_nfit_dimm_attribute_groups[] = { | |
62232e45 | 1089 | &nvdimm_attribute_group, |
4d88a97a | 1090 | &nd_device_attribute_group, |
e6dfb2de DW |
1091 | &acpi_nfit_dimm_attribute_group, |
1092 | NULL, | |
1093 | }; | |
1094 | ||
1095 | static struct nvdimm *acpi_nfit_dimm_by_handle(struct acpi_nfit_desc *acpi_desc, | |
1096 | u32 device_handle) | |
1097 | { | |
1098 | struct nfit_mem *nfit_mem; | |
1099 | ||
1100 | list_for_each_entry(nfit_mem, &acpi_desc->dimms, list) | |
1101 | if (__to_nfit_memdev(nfit_mem)->device_handle == device_handle) | |
1102 | return nfit_mem->nvdimm; | |
1103 | ||
1104 | return NULL; | |
1105 | } | |
1106 | ||
62232e45 DW |
1107 | static int acpi_nfit_add_dimm(struct acpi_nfit_desc *acpi_desc, |
1108 | struct nfit_mem *nfit_mem, u32 device_handle) | |
1109 | { | |
1110 | struct acpi_device *adev, *adev_dimm; | |
1111 | struct device *dev = acpi_desc->dev; | |
31eca76b DW |
1112 | unsigned long dsm_mask; |
1113 | const u8 *uuid; | |
60e95f43 | 1114 | int i; |
62232e45 | 1115 | |
e3654eca DW |
1116 | /* nfit test assumes 1:1 relationship between commands and dsms */ |
1117 | nfit_mem->dsm_mask = acpi_desc->dimm_cmd_force_en; | |
31eca76b | 1118 | nfit_mem->family = NVDIMM_FAMILY_INTEL; |
62232e45 DW |
1119 | adev = to_acpi_dev(acpi_desc); |
1120 | if (!adev) | |
1121 | return 0; | |
1122 | ||
1123 | adev_dimm = acpi_find_child_device(adev, device_handle, false); | |
1124 | nfit_mem->adev = adev_dimm; | |
1125 | if (!adev_dimm) { | |
1126 | dev_err(dev, "no ACPI.NFIT device with _ADR %#x, disabling...\n", | |
1127 | device_handle); | |
4d88a97a | 1128 | return force_enable_dimms ? 0 : -ENODEV; |
62232e45 DW |
1129 | } |
1130 | ||
31eca76b | 1131 | /* |
e02fb726 | 1132 | * Until standardization materializes we need to consider 4 |
31eca76b DW |
1133 | * different command sets. Note, that checking for function0 (bit0) |
1134 | * tells us if any commands are reachable through this uuid. | |
1135 | */ | |
e02fb726 | 1136 | for (i = NVDIMM_FAMILY_INTEL; i <= NVDIMM_FAMILY_MSFT; i++) |
31eca76b DW |
1137 | if (acpi_check_dsm(adev_dimm->handle, to_nfit_uuid(i), 1, 1)) |
1138 | break; | |
1139 | ||
1140 | /* limit the supported commands to those that are publicly documented */ | |
1141 | nfit_mem->family = i; | |
87554098 | 1142 | if (nfit_mem->family == NVDIMM_FAMILY_INTEL) { |
31eca76b | 1143 | dsm_mask = 0x3fe; |
87554098 DW |
1144 | if (disable_vendor_specific) |
1145 | dsm_mask &= ~(1 << ND_CMD_VENDOR); | |
e02fb726 | 1146 | } else if (nfit_mem->family == NVDIMM_FAMILY_HPE1) { |
31eca76b | 1147 | dsm_mask = 0x1c3c76; |
e02fb726 | 1148 | } else if (nfit_mem->family == NVDIMM_FAMILY_HPE2) { |
31eca76b | 1149 | dsm_mask = 0x1fe; |
87554098 DW |
1150 | if (disable_vendor_specific) |
1151 | dsm_mask &= ~(1 << 8); | |
e02fb726 | 1152 | } else if (nfit_mem->family == NVDIMM_FAMILY_MSFT) { |
1153 | dsm_mask = 0xffffffff; | |
87554098 | 1154 | } else { |
31eca76b DW |
1155 | dev_err(dev, "unknown dimm command family\n"); |
1156 | nfit_mem->family = -1; | |
1157 | return force_enable_dimms ? 0 : -ENODEV; | |
1158 | } | |
1159 | ||
1160 | uuid = to_nfit_uuid(nfit_mem->family); | |
1161 | for_each_set_bit(i, &dsm_mask, BITS_PER_LONG) | |
62232e45 DW |
1162 | if (acpi_check_dsm(adev_dimm->handle, uuid, 1, 1ULL << i)) |
1163 | set_bit(i, &nfit_mem->dsm_mask); | |
1164 | ||
60e95f43 | 1165 | return 0; |
62232e45 DW |
1166 | } |
1167 | ||
e6dfb2de DW |
1168 | static int acpi_nfit_register_dimms(struct acpi_nfit_desc *acpi_desc) |
1169 | { | |
1170 | struct nfit_mem *nfit_mem; | |
4d88a97a | 1171 | int dimm_count = 0; |
e6dfb2de DW |
1172 | |
1173 | list_for_each_entry(nfit_mem, &acpi_desc->dimms, list) { | |
31eca76b | 1174 | unsigned long flags = 0, cmd_mask; |
e6dfb2de | 1175 | struct nvdimm *nvdimm; |
e6dfb2de | 1176 | u32 device_handle; |
58138820 | 1177 | u16 mem_flags; |
62232e45 | 1178 | int rc; |
e6dfb2de DW |
1179 | |
1180 | device_handle = __to_nfit_memdev(nfit_mem)->device_handle; | |
1181 | nvdimm = acpi_nfit_dimm_by_handle(acpi_desc, device_handle); | |
1182 | if (nvdimm) { | |
20985164 | 1183 | dimm_count++; |
e6dfb2de DW |
1184 | continue; |
1185 | } | |
1186 | ||
1187 | if (nfit_mem->bdw && nfit_mem->memdev_pmem) | |
1188 | flags |= NDD_ALIASING; | |
1189 | ||
58138820 | 1190 | mem_flags = __to_nfit_memdev(nfit_mem)->flags; |
ca321d1c | 1191 | if (mem_flags & ACPI_NFIT_MEM_NOT_ARMED) |
58138820 DW |
1192 | flags |= NDD_UNARMED; |
1193 | ||
62232e45 DW |
1194 | rc = acpi_nfit_add_dimm(acpi_desc, nfit_mem, device_handle); |
1195 | if (rc) | |
1196 | continue; | |
1197 | ||
e3654eca | 1198 | /* |
31eca76b DW |
1199 | * TODO: provide translation for non-NVDIMM_FAMILY_INTEL |
1200 | * devices (i.e. from nd_cmd to acpi_dsm) to standardize the | |
1201 | * userspace interface. | |
e3654eca | 1202 | */ |
31eca76b DW |
1203 | cmd_mask = 1UL << ND_CMD_CALL; |
1204 | if (nfit_mem->family == NVDIMM_FAMILY_INTEL) | |
1205 | cmd_mask |= nfit_mem->dsm_mask; | |
1206 | ||
e6dfb2de | 1207 | nvdimm = nvdimm_create(acpi_desc->nvdimm_bus, nfit_mem, |
62232e45 | 1208 | acpi_nfit_dimm_attribute_groups, |
31eca76b | 1209 | flags, cmd_mask); |
e6dfb2de DW |
1210 | if (!nvdimm) |
1211 | return -ENOMEM; | |
1212 | ||
1213 | nfit_mem->nvdimm = nvdimm; | |
4d88a97a | 1214 | dimm_count++; |
58138820 DW |
1215 | |
1216 | if ((mem_flags & ACPI_NFIT_MEM_FAILED_MASK) == 0) | |
1217 | continue; | |
1218 | ||
402bae59 | 1219 | dev_info(acpi_desc->dev, "%s flags:%s%s%s%s\n", |
58138820 | 1220 | nvdimm_name(nvdimm), |
402bae59 TK |
1221 | mem_flags & ACPI_NFIT_MEM_SAVE_FAILED ? " save_fail" : "", |
1222 | mem_flags & ACPI_NFIT_MEM_RESTORE_FAILED ? " restore_fail":"", | |
1223 | mem_flags & ACPI_NFIT_MEM_FLUSH_FAILED ? " flush_fail" : "", | |
ca321d1c | 1224 | mem_flags & ACPI_NFIT_MEM_NOT_ARMED ? " not_armed" : ""); |
58138820 | 1225 | |
e6dfb2de DW |
1226 | } |
1227 | ||
4d88a97a | 1228 | return nvdimm_bus_check_dimm_count(acpi_desc->nvdimm_bus, dimm_count); |
e6dfb2de DW |
1229 | } |
1230 | ||
62232e45 DW |
1231 | static void acpi_nfit_init_dsms(struct acpi_nfit_desc *acpi_desc) |
1232 | { | |
1233 | struct nvdimm_bus_descriptor *nd_desc = &acpi_desc->nd_desc; | |
1234 | const u8 *uuid = to_nfit_uuid(NFIT_DEV_BUS); | |
1235 | struct acpi_device *adev; | |
1236 | int i; | |
1237 | ||
e3654eca | 1238 | nd_desc->cmd_mask = acpi_desc->bus_cmd_force_en; |
62232e45 DW |
1239 | adev = to_acpi_dev(acpi_desc); |
1240 | if (!adev) | |
1241 | return; | |
1242 | ||
d4f32367 | 1243 | for (i = ND_CMD_ARS_CAP; i <= ND_CMD_CLEAR_ERROR; i++) |
62232e45 | 1244 | if (acpi_check_dsm(adev->handle, uuid, 1, 1ULL << i)) |
e3654eca | 1245 | set_bit(i, &nd_desc->cmd_mask); |
62232e45 DW |
1246 | } |
1247 | ||
1f7df6f8 DW |
1248 | static ssize_t range_index_show(struct device *dev, |
1249 | struct device_attribute *attr, char *buf) | |
1250 | { | |
1251 | struct nd_region *nd_region = to_nd_region(dev); | |
1252 | struct nfit_spa *nfit_spa = nd_region_provider_data(nd_region); | |
1253 | ||
1254 | return sprintf(buf, "%d\n", nfit_spa->spa->range_index); | |
1255 | } | |
1256 | static DEVICE_ATTR_RO(range_index); | |
1257 | ||
1258 | static struct attribute *acpi_nfit_region_attributes[] = { | |
1259 | &dev_attr_range_index.attr, | |
1260 | NULL, | |
1261 | }; | |
1262 | ||
1263 | static struct attribute_group acpi_nfit_region_attribute_group = { | |
1264 | .name = "nfit", | |
1265 | .attrs = acpi_nfit_region_attributes, | |
1266 | }; | |
1267 | ||
1268 | static const struct attribute_group *acpi_nfit_region_attribute_groups[] = { | |
1269 | &nd_region_attribute_group, | |
1270 | &nd_mapping_attribute_group, | |
3d88002e | 1271 | &nd_device_attribute_group, |
74ae66c3 | 1272 | &nd_numa_attribute_group, |
1f7df6f8 DW |
1273 | &acpi_nfit_region_attribute_group, |
1274 | NULL, | |
1275 | }; | |
1276 | ||
eaf96153 DW |
1277 | /* enough info to uniquely specify an interleave set */ |
1278 | struct nfit_set_info { | |
1279 | struct nfit_set_info_map { | |
1280 | u64 region_offset; | |
1281 | u32 serial_number; | |
1282 | u32 pad; | |
1283 | } mapping[0]; | |
1284 | }; | |
1285 | ||
1286 | static size_t sizeof_nfit_set_info(int num_mappings) | |
1287 | { | |
1288 | return sizeof(struct nfit_set_info) | |
1289 | + num_mappings * sizeof(struct nfit_set_info_map); | |
1290 | } | |
1291 | ||
1292 | static int cmp_map(const void *m0, const void *m1) | |
1293 | { | |
1294 | const struct nfit_set_info_map *map0 = m0; | |
1295 | const struct nfit_set_info_map *map1 = m1; | |
1296 | ||
1297 | return memcmp(&map0->region_offset, &map1->region_offset, | |
1298 | sizeof(u64)); | |
1299 | } | |
1300 | ||
1301 | /* Retrieve the nth entry referencing this spa */ | |
1302 | static struct acpi_nfit_memory_map *memdev_from_spa( | |
1303 | struct acpi_nfit_desc *acpi_desc, u16 range_index, int n) | |
1304 | { | |
1305 | struct nfit_memdev *nfit_memdev; | |
1306 | ||
1307 | list_for_each_entry(nfit_memdev, &acpi_desc->memdevs, list) | |
1308 | if (nfit_memdev->memdev->range_index == range_index) | |
1309 | if (n-- == 0) | |
1310 | return nfit_memdev->memdev; | |
1311 | return NULL; | |
1312 | } | |
1313 | ||
1314 | static int acpi_nfit_init_interleave_set(struct acpi_nfit_desc *acpi_desc, | |
1315 | struct nd_region_desc *ndr_desc, | |
1316 | struct acpi_nfit_system_address *spa) | |
1317 | { | |
1318 | int i, spa_type = nfit_spa_type(spa); | |
1319 | struct device *dev = acpi_desc->dev; | |
1320 | struct nd_interleave_set *nd_set; | |
1321 | u16 nr = ndr_desc->num_mappings; | |
1322 | struct nfit_set_info *info; | |
1323 | ||
1324 | if (spa_type == NFIT_SPA_PM || spa_type == NFIT_SPA_VOLATILE) | |
1325 | /* pass */; | |
1326 | else | |
1327 | return 0; | |
1328 | ||
1329 | nd_set = devm_kzalloc(dev, sizeof(*nd_set), GFP_KERNEL); | |
1330 | if (!nd_set) | |
1331 | return -ENOMEM; | |
1332 | ||
1333 | info = devm_kzalloc(dev, sizeof_nfit_set_info(nr), GFP_KERNEL); | |
1334 | if (!info) | |
1335 | return -ENOMEM; | |
1336 | for (i = 0; i < nr; i++) { | |
1337 | struct nd_mapping *nd_mapping = &ndr_desc->nd_mapping[i]; | |
1338 | struct nfit_set_info_map *map = &info->mapping[i]; | |
1339 | struct nvdimm *nvdimm = nd_mapping->nvdimm; | |
1340 | struct nfit_mem *nfit_mem = nvdimm_provider_data(nvdimm); | |
1341 | struct acpi_nfit_memory_map *memdev = memdev_from_spa(acpi_desc, | |
1342 | spa->range_index, i); | |
1343 | ||
1344 | if (!memdev || !nfit_mem->dcr) { | |
1345 | dev_err(dev, "%s: failed to find DCR\n", __func__); | |
1346 | return -ENODEV; | |
1347 | } | |
1348 | ||
1349 | map->region_offset = memdev->region_offset; | |
1350 | map->serial_number = nfit_mem->dcr->serial_number; | |
1351 | } | |
1352 | ||
1353 | sort(&info->mapping[0], nr, sizeof(struct nfit_set_info_map), | |
1354 | cmp_map, NULL); | |
1355 | nd_set->cookie = nd_fletcher64(info, sizeof_nfit_set_info(nr), 0); | |
1356 | ndr_desc->nd_set = nd_set; | |
1357 | devm_kfree(dev, info); | |
1358 | ||
1359 | return 0; | |
1360 | } | |
1361 | ||
047fc8a1 RZ |
1362 | static u64 to_interleave_offset(u64 offset, struct nfit_blk_mmio *mmio) |
1363 | { | |
1364 | struct acpi_nfit_interleave *idt = mmio->idt; | |
1365 | u32 sub_line_offset, line_index, line_offset; | |
1366 | u64 line_no, table_skip_count, table_offset; | |
1367 | ||
1368 | line_no = div_u64_rem(offset, mmio->line_size, &sub_line_offset); | |
1369 | table_skip_count = div_u64_rem(line_no, mmio->num_lines, &line_index); | |
1370 | line_offset = idt->line_offset[line_index] | |
1371 | * mmio->line_size; | |
1372 | table_offset = table_skip_count * mmio->table_size; | |
1373 | ||
1374 | return mmio->base_offset + line_offset + table_offset + sub_line_offset; | |
1375 | } | |
1376 | ||
c2ad2954 RZ |
1377 | static void wmb_blk(struct nfit_blk *nfit_blk) |
1378 | { | |
1379 | ||
1380 | if (nfit_blk->nvdimm_flush) { | |
1381 | /* | |
1382 | * The first wmb() is needed to 'sfence' all previous writes | |
1383 | * such that they are architecturally visible for the platform | |
1384 | * buffer flush. Note that we've already arranged for pmem | |
1385 | * writes to avoid the cache via arch_memcpy_to_pmem(). The | |
1386 | * final wmb() ensures ordering for the NVDIMM flush write. | |
1387 | */ | |
1388 | wmb(); | |
1389 | writeq(1, nfit_blk->nvdimm_flush); | |
1390 | wmb(); | |
1391 | } else | |
1392 | wmb_pmem(); | |
1393 | } | |
1394 | ||
de4a196c | 1395 | static u32 read_blk_stat(struct nfit_blk *nfit_blk, unsigned int bw) |
047fc8a1 RZ |
1396 | { |
1397 | struct nfit_blk_mmio *mmio = &nfit_blk->mmio[DCR]; | |
1398 | u64 offset = nfit_blk->stat_offset + mmio->size * bw; | |
1399 | ||
1400 | if (mmio->num_lines) | |
1401 | offset = to_interleave_offset(offset, mmio); | |
1402 | ||
12f03ee6 | 1403 | return readl(mmio->addr.base + offset); |
047fc8a1 RZ |
1404 | } |
1405 | ||
1406 | static void write_blk_ctl(struct nfit_blk *nfit_blk, unsigned int bw, | |
1407 | resource_size_t dpa, unsigned int len, unsigned int write) | |
1408 | { | |
1409 | u64 cmd, offset; | |
1410 | struct nfit_blk_mmio *mmio = &nfit_blk->mmio[DCR]; | |
1411 | ||
1412 | enum { | |
1413 | BCW_OFFSET_MASK = (1ULL << 48)-1, | |
1414 | BCW_LEN_SHIFT = 48, | |
1415 | BCW_LEN_MASK = (1ULL << 8) - 1, | |
1416 | BCW_CMD_SHIFT = 56, | |
1417 | }; | |
1418 | ||
1419 | cmd = (dpa >> L1_CACHE_SHIFT) & BCW_OFFSET_MASK; | |
1420 | len = len >> L1_CACHE_SHIFT; | |
1421 | cmd |= ((u64) len & BCW_LEN_MASK) << BCW_LEN_SHIFT; | |
1422 | cmd |= ((u64) write) << BCW_CMD_SHIFT; | |
1423 | ||
1424 | offset = nfit_blk->cmd_offset + mmio->size * bw; | |
1425 | if (mmio->num_lines) | |
1426 | offset = to_interleave_offset(offset, mmio); | |
1427 | ||
67a3e8fe | 1428 | writeq(cmd, mmio->addr.base + offset); |
c2ad2954 | 1429 | wmb_blk(nfit_blk); |
f0f2c072 | 1430 | |
aef25338 | 1431 | if (nfit_blk->dimm_flags & NFIT_BLK_DCR_LATCH) |
67a3e8fe | 1432 | readq(mmio->addr.base + offset); |
047fc8a1 RZ |
1433 | } |
1434 | ||
1435 | static int acpi_nfit_blk_single_io(struct nfit_blk *nfit_blk, | |
1436 | resource_size_t dpa, void *iobuf, size_t len, int rw, | |
1437 | unsigned int lane) | |
1438 | { | |
1439 | struct nfit_blk_mmio *mmio = &nfit_blk->mmio[BDW]; | |
1440 | unsigned int copied = 0; | |
1441 | u64 base_offset; | |
1442 | int rc; | |
1443 | ||
1444 | base_offset = nfit_blk->bdw_offset + dpa % L1_CACHE_BYTES | |
1445 | + lane * mmio->size; | |
047fc8a1 RZ |
1446 | write_blk_ctl(nfit_blk, lane, dpa, len, rw); |
1447 | while (len) { | |
1448 | unsigned int c; | |
1449 | u64 offset; | |
1450 | ||
1451 | if (mmio->num_lines) { | |
1452 | u32 line_offset; | |
1453 | ||
1454 | offset = to_interleave_offset(base_offset + copied, | |
1455 | mmio); | |
1456 | div_u64_rem(offset, mmio->line_size, &line_offset); | |
1457 | c = min_t(size_t, len, mmio->line_size - line_offset); | |
1458 | } else { | |
1459 | offset = base_offset + nfit_blk->bdw_offset; | |
1460 | c = len; | |
1461 | } | |
1462 | ||
1463 | if (rw) | |
67a3e8fe | 1464 | memcpy_to_pmem(mmio->addr.aperture + offset, |
c2ad2954 | 1465 | iobuf + copied, c); |
67a3e8fe | 1466 | else { |
aef25338 | 1467 | if (nfit_blk->dimm_flags & NFIT_BLK_READ_FLUSH) |
67a3e8fe RZ |
1468 | mmio_flush_range((void __force *) |
1469 | mmio->addr.aperture + offset, c); | |
1470 | ||
c2ad2954 | 1471 | memcpy_from_pmem(iobuf + copied, |
67a3e8fe RZ |
1472 | mmio->addr.aperture + offset, c); |
1473 | } | |
047fc8a1 RZ |
1474 | |
1475 | copied += c; | |
1476 | len -= c; | |
1477 | } | |
c2ad2954 RZ |
1478 | |
1479 | if (rw) | |
1480 | wmb_blk(nfit_blk); | |
1481 | ||
047fc8a1 RZ |
1482 | rc = read_blk_stat(nfit_blk, lane) ? -EIO : 0; |
1483 | return rc; | |
1484 | } | |
1485 | ||
1486 | static int acpi_nfit_blk_region_do_io(struct nd_blk_region *ndbr, | |
1487 | resource_size_t dpa, void *iobuf, u64 len, int rw) | |
1488 | { | |
1489 | struct nfit_blk *nfit_blk = nd_blk_region_provider_data(ndbr); | |
1490 | struct nfit_blk_mmio *mmio = &nfit_blk->mmio[BDW]; | |
1491 | struct nd_region *nd_region = nfit_blk->nd_region; | |
1492 | unsigned int lane, copied = 0; | |
1493 | int rc = 0; | |
1494 | ||
1495 | lane = nd_region_acquire_lane(nd_region); | |
1496 | while (len) { | |
1497 | u64 c = min(len, mmio->size); | |
1498 | ||
1499 | rc = acpi_nfit_blk_single_io(nfit_blk, dpa + copied, | |
1500 | iobuf + copied, c, rw, lane); | |
1501 | if (rc) | |
1502 | break; | |
1503 | ||
1504 | copied += c; | |
1505 | len -= c; | |
1506 | } | |
1507 | nd_region_release_lane(nd_region, lane); | |
1508 | ||
1509 | return rc; | |
1510 | } | |
1511 | ||
1512 | static void nfit_spa_mapping_release(struct kref *kref) | |
1513 | { | |
1514 | struct nfit_spa_mapping *spa_map = to_spa_map(kref); | |
1515 | struct acpi_nfit_system_address *spa = spa_map->spa; | |
1516 | struct acpi_nfit_desc *acpi_desc = spa_map->acpi_desc; | |
1517 | ||
1518 | WARN_ON(!mutex_is_locked(&acpi_desc->spa_map_mutex)); | |
1519 | dev_dbg(acpi_desc->dev, "%s: SPA%d\n", __func__, spa->range_index); | |
67a3e8fe RZ |
1520 | if (spa_map->type == SPA_MAP_APERTURE) |
1521 | memunmap((void __force *)spa_map->addr.aperture); | |
1522 | else | |
1523 | iounmap(spa_map->addr.base); | |
047fc8a1 RZ |
1524 | release_mem_region(spa->address, spa->length); |
1525 | list_del(&spa_map->list); | |
1526 | kfree(spa_map); | |
1527 | } | |
1528 | ||
1529 | static struct nfit_spa_mapping *find_spa_mapping( | |
1530 | struct acpi_nfit_desc *acpi_desc, | |
1531 | struct acpi_nfit_system_address *spa) | |
1532 | { | |
1533 | struct nfit_spa_mapping *spa_map; | |
1534 | ||
1535 | WARN_ON(!mutex_is_locked(&acpi_desc->spa_map_mutex)); | |
1536 | list_for_each_entry(spa_map, &acpi_desc->spa_maps, list) | |
1537 | if (spa_map->spa == spa) | |
1538 | return spa_map; | |
1539 | ||
1540 | return NULL; | |
1541 | } | |
1542 | ||
1543 | static void nfit_spa_unmap(struct acpi_nfit_desc *acpi_desc, | |
1544 | struct acpi_nfit_system_address *spa) | |
1545 | { | |
1546 | struct nfit_spa_mapping *spa_map; | |
1547 | ||
1548 | mutex_lock(&acpi_desc->spa_map_mutex); | |
1549 | spa_map = find_spa_mapping(acpi_desc, spa); | |
1550 | ||
1551 | if (spa_map) | |
1552 | kref_put(&spa_map->kref, nfit_spa_mapping_release); | |
1553 | mutex_unlock(&acpi_desc->spa_map_mutex); | |
1554 | } | |
1555 | ||
1556 | static void __iomem *__nfit_spa_map(struct acpi_nfit_desc *acpi_desc, | |
c2ad2954 | 1557 | struct acpi_nfit_system_address *spa, enum spa_map_type type) |
047fc8a1 RZ |
1558 | { |
1559 | resource_size_t start = spa->address; | |
1560 | resource_size_t n = spa->length; | |
1561 | struct nfit_spa_mapping *spa_map; | |
1562 | struct resource *res; | |
1563 | ||
1564 | WARN_ON(!mutex_is_locked(&acpi_desc->spa_map_mutex)); | |
1565 | ||
1566 | spa_map = find_spa_mapping(acpi_desc, spa); | |
1567 | if (spa_map) { | |
1568 | kref_get(&spa_map->kref); | |
67a3e8fe | 1569 | return spa_map->addr.base; |
047fc8a1 RZ |
1570 | } |
1571 | ||
1572 | spa_map = kzalloc(sizeof(*spa_map), GFP_KERNEL); | |
1573 | if (!spa_map) | |
1574 | return NULL; | |
1575 | ||
1576 | INIT_LIST_HEAD(&spa_map->list); | |
1577 | spa_map->spa = spa; | |
1578 | kref_init(&spa_map->kref); | |
1579 | spa_map->acpi_desc = acpi_desc; | |
1580 | ||
1581 | res = request_mem_region(start, n, dev_name(acpi_desc->dev)); | |
1582 | if (!res) | |
1583 | goto err_mem; | |
1584 | ||
67a3e8fe RZ |
1585 | spa_map->type = type; |
1586 | if (type == SPA_MAP_APERTURE) | |
1587 | spa_map->addr.aperture = (void __pmem *)memremap(start, n, | |
1588 | ARCH_MEMREMAP_PMEM); | |
1589 | else | |
1590 | spa_map->addr.base = ioremap_nocache(start, n); | |
1591 | ||
c2ad2954 | 1592 | |
67a3e8fe | 1593 | if (!spa_map->addr.base) |
047fc8a1 RZ |
1594 | goto err_map; |
1595 | ||
1596 | list_add_tail(&spa_map->list, &acpi_desc->spa_maps); | |
67a3e8fe | 1597 | return spa_map->addr.base; |
047fc8a1 RZ |
1598 | |
1599 | err_map: | |
1600 | release_mem_region(start, n); | |
1601 | err_mem: | |
1602 | kfree(spa_map); | |
1603 | return NULL; | |
1604 | } | |
1605 | ||
1606 | /** | |
1607 | * nfit_spa_map - interleave-aware managed-mappings of acpi_nfit_system_address ranges | |
1608 | * @nvdimm_bus: NFIT-bus that provided the spa table entry | |
1609 | * @nfit_spa: spa table to map | |
c2ad2954 | 1610 | * @type: aperture or control region |
047fc8a1 RZ |
1611 | * |
1612 | * In the case where block-data-window apertures and | |
1613 | * dimm-control-regions are interleaved they will end up sharing a | |
1614 | * single request_mem_region() + ioremap() for the address range. In | |
1615 | * the style of devm nfit_spa_map() mappings are automatically dropped | |
1616 | * when all region devices referencing the same mapping are disabled / | |
1617 | * unbound. | |
1618 | */ | |
1619 | static void __iomem *nfit_spa_map(struct acpi_nfit_desc *acpi_desc, | |
c2ad2954 | 1620 | struct acpi_nfit_system_address *spa, enum spa_map_type type) |
047fc8a1 RZ |
1621 | { |
1622 | void __iomem *iomem; | |
1623 | ||
1624 | mutex_lock(&acpi_desc->spa_map_mutex); | |
c2ad2954 | 1625 | iomem = __nfit_spa_map(acpi_desc, spa, type); |
047fc8a1 RZ |
1626 | mutex_unlock(&acpi_desc->spa_map_mutex); |
1627 | ||
1628 | return iomem; | |
1629 | } | |
1630 | ||
1631 | static int nfit_blk_init_interleave(struct nfit_blk_mmio *mmio, | |
1632 | struct acpi_nfit_interleave *idt, u16 interleave_ways) | |
1633 | { | |
1634 | if (idt) { | |
1635 | mmio->num_lines = idt->line_count; | |
1636 | mmio->line_size = idt->line_size; | |
1637 | if (interleave_ways == 0) | |
1638 | return -ENXIO; | |
1639 | mmio->table_size = mmio->num_lines * interleave_ways | |
1640 | * mmio->line_size; | |
1641 | } | |
1642 | ||
1643 | return 0; | |
1644 | } | |
1645 | ||
f0f2c072 RZ |
1646 | static int acpi_nfit_blk_get_flags(struct nvdimm_bus_descriptor *nd_desc, |
1647 | struct nvdimm *nvdimm, struct nfit_blk *nfit_blk) | |
1648 | { | |
1649 | struct nd_cmd_dimm_flags flags; | |
1650 | int rc; | |
1651 | ||
1652 | memset(&flags, 0, sizeof(flags)); | |
1653 | rc = nd_desc->ndctl(nd_desc, nvdimm, ND_CMD_DIMM_FLAGS, &flags, | |
aef25338 | 1654 | sizeof(flags), NULL); |
f0f2c072 RZ |
1655 | |
1656 | if (rc >= 0 && flags.status == 0) | |
1657 | nfit_blk->dimm_flags = flags.flags; | |
1658 | else if (rc == -ENOTTY) { | |
1659 | /* fall back to a conservative default */ | |
aef25338 | 1660 | nfit_blk->dimm_flags = NFIT_BLK_DCR_LATCH | NFIT_BLK_READ_FLUSH; |
f0f2c072 RZ |
1661 | rc = 0; |
1662 | } else | |
1663 | rc = -ENXIO; | |
1664 | ||
1665 | return rc; | |
1666 | } | |
1667 | ||
047fc8a1 RZ |
1668 | static int acpi_nfit_blk_region_enable(struct nvdimm_bus *nvdimm_bus, |
1669 | struct device *dev) | |
1670 | { | |
1671 | struct nvdimm_bus_descriptor *nd_desc = to_nd_desc(nvdimm_bus); | |
1672 | struct acpi_nfit_desc *acpi_desc = to_acpi_desc(nd_desc); | |
1673 | struct nd_blk_region *ndbr = to_nd_blk_region(dev); | |
c2ad2954 | 1674 | struct nfit_flush *nfit_flush; |
047fc8a1 RZ |
1675 | struct nfit_blk_mmio *mmio; |
1676 | struct nfit_blk *nfit_blk; | |
1677 | struct nfit_mem *nfit_mem; | |
1678 | struct nvdimm *nvdimm; | |
1679 | int rc; | |
1680 | ||
1681 | nvdimm = nd_blk_region_to_dimm(ndbr); | |
1682 | nfit_mem = nvdimm_provider_data(nvdimm); | |
1683 | if (!nfit_mem || !nfit_mem->dcr || !nfit_mem->bdw) { | |
1684 | dev_dbg(dev, "%s: missing%s%s%s\n", __func__, | |
1685 | nfit_mem ? "" : " nfit_mem", | |
193ccca4 DW |
1686 | (nfit_mem && nfit_mem->dcr) ? "" : " dcr", |
1687 | (nfit_mem && nfit_mem->bdw) ? "" : " bdw"); | |
047fc8a1 RZ |
1688 | return -ENXIO; |
1689 | } | |
1690 | ||
1691 | nfit_blk = devm_kzalloc(dev, sizeof(*nfit_blk), GFP_KERNEL); | |
1692 | if (!nfit_blk) | |
1693 | return -ENOMEM; | |
1694 | nd_blk_region_set_provider_data(ndbr, nfit_blk); | |
1695 | nfit_blk->nd_region = to_nd_region(dev); | |
1696 | ||
1697 | /* map block aperture memory */ | |
1698 | nfit_blk->bdw_offset = nfit_mem->bdw->offset; | |
1699 | mmio = &nfit_blk->mmio[BDW]; | |
67a3e8fe | 1700 | mmio->addr.base = nfit_spa_map(acpi_desc, nfit_mem->spa_bdw, |
c2ad2954 | 1701 | SPA_MAP_APERTURE); |
67a3e8fe | 1702 | if (!mmio->addr.base) { |
047fc8a1 RZ |
1703 | dev_dbg(dev, "%s: %s failed to map bdw\n", __func__, |
1704 | nvdimm_name(nvdimm)); | |
1705 | return -ENOMEM; | |
1706 | } | |
1707 | mmio->size = nfit_mem->bdw->size; | |
1708 | mmio->base_offset = nfit_mem->memdev_bdw->region_offset; | |
1709 | mmio->idt = nfit_mem->idt_bdw; | |
1710 | mmio->spa = nfit_mem->spa_bdw; | |
1711 | rc = nfit_blk_init_interleave(mmio, nfit_mem->idt_bdw, | |
1712 | nfit_mem->memdev_bdw->interleave_ways); | |
1713 | if (rc) { | |
1714 | dev_dbg(dev, "%s: %s failed to init bdw interleave\n", | |
1715 | __func__, nvdimm_name(nvdimm)); | |
1716 | return rc; | |
1717 | } | |
1718 | ||
1719 | /* map block control memory */ | |
1720 | nfit_blk->cmd_offset = nfit_mem->dcr->command_offset; | |
1721 | nfit_blk->stat_offset = nfit_mem->dcr->status_offset; | |
1722 | mmio = &nfit_blk->mmio[DCR]; | |
67a3e8fe | 1723 | mmio->addr.base = nfit_spa_map(acpi_desc, nfit_mem->spa_dcr, |
c2ad2954 | 1724 | SPA_MAP_CONTROL); |
67a3e8fe | 1725 | if (!mmio->addr.base) { |
047fc8a1 RZ |
1726 | dev_dbg(dev, "%s: %s failed to map dcr\n", __func__, |
1727 | nvdimm_name(nvdimm)); | |
1728 | return -ENOMEM; | |
1729 | } | |
1730 | mmio->size = nfit_mem->dcr->window_size; | |
1731 | mmio->base_offset = nfit_mem->memdev_dcr->region_offset; | |
1732 | mmio->idt = nfit_mem->idt_dcr; | |
1733 | mmio->spa = nfit_mem->spa_dcr; | |
1734 | rc = nfit_blk_init_interleave(mmio, nfit_mem->idt_dcr, | |
1735 | nfit_mem->memdev_dcr->interleave_ways); | |
1736 | if (rc) { | |
1737 | dev_dbg(dev, "%s: %s failed to init dcr interleave\n", | |
1738 | __func__, nvdimm_name(nvdimm)); | |
1739 | return rc; | |
1740 | } | |
1741 | ||
f0f2c072 RZ |
1742 | rc = acpi_nfit_blk_get_flags(nd_desc, nvdimm, nfit_blk); |
1743 | if (rc < 0) { | |
1744 | dev_dbg(dev, "%s: %s failed get DIMM flags\n", | |
1745 | __func__, nvdimm_name(nvdimm)); | |
1746 | return rc; | |
1747 | } | |
1748 | ||
c2ad2954 RZ |
1749 | nfit_flush = nfit_mem->nfit_flush; |
1750 | if (nfit_flush && nfit_flush->flush->hint_count != 0) { | |
1751 | nfit_blk->nvdimm_flush = devm_ioremap_nocache(dev, | |
1752 | nfit_flush->flush->hint_address[0], 8); | |
1753 | if (!nfit_blk->nvdimm_flush) | |
1754 | return -ENOMEM; | |
1755 | } | |
1756 | ||
96601adb | 1757 | if (!arch_has_wmb_pmem() && !nfit_blk->nvdimm_flush) |
c2ad2954 RZ |
1758 | dev_warn(dev, "unable to guarantee persistence of writes\n"); |
1759 | ||
047fc8a1 RZ |
1760 | if (mmio->line_size == 0) |
1761 | return 0; | |
1762 | ||
1763 | if ((u32) nfit_blk->cmd_offset % mmio->line_size | |
1764 | + 8 > mmio->line_size) { | |
1765 | dev_dbg(dev, "cmd_offset crosses interleave boundary\n"); | |
1766 | return -ENXIO; | |
1767 | } else if ((u32) nfit_blk->stat_offset % mmio->line_size | |
1768 | + 8 > mmio->line_size) { | |
1769 | dev_dbg(dev, "stat_offset crosses interleave boundary\n"); | |
1770 | return -ENXIO; | |
1771 | } | |
1772 | ||
1773 | return 0; | |
1774 | } | |
1775 | ||
1776 | static void acpi_nfit_blk_region_disable(struct nvdimm_bus *nvdimm_bus, | |
1777 | struct device *dev) | |
1778 | { | |
1779 | struct nvdimm_bus_descriptor *nd_desc = to_nd_desc(nvdimm_bus); | |
1780 | struct acpi_nfit_desc *acpi_desc = to_acpi_desc(nd_desc); | |
1781 | struct nd_blk_region *ndbr = to_nd_blk_region(dev); | |
1782 | struct nfit_blk *nfit_blk = nd_blk_region_provider_data(ndbr); | |
1783 | int i; | |
1784 | ||
1785 | if (!nfit_blk) | |
1786 | return; /* never enabled */ | |
1787 | ||
1788 | /* auto-free BLK spa mappings */ | |
1789 | for (i = 0; i < 2; i++) { | |
1790 | struct nfit_blk_mmio *mmio = &nfit_blk->mmio[i]; | |
1791 | ||
67a3e8fe | 1792 | if (mmio->addr.base) |
047fc8a1 RZ |
1793 | nfit_spa_unmap(acpi_desc, mmio->spa); |
1794 | } | |
1795 | nd_blk_region_set_provider_data(ndbr, NULL); | |
1796 | /* devm will free nfit_blk */ | |
1797 | } | |
1798 | ||
aef25338 | 1799 | static int ars_get_cap(struct acpi_nfit_desc *acpi_desc, |
1cf03c00 | 1800 | struct nd_cmd_ars_cap *cmd, struct nfit_spa *nfit_spa) |
0caeef63 | 1801 | { |
aef25338 | 1802 | struct nvdimm_bus_descriptor *nd_desc = &acpi_desc->nd_desc; |
1cf03c00 | 1803 | struct acpi_nfit_system_address *spa = nfit_spa->spa; |
aef25338 DW |
1804 | int cmd_rc, rc; |
1805 | ||
1cf03c00 DW |
1806 | cmd->address = spa->address; |
1807 | cmd->length = spa->length; | |
aef25338 DW |
1808 | rc = nd_desc->ndctl(nd_desc, NULL, ND_CMD_ARS_CAP, cmd, |
1809 | sizeof(*cmd), &cmd_rc); | |
1810 | if (rc < 0) | |
1811 | return rc; | |
1cf03c00 | 1812 | return cmd_rc; |
0caeef63 VV |
1813 | } |
1814 | ||
1cf03c00 | 1815 | static int ars_start(struct acpi_nfit_desc *acpi_desc, struct nfit_spa *nfit_spa) |
0caeef63 VV |
1816 | { |
1817 | int rc; | |
1cf03c00 DW |
1818 | int cmd_rc; |
1819 | struct nd_cmd_ars_start ars_start; | |
1820 | struct acpi_nfit_system_address *spa = nfit_spa->spa; | |
1821 | struct nvdimm_bus_descriptor *nd_desc = &acpi_desc->nd_desc; | |
0caeef63 | 1822 | |
1cf03c00 DW |
1823 | memset(&ars_start, 0, sizeof(ars_start)); |
1824 | ars_start.address = spa->address; | |
1825 | ars_start.length = spa->length; | |
1826 | if (nfit_spa_type(spa) == NFIT_SPA_PM) | |
1827 | ars_start.type = ND_ARS_PERSISTENT; | |
1828 | else if (nfit_spa_type(spa) == NFIT_SPA_VOLATILE) | |
1829 | ars_start.type = ND_ARS_VOLATILE; | |
1830 | else | |
1831 | return -ENOTTY; | |
aef25338 | 1832 | |
1cf03c00 DW |
1833 | rc = nd_desc->ndctl(nd_desc, NULL, ND_CMD_ARS_START, &ars_start, |
1834 | sizeof(ars_start), &cmd_rc); | |
aef25338 | 1835 | |
1cf03c00 DW |
1836 | if (rc < 0) |
1837 | return rc; | |
1838 | return cmd_rc; | |
0caeef63 VV |
1839 | } |
1840 | ||
1cf03c00 | 1841 | static int ars_continue(struct acpi_nfit_desc *acpi_desc) |
0caeef63 | 1842 | { |
aef25338 | 1843 | int rc, cmd_rc; |
1cf03c00 DW |
1844 | struct nd_cmd_ars_start ars_start; |
1845 | struct nvdimm_bus_descriptor *nd_desc = &acpi_desc->nd_desc; | |
1846 | struct nd_cmd_ars_status *ars_status = acpi_desc->ars_status; | |
1847 | ||
1848 | memset(&ars_start, 0, sizeof(ars_start)); | |
1849 | ars_start.address = ars_status->restart_address; | |
1850 | ars_start.length = ars_status->restart_length; | |
1851 | ars_start.type = ars_status->type; | |
1852 | rc = nd_desc->ndctl(nd_desc, NULL, ND_CMD_ARS_START, &ars_start, | |
1853 | sizeof(ars_start), &cmd_rc); | |
1854 | if (rc < 0) | |
1855 | return rc; | |
1856 | return cmd_rc; | |
1857 | } | |
0caeef63 | 1858 | |
1cf03c00 DW |
1859 | static int ars_get_status(struct acpi_nfit_desc *acpi_desc) |
1860 | { | |
1861 | struct nvdimm_bus_descriptor *nd_desc = &acpi_desc->nd_desc; | |
1862 | struct nd_cmd_ars_status *ars_status = acpi_desc->ars_status; | |
1863 | int rc, cmd_rc; | |
aef25338 | 1864 | |
1cf03c00 DW |
1865 | rc = nd_desc->ndctl(nd_desc, NULL, ND_CMD_ARS_STATUS, ars_status, |
1866 | acpi_desc->ars_status_size, &cmd_rc); | |
1867 | if (rc < 0) | |
1868 | return rc; | |
1869 | return cmd_rc; | |
0caeef63 VV |
1870 | } |
1871 | ||
1872 | static int ars_status_process_records(struct nvdimm_bus *nvdimm_bus, | |
1cf03c00 | 1873 | struct nd_cmd_ars_status *ars_status) |
0caeef63 VV |
1874 | { |
1875 | int rc; | |
1876 | u32 i; | |
1877 | ||
0caeef63 VV |
1878 | for (i = 0; i < ars_status->num_records; i++) { |
1879 | rc = nvdimm_bus_add_poison(nvdimm_bus, | |
1880 | ars_status->records[i].err_address, | |
1881 | ars_status->records[i].length); | |
1882 | if (rc) | |
1883 | return rc; | |
1884 | } | |
1885 | ||
1886 | return 0; | |
1887 | } | |
1888 | ||
af1996ef TK |
1889 | static void acpi_nfit_remove_resource(void *data) |
1890 | { | |
1891 | struct resource *res = data; | |
1892 | ||
1893 | remove_resource(res); | |
1894 | } | |
1895 | ||
1896 | static int acpi_nfit_insert_resource(struct acpi_nfit_desc *acpi_desc, | |
1897 | struct nd_region_desc *ndr_desc) | |
1898 | { | |
1899 | struct resource *res, *nd_res = ndr_desc->res; | |
1900 | int is_pmem, ret; | |
1901 | ||
1902 | /* No operation if the region is already registered as PMEM */ | |
1903 | is_pmem = region_intersects(nd_res->start, resource_size(nd_res), | |
1904 | IORESOURCE_MEM, IORES_DESC_PERSISTENT_MEMORY); | |
1905 | if (is_pmem == REGION_INTERSECTS) | |
1906 | return 0; | |
1907 | ||
1908 | res = devm_kzalloc(acpi_desc->dev, sizeof(*res), GFP_KERNEL); | |
1909 | if (!res) | |
1910 | return -ENOMEM; | |
1911 | ||
1912 | res->name = "Persistent Memory"; | |
1913 | res->start = nd_res->start; | |
1914 | res->end = nd_res->end; | |
1915 | res->flags = IORESOURCE_MEM; | |
1916 | res->desc = IORES_DESC_PERSISTENT_MEMORY; | |
1917 | ||
1918 | ret = insert_resource(&iomem_resource, res); | |
1919 | if (ret) | |
1920 | return ret; | |
1921 | ||
d932dd2c SV |
1922 | ret = devm_add_action_or_reset(acpi_desc->dev, |
1923 | acpi_nfit_remove_resource, | |
1924 | res); | |
1925 | if (ret) | |
af1996ef | 1926 | return ret; |
af1996ef TK |
1927 | |
1928 | return 0; | |
1929 | } | |
1930 | ||
1f7df6f8 DW |
1931 | static int acpi_nfit_init_mapping(struct acpi_nfit_desc *acpi_desc, |
1932 | struct nd_mapping *nd_mapping, struct nd_region_desc *ndr_desc, | |
1933 | struct acpi_nfit_memory_map *memdev, | |
1cf03c00 | 1934 | struct nfit_spa *nfit_spa) |
1f7df6f8 DW |
1935 | { |
1936 | struct nvdimm *nvdimm = acpi_nfit_dimm_by_handle(acpi_desc, | |
1937 | memdev->device_handle); | |
1cf03c00 | 1938 | struct acpi_nfit_system_address *spa = nfit_spa->spa; |
047fc8a1 | 1939 | struct nd_blk_region_desc *ndbr_desc; |
1f7df6f8 DW |
1940 | struct nfit_mem *nfit_mem; |
1941 | int blk_valid = 0; | |
1942 | ||
1943 | if (!nvdimm) { | |
1944 | dev_err(acpi_desc->dev, "spa%d dimm: %#x not found\n", | |
1945 | spa->range_index, memdev->device_handle); | |
1946 | return -ENODEV; | |
1947 | } | |
1948 | ||
1949 | nd_mapping->nvdimm = nvdimm; | |
1950 | switch (nfit_spa_type(spa)) { | |
1951 | case NFIT_SPA_PM: | |
1952 | case NFIT_SPA_VOLATILE: | |
1953 | nd_mapping->start = memdev->address; | |
1954 | nd_mapping->size = memdev->region_size; | |
1955 | break; | |
1956 | case NFIT_SPA_DCR: | |
1957 | nfit_mem = nvdimm_provider_data(nvdimm); | |
1958 | if (!nfit_mem || !nfit_mem->bdw) { | |
1959 | dev_dbg(acpi_desc->dev, "spa%d %s missing bdw\n", | |
1960 | spa->range_index, nvdimm_name(nvdimm)); | |
1961 | } else { | |
1962 | nd_mapping->size = nfit_mem->bdw->capacity; | |
1963 | nd_mapping->start = nfit_mem->bdw->start_address; | |
5212e11f | 1964 | ndr_desc->num_lanes = nfit_mem->bdw->windows; |
1f7df6f8 DW |
1965 | blk_valid = 1; |
1966 | } | |
1967 | ||
1968 | ndr_desc->nd_mapping = nd_mapping; | |
1969 | ndr_desc->num_mappings = blk_valid; | |
047fc8a1 RZ |
1970 | ndbr_desc = to_blk_region_desc(ndr_desc); |
1971 | ndbr_desc->enable = acpi_nfit_blk_region_enable; | |
1972 | ndbr_desc->disable = acpi_nfit_blk_region_disable; | |
6bc75619 | 1973 | ndbr_desc->do_io = acpi_desc->blk_do_io; |
1cf03c00 DW |
1974 | nfit_spa->nd_region = nvdimm_blk_region_create(acpi_desc->nvdimm_bus, |
1975 | ndr_desc); | |
1976 | if (!nfit_spa->nd_region) | |
1f7df6f8 DW |
1977 | return -ENOMEM; |
1978 | break; | |
1979 | } | |
1980 | ||
1981 | return 0; | |
1982 | } | |
1983 | ||
1984 | static int acpi_nfit_register_region(struct acpi_nfit_desc *acpi_desc, | |
1985 | struct nfit_spa *nfit_spa) | |
1986 | { | |
1987 | static struct nd_mapping nd_mappings[ND_MAX_MAPPINGS]; | |
1988 | struct acpi_nfit_system_address *spa = nfit_spa->spa; | |
047fc8a1 RZ |
1989 | struct nd_blk_region_desc ndbr_desc; |
1990 | struct nd_region_desc *ndr_desc; | |
1f7df6f8 | 1991 | struct nfit_memdev *nfit_memdev; |
1f7df6f8 DW |
1992 | struct nvdimm_bus *nvdimm_bus; |
1993 | struct resource res; | |
eaf96153 | 1994 | int count = 0, rc; |
1f7df6f8 | 1995 | |
1cf03c00 | 1996 | if (nfit_spa->nd_region) |
20985164 VV |
1997 | return 0; |
1998 | ||
1f7df6f8 DW |
1999 | if (spa->range_index == 0) { |
2000 | dev_dbg(acpi_desc->dev, "%s: detected invalid spa index\n", | |
2001 | __func__); | |
2002 | return 0; | |
2003 | } | |
2004 | ||
2005 | memset(&res, 0, sizeof(res)); | |
2006 | memset(&nd_mappings, 0, sizeof(nd_mappings)); | |
047fc8a1 | 2007 | memset(&ndbr_desc, 0, sizeof(ndbr_desc)); |
1f7df6f8 DW |
2008 | res.start = spa->address; |
2009 | res.end = res.start + spa->length - 1; | |
047fc8a1 RZ |
2010 | ndr_desc = &ndbr_desc.ndr_desc; |
2011 | ndr_desc->res = &res; | |
2012 | ndr_desc->provider_data = nfit_spa; | |
2013 | ndr_desc->attr_groups = acpi_nfit_region_attribute_groups; | |
41d7a6d6 TK |
2014 | if (spa->flags & ACPI_NFIT_PROXIMITY_VALID) |
2015 | ndr_desc->numa_node = acpi_map_pxm_to_online_node( | |
2016 | spa->proximity_domain); | |
2017 | else | |
2018 | ndr_desc->numa_node = NUMA_NO_NODE; | |
2019 | ||
1f7df6f8 DW |
2020 | list_for_each_entry(nfit_memdev, &acpi_desc->memdevs, list) { |
2021 | struct acpi_nfit_memory_map *memdev = nfit_memdev->memdev; | |
2022 | struct nd_mapping *nd_mapping; | |
1f7df6f8 DW |
2023 | |
2024 | if (memdev->range_index != spa->range_index) | |
2025 | continue; | |
2026 | if (count >= ND_MAX_MAPPINGS) { | |
2027 | dev_err(acpi_desc->dev, "spa%d exceeds max mappings %d\n", | |
2028 | spa->range_index, ND_MAX_MAPPINGS); | |
2029 | return -ENXIO; | |
2030 | } | |
2031 | nd_mapping = &nd_mappings[count++]; | |
047fc8a1 | 2032 | rc = acpi_nfit_init_mapping(acpi_desc, nd_mapping, ndr_desc, |
1cf03c00 | 2033 | memdev, nfit_spa); |
1f7df6f8 | 2034 | if (rc) |
1cf03c00 | 2035 | goto out; |
1f7df6f8 DW |
2036 | } |
2037 | ||
047fc8a1 RZ |
2038 | ndr_desc->nd_mapping = nd_mappings; |
2039 | ndr_desc->num_mappings = count; | |
2040 | rc = acpi_nfit_init_interleave_set(acpi_desc, ndr_desc, spa); | |
eaf96153 | 2041 | if (rc) |
1cf03c00 | 2042 | goto out; |
eaf96153 | 2043 | |
1f7df6f8 DW |
2044 | nvdimm_bus = acpi_desc->nvdimm_bus; |
2045 | if (nfit_spa_type(spa) == NFIT_SPA_PM) { | |
af1996ef | 2046 | rc = acpi_nfit_insert_resource(acpi_desc, ndr_desc); |
48901165 | 2047 | if (rc) { |
af1996ef TK |
2048 | dev_warn(acpi_desc->dev, |
2049 | "failed to insert pmem resource to iomem: %d\n", | |
2050 | rc); | |
48901165 | 2051 | goto out; |
0caeef63 | 2052 | } |
48901165 | 2053 | |
1cf03c00 DW |
2054 | nfit_spa->nd_region = nvdimm_pmem_region_create(nvdimm_bus, |
2055 | ndr_desc); | |
2056 | if (!nfit_spa->nd_region) | |
2057 | rc = -ENOMEM; | |
1f7df6f8 | 2058 | } else if (nfit_spa_type(spa) == NFIT_SPA_VOLATILE) { |
1cf03c00 DW |
2059 | nfit_spa->nd_region = nvdimm_volatile_region_create(nvdimm_bus, |
2060 | ndr_desc); | |
2061 | if (!nfit_spa->nd_region) | |
2062 | rc = -ENOMEM; | |
1f7df6f8 | 2063 | } |
20985164 | 2064 | |
1cf03c00 DW |
2065 | out: |
2066 | if (rc) | |
2067 | dev_err(acpi_desc->dev, "failed to register spa range %d\n", | |
2068 | nfit_spa->spa->range_index); | |
2069 | return rc; | |
2070 | } | |
2071 | ||
2072 | static int ars_status_alloc(struct acpi_nfit_desc *acpi_desc, | |
2073 | u32 max_ars) | |
2074 | { | |
2075 | struct device *dev = acpi_desc->dev; | |
2076 | struct nd_cmd_ars_status *ars_status; | |
2077 | ||
2078 | if (acpi_desc->ars_status && acpi_desc->ars_status_size >= max_ars) { | |
2079 | memset(acpi_desc->ars_status, 0, acpi_desc->ars_status_size); | |
2080 | return 0; | |
2081 | } | |
2082 | ||
2083 | if (acpi_desc->ars_status) | |
2084 | devm_kfree(dev, acpi_desc->ars_status); | |
2085 | acpi_desc->ars_status = NULL; | |
2086 | ars_status = devm_kzalloc(dev, max_ars, GFP_KERNEL); | |
2087 | if (!ars_status) | |
2088 | return -ENOMEM; | |
2089 | acpi_desc->ars_status = ars_status; | |
2090 | acpi_desc->ars_status_size = max_ars; | |
1f7df6f8 DW |
2091 | return 0; |
2092 | } | |
2093 | ||
1cf03c00 DW |
2094 | static int acpi_nfit_query_poison(struct acpi_nfit_desc *acpi_desc, |
2095 | struct nfit_spa *nfit_spa) | |
2096 | { | |
2097 | struct acpi_nfit_system_address *spa = nfit_spa->spa; | |
2098 | int rc; | |
2099 | ||
2100 | if (!nfit_spa->max_ars) { | |
2101 | struct nd_cmd_ars_cap ars_cap; | |
2102 | ||
2103 | memset(&ars_cap, 0, sizeof(ars_cap)); | |
2104 | rc = ars_get_cap(acpi_desc, &ars_cap, nfit_spa); | |
2105 | if (rc < 0) | |
2106 | return rc; | |
2107 | nfit_spa->max_ars = ars_cap.max_ars_out; | |
2108 | nfit_spa->clear_err_unit = ars_cap.clear_err_unit; | |
2109 | /* check that the supported scrub types match the spa type */ | |
2110 | if (nfit_spa_type(spa) == NFIT_SPA_VOLATILE && | |
2111 | ((ars_cap.status >> 16) & ND_ARS_VOLATILE) == 0) | |
2112 | return -ENOTTY; | |
2113 | else if (nfit_spa_type(spa) == NFIT_SPA_PM && | |
2114 | ((ars_cap.status >> 16) & ND_ARS_PERSISTENT) == 0) | |
2115 | return -ENOTTY; | |
2116 | } | |
2117 | ||
2118 | if (ars_status_alloc(acpi_desc, nfit_spa->max_ars)) | |
2119 | return -ENOMEM; | |
2120 | ||
2121 | rc = ars_get_status(acpi_desc); | |
2122 | if (rc < 0 && rc != -ENOSPC) | |
2123 | return rc; | |
2124 | ||
2125 | if (ars_status_process_records(acpi_desc->nvdimm_bus, | |
2126 | acpi_desc->ars_status)) | |
2127 | return -ENOMEM; | |
2128 | ||
2129 | return 0; | |
2130 | } | |
2131 | ||
2132 | static void acpi_nfit_async_scrub(struct acpi_nfit_desc *acpi_desc, | |
2133 | struct nfit_spa *nfit_spa) | |
2134 | { | |
2135 | struct acpi_nfit_system_address *spa = nfit_spa->spa; | |
2136 | unsigned int overflow_retry = scrub_overflow_abort; | |
2137 | u64 init_ars_start = 0, init_ars_len = 0; | |
2138 | struct device *dev = acpi_desc->dev; | |
2139 | unsigned int tmo = scrub_timeout; | |
2140 | int rc; | |
2141 | ||
2142 | if (nfit_spa->ars_done || !nfit_spa->nd_region) | |
2143 | return; | |
2144 | ||
2145 | rc = ars_start(acpi_desc, nfit_spa); | |
2146 | /* | |
2147 | * If we timed out the initial scan we'll still be busy here, | |
2148 | * and will wait another timeout before giving up permanently. | |
2149 | */ | |
2150 | if (rc < 0 && rc != -EBUSY) | |
2151 | return; | |
2152 | ||
2153 | do { | |
2154 | u64 ars_start, ars_len; | |
2155 | ||
2156 | if (acpi_desc->cancel) | |
2157 | break; | |
2158 | rc = acpi_nfit_query_poison(acpi_desc, nfit_spa); | |
2159 | if (rc == -ENOTTY) | |
2160 | break; | |
2161 | if (rc == -EBUSY && !tmo) { | |
2162 | dev_warn(dev, "range %d ars timeout, aborting\n", | |
2163 | spa->range_index); | |
2164 | break; | |
2165 | } | |
2166 | ||
2167 | if (rc == -EBUSY) { | |
2168 | /* | |
2169 | * Note, entries may be appended to the list | |
2170 | * while the lock is dropped, but the workqueue | |
2171 | * being active prevents entries being deleted / | |
2172 | * freed. | |
2173 | */ | |
2174 | mutex_unlock(&acpi_desc->init_mutex); | |
2175 | ssleep(1); | |
2176 | tmo--; | |
2177 | mutex_lock(&acpi_desc->init_mutex); | |
2178 | continue; | |
2179 | } | |
2180 | ||
2181 | /* we got some results, but there are more pending... */ | |
2182 | if (rc == -ENOSPC && overflow_retry--) { | |
2183 | if (!init_ars_len) { | |
2184 | init_ars_len = acpi_desc->ars_status->length; | |
2185 | init_ars_start = acpi_desc->ars_status->address; | |
2186 | } | |
2187 | rc = ars_continue(acpi_desc); | |
2188 | } | |
2189 | ||
2190 | if (rc < 0) { | |
2191 | dev_warn(dev, "range %d ars continuation failed\n", | |
2192 | spa->range_index); | |
2193 | break; | |
2194 | } | |
2195 | ||
2196 | if (init_ars_len) { | |
2197 | ars_start = init_ars_start; | |
2198 | ars_len = init_ars_len; | |
2199 | } else { | |
2200 | ars_start = acpi_desc->ars_status->address; | |
2201 | ars_len = acpi_desc->ars_status->length; | |
2202 | } | |
2203 | dev_dbg(dev, "spa range: %d ars from %#llx + %#llx complete\n", | |
2204 | spa->range_index, ars_start, ars_len); | |
2205 | /* notify the region about new poison entries */ | |
2206 | nvdimm_region_notify(nfit_spa->nd_region, | |
2207 | NVDIMM_REVALIDATE_POISON); | |
2208 | break; | |
2209 | } while (1); | |
2210 | } | |
2211 | ||
2212 | static void acpi_nfit_scrub(struct work_struct *work) | |
1f7df6f8 | 2213 | { |
1cf03c00 DW |
2214 | struct device *dev; |
2215 | u64 init_scrub_length = 0; | |
1f7df6f8 | 2216 | struct nfit_spa *nfit_spa; |
1cf03c00 DW |
2217 | u64 init_scrub_address = 0; |
2218 | bool init_ars_done = false; | |
2219 | struct acpi_nfit_desc *acpi_desc; | |
2220 | unsigned int tmo = scrub_timeout; | |
2221 | unsigned int overflow_retry = scrub_overflow_abort; | |
2222 | ||
2223 | acpi_desc = container_of(work, typeof(*acpi_desc), work); | |
2224 | dev = acpi_desc->dev; | |
1f7df6f8 | 2225 | |
1cf03c00 DW |
2226 | /* |
2227 | * We scrub in 2 phases. The first phase waits for any platform | |
2228 | * firmware initiated scrubs to complete and then we go search for the | |
2229 | * affected spa regions to mark them scanned. In the second phase we | |
2230 | * initiate a directed scrub for every range that was not scrubbed in | |
2231 | * phase 1. | |
2232 | */ | |
2233 | ||
2234 | /* process platform firmware initiated scrubs */ | |
2235 | retry: | |
2236 | mutex_lock(&acpi_desc->init_mutex); | |
1f7df6f8 | 2237 | list_for_each_entry(nfit_spa, &acpi_desc->spas, list) { |
1cf03c00 DW |
2238 | struct nd_cmd_ars_status *ars_status; |
2239 | struct acpi_nfit_system_address *spa; | |
2240 | u64 ars_start, ars_len; | |
2241 | int rc; | |
1f7df6f8 | 2242 | |
1cf03c00 DW |
2243 | if (acpi_desc->cancel) |
2244 | break; | |
2245 | ||
2246 | if (nfit_spa->nd_region) | |
2247 | continue; | |
2248 | ||
2249 | if (init_ars_done) { | |
2250 | /* | |
2251 | * No need to re-query, we're now just | |
2252 | * reconciling all the ranges covered by the | |
2253 | * initial scrub | |
2254 | */ | |
2255 | rc = 0; | |
2256 | } else | |
2257 | rc = acpi_nfit_query_poison(acpi_desc, nfit_spa); | |
2258 | ||
2259 | if (rc == -ENOTTY) { | |
2260 | /* no ars capability, just register spa and move on */ | |
2261 | acpi_nfit_register_region(acpi_desc, nfit_spa); | |
2262 | continue; | |
2263 | } | |
2264 | ||
2265 | if (rc == -EBUSY && !tmo) { | |
2266 | /* fallthrough to directed scrub in phase 2 */ | |
2267 | dev_warn(dev, "timeout awaiting ars results, continuing...\n"); | |
2268 | break; | |
2269 | } else if (rc == -EBUSY) { | |
2270 | mutex_unlock(&acpi_desc->init_mutex); | |
2271 | ssleep(1); | |
2272 | tmo--; | |
2273 | goto retry; | |
2274 | } | |
2275 | ||
2276 | /* we got some results, but there are more pending... */ | |
2277 | if (rc == -ENOSPC && overflow_retry--) { | |
2278 | ars_status = acpi_desc->ars_status; | |
2279 | /* | |
2280 | * Record the original scrub range, so that we | |
2281 | * can recall all the ranges impacted by the | |
2282 | * initial scrub. | |
2283 | */ | |
2284 | if (!init_scrub_length) { | |
2285 | init_scrub_length = ars_status->length; | |
2286 | init_scrub_address = ars_status->address; | |
2287 | } | |
2288 | rc = ars_continue(acpi_desc); | |
2289 | if (rc == 0) { | |
2290 | mutex_unlock(&acpi_desc->init_mutex); | |
2291 | goto retry; | |
2292 | } | |
2293 | } | |
2294 | ||
2295 | if (rc < 0) { | |
2296 | /* | |
2297 | * Initial scrub failed, we'll give it one more | |
2298 | * try below... | |
2299 | */ | |
2300 | break; | |
2301 | } | |
2302 | ||
2303 | /* We got some final results, record completed ranges */ | |
2304 | ars_status = acpi_desc->ars_status; | |
2305 | if (init_scrub_length) { | |
2306 | ars_start = init_scrub_address; | |
2307 | ars_len = ars_start + init_scrub_length; | |
2308 | } else { | |
2309 | ars_start = ars_status->address; | |
2310 | ars_len = ars_status->length; | |
2311 | } | |
2312 | spa = nfit_spa->spa; | |
2313 | ||
2314 | if (!init_ars_done) { | |
2315 | init_ars_done = true; | |
2316 | dev_dbg(dev, "init scrub %#llx + %#llx complete\n", | |
2317 | ars_start, ars_len); | |
2318 | } | |
2319 | if (ars_start <= spa->address && ars_start + ars_len | |
2320 | >= spa->address + spa->length) | |
2321 | acpi_nfit_register_region(acpi_desc, nfit_spa); | |
1f7df6f8 | 2322 | } |
1cf03c00 DW |
2323 | |
2324 | /* | |
2325 | * For all the ranges not covered by an initial scrub we still | |
2326 | * want to see if there are errors, but it's ok to discover them | |
2327 | * asynchronously. | |
2328 | */ | |
2329 | list_for_each_entry(nfit_spa, &acpi_desc->spas, list) { | |
2330 | /* | |
2331 | * Flag all the ranges that still need scrubbing, but | |
2332 | * register them now to make data available. | |
2333 | */ | |
2334 | if (nfit_spa->nd_region) | |
2335 | nfit_spa->ars_done = 1; | |
2336 | else | |
2337 | acpi_nfit_register_region(acpi_desc, nfit_spa); | |
2338 | } | |
2339 | ||
2340 | list_for_each_entry(nfit_spa, &acpi_desc->spas, list) | |
2341 | acpi_nfit_async_scrub(acpi_desc, nfit_spa); | |
2342 | mutex_unlock(&acpi_desc->init_mutex); | |
2343 | } | |
2344 | ||
2345 | static int acpi_nfit_register_regions(struct acpi_nfit_desc *acpi_desc) | |
2346 | { | |
2347 | struct nfit_spa *nfit_spa; | |
2348 | int rc; | |
2349 | ||
2350 | list_for_each_entry(nfit_spa, &acpi_desc->spas, list) | |
2351 | if (nfit_spa_type(nfit_spa->spa) == NFIT_SPA_DCR) { | |
2352 | /* BLK regions don't need to wait for ars results */ | |
2353 | rc = acpi_nfit_register_region(acpi_desc, nfit_spa); | |
2354 | if (rc) | |
2355 | return rc; | |
2356 | } | |
2357 | ||
2358 | queue_work(nfit_wq, &acpi_desc->work); | |
1f7df6f8 DW |
2359 | return 0; |
2360 | } | |
2361 | ||
20985164 VV |
2362 | static int acpi_nfit_check_deletions(struct acpi_nfit_desc *acpi_desc, |
2363 | struct nfit_table_prev *prev) | |
2364 | { | |
2365 | struct device *dev = acpi_desc->dev; | |
2366 | ||
2367 | if (!list_empty(&prev->spas) || | |
2368 | !list_empty(&prev->memdevs) || | |
2369 | !list_empty(&prev->dcrs) || | |
2370 | !list_empty(&prev->bdws) || | |
2371 | !list_empty(&prev->idts) || | |
2372 | !list_empty(&prev->flushes)) { | |
2373 | dev_err(dev, "new nfit deletes entries (unsupported)\n"); | |
2374 | return -ENXIO; | |
2375 | } | |
2376 | return 0; | |
2377 | } | |
2378 | ||
6bc75619 | 2379 | int acpi_nfit_init(struct acpi_nfit_desc *acpi_desc, acpi_size sz) |
b94d5230 DW |
2380 | { |
2381 | struct device *dev = acpi_desc->dev; | |
20985164 | 2382 | struct nfit_table_prev prev; |
b94d5230 DW |
2383 | const void *end; |
2384 | u8 *data; | |
1f7df6f8 | 2385 | int rc; |
b94d5230 | 2386 | |
20985164 VV |
2387 | mutex_lock(&acpi_desc->init_mutex); |
2388 | ||
2389 | INIT_LIST_HEAD(&prev.spas); | |
2390 | INIT_LIST_HEAD(&prev.memdevs); | |
2391 | INIT_LIST_HEAD(&prev.dcrs); | |
2392 | INIT_LIST_HEAD(&prev.bdws); | |
2393 | INIT_LIST_HEAD(&prev.idts); | |
2394 | INIT_LIST_HEAD(&prev.flushes); | |
2395 | ||
2396 | list_cut_position(&prev.spas, &acpi_desc->spas, | |
2397 | acpi_desc->spas.prev); | |
2398 | list_cut_position(&prev.memdevs, &acpi_desc->memdevs, | |
2399 | acpi_desc->memdevs.prev); | |
2400 | list_cut_position(&prev.dcrs, &acpi_desc->dcrs, | |
2401 | acpi_desc->dcrs.prev); | |
2402 | list_cut_position(&prev.bdws, &acpi_desc->bdws, | |
2403 | acpi_desc->bdws.prev); | |
2404 | list_cut_position(&prev.idts, &acpi_desc->idts, | |
2405 | acpi_desc->idts.prev); | |
2406 | list_cut_position(&prev.flushes, &acpi_desc->flushes, | |
2407 | acpi_desc->flushes.prev); | |
b94d5230 DW |
2408 | |
2409 | data = (u8 *) acpi_desc->nfit; | |
2410 | end = data + sz; | |
b94d5230 | 2411 | while (!IS_ERR_OR_NULL(data)) |
20985164 | 2412 | data = add_table(acpi_desc, &prev, data, end); |
b94d5230 DW |
2413 | |
2414 | if (IS_ERR(data)) { | |
2415 | dev_dbg(dev, "%s: nfit table parsing error: %ld\n", __func__, | |
2416 | PTR_ERR(data)); | |
20985164 VV |
2417 | rc = PTR_ERR(data); |
2418 | goto out_unlock; | |
b94d5230 DW |
2419 | } |
2420 | ||
20985164 VV |
2421 | rc = acpi_nfit_check_deletions(acpi_desc, &prev); |
2422 | if (rc) | |
2423 | goto out_unlock; | |
2424 | ||
81ed4e36 DW |
2425 | rc = nfit_mem_init(acpi_desc); |
2426 | if (rc) | |
20985164 | 2427 | goto out_unlock; |
b94d5230 | 2428 | |
62232e45 DW |
2429 | acpi_nfit_init_dsms(acpi_desc); |
2430 | ||
1f7df6f8 DW |
2431 | rc = acpi_nfit_register_dimms(acpi_desc); |
2432 | if (rc) | |
20985164 VV |
2433 | goto out_unlock; |
2434 | ||
2435 | rc = acpi_nfit_register_regions(acpi_desc); | |
1f7df6f8 | 2436 | |
20985164 VV |
2437 | out_unlock: |
2438 | mutex_unlock(&acpi_desc->init_mutex); | |
2439 | return rc; | |
b94d5230 | 2440 | } |
6bc75619 | 2441 | EXPORT_SYMBOL_GPL(acpi_nfit_init); |
b94d5230 | 2442 | |
7ae0fa43 DW |
2443 | struct acpi_nfit_flush_work { |
2444 | struct work_struct work; | |
2445 | struct completion cmp; | |
2446 | }; | |
2447 | ||
2448 | static void flush_probe(struct work_struct *work) | |
2449 | { | |
2450 | struct acpi_nfit_flush_work *flush; | |
2451 | ||
2452 | flush = container_of(work, typeof(*flush), work); | |
2453 | complete(&flush->cmp); | |
2454 | } | |
2455 | ||
2456 | static int acpi_nfit_flush_probe(struct nvdimm_bus_descriptor *nd_desc) | |
2457 | { | |
2458 | struct acpi_nfit_desc *acpi_desc = to_acpi_nfit_desc(nd_desc); | |
2459 | struct device *dev = acpi_desc->dev; | |
2460 | struct acpi_nfit_flush_work flush; | |
2461 | ||
2462 | /* bounce the device lock to flush acpi_nfit_add / acpi_nfit_notify */ | |
2463 | device_lock(dev); | |
2464 | device_unlock(dev); | |
2465 | ||
2466 | /* | |
2467 | * Scrub work could take 10s of seconds, userspace may give up so we | |
2468 | * need to be interruptible while waiting. | |
2469 | */ | |
2470 | INIT_WORK_ONSTACK(&flush.work, flush_probe); | |
2471 | COMPLETION_INITIALIZER_ONSTACK(flush.cmp); | |
2472 | queue_work(nfit_wq, &flush.work); | |
2473 | return wait_for_completion_interruptible(&flush.cmp); | |
2474 | } | |
2475 | ||
87bf572e DW |
2476 | static int acpi_nfit_clear_to_send(struct nvdimm_bus_descriptor *nd_desc, |
2477 | struct nvdimm *nvdimm, unsigned int cmd) | |
2478 | { | |
2479 | struct acpi_nfit_desc *acpi_desc = to_acpi_nfit_desc(nd_desc); | |
2480 | ||
2481 | if (nvdimm) | |
2482 | return 0; | |
2483 | if (cmd != ND_CMD_ARS_START) | |
2484 | return 0; | |
2485 | ||
2486 | /* | |
2487 | * The kernel and userspace may race to initiate a scrub, but | |
2488 | * the scrub thread is prepared to lose that initial race. It | |
2489 | * just needs guarantees that any ars it initiates are not | |
2490 | * interrupted by any intervening start reqeusts from userspace. | |
2491 | */ | |
2492 | if (work_busy(&acpi_desc->work)) | |
2493 | return -EBUSY; | |
2494 | ||
2495 | return 0; | |
2496 | } | |
2497 | ||
a61fe6f7 | 2498 | void acpi_nfit_desc_init(struct acpi_nfit_desc *acpi_desc, struct device *dev) |
b94d5230 DW |
2499 | { |
2500 | struct nvdimm_bus_descriptor *nd_desc; | |
b94d5230 DW |
2501 | |
2502 | dev_set_drvdata(dev, acpi_desc); | |
2503 | acpi_desc->dev = dev; | |
6bc75619 | 2504 | acpi_desc->blk_do_io = acpi_nfit_blk_region_do_io; |
b94d5230 DW |
2505 | nd_desc = &acpi_desc->nd_desc; |
2506 | nd_desc->provider_name = "ACPI.NFIT"; | |
2507 | nd_desc->ndctl = acpi_nfit_ctl; | |
7ae0fa43 | 2508 | nd_desc->flush_probe = acpi_nfit_flush_probe; |
87bf572e | 2509 | nd_desc->clear_to_send = acpi_nfit_clear_to_send; |
45def22c | 2510 | nd_desc->attr_groups = acpi_nfit_attribute_groups; |
b94d5230 | 2511 | |
20985164 VV |
2512 | INIT_LIST_HEAD(&acpi_desc->spa_maps); |
2513 | INIT_LIST_HEAD(&acpi_desc->spas); | |
2514 | INIT_LIST_HEAD(&acpi_desc->dcrs); | |
2515 | INIT_LIST_HEAD(&acpi_desc->bdws); | |
2516 | INIT_LIST_HEAD(&acpi_desc->idts); | |
2517 | INIT_LIST_HEAD(&acpi_desc->flushes); | |
2518 | INIT_LIST_HEAD(&acpi_desc->memdevs); | |
2519 | INIT_LIST_HEAD(&acpi_desc->dimms); | |
2520 | mutex_init(&acpi_desc->spa_map_mutex); | |
2521 | mutex_init(&acpi_desc->init_mutex); | |
1cf03c00 | 2522 | INIT_WORK(&acpi_desc->work, acpi_nfit_scrub); |
20985164 | 2523 | } |
a61fe6f7 | 2524 | EXPORT_SYMBOL_GPL(acpi_nfit_desc_init); |
20985164 VV |
2525 | |
2526 | static int acpi_nfit_add(struct acpi_device *adev) | |
2527 | { | |
2528 | struct acpi_buffer buf = { ACPI_ALLOCATE_BUFFER, NULL }; | |
2529 | struct acpi_nfit_desc *acpi_desc; | |
2530 | struct device *dev = &adev->dev; | |
2531 | struct acpi_table_header *tbl; | |
2532 | acpi_status status = AE_OK; | |
2533 | acpi_size sz; | |
2534 | int rc; | |
2535 | ||
82595423 | 2536 | status = acpi_get_table_with_size(ACPI_SIG_NFIT, 0, &tbl, &sz); |
20985164 VV |
2537 | if (ACPI_FAILURE(status)) { |
2538 | /* This is ok, we could have an nvdimm hotplugged later */ | |
2539 | dev_dbg(dev, "failed to find NFIT at startup\n"); | |
2540 | return 0; | |
2541 | } | |
2542 | ||
a61fe6f7 DW |
2543 | acpi_desc = devm_kzalloc(dev, sizeof(*acpi_desc), GFP_KERNEL); |
2544 | if (!acpi_desc) | |
2545 | return -ENOMEM; | |
2546 | acpi_nfit_desc_init(acpi_desc, &adev->dev); | |
2547 | acpi_desc->nvdimm_bus = nvdimm_bus_register(dev, &acpi_desc->nd_desc); | |
2548 | if (!acpi_desc->nvdimm_bus) | |
2549 | return -ENOMEM; | |
20985164 | 2550 | |
6b577c9d LK |
2551 | /* |
2552 | * Save the acpi header for later and then skip it, | |
2553 | * making nfit point to the first nfit table header. | |
2554 | */ | |
2555 | acpi_desc->acpi_header = *tbl; | |
2556 | acpi_desc->nfit = (void *) tbl + sizeof(struct acpi_table_nfit); | |
2557 | sz -= sizeof(struct acpi_table_nfit); | |
20985164 VV |
2558 | |
2559 | /* Evaluate _FIT and override with that if present */ | |
2560 | status = acpi_evaluate_object(adev->handle, "_FIT", NULL, &buf); | |
2561 | if (ACPI_SUCCESS(status) && buf.length > 0) { | |
6b577c9d LK |
2562 | union acpi_object *obj; |
2563 | /* | |
2564 | * Adjust for the acpi_object header of the _FIT | |
2565 | */ | |
2566 | obj = buf.pointer; | |
2567 | if (obj->type == ACPI_TYPE_BUFFER) { | |
2568 | acpi_desc->nfit = | |
2569 | (struct acpi_nfit_header *)obj->buffer.pointer; | |
2570 | sz = obj->buffer.length; | |
2571 | } else | |
2572 | dev_dbg(dev, "%s invalid type %d, ignoring _FIT\n", | |
2573 | __func__, (int) obj->type); | |
20985164 | 2574 | } |
b94d5230 DW |
2575 | |
2576 | rc = acpi_nfit_init(acpi_desc, sz); | |
2577 | if (rc) { | |
2578 | nvdimm_bus_unregister(acpi_desc->nvdimm_bus); | |
2579 | return rc; | |
2580 | } | |
2581 | return 0; | |
2582 | } | |
2583 | ||
2584 | static int acpi_nfit_remove(struct acpi_device *adev) | |
2585 | { | |
2586 | struct acpi_nfit_desc *acpi_desc = dev_get_drvdata(&adev->dev); | |
2587 | ||
7ae0fa43 DW |
2588 | acpi_desc->cancel = 1; |
2589 | flush_workqueue(nfit_wq); | |
b94d5230 DW |
2590 | nvdimm_bus_unregister(acpi_desc->nvdimm_bus); |
2591 | return 0; | |
2592 | } | |
2593 | ||
20985164 VV |
2594 | static void acpi_nfit_notify(struct acpi_device *adev, u32 event) |
2595 | { | |
2596 | struct acpi_nfit_desc *acpi_desc = dev_get_drvdata(&adev->dev); | |
2597 | struct acpi_buffer buf = { ACPI_ALLOCATE_BUFFER, NULL }; | |
6b577c9d LK |
2598 | struct acpi_nfit_header *nfit_saved; |
2599 | union acpi_object *obj; | |
20985164 VV |
2600 | struct device *dev = &adev->dev; |
2601 | acpi_status status; | |
2602 | int ret; | |
2603 | ||
2604 | dev_dbg(dev, "%s: event: %d\n", __func__, event); | |
2605 | ||
2606 | device_lock(dev); | |
2607 | if (!dev->driver) { | |
2608 | /* dev->driver may be null if we're being removed */ | |
2609 | dev_dbg(dev, "%s: no driver found for dev\n", __func__); | |
d91e8928 | 2610 | goto out_unlock; |
20985164 VV |
2611 | } |
2612 | ||
2613 | if (!acpi_desc) { | |
a61fe6f7 DW |
2614 | acpi_desc = devm_kzalloc(dev, sizeof(*acpi_desc), GFP_KERNEL); |
2615 | if (!acpi_desc) | |
2616 | goto out_unlock; | |
2617 | acpi_nfit_desc_init(acpi_desc, &adev->dev); | |
2618 | acpi_desc->nvdimm_bus = nvdimm_bus_register(dev, &acpi_desc->nd_desc); | |
2619 | if (!acpi_desc->nvdimm_bus) | |
20985164 | 2620 | goto out_unlock; |
7ae0fa43 DW |
2621 | } else { |
2622 | /* | |
2623 | * Finish previous registration before considering new | |
2624 | * regions. | |
2625 | */ | |
2626 | flush_workqueue(nfit_wq); | |
20985164 VV |
2627 | } |
2628 | ||
2629 | /* Evaluate _FIT */ | |
2630 | status = acpi_evaluate_object(adev->handle, "_FIT", NULL, &buf); | |
2631 | if (ACPI_FAILURE(status)) { | |
2632 | dev_err(dev, "failed to evaluate _FIT\n"); | |
2633 | goto out_unlock; | |
2634 | } | |
2635 | ||
2636 | nfit_saved = acpi_desc->nfit; | |
6b577c9d LK |
2637 | obj = buf.pointer; |
2638 | if (obj->type == ACPI_TYPE_BUFFER) { | |
2639 | acpi_desc->nfit = | |
2640 | (struct acpi_nfit_header *)obj->buffer.pointer; | |
2641 | ret = acpi_nfit_init(acpi_desc, obj->buffer.length); | |
2642 | if (ret) { | |
2643 | /* Merge failed, restore old nfit, and exit */ | |
2644 | acpi_desc->nfit = nfit_saved; | |
2645 | dev_err(dev, "failed to merge updated NFIT\n"); | |
2646 | } | |
2647 | } else { | |
2648 | /* Bad _FIT, restore old nfit */ | |
2649 | dev_err(dev, "Invalid _FIT\n"); | |
20985164 VV |
2650 | } |
2651 | kfree(buf.pointer); | |
2652 | ||
2653 | out_unlock: | |
2654 | device_unlock(dev); | |
2655 | } | |
2656 | ||
b94d5230 DW |
2657 | static const struct acpi_device_id acpi_nfit_ids[] = { |
2658 | { "ACPI0012", 0 }, | |
2659 | { "", 0 }, | |
2660 | }; | |
2661 | MODULE_DEVICE_TABLE(acpi, acpi_nfit_ids); | |
2662 | ||
2663 | static struct acpi_driver acpi_nfit_driver = { | |
2664 | .name = KBUILD_MODNAME, | |
2665 | .ids = acpi_nfit_ids, | |
2666 | .ops = { | |
2667 | .add = acpi_nfit_add, | |
2668 | .remove = acpi_nfit_remove, | |
20985164 | 2669 | .notify = acpi_nfit_notify, |
b94d5230 DW |
2670 | }, |
2671 | }; | |
2672 | ||
2673 | static __init int nfit_init(void) | |
2674 | { | |
2675 | BUILD_BUG_ON(sizeof(struct acpi_table_nfit) != 40); | |
2676 | BUILD_BUG_ON(sizeof(struct acpi_nfit_system_address) != 56); | |
2677 | BUILD_BUG_ON(sizeof(struct acpi_nfit_memory_map) != 48); | |
2678 | BUILD_BUG_ON(sizeof(struct acpi_nfit_interleave) != 20); | |
2679 | BUILD_BUG_ON(sizeof(struct acpi_nfit_smbios) != 9); | |
2680 | BUILD_BUG_ON(sizeof(struct acpi_nfit_control_region) != 80); | |
2681 | BUILD_BUG_ON(sizeof(struct acpi_nfit_data_region) != 40); | |
2682 | ||
2683 | acpi_str_to_uuid(UUID_VOLATILE_MEMORY, nfit_uuid[NFIT_SPA_VOLATILE]); | |
2684 | acpi_str_to_uuid(UUID_PERSISTENT_MEMORY, nfit_uuid[NFIT_SPA_PM]); | |
2685 | acpi_str_to_uuid(UUID_CONTROL_REGION, nfit_uuid[NFIT_SPA_DCR]); | |
2686 | acpi_str_to_uuid(UUID_DATA_REGION, nfit_uuid[NFIT_SPA_BDW]); | |
2687 | acpi_str_to_uuid(UUID_VOLATILE_VIRTUAL_DISK, nfit_uuid[NFIT_SPA_VDISK]); | |
2688 | acpi_str_to_uuid(UUID_VOLATILE_VIRTUAL_CD, nfit_uuid[NFIT_SPA_VCD]); | |
2689 | acpi_str_to_uuid(UUID_PERSISTENT_VIRTUAL_DISK, nfit_uuid[NFIT_SPA_PDISK]); | |
2690 | acpi_str_to_uuid(UUID_PERSISTENT_VIRTUAL_CD, nfit_uuid[NFIT_SPA_PCD]); | |
2691 | acpi_str_to_uuid(UUID_NFIT_BUS, nfit_uuid[NFIT_DEV_BUS]); | |
2692 | acpi_str_to_uuid(UUID_NFIT_DIMM, nfit_uuid[NFIT_DEV_DIMM]); | |
31eca76b DW |
2693 | acpi_str_to_uuid(UUID_NFIT_DIMM_N_HPE1, nfit_uuid[NFIT_DEV_DIMM_N_HPE1]); |
2694 | acpi_str_to_uuid(UUID_NFIT_DIMM_N_HPE2, nfit_uuid[NFIT_DEV_DIMM_N_HPE2]); | |
e02fb726 | 2695 | acpi_str_to_uuid(UUID_NFIT_DIMM_N_MSFT, nfit_uuid[NFIT_DEV_DIMM_N_MSFT]); |
b94d5230 | 2696 | |
7ae0fa43 DW |
2697 | nfit_wq = create_singlethread_workqueue("nfit"); |
2698 | if (!nfit_wq) | |
2699 | return -ENOMEM; | |
2700 | ||
b94d5230 DW |
2701 | return acpi_bus_register_driver(&acpi_nfit_driver); |
2702 | } | |
2703 | ||
2704 | static __exit void nfit_exit(void) | |
2705 | { | |
2706 | acpi_bus_unregister_driver(&acpi_nfit_driver); | |
7ae0fa43 | 2707 | destroy_workqueue(nfit_wq); |
b94d5230 DW |
2708 | } |
2709 | ||
2710 | module_init(nfit_init); | |
2711 | module_exit(nfit_exit); | |
2712 | MODULE_LICENSE("GPL v2"); | |
2713 | MODULE_AUTHOR("Intel Corporation"); |