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02cdfcf0 DM |
1 | |
2 | /* | |
3 | * acard-ahci.c - ACard AHCI SATA support | |
4 | * | |
8c3d3d4b | 5 | * Maintained by: Tejun Heo <tj@kernel.org> |
02cdfcf0 DM |
6 | * Please ALWAYS copy linux-ide@vger.kernel.org |
7 | * on emails. | |
8 | * | |
9 | * Copyright 2010 Red Hat, Inc. | |
10 | * | |
11 | * | |
12 | * This program is free software; you can redistribute it and/or modify | |
13 | * it under the terms of the GNU General Public License as published by | |
14 | * the Free Software Foundation; either version 2, or (at your option) | |
15 | * any later version. | |
16 | * | |
17 | * This program is distributed in the hope that it will be useful, | |
18 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
19 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
20 | * GNU General Public License for more details. | |
21 | * | |
22 | * You should have received a copy of the GNU General Public License | |
23 | * along with this program; see the file COPYING. If not, write to | |
24 | * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. | |
25 | * | |
26 | * | |
27 | * libata documentation is available via 'make {ps|pdf}docs', | |
28 | * as Documentation/DocBook/libata.* | |
29 | * | |
30 | * AHCI hardware documentation: | |
31 | * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf | |
32 | * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf | |
33 | * | |
34 | */ | |
35 | ||
36 | #include <linux/kernel.h> | |
37 | #include <linux/module.h> | |
38 | #include <linux/pci.h> | |
02cdfcf0 DM |
39 | #include <linux/blkdev.h> |
40 | #include <linux/delay.h> | |
41 | #include <linux/interrupt.h> | |
42 | #include <linux/dma-mapping.h> | |
43 | #include <linux/device.h> | |
44 | #include <linux/dmi.h> | |
45 | #include <linux/gfp.h> | |
46 | #include <scsi/scsi_host.h> | |
47 | #include <scsi/scsi_cmnd.h> | |
48 | #include <linux/libata.h> | |
49 | #include "ahci.h" | |
50 | ||
51 | #define DRV_NAME "acard-ahci" | |
52 | #define DRV_VERSION "1.0" | |
53 | ||
54 | /* | |
55 | Received FIS structure limited to 80h. | |
56 | */ | |
57 | ||
58 | #define ACARD_AHCI_RX_FIS_SZ 128 | |
59 | ||
60 | enum { | |
61 | AHCI_PCI_BAR = 5, | |
62 | }; | |
63 | ||
64 | enum board_ids { | |
65 | board_acard_ahci, | |
66 | }; | |
67 | ||
68 | struct acard_sg { | |
69 | __le32 addr; | |
70 | __le32 addr_hi; | |
71 | __le32 reserved; | |
72 | __le32 size; /* bit 31 (EOT) max==0x10000 (64k) */ | |
73 | }; | |
74 | ||
75 | static void acard_ahci_qc_prep(struct ata_queued_cmd *qc); | |
76 | static bool acard_ahci_qc_fill_rtf(struct ata_queued_cmd *qc); | |
77 | static int acard_ahci_port_start(struct ata_port *ap); | |
78 | static int acard_ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent); | |
79 | ||
58eb8cd5 | 80 | #ifdef CONFIG_PM_SLEEP |
02cdfcf0 DM |
81 | static int acard_ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg); |
82 | static int acard_ahci_pci_device_resume(struct pci_dev *pdev); | |
83 | #endif | |
84 | ||
85 | static struct scsi_host_template acard_ahci_sht = { | |
86 | AHCI_SHT("acard-ahci"), | |
87 | }; | |
88 | ||
89 | static struct ata_port_operations acard_ops = { | |
90 | .inherits = &ahci_ops, | |
91 | .qc_prep = acard_ahci_qc_prep, | |
92 | .qc_fill_rtf = acard_ahci_qc_fill_rtf, | |
93 | .port_start = acard_ahci_port_start, | |
94 | }; | |
95 | ||
96 | #define AHCI_HFLAGS(flags) .private_data = (void *)(flags) | |
97 | ||
98 | static const struct ata_port_info acard_ahci_port_info[] = { | |
99 | [board_acard_ahci] = | |
100 | { | |
101 | AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ), | |
102 | .flags = AHCI_FLAG_COMMON, | |
103 | .pio_mask = ATA_PIO4, | |
104 | .udma_mask = ATA_UDMA6, | |
105 | .port_ops = &acard_ops, | |
106 | }, | |
107 | }; | |
108 | ||
109 | static const struct pci_device_id acard_ahci_pci_tbl[] = { | |
110 | /* ACard */ | |
111 | { PCI_VDEVICE(ARTOP, 0x000d), board_acard_ahci }, /* ATP8620 */ | |
112 | ||
113 | { } /* terminate list */ | |
114 | }; | |
115 | ||
116 | static struct pci_driver acard_ahci_pci_driver = { | |
117 | .name = DRV_NAME, | |
118 | .id_table = acard_ahci_pci_tbl, | |
119 | .probe = acard_ahci_init_one, | |
120 | .remove = ata_pci_remove_one, | |
58eb8cd5 | 121 | #ifdef CONFIG_PM_SLEEP |
02cdfcf0 DM |
122 | .suspend = acard_ahci_pci_device_suspend, |
123 | .resume = acard_ahci_pci_device_resume, | |
124 | #endif | |
125 | }; | |
126 | ||
58eb8cd5 | 127 | #ifdef CONFIG_PM_SLEEP |
02cdfcf0 DM |
128 | static int acard_ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg) |
129 | { | |
0a86e1c8 | 130 | struct ata_host *host = pci_get_drvdata(pdev); |
02cdfcf0 DM |
131 | struct ahci_host_priv *hpriv = host->private_data; |
132 | void __iomem *mmio = hpriv->mmio; | |
133 | u32 ctl; | |
134 | ||
135 | if (mesg.event & PM_EVENT_SUSPEND && | |
136 | hpriv->flags & AHCI_HFLAG_NO_SUSPEND) { | |
a44fec1f JP |
137 | dev_err(&pdev->dev, |
138 | "BIOS update required for suspend/resume\n"); | |
02cdfcf0 DM |
139 | return -EIO; |
140 | } | |
141 | ||
142 | if (mesg.event & PM_EVENT_SLEEP) { | |
143 | /* AHCI spec rev1.1 section 8.3.3: | |
144 | * Software must disable interrupts prior to requesting a | |
145 | * transition of the HBA to D3 state. | |
146 | */ | |
147 | ctl = readl(mmio + HOST_CTL); | |
148 | ctl &= ~HOST_IRQ_EN; | |
149 | writel(ctl, mmio + HOST_CTL); | |
150 | readl(mmio + HOST_CTL); /* flush */ | |
151 | } | |
152 | ||
153 | return ata_pci_device_suspend(pdev, mesg); | |
154 | } | |
155 | ||
156 | static int acard_ahci_pci_device_resume(struct pci_dev *pdev) | |
157 | { | |
0a86e1c8 | 158 | struct ata_host *host = pci_get_drvdata(pdev); |
02cdfcf0 DM |
159 | int rc; |
160 | ||
161 | rc = ata_pci_device_do_resume(pdev); | |
162 | if (rc) | |
163 | return rc; | |
164 | ||
165 | if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) { | |
166 | rc = ahci_reset_controller(host); | |
167 | if (rc) | |
168 | return rc; | |
169 | ||
170 | ahci_init_controller(host); | |
171 | } | |
172 | ||
173 | ata_host_resume(host); | |
174 | ||
175 | return 0; | |
176 | } | |
177 | #endif | |
178 | ||
179 | static int acard_ahci_configure_dma_masks(struct pci_dev *pdev, int using_dac) | |
180 | { | |
181 | int rc; | |
182 | ||
183 | if (using_dac && | |
184 | !pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) { | |
185 | rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)); | |
186 | if (rc) { | |
187 | rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)); | |
188 | if (rc) { | |
a44fec1f | 189 | dev_err(&pdev->dev, |
02cdfcf0 DM |
190 | "64-bit DMA enable failed\n"); |
191 | return rc; | |
192 | } | |
193 | } | |
194 | } else { | |
195 | rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); | |
196 | if (rc) { | |
a44fec1f | 197 | dev_err(&pdev->dev, "32-bit DMA enable failed\n"); |
02cdfcf0 DM |
198 | return rc; |
199 | } | |
200 | rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)); | |
201 | if (rc) { | |
a44fec1f JP |
202 | dev_err(&pdev->dev, |
203 | "32-bit consistent DMA enable failed\n"); | |
02cdfcf0 DM |
204 | return rc; |
205 | } | |
206 | } | |
207 | return 0; | |
208 | } | |
209 | ||
210 | static void acard_ahci_pci_print_info(struct ata_host *host) | |
211 | { | |
212 | struct pci_dev *pdev = to_pci_dev(host->dev); | |
213 | u16 cc; | |
214 | const char *scc_s; | |
215 | ||
216 | pci_read_config_word(pdev, 0x0a, &cc); | |
217 | if (cc == PCI_CLASS_STORAGE_IDE) | |
218 | scc_s = "IDE"; | |
219 | else if (cc == PCI_CLASS_STORAGE_SATA) | |
220 | scc_s = "SATA"; | |
221 | else if (cc == PCI_CLASS_STORAGE_RAID) | |
222 | scc_s = "RAID"; | |
223 | else | |
224 | scc_s = "unknown"; | |
225 | ||
226 | ahci_print_info(host, scc_s); | |
227 | } | |
228 | ||
229 | static unsigned int acard_ahci_fill_sg(struct ata_queued_cmd *qc, void *cmd_tbl) | |
230 | { | |
231 | struct scatterlist *sg; | |
232 | struct acard_sg *acard_sg = cmd_tbl + AHCI_CMD_TBL_HDR_SZ; | |
233 | unsigned int si, last_si = 0; | |
234 | ||
235 | VPRINTK("ENTER\n"); | |
236 | ||
237 | /* | |
238 | * Next, the S/G list. | |
239 | */ | |
240 | for_each_sg(qc->sg, sg, qc->n_elem, si) { | |
241 | dma_addr_t addr = sg_dma_address(sg); | |
242 | u32 sg_len = sg_dma_len(sg); | |
243 | ||
244 | /* | |
245 | * ACard note: | |
246 | * We must set an end-of-table (EOT) bit, | |
247 | * and the segment cannot exceed 64k (0x10000) | |
248 | */ | |
249 | acard_sg[si].addr = cpu_to_le32(addr & 0xffffffff); | |
250 | acard_sg[si].addr_hi = cpu_to_le32((addr >> 16) >> 16); | |
251 | acard_sg[si].size = cpu_to_le32(sg_len); | |
252 | last_si = si; | |
253 | } | |
254 | ||
255 | acard_sg[last_si].size |= cpu_to_le32(1 << 31); /* set EOT */ | |
256 | ||
257 | return si; | |
258 | } | |
259 | ||
260 | static void acard_ahci_qc_prep(struct ata_queued_cmd *qc) | |
261 | { | |
262 | struct ata_port *ap = qc->ap; | |
263 | struct ahci_port_priv *pp = ap->private_data; | |
264 | int is_atapi = ata_is_atapi(qc->tf.protocol); | |
265 | void *cmd_tbl; | |
266 | u32 opts; | |
267 | const u32 cmd_fis_len = 5; /* five dwords */ | |
268 | unsigned int n_elem; | |
269 | ||
270 | /* | |
271 | * Fill in command table information. First, the header, | |
272 | * a SATA Register - Host to Device command FIS. | |
273 | */ | |
274 | cmd_tbl = pp->cmd_tbl + qc->tag * AHCI_CMD_TBL_SZ; | |
275 | ||
276 | ata_tf_to_fis(&qc->tf, qc->dev->link->pmp, 1, cmd_tbl); | |
277 | if (is_atapi) { | |
278 | memset(cmd_tbl + AHCI_CMD_TBL_CDB, 0, 32); | |
279 | memcpy(cmd_tbl + AHCI_CMD_TBL_CDB, qc->cdb, qc->dev->cdb_len); | |
280 | } | |
281 | ||
282 | n_elem = 0; | |
283 | if (qc->flags & ATA_QCFLAG_DMAMAP) | |
284 | n_elem = acard_ahci_fill_sg(qc, cmd_tbl); | |
285 | ||
286 | /* | |
287 | * Fill in command slot information. | |
288 | * | |
289 | * ACard note: prd table length not filled in | |
290 | */ | |
291 | opts = cmd_fis_len | (qc->dev->link->pmp << 12); | |
292 | if (qc->tf.flags & ATA_TFLAG_WRITE) | |
293 | opts |= AHCI_CMD_WRITE; | |
294 | if (is_atapi) | |
295 | opts |= AHCI_CMD_ATAPI | AHCI_CMD_PREFETCH; | |
296 | ||
297 | ahci_fill_cmd_slot(pp, qc->tag, opts); | |
298 | } | |
299 | ||
300 | static bool acard_ahci_qc_fill_rtf(struct ata_queued_cmd *qc) | |
301 | { | |
302 | struct ahci_port_priv *pp = qc->ap->private_data; | |
303 | u8 *rx_fis = pp->rx_fis; | |
304 | ||
305 | if (pp->fbs_enabled) | |
306 | rx_fis += qc->dev->link->pmp * ACARD_AHCI_RX_FIS_SZ; | |
307 | ||
308 | /* | |
309 | * After a successful execution of an ATA PIO data-in command, | |
310 | * the device doesn't send D2H Reg FIS to update the TF and | |
311 | * the host should take TF and E_Status from the preceding PIO | |
312 | * Setup FIS. | |
313 | */ | |
314 | if (qc->tf.protocol == ATA_PROT_PIO && qc->dma_dir == DMA_FROM_DEVICE && | |
315 | !(qc->flags & ATA_QCFLAG_FAILED)) { | |
316 | ata_tf_from_fis(rx_fis + RX_FIS_PIO_SETUP, &qc->result_tf); | |
317 | qc->result_tf.command = (rx_fis + RX_FIS_PIO_SETUP)[15]; | |
318 | } else | |
319 | ata_tf_from_fis(rx_fis + RX_FIS_D2H_REG, &qc->result_tf); | |
320 | ||
321 | return true; | |
322 | } | |
323 | ||
324 | static int acard_ahci_port_start(struct ata_port *ap) | |
325 | { | |
326 | struct ahci_host_priv *hpriv = ap->host->private_data; | |
327 | struct device *dev = ap->host->dev; | |
328 | struct ahci_port_priv *pp; | |
329 | void *mem; | |
330 | dma_addr_t mem_dma; | |
331 | size_t dma_sz, rx_fis_sz; | |
332 | ||
333 | pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL); | |
334 | if (!pp) | |
335 | return -ENOMEM; | |
336 | ||
337 | /* check FBS capability */ | |
338 | if ((hpriv->cap & HOST_CAP_FBS) && sata_pmp_supported(ap)) { | |
339 | void __iomem *port_mmio = ahci_port_base(ap); | |
340 | u32 cmd = readl(port_mmio + PORT_CMD); | |
341 | if (cmd & PORT_CMD_FBSCP) | |
342 | pp->fbs_supported = true; | |
343 | else if (hpriv->flags & AHCI_HFLAG_YES_FBS) { | |
a44fec1f JP |
344 | dev_info(dev, "port %d can do FBS, forcing FBSCP\n", |
345 | ap->port_no); | |
02cdfcf0 DM |
346 | pp->fbs_supported = true; |
347 | } else | |
a44fec1f JP |
348 | dev_warn(dev, "port %d is not capable of FBS\n", |
349 | ap->port_no); | |
02cdfcf0 DM |
350 | } |
351 | ||
352 | if (pp->fbs_supported) { | |
353 | dma_sz = AHCI_PORT_PRIV_FBS_DMA_SZ; | |
354 | rx_fis_sz = ACARD_AHCI_RX_FIS_SZ * 16; | |
355 | } else { | |
356 | dma_sz = AHCI_PORT_PRIV_DMA_SZ; | |
357 | rx_fis_sz = ACARD_AHCI_RX_FIS_SZ; | |
358 | } | |
359 | ||
360 | mem = dmam_alloc_coherent(dev, dma_sz, &mem_dma, GFP_KERNEL); | |
361 | if (!mem) | |
362 | return -ENOMEM; | |
363 | memset(mem, 0, dma_sz); | |
364 | ||
365 | /* | |
366 | * First item in chunk of DMA memory: 32-slot command table, | |
367 | * 32 bytes each in size | |
368 | */ | |
369 | pp->cmd_slot = mem; | |
370 | pp->cmd_slot_dma = mem_dma; | |
371 | ||
372 | mem += AHCI_CMD_SLOT_SZ; | |
373 | mem_dma += AHCI_CMD_SLOT_SZ; | |
374 | ||
375 | /* | |
376 | * Second item: Received-FIS area | |
377 | */ | |
378 | pp->rx_fis = mem; | |
379 | pp->rx_fis_dma = mem_dma; | |
380 | ||
381 | mem += rx_fis_sz; | |
382 | mem_dma += rx_fis_sz; | |
383 | ||
384 | /* | |
385 | * Third item: data area for storing a single command | |
386 | * and its scatter-gather table | |
387 | */ | |
388 | pp->cmd_tbl = mem; | |
389 | pp->cmd_tbl_dma = mem_dma; | |
390 | ||
391 | /* | |
392 | * Save off initial list of interrupts to be enabled. | |
393 | * This could be changed later | |
394 | */ | |
395 | pp->intr_mask = DEF_PORT_IRQ; | |
396 | ||
397 | ap->private_data = pp; | |
398 | ||
399 | /* engage engines, captain */ | |
400 | return ahci_port_resume(ap); | |
401 | } | |
402 | ||
403 | static int acard_ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) | |
404 | { | |
02cdfcf0 DM |
405 | unsigned int board_id = ent->driver_data; |
406 | struct ata_port_info pi = acard_ahci_port_info[board_id]; | |
407 | const struct ata_port_info *ppi[] = { &pi, NULL }; | |
408 | struct device *dev = &pdev->dev; | |
409 | struct ahci_host_priv *hpriv; | |
410 | struct ata_host *host; | |
411 | int n_ports, i, rc; | |
412 | ||
413 | VPRINTK("ENTER\n"); | |
414 | ||
f68b3afe | 415 | WARN_ON((int)ATA_MAX_QUEUE > AHCI_MAX_CMDS); |
02cdfcf0 | 416 | |
06296a1e | 417 | ata_print_version_once(&pdev->dev, DRV_VERSION); |
02cdfcf0 DM |
418 | |
419 | /* acquire resources */ | |
420 | rc = pcim_enable_device(pdev); | |
421 | if (rc) | |
422 | return rc; | |
423 | ||
424 | /* AHCI controllers often implement SFF compatible interface. | |
425 | * Grab all PCI BARs just in case. | |
426 | */ | |
427 | rc = pcim_iomap_regions_request_all(pdev, 1 << AHCI_PCI_BAR, DRV_NAME); | |
428 | if (rc == -EBUSY) | |
429 | pcim_pin_device(pdev); | |
430 | if (rc) | |
431 | return rc; | |
432 | ||
433 | hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL); | |
434 | if (!hpriv) | |
435 | return -ENOMEM; | |
436 | hpriv->flags |= (unsigned long)pi.private_data; | |
437 | ||
438 | if (!(hpriv->flags & AHCI_HFLAG_NO_MSI)) | |
439 | pci_enable_msi(pdev); | |
440 | ||
441 | hpriv->mmio = pcim_iomap_table(pdev)[AHCI_PCI_BAR]; | |
442 | ||
443 | /* save initial config */ | |
725c7b57 | 444 | ahci_save_initial_config(&pdev->dev, hpriv); |
02cdfcf0 DM |
445 | |
446 | /* prepare host */ | |
447 | if (hpriv->cap & HOST_CAP_NCQ) | |
448 | pi.flags |= ATA_FLAG_NCQ; | |
449 | ||
450 | if (hpriv->cap & HOST_CAP_PMP) | |
451 | pi.flags |= ATA_FLAG_PMP; | |
452 | ||
453 | ahci_set_em_messages(hpriv, &pi); | |
454 | ||
455 | /* CAP.NP sometimes indicate the index of the last enabled | |
456 | * port, at other times, that of the last possible port, so | |
457 | * determining the maximum port number requires looking at | |
458 | * both CAP.NP and port_map. | |
459 | */ | |
460 | n_ports = max(ahci_nr_ports(hpriv->cap), fls(hpriv->port_map)); | |
461 | ||
462 | host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports); | |
463 | if (!host) | |
464 | return -ENOMEM; | |
465 | host->private_data = hpriv; | |
466 | ||
467 | if (!(hpriv->cap & HOST_CAP_SSS) || ahci_ignore_sss) | |
468 | host->flags |= ATA_HOST_PARALLEL_SCAN; | |
469 | else | |
470 | printk(KERN_INFO "ahci: SSS flag set, parallel bus scan disabled\n"); | |
471 | ||
472 | for (i = 0; i < host->n_ports; i++) { | |
473 | struct ata_port *ap = host->ports[i]; | |
474 | ||
475 | ata_port_pbar_desc(ap, AHCI_PCI_BAR, -1, "abar"); | |
476 | ata_port_pbar_desc(ap, AHCI_PCI_BAR, | |
477 | 0x100 + ap->port_no * 0x80, "port"); | |
478 | ||
479 | /* set initial link pm policy */ | |
480 | /* | |
481 | ap->pm_policy = NOT_AVAILABLE; | |
482 | */ | |
483 | /* disabled/not-implemented port */ | |
484 | if (!(hpriv->port_map & (1 << i))) | |
485 | ap->ops = &ata_dummy_port_ops; | |
486 | } | |
487 | ||
488 | /* initialize adapter */ | |
489 | rc = acard_ahci_configure_dma_masks(pdev, hpriv->cap & HOST_CAP_64); | |
490 | if (rc) | |
491 | return rc; | |
492 | ||
493 | rc = ahci_reset_controller(host); | |
494 | if (rc) | |
495 | return rc; | |
496 | ||
497 | ahci_init_controller(host); | |
498 | acard_ahci_pci_print_info(host); | |
499 | ||
500 | pci_set_master(pdev); | |
501 | return ata_host_activate(host, pdev->irq, ahci_interrupt, IRQF_SHARED, | |
502 | &acard_ahci_sht); | |
503 | } | |
504 | ||
2fc75da0 | 505 | module_pci_driver(acard_ahci_pci_driver); |
02cdfcf0 DM |
506 | |
507 | MODULE_AUTHOR("Jeff Garzik"); | |
508 | MODULE_DESCRIPTION("ACard AHCI SATA low-level driver"); | |
509 | MODULE_LICENSE("GPL"); | |
510 | MODULE_DEVICE_TABLE(pci, acard_ahci_pci_tbl); | |
511 | MODULE_VERSION(DRV_VERSION); |