Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * ahci.c - AHCI SATA support | |
3 | * | |
8c3d3d4b | 4 | * Maintained by: Tejun Heo <tj@kernel.org> |
af36d7f0 JG |
5 | * Please ALWAYS copy linux-ide@vger.kernel.org |
6 | * on emails. | |
7 | * | |
8 | * Copyright 2004-2005 Red Hat, Inc. | |
9 | * | |
10 | * | |
11 | * This program is free software; you can redistribute it and/or modify | |
12 | * it under the terms of the GNU General Public License as published by | |
13 | * the Free Software Foundation; either version 2, or (at your option) | |
14 | * any later version. | |
15 | * | |
16 | * This program is distributed in the hope that it will be useful, | |
17 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
19 | * GNU General Public License for more details. | |
20 | * | |
21 | * You should have received a copy of the GNU General Public License | |
22 | * along with this program; see the file COPYING. If not, write to | |
23 | * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. | |
24 | * | |
25 | * | |
26 | * libata documentation is available via 'make {ps|pdf}docs', | |
27 | * as Documentation/DocBook/libata.* | |
28 | * | |
29 | * AHCI hardware documentation: | |
1da177e4 | 30 | * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf |
af36d7f0 | 31 | * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf |
1da177e4 LT |
32 | * |
33 | */ | |
34 | ||
35 | #include <linux/kernel.h> | |
36 | #include <linux/module.h> | |
37 | #include <linux/pci.h> | |
1da177e4 LT |
38 | #include <linux/blkdev.h> |
39 | #include <linux/delay.h> | |
40 | #include <linux/interrupt.h> | |
87507cfd | 41 | #include <linux/dma-mapping.h> |
a9524a76 | 42 | #include <linux/device.h> |
edc93052 | 43 | #include <linux/dmi.h> |
5a0e3ad6 | 44 | #include <linux/gfp.h> |
ee2aad42 | 45 | #include <linux/msi.h> |
1da177e4 | 46 | #include <scsi/scsi_host.h> |
193515d5 | 47 | #include <scsi/scsi_cmnd.h> |
1da177e4 | 48 | #include <linux/libata.h> |
365cfa1e | 49 | #include "ahci.h" |
1da177e4 LT |
50 | |
51 | #define DRV_NAME "ahci" | |
7d50b60b | 52 | #define DRV_VERSION "3.0" |
1da177e4 | 53 | |
1da177e4 | 54 | enum { |
318893e1 | 55 | AHCI_PCI_BAR_STA2X11 = 0, |
b7ae128d | 56 | AHCI_PCI_BAR_CAVIUM = 0, |
7f9c9f8e | 57 | AHCI_PCI_BAR_ENMOTUS = 2, |
318893e1 | 58 | AHCI_PCI_BAR_STANDARD = 5, |
441577ef TH |
59 | }; |
60 | ||
61 | enum board_ids { | |
62 | /* board IDs by feature in alphabetical order */ | |
63 | board_ahci, | |
64 | board_ahci_ign_iferr, | |
66a7cbc3 | 65 | board_ahci_nomsi, |
67809f85 | 66 | board_ahci_noncq, |
441577ef | 67 | board_ahci_nosntf, |
5f173107 | 68 | board_ahci_yes_fbs, |
1da177e4 | 69 | |
441577ef | 70 | /* board IDs for specific chipsets in alphabetical order */ |
dbfe8ef5 | 71 | board_ahci_avn, |
441577ef | 72 | board_ahci_mcp65, |
83f2b963 TH |
73 | board_ahci_mcp77, |
74 | board_ahci_mcp89, | |
441577ef TH |
75 | board_ahci_mv, |
76 | board_ahci_sb600, | |
77 | board_ahci_sb700, /* for SB700 and SB800 */ | |
78 | board_ahci_vt8251, | |
79 | ||
80 | /* aliases */ | |
81 | board_ahci_mcp_linux = board_ahci_mcp65, | |
82 | board_ahci_mcp67 = board_ahci_mcp65, | |
83 | board_ahci_mcp73 = board_ahci_mcp65, | |
83f2b963 | 84 | board_ahci_mcp79 = board_ahci_mcp77, |
1da177e4 LT |
85 | }; |
86 | ||
2dcb407e | 87 | static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent); |
a1efdaba TH |
88 | static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class, |
89 | unsigned long deadline); | |
dbfe8ef5 DW |
90 | static int ahci_avn_hardreset(struct ata_link *link, unsigned int *class, |
91 | unsigned long deadline); | |
cb85696d JL |
92 | static void ahci_mcp89_apple_enable(struct pci_dev *pdev); |
93 | static bool is_mcp89_apple(struct pci_dev *pdev); | |
a1efdaba TH |
94 | static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class, |
95 | unsigned long deadline); | |
438ac6d5 | 96 | #ifdef CONFIG_PM |
c1332875 TH |
97 | static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg); |
98 | static int ahci_pci_device_resume(struct pci_dev *pdev); | |
438ac6d5 | 99 | #endif |
ad616ffb | 100 | |
fad16e7a TH |
101 | static struct scsi_host_template ahci_sht = { |
102 | AHCI_SHT("ahci"), | |
103 | }; | |
104 | ||
029cfd6b TH |
105 | static struct ata_port_operations ahci_vt8251_ops = { |
106 | .inherits = &ahci_ops, | |
a1efdaba | 107 | .hardreset = ahci_vt8251_hardreset, |
029cfd6b | 108 | }; |
edc93052 | 109 | |
029cfd6b TH |
110 | static struct ata_port_operations ahci_p5wdh_ops = { |
111 | .inherits = &ahci_ops, | |
a1efdaba | 112 | .hardreset = ahci_p5wdh_hardreset, |
edc93052 TH |
113 | }; |
114 | ||
dbfe8ef5 DW |
115 | static struct ata_port_operations ahci_avn_ops = { |
116 | .inherits = &ahci_ops, | |
117 | .hardreset = ahci_avn_hardreset, | |
118 | }; | |
119 | ||
98ac62de | 120 | static const struct ata_port_info ahci_port_info[] = { |
441577ef | 121 | /* by features */ |
facb8fa6 | 122 | [board_ahci] = { |
1188c0d8 | 123 | .flags = AHCI_FLAG_COMMON, |
14bdef98 | 124 | .pio_mask = ATA_PIO4, |
469248ab | 125 | .udma_mask = ATA_UDMA6, |
1da177e4 LT |
126 | .port_ops = &ahci_ops, |
127 | }, | |
facb8fa6 | 128 | [board_ahci_ign_iferr] = { |
441577ef | 129 | AHCI_HFLAGS (AHCI_HFLAG_IGN_IRQ_IF_ERR), |
417a1a6d | 130 | .flags = AHCI_FLAG_COMMON, |
14bdef98 | 131 | .pio_mask = ATA_PIO4, |
469248ab | 132 | .udma_mask = ATA_UDMA6, |
441577ef | 133 | .port_ops = &ahci_ops, |
bf2af2a2 | 134 | }, |
66a7cbc3 TH |
135 | [board_ahci_nomsi] = { |
136 | AHCI_HFLAGS (AHCI_HFLAG_NO_MSI), | |
137 | .flags = AHCI_FLAG_COMMON, | |
138 | .pio_mask = ATA_PIO4, | |
139 | .udma_mask = ATA_UDMA6, | |
140 | .port_ops = &ahci_ops, | |
141 | }, | |
67809f85 LK |
142 | [board_ahci_noncq] = { |
143 | AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ), | |
144 | .flags = AHCI_FLAG_COMMON, | |
145 | .pio_mask = ATA_PIO4, | |
146 | .udma_mask = ATA_UDMA6, | |
147 | .port_ops = &ahci_ops, | |
148 | }, | |
facb8fa6 | 149 | [board_ahci_nosntf] = { |
441577ef | 150 | AHCI_HFLAGS (AHCI_HFLAG_NO_SNTF), |
417a1a6d | 151 | .flags = AHCI_FLAG_COMMON, |
14bdef98 | 152 | .pio_mask = ATA_PIO4, |
469248ab | 153 | .udma_mask = ATA_UDMA6, |
41669553 TH |
154 | .port_ops = &ahci_ops, |
155 | }, | |
facb8fa6 | 156 | [board_ahci_yes_fbs] = { |
5f173107 TH |
157 | AHCI_HFLAGS (AHCI_HFLAG_YES_FBS), |
158 | .flags = AHCI_FLAG_COMMON, | |
159 | .pio_mask = ATA_PIO4, | |
160 | .udma_mask = ATA_UDMA6, | |
161 | .port_ops = &ahci_ops, | |
162 | }, | |
441577ef | 163 | /* by chipsets */ |
dbfe8ef5 DW |
164 | [board_ahci_avn] = { |
165 | .flags = AHCI_FLAG_COMMON, | |
166 | .pio_mask = ATA_PIO4, | |
167 | .udma_mask = ATA_UDMA6, | |
168 | .port_ops = &ahci_avn_ops, | |
169 | }, | |
facb8fa6 | 170 | [board_ahci_mcp65] = { |
83f2b963 TH |
171 | AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP | |
172 | AHCI_HFLAG_YES_NCQ), | |
ae01b249 | 173 | .flags = AHCI_FLAG_COMMON | ATA_FLAG_NO_DIPM, |
83f2b963 TH |
174 | .pio_mask = ATA_PIO4, |
175 | .udma_mask = ATA_UDMA6, | |
176 | .port_ops = &ahci_ops, | |
177 | }, | |
facb8fa6 | 178 | [board_ahci_mcp77] = { |
83f2b963 TH |
179 | AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP), |
180 | .flags = AHCI_FLAG_COMMON, | |
181 | .pio_mask = ATA_PIO4, | |
182 | .udma_mask = ATA_UDMA6, | |
183 | .port_ops = &ahci_ops, | |
184 | }, | |
facb8fa6 | 185 | [board_ahci_mcp89] = { |
83f2b963 | 186 | AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA), |
417a1a6d | 187 | .flags = AHCI_FLAG_COMMON, |
14bdef98 | 188 | .pio_mask = ATA_PIO4, |
469248ab | 189 | .udma_mask = ATA_UDMA6, |
441577ef | 190 | .port_ops = &ahci_ops, |
55a61604 | 191 | }, |
facb8fa6 | 192 | [board_ahci_mv] = { |
417a1a6d | 193 | AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_MSI | |
17248461 | 194 | AHCI_HFLAG_MV_PATA | AHCI_HFLAG_NO_PMP), |
9cbe056f | 195 | .flags = ATA_FLAG_SATA | ATA_FLAG_PIO_DMA, |
14bdef98 | 196 | .pio_mask = ATA_PIO4, |
cd70c266 JG |
197 | .udma_mask = ATA_UDMA6, |
198 | .port_ops = &ahci_ops, | |
199 | }, | |
facb8fa6 | 200 | [board_ahci_sb600] = { |
441577ef TH |
201 | AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL | |
202 | AHCI_HFLAG_NO_MSI | AHCI_HFLAG_SECT255 | | |
203 | AHCI_HFLAG_32BIT_ONLY), | |
e39fc8c9 | 204 | .flags = AHCI_FLAG_COMMON, |
14bdef98 | 205 | .pio_mask = ATA_PIO4, |
e39fc8c9 | 206 | .udma_mask = ATA_UDMA6, |
345347c5 | 207 | .port_ops = &ahci_pmp_retry_srst_ops, |
e39fc8c9 | 208 | }, |
facb8fa6 | 209 | [board_ahci_sb700] = { /* for SB700 and SB800 */ |
441577ef | 210 | AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL), |
aa431dd3 TH |
211 | .flags = AHCI_FLAG_COMMON, |
212 | .pio_mask = ATA_PIO4, | |
213 | .udma_mask = ATA_UDMA6, | |
345347c5 | 214 | .port_ops = &ahci_pmp_retry_srst_ops, |
aa431dd3 | 215 | }, |
facb8fa6 | 216 | [board_ahci_vt8251] = { |
441577ef | 217 | AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_PMP), |
1b677afd SL |
218 | .flags = AHCI_FLAG_COMMON, |
219 | .pio_mask = ATA_PIO4, | |
220 | .udma_mask = ATA_UDMA6, | |
441577ef | 221 | .port_ops = &ahci_vt8251_ops, |
1b677afd | 222 | }, |
1da177e4 LT |
223 | }; |
224 | ||
3b7d697d | 225 | static const struct pci_device_id ahci_pci_tbl[] = { |
fe7fa31a | 226 | /* Intel */ |
54bb3a94 JG |
227 | { PCI_VDEVICE(INTEL, 0x2652), board_ahci }, /* ICH6 */ |
228 | { PCI_VDEVICE(INTEL, 0x2653), board_ahci }, /* ICH6M */ | |
229 | { PCI_VDEVICE(INTEL, 0x27c1), board_ahci }, /* ICH7 */ | |
230 | { PCI_VDEVICE(INTEL, 0x27c5), board_ahci }, /* ICH7M */ | |
231 | { PCI_VDEVICE(INTEL, 0x27c3), board_ahci }, /* ICH7R */ | |
82490c09 | 232 | { PCI_VDEVICE(AL, 0x5288), board_ahci_ign_iferr }, /* ULi M5288 */ |
54bb3a94 JG |
233 | { PCI_VDEVICE(INTEL, 0x2681), board_ahci }, /* ESB2 */ |
234 | { PCI_VDEVICE(INTEL, 0x2682), board_ahci }, /* ESB2 */ | |
235 | { PCI_VDEVICE(INTEL, 0x2683), board_ahci }, /* ESB2 */ | |
236 | { PCI_VDEVICE(INTEL, 0x27c6), board_ahci }, /* ICH7-M DH */ | |
7a234aff | 237 | { PCI_VDEVICE(INTEL, 0x2821), board_ahci }, /* ICH8 */ |
1b677afd | 238 | { PCI_VDEVICE(INTEL, 0x2822), board_ahci_nosntf }, /* ICH8 */ |
7a234aff TH |
239 | { PCI_VDEVICE(INTEL, 0x2824), board_ahci }, /* ICH8 */ |
240 | { PCI_VDEVICE(INTEL, 0x2829), board_ahci }, /* ICH8M */ | |
241 | { PCI_VDEVICE(INTEL, 0x282a), board_ahci }, /* ICH8M */ | |
242 | { PCI_VDEVICE(INTEL, 0x2922), board_ahci }, /* ICH9 */ | |
243 | { PCI_VDEVICE(INTEL, 0x2923), board_ahci }, /* ICH9 */ | |
244 | { PCI_VDEVICE(INTEL, 0x2924), board_ahci }, /* ICH9 */ | |
245 | { PCI_VDEVICE(INTEL, 0x2925), board_ahci }, /* ICH9 */ | |
246 | { PCI_VDEVICE(INTEL, 0x2927), board_ahci }, /* ICH9 */ | |
247 | { PCI_VDEVICE(INTEL, 0x2929), board_ahci }, /* ICH9M */ | |
248 | { PCI_VDEVICE(INTEL, 0x292a), board_ahci }, /* ICH9M */ | |
249 | { PCI_VDEVICE(INTEL, 0x292b), board_ahci }, /* ICH9M */ | |
250 | { PCI_VDEVICE(INTEL, 0x292c), board_ahci }, /* ICH9M */ | |
251 | { PCI_VDEVICE(INTEL, 0x292f), board_ahci }, /* ICH9M */ | |
252 | { PCI_VDEVICE(INTEL, 0x294d), board_ahci }, /* ICH9 */ | |
253 | { PCI_VDEVICE(INTEL, 0x294e), board_ahci }, /* ICH9M */ | |
d4155e6f JG |
254 | { PCI_VDEVICE(INTEL, 0x502a), board_ahci }, /* Tolapai */ |
255 | { PCI_VDEVICE(INTEL, 0x502b), board_ahci }, /* Tolapai */ | |
16ad1ad9 | 256 | { PCI_VDEVICE(INTEL, 0x3a05), board_ahci }, /* ICH10 */ |
b2dde6af | 257 | { PCI_VDEVICE(INTEL, 0x3a22), board_ahci }, /* ICH10 */ |
16ad1ad9 | 258 | { PCI_VDEVICE(INTEL, 0x3a25), board_ahci }, /* ICH10 */ |
c1f57d9b DM |
259 | { PCI_VDEVICE(INTEL, 0x3b22), board_ahci }, /* PCH AHCI */ |
260 | { PCI_VDEVICE(INTEL, 0x3b23), board_ahci }, /* PCH AHCI */ | |
adcb5308 | 261 | { PCI_VDEVICE(INTEL, 0x3b24), board_ahci }, /* PCH RAID */ |
8e48b6b3 | 262 | { PCI_VDEVICE(INTEL, 0x3b25), board_ahci }, /* PCH RAID */ |
c1f57d9b | 263 | { PCI_VDEVICE(INTEL, 0x3b29), board_ahci }, /* PCH AHCI */ |
adcb5308 | 264 | { PCI_VDEVICE(INTEL, 0x3b2b), board_ahci }, /* PCH RAID */ |
8e48b6b3 | 265 | { PCI_VDEVICE(INTEL, 0x3b2c), board_ahci }, /* PCH RAID */ |
c1f57d9b | 266 | { PCI_VDEVICE(INTEL, 0x3b2f), board_ahci }, /* PCH AHCI */ |
5623cab8 SH |
267 | { PCI_VDEVICE(INTEL, 0x1c02), board_ahci }, /* CPT AHCI */ |
268 | { PCI_VDEVICE(INTEL, 0x1c03), board_ahci }, /* CPT AHCI */ | |
269 | { PCI_VDEVICE(INTEL, 0x1c04), board_ahci }, /* CPT RAID */ | |
270 | { PCI_VDEVICE(INTEL, 0x1c05), board_ahci }, /* CPT RAID */ | |
271 | { PCI_VDEVICE(INTEL, 0x1c06), board_ahci }, /* CPT RAID */ | |
272 | { PCI_VDEVICE(INTEL, 0x1c07), board_ahci }, /* CPT RAID */ | |
992b3fb9 SH |
273 | { PCI_VDEVICE(INTEL, 0x1d02), board_ahci }, /* PBG AHCI */ |
274 | { PCI_VDEVICE(INTEL, 0x1d04), board_ahci }, /* PBG RAID */ | |
275 | { PCI_VDEVICE(INTEL, 0x1d06), board_ahci }, /* PBG RAID */ | |
64a3903d | 276 | { PCI_VDEVICE(INTEL, 0x2826), board_ahci }, /* PBG RAID */ |
a4a461a6 | 277 | { PCI_VDEVICE(INTEL, 0x2323), board_ahci }, /* DH89xxCC AHCI */ |
181e3cea SH |
278 | { PCI_VDEVICE(INTEL, 0x1e02), board_ahci }, /* Panther Point AHCI */ |
279 | { PCI_VDEVICE(INTEL, 0x1e03), board_ahci }, /* Panther Point AHCI */ | |
280 | { PCI_VDEVICE(INTEL, 0x1e04), board_ahci }, /* Panther Point RAID */ | |
281 | { PCI_VDEVICE(INTEL, 0x1e05), board_ahci }, /* Panther Point RAID */ | |
282 | { PCI_VDEVICE(INTEL, 0x1e06), board_ahci }, /* Panther Point RAID */ | |
283 | { PCI_VDEVICE(INTEL, 0x1e07), board_ahci }, /* Panther Point RAID */ | |
2cab7a4c | 284 | { PCI_VDEVICE(INTEL, 0x1e0e), board_ahci }, /* Panther Point RAID */ |
ea4ace66 SH |
285 | { PCI_VDEVICE(INTEL, 0x8c02), board_ahci }, /* Lynx Point AHCI */ |
286 | { PCI_VDEVICE(INTEL, 0x8c03), board_ahci }, /* Lynx Point AHCI */ | |
287 | { PCI_VDEVICE(INTEL, 0x8c04), board_ahci }, /* Lynx Point RAID */ | |
288 | { PCI_VDEVICE(INTEL, 0x8c05), board_ahci }, /* Lynx Point RAID */ | |
289 | { PCI_VDEVICE(INTEL, 0x8c06), board_ahci }, /* Lynx Point RAID */ | |
290 | { PCI_VDEVICE(INTEL, 0x8c07), board_ahci }, /* Lynx Point RAID */ | |
291 | { PCI_VDEVICE(INTEL, 0x8c0e), board_ahci }, /* Lynx Point RAID */ | |
292 | { PCI_VDEVICE(INTEL, 0x8c0f), board_ahci }, /* Lynx Point RAID */ | |
77b12bc9 JR |
293 | { PCI_VDEVICE(INTEL, 0x9c02), board_ahci }, /* Lynx Point-LP AHCI */ |
294 | { PCI_VDEVICE(INTEL, 0x9c03), board_ahci }, /* Lynx Point-LP AHCI */ | |
295 | { PCI_VDEVICE(INTEL, 0x9c04), board_ahci }, /* Lynx Point-LP RAID */ | |
296 | { PCI_VDEVICE(INTEL, 0x9c05), board_ahci }, /* Lynx Point-LP RAID */ | |
297 | { PCI_VDEVICE(INTEL, 0x9c06), board_ahci }, /* Lynx Point-LP RAID */ | |
298 | { PCI_VDEVICE(INTEL, 0x9c07), board_ahci }, /* Lynx Point-LP RAID */ | |
299 | { PCI_VDEVICE(INTEL, 0x9c0e), board_ahci }, /* Lynx Point-LP RAID */ | |
300 | { PCI_VDEVICE(INTEL, 0x9c0f), board_ahci }, /* Lynx Point-LP RAID */ | |
29e674dd SH |
301 | { PCI_VDEVICE(INTEL, 0x1f22), board_ahci }, /* Avoton AHCI */ |
302 | { PCI_VDEVICE(INTEL, 0x1f23), board_ahci }, /* Avoton AHCI */ | |
303 | { PCI_VDEVICE(INTEL, 0x1f24), board_ahci }, /* Avoton RAID */ | |
304 | { PCI_VDEVICE(INTEL, 0x1f25), board_ahci }, /* Avoton RAID */ | |
305 | { PCI_VDEVICE(INTEL, 0x1f26), board_ahci }, /* Avoton RAID */ | |
306 | { PCI_VDEVICE(INTEL, 0x1f27), board_ahci }, /* Avoton RAID */ | |
307 | { PCI_VDEVICE(INTEL, 0x1f2e), board_ahci }, /* Avoton RAID */ | |
308 | { PCI_VDEVICE(INTEL, 0x1f2f), board_ahci }, /* Avoton RAID */ | |
dbfe8ef5 DW |
309 | { PCI_VDEVICE(INTEL, 0x1f32), board_ahci_avn }, /* Avoton AHCI */ |
310 | { PCI_VDEVICE(INTEL, 0x1f33), board_ahci_avn }, /* Avoton AHCI */ | |
311 | { PCI_VDEVICE(INTEL, 0x1f34), board_ahci_avn }, /* Avoton RAID */ | |
312 | { PCI_VDEVICE(INTEL, 0x1f35), board_ahci_avn }, /* Avoton RAID */ | |
313 | { PCI_VDEVICE(INTEL, 0x1f36), board_ahci_avn }, /* Avoton RAID */ | |
314 | { PCI_VDEVICE(INTEL, 0x1f37), board_ahci_avn }, /* Avoton RAID */ | |
315 | { PCI_VDEVICE(INTEL, 0x1f3e), board_ahci_avn }, /* Avoton RAID */ | |
316 | { PCI_VDEVICE(INTEL, 0x1f3f), board_ahci_avn }, /* Avoton RAID */ | |
efda332c JR |
317 | { PCI_VDEVICE(INTEL, 0x2823), board_ahci }, /* Wellsburg RAID */ |
318 | { PCI_VDEVICE(INTEL, 0x2827), board_ahci }, /* Wellsburg RAID */ | |
151743fd JR |
319 | { PCI_VDEVICE(INTEL, 0x8d02), board_ahci }, /* Wellsburg AHCI */ |
320 | { PCI_VDEVICE(INTEL, 0x8d04), board_ahci }, /* Wellsburg RAID */ | |
321 | { PCI_VDEVICE(INTEL, 0x8d06), board_ahci }, /* Wellsburg RAID */ | |
322 | { PCI_VDEVICE(INTEL, 0x8d0e), board_ahci }, /* Wellsburg RAID */ | |
323 | { PCI_VDEVICE(INTEL, 0x8d62), board_ahci }, /* Wellsburg AHCI */ | |
324 | { PCI_VDEVICE(INTEL, 0x8d64), board_ahci }, /* Wellsburg RAID */ | |
325 | { PCI_VDEVICE(INTEL, 0x8d66), board_ahci }, /* Wellsburg RAID */ | |
326 | { PCI_VDEVICE(INTEL, 0x8d6e), board_ahci }, /* Wellsburg RAID */ | |
1cfc7df3 | 327 | { PCI_VDEVICE(INTEL, 0x23a3), board_ahci }, /* Coleto Creek AHCI */ |
9f961a5f JR |
328 | { PCI_VDEVICE(INTEL, 0x9c83), board_ahci }, /* Wildcat Point-LP AHCI */ |
329 | { PCI_VDEVICE(INTEL, 0x9c85), board_ahci }, /* Wildcat Point-LP RAID */ | |
330 | { PCI_VDEVICE(INTEL, 0x9c87), board_ahci }, /* Wildcat Point-LP RAID */ | |
331 | { PCI_VDEVICE(INTEL, 0x9c8f), board_ahci }, /* Wildcat Point-LP RAID */ | |
1b071a09 JR |
332 | { PCI_VDEVICE(INTEL, 0x8c82), board_ahci }, /* 9 Series AHCI */ |
333 | { PCI_VDEVICE(INTEL, 0x8c83), board_ahci }, /* 9 Series AHCI */ | |
334 | { PCI_VDEVICE(INTEL, 0x8c84), board_ahci }, /* 9 Series RAID */ | |
335 | { PCI_VDEVICE(INTEL, 0x8c85), board_ahci }, /* 9 Series RAID */ | |
336 | { PCI_VDEVICE(INTEL, 0x8c86), board_ahci }, /* 9 Series RAID */ | |
337 | { PCI_VDEVICE(INTEL, 0x8c87), board_ahci }, /* 9 Series RAID */ | |
338 | { PCI_VDEVICE(INTEL, 0x8c8e), board_ahci }, /* 9 Series RAID */ | |
339 | { PCI_VDEVICE(INTEL, 0x8c8f), board_ahci }, /* 9 Series RAID */ | |
249cd0a1 DR |
340 | { PCI_VDEVICE(INTEL, 0x9d03), board_ahci }, /* Sunrise Point-LP AHCI */ |
341 | { PCI_VDEVICE(INTEL, 0x9d05), board_ahci }, /* Sunrise Point-LP RAID */ | |
342 | { PCI_VDEVICE(INTEL, 0x9d07), board_ahci }, /* Sunrise Point-LP RAID */ | |
690000b9 | 343 | { PCI_VDEVICE(INTEL, 0xa103), board_ahci }, /* Sunrise Point-H AHCI */ |
690000b9 JR |
344 | { PCI_VDEVICE(INTEL, 0xa105), board_ahci }, /* Sunrise Point-H RAID */ |
345 | { PCI_VDEVICE(INTEL, 0xa107), board_ahci }, /* Sunrise Point-H RAID */ | |
346 | { PCI_VDEVICE(INTEL, 0xa10f), board_ahci }, /* Sunrise Point-H RAID */ | |
fe7fa31a | 347 | |
e34bb370 TH |
348 | /* JMicron 360/1/3/5/6, match class to avoid IDE function */ |
349 | { PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, | |
350 | PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci_ign_iferr }, | |
1fefb8fd BH |
351 | /* JMicron 362B and 362C have an AHCI function with IDE class code */ |
352 | { PCI_VDEVICE(JMICRON, 0x2362), board_ahci_ign_iferr }, | |
353 | { PCI_VDEVICE(JMICRON, 0x236f), board_ahci_ign_iferr }, | |
fe7fa31a JG |
354 | |
355 | /* ATI */ | |
c65ec1c2 | 356 | { PCI_VDEVICE(ATI, 0x4380), board_ahci_sb600 }, /* ATI SB600 */ |
e39fc8c9 SH |
357 | { PCI_VDEVICE(ATI, 0x4390), board_ahci_sb700 }, /* ATI SB700/800 */ |
358 | { PCI_VDEVICE(ATI, 0x4391), board_ahci_sb700 }, /* ATI SB700/800 */ | |
359 | { PCI_VDEVICE(ATI, 0x4392), board_ahci_sb700 }, /* ATI SB700/800 */ | |
360 | { PCI_VDEVICE(ATI, 0x4393), board_ahci_sb700 }, /* ATI SB700/800 */ | |
361 | { PCI_VDEVICE(ATI, 0x4394), board_ahci_sb700 }, /* ATI SB700/800 */ | |
362 | { PCI_VDEVICE(ATI, 0x4395), board_ahci_sb700 }, /* ATI SB700/800 */ | |
fe7fa31a | 363 | |
e2dd90b1 | 364 | /* AMD */ |
5deab536 | 365 | { PCI_VDEVICE(AMD, 0x7800), board_ahci }, /* AMD Hudson-2 */ |
fafe5c3d | 366 | { PCI_VDEVICE(AMD, 0x7900), board_ahci }, /* AMD CZ */ |
e2dd90b1 SH |
367 | /* AMD is using RAID class only for ahci controllers */ |
368 | { PCI_VENDOR_ID_AMD, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, | |
369 | PCI_CLASS_STORAGE_RAID << 8, 0xffffff, board_ahci }, | |
370 | ||
fe7fa31a | 371 | /* VIA */ |
54bb3a94 | 372 | { PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251 }, /* VIA VT8251 */ |
bf335542 | 373 | { PCI_VDEVICE(VIA, 0x6287), board_ahci_vt8251 }, /* VIA VT8251 */ |
fe7fa31a JG |
374 | |
375 | /* NVIDIA */ | |
e297d99e TH |
376 | { PCI_VDEVICE(NVIDIA, 0x044c), board_ahci_mcp65 }, /* MCP65 */ |
377 | { PCI_VDEVICE(NVIDIA, 0x044d), board_ahci_mcp65 }, /* MCP65 */ | |
378 | { PCI_VDEVICE(NVIDIA, 0x044e), board_ahci_mcp65 }, /* MCP65 */ | |
379 | { PCI_VDEVICE(NVIDIA, 0x044f), board_ahci_mcp65 }, /* MCP65 */ | |
380 | { PCI_VDEVICE(NVIDIA, 0x045c), board_ahci_mcp65 }, /* MCP65 */ | |
381 | { PCI_VDEVICE(NVIDIA, 0x045d), board_ahci_mcp65 }, /* MCP65 */ | |
382 | { PCI_VDEVICE(NVIDIA, 0x045e), board_ahci_mcp65 }, /* MCP65 */ | |
383 | { PCI_VDEVICE(NVIDIA, 0x045f), board_ahci_mcp65 }, /* MCP65 */ | |
441577ef TH |
384 | { PCI_VDEVICE(NVIDIA, 0x0550), board_ahci_mcp67 }, /* MCP67 */ |
385 | { PCI_VDEVICE(NVIDIA, 0x0551), board_ahci_mcp67 }, /* MCP67 */ | |
386 | { PCI_VDEVICE(NVIDIA, 0x0552), board_ahci_mcp67 }, /* MCP67 */ | |
387 | { PCI_VDEVICE(NVIDIA, 0x0553), board_ahci_mcp67 }, /* MCP67 */ | |
388 | { PCI_VDEVICE(NVIDIA, 0x0554), board_ahci_mcp67 }, /* MCP67 */ | |
389 | { PCI_VDEVICE(NVIDIA, 0x0555), board_ahci_mcp67 }, /* MCP67 */ | |
390 | { PCI_VDEVICE(NVIDIA, 0x0556), board_ahci_mcp67 }, /* MCP67 */ | |
391 | { PCI_VDEVICE(NVIDIA, 0x0557), board_ahci_mcp67 }, /* MCP67 */ | |
392 | { PCI_VDEVICE(NVIDIA, 0x0558), board_ahci_mcp67 }, /* MCP67 */ | |
393 | { PCI_VDEVICE(NVIDIA, 0x0559), board_ahci_mcp67 }, /* MCP67 */ | |
394 | { PCI_VDEVICE(NVIDIA, 0x055a), board_ahci_mcp67 }, /* MCP67 */ | |
395 | { PCI_VDEVICE(NVIDIA, 0x055b), board_ahci_mcp67 }, /* MCP67 */ | |
396 | { PCI_VDEVICE(NVIDIA, 0x0580), board_ahci_mcp_linux }, /* Linux ID */ | |
397 | { PCI_VDEVICE(NVIDIA, 0x0581), board_ahci_mcp_linux }, /* Linux ID */ | |
398 | { PCI_VDEVICE(NVIDIA, 0x0582), board_ahci_mcp_linux }, /* Linux ID */ | |
399 | { PCI_VDEVICE(NVIDIA, 0x0583), board_ahci_mcp_linux }, /* Linux ID */ | |
400 | { PCI_VDEVICE(NVIDIA, 0x0584), board_ahci_mcp_linux }, /* Linux ID */ | |
401 | { PCI_VDEVICE(NVIDIA, 0x0585), board_ahci_mcp_linux }, /* Linux ID */ | |
402 | { PCI_VDEVICE(NVIDIA, 0x0586), board_ahci_mcp_linux }, /* Linux ID */ | |
403 | { PCI_VDEVICE(NVIDIA, 0x0587), board_ahci_mcp_linux }, /* Linux ID */ | |
404 | { PCI_VDEVICE(NVIDIA, 0x0588), board_ahci_mcp_linux }, /* Linux ID */ | |
405 | { PCI_VDEVICE(NVIDIA, 0x0589), board_ahci_mcp_linux }, /* Linux ID */ | |
406 | { PCI_VDEVICE(NVIDIA, 0x058a), board_ahci_mcp_linux }, /* Linux ID */ | |
407 | { PCI_VDEVICE(NVIDIA, 0x058b), board_ahci_mcp_linux }, /* Linux ID */ | |
408 | { PCI_VDEVICE(NVIDIA, 0x058c), board_ahci_mcp_linux }, /* Linux ID */ | |
409 | { PCI_VDEVICE(NVIDIA, 0x058d), board_ahci_mcp_linux }, /* Linux ID */ | |
410 | { PCI_VDEVICE(NVIDIA, 0x058e), board_ahci_mcp_linux }, /* Linux ID */ | |
411 | { PCI_VDEVICE(NVIDIA, 0x058f), board_ahci_mcp_linux }, /* Linux ID */ | |
412 | { PCI_VDEVICE(NVIDIA, 0x07f0), board_ahci_mcp73 }, /* MCP73 */ | |
413 | { PCI_VDEVICE(NVIDIA, 0x07f1), board_ahci_mcp73 }, /* MCP73 */ | |
414 | { PCI_VDEVICE(NVIDIA, 0x07f2), board_ahci_mcp73 }, /* MCP73 */ | |
415 | { PCI_VDEVICE(NVIDIA, 0x07f3), board_ahci_mcp73 }, /* MCP73 */ | |
416 | { PCI_VDEVICE(NVIDIA, 0x07f4), board_ahci_mcp73 }, /* MCP73 */ | |
417 | { PCI_VDEVICE(NVIDIA, 0x07f5), board_ahci_mcp73 }, /* MCP73 */ | |
418 | { PCI_VDEVICE(NVIDIA, 0x07f6), board_ahci_mcp73 }, /* MCP73 */ | |
419 | { PCI_VDEVICE(NVIDIA, 0x07f7), board_ahci_mcp73 }, /* MCP73 */ | |
420 | { PCI_VDEVICE(NVIDIA, 0x07f8), board_ahci_mcp73 }, /* MCP73 */ | |
421 | { PCI_VDEVICE(NVIDIA, 0x07f9), board_ahci_mcp73 }, /* MCP73 */ | |
422 | { PCI_VDEVICE(NVIDIA, 0x07fa), board_ahci_mcp73 }, /* MCP73 */ | |
423 | { PCI_VDEVICE(NVIDIA, 0x07fb), board_ahci_mcp73 }, /* MCP73 */ | |
424 | { PCI_VDEVICE(NVIDIA, 0x0ad0), board_ahci_mcp77 }, /* MCP77 */ | |
425 | { PCI_VDEVICE(NVIDIA, 0x0ad1), board_ahci_mcp77 }, /* MCP77 */ | |
426 | { PCI_VDEVICE(NVIDIA, 0x0ad2), board_ahci_mcp77 }, /* MCP77 */ | |
427 | { PCI_VDEVICE(NVIDIA, 0x0ad3), board_ahci_mcp77 }, /* MCP77 */ | |
428 | { PCI_VDEVICE(NVIDIA, 0x0ad4), board_ahci_mcp77 }, /* MCP77 */ | |
429 | { PCI_VDEVICE(NVIDIA, 0x0ad5), board_ahci_mcp77 }, /* MCP77 */ | |
430 | { PCI_VDEVICE(NVIDIA, 0x0ad6), board_ahci_mcp77 }, /* MCP77 */ | |
431 | { PCI_VDEVICE(NVIDIA, 0x0ad7), board_ahci_mcp77 }, /* MCP77 */ | |
432 | { PCI_VDEVICE(NVIDIA, 0x0ad8), board_ahci_mcp77 }, /* MCP77 */ | |
433 | { PCI_VDEVICE(NVIDIA, 0x0ad9), board_ahci_mcp77 }, /* MCP77 */ | |
434 | { PCI_VDEVICE(NVIDIA, 0x0ada), board_ahci_mcp77 }, /* MCP77 */ | |
435 | { PCI_VDEVICE(NVIDIA, 0x0adb), board_ahci_mcp77 }, /* MCP77 */ | |
436 | { PCI_VDEVICE(NVIDIA, 0x0ab4), board_ahci_mcp79 }, /* MCP79 */ | |
437 | { PCI_VDEVICE(NVIDIA, 0x0ab5), board_ahci_mcp79 }, /* MCP79 */ | |
438 | { PCI_VDEVICE(NVIDIA, 0x0ab6), board_ahci_mcp79 }, /* MCP79 */ | |
439 | { PCI_VDEVICE(NVIDIA, 0x0ab7), board_ahci_mcp79 }, /* MCP79 */ | |
440 | { PCI_VDEVICE(NVIDIA, 0x0ab8), board_ahci_mcp79 }, /* MCP79 */ | |
441 | { PCI_VDEVICE(NVIDIA, 0x0ab9), board_ahci_mcp79 }, /* MCP79 */ | |
442 | { PCI_VDEVICE(NVIDIA, 0x0aba), board_ahci_mcp79 }, /* MCP79 */ | |
443 | { PCI_VDEVICE(NVIDIA, 0x0abb), board_ahci_mcp79 }, /* MCP79 */ | |
444 | { PCI_VDEVICE(NVIDIA, 0x0abc), board_ahci_mcp79 }, /* MCP79 */ | |
445 | { PCI_VDEVICE(NVIDIA, 0x0abd), board_ahci_mcp79 }, /* MCP79 */ | |
446 | { PCI_VDEVICE(NVIDIA, 0x0abe), board_ahci_mcp79 }, /* MCP79 */ | |
447 | { PCI_VDEVICE(NVIDIA, 0x0abf), board_ahci_mcp79 }, /* MCP79 */ | |
448 | { PCI_VDEVICE(NVIDIA, 0x0d84), board_ahci_mcp89 }, /* MCP89 */ | |
449 | { PCI_VDEVICE(NVIDIA, 0x0d85), board_ahci_mcp89 }, /* MCP89 */ | |
450 | { PCI_VDEVICE(NVIDIA, 0x0d86), board_ahci_mcp89 }, /* MCP89 */ | |
451 | { PCI_VDEVICE(NVIDIA, 0x0d87), board_ahci_mcp89 }, /* MCP89 */ | |
452 | { PCI_VDEVICE(NVIDIA, 0x0d88), board_ahci_mcp89 }, /* MCP89 */ | |
453 | { PCI_VDEVICE(NVIDIA, 0x0d89), board_ahci_mcp89 }, /* MCP89 */ | |
454 | { PCI_VDEVICE(NVIDIA, 0x0d8a), board_ahci_mcp89 }, /* MCP89 */ | |
455 | { PCI_VDEVICE(NVIDIA, 0x0d8b), board_ahci_mcp89 }, /* MCP89 */ | |
456 | { PCI_VDEVICE(NVIDIA, 0x0d8c), board_ahci_mcp89 }, /* MCP89 */ | |
457 | { PCI_VDEVICE(NVIDIA, 0x0d8d), board_ahci_mcp89 }, /* MCP89 */ | |
458 | { PCI_VDEVICE(NVIDIA, 0x0d8e), board_ahci_mcp89 }, /* MCP89 */ | |
459 | { PCI_VDEVICE(NVIDIA, 0x0d8f), board_ahci_mcp89 }, /* MCP89 */ | |
fe7fa31a | 460 | |
95916edd | 461 | /* SiS */ |
20e2de4a TH |
462 | { PCI_VDEVICE(SI, 0x1184), board_ahci }, /* SiS 966 */ |
463 | { PCI_VDEVICE(SI, 0x1185), board_ahci }, /* SiS 968 */ | |
464 | { PCI_VDEVICE(SI, 0x0186), board_ahci }, /* SiS 968 */ | |
95916edd | 465 | |
318893e1 AR |
466 | /* ST Microelectronics */ |
467 | { PCI_VDEVICE(STMICRO, 0xCC06), board_ahci }, /* ST ConneXt */ | |
468 | ||
cd70c266 JG |
469 | /* Marvell */ |
470 | { PCI_VDEVICE(MARVELL, 0x6145), board_ahci_mv }, /* 6145 */ | |
c40e7cb8 | 471 | { PCI_VDEVICE(MARVELL, 0x6121), board_ahci_mv }, /* 6121 */ |
69fd3157 | 472 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9123), |
10aca06c AH |
473 | .class = PCI_CLASS_STORAGE_SATA_AHCI, |
474 | .class_mask = 0xffffff, | |
5f173107 | 475 | .driver_data = board_ahci_yes_fbs }, /* 88se9128 */ |
69fd3157 | 476 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9125), |
467b41c6 | 477 | .driver_data = board_ahci_yes_fbs }, /* 88se9125 */ |
e098f5cb SG |
478 | { PCI_DEVICE_SUB(PCI_VENDOR_ID_MARVELL_EXT, 0x9178, |
479 | PCI_VENDOR_ID_MARVELL_EXT, 0x9170), | |
480 | .driver_data = board_ahci_yes_fbs }, /* 88se9170 */ | |
69fd3157 | 481 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x917a), |
642d8925 | 482 | .driver_data = board_ahci_yes_fbs }, /* 88se9172 */ |
fcce9a35 | 483 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9172), |
c5edfff9 MK |
484 | .driver_data = board_ahci_yes_fbs }, /* 88se9182 */ |
485 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9182), | |
fcce9a35 | 486 | .driver_data = board_ahci_yes_fbs }, /* 88se9172 */ |
69fd3157 | 487 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9192), |
17c60c6b | 488 | .driver_data = board_ahci_yes_fbs }, /* 88se9172 on some Gigabyte */ |
754a292f AS |
489 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a0), |
490 | .driver_data = board_ahci_yes_fbs }, | |
69fd3157 | 491 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a3), |
50be5e36 | 492 | .driver_data = board_ahci_yes_fbs }, |
6d5278a6 SB |
493 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9230), |
494 | .driver_data = board_ahci_yes_fbs }, | |
d2518365 JC |
495 | { PCI_DEVICE(PCI_VENDOR_ID_TTI, 0x0642), |
496 | .driver_data = board_ahci_yes_fbs }, | |
cd70c266 | 497 | |
c77a036b MN |
498 | /* Promise */ |
499 | { PCI_VDEVICE(PROMISE, 0x3f20), board_ahci }, /* PDC42819 */ | |
b32bfc06 | 500 | { PCI_VDEVICE(PROMISE, 0x3781), board_ahci }, /* FastTrak TX8660 ahci-mode */ |
c77a036b | 501 | |
c9703765 | 502 | /* Asmedia */ |
7b4f6eca AC |
503 | { PCI_VDEVICE(ASMEDIA, 0x0601), board_ahci }, /* ASM1060 */ |
504 | { PCI_VDEVICE(ASMEDIA, 0x0602), board_ahci }, /* ASM1060 */ | |
505 | { PCI_VDEVICE(ASMEDIA, 0x0611), board_ahci }, /* ASM1061 */ | |
506 | { PCI_VDEVICE(ASMEDIA, 0x0612), board_ahci }, /* ASM1062 */ | |
c9703765 | 507 | |
67809f85 | 508 | /* |
66a7cbc3 TH |
509 | * Samsung SSDs found on some macbooks. NCQ times out if MSI is |
510 | * enabled. https://bugzilla.kernel.org/show_bug.cgi?id=60731 | |
67809f85 | 511 | */ |
66a7cbc3 | 512 | { PCI_VDEVICE(SAMSUNG, 0x1600), board_ahci_nomsi }, |
2b21ef0a | 513 | { PCI_VDEVICE(SAMSUNG, 0xa800), board_ahci_nomsi }, |
67809f85 | 514 | |
7f9c9f8e HD |
515 | /* Enmotus */ |
516 | { PCI_DEVICE(0x1c44, 0x8000), board_ahci }, | |
517 | ||
415ae2b5 JG |
518 | /* Generic, PCI class code for AHCI */ |
519 | { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, | |
c9f89475 | 520 | PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci }, |
415ae2b5 | 521 | |
1da177e4 LT |
522 | { } /* terminate list */ |
523 | }; | |
524 | ||
525 | ||
526 | static struct pci_driver ahci_pci_driver = { | |
527 | .name = DRV_NAME, | |
528 | .id_table = ahci_pci_tbl, | |
529 | .probe = ahci_init_one, | |
24dc5f33 | 530 | .remove = ata_pci_remove_one, |
438ac6d5 | 531 | #ifdef CONFIG_PM |
c1332875 | 532 | .suspend = ahci_pci_device_suspend, |
365cfa1e AV |
533 | .resume = ahci_pci_device_resume, |
534 | #endif | |
535 | }; | |
1da177e4 | 536 | |
365cfa1e AV |
537 | #if defined(CONFIG_PATA_MARVELL) || defined(CONFIG_PATA_MARVELL_MODULE) |
538 | static int marvell_enable; | |
539 | #else | |
540 | static int marvell_enable = 1; | |
541 | #endif | |
542 | module_param(marvell_enable, int, 0644); | |
543 | MODULE_PARM_DESC(marvell_enable, "Marvell SATA via AHCI (1 = enabled)"); | |
d28f87aa | 544 | |
1da177e4 | 545 | |
365cfa1e AV |
546 | static void ahci_pci_save_initial_config(struct pci_dev *pdev, |
547 | struct ahci_host_priv *hpriv) | |
548 | { | |
365cfa1e AV |
549 | if (pdev->vendor == PCI_VENDOR_ID_JMICRON && pdev->device == 0x2361) { |
550 | dev_info(&pdev->dev, "JMB361 has only one port\n"); | |
9a23c1d6 | 551 | hpriv->force_port_map = 1; |
1da177e4 LT |
552 | } |
553 | ||
365cfa1e AV |
554 | /* |
555 | * Temporary Marvell 6145 hack: PATA port presence | |
556 | * is asserted through the standard AHCI port | |
557 | * presence register, as bit 4 (counting from 0) | |
d28f87aa | 558 | */ |
365cfa1e AV |
559 | if (hpriv->flags & AHCI_HFLAG_MV_PATA) { |
560 | if (pdev->device == 0x6121) | |
9a23c1d6 | 561 | hpriv->mask_port_map = 0x3; |
365cfa1e | 562 | else |
9a23c1d6 | 563 | hpriv->mask_port_map = 0xf; |
365cfa1e AV |
564 | dev_info(&pdev->dev, |
565 | "Disabling your PATA port. Use the boot option 'ahci.marvell_enable=0' to avoid this.\n"); | |
566 | } | |
1da177e4 | 567 | |
725c7b57 | 568 | ahci_save_initial_config(&pdev->dev, hpriv); |
1da177e4 LT |
569 | } |
570 | ||
365cfa1e | 571 | static int ahci_pci_reset_controller(struct ata_host *host) |
1da177e4 | 572 | { |
365cfa1e | 573 | struct pci_dev *pdev = to_pci_dev(host->dev); |
7d50b60b | 574 | |
365cfa1e | 575 | ahci_reset_controller(host); |
1da177e4 | 576 | |
365cfa1e AV |
577 | if (pdev->vendor == PCI_VENDOR_ID_INTEL) { |
578 | struct ahci_host_priv *hpriv = host->private_data; | |
579 | u16 tmp16; | |
d6ef3153 | 580 | |
365cfa1e AV |
581 | /* configure PCS */ |
582 | pci_read_config_word(pdev, 0x92, &tmp16); | |
583 | if ((tmp16 & hpriv->port_map) != hpriv->port_map) { | |
584 | tmp16 |= hpriv->port_map; | |
585 | pci_write_config_word(pdev, 0x92, tmp16); | |
586 | } | |
d6ef3153 SH |
587 | } |
588 | ||
1da177e4 LT |
589 | return 0; |
590 | } | |
591 | ||
365cfa1e | 592 | static void ahci_pci_init_controller(struct ata_host *host) |
78cd52d0 | 593 | { |
365cfa1e AV |
594 | struct ahci_host_priv *hpriv = host->private_data; |
595 | struct pci_dev *pdev = to_pci_dev(host->dev); | |
596 | void __iomem *port_mmio; | |
78cd52d0 | 597 | u32 tmp; |
365cfa1e | 598 | int mv; |
78cd52d0 | 599 | |
365cfa1e AV |
600 | if (hpriv->flags & AHCI_HFLAG_MV_PATA) { |
601 | if (pdev->device == 0x6121) | |
602 | mv = 2; | |
603 | else | |
604 | mv = 4; | |
605 | port_mmio = __ahci_port_base(host, mv); | |
78cd52d0 | 606 | |
365cfa1e | 607 | writel(0, port_mmio + PORT_IRQ_MASK); |
78cd52d0 | 608 | |
365cfa1e AV |
609 | /* clear port IRQ */ |
610 | tmp = readl(port_mmio + PORT_IRQ_STAT); | |
611 | VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp); | |
612 | if (tmp) | |
613 | writel(tmp, port_mmio + PORT_IRQ_STAT); | |
78cd52d0 TH |
614 | } |
615 | ||
365cfa1e | 616 | ahci_init_controller(host); |
edc93052 TH |
617 | } |
618 | ||
365cfa1e AV |
619 | static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class, |
620 | unsigned long deadline) | |
d6ef3153 | 621 | { |
365cfa1e | 622 | struct ata_port *ap = link->ap; |
039ece38 | 623 | struct ahci_host_priv *hpriv = ap->host->private_data; |
365cfa1e | 624 | bool online; |
d6ef3153 SH |
625 | int rc; |
626 | ||
365cfa1e | 627 | DPRINTK("ENTER\n"); |
d6ef3153 | 628 | |
365cfa1e | 629 | ahci_stop_engine(ap); |
d6ef3153 | 630 | |
365cfa1e AV |
631 | rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context), |
632 | deadline, &online, NULL); | |
d6ef3153 | 633 | |
039ece38 | 634 | hpriv->start_engine(ap); |
d6ef3153 | 635 | |
365cfa1e | 636 | DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class); |
d6ef3153 | 637 | |
365cfa1e AV |
638 | /* vt8251 doesn't clear BSY on signature FIS reception, |
639 | * request follow-up softreset. | |
640 | */ | |
641 | return online ? -EAGAIN : rc; | |
7d50b60b TH |
642 | } |
643 | ||
365cfa1e AV |
644 | static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class, |
645 | unsigned long deadline) | |
7d50b60b | 646 | { |
365cfa1e | 647 | struct ata_port *ap = link->ap; |
1c954a4d | 648 | struct ahci_port_priv *pp = ap->private_data; |
039ece38 | 649 | struct ahci_host_priv *hpriv = ap->host->private_data; |
365cfa1e AV |
650 | u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG; |
651 | struct ata_taskfile tf; | |
652 | bool online; | |
653 | int rc; | |
7d50b60b | 654 | |
365cfa1e | 655 | ahci_stop_engine(ap); |
028a2596 | 656 | |
365cfa1e AV |
657 | /* clear D2H reception area to properly wait for D2H FIS */ |
658 | ata_tf_init(link->device, &tf); | |
9bbb1b0e | 659 | tf.command = ATA_BUSY; |
365cfa1e | 660 | ata_tf_to_fis(&tf, 0, 0, d2h_fis); |
7d50b60b | 661 | |
365cfa1e AV |
662 | rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context), |
663 | deadline, &online, NULL); | |
028a2596 | 664 | |
039ece38 | 665 | hpriv->start_engine(ap); |
c1332875 | 666 | |
365cfa1e AV |
667 | /* The pseudo configuration device on SIMG4726 attached to |
668 | * ASUS P5W-DH Deluxe doesn't send signature FIS after | |
669 | * hardreset if no device is attached to the first downstream | |
670 | * port && the pseudo device locks up on SRST w/ PMP==0. To | |
671 | * work around this, wait for !BSY only briefly. If BSY isn't | |
672 | * cleared, perform CLO and proceed to IDENTIFY (achieved by | |
673 | * ATA_LFLAG_NO_SRST and ATA_LFLAG_ASSUME_ATA). | |
674 | * | |
675 | * Wait for two seconds. Devices attached to downstream port | |
676 | * which can't process the following IDENTIFY after this will | |
677 | * have to be reset again. For most cases, this should | |
678 | * suffice while making probing snappish enough. | |
679 | */ | |
680 | if (online) { | |
681 | rc = ata_wait_after_reset(link, jiffies + 2 * HZ, | |
682 | ahci_check_ready); | |
683 | if (rc) | |
684 | ahci_kick_engine(ap); | |
c1332875 | 685 | } |
c1332875 TH |
686 | return rc; |
687 | } | |
688 | ||
dbfe8ef5 DW |
689 | /* |
690 | * ahci_avn_hardreset - attempt more aggressive recovery of Avoton ports. | |
691 | * | |
692 | * It has been observed with some SSDs that the timing of events in the | |
693 | * link synchronization phase can leave the port in a state that can not | |
694 | * be recovered by a SATA-hard-reset alone. The failing signature is | |
695 | * SStatus.DET stuck at 1 ("Device presence detected but Phy | |
696 | * communication not established"). It was found that unloading and | |
697 | * reloading the driver when this problem occurs allows the drive | |
698 | * connection to be recovered (DET advanced to 0x3). The critical | |
699 | * component of reloading the driver is that the port state machines are | |
700 | * reset by bouncing "port enable" in the AHCI PCS configuration | |
701 | * register. So, reproduce that effect by bouncing a port whenever we | |
702 | * see DET==1 after a reset. | |
703 | */ | |
704 | static int ahci_avn_hardreset(struct ata_link *link, unsigned int *class, | |
705 | unsigned long deadline) | |
706 | { | |
707 | const unsigned long *timing = sata_ehc_deb_timing(&link->eh_context); | |
708 | struct ata_port *ap = link->ap; | |
709 | struct ahci_port_priv *pp = ap->private_data; | |
710 | struct ahci_host_priv *hpriv = ap->host->private_data; | |
711 | u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG; | |
712 | unsigned long tmo = deadline - jiffies; | |
713 | struct ata_taskfile tf; | |
714 | bool online; | |
715 | int rc, i; | |
716 | ||
717 | DPRINTK("ENTER\n"); | |
718 | ||
719 | ahci_stop_engine(ap); | |
720 | ||
721 | for (i = 0; i < 2; i++) { | |
722 | u16 val; | |
723 | u32 sstatus; | |
724 | int port = ap->port_no; | |
725 | struct ata_host *host = ap->host; | |
726 | struct pci_dev *pdev = to_pci_dev(host->dev); | |
727 | ||
728 | /* clear D2H reception area to properly wait for D2H FIS */ | |
729 | ata_tf_init(link->device, &tf); | |
730 | tf.command = ATA_BUSY; | |
731 | ata_tf_to_fis(&tf, 0, 0, d2h_fis); | |
732 | ||
733 | rc = sata_link_hardreset(link, timing, deadline, &online, | |
734 | ahci_check_ready); | |
735 | ||
736 | if (sata_scr_read(link, SCR_STATUS, &sstatus) != 0 || | |
737 | (sstatus & 0xf) != 1) | |
738 | break; | |
739 | ||
740 | ata_link_printk(link, KERN_INFO, "avn bounce port%d\n", | |
741 | port); | |
742 | ||
743 | pci_read_config_word(pdev, 0x92, &val); | |
744 | val &= ~(1 << port); | |
745 | pci_write_config_word(pdev, 0x92, val); | |
746 | ata_msleep(ap, 1000); | |
747 | val |= 1 << port; | |
748 | pci_write_config_word(pdev, 0x92, val); | |
749 | deadline += tmo; | |
750 | } | |
751 | ||
752 | hpriv->start_engine(ap); | |
753 | ||
754 | if (online) | |
755 | *class = ahci_dev_classify(ap); | |
756 | ||
757 | DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class); | |
758 | return rc; | |
759 | } | |
760 | ||
761 | ||
365cfa1e | 762 | #ifdef CONFIG_PM |
c1332875 TH |
763 | static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg) |
764 | { | |
0a86e1c8 | 765 | struct ata_host *host = pci_get_drvdata(pdev); |
9b10ae86 | 766 | struct ahci_host_priv *hpriv = host->private_data; |
d8993349 | 767 | void __iomem *mmio = hpriv->mmio; |
c1332875 TH |
768 | u32 ctl; |
769 | ||
9b10ae86 TH |
770 | if (mesg.event & PM_EVENT_SUSPEND && |
771 | hpriv->flags & AHCI_HFLAG_NO_SUSPEND) { | |
a44fec1f JP |
772 | dev_err(&pdev->dev, |
773 | "BIOS update required for suspend/resume\n"); | |
9b10ae86 TH |
774 | return -EIO; |
775 | } | |
776 | ||
3a2d5b70 | 777 | if (mesg.event & PM_EVENT_SLEEP) { |
c1332875 TH |
778 | /* AHCI spec rev1.1 section 8.3.3: |
779 | * Software must disable interrupts prior to requesting a | |
780 | * transition of the HBA to D3 state. | |
781 | */ | |
782 | ctl = readl(mmio + HOST_CTL); | |
783 | ctl &= ~HOST_IRQ_EN; | |
784 | writel(ctl, mmio + HOST_CTL); | |
785 | readl(mmio + HOST_CTL); /* flush */ | |
786 | } | |
787 | ||
788 | return ata_pci_device_suspend(pdev, mesg); | |
789 | } | |
790 | ||
791 | static int ahci_pci_device_resume(struct pci_dev *pdev) | |
792 | { | |
0a86e1c8 | 793 | struct ata_host *host = pci_get_drvdata(pdev); |
c1332875 TH |
794 | int rc; |
795 | ||
553c4aa6 TH |
796 | rc = ata_pci_device_do_resume(pdev); |
797 | if (rc) | |
798 | return rc; | |
c1332875 | 799 | |
cb85696d JL |
800 | /* Apple BIOS helpfully mangles the registers on resume */ |
801 | if (is_mcp89_apple(pdev)) | |
802 | ahci_mcp89_apple_enable(pdev); | |
803 | ||
c1332875 | 804 | if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) { |
3303040d | 805 | rc = ahci_pci_reset_controller(host); |
c1332875 TH |
806 | if (rc) |
807 | return rc; | |
808 | ||
781d6550 | 809 | ahci_pci_init_controller(host); |
c1332875 TH |
810 | } |
811 | ||
cca3974e | 812 | ata_host_resume(host); |
c1332875 TH |
813 | |
814 | return 0; | |
815 | } | |
438ac6d5 | 816 | #endif |
c1332875 | 817 | |
4447d351 | 818 | static int ahci_configure_dma_masks(struct pci_dev *pdev, int using_dac) |
1da177e4 | 819 | { |
1da177e4 | 820 | int rc; |
1da177e4 | 821 | |
318893e1 AR |
822 | /* |
823 | * If the device fixup already set the dma_mask to some non-standard | |
824 | * value, don't extend it here. This happens on STA2X11, for example. | |
825 | */ | |
826 | if (pdev->dma_mask && pdev->dma_mask < DMA_BIT_MASK(32)) | |
827 | return 0; | |
828 | ||
1da177e4 | 829 | if (using_dac && |
c54c719b QL |
830 | !dma_set_mask(&pdev->dev, DMA_BIT_MASK(64))) { |
831 | rc = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64)); | |
1da177e4 | 832 | if (rc) { |
c54c719b | 833 | rc = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32)); |
1da177e4 | 834 | if (rc) { |
a44fec1f JP |
835 | dev_err(&pdev->dev, |
836 | "64-bit DMA enable failed\n"); | |
1da177e4 LT |
837 | return rc; |
838 | } | |
839 | } | |
1da177e4 | 840 | } else { |
c54c719b | 841 | rc = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32)); |
1da177e4 | 842 | if (rc) { |
a44fec1f | 843 | dev_err(&pdev->dev, "32-bit DMA enable failed\n"); |
1da177e4 LT |
844 | return rc; |
845 | } | |
c54c719b | 846 | rc = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32)); |
1da177e4 | 847 | if (rc) { |
a44fec1f JP |
848 | dev_err(&pdev->dev, |
849 | "32-bit consistent DMA enable failed\n"); | |
1da177e4 LT |
850 | return rc; |
851 | } | |
852 | } | |
1da177e4 LT |
853 | return 0; |
854 | } | |
855 | ||
439fcaec AV |
856 | static void ahci_pci_print_info(struct ata_host *host) |
857 | { | |
858 | struct pci_dev *pdev = to_pci_dev(host->dev); | |
859 | u16 cc; | |
860 | const char *scc_s; | |
861 | ||
862 | pci_read_config_word(pdev, 0x0a, &cc); | |
863 | if (cc == PCI_CLASS_STORAGE_IDE) | |
864 | scc_s = "IDE"; | |
865 | else if (cc == PCI_CLASS_STORAGE_SATA) | |
866 | scc_s = "SATA"; | |
867 | else if (cc == PCI_CLASS_STORAGE_RAID) | |
868 | scc_s = "RAID"; | |
869 | else | |
870 | scc_s = "unknown"; | |
871 | ||
872 | ahci_print_info(host, scc_s); | |
873 | } | |
874 | ||
edc93052 TH |
875 | /* On ASUS P5W DH Deluxe, the second port of PCI device 00:1f.2 is |
876 | * hardwired to on-board SIMG 4726. The chipset is ICH8 and doesn't | |
877 | * support PMP and the 4726 either directly exports the device | |
878 | * attached to the first downstream port or acts as a hardware storage | |
879 | * controller and emulate a single ATA device (can be RAID 0/1 or some | |
880 | * other configuration). | |
881 | * | |
882 | * When there's no device attached to the first downstream port of the | |
883 | * 4726, "Config Disk" appears, which is a pseudo ATA device to | |
884 | * configure the 4726. However, ATA emulation of the device is very | |
885 | * lame. It doesn't send signature D2H Reg FIS after the initial | |
886 | * hardreset, pukes on SRST w/ PMP==0 and has bunch of other issues. | |
887 | * | |
888 | * The following function works around the problem by always using | |
889 | * hardreset on the port and not depending on receiving signature FIS | |
890 | * afterward. If signature FIS isn't received soon, ATA class is | |
891 | * assumed without follow-up softreset. | |
892 | */ | |
893 | static void ahci_p5wdh_workaround(struct ata_host *host) | |
894 | { | |
1bd06867 | 895 | static const struct dmi_system_id sysids[] = { |
edc93052 TH |
896 | { |
897 | .ident = "P5W DH Deluxe", | |
898 | .matches = { | |
899 | DMI_MATCH(DMI_SYS_VENDOR, | |
900 | "ASUSTEK COMPUTER INC"), | |
901 | DMI_MATCH(DMI_PRODUCT_NAME, "P5W DH Deluxe"), | |
902 | }, | |
903 | }, | |
904 | { } | |
905 | }; | |
906 | struct pci_dev *pdev = to_pci_dev(host->dev); | |
907 | ||
908 | if (pdev->bus->number == 0 && pdev->devfn == PCI_DEVFN(0x1f, 2) && | |
909 | dmi_check_system(sysids)) { | |
910 | struct ata_port *ap = host->ports[1]; | |
911 | ||
a44fec1f JP |
912 | dev_info(&pdev->dev, |
913 | "enabling ASUS P5W DH Deluxe on-board SIMG4726 workaround\n"); | |
edc93052 TH |
914 | |
915 | ap->ops = &ahci_p5wdh_ops; | |
916 | ap->link.flags |= ATA_LFLAG_NO_SRST | ATA_LFLAG_ASSUME_ATA; | |
917 | } | |
918 | } | |
919 | ||
cb85696d JL |
920 | /* |
921 | * Macbook7,1 firmware forcibly disables MCP89 AHCI and changes PCI ID when | |
922 | * booting in BIOS compatibility mode. We restore the registers but not ID. | |
923 | */ | |
924 | static void ahci_mcp89_apple_enable(struct pci_dev *pdev) | |
925 | { | |
926 | u32 val; | |
927 | ||
928 | printk(KERN_INFO "ahci: enabling MCP89 AHCI mode\n"); | |
929 | ||
930 | pci_read_config_dword(pdev, 0xf8, &val); | |
931 | val |= 1 << 0x1b; | |
932 | /* the following changes the device ID, but appears not to affect function */ | |
933 | /* val = (val & ~0xf0000000) | 0x80000000; */ | |
934 | pci_write_config_dword(pdev, 0xf8, val); | |
935 | ||
936 | pci_read_config_dword(pdev, 0x54c, &val); | |
937 | val |= 1 << 0xc; | |
938 | pci_write_config_dword(pdev, 0x54c, val); | |
939 | ||
940 | pci_read_config_dword(pdev, 0x4a4, &val); | |
941 | val &= 0xff; | |
942 | val |= 0x01060100; | |
943 | pci_write_config_dword(pdev, 0x4a4, val); | |
944 | ||
945 | pci_read_config_dword(pdev, 0x54c, &val); | |
946 | val &= ~(1 << 0xc); | |
947 | pci_write_config_dword(pdev, 0x54c, val); | |
948 | ||
949 | pci_read_config_dword(pdev, 0xf8, &val); | |
950 | val &= ~(1 << 0x1b); | |
951 | pci_write_config_dword(pdev, 0xf8, val); | |
952 | } | |
953 | ||
954 | static bool is_mcp89_apple(struct pci_dev *pdev) | |
955 | { | |
956 | return pdev->vendor == PCI_VENDOR_ID_NVIDIA && | |
957 | pdev->device == PCI_DEVICE_ID_NVIDIA_NFORCE_MCP89_SATA && | |
958 | pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE && | |
959 | pdev->subsystem_device == 0xcb89; | |
960 | } | |
961 | ||
2fcad9d2 TH |
962 | /* only some SB600 ahci controllers can do 64bit DMA */ |
963 | static bool ahci_sb600_enable_64bit(struct pci_dev *pdev) | |
58a09b38 SH |
964 | { |
965 | static const struct dmi_system_id sysids[] = { | |
03d783bf TH |
966 | /* |
967 | * The oldest version known to be broken is 0901 and | |
968 | * working is 1501 which was released on 2007-10-26. | |
2fcad9d2 TH |
969 | * Enable 64bit DMA on 1501 and anything newer. |
970 | * | |
03d783bf TH |
971 | * Please read bko#9412 for more info. |
972 | */ | |
58a09b38 SH |
973 | { |
974 | .ident = "ASUS M2A-VM", | |
975 | .matches = { | |
976 | DMI_MATCH(DMI_BOARD_VENDOR, | |
977 | "ASUSTeK Computer INC."), | |
978 | DMI_MATCH(DMI_BOARD_NAME, "M2A-VM"), | |
979 | }, | |
03d783bf | 980 | .driver_data = "20071026", /* yyyymmdd */ |
58a09b38 | 981 | }, |
e65cc194 MN |
982 | /* |
983 | * All BIOS versions for the MSI K9A2 Platinum (MS-7376) | |
984 | * support 64bit DMA. | |
985 | * | |
986 | * BIOS versions earlier than 1.5 had the Manufacturer DMI | |
987 | * fields as "MICRO-STAR INTERANTIONAL CO.,LTD". | |
988 | * This spelling mistake was fixed in BIOS version 1.5, so | |
989 | * 1.5 and later have the Manufacturer as | |
990 | * "MICRO-STAR INTERNATIONAL CO.,LTD". | |
991 | * So try to match on DMI_BOARD_VENDOR of "MICRO-STAR INTER". | |
992 | * | |
993 | * BIOS versions earlier than 1.9 had a Board Product Name | |
994 | * DMI field of "MS-7376". This was changed to be | |
995 | * "K9A2 Platinum (MS-7376)" in version 1.9, but we can still | |
996 | * match on DMI_BOARD_NAME of "MS-7376". | |
997 | */ | |
998 | { | |
999 | .ident = "MSI K9A2 Platinum", | |
1000 | .matches = { | |
1001 | DMI_MATCH(DMI_BOARD_VENDOR, | |
1002 | "MICRO-STAR INTER"), | |
1003 | DMI_MATCH(DMI_BOARD_NAME, "MS-7376"), | |
1004 | }, | |
1005 | }, | |
ff0173c1 MN |
1006 | /* |
1007 | * All BIOS versions for the MSI K9AGM2 (MS-7327) support | |
1008 | * 64bit DMA. | |
1009 | * | |
1010 | * This board also had the typo mentioned above in the | |
1011 | * Manufacturer DMI field (fixed in BIOS version 1.5), so | |
1012 | * match on DMI_BOARD_VENDOR of "MICRO-STAR INTER" again. | |
1013 | */ | |
1014 | { | |
1015 | .ident = "MSI K9AGM2", | |
1016 | .matches = { | |
1017 | DMI_MATCH(DMI_BOARD_VENDOR, | |
1018 | "MICRO-STAR INTER"), | |
1019 | DMI_MATCH(DMI_BOARD_NAME, "MS-7327"), | |
1020 | }, | |
1021 | }, | |
3c4aa91f MN |
1022 | /* |
1023 | * All BIOS versions for the Asus M3A support 64bit DMA. | |
1024 | * (all release versions from 0301 to 1206 were tested) | |
1025 | */ | |
1026 | { | |
1027 | .ident = "ASUS M3A", | |
1028 | .matches = { | |
1029 | DMI_MATCH(DMI_BOARD_VENDOR, | |
1030 | "ASUSTeK Computer INC."), | |
1031 | DMI_MATCH(DMI_BOARD_NAME, "M3A"), | |
1032 | }, | |
1033 | }, | |
58a09b38 SH |
1034 | { } |
1035 | }; | |
03d783bf | 1036 | const struct dmi_system_id *match; |
2fcad9d2 TH |
1037 | int year, month, date; |
1038 | char buf[9]; | |
58a09b38 | 1039 | |
03d783bf | 1040 | match = dmi_first_match(sysids); |
58a09b38 | 1041 | if (pdev->bus->number != 0 || pdev->devfn != PCI_DEVFN(0x12, 0) || |
03d783bf | 1042 | !match) |
58a09b38 SH |
1043 | return false; |
1044 | ||
e65cc194 MN |
1045 | if (!match->driver_data) |
1046 | goto enable_64bit; | |
1047 | ||
2fcad9d2 TH |
1048 | dmi_get_date(DMI_BIOS_DATE, &year, &month, &date); |
1049 | snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date); | |
03d783bf | 1050 | |
e65cc194 MN |
1051 | if (strcmp(buf, match->driver_data) >= 0) |
1052 | goto enable_64bit; | |
1053 | else { | |
a44fec1f JP |
1054 | dev_warn(&pdev->dev, |
1055 | "%s: BIOS too old, forcing 32bit DMA, update BIOS\n", | |
1056 | match->ident); | |
2fcad9d2 TH |
1057 | return false; |
1058 | } | |
e65cc194 MN |
1059 | |
1060 | enable_64bit: | |
a44fec1f | 1061 | dev_warn(&pdev->dev, "%s: enabling 64bit DMA\n", match->ident); |
e65cc194 | 1062 | return true; |
58a09b38 SH |
1063 | } |
1064 | ||
1fd68434 RW |
1065 | static bool ahci_broken_system_poweroff(struct pci_dev *pdev) |
1066 | { | |
1067 | static const struct dmi_system_id broken_systems[] = { | |
1068 | { | |
1069 | .ident = "HP Compaq nx6310", | |
1070 | .matches = { | |
1071 | DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"), | |
1072 | DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq nx6310"), | |
1073 | }, | |
1074 | /* PCI slot number of the controller */ | |
1075 | .driver_data = (void *)0x1FUL, | |
1076 | }, | |
d2f9c061 MR |
1077 | { |
1078 | .ident = "HP Compaq 6720s", | |
1079 | .matches = { | |
1080 | DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"), | |
1081 | DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq 6720s"), | |
1082 | }, | |
1083 | /* PCI slot number of the controller */ | |
1084 | .driver_data = (void *)0x1FUL, | |
1085 | }, | |
1fd68434 RW |
1086 | |
1087 | { } /* terminate list */ | |
1088 | }; | |
1089 | const struct dmi_system_id *dmi = dmi_first_match(broken_systems); | |
1090 | ||
1091 | if (dmi) { | |
1092 | unsigned long slot = (unsigned long)dmi->driver_data; | |
1093 | /* apply the quirk only to on-board controllers */ | |
1094 | return slot == PCI_SLOT(pdev->devfn); | |
1095 | } | |
1096 | ||
1097 | return false; | |
1098 | } | |
1099 | ||
9b10ae86 TH |
1100 | static bool ahci_broken_suspend(struct pci_dev *pdev) |
1101 | { | |
1102 | static const struct dmi_system_id sysids[] = { | |
1103 | /* | |
1104 | * On HP dv[4-6] and HDX18 with earlier BIOSen, link | |
1105 | * to the harddisk doesn't become online after | |
1106 | * resuming from STR. Warn and fail suspend. | |
9deb3431 TH |
1107 | * |
1108 | * http://bugzilla.kernel.org/show_bug.cgi?id=12276 | |
1109 | * | |
1110 | * Use dates instead of versions to match as HP is | |
1111 | * apparently recycling both product and version | |
1112 | * strings. | |
1113 | * | |
1114 | * http://bugzilla.kernel.org/show_bug.cgi?id=15462 | |
9b10ae86 TH |
1115 | */ |
1116 | { | |
1117 | .ident = "dv4", | |
1118 | .matches = { | |
1119 | DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"), | |
1120 | DMI_MATCH(DMI_PRODUCT_NAME, | |
1121 | "HP Pavilion dv4 Notebook PC"), | |
1122 | }, | |
9deb3431 | 1123 | .driver_data = "20090105", /* F.30 */ |
9b10ae86 TH |
1124 | }, |
1125 | { | |
1126 | .ident = "dv5", | |
1127 | .matches = { | |
1128 | DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"), | |
1129 | DMI_MATCH(DMI_PRODUCT_NAME, | |
1130 | "HP Pavilion dv5 Notebook PC"), | |
1131 | }, | |
9deb3431 | 1132 | .driver_data = "20090506", /* F.16 */ |
9b10ae86 TH |
1133 | }, |
1134 | { | |
1135 | .ident = "dv6", | |
1136 | .matches = { | |
1137 | DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"), | |
1138 | DMI_MATCH(DMI_PRODUCT_NAME, | |
1139 | "HP Pavilion dv6 Notebook PC"), | |
1140 | }, | |
9deb3431 | 1141 | .driver_data = "20090423", /* F.21 */ |
9b10ae86 TH |
1142 | }, |
1143 | { | |
1144 | .ident = "HDX18", | |
1145 | .matches = { | |
1146 | DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"), | |
1147 | DMI_MATCH(DMI_PRODUCT_NAME, | |
1148 | "HP HDX18 Notebook PC"), | |
1149 | }, | |
9deb3431 | 1150 | .driver_data = "20090430", /* F.23 */ |
9b10ae86 | 1151 | }, |
cedc9bf9 TH |
1152 | /* |
1153 | * Acer eMachines G725 has the same problem. BIOS | |
1154 | * V1.03 is known to be broken. V3.04 is known to | |
25985edc | 1155 | * work. Between, there are V1.06, V2.06 and V3.03 |
cedc9bf9 TH |
1156 | * that we don't have much idea about. For now, |
1157 | * blacklist anything older than V3.04. | |
9deb3431 TH |
1158 | * |
1159 | * http://bugzilla.kernel.org/show_bug.cgi?id=15104 | |
cedc9bf9 TH |
1160 | */ |
1161 | { | |
1162 | .ident = "G725", | |
1163 | .matches = { | |
1164 | DMI_MATCH(DMI_SYS_VENDOR, "eMachines"), | |
1165 | DMI_MATCH(DMI_PRODUCT_NAME, "eMachines G725"), | |
1166 | }, | |
9deb3431 | 1167 | .driver_data = "20091216", /* V3.04 */ |
cedc9bf9 | 1168 | }, |
9b10ae86 TH |
1169 | { } /* terminate list */ |
1170 | }; | |
1171 | const struct dmi_system_id *dmi = dmi_first_match(sysids); | |
9deb3431 TH |
1172 | int year, month, date; |
1173 | char buf[9]; | |
9b10ae86 TH |
1174 | |
1175 | if (!dmi || pdev->bus->number || pdev->devfn != PCI_DEVFN(0x1f, 2)) | |
1176 | return false; | |
1177 | ||
9deb3431 TH |
1178 | dmi_get_date(DMI_BIOS_DATE, &year, &month, &date); |
1179 | snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date); | |
9b10ae86 | 1180 | |
9deb3431 | 1181 | return strcmp(buf, dmi->driver_data) < 0; |
9b10ae86 TH |
1182 | } |
1183 | ||
5594639a TH |
1184 | static bool ahci_broken_online(struct pci_dev *pdev) |
1185 | { | |
1186 | #define ENCODE_BUSDEVFN(bus, slot, func) \ | |
1187 | (void *)(unsigned long)(((bus) << 8) | PCI_DEVFN((slot), (func))) | |
1188 | static const struct dmi_system_id sysids[] = { | |
1189 | /* | |
1190 | * There are several gigabyte boards which use | |
1191 | * SIMG5723s configured as hardware RAID. Certain | |
1192 | * 5723 firmware revisions shipped there keep the link | |
1193 | * online but fail to answer properly to SRST or | |
1194 | * IDENTIFY when no device is attached downstream | |
1195 | * causing libata to retry quite a few times leading | |
1196 | * to excessive detection delay. | |
1197 | * | |
1198 | * As these firmwares respond to the second reset try | |
1199 | * with invalid device signature, considering unknown | |
1200 | * sig as offline works around the problem acceptably. | |
1201 | */ | |
1202 | { | |
1203 | .ident = "EP45-DQ6", | |
1204 | .matches = { | |
1205 | DMI_MATCH(DMI_BOARD_VENDOR, | |
1206 | "Gigabyte Technology Co., Ltd."), | |
1207 | DMI_MATCH(DMI_BOARD_NAME, "EP45-DQ6"), | |
1208 | }, | |
1209 | .driver_data = ENCODE_BUSDEVFN(0x0a, 0x00, 0), | |
1210 | }, | |
1211 | { | |
1212 | .ident = "EP45-DS5", | |
1213 | .matches = { | |
1214 | DMI_MATCH(DMI_BOARD_VENDOR, | |
1215 | "Gigabyte Technology Co., Ltd."), | |
1216 | DMI_MATCH(DMI_BOARD_NAME, "EP45-DS5"), | |
1217 | }, | |
1218 | .driver_data = ENCODE_BUSDEVFN(0x03, 0x00, 0), | |
1219 | }, | |
1220 | { } /* terminate list */ | |
1221 | }; | |
1222 | #undef ENCODE_BUSDEVFN | |
1223 | const struct dmi_system_id *dmi = dmi_first_match(sysids); | |
1224 | unsigned int val; | |
1225 | ||
1226 | if (!dmi) | |
1227 | return false; | |
1228 | ||
1229 | val = (unsigned long)dmi->driver_data; | |
1230 | ||
1231 | return pdev->bus->number == (val >> 8) && pdev->devfn == (val & 0xff); | |
1232 | } | |
1233 | ||
0cf4a7d6 JP |
1234 | static bool ahci_broken_devslp(struct pci_dev *pdev) |
1235 | { | |
1236 | /* device with broken DEVSLP but still showing SDS capability */ | |
1237 | static const struct pci_device_id ids[] = { | |
1238 | { PCI_VDEVICE(INTEL, 0x0f23)}, /* Valleyview SoC */ | |
1239 | {} | |
1240 | }; | |
1241 | ||
1242 | return pci_match_id(ids, pdev); | |
1243 | } | |
1244 | ||
8e513217 | 1245 | #ifdef CONFIG_ATA_ACPI |
f80ae7e4 TH |
1246 | static void ahci_gtf_filter_workaround(struct ata_host *host) |
1247 | { | |
1248 | static const struct dmi_system_id sysids[] = { | |
1249 | /* | |
1250 | * Aspire 3810T issues a bunch of SATA enable commands | |
1251 | * via _GTF including an invalid one and one which is | |
1252 | * rejected by the device. Among the successful ones | |
1253 | * is FPDMA non-zero offset enable which when enabled | |
1254 | * only on the drive side leads to NCQ command | |
1255 | * failures. Filter it out. | |
1256 | */ | |
1257 | { | |
1258 | .ident = "Aspire 3810T", | |
1259 | .matches = { | |
1260 | DMI_MATCH(DMI_SYS_VENDOR, "Acer"), | |
1261 | DMI_MATCH(DMI_PRODUCT_NAME, "Aspire 3810T"), | |
1262 | }, | |
1263 | .driver_data = (void *)ATA_ACPI_FILTER_FPDMA_OFFSET, | |
1264 | }, | |
1265 | { } | |
1266 | }; | |
1267 | const struct dmi_system_id *dmi = dmi_first_match(sysids); | |
1268 | unsigned int filter; | |
1269 | int i; | |
1270 | ||
1271 | if (!dmi) | |
1272 | return; | |
1273 | ||
1274 | filter = (unsigned long)dmi->driver_data; | |
a44fec1f JP |
1275 | dev_info(host->dev, "applying extra ACPI _GTF filter 0x%x for %s\n", |
1276 | filter, dmi->ident); | |
f80ae7e4 TH |
1277 | |
1278 | for (i = 0; i < host->n_ports; i++) { | |
1279 | struct ata_port *ap = host->ports[i]; | |
1280 | struct ata_link *link; | |
1281 | struct ata_device *dev; | |
1282 | ||
1283 | ata_for_each_link(link, ap, EDGE) | |
1284 | ata_for_each_dev(dev, link, ALL) | |
1285 | dev->gtf_filter |= filter; | |
1286 | } | |
1287 | } | |
8e513217 MT |
1288 | #else |
1289 | static inline void ahci_gtf_filter_workaround(struct ata_host *host) | |
1290 | {} | |
1291 | #endif | |
f80ae7e4 | 1292 | |
ee2aad42 RR |
1293 | /* |
1294 | * ahci_init_msix() only implements single MSI-X support, not multiple | |
1295 | * MSI-X per-port interrupts. This is needed for host controllers that only | |
1296 | * have MSI-X support implemented, but no MSI or intx. | |
1297 | */ | |
1298 | static int ahci_init_msix(struct pci_dev *pdev, unsigned int n_ports, | |
1299 | struct ahci_host_priv *hpriv) | |
5ca72c4f | 1300 | { |
ccf8f53c | 1301 | int rc, nvec; |
ee2aad42 | 1302 | struct msix_entry entry = {}; |
5ca72c4f | 1303 | |
ee2aad42 | 1304 | /* Do not init MSI-X if MSI is disabled for the device */ |
7b92b4f6 | 1305 | if (hpriv->flags & AHCI_HFLAG_NO_MSI) |
ee2aad42 RR |
1306 | return -ENODEV; |
1307 | ||
1308 | nvec = pci_msix_vec_count(pdev); | |
1309 | if (nvec < 0) | |
1310 | return nvec; | |
1311 | ||
1312 | if (!nvec) { | |
1313 | rc = -ENODEV; | |
1314 | goto fail; | |
1315 | } | |
1316 | ||
1317 | /* | |
1318 | * There can be more than one vector (e.g. for error detection or | |
1319 | * hdd hotplug). Only the first vector (entry.entry = 0) is used. | |
1320 | */ | |
1321 | rc = pci_enable_msix_exact(pdev, &entry, 1); | |
1322 | if (rc < 0) | |
1323 | goto fail; | |
1324 | ||
34c56932 | 1325 | hpriv->irq = entry.vector; |
ee2aad42 RR |
1326 | |
1327 | return 1; | |
1328 | fail: | |
1329 | dev_err(&pdev->dev, | |
1330 | "failed to enable MSI-X with error %d, # of vectors: %d\n", | |
1331 | rc, nvec); | |
1332 | ||
1333 | return rc; | |
1334 | } | |
1335 | ||
a1c82311 RR |
1336 | static int ahci_init_msi(struct pci_dev *pdev, unsigned int n_ports, |
1337 | struct ahci_host_priv *hpriv) | |
5ca72c4f | 1338 | { |
ccf8f53c | 1339 | int rc, nvec; |
5ca72c4f | 1340 | |
7b92b4f6 | 1341 | if (hpriv->flags & AHCI_HFLAG_NO_MSI) |
a1c82311 | 1342 | return -ENODEV; |
7b92b4f6 | 1343 | |
fc061d96 AG |
1344 | nvec = pci_msi_vec_count(pdev); |
1345 | if (nvec < 0) | |
a1c82311 | 1346 | return nvec; |
7b92b4f6 AG |
1347 | |
1348 | /* | |
1349 | * If number of MSIs is less than number of ports then Sharing Last | |
1350 | * Message mode could be enforced. In this case assume that advantage | |
1351 | * of multipe MSIs is negated and use single MSI mode instead. | |
1352 | */ | |
fc061d96 | 1353 | if (nvec < n_ports) |
7b92b4f6 AG |
1354 | goto single_msi; |
1355 | ||
ccf8f53c AG |
1356 | rc = pci_enable_msi_exact(pdev, nvec); |
1357 | if (rc == -ENOSPC) | |
fc40363b | 1358 | goto single_msi; |
a1c82311 RR |
1359 | if (rc < 0) |
1360 | return rc; | |
5ca72c4f | 1361 | |
ab0f9e78 AG |
1362 | /* fallback to single MSI mode if the controller enforced MRSM mode */ |
1363 | if (readl(hpriv->mmio + HOST_CTL) & HOST_MRSM) { | |
1364 | pci_disable_msi(pdev); | |
1365 | printk(KERN_INFO "ahci: MRSM is on, fallback to single MSI\n"); | |
1366 | goto single_msi; | |
1367 | } | |
1368 | ||
c3ebd6a9 AG |
1369 | if (nvec > 1) |
1370 | hpriv->flags |= AHCI_HFLAG_MULTI_MSI; | |
1371 | ||
21bfd1aa | 1372 | goto out; |
7b92b4f6 AG |
1373 | |
1374 | single_msi: | |
21bfd1aa RR |
1375 | nvec = 1; |
1376 | ||
a1c82311 RR |
1377 | rc = pci_enable_msi(pdev); |
1378 | if (rc < 0) | |
1379 | return rc; | |
21bfd1aa RR |
1380 | out: |
1381 | hpriv->irq = pdev->irq; | |
a1c82311 | 1382 | |
21bfd1aa | 1383 | return nvec; |
a1c82311 | 1384 | } |
7b92b4f6 | 1385 | |
a1c82311 RR |
1386 | static int ahci_init_interrupts(struct pci_dev *pdev, unsigned int n_ports, |
1387 | struct ahci_host_priv *hpriv) | |
1388 | { | |
1389 | int nvec; | |
1390 | ||
1391 | nvec = ahci_init_msi(pdev, n_ports, hpriv); | |
1392 | if (nvec >= 0) | |
1393 | return nvec; | |
1394 | ||
ee2aad42 RR |
1395 | /* |
1396 | * Currently, MSI-X support only implements single IRQ mode and | |
1397 | * exists for controllers which can't do other types of IRQ. Only | |
1398 | * set it up if MSI fails. | |
1399 | */ | |
1400 | nvec = ahci_init_msix(pdev, n_ports, hpriv); | |
1401 | if (nvec >= 0) | |
1402 | return nvec; | |
7b92b4f6 | 1403 | |
a1c82311 | 1404 | /* lagacy intx interrupts */ |
5ca72c4f | 1405 | pci_intx(pdev, 1); |
21bfd1aa | 1406 | hpriv->irq = pdev->irq; |
a1c82311 | 1407 | |
5ca72c4f AG |
1408 | return 0; |
1409 | } | |
1410 | ||
24dc5f33 | 1411 | static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) |
1da177e4 | 1412 | { |
e297d99e TH |
1413 | unsigned int board_id = ent->driver_data; |
1414 | struct ata_port_info pi = ahci_port_info[board_id]; | |
4447d351 | 1415 | const struct ata_port_info *ppi[] = { &pi, NULL }; |
24dc5f33 | 1416 | struct device *dev = &pdev->dev; |
1da177e4 | 1417 | struct ahci_host_priv *hpriv; |
4447d351 | 1418 | struct ata_host *host; |
c3ebd6a9 | 1419 | int n_ports, i, rc; |
318893e1 | 1420 | int ahci_pci_bar = AHCI_PCI_BAR_STANDARD; |
1da177e4 LT |
1421 | |
1422 | VPRINTK("ENTER\n"); | |
1423 | ||
b429dd59 | 1424 | WARN_ON((int)ATA_MAX_QUEUE > AHCI_MAX_CMDS); |
12fad3f9 | 1425 | |
06296a1e | 1426 | ata_print_version_once(&pdev->dev, DRV_VERSION); |
1da177e4 | 1427 | |
5b66c829 AC |
1428 | /* The AHCI driver can only drive the SATA ports, the PATA driver |
1429 | can drive them all so if both drivers are selected make sure | |
1430 | AHCI stays out of the way */ | |
1431 | if (pdev->vendor == PCI_VENDOR_ID_MARVELL && !marvell_enable) | |
1432 | return -ENODEV; | |
1433 | ||
cb85696d JL |
1434 | /* Apple BIOS on MCP89 prevents us using AHCI */ |
1435 | if (is_mcp89_apple(pdev)) | |
1436 | ahci_mcp89_apple_enable(pdev); | |
c6353b45 | 1437 | |
7a02267e MN |
1438 | /* Promise's PDC42819 is a SAS/SATA controller that has an AHCI mode. |
1439 | * At the moment, we can only use the AHCI mode. Let the users know | |
1440 | * that for SAS drives they're out of luck. | |
1441 | */ | |
1442 | if (pdev->vendor == PCI_VENDOR_ID_PROMISE) | |
a44fec1f JP |
1443 | dev_info(&pdev->dev, |
1444 | "PDC42819 can only drive SATA devices with this driver\n"); | |
7a02267e | 1445 | |
b7ae128d | 1446 | /* Some devices use non-standard BARs */ |
318893e1 AR |
1447 | if (pdev->vendor == PCI_VENDOR_ID_STMICRO && pdev->device == 0xCC06) |
1448 | ahci_pci_bar = AHCI_PCI_BAR_STA2X11; | |
7f9c9f8e HD |
1449 | else if (pdev->vendor == 0x1c44 && pdev->device == 0x8000) |
1450 | ahci_pci_bar = AHCI_PCI_BAR_ENMOTUS; | |
b7ae128d RR |
1451 | else if (pdev->vendor == 0x177d && pdev->device == 0xa01c) |
1452 | ahci_pci_bar = AHCI_PCI_BAR_CAVIUM; | |
318893e1 | 1453 | |
e6b7e41c CL |
1454 | /* |
1455 | * The JMicron chip 361/363 contains one SATA controller and one | |
1456 | * PATA controller,for powering on these both controllers, we must | |
1457 | * follow the sequence one by one, otherwise one of them can not be | |
1458 | * powered on successfully, so here we disable the async suspend | |
1459 | * method for these chips. | |
1460 | */ | |
1461 | if (pdev->vendor == PCI_VENDOR_ID_JMICRON && | |
1462 | (pdev->device == PCI_DEVICE_ID_JMICRON_JMB363 || | |
1463 | pdev->device == PCI_DEVICE_ID_JMICRON_JMB361)) | |
1464 | device_disable_async_suspend(&pdev->dev); | |
1465 | ||
4447d351 | 1466 | /* acquire resources */ |
24dc5f33 | 1467 | rc = pcim_enable_device(pdev); |
1da177e4 LT |
1468 | if (rc) |
1469 | return rc; | |
1470 | ||
c4f7792c TH |
1471 | if (pdev->vendor == PCI_VENDOR_ID_INTEL && |
1472 | (pdev->device == 0x2652 || pdev->device == 0x2653)) { | |
1473 | u8 map; | |
1474 | ||
1475 | /* ICH6s share the same PCI ID for both piix and ahci | |
1476 | * modes. Enabling ahci mode while MAP indicates | |
1477 | * combined mode is a bad idea. Yield to ata_piix. | |
1478 | */ | |
1479 | pci_read_config_byte(pdev, ICH_MAP, &map); | |
1480 | if (map & 0x3) { | |
a44fec1f JP |
1481 | dev_info(&pdev->dev, |
1482 | "controller is in combined mode, can't enable AHCI mode\n"); | |
c4f7792c TH |
1483 | return -ENODEV; |
1484 | } | |
1485 | } | |
1486 | ||
6fec8871 PB |
1487 | /* AHCI controllers often implement SFF compatible interface. |
1488 | * Grab all PCI BARs just in case. | |
1489 | */ | |
1490 | rc = pcim_iomap_regions_request_all(pdev, 1 << ahci_pci_bar, DRV_NAME); | |
1491 | if (rc == -EBUSY) | |
1492 | pcim_pin_device(pdev); | |
1493 | if (rc) | |
1494 | return rc; | |
1495 | ||
24dc5f33 TH |
1496 | hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL); |
1497 | if (!hpriv) | |
1498 | return -ENOMEM; | |
417a1a6d TH |
1499 | hpriv->flags |= (unsigned long)pi.private_data; |
1500 | ||
e297d99e TH |
1501 | /* MCP65 revision A1 and A2 can't do MSI */ |
1502 | if (board_id == board_ahci_mcp65 && | |
1503 | (pdev->revision == 0xa1 || pdev->revision == 0xa2)) | |
1504 | hpriv->flags |= AHCI_HFLAG_NO_MSI; | |
1505 | ||
e427fe04 SH |
1506 | /* SB800 does NOT need the workaround to ignore SERR_INTERNAL */ |
1507 | if (board_id == board_ahci_sb700 && pdev->revision >= 0x40) | |
1508 | hpriv->flags &= ~AHCI_HFLAG_IGN_SERR_INTERNAL; | |
1509 | ||
2fcad9d2 TH |
1510 | /* only some SB600s can do 64bit DMA */ |
1511 | if (ahci_sb600_enable_64bit(pdev)) | |
1512 | hpriv->flags &= ~AHCI_HFLAG_32BIT_ONLY; | |
58a09b38 | 1513 | |
318893e1 | 1514 | hpriv->mmio = pcim_iomap_table(pdev)[ahci_pci_bar]; |
d8993349 | 1515 | |
0cf4a7d6 JP |
1516 | /* must set flag prior to save config in order to take effect */ |
1517 | if (ahci_broken_devslp(pdev)) | |
1518 | hpriv->flags |= AHCI_HFLAG_NO_DEVSLP; | |
1519 | ||
4447d351 | 1520 | /* save initial config */ |
394d6e53 | 1521 | ahci_pci_save_initial_config(pdev, hpriv); |
1da177e4 | 1522 | |
4447d351 | 1523 | /* prepare host */ |
453d3131 RH |
1524 | if (hpriv->cap & HOST_CAP_NCQ) { |
1525 | pi.flags |= ATA_FLAG_NCQ; | |
83f2b963 TH |
1526 | /* |
1527 | * Auto-activate optimization is supposed to be | |
1528 | * supported on all AHCI controllers indicating NCQ | |
1529 | * capability, but it seems to be broken on some | |
1530 | * chipsets including NVIDIAs. | |
1531 | */ | |
1532 | if (!(hpriv->flags & AHCI_HFLAG_NO_FPDMA_AA)) | |
453d3131 | 1533 | pi.flags |= ATA_FLAG_FPDMA_AA; |
40fb59e7 MC |
1534 | |
1535 | /* | |
1536 | * All AHCI controllers should be forward-compatible | |
1537 | * with the new auxiliary field. This code should be | |
1538 | * conditionalized if any buggy AHCI controllers are | |
1539 | * encountered. | |
1540 | */ | |
1541 | pi.flags |= ATA_FLAG_FPDMA_AUX; | |
453d3131 | 1542 | } |
1da177e4 | 1543 | |
7d50b60b TH |
1544 | if (hpriv->cap & HOST_CAP_PMP) |
1545 | pi.flags |= ATA_FLAG_PMP; | |
1546 | ||
0cbb0e77 | 1547 | ahci_set_em_messages(hpriv, &pi); |
18f7ba4c | 1548 | |
1fd68434 RW |
1549 | if (ahci_broken_system_poweroff(pdev)) { |
1550 | pi.flags |= ATA_FLAG_NO_POWEROFF_SPINDOWN; | |
1551 | dev_info(&pdev->dev, | |
1552 | "quirky BIOS, skipping spindown on poweroff\n"); | |
1553 | } | |
1554 | ||
9b10ae86 TH |
1555 | if (ahci_broken_suspend(pdev)) { |
1556 | hpriv->flags |= AHCI_HFLAG_NO_SUSPEND; | |
a44fec1f JP |
1557 | dev_warn(&pdev->dev, |
1558 | "BIOS update required for suspend/resume\n"); | |
9b10ae86 TH |
1559 | } |
1560 | ||
5594639a TH |
1561 | if (ahci_broken_online(pdev)) { |
1562 | hpriv->flags |= AHCI_HFLAG_SRST_TOUT_IS_OFFLINE; | |
1563 | dev_info(&pdev->dev, | |
1564 | "online status unreliable, applying workaround\n"); | |
1565 | } | |
1566 | ||
837f5f8f TH |
1567 | /* CAP.NP sometimes indicate the index of the last enabled |
1568 | * port, at other times, that of the last possible port, so | |
1569 | * determining the maximum port number requires looking at | |
1570 | * both CAP.NP and port_map. | |
1571 | */ | |
1572 | n_ports = max(ahci_nr_ports(hpriv->cap), fls(hpriv->port_map)); | |
1573 | ||
1574 | host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports); | |
4447d351 TH |
1575 | if (!host) |
1576 | return -ENOMEM; | |
4447d351 TH |
1577 | host->private_data = hpriv; |
1578 | ||
21bfd1aa RR |
1579 | ahci_init_interrupts(pdev, n_ports, hpriv); |
1580 | ||
f3d7f23f | 1581 | if (!(hpriv->cap & HOST_CAP_SSS) || ahci_ignore_sss) |
886ad09f | 1582 | host->flags |= ATA_HOST_PARALLEL_SCAN; |
f3d7f23f | 1583 | else |
d2782d96 | 1584 | dev_info(&pdev->dev, "SSS flag set, parallel bus scan disabled\n"); |
886ad09f | 1585 | |
18f7ba4c KCA |
1586 | if (pi.flags & ATA_FLAG_EM) |
1587 | ahci_reset_em(host); | |
1588 | ||
4447d351 | 1589 | for (i = 0; i < host->n_ports; i++) { |
dab632e8 | 1590 | struct ata_port *ap = host->ports[i]; |
4447d351 | 1591 | |
318893e1 AR |
1592 | ata_port_pbar_desc(ap, ahci_pci_bar, -1, "abar"); |
1593 | ata_port_pbar_desc(ap, ahci_pci_bar, | |
cbcdd875 TH |
1594 | 0x100 + ap->port_no * 0x80, "port"); |
1595 | ||
18f7ba4c KCA |
1596 | /* set enclosure management message type */ |
1597 | if (ap->flags & ATA_FLAG_EM) | |
008dbd61 | 1598 | ap->em_message_type = hpriv->em_msg_type; |
18f7ba4c KCA |
1599 | |
1600 | ||
dab632e8 | 1601 | /* disabled/not-implemented port */ |
350756f6 | 1602 | if (!(hpriv->port_map & (1 << i))) |
dab632e8 | 1603 | ap->ops = &ata_dummy_port_ops; |
4447d351 | 1604 | } |
d447df14 | 1605 | |
edc93052 TH |
1606 | /* apply workaround for ASUS P5W DH Deluxe mainboard */ |
1607 | ahci_p5wdh_workaround(host); | |
1608 | ||
f80ae7e4 TH |
1609 | /* apply gtf filter quirk */ |
1610 | ahci_gtf_filter_workaround(host); | |
1611 | ||
4447d351 TH |
1612 | /* initialize adapter */ |
1613 | rc = ahci_configure_dma_masks(pdev, hpriv->cap & HOST_CAP_64); | |
1da177e4 | 1614 | if (rc) |
24dc5f33 | 1615 | return rc; |
1da177e4 | 1616 | |
3303040d | 1617 | rc = ahci_pci_reset_controller(host); |
4447d351 TH |
1618 | if (rc) |
1619 | return rc; | |
1da177e4 | 1620 | |
781d6550 | 1621 | ahci_pci_init_controller(host); |
439fcaec | 1622 | ahci_pci_print_info(host); |
1da177e4 | 1623 | |
4447d351 | 1624 | pci_set_master(pdev); |
5ca72c4f | 1625 | |
21bfd1aa | 1626 | return ahci_host_activate(host, &ahci_sht); |
907f4678 | 1627 | } |
1da177e4 | 1628 | |
2fc75da0 | 1629 | module_pci_driver(ahci_pci_driver); |
1da177e4 LT |
1630 | |
1631 | MODULE_AUTHOR("Jeff Garzik"); | |
1632 | MODULE_DESCRIPTION("AHCI SATA low-level driver"); | |
1633 | MODULE_LICENSE("GPL"); | |
1634 | MODULE_DEVICE_TABLE(pci, ahci_pci_tbl); | |
6885433c | 1635 | MODULE_VERSION(DRV_VERSION); |