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ata: use pci_get_drvdata()
[deliverable/linux.git] / drivers / ata / ahci.c
CommitLineData
1da177e4
LT		 1/*
2 * ahci.c - AHCI SATA support
3 *
af36d7f0
JG		 4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
7 *
8 * Copyright 2004-2005 Red Hat, Inc.
9 *
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
24 *
25 *
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
28 *
29 * AHCI hardware documentation:
1da177e4 30 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
af36d7f0 31 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
1da177e4
LT		 32 *
33 */
34
35#include <linux/kernel.h>
36#include <linux/module.h>
37#include <linux/pci.h>
38#include <linux/init.h>
39#include <linux/blkdev.h>
40#include <linux/delay.h>
41#include <linux/interrupt.h>
87507cfd 42#include <linux/dma-mapping.h>
a9524a76 43#include <linux/device.h>
edc93052 44#include <linux/dmi.h>
5a0e3ad6 45#include <linux/gfp.h>
1da177e4 46#include <scsi/scsi_host.h>
193515d5 47#include <scsi/scsi_cmnd.h>
1da177e4 48#include <linux/libata.h>
365cfa1e 49#include "ahci.h"
1da177e4
LT		 50
51#define DRV_NAME "ahci"
7d50b60b 52#define DRV_VERSION "3.0"
1da177e4 53
1da177e4 54enum {
318893e1 55 AHCI_PCI_BAR_STA2X11 = 0,
7f9c9f8e 56 AHCI_PCI_BAR_ENMOTUS = 2,
318893e1 57 AHCI_PCI_BAR_STANDARD = 5,
441577ef
TH		 58};
59
60enum board_ids {
61 /* board IDs by feature in alphabetical order */
62 board_ahci,
63 board_ahci_ign_iferr,
64 board_ahci_nosntf,
5f173107 65 board_ahci_yes_fbs,
1da177e4 66
441577ef
TH		 67 /* board IDs for specific chipsets in alphabetical order */
68 board_ahci_mcp65,
83f2b963
TH		 69 board_ahci_mcp77,
70 board_ahci_mcp89,
441577ef
TH		 71 board_ahci_mv,
72 board_ahci_sb600,
73 board_ahci_sb700, /* for SB700 and SB800 */
74 board_ahci_vt8251,
75
76 /* aliases */
77 board_ahci_mcp_linux = board_ahci_mcp65,
78 board_ahci_mcp67 = board_ahci_mcp65,
79 board_ahci_mcp73 = board_ahci_mcp65,
83f2b963 80 board_ahci_mcp79 = board_ahci_mcp77,
1da177e4
LT		 81};
82
2dcb407e 83static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
a1efdaba
TH		 84static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
85 unsigned long deadline);
86static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
87 unsigned long deadline);
438ac6d5 88#ifdef CONFIG_PM
c1332875
TH		 89static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg);
90static int ahci_pci_device_resume(struct pci_dev *pdev);
438ac6d5 91#endif
ad616ffb 92
fad16e7a
TH		 93static struct scsi_host_template ahci_sht = {
94 AHCI_SHT("ahci"),
95};
96
029cfd6b
TH		 97static struct ata_port_operations ahci_vt8251_ops = {
98 .inherits = &ahci_ops,
a1efdaba 99 .hardreset = ahci_vt8251_hardreset,
029cfd6b 100};
edc93052 101
029cfd6b
TH		 102static struct ata_port_operations ahci_p5wdh_ops = {
103 .inherits = &ahci_ops,
a1efdaba 104 .hardreset = ahci_p5wdh_hardreset,
edc93052
TH		 105};
106
98ac62de 107static const struct ata_port_info ahci_port_info[] = {
441577ef 108 /* by features */
facb8fa6 109 [board_ahci] = {
1188c0d8 110 .flags = AHCI_FLAG_COMMON,
14bdef98 111 .pio_mask = ATA_PIO4,
469248ab 112 .udma_mask = ATA_UDMA6,
1da177e4
LT		 113 .port_ops = &ahci_ops,
114 },
facb8fa6 115 [board_ahci_ign_iferr] = {
441577ef 116 AHCI_HFLAGS (AHCI_HFLAG_IGN_IRQ_IF_ERR),
417a1a6d 117 .flags = AHCI_FLAG_COMMON,
14bdef98 118 .pio_mask = ATA_PIO4,
469248ab 119 .udma_mask = ATA_UDMA6,
441577ef 120 .port_ops = &ahci_ops,
bf2af2a2 121 },
facb8fa6 122 [board_ahci_nosntf] = {
441577ef 123 AHCI_HFLAGS (AHCI_HFLAG_NO_SNTF),
417a1a6d 124 .flags = AHCI_FLAG_COMMON,
14bdef98 125 .pio_mask = ATA_PIO4,
469248ab 126 .udma_mask = ATA_UDMA6,
41669553
TH		 127 .port_ops = &ahci_ops,
128 },
facb8fa6 129 [board_ahci_yes_fbs] = {
5f173107
TH		 130 AHCI_HFLAGS (AHCI_HFLAG_YES_FBS),
131 .flags = AHCI_FLAG_COMMON,
132 .pio_mask = ATA_PIO4,
133 .udma_mask = ATA_UDMA6,
134 .port_ops = &ahci_ops,
135 },
441577ef 136 /* by chipsets */
facb8fa6 137 [board_ahci_mcp65] = {
83f2b963
TH		 138 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP |
139 AHCI_HFLAG_YES_NCQ),
ae01b249 140 .flags = AHCI_FLAG_COMMON | ATA_FLAG_NO_DIPM,
83f2b963
TH		 141 .pio_mask = ATA_PIO4,
142 .udma_mask = ATA_UDMA6,
143 .port_ops = &ahci_ops,
144 },
facb8fa6 145 [board_ahci_mcp77] = {
83f2b963
TH		 146 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP),
147 .flags = AHCI_FLAG_COMMON,
148 .pio_mask = ATA_PIO4,
149 .udma_mask = ATA_UDMA6,
150 .port_ops = &ahci_ops,
151 },
facb8fa6 152 [board_ahci_mcp89] = {
83f2b963 153 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA),
417a1a6d 154 .flags = AHCI_FLAG_COMMON,
14bdef98 155 .pio_mask = ATA_PIO4,
469248ab 156 .udma_mask = ATA_UDMA6,
441577ef 157 .port_ops = &ahci_ops,
55a61604 158 },
facb8fa6 159 [board_ahci_mv] = {
417a1a6d 160 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_MSI |
17248461 161 AHCI_HFLAG_MV_PATA | AHCI_HFLAG_NO_PMP),
9cbe056f 162 .flags = ATA_FLAG_SATA | ATA_FLAG_PIO_DMA,
14bdef98 163 .pio_mask = ATA_PIO4,
cd70c266
JG		 164 .udma_mask = ATA_UDMA6,
165 .port_ops = &ahci_ops,
166 },
facb8fa6 167 [board_ahci_sb600] = {
441577ef
TH		 168 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL |
169 AHCI_HFLAG_NO_MSI | AHCI_HFLAG_SECT255 |
170 AHCI_HFLAG_32BIT_ONLY),
e39fc8c9 171 .flags = AHCI_FLAG_COMMON,
14bdef98 172 .pio_mask = ATA_PIO4,
e39fc8c9 173 .udma_mask = ATA_UDMA6,
345347c5 174 .port_ops = &ahci_pmp_retry_srst_ops,
e39fc8c9 175 },
facb8fa6 176 [board_ahci_sb700] = { /* for SB700 and SB800 */
441577ef 177 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL),
aa431dd3
TH		 178 .flags = AHCI_FLAG_COMMON,
179 .pio_mask = ATA_PIO4,
180 .udma_mask = ATA_UDMA6,
345347c5 181 .port_ops = &ahci_pmp_retry_srst_ops,
aa431dd3 182 },
facb8fa6 183 [board_ahci_vt8251] = {
441577ef 184 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_PMP),
1b677afd
SL		 185 .flags = AHCI_FLAG_COMMON,
186 .pio_mask = ATA_PIO4,
187 .udma_mask = ATA_UDMA6,
441577ef 188 .port_ops = &ahci_vt8251_ops,
1b677afd 189 },
1da177e4
LT		 190};
191
3b7d697d 192static const struct pci_device_id ahci_pci_tbl[] = {
fe7fa31a 193 /* Intel */
54bb3a94
JG		 194 { PCI_VDEVICE(INTEL, 0x2652), board_ahci }, /* ICH6 */
195 { PCI_VDEVICE(INTEL, 0x2653), board_ahci }, /* ICH6M */
196 { PCI_VDEVICE(INTEL, 0x27c1), board_ahci }, /* ICH7 */
197 { PCI_VDEVICE(INTEL, 0x27c5), board_ahci }, /* ICH7M */
198 { PCI_VDEVICE(INTEL, 0x27c3), board_ahci }, /* ICH7R */
82490c09 199 { PCI_VDEVICE(AL, 0x5288), board_ahci_ign_iferr }, /* ULi M5288 */
54bb3a94
JG		 200 { PCI_VDEVICE(INTEL, 0x2681), board_ahci }, /* ESB2 */
201 { PCI_VDEVICE(INTEL, 0x2682), board_ahci }, /* ESB2 */
202 { PCI_VDEVICE(INTEL, 0x2683), board_ahci }, /* ESB2 */
203 { PCI_VDEVICE(INTEL, 0x27c6), board_ahci }, /* ICH7-M DH */
7a234aff 204 { PCI_VDEVICE(INTEL, 0x2821), board_ahci }, /* ICH8 */
1b677afd 205 { PCI_VDEVICE(INTEL, 0x2822), board_ahci_nosntf }, /* ICH8 */
7a234aff
TH		 206 { PCI_VDEVICE(INTEL, 0x2824), board_ahci }, /* ICH8 */
207 { PCI_VDEVICE(INTEL, 0x2829), board_ahci }, /* ICH8M */
208 { PCI_VDEVICE(INTEL, 0x282a), board_ahci }, /* ICH8M */
209 { PCI_VDEVICE(INTEL, 0x2922), board_ahci }, /* ICH9 */
210 { PCI_VDEVICE(INTEL, 0x2923), board_ahci }, /* ICH9 */
211 { PCI_VDEVICE(INTEL, 0x2924), board_ahci }, /* ICH9 */
212 { PCI_VDEVICE(INTEL, 0x2925), board_ahci }, /* ICH9 */
213 { PCI_VDEVICE(INTEL, 0x2927), board_ahci }, /* ICH9 */
214 { PCI_VDEVICE(INTEL, 0x2929), board_ahci }, /* ICH9M */
215 { PCI_VDEVICE(INTEL, 0x292a), board_ahci }, /* ICH9M */
216 { PCI_VDEVICE(INTEL, 0x292b), board_ahci }, /* ICH9M */
217 { PCI_VDEVICE(INTEL, 0x292c), board_ahci }, /* ICH9M */
218 { PCI_VDEVICE(INTEL, 0x292f), board_ahci }, /* ICH9M */
219 { PCI_VDEVICE(INTEL, 0x294d), board_ahci }, /* ICH9 */
220 { PCI_VDEVICE(INTEL, 0x294e), board_ahci }, /* ICH9M */
d4155e6f
JG		 221 { PCI_VDEVICE(INTEL, 0x502a), board_ahci }, /* Tolapai */
222 { PCI_VDEVICE(INTEL, 0x502b), board_ahci }, /* Tolapai */
16ad1ad9 223 { PCI_VDEVICE(INTEL, 0x3a05), board_ahci }, /* ICH10 */
b2dde6af 224 { PCI_VDEVICE(INTEL, 0x3a22), board_ahci }, /* ICH10 */
16ad1ad9 225 { PCI_VDEVICE(INTEL, 0x3a25), board_ahci }, /* ICH10 */
c1f57d9b
DM		 226 { PCI_VDEVICE(INTEL, 0x3b22), board_ahci }, /* PCH AHCI */
227 { PCI_VDEVICE(INTEL, 0x3b23), board_ahci }, /* PCH AHCI */
adcb5308 228 { PCI_VDEVICE(INTEL, 0x3b24), board_ahci }, /* PCH RAID */
8e48b6b3 229 { PCI_VDEVICE(INTEL, 0x3b25), board_ahci }, /* PCH RAID */
c1f57d9b 230 { PCI_VDEVICE(INTEL, 0x3b29), board_ahci }, /* PCH AHCI */
adcb5308 231 { PCI_VDEVICE(INTEL, 0x3b2b), board_ahci }, /* PCH RAID */
8e48b6b3 232 { PCI_VDEVICE(INTEL, 0x3b2c), board_ahci }, /* PCH RAID */
c1f57d9b 233 { PCI_VDEVICE(INTEL, 0x3b2f), board_ahci }, /* PCH AHCI */
5623cab8
SH		 234 { PCI_VDEVICE(INTEL, 0x1c02), board_ahci }, /* CPT AHCI */
235 { PCI_VDEVICE(INTEL, 0x1c03), board_ahci }, /* CPT AHCI */
236 { PCI_VDEVICE(INTEL, 0x1c04), board_ahci }, /* CPT RAID */
237 { PCI_VDEVICE(INTEL, 0x1c05), board_ahci }, /* CPT RAID */
238 { PCI_VDEVICE(INTEL, 0x1c06), board_ahci }, /* CPT RAID */
239 { PCI_VDEVICE(INTEL, 0x1c07), board_ahci }, /* CPT RAID */
992b3fb9
SH		 240 { PCI_VDEVICE(INTEL, 0x1d02), board_ahci }, /* PBG AHCI */
241 { PCI_VDEVICE(INTEL, 0x1d04), board_ahci }, /* PBG RAID */
242 { PCI_VDEVICE(INTEL, 0x1d06), board_ahci }, /* PBG RAID */
64a3903d 243 { PCI_VDEVICE(INTEL, 0x2826), board_ahci }, /* PBG RAID */
a4a461a6 244 { PCI_VDEVICE(INTEL, 0x2323), board_ahci }, /* DH89xxCC AHCI */
181e3cea
SH		 245 { PCI_VDEVICE(INTEL, 0x1e02), board_ahci }, /* Panther Point AHCI */
246 { PCI_VDEVICE(INTEL, 0x1e03), board_ahci }, /* Panther Point AHCI */
247 { PCI_VDEVICE(INTEL, 0x1e04), board_ahci }, /* Panther Point RAID */
248 { PCI_VDEVICE(INTEL, 0x1e05), board_ahci }, /* Panther Point RAID */
249 { PCI_VDEVICE(INTEL, 0x1e06), board_ahci }, /* Panther Point RAID */
250 { PCI_VDEVICE(INTEL, 0x1e07), board_ahci }, /* Panther Point RAID */
2cab7a4c 251 { PCI_VDEVICE(INTEL, 0x1e0e), board_ahci }, /* Panther Point RAID */
ea4ace66
SH		 252 { PCI_VDEVICE(INTEL, 0x8c02), board_ahci }, /* Lynx Point AHCI */
253 { PCI_VDEVICE(INTEL, 0x8c03), board_ahci }, /* Lynx Point AHCI */
254 { PCI_VDEVICE(INTEL, 0x8c04), board_ahci }, /* Lynx Point RAID */
255 { PCI_VDEVICE(INTEL, 0x8c05), board_ahci }, /* Lynx Point RAID */
256 { PCI_VDEVICE(INTEL, 0x8c06), board_ahci }, /* Lynx Point RAID */
257 { PCI_VDEVICE(INTEL, 0x8c07), board_ahci }, /* Lynx Point RAID */
258 { PCI_VDEVICE(INTEL, 0x8c0e), board_ahci }, /* Lynx Point RAID */
259 { PCI_VDEVICE(INTEL, 0x8c0f), board_ahci }, /* Lynx Point RAID */
77b12bc9
JR		 260 { PCI_VDEVICE(INTEL, 0x9c02), board_ahci }, /* Lynx Point-LP AHCI */
261 { PCI_VDEVICE(INTEL, 0x9c03), board_ahci }, /* Lynx Point-LP AHCI */
262 { PCI_VDEVICE(INTEL, 0x9c04), board_ahci }, /* Lynx Point-LP RAID */
263 { PCI_VDEVICE(INTEL, 0x9c05), board_ahci }, /* Lynx Point-LP RAID */
264 { PCI_VDEVICE(INTEL, 0x9c06), board_ahci }, /* Lynx Point-LP RAID */
265 { PCI_VDEVICE(INTEL, 0x9c07), board_ahci }, /* Lynx Point-LP RAID */
266 { PCI_VDEVICE(INTEL, 0x9c0e), board_ahci }, /* Lynx Point-LP RAID */
267 { PCI_VDEVICE(INTEL, 0x9c0f), board_ahci }, /* Lynx Point-LP RAID */
29e674dd
SH		 268 { PCI_VDEVICE(INTEL, 0x1f22), board_ahci }, /* Avoton AHCI */
269 { PCI_VDEVICE(INTEL, 0x1f23), board_ahci }, /* Avoton AHCI */
270 { PCI_VDEVICE(INTEL, 0x1f24), board_ahci }, /* Avoton RAID */
271 { PCI_VDEVICE(INTEL, 0x1f25), board_ahci }, /* Avoton RAID */
272 { PCI_VDEVICE(INTEL, 0x1f26), board_ahci }, /* Avoton RAID */
273 { PCI_VDEVICE(INTEL, 0x1f27), board_ahci }, /* Avoton RAID */
274 { PCI_VDEVICE(INTEL, 0x1f2e), board_ahci }, /* Avoton RAID */
275 { PCI_VDEVICE(INTEL, 0x1f2f), board_ahci }, /* Avoton RAID */
276 { PCI_VDEVICE(INTEL, 0x1f32), board_ahci }, /* Avoton AHCI */
277 { PCI_VDEVICE(INTEL, 0x1f33), board_ahci }, /* Avoton AHCI */
278 { PCI_VDEVICE(INTEL, 0x1f34), board_ahci }, /* Avoton RAID */
279 { PCI_VDEVICE(INTEL, 0x1f35), board_ahci }, /* Avoton RAID */
280 { PCI_VDEVICE(INTEL, 0x1f36), board_ahci }, /* Avoton RAID */
281 { PCI_VDEVICE(INTEL, 0x1f37), board_ahci }, /* Avoton RAID */
282 { PCI_VDEVICE(INTEL, 0x1f3e), board_ahci }, /* Avoton RAID */
283 { PCI_VDEVICE(INTEL, 0x1f3f), board_ahci }, /* Avoton RAID */
efda332c
JR		 284 { PCI_VDEVICE(INTEL, 0x2823), board_ahci }, /* Wellsburg RAID */
285 { PCI_VDEVICE(INTEL, 0x2827), board_ahci }, /* Wellsburg RAID */
151743fd
JR		 286 { PCI_VDEVICE(INTEL, 0x8d02), board_ahci }, /* Wellsburg AHCI */
287 { PCI_VDEVICE(INTEL, 0x8d04), board_ahci }, /* Wellsburg RAID */
288 { PCI_VDEVICE(INTEL, 0x8d06), board_ahci }, /* Wellsburg RAID */
289 { PCI_VDEVICE(INTEL, 0x8d0e), board_ahci }, /* Wellsburg RAID */
290 { PCI_VDEVICE(INTEL, 0x8d62), board_ahci }, /* Wellsburg AHCI */
291 { PCI_VDEVICE(INTEL, 0x8d64), board_ahci }, /* Wellsburg RAID */
292 { PCI_VDEVICE(INTEL, 0x8d66), board_ahci }, /* Wellsburg RAID */
293 { PCI_VDEVICE(INTEL, 0x8d6e), board_ahci }, /* Wellsburg RAID */
fe7fa31a 294
e34bb370
TH		 295 /* JMicron 360/1/3/5/6, match class to avoid IDE function */
296 { PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
297 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci_ign_iferr },
1fefb8fd
BH		 298 /* JMicron 362B and 362C have an AHCI function with IDE class code */
299 { PCI_VDEVICE(JMICRON, 0x2362), board_ahci_ign_iferr },
300 { PCI_VDEVICE(JMICRON, 0x236f), board_ahci_ign_iferr },
fe7fa31a
JG		 301
302 /* ATI */
c65ec1c2 303 { PCI_VDEVICE(ATI, 0x4380), board_ahci_sb600 }, /* ATI SB600 */
e39fc8c9
SH		 304 { PCI_VDEVICE(ATI, 0x4390), board_ahci_sb700 }, /* ATI SB700/800 */
305 { PCI_VDEVICE(ATI, 0x4391), board_ahci_sb700 }, /* ATI SB700/800 */
306 { PCI_VDEVICE(ATI, 0x4392), board_ahci_sb700 }, /* ATI SB700/800 */
307 { PCI_VDEVICE(ATI, 0x4393), board_ahci_sb700 }, /* ATI SB700/800 */
308 { PCI_VDEVICE(ATI, 0x4394), board_ahci_sb700 }, /* ATI SB700/800 */
309 { PCI_VDEVICE(ATI, 0x4395), board_ahci_sb700 }, /* ATI SB700/800 */
fe7fa31a 310
e2dd90b1 311 /* AMD */
5deab536 312 { PCI_VDEVICE(AMD, 0x7800), board_ahci }, /* AMD Hudson-2 */
e2dd90b1
SH		 313 /* AMD is using RAID class only for ahci controllers */
314 { PCI_VENDOR_ID_AMD, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
315 PCI_CLASS_STORAGE_RAID << 8, 0xffffff, board_ahci },
316
fe7fa31a 317 /* VIA */
54bb3a94 318 { PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251 }, /* VIA VT8251 */
bf335542 319 { PCI_VDEVICE(VIA, 0x6287), board_ahci_vt8251 }, /* VIA VT8251 */
fe7fa31a
JG		 320
321 /* NVIDIA */
e297d99e
TH		 322 { PCI_VDEVICE(NVIDIA, 0x044c), board_ahci_mcp65 }, /* MCP65 */
323 { PCI_VDEVICE(NVIDIA, 0x044d), board_ahci_mcp65 }, /* MCP65 */
324 { PCI_VDEVICE(NVIDIA, 0x044e), board_ahci_mcp65 }, /* MCP65 */
325 { PCI_VDEVICE(NVIDIA, 0x044f), board_ahci_mcp65 }, /* MCP65 */
326 { PCI_VDEVICE(NVIDIA, 0x045c), board_ahci_mcp65 }, /* MCP65 */
327 { PCI_VDEVICE(NVIDIA, 0x045d), board_ahci_mcp65 }, /* MCP65 */
328 { PCI_VDEVICE(NVIDIA, 0x045e), board_ahci_mcp65 }, /* MCP65 */
329 { PCI_VDEVICE(NVIDIA, 0x045f), board_ahci_mcp65 }, /* MCP65 */
441577ef
TH		 330 { PCI_VDEVICE(NVIDIA, 0x0550), board_ahci_mcp67 }, /* MCP67 */
331 { PCI_VDEVICE(NVIDIA, 0x0551), board_ahci_mcp67 }, /* MCP67 */
332 { PCI_VDEVICE(NVIDIA, 0x0552), board_ahci_mcp67 }, /* MCP67 */
333 { PCI_VDEVICE(NVIDIA, 0x0553), board_ahci_mcp67 }, /* MCP67 */
334 { PCI_VDEVICE(NVIDIA, 0x0554), board_ahci_mcp67 }, /* MCP67 */
335 { PCI_VDEVICE(NVIDIA, 0x0555), board_ahci_mcp67 }, /* MCP67 */
336 { PCI_VDEVICE(NVIDIA, 0x0556), board_ahci_mcp67 }, /* MCP67 */
337 { PCI_VDEVICE(NVIDIA, 0x0557), board_ahci_mcp67 }, /* MCP67 */
338 { PCI_VDEVICE(NVIDIA, 0x0558), board_ahci_mcp67 }, /* MCP67 */
339 { PCI_VDEVICE(NVIDIA, 0x0559), board_ahci_mcp67 }, /* MCP67 */
340 { PCI_VDEVICE(NVIDIA, 0x055a), board_ahci_mcp67 }, /* MCP67 */
341 { PCI_VDEVICE(NVIDIA, 0x055b), board_ahci_mcp67 }, /* MCP67 */
342 { PCI_VDEVICE(NVIDIA, 0x0580), board_ahci_mcp_linux }, /* Linux ID */
343 { PCI_VDEVICE(NVIDIA, 0x0581), board_ahci_mcp_linux }, /* Linux ID */
344 { PCI_VDEVICE(NVIDIA, 0x0582), board_ahci_mcp_linux }, /* Linux ID */
345 { PCI_VDEVICE(NVIDIA, 0x0583), board_ahci_mcp_linux }, /* Linux ID */
346 { PCI_VDEVICE(NVIDIA, 0x0584), board_ahci_mcp_linux }, /* Linux ID */
347 { PCI_VDEVICE(NVIDIA, 0x0585), board_ahci_mcp_linux }, /* Linux ID */
348 { PCI_VDEVICE(NVIDIA, 0x0586), board_ahci_mcp_linux }, /* Linux ID */
349 { PCI_VDEVICE(NVIDIA, 0x0587), board_ahci_mcp_linux }, /* Linux ID */
350 { PCI_VDEVICE(NVIDIA, 0x0588), board_ahci_mcp_linux }, /* Linux ID */
351 { PCI_VDEVICE(NVIDIA, 0x0589), board_ahci_mcp_linux }, /* Linux ID */
352 { PCI_VDEVICE(NVIDIA, 0x058a), board_ahci_mcp_linux }, /* Linux ID */
353 { PCI_VDEVICE(NVIDIA, 0x058b), board_ahci_mcp_linux }, /* Linux ID */
354 { PCI_VDEVICE(NVIDIA, 0x058c), board_ahci_mcp_linux }, /* Linux ID */
355 { PCI_VDEVICE(NVIDIA, 0x058d), board_ahci_mcp_linux }, /* Linux ID */
356 { PCI_VDEVICE(NVIDIA, 0x058e), board_ahci_mcp_linux }, /* Linux ID */
357 { PCI_VDEVICE(NVIDIA, 0x058f), board_ahci_mcp_linux }, /* Linux ID */
358 { PCI_VDEVICE(NVIDIA, 0x07f0), board_ahci_mcp73 }, /* MCP73 */
359 { PCI_VDEVICE(NVIDIA, 0x07f1), board_ahci_mcp73 }, /* MCP73 */
360 { PCI_VDEVICE(NVIDIA, 0x07f2), board_ahci_mcp73 }, /* MCP73 */
361 { PCI_VDEVICE(NVIDIA, 0x07f3), board_ahci_mcp73 }, /* MCP73 */
362 { PCI_VDEVICE(NVIDIA, 0x07f4), board_ahci_mcp73 }, /* MCP73 */
363 { PCI_VDEVICE(NVIDIA, 0x07f5), board_ahci_mcp73 }, /* MCP73 */
364 { PCI_VDEVICE(NVIDIA, 0x07f6), board_ahci_mcp73 }, /* MCP73 */
365 { PCI_VDEVICE(NVIDIA, 0x07f7), board_ahci_mcp73 }, /* MCP73 */
366 { PCI_VDEVICE(NVIDIA, 0x07f8), board_ahci_mcp73 }, /* MCP73 */
367 { PCI_VDEVICE(NVIDIA, 0x07f9), board_ahci_mcp73 }, /* MCP73 */
368 { PCI_VDEVICE(NVIDIA, 0x07fa), board_ahci_mcp73 }, /* MCP73 */
369 { PCI_VDEVICE(NVIDIA, 0x07fb), board_ahci_mcp73 }, /* MCP73 */
370 { PCI_VDEVICE(NVIDIA, 0x0ad0), board_ahci_mcp77 }, /* MCP77 */
371 { PCI_VDEVICE(NVIDIA, 0x0ad1), board_ahci_mcp77 }, /* MCP77 */
372 { PCI_VDEVICE(NVIDIA, 0x0ad2), board_ahci_mcp77 }, /* MCP77 */
373 { PCI_VDEVICE(NVIDIA, 0x0ad3), board_ahci_mcp77 }, /* MCP77 */
374 { PCI_VDEVICE(NVIDIA, 0x0ad4), board_ahci_mcp77 }, /* MCP77 */
375 { PCI_VDEVICE(NVIDIA, 0x0ad5), board_ahci_mcp77 }, /* MCP77 */
376 { PCI_VDEVICE(NVIDIA, 0x0ad6), board_ahci_mcp77 }, /* MCP77 */
377 { PCI_VDEVICE(NVIDIA, 0x0ad7), board_ahci_mcp77 }, /* MCP77 */
378 { PCI_VDEVICE(NVIDIA, 0x0ad8), board_ahci_mcp77 }, /* MCP77 */
379 { PCI_VDEVICE(NVIDIA, 0x0ad9), board_ahci_mcp77 }, /* MCP77 */
380 { PCI_VDEVICE(NVIDIA, 0x0ada), board_ahci_mcp77 }, /* MCP77 */
381 { PCI_VDEVICE(NVIDIA, 0x0adb), board_ahci_mcp77 }, /* MCP77 */
382 { PCI_VDEVICE(NVIDIA, 0x0ab4), board_ahci_mcp79 }, /* MCP79 */
383 { PCI_VDEVICE(NVIDIA, 0x0ab5), board_ahci_mcp79 }, /* MCP79 */
384 { PCI_VDEVICE(NVIDIA, 0x0ab6), board_ahci_mcp79 }, /* MCP79 */
385 { PCI_VDEVICE(NVIDIA, 0x0ab7), board_ahci_mcp79 }, /* MCP79 */
386 { PCI_VDEVICE(NVIDIA, 0x0ab8), board_ahci_mcp79 }, /* MCP79 */
387 { PCI_VDEVICE(NVIDIA, 0x0ab9), board_ahci_mcp79 }, /* MCP79 */
388 { PCI_VDEVICE(NVIDIA, 0x0aba), board_ahci_mcp79 }, /* MCP79 */
389 { PCI_VDEVICE(NVIDIA, 0x0abb), board_ahci_mcp79 }, /* MCP79 */
390 { PCI_VDEVICE(NVIDIA, 0x0abc), board_ahci_mcp79 }, /* MCP79 */
391 { PCI_VDEVICE(NVIDIA, 0x0abd), board_ahci_mcp79 }, /* MCP79 */
392 { PCI_VDEVICE(NVIDIA, 0x0abe), board_ahci_mcp79 }, /* MCP79 */
393 { PCI_VDEVICE(NVIDIA, 0x0abf), board_ahci_mcp79 }, /* MCP79 */
394 { PCI_VDEVICE(NVIDIA, 0x0d84), board_ahci_mcp89 }, /* MCP89 */
395 { PCI_VDEVICE(NVIDIA, 0x0d85), board_ahci_mcp89 }, /* MCP89 */
396 { PCI_VDEVICE(NVIDIA, 0x0d86), board_ahci_mcp89 }, /* MCP89 */
397 { PCI_VDEVICE(NVIDIA, 0x0d87), board_ahci_mcp89 }, /* MCP89 */
398 { PCI_VDEVICE(NVIDIA, 0x0d88), board_ahci_mcp89 }, /* MCP89 */
399 { PCI_VDEVICE(NVIDIA, 0x0d89), board_ahci_mcp89 }, /* MCP89 */
400 { PCI_VDEVICE(NVIDIA, 0x0d8a), board_ahci_mcp89 }, /* MCP89 */
401 { PCI_VDEVICE(NVIDIA, 0x0d8b), board_ahci_mcp89 }, /* MCP89 */
402 { PCI_VDEVICE(NVIDIA, 0x0d8c), board_ahci_mcp89 }, /* MCP89 */
403 { PCI_VDEVICE(NVIDIA, 0x0d8d), board_ahci_mcp89 }, /* MCP89 */
404 { PCI_VDEVICE(NVIDIA, 0x0d8e), board_ahci_mcp89 }, /* MCP89 */
405 { PCI_VDEVICE(NVIDIA, 0x0d8f), board_ahci_mcp89 }, /* MCP89 */
fe7fa31a 406
95916edd 407 /* SiS */
20e2de4a
TH		 408 { PCI_VDEVICE(SI, 0x1184), board_ahci }, /* SiS 966 */
409 { PCI_VDEVICE(SI, 0x1185), board_ahci }, /* SiS 968 */
410 { PCI_VDEVICE(SI, 0x0186), board_ahci }, /* SiS 968 */
95916edd 411
318893e1
AR		 412 /* ST Microelectronics */
413 { PCI_VDEVICE(STMICRO, 0xCC06), board_ahci }, /* ST ConneXt */
414
cd70c266
JG		 415 /* Marvell */
416 { PCI_VDEVICE(MARVELL, 0x6145), board_ahci_mv }, /* 6145 */
c40e7cb8 417 { PCI_VDEVICE(MARVELL, 0x6121), board_ahci_mv }, /* 6121 */
69fd3157 418 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9123),
10aca06c
AH		 419 .class = PCI_CLASS_STORAGE_SATA_AHCI,
420 .class_mask = 0xffffff,
5f173107 421 .driver_data = board_ahci_yes_fbs }, /* 88se9128 */
69fd3157 422 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9125),
467b41c6 423 .driver_data = board_ahci_yes_fbs }, /* 88se9125 */
69fd3157 424 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x917a),
642d8925 425 .driver_data = board_ahci_yes_fbs }, /* 88se9172 */
69fd3157 426 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9192),
17c60c6b 427 .driver_data = board_ahci_yes_fbs }, /* 88se9172 on some Gigabyte */
69fd3157 428 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a3),
50be5e36 429 .driver_data = board_ahci_yes_fbs },
cd70c266 430
c77a036b
MN		 431 /* Promise */
432 { PCI_VDEVICE(PROMISE, 0x3f20), board_ahci }, /* PDC42819 */
433
c9703765 434 /* Asmedia */
7b4f6eca
AC		 435 { PCI_VDEVICE(ASMEDIA, 0x0601), board_ahci }, /* ASM1060 */
436 { PCI_VDEVICE(ASMEDIA, 0x0602), board_ahci }, /* ASM1060 */
437 { PCI_VDEVICE(ASMEDIA, 0x0611), board_ahci }, /* ASM1061 */
438 { PCI_VDEVICE(ASMEDIA, 0x0612), board_ahci }, /* ASM1062 */
c9703765 439
7f9c9f8e
HD		 440 /* Enmotus */
441 { PCI_DEVICE(0x1c44, 0x8000), board_ahci },
442
415ae2b5
JG		 443 /* Generic, PCI class code for AHCI */
444 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
c9f89475 445 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci },
415ae2b5 446
1da177e4
LT		 447 { } /* terminate list */
448};
449
450
451static struct pci_driver ahci_pci_driver = {
452 .name = DRV_NAME,
453 .id_table = ahci_pci_tbl,
454 .probe = ahci_init_one,
24dc5f33 455 .remove = ata_pci_remove_one,
438ac6d5 456#ifdef CONFIG_PM
c1332875 457 .suspend = ahci_pci_device_suspend,
365cfa1e
AV		 458 .resume = ahci_pci_device_resume,
459#endif
460};
1da177e4 461
365cfa1e
AV		 462#if defined(CONFIG_PATA_MARVELL) || defined(CONFIG_PATA_MARVELL_MODULE)
463static int marvell_enable;
464#else
465static int marvell_enable = 1;
466#endif
467module_param(marvell_enable, int, 0644);
468MODULE_PARM_DESC(marvell_enable, "Marvell SATA via AHCI (1 = enabled)");
d28f87aa 469
1da177e4 470
365cfa1e
AV		 471static void ahci_pci_save_initial_config(struct pci_dev *pdev,
472 struct ahci_host_priv *hpriv)
473{
474 unsigned int force_port_map = 0;
475 unsigned int mask_port_map = 0;
67846b30 476
365cfa1e
AV		 477 if (pdev->vendor == PCI_VENDOR_ID_JMICRON && pdev->device == 0x2361) {
478 dev_info(&pdev->dev, "JMB361 has only one port\n");
479 force_port_map = 1;
1da177e4
LT		 480 }
481
365cfa1e
AV		 482 /*
483 * Temporary Marvell 6145 hack: PATA port presence
484 * is asserted through the standard AHCI port
485 * presence register, as bit 4 (counting from 0)
d28f87aa 486 */
365cfa1e
AV		 487 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
488 if (pdev->device == 0x6121)
489 mask_port_map = 0x3;
490 else
491 mask_port_map = 0xf;
492 dev_info(&pdev->dev,
493 "Disabling your PATA port. Use the boot option 'ahci.marvell_enable=0' to avoid this.\n");
494 }
1da177e4 495
365cfa1e
AV		 496 ahci_save_initial_config(&pdev->dev, hpriv, force_port_map,
497 mask_port_map);
1da177e4
LT		 498}
499
365cfa1e 500static int ahci_pci_reset_controller(struct ata_host *host)
1da177e4 501{
365cfa1e 502 struct pci_dev *pdev = to_pci_dev(host->dev);
7d50b60b 503
365cfa1e 504 ahci_reset_controller(host);
1da177e4 505
365cfa1e
AV		 506 if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
507 struct ahci_host_priv *hpriv = host->private_data;
508 u16 tmp16;
d6ef3153 509
365cfa1e
AV		 510 /* configure PCS */
511 pci_read_config_word(pdev, 0x92, &tmp16);
512 if ((tmp16 & hpriv->port_map) != hpriv->port_map) {
513 tmp16 |= hpriv->port_map;
514 pci_write_config_word(pdev, 0x92, tmp16);
515 }
d6ef3153
SH		 516 }
517
1da177e4
LT		 518 return 0;
519}
520
365cfa1e 521static void ahci_pci_init_controller(struct ata_host *host)
78cd52d0 522{
365cfa1e
AV		 523 struct ahci_host_priv *hpriv = host->private_data;
524 struct pci_dev *pdev = to_pci_dev(host->dev);
525 void __iomem *port_mmio;
78cd52d0 526 u32 tmp;
365cfa1e 527 int mv;
78cd52d0 528
365cfa1e
AV		 529 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
530 if (pdev->device == 0x6121)
531 mv = 2;
532 else
533 mv = 4;
534 port_mmio = __ahci_port_base(host, mv);
78cd52d0 535
365cfa1e 536 writel(0, port_mmio + PORT_IRQ_MASK);
78cd52d0 537
365cfa1e
AV		 538 /* clear port IRQ */
539 tmp = readl(port_mmio + PORT_IRQ_STAT);
540 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
541 if (tmp)
542 writel(tmp, port_mmio + PORT_IRQ_STAT);
78cd52d0
TH		 543 }
544
365cfa1e 545 ahci_init_controller(host);
edc93052
TH		 546}
547
365cfa1e
AV		 548static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
549 unsigned long deadline)
d6ef3153 550{
365cfa1e
AV		 551 struct ata_port *ap = link->ap;
552 bool online;
d6ef3153
SH		 553 int rc;
554
365cfa1e 555 DPRINTK("ENTER\n");
d6ef3153 556
365cfa1e 557 ahci_stop_engine(ap);
d6ef3153 558
365cfa1e
AV		 559 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
560 deadline, &online, NULL);
d6ef3153
SH		 561
562 ahci_start_engine(ap);
d6ef3153 563
365cfa1e 564 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
d6ef3153 565
365cfa1e
AV		 566 /* vt8251 doesn't clear BSY on signature FIS reception,
567 * request follow-up softreset.
568 */
569 return online ? -EAGAIN : rc;
7d50b60b
TH		 570}
571
365cfa1e
AV		 572static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
573 unsigned long deadline)
7d50b60b 574{
365cfa1e 575 struct ata_port *ap = link->ap;
1c954a4d 576 struct ahci_port_priv *pp = ap->private_data;
365cfa1e
AV		 577 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
578 struct ata_taskfile tf;
579 bool online;
580 int rc;
7d50b60b 581
365cfa1e 582 ahci_stop_engine(ap);
028a2596 583
365cfa1e
AV		 584 /* clear D2H reception area to properly wait for D2H FIS */
585 ata_tf_init(link->device, &tf);
586 tf.command = 0x80;
587 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
7d50b60b 588
365cfa1e
AV		 589 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
590 deadline, &online, NULL);
028a2596 591
365cfa1e 592 ahci_start_engine(ap);
c1332875 593
365cfa1e
AV		 594 /* The pseudo configuration device on SIMG4726 attached to
595 * ASUS P5W-DH Deluxe doesn't send signature FIS after
596 * hardreset if no device is attached to the first downstream
597 * port && the pseudo device locks up on SRST w/ PMP==0. To
598 * work around this, wait for !BSY only briefly. If BSY isn't
599 * cleared, perform CLO and proceed to IDENTIFY (achieved by
600 * ATA_LFLAG_NO_SRST and ATA_LFLAG_ASSUME_ATA).
601 *
602 * Wait for two seconds. Devices attached to downstream port
603 * which can't process the following IDENTIFY after this will
604 * have to be reset again. For most cases, this should
605 * suffice while making probing snappish enough.
606 */
607 if (online) {
608 rc = ata_wait_after_reset(link, jiffies + 2 * HZ,
609 ahci_check_ready);
610 if (rc)
611 ahci_kick_engine(ap);
c1332875 612 }
c1332875
TH		 613 return rc;
614}
615
365cfa1e 616#ifdef CONFIG_PM
c1332875
TH		 617static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg)
618{
0a86e1c8 619 struct ata_host *host = pci_get_drvdata(pdev);
9b10ae86 620 struct ahci_host_priv *hpriv = host->private_data;
d8993349 621 void __iomem *mmio = hpriv->mmio;
c1332875
TH		 622 u32 ctl;
623
9b10ae86
TH		 624 if (mesg.event & PM_EVENT_SUSPEND &&
625 hpriv->flags & AHCI_HFLAG_NO_SUSPEND) {
a44fec1f
JP		 626 dev_err(&pdev->dev,
627 "BIOS update required for suspend/resume\n");
9b10ae86
TH		 628 return -EIO;
629 }
630
3a2d5b70 631 if (mesg.event & PM_EVENT_SLEEP) {
c1332875
TH		 632 /* AHCI spec rev1.1 section 8.3.3:
633 * Software must disable interrupts prior to requesting a
634 * transition of the HBA to D3 state.
635 */
636 ctl = readl(mmio + HOST_CTL);
637 ctl &= ~HOST_IRQ_EN;
638 writel(ctl, mmio + HOST_CTL);
639 readl(mmio + HOST_CTL); /* flush */
640 }
641
642 return ata_pci_device_suspend(pdev, mesg);
643}
644
645static int ahci_pci_device_resume(struct pci_dev *pdev)
646{
0a86e1c8 647 struct ata_host *host = pci_get_drvdata(pdev);
c1332875
TH		 648 int rc;
649
553c4aa6
TH		 650 rc = ata_pci_device_do_resume(pdev);
651 if (rc)
652 return rc;
c1332875
TH		 653
654 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
3303040d 655 rc = ahci_pci_reset_controller(host);
c1332875
TH		 656 if (rc)
657 return rc;
658
781d6550 659 ahci_pci_init_controller(host);
c1332875
TH		 660 }
661
cca3974e 662 ata_host_resume(host);
c1332875
TH		 663
664 return 0;
665}
438ac6d5 666#endif
c1332875 667
4447d351 668static int ahci_configure_dma_masks(struct pci_dev *pdev, int using_dac)
1da177e4 669{
1da177e4 670 int rc;
1da177e4 671
318893e1
AR		 672 /*
673 * If the device fixup already set the dma_mask to some non-standard
674 * value, don't extend it here. This happens on STA2X11, for example.
675 */
676 if (pdev->dma_mask && pdev->dma_mask < DMA_BIT_MASK(32))
677 return 0;
678
1da177e4 679 if (using_dac &&
6a35528a
YH		 680 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
681 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
1da177e4 682 if (rc) {
284901a9 683 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
1da177e4 684 if (rc) {
a44fec1f
JP		 685 dev_err(&pdev->dev,
686 "64-bit DMA enable failed\n");
1da177e4
LT		 687 return rc;
688 }
689 }
1da177e4 690 } else {
284901a9 691 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
1da177e4 692 if (rc) {
a44fec1f 693 dev_err(&pdev->dev, "32-bit DMA enable failed\n");
1da177e4
LT		 694 return rc;
695 }
284901a9 696 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
1da177e4 697 if (rc) {
a44fec1f
JP		 698 dev_err(&pdev->dev,
699 "32-bit consistent DMA enable failed\n");
1da177e4
LT		 700 return rc;
701 }
702 }
1da177e4
LT		 703 return 0;
704}
705
439fcaec
AV		 706static void ahci_pci_print_info(struct ata_host *host)
707{
708 struct pci_dev *pdev = to_pci_dev(host->dev);
709 u16 cc;
710 const char *scc_s;
711
712 pci_read_config_word(pdev, 0x0a, &cc);
713 if (cc == PCI_CLASS_STORAGE_IDE)
714 scc_s = "IDE";
715 else if (cc == PCI_CLASS_STORAGE_SATA)
716 scc_s = "SATA";
717 else if (cc == PCI_CLASS_STORAGE_RAID)
718 scc_s = "RAID";
719 else
720 scc_s = "unknown";
721
722 ahci_print_info(host, scc_s);
723}
724
edc93052
TH		 725/* On ASUS P5W DH Deluxe, the second port of PCI device 00:1f.2 is
726 * hardwired to on-board SIMG 4726. The chipset is ICH8 and doesn't
727 * support PMP and the 4726 either directly exports the device
728 * attached to the first downstream port or acts as a hardware storage
729 * controller and emulate a single ATA device (can be RAID 0/1 or some
730 * other configuration).
731 *
732 * When there's no device attached to the first downstream port of the
733 * 4726, "Config Disk" appears, which is a pseudo ATA device to
734 * configure the 4726. However, ATA emulation of the device is very
735 * lame. It doesn't send signature D2H Reg FIS after the initial
736 * hardreset, pukes on SRST w/ PMP==0 and has bunch of other issues.
737 *
738 * The following function works around the problem by always using
739 * hardreset on the port and not depending on receiving signature FIS
740 * afterward. If signature FIS isn't received soon, ATA class is
741 * assumed without follow-up softreset.
742 */
743static void ahci_p5wdh_workaround(struct ata_host *host)
744{
745 static struct dmi_system_id sysids[] = {
746 {
747 .ident = "P5W DH Deluxe",
748 .matches = {
749 DMI_MATCH(DMI_SYS_VENDOR,
750 "ASUSTEK COMPUTER INC"),
751 DMI_MATCH(DMI_PRODUCT_NAME, "P5W DH Deluxe"),
752 },
753 },
754 { }
755 };
756 struct pci_dev *pdev = to_pci_dev(host->dev);
757
758 if (pdev->bus->number == 0 && pdev->devfn == PCI_DEVFN(0x1f, 2) &&
759 dmi_check_system(sysids)) {
760 struct ata_port *ap = host->ports[1];
761
a44fec1f
JP		 762 dev_info(&pdev->dev,
763 "enabling ASUS P5W DH Deluxe on-board SIMG4726 workaround\n");
edc93052
TH		 764
765 ap->ops = &ahci_p5wdh_ops;
766 ap->link.flags |= ATA_LFLAG_NO_SRST | ATA_LFLAG_ASSUME_ATA;
767 }
768}
769
2fcad9d2
TH		 770/* only some SB600 ahci controllers can do 64bit DMA */
771static bool ahci_sb600_enable_64bit(struct pci_dev *pdev)
58a09b38
SH		 772{
773 static const struct dmi_system_id sysids[] = {
03d783bf
TH		 774 /*
775 * The oldest version known to be broken is 0901 and
776 * working is 1501 which was released on 2007-10-26.
2fcad9d2
TH		 777 * Enable 64bit DMA on 1501 and anything newer.
778 *
03d783bf
TH		 779 * Please read bko#9412 for more info.
780 */
58a09b38
SH		 781 {
782 .ident = "ASUS M2A-VM",
783 .matches = {
784 DMI_MATCH(DMI_BOARD_VENDOR,
785 "ASUSTeK Computer INC."),
786 DMI_MATCH(DMI_BOARD_NAME, "M2A-VM"),
787 },
03d783bf 788 .driver_data = "20071026", /* yyyymmdd */
58a09b38 789 },
e65cc194
MN		 790 /*
791 * All BIOS versions for the MSI K9A2 Platinum (MS-7376)
792 * support 64bit DMA.
793 *
794 * BIOS versions earlier than 1.5 had the Manufacturer DMI
795 * fields as "MICRO-STAR INTERANTIONAL CO.,LTD".
796 * This spelling mistake was fixed in BIOS version 1.5, so
797 * 1.5 and later have the Manufacturer as
798 * "MICRO-STAR INTERNATIONAL CO.,LTD".
799 * So try to match on DMI_BOARD_VENDOR of "MICRO-STAR INTER".
800 *
801 * BIOS versions earlier than 1.9 had a Board Product Name
802 * DMI field of "MS-7376". This was changed to be
803 * "K9A2 Platinum (MS-7376)" in version 1.9, but we can still
804 * match on DMI_BOARD_NAME of "MS-7376".
805 */
806 {
807 .ident = "MSI K9A2 Platinum",
808 .matches = {
809 DMI_MATCH(DMI_BOARD_VENDOR,
810 "MICRO-STAR INTER"),
811 DMI_MATCH(DMI_BOARD_NAME, "MS-7376"),
812 },
813 },
ff0173c1
MN		 814 /*
815 * All BIOS versions for the MSI K9AGM2 (MS-7327) support
816 * 64bit DMA.
817 *
818 * This board also had the typo mentioned above in the
819 * Manufacturer DMI field (fixed in BIOS version 1.5), so
820 * match on DMI_BOARD_VENDOR of "MICRO-STAR INTER" again.
821 */
822 {
823 .ident = "MSI K9AGM2",
824 .matches = {
825 DMI_MATCH(DMI_BOARD_VENDOR,
826 "MICRO-STAR INTER"),
827 DMI_MATCH(DMI_BOARD_NAME, "MS-7327"),
828 },
829 },
3c4aa91f
MN		 830 /*
831 * All BIOS versions for the Asus M3A support 64bit DMA.
832 * (all release versions from 0301 to 1206 were tested)
833 */
834 {
835 .ident = "ASUS M3A",
836 .matches = {
837 DMI_MATCH(DMI_BOARD_VENDOR,
838 "ASUSTeK Computer INC."),
839 DMI_MATCH(DMI_BOARD_NAME, "M3A"),
840 },
841 },
58a09b38
SH		 842 { }
843 };
03d783bf 844 const struct dmi_system_id *match;
2fcad9d2
TH		 845 int year, month, date;
846 char buf[9];
58a09b38 847
03d783bf 848 match = dmi_first_match(sysids);
58a09b38 849 if (pdev->bus->number != 0 || pdev->devfn != PCI_DEVFN(0x12, 0) ||
03d783bf 850 !match)
58a09b38
SH		 851 return false;
852
e65cc194
MN		 853 if (!match->driver_data)
854 goto enable_64bit;
855
2fcad9d2
TH		 856 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
857 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
03d783bf 858
e65cc194
MN		 859 if (strcmp(buf, match->driver_data) >= 0)
860 goto enable_64bit;
861 else {
a44fec1f
JP		 862 dev_warn(&pdev->dev,
863 "%s: BIOS too old, forcing 32bit DMA, update BIOS\n",
864 match->ident);
2fcad9d2
TH		 865 return false;
866 }
e65cc194
MN		 867
868enable_64bit:
a44fec1f 869 dev_warn(&pdev->dev, "%s: enabling 64bit DMA\n", match->ident);
e65cc194 870 return true;
58a09b38
SH		 871}
872
1fd68434
RW		 873static bool ahci_broken_system_poweroff(struct pci_dev *pdev)
874{
875 static const struct dmi_system_id broken_systems[] = {
876 {
877 .ident = "HP Compaq nx6310",
878 .matches = {
879 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
880 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq nx6310"),
881 },
882 /* PCI slot number of the controller */
883 .driver_data = (void *)0x1FUL,
884 },
d2f9c061
MR		 885 {
886 .ident = "HP Compaq 6720s",
887 .matches = {
888 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
889 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq 6720s"),
890 },
891 /* PCI slot number of the controller */
892 .driver_data = (void *)0x1FUL,
893 },
1fd68434
RW		 894
895 { } /* terminate list */
896 };
897 const struct dmi_system_id *dmi = dmi_first_match(broken_systems);
898
899 if (dmi) {
900 unsigned long slot = (unsigned long)dmi->driver_data;
901 /* apply the quirk only to on-board controllers */
902 return slot == PCI_SLOT(pdev->devfn);
903 }
904
905 return false;
906}
907
9b10ae86
TH		 908static bool ahci_broken_suspend(struct pci_dev *pdev)
909{
910 static const struct dmi_system_id sysids[] = {
911 /*
912 * On HP dv[4-6] and HDX18 with earlier BIOSen, link
913 * to the harddisk doesn't become online after
914 * resuming from STR. Warn and fail suspend.
9deb3431
TH		 915 *
916 * http://bugzilla.kernel.org/show_bug.cgi?id=12276
917 *
918 * Use dates instead of versions to match as HP is
919 * apparently recycling both product and version
920 * strings.
921 *
922 * http://bugzilla.kernel.org/show_bug.cgi?id=15462
9b10ae86
TH		 923 */
924 {
925 .ident = "dv4",
926 .matches = {
927 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
928 DMI_MATCH(DMI_PRODUCT_NAME,
929 "HP Pavilion dv4 Notebook PC"),
930 },
9deb3431 931 .driver_data = "20090105", /* F.30 */
9b10ae86
TH		 932 },
933 {
934 .ident = "dv5",
935 .matches = {
936 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
937 DMI_MATCH(DMI_PRODUCT_NAME,
938 "HP Pavilion dv5 Notebook PC"),
939 },
9deb3431 940 .driver_data = "20090506", /* F.16 */
9b10ae86
TH		 941 },
942 {
943 .ident = "dv6",
944 .matches = {
945 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
946 DMI_MATCH(DMI_PRODUCT_NAME,
947 "HP Pavilion dv6 Notebook PC"),
948 },
9deb3431 949 .driver_data = "20090423", /* F.21 */
9b10ae86
TH		 950 },
951 {
952 .ident = "HDX18",
953 .matches = {
954 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
955 DMI_MATCH(DMI_PRODUCT_NAME,
956 "HP HDX18 Notebook PC"),
957 },
9deb3431 958 .driver_data = "20090430", /* F.23 */
9b10ae86 959 },
cedc9bf9
TH		 960 /*
961 * Acer eMachines G725 has the same problem. BIOS
962 * V1.03 is known to be broken. V3.04 is known to
25985edc 963 * work. Between, there are V1.06, V2.06 and V3.03
cedc9bf9
TH		 964 * that we don't have much idea about. For now,
965 * blacklist anything older than V3.04.
9deb3431
TH		 966 *
967 * http://bugzilla.kernel.org/show_bug.cgi?id=15104
cedc9bf9
TH		 968 */
969 {
970 .ident = "G725",
971 .matches = {
972 DMI_MATCH(DMI_SYS_VENDOR, "eMachines"),
973 DMI_MATCH(DMI_PRODUCT_NAME, "eMachines G725"),
974 },
9deb3431 975 .driver_data = "20091216", /* V3.04 */
cedc9bf9 976 },
9b10ae86
TH		 977 { } /* terminate list */
978 };
979 const struct dmi_system_id *dmi = dmi_first_match(sysids);
9deb3431
TH		 980 int year, month, date;
981 char buf[9];
9b10ae86
TH		 982
983 if (!dmi || pdev->bus->number || pdev->devfn != PCI_DEVFN(0x1f, 2))
984 return false;
985
9deb3431
TH		 986 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
987 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
9b10ae86 988
9deb3431 989 return strcmp(buf, dmi->driver_data) < 0;
9b10ae86
TH		 990}
991
5594639a
TH		 992static bool ahci_broken_online(struct pci_dev *pdev)
993{
994#define ENCODE_BUSDEVFN(bus, slot, func) \
995 (void *)(unsigned long)(((bus) << 8) | PCI_DEVFN((slot), (func)))
996 static const struct dmi_system_id sysids[] = {
997 /*
998 * There are several gigabyte boards which use
999 * SIMG5723s configured as hardware RAID. Certain
1000 * 5723 firmware revisions shipped there keep the link
1001 * online but fail to answer properly to SRST or
1002 * IDENTIFY when no device is attached downstream
1003 * causing libata to retry quite a few times leading
1004 * to excessive detection delay.
1005 *
1006 * As these firmwares respond to the second reset try
1007 * with invalid device signature, considering unknown
1008 * sig as offline works around the problem acceptably.
1009 */
1010 {
1011 .ident = "EP45-DQ6",
1012 .matches = {
1013 DMI_MATCH(DMI_BOARD_VENDOR,
1014 "Gigabyte Technology Co., Ltd."),
1015 DMI_MATCH(DMI_BOARD_NAME, "EP45-DQ6"),
1016 },
1017 .driver_data = ENCODE_BUSDEVFN(0x0a, 0x00, 0),
1018 },
1019 {
1020 .ident = "EP45-DS5",
1021 .matches = {
1022 DMI_MATCH(DMI_BOARD_VENDOR,
1023 "Gigabyte Technology Co., Ltd."),
1024 DMI_MATCH(DMI_BOARD_NAME, "EP45-DS5"),
1025 },
1026 .driver_data = ENCODE_BUSDEVFN(0x03, 0x00, 0),
1027 },
1028 { } /* terminate list */
1029 };
1030#undef ENCODE_BUSDEVFN
1031 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1032 unsigned int val;
1033
1034 if (!dmi)
1035 return false;
1036
1037 val = (unsigned long)dmi->driver_data;
1038
1039 return pdev->bus->number == (val >> 8) && pdev->devfn == (val & 0xff);
1040}
1041
8e513217 1042#ifdef CONFIG_ATA_ACPI
f80ae7e4
TH		 1043static void ahci_gtf_filter_workaround(struct ata_host *host)
1044{
1045 static const struct dmi_system_id sysids[] = {
1046 /*
1047 * Aspire 3810T issues a bunch of SATA enable commands
1048 * via _GTF including an invalid one and one which is
1049 * rejected by the device. Among the successful ones
1050 * is FPDMA non-zero offset enable which when enabled
1051 * only on the drive side leads to NCQ command
1052 * failures. Filter it out.
1053 */
1054 {
1055 .ident = "Aspire 3810T",
1056 .matches = {
1057 DMI_MATCH(DMI_SYS_VENDOR, "Acer"),
1058 DMI_MATCH(DMI_PRODUCT_NAME, "Aspire 3810T"),
1059 },
1060 .driver_data = (void *)ATA_ACPI_FILTER_FPDMA_OFFSET,
1061 },
1062 { }
1063 };
1064 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1065 unsigned int filter;
1066 int i;
1067
1068 if (!dmi)
1069 return;
1070
1071 filter = (unsigned long)dmi->driver_data;
a44fec1f
JP		 1072 dev_info(host->dev, "applying extra ACPI _GTF filter 0x%x for %s\n",
1073 filter, dmi->ident);
f80ae7e4
TH		 1074
1075 for (i = 0; i < host->n_ports; i++) {
1076 struct ata_port *ap = host->ports[i];
1077 struct ata_link *link;
1078 struct ata_device *dev;
1079
1080 ata_for_each_link(link, ap, EDGE)
1081 ata_for_each_dev(dev, link, ALL)
1082 dev->gtf_filter |= filter;
1083 }
1084}
8e513217
MT		 1085#else
1086static inline void ahci_gtf_filter_workaround(struct ata_host *host)
1087{}
1088#endif
f80ae7e4 1089
5ca72c4f
AG		 1090int ahci_init_interrupts(struct pci_dev *pdev, struct ahci_host_priv *hpriv)
1091{
1092 int rc;
1093 unsigned int maxvec;
1094
1095 if (!(hpriv->flags & AHCI_HFLAG_NO_MSI)) {
1096 rc = pci_enable_msi_block_auto(pdev, &maxvec);
1097 if (rc > 0) {
1098 if ((rc == maxvec) || (rc == 1))
1099 return rc;
1100 /*
1101 * Assume that advantage of multipe MSIs is negated,
1102 * so fallback to single MSI mode to save resources
1103 */
1104 pci_disable_msi(pdev);
1105 if (!pci_enable_msi(pdev))
1106 return 1;
1107 }
1108 }
1109
1110 pci_intx(pdev, 1);
1111 return 0;
1112}
1113
1114/**
1115 * ahci_host_activate - start AHCI host, request IRQs and register it
1116 * @host: target ATA host
1117 * @irq: base IRQ number to request
1118 * @n_msis: number of MSIs allocated for this host
1119 * @irq_handler: irq_handler used when requesting IRQs
1120 * @irq_flags: irq_flags used when requesting IRQs
1121 *
1122 * Similar to ata_host_activate, but requests IRQs according to AHCI-1.1
1123 * when multiple MSIs were allocated. That is one MSI per port, starting
1124 * from @irq.
1125 *
1126 * LOCKING:
1127 * Inherited from calling layer (may sleep).
1128 *
1129 * RETURNS:
1130 * 0 on success, -errno otherwise.
1131 */
1132int ahci_host_activate(struct ata_host *host, int irq, unsigned int n_msis)
1133{
1134 int i, rc;
1135
1136 /* Sharing Last Message among several ports is not supported */
1137 if (n_msis < host->n_ports)
1138 return -EINVAL;
1139
1140 rc = ata_host_start(host);
1141 if (rc)
1142 return rc;
1143
1144 for (i = 0; i < host->n_ports; i++) {
b29900e6
AG		 1145 struct ahci_port_priv *pp = host->ports[i]->private_data;
1146
5ca72c4f
AG		 1147 rc = devm_request_threaded_irq(host->dev,
1148 irq + i, ahci_hw_interrupt, ahci_thread_fn, IRQF_SHARED,
b29900e6 1149 pp->irq_desc, host->ports[i]);
5ca72c4f
AG		 1150 if (rc)
1151 goto out_free_irqs;
1152 }
1153
1154 for (i = 0; i < host->n_ports; i++)
1155 ata_port_desc(host->ports[i], "irq %d", irq + i);
1156
1157 rc = ata_host_register(host, &ahci_sht);
1158 if (rc)
1159 goto out_free_all_irqs;
1160
1161 return 0;
1162
1163out_free_all_irqs:
1164 i = host->n_ports;
1165out_free_irqs:
1166 for (i--; i >= 0; i--)
1167 devm_free_irq(host->dev, irq + i, host->ports[i]);
1168
1169 return rc;
1170}
1171
24dc5f33 1172static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1da177e4 1173{
e297d99e
TH		 1174 unsigned int board_id = ent->driver_data;
1175 struct ata_port_info pi = ahci_port_info[board_id];
4447d351 1176 const struct ata_port_info *ppi[] = { &pi, NULL };
24dc5f33 1177 struct device *dev = &pdev->dev;
1da177e4 1178 struct ahci_host_priv *hpriv;
4447d351 1179 struct ata_host *host;
5ca72c4f 1180 int n_ports, n_msis, i, rc;
318893e1 1181 int ahci_pci_bar = AHCI_PCI_BAR_STANDARD;
1da177e4
LT		 1182
1183 VPRINTK("ENTER\n");
1184
b429dd59 1185 WARN_ON((int)ATA_MAX_QUEUE > AHCI_MAX_CMDS);
12fad3f9 1186
06296a1e 1187 ata_print_version_once(&pdev->dev, DRV_VERSION);
1da177e4 1188
5b66c829
AC		 1189 /* The AHCI driver can only drive the SATA ports, the PATA driver
1190 can drive them all so if both drivers are selected make sure
1191 AHCI stays out of the way */
1192 if (pdev->vendor == PCI_VENDOR_ID_MARVELL && !marvell_enable)
1193 return -ENODEV;
1194
c6353b45
TH		 1195 /*
1196 * For some reason, MCP89 on MacBook 7,1 doesn't work with
1197 * ahci, use ata_generic instead.
1198 */
1199 if (pdev->vendor == PCI_VENDOR_ID_NVIDIA &&
1200 pdev->device == PCI_DEVICE_ID_NVIDIA_NFORCE_MCP89_SATA &&
1201 pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE &&
1202 pdev->subsystem_device == 0xcb89)
1203 return -ENODEV;
1204
7a02267e
MN		 1205 /* Promise's PDC42819 is a SAS/SATA controller that has an AHCI mode.
1206 * At the moment, we can only use the AHCI mode. Let the users know
1207 * that for SAS drives they're out of luck.
1208 */
1209 if (pdev->vendor == PCI_VENDOR_ID_PROMISE)
a44fec1f
JP		 1210 dev_info(&pdev->dev,
1211 "PDC42819 can only drive SATA devices with this driver\n");
7a02267e 1212
7f9c9f8e 1213 /* Both Connext and Enmotus devices use non-standard BARs */
318893e1
AR		 1214 if (pdev->vendor == PCI_VENDOR_ID_STMICRO && pdev->device == 0xCC06)
1215 ahci_pci_bar = AHCI_PCI_BAR_STA2X11;
7f9c9f8e
HD		 1216 else if (pdev->vendor == 0x1c44 && pdev->device == 0x8000)
1217 ahci_pci_bar = AHCI_PCI_BAR_ENMOTUS;
318893e1 1218
4447d351 1219 /* acquire resources */
24dc5f33 1220 rc = pcim_enable_device(pdev);
1da177e4
LT		 1221 if (rc)
1222 return rc;
1223
dea55137
TH		 1224 /* AHCI controllers often implement SFF compatible interface.
1225 * Grab all PCI BARs just in case.
1226 */
318893e1 1227 rc = pcim_iomap_regions_request_all(pdev, 1 << ahci_pci_bar, DRV_NAME);
0d5ff566 1228 if (rc == -EBUSY)
24dc5f33 1229 pcim_pin_device(pdev);
0d5ff566 1230 if (rc)
24dc5f33 1231 return rc;
1da177e4 1232
c4f7792c
TH		 1233 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
1234 (pdev->device == 0x2652 || pdev->device == 0x2653)) {
1235 u8 map;
1236
1237 /* ICH6s share the same PCI ID for both piix and ahci
1238 * modes. Enabling ahci mode while MAP indicates
1239 * combined mode is a bad idea. Yield to ata_piix.
1240 */
1241 pci_read_config_byte(pdev, ICH_MAP, &map);
1242 if (map & 0x3) {
a44fec1f
JP		 1243 dev_info(&pdev->dev,
1244 "controller is in combined mode, can't enable AHCI mode\n");
c4f7792c
TH		 1245 return -ENODEV;
1246 }
1247 }
1248
24dc5f33
TH		 1249 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
1250 if (!hpriv)
1251 return -ENOMEM;
417a1a6d
TH		 1252 hpriv->flags |= (unsigned long)pi.private_data;
1253
e297d99e
TH		 1254 /* MCP65 revision A1 and A2 can't do MSI */
1255 if (board_id == board_ahci_mcp65 &&
1256 (pdev->revision == 0xa1 || pdev->revision == 0xa2))
1257 hpriv->flags |= AHCI_HFLAG_NO_MSI;
1258
e427fe04
SH		 1259 /* SB800 does NOT need the workaround to ignore SERR_INTERNAL */
1260 if (board_id == board_ahci_sb700 && pdev->revision >= 0x40)
1261 hpriv->flags &= ~AHCI_HFLAG_IGN_SERR_INTERNAL;
1262
2fcad9d2
TH		 1263 /* only some SB600s can do 64bit DMA */
1264 if (ahci_sb600_enable_64bit(pdev))
1265 hpriv->flags &= ~AHCI_HFLAG_32BIT_ONLY;
58a09b38 1266
318893e1 1267 hpriv->mmio = pcim_iomap_table(pdev)[ahci_pci_bar];
d8993349 1268
5ca72c4f
AG		 1269 n_msis = ahci_init_interrupts(pdev, hpriv);
1270 if (n_msis > 1)
1271 hpriv->flags |= AHCI_HFLAG_MULTI_MSI;
1272
4447d351 1273 /* save initial config */
394d6e53 1274 ahci_pci_save_initial_config(pdev, hpriv);
1da177e4 1275
4447d351 1276 /* prepare host */
453d3131
RH		 1277 if (hpriv->cap & HOST_CAP_NCQ) {
1278 pi.flags |= ATA_FLAG_NCQ;
83f2b963
TH		 1279 /*
1280 * Auto-activate optimization is supposed to be
1281 * supported on all AHCI controllers indicating NCQ
1282 * capability, but it seems to be broken on some
1283 * chipsets including NVIDIAs.
1284 */
1285 if (!(hpriv->flags & AHCI_HFLAG_NO_FPDMA_AA))
453d3131
RH		 1286 pi.flags |= ATA_FLAG_FPDMA_AA;
1287 }
1da177e4 1288
7d50b60b
TH		 1289 if (hpriv->cap & HOST_CAP_PMP)
1290 pi.flags |= ATA_FLAG_PMP;
1291
0cbb0e77 1292 ahci_set_em_messages(hpriv, &pi);
18f7ba4c 1293
1fd68434
RW		 1294 if (ahci_broken_system_poweroff(pdev)) {
1295 pi.flags |= ATA_FLAG_NO_POWEROFF_SPINDOWN;
1296 dev_info(&pdev->dev,
1297 "quirky BIOS, skipping spindown on poweroff\n");
1298 }
1299
9b10ae86
TH		 1300 if (ahci_broken_suspend(pdev)) {
1301 hpriv->flags |= AHCI_HFLAG_NO_SUSPEND;
a44fec1f
JP		 1302 dev_warn(&pdev->dev,
1303 "BIOS update required for suspend/resume\n");
9b10ae86
TH		 1304 }
1305
5594639a
TH		 1306 if (ahci_broken_online(pdev)) {
1307 hpriv->flags |= AHCI_HFLAG_SRST_TOUT_IS_OFFLINE;
1308 dev_info(&pdev->dev,
1309 "online status unreliable, applying workaround\n");
1310 }
1311
837f5f8f
TH		 1312 /* CAP.NP sometimes indicate the index of the last enabled
1313 * port, at other times, that of the last possible port, so
1314 * determining the maximum port number requires looking at
1315 * both CAP.NP and port_map.
1316 */
1317 n_ports = max(ahci_nr_ports(hpriv->cap), fls(hpriv->port_map));
1318
1319 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
4447d351
TH		 1320 if (!host)
1321 return -ENOMEM;
4447d351
TH		 1322 host->private_data = hpriv;
1323
f3d7f23f 1324 if (!(hpriv->cap & HOST_CAP_SSS) || ahci_ignore_sss)
886ad09f 1325 host->flags |= ATA_HOST_PARALLEL_SCAN;
f3d7f23f
AV		 1326 else
1327 printk(KERN_INFO "ahci: SSS flag set, parallel bus scan disabled\n");
886ad09f 1328
18f7ba4c
KCA		 1329 if (pi.flags & ATA_FLAG_EM)
1330 ahci_reset_em(host);
1331
4447d351 1332 for (i = 0; i < host->n_ports; i++) {
dab632e8 1333 struct ata_port *ap = host->ports[i];
4447d351 1334
318893e1
AR		 1335 ata_port_pbar_desc(ap, ahci_pci_bar, -1, "abar");
1336 ata_port_pbar_desc(ap, ahci_pci_bar,
cbcdd875
TH		 1337 0x100 + ap->port_no * 0x80, "port");
1338
18f7ba4c
KCA		 1339 /* set enclosure management message type */
1340 if (ap->flags & ATA_FLAG_EM)
008dbd61 1341 ap->em_message_type = hpriv->em_msg_type;
18f7ba4c
KCA		 1342
1343
dab632e8 1344 /* disabled/not-implemented port */
350756f6 1345 if (!(hpriv->port_map & (1 << i)))
dab632e8 1346 ap->ops = &ata_dummy_port_ops;
4447d351 1347 }
d447df14 1348
edc93052
TH		 1349 /* apply workaround for ASUS P5W DH Deluxe mainboard */
1350 ahci_p5wdh_workaround(host);
1351
f80ae7e4
TH		 1352 /* apply gtf filter quirk */
1353 ahci_gtf_filter_workaround(host);
1354
4447d351
TH		 1355 /* initialize adapter */
1356 rc = ahci_configure_dma_masks(pdev, hpriv->cap & HOST_CAP_64);
1da177e4 1357 if (rc)
24dc5f33 1358 return rc;
1da177e4 1359
3303040d 1360 rc = ahci_pci_reset_controller(host);
4447d351
TH		 1361 if (rc)
1362 return rc;
1da177e4 1363
781d6550 1364 ahci_pci_init_controller(host);
439fcaec 1365 ahci_pci_print_info(host);
1da177e4 1366
4447d351 1367 pci_set_master(pdev);
5ca72c4f
AG		 1368
1369 if (hpriv->flags & AHCI_HFLAG_MULTI_MSI)
1370 return ahci_host_activate(host, pdev->irq, n_msis);
1371
4447d351
TH		 1372 return ata_host_activate(host, pdev->irq, ahci_interrupt, IRQF_SHARED,
1373 &ahci_sht);
907f4678 1374}
1da177e4 1375
2fc75da0 1376module_pci_driver(ahci_pci_driver);
1da177e4
LT		 1377
1378MODULE_AUTHOR("Jeff Garzik");
1379MODULE_DESCRIPTION("AHCI SATA low-level driver");
1380MODULE_LICENSE("GPL");
1381MODULE_DEVICE_TABLE(pci, ahci_pci_tbl);
6885433c 1382MODULE_VERSION(DRV_VERSION);
Linux kernel - Deliverables
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