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ata_piix: Add Device IDs for Intel Wellsburg PCH
[deliverable/linux.git] / drivers / ata / ahci.c
CommitLineData
1da177e4
LT		 1/*
2 * ahci.c - AHCI SATA support
3 *
af36d7f0
JG		 4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
7 *
8 * Copyright 2004-2005 Red Hat, Inc.
9 *
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
24 *
25 *
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
28 *
29 * AHCI hardware documentation:
1da177e4 30 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
af36d7f0 31 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
1da177e4
LT		 32 *
33 */
34
35#include <linux/kernel.h>
36#include <linux/module.h>
37#include <linux/pci.h>
38#include <linux/init.h>
39#include <linux/blkdev.h>
40#include <linux/delay.h>
41#include <linux/interrupt.h>
87507cfd 42#include <linux/dma-mapping.h>
a9524a76 43#include <linux/device.h>
edc93052 44#include <linux/dmi.h>
5a0e3ad6 45#include <linux/gfp.h>
1da177e4 46#include <scsi/scsi_host.h>
193515d5 47#include <scsi/scsi_cmnd.h>
1da177e4 48#include <linux/libata.h>
365cfa1e 49#include "ahci.h"
1da177e4
LT		 50
51#define DRV_NAME "ahci"
7d50b60b 52#define DRV_VERSION "3.0"
1da177e4 53
1da177e4 54enum {
318893e1 55 AHCI_PCI_BAR_STA2X11 = 0,
7f9c9f8e 56 AHCI_PCI_BAR_ENMOTUS = 2,
318893e1 57 AHCI_PCI_BAR_STANDARD = 5,
441577ef
TH		 58};
59
60enum board_ids {
61 /* board IDs by feature in alphabetical order */
62 board_ahci,
63 board_ahci_ign_iferr,
64 board_ahci_nosntf,
5f173107 65 board_ahci_yes_fbs,
1da177e4 66
441577ef
TH		 67 /* board IDs for specific chipsets in alphabetical order */
68 board_ahci_mcp65,
83f2b963
TH		 69 board_ahci_mcp77,
70 board_ahci_mcp89,
441577ef
TH		 71 board_ahci_mv,
72 board_ahci_sb600,
73 board_ahci_sb700, /* for SB700 and SB800 */
74 board_ahci_vt8251,
75
76 /* aliases */
77 board_ahci_mcp_linux = board_ahci_mcp65,
78 board_ahci_mcp67 = board_ahci_mcp65,
79 board_ahci_mcp73 = board_ahci_mcp65,
83f2b963 80 board_ahci_mcp79 = board_ahci_mcp77,
1da177e4
LT		 81};
82
2dcb407e 83static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
a1efdaba
TH		 84static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
85 unsigned long deadline);
86static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
87 unsigned long deadline);
438ac6d5 88#ifdef CONFIG_PM
c1332875
TH		 89static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg);
90static int ahci_pci_device_resume(struct pci_dev *pdev);
438ac6d5 91#endif
ad616ffb 92
fad16e7a
TH		 93static struct scsi_host_template ahci_sht = {
94 AHCI_SHT("ahci"),
95};
96
029cfd6b
TH		 97static struct ata_port_operations ahci_vt8251_ops = {
98 .inherits = &ahci_ops,
a1efdaba 99 .hardreset = ahci_vt8251_hardreset,
029cfd6b 100};
edc93052 101
029cfd6b
TH		 102static struct ata_port_operations ahci_p5wdh_ops = {
103 .inherits = &ahci_ops,
a1efdaba 104 .hardreset = ahci_p5wdh_hardreset,
edc93052
TH		 105};
106
98ac62de 107static const struct ata_port_info ahci_port_info[] = {
441577ef 108 /* by features */
facb8fa6 109 [board_ahci] = {
1188c0d8 110 .flags = AHCI_FLAG_COMMON,
14bdef98 111 .pio_mask = ATA_PIO4,
469248ab 112 .udma_mask = ATA_UDMA6,
1da177e4
LT		 113 .port_ops = &ahci_ops,
114 },
facb8fa6 115 [board_ahci_ign_iferr] = {
441577ef 116 AHCI_HFLAGS (AHCI_HFLAG_IGN_IRQ_IF_ERR),
417a1a6d 117 .flags = AHCI_FLAG_COMMON,
14bdef98 118 .pio_mask = ATA_PIO4,
469248ab 119 .udma_mask = ATA_UDMA6,
441577ef 120 .port_ops = &ahci_ops,
bf2af2a2 121 },
facb8fa6 122 [board_ahci_nosntf] = {
441577ef 123 AHCI_HFLAGS (AHCI_HFLAG_NO_SNTF),
417a1a6d 124 .flags = AHCI_FLAG_COMMON,
14bdef98 125 .pio_mask = ATA_PIO4,
469248ab 126 .udma_mask = ATA_UDMA6,
41669553
TH		 127 .port_ops = &ahci_ops,
128 },
facb8fa6 129 [board_ahci_yes_fbs] = {
5f173107
TH		 130 AHCI_HFLAGS (AHCI_HFLAG_YES_FBS),
131 .flags = AHCI_FLAG_COMMON,
132 .pio_mask = ATA_PIO4,
133 .udma_mask = ATA_UDMA6,
134 .port_ops = &ahci_ops,
135 },
441577ef 136 /* by chipsets */
facb8fa6 137 [board_ahci_mcp65] = {
83f2b963
TH		 138 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP |
139 AHCI_HFLAG_YES_NCQ),
ae01b249 140 .flags = AHCI_FLAG_COMMON | ATA_FLAG_NO_DIPM,
83f2b963
TH		 141 .pio_mask = ATA_PIO4,
142 .udma_mask = ATA_UDMA6,
143 .port_ops = &ahci_ops,
144 },
facb8fa6 145 [board_ahci_mcp77] = {
83f2b963
TH		 146 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP),
147 .flags = AHCI_FLAG_COMMON,
148 .pio_mask = ATA_PIO4,
149 .udma_mask = ATA_UDMA6,
150 .port_ops = &ahci_ops,
151 },
facb8fa6 152 [board_ahci_mcp89] = {
83f2b963 153 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA),
417a1a6d 154 .flags = AHCI_FLAG_COMMON,
14bdef98 155 .pio_mask = ATA_PIO4,
469248ab 156 .udma_mask = ATA_UDMA6,
441577ef 157 .port_ops = &ahci_ops,
55a61604 158 },
facb8fa6 159 [board_ahci_mv] = {
417a1a6d 160 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_MSI |
17248461 161 AHCI_HFLAG_MV_PATA | AHCI_HFLAG_NO_PMP),
9cbe056f 162 .flags = ATA_FLAG_SATA | ATA_FLAG_PIO_DMA,
14bdef98 163 .pio_mask = ATA_PIO4,
cd70c266
JG		 164 .udma_mask = ATA_UDMA6,
165 .port_ops = &ahci_ops,
166 },
facb8fa6 167 [board_ahci_sb600] = {
441577ef
TH		 168 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL |
169 AHCI_HFLAG_NO_MSI | AHCI_HFLAG_SECT255 |
170 AHCI_HFLAG_32BIT_ONLY),
e39fc8c9 171 .flags = AHCI_FLAG_COMMON,
14bdef98 172 .pio_mask = ATA_PIO4,
e39fc8c9 173 .udma_mask = ATA_UDMA6,
345347c5 174 .port_ops = &ahci_pmp_retry_srst_ops,
e39fc8c9 175 },
facb8fa6 176 [board_ahci_sb700] = { /* for SB700 and SB800 */
441577ef 177 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL),
aa431dd3
TH		 178 .flags = AHCI_FLAG_COMMON,
179 .pio_mask = ATA_PIO4,
180 .udma_mask = ATA_UDMA6,
345347c5 181 .port_ops = &ahci_pmp_retry_srst_ops,
aa431dd3 182 },
facb8fa6 183 [board_ahci_vt8251] = {
441577ef 184 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_PMP),
1b677afd
SL		 185 .flags = AHCI_FLAG_COMMON,
186 .pio_mask = ATA_PIO4,
187 .udma_mask = ATA_UDMA6,
441577ef 188 .port_ops = &ahci_vt8251_ops,
1b677afd 189 },
1da177e4
LT		 190};
191
3b7d697d 192static const struct pci_device_id ahci_pci_tbl[] = {
fe7fa31a 193 /* Intel */
54bb3a94
JG		 194 { PCI_VDEVICE(INTEL, 0x2652), board_ahci }, /* ICH6 */
195 { PCI_VDEVICE(INTEL, 0x2653), board_ahci }, /* ICH6M */
196 { PCI_VDEVICE(INTEL, 0x27c1), board_ahci }, /* ICH7 */
197 { PCI_VDEVICE(INTEL, 0x27c5), board_ahci }, /* ICH7M */
198 { PCI_VDEVICE(INTEL, 0x27c3), board_ahci }, /* ICH7R */
82490c09 199 { PCI_VDEVICE(AL, 0x5288), board_ahci_ign_iferr }, /* ULi M5288 */
54bb3a94
JG		 200 { PCI_VDEVICE(INTEL, 0x2681), board_ahci }, /* ESB2 */
201 { PCI_VDEVICE(INTEL, 0x2682), board_ahci }, /* ESB2 */
202 { PCI_VDEVICE(INTEL, 0x2683), board_ahci }, /* ESB2 */
203 { PCI_VDEVICE(INTEL, 0x27c6), board_ahci }, /* ICH7-M DH */
7a234aff 204 { PCI_VDEVICE(INTEL, 0x2821), board_ahci }, /* ICH8 */
1b677afd 205 { PCI_VDEVICE(INTEL, 0x2822), board_ahci_nosntf }, /* ICH8 */
7a234aff
TH		 206 { PCI_VDEVICE(INTEL, 0x2824), board_ahci }, /* ICH8 */
207 { PCI_VDEVICE(INTEL, 0x2829), board_ahci }, /* ICH8M */
208 { PCI_VDEVICE(INTEL, 0x282a), board_ahci }, /* ICH8M */
209 { PCI_VDEVICE(INTEL, 0x2922), board_ahci }, /* ICH9 */
210 { PCI_VDEVICE(INTEL, 0x2923), board_ahci }, /* ICH9 */
211 { PCI_VDEVICE(INTEL, 0x2924), board_ahci }, /* ICH9 */
212 { PCI_VDEVICE(INTEL, 0x2925), board_ahci }, /* ICH9 */
213 { PCI_VDEVICE(INTEL, 0x2927), board_ahci }, /* ICH9 */
214 { PCI_VDEVICE(INTEL, 0x2929), board_ahci }, /* ICH9M */
215 { PCI_VDEVICE(INTEL, 0x292a), board_ahci }, /* ICH9M */
216 { PCI_VDEVICE(INTEL, 0x292b), board_ahci }, /* ICH9M */
217 { PCI_VDEVICE(INTEL, 0x292c), board_ahci }, /* ICH9M */
218 { PCI_VDEVICE(INTEL, 0x292f), board_ahci }, /* ICH9M */
219 { PCI_VDEVICE(INTEL, 0x294d), board_ahci }, /* ICH9 */
220 { PCI_VDEVICE(INTEL, 0x294e), board_ahci }, /* ICH9M */
d4155e6f
JG		 221 { PCI_VDEVICE(INTEL, 0x502a), board_ahci }, /* Tolapai */
222 { PCI_VDEVICE(INTEL, 0x502b), board_ahci }, /* Tolapai */
16ad1ad9 223 { PCI_VDEVICE(INTEL, 0x3a05), board_ahci }, /* ICH10 */
b2dde6af 224 { PCI_VDEVICE(INTEL, 0x3a22), board_ahci }, /* ICH10 */
16ad1ad9 225 { PCI_VDEVICE(INTEL, 0x3a25), board_ahci }, /* ICH10 */
c1f57d9b
DM		 226 { PCI_VDEVICE(INTEL, 0x3b22), board_ahci }, /* PCH AHCI */
227 { PCI_VDEVICE(INTEL, 0x3b23), board_ahci }, /* PCH AHCI */
adcb5308 228 { PCI_VDEVICE(INTEL, 0x3b24), board_ahci }, /* PCH RAID */
8e48b6b3 229 { PCI_VDEVICE(INTEL, 0x3b25), board_ahci }, /* PCH RAID */
c1f57d9b 230 { PCI_VDEVICE(INTEL, 0x3b29), board_ahci }, /* PCH AHCI */
adcb5308 231 { PCI_VDEVICE(INTEL, 0x3b2b), board_ahci }, /* PCH RAID */
8e48b6b3 232 { PCI_VDEVICE(INTEL, 0x3b2c), board_ahci }, /* PCH RAID */
c1f57d9b 233 { PCI_VDEVICE(INTEL, 0x3b2f), board_ahci }, /* PCH AHCI */
5623cab8
SH		 234 { PCI_VDEVICE(INTEL, 0x1c02), board_ahci }, /* CPT AHCI */
235 { PCI_VDEVICE(INTEL, 0x1c03), board_ahci }, /* CPT AHCI */
236 { PCI_VDEVICE(INTEL, 0x1c04), board_ahci }, /* CPT RAID */
237 { PCI_VDEVICE(INTEL, 0x1c05), board_ahci }, /* CPT RAID */
238 { PCI_VDEVICE(INTEL, 0x1c06), board_ahci }, /* CPT RAID */
239 { PCI_VDEVICE(INTEL, 0x1c07), board_ahci }, /* CPT RAID */
992b3fb9
SH		 240 { PCI_VDEVICE(INTEL, 0x1d02), board_ahci }, /* PBG AHCI */
241 { PCI_VDEVICE(INTEL, 0x1d04), board_ahci }, /* PBG RAID */
242 { PCI_VDEVICE(INTEL, 0x1d06), board_ahci }, /* PBG RAID */
64a3903d 243 { PCI_VDEVICE(INTEL, 0x2826), board_ahci }, /* PBG RAID */
a4a461a6 244 { PCI_VDEVICE(INTEL, 0x2323), board_ahci }, /* DH89xxCC AHCI */
181e3cea
SH		 245 { PCI_VDEVICE(INTEL, 0x1e02), board_ahci }, /* Panther Point AHCI */
246 { PCI_VDEVICE(INTEL, 0x1e03), board_ahci }, /* Panther Point AHCI */
247 { PCI_VDEVICE(INTEL, 0x1e04), board_ahci }, /* Panther Point RAID */
248 { PCI_VDEVICE(INTEL, 0x1e05), board_ahci }, /* Panther Point RAID */
249 { PCI_VDEVICE(INTEL, 0x1e06), board_ahci }, /* Panther Point RAID */
250 { PCI_VDEVICE(INTEL, 0x1e07), board_ahci }, /* Panther Point RAID */
2cab7a4c 251 { PCI_VDEVICE(INTEL, 0x1e0e), board_ahci }, /* Panther Point RAID */
ea4ace66
SH		 252 { PCI_VDEVICE(INTEL, 0x8c02), board_ahci }, /* Lynx Point AHCI */
253 { PCI_VDEVICE(INTEL, 0x8c03), board_ahci }, /* Lynx Point AHCI */
254 { PCI_VDEVICE(INTEL, 0x8c04), board_ahci }, /* Lynx Point RAID */
255 { PCI_VDEVICE(INTEL, 0x8c05), board_ahci }, /* Lynx Point RAID */
256 { PCI_VDEVICE(INTEL, 0x8c06), board_ahci }, /* Lynx Point RAID */
257 { PCI_VDEVICE(INTEL, 0x8c07), board_ahci }, /* Lynx Point RAID */
258 { PCI_VDEVICE(INTEL, 0x8c0e), board_ahci }, /* Lynx Point RAID */
259 { PCI_VDEVICE(INTEL, 0x8c0f), board_ahci }, /* Lynx Point RAID */
77b12bc9
JR		 260 { PCI_VDEVICE(INTEL, 0x9c02), board_ahci }, /* Lynx Point-LP AHCI */
261 { PCI_VDEVICE(INTEL, 0x9c03), board_ahci }, /* Lynx Point-LP AHCI */
262 { PCI_VDEVICE(INTEL, 0x9c04), board_ahci }, /* Lynx Point-LP RAID */
263 { PCI_VDEVICE(INTEL, 0x9c05), board_ahci }, /* Lynx Point-LP RAID */
264 { PCI_VDEVICE(INTEL, 0x9c06), board_ahci }, /* Lynx Point-LP RAID */
265 { PCI_VDEVICE(INTEL, 0x9c07), board_ahci }, /* Lynx Point-LP RAID */
266 { PCI_VDEVICE(INTEL, 0x9c0e), board_ahci }, /* Lynx Point-LP RAID */
267 { PCI_VDEVICE(INTEL, 0x9c0f), board_ahci }, /* Lynx Point-LP RAID */
29e674dd
SH		 268 { PCI_VDEVICE(INTEL, 0x1f22), board_ahci }, /* Avoton AHCI */
269 { PCI_VDEVICE(INTEL, 0x1f23), board_ahci }, /* Avoton AHCI */
270 { PCI_VDEVICE(INTEL, 0x1f24), board_ahci }, /* Avoton RAID */
271 { PCI_VDEVICE(INTEL, 0x1f25), board_ahci }, /* Avoton RAID */
272 { PCI_VDEVICE(INTEL, 0x1f26), board_ahci }, /* Avoton RAID */
273 { PCI_VDEVICE(INTEL, 0x1f27), board_ahci }, /* Avoton RAID */
274 { PCI_VDEVICE(INTEL, 0x1f2e), board_ahci }, /* Avoton RAID */
275 { PCI_VDEVICE(INTEL, 0x1f2f), board_ahci }, /* Avoton RAID */
276 { PCI_VDEVICE(INTEL, 0x1f32), board_ahci }, /* Avoton AHCI */
277 { PCI_VDEVICE(INTEL, 0x1f33), board_ahci }, /* Avoton AHCI */
278 { PCI_VDEVICE(INTEL, 0x1f34), board_ahci }, /* Avoton RAID */
279 { PCI_VDEVICE(INTEL, 0x1f35), board_ahci }, /* Avoton RAID */
280 { PCI_VDEVICE(INTEL, 0x1f36), board_ahci }, /* Avoton RAID */
281 { PCI_VDEVICE(INTEL, 0x1f37), board_ahci }, /* Avoton RAID */
282 { PCI_VDEVICE(INTEL, 0x1f3e), board_ahci }, /* Avoton RAID */
283 { PCI_VDEVICE(INTEL, 0x1f3f), board_ahci }, /* Avoton RAID */
fe7fa31a 284
e34bb370
TH		 285 /* JMicron 360/1/3/5/6, match class to avoid IDE function */
286 { PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
287 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci_ign_iferr },
1fefb8fd
BH		 288 /* JMicron 362B and 362C have an AHCI function with IDE class code */
289 { PCI_VDEVICE(JMICRON, 0x2362), board_ahci_ign_iferr },
290 { PCI_VDEVICE(JMICRON, 0x236f), board_ahci_ign_iferr },
fe7fa31a
JG		 291
292 /* ATI */
c65ec1c2 293 { PCI_VDEVICE(ATI, 0x4380), board_ahci_sb600 }, /* ATI SB600 */
e39fc8c9
SH		 294 { PCI_VDEVICE(ATI, 0x4390), board_ahci_sb700 }, /* ATI SB700/800 */
295 { PCI_VDEVICE(ATI, 0x4391), board_ahci_sb700 }, /* ATI SB700/800 */
296 { PCI_VDEVICE(ATI, 0x4392), board_ahci_sb700 }, /* ATI SB700/800 */
297 { PCI_VDEVICE(ATI, 0x4393), board_ahci_sb700 }, /* ATI SB700/800 */
298 { PCI_VDEVICE(ATI, 0x4394), board_ahci_sb700 }, /* ATI SB700/800 */
299 { PCI_VDEVICE(ATI, 0x4395), board_ahci_sb700 }, /* ATI SB700/800 */
fe7fa31a 300
e2dd90b1 301 /* AMD */
5deab536 302 { PCI_VDEVICE(AMD, 0x7800), board_ahci }, /* AMD Hudson-2 */
e2dd90b1
SH		 303 /* AMD is using RAID class only for ahci controllers */
304 { PCI_VENDOR_ID_AMD, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
305 PCI_CLASS_STORAGE_RAID << 8, 0xffffff, board_ahci },
306
fe7fa31a 307 /* VIA */
54bb3a94 308 { PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251 }, /* VIA VT8251 */
bf335542 309 { PCI_VDEVICE(VIA, 0x6287), board_ahci_vt8251 }, /* VIA VT8251 */
fe7fa31a
JG		 310
311 /* NVIDIA */
e297d99e
TH		 312 { PCI_VDEVICE(NVIDIA, 0x044c), board_ahci_mcp65 }, /* MCP65 */
313 { PCI_VDEVICE(NVIDIA, 0x044d), board_ahci_mcp65 }, /* MCP65 */
314 { PCI_VDEVICE(NVIDIA, 0x044e), board_ahci_mcp65 }, /* MCP65 */
315 { PCI_VDEVICE(NVIDIA, 0x044f), board_ahci_mcp65 }, /* MCP65 */
316 { PCI_VDEVICE(NVIDIA, 0x045c), board_ahci_mcp65 }, /* MCP65 */
317 { PCI_VDEVICE(NVIDIA, 0x045d), board_ahci_mcp65 }, /* MCP65 */
318 { PCI_VDEVICE(NVIDIA, 0x045e), board_ahci_mcp65 }, /* MCP65 */
319 { PCI_VDEVICE(NVIDIA, 0x045f), board_ahci_mcp65 }, /* MCP65 */
441577ef
TH		 320 { PCI_VDEVICE(NVIDIA, 0x0550), board_ahci_mcp67 }, /* MCP67 */
321 { PCI_VDEVICE(NVIDIA, 0x0551), board_ahci_mcp67 }, /* MCP67 */
322 { PCI_VDEVICE(NVIDIA, 0x0552), board_ahci_mcp67 }, /* MCP67 */
323 { PCI_VDEVICE(NVIDIA, 0x0553), board_ahci_mcp67 }, /* MCP67 */
324 { PCI_VDEVICE(NVIDIA, 0x0554), board_ahci_mcp67 }, /* MCP67 */
325 { PCI_VDEVICE(NVIDIA, 0x0555), board_ahci_mcp67 }, /* MCP67 */
326 { PCI_VDEVICE(NVIDIA, 0x0556), board_ahci_mcp67 }, /* MCP67 */
327 { PCI_VDEVICE(NVIDIA, 0x0557), board_ahci_mcp67 }, /* MCP67 */
328 { PCI_VDEVICE(NVIDIA, 0x0558), board_ahci_mcp67 }, /* MCP67 */
329 { PCI_VDEVICE(NVIDIA, 0x0559), board_ahci_mcp67 }, /* MCP67 */
330 { PCI_VDEVICE(NVIDIA, 0x055a), board_ahci_mcp67 }, /* MCP67 */
331 { PCI_VDEVICE(NVIDIA, 0x055b), board_ahci_mcp67 }, /* MCP67 */
332 { PCI_VDEVICE(NVIDIA, 0x0580), board_ahci_mcp_linux }, /* Linux ID */
333 { PCI_VDEVICE(NVIDIA, 0x0581), board_ahci_mcp_linux }, /* Linux ID */
334 { PCI_VDEVICE(NVIDIA, 0x0582), board_ahci_mcp_linux }, /* Linux ID */
335 { PCI_VDEVICE(NVIDIA, 0x0583), board_ahci_mcp_linux }, /* Linux ID */
336 { PCI_VDEVICE(NVIDIA, 0x0584), board_ahci_mcp_linux }, /* Linux ID */
337 { PCI_VDEVICE(NVIDIA, 0x0585), board_ahci_mcp_linux }, /* Linux ID */
338 { PCI_VDEVICE(NVIDIA, 0x0586), board_ahci_mcp_linux }, /* Linux ID */
339 { PCI_VDEVICE(NVIDIA, 0x0587), board_ahci_mcp_linux }, /* Linux ID */
340 { PCI_VDEVICE(NVIDIA, 0x0588), board_ahci_mcp_linux }, /* Linux ID */
341 { PCI_VDEVICE(NVIDIA, 0x0589), board_ahci_mcp_linux }, /* Linux ID */
342 { PCI_VDEVICE(NVIDIA, 0x058a), board_ahci_mcp_linux }, /* Linux ID */
343 { PCI_VDEVICE(NVIDIA, 0x058b), board_ahci_mcp_linux }, /* Linux ID */
344 { PCI_VDEVICE(NVIDIA, 0x058c), board_ahci_mcp_linux }, /* Linux ID */
345 { PCI_VDEVICE(NVIDIA, 0x058d), board_ahci_mcp_linux }, /* Linux ID */
346 { PCI_VDEVICE(NVIDIA, 0x058e), board_ahci_mcp_linux }, /* Linux ID */
347 { PCI_VDEVICE(NVIDIA, 0x058f), board_ahci_mcp_linux }, /* Linux ID */
348 { PCI_VDEVICE(NVIDIA, 0x07f0), board_ahci_mcp73 }, /* MCP73 */
349 { PCI_VDEVICE(NVIDIA, 0x07f1), board_ahci_mcp73 }, /* MCP73 */
350 { PCI_VDEVICE(NVIDIA, 0x07f2), board_ahci_mcp73 }, /* MCP73 */
351 { PCI_VDEVICE(NVIDIA, 0x07f3), board_ahci_mcp73 }, /* MCP73 */
352 { PCI_VDEVICE(NVIDIA, 0x07f4), board_ahci_mcp73 }, /* MCP73 */
353 { PCI_VDEVICE(NVIDIA, 0x07f5), board_ahci_mcp73 }, /* MCP73 */
354 { PCI_VDEVICE(NVIDIA, 0x07f6), board_ahci_mcp73 }, /* MCP73 */
355 { PCI_VDEVICE(NVIDIA, 0x07f7), board_ahci_mcp73 }, /* MCP73 */
356 { PCI_VDEVICE(NVIDIA, 0x07f8), board_ahci_mcp73 }, /* MCP73 */
357 { PCI_VDEVICE(NVIDIA, 0x07f9), board_ahci_mcp73 }, /* MCP73 */
358 { PCI_VDEVICE(NVIDIA, 0x07fa), board_ahci_mcp73 }, /* MCP73 */
359 { PCI_VDEVICE(NVIDIA, 0x07fb), board_ahci_mcp73 }, /* MCP73 */
360 { PCI_VDEVICE(NVIDIA, 0x0ad0), board_ahci_mcp77 }, /* MCP77 */
361 { PCI_VDEVICE(NVIDIA, 0x0ad1), board_ahci_mcp77 }, /* MCP77 */
362 { PCI_VDEVICE(NVIDIA, 0x0ad2), board_ahci_mcp77 }, /* MCP77 */
363 { PCI_VDEVICE(NVIDIA, 0x0ad3), board_ahci_mcp77 }, /* MCP77 */
364 { PCI_VDEVICE(NVIDIA, 0x0ad4), board_ahci_mcp77 }, /* MCP77 */
365 { PCI_VDEVICE(NVIDIA, 0x0ad5), board_ahci_mcp77 }, /* MCP77 */
366 { PCI_VDEVICE(NVIDIA, 0x0ad6), board_ahci_mcp77 }, /* MCP77 */
367 { PCI_VDEVICE(NVIDIA, 0x0ad7), board_ahci_mcp77 }, /* MCP77 */
368 { PCI_VDEVICE(NVIDIA, 0x0ad8), board_ahci_mcp77 }, /* MCP77 */
369 { PCI_VDEVICE(NVIDIA, 0x0ad9), board_ahci_mcp77 }, /* MCP77 */
370 { PCI_VDEVICE(NVIDIA, 0x0ada), board_ahci_mcp77 }, /* MCP77 */
371 { PCI_VDEVICE(NVIDIA, 0x0adb), board_ahci_mcp77 }, /* MCP77 */
372 { PCI_VDEVICE(NVIDIA, 0x0ab4), board_ahci_mcp79 }, /* MCP79 */
373 { PCI_VDEVICE(NVIDIA, 0x0ab5), board_ahci_mcp79 }, /* MCP79 */
374 { PCI_VDEVICE(NVIDIA, 0x0ab6), board_ahci_mcp79 }, /* MCP79 */
375 { PCI_VDEVICE(NVIDIA, 0x0ab7), board_ahci_mcp79 }, /* MCP79 */
376 { PCI_VDEVICE(NVIDIA, 0x0ab8), board_ahci_mcp79 }, /* MCP79 */
377 { PCI_VDEVICE(NVIDIA, 0x0ab9), board_ahci_mcp79 }, /* MCP79 */
378 { PCI_VDEVICE(NVIDIA, 0x0aba), board_ahci_mcp79 }, /* MCP79 */
379 { PCI_VDEVICE(NVIDIA, 0x0abb), board_ahci_mcp79 }, /* MCP79 */
380 { PCI_VDEVICE(NVIDIA, 0x0abc), board_ahci_mcp79 }, /* MCP79 */
381 { PCI_VDEVICE(NVIDIA, 0x0abd), board_ahci_mcp79 }, /* MCP79 */
382 { PCI_VDEVICE(NVIDIA, 0x0abe), board_ahci_mcp79 }, /* MCP79 */
383 { PCI_VDEVICE(NVIDIA, 0x0abf), board_ahci_mcp79 }, /* MCP79 */
384 { PCI_VDEVICE(NVIDIA, 0x0d84), board_ahci_mcp89 }, /* MCP89 */
385 { PCI_VDEVICE(NVIDIA, 0x0d85), board_ahci_mcp89 }, /* MCP89 */
386 { PCI_VDEVICE(NVIDIA, 0x0d86), board_ahci_mcp89 }, /* MCP89 */
387 { PCI_VDEVICE(NVIDIA, 0x0d87), board_ahci_mcp89 }, /* MCP89 */
388 { PCI_VDEVICE(NVIDIA, 0x0d88), board_ahci_mcp89 }, /* MCP89 */
389 { PCI_VDEVICE(NVIDIA, 0x0d89), board_ahci_mcp89 }, /* MCP89 */
390 { PCI_VDEVICE(NVIDIA, 0x0d8a), board_ahci_mcp89 }, /* MCP89 */
391 { PCI_VDEVICE(NVIDIA, 0x0d8b), board_ahci_mcp89 }, /* MCP89 */
392 { PCI_VDEVICE(NVIDIA, 0x0d8c), board_ahci_mcp89 }, /* MCP89 */
393 { PCI_VDEVICE(NVIDIA, 0x0d8d), board_ahci_mcp89 }, /* MCP89 */
394 { PCI_VDEVICE(NVIDIA, 0x0d8e), board_ahci_mcp89 }, /* MCP89 */
395 { PCI_VDEVICE(NVIDIA, 0x0d8f), board_ahci_mcp89 }, /* MCP89 */
fe7fa31a 396
95916edd 397 /* SiS */
20e2de4a
TH		 398 { PCI_VDEVICE(SI, 0x1184), board_ahci }, /* SiS 966 */
399 { PCI_VDEVICE(SI, 0x1185), board_ahci }, /* SiS 968 */
400 { PCI_VDEVICE(SI, 0x0186), board_ahci }, /* SiS 968 */
95916edd 401
318893e1
AR		 402 /* ST Microelectronics */
403 { PCI_VDEVICE(STMICRO, 0xCC06), board_ahci }, /* ST ConneXt */
404
cd70c266
JG		 405 /* Marvell */
406 { PCI_VDEVICE(MARVELL, 0x6145), board_ahci_mv }, /* 6145 */
c40e7cb8 407 { PCI_VDEVICE(MARVELL, 0x6121), board_ahci_mv }, /* 6121 */
5f173107 408 { PCI_DEVICE(0x1b4b, 0x9123),
10aca06c
AH		 409 .class = PCI_CLASS_STORAGE_SATA_AHCI,
410 .class_mask = 0xffffff,
5f173107 411 .driver_data = board_ahci_yes_fbs }, /* 88se9128 */
467b41c6
PJ		 412 { PCI_DEVICE(0x1b4b, 0x9125),
413 .driver_data = board_ahci_yes_fbs }, /* 88se9125 */
642d8925
MJ		 414 { PCI_DEVICE(0x1b4b, 0x917a),
415 .driver_data = board_ahci_yes_fbs }, /* 88se9172 */
17c60c6b
AC		 416 { PCI_DEVICE(0x1b4b, 0x9192),
417 .driver_data = board_ahci_yes_fbs }, /* 88se9172 on some Gigabyte */
50be5e36
TH		 418 { PCI_DEVICE(0x1b4b, 0x91a3),
419 .driver_data = board_ahci_yes_fbs },
cd70c266 420
c77a036b
MN		 421 /* Promise */
422 { PCI_VDEVICE(PROMISE, 0x3f20), board_ahci }, /* PDC42819 */
423
c9703765 424 /* Asmedia */
7b4f6eca
AC		 425 { PCI_VDEVICE(ASMEDIA, 0x0601), board_ahci }, /* ASM1060 */
426 { PCI_VDEVICE(ASMEDIA, 0x0602), board_ahci }, /* ASM1060 */
427 { PCI_VDEVICE(ASMEDIA, 0x0611), board_ahci }, /* ASM1061 */
428 { PCI_VDEVICE(ASMEDIA, 0x0612), board_ahci }, /* ASM1062 */
c9703765 429
7f9c9f8e
HD		 430 /* Enmotus */
431 { PCI_DEVICE(0x1c44, 0x8000), board_ahci },
432
415ae2b5
JG		 433 /* Generic, PCI class code for AHCI */
434 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
c9f89475 435 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci },
415ae2b5 436
1da177e4
LT		 437 { } /* terminate list */
438};
439
440
441static struct pci_driver ahci_pci_driver = {
442 .name = DRV_NAME,
443 .id_table = ahci_pci_tbl,
444 .probe = ahci_init_one,
24dc5f33 445 .remove = ata_pci_remove_one,
438ac6d5 446#ifdef CONFIG_PM
c1332875 447 .suspend = ahci_pci_device_suspend,
365cfa1e
AV		 448 .resume = ahci_pci_device_resume,
449#endif
450};
1da177e4 451
365cfa1e
AV		 452#if defined(CONFIG_PATA_MARVELL) || defined(CONFIG_PATA_MARVELL_MODULE)
453static int marvell_enable;
454#else
455static int marvell_enable = 1;
456#endif
457module_param(marvell_enable, int, 0644);
458MODULE_PARM_DESC(marvell_enable, "Marvell SATA via AHCI (1 = enabled)");
d28f87aa 459
1da177e4 460
365cfa1e
AV		 461static void ahci_pci_save_initial_config(struct pci_dev *pdev,
462 struct ahci_host_priv *hpriv)
463{
464 unsigned int force_port_map = 0;
465 unsigned int mask_port_map = 0;
67846b30 466
365cfa1e
AV		 467 if (pdev->vendor == PCI_VENDOR_ID_JMICRON && pdev->device == 0x2361) {
468 dev_info(&pdev->dev, "JMB361 has only one port\n");
469 force_port_map = 1;
1da177e4
LT		 470 }
471
365cfa1e
AV		 472 /*
473 * Temporary Marvell 6145 hack: PATA port presence
474 * is asserted through the standard AHCI port
475 * presence register, as bit 4 (counting from 0)
d28f87aa 476 */
365cfa1e
AV		 477 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
478 if (pdev->device == 0x6121)
479 mask_port_map = 0x3;
480 else
481 mask_port_map = 0xf;
482 dev_info(&pdev->dev,
483 "Disabling your PATA port. Use the boot option 'ahci.marvell_enable=0' to avoid this.\n");
484 }
1da177e4 485
365cfa1e
AV		 486 ahci_save_initial_config(&pdev->dev, hpriv, force_port_map,
487 mask_port_map);
1da177e4
LT		 488}
489
365cfa1e 490static int ahci_pci_reset_controller(struct ata_host *host)
1da177e4 491{
365cfa1e 492 struct pci_dev *pdev = to_pci_dev(host->dev);
7d50b60b 493
365cfa1e 494 ahci_reset_controller(host);
1da177e4 495
365cfa1e
AV		 496 if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
497 struct ahci_host_priv *hpriv = host->private_data;
498 u16 tmp16;
d6ef3153 499
365cfa1e
AV		 500 /* configure PCS */
501 pci_read_config_word(pdev, 0x92, &tmp16);
502 if ((tmp16 & hpriv->port_map) != hpriv->port_map) {
503 tmp16 |= hpriv->port_map;
504 pci_write_config_word(pdev, 0x92, tmp16);
505 }
d6ef3153
SH		 506 }
507
1da177e4
LT		 508 return 0;
509}
510
365cfa1e 511static void ahci_pci_init_controller(struct ata_host *host)
78cd52d0 512{
365cfa1e
AV		 513 struct ahci_host_priv *hpriv = host->private_data;
514 struct pci_dev *pdev = to_pci_dev(host->dev);
515 void __iomem *port_mmio;
78cd52d0 516 u32 tmp;
365cfa1e 517 int mv;
78cd52d0 518
365cfa1e
AV		 519 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
520 if (pdev->device == 0x6121)
521 mv = 2;
522 else
523 mv = 4;
524 port_mmio = __ahci_port_base(host, mv);
78cd52d0 525
365cfa1e 526 writel(0, port_mmio + PORT_IRQ_MASK);
78cd52d0 527
365cfa1e
AV		 528 /* clear port IRQ */
529 tmp = readl(port_mmio + PORT_IRQ_STAT);
530 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
531 if (tmp)
532 writel(tmp, port_mmio + PORT_IRQ_STAT);
78cd52d0
TH		 533 }
534
365cfa1e 535 ahci_init_controller(host);
edc93052
TH		 536}
537
365cfa1e
AV		 538static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
539 unsigned long deadline)
d6ef3153 540{
365cfa1e
AV		 541 struct ata_port *ap = link->ap;
542 bool online;
d6ef3153
SH		 543 int rc;
544
365cfa1e 545 DPRINTK("ENTER\n");
d6ef3153 546
365cfa1e 547 ahci_stop_engine(ap);
d6ef3153 548
365cfa1e
AV		 549 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
550 deadline, &online, NULL);
d6ef3153
SH		 551
552 ahci_start_engine(ap);
d6ef3153 553
365cfa1e 554 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
d6ef3153 555
365cfa1e
AV		 556 /* vt8251 doesn't clear BSY on signature FIS reception,
557 * request follow-up softreset.
558 */
559 return online ? -EAGAIN : rc;
7d50b60b
TH		 560}
561
365cfa1e
AV		 562static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
563 unsigned long deadline)
7d50b60b 564{
365cfa1e 565 struct ata_port *ap = link->ap;
1c954a4d 566 struct ahci_port_priv *pp = ap->private_data;
365cfa1e
AV		 567 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
568 struct ata_taskfile tf;
569 bool online;
570 int rc;
7d50b60b 571
365cfa1e 572 ahci_stop_engine(ap);
028a2596 573
365cfa1e
AV		 574 /* clear D2H reception area to properly wait for D2H FIS */
575 ata_tf_init(link->device, &tf);
576 tf.command = 0x80;
577 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
7d50b60b 578
365cfa1e
AV		 579 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
580 deadline, &online, NULL);
028a2596 581
365cfa1e 582 ahci_start_engine(ap);
c1332875 583
365cfa1e
AV		 584 /* The pseudo configuration device on SIMG4726 attached to
585 * ASUS P5W-DH Deluxe doesn't send signature FIS after
586 * hardreset if no device is attached to the first downstream
587 * port && the pseudo device locks up on SRST w/ PMP==0. To
588 * work around this, wait for !BSY only briefly. If BSY isn't
589 * cleared, perform CLO and proceed to IDENTIFY (achieved by
590 * ATA_LFLAG_NO_SRST and ATA_LFLAG_ASSUME_ATA).
591 *
592 * Wait for two seconds. Devices attached to downstream port
593 * which can't process the following IDENTIFY after this will
594 * have to be reset again. For most cases, this should
595 * suffice while making probing snappish enough.
596 */
597 if (online) {
598 rc = ata_wait_after_reset(link, jiffies + 2 * HZ,
599 ahci_check_ready);
600 if (rc)
601 ahci_kick_engine(ap);
c1332875 602 }
c1332875
TH		 603 return rc;
604}
605
365cfa1e 606#ifdef CONFIG_PM
c1332875
TH		 607static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg)
608{
cca3974e 609 struct ata_host *host = dev_get_drvdata(&pdev->dev);
9b10ae86 610 struct ahci_host_priv *hpriv = host->private_data;
d8993349 611 void __iomem *mmio = hpriv->mmio;
c1332875
TH		 612 u32 ctl;
613
9b10ae86
TH		 614 if (mesg.event & PM_EVENT_SUSPEND &&
615 hpriv->flags & AHCI_HFLAG_NO_SUSPEND) {
a44fec1f
JP		 616 dev_err(&pdev->dev,
617 "BIOS update required for suspend/resume\n");
9b10ae86
TH		 618 return -EIO;
619 }
620
3a2d5b70 621 if (mesg.event & PM_EVENT_SLEEP) {
c1332875
TH		 622 /* AHCI spec rev1.1 section 8.3.3:
623 * Software must disable interrupts prior to requesting a
624 * transition of the HBA to D3 state.
625 */
626 ctl = readl(mmio + HOST_CTL);
627 ctl &= ~HOST_IRQ_EN;
628 writel(ctl, mmio + HOST_CTL);
629 readl(mmio + HOST_CTL); /* flush */
630 }
631
632 return ata_pci_device_suspend(pdev, mesg);
633}
634
635static int ahci_pci_device_resume(struct pci_dev *pdev)
636{
cca3974e 637 struct ata_host *host = dev_get_drvdata(&pdev->dev);
c1332875
TH		 638 int rc;
639
553c4aa6
TH		 640 rc = ata_pci_device_do_resume(pdev);
641 if (rc)
642 return rc;
c1332875
TH		 643
644 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
3303040d 645 rc = ahci_pci_reset_controller(host);
c1332875
TH		 646 if (rc)
647 return rc;
648
781d6550 649 ahci_pci_init_controller(host);
c1332875
TH		 650 }
651
cca3974e 652 ata_host_resume(host);
c1332875
TH		 653
654 return 0;
655}
438ac6d5 656#endif
c1332875 657
4447d351 658static int ahci_configure_dma_masks(struct pci_dev *pdev, int using_dac)
1da177e4 659{
1da177e4 660 int rc;
1da177e4 661
318893e1
AR		 662 /*
663 * If the device fixup already set the dma_mask to some non-standard
664 * value, don't extend it here. This happens on STA2X11, for example.
665 */
666 if (pdev->dma_mask && pdev->dma_mask < DMA_BIT_MASK(32))
667 return 0;
668
1da177e4 669 if (using_dac &&
6a35528a
YH		 670 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
671 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
1da177e4 672 if (rc) {
284901a9 673 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
1da177e4 674 if (rc) {
a44fec1f
JP		 675 dev_err(&pdev->dev,
676 "64-bit DMA enable failed\n");
1da177e4
LT		 677 return rc;
678 }
679 }
1da177e4 680 } else {
284901a9 681 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
1da177e4 682 if (rc) {
a44fec1f 683 dev_err(&pdev->dev, "32-bit DMA enable failed\n");
1da177e4
LT		 684 return rc;
685 }
284901a9 686 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
1da177e4 687 if (rc) {
a44fec1f
JP		 688 dev_err(&pdev->dev,
689 "32-bit consistent DMA enable failed\n");
1da177e4
LT		 690 return rc;
691 }
692 }
1da177e4
LT		 693 return 0;
694}
695
439fcaec
AV		 696static void ahci_pci_print_info(struct ata_host *host)
697{
698 struct pci_dev *pdev = to_pci_dev(host->dev);
699 u16 cc;
700 const char *scc_s;
701
702 pci_read_config_word(pdev, 0x0a, &cc);
703 if (cc == PCI_CLASS_STORAGE_IDE)
704 scc_s = "IDE";
705 else if (cc == PCI_CLASS_STORAGE_SATA)
706 scc_s = "SATA";
707 else if (cc == PCI_CLASS_STORAGE_RAID)
708 scc_s = "RAID";
709 else
710 scc_s = "unknown";
711
712 ahci_print_info(host, scc_s);
713}
714
edc93052
TH		 715/* On ASUS P5W DH Deluxe, the second port of PCI device 00:1f.2 is
716 * hardwired to on-board SIMG 4726. The chipset is ICH8 and doesn't
717 * support PMP and the 4726 either directly exports the device
718 * attached to the first downstream port or acts as a hardware storage
719 * controller and emulate a single ATA device (can be RAID 0/1 or some
720 * other configuration).
721 *
722 * When there's no device attached to the first downstream port of the
723 * 4726, "Config Disk" appears, which is a pseudo ATA device to
724 * configure the 4726. However, ATA emulation of the device is very
725 * lame. It doesn't send signature D2H Reg FIS after the initial
726 * hardreset, pukes on SRST w/ PMP==0 and has bunch of other issues.
727 *
728 * The following function works around the problem by always using
729 * hardreset on the port and not depending on receiving signature FIS
730 * afterward. If signature FIS isn't received soon, ATA class is
731 * assumed without follow-up softreset.
732 */
733static void ahci_p5wdh_workaround(struct ata_host *host)
734{
735 static struct dmi_system_id sysids[] = {
736 {
737 .ident = "P5W DH Deluxe",
738 .matches = {
739 DMI_MATCH(DMI_SYS_VENDOR,
740 "ASUSTEK COMPUTER INC"),
741 DMI_MATCH(DMI_PRODUCT_NAME, "P5W DH Deluxe"),
742 },
743 },
744 { }
745 };
746 struct pci_dev *pdev = to_pci_dev(host->dev);
747
748 if (pdev->bus->number == 0 && pdev->devfn == PCI_DEVFN(0x1f, 2) &&
749 dmi_check_system(sysids)) {
750 struct ata_port *ap = host->ports[1];
751
a44fec1f
JP		 752 dev_info(&pdev->dev,
753 "enabling ASUS P5W DH Deluxe on-board SIMG4726 workaround\n");
edc93052
TH		 754
755 ap->ops = &ahci_p5wdh_ops;
756 ap->link.flags |= ATA_LFLAG_NO_SRST | ATA_LFLAG_ASSUME_ATA;
757 }
758}
759
2fcad9d2
TH		 760/* only some SB600 ahci controllers can do 64bit DMA */
761static bool ahci_sb600_enable_64bit(struct pci_dev *pdev)
58a09b38
SH		 762{
763 static const struct dmi_system_id sysids[] = {
03d783bf
TH		 764 /*
765 * The oldest version known to be broken is 0901 and
766 * working is 1501 which was released on 2007-10-26.
2fcad9d2
TH		 767 * Enable 64bit DMA on 1501 and anything newer.
768 *
03d783bf
TH		 769 * Please read bko#9412 for more info.
770 */
58a09b38
SH		 771 {
772 .ident = "ASUS M2A-VM",
773 .matches = {
774 DMI_MATCH(DMI_BOARD_VENDOR,
775 "ASUSTeK Computer INC."),
776 DMI_MATCH(DMI_BOARD_NAME, "M2A-VM"),
777 },
03d783bf 778 .driver_data = "20071026", /* yyyymmdd */
58a09b38 779 },
e65cc194
MN		 780 /*
781 * All BIOS versions for the MSI K9A2 Platinum (MS-7376)
782 * support 64bit DMA.
783 *
784 * BIOS versions earlier than 1.5 had the Manufacturer DMI
785 * fields as "MICRO-STAR INTERANTIONAL CO.,LTD".
786 * This spelling mistake was fixed in BIOS version 1.5, so
787 * 1.5 and later have the Manufacturer as
788 * "MICRO-STAR INTERNATIONAL CO.,LTD".
789 * So try to match on DMI_BOARD_VENDOR of "MICRO-STAR INTER".
790 *
791 * BIOS versions earlier than 1.9 had a Board Product Name
792 * DMI field of "MS-7376". This was changed to be
793 * "K9A2 Platinum (MS-7376)" in version 1.9, but we can still
794 * match on DMI_BOARD_NAME of "MS-7376".
795 */
796 {
797 .ident = "MSI K9A2 Platinum",
798 .matches = {
799 DMI_MATCH(DMI_BOARD_VENDOR,
800 "MICRO-STAR INTER"),
801 DMI_MATCH(DMI_BOARD_NAME, "MS-7376"),
802 },
803 },
ff0173c1
MN		 804 /*
805 * All BIOS versions for the MSI K9AGM2 (MS-7327) support
806 * 64bit DMA.
807 *
808 * This board also had the typo mentioned above in the
809 * Manufacturer DMI field (fixed in BIOS version 1.5), so
810 * match on DMI_BOARD_VENDOR of "MICRO-STAR INTER" again.
811 */
812 {
813 .ident = "MSI K9AGM2",
814 .matches = {
815 DMI_MATCH(DMI_BOARD_VENDOR,
816 "MICRO-STAR INTER"),
817 DMI_MATCH(DMI_BOARD_NAME, "MS-7327"),
818 },
819 },
3c4aa91f
MN		 820 /*
821 * All BIOS versions for the Asus M3A support 64bit DMA.
822 * (all release versions from 0301 to 1206 were tested)
823 */
824 {
825 .ident = "ASUS M3A",
826 .matches = {
827 DMI_MATCH(DMI_BOARD_VENDOR,
828 "ASUSTeK Computer INC."),
829 DMI_MATCH(DMI_BOARD_NAME, "M3A"),
830 },
831 },
58a09b38
SH		 832 { }
833 };
03d783bf 834 const struct dmi_system_id *match;
2fcad9d2
TH		 835 int year, month, date;
836 char buf[9];
58a09b38 837
03d783bf 838 match = dmi_first_match(sysids);
58a09b38 839 if (pdev->bus->number != 0 || pdev->devfn != PCI_DEVFN(0x12, 0) ||
03d783bf 840 !match)
58a09b38
SH		 841 return false;
842
e65cc194
MN		 843 if (!match->driver_data)
844 goto enable_64bit;
845
2fcad9d2
TH		 846 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
847 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
03d783bf 848
e65cc194
MN		 849 if (strcmp(buf, match->driver_data) >= 0)
850 goto enable_64bit;
851 else {
a44fec1f
JP		 852 dev_warn(&pdev->dev,
853 "%s: BIOS too old, forcing 32bit DMA, update BIOS\n",
854 match->ident);
2fcad9d2
TH		 855 return false;
856 }
e65cc194
MN		 857
858enable_64bit:
a44fec1f 859 dev_warn(&pdev->dev, "%s: enabling 64bit DMA\n", match->ident);
e65cc194 860 return true;
58a09b38
SH		 861}
862
1fd68434
RW		 863static bool ahci_broken_system_poweroff(struct pci_dev *pdev)
864{
865 static const struct dmi_system_id broken_systems[] = {
866 {
867 .ident = "HP Compaq nx6310",
868 .matches = {
869 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
870 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq nx6310"),
871 },
872 /* PCI slot number of the controller */
873 .driver_data = (void *)0x1FUL,
874 },
d2f9c061
MR		 875 {
876 .ident = "HP Compaq 6720s",
877 .matches = {
878 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
879 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq 6720s"),
880 },
881 /* PCI slot number of the controller */
882 .driver_data = (void *)0x1FUL,
883 },
1fd68434
RW		 884
885 { } /* terminate list */
886 };
887 const struct dmi_system_id *dmi = dmi_first_match(broken_systems);
888
889 if (dmi) {
890 unsigned long slot = (unsigned long)dmi->driver_data;
891 /* apply the quirk only to on-board controllers */
892 return slot == PCI_SLOT(pdev->devfn);
893 }
894
895 return false;
896}
897
9b10ae86
TH		 898static bool ahci_broken_suspend(struct pci_dev *pdev)
899{
900 static const struct dmi_system_id sysids[] = {
901 /*
902 * On HP dv[4-6] and HDX18 with earlier BIOSen, link
903 * to the harddisk doesn't become online after
904 * resuming from STR. Warn and fail suspend.
9deb3431
TH		 905 *
906 * http://bugzilla.kernel.org/show_bug.cgi?id=12276
907 *
908 * Use dates instead of versions to match as HP is
909 * apparently recycling both product and version
910 * strings.
911 *
912 * http://bugzilla.kernel.org/show_bug.cgi?id=15462
9b10ae86
TH		 913 */
914 {
915 .ident = "dv4",
916 .matches = {
917 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
918 DMI_MATCH(DMI_PRODUCT_NAME,
919 "HP Pavilion dv4 Notebook PC"),
920 },
9deb3431 921 .driver_data = "20090105", /* F.30 */
9b10ae86
TH		 922 },
923 {
924 .ident = "dv5",
925 .matches = {
926 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
927 DMI_MATCH(DMI_PRODUCT_NAME,
928 "HP Pavilion dv5 Notebook PC"),
929 },
9deb3431 930 .driver_data = "20090506", /* F.16 */
9b10ae86
TH		 931 },
932 {
933 .ident = "dv6",
934 .matches = {
935 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
936 DMI_MATCH(DMI_PRODUCT_NAME,
937 "HP Pavilion dv6 Notebook PC"),
938 },
9deb3431 939 .driver_data = "20090423", /* F.21 */
9b10ae86
TH		 940 },
941 {
942 .ident = "HDX18",
943 .matches = {
944 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
945 DMI_MATCH(DMI_PRODUCT_NAME,
946 "HP HDX18 Notebook PC"),
947 },
9deb3431 948 .driver_data = "20090430", /* F.23 */
9b10ae86 949 },
cedc9bf9
TH		 950 /*
951 * Acer eMachines G725 has the same problem. BIOS
952 * V1.03 is known to be broken. V3.04 is known to
25985edc 953 * work. Between, there are V1.06, V2.06 and V3.03
cedc9bf9
TH		 954 * that we don't have much idea about. For now,
955 * blacklist anything older than V3.04.
9deb3431
TH		 956 *
957 * http://bugzilla.kernel.org/show_bug.cgi?id=15104
cedc9bf9
TH		 958 */
959 {
960 .ident = "G725",
961 .matches = {
962 DMI_MATCH(DMI_SYS_VENDOR, "eMachines"),
963 DMI_MATCH(DMI_PRODUCT_NAME, "eMachines G725"),
964 },
9deb3431 965 .driver_data = "20091216", /* V3.04 */
cedc9bf9 966 },
9b10ae86
TH		 967 { } /* terminate list */
968 };
969 const struct dmi_system_id *dmi = dmi_first_match(sysids);
9deb3431
TH		 970 int year, month, date;
971 char buf[9];
9b10ae86
TH		 972
973 if (!dmi || pdev->bus->number || pdev->devfn != PCI_DEVFN(0x1f, 2))
974 return false;
975
9deb3431
TH		 976 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
977 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
9b10ae86 978
9deb3431 979 return strcmp(buf, dmi->driver_data) < 0;
9b10ae86
TH		 980}
981
5594639a
TH		 982static bool ahci_broken_online(struct pci_dev *pdev)
983{
984#define ENCODE_BUSDEVFN(bus, slot, func) \
985 (void *)(unsigned long)(((bus) << 8) | PCI_DEVFN((slot), (func)))
986 static const struct dmi_system_id sysids[] = {
987 /*
988 * There are several gigabyte boards which use
989 * SIMG5723s configured as hardware RAID. Certain
990 * 5723 firmware revisions shipped there keep the link
991 * online but fail to answer properly to SRST or
992 * IDENTIFY when no device is attached downstream
993 * causing libata to retry quite a few times leading
994 * to excessive detection delay.
995 *
996 * As these firmwares respond to the second reset try
997 * with invalid device signature, considering unknown
998 * sig as offline works around the problem acceptably.
999 */
1000 {
1001 .ident = "EP45-DQ6",
1002 .matches = {
1003 DMI_MATCH(DMI_BOARD_VENDOR,
1004 "Gigabyte Technology Co., Ltd."),
1005 DMI_MATCH(DMI_BOARD_NAME, "EP45-DQ6"),
1006 },
1007 .driver_data = ENCODE_BUSDEVFN(0x0a, 0x00, 0),
1008 },
1009 {
1010 .ident = "EP45-DS5",
1011 .matches = {
1012 DMI_MATCH(DMI_BOARD_VENDOR,
1013 "Gigabyte Technology Co., Ltd."),
1014 DMI_MATCH(DMI_BOARD_NAME, "EP45-DS5"),
1015 },
1016 .driver_data = ENCODE_BUSDEVFN(0x03, 0x00, 0),
1017 },
1018 { } /* terminate list */
1019 };
1020#undef ENCODE_BUSDEVFN
1021 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1022 unsigned int val;
1023
1024 if (!dmi)
1025 return false;
1026
1027 val = (unsigned long)dmi->driver_data;
1028
1029 return pdev->bus->number == (val >> 8) && pdev->devfn == (val & 0xff);
1030}
1031
8e513217 1032#ifdef CONFIG_ATA_ACPI
f80ae7e4
TH		 1033static void ahci_gtf_filter_workaround(struct ata_host *host)
1034{
1035 static const struct dmi_system_id sysids[] = {
1036 /*
1037 * Aspire 3810T issues a bunch of SATA enable commands
1038 * via _GTF including an invalid one and one which is
1039 * rejected by the device. Among the successful ones
1040 * is FPDMA non-zero offset enable which when enabled
1041 * only on the drive side leads to NCQ command
1042 * failures. Filter it out.
1043 */
1044 {
1045 .ident = "Aspire 3810T",
1046 .matches = {
1047 DMI_MATCH(DMI_SYS_VENDOR, "Acer"),
1048 DMI_MATCH(DMI_PRODUCT_NAME, "Aspire 3810T"),
1049 },
1050 .driver_data = (void *)ATA_ACPI_FILTER_FPDMA_OFFSET,
1051 },
1052 { }
1053 };
1054 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1055 unsigned int filter;
1056 int i;
1057
1058 if (!dmi)
1059 return;
1060
1061 filter = (unsigned long)dmi->driver_data;
a44fec1f
JP		 1062 dev_info(host->dev, "applying extra ACPI _GTF filter 0x%x for %s\n",
1063 filter, dmi->ident);
f80ae7e4
TH		 1064
1065 for (i = 0; i < host->n_ports; i++) {
1066 struct ata_port *ap = host->ports[i];
1067 struct ata_link *link;
1068 struct ata_device *dev;
1069
1070 ata_for_each_link(link, ap, EDGE)
1071 ata_for_each_dev(dev, link, ALL)
1072 dev->gtf_filter |= filter;
1073 }
1074}
8e513217
MT		 1075#else
1076static inline void ahci_gtf_filter_workaround(struct ata_host *host)
1077{}
1078#endif
f80ae7e4 1079
24dc5f33 1080static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1da177e4 1081{
e297d99e
TH		 1082 unsigned int board_id = ent->driver_data;
1083 struct ata_port_info pi = ahci_port_info[board_id];
4447d351 1084 const struct ata_port_info *ppi[] = { &pi, NULL };
24dc5f33 1085 struct device *dev = &pdev->dev;
1da177e4 1086 struct ahci_host_priv *hpriv;
4447d351 1087 struct ata_host *host;
837f5f8f 1088 int n_ports, i, rc;
318893e1 1089 int ahci_pci_bar = AHCI_PCI_BAR_STANDARD;
1da177e4
LT		 1090
1091 VPRINTK("ENTER\n");
1092
b429dd59 1093 WARN_ON((int)ATA_MAX_QUEUE > AHCI_MAX_CMDS);
12fad3f9 1094
06296a1e 1095 ata_print_version_once(&pdev->dev, DRV_VERSION);
1da177e4 1096
5b66c829
AC		 1097 /* The AHCI driver can only drive the SATA ports, the PATA driver
1098 can drive them all so if both drivers are selected make sure
1099 AHCI stays out of the way */
1100 if (pdev->vendor == PCI_VENDOR_ID_MARVELL && !marvell_enable)
1101 return -ENODEV;
1102
c6353b45
TH		 1103 /*
1104 * For some reason, MCP89 on MacBook 7,1 doesn't work with
1105 * ahci, use ata_generic instead.
1106 */
1107 if (pdev->vendor == PCI_VENDOR_ID_NVIDIA &&
1108 pdev->device == PCI_DEVICE_ID_NVIDIA_NFORCE_MCP89_SATA &&
1109 pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE &&
1110 pdev->subsystem_device == 0xcb89)
1111 return -ENODEV;
1112
7a02267e
MN		 1113 /* Promise's PDC42819 is a SAS/SATA controller that has an AHCI mode.
1114 * At the moment, we can only use the AHCI mode. Let the users know
1115 * that for SAS drives they're out of luck.
1116 */
1117 if (pdev->vendor == PCI_VENDOR_ID_PROMISE)
a44fec1f
JP		 1118 dev_info(&pdev->dev,
1119 "PDC42819 can only drive SATA devices with this driver\n");
7a02267e 1120
7f9c9f8e 1121 /* Both Connext and Enmotus devices use non-standard BARs */
318893e1
AR		 1122 if (pdev->vendor == PCI_VENDOR_ID_STMICRO && pdev->device == 0xCC06)
1123 ahci_pci_bar = AHCI_PCI_BAR_STA2X11;
7f9c9f8e
HD		 1124 else if (pdev->vendor == 0x1c44 && pdev->device == 0x8000)
1125 ahci_pci_bar = AHCI_PCI_BAR_ENMOTUS;
318893e1 1126
4447d351 1127 /* acquire resources */
24dc5f33 1128 rc = pcim_enable_device(pdev);
1da177e4
LT		 1129 if (rc)
1130 return rc;
1131
dea55137
TH		 1132 /* AHCI controllers often implement SFF compatible interface.
1133 * Grab all PCI BARs just in case.
1134 */
318893e1 1135 rc = pcim_iomap_regions_request_all(pdev, 1 << ahci_pci_bar, DRV_NAME);
0d5ff566 1136 if (rc == -EBUSY)
24dc5f33 1137 pcim_pin_device(pdev);
0d5ff566 1138 if (rc)
24dc5f33 1139 return rc;
1da177e4 1140
c4f7792c
TH		 1141 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
1142 (pdev->device == 0x2652 || pdev->device == 0x2653)) {
1143 u8 map;
1144
1145 /* ICH6s share the same PCI ID for both piix and ahci
1146 * modes. Enabling ahci mode while MAP indicates
1147 * combined mode is a bad idea. Yield to ata_piix.
1148 */
1149 pci_read_config_byte(pdev, ICH_MAP, &map);
1150 if (map & 0x3) {
a44fec1f
JP		 1151 dev_info(&pdev->dev,
1152 "controller is in combined mode, can't enable AHCI mode\n");
c4f7792c
TH		 1153 return -ENODEV;
1154 }
1155 }
1156
24dc5f33
TH		 1157 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
1158 if (!hpriv)
1159 return -ENOMEM;
417a1a6d
TH		 1160 hpriv->flags |= (unsigned long)pi.private_data;
1161
e297d99e
TH		 1162 /* MCP65 revision A1 and A2 can't do MSI */
1163 if (board_id == board_ahci_mcp65 &&
1164 (pdev->revision == 0xa1 || pdev->revision == 0xa2))
1165 hpriv->flags |= AHCI_HFLAG_NO_MSI;
1166
e427fe04
SH		 1167 /* SB800 does NOT need the workaround to ignore SERR_INTERNAL */
1168 if (board_id == board_ahci_sb700 && pdev->revision >= 0x40)
1169 hpriv->flags &= ~AHCI_HFLAG_IGN_SERR_INTERNAL;
1170
2fcad9d2
TH		 1171 /* only some SB600s can do 64bit DMA */
1172 if (ahci_sb600_enable_64bit(pdev))
1173 hpriv->flags &= ~AHCI_HFLAG_32BIT_ONLY;
58a09b38 1174
31b239ad
TH		 1175 if ((hpriv->flags & AHCI_HFLAG_NO_MSI) || pci_enable_msi(pdev))
1176 pci_intx(pdev, 1);
1da177e4 1177
318893e1 1178 hpriv->mmio = pcim_iomap_table(pdev)[ahci_pci_bar];
d8993349 1179
4447d351 1180 /* save initial config */
394d6e53 1181 ahci_pci_save_initial_config(pdev, hpriv);
1da177e4 1182
4447d351 1183 /* prepare host */
453d3131
RH		 1184 if (hpriv->cap & HOST_CAP_NCQ) {
1185 pi.flags |= ATA_FLAG_NCQ;
83f2b963
TH		 1186 /*
1187 * Auto-activate optimization is supposed to be
1188 * supported on all AHCI controllers indicating NCQ
1189 * capability, but it seems to be broken on some
1190 * chipsets including NVIDIAs.
1191 */
1192 if (!(hpriv->flags & AHCI_HFLAG_NO_FPDMA_AA))
453d3131
RH		 1193 pi.flags |= ATA_FLAG_FPDMA_AA;
1194 }
1da177e4 1195
7d50b60b
TH		 1196 if (hpriv->cap & HOST_CAP_PMP)
1197 pi.flags |= ATA_FLAG_PMP;
1198
0cbb0e77 1199 ahci_set_em_messages(hpriv, &pi);
18f7ba4c 1200
1fd68434
RW		 1201 if (ahci_broken_system_poweroff(pdev)) {
1202 pi.flags |= ATA_FLAG_NO_POWEROFF_SPINDOWN;
1203 dev_info(&pdev->dev,
1204 "quirky BIOS, skipping spindown on poweroff\n");
1205 }
1206
9b10ae86
TH		 1207 if (ahci_broken_suspend(pdev)) {
1208 hpriv->flags |= AHCI_HFLAG_NO_SUSPEND;
a44fec1f
JP		 1209 dev_warn(&pdev->dev,
1210 "BIOS update required for suspend/resume\n");
9b10ae86
TH		 1211 }
1212
5594639a
TH		 1213 if (ahci_broken_online(pdev)) {
1214 hpriv->flags |= AHCI_HFLAG_SRST_TOUT_IS_OFFLINE;
1215 dev_info(&pdev->dev,
1216 "online status unreliable, applying workaround\n");
1217 }
1218
837f5f8f
TH		 1219 /* CAP.NP sometimes indicate the index of the last enabled
1220 * port, at other times, that of the last possible port, so
1221 * determining the maximum port number requires looking at
1222 * both CAP.NP and port_map.
1223 */
1224 n_ports = max(ahci_nr_ports(hpriv->cap), fls(hpriv->port_map));
1225
1226 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
4447d351
TH		 1227 if (!host)
1228 return -ENOMEM;
4447d351
TH		 1229 host->private_data = hpriv;
1230
f3d7f23f 1231 if (!(hpriv->cap & HOST_CAP_SSS) || ahci_ignore_sss)
886ad09f 1232 host->flags |= ATA_HOST_PARALLEL_SCAN;
f3d7f23f
AV		 1233 else
1234 printk(KERN_INFO "ahci: SSS flag set, parallel bus scan disabled\n");
886ad09f 1235
18f7ba4c
KCA		 1236 if (pi.flags & ATA_FLAG_EM)
1237 ahci_reset_em(host);
1238
4447d351 1239 for (i = 0; i < host->n_ports; i++) {
dab632e8 1240 struct ata_port *ap = host->ports[i];
4447d351 1241
318893e1
AR		 1242 ata_port_pbar_desc(ap, ahci_pci_bar, -1, "abar");
1243 ata_port_pbar_desc(ap, ahci_pci_bar,
cbcdd875
TH		 1244 0x100 + ap->port_no * 0x80, "port");
1245
18f7ba4c
KCA		 1246 /* set enclosure management message type */
1247 if (ap->flags & ATA_FLAG_EM)
008dbd61 1248 ap->em_message_type = hpriv->em_msg_type;
18f7ba4c
KCA		 1249
1250
dab632e8 1251 /* disabled/not-implemented port */
350756f6 1252 if (!(hpriv->port_map & (1 << i)))
dab632e8 1253 ap->ops = &ata_dummy_port_ops;
4447d351 1254 }
d447df14 1255
edc93052
TH		 1256 /* apply workaround for ASUS P5W DH Deluxe mainboard */
1257 ahci_p5wdh_workaround(host);
1258
f80ae7e4
TH		 1259 /* apply gtf filter quirk */
1260 ahci_gtf_filter_workaround(host);
1261
4447d351
TH		 1262 /* initialize adapter */
1263 rc = ahci_configure_dma_masks(pdev, hpriv->cap & HOST_CAP_64);
1da177e4 1264 if (rc)
24dc5f33 1265 return rc;
1da177e4 1266
3303040d 1267 rc = ahci_pci_reset_controller(host);
4447d351
TH		 1268 if (rc)
1269 return rc;
1da177e4 1270
781d6550 1271 ahci_pci_init_controller(host);
439fcaec 1272 ahci_pci_print_info(host);
1da177e4 1273
4447d351
TH		 1274 pci_set_master(pdev);
1275 return ata_host_activate(host, pdev->irq, ahci_interrupt, IRQF_SHARED,
1276 &ahci_sht);
907f4678 1277}
1da177e4 1278
2fc75da0 1279module_pci_driver(ahci_pci_driver);
1da177e4
LT		 1280
1281MODULE_AUTHOR("Jeff Garzik");
1282MODULE_DESCRIPTION("AHCI SATA low-level driver");
1283MODULE_LICENSE("GPL");
1284MODULE_DEVICE_TABLE(pci, ahci_pci_tbl);
6885433c 1285MODULE_VERSION(DRV_VERSION);
Linux kernel - Deliverables
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