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ahci: recognize Marvell 88se9125 PCIe SATA 6.0 Gb/s controller
[deliverable/linux.git] / drivers / ata / ahci.c
CommitLineData
1da177e4
LT		 1/*
2 * ahci.c - AHCI SATA support
3 *
af36d7f0
JG		 4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
7 *
8 * Copyright 2004-2005 Red Hat, Inc.
9 *
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
24 *
25 *
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
28 *
29 * AHCI hardware documentation:
1da177e4 30 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
af36d7f0 31 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
1da177e4
LT		 32 *
33 */
34
35#include <linux/kernel.h>
36#include <linux/module.h>
37#include <linux/pci.h>
38#include <linux/init.h>
39#include <linux/blkdev.h>
40#include <linux/delay.h>
41#include <linux/interrupt.h>
87507cfd 42#include <linux/dma-mapping.h>
a9524a76 43#include <linux/device.h>
edc93052 44#include <linux/dmi.h>
5a0e3ad6 45#include <linux/gfp.h>
1da177e4 46#include <scsi/scsi_host.h>
193515d5 47#include <scsi/scsi_cmnd.h>
1da177e4 48#include <linux/libata.h>
365cfa1e 49#include "ahci.h"
1da177e4
LT		 50
51#define DRV_NAME "ahci"
7d50b60b 52#define DRV_VERSION "3.0"
1da177e4 53
1da177e4
LT		 54enum {
55 AHCI_PCI_BAR = 5,
441577ef
TH		 56};
57
58enum board_ids {
59 /* board IDs by feature in alphabetical order */
60 board_ahci,
61 board_ahci_ign_iferr,
62 board_ahci_nosntf,
5f173107 63 board_ahci_yes_fbs,
1da177e4 64
441577ef
TH		 65 /* board IDs for specific chipsets in alphabetical order */
66 board_ahci_mcp65,
83f2b963
TH		 67 board_ahci_mcp77,
68 board_ahci_mcp89,
441577ef
TH		 69 board_ahci_mv,
70 board_ahci_sb600,
71 board_ahci_sb700, /* for SB700 and SB800 */
72 board_ahci_vt8251,
73
74 /* aliases */
75 board_ahci_mcp_linux = board_ahci_mcp65,
76 board_ahci_mcp67 = board_ahci_mcp65,
77 board_ahci_mcp73 = board_ahci_mcp65,
83f2b963 78 board_ahci_mcp79 = board_ahci_mcp77,
1da177e4
LT		 79};
80
2dcb407e 81static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
bd17243a
SH		 82static int ahci_sb600_softreset(struct ata_link *link, unsigned int *class,
83 unsigned long deadline);
a1efdaba
TH		 84static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
85 unsigned long deadline);
86static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
87 unsigned long deadline);
438ac6d5 88#ifdef CONFIG_PM
c1332875
TH		 89static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg);
90static int ahci_pci_device_resume(struct pci_dev *pdev);
438ac6d5 91#endif
ad616ffb 92
fad16e7a
TH		 93static struct scsi_host_template ahci_sht = {
94 AHCI_SHT("ahci"),
95};
96
029cfd6b
TH		 97static struct ata_port_operations ahci_vt8251_ops = {
98 .inherits = &ahci_ops,
a1efdaba 99 .hardreset = ahci_vt8251_hardreset,
029cfd6b 100};
edc93052 101
029cfd6b
TH		 102static struct ata_port_operations ahci_p5wdh_ops = {
103 .inherits = &ahci_ops,
a1efdaba 104 .hardreset = ahci_p5wdh_hardreset,
edc93052
TH		 105};
106
bd17243a
SH		 107static struct ata_port_operations ahci_sb600_ops = {
108 .inherits = &ahci_ops,
109 .softreset = ahci_sb600_softreset,
110 .pmp_softreset = ahci_sb600_softreset,
111};
112
417a1a6d
TH		 113#define AHCI_HFLAGS(flags) .private_data = (void *)(flags)
114
98ac62de 115static const struct ata_port_info ahci_port_info[] = {
441577ef 116 /* by features */
4da646b7 117 [board_ahci] =
1da177e4 118 {
1188c0d8 119 .flags = AHCI_FLAG_COMMON,
14bdef98 120 .pio_mask = ATA_PIO4,
469248ab 121 .udma_mask = ATA_UDMA6,
1da177e4
LT		 122 .port_ops = &ahci_ops,
123 },
441577ef 124 [board_ahci_ign_iferr] =
bf2af2a2 125 {
441577ef 126 AHCI_HFLAGS (AHCI_HFLAG_IGN_IRQ_IF_ERR),
417a1a6d 127 .flags = AHCI_FLAG_COMMON,
14bdef98 128 .pio_mask = ATA_PIO4,
469248ab 129 .udma_mask = ATA_UDMA6,
441577ef 130 .port_ops = &ahci_ops,
bf2af2a2 131 },
441577ef 132 [board_ahci_nosntf] =
41669553 133 {
441577ef 134 AHCI_HFLAGS (AHCI_HFLAG_NO_SNTF),
417a1a6d 135 .flags = AHCI_FLAG_COMMON,
14bdef98 136 .pio_mask = ATA_PIO4,
469248ab 137 .udma_mask = ATA_UDMA6,
41669553
TH		 138 .port_ops = &ahci_ops,
139 },
5f173107
TH		 140 [board_ahci_yes_fbs] =
141 {
142 AHCI_HFLAGS (AHCI_HFLAG_YES_FBS),
143 .flags = AHCI_FLAG_COMMON,
144 .pio_mask = ATA_PIO4,
145 .udma_mask = ATA_UDMA6,
146 .port_ops = &ahci_ops,
147 },
441577ef
TH		 148 /* by chipsets */
149 [board_ahci_mcp65] =
55a61604 150 {
83f2b963
TH		 151 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP |
152 AHCI_HFLAG_YES_NCQ),
153 .flags = AHCI_FLAG_COMMON,
154 .pio_mask = ATA_PIO4,
155 .udma_mask = ATA_UDMA6,
156 .port_ops = &ahci_ops,
157 },
158 [board_ahci_mcp77] =
159 {
160 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP),
161 .flags = AHCI_FLAG_COMMON,
162 .pio_mask = ATA_PIO4,
163 .udma_mask = ATA_UDMA6,
164 .port_ops = &ahci_ops,
165 },
166 [board_ahci_mcp89] =
167 {
168 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA),
417a1a6d 169 .flags = AHCI_FLAG_COMMON,
14bdef98 170 .pio_mask = ATA_PIO4,
469248ab 171 .udma_mask = ATA_UDMA6,
441577ef 172 .port_ops = &ahci_ops,
55a61604 173 },
4da646b7 174 [board_ahci_mv] =
cd70c266 175 {
417a1a6d 176 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_MSI |
17248461 177 AHCI_HFLAG_MV_PATA | AHCI_HFLAG_NO_PMP),
9cbe056f 178 .flags = ATA_FLAG_SATA | ATA_FLAG_PIO_DMA,
14bdef98 179 .pio_mask = ATA_PIO4,
cd70c266
JG		 180 .udma_mask = ATA_UDMA6,
181 .port_ops = &ahci_ops,
182 },
441577ef 183 [board_ahci_sb600] =
e39fc8c9 184 {
441577ef
TH		 185 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL |
186 AHCI_HFLAG_NO_MSI | AHCI_HFLAG_SECT255 |
187 AHCI_HFLAG_32BIT_ONLY),
e39fc8c9 188 .flags = AHCI_FLAG_COMMON,
14bdef98 189 .pio_mask = ATA_PIO4,
e39fc8c9 190 .udma_mask = ATA_UDMA6,
bd17243a 191 .port_ops = &ahci_sb600_ops,
e39fc8c9 192 },
441577ef 193 [board_ahci_sb700] = /* for SB700 and SB800 */
aa431dd3 194 {
441577ef 195 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL),
aa431dd3
TH		 196 .flags = AHCI_FLAG_COMMON,
197 .pio_mask = ATA_PIO4,
198 .udma_mask = ATA_UDMA6,
441577ef 199 .port_ops = &ahci_sb600_ops,
aa431dd3 200 },
441577ef 201 [board_ahci_vt8251] =
1b677afd 202 {
441577ef 203 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_PMP),
1b677afd
SL		 204 .flags = AHCI_FLAG_COMMON,
205 .pio_mask = ATA_PIO4,
206 .udma_mask = ATA_UDMA6,
441577ef 207 .port_ops = &ahci_vt8251_ops,
1b677afd 208 },
1da177e4
LT		 209};
210
3b7d697d 211static const struct pci_device_id ahci_pci_tbl[] = {
fe7fa31a 212 /* Intel */
54bb3a94
JG		 213 { PCI_VDEVICE(INTEL, 0x2652), board_ahci }, /* ICH6 */
214 { PCI_VDEVICE(INTEL, 0x2653), board_ahci }, /* ICH6M */
215 { PCI_VDEVICE(INTEL, 0x27c1), board_ahci }, /* ICH7 */
216 { PCI_VDEVICE(INTEL, 0x27c5), board_ahci }, /* ICH7M */
217 { PCI_VDEVICE(INTEL, 0x27c3), board_ahci }, /* ICH7R */
82490c09 218 { PCI_VDEVICE(AL, 0x5288), board_ahci_ign_iferr }, /* ULi M5288 */
54bb3a94
JG		 219 { PCI_VDEVICE(INTEL, 0x2681), board_ahci }, /* ESB2 */
220 { PCI_VDEVICE(INTEL, 0x2682), board_ahci }, /* ESB2 */
221 { PCI_VDEVICE(INTEL, 0x2683), board_ahci }, /* ESB2 */
222 { PCI_VDEVICE(INTEL, 0x27c6), board_ahci }, /* ICH7-M DH */
7a234aff 223 { PCI_VDEVICE(INTEL, 0x2821), board_ahci }, /* ICH8 */
1b677afd 224 { PCI_VDEVICE(INTEL, 0x2822), board_ahci_nosntf }, /* ICH8 */
7a234aff
TH		 225 { PCI_VDEVICE(INTEL, 0x2824), board_ahci }, /* ICH8 */
226 { PCI_VDEVICE(INTEL, 0x2829), board_ahci }, /* ICH8M */
227 { PCI_VDEVICE(INTEL, 0x282a), board_ahci }, /* ICH8M */
228 { PCI_VDEVICE(INTEL, 0x2922), board_ahci }, /* ICH9 */
229 { PCI_VDEVICE(INTEL, 0x2923), board_ahci }, /* ICH9 */
230 { PCI_VDEVICE(INTEL, 0x2924), board_ahci }, /* ICH9 */
231 { PCI_VDEVICE(INTEL, 0x2925), board_ahci }, /* ICH9 */
232 { PCI_VDEVICE(INTEL, 0x2927), board_ahci }, /* ICH9 */
233 { PCI_VDEVICE(INTEL, 0x2929), board_ahci }, /* ICH9M */
234 { PCI_VDEVICE(INTEL, 0x292a), board_ahci }, /* ICH9M */
235 { PCI_VDEVICE(INTEL, 0x292b), board_ahci }, /* ICH9M */
236 { PCI_VDEVICE(INTEL, 0x292c), board_ahci }, /* ICH9M */
237 { PCI_VDEVICE(INTEL, 0x292f), board_ahci }, /* ICH9M */
238 { PCI_VDEVICE(INTEL, 0x294d), board_ahci }, /* ICH9 */
239 { PCI_VDEVICE(INTEL, 0x294e), board_ahci }, /* ICH9M */
d4155e6f
JG		 240 { PCI_VDEVICE(INTEL, 0x502a), board_ahci }, /* Tolapai */
241 { PCI_VDEVICE(INTEL, 0x502b), board_ahci }, /* Tolapai */
16ad1ad9 242 { PCI_VDEVICE(INTEL, 0x3a05), board_ahci }, /* ICH10 */
b2dde6af 243 { PCI_VDEVICE(INTEL, 0x3a22), board_ahci }, /* ICH10 */
16ad1ad9 244 { PCI_VDEVICE(INTEL, 0x3a25), board_ahci }, /* ICH10 */
c1f57d9b
DM		 245 { PCI_VDEVICE(INTEL, 0x3b22), board_ahci }, /* PCH AHCI */
246 { PCI_VDEVICE(INTEL, 0x3b23), board_ahci }, /* PCH AHCI */
adcb5308 247 { PCI_VDEVICE(INTEL, 0x3b24), board_ahci }, /* PCH RAID */
8e48b6b3 248 { PCI_VDEVICE(INTEL, 0x3b25), board_ahci }, /* PCH RAID */
c1f57d9b 249 { PCI_VDEVICE(INTEL, 0x3b29), board_ahci }, /* PCH AHCI */
adcb5308 250 { PCI_VDEVICE(INTEL, 0x3b2b), board_ahci }, /* PCH RAID */
8e48b6b3 251 { PCI_VDEVICE(INTEL, 0x3b2c), board_ahci }, /* PCH RAID */
c1f57d9b 252 { PCI_VDEVICE(INTEL, 0x3b2f), board_ahci }, /* PCH AHCI */
5623cab8
SH		 253 { PCI_VDEVICE(INTEL, 0x1c02), board_ahci }, /* CPT AHCI */
254 { PCI_VDEVICE(INTEL, 0x1c03), board_ahci }, /* CPT AHCI */
255 { PCI_VDEVICE(INTEL, 0x1c04), board_ahci }, /* CPT RAID */
256 { PCI_VDEVICE(INTEL, 0x1c05), board_ahci }, /* CPT RAID */
257 { PCI_VDEVICE(INTEL, 0x1c06), board_ahci }, /* CPT RAID */
258 { PCI_VDEVICE(INTEL, 0x1c07), board_ahci }, /* CPT RAID */
992b3fb9
SH		 259 { PCI_VDEVICE(INTEL, 0x1d02), board_ahci }, /* PBG AHCI */
260 { PCI_VDEVICE(INTEL, 0x1d04), board_ahci }, /* PBG RAID */
261 { PCI_VDEVICE(INTEL, 0x1d06), board_ahci }, /* PBG RAID */
a4a461a6 262 { PCI_VDEVICE(INTEL, 0x2323), board_ahci }, /* DH89xxCC AHCI */
fe7fa31a 263
e34bb370
TH		 264 /* JMicron 360/1/3/5/6, match class to avoid IDE function */
265 { PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
266 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci_ign_iferr },
fe7fa31a
JG		 267
268 /* ATI */
c65ec1c2 269 { PCI_VDEVICE(ATI, 0x4380), board_ahci_sb600 }, /* ATI SB600 */
e39fc8c9
SH		 270 { PCI_VDEVICE(ATI, 0x4390), board_ahci_sb700 }, /* ATI SB700/800 */
271 { PCI_VDEVICE(ATI, 0x4391), board_ahci_sb700 }, /* ATI SB700/800 */
272 { PCI_VDEVICE(ATI, 0x4392), board_ahci_sb700 }, /* ATI SB700/800 */
273 { PCI_VDEVICE(ATI, 0x4393), board_ahci_sb700 }, /* ATI SB700/800 */
274 { PCI_VDEVICE(ATI, 0x4394), board_ahci_sb700 }, /* ATI SB700/800 */
275 { PCI_VDEVICE(ATI, 0x4395), board_ahci_sb700 }, /* ATI SB700/800 */
fe7fa31a 276
e2dd90b1 277 /* AMD */
5deab536 278 { PCI_VDEVICE(AMD, 0x7800), board_ahci }, /* AMD Hudson-2 */
e2dd90b1
SH		 279 /* AMD is using RAID class only for ahci controllers */
280 { PCI_VENDOR_ID_AMD, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
281 PCI_CLASS_STORAGE_RAID << 8, 0xffffff, board_ahci },
282
fe7fa31a 283 /* VIA */
54bb3a94 284 { PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251 }, /* VIA VT8251 */
bf335542 285 { PCI_VDEVICE(VIA, 0x6287), board_ahci_vt8251 }, /* VIA VT8251 */
fe7fa31a
JG		 286
287 /* NVIDIA */
e297d99e
TH		 288 { PCI_VDEVICE(NVIDIA, 0x044c), board_ahci_mcp65 }, /* MCP65 */
289 { PCI_VDEVICE(NVIDIA, 0x044d), board_ahci_mcp65 }, /* MCP65 */
290 { PCI_VDEVICE(NVIDIA, 0x044e), board_ahci_mcp65 }, /* MCP65 */
291 { PCI_VDEVICE(NVIDIA, 0x044f), board_ahci_mcp65 }, /* MCP65 */
292 { PCI_VDEVICE(NVIDIA, 0x045c), board_ahci_mcp65 }, /* MCP65 */
293 { PCI_VDEVICE(NVIDIA, 0x045d), board_ahci_mcp65 }, /* MCP65 */
294 { PCI_VDEVICE(NVIDIA, 0x045e), board_ahci_mcp65 }, /* MCP65 */
295 { PCI_VDEVICE(NVIDIA, 0x045f), board_ahci_mcp65 }, /* MCP65 */
441577ef
TH		 296 { PCI_VDEVICE(NVIDIA, 0x0550), board_ahci_mcp67 }, /* MCP67 */
297 { PCI_VDEVICE(NVIDIA, 0x0551), board_ahci_mcp67 }, /* MCP67 */
298 { PCI_VDEVICE(NVIDIA, 0x0552), board_ahci_mcp67 }, /* MCP67 */
299 { PCI_VDEVICE(NVIDIA, 0x0553), board_ahci_mcp67 }, /* MCP67 */
300 { PCI_VDEVICE(NVIDIA, 0x0554), board_ahci_mcp67 }, /* MCP67 */
301 { PCI_VDEVICE(NVIDIA, 0x0555), board_ahci_mcp67 }, /* MCP67 */
302 { PCI_VDEVICE(NVIDIA, 0x0556), board_ahci_mcp67 }, /* MCP67 */
303 { PCI_VDEVICE(NVIDIA, 0x0557), board_ahci_mcp67 }, /* MCP67 */
304 { PCI_VDEVICE(NVIDIA, 0x0558), board_ahci_mcp67 }, /* MCP67 */
305 { PCI_VDEVICE(NVIDIA, 0x0559), board_ahci_mcp67 }, /* MCP67 */
306 { PCI_VDEVICE(NVIDIA, 0x055a), board_ahci_mcp67 }, /* MCP67 */
307 { PCI_VDEVICE(NVIDIA, 0x055b), board_ahci_mcp67 }, /* MCP67 */
308 { PCI_VDEVICE(NVIDIA, 0x0580), board_ahci_mcp_linux }, /* Linux ID */
309 { PCI_VDEVICE(NVIDIA, 0x0581), board_ahci_mcp_linux }, /* Linux ID */
310 { PCI_VDEVICE(NVIDIA, 0x0582), board_ahci_mcp_linux }, /* Linux ID */
311 { PCI_VDEVICE(NVIDIA, 0x0583), board_ahci_mcp_linux }, /* Linux ID */
312 { PCI_VDEVICE(NVIDIA, 0x0584), board_ahci_mcp_linux }, /* Linux ID */
313 { PCI_VDEVICE(NVIDIA, 0x0585), board_ahci_mcp_linux }, /* Linux ID */
314 { PCI_VDEVICE(NVIDIA, 0x0586), board_ahci_mcp_linux }, /* Linux ID */
315 { PCI_VDEVICE(NVIDIA, 0x0587), board_ahci_mcp_linux }, /* Linux ID */
316 { PCI_VDEVICE(NVIDIA, 0x0588), board_ahci_mcp_linux }, /* Linux ID */
317 { PCI_VDEVICE(NVIDIA, 0x0589), board_ahci_mcp_linux }, /* Linux ID */
318 { PCI_VDEVICE(NVIDIA, 0x058a), board_ahci_mcp_linux }, /* Linux ID */
319 { PCI_VDEVICE(NVIDIA, 0x058b), board_ahci_mcp_linux }, /* Linux ID */
320 { PCI_VDEVICE(NVIDIA, 0x058c), board_ahci_mcp_linux }, /* Linux ID */
321 { PCI_VDEVICE(NVIDIA, 0x058d), board_ahci_mcp_linux }, /* Linux ID */
322 { PCI_VDEVICE(NVIDIA, 0x058e), board_ahci_mcp_linux }, /* Linux ID */
323 { PCI_VDEVICE(NVIDIA, 0x058f), board_ahci_mcp_linux }, /* Linux ID */
324 { PCI_VDEVICE(NVIDIA, 0x07f0), board_ahci_mcp73 }, /* MCP73 */
325 { PCI_VDEVICE(NVIDIA, 0x07f1), board_ahci_mcp73 }, /* MCP73 */
326 { PCI_VDEVICE(NVIDIA, 0x07f2), board_ahci_mcp73 }, /* MCP73 */
327 { PCI_VDEVICE(NVIDIA, 0x07f3), board_ahci_mcp73 }, /* MCP73 */
328 { PCI_VDEVICE(NVIDIA, 0x07f4), board_ahci_mcp73 }, /* MCP73 */
329 { PCI_VDEVICE(NVIDIA, 0x07f5), board_ahci_mcp73 }, /* MCP73 */
330 { PCI_VDEVICE(NVIDIA, 0x07f6), board_ahci_mcp73 }, /* MCP73 */
331 { PCI_VDEVICE(NVIDIA, 0x07f7), board_ahci_mcp73 }, /* MCP73 */
332 { PCI_VDEVICE(NVIDIA, 0x07f8), board_ahci_mcp73 }, /* MCP73 */
333 { PCI_VDEVICE(NVIDIA, 0x07f9), board_ahci_mcp73 }, /* MCP73 */
334 { PCI_VDEVICE(NVIDIA, 0x07fa), board_ahci_mcp73 }, /* MCP73 */
335 { PCI_VDEVICE(NVIDIA, 0x07fb), board_ahci_mcp73 }, /* MCP73 */
336 { PCI_VDEVICE(NVIDIA, 0x0ad0), board_ahci_mcp77 }, /* MCP77 */
337 { PCI_VDEVICE(NVIDIA, 0x0ad1), board_ahci_mcp77 }, /* MCP77 */
338 { PCI_VDEVICE(NVIDIA, 0x0ad2), board_ahci_mcp77 }, /* MCP77 */
339 { PCI_VDEVICE(NVIDIA, 0x0ad3), board_ahci_mcp77 }, /* MCP77 */
340 { PCI_VDEVICE(NVIDIA, 0x0ad4), board_ahci_mcp77 }, /* MCP77 */
341 { PCI_VDEVICE(NVIDIA, 0x0ad5), board_ahci_mcp77 }, /* MCP77 */
342 { PCI_VDEVICE(NVIDIA, 0x0ad6), board_ahci_mcp77 }, /* MCP77 */
343 { PCI_VDEVICE(NVIDIA, 0x0ad7), board_ahci_mcp77 }, /* MCP77 */
344 { PCI_VDEVICE(NVIDIA, 0x0ad8), board_ahci_mcp77 }, /* MCP77 */
345 { PCI_VDEVICE(NVIDIA, 0x0ad9), board_ahci_mcp77 }, /* MCP77 */
346 { PCI_VDEVICE(NVIDIA, 0x0ada), board_ahci_mcp77 }, /* MCP77 */
347 { PCI_VDEVICE(NVIDIA, 0x0adb), board_ahci_mcp77 }, /* MCP77 */
348 { PCI_VDEVICE(NVIDIA, 0x0ab4), board_ahci_mcp79 }, /* MCP79 */
349 { PCI_VDEVICE(NVIDIA, 0x0ab5), board_ahci_mcp79 }, /* MCP79 */
350 { PCI_VDEVICE(NVIDIA, 0x0ab6), board_ahci_mcp79 }, /* MCP79 */
351 { PCI_VDEVICE(NVIDIA, 0x0ab7), board_ahci_mcp79 }, /* MCP79 */
352 { PCI_VDEVICE(NVIDIA, 0x0ab8), board_ahci_mcp79 }, /* MCP79 */
353 { PCI_VDEVICE(NVIDIA, 0x0ab9), board_ahci_mcp79 }, /* MCP79 */
354 { PCI_VDEVICE(NVIDIA, 0x0aba), board_ahci_mcp79 }, /* MCP79 */
355 { PCI_VDEVICE(NVIDIA, 0x0abb), board_ahci_mcp79 }, /* MCP79 */
356 { PCI_VDEVICE(NVIDIA, 0x0abc), board_ahci_mcp79 }, /* MCP79 */
357 { PCI_VDEVICE(NVIDIA, 0x0abd), board_ahci_mcp79 }, /* MCP79 */
358 { PCI_VDEVICE(NVIDIA, 0x0abe), board_ahci_mcp79 }, /* MCP79 */
359 { PCI_VDEVICE(NVIDIA, 0x0abf), board_ahci_mcp79 }, /* MCP79 */
360 { PCI_VDEVICE(NVIDIA, 0x0d84), board_ahci_mcp89 }, /* MCP89 */
361 { PCI_VDEVICE(NVIDIA, 0x0d85), board_ahci_mcp89 }, /* MCP89 */
362 { PCI_VDEVICE(NVIDIA, 0x0d86), board_ahci_mcp89 }, /* MCP89 */
363 { PCI_VDEVICE(NVIDIA, 0x0d87), board_ahci_mcp89 }, /* MCP89 */
364 { PCI_VDEVICE(NVIDIA, 0x0d88), board_ahci_mcp89 }, /* MCP89 */
365 { PCI_VDEVICE(NVIDIA, 0x0d89), board_ahci_mcp89 }, /* MCP89 */
366 { PCI_VDEVICE(NVIDIA, 0x0d8a), board_ahci_mcp89 }, /* MCP89 */
367 { PCI_VDEVICE(NVIDIA, 0x0d8b), board_ahci_mcp89 }, /* MCP89 */
368 { PCI_VDEVICE(NVIDIA, 0x0d8c), board_ahci_mcp89 }, /* MCP89 */
369 { PCI_VDEVICE(NVIDIA, 0x0d8d), board_ahci_mcp89 }, /* MCP89 */
370 { PCI_VDEVICE(NVIDIA, 0x0d8e), board_ahci_mcp89 }, /* MCP89 */
371 { PCI_VDEVICE(NVIDIA, 0x0d8f), board_ahci_mcp89 }, /* MCP89 */
fe7fa31a 372
95916edd 373 /* SiS */
20e2de4a
TH		 374 { PCI_VDEVICE(SI, 0x1184), board_ahci }, /* SiS 966 */
375 { PCI_VDEVICE(SI, 0x1185), board_ahci }, /* SiS 968 */
376 { PCI_VDEVICE(SI, 0x0186), board_ahci }, /* SiS 968 */
95916edd 377
cd70c266
JG		 378 /* Marvell */
379 { PCI_VDEVICE(MARVELL, 0x6145), board_ahci_mv }, /* 6145 */
c40e7cb8 380 { PCI_VDEVICE(MARVELL, 0x6121), board_ahci_mv }, /* 6121 */
5f173107 381 { PCI_DEVICE(0x1b4b, 0x9123),
10aca06c
AH		 382 .class = PCI_CLASS_STORAGE_SATA_AHCI,
383 .class_mask = 0xffffff,
5f173107 384 .driver_data = board_ahci_yes_fbs }, /* 88se9128 */
467b41c6
PJ		 385 { PCI_DEVICE(0x1b4b, 0x9125),
386 .driver_data = board_ahci_yes_fbs }, /* 88se9125 */
cd70c266 387
c77a036b
MN		 388 /* Promise */
389 { PCI_VDEVICE(PROMISE, 0x3f20), board_ahci }, /* PDC42819 */
390
415ae2b5
JG		 391 /* Generic, PCI class code for AHCI */
392 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
c9f89475 393 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci },
415ae2b5 394
1da177e4
LT		 395 { } /* terminate list */
396};
397
398
399static struct pci_driver ahci_pci_driver = {
400 .name = DRV_NAME,
401 .id_table = ahci_pci_tbl,
402 .probe = ahci_init_one,
24dc5f33 403 .remove = ata_pci_remove_one,
438ac6d5 404#ifdef CONFIG_PM
c1332875 405 .suspend = ahci_pci_device_suspend,
365cfa1e
AV		 406 .resume = ahci_pci_device_resume,
407#endif
408};
1da177e4 409
365cfa1e
AV		 410#if defined(CONFIG_PATA_MARVELL) || defined(CONFIG_PATA_MARVELL_MODULE)
411static int marvell_enable;
412#else
413static int marvell_enable = 1;
414#endif
415module_param(marvell_enable, int, 0644);
416MODULE_PARM_DESC(marvell_enable, "Marvell SATA via AHCI (1 = enabled)");
d28f87aa 417
1da177e4 418
365cfa1e
AV		 419static void ahci_pci_save_initial_config(struct pci_dev *pdev,
420 struct ahci_host_priv *hpriv)
421{
422 unsigned int force_port_map = 0;
423 unsigned int mask_port_map = 0;
67846b30 424
365cfa1e
AV		 425 if (pdev->vendor == PCI_VENDOR_ID_JMICRON && pdev->device == 0x2361) {
426 dev_info(&pdev->dev, "JMB361 has only one port\n");
427 force_port_map = 1;
1da177e4
LT		 428 }
429
365cfa1e
AV		 430 /*
431 * Temporary Marvell 6145 hack: PATA port presence
432 * is asserted through the standard AHCI port
433 * presence register, as bit 4 (counting from 0)
d28f87aa 434 */
365cfa1e
AV		 435 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
436 if (pdev->device == 0x6121)
437 mask_port_map = 0x3;
438 else
439 mask_port_map = 0xf;
440 dev_info(&pdev->dev,
441 "Disabling your PATA port. Use the boot option 'ahci.marvell_enable=0' to avoid this.\n");
442 }
1da177e4 443
365cfa1e
AV		 444 ahci_save_initial_config(&pdev->dev, hpriv, force_port_map,
445 mask_port_map);
1da177e4
LT		 446}
447
365cfa1e 448static int ahci_pci_reset_controller(struct ata_host *host)
1da177e4 449{
365cfa1e 450 struct pci_dev *pdev = to_pci_dev(host->dev);
7d50b60b 451
365cfa1e 452 ahci_reset_controller(host);
1da177e4 453
365cfa1e
AV		 454 if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
455 struct ahci_host_priv *hpriv = host->private_data;
456 u16 tmp16;
d6ef3153 457
365cfa1e
AV		 458 /* configure PCS */
459 pci_read_config_word(pdev, 0x92, &tmp16);
460 if ((tmp16 & hpriv->port_map) != hpriv->port_map) {
461 tmp16 |= hpriv->port_map;
462 pci_write_config_word(pdev, 0x92, tmp16);
463 }
d6ef3153
SH		 464 }
465
1da177e4
LT		 466 return 0;
467}
468
365cfa1e 469static void ahci_pci_init_controller(struct ata_host *host)
78cd52d0 470{
365cfa1e
AV		 471 struct ahci_host_priv *hpriv = host->private_data;
472 struct pci_dev *pdev = to_pci_dev(host->dev);
473 void __iomem *port_mmio;
78cd52d0 474 u32 tmp;
365cfa1e 475 int mv;
78cd52d0 476
365cfa1e
AV		 477 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
478 if (pdev->device == 0x6121)
479 mv = 2;
480 else
481 mv = 4;
482 port_mmio = __ahci_port_base(host, mv);
78cd52d0 483
365cfa1e 484 writel(0, port_mmio + PORT_IRQ_MASK);
78cd52d0 485
365cfa1e
AV		 486 /* clear port IRQ */
487 tmp = readl(port_mmio + PORT_IRQ_STAT);
488 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
489 if (tmp)
490 writel(tmp, port_mmio + PORT_IRQ_STAT);
78cd52d0
TH		 491 }
492
365cfa1e 493 ahci_init_controller(host);
edc93052
TH		 494}
495
365cfa1e 496static int ahci_sb600_check_ready(struct ata_link *link)
78cd52d0 497{
365cfa1e
AV		 498 void __iomem *port_mmio = ahci_port_base(link->ap);
499 u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF;
500 u32 irq_status = readl(port_mmio + PORT_IRQ_STAT);
501
502 /*
503 * There is no need to check TFDATA if BAD PMP is found due to HW bug,
504 * which can save timeout delay.
505 */
506 if (irq_status & PORT_IRQ_BAD_PMP)
507 return -EIO;
78cd52d0 508
365cfa1e 509 return ata_check_ready(status);
78cd52d0
TH		 510}
511
365cfa1e
AV		 512static int ahci_sb600_softreset(struct ata_link *link, unsigned int *class,
513 unsigned long deadline)
d6ef3153 514{
365cfa1e 515 struct ata_port *ap = link->ap;
d6ef3153 516 void __iomem *port_mmio = ahci_port_base(ap);
365cfa1e 517 int pmp = sata_srst_pmp(link);
d6ef3153 518 int rc;
365cfa1e 519 u32 irq_sts;
d6ef3153 520
365cfa1e 521 DPRINTK("ENTER\n");
d6ef3153 522
365cfa1e
AV		 523 rc = ahci_do_softreset(link, class, pmp, deadline,
524 ahci_sb600_check_ready);
d6ef3153 525
365cfa1e
AV		 526 /*
527 * Soft reset fails on some ATI chips with IPMS set when PMP
528 * is enabled but SATA HDD/ODD is connected to SATA port,
529 * do soft reset again to port 0.
530 */
531 if (rc == -EIO) {
532 irq_sts = readl(port_mmio + PORT_IRQ_STAT);
533 if (irq_sts & PORT_IRQ_BAD_PMP) {
534 ata_link_printk(link, KERN_WARNING,
535 "applying SB600 PMP SRST workaround "
536 "and retrying\n");
537 rc = ahci_do_softreset(link, class, 0, deadline,
538 ahci_check_ready);
539 }
540 }
d6ef3153 541
365cfa1e 542 return rc;
d6ef3153
SH		 543}
544
365cfa1e
AV		 545static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
546 unsigned long deadline)
d6ef3153 547{
365cfa1e
AV		 548 struct ata_port *ap = link->ap;
549 bool online;
d6ef3153
SH		 550 int rc;
551
365cfa1e 552 DPRINTK("ENTER\n");
d6ef3153 553
365cfa1e 554 ahci_stop_engine(ap);
d6ef3153 555
365cfa1e
AV		 556 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
557 deadline, &online, NULL);
d6ef3153
SH		 558
559 ahci_start_engine(ap);
d6ef3153 560
365cfa1e 561 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
d6ef3153 562
365cfa1e
AV		 563 /* vt8251 doesn't clear BSY on signature FIS reception,
564 * request follow-up softreset.
565 */
566 return online ? -EAGAIN : rc;
7d50b60b
TH		 567}
568
365cfa1e
AV		 569static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
570 unsigned long deadline)
7d50b60b 571{
365cfa1e 572 struct ata_port *ap = link->ap;
1c954a4d 573 struct ahci_port_priv *pp = ap->private_data;
365cfa1e
AV		 574 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
575 struct ata_taskfile tf;
576 bool online;
577 int rc;
7d50b60b 578
365cfa1e 579 ahci_stop_engine(ap);
028a2596 580
365cfa1e
AV		 581 /* clear D2H reception area to properly wait for D2H FIS */
582 ata_tf_init(link->device, &tf);
583 tf.command = 0x80;
584 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
7d50b60b 585
365cfa1e
AV		 586 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
587 deadline, &online, NULL);
028a2596 588
365cfa1e 589 ahci_start_engine(ap);
c1332875 590
365cfa1e
AV		 591 /* The pseudo configuration device on SIMG4726 attached to
592 * ASUS P5W-DH Deluxe doesn't send signature FIS after
593 * hardreset if no device is attached to the first downstream
594 * port && the pseudo device locks up on SRST w/ PMP==0. To
595 * work around this, wait for !BSY only briefly. If BSY isn't
596 * cleared, perform CLO and proceed to IDENTIFY (achieved by
597 * ATA_LFLAG_NO_SRST and ATA_LFLAG_ASSUME_ATA).
598 *
599 * Wait for two seconds. Devices attached to downstream port
600 * which can't process the following IDENTIFY after this will
601 * have to be reset again. For most cases, this should
602 * suffice while making probing snappish enough.
603 */
604 if (online) {
605 rc = ata_wait_after_reset(link, jiffies + 2 * HZ,
606 ahci_check_ready);
607 if (rc)
608 ahci_kick_engine(ap);
c1332875 609 }
c1332875
TH		 610 return rc;
611}
612
365cfa1e 613#ifdef CONFIG_PM
c1332875
TH		 614static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg)
615{
cca3974e 616 struct ata_host *host = dev_get_drvdata(&pdev->dev);
9b10ae86 617 struct ahci_host_priv *hpriv = host->private_data;
d8993349 618 void __iomem *mmio = hpriv->mmio;
c1332875
TH		 619 u32 ctl;
620
9b10ae86
TH		 621 if (mesg.event & PM_EVENT_SUSPEND &&
622 hpriv->flags & AHCI_HFLAG_NO_SUSPEND) {
623 dev_printk(KERN_ERR, &pdev->dev,
624 "BIOS update required for suspend/resume\n");
625 return -EIO;
626 }
627
3a2d5b70 628 if (mesg.event & PM_EVENT_SLEEP) {
c1332875
TH		 629 /* AHCI spec rev1.1 section 8.3.3:
630 * Software must disable interrupts prior to requesting a
631 * transition of the HBA to D3 state.
632 */
633 ctl = readl(mmio + HOST_CTL);
634 ctl &= ~HOST_IRQ_EN;
635 writel(ctl, mmio + HOST_CTL);
636 readl(mmio + HOST_CTL); /* flush */
637 }
638
639 return ata_pci_device_suspend(pdev, mesg);
640}
641
642static int ahci_pci_device_resume(struct pci_dev *pdev)
643{
cca3974e 644 struct ata_host *host = dev_get_drvdata(&pdev->dev);
c1332875
TH		 645 int rc;
646
553c4aa6
TH		 647 rc = ata_pci_device_do_resume(pdev);
648 if (rc)
649 return rc;
c1332875
TH		 650
651 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
3303040d 652 rc = ahci_pci_reset_controller(host);
c1332875
TH		 653 if (rc)
654 return rc;
655
781d6550 656 ahci_pci_init_controller(host);
c1332875
TH		 657 }
658
cca3974e 659 ata_host_resume(host);
c1332875
TH		 660
661 return 0;
662}
438ac6d5 663#endif
c1332875 664
4447d351 665static int ahci_configure_dma_masks(struct pci_dev *pdev, int using_dac)
1da177e4 666{
1da177e4 667 int rc;
1da177e4 668
1da177e4 669 if (using_dac &&
6a35528a
YH		 670 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
671 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
1da177e4 672 if (rc) {
284901a9 673 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
1da177e4 674 if (rc) {
a9524a76
JG		 675 dev_printk(KERN_ERR, &pdev->dev,
676 "64-bit DMA enable failed\n");
1da177e4
LT		 677 return rc;
678 }
679 }
1da177e4 680 } else {
284901a9 681 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
1da177e4 682 if (rc) {
a9524a76
JG		 683 dev_printk(KERN_ERR, &pdev->dev,
684 "32-bit DMA enable failed\n");
1da177e4
LT		 685 return rc;
686 }
284901a9 687 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
1da177e4 688 if (rc) {
a9524a76
JG		 689 dev_printk(KERN_ERR, &pdev->dev,
690 "32-bit consistent DMA enable failed\n");
1da177e4
LT		 691 return rc;
692 }
693 }
1da177e4
LT		 694 return 0;
695}
696
439fcaec
AV		 697static void ahci_pci_print_info(struct ata_host *host)
698{
699 struct pci_dev *pdev = to_pci_dev(host->dev);
700 u16 cc;
701 const char *scc_s;
702
703 pci_read_config_word(pdev, 0x0a, &cc);
704 if (cc == PCI_CLASS_STORAGE_IDE)
705 scc_s = "IDE";
706 else if (cc == PCI_CLASS_STORAGE_SATA)
707 scc_s = "SATA";
708 else if (cc == PCI_CLASS_STORAGE_RAID)
709 scc_s = "RAID";
710 else
711 scc_s = "unknown";
712
713 ahci_print_info(host, scc_s);
714}
715
edc93052
TH		 716/* On ASUS P5W DH Deluxe, the second port of PCI device 00:1f.2 is
717 * hardwired to on-board SIMG 4726. The chipset is ICH8 and doesn't
718 * support PMP and the 4726 either directly exports the device
719 * attached to the first downstream port or acts as a hardware storage
720 * controller and emulate a single ATA device (can be RAID 0/1 or some
721 * other configuration).
722 *
723 * When there's no device attached to the first downstream port of the
724 * 4726, "Config Disk" appears, which is a pseudo ATA device to
725 * configure the 4726. However, ATA emulation of the device is very
726 * lame. It doesn't send signature D2H Reg FIS after the initial
727 * hardreset, pukes on SRST w/ PMP==0 and has bunch of other issues.
728 *
729 * The following function works around the problem by always using
730 * hardreset on the port and not depending on receiving signature FIS
731 * afterward. If signature FIS isn't received soon, ATA class is
732 * assumed without follow-up softreset.
733 */
734static void ahci_p5wdh_workaround(struct ata_host *host)
735{
736 static struct dmi_system_id sysids[] = {
737 {
738 .ident = "P5W DH Deluxe",
739 .matches = {
740 DMI_MATCH(DMI_SYS_VENDOR,
741 "ASUSTEK COMPUTER INC"),
742 DMI_MATCH(DMI_PRODUCT_NAME, "P5W DH Deluxe"),
743 },
744 },
745 { }
746 };
747 struct pci_dev *pdev = to_pci_dev(host->dev);
748
749 if (pdev->bus->number == 0 && pdev->devfn == PCI_DEVFN(0x1f, 2) &&
750 dmi_check_system(sysids)) {
751 struct ata_port *ap = host->ports[1];
752
753 dev_printk(KERN_INFO, &pdev->dev, "enabling ASUS P5W DH "
754 "Deluxe on-board SIMG4726 workaround\n");
755
756 ap->ops = &ahci_p5wdh_ops;
757 ap->link.flags |= ATA_LFLAG_NO_SRST | ATA_LFLAG_ASSUME_ATA;
758 }
759}
760
2fcad9d2
TH		 761/* only some SB600 ahci controllers can do 64bit DMA */
762static bool ahci_sb600_enable_64bit(struct pci_dev *pdev)
58a09b38
SH		 763{
764 static const struct dmi_system_id sysids[] = {
03d783bf
TH		 765 /*
766 * The oldest version known to be broken is 0901 and
767 * working is 1501 which was released on 2007-10-26.
2fcad9d2
TH		 768 * Enable 64bit DMA on 1501 and anything newer.
769 *
03d783bf
TH		 770 * Please read bko#9412 for more info.
771 */
58a09b38
SH		 772 {
773 .ident = "ASUS M2A-VM",
774 .matches = {
775 DMI_MATCH(DMI_BOARD_VENDOR,
776 "ASUSTeK Computer INC."),
777 DMI_MATCH(DMI_BOARD_NAME, "M2A-VM"),
778 },
03d783bf 779 .driver_data = "20071026", /* yyyymmdd */
58a09b38 780 },
e65cc194
MN		 781 /*
782 * All BIOS versions for the MSI K9A2 Platinum (MS-7376)
783 * support 64bit DMA.
784 *
785 * BIOS versions earlier than 1.5 had the Manufacturer DMI
786 * fields as "MICRO-STAR INTERANTIONAL CO.,LTD".
787 * This spelling mistake was fixed in BIOS version 1.5, so
788 * 1.5 and later have the Manufacturer as
789 * "MICRO-STAR INTERNATIONAL CO.,LTD".
790 * So try to match on DMI_BOARD_VENDOR of "MICRO-STAR INTER".
791 *
792 * BIOS versions earlier than 1.9 had a Board Product Name
793 * DMI field of "MS-7376". This was changed to be
794 * "K9A2 Platinum (MS-7376)" in version 1.9, but we can still
795 * match on DMI_BOARD_NAME of "MS-7376".
796 */
797 {
798 .ident = "MSI K9A2 Platinum",
799 .matches = {
800 DMI_MATCH(DMI_BOARD_VENDOR,
801 "MICRO-STAR INTER"),
802 DMI_MATCH(DMI_BOARD_NAME, "MS-7376"),
803 },
804 },
58a09b38
SH		 805 { }
806 };
03d783bf 807 const struct dmi_system_id *match;
2fcad9d2
TH		 808 int year, month, date;
809 char buf[9];
58a09b38 810
03d783bf 811 match = dmi_first_match(sysids);
58a09b38 812 if (pdev->bus->number != 0 || pdev->devfn != PCI_DEVFN(0x12, 0) ||
03d783bf 813 !match)
58a09b38
SH		 814 return false;
815
e65cc194
MN		 816 if (!match->driver_data)
817 goto enable_64bit;
818
2fcad9d2
TH		 819 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
820 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
03d783bf 821
e65cc194
MN		 822 if (strcmp(buf, match->driver_data) >= 0)
823 goto enable_64bit;
824 else {
03d783bf
TH		 825 dev_printk(KERN_WARNING, &pdev->dev, "%s: BIOS too old, "
826 "forcing 32bit DMA, update BIOS\n", match->ident);
2fcad9d2
TH		 827 return false;
828 }
e65cc194
MN		 829
830enable_64bit:
831 dev_printk(KERN_WARNING, &pdev->dev, "%s: enabling 64bit DMA\n",
832 match->ident);
833 return true;
58a09b38
SH		 834}
835
1fd68434
RW		 836static bool ahci_broken_system_poweroff(struct pci_dev *pdev)
837{
838 static const struct dmi_system_id broken_systems[] = {
839 {
840 .ident = "HP Compaq nx6310",
841 .matches = {
842 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
843 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq nx6310"),
844 },
845 /* PCI slot number of the controller */
846 .driver_data = (void *)0x1FUL,
847 },
d2f9c061
MR		 848 {
849 .ident = "HP Compaq 6720s",
850 .matches = {
851 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
852 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq 6720s"),
853 },
854 /* PCI slot number of the controller */
855 .driver_data = (void *)0x1FUL,
856 },
1fd68434
RW		 857
858 { } /* terminate list */
859 };
860 const struct dmi_system_id *dmi = dmi_first_match(broken_systems);
861
862 if (dmi) {
863 unsigned long slot = (unsigned long)dmi->driver_data;
864 /* apply the quirk only to on-board controllers */
865 return slot == PCI_SLOT(pdev->devfn);
866 }
867
868 return false;
869}
870
9b10ae86
TH		 871static bool ahci_broken_suspend(struct pci_dev *pdev)
872{
873 static const struct dmi_system_id sysids[] = {
874 /*
875 * On HP dv[4-6] and HDX18 with earlier BIOSen, link
876 * to the harddisk doesn't become online after
877 * resuming from STR. Warn and fail suspend.
9deb3431
TH		 878 *
879 * http://bugzilla.kernel.org/show_bug.cgi?id=12276
880 *
881 * Use dates instead of versions to match as HP is
882 * apparently recycling both product and version
883 * strings.
884 *
885 * http://bugzilla.kernel.org/show_bug.cgi?id=15462
9b10ae86
TH		 886 */
887 {
888 .ident = "dv4",
889 .matches = {
890 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
891 DMI_MATCH(DMI_PRODUCT_NAME,
892 "HP Pavilion dv4 Notebook PC"),
893 },
9deb3431 894 .driver_data = "20090105", /* F.30 */
9b10ae86
TH		 895 },
896 {
897 .ident = "dv5",
898 .matches = {
899 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
900 DMI_MATCH(DMI_PRODUCT_NAME,
901 "HP Pavilion dv5 Notebook PC"),
902 },
9deb3431 903 .driver_data = "20090506", /* F.16 */
9b10ae86
TH		 904 },
905 {
906 .ident = "dv6",
907 .matches = {
908 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
909 DMI_MATCH(DMI_PRODUCT_NAME,
910 "HP Pavilion dv6 Notebook PC"),
911 },
9deb3431 912 .driver_data = "20090423", /* F.21 */
9b10ae86
TH		 913 },
914 {
915 .ident = "HDX18",
916 .matches = {
917 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
918 DMI_MATCH(DMI_PRODUCT_NAME,
919 "HP HDX18 Notebook PC"),
920 },
9deb3431 921 .driver_data = "20090430", /* F.23 */
9b10ae86 922 },
cedc9bf9
TH		 923 /*
924 * Acer eMachines G725 has the same problem. BIOS
925 * V1.03 is known to be broken. V3.04 is known to
926 * work. Inbetween, there are V1.06, V2.06 and V3.03
927 * that we don't have much idea about. For now,
928 * blacklist anything older than V3.04.
9deb3431
TH		 929 *
930 * http://bugzilla.kernel.org/show_bug.cgi?id=15104
cedc9bf9
TH		 931 */
932 {
933 .ident = "G725",
934 .matches = {
935 DMI_MATCH(DMI_SYS_VENDOR, "eMachines"),
936 DMI_MATCH(DMI_PRODUCT_NAME, "eMachines G725"),
937 },
9deb3431 938 .driver_data = "20091216", /* V3.04 */
cedc9bf9 939 },
9b10ae86
TH		 940 { } /* terminate list */
941 };
942 const struct dmi_system_id *dmi = dmi_first_match(sysids);
9deb3431
TH		 943 int year, month, date;
944 char buf[9];
9b10ae86
TH		 945
946 if (!dmi || pdev->bus->number || pdev->devfn != PCI_DEVFN(0x1f, 2))
947 return false;
948
9deb3431
TH		 949 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
950 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
9b10ae86 951
9deb3431 952 return strcmp(buf, dmi->driver_data) < 0;
9b10ae86
TH		 953}
954
5594639a
TH		 955static bool ahci_broken_online(struct pci_dev *pdev)
956{
957#define ENCODE_BUSDEVFN(bus, slot, func) \
958 (void *)(unsigned long)(((bus) << 8) | PCI_DEVFN((slot), (func)))
959 static const struct dmi_system_id sysids[] = {
960 /*
961 * There are several gigabyte boards which use
962 * SIMG5723s configured as hardware RAID. Certain
963 * 5723 firmware revisions shipped there keep the link
964 * online but fail to answer properly to SRST or
965 * IDENTIFY when no device is attached downstream
966 * causing libata to retry quite a few times leading
967 * to excessive detection delay.
968 *
969 * As these firmwares respond to the second reset try
970 * with invalid device signature, considering unknown
971 * sig as offline works around the problem acceptably.
972 */
973 {
974 .ident = "EP45-DQ6",
975 .matches = {
976 DMI_MATCH(DMI_BOARD_VENDOR,
977 "Gigabyte Technology Co., Ltd."),
978 DMI_MATCH(DMI_BOARD_NAME, "EP45-DQ6"),
979 },
980 .driver_data = ENCODE_BUSDEVFN(0x0a, 0x00, 0),
981 },
982 {
983 .ident = "EP45-DS5",
984 .matches = {
985 DMI_MATCH(DMI_BOARD_VENDOR,
986 "Gigabyte Technology Co., Ltd."),
987 DMI_MATCH(DMI_BOARD_NAME, "EP45-DS5"),
988 },
989 .driver_data = ENCODE_BUSDEVFN(0x03, 0x00, 0),
990 },
991 { } /* terminate list */
992 };
993#undef ENCODE_BUSDEVFN
994 const struct dmi_system_id *dmi = dmi_first_match(sysids);
995 unsigned int val;
996
997 if (!dmi)
998 return false;
999
1000 val = (unsigned long)dmi->driver_data;
1001
1002 return pdev->bus->number == (val >> 8) && pdev->devfn == (val & 0xff);
1003}
1004
8e513217 1005#ifdef CONFIG_ATA_ACPI
f80ae7e4
TH		 1006static void ahci_gtf_filter_workaround(struct ata_host *host)
1007{
1008 static const struct dmi_system_id sysids[] = {
1009 /*
1010 * Aspire 3810T issues a bunch of SATA enable commands
1011 * via _GTF including an invalid one and one which is
1012 * rejected by the device. Among the successful ones
1013 * is FPDMA non-zero offset enable which when enabled
1014 * only on the drive side leads to NCQ command
1015 * failures. Filter it out.
1016 */
1017 {
1018 .ident = "Aspire 3810T",
1019 .matches = {
1020 DMI_MATCH(DMI_SYS_VENDOR, "Acer"),
1021 DMI_MATCH(DMI_PRODUCT_NAME, "Aspire 3810T"),
1022 },
1023 .driver_data = (void *)ATA_ACPI_FILTER_FPDMA_OFFSET,
1024 },
1025 { }
1026 };
1027 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1028 unsigned int filter;
1029 int i;
1030
1031 if (!dmi)
1032 return;
1033
1034 filter = (unsigned long)dmi->driver_data;
1035 dev_printk(KERN_INFO, host->dev,
1036 "applying extra ACPI _GTF filter 0x%x for %s\n",
1037 filter, dmi->ident);
1038
1039 for (i = 0; i < host->n_ports; i++) {
1040 struct ata_port *ap = host->ports[i];
1041 struct ata_link *link;
1042 struct ata_device *dev;
1043
1044 ata_for_each_link(link, ap, EDGE)
1045 ata_for_each_dev(dev, link, ALL)
1046 dev->gtf_filter |= filter;
1047 }
1048}
8e513217
MT		 1049#else
1050static inline void ahci_gtf_filter_workaround(struct ata_host *host)
1051{}
1052#endif
f80ae7e4 1053
24dc5f33 1054static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1da177e4
LT		 1055{
1056 static int printed_version;
e297d99e
TH		 1057 unsigned int board_id = ent->driver_data;
1058 struct ata_port_info pi = ahci_port_info[board_id];
4447d351 1059 const struct ata_port_info *ppi[] = { &pi, NULL };
24dc5f33 1060 struct device *dev = &pdev->dev;
1da177e4 1061 struct ahci_host_priv *hpriv;
4447d351 1062 struct ata_host *host;
837f5f8f 1063 int n_ports, i, rc;
1da177e4
LT		 1064
1065 VPRINTK("ENTER\n");
1066
b429dd59 1067 WARN_ON((int)ATA_MAX_QUEUE > AHCI_MAX_CMDS);
12fad3f9 1068
1da177e4 1069 if (!printed_version++)
a9524a76 1070 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
1da177e4 1071
5b66c829
AC		 1072 /* The AHCI driver can only drive the SATA ports, the PATA driver
1073 can drive them all so if both drivers are selected make sure
1074 AHCI stays out of the way */
1075 if (pdev->vendor == PCI_VENDOR_ID_MARVELL && !marvell_enable)
1076 return -ENODEV;
1077
c6353b45
TH		 1078 /*
1079 * For some reason, MCP89 on MacBook 7,1 doesn't work with
1080 * ahci, use ata_generic instead.
1081 */
1082 if (pdev->vendor == PCI_VENDOR_ID_NVIDIA &&
1083 pdev->device == PCI_DEVICE_ID_NVIDIA_NFORCE_MCP89_SATA &&
1084 pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE &&
1085 pdev->subsystem_device == 0xcb89)
1086 return -ENODEV;
1087
7a02267e
MN		 1088 /* Promise's PDC42819 is a SAS/SATA controller that has an AHCI mode.
1089 * At the moment, we can only use the AHCI mode. Let the users know
1090 * that for SAS drives they're out of luck.
1091 */
1092 if (pdev->vendor == PCI_VENDOR_ID_PROMISE)
1093 dev_printk(KERN_INFO, &pdev->dev, "PDC42819 "
1094 "can only drive SATA devices with this driver\n");
1095
4447d351 1096 /* acquire resources */
24dc5f33 1097 rc = pcim_enable_device(pdev);
1da177e4
LT		 1098 if (rc)
1099 return rc;
1100
dea55137
TH		 1101 /* AHCI controllers often implement SFF compatible interface.
1102 * Grab all PCI BARs just in case.
1103 */
1104 rc = pcim_iomap_regions_request_all(pdev, 1 << AHCI_PCI_BAR, DRV_NAME);
0d5ff566 1105 if (rc == -EBUSY)
24dc5f33 1106 pcim_pin_device(pdev);
0d5ff566 1107 if (rc)
24dc5f33 1108 return rc;
1da177e4 1109
c4f7792c
TH		 1110 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
1111 (pdev->device == 0x2652 || pdev->device == 0x2653)) {
1112 u8 map;
1113
1114 /* ICH6s share the same PCI ID for both piix and ahci
1115 * modes. Enabling ahci mode while MAP indicates
1116 * combined mode is a bad idea. Yield to ata_piix.
1117 */
1118 pci_read_config_byte(pdev, ICH_MAP, &map);
1119 if (map & 0x3) {
1120 dev_printk(KERN_INFO, &pdev->dev, "controller is in "
1121 "combined mode, can't enable AHCI mode\n");
1122 return -ENODEV;
1123 }
1124 }
1125
24dc5f33
TH		 1126 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
1127 if (!hpriv)
1128 return -ENOMEM;
417a1a6d
TH		 1129 hpriv->flags |= (unsigned long)pi.private_data;
1130
e297d99e
TH		 1131 /* MCP65 revision A1 and A2 can't do MSI */
1132 if (board_id == board_ahci_mcp65 &&
1133 (pdev->revision == 0xa1 || pdev->revision == 0xa2))
1134 hpriv->flags |= AHCI_HFLAG_NO_MSI;
1135
e427fe04
SH		 1136 /* SB800 does NOT need the workaround to ignore SERR_INTERNAL */
1137 if (board_id == board_ahci_sb700 && pdev->revision >= 0x40)
1138 hpriv->flags &= ~AHCI_HFLAG_IGN_SERR_INTERNAL;
1139
2fcad9d2
TH		 1140 /* only some SB600s can do 64bit DMA */
1141 if (ahci_sb600_enable_64bit(pdev))
1142 hpriv->flags &= ~AHCI_HFLAG_32BIT_ONLY;
58a09b38 1143
31b239ad
TH		 1144 if ((hpriv->flags & AHCI_HFLAG_NO_MSI) || pci_enable_msi(pdev))
1145 pci_intx(pdev, 1);
1da177e4 1146
d8993349
AV		 1147 hpriv->mmio = pcim_iomap_table(pdev)[AHCI_PCI_BAR];
1148
4447d351 1149 /* save initial config */
394d6e53 1150 ahci_pci_save_initial_config(pdev, hpriv);
1da177e4 1151
4447d351 1152 /* prepare host */
453d3131
RH		 1153 if (hpriv->cap & HOST_CAP_NCQ) {
1154 pi.flags |= ATA_FLAG_NCQ;
83f2b963
TH		 1155 /*
1156 * Auto-activate optimization is supposed to be
1157 * supported on all AHCI controllers indicating NCQ
1158 * capability, but it seems to be broken on some
1159 * chipsets including NVIDIAs.
1160 */
1161 if (!(hpriv->flags & AHCI_HFLAG_NO_FPDMA_AA))
453d3131
RH		 1162 pi.flags |= ATA_FLAG_FPDMA_AA;
1163 }
1da177e4 1164
7d50b60b
TH		 1165 if (hpriv->cap & HOST_CAP_PMP)
1166 pi.flags |= ATA_FLAG_PMP;
1167
0cbb0e77 1168 ahci_set_em_messages(hpriv, &pi);
18f7ba4c 1169
1fd68434
RW		 1170 if (ahci_broken_system_poweroff(pdev)) {
1171 pi.flags |= ATA_FLAG_NO_POWEROFF_SPINDOWN;
1172 dev_info(&pdev->dev,
1173 "quirky BIOS, skipping spindown on poweroff\n");
1174 }
1175
9b10ae86
TH		 1176 if (ahci_broken_suspend(pdev)) {
1177 hpriv->flags |= AHCI_HFLAG_NO_SUSPEND;
1178 dev_printk(KERN_WARNING, &pdev->dev,
1179 "BIOS update required for suspend/resume\n");
1180 }
1181
5594639a
TH		 1182 if (ahci_broken_online(pdev)) {
1183 hpriv->flags |= AHCI_HFLAG_SRST_TOUT_IS_OFFLINE;
1184 dev_info(&pdev->dev,
1185 "online status unreliable, applying workaround\n");
1186 }
1187
837f5f8f
TH		 1188 /* CAP.NP sometimes indicate the index of the last enabled
1189 * port, at other times, that of the last possible port, so
1190 * determining the maximum port number requires looking at
1191 * both CAP.NP and port_map.
1192 */
1193 n_ports = max(ahci_nr_ports(hpriv->cap), fls(hpriv->port_map));
1194
1195 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
4447d351
TH		 1196 if (!host)
1197 return -ENOMEM;
4447d351
TH		 1198 host->private_data = hpriv;
1199
f3d7f23f 1200 if (!(hpriv->cap & HOST_CAP_SSS) || ahci_ignore_sss)
886ad09f 1201 host->flags |= ATA_HOST_PARALLEL_SCAN;
f3d7f23f
AV		 1202 else
1203 printk(KERN_INFO "ahci: SSS flag set, parallel bus scan disabled\n");
886ad09f 1204
18f7ba4c
KCA		 1205 if (pi.flags & ATA_FLAG_EM)
1206 ahci_reset_em(host);
1207
4447d351 1208 for (i = 0; i < host->n_ports; i++) {
dab632e8 1209 struct ata_port *ap = host->ports[i];
4447d351 1210
cbcdd875
TH		 1211 ata_port_pbar_desc(ap, AHCI_PCI_BAR, -1, "abar");
1212 ata_port_pbar_desc(ap, AHCI_PCI_BAR,
1213 0x100 + ap->port_no * 0x80, "port");
1214
18f7ba4c
KCA		 1215 /* set enclosure management message type */
1216 if (ap->flags & ATA_FLAG_EM)
008dbd61 1217 ap->em_message_type = hpriv->em_msg_type;
18f7ba4c
KCA		 1218
1219
dab632e8 1220 /* disabled/not-implemented port */
350756f6 1221 if (!(hpriv->port_map & (1 << i)))
dab632e8 1222 ap->ops = &ata_dummy_port_ops;
4447d351 1223 }
d447df14 1224
edc93052
TH		 1225 /* apply workaround for ASUS P5W DH Deluxe mainboard */
1226 ahci_p5wdh_workaround(host);
1227
f80ae7e4
TH		 1228 /* apply gtf filter quirk */
1229 ahci_gtf_filter_workaround(host);
1230
4447d351
TH		 1231 /* initialize adapter */
1232 rc = ahci_configure_dma_masks(pdev, hpriv->cap & HOST_CAP_64);
1da177e4 1233 if (rc)
24dc5f33 1234 return rc;
1da177e4 1235
3303040d 1236 rc = ahci_pci_reset_controller(host);
4447d351
TH		 1237 if (rc)
1238 return rc;
1da177e4 1239
781d6550 1240 ahci_pci_init_controller(host);
439fcaec 1241 ahci_pci_print_info(host);
1da177e4 1242
4447d351
TH		 1243 pci_set_master(pdev);
1244 return ata_host_activate(host, pdev->irq, ahci_interrupt, IRQF_SHARED,
1245 &ahci_sht);
907f4678 1246}
1da177e4
LT		 1247
1248static int __init ahci_init(void)
1249{
b7887196 1250 return pci_register_driver(&ahci_pci_driver);
1da177e4
LT		 1251}
1252
1da177e4
LT		 1253static void __exit ahci_exit(void)
1254{
1255 pci_unregister_driver(&ahci_pci_driver);
1256}
1257
1258
1259MODULE_AUTHOR("Jeff Garzik");
1260MODULE_DESCRIPTION("AHCI SATA low-level driver");
1261MODULE_LICENSE("GPL");
1262MODULE_DEVICE_TABLE(pci, ahci_pci_tbl);
6885433c 1263MODULE_VERSION(DRV_VERSION);
1da177e4
LT		 1264
1265module_init(ahci_init);
1266module_exit(ahci_exit);
Linux kernel - Deliverables
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