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Fix ahci driver 'flags' type
[deliverable/linux.git] / drivers / ata / ahci.c
CommitLineData
1da177e4
LT		 1/*
2 * ahci.c - AHCI SATA support
3 *
af36d7f0
JG		 4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
7 *
8 * Copyright 2004-2005 Red Hat, Inc.
9 *
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
24 *
25 *
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
28 *
29 * AHCI hardware documentation:
1da177e4 30 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
af36d7f0 31 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
1da177e4
LT		 32 *
33 */
34
35#include <linux/kernel.h>
36#include <linux/module.h>
37#include <linux/pci.h>
38#include <linux/init.h>
39#include <linux/blkdev.h>
40#include <linux/delay.h>
41#include <linux/interrupt.h>
87507cfd 42#include <linux/dma-mapping.h>
a9524a76 43#include <linux/device.h>
edc93052 44#include <linux/dmi.h>
1da177e4 45#include <scsi/scsi_host.h>
193515d5 46#include <scsi/scsi_cmnd.h>
1da177e4 47#include <linux/libata.h>
1da177e4
LT		 48
49#define DRV_NAME "ahci"
7d50b60b 50#define DRV_VERSION "3.0"
1da177e4 51
a22e6444
TH		 52static int ahci_skip_host_reset;
53module_param_named(skip_host_reset, ahci_skip_host_reset, int, 0444);
54MODULE_PARM_DESC(skip_host_reset, "skip global host reset (0=don't skip, 1=skip)");
55
31556594
KCA		 56static int ahci_enable_alpm(struct ata_port *ap,
57 enum link_pm policy);
58static void ahci_disable_alpm(struct ata_port *ap);
18f7ba4c
KCA		 59static ssize_t ahci_led_show(struct ata_port *ap, char *buf);
60static ssize_t ahci_led_store(struct ata_port *ap, const char *buf,
61 size_t size);
62static ssize_t ahci_transmit_led_message(struct ata_port *ap, u32 state,
63 ssize_t size);
64#define MAX_SLOTS 8
1da177e4
LT		 65
66enum {
67 AHCI_PCI_BAR = 5,
648a88be 68 AHCI_MAX_PORTS = 32,
1da177e4
LT		 69 AHCI_MAX_SG = 168, /* hardware max is 64K */
70 AHCI_DMA_BOUNDARY = 0xffffffff,
12fad3f9 71 AHCI_MAX_CMDS = 32,
dd410ff1 72 AHCI_CMD_SZ = 32,
12fad3f9 73 AHCI_CMD_SLOT_SZ = AHCI_MAX_CMDS * AHCI_CMD_SZ,
1da177e4 74 AHCI_RX_FIS_SZ = 256,
a0ea7328 75 AHCI_CMD_TBL_CDB = 0x40,
dd410ff1
TH		 76 AHCI_CMD_TBL_HDR_SZ = 0x80,
77 AHCI_CMD_TBL_SZ = AHCI_CMD_TBL_HDR_SZ + (AHCI_MAX_SG * 16),
78 AHCI_CMD_TBL_AR_SZ = AHCI_CMD_TBL_SZ * AHCI_MAX_CMDS,
79 AHCI_PORT_PRIV_DMA_SZ = AHCI_CMD_SLOT_SZ + AHCI_CMD_TBL_AR_SZ +
1da177e4
LT		 80 AHCI_RX_FIS_SZ,
81 AHCI_IRQ_ON_SG = (1 << 31),
82 AHCI_CMD_ATAPI = (1 << 5),
83 AHCI_CMD_WRITE = (1 << 6),
4b10e559 84 AHCI_CMD_PREFETCH = (1 << 7),
22b49985
TH		 85 AHCI_CMD_RESET = (1 << 8),
86 AHCI_CMD_CLR_BUSY = (1 << 10),
1da177e4
LT		 87
88 RX_FIS_D2H_REG = 0x40, /* offset of D2H Register FIS data */
0291f95f 89 RX_FIS_SDB = 0x58, /* offset of SDB FIS data */
78cd52d0 90 RX_FIS_UNK = 0x60, /* offset of Unknown FIS data */
1da177e4
LT		 91
92 board_ahci = 0,
7a234aff
TH		 93 board_ahci_vt8251 = 1,
94 board_ahci_ign_iferr = 2,
95 board_ahci_sb600 = 3,
96 board_ahci_mv = 4,
e39fc8c9 97 board_ahci_sb700 = 5,
e297d99e 98 board_ahci_mcp65 = 6,
9a3b103c 99 board_ahci_nopmp = 7,
1da177e4
LT		 100
101 /* global controller registers */
102 HOST_CAP = 0x00, /* host capabilities */
103 HOST_CTL = 0x04, /* global host control */
104 HOST_IRQ_STAT = 0x08, /* interrupt status */
105 HOST_PORTS_IMPL = 0x0c, /* bitmap of implemented ports */
106 HOST_VERSION = 0x10, /* AHCI spec. version compliancy */
18f7ba4c
KCA		 107 HOST_EM_LOC = 0x1c, /* Enclosure Management location */
108 HOST_EM_CTL = 0x20, /* Enclosure Management Control */
1da177e4
LT		 109
110 /* HOST_CTL bits */
111 HOST_RESET = (1 << 0), /* reset controller; self-clear */
112 HOST_IRQ_EN = (1 << 1), /* global IRQ enable */
113 HOST_AHCI_EN = (1 << 31), /* AHCI enabled */
114
115 /* HOST_CAP bits */
18f7ba4c 116 HOST_CAP_EMS = (1 << 6), /* Enclosure Management support */
0be0aa98 117 HOST_CAP_SSC = (1 << 14), /* Slumber capable */
7d50b60b 118 HOST_CAP_PMP = (1 << 17), /* Port Multiplier support */
22b49985 119 HOST_CAP_CLO = (1 << 24), /* Command List Override support */
31556594 120 HOST_CAP_ALPM = (1 << 26), /* Aggressive Link PM support */
0be0aa98 121 HOST_CAP_SSS = (1 << 27), /* Staggered Spin-up */
203ef6c4 122 HOST_CAP_SNTF = (1 << 29), /* SNotification register */
979db803 123 HOST_CAP_NCQ = (1 << 30), /* Native Command Queueing */
dd410ff1 124 HOST_CAP_64 = (1 << 31), /* PCI DAC (64-bit DMA) support */
1da177e4
LT		 125
126 /* registers for each SATA port */
127 PORT_LST_ADDR = 0x00, /* command list DMA addr */
128 PORT_LST_ADDR_HI = 0x04, /* command list DMA addr hi */
129 PORT_FIS_ADDR = 0x08, /* FIS rx buf addr */
130 PORT_FIS_ADDR_HI = 0x0c, /* FIS rx buf addr hi */
131 PORT_IRQ_STAT = 0x10, /* interrupt status */
132 PORT_IRQ_MASK = 0x14, /* interrupt enable/disable mask */
133 PORT_CMD = 0x18, /* port command */
134 PORT_TFDATA = 0x20, /* taskfile data */
135 PORT_SIG = 0x24, /* device TF signature */
136 PORT_CMD_ISSUE = 0x38, /* command issue */
1da177e4
LT		 137 PORT_SCR_STAT = 0x28, /* SATA phy register: SStatus */
138 PORT_SCR_CTL = 0x2c, /* SATA phy register: SControl */
139 PORT_SCR_ERR = 0x30, /* SATA phy register: SError */
140 PORT_SCR_ACT = 0x34, /* SATA phy register: SActive */
203ef6c4 141 PORT_SCR_NTF = 0x3c, /* SATA phy register: SNotification */
1da177e4
LT		 142
143 /* PORT_IRQ_{STAT,MASK} bits */
144 PORT_IRQ_COLD_PRES = (1 << 31), /* cold presence detect */
145 PORT_IRQ_TF_ERR = (1 << 30), /* task file error */
146 PORT_IRQ_HBUS_ERR = (1 << 29), /* host bus fatal error */
147 PORT_IRQ_HBUS_DATA_ERR = (1 << 28), /* host bus data error */
148 PORT_IRQ_IF_ERR = (1 << 27), /* interface fatal error */
149 PORT_IRQ_IF_NONFATAL = (1 << 26), /* interface non-fatal error */
150 PORT_IRQ_OVERFLOW = (1 << 24), /* xfer exhausted available S/G */
151 PORT_IRQ_BAD_PMP = (1 << 23), /* incorrect port multiplier */
152
153 PORT_IRQ_PHYRDY = (1 << 22), /* PhyRdy changed */
154 PORT_IRQ_DEV_ILCK = (1 << 7), /* device interlock */
155 PORT_IRQ_CONNECT = (1 << 6), /* port connect change status */
156 PORT_IRQ_SG_DONE = (1 << 5), /* descriptor processed */
157 PORT_IRQ_UNK_FIS = (1 << 4), /* unknown FIS rx'd */
158 PORT_IRQ_SDB_FIS = (1 << 3), /* Set Device Bits FIS rx'd */
159 PORT_IRQ_DMAS_FIS = (1 << 2), /* DMA Setup FIS rx'd */
160 PORT_IRQ_PIOS_FIS = (1 << 1), /* PIO Setup FIS rx'd */
161 PORT_IRQ_D2H_REG_FIS = (1 << 0), /* D2H Register FIS rx'd */
162
78cd52d0
TH		 163 PORT_IRQ_FREEZE = PORT_IRQ_HBUS_ERR |
164 PORT_IRQ_IF_ERR |
165 PORT_IRQ_CONNECT |
4296971d 166 PORT_IRQ_PHYRDY |
7d50b60b
TH		 167 PORT_IRQ_UNK_FIS |
168 PORT_IRQ_BAD_PMP,
78cd52d0
TH		 169 PORT_IRQ_ERROR = PORT_IRQ_FREEZE |
170 PORT_IRQ_TF_ERR |
171 PORT_IRQ_HBUS_DATA_ERR,
172 DEF_PORT_IRQ = PORT_IRQ_ERROR | PORT_IRQ_SG_DONE |
173 PORT_IRQ_SDB_FIS | PORT_IRQ_DMAS_FIS |
174 PORT_IRQ_PIOS_FIS | PORT_IRQ_D2H_REG_FIS,
1da177e4
LT		 175
176 /* PORT_CMD bits */
31556594
KCA		 177 PORT_CMD_ASP = (1 << 27), /* Aggressive Slumber/Partial */
178 PORT_CMD_ALPE = (1 << 26), /* Aggressive Link PM enable */
02eaa666 179 PORT_CMD_ATAPI = (1 << 24), /* Device is ATAPI */
7d50b60b 180 PORT_CMD_PMP = (1 << 17), /* PMP attached */
1da177e4
LT		 181 PORT_CMD_LIST_ON = (1 << 15), /* cmd list DMA engine running */
182 PORT_CMD_FIS_ON = (1 << 14), /* FIS DMA engine running */
183 PORT_CMD_FIS_RX = (1 << 4), /* Enable FIS receive DMA engine */
22b49985 184 PORT_CMD_CLO = (1 << 3), /* Command list override */
1da177e4
LT		 185 PORT_CMD_POWER_ON = (1 << 2), /* Power up device */
186 PORT_CMD_SPIN_UP = (1 << 1), /* Spin up device */
187 PORT_CMD_START = (1 << 0), /* Enable port DMA engine */
188
0be0aa98 189 PORT_CMD_ICC_MASK = (0xf << 28), /* i/f ICC state mask */
1da177e4
LT		 190 PORT_CMD_ICC_ACTIVE = (0x1 << 28), /* Put i/f in active state */
191 PORT_CMD_ICC_PARTIAL = (0x2 << 28), /* Put i/f in partial state */
192 PORT_CMD_ICC_SLUMBER = (0x6 << 28), /* Put i/f in slumber state */
4b0060f4 193
417a1a6d
TH		 194 /* hpriv->flags bits */
195 AHCI_HFLAG_NO_NCQ = (1 << 0),
196 AHCI_HFLAG_IGN_IRQ_IF_ERR = (1 << 1), /* ignore IRQ_IF_ERR */
197 AHCI_HFLAG_IGN_SERR_INTERNAL = (1 << 2), /* ignore SERR_INTERNAL */
198 AHCI_HFLAG_32BIT_ONLY = (1 << 3), /* force 32bit */
199 AHCI_HFLAG_MV_PATA = (1 << 4), /* PATA port */
200 AHCI_HFLAG_NO_MSI = (1 << 5), /* no PCI MSI */
6949b914 201 AHCI_HFLAG_NO_PMP = (1 << 6), /* no PMP */
31556594 202 AHCI_HFLAG_NO_HOTPLUG = (1 << 7), /* ignore PxSERR.DIAG.N */
a878539e 203 AHCI_HFLAG_SECT255 = (1 << 8), /* max 255 sectors */
e297d99e 204 AHCI_HFLAG_YES_NCQ = (1 << 9), /* force NCQ cap on */
417a1a6d 205
bf2af2a2 206 /* ap->flags bits */
1188c0d8
TH		 207
208 AHCI_FLAG_COMMON = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
209 ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA |
31556594
KCA		 210 ATA_FLAG_ACPI_SATA | ATA_FLAG_AN |
211 ATA_FLAG_IPM,
c4f7792c
TH		 212
213 ICH_MAP = 0x90, /* ICH MAP register */
18f7ba4c
KCA		 214
215 /* em_ctl bits */
216 EM_CTL_RST = (1 << 9), /* Reset */
217 EM_CTL_TM = (1 << 8), /* Transmit Message */
218 EM_CTL_ALHD = (1 << 26), /* Activity LED */
1da177e4
LT		 219};
220
221struct ahci_cmd_hdr {
4ca4e439
AV		 222 __le32 opts;
223 __le32 status;
224 __le32 tbl_addr;
225 __le32 tbl_addr_hi;
226 __le32 reserved[4];
1da177e4
LT		 227};
228
229struct ahci_sg {
4ca4e439
AV		 230 __le32 addr;
231 __le32 addr_hi;
232 __le32 reserved;
233 __le32 flags_size;
1da177e4
LT		 234};
235
18f7ba4c
KCA		 236struct ahci_em_priv {
237 enum sw_activity blink_policy;
238 struct timer_list timer;
239 unsigned long saved_activity;
240 unsigned long activity;
241 unsigned long led_state;
242};
243
1da177e4 244struct ahci_host_priv {
417a1a6d 245 unsigned int flags; /* AHCI_HFLAG_* */
d447df14
TH		 246 u32 cap; /* cap to use */
247 u32 port_map; /* port map to use */
248 u32 saved_cap; /* saved initial cap */
249 u32 saved_port_map; /* saved initial port_map */
18f7ba4c 250 u32 em_loc; /* enclosure management location */
1da177e4
LT		 251};
252
253struct ahci_port_priv {
7d50b60b 254 struct ata_link *active_link;
1da177e4
LT		 255 struct ahci_cmd_hdr *cmd_slot;
256 dma_addr_t cmd_slot_dma;
257 void *cmd_tbl;
258 dma_addr_t cmd_tbl_dma;
1da177e4
LT		 259 void *rx_fis;
260 dma_addr_t rx_fis_dma;
0291f95f 261 /* for NCQ spurious interrupt analysis */
0291f95f
TH		 262 unsigned int ncq_saw_d2h:1;
263 unsigned int ncq_saw_dmas:1;
afb2d552 264 unsigned int ncq_saw_sdb:1;
a7384925 265 u32 intr_mask; /* interrupts to enable */
18f7ba4c
KCA		 266 struct ahci_em_priv em_priv[MAX_SLOTS];/* enclosure management info
267 * per PM slot */
1da177e4
LT		 268};
269
da3dbb17
TH		 270static int ahci_scr_read(struct ata_port *ap, unsigned int sc_reg, u32 *val);
271static int ahci_scr_write(struct ata_port *ap, unsigned int sc_reg, u32 val);
2dcb407e 272static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
9a3d9eb0 273static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc);
4c9bf4e7 274static bool ahci_qc_fill_rtf(struct ata_queued_cmd *qc);
1da177e4
LT		 275static int ahci_port_start(struct ata_port *ap);
276static void ahci_port_stop(struct ata_port *ap);
1da177e4 277static void ahci_qc_prep(struct ata_queued_cmd *qc);
78cd52d0
TH		 278static void ahci_freeze(struct ata_port *ap);
279static void ahci_thaw(struct ata_port *ap);
7d50b60b
TH		 280static void ahci_pmp_attach(struct ata_port *ap);
281static void ahci_pmp_detach(struct ata_port *ap);
a1efdaba
TH		 282static int ahci_softreset(struct ata_link *link, unsigned int *class,
283 unsigned long deadline);
bd17243a
SH		 284static int ahci_sb600_softreset(struct ata_link *link, unsigned int *class,
285 unsigned long deadline);
a1efdaba
TH		 286static int ahci_hardreset(struct ata_link *link, unsigned int *class,
287 unsigned long deadline);
288static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
289 unsigned long deadline);
290static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
291 unsigned long deadline);
292static void ahci_postreset(struct ata_link *link, unsigned int *class);
78cd52d0
TH		 293static void ahci_error_handler(struct ata_port *ap);
294static void ahci_post_internal_cmd(struct ata_queued_cmd *qc);
df69c9c5 295static int ahci_port_resume(struct ata_port *ap);
a878539e 296static void ahci_dev_config(struct ata_device *dev);
dab632e8
JG		 297static unsigned int ahci_fill_sg(struct ata_queued_cmd *qc, void *cmd_tbl);
298static void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag,
299 u32 opts);
438ac6d5 300#ifdef CONFIG_PM
c1332875 301static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg);
c1332875
TH		 302static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg);
303static int ahci_pci_device_resume(struct pci_dev *pdev);
438ac6d5 304#endif
18f7ba4c
KCA		 305static ssize_t ahci_activity_show(struct ata_device *dev, char *buf);
306static ssize_t ahci_activity_store(struct ata_device *dev,
307 enum sw_activity val);
308static void ahci_init_sw_activity(struct ata_link *link);
1da177e4 309
ee959b00
TJ		 310static struct device_attribute *ahci_shost_attrs[] = {
311 &dev_attr_link_power_management_policy,
18f7ba4c
KCA		 312 &dev_attr_em_message_type,
313 &dev_attr_em_message,
314 NULL
315};
316
317static struct device_attribute *ahci_sdev_attrs[] = {
318 &dev_attr_sw_activity,
31556594
KCA		 319 NULL
320};
321
193515d5 322static struct scsi_host_template ahci_sht = {
68d1d07b 323 ATA_NCQ_SHT(DRV_NAME),
12fad3f9 324 .can_queue = AHCI_MAX_CMDS - 1,
1da177e4 325 .sg_tablesize = AHCI_MAX_SG,
1da177e4 326 .dma_boundary = AHCI_DMA_BOUNDARY,
31556594 327 .shost_attrs = ahci_shost_attrs,
18f7ba4c 328 .sdev_attrs = ahci_sdev_attrs,
1da177e4
LT		 329};
330
029cfd6b
TH		 331static struct ata_port_operations ahci_ops = {
332 .inherits = &sata_pmp_port_ops,
333
7d50b60b 334 .qc_defer = sata_pmp_qc_defer_cmd_switch,
1da177e4
LT		 335 .qc_prep = ahci_qc_prep,
336 .qc_issue = ahci_qc_issue,
4c9bf4e7 337 .qc_fill_rtf = ahci_qc_fill_rtf,
1da177e4 338
78cd52d0
TH		 339 .freeze = ahci_freeze,
340 .thaw = ahci_thaw,
a1efdaba
TH		 341 .softreset = ahci_softreset,
342 .hardreset = ahci_hardreset,
343 .postreset = ahci_postreset,
071f44b1 344 .pmp_softreset = ahci_softreset,
78cd52d0
TH		 345 .error_handler = ahci_error_handler,
346 .post_internal_cmd = ahci_post_internal_cmd,
6bd99b4e
TH		 347 .dev_config = ahci_dev_config,
348
ad616ffb
TH		 349 .scr_read = ahci_scr_read,
350 .scr_write = ahci_scr_write,
7d50b60b
TH		 351 .pmp_attach = ahci_pmp_attach,
352 .pmp_detach = ahci_pmp_detach,
7d50b60b 353
029cfd6b
TH		 354 .enable_pm = ahci_enable_alpm,
355 .disable_pm = ahci_disable_alpm,
18f7ba4c
KCA		 356 .em_show = ahci_led_show,
357 .em_store = ahci_led_store,
358 .sw_activity_show = ahci_activity_show,
359 .sw_activity_store = ahci_activity_store,
438ac6d5 360#ifdef CONFIG_PM
ad616ffb
TH		 361 .port_suspend = ahci_port_suspend,
362 .port_resume = ahci_port_resume,
438ac6d5 363#endif
ad616ffb
TH		 364 .port_start = ahci_port_start,
365 .port_stop = ahci_port_stop,
366};
367
029cfd6b
TH		 368static struct ata_port_operations ahci_vt8251_ops = {
369 .inherits = &ahci_ops,
a1efdaba 370 .hardreset = ahci_vt8251_hardreset,
029cfd6b 371};
edc93052 372
029cfd6b
TH		 373static struct ata_port_operations ahci_p5wdh_ops = {
374 .inherits = &ahci_ops,
a1efdaba 375 .hardreset = ahci_p5wdh_hardreset,
edc93052
TH		 376};
377
bd17243a
SH		 378static struct ata_port_operations ahci_sb600_ops = {
379 .inherits = &ahci_ops,
380 .softreset = ahci_sb600_softreset,
381 .pmp_softreset = ahci_sb600_softreset,
382};
383
417a1a6d
TH		 384#define AHCI_HFLAGS(flags) .private_data = (void *)(flags)
385
98ac62de 386static const struct ata_port_info ahci_port_info[] = {
1da177e4
LT		 387 /* board_ahci */
388 {
1188c0d8 389 .flags = AHCI_FLAG_COMMON,
7da79312 390 .pio_mask = 0x1f, /* pio0-4 */
469248ab 391 .udma_mask = ATA_UDMA6,
1da177e4
LT		 392 .port_ops = &ahci_ops,
393 },
bf2af2a2
BJ		 394 /* board_ahci_vt8251 */
395 {
6949b914 396 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_PMP),
417a1a6d 397 .flags = AHCI_FLAG_COMMON,
bf2af2a2 398 .pio_mask = 0x1f, /* pio0-4 */
469248ab 399 .udma_mask = ATA_UDMA6,
ad616ffb 400 .port_ops = &ahci_vt8251_ops,
bf2af2a2 401 },
41669553
TH		 402 /* board_ahci_ign_iferr */
403 {
417a1a6d
TH		 404 AHCI_HFLAGS (AHCI_HFLAG_IGN_IRQ_IF_ERR),
405 .flags = AHCI_FLAG_COMMON,
41669553 406 .pio_mask = 0x1f, /* pio0-4 */
469248ab 407 .udma_mask = ATA_UDMA6,
41669553
TH		 408 .port_ops = &ahci_ops,
409 },
55a61604
CH		 410 /* board_ahci_sb600 */
411 {
417a1a6d 412 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL |
22b5e7a7 413 AHCI_HFLAG_32BIT_ONLY | AHCI_HFLAG_NO_MSI |
bd17243a 414 AHCI_HFLAG_SECT255),
417a1a6d 415 .flags = AHCI_FLAG_COMMON,
55a61604 416 .pio_mask = 0x1f, /* pio0-4 */
469248ab 417 .udma_mask = ATA_UDMA6,
bd17243a 418 .port_ops = &ahci_sb600_ops,
55a61604 419 },
cd70c266
JG		 420 /* board_ahci_mv */
421 {
417a1a6d
TH		 422 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_MSI |
423 AHCI_HFLAG_MV_PATA),
cd70c266 424 .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
417a1a6d 425 ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA,
cd70c266
JG		 426 .pio_mask = 0x1f, /* pio0-4 */
427 .udma_mask = ATA_UDMA6,
428 .port_ops = &ahci_ops,
429 },
e39fc8c9
SH		 430 /* board_ahci_sb700 */
431 {
bd17243a 432 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL),
e39fc8c9 433 .flags = AHCI_FLAG_COMMON,
e39fc8c9
SH		 434 .pio_mask = 0x1f, /* pio0-4 */
435 .udma_mask = ATA_UDMA6,
bd17243a 436 .port_ops = &ahci_sb600_ops,
e39fc8c9 437 },
e297d99e
TH		 438 /* board_ahci_mcp65 */
439 {
440 AHCI_HFLAGS (AHCI_HFLAG_YES_NCQ),
441 .flags = AHCI_FLAG_COMMON,
442 .pio_mask = 0x1f, /* pio0-4 */
443 .udma_mask = ATA_UDMA6,
444 .port_ops = &ahci_ops,
445 },
9a3b103c
TH		 446 /* board_ahci_nopmp */
447 {
448 AHCI_HFLAGS (AHCI_HFLAG_NO_PMP),
449 .flags = AHCI_FLAG_COMMON,
450 .pio_mask = 0x1f, /* pio0-4 */
451 .udma_mask = ATA_UDMA6,
452 .port_ops = &ahci_ops,
453 },
1da177e4
LT		 454};
455
3b7d697d 456static const struct pci_device_id ahci_pci_tbl[] = {
fe7fa31a 457 /* Intel */
54bb3a94
JG		 458 { PCI_VDEVICE(INTEL, 0x2652), board_ahci }, /* ICH6 */
459 { PCI_VDEVICE(INTEL, 0x2653), board_ahci }, /* ICH6M */
460 { PCI_VDEVICE(INTEL, 0x27c1), board_ahci }, /* ICH7 */
461 { PCI_VDEVICE(INTEL, 0x27c5), board_ahci }, /* ICH7M */
462 { PCI_VDEVICE(INTEL, 0x27c3), board_ahci }, /* ICH7R */
82490c09 463 { PCI_VDEVICE(AL, 0x5288), board_ahci_ign_iferr }, /* ULi M5288 */
54bb3a94
JG		 464 { PCI_VDEVICE(INTEL, 0x2681), board_ahci }, /* ESB2 */
465 { PCI_VDEVICE(INTEL, 0x2682), board_ahci }, /* ESB2 */
466 { PCI_VDEVICE(INTEL, 0x2683), board_ahci }, /* ESB2 */
467 { PCI_VDEVICE(INTEL, 0x27c6), board_ahci }, /* ICH7-M DH */
7a234aff
TH		 468 { PCI_VDEVICE(INTEL, 0x2821), board_ahci }, /* ICH8 */
469 { PCI_VDEVICE(INTEL, 0x2822), board_ahci }, /* ICH8 */
470 { PCI_VDEVICE(INTEL, 0x2824), board_ahci }, /* ICH8 */
471 { PCI_VDEVICE(INTEL, 0x2829), board_ahci }, /* ICH8M */
472 { PCI_VDEVICE(INTEL, 0x282a), board_ahci }, /* ICH8M */
473 { PCI_VDEVICE(INTEL, 0x2922), board_ahci }, /* ICH9 */
474 { PCI_VDEVICE(INTEL, 0x2923), board_ahci }, /* ICH9 */
475 { PCI_VDEVICE(INTEL, 0x2924), board_ahci }, /* ICH9 */
476 { PCI_VDEVICE(INTEL, 0x2925), board_ahci }, /* ICH9 */
477 { PCI_VDEVICE(INTEL, 0x2927), board_ahci }, /* ICH9 */
478 { PCI_VDEVICE(INTEL, 0x2929), board_ahci }, /* ICH9M */
479 { PCI_VDEVICE(INTEL, 0x292a), board_ahci }, /* ICH9M */
480 { PCI_VDEVICE(INTEL, 0x292b), board_ahci }, /* ICH9M */
481 { PCI_VDEVICE(INTEL, 0x292c), board_ahci }, /* ICH9M */
482 { PCI_VDEVICE(INTEL, 0x292f), board_ahci }, /* ICH9M */
483 { PCI_VDEVICE(INTEL, 0x294d), board_ahci }, /* ICH9 */
484 { PCI_VDEVICE(INTEL, 0x294e), board_ahci }, /* ICH9M */
d4155e6f
JG		 485 { PCI_VDEVICE(INTEL, 0x502a), board_ahci }, /* Tolapai */
486 { PCI_VDEVICE(INTEL, 0x502b), board_ahci }, /* Tolapai */
16ad1ad9
JG		 487 { PCI_VDEVICE(INTEL, 0x3a05), board_ahci }, /* ICH10 */
488 { PCI_VDEVICE(INTEL, 0x3a25), board_ahci }, /* ICH10 */
fe7fa31a 489
e34bb370
TH		 490 /* JMicron 360/1/3/5/6, match class to avoid IDE function */
491 { PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
492 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci_ign_iferr },
fe7fa31a
JG		 493
494 /* ATI */
c65ec1c2 495 { PCI_VDEVICE(ATI, 0x4380), board_ahci_sb600 }, /* ATI SB600 */
e39fc8c9
SH		 496 { PCI_VDEVICE(ATI, 0x4390), board_ahci_sb700 }, /* ATI SB700/800 */
497 { PCI_VDEVICE(ATI, 0x4391), board_ahci_sb700 }, /* ATI SB700/800 */
498 { PCI_VDEVICE(ATI, 0x4392), board_ahci_sb700 }, /* ATI SB700/800 */
499 { PCI_VDEVICE(ATI, 0x4393), board_ahci_sb700 }, /* ATI SB700/800 */
500 { PCI_VDEVICE(ATI, 0x4394), board_ahci_sb700 }, /* ATI SB700/800 */
501 { PCI_VDEVICE(ATI, 0x4395), board_ahci_sb700 }, /* ATI SB700/800 */
fe7fa31a
JG		 502
503 /* VIA */
54bb3a94 504 { PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251 }, /* VIA VT8251 */
bf335542 505 { PCI_VDEVICE(VIA, 0x6287), board_ahci_vt8251 }, /* VIA VT8251 */
fe7fa31a
JG		 506
507 /* NVIDIA */
e297d99e
TH		 508 { PCI_VDEVICE(NVIDIA, 0x044c), board_ahci_mcp65 }, /* MCP65 */
509 { PCI_VDEVICE(NVIDIA, 0x044d), board_ahci_mcp65 }, /* MCP65 */
510 { PCI_VDEVICE(NVIDIA, 0x044e), board_ahci_mcp65 }, /* MCP65 */
511 { PCI_VDEVICE(NVIDIA, 0x044f), board_ahci_mcp65 }, /* MCP65 */
512 { PCI_VDEVICE(NVIDIA, 0x045c), board_ahci_mcp65 }, /* MCP65 */
513 { PCI_VDEVICE(NVIDIA, 0x045d), board_ahci_mcp65 }, /* MCP65 */
514 { PCI_VDEVICE(NVIDIA, 0x045e), board_ahci_mcp65 }, /* MCP65 */
515 { PCI_VDEVICE(NVIDIA, 0x045f), board_ahci_mcp65 }, /* MCP65 */
6fbf5ba4
PC		 516 { PCI_VDEVICE(NVIDIA, 0x0550), board_ahci }, /* MCP67 */
517 { PCI_VDEVICE(NVIDIA, 0x0551), board_ahci }, /* MCP67 */
518 { PCI_VDEVICE(NVIDIA, 0x0552), board_ahci }, /* MCP67 */
519 { PCI_VDEVICE(NVIDIA, 0x0553), board_ahci }, /* MCP67 */
895663cd
PC		 520 { PCI_VDEVICE(NVIDIA, 0x0554), board_ahci }, /* MCP67 */
521 { PCI_VDEVICE(NVIDIA, 0x0555), board_ahci }, /* MCP67 */
522 { PCI_VDEVICE(NVIDIA, 0x0556), board_ahci }, /* MCP67 */
523 { PCI_VDEVICE(NVIDIA, 0x0557), board_ahci }, /* MCP67 */
524 { PCI_VDEVICE(NVIDIA, 0x0558), board_ahci }, /* MCP67 */
525 { PCI_VDEVICE(NVIDIA, 0x0559), board_ahci }, /* MCP67 */
526 { PCI_VDEVICE(NVIDIA, 0x055a), board_ahci }, /* MCP67 */
527 { PCI_VDEVICE(NVIDIA, 0x055b), board_ahci }, /* MCP67 */
0522b286
PC		 528 { PCI_VDEVICE(NVIDIA, 0x07f0), board_ahci }, /* MCP73 */
529 { PCI_VDEVICE(NVIDIA, 0x07f1), board_ahci }, /* MCP73 */
530 { PCI_VDEVICE(NVIDIA, 0x07f2), board_ahci }, /* MCP73 */
531 { PCI_VDEVICE(NVIDIA, 0x07f3), board_ahci }, /* MCP73 */
532 { PCI_VDEVICE(NVIDIA, 0x07f4), board_ahci }, /* MCP73 */
533 { PCI_VDEVICE(NVIDIA, 0x07f5), board_ahci }, /* MCP73 */
534 { PCI_VDEVICE(NVIDIA, 0x07f6), board_ahci }, /* MCP73 */
535 { PCI_VDEVICE(NVIDIA, 0x07f7), board_ahci }, /* MCP73 */
536 { PCI_VDEVICE(NVIDIA, 0x07f8), board_ahci }, /* MCP73 */
537 { PCI_VDEVICE(NVIDIA, 0x07f9), board_ahci }, /* MCP73 */
538 { PCI_VDEVICE(NVIDIA, 0x07fa), board_ahci }, /* MCP73 */
539 { PCI_VDEVICE(NVIDIA, 0x07fb), board_ahci }, /* MCP73 */
540 { PCI_VDEVICE(NVIDIA, 0x0ad0), board_ahci }, /* MCP77 */
541 { PCI_VDEVICE(NVIDIA, 0x0ad1), board_ahci }, /* MCP77 */
542 { PCI_VDEVICE(NVIDIA, 0x0ad2), board_ahci }, /* MCP77 */
543 { PCI_VDEVICE(NVIDIA, 0x0ad3), board_ahci }, /* MCP77 */
544 { PCI_VDEVICE(NVIDIA, 0x0ad4), board_ahci }, /* MCP77 */
545 { PCI_VDEVICE(NVIDIA, 0x0ad5), board_ahci }, /* MCP77 */
546 { PCI_VDEVICE(NVIDIA, 0x0ad6), board_ahci }, /* MCP77 */
547 { PCI_VDEVICE(NVIDIA, 0x0ad7), board_ahci }, /* MCP77 */
548 { PCI_VDEVICE(NVIDIA, 0x0ad8), board_ahci }, /* MCP77 */
549 { PCI_VDEVICE(NVIDIA, 0x0ad9), board_ahci }, /* MCP77 */
550 { PCI_VDEVICE(NVIDIA, 0x0ada), board_ahci }, /* MCP77 */
551 { PCI_VDEVICE(NVIDIA, 0x0adb), board_ahci }, /* MCP77 */
6ba86958 552 { PCI_VDEVICE(NVIDIA, 0x0ab4), board_ahci }, /* MCP79 */
553 { PCI_VDEVICE(NVIDIA, 0x0ab5), board_ahci }, /* MCP79 */
554 { PCI_VDEVICE(NVIDIA, 0x0ab6), board_ahci }, /* MCP79 */
555 { PCI_VDEVICE(NVIDIA, 0x0ab7), board_ahci }, /* MCP79 */
7100819f
PC		 556 { PCI_VDEVICE(NVIDIA, 0x0ab8), board_ahci }, /* MCP79 */
557 { PCI_VDEVICE(NVIDIA, 0x0ab9), board_ahci }, /* MCP79 */
558 { PCI_VDEVICE(NVIDIA, 0x0aba), board_ahci }, /* MCP79 */
559 { PCI_VDEVICE(NVIDIA, 0x0abb), board_ahci }, /* MCP79 */
560 { PCI_VDEVICE(NVIDIA, 0x0abc), board_ahci }, /* MCP79 */
561 { PCI_VDEVICE(NVIDIA, 0x0abd), board_ahci }, /* MCP79 */
562 { PCI_VDEVICE(NVIDIA, 0x0abe), board_ahci }, /* MCP79 */
563 { PCI_VDEVICE(NVIDIA, 0x0abf), board_ahci }, /* MCP79 */
70d562cf 564 { PCI_VDEVICE(NVIDIA, 0x0bc8), board_ahci }, /* MCP7B */
565 { PCI_VDEVICE(NVIDIA, 0x0bc9), board_ahci }, /* MCP7B */
566 { PCI_VDEVICE(NVIDIA, 0x0bca), board_ahci }, /* MCP7B */
567 { PCI_VDEVICE(NVIDIA, 0x0bcb), board_ahci }, /* MCP7B */
568 { PCI_VDEVICE(NVIDIA, 0x0bcc), board_ahci }, /* MCP7B */
569 { PCI_VDEVICE(NVIDIA, 0x0bcd), board_ahci }, /* MCP7B */
570 { PCI_VDEVICE(NVIDIA, 0x0bce), board_ahci }, /* MCP7B */
571 { PCI_VDEVICE(NVIDIA, 0x0bcf), board_ahci }, /* MCP7B */
3072c379 572 { PCI_VDEVICE(NVIDIA, 0x0bc4), board_ahci }, /* MCP7B */
573 { PCI_VDEVICE(NVIDIA, 0x0bc5), board_ahci }, /* MCP7B */
574 { PCI_VDEVICE(NVIDIA, 0x0bc6), board_ahci }, /* MCP7B */
575 { PCI_VDEVICE(NVIDIA, 0x0bc7), board_ahci }, /* MCP7B */
fe7fa31a 576
95916edd 577 /* SiS */
9a3b103c
TH		 578 { PCI_VDEVICE(SI, 0x1184), board_ahci_nopmp }, /* SiS 966 */
579 { PCI_VDEVICE(SI, 0x1185), board_ahci_nopmp }, /* SiS 968 */
580 { PCI_VDEVICE(SI, 0x0186), board_ahci_nopmp }, /* SiS 968 */
95916edd 581
cd70c266
JG		 582 /* Marvell */
583 { PCI_VDEVICE(MARVELL, 0x6145), board_ahci_mv }, /* 6145 */
c40e7cb8 584 { PCI_VDEVICE(MARVELL, 0x6121), board_ahci_mv }, /* 6121 */
cd70c266 585
415ae2b5
JG		 586 /* Generic, PCI class code for AHCI */
587 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
c9f89475 588 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci },
415ae2b5 589
1da177e4
LT		 590 { } /* terminate list */
591};
592
593
594static struct pci_driver ahci_pci_driver = {
595 .name = DRV_NAME,
596 .id_table = ahci_pci_tbl,
597 .probe = ahci_init_one,
24dc5f33 598 .remove = ata_pci_remove_one,
438ac6d5 599#ifdef CONFIG_PM
c1332875
TH		 600 .suspend = ahci_pci_device_suspend,
601 .resume = ahci_pci_device_resume,
438ac6d5 602#endif
1da177e4
LT		 603};
604
18f7ba4c
KCA		 605static int ahci_em_messages = 1;
606module_param(ahci_em_messages, int, 0444);
607/* add other LED protocol types when they become supported */
608MODULE_PARM_DESC(ahci_em_messages,
609 "Set AHCI Enclosure Management Message type (0 = disabled, 1 = LED");
1da177e4 610
98fa4b60
TH		 611static inline int ahci_nr_ports(u32 cap)
612{
613 return (cap & 0x1f) + 1;
614}
615
dab632e8
JG		 616static inline void __iomem *__ahci_port_base(struct ata_host *host,
617 unsigned int port_no)
1da177e4 618{
dab632e8 619 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
4447d351 620
dab632e8
JG		 621 return mmio + 0x100 + (port_no * 0x80);
622}
623
624static inline void __iomem *ahci_port_base(struct ata_port *ap)
625{
626 return __ahci_port_base(ap->host, ap->port_no);
1da177e4
LT		 627}
628
b710a1f4
TH		 629static void ahci_enable_ahci(void __iomem *mmio)
630{
15fe982e 631 int i;
b710a1f4
TH		 632 u32 tmp;
633
634 /* turn on AHCI_EN */
635 tmp = readl(mmio + HOST_CTL);
15fe982e
TH		 636 if (tmp & HOST_AHCI_EN)
637 return;
638
639 /* Some controllers need AHCI_EN to be written multiple times.
640 * Try a few times before giving up.
641 */
642 for (i = 0; i < 5; i++) {
b710a1f4
TH		 643 tmp |= HOST_AHCI_EN;
644 writel(tmp, mmio + HOST_CTL);
645 tmp = readl(mmio + HOST_CTL); /* flush && sanity check */
15fe982e
TH		 646 if (tmp & HOST_AHCI_EN)
647 return;
648 msleep(10);
b710a1f4 649 }
15fe982e
TH		 650
651 WARN_ON(1);
b710a1f4
TH		 652}
653
d447df14
TH		 654/**
655 * ahci_save_initial_config - Save and fixup initial config values
4447d351 656 * @pdev: target PCI device
4447d351 657 * @hpriv: host private area to store config values
d447df14
TH		 658 *
659 * Some registers containing configuration info might be setup by
660 * BIOS and might be cleared on reset. This function saves the
661 * initial values of those registers into @hpriv such that they
662 * can be restored after controller reset.
663 *
664 * If inconsistent, config values are fixed up by this function.
665 *
666 * LOCKING:
667 * None.
668 */
4447d351 669static void ahci_save_initial_config(struct pci_dev *pdev,
4447d351 670 struct ahci_host_priv *hpriv)
d447df14 671{
4447d351 672 void __iomem *mmio = pcim_iomap_table(pdev)[AHCI_PCI_BAR];
d447df14 673 u32 cap, port_map;
17199b18 674 int i;
c40e7cb8 675 int mv;
d447df14 676
b710a1f4
TH		 677 /* make sure AHCI mode is enabled before accessing CAP */
678 ahci_enable_ahci(mmio);
679
d447df14
TH		 680 /* Values prefixed with saved_ are written back to host after
681 * reset. Values without are used for driver operation.
682 */
683 hpriv->saved_cap = cap = readl(mmio + HOST_CAP);
684 hpriv->saved_port_map = port_map = readl(mmio + HOST_PORTS_IMPL);
685
274c1fde 686 /* some chips have errata preventing 64bit use */
417a1a6d 687 if ((cap & HOST_CAP_64) && (hpriv->flags & AHCI_HFLAG_32BIT_ONLY)) {
c7a42156
TH		 688 dev_printk(KERN_INFO, &pdev->dev,
689 "controller can't do 64bit DMA, forcing 32bit\n");
690 cap &= ~HOST_CAP_64;
691 }
692
417a1a6d 693 if ((cap & HOST_CAP_NCQ) && (hpriv->flags & AHCI_HFLAG_NO_NCQ)) {
274c1fde
TH		 694 dev_printk(KERN_INFO, &pdev->dev,
695 "controller can't do NCQ, turning off CAP_NCQ\n");
696 cap &= ~HOST_CAP_NCQ;
697 }
698
e297d99e
TH		 699 if (!(cap & HOST_CAP_NCQ) && (hpriv->flags & AHCI_HFLAG_YES_NCQ)) {
700 dev_printk(KERN_INFO, &pdev->dev,
701 "controller can do NCQ, turning on CAP_NCQ\n");
702 cap |= HOST_CAP_NCQ;
703 }
704
258cd846 705 if ((cap & HOST_CAP_PMP) && (hpriv->flags & AHCI_HFLAG_NO_PMP)) {
6949b914
TH		 706 dev_printk(KERN_INFO, &pdev->dev,
707 "controller can't do PMP, turning off CAP_PMP\n");
708 cap &= ~HOST_CAP_PMP;
709 }
710
d799e083
TH		 711 if (pdev->vendor == PCI_VENDOR_ID_JMICRON && pdev->device == 0x2361 &&
712 port_map != 1) {
713 dev_printk(KERN_INFO, &pdev->dev,
714 "JMB361 has only one port, port_map 0x%x -> 0x%x\n",
715 port_map, 1);
716 port_map = 1;
717 }
718
cd70c266
JG		 719 /*
720 * Temporary Marvell 6145 hack: PATA port presence
721 * is asserted through the standard AHCI port
722 * presence register, as bit 4 (counting from 0)
723 */
417a1a6d 724 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
c40e7cb8
JAR		 725 if (pdev->device == 0x6121)
726 mv = 0x3;
727 else
728 mv = 0xf;
cd70c266
JG		 729 dev_printk(KERN_ERR, &pdev->dev,
730 "MV_AHCI HACK: port_map %x -> %x\n",
c40e7cb8
JAR		 731 port_map,
732 port_map & mv);
cd70c266 733
c40e7cb8 734 port_map &= mv;
cd70c266
JG		 735 }
736
17199b18 737 /* cross check port_map and cap.n_ports */
7a234aff 738 if (port_map) {
837f5f8f 739 int map_ports = 0;
17199b18 740
837f5f8f
TH		 741 for (i = 0; i < AHCI_MAX_PORTS; i++)
742 if (port_map & (1 << i))
743 map_ports++;
17199b18 744
837f5f8f
TH		 745 /* If PI has more ports than n_ports, whine, clear
746 * port_map and let it be generated from n_ports.
17199b18 747 */
837f5f8f 748 if (map_ports > ahci_nr_ports(cap)) {
4447d351 749 dev_printk(KERN_WARNING, &pdev->dev,
837f5f8f
TH		 750 "implemented port map (0x%x) contains more "
751 "ports than nr_ports (%u), using nr_ports\n",
752 port_map, ahci_nr_ports(cap));
7a234aff
TH		 753 port_map = 0;
754 }
755 }
756
757 /* fabricate port_map from cap.nr_ports */
758 if (!port_map) {
17199b18 759 port_map = (1 << ahci_nr_ports(cap)) - 1;
7a234aff
TH		 760 dev_printk(KERN_WARNING, &pdev->dev,
761 "forcing PORTS_IMPL to 0x%x\n", port_map);
762
763 /* write the fixed up value to the PI register */
764 hpriv->saved_port_map = port_map;
17199b18
TH		 765 }
766
d447df14
TH		 767 /* record values to use during operation */
768 hpriv->cap = cap;
769 hpriv->port_map = port_map;
770}
771
772/**
773 * ahci_restore_initial_config - Restore initial config
4447d351 774 * @host: target ATA host
d447df14
TH		 775 *
776 * Restore initial config stored by ahci_save_initial_config().
777 *
778 * LOCKING:
779 * None.
780 */
4447d351 781static void ahci_restore_initial_config(struct ata_host *host)
d447df14 782{
4447d351
TH		 783 struct ahci_host_priv *hpriv = host->private_data;
784 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
785
d447df14
TH		 786 writel(hpriv->saved_cap, mmio + HOST_CAP);
787 writel(hpriv->saved_port_map, mmio + HOST_PORTS_IMPL);
788 (void) readl(mmio + HOST_PORTS_IMPL); /* flush */
789}
790
203ef6c4 791static unsigned ahci_scr_offset(struct ata_port *ap, unsigned int sc_reg)
1da177e4 792{
203ef6c4
TH		 793 static const int offset[] = {
794 [SCR_STATUS] = PORT_SCR_STAT,
795 [SCR_CONTROL] = PORT_SCR_CTL,
796 [SCR_ERROR] = PORT_SCR_ERR,
797 [SCR_ACTIVE] = PORT_SCR_ACT,
798 [SCR_NOTIFICATION] = PORT_SCR_NTF,
799 };
800 struct ahci_host_priv *hpriv = ap->host->private_data;
1da177e4 801
203ef6c4
TH		 802 if (sc_reg < ARRAY_SIZE(offset) &&
803 (sc_reg != SCR_NOTIFICATION || (hpriv->cap & HOST_CAP_SNTF)))
804 return offset[sc_reg];
da3dbb17 805 return 0;
1da177e4
LT		 806}
807
203ef6c4 808static int ahci_scr_read(struct ata_port *ap, unsigned int sc_reg, u32 *val)
1da177e4 809{
203ef6c4
TH		 810 void __iomem *port_mmio = ahci_port_base(ap);
811 int offset = ahci_scr_offset(ap, sc_reg);
812
813 if (offset) {
814 *val = readl(port_mmio + offset);
815 return 0;
1da177e4 816 }
203ef6c4
TH		 817 return -EINVAL;
818}
1da177e4 819
203ef6c4
TH		 820static int ahci_scr_write(struct ata_port *ap, unsigned int sc_reg, u32 val)
821{
822 void __iomem *port_mmio = ahci_port_base(ap);
823 int offset = ahci_scr_offset(ap, sc_reg);
824
825 if (offset) {
826 writel(val, port_mmio + offset);
827 return 0;
828 }
829 return -EINVAL;
1da177e4
LT		 830}
831
4447d351 832static void ahci_start_engine(struct ata_port *ap)
7c76d1e8 833{
4447d351 834 void __iomem *port_mmio = ahci_port_base(ap);
7c76d1e8
TH		 835 u32 tmp;
836
d8fcd116 837 /* start DMA */
9f592056 838 tmp = readl(port_mmio + PORT_CMD);
7c76d1e8
TH		 839 tmp |= PORT_CMD_START;
840 writel(tmp, port_mmio + PORT_CMD);
841 readl(port_mmio + PORT_CMD); /* flush */
842}
843
4447d351 844static int ahci_stop_engine(struct ata_port *ap)
254950cd 845{
4447d351 846 void __iomem *port_mmio = ahci_port_base(ap);
254950cd
TH		 847 u32 tmp;
848
849 tmp = readl(port_mmio + PORT_CMD);
850
d8fcd116 851 /* check if the HBA is idle */
254950cd
TH		 852 if ((tmp & (PORT_CMD_START | PORT_CMD_LIST_ON)) == 0)
853 return 0;
854
d8fcd116 855 /* setting HBA to idle */
254950cd
TH		 856 tmp &= ~PORT_CMD_START;
857 writel(tmp, port_mmio + PORT_CMD);
858
d8fcd116 859 /* wait for engine to stop. This could be as long as 500 msec */
254950cd 860 tmp = ata_wait_register(port_mmio + PORT_CMD,
2dcb407e 861 PORT_CMD_LIST_ON, PORT_CMD_LIST_ON, 1, 500);
d8fcd116 862 if (tmp & PORT_CMD_LIST_ON)
254950cd
TH		 863 return -EIO;
864
865 return 0;
866}
867
4447d351 868static void ahci_start_fis_rx(struct ata_port *ap)
0be0aa98 869{
4447d351
TH		 870 void __iomem *port_mmio = ahci_port_base(ap);
871 struct ahci_host_priv *hpriv = ap->host->private_data;
872 struct ahci_port_priv *pp = ap->private_data;
0be0aa98
TH		 873 u32 tmp;
874
875 /* set FIS registers */
4447d351
TH		 876 if (hpriv->cap & HOST_CAP_64)
877 writel((pp->cmd_slot_dma >> 16) >> 16,
878 port_mmio + PORT_LST_ADDR_HI);
879 writel(pp->cmd_slot_dma & 0xffffffff, port_mmio + PORT_LST_ADDR);
0be0aa98 880
4447d351
TH		 881 if (hpriv->cap & HOST_CAP_64)
882 writel((pp->rx_fis_dma >> 16) >> 16,
883 port_mmio + PORT_FIS_ADDR_HI);
884 writel(pp->rx_fis_dma & 0xffffffff, port_mmio + PORT_FIS_ADDR);
0be0aa98
TH		 885
886 /* enable FIS reception */
887 tmp = readl(port_mmio + PORT_CMD);
888 tmp |= PORT_CMD_FIS_RX;
889 writel(tmp, port_mmio + PORT_CMD);
890
891 /* flush */
892 readl(port_mmio + PORT_CMD);
893}
894
4447d351 895static int ahci_stop_fis_rx(struct ata_port *ap)
0be0aa98 896{
4447d351 897 void __iomem *port_mmio = ahci_port_base(ap);
0be0aa98
TH		 898 u32 tmp;
899
900 /* disable FIS reception */
901 tmp = readl(port_mmio + PORT_CMD);
902 tmp &= ~PORT_CMD_FIS_RX;
903 writel(tmp, port_mmio + PORT_CMD);
904
905 /* wait for completion, spec says 500ms, give it 1000 */
906 tmp = ata_wait_register(port_mmio + PORT_CMD, PORT_CMD_FIS_ON,
907 PORT_CMD_FIS_ON, 10, 1000);
908 if (tmp & PORT_CMD_FIS_ON)
909 return -EBUSY;
910
911 return 0;
912}
913
4447d351 914static void ahci_power_up(struct ata_port *ap)
0be0aa98 915{
4447d351
TH		 916 struct ahci_host_priv *hpriv = ap->host->private_data;
917 void __iomem *port_mmio = ahci_port_base(ap);
0be0aa98
TH		 918 u32 cmd;
919
920 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
921
922 /* spin up device */
4447d351 923 if (hpriv->cap & HOST_CAP_SSS) {
0be0aa98
TH		 924 cmd |= PORT_CMD_SPIN_UP;
925 writel(cmd, port_mmio + PORT_CMD);
926 }
927
928 /* wake up link */
929 writel(cmd | PORT_CMD_ICC_ACTIVE, port_mmio + PORT_CMD);
930}
931
31556594
KCA		 932static void ahci_disable_alpm(struct ata_port *ap)
933{
934 struct ahci_host_priv *hpriv = ap->host->private_data;
935 void __iomem *port_mmio = ahci_port_base(ap);
936 u32 cmd;
937 struct ahci_port_priv *pp = ap->private_data;
938
939 /* IPM bits should be disabled by libata-core */
940 /* get the existing command bits */
941 cmd = readl(port_mmio + PORT_CMD);
942
943 /* disable ALPM and ASP */
944 cmd &= ~PORT_CMD_ASP;
945 cmd &= ~PORT_CMD_ALPE;
946
947 /* force the interface back to active */
948 cmd |= PORT_CMD_ICC_ACTIVE;
949
950 /* write out new cmd value */
951 writel(cmd, port_mmio + PORT_CMD);
952 cmd = readl(port_mmio + PORT_CMD);
953
954 /* wait 10ms to be sure we've come out of any low power state */
955 msleep(10);
956
957 /* clear out any PhyRdy stuff from interrupt status */
958 writel(PORT_IRQ_PHYRDY, port_mmio + PORT_IRQ_STAT);
959
960 /* go ahead and clean out PhyRdy Change from Serror too */
961 ahci_scr_write(ap, SCR_ERROR, ((1 << 16) | (1 << 18)));
962
963 /*
964 * Clear flag to indicate that we should ignore all PhyRdy
965 * state changes
966 */
967 hpriv->flags &= ~AHCI_HFLAG_NO_HOTPLUG;
968
969 /*
970 * Enable interrupts on Phy Ready.
971 */
972 pp->intr_mask |= PORT_IRQ_PHYRDY;
973 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
974
975 /*
976 * don't change the link pm policy - we can be called
977 * just to turn of link pm temporarily
978 */
979}
980
981static int ahci_enable_alpm(struct ata_port *ap,
982 enum link_pm policy)
983{
984 struct ahci_host_priv *hpriv = ap->host->private_data;
985 void __iomem *port_mmio = ahci_port_base(ap);
986 u32 cmd;
987 struct ahci_port_priv *pp = ap->private_data;
988 u32 asp;
989
990 /* Make sure the host is capable of link power management */
991 if (!(hpriv->cap & HOST_CAP_ALPM))
992 return -EINVAL;
993
994 switch (policy) {
995 case MAX_PERFORMANCE:
996 case NOT_AVAILABLE:
997 /*
998 * if we came here with NOT_AVAILABLE,
999 * it just means this is the first time we
1000 * have tried to enable - default to max performance,
1001 * and let the user go to lower power modes on request.
1002 */
1003 ahci_disable_alpm(ap);
1004 return 0;
1005 case MIN_POWER:
1006 /* configure HBA to enter SLUMBER */
1007 asp = PORT_CMD_ASP;
1008 break;
1009 case MEDIUM_POWER:
1010 /* configure HBA to enter PARTIAL */
1011 asp = 0;
1012 break;
1013 default:
1014 return -EINVAL;
1015 }
1016
1017 /*
1018 * Disable interrupts on Phy Ready. This keeps us from
1019 * getting woken up due to spurious phy ready interrupts
1020 * TBD - Hot plug should be done via polling now, is
1021 * that even supported?
1022 */
1023 pp->intr_mask &= ~PORT_IRQ_PHYRDY;
1024 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
1025
1026 /*
1027 * Set a flag to indicate that we should ignore all PhyRdy
1028 * state changes since these can happen now whenever we
1029 * change link state
1030 */
1031 hpriv->flags |= AHCI_HFLAG_NO_HOTPLUG;
1032
1033 /* get the existing command bits */
1034 cmd = readl(port_mmio + PORT_CMD);
1035
1036 /*
1037 * Set ASP based on Policy
1038 */
1039 cmd |= asp;
1040
1041 /*
1042 * Setting this bit will instruct the HBA to aggressively
1043 * enter a lower power link state when it's appropriate and
1044 * based on the value set above for ASP
1045 */
1046 cmd |= PORT_CMD_ALPE;
1047
1048 /* write out new cmd value */
1049 writel(cmd, port_mmio + PORT_CMD);
1050 cmd = readl(port_mmio + PORT_CMD);
1051
1052 /* IPM bits should be set by libata-core */
1053 return 0;
1054}
1055
438ac6d5 1056#ifdef CONFIG_PM
4447d351 1057static void ahci_power_down(struct ata_port *ap)
0be0aa98 1058{
4447d351
TH		 1059 struct ahci_host_priv *hpriv = ap->host->private_data;
1060 void __iomem *port_mmio = ahci_port_base(ap);
0be0aa98
TH		 1061 u32 cmd, scontrol;
1062
4447d351 1063 if (!(hpriv->cap & HOST_CAP_SSS))
07c53dac 1064 return;
0be0aa98 1065
07c53dac
TH		 1066 /* put device into listen mode, first set PxSCTL.DET to 0 */
1067 scontrol = readl(port_mmio + PORT_SCR_CTL);
1068 scontrol &= ~0xf;
1069 writel(scontrol, port_mmio + PORT_SCR_CTL);
0be0aa98 1070
07c53dac
TH		 1071 /* then set PxCMD.SUD to 0 */
1072 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
1073 cmd &= ~PORT_CMD_SPIN_UP;
1074 writel(cmd, port_mmio + PORT_CMD);
0be0aa98 1075}
438ac6d5 1076#endif
0be0aa98 1077
df69c9c5 1078static void ahci_start_port(struct ata_port *ap)
0be0aa98 1079{
18f7ba4c
KCA		 1080 struct ahci_port_priv *pp = ap->private_data;
1081 struct ata_link *link;
1082 struct ahci_em_priv *emp;
1083
0be0aa98 1084 /* enable FIS reception */
4447d351 1085 ahci_start_fis_rx(ap);
0be0aa98
TH		 1086
1087 /* enable DMA */
4447d351 1088 ahci_start_engine(ap);
18f7ba4c
KCA		 1089
1090 /* turn on LEDs */
1091 if (ap->flags & ATA_FLAG_EM) {
1092 ata_port_for_each_link(link, ap) {
1093 emp = &pp->em_priv[link->pmp];
1094 ahci_transmit_led_message(ap, emp->led_state, 4);
1095 }
1096 }
1097
1098 if (ap->flags & ATA_FLAG_SW_ACTIVITY)
1099 ata_port_for_each_link(link, ap)
1100 ahci_init_sw_activity(link);
1101
0be0aa98
TH		 1102}
1103
4447d351 1104static int ahci_deinit_port(struct ata_port *ap, const char **emsg)
0be0aa98
TH		 1105{
1106 int rc;
1107
1108 /* disable DMA */
4447d351 1109 rc = ahci_stop_engine(ap);
0be0aa98
TH		 1110 if (rc) {
1111 *emsg = "failed to stop engine";
1112 return rc;
1113 }
1114
1115 /* disable FIS reception */
4447d351 1116 rc = ahci_stop_fis_rx(ap);
0be0aa98
TH		 1117 if (rc) {
1118 *emsg = "failed stop FIS RX";
1119 return rc;
1120 }
1121
0be0aa98
TH		 1122 return 0;
1123}
1124
4447d351 1125static int ahci_reset_controller(struct ata_host *host)
d91542c1 1126{
4447d351 1127 struct pci_dev *pdev = to_pci_dev(host->dev);
49f29090 1128 struct ahci_host_priv *hpriv = host->private_data;
4447d351 1129 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
d447df14 1130 u32 tmp;
d91542c1 1131
3cc3eb11
JG		 1132 /* we must be in AHCI mode, before using anything
1133 * AHCI-specific, such as HOST_RESET.
1134 */
b710a1f4 1135 ahci_enable_ahci(mmio);
3cc3eb11
JG		 1136
1137 /* global controller reset */
a22e6444
TH		 1138 if (!ahci_skip_host_reset) {
1139 tmp = readl(mmio + HOST_CTL);
1140 if ((tmp & HOST_RESET) == 0) {
1141 writel(tmp | HOST_RESET, mmio + HOST_CTL);
1142 readl(mmio + HOST_CTL); /* flush */
1143 }
d91542c1 1144
24920c8a
ZR		 1145 /*
1146 * to perform host reset, OS should set HOST_RESET
1147 * and poll until this bit is read to be "0".
1148 * reset must complete within 1 second, or
a22e6444
TH		 1149 * the hardware should be considered fried.
1150 */
24920c8a
ZR		 1151 tmp = ata_wait_register(mmio + HOST_CTL, HOST_RESET,
1152 HOST_RESET, 10, 1000);
d91542c1 1153
a22e6444
TH		 1154 if (tmp & HOST_RESET) {
1155 dev_printk(KERN_ERR, host->dev,
1156 "controller reset failed (0x%x)\n", tmp);
1157 return -EIO;
1158 }
d91542c1 1159
a22e6444
TH		 1160 /* turn on AHCI mode */
1161 ahci_enable_ahci(mmio);
98fa4b60 1162
a22e6444
TH		 1163 /* Some registers might be cleared on reset. Restore
1164 * initial values.
1165 */
1166 ahci_restore_initial_config(host);
1167 } else
1168 dev_printk(KERN_INFO, host->dev,
1169 "skipping global host reset\n");
d91542c1
TH		 1170
1171 if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
1172 u16 tmp16;
1173
1174 /* configure PCS */
1175 pci_read_config_word(pdev, 0x92, &tmp16);
49f29090
TH		 1176 if ((tmp16 & hpriv->port_map) != hpriv->port_map) {
1177 tmp16 |= hpriv->port_map;
1178 pci_write_config_word(pdev, 0x92, tmp16);
1179 }
d91542c1
TH		 1180 }
1181
1182 return 0;
1183}
1184
18f7ba4c
KCA		 1185static void ahci_sw_activity(struct ata_link *link)
1186{
1187 struct ata_port *ap = link->ap;
1188 struct ahci_port_priv *pp = ap->private_data;
1189 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
1190
1191 if (!(link->flags & ATA_LFLAG_SW_ACTIVITY))
1192 return;
1193
1194 emp->activity++;
1195 if (!timer_pending(&emp->timer))
1196 mod_timer(&emp->timer, jiffies + msecs_to_jiffies(10));
1197}
1198
1199static void ahci_sw_activity_blink(unsigned long arg)
1200{
1201 struct ata_link *link = (struct ata_link *)arg;
1202 struct ata_port *ap = link->ap;
1203 struct ahci_port_priv *pp = ap->private_data;
1204 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
1205 unsigned long led_message = emp->led_state;
1206 u32 activity_led_state;
1207
1208 led_message &= 0xffff0000;
1209 led_message |= ap->port_no | (link->pmp << 8);
1210
1211 /* check to see if we've had activity. If so,
1212 * toggle state of LED and reset timer. If not,
1213 * turn LED to desired idle state.
1214 */
1215 if (emp->saved_activity != emp->activity) {
1216 emp->saved_activity = emp->activity;
1217 /* get the current LED state */
1218 activity_led_state = led_message & 0x00010000;
1219
1220 if (activity_led_state)
1221 activity_led_state = 0;
1222 else
1223 activity_led_state = 1;
1224
1225 /* clear old state */
1226 led_message &= 0xfff8ffff;
1227
1228 /* toggle state */
1229 led_message |= (activity_led_state << 16);
1230 mod_timer(&emp->timer, jiffies + msecs_to_jiffies(100));
1231 } else {
1232 /* switch to idle */
1233 led_message &= 0xfff8ffff;
1234 if (emp->blink_policy == BLINK_OFF)
1235 led_message |= (1 << 16);
1236 }
1237 ahci_transmit_led_message(ap, led_message, 4);
1238}
1239
1240static void ahci_init_sw_activity(struct ata_link *link)
1241{
1242 struct ata_port *ap = link->ap;
1243 struct ahci_port_priv *pp = ap->private_data;
1244 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
1245
1246 /* init activity stats, setup timer */
1247 emp->saved_activity = emp->activity = 0;
1248 setup_timer(&emp->timer, ahci_sw_activity_blink, (unsigned long)link);
1249
1250 /* check our blink policy and set flag for link if it's enabled */
1251 if (emp->blink_policy)
1252 link->flags |= ATA_LFLAG_SW_ACTIVITY;
1253}
1254
1255static int ahci_reset_em(struct ata_host *host)
1256{
1257 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
1258 u32 em_ctl;
1259
1260 em_ctl = readl(mmio + HOST_EM_CTL);
1261 if ((em_ctl & EM_CTL_TM) || (em_ctl & EM_CTL_RST))
1262 return -EINVAL;
1263
1264 writel(em_ctl | EM_CTL_RST, mmio + HOST_EM_CTL);
1265 return 0;
1266}
1267
1268static ssize_t ahci_transmit_led_message(struct ata_port *ap, u32 state,
1269 ssize_t size)
1270{
1271 struct ahci_host_priv *hpriv = ap->host->private_data;
1272 struct ahci_port_priv *pp = ap->private_data;
1273 void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR];
1274 u32 em_ctl;
1275 u32 message[] = {0, 0};
93082f0b 1276 unsigned long flags;
18f7ba4c
KCA		 1277 int pmp;
1278 struct ahci_em_priv *emp;
1279
1280 /* get the slot number from the message */
1281 pmp = (state & 0x0000ff00) >> 8;
1282 if (pmp < MAX_SLOTS)
1283 emp = &pp->em_priv[pmp];
1284 else
1285 return -EINVAL;
1286
1287 spin_lock_irqsave(ap->lock, flags);
1288
1289 /*
1290 * if we are still busy transmitting a previous message,
1291 * do not allow
1292 */
1293 em_ctl = readl(mmio + HOST_EM_CTL);
1294 if (em_ctl & EM_CTL_TM) {
1295 spin_unlock_irqrestore(ap->lock, flags);
1296 return -EINVAL;
1297 }
1298
1299 /*
1300 * create message header - this is all zero except for
1301 * the message size, which is 4 bytes.
1302 */
1303 message[0] |= (4 << 8);
1304
1305 /* ignore 0:4 of byte zero, fill in port info yourself */
1306 message[1] = ((state & 0xfffffff0) | ap->port_no);
1307
1308 /* write message to EM_LOC */
1309 writel(message[0], mmio + hpriv->em_loc);
1310 writel(message[1], mmio + hpriv->em_loc+4);
1311
1312 /* save off new led state for port/slot */
1313 emp->led_state = message[1];
1314
1315 /*
1316 * tell hardware to transmit the message
1317 */
1318 writel(em_ctl | EM_CTL_TM, mmio + HOST_EM_CTL);
1319
1320 spin_unlock_irqrestore(ap->lock, flags);
1321 return size;
1322}
1323
1324static ssize_t ahci_led_show(struct ata_port *ap, char *buf)
1325{
1326 struct ahci_port_priv *pp = ap->private_data;
1327 struct ata_link *link;
1328 struct ahci_em_priv *emp;
1329 int rc = 0;
1330
1331 ata_port_for_each_link(link, ap) {
1332 emp = &pp->em_priv[link->pmp];
1333 rc += sprintf(buf, "%lx\n", emp->led_state);
1334 }
1335 return rc;
1336}
1337
1338static ssize_t ahci_led_store(struct ata_port *ap, const char *buf,
1339 size_t size)
1340{
1341 int state;
1342 int pmp;
1343 struct ahci_port_priv *pp = ap->private_data;
1344 struct ahci_em_priv *emp;
1345
1346 state = simple_strtoul(buf, NULL, 0);
1347
1348 /* get the slot number from the message */
1349 pmp = (state & 0x0000ff00) >> 8;
1350 if (pmp < MAX_SLOTS)
1351 emp = &pp->em_priv[pmp];
1352 else
1353 return -EINVAL;
1354
1355 /* mask off the activity bits if we are in sw_activity
1356 * mode, user should turn off sw_activity before setting
1357 * activity led through em_message
1358 */
1359 if (emp->blink_policy)
1360 state &= 0xfff8ffff;
1361
1362 return ahci_transmit_led_message(ap, state, size);
1363}
1364
1365static ssize_t ahci_activity_store(struct ata_device *dev, enum sw_activity val)
1366{
1367 struct ata_link *link = dev->link;
1368 struct ata_port *ap = link->ap;
1369 struct ahci_port_priv *pp = ap->private_data;
1370 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
1371 u32 port_led_state = emp->led_state;
1372
1373 /* save the desired Activity LED behavior */
1374 if (val == OFF) {
1375 /* clear LFLAG */
1376 link->flags &= ~(ATA_LFLAG_SW_ACTIVITY);
1377
1378 /* set the LED to OFF */
1379 port_led_state &= 0xfff80000;
1380 port_led_state |= (ap->port_no | (link->pmp << 8));
1381 ahci_transmit_led_message(ap, port_led_state, 4);
1382 } else {
1383 link->flags |= ATA_LFLAG_SW_ACTIVITY;
1384 if (val == BLINK_OFF) {
1385 /* set LED to ON for idle */
1386 port_led_state &= 0xfff80000;
1387 port_led_state |= (ap->port_no | (link->pmp << 8));
1388 port_led_state |= 0x00010000; /* check this */
1389 ahci_transmit_led_message(ap, port_led_state, 4);
1390 }
1391 }
1392 emp->blink_policy = val;
1393 return 0;
1394}
1395
1396static ssize_t ahci_activity_show(struct ata_device *dev, char *buf)
1397{
1398 struct ata_link *link = dev->link;
1399 struct ata_port *ap = link->ap;
1400 struct ahci_port_priv *pp = ap->private_data;
1401 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
1402
1403 /* display the saved value of activity behavior for this
1404 * disk.
1405 */
1406 return sprintf(buf, "%d\n", emp->blink_policy);
1407}
1408
2bcd866b
JG		 1409static void ahci_port_init(struct pci_dev *pdev, struct ata_port *ap,
1410 int port_no, void __iomem *mmio,
1411 void __iomem *port_mmio)
1412{
1413 const char *emsg = NULL;
1414 int rc;
1415 u32 tmp;
1416
1417 /* make sure port is not active */
1418 rc = ahci_deinit_port(ap, &emsg);
1419 if (rc)
1420 dev_printk(KERN_WARNING, &pdev->dev,
1421 "%s (%d)\n", emsg, rc);
1422
1423 /* clear SError */
1424 tmp = readl(port_mmio + PORT_SCR_ERR);
1425 VPRINTK("PORT_SCR_ERR 0x%x\n", tmp);
1426 writel(tmp, port_mmio + PORT_SCR_ERR);
1427
1428 /* clear port IRQ */
1429 tmp = readl(port_mmio + PORT_IRQ_STAT);
1430 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
1431 if (tmp)
1432 writel(tmp, port_mmio + PORT_IRQ_STAT);
1433
1434 writel(1 << port_no, mmio + HOST_IRQ_STAT);
1435}
1436
4447d351 1437static void ahci_init_controller(struct ata_host *host)
d91542c1 1438{
417a1a6d 1439 struct ahci_host_priv *hpriv = host->private_data;
4447d351
TH		 1440 struct pci_dev *pdev = to_pci_dev(host->dev);
1441 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
2bcd866b 1442 int i;
cd70c266 1443 void __iomem *port_mmio;
d91542c1 1444 u32 tmp;
c40e7cb8 1445 int mv;
d91542c1 1446
417a1a6d 1447 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
c40e7cb8
JAR		 1448 if (pdev->device == 0x6121)
1449 mv = 2;
1450 else
1451 mv = 4;
1452 port_mmio = __ahci_port_base(host, mv);
cd70c266
JG		 1453
1454 writel(0, port_mmio + PORT_IRQ_MASK);
1455
1456 /* clear port IRQ */
1457 tmp = readl(port_mmio + PORT_IRQ_STAT);
1458 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
1459 if (tmp)
1460 writel(tmp, port_mmio + PORT_IRQ_STAT);
1461 }
1462
4447d351
TH		 1463 for (i = 0; i < host->n_ports; i++) {
1464 struct ata_port *ap = host->ports[i];
d91542c1 1465
cd70c266 1466 port_mmio = ahci_port_base(ap);
4447d351 1467 if (ata_port_is_dummy(ap))
d91542c1 1468 continue;
d91542c1 1469
2bcd866b 1470 ahci_port_init(pdev, ap, i, mmio, port_mmio);
d91542c1
TH		 1471 }
1472
1473 tmp = readl(mmio + HOST_CTL);
1474 VPRINTK("HOST_CTL 0x%x\n", tmp);
1475 writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL);
1476 tmp = readl(mmio + HOST_CTL);
1477 VPRINTK("HOST_CTL 0x%x\n", tmp);
1478}
1479
a878539e
JG		 1480static void ahci_dev_config(struct ata_device *dev)
1481{
1482 struct ahci_host_priv *hpriv = dev->link->ap->host->private_data;
1483
4cde32fc 1484 if (hpriv->flags & AHCI_HFLAG_SECT255) {
a878539e 1485 dev->max_sectors = 255;
4cde32fc
JG		 1486 ata_dev_printk(dev, KERN_INFO,
1487 "SB600 AHCI: limiting to 255 sectors per cmd\n");
1488 }
a878539e
JG		 1489}
1490
422b7595 1491static unsigned int ahci_dev_classify(struct ata_port *ap)
1da177e4 1492{
4447d351 1493 void __iomem *port_mmio = ahci_port_base(ap);
1da177e4 1494 struct ata_taskfile tf;
422b7595
TH		 1495 u32 tmp;
1496
1497 tmp = readl(port_mmio + PORT_SIG);
1498 tf.lbah = (tmp >> 24) & 0xff;
1499 tf.lbam = (tmp >> 16) & 0xff;
1500 tf.lbal = (tmp >> 8) & 0xff;
1501 tf.nsect = (tmp) & 0xff;
1502
1503 return ata_dev_classify(&tf);
1504}
1505
12fad3f9
TH		 1506static void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag,
1507 u32 opts)
cc9278ed 1508{
12fad3f9
TH		 1509 dma_addr_t cmd_tbl_dma;
1510
1511 cmd_tbl_dma = pp->cmd_tbl_dma + tag * AHCI_CMD_TBL_SZ;
1512
1513 pp->cmd_slot[tag].opts = cpu_to_le32(opts);
1514 pp->cmd_slot[tag].status = 0;
1515 pp->cmd_slot[tag].tbl_addr = cpu_to_le32(cmd_tbl_dma & 0xffffffff);
1516 pp->cmd_slot[tag].tbl_addr_hi = cpu_to_le32((cmd_tbl_dma >> 16) >> 16);
cc9278ed
TH		 1517}
1518
d2e75dff 1519static int ahci_kick_engine(struct ata_port *ap, int force_restart)
4658f79b 1520{
350756f6 1521 void __iomem *port_mmio = ahci_port_base(ap);
cca3974e 1522 struct ahci_host_priv *hpriv = ap->host->private_data;
520d06f9 1523 u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF;
bf2af2a2 1524 u32 tmp;
d2e75dff 1525 int busy, rc;
bf2af2a2 1526
d2e75dff 1527 /* do we need to kick the port? */
520d06f9 1528 busy = status & (ATA_BUSY | ATA_DRQ);
d2e75dff
TH		 1529 if (!busy && !force_restart)
1530 return 0;
1531
1532 /* stop engine */
1533 rc = ahci_stop_engine(ap);
1534 if (rc)
1535 goto out_restart;
1536
1537 /* need to do CLO? */
1538 if (!busy) {
1539 rc = 0;
1540 goto out_restart;
1541 }
1542
1543 if (!(hpriv->cap & HOST_CAP_CLO)) {
1544 rc = -EOPNOTSUPP;
1545 goto out_restart;
1546 }
bf2af2a2 1547
d2e75dff 1548 /* perform CLO */
bf2af2a2
BJ		 1549 tmp = readl(port_mmio + PORT_CMD);
1550 tmp |= PORT_CMD_CLO;
1551 writel(tmp, port_mmio + PORT_CMD);
1552
d2e75dff 1553 rc = 0;
bf2af2a2
BJ		 1554 tmp = ata_wait_register(port_mmio + PORT_CMD,
1555 PORT_CMD_CLO, PORT_CMD_CLO, 1, 500);
1556 if (tmp & PORT_CMD_CLO)
d2e75dff 1557 rc = -EIO;
bf2af2a2 1558
d2e75dff
TH		 1559 /* restart engine */
1560 out_restart:
1561 ahci_start_engine(ap);
1562 return rc;
bf2af2a2
BJ		 1563}
1564
91c4a2e0
TH		 1565static int ahci_exec_polled_cmd(struct ata_port *ap, int pmp,
1566 struct ata_taskfile *tf, int is_cmd, u16 flags,
1567 unsigned long timeout_msec)
bf2af2a2 1568{
91c4a2e0 1569 const u32 cmd_fis_len = 5; /* five dwords */
4658f79b 1570 struct ahci_port_priv *pp = ap->private_data;
4447d351 1571 void __iomem *port_mmio = ahci_port_base(ap);
91c4a2e0
TH		 1572 u8 *fis = pp->cmd_tbl;
1573 u32 tmp;
1574
1575 /* prep the command */
1576 ata_tf_to_fis(tf, pmp, is_cmd, fis);
1577 ahci_fill_cmd_slot(pp, 0, cmd_fis_len | flags | (pmp << 12));
1578
1579 /* issue & wait */
1580 writel(1, port_mmio + PORT_CMD_ISSUE);
1581
1582 if (timeout_msec) {
1583 tmp = ata_wait_register(port_mmio + PORT_CMD_ISSUE, 0x1, 0x1,
1584 1, timeout_msec);
1585 if (tmp & 0x1) {
1586 ahci_kick_engine(ap, 1);
1587 return -EBUSY;
1588 }
1589 } else
1590 readl(port_mmio + PORT_CMD_ISSUE); /* flush */
1591
1592 return 0;
1593}
1594
bd17243a
SH		 1595static int ahci_do_softreset(struct ata_link *link, unsigned int *class,
1596 int pmp, unsigned long deadline,
1597 int (*check_ready)(struct ata_link *link))
91c4a2e0 1598{
cc0680a5 1599 struct ata_port *ap = link->ap;
4658f79b 1600 const char *reason = NULL;
2cbb79eb 1601 unsigned long now, msecs;
4658f79b 1602 struct ata_taskfile tf;
4658f79b
TH		 1603 int rc;
1604
1605 DPRINTK("ENTER\n");
1606
1607 /* prepare for SRST (AHCI-1.1 10.4.1) */
d2e75dff 1608 rc = ahci_kick_engine(ap, 1);
994056d7 1609 if (rc && rc != -EOPNOTSUPP)
cc0680a5 1610 ata_link_printk(link, KERN_WARNING,
994056d7 1611 "failed to reset engine (errno=%d)\n", rc);
4658f79b 1612
cc0680a5 1613 ata_tf_init(link->device, &tf);
4658f79b
TH		 1614
1615 /* issue the first D2H Register FIS */
2cbb79eb
TH		 1616 msecs = 0;
1617 now = jiffies;
1618 if (time_after(now, deadline))
1619 msecs = jiffies_to_msecs(deadline - now);
1620
4658f79b 1621 tf.ctl |= ATA_SRST;
a9cf5e85 1622 if (ahci_exec_polled_cmd(ap, pmp, &tf, 0,
91c4a2e0 1623 AHCI_CMD_RESET | AHCI_CMD_CLR_BUSY, msecs)) {
4658f79b
TH		 1624 rc = -EIO;
1625 reason = "1st FIS failed";
1626 goto fail;
1627 }
1628
1629 /* spec says at least 5us, but be generous and sleep for 1ms */
1630 msleep(1);
1631
1632 /* issue the second D2H Register FIS */
4658f79b 1633 tf.ctl &= ~ATA_SRST;
a9cf5e85 1634 ahci_exec_polled_cmd(ap, pmp, &tf, 0, 0, 0);
4658f79b 1635
705e76be 1636 /* wait for link to become ready */
bd17243a 1637 rc = ata_wait_after_reset(link, deadline, check_ready);
9b89391c
TH		 1638 /* link occupied, -ENODEV too is an error */
1639 if (rc) {
1640 reason = "device not ready";
1641 goto fail;
4658f79b 1642 }
9b89391c 1643 *class = ahci_dev_classify(ap);
4658f79b
TH		 1644
1645 DPRINTK("EXIT, class=%u\n", *class);
1646 return 0;
1647
4658f79b 1648 fail:
cc0680a5 1649 ata_link_printk(link, KERN_ERR, "softreset failed (%s)\n", reason);
4658f79b
TH		 1650 return rc;
1651}
1652
bd17243a
SH		 1653static int ahci_check_ready(struct ata_link *link)
1654{
1655 void __iomem *port_mmio = ahci_port_base(link->ap);
1656 u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF;
1657
1658 return ata_check_ready(status);
1659}
1660
1661static int ahci_softreset(struct ata_link *link, unsigned int *class,
1662 unsigned long deadline)
1663{
1664 int pmp = sata_srst_pmp(link);
1665
1666 DPRINTK("ENTER\n");
1667
1668 return ahci_do_softreset(link, class, pmp, deadline, ahci_check_ready);
1669}
1670
1671static int ahci_sb600_check_ready(struct ata_link *link)
1672{
1673 void __iomem *port_mmio = ahci_port_base(link->ap);
1674 u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF;
1675 u32 irq_status = readl(port_mmio + PORT_IRQ_STAT);
1676
1677 /*
1678 * There is no need to check TFDATA if BAD PMP is found due to HW bug,
1679 * which can save timeout delay.
1680 */
1681 if (irq_status & PORT_IRQ_BAD_PMP)
1682 return -EIO;
1683
1684 return ata_check_ready(status);
1685}
1686
1687static int ahci_sb600_softreset(struct ata_link *link, unsigned int *class,
1688 unsigned long deadline)
1689{
1690 struct ata_port *ap = link->ap;
1691 void __iomem *port_mmio = ahci_port_base(ap);
1692 int pmp = sata_srst_pmp(link);
1693 int rc;
1694 u32 irq_sts;
1695
1696 DPRINTK("ENTER\n");
1697
1698 rc = ahci_do_softreset(link, class, pmp, deadline,
1699 ahci_sb600_check_ready);
1700
1701 /*
1702 * Soft reset fails on some ATI chips with IPMS set when PMP
1703 * is enabled but SATA HDD/ODD is connected to SATA port,
1704 * do soft reset again to port 0.
1705 */
1706 if (rc == -EIO) {
1707 irq_sts = readl(port_mmio + PORT_IRQ_STAT);
1708 if (irq_sts & PORT_IRQ_BAD_PMP) {
1709 ata_link_printk(link, KERN_WARNING,
1710 "failed due to HW bug, retry pmp=0\n");
1711 rc = ahci_do_softreset(link, class, 0, deadline,
1712 ahci_check_ready);
1713 }
1714 }
1715
1716 return rc;
1717}
1718
cc0680a5 1719static int ahci_hardreset(struct ata_link *link, unsigned int *class,
d4b2bab4 1720 unsigned long deadline)
422b7595 1721{
9dadd45b 1722 const unsigned long *timing = sata_ehc_deb_timing(&link->eh_context);
cc0680a5 1723 struct ata_port *ap = link->ap;
4296971d
TH		 1724 struct ahci_port_priv *pp = ap->private_data;
1725 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
1726 struct ata_taskfile tf;
9dadd45b 1727 bool online;
4bd00f6a
TH		 1728 int rc;
1729
1730 DPRINTK("ENTER\n");
1da177e4 1731
4447d351 1732 ahci_stop_engine(ap);
4296971d
TH		 1733
1734 /* clear D2H reception area to properly wait for D2H FIS */
cc0680a5 1735 ata_tf_init(link->device, &tf);
dfd7a3db 1736 tf.command = 0x80;
9977126c 1737 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
4296971d 1738
9dadd45b
TH		 1739 rc = sata_link_hardreset(link, timing, deadline, &online,
1740 ahci_check_ready);
4296971d 1741
4447d351 1742 ahci_start_engine(ap);
1da177e4 1743
9dadd45b 1744 if (online)
4bd00f6a 1745 *class = ahci_dev_classify(ap);
1da177e4 1746
4bd00f6a
TH		 1747 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
1748 return rc;
1749}
1750
cc0680a5 1751static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
d4b2bab4 1752 unsigned long deadline)
ad616ffb 1753{
cc0680a5 1754 struct ata_port *ap = link->ap;
9dadd45b 1755 bool online;
ad616ffb
TH		 1756 int rc;
1757
1758 DPRINTK("ENTER\n");
1759
4447d351 1760 ahci_stop_engine(ap);
ad616ffb 1761
cc0680a5 1762 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
9dadd45b 1763 deadline, &online, NULL);
ad616ffb 1764
4447d351 1765 ahci_start_engine(ap);
ad616ffb
TH		 1766
1767 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
1768
1769 /* vt8251 doesn't clear BSY on signature FIS reception,
1770 * request follow-up softreset.
1771 */
9dadd45b 1772 return online ? -EAGAIN : rc;
ad616ffb
TH		 1773}
1774
edc93052
TH		 1775static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
1776 unsigned long deadline)
1777{
1778 struct ata_port *ap = link->ap;
1779 struct ahci_port_priv *pp = ap->private_data;
1780 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
1781 struct ata_taskfile tf;
9dadd45b 1782 bool online;
edc93052
TH		 1783 int rc;
1784
1785 ahci_stop_engine(ap);
1786
1787 /* clear D2H reception area to properly wait for D2H FIS */
1788 ata_tf_init(link->device, &tf);
1789 tf.command = 0x80;
1790 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
1791
1792 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
9dadd45b 1793 deadline, &online, NULL);
edc93052
TH		 1794
1795 ahci_start_engine(ap);
1796
edc93052
TH		 1797 /* The pseudo configuration device on SIMG4726 attached to
1798 * ASUS P5W-DH Deluxe doesn't send signature FIS after
1799 * hardreset if no device is attached to the first downstream
1800 * port && the pseudo device locks up on SRST w/ PMP==0. To
1801 * work around this, wait for !BSY only briefly. If BSY isn't
1802 * cleared, perform CLO and proceed to IDENTIFY (achieved by
1803 * ATA_LFLAG_NO_SRST and ATA_LFLAG_ASSUME_ATA).
1804 *
1805 * Wait for two seconds. Devices attached to downstream port
1806 * which can't process the following IDENTIFY after this will
1807 * have to be reset again. For most cases, this should
1808 * suffice while making probing snappish enough.
1809 */
9dadd45b
TH		 1810 if (online) {
1811 rc = ata_wait_after_reset(link, jiffies + 2 * HZ,
1812 ahci_check_ready);
1813 if (rc)
1814 ahci_kick_engine(ap, 0);
1815 }
9dadd45b 1816 return rc;
edc93052
TH		 1817}
1818
cc0680a5 1819static void ahci_postreset(struct ata_link *link, unsigned int *class)
4bd00f6a 1820{
cc0680a5 1821 struct ata_port *ap = link->ap;
4447d351 1822 void __iomem *port_mmio = ahci_port_base(ap);
4bd00f6a
TH		 1823 u32 new_tmp, tmp;
1824
203c75b8 1825 ata_std_postreset(link, class);
02eaa666
JG		 1826
1827 /* Make sure port's ATAPI bit is set appropriately */
1828 new_tmp = tmp = readl(port_mmio + PORT_CMD);
4bd00f6a 1829 if (*class == ATA_DEV_ATAPI)
02eaa666
JG		 1830 new_tmp |= PORT_CMD_ATAPI;
1831 else
1832 new_tmp &= ~PORT_CMD_ATAPI;
1833 if (new_tmp != tmp) {
1834 writel(new_tmp, port_mmio + PORT_CMD);
1835 readl(port_mmio + PORT_CMD); /* flush */
1836 }
1da177e4
LT		 1837}
1838
12fad3f9 1839static unsigned int ahci_fill_sg(struct ata_queued_cmd *qc, void *cmd_tbl)
1da177e4 1840{
cedc9a47 1841 struct scatterlist *sg;
ff2aeb1e
TH		 1842 struct ahci_sg *ahci_sg = cmd_tbl + AHCI_CMD_TBL_HDR_SZ;
1843 unsigned int si;
1da177e4
LT		 1844
1845 VPRINTK("ENTER\n");
1846
1847 /*
1848 * Next, the S/G list.
1849 */
ff2aeb1e 1850 for_each_sg(qc->sg, sg, qc->n_elem, si) {
cedc9a47
JG		 1851 dma_addr_t addr = sg_dma_address(sg);
1852 u32 sg_len = sg_dma_len(sg);
1853
ff2aeb1e
TH		 1854 ahci_sg[si].addr = cpu_to_le32(addr & 0xffffffff);
1855 ahci_sg[si].addr_hi = cpu_to_le32((addr >> 16) >> 16);
1856 ahci_sg[si].flags_size = cpu_to_le32(sg_len - 1);
1da177e4 1857 }
828d09de 1858
ff2aeb1e 1859 return si;
1da177e4
LT		 1860}
1861
1862static void ahci_qc_prep(struct ata_queued_cmd *qc)
1863{
a0ea7328
JG		 1864 struct ata_port *ap = qc->ap;
1865 struct ahci_port_priv *pp = ap->private_data;
405e66b3 1866 int is_atapi = ata_is_atapi(qc->tf.protocol);
12fad3f9 1867 void *cmd_tbl;
1da177e4
LT		 1868 u32 opts;
1869 const u32 cmd_fis_len = 5; /* five dwords */
828d09de 1870 unsigned int n_elem;
1da177e4 1871
1da177e4
LT		 1872 /*
1873 * Fill in command table information. First, the header,
1874 * a SATA Register - Host to Device command FIS.
1875 */
12fad3f9
TH		 1876 cmd_tbl = pp->cmd_tbl + qc->tag * AHCI_CMD_TBL_SZ;
1877
7d50b60b 1878 ata_tf_to_fis(&qc->tf, qc->dev->link->pmp, 1, cmd_tbl);
cc9278ed 1879 if (is_atapi) {
12fad3f9
TH		 1880 memset(cmd_tbl + AHCI_CMD_TBL_CDB, 0, 32);
1881 memcpy(cmd_tbl + AHCI_CMD_TBL_CDB, qc->cdb, qc->dev->cdb_len);
a0ea7328 1882 }
1da177e4 1883
cc9278ed
TH		 1884 n_elem = 0;
1885 if (qc->flags & ATA_QCFLAG_DMAMAP)
12fad3f9 1886 n_elem = ahci_fill_sg(qc, cmd_tbl);
1da177e4 1887
cc9278ed
TH		 1888 /*
1889 * Fill in command slot information.
1890 */
7d50b60b 1891 opts = cmd_fis_len | n_elem << 16 | (qc->dev->link->pmp << 12);
cc9278ed
TH		 1892 if (qc->tf.flags & ATA_TFLAG_WRITE)
1893 opts |= AHCI_CMD_WRITE;
1894 if (is_atapi)
4b10e559 1895 opts |= AHCI_CMD_ATAPI | AHCI_CMD_PREFETCH;
828d09de 1896
12fad3f9 1897 ahci_fill_cmd_slot(pp, qc->tag, opts);
1da177e4
LT		 1898}
1899
78cd52d0 1900static void ahci_error_intr(struct ata_port *ap, u32 irq_stat)
1da177e4 1901{
417a1a6d 1902 struct ahci_host_priv *hpriv = ap->host->private_data;
78cd52d0 1903 struct ahci_port_priv *pp = ap->private_data;
7d50b60b
TH		 1904 struct ata_eh_info *host_ehi = &ap->link.eh_info;
1905 struct ata_link *link = NULL;
1906 struct ata_queued_cmd *active_qc;
1907 struct ata_eh_info *active_ehi;
78cd52d0 1908 u32 serror;
1da177e4 1909
7d50b60b
TH		 1910 /* determine active link */
1911 ata_port_for_each_link(link, ap)
1912 if (ata_link_active(link))
1913 break;
1914 if (!link)
1915 link = &ap->link;
1916
1917 active_qc = ata_qc_from_tag(ap, link->active_tag);
1918 active_ehi = &link->eh_info;
1919
1920 /* record irq stat */
1921 ata_ehi_clear_desc(host_ehi);
1922 ata_ehi_push_desc(host_ehi, "irq_stat 0x%08x", irq_stat);
1da177e4 1923
78cd52d0 1924 /* AHCI needs SError cleared; otherwise, it might lock up */
da3dbb17 1925 ahci_scr_read(ap, SCR_ERROR, &serror);
78cd52d0 1926 ahci_scr_write(ap, SCR_ERROR, serror);
7d50b60b 1927 host_ehi->serror |= serror;
78cd52d0 1928
41669553 1929 /* some controllers set IRQ_IF_ERR on device errors, ignore it */
417a1a6d 1930 if (hpriv->flags & AHCI_HFLAG_IGN_IRQ_IF_ERR)
41669553
TH		 1931 irq_stat &= ~PORT_IRQ_IF_ERR;
1932
55a61604 1933 if (irq_stat & PORT_IRQ_TF_ERR) {
7d50b60b
TH		 1934 /* If qc is active, charge it; otherwise, the active
1935 * link. There's no active qc on NCQ errors. It will
1936 * be determined by EH by reading log page 10h.
1937 */
1938 if (active_qc)
1939 active_qc->err_mask |= AC_ERR_DEV;
1940 else
1941 active_ehi->err_mask |= AC_ERR_DEV;
1942
417a1a6d 1943 if (hpriv->flags & AHCI_HFLAG_IGN_SERR_INTERNAL)
7d50b60b
TH		 1944 host_ehi->serror &= ~SERR_INTERNAL;
1945 }
1946
1947 if (irq_stat & PORT_IRQ_UNK_FIS) {
1948 u32 *unk = (u32 *)(pp->rx_fis + RX_FIS_UNK);
1949
1950 active_ehi->err_mask |= AC_ERR_HSM;
cf480626 1951 active_ehi->action |= ATA_EH_RESET;
7d50b60b
TH		 1952 ata_ehi_push_desc(active_ehi,
1953 "unknown FIS %08x %08x %08x %08x" ,
1954 unk[0], unk[1], unk[2], unk[3]);
1955 }
1956
071f44b1 1957 if (sata_pmp_attached(ap) && (irq_stat & PORT_IRQ_BAD_PMP)) {
7d50b60b 1958 active_ehi->err_mask |= AC_ERR_HSM;
cf480626 1959 active_ehi->action |= ATA_EH_RESET;
7d50b60b 1960 ata_ehi_push_desc(active_ehi, "incorrect PMP");
55a61604 1961 }
78cd52d0
TH		 1962
1963 if (irq_stat & (PORT_IRQ_HBUS_ERR | PORT_IRQ_HBUS_DATA_ERR)) {
7d50b60b 1964 host_ehi->err_mask |= AC_ERR_HOST_BUS;
cf480626 1965 host_ehi->action |= ATA_EH_RESET;
7d50b60b 1966 ata_ehi_push_desc(host_ehi, "host bus error");
1da177e4
LT		 1967 }
1968
78cd52d0 1969 if (irq_stat & PORT_IRQ_IF_ERR) {
7d50b60b 1970 host_ehi->err_mask |= AC_ERR_ATA_BUS;
cf480626 1971 host_ehi->action |= ATA_EH_RESET;
7d50b60b 1972 ata_ehi_push_desc(host_ehi, "interface fatal error");
78cd52d0 1973 }
1da177e4 1974
78cd52d0 1975 if (irq_stat & (PORT_IRQ_CONNECT | PORT_IRQ_PHYRDY)) {
7d50b60b
TH		 1976 ata_ehi_hotplugged(host_ehi);
1977 ata_ehi_push_desc(host_ehi, "%s",
1978 irq_stat & PORT_IRQ_CONNECT ?
78cd52d0
TH		 1979 "connection status changed" : "PHY RDY changed");
1980 }
1981
78cd52d0 1982 /* okay, let's hand over to EH */
a72ec4ce 1983
78cd52d0
TH		 1984 if (irq_stat & PORT_IRQ_FREEZE)
1985 ata_port_freeze(ap);
1986 else
1987 ata_port_abort(ap);
1da177e4
LT		 1988}
1989
df69c9c5 1990static void ahci_port_intr(struct ata_port *ap)
1da177e4 1991{
350756f6 1992 void __iomem *port_mmio = ahci_port_base(ap);
9af5c9c9 1993 struct ata_eh_info *ehi = &ap->link.eh_info;
0291f95f 1994 struct ahci_port_priv *pp = ap->private_data;
5f226c6b 1995 struct ahci_host_priv *hpriv = ap->host->private_data;
b06ce3e5 1996 int resetting = !!(ap->pflags & ATA_PFLAG_RESETTING);
12fad3f9 1997 u32 status, qc_active;
459ad688 1998 int rc;
1da177e4
LT		 1999
2000 status = readl(port_mmio + PORT_IRQ_STAT);
2001 writel(status, port_mmio + PORT_IRQ_STAT);
2002
b06ce3e5
TH		 2003 /* ignore BAD_PMP while resetting */
2004 if (unlikely(resetting))
2005 status &= ~PORT_IRQ_BAD_PMP;
2006
31556594
KCA		 2007 /* If we are getting PhyRdy, this is
2008 * just a power state change, we should
2009 * clear out this, plus the PhyRdy/Comm
2010 * Wake bits from Serror
2011 */
2012 if ((hpriv->flags & AHCI_HFLAG_NO_HOTPLUG) &&
2013 (status & PORT_IRQ_PHYRDY)) {
2014 status &= ~PORT_IRQ_PHYRDY;
2015 ahci_scr_write(ap, SCR_ERROR, ((1 << 16) | (1 << 18)));
2016 }
2017
78cd52d0
TH		 2018 if (unlikely(status & PORT_IRQ_ERROR)) {
2019 ahci_error_intr(ap, status);
2020 return;
1da177e4
LT		 2021 }
2022
2f294968 2023 if (status & PORT_IRQ_SDB_FIS) {
5f226c6b
TH		 2024 /* If SNotification is available, leave notification
2025 * handling to sata_async_notification(). If not,
2026 * emulate it by snooping SDB FIS RX area.
2027 *
2028 * Snooping FIS RX area is probably cheaper than
2029 * poking SNotification but some constrollers which
2030 * implement SNotification, ICH9 for example, don't
2031 * store AN SDB FIS into receive area.
2f294968 2032 */
5f226c6b 2033 if (hpriv->cap & HOST_CAP_SNTF)
7d77b247 2034 sata_async_notification(ap);
5f226c6b
TH		 2035 else {
2036 /* If the 'N' bit in word 0 of the FIS is set,
2037 * we just received asynchronous notification.
2038 * Tell libata about it.
2039 */
2040 const __le32 *f = pp->rx_fis + RX_FIS_SDB;
2041 u32 f0 = le32_to_cpu(f[0]);
2042
2043 if (f0 & (1 << 15))
2044 sata_async_notification(ap);
2045 }
2f294968
KCA		 2046 }
2047
7d50b60b
TH		 2048 /* pp->active_link is valid iff any command is in flight */
2049 if (ap->qc_active && pp->active_link->sactive)
12fad3f9
TH		 2050 qc_active = readl(port_mmio + PORT_SCR_ACT);
2051 else
2052 qc_active = readl(port_mmio + PORT_CMD_ISSUE);
2053
79f97dad 2054 rc = ata_qc_complete_multiple(ap, qc_active);
b06ce3e5 2055
459ad688
TH		 2056 /* while resetting, invalid completions are expected */
2057 if (unlikely(rc < 0 && !resetting)) {
12fad3f9 2058 ehi->err_mask |= AC_ERR_HSM;
cf480626 2059 ehi->action |= ATA_EH_RESET;
12fad3f9 2060 ata_port_freeze(ap);
1da177e4 2061 }
1da177e4
LT		 2062}
2063
7d12e780 2064static irqreturn_t ahci_interrupt(int irq, void *dev_instance)
1da177e4 2065{
cca3974e 2066 struct ata_host *host = dev_instance;
1da177e4
LT		 2067 struct ahci_host_priv *hpriv;
2068 unsigned int i, handled = 0;
ea6ba10b 2069 void __iomem *mmio;
d28f87aa 2070 u32 irq_stat, irq_masked;
1da177e4
LT		 2071
2072 VPRINTK("ENTER\n");
2073
cca3974e 2074 hpriv = host->private_data;
0d5ff566 2075 mmio = host->iomap[AHCI_PCI_BAR];
1da177e4
LT		 2076
2077 /* sigh. 0xffffffff is a valid return from h/w */
2078 irq_stat = readl(mmio + HOST_IRQ_STAT);
1da177e4
LT		 2079 if (!irq_stat)
2080 return IRQ_NONE;
2081
d28f87aa
TH		 2082 irq_masked = irq_stat & hpriv->port_map;
2083
2dcb407e 2084 spin_lock(&host->lock);
1da177e4 2085
2dcb407e 2086 for (i = 0; i < host->n_ports; i++) {
1da177e4 2087 struct ata_port *ap;
1da177e4 2088
d28f87aa 2089 if (!(irq_masked & (1 << i)))
67846b30
JG		 2090 continue;
2091
cca3974e 2092 ap = host->ports[i];
67846b30 2093 if (ap) {
df69c9c5 2094 ahci_port_intr(ap);
67846b30
JG		 2095 VPRINTK("port %u\n", i);
2096 } else {
2097 VPRINTK("port %u (no irq)\n", i);
6971ed1f 2098 if (ata_ratelimit())
cca3974e 2099 dev_printk(KERN_WARNING, host->dev,
a9524a76 2100 "interrupt on disabled port %u\n", i);
1da177e4 2101 }
67846b30 2102
1da177e4
LT		 2103 handled = 1;
2104 }
2105
d28f87aa
TH		 2106 /* HOST_IRQ_STAT behaves as level triggered latch meaning that
2107 * it should be cleared after all the port events are cleared;
2108 * otherwise, it will raise a spurious interrupt after each
2109 * valid one. Please read section 10.6.2 of ahci 1.1 for more
2110 * information.
2111 *
2112 * Also, use the unmasked value to clear interrupt as spurious
2113 * pending event on a dummy port might cause screaming IRQ.
2114 */
ea0c62f7
TH		 2115 writel(irq_stat, mmio + HOST_IRQ_STAT);
2116
cca3974e 2117 spin_unlock(&host->lock);
1da177e4
LT		 2118
2119 VPRINTK("EXIT\n");
2120
2121 return IRQ_RETVAL(handled);
2122}
2123
9a3d9eb0 2124static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc)
1da177e4
LT		 2125{
2126 struct ata_port *ap = qc->ap;
4447d351 2127 void __iomem *port_mmio = ahci_port_base(ap);
7d50b60b
TH		 2128 struct ahci_port_priv *pp = ap->private_data;
2129
2130 /* Keep track of the currently active link. It will be used
2131 * in completion path to determine whether NCQ phase is in
2132 * progress.
2133 */
2134 pp->active_link = qc->dev->link;
1da177e4 2135
12fad3f9
TH		 2136 if (qc->tf.protocol == ATA_PROT_NCQ)
2137 writel(1 << qc->tag, port_mmio + PORT_SCR_ACT);
2138 writel(1 << qc->tag, port_mmio + PORT_CMD_ISSUE);
1da177e4 2139
18f7ba4c
KCA		 2140 ahci_sw_activity(qc->dev->link);
2141
1da177e4
LT		 2142 return 0;
2143}
2144
4c9bf4e7
TH		 2145static bool ahci_qc_fill_rtf(struct ata_queued_cmd *qc)
2146{
2147 struct ahci_port_priv *pp = qc->ap->private_data;
2148 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
2149
2150 ata_tf_from_fis(d2h_fis, &qc->result_tf);
2151 return true;
2152}
2153
78cd52d0
TH		 2154static void ahci_freeze(struct ata_port *ap)
2155{
4447d351 2156 void __iomem *port_mmio = ahci_port_base(ap);
78cd52d0
TH		 2157
2158 /* turn IRQ off */
2159 writel(0, port_mmio + PORT_IRQ_MASK);
2160}
2161
2162static void ahci_thaw(struct ata_port *ap)
2163{
0d5ff566 2164 void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR];
4447d351 2165 void __iomem *port_mmio = ahci_port_base(ap);
78cd52d0 2166 u32 tmp;
a7384925 2167 struct ahci_port_priv *pp = ap->private_data;
78cd52d0
TH		 2168
2169 /* clear IRQ */
2170 tmp = readl(port_mmio + PORT_IRQ_STAT);
2171 writel(tmp, port_mmio + PORT_IRQ_STAT);
a718728f 2172 writel(1 << ap->port_no, mmio + HOST_IRQ_STAT);
78cd52d0 2173
1c954a4d
TH		 2174 /* turn IRQ back on */
2175 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
78cd52d0
TH		 2176}
2177
2178static void ahci_error_handler(struct ata_port *ap)
2179{
b51e9e5d 2180 if (!(ap->pflags & ATA_PFLAG_FROZEN)) {
78cd52d0 2181 /* restart engine */
4447d351
TH		 2182 ahci_stop_engine(ap);
2183 ahci_start_engine(ap);
78cd52d0
TH		 2184 }
2185
a1efdaba 2186 sata_pmp_error_handler(ap);
edc93052
TH		 2187}
2188
78cd52d0
TH		 2189static void ahci_post_internal_cmd(struct ata_queued_cmd *qc)
2190{
2191 struct ata_port *ap = qc->ap;
2192
d2e75dff
TH		 2193 /* make DMA engine forget about the failed command */
2194 if (qc->flags & ATA_QCFLAG_FAILED)
2195 ahci_kick_engine(ap, 1);
78cd52d0
TH		 2196}
2197
7d50b60b
TH		 2198static void ahci_pmp_attach(struct ata_port *ap)
2199{
2200 void __iomem *port_mmio = ahci_port_base(ap);
1c954a4d 2201 struct ahci_port_priv *pp = ap->private_data;
7d50b60b
TH		 2202 u32 cmd;
2203
2204 cmd = readl(port_mmio + PORT_CMD);
2205 cmd |= PORT_CMD_PMP;
2206 writel(cmd, port_mmio + PORT_CMD);
1c954a4d
TH		 2207
2208 pp->intr_mask |= PORT_IRQ_BAD_PMP;
2209 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
7d50b60b
TH		 2210}
2211
2212static void ahci_pmp_detach(struct ata_port *ap)
2213{
2214 void __iomem *port_mmio = ahci_port_base(ap);
1c954a4d 2215 struct ahci_port_priv *pp = ap->private_data;
7d50b60b
TH		 2216 u32 cmd;
2217
2218 cmd = readl(port_mmio + PORT_CMD);
2219 cmd &= ~PORT_CMD_PMP;
2220 writel(cmd, port_mmio + PORT_CMD);
1c954a4d
TH		 2221
2222 pp->intr_mask &= ~PORT_IRQ_BAD_PMP;
2223 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
7d50b60b
TH		 2224}
2225
028a2596
AD		 2226static int ahci_port_resume(struct ata_port *ap)
2227{
2228 ahci_power_up(ap);
2229 ahci_start_port(ap);
2230
071f44b1 2231 if (sata_pmp_attached(ap))
7d50b60b
TH		 2232 ahci_pmp_attach(ap);
2233 else
2234 ahci_pmp_detach(ap);
2235
028a2596
AD		 2236 return 0;
2237}
2238
438ac6d5 2239#ifdef CONFIG_PM
c1332875
TH		 2240static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg)
2241{
c1332875
TH		 2242 const char *emsg = NULL;
2243 int rc;
2244
4447d351 2245 rc = ahci_deinit_port(ap, &emsg);
8e16f941 2246 if (rc == 0)
4447d351 2247 ahci_power_down(ap);
8e16f941 2248 else {
c1332875 2249 ata_port_printk(ap, KERN_ERR, "%s (%d)\n", emsg, rc);
df69c9c5 2250 ahci_start_port(ap);
c1332875
TH		 2251 }
2252
2253 return rc;
2254}
2255
c1332875
TH		 2256static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg)
2257{
cca3974e 2258 struct ata_host *host = dev_get_drvdata(&pdev->dev);
0d5ff566 2259 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
c1332875
TH		 2260 u32 ctl;
2261
3a2d5b70 2262 if (mesg.event & PM_EVENT_SLEEP) {
c1332875
TH		 2263 /* AHCI spec rev1.1 section 8.3.3:
2264 * Software must disable interrupts prior to requesting a
2265 * transition of the HBA to D3 state.
2266 */
2267 ctl = readl(mmio + HOST_CTL);
2268 ctl &= ~HOST_IRQ_EN;
2269 writel(ctl, mmio + HOST_CTL);
2270 readl(mmio + HOST_CTL); /* flush */
2271 }
2272
2273 return ata_pci_device_suspend(pdev, mesg);
2274}
2275
2276static int ahci_pci_device_resume(struct pci_dev *pdev)
2277{
cca3974e 2278 struct ata_host *host = dev_get_drvdata(&pdev->dev);
c1332875
TH		 2279 int rc;
2280
553c4aa6
TH		 2281 rc = ata_pci_device_do_resume(pdev);
2282 if (rc)
2283 return rc;
c1332875
TH		 2284
2285 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
4447d351 2286 rc = ahci_reset_controller(host);
c1332875
TH		 2287 if (rc)
2288 return rc;
2289
4447d351 2290 ahci_init_controller(host);
c1332875
TH		 2291 }
2292
cca3974e 2293 ata_host_resume(host);
c1332875
TH		 2294
2295 return 0;
2296}
438ac6d5 2297#endif
c1332875 2298
254950cd
TH		 2299static int ahci_port_start(struct ata_port *ap)
2300{
cca3974e 2301 struct device *dev = ap->host->dev;
254950cd 2302 struct ahci_port_priv *pp;
254950cd
TH		 2303 void *mem;
2304 dma_addr_t mem_dma;
254950cd 2305
24dc5f33 2306 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
254950cd
TH		 2307 if (!pp)
2308 return -ENOMEM;
254950cd 2309
24dc5f33
TH		 2310 mem = dmam_alloc_coherent(dev, AHCI_PORT_PRIV_DMA_SZ, &mem_dma,
2311 GFP_KERNEL);
2312 if (!mem)
254950cd 2313 return -ENOMEM;
254950cd
TH		 2314 memset(mem, 0, AHCI_PORT_PRIV_DMA_SZ);
2315
2316 /*
2317 * First item in chunk of DMA memory: 32-slot command table,
2318 * 32 bytes each in size
2319 */
2320 pp->cmd_slot = mem;
2321 pp->cmd_slot_dma = mem_dma;
2322
2323 mem += AHCI_CMD_SLOT_SZ;
2324 mem_dma += AHCI_CMD_SLOT_SZ;
2325
2326 /*
2327 * Second item: Received-FIS area
2328 */
2329 pp->rx_fis = mem;
2330 pp->rx_fis_dma = mem_dma;
2331
2332 mem += AHCI_RX_FIS_SZ;
2333 mem_dma += AHCI_RX_FIS_SZ;
2334
2335 /*
2336 * Third item: data area for storing a single command
2337 * and its scatter-gather table
2338 */
2339 pp->cmd_tbl = mem;
2340 pp->cmd_tbl_dma = mem_dma;
2341
a7384925 2342 /*
2dcb407e
JG		 2343 * Save off initial list of interrupts to be enabled.
2344 * This could be changed later
2345 */
a7384925
KCA		 2346 pp->intr_mask = DEF_PORT_IRQ;
2347
254950cd
TH		 2348 ap->private_data = pp;
2349
df69c9c5
JG		 2350 /* engage engines, captain */
2351 return ahci_port_resume(ap);
254950cd
TH		 2352}
2353
2354static void ahci_port_stop(struct ata_port *ap)
2355{
0be0aa98
TH		 2356 const char *emsg = NULL;
2357 int rc;
254950cd 2358
0be0aa98 2359 /* de-initialize port */
4447d351 2360 rc = ahci_deinit_port(ap, &emsg);
0be0aa98
TH		 2361 if (rc)
2362 ata_port_printk(ap, KERN_WARNING, "%s (%d)\n", emsg, rc);
254950cd
TH		 2363}
2364
4447d351 2365static int ahci_configure_dma_masks(struct pci_dev *pdev, int using_dac)
1da177e4 2366{
1da177e4 2367 int rc;
1da177e4 2368
1da177e4
LT		 2369 if (using_dac &&
2370 !pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
2371 rc = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
2372 if (rc) {
2373 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
2374 if (rc) {
a9524a76
JG		 2375 dev_printk(KERN_ERR, &pdev->dev,
2376 "64-bit DMA enable failed\n");
1da177e4
LT		 2377 return rc;
2378 }
2379 }
1da177e4
LT		 2380 } else {
2381 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
2382 if (rc) {
a9524a76
JG		 2383 dev_printk(KERN_ERR, &pdev->dev,
2384 "32-bit DMA enable failed\n");
1da177e4
LT		 2385 return rc;
2386 }
2387 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
2388 if (rc) {
a9524a76
JG		 2389 dev_printk(KERN_ERR, &pdev->dev,
2390 "32-bit consistent DMA enable failed\n");
1da177e4
LT		 2391 return rc;
2392 }
2393 }
1da177e4
LT		 2394 return 0;
2395}
2396
4447d351 2397static void ahci_print_info(struct ata_host *host)
1da177e4 2398{
4447d351
TH		 2399 struct ahci_host_priv *hpriv = host->private_data;
2400 struct pci_dev *pdev = to_pci_dev(host->dev);
2401 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
1da177e4
LT		 2402 u32 vers, cap, impl, speed;
2403 const char *speed_s;
2404 u16 cc;
2405 const char *scc_s;
2406
2407 vers = readl(mmio + HOST_VERSION);
2408 cap = hpriv->cap;
2409 impl = hpriv->port_map;
2410
2411 speed = (cap >> 20) & 0xf;
2412 if (speed == 1)
2413 speed_s = "1.5";
2414 else if (speed == 2)
2415 speed_s = "3";
2416 else
2417 speed_s = "?";
2418
2419 pci_read_config_word(pdev, 0x0a, &cc);
c9f89475 2420 if (cc == PCI_CLASS_STORAGE_IDE)
1da177e4 2421 scc_s = "IDE";
c9f89475 2422 else if (cc == PCI_CLASS_STORAGE_SATA)
1da177e4 2423 scc_s = "SATA";
c9f89475 2424 else if (cc == PCI_CLASS_STORAGE_RAID)
1da177e4
LT		 2425 scc_s = "RAID";
2426 else
2427 scc_s = "unknown";
2428
a9524a76
JG		 2429 dev_printk(KERN_INFO, &pdev->dev,
2430 "AHCI %02x%02x.%02x%02x "
1da177e4 2431 "%u slots %u ports %s Gbps 0x%x impl %s mode\n"
2dcb407e 2432 ,
1da177e4 2433
2dcb407e
JG		 2434 (vers >> 24) & 0xff,
2435 (vers >> 16) & 0xff,
2436 (vers >> 8) & 0xff,
2437 vers & 0xff,
1da177e4
LT		 2438
2439 ((cap >> 8) & 0x1f) + 1,
2440 (cap & 0x1f) + 1,
2441 speed_s,
2442 impl,
2443 scc_s);
2444
a9524a76
JG		 2445 dev_printk(KERN_INFO, &pdev->dev,
2446 "flags: "
203ef6c4 2447 "%s%s%s%s%s%s%s"
18f7ba4c
KCA		 2448 "%s%s%s%s%s%s%s"
2449 "%s\n"
2dcb407e 2450 ,
1da177e4
LT		 2451
2452 cap & (1 << 31) ? "64bit " : "",
2453 cap & (1 << 30) ? "ncq " : "",
203ef6c4 2454 cap & (1 << 29) ? "sntf " : "",
1da177e4
LT		 2455 cap & (1 << 28) ? "ilck " : "",
2456 cap & (1 << 27) ? "stag " : "",
2457 cap & (1 << 26) ? "pm " : "",
2458 cap & (1 << 25) ? "led " : "",
2459
2460 cap & (1 << 24) ? "clo " : "",
2461 cap & (1 << 19) ? "nz " : "",
2462 cap & (1 << 18) ? "only " : "",
2463 cap & (1 << 17) ? "pmp " : "",
2464 cap & (1 << 15) ? "pio " : "",
2465 cap & (1 << 14) ? "slum " : "",
18f7ba4c
KCA		 2466 cap & (1 << 13) ? "part " : "",
2467 cap & (1 << 6) ? "ems ": ""
1da177e4
LT		 2468 );
2469}
2470
edc93052
TH		 2471/* On ASUS P5W DH Deluxe, the second port of PCI device 00:1f.2 is
2472 * hardwired to on-board SIMG 4726. The chipset is ICH8 and doesn't
2473 * support PMP and the 4726 either directly exports the device
2474 * attached to the first downstream port or acts as a hardware storage
2475 * controller and emulate a single ATA device (can be RAID 0/1 or some
2476 * other configuration).
2477 *
2478 * When there's no device attached to the first downstream port of the
2479 * 4726, "Config Disk" appears, which is a pseudo ATA device to
2480 * configure the 4726. However, ATA emulation of the device is very
2481 * lame. It doesn't send signature D2H Reg FIS after the initial
2482 * hardreset, pukes on SRST w/ PMP==0 and has bunch of other issues.
2483 *
2484 * The following function works around the problem by always using
2485 * hardreset on the port and not depending on receiving signature FIS
2486 * afterward. If signature FIS isn't received soon, ATA class is
2487 * assumed without follow-up softreset.
2488 */
2489static void ahci_p5wdh_workaround(struct ata_host *host)
2490{
2491 static struct dmi_system_id sysids[] = {
2492 {
2493 .ident = "P5W DH Deluxe",
2494 .matches = {
2495 DMI_MATCH(DMI_SYS_VENDOR,
2496 "ASUSTEK COMPUTER INC"),
2497 DMI_MATCH(DMI_PRODUCT_NAME, "P5W DH Deluxe"),
2498 },
2499 },
2500 { }
2501 };
2502 struct pci_dev *pdev = to_pci_dev(host->dev);
2503
2504 if (pdev->bus->number == 0 && pdev->devfn == PCI_DEVFN(0x1f, 2) &&
2505 dmi_check_system(sysids)) {
2506 struct ata_port *ap = host->ports[1];
2507
2508 dev_printk(KERN_INFO, &pdev->dev, "enabling ASUS P5W DH "
2509 "Deluxe on-board SIMG4726 workaround\n");
2510
2511 ap->ops = &ahci_p5wdh_ops;
2512 ap->link.flags |= ATA_LFLAG_NO_SRST | ATA_LFLAG_ASSUME_ATA;
2513 }
2514}
2515
24dc5f33 2516static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1da177e4
LT		 2517{
2518 static int printed_version;
e297d99e
TH		 2519 unsigned int board_id = ent->driver_data;
2520 struct ata_port_info pi = ahci_port_info[board_id];
4447d351 2521 const struct ata_port_info *ppi[] = { &pi, NULL };
24dc5f33 2522 struct device *dev = &pdev->dev;
1da177e4 2523 struct ahci_host_priv *hpriv;
4447d351 2524 struct ata_host *host;
837f5f8f 2525 int n_ports, i, rc;
1da177e4
LT		 2526
2527 VPRINTK("ENTER\n");
2528
12fad3f9
TH		 2529 WARN_ON(ATA_MAX_QUEUE > AHCI_MAX_CMDS);
2530
1da177e4 2531 if (!printed_version++)
a9524a76 2532 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
1da177e4 2533
4447d351 2534 /* acquire resources */
24dc5f33 2535 rc = pcim_enable_device(pdev);
1da177e4
LT		 2536 if (rc)
2537 return rc;
2538
dea55137
TH		 2539 /* AHCI controllers often implement SFF compatible interface.
2540 * Grab all PCI BARs just in case.
2541 */
2542 rc = pcim_iomap_regions_request_all(pdev, 1 << AHCI_PCI_BAR, DRV_NAME);
0d5ff566 2543 if (rc == -EBUSY)
24dc5f33 2544 pcim_pin_device(pdev);
0d5ff566 2545 if (rc)
24dc5f33 2546 return rc;
1da177e4 2547
c4f7792c
TH		 2548 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
2549 (pdev->device == 0x2652 || pdev->device == 0x2653)) {
2550 u8 map;
2551
2552 /* ICH6s share the same PCI ID for both piix and ahci
2553 * modes. Enabling ahci mode while MAP indicates
2554 * combined mode is a bad idea. Yield to ata_piix.
2555 */
2556 pci_read_config_byte(pdev, ICH_MAP, &map);
2557 if (map & 0x3) {
2558 dev_printk(KERN_INFO, &pdev->dev, "controller is in "
2559 "combined mode, can't enable AHCI mode\n");
2560 return -ENODEV;
2561 }
2562 }
2563
24dc5f33
TH		 2564 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
2565 if (!hpriv)
2566 return -ENOMEM;
417a1a6d
TH		 2567 hpriv->flags |= (unsigned long)pi.private_data;
2568
e297d99e
TH		 2569 /* MCP65 revision A1 and A2 can't do MSI */
2570 if (board_id == board_ahci_mcp65 &&
2571 (pdev->revision == 0xa1 || pdev->revision == 0xa2))
2572 hpriv->flags |= AHCI_HFLAG_NO_MSI;
2573
417a1a6d
TH		 2574 if ((hpriv->flags & AHCI_HFLAG_NO_MSI) || pci_enable_msi(pdev))
2575 pci_intx(pdev, 1);
1da177e4 2576
4447d351 2577 /* save initial config */
417a1a6d 2578 ahci_save_initial_config(pdev, hpriv);
1da177e4 2579
4447d351 2580 /* prepare host */
274c1fde 2581 if (hpriv->cap & HOST_CAP_NCQ)
4447d351 2582 pi.flags |= ATA_FLAG_NCQ;
1da177e4 2583
7d50b60b
TH		 2584 if (hpriv->cap & HOST_CAP_PMP)
2585 pi.flags |= ATA_FLAG_PMP;
2586
18f7ba4c
KCA		 2587 if (ahci_em_messages && (hpriv->cap & HOST_CAP_EMS)) {
2588 u8 messages;
2589 void __iomem *mmio = pcim_iomap_table(pdev)[AHCI_PCI_BAR];
2590 u32 em_loc = readl(mmio + HOST_EM_LOC);
2591 u32 em_ctl = readl(mmio + HOST_EM_CTL);
2592
2593 messages = (em_ctl & 0x000f0000) >> 16;
2594
2595 /* we only support LED message type right now */
2596 if ((messages & 0x01) && (ahci_em_messages == 1)) {
2597 /* store em_loc */
2598 hpriv->em_loc = ((em_loc >> 16) * 4);
2599 pi.flags |= ATA_FLAG_EM;
2600 if (!(em_ctl & EM_CTL_ALHD))
2601 pi.flags |= ATA_FLAG_SW_ACTIVITY;
2602 }
2603 }
2604
837f5f8f
TH		 2605 /* CAP.NP sometimes indicate the index of the last enabled
2606 * port, at other times, that of the last possible port, so
2607 * determining the maximum port number requires looking at
2608 * both CAP.NP and port_map.
2609 */
2610 n_ports = max(ahci_nr_ports(hpriv->cap), fls(hpriv->port_map));
2611
2612 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
4447d351
TH		 2613 if (!host)
2614 return -ENOMEM;
2615 host->iomap = pcim_iomap_table(pdev);
2616 host->private_data = hpriv;
2617
18f7ba4c
KCA		 2618 if (pi.flags & ATA_FLAG_EM)
2619 ahci_reset_em(host);
2620
4447d351 2621 for (i = 0; i < host->n_ports; i++) {
dab632e8 2622 struct ata_port *ap = host->ports[i];
4447d351 2623
cbcdd875
TH		 2624 ata_port_pbar_desc(ap, AHCI_PCI_BAR, -1, "abar");
2625 ata_port_pbar_desc(ap, AHCI_PCI_BAR,
2626 0x100 + ap->port_no * 0x80, "port");
2627
31556594
KCA		 2628 /* set initial link pm policy */
2629 ap->pm_policy = NOT_AVAILABLE;
2630
18f7ba4c
KCA		 2631 /* set enclosure management message type */
2632 if (ap->flags & ATA_FLAG_EM)
2633 ap->em_message_type = ahci_em_messages;
2634
2635
dab632e8 2636 /* disabled/not-implemented port */
350756f6 2637 if (!(hpriv->port_map & (1 << i)))
dab632e8 2638 ap->ops = &ata_dummy_port_ops;
4447d351 2639 }
d447df14 2640
edc93052
TH		 2641 /* apply workaround for ASUS P5W DH Deluxe mainboard */
2642 ahci_p5wdh_workaround(host);
2643
4447d351
TH		 2644 /* initialize adapter */
2645 rc = ahci_configure_dma_masks(pdev, hpriv->cap & HOST_CAP_64);
1da177e4 2646 if (rc)
24dc5f33 2647 return rc;
1da177e4 2648
4447d351
TH		 2649 rc = ahci_reset_controller(host);
2650 if (rc)
2651 return rc;
1da177e4 2652
4447d351
TH		 2653 ahci_init_controller(host);
2654 ahci_print_info(host);
1da177e4 2655
4447d351
TH		 2656 pci_set_master(pdev);
2657 return ata_host_activate(host, pdev->irq, ahci_interrupt, IRQF_SHARED,
2658 &ahci_sht);
907f4678 2659}
1da177e4
LT		 2660
2661static int __init ahci_init(void)
2662{
b7887196 2663 return pci_register_driver(&ahci_pci_driver);
1da177e4
LT		 2664}
2665
1da177e4
LT		 2666static void __exit ahci_exit(void)
2667{
2668 pci_unregister_driver(&ahci_pci_driver);
2669}
2670
2671
2672MODULE_AUTHOR("Jeff Garzik");
2673MODULE_DESCRIPTION("AHCI SATA low-level driver");
2674MODULE_LICENSE("GPL");
2675MODULE_DEVICE_TABLE(pci, ahci_pci_tbl);
6885433c 2676MODULE_VERSION(DRV_VERSION);
1da177e4
LT		 2677
2678module_init(ahci_init);
2679module_exit(ahci_exit);
Linux kernel - Deliverables
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