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IRQ: Typedef the IRQ handler function type
[deliverable/linux.git] / drivers / ata / ahci.c
CommitLineData
1da177e4
LT		 1/*
2 * ahci.c - AHCI SATA support
3 *
af36d7f0
JG		 4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
7 *
8 * Copyright 2004-2005 Red Hat, Inc.
9 *
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
24 *
25 *
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
28 *
29 * AHCI hardware documentation:
1da177e4 30 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
af36d7f0 31 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
1da177e4
LT		 32 *
33 */
34
35#include <linux/kernel.h>
36#include <linux/module.h>
37#include <linux/pci.h>
38#include <linux/init.h>
39#include <linux/blkdev.h>
40#include <linux/delay.h>
41#include <linux/interrupt.h>
42#include <linux/sched.h>
87507cfd 43#include <linux/dma-mapping.h>
a9524a76 44#include <linux/device.h>
1da177e4 45#include <scsi/scsi_host.h>
193515d5 46#include <scsi/scsi_cmnd.h>
1da177e4
LT		 47#include <linux/libata.h>
48#include <asm/io.h>
49
50#define DRV_NAME "ahci"
8676ce07 51#define DRV_VERSION "2.0"
1da177e4
LT		 52
53
54enum {
55 AHCI_PCI_BAR = 5,
56 AHCI_MAX_SG = 168, /* hardware max is 64K */
57 AHCI_DMA_BOUNDARY = 0xffffffff,
58 AHCI_USE_CLUSTERING = 0,
12fad3f9 59 AHCI_MAX_CMDS = 32,
dd410ff1 60 AHCI_CMD_SZ = 32,
12fad3f9 61 AHCI_CMD_SLOT_SZ = AHCI_MAX_CMDS * AHCI_CMD_SZ,
1da177e4 62 AHCI_RX_FIS_SZ = 256,
a0ea7328 63 AHCI_CMD_TBL_CDB = 0x40,
dd410ff1
TH		 64 AHCI_CMD_TBL_HDR_SZ = 0x80,
65 AHCI_CMD_TBL_SZ = AHCI_CMD_TBL_HDR_SZ + (AHCI_MAX_SG * 16),
66 AHCI_CMD_TBL_AR_SZ = AHCI_CMD_TBL_SZ * AHCI_MAX_CMDS,
67 AHCI_PORT_PRIV_DMA_SZ = AHCI_CMD_SLOT_SZ + AHCI_CMD_TBL_AR_SZ +
1da177e4
LT		 68 AHCI_RX_FIS_SZ,
69 AHCI_IRQ_ON_SG = (1 << 31),
70 AHCI_CMD_ATAPI = (1 << 5),
71 AHCI_CMD_WRITE = (1 << 6),
4b10e559 72 AHCI_CMD_PREFETCH = (1 << 7),
22b49985
TH		 73 AHCI_CMD_RESET = (1 << 8),
74 AHCI_CMD_CLR_BUSY = (1 << 10),
1da177e4
LT		 75
76 RX_FIS_D2H_REG = 0x40, /* offset of D2H Register FIS data */
78cd52d0 77 RX_FIS_UNK = 0x60, /* offset of Unknown FIS data */
1da177e4
LT		 78
79 board_ahci = 0,
bf2af2a2 80 board_ahci_vt8251 = 1,
1da177e4
LT		 81
82 /* global controller registers */
83 HOST_CAP = 0x00, /* host capabilities */
84 HOST_CTL = 0x04, /* global host control */
85 HOST_IRQ_STAT = 0x08, /* interrupt status */
86 HOST_PORTS_IMPL = 0x0c, /* bitmap of implemented ports */
87 HOST_VERSION = 0x10, /* AHCI spec. version compliancy */
88
89 /* HOST_CTL bits */
90 HOST_RESET = (1 << 0), /* reset controller; self-clear */
91 HOST_IRQ_EN = (1 << 1), /* global IRQ enable */
92 HOST_AHCI_EN = (1 << 31), /* AHCI enabled */
93
94 /* HOST_CAP bits */
0be0aa98 95 HOST_CAP_SSC = (1 << 14), /* Slumber capable */
22b49985 96 HOST_CAP_CLO = (1 << 24), /* Command List Override support */
0be0aa98 97 HOST_CAP_SSS = (1 << 27), /* Staggered Spin-up */
979db803 98 HOST_CAP_NCQ = (1 << 30), /* Native Command Queueing */
dd410ff1 99 HOST_CAP_64 = (1 << 31), /* PCI DAC (64-bit DMA) support */
1da177e4
LT		 100
101 /* registers for each SATA port */
102 PORT_LST_ADDR = 0x00, /* command list DMA addr */
103 PORT_LST_ADDR_HI = 0x04, /* command list DMA addr hi */
104 PORT_FIS_ADDR = 0x08, /* FIS rx buf addr */
105 PORT_FIS_ADDR_HI = 0x0c, /* FIS rx buf addr hi */
106 PORT_IRQ_STAT = 0x10, /* interrupt status */
107 PORT_IRQ_MASK = 0x14, /* interrupt enable/disable mask */
108 PORT_CMD = 0x18, /* port command */
109 PORT_TFDATA = 0x20, /* taskfile data */
110 PORT_SIG = 0x24, /* device TF signature */
111 PORT_CMD_ISSUE = 0x38, /* command issue */
112 PORT_SCR = 0x28, /* SATA phy register block */
113 PORT_SCR_STAT = 0x28, /* SATA phy register: SStatus */
114 PORT_SCR_CTL = 0x2c, /* SATA phy register: SControl */
115 PORT_SCR_ERR = 0x30, /* SATA phy register: SError */
116 PORT_SCR_ACT = 0x34, /* SATA phy register: SActive */
117
118 /* PORT_IRQ_{STAT,MASK} bits */
119 PORT_IRQ_COLD_PRES = (1 << 31), /* cold presence detect */
120 PORT_IRQ_TF_ERR = (1 << 30), /* task file error */
121 PORT_IRQ_HBUS_ERR = (1 << 29), /* host bus fatal error */
122 PORT_IRQ_HBUS_DATA_ERR = (1 << 28), /* host bus data error */
123 PORT_IRQ_IF_ERR = (1 << 27), /* interface fatal error */
124 PORT_IRQ_IF_NONFATAL = (1 << 26), /* interface non-fatal error */
125 PORT_IRQ_OVERFLOW = (1 << 24), /* xfer exhausted available S/G */
126 PORT_IRQ_BAD_PMP = (1 << 23), /* incorrect port multiplier */
127
128 PORT_IRQ_PHYRDY = (1 << 22), /* PhyRdy changed */
129 PORT_IRQ_DEV_ILCK = (1 << 7), /* device interlock */
130 PORT_IRQ_CONNECT = (1 << 6), /* port connect change status */
131 PORT_IRQ_SG_DONE = (1 << 5), /* descriptor processed */
132 PORT_IRQ_UNK_FIS = (1 << 4), /* unknown FIS rx'd */
133 PORT_IRQ_SDB_FIS = (1 << 3), /* Set Device Bits FIS rx'd */
134 PORT_IRQ_DMAS_FIS = (1 << 2), /* DMA Setup FIS rx'd */
135 PORT_IRQ_PIOS_FIS = (1 << 1), /* PIO Setup FIS rx'd */
136 PORT_IRQ_D2H_REG_FIS = (1 << 0), /* D2H Register FIS rx'd */
137
78cd52d0
TH		 138 PORT_IRQ_FREEZE = PORT_IRQ_HBUS_ERR |
139 PORT_IRQ_IF_ERR |
140 PORT_IRQ_CONNECT |
4296971d 141 PORT_IRQ_PHYRDY |
78cd52d0
TH		 142 PORT_IRQ_UNK_FIS,
143 PORT_IRQ_ERROR = PORT_IRQ_FREEZE |
144 PORT_IRQ_TF_ERR |
145 PORT_IRQ_HBUS_DATA_ERR,
146 DEF_PORT_IRQ = PORT_IRQ_ERROR | PORT_IRQ_SG_DONE |
147 PORT_IRQ_SDB_FIS | PORT_IRQ_DMAS_FIS |
148 PORT_IRQ_PIOS_FIS | PORT_IRQ_D2H_REG_FIS,
1da177e4
LT		 149
150 /* PORT_CMD bits */
02eaa666 151 PORT_CMD_ATAPI = (1 << 24), /* Device is ATAPI */
1da177e4
LT		 152 PORT_CMD_LIST_ON = (1 << 15), /* cmd list DMA engine running */
153 PORT_CMD_FIS_ON = (1 << 14), /* FIS DMA engine running */
154 PORT_CMD_FIS_RX = (1 << 4), /* Enable FIS receive DMA engine */
22b49985 155 PORT_CMD_CLO = (1 << 3), /* Command list override */
1da177e4
LT		 156 PORT_CMD_POWER_ON = (1 << 2), /* Power up device */
157 PORT_CMD_SPIN_UP = (1 << 1), /* Spin up device */
158 PORT_CMD_START = (1 << 0), /* Enable port DMA engine */
159
0be0aa98 160 PORT_CMD_ICC_MASK = (0xf << 28), /* i/f ICC state mask */
1da177e4
LT		 161 PORT_CMD_ICC_ACTIVE = (0x1 << 28), /* Put i/f in active state */
162 PORT_CMD_ICC_PARTIAL = (0x2 << 28), /* Put i/f in partial state */
163 PORT_CMD_ICC_SLUMBER = (0x6 << 28), /* Put i/f in slumber state */
4b0060f4
JG		 164
165 /* hpriv->flags bits */
166 AHCI_FLAG_MSI = (1 << 0),
bf2af2a2
BJ		 167
168 /* ap->flags bits */
169 AHCI_FLAG_RESET_NEEDS_CLO = (1 << 24),
71f0737b 170 AHCI_FLAG_NO_NCQ = (1 << 25),
1da177e4
LT		 171};
172
173struct ahci_cmd_hdr {
174 u32 opts;
175 u32 status;
176 u32 tbl_addr;
177 u32 tbl_addr_hi;
178 u32 reserved[4];
179};
180
181struct ahci_sg {
182 u32 addr;
183 u32 addr_hi;
184 u32 reserved;
185 u32 flags_size;
186};
187
188struct ahci_host_priv {
189 unsigned long flags;
190 u32 cap; /* cache of HOST_CAP register */
191 u32 port_map; /* cache of HOST_PORTS_IMPL reg */
192};
193
194struct ahci_port_priv {
195 struct ahci_cmd_hdr *cmd_slot;
196 dma_addr_t cmd_slot_dma;
197 void *cmd_tbl;
198 dma_addr_t cmd_tbl_dma;
1da177e4
LT		 199 void *rx_fis;
200 dma_addr_t rx_fis_dma;
201};
202
203static u32 ahci_scr_read (struct ata_port *ap, unsigned int sc_reg);
204static void ahci_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val);
205static int ahci_init_one (struct pci_dev *pdev, const struct pci_device_id *ent);
9a3d9eb0 206static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc);
1da177e4 207static irqreturn_t ahci_interrupt (int irq, void *dev_instance, struct pt_regs *regs);
1da177e4 208static void ahci_irq_clear(struct ata_port *ap);
1da177e4
LT		 209static int ahci_port_start(struct ata_port *ap);
210static void ahci_port_stop(struct ata_port *ap);
1da177e4
LT		 211static void ahci_tf_read(struct ata_port *ap, struct ata_taskfile *tf);
212static void ahci_qc_prep(struct ata_queued_cmd *qc);
213static u8 ahci_check_status(struct ata_port *ap);
78cd52d0
TH		 214static void ahci_freeze(struct ata_port *ap);
215static void ahci_thaw(struct ata_port *ap);
216static void ahci_error_handler(struct ata_port *ap);
217static void ahci_post_internal_cmd(struct ata_queued_cmd *qc);
c1332875
TH		 218static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg);
219static int ahci_port_resume(struct ata_port *ap);
220static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg);
221static int ahci_pci_device_resume(struct pci_dev *pdev);
907f4678 222static void ahci_remove_one (struct pci_dev *pdev);
1da177e4 223
193515d5 224static struct scsi_host_template ahci_sht = {
1da177e4
LT		 225 .module = THIS_MODULE,
226 .name = DRV_NAME,
227 .ioctl = ata_scsi_ioctl,
228 .queuecommand = ata_scsi_queuecmd,
12fad3f9
TH		 229 .change_queue_depth = ata_scsi_change_queue_depth,
230 .can_queue = AHCI_MAX_CMDS - 1,
1da177e4
LT		 231 .this_id = ATA_SHT_THIS_ID,
232 .sg_tablesize = AHCI_MAX_SG,
1da177e4
LT		 233 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
234 .emulated = ATA_SHT_EMULATED,
235 .use_clustering = AHCI_USE_CLUSTERING,
236 .proc_name = DRV_NAME,
237 .dma_boundary = AHCI_DMA_BOUNDARY,
238 .slave_configure = ata_scsi_slave_config,
ccf68c34 239 .slave_destroy = ata_scsi_slave_destroy,
1da177e4 240 .bios_param = ata_std_bios_param,
c1332875
TH		 241 .suspend = ata_scsi_device_suspend,
242 .resume = ata_scsi_device_resume,
1da177e4
LT		 243};
244
057ace5e 245static const struct ata_port_operations ahci_ops = {
1da177e4
LT		 246 .port_disable = ata_port_disable,
247
248 .check_status = ahci_check_status,
249 .check_altstatus = ahci_check_status,
1da177e4
LT		 250 .dev_select = ata_noop_dev_select,
251
252 .tf_read = ahci_tf_read,
253
1da177e4
LT		 254 .qc_prep = ahci_qc_prep,
255 .qc_issue = ahci_qc_issue,
256
1da177e4
LT		 257 .irq_handler = ahci_interrupt,
258 .irq_clear = ahci_irq_clear,
259
260 .scr_read = ahci_scr_read,
261 .scr_write = ahci_scr_write,
262
78cd52d0
TH		 263 .freeze = ahci_freeze,
264 .thaw = ahci_thaw,
265
266 .error_handler = ahci_error_handler,
267 .post_internal_cmd = ahci_post_internal_cmd,
268
c1332875
TH		 269 .port_suspend = ahci_port_suspend,
270 .port_resume = ahci_port_resume,
271
1da177e4
LT		 272 .port_start = ahci_port_start,
273 .port_stop = ahci_port_stop,
1da177e4
LT		 274};
275
98ac62de 276static const struct ata_port_info ahci_port_info[] = {
1da177e4
LT		 277 /* board_ahci */
278 {
279 .sht = &ahci_sht,
cca3974e 280 .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
4296971d
TH		 281 ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA |
282 ATA_FLAG_SKIP_D2H_BSY,
7da79312 283 .pio_mask = 0x1f, /* pio0-4 */
1da177e4
LT		 284 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
285 .port_ops = &ahci_ops,
286 },
bf2af2a2
BJ		 287 /* board_ahci_vt8251 */
288 {
289 .sht = &ahci_sht,
cca3974e 290 .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
bf2af2a2 291 ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA |
4296971d 292 ATA_FLAG_SKIP_D2H_BSY |
71f0737b 293 AHCI_FLAG_RESET_NEEDS_CLO | AHCI_FLAG_NO_NCQ,
bf2af2a2
BJ		 294 .pio_mask = 0x1f, /* pio0-4 */
295 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
296 .port_ops = &ahci_ops,
297 },
1da177e4
LT		 298};
299
3b7d697d 300static const struct pci_device_id ahci_pci_tbl[] = {
fe7fa31a 301 /* Intel */
54bb3a94
JG		 302 { PCI_VDEVICE(INTEL, 0x2652), board_ahci }, /* ICH6 */
303 { PCI_VDEVICE(INTEL, 0x2653), board_ahci }, /* ICH6M */
304 { PCI_VDEVICE(INTEL, 0x27c1), board_ahci }, /* ICH7 */
305 { PCI_VDEVICE(INTEL, 0x27c5), board_ahci }, /* ICH7M */
306 { PCI_VDEVICE(INTEL, 0x27c3), board_ahci }, /* ICH7R */
307 { PCI_VDEVICE(AL, 0x5288), board_ahci }, /* ULi M5288 */
308 { PCI_VDEVICE(INTEL, 0x2681), board_ahci }, /* ESB2 */
309 { PCI_VDEVICE(INTEL, 0x2682), board_ahci }, /* ESB2 */
310 { PCI_VDEVICE(INTEL, 0x2683), board_ahci }, /* ESB2 */
311 { PCI_VDEVICE(INTEL, 0x27c6), board_ahci }, /* ICH7-M DH */
312 { PCI_VDEVICE(INTEL, 0x2821), board_ahci }, /* ICH8 */
313 { PCI_VDEVICE(INTEL, 0x2822), board_ahci }, /* ICH8 */
314 { PCI_VDEVICE(INTEL, 0x2824), board_ahci }, /* ICH8 */
315 { PCI_VDEVICE(INTEL, 0x2829), board_ahci }, /* ICH8M */
316 { PCI_VDEVICE(INTEL, 0x282a), board_ahci }, /* ICH8M */
fe7fa31a
JG		 317
318 /* JMicron */
54bb3a94
JG		 319 { PCI_VDEVICE(JMICRON, 0x2360), board_ahci }, /* JMicron JMB360 */
320 { PCI_VDEVICE(JMICRON, 0x2361), board_ahci }, /* JMicron JMB361 */
321 { PCI_VDEVICE(JMICRON, 0x2363), board_ahci }, /* JMicron JMB363 */
322 { PCI_VDEVICE(JMICRON, 0x2365), board_ahci }, /* JMicron JMB365 */
323 { PCI_VDEVICE(JMICRON, 0x2366), board_ahci }, /* JMicron JMB366 */
fe7fa31a
JG		 324
325 /* ATI */
54bb3a94
JG		 326 { PCI_VDEVICE(ATI, 0x4380), board_ahci }, /* ATI SB600 non-raid */
327 { PCI_VDEVICE(ATI, 0x4381), board_ahci }, /* ATI SB600 raid */
fe7fa31a
JG		 328
329 /* VIA */
54bb3a94 330 { PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251 }, /* VIA VT8251 */
fe7fa31a
JG		 331
332 /* NVIDIA */
54bb3a94
JG		 333 { PCI_VDEVICE(NVIDIA, 0x044c), board_ahci }, /* MCP65 */
334 { PCI_VDEVICE(NVIDIA, 0x044d), board_ahci }, /* MCP65 */
335 { PCI_VDEVICE(NVIDIA, 0x044e), board_ahci }, /* MCP65 */
336 { PCI_VDEVICE(NVIDIA, 0x044f), board_ahci }, /* MCP65 */
fe7fa31a 337
95916edd 338 /* SiS */
54bb3a94
JG		 339 { PCI_VDEVICE(SI, 0x1184), board_ahci }, /* SiS 966 */
340 { PCI_VDEVICE(SI, 0x1185), board_ahci }, /* SiS 966 */
341 { PCI_VDEVICE(SI, 0x0186), board_ahci }, /* SiS 968 */
95916edd 342
1da177e4
LT		 343 { } /* terminate list */
344};
345
346
347static struct pci_driver ahci_pci_driver = {
348 .name = DRV_NAME,
349 .id_table = ahci_pci_tbl,
350 .probe = ahci_init_one,
c1332875
TH		 351 .suspend = ahci_pci_device_suspend,
352 .resume = ahci_pci_device_resume,
907f4678 353 .remove = ahci_remove_one,
1da177e4
LT		 354};
355
356
357static inline unsigned long ahci_port_base_ul (unsigned long base, unsigned int port)
358{
359 return base + 0x100 + (port * 0x80);
360}
361
ea6ba10b 362static inline void __iomem *ahci_port_base (void __iomem *base, unsigned int port)
1da177e4 363{
ea6ba10b 364 return (void __iomem *) ahci_port_base_ul((unsigned long)base, port);
1da177e4
LT		 365}
366
1da177e4
LT		 367static u32 ahci_scr_read (struct ata_port *ap, unsigned int sc_reg_in)
368{
369 unsigned int sc_reg;
370
371 switch (sc_reg_in) {
372 case SCR_STATUS: sc_reg = 0; break;
373 case SCR_CONTROL: sc_reg = 1; break;
374 case SCR_ERROR: sc_reg = 2; break;
375 case SCR_ACTIVE: sc_reg = 3; break;
376 default:
377 return 0xffffffffU;
378 }
379
1e4f2a96 380 return readl((void __iomem *) ap->ioaddr.scr_addr + (sc_reg * 4));
1da177e4
LT		 381}
382
383
384static void ahci_scr_write (struct ata_port *ap, unsigned int sc_reg_in,
385 u32 val)
386{
387 unsigned int sc_reg;
388
389 switch (sc_reg_in) {
390 case SCR_STATUS: sc_reg = 0; break;
391 case SCR_CONTROL: sc_reg = 1; break;
392 case SCR_ERROR: sc_reg = 2; break;
393 case SCR_ACTIVE: sc_reg = 3; break;
394 default:
395 return;
396 }
397
1e4f2a96 398 writel(val, (void __iomem *) ap->ioaddr.scr_addr + (sc_reg * 4));
1da177e4
LT		 399}
400
9f592056 401static void ahci_start_engine(void __iomem *port_mmio)
7c76d1e8 402{
7c76d1e8
TH		 403 u32 tmp;
404
d8fcd116 405 /* start DMA */
9f592056 406 tmp = readl(port_mmio + PORT_CMD);
7c76d1e8
TH		 407 tmp |= PORT_CMD_START;
408 writel(tmp, port_mmio + PORT_CMD);
409 readl(port_mmio + PORT_CMD); /* flush */
410}
411
254950cd
TH		 412static int ahci_stop_engine(void __iomem *port_mmio)
413{
414 u32 tmp;
415
416 tmp = readl(port_mmio + PORT_CMD);
417
d8fcd116 418 /* check if the HBA is idle */
254950cd
TH		 419 if ((tmp & (PORT_CMD_START | PORT_CMD_LIST_ON)) == 0)
420 return 0;
421
d8fcd116 422 /* setting HBA to idle */
254950cd
TH		 423 tmp &= ~PORT_CMD_START;
424 writel(tmp, port_mmio + PORT_CMD);
425
d8fcd116 426 /* wait for engine to stop. This could be as long as 500 msec */
254950cd
TH		 427 tmp = ata_wait_register(port_mmio + PORT_CMD,
428 PORT_CMD_LIST_ON, PORT_CMD_LIST_ON, 1, 500);
d8fcd116 429 if (tmp & PORT_CMD_LIST_ON)
254950cd
TH		 430 return -EIO;
431
432 return 0;
433}
434
0be0aa98
TH		 435static void ahci_start_fis_rx(void __iomem *port_mmio, u32 cap,
436 dma_addr_t cmd_slot_dma, dma_addr_t rx_fis_dma)
437{
438 u32 tmp;
439
440 /* set FIS registers */
441 if (cap & HOST_CAP_64)
442 writel((cmd_slot_dma >> 16) >> 16, port_mmio + PORT_LST_ADDR_HI);
443 writel(cmd_slot_dma & 0xffffffff, port_mmio + PORT_LST_ADDR);
444
445 if (cap & HOST_CAP_64)
446 writel((rx_fis_dma >> 16) >> 16, port_mmio + PORT_FIS_ADDR_HI);
447 writel(rx_fis_dma & 0xffffffff, port_mmio + PORT_FIS_ADDR);
448
449 /* enable FIS reception */
450 tmp = readl(port_mmio + PORT_CMD);
451 tmp |= PORT_CMD_FIS_RX;
452 writel(tmp, port_mmio + PORT_CMD);
453
454 /* flush */
455 readl(port_mmio + PORT_CMD);
456}
457
458static int ahci_stop_fis_rx(void __iomem *port_mmio)
459{
460 u32 tmp;
461
462 /* disable FIS reception */
463 tmp = readl(port_mmio + PORT_CMD);
464 tmp &= ~PORT_CMD_FIS_RX;
465 writel(tmp, port_mmio + PORT_CMD);
466
467 /* wait for completion, spec says 500ms, give it 1000 */
468 tmp = ata_wait_register(port_mmio + PORT_CMD, PORT_CMD_FIS_ON,
469 PORT_CMD_FIS_ON, 10, 1000);
470 if (tmp & PORT_CMD_FIS_ON)
471 return -EBUSY;
472
473 return 0;
474}
475
476static void ahci_power_up(void __iomem *port_mmio, u32 cap)
477{
478 u32 cmd;
479
480 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
481
482 /* spin up device */
483 if (cap & HOST_CAP_SSS) {
484 cmd |= PORT_CMD_SPIN_UP;
485 writel(cmd, port_mmio + PORT_CMD);
486 }
487
488 /* wake up link */
489 writel(cmd | PORT_CMD_ICC_ACTIVE, port_mmio + PORT_CMD);
490}
491
492static void ahci_power_down(void __iomem *port_mmio, u32 cap)
493{
494 u32 cmd, scontrol;
495
496 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
497
498 if (cap & HOST_CAP_SSC) {
499 /* enable transitions to slumber mode */
500 scontrol = readl(port_mmio + PORT_SCR_CTL);
501 if ((scontrol & 0x0f00) > 0x100) {
502 scontrol &= ~0xf00;
503 writel(scontrol, port_mmio + PORT_SCR_CTL);
504 }
505
506 /* put device into slumber mode */
507 writel(cmd | PORT_CMD_ICC_SLUMBER, port_mmio + PORT_CMD);
508
509 /* wait for the transition to complete */
510 ata_wait_register(port_mmio + PORT_CMD, PORT_CMD_ICC_SLUMBER,
511 PORT_CMD_ICC_SLUMBER, 1, 50);
512 }
513
514 /* put device into listen mode */
515 if (cap & HOST_CAP_SSS) {
516 /* first set PxSCTL.DET to 0 */
517 scontrol = readl(port_mmio + PORT_SCR_CTL);
518 scontrol &= ~0xf;
519 writel(scontrol, port_mmio + PORT_SCR_CTL);
520
521 /* then set PxCMD.SUD to 0 */
522 cmd &= ~PORT_CMD_SPIN_UP;
523 writel(cmd, port_mmio + PORT_CMD);
524 }
525}
526
527static void ahci_init_port(void __iomem *port_mmio, u32 cap,
528 dma_addr_t cmd_slot_dma, dma_addr_t rx_fis_dma)
529{
530 /* power up */
531 ahci_power_up(port_mmio, cap);
532
533 /* enable FIS reception */
534 ahci_start_fis_rx(port_mmio, cap, cmd_slot_dma, rx_fis_dma);
535
536 /* enable DMA */
537 ahci_start_engine(port_mmio);
538}
539
540static int ahci_deinit_port(void __iomem *port_mmio, u32 cap, const char **emsg)
541{
542 int rc;
543
544 /* disable DMA */
545 rc = ahci_stop_engine(port_mmio);
546 if (rc) {
547 *emsg = "failed to stop engine";
548 return rc;
549 }
550
551 /* disable FIS reception */
552 rc = ahci_stop_fis_rx(port_mmio);
553 if (rc) {
554 *emsg = "failed stop FIS RX";
555 return rc;
556 }
557
558 /* put device into slumber mode */
559 ahci_power_down(port_mmio, cap);
560
561 return 0;
562}
563
d91542c1
TH		 564static int ahci_reset_controller(void __iomem *mmio, struct pci_dev *pdev)
565{
566 u32 cap_save, tmp;
567
568 cap_save = readl(mmio + HOST_CAP);
569 cap_save &= ( (1<<28) | (1<<17) );
570 cap_save |= (1 << 27);
571
572 /* global controller reset */
573 tmp = readl(mmio + HOST_CTL);
574 if ((tmp & HOST_RESET) == 0) {
575 writel(tmp | HOST_RESET, mmio + HOST_CTL);
576 readl(mmio + HOST_CTL); /* flush */
577 }
578
579 /* reset must complete within 1 second, or
580 * the hardware should be considered fried.
581 */
582 ssleep(1);
583
584 tmp = readl(mmio + HOST_CTL);
585 if (tmp & HOST_RESET) {
586 dev_printk(KERN_ERR, &pdev->dev,
587 "controller reset failed (0x%x)\n", tmp);
588 return -EIO;
589 }
590
591 writel(HOST_AHCI_EN, mmio + HOST_CTL);
592 (void) readl(mmio + HOST_CTL); /* flush */
593 writel(cap_save, mmio + HOST_CAP);
594 writel(0xf, mmio + HOST_PORTS_IMPL);
595 (void) readl(mmio + HOST_PORTS_IMPL); /* flush */
596
597 if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
598 u16 tmp16;
599
600 /* configure PCS */
601 pci_read_config_word(pdev, 0x92, &tmp16);
602 tmp16 |= 0xf;
603 pci_write_config_word(pdev, 0x92, tmp16);
604 }
605
606 return 0;
607}
608
609static void ahci_init_controller(void __iomem *mmio, struct pci_dev *pdev,
610 int n_ports, u32 cap)
611{
612 int i, rc;
613 u32 tmp;
614
615 for (i = 0; i < n_ports; i++) {
616 void __iomem *port_mmio = ahci_port_base(mmio, i);
617 const char *emsg = NULL;
618
619#if 0 /* BIOSen initialize this incorrectly */
620 if (!(hpriv->port_map & (1 << i)))
621 continue;
622#endif
623
624 /* make sure port is not active */
625 rc = ahci_deinit_port(port_mmio, cap, &emsg);
626 if (rc)
627 dev_printk(KERN_WARNING, &pdev->dev,
628 "%s (%d)\n", emsg, rc);
629
630 /* clear SError */
631 tmp = readl(port_mmio + PORT_SCR_ERR);
632 VPRINTK("PORT_SCR_ERR 0x%x\n", tmp);
633 writel(tmp, port_mmio + PORT_SCR_ERR);
634
f4b5cc87 635 /* clear port IRQ */
d91542c1
TH		 636 tmp = readl(port_mmio + PORT_IRQ_STAT);
637 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
638 if (tmp)
639 writel(tmp, port_mmio + PORT_IRQ_STAT);
640
641 writel(1 << i, mmio + HOST_IRQ_STAT);
d91542c1
TH		 642 }
643
644 tmp = readl(mmio + HOST_CTL);
645 VPRINTK("HOST_CTL 0x%x\n", tmp);
646 writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL);
647 tmp = readl(mmio + HOST_CTL);
648 VPRINTK("HOST_CTL 0x%x\n", tmp);
649}
650
422b7595 651static unsigned int ahci_dev_classify(struct ata_port *ap)
1da177e4
LT		 652{
653 void __iomem *port_mmio = (void __iomem *) ap->ioaddr.cmd_addr;
654 struct ata_taskfile tf;
422b7595
TH		 655 u32 tmp;
656
657 tmp = readl(port_mmio + PORT_SIG);
658 tf.lbah = (tmp >> 24) & 0xff;
659 tf.lbam = (tmp >> 16) & 0xff;
660 tf.lbal = (tmp >> 8) & 0xff;
661 tf.nsect = (tmp) & 0xff;
662
663 return ata_dev_classify(&tf);
664}
665
12fad3f9
TH		 666static void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag,
667 u32 opts)
cc9278ed 668{
12fad3f9
TH		 669 dma_addr_t cmd_tbl_dma;
670
671 cmd_tbl_dma = pp->cmd_tbl_dma + tag * AHCI_CMD_TBL_SZ;
672
673 pp->cmd_slot[tag].opts = cpu_to_le32(opts);
674 pp->cmd_slot[tag].status = 0;
675 pp->cmd_slot[tag].tbl_addr = cpu_to_le32(cmd_tbl_dma & 0xffffffff);
676 pp->cmd_slot[tag].tbl_addr_hi = cpu_to_le32((cmd_tbl_dma >> 16) >> 16);
cc9278ed
TH		 677}
678
bf2af2a2 679static int ahci_clo(struct ata_port *ap)
4658f79b 680{
bf2af2a2 681 void __iomem *port_mmio = (void __iomem *) ap->ioaddr.cmd_addr;
cca3974e 682 struct ahci_host_priv *hpriv = ap->host->private_data;
bf2af2a2
BJ		 683 u32 tmp;
684
685 if (!(hpriv->cap & HOST_CAP_CLO))
686 return -EOPNOTSUPP;
687
688 tmp = readl(port_mmio + PORT_CMD);
689 tmp |= PORT_CMD_CLO;
690 writel(tmp, port_mmio + PORT_CMD);
691
692 tmp = ata_wait_register(port_mmio + PORT_CMD,
693 PORT_CMD_CLO, PORT_CMD_CLO, 1, 500);
694 if (tmp & PORT_CMD_CLO)
695 return -EIO;
696
697 return 0;
698}
699
4296971d
TH		 700static int ahci_prereset(struct ata_port *ap)
701{
702 if ((ap->flags & AHCI_FLAG_RESET_NEEDS_CLO) &&
703 (ata_busy_wait(ap, ATA_BUSY, 1000) & ATA_BUSY)) {
704 /* ATA_BUSY hasn't cleared, so send a CLO */
705 ahci_clo(ap);
706 }
707
708 return ata_std_prereset(ap);
709}
710
bf2af2a2
BJ		 711static int ahci_softreset(struct ata_port *ap, unsigned int *class)
712{
4658f79b 713 struct ahci_port_priv *pp = ap->private_data;
cca3974e 714 void __iomem *mmio = ap->host->mmio_base;
4658f79b
TH		 715 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
716 const u32 cmd_fis_len = 5; /* five dwords */
717 const char *reason = NULL;
718 struct ata_taskfile tf;
75fe1806 719 u32 tmp;
4658f79b
TH		 720 u8 *fis;
721 int rc;
722
723 DPRINTK("ENTER\n");
724
81952c54 725 if (ata_port_offline(ap)) {
c2a65852
TH		 726 DPRINTK("PHY reports no device\n");
727 *class = ATA_DEV_NONE;
728 return 0;
729 }
730
4658f79b 731 /* prepare for SRST (AHCI-1.1 10.4.1) */
5457f219 732 rc = ahci_stop_engine(port_mmio);
4658f79b
TH		 733 if (rc) {
734 reason = "failed to stop engine";
735 goto fail_restart;
736 }
737
738 /* check BUSY/DRQ, perform Command List Override if necessary */
739 ahci_tf_read(ap, &tf);
740 if (tf.command & (ATA_BUSY | ATA_DRQ)) {
bf2af2a2 741 rc = ahci_clo(ap);
4658f79b 742
bf2af2a2
BJ		 743 if (rc == -EOPNOTSUPP) {
744 reason = "port busy but CLO unavailable";
745 goto fail_restart;
746 } else if (rc) {
747 reason = "port busy but CLO failed";
4658f79b
TH		 748 goto fail_restart;
749 }
750 }
751
752 /* restart engine */
5457f219 753 ahci_start_engine(port_mmio);
4658f79b 754
3373efd8 755 ata_tf_init(ap->device, &tf);
4658f79b
TH		 756 fis = pp->cmd_tbl;
757
758 /* issue the first D2H Register FIS */
12fad3f9
TH		 759 ahci_fill_cmd_slot(pp, 0,
760 cmd_fis_len | AHCI_CMD_RESET | AHCI_CMD_CLR_BUSY);
4658f79b
TH		 761
762 tf.ctl |= ATA_SRST;
763 ata_tf_to_fis(&tf, fis, 0);
764 fis[1] &= ~(1 << 7); /* turn off Command FIS bit */
765
766 writel(1, port_mmio + PORT_CMD_ISSUE);
4658f79b 767
75fe1806
TH		 768 tmp = ata_wait_register(port_mmio + PORT_CMD_ISSUE, 0x1, 0x1, 1, 500);
769 if (tmp & 0x1) {
4658f79b
TH		 770 rc = -EIO;
771 reason = "1st FIS failed";
772 goto fail;
773 }
774
775 /* spec says at least 5us, but be generous and sleep for 1ms */
776 msleep(1);
777
778 /* issue the second D2H Register FIS */
12fad3f9 779 ahci_fill_cmd_slot(pp, 0, cmd_fis_len);
4658f79b
TH		 780
781 tf.ctl &= ~ATA_SRST;
782 ata_tf_to_fis(&tf, fis, 0);
783 fis[1] &= ~(1 << 7); /* turn off Command FIS bit */
784
785 writel(1, port_mmio + PORT_CMD_ISSUE);
786 readl(port_mmio + PORT_CMD_ISSUE); /* flush */
787
788 /* spec mandates ">= 2ms" before checking status.
789 * We wait 150ms, because that was the magic delay used for
790 * ATAPI devices in Hale Landis's ATADRVR, for the period of time
791 * between when the ATA command register is written, and then
792 * status is checked. Because waiting for "a while" before
793 * checking status is fine, post SRST, we perform this magic
794 * delay here as well.
795 */
796 msleep(150);
797
798 *class = ATA_DEV_NONE;
81952c54 799 if (ata_port_online(ap)) {
4658f79b
TH		 800 if (ata_busy_sleep(ap, ATA_TMOUT_BOOT_QUICK, ATA_TMOUT_BOOT)) {
801 rc = -EIO;
802 reason = "device not ready";
803 goto fail;
804 }
805 *class = ahci_dev_classify(ap);
806 }
807
808 DPRINTK("EXIT, class=%u\n", *class);
809 return 0;
810
811 fail_restart:
5457f219 812 ahci_start_engine(port_mmio);
4658f79b 813 fail:
f15a1daf 814 ata_port_printk(ap, KERN_ERR, "softreset failed (%s)\n", reason);
4658f79b
TH		 815 return rc;
816}
817
2bf2cb26 818static int ahci_hardreset(struct ata_port *ap, unsigned int *class)
422b7595 819{
4296971d
TH		 820 struct ahci_port_priv *pp = ap->private_data;
821 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
822 struct ata_taskfile tf;
cca3974e 823 void __iomem *mmio = ap->host->mmio_base;
5457f219 824 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
4bd00f6a
TH		 825 int rc;
826
827 DPRINTK("ENTER\n");
1da177e4 828
5457f219 829 ahci_stop_engine(port_mmio);
4296971d
TH		 830
831 /* clear D2H reception area to properly wait for D2H FIS */
832 ata_tf_init(ap->device, &tf);
833 tf.command = 0xff;
834 ata_tf_to_fis(&tf, d2h_fis, 0);
835
2bf2cb26 836 rc = sata_std_hardreset(ap, class);
4296971d 837
5457f219 838 ahci_start_engine(port_mmio);
1da177e4 839
81952c54 840 if (rc == 0 && ata_port_online(ap))
4bd00f6a
TH		 841 *class = ahci_dev_classify(ap);
842 if (*class == ATA_DEV_UNKNOWN)
843 *class = ATA_DEV_NONE;
1da177e4 844
4bd00f6a
TH		 845 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
846 return rc;
847}
848
849static void ahci_postreset(struct ata_port *ap, unsigned int *class)
850{
851 void __iomem *port_mmio = (void __iomem *) ap->ioaddr.cmd_addr;
852 u32 new_tmp, tmp;
853
854 ata_std_postreset(ap, class);
02eaa666
JG		 855
856 /* Make sure port's ATAPI bit is set appropriately */
857 new_tmp = tmp = readl(port_mmio + PORT_CMD);
4bd00f6a 858 if (*class == ATA_DEV_ATAPI)
02eaa666
JG		 859 new_tmp |= PORT_CMD_ATAPI;
860 else
861 new_tmp &= ~PORT_CMD_ATAPI;
862 if (new_tmp != tmp) {
863 writel(new_tmp, port_mmio + PORT_CMD);
864 readl(port_mmio + PORT_CMD); /* flush */
865 }
1da177e4
LT		 866}
867
868static u8 ahci_check_status(struct ata_port *ap)
869{
1e4f2a96 870 void __iomem *mmio = (void __iomem *) ap->ioaddr.cmd_addr;
1da177e4
LT		 871
872 return readl(mmio + PORT_TFDATA) & 0xFF;
873}
874
1da177e4
LT		 875static void ahci_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
876{
877 struct ahci_port_priv *pp = ap->private_data;
878 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
879
880 ata_tf_from_fis(d2h_fis, tf);
881}
882
12fad3f9 883static unsigned int ahci_fill_sg(struct ata_queued_cmd *qc, void *cmd_tbl)
1da177e4 884{
cedc9a47
JG		 885 struct scatterlist *sg;
886 struct ahci_sg *ahci_sg;
828d09de 887 unsigned int n_sg = 0;
1da177e4
LT		 888
889 VPRINTK("ENTER\n");
890
891 /*
892 * Next, the S/G list.
893 */
12fad3f9 894 ahci_sg = cmd_tbl + AHCI_CMD_TBL_HDR_SZ;
cedc9a47
JG		 895 ata_for_each_sg(sg, qc) {
896 dma_addr_t addr = sg_dma_address(sg);
897 u32 sg_len = sg_dma_len(sg);
898
899 ahci_sg->addr = cpu_to_le32(addr & 0xffffffff);
900 ahci_sg->addr_hi = cpu_to_le32((addr >> 16) >> 16);
901 ahci_sg->flags_size = cpu_to_le32(sg_len - 1);
828d09de 902
cedc9a47 903 ahci_sg++;
828d09de 904 n_sg++;
1da177e4 905 }
828d09de
JG		 906
907 return n_sg;
1da177e4
LT		 908}
909
910static void ahci_qc_prep(struct ata_queued_cmd *qc)
911{
a0ea7328
JG		 912 struct ata_port *ap = qc->ap;
913 struct ahci_port_priv *pp = ap->private_data;
cc9278ed 914 int is_atapi = is_atapi_taskfile(&qc->tf);
12fad3f9 915 void *cmd_tbl;
1da177e4
LT		 916 u32 opts;
917 const u32 cmd_fis_len = 5; /* five dwords */
828d09de 918 unsigned int n_elem;
1da177e4 919
1da177e4
LT		 920 /*
921 * Fill in command table information. First, the header,
922 * a SATA Register - Host to Device command FIS.
923 */
12fad3f9
TH		 924 cmd_tbl = pp->cmd_tbl + qc->tag * AHCI_CMD_TBL_SZ;
925
926 ata_tf_to_fis(&qc->tf, cmd_tbl, 0);
cc9278ed 927 if (is_atapi) {
12fad3f9
TH		 928 memset(cmd_tbl + AHCI_CMD_TBL_CDB, 0, 32);
929 memcpy(cmd_tbl + AHCI_CMD_TBL_CDB, qc->cdb, qc->dev->cdb_len);
a0ea7328 930 }
1da177e4 931
cc9278ed
TH		 932 n_elem = 0;
933 if (qc->flags & ATA_QCFLAG_DMAMAP)
12fad3f9 934 n_elem = ahci_fill_sg(qc, cmd_tbl);
1da177e4 935
cc9278ed
TH		 936 /*
937 * Fill in command slot information.
938 */
939 opts = cmd_fis_len | n_elem << 16;
940 if (qc->tf.flags & ATA_TFLAG_WRITE)
941 opts |= AHCI_CMD_WRITE;
942 if (is_atapi)
4b10e559 943 opts |= AHCI_CMD_ATAPI | AHCI_CMD_PREFETCH;
828d09de 944
12fad3f9 945 ahci_fill_cmd_slot(pp, qc->tag, opts);
1da177e4
LT		 946}
947
78cd52d0 948static void ahci_error_intr(struct ata_port *ap, u32 irq_stat)
1da177e4 949{
78cd52d0
TH		 950 struct ahci_port_priv *pp = ap->private_data;
951 struct ata_eh_info *ehi = &ap->eh_info;
952 unsigned int err_mask = 0, action = 0;
953 struct ata_queued_cmd *qc;
954 u32 serror;
1da177e4 955
78cd52d0 956 ata_ehi_clear_desc(ehi);
1da177e4 957
78cd52d0
TH		 958 /* AHCI needs SError cleared; otherwise, it might lock up */
959 serror = ahci_scr_read(ap, SCR_ERROR);
960 ahci_scr_write(ap, SCR_ERROR, serror);
1da177e4 961
78cd52d0
TH		 962 /* analyze @irq_stat */
963 ata_ehi_push_desc(ehi, "irq_stat 0x%08x", irq_stat);
964
965 if (irq_stat & PORT_IRQ_TF_ERR)
966 err_mask |= AC_ERR_DEV;
967
968 if (irq_stat & (PORT_IRQ_HBUS_ERR | PORT_IRQ_HBUS_DATA_ERR)) {
969 err_mask |= AC_ERR_HOST_BUS;
970 action |= ATA_EH_SOFTRESET;
1da177e4
LT		 971 }
972
78cd52d0
TH		 973 if (irq_stat & PORT_IRQ_IF_ERR) {
974 err_mask |= AC_ERR_ATA_BUS;
975 action |= ATA_EH_SOFTRESET;
976 ata_ehi_push_desc(ehi, ", interface fatal error");
977 }
1da177e4 978
78cd52d0 979 if (irq_stat & (PORT_IRQ_CONNECT | PORT_IRQ_PHYRDY)) {
4296971d 980 ata_ehi_hotplugged(ehi);
78cd52d0
TH		 981 ata_ehi_push_desc(ehi, ", %s", irq_stat & PORT_IRQ_CONNECT ?
982 "connection status changed" : "PHY RDY changed");
983 }
984
985 if (irq_stat & PORT_IRQ_UNK_FIS) {
986 u32 *unk = (u32 *)(pp->rx_fis + RX_FIS_UNK);
1da177e4 987
78cd52d0
TH		 988 err_mask |= AC_ERR_HSM;
989 action |= ATA_EH_SOFTRESET;
990 ata_ehi_push_desc(ehi, ", unknown FIS %08x %08x %08x %08x",
991 unk[0], unk[1], unk[2], unk[3]);
992 }
1da177e4 993
78cd52d0
TH		 994 /* okay, let's hand over to EH */
995 ehi->serror |= serror;
996 ehi->action |= action;
b8f6153e 997
1da177e4 998 qc = ata_qc_from_tag(ap, ap->active_tag);
78cd52d0
TH		 999 if (qc)
1000 qc->err_mask |= err_mask;
1001 else
1002 ehi->err_mask |= err_mask;
a72ec4ce 1003
78cd52d0
TH		 1004 if (irq_stat & PORT_IRQ_FREEZE)
1005 ata_port_freeze(ap);
1006 else
1007 ata_port_abort(ap);
1da177e4
LT		 1008}
1009
78cd52d0 1010static void ahci_host_intr(struct ata_port *ap)
1da177e4 1011{
cca3974e 1012 void __iomem *mmio = ap->host->mmio_base;
ea6ba10b 1013 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
12fad3f9
TH		 1014 struct ata_eh_info *ehi = &ap->eh_info;
1015 u32 status, qc_active;
1016 int rc;
1da177e4
LT		 1017
1018 status = readl(port_mmio + PORT_IRQ_STAT);
1019 writel(status, port_mmio + PORT_IRQ_STAT);
1020
78cd52d0
TH		 1021 if (unlikely(status & PORT_IRQ_ERROR)) {
1022 ahci_error_intr(ap, status);
1023 return;
1da177e4
LT		 1024 }
1025
12fad3f9
TH		 1026 if (ap->sactive)
1027 qc_active = readl(port_mmio + PORT_SCR_ACT);
1028 else
1029 qc_active = readl(port_mmio + PORT_CMD_ISSUE);
1030
1031 rc = ata_qc_complete_multiple(ap, qc_active, NULL);
1032 if (rc > 0)
1033 return;
1034 if (rc < 0) {
1035 ehi->err_mask |= AC_ERR_HSM;
1036 ehi->action |= ATA_EH_SOFTRESET;
1037 ata_port_freeze(ap);
1038 return;
1da177e4
LT		 1039 }
1040
2a3917a8
TH		 1041 /* hmmm... a spurious interupt */
1042
12fad3f9
TH		 1043 /* some devices send D2H reg with I bit set during NCQ command phase */
1044 if (ap->sactive && status & PORT_IRQ_D2H_REG_FIS)
1045 return;
1046
2a3917a8 1047 /* ignore interim PIO setup fis interrupts */
9bec2e38 1048 if (ata_tag_valid(ap->active_tag) && (status & PORT_IRQ_PIOS_FIS))
f1d39b29 1049 return;
2a3917a8 1050
78cd52d0
TH		 1051 if (ata_ratelimit())
1052 ata_port_printk(ap, KERN_INFO, "spurious interrupt "
12fad3f9
TH		 1053 "(irq_stat 0x%x active_tag %d sactive 0x%x)\n",
1054 status, ap->active_tag, ap->sactive);
1da177e4
LT		 1055}
1056
1057static void ahci_irq_clear(struct ata_port *ap)
1058{
1059 /* TODO */
1060}
1061
12fad3f9 1062static irqreturn_t ahci_interrupt(int irq, void *dev_instance, struct pt_regs *regs)
1da177e4 1063{
cca3974e 1064 struct ata_host *host = dev_instance;
1da177e4
LT		 1065 struct ahci_host_priv *hpriv;
1066 unsigned int i, handled = 0;
ea6ba10b 1067 void __iomem *mmio;
1da177e4
LT		 1068 u32 irq_stat, irq_ack = 0;
1069
1070 VPRINTK("ENTER\n");
1071
cca3974e
JG		 1072 hpriv = host->private_data;
1073 mmio = host->mmio_base;
1da177e4
LT		 1074
1075 /* sigh. 0xffffffff is a valid return from h/w */
1076 irq_stat = readl(mmio + HOST_IRQ_STAT);
1077 irq_stat &= hpriv->port_map;
1078 if (!irq_stat)
1079 return IRQ_NONE;
1080
cca3974e 1081 spin_lock(&host->lock);
1da177e4 1082
cca3974e 1083 for (i = 0; i < host->n_ports; i++) {
1da177e4 1084 struct ata_port *ap;
1da177e4 1085
67846b30
JG		 1086 if (!(irq_stat & (1 << i)))
1087 continue;
1088
cca3974e 1089 ap = host->ports[i];
67846b30 1090 if (ap) {
78cd52d0 1091 ahci_host_intr(ap);
67846b30
JG		 1092 VPRINTK("port %u\n", i);
1093 } else {
1094 VPRINTK("port %u (no irq)\n", i);
6971ed1f 1095 if (ata_ratelimit())
cca3974e 1096 dev_printk(KERN_WARNING, host->dev,
a9524a76 1097 "interrupt on disabled port %u\n", i);
1da177e4 1098 }
67846b30
JG		 1099
1100 irq_ack |= (1 << i);
1da177e4
LT		 1101 }
1102
1103 if (irq_ack) {
1104 writel(irq_ack, mmio + HOST_IRQ_STAT);
1105 handled = 1;
1106 }
1107
cca3974e 1108 spin_unlock(&host->lock);
1da177e4
LT		 1109
1110 VPRINTK("EXIT\n");
1111
1112 return IRQ_RETVAL(handled);
1113}
1114
9a3d9eb0 1115static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc)
1da177e4
LT		 1116{
1117 struct ata_port *ap = qc->ap;
ea6ba10b 1118 void __iomem *port_mmio = (void __iomem *) ap->ioaddr.cmd_addr;
1da177e4 1119
12fad3f9
TH		 1120 if (qc->tf.protocol == ATA_PROT_NCQ)
1121 writel(1 << qc->tag, port_mmio + PORT_SCR_ACT);
1122 writel(1 << qc->tag, port_mmio + PORT_CMD_ISSUE);
1da177e4
LT		 1123 readl(port_mmio + PORT_CMD_ISSUE); /* flush */
1124
1125 return 0;
1126}
1127
78cd52d0
TH		 1128static void ahci_freeze(struct ata_port *ap)
1129{
cca3974e 1130 void __iomem *mmio = ap->host->mmio_base;
78cd52d0
TH		 1131 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
1132
1133 /* turn IRQ off */
1134 writel(0, port_mmio + PORT_IRQ_MASK);
1135}
1136
1137static void ahci_thaw(struct ata_port *ap)
1138{
cca3974e 1139 void __iomem *mmio = ap->host->mmio_base;
78cd52d0
TH		 1140 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
1141 u32 tmp;
1142
1143 /* clear IRQ */
1144 tmp = readl(port_mmio + PORT_IRQ_STAT);
1145 writel(tmp, port_mmio + PORT_IRQ_STAT);
1146 writel(1 << ap->id, mmio + HOST_IRQ_STAT);
1147
1148 /* turn IRQ back on */
1149 writel(DEF_PORT_IRQ, port_mmio + PORT_IRQ_MASK);
1150}
1151
1152static void ahci_error_handler(struct ata_port *ap)
1153{
cca3974e 1154 void __iomem *mmio = ap->host->mmio_base;
5457f219 1155 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
1156
b51e9e5d 1157 if (!(ap->pflags & ATA_PFLAG_FROZEN)) {
78cd52d0 1158 /* restart engine */
5457f219 1159 ahci_stop_engine(port_mmio);
1160 ahci_start_engine(port_mmio);
78cd52d0
TH		 1161 }
1162
1163 /* perform recovery */
4296971d 1164 ata_do_eh(ap, ahci_prereset, ahci_softreset, ahci_hardreset,
f5914a46 1165 ahci_postreset);
78cd52d0
TH		 1166}
1167
1168static void ahci_post_internal_cmd(struct ata_queued_cmd *qc)
1169{
1170 struct ata_port *ap = qc->ap;
cca3974e 1171 void __iomem *mmio = ap->host->mmio_base;
5457f219 1172 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
78cd52d0
TH		 1173
1174 if (qc->flags & ATA_QCFLAG_FAILED)
1175 qc->err_mask |= AC_ERR_OTHER;
1176
1177 if (qc->err_mask) {
1178 /* make DMA engine forget about the failed command */
5457f219 1179 ahci_stop_engine(port_mmio);
1180 ahci_start_engine(port_mmio);
78cd52d0
TH		 1181 }
1182}
1183
c1332875
TH		 1184static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg)
1185{
cca3974e 1186 struct ahci_host_priv *hpriv = ap->host->private_data;
c1332875 1187 struct ahci_port_priv *pp = ap->private_data;
cca3974e 1188 void __iomem *mmio = ap->host->mmio_base;
c1332875
TH		 1189 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
1190 const char *emsg = NULL;
1191 int rc;
1192
1193 rc = ahci_deinit_port(port_mmio, hpriv->cap, &emsg);
1194 if (rc) {
1195 ata_port_printk(ap, KERN_ERR, "%s (%d)\n", emsg, rc);
1196 ahci_init_port(port_mmio, hpriv->cap,
1197 pp->cmd_slot_dma, pp->rx_fis_dma);
1198 }
1199
1200 return rc;
1201}
1202
1203static int ahci_port_resume(struct ata_port *ap)
1204{
1205 struct ahci_port_priv *pp = ap->private_data;
cca3974e
JG		 1206 struct ahci_host_priv *hpriv = ap->host->private_data;
1207 void __iomem *mmio = ap->host->mmio_base;
c1332875
TH		 1208 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
1209
1210 ahci_init_port(port_mmio, hpriv->cap, pp->cmd_slot_dma, pp->rx_fis_dma);
1211
1212 return 0;
1213}
1214
1215static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg)
1216{
cca3974e
JG		 1217 struct ata_host *host = dev_get_drvdata(&pdev->dev);
1218 void __iomem *mmio = host->mmio_base;
c1332875
TH		 1219 u32 ctl;
1220
1221 if (mesg.event == PM_EVENT_SUSPEND) {
1222 /* AHCI spec rev1.1 section 8.3.3:
1223 * Software must disable interrupts prior to requesting a
1224 * transition of the HBA to D3 state.
1225 */
1226 ctl = readl(mmio + HOST_CTL);
1227 ctl &= ~HOST_IRQ_EN;
1228 writel(ctl, mmio + HOST_CTL);
1229 readl(mmio + HOST_CTL); /* flush */
1230 }
1231
1232 return ata_pci_device_suspend(pdev, mesg);
1233}
1234
1235static int ahci_pci_device_resume(struct pci_dev *pdev)
1236{
cca3974e
JG		 1237 struct ata_host *host = dev_get_drvdata(&pdev->dev);
1238 struct ahci_host_priv *hpriv = host->private_data;
1239 void __iomem *mmio = host->mmio_base;
c1332875
TH		 1240 int rc;
1241
1242 ata_pci_device_do_resume(pdev);
1243
1244 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
1245 rc = ahci_reset_controller(mmio, pdev);
1246 if (rc)
1247 return rc;
1248
cca3974e 1249 ahci_init_controller(mmio, pdev, host->n_ports, hpriv->cap);
c1332875
TH		 1250 }
1251
cca3974e 1252 ata_host_resume(host);
c1332875
TH		 1253
1254 return 0;
1255}
1256
254950cd
TH		 1257static int ahci_port_start(struct ata_port *ap)
1258{
cca3974e
JG		 1259 struct device *dev = ap->host->dev;
1260 struct ahci_host_priv *hpriv = ap->host->private_data;
254950cd 1261 struct ahci_port_priv *pp;
cca3974e 1262 void __iomem *mmio = ap->host->mmio_base;
254950cd
TH		 1263 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
1264 void *mem;
1265 dma_addr_t mem_dma;
1266 int rc;
1267
1268 pp = kmalloc(sizeof(*pp), GFP_KERNEL);
1269 if (!pp)
1270 return -ENOMEM;
1271 memset(pp, 0, sizeof(*pp));
1272
1273 rc = ata_pad_alloc(ap, dev);
1274 if (rc) {
1275 kfree(pp);
1276 return rc;
1277 }
1278
1279 mem = dma_alloc_coherent(dev, AHCI_PORT_PRIV_DMA_SZ, &mem_dma, GFP_KERNEL);
1280 if (!mem) {
1281 ata_pad_free(ap, dev);
1282 kfree(pp);
1283 return -ENOMEM;
1284 }
1285 memset(mem, 0, AHCI_PORT_PRIV_DMA_SZ);
1286
1287 /*
1288 * First item in chunk of DMA memory: 32-slot command table,
1289 * 32 bytes each in size
1290 */
1291 pp->cmd_slot = mem;
1292 pp->cmd_slot_dma = mem_dma;
1293
1294 mem += AHCI_CMD_SLOT_SZ;
1295 mem_dma += AHCI_CMD_SLOT_SZ;
1296
1297 /*
1298 * Second item: Received-FIS area
1299 */
1300 pp->rx_fis = mem;
1301 pp->rx_fis_dma = mem_dma;
1302
1303 mem += AHCI_RX_FIS_SZ;
1304 mem_dma += AHCI_RX_FIS_SZ;
1305
1306 /*
1307 * Third item: data area for storing a single command
1308 * and its scatter-gather table
1309 */
1310 pp->cmd_tbl = mem;
1311 pp->cmd_tbl_dma = mem_dma;
1312
1313 ap->private_data = pp;
1314
0be0aa98
TH		 1315 /* initialize port */
1316 ahci_init_port(port_mmio, hpriv->cap, pp->cmd_slot_dma, pp->rx_fis_dma);
254950cd
TH		 1317
1318 return 0;
1319}
1320
1321static void ahci_port_stop(struct ata_port *ap)
1322{
cca3974e
JG		 1323 struct device *dev = ap->host->dev;
1324 struct ahci_host_priv *hpriv = ap->host->private_data;
254950cd 1325 struct ahci_port_priv *pp = ap->private_data;
cca3974e 1326 void __iomem *mmio = ap->host->mmio_base;
254950cd 1327 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
0be0aa98
TH		 1328 const char *emsg = NULL;
1329 int rc;
254950cd 1330
0be0aa98
TH		 1331 /* de-initialize port */
1332 rc = ahci_deinit_port(port_mmio, hpriv->cap, &emsg);
1333 if (rc)
1334 ata_port_printk(ap, KERN_WARNING, "%s (%d)\n", emsg, rc);
254950cd
TH		 1335
1336 ap->private_data = NULL;
1337 dma_free_coherent(dev, AHCI_PORT_PRIV_DMA_SZ,
1338 pp->cmd_slot, pp->cmd_slot_dma);
1339 ata_pad_free(ap, dev);
1340 kfree(pp);
1341}
1342
1da177e4
LT		 1343static void ahci_setup_port(struct ata_ioports *port, unsigned long base,
1344 unsigned int port_idx)
1345{
1346 VPRINTK("ENTER, base==0x%lx, port_idx %u\n", base, port_idx);
1347 base = ahci_port_base_ul(base, port_idx);
1348 VPRINTK("base now==0x%lx\n", base);
1349
1350 port->cmd_addr = base;
1351 port->scr_addr = base + PORT_SCR;
1352
1353 VPRINTK("EXIT\n");
1354}
1355
1356static int ahci_host_init(struct ata_probe_ent *probe_ent)
1357{
1358 struct ahci_host_priv *hpriv = probe_ent->private_data;
1359 struct pci_dev *pdev = to_pci_dev(probe_ent->dev);
1360 void __iomem *mmio = probe_ent->mmio_base;
0be0aa98 1361 unsigned int i, using_dac;
1da177e4 1362 int rc;
1da177e4 1363
d91542c1
TH		 1364 rc = ahci_reset_controller(mmio, pdev);
1365 if (rc)
1366 return rc;
1da177e4
LT		 1367
1368 hpriv->cap = readl(mmio + HOST_CAP);
1369 hpriv->port_map = readl(mmio + HOST_PORTS_IMPL);
1370 probe_ent->n_ports = (hpriv->cap & 0x1f) + 1;
1371
1372 VPRINTK("cap 0x%x port_map 0x%x n_ports %d\n",
1373 hpriv->cap, hpriv->port_map, probe_ent->n_ports);
1374
1375 using_dac = hpriv->cap & HOST_CAP_64;
1376 if (using_dac &&
1377 !pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
1378 rc = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
1379 if (rc) {
1380 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
1381 if (rc) {
a9524a76
JG		 1382 dev_printk(KERN_ERR, &pdev->dev,
1383 "64-bit DMA enable failed\n");
1da177e4
LT		 1384 return rc;
1385 }
1386 }
1da177e4
LT		 1387 } else {
1388 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
1389 if (rc) {
a9524a76
JG		 1390 dev_printk(KERN_ERR, &pdev->dev,
1391 "32-bit DMA enable failed\n");
1da177e4
LT		 1392 return rc;
1393 }
1394 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
1395 if (rc) {
a9524a76
JG		 1396 dev_printk(KERN_ERR, &pdev->dev,
1397 "32-bit consistent DMA enable failed\n");
1da177e4
LT		 1398 return rc;
1399 }
1400 }
1401
d91542c1
TH		 1402 for (i = 0; i < probe_ent->n_ports; i++)
1403 ahci_setup_port(&probe_ent->port[i], (unsigned long) mmio, i);
1da177e4 1404
d91542c1 1405 ahci_init_controller(mmio, pdev, probe_ent->n_ports, hpriv->cap);
1da177e4
LT		 1406
1407 pci_set_master(pdev);
1408
1409 return 0;
1410}
1411
1da177e4
LT		 1412static void ahci_print_info(struct ata_probe_ent *probe_ent)
1413{
1414 struct ahci_host_priv *hpriv = probe_ent->private_data;
1415 struct pci_dev *pdev = to_pci_dev(probe_ent->dev);
ea6ba10b 1416 void __iomem *mmio = probe_ent->mmio_base;
1da177e4
LT		 1417 u32 vers, cap, impl, speed;
1418 const char *speed_s;
1419 u16 cc;
1420 const char *scc_s;
1421
1422 vers = readl(mmio + HOST_VERSION);
1423 cap = hpriv->cap;
1424 impl = hpriv->port_map;
1425
1426 speed = (cap >> 20) & 0xf;
1427 if (speed == 1)
1428 speed_s = "1.5";
1429 else if (speed == 2)
1430 speed_s = "3";
1431 else
1432 speed_s = "?";
1433
1434 pci_read_config_word(pdev, 0x0a, &cc);
1435 if (cc == 0x0101)
1436 scc_s = "IDE";
1437 else if (cc == 0x0106)
1438 scc_s = "SATA";
1439 else if (cc == 0x0104)
1440 scc_s = "RAID";
1441 else
1442 scc_s = "unknown";
1443
a9524a76
JG		 1444 dev_printk(KERN_INFO, &pdev->dev,
1445 "AHCI %02x%02x.%02x%02x "
1da177e4
LT		 1446 "%u slots %u ports %s Gbps 0x%x impl %s mode\n"
1447 ,
1da177e4
LT		 1448
1449 (vers >> 24) & 0xff,
1450 (vers >> 16) & 0xff,
1451 (vers >> 8) & 0xff,
1452 vers & 0xff,
1453
1454 ((cap >> 8) & 0x1f) + 1,
1455 (cap & 0x1f) + 1,
1456 speed_s,
1457 impl,
1458 scc_s);
1459
a9524a76
JG		 1460 dev_printk(KERN_INFO, &pdev->dev,
1461 "flags: "
1da177e4
LT		 1462 "%s%s%s%s%s%s"
1463 "%s%s%s%s%s%s%s\n"
1464 ,
1da177e4
LT		 1465
1466 cap & (1 << 31) ? "64bit " : "",
1467 cap & (1 << 30) ? "ncq " : "",
1468 cap & (1 << 28) ? "ilck " : "",
1469 cap & (1 << 27) ? "stag " : "",
1470 cap & (1 << 26) ? "pm " : "",
1471 cap & (1 << 25) ? "led " : "",
1472
1473 cap & (1 << 24) ? "clo " : "",
1474 cap & (1 << 19) ? "nz " : "",
1475 cap & (1 << 18) ? "only " : "",
1476 cap & (1 << 17) ? "pmp " : "",
1477 cap & (1 << 15) ? "pio " : "",
1478 cap & (1 << 14) ? "slum " : "",
1479 cap & (1 << 13) ? "part " : ""
1480 );
1481}
1482
1483static int ahci_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
1484{
1485 static int printed_version;
1486 struct ata_probe_ent *probe_ent = NULL;
1487 struct ahci_host_priv *hpriv;
1488 unsigned long base;
ea6ba10b 1489 void __iomem *mmio_base;
1da177e4 1490 unsigned int board_idx = (unsigned int) ent->driver_data;
907f4678 1491 int have_msi, pci_dev_busy = 0;
1da177e4
LT		 1492 int rc;
1493
1494 VPRINTK("ENTER\n");
1495
12fad3f9
TH		 1496 WARN_ON(ATA_MAX_QUEUE > AHCI_MAX_CMDS);
1497
1da177e4 1498 if (!printed_version++)
a9524a76 1499 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
1da177e4 1500
9545b578 1501 /* JMicron-specific fixup: make sure we're in AHCI mode */
1502 /* This is protected from races with ata_jmicron by the pci probe
1503 locking */
1504 if (pdev->vendor == PCI_VENDOR_ID_JMICRON) {
1505 /* AHCI enable, AHCI on function 0 */
1506 pci_write_config_byte(pdev, 0x41, 0xa1);
1507 /* Function 1 is the PATA controller */
1508 if (PCI_FUNC(pdev->devfn))
1509 return -ENODEV;
1510 }
1511
1da177e4
LT		 1512 rc = pci_enable_device(pdev);
1513 if (rc)
1514 return rc;
1515
1516 rc = pci_request_regions(pdev, DRV_NAME);
1517 if (rc) {
1518 pci_dev_busy = 1;
1519 goto err_out;
1520 }
1521
907f4678
JG		 1522 if (pci_enable_msi(pdev) == 0)
1523 have_msi = 1;
1524 else {
1525 pci_intx(pdev, 1);
1526 have_msi = 0;
1527 }
1da177e4
LT		 1528
1529 probe_ent = kmalloc(sizeof(*probe_ent), GFP_KERNEL);
1530 if (probe_ent == NULL) {
1531 rc = -ENOMEM;
907f4678 1532 goto err_out_msi;
1da177e4
LT		 1533 }
1534
1535 memset(probe_ent, 0, sizeof(*probe_ent));
1536 probe_ent->dev = pci_dev_to_dev(pdev);
1537 INIT_LIST_HEAD(&probe_ent->node);
1538
374b1873 1539 mmio_base = pci_iomap(pdev, AHCI_PCI_BAR, 0);
1da177e4
LT		 1540 if (mmio_base == NULL) {
1541 rc = -ENOMEM;
1542 goto err_out_free_ent;
1543 }
1544 base = (unsigned long) mmio_base;
1545
1546 hpriv = kmalloc(sizeof(*hpriv), GFP_KERNEL);
1547 if (!hpriv) {
1548 rc = -ENOMEM;
1549 goto err_out_iounmap;
1550 }
1551 memset(hpriv, 0, sizeof(*hpriv));
1552
1553 probe_ent->sht = ahci_port_info[board_idx].sht;
cca3974e 1554 probe_ent->port_flags = ahci_port_info[board_idx].flags;
1da177e4
LT		 1555 probe_ent->pio_mask = ahci_port_info[board_idx].pio_mask;
1556 probe_ent->udma_mask = ahci_port_info[board_idx].udma_mask;
1557 probe_ent->port_ops = ahci_port_info[board_idx].port_ops;
1558
1559 probe_ent->irq = pdev->irq;
1d6f359a 1560 probe_ent->irq_flags = IRQF_SHARED;
1da177e4
LT		 1561 probe_ent->mmio_base = mmio_base;
1562 probe_ent->private_data = hpriv;
1563
4b0060f4
JG		 1564 if (have_msi)
1565 hpriv->flags |= AHCI_FLAG_MSI;
907f4678 1566
1da177e4
LT		 1567 /* initialize adapter */
1568 rc = ahci_host_init(probe_ent);
1569 if (rc)
1570 goto err_out_hpriv;
1571
cca3974e 1572 if (!(probe_ent->port_flags & AHCI_FLAG_NO_NCQ) &&
71f0737b 1573 (hpriv->cap & HOST_CAP_NCQ))
cca3974e 1574 probe_ent->port_flags |= ATA_FLAG_NCQ;
12fad3f9 1575
1da177e4
LT		 1576 ahci_print_info(probe_ent);
1577
1578 /* FIXME: check ata_device_add return value */
1579 ata_device_add(probe_ent);
1580 kfree(probe_ent);
1581
1582 return 0;
1583
1584err_out_hpriv:
1585 kfree(hpriv);
1586err_out_iounmap:
374b1873 1587 pci_iounmap(pdev, mmio_base);
1da177e4
LT		 1588err_out_free_ent:
1589 kfree(probe_ent);
907f4678
JG		 1590err_out_msi:
1591 if (have_msi)
1592 pci_disable_msi(pdev);
1593 else
1594 pci_intx(pdev, 0);
1da177e4
LT		 1595 pci_release_regions(pdev);
1596err_out:
1597 if (!pci_dev_busy)
1598 pci_disable_device(pdev);
1599 return rc;
1600}
1601
907f4678
JG		 1602static void ahci_remove_one (struct pci_dev *pdev)
1603{
1604 struct device *dev = pci_dev_to_dev(pdev);
cca3974e
JG		 1605 struct ata_host *host = dev_get_drvdata(dev);
1606 struct ahci_host_priv *hpriv = host->private_data;
907f4678
JG		 1607 unsigned int i;
1608 int have_msi;
1609
cca3974e
JG		 1610 for (i = 0; i < host->n_ports; i++)
1611 ata_port_detach(host->ports[i]);
907f4678 1612
4b0060f4 1613 have_msi = hpriv->flags & AHCI_FLAG_MSI;
cca3974e 1614 free_irq(host->irq, host);
907f4678 1615
cca3974e
JG		 1616 for (i = 0; i < host->n_ports; i++) {
1617 struct ata_port *ap = host->ports[i];
907f4678 1618
cca3974e
JG		 1619 ata_scsi_release(ap->scsi_host);
1620 scsi_host_put(ap->scsi_host);
907f4678
JG		 1621 }
1622
e005f01d 1623 kfree(hpriv);
cca3974e
JG		 1624 pci_iounmap(pdev, host->mmio_base);
1625 kfree(host);
ead5de99 1626
907f4678
JG		 1627 if (have_msi)
1628 pci_disable_msi(pdev);
1629 else
1630 pci_intx(pdev, 0);
1631 pci_release_regions(pdev);
907f4678
JG		 1632 pci_disable_device(pdev);
1633 dev_set_drvdata(dev, NULL);
1634}
1da177e4
LT		 1635
1636static int __init ahci_init(void)
1637{
b7887196 1638 return pci_register_driver(&ahci_pci_driver);
1da177e4
LT		 1639}
1640
1da177e4
LT		 1641static void __exit ahci_exit(void)
1642{
1643 pci_unregister_driver(&ahci_pci_driver);
1644}
1645
1646
1647MODULE_AUTHOR("Jeff Garzik");
1648MODULE_DESCRIPTION("AHCI SATA low-level driver");
1649MODULE_LICENSE("GPL");
1650MODULE_DEVICE_TABLE(pci, ahci_pci_tbl);
6885433c 1651MODULE_VERSION(DRV_VERSION);
1da177e4
LT		 1652
1653module_init(ahci_init);
1654module_exit(ahci_exit);
Linux kernel - Deliverables
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