[deliverable/linux.git] / drivers / ata / ahci_imx.c

/*
 * copyright (c) 2013 Freescale Semiconductor, Inc.
 * Freescale IMX AHCI SATA platform driver
 *
 * based on the AHCI SATA platform driver by Jeff Garzik and Anton Vorontsov
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms and conditions of the GNU General Public License,
 * version 2, as published by the Free Software Foundation.
 *
 * This program is distributed in the hope it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
 * more details.
 *
 * You should have received a copy of the GNU General Public License along with
 * this program. If not, see <http://www.gnu.org/licenses/>.
 */

#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <linux/ahci_platform.h>
#include <linux/of_device.h>
#include <linux/mfd/syscon.h>
#include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
#include <linux/libata.h>
#include "ahci.h"

enum {
	PORT_PHY_CTL = 0x178,			/* Port0 PHY Control */
	PORT_PHY_CTL_PDDQ_LOC = 0x100000,	/* PORT_PHY_CTL bits */
	HOST_TIMER1MS = 0xe0,			/* Timer 1-ms */
};

enum ahci_imx_type {
	AHCI_IMX53,
	AHCI_IMX6Q,
};

struct imx_ahci_priv {
	struct platform_device *ahci_pdev;
	enum ahci_imx_type type;

	/* i.MX53 clock */
	struct clk *sata_gate_clk;
	/* Common clock */
	struct clk *sata_ref_clk;
	struct clk *ahb_clk;

	struct regmap *gpr;
	bool no_device;
	bool first_time;
};

static int ahci_imx_hotplug;
module_param_named(hotplug, ahci_imx_hotplug, int, 0644);
MODULE_PARM_DESC(hotplug, "AHCI IMX hot-plug support (0=Don't support, 1=support)");

static int imx_sata_clock_enable(struct device *dev)
{
	struct imx_ahci_priv *imxpriv = dev_get_drvdata(dev->parent);
	int ret;

	if (imxpriv->type == AHCI_IMX53) {
		ret = clk_prepare_enable(imxpriv->sata_gate_clk);
		if (ret < 0) {
			dev_err(dev, "prepare-enable sata_gate clock err:%d\n",
				ret);
			return ret;
		}
	}

	ret = clk_prepare_enable(imxpriv->sata_ref_clk);
	if (ret < 0) {
		dev_err(dev, "prepare-enable sata_ref clock err:%d\n",
			ret);
		goto clk_err;
	}

	if (imxpriv->type == AHCI_IMX6Q) {
		regmap_update_bits(imxpriv->gpr, IOMUXC_GPR13,
				   IMX6Q_GPR13_SATA_MPLL_CLK_EN,
				   IMX6Q_GPR13_SATA_MPLL_CLK_EN);
	}

	usleep_range(1000, 2000);

	return 0;

clk_err:
	if (imxpriv->type == AHCI_IMX53)
		clk_disable_unprepare(imxpriv->sata_gate_clk);
	return ret;
}

static void imx_sata_clock_disable(struct device *dev)
{
	struct imx_ahci_priv *imxpriv = dev_get_drvdata(dev->parent);

	if (imxpriv->type == AHCI_IMX6Q) {
		regmap_update_bits(imxpriv->gpr, IOMUXC_GPR13,
				   IMX6Q_GPR13_SATA_MPLL_CLK_EN,
				   !IMX6Q_GPR13_SATA_MPLL_CLK_EN);
	}

	clk_disable_unprepare(imxpriv->sata_ref_clk);

	if (imxpriv->type == AHCI_IMX53)
		clk_disable_unprepare(imxpriv->sata_gate_clk);
}

static void ahci_imx_error_handler(struct ata_port *ap)
{
	u32 reg_val;
	struct ata_device *dev;
	struct ata_host *host = dev_get_drvdata(ap->dev);
	struct ahci_host_priv *hpriv = host->private_data;
	void __iomem *mmio = hpriv->mmio;
	struct imx_ahci_priv *imxpriv = dev_get_drvdata(ap->dev->parent);

	ahci_error_handler(ap);

	if (!(imxpriv->first_time) || ahci_imx_hotplug)
		return;

	imxpriv->first_time = false;

	ata_for_each_dev(dev, &ap->link, ENABLED)
		return;
	/*
	 * Disable link to save power.  An imx ahci port can't be recovered
	 * without full reset once the pddq mode is enabled making it
	 * impossible to use as part of libata LPM.
	 */
	reg_val = readl(mmio + PORT_PHY_CTL);
	writel(reg_val | PORT_PHY_CTL_PDDQ_LOC, mmio + PORT_PHY_CTL);
	imx_sata_clock_disable(ap->dev);
	imxpriv->no_device = true;
}

static int ahci_imx_softreset(struct ata_link *link, unsigned int *class,
		       unsigned long deadline)
{
	struct ata_port *ap = link->ap;
	struct imx_ahci_priv *imxpriv = dev_get_drvdata(ap->dev->parent);
	int ret = -EIO;

	if (imxpriv->type == AHCI_IMX53)
		ret = ahci_pmp_retry_srst_ops.softreset(link, class, deadline);
	else if (imxpriv->type == AHCI_IMX6Q)
		ret = ahci_ops.softreset(link, class, deadline);

	return ret;
}

static struct ata_port_operations ahci_imx_ops = {
	.inherits	= &ahci_platform_ops,
	.error_handler	= ahci_imx_error_handler,
	.softreset	= ahci_imx_softreset,
};

static const struct ata_port_info ahci_imx_port_info = {
	.flags		= AHCI_FLAG_COMMON,
	.pio_mask	= ATA_PIO4,
	.udma_mask	= ATA_UDMA6,
	.port_ops	= &ahci_imx_ops,
};

static int imx_sata_init(struct device *dev, void __iomem *mmio)
{
	int ret = 0;
	unsigned int reg_val;
	struct imx_ahci_priv *imxpriv = dev_get_drvdata(dev->parent);

	ret = imx_sata_clock_enable(dev);
	if (ret < 0)
		return ret;

	/*
	 * Configure the HWINIT bits of the HOST_CAP and HOST_PORTS_IMPL,
	 * and IP vendor specific register HOST_TIMER1MS.
	 * Configure CAP_SSS (support stagered spin up).
	 * Implement the port0.
	 * Get the ahb clock rate, and configure the TIMER1MS register.
	 */
	reg_val = readl(mmio + HOST_CAP);
	if (!(reg_val & HOST_CAP_SSS)) {
		reg_val |= HOST_CAP_SSS;
		writel(reg_val, mmio + HOST_CAP);
	}
	reg_val = readl(mmio + HOST_PORTS_IMPL);
	if (!(reg_val & 0x1)) {
		reg_val |= 0x1;
		writel(reg_val, mmio + HOST_PORTS_IMPL);
	}

	reg_val = clk_get_rate(imxpriv->ahb_clk) / 1000;
	writel(reg_val, mmio + HOST_TIMER1MS);

	return 0;
}

static void imx_sata_exit(struct device *dev)
{
	imx_sata_clock_disable(dev);
}

static int imx_ahci_suspend(struct device *dev)
{
	struct imx_ahci_priv *imxpriv =  dev_get_drvdata(dev->parent);

	/*
	 * If no_device is set, The CLKs had been gated off in the
	 * initialization so don't do it again here.
	 */
	if (!imxpriv->no_device)
		imx_sata_clock_disable(dev);

	return 0;
}

static int imx_ahci_resume(struct device *dev)
{
	struct imx_ahci_priv *imxpriv =  dev_get_drvdata(dev->parent);
	int ret = 0;

	if (!imxpriv->no_device)
		ret = imx_sata_clock_enable(dev);

	return ret;
}

static struct ahci_platform_data imx_sata_pdata = {
	.init		= imx_sata_init,
	.exit		= imx_sata_exit,
	.ata_port_info	= &ahci_imx_port_info,
	.suspend	= imx_ahci_suspend,
	.resume		= imx_ahci_resume,

};

static const struct of_device_id imx_ahci_of_match[] = {
	{ .compatible = "fsl,imx53-ahci", .data = (void *)AHCI_IMX53 },
	{ .compatible = "fsl,imx6q-ahci", .data = (void *)AHCI_IMX6Q },
	{},
};
MODULE_DEVICE_TABLE(of, imx_ahci_of_match);

static int imx_ahci_probe(struct platform_device *pdev)
{
	struct device *dev = &pdev->dev;
	struct resource *mem, *irq, res[2];
	const struct of_device_id *of_id;
	enum ahci_imx_type type;
	const struct ahci_platform_data *pdata = NULL;
	struct imx_ahci_priv *imxpriv;
	struct device *ahci_dev;
	struct platform_device *ahci_pdev;
	int ret;

	of_id = of_match_device(imx_ahci_of_match, dev);
	if (!of_id)
		return -EINVAL;

	type = (enum ahci_imx_type)of_id->data;
	pdata = &imx_sata_pdata;

	imxpriv = devm_kzalloc(dev, sizeof(*imxpriv), GFP_KERNEL);
	if (!imxpriv) {
		dev_err(dev, "can't alloc ahci_host_priv\n");
		return -ENOMEM;
	}

	ahci_pdev = platform_device_alloc("ahci", -1);
	if (!ahci_pdev)
		return -ENODEV;

	ahci_dev = &ahci_pdev->dev;
	ahci_dev->parent = dev;

	imxpriv->no_device = false;
	imxpriv->first_time = true;
	imxpriv->type = type;

	imxpriv->ahb_clk = devm_clk_get(dev, "ahb");
	if (IS_ERR(imxpriv->ahb_clk)) {
		dev_err(dev, "can't get ahb clock.\n");
		ret = PTR_ERR(imxpriv->ahb_clk);
		goto err_out;
	}

	if (type == AHCI_IMX53) {
		imxpriv->sata_gate_clk = devm_clk_get(dev, "sata_gate");
		if (IS_ERR(imxpriv->sata_gate_clk)) {
			dev_err(dev, "can't get sata_gate clock.\n");
			ret = PTR_ERR(imxpriv->sata_gate_clk);
			goto err_out;
		}
	}

	imxpriv->sata_ref_clk = devm_clk_get(dev, "sata_ref");
	if (IS_ERR(imxpriv->sata_ref_clk)) {
		dev_err(dev, "can't get sata_ref clock.\n");
		ret = PTR_ERR(imxpriv->sata_ref_clk);
		goto err_out;
	}

	imxpriv->ahci_pdev = ahci_pdev;
	platform_set_drvdata(pdev, imxpriv);

	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
	if (!mem || !irq) {
		dev_err(dev, "no mmio/irq resource\n");
		ret = -ENOMEM;
		goto err_out;
	}

	res[0] = *mem;
	res[1] = *irq;

	ahci_dev->coherent_dma_mask = DMA_BIT_MASK(32);
	ahci_dev->dma_mask = &ahci_dev->coherent_dma_mask;
	ahci_dev->of_node = dev->of_node;

	if (type == AHCI_IMX6Q) {
		imxpriv->gpr = syscon_regmap_lookup_by_compatible(
							"fsl,imx6q-iomuxc-gpr");
		if (IS_ERR(imxpriv->gpr)) {
			dev_err(dev,
				"failed to find fsl,imx6q-iomux-gpr regmap\n");
			ret = PTR_ERR(imxpriv->gpr);
			goto err_out;
		}

		/*
		 * Set PHY Paremeters, two steps to configure the GPR13,
		 * one write for rest of parameters, mask of first write
		 * is 0x07fffffe, and the other one write for setting
		 * the mpll_clk_en happens in imx_sata_clock_enable().
		 */
		regmap_update_bits(imxpriv->gpr, IOMUXC_GPR13,
				   IMX6Q_GPR13_SATA_RX_EQ_VAL_MASK |
				   IMX6Q_GPR13_SATA_RX_LOS_LVL_MASK |
				   IMX6Q_GPR13_SATA_RX_DPLL_MODE_MASK |
				   IMX6Q_GPR13_SATA_SPD_MODE_MASK |
				   IMX6Q_GPR13_SATA_MPLL_SS_EN |
				   IMX6Q_GPR13_SATA_TX_ATTEN_MASK |
				   IMX6Q_GPR13_SATA_TX_BOOST_MASK |
				   IMX6Q_GPR13_SATA_TX_LVL_MASK |
				   IMX6Q_GPR13_SATA_MPLL_CLK_EN |
				   IMX6Q_GPR13_SATA_TX_EDGE_RATE,
				   IMX6Q_GPR13_SATA_RX_EQ_VAL_3_0_DB |
				   IMX6Q_GPR13_SATA_RX_LOS_LVL_SATA2M |
				   IMX6Q_GPR13_SATA_RX_DPLL_MODE_2P_4F |
				   IMX6Q_GPR13_SATA_SPD_MODE_3P0G |
				   IMX6Q_GPR13_SATA_MPLL_SS_EN |
				   IMX6Q_GPR13_SATA_TX_ATTEN_9_16 |
				   IMX6Q_GPR13_SATA_TX_BOOST_3_33_DB |
				   IMX6Q_GPR13_SATA_TX_LVL_1_025_V);
	}

	ret = platform_device_add_resources(ahci_pdev, res, 2);
	if (ret)
		goto err_out;

	ret = platform_device_add_data(ahci_pdev, pdata, sizeof(*pdata));
	if (ret)
		goto err_out;

	ret = platform_device_add(ahci_pdev);
	if (ret) {
err_out:
		platform_device_put(ahci_pdev);
		return ret;
	}

	return 0;
}

static int imx_ahci_remove(struct platform_device *pdev)
{
	struct imx_ahci_priv *imxpriv = platform_get_drvdata(pdev);
	struct platform_device *ahci_pdev = imxpriv->ahci_pdev;

	platform_device_unregister(ahci_pdev);
	return 0;
}

static struct platform_driver imx_ahci_driver = {
	.probe = imx_ahci_probe,
	.remove = imx_ahci_remove,
	.driver = {
		.name = "ahci-imx",
		.owner = THIS_MODULE,
		.of_match_table = imx_ahci_of_match,
	},
};
module_platform_driver(imx_ahci_driver);

MODULE_DESCRIPTION("Freescale i.MX AHCI SATA platform driver");
MODULE_AUTHOR("Richard Zhu <Hong-Xing.Zhu@freescale.com>");
MODULE_LICENSE("GPL");
MODULE_ALIAS("ahci:imx");
Commit	Line	Data
9e54eae2	1	/*
8b789d89	2	* copyright (c) 2013 Freescale Semiconductor, Inc.
9e54eae2	3	* Freescale IMX AHCI SATA platform driver
9e54eae2 RZ	4	*
	5	* based on the AHCI SATA platform driver by Jeff Garzik and Anton Vorontsov
	6	*
	7	* This program is free software; you can redistribute it and/or modify it
	8	* under the terms and conditions of the GNU General Public License,
	9	* version 2, as published by the Free Software Foundation.
	10	*
	11	* This program is distributed in the hope it will be useful, but WITHOUT
	12	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	13	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	14	* more details.
	15	*
	16	* You should have received a copy of the GNU General Public License along with
	17	* this program. If not, see <http://www.gnu.org/licenses/>.
	18	*/
	19
	20	#include <linux/kernel.h>
	21	#include <linux/module.h>
	22	#include <linux/platform_device.h>
	23	#include <linux/regmap.h>
	24	#include <linux/ahci_platform.h>
	25	#include <linux/of_device.h>
	26	#include <linux/mfd/syscon.h>
	27	#include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
8b789d89	28	#include <linux/libata.h>
9e54eae2 RZ	29	#include "ahci.h"
	30
	31	enum {
8b789d89 RZ	32	PORT_PHY_CTL = 0x178, /* Port0 PHY Control */
	33	PORT_PHY_CTL_PDDQ_LOC = 0x100000, /* PORT_PHY_CTL bits */
	34	HOST_TIMER1MS = 0xe0, /* Timer 1-ms */
9e54eae2 RZ	35	};
9e54eae2 RZ	36
4a23d179 MV	37	enum ahci_imx_type {
	38	AHCI_IMX53,
	39	AHCI_IMX6Q,
	40	};
	41
9e54eae2 RZ	42	struct imx_ahci_priv {
9e54eae2 RZ	43	struct platform_device *ahci_pdev;
4a23d179 MV	44	enum ahci_imx_type type;
	45
	46	/* i.MX53 clock */
	47	struct clk *sata_gate_clk;
	48	/* Common clock */
9e54eae2 RZ	49	struct clk *sata_ref_clk;
9e54eae2 RZ	50	struct clk *ahb_clk;
4a23d179	51
9e54eae2	52	struct regmap *gpr;
8b789d89 RZ	53	bool no_device;
	54	bool first_time;
	55	};
	56
	57	static int ahci_imx_hotplug;
	58	module_param_named(hotplug, ahci_imx_hotplug, int, 0644);
	59	MODULE_PARM_DESC(hotplug, "AHCI IMX hot-plug support (0=Don't support, 1=support)");
	60
8403e2ec MV	61	static int imx_sata_clock_enable(struct device *dev)
	62	{
	63	struct imx_ahci_priv *imxpriv = dev_get_drvdata(dev->parent);
	64	int ret;
	65
4a23d179 MV	66	if (imxpriv->type == AHCI_IMX53) {
	67	ret = clk_prepare_enable(imxpriv->sata_gate_clk);
	68	if (ret < 0) {
	69	dev_err(dev, "prepare-enable sata_gate clock err:%d\n",
	70	ret);
	71	return ret;
	72	}
	73	}
	74
8403e2ec MV	75	ret = clk_prepare_enable(imxpriv->sata_ref_clk);
8403e2ec MV	76	if (ret < 0) {
4a23d179 MV	77	dev_err(dev, "prepare-enable sata_ref clock err:%d\n",
	78	ret);
	79	goto clk_err;
8403e2ec MV	80	}
8403e2ec MV	81
4a23d179 MV	82	if (imxpriv->type == AHCI_IMX6Q) {
	83	regmap_update_bits(imxpriv->gpr, IOMUXC_GPR13,
	84	IMX6Q_GPR13_SATA_MPLL_CLK_EN,
	85	IMX6Q_GPR13_SATA_MPLL_CLK_EN);
	86	}
8403e2ec MV	87
	88	usleep_range(1000, 2000);
	89
	90	return 0;
4a23d179 MV	91
	92	clk_err:
	93	if (imxpriv->type == AHCI_IMX53)
	94	clk_disable_unprepare(imxpriv->sata_gate_clk);
	95	return ret;
8403e2ec MV	96	}
	97
	98	static void imx_sata_clock_disable(struct device *dev)
	99	{
	100	struct imx_ahci_priv *imxpriv = dev_get_drvdata(dev->parent);
	101
4a23d179 MV	102	if (imxpriv->type == AHCI_IMX6Q) {
	103	regmap_update_bits(imxpriv->gpr, IOMUXC_GPR13,
	104	IMX6Q_GPR13_SATA_MPLL_CLK_EN,
	105	!IMX6Q_GPR13_SATA_MPLL_CLK_EN);
	106	}
	107
8403e2ec	108	clk_disable_unprepare(imxpriv->sata_ref_clk);
4a23d179 MV	109
	110	if (imxpriv->type == AHCI_IMX53)
	111	clk_disable_unprepare(imxpriv->sata_gate_clk);
8403e2ec MV	112	}
8403e2ec MV	113
8b789d89 RZ	114	static void ahci_imx_error_handler(struct ata_port *ap)
	115	{
	116	u32 reg_val;
	117	struct ata_device *dev;
	118	struct ata_host *host = dev_get_drvdata(ap->dev);
	119	struct ahci_host_priv *hpriv = host->private_data;
	120	void __iomem *mmio = hpriv->mmio;
	121	struct imx_ahci_priv *imxpriv = dev_get_drvdata(ap->dev->parent);
	122
	123	ahci_error_handler(ap);
	124
	125	if (!(imxpriv->first_time) \|\| ahci_imx_hotplug)
	126	return;
	127
	128	imxpriv->first_time = false;
	129
	130	ata_for_each_dev(dev, &ap->link, ENABLED)
	131	return;
	132	/*
	133	* Disable link to save power. An imx ahci port can't be recovered
	134	* without full reset once the pddq mode is enabled making it
	135	* impossible to use as part of libata LPM.
	136	*/
	137	reg_val = readl(mmio + PORT_PHY_CTL);
	138	writel(reg_val \| PORT_PHY_CTL_PDDQ_LOC, mmio + PORT_PHY_CTL);
8403e2ec	139	imx_sata_clock_disable(ap->dev);
8b789d89 RZ	140	imxpriv->no_device = true;
	141	}
	142
ee4e5a9a	143	static int ahci_imx_softreset(struct ata_link link, unsigned int class,
4a23d179 MV	144	unsigned long deadline)
	145	{
	146	struct ata_port *ap = link->ap;
	147	struct imx_ahci_priv *imxpriv = dev_get_drvdata(ap->dev->parent);
	148	int ret = -EIO;
	149
	150	if (imxpriv->type == AHCI_IMX53)
	151	ret = ahci_pmp_retry_srst_ops.softreset(link, class, deadline);
	152	else if (imxpriv->type == AHCI_IMX6Q)
	153	ret = ahci_ops.softreset(link, class, deadline);
	154
	155	return ret;
	156	}
	157
8b789d89 RZ	158	static struct ata_port_operations ahci_imx_ops = {
	159	.inherits = &ahci_platform_ops,
	160	.error_handler = ahci_imx_error_handler,
4a23d179	161	.softreset = ahci_imx_softreset,
8b789d89 RZ	162	};
	163
	164	static const struct ata_port_info ahci_imx_port_info = {
	165	.flags = AHCI_FLAG_COMMON,
	166	.pio_mask = ATA_PIO4,
	167	.udma_mask = ATA_UDMA6,
	168	.port_ops = &ahci_imx_ops,
9e54eae2 RZ	169	};
9e54eae2 RZ	170
4a23d179	171	static int imx_sata_init(struct device dev, void __iomem mmio)
9e54eae2 RZ	172	{
	173	int ret = 0;
	174	unsigned int reg_val;
	175	struct imx_ahci_priv *imxpriv = dev_get_drvdata(dev->parent);
	176
8403e2ec MV	177	ret = imx_sata_clock_enable(dev);
8403e2ec MV	178	if (ret < 0)
9e54eae2	179	return ret;
9e54eae2 RZ	180
	181	/*
	182	* Configure the HWINIT bits of the HOST_CAP and HOST_PORTS_IMPL,
	183	* and IP vendor specific register HOST_TIMER1MS.
	184	* Configure CAP_SSS (support stagered spin up).
	185	* Implement the port0.
	186	* Get the ahb clock rate, and configure the TIMER1MS register.
	187	*/
	188	reg_val = readl(mmio + HOST_CAP);
	189	if (!(reg_val & HOST_CAP_SSS)) {
	190	reg_val \|= HOST_CAP_SSS;
	191	writel(reg_val, mmio + HOST_CAP);
	192	}
	193	reg_val = readl(mmio + HOST_PORTS_IMPL);
	194	if (!(reg_val & 0x1)) {
	195	reg_val \|= 0x1;
	196	writel(reg_val, mmio + HOST_PORTS_IMPL);
	197	}
	198
	199	reg_val = clk_get_rate(imxpriv->ahb_clk) / 1000;
	200	writel(reg_val, mmio + HOST_TIMER1MS);
	201
	202	return 0;
	203	}
	204
4a23d179	205	static void imx_sata_exit(struct device *dev)
9e54eae2	206	{
8403e2ec	207	imx_sata_clock_disable(dev);
9e54eae2 RZ	208	}
9e54eae2 RZ	209
8b789d89 RZ	210	static int imx_ahci_suspend(struct device *dev)
	211	{
	212	struct imx_ahci_priv *imxpriv = dev_get_drvdata(dev->parent);
	213
	214	/*
	215	* If no_device is set, The CLKs had been gated off in the
	216	* initialization so don't do it again here.
	217	*/
8403e2ec MV	218	if (!imxpriv->no_device)
8403e2ec MV	219	imx_sata_clock_disable(dev);
8b789d89 RZ	220
	221	return 0;
	222	}
	223
	224	static int imx_ahci_resume(struct device *dev)
	225	{
	226	struct imx_ahci_priv *imxpriv = dev_get_drvdata(dev->parent);
8403e2ec	227	int ret = 0;
8b789d89	228
8403e2ec MV	229	if (!imxpriv->no_device)
8403e2ec MV	230	ret = imx_sata_clock_enable(dev);
8b789d89	231
8403e2ec	232	return ret;
8b789d89 RZ	233	}
8b789d89 RZ	234
4a23d179 MV	235	static struct ahci_platform_data imx_sata_pdata = {
	236	.init = imx_sata_init,
	237	.exit = imx_sata_exit,
	238	.ata_port_info = &ahci_imx_port_info,
	239	.suspend = imx_ahci_suspend,
	240	.resume = imx_ahci_resume,
	241
9e54eae2 RZ	242	};
	243
	244	static const struct of_device_id imx_ahci_of_match[] = {
4a23d179 MV	245	{ .compatible = "fsl,imx53-ahci", .data = (void *)AHCI_IMX53 },
4a23d179 MV	246	{ .compatible = "fsl,imx6q-ahci", .data = (void *)AHCI_IMX6Q },
9e54eae2 RZ	247	{},
	248	};
	249	MODULE_DEVICE_TABLE(of, imx_ahci_of_match);
	250
	251	static int imx_ahci_probe(struct platform_device *pdev)
	252	{
	253	struct device *dev = &pdev->dev;
	254	struct resource mem, irq, res[2];
	255	const struct of_device_id *of_id;
4a23d179	256	enum ahci_imx_type type;
9e54eae2 RZ	257	const struct ahci_platform_data *pdata = NULL;
	258	struct imx_ahci_priv *imxpriv;
	259	struct device *ahci_dev;
	260	struct platform_device *ahci_pdev;
	261	int ret;
	262
4a23d179 MV	263	of_id = of_match_device(imx_ahci_of_match, dev);
	264	if (!of_id)
	265	return -EINVAL;
	266
	267	type = (enum ahci_imx_type)of_id->data;
	268	pdata = &imx_sata_pdata;
	269
9e54eae2 RZ	270	imxpriv = devm_kzalloc(dev, sizeof(*imxpriv), GFP_KERNEL);
	271	if (!imxpriv) {
	272	dev_err(dev, "can't alloc ahci_host_priv\n");
	273	return -ENOMEM;
	274	}
	275
	276	ahci_pdev = platform_device_alloc("ahci", -1);
	277	if (!ahci_pdev)
	278	return -ENODEV;
	279
	280	ahci_dev = &ahci_pdev->dev;
	281	ahci_dev->parent = dev;
	282
8b789d89 RZ	283	imxpriv->no_device = false;
8b789d89 RZ	284	imxpriv->first_time = true;
4a23d179 MV	285	imxpriv->type = type;
4a23d179 MV	286
9e54eae2 RZ	287	imxpriv->ahb_clk = devm_clk_get(dev, "ahb");
	288	if (IS_ERR(imxpriv->ahb_clk)) {
	289	dev_err(dev, "can't get ahb clock.\n");
	290	ret = PTR_ERR(imxpriv->ahb_clk);
	291	goto err_out;
	292	}
	293
4a23d179 MV	294	if (type == AHCI_IMX53) {
	295	imxpriv->sata_gate_clk = devm_clk_get(dev, "sata_gate");
	296	if (IS_ERR(imxpriv->sata_gate_clk)) {
	297	dev_err(dev, "can't get sata_gate clock.\n");
	298	ret = PTR_ERR(imxpriv->sata_gate_clk);
	299	goto err_out;
	300	}
	301	}
	302
9e54eae2 RZ	303	imxpriv->sata_ref_clk = devm_clk_get(dev, "sata_ref");
	304	if (IS_ERR(imxpriv->sata_ref_clk)) {
	305	dev_err(dev, "can't get sata_ref clock.\n");
	306	ret = PTR_ERR(imxpriv->sata_ref_clk);
	307	goto err_out;
	308	}
	309
	310	imxpriv->ahci_pdev = ahci_pdev;
	311	platform_set_drvdata(pdev, imxpriv);
	312
9e54eae2 RZ	313	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	314	irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
	315	if (!mem \|\| !irq) {
	316	dev_err(dev, "no mmio/irq resource\n");
	317	ret = -ENOMEM;
	318	goto err_out;
	319	}
	320
	321	res[0] = *mem;
	322	res[1] = *irq;
	323
	324	ahci_dev->coherent_dma_mask = DMA_BIT_MASK(32);
	325	ahci_dev->dma_mask = &ahci_dev->coherent_dma_mask;
	326	ahci_dev->of_node = dev->of_node;
	327
4a23d179 MV	328	if (type == AHCI_IMX6Q) {
	329	imxpriv->gpr = syscon_regmap_lookup_by_compatible(
	330	"fsl,imx6q-iomuxc-gpr");
	331	if (IS_ERR(imxpriv->gpr)) {
	332	dev_err(dev,
	333	"failed to find fsl,imx6q-iomux-gpr regmap\n");
7d6203af WY	334	ret = PTR_ERR(imxpriv->gpr);
7d6203af WY	335	goto err_out;
4a23d179 MV	336	}
	337
	338	/*
	339	* Set PHY Paremeters, two steps to configure the GPR13,
	340	* one write for rest of parameters, mask of first write
	341	* is 0x07fffffe, and the other one write for setting
	342	* the mpll_clk_en happens in imx_sata_clock_enable().
	343	*/
	344	regmap_update_bits(imxpriv->gpr, IOMUXC_GPR13,
	345	IMX6Q_GPR13_SATA_RX_EQ_VAL_MASK \|
	346	IMX6Q_GPR13_SATA_RX_LOS_LVL_MASK \|
	347	IMX6Q_GPR13_SATA_RX_DPLL_MODE_MASK \|
	348	IMX6Q_GPR13_SATA_SPD_MODE_MASK \|
	349	IMX6Q_GPR13_SATA_MPLL_SS_EN \|
	350	IMX6Q_GPR13_SATA_TX_ATTEN_MASK \|
	351	IMX6Q_GPR13_SATA_TX_BOOST_MASK \|
	352	IMX6Q_GPR13_SATA_TX_LVL_MASK \|
	353	IMX6Q_GPR13_SATA_MPLL_CLK_EN \|
	354	IMX6Q_GPR13_SATA_TX_EDGE_RATE,
	355	IMX6Q_GPR13_SATA_RX_EQ_VAL_3_0_DB \|
	356	IMX6Q_GPR13_SATA_RX_LOS_LVL_SATA2M \|
	357	IMX6Q_GPR13_SATA_RX_DPLL_MODE_2P_4F \|
	358	IMX6Q_GPR13_SATA_SPD_MODE_3P0G \|
	359	IMX6Q_GPR13_SATA_MPLL_SS_EN \|
	360	IMX6Q_GPR13_SATA_TX_ATTEN_9_16 \|
	361	IMX6Q_GPR13_SATA_TX_BOOST_3_33_DB \|
	362	IMX6Q_GPR13_SATA_TX_LVL_1_025_V);
8403e2ec MV	363	}
8403e2ec MV	364
9e54eae2 RZ	365	ret = platform_device_add_resources(ahci_pdev, res, 2);
	366	if (ret)
	367	goto err_out;
	368
	369	ret = platform_device_add_data(ahci_pdev, pdata, sizeof(*pdata));
	370	if (ret)
	371	goto err_out;
	372
	373	ret = platform_device_add(ahci_pdev);
	374	if (ret) {
	375	err_out:
	376	platform_device_put(ahci_pdev);
	377	return ret;
	378	}
	379
	380	return 0;
	381	}
	382
	383	static int imx_ahci_remove(struct platform_device *pdev)
	384	{
	385	struct imx_ahci_priv *imxpriv = platform_get_drvdata(pdev);
	386	struct platform_device *ahci_pdev = imxpriv->ahci_pdev;
	387
	388	platform_device_unregister(ahci_pdev);
	389	return 0;
	390	}
	391
	392	static struct platform_driver imx_ahci_driver = {
	393	.probe = imx_ahci_probe,
	394	.remove = imx_ahci_remove,
	395	.driver = {
	396	.name = "ahci-imx",
	397	.owner = THIS_MODULE,
	398	.of_match_table = imx_ahci_of_match,
	399	},
	400	};
	401	module_platform_driver(imx_ahci_driver);
	402
	403	MODULE_DESCRIPTION("Freescale i.MX AHCI SATA platform driver");
	404	MODULE_AUTHOR("Richard Zhu <Hong-Xing.Zhu@freescale.com>");
	405	MODULE_LICENSE("GPL");
	406	MODULE_ALIAS("ahci:imx");