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669a5db4 JG |
1 | /* |
2 | * ata_generic.c - Generic PATA/SATA controller driver. | |
ab771630 | 3 | * Copyright 2005 Red Hat Inc, all rights reserved. |
669a5db4 | 4 | * |
85cd7251 | 5 | * Elements from ide/pci/generic.c |
669a5db4 JG |
6 | * Copyright (C) 2001-2002 Andre Hedrick <andre@linux-ide.org> |
7 | * Portions (C) Copyright 2002 Red Hat Inc <alan@redhat.com> | |
8 | * | |
9 | * May be copied or modified under the terms of the GNU General Public License | |
85cd7251 | 10 | * |
669a5db4 JG |
11 | * Driver for PCI IDE interfaces implementing the standard bus mastering |
12 | * interface functionality. This assumes the BIOS did the drive set up and | |
13 | * tuning for us. By default we do not grab all IDE class devices as they | |
14 | * may have other drivers or need fixups to avoid problems. Instead we keep | |
15 | * a default list of stuff without documentation/driver that appears to | |
85cd7251 | 16 | * work. |
669a5db4 JG |
17 | */ |
18 | ||
19 | #include <linux/kernel.h> | |
20 | #include <linux/module.h> | |
21 | #include <linux/pci.h> | |
22 | #include <linux/init.h> | |
23 | #include <linux/blkdev.h> | |
24 | #include <linux/delay.h> | |
25 | #include <scsi/scsi_host.h> | |
26 | #include <linux/libata.h> | |
27 | ||
28 | #define DRV_NAME "ata_generic" | |
5e8f757c | 29 | #define DRV_VERSION "0.2.15" |
669a5db4 JG |
30 | |
31 | /* | |
32 | * A generic parallel ATA driver using libata | |
33 | */ | |
34 | ||
1529c69a TH |
35 | enum { |
36 | ATA_GEN_CLASS_MATCH = (1 << 0), | |
37 | ATA_GEN_FORCE_DMA = (1 << 1), | |
60039a52 | 38 | ATA_GEN_INTEL_IDER = (1 << 2), |
1529c69a TH |
39 | }; |
40 | ||
669a5db4 JG |
41 | /** |
42 | * generic_set_mode - mode setting | |
0260731f | 43 | * @link: link to set up |
b229a7b0 | 44 | * @unused: returned device on error |
669a5db4 JG |
45 | * |
46 | * Use a non standard set_mode function. We don't want to be tuned. | |
47 | * The BIOS configured everything. Our job is not to fiddle. We | |
48 | * read the dma enabled bits from the PCI configuration of the device | |
85cd7251 | 49 | * and respect them. |
669a5db4 | 50 | */ |
85cd7251 | 51 | |
0260731f | 52 | static int generic_set_mode(struct ata_link *link, struct ata_device **unused) |
669a5db4 | 53 | { |
0260731f | 54 | struct ata_port *ap = link->ap; |
1529c69a | 55 | const struct pci_device_id *id = ap->host->private_data; |
669a5db4 | 56 | int dma_enabled = 0; |
f58229f8 | 57 | struct ata_device *dev; |
669a5db4 | 58 | |
1529c69a TH |
59 | if (id->driver_data & ATA_GEN_FORCE_DMA) { |
60 | dma_enabled = 0xff; | |
61 | } else if (ap->ioaddr.bmdma_addr) { | |
62 | /* Bits 5 and 6 indicate if DMA is active on master/slave */ | |
d6f4d5ea | 63 | dma_enabled = ioread8(ap->ioaddr.bmdma_addr + ATA_DMA_STATUS); |
1529c69a | 64 | } |
85cd7251 | 65 | |
1eca4365 | 66 | ata_for_each_dev(dev, link, ENABLED) { |
f8ab6d8e TH |
67 | /* We don't really care */ |
68 | dev->pio_mode = XFER_PIO_0; | |
69 | dev->dma_mode = XFER_MW_DMA_0; | |
70 | /* We do need the right mode information for DMA or PIO | |
71 | and this comes from the current configuration flags */ | |
72 | if (dma_enabled & (1 << (5 + dev->devno))) { | |
9d3501ab TH |
73 | unsigned int xfer_mask = ata_id_xfermask(dev->id); |
74 | const char *name; | |
75 | ||
76 | if (xfer_mask & (ATA_MASK_MWDMA | ATA_MASK_UDMA)) | |
77 | name = ata_mode_string(xfer_mask); | |
78 | else { | |
79 | /* SWDMA perhaps? */ | |
80 | name = "DMA"; | |
81 | xfer_mask |= ata_xfer_mode2mask(XFER_MW_DMA_0); | |
82 | } | |
83 | ||
a9a79dfe | 84 | ata_dev_info(dev, "configured for %s\n", name); |
9d3501ab TH |
85 | |
86 | dev->xfer_mode = ata_xfer_mask2mode(xfer_mask); | |
87 | dev->xfer_shift = ata_xfer_mode2shift(dev->xfer_mode); | |
f8ab6d8e TH |
88 | dev->flags &= ~ATA_DFLAG_PIO; |
89 | } else { | |
a9a79dfe | 90 | ata_dev_info(dev, "configured for PIO\n"); |
f8ab6d8e TH |
91 | dev->xfer_mode = XFER_PIO_0; |
92 | dev->xfer_shift = ATA_SHIFT_PIO; | |
93 | dev->flags |= ATA_DFLAG_PIO; | |
669a5db4 JG |
94 | } |
95 | } | |
b229a7b0 | 96 | return 0; |
669a5db4 JG |
97 | } |
98 | ||
99 | static struct scsi_host_template generic_sht = { | |
68d1d07b | 100 | ATA_BMDMA_SHT(DRV_NAME), |
669a5db4 JG |
101 | }; |
102 | ||
103 | static struct ata_port_operations generic_port_ops = { | |
029cfd6b | 104 | .inherits = &ata_bmdma_port_ops, |
eb4a2c7f | 105 | .cable_detect = ata_cable_unknown, |
029cfd6b | 106 | .set_mode = generic_set_mode, |
85cd7251 JG |
107 | }; |
108 | ||
669a5db4 JG |
109 | static int all_generic_ide; /* Set to claim all devices */ |
110 | ||
60039a52 AC |
111 | /** |
112 | * is_intel_ider - identify intel IDE-R devices | |
113 | * @dev: PCI device | |
114 | * | |
115 | * Distinguish Intel IDE-R controller devices from other Intel IDE | |
116 | * devices. IDE-R devices have no timing registers and are in | |
117 | * most respects virtual. They should be driven by the ata_generic | |
118 | * driver. | |
119 | * | |
120 | * IDE-R devices have PCI offset 0xF8.L as zero, later Intel ATA has | |
121 | * it non zero. All Intel ATA has 0x40 writable (timing), but it is | |
122 | * not writable on IDE-R devices (this is guaranteed). | |
123 | */ | |
124 | ||
125 | static int is_intel_ider(struct pci_dev *dev) | |
126 | { | |
127 | /* For Intel IDE the value at 0xF8 is only zero on IDE-R | |
128 | interfaces */ | |
129 | u32 r; | |
130 | u16 t; | |
131 | ||
132 | /* Check the manufacturing ID, it will be zero for IDE-R */ | |
133 | pci_read_config_dword(dev, 0xF8, &r); | |
134 | /* Not IDE-R: punt so that ata_(old)piix gets it */ | |
135 | if (r != 0) | |
136 | return 0; | |
137 | /* 0xF8 will also be zero on some early Intel IDE devices | |
138 | but they will have a sane timing register */ | |
139 | pci_read_config_word(dev, 0x40, &t); | |
140 | if (t != 0) | |
141 | return 0; | |
142 | /* Finally check if the timing register is writable so that | |
143 | we eliminate any early devices hot-docked in a docking | |
144 | station */ | |
145 | pci_write_config_word(dev, 0x40, 1); | |
146 | pci_read_config_word(dev, 0x40, &t); | |
147 | if (t) { | |
148 | pci_write_config_word(dev, 0x40, 0); | |
149 | return 0; | |
150 | } | |
151 | return 1; | |
152 | } | |
153 | ||
669a5db4 JG |
154 | /** |
155 | * ata_generic_init - attach generic IDE | |
156 | * @dev: PCI device found | |
157 | * @id: match entry | |
158 | * | |
159 | * Called each time a matching IDE interface is found. We check if the | |
85cd7251 | 160 | * interface is one we wish to claim and if so we perform any chip |
669a5db4 JG |
161 | * specific hacks then let the ATA layer do the heavy lifting. |
162 | */ | |
85cd7251 | 163 | |
669a5db4 JG |
164 | static int ata_generic_init_one(struct pci_dev *dev, const struct pci_device_id *id) |
165 | { | |
166 | u16 command; | |
1626aeb8 | 167 | static const struct ata_port_info info = { |
1d2808fd | 168 | .flags = ATA_FLAG_SLAVE_POSS, |
14bdef98 EIB |
169 | .pio_mask = ATA_PIO4, |
170 | .mwdma_mask = ATA_MWDMA2, | |
bf6263a8 | 171 | .udma_mask = ATA_UDMA5, |
669a5db4 JG |
172 | .port_ops = &generic_port_ops |
173 | }; | |
1626aeb8 | 174 | const struct ata_port_info *ppi[] = { &info, NULL }; |
85cd7251 | 175 | |
669a5db4 | 176 | /* Don't use the generic entry unless instructed to do so */ |
1529c69a | 177 | if ((id->driver_data & ATA_GEN_CLASS_MATCH) && all_generic_ide == 0) |
669a5db4 JG |
178 | return -ENODEV; |
179 | ||
60039a52 AC |
180 | if (id->driver_data & ATA_GEN_INTEL_IDER) |
181 | if (!is_intel_ider(dev)) | |
182 | return -ENODEV; | |
183 | ||
669a5db4 JG |
184 | /* Devices that need care */ |
185 | if (dev->vendor == PCI_VENDOR_ID_UMC && | |
186 | dev->device == PCI_DEVICE_ID_UMC_UM8886A && | |
187 | (!(PCI_FUNC(dev->devfn) & 1))) | |
188 | return -ENODEV; | |
189 | ||
190 | if (dev->vendor == PCI_VENDOR_ID_OPTI && | |
191 | dev->device == PCI_DEVICE_ID_OPTI_82C558 && | |
192 | (!(PCI_FUNC(dev->devfn) & 1))) | |
193 | return -ENODEV; | |
194 | ||
195 | /* Don't re-enable devices in generic mode or we will break some | |
196 | motherboards with disabled and unused IDE controllers */ | |
197 | pci_read_config_word(dev, PCI_COMMAND, &command); | |
198 | if (!(command & PCI_COMMAND_IO)) | |
199 | return -ENODEV; | |
85cd7251 | 200 | |
669a5db4 | 201 | if (dev->vendor == PCI_VENDOR_ID_AL) |
9363c382 | 202 | ata_pci_bmdma_clear_simplex(dev); |
669a5db4 | 203 | |
05177f17 AC |
204 | if (dev->vendor == PCI_VENDOR_ID_ATI) { |
205 | int rc = pcim_enable_device(dev); | |
206 | if (rc < 0) | |
207 | return rc; | |
208 | pcim_pin_device(dev); | |
209 | } | |
1529c69a | 210 | return ata_pci_bmdma_init_one(dev, ppi, &generic_sht, (void *)id, 0); |
669a5db4 JG |
211 | } |
212 | ||
213 | static struct pci_device_id ata_generic[] = { | |
214 | { PCI_DEVICE(PCI_VENDOR_ID_PCTECH, PCI_DEVICE_ID_PCTECH_SAMURAI_IDE), }, | |
215 | { PCI_DEVICE(PCI_VENDOR_ID_HOLTEK, PCI_DEVICE_ID_HOLTEK_6565), }, | |
85cd7251 | 216 | { PCI_DEVICE(PCI_VENDOR_ID_UMC, PCI_DEVICE_ID_UMC_UM8673F), }, |
669a5db4 JG |
217 | { PCI_DEVICE(PCI_VENDOR_ID_UMC, PCI_DEVICE_ID_UMC_UM8886A), }, |
218 | { PCI_DEVICE(PCI_VENDOR_ID_UMC, PCI_DEVICE_ID_UMC_UM8886BF), }, | |
219 | { PCI_DEVICE(PCI_VENDOR_ID_HINT, PCI_DEVICE_ID_HINT_VXPROII_IDE), }, | |
220 | { PCI_DEVICE(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C561), }, | |
221 | { PCI_DEVICE(PCI_VENDOR_ID_OPTI, PCI_DEVICE_ID_OPTI_82C558), }, | |
1529c69a TH |
222 | { PCI_DEVICE(PCI_VENDOR_ID_CENATEK,PCI_DEVICE_ID_CENATEK_IDE), |
223 | .driver_data = ATA_GEN_FORCE_DMA }, | |
c6353b45 TH |
224 | /* |
225 | * For some reason, MCP89 on MacBook 7,1 doesn't work with | |
226 | * ahci, use ata_generic instead. | |
227 | */ | |
228 | { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP89_SATA, | |
1529c69a TH |
229 | PCI_VENDOR_ID_APPLE, 0xcb89, |
230 | .driver_data = ATA_GEN_FORCE_DMA }, | |
8e182a90 | 231 | #if !defined(CONFIG_PATA_TOSHIBA) && !defined(CONFIG_PATA_TOSHIBA_MODULE) |
669a5db4 JG |
232 | { PCI_DEVICE(PCI_VENDOR_ID_TOSHIBA,PCI_DEVICE_ID_TOSHIBA_PICCOLO_1), }, |
233 | { PCI_DEVICE(PCI_VENDOR_ID_TOSHIBA,PCI_DEVICE_ID_TOSHIBA_PICCOLO_2), }, | |
8e182a90 AC |
234 | { PCI_DEVICE(PCI_VENDOR_ID_TOSHIBA,PCI_DEVICE_ID_TOSHIBA_PICCOLO_3), }, |
235 | { PCI_DEVICE(PCI_VENDOR_ID_TOSHIBA,PCI_DEVICE_ID_TOSHIBA_PICCOLO_5), }, | |
60039a52 AC |
236 | #endif |
237 | /* Intel, IDE class device */ | |
238 | { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, | |
4fca377f | 239 | PCI_CLASS_STORAGE_IDE << 8, 0xFFFFFF00UL, |
60039a52 | 240 | .driver_data = ATA_GEN_INTEL_IDER }, |
669a5db4 | 241 | /* Must come last. If you add entries adjust this table appropriately */ |
1529c69a TH |
242 | { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_IDE << 8, 0xFFFFFF00UL), |
243 | .driver_data = ATA_GEN_CLASS_MATCH }, | |
669a5db4 JG |
244 | { 0, }, |
245 | }; | |
246 | ||
247 | static struct pci_driver ata_generic_pci_driver = { | |
248 | .name = DRV_NAME, | |
249 | .id_table = ata_generic, | |
250 | .probe = ata_generic_init_one, | |
30ced0f0 | 251 | .remove = ata_pci_remove_one, |
438ac6d5 | 252 | #ifdef CONFIG_PM |
30ced0f0 A |
253 | .suspend = ata_pci_device_suspend, |
254 | .resume = ata_pci_device_resume, | |
438ac6d5 | 255 | #endif |
669a5db4 JG |
256 | }; |
257 | ||
258 | static int __init ata_generic_init(void) | |
259 | { | |
3f03c671 | 260 | return pci_register_driver(&ata_generic_pci_driver); |
669a5db4 JG |
261 | } |
262 | ||
263 | ||
264 | static void __exit ata_generic_exit(void) | |
265 | { | |
266 | pci_unregister_driver(&ata_generic_pci_driver); | |
267 | } | |
268 | ||
269 | ||
270 | MODULE_AUTHOR("Alan Cox"); | |
271 | MODULE_DESCRIPTION("low-level driver for generic ATA"); | |
272 | MODULE_LICENSE("GPL"); | |
273 | MODULE_DEVICE_TABLE(pci, ata_generic); | |
274 | MODULE_VERSION(DRV_VERSION); | |
275 | ||
276 | module_init(ata_generic_init); | |
277 | module_exit(ata_generic_exit); | |
278 | ||
279 | module_param(all_generic_ide, int, 0); |