Commit | Line | Data |
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1da177e4 | 1 | /* |
af36d7f0 JG |
2 | * ata_piix.c - Intel PATA/SATA controllers |
3 | * | |
4 | * Maintained by: Jeff Garzik <jgarzik@pobox.com> | |
5 | * Please ALWAYS copy linux-ide@vger.kernel.org | |
6 | * on emails. | |
7 | * | |
8 | * | |
9 | * Copyright 2003-2005 Red Hat Inc | |
10 | * Copyright 2003-2005 Jeff Garzik | |
11 | * | |
12 | * | |
13 | * Copyright header from piix.c: | |
14 | * | |
15 | * Copyright (C) 1998-1999 Andrzej Krzysztofowicz, Author and Maintainer | |
16 | * Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org> | |
ab771630 | 17 | * Copyright (C) 2003 Red Hat Inc |
af36d7f0 JG |
18 | * |
19 | * | |
20 | * This program is free software; you can redistribute it and/or modify | |
21 | * it under the terms of the GNU General Public License as published by | |
22 | * the Free Software Foundation; either version 2, or (at your option) | |
23 | * any later version. | |
24 | * | |
25 | * This program is distributed in the hope that it will be useful, | |
26 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
27 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
28 | * GNU General Public License for more details. | |
29 | * | |
30 | * You should have received a copy of the GNU General Public License | |
31 | * along with this program; see the file COPYING. If not, write to | |
32 | * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. | |
33 | * | |
34 | * | |
35 | * libata documentation is available via 'make {ps|pdf}docs', | |
36 | * as Documentation/DocBook/libata.* | |
37 | * | |
38 | * Hardware documentation available at http://developer.intel.com/ | |
39 | * | |
d96212ed | 40 | * Documentation |
25985edc LDM |
41 | * Publicly available from Intel web site. Errata documentation |
42 | * is also publicly available. As an aide to anyone hacking on this | |
2c5ff671 | 43 | * driver the list of errata that are relevant is below, going back to |
d96212ed AC |
44 | * PIIX4. Older device documentation is now a bit tricky to find. |
45 | * | |
88393161 | 46 | * The chipsets all follow very much the same design. The original Triton |
25985edc | 47 | * series chipsets do _not_ support independent device timings, but this |
d96212ed AC |
48 | * is fixed in Triton II. With the odd mobile exception the chips then |
49 | * change little except in gaining more modes until SATA arrives. This | |
25985edc | 50 | * driver supports only the chips with independent timing (that is those |
d96212ed AC |
51 | * with SITRE and the 0x44 timing register). See pata_oldpiix and pata_mpiix |
52 | * for the early chip drivers. | |
53 | * | |
54 | * Errata of note: | |
55 | * | |
56 | * Unfixable | |
57 | * PIIX4 errata #9 - Only on ultra obscure hw | |
58 | * ICH3 errata #13 - Not observed to affect real hw | |
59 | * by Intel | |
60 | * | |
61 | * Things we must deal with | |
62 | * PIIX4 errata #10 - BM IDE hang with non UDMA | |
63 | * (must stop/start dma to recover) | |
64 | * 440MX errata #15 - As PIIX4 errata #10 | |
65 | * PIIX4 errata #15 - Must not read control registers | |
66 | * during a PIO transfer | |
67 | * 440MX errata #13 - As PIIX4 errata #15 | |
68 | * ICH2 errata #21 - DMA mode 0 doesn't work right | |
69 | * ICH0/1 errata #55 - As ICH2 errata #21 | |
70 | * ICH2 spec c #9 - Extra operations needed to handle | |
71 | * drive hotswap [NOT YET SUPPORTED] | |
72 | * ICH2 spec c #20 - IDE PRD must not cross a 64K boundary | |
73 | * and must be dword aligned | |
74 | * ICH2 spec c #24 - UDMA mode 4,5 t85/86 should be 6ns not 3.3 | |
c611bed7 | 75 | * ICH7 errata #16 - MWDMA1 timings are incorrect |
d96212ed AC |
76 | * |
77 | * Should have been BIOS fixed: | |
78 | * 450NX: errata #19 - DMA hangs on old 450NX | |
79 | * 450NX: errata #20 - DMA hangs on old 450NX | |
80 | * 450NX: errata #25 - Corruption with DMA on old 450NX | |
81 | * ICH3 errata #15 - IDE deadlock under high load | |
82 | * (BIOS must set dev 31 fn 0 bit 23) | |
83 | * ICH3 errata #18 - Don't use native mode | |
1da177e4 LT |
84 | */ |
85 | ||
86 | #include <linux/kernel.h> | |
87 | #include <linux/module.h> | |
88 | #include <linux/pci.h> | |
89 | #include <linux/init.h> | |
90 | #include <linux/blkdev.h> | |
91 | #include <linux/delay.h> | |
6248e647 | 92 | #include <linux/device.h> |
5a0e3ad6 | 93 | #include <linux/gfp.h> |
1da177e4 LT |
94 | #include <scsi/scsi_host.h> |
95 | #include <linux/libata.h> | |
b8b275ef | 96 | #include <linux/dmi.h> |
1da177e4 LT |
97 | |
98 | #define DRV_NAME "ata_piix" | |
c611bed7 | 99 | #define DRV_VERSION "2.13" |
1da177e4 LT |
100 | |
101 | enum { | |
102 | PIIX_IOCFG = 0x54, /* IDE I/O configuration register */ | |
103 | ICH5_PMR = 0x90, /* port mapping register */ | |
104 | ICH5_PCS = 0x92, /* port control and status */ | |
c7290724 TH |
105 | PIIX_SIDPR_BAR = 5, |
106 | PIIX_SIDPR_LEN = 16, | |
107 | PIIX_SIDPR_IDX = 0, | |
108 | PIIX_SIDPR_DATA = 4, | |
1da177e4 | 109 | |
ff0fc146 | 110 | PIIX_FLAG_CHECKINTR = (1 << 28), /* make sure PCI INTx enabled */ |
c7290724 | 111 | PIIX_FLAG_SIDPR = (1 << 29), /* SATA idx/data pair regs */ |
1da177e4 | 112 | |
800b3996 TH |
113 | PIIX_PATA_FLAGS = ATA_FLAG_SLAVE_POSS, |
114 | PIIX_SATA_FLAGS = ATA_FLAG_SATA | PIIX_FLAG_CHECKINTR, | |
b3362f88 | 115 | |
1da177e4 LT |
116 | PIIX_80C_PRI = (1 << 5) | (1 << 4), |
117 | PIIX_80C_SEC = (1 << 7) | (1 << 6), | |
118 | ||
d33f58b8 TH |
119 | /* constants for mapping table */ |
120 | P0 = 0, /* port 0 */ | |
121 | P1 = 1, /* port 1 */ | |
122 | P2 = 2, /* port 2 */ | |
123 | P3 = 3, /* port 3 */ | |
124 | IDE = -1, /* IDE */ | |
25985edc | 125 | NA = -2, /* not available */ |
d33f58b8 TH |
126 | RV = -3, /* reserved */ |
127 | ||
7b6dbd68 | 128 | PIIX_AHCI_DEVICE = 6, |
b8b275ef TH |
129 | |
130 | /* host->flags bits */ | |
131 | PIIX_HOST_BROKEN_SUSPEND = (1 << 24), | |
1da177e4 LT |
132 | }; |
133 | ||
9cde9ed1 TH |
134 | enum piix_controller_ids { |
135 | /* controller IDs */ | |
136 | piix_pata_mwdma, /* PIIX3 MWDMA only */ | |
137 | piix_pata_33, /* PIIX4 at 33Mhz */ | |
138 | ich_pata_33, /* ICH up to UDMA 33 only */ | |
139 | ich_pata_66, /* ICH up to 66 Mhz */ | |
140 | ich_pata_100, /* ICH up to UDMA 100 */ | |
c611bed7 | 141 | ich_pata_100_nomwdma1, /* ICH up to UDMA 100 but with no MWDMA1*/ |
9cde9ed1 TH |
142 | ich5_sata, |
143 | ich6_sata, | |
9c0bf675 TH |
144 | ich6m_sata, |
145 | ich8_sata, | |
9cde9ed1 | 146 | ich8_2port_sata, |
9c0bf675 TH |
147 | ich8m_apple_sata, /* locks up on second port enable */ |
148 | tolapai_sata, | |
9cde9ed1 TH |
149 | piix_pata_vmw, /* PIIX4 for VMware, spurious DMA_ERR */ |
150 | }; | |
151 | ||
d33f58b8 TH |
152 | struct piix_map_db { |
153 | const u32 mask; | |
73291a1c | 154 | const u16 port_enable; |
d33f58b8 TH |
155 | const int map[][4]; |
156 | }; | |
157 | ||
d96715c1 TH |
158 | struct piix_host_priv { |
159 | const int *map; | |
2852bcf7 | 160 | u32 saved_iocfg; |
c7290724 | 161 | void __iomem *sidpr; |
d96715c1 TH |
162 | }; |
163 | ||
2dcb407e JG |
164 | static int piix_init_one(struct pci_dev *pdev, |
165 | const struct pci_device_id *ent); | |
2852bcf7 | 166 | static void piix_remove_one(struct pci_dev *pdev); |
a1efdaba | 167 | static int piix_pata_prereset(struct ata_link *link, unsigned long deadline); |
2dcb407e JG |
168 | static void piix_set_piomode(struct ata_port *ap, struct ata_device *adev); |
169 | static void piix_set_dmamode(struct ata_port *ap, struct ata_device *adev); | |
170 | static void ich_set_dmamode(struct ata_port *ap, struct ata_device *adev); | |
eb4a2c7f | 171 | static int ich_pata_cable_detect(struct ata_port *ap); |
25f98131 | 172 | static u8 piix_vmw_bmdma_status(struct ata_port *ap); |
82ef04fb TH |
173 | static int piix_sidpr_scr_read(struct ata_link *link, |
174 | unsigned int reg, u32 *val); | |
175 | static int piix_sidpr_scr_write(struct ata_link *link, | |
176 | unsigned int reg, u32 val); | |
a97c4006 TH |
177 | static int piix_sidpr_set_lpm(struct ata_link *link, enum ata_lpm_policy policy, |
178 | unsigned hints); | |
27943620 | 179 | static bool piix_irq_check(struct ata_port *ap); |
b8b275ef TH |
180 | #ifdef CONFIG_PM |
181 | static int piix_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg); | |
182 | static int piix_pci_device_resume(struct pci_dev *pdev); | |
183 | #endif | |
1da177e4 LT |
184 | |
185 | static unsigned int in_module_init = 1; | |
186 | ||
3b7d697d | 187 | static const struct pci_device_id piix_pci_tbl[] = { |
d2cdfc0d A |
188 | /* Intel PIIX3 for the 430HX etc */ |
189 | { 0x8086, 0x7010, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_mwdma }, | |
25f98131 TH |
190 | /* VMware ICH4 */ |
191 | { 0x8086, 0x7111, 0x15ad, 0x1976, 0, 0, piix_pata_vmw }, | |
669a5db4 JG |
192 | /* Intel PIIX4 for the 430TX/440BX/MX chipset: UDMA 33 */ |
193 | /* Also PIIX4E (fn3 rev 2) and PIIX4M (fn3 rev 3) */ | |
194 | { 0x8086, 0x7111, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 }, | |
669a5db4 JG |
195 | /* Intel PIIX4 */ |
196 | { 0x8086, 0x7199, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 }, | |
197 | /* Intel PIIX4 */ | |
198 | { 0x8086, 0x7601, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 }, | |
199 | /* Intel PIIX */ | |
200 | { 0x8086, 0x84CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 }, | |
201 | /* Intel ICH (i810, i815, i840) UDMA 66*/ | |
202 | { 0x8086, 0x2411, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_66 }, | |
203 | /* Intel ICH0 : UDMA 33*/ | |
204 | { 0x8086, 0x2421, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_33 }, | |
205 | /* Intel ICH2M */ | |
206 | { 0x8086, 0x244A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, | |
207 | /* Intel ICH2 (i810E2, i845, 850, 860) UDMA 100 */ | |
208 | { 0x8086, 0x244B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, | |
209 | /* Intel ICH3M */ | |
210 | { 0x8086, 0x248A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, | |
211 | /* Intel ICH3 (E7500/1) UDMA 100 */ | |
212 | { 0x8086, 0x248B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, | |
4bb969db BH |
213 | /* Intel ICH4-L */ |
214 | { 0x8086, 0x24C1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, | |
669a5db4 JG |
215 | /* Intel ICH4 (i845GV, i845E, i852, i855) UDMA 100 */ |
216 | { 0x8086, 0x24CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, | |
217 | { 0x8086, 0x24CB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, | |
218 | /* Intel ICH5 */ | |
2eb829e9 | 219 | { 0x8086, 0x24DB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, |
669a5db4 JG |
220 | /* C-ICH (i810E2) */ |
221 | { 0x8086, 0x245B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, | |
85cd7251 | 222 | /* ESB (855GME/875P + 6300ESB) UDMA 100 */ |
669a5db4 JG |
223 | { 0x8086, 0x25A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, |
224 | /* ICH6 (and 6) (i915) UDMA 100 */ | |
225 | { 0x8086, 0x266F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, | |
226 | /* ICH7/7-R (i945, i975) UDMA 100*/ | |
c611bed7 AC |
227 | { 0x8086, 0x27DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100_nomwdma1 }, |
228 | { 0x8086, 0x269E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100_nomwdma1 }, | |
c1e6f28c CL |
229 | /* ICH8 Mobile PATA Controller */ |
230 | { 0x8086, 0x2850, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, | |
1da177e4 | 231 | |
7654db1a | 232 | /* SATA ports */ |
4fca377f | 233 | |
1d076e5b | 234 | /* 82801EB (ICH5) */ |
1da177e4 | 235 | { 0x8086, 0x24d1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata }, |
1d076e5b | 236 | /* 82801EB (ICH5) */ |
1da177e4 | 237 | { 0x8086, 0x24df, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata }, |
1d076e5b | 238 | /* 6300ESB (ICH5 variant with broken PCS present bits) */ |
5e56a37c | 239 | { 0x8086, 0x25a3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata }, |
1d076e5b | 240 | /* 6300ESB pretending RAID */ |
5e56a37c | 241 | { 0x8086, 0x25b0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata }, |
1d076e5b | 242 | /* 82801FB/FW (ICH6/ICH6W) */ |
1da177e4 | 243 | { 0x8086, 0x2651, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata }, |
1d076e5b | 244 | /* 82801FR/FRW (ICH6R/ICH6RW) */ |
9c0bf675 | 245 | { 0x8086, 0x2652, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata }, |
5016d7d2 TH |
246 | /* 82801FBM ICH6M (ICH6R with only port 0 and 2 implemented). |
247 | * Attach iff the controller is in IDE mode. */ | |
248 | { 0x8086, 0x2653, PCI_ANY_ID, PCI_ANY_ID, | |
9c0bf675 | 249 | PCI_CLASS_STORAGE_IDE << 8, 0xffff00, ich6m_sata }, |
1d076e5b | 250 | /* 82801GB/GR/GH (ICH7, identical to ICH6) */ |
9c0bf675 | 251 | { 0x8086, 0x27c0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata }, |
1d076e5b | 252 | /* 2801GBM/GHM (ICH7M, identical to ICH6M) */ |
9c0bf675 | 253 | { 0x8086, 0x27c4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6m_sata }, |
f98b6573 | 254 | /* Enterprise Southbridge 2 (631xESB/632xESB) */ |
9c0bf675 | 255 | { 0x8086, 0x2680, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata }, |
f98b6573 | 256 | /* SATA Controller 1 IDE (ICH8) */ |
9c0bf675 | 257 | { 0x8086, 0x2820, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata }, |
f98b6573 | 258 | /* SATA Controller 2 IDE (ICH8) */ |
00242ec8 | 259 | { 0x8086, 0x2825, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata }, |
8d8ef2fb | 260 | /* Mobile SATA Controller IDE (ICH8M), Apple */ |
9c0bf675 | 261 | { 0x8086, 0x2828, 0x106b, 0x00a0, 0, 0, ich8m_apple_sata }, |
23cf296e | 262 | { 0x8086, 0x2828, 0x106b, 0x00a1, 0, 0, ich8m_apple_sata }, |
487eff68 | 263 | { 0x8086, 0x2828, 0x106b, 0x00a3, 0, 0, ich8m_apple_sata }, |
23cf296e TH |
264 | /* Mobile SATA Controller IDE (ICH8M) */ |
265 | { 0x8086, 0x2828, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata }, | |
f98b6573 | 266 | /* SATA Controller IDE (ICH9) */ |
9c0bf675 | 267 | { 0x8086, 0x2920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata }, |
f98b6573 | 268 | /* SATA Controller IDE (ICH9) */ |
00242ec8 | 269 | { 0x8086, 0x2921, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata }, |
f98b6573 | 270 | /* SATA Controller IDE (ICH9) */ |
00242ec8 | 271 | { 0x8086, 0x2926, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata }, |
f98b6573 | 272 | /* SATA Controller IDE (ICH9M) */ |
00242ec8 | 273 | { 0x8086, 0x2928, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata }, |
f98b6573 | 274 | /* SATA Controller IDE (ICH9M) */ |
00242ec8 | 275 | { 0x8086, 0x292d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata }, |
f98b6573 | 276 | /* SATA Controller IDE (ICH9M) */ |
9c0bf675 | 277 | { 0x8086, 0x292e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata }, |
c5cf0ffa | 278 | /* SATA Controller IDE (Tolapai) */ |
9c0bf675 | 279 | { 0x8086, 0x5028, PCI_ANY_ID, PCI_ANY_ID, 0, 0, tolapai_sata }, |
bf7f22b9 | 280 | /* SATA Controller IDE (ICH10) */ |
9c0bf675 | 281 | { 0x8086, 0x3a00, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata }, |
bf7f22b9 JG |
282 | /* SATA Controller IDE (ICH10) */ |
283 | { 0x8086, 0x3a06, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata }, | |
284 | /* SATA Controller IDE (ICH10) */ | |
9c0bf675 | 285 | { 0x8086, 0x3a20, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata }, |
bf7f22b9 JG |
286 | /* SATA Controller IDE (ICH10) */ |
287 | { 0x8086, 0x3a26, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata }, | |
c6c6a1af SH |
288 | /* SATA Controller IDE (PCH) */ |
289 | { 0x8086, 0x3b20, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata }, | |
290 | /* SATA Controller IDE (PCH) */ | |
0395e61b SH |
291 | { 0x8086, 0x3b21, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata }, |
292 | /* SATA Controller IDE (PCH) */ | |
c6c6a1af SH |
293 | { 0x8086, 0x3b26, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata }, |
294 | /* SATA Controller IDE (PCH) */ | |
0395e61b SH |
295 | { 0x8086, 0x3b28, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata }, |
296 | /* SATA Controller IDE (PCH) */ | |
c6c6a1af SH |
297 | { 0x8086, 0x3b2d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata }, |
298 | /* SATA Controller IDE (PCH) */ | |
299 | { 0x8086, 0x3b2e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata }, | |
88e8201e SH |
300 | /* SATA Controller IDE (CPT) */ |
301 | { 0x8086, 0x1c00, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata }, | |
302 | /* SATA Controller IDE (CPT) */ | |
303 | { 0x8086, 0x1c01, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata }, | |
304 | /* SATA Controller IDE (CPT) */ | |
305 | { 0x8086, 0x1c08, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata }, | |
306 | /* SATA Controller IDE (CPT) */ | |
307 | { 0x8086, 0x1c09, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata }, | |
238e149c SH |
308 | /* SATA Controller IDE (PBG) */ |
309 | { 0x8086, 0x1d00, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata }, | |
310 | /* SATA Controller IDE (PBG) */ | |
311 | { 0x8086, 0x1d08, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata }, | |
4a836c70 SH |
312 | /* SATA Controller IDE (Panther Point) */ |
313 | { 0x8086, 0x1e00, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata }, | |
314 | /* SATA Controller IDE (Panther Point) */ | |
315 | { 0x8086, 0x1e01, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata }, | |
316 | /* SATA Controller IDE (Panther Point) */ | |
317 | { 0x8086, 0x1e08, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata }, | |
318 | /* SATA Controller IDE (Panther Point) */ | |
319 | { 0x8086, 0x1e09, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata }, | |
1da177e4 LT |
320 | { } /* terminate list */ |
321 | }; | |
322 | ||
323 | static struct pci_driver piix_pci_driver = { | |
324 | .name = DRV_NAME, | |
325 | .id_table = piix_pci_tbl, | |
326 | .probe = piix_init_one, | |
2852bcf7 | 327 | .remove = piix_remove_one, |
438ac6d5 | 328 | #ifdef CONFIG_PM |
b8b275ef TH |
329 | .suspend = piix_pci_device_suspend, |
330 | .resume = piix_pci_device_resume, | |
438ac6d5 | 331 | #endif |
1da177e4 LT |
332 | }; |
333 | ||
193515d5 | 334 | static struct scsi_host_template piix_sht = { |
68d1d07b | 335 | ATA_BMDMA_SHT(DRV_NAME), |
1da177e4 LT |
336 | }; |
337 | ||
27943620 | 338 | static struct ata_port_operations piix_sata_ops = { |
871af121 | 339 | .inherits = &ata_bmdma32_port_ops, |
27943620 TH |
340 | .sff_irq_check = piix_irq_check, |
341 | }; | |
342 | ||
343 | static struct ata_port_operations piix_pata_ops = { | |
344 | .inherits = &piix_sata_ops, | |
029cfd6b | 345 | .cable_detect = ata_cable_40wire, |
1da177e4 LT |
346 | .set_piomode = piix_set_piomode, |
347 | .set_dmamode = piix_set_dmamode, | |
a1efdaba | 348 | .prereset = piix_pata_prereset, |
1da177e4 LT |
349 | }; |
350 | ||
029cfd6b TH |
351 | static struct ata_port_operations piix_vmw_ops = { |
352 | .inherits = &piix_pata_ops, | |
353 | .bmdma_status = piix_vmw_bmdma_status, | |
669a5db4 JG |
354 | }; |
355 | ||
029cfd6b TH |
356 | static struct ata_port_operations ich_pata_ops = { |
357 | .inherits = &piix_pata_ops, | |
358 | .cable_detect = ich_pata_cable_detect, | |
359 | .set_dmamode = ich_set_dmamode, | |
1da177e4 LT |
360 | }; |
361 | ||
a97c4006 TH |
362 | static struct device_attribute *piix_sidpr_shost_attrs[] = { |
363 | &dev_attr_link_power_management_policy, | |
364 | NULL | |
365 | }; | |
366 | ||
367 | static struct scsi_host_template piix_sidpr_sht = { | |
368 | ATA_BMDMA_SHT(DRV_NAME), | |
369 | .shost_attrs = piix_sidpr_shost_attrs, | |
370 | }; | |
371 | ||
029cfd6b TH |
372 | static struct ata_port_operations piix_sidpr_sata_ops = { |
373 | .inherits = &piix_sata_ops, | |
57c9efdf | 374 | .hardreset = sata_std_hardreset, |
c7290724 TH |
375 | .scr_read = piix_sidpr_scr_read, |
376 | .scr_write = piix_sidpr_scr_write, | |
a97c4006 | 377 | .set_lpm = piix_sidpr_set_lpm, |
c7290724 TH |
378 | }; |
379 | ||
d96715c1 | 380 | static const struct piix_map_db ich5_map_db = { |
d33f58b8 | 381 | .mask = 0x7, |
ea35d29e | 382 | .port_enable = 0x3, |
d33f58b8 TH |
383 | .map = { |
384 | /* PM PS SM SS MAP */ | |
385 | { P0, NA, P1, NA }, /* 000b */ | |
386 | { P1, NA, P0, NA }, /* 001b */ | |
387 | { RV, RV, RV, RV }, | |
388 | { RV, RV, RV, RV }, | |
389 | { P0, P1, IDE, IDE }, /* 100b */ | |
390 | { P1, P0, IDE, IDE }, /* 101b */ | |
391 | { IDE, IDE, P0, P1 }, /* 110b */ | |
392 | { IDE, IDE, P1, P0 }, /* 111b */ | |
393 | }, | |
394 | }; | |
395 | ||
d96715c1 | 396 | static const struct piix_map_db ich6_map_db = { |
d33f58b8 | 397 | .mask = 0x3, |
ea35d29e | 398 | .port_enable = 0xf, |
d33f58b8 TH |
399 | .map = { |
400 | /* PM PS SM SS MAP */ | |
79ea24e7 | 401 | { P0, P2, P1, P3 }, /* 00b */ |
d33f58b8 TH |
402 | { IDE, IDE, P1, P3 }, /* 01b */ |
403 | { P0, P2, IDE, IDE }, /* 10b */ | |
404 | { RV, RV, RV, RV }, | |
405 | }, | |
406 | }; | |
407 | ||
d96715c1 | 408 | static const struct piix_map_db ich6m_map_db = { |
d33f58b8 | 409 | .mask = 0x3, |
ea35d29e | 410 | .port_enable = 0x5, |
67083741 TH |
411 | |
412 | /* Map 01b isn't specified in the doc but some notebooks use | |
c6446a4c TH |
413 | * it anyway. MAP 01b have been spotted on both ICH6M and |
414 | * ICH7M. | |
67083741 TH |
415 | */ |
416 | .map = { | |
417 | /* PM PS SM SS MAP */ | |
e04b3b9d | 418 | { P0, P2, NA, NA }, /* 00b */ |
67083741 TH |
419 | { IDE, IDE, P1, P3 }, /* 01b */ |
420 | { P0, P2, IDE, IDE }, /* 10b */ | |
421 | { RV, RV, RV, RV }, | |
422 | }, | |
423 | }; | |
424 | ||
08f12edc JG |
425 | static const struct piix_map_db ich8_map_db = { |
426 | .mask = 0x3, | |
a0ce9aca | 427 | .port_enable = 0xf, |
08f12edc JG |
428 | .map = { |
429 | /* PM PS SM SS MAP */ | |
158f30c8 | 430 | { P0, P2, P1, P3 }, /* 00b (hardwired when in AHCI) */ |
08f12edc | 431 | { RV, RV, RV, RV }, |
ac2b0437 | 432 | { P0, P2, IDE, IDE }, /* 10b (IDE mode) */ |
08f12edc JG |
433 | { RV, RV, RV, RV }, |
434 | }, | |
435 | }; | |
436 | ||
00242ec8 | 437 | static const struct piix_map_db ich8_2port_map_db = { |
e2d352af JG |
438 | .mask = 0x3, |
439 | .port_enable = 0x3, | |
440 | .map = { | |
441 | /* PM PS SM SS MAP */ | |
442 | { P0, NA, P1, NA }, /* 00b */ | |
443 | { RV, RV, RV, RV }, /* 01b */ | |
444 | { RV, RV, RV, RV }, /* 10b */ | |
445 | { RV, RV, RV, RV }, | |
446 | }, | |
c5cf0ffa JG |
447 | }; |
448 | ||
8d8ef2fb TR |
449 | static const struct piix_map_db ich8m_apple_map_db = { |
450 | .mask = 0x3, | |
451 | .port_enable = 0x1, | |
452 | .map = { | |
453 | /* PM PS SM SS MAP */ | |
454 | { P0, NA, NA, NA }, /* 00b */ | |
455 | { RV, RV, RV, RV }, | |
456 | { P0, P2, IDE, IDE }, /* 10b */ | |
457 | { RV, RV, RV, RV }, | |
458 | }, | |
459 | }; | |
460 | ||
00242ec8 | 461 | static const struct piix_map_db tolapai_map_db = { |
8f73a688 JG |
462 | .mask = 0x3, |
463 | .port_enable = 0x3, | |
464 | .map = { | |
465 | /* PM PS SM SS MAP */ | |
466 | { P0, NA, P1, NA }, /* 00b */ | |
467 | { RV, RV, RV, RV }, /* 01b */ | |
468 | { RV, RV, RV, RV }, /* 10b */ | |
469 | { RV, RV, RV, RV }, | |
470 | }, | |
471 | }; | |
472 | ||
d96715c1 TH |
473 | static const struct piix_map_db *piix_map_db_table[] = { |
474 | [ich5_sata] = &ich5_map_db, | |
d96715c1 | 475 | [ich6_sata] = &ich6_map_db, |
9c0bf675 TH |
476 | [ich6m_sata] = &ich6m_map_db, |
477 | [ich8_sata] = &ich8_map_db, | |
00242ec8 | 478 | [ich8_2port_sata] = &ich8_2port_map_db, |
9c0bf675 TH |
479 | [ich8m_apple_sata] = &ich8m_apple_map_db, |
480 | [tolapai_sata] = &tolapai_map_db, | |
d96715c1 TH |
481 | }; |
482 | ||
1da177e4 | 483 | static struct ata_port_info piix_port_info[] = { |
00242ec8 TH |
484 | [piix_pata_mwdma] = /* PIIX3 MWDMA only */ |
485 | { | |
00242ec8 | 486 | .flags = PIIX_PATA_FLAGS, |
14bdef98 EIB |
487 | .pio_mask = ATA_PIO4, |
488 | .mwdma_mask = ATA_MWDMA12_ONLY, /* mwdma1-2 ?? CHECK 0 should be ok but slow */ | |
00242ec8 TH |
489 | .port_ops = &piix_pata_ops, |
490 | }, | |
491 | ||
ec300d99 | 492 | [piix_pata_33] = /* PIIX4 at 33MHz */ |
1d076e5b | 493 | { |
b3362f88 | 494 | .flags = PIIX_PATA_FLAGS, |
14bdef98 EIB |
495 | .pio_mask = ATA_PIO4, |
496 | .mwdma_mask = ATA_MWDMA12_ONLY, /* mwdma1-2 ?? CHECK 0 should be ok but slow */ | |
497 | .udma_mask = ATA_UDMA2, | |
1d076e5b TH |
498 | .port_ops = &piix_pata_ops, |
499 | }, | |
500 | ||
ec300d99 | 501 | [ich_pata_33] = /* ICH0 - ICH at 33Mhz*/ |
669a5db4 | 502 | { |
b3362f88 | 503 | .flags = PIIX_PATA_FLAGS, |
14bdef98 EIB |
504 | .pio_mask = ATA_PIO4, |
505 | .mwdma_mask = ATA_MWDMA12_ONLY, /* Check: maybe MWDMA0 is ok */ | |
506 | .udma_mask = ATA_UDMA2, | |
669a5db4 JG |
507 | .port_ops = &ich_pata_ops, |
508 | }, | |
ec300d99 JG |
509 | |
510 | [ich_pata_66] = /* ICH controllers up to 66MHz */ | |
1da177e4 | 511 | { |
b3362f88 | 512 | .flags = PIIX_PATA_FLAGS, |
14bdef98 EIB |
513 | .pio_mask = ATA_PIO4, |
514 | .mwdma_mask = ATA_MWDMA12_ONLY, /* MWDMA0 is broken on chip */ | |
669a5db4 JG |
515 | .udma_mask = ATA_UDMA4, |
516 | .port_ops = &ich_pata_ops, | |
517 | }, | |
85cd7251 | 518 | |
ec300d99 | 519 | [ich_pata_100] = |
669a5db4 | 520 | { |
b3362f88 | 521 | .flags = PIIX_PATA_FLAGS | PIIX_FLAG_CHECKINTR, |
14bdef98 EIB |
522 | .pio_mask = ATA_PIO4, |
523 | .mwdma_mask = ATA_MWDMA12_ONLY, | |
524 | .udma_mask = ATA_UDMA5, | |
669a5db4 | 525 | .port_ops = &ich_pata_ops, |
1da177e4 LT |
526 | }, |
527 | ||
c611bed7 AC |
528 | [ich_pata_100_nomwdma1] = |
529 | { | |
530 | .flags = PIIX_PATA_FLAGS | PIIX_FLAG_CHECKINTR, | |
531 | .pio_mask = ATA_PIO4, | |
532 | .mwdma_mask = ATA_MWDMA2_ONLY, | |
533 | .udma_mask = ATA_UDMA5, | |
534 | .port_ops = &ich_pata_ops, | |
535 | }, | |
536 | ||
ec300d99 | 537 | [ich5_sata] = |
1da177e4 | 538 | { |
228c1590 | 539 | .flags = PIIX_SATA_FLAGS, |
14bdef98 EIB |
540 | .pio_mask = ATA_PIO4, |
541 | .mwdma_mask = ATA_MWDMA2, | |
bf6263a8 | 542 | .udma_mask = ATA_UDMA6, |
1da177e4 LT |
543 | .port_ops = &piix_sata_ops, |
544 | }, | |
545 | ||
ec300d99 | 546 | [ich6_sata] = |
1da177e4 | 547 | { |
723159c5 | 548 | .flags = PIIX_SATA_FLAGS, |
14bdef98 EIB |
549 | .pio_mask = ATA_PIO4, |
550 | .mwdma_mask = ATA_MWDMA2, | |
bf6263a8 | 551 | .udma_mask = ATA_UDMA6, |
1da177e4 LT |
552 | .port_ops = &piix_sata_ops, |
553 | }, | |
554 | ||
9c0bf675 | 555 | [ich6m_sata] = |
c368ca4e | 556 | { |
5016d7d2 | 557 | .flags = PIIX_SATA_FLAGS, |
14bdef98 EIB |
558 | .pio_mask = ATA_PIO4, |
559 | .mwdma_mask = ATA_MWDMA2, | |
bf6263a8 | 560 | .udma_mask = ATA_UDMA6, |
c368ca4e JG |
561 | .port_ops = &piix_sata_ops, |
562 | }, | |
1d076e5b | 563 | |
9c0bf675 | 564 | [ich8_sata] = |
08f12edc | 565 | { |
5016d7d2 | 566 | .flags = PIIX_SATA_FLAGS | PIIX_FLAG_SIDPR, |
14bdef98 EIB |
567 | .pio_mask = ATA_PIO4, |
568 | .mwdma_mask = ATA_MWDMA2, | |
bf6263a8 | 569 | .udma_mask = ATA_UDMA6, |
08f12edc JG |
570 | .port_ops = &piix_sata_ops, |
571 | }, | |
669a5db4 | 572 | |
00242ec8 | 573 | [ich8_2port_sata] = |
c5cf0ffa | 574 | { |
5016d7d2 | 575 | .flags = PIIX_SATA_FLAGS | PIIX_FLAG_SIDPR, |
14bdef98 EIB |
576 | .pio_mask = ATA_PIO4, |
577 | .mwdma_mask = ATA_MWDMA2, | |
c5cf0ffa JG |
578 | .udma_mask = ATA_UDMA6, |
579 | .port_ops = &piix_sata_ops, | |
580 | }, | |
8f73a688 | 581 | |
9c0bf675 | 582 | [tolapai_sata] = |
8f73a688 | 583 | { |
5016d7d2 | 584 | .flags = PIIX_SATA_FLAGS, |
14bdef98 EIB |
585 | .pio_mask = ATA_PIO4, |
586 | .mwdma_mask = ATA_MWDMA2, | |
8f73a688 JG |
587 | .udma_mask = ATA_UDMA6, |
588 | .port_ops = &piix_sata_ops, | |
589 | }, | |
8d8ef2fb | 590 | |
9c0bf675 | 591 | [ich8m_apple_sata] = |
8d8ef2fb | 592 | { |
23cf296e | 593 | .flags = PIIX_SATA_FLAGS, |
14bdef98 EIB |
594 | .pio_mask = ATA_PIO4, |
595 | .mwdma_mask = ATA_MWDMA2, | |
8d8ef2fb TR |
596 | .udma_mask = ATA_UDMA6, |
597 | .port_ops = &piix_sata_ops, | |
598 | }, | |
599 | ||
25f98131 TH |
600 | [piix_pata_vmw] = |
601 | { | |
25f98131 | 602 | .flags = PIIX_PATA_FLAGS, |
14bdef98 EIB |
603 | .pio_mask = ATA_PIO4, |
604 | .mwdma_mask = ATA_MWDMA12_ONLY, /* mwdma1-2 ?? CHECK 0 should be ok but slow */ | |
605 | .udma_mask = ATA_UDMA2, | |
25f98131 TH |
606 | .port_ops = &piix_vmw_ops, |
607 | }, | |
608 | ||
1da177e4 LT |
609 | }; |
610 | ||
611 | static struct pci_bits piix_enable_bits[] = { | |
612 | { 0x41U, 1U, 0x80UL, 0x80UL }, /* port 0 */ | |
613 | { 0x43U, 1U, 0x80UL, 0x80UL }, /* port 1 */ | |
614 | }; | |
615 | ||
616 | MODULE_AUTHOR("Andre Hedrick, Alan Cox, Andrzej Krzysztofowicz, Jeff Garzik"); | |
617 | MODULE_DESCRIPTION("SCSI low-level driver for Intel PIIX/ICH ATA controllers"); | |
618 | MODULE_LICENSE("GPL"); | |
619 | MODULE_DEVICE_TABLE(pci, piix_pci_tbl); | |
620 | MODULE_VERSION(DRV_VERSION); | |
621 | ||
fc085150 AC |
622 | struct ich_laptop { |
623 | u16 device; | |
624 | u16 subvendor; | |
625 | u16 subdevice; | |
626 | }; | |
627 | ||
628 | /* | |
629 | * List of laptops that use short cables rather than 80 wire | |
630 | */ | |
631 | ||
632 | static const struct ich_laptop ich_laptop[] = { | |
633 | /* devid, subvendor, subdev */ | |
634 | { 0x27DF, 0x0005, 0x0280 }, /* ICH7 on Acer 5602WLMi */ | |
2655e2ce | 635 | { 0x27DF, 0x1025, 0x0102 }, /* ICH7 on Acer 5602aWLMi */ |
babfb682 | 636 | { 0x27DF, 0x1025, 0x0110 }, /* ICH7 on Acer 3682WLMi */ |
6034734d | 637 | { 0x27DF, 0x1028, 0x02b0 }, /* ICH7 on unknown Dell */ |
12340106 | 638 | { 0x27DF, 0x1043, 0x1267 }, /* ICH7 on Asus W5F */ |
54174db3 | 639 | { 0x27DF, 0x103C, 0x30A1 }, /* ICH7 on HP Compaq nc2400 */ |
af901ca1 | 640 | { 0x27DF, 0x103C, 0x361a }, /* ICH7 on unknown HP */ |
d09addf6 | 641 | { 0x27DF, 0x1071, 0xD221 }, /* ICH7 on Hercules EC-900 */ |
6034734d | 642 | { 0x27DF, 0x152D, 0x0778 }, /* ICH7 on unknown Intel */ |
b33620f9 | 643 | { 0x24CA, 0x1025, 0x0061 }, /* ICH4 on ACER Aspire 2023WLMi */ |
e1fefea9 CIK |
644 | { 0x24CA, 0x1025, 0x003d }, /* ICH4 on ACER TM290 */ |
645 | { 0x266F, 0x1025, 0x0066 }, /* ICH6 on ACER Aspire 1694WLMi */ | |
01ce2601 | 646 | { 0x2653, 0x1043, 0x82D8 }, /* ICH6M on Asus Eee 701 */ |
124a6eec | 647 | { 0x27df, 0x104d, 0x900e }, /* ICH7 on Sony TZ-90 */ |
fc085150 AC |
648 | /* end marker */ |
649 | { 0, } | |
650 | }; | |
651 | ||
1da177e4 | 652 | /** |
eb4a2c7f | 653 | * ich_pata_cable_detect - Probe host controller cable detect info |
1da177e4 LT |
654 | * @ap: Port for which cable detect info is desired |
655 | * | |
656 | * Read 80c cable indicator from ATA PCI device's PCI config | |
657 | * register. This register is normally set by firmware (BIOS). | |
658 | * | |
659 | * LOCKING: | |
660 | * None (inherited from caller). | |
661 | */ | |
669a5db4 | 662 | |
eb4a2c7f | 663 | static int ich_pata_cable_detect(struct ata_port *ap) |
1da177e4 | 664 | { |
cca3974e | 665 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); |
2852bcf7 | 666 | struct piix_host_priv *hpriv = ap->host->private_data; |
fc085150 | 667 | const struct ich_laptop *lap = &ich_laptop[0]; |
2852bcf7 | 668 | u8 mask; |
1da177e4 | 669 | |
fc085150 AC |
670 | /* Check for specials - Acer Aspire 5602WLMi */ |
671 | while (lap->device) { | |
672 | if (lap->device == pdev->device && | |
673 | lap->subvendor == pdev->subsystem_vendor && | |
2dcb407e | 674 | lap->subdevice == pdev->subsystem_device) |
eb4a2c7f | 675 | return ATA_CBL_PATA40_SHORT; |
2dcb407e | 676 | |
fc085150 AC |
677 | lap++; |
678 | } | |
679 | ||
1da177e4 | 680 | /* check BIOS cable detect results */ |
2a88d1ac | 681 | mask = ap->port_no == 0 ? PIIX_80C_PRI : PIIX_80C_SEC; |
2852bcf7 | 682 | if ((hpriv->saved_iocfg & mask) == 0) |
eb4a2c7f AC |
683 | return ATA_CBL_PATA40; |
684 | return ATA_CBL_PATA80; | |
1da177e4 LT |
685 | } |
686 | ||
687 | /** | |
ccc4672a | 688 | * piix_pata_prereset - prereset for PATA host controller |
cc0680a5 | 689 | * @link: Target link |
d4b2bab4 | 690 | * @deadline: deadline jiffies for the operation |
1da177e4 | 691 | * |
573db6b8 TH |
692 | * LOCKING: |
693 | * None (inherited from caller). | |
694 | */ | |
cc0680a5 | 695 | static int piix_pata_prereset(struct ata_link *link, unsigned long deadline) |
1da177e4 | 696 | { |
cc0680a5 | 697 | struct ata_port *ap = link->ap; |
cca3974e | 698 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); |
1da177e4 | 699 | |
c961922b AC |
700 | if (!pci_test_config_bits(pdev, &piix_enable_bits[ap->port_no])) |
701 | return -ENOENT; | |
9363c382 | 702 | return ata_sff_prereset(link, deadline); |
ccc4672a TH |
703 | } |
704 | ||
60c3be38 BZ |
705 | static DEFINE_SPINLOCK(piix_lock); |
706 | ||
1da177e4 LT |
707 | /** |
708 | * piix_set_piomode - Initialize host controller PATA PIO timings | |
709 | * @ap: Port whose timings we are configuring | |
710 | * @adev: um | |
1da177e4 LT |
711 | * |
712 | * Set PIO mode for device, in host controller PCI config space. | |
713 | * | |
714 | * LOCKING: | |
715 | * None (inherited from caller). | |
716 | */ | |
717 | ||
2dcb407e | 718 | static void piix_set_piomode(struct ata_port *ap, struct ata_device *adev) |
1da177e4 | 719 | { |
cca3974e | 720 | struct pci_dev *dev = to_pci_dev(ap->host->dev); |
60c3be38 BZ |
721 | unsigned long flags; |
722 | unsigned int pio = adev->pio_mode - XFER_PIO_0; | |
1da177e4 | 723 | unsigned int is_slave = (adev->devno != 0); |
2a88d1ac | 724 | unsigned int master_port= ap->port_no ? 0x42 : 0x40; |
1da177e4 LT |
725 | unsigned int slave_port = 0x44; |
726 | u16 master_data; | |
727 | u8 slave_data; | |
669a5db4 JG |
728 | u8 udma_enable; |
729 | int control = 0; | |
85cd7251 | 730 | |
669a5db4 JG |
731 | /* |
732 | * See Intel Document 298600-004 for the timing programing rules | |
733 | * for ICH controllers. | |
734 | */ | |
1da177e4 LT |
735 | |
736 | static const /* ISP RTC */ | |
737 | u8 timings[][2] = { { 0, 0 }, | |
738 | { 0, 0 }, | |
739 | { 1, 0 }, | |
740 | { 2, 1 }, | |
741 | { 2, 3 }, }; | |
742 | ||
669a5db4 JG |
743 | if (pio >= 2) |
744 | control |= 1; /* TIME1 enable */ | |
745 | if (ata_pio_need_iordy(adev)) | |
746 | control |= 2; /* IE enable */ | |
747 | ||
85cd7251 | 748 | /* Intel specifies that the PPE functionality is for disk only */ |
669a5db4 JG |
749 | if (adev->class == ATA_DEV_ATA) |
750 | control |= 4; /* PPE enable */ | |
751 | ||
60c3be38 BZ |
752 | spin_lock_irqsave(&piix_lock, flags); |
753 | ||
a5bf5f5a TH |
754 | /* PIO configuration clears DTE unconditionally. It will be |
755 | * programmed in set_dmamode which is guaranteed to be called | |
756 | * after set_piomode if any DMA mode is available. | |
757 | */ | |
1da177e4 LT |
758 | pci_read_config_word(dev, master_port, &master_data); |
759 | if (is_slave) { | |
a5bf5f5a TH |
760 | /* clear TIME1|IE1|PPE1|DTE1 */ |
761 | master_data &= 0xff0f; | |
1967b7ff | 762 | /* Enable SITRE (separate slave timing register) */ |
1da177e4 | 763 | master_data |= 0x4000; |
669a5db4 JG |
764 | /* enable PPE1, IE1 and TIME1 as needed */ |
765 | master_data |= (control << 4); | |
1da177e4 | 766 | pci_read_config_byte(dev, slave_port, &slave_data); |
2a88d1ac | 767 | slave_data &= (ap->port_no ? 0x0f : 0xf0); |
669a5db4 | 768 | /* Load the timing nibble for this slave */ |
a5bf5f5a TH |
769 | slave_data |= ((timings[pio][0] << 2) | timings[pio][1]) |
770 | << (ap->port_no ? 4 : 0); | |
1da177e4 | 771 | } else { |
a5bf5f5a TH |
772 | /* clear ISP|RCT|TIME0|IE0|PPE0|DTE0 */ |
773 | master_data &= 0xccf0; | |
669a5db4 JG |
774 | /* Enable PPE, IE and TIME as appropriate */ |
775 | master_data |= control; | |
a5bf5f5a | 776 | /* load ISP and RCT */ |
1da177e4 LT |
777 | master_data |= |
778 | (timings[pio][0] << 12) | | |
779 | (timings[pio][1] << 8); | |
780 | } | |
781 | pci_write_config_word(dev, master_port, master_data); | |
782 | if (is_slave) | |
783 | pci_write_config_byte(dev, slave_port, slave_data); | |
669a5db4 JG |
784 | |
785 | /* Ensure the UDMA bit is off - it will be turned back on if | |
786 | UDMA is selected */ | |
85cd7251 | 787 | |
669a5db4 JG |
788 | if (ap->udma_mask) { |
789 | pci_read_config_byte(dev, 0x48, &udma_enable); | |
790 | udma_enable &= ~(1 << (2 * ap->port_no + adev->devno)); | |
791 | pci_write_config_byte(dev, 0x48, udma_enable); | |
792 | } | |
60c3be38 BZ |
793 | |
794 | spin_unlock_irqrestore(&piix_lock, flags); | |
1da177e4 LT |
795 | } |
796 | ||
797 | /** | |
669a5db4 | 798 | * do_pata_set_dmamode - Initialize host controller PATA PIO timings |
1da177e4 | 799 | * @ap: Port whose timings we are configuring |
669a5db4 | 800 | * @adev: Drive in question |
c32a8fd7 | 801 | * @isich: set if the chip is an ICH device |
1da177e4 LT |
802 | * |
803 | * Set UDMA mode for device, in host controller PCI config space. | |
804 | * | |
805 | * LOCKING: | |
806 | * None (inherited from caller). | |
807 | */ | |
808 | ||
2dcb407e | 809 | static void do_pata_set_dmamode(struct ata_port *ap, struct ata_device *adev, int isich) |
1da177e4 | 810 | { |
cca3974e | 811 | struct pci_dev *dev = to_pci_dev(ap->host->dev); |
60c3be38 | 812 | unsigned long flags; |
669a5db4 JG |
813 | u8 master_port = ap->port_no ? 0x42 : 0x40; |
814 | u16 master_data; | |
815 | u8 speed = adev->dma_mode; | |
816 | int devid = adev->devno + 2 * ap->port_no; | |
dedf61db | 817 | u8 udma_enable = 0; |
85cd7251 | 818 | |
669a5db4 JG |
819 | static const /* ISP RTC */ |
820 | u8 timings[][2] = { { 0, 0 }, | |
821 | { 0, 0 }, | |
822 | { 1, 0 }, | |
823 | { 2, 1 }, | |
824 | { 2, 3 }, }; | |
825 | ||
60c3be38 BZ |
826 | spin_lock_irqsave(&piix_lock, flags); |
827 | ||
669a5db4 | 828 | pci_read_config_word(dev, master_port, &master_data); |
d2cdfc0d A |
829 | if (ap->udma_mask) |
830 | pci_read_config_byte(dev, 0x48, &udma_enable); | |
1da177e4 LT |
831 | |
832 | if (speed >= XFER_UDMA_0) { | |
669a5db4 JG |
833 | unsigned int udma = adev->dma_mode - XFER_UDMA_0; |
834 | u16 udma_timing; | |
835 | u16 ideconf; | |
836 | int u_clock, u_speed; | |
85cd7251 | 837 | |
669a5db4 | 838 | /* |
2dcb407e | 839 | * UDMA is handled by a combination of clock switching and |
85cd7251 JG |
840 | * selection of dividers |
841 | * | |
669a5db4 | 842 | * Handy rule: Odd modes are UDMATIMx 01, even are 02 |
85cd7251 | 843 | * except UDMA0 which is 00 |
669a5db4 JG |
844 | */ |
845 | u_speed = min(2 - (udma & 1), udma); | |
846 | if (udma == 5) | |
847 | u_clock = 0x1000; /* 100Mhz */ | |
848 | else if (udma > 2) | |
849 | u_clock = 1; /* 66Mhz */ | |
850 | else | |
851 | u_clock = 0; /* 33Mhz */ | |
85cd7251 | 852 | |
669a5db4 | 853 | udma_enable |= (1 << devid); |
85cd7251 | 854 | |
669a5db4 JG |
855 | /* Load the CT/RP selection */ |
856 | pci_read_config_word(dev, 0x4A, &udma_timing); | |
857 | udma_timing &= ~(3 << (4 * devid)); | |
858 | udma_timing |= u_speed << (4 * devid); | |
859 | pci_write_config_word(dev, 0x4A, udma_timing); | |
860 | ||
85cd7251 | 861 | if (isich) { |
669a5db4 JG |
862 | /* Select a 33/66/100Mhz clock */ |
863 | pci_read_config_word(dev, 0x54, &ideconf); | |
864 | ideconf &= ~(0x1001 << devid); | |
865 | ideconf |= u_clock << devid; | |
866 | /* For ICH or later we should set bit 10 for better | |
867 | performance (WR_PingPong_En) */ | |
868 | pci_write_config_word(dev, 0x54, ideconf); | |
1da177e4 | 869 | } |
1da177e4 | 870 | } else { |
669a5db4 JG |
871 | /* |
872 | * MWDMA is driven by the PIO timings. We must also enable | |
873 | * IORDY unconditionally along with TIME1. PPE has already | |
874 | * been set when the PIO timing was set. | |
875 | */ | |
876 | unsigned int mwdma = adev->dma_mode - XFER_MW_DMA_0; | |
877 | unsigned int control; | |
878 | u8 slave_data; | |
879 | const unsigned int needed_pio[3] = { | |
880 | XFER_PIO_0, XFER_PIO_3, XFER_PIO_4 | |
881 | }; | |
882 | int pio = needed_pio[mwdma] - XFER_PIO_0; | |
85cd7251 | 883 | |
669a5db4 | 884 | control = 3; /* IORDY|TIME1 */ |
85cd7251 | 885 | |
669a5db4 JG |
886 | /* If the drive MWDMA is faster than it can do PIO then |
887 | we must force PIO into PIO0 */ | |
85cd7251 | 888 | |
669a5db4 JG |
889 | if (adev->pio_mode < needed_pio[mwdma]) |
890 | /* Enable DMA timing only */ | |
891 | control |= 8; /* PIO cycles in PIO0 */ | |
892 | ||
893 | if (adev->devno) { /* Slave */ | |
894 | master_data &= 0xFF4F; /* Mask out IORDY|TIME1|DMAONLY */ | |
895 | master_data |= control << 4; | |
896 | pci_read_config_byte(dev, 0x44, &slave_data); | |
a5bf5f5a | 897 | slave_data &= (ap->port_no ? 0x0f : 0xf0); |
669a5db4 JG |
898 | /* Load the matching timing */ |
899 | slave_data |= ((timings[pio][0] << 2) | timings[pio][1]) << (ap->port_no ? 4 : 0); | |
900 | pci_write_config_byte(dev, 0x44, slave_data); | |
901 | } else { /* Master */ | |
85cd7251 | 902 | master_data &= 0xCCF4; /* Mask out IORDY|TIME1|DMAONLY |
669a5db4 JG |
903 | and master timing bits */ |
904 | master_data |= control; | |
905 | master_data |= | |
906 | (timings[pio][0] << 12) | | |
907 | (timings[pio][1] << 8); | |
908 | } | |
a5bf5f5a | 909 | |
69385943 | 910 | if (ap->udma_mask) |
a5bf5f5a | 911 | udma_enable &= ~(1 << devid); |
69385943 BZ |
912 | |
913 | pci_write_config_word(dev, master_port, master_data); | |
1da177e4 | 914 | } |
669a5db4 JG |
915 | /* Don't scribble on 0x48 if the controller does not support UDMA */ |
916 | if (ap->udma_mask) | |
917 | pci_write_config_byte(dev, 0x48, udma_enable); | |
60c3be38 BZ |
918 | |
919 | spin_unlock_irqrestore(&piix_lock, flags); | |
669a5db4 JG |
920 | } |
921 | ||
922 | /** | |
923 | * piix_set_dmamode - Initialize host controller PATA DMA timings | |
924 | * @ap: Port whose timings we are configuring | |
925 | * @adev: um | |
926 | * | |
927 | * Set MW/UDMA mode for device, in host controller PCI config space. | |
928 | * | |
929 | * LOCKING: | |
930 | * None (inherited from caller). | |
931 | */ | |
932 | ||
2dcb407e | 933 | static void piix_set_dmamode(struct ata_port *ap, struct ata_device *adev) |
669a5db4 JG |
934 | { |
935 | do_pata_set_dmamode(ap, adev, 0); | |
936 | } | |
937 | ||
938 | /** | |
939 | * ich_set_dmamode - Initialize host controller PATA DMA timings | |
940 | * @ap: Port whose timings we are configuring | |
941 | * @adev: um | |
942 | * | |
943 | * Set MW/UDMA mode for device, in host controller PCI config space. | |
944 | * | |
945 | * LOCKING: | |
946 | * None (inherited from caller). | |
947 | */ | |
948 | ||
2dcb407e | 949 | static void ich_set_dmamode(struct ata_port *ap, struct ata_device *adev) |
669a5db4 JG |
950 | { |
951 | do_pata_set_dmamode(ap, adev, 1); | |
1da177e4 LT |
952 | } |
953 | ||
c7290724 TH |
954 | /* |
955 | * Serial ATA Index/Data Pair Superset Registers access | |
956 | * | |
957 | * Beginning from ICH8, there's a sane way to access SCRs using index | |
be77e43a TH |
958 | * and data register pair located at BAR5 which means that we have |
959 | * separate SCRs for master and slave. This is handled using libata | |
960 | * slave_link facility. | |
c7290724 TH |
961 | */ |
962 | static const int piix_sidx_map[] = { | |
963 | [SCR_STATUS] = 0, | |
964 | [SCR_ERROR] = 2, | |
965 | [SCR_CONTROL] = 1, | |
966 | }; | |
967 | ||
be77e43a | 968 | static void piix_sidpr_sel(struct ata_link *link, unsigned int reg) |
c7290724 | 969 | { |
be77e43a | 970 | struct ata_port *ap = link->ap; |
c7290724 TH |
971 | struct piix_host_priv *hpriv = ap->host->private_data; |
972 | ||
be77e43a | 973 | iowrite32(((ap->port_no * 2 + link->pmp) << 8) | piix_sidx_map[reg], |
c7290724 TH |
974 | hpriv->sidpr + PIIX_SIDPR_IDX); |
975 | } | |
976 | ||
82ef04fb TH |
977 | static int piix_sidpr_scr_read(struct ata_link *link, |
978 | unsigned int reg, u32 *val) | |
c7290724 | 979 | { |
be77e43a | 980 | struct piix_host_priv *hpriv = link->ap->host->private_data; |
c7290724 TH |
981 | |
982 | if (reg >= ARRAY_SIZE(piix_sidx_map)) | |
983 | return -EINVAL; | |
984 | ||
be77e43a TH |
985 | piix_sidpr_sel(link, reg); |
986 | *val = ioread32(hpriv->sidpr + PIIX_SIDPR_DATA); | |
c7290724 TH |
987 | return 0; |
988 | } | |
989 | ||
82ef04fb TH |
990 | static int piix_sidpr_scr_write(struct ata_link *link, |
991 | unsigned int reg, u32 val) | |
c7290724 | 992 | { |
be77e43a | 993 | struct piix_host_priv *hpriv = link->ap->host->private_data; |
82ef04fb | 994 | |
c7290724 TH |
995 | if (reg >= ARRAY_SIZE(piix_sidx_map)) |
996 | return -EINVAL; | |
997 | ||
be77e43a TH |
998 | piix_sidpr_sel(link, reg); |
999 | iowrite32(val, hpriv->sidpr + PIIX_SIDPR_DATA); | |
c7290724 TH |
1000 | return 0; |
1001 | } | |
1002 | ||
a97c4006 TH |
1003 | static int piix_sidpr_set_lpm(struct ata_link *link, enum ata_lpm_policy policy, |
1004 | unsigned hints) | |
1005 | { | |
1006 | return sata_link_scr_lpm(link, policy, false); | |
1007 | } | |
1008 | ||
27943620 TH |
1009 | static bool piix_irq_check(struct ata_port *ap) |
1010 | { | |
1011 | if (unlikely(!ap->ioaddr.bmdma_addr)) | |
1012 | return false; | |
1013 | ||
1014 | return ap->ops->bmdma_status(ap) & ATA_DMA_INTR; | |
1015 | } | |
1016 | ||
b8b275ef | 1017 | #ifdef CONFIG_PM |
8c3832eb TH |
1018 | static int piix_broken_suspend(void) |
1019 | { | |
1855256c | 1020 | static const struct dmi_system_id sysids[] = { |
4c74d4ec TH |
1021 | { |
1022 | .ident = "TECRA M3", | |
1023 | .matches = { | |
1024 | DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), | |
1025 | DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M3"), | |
1026 | }, | |
1027 | }, | |
04d86d6f PS |
1028 | { |
1029 | .ident = "TECRA M3", | |
1030 | .matches = { | |
1031 | DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), | |
1032 | DMI_MATCH(DMI_PRODUCT_NAME, "Tecra M3"), | |
1033 | }, | |
1034 | }, | |
d1aa690a PS |
1035 | { |
1036 | .ident = "TECRA M4", | |
1037 | .matches = { | |
1038 | DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), | |
1039 | DMI_MATCH(DMI_PRODUCT_NAME, "Tecra M4"), | |
1040 | }, | |
1041 | }, | |
040dee53 TH |
1042 | { |
1043 | .ident = "TECRA M4", | |
1044 | .matches = { | |
1045 | DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), | |
1046 | DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M4"), | |
1047 | }, | |
1048 | }, | |
8c3832eb TH |
1049 | { |
1050 | .ident = "TECRA M5", | |
1051 | .matches = { | |
1052 | DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), | |
1053 | DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M5"), | |
1054 | }, | |
b8b275ef | 1055 | }, |
ffe188dd PS |
1056 | { |
1057 | .ident = "TECRA M6", | |
1058 | .matches = { | |
1059 | DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), | |
1060 | DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M6"), | |
1061 | }, | |
1062 | }, | |
5c08ea01 TH |
1063 | { |
1064 | .ident = "TECRA M7", | |
1065 | .matches = { | |
1066 | DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), | |
1067 | DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M7"), | |
1068 | }, | |
1069 | }, | |
04d86d6f PS |
1070 | { |
1071 | .ident = "TECRA A8", | |
1072 | .matches = { | |
1073 | DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), | |
1074 | DMI_MATCH(DMI_PRODUCT_NAME, "TECRA A8"), | |
1075 | }, | |
1076 | }, | |
ffe188dd PS |
1077 | { |
1078 | .ident = "Satellite R20", | |
1079 | .matches = { | |
1080 | DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), | |
1081 | DMI_MATCH(DMI_PRODUCT_NAME, "Satellite R20"), | |
1082 | }, | |
1083 | }, | |
04d86d6f PS |
1084 | { |
1085 | .ident = "Satellite R25", | |
1086 | .matches = { | |
1087 | DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), | |
1088 | DMI_MATCH(DMI_PRODUCT_NAME, "Satellite R25"), | |
1089 | }, | |
1090 | }, | |
3cc0b9d3 TH |
1091 | { |
1092 | .ident = "Satellite U200", | |
1093 | .matches = { | |
1094 | DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), | |
1095 | DMI_MATCH(DMI_PRODUCT_NAME, "Satellite U200"), | |
1096 | }, | |
1097 | }, | |
04d86d6f PS |
1098 | { |
1099 | .ident = "Satellite U200", | |
1100 | .matches = { | |
1101 | DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), | |
1102 | DMI_MATCH(DMI_PRODUCT_NAME, "SATELLITE U200"), | |
1103 | }, | |
1104 | }, | |
62320e23 YC |
1105 | { |
1106 | .ident = "Satellite Pro U200", | |
1107 | .matches = { | |
1108 | DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), | |
1109 | DMI_MATCH(DMI_PRODUCT_NAME, "SATELLITE PRO U200"), | |
1110 | }, | |
1111 | }, | |
8c3832eb TH |
1112 | { |
1113 | .ident = "Satellite U205", | |
1114 | .matches = { | |
1115 | DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), | |
1116 | DMI_MATCH(DMI_PRODUCT_NAME, "Satellite U205"), | |
1117 | }, | |
b8b275ef | 1118 | }, |
de753e5e TH |
1119 | { |
1120 | .ident = "SATELLITE U205", | |
1121 | .matches = { | |
1122 | DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), | |
1123 | DMI_MATCH(DMI_PRODUCT_NAME, "SATELLITE U205"), | |
1124 | }, | |
1125 | }, | |
8c3832eb TH |
1126 | { |
1127 | .ident = "Portege M500", | |
1128 | .matches = { | |
1129 | DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), | |
1130 | DMI_MATCH(DMI_PRODUCT_NAME, "PORTEGE M500"), | |
1131 | }, | |
b8b275ef | 1132 | }, |
c3f93b8f TH |
1133 | { |
1134 | .ident = "VGN-BX297XP", | |
1135 | .matches = { | |
1136 | DMI_MATCH(DMI_SYS_VENDOR, "Sony Corporation"), | |
1137 | DMI_MATCH(DMI_PRODUCT_NAME, "VGN-BX297XP"), | |
1138 | }, | |
1139 | }, | |
7d051548 JG |
1140 | |
1141 | { } /* terminate list */ | |
8c3832eb | 1142 | }; |
7abe79c3 TH |
1143 | static const char *oemstrs[] = { |
1144 | "Tecra M3,", | |
1145 | }; | |
1146 | int i; | |
8c3832eb TH |
1147 | |
1148 | if (dmi_check_system(sysids)) | |
1149 | return 1; | |
1150 | ||
7abe79c3 TH |
1151 | for (i = 0; i < ARRAY_SIZE(oemstrs); i++) |
1152 | if (dmi_find_device(DMI_DEV_TYPE_OEM_STRING, oemstrs[i], NULL)) | |
1153 | return 1; | |
1154 | ||
1eedb4a9 TH |
1155 | /* TECRA M4 sometimes forgets its identify and reports bogus |
1156 | * DMI information. As the bogus information is a bit | |
1157 | * generic, match as many entries as possible. This manual | |
1158 | * matching is necessary because dmi_system_id.matches is | |
1159 | * limited to four entries. | |
1160 | */ | |
3c387730 JS |
1161 | if (dmi_match(DMI_SYS_VENDOR, "TOSHIBA") && |
1162 | dmi_match(DMI_PRODUCT_NAME, "000000") && | |
1163 | dmi_match(DMI_PRODUCT_VERSION, "000000") && | |
1164 | dmi_match(DMI_PRODUCT_SERIAL, "000000") && | |
1165 | dmi_match(DMI_BOARD_VENDOR, "TOSHIBA") && | |
1166 | dmi_match(DMI_BOARD_NAME, "Portable PC") && | |
1167 | dmi_match(DMI_BOARD_VERSION, "Version A0")) | |
1eedb4a9 TH |
1168 | return 1; |
1169 | ||
8c3832eb TH |
1170 | return 0; |
1171 | } | |
b8b275ef TH |
1172 | |
1173 | static int piix_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg) | |
1174 | { | |
1175 | struct ata_host *host = dev_get_drvdata(&pdev->dev); | |
1176 | unsigned long flags; | |
1177 | int rc = 0; | |
1178 | ||
1179 | rc = ata_host_suspend(host, mesg); | |
1180 | if (rc) | |
1181 | return rc; | |
1182 | ||
1183 | /* Some braindamaged ACPI suspend implementations expect the | |
1184 | * controller to be awake on entry; otherwise, it burns cpu | |
1185 | * cycles and power trying to do something to the sleeping | |
1186 | * beauty. | |
1187 | */ | |
3a2d5b70 | 1188 | if (piix_broken_suspend() && (mesg.event & PM_EVENT_SLEEP)) { |
b8b275ef TH |
1189 | pci_save_state(pdev); |
1190 | ||
1191 | /* mark its power state as "unknown", since we don't | |
1192 | * know if e.g. the BIOS will change its device state | |
1193 | * when we suspend. | |
1194 | */ | |
1195 | if (pdev->current_state == PCI_D0) | |
1196 | pdev->current_state = PCI_UNKNOWN; | |
1197 | ||
1198 | /* tell resume that it's waking up from broken suspend */ | |
1199 | spin_lock_irqsave(&host->lock, flags); | |
1200 | host->flags |= PIIX_HOST_BROKEN_SUSPEND; | |
1201 | spin_unlock_irqrestore(&host->lock, flags); | |
1202 | } else | |
1203 | ata_pci_device_do_suspend(pdev, mesg); | |
1204 | ||
1205 | return 0; | |
1206 | } | |
1207 | ||
1208 | static int piix_pci_device_resume(struct pci_dev *pdev) | |
1209 | { | |
1210 | struct ata_host *host = dev_get_drvdata(&pdev->dev); | |
1211 | unsigned long flags; | |
1212 | int rc; | |
1213 | ||
1214 | if (host->flags & PIIX_HOST_BROKEN_SUSPEND) { | |
1215 | spin_lock_irqsave(&host->lock, flags); | |
1216 | host->flags &= ~PIIX_HOST_BROKEN_SUSPEND; | |
1217 | spin_unlock_irqrestore(&host->lock, flags); | |
1218 | ||
1219 | pci_set_power_state(pdev, PCI_D0); | |
1220 | pci_restore_state(pdev); | |
1221 | ||
1222 | /* PCI device wasn't disabled during suspend. Use | |
0b62e13b TH |
1223 | * pci_reenable_device() to avoid affecting the enable |
1224 | * count. | |
b8b275ef | 1225 | */ |
0b62e13b | 1226 | rc = pci_reenable_device(pdev); |
b8b275ef | 1227 | if (rc) |
a44fec1f JP |
1228 | dev_err(&pdev->dev, |
1229 | "failed to enable device after resume (%d)\n", | |
1230 | rc); | |
b8b275ef TH |
1231 | } else |
1232 | rc = ata_pci_device_do_resume(pdev); | |
1233 | ||
1234 | if (rc == 0) | |
1235 | ata_host_resume(host); | |
1236 | ||
1237 | return rc; | |
1238 | } | |
1239 | #endif | |
1240 | ||
25f98131 TH |
1241 | static u8 piix_vmw_bmdma_status(struct ata_port *ap) |
1242 | { | |
1243 | return ata_bmdma_status(ap) & ~ATA_DMA_ERR; | |
1244 | } | |
1245 | ||
1da177e4 LT |
1246 | #define AHCI_PCI_BAR 5 |
1247 | #define AHCI_GLOBAL_CTL 0x04 | |
1248 | #define AHCI_ENABLE (1 << 31) | |
1249 | static int piix_disable_ahci(struct pci_dev *pdev) | |
1250 | { | |
ea6ba10b | 1251 | void __iomem *mmio; |
1da177e4 LT |
1252 | u32 tmp; |
1253 | int rc = 0; | |
1254 | ||
1255 | /* BUG: pci_enable_device has not yet been called. This | |
1256 | * works because this device is usually set up by BIOS. | |
1257 | */ | |
1258 | ||
374b1873 JG |
1259 | if (!pci_resource_start(pdev, AHCI_PCI_BAR) || |
1260 | !pci_resource_len(pdev, AHCI_PCI_BAR)) | |
1da177e4 | 1261 | return 0; |
7b6dbd68 | 1262 | |
374b1873 | 1263 | mmio = pci_iomap(pdev, AHCI_PCI_BAR, 64); |
1da177e4 LT |
1264 | if (!mmio) |
1265 | return -ENOMEM; | |
7b6dbd68 | 1266 | |
c47a631f | 1267 | tmp = ioread32(mmio + AHCI_GLOBAL_CTL); |
1da177e4 LT |
1268 | if (tmp & AHCI_ENABLE) { |
1269 | tmp &= ~AHCI_ENABLE; | |
c47a631f | 1270 | iowrite32(tmp, mmio + AHCI_GLOBAL_CTL); |
1da177e4 | 1271 | |
c47a631f | 1272 | tmp = ioread32(mmio + AHCI_GLOBAL_CTL); |
1da177e4 LT |
1273 | if (tmp & AHCI_ENABLE) |
1274 | rc = -EIO; | |
1275 | } | |
7b6dbd68 | 1276 | |
374b1873 | 1277 | pci_iounmap(pdev, mmio); |
1da177e4 LT |
1278 | return rc; |
1279 | } | |
1280 | ||
c621b140 AC |
1281 | /** |
1282 | * piix_check_450nx_errata - Check for problem 450NX setup | |
c893a3ae | 1283 | * @ata_dev: the PCI device to check |
2e9edbf8 | 1284 | * |
c621b140 AC |
1285 | * Check for the present of 450NX errata #19 and errata #25. If |
1286 | * they are found return an error code so we can turn off DMA | |
1287 | */ | |
1288 | ||
1289 | static int __devinit piix_check_450nx_errata(struct pci_dev *ata_dev) | |
1290 | { | |
1291 | struct pci_dev *pdev = NULL; | |
1292 | u16 cfg; | |
c621b140 | 1293 | int no_piix_dma = 0; |
2e9edbf8 | 1294 | |
2dcb407e | 1295 | while ((pdev = pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, pdev)) != NULL) { |
c621b140 AC |
1296 | /* Look for 450NX PXB. Check for problem configurations |
1297 | A PCI quirk checks bit 6 already */ | |
c621b140 AC |
1298 | pci_read_config_word(pdev, 0x41, &cfg); |
1299 | /* Only on the original revision: IDE DMA can hang */ | |
44c10138 | 1300 | if (pdev->revision == 0x00) |
c621b140 AC |
1301 | no_piix_dma = 1; |
1302 | /* On all revisions below 5 PXB bus lock must be disabled for IDE */ | |
44c10138 | 1303 | else if (cfg & (1<<14) && pdev->revision < 5) |
c621b140 AC |
1304 | no_piix_dma = 2; |
1305 | } | |
31a34fe7 | 1306 | if (no_piix_dma) |
a44fec1f JP |
1307 | dev_warn(&ata_dev->dev, |
1308 | "450NX errata present, disabling IDE DMA%s\n", | |
1309 | no_piix_dma == 2 ? " - a BIOS update may resolve this" | |
1310 | : ""); | |
1311 | ||
c621b140 | 1312 | return no_piix_dma; |
2e9edbf8 | 1313 | } |
c621b140 | 1314 | |
8b09f0da | 1315 | static void __devinit piix_init_pcs(struct ata_host *host, |
ea35d29e JG |
1316 | const struct piix_map_db *map_db) |
1317 | { | |
8b09f0da | 1318 | struct pci_dev *pdev = to_pci_dev(host->dev); |
ea35d29e JG |
1319 | u16 pcs, new_pcs; |
1320 | ||
1321 | pci_read_config_word(pdev, ICH5_PCS, &pcs); | |
1322 | ||
1323 | new_pcs = pcs | map_db->port_enable; | |
1324 | ||
1325 | if (new_pcs != pcs) { | |
1326 | DPRINTK("updating PCS from 0x%x to 0x%x\n", pcs, new_pcs); | |
1327 | pci_write_config_word(pdev, ICH5_PCS, new_pcs); | |
1328 | msleep(150); | |
1329 | } | |
1330 | } | |
1331 | ||
8b09f0da TH |
1332 | static const int *__devinit piix_init_sata_map(struct pci_dev *pdev, |
1333 | struct ata_port_info *pinfo, | |
1334 | const struct piix_map_db *map_db) | |
d33f58b8 | 1335 | { |
b4482a4b | 1336 | const int *map; |
d33f58b8 TH |
1337 | int i, invalid_map = 0; |
1338 | u8 map_value; | |
1339 | ||
1340 | pci_read_config_byte(pdev, ICH5_PMR, &map_value); | |
1341 | ||
1342 | map = map_db->map[map_value & map_db->mask]; | |
1343 | ||
a44fec1f | 1344 | dev_info(&pdev->dev, "MAP ["); |
d33f58b8 TH |
1345 | for (i = 0; i < 4; i++) { |
1346 | switch (map[i]) { | |
1347 | case RV: | |
1348 | invalid_map = 1; | |
a44fec1f | 1349 | pr_cont(" XX"); |
d33f58b8 TH |
1350 | break; |
1351 | ||
1352 | case NA: | |
a44fec1f | 1353 | pr_cont(" --"); |
d33f58b8 TH |
1354 | break; |
1355 | ||
1356 | case IDE: | |
1357 | WARN_ON((i & 1) || map[i + 1] != IDE); | |
669a5db4 | 1358 | pinfo[i / 2] = piix_port_info[ich_pata_100]; |
d33f58b8 | 1359 | i++; |
a44fec1f | 1360 | pr_cont(" IDE IDE"); |
d33f58b8 TH |
1361 | break; |
1362 | ||
1363 | default: | |
a44fec1f | 1364 | pr_cont(" P%d", map[i]); |
d33f58b8 | 1365 | if (i & 1) |
cca3974e | 1366 | pinfo[i / 2].flags |= ATA_FLAG_SLAVE_POSS; |
d33f58b8 TH |
1367 | break; |
1368 | } | |
1369 | } | |
a44fec1f | 1370 | pr_cont(" ]\n"); |
d33f58b8 TH |
1371 | |
1372 | if (invalid_map) | |
a44fec1f | 1373 | dev_err(&pdev->dev, "invalid MAP value %u\n", map_value); |
d33f58b8 | 1374 | |
8b09f0da | 1375 | return map; |
d33f58b8 TH |
1376 | } |
1377 | ||
e9c1670c TH |
1378 | static bool piix_no_sidpr(struct ata_host *host) |
1379 | { | |
1380 | struct pci_dev *pdev = to_pci_dev(host->dev); | |
1381 | ||
1382 | /* | |
1383 | * Samsung DB-P70 only has three ATA ports exposed and | |
1384 | * curiously the unconnected first port reports link online | |
1385 | * while not responding to SRST protocol causing excessive | |
1386 | * detection delay. | |
1387 | * | |
1388 | * Unfortunately, the system doesn't carry enough DMI | |
1389 | * information to identify the machine but does have subsystem | |
1390 | * vendor and device set. As it's unclear whether the | |
1391 | * subsystem vendor/device is used only for this specific | |
1392 | * board, the port can't be disabled solely with the | |
1393 | * information; however, turning off SIDPR access works around | |
1394 | * the problem. Turn it off. | |
1395 | * | |
1396 | * This problem is reported in bnc#441240. | |
1397 | * | |
1398 | * https://bugzilla.novell.com/show_bug.cgi?id=441420 | |
1399 | */ | |
1400 | if (pdev->vendor == PCI_VENDOR_ID_INTEL && pdev->device == 0x2920 && | |
1401 | pdev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG && | |
1402 | pdev->subsystem_device == 0xb049) { | |
a44fec1f JP |
1403 | dev_warn(host->dev, |
1404 | "Samsung DB-P70 detected, disabling SIDPR\n"); | |
e9c1670c TH |
1405 | return true; |
1406 | } | |
1407 | ||
1408 | return false; | |
1409 | } | |
1410 | ||
be77e43a | 1411 | static int __devinit piix_init_sidpr(struct ata_host *host) |
c7290724 TH |
1412 | { |
1413 | struct pci_dev *pdev = to_pci_dev(host->dev); | |
1414 | struct piix_host_priv *hpriv = host->private_data; | |
be77e43a | 1415 | struct ata_link *link0 = &host->ports[0]->link; |
cb6716c8 | 1416 | u32 scontrol; |
be77e43a | 1417 | int i, rc; |
c7290724 TH |
1418 | |
1419 | /* check for availability */ | |
1420 | for (i = 0; i < 4; i++) | |
1421 | if (hpriv->map[i] == IDE) | |
be77e43a | 1422 | return 0; |
c7290724 | 1423 | |
e9c1670c TH |
1424 | /* is it blacklisted? */ |
1425 | if (piix_no_sidpr(host)) | |
1426 | return 0; | |
1427 | ||
c7290724 | 1428 | if (!(host->ports[0]->flags & PIIX_FLAG_SIDPR)) |
be77e43a | 1429 | return 0; |
c7290724 TH |
1430 | |
1431 | if (pci_resource_start(pdev, PIIX_SIDPR_BAR) == 0 || | |
1432 | pci_resource_len(pdev, PIIX_SIDPR_BAR) != PIIX_SIDPR_LEN) | |
be77e43a | 1433 | return 0; |
c7290724 TH |
1434 | |
1435 | if (pcim_iomap_regions(pdev, 1 << PIIX_SIDPR_BAR, DRV_NAME)) | |
be77e43a | 1436 | return 0; |
c7290724 TH |
1437 | |
1438 | hpriv->sidpr = pcim_iomap_table(pdev)[PIIX_SIDPR_BAR]; | |
cb6716c8 TH |
1439 | |
1440 | /* SCR access via SIDPR doesn't work on some configurations. | |
1441 | * Give it a test drive by inhibiting power save modes which | |
1442 | * we'll do anyway. | |
1443 | */ | |
be77e43a | 1444 | piix_sidpr_scr_read(link0, SCR_CONTROL, &scontrol); |
cb6716c8 TH |
1445 | |
1446 | /* if IPM is already 3, SCR access is probably working. Don't | |
1447 | * un-inhibit power save modes as BIOS might have inhibited | |
1448 | * them for a reason. | |
1449 | */ | |
1450 | if ((scontrol & 0xf00) != 0x300) { | |
1451 | scontrol |= 0x300; | |
be77e43a TH |
1452 | piix_sidpr_scr_write(link0, SCR_CONTROL, scontrol); |
1453 | piix_sidpr_scr_read(link0, SCR_CONTROL, &scontrol); | |
cb6716c8 TH |
1454 | |
1455 | if ((scontrol & 0xf00) != 0x300) { | |
a44fec1f JP |
1456 | dev_info(host->dev, |
1457 | "SCR access via SIDPR is available but doesn't work\n"); | |
be77e43a | 1458 | return 0; |
cb6716c8 TH |
1459 | } |
1460 | } | |
1461 | ||
be77e43a TH |
1462 | /* okay, SCRs available, set ops and ask libata for slave_link */ |
1463 | for (i = 0; i < 2; i++) { | |
1464 | struct ata_port *ap = host->ports[i]; | |
1465 | ||
1466 | ap->ops = &piix_sidpr_sata_ops; | |
1467 | ||
1468 | if (ap->flags & ATA_FLAG_SLAVE_POSS) { | |
1469 | rc = ata_slave_link_init(ap); | |
1470 | if (rc) | |
1471 | return rc; | |
1472 | } | |
1473 | } | |
1474 | ||
1475 | return 0; | |
c7290724 TH |
1476 | } |
1477 | ||
2852bcf7 | 1478 | static void piix_iocfg_bit18_quirk(struct ata_host *host) |
43a98f05 | 1479 | { |
1855256c | 1480 | static const struct dmi_system_id sysids[] = { |
43a98f05 TH |
1481 | { |
1482 | /* Clevo M570U sets IOCFG bit 18 if the cdrom | |
1483 | * isn't used to boot the system which | |
1484 | * disables the channel. | |
1485 | */ | |
1486 | .ident = "M570U", | |
1487 | .matches = { | |
1488 | DMI_MATCH(DMI_SYS_VENDOR, "Clevo Co."), | |
1489 | DMI_MATCH(DMI_PRODUCT_NAME, "M570U"), | |
1490 | }, | |
1491 | }, | |
7d051548 JG |
1492 | |
1493 | { } /* terminate list */ | |
43a98f05 | 1494 | }; |
2852bcf7 TH |
1495 | struct pci_dev *pdev = to_pci_dev(host->dev); |
1496 | struct piix_host_priv *hpriv = host->private_data; | |
43a98f05 TH |
1497 | |
1498 | if (!dmi_check_system(sysids)) | |
1499 | return; | |
1500 | ||
1501 | /* The datasheet says that bit 18 is NOOP but certain systems | |
1502 | * seem to use it to disable a channel. Clear the bit on the | |
1503 | * affected systems. | |
1504 | */ | |
2852bcf7 | 1505 | if (hpriv->saved_iocfg & (1 << 18)) { |
a44fec1f | 1506 | dev_info(&pdev->dev, "applying IOCFG bit18 quirk\n"); |
2852bcf7 TH |
1507 | pci_write_config_dword(pdev, PIIX_IOCFG, |
1508 | hpriv->saved_iocfg & ~(1 << 18)); | |
43a98f05 TH |
1509 | } |
1510 | } | |
1511 | ||
5f451fe1 RW |
1512 | static bool piix_broken_system_poweroff(struct pci_dev *pdev) |
1513 | { | |
1514 | static const struct dmi_system_id broken_systems[] = { | |
1515 | { | |
1516 | .ident = "HP Compaq 2510p", | |
1517 | .matches = { | |
1518 | DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"), | |
1519 | DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq 2510p"), | |
1520 | }, | |
1521 | /* PCI slot number of the controller */ | |
1522 | .driver_data = (void *)0x1FUL, | |
1523 | }, | |
65e31643 VS |
1524 | { |
1525 | .ident = "HP Compaq nc6000", | |
1526 | .matches = { | |
1527 | DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"), | |
1528 | DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq nc6000"), | |
1529 | }, | |
1530 | /* PCI slot number of the controller */ | |
1531 | .driver_data = (void *)0x1FUL, | |
1532 | }, | |
5f451fe1 RW |
1533 | |
1534 | { } /* terminate list */ | |
1535 | }; | |
1536 | const struct dmi_system_id *dmi = dmi_first_match(broken_systems); | |
1537 | ||
1538 | if (dmi) { | |
1539 | unsigned long slot = (unsigned long)dmi->driver_data; | |
1540 | /* apply the quirk only to on-board controllers */ | |
1541 | return slot == PCI_SLOT(pdev->devfn); | |
1542 | } | |
1543 | ||
1544 | return false; | |
1545 | } | |
1546 | ||
1da177e4 LT |
1547 | /** |
1548 | * piix_init_one - Register PIIX ATA PCI device with kernel services | |
1549 | * @pdev: PCI device to register | |
1550 | * @ent: Entry in piix_pci_tbl matching with @pdev | |
1551 | * | |
1552 | * Called from kernel PCI layer. We probe for combined mode (sigh), | |
1553 | * and then hand over control to libata, for it to do the rest. | |
1554 | * | |
1555 | * LOCKING: | |
1556 | * Inherited from PCI layer (may sleep). | |
1557 | * | |
1558 | * RETURNS: | |
1559 | * Zero on success, or -ERRNO value. | |
1560 | */ | |
1561 | ||
bc5468f5 AB |
1562 | static int __devinit piix_init_one(struct pci_dev *pdev, |
1563 | const struct pci_device_id *ent) | |
1da177e4 | 1564 | { |
24dc5f33 | 1565 | struct device *dev = &pdev->dev; |
d33f58b8 | 1566 | struct ata_port_info port_info[2]; |
1626aeb8 | 1567 | const struct ata_port_info *ppi[] = { &port_info[0], &port_info[1] }; |
a97c4006 | 1568 | struct scsi_host_template *sht = &piix_sht; |
cca3974e | 1569 | unsigned long port_flags; |
8b09f0da TH |
1570 | struct ata_host *host; |
1571 | struct piix_host_priv *hpriv; | |
1572 | int rc; | |
1da177e4 | 1573 | |
06296a1e | 1574 | ata_print_version_once(&pdev->dev, DRV_VERSION); |
1da177e4 | 1575 | |
347979a0 AC |
1576 | /* no hotplugging support for later devices (FIXME) */ |
1577 | if (!in_module_init && ent->driver_data >= ich5_sata) | |
1da177e4 LT |
1578 | return -ENODEV; |
1579 | ||
5f451fe1 RW |
1580 | if (piix_broken_system_poweroff(pdev)) { |
1581 | piix_port_info[ent->driver_data].flags |= | |
1582 | ATA_FLAG_NO_POWEROFF_SPINDOWN | | |
1583 | ATA_FLAG_NO_HIBERNATE_SPINDOWN; | |
1584 | dev_info(&pdev->dev, "quirky BIOS, skipping spindown " | |
1585 | "on poweroff and hibernation\n"); | |
1586 | } | |
1587 | ||
8b09f0da TH |
1588 | port_info[0] = piix_port_info[ent->driver_data]; |
1589 | port_info[1] = piix_port_info[ent->driver_data]; | |
1590 | ||
1591 | port_flags = port_info[0].flags; | |
1592 | ||
1593 | /* enable device and prepare host */ | |
1594 | rc = pcim_enable_device(pdev); | |
1595 | if (rc) | |
1596 | return rc; | |
1597 | ||
2852bcf7 TH |
1598 | hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL); |
1599 | if (!hpriv) | |
1600 | return -ENOMEM; | |
1601 | ||
1602 | /* Save IOCFG, this will be used for cable detection, quirk | |
1603 | * detection and restoration on detach. This is necessary | |
1604 | * because some ACPI implementations mess up cable related | |
1605 | * bits on _STM. Reported on kernel bz#11879. | |
1606 | */ | |
1607 | pci_read_config_dword(pdev, PIIX_IOCFG, &hpriv->saved_iocfg); | |
1608 | ||
5016d7d2 TH |
1609 | /* ICH6R may be driven by either ata_piix or ahci driver |
1610 | * regardless of BIOS configuration. Make sure AHCI mode is | |
1611 | * off. | |
1612 | */ | |
1613 | if (pdev->vendor == PCI_VENDOR_ID_INTEL && pdev->device == 0x2652) { | |
da3ceb22 | 1614 | rc = piix_disable_ahci(pdev); |
5016d7d2 TH |
1615 | if (rc) |
1616 | return rc; | |
1617 | } | |
1618 | ||
8b09f0da | 1619 | /* SATA map init can change port_info, do it before prepping host */ |
8b09f0da TH |
1620 | if (port_flags & ATA_FLAG_SATA) |
1621 | hpriv->map = piix_init_sata_map(pdev, port_info, | |
1622 | piix_map_db_table[ent->driver_data]); | |
1da177e4 | 1623 | |
1c5afdf7 | 1624 | rc = ata_pci_bmdma_prepare_host(pdev, ppi, &host); |
8b09f0da TH |
1625 | if (rc) |
1626 | return rc; | |
1627 | host->private_data = hpriv; | |
ff0fc146 | 1628 | |
8b09f0da | 1629 | /* initialize controller */ |
c7290724 | 1630 | if (port_flags & ATA_FLAG_SATA) { |
8b09f0da | 1631 | piix_init_pcs(host, piix_map_db_table[ent->driver_data]); |
be77e43a TH |
1632 | rc = piix_init_sidpr(host); |
1633 | if (rc) | |
1634 | return rc; | |
a97c4006 TH |
1635 | if (host->ports[0]->ops == &piix_sidpr_sata_ops) |
1636 | sht = &piix_sidpr_sht; | |
c7290724 | 1637 | } |
1da177e4 | 1638 | |
43a98f05 | 1639 | /* apply IOCFG bit18 quirk */ |
2852bcf7 | 1640 | piix_iocfg_bit18_quirk(host); |
43a98f05 | 1641 | |
1da177e4 LT |
1642 | /* On ICH5, some BIOSen disable the interrupt using the |
1643 | * PCI_COMMAND_INTX_DISABLE bit added in PCI 2.3. | |
1644 | * On ICH6, this bit has the same effect, but only when | |
1645 | * MSI is disabled (and it is disabled, as we don't use | |
1646 | * message-signalled interrupts currently). | |
1647 | */ | |
cca3974e | 1648 | if (port_flags & PIIX_FLAG_CHECKINTR) |
a04ce0ff | 1649 | pci_intx(pdev, 1); |
1da177e4 | 1650 | |
c621b140 AC |
1651 | if (piix_check_450nx_errata(pdev)) { |
1652 | /* This writes into the master table but it does not | |
1653 | really matter for this errata as we will apply it to | |
1654 | all the PIIX devices on the board */ | |
8b09f0da TH |
1655 | host->ports[0]->mwdma_mask = 0; |
1656 | host->ports[0]->udma_mask = 0; | |
1657 | host->ports[1]->mwdma_mask = 0; | |
1658 | host->ports[1]->udma_mask = 0; | |
c621b140 | 1659 | } |
517d3cc1 | 1660 | host->flags |= ATA_HOST_PARALLEL_SCAN; |
8b09f0da TH |
1661 | |
1662 | pci_set_master(pdev); | |
a97c4006 | 1663 | return ata_pci_sff_activate_host(host, ata_bmdma_interrupt, sht); |
1da177e4 LT |
1664 | } |
1665 | ||
2852bcf7 TH |
1666 | static void piix_remove_one(struct pci_dev *pdev) |
1667 | { | |
1668 | struct ata_host *host = dev_get_drvdata(&pdev->dev); | |
1669 | struct piix_host_priv *hpriv = host->private_data; | |
1670 | ||
1671 | pci_write_config_dword(pdev, PIIX_IOCFG, hpriv->saved_iocfg); | |
1672 | ||
1673 | ata_pci_remove_one(pdev); | |
1674 | } | |
1675 | ||
1da177e4 LT |
1676 | static int __init piix_init(void) |
1677 | { | |
1678 | int rc; | |
1679 | ||
b7887196 PR |
1680 | DPRINTK("pci_register_driver\n"); |
1681 | rc = pci_register_driver(&piix_pci_driver); | |
1da177e4 LT |
1682 | if (rc) |
1683 | return rc; | |
1684 | ||
1685 | in_module_init = 0; | |
1686 | ||
1687 | DPRINTK("done\n"); | |
1688 | return 0; | |
1689 | } | |
1690 | ||
1da177e4 LT |
1691 | static void __exit piix_exit(void) |
1692 | { | |
1693 | pci_unregister_driver(&piix_pci_driver); | |
1694 | } | |
1695 | ||
1696 | module_init(piix_init); | |
1697 | module_exit(piix_exit); |