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1da177e4 | 1 | /* |
af36d7f0 JG |
2 | * ata_piix.c - Intel PATA/SATA controllers |
3 | * | |
4 | * Maintained by: Jeff Garzik <jgarzik@pobox.com> | |
5 | * Please ALWAYS copy linux-ide@vger.kernel.org | |
6 | * on emails. | |
7 | * | |
8 | * | |
9 | * Copyright 2003-2005 Red Hat Inc | |
10 | * Copyright 2003-2005 Jeff Garzik | |
11 | * | |
12 | * | |
13 | * Copyright header from piix.c: | |
14 | * | |
15 | * Copyright (C) 1998-1999 Andrzej Krzysztofowicz, Author and Maintainer | |
16 | * Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org> | |
17 | * Copyright (C) 2003 Red Hat Inc <alan@redhat.com> | |
18 | * | |
19 | * | |
20 | * This program is free software; you can redistribute it and/or modify | |
21 | * it under the terms of the GNU General Public License as published by | |
22 | * the Free Software Foundation; either version 2, or (at your option) | |
23 | * any later version. | |
24 | * | |
25 | * This program is distributed in the hope that it will be useful, | |
26 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
27 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
28 | * GNU General Public License for more details. | |
29 | * | |
30 | * You should have received a copy of the GNU General Public License | |
31 | * along with this program; see the file COPYING. If not, write to | |
32 | * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. | |
33 | * | |
34 | * | |
35 | * libata documentation is available via 'make {ps|pdf}docs', | |
36 | * as Documentation/DocBook/libata.* | |
37 | * | |
38 | * Hardware documentation available at http://developer.intel.com/ | |
39 | * | |
d96212ed AC |
40 | * Documentation |
41 | * Publically available from Intel web site. Errata documentation | |
42 | * is also publically available. As an aide to anyone hacking on this | |
2c5ff671 | 43 | * driver the list of errata that are relevant is below, going back to |
d96212ed AC |
44 | * PIIX4. Older device documentation is now a bit tricky to find. |
45 | * | |
46 | * The chipsets all follow very much the same design. The orginal Triton | |
47 | * series chipsets do _not_ support independant device timings, but this | |
48 | * is fixed in Triton II. With the odd mobile exception the chips then | |
49 | * change little except in gaining more modes until SATA arrives. This | |
50 | * driver supports only the chips with independant timing (that is those | |
51 | * with SITRE and the 0x44 timing register). See pata_oldpiix and pata_mpiix | |
52 | * for the early chip drivers. | |
53 | * | |
54 | * Errata of note: | |
55 | * | |
56 | * Unfixable | |
57 | * PIIX4 errata #9 - Only on ultra obscure hw | |
58 | * ICH3 errata #13 - Not observed to affect real hw | |
59 | * by Intel | |
60 | * | |
61 | * Things we must deal with | |
62 | * PIIX4 errata #10 - BM IDE hang with non UDMA | |
63 | * (must stop/start dma to recover) | |
64 | * 440MX errata #15 - As PIIX4 errata #10 | |
65 | * PIIX4 errata #15 - Must not read control registers | |
66 | * during a PIO transfer | |
67 | * 440MX errata #13 - As PIIX4 errata #15 | |
68 | * ICH2 errata #21 - DMA mode 0 doesn't work right | |
69 | * ICH0/1 errata #55 - As ICH2 errata #21 | |
70 | * ICH2 spec c #9 - Extra operations needed to handle | |
71 | * drive hotswap [NOT YET SUPPORTED] | |
72 | * ICH2 spec c #20 - IDE PRD must not cross a 64K boundary | |
73 | * and must be dword aligned | |
74 | * ICH2 spec c #24 - UDMA mode 4,5 t85/86 should be 6ns not 3.3 | |
75 | * | |
76 | * Should have been BIOS fixed: | |
77 | * 450NX: errata #19 - DMA hangs on old 450NX | |
78 | * 450NX: errata #20 - DMA hangs on old 450NX | |
79 | * 450NX: errata #25 - Corruption with DMA on old 450NX | |
80 | * ICH3 errata #15 - IDE deadlock under high load | |
81 | * (BIOS must set dev 31 fn 0 bit 23) | |
82 | * ICH3 errata #18 - Don't use native mode | |
1da177e4 LT |
83 | */ |
84 | ||
85 | #include <linux/kernel.h> | |
86 | #include <linux/module.h> | |
87 | #include <linux/pci.h> | |
88 | #include <linux/init.h> | |
89 | #include <linux/blkdev.h> | |
90 | #include <linux/delay.h> | |
6248e647 | 91 | #include <linux/device.h> |
1da177e4 LT |
92 | #include <scsi/scsi_host.h> |
93 | #include <linux/libata.h> | |
b8b275ef | 94 | #include <linux/dmi.h> |
1da177e4 LT |
95 | |
96 | #define DRV_NAME "ata_piix" | |
2a3103ce | 97 | #define DRV_VERSION "2.12" |
1da177e4 LT |
98 | |
99 | enum { | |
100 | PIIX_IOCFG = 0x54, /* IDE I/O configuration register */ | |
101 | ICH5_PMR = 0x90, /* port mapping register */ | |
102 | ICH5_PCS = 0x92, /* port control and status */ | |
c7290724 TH |
103 | PIIX_SIDPR_BAR = 5, |
104 | PIIX_SIDPR_LEN = 16, | |
105 | PIIX_SIDPR_IDX = 0, | |
106 | PIIX_SIDPR_DATA = 4, | |
1da177e4 | 107 | |
ff0fc146 | 108 | PIIX_FLAG_CHECKINTR = (1 << 28), /* make sure PCI INTx enabled */ |
c7290724 | 109 | PIIX_FLAG_SIDPR = (1 << 29), /* SATA idx/data pair regs */ |
1da177e4 | 110 | |
800b3996 TH |
111 | PIIX_PATA_FLAGS = ATA_FLAG_SLAVE_POSS, |
112 | PIIX_SATA_FLAGS = ATA_FLAG_SATA | PIIX_FLAG_CHECKINTR, | |
b3362f88 | 113 | |
1da177e4 LT |
114 | PIIX_80C_PRI = (1 << 5) | (1 << 4), |
115 | PIIX_80C_SEC = (1 << 7) | (1 << 6), | |
116 | ||
d33f58b8 TH |
117 | /* constants for mapping table */ |
118 | P0 = 0, /* port 0 */ | |
119 | P1 = 1, /* port 1 */ | |
120 | P2 = 2, /* port 2 */ | |
121 | P3 = 3, /* port 3 */ | |
122 | IDE = -1, /* IDE */ | |
123 | NA = -2, /* not avaliable */ | |
124 | RV = -3, /* reserved */ | |
125 | ||
7b6dbd68 | 126 | PIIX_AHCI_DEVICE = 6, |
b8b275ef TH |
127 | |
128 | /* host->flags bits */ | |
129 | PIIX_HOST_BROKEN_SUSPEND = (1 << 24), | |
1da177e4 LT |
130 | }; |
131 | ||
9cde9ed1 TH |
132 | enum piix_controller_ids { |
133 | /* controller IDs */ | |
134 | piix_pata_mwdma, /* PIIX3 MWDMA only */ | |
135 | piix_pata_33, /* PIIX4 at 33Mhz */ | |
136 | ich_pata_33, /* ICH up to UDMA 33 only */ | |
137 | ich_pata_66, /* ICH up to 66 Mhz */ | |
138 | ich_pata_100, /* ICH up to UDMA 100 */ | |
139 | ich5_sata, | |
140 | ich6_sata, | |
9c0bf675 TH |
141 | ich6m_sata, |
142 | ich8_sata, | |
9cde9ed1 | 143 | ich8_2port_sata, |
9c0bf675 TH |
144 | ich8m_apple_sata, /* locks up on second port enable */ |
145 | tolapai_sata, | |
9cde9ed1 TH |
146 | piix_pata_vmw, /* PIIX4 for VMware, spurious DMA_ERR */ |
147 | }; | |
148 | ||
d33f58b8 TH |
149 | struct piix_map_db { |
150 | const u32 mask; | |
73291a1c | 151 | const u16 port_enable; |
d33f58b8 TH |
152 | const int map[][4]; |
153 | }; | |
154 | ||
d96715c1 TH |
155 | struct piix_host_priv { |
156 | const int *map; | |
c7290724 | 157 | void __iomem *sidpr; |
d96715c1 TH |
158 | }; |
159 | ||
2dcb407e JG |
160 | static int piix_init_one(struct pci_dev *pdev, |
161 | const struct pci_device_id *ent); | |
a1efdaba | 162 | static int piix_pata_prereset(struct ata_link *link, unsigned long deadline); |
2dcb407e JG |
163 | static void piix_set_piomode(struct ata_port *ap, struct ata_device *adev); |
164 | static void piix_set_dmamode(struct ata_port *ap, struct ata_device *adev); | |
165 | static void ich_set_dmamode(struct ata_port *ap, struct ata_device *adev); | |
eb4a2c7f | 166 | static int ich_pata_cable_detect(struct ata_port *ap); |
25f98131 | 167 | static u8 piix_vmw_bmdma_status(struct ata_port *ap); |
c7290724 TH |
168 | static int piix_sidpr_scr_read(struct ata_port *ap, unsigned int reg, u32 *val); |
169 | static int piix_sidpr_scr_write(struct ata_port *ap, unsigned int reg, u32 val); | |
b8b275ef TH |
170 | #ifdef CONFIG_PM |
171 | static int piix_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg); | |
172 | static int piix_pci_device_resume(struct pci_dev *pdev); | |
173 | #endif | |
1da177e4 LT |
174 | |
175 | static unsigned int in_module_init = 1; | |
176 | ||
3b7d697d | 177 | static const struct pci_device_id piix_pci_tbl[] = { |
d2cdfc0d A |
178 | /* Intel PIIX3 for the 430HX etc */ |
179 | { 0x8086, 0x7010, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_mwdma }, | |
25f98131 TH |
180 | /* VMware ICH4 */ |
181 | { 0x8086, 0x7111, 0x15ad, 0x1976, 0, 0, piix_pata_vmw }, | |
669a5db4 JG |
182 | /* Intel PIIX4 for the 430TX/440BX/MX chipset: UDMA 33 */ |
183 | /* Also PIIX4E (fn3 rev 2) and PIIX4M (fn3 rev 3) */ | |
184 | { 0x8086, 0x7111, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 }, | |
669a5db4 JG |
185 | /* Intel PIIX4 */ |
186 | { 0x8086, 0x7199, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 }, | |
187 | /* Intel PIIX4 */ | |
188 | { 0x8086, 0x7601, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 }, | |
189 | /* Intel PIIX */ | |
190 | { 0x8086, 0x84CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 }, | |
191 | /* Intel ICH (i810, i815, i840) UDMA 66*/ | |
192 | { 0x8086, 0x2411, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_66 }, | |
193 | /* Intel ICH0 : UDMA 33*/ | |
194 | { 0x8086, 0x2421, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_33 }, | |
195 | /* Intel ICH2M */ | |
196 | { 0x8086, 0x244A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, | |
197 | /* Intel ICH2 (i810E2, i845, 850, 860) UDMA 100 */ | |
198 | { 0x8086, 0x244B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, | |
199 | /* Intel ICH3M */ | |
200 | { 0x8086, 0x248A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, | |
201 | /* Intel ICH3 (E7500/1) UDMA 100 */ | |
202 | { 0x8086, 0x248B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, | |
203 | /* Intel ICH4 (i845GV, i845E, i852, i855) UDMA 100 */ | |
204 | { 0x8086, 0x24CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, | |
205 | { 0x8086, 0x24CB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, | |
206 | /* Intel ICH5 */ | |
2eb829e9 | 207 | { 0x8086, 0x24DB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, |
669a5db4 JG |
208 | /* C-ICH (i810E2) */ |
209 | { 0x8086, 0x245B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, | |
85cd7251 | 210 | /* ESB (855GME/875P + 6300ESB) UDMA 100 */ |
669a5db4 JG |
211 | { 0x8086, 0x25A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, |
212 | /* ICH6 (and 6) (i915) UDMA 100 */ | |
213 | { 0x8086, 0x266F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, | |
214 | /* ICH7/7-R (i945, i975) UDMA 100*/ | |
2eb829e9 | 215 | { 0x8086, 0x27DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, |
669a5db4 | 216 | { 0x8086, 0x269E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, |
c1e6f28c CL |
217 | /* ICH8 Mobile PATA Controller */ |
218 | { 0x8086, 0x2850, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, | |
1da177e4 LT |
219 | |
220 | /* NOTE: The following PCI ids must be kept in sync with the | |
221 | * list in drivers/pci/quirks.c. | |
222 | */ | |
223 | ||
1d076e5b | 224 | /* 82801EB (ICH5) */ |
1da177e4 | 225 | { 0x8086, 0x24d1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata }, |
1d076e5b | 226 | /* 82801EB (ICH5) */ |
1da177e4 | 227 | { 0x8086, 0x24df, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata }, |
1d076e5b | 228 | /* 6300ESB (ICH5 variant with broken PCS present bits) */ |
5e56a37c | 229 | { 0x8086, 0x25a3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata }, |
1d076e5b | 230 | /* 6300ESB pretending RAID */ |
5e56a37c | 231 | { 0x8086, 0x25b0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata }, |
1d076e5b | 232 | /* 82801FB/FW (ICH6/ICH6W) */ |
1da177e4 | 233 | { 0x8086, 0x2651, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata }, |
1d076e5b | 234 | /* 82801FR/FRW (ICH6R/ICH6RW) */ |
9c0bf675 | 235 | { 0x8086, 0x2652, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata }, |
5016d7d2 TH |
236 | /* 82801FBM ICH6M (ICH6R with only port 0 and 2 implemented). |
237 | * Attach iff the controller is in IDE mode. */ | |
238 | { 0x8086, 0x2653, PCI_ANY_ID, PCI_ANY_ID, | |
9c0bf675 | 239 | PCI_CLASS_STORAGE_IDE << 8, 0xffff00, ich6m_sata }, |
1d076e5b | 240 | /* 82801GB/GR/GH (ICH7, identical to ICH6) */ |
9c0bf675 | 241 | { 0x8086, 0x27c0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata }, |
1d076e5b | 242 | /* 2801GBM/GHM (ICH7M, identical to ICH6M) */ |
9c0bf675 | 243 | { 0x8086, 0x27c4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6m_sata }, |
f98b6573 | 244 | /* Enterprise Southbridge 2 (631xESB/632xESB) */ |
9c0bf675 | 245 | { 0x8086, 0x2680, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata }, |
f98b6573 | 246 | /* SATA Controller 1 IDE (ICH8) */ |
9c0bf675 | 247 | { 0x8086, 0x2820, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata }, |
f98b6573 | 248 | /* SATA Controller 2 IDE (ICH8) */ |
00242ec8 | 249 | { 0x8086, 0x2825, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata }, |
8d8ef2fb | 250 | /* Mobile SATA Controller IDE (ICH8M), Apple */ |
9c0bf675 | 251 | { 0x8086, 0x2828, 0x106b, 0x00a0, 0, 0, ich8m_apple_sata }, |
23cf296e | 252 | { 0x8086, 0x2828, 0x106b, 0x00a1, 0, 0, ich8m_apple_sata }, |
487eff68 | 253 | { 0x8086, 0x2828, 0x106b, 0x00a3, 0, 0, ich8m_apple_sata }, |
23cf296e TH |
254 | /* Mobile SATA Controller IDE (ICH8M) */ |
255 | { 0x8086, 0x2828, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata }, | |
f98b6573 | 256 | /* SATA Controller IDE (ICH9) */ |
9c0bf675 | 257 | { 0x8086, 0x2920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata }, |
f98b6573 | 258 | /* SATA Controller IDE (ICH9) */ |
00242ec8 | 259 | { 0x8086, 0x2921, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata }, |
f98b6573 | 260 | /* SATA Controller IDE (ICH9) */ |
00242ec8 | 261 | { 0x8086, 0x2926, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata }, |
f98b6573 | 262 | /* SATA Controller IDE (ICH9M) */ |
00242ec8 | 263 | { 0x8086, 0x2928, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata }, |
f98b6573 | 264 | /* SATA Controller IDE (ICH9M) */ |
00242ec8 | 265 | { 0x8086, 0x292d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata }, |
f98b6573 | 266 | /* SATA Controller IDE (ICH9M) */ |
9c0bf675 | 267 | { 0x8086, 0x292e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata }, |
c5cf0ffa | 268 | /* SATA Controller IDE (Tolapai) */ |
9c0bf675 | 269 | { 0x8086, 0x5028, PCI_ANY_ID, PCI_ANY_ID, 0, 0, tolapai_sata }, |
bf7f22b9 | 270 | /* SATA Controller IDE (ICH10) */ |
9c0bf675 | 271 | { 0x8086, 0x3a00, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata }, |
bf7f22b9 JG |
272 | /* SATA Controller IDE (ICH10) */ |
273 | { 0x8086, 0x3a06, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata }, | |
274 | /* SATA Controller IDE (ICH10) */ | |
9c0bf675 | 275 | { 0x8086, 0x3a20, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata }, |
bf7f22b9 JG |
276 | /* SATA Controller IDE (ICH10) */ |
277 | { 0x8086, 0x3a26, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata }, | |
c6c6a1af SH |
278 | /* SATA Controller IDE (PCH) */ |
279 | { 0x8086, 0x3b20, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata }, | |
280 | /* SATA Controller IDE (PCH) */ | |
281 | { 0x8086, 0x3b26, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata }, | |
282 | /* SATA Controller IDE (PCH) */ | |
283 | { 0x8086, 0x3b2d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata }, | |
284 | /* SATA Controller IDE (PCH) */ | |
285 | { 0x8086, 0x3b2e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata }, | |
1da177e4 LT |
286 | |
287 | { } /* terminate list */ | |
288 | }; | |
289 | ||
290 | static struct pci_driver piix_pci_driver = { | |
291 | .name = DRV_NAME, | |
292 | .id_table = piix_pci_tbl, | |
293 | .probe = piix_init_one, | |
294 | .remove = ata_pci_remove_one, | |
438ac6d5 | 295 | #ifdef CONFIG_PM |
b8b275ef TH |
296 | .suspend = piix_pci_device_suspend, |
297 | .resume = piix_pci_device_resume, | |
438ac6d5 | 298 | #endif |
1da177e4 LT |
299 | }; |
300 | ||
193515d5 | 301 | static struct scsi_host_template piix_sht = { |
68d1d07b | 302 | ATA_BMDMA_SHT(DRV_NAME), |
1da177e4 LT |
303 | }; |
304 | ||
029cfd6b TH |
305 | static struct ata_port_operations piix_pata_ops = { |
306 | .inherits = &ata_bmdma_port_ops, | |
307 | .cable_detect = ata_cable_40wire, | |
1da177e4 LT |
308 | .set_piomode = piix_set_piomode, |
309 | .set_dmamode = piix_set_dmamode, | |
a1efdaba | 310 | .prereset = piix_pata_prereset, |
1da177e4 LT |
311 | }; |
312 | ||
029cfd6b TH |
313 | static struct ata_port_operations piix_vmw_ops = { |
314 | .inherits = &piix_pata_ops, | |
315 | .bmdma_status = piix_vmw_bmdma_status, | |
669a5db4 JG |
316 | }; |
317 | ||
029cfd6b TH |
318 | static struct ata_port_operations ich_pata_ops = { |
319 | .inherits = &piix_pata_ops, | |
320 | .cable_detect = ich_pata_cable_detect, | |
321 | .set_dmamode = ich_set_dmamode, | |
1da177e4 LT |
322 | }; |
323 | ||
029cfd6b TH |
324 | static struct ata_port_operations piix_sata_ops = { |
325 | .inherits = &ata_bmdma_port_ops, | |
25f98131 TH |
326 | }; |
327 | ||
029cfd6b TH |
328 | static struct ata_port_operations piix_sidpr_sata_ops = { |
329 | .inherits = &piix_sata_ops, | |
57c9efdf | 330 | .hardreset = sata_std_hardreset, |
c7290724 TH |
331 | .scr_read = piix_sidpr_scr_read, |
332 | .scr_write = piix_sidpr_scr_write, | |
c7290724 TH |
333 | }; |
334 | ||
d96715c1 | 335 | static const struct piix_map_db ich5_map_db = { |
d33f58b8 | 336 | .mask = 0x7, |
ea35d29e | 337 | .port_enable = 0x3, |
d33f58b8 TH |
338 | .map = { |
339 | /* PM PS SM SS MAP */ | |
340 | { P0, NA, P1, NA }, /* 000b */ | |
341 | { P1, NA, P0, NA }, /* 001b */ | |
342 | { RV, RV, RV, RV }, | |
343 | { RV, RV, RV, RV }, | |
344 | { P0, P1, IDE, IDE }, /* 100b */ | |
345 | { P1, P0, IDE, IDE }, /* 101b */ | |
346 | { IDE, IDE, P0, P1 }, /* 110b */ | |
347 | { IDE, IDE, P1, P0 }, /* 111b */ | |
348 | }, | |
349 | }; | |
350 | ||
d96715c1 | 351 | static const struct piix_map_db ich6_map_db = { |
d33f58b8 | 352 | .mask = 0x3, |
ea35d29e | 353 | .port_enable = 0xf, |
d33f58b8 TH |
354 | .map = { |
355 | /* PM PS SM SS MAP */ | |
79ea24e7 | 356 | { P0, P2, P1, P3 }, /* 00b */ |
d33f58b8 TH |
357 | { IDE, IDE, P1, P3 }, /* 01b */ |
358 | { P0, P2, IDE, IDE }, /* 10b */ | |
359 | { RV, RV, RV, RV }, | |
360 | }, | |
361 | }; | |
362 | ||
d96715c1 | 363 | static const struct piix_map_db ich6m_map_db = { |
d33f58b8 | 364 | .mask = 0x3, |
ea35d29e | 365 | .port_enable = 0x5, |
67083741 TH |
366 | |
367 | /* Map 01b isn't specified in the doc but some notebooks use | |
c6446a4c TH |
368 | * it anyway. MAP 01b have been spotted on both ICH6M and |
369 | * ICH7M. | |
67083741 TH |
370 | */ |
371 | .map = { | |
372 | /* PM PS SM SS MAP */ | |
e04b3b9d | 373 | { P0, P2, NA, NA }, /* 00b */ |
67083741 TH |
374 | { IDE, IDE, P1, P3 }, /* 01b */ |
375 | { P0, P2, IDE, IDE }, /* 10b */ | |
376 | { RV, RV, RV, RV }, | |
377 | }, | |
378 | }; | |
379 | ||
08f12edc JG |
380 | static const struct piix_map_db ich8_map_db = { |
381 | .mask = 0x3, | |
a0ce9aca | 382 | .port_enable = 0xf, |
08f12edc JG |
383 | .map = { |
384 | /* PM PS SM SS MAP */ | |
158f30c8 | 385 | { P0, P2, P1, P3 }, /* 00b (hardwired when in AHCI) */ |
08f12edc | 386 | { RV, RV, RV, RV }, |
ac2b0437 | 387 | { P0, P2, IDE, IDE }, /* 10b (IDE mode) */ |
08f12edc JG |
388 | { RV, RV, RV, RV }, |
389 | }, | |
390 | }; | |
391 | ||
00242ec8 | 392 | static const struct piix_map_db ich8_2port_map_db = { |
e2d352af JG |
393 | .mask = 0x3, |
394 | .port_enable = 0x3, | |
395 | .map = { | |
396 | /* PM PS SM SS MAP */ | |
397 | { P0, NA, P1, NA }, /* 00b */ | |
398 | { RV, RV, RV, RV }, /* 01b */ | |
399 | { RV, RV, RV, RV }, /* 10b */ | |
400 | { RV, RV, RV, RV }, | |
401 | }, | |
c5cf0ffa JG |
402 | }; |
403 | ||
8d8ef2fb TR |
404 | static const struct piix_map_db ich8m_apple_map_db = { |
405 | .mask = 0x3, | |
406 | .port_enable = 0x1, | |
407 | .map = { | |
408 | /* PM PS SM SS MAP */ | |
409 | { P0, NA, NA, NA }, /* 00b */ | |
410 | { RV, RV, RV, RV }, | |
411 | { P0, P2, IDE, IDE }, /* 10b */ | |
412 | { RV, RV, RV, RV }, | |
413 | }, | |
414 | }; | |
415 | ||
00242ec8 | 416 | static const struct piix_map_db tolapai_map_db = { |
8f73a688 JG |
417 | .mask = 0x3, |
418 | .port_enable = 0x3, | |
419 | .map = { | |
420 | /* PM PS SM SS MAP */ | |
421 | { P0, NA, P1, NA }, /* 00b */ | |
422 | { RV, RV, RV, RV }, /* 01b */ | |
423 | { RV, RV, RV, RV }, /* 10b */ | |
424 | { RV, RV, RV, RV }, | |
425 | }, | |
426 | }; | |
427 | ||
d96715c1 TH |
428 | static const struct piix_map_db *piix_map_db_table[] = { |
429 | [ich5_sata] = &ich5_map_db, | |
d96715c1 | 430 | [ich6_sata] = &ich6_map_db, |
9c0bf675 TH |
431 | [ich6m_sata] = &ich6m_map_db, |
432 | [ich8_sata] = &ich8_map_db, | |
00242ec8 | 433 | [ich8_2port_sata] = &ich8_2port_map_db, |
9c0bf675 TH |
434 | [ich8m_apple_sata] = &ich8m_apple_map_db, |
435 | [tolapai_sata] = &tolapai_map_db, | |
d96715c1 TH |
436 | }; |
437 | ||
1da177e4 | 438 | static struct ata_port_info piix_port_info[] = { |
00242ec8 TH |
439 | [piix_pata_mwdma] = /* PIIX3 MWDMA only */ |
440 | { | |
00242ec8 TH |
441 | .flags = PIIX_PATA_FLAGS, |
442 | .pio_mask = 0x1f, /* pio0-4 */ | |
443 | .mwdma_mask = 0x06, /* mwdma1-2 ?? CHECK 0 should be ok but slow */ | |
444 | .port_ops = &piix_pata_ops, | |
445 | }, | |
446 | ||
ec300d99 | 447 | [piix_pata_33] = /* PIIX4 at 33MHz */ |
1d076e5b | 448 | { |
b3362f88 | 449 | .flags = PIIX_PATA_FLAGS, |
1d076e5b | 450 | .pio_mask = 0x1f, /* pio0-4 */ |
669a5db4 | 451 | .mwdma_mask = 0x06, /* mwdma1-2 ?? CHECK 0 should be ok but slow */ |
1d076e5b TH |
452 | .udma_mask = ATA_UDMA_MASK_40C, |
453 | .port_ops = &piix_pata_ops, | |
454 | }, | |
455 | ||
ec300d99 | 456 | [ich_pata_33] = /* ICH0 - ICH at 33Mhz*/ |
669a5db4 | 457 | { |
b3362f88 | 458 | .flags = PIIX_PATA_FLAGS, |
669a5db4 JG |
459 | .pio_mask = 0x1f, /* pio 0-4 */ |
460 | .mwdma_mask = 0x06, /* Check: maybe 0x07 */ | |
461 | .udma_mask = ATA_UDMA2, /* UDMA33 */ | |
462 | .port_ops = &ich_pata_ops, | |
463 | }, | |
ec300d99 JG |
464 | |
465 | [ich_pata_66] = /* ICH controllers up to 66MHz */ | |
1da177e4 | 466 | { |
b3362f88 | 467 | .flags = PIIX_PATA_FLAGS, |
669a5db4 JG |
468 | .pio_mask = 0x1f, /* pio 0-4 */ |
469 | .mwdma_mask = 0x06, /* MWDMA0 is broken on chip */ | |
470 | .udma_mask = ATA_UDMA4, | |
471 | .port_ops = &ich_pata_ops, | |
472 | }, | |
85cd7251 | 473 | |
ec300d99 | 474 | [ich_pata_100] = |
669a5db4 | 475 | { |
b3362f88 | 476 | .flags = PIIX_PATA_FLAGS | PIIX_FLAG_CHECKINTR, |
1da177e4 | 477 | .pio_mask = 0x1f, /* pio0-4 */ |
1da177e4 | 478 | .mwdma_mask = 0x06, /* mwdma1-2 */ |
669a5db4 JG |
479 | .udma_mask = ATA_UDMA5, /* udma0-5 */ |
480 | .port_ops = &ich_pata_ops, | |
1da177e4 LT |
481 | }, |
482 | ||
ec300d99 | 483 | [ich5_sata] = |
1da177e4 | 484 | { |
228c1590 | 485 | .flags = PIIX_SATA_FLAGS, |
1da177e4 LT |
486 | .pio_mask = 0x1f, /* pio0-4 */ |
487 | .mwdma_mask = 0x07, /* mwdma0-2 */ | |
bf6263a8 | 488 | .udma_mask = ATA_UDMA6, |
1da177e4 LT |
489 | .port_ops = &piix_sata_ops, |
490 | }, | |
491 | ||
ec300d99 | 492 | [ich6_sata] = |
1da177e4 | 493 | { |
723159c5 | 494 | .flags = PIIX_SATA_FLAGS, |
1da177e4 LT |
495 | .pio_mask = 0x1f, /* pio0-4 */ |
496 | .mwdma_mask = 0x07, /* mwdma0-2 */ | |
bf6263a8 | 497 | .udma_mask = ATA_UDMA6, |
1da177e4 LT |
498 | .port_ops = &piix_sata_ops, |
499 | }, | |
500 | ||
9c0bf675 | 501 | [ich6m_sata] = |
c368ca4e | 502 | { |
5016d7d2 | 503 | .flags = PIIX_SATA_FLAGS, |
c368ca4e JG |
504 | .pio_mask = 0x1f, /* pio0-4 */ |
505 | .mwdma_mask = 0x07, /* mwdma0-2 */ | |
bf6263a8 | 506 | .udma_mask = ATA_UDMA6, |
c368ca4e JG |
507 | .port_ops = &piix_sata_ops, |
508 | }, | |
1d076e5b | 509 | |
9c0bf675 | 510 | [ich8_sata] = |
08f12edc | 511 | { |
5016d7d2 | 512 | .flags = PIIX_SATA_FLAGS | PIIX_FLAG_SIDPR, |
08f12edc JG |
513 | .pio_mask = 0x1f, /* pio0-4 */ |
514 | .mwdma_mask = 0x07, /* mwdma0-2 */ | |
bf6263a8 | 515 | .udma_mask = ATA_UDMA6, |
08f12edc JG |
516 | .port_ops = &piix_sata_ops, |
517 | }, | |
669a5db4 | 518 | |
00242ec8 | 519 | [ich8_2port_sata] = |
c5cf0ffa | 520 | { |
5016d7d2 | 521 | .flags = PIIX_SATA_FLAGS | PIIX_FLAG_SIDPR, |
c5cf0ffa JG |
522 | .pio_mask = 0x1f, /* pio0-4 */ |
523 | .mwdma_mask = 0x07, /* mwdma0-2 */ | |
524 | .udma_mask = ATA_UDMA6, | |
525 | .port_ops = &piix_sata_ops, | |
526 | }, | |
8f73a688 | 527 | |
9c0bf675 | 528 | [tolapai_sata] = |
8f73a688 | 529 | { |
5016d7d2 | 530 | .flags = PIIX_SATA_FLAGS, |
8f73a688 JG |
531 | .pio_mask = 0x1f, /* pio0-4 */ |
532 | .mwdma_mask = 0x07, /* mwdma0-2 */ | |
533 | .udma_mask = ATA_UDMA6, | |
534 | .port_ops = &piix_sata_ops, | |
535 | }, | |
8d8ef2fb | 536 | |
9c0bf675 | 537 | [ich8m_apple_sata] = |
8d8ef2fb | 538 | { |
23cf296e | 539 | .flags = PIIX_SATA_FLAGS, |
8d8ef2fb TR |
540 | .pio_mask = 0x1f, /* pio0-4 */ |
541 | .mwdma_mask = 0x07, /* mwdma0-2 */ | |
542 | .udma_mask = ATA_UDMA6, | |
543 | .port_ops = &piix_sata_ops, | |
544 | }, | |
545 | ||
25f98131 TH |
546 | [piix_pata_vmw] = |
547 | { | |
25f98131 TH |
548 | .flags = PIIX_PATA_FLAGS, |
549 | .pio_mask = 0x1f, /* pio0-4 */ | |
550 | .mwdma_mask = 0x06, /* mwdma1-2 ?? CHECK 0 should be ok but slow */ | |
551 | .udma_mask = ATA_UDMA_MASK_40C, | |
552 | .port_ops = &piix_vmw_ops, | |
553 | }, | |
554 | ||
1da177e4 LT |
555 | }; |
556 | ||
557 | static struct pci_bits piix_enable_bits[] = { | |
558 | { 0x41U, 1U, 0x80UL, 0x80UL }, /* port 0 */ | |
559 | { 0x43U, 1U, 0x80UL, 0x80UL }, /* port 1 */ | |
560 | }; | |
561 | ||
562 | MODULE_AUTHOR("Andre Hedrick, Alan Cox, Andrzej Krzysztofowicz, Jeff Garzik"); | |
563 | MODULE_DESCRIPTION("SCSI low-level driver for Intel PIIX/ICH ATA controllers"); | |
564 | MODULE_LICENSE("GPL"); | |
565 | MODULE_DEVICE_TABLE(pci, piix_pci_tbl); | |
566 | MODULE_VERSION(DRV_VERSION); | |
567 | ||
fc085150 AC |
568 | struct ich_laptop { |
569 | u16 device; | |
570 | u16 subvendor; | |
571 | u16 subdevice; | |
572 | }; | |
573 | ||
574 | /* | |
575 | * List of laptops that use short cables rather than 80 wire | |
576 | */ | |
577 | ||
578 | static const struct ich_laptop ich_laptop[] = { | |
579 | /* devid, subvendor, subdev */ | |
580 | { 0x27DF, 0x0005, 0x0280 }, /* ICH7 on Acer 5602WLMi */ | |
2655e2ce | 581 | { 0x27DF, 0x1025, 0x0102 }, /* ICH7 on Acer 5602aWLMi */ |
babfb682 | 582 | { 0x27DF, 0x1025, 0x0110 }, /* ICH7 on Acer 3682WLMi */ |
12340106 | 583 | { 0x27DF, 0x1043, 0x1267 }, /* ICH7 on Asus W5F */ |
54174db3 | 584 | { 0x27DF, 0x103C, 0x30A1 }, /* ICH7 on HP Compaq nc2400 */ |
b33620f9 | 585 | { 0x24CA, 0x1025, 0x0061 }, /* ICH4 on ACER Aspire 2023WLMi */ |
e1fefea9 CIK |
586 | { 0x24CA, 0x1025, 0x003d }, /* ICH4 on ACER TM290 */ |
587 | { 0x266F, 0x1025, 0x0066 }, /* ICH6 on ACER Aspire 1694WLMi */ | |
01ce2601 | 588 | { 0x2653, 0x1043, 0x82D8 }, /* ICH6M on Asus Eee 701 */ |
fc085150 AC |
589 | /* end marker */ |
590 | { 0, } | |
591 | }; | |
592 | ||
1da177e4 | 593 | /** |
eb4a2c7f | 594 | * ich_pata_cable_detect - Probe host controller cable detect info |
1da177e4 LT |
595 | * @ap: Port for which cable detect info is desired |
596 | * | |
597 | * Read 80c cable indicator from ATA PCI device's PCI config | |
598 | * register. This register is normally set by firmware (BIOS). | |
599 | * | |
600 | * LOCKING: | |
601 | * None (inherited from caller). | |
602 | */ | |
669a5db4 | 603 | |
eb4a2c7f | 604 | static int ich_pata_cable_detect(struct ata_port *ap) |
1da177e4 | 605 | { |
cca3974e | 606 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); |
fc085150 | 607 | const struct ich_laptop *lap = &ich_laptop[0]; |
1da177e4 LT |
608 | u8 tmp, mask; |
609 | ||
fc085150 AC |
610 | /* Check for specials - Acer Aspire 5602WLMi */ |
611 | while (lap->device) { | |
612 | if (lap->device == pdev->device && | |
613 | lap->subvendor == pdev->subsystem_vendor && | |
2dcb407e | 614 | lap->subdevice == pdev->subsystem_device) |
eb4a2c7f | 615 | return ATA_CBL_PATA40_SHORT; |
2dcb407e | 616 | |
fc085150 AC |
617 | lap++; |
618 | } | |
619 | ||
1da177e4 | 620 | /* check BIOS cable detect results */ |
2a88d1ac | 621 | mask = ap->port_no == 0 ? PIIX_80C_PRI : PIIX_80C_SEC; |
1da177e4 LT |
622 | pci_read_config_byte(pdev, PIIX_IOCFG, &tmp); |
623 | if ((tmp & mask) == 0) | |
eb4a2c7f AC |
624 | return ATA_CBL_PATA40; |
625 | return ATA_CBL_PATA80; | |
1da177e4 LT |
626 | } |
627 | ||
628 | /** | |
ccc4672a | 629 | * piix_pata_prereset - prereset for PATA host controller |
cc0680a5 | 630 | * @link: Target link |
d4b2bab4 | 631 | * @deadline: deadline jiffies for the operation |
1da177e4 | 632 | * |
573db6b8 TH |
633 | * LOCKING: |
634 | * None (inherited from caller). | |
635 | */ | |
cc0680a5 | 636 | static int piix_pata_prereset(struct ata_link *link, unsigned long deadline) |
1da177e4 | 637 | { |
cc0680a5 | 638 | struct ata_port *ap = link->ap; |
cca3974e | 639 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); |
1da177e4 | 640 | |
c961922b AC |
641 | if (!pci_test_config_bits(pdev, &piix_enable_bits[ap->port_no])) |
642 | return -ENOENT; | |
9363c382 | 643 | return ata_sff_prereset(link, deadline); |
ccc4672a TH |
644 | } |
645 | ||
1da177e4 LT |
646 | /** |
647 | * piix_set_piomode - Initialize host controller PATA PIO timings | |
648 | * @ap: Port whose timings we are configuring | |
649 | * @adev: um | |
1da177e4 LT |
650 | * |
651 | * Set PIO mode for device, in host controller PCI config space. | |
652 | * | |
653 | * LOCKING: | |
654 | * None (inherited from caller). | |
655 | */ | |
656 | ||
2dcb407e | 657 | static void piix_set_piomode(struct ata_port *ap, struct ata_device *adev) |
1da177e4 LT |
658 | { |
659 | unsigned int pio = adev->pio_mode - XFER_PIO_0; | |
cca3974e | 660 | struct pci_dev *dev = to_pci_dev(ap->host->dev); |
1da177e4 | 661 | unsigned int is_slave = (adev->devno != 0); |
2a88d1ac | 662 | unsigned int master_port= ap->port_no ? 0x42 : 0x40; |
1da177e4 LT |
663 | unsigned int slave_port = 0x44; |
664 | u16 master_data; | |
665 | u8 slave_data; | |
669a5db4 JG |
666 | u8 udma_enable; |
667 | int control = 0; | |
85cd7251 | 668 | |
669a5db4 JG |
669 | /* |
670 | * See Intel Document 298600-004 for the timing programing rules | |
671 | * for ICH controllers. | |
672 | */ | |
1da177e4 LT |
673 | |
674 | static const /* ISP RTC */ | |
675 | u8 timings[][2] = { { 0, 0 }, | |
676 | { 0, 0 }, | |
677 | { 1, 0 }, | |
678 | { 2, 1 }, | |
679 | { 2, 3 }, }; | |
680 | ||
669a5db4 JG |
681 | if (pio >= 2) |
682 | control |= 1; /* TIME1 enable */ | |
683 | if (ata_pio_need_iordy(adev)) | |
684 | control |= 2; /* IE enable */ | |
685 | ||
85cd7251 | 686 | /* Intel specifies that the PPE functionality is for disk only */ |
669a5db4 JG |
687 | if (adev->class == ATA_DEV_ATA) |
688 | control |= 4; /* PPE enable */ | |
689 | ||
a5bf5f5a TH |
690 | /* PIO configuration clears DTE unconditionally. It will be |
691 | * programmed in set_dmamode which is guaranteed to be called | |
692 | * after set_piomode if any DMA mode is available. | |
693 | */ | |
1da177e4 LT |
694 | pci_read_config_word(dev, master_port, &master_data); |
695 | if (is_slave) { | |
a5bf5f5a TH |
696 | /* clear TIME1|IE1|PPE1|DTE1 */ |
697 | master_data &= 0xff0f; | |
1967b7ff | 698 | /* Enable SITRE (separate slave timing register) */ |
1da177e4 | 699 | master_data |= 0x4000; |
669a5db4 JG |
700 | /* enable PPE1, IE1 and TIME1 as needed */ |
701 | master_data |= (control << 4); | |
1da177e4 | 702 | pci_read_config_byte(dev, slave_port, &slave_data); |
2a88d1ac | 703 | slave_data &= (ap->port_no ? 0x0f : 0xf0); |
669a5db4 | 704 | /* Load the timing nibble for this slave */ |
a5bf5f5a TH |
705 | slave_data |= ((timings[pio][0] << 2) | timings[pio][1]) |
706 | << (ap->port_no ? 4 : 0); | |
1da177e4 | 707 | } else { |
a5bf5f5a TH |
708 | /* clear ISP|RCT|TIME0|IE0|PPE0|DTE0 */ |
709 | master_data &= 0xccf0; | |
669a5db4 JG |
710 | /* Enable PPE, IE and TIME as appropriate */ |
711 | master_data |= control; | |
a5bf5f5a | 712 | /* load ISP and RCT */ |
1da177e4 LT |
713 | master_data |= |
714 | (timings[pio][0] << 12) | | |
715 | (timings[pio][1] << 8); | |
716 | } | |
717 | pci_write_config_word(dev, master_port, master_data); | |
718 | if (is_slave) | |
719 | pci_write_config_byte(dev, slave_port, slave_data); | |
669a5db4 JG |
720 | |
721 | /* Ensure the UDMA bit is off - it will be turned back on if | |
722 | UDMA is selected */ | |
85cd7251 | 723 | |
669a5db4 JG |
724 | if (ap->udma_mask) { |
725 | pci_read_config_byte(dev, 0x48, &udma_enable); | |
726 | udma_enable &= ~(1 << (2 * ap->port_no + adev->devno)); | |
727 | pci_write_config_byte(dev, 0x48, udma_enable); | |
728 | } | |
1da177e4 LT |
729 | } |
730 | ||
731 | /** | |
669a5db4 | 732 | * do_pata_set_dmamode - Initialize host controller PATA PIO timings |
1da177e4 | 733 | * @ap: Port whose timings we are configuring |
669a5db4 | 734 | * @adev: Drive in question |
1da177e4 | 735 | * @udma: udma mode, 0 - 6 |
c32a8fd7 | 736 | * @isich: set if the chip is an ICH device |
1da177e4 LT |
737 | * |
738 | * Set UDMA mode for device, in host controller PCI config space. | |
739 | * | |
740 | * LOCKING: | |
741 | * None (inherited from caller). | |
742 | */ | |
743 | ||
2dcb407e | 744 | static void do_pata_set_dmamode(struct ata_port *ap, struct ata_device *adev, int isich) |
1da177e4 | 745 | { |
cca3974e | 746 | struct pci_dev *dev = to_pci_dev(ap->host->dev); |
669a5db4 JG |
747 | u8 master_port = ap->port_no ? 0x42 : 0x40; |
748 | u16 master_data; | |
749 | u8 speed = adev->dma_mode; | |
750 | int devid = adev->devno + 2 * ap->port_no; | |
dedf61db | 751 | u8 udma_enable = 0; |
85cd7251 | 752 | |
669a5db4 JG |
753 | static const /* ISP RTC */ |
754 | u8 timings[][2] = { { 0, 0 }, | |
755 | { 0, 0 }, | |
756 | { 1, 0 }, | |
757 | { 2, 1 }, | |
758 | { 2, 3 }, }; | |
759 | ||
760 | pci_read_config_word(dev, master_port, &master_data); | |
d2cdfc0d A |
761 | if (ap->udma_mask) |
762 | pci_read_config_byte(dev, 0x48, &udma_enable); | |
1da177e4 LT |
763 | |
764 | if (speed >= XFER_UDMA_0) { | |
669a5db4 JG |
765 | unsigned int udma = adev->dma_mode - XFER_UDMA_0; |
766 | u16 udma_timing; | |
767 | u16 ideconf; | |
768 | int u_clock, u_speed; | |
85cd7251 | 769 | |
669a5db4 | 770 | /* |
2dcb407e | 771 | * UDMA is handled by a combination of clock switching and |
85cd7251 JG |
772 | * selection of dividers |
773 | * | |
669a5db4 | 774 | * Handy rule: Odd modes are UDMATIMx 01, even are 02 |
85cd7251 | 775 | * except UDMA0 which is 00 |
669a5db4 JG |
776 | */ |
777 | u_speed = min(2 - (udma & 1), udma); | |
778 | if (udma == 5) | |
779 | u_clock = 0x1000; /* 100Mhz */ | |
780 | else if (udma > 2) | |
781 | u_clock = 1; /* 66Mhz */ | |
782 | else | |
783 | u_clock = 0; /* 33Mhz */ | |
85cd7251 | 784 | |
669a5db4 | 785 | udma_enable |= (1 << devid); |
85cd7251 | 786 | |
669a5db4 JG |
787 | /* Load the CT/RP selection */ |
788 | pci_read_config_word(dev, 0x4A, &udma_timing); | |
789 | udma_timing &= ~(3 << (4 * devid)); | |
790 | udma_timing |= u_speed << (4 * devid); | |
791 | pci_write_config_word(dev, 0x4A, udma_timing); | |
792 | ||
85cd7251 | 793 | if (isich) { |
669a5db4 JG |
794 | /* Select a 33/66/100Mhz clock */ |
795 | pci_read_config_word(dev, 0x54, &ideconf); | |
796 | ideconf &= ~(0x1001 << devid); | |
797 | ideconf |= u_clock << devid; | |
798 | /* For ICH or later we should set bit 10 for better | |
799 | performance (WR_PingPong_En) */ | |
800 | pci_write_config_word(dev, 0x54, ideconf); | |
1da177e4 | 801 | } |
1da177e4 | 802 | } else { |
669a5db4 JG |
803 | /* |
804 | * MWDMA is driven by the PIO timings. We must also enable | |
805 | * IORDY unconditionally along with TIME1. PPE has already | |
806 | * been set when the PIO timing was set. | |
807 | */ | |
808 | unsigned int mwdma = adev->dma_mode - XFER_MW_DMA_0; | |
809 | unsigned int control; | |
810 | u8 slave_data; | |
811 | const unsigned int needed_pio[3] = { | |
812 | XFER_PIO_0, XFER_PIO_3, XFER_PIO_4 | |
813 | }; | |
814 | int pio = needed_pio[mwdma] - XFER_PIO_0; | |
85cd7251 | 815 | |
669a5db4 | 816 | control = 3; /* IORDY|TIME1 */ |
85cd7251 | 817 | |
669a5db4 JG |
818 | /* If the drive MWDMA is faster than it can do PIO then |
819 | we must force PIO into PIO0 */ | |
85cd7251 | 820 | |
669a5db4 JG |
821 | if (adev->pio_mode < needed_pio[mwdma]) |
822 | /* Enable DMA timing only */ | |
823 | control |= 8; /* PIO cycles in PIO0 */ | |
824 | ||
825 | if (adev->devno) { /* Slave */ | |
826 | master_data &= 0xFF4F; /* Mask out IORDY|TIME1|DMAONLY */ | |
827 | master_data |= control << 4; | |
828 | pci_read_config_byte(dev, 0x44, &slave_data); | |
a5bf5f5a | 829 | slave_data &= (ap->port_no ? 0x0f : 0xf0); |
669a5db4 JG |
830 | /* Load the matching timing */ |
831 | slave_data |= ((timings[pio][0] << 2) | timings[pio][1]) << (ap->port_no ? 4 : 0); | |
832 | pci_write_config_byte(dev, 0x44, slave_data); | |
833 | } else { /* Master */ | |
85cd7251 | 834 | master_data &= 0xCCF4; /* Mask out IORDY|TIME1|DMAONLY |
669a5db4 JG |
835 | and master timing bits */ |
836 | master_data |= control; | |
837 | master_data |= | |
838 | (timings[pio][0] << 12) | | |
839 | (timings[pio][1] << 8); | |
840 | } | |
a5bf5f5a TH |
841 | |
842 | if (ap->udma_mask) { | |
843 | udma_enable &= ~(1 << devid); | |
844 | pci_write_config_word(dev, master_port, master_data); | |
845 | } | |
1da177e4 | 846 | } |
669a5db4 JG |
847 | /* Don't scribble on 0x48 if the controller does not support UDMA */ |
848 | if (ap->udma_mask) | |
849 | pci_write_config_byte(dev, 0x48, udma_enable); | |
850 | } | |
851 | ||
852 | /** | |
853 | * piix_set_dmamode - Initialize host controller PATA DMA timings | |
854 | * @ap: Port whose timings we are configuring | |
855 | * @adev: um | |
856 | * | |
857 | * Set MW/UDMA mode for device, in host controller PCI config space. | |
858 | * | |
859 | * LOCKING: | |
860 | * None (inherited from caller). | |
861 | */ | |
862 | ||
2dcb407e | 863 | static void piix_set_dmamode(struct ata_port *ap, struct ata_device *adev) |
669a5db4 JG |
864 | { |
865 | do_pata_set_dmamode(ap, adev, 0); | |
866 | } | |
867 | ||
868 | /** | |
869 | * ich_set_dmamode - Initialize host controller PATA DMA timings | |
870 | * @ap: Port whose timings we are configuring | |
871 | * @adev: um | |
872 | * | |
873 | * Set MW/UDMA mode for device, in host controller PCI config space. | |
874 | * | |
875 | * LOCKING: | |
876 | * None (inherited from caller). | |
877 | */ | |
878 | ||
2dcb407e | 879 | static void ich_set_dmamode(struct ata_port *ap, struct ata_device *adev) |
669a5db4 JG |
880 | { |
881 | do_pata_set_dmamode(ap, adev, 1); | |
1da177e4 LT |
882 | } |
883 | ||
c7290724 TH |
884 | /* |
885 | * Serial ATA Index/Data Pair Superset Registers access | |
886 | * | |
887 | * Beginning from ICH8, there's a sane way to access SCRs using index | |
888 | * and data register pair located at BAR5. This creates an | |
889 | * interesting problem of mapping two SCRs to one port. | |
890 | * | |
891 | * Although they have separate SCRs, the master and slave aren't | |
892 | * independent enough to be treated as separate links - e.g. softreset | |
893 | * resets both. Also, there's no protocol defined for hard resetting | |
894 | * singled device sharing the virtual port (no defined way to acquire | |
895 | * device signature). This is worked around by merging the SCR values | |
896 | * into one sensible value and requesting follow-up SRST after | |
897 | * hardreset. | |
898 | * | |
899 | * SCR merging is perfomed in nibbles which is the unit contents in | |
900 | * SCRs are organized. If two values are equal, the value is used. | |
901 | * When they differ, merge table which lists precedence of possible | |
902 | * values is consulted and the first match or the last entry when | |
903 | * nothing matches is used. When there's no merge table for the | |
904 | * specific nibble, value from the first port is used. | |
905 | */ | |
906 | static const int piix_sidx_map[] = { | |
907 | [SCR_STATUS] = 0, | |
908 | [SCR_ERROR] = 2, | |
909 | [SCR_CONTROL] = 1, | |
910 | }; | |
911 | ||
912 | static void piix_sidpr_sel(struct ata_device *dev, unsigned int reg) | |
913 | { | |
914 | struct ata_port *ap = dev->link->ap; | |
915 | struct piix_host_priv *hpriv = ap->host->private_data; | |
916 | ||
917 | iowrite32(((ap->port_no * 2 + dev->devno) << 8) | piix_sidx_map[reg], | |
918 | hpriv->sidpr + PIIX_SIDPR_IDX); | |
919 | } | |
920 | ||
921 | static int piix_sidpr_read(struct ata_device *dev, unsigned int reg) | |
922 | { | |
923 | struct piix_host_priv *hpriv = dev->link->ap->host->private_data; | |
924 | ||
925 | piix_sidpr_sel(dev, reg); | |
926 | return ioread32(hpriv->sidpr + PIIX_SIDPR_DATA); | |
927 | } | |
928 | ||
929 | static void piix_sidpr_write(struct ata_device *dev, unsigned int reg, u32 val) | |
930 | { | |
931 | struct piix_host_priv *hpriv = dev->link->ap->host->private_data; | |
932 | ||
933 | piix_sidpr_sel(dev, reg); | |
934 | iowrite32(val, hpriv->sidpr + PIIX_SIDPR_DATA); | |
935 | } | |
936 | ||
4a537a55 | 937 | static u32 piix_merge_scr(u32 val0, u32 val1, const int * const *merge_tbl) |
c7290724 TH |
938 | { |
939 | u32 val = 0; | |
940 | int i, mi; | |
941 | ||
942 | for (i = 0, mi = 0; i < 32 / 4; i++) { | |
943 | u8 c0 = (val0 >> (i * 4)) & 0xf; | |
944 | u8 c1 = (val1 >> (i * 4)) & 0xf; | |
945 | u8 merged = c0; | |
946 | const int *cur; | |
947 | ||
948 | /* if no merge preference, assume the first value */ | |
949 | cur = merge_tbl[mi]; | |
950 | if (!cur) | |
951 | goto done; | |
952 | mi++; | |
953 | ||
954 | /* if two values equal, use it */ | |
955 | if (c0 == c1) | |
956 | goto done; | |
957 | ||
958 | /* choose the first match or the last from the merge table */ | |
959 | while (*cur != -1) { | |
960 | if (c0 == *cur || c1 == *cur) | |
961 | break; | |
962 | cur++; | |
963 | } | |
964 | if (*cur == -1) | |
965 | cur--; | |
966 | merged = *cur; | |
967 | done: | |
968 | val |= merged << (i * 4); | |
969 | } | |
970 | ||
971 | return val; | |
972 | } | |
973 | ||
974 | static int piix_sidpr_scr_read(struct ata_port *ap, unsigned int reg, u32 *val) | |
975 | { | |
976 | const int * const sstatus_merge_tbl[] = { | |
977 | /* DET */ (const int []){ 1, 3, 0, 4, 3, -1 }, | |
978 | /* SPD */ (const int []){ 2, 1, 0, -1 }, | |
979 | /* IPM */ (const int []){ 6, 2, 1, 0, -1 }, | |
980 | NULL, | |
981 | }; | |
982 | const int * const scontrol_merge_tbl[] = { | |
983 | /* DET */ (const int []){ 1, 0, 4, 0, -1 }, | |
984 | /* SPD */ (const int []){ 0, 2, 1, 0, -1 }, | |
985 | /* IPM */ (const int []){ 0, 1, 2, 3, 0, -1 }, | |
986 | NULL, | |
987 | }; | |
988 | u32 v0, v1; | |
989 | ||
990 | if (reg >= ARRAY_SIZE(piix_sidx_map)) | |
991 | return -EINVAL; | |
992 | ||
993 | if (!(ap->flags & ATA_FLAG_SLAVE_POSS)) { | |
994 | *val = piix_sidpr_read(&ap->link.device[0], reg); | |
995 | return 0; | |
996 | } | |
997 | ||
998 | v0 = piix_sidpr_read(&ap->link.device[0], reg); | |
999 | v1 = piix_sidpr_read(&ap->link.device[1], reg); | |
1000 | ||
1001 | switch (reg) { | |
1002 | case SCR_STATUS: | |
1003 | *val = piix_merge_scr(v0, v1, sstatus_merge_tbl); | |
1004 | break; | |
1005 | case SCR_ERROR: | |
1006 | *val = v0 | v1; | |
1007 | break; | |
1008 | case SCR_CONTROL: | |
1009 | *val = piix_merge_scr(v0, v1, scontrol_merge_tbl); | |
1010 | break; | |
1011 | } | |
1012 | ||
1013 | return 0; | |
1014 | } | |
1015 | ||
1016 | static int piix_sidpr_scr_write(struct ata_port *ap, unsigned int reg, u32 val) | |
1017 | { | |
1018 | if (reg >= ARRAY_SIZE(piix_sidx_map)) | |
1019 | return -EINVAL; | |
1020 | ||
1021 | piix_sidpr_write(&ap->link.device[0], reg, val); | |
1022 | ||
1023 | if (ap->flags & ATA_FLAG_SLAVE_POSS) | |
1024 | piix_sidpr_write(&ap->link.device[1], reg, val); | |
1025 | ||
1026 | return 0; | |
1027 | } | |
1028 | ||
b8b275ef | 1029 | #ifdef CONFIG_PM |
8c3832eb TH |
1030 | static int piix_broken_suspend(void) |
1031 | { | |
1855256c | 1032 | static const struct dmi_system_id sysids[] = { |
4c74d4ec TH |
1033 | { |
1034 | .ident = "TECRA M3", | |
1035 | .matches = { | |
1036 | DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), | |
1037 | DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M3"), | |
1038 | }, | |
1039 | }, | |
04d86d6f PS |
1040 | { |
1041 | .ident = "TECRA M3", | |
1042 | .matches = { | |
1043 | DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), | |
1044 | DMI_MATCH(DMI_PRODUCT_NAME, "Tecra M3"), | |
1045 | }, | |
1046 | }, | |
d1aa690a PS |
1047 | { |
1048 | .ident = "TECRA M4", | |
1049 | .matches = { | |
1050 | DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), | |
1051 | DMI_MATCH(DMI_PRODUCT_NAME, "Tecra M4"), | |
1052 | }, | |
1053 | }, | |
040dee53 TH |
1054 | { |
1055 | .ident = "TECRA M4", | |
1056 | .matches = { | |
1057 | DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), | |
1058 | DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M4"), | |
1059 | }, | |
1060 | }, | |
8c3832eb TH |
1061 | { |
1062 | .ident = "TECRA M5", | |
1063 | .matches = { | |
1064 | DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), | |
1065 | DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M5"), | |
1066 | }, | |
b8b275ef | 1067 | }, |
ffe188dd PS |
1068 | { |
1069 | .ident = "TECRA M6", | |
1070 | .matches = { | |
1071 | DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), | |
1072 | DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M6"), | |
1073 | }, | |
1074 | }, | |
5c08ea01 TH |
1075 | { |
1076 | .ident = "TECRA M7", | |
1077 | .matches = { | |
1078 | DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), | |
1079 | DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M7"), | |
1080 | }, | |
1081 | }, | |
04d86d6f PS |
1082 | { |
1083 | .ident = "TECRA A8", | |
1084 | .matches = { | |
1085 | DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), | |
1086 | DMI_MATCH(DMI_PRODUCT_NAME, "TECRA A8"), | |
1087 | }, | |
1088 | }, | |
ffe188dd PS |
1089 | { |
1090 | .ident = "Satellite R20", | |
1091 | .matches = { | |
1092 | DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), | |
1093 | DMI_MATCH(DMI_PRODUCT_NAME, "Satellite R20"), | |
1094 | }, | |
1095 | }, | |
04d86d6f PS |
1096 | { |
1097 | .ident = "Satellite R25", | |
1098 | .matches = { | |
1099 | DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), | |
1100 | DMI_MATCH(DMI_PRODUCT_NAME, "Satellite R25"), | |
1101 | }, | |
1102 | }, | |
3cc0b9d3 TH |
1103 | { |
1104 | .ident = "Satellite U200", | |
1105 | .matches = { | |
1106 | DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), | |
1107 | DMI_MATCH(DMI_PRODUCT_NAME, "Satellite U200"), | |
1108 | }, | |
1109 | }, | |
04d86d6f PS |
1110 | { |
1111 | .ident = "Satellite U200", | |
1112 | .matches = { | |
1113 | DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), | |
1114 | DMI_MATCH(DMI_PRODUCT_NAME, "SATELLITE U200"), | |
1115 | }, | |
1116 | }, | |
62320e23 YC |
1117 | { |
1118 | .ident = "Satellite Pro U200", | |
1119 | .matches = { | |
1120 | DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), | |
1121 | DMI_MATCH(DMI_PRODUCT_NAME, "SATELLITE PRO U200"), | |
1122 | }, | |
1123 | }, | |
8c3832eb TH |
1124 | { |
1125 | .ident = "Satellite U205", | |
1126 | .matches = { | |
1127 | DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), | |
1128 | DMI_MATCH(DMI_PRODUCT_NAME, "Satellite U205"), | |
1129 | }, | |
b8b275ef | 1130 | }, |
de753e5e TH |
1131 | { |
1132 | .ident = "SATELLITE U205", | |
1133 | .matches = { | |
1134 | DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), | |
1135 | DMI_MATCH(DMI_PRODUCT_NAME, "SATELLITE U205"), | |
1136 | }, | |
1137 | }, | |
8c3832eb TH |
1138 | { |
1139 | .ident = "Portege M500", | |
1140 | .matches = { | |
1141 | DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), | |
1142 | DMI_MATCH(DMI_PRODUCT_NAME, "PORTEGE M500"), | |
1143 | }, | |
b8b275ef | 1144 | }, |
7d051548 JG |
1145 | |
1146 | { } /* terminate list */ | |
8c3832eb | 1147 | }; |
7abe79c3 TH |
1148 | static const char *oemstrs[] = { |
1149 | "Tecra M3,", | |
1150 | }; | |
1151 | int i; | |
8c3832eb TH |
1152 | |
1153 | if (dmi_check_system(sysids)) | |
1154 | return 1; | |
1155 | ||
7abe79c3 TH |
1156 | for (i = 0; i < ARRAY_SIZE(oemstrs); i++) |
1157 | if (dmi_find_device(DMI_DEV_TYPE_OEM_STRING, oemstrs[i], NULL)) | |
1158 | return 1; | |
1159 | ||
8c3832eb TH |
1160 | return 0; |
1161 | } | |
b8b275ef TH |
1162 | |
1163 | static int piix_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg) | |
1164 | { | |
1165 | struct ata_host *host = dev_get_drvdata(&pdev->dev); | |
1166 | unsigned long flags; | |
1167 | int rc = 0; | |
1168 | ||
1169 | rc = ata_host_suspend(host, mesg); | |
1170 | if (rc) | |
1171 | return rc; | |
1172 | ||
1173 | /* Some braindamaged ACPI suspend implementations expect the | |
1174 | * controller to be awake on entry; otherwise, it burns cpu | |
1175 | * cycles and power trying to do something to the sleeping | |
1176 | * beauty. | |
1177 | */ | |
3a2d5b70 | 1178 | if (piix_broken_suspend() && (mesg.event & PM_EVENT_SLEEP)) { |
b8b275ef TH |
1179 | pci_save_state(pdev); |
1180 | ||
1181 | /* mark its power state as "unknown", since we don't | |
1182 | * know if e.g. the BIOS will change its device state | |
1183 | * when we suspend. | |
1184 | */ | |
1185 | if (pdev->current_state == PCI_D0) | |
1186 | pdev->current_state = PCI_UNKNOWN; | |
1187 | ||
1188 | /* tell resume that it's waking up from broken suspend */ | |
1189 | spin_lock_irqsave(&host->lock, flags); | |
1190 | host->flags |= PIIX_HOST_BROKEN_SUSPEND; | |
1191 | spin_unlock_irqrestore(&host->lock, flags); | |
1192 | } else | |
1193 | ata_pci_device_do_suspend(pdev, mesg); | |
1194 | ||
1195 | return 0; | |
1196 | } | |
1197 | ||
1198 | static int piix_pci_device_resume(struct pci_dev *pdev) | |
1199 | { | |
1200 | struct ata_host *host = dev_get_drvdata(&pdev->dev); | |
1201 | unsigned long flags; | |
1202 | int rc; | |
1203 | ||
1204 | if (host->flags & PIIX_HOST_BROKEN_SUSPEND) { | |
1205 | spin_lock_irqsave(&host->lock, flags); | |
1206 | host->flags &= ~PIIX_HOST_BROKEN_SUSPEND; | |
1207 | spin_unlock_irqrestore(&host->lock, flags); | |
1208 | ||
1209 | pci_set_power_state(pdev, PCI_D0); | |
1210 | pci_restore_state(pdev); | |
1211 | ||
1212 | /* PCI device wasn't disabled during suspend. Use | |
0b62e13b TH |
1213 | * pci_reenable_device() to avoid affecting the enable |
1214 | * count. | |
b8b275ef | 1215 | */ |
0b62e13b | 1216 | rc = pci_reenable_device(pdev); |
b8b275ef TH |
1217 | if (rc) |
1218 | dev_printk(KERN_ERR, &pdev->dev, "failed to enable " | |
1219 | "device after resume (%d)\n", rc); | |
1220 | } else | |
1221 | rc = ata_pci_device_do_resume(pdev); | |
1222 | ||
1223 | if (rc == 0) | |
1224 | ata_host_resume(host); | |
1225 | ||
1226 | return rc; | |
1227 | } | |
1228 | #endif | |
1229 | ||
25f98131 TH |
1230 | static u8 piix_vmw_bmdma_status(struct ata_port *ap) |
1231 | { | |
1232 | return ata_bmdma_status(ap) & ~ATA_DMA_ERR; | |
1233 | } | |
1234 | ||
1da177e4 LT |
1235 | #define AHCI_PCI_BAR 5 |
1236 | #define AHCI_GLOBAL_CTL 0x04 | |
1237 | #define AHCI_ENABLE (1 << 31) | |
1238 | static int piix_disable_ahci(struct pci_dev *pdev) | |
1239 | { | |
ea6ba10b | 1240 | void __iomem *mmio; |
1da177e4 LT |
1241 | u32 tmp; |
1242 | int rc = 0; | |
1243 | ||
1244 | /* BUG: pci_enable_device has not yet been called. This | |
1245 | * works because this device is usually set up by BIOS. | |
1246 | */ | |
1247 | ||
374b1873 JG |
1248 | if (!pci_resource_start(pdev, AHCI_PCI_BAR) || |
1249 | !pci_resource_len(pdev, AHCI_PCI_BAR)) | |
1da177e4 | 1250 | return 0; |
7b6dbd68 | 1251 | |
374b1873 | 1252 | mmio = pci_iomap(pdev, AHCI_PCI_BAR, 64); |
1da177e4 LT |
1253 | if (!mmio) |
1254 | return -ENOMEM; | |
7b6dbd68 | 1255 | |
c47a631f | 1256 | tmp = ioread32(mmio + AHCI_GLOBAL_CTL); |
1da177e4 LT |
1257 | if (tmp & AHCI_ENABLE) { |
1258 | tmp &= ~AHCI_ENABLE; | |
c47a631f | 1259 | iowrite32(tmp, mmio + AHCI_GLOBAL_CTL); |
1da177e4 | 1260 | |
c47a631f | 1261 | tmp = ioread32(mmio + AHCI_GLOBAL_CTL); |
1da177e4 LT |
1262 | if (tmp & AHCI_ENABLE) |
1263 | rc = -EIO; | |
1264 | } | |
7b6dbd68 | 1265 | |
374b1873 | 1266 | pci_iounmap(pdev, mmio); |
1da177e4 LT |
1267 | return rc; |
1268 | } | |
1269 | ||
c621b140 AC |
1270 | /** |
1271 | * piix_check_450nx_errata - Check for problem 450NX setup | |
c893a3ae | 1272 | * @ata_dev: the PCI device to check |
2e9edbf8 | 1273 | * |
c621b140 AC |
1274 | * Check for the present of 450NX errata #19 and errata #25. If |
1275 | * they are found return an error code so we can turn off DMA | |
1276 | */ | |
1277 | ||
1278 | static int __devinit piix_check_450nx_errata(struct pci_dev *ata_dev) | |
1279 | { | |
1280 | struct pci_dev *pdev = NULL; | |
1281 | u16 cfg; | |
c621b140 | 1282 | int no_piix_dma = 0; |
2e9edbf8 | 1283 | |
2dcb407e | 1284 | while ((pdev = pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, pdev)) != NULL) { |
c621b140 AC |
1285 | /* Look for 450NX PXB. Check for problem configurations |
1286 | A PCI quirk checks bit 6 already */ | |
c621b140 AC |
1287 | pci_read_config_word(pdev, 0x41, &cfg); |
1288 | /* Only on the original revision: IDE DMA can hang */ | |
44c10138 | 1289 | if (pdev->revision == 0x00) |
c621b140 AC |
1290 | no_piix_dma = 1; |
1291 | /* On all revisions below 5 PXB bus lock must be disabled for IDE */ | |
44c10138 | 1292 | else if (cfg & (1<<14) && pdev->revision < 5) |
c621b140 AC |
1293 | no_piix_dma = 2; |
1294 | } | |
31a34fe7 | 1295 | if (no_piix_dma) |
c621b140 | 1296 | dev_printk(KERN_WARNING, &ata_dev->dev, "450NX errata present, disabling IDE DMA.\n"); |
31a34fe7 | 1297 | if (no_piix_dma == 2) |
c621b140 AC |
1298 | dev_printk(KERN_WARNING, &ata_dev->dev, "A BIOS update may resolve this.\n"); |
1299 | return no_piix_dma; | |
2e9edbf8 | 1300 | } |
c621b140 | 1301 | |
8b09f0da | 1302 | static void __devinit piix_init_pcs(struct ata_host *host, |
ea35d29e JG |
1303 | const struct piix_map_db *map_db) |
1304 | { | |
8b09f0da | 1305 | struct pci_dev *pdev = to_pci_dev(host->dev); |
ea35d29e JG |
1306 | u16 pcs, new_pcs; |
1307 | ||
1308 | pci_read_config_word(pdev, ICH5_PCS, &pcs); | |
1309 | ||
1310 | new_pcs = pcs | map_db->port_enable; | |
1311 | ||
1312 | if (new_pcs != pcs) { | |
1313 | DPRINTK("updating PCS from 0x%x to 0x%x\n", pcs, new_pcs); | |
1314 | pci_write_config_word(pdev, ICH5_PCS, new_pcs); | |
1315 | msleep(150); | |
1316 | } | |
1317 | } | |
1318 | ||
8b09f0da TH |
1319 | static const int *__devinit piix_init_sata_map(struct pci_dev *pdev, |
1320 | struct ata_port_info *pinfo, | |
1321 | const struct piix_map_db *map_db) | |
d33f58b8 | 1322 | { |
b4482a4b | 1323 | const int *map; |
d33f58b8 TH |
1324 | int i, invalid_map = 0; |
1325 | u8 map_value; | |
1326 | ||
1327 | pci_read_config_byte(pdev, ICH5_PMR, &map_value); | |
1328 | ||
1329 | map = map_db->map[map_value & map_db->mask]; | |
1330 | ||
1331 | dev_printk(KERN_INFO, &pdev->dev, "MAP ["); | |
1332 | for (i = 0; i < 4; i++) { | |
1333 | switch (map[i]) { | |
1334 | case RV: | |
1335 | invalid_map = 1; | |
1336 | printk(" XX"); | |
1337 | break; | |
1338 | ||
1339 | case NA: | |
1340 | printk(" --"); | |
1341 | break; | |
1342 | ||
1343 | case IDE: | |
1344 | WARN_ON((i & 1) || map[i + 1] != IDE); | |
669a5db4 | 1345 | pinfo[i / 2] = piix_port_info[ich_pata_100]; |
d33f58b8 TH |
1346 | i++; |
1347 | printk(" IDE IDE"); | |
1348 | break; | |
1349 | ||
1350 | default: | |
1351 | printk(" P%d", map[i]); | |
1352 | if (i & 1) | |
cca3974e | 1353 | pinfo[i / 2].flags |= ATA_FLAG_SLAVE_POSS; |
d33f58b8 TH |
1354 | break; |
1355 | } | |
1356 | } | |
1357 | printk(" ]\n"); | |
1358 | ||
1359 | if (invalid_map) | |
1360 | dev_printk(KERN_ERR, &pdev->dev, | |
1361 | "invalid MAP value %u\n", map_value); | |
1362 | ||
8b09f0da | 1363 | return map; |
d33f58b8 TH |
1364 | } |
1365 | ||
c7290724 TH |
1366 | static void __devinit piix_init_sidpr(struct ata_host *host) |
1367 | { | |
1368 | struct pci_dev *pdev = to_pci_dev(host->dev); | |
1369 | struct piix_host_priv *hpriv = host->private_data; | |
cb6716c8 TH |
1370 | struct ata_device *dev0 = &host->ports[0]->link.device[0]; |
1371 | u32 scontrol; | |
c7290724 TH |
1372 | int i; |
1373 | ||
1374 | /* check for availability */ | |
1375 | for (i = 0; i < 4; i++) | |
1376 | if (hpriv->map[i] == IDE) | |
1377 | return; | |
1378 | ||
1379 | if (!(host->ports[0]->flags & PIIX_FLAG_SIDPR)) | |
1380 | return; | |
1381 | ||
1382 | if (pci_resource_start(pdev, PIIX_SIDPR_BAR) == 0 || | |
1383 | pci_resource_len(pdev, PIIX_SIDPR_BAR) != PIIX_SIDPR_LEN) | |
1384 | return; | |
1385 | ||
1386 | if (pcim_iomap_regions(pdev, 1 << PIIX_SIDPR_BAR, DRV_NAME)) | |
1387 | return; | |
1388 | ||
1389 | hpriv->sidpr = pcim_iomap_table(pdev)[PIIX_SIDPR_BAR]; | |
cb6716c8 TH |
1390 | |
1391 | /* SCR access via SIDPR doesn't work on some configurations. | |
1392 | * Give it a test drive by inhibiting power save modes which | |
1393 | * we'll do anyway. | |
1394 | */ | |
1395 | scontrol = piix_sidpr_read(dev0, SCR_CONTROL); | |
1396 | ||
1397 | /* if IPM is already 3, SCR access is probably working. Don't | |
1398 | * un-inhibit power save modes as BIOS might have inhibited | |
1399 | * them for a reason. | |
1400 | */ | |
1401 | if ((scontrol & 0xf00) != 0x300) { | |
1402 | scontrol |= 0x300; | |
1403 | piix_sidpr_write(dev0, SCR_CONTROL, scontrol); | |
1404 | scontrol = piix_sidpr_read(dev0, SCR_CONTROL); | |
1405 | ||
1406 | if ((scontrol & 0xf00) != 0x300) { | |
1407 | dev_printk(KERN_INFO, host->dev, "SCR access via " | |
1408 | "SIDPR is available but doesn't work\n"); | |
1409 | return; | |
1410 | } | |
1411 | } | |
1412 | ||
c7290724 TH |
1413 | host->ports[0]->ops = &piix_sidpr_sata_ops; |
1414 | host->ports[1]->ops = &piix_sidpr_sata_ops; | |
1415 | } | |
1416 | ||
43a98f05 TH |
1417 | static void piix_iocfg_bit18_quirk(struct pci_dev *pdev) |
1418 | { | |
1855256c | 1419 | static const struct dmi_system_id sysids[] = { |
43a98f05 TH |
1420 | { |
1421 | /* Clevo M570U sets IOCFG bit 18 if the cdrom | |
1422 | * isn't used to boot the system which | |
1423 | * disables the channel. | |
1424 | */ | |
1425 | .ident = "M570U", | |
1426 | .matches = { | |
1427 | DMI_MATCH(DMI_SYS_VENDOR, "Clevo Co."), | |
1428 | DMI_MATCH(DMI_PRODUCT_NAME, "M570U"), | |
1429 | }, | |
1430 | }, | |
7d051548 JG |
1431 | |
1432 | { } /* terminate list */ | |
43a98f05 TH |
1433 | }; |
1434 | u32 iocfg; | |
1435 | ||
1436 | if (!dmi_check_system(sysids)) | |
1437 | return; | |
1438 | ||
1439 | /* The datasheet says that bit 18 is NOOP but certain systems | |
1440 | * seem to use it to disable a channel. Clear the bit on the | |
1441 | * affected systems. | |
1442 | */ | |
1443 | pci_read_config_dword(pdev, PIIX_IOCFG, &iocfg); | |
1444 | if (iocfg & (1 << 18)) { | |
1445 | dev_printk(KERN_INFO, &pdev->dev, | |
1446 | "applying IOCFG bit18 quirk\n"); | |
1447 | iocfg &= ~(1 << 18); | |
1448 | pci_write_config_dword(pdev, PIIX_IOCFG, iocfg); | |
1449 | } | |
1450 | } | |
1451 | ||
1da177e4 LT |
1452 | /** |
1453 | * piix_init_one - Register PIIX ATA PCI device with kernel services | |
1454 | * @pdev: PCI device to register | |
1455 | * @ent: Entry in piix_pci_tbl matching with @pdev | |
1456 | * | |
1457 | * Called from kernel PCI layer. We probe for combined mode (sigh), | |
1458 | * and then hand over control to libata, for it to do the rest. | |
1459 | * | |
1460 | * LOCKING: | |
1461 | * Inherited from PCI layer (may sleep). | |
1462 | * | |
1463 | * RETURNS: | |
1464 | * Zero on success, or -ERRNO value. | |
1465 | */ | |
1466 | ||
bc5468f5 AB |
1467 | static int __devinit piix_init_one(struct pci_dev *pdev, |
1468 | const struct pci_device_id *ent) | |
1da177e4 LT |
1469 | { |
1470 | static int printed_version; | |
24dc5f33 | 1471 | struct device *dev = &pdev->dev; |
d33f58b8 | 1472 | struct ata_port_info port_info[2]; |
1626aeb8 | 1473 | const struct ata_port_info *ppi[] = { &port_info[0], &port_info[1] }; |
cca3974e | 1474 | unsigned long port_flags; |
8b09f0da TH |
1475 | struct ata_host *host; |
1476 | struct piix_host_priv *hpriv; | |
1477 | int rc; | |
1da177e4 LT |
1478 | |
1479 | if (!printed_version++) | |
6248e647 JG |
1480 | dev_printk(KERN_DEBUG, &pdev->dev, |
1481 | "version " DRV_VERSION "\n"); | |
1da177e4 LT |
1482 | |
1483 | /* no hotplugging support (FIXME) */ | |
1484 | if (!in_module_init) | |
1485 | return -ENODEV; | |
1486 | ||
8b09f0da TH |
1487 | port_info[0] = piix_port_info[ent->driver_data]; |
1488 | port_info[1] = piix_port_info[ent->driver_data]; | |
1489 | ||
1490 | port_flags = port_info[0].flags; | |
1491 | ||
1492 | /* enable device and prepare host */ | |
1493 | rc = pcim_enable_device(pdev); | |
1494 | if (rc) | |
1495 | return rc; | |
1496 | ||
5016d7d2 TH |
1497 | /* ICH6R may be driven by either ata_piix or ahci driver |
1498 | * regardless of BIOS configuration. Make sure AHCI mode is | |
1499 | * off. | |
1500 | */ | |
1501 | if (pdev->vendor == PCI_VENDOR_ID_INTEL && pdev->device == 0x2652) { | |
da3ceb22 | 1502 | rc = piix_disable_ahci(pdev); |
5016d7d2 TH |
1503 | if (rc) |
1504 | return rc; | |
1505 | } | |
1506 | ||
8b09f0da | 1507 | /* SATA map init can change port_info, do it before prepping host */ |
24dc5f33 | 1508 | hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL); |
d96715c1 TH |
1509 | if (!hpriv) |
1510 | return -ENOMEM; | |
1511 | ||
8b09f0da TH |
1512 | if (port_flags & ATA_FLAG_SATA) |
1513 | hpriv->map = piix_init_sata_map(pdev, port_info, | |
1514 | piix_map_db_table[ent->driver_data]); | |
1da177e4 | 1515 | |
9363c382 | 1516 | rc = ata_pci_sff_prepare_host(pdev, ppi, &host); |
8b09f0da TH |
1517 | if (rc) |
1518 | return rc; | |
1519 | host->private_data = hpriv; | |
ff0fc146 | 1520 | |
8b09f0da | 1521 | /* initialize controller */ |
c7290724 | 1522 | if (port_flags & ATA_FLAG_SATA) { |
8b09f0da | 1523 | piix_init_pcs(host, piix_map_db_table[ent->driver_data]); |
c7290724 TH |
1524 | piix_init_sidpr(host); |
1525 | } | |
1da177e4 | 1526 | |
43a98f05 TH |
1527 | /* apply IOCFG bit18 quirk */ |
1528 | piix_iocfg_bit18_quirk(pdev); | |
1529 | ||
1da177e4 LT |
1530 | /* On ICH5, some BIOSen disable the interrupt using the |
1531 | * PCI_COMMAND_INTX_DISABLE bit added in PCI 2.3. | |
1532 | * On ICH6, this bit has the same effect, but only when | |
1533 | * MSI is disabled (and it is disabled, as we don't use | |
1534 | * message-signalled interrupts currently). | |
1535 | */ | |
cca3974e | 1536 | if (port_flags & PIIX_FLAG_CHECKINTR) |
a04ce0ff | 1537 | pci_intx(pdev, 1); |
1da177e4 | 1538 | |
c621b140 AC |
1539 | if (piix_check_450nx_errata(pdev)) { |
1540 | /* This writes into the master table but it does not | |
1541 | really matter for this errata as we will apply it to | |
1542 | all the PIIX devices on the board */ | |
8b09f0da TH |
1543 | host->ports[0]->mwdma_mask = 0; |
1544 | host->ports[0]->udma_mask = 0; | |
1545 | host->ports[1]->mwdma_mask = 0; | |
1546 | host->ports[1]->udma_mask = 0; | |
c621b140 | 1547 | } |
8b09f0da TH |
1548 | |
1549 | pci_set_master(pdev); | |
9363c382 | 1550 | return ata_pci_sff_activate_host(host, ata_sff_interrupt, &piix_sht); |
1da177e4 LT |
1551 | } |
1552 | ||
1da177e4 LT |
1553 | static int __init piix_init(void) |
1554 | { | |
1555 | int rc; | |
1556 | ||
b7887196 PR |
1557 | DPRINTK("pci_register_driver\n"); |
1558 | rc = pci_register_driver(&piix_pci_driver); | |
1da177e4 LT |
1559 | if (rc) |
1560 | return rc; | |
1561 | ||
1562 | in_module_init = 0; | |
1563 | ||
1564 | DPRINTK("done\n"); | |
1565 | return 0; | |
1566 | } | |
1567 | ||
1da177e4 LT |
1568 | static void __exit piix_exit(void) |
1569 | { | |
1570 | pci_unregister_driver(&piix_pci_driver); | |
1571 | } | |
1572 | ||
1573 | module_init(piix_init); | |
1574 | module_exit(piix_exit); |