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ata: Convert dev_printk(KERN_<LEVEL> to dev_<level>(
[deliverable/linux.git] / drivers / ata / libahci.c
CommitLineData
365cfa1e
AV		 1/*
2 * libahci.c - Common AHCI SATA low-level routines
3 *
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
7 *
8 * Copyright 2004-2005 Red Hat, Inc.
9 *
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
24 *
25 *
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
28 *
29 * AHCI hardware documentation:
30 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
31 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
32 *
33 */
34
35#include <linux/kernel.h>
fbaf666b 36#include <linux/gfp.h>
365cfa1e
AV		 37#include <linux/module.h>
38#include <linux/init.h>
39#include <linux/blkdev.h>
40#include <linux/delay.h>
41#include <linux/interrupt.h>
42#include <linux/dma-mapping.h>
43#include <linux/device.h>
44#include <scsi/scsi_host.h>
45#include <scsi/scsi_cmnd.h>
46#include <linux/libata.h>
47#include "ahci.h"
48
49static int ahci_skip_host_reset;
50int ahci_ignore_sss;
51EXPORT_SYMBOL_GPL(ahci_ignore_sss);
52
53module_param_named(skip_host_reset, ahci_skip_host_reset, int, 0444);
54MODULE_PARM_DESC(skip_host_reset, "skip global host reset (0=don't skip, 1=skip)");
55
56module_param_named(ignore_sss, ahci_ignore_sss, int, 0444);
57MODULE_PARM_DESC(ignore_sss, "Ignore staggered spinup flag (0=don't ignore, 1=ignore)");
58
6b7ae954
TH		 59static int ahci_set_lpm(struct ata_link *link, enum ata_lpm_policy policy,
60 unsigned hints);
365cfa1e
AV		 61static ssize_t ahci_led_show(struct ata_port *ap, char *buf);
62static ssize_t ahci_led_store(struct ata_port *ap, const char *buf,
63 size_t size);
64static ssize_t ahci_transmit_led_message(struct ata_port *ap, u32 state,
65 ssize_t size);
66
67
68
69static int ahci_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val);
70static int ahci_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val);
71static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc);
72static bool ahci_qc_fill_rtf(struct ata_queued_cmd *qc);
73static int ahci_port_start(struct ata_port *ap);
74static void ahci_port_stop(struct ata_port *ap);
75static void ahci_qc_prep(struct ata_queued_cmd *qc);
76static int ahci_pmp_qc_defer(struct ata_queued_cmd *qc);
77static void ahci_freeze(struct ata_port *ap);
78static void ahci_thaw(struct ata_port *ap);
79static void ahci_enable_fbs(struct ata_port *ap);
80static void ahci_disable_fbs(struct ata_port *ap);
81static void ahci_pmp_attach(struct ata_port *ap);
82static void ahci_pmp_detach(struct ata_port *ap);
83static int ahci_softreset(struct ata_link *link, unsigned int *class,
84 unsigned long deadline);
85static int ahci_hardreset(struct ata_link *link, unsigned int *class,
86 unsigned long deadline);
87static void ahci_postreset(struct ata_link *link, unsigned int *class);
88static void ahci_error_handler(struct ata_port *ap);
89static void ahci_post_internal_cmd(struct ata_queued_cmd *qc);
365cfa1e 90static void ahci_dev_config(struct ata_device *dev);
365cfa1e
AV		 91#ifdef CONFIG_PM
92static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg);
93#endif
94static ssize_t ahci_activity_show(struct ata_device *dev, char *buf);
95static ssize_t ahci_activity_store(struct ata_device *dev,
96 enum sw_activity val);
97static void ahci_init_sw_activity(struct ata_link *link);
98
99static ssize_t ahci_show_host_caps(struct device *dev,
100 struct device_attribute *attr, char *buf);
101static ssize_t ahci_show_host_cap2(struct device *dev,
102 struct device_attribute *attr, char *buf);
103static ssize_t ahci_show_host_version(struct device *dev,
104 struct device_attribute *attr, char *buf);
105static ssize_t ahci_show_port_cmd(struct device *dev,
106 struct device_attribute *attr, char *buf);
c0623166
HZ		 107static ssize_t ahci_read_em_buffer(struct device *dev,
108 struct device_attribute *attr, char *buf);
109static ssize_t ahci_store_em_buffer(struct device *dev,
110 struct device_attribute *attr,
111 const char *buf, size_t size);
6e5fe5b1
HR		 112static ssize_t ahci_show_em_supported(struct device *dev,
113 struct device_attribute *attr, char *buf);
365cfa1e
AV		 114
115static DEVICE_ATTR(ahci_host_caps, S_IRUGO, ahci_show_host_caps, NULL);
116static DEVICE_ATTR(ahci_host_cap2, S_IRUGO, ahci_show_host_cap2, NULL);
117static DEVICE_ATTR(ahci_host_version, S_IRUGO, ahci_show_host_version, NULL);
118static DEVICE_ATTR(ahci_port_cmd, S_IRUGO, ahci_show_port_cmd, NULL);
c0623166
HZ		 119static DEVICE_ATTR(em_buffer, S_IWUSR | S_IRUGO,
120 ahci_read_em_buffer, ahci_store_em_buffer);
6e5fe5b1 121static DEVICE_ATTR(em_message_supported, S_IRUGO, ahci_show_em_supported, NULL);
365cfa1e 122
fad16e7a 123struct device_attribute *ahci_shost_attrs[] = {
365cfa1e
AV		 124 &dev_attr_link_power_management_policy,
125 &dev_attr_em_message_type,
126 &dev_attr_em_message,
127 &dev_attr_ahci_host_caps,
128 &dev_attr_ahci_host_cap2,
129 &dev_attr_ahci_host_version,
130 &dev_attr_ahci_port_cmd,
c0623166 131 &dev_attr_em_buffer,
6e5fe5b1 132 &dev_attr_em_message_supported,
365cfa1e
AV		 133 NULL
134};
fad16e7a 135EXPORT_SYMBOL_GPL(ahci_shost_attrs);
365cfa1e 136
fad16e7a 137struct device_attribute *ahci_sdev_attrs[] = {
365cfa1e
AV		 138 &dev_attr_sw_activity,
139 &dev_attr_unload_heads,
140 NULL
141};
fad16e7a 142EXPORT_SYMBOL_GPL(ahci_sdev_attrs);
365cfa1e
AV		 143
144struct ata_port_operations ahci_ops = {
145 .inherits = &sata_pmp_port_ops,
146
147 .qc_defer = ahci_pmp_qc_defer,
148 .qc_prep = ahci_qc_prep,
149 .qc_issue = ahci_qc_issue,
150 .qc_fill_rtf = ahci_qc_fill_rtf,
151
152 .freeze = ahci_freeze,
153 .thaw = ahci_thaw,
154 .softreset = ahci_softreset,
155 .hardreset = ahci_hardreset,
156 .postreset = ahci_postreset,
157 .pmp_softreset = ahci_softreset,
158 .error_handler = ahci_error_handler,
159 .post_internal_cmd = ahci_post_internal_cmd,
160 .dev_config = ahci_dev_config,
161
162 .scr_read = ahci_scr_read,
163 .scr_write = ahci_scr_write,
164 .pmp_attach = ahci_pmp_attach,
165 .pmp_detach = ahci_pmp_detach,
166
6b7ae954 167 .set_lpm = ahci_set_lpm,
365cfa1e
AV		 168 .em_show = ahci_led_show,
169 .em_store = ahci_led_store,
170 .sw_activity_show = ahci_activity_show,
171 .sw_activity_store = ahci_activity_store,
172#ifdef CONFIG_PM
173 .port_suspend = ahci_port_suspend,
174 .port_resume = ahci_port_resume,
175#endif
176 .port_start = ahci_port_start,
177 .port_stop = ahci_port_stop,
178};
179EXPORT_SYMBOL_GPL(ahci_ops);
180
181int ahci_em_messages = 1;
182EXPORT_SYMBOL_GPL(ahci_em_messages);
183module_param(ahci_em_messages, int, 0444);
184/* add other LED protocol types when they become supported */
185MODULE_PARM_DESC(ahci_em_messages,
008dbd61 186 "AHCI Enclosure Management Message control (0 = off, 1 = on)");
365cfa1e
AV		 187
188static void ahci_enable_ahci(void __iomem *mmio)
189{
190 int i;
191 u32 tmp;
192
193 /* turn on AHCI_EN */
194 tmp = readl(mmio + HOST_CTL);
195 if (tmp & HOST_AHCI_EN)
196 return;
197
198 /* Some controllers need AHCI_EN to be written multiple times.
199 * Try a few times before giving up.
200 */
201 for (i = 0; i < 5; i++) {
202 tmp |= HOST_AHCI_EN;
203 writel(tmp, mmio + HOST_CTL);
204 tmp = readl(mmio + HOST_CTL); /* flush && sanity check */
205 if (tmp & HOST_AHCI_EN)
206 return;
207 msleep(10);
208 }
209
210 WARN_ON(1);
211}
212
213static ssize_t ahci_show_host_caps(struct device *dev,
214 struct device_attribute *attr, char *buf)
215{
216 struct Scsi_Host *shost = class_to_shost(dev);
217 struct ata_port *ap = ata_shost_to_port(shost);
218 struct ahci_host_priv *hpriv = ap->host->private_data;
219
220 return sprintf(buf, "%x\n", hpriv->cap);
221}
222
223static ssize_t ahci_show_host_cap2(struct device *dev,
224 struct device_attribute *attr, char *buf)
225{
226 struct Scsi_Host *shost = class_to_shost(dev);
227 struct ata_port *ap = ata_shost_to_port(shost);
228 struct ahci_host_priv *hpriv = ap->host->private_data;
229
230 return sprintf(buf, "%x\n", hpriv->cap2);
231}
232
233static ssize_t ahci_show_host_version(struct device *dev,
234 struct device_attribute *attr, char *buf)
235{
236 struct Scsi_Host *shost = class_to_shost(dev);
237 struct ata_port *ap = ata_shost_to_port(shost);
238 struct ahci_host_priv *hpriv = ap->host->private_data;
239 void __iomem *mmio = hpriv->mmio;
240
241 return sprintf(buf, "%x\n", readl(mmio + HOST_VERSION));
242}
243
244static ssize_t ahci_show_port_cmd(struct device *dev,
245 struct device_attribute *attr, char *buf)
246{
247 struct Scsi_Host *shost = class_to_shost(dev);
248 struct ata_port *ap = ata_shost_to_port(shost);
249 void __iomem *port_mmio = ahci_port_base(ap);
250
251 return sprintf(buf, "%x\n", readl(port_mmio + PORT_CMD));
252}
253
c0623166
HZ		 254static ssize_t ahci_read_em_buffer(struct device *dev,
255 struct device_attribute *attr, char *buf)
256{
257 struct Scsi_Host *shost = class_to_shost(dev);
258 struct ata_port *ap = ata_shost_to_port(shost);
259 struct ahci_host_priv *hpriv = ap->host->private_data;
260 void __iomem *mmio = hpriv->mmio;
261 void __iomem *em_mmio = mmio + hpriv->em_loc;
262 u32 em_ctl, msg;
263 unsigned long flags;
264 size_t count;
265 int i;
266
267 spin_lock_irqsave(ap->lock, flags);
268
269 em_ctl = readl(mmio + HOST_EM_CTL);
270 if (!(ap->flags & ATA_FLAG_EM) || em_ctl & EM_CTL_XMT ||
271 !(hpriv->em_msg_type & EM_MSG_TYPE_SGPIO)) {
272 spin_unlock_irqrestore(ap->lock, flags);
273 return -EINVAL;
274 }
275
276 if (!(em_ctl & EM_CTL_MR)) {
277 spin_unlock_irqrestore(ap->lock, flags);
278 return -EAGAIN;
279 }
280
281 if (!(em_ctl & EM_CTL_SMB))
282 em_mmio += hpriv->em_buf_sz;
283
284 count = hpriv->em_buf_sz;
285
286 /* the count should not be larger than PAGE_SIZE */
287 if (count > PAGE_SIZE) {
288 if (printk_ratelimit())
289 ata_port_printk(ap, KERN_WARNING,
290 "EM read buffer size too large: "
291 "buffer size %u, page size %lu\n",
292 hpriv->em_buf_sz, PAGE_SIZE);
293 count = PAGE_SIZE;
294 }
295
296 for (i = 0; i < count; i += 4) {
297 msg = readl(em_mmio + i);
298 buf[i] = msg & 0xff;
299 buf[i + 1] = (msg >> 8) & 0xff;
300 buf[i + 2] = (msg >> 16) & 0xff;
301 buf[i + 3] = (msg >> 24) & 0xff;
302 }
303
304 spin_unlock_irqrestore(ap->lock, flags);
305
306 return i;
307}
308
309static ssize_t ahci_store_em_buffer(struct device *dev,
310 struct device_attribute *attr,
311 const char *buf, size_t size)
312{
313 struct Scsi_Host *shost = class_to_shost(dev);
314 struct ata_port *ap = ata_shost_to_port(shost);
315 struct ahci_host_priv *hpriv = ap->host->private_data;
316 void __iomem *mmio = hpriv->mmio;
317 void __iomem *em_mmio = mmio + hpriv->em_loc;
f9ce889b 318 const unsigned char *msg_buf = buf;
c0623166
HZ		 319 u32 em_ctl, msg;
320 unsigned long flags;
321 int i;
322
323 /* check size validity */
324 if (!(ap->flags & ATA_FLAG_EM) ||
325 !(hpriv->em_msg_type & EM_MSG_TYPE_SGPIO) ||
326 size % 4 || size > hpriv->em_buf_sz)
327 return -EINVAL;
328
329 spin_lock_irqsave(ap->lock, flags);
330
331 em_ctl = readl(mmio + HOST_EM_CTL);
332 if (em_ctl & EM_CTL_TM) {
333 spin_unlock_irqrestore(ap->lock, flags);
334 return -EBUSY;
335 }
336
337 for (i = 0; i < size; i += 4) {
f9ce889b
HZ		 338 msg = msg_buf[i] | msg_buf[i + 1] << 8 |
339 msg_buf[i + 2] << 16 | msg_buf[i + 3] << 24;
c0623166
HZ		 340 writel(msg, em_mmio + i);
341 }
342
343 writel(em_ctl | EM_CTL_TM, mmio + HOST_EM_CTL);
344
345 spin_unlock_irqrestore(ap->lock, flags);
346
347 return size;
348}
349
6e5fe5b1
HR		 350static ssize_t ahci_show_em_supported(struct device *dev,
351 struct device_attribute *attr, char *buf)
352{
353 struct Scsi_Host *shost = class_to_shost(dev);
354 struct ata_port *ap = ata_shost_to_port(shost);
355 struct ahci_host_priv *hpriv = ap->host->private_data;
356 void __iomem *mmio = hpriv->mmio;
357 u32 em_ctl;
358
359 em_ctl = readl(mmio + HOST_EM_CTL);
360
361 return sprintf(buf, "%s%s%s%s\n",
362 em_ctl & EM_CTL_LED ? "led " : "",
363 em_ctl & EM_CTL_SAFTE ? "saf-te " : "",
364 em_ctl & EM_CTL_SES ? "ses-2 " : "",
365 em_ctl & EM_CTL_SGPIO ? "sgpio " : "");
366}
367
365cfa1e
AV		 368/**
369 * ahci_save_initial_config - Save and fixup initial config values
370 * @dev: target AHCI device
371 * @hpriv: host private area to store config values
372 * @force_port_map: force port map to a specified value
373 * @mask_port_map: mask out particular bits from port map
374 *
375 * Some registers containing configuration info might be setup by
376 * BIOS and might be cleared on reset. This function saves the
377 * initial values of those registers into @hpriv such that they
378 * can be restored after controller reset.
379 *
380 * If inconsistent, config values are fixed up by this function.
381 *
382 * LOCKING:
383 * None.
384 */
385void ahci_save_initial_config(struct device *dev,
386 struct ahci_host_priv *hpriv,
387 unsigned int force_port_map,
388 unsigned int mask_port_map)
389{
390 void __iomem *mmio = hpriv->mmio;
391 u32 cap, cap2, vers, port_map;
392 int i;
393
394 /* make sure AHCI mode is enabled before accessing CAP */
395 ahci_enable_ahci(mmio);
396
397 /* Values prefixed with saved_ are written back to host after
398 * reset. Values without are used for driver operation.
399 */
400 hpriv->saved_cap = cap = readl(mmio + HOST_CAP);
401 hpriv->saved_port_map = port_map = readl(mmio + HOST_PORTS_IMPL);
402
403 /* CAP2 register is only defined for AHCI 1.2 and later */
404 vers = readl(mmio + HOST_VERSION);
405 if ((vers >> 16) > 1 ||
406 ((vers >> 16) == 1 && (vers & 0xFFFF) >= 0x200))
407 hpriv->saved_cap2 = cap2 = readl(mmio + HOST_CAP2);
408 else
409 hpriv->saved_cap2 = cap2 = 0;
410
411 /* some chips have errata preventing 64bit use */
412 if ((cap & HOST_CAP_64) && (hpriv->flags & AHCI_HFLAG_32BIT_ONLY)) {
a44fec1f 413 dev_info(dev, "controller can't do 64bit DMA, forcing 32bit\n");
365cfa1e
AV		 414 cap &= ~HOST_CAP_64;
415 }
416
417 if ((cap & HOST_CAP_NCQ) && (hpriv->flags & AHCI_HFLAG_NO_NCQ)) {
a44fec1f 418 dev_info(dev, "controller can't do NCQ, turning off CAP_NCQ\n");
365cfa1e
AV		 419 cap &= ~HOST_CAP_NCQ;
420 }
421
422 if (!(cap & HOST_CAP_NCQ) && (hpriv->flags & AHCI_HFLAG_YES_NCQ)) {
a44fec1f 423 dev_info(dev, "controller can do NCQ, turning on CAP_NCQ\n");
365cfa1e
AV		 424 cap |= HOST_CAP_NCQ;
425 }
426
427 if ((cap & HOST_CAP_PMP) && (hpriv->flags & AHCI_HFLAG_NO_PMP)) {
a44fec1f 428 dev_info(dev, "controller can't do PMP, turning off CAP_PMP\n");
365cfa1e
AV		 429 cap &= ~HOST_CAP_PMP;
430 }
431
432 if ((cap & HOST_CAP_SNTF) && (hpriv->flags & AHCI_HFLAG_NO_SNTF)) {
a44fec1f
JP		 433 dev_info(dev,
434 "controller can't do SNTF, turning off CAP_SNTF\n");
365cfa1e
AV		 435 cap &= ~HOST_CAP_SNTF;
436 }
437
5f173107 438 if (!(cap & HOST_CAP_FBS) && (hpriv->flags & AHCI_HFLAG_YES_FBS)) {
a44fec1f 439 dev_info(dev, "controller can do FBS, turning on CAP_FBS\n");
5f173107
TH		 440 cap |= HOST_CAP_FBS;
441 }
442
365cfa1e 443 if (force_port_map && port_map != force_port_map) {
a44fec1f
JP		 444 dev_info(dev, "forcing port_map 0x%x -> 0x%x\n",
445 port_map, force_port_map);
365cfa1e
AV		 446 port_map = force_port_map;
447 }
448
449 if (mask_port_map) {
a44fec1f
JP		 450 dev_warn(dev, "masking port_map 0x%x -> 0x%x\n",
451 port_map,
452 port_map & mask_port_map);
365cfa1e
AV		 453 port_map &= mask_port_map;
454 }
455
456 /* cross check port_map and cap.n_ports */
457 if (port_map) {
458 int map_ports = 0;
459
460 for (i = 0; i < AHCI_MAX_PORTS; i++)
461 if (port_map & (1 << i))
462 map_ports++;
463
464 /* If PI has more ports than n_ports, whine, clear
465 * port_map and let it be generated from n_ports.
466 */
467 if (map_ports > ahci_nr_ports(cap)) {
a44fec1f
JP		 468 dev_warn(dev,
469 "implemented port map (0x%x) contains more ports than nr_ports (%u), using nr_ports\n",
470 port_map, ahci_nr_ports(cap));
365cfa1e
AV		 471 port_map = 0;
472 }
473 }
474
475 /* fabricate port_map from cap.nr_ports */
476 if (!port_map) {
477 port_map = (1 << ahci_nr_ports(cap)) - 1;
a44fec1f 478 dev_warn(dev, "forcing PORTS_IMPL to 0x%x\n", port_map);
365cfa1e
AV		 479
480 /* write the fixed up value to the PI register */
481 hpriv->saved_port_map = port_map;
482 }
483
484 /* record values to use during operation */
485 hpriv->cap = cap;
486 hpriv->cap2 = cap2;
487 hpriv->port_map = port_map;
488}
489EXPORT_SYMBOL_GPL(ahci_save_initial_config);
490
491/**
492 * ahci_restore_initial_config - Restore initial config
493 * @host: target ATA host
494 *
495 * Restore initial config stored by ahci_save_initial_config().
496 *
497 * LOCKING:
498 * None.
499 */
500static void ahci_restore_initial_config(struct ata_host *host)
501{
502 struct ahci_host_priv *hpriv = host->private_data;
503 void __iomem *mmio = hpriv->mmio;
504
505 writel(hpriv->saved_cap, mmio + HOST_CAP);
506 if (hpriv->saved_cap2)
507 writel(hpriv->saved_cap2, mmio + HOST_CAP2);
508 writel(hpriv->saved_port_map, mmio + HOST_PORTS_IMPL);
509 (void) readl(mmio + HOST_PORTS_IMPL); /* flush */
510}
511
512static unsigned ahci_scr_offset(struct ata_port *ap, unsigned int sc_reg)
513{
514 static const int offset[] = {
515 [SCR_STATUS] = PORT_SCR_STAT,
516 [SCR_CONTROL] = PORT_SCR_CTL,
517 [SCR_ERROR] = PORT_SCR_ERR,
518 [SCR_ACTIVE] = PORT_SCR_ACT,
519 [SCR_NOTIFICATION] = PORT_SCR_NTF,
520 };
521 struct ahci_host_priv *hpriv = ap->host->private_data;
522
523 if (sc_reg < ARRAY_SIZE(offset) &&
524 (sc_reg != SCR_NOTIFICATION || (hpriv->cap & HOST_CAP_SNTF)))
525 return offset[sc_reg];
526 return 0;
527}
528
529static int ahci_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val)
530{
531 void __iomem *port_mmio = ahci_port_base(link->ap);
532 int offset = ahci_scr_offset(link->ap, sc_reg);
533
534 if (offset) {
535 *val = readl(port_mmio + offset);
536 return 0;
537 }
538 return -EINVAL;
539}
540
541static int ahci_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val)
542{
543 void __iomem *port_mmio = ahci_port_base(link->ap);
544 int offset = ahci_scr_offset(link->ap, sc_reg);
545
546 if (offset) {
547 writel(val, port_mmio + offset);
548 return 0;
549 }
550 return -EINVAL;
551}
552
553void ahci_start_engine(struct ata_port *ap)
554{
555 void __iomem *port_mmio = ahci_port_base(ap);
556 u32 tmp;
557
558 /* start DMA */
559 tmp = readl(port_mmio + PORT_CMD);
560 tmp |= PORT_CMD_START;
561 writel(tmp, port_mmio + PORT_CMD);
562 readl(port_mmio + PORT_CMD); /* flush */
563}
564EXPORT_SYMBOL_GPL(ahci_start_engine);
565
566int ahci_stop_engine(struct ata_port *ap)
567{
568 void __iomem *port_mmio = ahci_port_base(ap);
569 u32 tmp;
570
571 tmp = readl(port_mmio + PORT_CMD);
572
573 /* check if the HBA is idle */
574 if ((tmp & (PORT_CMD_START | PORT_CMD_LIST_ON)) == 0)
575 return 0;
576
577 /* setting HBA to idle */
578 tmp &= ~PORT_CMD_START;
579 writel(tmp, port_mmio + PORT_CMD);
580
581 /* wait for engine to stop. This could be as long as 500 msec */
97750ceb 582 tmp = ata_wait_register(ap, port_mmio + PORT_CMD,
365cfa1e
AV		 583 PORT_CMD_LIST_ON, PORT_CMD_LIST_ON, 1, 500);
584 if (tmp & PORT_CMD_LIST_ON)
585 return -EIO;
586
587 return 0;
588}
589EXPORT_SYMBOL_GPL(ahci_stop_engine);
590
591static void ahci_start_fis_rx(struct ata_port *ap)
592{
593 void __iomem *port_mmio = ahci_port_base(ap);
594 struct ahci_host_priv *hpriv = ap->host->private_data;
595 struct ahci_port_priv *pp = ap->private_data;
596 u32 tmp;
597
598 /* set FIS registers */
599 if (hpriv->cap & HOST_CAP_64)
600 writel((pp->cmd_slot_dma >> 16) >> 16,
601 port_mmio + PORT_LST_ADDR_HI);
602 writel(pp->cmd_slot_dma & 0xffffffff, port_mmio + PORT_LST_ADDR);
603
604 if (hpriv->cap & HOST_CAP_64)
605 writel((pp->rx_fis_dma >> 16) >> 16,
606 port_mmio + PORT_FIS_ADDR_HI);
607 writel(pp->rx_fis_dma & 0xffffffff, port_mmio + PORT_FIS_ADDR);
608
609 /* enable FIS reception */
610 tmp = readl(port_mmio + PORT_CMD);
611 tmp |= PORT_CMD_FIS_RX;
612 writel(tmp, port_mmio + PORT_CMD);
613
614 /* flush */
615 readl(port_mmio + PORT_CMD);
616}
617
618static int ahci_stop_fis_rx(struct ata_port *ap)
619{
620 void __iomem *port_mmio = ahci_port_base(ap);
621 u32 tmp;
622
623 /* disable FIS reception */
624 tmp = readl(port_mmio + PORT_CMD);
625 tmp &= ~PORT_CMD_FIS_RX;
626 writel(tmp, port_mmio + PORT_CMD);
627
628 /* wait for completion, spec says 500ms, give it 1000 */
97750ceb 629 tmp = ata_wait_register(ap, port_mmio + PORT_CMD, PORT_CMD_FIS_ON,
365cfa1e
AV		 630 PORT_CMD_FIS_ON, 10, 1000);
631 if (tmp & PORT_CMD_FIS_ON)
632 return -EBUSY;
633
634 return 0;
635}
636
637static void ahci_power_up(struct ata_port *ap)
638{
639 struct ahci_host_priv *hpriv = ap->host->private_data;
640 void __iomem *port_mmio = ahci_port_base(ap);
641 u32 cmd;
642
643 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
644
645 /* spin up device */
646 if (hpriv->cap & HOST_CAP_SSS) {
647 cmd |= PORT_CMD_SPIN_UP;
648 writel(cmd, port_mmio + PORT_CMD);
649 }
650
651 /* wake up link */
652 writel(cmd | PORT_CMD_ICC_ACTIVE, port_mmio + PORT_CMD);
653}
654
6b7ae954
TH		 655static int ahci_set_lpm(struct ata_link *link, enum ata_lpm_policy policy,
656 unsigned int hints)
365cfa1e 657{
6b7ae954 658 struct ata_port *ap = link->ap;
365cfa1e 659 struct ahci_host_priv *hpriv = ap->host->private_data;
365cfa1e 660 struct ahci_port_priv *pp = ap->private_data;
365cfa1e 661 void __iomem *port_mmio = ahci_port_base(ap);
365cfa1e 662
6b7ae954 663 if (policy != ATA_LPM_MAX_POWER) {
365cfa1e 664 /*
6b7ae954
TH		 665 * Disable interrupts on Phy Ready. This keeps us from
666 * getting woken up due to spurious phy ready
667 * interrupts.
365cfa1e 668 */
6b7ae954
TH		 669 pp->intr_mask &= ~PORT_IRQ_PHYRDY;
670 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
671
672 sata_link_scr_lpm(link, policy, false);
365cfa1e
AV		 673 }
674
6b7ae954
TH		 675 if (hpriv->cap & HOST_CAP_ALPM) {
676 u32 cmd = readl(port_mmio + PORT_CMD);
365cfa1e 677
6b7ae954
TH		 678 if (policy == ATA_LPM_MAX_POWER || !(hints & ATA_LPM_HIPM)) {
679 cmd &= ~(PORT_CMD_ASP | PORT_CMD_ALPE);
680 cmd |= PORT_CMD_ICC_ACTIVE;
365cfa1e 681
6b7ae954
TH		 682 writel(cmd, port_mmio + PORT_CMD);
683 readl(port_mmio + PORT_CMD);
365cfa1e 684
6b7ae954 685 /* wait 10ms to be sure we've come out of LPM state */
97750ceb 686 ata_msleep(ap, 10);
6b7ae954
TH		 687 } else {
688 cmd |= PORT_CMD_ALPE;
689 if (policy == ATA_LPM_MIN_POWER)
690 cmd |= PORT_CMD_ASP;
365cfa1e 691
6b7ae954
TH		 692 /* write out new cmd value */
693 writel(cmd, port_mmio + PORT_CMD);
694 }
695 }
365cfa1e 696
6b7ae954
TH		 697 if (policy == ATA_LPM_MAX_POWER) {
698 sata_link_scr_lpm(link, policy, false);
699
700 /* turn PHYRDY IRQ back on */
701 pp->intr_mask |= PORT_IRQ_PHYRDY;
702 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
703 }
365cfa1e 704
365cfa1e
AV		 705 return 0;
706}
707
708#ifdef CONFIG_PM
709static void ahci_power_down(struct ata_port *ap)
710{
711 struct ahci_host_priv *hpriv = ap->host->private_data;
712 void __iomem *port_mmio = ahci_port_base(ap);
713 u32 cmd, scontrol;
714
715 if (!(hpriv->cap & HOST_CAP_SSS))
716 return;
717
718 /* put device into listen mode, first set PxSCTL.DET to 0 */
719 scontrol = readl(port_mmio + PORT_SCR_CTL);
720 scontrol &= ~0xf;
721 writel(scontrol, port_mmio + PORT_SCR_CTL);
722
723 /* then set PxCMD.SUD to 0 */
724 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
725 cmd &= ~PORT_CMD_SPIN_UP;
726 writel(cmd, port_mmio + PORT_CMD);
727}
728#endif
729
730static void ahci_start_port(struct ata_port *ap)
731{
732 struct ahci_port_priv *pp = ap->private_data;
733 struct ata_link *link;
734 struct ahci_em_priv *emp;
735 ssize_t rc;
736 int i;
737
738 /* enable FIS reception */
739 ahci_start_fis_rx(ap);
740
741 /* enable DMA */
742 ahci_start_engine(ap);
743
744 /* turn on LEDs */
745 if (ap->flags & ATA_FLAG_EM) {
746 ata_for_each_link(link, ap, EDGE) {
747 emp = &pp->em_priv[link->pmp];
748
749 /* EM Transmit bit maybe busy during init */
750 for (i = 0; i < EM_MAX_RETRY; i++) {
751 rc = ahci_transmit_led_message(ap,
752 emp->led_state,
753 4);
754 if (rc == -EBUSY)
97750ceb 755 ata_msleep(ap, 1);
365cfa1e
AV		 756 else
757 break;
758 }
759 }
760 }
761
762 if (ap->flags & ATA_FLAG_SW_ACTIVITY)
763 ata_for_each_link(link, ap, EDGE)
764 ahci_init_sw_activity(link);
765
766}
767
768static int ahci_deinit_port(struct ata_port *ap, const char **emsg)
769{
770 int rc;
771
772 /* disable DMA */
773 rc = ahci_stop_engine(ap);
774 if (rc) {
775 *emsg = "failed to stop engine";
776 return rc;
777 }
778
779 /* disable FIS reception */
780 rc = ahci_stop_fis_rx(ap);
781 if (rc) {
782 *emsg = "failed stop FIS RX";
783 return rc;
784 }
785
786 return 0;
787}
788
789int ahci_reset_controller(struct ata_host *host)
790{
791 struct ahci_host_priv *hpriv = host->private_data;
792 void __iomem *mmio = hpriv->mmio;
793 u32 tmp;
794
795 /* we must be in AHCI mode, before using anything
796 * AHCI-specific, such as HOST_RESET.
797 */
798 ahci_enable_ahci(mmio);
799
800 /* global controller reset */
801 if (!ahci_skip_host_reset) {
802 tmp = readl(mmio + HOST_CTL);
803 if ((tmp & HOST_RESET) == 0) {
804 writel(tmp | HOST_RESET, mmio + HOST_CTL);
805 readl(mmio + HOST_CTL); /* flush */
806 }
807
808 /*
809 * to perform host reset, OS should set HOST_RESET
810 * and poll until this bit is read to be "0".
811 * reset must complete within 1 second, or
812 * the hardware should be considered fried.
813 */
97750ceb 814 tmp = ata_wait_register(NULL, mmio + HOST_CTL, HOST_RESET,
365cfa1e
AV		 815 HOST_RESET, 10, 1000);
816
817 if (tmp & HOST_RESET) {
a44fec1f
JP		 818 dev_err(host->dev, "controller reset failed (0x%x)\n",
819 tmp);
365cfa1e
AV		 820 return -EIO;
821 }
822
823 /* turn on AHCI mode */
824 ahci_enable_ahci(mmio);
825
826 /* Some registers might be cleared on reset. Restore
827 * initial values.
828 */
829 ahci_restore_initial_config(host);
830 } else
a44fec1f 831 dev_info(host->dev, "skipping global host reset\n");
365cfa1e
AV		 832
833 return 0;
834}
835EXPORT_SYMBOL_GPL(ahci_reset_controller);
836
837static void ahci_sw_activity(struct ata_link *link)
838{
839 struct ata_port *ap = link->ap;
840 struct ahci_port_priv *pp = ap->private_data;
841 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
842
843 if (!(link->flags & ATA_LFLAG_SW_ACTIVITY))
844 return;
845
846 emp->activity++;
847 if (!timer_pending(&emp->timer))
848 mod_timer(&emp->timer, jiffies + msecs_to_jiffies(10));
849}
850
851static void ahci_sw_activity_blink(unsigned long arg)
852{
853 struct ata_link *link = (struct ata_link *)arg;
854 struct ata_port *ap = link->ap;
855 struct ahci_port_priv *pp = ap->private_data;
856 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
857 unsigned long led_message = emp->led_state;
858 u32 activity_led_state;
859 unsigned long flags;
860
861 led_message &= EM_MSG_LED_VALUE;
862 led_message |= ap->port_no | (link->pmp << 8);
863
864 /* check to see if we've had activity. If so,
865 * toggle state of LED and reset timer. If not,
866 * turn LED to desired idle state.
867 */
868 spin_lock_irqsave(ap->lock, flags);
869 if (emp->saved_activity != emp->activity) {
870 emp->saved_activity = emp->activity;
871 /* get the current LED state */
872 activity_led_state = led_message & EM_MSG_LED_VALUE_ON;
873
874 if (activity_led_state)
875 activity_led_state = 0;
876 else
877 activity_led_state = 1;
878
879 /* clear old state */
880 led_message &= ~EM_MSG_LED_VALUE_ACTIVITY;
881
882 /* toggle state */
883 led_message |= (activity_led_state << 16);
884 mod_timer(&emp->timer, jiffies + msecs_to_jiffies(100));
885 } else {
886 /* switch to idle */
887 led_message &= ~EM_MSG_LED_VALUE_ACTIVITY;
888 if (emp->blink_policy == BLINK_OFF)
889 led_message |= (1 << 16);
890 }
891 spin_unlock_irqrestore(ap->lock, flags);
892 ahci_transmit_led_message(ap, led_message, 4);
893}
894
895static void ahci_init_sw_activity(struct ata_link *link)
896{
897 struct ata_port *ap = link->ap;
898 struct ahci_port_priv *pp = ap->private_data;
899 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
900
901 /* init activity stats, setup timer */
902 emp->saved_activity = emp->activity = 0;
903 setup_timer(&emp->timer, ahci_sw_activity_blink, (unsigned long)link);
904
905 /* check our blink policy and set flag for link if it's enabled */
906 if (emp->blink_policy)
907 link->flags |= ATA_LFLAG_SW_ACTIVITY;
908}
909
910int ahci_reset_em(struct ata_host *host)
911{
912 struct ahci_host_priv *hpriv = host->private_data;
913 void __iomem *mmio = hpriv->mmio;
914 u32 em_ctl;
915
916 em_ctl = readl(mmio + HOST_EM_CTL);
917 if ((em_ctl & EM_CTL_TM) || (em_ctl & EM_CTL_RST))
918 return -EINVAL;
919
920 writel(em_ctl | EM_CTL_RST, mmio + HOST_EM_CTL);
921 return 0;
922}
923EXPORT_SYMBOL_GPL(ahci_reset_em);
924
925static ssize_t ahci_transmit_led_message(struct ata_port *ap, u32 state,
926 ssize_t size)
927{
928 struct ahci_host_priv *hpriv = ap->host->private_data;
929 struct ahci_port_priv *pp = ap->private_data;
930 void __iomem *mmio = hpriv->mmio;
931 u32 em_ctl;
932 u32 message[] = {0, 0};
933 unsigned long flags;
934 int pmp;
935 struct ahci_em_priv *emp;
936
937 /* get the slot number from the message */
938 pmp = (state & EM_MSG_LED_PMP_SLOT) >> 8;
939 if (pmp < EM_MAX_SLOTS)
940 emp = &pp->em_priv[pmp];
941 else
942 return -EINVAL;
943
944 spin_lock_irqsave(ap->lock, flags);
945
946 /*
947 * if we are still busy transmitting a previous message,
948 * do not allow
949 */
950 em_ctl = readl(mmio + HOST_EM_CTL);
951 if (em_ctl & EM_CTL_TM) {
952 spin_unlock_irqrestore(ap->lock, flags);
953 return -EBUSY;
954 }
955
008dbd61
HZ		 956 if (hpriv->em_msg_type & EM_MSG_TYPE_LED) {
957 /*
958 * create message header - this is all zero except for
959 * the message size, which is 4 bytes.
960 */
961 message[0] |= (4 << 8);
365cfa1e 962
008dbd61
HZ		 963 /* ignore 0:4 of byte zero, fill in port info yourself */
964 message[1] = ((state & ~EM_MSG_LED_HBA_PORT) | ap->port_no);
365cfa1e 965
008dbd61
HZ		 966 /* write message to EM_LOC */
967 writel(message[0], mmio + hpriv->em_loc);
968 writel(message[1], mmio + hpriv->em_loc+4);
969
970 /*
971 * tell hardware to transmit the message
972 */
973 writel(em_ctl | EM_CTL_TM, mmio + HOST_EM_CTL);
974 }
365cfa1e
AV		 975
976 /* save off new led state for port/slot */
977 emp->led_state = state;
978
365cfa1e
AV		 979 spin_unlock_irqrestore(ap->lock, flags);
980 return size;
981}
982
983static ssize_t ahci_led_show(struct ata_port *ap, char *buf)
984{
985 struct ahci_port_priv *pp = ap->private_data;
986 struct ata_link *link;
987 struct ahci_em_priv *emp;
988 int rc = 0;
989
990 ata_for_each_link(link, ap, EDGE) {
991 emp = &pp->em_priv[link->pmp];
992 rc += sprintf(buf, "%lx\n", emp->led_state);
993 }
994 return rc;
995}
996
997static ssize_t ahci_led_store(struct ata_port *ap, const char *buf,
998 size_t size)
999{
1000 int state;
1001 int pmp;
1002 struct ahci_port_priv *pp = ap->private_data;
1003 struct ahci_em_priv *emp;
1004
1005 state = simple_strtoul(buf, NULL, 0);
1006
1007 /* get the slot number from the message */
1008 pmp = (state & EM_MSG_LED_PMP_SLOT) >> 8;
1009 if (pmp < EM_MAX_SLOTS)
1010 emp = &pp->em_priv[pmp];
1011 else
1012 return -EINVAL;
1013
1014 /* mask off the activity bits if we are in sw_activity
1015 * mode, user should turn off sw_activity before setting
1016 * activity led through em_message
1017 */
1018 if (emp->blink_policy)
1019 state &= ~EM_MSG_LED_VALUE_ACTIVITY;
1020
1021 return ahci_transmit_led_message(ap, state, size);
1022}
1023
1024static ssize_t ahci_activity_store(struct ata_device *dev, enum sw_activity val)
1025{
1026 struct ata_link *link = dev->link;
1027 struct ata_port *ap = link->ap;
1028 struct ahci_port_priv *pp = ap->private_data;
1029 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
1030 u32 port_led_state = emp->led_state;
1031
1032 /* save the desired Activity LED behavior */
1033 if (val == OFF) {
1034 /* clear LFLAG */
1035 link->flags &= ~(ATA_LFLAG_SW_ACTIVITY);
1036
1037 /* set the LED to OFF */
1038 port_led_state &= EM_MSG_LED_VALUE_OFF;
1039 port_led_state |= (ap->port_no | (link->pmp << 8));
1040 ahci_transmit_led_message(ap, port_led_state, 4);
1041 } else {
1042 link->flags |= ATA_LFLAG_SW_ACTIVITY;
1043 if (val == BLINK_OFF) {
1044 /* set LED to ON for idle */
1045 port_led_state &= EM_MSG_LED_VALUE_OFF;
1046 port_led_state |= (ap->port_no | (link->pmp << 8));
1047 port_led_state |= EM_MSG_LED_VALUE_ON; /* check this */
1048 ahci_transmit_led_message(ap, port_led_state, 4);
1049 }
1050 }
1051 emp->blink_policy = val;
1052 return 0;
1053}
1054
1055static ssize_t ahci_activity_show(struct ata_device *dev, char *buf)
1056{
1057 struct ata_link *link = dev->link;
1058 struct ata_port *ap = link->ap;
1059 struct ahci_port_priv *pp = ap->private_data;
1060 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
1061
1062 /* display the saved value of activity behavior for this
1063 * disk.
1064 */
1065 return sprintf(buf, "%d\n", emp->blink_policy);
1066}
1067
1068static void ahci_port_init(struct device *dev, struct ata_port *ap,
1069 int port_no, void __iomem *mmio,
1070 void __iomem *port_mmio)
1071{
1072 const char *emsg = NULL;
1073 int rc;
1074 u32 tmp;
1075
1076 /* make sure port is not active */
1077 rc = ahci_deinit_port(ap, &emsg);
1078 if (rc)
1079 dev_warn(dev, "%s (%d)\n", emsg, rc);
1080
1081 /* clear SError */
1082 tmp = readl(port_mmio + PORT_SCR_ERR);
1083 VPRINTK("PORT_SCR_ERR 0x%x\n", tmp);
1084 writel(tmp, port_mmio + PORT_SCR_ERR);
1085
1086 /* clear port IRQ */
1087 tmp = readl(port_mmio + PORT_IRQ_STAT);
1088 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
1089 if (tmp)
1090 writel(tmp, port_mmio + PORT_IRQ_STAT);
1091
1092 writel(1 << port_no, mmio + HOST_IRQ_STAT);
1093}
1094
1095void ahci_init_controller(struct ata_host *host)
1096{
1097 struct ahci_host_priv *hpriv = host->private_data;
1098 void __iomem *mmio = hpriv->mmio;
1099 int i;
1100 void __iomem *port_mmio;
1101 u32 tmp;
1102
1103 for (i = 0; i < host->n_ports; i++) {
1104 struct ata_port *ap = host->ports[i];
1105
1106 port_mmio = ahci_port_base(ap);
1107 if (ata_port_is_dummy(ap))
1108 continue;
1109
1110 ahci_port_init(host->dev, ap, i, mmio, port_mmio);
1111 }
1112
1113 tmp = readl(mmio + HOST_CTL);
1114 VPRINTK("HOST_CTL 0x%x\n", tmp);
1115 writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL);
1116 tmp = readl(mmio + HOST_CTL);
1117 VPRINTK("HOST_CTL 0x%x\n", tmp);
1118}
1119EXPORT_SYMBOL_GPL(ahci_init_controller);
1120
1121static void ahci_dev_config(struct ata_device *dev)
1122{
1123 struct ahci_host_priv *hpriv = dev->link->ap->host->private_data;
1124
1125 if (hpriv->flags & AHCI_HFLAG_SECT255) {
1126 dev->max_sectors = 255;
1127 ata_dev_printk(dev, KERN_INFO,
1128 "SB600 AHCI: limiting to 255 sectors per cmd\n");
1129 }
1130}
1131
1132static unsigned int ahci_dev_classify(struct ata_port *ap)
1133{
1134 void __iomem *port_mmio = ahci_port_base(ap);
1135 struct ata_taskfile tf;
1136 u32 tmp;
1137
1138 tmp = readl(port_mmio + PORT_SIG);
1139 tf.lbah = (tmp >> 24) & 0xff;
1140 tf.lbam = (tmp >> 16) & 0xff;
1141 tf.lbal = (tmp >> 8) & 0xff;
1142 tf.nsect = (tmp) & 0xff;
1143
1144 return ata_dev_classify(&tf);
1145}
1146
02cdfcf0
DM		 1147void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag,
1148 u32 opts)
365cfa1e
AV		 1149{
1150 dma_addr_t cmd_tbl_dma;
1151
1152 cmd_tbl_dma = pp->cmd_tbl_dma + tag * AHCI_CMD_TBL_SZ;
1153
1154 pp->cmd_slot[tag].opts = cpu_to_le32(opts);
1155 pp->cmd_slot[tag].status = 0;
1156 pp->cmd_slot[tag].tbl_addr = cpu_to_le32(cmd_tbl_dma & 0xffffffff);
1157 pp->cmd_slot[tag].tbl_addr_hi = cpu_to_le32((cmd_tbl_dma >> 16) >> 16);
1158}
02cdfcf0 1159EXPORT_SYMBOL_GPL(ahci_fill_cmd_slot);
365cfa1e
AV		 1160
1161int ahci_kick_engine(struct ata_port *ap)
1162{
1163 void __iomem *port_mmio = ahci_port_base(ap);
1164 struct ahci_host_priv *hpriv = ap->host->private_data;
1165 u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF;
1166 u32 tmp;
1167 int busy, rc;
1168
1169 /* stop engine */
1170 rc = ahci_stop_engine(ap);
1171 if (rc)
1172 goto out_restart;
1173
1174 /* need to do CLO?
1175 * always do CLO if PMP is attached (AHCI-1.3 9.2)
1176 */
1177 busy = status & (ATA_BUSY | ATA_DRQ);
1178 if (!busy && !sata_pmp_attached(ap)) {
1179 rc = 0;
1180 goto out_restart;
1181 }
1182
1183 if (!(hpriv->cap & HOST_CAP_CLO)) {
1184 rc = -EOPNOTSUPP;
1185 goto out_restart;
1186 }
1187
1188 /* perform CLO */
1189 tmp = readl(port_mmio + PORT_CMD);
1190 tmp |= PORT_CMD_CLO;
1191 writel(tmp, port_mmio + PORT_CMD);
1192
1193 rc = 0;
97750ceb 1194 tmp = ata_wait_register(ap, port_mmio + PORT_CMD,
365cfa1e
AV		 1195 PORT_CMD_CLO, PORT_CMD_CLO, 1, 500);
1196 if (tmp & PORT_CMD_CLO)
1197 rc = -EIO;
1198
1199 /* restart engine */
1200 out_restart:
1201 ahci_start_engine(ap);
1202 return rc;
1203}
1204EXPORT_SYMBOL_GPL(ahci_kick_engine);
1205
1206static int ahci_exec_polled_cmd(struct ata_port *ap, int pmp,
1207 struct ata_taskfile *tf, int is_cmd, u16 flags,
1208 unsigned long timeout_msec)
1209{
1210 const u32 cmd_fis_len = 5; /* five dwords */
1211 struct ahci_port_priv *pp = ap->private_data;
1212 void __iomem *port_mmio = ahci_port_base(ap);
1213 u8 *fis = pp->cmd_tbl;
1214 u32 tmp;
1215
1216 /* prep the command */
1217 ata_tf_to_fis(tf, pmp, is_cmd, fis);
1218 ahci_fill_cmd_slot(pp, 0, cmd_fis_len | flags | (pmp << 12));
1219
1220 /* issue & wait */
1221 writel(1, port_mmio + PORT_CMD_ISSUE);
1222
1223 if (timeout_msec) {
97750ceb
TH		 1224 tmp = ata_wait_register(ap, port_mmio + PORT_CMD_ISSUE,
1225 0x1, 0x1, 1, timeout_msec);
365cfa1e
AV		 1226 if (tmp & 0x1) {
1227 ahci_kick_engine(ap);
1228 return -EBUSY;
1229 }
1230 } else
1231 readl(port_mmio + PORT_CMD_ISSUE); /* flush */
1232
1233 return 0;
1234}
1235
1236int ahci_do_softreset(struct ata_link *link, unsigned int *class,
1237 int pmp, unsigned long deadline,
1238 int (*check_ready)(struct ata_link *link))
1239{
1240 struct ata_port *ap = link->ap;
1241 struct ahci_host_priv *hpriv = ap->host->private_data;
1242 const char *reason = NULL;
1243 unsigned long now, msecs;
1244 struct ata_taskfile tf;
1245 int rc;
1246
1247 DPRINTK("ENTER\n");
1248
1249 /* prepare for SRST (AHCI-1.1 10.4.1) */
1250 rc = ahci_kick_engine(ap);
1251 if (rc && rc != -EOPNOTSUPP)
1252 ata_link_printk(link, KERN_WARNING,
1253 "failed to reset engine (errno=%d)\n", rc);
1254
1255 ata_tf_init(link->device, &tf);
1256
1257 /* issue the first D2H Register FIS */
1258 msecs = 0;
1259 now = jiffies;
f1f5a807 1260 if (time_after(deadline, now))
365cfa1e
AV		 1261 msecs = jiffies_to_msecs(deadline - now);
1262
1263 tf.ctl |= ATA_SRST;
1264 if (ahci_exec_polled_cmd(ap, pmp, &tf, 0,
1265 AHCI_CMD_RESET | AHCI_CMD_CLR_BUSY, msecs)) {
1266 rc = -EIO;
1267 reason = "1st FIS failed";
1268 goto fail;
1269 }
1270
1271 /* spec says at least 5us, but be generous and sleep for 1ms */
97750ceb 1272 ata_msleep(ap, 1);
365cfa1e
AV		 1273
1274 /* issue the second D2H Register FIS */
1275 tf.ctl &= ~ATA_SRST;
1276 ahci_exec_polled_cmd(ap, pmp, &tf, 0, 0, 0);
1277
1278 /* wait for link to become ready */
1279 rc = ata_wait_after_reset(link, deadline, check_ready);
1280 if (rc == -EBUSY && hpriv->flags & AHCI_HFLAG_SRST_TOUT_IS_OFFLINE) {
1281 /*
1282 * Workaround for cases where link online status can't
1283 * be trusted. Treat device readiness timeout as link
1284 * offline.
1285 */
1286 ata_link_printk(link, KERN_INFO,
1287 "device not ready, treating as offline\n");
1288 *class = ATA_DEV_NONE;
1289 } else if (rc) {
1290 /* link occupied, -ENODEV too is an error */
1291 reason = "device not ready";
1292 goto fail;
1293 } else
1294 *class = ahci_dev_classify(ap);
1295
1296 DPRINTK("EXIT, class=%u\n", *class);
1297 return 0;
1298
1299 fail:
1300 ata_link_printk(link, KERN_ERR, "softreset failed (%s)\n", reason);
1301 return rc;
1302}
1303
1304int ahci_check_ready(struct ata_link *link)
1305{
1306 void __iomem *port_mmio = ahci_port_base(link->ap);
1307 u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF;
1308
1309 return ata_check_ready(status);
1310}
1311EXPORT_SYMBOL_GPL(ahci_check_ready);
1312
1313static int ahci_softreset(struct ata_link *link, unsigned int *class,
1314 unsigned long deadline)
1315{
1316 int pmp = sata_srst_pmp(link);
1317
1318 DPRINTK("ENTER\n");
1319
1320 return ahci_do_softreset(link, class, pmp, deadline, ahci_check_ready);
1321}
1322EXPORT_SYMBOL_GPL(ahci_do_softreset);
1323
1324static int ahci_hardreset(struct ata_link *link, unsigned int *class,
1325 unsigned long deadline)
1326{
1327 const unsigned long *timing = sata_ehc_deb_timing(&link->eh_context);
1328 struct ata_port *ap = link->ap;
1329 struct ahci_port_priv *pp = ap->private_data;
1330 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
1331 struct ata_taskfile tf;
1332 bool online;
1333 int rc;
1334
1335 DPRINTK("ENTER\n");
1336
1337 ahci_stop_engine(ap);
1338
1339 /* clear D2H reception area to properly wait for D2H FIS */
1340 ata_tf_init(link->device, &tf);
1341 tf.command = 0x80;
1342 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
1343
1344 rc = sata_link_hardreset(link, timing, deadline, &online,
1345 ahci_check_ready);
1346
1347 ahci_start_engine(ap);
1348
1349 if (online)
1350 *class = ahci_dev_classify(ap);
1351
1352 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
1353 return rc;
1354}
1355
1356static void ahci_postreset(struct ata_link *link, unsigned int *class)
1357{
1358 struct ata_port *ap = link->ap;
1359 void __iomem *port_mmio = ahci_port_base(ap);
1360 u32 new_tmp, tmp;
1361
1362 ata_std_postreset(link, class);
1363
1364 /* Make sure port's ATAPI bit is set appropriately */
1365 new_tmp = tmp = readl(port_mmio + PORT_CMD);
1366 if (*class == ATA_DEV_ATAPI)
1367 new_tmp |= PORT_CMD_ATAPI;
1368 else
1369 new_tmp &= ~PORT_CMD_ATAPI;
1370 if (new_tmp != tmp) {
1371 writel(new_tmp, port_mmio + PORT_CMD);
1372 readl(port_mmio + PORT_CMD); /* flush */
1373 }
1374}
1375
1376static unsigned int ahci_fill_sg(struct ata_queued_cmd *qc, void *cmd_tbl)
1377{
1378 struct scatterlist *sg;
1379 struct ahci_sg *ahci_sg = cmd_tbl + AHCI_CMD_TBL_HDR_SZ;
1380 unsigned int si;
1381
1382 VPRINTK("ENTER\n");
1383
1384 /*
1385 * Next, the S/G list.
1386 */
1387 for_each_sg(qc->sg, sg, qc->n_elem, si) {
1388 dma_addr_t addr = sg_dma_address(sg);
1389 u32 sg_len = sg_dma_len(sg);
1390
1391 ahci_sg[si].addr = cpu_to_le32(addr & 0xffffffff);
1392 ahci_sg[si].addr_hi = cpu_to_le32((addr >> 16) >> 16);
1393 ahci_sg[si].flags_size = cpu_to_le32(sg_len - 1);
1394 }
1395
1396 return si;
1397}
1398
1399static int ahci_pmp_qc_defer(struct ata_queued_cmd *qc)
1400{
1401 struct ata_port *ap = qc->ap;
1402 struct ahci_port_priv *pp = ap->private_data;
1403
1404 if (!sata_pmp_attached(ap) || pp->fbs_enabled)
1405 return ata_std_qc_defer(qc);
1406 else
1407 return sata_pmp_qc_defer_cmd_switch(qc);
1408}
1409
1410static void ahci_qc_prep(struct ata_queued_cmd *qc)
1411{
1412 struct ata_port *ap = qc->ap;
1413 struct ahci_port_priv *pp = ap->private_data;
1414 int is_atapi = ata_is_atapi(qc->tf.protocol);
1415 void *cmd_tbl;
1416 u32 opts;
1417 const u32 cmd_fis_len = 5; /* five dwords */
1418 unsigned int n_elem;
1419
1420 /*
1421 * Fill in command table information. First, the header,
1422 * a SATA Register - Host to Device command FIS.
1423 */
1424 cmd_tbl = pp->cmd_tbl + qc->tag * AHCI_CMD_TBL_SZ;
1425
1426 ata_tf_to_fis(&qc->tf, qc->dev->link->pmp, 1, cmd_tbl);
1427 if (is_atapi) {
1428 memset(cmd_tbl + AHCI_CMD_TBL_CDB, 0, 32);
1429 memcpy(cmd_tbl + AHCI_CMD_TBL_CDB, qc->cdb, qc->dev->cdb_len);
1430 }
1431
1432 n_elem = 0;
1433 if (qc->flags & ATA_QCFLAG_DMAMAP)
1434 n_elem = ahci_fill_sg(qc, cmd_tbl);
1435
1436 /*
1437 * Fill in command slot information.
1438 */
1439 opts = cmd_fis_len | n_elem << 16 | (qc->dev->link->pmp << 12);
1440 if (qc->tf.flags & ATA_TFLAG_WRITE)
1441 opts |= AHCI_CMD_WRITE;
1442 if (is_atapi)
1443 opts |= AHCI_CMD_ATAPI | AHCI_CMD_PREFETCH;
1444
1445 ahci_fill_cmd_slot(pp, qc->tag, opts);
1446}
1447
1448static void ahci_fbs_dec_intr(struct ata_port *ap)
1449{
1450 struct ahci_port_priv *pp = ap->private_data;
1451 void __iomem *port_mmio = ahci_port_base(ap);
1452 u32 fbs = readl(port_mmio + PORT_FBS);
1453 int retries = 3;
1454
1455 DPRINTK("ENTER\n");
1456 BUG_ON(!pp->fbs_enabled);
1457
1458 /* time to wait for DEC is not specified by AHCI spec,
1459 * add a retry loop for safety.
1460 */
1461 writel(fbs | PORT_FBS_DEC, port_mmio + PORT_FBS);
1462 fbs = readl(port_mmio + PORT_FBS);
1463 while ((fbs & PORT_FBS_DEC) && retries--) {
1464 udelay(1);
1465 fbs = readl(port_mmio + PORT_FBS);
1466 }
1467
1468 if (fbs & PORT_FBS_DEC)
a44fec1f 1469 dev_err(ap->host->dev, "failed to clear device error\n");
365cfa1e
AV		 1470}
1471
1472static void ahci_error_intr(struct ata_port *ap, u32 irq_stat)
1473{
1474 struct ahci_host_priv *hpriv = ap->host->private_data;
1475 struct ahci_port_priv *pp = ap->private_data;
1476 struct ata_eh_info *host_ehi = &ap->link.eh_info;
1477 struct ata_link *link = NULL;
1478 struct ata_queued_cmd *active_qc;
1479 struct ata_eh_info *active_ehi;
1480 bool fbs_need_dec = false;
1481 u32 serror;
1482
1483 /* determine active link with error */
1484 if (pp->fbs_enabled) {
1485 void __iomem *port_mmio = ahci_port_base(ap);
1486 u32 fbs = readl(port_mmio + PORT_FBS);
1487 int pmp = fbs >> PORT_FBS_DWE_OFFSET;
1488
1489 if ((fbs & PORT_FBS_SDE) && (pmp < ap->nr_pmp_links) &&
1490 ata_link_online(&ap->pmp_link[pmp])) {
1491 link = &ap->pmp_link[pmp];
1492 fbs_need_dec = true;
1493 }
1494
1495 } else
1496 ata_for_each_link(link, ap, EDGE)
1497 if (ata_link_active(link))
1498 break;
1499
1500 if (!link)
1501 link = &ap->link;
1502
1503 active_qc = ata_qc_from_tag(ap, link->active_tag);
1504 active_ehi = &link->eh_info;
1505
1506 /* record irq stat */
1507 ata_ehi_clear_desc(host_ehi);
1508 ata_ehi_push_desc(host_ehi, "irq_stat 0x%08x", irq_stat);
1509
1510 /* AHCI needs SError cleared; otherwise, it might lock up */
1511 ahci_scr_read(&ap->link, SCR_ERROR, &serror);
1512 ahci_scr_write(&ap->link, SCR_ERROR, serror);
1513 host_ehi->serror |= serror;
1514
1515 /* some controllers set IRQ_IF_ERR on device errors, ignore it */
1516 if (hpriv->flags & AHCI_HFLAG_IGN_IRQ_IF_ERR)
1517 irq_stat &= ~PORT_IRQ_IF_ERR;
1518
1519 if (irq_stat & PORT_IRQ_TF_ERR) {
1520 /* If qc is active, charge it; otherwise, the active
1521 * link. There's no active qc on NCQ errors. It will
1522 * be determined by EH by reading log page 10h.
1523 */
1524 if (active_qc)
1525 active_qc->err_mask |= AC_ERR_DEV;
1526 else
1527 active_ehi->err_mask |= AC_ERR_DEV;
1528
1529 if (hpriv->flags & AHCI_HFLAG_IGN_SERR_INTERNAL)
1530 host_ehi->serror &= ~SERR_INTERNAL;
1531 }
1532
1533 if (irq_stat & PORT_IRQ_UNK_FIS) {
1534 u32 *unk = (u32 *)(pp->rx_fis + RX_FIS_UNK);
1535
1536 active_ehi->err_mask |= AC_ERR_HSM;
1537 active_ehi->action |= ATA_EH_RESET;
1538 ata_ehi_push_desc(active_ehi,
1539 "unknown FIS %08x %08x %08x %08x" ,
1540 unk[0], unk[1], unk[2], unk[3]);
1541 }
1542
1543 if (sata_pmp_attached(ap) && (irq_stat & PORT_IRQ_BAD_PMP)) {
1544 active_ehi->err_mask |= AC_ERR_HSM;
1545 active_ehi->action |= ATA_EH_RESET;
1546 ata_ehi_push_desc(active_ehi, "incorrect PMP");
1547 }
1548
1549 if (irq_stat & (PORT_IRQ_HBUS_ERR | PORT_IRQ_HBUS_DATA_ERR)) {
1550 host_ehi->err_mask |= AC_ERR_HOST_BUS;
1551 host_ehi->action |= ATA_EH_RESET;
1552 ata_ehi_push_desc(host_ehi, "host bus error");
1553 }
1554
1555 if (irq_stat & PORT_IRQ_IF_ERR) {
1556 if (fbs_need_dec)
1557 active_ehi->err_mask |= AC_ERR_DEV;
1558 else {
1559 host_ehi->err_mask |= AC_ERR_ATA_BUS;
1560 host_ehi->action |= ATA_EH_RESET;
1561 }
1562
1563 ata_ehi_push_desc(host_ehi, "interface fatal error");
1564 }
1565
1566 if (irq_stat & (PORT_IRQ_CONNECT | PORT_IRQ_PHYRDY)) {
1567 ata_ehi_hotplugged(host_ehi);
1568 ata_ehi_push_desc(host_ehi, "%s",
1569 irq_stat & PORT_IRQ_CONNECT ?
1570 "connection status changed" : "PHY RDY changed");
1571 }
1572
1573 /* okay, let's hand over to EH */
1574
1575 if (irq_stat & PORT_IRQ_FREEZE)
1576 ata_port_freeze(ap);
1577 else if (fbs_need_dec) {
1578 ata_link_abort(link);
1579 ahci_fbs_dec_intr(ap);
1580 } else
1581 ata_port_abort(ap);
1582}
1583
1584static void ahci_port_intr(struct ata_port *ap)
1585{
1586 void __iomem *port_mmio = ahci_port_base(ap);
1587 struct ata_eh_info *ehi = &ap->link.eh_info;
1588 struct ahci_port_priv *pp = ap->private_data;
1589 struct ahci_host_priv *hpriv = ap->host->private_data;
1590 int resetting = !!(ap->pflags & ATA_PFLAG_RESETTING);
1591 u32 status, qc_active = 0;
1592 int rc;
1593
1594 status = readl(port_mmio + PORT_IRQ_STAT);
1595 writel(status, port_mmio + PORT_IRQ_STAT);
1596
1597 /* ignore BAD_PMP while resetting */
1598 if (unlikely(resetting))
1599 status &= ~PORT_IRQ_BAD_PMP;
1600
6b7ae954
TH		 1601 /* if LPM is enabled, PHYRDY doesn't mean anything */
1602 if (ap->link.lpm_policy > ATA_LPM_MAX_POWER) {
365cfa1e 1603 status &= ~PORT_IRQ_PHYRDY;
6b7ae954 1604 ahci_scr_write(&ap->link, SCR_ERROR, SERR_PHYRDY_CHG);
365cfa1e
AV		 1605 }
1606
1607 if (unlikely(status & PORT_IRQ_ERROR)) {
1608 ahci_error_intr(ap, status);
1609 return;
1610 }
1611
1612 if (status & PORT_IRQ_SDB_FIS) {
1613 /* If SNotification is available, leave notification
1614 * handling to sata_async_notification(). If not,
1615 * emulate it by snooping SDB FIS RX area.
1616 *
1617 * Snooping FIS RX area is probably cheaper than
1618 * poking SNotification but some constrollers which
1619 * implement SNotification, ICH9 for example, don't
1620 * store AN SDB FIS into receive area.
1621 */
1622 if (hpriv->cap & HOST_CAP_SNTF)
1623 sata_async_notification(ap);
1624 else {
1625 /* If the 'N' bit in word 0 of the FIS is set,
1626 * we just received asynchronous notification.
1627 * Tell libata about it.
1628 *
1629 * Lack of SNotification should not appear in
1630 * ahci 1.2, so the workaround is unnecessary
1631 * when FBS is enabled.
1632 */
1633 if (pp->fbs_enabled)
1634 WARN_ON_ONCE(1);
1635 else {
1636 const __le32 *f = pp->rx_fis + RX_FIS_SDB;
1637 u32 f0 = le32_to_cpu(f[0]);
1638 if (f0 & (1 << 15))
1639 sata_async_notification(ap);
1640 }
1641 }
1642 }
1643
1644 /* pp->active_link is not reliable once FBS is enabled, both
1645 * PORT_SCR_ACT and PORT_CMD_ISSUE should be checked because
1646 * NCQ and non-NCQ commands may be in flight at the same time.
1647 */
1648 if (pp->fbs_enabled) {
1649 if (ap->qc_active) {
1650 qc_active = readl(port_mmio + PORT_SCR_ACT);
1651 qc_active |= readl(port_mmio + PORT_CMD_ISSUE);
1652 }
1653 } else {
1654 /* pp->active_link is valid iff any command is in flight */
1655 if (ap->qc_active && pp->active_link->sactive)
1656 qc_active = readl(port_mmio + PORT_SCR_ACT);
1657 else
1658 qc_active = readl(port_mmio + PORT_CMD_ISSUE);
1659 }
1660
1661
1662 rc = ata_qc_complete_multiple(ap, qc_active);
1663
1664 /* while resetting, invalid completions are expected */
1665 if (unlikely(rc < 0 && !resetting)) {
1666 ehi->err_mask |= AC_ERR_HSM;
1667 ehi->action |= ATA_EH_RESET;
1668 ata_port_freeze(ap);
1669 }
1670}
1671
1672irqreturn_t ahci_interrupt(int irq, void *dev_instance)
1673{
1674 struct ata_host *host = dev_instance;
1675 struct ahci_host_priv *hpriv;
1676 unsigned int i, handled = 0;
1677 void __iomem *mmio;
1678 u32 irq_stat, irq_masked;
1679
1680 VPRINTK("ENTER\n");
1681
1682 hpriv = host->private_data;
1683 mmio = hpriv->mmio;
1684
1685 /* sigh. 0xffffffff is a valid return from h/w */
1686 irq_stat = readl(mmio + HOST_IRQ_STAT);
1687 if (!irq_stat)
1688 return IRQ_NONE;
1689
1690 irq_masked = irq_stat & hpriv->port_map;
1691
1692 spin_lock(&host->lock);
1693
1694 for (i = 0; i < host->n_ports; i++) {
1695 struct ata_port *ap;
1696
1697 if (!(irq_masked & (1 << i)))
1698 continue;
1699
1700 ap = host->ports[i];
1701 if (ap) {
1702 ahci_port_intr(ap);
1703 VPRINTK("port %u\n", i);
1704 } else {
1705 VPRINTK("port %u (no irq)\n", i);
1706 if (ata_ratelimit())
a44fec1f
JP		 1707 dev_warn(host->dev,
1708 "interrupt on disabled port %u\n", i);
365cfa1e
AV		 1709 }
1710
1711 handled = 1;
1712 }
1713
1714 /* HOST_IRQ_STAT behaves as level triggered latch meaning that
1715 * it should be cleared after all the port events are cleared;
1716 * otherwise, it will raise a spurious interrupt after each
1717 * valid one. Please read section 10.6.2 of ahci 1.1 for more
1718 * information.
1719 *
1720 * Also, use the unmasked value to clear interrupt as spurious
1721 * pending event on a dummy port might cause screaming IRQ.
1722 */
1723 writel(irq_stat, mmio + HOST_IRQ_STAT);
1724
1725 spin_unlock(&host->lock);
1726
1727 VPRINTK("EXIT\n");
1728
1729 return IRQ_RETVAL(handled);
1730}
1731EXPORT_SYMBOL_GPL(ahci_interrupt);
1732
1733static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc)
1734{
1735 struct ata_port *ap = qc->ap;
1736 void __iomem *port_mmio = ahci_port_base(ap);
1737 struct ahci_port_priv *pp = ap->private_data;
1738
1739 /* Keep track of the currently active link. It will be used
1740 * in completion path to determine whether NCQ phase is in
1741 * progress.
1742 */
1743 pp->active_link = qc->dev->link;
1744
1745 if (qc->tf.protocol == ATA_PROT_NCQ)
1746 writel(1 << qc->tag, port_mmio + PORT_SCR_ACT);
1747
1748 if (pp->fbs_enabled && pp->fbs_last_dev != qc->dev->link->pmp) {
1749 u32 fbs = readl(port_mmio + PORT_FBS);
1750 fbs &= ~(PORT_FBS_DEV_MASK | PORT_FBS_DEC);
1751 fbs |= qc->dev->link->pmp << PORT_FBS_DEV_OFFSET;
1752 writel(fbs, port_mmio + PORT_FBS);
1753 pp->fbs_last_dev = qc->dev->link->pmp;
1754 }
1755
1756 writel(1 << qc->tag, port_mmio + PORT_CMD_ISSUE);
1757
1758 ahci_sw_activity(qc->dev->link);
1759
1760 return 0;
1761}
1762
1763static bool ahci_qc_fill_rtf(struct ata_queued_cmd *qc)
1764{
1765 struct ahci_port_priv *pp = qc->ap->private_data;
6ad60195 1766 u8 *rx_fis = pp->rx_fis;
365cfa1e
AV		 1767
1768 if (pp->fbs_enabled)
6ad60195
TH		 1769 rx_fis += qc->dev->link->pmp * AHCI_RX_FIS_SZ;
1770
1771 /*
1772 * After a successful execution of an ATA PIO data-in command,
1773 * the device doesn't send D2H Reg FIS to update the TF and
1774 * the host should take TF and E_Status from the preceding PIO
1775 * Setup FIS.
1776 */
1777 if (qc->tf.protocol == ATA_PROT_PIO && qc->dma_dir == DMA_FROM_DEVICE &&
1778 !(qc->flags & ATA_QCFLAG_FAILED)) {
1779 ata_tf_from_fis(rx_fis + RX_FIS_PIO_SETUP, &qc->result_tf);
1780 qc->result_tf.command = (rx_fis + RX_FIS_PIO_SETUP)[15];
1781 } else
1782 ata_tf_from_fis(rx_fis + RX_FIS_D2H_REG, &qc->result_tf);
365cfa1e 1783
365cfa1e
AV		 1784 return true;
1785}
1786
1787static void ahci_freeze(struct ata_port *ap)
1788{
1789 void __iomem *port_mmio = ahci_port_base(ap);
1790
1791 /* turn IRQ off */
1792 writel(0, port_mmio + PORT_IRQ_MASK);
1793}
1794
1795static void ahci_thaw(struct ata_port *ap)
1796{
1797 struct ahci_host_priv *hpriv = ap->host->private_data;
1798 void __iomem *mmio = hpriv->mmio;
1799 void __iomem *port_mmio = ahci_port_base(ap);
1800 u32 tmp;
1801 struct ahci_port_priv *pp = ap->private_data;
1802
1803 /* clear IRQ */
1804 tmp = readl(port_mmio + PORT_IRQ_STAT);
1805 writel(tmp, port_mmio + PORT_IRQ_STAT);
1806 writel(1 << ap->port_no, mmio + HOST_IRQ_STAT);
1807
1808 /* turn IRQ back on */
1809 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
1810}
1811
1812static void ahci_error_handler(struct ata_port *ap)
1813{
1814 if (!(ap->pflags & ATA_PFLAG_FROZEN)) {
1815 /* restart engine */
1816 ahci_stop_engine(ap);
1817 ahci_start_engine(ap);
1818 }
1819
1820 sata_pmp_error_handler(ap);
0ee71952
TH		 1821
1822 if (!ata_dev_enabled(ap->link.device))
1823 ahci_stop_engine(ap);
365cfa1e
AV		 1824}
1825
1826static void ahci_post_internal_cmd(struct ata_queued_cmd *qc)
1827{
1828 struct ata_port *ap = qc->ap;
1829
1830 /* make DMA engine forget about the failed command */
1831 if (qc->flags & ATA_QCFLAG_FAILED)
1832 ahci_kick_engine(ap);
1833}
1834
1835static void ahci_enable_fbs(struct ata_port *ap)
1836{
1837 struct ahci_port_priv *pp = ap->private_data;
1838 void __iomem *port_mmio = ahci_port_base(ap);
1839 u32 fbs;
1840 int rc;
1841
1842 if (!pp->fbs_supported)
1843 return;
1844
1845 fbs = readl(port_mmio + PORT_FBS);
1846 if (fbs & PORT_FBS_EN) {
1847 pp->fbs_enabled = true;
1848 pp->fbs_last_dev = -1; /* initialization */
1849 return;
1850 }
1851
1852 rc = ahci_stop_engine(ap);
1853 if (rc)
1854 return;
1855
1856 writel(fbs | PORT_FBS_EN, port_mmio + PORT_FBS);
1857 fbs = readl(port_mmio + PORT_FBS);
1858 if (fbs & PORT_FBS_EN) {
a44fec1f 1859 dev_info(ap->host->dev, "FBS is enabled\n");
365cfa1e
AV		 1860 pp->fbs_enabled = true;
1861 pp->fbs_last_dev = -1; /* initialization */
1862 } else
a44fec1f 1863 dev_err(ap->host->dev, "Failed to enable FBS\n");
365cfa1e
AV		 1864
1865 ahci_start_engine(ap);
1866}
1867
1868static void ahci_disable_fbs(struct ata_port *ap)
1869{
1870 struct ahci_port_priv *pp = ap->private_data;
1871 void __iomem *port_mmio = ahci_port_base(ap);
1872 u32 fbs;
1873 int rc;
1874
1875 if (!pp->fbs_supported)
1876 return;
1877
1878 fbs = readl(port_mmio + PORT_FBS);
1879 if ((fbs & PORT_FBS_EN) == 0) {
1880 pp->fbs_enabled = false;
1881 return;
1882 }
1883
1884 rc = ahci_stop_engine(ap);
1885 if (rc)
1886 return;
1887
1888 writel(fbs & ~PORT_FBS_EN, port_mmio + PORT_FBS);
1889 fbs = readl(port_mmio + PORT_FBS);
1890 if (fbs & PORT_FBS_EN)
a44fec1f 1891 dev_err(ap->host->dev, "Failed to disable FBS\n");
365cfa1e 1892 else {
a44fec1f 1893 dev_info(ap->host->dev, "FBS is disabled\n");
365cfa1e
AV		 1894 pp->fbs_enabled = false;
1895 }
1896
1897 ahci_start_engine(ap);
1898}
1899
1900static void ahci_pmp_attach(struct ata_port *ap)
1901{
1902 void __iomem *port_mmio = ahci_port_base(ap);
1903 struct ahci_port_priv *pp = ap->private_data;
1904 u32 cmd;
1905
1906 cmd = readl(port_mmio + PORT_CMD);
1907 cmd |= PORT_CMD_PMP;
1908 writel(cmd, port_mmio + PORT_CMD);
1909
1910 ahci_enable_fbs(ap);
1911
1912 pp->intr_mask |= PORT_IRQ_BAD_PMP;
7b3a24c5
MB		 1913
1914 /*
1915 * We must not change the port interrupt mask register if the
1916 * port is marked frozen, the value in pp->intr_mask will be
1917 * restored later when the port is thawed.
1918 *
1919 * Note that during initialization, the port is marked as
1920 * frozen since the irq handler is not yet registered.
1921 */
1922 if (!(ap->pflags & ATA_PFLAG_FROZEN))
1923 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
365cfa1e
AV		 1924}
1925
1926static void ahci_pmp_detach(struct ata_port *ap)
1927{
1928 void __iomem *port_mmio = ahci_port_base(ap);
1929 struct ahci_port_priv *pp = ap->private_data;
1930 u32 cmd;
1931
1932 ahci_disable_fbs(ap);
1933
1934 cmd = readl(port_mmio + PORT_CMD);
1935 cmd &= ~PORT_CMD_PMP;
1936 writel(cmd, port_mmio + PORT_CMD);
1937
1938 pp->intr_mask &= ~PORT_IRQ_BAD_PMP;
7b3a24c5
MB		 1939
1940 /* see comment above in ahci_pmp_attach() */
1941 if (!(ap->pflags & ATA_PFLAG_FROZEN))
1942 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
365cfa1e
AV		 1943}
1944
02cdfcf0 1945int ahci_port_resume(struct ata_port *ap)
365cfa1e
AV		 1946{
1947 ahci_power_up(ap);
1948 ahci_start_port(ap);
1949
1950 if (sata_pmp_attached(ap))
1951 ahci_pmp_attach(ap);
1952 else
1953 ahci_pmp_detach(ap);
1954
1955 return 0;
1956}
02cdfcf0 1957EXPORT_SYMBOL_GPL(ahci_port_resume);
365cfa1e
AV		 1958
1959#ifdef CONFIG_PM
1960static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg)
1961{
1962 const char *emsg = NULL;
1963 int rc;
1964
1965 rc = ahci_deinit_port(ap, &emsg);
1966 if (rc == 0)
1967 ahci_power_down(ap);
1968 else {
1969 ata_port_printk(ap, KERN_ERR, "%s (%d)\n", emsg, rc);
1970 ahci_start_port(ap);
1971 }
1972
1973 return rc;
1974}
1975#endif
1976
1977static int ahci_port_start(struct ata_port *ap)
1978{
1979 struct ahci_host_priv *hpriv = ap->host->private_data;
1980 struct device *dev = ap->host->dev;
1981 struct ahci_port_priv *pp;
1982 void *mem;
1983 dma_addr_t mem_dma;
1984 size_t dma_sz, rx_fis_sz;
1985
1986 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
1987 if (!pp)
1988 return -ENOMEM;
1989
1990 /* check FBS capability */
1991 if ((hpriv->cap & HOST_CAP_FBS) && sata_pmp_supported(ap)) {
1992 void __iomem *port_mmio = ahci_port_base(ap);
1993 u32 cmd = readl(port_mmio + PORT_CMD);
1994 if (cmd & PORT_CMD_FBSCP)
1995 pp->fbs_supported = true;
5f173107 1996 else if (hpriv->flags & AHCI_HFLAG_YES_FBS) {
a44fec1f
JP		 1997 dev_info(dev, "port %d can do FBS, forcing FBSCP\n",
1998 ap->port_no);
5f173107
TH		 1999 pp->fbs_supported = true;
2000 } else
a44fec1f
JP		 2001 dev_warn(dev, "port %d is not capable of FBS\n",
2002 ap->port_no);
365cfa1e
AV		 2003 }
2004
2005 if (pp->fbs_supported) {
2006 dma_sz = AHCI_PORT_PRIV_FBS_DMA_SZ;
2007 rx_fis_sz = AHCI_RX_FIS_SZ * 16;
2008 } else {
2009 dma_sz = AHCI_PORT_PRIV_DMA_SZ;
2010 rx_fis_sz = AHCI_RX_FIS_SZ;
2011 }
2012
2013 mem = dmam_alloc_coherent(dev, dma_sz, &mem_dma, GFP_KERNEL);
2014 if (!mem)
2015 return -ENOMEM;
2016 memset(mem, 0, dma_sz);
2017
2018 /*
2019 * First item in chunk of DMA memory: 32-slot command table,
2020 * 32 bytes each in size
2021 */
2022 pp->cmd_slot = mem;
2023 pp->cmd_slot_dma = mem_dma;
2024
2025 mem += AHCI_CMD_SLOT_SZ;
2026 mem_dma += AHCI_CMD_SLOT_SZ;
2027
2028 /*
2029 * Second item: Received-FIS area
2030 */
2031 pp->rx_fis = mem;
2032 pp->rx_fis_dma = mem_dma;
2033
2034 mem += rx_fis_sz;
2035 mem_dma += rx_fis_sz;
2036
2037 /*
2038 * Third item: data area for storing a single command
2039 * and its scatter-gather table
2040 */
2041 pp->cmd_tbl = mem;
2042 pp->cmd_tbl_dma = mem_dma;
2043
2044 /*
2045 * Save off initial list of interrupts to be enabled.
2046 * This could be changed later
2047 */
2048 pp->intr_mask = DEF_PORT_IRQ;
2049
2050 ap->private_data = pp;
2051
2052 /* engage engines, captain */
2053 return ahci_port_resume(ap);
2054}
2055
2056static void ahci_port_stop(struct ata_port *ap)
2057{
2058 const char *emsg = NULL;
2059 int rc;
2060
2061 /* de-initialize port */
2062 rc = ahci_deinit_port(ap, &emsg);
2063 if (rc)
2064 ata_port_printk(ap, KERN_WARNING, "%s (%d)\n", emsg, rc);
2065}
2066
2067void ahci_print_info(struct ata_host *host, const char *scc_s)
2068{
2069 struct ahci_host_priv *hpriv = host->private_data;
2070 void __iomem *mmio = hpriv->mmio;
2071 u32 vers, cap, cap2, impl, speed;
2072 const char *speed_s;
2073
2074 vers = readl(mmio + HOST_VERSION);
2075 cap = hpriv->cap;
2076 cap2 = hpriv->cap2;
2077 impl = hpriv->port_map;
2078
2079 speed = (cap >> 20) & 0xf;
2080 if (speed == 1)
2081 speed_s = "1.5";
2082 else if (speed == 2)
2083 speed_s = "3";
2084 else if (speed == 3)
2085 speed_s = "6";
2086 else
2087 speed_s = "?";
2088
2089 dev_info(host->dev,
2090 "AHCI %02x%02x.%02x%02x "
2091 "%u slots %u ports %s Gbps 0x%x impl %s mode\n"
2092 ,
2093
2094 (vers >> 24) & 0xff,
2095 (vers >> 16) & 0xff,
2096 (vers >> 8) & 0xff,
2097 vers & 0xff,
2098
2099 ((cap >> 8) & 0x1f) + 1,
2100 (cap & 0x1f) + 1,
2101 speed_s,
2102 impl,
2103 scc_s);
2104
2105 dev_info(host->dev,
2106 "flags: "
2107 "%s%s%s%s%s%s%s"
2108 "%s%s%s%s%s%s%s"
2109 "%s%s%s%s%s%s\n"
2110 ,
2111
2112 cap & HOST_CAP_64 ? "64bit " : "",
2113 cap & HOST_CAP_NCQ ? "ncq " : "",
2114 cap & HOST_CAP_SNTF ? "sntf " : "",
2115 cap & HOST_CAP_MPS ? "ilck " : "",
2116 cap & HOST_CAP_SSS ? "stag " : "",
2117 cap & HOST_CAP_ALPM ? "pm " : "",
2118 cap & HOST_CAP_LED ? "led " : "",
2119 cap & HOST_CAP_CLO ? "clo " : "",
2120 cap & HOST_CAP_ONLY ? "only " : "",
2121 cap & HOST_CAP_PMP ? "pmp " : "",
2122 cap & HOST_CAP_FBS ? "fbs " : "",
2123 cap & HOST_CAP_PIO_MULTI ? "pio " : "",
2124 cap & HOST_CAP_SSC ? "slum " : "",
2125 cap & HOST_CAP_PART ? "part " : "",
2126 cap & HOST_CAP_CCC ? "ccc " : "",
2127 cap & HOST_CAP_EMS ? "ems " : "",
2128 cap & HOST_CAP_SXS ? "sxs " : "",
2129 cap2 & HOST_CAP2_APST ? "apst " : "",
2130 cap2 & HOST_CAP2_NVMHCI ? "nvmp " : "",
2131 cap2 & HOST_CAP2_BOH ? "boh " : ""
2132 );
2133}
2134EXPORT_SYMBOL_GPL(ahci_print_info);
2135
2136void ahci_set_em_messages(struct ahci_host_priv *hpriv,
2137 struct ata_port_info *pi)
2138{
2139 u8 messages;
2140 void __iomem *mmio = hpriv->mmio;
2141 u32 em_loc = readl(mmio + HOST_EM_LOC);
2142 u32 em_ctl = readl(mmio + HOST_EM_CTL);
2143
2144 if (!ahci_em_messages || !(hpriv->cap & HOST_CAP_EMS))
2145 return;
2146
2147 messages = (em_ctl & EM_CTRL_MSG_TYPE) >> 16;
2148
008dbd61 2149 if (messages) {
365cfa1e
AV		 2150 /* store em_loc */
2151 hpriv->em_loc = ((em_loc >> 16) * 4);
c0623166 2152 hpriv->em_buf_sz = ((em_loc & 0xff) * 4);
008dbd61 2153 hpriv->em_msg_type = messages;
365cfa1e
AV		 2154 pi->flags |= ATA_FLAG_EM;
2155 if (!(em_ctl & EM_CTL_ALHD))
2156 pi->flags |= ATA_FLAG_SW_ACTIVITY;
2157 }
2158}
2159EXPORT_SYMBOL_GPL(ahci_set_em_messages);
2160
2161MODULE_AUTHOR("Jeff Garzik");
2162MODULE_DESCRIPTION("Common AHCI SATA low-level routines");
2163MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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