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1fdffbce JG |
1 | /* |
2 | * libata-bmdma.c - helper library for PCI IDE BMDMA | |
3 | * | |
4 | * Maintained by: Jeff Garzik <jgarzik@pobox.com> | |
5 | * Please ALWAYS copy linux-ide@vger.kernel.org | |
6 | * on emails. | |
7 | * | |
8 | * Copyright 2003-2006 Red Hat, Inc. All rights reserved. | |
9 | * Copyright 2003-2006 Jeff Garzik | |
10 | * | |
11 | * | |
12 | * This program is free software; you can redistribute it and/or modify | |
13 | * it under the terms of the GNU General Public License as published by | |
14 | * the Free Software Foundation; either version 2, or (at your option) | |
15 | * any later version. | |
16 | * | |
17 | * This program is distributed in the hope that it will be useful, | |
18 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
19 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
20 | * GNU General Public License for more details. | |
21 | * | |
22 | * You should have received a copy of the GNU General Public License | |
23 | * along with this program; see the file COPYING. If not, write to | |
24 | * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. | |
25 | * | |
26 | * | |
27 | * libata documentation is available via 'make {ps|pdf}docs', | |
28 | * as Documentation/DocBook/libata.* | |
29 | * | |
30 | * Hardware documentation available from http://www.t13.org/ and | |
31 | * http://www.sata-io.org/ | |
32 | * | |
33 | */ | |
34 | ||
1fdffbce JG |
35 | #include <linux/kernel.h> |
36 | #include <linux/pci.h> | |
37 | #include <linux/libata.h> | |
38 | ||
39 | #include "libata.h" | |
40 | ||
90088bb4 TH |
41 | /** |
42 | * ata_irq_on - Enable interrupts on a port. | |
43 | * @ap: Port on which interrupts are enabled. | |
44 | * | |
45 | * Enable interrupts on a legacy IDE device using MMIO or PIO, | |
46 | * wait for idle, clear any pending interrupts. | |
47 | * | |
48 | * LOCKING: | |
49 | * Inherited from caller. | |
50 | */ | |
51 | u8 ata_irq_on(struct ata_port *ap) | |
52 | { | |
53 | struct ata_ioports *ioaddr = &ap->ioaddr; | |
54 | u8 tmp; | |
55 | ||
56 | ap->ctl &= ~ATA_NIEN; | |
57 | ap->last_ctl = ap->ctl; | |
58 | ||
59 | if (ap->flags & ATA_FLAG_MMIO) | |
60 | writeb(ap->ctl, (void __iomem *) ioaddr->ctl_addr); | |
61 | else | |
62 | outb(ap->ctl, ioaddr->ctl_addr); | |
63 | tmp = ata_wait_idle(ap); | |
64 | ||
65 | ap->ops->irq_clear(ap); | |
66 | ||
67 | return tmp; | |
68 | } | |
69 | ||
1fdffbce JG |
70 | /** |
71 | * ata_tf_load_pio - send taskfile registers to host controller | |
72 | * @ap: Port to which output is sent | |
73 | * @tf: ATA taskfile register set | |
74 | * | |
75 | * Outputs ATA taskfile to standard ATA host controller. | |
76 | * | |
77 | * LOCKING: | |
78 | * Inherited from caller. | |
79 | */ | |
80 | ||
81 | static void ata_tf_load_pio(struct ata_port *ap, const struct ata_taskfile *tf) | |
82 | { | |
83 | struct ata_ioports *ioaddr = &ap->ioaddr; | |
84 | unsigned int is_addr = tf->flags & ATA_TFLAG_ISADDR; | |
85 | ||
86 | if (tf->ctl != ap->last_ctl) { | |
87 | outb(tf->ctl, ioaddr->ctl_addr); | |
88 | ap->last_ctl = tf->ctl; | |
89 | ata_wait_idle(ap); | |
90 | } | |
91 | ||
92 | if (is_addr && (tf->flags & ATA_TFLAG_LBA48)) { | |
93 | outb(tf->hob_feature, ioaddr->feature_addr); | |
94 | outb(tf->hob_nsect, ioaddr->nsect_addr); | |
95 | outb(tf->hob_lbal, ioaddr->lbal_addr); | |
96 | outb(tf->hob_lbam, ioaddr->lbam_addr); | |
97 | outb(tf->hob_lbah, ioaddr->lbah_addr); | |
98 | VPRINTK("hob: feat 0x%X nsect 0x%X, lba 0x%X 0x%X 0x%X\n", | |
99 | tf->hob_feature, | |
100 | tf->hob_nsect, | |
101 | tf->hob_lbal, | |
102 | tf->hob_lbam, | |
103 | tf->hob_lbah); | |
104 | } | |
105 | ||
106 | if (is_addr) { | |
107 | outb(tf->feature, ioaddr->feature_addr); | |
108 | outb(tf->nsect, ioaddr->nsect_addr); | |
109 | outb(tf->lbal, ioaddr->lbal_addr); | |
110 | outb(tf->lbam, ioaddr->lbam_addr); | |
111 | outb(tf->lbah, ioaddr->lbah_addr); | |
112 | VPRINTK("feat 0x%X nsect 0x%X lba 0x%X 0x%X 0x%X\n", | |
113 | tf->feature, | |
114 | tf->nsect, | |
115 | tf->lbal, | |
116 | tf->lbam, | |
117 | tf->lbah); | |
118 | } | |
119 | ||
120 | if (tf->flags & ATA_TFLAG_DEVICE) { | |
121 | outb(tf->device, ioaddr->device_addr); | |
122 | VPRINTK("device 0x%X\n", tf->device); | |
123 | } | |
124 | ||
125 | ata_wait_idle(ap); | |
126 | } | |
127 | ||
128 | /** | |
129 | * ata_tf_load_mmio - send taskfile registers to host controller | |
130 | * @ap: Port to which output is sent | |
131 | * @tf: ATA taskfile register set | |
132 | * | |
133 | * Outputs ATA taskfile to standard ATA host controller using MMIO. | |
134 | * | |
135 | * LOCKING: | |
136 | * Inherited from caller. | |
137 | */ | |
138 | ||
139 | static void ata_tf_load_mmio(struct ata_port *ap, const struct ata_taskfile *tf) | |
140 | { | |
141 | struct ata_ioports *ioaddr = &ap->ioaddr; | |
142 | unsigned int is_addr = tf->flags & ATA_TFLAG_ISADDR; | |
143 | ||
144 | if (tf->ctl != ap->last_ctl) { | |
145 | writeb(tf->ctl, (void __iomem *) ap->ioaddr.ctl_addr); | |
146 | ap->last_ctl = tf->ctl; | |
147 | ata_wait_idle(ap); | |
148 | } | |
149 | ||
150 | if (is_addr && (tf->flags & ATA_TFLAG_LBA48)) { | |
151 | writeb(tf->hob_feature, (void __iomem *) ioaddr->feature_addr); | |
152 | writeb(tf->hob_nsect, (void __iomem *) ioaddr->nsect_addr); | |
153 | writeb(tf->hob_lbal, (void __iomem *) ioaddr->lbal_addr); | |
154 | writeb(tf->hob_lbam, (void __iomem *) ioaddr->lbam_addr); | |
155 | writeb(tf->hob_lbah, (void __iomem *) ioaddr->lbah_addr); | |
156 | VPRINTK("hob: feat 0x%X nsect 0x%X, lba 0x%X 0x%X 0x%X\n", | |
157 | tf->hob_feature, | |
158 | tf->hob_nsect, | |
159 | tf->hob_lbal, | |
160 | tf->hob_lbam, | |
161 | tf->hob_lbah); | |
162 | } | |
163 | ||
164 | if (is_addr) { | |
165 | writeb(tf->feature, (void __iomem *) ioaddr->feature_addr); | |
166 | writeb(tf->nsect, (void __iomem *) ioaddr->nsect_addr); | |
167 | writeb(tf->lbal, (void __iomem *) ioaddr->lbal_addr); | |
168 | writeb(tf->lbam, (void __iomem *) ioaddr->lbam_addr); | |
169 | writeb(tf->lbah, (void __iomem *) ioaddr->lbah_addr); | |
170 | VPRINTK("feat 0x%X nsect 0x%X lba 0x%X 0x%X 0x%X\n", | |
171 | tf->feature, | |
172 | tf->nsect, | |
173 | tf->lbal, | |
174 | tf->lbam, | |
175 | tf->lbah); | |
176 | } | |
177 | ||
178 | if (tf->flags & ATA_TFLAG_DEVICE) { | |
179 | writeb(tf->device, (void __iomem *) ioaddr->device_addr); | |
180 | VPRINTK("device 0x%X\n", tf->device); | |
181 | } | |
182 | ||
183 | ata_wait_idle(ap); | |
184 | } | |
185 | ||
186 | ||
187 | /** | |
188 | * ata_tf_load - send taskfile registers to host controller | |
189 | * @ap: Port to which output is sent | |
190 | * @tf: ATA taskfile register set | |
191 | * | |
192 | * Outputs ATA taskfile to standard ATA host controller using MMIO | |
193 | * or PIO as indicated by the ATA_FLAG_MMIO flag. | |
194 | * Writes the control, feature, nsect, lbal, lbam, and lbah registers. | |
195 | * Optionally (ATA_TFLAG_LBA48) writes hob_feature, hob_nsect, | |
196 | * hob_lbal, hob_lbam, and hob_lbah. | |
197 | * | |
198 | * This function waits for idle (!BUSY and !DRQ) after writing | |
199 | * registers. If the control register has a new value, this | |
200 | * function also waits for idle after writing control and before | |
201 | * writing the remaining registers. | |
202 | * | |
203 | * May be used as the tf_load() entry in ata_port_operations. | |
204 | * | |
205 | * LOCKING: | |
206 | * Inherited from caller. | |
207 | */ | |
208 | void ata_tf_load(struct ata_port *ap, const struct ata_taskfile *tf) | |
209 | { | |
210 | if (ap->flags & ATA_FLAG_MMIO) | |
211 | ata_tf_load_mmio(ap, tf); | |
212 | else | |
213 | ata_tf_load_pio(ap, tf); | |
214 | } | |
215 | ||
216 | /** | |
217 | * ata_exec_command_pio - issue ATA command to host controller | |
218 | * @ap: port to which command is being issued | |
219 | * @tf: ATA taskfile register set | |
220 | * | |
221 | * Issues PIO write to ATA command register, with proper | |
222 | * synchronization with interrupt handler / other threads. | |
223 | * | |
224 | * LOCKING: | |
cca3974e | 225 | * spin_lock_irqsave(host lock) |
1fdffbce JG |
226 | */ |
227 | ||
228 | static void ata_exec_command_pio(struct ata_port *ap, const struct ata_taskfile *tf) | |
229 | { | |
230 | DPRINTK("ata%u: cmd 0x%X\n", ap->id, tf->command); | |
231 | ||
232 | outb(tf->command, ap->ioaddr.command_addr); | |
233 | ata_pause(ap); | |
234 | } | |
235 | ||
236 | ||
237 | /** | |
238 | * ata_exec_command_mmio - issue ATA command to host controller | |
239 | * @ap: port to which command is being issued | |
240 | * @tf: ATA taskfile register set | |
241 | * | |
242 | * Issues MMIO write to ATA command register, with proper | |
243 | * synchronization with interrupt handler / other threads. | |
244 | * | |
7c74ffd0 AC |
245 | * FIXME: missing write posting for 400nS delay enforcement |
246 | * | |
1fdffbce | 247 | * LOCKING: |
cca3974e | 248 | * spin_lock_irqsave(host lock) |
1fdffbce JG |
249 | */ |
250 | ||
251 | static void ata_exec_command_mmio(struct ata_port *ap, const struct ata_taskfile *tf) | |
252 | { | |
253 | DPRINTK("ata%u: cmd 0x%X\n", ap->id, tf->command); | |
254 | ||
255 | writeb(tf->command, (void __iomem *) ap->ioaddr.command_addr); | |
256 | ata_pause(ap); | |
257 | } | |
258 | ||
259 | ||
260 | /** | |
261 | * ata_exec_command - issue ATA command to host controller | |
262 | * @ap: port to which command is being issued | |
263 | * @tf: ATA taskfile register set | |
264 | * | |
265 | * Issues PIO/MMIO write to ATA command register, with proper | |
266 | * synchronization with interrupt handler / other threads. | |
267 | * | |
268 | * LOCKING: | |
cca3974e | 269 | * spin_lock_irqsave(host lock) |
1fdffbce JG |
270 | */ |
271 | void ata_exec_command(struct ata_port *ap, const struct ata_taskfile *tf) | |
272 | { | |
273 | if (ap->flags & ATA_FLAG_MMIO) | |
274 | ata_exec_command_mmio(ap, tf); | |
275 | else | |
276 | ata_exec_command_pio(ap, tf); | |
277 | } | |
278 | ||
279 | /** | |
280 | * ata_tf_read_pio - input device's ATA taskfile shadow registers | |
281 | * @ap: Port from which input is read | |
282 | * @tf: ATA taskfile register set for storing input | |
283 | * | |
284 | * Reads ATA taskfile registers for currently-selected device | |
285 | * into @tf. | |
286 | * | |
287 | * LOCKING: | |
288 | * Inherited from caller. | |
289 | */ | |
290 | ||
291 | static void ata_tf_read_pio(struct ata_port *ap, struct ata_taskfile *tf) | |
292 | { | |
293 | struct ata_ioports *ioaddr = &ap->ioaddr; | |
294 | ||
295 | tf->command = ata_check_status(ap); | |
296 | tf->feature = inb(ioaddr->error_addr); | |
297 | tf->nsect = inb(ioaddr->nsect_addr); | |
298 | tf->lbal = inb(ioaddr->lbal_addr); | |
299 | tf->lbam = inb(ioaddr->lbam_addr); | |
300 | tf->lbah = inb(ioaddr->lbah_addr); | |
301 | tf->device = inb(ioaddr->device_addr); | |
302 | ||
303 | if (tf->flags & ATA_TFLAG_LBA48) { | |
304 | outb(tf->ctl | ATA_HOB, ioaddr->ctl_addr); | |
305 | tf->hob_feature = inb(ioaddr->error_addr); | |
306 | tf->hob_nsect = inb(ioaddr->nsect_addr); | |
307 | tf->hob_lbal = inb(ioaddr->lbal_addr); | |
308 | tf->hob_lbam = inb(ioaddr->lbam_addr); | |
309 | tf->hob_lbah = inb(ioaddr->lbah_addr); | |
310 | } | |
311 | } | |
312 | ||
313 | /** | |
314 | * ata_tf_read_mmio - input device's ATA taskfile shadow registers | |
315 | * @ap: Port from which input is read | |
316 | * @tf: ATA taskfile register set for storing input | |
317 | * | |
318 | * Reads ATA taskfile registers for currently-selected device | |
319 | * into @tf via MMIO. | |
320 | * | |
321 | * LOCKING: | |
322 | * Inherited from caller. | |
323 | */ | |
324 | ||
325 | static void ata_tf_read_mmio(struct ata_port *ap, struct ata_taskfile *tf) | |
326 | { | |
327 | struct ata_ioports *ioaddr = &ap->ioaddr; | |
328 | ||
329 | tf->command = ata_check_status(ap); | |
330 | tf->feature = readb((void __iomem *)ioaddr->error_addr); | |
331 | tf->nsect = readb((void __iomem *)ioaddr->nsect_addr); | |
332 | tf->lbal = readb((void __iomem *)ioaddr->lbal_addr); | |
333 | tf->lbam = readb((void __iomem *)ioaddr->lbam_addr); | |
334 | tf->lbah = readb((void __iomem *)ioaddr->lbah_addr); | |
335 | tf->device = readb((void __iomem *)ioaddr->device_addr); | |
336 | ||
337 | if (tf->flags & ATA_TFLAG_LBA48) { | |
338 | writeb(tf->ctl | ATA_HOB, (void __iomem *) ap->ioaddr.ctl_addr); | |
339 | tf->hob_feature = readb((void __iomem *)ioaddr->error_addr); | |
340 | tf->hob_nsect = readb((void __iomem *)ioaddr->nsect_addr); | |
341 | tf->hob_lbal = readb((void __iomem *)ioaddr->lbal_addr); | |
342 | tf->hob_lbam = readb((void __iomem *)ioaddr->lbam_addr); | |
343 | tf->hob_lbah = readb((void __iomem *)ioaddr->lbah_addr); | |
344 | } | |
345 | } | |
346 | ||
347 | ||
348 | /** | |
349 | * ata_tf_read - input device's ATA taskfile shadow registers | |
350 | * @ap: Port from which input is read | |
351 | * @tf: ATA taskfile register set for storing input | |
352 | * | |
353 | * Reads ATA taskfile registers for currently-selected device | |
354 | * into @tf. | |
355 | * | |
356 | * Reads nsect, lbal, lbam, lbah, and device. If ATA_TFLAG_LBA48 | |
357 | * is set, also reads the hob registers. | |
358 | * | |
359 | * May be used as the tf_read() entry in ata_port_operations. | |
360 | * | |
361 | * LOCKING: | |
362 | * Inherited from caller. | |
363 | */ | |
364 | void ata_tf_read(struct ata_port *ap, struct ata_taskfile *tf) | |
365 | { | |
366 | if (ap->flags & ATA_FLAG_MMIO) | |
367 | ata_tf_read_mmio(ap, tf); | |
368 | else | |
369 | ata_tf_read_pio(ap, tf); | |
370 | } | |
371 | ||
372 | /** | |
373 | * ata_check_status_pio - Read device status reg & clear interrupt | |
374 | * @ap: port where the device is | |
375 | * | |
376 | * Reads ATA taskfile status register for currently-selected device | |
377 | * and return its value. This also clears pending interrupts | |
378 | * from this device | |
379 | * | |
380 | * LOCKING: | |
381 | * Inherited from caller. | |
382 | */ | |
383 | static u8 ata_check_status_pio(struct ata_port *ap) | |
384 | { | |
385 | return inb(ap->ioaddr.status_addr); | |
386 | } | |
387 | ||
388 | /** | |
389 | * ata_check_status_mmio - Read device status reg & clear interrupt | |
390 | * @ap: port where the device is | |
391 | * | |
392 | * Reads ATA taskfile status register for currently-selected device | |
393 | * via MMIO and return its value. This also clears pending interrupts | |
394 | * from this device | |
395 | * | |
396 | * LOCKING: | |
397 | * Inherited from caller. | |
398 | */ | |
399 | static u8 ata_check_status_mmio(struct ata_port *ap) | |
400 | { | |
401 | return readb((void __iomem *) ap->ioaddr.status_addr); | |
402 | } | |
403 | ||
404 | ||
405 | /** | |
406 | * ata_check_status - Read device status reg & clear interrupt | |
407 | * @ap: port where the device is | |
408 | * | |
409 | * Reads ATA taskfile status register for currently-selected device | |
410 | * and return its value. This also clears pending interrupts | |
411 | * from this device | |
412 | * | |
413 | * May be used as the check_status() entry in ata_port_operations. | |
414 | * | |
415 | * LOCKING: | |
416 | * Inherited from caller. | |
417 | */ | |
418 | u8 ata_check_status(struct ata_port *ap) | |
419 | { | |
420 | if (ap->flags & ATA_FLAG_MMIO) | |
421 | return ata_check_status_mmio(ap); | |
422 | return ata_check_status_pio(ap); | |
423 | } | |
424 | ||
425 | ||
426 | /** | |
427 | * ata_altstatus - Read device alternate status reg | |
428 | * @ap: port where the device is | |
429 | * | |
430 | * Reads ATA taskfile alternate status register for | |
431 | * currently-selected device and return its value. | |
432 | * | |
433 | * Note: may NOT be used as the check_altstatus() entry in | |
434 | * ata_port_operations. | |
435 | * | |
436 | * LOCKING: | |
437 | * Inherited from caller. | |
438 | */ | |
439 | u8 ata_altstatus(struct ata_port *ap) | |
440 | { | |
441 | if (ap->ops->check_altstatus) | |
442 | return ap->ops->check_altstatus(ap); | |
443 | ||
444 | if (ap->flags & ATA_FLAG_MMIO) | |
445 | return readb((void __iomem *)ap->ioaddr.altstatus_addr); | |
446 | return inb(ap->ioaddr.altstatus_addr); | |
447 | } | |
448 | ||
2cc432ee JG |
449 | /** |
450 | * ata_bmdma_setup_mmio - Set up PCI IDE BMDMA transaction | |
451 | * @qc: Info associated with this ATA transaction. | |
452 | * | |
453 | * LOCKING: | |
cca3974e | 454 | * spin_lock_irqsave(host lock) |
2cc432ee JG |
455 | */ |
456 | ||
457 | static void ata_bmdma_setup_mmio (struct ata_queued_cmd *qc) | |
458 | { | |
459 | struct ata_port *ap = qc->ap; | |
460 | unsigned int rw = (qc->tf.flags & ATA_TFLAG_WRITE); | |
461 | u8 dmactl; | |
462 | void __iomem *mmio = (void __iomem *) ap->ioaddr.bmdma_addr; | |
463 | ||
464 | /* load PRD table addr. */ | |
465 | mb(); /* make sure PRD table writes are visible to controller */ | |
466 | writel(ap->prd_dma, mmio + ATA_DMA_TABLE_OFS); | |
467 | ||
468 | /* specify data direction, triple-check start bit is clear */ | |
469 | dmactl = readb(mmio + ATA_DMA_CMD); | |
470 | dmactl &= ~(ATA_DMA_WR | ATA_DMA_START); | |
471 | if (!rw) | |
472 | dmactl |= ATA_DMA_WR; | |
473 | writeb(dmactl, mmio + ATA_DMA_CMD); | |
474 | ||
475 | /* issue r/w command */ | |
476 | ap->ops->exec_command(ap, &qc->tf); | |
477 | } | |
478 | ||
479 | /** | |
480 | * ata_bmdma_start_mmio - Start a PCI IDE BMDMA transaction | |
481 | * @qc: Info associated with this ATA transaction. | |
482 | * | |
483 | * LOCKING: | |
cca3974e | 484 | * spin_lock_irqsave(host lock) |
2cc432ee JG |
485 | */ |
486 | ||
487 | static void ata_bmdma_start_mmio (struct ata_queued_cmd *qc) | |
488 | { | |
489 | struct ata_port *ap = qc->ap; | |
490 | void __iomem *mmio = (void __iomem *) ap->ioaddr.bmdma_addr; | |
491 | u8 dmactl; | |
492 | ||
493 | /* start host DMA transaction */ | |
494 | dmactl = readb(mmio + ATA_DMA_CMD); | |
495 | writeb(dmactl | ATA_DMA_START, mmio + ATA_DMA_CMD); | |
496 | ||
497 | /* Strictly, one may wish to issue a readb() here, to | |
498 | * flush the mmio write. However, control also passes | |
499 | * to the hardware at this point, and it will interrupt | |
500 | * us when we are to resume control. So, in effect, | |
501 | * we don't care when the mmio write flushes. | |
502 | * Further, a read of the DMA status register _immediately_ | |
503 | * following the write may not be what certain flaky hardware | |
504 | * is expected, so I think it is best to not add a readb() | |
505 | * without first all the MMIO ATA cards/mobos. | |
506 | * Or maybe I'm just being paranoid. | |
507 | */ | |
508 | } | |
509 | ||
510 | /** | |
511 | * ata_bmdma_setup_pio - Set up PCI IDE BMDMA transaction (PIO) | |
512 | * @qc: Info associated with this ATA transaction. | |
513 | * | |
514 | * LOCKING: | |
cca3974e | 515 | * spin_lock_irqsave(host lock) |
2cc432ee JG |
516 | */ |
517 | ||
518 | static void ata_bmdma_setup_pio (struct ata_queued_cmd *qc) | |
519 | { | |
520 | struct ata_port *ap = qc->ap; | |
521 | unsigned int rw = (qc->tf.flags & ATA_TFLAG_WRITE); | |
522 | u8 dmactl; | |
523 | ||
524 | /* load PRD table addr. */ | |
525 | outl(ap->prd_dma, ap->ioaddr.bmdma_addr + ATA_DMA_TABLE_OFS); | |
526 | ||
527 | /* specify data direction, triple-check start bit is clear */ | |
528 | dmactl = inb(ap->ioaddr.bmdma_addr + ATA_DMA_CMD); | |
529 | dmactl &= ~(ATA_DMA_WR | ATA_DMA_START); | |
530 | if (!rw) | |
531 | dmactl |= ATA_DMA_WR; | |
532 | outb(dmactl, ap->ioaddr.bmdma_addr + ATA_DMA_CMD); | |
533 | ||
534 | /* issue r/w command */ | |
535 | ap->ops->exec_command(ap, &qc->tf); | |
536 | } | |
537 | ||
538 | /** | |
539 | * ata_bmdma_start_pio - Start a PCI IDE BMDMA transaction (PIO) | |
540 | * @qc: Info associated with this ATA transaction. | |
541 | * | |
542 | * LOCKING: | |
cca3974e | 543 | * spin_lock_irqsave(host lock) |
2cc432ee JG |
544 | */ |
545 | ||
546 | static void ata_bmdma_start_pio (struct ata_queued_cmd *qc) | |
547 | { | |
548 | struct ata_port *ap = qc->ap; | |
549 | u8 dmactl; | |
550 | ||
551 | /* start host DMA transaction */ | |
552 | dmactl = inb(ap->ioaddr.bmdma_addr + ATA_DMA_CMD); | |
553 | outb(dmactl | ATA_DMA_START, | |
554 | ap->ioaddr.bmdma_addr + ATA_DMA_CMD); | |
555 | } | |
556 | ||
557 | ||
558 | /** | |
559 | * ata_bmdma_start - Start a PCI IDE BMDMA transaction | |
560 | * @qc: Info associated with this ATA transaction. | |
561 | * | |
562 | * Writes the ATA_DMA_START flag to the DMA command register. | |
563 | * | |
564 | * May be used as the bmdma_start() entry in ata_port_operations. | |
565 | * | |
566 | * LOCKING: | |
cca3974e | 567 | * spin_lock_irqsave(host lock) |
2cc432ee JG |
568 | */ |
569 | void ata_bmdma_start(struct ata_queued_cmd *qc) | |
570 | { | |
571 | if (qc->ap->flags & ATA_FLAG_MMIO) | |
572 | ata_bmdma_start_mmio(qc); | |
573 | else | |
574 | ata_bmdma_start_pio(qc); | |
575 | } | |
576 | ||
577 | ||
578 | /** | |
579 | * ata_bmdma_setup - Set up PCI IDE BMDMA transaction | |
580 | * @qc: Info associated with this ATA transaction. | |
581 | * | |
582 | * Writes address of PRD table to device's PRD Table Address | |
583 | * register, sets the DMA control register, and calls | |
584 | * ops->exec_command() to start the transfer. | |
585 | * | |
586 | * May be used as the bmdma_setup() entry in ata_port_operations. | |
587 | * | |
588 | * LOCKING: | |
cca3974e | 589 | * spin_lock_irqsave(host lock) |
2cc432ee JG |
590 | */ |
591 | void ata_bmdma_setup(struct ata_queued_cmd *qc) | |
592 | { | |
593 | if (qc->ap->flags & ATA_FLAG_MMIO) | |
594 | ata_bmdma_setup_mmio(qc); | |
595 | else | |
596 | ata_bmdma_setup_pio(qc); | |
597 | } | |
598 | ||
599 | ||
600 | /** | |
601 | * ata_bmdma_irq_clear - Clear PCI IDE BMDMA interrupt. | |
602 | * @ap: Port associated with this ATA transaction. | |
603 | * | |
604 | * Clear interrupt and error flags in DMA status register. | |
605 | * | |
606 | * May be used as the irq_clear() entry in ata_port_operations. | |
607 | * | |
608 | * LOCKING: | |
cca3974e | 609 | * spin_lock_irqsave(host lock) |
2cc432ee JG |
610 | */ |
611 | ||
612 | void ata_bmdma_irq_clear(struct ata_port *ap) | |
613 | { | |
614 | if (!ap->ioaddr.bmdma_addr) | |
615 | return; | |
616 | ||
617 | if (ap->flags & ATA_FLAG_MMIO) { | |
618 | void __iomem *mmio = | |
619 | ((void __iomem *) ap->ioaddr.bmdma_addr) + ATA_DMA_STATUS; | |
620 | writeb(readb(mmio), mmio); | |
621 | } else { | |
622 | unsigned long addr = ap->ioaddr.bmdma_addr + ATA_DMA_STATUS; | |
623 | outb(inb(addr), addr); | |
624 | } | |
625 | } | |
626 | ||
627 | ||
628 | /** | |
629 | * ata_bmdma_status - Read PCI IDE BMDMA status | |
630 | * @ap: Port associated with this ATA transaction. | |
631 | * | |
632 | * Read and return BMDMA status register. | |
633 | * | |
634 | * May be used as the bmdma_status() entry in ata_port_operations. | |
635 | * | |
636 | * LOCKING: | |
cca3974e | 637 | * spin_lock_irqsave(host lock) |
2cc432ee JG |
638 | */ |
639 | ||
640 | u8 ata_bmdma_status(struct ata_port *ap) | |
641 | { | |
642 | u8 host_stat; | |
643 | if (ap->flags & ATA_FLAG_MMIO) { | |
644 | void __iomem *mmio = (void __iomem *) ap->ioaddr.bmdma_addr; | |
645 | host_stat = readb(mmio + ATA_DMA_STATUS); | |
646 | } else | |
647 | host_stat = inb(ap->ioaddr.bmdma_addr + ATA_DMA_STATUS); | |
648 | return host_stat; | |
649 | } | |
650 | ||
651 | ||
652 | /** | |
653 | * ata_bmdma_stop - Stop PCI IDE BMDMA transfer | |
654 | * @qc: Command we are ending DMA for | |
655 | * | |
656 | * Clears the ATA_DMA_START flag in the dma control register | |
657 | * | |
658 | * May be used as the bmdma_stop() entry in ata_port_operations. | |
659 | * | |
660 | * LOCKING: | |
cca3974e | 661 | * spin_lock_irqsave(host lock) |
2cc432ee JG |
662 | */ |
663 | ||
664 | void ata_bmdma_stop(struct ata_queued_cmd *qc) | |
665 | { | |
666 | struct ata_port *ap = qc->ap; | |
667 | if (ap->flags & ATA_FLAG_MMIO) { | |
668 | void __iomem *mmio = (void __iomem *) ap->ioaddr.bmdma_addr; | |
669 | ||
670 | /* clear start/stop bit */ | |
671 | writeb(readb(mmio + ATA_DMA_CMD) & ~ATA_DMA_START, | |
672 | mmio + ATA_DMA_CMD); | |
673 | } else { | |
674 | /* clear start/stop bit */ | |
675 | outb(inb(ap->ioaddr.bmdma_addr + ATA_DMA_CMD) & ~ATA_DMA_START, | |
676 | ap->ioaddr.bmdma_addr + ATA_DMA_CMD); | |
677 | } | |
678 | ||
679 | /* one-PIO-cycle guaranteed wait, per spec, for HDMA1:0 transition */ | |
680 | ata_altstatus(ap); /* dummy read */ | |
681 | } | |
682 | ||
6d97dbd7 TH |
683 | /** |
684 | * ata_bmdma_freeze - Freeze BMDMA controller port | |
685 | * @ap: port to freeze | |
686 | * | |
687 | * Freeze BMDMA controller port. | |
688 | * | |
689 | * LOCKING: | |
690 | * Inherited from caller. | |
691 | */ | |
692 | void ata_bmdma_freeze(struct ata_port *ap) | |
693 | { | |
694 | struct ata_ioports *ioaddr = &ap->ioaddr; | |
695 | ||
696 | ap->ctl |= ATA_NIEN; | |
697 | ap->last_ctl = ap->ctl; | |
698 | ||
699 | if (ap->flags & ATA_FLAG_MMIO) | |
700 | writeb(ap->ctl, (void __iomem *)ioaddr->ctl_addr); | |
701 | else | |
702 | outb(ap->ctl, ioaddr->ctl_addr); | |
0f0a3ad3 TH |
703 | |
704 | /* Under certain circumstances, some controllers raise IRQ on | |
705 | * ATA_NIEN manipulation. Also, many controllers fail to mask | |
706 | * previously pending IRQ on ATA_NIEN assertion. Clear it. | |
707 | */ | |
708 | ata_chk_status(ap); | |
709 | ||
710 | ap->ops->irq_clear(ap); | |
6d97dbd7 TH |
711 | } |
712 | ||
713 | /** | |
714 | * ata_bmdma_thaw - Thaw BMDMA controller port | |
715 | * @ap: port to thaw | |
716 | * | |
717 | * Thaw BMDMA controller port. | |
718 | * | |
719 | * LOCKING: | |
720 | * Inherited from caller. | |
721 | */ | |
722 | void ata_bmdma_thaw(struct ata_port *ap) | |
723 | { | |
724 | /* clear & re-enable interrupts */ | |
725 | ata_chk_status(ap); | |
726 | ap->ops->irq_clear(ap); | |
727 | if (ap->ioaddr.ctl_addr) /* FIXME: hack. create a hook instead */ | |
728 | ata_irq_on(ap); | |
729 | } | |
730 | ||
731 | /** | |
732 | * ata_bmdma_drive_eh - Perform EH with given methods for BMDMA controller | |
733 | * @ap: port to handle error for | |
f5914a46 | 734 | * @prereset: prereset method (can be NULL) |
6d97dbd7 TH |
735 | * @softreset: softreset method (can be NULL) |
736 | * @hardreset: hardreset method (can be NULL) | |
737 | * @postreset: postreset method (can be NULL) | |
738 | * | |
739 | * Handle error for ATA BMDMA controller. It can handle both | |
740 | * PATA and SATA controllers. Many controllers should be able to | |
741 | * use this EH as-is or with some added handling before and | |
742 | * after. | |
743 | * | |
744 | * This function is intended to be used for constructing | |
745 | * ->error_handler callback by low level drivers. | |
746 | * | |
747 | * LOCKING: | |
748 | * Kernel thread context (may sleep) | |
749 | */ | |
f5914a46 TH |
750 | void ata_bmdma_drive_eh(struct ata_port *ap, ata_prereset_fn_t prereset, |
751 | ata_reset_fn_t softreset, ata_reset_fn_t hardreset, | |
752 | ata_postreset_fn_t postreset) | |
6d97dbd7 | 753 | { |
6d97dbd7 TH |
754 | struct ata_queued_cmd *qc; |
755 | unsigned long flags; | |
756 | int thaw = 0; | |
757 | ||
758 | qc = __ata_qc_from_tag(ap, ap->active_tag); | |
759 | if (qc && !(qc->flags & ATA_QCFLAG_FAILED)) | |
760 | qc = NULL; | |
761 | ||
762 | /* reset PIO HSM and stop DMA engine */ | |
ba6a1308 | 763 | spin_lock_irqsave(ap->lock, flags); |
6d97dbd7 | 764 | |
6d97dbd7 TH |
765 | ap->hsm_task_state = HSM_ST_IDLE; |
766 | ||
767 | if (qc && (qc->tf.protocol == ATA_PROT_DMA || | |
768 | qc->tf.protocol == ATA_PROT_ATAPI_DMA)) { | |
769 | u8 host_stat; | |
770 | ||
fbbb262d | 771 | host_stat = ap->ops->bmdma_status(ap); |
6d97dbd7 | 772 | |
6d97dbd7 TH |
773 | /* BMDMA controllers indicate host bus error by |
774 | * setting DMA_ERR bit and timing out. As it wasn't | |
775 | * really a timeout event, adjust error mask and | |
776 | * cancel frozen state. | |
777 | */ | |
778 | if (qc->err_mask == AC_ERR_TIMEOUT && host_stat & ATA_DMA_ERR) { | |
779 | qc->err_mask = AC_ERR_HOST_BUS; | |
780 | thaw = 1; | |
781 | } | |
782 | ||
783 | ap->ops->bmdma_stop(qc); | |
784 | } | |
785 | ||
786 | ata_altstatus(ap); | |
787 | ata_chk_status(ap); | |
788 | ap->ops->irq_clear(ap); | |
789 | ||
ba6a1308 | 790 | spin_unlock_irqrestore(ap->lock, flags); |
6d97dbd7 TH |
791 | |
792 | if (thaw) | |
793 | ata_eh_thaw_port(ap); | |
794 | ||
795 | /* PIO and DMA engines have been stopped, perform recovery */ | |
f5914a46 | 796 | ata_do_eh(ap, prereset, softreset, hardreset, postreset); |
6d97dbd7 TH |
797 | } |
798 | ||
799 | /** | |
800 | * ata_bmdma_error_handler - Stock error handler for BMDMA controller | |
801 | * @ap: port to handle error for | |
802 | * | |
803 | * Stock error handler for BMDMA controller. | |
804 | * | |
805 | * LOCKING: | |
806 | * Kernel thread context (may sleep) | |
807 | */ | |
808 | void ata_bmdma_error_handler(struct ata_port *ap) | |
809 | { | |
810 | ata_reset_fn_t hardreset; | |
811 | ||
812 | hardreset = NULL; | |
813 | if (sata_scr_valid(ap)) | |
814 | hardreset = sata_std_hardreset; | |
815 | ||
f5914a46 TH |
816 | ata_bmdma_drive_eh(ap, ata_std_prereset, ata_std_softreset, hardreset, |
817 | ata_std_postreset); | |
6d97dbd7 TH |
818 | } |
819 | ||
820 | /** | |
821 | * ata_bmdma_post_internal_cmd - Stock post_internal_cmd for | |
822 | * BMDMA controller | |
823 | * @qc: internal command to clean up | |
824 | * | |
825 | * LOCKING: | |
826 | * Kernel thread context (may sleep) | |
827 | */ | |
828 | void ata_bmdma_post_internal_cmd(struct ata_queued_cmd *qc) | |
829 | { | |
830 | ata_bmdma_stop(qc); | |
831 | } | |
832 | ||
1fdffbce | 833 | #ifdef CONFIG_PCI |
1fdffbce JG |
834 | /** |
835 | * ata_pci_init_native_mode - Initialize native-mode driver | |
836 | * @pdev: pci device to be initialized | |
837 | * @port: array[2] of pointers to port info structures. | |
838 | * @ports: bitmap of ports present | |
839 | * | |
840 | * Utility function which allocates and initializes an | |
841 | * ata_probe_ent structure for a standard dual-port | |
842 | * PIO-based IDE controller. The returned ata_probe_ent | |
843 | * structure can be passed to ata_device_add(). The returned | |
844 | * ata_probe_ent structure should then be freed with kfree(). | |
845 | * | |
846 | * The caller need only pass the address of the primary port, the | |
847 | * secondary will be deduced automatically. If the device has non | |
848 | * standard secondary port mappings this function can be called twice, | |
849 | * once for each interface. | |
850 | */ | |
851 | ||
852 | struct ata_probe_ent * | |
853 | ata_pci_init_native_mode(struct pci_dev *pdev, struct ata_port_info **port, int ports) | |
854 | { | |
855 | struct ata_probe_ent *probe_ent = | |
856 | ata_probe_ent_alloc(pci_dev_to_dev(pdev), port[0]); | |
857 | int p = 0; | |
4e5ec5db | 858 | unsigned long bmdma; |
1fdffbce JG |
859 | |
860 | if (!probe_ent) | |
861 | return NULL; | |
862 | ||
863 | probe_ent->irq = pdev->irq; | |
1d6f359a | 864 | probe_ent->irq_flags = IRQF_SHARED; |
1fdffbce JG |
865 | |
866 | if (ports & ATA_PORT_PRIMARY) { | |
867 | probe_ent->port[p].cmd_addr = pci_resource_start(pdev, 0); | |
868 | probe_ent->port[p].altstatus_addr = | |
869 | probe_ent->port[p].ctl_addr = | |
870 | pci_resource_start(pdev, 1) | ATA_PCI_CTL_OFS; | |
4e5ec5db AC |
871 | bmdma = pci_resource_start(pdev, 4); |
872 | if (bmdma) { | |
873 | if (inb(bmdma + 2) & 0x80) | |
cca3974e | 874 | probe_ent->_host_flags |= ATA_HOST_SIMPLEX; |
4e5ec5db AC |
875 | probe_ent->port[p].bmdma_addr = bmdma; |
876 | } | |
1fdffbce JG |
877 | ata_std_ports(&probe_ent->port[p]); |
878 | p++; | |
879 | } | |
880 | ||
881 | if (ports & ATA_PORT_SECONDARY) { | |
882 | probe_ent->port[p].cmd_addr = pci_resource_start(pdev, 2); | |
883 | probe_ent->port[p].altstatus_addr = | |
884 | probe_ent->port[p].ctl_addr = | |
885 | pci_resource_start(pdev, 3) | ATA_PCI_CTL_OFS; | |
4e5ec5db AC |
886 | bmdma = pci_resource_start(pdev, 4); |
887 | if (bmdma) { | |
888 | bmdma += 8; | |
889 | if(inb(bmdma + 2) & 0x80) | |
cca3974e | 890 | probe_ent->_host_flags |= ATA_HOST_SIMPLEX; |
4e5ec5db AC |
891 | probe_ent->port[p].bmdma_addr = bmdma; |
892 | } | |
1fdffbce | 893 | ata_std_ports(&probe_ent->port[p]); |
fea63e38 | 894 | probe_ent->pinfo2 = port[1]; |
1fdffbce JG |
895 | p++; |
896 | } | |
897 | ||
898 | probe_ent->n_ports = p; | |
899 | return probe_ent; | |
900 | } | |
901 | ||
902 | ||
903 | static struct ata_probe_ent *ata_pci_init_legacy_port(struct pci_dev *pdev, | |
2ec7df04 | 904 | struct ata_port_info **port, int port_mask) |
1fdffbce JG |
905 | { |
906 | struct ata_probe_ent *probe_ent; | |
2ec7df04 AC |
907 | unsigned long bmdma = pci_resource_start(pdev, 4); |
908 | ||
2ec7df04 | 909 | probe_ent = ata_probe_ent_alloc(pci_dev_to_dev(pdev), port[0]); |
1fdffbce JG |
910 | if (!probe_ent) |
911 | return NULL; | |
912 | ||
c4b01f1d | 913 | probe_ent->n_ports = 2; |
8070217d | 914 | probe_ent->irq_flags = IRQF_SHARED; |
2ec7df04 AC |
915 | |
916 | if (port_mask & ATA_PORT_PRIMARY) { | |
daac0acd | 917 | probe_ent->irq = ATA_PRIMARY_IRQ; |
c4b01f1d TH |
918 | probe_ent->port[0].cmd_addr = ATA_PRIMARY_CMD; |
919 | probe_ent->port[0].altstatus_addr = | |
920 | probe_ent->port[0].ctl_addr = ATA_PRIMARY_CTL; | |
2ec7df04 AC |
921 | if (bmdma) { |
922 | probe_ent->port[0].bmdma_addr = bmdma; | |
923 | if (inb(bmdma + 2) & 0x80) | |
cca3974e | 924 | probe_ent->_host_flags |= ATA_HOST_SIMPLEX; |
2ec7df04 | 925 | } |
c4b01f1d TH |
926 | ata_std_ports(&probe_ent->port[0]); |
927 | } else | |
928 | probe_ent->dummy_port_mask |= ATA_PORT_PRIMARY; | |
929 | ||
2ec7df04 | 930 | if (port_mask & ATA_PORT_SECONDARY) { |
c4b01f1d | 931 | if (probe_ent->irq) |
daac0acd | 932 | probe_ent->irq2 = ATA_SECONDARY_IRQ; |
c4b01f1d | 933 | else |
fb463301 | 934 | probe_ent->irq = ATA_SECONDARY_IRQ; |
c4b01f1d TH |
935 | probe_ent->port[1].cmd_addr = ATA_SECONDARY_CMD; |
936 | probe_ent->port[1].altstatus_addr = | |
937 | probe_ent->port[1].ctl_addr = ATA_SECONDARY_CTL; | |
2ec7df04 | 938 | if (bmdma) { |
c4b01f1d | 939 | probe_ent->port[1].bmdma_addr = bmdma + 8; |
2ec7df04 | 940 | if (inb(bmdma + 10) & 0x80) |
cca3974e | 941 | probe_ent->_host_flags |= ATA_HOST_SIMPLEX; |
2ec7df04 | 942 | } |
c4b01f1d | 943 | ata_std_ports(&probe_ent->port[1]); |
d639ca94 JG |
944 | |
945 | /* FIXME: could be pointing to stack area; must copy */ | |
fea63e38 | 946 | probe_ent->pinfo2 = port[1]; |
c4b01f1d TH |
947 | } else |
948 | probe_ent->dummy_port_mask |= ATA_PORT_SECONDARY; | |
1fdffbce JG |
949 | |
950 | return probe_ent; | |
951 | } | |
952 | ||
953 | ||
954 | /** | |
955 | * ata_pci_init_one - Initialize/register PCI IDE host controller | |
956 | * @pdev: Controller to be initialized | |
957 | * @port_info: Information from low-level host driver | |
958 | * @n_ports: Number of ports attached to host controller | |
959 | * | |
960 | * This is a helper function which can be called from a driver's | |
961 | * xxx_init_one() probe function if the hardware uses traditional | |
962 | * IDE taskfile registers. | |
963 | * | |
964 | * This function calls pci_enable_device(), reserves its register | |
965 | * regions, sets the dma mask, enables bus master mode, and calls | |
966 | * ata_device_add() | |
967 | * | |
2ec7df04 AC |
968 | * ASSUMPTION: |
969 | * Nobody makes a single channel controller that appears solely as | |
970 | * the secondary legacy port on PCI. | |
971 | * | |
1fdffbce JG |
972 | * LOCKING: |
973 | * Inherited from PCI layer (may sleep). | |
974 | * | |
975 | * RETURNS: | |
976 | * Zero on success, negative on errno-based value on error. | |
977 | */ | |
978 | ||
979 | int ata_pci_init_one (struct pci_dev *pdev, struct ata_port_info **port_info, | |
980 | unsigned int n_ports) | |
981 | { | |
2ec7df04 | 982 | struct ata_probe_ent *probe_ent = NULL; |
1fdffbce | 983 | struct ata_port_info *port[2]; |
c791c306 | 984 | u8 mask; |
1fdffbce JG |
985 | unsigned int legacy_mode = 0; |
986 | int disable_dev_on_err = 1; | |
987 | int rc; | |
988 | ||
989 | DPRINTK("ENTER\n"); | |
990 | ||
c791c306 JG |
991 | BUG_ON(n_ports < 1 || n_ports > 2); |
992 | ||
1fdffbce JG |
993 | port[0] = port_info[0]; |
994 | if (n_ports > 1) | |
995 | port[1] = port_info[1]; | |
996 | else | |
997 | port[1] = port[0]; | |
998 | ||
1fdffbce JG |
999 | /* FIXME: Really for ATA it isn't safe because the device may be |
1000 | multi-purpose and we want to leave it alone if it was already | |
1001 | enabled. Secondly for shared use as Arjan says we want refcounting | |
1002 | ||
1003 | Checking dev->is_enabled is insufficient as this is not set at | |
1004 | boot for the primary video which is BIOS enabled | |
1005 | */ | |
1006 | ||
1007 | rc = pci_enable_device(pdev); | |
1008 | if (rc) | |
1009 | return rc; | |
1010 | ||
c791c306 JG |
1011 | if ((pdev->class >> 8) == PCI_CLASS_STORAGE_IDE) { |
1012 | u8 tmp8; | |
1013 | ||
1014 | /* TODO: What if one channel is in native mode ... */ | |
1015 | pci_read_config_byte(pdev, PCI_CLASS_PROG, &tmp8); | |
1016 | mask = (1 << 2) | (1 << 0); | |
1017 | if ((tmp8 & mask) != mask) | |
1018 | legacy_mode = (1 << 3); | |
8eb166bf AC |
1019 | #if defined(CONFIG_NO_ATA_LEGACY) |
1020 | /* Some platforms with PCI limits cannot address compat | |
1021 | port space. In that case we punt if their firmware has | |
1022 | left a device in compatibility mode */ | |
1023 | if (legacy_mode) { | |
1024 | printk(KERN_ERR "ata: Compatibility mode ATA is not supported on this platform, skipping.\n"); | |
1025 | return -EOPNOTSUPP; | |
1026 | } | |
1027 | #endif | |
c791c306 JG |
1028 | } |
1029 | ||
1fdffbce JG |
1030 | rc = pci_request_regions(pdev, DRV_NAME); |
1031 | if (rc) { | |
1032 | disable_dev_on_err = 0; | |
1033 | goto err_out; | |
1034 | } | |
1035 | ||
1fdffbce | 1036 | if (legacy_mode) { |
2ec7df04 | 1037 | if (!request_region(ATA_PRIMARY_CMD, 8, "libata")) { |
1fdffbce | 1038 | struct resource *conflict, res; |
2ec7df04 AC |
1039 | res.start = ATA_PRIMARY_CMD; |
1040 | res.end = ATA_PRIMARY_CMD + 8 - 1; | |
1fdffbce | 1041 | conflict = ____request_resource(&ioport_resource, &res); |
cb60736b AP |
1042 | while (conflict->child) |
1043 | conflict = ____request_resource(conflict, &res); | |
1fdffbce | 1044 | if (!strcmp(conflict->name, "libata")) |
2ec7df04 | 1045 | legacy_mode |= ATA_PORT_PRIMARY; |
1fdffbce JG |
1046 | else { |
1047 | disable_dev_on_err = 0; | |
a64f97f2 JG |
1048 | printk(KERN_WARNING "ata: 0x%0X IDE port busy\n" \ |
1049 | "ata: conflict with %s\n", | |
1050 | ATA_PRIMARY_CMD, | |
1051 | conflict->name); | |
1fdffbce JG |
1052 | } |
1053 | } else | |
2ec7df04 | 1054 | legacy_mode |= ATA_PORT_PRIMARY; |
1fdffbce | 1055 | |
2ec7df04 | 1056 | if (!request_region(ATA_SECONDARY_CMD, 8, "libata")) { |
1fdffbce | 1057 | struct resource *conflict, res; |
2ec7df04 AC |
1058 | res.start = ATA_SECONDARY_CMD; |
1059 | res.end = ATA_SECONDARY_CMD + 8 - 1; | |
1fdffbce | 1060 | conflict = ____request_resource(&ioport_resource, &res); |
cb60736b AP |
1061 | while (conflict->child) |
1062 | conflict = ____request_resource(conflict, &res); | |
1fdffbce | 1063 | if (!strcmp(conflict->name, "libata")) |
2ec7df04 | 1064 | legacy_mode |= ATA_PORT_SECONDARY; |
1fdffbce JG |
1065 | else { |
1066 | disable_dev_on_err = 0; | |
a64f97f2 JG |
1067 | printk(KERN_WARNING "ata: 0x%X IDE port busy\n" \ |
1068 | "ata: conflict with %s\n", | |
1069 | ATA_SECONDARY_CMD, | |
1070 | conflict->name); | |
1fdffbce JG |
1071 | } |
1072 | } else | |
2ec7df04 | 1073 | legacy_mode |= ATA_PORT_SECONDARY; |
1fdffbce JG |
1074 | } |
1075 | ||
1076 | /* we have legacy mode, but all ports are unavailable */ | |
1077 | if (legacy_mode == (1 << 3)) { | |
1078 | rc = -EBUSY; | |
1079 | goto err_out_regions; | |
1080 | } | |
1081 | ||
c791c306 | 1082 | /* TODO: If we get no DMA mask we should fall back to PIO */ |
1fdffbce JG |
1083 | rc = pci_set_dma_mask(pdev, ATA_DMA_MASK); |
1084 | if (rc) | |
1085 | goto err_out_regions; | |
1086 | rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK); | |
1087 | if (rc) | |
1088 | goto err_out_regions; | |
1089 | ||
1090 | if (legacy_mode) { | |
2ec7df04 | 1091 | probe_ent = ata_pci_init_legacy_port(pdev, port, legacy_mode); |
1fdffbce JG |
1092 | } else { |
1093 | if (n_ports == 2) | |
1094 | probe_ent = ata_pci_init_native_mode(pdev, port, ATA_PORT_PRIMARY | ATA_PORT_SECONDARY); | |
1095 | else | |
1096 | probe_ent = ata_pci_init_native_mode(pdev, port, ATA_PORT_PRIMARY); | |
1097 | } | |
2ec7df04 | 1098 | if (!probe_ent) { |
1fdffbce JG |
1099 | rc = -ENOMEM; |
1100 | goto err_out_regions; | |
1101 | } | |
1102 | ||
1103 | pci_set_master(pdev); | |
1104 | ||
c791c306 JG |
1105 | if (!ata_device_add(probe_ent)) { |
1106 | rc = -ENODEV; | |
1107 | goto err_out_ent; | |
1108 | } | |
1fdffbce JG |
1109 | |
1110 | kfree(probe_ent); | |
1fdffbce JG |
1111 | |
1112 | return 0; | |
1113 | ||
c791c306 JG |
1114 | err_out_ent: |
1115 | kfree(probe_ent); | |
1fdffbce | 1116 | err_out_regions: |
2ec7df04 AC |
1117 | if (legacy_mode & ATA_PORT_PRIMARY) |
1118 | release_region(ATA_PRIMARY_CMD, 8); | |
1119 | if (legacy_mode & ATA_PORT_SECONDARY) | |
1120 | release_region(ATA_SECONDARY_CMD, 8); | |
1fdffbce JG |
1121 | pci_release_regions(pdev); |
1122 | err_out: | |
1123 | if (disable_dev_on_err) | |
1124 | pci_disable_device(pdev); | |
1125 | return rc; | |
1126 | } | |
1127 | ||
d33d44fa AC |
1128 | /** |
1129 | * ata_pci_clear_simplex - attempt to kick device out of simplex | |
1130 | * @pdev: PCI device | |
1131 | * | |
1132 | * Some PCI ATA devices report simplex mode but in fact can be told to | |
2e9edbf8 | 1133 | * enter non simplex mode. This implements the neccessary logic to |
d33d44fa AC |
1134 | * perform the task on such devices. Calling it on other devices will |
1135 | * have -undefined- behaviour. | |
1136 | */ | |
1137 | ||
1138 | int ata_pci_clear_simplex(struct pci_dev *pdev) | |
1139 | { | |
1140 | unsigned long bmdma = pci_resource_start(pdev, 4); | |
1141 | u8 simplex; | |
1142 | ||
1143 | if (bmdma == 0) | |
1144 | return -ENOENT; | |
1145 | ||
1146 | simplex = inb(bmdma + 0x02); | |
1147 | outb(simplex & 0x60, bmdma + 0x02); | |
1148 | simplex = inb(bmdma + 0x02); | |
1149 | if (simplex & 0x80) | |
1150 | return -EOPNOTSUPP; | |
1151 | return 0; | |
1152 | } | |
1153 | ||
1154 | unsigned long ata_pci_default_filter(const struct ata_port *ap, struct ata_device *adev, unsigned long xfer_mask) | |
1155 | { | |
1156 | /* Filter out DMA modes if the device has been configured by | |
1157 | the BIOS as PIO only */ | |
2e9edbf8 | 1158 | |
d33d44fa AC |
1159 | if (ap->ioaddr.bmdma_addr == 0) |
1160 | xfer_mask &= ~(ATA_MASK_MWDMA | ATA_MASK_UDMA); | |
1161 | return xfer_mask; | |
1162 | } | |
1163 | ||
1fdffbce JG |
1164 | #endif /* CONFIG_PCI */ |
1165 |