libata: initialize port_task when !CONFIG_ATA_SFF
[deliverable/linux.git] / drivers / ata / libata-sff.c
CommitLineData
1fdffbce 1/*
f3a03b09 2 * libata-sff.c - helper library for PCI IDE BMDMA
1fdffbce
JG
3 *
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
7 *
8 * Copyright 2003-2006 Red Hat, Inc. All rights reserved.
9 * Copyright 2003-2006 Jeff Garzik
10 *
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2, or (at your option)
15 * any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; see the file COPYING. If not, write to
24 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
25 *
26 *
27 * libata documentation is available via 'make {ps|pdf}docs',
28 * as Documentation/DocBook/libata.*
29 *
30 * Hardware documentation available from http://www.t13.org/ and
31 * http://www.sata-io.org/
32 *
33 */
34
1fdffbce
JG
35#include <linux/kernel.h>
36#include <linux/pci.h>
37#include <linux/libata.h>
624d5c51 38#include <linux/highmem.h>
1fdffbce
JG
39
40#include "libata.h"
41
624d5c51
TH
42const struct ata_port_operations ata_sff_port_ops = {
43 .inherits = &ata_base_port_ops,
44
9363c382
TH
45 .qc_prep = ata_sff_qc_prep,
46 .qc_issue = ata_sff_qc_issue,
4c9bf4e7 47 .qc_fill_rtf = ata_sff_qc_fill_rtf,
9363c382
TH
48
49 .freeze = ata_sff_freeze,
50 .thaw = ata_sff_thaw,
0aa1113d 51 .prereset = ata_sff_prereset,
9363c382 52 .softreset = ata_sff_softreset,
57c9efdf 53 .hardreset = sata_sff_hardreset,
203c75b8 54 .postreset = ata_sff_postreset,
9363c382
TH
55 .error_handler = ata_sff_error_handler,
56 .post_internal_cmd = ata_sff_post_internal_cmd,
57
5682ed33
TH
58 .sff_dev_select = ata_sff_dev_select,
59 .sff_check_status = ata_sff_check_status,
60 .sff_tf_load = ata_sff_tf_load,
61 .sff_tf_read = ata_sff_tf_read,
62 .sff_exec_command = ata_sff_exec_command,
63 .sff_data_xfer = ata_sff_data_xfer,
64 .sff_irq_on = ata_sff_irq_on,
288623a0 65 .sff_irq_clear = ata_sff_irq_clear,
624d5c51
TH
66
67 .port_start = ata_sff_port_start,
68};
69
70const struct ata_port_operations ata_bmdma_port_ops = {
71 .inherits = &ata_sff_port_ops,
72
9363c382 73 .mode_filter = ata_bmdma_mode_filter,
624d5c51
TH
74
75 .bmdma_setup = ata_bmdma_setup,
76 .bmdma_start = ata_bmdma_start,
77 .bmdma_stop = ata_bmdma_stop,
78 .bmdma_status = ata_bmdma_status,
624d5c51
TH
79};
80
81/**
82 * ata_fill_sg - Fill PCI IDE PRD table
83 * @qc: Metadata associated with taskfile to be transferred
84 *
85 * Fill PCI IDE PRD (scatter-gather) table with segments
86 * associated with the current disk command.
87 *
88 * LOCKING:
89 * spin_lock_irqsave(host lock)
90 *
91 */
92static void ata_fill_sg(struct ata_queued_cmd *qc)
93{
94 struct ata_port *ap = qc->ap;
95 struct scatterlist *sg;
96 unsigned int si, pi;
97
98 pi = 0;
99 for_each_sg(qc->sg, sg, qc->n_elem, si) {
100 u32 addr, offset;
101 u32 sg_len, len;
102
103 /* determine if physical DMA addr spans 64K boundary.
104 * Note h/w doesn't support 64-bit, so we unconditionally
105 * truncate dma_addr_t to u32.
106 */
107 addr = (u32) sg_dma_address(sg);
108 sg_len = sg_dma_len(sg);
109
110 while (sg_len) {
111 offset = addr & 0xffff;
112 len = sg_len;
113 if ((offset + sg_len) > 0x10000)
114 len = 0x10000 - offset;
115
116 ap->prd[pi].addr = cpu_to_le32(addr);
117 ap->prd[pi].flags_len = cpu_to_le32(len & 0xffff);
118 VPRINTK("PRD[%u] = (0x%X, 0x%X)\n", pi, addr, len);
119
120 pi++;
121 sg_len -= len;
122 addr += len;
123 }
124 }
125
126 ap->prd[pi - 1].flags_len |= cpu_to_le32(ATA_PRD_EOT);
127}
128
129/**
130 * ata_fill_sg_dumb - Fill PCI IDE PRD table
131 * @qc: Metadata associated with taskfile to be transferred
132 *
133 * Fill PCI IDE PRD (scatter-gather) table with segments
134 * associated with the current disk command. Perform the fill
135 * so that we avoid writing any length 64K records for
136 * controllers that don't follow the spec.
137 *
138 * LOCKING:
139 * spin_lock_irqsave(host lock)
140 *
141 */
142static void ata_fill_sg_dumb(struct ata_queued_cmd *qc)
143{
144 struct ata_port *ap = qc->ap;
145 struct scatterlist *sg;
146 unsigned int si, pi;
147
148 pi = 0;
149 for_each_sg(qc->sg, sg, qc->n_elem, si) {
150 u32 addr, offset;
151 u32 sg_len, len, blen;
152
153 /* determine if physical DMA addr spans 64K boundary.
154 * Note h/w doesn't support 64-bit, so we unconditionally
155 * truncate dma_addr_t to u32.
156 */
157 addr = (u32) sg_dma_address(sg);
158 sg_len = sg_dma_len(sg);
159
160 while (sg_len) {
161 offset = addr & 0xffff;
162 len = sg_len;
163 if ((offset + sg_len) > 0x10000)
164 len = 0x10000 - offset;
165
166 blen = len & 0xffff;
167 ap->prd[pi].addr = cpu_to_le32(addr);
168 if (blen == 0) {
169 /* Some PATA chipsets like the CS5530 can't
170 cope with 0x0000 meaning 64K as the spec says */
171 ap->prd[pi].flags_len = cpu_to_le32(0x8000);
172 blen = 0x8000;
173 ap->prd[++pi].addr = cpu_to_le32(addr + 0x8000);
174 }
175 ap->prd[pi].flags_len = cpu_to_le32(blen);
176 VPRINTK("PRD[%u] = (0x%X, 0x%X)\n", pi, addr, len);
177
178 pi++;
179 sg_len -= len;
180 addr += len;
181 }
182 }
183
184 ap->prd[pi - 1].flags_len |= cpu_to_le32(ATA_PRD_EOT);
185}
186
187/**
9363c382 188 * ata_sff_qc_prep - Prepare taskfile for submission
624d5c51
TH
189 * @qc: Metadata associated with taskfile to be prepared
190 *
191 * Prepare ATA taskfile for submission.
192 *
193 * LOCKING:
194 * spin_lock_irqsave(host lock)
195 */
9363c382 196void ata_sff_qc_prep(struct ata_queued_cmd *qc)
624d5c51
TH
197{
198 if (!(qc->flags & ATA_QCFLAG_DMAMAP))
199 return;
200
201 ata_fill_sg(qc);
202}
203
204/**
9363c382 205 * ata_sff_dumb_qc_prep - Prepare taskfile for submission
624d5c51
TH
206 * @qc: Metadata associated with taskfile to be prepared
207 *
208 * Prepare ATA taskfile for submission.
209 *
210 * LOCKING:
211 * spin_lock_irqsave(host lock)
212 */
9363c382 213void ata_sff_dumb_qc_prep(struct ata_queued_cmd *qc)
624d5c51
TH
214{
215 if (!(qc->flags & ATA_QCFLAG_DMAMAP))
216 return;
217
218 ata_fill_sg_dumb(qc);
219}
220
272f7884 221/**
9363c382 222 * ata_sff_check_status - Read device status reg & clear interrupt
272f7884
TH
223 * @ap: port where the device is
224 *
225 * Reads ATA taskfile status register for currently-selected device
226 * and return its value. This also clears pending interrupts
227 * from this device
228 *
229 * LOCKING:
230 * Inherited from caller.
231 */
9363c382 232u8 ata_sff_check_status(struct ata_port *ap)
272f7884
TH
233{
234 return ioread8(ap->ioaddr.status_addr);
235}
236
237/**
9363c382 238 * ata_sff_altstatus - Read device alternate status reg
272f7884
TH
239 * @ap: port where the device is
240 *
241 * Reads ATA taskfile alternate status register for
242 * currently-selected device and return its value.
243 *
244 * Note: may NOT be used as the check_altstatus() entry in
245 * ata_port_operations.
246 *
247 * LOCKING:
248 * Inherited from caller.
249 */
a57c1bad 250static u8 ata_sff_altstatus(struct ata_port *ap)
624d5c51 251{
5682ed33
TH
252 if (ap->ops->sff_check_altstatus)
253 return ap->ops->sff_check_altstatus(ap);
624d5c51
TH
254
255 return ioread8(ap->ioaddr.altstatus_addr);
256}
257
a57c1bad
AC
258/**
259 * ata_sff_irq_status - Check if the device is busy
260 * @ap: port where the device is
261 *
262 * Determine if the port is currently busy. Uses altstatus
263 * if available in order to avoid clearing shared IRQ status
264 * when finding an IRQ source. Non ctl capable devices don't
265 * share interrupt lines fortunately for us.
266 *
267 * LOCKING:
268 * Inherited from caller.
269 */
270static u8 ata_sff_irq_status(struct ata_port *ap)
271{
272 u8 status;
273
274 if (ap->ops->sff_check_altstatus || ap->ioaddr.altstatus_addr) {
275 status = ata_sff_altstatus(ap);
276 /* Not us: We are busy */
277 if (status & ATA_BUSY)
278 return status;
279 }
280 /* Clear INTRQ latch */
6311c90a 281 status = ap->ops->sff_check_status(ap);
a57c1bad
AC
282 return status;
283}
284
285/**
286 * ata_sff_sync - Flush writes
287 * @ap: Port to wait for.
288 *
289 * CAUTION:
290 * If we have an mmio device with no ctl and no altstatus
291 * method this will fail. No such devices are known to exist.
292 *
293 * LOCKING:
294 * Inherited from caller.
295 */
296
297static void ata_sff_sync(struct ata_port *ap)
298{
299 if (ap->ops->sff_check_altstatus)
300 ap->ops->sff_check_altstatus(ap);
301 else if (ap->ioaddr.altstatus_addr)
302 ioread8(ap->ioaddr.altstatus_addr);
303}
304
305/**
306 * ata_sff_pause - Flush writes and wait 400nS
307 * @ap: Port to pause for.
308 *
309 * CAUTION:
310 * If we have an mmio device with no ctl and no altstatus
311 * method this will fail. No such devices are known to exist.
312 *
313 * LOCKING:
314 * Inherited from caller.
315 */
316
317void ata_sff_pause(struct ata_port *ap)
318{
319 ata_sff_sync(ap);
320 ndelay(400);
321}
322
323/**
324 * ata_sff_dma_pause - Pause before commencing DMA
325 * @ap: Port to pause for.
326 *
327 * Perform I/O fencing and ensure sufficient cycle delays occur
328 * for the HDMA1:0 transition
329 */
330
331void ata_sff_dma_pause(struct ata_port *ap)
332{
333 if (ap->ops->sff_check_altstatus || ap->ioaddr.altstatus_addr) {
334 /* An altstatus read will cause the needed delay without
335 messing up the IRQ status */
336 ata_sff_altstatus(ap);
337 return;
338 }
339 /* There are no DMA controllers without ctl. BUG here to ensure
340 we never violate the HDMA1:0 transition timing and risk
341 corruption. */
342 BUG();
343}
344
624d5c51 345/**
9363c382 346 * ata_sff_busy_sleep - sleep until BSY clears, or timeout
624d5c51 347 * @ap: port containing status register to be polled
341c2c95
TH
348 * @tmout_pat: impatience timeout in msecs
349 * @tmout: overall timeout in msecs
624d5c51
TH
350 *
351 * Sleep until ATA Status register bit BSY clears,
352 * or a timeout occurs.
353 *
354 * LOCKING:
355 * Kernel thread context (may sleep).
356 *
357 * RETURNS:
358 * 0 on success, -errno otherwise.
359 */
9363c382
TH
360int ata_sff_busy_sleep(struct ata_port *ap,
361 unsigned long tmout_pat, unsigned long tmout)
624d5c51
TH
362{
363 unsigned long timer_start, timeout;
364 u8 status;
365
9363c382 366 status = ata_sff_busy_wait(ap, ATA_BUSY, 300);
624d5c51 367 timer_start = jiffies;
341c2c95 368 timeout = ata_deadline(timer_start, tmout_pat);
624d5c51
TH
369 while (status != 0xff && (status & ATA_BUSY) &&
370 time_before(jiffies, timeout)) {
371 msleep(50);
9363c382 372 status = ata_sff_busy_wait(ap, ATA_BUSY, 3);
624d5c51
TH
373 }
374
375 if (status != 0xff && (status & ATA_BUSY))
376 ata_port_printk(ap, KERN_WARNING,
377 "port is slow to respond, please be patient "
378 "(Status 0x%x)\n", status);
379
341c2c95 380 timeout = ata_deadline(timer_start, tmout);
624d5c51
TH
381 while (status != 0xff && (status & ATA_BUSY) &&
382 time_before(jiffies, timeout)) {
383 msleep(50);
5682ed33 384 status = ap->ops->sff_check_status(ap);
624d5c51
TH
385 }
386
387 if (status == 0xff)
388 return -ENODEV;
389
390 if (status & ATA_BUSY) {
391 ata_port_printk(ap, KERN_ERR, "port failed to respond "
392 "(%lu secs, Status 0x%x)\n",
341c2c95 393 DIV_ROUND_UP(tmout, 1000), status);
624d5c51
TH
394 return -EBUSY;
395 }
396
397 return 0;
398}
399
aa2731ad
TH
400static int ata_sff_check_ready(struct ata_link *link)
401{
402 u8 status = link->ap->ops->sff_check_status(link->ap);
403
78ab88f0 404 return ata_check_ready(status);
aa2731ad
TH
405}
406
624d5c51 407/**
9363c382 408 * ata_sff_wait_ready - sleep until BSY clears, or timeout
705e76be 409 * @link: SFF link to wait ready status for
624d5c51
TH
410 * @deadline: deadline jiffies for the operation
411 *
412 * Sleep until ATA Status register bit BSY clears, or timeout
413 * occurs.
414 *
415 * LOCKING:
416 * Kernel thread context (may sleep).
417 *
418 * RETURNS:
419 * 0 on success, -errno otherwise.
420 */
705e76be 421int ata_sff_wait_ready(struct ata_link *link, unsigned long deadline)
624d5c51 422{
aa2731ad 423 return ata_wait_ready(link, deadline, ata_sff_check_ready);
624d5c51
TH
424}
425
426/**
9363c382 427 * ata_sff_dev_select - Select device 0/1 on ATA bus
624d5c51
TH
428 * @ap: ATA channel to manipulate
429 * @device: ATA device (numbered from zero) to select
430 *
431 * Use the method defined in the ATA specification to
432 * make either device 0, or device 1, active on the
433 * ATA channel. Works with both PIO and MMIO.
434 *
435 * May be used as the dev_select() entry in ata_port_operations.
436 *
437 * LOCKING:
438 * caller.
439 */
9363c382 440void ata_sff_dev_select(struct ata_port *ap, unsigned int device)
624d5c51
TH
441{
442 u8 tmp;
443
444 if (device == 0)
445 tmp = ATA_DEVICE_OBS;
446 else
447 tmp = ATA_DEVICE_OBS | ATA_DEV1;
448
449 iowrite8(tmp, ap->ioaddr.device_addr);
9363c382 450 ata_sff_pause(ap); /* needed; also flushes, for mmio */
624d5c51
TH
451}
452
453/**
454 * ata_dev_select - Select device 0/1 on ATA bus
455 * @ap: ATA channel to manipulate
456 * @device: ATA device (numbered from zero) to select
457 * @wait: non-zero to wait for Status register BSY bit to clear
458 * @can_sleep: non-zero if context allows sleeping
459 *
460 * Use the method defined in the ATA specification to
461 * make either device 0, or device 1, active on the
462 * ATA channel.
463 *
9363c382
TH
464 * This is a high-level version of ata_sff_dev_select(), which
465 * additionally provides the services of inserting the proper
466 * pauses and status polling, where needed.
624d5c51
TH
467 *
468 * LOCKING:
469 * caller.
470 */
471void ata_dev_select(struct ata_port *ap, unsigned int device,
472 unsigned int wait, unsigned int can_sleep)
473{
474 if (ata_msg_probe(ap))
475 ata_port_printk(ap, KERN_INFO, "ata_dev_select: ENTER, "
476 "device %u, wait %u\n", device, wait);
477
478 if (wait)
479 ata_wait_idle(ap);
480
5682ed33 481 ap->ops->sff_dev_select(ap, device);
624d5c51
TH
482
483 if (wait) {
484 if (can_sleep && ap->link.device[device].class == ATA_DEV_ATAPI)
485 msleep(150);
486 ata_wait_idle(ap);
487 }
488}
489
490/**
9363c382 491 * ata_sff_irq_on - Enable interrupts on a port.
624d5c51
TH
492 * @ap: Port on which interrupts are enabled.
493 *
494 * Enable interrupts on a legacy IDE device using MMIO or PIO,
495 * wait for idle, clear any pending interrupts.
496 *
497 * LOCKING:
498 * Inherited from caller.
499 */
9363c382 500u8 ata_sff_irq_on(struct ata_port *ap)
624d5c51
TH
501{
502 struct ata_ioports *ioaddr = &ap->ioaddr;
503 u8 tmp;
504
505 ap->ctl &= ~ATA_NIEN;
506 ap->last_ctl = ap->ctl;
507
508 if (ioaddr->ctl_addr)
509 iowrite8(ap->ctl, ioaddr->ctl_addr);
510 tmp = ata_wait_idle(ap);
511
5682ed33 512 ap->ops->sff_irq_clear(ap);
624d5c51
TH
513
514 return tmp;
515}
516
517/**
9363c382 518 * ata_sff_irq_clear - Clear PCI IDE BMDMA interrupt.
624d5c51
TH
519 * @ap: Port associated with this ATA transaction.
520 *
521 * Clear interrupt and error flags in DMA status register.
522 *
523 * May be used as the irq_clear() entry in ata_port_operations.
524 *
525 * LOCKING:
526 * spin_lock_irqsave(host lock)
527 */
9363c382 528void ata_sff_irq_clear(struct ata_port *ap)
624d5c51
TH
529{
530 void __iomem *mmio = ap->ioaddr.bmdma_addr;
531
532 if (!mmio)
533 return;
534
535 iowrite8(ioread8(mmio + ATA_DMA_STATUS), mmio + ATA_DMA_STATUS);
536}
537
538/**
9363c382 539 * ata_sff_tf_load - send taskfile registers to host controller
624d5c51
TH
540 * @ap: Port to which output is sent
541 * @tf: ATA taskfile register set
542 *
543 * Outputs ATA taskfile to standard ATA host controller.
544 *
545 * LOCKING:
546 * Inherited from caller.
547 */
9363c382 548void ata_sff_tf_load(struct ata_port *ap, const struct ata_taskfile *tf)
624d5c51
TH
549{
550 struct ata_ioports *ioaddr = &ap->ioaddr;
551 unsigned int is_addr = tf->flags & ATA_TFLAG_ISADDR;
552
553 if (tf->ctl != ap->last_ctl) {
554 if (ioaddr->ctl_addr)
555 iowrite8(tf->ctl, ioaddr->ctl_addr);
556 ap->last_ctl = tf->ctl;
557 ata_wait_idle(ap);
558 }
559
560 if (is_addr && (tf->flags & ATA_TFLAG_LBA48)) {
561 WARN_ON(!ioaddr->ctl_addr);
562 iowrite8(tf->hob_feature, ioaddr->feature_addr);
563 iowrite8(tf->hob_nsect, ioaddr->nsect_addr);
564 iowrite8(tf->hob_lbal, ioaddr->lbal_addr);
565 iowrite8(tf->hob_lbam, ioaddr->lbam_addr);
566 iowrite8(tf->hob_lbah, ioaddr->lbah_addr);
567 VPRINTK("hob: feat 0x%X nsect 0x%X, lba 0x%X 0x%X 0x%X\n",
568 tf->hob_feature,
569 tf->hob_nsect,
570 tf->hob_lbal,
571 tf->hob_lbam,
572 tf->hob_lbah);
573 }
574
575 if (is_addr) {
576 iowrite8(tf->feature, ioaddr->feature_addr);
577 iowrite8(tf->nsect, ioaddr->nsect_addr);
578 iowrite8(tf->lbal, ioaddr->lbal_addr);
579 iowrite8(tf->lbam, ioaddr->lbam_addr);
580 iowrite8(tf->lbah, ioaddr->lbah_addr);
581 VPRINTK("feat 0x%X nsect 0x%X lba 0x%X 0x%X 0x%X\n",
582 tf->feature,
583 tf->nsect,
584 tf->lbal,
585 tf->lbam,
586 tf->lbah);
587 }
588
589 if (tf->flags & ATA_TFLAG_DEVICE) {
590 iowrite8(tf->device, ioaddr->device_addr);
591 VPRINTK("device 0x%X\n", tf->device);
592 }
593
594 ata_wait_idle(ap);
595}
596
597/**
9363c382 598 * ata_sff_tf_read - input device's ATA taskfile shadow registers
624d5c51
TH
599 * @ap: Port from which input is read
600 * @tf: ATA taskfile register set for storing input
601 *
602 * Reads ATA taskfile registers for currently-selected device
603 * into @tf. Assumes the device has a fully SFF compliant task file
604 * layout and behaviour. If you device does not (eg has a different
605 * status method) then you will need to provide a replacement tf_read
606 *
607 * LOCKING:
608 * Inherited from caller.
609 */
9363c382 610void ata_sff_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
624d5c51
TH
611{
612 struct ata_ioports *ioaddr = &ap->ioaddr;
613
9363c382 614 tf->command = ata_sff_check_status(ap);
624d5c51
TH
615 tf->feature = ioread8(ioaddr->error_addr);
616 tf->nsect = ioread8(ioaddr->nsect_addr);
617 tf->lbal = ioread8(ioaddr->lbal_addr);
618 tf->lbam = ioread8(ioaddr->lbam_addr);
619 tf->lbah = ioread8(ioaddr->lbah_addr);
620 tf->device = ioread8(ioaddr->device_addr);
621
622 if (tf->flags & ATA_TFLAG_LBA48) {
623 if (likely(ioaddr->ctl_addr)) {
624 iowrite8(tf->ctl | ATA_HOB, ioaddr->ctl_addr);
625 tf->hob_feature = ioread8(ioaddr->error_addr);
626 tf->hob_nsect = ioread8(ioaddr->nsect_addr);
627 tf->hob_lbal = ioread8(ioaddr->lbal_addr);
628 tf->hob_lbam = ioread8(ioaddr->lbam_addr);
629 tf->hob_lbah = ioread8(ioaddr->lbah_addr);
630 iowrite8(tf->ctl, ioaddr->ctl_addr);
631 ap->last_ctl = tf->ctl;
632 } else
633 WARN_ON(1);
634 }
635}
636
637/**
9363c382 638 * ata_sff_exec_command - issue ATA command to host controller
624d5c51
TH
639 * @ap: port to which command is being issued
640 * @tf: ATA taskfile register set
641 *
642 * Issues ATA command, with proper synchronization with interrupt
643 * handler / other threads.
644 *
645 * LOCKING:
646 * spin_lock_irqsave(host lock)
647 */
9363c382 648void ata_sff_exec_command(struct ata_port *ap, const struct ata_taskfile *tf)
624d5c51
TH
649{
650 DPRINTK("ata%u: cmd 0x%X\n", ap->print_id, tf->command);
651
652 iowrite8(tf->command, ap->ioaddr.command_addr);
9363c382 653 ata_sff_pause(ap);
624d5c51
TH
654}
655
656/**
657 * ata_tf_to_host - issue ATA taskfile to host controller
658 * @ap: port to which command is being issued
659 * @tf: ATA taskfile register set
660 *
661 * Issues ATA taskfile register set to ATA host controller,
662 * with proper synchronization with interrupt handler and
663 * other threads.
664 *
665 * LOCKING:
666 * spin_lock_irqsave(host lock)
667 */
668static inline void ata_tf_to_host(struct ata_port *ap,
669 const struct ata_taskfile *tf)
670{
5682ed33
TH
671 ap->ops->sff_tf_load(ap, tf);
672 ap->ops->sff_exec_command(ap, tf);
624d5c51
TH
673}
674
675/**
9363c382 676 * ata_sff_data_xfer - Transfer data by PIO
624d5c51
TH
677 * @dev: device to target
678 * @buf: data buffer
679 * @buflen: buffer length
680 * @rw: read/write
681 *
682 * Transfer data from/to the device data register by PIO.
683 *
684 * LOCKING:
685 * Inherited from caller.
686 *
687 * RETURNS:
688 * Bytes consumed.
689 */
9363c382
TH
690unsigned int ata_sff_data_xfer(struct ata_device *dev, unsigned char *buf,
691 unsigned int buflen, int rw)
624d5c51
TH
692{
693 struct ata_port *ap = dev->link->ap;
694 void __iomem *data_addr = ap->ioaddr.data_addr;
695 unsigned int words = buflen >> 1;
696
697 /* Transfer multiple of 2 bytes */
698 if (rw == READ)
699 ioread16_rep(data_addr, buf, words);
700 else
701 iowrite16_rep(data_addr, buf, words);
702
703 /* Transfer trailing 1 byte, if any. */
704 if (unlikely(buflen & 0x01)) {
705 __le16 align_buf[1] = { 0 };
706 unsigned char *trailing_buf = buf + buflen - 1;
707
708 if (rw == READ) {
709 align_buf[0] = cpu_to_le16(ioread16(data_addr));
710 memcpy(trailing_buf, align_buf, 1);
711 } else {
712 memcpy(align_buf, trailing_buf, 1);
713 iowrite16(le16_to_cpu(align_buf[0]), data_addr);
714 }
715 words++;
716 }
717
718 return words << 1;
719}
720
721/**
9363c382 722 * ata_sff_data_xfer_noirq - Transfer data by PIO
624d5c51
TH
723 * @dev: device to target
724 * @buf: data buffer
725 * @buflen: buffer length
726 * @rw: read/write
727 *
728 * Transfer data from/to the device data register by PIO. Do the
729 * transfer with interrupts disabled.
730 *
731 * LOCKING:
732 * Inherited from caller.
733 *
734 * RETURNS:
735 * Bytes consumed.
736 */
9363c382
TH
737unsigned int ata_sff_data_xfer_noirq(struct ata_device *dev, unsigned char *buf,
738 unsigned int buflen, int rw)
624d5c51
TH
739{
740 unsigned long flags;
741 unsigned int consumed;
742
743 local_irq_save(flags);
9363c382 744 consumed = ata_sff_data_xfer(dev, buf, buflen, rw);
624d5c51
TH
745 local_irq_restore(flags);
746
747 return consumed;
748}
749
750/**
751 * ata_pio_sector - Transfer a sector of data.
752 * @qc: Command on going
753 *
754 * Transfer qc->sect_size bytes of data from/to the ATA device.
755 *
756 * LOCKING:
757 * Inherited from caller.
758 */
759static void ata_pio_sector(struct ata_queued_cmd *qc)
760{
761 int do_write = (qc->tf.flags & ATA_TFLAG_WRITE);
762 struct ata_port *ap = qc->ap;
763 struct page *page;
764 unsigned int offset;
765 unsigned char *buf;
766
767 if (qc->curbytes == qc->nbytes - qc->sect_size)
768 ap->hsm_task_state = HSM_ST_LAST;
769
770 page = sg_page(qc->cursg);
771 offset = qc->cursg->offset + qc->cursg_ofs;
772
773 /* get the current page and offset */
774 page = nth_page(page, (offset >> PAGE_SHIFT));
775 offset %= PAGE_SIZE;
776
777 DPRINTK("data %s\n", qc->tf.flags & ATA_TFLAG_WRITE ? "write" : "read");
778
779 if (PageHighMem(page)) {
780 unsigned long flags;
781
782 /* FIXME: use a bounce buffer */
783 local_irq_save(flags);
784 buf = kmap_atomic(page, KM_IRQ0);
785
786 /* do the actual data transfer */
5682ed33
TH
787 ap->ops->sff_data_xfer(qc->dev, buf + offset, qc->sect_size,
788 do_write);
624d5c51
TH
789
790 kunmap_atomic(buf, KM_IRQ0);
791 local_irq_restore(flags);
792 } else {
793 buf = page_address(page);
5682ed33
TH
794 ap->ops->sff_data_xfer(qc->dev, buf + offset, qc->sect_size,
795 do_write);
624d5c51
TH
796 }
797
798 qc->curbytes += qc->sect_size;
799 qc->cursg_ofs += qc->sect_size;
800
801 if (qc->cursg_ofs == qc->cursg->length) {
802 qc->cursg = sg_next(qc->cursg);
803 qc->cursg_ofs = 0;
804 }
805}
806
807/**
808 * ata_pio_sectors - Transfer one or many sectors.
809 * @qc: Command on going
810 *
811 * Transfer one or many sectors of data from/to the
812 * ATA device for the DRQ request.
813 *
814 * LOCKING:
815 * Inherited from caller.
816 */
817static void ata_pio_sectors(struct ata_queued_cmd *qc)
818{
819 if (is_multi_taskfile(&qc->tf)) {
820 /* READ/WRITE MULTIPLE */
821 unsigned int nsect;
822
823 WARN_ON(qc->dev->multi_count == 0);
824
825 nsect = min((qc->nbytes - qc->curbytes) / qc->sect_size,
826 qc->dev->multi_count);
827 while (nsect--)
828 ata_pio_sector(qc);
829 } else
830 ata_pio_sector(qc);
831
a57c1bad 832 ata_sff_sync(qc->ap); /* flush */
624d5c51
TH
833}
834
835/**
836 * atapi_send_cdb - Write CDB bytes to hardware
837 * @ap: Port to which ATAPI device is attached.
838 * @qc: Taskfile currently active
839 *
840 * When device has indicated its readiness to accept
841 * a CDB, this function is called. Send the CDB.
842 *
843 * LOCKING:
844 * caller.
845 */
846static void atapi_send_cdb(struct ata_port *ap, struct ata_queued_cmd *qc)
847{
848 /* send SCSI cdb */
849 DPRINTK("send cdb\n");
850 WARN_ON(qc->dev->cdb_len < 12);
851
5682ed33 852 ap->ops->sff_data_xfer(qc->dev, qc->cdb, qc->dev->cdb_len, 1);
a57c1bad
AC
853 ata_sff_sync(ap);
854 /* FIXME: If the CDB is for DMA do we need to do the transition delay
855 or is bmdma_start guaranteed to do it ? */
624d5c51
TH
856 switch (qc->tf.protocol) {
857 case ATAPI_PROT_PIO:
858 ap->hsm_task_state = HSM_ST;
859 break;
860 case ATAPI_PROT_NODATA:
861 ap->hsm_task_state = HSM_ST_LAST;
862 break;
863 case ATAPI_PROT_DMA:
864 ap->hsm_task_state = HSM_ST_LAST;
865 /* initiate bmdma */
866 ap->ops->bmdma_start(qc);
867 break;
868 }
869}
870
871/**
872 * __atapi_pio_bytes - Transfer data from/to the ATAPI device.
873 * @qc: Command on going
874 * @bytes: number of bytes
875 *
876 * Transfer Transfer data from/to the ATAPI device.
877 *
878 * LOCKING:
879 * Inherited from caller.
880 *
881 */
882static int __atapi_pio_bytes(struct ata_queued_cmd *qc, unsigned int bytes)
883{
884 int rw = (qc->tf.flags & ATA_TFLAG_WRITE) ? WRITE : READ;
885 struct ata_port *ap = qc->ap;
886 struct ata_device *dev = qc->dev;
887 struct ata_eh_info *ehi = &dev->link->eh_info;
888 struct scatterlist *sg;
889 struct page *page;
890 unsigned char *buf;
891 unsigned int offset, count, consumed;
892
893next_sg:
894 sg = qc->cursg;
895 if (unlikely(!sg)) {
896 ata_ehi_push_desc(ehi, "unexpected or too much trailing data "
897 "buf=%u cur=%u bytes=%u",
898 qc->nbytes, qc->curbytes, bytes);
899 return -1;
900 }
901
902 page = sg_page(sg);
903 offset = sg->offset + qc->cursg_ofs;
904
905 /* get the current page and offset */
906 page = nth_page(page, (offset >> PAGE_SHIFT));
907 offset %= PAGE_SIZE;
908
909 /* don't overrun current sg */
910 count = min(sg->length - qc->cursg_ofs, bytes);
911
912 /* don't cross page boundaries */
913 count = min(count, (unsigned int)PAGE_SIZE - offset);
914
915 DPRINTK("data %s\n", qc->tf.flags & ATA_TFLAG_WRITE ? "write" : "read");
916
917 if (PageHighMem(page)) {
918 unsigned long flags;
919
920 /* FIXME: use bounce buffer */
921 local_irq_save(flags);
922 buf = kmap_atomic(page, KM_IRQ0);
923
924 /* do the actual data transfer */
5682ed33 925 consumed = ap->ops->sff_data_xfer(dev, buf + offset, count, rw);
624d5c51
TH
926
927 kunmap_atomic(buf, KM_IRQ0);
928 local_irq_restore(flags);
929 } else {
930 buf = page_address(page);
5682ed33 931 consumed = ap->ops->sff_data_xfer(dev, buf + offset, count, rw);
624d5c51
TH
932 }
933
934 bytes -= min(bytes, consumed);
935 qc->curbytes += count;
936 qc->cursg_ofs += count;
937
938 if (qc->cursg_ofs == sg->length) {
939 qc->cursg = sg_next(qc->cursg);
940 qc->cursg_ofs = 0;
941 }
942
943 /* consumed can be larger than count only for the last transfer */
944 WARN_ON(qc->cursg && count != consumed);
945
946 if (bytes)
947 goto next_sg;
948 return 0;
949}
950
951/**
952 * atapi_pio_bytes - Transfer data from/to the ATAPI device.
953 * @qc: Command on going
954 *
955 * Transfer Transfer data from/to the ATAPI device.
956 *
957 * LOCKING:
958 * Inherited from caller.
959 */
960static void atapi_pio_bytes(struct ata_queued_cmd *qc)
961{
962 struct ata_port *ap = qc->ap;
963 struct ata_device *dev = qc->dev;
964 struct ata_eh_info *ehi = &dev->link->eh_info;
965 unsigned int ireason, bc_lo, bc_hi, bytes;
966 int i_write, do_write = (qc->tf.flags & ATA_TFLAG_WRITE) ? 1 : 0;
967
968 /* Abuse qc->result_tf for temp storage of intermediate TF
969 * here to save some kernel stack usage.
970 * For normal completion, qc->result_tf is not relevant. For
971 * error, qc->result_tf is later overwritten by ata_qc_complete().
972 * So, the correctness of qc->result_tf is not affected.
973 */
5682ed33 974 ap->ops->sff_tf_read(ap, &qc->result_tf);
624d5c51
TH
975 ireason = qc->result_tf.nsect;
976 bc_lo = qc->result_tf.lbam;
977 bc_hi = qc->result_tf.lbah;
978 bytes = (bc_hi << 8) | bc_lo;
979
980 /* shall be cleared to zero, indicating xfer of data */
981 if (unlikely(ireason & (1 << 0)))
982 goto atapi_check;
983
984 /* make sure transfer direction matches expected */
985 i_write = ((ireason & (1 << 1)) == 0) ? 1 : 0;
986 if (unlikely(do_write != i_write))
987 goto atapi_check;
988
989 if (unlikely(!bytes))
990 goto atapi_check;
991
992 VPRINTK("ata%u: xfering %d bytes\n", ap->print_id, bytes);
993
994 if (unlikely(__atapi_pio_bytes(qc, bytes)))
995 goto err_out;
a57c1bad 996 ata_sff_sync(ap); /* flush */
624d5c51
TH
997
998 return;
999
1000 atapi_check:
1001 ata_ehi_push_desc(ehi, "ATAPI check failed (ireason=0x%x bytes=%u)",
1002 ireason, bytes);
1003 err_out:
1004 qc->err_mask |= AC_ERR_HSM;
1005 ap->hsm_task_state = HSM_ST_ERR;
1006}
1007
1008/**
1009 * ata_hsm_ok_in_wq - Check if the qc can be handled in the workqueue.
1010 * @ap: the target ata_port
1011 * @qc: qc on going
1012 *
1013 * RETURNS:
1014 * 1 if ok in workqueue, 0 otherwise.
1015 */
1016static inline int ata_hsm_ok_in_wq(struct ata_port *ap, struct ata_queued_cmd *qc)
1017{
1018 if (qc->tf.flags & ATA_TFLAG_POLLING)
1019 return 1;
1020
1021 if (ap->hsm_task_state == HSM_ST_FIRST) {
1022 if (qc->tf.protocol == ATA_PROT_PIO &&
1023 (qc->tf.flags & ATA_TFLAG_WRITE))
1024 return 1;
1025
1026 if (ata_is_atapi(qc->tf.protocol) &&
1027 !(qc->dev->flags & ATA_DFLAG_CDB_INTR))
1028 return 1;
1029 }
1030
1031 return 0;
1032}
1033
1034/**
1035 * ata_hsm_qc_complete - finish a qc running on standard HSM
1036 * @qc: Command to complete
1037 * @in_wq: 1 if called from workqueue, 0 otherwise
1038 *
1039 * Finish @qc which is running on standard HSM.
1040 *
1041 * LOCKING:
1042 * If @in_wq is zero, spin_lock_irqsave(host lock).
1043 * Otherwise, none on entry and grabs host lock.
1044 */
1045static void ata_hsm_qc_complete(struct ata_queued_cmd *qc, int in_wq)
1046{
1047 struct ata_port *ap = qc->ap;
1048 unsigned long flags;
1049
1050 if (ap->ops->error_handler) {
1051 if (in_wq) {
1052 spin_lock_irqsave(ap->lock, flags);
1053
1054 /* EH might have kicked in while host lock is
1055 * released.
1056 */
1057 qc = ata_qc_from_tag(ap, qc->tag);
1058 if (qc) {
1059 if (likely(!(qc->err_mask & AC_ERR_HSM))) {
5682ed33 1060 ap->ops->sff_irq_on(ap);
624d5c51
TH
1061 ata_qc_complete(qc);
1062 } else
1063 ata_port_freeze(ap);
1064 }
1065
1066 spin_unlock_irqrestore(ap->lock, flags);
1067 } else {
1068 if (likely(!(qc->err_mask & AC_ERR_HSM)))
1069 ata_qc_complete(qc);
1070 else
1071 ata_port_freeze(ap);
1072 }
1073 } else {
1074 if (in_wq) {
1075 spin_lock_irqsave(ap->lock, flags);
5682ed33 1076 ap->ops->sff_irq_on(ap);
624d5c51
TH
1077 ata_qc_complete(qc);
1078 spin_unlock_irqrestore(ap->lock, flags);
1079 } else
1080 ata_qc_complete(qc);
1081 }
1082}
1083
1084/**
9363c382 1085 * ata_sff_hsm_move - move the HSM to the next state.
624d5c51
TH
1086 * @ap: the target ata_port
1087 * @qc: qc on going
1088 * @status: current device status
1089 * @in_wq: 1 if called from workqueue, 0 otherwise
1090 *
1091 * RETURNS:
1092 * 1 when poll next status needed, 0 otherwise.
1093 */
9363c382
TH
1094int ata_sff_hsm_move(struct ata_port *ap, struct ata_queued_cmd *qc,
1095 u8 status, int in_wq)
624d5c51 1096{
a836d3e8 1097 struct ata_eh_info *ehi = &ap->link.eh_info;
624d5c51
TH
1098 unsigned long flags = 0;
1099 int poll_next;
1100
1101 WARN_ON((qc->flags & ATA_QCFLAG_ACTIVE) == 0);
1102
9363c382 1103 /* Make sure ata_sff_qc_issue() does not throw things
624d5c51
TH
1104 * like DMA polling into the workqueue. Notice that
1105 * in_wq is not equivalent to (qc->tf.flags & ATA_TFLAG_POLLING).
1106 */
1107 WARN_ON(in_wq != ata_hsm_ok_in_wq(ap, qc));
1108
1109fsm_start:
1110 DPRINTK("ata%u: protocol %d task_state %d (dev_stat 0x%X)\n",
1111 ap->print_id, qc->tf.protocol, ap->hsm_task_state, status);
1112
1113 switch (ap->hsm_task_state) {
1114 case HSM_ST_FIRST:
1115 /* Send first data block or PACKET CDB */
1116
1117 /* If polling, we will stay in the work queue after
1118 * sending the data. Otherwise, interrupt handler
1119 * takes over after sending the data.
1120 */
1121 poll_next = (qc->tf.flags & ATA_TFLAG_POLLING);
1122
1123 /* check device status */
1124 if (unlikely((status & ATA_DRQ) == 0)) {
1125 /* handle BSY=0, DRQ=0 as error */
1126 if (likely(status & (ATA_ERR | ATA_DF)))
1127 /* device stops HSM for abort/error */
1128 qc->err_mask |= AC_ERR_DEV;
a836d3e8 1129 else {
624d5c51 1130 /* HSM violation. Let EH handle this */
a836d3e8
TH
1131 ata_ehi_push_desc(ehi,
1132 "ST_FIRST: !(DRQ|ERR|DF)");
624d5c51 1133 qc->err_mask |= AC_ERR_HSM;
a836d3e8 1134 }
624d5c51
TH
1135
1136 ap->hsm_task_state = HSM_ST_ERR;
1137 goto fsm_start;
1138 }
1139
1140 /* Device should not ask for data transfer (DRQ=1)
1141 * when it finds something wrong.
1142 * We ignore DRQ here and stop the HSM by
1143 * changing hsm_task_state to HSM_ST_ERR and
1144 * let the EH abort the command or reset the device.
1145 */
1146 if (unlikely(status & (ATA_ERR | ATA_DF))) {
1147 /* Some ATAPI tape drives forget to clear the ERR bit
1148 * when doing the next command (mostly request sense).
1149 * We ignore ERR here to workaround and proceed sending
1150 * the CDB.
1151 */
1152 if (!(qc->dev->horkage & ATA_HORKAGE_STUCK_ERR)) {
a836d3e8
TH
1153 ata_ehi_push_desc(ehi, "ST_FIRST: "
1154 "DRQ=1 with device error, "
1155 "dev_stat 0x%X", status);
624d5c51
TH
1156 qc->err_mask |= AC_ERR_HSM;
1157 ap->hsm_task_state = HSM_ST_ERR;
1158 goto fsm_start;
1159 }
1160 }
1161
1162 /* Send the CDB (atapi) or the first data block (ata pio out).
1163 * During the state transition, interrupt handler shouldn't
1164 * be invoked before the data transfer is complete and
1165 * hsm_task_state is changed. Hence, the following locking.
1166 */
1167 if (in_wq)
1168 spin_lock_irqsave(ap->lock, flags);
1169
1170 if (qc->tf.protocol == ATA_PROT_PIO) {
1171 /* PIO data out protocol.
1172 * send first data block.
1173 */
1174
1175 /* ata_pio_sectors() might change the state
1176 * to HSM_ST_LAST. so, the state is changed here
1177 * before ata_pio_sectors().
1178 */
1179 ap->hsm_task_state = HSM_ST;
1180 ata_pio_sectors(qc);
1181 } else
1182 /* send CDB */
1183 atapi_send_cdb(ap, qc);
1184
1185 if (in_wq)
1186 spin_unlock_irqrestore(ap->lock, flags);
1187
1188 /* if polling, ata_pio_task() handles the rest.
1189 * otherwise, interrupt handler takes over from here.
1190 */
1191 break;
1192
1193 case HSM_ST:
1194 /* complete command or read/write the data register */
1195 if (qc->tf.protocol == ATAPI_PROT_PIO) {
1196 /* ATAPI PIO protocol */
1197 if ((status & ATA_DRQ) == 0) {
1198 /* No more data to transfer or device error.
1199 * Device error will be tagged in HSM_ST_LAST.
1200 */
1201 ap->hsm_task_state = HSM_ST_LAST;
1202 goto fsm_start;
1203 }
1204
1205 /* Device should not ask for data transfer (DRQ=1)
1206 * when it finds something wrong.
1207 * We ignore DRQ here and stop the HSM by
1208 * changing hsm_task_state to HSM_ST_ERR and
1209 * let the EH abort the command or reset the device.
1210 */
1211 if (unlikely(status & (ATA_ERR | ATA_DF))) {
a836d3e8
TH
1212 ata_ehi_push_desc(ehi, "ST-ATAPI: "
1213 "DRQ=1 with device error, "
1214 "dev_stat 0x%X", status);
624d5c51
TH
1215 qc->err_mask |= AC_ERR_HSM;
1216 ap->hsm_task_state = HSM_ST_ERR;
1217 goto fsm_start;
1218 }
1219
1220 atapi_pio_bytes(qc);
1221
1222 if (unlikely(ap->hsm_task_state == HSM_ST_ERR))
1223 /* bad ireason reported by device */
1224 goto fsm_start;
1225
1226 } else {
1227 /* ATA PIO protocol */
1228 if (unlikely((status & ATA_DRQ) == 0)) {
1229 /* handle BSY=0, DRQ=0 as error */
1230 if (likely(status & (ATA_ERR | ATA_DF)))
1231 /* device stops HSM for abort/error */
1232 qc->err_mask |= AC_ERR_DEV;
a836d3e8 1233 else {
624d5c51
TH
1234 /* HSM violation. Let EH handle this.
1235 * Phantom devices also trigger this
1236 * condition. Mark hint.
1237 */
a836d3e8
TH
1238 ata_ehi_push_desc(ehi, "ST-ATA: "
1239 "DRQ=1 with device error, "
1240 "dev_stat 0x%X", status);
624d5c51
TH
1241 qc->err_mask |= AC_ERR_HSM |
1242 AC_ERR_NODEV_HINT;
a836d3e8 1243 }
624d5c51
TH
1244
1245 ap->hsm_task_state = HSM_ST_ERR;
1246 goto fsm_start;
1247 }
1248
1249 /* For PIO reads, some devices may ask for
1250 * data transfer (DRQ=1) alone with ERR=1.
1251 * We respect DRQ here and transfer one
1252 * block of junk data before changing the
1253 * hsm_task_state to HSM_ST_ERR.
1254 *
1255 * For PIO writes, ERR=1 DRQ=1 doesn't make
1256 * sense since the data block has been
1257 * transferred to the device.
1258 */
1259 if (unlikely(status & (ATA_ERR | ATA_DF))) {
1260 /* data might be corrputed */
1261 qc->err_mask |= AC_ERR_DEV;
1262
1263 if (!(qc->tf.flags & ATA_TFLAG_WRITE)) {
1264 ata_pio_sectors(qc);
1265 status = ata_wait_idle(ap);
1266 }
1267
a836d3e8
TH
1268 if (status & (ATA_BUSY | ATA_DRQ)) {
1269 ata_ehi_push_desc(ehi, "ST-ATA: "
1270 "BUSY|DRQ persists on ERR|DF, "
1271 "dev_stat 0x%X", status);
624d5c51 1272 qc->err_mask |= AC_ERR_HSM;
a836d3e8 1273 }
624d5c51
TH
1274
1275 /* ata_pio_sectors() might change the
1276 * state to HSM_ST_LAST. so, the state
1277 * is changed after ata_pio_sectors().
1278 */
1279 ap->hsm_task_state = HSM_ST_ERR;
1280 goto fsm_start;
1281 }
1282
1283 ata_pio_sectors(qc);
1284
1285 if (ap->hsm_task_state == HSM_ST_LAST &&
1286 (!(qc->tf.flags & ATA_TFLAG_WRITE))) {
1287 /* all data read */
1288 status = ata_wait_idle(ap);
1289 goto fsm_start;
1290 }
1291 }
1292
1293 poll_next = 1;
1294 break;
1295
1296 case HSM_ST_LAST:
1297 if (unlikely(!ata_ok(status))) {
1298 qc->err_mask |= __ac_err_mask(status);
1299 ap->hsm_task_state = HSM_ST_ERR;
1300 goto fsm_start;
1301 }
1302
1303 /* no more data to transfer */
1304 DPRINTK("ata%u: dev %u command complete, drv_stat 0x%x\n",
1305 ap->print_id, qc->dev->devno, status);
1306
411cb386 1307 WARN_ON(qc->err_mask & (AC_ERR_DEV | AC_ERR_HSM));
624d5c51
TH
1308
1309 ap->hsm_task_state = HSM_ST_IDLE;
1310
1311 /* complete taskfile transaction */
1312 ata_hsm_qc_complete(qc, in_wq);
1313
1314 poll_next = 0;
1315 break;
1316
1317 case HSM_ST_ERR:
624d5c51
TH
1318 ap->hsm_task_state = HSM_ST_IDLE;
1319
1320 /* complete taskfile transaction */
1321 ata_hsm_qc_complete(qc, in_wq);
1322
1323 poll_next = 0;
1324 break;
1325 default:
1326 poll_next = 0;
1327 BUG();
1328 }
1329
1330 return poll_next;
1331}
1332
1333void ata_pio_task(struct work_struct *work)
1334{
1335 struct ata_port *ap =
1336 container_of(work, struct ata_port, port_task.work);
1337 struct ata_queued_cmd *qc = ap->port_task_data;
1338 u8 status;
1339 int poll_next;
1340
1341fsm_start:
1342 WARN_ON(ap->hsm_task_state == HSM_ST_IDLE);
1343
1344 /*
1345 * This is purely heuristic. This is a fast path.
1346 * Sometimes when we enter, BSY will be cleared in
1347 * a chk-status or two. If not, the drive is probably seeking
1348 * or something. Snooze for a couple msecs, then
1349 * chk-status again. If still busy, queue delayed work.
1350 */
9363c382 1351 status = ata_sff_busy_wait(ap, ATA_BUSY, 5);
624d5c51
TH
1352 if (status & ATA_BUSY) {
1353 msleep(2);
9363c382 1354 status = ata_sff_busy_wait(ap, ATA_BUSY, 10);
624d5c51
TH
1355 if (status & ATA_BUSY) {
1356 ata_pio_queue_task(ap, qc, ATA_SHORT_PAUSE);
1357 return;
1358 }
1359 }
1360
1361 /* move the HSM */
9363c382 1362 poll_next = ata_sff_hsm_move(ap, qc, status, 1);
624d5c51
TH
1363
1364 /* another command or interrupt handler
1365 * may be running at this point.
1366 */
1367 if (poll_next)
1368 goto fsm_start;
1369}
1370
1371/**
9363c382 1372 * ata_sff_qc_issue - issue taskfile to device in proto-dependent manner
624d5c51
TH
1373 * @qc: command to issue to device
1374 *
1375 * Using various libata functions and hooks, this function
1376 * starts an ATA command. ATA commands are grouped into
1377 * classes called "protocols", and issuing each type of protocol
1378 * is slightly different.
1379 *
1380 * May be used as the qc_issue() entry in ata_port_operations.
1381 *
1382 * LOCKING:
1383 * spin_lock_irqsave(host lock)
1384 *
1385 * RETURNS:
1386 * Zero on success, AC_ERR_* mask on failure
1387 */
9363c382 1388unsigned int ata_sff_qc_issue(struct ata_queued_cmd *qc)
624d5c51
TH
1389{
1390 struct ata_port *ap = qc->ap;
1391
1392 /* Use polling pio if the LLD doesn't handle
1393 * interrupt driven pio and atapi CDB interrupt.
1394 */
1395 if (ap->flags & ATA_FLAG_PIO_POLLING) {
1396 switch (qc->tf.protocol) {
1397 case ATA_PROT_PIO:
1398 case ATA_PROT_NODATA:
1399 case ATAPI_PROT_PIO:
1400 case ATAPI_PROT_NODATA:
1401 qc->tf.flags |= ATA_TFLAG_POLLING;
1402 break;
1403 case ATAPI_PROT_DMA:
1404 if (qc->dev->flags & ATA_DFLAG_CDB_INTR)
1405 /* see ata_dma_blacklisted() */
1406 BUG();
1407 break;
1408 default:
1409 break;
1410 }
1411 }
1412
1413 /* select the device */
1414 ata_dev_select(ap, qc->dev->devno, 1, 0);
1415
1416 /* start the command */
1417 switch (qc->tf.protocol) {
1418 case ATA_PROT_NODATA:
1419 if (qc->tf.flags & ATA_TFLAG_POLLING)
1420 ata_qc_set_polling(qc);
1421
1422 ata_tf_to_host(ap, &qc->tf);
1423 ap->hsm_task_state = HSM_ST_LAST;
1424
1425 if (qc->tf.flags & ATA_TFLAG_POLLING)
1426 ata_pio_queue_task(ap, qc, 0);
1427
1428 break;
1429
1430 case ATA_PROT_DMA:
1431 WARN_ON(qc->tf.flags & ATA_TFLAG_POLLING);
1432
5682ed33 1433 ap->ops->sff_tf_load(ap, &qc->tf); /* load tf registers */
624d5c51
TH
1434 ap->ops->bmdma_setup(qc); /* set up bmdma */
1435 ap->ops->bmdma_start(qc); /* initiate bmdma */
1436 ap->hsm_task_state = HSM_ST_LAST;
1437 break;
1438
1439 case ATA_PROT_PIO:
1440 if (qc->tf.flags & ATA_TFLAG_POLLING)
1441 ata_qc_set_polling(qc);
1442
1443 ata_tf_to_host(ap, &qc->tf);
1444
1445 if (qc->tf.flags & ATA_TFLAG_WRITE) {
1446 /* PIO data out protocol */
1447 ap->hsm_task_state = HSM_ST_FIRST;
1448 ata_pio_queue_task(ap, qc, 0);
1449
1450 /* always send first data block using
1451 * the ata_pio_task() codepath.
1452 */
1453 } else {
1454 /* PIO data in protocol */
1455 ap->hsm_task_state = HSM_ST;
1456
1457 if (qc->tf.flags & ATA_TFLAG_POLLING)
1458 ata_pio_queue_task(ap, qc, 0);
1459
1460 /* if polling, ata_pio_task() handles the rest.
1461 * otherwise, interrupt handler takes over from here.
1462 */
1463 }
1464
1465 break;
1466
1467 case ATAPI_PROT_PIO:
1468 case ATAPI_PROT_NODATA:
1469 if (qc->tf.flags & ATA_TFLAG_POLLING)
1470 ata_qc_set_polling(qc);
1471
1472 ata_tf_to_host(ap, &qc->tf);
1473
1474 ap->hsm_task_state = HSM_ST_FIRST;
1475
1476 /* send cdb by polling if no cdb interrupt */
1477 if ((!(qc->dev->flags & ATA_DFLAG_CDB_INTR)) ||
1478 (qc->tf.flags & ATA_TFLAG_POLLING))
1479 ata_pio_queue_task(ap, qc, 0);
1480 break;
1481
1482 case ATAPI_PROT_DMA:
1483 WARN_ON(qc->tf.flags & ATA_TFLAG_POLLING);
1484
5682ed33 1485 ap->ops->sff_tf_load(ap, &qc->tf); /* load tf registers */
624d5c51
TH
1486 ap->ops->bmdma_setup(qc); /* set up bmdma */
1487 ap->hsm_task_state = HSM_ST_FIRST;
1488
1489 /* send cdb by polling if no cdb interrupt */
1490 if (!(qc->dev->flags & ATA_DFLAG_CDB_INTR))
1491 ata_pio_queue_task(ap, qc, 0);
1492 break;
1493
1494 default:
1495 WARN_ON(1);
1496 return AC_ERR_SYSTEM;
1497 }
1498
1499 return 0;
1500}
1501
22183bf5
TH
1502/**
1503 * ata_sff_qc_fill_rtf - fill result TF using ->sff_tf_read
1504 * @qc: qc to fill result TF for
1505 *
1506 * @qc is finished and result TF needs to be filled. Fill it
1507 * using ->sff_tf_read.
1508 *
1509 * LOCKING:
1510 * spin_lock_irqsave(host lock)
1511 *
1512 * RETURNS:
1513 * true indicating that result TF is successfully filled.
1514 */
1515bool ata_sff_qc_fill_rtf(struct ata_queued_cmd *qc)
1516{
1517 qc->ap->ops->sff_tf_read(qc->ap, &qc->result_tf);
1518 return true;
1519}
1520
624d5c51 1521/**
9363c382 1522 * ata_sff_host_intr - Handle host interrupt for given (port, task)
624d5c51
TH
1523 * @ap: Port on which interrupt arrived (possibly...)
1524 * @qc: Taskfile currently active in engine
1525 *
1526 * Handle host interrupt for given queued command. Currently,
1527 * only DMA interrupts are handled. All other commands are
1528 * handled via polling with interrupts disabled (nIEN bit).
1529 *
1530 * LOCKING:
1531 * spin_lock_irqsave(host lock)
1532 *
1533 * RETURNS:
1534 * One if interrupt was handled, zero if not (shared irq).
1535 */
9363c382
TH
1536inline unsigned int ata_sff_host_intr(struct ata_port *ap,
1537 struct ata_queued_cmd *qc)
624d5c51
TH
1538{
1539 struct ata_eh_info *ehi = &ap->link.eh_info;
1540 u8 status, host_stat = 0;
1541
1542 VPRINTK("ata%u: protocol %d task_state %d\n",
1543 ap->print_id, qc->tf.protocol, ap->hsm_task_state);
1544
1545 /* Check whether we are expecting interrupt in this state */
1546 switch (ap->hsm_task_state) {
1547 case HSM_ST_FIRST:
1548 /* Some pre-ATAPI-4 devices assert INTRQ
1549 * at this state when ready to receive CDB.
1550 */
1551
1552 /* Check the ATA_DFLAG_CDB_INTR flag is enough here.
1553 * The flag was turned on only for atapi devices. No
1554 * need to check ata_is_atapi(qc->tf.protocol) again.
1555 */
1556 if (!(qc->dev->flags & ATA_DFLAG_CDB_INTR))
1557 goto idle_irq;
1558 break;
1559 case HSM_ST_LAST:
1560 if (qc->tf.protocol == ATA_PROT_DMA ||
1561 qc->tf.protocol == ATAPI_PROT_DMA) {
1562 /* check status of DMA engine */
1563 host_stat = ap->ops->bmdma_status(ap);
1564 VPRINTK("ata%u: host_stat 0x%X\n",
1565 ap->print_id, host_stat);
1566
1567 /* if it's not our irq... */
1568 if (!(host_stat & ATA_DMA_INTR))
1569 goto idle_irq;
1570
1571 /* before we do anything else, clear DMA-Start bit */
1572 ap->ops->bmdma_stop(qc);
1573
1574 if (unlikely(host_stat & ATA_DMA_ERR)) {
1575 /* error when transfering data to/from memory */
1576 qc->err_mask |= AC_ERR_HOST_BUS;
1577 ap->hsm_task_state = HSM_ST_ERR;
1578 }
1579 }
1580 break;
1581 case HSM_ST:
1582 break;
1583 default:
1584 goto idle_irq;
1585 }
1586
624d5c51 1587
a57c1bad
AC
1588 /* check main status, clearing INTRQ if needed */
1589 status = ata_sff_irq_status(ap);
1590 if (status & ATA_BUSY)
624d5c51
TH
1591 goto idle_irq;
1592
1593 /* ack bmdma irq events */
5682ed33 1594 ap->ops->sff_irq_clear(ap);
624d5c51 1595
9363c382 1596 ata_sff_hsm_move(ap, qc, status, 0);
624d5c51
TH
1597
1598 if (unlikely(qc->err_mask) && (qc->tf.protocol == ATA_PROT_DMA ||
1599 qc->tf.protocol == ATAPI_PROT_DMA))
1600 ata_ehi_push_desc(ehi, "BMDMA stat 0x%x", host_stat);
1601
1602 return 1; /* irq handled */
1603
1604idle_irq:
1605 ap->stats.idle_irq++;
1606
1607#ifdef ATA_IRQ_TRAP
1608 if ((ap->stats.idle_irq % 1000) == 0) {
5682ed33
TH
1609 ap->ops->sff_check_status(ap);
1610 ap->ops->sff_irq_clear(ap);
624d5c51
TH
1611 ata_port_printk(ap, KERN_WARNING, "irq trap\n");
1612 return 1;
1613 }
1614#endif
1615 return 0; /* irq not handled */
1616}
1617
1618/**
9363c382 1619 * ata_sff_interrupt - Default ATA host interrupt handler
624d5c51
TH
1620 * @irq: irq line (unused)
1621 * @dev_instance: pointer to our ata_host information structure
1622 *
1623 * Default interrupt handler for PCI IDE devices. Calls
9363c382 1624 * ata_sff_host_intr() for each port that is not disabled.
624d5c51
TH
1625 *
1626 * LOCKING:
1627 * Obtains host lock during operation.
1628 *
1629 * RETURNS:
1630 * IRQ_NONE or IRQ_HANDLED.
1631 */
9363c382 1632irqreturn_t ata_sff_interrupt(int irq, void *dev_instance)
624d5c51
TH
1633{
1634 struct ata_host *host = dev_instance;
1635 unsigned int i;
1636 unsigned int handled = 0;
1637 unsigned long flags;
1638
1639 /* TODO: make _irqsave conditional on x86 PCI IDE legacy mode */
1640 spin_lock_irqsave(&host->lock, flags);
1641
1642 for (i = 0; i < host->n_ports; i++) {
1643 struct ata_port *ap;
1644
1645 ap = host->ports[i];
1646 if (ap &&
1647 !(ap->flags & ATA_FLAG_DISABLED)) {
1648 struct ata_queued_cmd *qc;
1649
1650 qc = ata_qc_from_tag(ap, ap->link.active_tag);
1651 if (qc && (!(qc->tf.flags & ATA_TFLAG_POLLING)) &&
1652 (qc->flags & ATA_QCFLAG_ACTIVE))
9363c382 1653 handled |= ata_sff_host_intr(ap, qc);
624d5c51
TH
1654 }
1655 }
1656
1657 spin_unlock_irqrestore(&host->lock, flags);
1658
1659 return IRQ_RETVAL(handled);
1660}
1661
1662/**
9363c382 1663 * ata_sff_freeze - Freeze SFF controller port
624d5c51
TH
1664 * @ap: port to freeze
1665 *
1666 * Freeze BMDMA controller port.
1667 *
1668 * LOCKING:
1669 * Inherited from caller.
1670 */
9363c382 1671void ata_sff_freeze(struct ata_port *ap)
624d5c51
TH
1672{
1673 struct ata_ioports *ioaddr = &ap->ioaddr;
1674
1675 ap->ctl |= ATA_NIEN;
1676 ap->last_ctl = ap->ctl;
1677
1678 if (ioaddr->ctl_addr)
1679 iowrite8(ap->ctl, ioaddr->ctl_addr);
1680
1681 /* Under certain circumstances, some controllers raise IRQ on
1682 * ATA_NIEN manipulation. Also, many controllers fail to mask
1683 * previously pending IRQ on ATA_NIEN assertion. Clear it.
1684 */
5682ed33 1685 ap->ops->sff_check_status(ap);
624d5c51 1686
5682ed33 1687 ap->ops->sff_irq_clear(ap);
624d5c51
TH
1688}
1689
1690/**
9363c382 1691 * ata_sff_thaw - Thaw SFF controller port
624d5c51
TH
1692 * @ap: port to thaw
1693 *
9363c382 1694 * Thaw SFF controller port.
624d5c51
TH
1695 *
1696 * LOCKING:
1697 * Inherited from caller.
1698 */
9363c382 1699void ata_sff_thaw(struct ata_port *ap)
272f7884 1700{
624d5c51 1701 /* clear & re-enable interrupts */
5682ed33
TH
1702 ap->ops->sff_check_status(ap);
1703 ap->ops->sff_irq_clear(ap);
1704 ap->ops->sff_irq_on(ap);
272f7884
TH
1705}
1706
0aa1113d
TH
1707/**
1708 * ata_sff_prereset - prepare SFF link for reset
1709 * @link: SFF link to be reset
1710 * @deadline: deadline jiffies for the operation
1711 *
1712 * SFF link @link is about to be reset. Initialize it. It first
1713 * calls ata_std_prereset() and wait for !BSY if the port is
1714 * being softreset.
1715 *
1716 * LOCKING:
1717 * Kernel thread context (may sleep)
1718 *
1719 * RETURNS:
1720 * 0 on success, -errno otherwise.
1721 */
1722int ata_sff_prereset(struct ata_link *link, unsigned long deadline)
1723{
0aa1113d
TH
1724 struct ata_eh_context *ehc = &link->eh_context;
1725 int rc;
1726
1727 rc = ata_std_prereset(link, deadline);
1728 if (rc)
1729 return rc;
1730
1731 /* if we're about to do hardreset, nothing more to do */
1732 if (ehc->i.action & ATA_EH_HARDRESET)
1733 return 0;
1734
1735 /* wait for !BSY if we don't know that no device is attached */
1736 if (!ata_link_offline(link)) {
705e76be 1737 rc = ata_sff_wait_ready(link, deadline);
0aa1113d
TH
1738 if (rc && rc != -ENODEV) {
1739 ata_link_printk(link, KERN_WARNING, "device not ready "
1740 "(errno=%d), forcing hardreset\n", rc);
1741 ehc->i.action |= ATA_EH_HARDRESET;
1742 }
1743 }
1744
1745 return 0;
1746}
1747
90088bb4 1748/**
624d5c51
TH
1749 * ata_devchk - PATA device presence detection
1750 * @ap: ATA channel to examine
1751 * @device: Device to examine (starting at zero)
90088bb4 1752 *
624d5c51
TH
1753 * This technique was originally described in
1754 * Hale Landis's ATADRVR (www.ata-atapi.com), and
1755 * later found its way into the ATA/ATAPI spec.
1756 *
1757 * Write a pattern to the ATA shadow registers,
1758 * and if a device is present, it will respond by
1759 * correctly storing and echoing back the
1760 * ATA shadow register contents.
90088bb4
TH
1761 *
1762 * LOCKING:
624d5c51 1763 * caller.
90088bb4 1764 */
624d5c51 1765static unsigned int ata_devchk(struct ata_port *ap, unsigned int device)
90088bb4
TH
1766{
1767 struct ata_ioports *ioaddr = &ap->ioaddr;
624d5c51 1768 u8 nsect, lbal;
90088bb4 1769
5682ed33 1770 ap->ops->sff_dev_select(ap, device);
90088bb4 1771
624d5c51
TH
1772 iowrite8(0x55, ioaddr->nsect_addr);
1773 iowrite8(0xaa, ioaddr->lbal_addr);
90088bb4 1774
624d5c51
TH
1775 iowrite8(0xaa, ioaddr->nsect_addr);
1776 iowrite8(0x55, ioaddr->lbal_addr);
90088bb4 1777
624d5c51
TH
1778 iowrite8(0x55, ioaddr->nsect_addr);
1779 iowrite8(0xaa, ioaddr->lbal_addr);
1780
1781 nsect = ioread8(ioaddr->nsect_addr);
1782 lbal = ioread8(ioaddr->lbal_addr);
1783
1784 if ((nsect == 0x55) && (lbal == 0xaa))
1785 return 1; /* we found a device */
1786
1787 return 0; /* nothing found */
90088bb4
TH
1788}
1789
272f7884 1790/**
9363c382 1791 * ata_sff_dev_classify - Parse returned ATA device signature
624d5c51
TH
1792 * @dev: ATA device to classify (starting at zero)
1793 * @present: device seems present
1794 * @r_err: Value of error register on completion
272f7884 1795 *
624d5c51
TH
1796 * After an event -- SRST, E.D.D., or SATA COMRESET -- occurs,
1797 * an ATA/ATAPI-defined set of values is placed in the ATA
1798 * shadow registers, indicating the results of device detection
1799 * and diagnostics.
272f7884 1800 *
624d5c51
TH
1801 * Select the ATA device, and read the values from the ATA shadow
1802 * registers. Then parse according to the Error register value,
1803 * and the spec-defined values examined by ata_dev_classify().
272f7884
TH
1804 *
1805 * LOCKING:
624d5c51
TH
1806 * caller.
1807 *
1808 * RETURNS:
1809 * Device type - %ATA_DEV_ATA, %ATA_DEV_ATAPI or %ATA_DEV_NONE.
272f7884 1810 */
9363c382 1811unsigned int ata_sff_dev_classify(struct ata_device *dev, int present,
624d5c51 1812 u8 *r_err)
272f7884 1813{
624d5c51
TH
1814 struct ata_port *ap = dev->link->ap;
1815 struct ata_taskfile tf;
1816 unsigned int class;
1817 u8 err;
1818
5682ed33 1819 ap->ops->sff_dev_select(ap, dev->devno);
624d5c51
TH
1820
1821 memset(&tf, 0, sizeof(tf));
1822
5682ed33 1823 ap->ops->sff_tf_read(ap, &tf);
624d5c51
TH
1824 err = tf.feature;
1825 if (r_err)
1826 *r_err = err;
1827
1828 /* see if device passed diags: continue and warn later */
1829 if (err == 0)
1830 /* diagnostic fail : do nothing _YET_ */
1831 dev->horkage |= ATA_HORKAGE_DIAGNOSTIC;
1832 else if (err == 1)
1833 /* do nothing */ ;
1834 else if ((dev->devno == 0) && (err == 0x81))
1835 /* do nothing */ ;
1836 else
1837 return ATA_DEV_NONE;
272f7884 1838
624d5c51
TH
1839 /* determine if device is ATA or ATAPI */
1840 class = ata_dev_classify(&tf);
272f7884 1841
624d5c51
TH
1842 if (class == ATA_DEV_UNKNOWN) {
1843 /* If the device failed diagnostic, it's likely to
1844 * have reported incorrect device signature too.
1845 * Assume ATA device if the device seems present but
1846 * device signature is invalid with diagnostic
1847 * failure.
1848 */
1849 if (present && (dev->horkage & ATA_HORKAGE_DIAGNOSTIC))
1850 class = ATA_DEV_ATA;
1851 else
1852 class = ATA_DEV_NONE;
5682ed33
TH
1853 } else if ((class == ATA_DEV_ATA) &&
1854 (ap->ops->sff_check_status(ap) == 0))
624d5c51
TH
1855 class = ATA_DEV_NONE;
1856
1857 return class;
272f7884
TH
1858}
1859
705e76be
TH
1860/**
1861 * ata_sff_wait_after_reset - wait for devices to become ready after reset
1862 * @link: SFF link which is just reset
1863 * @devmask: mask of present devices
1864 * @deadline: deadline jiffies for the operation
1865 *
1866 * Wait devices attached to SFF @link to become ready after
1867 * reset. It contains preceding 150ms wait to avoid accessing TF
1868 * status register too early.
1869 *
1870 * LOCKING:
1871 * Kernel thread context (may sleep).
1872 *
1873 * RETURNS:
1874 * 0 on success, -ENODEV if some or all of devices in @devmask
1875 * don't seem to exist. -errno on other errors.
1876 */
1877int ata_sff_wait_after_reset(struct ata_link *link, unsigned int devmask,
1878 unsigned long deadline)
1fdffbce 1879{
705e76be 1880 struct ata_port *ap = link->ap;
1fdffbce 1881 struct ata_ioports *ioaddr = &ap->ioaddr;
624d5c51
TH
1882 unsigned int dev0 = devmask & (1 << 0);
1883 unsigned int dev1 = devmask & (1 << 1);
1884 int rc, ret = 0;
1fdffbce 1885
341c2c95 1886 msleep(ATA_WAIT_AFTER_RESET);
705e76be
TH
1887
1888 /* always check readiness of the master device */
1889 rc = ata_sff_wait_ready(link, deadline);
1890 /* -ENODEV means the odd clown forgot the D7 pulldown resistor
1891 * and TF status is 0xff, bail out on it too.
624d5c51 1892 */
705e76be
TH
1893 if (rc)
1894 return rc;
1fdffbce 1895
624d5c51
TH
1896 /* if device 1 was found in ata_devchk, wait for register
1897 * access briefly, then wait for BSY to clear.
1898 */
1899 if (dev1) {
1900 int i;
1fdffbce 1901
5682ed33 1902 ap->ops->sff_dev_select(ap, 1);
1fdffbce 1903
624d5c51
TH
1904 /* Wait for register access. Some ATAPI devices fail
1905 * to set nsect/lbal after reset, so don't waste too
1906 * much time on it. We're gonna wait for !BSY anyway.
1907 */
1908 for (i = 0; i < 2; i++) {
1909 u8 nsect, lbal;
1910
1911 nsect = ioread8(ioaddr->nsect_addr);
1912 lbal = ioread8(ioaddr->lbal_addr);
1913 if ((nsect == 1) && (lbal == 1))
1914 break;
1915 msleep(50); /* give drive a breather */
1916 }
1917
705e76be 1918 rc = ata_sff_wait_ready(link, deadline);
624d5c51
TH
1919 if (rc) {
1920 if (rc != -ENODEV)
1921 return rc;
1922 ret = rc;
1923 }
1fdffbce
JG
1924 }
1925
624d5c51 1926 /* is all this really necessary? */
5682ed33 1927 ap->ops->sff_dev_select(ap, 0);
624d5c51 1928 if (dev1)
5682ed33 1929 ap->ops->sff_dev_select(ap, 1);
624d5c51 1930 if (dev0)
5682ed33 1931 ap->ops->sff_dev_select(ap, 0);
624d5c51
TH
1932
1933 return ret;
1fdffbce
JG
1934}
1935
624d5c51
TH
1936static int ata_bus_softreset(struct ata_port *ap, unsigned int devmask,
1937 unsigned long deadline)
2cc432ee 1938{
624d5c51 1939 struct ata_ioports *ioaddr = &ap->ioaddr;
2cc432ee 1940
624d5c51
TH
1941 DPRINTK("ata%u: bus reset via SRST\n", ap->print_id);
1942
1943 /* software reset. causes dev0 to be selected */
1944 iowrite8(ap->ctl, ioaddr->ctl_addr);
1945 udelay(20); /* FIXME: flush */
1946 iowrite8(ap->ctl | ATA_SRST, ioaddr->ctl_addr);
1947 udelay(20); /* FIXME: flush */
1948 iowrite8(ap->ctl, ioaddr->ctl_addr);
1949
705e76be
TH
1950 /* wait the port to become ready */
1951 return ata_sff_wait_after_reset(&ap->link, devmask, deadline);
2cc432ee
JG
1952}
1953
6d97dbd7 1954/**
9363c382 1955 * ata_sff_softreset - reset host port via ATA SRST
624d5c51
TH
1956 * @link: ATA link to reset
1957 * @classes: resulting classes of attached devices
1958 * @deadline: deadline jiffies for the operation
6d97dbd7 1959 *
624d5c51 1960 * Reset host port using ATA SRST.
6d97dbd7
TH
1961 *
1962 * LOCKING:
624d5c51
TH
1963 * Kernel thread context (may sleep)
1964 *
1965 * RETURNS:
1966 * 0 on success, -errno otherwise.
6d97dbd7 1967 */
9363c382 1968int ata_sff_softreset(struct ata_link *link, unsigned int *classes,
624d5c51 1969 unsigned long deadline)
6d97dbd7 1970{
624d5c51
TH
1971 struct ata_port *ap = link->ap;
1972 unsigned int slave_possible = ap->flags & ATA_FLAG_SLAVE_POSS;
1973 unsigned int devmask = 0;
1974 int rc;
1975 u8 err;
6d97dbd7 1976
624d5c51 1977 DPRINTK("ENTER\n");
6d97dbd7 1978
624d5c51
TH
1979 /* determine if device 0/1 are present */
1980 if (ata_devchk(ap, 0))
1981 devmask |= (1 << 0);
1982 if (slave_possible && ata_devchk(ap, 1))
1983 devmask |= (1 << 1);
1984
1985 /* select device 0 again */
5682ed33 1986 ap->ops->sff_dev_select(ap, 0);
624d5c51
TH
1987
1988 /* issue bus reset */
1989 DPRINTK("about to softreset, devmask=%x\n", devmask);
1990 rc = ata_bus_softreset(ap, devmask, deadline);
1991 /* if link is occupied, -ENODEV too is an error */
1992 if (rc && (rc != -ENODEV || sata_scr_valid(link))) {
1993 ata_link_printk(link, KERN_ERR, "SRST failed (errno=%d)\n", rc);
1994 return rc;
1995 }
0f0a3ad3 1996
624d5c51 1997 /* determine by signature whether we have ATA or ATAPI devices */
9363c382 1998 classes[0] = ata_sff_dev_classify(&link->device[0],
624d5c51
TH
1999 devmask & (1 << 0), &err);
2000 if (slave_possible && err != 0x81)
9363c382 2001 classes[1] = ata_sff_dev_classify(&link->device[1],
624d5c51
TH
2002 devmask & (1 << 1), &err);
2003
624d5c51
TH
2004 DPRINTK("EXIT, classes[0]=%u [1]=%u\n", classes[0], classes[1]);
2005 return 0;
6d97dbd7
TH
2006}
2007
2008/**
9363c382 2009 * sata_sff_hardreset - reset host port via SATA phy reset
624d5c51
TH
2010 * @link: link to reset
2011 * @class: resulting class of attached device
2012 * @deadline: deadline jiffies for the operation
6d97dbd7 2013 *
624d5c51
TH
2014 * SATA phy-reset host port using DET bits of SControl register,
2015 * wait for !BSY and classify the attached device.
6d97dbd7
TH
2016 *
2017 * LOCKING:
624d5c51
TH
2018 * Kernel thread context (may sleep)
2019 *
2020 * RETURNS:
2021 * 0 on success, -errno otherwise.
6d97dbd7 2022 */
9363c382 2023int sata_sff_hardreset(struct ata_link *link, unsigned int *class,
624d5c51 2024 unsigned long deadline)
6d97dbd7 2025{
9dadd45b
TH
2026 struct ata_eh_context *ehc = &link->eh_context;
2027 const unsigned long *timing = sata_ehc_deb_timing(ehc);
2028 bool online;
624d5c51
TH
2029 int rc;
2030
9dadd45b
TH
2031 rc = sata_link_hardreset(link, timing, deadline, &online,
2032 ata_sff_check_ready);
9dadd45b
TH
2033 if (online)
2034 *class = ata_sff_dev_classify(link->device, 1, NULL);
624d5c51
TH
2035
2036 DPRINTK("EXIT, class=%u\n", *class);
9dadd45b 2037 return rc;
6d97dbd7
TH
2038}
2039
203c75b8
TH
2040/**
2041 * ata_sff_postreset - SFF postreset callback
2042 * @link: the target SFF ata_link
2043 * @classes: classes of attached devices
2044 *
2045 * This function is invoked after a successful reset. It first
2046 * calls ata_std_postreset() and performs SFF specific postreset
2047 * processing.
2048 *
2049 * LOCKING:
2050 * Kernel thread context (may sleep)
2051 */
2052void ata_sff_postreset(struct ata_link *link, unsigned int *classes)
2053{
2054 struct ata_port *ap = link->ap;
2055
2056 ata_std_postreset(link, classes);
2057
2058 /* is double-select really necessary? */
2059 if (classes[0] != ATA_DEV_NONE)
2060 ap->ops->sff_dev_select(ap, 1);
2061 if (classes[1] != ATA_DEV_NONE)
2062 ap->ops->sff_dev_select(ap, 0);
2063
2064 /* bail out if no device is present */
2065 if (classes[0] == ATA_DEV_NONE && classes[1] == ATA_DEV_NONE) {
2066 DPRINTK("EXIT, no device\n");
2067 return;
2068 }
2069
2070 /* set up device control */
2071 if (ap->ioaddr.ctl_addr)
2072 iowrite8(ap->ctl, ap->ioaddr.ctl_addr);
2073}
2074
6d97dbd7 2075/**
9363c382 2076 * ata_sff_error_handler - Stock error handler for BMDMA controller
6d97dbd7 2077 * @ap: port to handle error for
6d97dbd7 2078 *
9363c382 2079 * Stock error handler for SFF controller. It can handle both
6d97dbd7
TH
2080 * PATA and SATA controllers. Many controllers should be able to
2081 * use this EH as-is or with some added handling before and
2082 * after.
2083 *
6d97dbd7
TH
2084 * LOCKING:
2085 * Kernel thread context (may sleep)
2086 */
9363c382 2087void ata_sff_error_handler(struct ata_port *ap)
6d97dbd7 2088{
a1efdaba
TH
2089 ata_reset_fn_t softreset = ap->ops->softreset;
2090 ata_reset_fn_t hardreset = ap->ops->hardreset;
6d97dbd7
TH
2091 struct ata_queued_cmd *qc;
2092 unsigned long flags;
2093 int thaw = 0;
2094
9af5c9c9 2095 qc = __ata_qc_from_tag(ap, ap->link.active_tag);
6d97dbd7
TH
2096 if (qc && !(qc->flags & ATA_QCFLAG_FAILED))
2097 qc = NULL;
2098
2099 /* reset PIO HSM and stop DMA engine */
ba6a1308 2100 spin_lock_irqsave(ap->lock, flags);
6d97dbd7 2101
6d97dbd7
TH
2102 ap->hsm_task_state = HSM_ST_IDLE;
2103
ed82f964
TH
2104 if (ap->ioaddr.bmdma_addr &&
2105 qc && (qc->tf.protocol == ATA_PROT_DMA ||
0dc36888 2106 qc->tf.protocol == ATAPI_PROT_DMA)) {
6d97dbd7
TH
2107 u8 host_stat;
2108
fbbb262d 2109 host_stat = ap->ops->bmdma_status(ap);
6d97dbd7 2110
6d97dbd7
TH
2111 /* BMDMA controllers indicate host bus error by
2112 * setting DMA_ERR bit and timing out. As it wasn't
2113 * really a timeout event, adjust error mask and
2114 * cancel frozen state.
2115 */
18d90deb 2116 if (qc->err_mask == AC_ERR_TIMEOUT && (host_stat & ATA_DMA_ERR)) {
6d97dbd7
TH
2117 qc->err_mask = AC_ERR_HOST_BUS;
2118 thaw = 1;
2119 }
2120
2121 ap->ops->bmdma_stop(qc);
2122 }
2123
a57c1bad 2124 ata_sff_sync(ap); /* FIXME: We don't need this */
5682ed33
TH
2125 ap->ops->sff_check_status(ap);
2126 ap->ops->sff_irq_clear(ap);
6d97dbd7 2127
ba6a1308 2128 spin_unlock_irqrestore(ap->lock, flags);
6d97dbd7
TH
2129
2130 if (thaw)
2131 ata_eh_thaw_port(ap);
2132
2133 /* PIO and DMA engines have been stopped, perform recovery */
6d97dbd7 2134
57c9efdf
TH
2135 /* Ignore ata_sff_softreset if ctl isn't accessible and
2136 * built-in hardresets if SCR access isn't available.
a1efdaba 2137 */
9363c382 2138 if (softreset == ata_sff_softreset && !ap->ioaddr.ctl_addr)
a1efdaba 2139 softreset = NULL;
57c9efdf 2140 if (ata_is_builtin_hardreset(hardreset) && !sata_scr_valid(&ap->link))
a1efdaba 2141 hardreset = NULL;
6d97dbd7 2142
a1efdaba
TH
2143 ata_do_eh(ap, ap->ops->prereset, softreset, hardreset,
2144 ap->ops->postreset);
6d97dbd7
TH
2145}
2146
2147/**
9363c382 2148 * ata_sff_post_internal_cmd - Stock post_internal_cmd for SFF controller
6d97dbd7
TH
2149 * @qc: internal command to clean up
2150 *
2151 * LOCKING:
2152 * Kernel thread context (may sleep)
2153 */
9363c382 2154void ata_sff_post_internal_cmd(struct ata_queued_cmd *qc)
6d97dbd7 2155{
61dd08c6
A
2156 if (qc->ap->ioaddr.bmdma_addr)
2157 ata_bmdma_stop(qc);
6d97dbd7
TH
2158}
2159
d92e74d3
AC
2160/**
2161 * ata_sff_port_start - Set port up for dma.
2162 * @ap: Port to initialize
2163 *
2164 * Called just after data structures for each port are
2165 * initialized. Allocates space for PRD table if the device
2166 * is DMA capable SFF.
2167 *
2168 * May be used as the port_start() entry in ata_port_operations.
2169 *
2170 * LOCKING:
2171 * Inherited from caller.
2172 */
d92e74d3
AC
2173int ata_sff_port_start(struct ata_port *ap)
2174{
2175 if (ap->ioaddr.bmdma_addr)
2176 return ata_port_start(ap);
2177 return 0;
2178}
2179
624d5c51 2180/**
9363c382 2181 * ata_sff_std_ports - initialize ioaddr with standard port offsets.
624d5c51
TH
2182 * @ioaddr: IO address structure to be initialized
2183 *
2184 * Utility function which initializes data_addr, error_addr,
2185 * feature_addr, nsect_addr, lbal_addr, lbam_addr, lbah_addr,
2186 * device_addr, status_addr, and command_addr to standard offsets
2187 * relative to cmd_addr.
2188 *
2189 * Does not set ctl_addr, altstatus_addr, bmdma_addr, or scr_addr.
2190 */
9363c382 2191void ata_sff_std_ports(struct ata_ioports *ioaddr)
624d5c51
TH
2192{
2193 ioaddr->data_addr = ioaddr->cmd_addr + ATA_REG_DATA;
2194 ioaddr->error_addr = ioaddr->cmd_addr + ATA_REG_ERR;
2195 ioaddr->feature_addr = ioaddr->cmd_addr + ATA_REG_FEATURE;
2196 ioaddr->nsect_addr = ioaddr->cmd_addr + ATA_REG_NSECT;
2197 ioaddr->lbal_addr = ioaddr->cmd_addr + ATA_REG_LBAL;
2198 ioaddr->lbam_addr = ioaddr->cmd_addr + ATA_REG_LBAM;
2199 ioaddr->lbah_addr = ioaddr->cmd_addr + ATA_REG_LBAH;
2200 ioaddr->device_addr = ioaddr->cmd_addr + ATA_REG_DEVICE;
2201 ioaddr->status_addr = ioaddr->cmd_addr + ATA_REG_STATUS;
2202 ioaddr->command_addr = ioaddr->cmd_addr + ATA_REG_CMD;
2203}
2204
9363c382
TH
2205unsigned long ata_bmdma_mode_filter(struct ata_device *adev,
2206 unsigned long xfer_mask)
071ce34d
TH
2207{
2208 /* Filter out DMA modes if the device has been configured by
2209 the BIOS as PIO only */
2210
2211 if (adev->link->ap->ioaddr.bmdma_addr == NULL)
2212 xfer_mask &= ~(ATA_MASK_MWDMA | ATA_MASK_UDMA);
2213 return xfer_mask;
2214}
2215
272f7884
TH
2216/**
2217 * ata_bmdma_setup - Set up PCI IDE BMDMA transaction
2218 * @qc: Info associated with this ATA transaction.
2219 *
2220 * LOCKING:
2221 * spin_lock_irqsave(host lock)
2222 */
2223void ata_bmdma_setup(struct ata_queued_cmd *qc)
2224{
2225 struct ata_port *ap = qc->ap;
2226 unsigned int rw = (qc->tf.flags & ATA_TFLAG_WRITE);
2227 u8 dmactl;
2228
2229 /* load PRD table addr. */
2230 mb(); /* make sure PRD table writes are visible to controller */
2231 iowrite32(ap->prd_dma, ap->ioaddr.bmdma_addr + ATA_DMA_TABLE_OFS);
2232
2233 /* specify data direction, triple-check start bit is clear */
2234 dmactl = ioread8(ap->ioaddr.bmdma_addr + ATA_DMA_CMD);
2235 dmactl &= ~(ATA_DMA_WR | ATA_DMA_START);
2236 if (!rw)
2237 dmactl |= ATA_DMA_WR;
2238 iowrite8(dmactl, ap->ioaddr.bmdma_addr + ATA_DMA_CMD);
2239
2240 /* issue r/w command */
5682ed33 2241 ap->ops->sff_exec_command(ap, &qc->tf);
272f7884
TH
2242}
2243
2244/**
2245 * ata_bmdma_start - Start a PCI IDE BMDMA transaction
2246 * @qc: Info associated with this ATA transaction.
2247 *
2248 * LOCKING:
2249 * spin_lock_irqsave(host lock)
2250 */
2251void ata_bmdma_start(struct ata_queued_cmd *qc)
2252{
2253 struct ata_port *ap = qc->ap;
2254 u8 dmactl;
2255
2256 /* start host DMA transaction */
2257 dmactl = ioread8(ap->ioaddr.bmdma_addr + ATA_DMA_CMD);
2258 iowrite8(dmactl | ATA_DMA_START, ap->ioaddr.bmdma_addr + ATA_DMA_CMD);
2259
2260 /* Strictly, one may wish to issue an ioread8() here, to
2261 * flush the mmio write. However, control also passes
2262 * to the hardware at this point, and it will interrupt
2263 * us when we are to resume control. So, in effect,
2264 * we don't care when the mmio write flushes.
2265 * Further, a read of the DMA status register _immediately_
2266 * following the write may not be what certain flaky hardware
2267 * is expected, so I think it is best to not add a readb()
2268 * without first all the MMIO ATA cards/mobos.
2269 * Or maybe I'm just being paranoid.
2270 *
2271 * FIXME: The posting of this write means I/O starts are
2272 * unneccessarily delayed for MMIO
2273 */
2274}
2275
2276/**
2277 * ata_bmdma_stop - Stop PCI IDE BMDMA transfer
2278 * @qc: Command we are ending DMA for
2279 *
2280 * Clears the ATA_DMA_START flag in the dma control register
2281 *
2282 * May be used as the bmdma_stop() entry in ata_port_operations.
2283 *
2284 * LOCKING:
2285 * spin_lock_irqsave(host lock)
2286 */
2287void ata_bmdma_stop(struct ata_queued_cmd *qc)
2288{
2289 struct ata_port *ap = qc->ap;
2290 void __iomem *mmio = ap->ioaddr.bmdma_addr;
2291
2292 /* clear start/stop bit */
2293 iowrite8(ioread8(mmio + ATA_DMA_CMD) & ~ATA_DMA_START,
2294 mmio + ATA_DMA_CMD);
2295
2296 /* one-PIO-cycle guaranteed wait, per spec, for HDMA1:0 transition */
a57c1bad 2297 ata_sff_dma_pause(ap);
272f7884
TH
2298}
2299
2300/**
2301 * ata_bmdma_status - Read PCI IDE BMDMA status
2302 * @ap: Port associated with this ATA transaction.
2303 *
2304 * Read and return BMDMA status register.
2305 *
2306 * May be used as the bmdma_status() entry in ata_port_operations.
2307 *
2308 * LOCKING:
2309 * spin_lock_irqsave(host lock)
2310 */
2311u8 ata_bmdma_status(struct ata_port *ap)
2312{
2313 return ioread8(ap->ioaddr.bmdma_addr + ATA_DMA_STATUS);
2314}
2315
2316/**
624d5c51
TH
2317 * ata_bus_reset - reset host port and associated ATA channel
2318 * @ap: port to reset
2319 *
2320 * This is typically the first time we actually start issuing
2321 * commands to the ATA channel. We wait for BSY to clear, then
2322 * issue EXECUTE DEVICE DIAGNOSTIC command, polling for its
2323 * result. Determine what devices, if any, are on the channel
2324 * by looking at the device 0/1 error register. Look at the signature
2325 * stored in each device's taskfile registers, to determine if
2326 * the device is ATA or ATAPI.
2327 *
2328 * LOCKING:
2329 * PCI/etc. bus probe sem.
2330 * Obtains host lock.
2331 *
2332 * SIDE EFFECTS:
2333 * Sets ATA_FLAG_DISABLED if bus reset fails.
2334 *
2335 * DEPRECATED:
2336 * This function is only for drivers which still use old EH and
2337 * will be removed soon.
272f7884 2338 */
624d5c51 2339void ata_bus_reset(struct ata_port *ap)
272f7884 2340{
624d5c51
TH
2341 struct ata_device *device = ap->link.device;
2342 struct ata_ioports *ioaddr = &ap->ioaddr;
2343 unsigned int slave_possible = ap->flags & ATA_FLAG_SLAVE_POSS;
2344 u8 err;
2345 unsigned int dev0, dev1 = 0, devmask = 0;
2346 int rc;
2347
2348 DPRINTK("ENTER, host %u, port %u\n", ap->print_id, ap->port_no);
2349
2350 /* determine if device 0/1 are present */
2351 if (ap->flags & ATA_FLAG_SATA_RESET)
2352 dev0 = 1;
2353 else {
2354 dev0 = ata_devchk(ap, 0);
2355 if (slave_possible)
2356 dev1 = ata_devchk(ap, 1);
2357 }
2358
2359 if (dev0)
2360 devmask |= (1 << 0);
2361 if (dev1)
2362 devmask |= (1 << 1);
2363
2364 /* select device 0 again */
5682ed33 2365 ap->ops->sff_dev_select(ap, 0);
624d5c51
TH
2366
2367 /* issue bus reset */
2368 if (ap->flags & ATA_FLAG_SRST) {
341c2c95
TH
2369 rc = ata_bus_softreset(ap, devmask,
2370 ata_deadline(jiffies, 40000));
624d5c51
TH
2371 if (rc && rc != -ENODEV)
2372 goto err_out;
2373 }
2374
2375 /*
2376 * determine by signature whether we have ATA or ATAPI devices
2377 */
9363c382 2378 device[0].class = ata_sff_dev_classify(&device[0], dev0, &err);
624d5c51 2379 if ((slave_possible) && (err != 0x81))
9363c382 2380 device[1].class = ata_sff_dev_classify(&device[1], dev1, &err);
624d5c51
TH
2381
2382 /* is double-select really necessary? */
2383 if (device[1].class != ATA_DEV_NONE)
5682ed33 2384 ap->ops->sff_dev_select(ap, 1);
624d5c51 2385 if (device[0].class != ATA_DEV_NONE)
5682ed33 2386 ap->ops->sff_dev_select(ap, 0);
624d5c51
TH
2387
2388 /* if no devices were detected, disable this port */
2389 if ((device[0].class == ATA_DEV_NONE) &&
2390 (device[1].class == ATA_DEV_NONE))
2391 goto err_out;
2392
2393 if (ap->flags & (ATA_FLAG_SATA_RESET | ATA_FLAG_SRST)) {
2394 /* set up device control for ATA_FLAG_SATA_RESET */
2395 iowrite8(ap->ctl, ioaddr->ctl_addr);
2396 }
2397
2398 DPRINTK("EXIT\n");
2399 return;
2400
2401err_out:
2402 ata_port_printk(ap, KERN_ERR, "disabling port\n");
2403 ata_port_disable(ap);
2404
2405 DPRINTK("EXIT\n");
272f7884
TH
2406}
2407
1fdffbce 2408#ifdef CONFIG_PCI
4112e16a 2409
272f7884 2410/**
9363c382 2411 * ata_pci_bmdma_clear_simplex - attempt to kick device out of simplex
272f7884
TH
2412 * @pdev: PCI device
2413 *
2414 * Some PCI ATA devices report simplex mode but in fact can be told to
2415 * enter non simplex mode. This implements the necessary logic to
2416 * perform the task on such devices. Calling it on other devices will
2417 * have -undefined- behaviour.
2418 */
9363c382 2419int ata_pci_bmdma_clear_simplex(struct pci_dev *pdev)
4112e16a 2420{
272f7884
TH
2421 unsigned long bmdma = pci_resource_start(pdev, 4);
2422 u8 simplex;
a84471fe 2423
272f7884
TH
2424 if (bmdma == 0)
2425 return -ENOENT;
2426
2427 simplex = inb(bmdma + 0x02);
2428 outb(simplex & 0x60, bmdma + 0x02);
2429 simplex = inb(bmdma + 0x02);
2430 if (simplex & 0x80)
2431 return -EOPNOTSUPP;
2432 return 0;
2433}
2434
0f834de3 2435/**
9363c382 2436 * ata_pci_bmdma_init - acquire PCI BMDMA resources and init ATA host
0f834de3
TH
2437 * @host: target ATA host
2438 *
2439 * Acquire PCI BMDMA resources and initialize @host accordingly.
2440 *
2441 * LOCKING:
2442 * Inherited from calling layer (may sleep).
2443 *
2444 * RETURNS:
2445 * 0 on success, -errno otherwise.
2446 */
9363c382 2447int ata_pci_bmdma_init(struct ata_host *host)
1fdffbce 2448{
0f834de3
TH
2449 struct device *gdev = host->dev;
2450 struct pci_dev *pdev = to_pci_dev(gdev);
2451 int i, rc;
0d5ff566 2452
6fdc99a2
AC
2453 /* No BAR4 allocation: No DMA */
2454 if (pci_resource_start(pdev, 4) == 0)
2455 return 0;
2456
0f834de3
TH
2457 /* TODO: If we get no DMA mask we should fall back to PIO */
2458 rc = pci_set_dma_mask(pdev, ATA_DMA_MASK);
2459 if (rc)
2460 return rc;
2461 rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK);
2462 if (rc)
2463 return rc;
2464
2465 /* request and iomap DMA region */
35a10a80 2466 rc = pcim_iomap_regions(pdev, 1 << 4, dev_driver_string(gdev));
0f834de3
TH
2467 if (rc) {
2468 dev_printk(KERN_ERR, gdev, "failed to request/iomap BAR4\n");
2469 return -ENOMEM;
0d5ff566 2470 }
0f834de3 2471 host->iomap = pcim_iomap_table(pdev);
0d5ff566 2472
1626aeb8 2473 for (i = 0; i < 2; i++) {
0f834de3 2474 struct ata_port *ap = host->ports[i];
0f834de3
TH
2475 void __iomem *bmdma = host->iomap[4] + 8 * i;
2476
2477 if (ata_port_is_dummy(ap))
2478 continue;
2479
21b0ad4f 2480 ap->ioaddr.bmdma_addr = bmdma;
0f834de3
TH
2481 if ((!(ap->flags & ATA_FLAG_IGN_SIMPLEX)) &&
2482 (ioread8(bmdma + 2) & 0x80))
2483 host->flags |= ATA_HOST_SIMPLEX;
cbcdd875
TH
2484
2485 ata_port_desc(ap, "bmdma 0x%llx",
2486 (unsigned long long)pci_resource_start(pdev, 4) + 8 * i);
0d5ff566
TH
2487 }
2488
0f834de3
TH
2489 return 0;
2490}
2ec7df04 2491
272f7884
TH
2492static int ata_resources_present(struct pci_dev *pdev, int port)
2493{
2494 int i;
2495
2496 /* Check the PCI resources for this channel are enabled */
2497 port = port * 2;
2498 for (i = 0; i < 2; i ++) {
2499 if (pci_resource_start(pdev, port + i) == 0 ||
2500 pci_resource_len(pdev, port + i) == 0)
2501 return 0;
2502 }
2503 return 1;
2504}
2505
d491b27b 2506/**
9363c382 2507 * ata_pci_sff_init_host - acquire native PCI ATA resources and init host
d491b27b 2508 * @host: target ATA host
d491b27b 2509 *
1626aeb8
TH
2510 * Acquire native PCI ATA resources for @host and initialize the
2511 * first two ports of @host accordingly. Ports marked dummy are
2512 * skipped and allocation failure makes the port dummy.
d491b27b 2513 *
d583bc18
TH
2514 * Note that native PCI resources are valid even for legacy hosts
2515 * as we fix up pdev resources array early in boot, so this
2516 * function can be used for both native and legacy SFF hosts.
2517 *
d491b27b
TH
2518 * LOCKING:
2519 * Inherited from calling layer (may sleep).
2520 *
2521 * RETURNS:
1626aeb8
TH
2522 * 0 if at least one port is initialized, -ENODEV if no port is
2523 * available.
d491b27b 2524 */
9363c382 2525int ata_pci_sff_init_host(struct ata_host *host)
d491b27b
TH
2526{
2527 struct device *gdev = host->dev;
2528 struct pci_dev *pdev = to_pci_dev(gdev);
1626aeb8 2529 unsigned int mask = 0;
d491b27b
TH
2530 int i, rc;
2531
d491b27b
TH
2532 /* request, iomap BARs and init port addresses accordingly */
2533 for (i = 0; i < 2; i++) {
2534 struct ata_port *ap = host->ports[i];
2535 int base = i * 2;
2536 void __iomem * const *iomap;
2537
1626aeb8
TH
2538 if (ata_port_is_dummy(ap))
2539 continue;
2540
2541 /* Discard disabled ports. Some controllers show
2542 * their unused channels this way. Disabled ports are
2543 * made dummy.
2544 */
2545 if (!ata_resources_present(pdev, i)) {
2546 ap->ops = &ata_dummy_port_ops;
d491b27b 2547 continue;
1626aeb8 2548 }
d491b27b 2549
35a10a80
TH
2550 rc = pcim_iomap_regions(pdev, 0x3 << base,
2551 dev_driver_string(gdev));
d491b27b 2552 if (rc) {
1626aeb8
TH
2553 dev_printk(KERN_WARNING, gdev,
2554 "failed to request/iomap BARs for port %d "
2555 "(errno=%d)\n", i, rc);
d491b27b
TH
2556 if (rc == -EBUSY)
2557 pcim_pin_device(pdev);
1626aeb8
TH
2558 ap->ops = &ata_dummy_port_ops;
2559 continue;
d491b27b
TH
2560 }
2561 host->iomap = iomap = pcim_iomap_table(pdev);
2562
2563 ap->ioaddr.cmd_addr = iomap[base];
2564 ap->ioaddr.altstatus_addr =
2565 ap->ioaddr.ctl_addr = (void __iomem *)
2566 ((unsigned long)iomap[base + 1] | ATA_PCI_CTL_OFS);
9363c382 2567 ata_sff_std_ports(&ap->ioaddr);
1626aeb8 2568
cbcdd875
TH
2569 ata_port_desc(ap, "cmd 0x%llx ctl 0x%llx",
2570 (unsigned long long)pci_resource_start(pdev, base),
2571 (unsigned long long)pci_resource_start(pdev, base + 1));
2572
1626aeb8
TH
2573 mask |= 1 << i;
2574 }
2575
2576 if (!mask) {
2577 dev_printk(KERN_ERR, gdev, "no available native port\n");
2578 return -ENODEV;
d491b27b
TH
2579 }
2580
2581 return 0;
2582}
2583
21b0ad4f 2584/**
9363c382 2585 * ata_pci_sff_prepare_host - helper to prepare native PCI ATA host
21b0ad4f 2586 * @pdev: target PCI device
1626aeb8 2587 * @ppi: array of port_info, must be enough for two ports
21b0ad4f
TH
2588 * @r_host: out argument for the initialized ATA host
2589 *
2590 * Helper to allocate ATA host for @pdev, acquire all native PCI
2591 * resources and initialize it accordingly in one go.
2592 *
2593 * LOCKING:
2594 * Inherited from calling layer (may sleep).
2595 *
2596 * RETURNS:
2597 * 0 on success, -errno otherwise.
2598 */
9363c382 2599int ata_pci_sff_prepare_host(struct pci_dev *pdev,
d583bc18
TH
2600 const struct ata_port_info * const * ppi,
2601 struct ata_host **r_host)
21b0ad4f
TH
2602{
2603 struct ata_host *host;
21b0ad4f
TH
2604 int rc;
2605
2606 if (!devres_open_group(&pdev->dev, NULL, GFP_KERNEL))
2607 return -ENOMEM;
2608
2609 host = ata_host_alloc_pinfo(&pdev->dev, ppi, 2);
2610 if (!host) {
2611 dev_printk(KERN_ERR, &pdev->dev,
2612 "failed to allocate ATA host\n");
2613 rc = -ENOMEM;
2614 goto err_out;
2615 }
2616
9363c382 2617 rc = ata_pci_sff_init_host(host);
21b0ad4f
TH
2618 if (rc)
2619 goto err_out;
2620
2621 /* init DMA related stuff */
9363c382 2622 rc = ata_pci_bmdma_init(host);
21b0ad4f
TH
2623 if (rc)
2624 goto err_bmdma;
2625
2626 devres_remove_group(&pdev->dev, NULL);
2627 *r_host = host;
2628 return 0;
2629
2630 err_bmdma:
2631 /* This is necessary because PCI and iomap resources are
2632 * merged and releasing the top group won't release the
2633 * acquired resources if some of those have been acquired
2634 * before entering this function.
2635 */
2636 pcim_iounmap_regions(pdev, 0xf);
2637 err_out:
2638 devres_release_group(&pdev->dev, NULL);
2639 return rc;
2640}
2641
4e6b79fa 2642/**
9363c382 2643 * ata_pci_sff_activate_host - start SFF host, request IRQ and register it
4e6b79fa
TH
2644 * @host: target SFF ATA host
2645 * @irq_handler: irq_handler used when requesting IRQ(s)
2646 * @sht: scsi_host_template to use when registering the host
2647 *
2648 * This is the counterpart of ata_host_activate() for SFF ATA
2649 * hosts. This separate helper is necessary because SFF hosts
2650 * use two separate interrupts in legacy mode.
2651 *
2652 * LOCKING:
2653 * Inherited from calling layer (may sleep).
2654 *
2655 * RETURNS:
2656 * 0 on success, -errno otherwise.
2657 */
9363c382 2658int ata_pci_sff_activate_host(struct ata_host *host,
4e6b79fa
TH
2659 irq_handler_t irq_handler,
2660 struct scsi_host_template *sht)
2661{
2662 struct device *dev = host->dev;
2663 struct pci_dev *pdev = to_pci_dev(dev);
2664 const char *drv_name = dev_driver_string(host->dev);
2665 int legacy_mode = 0, rc;
2666
2667 rc = ata_host_start(host);
2668 if (rc)
2669 return rc;
2670
2671 if ((pdev->class >> 8) == PCI_CLASS_STORAGE_IDE) {
2672 u8 tmp8, mask;
2673
2674 /* TODO: What if one channel is in native mode ... */
2675 pci_read_config_byte(pdev, PCI_CLASS_PROG, &tmp8);
2676 mask = (1 << 2) | (1 << 0);
2677 if ((tmp8 & mask) != mask)
2678 legacy_mode = 1;
2679#if defined(CONFIG_NO_ATA_LEGACY)
2680 /* Some platforms with PCI limits cannot address compat
2681 port space. In that case we punt if their firmware has
2682 left a device in compatibility mode */
2683 if (legacy_mode) {
2684 printk(KERN_ERR "ata: Compatibility mode ATA is not supported on this platform, skipping.\n");
2685 return -EOPNOTSUPP;
2686 }
2687#endif
2688 }
2689
2690 if (!devres_open_group(dev, NULL, GFP_KERNEL))
2691 return -ENOMEM;
2692
2693 if (!legacy_mode && pdev->irq) {
2694 rc = devm_request_irq(dev, pdev->irq, irq_handler,
2695 IRQF_SHARED, drv_name, host);
2696 if (rc)
2697 goto out;
2698
2699 ata_port_desc(host->ports[0], "irq %d", pdev->irq);
2700 ata_port_desc(host->ports[1], "irq %d", pdev->irq);
2701 } else if (legacy_mode) {
2702 if (!ata_port_is_dummy(host->ports[0])) {
2703 rc = devm_request_irq(dev, ATA_PRIMARY_IRQ(pdev),
2704 irq_handler, IRQF_SHARED,
2705 drv_name, host);
2706 if (rc)
2707 goto out;
2708
2709 ata_port_desc(host->ports[0], "irq %d",
2710 ATA_PRIMARY_IRQ(pdev));
2711 }
2712
2713 if (!ata_port_is_dummy(host->ports[1])) {
2714 rc = devm_request_irq(dev, ATA_SECONDARY_IRQ(pdev),
2715 irq_handler, IRQF_SHARED,
2716 drv_name, host);
2717 if (rc)
2718 goto out;
2719
2720 ata_port_desc(host->ports[1], "irq %d",
2721 ATA_SECONDARY_IRQ(pdev));
2722 }
2723 }
2724
2725 rc = ata_host_register(host, sht);
2726 out:
2727 if (rc == 0)
2728 devres_remove_group(dev, NULL);
2729 else
2730 devres_release_group(dev, NULL);
2731
2732 return rc;
2733}
2734
1fdffbce 2735/**
9363c382 2736 * ata_pci_sff_init_one - Initialize/register PCI IDE host controller
1fdffbce 2737 * @pdev: Controller to be initialized
1626aeb8 2738 * @ppi: array of port_info, must be enough for two ports
1bd5b715 2739 * @sht: scsi_host_template to use when registering the host
887125e3 2740 * @host_priv: host private_data
1fdffbce
JG
2741 *
2742 * This is a helper function which can be called from a driver's
2743 * xxx_init_one() probe function if the hardware uses traditional
2744 * IDE taskfile registers.
2745 *
2746 * This function calls pci_enable_device(), reserves its register
2747 * regions, sets the dma mask, enables bus master mode, and calls
2748 * ata_device_add()
2749 *
2ec7df04
AC
2750 * ASSUMPTION:
2751 * Nobody makes a single channel controller that appears solely as
2752 * the secondary legacy port on PCI.
2753 *
1fdffbce
JG
2754 * LOCKING:
2755 * Inherited from PCI layer (may sleep).
2756 *
2757 * RETURNS:
2758 * Zero on success, negative on errno-based value on error.
2759 */
9363c382
TH
2760int ata_pci_sff_init_one(struct pci_dev *pdev,
2761 const struct ata_port_info * const * ppi,
2762 struct scsi_host_template *sht, void *host_priv)
1fdffbce 2763{
f0d36efd 2764 struct device *dev = &pdev->dev;
1626aeb8 2765 const struct ata_port_info *pi = NULL;
0f834de3 2766 struct ata_host *host = NULL;
1626aeb8 2767 int i, rc;
1fdffbce
JG
2768
2769 DPRINTK("ENTER\n");
2770
1626aeb8
TH
2771 /* look up the first valid port_info */
2772 for (i = 0; i < 2 && ppi[i]; i++) {
2773 if (ppi[i]->port_ops != &ata_dummy_port_ops) {
2774 pi = ppi[i];
2775 break;
2776 }
2777 }
f0d36efd 2778
1626aeb8
TH
2779 if (!pi) {
2780 dev_printk(KERN_ERR, &pdev->dev,
2781 "no valid port_info specified\n");
2782 return -EINVAL;
2783 }
c791c306 2784
1626aeb8
TH
2785 if (!devres_open_group(dev, NULL, GFP_KERNEL))
2786 return -ENOMEM;
1fdffbce 2787
f0d36efd 2788 rc = pcim_enable_device(pdev);
1fdffbce 2789 if (rc)
4e6b79fa 2790 goto out;
1fdffbce 2791
4e6b79fa 2792 /* prepare and activate SFF host */
9363c382 2793 rc = ata_pci_sff_prepare_host(pdev, ppi, &host);
d583bc18 2794 if (rc)
4e6b79fa 2795 goto out;
887125e3 2796 host->private_data = host_priv;
d491b27b 2797
d491b27b 2798 pci_set_master(pdev);
9363c382 2799 rc = ata_pci_sff_activate_host(host, ata_sff_interrupt, sht);
4e6b79fa
TH
2800 out:
2801 if (rc == 0)
2802 devres_remove_group(&pdev->dev, NULL);
2803 else
2804 devres_release_group(&pdev->dev, NULL);
d491b27b 2805
1fdffbce
JG
2806 return rc;
2807}
2808
2809#endif /* CONFIG_PCI */
2810
624d5c51
TH
2811EXPORT_SYMBOL_GPL(ata_sff_port_ops);
2812EXPORT_SYMBOL_GPL(ata_bmdma_port_ops);
9363c382
TH
2813EXPORT_SYMBOL_GPL(ata_sff_qc_prep);
2814EXPORT_SYMBOL_GPL(ata_sff_dumb_qc_prep);
2815EXPORT_SYMBOL_GPL(ata_sff_dev_select);
2816EXPORT_SYMBOL_GPL(ata_sff_check_status);
a57c1bad
AC
2817EXPORT_SYMBOL_GPL(ata_sff_dma_pause);
2818EXPORT_SYMBOL_GPL(ata_sff_pause);
9363c382
TH
2819EXPORT_SYMBOL_GPL(ata_sff_busy_sleep);
2820EXPORT_SYMBOL_GPL(ata_sff_wait_ready);
2821EXPORT_SYMBOL_GPL(ata_sff_tf_load);
2822EXPORT_SYMBOL_GPL(ata_sff_tf_read);
2823EXPORT_SYMBOL_GPL(ata_sff_exec_command);
2824EXPORT_SYMBOL_GPL(ata_sff_data_xfer);
2825EXPORT_SYMBOL_GPL(ata_sff_data_xfer_noirq);
2826EXPORT_SYMBOL_GPL(ata_sff_irq_on);
2827EXPORT_SYMBOL_GPL(ata_sff_irq_clear);
2828EXPORT_SYMBOL_GPL(ata_sff_hsm_move);
2829EXPORT_SYMBOL_GPL(ata_sff_qc_issue);
22183bf5 2830EXPORT_SYMBOL_GPL(ata_sff_qc_fill_rtf);
9363c382
TH
2831EXPORT_SYMBOL_GPL(ata_sff_host_intr);
2832EXPORT_SYMBOL_GPL(ata_sff_interrupt);
2833EXPORT_SYMBOL_GPL(ata_sff_freeze);
2834EXPORT_SYMBOL_GPL(ata_sff_thaw);
2835EXPORT_SYMBOL_GPL(ata_sff_prereset);
2836EXPORT_SYMBOL_GPL(ata_sff_dev_classify);
2837EXPORT_SYMBOL_GPL(ata_sff_wait_after_reset);
2838EXPORT_SYMBOL_GPL(ata_sff_softreset);
2839EXPORT_SYMBOL_GPL(sata_sff_hardreset);
2840EXPORT_SYMBOL_GPL(ata_sff_postreset);
2841EXPORT_SYMBOL_GPL(ata_sff_error_handler);
2842EXPORT_SYMBOL_GPL(ata_sff_post_internal_cmd);
624d5c51 2843EXPORT_SYMBOL_GPL(ata_sff_port_start);
9363c382
TH
2844EXPORT_SYMBOL_GPL(ata_sff_std_ports);
2845EXPORT_SYMBOL_GPL(ata_bmdma_mode_filter);
624d5c51
TH
2846EXPORT_SYMBOL_GPL(ata_bmdma_setup);
2847EXPORT_SYMBOL_GPL(ata_bmdma_start);
2848EXPORT_SYMBOL_GPL(ata_bmdma_stop);
2849EXPORT_SYMBOL_GPL(ata_bmdma_status);
2850EXPORT_SYMBOL_GPL(ata_bus_reset);
2851#ifdef CONFIG_PCI
9363c382
TH
2852EXPORT_SYMBOL_GPL(ata_pci_bmdma_clear_simplex);
2853EXPORT_SYMBOL_GPL(ata_pci_bmdma_init);
2854EXPORT_SYMBOL_GPL(ata_pci_sff_init_host);
2855EXPORT_SYMBOL_GPL(ata_pci_sff_prepare_host);
2856EXPORT_SYMBOL_GPL(ata_pci_sff_activate_host);
2857EXPORT_SYMBOL_GPL(ata_pci_sff_init_one);
624d5c51 2858#endif /* CONFIG_PCI */
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