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a480167b VK |
1 | /* |
2 | * drivers/ata/pata_arasan_cf.c | |
3 | * | |
4 | * Arasan Compact Flash host controller source file | |
5 | * | |
6 | * Copyright (C) 2011 ST Microelectronics | |
10d8935f | 7 | * Viresh Kumar <viresh.linux@gmail.com> |
a480167b VK |
8 | * |
9 | * This file is licensed under the terms of the GNU General Public | |
10 | * License version 2. This program is licensed "as is" without any | |
11 | * warranty of any kind, whether express or implied. | |
12 | */ | |
13 | ||
14 | /* | |
15 | * The Arasan CompactFlash Device Controller IP core has three basic modes of | |
16 | * operation: PC card ATA using I/O mode, PC card ATA using memory mode, PC card | |
17 | * ATA using true IDE modes. This driver supports only True IDE mode currently. | |
18 | * | |
19 | * Arasan CF Controller shares global irq register with Arasan XD Controller. | |
20 | * | |
21 | * Tested on arch/arm/mach-spear13xx | |
22 | */ | |
23 | ||
24 | #include <linux/ata.h> | |
25 | #include <linux/clk.h> | |
26 | #include <linux/completion.h> | |
27 | #include <linux/delay.h> | |
28 | #include <linux/dmaengine.h> | |
29 | #include <linux/io.h> | |
30 | #include <linux/irq.h> | |
31 | #include <linux/kernel.h> | |
32 | #include <linux/libata.h> | |
33 | #include <linux/module.h> | |
26fdaa74 | 34 | #include <linux/of.h> |
a480167b VK |
35 | #include <linux/pata_arasan_cf_data.h> |
36 | #include <linux/platform_device.h> | |
37 | #include <linux/pm.h> | |
38 | #include <linux/slab.h> | |
39 | #include <linux/spinlock.h> | |
40 | #include <linux/types.h> | |
41 | #include <linux/workqueue.h> | |
42 | ||
43 | #define DRIVER_NAME "arasan_cf" | |
44 | #define TIMEOUT msecs_to_jiffies(3000) | |
45 | ||
46 | /* Registers */ | |
47 | /* CompactFlash Interface Status */ | |
48 | #define CFI_STS 0x000 | |
49 | #define STS_CHG (1) | |
50 | #define BIN_AUDIO_OUT (1 << 1) | |
51 | #define CARD_DETECT1 (1 << 2) | |
52 | #define CARD_DETECT2 (1 << 3) | |
53 | #define INP_ACK (1 << 4) | |
54 | #define CARD_READY (1 << 5) | |
55 | #define IO_READY (1 << 6) | |
56 | #define B16_IO_PORT_SEL (1 << 7) | |
57 | /* IRQ */ | |
58 | #define IRQ_STS 0x004 | |
59 | /* Interrupt Enable */ | |
60 | #define IRQ_EN 0x008 | |
61 | #define CARD_DETECT_IRQ (1) | |
62 | #define STATUS_CHNG_IRQ (1 << 1) | |
63 | #define MEM_MODE_IRQ (1 << 2) | |
64 | #define IO_MODE_IRQ (1 << 3) | |
65 | #define TRUE_IDE_MODE_IRQ (1 << 8) | |
66 | #define PIO_XFER_ERR_IRQ (1 << 9) | |
67 | #define BUF_AVAIL_IRQ (1 << 10) | |
68 | #define XFER_DONE_IRQ (1 << 11) | |
69 | #define IGNORED_IRQS (STATUS_CHNG_IRQ | MEM_MODE_IRQ | IO_MODE_IRQ |\ | |
70 | TRUE_IDE_MODE_IRQ) | |
71 | #define TRUE_IDE_IRQS (CARD_DETECT_IRQ | PIO_XFER_ERR_IRQ |\ | |
72 | BUF_AVAIL_IRQ | XFER_DONE_IRQ) | |
73 | /* Operation Mode */ | |
74 | #define OP_MODE 0x00C | |
75 | #define CARD_MODE_MASK (0x3) | |
76 | #define MEM_MODE (0x0) | |
77 | #define IO_MODE (0x1) | |
78 | #define TRUE_IDE_MODE (0x2) | |
79 | ||
80 | #define CARD_TYPE_MASK (1 << 2) | |
81 | #define CF_CARD (0) | |
82 | #define CF_PLUS_CARD (1 << 2) | |
83 | ||
84 | #define CARD_RESET (1 << 3) | |
85 | #define CFHOST_ENB (1 << 4) | |
86 | #define OUTPUTS_TRISTATE (1 << 5) | |
87 | #define ULTRA_DMA_ENB (1 << 8) | |
88 | #define MULTI_WORD_DMA_ENB (1 << 9) | |
89 | #define DRQ_BLOCK_SIZE_MASK (0x3 << 11) | |
90 | #define DRQ_BLOCK_SIZE_512 (0) | |
91 | #define DRQ_BLOCK_SIZE_1024 (1 << 11) | |
92 | #define DRQ_BLOCK_SIZE_2048 (2 << 11) | |
93 | #define DRQ_BLOCK_SIZE_4096 (3 << 11) | |
94 | /* CF Interface Clock Configuration */ | |
95 | #define CLK_CFG 0x010 | |
96 | #define CF_IF_CLK_MASK (0XF) | |
97 | /* CF Timing Mode Configuration */ | |
98 | #define TM_CFG 0x014 | |
99 | #define MEM_MODE_TIMING_MASK (0x3) | |
100 | #define MEM_MODE_TIMING_250NS (0x0) | |
101 | #define MEM_MODE_TIMING_120NS (0x1) | |
102 | #define MEM_MODE_TIMING_100NS (0x2) | |
103 | #define MEM_MODE_TIMING_80NS (0x3) | |
104 | ||
105 | #define IO_MODE_TIMING_MASK (0x3 << 2) | |
106 | #define IO_MODE_TIMING_250NS (0x0 << 2) | |
107 | #define IO_MODE_TIMING_120NS (0x1 << 2) | |
108 | #define IO_MODE_TIMING_100NS (0x2 << 2) | |
109 | #define IO_MODE_TIMING_80NS (0x3 << 2) | |
110 | ||
111 | #define TRUEIDE_PIO_TIMING_MASK (0x7 << 4) | |
112 | #define TRUEIDE_PIO_TIMING_SHIFT 4 | |
113 | ||
114 | #define TRUEIDE_MWORD_DMA_TIMING_MASK (0x7 << 7) | |
115 | #define TRUEIDE_MWORD_DMA_TIMING_SHIFT 7 | |
116 | ||
117 | #define ULTRA_DMA_TIMING_MASK (0x7 << 10) | |
118 | #define ULTRA_DMA_TIMING_SHIFT 10 | |
119 | /* CF Transfer Address */ | |
120 | #define XFER_ADDR 0x014 | |
121 | #define XFER_ADDR_MASK (0x7FF) | |
122 | #define MAX_XFER_COUNT 0x20000u | |
123 | /* Transfer Control */ | |
124 | #define XFER_CTR 0x01C | |
125 | #define XFER_COUNT_MASK (0x3FFFF) | |
126 | #define ADDR_INC_DISABLE (1 << 24) | |
127 | #define XFER_WIDTH_MASK (1 << 25) | |
128 | #define XFER_WIDTH_8B (0) | |
129 | #define XFER_WIDTH_16B (1 << 25) | |
130 | ||
131 | #define MEM_TYPE_MASK (1 << 26) | |
132 | #define MEM_TYPE_COMMON (0) | |
133 | #define MEM_TYPE_ATTRIBUTE (1 << 26) | |
134 | ||
135 | #define MEM_IO_XFER_MASK (1 << 27) | |
136 | #define MEM_XFER (0) | |
137 | #define IO_XFER (1 << 27) | |
138 | ||
139 | #define DMA_XFER_MODE (1 << 28) | |
140 | ||
141 | #define AHB_BUS_NORMAL_PIO_OPRTN (~(1 << 29)) | |
142 | #define XFER_DIR_MASK (1 << 30) | |
143 | #define XFER_READ (0) | |
144 | #define XFER_WRITE (1 << 30) | |
145 | ||
146 | #define XFER_START (1 << 31) | |
147 | /* Write Data Port */ | |
148 | #define WRITE_PORT 0x024 | |
149 | /* Read Data Port */ | |
150 | #define READ_PORT 0x028 | |
151 | /* ATA Data Port */ | |
152 | #define ATA_DATA_PORT 0x030 | |
153 | #define ATA_DATA_PORT_MASK (0xFFFF) | |
154 | /* ATA Error/Features */ | |
155 | #define ATA_ERR_FTR 0x034 | |
156 | /* ATA Sector Count */ | |
157 | #define ATA_SC 0x038 | |
158 | /* ATA Sector Number */ | |
159 | #define ATA_SN 0x03C | |
160 | /* ATA Cylinder Low */ | |
161 | #define ATA_CL 0x040 | |
162 | /* ATA Cylinder High */ | |
163 | #define ATA_CH 0x044 | |
164 | /* ATA Select Card/Head */ | |
165 | #define ATA_SH 0x048 | |
166 | /* ATA Status-Command */ | |
167 | #define ATA_STS_CMD 0x04C | |
168 | /* ATA Alternate Status/Device Control */ | |
169 | #define ATA_ASTS_DCTR 0x050 | |
170 | /* Extended Write Data Port 0x200-0x3FC */ | |
171 | #define EXT_WRITE_PORT 0x200 | |
172 | /* Extended Read Data Port 0x400-0x5FC */ | |
173 | #define EXT_READ_PORT 0x400 | |
174 | #define FIFO_SIZE 0x200u | |
175 | /* Global Interrupt Status */ | |
176 | #define GIRQ_STS 0x800 | |
177 | /* Global Interrupt Status enable */ | |
178 | #define GIRQ_STS_EN 0x804 | |
179 | /* Global Interrupt Signal enable */ | |
180 | #define GIRQ_SGN_EN 0x808 | |
181 | #define GIRQ_CF (1) | |
182 | #define GIRQ_XD (1 << 1) | |
183 | ||
184 | /* Compact Flash Controller Dev Structure */ | |
185 | struct arasan_cf_dev { | |
186 | /* pointer to ata_host structure */ | |
187 | struct ata_host *host; | |
d14fb1e9 | 188 | /* clk structure */ |
a480167b | 189 | struct clk *clk; |
a480167b VK |
190 | |
191 | /* physical base address of controller */ | |
192 | dma_addr_t pbase; | |
193 | /* virtual base address of controller */ | |
194 | void __iomem *vbase; | |
195 | /* irq number*/ | |
196 | int irq; | |
197 | ||
198 | /* status to be updated to framework regarding DMA transfer */ | |
199 | u8 dma_status; | |
200 | /* Card is present or Not */ | |
201 | u8 card_present; | |
202 | ||
203 | /* dma specific */ | |
204 | /* Completion for transfer complete interrupt from controller */ | |
205 | struct completion cf_completion; | |
206 | /* Completion for DMA transfer complete. */ | |
207 | struct completion dma_completion; | |
208 | /* Dma channel allocated */ | |
209 | struct dma_chan *dma_chan; | |
210 | /* Mask for DMA transfers */ | |
211 | dma_cap_mask_t mask; | |
60a230e4 VK |
212 | /* dma channel private data */ |
213 | void *dma_priv; | |
a480167b VK |
214 | /* DMA transfer work */ |
215 | struct work_struct work; | |
216 | /* DMA delayed finish work */ | |
217 | struct delayed_work dwork; | |
218 | /* qc to be transferred using DMA */ | |
219 | struct ata_queued_cmd *qc; | |
220 | }; | |
221 | ||
222 | static struct scsi_host_template arasan_cf_sht = { | |
223 | ATA_BASE_SHT(DRIVER_NAME), | |
224 | .sg_tablesize = SG_NONE, | |
225 | .dma_boundary = 0xFFFFFFFFUL, | |
226 | }; | |
227 | ||
228 | static void cf_dumpregs(struct arasan_cf_dev *acdev) | |
229 | { | |
230 | struct device *dev = acdev->host->dev; | |
231 | ||
232 | dev_dbg(dev, ": =========== REGISTER DUMP ==========="); | |
233 | dev_dbg(dev, ": CFI_STS: %x", readl(acdev->vbase + CFI_STS)); | |
234 | dev_dbg(dev, ": IRQ_STS: %x", readl(acdev->vbase + IRQ_STS)); | |
235 | dev_dbg(dev, ": IRQ_EN: %x", readl(acdev->vbase + IRQ_EN)); | |
236 | dev_dbg(dev, ": OP_MODE: %x", readl(acdev->vbase + OP_MODE)); | |
237 | dev_dbg(dev, ": CLK_CFG: %x", readl(acdev->vbase + CLK_CFG)); | |
238 | dev_dbg(dev, ": TM_CFG: %x", readl(acdev->vbase + TM_CFG)); | |
239 | dev_dbg(dev, ": XFER_CTR: %x", readl(acdev->vbase + XFER_CTR)); | |
240 | dev_dbg(dev, ": GIRQ_STS: %x", readl(acdev->vbase + GIRQ_STS)); | |
241 | dev_dbg(dev, ": GIRQ_STS_EN: %x", readl(acdev->vbase + GIRQ_STS_EN)); | |
242 | dev_dbg(dev, ": GIRQ_SGN_EN: %x", readl(acdev->vbase + GIRQ_SGN_EN)); | |
243 | dev_dbg(dev, ": ====================================="); | |
244 | } | |
245 | ||
246 | /* Enable/Disable global interrupts shared between CF and XD ctrlr. */ | |
247 | static void cf_ginterrupt_enable(struct arasan_cf_dev *acdev, bool enable) | |
248 | { | |
249 | /* enable should be 0 or 1 */ | |
250 | writel(enable, acdev->vbase + GIRQ_STS_EN); | |
251 | writel(enable, acdev->vbase + GIRQ_SGN_EN); | |
252 | } | |
253 | ||
254 | /* Enable/Disable CF interrupts */ | |
255 | static inline void | |
256 | cf_interrupt_enable(struct arasan_cf_dev *acdev, u32 mask, bool enable) | |
257 | { | |
258 | u32 val = readl(acdev->vbase + IRQ_EN); | |
259 | /* clear & enable/disable irqs */ | |
260 | if (enable) { | |
261 | writel(mask, acdev->vbase + IRQ_STS); | |
262 | writel(val | mask, acdev->vbase + IRQ_EN); | |
263 | } else | |
264 | writel(val & ~mask, acdev->vbase + IRQ_EN); | |
265 | } | |
266 | ||
267 | static inline void cf_card_reset(struct arasan_cf_dev *acdev) | |
268 | { | |
269 | u32 val = readl(acdev->vbase + OP_MODE); | |
270 | ||
271 | writel(val | CARD_RESET, acdev->vbase + OP_MODE); | |
272 | udelay(200); | |
273 | writel(val & ~CARD_RESET, acdev->vbase + OP_MODE); | |
274 | } | |
275 | ||
276 | static inline void cf_ctrl_reset(struct arasan_cf_dev *acdev) | |
277 | { | |
278 | writel(readl(acdev->vbase + OP_MODE) & ~CFHOST_ENB, | |
279 | acdev->vbase + OP_MODE); | |
280 | writel(readl(acdev->vbase + OP_MODE) | CFHOST_ENB, | |
281 | acdev->vbase + OP_MODE); | |
282 | } | |
283 | ||
284 | static void cf_card_detect(struct arasan_cf_dev *acdev, bool hotplugged) | |
285 | { | |
286 | struct ata_port *ap = acdev->host->ports[0]; | |
287 | struct ata_eh_info *ehi = &ap->link.eh_info; | |
288 | u32 val = readl(acdev->vbase + CFI_STS); | |
289 | ||
290 | /* Both CD1 & CD2 should be low if card inserted completely */ | |
291 | if (!(val & (CARD_DETECT1 | CARD_DETECT2))) { | |
292 | if (acdev->card_present) | |
293 | return; | |
294 | acdev->card_present = 1; | |
295 | cf_card_reset(acdev); | |
296 | } else { | |
297 | if (!acdev->card_present) | |
298 | return; | |
299 | acdev->card_present = 0; | |
300 | } | |
301 | ||
302 | if (hotplugged) { | |
303 | ata_ehi_hotplugged(ehi); | |
304 | ata_port_freeze(ap); | |
305 | } | |
306 | } | |
307 | ||
308 | static int cf_init(struct arasan_cf_dev *acdev) | |
309 | { | |
310 | struct arasan_cf_pdata *pdata = dev_get_platdata(acdev->host->dev); | |
311 | unsigned long flags; | |
312 | int ret = 0; | |
313 | ||
3f09e6c0 | 314 | ret = clk_prepare_enable(acdev->clk); |
a480167b VK |
315 | if (ret) { |
316 | dev_dbg(acdev->host->dev, "clock enable failed"); | |
317 | return ret; | |
318 | } | |
a480167b VK |
319 | |
320 | spin_lock_irqsave(&acdev->host->lock, flags); | |
321 | /* configure CF interface clock */ | |
322 | writel((pdata->cf_if_clk <= CF_IF_CLK_200M) ? pdata->cf_if_clk : | |
323 | CF_IF_CLK_166M, acdev->vbase + CLK_CFG); | |
324 | ||
325 | writel(TRUE_IDE_MODE | CFHOST_ENB, acdev->vbase + OP_MODE); | |
326 | cf_interrupt_enable(acdev, CARD_DETECT_IRQ, 1); | |
327 | cf_ginterrupt_enable(acdev, 1); | |
328 | spin_unlock_irqrestore(&acdev->host->lock, flags); | |
329 | ||
330 | return ret; | |
331 | } | |
332 | ||
333 | static void cf_exit(struct arasan_cf_dev *acdev) | |
334 | { | |
335 | unsigned long flags; | |
336 | ||
337 | spin_lock_irqsave(&acdev->host->lock, flags); | |
338 | cf_ginterrupt_enable(acdev, 0); | |
339 | cf_interrupt_enable(acdev, TRUE_IDE_IRQS, 0); | |
340 | cf_card_reset(acdev); | |
341 | writel(readl(acdev->vbase + OP_MODE) & ~CFHOST_ENB, | |
342 | acdev->vbase + OP_MODE); | |
343 | spin_unlock_irqrestore(&acdev->host->lock, flags); | |
3f09e6c0 | 344 | clk_disable_unprepare(acdev->clk); |
a480167b VK |
345 | } |
346 | ||
347 | static void dma_callback(void *dev) | |
348 | { | |
349 | struct arasan_cf_dev *acdev = (struct arasan_cf_dev *) dev; | |
350 | ||
351 | complete(&acdev->dma_completion); | |
352 | } | |
353 | ||
354 | static bool filter(struct dma_chan *chan, void *slave) | |
355 | { | |
60a230e4 | 356 | chan->private = slave; |
a480167b VK |
357 | return true; |
358 | } | |
359 | ||
360 | static inline void dma_complete(struct arasan_cf_dev *acdev) | |
361 | { | |
362 | struct ata_queued_cmd *qc = acdev->qc; | |
363 | unsigned long flags; | |
364 | ||
365 | acdev->qc = NULL; | |
366 | ata_sff_interrupt(acdev->irq, acdev->host); | |
367 | ||
368 | spin_lock_irqsave(&acdev->host->lock, flags); | |
369 | if (unlikely(qc->err_mask) && ata_is_dma(qc->tf.protocol)) | |
370 | ata_ehi_push_desc(&qc->ap->link.eh_info, "DMA Failed: Timeout"); | |
371 | spin_unlock_irqrestore(&acdev->host->lock, flags); | |
372 | } | |
373 | ||
374 | static inline int wait4buf(struct arasan_cf_dev *acdev) | |
375 | { | |
376 | if (!wait_for_completion_timeout(&acdev->cf_completion, TIMEOUT)) { | |
377 | u32 rw = acdev->qc->tf.flags & ATA_TFLAG_WRITE; | |
378 | ||
379 | dev_err(acdev->host->dev, "%s TimeOut", rw ? "write" : "read"); | |
380 | return -ETIMEDOUT; | |
381 | } | |
382 | ||
25985edc | 383 | /* Check if PIO Error interrupt has occurred */ |
a480167b VK |
384 | if (acdev->dma_status & ATA_DMA_ERR) |
385 | return -EAGAIN; | |
386 | ||
387 | return 0; | |
388 | } | |
389 | ||
390 | static int | |
391 | dma_xfer(struct arasan_cf_dev *acdev, dma_addr_t src, dma_addr_t dest, u32 len) | |
392 | { | |
393 | struct dma_async_tx_descriptor *tx; | |
394 | struct dma_chan *chan = acdev->dma_chan; | |
395 | dma_cookie_t cookie; | |
396 | unsigned long flags = DMA_PREP_INTERRUPT | DMA_COMPL_SKIP_SRC_UNMAP | | |
397 | DMA_COMPL_SKIP_DEST_UNMAP; | |
398 | int ret = 0; | |
399 | ||
400 | tx = chan->device->device_prep_dma_memcpy(chan, dest, src, len, flags); | |
401 | if (!tx) { | |
402 | dev_err(acdev->host->dev, "device_prep_dma_memcpy failed\n"); | |
403 | return -EAGAIN; | |
404 | } | |
405 | ||
406 | tx->callback = dma_callback; | |
407 | tx->callback_param = acdev; | |
408 | cookie = tx->tx_submit(tx); | |
409 | ||
410 | ret = dma_submit_error(cookie); | |
411 | if (ret) { | |
412 | dev_err(acdev->host->dev, "dma_submit_error\n"); | |
413 | return ret; | |
414 | } | |
415 | ||
416 | chan->device->device_issue_pending(chan); | |
417 | ||
418 | /* Wait for DMA to complete */ | |
419 | if (!wait_for_completion_timeout(&acdev->dma_completion, TIMEOUT)) { | |
420 | chan->device->device_control(chan, DMA_TERMINATE_ALL, 0); | |
421 | dev_err(acdev->host->dev, "wait_for_completion_timeout\n"); | |
422 | return -ETIMEDOUT; | |
423 | } | |
424 | ||
425 | return ret; | |
426 | } | |
427 | ||
428 | static int sg_xfer(struct arasan_cf_dev *acdev, struct scatterlist *sg) | |
429 | { | |
430 | dma_addr_t dest = 0, src = 0; | |
431 | u32 xfer_cnt, sglen, dma_len, xfer_ctr; | |
432 | u32 write = acdev->qc->tf.flags & ATA_TFLAG_WRITE; | |
433 | unsigned long flags; | |
434 | int ret = 0; | |
435 | ||
436 | sglen = sg_dma_len(sg); | |
437 | if (write) { | |
438 | src = sg_dma_address(sg); | |
439 | dest = acdev->pbase + EXT_WRITE_PORT; | |
440 | } else { | |
441 | dest = sg_dma_address(sg); | |
442 | src = acdev->pbase + EXT_READ_PORT; | |
443 | } | |
444 | ||
445 | /* | |
446 | * For each sg: | |
447 | * MAX_XFER_COUNT data will be transferred before we get transfer | |
25985edc | 448 | * complete interrupt. Between after FIFO_SIZE data |
a480167b VK |
449 | * buffer available interrupt will be generated. At this time we will |
450 | * fill FIFO again: max FIFO_SIZE data. | |
451 | */ | |
452 | while (sglen) { | |
453 | xfer_cnt = min(sglen, MAX_XFER_COUNT); | |
454 | spin_lock_irqsave(&acdev->host->lock, flags); | |
455 | xfer_ctr = readl(acdev->vbase + XFER_CTR) & | |
456 | ~XFER_COUNT_MASK; | |
457 | writel(xfer_ctr | xfer_cnt | XFER_START, | |
458 | acdev->vbase + XFER_CTR); | |
459 | spin_unlock_irqrestore(&acdev->host->lock, flags); | |
460 | ||
25985edc | 461 | /* continue dma xfers until current sg is completed */ |
a480167b VK |
462 | while (xfer_cnt) { |
463 | /* wait for read to complete */ | |
464 | if (!write) { | |
465 | ret = wait4buf(acdev); | |
466 | if (ret) | |
467 | goto fail; | |
468 | } | |
469 | ||
470 | /* read/write FIFO in chunk of FIFO_SIZE */ | |
471 | dma_len = min(xfer_cnt, FIFO_SIZE); | |
472 | ret = dma_xfer(acdev, src, dest, dma_len); | |
473 | if (ret) { | |
474 | dev_err(acdev->host->dev, "dma failed"); | |
475 | goto fail; | |
476 | } | |
477 | ||
478 | if (write) | |
479 | src += dma_len; | |
480 | else | |
481 | dest += dma_len; | |
482 | ||
483 | sglen -= dma_len; | |
484 | xfer_cnt -= dma_len; | |
485 | ||
486 | /* wait for write to complete */ | |
487 | if (write) { | |
488 | ret = wait4buf(acdev); | |
489 | if (ret) | |
490 | goto fail; | |
491 | } | |
492 | } | |
493 | } | |
494 | ||
495 | fail: | |
496 | spin_lock_irqsave(&acdev->host->lock, flags); | |
497 | writel(readl(acdev->vbase + XFER_CTR) & ~XFER_START, | |
498 | acdev->vbase + XFER_CTR); | |
499 | spin_unlock_irqrestore(&acdev->host->lock, flags); | |
500 | ||
501 | return ret; | |
502 | } | |
503 | ||
504 | /* | |
505 | * This routine uses External DMA controller to read/write data to FIFO of CF | |
506 | * controller. There are two xfer related interrupt supported by CF controller: | |
507 | * - buf_avail: This interrupt is generated as soon as we have buffer of 512 | |
508 | * bytes available for reading or empty buffer available for writing. | |
509 | * - xfer_done: This interrupt is generated on transfer of "xfer_size" amount of | |
510 | * data to/from FIFO. xfer_size is programmed in XFER_CTR register. | |
511 | * | |
512 | * Max buffer size = FIFO_SIZE = 512 Bytes. | |
513 | * Max xfer_size = MAX_XFER_COUNT = 256 KB. | |
514 | */ | |
515 | static void data_xfer(struct work_struct *work) | |
516 | { | |
517 | struct arasan_cf_dev *acdev = container_of(work, struct arasan_cf_dev, | |
518 | work); | |
519 | struct ata_queued_cmd *qc = acdev->qc; | |
520 | struct scatterlist *sg; | |
521 | unsigned long flags; | |
522 | u32 temp; | |
523 | int ret = 0; | |
524 | ||
525 | /* request dma channels */ | |
526 | /* dma_request_channel may sleep, so calling from process context */ | |
60a230e4 VK |
527 | acdev->dma_chan = dma_request_channel(acdev->mask, filter, |
528 | acdev->dma_priv); | |
a480167b VK |
529 | if (!acdev->dma_chan) { |
530 | dev_err(acdev->host->dev, "Unable to get dma_chan\n"); | |
531 | goto chan_request_fail; | |
532 | } | |
533 | ||
534 | for_each_sg(qc->sg, sg, qc->n_elem, temp) { | |
535 | ret = sg_xfer(acdev, sg); | |
536 | if (ret) | |
537 | break; | |
538 | } | |
539 | ||
540 | dma_release_channel(acdev->dma_chan); | |
541 | ||
542 | /* data xferred successfully */ | |
543 | if (!ret) { | |
544 | u32 status; | |
545 | ||
546 | spin_lock_irqsave(&acdev->host->lock, flags); | |
547 | status = ioread8(qc->ap->ioaddr.altstatus_addr); | |
548 | spin_unlock_irqrestore(&acdev->host->lock, flags); | |
549 | if (status & (ATA_BUSY | ATA_DRQ)) { | |
550 | ata_sff_queue_delayed_work(&acdev->dwork, 1); | |
551 | return; | |
552 | } | |
553 | ||
554 | goto sff_intr; | |
555 | } | |
556 | ||
557 | cf_dumpregs(acdev); | |
558 | ||
559 | chan_request_fail: | |
560 | spin_lock_irqsave(&acdev->host->lock, flags); | |
25985edc | 561 | /* error when transferring data to/from memory */ |
a480167b VK |
562 | qc->err_mask |= AC_ERR_HOST_BUS; |
563 | qc->ap->hsm_task_state = HSM_ST_ERR; | |
564 | ||
565 | cf_ctrl_reset(acdev); | |
566 | spin_unlock_irqrestore(qc->ap->lock, flags); | |
567 | sff_intr: | |
568 | dma_complete(acdev); | |
569 | } | |
570 | ||
571 | static void delayed_finish(struct work_struct *work) | |
572 | { | |
573 | struct arasan_cf_dev *acdev = container_of(work, struct arasan_cf_dev, | |
574 | dwork.work); | |
575 | struct ata_queued_cmd *qc = acdev->qc; | |
576 | unsigned long flags; | |
577 | u8 status; | |
578 | ||
579 | spin_lock_irqsave(&acdev->host->lock, flags); | |
580 | status = ioread8(qc->ap->ioaddr.altstatus_addr); | |
581 | spin_unlock_irqrestore(&acdev->host->lock, flags); | |
582 | ||
583 | if (status & (ATA_BUSY | ATA_DRQ)) | |
584 | ata_sff_queue_delayed_work(&acdev->dwork, 1); | |
585 | else | |
586 | dma_complete(acdev); | |
587 | } | |
588 | ||
589 | static irqreturn_t arasan_cf_interrupt(int irq, void *dev) | |
590 | { | |
591 | struct arasan_cf_dev *acdev = ((struct ata_host *)dev)->private_data; | |
592 | unsigned long flags; | |
593 | u32 irqsts; | |
594 | ||
595 | irqsts = readl(acdev->vbase + GIRQ_STS); | |
596 | if (!(irqsts & GIRQ_CF)) | |
597 | return IRQ_NONE; | |
598 | ||
599 | spin_lock_irqsave(&acdev->host->lock, flags); | |
600 | irqsts = readl(acdev->vbase + IRQ_STS); | |
601 | writel(irqsts, acdev->vbase + IRQ_STS); /* clear irqs */ | |
602 | writel(GIRQ_CF, acdev->vbase + GIRQ_STS); /* clear girqs */ | |
603 | ||
604 | /* handle only relevant interrupts */ | |
605 | irqsts &= ~IGNORED_IRQS; | |
606 | ||
607 | if (irqsts & CARD_DETECT_IRQ) { | |
608 | cf_card_detect(acdev, 1); | |
609 | spin_unlock_irqrestore(&acdev->host->lock, flags); | |
610 | return IRQ_HANDLED; | |
611 | } | |
612 | ||
613 | if (irqsts & PIO_XFER_ERR_IRQ) { | |
614 | acdev->dma_status = ATA_DMA_ERR; | |
615 | writel(readl(acdev->vbase + XFER_CTR) & ~XFER_START, | |
616 | acdev->vbase + XFER_CTR); | |
617 | spin_unlock_irqrestore(&acdev->host->lock, flags); | |
618 | complete(&acdev->cf_completion); | |
619 | dev_err(acdev->host->dev, "pio xfer err irq\n"); | |
620 | return IRQ_HANDLED; | |
621 | } | |
622 | ||
623 | spin_unlock_irqrestore(&acdev->host->lock, flags); | |
624 | ||
625 | if (irqsts & BUF_AVAIL_IRQ) { | |
626 | complete(&acdev->cf_completion); | |
627 | return IRQ_HANDLED; | |
628 | } | |
629 | ||
630 | if (irqsts & XFER_DONE_IRQ) { | |
631 | struct ata_queued_cmd *qc = acdev->qc; | |
632 | ||
633 | /* Send Complete only for write */ | |
634 | if (qc->tf.flags & ATA_TFLAG_WRITE) | |
635 | complete(&acdev->cf_completion); | |
636 | } | |
637 | ||
638 | return IRQ_HANDLED; | |
639 | } | |
640 | ||
641 | static void arasan_cf_freeze(struct ata_port *ap) | |
642 | { | |
643 | struct arasan_cf_dev *acdev = ap->host->private_data; | |
644 | ||
645 | /* stop transfer and reset controller */ | |
646 | writel(readl(acdev->vbase + XFER_CTR) & ~XFER_START, | |
647 | acdev->vbase + XFER_CTR); | |
648 | cf_ctrl_reset(acdev); | |
649 | acdev->dma_status = ATA_DMA_ERR; | |
650 | ||
651 | ata_sff_dma_pause(ap); | |
652 | ata_sff_freeze(ap); | |
653 | } | |
654 | ||
655 | void arasan_cf_error_handler(struct ata_port *ap) | |
656 | { | |
657 | struct arasan_cf_dev *acdev = ap->host->private_data; | |
658 | ||
659 | /* | |
660 | * DMA transfers using an external DMA controller may be scheduled. | |
661 | * Abort them before handling error. Refer data_xfer() for further | |
662 | * details. | |
663 | */ | |
664 | cancel_work_sync(&acdev->work); | |
665 | cancel_delayed_work_sync(&acdev->dwork); | |
666 | return ata_sff_error_handler(ap); | |
667 | } | |
668 | ||
669 | static void arasan_cf_dma_start(struct arasan_cf_dev *acdev) | |
670 | { | |
671 | u32 xfer_ctr = readl(acdev->vbase + XFER_CTR) & ~XFER_DIR_MASK; | |
672 | u32 write = acdev->qc->tf.flags & ATA_TFLAG_WRITE; | |
673 | ||
674 | xfer_ctr |= write ? XFER_WRITE : XFER_READ; | |
675 | writel(xfer_ctr, acdev->vbase + XFER_CTR); | |
676 | ||
677 | acdev->qc->ap->ops->sff_exec_command(acdev->qc->ap, &acdev->qc->tf); | |
678 | ata_sff_queue_work(&acdev->work); | |
679 | } | |
680 | ||
681 | unsigned int arasan_cf_qc_issue(struct ata_queued_cmd *qc) | |
682 | { | |
683 | struct ata_port *ap = qc->ap; | |
684 | struct arasan_cf_dev *acdev = ap->host->private_data; | |
685 | ||
686 | /* defer PIO handling to sff_qc_issue */ | |
687 | if (!ata_is_dma(qc->tf.protocol)) | |
688 | return ata_sff_qc_issue(qc); | |
689 | ||
690 | /* select the device */ | |
691 | ata_wait_idle(ap); | |
692 | ata_sff_dev_select(ap, qc->dev->devno); | |
693 | ata_wait_idle(ap); | |
694 | ||
695 | /* start the command */ | |
696 | switch (qc->tf.protocol) { | |
697 | case ATA_PROT_DMA: | |
698 | WARN_ON_ONCE(qc->tf.flags & ATA_TFLAG_POLLING); | |
699 | ||
700 | ap->ops->sff_tf_load(ap, &qc->tf); | |
701 | acdev->dma_status = 0; | |
702 | acdev->qc = qc; | |
703 | arasan_cf_dma_start(acdev); | |
704 | ap->hsm_task_state = HSM_ST_LAST; | |
705 | break; | |
706 | ||
707 | default: | |
708 | WARN_ON(1); | |
709 | return AC_ERR_SYSTEM; | |
710 | } | |
711 | ||
712 | return 0; | |
713 | } | |
714 | ||
715 | static void arasan_cf_set_piomode(struct ata_port *ap, struct ata_device *adev) | |
716 | { | |
717 | struct arasan_cf_dev *acdev = ap->host->private_data; | |
718 | u8 pio = adev->pio_mode - XFER_PIO_0; | |
719 | unsigned long flags; | |
720 | u32 val; | |
721 | ||
722 | /* Arasan ctrl supports Mode0 -> Mode6 */ | |
723 | if (pio > 6) { | |
724 | dev_err(ap->dev, "Unknown PIO mode\n"); | |
725 | return; | |
726 | } | |
727 | ||
728 | spin_lock_irqsave(&acdev->host->lock, flags); | |
729 | val = readl(acdev->vbase + OP_MODE) & | |
730 | ~(ULTRA_DMA_ENB | MULTI_WORD_DMA_ENB | DRQ_BLOCK_SIZE_MASK); | |
731 | writel(val, acdev->vbase + OP_MODE); | |
732 | val = readl(acdev->vbase + TM_CFG) & ~TRUEIDE_PIO_TIMING_MASK; | |
733 | val |= pio << TRUEIDE_PIO_TIMING_SHIFT; | |
734 | writel(val, acdev->vbase + TM_CFG); | |
735 | ||
736 | cf_interrupt_enable(acdev, BUF_AVAIL_IRQ | XFER_DONE_IRQ, 0); | |
737 | cf_interrupt_enable(acdev, PIO_XFER_ERR_IRQ, 1); | |
738 | spin_unlock_irqrestore(&acdev->host->lock, flags); | |
739 | } | |
740 | ||
741 | static void arasan_cf_set_dmamode(struct ata_port *ap, struct ata_device *adev) | |
742 | { | |
743 | struct arasan_cf_dev *acdev = ap->host->private_data; | |
744 | u32 opmode, tmcfg, dma_mode = adev->dma_mode; | |
745 | unsigned long flags; | |
746 | ||
747 | spin_lock_irqsave(&acdev->host->lock, flags); | |
748 | opmode = readl(acdev->vbase + OP_MODE) & | |
749 | ~(MULTI_WORD_DMA_ENB | ULTRA_DMA_ENB); | |
750 | tmcfg = readl(acdev->vbase + TM_CFG); | |
751 | ||
752 | if ((dma_mode >= XFER_UDMA_0) && (dma_mode <= XFER_UDMA_6)) { | |
753 | opmode |= ULTRA_DMA_ENB; | |
754 | tmcfg &= ~ULTRA_DMA_TIMING_MASK; | |
755 | tmcfg |= (dma_mode - XFER_UDMA_0) << ULTRA_DMA_TIMING_SHIFT; | |
756 | } else if ((dma_mode >= XFER_MW_DMA_0) && (dma_mode <= XFER_MW_DMA_4)) { | |
757 | opmode |= MULTI_WORD_DMA_ENB; | |
758 | tmcfg &= ~TRUEIDE_MWORD_DMA_TIMING_MASK; | |
759 | tmcfg |= (dma_mode - XFER_MW_DMA_0) << | |
760 | TRUEIDE_MWORD_DMA_TIMING_SHIFT; | |
761 | } else { | |
762 | dev_err(ap->dev, "Unknown DMA mode\n"); | |
763 | spin_unlock_irqrestore(&acdev->host->lock, flags); | |
764 | return; | |
765 | } | |
766 | ||
767 | writel(opmode, acdev->vbase + OP_MODE); | |
768 | writel(tmcfg, acdev->vbase + TM_CFG); | |
769 | writel(DMA_XFER_MODE, acdev->vbase + XFER_CTR); | |
770 | ||
771 | cf_interrupt_enable(acdev, PIO_XFER_ERR_IRQ, 0); | |
772 | cf_interrupt_enable(acdev, BUF_AVAIL_IRQ | XFER_DONE_IRQ, 1); | |
773 | spin_unlock_irqrestore(&acdev->host->lock, flags); | |
774 | } | |
775 | ||
776 | static struct ata_port_operations arasan_cf_ops = { | |
777 | .inherits = &ata_sff_port_ops, | |
778 | .freeze = arasan_cf_freeze, | |
779 | .error_handler = arasan_cf_error_handler, | |
780 | .qc_issue = arasan_cf_qc_issue, | |
781 | .set_piomode = arasan_cf_set_piomode, | |
782 | .set_dmamode = arasan_cf_set_dmamode, | |
783 | }; | |
784 | ||
785 | static int __devinit arasan_cf_probe(struct platform_device *pdev) | |
786 | { | |
787 | struct arasan_cf_dev *acdev; | |
788 | struct arasan_cf_pdata *pdata = dev_get_platdata(&pdev->dev); | |
789 | struct ata_host *host; | |
790 | struct ata_port *ap; | |
791 | struct resource *res; | |
792 | irq_handler_t irq_handler = NULL; | |
793 | int ret = 0; | |
794 | ||
795 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
796 | if (!res) | |
797 | return -EINVAL; | |
798 | ||
799 | if (!devm_request_mem_region(&pdev->dev, res->start, resource_size(res), | |
800 | DRIVER_NAME)) { | |
801 | dev_warn(&pdev->dev, "Failed to get memory region resource\n"); | |
802 | return -ENOENT; | |
803 | } | |
804 | ||
805 | acdev = devm_kzalloc(&pdev->dev, sizeof(*acdev), GFP_KERNEL); | |
806 | if (!acdev) { | |
807 | dev_warn(&pdev->dev, "kzalloc fail\n"); | |
808 | return -ENOMEM; | |
809 | } | |
810 | ||
811 | /* if irq is 0, support only PIO */ | |
812 | acdev->irq = platform_get_irq(pdev, 0); | |
813 | if (acdev->irq) | |
814 | irq_handler = arasan_cf_interrupt; | |
815 | else | |
816 | pdata->quirk |= CF_BROKEN_MWDMA | CF_BROKEN_UDMA; | |
817 | ||
818 | acdev->pbase = res->start; | |
819 | acdev->vbase = devm_ioremap_nocache(&pdev->dev, res->start, | |
820 | resource_size(res)); | |
821 | if (!acdev->vbase) { | |
822 | dev_warn(&pdev->dev, "ioremap fail\n"); | |
823 | return -ENOMEM; | |
824 | } | |
825 | ||
a480167b VK |
826 | acdev->clk = clk_get(&pdev->dev, NULL); |
827 | if (IS_ERR(acdev->clk)) { | |
828 | dev_warn(&pdev->dev, "Clock not found\n"); | |
829 | return PTR_ERR(acdev->clk); | |
830 | } | |
a480167b VK |
831 | |
832 | /* allocate host */ | |
833 | host = ata_host_alloc(&pdev->dev, 1); | |
834 | if (!host) { | |
835 | ret = -ENOMEM; | |
836 | dev_warn(&pdev->dev, "alloc host fail\n"); | |
837 | goto free_clk; | |
838 | } | |
839 | ||
840 | ap = host->ports[0]; | |
841 | host->private_data = acdev; | |
842 | acdev->host = host; | |
843 | ap->ops = &arasan_cf_ops; | |
844 | ap->pio_mask = ATA_PIO6; | |
845 | ap->mwdma_mask = ATA_MWDMA4; | |
846 | ap->udma_mask = ATA_UDMA6; | |
847 | ||
848 | init_completion(&acdev->cf_completion); | |
849 | init_completion(&acdev->dma_completion); | |
850 | INIT_WORK(&acdev->work, data_xfer); | |
851 | INIT_DELAYED_WORK(&acdev->dwork, delayed_finish); | |
852 | dma_cap_set(DMA_MEMCPY, acdev->mask); | |
60a230e4 | 853 | acdev->dma_priv = pdata->dma_priv; |
a480167b VK |
854 | |
855 | /* Handle platform specific quirks */ | |
856 | if (pdata->quirk) { | |
857 | if (pdata->quirk & CF_BROKEN_PIO) { | |
858 | ap->ops->set_piomode = NULL; | |
859 | ap->pio_mask = 0; | |
860 | } | |
861 | if (pdata->quirk & CF_BROKEN_MWDMA) | |
862 | ap->mwdma_mask = 0; | |
863 | if (pdata->quirk & CF_BROKEN_UDMA) | |
864 | ap->udma_mask = 0; | |
865 | } | |
866 | ap->flags |= ATA_FLAG_PIO_POLLING | ATA_FLAG_NO_ATAPI; | |
867 | ||
868 | ap->ioaddr.cmd_addr = acdev->vbase + ATA_DATA_PORT; | |
869 | ap->ioaddr.data_addr = acdev->vbase + ATA_DATA_PORT; | |
870 | ap->ioaddr.error_addr = acdev->vbase + ATA_ERR_FTR; | |
871 | ap->ioaddr.feature_addr = acdev->vbase + ATA_ERR_FTR; | |
872 | ap->ioaddr.nsect_addr = acdev->vbase + ATA_SC; | |
873 | ap->ioaddr.lbal_addr = acdev->vbase + ATA_SN; | |
874 | ap->ioaddr.lbam_addr = acdev->vbase + ATA_CL; | |
875 | ap->ioaddr.lbah_addr = acdev->vbase + ATA_CH; | |
876 | ap->ioaddr.device_addr = acdev->vbase + ATA_SH; | |
877 | ap->ioaddr.status_addr = acdev->vbase + ATA_STS_CMD; | |
878 | ap->ioaddr.command_addr = acdev->vbase + ATA_STS_CMD; | |
879 | ap->ioaddr.altstatus_addr = acdev->vbase + ATA_ASTS_DCTR; | |
880 | ap->ioaddr.ctl_addr = acdev->vbase + ATA_ASTS_DCTR; | |
881 | ||
a17139b6 JG |
882 | ata_port_desc(ap, "phy_addr %llx virt_addr %p", |
883 | (unsigned long long) res->start, acdev->vbase); | |
a480167b VK |
884 | |
885 | ret = cf_init(acdev); | |
886 | if (ret) | |
887 | goto free_clk; | |
888 | ||
889 | cf_card_detect(acdev, 0); | |
890 | ||
891 | return ata_host_activate(host, acdev->irq, irq_handler, 0, | |
892 | &arasan_cf_sht); | |
893 | ||
894 | free_clk: | |
a480167b | 895 | clk_put(acdev->clk); |
a480167b VK |
896 | return ret; |
897 | } | |
898 | ||
899 | static int __devexit arasan_cf_remove(struct platform_device *pdev) | |
900 | { | |
901 | struct ata_host *host = dev_get_drvdata(&pdev->dev); | |
902 | struct arasan_cf_dev *acdev = host->ports[0]->private_data; | |
903 | ||
904 | ata_host_detach(host); | |
905 | cf_exit(acdev); | |
a480167b | 906 | clk_put(acdev->clk); |
a480167b VK |
907 | |
908 | return 0; | |
909 | } | |
910 | ||
911 | #ifdef CONFIG_PM | |
912 | static int arasan_cf_suspend(struct device *dev) | |
913 | { | |
90f0adf0 | 914 | struct ata_host *host = dev_get_drvdata(dev); |
a480167b VK |
915 | struct arasan_cf_dev *acdev = host->ports[0]->private_data; |
916 | ||
40679b3c | 917 | if (acdev->dma_chan) |
a480167b VK |
918 | acdev->dma_chan->device->device_control(acdev->dma_chan, |
919 | DMA_TERMINATE_ALL, 0); | |
40679b3c | 920 | |
a480167b VK |
921 | cf_exit(acdev); |
922 | return ata_host_suspend(host, PMSG_SUSPEND); | |
923 | } | |
924 | ||
925 | static int arasan_cf_resume(struct device *dev) | |
926 | { | |
90f0adf0 | 927 | struct ata_host *host = dev_get_drvdata(dev); |
a480167b VK |
928 | struct arasan_cf_dev *acdev = host->ports[0]->private_data; |
929 | ||
930 | cf_init(acdev); | |
931 | ata_host_resume(host); | |
932 | ||
933 | return 0; | |
934 | } | |
fb9751d4 | 935 | #endif |
a480167b | 936 | |
40679b3c | 937 | static SIMPLE_DEV_PM_OPS(arasan_cf_pm_ops, arasan_cf_suspend, arasan_cf_resume); |
a480167b | 938 | |
26fdaa74 VK |
939 | #ifdef CONFIG_OF |
940 | static const struct of_device_id arasan_cf_id_table[] = { | |
941 | { .compatible = "arasan,cf-spear1340" }, | |
942 | {} | |
943 | }; | |
944 | MODULE_DEVICE_TABLE(of, arasan_cf_id_table); | |
945 | #endif | |
946 | ||
a480167b VK |
947 | static struct platform_driver arasan_cf_driver = { |
948 | .probe = arasan_cf_probe, | |
949 | .remove = __devexit_p(arasan_cf_remove), | |
950 | .driver = { | |
951 | .name = DRIVER_NAME, | |
952 | .owner = THIS_MODULE, | |
40679b3c | 953 | .pm = &arasan_cf_pm_ops, |
26fdaa74 | 954 | .of_match_table = of_match_ptr(arasan_cf_id_table), |
a480167b VK |
955 | }, |
956 | }; | |
957 | ||
99c8ea3e | 958 | module_platform_driver(arasan_cf_driver); |
a480167b | 959 | |
10d8935f | 960 | MODULE_AUTHOR("Viresh Kumar <viresh.linux@gmail.com>"); |
a480167b VK |
961 | MODULE_DESCRIPTION("Arasan ATA Compact Flash driver"); |
962 | MODULE_LICENSE("GPL"); | |
963 | MODULE_ALIAS("platform:" DRIVER_NAME); |