[deliverable/linux.git] / drivers / ata / pata_artop.c

/*
 *    pata_artop.c - ARTOP ATA controller driver
 *
 *	(C) 2006 Red Hat <alan@redhat.com>
 *	(C) 2007 Bartlomiej Zolnierkiewicz
 *
 *    Based in part on drivers/ide/pci/aec62xx.c
 *	Copyright (C) 1999-2002	Andre Hedrick <andre@linux-ide.org>
 *	865/865R fixes for Macintosh card version from a patch to the old
 *		driver by Thibaut VARENE <varenet@parisc-linux.org>
 *	When setting the PCI latency we must set 0x80 or higher for burst
 *		performance Alessandro Zummo <alessandro.zummo@towertech.it>
 *
 *	TODO
 *	850 serialization once the core supports it
 *	Investigate no_dsc on 850R
 *	Clock detect
 */

#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/pci.h>
#include <linux/init.h>
#include <linux/blkdev.h>
#include <linux/delay.h>
#include <linux/device.h>
#include <scsi/scsi_host.h>
#include <linux/libata.h>
#include <linux/ata.h>

#define DRV_NAME	"pata_artop"
#define DRV_VERSION	"0.4.4"

/*
 *	The ARTOP has 33 Mhz and "over clocked" timing tables. Until we
 *	get PCI bus speed functionality we leave this as 0. Its a variable
 *	for when we get the functionality and also for folks wanting to
 *	test stuff.
 */

static int clock = 0;

static int artop6210_pre_reset(struct ata_port *ap, unsigned long deadline)
{
	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	const struct pci_bits artop_enable_bits[] = {
		{ 0x4AU, 1U, 0x02UL, 0x02UL },	/* port 0 */
		{ 0x4AU, 1U, 0x04UL, 0x04UL },	/* port 1 */
	};

	if (!pci_test_config_bits(pdev, &artop_enable_bits[ap->port_no]))
		return -ENOENT;

	return ata_std_prereset(ap, deadline);
}

/**
 *	artop6210_error_handler - Probe specified port on PATA host controller
 *	@ap: Port to probe
 *
 *	LOCKING:
 *	None (inherited from caller).
 */

static void artop6210_error_handler(struct ata_port *ap)
{
	ata_bmdma_drive_eh(ap, artop6210_pre_reset,
				    ata_std_softreset, NULL,
				    ata_std_postreset);
}

/**
 *	artop6260_pre_reset	-	check for 40/80 pin
 *	@ap: Port
 *	@deadline: deadline jiffies for the operation
 *
 *	The ARTOP hardware reports the cable detect bits in register 0x49.
 *	Nothing complicated needed here.
 */

static int artop6260_pre_reset(struct ata_port *ap, unsigned long deadline)
{
	static const struct pci_bits artop_enable_bits[] = {
		{ 0x4AU, 1U, 0x02UL, 0x02UL },	/* port 0 */
		{ 0x4AU, 1U, 0x04UL, 0x04UL },	/* port 1 */
	};

	struct pci_dev *pdev = to_pci_dev(ap->host->dev);

	/* Odd numbered device ids are the units with enable bits (the -R cards) */
	if (pdev->device % 1 && !pci_test_config_bits(pdev, &artop_enable_bits[ap->port_no]))
		return -ENOENT;

	return ata_std_prereset(ap, deadline);
}

/**
 *	artop6260_cable_detect	-	identify cable type
 *	@ap: Port
 *
 *	Identify the cable type for the ARTOP interface in question
 */

static int artop6260_cable_detect(struct ata_port *ap)
{
	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	u8 tmp;
	pci_read_config_byte(pdev, 0x49, &tmp);
	if (tmp & (1 << ap->port_no))
		return ATA_CBL_PATA40;
	return ATA_CBL_PATA80;
}

/**
 *	artop6260_error_handler - Probe specified port on PATA host controller
 *	@ap: Port to probe
 *
 *	LOCKING:
 *	None (inherited from caller).
 */

static void artop6260_error_handler(struct ata_port *ap)
{
	ata_bmdma_drive_eh(ap, artop6260_pre_reset,
				    ata_std_softreset, NULL,
				    ata_std_postreset);
}

/**
 *	artop6210_load_piomode - Load a set of PATA PIO timings
 *	@ap: Port whose timings we are configuring
 *	@adev: Device
 *	@pio: PIO mode
 *
 *	Set PIO mode for device, in host controller PCI config space. This
 *	is used both to set PIO timings in PIO mode and also to set the
 *	matching PIO clocking for UDMA, as well as the MWDMA timings.
 *
 *	LOCKING:
 *	None (inherited from caller).
 */

static void artop6210_load_piomode(struct ata_port *ap, struct ata_device *adev, unsigned int pio)
{
	struct pci_dev *pdev	= to_pci_dev(ap->host->dev);
	int dn = adev->devno + 2 * ap->port_no;
	const u16 timing[2][5] = {
		{ 0x0000, 0x000A, 0x0008, 0x0303, 0x0301 },
		{ 0x0700, 0x070A, 0x0708, 0x0403, 0x0401 }

	};
	/* Load the PIO timing active/recovery bits */
	pci_write_config_word(pdev, 0x40 + 2 * dn, timing[clock][pio]);
}

/**
 *	artop6210_set_piomode - Initialize host controller PATA PIO timings
 *	@ap: Port whose timings we are configuring
 *	@adev: Device we are configuring
 *
 *	Set PIO mode for device, in host controller PCI config space. For
 *	ARTOP we must also clear the UDMA bits if we are not doing UDMA. In
 *	the event UDMA is used the later call to set_dmamode will set the
 *	bits as required.
 *
 *	LOCKING:
 *	None (inherited from caller).
 */

static void artop6210_set_piomode(struct ata_port *ap, struct ata_device *adev)
{
	struct pci_dev *pdev	= to_pci_dev(ap->host->dev);
	int dn = adev->devno + 2 * ap->port_no;
	u8 ultra;

	artop6210_load_piomode(ap, adev, adev->pio_mode - XFER_PIO_0);

	/* Clear the UDMA mode bits (set_dmamode will redo this if needed) */
	pci_read_config_byte(pdev, 0x54, &ultra);
	ultra &= ~(3 << (2 * dn));
	pci_write_config_byte(pdev, 0x54, ultra);
}

/**
 *	artop6260_load_piomode - Initialize host controller PATA PIO timings
 *	@ap: Port whose timings we are configuring
 *	@adev: Device we are configuring
 *	@pio: PIO mode
 *
 *	Set PIO mode for device, in host controller PCI config space. The
 *	ARTOP6260 and relatives store the timing data differently.
 *
 *	LOCKING:
 *	None (inherited from caller).
 */

static void artop6260_load_piomode (struct ata_port *ap, struct ata_device *adev, unsigned int pio)
{
	struct pci_dev *pdev	= to_pci_dev(ap->host->dev);
	int dn = adev->devno + 2 * ap->port_no;
	const u8 timing[2][5] = {
		{ 0x00, 0x0A, 0x08, 0x33, 0x31 },
		{ 0x70, 0x7A, 0x78, 0x43, 0x41 }

	};
	/* Load the PIO timing active/recovery bits */
	pci_write_config_byte(pdev, 0x40 + dn, timing[clock][pio]);
}

/**
 *	artop6260_set_piomode - Initialize host controller PATA PIO timings
 *	@ap: Port whose timings we are configuring
 *	@adev: Device we are configuring
 *
 *	Set PIO mode for device, in host controller PCI config space. For
 *	ARTOP we must also clear the UDMA bits if we are not doing UDMA. In
 *	the event UDMA is used the later call to set_dmamode will set the
 *	bits as required.
 *
 *	LOCKING:
 *	None (inherited from caller).
 */

static void artop6260_set_piomode(struct ata_port *ap, struct ata_device *adev)
{
	struct pci_dev *pdev	= to_pci_dev(ap->host->dev);
	u8 ultra;

	artop6260_load_piomode(ap, adev, adev->pio_mode - XFER_PIO_0);

	/* Clear the UDMA mode bits (set_dmamode will redo this if needed) */
	pci_read_config_byte(pdev, 0x44 + ap->port_no, &ultra);
	ultra &= ~(7 << (4  * adev->devno));	/* One nibble per drive */
	pci_write_config_byte(pdev, 0x44 + ap->port_no, ultra);
}

/**
 *	artop6210_set_dmamode - Initialize host controller PATA PIO timings
 *	@ap: Port whose timings we are configuring
 *	@adev: Device whose timings we are configuring
 *
 *	Set DMA mode for device, in host controller PCI config space.
 *
 *	LOCKING:
 *	None (inherited from caller).
 */

static void artop6210_set_dmamode (struct ata_port *ap, struct ata_device *adev)
{
	unsigned int pio;
	struct pci_dev *pdev	= to_pci_dev(ap->host->dev);
	int dn = adev->devno + 2 * ap->port_no;
	u8 ultra;

	if (adev->dma_mode == XFER_MW_DMA_0)
		pio = 1;
	else
		pio = 4;

	/* Load the PIO timing active/recovery bits */
	artop6210_load_piomode(ap, adev, pio);

	pci_read_config_byte(pdev, 0x54, &ultra);
	ultra &= ~(3 << (2 * dn));

	/* Add ultra DMA bits if in UDMA mode */
	if (adev->dma_mode >= XFER_UDMA_0) {
		u8 mode = (adev->dma_mode - XFER_UDMA_0) + 1 - clock;
		if (mode == 0)
			mode = 1;
		ultra |= (mode << (2 * dn));
	}
	pci_write_config_byte(pdev, 0x54, ultra);
}

/**
 *	artop6260_set_dmamode - Initialize host controller PATA PIO timings
 *	@ap: Port whose timings we are configuring
 *	@adev: Device we are configuring
 *
 *	Set DMA mode for device, in host controller PCI config space. The
 *	ARTOP6260 and relatives store the timing data differently.
 *
 *	LOCKING:
 *	None (inherited from caller).
 */

static void artop6260_set_dmamode (struct ata_port *ap, struct ata_device *adev)
{
	unsigned int pio	= adev->pio_mode - XFER_PIO_0;
	struct pci_dev *pdev	= to_pci_dev(ap->host->dev);
	u8 ultra;

	if (adev->dma_mode == XFER_MW_DMA_0)
		pio = 1;
	else
		pio = 4;

	/* Load the PIO timing active/recovery bits */
	artop6260_load_piomode(ap, adev, pio);

	/* Add ultra DMA bits if in UDMA mode */
	pci_read_config_byte(pdev, 0x44 + ap->port_no, &ultra);
	ultra &= ~(7 << (4  * adev->devno));	/* One nibble per drive */
	if (adev->dma_mode >= XFER_UDMA_0) {
		u8 mode = adev->dma_mode - XFER_UDMA_0 + 1 - clock;
		if (mode == 0)
			mode = 1;
		ultra |= (mode << (4 * adev->devno));
	}
	pci_write_config_byte(pdev, 0x44 + ap->port_no, ultra);
}

static struct scsi_host_template artop_sht = {
	.module			= THIS_MODULE,
	.name			= DRV_NAME,
	.ioctl			= ata_scsi_ioctl,
	.queuecommand		= ata_scsi_queuecmd,
	.can_queue		= ATA_DEF_QUEUE,
	.this_id		= ATA_SHT_THIS_ID,
	.sg_tablesize		= LIBATA_MAX_PRD,
	.cmd_per_lun		= ATA_SHT_CMD_PER_LUN,
	.emulated		= ATA_SHT_EMULATED,
	.use_clustering		= ATA_SHT_USE_CLUSTERING,
	.proc_name		= DRV_NAME,
	.dma_boundary		= ATA_DMA_BOUNDARY,
	.slave_configure	= ata_scsi_slave_config,
	.slave_destroy		= ata_scsi_slave_destroy,
	.bios_param		= ata_std_bios_param,
};

static const struct ata_port_operations artop6210_ops = {
	.port_disable		= ata_port_disable,
	.set_piomode		= artop6210_set_piomode,
	.set_dmamode		= artop6210_set_dmamode,
	.mode_filter		= ata_pci_default_filter,

	.tf_load		= ata_tf_load,
	.tf_read		= ata_tf_read,
	.check_status		= ata_check_status,
	.exec_command		= ata_exec_command,
	.dev_select		= ata_std_dev_select,

	.freeze			= ata_bmdma_freeze,
	.thaw			= ata_bmdma_thaw,
	.error_handler		= artop6210_error_handler,
	.post_internal_cmd 	= ata_bmdma_post_internal_cmd,
	.cable_detect		= ata_cable_40wire,

	.bmdma_setup		= ata_bmdma_setup,
	.bmdma_start		= ata_bmdma_start,
	.bmdma_stop		= ata_bmdma_stop,
	.bmdma_status		= ata_bmdma_status,
	.qc_prep		= ata_qc_prep,
	.qc_issue		= ata_qc_issue_prot,

	.data_xfer		= ata_data_xfer,

	.irq_handler		= ata_interrupt,
	.irq_clear		= ata_bmdma_irq_clear,
	.irq_on			= ata_irq_on,
	.irq_ack		= ata_irq_ack,

	.port_start		= ata_port_start,
};

static const struct ata_port_operations artop6260_ops = {
	.port_disable		= ata_port_disable,
	.set_piomode		= artop6260_set_piomode,
	.set_dmamode		= artop6260_set_dmamode,

	.tf_load		= ata_tf_load,
	.tf_read		= ata_tf_read,
	.check_status		= ata_check_status,
	.exec_command		= ata_exec_command,
	.dev_select		= ata_std_dev_select,

	.freeze			= ata_bmdma_freeze,
	.thaw			= ata_bmdma_thaw,
	.error_handler		= artop6260_error_handler,
	.post_internal_cmd 	= ata_bmdma_post_internal_cmd,
	.cable_detect		= artop6260_cable_detect,

	.bmdma_setup		= ata_bmdma_setup,
	.bmdma_start		= ata_bmdma_start,
	.bmdma_stop		= ata_bmdma_stop,
	.bmdma_status		= ata_bmdma_status,
	.qc_prep		= ata_qc_prep,
	.qc_issue		= ata_qc_issue_prot,
	.data_xfer		= ata_data_xfer,

	.irq_handler		= ata_interrupt,
	.irq_clear		= ata_bmdma_irq_clear,
	.irq_on			= ata_irq_on,
	.irq_ack		= ata_irq_ack,

	.port_start		= ata_port_start,
};


/**
 *	artop_init_one - Register ARTOP ATA PCI device with kernel services
 *	@pdev: PCI device to register
 *	@ent: Entry in artop_pci_tbl matching with @pdev
 *
 *	Called from kernel PCI layer.
 *
 *	LOCKING:
 *	Inherited from PCI layer (may sleep).
 *
 *	RETURNS:
 *	Zero on success, or -ERRNO value.
 */

static int artop_init_one (struct pci_dev *pdev, const struct pci_device_id *id)
{
	static int printed_version;
	static const struct ata_port_info info_6210 = {
		.sht		= &artop_sht,
		.flags		= ATA_FLAG_SLAVE_POSS,
		.pio_mask	= 0x1f,	/* pio0-4 */
		.mwdma_mask	= 0x07, /* mwdma0-2 */
		.udma_mask 	= ATA_UDMA2,
		.port_ops	= &artop6210_ops,
	};
	static const struct ata_port_info info_626x = {
		.sht		= &artop_sht,
		.flags		= ATA_FLAG_SLAVE_POSS,
		.pio_mask	= 0x1f,	/* pio0-4 */
		.mwdma_mask	= 0x07, /* mwdma0-2 */
		.udma_mask 	= ATA_UDMA4,
		.port_ops	= &artop6260_ops,
	};
	static const struct ata_port_info info_628x = {
		.sht		= &artop_sht,
		.flags		= ATA_FLAG_SLAVE_POSS,
		.pio_mask	= 0x1f,	/* pio0-4 */
		.mwdma_mask	= 0x07, /* mwdma0-2 */
		.udma_mask 	= ATA_UDMA5,
		.port_ops	= &artop6260_ops,
	};
	static const struct ata_port_info info_628x_fast = {
		.sht		= &artop_sht,
		.flags		= ATA_FLAG_SLAVE_POSS,
		.pio_mask	= 0x1f,	/* pio0-4 */
		.mwdma_mask	= 0x07, /* mwdma0-2 */
		.udma_mask 	= ATA_UDMA6,
		.port_ops	= &artop6260_ops,
	};
	const struct ata_port_info *ppi[] = { NULL, NULL };

	if (!printed_version++)
		dev_printk(KERN_DEBUG, &pdev->dev,
			   "version " DRV_VERSION "\n");

	if (id->driver_data == 0) {	/* 6210 variant */
		ppi[0] = &info_6210;
		ppi[1] = &ata_dummy_port_info;
		/* BIOS may have left us in UDMA, clear it before libata probe */
		pci_write_config_byte(pdev, 0x54, 0);
		/* For the moment (also lacks dsc) */
		printk(KERN_WARNING "ARTOP 6210 requires serialize functionality not yet supported by libata.\n");
		printk(KERN_WARNING "Secondary ATA ports will not be activated.\n");
	}
	else if (id->driver_data == 1)	/* 6260 */
		ppi[0] = &info_626x;
	else if (id->driver_data == 2)	{ /* 6280 or 6280 + fast */
		unsigned long io = pci_resource_start(pdev, 4);
		u8 reg;

		ppi[0] = &info_628x;
		if (inb(io) & 0x10)
			ppi[0] = &info_628x_fast;
		/* Mac systems come up with some registers not set as we
		   will need them */

		/* Clear reset & test bits */
		pci_read_config_byte(pdev, 0x49, &reg);
		pci_write_config_byte(pdev, 0x49, reg & ~ 0x30);

		/* PCI latency must be > 0x80 for burst mode, tweak it
		 * if required.
		 */
		pci_read_config_byte(pdev, PCI_LATENCY_TIMER, &reg);
		if (reg <= 0x80)
			pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0x90);

		/* Enable IRQ output and burst mode */
		pci_read_config_byte(pdev, 0x4a, &reg);
		pci_write_config_byte(pdev, 0x4a, (reg & ~0x01) | 0x80);

	}

	BUG_ON(ppi[0] == NULL);

	return ata_pci_init_one(pdev, ppi);
}

static const struct pci_device_id artop_pci_tbl[] = {
	{ PCI_VDEVICE(ARTOP, 0x0005), 0 },
	{ PCI_VDEVICE(ARTOP, 0x0006), 1 },
	{ PCI_VDEVICE(ARTOP, 0x0007), 1 },
	{ PCI_VDEVICE(ARTOP, 0x0008), 2 },
	{ PCI_VDEVICE(ARTOP, 0x0009), 2 },

	{ }	/* terminate list */
};

static struct pci_driver artop_pci_driver = {
	.name			= DRV_NAME,
	.id_table		= artop_pci_tbl,
	.probe			= artop_init_one,
	.remove			= ata_pci_remove_one,
};

static int __init artop_init(void)
{
	return pci_register_driver(&artop_pci_driver);
}

static void __exit artop_exit(void)
{
	pci_unregister_driver(&artop_pci_driver);
}

module_init(artop_init);
module_exit(artop_exit);

MODULE_AUTHOR("Alan Cox");
MODULE_DESCRIPTION("SCSI low-level driver for ARTOP PATA");
MODULE_LICENSE("GPL");
MODULE_DEVICE_TABLE(pci, artop_pci_tbl);
MODULE_VERSION(DRV_VERSION);
Commit	Line	Data
669a5db4 JG	1	/*
	2	* pata_artop.c - ARTOP ATA controller driver
	3	*
	4	* (C) 2006 Red Hat <alan@redhat.com>
be456b77	5	* (C) 2007 Bartlomiej Zolnierkiewicz
669a5db4 JG	6	*
	7	* Based in part on drivers/ide/pci/aec62xx.c
	8	* Copyright (C) 1999-2002 Andre Hedrick <andre@linux-ide.org>
	9	* 865/865R fixes for Macintosh card version from a patch to the old
	10	* driver by Thibaut VARENE <varenet@parisc-linux.org>
	11	* When setting the PCI latency we must set 0x80 or higher for burst
	12	* performance Alessandro Zummo <alessandro.zummo@towertech.it>
	13	*
	14	* TODO
	15	* 850 serialization once the core supports it
	16	* Investigate no_dsc on 850R
	17	* Clock detect
	18	*/
	19
	20	#include <linux/kernel.h>
	21	#include <linux/module.h>
	22	#include <linux/pci.h>
	23	#include <linux/init.h>
	24	#include <linux/blkdev.h>
	25	#include <linux/delay.h>
	26	#include <linux/device.h>
	27	#include <scsi/scsi_host.h>
	28	#include <linux/libata.h>
	29	#include <linux/ata.h>
	30
	31	#define DRV_NAME "pata_artop"
be456b77	32	#define DRV_VERSION "0.4.4"
669a5db4 JG	33
	34	/*
	35	* The ARTOP has 33 Mhz and "over clocked" timing tables. Until we
	36	* get PCI bus speed functionality we leave this as 0. Its a variable
	37	* for when we get the functionality and also for folks wanting to
	38	* test stuff.
	39	*/
	40
	41	static int clock = 0;
	42
d4b2bab4	43	static int artop6210_pre_reset(struct ata_port *ap, unsigned long deadline)
669a5db4 JG	44	{
	45	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	46	const struct pci_bits artop_enable_bits[] = {
	47	{ 0x4AU, 1U, 0x02UL, 0x02UL }, /* port 0 */
	48	{ 0x4AU, 1U, 0x04UL, 0x04UL }, /* port 1 */
	49	};
	50
c961922b AC	51	if (!pci_test_config_bits(pdev, &artop_enable_bits[ap->port_no]))
c961922b AC	52	return -ENOENT;
d4b2bab4 TH	53
d4b2bab4 TH	54	return ata_std_prereset(ap, deadline);
669a5db4 JG	55	}
	56
	57	/**
	58	* artop6210_error_handler - Probe specified port on PATA host controller
	59	* @ap: Port to probe
	60	*
	61	* LOCKING:
	62	* None (inherited from caller).
	63	*/
	64
	65	static void artop6210_error_handler(struct ata_port *ap)
	66	{
	67	ata_bmdma_drive_eh(ap, artop6210_pre_reset,
	68	ata_std_softreset, NULL,
	69	ata_std_postreset);
	70	}
	71
	72	/**
	73	* artop6260_pre_reset - check for 40/80 pin
	74	* @ap: Port
d4b2bab4	75	* @deadline: deadline jiffies for the operation
669a5db4 JG	76	*
	77	* The ARTOP hardware reports the cable detect bits in register 0x49.
	78	* Nothing complicated needed here.
	79	*/
	80
d4b2bab4	81	static int artop6260_pre_reset(struct ata_port *ap, unsigned long deadline)
669a5db4 JG	82	{
	83	static const struct pci_bits artop_enable_bits[] = {
	84	{ 0x4AU, 1U, 0x02UL, 0x02UL }, /* port 0 */
	85	{ 0x4AU, 1U, 0x04UL, 0x04UL }, /* port 1 */
	86	};
	87
	88	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
669a5db4 JG	89
669a5db4 JG	90	/* Odd numbered device ids are the units with enable bits (the -R cards) */
c961922b AC	91	if (pdev->device % 1 && !pci_test_config_bits(pdev, &artop_enable_bits[ap->port_no]))
c961922b AC	92	return -ENOENT;
27c78b37 JG	93
27c78b37 JG	94	return ata_std_prereset(ap, deadline);
a73984a0	95	}
c961922b	96
a73984a0 JG	97	/**
	98	* artop6260_cable_detect - identify cable type
	99	* @ap: Port
	100	*
c343a839	101	* Identify the cable type for the ARTOP interface in question
a73984a0	102	*/
a617c09f	103
a73984a0 JG	104	static int artop6260_cable_detect(struct ata_port *ap)
	105	{
	106	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	107	u8 tmp;
669a5db4	108	pci_read_config_byte(pdev, 0x49, &tmp);
3f9dd27a	109	if (tmp & (1 << ap->port_no))
a73984a0 JG	110	return ATA_CBL_PATA40;
a73984a0 JG	111	return ATA_CBL_PATA80;
669a5db4 JG	112	}
	113
	114	/**
	115	* artop6260_error_handler - Probe specified port on PATA host controller
	116	* @ap: Port to probe
	117	*
	118	* LOCKING:
	119	* None (inherited from caller).
	120	*/
	121
	122	static void artop6260_error_handler(struct ata_port *ap)
	123	{
	124	ata_bmdma_drive_eh(ap, artop6260_pre_reset,
	125	ata_std_softreset, NULL,
	126	ata_std_postreset);
	127	}
	128
	129	/**
	130	* artop6210_load_piomode - Load a set of PATA PIO timings
	131	* @ap: Port whose timings we are configuring
	132	* @adev: Device
	133	* @pio: PIO mode
	134	*
	135	* Set PIO mode for device, in host controller PCI config space. This
	136	* is used both to set PIO timings in PIO mode and also to set the
	137	* matching PIO clocking for UDMA, as well as the MWDMA timings.
	138	*
	139	* LOCKING:
	140	* None (inherited from caller).
	141	*/
	142
	143	static void artop6210_load_piomode(struct ata_port ap, struct ata_device adev, unsigned int pio)
	144	{
	145	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	146	int dn = adev->devno + 2 * ap->port_no;
	147	const u16 timing[2][5] = {
	148	{ 0x0000, 0x000A, 0x0008, 0x0303, 0x0301 },
	149	{ 0x0700, 0x070A, 0x0708, 0x0403, 0x0401 }
	150
	151	};
	152	/* Load the PIO timing active/recovery bits */
	153	pci_write_config_word(pdev, 0x40 + 2 * dn, timing[clock][pio]);
	154	}
	155
	156	/**
	157	* artop6210_set_piomode - Initialize host controller PATA PIO timings
	158	* @ap: Port whose timings we are configuring
	159	* @adev: Device we are configuring
	160	*
	161	* Set PIO mode for device, in host controller PCI config space. For
	162	* ARTOP we must also clear the UDMA bits if we are not doing UDMA. In
	163	* the event UDMA is used the later call to set_dmamode will set the
	164	* bits as required.
	165	*
	166	* LOCKING:
	167	* None (inherited from caller).
	168	*/
	169
	170	static void artop6210_set_piomode(struct ata_port ap, struct ata_device adev)
	171	{
	172	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	173	int dn = adev->devno + 2 * ap->port_no;
	174	u8 ultra;
	175
176	artop6210_load_piomode(ap, adev, adev->pio_mode - XFER_PIO_0);
177
178	/* Clear the UDMA mode bits (set_dmamode will redo this if needed) */
179	pci_read_config_byte(pdev, 0x54, &ultra);
180	ultra &= ~(3 << (2 * dn));
181	pci_write_config_byte(pdev, 0x54, ultra);
182	}
183
184	/**
185	* artop6260_load_piomode - Initialize host controller PATA PIO timings
186	* @ap: Port whose timings we are configuring
187	* @adev: Device we are configuring
188	* @pio: PIO mode
189	*
190	* Set PIO mode for device, in host controller PCI config space. The
191	* ARTOP6260 and relatives store the timing data differently.
192	*
193	* LOCKING:
194	* None (inherited from caller).
195	*/
196
197	static void artop6260_load_piomode (struct ata_port ap, struct ata_device adev, unsigned int pio)
198	{
199	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
200	int dn = adev->devno + 2 * ap->port_no;
201	const u8 timing[2][5] = {
202	{ 0x00, 0x0A, 0x08, 0x33, 0x31 },
203	{ 0x70, 0x7A, 0x78, 0x43, 0x41 }
204
205	};
206	/* Load the PIO timing active/recovery bits */
207	pci_write_config_byte(pdev, 0x40 + dn, timing[clock][pio]);
208	}
209
210	/**
211	* artop6260_set_piomode - Initialize host controller PATA PIO timings
212	* @ap: Port whose timings we are configuring
213	* @adev: Device we are configuring
214	*
215	* Set PIO mode for device, in host controller PCI config space. For
216	* ARTOP we must also clear the UDMA bits if we are not doing UDMA. In
217	* the event UDMA is used the later call to set_dmamode will set the
218	* bits as required.
219	*
220	* LOCKING:
221	* None (inherited from caller).
222	*/
223
224	static void artop6260_set_piomode(struct ata_port ap, struct ata_device adev)
225	{
226	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
227	u8 ultra;
228
229	artop6260_load_piomode(ap, adev, adev->pio_mode - XFER_PIO_0);
230
231	/* Clear the UDMA mode bits (set_dmamode will redo this if needed) */
232	pci_read_config_byte(pdev, 0x44 + ap->port_no, &ultra);
233	ultra &= ~(7 << (4 * adev->devno)); /* One nibble per drive */
234	pci_write_config_byte(pdev, 0x44 + ap->port_no, ultra);
235	}
236
237	/**
238	* artop6210_set_dmamode - Initialize host controller PATA PIO timings
239	* @ap: Port whose timings we are configuring
a73984a0	240	* @adev: Device whose timings we are configuring
669a5db4 JG	241	*
	242	* Set DMA mode for device, in host controller PCI config space.
	243	*
	244	* LOCKING:
	245	* None (inherited from caller).
	246	*/
	247
	248	static void artop6210_set_dmamode (struct ata_port ap, struct ata_device adev)
	249	{
	250	unsigned int pio;
	251	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	252	int dn = adev->devno + 2 * ap->port_no;
	253	u8 ultra;
	254
	255	if (adev->dma_mode == XFER_MW_DMA_0)
	256	pio = 1;
	257	else
	258	pio = 4;
	259
	260	/* Load the PIO timing active/recovery bits */
	261	artop6210_load_piomode(ap, adev, pio);
	262
	263	pci_read_config_byte(pdev, 0x54, &ultra);
	264	ultra &= ~(3 << (2 * dn));
	265
	266	/* Add ultra DMA bits if in UDMA mode */
	267	if (adev->dma_mode >= XFER_UDMA_0) {
	268	u8 mode = (adev->dma_mode - XFER_UDMA_0) + 1 - clock;
	269	if (mode == 0)
	270	mode = 1;
	271	ultra \|= (mode << (2 * dn));
	272	}
	273	pci_write_config_byte(pdev, 0x54, ultra);
	274	}
	275
	276	/**
	277	* artop6260_set_dmamode - Initialize host controller PATA PIO timings
	278	* @ap: Port whose timings we are configuring
	279	* @adev: Device we are configuring
	280	*
	281	* Set DMA mode for device, in host controller PCI config space. The
	282	* ARTOP6260 and relatives store the timing data differently.
	283	*
	284	* LOCKING:
	285	* None (inherited from caller).
	286	*/
	287
	288	static void artop6260_set_dmamode (struct ata_port ap, struct ata_device adev)
	289	{
	290	unsigned int pio = adev->pio_mode - XFER_PIO_0;
	291	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	292	u8 ultra;
	293
	294	if (adev->dma_mode == XFER_MW_DMA_0)
	295	pio = 1;
	296	else
	297	pio = 4;
	298
	299	/* Load the PIO timing active/recovery bits */
	300	artop6260_load_piomode(ap, adev, pio);
	301
	302	/* Add ultra DMA bits if in UDMA mode */
	303	pci_read_config_byte(pdev, 0x44 + ap->port_no, &ultra);
	304	ultra &= ~(7 << (4 * adev->devno)); /* One nibble per drive */
305	if (adev->dma_mode >= XFER_UDMA_0) {
306	u8 mode = adev->dma_mode - XFER_UDMA_0 + 1 - clock;
307	if (mode == 0)
308	mode = 1;
309	ultra \|= (mode << (4 * adev->devno));
310	}
311	pci_write_config_byte(pdev, 0x44 + ap->port_no, ultra);
312	}
313
314	static struct scsi_host_template artop_sht = {
315	.module = THIS_MODULE,
316	.name = DRV_NAME,
317	.ioctl = ata_scsi_ioctl,
318	.queuecommand = ata_scsi_queuecmd,
319	.can_queue = ATA_DEF_QUEUE,
320	.this_id = ATA_SHT_THIS_ID,
321	.sg_tablesize = LIBATA_MAX_PRD,
669a5db4 JG	322	.cmd_per_lun = ATA_SHT_CMD_PER_LUN,
	323	.emulated = ATA_SHT_EMULATED,
	324	.use_clustering = ATA_SHT_USE_CLUSTERING,
	325	.proc_name = DRV_NAME,
	326	.dma_boundary = ATA_DMA_BOUNDARY,
	327	.slave_configure = ata_scsi_slave_config,
afdfe899	328	.slave_destroy = ata_scsi_slave_destroy,
669a5db4 JG	329	.bios_param = ata_std_bios_param,
	330	};
	331
	332	static const struct ata_port_operations artop6210_ops = {
	333	.port_disable = ata_port_disable,
	334	.set_piomode = artop6210_set_piomode,
	335	.set_dmamode = artop6210_set_dmamode,
	336	.mode_filter = ata_pci_default_filter,
	337
	338	.tf_load = ata_tf_load,
	339	.tf_read = ata_tf_read,
	340	.check_status = ata_check_status,
	341	.exec_command = ata_exec_command,
	342	.dev_select = ata_std_dev_select,
	343
	344	.freeze = ata_bmdma_freeze,
	345	.thaw = ata_bmdma_thaw,
	346	.error_handler = artop6210_error_handler,
	347	.post_internal_cmd = ata_bmdma_post_internal_cmd,
a73984a0	348	.cable_detect = ata_cable_40wire,
669a5db4 JG	349
	350	.bmdma_setup = ata_bmdma_setup,
	351	.bmdma_start = ata_bmdma_start,
	352	.bmdma_stop = ata_bmdma_stop,
	353	.bmdma_status = ata_bmdma_status,
	354	.qc_prep = ata_qc_prep,
	355	.qc_issue = ata_qc_issue_prot,
bda30288	356
0d5ff566	357	.data_xfer = ata_data_xfer,
669a5db4 JG	358
	359	.irq_handler = ata_interrupt,
	360	.irq_clear = ata_bmdma_irq_clear,
246ce3b6 AI	361	.irq_on = ata_irq_on,
246ce3b6 AI	362	.irq_ack = ata_irq_ack,
669a5db4 JG	363
669a5db4 JG	364	.port_start = ata_port_start,
669a5db4 JG	365	};
	366
	367	static const struct ata_port_operations artop6260_ops = {
	368	.port_disable = ata_port_disable,
	369	.set_piomode = artop6260_set_piomode,
	370	.set_dmamode = artop6260_set_dmamode,
	371
	372	.tf_load = ata_tf_load,
	373	.tf_read = ata_tf_read,
	374	.check_status = ata_check_status,
	375	.exec_command = ata_exec_command,
	376	.dev_select = ata_std_dev_select,
	377
	378	.freeze = ata_bmdma_freeze,
	379	.thaw = ata_bmdma_thaw,
	380	.error_handler = artop6260_error_handler,
	381	.post_internal_cmd = ata_bmdma_post_internal_cmd,
a73984a0	382	.cable_detect = artop6260_cable_detect,
669a5db4 JG	383
	384	.bmdma_setup = ata_bmdma_setup,
	385	.bmdma_start = ata_bmdma_start,
	386	.bmdma_stop = ata_bmdma_stop,
	387	.bmdma_status = ata_bmdma_status,
	388	.qc_prep = ata_qc_prep,
	389	.qc_issue = ata_qc_issue_prot,
0d5ff566	390	.data_xfer = ata_data_xfer,
669a5db4	391
669a5db4 JG	392	.irq_handler = ata_interrupt,
669a5db4 JG	393	.irq_clear = ata_bmdma_irq_clear,
246ce3b6 AI	394	.irq_on = ata_irq_on,
246ce3b6 AI	395	.irq_ack = ata_irq_ack,
669a5db4 JG	396
669a5db4 JG	397	.port_start = ata_port_start,
669a5db4 JG	398	};
	399
	400
	401	/**
	402	* artop_init_one - Register ARTOP ATA PCI device with kernel services
	403	* @pdev: PCI device to register
	404	* @ent: Entry in artop_pci_tbl matching with @pdev
	405	*
	406	* Called from kernel PCI layer.
	407	*
	408	* LOCKING:
	409	* Inherited from PCI layer (may sleep).
	410	*
	411	* RETURNS:
	412	* Zero on success, or -ERRNO value.
	413	*/
	414
	415	static int artop_init_one (struct pci_dev pdev, const struct pci_device_id id)
	416	{
	417	static int printed_version;
1626aeb8	418	static const struct ata_port_info info_6210 = {
669a5db4	419	.sht = &artop_sht,
1d2808fd	420	.flags = ATA_FLAG_SLAVE_POSS,
669a5db4 JG	421	.pio_mask = 0x1f, /* pio0-4 */
	422	.mwdma_mask = 0x07, /* mwdma0-2 */
	423	.udma_mask = ATA_UDMA2,
	424	.port_ops = &artop6210_ops,
	425	};
1626aeb8	426	static const struct ata_port_info info_626x = {
669a5db4	427	.sht = &artop_sht,
1d2808fd	428	.flags = ATA_FLAG_SLAVE_POSS,
669a5db4 JG	429	.pio_mask = 0x1f, /* pio0-4 */
	430	.mwdma_mask = 0x07, /* mwdma0-2 */
	431	.udma_mask = ATA_UDMA4,
	432	.port_ops = &artop6260_ops,
	433	};
be456b77	434	static const struct ata_port_info info_628x = {
669a5db4	435	.sht = &artop_sht,
1d2808fd	436	.flags = ATA_FLAG_SLAVE_POSS,
669a5db4 JG	437	.pio_mask = 0x1f, /* pio0-4 */
	438	.mwdma_mask = 0x07, /* mwdma0-2 */
	439	.udma_mask = ATA_UDMA5,
	440	.port_ops = &artop6260_ops,
	441	};
be456b77 BZ	442	static const struct ata_port_info info_628x_fast = {
	443	.sht = &artop_sht,
	444	.flags = ATA_FLAG_SLAVE_POSS,
	445	.pio_mask = 0x1f, /* pio0-4 */
	446	.mwdma_mask = 0x07, /* mwdma0-2 */
	447	.udma_mask = ATA_UDMA6,
	448	.port_ops = &artop6260_ops,
	449	};
1626aeb8	450	const struct ata_port_info *ppi[] = { NULL, NULL };
669a5db4 JG	451
	452	if (!printed_version++)
	453	dev_printk(KERN_DEBUG, &pdev->dev,
	454	"version " DRV_VERSION "\n");
	455
	456	if (id->driver_data == 0) { /* 6210 variant */
1626aeb8 TH	457	ppi[0] = &info_6210;
1626aeb8 TH	458	ppi[1] = &ata_dummy_port_info;
669a5db4 JG	459	/* BIOS may have left us in UDMA, clear it before libata probe */
	460	pci_write_config_byte(pdev, 0x54, 0);
	461	/* For the moment (also lacks dsc) */
	462	printk(KERN_WARNING "ARTOP 6210 requires serialize functionality not yet supported by libata.\n");
	463	printk(KERN_WARNING "Secondary ATA ports will not be activated.\n");
669a5db4 JG	464	}
669a5db4 JG	465	else if (id->driver_data == 1) /* 6260 */
1626aeb8	466	ppi[0] = &info_626x;
be456b77	467	else if (id->driver_data == 2) { /* 6280 or 6280 + fast */
669a5db4 JG	468	unsigned long io = pci_resource_start(pdev, 4);
	469	u8 reg;
	470
be456b77	471	ppi[0] = &info_628x;
669a5db4	472	if (inb(io) & 0x10)
be456b77	473	ppi[0] = &info_628x_fast;
669a5db4 JG	474	/* Mac systems come up with some registers not set as we
	475	will need them */
	476
	477	/* Clear reset & test bits */
	478	pci_read_config_byte(pdev, 0x49, &reg);
	479	pci_write_config_byte(pdev, 0x49, reg & ~ 0x30);
	480
	481	/* PCI latency must be > 0x80 for burst mode, tweak it
	482	* if required.
	483	*/
	484	pci_read_config_byte(pdev, PCI_LATENCY_TIMER, &reg);
	485	if (reg <= 0x80)
	486	pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0x90);
	487
	488	/* Enable IRQ output and burst mode */
	489	pci_read_config_byte(pdev, 0x4a, &reg);
	490	pci_write_config_byte(pdev, 0x4a, (reg & ~0x01) \| 0x80);
	491
	492	}
15a7c3bb	493
1626aeb8	494	BUG_ON(ppi[0] == NULL);
15a7c3bb	495
1626aeb8	496	return ata_pci_init_one(pdev, ppi);
669a5db4 JG	497	}
	498
	499	static const struct pci_device_id artop_pci_tbl[] = {
2d2744fc JG	500	{ PCI_VDEVICE(ARTOP, 0x0005), 0 },
	501	{ PCI_VDEVICE(ARTOP, 0x0006), 1 },
	502	{ PCI_VDEVICE(ARTOP, 0x0007), 1 },
	503	{ PCI_VDEVICE(ARTOP, 0x0008), 2 },
	504	{ PCI_VDEVICE(ARTOP, 0x0009), 2 },
	505
669a5db4 JG	506	{ } /* terminate list */
	507	};
	508
	509	static struct pci_driver artop_pci_driver = {
	510	.name = DRV_NAME,
	511	.id_table = artop_pci_tbl,
	512	.probe = artop_init_one,
	513	.remove = ata_pci_remove_one,
	514	};
	515
	516	static int __init artop_init(void)
	517	{
	518	return pci_register_driver(&artop_pci_driver);
	519	}
	520
	521	static void __exit artop_exit(void)
	522	{
	523	pci_unregister_driver(&artop_pci_driver);
	524	}
	525
669a5db4 JG	526	module_init(artop_init);
	527	module_exit(artop_exit);
	528
	529	MODULE_AUTHOR("Alan Cox");
	530	MODULE_DESCRIPTION("SCSI low-level driver for ARTOP PATA");
	531	MODULE_LICENSE("GPL");
	532	MODULE_DEVICE_TABLE(pci, artop_pci_tbl);
	533	MODULE_VERSION(DRV_VERSION);
	534