[deliverable/linux.git] / drivers / ata / pata_cmd64x.c

/*
 * pata_cmd64x.c 	- ATI PATA for new ATA layer
 *			  (C) 2005 Red Hat Inc
 *			  Alan Cox <alan@redhat.com>
 *
 * Based upon
 * linux/drivers/ide/pci/cmd64x.c		Version 1.30	Sept 10, 2002
 *
 * cmd64x.c: Enable interrupts at initialization time on Ultra/PCI machines.
 *           Note, this driver is not used at all on other systems because
 *           there the "BIOS" has done all of the following already.
 *           Due to massive hardware bugs, UltraDMA is only supported
 *           on the 646U2 and not on the 646U.
 *
 * Copyright (C) 1998		Eddie C. Dost  (ecd@skynet.be)
 * Copyright (C) 1998		David S. Miller (davem@redhat.com)
 *
 * Copyright (C) 1999-2002	Andre Hedrick <andre@linux-ide.org>
 *
 * TODO
 *	Testing work
 */

#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/pci.h>
#include <linux/init.h>
#include <linux/blkdev.h>
#include <linux/delay.h>
#include <scsi/scsi_host.h>
#include <linux/libata.h>

#define DRV_NAME "pata_cmd64x"
#define DRV_VERSION "0.2.2"

/*
 * CMD64x specific registers definition.
 */

enum {
	CFR 		= 0x50,
		CFR_INTR_CH0  = 0x02,
	CNTRL 		= 0x51,
		CNTRL_DIS_RA0 = 0x40,
		CNTRL_DIS_RA1 = 0x80,
		CNTRL_ENA_2ND = 0x08,
	CMDTIM 		= 0x52,
	ARTTIM0 	= 0x53,
	DRWTIM0 	= 0x54,
	ARTTIM1 	= 0x55,
	DRWTIM1 	= 0x56,
	ARTTIM23 	= 0x57,
		ARTTIM23_DIS_RA2  = 0x04,
		ARTTIM23_DIS_RA3  = 0x08,
		ARTTIM23_INTR_CH1 = 0x10,
	ARTTIM2 	= 0x57,
	ARTTIM3 	= 0x57,
	DRWTIM23	= 0x58,
	DRWTIM2 	= 0x58,
	BRST 		= 0x59,
	DRWTIM3 	= 0x5b,
	BMIDECR0	= 0x70,
	MRDMODE		= 0x71,
		MRDMODE_INTR_CH0 = 0x04,
		MRDMODE_INTR_CH1 = 0x08,
		MRDMODE_BLK_CH0  = 0x10,
		MRDMODE_BLK_CH1	 = 0x20,
	BMIDESR0	= 0x72,
	UDIDETCR0	= 0x73,
	DTPR0		= 0x74,
	BMIDECR1	= 0x78,
	BMIDECSR	= 0x79,
	BMIDESR1	= 0x7A,
	UDIDETCR1	= 0x7B,
	DTPR1		= 0x7C
};

static int cmd64x_pre_reset(struct ata_port *ap)
{
	ap->cbl = ATA_CBL_PATA40;
	return ata_std_prereset(ap);
}

static int cmd648_pre_reset(struct ata_port *ap)
{
	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	u8 r;

	/* Check cable detect bits */
	pci_read_config_byte(pdev, BMIDECSR, &r);
	if (r & (1 << ap->port_no))
		ap->cbl = ATA_CBL_PATA80;
	else
		ap->cbl = ATA_CBL_PATA40;

	return ata_std_prereset(ap);
}

static void cmd64x_error_handler(struct ata_port *ap)
{
	return ata_bmdma_drive_eh(ap, cmd64x_pre_reset, ata_std_softreset, NULL, ata_std_postreset);
}

static void cmd648_error_handler(struct ata_port *ap)
{
	ata_bmdma_drive_eh(ap, cmd648_pre_reset, ata_std_softreset, NULL, ata_std_postreset);
}

/**
 *	cmd64x_set_piomode	-	set initial PIO mode data
 *	@ap: ATA interface
 *	@adev: ATA device
 *
 *	Called to do the PIO mode setup.
 */

static void cmd64x_set_piomode(struct ata_port *ap, struct ata_device *adev)
{
	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	struct ata_timing t;
	const unsigned long T = 1000000 / 33;
	const u8 setup_data[] = { 0x40, 0x40, 0x40, 0x80, 0x00 };

	u8 reg;

	/* Port layout is not logical so use a table */
	const u8 arttim_port[2][2] = {
		{ ARTTIM0, ARTTIM1 },
		{ ARTTIM23, ARTTIM23 }
	};
	const u8 drwtim_port[2][2] = {
		{ DRWTIM0, DRWTIM1 },
		{ DRWTIM2, DRWTIM3 }
	};

	int arttim = arttim_port[ap->port_no][adev->devno];
	int drwtim = drwtim_port[ap->port_no][adev->devno];


	if (ata_timing_compute(adev, adev->pio_mode, &t, T, 0) < 0) {
		printk(KERN_ERR DRV_NAME ": mode computation failed.\n");
		return;
	}
	if (ap->port_no) {
		/* Slave has shared address setup */
		struct ata_device *pair = ata_dev_pair(adev);

		if (pair) {
			struct ata_timing tp;
			ata_timing_compute(pair, pair->pio_mode, &tp, T, 0);
			ata_timing_merge(&t, &tp, &t, ATA_TIMING_SETUP);
		}
	}

	printk(KERN_DEBUG DRV_NAME ": active %d recovery %d setup %d.\n",
		t.active, t.recover, t.setup);
	if (t.recover > 16) {
		t.active += t.recover - 16;
		t.recover = 16;
	}
	if (t.active > 16)
		t.active = 16;

	/* Now convert the clocks into values we can actually stuff into
	   the chip */

	if (t.recover > 1)
		t.recover--;
	else
		t.recover = 15;

	if (t.setup > 4)
		t.setup = 0xC0;
	else
		t.setup = setup_data[t.setup];

	t.active &= 0x0F;	/* 0 = 16 */

	/* Load setup timing */
	pci_read_config_byte(pdev, arttim, &reg);
	reg &= 0x3F;
	reg |= t.setup;
	pci_write_config_byte(pdev, arttim, reg);

	/* Load active/recovery */
	pci_write_config_byte(pdev, drwtim, (t.active << 4) | t.recover);
}

/**
 *	cmd64x_set_dmamode	-	set initial DMA mode data
 *	@ap: ATA interface
 *	@adev: ATA device
 *
 *	Called to do the DMA mode setup.
 */

static void cmd64x_set_dmamode(struct ata_port *ap, struct ata_device *adev)
{
	static const u8 udma_data[] = {
		0x30, 0x20, 0x10, 0x20, 0x10, 0x00
	};
	static const u8 mwdma_data[] = {
		0x30, 0x20, 0x10
	};

	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	u8 regU, regD;

	int pciU = UDIDETCR0 + 8 * ap->port_no;
	int pciD = BMIDESR0 + 8 * ap->port_no;
	int shift = 2 * adev->devno;

	pci_read_config_byte(pdev, pciD, &regD);
	pci_read_config_byte(pdev, pciU, &regU);

	/* DMA bits off */
	regD &= ~(0x20 << adev->devno);
	/* DMA control bits */
	regU &= ~(0x30 << shift);
	/* DMA timing bits */
	regU &= ~(0x05 << adev->devno);

	if (adev->dma_mode >= XFER_UDMA_0) {
		/* Merge thge timing value */
		regU |= udma_data[adev->dma_mode - XFER_UDMA_0] << shift;
		/* Merge the control bits */
		regU |= 1 << adev->devno; /* UDMA on */
		if (adev->dma_mode > 2)	/* 15nS timing */
			regU |= 4 << adev->devno;
	} else
		regD |= mwdma_data[adev->dma_mode - XFER_MW_DMA_0] << shift;

	regD |= 0x20 << adev->devno;

	pci_write_config_byte(pdev, pciU, regU);
	pci_write_config_byte(pdev, pciD, regD);
}

/**
 *	cmd648_dma_stop	-	DMA stop callback
 *	@qc: Command in progress
 *
 *	DMA has completed.
 */

static void cmd648_bmdma_stop(struct ata_queued_cmd *qc)
{
	struct ata_port *ap = qc->ap;
	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	u8 dma_intr;
	int dma_mask = ap->port_no ? ARTTIM23_INTR_CH1 : CFR_INTR_CH0;
	int dma_reg = ap->port_no ? ARTTIM2 : CFR;

	ata_bmdma_stop(qc);

	pci_read_config_byte(pdev, dma_reg, &dma_intr);
	pci_write_config_byte(pdev, dma_reg, dma_intr | dma_mask);
}

/**
 *	cmd646r1_dma_stop	-	DMA stop callback
 *	@qc: Command in progress
 *
 *	Stub for now while investigating the r1 quirk in the old driver.
 */

static void cmd646r1_bmdma_stop(struct ata_queued_cmd *qc)
{
	ata_bmdma_stop(qc);
}

static struct scsi_host_template cmd64x_sht = {
	.module			= THIS_MODULE,
	.name			= DRV_NAME,
	.ioctl			= ata_scsi_ioctl,
	.queuecommand		= ata_scsi_queuecmd,
	.can_queue		= ATA_DEF_QUEUE,
	.this_id		= ATA_SHT_THIS_ID,
	.sg_tablesize		= LIBATA_MAX_PRD,
	.cmd_per_lun		= ATA_SHT_CMD_PER_LUN,
	.emulated		= ATA_SHT_EMULATED,
	.use_clustering		= ATA_SHT_USE_CLUSTERING,
	.proc_name		= DRV_NAME,
	.dma_boundary		= ATA_DMA_BOUNDARY,
	.slave_configure	= ata_scsi_slave_config,
	.slave_destroy		= ata_scsi_slave_destroy,
	.bios_param		= ata_std_bios_param,
	.resume			= ata_scsi_device_resume,
	.suspend		= ata_scsi_device_suspend,
};

static struct ata_port_operations cmd64x_port_ops = {
	.port_disable	= ata_port_disable,
	.set_piomode	= cmd64x_set_piomode,
	.set_dmamode	= cmd64x_set_dmamode,
	.mode_filter	= ata_pci_default_filter,
	.tf_load	= ata_tf_load,
	.tf_read	= ata_tf_read,
	.check_status 	= ata_check_status,
	.exec_command	= ata_exec_command,
	.dev_select 	= ata_std_dev_select,

	.freeze		= ata_bmdma_freeze,
	.thaw		= ata_bmdma_thaw,
	.error_handler	= cmd64x_error_handler,
	.post_internal_cmd = ata_bmdma_post_internal_cmd,

	.bmdma_setup 	= ata_bmdma_setup,
	.bmdma_start 	= ata_bmdma_start,
	.bmdma_stop	= ata_bmdma_stop,
	.bmdma_status 	= ata_bmdma_status,

	.qc_prep 	= ata_qc_prep,
	.qc_issue	= ata_qc_issue_prot,

	.data_xfer	= ata_pio_data_xfer,

	.irq_handler	= ata_interrupt,
	.irq_clear	= ata_bmdma_irq_clear,

	.port_start	= ata_port_start,
};

static struct ata_port_operations cmd646r1_port_ops = {
	.port_disable	= ata_port_disable,
	.set_piomode	= cmd64x_set_piomode,
	.set_dmamode	= cmd64x_set_dmamode,
	.mode_filter	= ata_pci_default_filter,
	.tf_load	= ata_tf_load,
	.tf_read	= ata_tf_read,
	.check_status 	= ata_check_status,
	.exec_command	= ata_exec_command,
	.dev_select 	= ata_std_dev_select,

	.freeze		= ata_bmdma_freeze,
	.thaw		= ata_bmdma_thaw,
	.error_handler	= cmd64x_error_handler,
	.post_internal_cmd = ata_bmdma_post_internal_cmd,

	.bmdma_setup 	= ata_bmdma_setup,
	.bmdma_start 	= ata_bmdma_start,
	.bmdma_stop	= cmd646r1_bmdma_stop,
	.bmdma_status 	= ata_bmdma_status,

	.qc_prep 	= ata_qc_prep,
	.qc_issue	= ata_qc_issue_prot,

	.data_xfer	= ata_pio_data_xfer,

	.irq_handler	= ata_interrupt,
	.irq_clear	= ata_bmdma_irq_clear,

	.port_start	= ata_port_start,
};

static struct ata_port_operations cmd648_port_ops = {
	.port_disable	= ata_port_disable,
	.set_piomode	= cmd64x_set_piomode,
	.set_dmamode	= cmd64x_set_dmamode,
	.mode_filter	= ata_pci_default_filter,
	.tf_load	= ata_tf_load,
	.tf_read	= ata_tf_read,
	.check_status 	= ata_check_status,
	.exec_command	= ata_exec_command,
	.dev_select 	= ata_std_dev_select,

	.freeze		= ata_bmdma_freeze,
	.thaw		= ata_bmdma_thaw,
	.error_handler	= cmd648_error_handler,
	.post_internal_cmd = ata_bmdma_post_internal_cmd,

	.bmdma_setup 	= ata_bmdma_setup,
	.bmdma_start 	= ata_bmdma_start,
	.bmdma_stop	= cmd648_bmdma_stop,
	.bmdma_status 	= ata_bmdma_status,

	.qc_prep 	= ata_qc_prep,
	.qc_issue	= ata_qc_issue_prot,

	.data_xfer	= ata_pio_data_xfer,

	.irq_handler	= ata_interrupt,
	.irq_clear	= ata_bmdma_irq_clear,

	.port_start	= ata_port_start,
};

static int cmd64x_init_one(struct pci_dev *pdev, const struct pci_device_id *id)
{
	u32 class_rev;

	static struct ata_port_info cmd_info[6] = {
		{	/* CMD 643 - no UDMA */
			.sht = &cmd64x_sht,
			.flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
			.pio_mask = 0x1f,
			.mwdma_mask = 0x07,
			.port_ops = &cmd64x_port_ops
		},
		{	/* CMD 646 with broken UDMA */
			.sht = &cmd64x_sht,
			.flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
			.pio_mask = 0x1f,
			.mwdma_mask = 0x07,
			.port_ops = &cmd64x_port_ops
		},
		{	/* CMD 646 with working UDMA */
			.sht = &cmd64x_sht,
			.flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
			.pio_mask = 0x1f,
			.mwdma_mask = 0x07,
			.udma_mask = ATA_UDMA1,
			.port_ops = &cmd64x_port_ops
		},
		{	/* CMD 646 rev 1  */
			.sht = &cmd64x_sht,
			.flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
			.pio_mask = 0x1f,
			.mwdma_mask = 0x07,
			.port_ops = &cmd646r1_port_ops
		},
		{	/* CMD 648 */
			.sht = &cmd64x_sht,
			.flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
			.pio_mask = 0x1f,
			.mwdma_mask = 0x07,
			.udma_mask = ATA_UDMA2,
			.port_ops = &cmd648_port_ops
		},
		{	/* CMD 649 */
			.sht = &cmd64x_sht,
			.flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
			.pio_mask = 0x1f,
			.mwdma_mask = 0x07,
			.udma_mask = ATA_UDMA3,
			.port_ops = &cmd648_port_ops
		}
	};
	static struct ata_port_info *port_info[2], *info;
	u8 mrdmode;

	info = &cmd_info[id->driver_data];

	pci_read_config_dword(pdev, PCI_CLASS_REVISION, &class_rev);
	class_rev &= 0xFF;

	if (id->driver_data == 0)	/* 643 */
		ata_pci_clear_simplex(pdev);

	if (pdev->device == PCI_DEVICE_ID_CMD_646) {
		/* Does UDMA work ? */
		if (class_rev > 4)
			info = &cmd_info[2];
		/* Early rev with other problems ? */
		else if (class_rev == 1)
			info = &cmd_info[3];
	}

	pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 64);
	pci_read_config_byte(pdev, MRDMODE, &mrdmode);
	mrdmode &= ~ 0x30;	/* IRQ set up */
	mrdmode |= 0x02;	/* Memory read line enable */
	pci_write_config_byte(pdev, MRDMODE, mrdmode);

	/* Force PIO 0 here.. */

	/* PPC specific fixup copied from old driver */
#ifdef CONFIG_PPC
	pci_write_config_byte(pdev, UDIDETCR0, 0xF0);
#endif

	port_info[0] = port_info[1] = info;
	return ata_pci_init_one(pdev, port_info, 2);
}

static int cmd64x_reinit_one(struct pci_dev *pdev)
{
	u8 mrdmode;
	pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 64);
	pci_read_config_byte(pdev, MRDMODE, &mrdmode);
	mrdmode &= ~ 0x30;	/* IRQ set up */
	mrdmode |= 0x02;	/* Memory read line enable */
	pci_write_config_byte(pdev, MRDMODE, mrdmode);
#ifdef CONFIG_PPC
	pci_write_config_byte(pdev, UDIDETCR0, 0xF0);
#endif
	return ata_pci_device_resume(pdev);
}

static const struct pci_device_id cmd64x[] = {
	{ PCI_VDEVICE(CMD, PCI_DEVICE_ID_CMD_643), 0 },
	{ PCI_VDEVICE(CMD, PCI_DEVICE_ID_CMD_646), 1 },
	{ PCI_VDEVICE(CMD, PCI_DEVICE_ID_CMD_648), 4 },
	{ PCI_VDEVICE(CMD, PCI_DEVICE_ID_CMD_649), 5 },

	{ },
};

static struct pci_driver cmd64x_pci_driver = {
	.name 		= DRV_NAME,
	.id_table	= cmd64x,
	.probe 		= cmd64x_init_one,
	.remove		= ata_pci_remove_one,
	.suspend	= ata_pci_device_suspend,
	.resume		= cmd64x_reinit_one,
};

static int __init cmd64x_init(void)
{
	return pci_register_driver(&cmd64x_pci_driver);
}

static void __exit cmd64x_exit(void)
{
	pci_unregister_driver(&cmd64x_pci_driver);
}

MODULE_AUTHOR("Alan Cox");
MODULE_DESCRIPTION("low-level driver for CMD64x series PATA controllers");
MODULE_LICENSE("GPL");
MODULE_DEVICE_TABLE(pci, cmd64x);
MODULE_VERSION(DRV_VERSION);

module_init(cmd64x_init);
module_exit(cmd64x_exit);
Commit	Line	Data
669a5db4 JG	1	/*
	2	* pata_cmd64x.c - ATI PATA for new ATA layer
	3	* (C) 2005 Red Hat Inc
	4	* Alan Cox <alan@redhat.com>
	5	*
	6	* Based upon
	7	* linux/drivers/ide/pci/cmd64x.c Version 1.30 Sept 10, 2002
	8	*
	9	* cmd64x.c: Enable interrupts at initialization time on Ultra/PCI machines.
	10	* Note, this driver is not used at all on other systems because
	11	* there the "BIOS" has done all of the following already.
	12	* Due to massive hardware bugs, UltraDMA is only supported
	13	* on the 646U2 and not on the 646U.
	14	*
	15	* Copyright (C) 1998 Eddie C. Dost (ecd@skynet.be)
	16	* Copyright (C) 1998 David S. Miller (davem@redhat.com)
	17	*
	18	* Copyright (C) 1999-2002 Andre Hedrick <andre@linux-ide.org>
	19	*
	20	* TODO
	21	* Testing work
	22	*/
85cd7251	23
669a5db4 JG	24	#include <linux/kernel.h>
	25	#include <linux/module.h>
	26	#include <linux/pci.h>
	27	#include <linux/init.h>
	28	#include <linux/blkdev.h>
	29	#include <linux/delay.h>
	30	#include <scsi/scsi_host.h>
	31	#include <linux/libata.h>
	32
	33	#define DRV_NAME "pata_cmd64x"
7f72a379	34	#define DRV_VERSION "0.2.2"
669a5db4 JG	35
	36	/*
	37	* CMD64x specific registers definition.
	38	*/
85cd7251	39
669a5db4 JG	40	enum {
	41	CFR = 0x50,
	42	CFR_INTR_CH0 = 0x02,
	43	CNTRL = 0x51,
	44	CNTRL_DIS_RA0 = 0x40,
	45	CNTRL_DIS_RA1 = 0x80,
	46	CNTRL_ENA_2ND = 0x08,
	47	CMDTIM = 0x52,
	48	ARTTIM0 = 0x53,
	49	DRWTIM0 = 0x54,
	50	ARTTIM1 = 0x55,
	51	DRWTIM1 = 0x56,
	52	ARTTIM23 = 0x57,
	53	ARTTIM23_DIS_RA2 = 0x04,
	54	ARTTIM23_DIS_RA3 = 0x08,
	55	ARTTIM23_INTR_CH1 = 0x10,
	56	ARTTIM2 = 0x57,
	57	ARTTIM3 = 0x57,
	58	DRWTIM23 = 0x58,
	59	DRWTIM2 = 0x58,
	60	BRST = 0x59,
	61	DRWTIM3 = 0x5b,
	62	BMIDECR0 = 0x70,
	63	MRDMODE = 0x71,
	64	MRDMODE_INTR_CH0 = 0x04,
	65	MRDMODE_INTR_CH1 = 0x08,
	66	MRDMODE_BLK_CH0 = 0x10,
	67	MRDMODE_BLK_CH1 = 0x20,
	68	BMIDESR0 = 0x72,
	69	UDIDETCR0 = 0x73,
	70	DTPR0 = 0x74,
	71	BMIDECR1 = 0x78,
	72	BMIDECSR = 0x79,
	73	BMIDESR1 = 0x7A,
	74	UDIDETCR1 = 0x7B,
	75	DTPR1 = 0x7C
	76	};
	77
	78	static int cmd64x_pre_reset(struct ata_port *ap)
	79	{
	80	ap->cbl = ATA_CBL_PATA40;
	81	return ata_std_prereset(ap);
	82	}
	83
	84	static int cmd648_pre_reset(struct ata_port *ap)
	85	{
	86	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	87	u8 r;
	88
	89	/* Check cable detect bits */
	90	pci_read_config_byte(pdev, BMIDECSR, &r);
	91	if (r & (1 << ap->port_no))
	92	ap->cbl = ATA_CBL_PATA80;
85cd7251	93	else
669a5db4	94	ap->cbl = ATA_CBL_PATA40;
85cd7251	95
669a5db4 JG	96	return ata_std_prereset(ap);
	97	}
	98
	99	static void cmd64x_error_handler(struct ata_port *ap)
	100	{
	101	return ata_bmdma_drive_eh(ap, cmd64x_pre_reset, ata_std_softreset, NULL, ata_std_postreset);
	102	}
	103
	104	static void cmd648_error_handler(struct ata_port *ap)
	105	{
	106	ata_bmdma_drive_eh(ap, cmd648_pre_reset, ata_std_softreset, NULL, ata_std_postreset);
	107	}
	108
	109	/**
	110	* cmd64x_set_piomode - set initial PIO mode data
	111	* @ap: ATA interface
	112	* @adev: ATA device
	113	*
	114	* Called to do the PIO mode setup.
	115	*/
85cd7251	116
669a5db4 JG	117	static void cmd64x_set_piomode(struct ata_port ap, struct ata_device adev)
	118	{
	119	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	120	struct ata_timing t;
	121	const unsigned long T = 1000000 / 33;
	122	const u8 setup_data[] = { 0x40, 0x40, 0x40, 0x80, 0x00 };
85cd7251	123
669a5db4	124	u8 reg;
85cd7251	125
669a5db4	126	/* Port layout is not logical so use a table */
85cd7251	127	const u8 arttim_port[2][2] = {
669a5db4 JG	128	{ ARTTIM0, ARTTIM1 },
	129	{ ARTTIM23, ARTTIM23 }
	130	};
	131	const u8 drwtim_port[2][2] = {
	132	{ DRWTIM0, DRWTIM1 },
	133	{ DRWTIM2, DRWTIM3 }
	134	};
85cd7251	135
669a5db4 JG	136	int arttim = arttim_port[ap->port_no][adev->devno];
669a5db4 JG	137	int drwtim = drwtim_port[ap->port_no][adev->devno];
85cd7251 JG	138
85cd7251 JG	139
669a5db4 JG	140	if (ata_timing_compute(adev, adev->pio_mode, &t, T, 0) < 0) {
	141	printk(KERN_ERR DRV_NAME ": mode computation failed.\n");
	142	return;
	143	}
	144	if (ap->port_no) {
	145	/* Slave has shared address setup */
	146	struct ata_device *pair = ata_dev_pair(adev);
85cd7251	147
669a5db4 JG	148	if (pair) {
	149	struct ata_timing tp;
	150	ata_timing_compute(pair, pair->pio_mode, &tp, T, 0);
	151	ata_timing_merge(&t, &tp, &t, ATA_TIMING_SETUP);
	152	}
	153	}
85cd7251	154
669a5db4 JG	155	printk(KERN_DEBUG DRV_NAME ": active %d recovery %d setup %d.\n",
	156	t.active, t.recover, t.setup);
	157	if (t.recover > 16) {
	158	t.active += t.recover - 16;
	159	t.recover = 16;
	160	}
	161	if (t.active > 16)
	162	t.active = 16;
85cd7251	163
669a5db4 JG	164	/* Now convert the clocks into values we can actually stuff into
669a5db4 JG	165	the chip */
85cd7251	166
669a5db4 JG	167	if (t.recover > 1)
	168	t.recover--;
	169	else
	170	t.recover = 15;
85cd7251	171
669a5db4 JG	172	if (t.setup > 4)
	173	t.setup = 0xC0;
	174	else
	175	t.setup = setup_data[t.setup];
85cd7251	176
669a5db4	177	t.active &= 0x0F; /* 0 = 16 */
85cd7251	178
669a5db4 JG	179	/* Load setup timing */
	180	pci_read_config_byte(pdev, arttim, &reg);
	181	reg &= 0x3F;
	182	reg \|= t.setup;
	183	pci_write_config_byte(pdev, arttim, reg);
85cd7251	184
669a5db4	185	/* Load active/recovery */
85cd7251	186	pci_write_config_byte(pdev, drwtim, (t.active << 4) \| t.recover);
669a5db4 JG	187	}
	188
	189	/**
	190	* cmd64x_set_dmamode - set initial DMA mode data
	191	* @ap: ATA interface
	192	* @adev: ATA device
	193	*
	194	* Called to do the DMA mode setup.
	195	*/
85cd7251	196
669a5db4 JG	197	static void cmd64x_set_dmamode(struct ata_port ap, struct ata_device adev)
	198	{
	199	static const u8 udma_data[] = {
6a40da02	200	0x30, 0x20, 0x10, 0x20, 0x10, 0x00
669a5db4	201	};
85cd7251	202	static const u8 mwdma_data[] = {
669a5db4 JG	203	0x30, 0x20, 0x10
669a5db4 JG	204	};
85cd7251	205
669a5db4 JG	206	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	207	u8 regU, regD;
	208
	209	int pciU = UDIDETCR0 + 8 * ap->port_no;
	210	int pciD = BMIDESR0 + 8 * ap->port_no;
	211	int shift = 2 * adev->devno;
85cd7251	212
669a5db4 JG	213	pci_read_config_byte(pdev, pciD, &regD);
	214	pci_read_config_byte(pdev, pciU, &regU);
	215
6a40da02 A	216	/* DMA bits off */
	217	regD &= ~(0x20 << adev->devno);
	218	/* DMA control bits */
	219	regU &= ~(0x30 << shift);
	220	/* DMA timing bits */
	221	regU &= ~(0x05 << adev->devno);
85cd7251	222
6a40da02 A	223	if (adev->dma_mode >= XFER_UDMA_0) {
6a40da02 A	224	/* Merge thge timing value */
669a5db4	225	regU \|= udma_data[adev->dma_mode - XFER_UDMA_0] << shift;
6a40da02 A	226	/* Merge the control bits */
	227	regU \|= 1 << adev->devno; /* UDMA on */
	228	if (adev->dma_mode > 2) /* 15nS timing */
	229	regU \|= 4 << adev->devno;
	230	} else
669a5db4 JG	231	regD \|= mwdma_data[adev->dma_mode - XFER_MW_DMA_0] << shift;
	232
	233	regD \|= 0x20 << adev->devno;
	234
	235	pci_write_config_byte(pdev, pciU, regU);
	236	pci_write_config_byte(pdev, pciD, regD);
	237	}
	238
	239	/**
	240	* cmd648_dma_stop - DMA stop callback
	241	* @qc: Command in progress
	242	*
	243	* DMA has completed.
	244	*/
	245
	246	static void cmd648_bmdma_stop(struct ata_queued_cmd *qc)
	247	{
	248	struct ata_port *ap = qc->ap;
	249	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	250	u8 dma_intr;
6a40da02 A	251	int dma_mask = ap->port_no ? ARTTIM23_INTR_CH1 : CFR_INTR_CH0;
6a40da02 A	252	int dma_reg = ap->port_no ? ARTTIM2 : CFR;
85cd7251	253
669a5db4	254	ata_bmdma_stop(qc);
85cd7251	255
669a5db4 JG	256	pci_read_config_byte(pdev, dma_reg, &dma_intr);
	257	pci_write_config_byte(pdev, dma_reg, dma_intr \| dma_mask);
	258	}
85cd7251	259
669a5db4 JG	260	/**
	261	* cmd646r1_dma_stop - DMA stop callback
	262	* @qc: Command in progress
	263	*
	264	* Stub for now while investigating the r1 quirk in the old driver.
	265	*/
	266
	267	static void cmd646r1_bmdma_stop(struct ata_queued_cmd *qc)
	268	{
	269	ata_bmdma_stop(qc);
	270	}
85cd7251	271
669a5db4 JG	272	static struct scsi_host_template cmd64x_sht = {
	273	.module = THIS_MODULE,
	274	.name = DRV_NAME,
	275	.ioctl = ata_scsi_ioctl,
	276	.queuecommand = ata_scsi_queuecmd,
	277	.can_queue = ATA_DEF_QUEUE,
	278	.this_id = ATA_SHT_THIS_ID,
	279	.sg_tablesize = LIBATA_MAX_PRD,
669a5db4 JG	280	.cmd_per_lun = ATA_SHT_CMD_PER_LUN,
	281	.emulated = ATA_SHT_EMULATED,
	282	.use_clustering = ATA_SHT_USE_CLUSTERING,
	283	.proc_name = DRV_NAME,
	284	.dma_boundary = ATA_DMA_BOUNDARY,
	285	.slave_configure = ata_scsi_slave_config,
afdfe899	286	.slave_destroy = ata_scsi_slave_destroy,
669a5db4	287	.bios_param = ata_std_bios_param,
7f72a379 A	288	.resume = ata_scsi_device_resume,
7f72a379 A	289	.suspend = ata_scsi_device_suspend,
669a5db4 JG	290	};
	291
	292	static struct ata_port_operations cmd64x_port_ops = {
	293	.port_disable = ata_port_disable,
	294	.set_piomode = cmd64x_set_piomode,
	295	.set_dmamode = cmd64x_set_dmamode,
	296	.mode_filter = ata_pci_default_filter,
	297	.tf_load = ata_tf_load,
	298	.tf_read = ata_tf_read,
	299	.check_status = ata_check_status,
	300	.exec_command = ata_exec_command,
	301	.dev_select = ata_std_dev_select,
	302
	303	.freeze = ata_bmdma_freeze,
	304	.thaw = ata_bmdma_thaw,
	305	.error_handler = cmd64x_error_handler,
	306	.post_internal_cmd = ata_bmdma_post_internal_cmd,
	307
	308	.bmdma_setup = ata_bmdma_setup,
	309	.bmdma_start = ata_bmdma_start,
	310	.bmdma_stop = ata_bmdma_stop,
	311	.bmdma_status = ata_bmdma_status,
	312
	313	.qc_prep = ata_qc_prep,
	314	.qc_issue = ata_qc_issue_prot,
bda30288	315
669a5db4 JG	316	.data_xfer = ata_pio_data_xfer,
	317
	318	.irq_handler = ata_interrupt,
	319	.irq_clear = ata_bmdma_irq_clear,
85cd7251	320
669a5db4	321	.port_start = ata_port_start,
85cd7251	322	};
669a5db4 JG	323
	324	static struct ata_port_operations cmd646r1_port_ops = {
	325	.port_disable = ata_port_disable,
	326	.set_piomode = cmd64x_set_piomode,
	327	.set_dmamode = cmd64x_set_dmamode,
	328	.mode_filter = ata_pci_default_filter,
	329	.tf_load = ata_tf_load,
	330	.tf_read = ata_tf_read,
	331	.check_status = ata_check_status,
	332	.exec_command = ata_exec_command,
	333	.dev_select = ata_std_dev_select,
	334
	335	.freeze = ata_bmdma_freeze,
	336	.thaw = ata_bmdma_thaw,
	337	.error_handler = cmd64x_error_handler,
	338	.post_internal_cmd = ata_bmdma_post_internal_cmd,
	339
	340	.bmdma_setup = ata_bmdma_setup,
	341	.bmdma_start = ata_bmdma_start,
	342	.bmdma_stop = cmd646r1_bmdma_stop,
	343	.bmdma_status = ata_bmdma_status,
	344
	345	.qc_prep = ata_qc_prep,
	346	.qc_issue = ata_qc_issue_prot,
bda30288	347
669a5db4 JG	348	.data_xfer = ata_pio_data_xfer,
	349
	350	.irq_handler = ata_interrupt,
	351	.irq_clear = ata_bmdma_irq_clear,
85cd7251	352
669a5db4	353	.port_start = ata_port_start,
85cd7251	354	};
669a5db4 JG	355
	356	static struct ata_port_operations cmd648_port_ops = {
	357	.port_disable = ata_port_disable,
	358	.set_piomode = cmd64x_set_piomode,
	359	.set_dmamode = cmd64x_set_dmamode,
	360	.mode_filter = ata_pci_default_filter,
	361	.tf_load = ata_tf_load,
	362	.tf_read = ata_tf_read,
	363	.check_status = ata_check_status,
	364	.exec_command = ata_exec_command,
	365	.dev_select = ata_std_dev_select,
	366
	367	.freeze = ata_bmdma_freeze,
	368	.thaw = ata_bmdma_thaw,
	369	.error_handler = cmd648_error_handler,
	370	.post_internal_cmd = ata_bmdma_post_internal_cmd,
	371
	372	.bmdma_setup = ata_bmdma_setup,
	373	.bmdma_start = ata_bmdma_start,
	374	.bmdma_stop = cmd648_bmdma_stop,
	375	.bmdma_status = ata_bmdma_status,
	376
	377	.qc_prep = ata_qc_prep,
	378	.qc_issue = ata_qc_issue_prot,
bda30288	379
669a5db4 JG	380	.data_xfer = ata_pio_data_xfer,
	381
	382	.irq_handler = ata_interrupt,
	383	.irq_clear = ata_bmdma_irq_clear,
85cd7251	384
669a5db4	385	.port_start = ata_port_start,
85cd7251 JG	386	};
85cd7251 JG	387
669a5db4 JG	388	static int cmd64x_init_one(struct pci_dev pdev, const struct pci_device_id id)
	389	{
	390	u32 class_rev;
85cd7251	391
669a5db4 JG	392	static struct ata_port_info cmd_info[6] = {
	393	{ /* CMD 643 - no UDMA */
	394	.sht = &cmd64x_sht,
	395	.flags = ATA_FLAG_SLAVE_POSS \| ATA_FLAG_SRST,
	396	.pio_mask = 0x1f,
	397	.mwdma_mask = 0x07,
	398	.port_ops = &cmd64x_port_ops
	399	},
	400	{ /* CMD 646 with broken UDMA */
	401	.sht = &cmd64x_sht,
	402	.flags = ATA_FLAG_SLAVE_POSS \| ATA_FLAG_SRST,
	403	.pio_mask = 0x1f,
	404	.mwdma_mask = 0x07,
	405	.port_ops = &cmd64x_port_ops
	406	},
	407	{ /* CMD 646 with working UDMA */
	408	.sht = &cmd64x_sht,
	409	.flags = ATA_FLAG_SLAVE_POSS \| ATA_FLAG_SRST,
	410	.pio_mask = 0x1f,
	411	.mwdma_mask = 0x07,
	412	.udma_mask = ATA_UDMA1,
	413	.port_ops = &cmd64x_port_ops
	414	},
	415	{ /* CMD 646 rev 1 */
	416	.sht = &cmd64x_sht,
	417	.flags = ATA_FLAG_SLAVE_POSS \| ATA_FLAG_SRST,
	418	.pio_mask = 0x1f,
	419	.mwdma_mask = 0x07,
	420	.port_ops = &cmd646r1_port_ops
	421	},
	422	{ /* CMD 648 */
	423	.sht = &cmd64x_sht,
	424	.flags = ATA_FLAG_SLAVE_POSS \| ATA_FLAG_SRST,
	425	.pio_mask = 0x1f,
	426	.mwdma_mask = 0x07,
	427	.udma_mask = ATA_UDMA2,
	428	.port_ops = &cmd648_port_ops
	429	},
	430	{ /* CMD 649 */
	431	.sht = &cmd64x_sht,
	432	.flags = ATA_FLAG_SLAVE_POSS \| ATA_FLAG_SRST,
	433	.pio_mask = 0x1f,
	434	.mwdma_mask = 0x07,
	435	.udma_mask = ATA_UDMA3,
	436	.port_ops = &cmd648_port_ops
	437	}
	438	};
	439	static struct ata_port_info port_info[2], info;
	440	u8 mrdmode;
85cd7251	441
669a5db4	442	info = &cmd_info[id->driver_data];
85cd7251	443
669a5db4 JG	444	pci_read_config_dword(pdev, PCI_CLASS_REVISION, &class_rev);
669a5db4 JG	445	class_rev &= 0xFF;
85cd7251	446
669a5db4 JG	447	if (id->driver_data == 0) /* 643 */
669a5db4 JG	448	ata_pci_clear_simplex(pdev);
85cd7251	449
669a5db4 JG	450	if (pdev->device == PCI_DEVICE_ID_CMD_646) {
	451	/* Does UDMA work ? */
	452	if (class_rev > 4)
	453	info = &cmd_info[2];
	454	/* Early rev with other problems ? */
	455	else if (class_rev == 1)
	456	info = &cmd_info[3];
	457	}
	458
	459	pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 64);
	460	pci_read_config_byte(pdev, MRDMODE, &mrdmode);
	461	mrdmode &= ~ 0x30; /* IRQ set up */
	462	mrdmode \|= 0x02; /* Memory read line enable */
	463	pci_write_config_byte(pdev, MRDMODE, mrdmode);
85cd7251	464
669a5db4	465	/* Force PIO 0 here.. */
85cd7251	466
669a5db4 JG	467	/* PPC specific fixup copied from old driver */
	468	#ifdef CONFIG_PPC
	469	pci_write_config_byte(pdev, UDIDETCR0, 0xF0);
	470	#endif
85cd7251	471
669a5db4 JG	472	port_info[0] = port_info[1] = info;
	473	return ata_pci_init_one(pdev, port_info, 2);
	474	}
	475
7f72a379 A	476	static int cmd64x_reinit_one(struct pci_dev *pdev)
	477	{
	478	u8 mrdmode;
	479	pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 64);
	480	pci_read_config_byte(pdev, MRDMODE, &mrdmode);
	481	mrdmode &= ~ 0x30; /* IRQ set up */
	482	mrdmode \|= 0x02; /* Memory read line enable */
	483	pci_write_config_byte(pdev, MRDMODE, mrdmode);
	484	#ifdef CONFIG_PPC
	485	pci_write_config_byte(pdev, UDIDETCR0, 0xF0);
	486	#endif
	487	return ata_pci_device_resume(pdev);
	488	}
	489
2d2744fc JG	490	static const struct pci_device_id cmd64x[] = {
	491	{ PCI_VDEVICE(CMD, PCI_DEVICE_ID_CMD_643), 0 },
	492	{ PCI_VDEVICE(CMD, PCI_DEVICE_ID_CMD_646), 1 },
	493	{ PCI_VDEVICE(CMD, PCI_DEVICE_ID_CMD_648), 4 },
	494	{ PCI_VDEVICE(CMD, PCI_DEVICE_ID_CMD_649), 5 },
	495
	496	{ },
669a5db4 JG	497	};
	498
	499	static struct pci_driver cmd64x_pci_driver = {
2d2744fc	500	.name = DRV_NAME,
669a5db4 JG	501	.id_table = cmd64x,
669a5db4 JG	502	.probe = cmd64x_init_one,
7f72a379 A	503	.remove = ata_pci_remove_one,
	504	.suspend = ata_pci_device_suspend,
	505	.resume = cmd64x_reinit_one,
669a5db4 JG	506	};
	507
	508	static int __init cmd64x_init(void)
	509	{
	510	return pci_register_driver(&cmd64x_pci_driver);
	511	}
	512
669a5db4 JG	513	static void __exit cmd64x_exit(void)
	514	{
	515	pci_unregister_driver(&cmd64x_pci_driver);
	516	}
	517
669a5db4 JG	518	MODULE_AUTHOR("Alan Cox");
	519	MODULE_DESCRIPTION("low-level driver for CMD64x series PATA controllers");
	520	MODULE_LICENSE("GPL");
	521	MODULE_DEVICE_TABLE(pci, cmd64x);
	522	MODULE_VERSION(DRV_VERSION);
	523
	524	module_init(cmd64x_init);
	525	module_exit(cmd64x_exit);