[deliverable/linux.git] / drivers / ata / pata_cs5530.c

/*
 * pata-cs5530.c 	- CS5530 PATA for new ATA layer
 *			  (C) 2005 Red Hat Inc
 *			  Alan Cox <alan@redhat.com>
 *
 * based upon cs5530.c by Mark Lord.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 *
 * Loosely based on the piix & svwks drivers.
 *
 * Documentation:
 *	Available from AMD web site.
 */

#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/pci.h>
#include <linux/init.h>
#include <linux/blkdev.h>
#include <linux/delay.h>
#include <scsi/scsi_host.h>
#include <linux/libata.h>
#include <linux/dmi.h>

#define DRV_NAME	"pata_cs5530"
#define DRV_VERSION	"0.7.4"

static void __iomem *cs5530_port_base(struct ata_port *ap)
{
	unsigned long bmdma = (unsigned long)ap->ioaddr.bmdma_addr;

	return (void __iomem *)((bmdma & ~0x0F) + 0x20 + 0x10 * ap->port_no);
}

/**
 *	cs5530_set_piomode		-	PIO setup
 *	@ap: ATA interface
 *	@adev: device on the interface
 *
 *	Set our PIO requirements. This is fairly simple on the CS5530
 *	chips.
 */

static void cs5530_set_piomode(struct ata_port *ap, struct ata_device *adev)
{
	static const unsigned int cs5530_pio_timings[2][5] = {
		{0x00009172, 0x00012171, 0x00020080, 0x00032010, 0x00040010},
		{0xd1329172, 0x71212171, 0x30200080, 0x20102010, 0x00100010}
	};
	void __iomem *base = cs5530_port_base(ap);
	u32 tuning;
	int format;

	/* Find out which table to use */
	tuning = ioread32(base + 0x04);
	format = (tuning & 0x80000000UL) ? 1 : 0;

	/* Now load the right timing register */
	if (adev->devno)
		base += 0x08;

	iowrite32(cs5530_pio_timings[format][adev->pio_mode - XFER_PIO_0], base);
}

/**
 *	cs5530_set_dmamode		-	DMA timing setup
 *	@ap: ATA interface
 *	@adev: Device being configured
 *
 *	We cannot mix MWDMA and UDMA without reloading timings each switch
 *	master to slave. We track the last DMA setup in order to minimise
 *	reloads.
 */

static void cs5530_set_dmamode(struct ata_port *ap, struct ata_device *adev)
{
	void __iomem *base = cs5530_port_base(ap);
	u32 tuning, timing = 0;
	u8 reg;

	/* Find out which table to use */
	tuning = ioread32(base + 0x04);

	switch(adev->dma_mode) {
		case XFER_UDMA_0:
			timing  = 0x00921250;break;
		case XFER_UDMA_1:
			timing  = 0x00911140;break;
		case XFER_UDMA_2:
			timing  = 0x00911030;break;
		case XFER_MW_DMA_0:
			timing  = 0x00077771;break;
		case XFER_MW_DMA_1:
			timing  = 0x00012121;break;
		case XFER_MW_DMA_2:
			timing  = 0x00002020;break;
		default:
			BUG();
	}
	/* Merge in the PIO format bit */
	timing |= (tuning & 0x80000000UL);
	if (adev->devno == 0) /* Master */
		iowrite32(timing, base + 0x04);
	else {
		if (timing & 0x00100000)
			tuning |= 0x00100000;	/* UDMA for both */
		else
			tuning &= ~0x00100000;	/* MWDMA for both */
		iowrite32(tuning, base + 0x04);
		iowrite32(timing, base + 0x0C);
	}

	/* Set the DMA capable bit in the BMDMA area */
	reg = ioread8(ap->ioaddr.bmdma_addr + ATA_DMA_STATUS);
	reg |= (1 << (5 + adev->devno));
	iowrite8(reg, ap->ioaddr.bmdma_addr + ATA_DMA_STATUS);

	/* Remember the last DMA setup we did */

	ap->private_data = adev;
}

/**
 *	cs5530_qc_issue_prot	-	command issue
 *	@qc: command pending
 *
 *	Called when the libata layer is about to issue a command. We wrap
 *	this interface so that we can load the correct ATA timings if
 *	necessary.  Specifically we have a problem that there is only
 *	one MWDMA/UDMA bit.
 */

static unsigned int cs5530_qc_issue_prot(struct ata_queued_cmd *qc)
{
	struct ata_port *ap = qc->ap;
	struct ata_device *adev = qc->dev;
	struct ata_device *prev = ap->private_data;

	/* See if the DMA settings could be wrong */
	if (adev->dma_mode != 0 && adev != prev && prev != NULL) {
		/* Maybe, but do the channels match MWDMA/UDMA ? */
		if ((adev->dma_mode >= XFER_UDMA_0 && prev->dma_mode < XFER_UDMA_0) ||
		    (adev->dma_mode < XFER_UDMA_0 && prev->dma_mode >= XFER_UDMA_0))
		    	/* Switch the mode bits */
		    	cs5530_set_dmamode(ap, adev);
	}

	return ata_qc_issue_prot(qc);
}

static struct scsi_host_template cs5530_sht = {
	ATA_BMDMA_SHT(DRV_NAME),
	.sg_tablesize	= LIBATA_DUMB_MAX_PRD,
};

static struct ata_port_operations cs5530_port_ops = {
	.inherits	= &ata_bmdma_port_ops,

	.qc_prep 	= ata_dumb_qc_prep,
	.qc_issue	= cs5530_qc_issue_prot,

	.cable_detect	= ata_cable_40wire,
	.set_piomode	= cs5530_set_piomode,
	.set_dmamode	= cs5530_set_dmamode,
};

static const struct dmi_system_id palmax_dmi_table[] = {
	{
		.ident = "Palmax PD1100",
		.matches = {
			DMI_MATCH(DMI_SYS_VENDOR, "Cyrix"),
			DMI_MATCH(DMI_PRODUCT_NAME, "Caddis"),
		},
	},
	{ }
};

static int cs5530_is_palmax(void)
{
	if (dmi_check_system(palmax_dmi_table)) {
		printk(KERN_INFO "Palmax PD1100: Disabling DMA on docking port.\n");
		return 1;
	}
	return 0;
}


/**
 *	cs5530_init_chip	-	Chipset init
 *
 *	Perform the chip initialisation work that is shared between both
 *	setup and resume paths
 */

static int cs5530_init_chip(void)
{
	struct pci_dev *master_0 = NULL, *cs5530_0 = NULL, *dev = NULL;

	while ((dev = pci_get_device(PCI_VENDOR_ID_CYRIX, PCI_ANY_ID, dev)) != NULL) {
		switch (dev->device) {
			case PCI_DEVICE_ID_CYRIX_PCI_MASTER:
				master_0 = pci_dev_get(dev);
				break;
			case PCI_DEVICE_ID_CYRIX_5530_LEGACY:
				cs5530_0 = pci_dev_get(dev);
				break;
		}
	}
	if (!master_0) {
		printk(KERN_ERR DRV_NAME ": unable to locate PCI MASTER function\n");
		goto fail_put;
	}
	if (!cs5530_0) {
		printk(KERN_ERR DRV_NAME ": unable to locate CS5530 LEGACY function\n");
		goto fail_put;
	}

	pci_set_master(cs5530_0);
	pci_try_set_mwi(cs5530_0);

	/*
	 * Set PCI CacheLineSize to 16-bytes:
	 * --> Write 0x04 into 8-bit PCI CACHELINESIZE reg of function 0 of the cs5530
	 *
	 * Note: This value is constant because the 5530 is only a Geode companion
	 */

	pci_write_config_byte(cs5530_0, PCI_CACHE_LINE_SIZE, 0x04);

	/*
	 * Disable trapping of UDMA register accesses (Win98 hack):
	 * --> Write 0x5006 into 16-bit reg at offset 0xd0 of function 0 of the cs5530
	 */

	pci_write_config_word(cs5530_0, 0xd0, 0x5006);

	/*
	 * Bit-1 at 0x40 enables MemoryWriteAndInvalidate on internal X-bus:
	 * The other settings are what is necessary to get the register
	 * into a sane state for IDE DMA operation.
	 */

	pci_write_config_byte(master_0, 0x40, 0x1e);

	/*
	 * Set max PCI burst size (16-bytes seems to work best):
	 *	   16bytes: set bit-1 at 0x41 (reg value of 0x16)
	 *	all others: clear bit-1 at 0x41, and do:
	 *	  128bytes: OR 0x00 at 0x41
	 *	  256bytes: OR 0x04 at 0x41
	 *	  512bytes: OR 0x08 at 0x41
	 *	 1024bytes: OR 0x0c at 0x41
	 */

	pci_write_config_byte(master_0, 0x41, 0x14);

	/*
	 * These settings are necessary to get the chip
	 * into a sane state for IDE DMA operation.
	 */

	pci_write_config_byte(master_0, 0x42, 0x00);
	pci_write_config_byte(master_0, 0x43, 0xc1);

	pci_dev_put(master_0);
	pci_dev_put(cs5530_0);
	return 0;
fail_put:
	if (master_0)
		pci_dev_put(master_0);
	if (cs5530_0)
		pci_dev_put(cs5530_0);
	return -ENODEV;
}

/**
 *	cs5530_init_one		-	Initialise a CS5530
 *	@dev: PCI device
 *	@id: Entry in match table
 *
 *	Install a driver for the newly found CS5530 companion chip. Most of
 *	this is just housekeeping. We have to set the chip up correctly and
 *	turn off various bits of emulation magic.
 */

static int cs5530_init_one(struct pci_dev *pdev, const struct pci_device_id *id)
{
	static const struct ata_port_info info = {
		.flags = ATA_FLAG_SLAVE_POSS,
		.pio_mask = 0x1f,
		.mwdma_mask = 0x07,
		.udma_mask = 0x07,
		.port_ops = &cs5530_port_ops
	};
	/* The docking connector doesn't do UDMA, and it seems not MWDMA */
	static const struct ata_port_info info_palmax_secondary = {
		.flags = ATA_FLAG_SLAVE_POSS,
		.pio_mask = 0x1f,
		.port_ops = &cs5530_port_ops
	};
	const struct ata_port_info *ppi[] = { &info, NULL };
	int rc;

	rc = pcim_enable_device(pdev);
	if (rc)
		return rc;

	/* Chip initialisation */
	if (cs5530_init_chip())
		return -ENODEV;

	if (cs5530_is_palmax())
		ppi[1] = &info_palmax_secondary;

	/* Now kick off ATA set up */
	return ata_pci_init_one(pdev, ppi, &cs5530_sht, NULL);
}

#ifdef CONFIG_PM
static int cs5530_reinit_one(struct pci_dev *pdev)
{
	struct ata_host *host = dev_get_drvdata(&pdev->dev);
	int rc;

	rc = ata_pci_device_do_resume(pdev);
	if (rc)
		return rc;

	/* If we fail on resume we are doomed */
	if (cs5530_init_chip())
		return -EIO;

	ata_host_resume(host);
	return 0;
}
#endif /* CONFIG_PM */

static const struct pci_device_id cs5530[] = {
	{ PCI_VDEVICE(CYRIX, PCI_DEVICE_ID_CYRIX_5530_IDE), },

	{ },
};

static struct pci_driver cs5530_pci_driver = {
	.name 		= DRV_NAME,
	.id_table	= cs5530,
	.probe 		= cs5530_init_one,
	.remove		= ata_pci_remove_one,
#ifdef CONFIG_PM
	.suspend	= ata_pci_device_suspend,
	.resume		= cs5530_reinit_one,
#endif
};

static int __init cs5530_init(void)
{
	return pci_register_driver(&cs5530_pci_driver);
}

static void __exit cs5530_exit(void)
{
	pci_unregister_driver(&cs5530_pci_driver);
}

MODULE_AUTHOR("Alan Cox");
MODULE_DESCRIPTION("low-level driver for the Cyrix/NS/AMD 5530");
MODULE_LICENSE("GPL");
MODULE_DEVICE_TABLE(pci, cs5530);
MODULE_VERSION(DRV_VERSION);

module_init(cs5530_init);
module_exit(cs5530_exit);
Commit	Line	Data
669a5db4 JG	1	/*
	2	* pata-cs5530.c - CS5530 PATA for new ATA layer
	3	* (C) 2005 Red Hat Inc
	4	* Alan Cox <alan@redhat.com>
	5	*
	6	* based upon cs5530.c by Mark Lord.
	7	*
	8	* This program is free software; you can redistribute it and/or modify
	9	* it under the terms of the GNU General Public License version 2 as
	10	* published by the Free Software Foundation.
	11	*
	12	* This program is distributed in the hope that it will be useful,
	13	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	15	* GNU General Public License for more details.
	16	*
	17	* You should have received a copy of the GNU General Public License
	18	* along with this program; if not, write to the Free Software
	19	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	20	*
	21	* Loosely based on the piix & svwks drivers.
	22	*
	23	* Documentation:
	24	* Available from AMD web site.
	25	*/
	26
	27	#include <linux/kernel.h>
	28	#include <linux/module.h>
	29	#include <linux/pci.h>
	30	#include <linux/init.h>
	31	#include <linux/blkdev.h>
	32	#include <linux/delay.h>
	33	#include <scsi/scsi_host.h>
	34	#include <linux/libata.h>
	35	#include <linux/dmi.h>
	36
	37	#define DRV_NAME "pata_cs5530"
2a3103ce	38	#define DRV_VERSION "0.7.4"
669a5db4	39
0d5ff566 TH	40	static void __iomem cs5530_port_base(struct ata_port ap)
	41	{
	42	unsigned long bmdma = (unsigned long)ap->ioaddr.bmdma_addr;
	43
	44	return (void __iomem )((bmdma & ~0x0F) + 0x20 + 0x10 ap->port_no);
	45	}
	46
669a5db4 JG	47	/**
	48	* cs5530_set_piomode - PIO setup
	49	* @ap: ATA interface
	50	* @adev: device on the interface
	51	*
	52	* Set our PIO requirements. This is fairly simple on the CS5530
	53	* chips.
	54	*/
	55
	56	static void cs5530_set_piomode(struct ata_port ap, struct ata_device adev)
	57	{
	58	static const unsigned int cs5530_pio_timings[2][5] = {
	59	{0x00009172, 0x00012171, 0x00020080, 0x00032010, 0x00040010},
	60	{0xd1329172, 0x71212171, 0x30200080, 0x20102010, 0x00100010}
	61	};
0d5ff566	62	void __iomem *base = cs5530_port_base(ap);
669a5db4 JG	63	u32 tuning;
	64	int format;
	65
	66	/* Find out which table to use */
0d5ff566	67	tuning = ioread32(base + 0x04);
669a5db4 JG	68	format = (tuning & 0x80000000UL) ? 1 : 0;
	69
	70	/* Now load the right timing register */
	71	if (adev->devno)
	72	base += 0x08;
	73
0d5ff566	74	iowrite32(cs5530_pio_timings[format][adev->pio_mode - XFER_PIO_0], base);
669a5db4 JG	75	}
	76
	77	/**
	78	* cs5530_set_dmamode - DMA timing setup
	79	* @ap: ATA interface
	80	* @adev: Device being configured
	81	*
	82	* We cannot mix MWDMA and UDMA without reloading timings each switch
	83	* master to slave. We track the last DMA setup in order to minimise
	84	* reloads.
	85	*/
	86
	87	static void cs5530_set_dmamode(struct ata_port ap, struct ata_device adev)
	88	{
0d5ff566	89	void __iomem *base = cs5530_port_base(ap);
669a5db4 JG	90	u32 tuning, timing = 0;
	91	u8 reg;
	92
	93	/* Find out which table to use */
0d5ff566	94	tuning = ioread32(base + 0x04);
669a5db4 JG	95
	96	switch(adev->dma_mode) {
	97	case XFER_UDMA_0:
	98	timing = 0x00921250;break;
	99	case XFER_UDMA_1:
	100	timing = 0x00911140;break;
	101	case XFER_UDMA_2:
	102	timing = 0x00911030;break;
	103	case XFER_MW_DMA_0:
	104	timing = 0x00077771;break;
	105	case XFER_MW_DMA_1:
	106	timing = 0x00012121;break;
	107	case XFER_MW_DMA_2:
	108	timing = 0x00002020;break;
	109	default:
	110	BUG();
	111	}
	112	/* Merge in the PIO format bit */
	113	timing \|= (tuning & 0x80000000UL);
	114	if (adev->devno == 0) /* Master */
0d5ff566	115	iowrite32(timing, base + 0x04);
669a5db4 JG	116	else {
	117	if (timing & 0x00100000)
	118	tuning \|= 0x00100000; /* UDMA for both */
	119	else
	120	tuning &= ~0x00100000; /* MWDMA for both */
0d5ff566 TH	121	iowrite32(tuning, base + 0x04);
0d5ff566 TH	122	iowrite32(timing, base + 0x0C);
669a5db4 JG	123	}
	124
	125	/* Set the DMA capable bit in the BMDMA area */
0d5ff566	126	reg = ioread8(ap->ioaddr.bmdma_addr + ATA_DMA_STATUS);
669a5db4	127	reg \|= (1 << (5 + adev->devno));
0d5ff566	128	iowrite8(reg, ap->ioaddr.bmdma_addr + ATA_DMA_STATUS);
669a5db4 JG	129
	130	/* Remember the last DMA setup we did */
	131
	132	ap->private_data = adev;
	133	}
	134
	135	/**
	136	* cs5530_qc_issue_prot - command issue
	137	* @qc: command pending
	138	*
	139	* Called when the libata layer is about to issue a command. We wrap
	140	* this interface so that we can load the correct ATA timings if
3a4fa0a2	141	* necessary. Specifically we have a problem that there is only
669a5db4 JG	142	* one MWDMA/UDMA bit.
	143	*/
	144
	145	static unsigned int cs5530_qc_issue_prot(struct ata_queued_cmd *qc)
	146	{
	147	struct ata_port *ap = qc->ap;
	148	struct ata_device *adev = qc->dev;
	149	struct ata_device *prev = ap->private_data;
	150
	151	/* See if the DMA settings could be wrong */
	152	if (adev->dma_mode != 0 && adev != prev && prev != NULL) {
	153	/* Maybe, but do the channels match MWDMA/UDMA ? */
	154	if ((adev->dma_mode >= XFER_UDMA_0 && prev->dma_mode < XFER_UDMA_0) \|\|
	155	(adev->dma_mode < XFER_UDMA_0 && prev->dma_mode >= XFER_UDMA_0))
	156	/* Switch the mode bits */
	157	cs5530_set_dmamode(ap, adev);
	158	}
	159
	160	return ata_qc_issue_prot(qc);
	161	}
	162
669a5db4	163	static struct scsi_host_template cs5530_sht = {
68d1d07b TH	164	ATA_BMDMA_SHT(DRV_NAME),
68d1d07b TH	165	.sg_tablesize = LIBATA_DUMB_MAX_PRD,
669a5db4 JG	166	};
	167
	168	static struct ata_port_operations cs5530_port_ops = {
029cfd6b	169	.inherits = &ata_bmdma_port_ops,
669a5db4	170
d26fc955	171	.qc_prep = ata_dumb_qc_prep,
669a5db4	172	.qc_issue = cs5530_qc_issue_prot,
bda30288	173
029cfd6b TH	174	.cable_detect = ata_cable_40wire,
	175	.set_piomode = cs5530_set_piomode,
	176	.set_dmamode = cs5530_set_dmamode,
669a5db4 JG	177	};
669a5db4 JG	178
1855256c	179	static const struct dmi_system_id palmax_dmi_table[] = {
669a5db4 JG	180	{
	181	.ident = "Palmax PD1100",
	182	.matches = {
	183	DMI_MATCH(DMI_SYS_VENDOR, "Cyrix"),
	184	DMI_MATCH(DMI_PRODUCT_NAME, "Caddis"),
	185	},
	186	},
	187	{ }
	188	};
	189
	190	static int cs5530_is_palmax(void)
	191	{
	192	if (dmi_check_system(palmax_dmi_table)) {
	193	printk(KERN_INFO "Palmax PD1100: Disabling DMA on docking port.\n");
	194	return 1;
	195	}
	196	return 0;
	197	}
	198
f7e37ba8	199
669a5db4	200	/**
f7e37ba8	201	* cs5530_init_chip - Chipset init
669a5db4	202	*
f7e37ba8 A	203	* Perform the chip initialisation work that is shared between both
f7e37ba8 A	204	* setup and resume paths
669a5db4	205	*/
f20b16ff	206
f7e37ba8	207	static int cs5530_init_chip(void)
669a5db4	208	{
f7e37ba8	209	struct pci_dev master_0 = NULL, cs5530_0 = NULL, *dev = NULL;
669a5db4	210
669a5db4 JG	211	while ((dev = pci_get_device(PCI_VENDOR_ID_CYRIX, PCI_ANY_ID, dev)) != NULL) {
	212	switch (dev->device) {
	213	case PCI_DEVICE_ID_CYRIX_PCI_MASTER:
	214	master_0 = pci_dev_get(dev);
	215	break;
	216	case PCI_DEVICE_ID_CYRIX_5530_LEGACY:
	217	cs5530_0 = pci_dev_get(dev);
	218	break;
	219	}
	220	}
	221	if (!master_0) {
	222	printk(KERN_ERR DRV_NAME ": unable to locate PCI MASTER function\n");
	223	goto fail_put;
	224	}
	225	if (!cs5530_0) {
	226	printk(KERN_ERR DRV_NAME ": unable to locate CS5530 LEGACY function\n");
	227	goto fail_put;
	228	}
	229
	230	pci_set_master(cs5530_0);
694625c0	231	pci_try_set_mwi(cs5530_0);
669a5db4 JG	232
	233	/*
	234	* Set PCI CacheLineSize to 16-bytes:
	235	* --> Write 0x04 into 8-bit PCI CACHELINESIZE reg of function 0 of the cs5530
	236	*
	237	* Note: This value is constant because the 5530 is only a Geode companion
	238	*/
	239
	240	pci_write_config_byte(cs5530_0, PCI_CACHE_LINE_SIZE, 0x04);
	241
	242	/*
	243	* Disable trapping of UDMA register accesses (Win98 hack):
	244	* --> Write 0x5006 into 16-bit reg at offset 0xd0 of function 0 of the cs5530
	245	*/
	246
	247	pci_write_config_word(cs5530_0, 0xd0, 0x5006);
	248
	249	/*
	250	* Bit-1 at 0x40 enables MemoryWriteAndInvalidate on internal X-bus:
	251	* The other settings are what is necessary to get the register
	252	* into a sane state for IDE DMA operation.
	253	*/
	254
	255	pci_write_config_byte(master_0, 0x40, 0x1e);
	256
	257	/*
	258	* Set max PCI burst size (16-bytes seems to work best):
	259	* 16bytes: set bit-1 at 0x41 (reg value of 0x16)
	260	* all others: clear bit-1 at 0x41, and do:
	261	* 128bytes: OR 0x00 at 0x41
	262	* 256bytes: OR 0x04 at 0x41
	263	* 512bytes: OR 0x08 at 0x41
	264	* 1024bytes: OR 0x0c at 0x41
	265	*/
	266
	267	pci_write_config_byte(master_0, 0x41, 0x14);
	268
	269	/*
	270	* These settings are necessary to get the chip
	271	* into a sane state for IDE DMA operation.
	272	*/
	273
	274	pci_write_config_byte(master_0, 0x42, 0x00);
	275	pci_write_config_byte(master_0, 0x43, 0xc1);
	276
	277	pci_dev_put(master_0);
	278	pci_dev_put(cs5530_0);
f7e37ba8	279	return 0;
669a5db4 JG	280	fail_put:
	281	if (master_0)
	282	pci_dev_put(master_0);
	283	if (cs5530_0)
	284	pci_dev_put(cs5530_0);
	285	return -ENODEV;
	286	}
	287
f7e37ba8 A	288	/**
	289	* cs5530_init_one - Initialise a CS5530
	290	* @dev: PCI device
	291	* @id: Entry in match table
	292	*
	293	* Install a driver for the newly found CS5530 companion chip. Most of
	294	* this is just housekeeping. We have to set the chip up correctly and
	295	* turn off various bits of emulation magic.
	296	*/
	297
	298	static int cs5530_init_one(struct pci_dev pdev, const struct pci_device_id id)
	299	{
1626aeb8	300	static const struct ata_port_info info = {
1d2808fd	301	.flags = ATA_FLAG_SLAVE_POSS,
f7e37ba8 A	302	.pio_mask = 0x1f,
	303	.mwdma_mask = 0x07,
	304	.udma_mask = 0x07,
	305	.port_ops = &cs5530_port_ops
	306	};
	307	/* The docking connector doesn't do UDMA, and it seems not MWDMA */
1626aeb8	308	static const struct ata_port_info info_palmax_secondary = {
1d2808fd	309	.flags = ATA_FLAG_SLAVE_POSS,
f7e37ba8 A	310	.pio_mask = 0x1f,
	311	.port_ops = &cs5530_port_ops
	312	};
1626aeb8	313	const struct ata_port_info *ppi[] = { &info, NULL };
f08048e9 TH	314	int rc;
	315
	316	rc = pcim_enable_device(pdev);
	317	if (rc)
	318	return rc;
f20b16ff	319
f7e37ba8 A	320	/* Chip initialisation */
	321	if (cs5530_init_chip())
	322	return -ENODEV;
f20b16ff	323
f7e37ba8	324	if (cs5530_is_palmax())
1626aeb8	325	ppi[1] = &info_palmax_secondary;
f7e37ba8 A	326
f7e37ba8 A	327	/* Now kick off ATA set up */
887125e3	328	return ata_pci_init_one(pdev, ppi, &cs5530_sht, NULL);
f7e37ba8 A	329	}
f7e37ba8 A	330
438ac6d5	331	#ifdef CONFIG_PM
f7e37ba8 A	332	static int cs5530_reinit_one(struct pci_dev *pdev)
f7e37ba8 A	333	{
f08048e9 TH	334	struct ata_host *host = dev_get_drvdata(&pdev->dev);
	335	int rc;
	336
	337	rc = ata_pci_device_do_resume(pdev);
	338	if (rc)
	339	return rc;
	340
f7e37ba8	341	/* If we fail on resume we are doomed */
0153260a	342	if (cs5530_init_chip())
f08048e9 TH	343	return -EIO;
	344
	345	ata_host_resume(host);
	346	return 0;
f7e37ba8	347	}
438ac6d5	348	#endif /* CONFIG_PM */
f20b16ff	349
2d2744fc JG	350	static const struct pci_device_id cs5530[] = {
	351	{ PCI_VDEVICE(CYRIX, PCI_DEVICE_ID_CYRIX_5530_IDE), },
	352
	353	{ },
669a5db4 JG	354	};
	355
	356	static struct pci_driver cs5530_pci_driver = {
2d2744fc	357	.name = DRV_NAME,
669a5db4 JG	358	.id_table = cs5530,
669a5db4 JG	359	.probe = cs5530_init_one,
f7e37ba8	360	.remove = ata_pci_remove_one,
438ac6d5	361	#ifdef CONFIG_PM
f7e37ba8 A	362	.suspend = ata_pci_device_suspend,
f7e37ba8 A	363	.resume = cs5530_reinit_one,
438ac6d5	364	#endif
669a5db4 JG	365	};
	366
	367	static int __init cs5530_init(void)
	368	{
	369	return pci_register_driver(&cs5530_pci_driver);
	370	}
	371
669a5db4 JG	372	static void __exit cs5530_exit(void)
	373	{
	374	pci_unregister_driver(&cs5530_pci_driver);
	375	}
	376
669a5db4 JG	377	MODULE_AUTHOR("Alan Cox");
	378	MODULE_DESCRIPTION("low-level driver for the Cyrix/NS/AMD 5530");
	379	MODULE_LICENSE("GPL");
	380	MODULE_DEVICE_TABLE(pci, cs5530);
	381	MODULE_VERSION(DRV_VERSION);
	382
	383	module_init(cs5530_init);
	384	module_exit(cs5530_exit);