Commit | Line | Data |
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669a5db4 JG |
1 | /* |
2 | * Libata driver for the highpoint 37x and 30x UDMA66 ATA controllers. | |
3 | * | |
4 | * This driver is heavily based upon: | |
5 | * | |
6 | * linux/drivers/ide/pci/hpt366.c Version 0.36 April 25, 2003 | |
7 | * | |
8 | * Copyright (C) 1999-2003 Andre Hedrick <andre@linux-ide.org> | |
9 | * Portions Copyright (C) 2001 Sun Microsystems, Inc. | |
10 | * Portions Copyright (C) 2003 Red Hat Inc | |
8e834c2e | 11 | * Portions Copyright (C) 2005-2010 MontaVista Software, Inc. |
669a5db4 JG |
12 | * |
13 | * TODO | |
d44a65f7 | 14 | * Look into engine reset on timeout errors. Should not be required. |
669a5db4 JG |
15 | */ |
16 | ||
8d7b1c70 JP |
17 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
18 | ||
669a5db4 JG |
19 | #include <linux/kernel.h> |
20 | #include <linux/module.h> | |
21 | #include <linux/pci.h> | |
669a5db4 JG |
22 | #include <linux/blkdev.h> |
23 | #include <linux/delay.h> | |
24 | #include <scsi/scsi_host.h> | |
25 | #include <linux/libata.h> | |
26 | ||
27 | #define DRV_NAME "pata_hpt37x" | |
8d7b1c70 | 28 | #define DRV_VERSION "0.6.23" |
669a5db4 JG |
29 | |
30 | struct hpt_clock { | |
31 | u8 xfer_speed; | |
32 | u32 timing; | |
33 | }; | |
34 | ||
35 | struct hpt_chip { | |
36 | const char *name; | |
37 | unsigned int base; | |
38 | struct hpt_clock const *clocks[4]; | |
39 | }; | |
40 | ||
41 | /* key for bus clock timings | |
42 | * bit | |
fd5e62e2 SS |
43 | * 0:3 data_high_time. Inactive time of DIOW_/DIOR_ for PIO and MW DMA. |
44 | * cycles = value + 1 | |
45 | * 4:8 data_low_time. Active time of DIOW_/DIOR_ for PIO and MW DMA. | |
46 | * cycles = value + 1 | |
47 | * 9:12 cmd_high_time. Inactive time of DIOW_/DIOR_ during task file | |
669a5db4 | 48 | * register access. |
fd5e62e2 | 49 | * 13:17 cmd_low_time. Active time of DIOW_/DIOR_ during task file |
669a5db4 | 50 | * register access. |
fd5e62e2 SS |
51 | * 18:20 udma_cycle_time. Clock cycles for UDMA xfer. |
52 | * 21 CLK frequency for UDMA: 0=ATA clock, 1=dual ATA clock. | |
53 | * 22:24 pre_high_time. Time to initialize 1st cycle for PIO and MW DMA xfer. | |
54 | * 25:27 cmd_pre_high_time. Time to initialize 1st PIO cycle for task file | |
669a5db4 | 55 | * register access. |
fd5e62e2 SS |
56 | * 28 UDMA enable. |
57 | * 29 DMA enable. | |
58 | * 30 PIO_MST enable. If set, the chip is in bus master mode during | |
59 | * PIO xfer. | |
60 | * 31 FIFO enable. Only for PIO. | |
669a5db4 JG |
61 | */ |
62 | ||
fcc2f69a AC |
63 | static struct hpt_clock hpt37x_timings_33[] = { |
64 | { XFER_UDMA_6, 0x12446231 }, /* 0x12646231 ?? */ | |
65 | { XFER_UDMA_5, 0x12446231 }, | |
66 | { XFER_UDMA_4, 0x12446231 }, | |
67 | { XFER_UDMA_3, 0x126c6231 }, | |
68 | { XFER_UDMA_2, 0x12486231 }, | |
69 | { XFER_UDMA_1, 0x124c6233 }, | |
70 | { XFER_UDMA_0, 0x12506297 }, | |
71 | ||
72 | { XFER_MW_DMA_2, 0x22406c31 }, | |
73 | { XFER_MW_DMA_1, 0x22406c33 }, | |
74 | { XFER_MW_DMA_0, 0x22406c97 }, | |
75 | ||
76 | { XFER_PIO_4, 0x06414e31 }, | |
77 | { XFER_PIO_3, 0x06414e42 }, | |
78 | { XFER_PIO_2, 0x06414e53 }, | |
79 | { XFER_PIO_1, 0x06814e93 }, | |
80 | { XFER_PIO_0, 0x06814ea7 } | |
669a5db4 JG |
81 | }; |
82 | ||
fcc2f69a AC |
83 | static struct hpt_clock hpt37x_timings_50[] = { |
84 | { XFER_UDMA_6, 0x12848242 }, | |
85 | { XFER_UDMA_5, 0x12848242 }, | |
86 | { XFER_UDMA_4, 0x12ac8242 }, | |
87 | { XFER_UDMA_3, 0x128c8242 }, | |
88 | { XFER_UDMA_2, 0x120c8242 }, | |
89 | { XFER_UDMA_1, 0x12148254 }, | |
90 | { XFER_UDMA_0, 0x121882ea }, | |
91 | ||
92 | { XFER_MW_DMA_2, 0x22808242 }, | |
93 | { XFER_MW_DMA_1, 0x22808254 }, | |
94 | { XFER_MW_DMA_0, 0x228082ea }, | |
95 | ||
96 | { XFER_PIO_4, 0x0a81f442 }, | |
97 | { XFER_PIO_3, 0x0a81f443 }, | |
98 | { XFER_PIO_2, 0x0a81f454 }, | |
99 | { XFER_PIO_1, 0x0ac1f465 }, | |
100 | { XFER_PIO_0, 0x0ac1f48a } | |
669a5db4 JG |
101 | }; |
102 | ||
fcc2f69a AC |
103 | static struct hpt_clock hpt37x_timings_66[] = { |
104 | { XFER_UDMA_6, 0x1c869c62 }, | |
105 | { XFER_UDMA_5, 0x1cae9c62 }, /* 0x1c8a9c62 */ | |
106 | { XFER_UDMA_4, 0x1c8a9c62 }, | |
107 | { XFER_UDMA_3, 0x1c8e9c62 }, | |
108 | { XFER_UDMA_2, 0x1c929c62 }, | |
109 | { XFER_UDMA_1, 0x1c9a9c62 }, | |
110 | { XFER_UDMA_0, 0x1c829c62 }, | |
111 | ||
112 | { XFER_MW_DMA_2, 0x2c829c62 }, | |
113 | { XFER_MW_DMA_1, 0x2c829c66 }, | |
114 | { XFER_MW_DMA_0, 0x2c829d2e }, | |
115 | ||
116 | { XFER_PIO_4, 0x0c829c62 }, | |
117 | { XFER_PIO_3, 0x0c829c84 }, | |
118 | { XFER_PIO_2, 0x0c829ca6 }, | |
119 | { XFER_PIO_1, 0x0d029d26 }, | |
120 | { XFER_PIO_0, 0x0d029d5e } | |
669a5db4 JG |
121 | }; |
122 | ||
669a5db4 JG |
123 | |
124 | static const struct hpt_chip hpt370 = { | |
125 | "HPT370", | |
126 | 48, | |
127 | { | |
fcc2f69a | 128 | hpt37x_timings_33, |
669a5db4 JG |
129 | NULL, |
130 | NULL, | |
a4734468 | 131 | NULL |
669a5db4 JG |
132 | } |
133 | }; | |
134 | ||
135 | static const struct hpt_chip hpt370a = { | |
136 | "HPT370A", | |
137 | 48, | |
138 | { | |
fcc2f69a | 139 | hpt37x_timings_33, |
669a5db4 | 140 | NULL, |
fcc2f69a | 141 | hpt37x_timings_50, |
a4734468 | 142 | NULL |
669a5db4 JG |
143 | } |
144 | }; | |
145 | ||
146 | static const struct hpt_chip hpt372 = { | |
147 | "HPT372", | |
148 | 55, | |
149 | { | |
fcc2f69a | 150 | hpt37x_timings_33, |
669a5db4 | 151 | NULL, |
fcc2f69a AC |
152 | hpt37x_timings_50, |
153 | hpt37x_timings_66 | |
669a5db4 JG |
154 | } |
155 | }; | |
156 | ||
157 | static const struct hpt_chip hpt302 = { | |
158 | "HPT302", | |
159 | 66, | |
160 | { | |
fcc2f69a | 161 | hpt37x_timings_33, |
669a5db4 | 162 | NULL, |
fcc2f69a AC |
163 | hpt37x_timings_50, |
164 | hpt37x_timings_66 | |
669a5db4 JG |
165 | } |
166 | }; | |
167 | ||
168 | static const struct hpt_chip hpt371 = { | |
169 | "HPT371", | |
170 | 66, | |
171 | { | |
fcc2f69a | 172 | hpt37x_timings_33, |
669a5db4 | 173 | NULL, |
fcc2f69a AC |
174 | hpt37x_timings_50, |
175 | hpt37x_timings_66 | |
669a5db4 JG |
176 | } |
177 | }; | |
178 | ||
179 | static const struct hpt_chip hpt372a = { | |
180 | "HPT372A", | |
181 | 66, | |
182 | { | |
fcc2f69a | 183 | hpt37x_timings_33, |
669a5db4 | 184 | NULL, |
fcc2f69a AC |
185 | hpt37x_timings_50, |
186 | hpt37x_timings_66 | |
669a5db4 JG |
187 | } |
188 | }; | |
189 | ||
190 | static const struct hpt_chip hpt374 = { | |
191 | "HPT374", | |
192 | 48, | |
193 | { | |
fcc2f69a | 194 | hpt37x_timings_33, |
669a5db4 JG |
195 | NULL, |
196 | NULL, | |
197 | NULL | |
198 | } | |
199 | }; | |
200 | ||
201 | /** | |
202 | * hpt37x_find_mode - reset the hpt37x bus | |
203 | * @ap: ATA port | |
204 | * @speed: transfer mode | |
205 | * | |
206 | * Return the 32bit register programming information for this channel | |
207 | * that matches the speed provided. | |
208 | */ | |
85cd7251 | 209 | |
669a5db4 JG |
210 | static u32 hpt37x_find_mode(struct ata_port *ap, int speed) |
211 | { | |
212 | struct hpt_clock *clocks = ap->host->private_data; | |
85cd7251 | 213 | |
49bfbd38 | 214 | while (clocks->xfer_speed) { |
669a5db4 JG |
215 | if (clocks->xfer_speed == speed) |
216 | return clocks->timing; | |
217 | clocks++; | |
218 | } | |
219 | BUG(); | |
220 | return 0xffffffffU; /* silence compiler warning */ | |
221 | } | |
222 | ||
49bfbd38 SS |
223 | static int hpt_dma_blacklisted(const struct ata_device *dev, char *modestr, |
224 | const char * const list[]) | |
669a5db4 | 225 | { |
8bfa79fc | 226 | unsigned char model_num[ATA_ID_PROD_LEN + 1]; |
669a5db4 JG |
227 | int i = 0; |
228 | ||
8bfa79fc | 229 | ata_id_c_string(dev->id, model_num, ATA_ID_PROD, sizeof(model_num)); |
669a5db4 | 230 | |
8bfa79fc TH |
231 | while (list[i] != NULL) { |
232 | if (!strcmp(list[i], model_num)) { | |
8d7b1c70 JP |
233 | pr_warn("%s is not supported for %s\n", |
234 | modestr, list[i]); | |
669a5db4 JG |
235 | return 1; |
236 | } | |
237 | i++; | |
238 | } | |
239 | return 0; | |
240 | } | |
241 | ||
49bfbd38 SS |
242 | static const char * const bad_ata33[] = { |
243 | "Maxtor 92720U8", "Maxtor 92040U6", "Maxtor 91360U4", "Maxtor 91020U3", | |
244 | "Maxtor 90845U3", "Maxtor 90650U2", | |
245 | "Maxtor 91360D8", "Maxtor 91190D7", "Maxtor 91020D6", "Maxtor 90845D5", | |
246 | "Maxtor 90680D4", "Maxtor 90510D3", "Maxtor 90340D2", | |
247 | "Maxtor 91152D8", "Maxtor 91008D7", "Maxtor 90845D6", "Maxtor 90840D6", | |
248 | "Maxtor 90720D5", "Maxtor 90648D5", "Maxtor 90576D4", | |
669a5db4 JG |
249 | "Maxtor 90510D4", |
250 | "Maxtor 90432D3", "Maxtor 90288D2", "Maxtor 90256D2", | |
49bfbd38 SS |
251 | "Maxtor 91000D8", "Maxtor 90910D8", "Maxtor 90875D7", "Maxtor 90840D7", |
252 | "Maxtor 90750D6", "Maxtor 90625D5", "Maxtor 90500D4", | |
253 | "Maxtor 91728D8", "Maxtor 91512D7", "Maxtor 91303D6", "Maxtor 91080D5", | |
254 | "Maxtor 90845D4", "Maxtor 90680D4", "Maxtor 90648D3", "Maxtor 90432D2", | |
669a5db4 JG |
255 | NULL |
256 | }; | |
257 | ||
49bfbd38 | 258 | static const char * const bad_ata100_5[] = { |
669a5db4 JG |
259 | "IBM-DTLA-307075", |
260 | "IBM-DTLA-307060", | |
261 | "IBM-DTLA-307045", | |
262 | "IBM-DTLA-307030", | |
263 | "IBM-DTLA-307020", | |
264 | "IBM-DTLA-307015", | |
265 | "IBM-DTLA-305040", | |
266 | "IBM-DTLA-305030", | |
267 | "IBM-DTLA-305020", | |
268 | "IC35L010AVER07-0", | |
269 | "IC35L020AVER07-0", | |
270 | "IC35L030AVER07-0", | |
271 | "IC35L040AVER07-0", | |
272 | "IC35L060AVER07-0", | |
273 | "WDC AC310200R", | |
274 | NULL | |
275 | }; | |
276 | ||
277 | /** | |
278 | * hpt370_filter - mode selection filter | |
669a5db4 JG |
279 | * @adev: ATA device |
280 | * | |
281 | * Block UDMA on devices that cause trouble with this controller. | |
282 | */ | |
85cd7251 | 283 | |
a76b62ca | 284 | static unsigned long hpt370_filter(struct ata_device *adev, unsigned long mask) |
669a5db4 | 285 | { |
6929da44 | 286 | if (adev->class == ATA_DEV_ATA) { |
669a5db4 JG |
287 | if (hpt_dma_blacklisted(adev, "UDMA", bad_ata33)) |
288 | mask &= ~ATA_MASK_UDMA; | |
289 | if (hpt_dma_blacklisted(adev, "UDMA100", bad_ata100_5)) | |
6ddd6861 | 290 | mask &= ~(0xE0 << ATA_SHIFT_UDMA); |
669a5db4 | 291 | } |
c7087652 | 292 | return mask; |
669a5db4 JG |
293 | } |
294 | ||
295 | /** | |
296 | * hpt370a_filter - mode selection filter | |
669a5db4 JG |
297 | * @adev: ATA device |
298 | * | |
299 | * Block UDMA on devices that cause trouble with this controller. | |
300 | */ | |
85cd7251 | 301 | |
a76b62ca | 302 | static unsigned long hpt370a_filter(struct ata_device *adev, unsigned long mask) |
669a5db4 | 303 | { |
73946f9f | 304 | if (adev->class == ATA_DEV_ATA) { |
669a5db4 | 305 | if (hpt_dma_blacklisted(adev, "UDMA100", bad_ata100_5)) |
6ddd6861 | 306 | mask &= ~(0xE0 << ATA_SHIFT_UDMA); |
669a5db4 | 307 | } |
c7087652 | 308 | return mask; |
669a5db4 | 309 | } |
85cd7251 | 310 | |
8e834c2e SS |
311 | /** |
312 | * hpt372_filter - mode selection filter | |
313 | * @adev: ATA device | |
314 | * @mask: mode mask | |
315 | * | |
316 | * The Marvell bridge chips used on the HighPoint SATA cards do not seem | |
317 | * to support the UltraDMA modes 1, 2, and 3 as well as any MWDMA modes... | |
318 | */ | |
319 | static unsigned long hpt372_filter(struct ata_device *adev, unsigned long mask) | |
320 | { | |
321 | if (ata_id_is_sata(adev->id)) | |
322 | mask &= ~((0xE << ATA_SHIFT_UDMA) | ATA_MASK_MWDMA); | |
323 | ||
324 | return mask; | |
325 | } | |
326 | ||
9e87be9e BZ |
327 | /** |
328 | * hpt37x_cable_detect - Detect the cable type | |
329 | * @ap: ATA port to detect on | |
330 | * | |
331 | * Return the cable type attached to this port | |
332 | */ | |
333 | ||
334 | static int hpt37x_cable_detect(struct ata_port *ap) | |
335 | { | |
336 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); | |
337 | u8 scr2, ata66; | |
338 | ||
339 | pci_read_config_byte(pdev, 0x5B, &scr2); | |
340 | pci_write_config_byte(pdev, 0x5B, scr2 & ~0x01); | |
10a9c969 BZ |
341 | |
342 | udelay(10); /* debounce */ | |
343 | ||
9e87be9e BZ |
344 | /* Cable register now active */ |
345 | pci_read_config_byte(pdev, 0x5A, &ata66); | |
346 | /* Restore state */ | |
347 | pci_write_config_byte(pdev, 0x5B, scr2); | |
348 | ||
349 | if (ata66 & (2 >> ap->port_no)) | |
350 | return ATA_CBL_PATA40; | |
351 | else | |
352 | return ATA_CBL_PATA80; | |
353 | } | |
354 | ||
355 | /** | |
356 | * hpt374_fn1_cable_detect - Detect the cable type | |
357 | * @ap: ATA port to detect on | |
358 | * | |
359 | * Return the cable type attached to this port | |
360 | */ | |
361 | ||
362 | static int hpt374_fn1_cable_detect(struct ata_port *ap) | |
363 | { | |
364 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); | |
365 | unsigned int mcrbase = 0x50 + 4 * ap->port_no; | |
366 | u16 mcr3; | |
367 | u8 ata66; | |
368 | ||
369 | /* Do the extra channel work */ | |
370 | pci_read_config_word(pdev, mcrbase + 2, &mcr3); | |
371 | /* Set bit 15 of 0x52 to enable TCBLID as input */ | |
372 | pci_write_config_word(pdev, mcrbase + 2, mcr3 | 0x8000); | |
373 | pci_read_config_byte(pdev, 0x5A, &ata66); | |
374 | /* Reset TCBLID/FCBLID to output */ | |
375 | pci_write_config_word(pdev, mcrbase + 2, mcr3); | |
376 | ||
377 | if (ata66 & (2 >> ap->port_no)) | |
378 | return ATA_CBL_PATA40; | |
379 | else | |
380 | return ATA_CBL_PATA80; | |
381 | } | |
382 | ||
669a5db4 JG |
383 | /** |
384 | * hpt37x_pre_reset - reset the hpt37x bus | |
cc0680a5 | 385 | * @link: ATA link to reset |
d4b2bab4 | 386 | * @deadline: deadline jiffies for the operation |
669a5db4 | 387 | * |
ab81a505 | 388 | * Perform the initial reset handling for the HPT37x. |
669a5db4 | 389 | */ |
85cd7251 | 390 | |
cc0680a5 | 391 | static int hpt37x_pre_reset(struct ata_link *link, unsigned long deadline) |
669a5db4 | 392 | { |
cc0680a5 | 393 | struct ata_port *ap = link->ap; |
669a5db4 | 394 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); |
b5bf24b9 AC |
395 | static const struct pci_bits hpt37x_enable_bits[] = { |
396 | { 0x50, 1, 0x04, 0x04 }, | |
397 | { 0x54, 1, 0x04, 0x04 } | |
398 | }; | |
49bfbd38 | 399 | |
b5bf24b9 AC |
400 | if (!pci_test_config_bits(pdev, &hpt37x_enable_bits[ap->port_no])) |
401 | return -ENOENT; | |
f20b16ff | 402 | |
669a5db4 | 403 | /* Reset the state machine */ |
fcc2f69a | 404 | pci_write_config_byte(pdev, 0x50 + 4 * ap->port_no, 0x37); |
669a5db4 | 405 | udelay(100); |
85cd7251 | 406 | |
9363c382 | 407 | return ata_sff_prereset(link, deadline); |
669a5db4 JG |
408 | } |
409 | ||
1a1b172b SS |
410 | static void hpt370_set_mode(struct ata_port *ap, struct ata_device *adev, |
411 | u8 mode) | |
669a5db4 JG |
412 | { |
413 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); | |
414 | u32 addr1, addr2; | |
1a1b172b | 415 | u32 reg, timing, mask; |
669a5db4 JG |
416 | u8 fast; |
417 | ||
418 | addr1 = 0x40 + 4 * (adev->devno + 2 * ap->port_no); | |
419 | addr2 = 0x51 + 4 * ap->port_no; | |
85cd7251 | 420 | |
669a5db4 JG |
421 | /* Fast interrupt prediction disable, hold off interrupt disable */ |
422 | pci_read_config_byte(pdev, addr2, &fast); | |
423 | fast &= ~0x02; | |
424 | fast |= 0x01; | |
425 | pci_write_config_byte(pdev, addr2, fast); | |
85cd7251 | 426 | |
1a1b172b SS |
427 | /* Determine timing mask and find matching mode entry */ |
428 | if (mode < XFER_MW_DMA_0) | |
429 | mask = 0xcfc3ffff; | |
430 | else if (mode < XFER_UDMA_0) | |
431 | mask = 0x31c001ff; | |
432 | else | |
433 | mask = 0x303c0000; | |
434 | ||
435 | timing = hpt37x_find_mode(ap, mode); | |
436 | ||
669a5db4 | 437 | pci_read_config_dword(pdev, addr1, ®); |
1a1b172b SS |
438 | reg = (reg & ~mask) | (timing & mask); |
439 | pci_write_config_dword(pdev, addr1, reg); | |
440 | } | |
441 | /** | |
442 | * hpt370_set_piomode - PIO setup | |
443 | * @ap: ATA interface | |
444 | * @adev: device on the interface | |
445 | * | |
446 | * Perform PIO mode setup. | |
447 | */ | |
448 | ||
449 | static void hpt370_set_piomode(struct ata_port *ap, struct ata_device *adev) | |
450 | { | |
451 | hpt370_set_mode(ap, adev, adev->pio_mode); | |
669a5db4 JG |
452 | } |
453 | ||
454 | /** | |
455 | * hpt370_set_dmamode - DMA timing setup | |
456 | * @ap: ATA interface | |
457 | * @adev: Device being configured | |
458 | * | |
1a1b172b | 459 | * Set up the channel for MWDMA or UDMA modes. |
669a5db4 | 460 | */ |
85cd7251 | 461 | |
669a5db4 JG |
462 | static void hpt370_set_dmamode(struct ata_port *ap, struct ata_device *adev) |
463 | { | |
1a1b172b | 464 | hpt370_set_mode(ap, adev, adev->dma_mode); |
669a5db4 JG |
465 | } |
466 | ||
669a5db4 JG |
467 | /** |
468 | * hpt370_bmdma_end - DMA engine stop | |
469 | * @qc: ATA command | |
470 | * | |
471 | * Work around the HPT370 DMA engine. | |
472 | */ | |
85cd7251 | 473 | |
669a5db4 JG |
474 | static void hpt370_bmdma_stop(struct ata_queued_cmd *qc) |
475 | { | |
476 | struct ata_port *ap = qc->ap; | |
477 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); | |
0d5ff566 | 478 | void __iomem *bmdma = ap->ioaddr.bmdma_addr; |
56f46f8c SS |
479 | u8 dma_stat = ioread8(bmdma + ATA_DMA_STATUS); |
480 | u8 dma_cmd; | |
85cd7251 | 481 | |
56f46f8c | 482 | if (dma_stat & ATA_DMA_ACTIVE) { |
669a5db4 | 483 | udelay(20); |
56f46f8c | 484 | dma_stat = ioread8(bmdma + ATA_DMA_STATUS); |
669a5db4 | 485 | } |
56f46f8c | 486 | if (dma_stat & ATA_DMA_ACTIVE) { |
669a5db4 JG |
487 | /* Clear the engine */ |
488 | pci_write_config_byte(pdev, 0x50 + 4 * ap->port_no, 0x37); | |
489 | udelay(10); | |
490 | /* Stop DMA */ | |
56f46f8c SS |
491 | dma_cmd = ioread8(bmdma + ATA_DMA_CMD); |
492 | iowrite8(dma_cmd & ~ATA_DMA_START, bmdma + ATA_DMA_CMD); | |
669a5db4 | 493 | /* Clear Error */ |
56f46f8c SS |
494 | dma_stat = ioread8(bmdma + ATA_DMA_STATUS); |
495 | iowrite8(dma_stat | ATA_DMA_INTR | ATA_DMA_ERR, | |
496 | bmdma + ATA_DMA_STATUS); | |
669a5db4 JG |
497 | /* Clear the engine */ |
498 | pci_write_config_byte(pdev, 0x50 + 4 * ap->port_no, 0x37); | |
499 | udelay(10); | |
500 | } | |
501 | ata_bmdma_stop(qc); | |
502 | } | |
503 | ||
1a1b172b SS |
504 | static void hpt372_set_mode(struct ata_port *ap, struct ata_device *adev, |
505 | u8 mode) | |
669a5db4 JG |
506 | { |
507 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); | |
508 | u32 addr1, addr2; | |
1a1b172b | 509 | u32 reg, timing, mask; |
669a5db4 JG |
510 | u8 fast; |
511 | ||
512 | addr1 = 0x40 + 4 * (adev->devno + 2 * ap->port_no); | |
513 | addr2 = 0x51 + 4 * ap->port_no; | |
85cd7251 | 514 | |
669a5db4 JG |
515 | /* Fast interrupt prediction disable, hold off interrupt disable */ |
516 | pci_read_config_byte(pdev, addr2, &fast); | |
517 | fast &= ~0x07; | |
518 | pci_write_config_byte(pdev, addr2, fast); | |
85cd7251 | 519 | |
1a1b172b SS |
520 | /* Determine timing mask and find matching mode entry */ |
521 | if (mode < XFER_MW_DMA_0) | |
522 | mask = 0xcfc3ffff; | |
523 | else if (mode < XFER_UDMA_0) | |
524 | mask = 0x31c001ff; | |
525 | else | |
526 | mask = 0x303c0000; | |
527 | ||
528 | timing = hpt37x_find_mode(ap, mode); | |
529 | ||
669a5db4 | 530 | pci_read_config_dword(pdev, addr1, ®); |
1a1b172b SS |
531 | reg = (reg & ~mask) | (timing & mask); |
532 | pci_write_config_dword(pdev, addr1, reg); | |
533 | } | |
85cd7251 | 534 | |
1a1b172b SS |
535 | /** |
536 | * hpt372_set_piomode - PIO setup | |
537 | * @ap: ATA interface | |
538 | * @adev: device on the interface | |
539 | * | |
540 | * Perform PIO mode setup. | |
541 | */ | |
542 | ||
543 | static void hpt372_set_piomode(struct ata_port *ap, struct ata_device *adev) | |
544 | { | |
545 | hpt372_set_mode(ap, adev, adev->pio_mode); | |
669a5db4 JG |
546 | } |
547 | ||
548 | /** | |
549 | * hpt372_set_dmamode - DMA timing setup | |
550 | * @ap: ATA interface | |
551 | * @adev: Device being configured | |
552 | * | |
1a1b172b | 553 | * Set up the channel for MWDMA or UDMA modes. |
669a5db4 | 554 | */ |
85cd7251 | 555 | |
669a5db4 JG |
556 | static void hpt372_set_dmamode(struct ata_port *ap, struct ata_device *adev) |
557 | { | |
1a1b172b | 558 | hpt372_set_mode(ap, adev, adev->dma_mode); |
669a5db4 JG |
559 | } |
560 | ||
561 | /** | |
562 | * hpt37x_bmdma_end - DMA engine stop | |
563 | * @qc: ATA command | |
564 | * | |
565 | * Clean up after the HPT372 and later DMA engine | |
566 | */ | |
85cd7251 | 567 | |
669a5db4 JG |
568 | static void hpt37x_bmdma_stop(struct ata_queued_cmd *qc) |
569 | { | |
570 | struct ata_port *ap = qc->ap; | |
571 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); | |
6929da44 | 572 | int mscreg = 0x50 + 4 * ap->port_no; |
669a5db4 | 573 | u8 bwsr_stat, msc_stat; |
85cd7251 | 574 | |
669a5db4 JG |
575 | pci_read_config_byte(pdev, 0x6A, &bwsr_stat); |
576 | pci_read_config_byte(pdev, mscreg, &msc_stat); | |
577 | if (bwsr_stat & (1 << ap->port_no)) | |
578 | pci_write_config_byte(pdev, mscreg, msc_stat | 0x30); | |
579 | ata_bmdma_stop(qc); | |
580 | } | |
581 | ||
582 | ||
583 | static struct scsi_host_template hpt37x_sht = { | |
68d1d07b | 584 | ATA_BMDMA_SHT(DRV_NAME), |
669a5db4 JG |
585 | }; |
586 | ||
587 | /* | |
588 | * Configuration for HPT370 | |
589 | */ | |
85cd7251 | 590 | |
669a5db4 | 591 | static struct ata_port_operations hpt370_port_ops = { |
029cfd6b | 592 | .inherits = &ata_bmdma_port_ops, |
669a5db4 | 593 | |
669a5db4 | 594 | .bmdma_stop = hpt370_bmdma_stop, |
669a5db4 | 595 | |
029cfd6b | 596 | .mode_filter = hpt370_filter, |
9e87be9e | 597 | .cable_detect = hpt37x_cable_detect, |
029cfd6b TH |
598 | .set_piomode = hpt370_set_piomode, |
599 | .set_dmamode = hpt370_set_dmamode, | |
a1efdaba | 600 | .prereset = hpt37x_pre_reset, |
85cd7251 | 601 | }; |
669a5db4 JG |
602 | |
603 | /* | |
604 | * Configuration for HPT370A. Close to 370 but less filters | |
605 | */ | |
85cd7251 | 606 | |
669a5db4 | 607 | static struct ata_port_operations hpt370a_port_ops = { |
029cfd6b | 608 | .inherits = &hpt370_port_ops, |
669a5db4 | 609 | .mode_filter = hpt370a_filter, |
85cd7251 | 610 | }; |
669a5db4 JG |
611 | |
612 | /* | |
8e834c2e SS |
613 | * Configuration for HPT371 and HPT302. Slightly different PIO and DMA |
614 | * mode setting functionality. | |
669a5db4 | 615 | */ |
85cd7251 | 616 | |
8e834c2e | 617 | static struct ata_port_operations hpt302_port_ops = { |
029cfd6b | 618 | .inherits = &ata_bmdma_port_ops, |
669a5db4 | 619 | |
669a5db4 | 620 | .bmdma_stop = hpt37x_bmdma_stop, |
669a5db4 | 621 | |
9e87be9e | 622 | .cable_detect = hpt37x_cable_detect, |
029cfd6b TH |
623 | .set_piomode = hpt372_set_piomode, |
624 | .set_dmamode = hpt372_set_dmamode, | |
a1efdaba | 625 | .prereset = hpt37x_pre_reset, |
85cd7251 | 626 | }; |
669a5db4 JG |
627 | |
628 | /* | |
8e834c2e SS |
629 | * Configuration for HPT372. Mode setting works like 371 and 302 |
630 | * but we have a mode filter. | |
631 | */ | |
632 | ||
633 | static struct ata_port_operations hpt372_port_ops = { | |
634 | .inherits = &hpt302_port_ops, | |
635 | .mode_filter = hpt372_filter, | |
636 | }; | |
637 | ||
638 | /* | |
639 | * Configuration for HPT374. Mode setting and filtering works like 372 | |
a1efdaba | 640 | * but we have a different cable detection procedure for function 1. |
669a5db4 | 641 | */ |
85cd7251 | 642 | |
a1efdaba | 643 | static struct ata_port_operations hpt374_fn1_port_ops = { |
029cfd6b | 644 | .inherits = &hpt372_port_ops, |
9e87be9e | 645 | .cable_detect = hpt374_fn1_cable_detect, |
85cd7251 | 646 | }; |
669a5db4 JG |
647 | |
648 | /** | |
ad452d64 | 649 | * hpt37x_clock_slot - Turn timing to PC clock entry |
669a5db4 JG |
650 | * @freq: Reported frequency timing |
651 | * @base: Base timing | |
652 | * | |
653 | * Turn the timing data intoa clock slot (0 for 33, 1 for 40, 2 for 50 | |
654 | * and 3 for 66Mhz) | |
655 | */ | |
85cd7251 | 656 | |
669a5db4 JG |
657 | static int hpt37x_clock_slot(unsigned int freq, unsigned int base) |
658 | { | |
659 | unsigned int f = (base * freq) / 192; /* Mhz */ | |
660 | if (f < 40) | |
661 | return 0; /* 33Mhz slot */ | |
662 | if (f < 45) | |
663 | return 1; /* 40Mhz slot */ | |
664 | if (f < 55) | |
665 | return 2; /* 50Mhz slot */ | |
666 | return 3; /* 60Mhz slot */ | |
667 | } | |
668 | ||
669 | /** | |
670 | * hpt37x_calibrate_dpll - Calibrate the DPLL loop | |
85cd7251 | 671 | * @dev: PCI device |
669a5db4 JG |
672 | * |
673 | * Perform a calibration cycle on the HPT37x DPLL. Returns 1 if this | |
674 | * succeeds | |
675 | */ | |
676 | ||
677 | static int hpt37x_calibrate_dpll(struct pci_dev *dev) | |
678 | { | |
679 | u8 reg5b; | |
680 | u32 reg5c; | |
681 | int tries; | |
85cd7251 | 682 | |
49bfbd38 | 683 | for (tries = 0; tries < 0x5000; tries++) { |
669a5db4 JG |
684 | udelay(50); |
685 | pci_read_config_byte(dev, 0x5b, ®5b); | |
686 | if (reg5b & 0x80) { | |
687 | /* See if it stays set */ | |
49bfbd38 | 688 | for (tries = 0; tries < 0x1000; tries++) { |
669a5db4 JG |
689 | pci_read_config_byte(dev, 0x5b, ®5b); |
690 | /* Failed ? */ | |
691 | if ((reg5b & 0x80) == 0) | |
692 | return 0; | |
693 | } | |
694 | /* Turn off tuning, we have the DPLL set */ | |
695 | pci_read_config_dword(dev, 0x5c, ®5c); | |
49bfbd38 | 696 | pci_write_config_dword(dev, 0x5c, reg5c & ~0x100); |
669a5db4 JG |
697 | return 1; |
698 | } | |
699 | } | |
700 | /* Never went stable */ | |
701 | return 0; | |
702 | } | |
73946f9f AC |
703 | |
704 | static u32 hpt374_read_freq(struct pci_dev *pdev) | |
705 | { | |
706 | u32 freq; | |
707 | unsigned long io_base = pci_resource_start(pdev, 4); | |
49bfbd38 | 708 | |
73946f9f | 709 | if (PCI_FUNC(pdev->devfn) & 1) { |
40f46f17 AM |
710 | struct pci_dev *pdev_0; |
711 | ||
712 | pdev_0 = pci_get_slot(pdev->bus, pdev->devfn - 1); | |
73946f9f AC |
713 | /* Someone hot plugged the controller on us ? */ |
714 | if (pdev_0 == NULL) | |
715 | return 0; | |
716 | io_base = pci_resource_start(pdev_0, 4); | |
717 | freq = inl(io_base + 0x90); | |
718 | pci_dev_put(pdev_0); | |
40f46f17 | 719 | } else |
73946f9f AC |
720 | freq = inl(io_base + 0x90); |
721 | return freq; | |
722 | } | |
723 | ||
669a5db4 JG |
724 | /** |
725 | * hpt37x_init_one - Initialise an HPT37X/302 | |
726 | * @dev: PCI device | |
727 | * @id: Entry in match table | |
728 | * | |
729 | * Initialise an HPT37x device. There are some interesting complications | |
730 | * here. Firstly the chip may report 366 and be one of several variants. | |
731 | * Secondly all the timings depend on the clock for the chip which we must | |
732 | * detect and look up | |
733 | * | |
734 | * This is the known chip mappings. It may be missing a couple of later | |
735 | * releases. | |
736 | * | |
737 | * Chip version PCI Rev Notes | |
738 | * HPT366 4 (HPT366) 0 Other driver | |
739 | * HPT366 4 (HPT366) 1 Other driver | |
740 | * HPT368 4 (HPT366) 2 Other driver | |
741 | * HPT370 4 (HPT366) 3 UDMA100 | |
742 | * HPT370A 4 (HPT366) 4 UDMA100 | |
743 | * HPT372 4 (HPT366) 5 UDMA133 (1) | |
744 | * HPT372N 4 (HPT366) 6 Other driver | |
745 | * HPT372A 5 (HPT372) 1 UDMA133 (1) | |
746 | * HPT372N 5 (HPT372) 2 Other driver | |
747 | * HPT302 6 (HPT302) 1 UDMA133 | |
748 | * HPT302N 6 (HPT302) 2 Other driver | |
749 | * HPT371 7 (HPT371) * UDMA133 | |
750 | * HPT374 8 (HPT374) * UDMA133 4 channel | |
751 | * HPT372N 9 (HPT372N) * Other driver | |
752 | * | |
753 | * (1) UDMA133 support depends on the bus clock | |
754 | */ | |
85cd7251 | 755 | |
669a5db4 JG |
756 | static int hpt37x_init_one(struct pci_dev *dev, const struct pci_device_id *id) |
757 | { | |
758 | /* HPT370 - UDMA100 */ | |
1626aeb8 | 759 | static const struct ata_port_info info_hpt370 = { |
1d2808fd | 760 | .flags = ATA_FLAG_SLAVE_POSS, |
14bdef98 EIB |
761 | .pio_mask = ATA_PIO4, |
762 | .mwdma_mask = ATA_MWDMA2, | |
bf6263a8 | 763 | .udma_mask = ATA_UDMA5, |
669a5db4 JG |
764 | .port_ops = &hpt370_port_ops |
765 | }; | |
766 | /* HPT370A - UDMA100 */ | |
1626aeb8 | 767 | static const struct ata_port_info info_hpt370a = { |
1d2808fd | 768 | .flags = ATA_FLAG_SLAVE_POSS, |
14bdef98 EIB |
769 | .pio_mask = ATA_PIO4, |
770 | .mwdma_mask = ATA_MWDMA2, | |
bf6263a8 | 771 | .udma_mask = ATA_UDMA5, |
669a5db4 JG |
772 | .port_ops = &hpt370a_port_ops |
773 | }; | |
fc2698d5 | 774 | /* HPT370 - UDMA66 */ |
1626aeb8 | 775 | static const struct ata_port_info info_hpt370_33 = { |
1d2808fd | 776 | .flags = ATA_FLAG_SLAVE_POSS, |
14bdef98 EIB |
777 | .pio_mask = ATA_PIO4, |
778 | .mwdma_mask = ATA_MWDMA2, | |
fc2698d5 | 779 | .udma_mask = ATA_UDMA4, |
fcc2f69a AC |
780 | .port_ops = &hpt370_port_ops |
781 | }; | |
fc2698d5 | 782 | /* HPT370A - UDMA66 */ |
1626aeb8 | 783 | static const struct ata_port_info info_hpt370a_33 = { |
1d2808fd | 784 | .flags = ATA_FLAG_SLAVE_POSS, |
14bdef98 EIB |
785 | .pio_mask = ATA_PIO4, |
786 | .mwdma_mask = ATA_MWDMA2, | |
fc2698d5 | 787 | .udma_mask = ATA_UDMA4, |
fcc2f69a AC |
788 | .port_ops = &hpt370a_port_ops |
789 | }; | |
8e834c2e | 790 | /* HPT372 - UDMA133 */ |
1626aeb8 | 791 | static const struct ata_port_info info_hpt372 = { |
1d2808fd | 792 | .flags = ATA_FLAG_SLAVE_POSS, |
14bdef98 EIB |
793 | .pio_mask = ATA_PIO4, |
794 | .mwdma_mask = ATA_MWDMA2, | |
bf6263a8 | 795 | .udma_mask = ATA_UDMA6, |
669a5db4 JG |
796 | .port_ops = &hpt372_port_ops |
797 | }; | |
8e834c2e SS |
798 | /* HPT371, 302 - UDMA133 */ |
799 | static const struct ata_port_info info_hpt302 = { | |
800 | .flags = ATA_FLAG_SLAVE_POSS, | |
801 | .pio_mask = ATA_PIO4, | |
802 | .mwdma_mask = ATA_MWDMA2, | |
803 | .udma_mask = ATA_UDMA6, | |
804 | .port_ops = &hpt302_port_ops | |
805 | }; | |
defed559 | 806 | /* HPT374 - UDMA100, function 1 uses different cable_detect method */ |
a1efdaba TH |
807 | static const struct ata_port_info info_hpt374_fn0 = { |
808 | .flags = ATA_FLAG_SLAVE_POSS, | |
14bdef98 EIB |
809 | .pio_mask = ATA_PIO4, |
810 | .mwdma_mask = ATA_MWDMA2, | |
a1efdaba TH |
811 | .udma_mask = ATA_UDMA5, |
812 | .port_ops = &hpt372_port_ops | |
813 | }; | |
814 | static const struct ata_port_info info_hpt374_fn1 = { | |
1d2808fd | 815 | .flags = ATA_FLAG_SLAVE_POSS, |
14bdef98 EIB |
816 | .pio_mask = ATA_PIO4, |
817 | .mwdma_mask = ATA_MWDMA2, | |
bf6263a8 | 818 | .udma_mask = ATA_UDMA5, |
a1efdaba | 819 | .port_ops = &hpt374_fn1_port_ops |
669a5db4 JG |
820 | }; |
821 | ||
822 | static const int MHz[4] = { 33, 40, 50, 66 }; | |
1626aeb8 | 823 | void *private_data = NULL; |
887125e3 | 824 | const struct ata_port_info *ppi[] = { NULL, NULL }; |
89d3b360 | 825 | u8 rev = dev->revision; |
669a5db4 | 826 | u8 irqmask; |
fcc2f69a | 827 | u8 mcr1; |
669a5db4 | 828 | u32 freq; |
fcc2f69a | 829 | int prefer_dpll = 1; |
a617c09f | 830 | |
fcc2f69a | 831 | unsigned long iobase = pci_resource_start(dev, 4); |
669a5db4 JG |
832 | |
833 | const struct hpt_chip *chip_table; | |
834 | int clock_slot; | |
f08048e9 TH |
835 | int rc; |
836 | ||
837 | rc = pcim_enable_device(dev); | |
838 | if (rc) | |
839 | return rc; | |
669a5db4 | 840 | |
910f7bb1 SS |
841 | switch (dev->device) { |
842 | case PCI_DEVICE_ID_TTI_HPT366: | |
669a5db4 JG |
843 | /* May be a later chip in disguise. Check */ |
844 | /* Older chips are in the HPT366 driver. Ignore them */ | |
89d3b360 | 845 | if (rev < 3) |
669a5db4 JG |
846 | return -ENODEV; |
847 | /* N series chips have their own driver. Ignore */ | |
89d3b360 | 848 | if (rev == 6) |
669a5db4 JG |
849 | return -ENODEV; |
850 | ||
49bfbd38 SS |
851 | switch (rev) { |
852 | case 3: | |
853 | ppi[0] = &info_hpt370; | |
854 | chip_table = &hpt370; | |
855 | prefer_dpll = 0; | |
856 | break; | |
857 | case 4: | |
858 | ppi[0] = &info_hpt370a; | |
859 | chip_table = &hpt370a; | |
860 | prefer_dpll = 0; | |
861 | break; | |
862 | case 5: | |
863 | ppi[0] = &info_hpt372; | |
864 | chip_table = &hpt372; | |
865 | break; | |
866 | default: | |
8d7b1c70 JP |
867 | pr_err("Unknown HPT366 subtype, please report (%d)\n", |
868 | rev); | |
49bfbd38 | 869 | return -ENODEV; |
669a5db4 | 870 | } |
910f7bb1 SS |
871 | break; |
872 | case PCI_DEVICE_ID_TTI_HPT372: | |
873 | /* 372N if rev >= 2 */ | |
874 | if (rev >= 2) | |
875 | return -ENODEV; | |
876 | ppi[0] = &info_hpt372; | |
877 | chip_table = &hpt372a; | |
878 | break; | |
879 | case PCI_DEVICE_ID_TTI_HPT302: | |
880 | /* 302N if rev > 1 */ | |
881 | if (rev > 1) | |
882 | return -ENODEV; | |
883 | ppi[0] = &info_hpt302; | |
884 | /* Check this */ | |
885 | chip_table = &hpt302; | |
886 | break; | |
887 | case PCI_DEVICE_ID_TTI_HPT371: | |
888 | if (rev > 1) | |
889 | return -ENODEV; | |
890 | ppi[0] = &info_hpt302; | |
891 | chip_table = &hpt371; | |
892 | /* | |
893 | * Single channel device, master is not present but the BIOS | |
894 | * (or us for non x86) must mark it absent | |
895 | */ | |
896 | pci_read_config_byte(dev, 0x50, &mcr1); | |
897 | mcr1 &= ~0x04; | |
898 | pci_write_config_byte(dev, 0x50, mcr1); | |
899 | break; | |
900 | case PCI_DEVICE_ID_TTI_HPT374: | |
901 | chip_table = &hpt374; | |
902 | if (!(PCI_FUNC(dev->devfn) & 1)) | |
903 | *ppi = &info_hpt374_fn0; | |
904 | else | |
905 | *ppi = &info_hpt374_fn1; | |
906 | break; | |
907 | default: | |
8d7b1c70 | 908 | pr_err("PCI table is bogus, please report (%d)\n", dev->device); |
910f7bb1 | 909 | return -ENODEV; |
669a5db4 JG |
910 | } |
911 | /* Ok so this is a chip we support */ | |
912 | ||
913 | pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, (L1_CACHE_BYTES / 4)); | |
914 | pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x78); | |
915 | pci_write_config_byte(dev, PCI_MIN_GNT, 0x08); | |
916 | pci_write_config_byte(dev, PCI_MAX_LAT, 0x08); | |
917 | ||
918 | pci_read_config_byte(dev, 0x5A, &irqmask); | |
919 | irqmask &= ~0x10; | |
920 | pci_write_config_byte(dev, 0x5a, irqmask); | |
921 | ||
922 | /* | |
923 | * default to pci clock. make sure MA15/16 are set to output | |
924 | * to prevent drives having problems with 40-pin cables. Needed | |
925 | * for some drives such as IBM-DTLA which will not enter ready | |
926 | * state on reset when PDIAG is a input. | |
927 | */ | |
928 | ||
85cd7251 | 929 | pci_write_config_byte(dev, 0x5b, 0x23); |
a617c09f | 930 | |
fcc2f69a AC |
931 | /* |
932 | * HighPoint does this for HPT372A. | |
933 | * NOTE: This register is only writeable via I/O space. | |
934 | */ | |
935 | if (chip_table == &hpt372a) | |
936 | outb(0x0e, iobase + 0x9c); | |
85cd7251 | 937 | |
49bfbd38 SS |
938 | /* |
939 | * Some devices do not let this value be accessed via PCI space | |
940 | * according to the old driver. In addition we must use the value | |
941 | * from FN 0 on the HPT374. | |
942 | */ | |
73946f9f AC |
943 | |
944 | if (chip_table == &hpt374) { | |
945 | freq = hpt374_read_freq(dev); | |
946 | if (freq == 0) | |
947 | return -ENODEV; | |
948 | } else | |
949 | freq = inl(iobase + 0x90); | |
fcc2f69a | 950 | |
669a5db4 JG |
951 | if ((freq >> 12) != 0xABCDE) { |
952 | int i; | |
953 | u8 sr; | |
954 | u32 total = 0; | |
85cd7251 | 955 | |
8d7b1c70 | 956 | pr_warn("BIOS has not set timing clocks\n"); |
85cd7251 | 957 | |
669a5db4 | 958 | /* This is the process the HPT371 BIOS is reported to use */ |
49bfbd38 | 959 | for (i = 0; i < 128; i++) { |
669a5db4 | 960 | pci_read_config_byte(dev, 0x78, &sr); |
fcc2f69a | 961 | total += sr & 0x1FF; |
669a5db4 JG |
962 | udelay(15); |
963 | } | |
964 | freq = total / 128; | |
965 | } | |
966 | freq &= 0x1FF; | |
85cd7251 | 967 | |
669a5db4 JG |
968 | /* |
969 | * Turn the frequency check into a band and then find a timing | |
970 | * table to match it. | |
971 | */ | |
a617c09f | 972 | |
669a5db4 | 973 | clock_slot = hpt37x_clock_slot(freq, chip_table->base); |
fcc2f69a | 974 | if (chip_table->clocks[clock_slot] == NULL || prefer_dpll) { |
669a5db4 JG |
975 | /* |
976 | * We need to try PLL mode instead | |
fcc2f69a AC |
977 | * |
978 | * For non UDMA133 capable devices we should | |
979 | * use a 50MHz DPLL by choice | |
669a5db4 | 980 | */ |
fcc2f69a | 981 | unsigned int f_low, f_high; |
960c8a10 | 982 | int dpll, adjust; |
a617c09f | 983 | |
960c8a10 | 984 | /* Compute DPLL */ |
887125e3 | 985 | dpll = (ppi[0]->udma_mask & 0xC0) ? 3 : 2; |
a617c09f | 986 | |
960c8a10 | 987 | f_low = (MHz[clock_slot] * 48) / MHz[dpll]; |
fcc2f69a | 988 | f_high = f_low + 2; |
960c8a10 AC |
989 | if (clock_slot > 1) |
990 | f_high += 2; | |
fcc2f69a AC |
991 | |
992 | /* Select the DPLL clock. */ | |
993 | pci_write_config_byte(dev, 0x5b, 0x21); | |
49bfbd38 SS |
994 | pci_write_config_dword(dev, 0x5C, |
995 | (f_high << 16) | f_low | 0x100); | |
85cd7251 | 996 | |
49bfbd38 | 997 | for (adjust = 0; adjust < 8; adjust++) { |
669a5db4 JG |
998 | if (hpt37x_calibrate_dpll(dev)) |
999 | break; | |
49bfbd38 SS |
1000 | /* |
1001 | * See if it'll settle at a fractionally | |
1002 | * different clock | |
1003 | */ | |
64a81709 AC |
1004 | if (adjust & 1) |
1005 | f_low -= adjust >> 1; | |
1006 | else | |
1007 | f_high += adjust >> 1; | |
49bfbd38 SS |
1008 | pci_write_config_dword(dev, 0x5C, |
1009 | (f_high << 16) | f_low | 0x100); | |
669a5db4 JG |
1010 | } |
1011 | if (adjust == 8) { | |
8d7b1c70 | 1012 | pr_err("DPLL did not stabilize!\n"); |
669a5db4 JG |
1013 | return -ENODEV; |
1014 | } | |
960c8a10 | 1015 | if (dpll == 3) |
1626aeb8 | 1016 | private_data = (void *)hpt37x_timings_66; |
fcc2f69a | 1017 | else |
1626aeb8 | 1018 | private_data = (void *)hpt37x_timings_50; |
85cd7251 | 1019 | |
8d7b1c70 | 1020 | pr_info("bus clock %dMHz, using %dMHz DPLL\n", |
40d69ba0 | 1021 | MHz[clock_slot], MHz[dpll]); |
669a5db4 | 1022 | } else { |
1626aeb8 | 1023 | private_data = (void *)chip_table->clocks[clock_slot]; |
669a5db4 | 1024 | /* |
a4734468 AC |
1025 | * Perform a final fixup. Note that we will have used the |
1026 | * DPLL on the HPT372 which means we don't have to worry | |
1027 | * about lack of UDMA133 support on lower clocks | |
49bfbd38 | 1028 | */ |
85cd7251 | 1029 | |
887125e3 TH |
1030 | if (clock_slot < 2 && ppi[0] == &info_hpt370) |
1031 | ppi[0] = &info_hpt370_33; | |
1032 | if (clock_slot < 2 && ppi[0] == &info_hpt370a) | |
1033 | ppi[0] = &info_hpt370a_33; | |
40d69ba0 | 1034 | |
8d7b1c70 | 1035 | pr_info("%s using %dMHz bus clock\n", |
40d69ba0 | 1036 | chip_table->name, MHz[clock_slot]); |
669a5db4 | 1037 | } |
fcc2f69a | 1038 | |
669a5db4 | 1039 | /* Now kick off ATA set up */ |
1c5afdf7 | 1040 | return ata_pci_bmdma_init_one(dev, ppi, &hpt37x_sht, private_data, 0); |
669a5db4 JG |
1041 | } |
1042 | ||
2d2744fc JG |
1043 | static const struct pci_device_id hpt37x[] = { |
1044 | { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT366), }, | |
1045 | { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT371), }, | |
1046 | { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT372), }, | |
1047 | { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT374), }, | |
1048 | { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT302), }, | |
1049 | ||
1050 | { }, | |
669a5db4 JG |
1051 | }; |
1052 | ||
1053 | static struct pci_driver hpt37x_pci_driver = { | |
49bfbd38 | 1054 | .name = DRV_NAME, |
669a5db4 | 1055 | .id_table = hpt37x, |
49bfbd38 | 1056 | .probe = hpt37x_init_one, |
669a5db4 JG |
1057 | .remove = ata_pci_remove_one |
1058 | }; | |
1059 | ||
2fc75da0 | 1060 | module_pci_driver(hpt37x_pci_driver); |
669a5db4 | 1061 | |
669a5db4 JG |
1062 | MODULE_AUTHOR("Alan Cox"); |
1063 | MODULE_DESCRIPTION("low-level driver for the Highpoint HPT37x/30x"); | |
1064 | MODULE_LICENSE("GPL"); | |
1065 | MODULE_DEVICE_TABLE(pci, hpt37x); | |
1066 | MODULE_VERSION(DRV_VERSION); |