Commit | Line | Data |
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669a5db4 JG |
1 | /* |
2 | * Libata driver for the highpoint 37x and 30x UDMA66 ATA controllers. | |
3 | * | |
4 | * This driver is heavily based upon: | |
5 | * | |
6 | * linux/drivers/ide/pci/hpt366.c Version 0.36 April 25, 2003 | |
7 | * | |
8 | * Copyright (C) 1999-2003 Andre Hedrick <andre@linux-ide.org> | |
9 | * Portions Copyright (C) 2001 Sun Microsystems, Inc. | |
10 | * Portions Copyright (C) 2003 Red Hat Inc | |
265b7215 | 11 | * Portions Copyright (C) 2005-2009 MontaVista Software, Inc. |
669a5db4 JG |
12 | * |
13 | * TODO | |
d44a65f7 | 14 | * Look into engine reset on timeout errors. Should not be required. |
669a5db4 JG |
15 | */ |
16 | ||
17 | #include <linux/kernel.h> | |
18 | #include <linux/module.h> | |
19 | #include <linux/pci.h> | |
20 | #include <linux/init.h> | |
21 | #include <linux/blkdev.h> | |
22 | #include <linux/delay.h> | |
23 | #include <scsi/scsi_host.h> | |
24 | #include <linux/libata.h> | |
25 | ||
26 | #define DRV_NAME "pata_hpt37x" | |
1a1b172b | 27 | #define DRV_VERSION "0.6.15" |
669a5db4 JG |
28 | |
29 | struct hpt_clock { | |
30 | u8 xfer_speed; | |
31 | u32 timing; | |
32 | }; | |
33 | ||
34 | struct hpt_chip { | |
35 | const char *name; | |
36 | unsigned int base; | |
37 | struct hpt_clock const *clocks[4]; | |
38 | }; | |
39 | ||
40 | /* key for bus clock timings | |
41 | * bit | |
fd5e62e2 SS |
42 | * 0:3 data_high_time. Inactive time of DIOW_/DIOR_ for PIO and MW DMA. |
43 | * cycles = value + 1 | |
44 | * 4:8 data_low_time. Active time of DIOW_/DIOR_ for PIO and MW DMA. | |
45 | * cycles = value + 1 | |
46 | * 9:12 cmd_high_time. Inactive time of DIOW_/DIOR_ during task file | |
669a5db4 | 47 | * register access. |
fd5e62e2 | 48 | * 13:17 cmd_low_time. Active time of DIOW_/DIOR_ during task file |
669a5db4 | 49 | * register access. |
fd5e62e2 SS |
50 | * 18:20 udma_cycle_time. Clock cycles for UDMA xfer. |
51 | * 21 CLK frequency for UDMA: 0=ATA clock, 1=dual ATA clock. | |
52 | * 22:24 pre_high_time. Time to initialize 1st cycle for PIO and MW DMA xfer. | |
53 | * 25:27 cmd_pre_high_time. Time to initialize 1st PIO cycle for task file | |
669a5db4 | 54 | * register access. |
fd5e62e2 SS |
55 | * 28 UDMA enable. |
56 | * 29 DMA enable. | |
57 | * 30 PIO_MST enable. If set, the chip is in bus master mode during | |
58 | * PIO xfer. | |
59 | * 31 FIFO enable. Only for PIO. | |
669a5db4 JG |
60 | */ |
61 | ||
fcc2f69a AC |
62 | static struct hpt_clock hpt37x_timings_33[] = { |
63 | { XFER_UDMA_6, 0x12446231 }, /* 0x12646231 ?? */ | |
64 | { XFER_UDMA_5, 0x12446231 }, | |
65 | { XFER_UDMA_4, 0x12446231 }, | |
66 | { XFER_UDMA_3, 0x126c6231 }, | |
67 | { XFER_UDMA_2, 0x12486231 }, | |
68 | { XFER_UDMA_1, 0x124c6233 }, | |
69 | { XFER_UDMA_0, 0x12506297 }, | |
70 | ||
71 | { XFER_MW_DMA_2, 0x22406c31 }, | |
72 | { XFER_MW_DMA_1, 0x22406c33 }, | |
73 | { XFER_MW_DMA_0, 0x22406c97 }, | |
74 | ||
75 | { XFER_PIO_4, 0x06414e31 }, | |
76 | { XFER_PIO_3, 0x06414e42 }, | |
77 | { XFER_PIO_2, 0x06414e53 }, | |
78 | { XFER_PIO_1, 0x06814e93 }, | |
79 | { XFER_PIO_0, 0x06814ea7 } | |
669a5db4 JG |
80 | }; |
81 | ||
fcc2f69a AC |
82 | static struct hpt_clock hpt37x_timings_50[] = { |
83 | { XFER_UDMA_6, 0x12848242 }, | |
84 | { XFER_UDMA_5, 0x12848242 }, | |
85 | { XFER_UDMA_4, 0x12ac8242 }, | |
86 | { XFER_UDMA_3, 0x128c8242 }, | |
87 | { XFER_UDMA_2, 0x120c8242 }, | |
88 | { XFER_UDMA_1, 0x12148254 }, | |
89 | { XFER_UDMA_0, 0x121882ea }, | |
90 | ||
91 | { XFER_MW_DMA_2, 0x22808242 }, | |
92 | { XFER_MW_DMA_1, 0x22808254 }, | |
93 | { XFER_MW_DMA_0, 0x228082ea }, | |
94 | ||
95 | { XFER_PIO_4, 0x0a81f442 }, | |
96 | { XFER_PIO_3, 0x0a81f443 }, | |
97 | { XFER_PIO_2, 0x0a81f454 }, | |
98 | { XFER_PIO_1, 0x0ac1f465 }, | |
99 | { XFER_PIO_0, 0x0ac1f48a } | |
669a5db4 JG |
100 | }; |
101 | ||
fcc2f69a AC |
102 | static struct hpt_clock hpt37x_timings_66[] = { |
103 | { XFER_UDMA_6, 0x1c869c62 }, | |
104 | { XFER_UDMA_5, 0x1cae9c62 }, /* 0x1c8a9c62 */ | |
105 | { XFER_UDMA_4, 0x1c8a9c62 }, | |
106 | { XFER_UDMA_3, 0x1c8e9c62 }, | |
107 | { XFER_UDMA_2, 0x1c929c62 }, | |
108 | { XFER_UDMA_1, 0x1c9a9c62 }, | |
109 | { XFER_UDMA_0, 0x1c829c62 }, | |
110 | ||
111 | { XFER_MW_DMA_2, 0x2c829c62 }, | |
112 | { XFER_MW_DMA_1, 0x2c829c66 }, | |
113 | { XFER_MW_DMA_0, 0x2c829d2e }, | |
114 | ||
115 | { XFER_PIO_4, 0x0c829c62 }, | |
116 | { XFER_PIO_3, 0x0c829c84 }, | |
117 | { XFER_PIO_2, 0x0c829ca6 }, | |
118 | { XFER_PIO_1, 0x0d029d26 }, | |
119 | { XFER_PIO_0, 0x0d029d5e } | |
669a5db4 JG |
120 | }; |
121 | ||
669a5db4 JG |
122 | |
123 | static const struct hpt_chip hpt370 = { | |
124 | "HPT370", | |
125 | 48, | |
126 | { | |
fcc2f69a | 127 | hpt37x_timings_33, |
669a5db4 JG |
128 | NULL, |
129 | NULL, | |
a4734468 | 130 | NULL |
669a5db4 JG |
131 | } |
132 | }; | |
133 | ||
134 | static const struct hpt_chip hpt370a = { | |
135 | "HPT370A", | |
136 | 48, | |
137 | { | |
fcc2f69a | 138 | hpt37x_timings_33, |
669a5db4 | 139 | NULL, |
fcc2f69a | 140 | hpt37x_timings_50, |
a4734468 | 141 | NULL |
669a5db4 JG |
142 | } |
143 | }; | |
144 | ||
145 | static const struct hpt_chip hpt372 = { | |
146 | "HPT372", | |
147 | 55, | |
148 | { | |
fcc2f69a | 149 | hpt37x_timings_33, |
669a5db4 | 150 | NULL, |
fcc2f69a AC |
151 | hpt37x_timings_50, |
152 | hpt37x_timings_66 | |
669a5db4 JG |
153 | } |
154 | }; | |
155 | ||
156 | static const struct hpt_chip hpt302 = { | |
157 | "HPT302", | |
158 | 66, | |
159 | { | |
fcc2f69a | 160 | hpt37x_timings_33, |
669a5db4 | 161 | NULL, |
fcc2f69a AC |
162 | hpt37x_timings_50, |
163 | hpt37x_timings_66 | |
669a5db4 JG |
164 | } |
165 | }; | |
166 | ||
167 | static const struct hpt_chip hpt371 = { | |
168 | "HPT371", | |
169 | 66, | |
170 | { | |
fcc2f69a | 171 | hpt37x_timings_33, |
669a5db4 | 172 | NULL, |
fcc2f69a AC |
173 | hpt37x_timings_50, |
174 | hpt37x_timings_66 | |
669a5db4 JG |
175 | } |
176 | }; | |
177 | ||
178 | static const struct hpt_chip hpt372a = { | |
179 | "HPT372A", | |
180 | 66, | |
181 | { | |
fcc2f69a | 182 | hpt37x_timings_33, |
669a5db4 | 183 | NULL, |
fcc2f69a AC |
184 | hpt37x_timings_50, |
185 | hpt37x_timings_66 | |
669a5db4 JG |
186 | } |
187 | }; | |
188 | ||
189 | static const struct hpt_chip hpt374 = { | |
190 | "HPT374", | |
191 | 48, | |
192 | { | |
fcc2f69a | 193 | hpt37x_timings_33, |
669a5db4 JG |
194 | NULL, |
195 | NULL, | |
196 | NULL | |
197 | } | |
198 | }; | |
199 | ||
200 | /** | |
201 | * hpt37x_find_mode - reset the hpt37x bus | |
202 | * @ap: ATA port | |
203 | * @speed: transfer mode | |
204 | * | |
205 | * Return the 32bit register programming information for this channel | |
206 | * that matches the speed provided. | |
207 | */ | |
85cd7251 | 208 | |
669a5db4 JG |
209 | static u32 hpt37x_find_mode(struct ata_port *ap, int speed) |
210 | { | |
211 | struct hpt_clock *clocks = ap->host->private_data; | |
85cd7251 | 212 | |
669a5db4 JG |
213 | while(clocks->xfer_speed) { |
214 | if (clocks->xfer_speed == speed) | |
215 | return clocks->timing; | |
216 | clocks++; | |
217 | } | |
218 | BUG(); | |
219 | return 0xffffffffU; /* silence compiler warning */ | |
220 | } | |
221 | ||
222 | static int hpt_dma_blacklisted(const struct ata_device *dev, char *modestr, const char *list[]) | |
223 | { | |
8bfa79fc | 224 | unsigned char model_num[ATA_ID_PROD_LEN + 1]; |
669a5db4 JG |
225 | int i = 0; |
226 | ||
8bfa79fc | 227 | ata_id_c_string(dev->id, model_num, ATA_ID_PROD, sizeof(model_num)); |
669a5db4 | 228 | |
8bfa79fc TH |
229 | while (list[i] != NULL) { |
230 | if (!strcmp(list[i], model_num)) { | |
85cd7251 | 231 | printk(KERN_WARNING DRV_NAME ": %s is not supported for %s.\n", |
669a5db4 JG |
232 | modestr, list[i]); |
233 | return 1; | |
234 | } | |
235 | i++; | |
236 | } | |
237 | return 0; | |
238 | } | |
239 | ||
240 | static const char *bad_ata33[] = { | |
241 | "Maxtor 92720U8", "Maxtor 92040U6", "Maxtor 91360U4", "Maxtor 91020U3", "Maxtor 90845U3", "Maxtor 90650U2", | |
242 | "Maxtor 91360D8", "Maxtor 91190D7", "Maxtor 91020D6", "Maxtor 90845D5", "Maxtor 90680D4", "Maxtor 90510D3", "Maxtor 90340D2", | |
243 | "Maxtor 91152D8", "Maxtor 91008D7", "Maxtor 90845D6", "Maxtor 90840D6", "Maxtor 90720D5", "Maxtor 90648D5", "Maxtor 90576D4", | |
244 | "Maxtor 90510D4", | |
245 | "Maxtor 90432D3", "Maxtor 90288D2", "Maxtor 90256D2", | |
246 | "Maxtor 91000D8", "Maxtor 90910D8", "Maxtor 90875D7", "Maxtor 90840D7", "Maxtor 90750D6", "Maxtor 90625D5", "Maxtor 90500D4", | |
247 | "Maxtor 91728D8", "Maxtor 91512D7", "Maxtor 91303D6", "Maxtor 91080D5", "Maxtor 90845D4", "Maxtor 90680D4", "Maxtor 90648D3", "Maxtor 90432D2", | |
248 | NULL | |
249 | }; | |
250 | ||
251 | static const char *bad_ata100_5[] = { | |
252 | "IBM-DTLA-307075", | |
253 | "IBM-DTLA-307060", | |
254 | "IBM-DTLA-307045", | |
255 | "IBM-DTLA-307030", | |
256 | "IBM-DTLA-307020", | |
257 | "IBM-DTLA-307015", | |
258 | "IBM-DTLA-305040", | |
259 | "IBM-DTLA-305030", | |
260 | "IBM-DTLA-305020", | |
261 | "IC35L010AVER07-0", | |
262 | "IC35L020AVER07-0", | |
263 | "IC35L030AVER07-0", | |
264 | "IC35L040AVER07-0", | |
265 | "IC35L060AVER07-0", | |
266 | "WDC AC310200R", | |
267 | NULL | |
268 | }; | |
269 | ||
270 | /** | |
271 | * hpt370_filter - mode selection filter | |
669a5db4 JG |
272 | * @adev: ATA device |
273 | * | |
274 | * Block UDMA on devices that cause trouble with this controller. | |
275 | */ | |
85cd7251 | 276 | |
a76b62ca | 277 | static unsigned long hpt370_filter(struct ata_device *adev, unsigned long mask) |
669a5db4 | 278 | { |
6929da44 | 279 | if (adev->class == ATA_DEV_ATA) { |
669a5db4 JG |
280 | if (hpt_dma_blacklisted(adev, "UDMA", bad_ata33)) |
281 | mask &= ~ATA_MASK_UDMA; | |
282 | if (hpt_dma_blacklisted(adev, "UDMA100", bad_ata100_5)) | |
6ddd6861 | 283 | mask &= ~(0xE0 << ATA_SHIFT_UDMA); |
669a5db4 | 284 | } |
c7087652 | 285 | return mask; |
669a5db4 JG |
286 | } |
287 | ||
288 | /** | |
289 | * hpt370a_filter - mode selection filter | |
669a5db4 JG |
290 | * @adev: ATA device |
291 | * | |
292 | * Block UDMA on devices that cause trouble with this controller. | |
293 | */ | |
85cd7251 | 294 | |
a76b62ca | 295 | static unsigned long hpt370a_filter(struct ata_device *adev, unsigned long mask) |
669a5db4 | 296 | { |
73946f9f | 297 | if (adev->class == ATA_DEV_ATA) { |
669a5db4 | 298 | if (hpt_dma_blacklisted(adev, "UDMA100", bad_ata100_5)) |
6ddd6861 | 299 | mask &= ~(0xE0 << ATA_SHIFT_UDMA); |
669a5db4 | 300 | } |
c7087652 | 301 | return mask; |
669a5db4 | 302 | } |
85cd7251 | 303 | |
9e87be9e BZ |
304 | /** |
305 | * hpt37x_cable_detect - Detect the cable type | |
306 | * @ap: ATA port to detect on | |
307 | * | |
308 | * Return the cable type attached to this port | |
309 | */ | |
310 | ||
311 | static int hpt37x_cable_detect(struct ata_port *ap) | |
312 | { | |
313 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); | |
314 | u8 scr2, ata66; | |
315 | ||
316 | pci_read_config_byte(pdev, 0x5B, &scr2); | |
317 | pci_write_config_byte(pdev, 0x5B, scr2 & ~0x01); | |
10a9c969 BZ |
318 | |
319 | udelay(10); /* debounce */ | |
320 | ||
9e87be9e BZ |
321 | /* Cable register now active */ |
322 | pci_read_config_byte(pdev, 0x5A, &ata66); | |
323 | /* Restore state */ | |
324 | pci_write_config_byte(pdev, 0x5B, scr2); | |
325 | ||
326 | if (ata66 & (2 >> ap->port_no)) | |
327 | return ATA_CBL_PATA40; | |
328 | else | |
329 | return ATA_CBL_PATA80; | |
330 | } | |
331 | ||
332 | /** | |
333 | * hpt374_fn1_cable_detect - Detect the cable type | |
334 | * @ap: ATA port to detect on | |
335 | * | |
336 | * Return the cable type attached to this port | |
337 | */ | |
338 | ||
339 | static int hpt374_fn1_cable_detect(struct ata_port *ap) | |
340 | { | |
341 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); | |
342 | unsigned int mcrbase = 0x50 + 4 * ap->port_no; | |
343 | u16 mcr3; | |
344 | u8 ata66; | |
345 | ||
346 | /* Do the extra channel work */ | |
347 | pci_read_config_word(pdev, mcrbase + 2, &mcr3); | |
348 | /* Set bit 15 of 0x52 to enable TCBLID as input */ | |
349 | pci_write_config_word(pdev, mcrbase + 2, mcr3 | 0x8000); | |
350 | pci_read_config_byte(pdev, 0x5A, &ata66); | |
351 | /* Reset TCBLID/FCBLID to output */ | |
352 | pci_write_config_word(pdev, mcrbase + 2, mcr3); | |
353 | ||
354 | if (ata66 & (2 >> ap->port_no)) | |
355 | return ATA_CBL_PATA40; | |
356 | else | |
357 | return ATA_CBL_PATA80; | |
358 | } | |
359 | ||
669a5db4 JG |
360 | /** |
361 | * hpt37x_pre_reset - reset the hpt37x bus | |
cc0680a5 | 362 | * @link: ATA link to reset |
d4b2bab4 | 363 | * @deadline: deadline jiffies for the operation |
669a5db4 | 364 | * |
ab81a505 | 365 | * Perform the initial reset handling for the HPT37x. |
669a5db4 | 366 | */ |
85cd7251 | 367 | |
cc0680a5 | 368 | static int hpt37x_pre_reset(struct ata_link *link, unsigned long deadline) |
669a5db4 | 369 | { |
cc0680a5 | 370 | struct ata_port *ap = link->ap; |
669a5db4 | 371 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); |
b5bf24b9 AC |
372 | static const struct pci_bits hpt37x_enable_bits[] = { |
373 | { 0x50, 1, 0x04, 0x04 }, | |
374 | { 0x54, 1, 0x04, 0x04 } | |
375 | }; | |
376 | if (!pci_test_config_bits(pdev, &hpt37x_enable_bits[ap->port_no])) | |
377 | return -ENOENT; | |
f20b16ff | 378 | |
669a5db4 | 379 | /* Reset the state machine */ |
fcc2f69a | 380 | pci_write_config_byte(pdev, 0x50 + 4 * ap->port_no, 0x37); |
669a5db4 | 381 | udelay(100); |
85cd7251 | 382 | |
9363c382 | 383 | return ata_sff_prereset(link, deadline); |
669a5db4 JG |
384 | } |
385 | ||
1a1b172b SS |
386 | static void hpt370_set_mode(struct ata_port *ap, struct ata_device *adev, |
387 | u8 mode) | |
669a5db4 JG |
388 | { |
389 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); | |
390 | u32 addr1, addr2; | |
1a1b172b | 391 | u32 reg, timing, mask; |
669a5db4 JG |
392 | u8 fast; |
393 | ||
394 | addr1 = 0x40 + 4 * (adev->devno + 2 * ap->port_no); | |
395 | addr2 = 0x51 + 4 * ap->port_no; | |
85cd7251 | 396 | |
669a5db4 JG |
397 | /* Fast interrupt prediction disable, hold off interrupt disable */ |
398 | pci_read_config_byte(pdev, addr2, &fast); | |
399 | fast &= ~0x02; | |
400 | fast |= 0x01; | |
401 | pci_write_config_byte(pdev, addr2, fast); | |
85cd7251 | 402 | |
1a1b172b SS |
403 | /* Determine timing mask and find matching mode entry */ |
404 | if (mode < XFER_MW_DMA_0) | |
405 | mask = 0xcfc3ffff; | |
406 | else if (mode < XFER_UDMA_0) | |
407 | mask = 0x31c001ff; | |
408 | else | |
409 | mask = 0x303c0000; | |
410 | ||
411 | timing = hpt37x_find_mode(ap, mode); | |
412 | ||
669a5db4 | 413 | pci_read_config_dword(pdev, addr1, ®); |
1a1b172b SS |
414 | reg = (reg & ~mask) | (timing & mask); |
415 | pci_write_config_dword(pdev, addr1, reg); | |
416 | } | |
417 | /** | |
418 | * hpt370_set_piomode - PIO setup | |
419 | * @ap: ATA interface | |
420 | * @adev: device on the interface | |
421 | * | |
422 | * Perform PIO mode setup. | |
423 | */ | |
424 | ||
425 | static void hpt370_set_piomode(struct ata_port *ap, struct ata_device *adev) | |
426 | { | |
427 | hpt370_set_mode(ap, adev, adev->pio_mode); | |
669a5db4 JG |
428 | } |
429 | ||
430 | /** | |
431 | * hpt370_set_dmamode - DMA timing setup | |
432 | * @ap: ATA interface | |
433 | * @adev: Device being configured | |
434 | * | |
1a1b172b | 435 | * Set up the channel for MWDMA or UDMA modes. |
669a5db4 | 436 | */ |
85cd7251 | 437 | |
669a5db4 JG |
438 | static void hpt370_set_dmamode(struct ata_port *ap, struct ata_device *adev) |
439 | { | |
1a1b172b | 440 | hpt370_set_mode(ap, adev, adev->dma_mode); |
669a5db4 JG |
441 | } |
442 | ||
669a5db4 JG |
443 | /** |
444 | * hpt370_bmdma_end - DMA engine stop | |
445 | * @qc: ATA command | |
446 | * | |
447 | * Work around the HPT370 DMA engine. | |
448 | */ | |
85cd7251 | 449 | |
669a5db4 JG |
450 | static void hpt370_bmdma_stop(struct ata_queued_cmd *qc) |
451 | { | |
452 | struct ata_port *ap = qc->ap; | |
453 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); | |
0d5ff566 | 454 | void __iomem *bmdma = ap->ioaddr.bmdma_addr; |
56f46f8c SS |
455 | u8 dma_stat = ioread8(bmdma + ATA_DMA_STATUS); |
456 | u8 dma_cmd; | |
85cd7251 | 457 | |
56f46f8c | 458 | if (dma_stat & ATA_DMA_ACTIVE) { |
669a5db4 | 459 | udelay(20); |
56f46f8c | 460 | dma_stat = ioread8(bmdma + ATA_DMA_STATUS); |
669a5db4 | 461 | } |
56f46f8c | 462 | if (dma_stat & ATA_DMA_ACTIVE) { |
669a5db4 JG |
463 | /* Clear the engine */ |
464 | pci_write_config_byte(pdev, 0x50 + 4 * ap->port_no, 0x37); | |
465 | udelay(10); | |
466 | /* Stop DMA */ | |
56f46f8c SS |
467 | dma_cmd = ioread8(bmdma + ATA_DMA_CMD); |
468 | iowrite8(dma_cmd & ~ATA_DMA_START, bmdma + ATA_DMA_CMD); | |
669a5db4 | 469 | /* Clear Error */ |
56f46f8c SS |
470 | dma_stat = ioread8(bmdma + ATA_DMA_STATUS); |
471 | iowrite8(dma_stat | ATA_DMA_INTR | ATA_DMA_ERR, | |
472 | bmdma + ATA_DMA_STATUS); | |
669a5db4 JG |
473 | /* Clear the engine */ |
474 | pci_write_config_byte(pdev, 0x50 + 4 * ap->port_no, 0x37); | |
475 | udelay(10); | |
476 | } | |
477 | ata_bmdma_stop(qc); | |
478 | } | |
479 | ||
1a1b172b SS |
480 | static void hpt372_set_mode(struct ata_port *ap, struct ata_device *adev, |
481 | u8 mode) | |
669a5db4 JG |
482 | { |
483 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); | |
484 | u32 addr1, addr2; | |
1a1b172b | 485 | u32 reg, timing, mask; |
669a5db4 JG |
486 | u8 fast; |
487 | ||
488 | addr1 = 0x40 + 4 * (adev->devno + 2 * ap->port_no); | |
489 | addr2 = 0x51 + 4 * ap->port_no; | |
85cd7251 | 490 | |
669a5db4 JG |
491 | /* Fast interrupt prediction disable, hold off interrupt disable */ |
492 | pci_read_config_byte(pdev, addr2, &fast); | |
493 | fast &= ~0x07; | |
494 | pci_write_config_byte(pdev, addr2, fast); | |
85cd7251 | 495 | |
1a1b172b SS |
496 | /* Determine timing mask and find matching mode entry */ |
497 | if (mode < XFER_MW_DMA_0) | |
498 | mask = 0xcfc3ffff; | |
499 | else if (mode < XFER_UDMA_0) | |
500 | mask = 0x31c001ff; | |
501 | else | |
502 | mask = 0x303c0000; | |
503 | ||
504 | timing = hpt37x_find_mode(ap, mode); | |
505 | ||
669a5db4 | 506 | pci_read_config_dword(pdev, addr1, ®); |
1a1b172b SS |
507 | reg = (reg & ~mask) | (timing & mask); |
508 | pci_write_config_dword(pdev, addr1, reg); | |
509 | } | |
85cd7251 | 510 | |
1a1b172b SS |
511 | /** |
512 | * hpt372_set_piomode - PIO setup | |
513 | * @ap: ATA interface | |
514 | * @adev: device on the interface | |
515 | * | |
516 | * Perform PIO mode setup. | |
517 | */ | |
518 | ||
519 | static void hpt372_set_piomode(struct ata_port *ap, struct ata_device *adev) | |
520 | { | |
521 | hpt372_set_mode(ap, adev, adev->pio_mode); | |
669a5db4 JG |
522 | } |
523 | ||
524 | /** | |
525 | * hpt372_set_dmamode - DMA timing setup | |
526 | * @ap: ATA interface | |
527 | * @adev: Device being configured | |
528 | * | |
1a1b172b | 529 | * Set up the channel for MWDMA or UDMA modes. |
669a5db4 | 530 | */ |
85cd7251 | 531 | |
669a5db4 JG |
532 | static void hpt372_set_dmamode(struct ata_port *ap, struct ata_device *adev) |
533 | { | |
1a1b172b | 534 | hpt372_set_mode(ap, adev, adev->dma_mode); |
669a5db4 JG |
535 | } |
536 | ||
537 | /** | |
538 | * hpt37x_bmdma_end - DMA engine stop | |
539 | * @qc: ATA command | |
540 | * | |
541 | * Clean up after the HPT372 and later DMA engine | |
542 | */ | |
85cd7251 | 543 | |
669a5db4 JG |
544 | static void hpt37x_bmdma_stop(struct ata_queued_cmd *qc) |
545 | { | |
546 | struct ata_port *ap = qc->ap; | |
547 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); | |
6929da44 | 548 | int mscreg = 0x50 + 4 * ap->port_no; |
669a5db4 | 549 | u8 bwsr_stat, msc_stat; |
85cd7251 | 550 | |
669a5db4 JG |
551 | pci_read_config_byte(pdev, 0x6A, &bwsr_stat); |
552 | pci_read_config_byte(pdev, mscreg, &msc_stat); | |
553 | if (bwsr_stat & (1 << ap->port_no)) | |
554 | pci_write_config_byte(pdev, mscreg, msc_stat | 0x30); | |
555 | ata_bmdma_stop(qc); | |
556 | } | |
557 | ||
558 | ||
559 | static struct scsi_host_template hpt37x_sht = { | |
68d1d07b | 560 | ATA_BMDMA_SHT(DRV_NAME), |
669a5db4 JG |
561 | }; |
562 | ||
563 | /* | |
564 | * Configuration for HPT370 | |
565 | */ | |
85cd7251 | 566 | |
669a5db4 | 567 | static struct ata_port_operations hpt370_port_ops = { |
029cfd6b | 568 | .inherits = &ata_bmdma_port_ops, |
669a5db4 | 569 | |
669a5db4 | 570 | .bmdma_stop = hpt370_bmdma_stop, |
669a5db4 | 571 | |
029cfd6b | 572 | .mode_filter = hpt370_filter, |
9e87be9e | 573 | .cable_detect = hpt37x_cable_detect, |
029cfd6b TH |
574 | .set_piomode = hpt370_set_piomode, |
575 | .set_dmamode = hpt370_set_dmamode, | |
a1efdaba | 576 | .prereset = hpt37x_pre_reset, |
85cd7251 | 577 | }; |
669a5db4 JG |
578 | |
579 | /* | |
580 | * Configuration for HPT370A. Close to 370 but less filters | |
581 | */ | |
85cd7251 | 582 | |
669a5db4 | 583 | static struct ata_port_operations hpt370a_port_ops = { |
029cfd6b | 584 | .inherits = &hpt370_port_ops, |
669a5db4 | 585 | .mode_filter = hpt370a_filter, |
85cd7251 | 586 | }; |
669a5db4 JG |
587 | |
588 | /* | |
589 | * Configuration for HPT372, HPT371, HPT302. Slightly different PIO | |
590 | * and DMA mode setting functionality. | |
591 | */ | |
85cd7251 | 592 | |
669a5db4 | 593 | static struct ata_port_operations hpt372_port_ops = { |
029cfd6b | 594 | .inherits = &ata_bmdma_port_ops, |
669a5db4 | 595 | |
669a5db4 | 596 | .bmdma_stop = hpt37x_bmdma_stop, |
669a5db4 | 597 | |
9e87be9e | 598 | .cable_detect = hpt37x_cable_detect, |
029cfd6b TH |
599 | .set_piomode = hpt372_set_piomode, |
600 | .set_dmamode = hpt372_set_dmamode, | |
a1efdaba | 601 | .prereset = hpt37x_pre_reset, |
85cd7251 | 602 | }; |
669a5db4 JG |
603 | |
604 | /* | |
605 | * Configuration for HPT374. Mode setting works like 372 and friends | |
a1efdaba | 606 | * but we have a different cable detection procedure for function 1. |
669a5db4 | 607 | */ |
85cd7251 | 608 | |
a1efdaba | 609 | static struct ata_port_operations hpt374_fn1_port_ops = { |
029cfd6b | 610 | .inherits = &hpt372_port_ops, |
9e87be9e | 611 | .cable_detect = hpt374_fn1_cable_detect, |
ab81a505 | 612 | .prereset = hpt37x_pre_reset, |
85cd7251 | 613 | }; |
669a5db4 JG |
614 | |
615 | /** | |
ad452d64 | 616 | * hpt37x_clock_slot - Turn timing to PC clock entry |
669a5db4 JG |
617 | * @freq: Reported frequency timing |
618 | * @base: Base timing | |
619 | * | |
620 | * Turn the timing data intoa clock slot (0 for 33, 1 for 40, 2 for 50 | |
621 | * and 3 for 66Mhz) | |
622 | */ | |
85cd7251 | 623 | |
669a5db4 JG |
624 | static int hpt37x_clock_slot(unsigned int freq, unsigned int base) |
625 | { | |
626 | unsigned int f = (base * freq) / 192; /* Mhz */ | |
627 | if (f < 40) | |
628 | return 0; /* 33Mhz slot */ | |
629 | if (f < 45) | |
630 | return 1; /* 40Mhz slot */ | |
631 | if (f < 55) | |
632 | return 2; /* 50Mhz slot */ | |
633 | return 3; /* 60Mhz slot */ | |
634 | } | |
635 | ||
636 | /** | |
637 | * hpt37x_calibrate_dpll - Calibrate the DPLL loop | |
85cd7251 | 638 | * @dev: PCI device |
669a5db4 JG |
639 | * |
640 | * Perform a calibration cycle on the HPT37x DPLL. Returns 1 if this | |
641 | * succeeds | |
642 | */ | |
643 | ||
644 | static int hpt37x_calibrate_dpll(struct pci_dev *dev) | |
645 | { | |
646 | u8 reg5b; | |
647 | u32 reg5c; | |
648 | int tries; | |
85cd7251 | 649 | |
669a5db4 JG |
650 | for(tries = 0; tries < 0x5000; tries++) { |
651 | udelay(50); | |
652 | pci_read_config_byte(dev, 0x5b, ®5b); | |
653 | if (reg5b & 0x80) { | |
654 | /* See if it stays set */ | |
655 | for(tries = 0; tries < 0x1000; tries ++) { | |
656 | pci_read_config_byte(dev, 0x5b, ®5b); | |
657 | /* Failed ? */ | |
658 | if ((reg5b & 0x80) == 0) | |
659 | return 0; | |
660 | } | |
661 | /* Turn off tuning, we have the DPLL set */ | |
662 | pci_read_config_dword(dev, 0x5c, ®5c); | |
663 | pci_write_config_dword(dev, 0x5c, reg5c & ~ 0x100); | |
664 | return 1; | |
665 | } | |
666 | } | |
667 | /* Never went stable */ | |
668 | return 0; | |
669 | } | |
73946f9f AC |
670 | |
671 | static u32 hpt374_read_freq(struct pci_dev *pdev) | |
672 | { | |
673 | u32 freq; | |
674 | unsigned long io_base = pci_resource_start(pdev, 4); | |
675 | if (PCI_FUNC(pdev->devfn) & 1) { | |
40f46f17 AM |
676 | struct pci_dev *pdev_0; |
677 | ||
678 | pdev_0 = pci_get_slot(pdev->bus, pdev->devfn - 1); | |
73946f9f AC |
679 | /* Someone hot plugged the controller on us ? */ |
680 | if (pdev_0 == NULL) | |
681 | return 0; | |
682 | io_base = pci_resource_start(pdev_0, 4); | |
683 | freq = inl(io_base + 0x90); | |
684 | pci_dev_put(pdev_0); | |
40f46f17 | 685 | } else |
73946f9f AC |
686 | freq = inl(io_base + 0x90); |
687 | return freq; | |
688 | } | |
689 | ||
669a5db4 JG |
690 | /** |
691 | * hpt37x_init_one - Initialise an HPT37X/302 | |
692 | * @dev: PCI device | |
693 | * @id: Entry in match table | |
694 | * | |
695 | * Initialise an HPT37x device. There are some interesting complications | |
696 | * here. Firstly the chip may report 366 and be one of several variants. | |
697 | * Secondly all the timings depend on the clock for the chip which we must | |
698 | * detect and look up | |
699 | * | |
700 | * This is the known chip mappings. It may be missing a couple of later | |
701 | * releases. | |
702 | * | |
703 | * Chip version PCI Rev Notes | |
704 | * HPT366 4 (HPT366) 0 Other driver | |
705 | * HPT366 4 (HPT366) 1 Other driver | |
706 | * HPT368 4 (HPT366) 2 Other driver | |
707 | * HPT370 4 (HPT366) 3 UDMA100 | |
708 | * HPT370A 4 (HPT366) 4 UDMA100 | |
709 | * HPT372 4 (HPT366) 5 UDMA133 (1) | |
710 | * HPT372N 4 (HPT366) 6 Other driver | |
711 | * HPT372A 5 (HPT372) 1 UDMA133 (1) | |
712 | * HPT372N 5 (HPT372) 2 Other driver | |
713 | * HPT302 6 (HPT302) 1 UDMA133 | |
714 | * HPT302N 6 (HPT302) 2 Other driver | |
715 | * HPT371 7 (HPT371) * UDMA133 | |
716 | * HPT374 8 (HPT374) * UDMA133 4 channel | |
717 | * HPT372N 9 (HPT372N) * Other driver | |
718 | * | |
719 | * (1) UDMA133 support depends on the bus clock | |
720 | */ | |
85cd7251 | 721 | |
669a5db4 JG |
722 | static int hpt37x_init_one(struct pci_dev *dev, const struct pci_device_id *id) |
723 | { | |
724 | /* HPT370 - UDMA100 */ | |
1626aeb8 | 725 | static const struct ata_port_info info_hpt370 = { |
1d2808fd | 726 | .flags = ATA_FLAG_SLAVE_POSS, |
14bdef98 EIB |
727 | .pio_mask = ATA_PIO4, |
728 | .mwdma_mask = ATA_MWDMA2, | |
bf6263a8 | 729 | .udma_mask = ATA_UDMA5, |
669a5db4 JG |
730 | .port_ops = &hpt370_port_ops |
731 | }; | |
732 | /* HPT370A - UDMA100 */ | |
1626aeb8 | 733 | static const struct ata_port_info info_hpt370a = { |
1d2808fd | 734 | .flags = ATA_FLAG_SLAVE_POSS, |
14bdef98 EIB |
735 | .pio_mask = ATA_PIO4, |
736 | .mwdma_mask = ATA_MWDMA2, | |
bf6263a8 | 737 | .udma_mask = ATA_UDMA5, |
669a5db4 JG |
738 | .port_ops = &hpt370a_port_ops |
739 | }; | |
fcc2f69a | 740 | /* HPT370 - UDMA100 */ |
1626aeb8 | 741 | static const struct ata_port_info info_hpt370_33 = { |
1d2808fd | 742 | .flags = ATA_FLAG_SLAVE_POSS, |
14bdef98 EIB |
743 | .pio_mask = ATA_PIO4, |
744 | .mwdma_mask = ATA_MWDMA2, | |
73946f9f | 745 | .udma_mask = ATA_UDMA5, |
fcc2f69a AC |
746 | .port_ops = &hpt370_port_ops |
747 | }; | |
748 | /* HPT370A - UDMA100 */ | |
1626aeb8 | 749 | static const struct ata_port_info info_hpt370a_33 = { |
1d2808fd | 750 | .flags = ATA_FLAG_SLAVE_POSS, |
14bdef98 EIB |
751 | .pio_mask = ATA_PIO4, |
752 | .mwdma_mask = ATA_MWDMA2, | |
73946f9f | 753 | .udma_mask = ATA_UDMA5, |
fcc2f69a AC |
754 | .port_ops = &hpt370a_port_ops |
755 | }; | |
669a5db4 | 756 | /* HPT371, 372 and friends - UDMA133 */ |
1626aeb8 | 757 | static const struct ata_port_info info_hpt372 = { |
1d2808fd | 758 | .flags = ATA_FLAG_SLAVE_POSS, |
14bdef98 EIB |
759 | .pio_mask = ATA_PIO4, |
760 | .mwdma_mask = ATA_MWDMA2, | |
bf6263a8 | 761 | .udma_mask = ATA_UDMA6, |
669a5db4 JG |
762 | .port_ops = &hpt372_port_ops |
763 | }; | |
a1efdaba TH |
764 | /* HPT374 - UDMA100, function 1 uses different prereset method */ |
765 | static const struct ata_port_info info_hpt374_fn0 = { | |
766 | .flags = ATA_FLAG_SLAVE_POSS, | |
14bdef98 EIB |
767 | .pio_mask = ATA_PIO4, |
768 | .mwdma_mask = ATA_MWDMA2, | |
a1efdaba TH |
769 | .udma_mask = ATA_UDMA5, |
770 | .port_ops = &hpt372_port_ops | |
771 | }; | |
772 | static const struct ata_port_info info_hpt374_fn1 = { | |
1d2808fd | 773 | .flags = ATA_FLAG_SLAVE_POSS, |
14bdef98 EIB |
774 | .pio_mask = ATA_PIO4, |
775 | .mwdma_mask = ATA_MWDMA2, | |
bf6263a8 | 776 | .udma_mask = ATA_UDMA5, |
a1efdaba | 777 | .port_ops = &hpt374_fn1_port_ops |
669a5db4 JG |
778 | }; |
779 | ||
780 | static const int MHz[4] = { 33, 40, 50, 66 }; | |
1626aeb8 | 781 | void *private_data = NULL; |
887125e3 | 782 | const struct ata_port_info *ppi[] = { NULL, NULL }; |
89d3b360 | 783 | u8 rev = dev->revision; |
669a5db4 | 784 | u8 irqmask; |
fcc2f69a | 785 | u8 mcr1; |
669a5db4 | 786 | u32 freq; |
fcc2f69a | 787 | int prefer_dpll = 1; |
a617c09f | 788 | |
fcc2f69a | 789 | unsigned long iobase = pci_resource_start(dev, 4); |
669a5db4 JG |
790 | |
791 | const struct hpt_chip *chip_table; | |
792 | int clock_slot; | |
f08048e9 TH |
793 | int rc; |
794 | ||
795 | rc = pcim_enable_device(dev); | |
796 | if (rc) | |
797 | return rc; | |
669a5db4 | 798 | |
669a5db4 JG |
799 | if (dev->device == PCI_DEVICE_ID_TTI_HPT366) { |
800 | /* May be a later chip in disguise. Check */ | |
801 | /* Older chips are in the HPT366 driver. Ignore them */ | |
89d3b360 | 802 | if (rev < 3) |
669a5db4 JG |
803 | return -ENODEV; |
804 | /* N series chips have their own driver. Ignore */ | |
89d3b360 | 805 | if (rev == 6) |
669a5db4 JG |
806 | return -ENODEV; |
807 | ||
89d3b360 | 808 | switch(rev) { |
669a5db4 | 809 | case 3: |
887125e3 | 810 | ppi[0] = &info_hpt370; |
669a5db4 | 811 | chip_table = &hpt370; |
fcc2f69a | 812 | prefer_dpll = 0; |
669a5db4 JG |
813 | break; |
814 | case 4: | |
887125e3 | 815 | ppi[0] = &info_hpt370a; |
669a5db4 | 816 | chip_table = &hpt370a; |
fcc2f69a | 817 | prefer_dpll = 0; |
669a5db4 JG |
818 | break; |
819 | case 5: | |
887125e3 | 820 | ppi[0] = &info_hpt372; |
669a5db4 JG |
821 | chip_table = &hpt372; |
822 | break; | |
823 | default: | |
89d3b360 SS |
824 | printk(KERN_ERR "pata_hpt37x: Unknown HPT366 " |
825 | "subtype, please report (%d).\n", rev); | |
669a5db4 JG |
826 | return -ENODEV; |
827 | } | |
828 | } else { | |
829 | switch(dev->device) { | |
830 | case PCI_DEVICE_ID_TTI_HPT372: | |
831 | /* 372N if rev >= 2*/ | |
89d3b360 | 832 | if (rev >= 2) |
669a5db4 | 833 | return -ENODEV; |
887125e3 | 834 | ppi[0] = &info_hpt372; |
669a5db4 JG |
835 | chip_table = &hpt372a; |
836 | break; | |
837 | case PCI_DEVICE_ID_TTI_HPT302: | |
838 | /* 302N if rev > 1 */ | |
89d3b360 | 839 | if (rev > 1) |
669a5db4 | 840 | return -ENODEV; |
887125e3 | 841 | ppi[0] = &info_hpt372; |
669a5db4 JG |
842 | /* Check this */ |
843 | chip_table = &hpt302; | |
844 | break; | |
845 | case PCI_DEVICE_ID_TTI_HPT371: | |
89d3b360 | 846 | if (rev > 1) |
fcc2f69a | 847 | return -ENODEV; |
887125e3 | 848 | ppi[0] = &info_hpt372; |
669a5db4 | 849 | chip_table = &hpt371; |
a4734468 AC |
850 | /* Single channel device, master is not present |
851 | but the BIOS (or us for non x86) must mark it | |
fcc2f69a AC |
852 | absent */ |
853 | pci_read_config_byte(dev, 0x50, &mcr1); | |
854 | mcr1 &= ~0x04; | |
855 | pci_write_config_byte(dev, 0x50, mcr1); | |
669a5db4 JG |
856 | break; |
857 | case PCI_DEVICE_ID_TTI_HPT374: | |
858 | chip_table = &hpt374; | |
a1efdaba TH |
859 | if (!(PCI_FUNC(dev->devfn) & 1)) |
860 | *ppi = &info_hpt374_fn0; | |
861 | else | |
862 | *ppi = &info_hpt374_fn1; | |
669a5db4 JG |
863 | break; |
864 | default: | |
865 | printk(KERN_ERR "pata_hpt37x: PCI table is bogus please report (%d).\n", dev->device); | |
866 | return -ENODEV; | |
867 | } | |
868 | } | |
869 | /* Ok so this is a chip we support */ | |
870 | ||
871 | pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, (L1_CACHE_BYTES / 4)); | |
872 | pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x78); | |
873 | pci_write_config_byte(dev, PCI_MIN_GNT, 0x08); | |
874 | pci_write_config_byte(dev, PCI_MAX_LAT, 0x08); | |
875 | ||
876 | pci_read_config_byte(dev, 0x5A, &irqmask); | |
877 | irqmask &= ~0x10; | |
878 | pci_write_config_byte(dev, 0x5a, irqmask); | |
879 | ||
880 | /* | |
881 | * default to pci clock. make sure MA15/16 are set to output | |
882 | * to prevent drives having problems with 40-pin cables. Needed | |
883 | * for some drives such as IBM-DTLA which will not enter ready | |
884 | * state on reset when PDIAG is a input. | |
885 | */ | |
886 | ||
85cd7251 | 887 | pci_write_config_byte(dev, 0x5b, 0x23); |
a617c09f | 888 | |
fcc2f69a AC |
889 | /* |
890 | * HighPoint does this for HPT372A. | |
891 | * NOTE: This register is only writeable via I/O space. | |
892 | */ | |
893 | if (chip_table == &hpt372a) | |
894 | outb(0x0e, iobase + 0x9c); | |
85cd7251 | 895 | |
fcc2f69a | 896 | /* Some devices do not let this value be accessed via PCI space |
73946f9f AC |
897 | according to the old driver. In addition we must use the value |
898 | from FN 0 on the HPT374 */ | |
899 | ||
900 | if (chip_table == &hpt374) { | |
901 | freq = hpt374_read_freq(dev); | |
902 | if (freq == 0) | |
903 | return -ENODEV; | |
904 | } else | |
905 | freq = inl(iobase + 0x90); | |
fcc2f69a | 906 | |
669a5db4 JG |
907 | if ((freq >> 12) != 0xABCDE) { |
908 | int i; | |
909 | u8 sr; | |
910 | u32 total = 0; | |
85cd7251 | 911 | |
669a5db4 | 912 | printk(KERN_WARNING "pata_hpt37x: BIOS has not set timing clocks.\n"); |
85cd7251 | 913 | |
669a5db4 JG |
914 | /* This is the process the HPT371 BIOS is reported to use */ |
915 | for(i = 0; i < 128; i++) { | |
916 | pci_read_config_byte(dev, 0x78, &sr); | |
fcc2f69a | 917 | total += sr & 0x1FF; |
669a5db4 JG |
918 | udelay(15); |
919 | } | |
920 | freq = total / 128; | |
921 | } | |
922 | freq &= 0x1FF; | |
85cd7251 | 923 | |
669a5db4 JG |
924 | /* |
925 | * Turn the frequency check into a band and then find a timing | |
926 | * table to match it. | |
927 | */ | |
a617c09f | 928 | |
669a5db4 | 929 | clock_slot = hpt37x_clock_slot(freq, chip_table->base); |
fcc2f69a | 930 | if (chip_table->clocks[clock_slot] == NULL || prefer_dpll) { |
669a5db4 JG |
931 | /* |
932 | * We need to try PLL mode instead | |
fcc2f69a AC |
933 | * |
934 | * For non UDMA133 capable devices we should | |
935 | * use a 50MHz DPLL by choice | |
669a5db4 | 936 | */ |
fcc2f69a | 937 | unsigned int f_low, f_high; |
960c8a10 | 938 | int dpll, adjust; |
a617c09f | 939 | |
960c8a10 | 940 | /* Compute DPLL */ |
887125e3 | 941 | dpll = (ppi[0]->udma_mask & 0xC0) ? 3 : 2; |
a617c09f | 942 | |
960c8a10 | 943 | f_low = (MHz[clock_slot] * 48) / MHz[dpll]; |
fcc2f69a | 944 | f_high = f_low + 2; |
960c8a10 AC |
945 | if (clock_slot > 1) |
946 | f_high += 2; | |
fcc2f69a AC |
947 | |
948 | /* Select the DPLL clock. */ | |
949 | pci_write_config_byte(dev, 0x5b, 0x21); | |
64a81709 | 950 | pci_write_config_dword(dev, 0x5C, (f_high << 16) | f_low | 0x100); |
85cd7251 | 951 | |
669a5db4 JG |
952 | for(adjust = 0; adjust < 8; adjust++) { |
953 | if (hpt37x_calibrate_dpll(dev)) | |
954 | break; | |
955 | /* See if it'll settle at a fractionally different clock */ | |
64a81709 AC |
956 | if (adjust & 1) |
957 | f_low -= adjust >> 1; | |
958 | else | |
959 | f_high += adjust >> 1; | |
960 | pci_write_config_dword(dev, 0x5C, (f_high << 16) | f_low | 0x100); | |
669a5db4 JG |
961 | } |
962 | if (adjust == 8) { | |
80b8987c | 963 | printk(KERN_ERR "pata_hpt37x: DPLL did not stabilize!\n"); |
669a5db4 JG |
964 | return -ENODEV; |
965 | } | |
960c8a10 | 966 | if (dpll == 3) |
1626aeb8 | 967 | private_data = (void *)hpt37x_timings_66; |
fcc2f69a | 968 | else |
1626aeb8 | 969 | private_data = (void *)hpt37x_timings_50; |
85cd7251 | 970 | |
80b8987c SS |
971 | printk(KERN_INFO "pata_hpt37x: bus clock %dMHz, using %dMHz DPLL.\n", |
972 | MHz[clock_slot], MHz[dpll]); | |
669a5db4 | 973 | } else { |
1626aeb8 | 974 | private_data = (void *)chip_table->clocks[clock_slot]; |
669a5db4 | 975 | /* |
a4734468 AC |
976 | * Perform a final fixup. Note that we will have used the |
977 | * DPLL on the HPT372 which means we don't have to worry | |
978 | * about lack of UDMA133 support on lower clocks | |
979 | */ | |
85cd7251 | 980 | |
887125e3 TH |
981 | if (clock_slot < 2 && ppi[0] == &info_hpt370) |
982 | ppi[0] = &info_hpt370_33; | |
983 | if (clock_slot < 2 && ppi[0] == &info_hpt370a) | |
984 | ppi[0] = &info_hpt370a_33; | |
80b8987c SS |
985 | printk(KERN_INFO "pata_hpt37x: %s using %dMHz bus clock.\n", |
986 | chip_table->name, MHz[clock_slot]); | |
669a5db4 | 987 | } |
fcc2f69a | 988 | |
669a5db4 | 989 | /* Now kick off ATA set up */ |
1c5afdf7 | 990 | return ata_pci_bmdma_init_one(dev, ppi, &hpt37x_sht, private_data, 0); |
669a5db4 JG |
991 | } |
992 | ||
2d2744fc JG |
993 | static const struct pci_device_id hpt37x[] = { |
994 | { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT366), }, | |
995 | { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT371), }, | |
996 | { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT372), }, | |
997 | { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT374), }, | |
998 | { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT302), }, | |
999 | ||
1000 | { }, | |
669a5db4 JG |
1001 | }; |
1002 | ||
1003 | static struct pci_driver hpt37x_pci_driver = { | |
2d2744fc | 1004 | .name = DRV_NAME, |
669a5db4 JG |
1005 | .id_table = hpt37x, |
1006 | .probe = hpt37x_init_one, | |
1007 | .remove = ata_pci_remove_one | |
1008 | }; | |
1009 | ||
1010 | static int __init hpt37x_init(void) | |
1011 | { | |
1012 | return pci_register_driver(&hpt37x_pci_driver); | |
1013 | } | |
1014 | ||
669a5db4 JG |
1015 | static void __exit hpt37x_exit(void) |
1016 | { | |
1017 | pci_unregister_driver(&hpt37x_pci_driver); | |
1018 | } | |
1019 | ||
669a5db4 JG |
1020 | MODULE_AUTHOR("Alan Cox"); |
1021 | MODULE_DESCRIPTION("low-level driver for the Highpoint HPT37x/30x"); | |
1022 | MODULE_LICENSE("GPL"); | |
1023 | MODULE_DEVICE_TABLE(pci, hpt37x); | |
1024 | MODULE_VERSION(DRV_VERSION); | |
1025 | ||
1026 | module_init(hpt37x_init); | |
1027 | module_exit(hpt37x_exit); |