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669a5db4 JG |
1 | /* |
2 | * Libata driver for the highpoint 37x and 30x UDMA66 ATA controllers. | |
3 | * | |
4 | * This driver is heavily based upon: | |
5 | * | |
6 | * linux/drivers/ide/pci/hpt366.c Version 0.36 April 25, 2003 | |
7 | * | |
8 | * Copyright (C) 1999-2003 Andre Hedrick <andre@linux-ide.org> | |
9 | * Portions Copyright (C) 2001 Sun Microsystems, Inc. | |
10 | * Portions Copyright (C) 2003 Red Hat Inc | |
8e834c2e | 11 | * Portions Copyright (C) 2005-2010 MontaVista Software, Inc. |
669a5db4 JG |
12 | * |
13 | * TODO | |
d44a65f7 | 14 | * Look into engine reset on timeout errors. Should not be required. |
669a5db4 JG |
15 | */ |
16 | ||
8d7b1c70 JP |
17 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
18 | ||
669a5db4 JG |
19 | #include <linux/kernel.h> |
20 | #include <linux/module.h> | |
21 | #include <linux/pci.h> | |
22 | #include <linux/init.h> | |
23 | #include <linux/blkdev.h> | |
24 | #include <linux/delay.h> | |
25 | #include <scsi/scsi_host.h> | |
26 | #include <linux/libata.h> | |
27 | ||
28 | #define DRV_NAME "pata_hpt37x" | |
8d7b1c70 | 29 | #define DRV_VERSION "0.6.23" |
669a5db4 JG |
30 | |
31 | struct hpt_clock { | |
32 | u8 xfer_speed; | |
33 | u32 timing; | |
34 | }; | |
35 | ||
36 | struct hpt_chip { | |
37 | const char *name; | |
38 | unsigned int base; | |
39 | struct hpt_clock const *clocks[4]; | |
40 | }; | |
41 | ||
42 | /* key for bus clock timings | |
43 | * bit | |
fd5e62e2 SS |
44 | * 0:3 data_high_time. Inactive time of DIOW_/DIOR_ for PIO and MW DMA. |
45 | * cycles = value + 1 | |
46 | * 4:8 data_low_time. Active time of DIOW_/DIOR_ for PIO and MW DMA. | |
47 | * cycles = value + 1 | |
48 | * 9:12 cmd_high_time. Inactive time of DIOW_/DIOR_ during task file | |
669a5db4 | 49 | * register access. |
fd5e62e2 | 50 | * 13:17 cmd_low_time. Active time of DIOW_/DIOR_ during task file |
669a5db4 | 51 | * register access. |
fd5e62e2 SS |
52 | * 18:20 udma_cycle_time. Clock cycles for UDMA xfer. |
53 | * 21 CLK frequency for UDMA: 0=ATA clock, 1=dual ATA clock. | |
54 | * 22:24 pre_high_time. Time to initialize 1st cycle for PIO and MW DMA xfer. | |
55 | * 25:27 cmd_pre_high_time. Time to initialize 1st PIO cycle for task file | |
669a5db4 | 56 | * register access. |
fd5e62e2 SS |
57 | * 28 UDMA enable. |
58 | * 29 DMA enable. | |
59 | * 30 PIO_MST enable. If set, the chip is in bus master mode during | |
60 | * PIO xfer. | |
61 | * 31 FIFO enable. Only for PIO. | |
669a5db4 JG |
62 | */ |
63 | ||
fcc2f69a AC |
64 | static struct hpt_clock hpt37x_timings_33[] = { |
65 | { XFER_UDMA_6, 0x12446231 }, /* 0x12646231 ?? */ | |
66 | { XFER_UDMA_5, 0x12446231 }, | |
67 | { XFER_UDMA_4, 0x12446231 }, | |
68 | { XFER_UDMA_3, 0x126c6231 }, | |
69 | { XFER_UDMA_2, 0x12486231 }, | |
70 | { XFER_UDMA_1, 0x124c6233 }, | |
71 | { XFER_UDMA_0, 0x12506297 }, | |
72 | ||
73 | { XFER_MW_DMA_2, 0x22406c31 }, | |
74 | { XFER_MW_DMA_1, 0x22406c33 }, | |
75 | { XFER_MW_DMA_0, 0x22406c97 }, | |
76 | ||
77 | { XFER_PIO_4, 0x06414e31 }, | |
78 | { XFER_PIO_3, 0x06414e42 }, | |
79 | { XFER_PIO_2, 0x06414e53 }, | |
80 | { XFER_PIO_1, 0x06814e93 }, | |
81 | { XFER_PIO_0, 0x06814ea7 } | |
669a5db4 JG |
82 | }; |
83 | ||
fcc2f69a AC |
84 | static struct hpt_clock hpt37x_timings_50[] = { |
85 | { XFER_UDMA_6, 0x12848242 }, | |
86 | { XFER_UDMA_5, 0x12848242 }, | |
87 | { XFER_UDMA_4, 0x12ac8242 }, | |
88 | { XFER_UDMA_3, 0x128c8242 }, | |
89 | { XFER_UDMA_2, 0x120c8242 }, | |
90 | { XFER_UDMA_1, 0x12148254 }, | |
91 | { XFER_UDMA_0, 0x121882ea }, | |
92 | ||
93 | { XFER_MW_DMA_2, 0x22808242 }, | |
94 | { XFER_MW_DMA_1, 0x22808254 }, | |
95 | { XFER_MW_DMA_0, 0x228082ea }, | |
96 | ||
97 | { XFER_PIO_4, 0x0a81f442 }, | |
98 | { XFER_PIO_3, 0x0a81f443 }, | |
99 | { XFER_PIO_2, 0x0a81f454 }, | |
100 | { XFER_PIO_1, 0x0ac1f465 }, | |
101 | { XFER_PIO_0, 0x0ac1f48a } | |
669a5db4 JG |
102 | }; |
103 | ||
fcc2f69a AC |
104 | static struct hpt_clock hpt37x_timings_66[] = { |
105 | { XFER_UDMA_6, 0x1c869c62 }, | |
106 | { XFER_UDMA_5, 0x1cae9c62 }, /* 0x1c8a9c62 */ | |
107 | { XFER_UDMA_4, 0x1c8a9c62 }, | |
108 | { XFER_UDMA_3, 0x1c8e9c62 }, | |
109 | { XFER_UDMA_2, 0x1c929c62 }, | |
110 | { XFER_UDMA_1, 0x1c9a9c62 }, | |
111 | { XFER_UDMA_0, 0x1c829c62 }, | |
112 | ||
113 | { XFER_MW_DMA_2, 0x2c829c62 }, | |
114 | { XFER_MW_DMA_1, 0x2c829c66 }, | |
115 | { XFER_MW_DMA_0, 0x2c829d2e }, | |
116 | ||
117 | { XFER_PIO_4, 0x0c829c62 }, | |
118 | { XFER_PIO_3, 0x0c829c84 }, | |
119 | { XFER_PIO_2, 0x0c829ca6 }, | |
120 | { XFER_PIO_1, 0x0d029d26 }, | |
121 | { XFER_PIO_0, 0x0d029d5e } | |
669a5db4 JG |
122 | }; |
123 | ||
669a5db4 JG |
124 | |
125 | static const struct hpt_chip hpt370 = { | |
126 | "HPT370", | |
127 | 48, | |
128 | { | |
fcc2f69a | 129 | hpt37x_timings_33, |
669a5db4 JG |
130 | NULL, |
131 | NULL, | |
a4734468 | 132 | NULL |
669a5db4 JG |
133 | } |
134 | }; | |
135 | ||
136 | static const struct hpt_chip hpt370a = { | |
137 | "HPT370A", | |
138 | 48, | |
139 | { | |
fcc2f69a | 140 | hpt37x_timings_33, |
669a5db4 | 141 | NULL, |
fcc2f69a | 142 | hpt37x_timings_50, |
a4734468 | 143 | NULL |
669a5db4 JG |
144 | } |
145 | }; | |
146 | ||
147 | static const struct hpt_chip hpt372 = { | |
148 | "HPT372", | |
149 | 55, | |
150 | { | |
fcc2f69a | 151 | hpt37x_timings_33, |
669a5db4 | 152 | NULL, |
fcc2f69a AC |
153 | hpt37x_timings_50, |
154 | hpt37x_timings_66 | |
669a5db4 JG |
155 | } |
156 | }; | |
157 | ||
158 | static const struct hpt_chip hpt302 = { | |
159 | "HPT302", | |
160 | 66, | |
161 | { | |
fcc2f69a | 162 | hpt37x_timings_33, |
669a5db4 | 163 | NULL, |
fcc2f69a AC |
164 | hpt37x_timings_50, |
165 | hpt37x_timings_66 | |
669a5db4 JG |
166 | } |
167 | }; | |
168 | ||
169 | static const struct hpt_chip hpt371 = { | |
170 | "HPT371", | |
171 | 66, | |
172 | { | |
fcc2f69a | 173 | hpt37x_timings_33, |
669a5db4 | 174 | NULL, |
fcc2f69a AC |
175 | hpt37x_timings_50, |
176 | hpt37x_timings_66 | |
669a5db4 JG |
177 | } |
178 | }; | |
179 | ||
180 | static const struct hpt_chip hpt372a = { | |
181 | "HPT372A", | |
182 | 66, | |
183 | { | |
fcc2f69a | 184 | hpt37x_timings_33, |
669a5db4 | 185 | NULL, |
fcc2f69a AC |
186 | hpt37x_timings_50, |
187 | hpt37x_timings_66 | |
669a5db4 JG |
188 | } |
189 | }; | |
190 | ||
191 | static const struct hpt_chip hpt374 = { | |
192 | "HPT374", | |
193 | 48, | |
194 | { | |
fcc2f69a | 195 | hpt37x_timings_33, |
669a5db4 JG |
196 | NULL, |
197 | NULL, | |
198 | NULL | |
199 | } | |
200 | }; | |
201 | ||
202 | /** | |
203 | * hpt37x_find_mode - reset the hpt37x bus | |
204 | * @ap: ATA port | |
205 | * @speed: transfer mode | |
206 | * | |
207 | * Return the 32bit register programming information for this channel | |
208 | * that matches the speed provided. | |
209 | */ | |
85cd7251 | 210 | |
669a5db4 JG |
211 | static u32 hpt37x_find_mode(struct ata_port *ap, int speed) |
212 | { | |
213 | struct hpt_clock *clocks = ap->host->private_data; | |
85cd7251 | 214 | |
49bfbd38 | 215 | while (clocks->xfer_speed) { |
669a5db4 JG |
216 | if (clocks->xfer_speed == speed) |
217 | return clocks->timing; | |
218 | clocks++; | |
219 | } | |
220 | BUG(); | |
221 | return 0xffffffffU; /* silence compiler warning */ | |
222 | } | |
223 | ||
49bfbd38 SS |
224 | static int hpt_dma_blacklisted(const struct ata_device *dev, char *modestr, |
225 | const char * const list[]) | |
669a5db4 | 226 | { |
8bfa79fc | 227 | unsigned char model_num[ATA_ID_PROD_LEN + 1]; |
669a5db4 JG |
228 | int i = 0; |
229 | ||
8bfa79fc | 230 | ata_id_c_string(dev->id, model_num, ATA_ID_PROD, sizeof(model_num)); |
669a5db4 | 231 | |
8bfa79fc TH |
232 | while (list[i] != NULL) { |
233 | if (!strcmp(list[i], model_num)) { | |
8d7b1c70 JP |
234 | pr_warn("%s is not supported for %s\n", |
235 | modestr, list[i]); | |
669a5db4 JG |
236 | return 1; |
237 | } | |
238 | i++; | |
239 | } | |
240 | return 0; | |
241 | } | |
242 | ||
49bfbd38 SS |
243 | static const char * const bad_ata33[] = { |
244 | "Maxtor 92720U8", "Maxtor 92040U6", "Maxtor 91360U4", "Maxtor 91020U3", | |
245 | "Maxtor 90845U3", "Maxtor 90650U2", | |
246 | "Maxtor 91360D8", "Maxtor 91190D7", "Maxtor 91020D6", "Maxtor 90845D5", | |
247 | "Maxtor 90680D4", "Maxtor 90510D3", "Maxtor 90340D2", | |
248 | "Maxtor 91152D8", "Maxtor 91008D7", "Maxtor 90845D6", "Maxtor 90840D6", | |
249 | "Maxtor 90720D5", "Maxtor 90648D5", "Maxtor 90576D4", | |
669a5db4 JG |
250 | "Maxtor 90510D4", |
251 | "Maxtor 90432D3", "Maxtor 90288D2", "Maxtor 90256D2", | |
49bfbd38 SS |
252 | "Maxtor 91000D8", "Maxtor 90910D8", "Maxtor 90875D7", "Maxtor 90840D7", |
253 | "Maxtor 90750D6", "Maxtor 90625D5", "Maxtor 90500D4", | |
254 | "Maxtor 91728D8", "Maxtor 91512D7", "Maxtor 91303D6", "Maxtor 91080D5", | |
255 | "Maxtor 90845D4", "Maxtor 90680D4", "Maxtor 90648D3", "Maxtor 90432D2", | |
669a5db4 JG |
256 | NULL |
257 | }; | |
258 | ||
49bfbd38 | 259 | static const char * const bad_ata100_5[] = { |
669a5db4 JG |
260 | "IBM-DTLA-307075", |
261 | "IBM-DTLA-307060", | |
262 | "IBM-DTLA-307045", | |
263 | "IBM-DTLA-307030", | |
264 | "IBM-DTLA-307020", | |
265 | "IBM-DTLA-307015", | |
266 | "IBM-DTLA-305040", | |
267 | "IBM-DTLA-305030", | |
268 | "IBM-DTLA-305020", | |
269 | "IC35L010AVER07-0", | |
270 | "IC35L020AVER07-0", | |
271 | "IC35L030AVER07-0", | |
272 | "IC35L040AVER07-0", | |
273 | "IC35L060AVER07-0", | |
274 | "WDC AC310200R", | |
275 | NULL | |
276 | }; | |
277 | ||
278 | /** | |
279 | * hpt370_filter - mode selection filter | |
669a5db4 JG |
280 | * @adev: ATA device |
281 | * | |
282 | * Block UDMA on devices that cause trouble with this controller. | |
283 | */ | |
85cd7251 | 284 | |
a76b62ca | 285 | static unsigned long hpt370_filter(struct ata_device *adev, unsigned long mask) |
669a5db4 | 286 | { |
6929da44 | 287 | if (adev->class == ATA_DEV_ATA) { |
669a5db4 JG |
288 | if (hpt_dma_blacklisted(adev, "UDMA", bad_ata33)) |
289 | mask &= ~ATA_MASK_UDMA; | |
290 | if (hpt_dma_blacklisted(adev, "UDMA100", bad_ata100_5)) | |
6ddd6861 | 291 | mask &= ~(0xE0 << ATA_SHIFT_UDMA); |
669a5db4 | 292 | } |
c7087652 | 293 | return mask; |
669a5db4 JG |
294 | } |
295 | ||
296 | /** | |
297 | * hpt370a_filter - mode selection filter | |
669a5db4 JG |
298 | * @adev: ATA device |
299 | * | |
300 | * Block UDMA on devices that cause trouble with this controller. | |
301 | */ | |
85cd7251 | 302 | |
a76b62ca | 303 | static unsigned long hpt370a_filter(struct ata_device *adev, unsigned long mask) |
669a5db4 | 304 | { |
73946f9f | 305 | if (adev->class == ATA_DEV_ATA) { |
669a5db4 | 306 | if (hpt_dma_blacklisted(adev, "UDMA100", bad_ata100_5)) |
6ddd6861 | 307 | mask &= ~(0xE0 << ATA_SHIFT_UDMA); |
669a5db4 | 308 | } |
c7087652 | 309 | return mask; |
669a5db4 | 310 | } |
85cd7251 | 311 | |
8e834c2e SS |
312 | /** |
313 | * hpt372_filter - mode selection filter | |
314 | * @adev: ATA device | |
315 | * @mask: mode mask | |
316 | * | |
317 | * The Marvell bridge chips used on the HighPoint SATA cards do not seem | |
318 | * to support the UltraDMA modes 1, 2, and 3 as well as any MWDMA modes... | |
319 | */ | |
320 | static unsigned long hpt372_filter(struct ata_device *adev, unsigned long mask) | |
321 | { | |
322 | if (ata_id_is_sata(adev->id)) | |
323 | mask &= ~((0xE << ATA_SHIFT_UDMA) | ATA_MASK_MWDMA); | |
324 | ||
325 | return mask; | |
326 | } | |
327 | ||
9e87be9e BZ |
328 | /** |
329 | * hpt37x_cable_detect - Detect the cable type | |
330 | * @ap: ATA port to detect on | |
331 | * | |
332 | * Return the cable type attached to this port | |
333 | */ | |
334 | ||
335 | static int hpt37x_cable_detect(struct ata_port *ap) | |
336 | { | |
337 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); | |
338 | u8 scr2, ata66; | |
339 | ||
340 | pci_read_config_byte(pdev, 0x5B, &scr2); | |
341 | pci_write_config_byte(pdev, 0x5B, scr2 & ~0x01); | |
10a9c969 BZ |
342 | |
343 | udelay(10); /* debounce */ | |
344 | ||
9e87be9e BZ |
345 | /* Cable register now active */ |
346 | pci_read_config_byte(pdev, 0x5A, &ata66); | |
347 | /* Restore state */ | |
348 | pci_write_config_byte(pdev, 0x5B, scr2); | |
349 | ||
350 | if (ata66 & (2 >> ap->port_no)) | |
351 | return ATA_CBL_PATA40; | |
352 | else | |
353 | return ATA_CBL_PATA80; | |
354 | } | |
355 | ||
356 | /** | |
357 | * hpt374_fn1_cable_detect - Detect the cable type | |
358 | * @ap: ATA port to detect on | |
359 | * | |
360 | * Return the cable type attached to this port | |
361 | */ | |
362 | ||
363 | static int hpt374_fn1_cable_detect(struct ata_port *ap) | |
364 | { | |
365 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); | |
366 | unsigned int mcrbase = 0x50 + 4 * ap->port_no; | |
367 | u16 mcr3; | |
368 | u8 ata66; | |
369 | ||
370 | /* Do the extra channel work */ | |
371 | pci_read_config_word(pdev, mcrbase + 2, &mcr3); | |
372 | /* Set bit 15 of 0x52 to enable TCBLID as input */ | |
373 | pci_write_config_word(pdev, mcrbase + 2, mcr3 | 0x8000); | |
374 | pci_read_config_byte(pdev, 0x5A, &ata66); | |
375 | /* Reset TCBLID/FCBLID to output */ | |
376 | pci_write_config_word(pdev, mcrbase + 2, mcr3); | |
377 | ||
378 | if (ata66 & (2 >> ap->port_no)) | |
379 | return ATA_CBL_PATA40; | |
380 | else | |
381 | return ATA_CBL_PATA80; | |
382 | } | |
383 | ||
669a5db4 JG |
384 | /** |
385 | * hpt37x_pre_reset - reset the hpt37x bus | |
cc0680a5 | 386 | * @link: ATA link to reset |
d4b2bab4 | 387 | * @deadline: deadline jiffies for the operation |
669a5db4 | 388 | * |
ab81a505 | 389 | * Perform the initial reset handling for the HPT37x. |
669a5db4 | 390 | */ |
85cd7251 | 391 | |
cc0680a5 | 392 | static int hpt37x_pre_reset(struct ata_link *link, unsigned long deadline) |
669a5db4 | 393 | { |
cc0680a5 | 394 | struct ata_port *ap = link->ap; |
669a5db4 | 395 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); |
b5bf24b9 AC |
396 | static const struct pci_bits hpt37x_enable_bits[] = { |
397 | { 0x50, 1, 0x04, 0x04 }, | |
398 | { 0x54, 1, 0x04, 0x04 } | |
399 | }; | |
49bfbd38 | 400 | |
b5bf24b9 AC |
401 | if (!pci_test_config_bits(pdev, &hpt37x_enable_bits[ap->port_no])) |
402 | return -ENOENT; | |
f20b16ff | 403 | |
669a5db4 | 404 | /* Reset the state machine */ |
fcc2f69a | 405 | pci_write_config_byte(pdev, 0x50 + 4 * ap->port_no, 0x37); |
669a5db4 | 406 | udelay(100); |
85cd7251 | 407 | |
9363c382 | 408 | return ata_sff_prereset(link, deadline); |
669a5db4 JG |
409 | } |
410 | ||
1a1b172b SS |
411 | static void hpt370_set_mode(struct ata_port *ap, struct ata_device *adev, |
412 | u8 mode) | |
669a5db4 JG |
413 | { |
414 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); | |
415 | u32 addr1, addr2; | |
1a1b172b | 416 | u32 reg, timing, mask; |
669a5db4 JG |
417 | u8 fast; |
418 | ||
419 | addr1 = 0x40 + 4 * (adev->devno + 2 * ap->port_no); | |
420 | addr2 = 0x51 + 4 * ap->port_no; | |
85cd7251 | 421 | |
669a5db4 JG |
422 | /* Fast interrupt prediction disable, hold off interrupt disable */ |
423 | pci_read_config_byte(pdev, addr2, &fast); | |
424 | fast &= ~0x02; | |
425 | fast |= 0x01; | |
426 | pci_write_config_byte(pdev, addr2, fast); | |
85cd7251 | 427 | |
1a1b172b SS |
428 | /* Determine timing mask and find matching mode entry */ |
429 | if (mode < XFER_MW_DMA_0) | |
430 | mask = 0xcfc3ffff; | |
431 | else if (mode < XFER_UDMA_0) | |
432 | mask = 0x31c001ff; | |
433 | else | |
434 | mask = 0x303c0000; | |
435 | ||
436 | timing = hpt37x_find_mode(ap, mode); | |
437 | ||
669a5db4 | 438 | pci_read_config_dword(pdev, addr1, ®); |
1a1b172b SS |
439 | reg = (reg & ~mask) | (timing & mask); |
440 | pci_write_config_dword(pdev, addr1, reg); | |
441 | } | |
442 | /** | |
443 | * hpt370_set_piomode - PIO setup | |
444 | * @ap: ATA interface | |
445 | * @adev: device on the interface | |
446 | * | |
447 | * Perform PIO mode setup. | |
448 | */ | |
449 | ||
450 | static void hpt370_set_piomode(struct ata_port *ap, struct ata_device *adev) | |
451 | { | |
452 | hpt370_set_mode(ap, adev, adev->pio_mode); | |
669a5db4 JG |
453 | } |
454 | ||
455 | /** | |
456 | * hpt370_set_dmamode - DMA timing setup | |
457 | * @ap: ATA interface | |
458 | * @adev: Device being configured | |
459 | * | |
1a1b172b | 460 | * Set up the channel for MWDMA or UDMA modes. |
669a5db4 | 461 | */ |
85cd7251 | 462 | |
669a5db4 JG |
463 | static void hpt370_set_dmamode(struct ata_port *ap, struct ata_device *adev) |
464 | { | |
1a1b172b | 465 | hpt370_set_mode(ap, adev, adev->dma_mode); |
669a5db4 JG |
466 | } |
467 | ||
669a5db4 JG |
468 | /** |
469 | * hpt370_bmdma_end - DMA engine stop | |
470 | * @qc: ATA command | |
471 | * | |
472 | * Work around the HPT370 DMA engine. | |
473 | */ | |
85cd7251 | 474 | |
669a5db4 JG |
475 | static void hpt370_bmdma_stop(struct ata_queued_cmd *qc) |
476 | { | |
477 | struct ata_port *ap = qc->ap; | |
478 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); | |
0d5ff566 | 479 | void __iomem *bmdma = ap->ioaddr.bmdma_addr; |
56f46f8c SS |
480 | u8 dma_stat = ioread8(bmdma + ATA_DMA_STATUS); |
481 | u8 dma_cmd; | |
85cd7251 | 482 | |
56f46f8c | 483 | if (dma_stat & ATA_DMA_ACTIVE) { |
669a5db4 | 484 | udelay(20); |
56f46f8c | 485 | dma_stat = ioread8(bmdma + ATA_DMA_STATUS); |
669a5db4 | 486 | } |
56f46f8c | 487 | if (dma_stat & ATA_DMA_ACTIVE) { |
669a5db4 JG |
488 | /* Clear the engine */ |
489 | pci_write_config_byte(pdev, 0x50 + 4 * ap->port_no, 0x37); | |
490 | udelay(10); | |
491 | /* Stop DMA */ | |
56f46f8c SS |
492 | dma_cmd = ioread8(bmdma + ATA_DMA_CMD); |
493 | iowrite8(dma_cmd & ~ATA_DMA_START, bmdma + ATA_DMA_CMD); | |
669a5db4 | 494 | /* Clear Error */ |
56f46f8c SS |
495 | dma_stat = ioread8(bmdma + ATA_DMA_STATUS); |
496 | iowrite8(dma_stat | ATA_DMA_INTR | ATA_DMA_ERR, | |
497 | bmdma + ATA_DMA_STATUS); | |
669a5db4 JG |
498 | /* Clear the engine */ |
499 | pci_write_config_byte(pdev, 0x50 + 4 * ap->port_no, 0x37); | |
500 | udelay(10); | |
501 | } | |
502 | ata_bmdma_stop(qc); | |
503 | } | |
504 | ||
1a1b172b SS |
505 | static void hpt372_set_mode(struct ata_port *ap, struct ata_device *adev, |
506 | u8 mode) | |
669a5db4 JG |
507 | { |
508 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); | |
509 | u32 addr1, addr2; | |
1a1b172b | 510 | u32 reg, timing, mask; |
669a5db4 JG |
511 | u8 fast; |
512 | ||
513 | addr1 = 0x40 + 4 * (adev->devno + 2 * ap->port_no); | |
514 | addr2 = 0x51 + 4 * ap->port_no; | |
85cd7251 | 515 | |
669a5db4 JG |
516 | /* Fast interrupt prediction disable, hold off interrupt disable */ |
517 | pci_read_config_byte(pdev, addr2, &fast); | |
518 | fast &= ~0x07; | |
519 | pci_write_config_byte(pdev, addr2, fast); | |
85cd7251 | 520 | |
1a1b172b SS |
521 | /* Determine timing mask and find matching mode entry */ |
522 | if (mode < XFER_MW_DMA_0) | |
523 | mask = 0xcfc3ffff; | |
524 | else if (mode < XFER_UDMA_0) | |
525 | mask = 0x31c001ff; | |
526 | else | |
527 | mask = 0x303c0000; | |
528 | ||
529 | timing = hpt37x_find_mode(ap, mode); | |
530 | ||
669a5db4 | 531 | pci_read_config_dword(pdev, addr1, ®); |
1a1b172b SS |
532 | reg = (reg & ~mask) | (timing & mask); |
533 | pci_write_config_dword(pdev, addr1, reg); | |
534 | } | |
85cd7251 | 535 | |
1a1b172b SS |
536 | /** |
537 | * hpt372_set_piomode - PIO setup | |
538 | * @ap: ATA interface | |
539 | * @adev: device on the interface | |
540 | * | |
541 | * Perform PIO mode setup. | |
542 | */ | |
543 | ||
544 | static void hpt372_set_piomode(struct ata_port *ap, struct ata_device *adev) | |
545 | { | |
546 | hpt372_set_mode(ap, adev, adev->pio_mode); | |
669a5db4 JG |
547 | } |
548 | ||
549 | /** | |
550 | * hpt372_set_dmamode - DMA timing setup | |
551 | * @ap: ATA interface | |
552 | * @adev: Device being configured | |
553 | * | |
1a1b172b | 554 | * Set up the channel for MWDMA or UDMA modes. |
669a5db4 | 555 | */ |
85cd7251 | 556 | |
669a5db4 JG |
557 | static void hpt372_set_dmamode(struct ata_port *ap, struct ata_device *adev) |
558 | { | |
1a1b172b | 559 | hpt372_set_mode(ap, adev, adev->dma_mode); |
669a5db4 JG |
560 | } |
561 | ||
562 | /** | |
563 | * hpt37x_bmdma_end - DMA engine stop | |
564 | * @qc: ATA command | |
565 | * | |
566 | * Clean up after the HPT372 and later DMA engine | |
567 | */ | |
85cd7251 | 568 | |
669a5db4 JG |
569 | static void hpt37x_bmdma_stop(struct ata_queued_cmd *qc) |
570 | { | |
571 | struct ata_port *ap = qc->ap; | |
572 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); | |
6929da44 | 573 | int mscreg = 0x50 + 4 * ap->port_no; |
669a5db4 | 574 | u8 bwsr_stat, msc_stat; |
85cd7251 | 575 | |
669a5db4 JG |
576 | pci_read_config_byte(pdev, 0x6A, &bwsr_stat); |
577 | pci_read_config_byte(pdev, mscreg, &msc_stat); | |
578 | if (bwsr_stat & (1 << ap->port_no)) | |
579 | pci_write_config_byte(pdev, mscreg, msc_stat | 0x30); | |
580 | ata_bmdma_stop(qc); | |
581 | } | |
582 | ||
583 | ||
584 | static struct scsi_host_template hpt37x_sht = { | |
68d1d07b | 585 | ATA_BMDMA_SHT(DRV_NAME), |
669a5db4 JG |
586 | }; |
587 | ||
588 | /* | |
589 | * Configuration for HPT370 | |
590 | */ | |
85cd7251 | 591 | |
669a5db4 | 592 | static struct ata_port_operations hpt370_port_ops = { |
029cfd6b | 593 | .inherits = &ata_bmdma_port_ops, |
669a5db4 | 594 | |
669a5db4 | 595 | .bmdma_stop = hpt370_bmdma_stop, |
669a5db4 | 596 | |
029cfd6b | 597 | .mode_filter = hpt370_filter, |
9e87be9e | 598 | .cable_detect = hpt37x_cable_detect, |
029cfd6b TH |
599 | .set_piomode = hpt370_set_piomode, |
600 | .set_dmamode = hpt370_set_dmamode, | |
a1efdaba | 601 | .prereset = hpt37x_pre_reset, |
85cd7251 | 602 | }; |
669a5db4 JG |
603 | |
604 | /* | |
605 | * Configuration for HPT370A. Close to 370 but less filters | |
606 | */ | |
85cd7251 | 607 | |
669a5db4 | 608 | static struct ata_port_operations hpt370a_port_ops = { |
029cfd6b | 609 | .inherits = &hpt370_port_ops, |
669a5db4 | 610 | .mode_filter = hpt370a_filter, |
85cd7251 | 611 | }; |
669a5db4 JG |
612 | |
613 | /* | |
8e834c2e SS |
614 | * Configuration for HPT371 and HPT302. Slightly different PIO and DMA |
615 | * mode setting functionality. | |
669a5db4 | 616 | */ |
85cd7251 | 617 | |
8e834c2e | 618 | static struct ata_port_operations hpt302_port_ops = { |
029cfd6b | 619 | .inherits = &ata_bmdma_port_ops, |
669a5db4 | 620 | |
669a5db4 | 621 | .bmdma_stop = hpt37x_bmdma_stop, |
669a5db4 | 622 | |
9e87be9e | 623 | .cable_detect = hpt37x_cable_detect, |
029cfd6b TH |
624 | .set_piomode = hpt372_set_piomode, |
625 | .set_dmamode = hpt372_set_dmamode, | |
a1efdaba | 626 | .prereset = hpt37x_pre_reset, |
85cd7251 | 627 | }; |
669a5db4 JG |
628 | |
629 | /* | |
8e834c2e SS |
630 | * Configuration for HPT372. Mode setting works like 371 and 302 |
631 | * but we have a mode filter. | |
632 | */ | |
633 | ||
634 | static struct ata_port_operations hpt372_port_ops = { | |
635 | .inherits = &hpt302_port_ops, | |
636 | .mode_filter = hpt372_filter, | |
637 | }; | |
638 | ||
639 | /* | |
640 | * Configuration for HPT374. Mode setting and filtering works like 372 | |
a1efdaba | 641 | * but we have a different cable detection procedure for function 1. |
669a5db4 | 642 | */ |
85cd7251 | 643 | |
a1efdaba | 644 | static struct ata_port_operations hpt374_fn1_port_ops = { |
029cfd6b | 645 | .inherits = &hpt372_port_ops, |
9e87be9e | 646 | .cable_detect = hpt374_fn1_cable_detect, |
85cd7251 | 647 | }; |
669a5db4 JG |
648 | |
649 | /** | |
ad452d64 | 650 | * hpt37x_clock_slot - Turn timing to PC clock entry |
669a5db4 JG |
651 | * @freq: Reported frequency timing |
652 | * @base: Base timing | |
653 | * | |
654 | * Turn the timing data intoa clock slot (0 for 33, 1 for 40, 2 for 50 | |
655 | * and 3 for 66Mhz) | |
656 | */ | |
85cd7251 | 657 | |
669a5db4 JG |
658 | static int hpt37x_clock_slot(unsigned int freq, unsigned int base) |
659 | { | |
660 | unsigned int f = (base * freq) / 192; /* Mhz */ | |
661 | if (f < 40) | |
662 | return 0; /* 33Mhz slot */ | |
663 | if (f < 45) | |
664 | return 1; /* 40Mhz slot */ | |
665 | if (f < 55) | |
666 | return 2; /* 50Mhz slot */ | |
667 | return 3; /* 60Mhz slot */ | |
668 | } | |
669 | ||
670 | /** | |
671 | * hpt37x_calibrate_dpll - Calibrate the DPLL loop | |
85cd7251 | 672 | * @dev: PCI device |
669a5db4 JG |
673 | * |
674 | * Perform a calibration cycle on the HPT37x DPLL. Returns 1 if this | |
675 | * succeeds | |
676 | */ | |
677 | ||
678 | static int hpt37x_calibrate_dpll(struct pci_dev *dev) | |
679 | { | |
680 | u8 reg5b; | |
681 | u32 reg5c; | |
682 | int tries; | |
85cd7251 | 683 | |
49bfbd38 | 684 | for (tries = 0; tries < 0x5000; tries++) { |
669a5db4 JG |
685 | udelay(50); |
686 | pci_read_config_byte(dev, 0x5b, ®5b); | |
687 | if (reg5b & 0x80) { | |
688 | /* See if it stays set */ | |
49bfbd38 | 689 | for (tries = 0; tries < 0x1000; tries++) { |
669a5db4 JG |
690 | pci_read_config_byte(dev, 0x5b, ®5b); |
691 | /* Failed ? */ | |
692 | if ((reg5b & 0x80) == 0) | |
693 | return 0; | |
694 | } | |
695 | /* Turn off tuning, we have the DPLL set */ | |
696 | pci_read_config_dword(dev, 0x5c, ®5c); | |
49bfbd38 | 697 | pci_write_config_dword(dev, 0x5c, reg5c & ~0x100); |
669a5db4 JG |
698 | return 1; |
699 | } | |
700 | } | |
701 | /* Never went stable */ | |
702 | return 0; | |
703 | } | |
73946f9f AC |
704 | |
705 | static u32 hpt374_read_freq(struct pci_dev *pdev) | |
706 | { | |
707 | u32 freq; | |
708 | unsigned long io_base = pci_resource_start(pdev, 4); | |
49bfbd38 | 709 | |
73946f9f | 710 | if (PCI_FUNC(pdev->devfn) & 1) { |
40f46f17 AM |
711 | struct pci_dev *pdev_0; |
712 | ||
713 | pdev_0 = pci_get_slot(pdev->bus, pdev->devfn - 1); | |
73946f9f AC |
714 | /* Someone hot plugged the controller on us ? */ |
715 | if (pdev_0 == NULL) | |
716 | return 0; | |
717 | io_base = pci_resource_start(pdev_0, 4); | |
718 | freq = inl(io_base + 0x90); | |
719 | pci_dev_put(pdev_0); | |
40f46f17 | 720 | } else |
73946f9f AC |
721 | freq = inl(io_base + 0x90); |
722 | return freq; | |
723 | } | |
724 | ||
669a5db4 JG |
725 | /** |
726 | * hpt37x_init_one - Initialise an HPT37X/302 | |
727 | * @dev: PCI device | |
728 | * @id: Entry in match table | |
729 | * | |
730 | * Initialise an HPT37x device. There are some interesting complications | |
731 | * here. Firstly the chip may report 366 and be one of several variants. | |
732 | * Secondly all the timings depend on the clock for the chip which we must | |
733 | * detect and look up | |
734 | * | |
735 | * This is the known chip mappings. It may be missing a couple of later | |
736 | * releases. | |
737 | * | |
738 | * Chip version PCI Rev Notes | |
739 | * HPT366 4 (HPT366) 0 Other driver | |
740 | * HPT366 4 (HPT366) 1 Other driver | |
741 | * HPT368 4 (HPT366) 2 Other driver | |
742 | * HPT370 4 (HPT366) 3 UDMA100 | |
743 | * HPT370A 4 (HPT366) 4 UDMA100 | |
744 | * HPT372 4 (HPT366) 5 UDMA133 (1) | |
745 | * HPT372N 4 (HPT366) 6 Other driver | |
746 | * HPT372A 5 (HPT372) 1 UDMA133 (1) | |
747 | * HPT372N 5 (HPT372) 2 Other driver | |
748 | * HPT302 6 (HPT302) 1 UDMA133 | |
749 | * HPT302N 6 (HPT302) 2 Other driver | |
750 | * HPT371 7 (HPT371) * UDMA133 | |
751 | * HPT374 8 (HPT374) * UDMA133 4 channel | |
752 | * HPT372N 9 (HPT372N) * Other driver | |
753 | * | |
754 | * (1) UDMA133 support depends on the bus clock | |
755 | */ | |
85cd7251 | 756 | |
669a5db4 JG |
757 | static int hpt37x_init_one(struct pci_dev *dev, const struct pci_device_id *id) |
758 | { | |
759 | /* HPT370 - UDMA100 */ | |
1626aeb8 | 760 | static const struct ata_port_info info_hpt370 = { |
1d2808fd | 761 | .flags = ATA_FLAG_SLAVE_POSS, |
14bdef98 EIB |
762 | .pio_mask = ATA_PIO4, |
763 | .mwdma_mask = ATA_MWDMA2, | |
bf6263a8 | 764 | .udma_mask = ATA_UDMA5, |
669a5db4 JG |
765 | .port_ops = &hpt370_port_ops |
766 | }; | |
767 | /* HPT370A - UDMA100 */ | |
1626aeb8 | 768 | static const struct ata_port_info info_hpt370a = { |
1d2808fd | 769 | .flags = ATA_FLAG_SLAVE_POSS, |
14bdef98 EIB |
770 | .pio_mask = ATA_PIO4, |
771 | .mwdma_mask = ATA_MWDMA2, | |
bf6263a8 | 772 | .udma_mask = ATA_UDMA5, |
669a5db4 JG |
773 | .port_ops = &hpt370a_port_ops |
774 | }; | |
fc2698d5 | 775 | /* HPT370 - UDMA66 */ |
1626aeb8 | 776 | static const struct ata_port_info info_hpt370_33 = { |
1d2808fd | 777 | .flags = ATA_FLAG_SLAVE_POSS, |
14bdef98 EIB |
778 | .pio_mask = ATA_PIO4, |
779 | .mwdma_mask = ATA_MWDMA2, | |
fc2698d5 | 780 | .udma_mask = ATA_UDMA4, |
fcc2f69a AC |
781 | .port_ops = &hpt370_port_ops |
782 | }; | |
fc2698d5 | 783 | /* HPT370A - UDMA66 */ |
1626aeb8 | 784 | static const struct ata_port_info info_hpt370a_33 = { |
1d2808fd | 785 | .flags = ATA_FLAG_SLAVE_POSS, |
14bdef98 EIB |
786 | .pio_mask = ATA_PIO4, |
787 | .mwdma_mask = ATA_MWDMA2, | |
fc2698d5 | 788 | .udma_mask = ATA_UDMA4, |
fcc2f69a AC |
789 | .port_ops = &hpt370a_port_ops |
790 | }; | |
8e834c2e | 791 | /* HPT372 - UDMA133 */ |
1626aeb8 | 792 | static const struct ata_port_info info_hpt372 = { |
1d2808fd | 793 | .flags = ATA_FLAG_SLAVE_POSS, |
14bdef98 EIB |
794 | .pio_mask = ATA_PIO4, |
795 | .mwdma_mask = ATA_MWDMA2, | |
bf6263a8 | 796 | .udma_mask = ATA_UDMA6, |
669a5db4 JG |
797 | .port_ops = &hpt372_port_ops |
798 | }; | |
8e834c2e SS |
799 | /* HPT371, 302 - UDMA133 */ |
800 | static const struct ata_port_info info_hpt302 = { | |
801 | .flags = ATA_FLAG_SLAVE_POSS, | |
802 | .pio_mask = ATA_PIO4, | |
803 | .mwdma_mask = ATA_MWDMA2, | |
804 | .udma_mask = ATA_UDMA6, | |
805 | .port_ops = &hpt302_port_ops | |
806 | }; | |
defed559 | 807 | /* HPT374 - UDMA100, function 1 uses different cable_detect method */ |
a1efdaba TH |
808 | static const struct ata_port_info info_hpt374_fn0 = { |
809 | .flags = ATA_FLAG_SLAVE_POSS, | |
14bdef98 EIB |
810 | .pio_mask = ATA_PIO4, |
811 | .mwdma_mask = ATA_MWDMA2, | |
a1efdaba TH |
812 | .udma_mask = ATA_UDMA5, |
813 | .port_ops = &hpt372_port_ops | |
814 | }; | |
815 | static const struct ata_port_info info_hpt374_fn1 = { | |
1d2808fd | 816 | .flags = ATA_FLAG_SLAVE_POSS, |
14bdef98 EIB |
817 | .pio_mask = ATA_PIO4, |
818 | .mwdma_mask = ATA_MWDMA2, | |
bf6263a8 | 819 | .udma_mask = ATA_UDMA5, |
a1efdaba | 820 | .port_ops = &hpt374_fn1_port_ops |
669a5db4 JG |
821 | }; |
822 | ||
823 | static const int MHz[4] = { 33, 40, 50, 66 }; | |
1626aeb8 | 824 | void *private_data = NULL; |
887125e3 | 825 | const struct ata_port_info *ppi[] = { NULL, NULL }; |
89d3b360 | 826 | u8 rev = dev->revision; |
669a5db4 | 827 | u8 irqmask; |
fcc2f69a | 828 | u8 mcr1; |
669a5db4 | 829 | u32 freq; |
fcc2f69a | 830 | int prefer_dpll = 1; |
a617c09f | 831 | |
fcc2f69a | 832 | unsigned long iobase = pci_resource_start(dev, 4); |
669a5db4 JG |
833 | |
834 | const struct hpt_chip *chip_table; | |
835 | int clock_slot; | |
f08048e9 TH |
836 | int rc; |
837 | ||
838 | rc = pcim_enable_device(dev); | |
839 | if (rc) | |
840 | return rc; | |
669a5db4 | 841 | |
910f7bb1 SS |
842 | switch (dev->device) { |
843 | case PCI_DEVICE_ID_TTI_HPT366: | |
669a5db4 JG |
844 | /* May be a later chip in disguise. Check */ |
845 | /* Older chips are in the HPT366 driver. Ignore them */ | |
89d3b360 | 846 | if (rev < 3) |
669a5db4 JG |
847 | return -ENODEV; |
848 | /* N series chips have their own driver. Ignore */ | |
89d3b360 | 849 | if (rev == 6) |
669a5db4 JG |
850 | return -ENODEV; |
851 | ||
49bfbd38 SS |
852 | switch (rev) { |
853 | case 3: | |
854 | ppi[0] = &info_hpt370; | |
855 | chip_table = &hpt370; | |
856 | prefer_dpll = 0; | |
857 | break; | |
858 | case 4: | |
859 | ppi[0] = &info_hpt370a; | |
860 | chip_table = &hpt370a; | |
861 | prefer_dpll = 0; | |
862 | break; | |
863 | case 5: | |
864 | ppi[0] = &info_hpt372; | |
865 | chip_table = &hpt372; | |
866 | break; | |
867 | default: | |
8d7b1c70 JP |
868 | pr_err("Unknown HPT366 subtype, please report (%d)\n", |
869 | rev); | |
49bfbd38 | 870 | return -ENODEV; |
669a5db4 | 871 | } |
910f7bb1 SS |
872 | break; |
873 | case PCI_DEVICE_ID_TTI_HPT372: | |
874 | /* 372N if rev >= 2 */ | |
875 | if (rev >= 2) | |
876 | return -ENODEV; | |
877 | ppi[0] = &info_hpt372; | |
878 | chip_table = &hpt372a; | |
879 | break; | |
880 | case PCI_DEVICE_ID_TTI_HPT302: | |
881 | /* 302N if rev > 1 */ | |
882 | if (rev > 1) | |
883 | return -ENODEV; | |
884 | ppi[0] = &info_hpt302; | |
885 | /* Check this */ | |
886 | chip_table = &hpt302; | |
887 | break; | |
888 | case PCI_DEVICE_ID_TTI_HPT371: | |
889 | if (rev > 1) | |
890 | return -ENODEV; | |
891 | ppi[0] = &info_hpt302; | |
892 | chip_table = &hpt371; | |
893 | /* | |
894 | * Single channel device, master is not present but the BIOS | |
895 | * (or us for non x86) must mark it absent | |
896 | */ | |
897 | pci_read_config_byte(dev, 0x50, &mcr1); | |
898 | mcr1 &= ~0x04; | |
899 | pci_write_config_byte(dev, 0x50, mcr1); | |
900 | break; | |
901 | case PCI_DEVICE_ID_TTI_HPT374: | |
902 | chip_table = &hpt374; | |
903 | if (!(PCI_FUNC(dev->devfn) & 1)) | |
904 | *ppi = &info_hpt374_fn0; | |
905 | else | |
906 | *ppi = &info_hpt374_fn1; | |
907 | break; | |
908 | default: | |
8d7b1c70 | 909 | pr_err("PCI table is bogus, please report (%d)\n", dev->device); |
910f7bb1 | 910 | return -ENODEV; |
669a5db4 JG |
911 | } |
912 | /* Ok so this is a chip we support */ | |
913 | ||
914 | pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, (L1_CACHE_BYTES / 4)); | |
915 | pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x78); | |
916 | pci_write_config_byte(dev, PCI_MIN_GNT, 0x08); | |
917 | pci_write_config_byte(dev, PCI_MAX_LAT, 0x08); | |
918 | ||
919 | pci_read_config_byte(dev, 0x5A, &irqmask); | |
920 | irqmask &= ~0x10; | |
921 | pci_write_config_byte(dev, 0x5a, irqmask); | |
922 | ||
923 | /* | |
924 | * default to pci clock. make sure MA15/16 are set to output | |
925 | * to prevent drives having problems with 40-pin cables. Needed | |
926 | * for some drives such as IBM-DTLA which will not enter ready | |
927 | * state on reset when PDIAG is a input. | |
928 | */ | |
929 | ||
85cd7251 | 930 | pci_write_config_byte(dev, 0x5b, 0x23); |
a617c09f | 931 | |
fcc2f69a AC |
932 | /* |
933 | * HighPoint does this for HPT372A. | |
934 | * NOTE: This register is only writeable via I/O space. | |
935 | */ | |
936 | if (chip_table == &hpt372a) | |
937 | outb(0x0e, iobase + 0x9c); | |
85cd7251 | 938 | |
49bfbd38 SS |
939 | /* |
940 | * Some devices do not let this value be accessed via PCI space | |
941 | * according to the old driver. In addition we must use the value | |
942 | * from FN 0 on the HPT374. | |
943 | */ | |
73946f9f AC |
944 | |
945 | if (chip_table == &hpt374) { | |
946 | freq = hpt374_read_freq(dev); | |
947 | if (freq == 0) | |
948 | return -ENODEV; | |
949 | } else | |
950 | freq = inl(iobase + 0x90); | |
fcc2f69a | 951 | |
669a5db4 JG |
952 | if ((freq >> 12) != 0xABCDE) { |
953 | int i; | |
954 | u8 sr; | |
955 | u32 total = 0; | |
85cd7251 | 956 | |
8d7b1c70 | 957 | pr_warn("BIOS has not set timing clocks\n"); |
85cd7251 | 958 | |
669a5db4 | 959 | /* This is the process the HPT371 BIOS is reported to use */ |
49bfbd38 | 960 | for (i = 0; i < 128; i++) { |
669a5db4 | 961 | pci_read_config_byte(dev, 0x78, &sr); |
fcc2f69a | 962 | total += sr & 0x1FF; |
669a5db4 JG |
963 | udelay(15); |
964 | } | |
965 | freq = total / 128; | |
966 | } | |
967 | freq &= 0x1FF; | |
85cd7251 | 968 | |
669a5db4 JG |
969 | /* |
970 | * Turn the frequency check into a band and then find a timing | |
971 | * table to match it. | |
972 | */ | |
a617c09f | 973 | |
669a5db4 | 974 | clock_slot = hpt37x_clock_slot(freq, chip_table->base); |
fcc2f69a | 975 | if (chip_table->clocks[clock_slot] == NULL || prefer_dpll) { |
669a5db4 JG |
976 | /* |
977 | * We need to try PLL mode instead | |
fcc2f69a AC |
978 | * |
979 | * For non UDMA133 capable devices we should | |
980 | * use a 50MHz DPLL by choice | |
669a5db4 | 981 | */ |
fcc2f69a | 982 | unsigned int f_low, f_high; |
960c8a10 | 983 | int dpll, adjust; |
a617c09f | 984 | |
960c8a10 | 985 | /* Compute DPLL */ |
887125e3 | 986 | dpll = (ppi[0]->udma_mask & 0xC0) ? 3 : 2; |
a617c09f | 987 | |
960c8a10 | 988 | f_low = (MHz[clock_slot] * 48) / MHz[dpll]; |
fcc2f69a | 989 | f_high = f_low + 2; |
960c8a10 AC |
990 | if (clock_slot > 1) |
991 | f_high += 2; | |
fcc2f69a AC |
992 | |
993 | /* Select the DPLL clock. */ | |
994 | pci_write_config_byte(dev, 0x5b, 0x21); | |
49bfbd38 SS |
995 | pci_write_config_dword(dev, 0x5C, |
996 | (f_high << 16) | f_low | 0x100); | |
85cd7251 | 997 | |
49bfbd38 | 998 | for (adjust = 0; adjust < 8; adjust++) { |
669a5db4 JG |
999 | if (hpt37x_calibrate_dpll(dev)) |
1000 | break; | |
49bfbd38 SS |
1001 | /* |
1002 | * See if it'll settle at a fractionally | |
1003 | * different clock | |
1004 | */ | |
64a81709 AC |
1005 | if (adjust & 1) |
1006 | f_low -= adjust >> 1; | |
1007 | else | |
1008 | f_high += adjust >> 1; | |
49bfbd38 SS |
1009 | pci_write_config_dword(dev, 0x5C, |
1010 | (f_high << 16) | f_low | 0x100); | |
669a5db4 JG |
1011 | } |
1012 | if (adjust == 8) { | |
8d7b1c70 | 1013 | pr_err("DPLL did not stabilize!\n"); |
669a5db4 JG |
1014 | return -ENODEV; |
1015 | } | |
960c8a10 | 1016 | if (dpll == 3) |
1626aeb8 | 1017 | private_data = (void *)hpt37x_timings_66; |
fcc2f69a | 1018 | else |
1626aeb8 | 1019 | private_data = (void *)hpt37x_timings_50; |
85cd7251 | 1020 | |
8d7b1c70 | 1021 | pr_info("bus clock %dMHz, using %dMHz DPLL\n", |
40d69ba0 | 1022 | MHz[clock_slot], MHz[dpll]); |
669a5db4 | 1023 | } else { |
1626aeb8 | 1024 | private_data = (void *)chip_table->clocks[clock_slot]; |
669a5db4 | 1025 | /* |
a4734468 AC |
1026 | * Perform a final fixup. Note that we will have used the |
1027 | * DPLL on the HPT372 which means we don't have to worry | |
1028 | * about lack of UDMA133 support on lower clocks | |
49bfbd38 | 1029 | */ |
85cd7251 | 1030 | |
887125e3 TH |
1031 | if (clock_slot < 2 && ppi[0] == &info_hpt370) |
1032 | ppi[0] = &info_hpt370_33; | |
1033 | if (clock_slot < 2 && ppi[0] == &info_hpt370a) | |
1034 | ppi[0] = &info_hpt370a_33; | |
40d69ba0 | 1035 | |
8d7b1c70 | 1036 | pr_info("%s using %dMHz bus clock\n", |
40d69ba0 | 1037 | chip_table->name, MHz[clock_slot]); |
669a5db4 | 1038 | } |
fcc2f69a | 1039 | |
669a5db4 | 1040 | /* Now kick off ATA set up */ |
1c5afdf7 | 1041 | return ata_pci_bmdma_init_one(dev, ppi, &hpt37x_sht, private_data, 0); |
669a5db4 JG |
1042 | } |
1043 | ||
2d2744fc JG |
1044 | static const struct pci_device_id hpt37x[] = { |
1045 | { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT366), }, | |
1046 | { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT371), }, | |
1047 | { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT372), }, | |
1048 | { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT374), }, | |
1049 | { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT302), }, | |
1050 | ||
1051 | { }, | |
669a5db4 JG |
1052 | }; |
1053 | ||
1054 | static struct pci_driver hpt37x_pci_driver = { | |
49bfbd38 | 1055 | .name = DRV_NAME, |
669a5db4 | 1056 | .id_table = hpt37x, |
49bfbd38 | 1057 | .probe = hpt37x_init_one, |
669a5db4 JG |
1058 | .remove = ata_pci_remove_one |
1059 | }; | |
1060 | ||
2fc75da0 | 1061 | module_pci_driver(hpt37x_pci_driver); |
669a5db4 | 1062 | |
669a5db4 JG |
1063 | MODULE_AUTHOR("Alan Cox"); |
1064 | MODULE_DESCRIPTION("low-level driver for the Highpoint HPT37x/30x"); | |
1065 | MODULE_LICENSE("GPL"); | |
1066 | MODULE_DEVICE_TABLE(pci, hpt37x); | |
1067 | MODULE_VERSION(DRV_VERSION); |