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669a5db4 | 1 | /* |
c343a839 | 2 | * pata_it821x.c - IT821x PATA for new ATA layer |
669a5db4 JG |
3 | * (C) 2005 Red Hat Inc |
4 | * Alan Cox <alan@redhat.com> | |
5 | * | |
6 | * based upon | |
7 | * | |
8 | * it821x.c | |
85cd7251 | 9 | * |
669a5db4 JG |
10 | * linux/drivers/ide/pci/it821x.c Version 0.09 December 2004 |
11 | * | |
12 | * Copyright (C) 2004 Red Hat <alan@redhat.com> | |
13 | * | |
14 | * May be copied or modified under the terms of the GNU General Public License | |
15 | * Based in part on the ITE vendor provided SCSI driver. | |
16 | * | |
17 | * Documentation available from | |
18 | * http://www.ite.com.tw/pc/IT8212F_V04.pdf | |
19 | * Some other documents are NDA. | |
20 | * | |
21 | * The ITE8212 isn't exactly a standard IDE controller. It has two | |
22 | * modes. In pass through mode then it is an IDE controller. In its smart | |
23 | * mode its actually quite a capable hardware raid controller disguised | |
24 | * as an IDE controller. Smart mode only understands DMA read/write and | |
25 | * identify, none of the fancier commands apply. The IT8211 is identical | |
26 | * in other respects but lacks the raid mode. | |
27 | * | |
28 | * Errata: | |
29 | * o Rev 0x10 also requires master/slave hold the same DMA timings and | |
30 | * cannot do ATAPI MWDMA. | |
31 | * o The identify data for raid volumes lacks CHS info (technically ok) | |
32 | * but also fails to set the LBA28 and other bits. We fix these in | |
33 | * the IDE probe quirk code. | |
34 | * o If you write LBA48 sized I/O's (ie > 256 sector) in smart mode | |
35 | * raid then the controller firmware dies | |
36 | * o Smart mode without RAID doesn't clear all the necessary identify | |
37 | * bits to reduce the command set to the one used | |
38 | * | |
39 | * This has a few impacts on the driver | |
40 | * - In pass through mode we do all the work you would expect | |
41 | * - In smart mode the clocking set up is done by the controller generally | |
42 | * but we must watch the other limits and filter. | |
43 | * - There are a few extra vendor commands that actually talk to the | |
44 | * controller but only work PIO with no IRQ. | |
45 | * | |
46 | * Vendor areas of the identify block in smart mode are used for the | |
47 | * timing and policy set up. Each HDD in raid mode also has a serial | |
48 | * block on the disk. The hardware extra commands are get/set chip status, | |
49 | * rebuild, get rebuild status. | |
50 | * | |
51 | * In Linux the driver supports pass through mode as if the device was | |
52 | * just another IDE controller. If the smart mode is running then | |
53 | * volumes are managed by the controller firmware and each IDE "disk" | |
54 | * is a raid volume. Even more cute - the controller can do automated | |
55 | * hotplug and rebuild. | |
56 | * | |
57 | * The pass through controller itself is a little demented. It has a | |
58 | * flaw that it has a single set of PIO/MWDMA timings per channel so | |
59 | * non UDMA devices restrict each others performance. It also has a | |
60 | * single clock source per channel so mixed UDMA100/133 performance | |
61 | * isn't perfect and we have to pick a clock. Thankfully none of this | |
62 | * matters in smart mode. ATAPI DMA is not currently supported. | |
63 | * | |
64 | * It seems the smart mode is a win for RAID1/RAID10 but otherwise not. | |
65 | * | |
66 | * TODO | |
67 | * - ATAPI and other speed filtering | |
669a5db4 JG |
68 | * - RAID configuration ioctls |
69 | */ | |
70 | ||
71 | #include <linux/kernel.h> | |
72 | #include <linux/module.h> | |
73 | #include <linux/pci.h> | |
74 | #include <linux/init.h> | |
75 | #include <linux/blkdev.h> | |
76 | #include <linux/delay.h> | |
77 | #include <scsi/scsi_host.h> | |
78 | #include <linux/libata.h> | |
79 | ||
80 | ||
81 | #define DRV_NAME "pata_it821x" | |
a0fcdc02 | 82 | #define DRV_VERSION "0.3.6" |
669a5db4 JG |
83 | |
84 | struct it821x_dev | |
85 | { | |
86 | unsigned int smart:1, /* Are we in smart raid mode */ | |
87 | timing10:1; /* Rev 0x10 */ | |
88 | u8 clock_mode; /* 0, ATA_50 or ATA_66 */ | |
89 | u8 want[2][2]; /* Mode/Pri log for master slave */ | |
90 | /* We need these for switching the clock when DMA goes on/off | |
91 | The high byte is the 66Mhz timing */ | |
92 | u16 pio[2]; /* Cached PIO values */ | |
93 | u16 mwdma[2]; /* Cached MWDMA values */ | |
94 | u16 udma[2]; /* Cached UDMA values (per drive) */ | |
95 | u16 last_device; /* Master or slave loaded ? */ | |
96 | }; | |
97 | ||
98 | #define ATA_66 0 | |
99 | #define ATA_50 1 | |
100 | #define ATA_ANY 2 | |
101 | ||
102 | #define UDMA_OFF 0 | |
103 | #define MWDMA_OFF 0 | |
104 | ||
105 | /* | |
106 | * We allow users to force the card into non raid mode without | |
107 | * flashing the alternative BIOS. This is also neccessary right now | |
108 | * for embedded platforms that cannot run a PC BIOS but are using this | |
109 | * device. | |
110 | */ | |
111 | ||
112 | static int it8212_noraid; | |
113 | ||
669a5db4 JG |
114 | /** |
115 | * it821x_program - program the PIO/MWDMA registers | |
116 | * @ap: ATA port | |
117 | * @adev: Device to program | |
118 | * @timing: Timing value (66Mhz in top 8bits, 50 in the low 8) | |
119 | * | |
120 | * Program the PIO/MWDMA timing for this channel according to the | |
121 | * current clock. These share the same register so are managed by | |
122 | * the DMA start/stop sequence as with the old driver. | |
123 | */ | |
124 | ||
125 | static void it821x_program(struct ata_port *ap, struct ata_device *adev, u16 timing) | |
126 | { | |
127 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); | |
128 | struct it821x_dev *itdev = ap->private_data; | |
129 | int channel = ap->port_no; | |
130 | u8 conf; | |
131 | ||
132 | /* Program PIO/MWDMA timing bits */ | |
133 | if (itdev->clock_mode == ATA_66) | |
134 | conf = timing >> 8; | |
135 | else | |
136 | conf = timing & 0xFF; | |
137 | pci_write_config_byte(pdev, 0x54 + 4 * channel, conf); | |
138 | } | |
139 | ||
140 | ||
141 | /** | |
142 | * it821x_program_udma - program the UDMA registers | |
143 | * @ap: ATA port | |
144 | * @adev: ATA device to update | |
145 | * @timing: Timing bits. Top 8 are for 66Mhz bottom for 50Mhz | |
146 | * | |
147 | * Program the UDMA timing for this drive according to the | |
148 | * current clock. Handles the dual clocks and also knows about | |
149 | * the errata on the 0x10 revision. The UDMA errata is partly handled | |
150 | * here and partly in start_dma. | |
151 | */ | |
152 | ||
153 | static void it821x_program_udma(struct ata_port *ap, struct ata_device *adev, u16 timing) | |
154 | { | |
155 | struct it821x_dev *itdev = ap->private_data; | |
156 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); | |
157 | int channel = ap->port_no; | |
158 | int unit = adev->devno; | |
159 | u8 conf; | |
160 | ||
161 | /* Program UDMA timing bits */ | |
162 | if (itdev->clock_mode == ATA_66) | |
163 | conf = timing >> 8; | |
164 | else | |
165 | conf = timing & 0xFF; | |
166 | if (itdev->timing10 == 0) | |
167 | pci_write_config_byte(pdev, 0x56 + 4 * channel + unit, conf); | |
168 | else { | |
169 | /* Early revision must be programmed for both together */ | |
170 | pci_write_config_byte(pdev, 0x56 + 4 * channel, conf); | |
171 | pci_write_config_byte(pdev, 0x56 + 4 * channel + 1, conf); | |
172 | } | |
173 | } | |
174 | ||
175 | /** | |
176 | * it821x_clock_strategy | |
177 | * @ap: ATA interface | |
178 | * @adev: ATA device being updated | |
179 | * | |
180 | * Select between the 50 and 66Mhz base clocks to get the best | |
181 | * results for this interface. | |
182 | */ | |
183 | ||
184 | static void it821x_clock_strategy(struct ata_port *ap, struct ata_device *adev) | |
185 | { | |
186 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); | |
187 | struct it821x_dev *itdev = ap->private_data; | |
188 | u8 unit = adev->devno; | |
189 | struct ata_device *pair = ata_dev_pair(adev); | |
190 | ||
191 | int clock, altclock; | |
192 | u8 v; | |
193 | int sel = 0; | |
194 | ||
195 | /* Look for the most wanted clocking */ | |
196 | if (itdev->want[0][0] > itdev->want[1][0]) { | |
197 | clock = itdev->want[0][1]; | |
198 | altclock = itdev->want[1][1]; | |
199 | } else { | |
200 | clock = itdev->want[1][1]; | |
201 | altclock = itdev->want[0][1]; | |
202 | } | |
203 | ||
204 | /* Master doesn't care does the slave ? */ | |
205 | if (clock == ATA_ANY) | |
206 | clock = altclock; | |
207 | ||
208 | /* Nobody cares - keep the same clock */ | |
209 | if (clock == ATA_ANY) | |
210 | return; | |
211 | /* No change */ | |
212 | if (clock == itdev->clock_mode) | |
213 | return; | |
214 | ||
215 | /* Load this into the controller */ | |
216 | if (clock == ATA_66) | |
217 | itdev->clock_mode = ATA_66; | |
218 | else { | |
219 | itdev->clock_mode = ATA_50; | |
220 | sel = 1; | |
221 | } | |
222 | pci_read_config_byte(pdev, 0x50, &v); | |
223 | v &= ~(1 << (1 + ap->port_no)); | |
224 | v |= sel << (1 + ap->port_no); | |
225 | pci_write_config_byte(pdev, 0x50, v); | |
226 | ||
227 | /* | |
228 | * Reprogram the UDMA/PIO of the pair drive for the switch | |
229 | * MWDMA will be dealt with by the dma switcher | |
230 | */ | |
231 | if (pair && itdev->udma[1-unit] != UDMA_OFF) { | |
232 | it821x_program_udma(ap, pair, itdev->udma[1-unit]); | |
233 | it821x_program(ap, pair, itdev->pio[1-unit]); | |
234 | } | |
235 | /* | |
236 | * Reprogram the UDMA/PIO of our drive for the switch. | |
237 | * MWDMA will be dealt with by the dma switcher | |
238 | */ | |
239 | if (itdev->udma[unit] != UDMA_OFF) { | |
240 | it821x_program_udma(ap, adev, itdev->udma[unit]); | |
241 | it821x_program(ap, adev, itdev->pio[unit]); | |
242 | } | |
243 | } | |
244 | ||
245 | /** | |
246 | * it821x_passthru_set_piomode - set PIO mode data | |
247 | * @ap: ATA interface | |
248 | * @adev: ATA device | |
249 | * | |
250 | * Configure for PIO mode. This is complicated as the register is | |
251 | * shared by PIO and MWDMA and for both channels. | |
252 | */ | |
253 | ||
254 | static void it821x_passthru_set_piomode(struct ata_port *ap, struct ata_device *adev) | |
255 | { | |
256 | /* Spec says 89 ref driver uses 88 */ | |
257 | static const u16 pio[] = { 0xAA88, 0xA382, 0xA181, 0x3332, 0x3121 }; | |
258 | static const u8 pio_want[] = { ATA_66, ATA_66, ATA_66, ATA_66, ATA_ANY }; | |
259 | ||
260 | struct it821x_dev *itdev = ap->private_data; | |
261 | int unit = adev->devno; | |
262 | int mode_wanted = adev->pio_mode - XFER_PIO_0; | |
85cd7251 | 263 | |
669a5db4 JG |
264 | /* We prefer 66Mhz clock for PIO 0-3, don't care for PIO4 */ |
265 | itdev->want[unit][1] = pio_want[mode_wanted]; | |
266 | itdev->want[unit][0] = 1; /* PIO is lowest priority */ | |
267 | itdev->pio[unit] = pio[mode_wanted]; | |
268 | it821x_clock_strategy(ap, adev); | |
269 | it821x_program(ap, adev, itdev->pio[unit]); | |
270 | } | |
271 | ||
272 | /** | |
273 | * it821x_passthru_set_dmamode - set initial DMA mode data | |
274 | * @ap: ATA interface | |
275 | * @adev: ATA device | |
276 | * | |
277 | * Set up the DMA modes. The actions taken depend heavily on the mode | |
85cd7251 | 278 | * to use. If UDMA is used as is hopefully the usual case then the |
669a5db4 JG |
279 | * timing register is private and we need only consider the clock. If |
280 | * we are using MWDMA then we have to manage the setting ourself as | |
281 | * we switch devices and mode. | |
282 | */ | |
283 | ||
284 | static void it821x_passthru_set_dmamode(struct ata_port *ap, struct ata_device *adev) | |
285 | { | |
286 | static const u16 dma[] = { 0x8866, 0x3222, 0x3121 }; | |
287 | static const u8 mwdma_want[] = { ATA_ANY, ATA_66, ATA_ANY }; | |
288 | static const u16 udma[] = { 0x4433, 0x4231, 0x3121, 0x2121, 0x1111, 0x2211, 0x1111 }; | |
289 | static const u8 udma_want[] = { ATA_ANY, ATA_50, ATA_ANY, ATA_66, ATA_66, ATA_50, ATA_66 }; | |
290 | ||
291 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); | |
292 | struct it821x_dev *itdev = ap->private_data; | |
293 | int channel = ap->port_no; | |
294 | int unit = adev->devno; | |
295 | u8 conf; | |
296 | ||
297 | if (adev->dma_mode >= XFER_UDMA_0) { | |
298 | int mode_wanted = adev->dma_mode - XFER_UDMA_0; | |
85cd7251 | 299 | |
669a5db4 JG |
300 | itdev->want[unit][1] = udma_want[mode_wanted]; |
301 | itdev->want[unit][0] = 3; /* UDMA is high priority */ | |
302 | itdev->mwdma[unit] = MWDMA_OFF; | |
303 | itdev->udma[unit] = udma[mode_wanted]; | |
304 | if (mode_wanted >= 5) | |
305 | itdev->udma[unit] |= 0x8080; /* UDMA 5/6 select on */ | |
306 | ||
307 | /* UDMA on. Again revision 0x10 must do the pair */ | |
308 | pci_read_config_byte(pdev, 0x50, &conf); | |
309 | if (itdev->timing10) | |
310 | conf &= channel ? 0x9F: 0xE7; | |
311 | else | |
312 | conf &= ~ (1 << (3 + 2 * channel + unit)); | |
313 | pci_write_config_byte(pdev, 0x50, conf); | |
314 | it821x_clock_strategy(ap, adev); | |
315 | it821x_program_udma(ap, adev, itdev->udma[unit]); | |
316 | } else { | |
317 | int mode_wanted = adev->dma_mode - XFER_MW_DMA_0; | |
85cd7251 | 318 | |
669a5db4 JG |
319 | itdev->want[unit][1] = mwdma_want[mode_wanted]; |
320 | itdev->want[unit][0] = 2; /* MWDMA is low priority */ | |
321 | itdev->mwdma[unit] = dma[mode_wanted]; | |
322 | itdev->udma[unit] = UDMA_OFF; | |
323 | ||
324 | /* UDMA bits off - Revision 0x10 do them in pairs */ | |
325 | pci_read_config_byte(pdev, 0x50, &conf); | |
326 | if (itdev->timing10) | |
327 | conf |= channel ? 0x60: 0x18; | |
328 | else | |
329 | conf |= 1 << (3 + 2 * channel + unit); | |
330 | pci_write_config_byte(pdev, 0x50, conf); | |
331 | it821x_clock_strategy(ap, adev); | |
332 | } | |
333 | } | |
334 | ||
335 | /** | |
336 | * it821x_passthru_dma_start - DMA start callback | |
337 | * @qc: Command in progress | |
338 | * | |
339 | * Usually drivers set the DMA timing at the point the set_dmamode call | |
85cd7251 | 340 | * is made. IT821x however requires we load new timings on the |
669a5db4 JG |
341 | * transitions in some cases. |
342 | */ | |
343 | ||
344 | static void it821x_passthru_bmdma_start(struct ata_queued_cmd *qc) | |
345 | { | |
346 | struct ata_port *ap = qc->ap; | |
347 | struct ata_device *adev = qc->dev; | |
348 | struct it821x_dev *itdev = ap->private_data; | |
349 | int unit = adev->devno; | |
350 | ||
351 | if (itdev->mwdma[unit] != MWDMA_OFF) | |
352 | it821x_program(ap, adev, itdev->mwdma[unit]); | |
353 | else if (itdev->udma[unit] != UDMA_OFF && itdev->timing10) | |
354 | it821x_program_udma(ap, adev, itdev->udma[unit]); | |
355 | ata_bmdma_start(qc); | |
356 | } | |
357 | ||
358 | /** | |
359 | * it821x_passthru_dma_stop - DMA stop callback | |
360 | * @qc: ATA command | |
361 | * | |
362 | * We loaded new timings in dma_start, as a result we need to restore | |
363 | * the PIO timings in dma_stop so that the next command issue gets the | |
364 | * right clock values. | |
365 | */ | |
366 | ||
367 | static void it821x_passthru_bmdma_stop(struct ata_queued_cmd *qc) | |
368 | { | |
369 | struct ata_port *ap = qc->ap; | |
370 | struct ata_device *adev = qc->dev; | |
371 | struct it821x_dev *itdev = ap->private_data; | |
372 | int unit = adev->devno; | |
373 | ||
374 | ata_bmdma_stop(qc); | |
375 | if (itdev->mwdma[unit] != MWDMA_OFF) | |
376 | it821x_program(ap, adev, itdev->pio[unit]); | |
377 | } | |
378 | ||
379 | ||
380 | /** | |
381 | * it821x_passthru_dev_select - Select master/slave | |
382 | * @ap: ATA port | |
383 | * @device: Device number (not pointer) | |
384 | * | |
385 | * Device selection hook. If neccessary perform clock switching | |
386 | */ | |
85cd7251 | 387 | |
669a5db4 JG |
388 | static void it821x_passthru_dev_select(struct ata_port *ap, |
389 | unsigned int device) | |
390 | { | |
391 | struct it821x_dev *itdev = ap->private_data; | |
392 | if (itdev && device != itdev->last_device) { | |
393 | struct ata_device *adev = &ap->device[device]; | |
394 | it821x_program(ap, adev, itdev->pio[adev->devno]); | |
395 | itdev->last_device = device; | |
396 | } | |
397 | ata_std_dev_select(ap, device); | |
398 | } | |
399 | ||
400 | /** | |
401 | * it821x_smart_qc_issue_prot - wrap qc issue prot | |
402 | * @qc: command | |
403 | * | |
404 | * Wrap the command issue sequence for the IT821x. We need to | |
405 | * perform out own device selection timing loads before the | |
406 | * usual happenings kick off | |
407 | */ | |
85cd7251 | 408 | |
669a5db4 JG |
409 | static unsigned int it821x_smart_qc_issue_prot(struct ata_queued_cmd *qc) |
410 | { | |
411 | switch(qc->tf.command) | |
412 | { | |
413 | /* Commands the firmware supports */ | |
414 | case ATA_CMD_READ: | |
415 | case ATA_CMD_READ_EXT: | |
416 | case ATA_CMD_WRITE: | |
417 | case ATA_CMD_WRITE_EXT: | |
418 | case ATA_CMD_PIO_READ: | |
419 | case ATA_CMD_PIO_READ_EXT: | |
420 | case ATA_CMD_PIO_WRITE: | |
421 | case ATA_CMD_PIO_WRITE_EXT: | |
422 | case ATA_CMD_READ_MULTI: | |
423 | case ATA_CMD_READ_MULTI_EXT: | |
424 | case ATA_CMD_WRITE_MULTI: | |
425 | case ATA_CMD_WRITE_MULTI_EXT: | |
426 | case ATA_CMD_ID_ATA: | |
427 | /* Arguably should just no-op this one */ | |
428 | case ATA_CMD_SET_FEATURES: | |
429 | return ata_qc_issue_prot(qc); | |
430 | } | |
431 | printk(KERN_DEBUG "it821x: can't process command 0x%02X\n", qc->tf.command); | |
432 | return AC_ERR_INVALID; | |
433 | } | |
434 | ||
435 | /** | |
436 | * it821x_passthru_qc_issue_prot - wrap qc issue prot | |
437 | * @qc: command | |
438 | * | |
439 | * Wrap the command issue sequence for the IT821x. We need to | |
440 | * perform out own device selection timing loads before the | |
441 | * usual happenings kick off | |
442 | */ | |
85cd7251 | 443 | |
669a5db4 JG |
444 | static unsigned int it821x_passthru_qc_issue_prot(struct ata_queued_cmd *qc) |
445 | { | |
446 | it821x_passthru_dev_select(qc->ap, qc->dev->devno); | |
447 | return ata_qc_issue_prot(qc); | |
448 | } | |
449 | ||
450 | /** | |
451 | * it821x_smart_set_mode - mode setting | |
452 | * @ap: interface to set up | |
b229a7b0 | 453 | * @unused: device that failed (error only) |
669a5db4 JG |
454 | * |
455 | * Use a non standard set_mode function. We don't want to be tuned. | |
456 | * The BIOS configured everything. Our job is not to fiddle. We | |
457 | * read the dma enabled bits from the PCI configuration of the device | |
85cd7251 | 458 | * and respect them. |
669a5db4 | 459 | */ |
85cd7251 | 460 | |
b229a7b0 | 461 | static int it821x_smart_set_mode(struct ata_port *ap, struct ata_device **unused) |
669a5db4 JG |
462 | { |
463 | int dma_enabled = 0; | |
464 | int i; | |
465 | ||
466 | /* Bits 5 and 6 indicate if DMA is active on master/slave */ | |
467 | /* It is possible that BMDMA isn't allocated */ | |
468 | if (ap->ioaddr.bmdma_addr) | |
0d5ff566 | 469 | dma_enabled = ioread8(ap->ioaddr.bmdma_addr + ATA_DMA_CMD); |
85cd7251 | 470 | |
669a5db4 JG |
471 | for (i = 0; i < ATA_MAX_DEVICES; i++) { |
472 | struct ata_device *dev = &ap->device[i]; | |
473 | if (ata_dev_enabled(dev)) { | |
474 | /* We don't really care */ | |
475 | dev->pio_mode = XFER_PIO_0; | |
476 | dev->dma_mode = XFER_MW_DMA_0; | |
85cd7251 | 477 | /* We do need the right mode information for DMA or PIO |
669a5db4 JG |
478 | and this comes from the current configuration flags */ |
479 | if (dma_enabled & (1 << (5 + i))) { | |
616ece2e | 480 | ata_dev_printk(dev, KERN_INFO, "configured for DMA\n"); |
669a5db4 JG |
481 | dev->xfer_mode = XFER_MW_DMA_0; |
482 | dev->xfer_shift = ATA_SHIFT_MWDMA; | |
483 | dev->flags &= ~ATA_DFLAG_PIO; | |
484 | } else { | |
616ece2e | 485 | ata_dev_printk(dev, KERN_INFO, "configured for PIO\n"); |
669a5db4 JG |
486 | dev->xfer_mode = XFER_PIO_0; |
487 | dev->xfer_shift = ATA_SHIFT_PIO; | |
488 | dev->flags |= ATA_DFLAG_PIO; | |
489 | } | |
490 | } | |
491 | } | |
b229a7b0 | 492 | return 0; |
669a5db4 JG |
493 | } |
494 | ||
495 | /** | |
496 | * it821x_dev_config - Called each device identify | |
669a5db4 JG |
497 | * @adev: Device that has just been identified |
498 | * | |
499 | * Perform the initial setup needed for each device that is chip | |
500 | * special. In our case we need to lock the sector count to avoid | |
501 | * blowing the brains out of the firmware with large LBA48 requests | |
502 | * | |
503 | * FIXME: When FUA appears we need to block FUA too. And SMART and | |
504 | * basically we need to filter commands for this chip. | |
505 | */ | |
85cd7251 | 506 | |
cd0d3bbc | 507 | static void it821x_dev_config(struct ata_device *adev) |
669a5db4 | 508 | { |
8bfa79fc | 509 | unsigned char model_num[ATA_ID_PROD_LEN + 1]; |
669a5db4 | 510 | |
8bfa79fc | 511 | ata_id_c_string(adev->id, model_num, ATA_ID_PROD, sizeof(model_num)); |
669a5db4 JG |
512 | |
513 | if (adev->max_sectors > 255) | |
514 | adev->max_sectors = 255; | |
85cd7251 | 515 | |
669a5db4 JG |
516 | if (strstr(model_num, "Integrated Technology Express")) { |
517 | /* RAID mode */ | |
518 | printk(KERN_INFO "IT821x %sRAID%d volume", | |
519 | adev->id[147]?"Bootable ":"", | |
520 | adev->id[129]); | |
521 | if (adev->id[129] != 1) | |
522 | printk("(%dK stripe)", adev->id[146]); | |
523 | printk(".\n"); | |
524 | } | |
525 | } | |
526 | ||
527 | ||
528 | /** | |
529 | * it821x_check_atapi_dma - ATAPI DMA handler | |
530 | * @qc: Command we are about to issue | |
531 | * | |
532 | * Decide if this ATAPI command can be issued by DMA on this | |
533 | * controller. Return 0 if it can be. | |
534 | */ | |
85cd7251 | 535 | |
669a5db4 JG |
536 | static int it821x_check_atapi_dma(struct ata_queued_cmd *qc) |
537 | { | |
538 | struct ata_port *ap = qc->ap; | |
539 | struct it821x_dev *itdev = ap->private_data; | |
85cd7251 | 540 | |
669a5db4 JG |
541 | /* No ATAPI DMA in smart mode */ |
542 | if (itdev->smart) | |
543 | return -EOPNOTSUPP; | |
544 | /* No ATAPI DMA on rev 10 */ | |
545 | if (itdev->timing10) | |
546 | return -EOPNOTSUPP; | |
547 | /* Cool */ | |
548 | return 0; | |
549 | } | |
85cd7251 | 550 | |
669a5db4 JG |
551 | |
552 | /** | |
553 | * it821x_port_start - port setup | |
554 | * @ap: ATA port being set up | |
555 | * | |
556 | * The it821x needs to maintain private data structures and also to | |
557 | * use the standard PCI interface which lacks support for this | |
85cd7251 | 558 | * functionality. We instead set up the private data on the port |
669a5db4 JG |
559 | * start hook, and tear it down on port stop |
560 | */ | |
85cd7251 | 561 | |
669a5db4 JG |
562 | static int it821x_port_start(struct ata_port *ap) |
563 | { | |
564 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); | |
565 | struct it821x_dev *itdev; | |
566 | u8 conf; | |
567 | ||
568 | int ret = ata_port_start(ap); | |
569 | if (ret < 0) | |
570 | return ret; | |
85cd7251 | 571 | |
24dc5f33 TH |
572 | itdev = devm_kzalloc(&pdev->dev, sizeof(struct it821x_dev), GFP_KERNEL); |
573 | if (itdev == NULL) | |
669a5db4 | 574 | return -ENOMEM; |
24dc5f33 | 575 | ap->private_data = itdev; |
669a5db4 JG |
576 | |
577 | pci_read_config_byte(pdev, 0x50, &conf); | |
578 | ||
579 | if (conf & 1) { | |
580 | itdev->smart = 1; | |
581 | /* Long I/O's although allowed in LBA48 space cause the | |
582 | onboard firmware to enter the twighlight zone */ | |
583 | /* No ATAPI DMA in this mode either */ | |
584 | } | |
585 | /* Pull the current clocks from 0x50 */ | |
586 | if (conf & (1 << (1 + ap->port_no))) | |
587 | itdev->clock_mode = ATA_50; | |
588 | else | |
589 | itdev->clock_mode = ATA_66; | |
590 | ||
591 | itdev->want[0][1] = ATA_ANY; | |
592 | itdev->want[1][1] = ATA_ANY; | |
593 | itdev->last_device = -1; | |
594 | ||
595 | pci_read_config_byte(pdev, PCI_REVISION_ID, &conf); | |
596 | if (conf == 0x10) { | |
597 | itdev->timing10 = 1; | |
598 | /* Need to disable ATAPI DMA for this case */ | |
599 | if (!itdev->smart) | |
600 | printk(KERN_WARNING DRV_NAME": Revision 0x10, workarounds activated.\n"); | |
601 | } | |
602 | ||
603 | return 0; | |
604 | } | |
605 | ||
669a5db4 JG |
606 | static struct scsi_host_template it821x_sht = { |
607 | .module = THIS_MODULE, | |
608 | .name = DRV_NAME, | |
609 | .ioctl = ata_scsi_ioctl, | |
610 | .queuecommand = ata_scsi_queuecmd, | |
611 | .can_queue = ATA_DEF_QUEUE, | |
612 | .this_id = ATA_SHT_THIS_ID, | |
613 | .sg_tablesize = LIBATA_MAX_PRD, | |
669a5db4 JG |
614 | .cmd_per_lun = ATA_SHT_CMD_PER_LUN, |
615 | .emulated = ATA_SHT_EMULATED, | |
616 | .use_clustering = ATA_SHT_USE_CLUSTERING, | |
617 | .proc_name = DRV_NAME, | |
618 | .dma_boundary = ATA_DMA_BOUNDARY, | |
619 | .slave_configure = ata_scsi_slave_config, | |
afdfe899 | 620 | .slave_destroy = ata_scsi_slave_destroy, |
669a5db4 JG |
621 | .bios_param = ata_std_bios_param, |
622 | }; | |
623 | ||
624 | static struct ata_port_operations it821x_smart_port_ops = { | |
625 | .set_mode = it821x_smart_set_mode, | |
626 | .port_disable = ata_port_disable, | |
627 | .tf_load = ata_tf_load, | |
628 | .tf_read = ata_tf_read, | |
629 | .mode_filter = ata_pci_default_filter, | |
85cd7251 | 630 | |
669a5db4 JG |
631 | .check_status = ata_check_status, |
632 | .check_atapi_dma= it821x_check_atapi_dma, | |
633 | .exec_command = ata_exec_command, | |
634 | .dev_select = ata_std_dev_select, | |
635 | .dev_config = it821x_dev_config, | |
636 | ||
637 | .freeze = ata_bmdma_freeze, | |
638 | .thaw = ata_bmdma_thaw, | |
a0fcdc02 | 639 | .error_handler = ata_bmdma_error_handler, |
669a5db4 | 640 | .post_internal_cmd = ata_bmdma_post_internal_cmd, |
a0fcdc02 | 641 | .cable_detect = ata_cable_unknown, |
669a5db4 JG |
642 | |
643 | .bmdma_setup = ata_bmdma_setup, | |
644 | .bmdma_start = ata_bmdma_start, | |
645 | .bmdma_stop = ata_bmdma_stop, | |
646 | .bmdma_status = ata_bmdma_status, | |
647 | ||
648 | .qc_prep = ata_qc_prep, | |
649 | .qc_issue = it821x_smart_qc_issue_prot, | |
bda30288 | 650 | |
0d5ff566 | 651 | .data_xfer = ata_data_xfer, |
669a5db4 JG |
652 | |
653 | .irq_handler = ata_interrupt, | |
654 | .irq_clear = ata_bmdma_irq_clear, | |
246ce3b6 AI |
655 | .irq_on = ata_irq_on, |
656 | .irq_ack = ata_irq_ack, | |
669a5db4 JG |
657 | |
658 | .port_start = it821x_port_start, | |
85cd7251 | 659 | }; |
669a5db4 JG |
660 | |
661 | static struct ata_port_operations it821x_passthru_port_ops = { | |
662 | .port_disable = ata_port_disable, | |
663 | .set_piomode = it821x_passthru_set_piomode, | |
664 | .set_dmamode = it821x_passthru_set_dmamode, | |
665 | .mode_filter = ata_pci_default_filter, | |
85cd7251 | 666 | |
669a5db4 JG |
667 | .tf_load = ata_tf_load, |
668 | .tf_read = ata_tf_read, | |
669 | .check_status = ata_check_status, | |
670 | .exec_command = ata_exec_command, | |
671 | .check_atapi_dma= it821x_check_atapi_dma, | |
672 | .dev_select = it821x_passthru_dev_select, | |
673 | ||
674 | .freeze = ata_bmdma_freeze, | |
675 | .thaw = ata_bmdma_thaw, | |
a0fcdc02 | 676 | .error_handler = ata_bmdma_error_handler, |
669a5db4 | 677 | .post_internal_cmd = ata_bmdma_post_internal_cmd, |
a0fcdc02 | 678 | .cable_detect = ata_cable_unknown, |
669a5db4 JG |
679 | |
680 | .bmdma_setup = ata_bmdma_setup, | |
681 | .bmdma_start = it821x_passthru_bmdma_start, | |
682 | .bmdma_stop = it821x_passthru_bmdma_stop, | |
683 | .bmdma_status = ata_bmdma_status, | |
684 | ||
685 | .qc_prep = ata_qc_prep, | |
686 | .qc_issue = it821x_passthru_qc_issue_prot, | |
bda30288 | 687 | |
0d5ff566 | 688 | .data_xfer = ata_data_xfer, |
669a5db4 JG |
689 | |
690 | .irq_clear = ata_bmdma_irq_clear, | |
691 | .irq_handler = ata_interrupt, | |
246ce3b6 AI |
692 | .irq_on = ata_irq_on, |
693 | .irq_ack = ata_irq_ack, | |
669a5db4 JG |
694 | |
695 | .port_start = it821x_port_start, | |
85cd7251 | 696 | }; |
669a5db4 JG |
697 | |
698 | static void __devinit it821x_disable_raid(struct pci_dev *pdev) | |
699 | { | |
700 | /* Reset local CPU, and set BIOS not ready */ | |
701 | pci_write_config_byte(pdev, 0x5E, 0x01); | |
702 | ||
703 | /* Set to bypass mode, and reset PCI bus */ | |
704 | pci_write_config_byte(pdev, 0x50, 0x00); | |
705 | pci_write_config_word(pdev, PCI_COMMAND, | |
706 | PCI_COMMAND_PARITY | PCI_COMMAND_IO | | |
707 | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); | |
708 | pci_write_config_word(pdev, 0x40, 0xA0F3); | |
709 | ||
710 | pci_write_config_dword(pdev,0x4C, 0x02040204); | |
711 | pci_write_config_byte(pdev, 0x42, 0x36); | |
712 | pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0x20); | |
713 | } | |
714 | ||
85cd7251 | 715 | |
669a5db4 JG |
716 | static int it821x_init_one(struct pci_dev *pdev, const struct pci_device_id *id) |
717 | { | |
718 | u8 conf; | |
85cd7251 | 719 | |
1626aeb8 | 720 | static const struct ata_port_info info_smart = { |
669a5db4 JG |
721 | .sht = &it821x_sht, |
722 | .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST, | |
723 | .pio_mask = 0x1f, | |
724 | .mwdma_mask = 0x07, | |
725 | .port_ops = &it821x_smart_port_ops | |
726 | }; | |
1626aeb8 | 727 | static const struct ata_port_info info_passthru = { |
669a5db4 JG |
728 | .sht = &it821x_sht, |
729 | .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST, | |
730 | .pio_mask = 0x1f, | |
731 | .mwdma_mask = 0x07, | |
732 | .udma_mask = 0x7f, | |
733 | .port_ops = &it821x_passthru_port_ops | |
734 | }; | |
85cd7251 | 735 | |
1626aeb8 | 736 | const struct ata_port_info *ppi[] = { NULL, NULL }; |
669a5db4 JG |
737 | static char *mode[2] = { "pass through", "smart" }; |
738 | ||
739 | /* Force the card into bypass mode if so requested */ | |
740 | if (it8212_noraid) { | |
741 | printk(KERN_INFO DRV_NAME ": forcing bypass mode.\n"); | |
742 | it821x_disable_raid(pdev); | |
743 | } | |
744 | pci_read_config_byte(pdev, 0x50, &conf); | |
745 | conf &= 1; | |
85cd7251 | 746 | |
669a5db4 JG |
747 | printk(KERN_INFO DRV_NAME ": controller in %s mode.\n", mode[conf]); |
748 | if (conf == 0) | |
1626aeb8 | 749 | ppi[0] = &info_passthru; |
669a5db4 | 750 | else |
1626aeb8 | 751 | ppi[0] = &info_smart; |
85cd7251 | 752 | |
1626aeb8 | 753 | return ata_pci_init_one(pdev, ppi); |
669a5db4 JG |
754 | } |
755 | ||
438ac6d5 | 756 | #ifdef CONFIG_PM |
f535d53f A |
757 | static int it821x_reinit_one(struct pci_dev *pdev) |
758 | { | |
759 | /* Resume - turn raid back off if need be */ | |
760 | if (it8212_noraid) | |
761 | it821x_disable_raid(pdev); | |
762 | return ata_pci_device_resume(pdev); | |
763 | } | |
438ac6d5 | 764 | #endif |
f535d53f | 765 | |
2d2744fc JG |
766 | static const struct pci_device_id it821x[] = { |
767 | { PCI_VDEVICE(ITE, PCI_DEVICE_ID_ITE_8211), }, | |
768 | { PCI_VDEVICE(ITE, PCI_DEVICE_ID_ITE_8212), }, | |
769 | ||
770 | { }, | |
669a5db4 JG |
771 | }; |
772 | ||
773 | static struct pci_driver it821x_pci_driver = { | |
2d2744fc | 774 | .name = DRV_NAME, |
669a5db4 JG |
775 | .id_table = it821x, |
776 | .probe = it821x_init_one, | |
f535d53f | 777 | .remove = ata_pci_remove_one, |
438ac6d5 | 778 | #ifdef CONFIG_PM |
f535d53f A |
779 | .suspend = ata_pci_device_suspend, |
780 | .resume = it821x_reinit_one, | |
438ac6d5 | 781 | #endif |
669a5db4 JG |
782 | }; |
783 | ||
784 | static int __init it821x_init(void) | |
785 | { | |
786 | return pci_register_driver(&it821x_pci_driver); | |
787 | } | |
788 | ||
669a5db4 JG |
789 | static void __exit it821x_exit(void) |
790 | { | |
791 | pci_unregister_driver(&it821x_pci_driver); | |
792 | } | |
793 | ||
669a5db4 JG |
794 | MODULE_AUTHOR("Alan Cox"); |
795 | MODULE_DESCRIPTION("low-level driver for the IT8211/IT8212 IDE RAID controller"); | |
796 | MODULE_LICENSE("GPL"); | |
797 | MODULE_DEVICE_TABLE(pci, it821x); | |
798 | MODULE_VERSION(DRV_VERSION); | |
799 | ||
800 | ||
801 | module_param_named(noraid, it8212_noraid, int, S_IRUGO); | |
802 | MODULE_PARM_DESC(it8212_noraid, "Force card into bypass mode"); | |
803 | ||
804 | module_init(it821x_init); | |
805 | module_exit(it821x_exit); |