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669a5db4 JG |
1 | /* |
2 | * pata-legacy.c - Legacy port PATA/SATA controller driver. | |
ab771630 | 3 | * Copyright 2005/2006 Red Hat, all rights reserved. |
669a5db4 JG |
4 | * |
5 | * This program is free software; you can redistribute it and/or modify | |
6 | * it under the terms of the GNU General Public License as published by | |
7 | * the Free Software Foundation; either version 2, or (at your option) | |
8 | * any later version. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
14 | * | |
15 | * You should have received a copy of the GNU General Public License | |
16 | * along with this program; see the file COPYING. If not, write to | |
17 | * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. | |
18 | * | |
19 | * An ATA driver for the legacy ATA ports. | |
20 | * | |
21 | * Data Sources: | |
22 | * Opti 82C465/82C611 support: Data sheets at opti-inc.com | |
23 | * HT6560 series: | |
24 | * Promise 20230/20620: | |
25 | * http://www.ryston.cz/petr/vlb/pdc20230b.html | |
26 | * http://www.ryston.cz/petr/vlb/pdc20230c.html | |
27 | * http://www.ryston.cz/petr/vlb/pdc20630.html | |
9c7e0d22 BZ |
28 | * QDI65x0: |
29 | * http://www.ryston.cz/petr/vlb/qd6500.html | |
30 | * http://www.ryston.cz/petr/vlb/qd6580.html | |
31 | * | |
32 | * QDI65x0 probe code based on drivers/ide/legacy/qd65xx.c | |
33 | * Rewritten from the work of Colten Edwards <pje120@cs.usask.ca> by | |
34 | * Samuel Thibault <samuel.thibault@ens-lyon.org> | |
669a5db4 JG |
35 | * |
36 | * Unsupported but docs exist: | |
37 | * Appian/Adaptec AIC25VL01/Cirrus Logic PD7220 | |
669a5db4 JG |
38 | * |
39 | * This driver handles legacy (that is "ISA/VLB side") IDE ports found | |
40 | * on PC class systems. There are three hybrid devices that are exceptions | |
41 | * The Cyrix 5510/5520 where a pre SFF ATA device is on the bridge and | |
42 | * the MPIIX where the tuning is PCI side but the IDE is "ISA side". | |
43 | * | |
44 | * Specific support is included for the ht6560a/ht6560b/opti82c611a/ | |
9c7e0d22 | 45 | * opti82c465mv/promise 20230c/20630/qdi65x0/winbond83759A |
669a5db4 JG |
46 | * |
47 | * Use the autospeed and pio_mask options with: | |
48 | * Appian ADI/2 aka CLPD7220 or AIC25VL01. | |
49 | * Use the jumpers, autospeed and set pio_mask to the mode on the jumpers with | |
50 | * Goldstar GM82C711, PIC-1288A-125, UMC 82C871F, Winbond W83759, | |
51 | * Winbond W83759A, Promise PDC20230-B | |
52 | * | |
53 | * For now use autospeed and pio_mask as above with the W83759A. This may | |
54 | * change. | |
55 | * | |
669a5db4 JG |
56 | */ |
57 | ||
45bc955b | 58 | #include <linux/async.h> |
669a5db4 JG |
59 | #include <linux/kernel.h> |
60 | #include <linux/module.h> | |
61 | #include <linux/pci.h> | |
62 | #include <linux/init.h> | |
63 | #include <linux/blkdev.h> | |
64 | #include <linux/delay.h> | |
65 | #include <scsi/scsi_host.h> | |
66 | #include <linux/ata.h> | |
67 | #include <linux/libata.h> | |
68 | #include <linux/platform_device.h> | |
69 | ||
70 | #define DRV_NAME "pata_legacy" | |
b8325487 | 71 | #define DRV_VERSION "0.6.5" |
669a5db4 JG |
72 | |
73 | #define NR_HOST 6 | |
74 | ||
defc9cd8 AC |
75 | static int all; |
76 | module_param(all, int, 0444); | |
77 | MODULE_PARM_DESC(all, "Grab all legacy port devices, even if PCI(0=off, 1=on)"); | |
669a5db4 JG |
78 | |
79 | struct legacy_data { | |
80 | unsigned long timing; | |
81 | u8 clock[2]; | |
82 | u8 last; | |
83 | int fast; | |
84 | struct platform_device *platform_dev; | |
85 | ||
86 | }; | |
87 | ||
defc9cd8 AC |
88 | enum controller { |
89 | BIOS = 0, | |
90 | SNOOP = 1, | |
91 | PDC20230 = 2, | |
92 | HT6560A = 3, | |
93 | HT6560B = 4, | |
94 | OPTI611A = 5, | |
95 | OPTI46X = 6, | |
96 | QDI6500 = 7, | |
97 | QDI6580 = 8, | |
98 | QDI6580DP = 9, /* Dual channel mode is different */ | |
b8325487 | 99 | W83759A = 10, |
defc9cd8 AC |
100 | |
101 | UNKNOWN = -1 | |
102 | }; | |
103 | ||
104 | ||
105 | struct legacy_probe { | |
106 | unsigned char *name; | |
107 | unsigned long port; | |
108 | unsigned int irq; | |
109 | unsigned int slot; | |
110 | enum controller type; | |
111 | unsigned long private; | |
112 | }; | |
113 | ||
114 | struct legacy_controller { | |
115 | const char *name; | |
116 | struct ata_port_operations *ops; | |
117 | unsigned int pio_mask; | |
118 | unsigned int flags; | |
e3cf95dd | 119 | unsigned int pflags; |
b8325487 AC |
120 | int (*setup)(struct platform_device *, struct legacy_probe *probe, |
121 | struct legacy_data *data); | |
defc9cd8 AC |
122 | }; |
123 | ||
124 | static int legacy_port[NR_HOST] = { 0x1f0, 0x170, 0x1e8, 0x168, 0x1e0, 0x160 }; | |
125 | ||
126 | static struct legacy_probe probe_list[NR_HOST]; | |
669a5db4 JG |
127 | static struct legacy_data legacy_data[NR_HOST]; |
128 | static struct ata_host *legacy_host[NR_HOST]; | |
129 | static int nr_legacy_host; | |
130 | ||
131 | ||
defc9cd8 AC |
132 | static int probe_all; /* Set to check all ISA port ranges */ |
133 | static int ht6560a; /* HT 6560A on primary 1, second 2, both 3 */ | |
134 | static int ht6560b; /* HT 6560A on primary 1, second 2, both 3 */ | |
135 | static int opti82c611a; /* Opti82c611A on primary 1, sec 2, both 3 */ | |
136 | static int opti82c46x; /* Opti 82c465MV present(pri/sec autodetect) */ | |
137 | static int qdi; /* Set to probe QDI controllers */ | |
b8325487 | 138 | static int winbond; /* Set to probe Winbond controllers, |
8397248d | 139 | give I/O port if non standard */ |
defc9cd8 | 140 | static int autospeed; /* Chip present which snoops speed changes */ |
14bdef98 | 141 | static int pio_mask = ATA_PIO4; /* PIO range for autospeed devices */ |
f834e49f | 142 | static int iordy_mask = 0xFFFFFFFF; /* Use iordy if available */ |
669a5db4 | 143 | |
defc9cd8 AC |
144 | /** |
145 | * legacy_probe_add - Add interface to probe list | |
146 | * @port: Controller port | |
147 | * @irq: IRQ number | |
148 | * @type: Controller type | |
149 | * @private: Controller specific info | |
150 | * | |
151 | * Add an entry into the probe list for ATA controllers. This is used | |
152 | * to add the default ISA slots and then to build up the table | |
153 | * further according to other ISA/VLB/Weird device scans | |
154 | * | |
155 | * An I/O port list is used to keep ordering stable and sane, as we | |
156 | * don't have any good way to talk about ordering otherwise | |
157 | */ | |
158 | ||
159 | static int legacy_probe_add(unsigned long port, unsigned int irq, | |
160 | enum controller type, unsigned long private) | |
161 | { | |
162 | struct legacy_probe *lp = &probe_list[0]; | |
163 | int i; | |
164 | struct legacy_probe *free = NULL; | |
165 | ||
166 | for (i = 0; i < NR_HOST; i++) { | |
167 | if (lp->port == 0 && free == NULL) | |
168 | free = lp; | |
169 | /* Matching port, or the correct slot for ordering */ | |
170 | if (lp->port == port || legacy_port[i] == port) { | |
171 | free = lp; | |
172 | break; | |
173 | } | |
174 | lp++; | |
175 | } | |
176 | if (free == NULL) { | |
177 | printk(KERN_ERR "pata_legacy: Too many interfaces.\n"); | |
178 | return -1; | |
179 | } | |
180 | /* Fill in the entry for later probing */ | |
181 | free->port = port; | |
182 | free->irq = irq; | |
183 | free->type = type; | |
184 | free->private = private; | |
185 | return 0; | |
186 | } | |
187 | ||
188 | ||
669a5db4 JG |
189 | /** |
190 | * legacy_set_mode - mode setting | |
0260731f | 191 | * @link: IDE link |
b229a7b0 | 192 | * @unused: Device that failed when error is returned |
669a5db4 JG |
193 | * |
194 | * Use a non standard set_mode function. We don't want to be tuned. | |
195 | * | |
196 | * The BIOS configured everything. Our job is not to fiddle. Just use | |
197 | * whatever PIO the hardware is using and leave it at that. When we | |
198 | * get some kind of nice user driven API for control then we can | |
199 | * expand on this as per hdparm in the base kernel. | |
200 | */ | |
201 | ||
0260731f | 202 | static int legacy_set_mode(struct ata_link *link, struct ata_device **unused) |
669a5db4 | 203 | { |
f58229f8 | 204 | struct ata_device *dev; |
669a5db4 | 205 | |
1eca4365 TH |
206 | ata_for_each_dev(dev, link, ENABLED) { |
207 | ata_dev_printk(dev, KERN_INFO, "configured for PIO\n"); | |
208 | dev->pio_mode = XFER_PIO_0; | |
209 | dev->xfer_mode = XFER_PIO_0; | |
210 | dev->xfer_shift = ATA_SHIFT_PIO; | |
211 | dev->flags |= ATA_DFLAG_PIO; | |
669a5db4 | 212 | } |
b229a7b0 | 213 | return 0; |
669a5db4 JG |
214 | } |
215 | ||
216 | static struct scsi_host_template legacy_sht = { | |
68d1d07b | 217 | ATA_PIO_SHT(DRV_NAME), |
669a5db4 JG |
218 | }; |
219 | ||
029cfd6b TH |
220 | static const struct ata_port_operations legacy_base_port_ops = { |
221 | .inherits = &ata_sff_port_ops, | |
222 | .cable_detect = ata_cable_40wire, | |
223 | }; | |
224 | ||
669a5db4 JG |
225 | /* |
226 | * These ops are used if the user indicates the hardware | |
227 | * snoops the commands to decide on the mode and handles the | |
228 | * mode selection "magically" itself. Several legacy controllers | |
229 | * do this. The mode range can be set if it is not 0x1F by setting | |
230 | * pio_mask as well. | |
231 | */ | |
232 | ||
233 | static struct ata_port_operations simple_port_ops = { | |
029cfd6b | 234 | .inherits = &legacy_base_port_ops, |
5682ed33 | 235 | .sff_data_xfer = ata_sff_data_xfer_noirq, |
669a5db4 JG |
236 | }; |
237 | ||
238 | static struct ata_port_operations legacy_port_ops = { | |
029cfd6b | 239 | .inherits = &legacy_base_port_ops, |
5682ed33 | 240 | .sff_data_xfer = ata_sff_data_xfer_noirq, |
029cfd6b | 241 | .set_mode = legacy_set_mode, |
669a5db4 JG |
242 | }; |
243 | ||
244 | /* | |
245 | * Promise 20230C and 20620 support | |
246 | * | |
defc9cd8 AC |
247 | * This controller supports PIO0 to PIO2. We set PIO timings |
248 | * conservatively to allow for 50MHz Vesa Local Bus. The 20620 DMA | |
249 | * support is weird being DMA to controller and PIO'd to the host | |
250 | * and not supported. | |
669a5db4 JG |
251 | */ |
252 | ||
253 | static void pdc20230_set_piomode(struct ata_port *ap, struct ata_device *adev) | |
254 | { | |
255 | int tries = 5; | |
256 | int pio = adev->pio_mode - XFER_PIO_0; | |
257 | u8 rt; | |
258 | unsigned long flags; | |
85cd7251 | 259 | |
669a5db4 | 260 | /* Safe as UP only. Force I/Os to occur together */ |
85cd7251 | 261 | |
669a5db4 | 262 | local_irq_save(flags); |
85cd7251 | 263 | |
669a5db4 | 264 | /* Unlock the control interface */ |
defc9cd8 | 265 | do { |
669a5db4 JG |
266 | inb(0x1F5); |
267 | outb(inb(0x1F2) | 0x80, 0x1F2); | |
268 | inb(0x1F2); | |
269 | inb(0x3F6); | |
270 | inb(0x3F6); | |
271 | inb(0x1F2); | |
272 | inb(0x1F2); | |
273 | } | |
defc9cd8 | 274 | while ((inb(0x1F2) & 0x80) && --tries); |
669a5db4 JG |
275 | |
276 | local_irq_restore(flags); | |
85cd7251 | 277 | |
669a5db4 JG |
278 | outb(inb(0x1F4) & 0x07, 0x1F4); |
279 | ||
280 | rt = inb(0x1F3); | |
281 | rt &= 0x07 << (3 * adev->devno); | |
282 | if (pio) | |
283 | rt |= (1 + 3 * pio) << (3 * adev->devno); | |
284 | ||
285 | udelay(100); | |
286 | outb(inb(0x1F2) | 0x01, 0x1F2); | |
287 | udelay(100); | |
288 | inb(0x1F5); | |
289 | ||
290 | } | |
291 | ||
55dba312 | 292 | static unsigned int pdc_data_xfer_vlb(struct ata_device *dev, |
defc9cd8 | 293 | unsigned char *buf, unsigned int buflen, int rw) |
669a5db4 | 294 | { |
c55af1f5 | 295 | int slop = buflen & 3; |
16e6aeca ZX |
296 | struct ata_port *ap = dev->link->ap; |
297 | ||
c55af1f5 | 298 | /* 32bit I/O capable *and* we need to write a whole number of dwords */ |
e3cf95dd AC |
299 | if (ata_id_has_dword_io(dev->id) && (slop == 0 || slop == 3) |
300 | && (ap->pflags & ATA_PFLAG_PIO32)) { | |
55dba312 TH |
301 | unsigned long flags; |
302 | ||
669a5db4 JG |
303 | local_irq_save(flags); |
304 | ||
305 | /* Perform the 32bit I/O synchronization sequence */ | |
0d5ff566 TH |
306 | ioread8(ap->ioaddr.nsect_addr); |
307 | ioread8(ap->ioaddr.nsect_addr); | |
308 | ioread8(ap->ioaddr.nsect_addr); | |
669a5db4 JG |
309 | |
310 | /* Now the data */ | |
55dba312 | 311 | if (rw == READ) |
0d5ff566 | 312 | ioread32_rep(ap->ioaddr.data_addr, buf, buflen >> 2); |
55dba312 TH |
313 | else |
314 | iowrite32_rep(ap->ioaddr.data_addr, buf, buflen >> 2); | |
669a5db4 JG |
315 | |
316 | if (unlikely(slop)) { | |
6ad67403 | 317 | __le32 pad; |
55dba312 | 318 | if (rw == READ) { |
b50e56d8 | 319 | pad = cpu_to_le32(ioread32(ap->ioaddr.data_addr)); |
669a5db4 | 320 | memcpy(buf + buflen - slop, &pad, slop); |
55dba312 TH |
321 | } else { |
322 | memcpy(&pad, buf + buflen - slop, slop); | |
323 | iowrite32(le32_to_cpu(pad), ap->ioaddr.data_addr); | |
669a5db4 | 324 | } |
55dba312 | 325 | buflen += 4 - slop; |
669a5db4 JG |
326 | } |
327 | local_irq_restore(flags); | |
55dba312 | 328 | } else |
9363c382 | 329 | buflen = ata_sff_data_xfer_noirq(dev, buf, buflen, rw); |
55dba312 TH |
330 | |
331 | return buflen; | |
669a5db4 JG |
332 | } |
333 | ||
334 | static struct ata_port_operations pdc20230_port_ops = { | |
029cfd6b | 335 | .inherits = &legacy_base_port_ops, |
669a5db4 | 336 | .set_piomode = pdc20230_set_piomode, |
5682ed33 | 337 | .sff_data_xfer = pdc_data_xfer_vlb, |
669a5db4 JG |
338 | }; |
339 | ||
340 | /* | |
341 | * Holtek 6560A support | |
342 | * | |
defc9cd8 AC |
343 | * This controller supports PIO0 to PIO2 (no IORDY even though higher |
344 | * timings can be loaded). | |
669a5db4 JG |
345 | */ |
346 | ||
347 | static void ht6560a_set_piomode(struct ata_port *ap, struct ata_device *adev) | |
348 | { | |
349 | u8 active, recover; | |
350 | struct ata_timing t; | |
351 | ||
352 | /* Get the timing data in cycles. For now play safe at 50Mhz */ | |
353 | ata_timing_compute(adev, adev->pio_mode, &t, 20000, 1000); | |
354 | ||
07633b5d HH |
355 | active = clamp_val(t.active, 2, 15); |
356 | recover = clamp_val(t.recover, 4, 15); | |
669a5db4 JG |
357 | |
358 | inb(0x3E6); | |
359 | inb(0x3E6); | |
360 | inb(0x3E6); | |
361 | inb(0x3E6); | |
362 | ||
0d5ff566 TH |
363 | iowrite8(recover << 4 | active, ap->ioaddr.device_addr); |
364 | ioread8(ap->ioaddr.status_addr); | |
669a5db4 JG |
365 | } |
366 | ||
367 | static struct ata_port_operations ht6560a_port_ops = { | |
029cfd6b | 368 | .inherits = &legacy_base_port_ops, |
669a5db4 | 369 | .set_piomode = ht6560a_set_piomode, |
669a5db4 JG |
370 | }; |
371 | ||
372 | /* | |
373 | * Holtek 6560B support | |
374 | * | |
defc9cd8 AC |
375 | * This controller supports PIO0 to PIO4. We honour the BIOS/jumper FIFO |
376 | * setting unless we see an ATAPI device in which case we force it off. | |
669a5db4 JG |
377 | * |
378 | * FIXME: need to implement 2nd channel support. | |
379 | */ | |
380 | ||
381 | static void ht6560b_set_piomode(struct ata_port *ap, struct ata_device *adev) | |
382 | { | |
383 | u8 active, recover; | |
384 | struct ata_timing t; | |
385 | ||
386 | /* Get the timing data in cycles. For now play safe at 50Mhz */ | |
387 | ata_timing_compute(adev, adev->pio_mode, &t, 20000, 1000); | |
388 | ||
07633b5d HH |
389 | active = clamp_val(t.active, 2, 15); |
390 | recover = clamp_val(t.recover, 2, 16); | |
669a5db4 JG |
391 | recover &= 0x15; |
392 | ||
393 | inb(0x3E6); | |
394 | inb(0x3E6); | |
395 | inb(0x3E6); | |
396 | inb(0x3E6); | |
397 | ||
0d5ff566 | 398 | iowrite8(recover << 4 | active, ap->ioaddr.device_addr); |
669a5db4 JG |
399 | |
400 | if (adev->class != ATA_DEV_ATA) { | |
401 | u8 rconf = inb(0x3E6); | |
402 | if (rconf & 0x24) { | |
defc9cd8 | 403 | rconf &= ~0x24; |
669a5db4 JG |
404 | outb(rconf, 0x3E6); |
405 | } | |
406 | } | |
0d5ff566 | 407 | ioread8(ap->ioaddr.status_addr); |
669a5db4 JG |
408 | } |
409 | ||
410 | static struct ata_port_operations ht6560b_port_ops = { | |
029cfd6b | 411 | .inherits = &legacy_base_port_ops, |
669a5db4 | 412 | .set_piomode = ht6560b_set_piomode, |
669a5db4 JG |
413 | }; |
414 | ||
415 | /* | |
416 | * Opti core chipset helpers | |
417 | */ | |
85cd7251 | 418 | |
669a5db4 JG |
419 | /** |
420 | * opti_syscfg - read OPTI chipset configuration | |
421 | * @reg: Configuration register to read | |
422 | * | |
423 | * Returns the value of an OPTI system board configuration register. | |
424 | */ | |
425 | ||
426 | static u8 opti_syscfg(u8 reg) | |
427 | { | |
428 | unsigned long flags; | |
429 | u8 r; | |
85cd7251 | 430 | |
669a5db4 JG |
431 | /* Uniprocessor chipset and must force cycles adjancent */ |
432 | local_irq_save(flags); | |
433 | outb(reg, 0x22); | |
434 | r = inb(0x24); | |
435 | local_irq_restore(flags); | |
436 | return r; | |
437 | } | |
438 | ||
439 | /* | |
440 | * Opti 82C611A | |
441 | * | |
442 | * This controller supports PIO0 to PIO3. | |
443 | */ | |
444 | ||
defc9cd8 AC |
445 | static void opti82c611a_set_piomode(struct ata_port *ap, |
446 | struct ata_device *adev) | |
669a5db4 JG |
447 | { |
448 | u8 active, recover, setup; | |
449 | struct ata_timing t; | |
450 | struct ata_device *pair = ata_dev_pair(adev); | |
451 | int clock; | |
452 | int khz[4] = { 50000, 40000, 33000, 25000 }; | |
453 | u8 rc; | |
454 | ||
455 | /* Enter configuration mode */ | |
0d5ff566 TH |
456 | ioread16(ap->ioaddr.error_addr); |
457 | ioread16(ap->ioaddr.error_addr); | |
458 | iowrite8(3, ap->ioaddr.nsect_addr); | |
669a5db4 JG |
459 | |
460 | /* Read VLB clock strapping */ | |
0d5ff566 | 461 | clock = 1000000000 / khz[ioread8(ap->ioaddr.lbah_addr) & 0x03]; |
669a5db4 JG |
462 | |
463 | /* Get the timing data in cycles */ | |
464 | ata_timing_compute(adev, adev->pio_mode, &t, clock, 1000); | |
465 | ||
466 | /* Setup timing is shared */ | |
467 | if (pair) { | |
468 | struct ata_timing tp; | |
469 | ata_timing_compute(pair, pair->pio_mode, &tp, clock, 1000); | |
470 | ||
471 | ata_timing_merge(&t, &tp, &t, ATA_TIMING_SETUP); | |
472 | } | |
473 | ||
07633b5d HH |
474 | active = clamp_val(t.active, 2, 17) - 2; |
475 | recover = clamp_val(t.recover, 1, 16) - 1; | |
476 | setup = clamp_val(t.setup, 1, 4) - 1; | |
669a5db4 JG |
477 | |
478 | /* Select the right timing bank for write timing */ | |
0d5ff566 | 479 | rc = ioread8(ap->ioaddr.lbal_addr); |
669a5db4 JG |
480 | rc &= 0x7F; |
481 | rc |= (adev->devno << 7); | |
0d5ff566 | 482 | iowrite8(rc, ap->ioaddr.lbal_addr); |
669a5db4 JG |
483 | |
484 | /* Write the timings */ | |
0d5ff566 | 485 | iowrite8(active << 4 | recover, ap->ioaddr.error_addr); |
669a5db4 JG |
486 | |
487 | /* Select the right bank for read timings, also | |
488 | load the shared timings for address */ | |
0d5ff566 | 489 | rc = ioread8(ap->ioaddr.device_addr); |
669a5db4 JG |
490 | rc &= 0xC0; |
491 | rc |= adev->devno; /* Index select */ | |
492 | rc |= (setup << 4) | 0x04; | |
0d5ff566 | 493 | iowrite8(rc, ap->ioaddr.device_addr); |
669a5db4 JG |
494 | |
495 | /* Load the read timings */ | |
0d5ff566 | 496 | iowrite8(active << 4 | recover, ap->ioaddr.data_addr); |
669a5db4 JG |
497 | |
498 | /* Ensure the timing register mode is right */ | |
0d5ff566 | 499 | rc = ioread8(ap->ioaddr.lbal_addr); |
669a5db4 JG |
500 | rc &= 0x73; |
501 | rc |= 0x84; | |
0d5ff566 | 502 | iowrite8(rc, ap->ioaddr.lbal_addr); |
669a5db4 JG |
503 | |
504 | /* Exit command mode */ | |
0d5ff566 | 505 | iowrite8(0x83, ap->ioaddr.nsect_addr); |
669a5db4 JG |
506 | } |
507 | ||
508 | ||
509 | static struct ata_port_operations opti82c611a_port_ops = { | |
029cfd6b | 510 | .inherits = &legacy_base_port_ops, |
669a5db4 | 511 | .set_piomode = opti82c611a_set_piomode, |
669a5db4 JG |
512 | }; |
513 | ||
514 | /* | |
515 | * Opti 82C465MV | |
516 | * | |
517 | * This controller supports PIO0 to PIO3. Unlike the 611A the MVB | |
518 | * version is dual channel but doesn't have a lot of unique registers. | |
519 | */ | |
520 | ||
521 | static void opti82c46x_set_piomode(struct ata_port *ap, struct ata_device *adev) | |
522 | { | |
523 | u8 active, recover, setup; | |
524 | struct ata_timing t; | |
525 | struct ata_device *pair = ata_dev_pair(adev); | |
526 | int clock; | |
527 | int khz[4] = { 50000, 40000, 33000, 25000 }; | |
528 | u8 rc; | |
529 | u8 sysclk; | |
530 | ||
531 | /* Get the clock */ | |
532 | sysclk = opti_syscfg(0xAC) & 0xC0; /* BIOS set */ | |
533 | ||
534 | /* Enter configuration mode */ | |
0d5ff566 TH |
535 | ioread16(ap->ioaddr.error_addr); |
536 | ioread16(ap->ioaddr.error_addr); | |
537 | iowrite8(3, ap->ioaddr.nsect_addr); | |
669a5db4 JG |
538 | |
539 | /* Read VLB clock strapping */ | |
540 | clock = 1000000000 / khz[sysclk]; | |
541 | ||
542 | /* Get the timing data in cycles */ | |
543 | ata_timing_compute(adev, adev->pio_mode, &t, clock, 1000); | |
544 | ||
545 | /* Setup timing is shared */ | |
546 | if (pair) { | |
547 | struct ata_timing tp; | |
548 | ata_timing_compute(pair, pair->pio_mode, &tp, clock, 1000); | |
549 | ||
550 | ata_timing_merge(&t, &tp, &t, ATA_TIMING_SETUP); | |
551 | } | |
552 | ||
07633b5d HH |
553 | active = clamp_val(t.active, 2, 17) - 2; |
554 | recover = clamp_val(t.recover, 1, 16) - 1; | |
555 | setup = clamp_val(t.setup, 1, 4) - 1; | |
669a5db4 JG |
556 | |
557 | /* Select the right timing bank for write timing */ | |
0d5ff566 | 558 | rc = ioread8(ap->ioaddr.lbal_addr); |
669a5db4 JG |
559 | rc &= 0x7F; |
560 | rc |= (adev->devno << 7); | |
0d5ff566 | 561 | iowrite8(rc, ap->ioaddr.lbal_addr); |
669a5db4 JG |
562 | |
563 | /* Write the timings */ | |
0d5ff566 | 564 | iowrite8(active << 4 | recover, ap->ioaddr.error_addr); |
669a5db4 JG |
565 | |
566 | /* Select the right bank for read timings, also | |
567 | load the shared timings for address */ | |
0d5ff566 | 568 | rc = ioread8(ap->ioaddr.device_addr); |
669a5db4 JG |
569 | rc &= 0xC0; |
570 | rc |= adev->devno; /* Index select */ | |
571 | rc |= (setup << 4) | 0x04; | |
0d5ff566 | 572 | iowrite8(rc, ap->ioaddr.device_addr); |
669a5db4 JG |
573 | |
574 | /* Load the read timings */ | |
0d5ff566 | 575 | iowrite8(active << 4 | recover, ap->ioaddr.data_addr); |
669a5db4 JG |
576 | |
577 | /* Ensure the timing register mode is right */ | |
0d5ff566 | 578 | rc = ioread8(ap->ioaddr.lbal_addr); |
669a5db4 JG |
579 | rc &= 0x73; |
580 | rc |= 0x84; | |
0d5ff566 | 581 | iowrite8(rc, ap->ioaddr.lbal_addr); |
669a5db4 JG |
582 | |
583 | /* Exit command mode */ | |
0d5ff566 | 584 | iowrite8(0x83, ap->ioaddr.nsect_addr); |
669a5db4 JG |
585 | |
586 | /* We need to know this for quad device on the MVB */ | |
587 | ap->host->private_data = ap; | |
588 | } | |
589 | ||
590 | /** | |
9363c382 | 591 | * opt82c465mv_qc_issue - command issue |
669a5db4 JG |
592 | * @qc: command pending |
593 | * | |
594 | * Called when the libata layer is about to issue a command. We wrap | |
595 | * this interface so that we can load the correct ATA timings. The | |
596 | * MVB has a single set of timing registers and these are shared | |
597 | * across channels. As there are two registers we really ought to | |
598 | * track the last two used values as a sort of register window. For | |
599 | * now we just reload on a channel switch. On the single channel | |
600 | * setup this condition never fires so we do nothing extra. | |
601 | * | |
602 | * FIXME: dual channel needs ->serialize support | |
603 | */ | |
604 | ||
9363c382 | 605 | static unsigned int opti82c46x_qc_issue(struct ata_queued_cmd *qc) |
669a5db4 JG |
606 | { |
607 | struct ata_port *ap = qc->ap; | |
608 | struct ata_device *adev = qc->dev; | |
609 | ||
610 | /* If timings are set and for the wrong channel (2nd test is | |
611 | due to a libata shortcoming and will eventually go I hope) */ | |
612 | if (ap->host->private_data != ap->host | |
613 | && ap->host->private_data != NULL) | |
614 | opti82c46x_set_piomode(ap, adev); | |
615 | ||
9363c382 | 616 | return ata_sff_qc_issue(qc); |
669a5db4 JG |
617 | } |
618 | ||
619 | static struct ata_port_operations opti82c46x_port_ops = { | |
029cfd6b | 620 | .inherits = &legacy_base_port_ops, |
669a5db4 | 621 | .set_piomode = opti82c46x_set_piomode, |
9363c382 | 622 | .qc_issue = opti82c46x_qc_issue, |
669a5db4 JG |
623 | }; |
624 | ||
defc9cd8 AC |
625 | static void qdi6500_set_piomode(struct ata_port *ap, struct ata_device *adev) |
626 | { | |
627 | struct ata_timing t; | |
cb616dd5 | 628 | struct legacy_data *ld_qdi = ap->host->private_data; |
defc9cd8 AC |
629 | int active, recovery; |
630 | u8 timing; | |
631 | ||
632 | /* Get the timing data in cycles */ | |
633 | ata_timing_compute(adev, adev->pio_mode, &t, 30303, 1000); | |
634 | ||
cb616dd5 | 635 | if (ld_qdi->fast) { |
07633b5d HH |
636 | active = 8 - clamp_val(t.active, 1, 8); |
637 | recovery = 18 - clamp_val(t.recover, 3, 18); | |
defc9cd8 | 638 | } else { |
07633b5d HH |
639 | active = 9 - clamp_val(t.active, 2, 9); |
640 | recovery = 15 - clamp_val(t.recover, 0, 15); | |
defc9cd8 AC |
641 | } |
642 | timing = (recovery << 4) | active | 0x08; | |
643 | ||
cb616dd5 | 644 | ld_qdi->clock[adev->devno] = timing; |
defc9cd8 | 645 | |
cb616dd5 | 646 | outb(timing, ld_qdi->timing); |
defc9cd8 | 647 | } |
669a5db4 JG |
648 | |
649 | /** | |
defc9cd8 AC |
650 | * qdi6580dp_set_piomode - PIO setup for dual channel |
651 | * @ap: Port | |
652 | * @adev: Device | |
669a5db4 | 653 | * |
defc9cd8 | 654 | * In dual channel mode the 6580 has one clock per channel and we have |
9363c382 | 655 | * to software clockswitch in qc_issue. |
669a5db4 JG |
656 | */ |
657 | ||
defc9cd8 | 658 | static void qdi6580dp_set_piomode(struct ata_port *ap, struct ata_device *adev) |
669a5db4 | 659 | { |
defc9cd8 | 660 | struct ata_timing t; |
cb616dd5 | 661 | struct legacy_data *ld_qdi = ap->host->private_data; |
defc9cd8 AC |
662 | int active, recovery; |
663 | u8 timing; | |
669a5db4 | 664 | |
defc9cd8 AC |
665 | /* Get the timing data in cycles */ |
666 | ata_timing_compute(adev, adev->pio_mode, &t, 30303, 1000); | |
667 | ||
cb616dd5 | 668 | if (ld_qdi->fast) { |
07633b5d HH |
669 | active = 8 - clamp_val(t.active, 1, 8); |
670 | recovery = 18 - clamp_val(t.recover, 3, 18); | |
defc9cd8 | 671 | } else { |
07633b5d HH |
672 | active = 9 - clamp_val(t.active, 2, 9); |
673 | recovery = 15 - clamp_val(t.recover, 0, 15); | |
defc9cd8 AC |
674 | } |
675 | timing = (recovery << 4) | active | 0x08; | |
24dc5f33 | 676 | |
cb616dd5 | 677 | ld_qdi->clock[adev->devno] = timing; |
669a5db4 | 678 | |
cb616dd5 | 679 | outb(timing, ld_qdi->timing + 2 * ap->port_no); |
defc9cd8 AC |
680 | /* Clear the FIFO */ |
681 | if (adev->class != ATA_DEV_ATA) | |
6809e730 | 682 | outb(0x5F, (ld_qdi->timing & 0xFFF0) + 3); |
defc9cd8 | 683 | } |
0d5ff566 | 684 | |
defc9cd8 AC |
685 | /** |
686 | * qdi6580_set_piomode - PIO setup for single channel | |
687 | * @ap: Port | |
688 | * @adev: Device | |
689 | * | |
690 | * In single channel mode the 6580 has one clock per device and we can | |
691 | * avoid the requirement to clock switch. We also have to load the timing | |
692 | * into the right clock according to whether we are master or slave. | |
693 | */ | |
694 | ||
695 | static void qdi6580_set_piomode(struct ata_port *ap, struct ata_device *adev) | |
696 | { | |
697 | struct ata_timing t; | |
cb616dd5 | 698 | struct legacy_data *ld_qdi = ap->host->private_data; |
defc9cd8 AC |
699 | int active, recovery; |
700 | u8 timing; | |
701 | ||
702 | /* Get the timing data in cycles */ | |
703 | ata_timing_compute(adev, adev->pio_mode, &t, 30303, 1000); | |
704 | ||
cb616dd5 | 705 | if (ld_qdi->fast) { |
07633b5d HH |
706 | active = 8 - clamp_val(t.active, 1, 8); |
707 | recovery = 18 - clamp_val(t.recover, 3, 18); | |
defc9cd8 | 708 | } else { |
07633b5d HH |
709 | active = 9 - clamp_val(t.active, 2, 9); |
710 | recovery = 15 - clamp_val(t.recover, 0, 15); | |
669a5db4 | 711 | } |
defc9cd8 | 712 | timing = (recovery << 4) | active | 0x08; |
cb616dd5 HH |
713 | ld_qdi->clock[adev->devno] = timing; |
714 | outb(timing, ld_qdi->timing + 2 * adev->devno); | |
defc9cd8 AC |
715 | /* Clear the FIFO */ |
716 | if (adev->class != ATA_DEV_ATA) | |
6809e730 | 717 | outb(0x5F, (ld_qdi->timing & 0xFFF0) + 3); |
defc9cd8 AC |
718 | } |
719 | ||
720 | /** | |
9363c382 | 721 | * qdi_qc_issue - command issue |
defc9cd8 AC |
722 | * @qc: command pending |
723 | * | |
724 | * Called when the libata layer is about to issue a command. We wrap | |
725 | * this interface so that we can load the correct ATA timings. | |
726 | */ | |
727 | ||
9363c382 | 728 | static unsigned int qdi_qc_issue(struct ata_queued_cmd *qc) |
defc9cd8 AC |
729 | { |
730 | struct ata_port *ap = qc->ap; | |
731 | struct ata_device *adev = qc->dev; | |
cb616dd5 | 732 | struct legacy_data *ld_qdi = ap->host->private_data; |
defc9cd8 | 733 | |
cb616dd5 | 734 | if (ld_qdi->clock[adev->devno] != ld_qdi->last) { |
defc9cd8 | 735 | if (adev->pio_mode) { |
cb616dd5 HH |
736 | ld_qdi->last = ld_qdi->clock[adev->devno]; |
737 | outb(ld_qdi->clock[adev->devno], ld_qdi->timing + | |
defc9cd8 AC |
738 | 2 * ap->port_no); |
739 | } | |
669a5db4 | 740 | } |
9363c382 | 741 | return ata_sff_qc_issue(qc); |
defc9cd8 | 742 | } |
669a5db4 | 743 | |
b8325487 | 744 | static unsigned int vlb32_data_xfer(struct ata_device *adev, unsigned char *buf, |
defc9cd8 AC |
745 | unsigned int buflen, int rw) |
746 | { | |
747 | struct ata_port *ap = adev->link->ap; | |
748 | int slop = buflen & 3; | |
669a5db4 | 749 | |
e3cf95dd AC |
750 | if (ata_id_has_dword_io(adev->id) && (slop == 0 || slop == 3) |
751 | && (ap->pflags & ATA_PFLAG_PIO32)) { | |
defc9cd8 AC |
752 | if (rw == WRITE) |
753 | iowrite32_rep(ap->ioaddr.data_addr, buf, buflen >> 2); | |
754 | else | |
755 | ioread32_rep(ap->ioaddr.data_addr, buf, buflen >> 2); | |
669a5db4 | 756 | |
defc9cd8 | 757 | if (unlikely(slop)) { |
6ad67403 | 758 | __le32 pad; |
defc9cd8 AC |
759 | if (rw == WRITE) { |
760 | memcpy(&pad, buf + buflen - slop, slop); | |
6ad67403 | 761 | iowrite32(le32_to_cpu(pad), ap->ioaddr.data_addr); |
defc9cd8 | 762 | } else { |
6ad67403 | 763 | pad = cpu_to_le32(ioread32(ap->ioaddr.data_addr)); |
defc9cd8 AC |
764 | memcpy(buf + buflen - slop, &pad, slop); |
765 | } | |
766 | } | |
767 | return (buflen + 3) & ~3; | |
768 | } else | |
9363c382 | 769 | return ata_sff_data_xfer(adev, buf, buflen, rw); |
defc9cd8 AC |
770 | } |
771 | ||
b8325487 AC |
772 | static int qdi_port(struct platform_device *dev, |
773 | struct legacy_probe *lp, struct legacy_data *ld) | |
774 | { | |
775 | if (devm_request_region(&dev->dev, lp->private, 4, "qdi") == NULL) | |
776 | return -EBUSY; | |
777 | ld->timing = lp->private; | |
778 | return 0; | |
779 | } | |
780 | ||
defc9cd8 | 781 | static struct ata_port_operations qdi6500_port_ops = { |
029cfd6b | 782 | .inherits = &legacy_base_port_ops, |
defc9cd8 | 783 | .set_piomode = qdi6500_set_piomode, |
9363c382 | 784 | .qc_issue = qdi_qc_issue, |
5682ed33 | 785 | .sff_data_xfer = vlb32_data_xfer, |
defc9cd8 AC |
786 | }; |
787 | ||
788 | static struct ata_port_operations qdi6580_port_ops = { | |
029cfd6b | 789 | .inherits = &legacy_base_port_ops, |
defc9cd8 | 790 | .set_piomode = qdi6580_set_piomode, |
5682ed33 | 791 | .sff_data_xfer = vlb32_data_xfer, |
defc9cd8 AC |
792 | }; |
793 | ||
794 | static struct ata_port_operations qdi6580dp_port_ops = { | |
029cfd6b | 795 | .inherits = &legacy_base_port_ops, |
defc9cd8 | 796 | .set_piomode = qdi6580dp_set_piomode, |
43c7d17e | 797 | .qc_issue = qdi_qc_issue, |
5682ed33 | 798 | .sff_data_xfer = vlb32_data_xfer, |
defc9cd8 AC |
799 | }; |
800 | ||
b8325487 AC |
801 | static DEFINE_SPINLOCK(winbond_lock); |
802 | ||
803 | static void winbond_writecfg(unsigned long port, u8 reg, u8 val) | |
804 | { | |
805 | unsigned long flags; | |
806 | spin_lock_irqsave(&winbond_lock, flags); | |
807 | outb(reg, port + 0x01); | |
808 | outb(val, port + 0x02); | |
809 | spin_unlock_irqrestore(&winbond_lock, flags); | |
810 | } | |
811 | ||
812 | static u8 winbond_readcfg(unsigned long port, u8 reg) | |
813 | { | |
814 | u8 val; | |
815 | ||
816 | unsigned long flags; | |
817 | spin_lock_irqsave(&winbond_lock, flags); | |
818 | outb(reg, port + 0x01); | |
819 | val = inb(port + 0x02); | |
820 | spin_unlock_irqrestore(&winbond_lock, flags); | |
821 | ||
822 | return val; | |
823 | } | |
824 | ||
825 | static void winbond_set_piomode(struct ata_port *ap, struct ata_device *adev) | |
826 | { | |
827 | struct ata_timing t; | |
cb616dd5 | 828 | struct legacy_data *ld_winbond = ap->host->private_data; |
b8325487 AC |
829 | int active, recovery; |
830 | u8 reg; | |
831 | int timing = 0x88 + (ap->port_no * 4) + (adev->devno * 2); | |
832 | ||
cb616dd5 | 833 | reg = winbond_readcfg(ld_winbond->timing, 0x81); |
b8325487 AC |
834 | |
835 | /* Get the timing data in cycles */ | |
836 | if (reg & 0x40) /* Fast VLB bus, assume 50MHz */ | |
837 | ata_timing_compute(adev, adev->pio_mode, &t, 20000, 1000); | |
838 | else | |
839 | ata_timing_compute(adev, adev->pio_mode, &t, 30303, 1000); | |
840 | ||
07633b5d HH |
841 | active = (clamp_val(t.active, 3, 17) - 1) & 0x0F; |
842 | recovery = (clamp_val(t.recover, 1, 15) + 1) & 0x0F; | |
b8325487 | 843 | timing = (active << 4) | recovery; |
cb616dd5 | 844 | winbond_writecfg(ld_winbond->timing, timing, reg); |
b8325487 AC |
845 | |
846 | /* Load the setup timing */ | |
847 | ||
848 | reg = 0x35; | |
849 | if (adev->class != ATA_DEV_ATA) | |
850 | reg |= 0x08; /* FIFO off */ | |
851 | if (!ata_pio_need_iordy(adev)) | |
852 | reg |= 0x02; /* IORDY off */ | |
07633b5d | 853 | reg |= (clamp_val(t.setup, 0, 3) << 6); |
cb616dd5 | 854 | winbond_writecfg(ld_winbond->timing, timing + 1, reg); |
b8325487 AC |
855 | } |
856 | ||
857 | static int winbond_port(struct platform_device *dev, | |
858 | struct legacy_probe *lp, struct legacy_data *ld) | |
859 | { | |
860 | if (devm_request_region(&dev->dev, lp->private, 4, "winbond") == NULL) | |
861 | return -EBUSY; | |
862 | ld->timing = lp->private; | |
863 | return 0; | |
864 | } | |
865 | ||
866 | static struct ata_port_operations winbond_port_ops = { | |
029cfd6b | 867 | .inherits = &legacy_base_port_ops, |
b8325487 | 868 | .set_piomode = winbond_set_piomode, |
5682ed33 | 869 | .sff_data_xfer = vlb32_data_xfer, |
b8325487 AC |
870 | }; |
871 | ||
defc9cd8 AC |
872 | static struct legacy_controller controllers[] = { |
873 | {"BIOS", &legacy_port_ops, 0x1F, | |
e3cf95dd | 874 | ATA_FLAG_NO_IORDY, 0, NULL }, |
defc9cd8 | 875 | {"Snooping", &simple_port_ops, 0x1F, |
e3cf95dd | 876 | 0, 0, NULL }, |
defc9cd8 | 877 | {"PDC20230", &pdc20230_port_ops, 0x7, |
e3cf95dd | 878 | ATA_FLAG_NO_IORDY, |
16e6aeca | 879 | ATA_PFLAG_PIO32 | ATA_PFLAG_PIO32CHANGE, NULL }, |
defc9cd8 | 880 | {"HT6560A", &ht6560a_port_ops, 0x07, |
e3cf95dd | 881 | ATA_FLAG_NO_IORDY, 0, NULL }, |
defc9cd8 | 882 | {"HT6560B", &ht6560b_port_ops, 0x1F, |
e3cf95dd | 883 | ATA_FLAG_NO_IORDY, 0, NULL }, |
defc9cd8 | 884 | {"OPTI82C611A", &opti82c611a_port_ops, 0x0F, |
e3cf95dd | 885 | 0, 0, NULL }, |
defc9cd8 | 886 | {"OPTI82C46X", &opti82c46x_port_ops, 0x0F, |
e3cf95dd | 887 | 0, 0, NULL }, |
defc9cd8 | 888 | {"QDI6500", &qdi6500_port_ops, 0x07, |
e3cf95dd | 889 | ATA_FLAG_NO_IORDY, |
16e6aeca | 890 | ATA_PFLAG_PIO32 | ATA_PFLAG_PIO32CHANGE, qdi_port }, |
defc9cd8 | 891 | {"QDI6580", &qdi6580_port_ops, 0x1F, |
16e6aeca | 892 | 0, ATA_PFLAG_PIO32 | ATA_PFLAG_PIO32CHANGE, qdi_port }, |
defc9cd8 | 893 | {"QDI6580DP", &qdi6580dp_port_ops, 0x1F, |
16e6aeca | 894 | 0, ATA_PFLAG_PIO32 | ATA_PFLAG_PIO32CHANGE, qdi_port }, |
b8325487 | 895 | {"W83759A", &winbond_port_ops, 0x1F, |
16e6aeca | 896 | 0, ATA_PFLAG_PIO32 | ATA_PFLAG_PIO32CHANGE, |
e3cf95dd | 897 | winbond_port } |
defc9cd8 AC |
898 | }; |
899 | ||
900 | /** | |
901 | * probe_chip_type - Discover controller | |
902 | * @probe: Probe entry to check | |
903 | * | |
904 | * Probe an ATA port and identify the type of controller. We don't | |
905 | * check if the controller appears to be driveless at this point. | |
906 | */ | |
907 | ||
b8325487 | 908 | static __init int probe_chip_type(struct legacy_probe *probe) |
defc9cd8 AC |
909 | { |
910 | int mask = 1 << probe->slot; | |
911 | ||
b8325487 AC |
912 | if (winbond && (probe->port == 0x1F0 || probe->port == 0x170)) { |
913 | u8 reg = winbond_readcfg(winbond, 0x81); | |
914 | reg |= 0x80; /* jumpered mode off */ | |
915 | winbond_writecfg(winbond, 0x81, reg); | |
916 | reg = winbond_readcfg(winbond, 0x83); | |
917 | reg |= 0xF0; /* local control */ | |
918 | winbond_writecfg(winbond, 0x83, reg); | |
919 | reg = winbond_readcfg(winbond, 0x85); | |
920 | reg |= 0xF0; /* programmable timing */ | |
921 | winbond_writecfg(winbond, 0x85, reg); | |
922 | ||
923 | reg = winbond_readcfg(winbond, 0x81); | |
924 | ||
925 | if (reg & mask) | |
926 | return W83759A; | |
927 | } | |
defc9cd8 AC |
928 | if (probe->port == 0x1F0) { |
929 | unsigned long flags; | |
930 | local_irq_save(flags); | |
669a5db4 | 931 | /* Probes */ |
669a5db4 | 932 | outb(inb(0x1F2) | 0x80, 0x1F2); |
defc9cd8 | 933 | inb(0x1F5); |
669a5db4 JG |
934 | inb(0x1F2); |
935 | inb(0x3F6); | |
936 | inb(0x3F6); | |
937 | inb(0x1F2); | |
938 | inb(0x1F2); | |
939 | ||
940 | if ((inb(0x1F2) & 0x80) == 0) { | |
941 | /* PDC20230c or 20630 ? */ | |
defc9cd8 AC |
942 | printk(KERN_INFO "PDC20230-C/20630 VLB ATA controller" |
943 | " detected.\n"); | |
669a5db4 JG |
944 | udelay(100); |
945 | inb(0x1F5); | |
defc9cd8 AC |
946 | local_irq_restore(flags); |
947 | return PDC20230; | |
669a5db4 JG |
948 | } else { |
949 | outb(0x55, 0x1F2); | |
950 | inb(0x1F2); | |
951 | inb(0x1F2); | |
defc9cd8 AC |
952 | if (inb(0x1F2) == 0x00) |
953 | printk(KERN_INFO "PDC20230-B VLB ATA " | |
954 | "controller detected.\n"); | |
955 | local_irq_restore(flags); | |
956 | return BIOS; | |
669a5db4 JG |
957 | } |
958 | local_irq_restore(flags); | |
959 | } | |
960 | ||
defc9cd8 AC |
961 | if (ht6560a & mask) |
962 | return HT6560A; | |
963 | if (ht6560b & mask) | |
964 | return HT6560B; | |
965 | if (opti82c611a & mask) | |
966 | return OPTI611A; | |
967 | if (opti82c46x & mask) | |
968 | return OPTI46X; | |
969 | if (autospeed & mask) | |
970 | return SNOOP; | |
971 | return BIOS; | |
972 | } | |
973 | ||
974 | ||
975 | /** | |
976 | * legacy_init_one - attach a legacy interface | |
977 | * @pl: probe record | |
978 | * | |
979 | * Register an ISA bus IDE interface. Such interfaces are PIO and we | |
980 | * assume do not support IRQ sharing. | |
981 | */ | |
982 | ||
983 | static __init int legacy_init_one(struct legacy_probe *probe) | |
984 | { | |
985 | struct legacy_controller *controller = &controllers[probe->type]; | |
986 | int pio_modes = controller->pio_mask; | |
987 | unsigned long io = probe->port; | |
988 | u32 mask = (1 << probe->slot); | |
989 | struct ata_port_operations *ops = controller->ops; | |
990 | struct legacy_data *ld = &legacy_data[probe->slot]; | |
991 | struct ata_host *host = NULL; | |
992 | struct ata_port *ap; | |
993 | struct platform_device *pdev; | |
994 | struct ata_device *dev; | |
995 | void __iomem *io_addr, *ctrl_addr; | |
996 | u32 iordy = (iordy_mask & mask) ? 0: ATA_FLAG_NO_IORDY; | |
997 | int ret; | |
998 | ||
999 | iordy |= controller->flags; | |
1000 | ||
1001 | pdev = platform_device_register_simple(DRV_NAME, probe->slot, NULL, 0); | |
1002 | if (IS_ERR(pdev)) | |
1003 | return PTR_ERR(pdev); | |
669a5db4 | 1004 | |
defc9cd8 AC |
1005 | ret = -EBUSY; |
1006 | if (devm_request_region(&pdev->dev, io, 8, "pata_legacy") == NULL || | |
1007 | devm_request_region(&pdev->dev, io + 0x0206, 1, | |
1008 | "pata_legacy") == NULL) | |
1009 | goto fail; | |
f834e49f | 1010 | |
5d728824 | 1011 | ret = -ENOMEM; |
defc9cd8 AC |
1012 | io_addr = devm_ioport_map(&pdev->dev, io, 8); |
1013 | ctrl_addr = devm_ioport_map(&pdev->dev, io + 0x0206, 1); | |
1014 | if (!io_addr || !ctrl_addr) | |
1015 | goto fail; | |
1016 | if (controller->setup) | |
b8325487 | 1017 | if (controller->setup(pdev, probe, ld) < 0) |
defc9cd8 | 1018 | goto fail; |
5d728824 TH |
1019 | host = ata_host_alloc(&pdev->dev, 1); |
1020 | if (!host) | |
1021 | goto fail; | |
1022 | ap = host->ports[0]; | |
1023 | ||
1024 | ap->ops = ops; | |
1025 | ap->pio_mask = pio_modes; | |
1026 | ap->flags |= ATA_FLAG_SLAVE_POSS | iordy; | |
e3cf95dd | 1027 | ap->pflags |= controller->pflags; |
5d728824 TH |
1028 | ap->ioaddr.cmd_addr = io_addr; |
1029 | ap->ioaddr.altstatus_addr = ctrl_addr; | |
1030 | ap->ioaddr.ctl_addr = ctrl_addr; | |
9363c382 | 1031 | ata_sff_std_ports(&ap->ioaddr); |
b8325487 | 1032 | ap->host->private_data = ld; |
5d728824 | 1033 | |
defc9cd8 | 1034 | ata_port_desc(ap, "cmd 0x%lx ctl 0x%lx", io, io + 0x0206); |
cbcdd875 | 1035 | |
9363c382 TH |
1036 | ret = ata_host_activate(host, probe->irq, ata_sff_interrupt, 0, |
1037 | &legacy_sht); | |
5d728824 | 1038 | if (ret) |
669a5db4 | 1039 | goto fail; |
45bc955b | 1040 | async_synchronize_full(); |
669a5db4 | 1041 | ld->platform_dev = pdev; |
669a5db4 | 1042 | |
defc9cd8 AC |
1043 | /* Nothing found means we drop the port as its probably not there */ |
1044 | ||
1045 | ret = -ENODEV; | |
1eca4365 | 1046 | ata_for_each_dev(dev, &ap->link, ALL) { |
defc9cd8 AC |
1047 | if (!ata_dev_absent(dev)) { |
1048 | legacy_host[probe->slot] = host; | |
1049 | ld->platform_dev = pdev; | |
1050 | return 0; | |
1051 | } | |
1052 | } | |
20cbf5f8 | 1053 | ata_host_detach(host); |
669a5db4 JG |
1054 | fail: |
1055 | platform_device_unregister(pdev); | |
669a5db4 JG |
1056 | return ret; |
1057 | } | |
1058 | ||
1059 | /** | |
1060 | * legacy_check_special_cases - ATA special cases | |
1061 | * @p: PCI device to check | |
1062 | * @master: set this if we find an ATA master | |
1063 | * @master: set this if we find an ATA secondary | |
1064 | * | |
defc9cd8 AC |
1065 | * A small number of vendors implemented early PCI ATA interfaces |
1066 | * on bridge logic without the ATA interface being PCI visible. | |
1067 | * Where we have a matching PCI driver we must skip the relevant | |
1068 | * device here. If we don't know about it then the legacy driver | |
1069 | * is the right driver anyway. | |
669a5db4 JG |
1070 | */ |
1071 | ||
b8325487 | 1072 | static void __init legacy_check_special_cases(struct pci_dev *p, int *primary, |
defc9cd8 | 1073 | int *secondary) |
669a5db4 JG |
1074 | { |
1075 | /* Cyrix CS5510 pre SFF MWDMA ATA on the bridge */ | |
1076 | if (p->vendor == 0x1078 && p->device == 0x0000) { | |
1077 | *primary = *secondary = 1; | |
1078 | return; | |
1079 | } | |
1080 | /* Cyrix CS5520 pre SFF MWDMA ATA on the bridge */ | |
1081 | if (p->vendor == 0x1078 && p->device == 0x0002) { | |
1082 | *primary = *secondary = 1; | |
1083 | return; | |
1084 | } | |
1085 | /* Intel MPIIX - PIO ATA on non PCI side of bridge */ | |
1086 | if (p->vendor == 0x8086 && p->device == 0x1234) { | |
1087 | u16 r; | |
1088 | pci_read_config_word(p, 0x6C, &r); | |
defc9cd8 AC |
1089 | if (r & 0x8000) { |
1090 | /* ATA port enabled */ | |
669a5db4 JG |
1091 | if (r & 0x4000) |
1092 | *secondary = 1; | |
1093 | else | |
1094 | *primary = 1; | |
1095 | } | |
1096 | return; | |
1097 | } | |
1098 | } | |
1099 | ||
defc9cd8 AC |
1100 | static __init void probe_opti_vlb(void) |
1101 | { | |
1102 | /* If an OPTI 82C46X is present find out where the channels are */ | |
1103 | static const char *optis[4] = { | |
1104 | "3/463MV", "5MV", | |
1105 | "5MVA", "5MVB" | |
1106 | }; | |
1107 | u8 chans = 1; | |
1108 | u8 ctrl = (opti_syscfg(0x30) & 0xC0) >> 6; | |
1109 | ||
1110 | opti82c46x = 3; /* Assume master and slave first */ | |
1111 | printk(KERN_INFO DRV_NAME ": Opti 82C46%s chipset support.\n", | |
1112 | optis[ctrl]); | |
1113 | if (ctrl == 3) | |
1114 | chans = (opti_syscfg(0x3F) & 0x20) ? 2 : 1; | |
1115 | ctrl = opti_syscfg(0xAC); | |
1116 | /* Check enabled and this port is the 465MV port. On the | |
1117 | MVB we may have two channels */ | |
1118 | if (ctrl & 8) { | |
1119 | if (chans == 2) { | |
1120 | legacy_probe_add(0x1F0, 14, OPTI46X, 0); | |
1121 | legacy_probe_add(0x170, 15, OPTI46X, 0); | |
1122 | } | |
1123 | if (ctrl & 4) | |
1124 | legacy_probe_add(0x170, 15, OPTI46X, 0); | |
1125 | else | |
1126 | legacy_probe_add(0x1F0, 14, OPTI46X, 0); | |
1127 | } else | |
1128 | legacy_probe_add(0x1F0, 14, OPTI46X, 0); | |
1129 | } | |
1130 | ||
1131 | static __init void qdi65_identify_port(u8 r, u8 res, unsigned long port) | |
1132 | { | |
1133 | static const unsigned long ide_port[2] = { 0x170, 0x1F0 }; | |
1134 | /* Check card type */ | |
1135 | if ((r & 0xF0) == 0xC0) { | |
1136 | /* QD6500: single channel */ | |
b8325487 | 1137 | if (r & 8) |
defc9cd8 | 1138 | /* Disabled ? */ |
defc9cd8 | 1139 | return; |
defc9cd8 AC |
1140 | legacy_probe_add(ide_port[r & 0x01], 14 + (r & 0x01), |
1141 | QDI6500, port); | |
1142 | } | |
1143 | if (((r & 0xF0) == 0xA0) || (r & 0xF0) == 0x50) { | |
1144 | /* QD6580: dual channel */ | |
1145 | if (!request_region(port + 2 , 2, "pata_qdi")) { | |
1146 | release_region(port, 2); | |
1147 | return; | |
1148 | } | |
1149 | res = inb(port + 3); | |
1150 | /* Single channel mode ? */ | |
1151 | if (res & 1) | |
1152 | legacy_probe_add(ide_port[r & 0x01], 14 + (r & 0x01), | |
1153 | QDI6580, port); | |
1154 | else { /* Dual channel mode */ | |
1155 | legacy_probe_add(0x1F0, 14, QDI6580DP, port); | |
1156 | /* port + 0x02, r & 0x04 */ | |
1157 | legacy_probe_add(0x170, 15, QDI6580DP, port + 2); | |
1158 | } | |
b8325487 | 1159 | release_region(port + 2, 2); |
defc9cd8 AC |
1160 | } |
1161 | } | |
1162 | ||
1163 | static __init void probe_qdi_vlb(void) | |
1164 | { | |
1165 | unsigned long flags; | |
1166 | static const unsigned long qd_port[2] = { 0x30, 0xB0 }; | |
1167 | int i; | |
1168 | ||
1169 | /* | |
1170 | * Check each possible QD65xx base address | |
1171 | */ | |
1172 | ||
1173 | for (i = 0; i < 2; i++) { | |
1174 | unsigned long port = qd_port[i]; | |
1175 | u8 r, res; | |
1176 | ||
1177 | ||
1178 | if (request_region(port, 2, "pata_qdi")) { | |
1179 | /* Check for a card */ | |
1180 | local_irq_save(flags); | |
1181 | /* I have no h/w that needs this delay but it | |
1182 | is present in the historic code */ | |
1183 | r = inb(port); | |
1184 | udelay(1); | |
1185 | outb(0x19, port); | |
1186 | udelay(1); | |
1187 | res = inb(port); | |
1188 | udelay(1); | |
1189 | outb(r, port); | |
1190 | udelay(1); | |
1191 | local_irq_restore(flags); | |
1192 | ||
1193 | /* Fail */ | |
1194 | if (res == 0x19) { | |
1195 | release_region(port, 2); | |
1196 | continue; | |
1197 | } | |
1198 | /* Passes the presence test */ | |
1199 | r = inb(port + 1); | |
1200 | udelay(1); | |
1201 | /* Check port agrees with port set */ | |
b8325487 AC |
1202 | if ((r & 2) >> 1 == i) |
1203 | qdi65_identify_port(r, res, port); | |
1204 | release_region(port, 2); | |
defc9cd8 AC |
1205 | } |
1206 | } | |
1207 | } | |
669a5db4 JG |
1208 | |
1209 | /** | |
1210 | * legacy_init - attach legacy interfaces | |
1211 | * | |
1212 | * Attach legacy IDE interfaces by scanning the usual IRQ/port suspects. | |
1213 | * Right now we do not scan the ide0 and ide1 address but should do so | |
1214 | * for non PCI systems or systems with no PCI IDE legacy mode devices. | |
1215 | * If you fix that note there are special cases to consider like VLB | |
1216 | * drivers and CS5510/20. | |
1217 | */ | |
1218 | ||
1219 | static __init int legacy_init(void) | |
1220 | { | |
1221 | int i; | |
1222 | int ct = 0; | |
1223 | int primary = 0; | |
1224 | int secondary = 0; | |
defc9cd8 AC |
1225 | int pci_present = 0; |
1226 | struct legacy_probe *pl = &probe_list[0]; | |
1227 | int slot = 0; | |
669a5db4 JG |
1228 | |
1229 | struct pci_dev *p = NULL; | |
1230 | ||
1231 | for_each_pci_dev(p) { | |
1232 | int r; | |
defc9cd8 AC |
1233 | /* Check for any overlap of the system ATA mappings. Native |
1234 | mode controllers stuck on these addresses or some devices | |
1235 | in 'raid' mode won't be found by the storage class test */ | |
669a5db4 JG |
1236 | for (r = 0; r < 6; r++) { |
1237 | if (pci_resource_start(p, r) == 0x1f0) | |
1238 | primary = 1; | |
1239 | if (pci_resource_start(p, r) == 0x170) | |
1240 | secondary = 1; | |
1241 | } | |
1242 | /* Check for special cases */ | |
1243 | legacy_check_special_cases(p, &primary, &secondary); | |
1244 | ||
defc9cd8 AC |
1245 | /* If PCI bus is present then don't probe for tertiary |
1246 | legacy ports */ | |
1247 | pci_present = 1; | |
669a5db4 JG |
1248 | } |
1249 | ||
b8325487 AC |
1250 | if (winbond == 1) |
1251 | winbond = 0x130; /* Default port, alt is 1B0 */ | |
1252 | ||
defc9cd8 AC |
1253 | if (primary == 0 || all) |
1254 | legacy_probe_add(0x1F0, 14, UNKNOWN, 0); | |
1255 | if (secondary == 0 || all) | |
1256 | legacy_probe_add(0x170, 15, UNKNOWN, 0); | |
1257 | ||
1258 | if (probe_all || !pci_present) { | |
1259 | /* ISA/VLB extra ports */ | |
1260 | legacy_probe_add(0x1E8, 11, UNKNOWN, 0); | |
1261 | legacy_probe_add(0x168, 10, UNKNOWN, 0); | |
1262 | legacy_probe_add(0x1E0, 8, UNKNOWN, 0); | |
1263 | legacy_probe_add(0x160, 12, UNKNOWN, 0); | |
669a5db4 JG |
1264 | } |
1265 | ||
defc9cd8 AC |
1266 | if (opti82c46x) |
1267 | probe_opti_vlb(); | |
1268 | if (qdi) | |
1269 | probe_qdi_vlb(); | |
1270 | ||
defc9cd8 AC |
1271 | for (i = 0; i < NR_HOST; i++, pl++) { |
1272 | if (pl->port == 0) | |
669a5db4 | 1273 | continue; |
defc9cd8 AC |
1274 | if (pl->type == UNKNOWN) |
1275 | pl->type = probe_chip_type(pl); | |
1276 | pl->slot = slot++; | |
1277 | if (legacy_init_one(pl) == 0) | |
669a5db4 JG |
1278 | ct++; |
1279 | } | |
1280 | if (ct != 0) | |
1281 | return 0; | |
1282 | return -ENODEV; | |
1283 | } | |
1284 | ||
1285 | static __exit void legacy_exit(void) | |
1286 | { | |
1287 | int i; | |
1288 | ||
1289 | for (i = 0; i < nr_legacy_host; i++) { | |
1290 | struct legacy_data *ld = &legacy_data[i]; | |
24dc5f33 | 1291 | ata_host_detach(legacy_host[i]); |
669a5db4 | 1292 | platform_device_unregister(ld->platform_dev); |
669a5db4 JG |
1293 | } |
1294 | } | |
1295 | ||
1296 | MODULE_AUTHOR("Alan Cox"); | |
1297 | MODULE_DESCRIPTION("low-level driver for legacy ATA"); | |
1298 | MODULE_LICENSE("GPL"); | |
1299 | MODULE_VERSION(DRV_VERSION); | |
1300 | ||
1301 | module_param(probe_all, int, 0); | |
1302 | module_param(autospeed, int, 0); | |
1303 | module_param(ht6560a, int, 0); | |
1304 | module_param(ht6560b, int, 0); | |
1305 | module_param(opti82c611a, int, 0); | |
1306 | module_param(opti82c46x, int, 0); | |
defc9cd8 | 1307 | module_param(qdi, int, 0); |
669a5db4 | 1308 | module_param(pio_mask, int, 0); |
f834e49f | 1309 | module_param(iordy_mask, int, 0); |
669a5db4 JG |
1310 | |
1311 | module_init(legacy_init); | |
1312 | module_exit(legacy_exit); |