Commit | Line | Data |
---|---|---|
669a5db4 JG |
1 | /* |
2 | * pata-legacy.c - Legacy port PATA/SATA controller driver. | |
3 | * Copyright 2005/2006 Red Hat <alan@redhat.com>, all rights reserved. | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify | |
6 | * it under the terms of the GNU General Public License as published by | |
7 | * the Free Software Foundation; either version 2, or (at your option) | |
8 | * any later version. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
14 | * | |
15 | * You should have received a copy of the GNU General Public License | |
16 | * along with this program; see the file COPYING. If not, write to | |
17 | * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. | |
18 | * | |
19 | * An ATA driver for the legacy ATA ports. | |
20 | * | |
21 | * Data Sources: | |
22 | * Opti 82C465/82C611 support: Data sheets at opti-inc.com | |
23 | * HT6560 series: | |
24 | * Promise 20230/20620: | |
25 | * http://www.ryston.cz/petr/vlb/pdc20230b.html | |
26 | * http://www.ryston.cz/petr/vlb/pdc20230c.html | |
27 | * http://www.ryston.cz/petr/vlb/pdc20630.html | |
28 | * | |
29 | * Unsupported but docs exist: | |
30 | * Appian/Adaptec AIC25VL01/Cirrus Logic PD7220 | |
669a5db4 JG |
31 | * |
32 | * This driver handles legacy (that is "ISA/VLB side") IDE ports found | |
33 | * on PC class systems. There are three hybrid devices that are exceptions | |
34 | * The Cyrix 5510/5520 where a pre SFF ATA device is on the bridge and | |
35 | * the MPIIX where the tuning is PCI side but the IDE is "ISA side". | |
36 | * | |
37 | * Specific support is included for the ht6560a/ht6560b/opti82c611a/ | |
b8325487 | 38 | * opti82c465mv/promise 20230c/20630/winbond83759A |
669a5db4 JG |
39 | * |
40 | * Use the autospeed and pio_mask options with: | |
41 | * Appian ADI/2 aka CLPD7220 or AIC25VL01. | |
42 | * Use the jumpers, autospeed and set pio_mask to the mode on the jumpers with | |
43 | * Goldstar GM82C711, PIC-1288A-125, UMC 82C871F, Winbond W83759, | |
44 | * Winbond W83759A, Promise PDC20230-B | |
45 | * | |
46 | * For now use autospeed and pio_mask as above with the W83759A. This may | |
47 | * change. | |
48 | * | |
669a5db4 JG |
49 | */ |
50 | ||
51 | #include <linux/kernel.h> | |
52 | #include <linux/module.h> | |
53 | #include <linux/pci.h> | |
54 | #include <linux/init.h> | |
55 | #include <linux/blkdev.h> | |
56 | #include <linux/delay.h> | |
57 | #include <scsi/scsi_host.h> | |
58 | #include <linux/ata.h> | |
59 | #include <linux/libata.h> | |
60 | #include <linux/platform_device.h> | |
61 | ||
62 | #define DRV_NAME "pata_legacy" | |
b8325487 | 63 | #define DRV_VERSION "0.6.5" |
669a5db4 JG |
64 | |
65 | #define NR_HOST 6 | |
66 | ||
defc9cd8 AC |
67 | static int all; |
68 | module_param(all, int, 0444); | |
69 | MODULE_PARM_DESC(all, "Grab all legacy port devices, even if PCI(0=off, 1=on)"); | |
669a5db4 JG |
70 | |
71 | struct legacy_data { | |
72 | unsigned long timing; | |
73 | u8 clock[2]; | |
74 | u8 last; | |
75 | int fast; | |
76 | struct platform_device *platform_dev; | |
77 | ||
78 | }; | |
79 | ||
defc9cd8 AC |
80 | enum controller { |
81 | BIOS = 0, | |
82 | SNOOP = 1, | |
83 | PDC20230 = 2, | |
84 | HT6560A = 3, | |
85 | HT6560B = 4, | |
86 | OPTI611A = 5, | |
87 | OPTI46X = 6, | |
88 | QDI6500 = 7, | |
89 | QDI6580 = 8, | |
90 | QDI6580DP = 9, /* Dual channel mode is different */ | |
b8325487 | 91 | W83759A = 10, |
defc9cd8 AC |
92 | |
93 | UNKNOWN = -1 | |
94 | }; | |
95 | ||
96 | ||
97 | struct legacy_probe { | |
98 | unsigned char *name; | |
99 | unsigned long port; | |
100 | unsigned int irq; | |
101 | unsigned int slot; | |
102 | enum controller type; | |
103 | unsigned long private; | |
104 | }; | |
105 | ||
106 | struct legacy_controller { | |
107 | const char *name; | |
108 | struct ata_port_operations *ops; | |
109 | unsigned int pio_mask; | |
110 | unsigned int flags; | |
b8325487 AC |
111 | int (*setup)(struct platform_device *, struct legacy_probe *probe, |
112 | struct legacy_data *data); | |
defc9cd8 AC |
113 | }; |
114 | ||
115 | static int legacy_port[NR_HOST] = { 0x1f0, 0x170, 0x1e8, 0x168, 0x1e0, 0x160 }; | |
116 | ||
117 | static struct legacy_probe probe_list[NR_HOST]; | |
669a5db4 JG |
118 | static struct legacy_data legacy_data[NR_HOST]; |
119 | static struct ata_host *legacy_host[NR_HOST]; | |
120 | static int nr_legacy_host; | |
121 | ||
122 | ||
defc9cd8 AC |
123 | static int probe_all; /* Set to check all ISA port ranges */ |
124 | static int ht6560a; /* HT 6560A on primary 1, second 2, both 3 */ | |
125 | static int ht6560b; /* HT 6560A on primary 1, second 2, both 3 */ | |
126 | static int opti82c611a; /* Opti82c611A on primary 1, sec 2, both 3 */ | |
127 | static int opti82c46x; /* Opti 82c465MV present(pri/sec autodetect) */ | |
128 | static int qdi; /* Set to probe QDI controllers */ | |
b8325487 | 129 | static int winbond; /* Set to probe Winbond controllers, |
8397248d | 130 | give I/O port if non standard */ |
defc9cd8 AC |
131 | static int autospeed; /* Chip present which snoops speed changes */ |
132 | static int pio_mask = 0x1F; /* PIO range for autospeed devices */ | |
f834e49f | 133 | static int iordy_mask = 0xFFFFFFFF; /* Use iordy if available */ |
669a5db4 | 134 | |
defc9cd8 AC |
135 | /** |
136 | * legacy_probe_add - Add interface to probe list | |
137 | * @port: Controller port | |
138 | * @irq: IRQ number | |
139 | * @type: Controller type | |
140 | * @private: Controller specific info | |
141 | * | |
142 | * Add an entry into the probe list for ATA controllers. This is used | |
143 | * to add the default ISA slots and then to build up the table | |
144 | * further according to other ISA/VLB/Weird device scans | |
145 | * | |
146 | * An I/O port list is used to keep ordering stable and sane, as we | |
147 | * don't have any good way to talk about ordering otherwise | |
148 | */ | |
149 | ||
150 | static int legacy_probe_add(unsigned long port, unsigned int irq, | |
151 | enum controller type, unsigned long private) | |
152 | { | |
153 | struct legacy_probe *lp = &probe_list[0]; | |
154 | int i; | |
155 | struct legacy_probe *free = NULL; | |
156 | ||
157 | for (i = 0; i < NR_HOST; i++) { | |
158 | if (lp->port == 0 && free == NULL) | |
159 | free = lp; | |
160 | /* Matching port, or the correct slot for ordering */ | |
161 | if (lp->port == port || legacy_port[i] == port) { | |
162 | free = lp; | |
163 | break; | |
164 | } | |
165 | lp++; | |
166 | } | |
167 | if (free == NULL) { | |
168 | printk(KERN_ERR "pata_legacy: Too many interfaces.\n"); | |
169 | return -1; | |
170 | } | |
171 | /* Fill in the entry for later probing */ | |
172 | free->port = port; | |
173 | free->irq = irq; | |
174 | free->type = type; | |
175 | free->private = private; | |
176 | return 0; | |
177 | } | |
178 | ||
179 | ||
669a5db4 JG |
180 | /** |
181 | * legacy_set_mode - mode setting | |
0260731f | 182 | * @link: IDE link |
b229a7b0 | 183 | * @unused: Device that failed when error is returned |
669a5db4 JG |
184 | * |
185 | * Use a non standard set_mode function. We don't want to be tuned. | |
186 | * | |
187 | * The BIOS configured everything. Our job is not to fiddle. Just use | |
188 | * whatever PIO the hardware is using and leave it at that. When we | |
189 | * get some kind of nice user driven API for control then we can | |
190 | * expand on this as per hdparm in the base kernel. | |
191 | */ | |
192 | ||
0260731f | 193 | static int legacy_set_mode(struct ata_link *link, struct ata_device **unused) |
669a5db4 | 194 | { |
f58229f8 | 195 | struct ata_device *dev; |
669a5db4 | 196 | |
0260731f | 197 | ata_link_for_each_dev(dev, link) { |
669a5db4 | 198 | if (ata_dev_enabled(dev)) { |
defc9cd8 AC |
199 | ata_dev_printk(dev, KERN_INFO, |
200 | "configured for PIO\n"); | |
669a5db4 JG |
201 | dev->pio_mode = XFER_PIO_0; |
202 | dev->xfer_mode = XFER_PIO_0; | |
203 | dev->xfer_shift = ATA_SHIFT_PIO; | |
204 | dev->flags |= ATA_DFLAG_PIO; | |
205 | } | |
206 | } | |
b229a7b0 | 207 | return 0; |
669a5db4 JG |
208 | } |
209 | ||
210 | static struct scsi_host_template legacy_sht = { | |
68d1d07b | 211 | ATA_PIO_SHT(DRV_NAME), |
669a5db4 JG |
212 | }; |
213 | ||
029cfd6b TH |
214 | static const struct ata_port_operations legacy_base_port_ops = { |
215 | .inherits = &ata_sff_port_ops, | |
216 | .cable_detect = ata_cable_40wire, | |
217 | }; | |
218 | ||
669a5db4 JG |
219 | /* |
220 | * These ops are used if the user indicates the hardware | |
221 | * snoops the commands to decide on the mode and handles the | |
222 | * mode selection "magically" itself. Several legacy controllers | |
223 | * do this. The mode range can be set if it is not 0x1F by setting | |
224 | * pio_mask as well. | |
225 | */ | |
226 | ||
227 | static struct ata_port_operations simple_port_ops = { | |
029cfd6b | 228 | .inherits = &legacy_base_port_ops, |
9363c382 | 229 | .data_xfer = ata_sff_data_xfer_noirq, |
669a5db4 JG |
230 | }; |
231 | ||
232 | static struct ata_port_operations legacy_port_ops = { | |
029cfd6b | 233 | .inherits = &legacy_base_port_ops, |
9363c382 | 234 | .data_xfer = ata_sff_data_xfer_noirq, |
029cfd6b | 235 | .set_mode = legacy_set_mode, |
669a5db4 JG |
236 | }; |
237 | ||
238 | /* | |
239 | * Promise 20230C and 20620 support | |
240 | * | |
defc9cd8 AC |
241 | * This controller supports PIO0 to PIO2. We set PIO timings |
242 | * conservatively to allow for 50MHz Vesa Local Bus. The 20620 DMA | |
243 | * support is weird being DMA to controller and PIO'd to the host | |
244 | * and not supported. | |
669a5db4 JG |
245 | */ |
246 | ||
247 | static void pdc20230_set_piomode(struct ata_port *ap, struct ata_device *adev) | |
248 | { | |
249 | int tries = 5; | |
250 | int pio = adev->pio_mode - XFER_PIO_0; | |
251 | u8 rt; | |
252 | unsigned long flags; | |
85cd7251 | 253 | |
669a5db4 | 254 | /* Safe as UP only. Force I/Os to occur together */ |
85cd7251 | 255 | |
669a5db4 | 256 | local_irq_save(flags); |
85cd7251 | 257 | |
669a5db4 | 258 | /* Unlock the control interface */ |
defc9cd8 | 259 | do { |
669a5db4 JG |
260 | inb(0x1F5); |
261 | outb(inb(0x1F2) | 0x80, 0x1F2); | |
262 | inb(0x1F2); | |
263 | inb(0x3F6); | |
264 | inb(0x3F6); | |
265 | inb(0x1F2); | |
266 | inb(0x1F2); | |
267 | } | |
defc9cd8 | 268 | while ((inb(0x1F2) & 0x80) && --tries); |
669a5db4 JG |
269 | |
270 | local_irq_restore(flags); | |
85cd7251 | 271 | |
669a5db4 JG |
272 | outb(inb(0x1F4) & 0x07, 0x1F4); |
273 | ||
274 | rt = inb(0x1F3); | |
275 | rt &= 0x07 << (3 * adev->devno); | |
276 | if (pio) | |
277 | rt |= (1 + 3 * pio) << (3 * adev->devno); | |
278 | ||
279 | udelay(100); | |
280 | outb(inb(0x1F2) | 0x01, 0x1F2); | |
281 | udelay(100); | |
282 | inb(0x1F5); | |
283 | ||
284 | } | |
285 | ||
55dba312 | 286 | static unsigned int pdc_data_xfer_vlb(struct ata_device *dev, |
defc9cd8 | 287 | unsigned char *buf, unsigned int buflen, int rw) |
669a5db4 | 288 | { |
c294f1b3 | 289 | if (ata_id_has_dword_io(dev->id)) { |
55dba312 TH |
290 | struct ata_port *ap = dev->link->ap; |
291 | int slop = buflen & 3; | |
292 | unsigned long flags; | |
293 | ||
669a5db4 JG |
294 | local_irq_save(flags); |
295 | ||
296 | /* Perform the 32bit I/O synchronization sequence */ | |
0d5ff566 TH |
297 | ioread8(ap->ioaddr.nsect_addr); |
298 | ioread8(ap->ioaddr.nsect_addr); | |
299 | ioread8(ap->ioaddr.nsect_addr); | |
669a5db4 JG |
300 | |
301 | /* Now the data */ | |
55dba312 | 302 | if (rw == READ) |
0d5ff566 | 303 | ioread32_rep(ap->ioaddr.data_addr, buf, buflen >> 2); |
55dba312 TH |
304 | else |
305 | iowrite32_rep(ap->ioaddr.data_addr, buf, buflen >> 2); | |
669a5db4 JG |
306 | |
307 | if (unlikely(slop)) { | |
55dba312 TH |
308 | u32 pad; |
309 | if (rw == READ) { | |
b50e56d8 | 310 | pad = cpu_to_le32(ioread32(ap->ioaddr.data_addr)); |
669a5db4 | 311 | memcpy(buf + buflen - slop, &pad, slop); |
55dba312 TH |
312 | } else { |
313 | memcpy(&pad, buf + buflen - slop, slop); | |
314 | iowrite32(le32_to_cpu(pad), ap->ioaddr.data_addr); | |
669a5db4 | 315 | } |
55dba312 | 316 | buflen += 4 - slop; |
669a5db4 JG |
317 | } |
318 | local_irq_restore(flags); | |
55dba312 | 319 | } else |
9363c382 | 320 | buflen = ata_sff_data_xfer_noirq(dev, buf, buflen, rw); |
55dba312 TH |
321 | |
322 | return buflen; | |
669a5db4 JG |
323 | } |
324 | ||
325 | static struct ata_port_operations pdc20230_port_ops = { | |
029cfd6b | 326 | .inherits = &legacy_base_port_ops, |
669a5db4 | 327 | .set_piomode = pdc20230_set_piomode, |
669a5db4 | 328 | .data_xfer = pdc_data_xfer_vlb, |
669a5db4 JG |
329 | }; |
330 | ||
331 | /* | |
332 | * Holtek 6560A support | |
333 | * | |
defc9cd8 AC |
334 | * This controller supports PIO0 to PIO2 (no IORDY even though higher |
335 | * timings can be loaded). | |
669a5db4 JG |
336 | */ |
337 | ||
338 | static void ht6560a_set_piomode(struct ata_port *ap, struct ata_device *adev) | |
339 | { | |
340 | u8 active, recover; | |
341 | struct ata_timing t; | |
342 | ||
343 | /* Get the timing data in cycles. For now play safe at 50Mhz */ | |
344 | ata_timing_compute(adev, adev->pio_mode, &t, 20000, 1000); | |
345 | ||
346 | active = FIT(t.active, 2, 15); | |
347 | recover = FIT(t.recover, 4, 15); | |
348 | ||
349 | inb(0x3E6); | |
350 | inb(0x3E6); | |
351 | inb(0x3E6); | |
352 | inb(0x3E6); | |
353 | ||
0d5ff566 TH |
354 | iowrite8(recover << 4 | active, ap->ioaddr.device_addr); |
355 | ioread8(ap->ioaddr.status_addr); | |
669a5db4 JG |
356 | } |
357 | ||
358 | static struct ata_port_operations ht6560a_port_ops = { | |
029cfd6b | 359 | .inherits = &legacy_base_port_ops, |
669a5db4 | 360 | .set_piomode = ht6560a_set_piomode, |
669a5db4 JG |
361 | }; |
362 | ||
363 | /* | |
364 | * Holtek 6560B support | |
365 | * | |
defc9cd8 AC |
366 | * This controller supports PIO0 to PIO4. We honour the BIOS/jumper FIFO |
367 | * setting unless we see an ATAPI device in which case we force it off. | |
669a5db4 JG |
368 | * |
369 | * FIXME: need to implement 2nd channel support. | |
370 | */ | |
371 | ||
372 | static void ht6560b_set_piomode(struct ata_port *ap, struct ata_device *adev) | |
373 | { | |
374 | u8 active, recover; | |
375 | struct ata_timing t; | |
376 | ||
377 | /* Get the timing data in cycles. For now play safe at 50Mhz */ | |
378 | ata_timing_compute(adev, adev->pio_mode, &t, 20000, 1000); | |
379 | ||
380 | active = FIT(t.active, 2, 15); | |
381 | recover = FIT(t.recover, 2, 16); | |
382 | recover &= 0x15; | |
383 | ||
384 | inb(0x3E6); | |
385 | inb(0x3E6); | |
386 | inb(0x3E6); | |
387 | inb(0x3E6); | |
388 | ||
0d5ff566 | 389 | iowrite8(recover << 4 | active, ap->ioaddr.device_addr); |
669a5db4 JG |
390 | |
391 | if (adev->class != ATA_DEV_ATA) { | |
392 | u8 rconf = inb(0x3E6); | |
393 | if (rconf & 0x24) { | |
defc9cd8 | 394 | rconf &= ~0x24; |
669a5db4 JG |
395 | outb(rconf, 0x3E6); |
396 | } | |
397 | } | |
0d5ff566 | 398 | ioread8(ap->ioaddr.status_addr); |
669a5db4 JG |
399 | } |
400 | ||
401 | static struct ata_port_operations ht6560b_port_ops = { | |
029cfd6b | 402 | .inherits = &legacy_base_port_ops, |
669a5db4 | 403 | .set_piomode = ht6560b_set_piomode, |
669a5db4 JG |
404 | }; |
405 | ||
406 | /* | |
407 | * Opti core chipset helpers | |
408 | */ | |
85cd7251 | 409 | |
669a5db4 JG |
410 | /** |
411 | * opti_syscfg - read OPTI chipset configuration | |
412 | * @reg: Configuration register to read | |
413 | * | |
414 | * Returns the value of an OPTI system board configuration register. | |
415 | */ | |
416 | ||
417 | static u8 opti_syscfg(u8 reg) | |
418 | { | |
419 | unsigned long flags; | |
420 | u8 r; | |
85cd7251 | 421 | |
669a5db4 JG |
422 | /* Uniprocessor chipset and must force cycles adjancent */ |
423 | local_irq_save(flags); | |
424 | outb(reg, 0x22); | |
425 | r = inb(0x24); | |
426 | local_irq_restore(flags); | |
427 | return r; | |
428 | } | |
429 | ||
430 | /* | |
431 | * Opti 82C611A | |
432 | * | |
433 | * This controller supports PIO0 to PIO3. | |
434 | */ | |
435 | ||
defc9cd8 AC |
436 | static void opti82c611a_set_piomode(struct ata_port *ap, |
437 | struct ata_device *adev) | |
669a5db4 JG |
438 | { |
439 | u8 active, recover, setup; | |
440 | struct ata_timing t; | |
441 | struct ata_device *pair = ata_dev_pair(adev); | |
442 | int clock; | |
443 | int khz[4] = { 50000, 40000, 33000, 25000 }; | |
444 | u8 rc; | |
445 | ||
446 | /* Enter configuration mode */ | |
0d5ff566 TH |
447 | ioread16(ap->ioaddr.error_addr); |
448 | ioread16(ap->ioaddr.error_addr); | |
449 | iowrite8(3, ap->ioaddr.nsect_addr); | |
669a5db4 JG |
450 | |
451 | /* Read VLB clock strapping */ | |
0d5ff566 | 452 | clock = 1000000000 / khz[ioread8(ap->ioaddr.lbah_addr) & 0x03]; |
669a5db4 JG |
453 | |
454 | /* Get the timing data in cycles */ | |
455 | ata_timing_compute(adev, adev->pio_mode, &t, clock, 1000); | |
456 | ||
457 | /* Setup timing is shared */ | |
458 | if (pair) { | |
459 | struct ata_timing tp; | |
460 | ata_timing_compute(pair, pair->pio_mode, &tp, clock, 1000); | |
461 | ||
462 | ata_timing_merge(&t, &tp, &t, ATA_TIMING_SETUP); | |
463 | } | |
464 | ||
465 | active = FIT(t.active, 2, 17) - 2; | |
466 | recover = FIT(t.recover, 1, 16) - 1; | |
467 | setup = FIT(t.setup, 1, 4) - 1; | |
468 | ||
469 | /* Select the right timing bank for write timing */ | |
0d5ff566 | 470 | rc = ioread8(ap->ioaddr.lbal_addr); |
669a5db4 JG |
471 | rc &= 0x7F; |
472 | rc |= (adev->devno << 7); | |
0d5ff566 | 473 | iowrite8(rc, ap->ioaddr.lbal_addr); |
669a5db4 JG |
474 | |
475 | /* Write the timings */ | |
0d5ff566 | 476 | iowrite8(active << 4 | recover, ap->ioaddr.error_addr); |
669a5db4 JG |
477 | |
478 | /* Select the right bank for read timings, also | |
479 | load the shared timings for address */ | |
0d5ff566 | 480 | rc = ioread8(ap->ioaddr.device_addr); |
669a5db4 JG |
481 | rc &= 0xC0; |
482 | rc |= adev->devno; /* Index select */ | |
483 | rc |= (setup << 4) | 0x04; | |
0d5ff566 | 484 | iowrite8(rc, ap->ioaddr.device_addr); |
669a5db4 JG |
485 | |
486 | /* Load the read timings */ | |
0d5ff566 | 487 | iowrite8(active << 4 | recover, ap->ioaddr.data_addr); |
669a5db4 JG |
488 | |
489 | /* Ensure the timing register mode is right */ | |
0d5ff566 | 490 | rc = ioread8(ap->ioaddr.lbal_addr); |
669a5db4 JG |
491 | rc &= 0x73; |
492 | rc |= 0x84; | |
0d5ff566 | 493 | iowrite8(rc, ap->ioaddr.lbal_addr); |
669a5db4 JG |
494 | |
495 | /* Exit command mode */ | |
0d5ff566 | 496 | iowrite8(0x83, ap->ioaddr.nsect_addr); |
669a5db4 JG |
497 | } |
498 | ||
499 | ||
500 | static struct ata_port_operations opti82c611a_port_ops = { | |
029cfd6b | 501 | .inherits = &legacy_base_port_ops, |
669a5db4 | 502 | .set_piomode = opti82c611a_set_piomode, |
669a5db4 JG |
503 | }; |
504 | ||
505 | /* | |
506 | * Opti 82C465MV | |
507 | * | |
508 | * This controller supports PIO0 to PIO3. Unlike the 611A the MVB | |
509 | * version is dual channel but doesn't have a lot of unique registers. | |
510 | */ | |
511 | ||
512 | static void opti82c46x_set_piomode(struct ata_port *ap, struct ata_device *adev) | |
513 | { | |
514 | u8 active, recover, setup; | |
515 | struct ata_timing t; | |
516 | struct ata_device *pair = ata_dev_pair(adev); | |
517 | int clock; | |
518 | int khz[4] = { 50000, 40000, 33000, 25000 }; | |
519 | u8 rc; | |
520 | u8 sysclk; | |
521 | ||
522 | /* Get the clock */ | |
523 | sysclk = opti_syscfg(0xAC) & 0xC0; /* BIOS set */ | |
524 | ||
525 | /* Enter configuration mode */ | |
0d5ff566 TH |
526 | ioread16(ap->ioaddr.error_addr); |
527 | ioread16(ap->ioaddr.error_addr); | |
528 | iowrite8(3, ap->ioaddr.nsect_addr); | |
669a5db4 JG |
529 | |
530 | /* Read VLB clock strapping */ | |
531 | clock = 1000000000 / khz[sysclk]; | |
532 | ||
533 | /* Get the timing data in cycles */ | |
534 | ata_timing_compute(adev, adev->pio_mode, &t, clock, 1000); | |
535 | ||
536 | /* Setup timing is shared */ | |
537 | if (pair) { | |
538 | struct ata_timing tp; | |
539 | ata_timing_compute(pair, pair->pio_mode, &tp, clock, 1000); | |
540 | ||
541 | ata_timing_merge(&t, &tp, &t, ATA_TIMING_SETUP); | |
542 | } | |
543 | ||
544 | active = FIT(t.active, 2, 17) - 2; | |
545 | recover = FIT(t.recover, 1, 16) - 1; | |
546 | setup = FIT(t.setup, 1, 4) - 1; | |
547 | ||
548 | /* Select the right timing bank for write timing */ | |
0d5ff566 | 549 | rc = ioread8(ap->ioaddr.lbal_addr); |
669a5db4 JG |
550 | rc &= 0x7F; |
551 | rc |= (adev->devno << 7); | |
0d5ff566 | 552 | iowrite8(rc, ap->ioaddr.lbal_addr); |
669a5db4 JG |
553 | |
554 | /* Write the timings */ | |
0d5ff566 | 555 | iowrite8(active << 4 | recover, ap->ioaddr.error_addr); |
669a5db4 JG |
556 | |
557 | /* Select the right bank for read timings, also | |
558 | load the shared timings for address */ | |
0d5ff566 | 559 | rc = ioread8(ap->ioaddr.device_addr); |
669a5db4 JG |
560 | rc &= 0xC0; |
561 | rc |= adev->devno; /* Index select */ | |
562 | rc |= (setup << 4) | 0x04; | |
0d5ff566 | 563 | iowrite8(rc, ap->ioaddr.device_addr); |
669a5db4 JG |
564 | |
565 | /* Load the read timings */ | |
0d5ff566 | 566 | iowrite8(active << 4 | recover, ap->ioaddr.data_addr); |
669a5db4 JG |
567 | |
568 | /* Ensure the timing register mode is right */ | |
0d5ff566 | 569 | rc = ioread8(ap->ioaddr.lbal_addr); |
669a5db4 JG |
570 | rc &= 0x73; |
571 | rc |= 0x84; | |
0d5ff566 | 572 | iowrite8(rc, ap->ioaddr.lbal_addr); |
669a5db4 JG |
573 | |
574 | /* Exit command mode */ | |
0d5ff566 | 575 | iowrite8(0x83, ap->ioaddr.nsect_addr); |
669a5db4 JG |
576 | |
577 | /* We need to know this for quad device on the MVB */ | |
578 | ap->host->private_data = ap; | |
579 | } | |
580 | ||
581 | /** | |
9363c382 | 582 | * opt82c465mv_qc_issue - command issue |
669a5db4 JG |
583 | * @qc: command pending |
584 | * | |
585 | * Called when the libata layer is about to issue a command. We wrap | |
586 | * this interface so that we can load the correct ATA timings. The | |
587 | * MVB has a single set of timing registers and these are shared | |
588 | * across channels. As there are two registers we really ought to | |
589 | * track the last two used values as a sort of register window. For | |
590 | * now we just reload on a channel switch. On the single channel | |
591 | * setup this condition never fires so we do nothing extra. | |
592 | * | |
593 | * FIXME: dual channel needs ->serialize support | |
594 | */ | |
595 | ||
9363c382 | 596 | static unsigned int opti82c46x_qc_issue(struct ata_queued_cmd *qc) |
669a5db4 JG |
597 | { |
598 | struct ata_port *ap = qc->ap; | |
599 | struct ata_device *adev = qc->dev; | |
600 | ||
601 | /* If timings are set and for the wrong channel (2nd test is | |
602 | due to a libata shortcoming and will eventually go I hope) */ | |
603 | if (ap->host->private_data != ap->host | |
604 | && ap->host->private_data != NULL) | |
605 | opti82c46x_set_piomode(ap, adev); | |
606 | ||
9363c382 | 607 | return ata_sff_qc_issue(qc); |
669a5db4 JG |
608 | } |
609 | ||
610 | static struct ata_port_operations opti82c46x_port_ops = { | |
029cfd6b | 611 | .inherits = &legacy_base_port_ops, |
669a5db4 | 612 | .set_piomode = opti82c46x_set_piomode, |
9363c382 | 613 | .qc_issue = opti82c46x_qc_issue, |
669a5db4 JG |
614 | }; |
615 | ||
defc9cd8 AC |
616 | static void qdi6500_set_piomode(struct ata_port *ap, struct ata_device *adev) |
617 | { | |
618 | struct ata_timing t; | |
cb616dd5 | 619 | struct legacy_data *ld_qdi = ap->host->private_data; |
defc9cd8 AC |
620 | int active, recovery; |
621 | u8 timing; | |
622 | ||
623 | /* Get the timing data in cycles */ | |
624 | ata_timing_compute(adev, adev->pio_mode, &t, 30303, 1000); | |
625 | ||
cb616dd5 | 626 | if (ld_qdi->fast) { |
defc9cd8 AC |
627 | active = 8 - FIT(t.active, 1, 8); |
628 | recovery = 18 - FIT(t.recover, 3, 18); | |
629 | } else { | |
630 | active = 9 - FIT(t.active, 2, 9); | |
631 | recovery = 15 - FIT(t.recover, 0, 15); | |
632 | } | |
633 | timing = (recovery << 4) | active | 0x08; | |
634 | ||
cb616dd5 | 635 | ld_qdi->clock[adev->devno] = timing; |
defc9cd8 | 636 | |
cb616dd5 | 637 | outb(timing, ld_qdi->timing); |
defc9cd8 | 638 | } |
669a5db4 JG |
639 | |
640 | /** | |
defc9cd8 AC |
641 | * qdi6580dp_set_piomode - PIO setup for dual channel |
642 | * @ap: Port | |
643 | * @adev: Device | |
669a5db4 JG |
644 | * @irq: interrupt line |
645 | * | |
defc9cd8 | 646 | * In dual channel mode the 6580 has one clock per channel and we have |
9363c382 | 647 | * to software clockswitch in qc_issue. |
669a5db4 JG |
648 | */ |
649 | ||
defc9cd8 | 650 | static void qdi6580dp_set_piomode(struct ata_port *ap, struct ata_device *adev) |
669a5db4 | 651 | { |
defc9cd8 | 652 | struct ata_timing t; |
cb616dd5 | 653 | struct legacy_data *ld_qdi = ap->host->private_data; |
defc9cd8 AC |
654 | int active, recovery; |
655 | u8 timing; | |
669a5db4 | 656 | |
defc9cd8 AC |
657 | /* Get the timing data in cycles */ |
658 | ata_timing_compute(adev, adev->pio_mode, &t, 30303, 1000); | |
659 | ||
cb616dd5 | 660 | if (ld_qdi->fast) { |
defc9cd8 AC |
661 | active = 8 - FIT(t.active, 1, 8); |
662 | recovery = 18 - FIT(t.recover, 3, 18); | |
663 | } else { | |
664 | active = 9 - FIT(t.active, 2, 9); | |
665 | recovery = 15 - FIT(t.recover, 0, 15); | |
666 | } | |
667 | timing = (recovery << 4) | active | 0x08; | |
24dc5f33 | 668 | |
cb616dd5 | 669 | ld_qdi->clock[adev->devno] = timing; |
669a5db4 | 670 | |
cb616dd5 | 671 | outb(timing, ld_qdi->timing + 2 * ap->port_no); |
defc9cd8 AC |
672 | /* Clear the FIFO */ |
673 | if (adev->class != ATA_DEV_ATA) | |
cb616dd5 | 674 | outb(0x5F, ld_qdi->timing + 3); |
defc9cd8 | 675 | } |
0d5ff566 | 676 | |
defc9cd8 AC |
677 | /** |
678 | * qdi6580_set_piomode - PIO setup for single channel | |
679 | * @ap: Port | |
680 | * @adev: Device | |
681 | * | |
682 | * In single channel mode the 6580 has one clock per device and we can | |
683 | * avoid the requirement to clock switch. We also have to load the timing | |
684 | * into the right clock according to whether we are master or slave. | |
685 | */ | |
686 | ||
687 | static void qdi6580_set_piomode(struct ata_port *ap, struct ata_device *adev) | |
688 | { | |
689 | struct ata_timing t; | |
cb616dd5 | 690 | struct legacy_data *ld_qdi = ap->host->private_data; |
defc9cd8 AC |
691 | int active, recovery; |
692 | u8 timing; | |
693 | ||
694 | /* Get the timing data in cycles */ | |
695 | ata_timing_compute(adev, adev->pio_mode, &t, 30303, 1000); | |
696 | ||
cb616dd5 | 697 | if (ld_qdi->fast) { |
defc9cd8 AC |
698 | active = 8 - FIT(t.active, 1, 8); |
699 | recovery = 18 - FIT(t.recover, 3, 18); | |
700 | } else { | |
701 | active = 9 - FIT(t.active, 2, 9); | |
702 | recovery = 15 - FIT(t.recover, 0, 15); | |
669a5db4 | 703 | } |
defc9cd8 | 704 | timing = (recovery << 4) | active | 0x08; |
cb616dd5 HH |
705 | ld_qdi->clock[adev->devno] = timing; |
706 | outb(timing, ld_qdi->timing + 2 * adev->devno); | |
defc9cd8 AC |
707 | /* Clear the FIFO */ |
708 | if (adev->class != ATA_DEV_ATA) | |
cb616dd5 | 709 | outb(0x5F, ld_qdi->timing + 3); |
defc9cd8 AC |
710 | } |
711 | ||
712 | /** | |
9363c382 | 713 | * qdi_qc_issue - command issue |
defc9cd8 AC |
714 | * @qc: command pending |
715 | * | |
716 | * Called when the libata layer is about to issue a command. We wrap | |
717 | * this interface so that we can load the correct ATA timings. | |
718 | */ | |
719 | ||
9363c382 | 720 | static unsigned int qdi_qc_issue(struct ata_queued_cmd *qc) |
defc9cd8 AC |
721 | { |
722 | struct ata_port *ap = qc->ap; | |
723 | struct ata_device *adev = qc->dev; | |
cb616dd5 | 724 | struct legacy_data *ld_qdi = ap->host->private_data; |
defc9cd8 | 725 | |
cb616dd5 | 726 | if (ld_qdi->clock[adev->devno] != ld_qdi->last) { |
defc9cd8 | 727 | if (adev->pio_mode) { |
cb616dd5 HH |
728 | ld_qdi->last = ld_qdi->clock[adev->devno]; |
729 | outb(ld_qdi->clock[adev->devno], ld_qdi->timing + | |
defc9cd8 AC |
730 | 2 * ap->port_no); |
731 | } | |
669a5db4 | 732 | } |
9363c382 | 733 | return ata_sff_qc_issue(qc); |
defc9cd8 | 734 | } |
669a5db4 | 735 | |
b8325487 | 736 | static unsigned int vlb32_data_xfer(struct ata_device *adev, unsigned char *buf, |
defc9cd8 AC |
737 | unsigned int buflen, int rw) |
738 | { | |
739 | struct ata_port *ap = adev->link->ap; | |
740 | int slop = buflen & 3; | |
669a5db4 | 741 | |
defc9cd8 AC |
742 | if (ata_id_has_dword_io(adev->id)) { |
743 | if (rw == WRITE) | |
744 | iowrite32_rep(ap->ioaddr.data_addr, buf, buflen >> 2); | |
745 | else | |
746 | ioread32_rep(ap->ioaddr.data_addr, buf, buflen >> 2); | |
669a5db4 | 747 | |
defc9cd8 AC |
748 | if (unlikely(slop)) { |
749 | u32 pad; | |
750 | if (rw == WRITE) { | |
751 | memcpy(&pad, buf + buflen - slop, slop); | |
752 | pad = le32_to_cpu(pad); | |
753 | iowrite32(pad, ap->ioaddr.data_addr); | |
754 | } else { | |
755 | pad = ioread32(ap->ioaddr.data_addr); | |
756 | pad = cpu_to_le32(pad); | |
757 | memcpy(buf + buflen - slop, &pad, slop); | |
758 | } | |
759 | } | |
760 | return (buflen + 3) & ~3; | |
761 | } else | |
9363c382 | 762 | return ata_sff_data_xfer(adev, buf, buflen, rw); |
defc9cd8 AC |
763 | } |
764 | ||
b8325487 AC |
765 | static int qdi_port(struct platform_device *dev, |
766 | struct legacy_probe *lp, struct legacy_data *ld) | |
767 | { | |
768 | if (devm_request_region(&dev->dev, lp->private, 4, "qdi") == NULL) | |
769 | return -EBUSY; | |
770 | ld->timing = lp->private; | |
771 | return 0; | |
772 | } | |
773 | ||
defc9cd8 | 774 | static struct ata_port_operations qdi6500_port_ops = { |
029cfd6b | 775 | .inherits = &legacy_base_port_ops, |
defc9cd8 | 776 | .set_piomode = qdi6500_set_piomode, |
9363c382 | 777 | .qc_issue = qdi_qc_issue, |
b8325487 | 778 | .data_xfer = vlb32_data_xfer, |
defc9cd8 AC |
779 | }; |
780 | ||
781 | static struct ata_port_operations qdi6580_port_ops = { | |
029cfd6b | 782 | .inherits = &legacy_base_port_ops, |
defc9cd8 | 783 | .set_piomode = qdi6580_set_piomode, |
b8325487 | 784 | .data_xfer = vlb32_data_xfer, |
defc9cd8 AC |
785 | }; |
786 | ||
787 | static struct ata_port_operations qdi6580dp_port_ops = { | |
029cfd6b | 788 | .inherits = &legacy_base_port_ops, |
defc9cd8 | 789 | .set_piomode = qdi6580dp_set_piomode, |
b8325487 | 790 | .data_xfer = vlb32_data_xfer, |
defc9cd8 AC |
791 | }; |
792 | ||
b8325487 AC |
793 | static DEFINE_SPINLOCK(winbond_lock); |
794 | ||
795 | static void winbond_writecfg(unsigned long port, u8 reg, u8 val) | |
796 | { | |
797 | unsigned long flags; | |
798 | spin_lock_irqsave(&winbond_lock, flags); | |
799 | outb(reg, port + 0x01); | |
800 | outb(val, port + 0x02); | |
801 | spin_unlock_irqrestore(&winbond_lock, flags); | |
802 | } | |
803 | ||
804 | static u8 winbond_readcfg(unsigned long port, u8 reg) | |
805 | { | |
806 | u8 val; | |
807 | ||
808 | unsigned long flags; | |
809 | spin_lock_irqsave(&winbond_lock, flags); | |
810 | outb(reg, port + 0x01); | |
811 | val = inb(port + 0x02); | |
812 | spin_unlock_irqrestore(&winbond_lock, flags); | |
813 | ||
814 | return val; | |
815 | } | |
816 | ||
817 | static void winbond_set_piomode(struct ata_port *ap, struct ata_device *adev) | |
818 | { | |
819 | struct ata_timing t; | |
cb616dd5 | 820 | struct legacy_data *ld_winbond = ap->host->private_data; |
b8325487 AC |
821 | int active, recovery; |
822 | u8 reg; | |
823 | int timing = 0x88 + (ap->port_no * 4) + (adev->devno * 2); | |
824 | ||
cb616dd5 | 825 | reg = winbond_readcfg(ld_winbond->timing, 0x81); |
b8325487 AC |
826 | |
827 | /* Get the timing data in cycles */ | |
828 | if (reg & 0x40) /* Fast VLB bus, assume 50MHz */ | |
829 | ata_timing_compute(adev, adev->pio_mode, &t, 20000, 1000); | |
830 | else | |
831 | ata_timing_compute(adev, adev->pio_mode, &t, 30303, 1000); | |
832 | ||
833 | active = (FIT(t.active, 3, 17) - 1) & 0x0F; | |
834 | recovery = (FIT(t.recover, 1, 15) + 1) & 0x0F; | |
835 | timing = (active << 4) | recovery; | |
cb616dd5 | 836 | winbond_writecfg(ld_winbond->timing, timing, reg); |
b8325487 AC |
837 | |
838 | /* Load the setup timing */ | |
839 | ||
840 | reg = 0x35; | |
841 | if (adev->class != ATA_DEV_ATA) | |
842 | reg |= 0x08; /* FIFO off */ | |
843 | if (!ata_pio_need_iordy(adev)) | |
844 | reg |= 0x02; /* IORDY off */ | |
845 | reg |= (FIT(t.setup, 0, 3) << 6); | |
cb616dd5 | 846 | winbond_writecfg(ld_winbond->timing, timing + 1, reg); |
b8325487 AC |
847 | } |
848 | ||
849 | static int winbond_port(struct platform_device *dev, | |
850 | struct legacy_probe *lp, struct legacy_data *ld) | |
851 | { | |
852 | if (devm_request_region(&dev->dev, lp->private, 4, "winbond") == NULL) | |
853 | return -EBUSY; | |
854 | ld->timing = lp->private; | |
855 | return 0; | |
856 | } | |
857 | ||
858 | static struct ata_port_operations winbond_port_ops = { | |
029cfd6b | 859 | .inherits = &legacy_base_port_ops, |
b8325487 | 860 | .set_piomode = winbond_set_piomode, |
b8325487 | 861 | .data_xfer = vlb32_data_xfer, |
b8325487 AC |
862 | }; |
863 | ||
defc9cd8 AC |
864 | static struct legacy_controller controllers[] = { |
865 | {"BIOS", &legacy_port_ops, 0x1F, | |
866 | ATA_FLAG_NO_IORDY, NULL }, | |
867 | {"Snooping", &simple_port_ops, 0x1F, | |
868 | 0 , NULL }, | |
869 | {"PDC20230", &pdc20230_port_ops, 0x7, | |
870 | ATA_FLAG_NO_IORDY, NULL }, | |
871 | {"HT6560A", &ht6560a_port_ops, 0x07, | |
872 | ATA_FLAG_NO_IORDY, NULL }, | |
873 | {"HT6560B", &ht6560b_port_ops, 0x1F, | |
874 | ATA_FLAG_NO_IORDY, NULL }, | |
875 | {"OPTI82C611A", &opti82c611a_port_ops, 0x0F, | |
876 | 0 , NULL }, | |
877 | {"OPTI82C46X", &opti82c46x_port_ops, 0x0F, | |
878 | 0 , NULL }, | |
879 | {"QDI6500", &qdi6500_port_ops, 0x07, | |
b8325487 | 880 | ATA_FLAG_NO_IORDY, qdi_port }, |
defc9cd8 | 881 | {"QDI6580", &qdi6580_port_ops, 0x1F, |
b8325487 | 882 | 0 , qdi_port }, |
defc9cd8 | 883 | {"QDI6580DP", &qdi6580dp_port_ops, 0x1F, |
b8325487 AC |
884 | 0 , qdi_port }, |
885 | {"W83759A", &winbond_port_ops, 0x1F, | |
886 | 0 , winbond_port } | |
defc9cd8 AC |
887 | }; |
888 | ||
889 | /** | |
890 | * probe_chip_type - Discover controller | |
891 | * @probe: Probe entry to check | |
892 | * | |
893 | * Probe an ATA port and identify the type of controller. We don't | |
894 | * check if the controller appears to be driveless at this point. | |
895 | */ | |
896 | ||
b8325487 | 897 | static __init int probe_chip_type(struct legacy_probe *probe) |
defc9cd8 AC |
898 | { |
899 | int mask = 1 << probe->slot; | |
900 | ||
b8325487 AC |
901 | if (winbond && (probe->port == 0x1F0 || probe->port == 0x170)) { |
902 | u8 reg = winbond_readcfg(winbond, 0x81); | |
903 | reg |= 0x80; /* jumpered mode off */ | |
904 | winbond_writecfg(winbond, 0x81, reg); | |
905 | reg = winbond_readcfg(winbond, 0x83); | |
906 | reg |= 0xF0; /* local control */ | |
907 | winbond_writecfg(winbond, 0x83, reg); | |
908 | reg = winbond_readcfg(winbond, 0x85); | |
909 | reg |= 0xF0; /* programmable timing */ | |
910 | winbond_writecfg(winbond, 0x85, reg); | |
911 | ||
912 | reg = winbond_readcfg(winbond, 0x81); | |
913 | ||
914 | if (reg & mask) | |
915 | return W83759A; | |
916 | } | |
defc9cd8 AC |
917 | if (probe->port == 0x1F0) { |
918 | unsigned long flags; | |
919 | local_irq_save(flags); | |
669a5db4 | 920 | /* Probes */ |
669a5db4 | 921 | outb(inb(0x1F2) | 0x80, 0x1F2); |
defc9cd8 | 922 | inb(0x1F5); |
669a5db4 JG |
923 | inb(0x1F2); |
924 | inb(0x3F6); | |
925 | inb(0x3F6); | |
926 | inb(0x1F2); | |
927 | inb(0x1F2); | |
928 | ||
929 | if ((inb(0x1F2) & 0x80) == 0) { | |
930 | /* PDC20230c or 20630 ? */ | |
defc9cd8 AC |
931 | printk(KERN_INFO "PDC20230-C/20630 VLB ATA controller" |
932 | " detected.\n"); | |
669a5db4 JG |
933 | udelay(100); |
934 | inb(0x1F5); | |
defc9cd8 AC |
935 | local_irq_restore(flags); |
936 | return PDC20230; | |
669a5db4 JG |
937 | } else { |
938 | outb(0x55, 0x1F2); | |
939 | inb(0x1F2); | |
940 | inb(0x1F2); | |
defc9cd8 AC |
941 | if (inb(0x1F2) == 0x00) |
942 | printk(KERN_INFO "PDC20230-B VLB ATA " | |
943 | "controller detected.\n"); | |
944 | local_irq_restore(flags); | |
945 | return BIOS; | |
669a5db4 JG |
946 | } |
947 | local_irq_restore(flags); | |
948 | } | |
949 | ||
defc9cd8 AC |
950 | if (ht6560a & mask) |
951 | return HT6560A; | |
952 | if (ht6560b & mask) | |
953 | return HT6560B; | |
954 | if (opti82c611a & mask) | |
955 | return OPTI611A; | |
956 | if (opti82c46x & mask) | |
957 | return OPTI46X; | |
958 | if (autospeed & mask) | |
959 | return SNOOP; | |
960 | return BIOS; | |
961 | } | |
962 | ||
963 | ||
964 | /** | |
965 | * legacy_init_one - attach a legacy interface | |
966 | * @pl: probe record | |
967 | * | |
968 | * Register an ISA bus IDE interface. Such interfaces are PIO and we | |
969 | * assume do not support IRQ sharing. | |
970 | */ | |
971 | ||
972 | static __init int legacy_init_one(struct legacy_probe *probe) | |
973 | { | |
974 | struct legacy_controller *controller = &controllers[probe->type]; | |
975 | int pio_modes = controller->pio_mask; | |
976 | unsigned long io = probe->port; | |
977 | u32 mask = (1 << probe->slot); | |
978 | struct ata_port_operations *ops = controller->ops; | |
979 | struct legacy_data *ld = &legacy_data[probe->slot]; | |
980 | struct ata_host *host = NULL; | |
981 | struct ata_port *ap; | |
982 | struct platform_device *pdev; | |
983 | struct ata_device *dev; | |
984 | void __iomem *io_addr, *ctrl_addr; | |
985 | u32 iordy = (iordy_mask & mask) ? 0: ATA_FLAG_NO_IORDY; | |
986 | int ret; | |
987 | ||
988 | iordy |= controller->flags; | |
989 | ||
990 | pdev = platform_device_register_simple(DRV_NAME, probe->slot, NULL, 0); | |
991 | if (IS_ERR(pdev)) | |
992 | return PTR_ERR(pdev); | |
669a5db4 | 993 | |
defc9cd8 AC |
994 | ret = -EBUSY; |
995 | if (devm_request_region(&pdev->dev, io, 8, "pata_legacy") == NULL || | |
996 | devm_request_region(&pdev->dev, io + 0x0206, 1, | |
997 | "pata_legacy") == NULL) | |
998 | goto fail; | |
f834e49f | 999 | |
5d728824 | 1000 | ret = -ENOMEM; |
defc9cd8 AC |
1001 | io_addr = devm_ioport_map(&pdev->dev, io, 8); |
1002 | ctrl_addr = devm_ioport_map(&pdev->dev, io + 0x0206, 1); | |
1003 | if (!io_addr || !ctrl_addr) | |
1004 | goto fail; | |
1005 | if (controller->setup) | |
b8325487 | 1006 | if (controller->setup(pdev, probe, ld) < 0) |
defc9cd8 | 1007 | goto fail; |
5d728824 TH |
1008 | host = ata_host_alloc(&pdev->dev, 1); |
1009 | if (!host) | |
1010 | goto fail; | |
1011 | ap = host->ports[0]; | |
1012 | ||
1013 | ap->ops = ops; | |
1014 | ap->pio_mask = pio_modes; | |
1015 | ap->flags |= ATA_FLAG_SLAVE_POSS | iordy; | |
1016 | ap->ioaddr.cmd_addr = io_addr; | |
1017 | ap->ioaddr.altstatus_addr = ctrl_addr; | |
1018 | ap->ioaddr.ctl_addr = ctrl_addr; | |
9363c382 | 1019 | ata_sff_std_ports(&ap->ioaddr); |
b8325487 | 1020 | ap->host->private_data = ld; |
5d728824 | 1021 | |
defc9cd8 | 1022 | ata_port_desc(ap, "cmd 0x%lx ctl 0x%lx", io, io + 0x0206); |
cbcdd875 | 1023 | |
9363c382 TH |
1024 | ret = ata_host_activate(host, probe->irq, ata_sff_interrupt, 0, |
1025 | &legacy_sht); | |
5d728824 | 1026 | if (ret) |
669a5db4 | 1027 | goto fail; |
669a5db4 | 1028 | ld->platform_dev = pdev; |
669a5db4 | 1029 | |
defc9cd8 AC |
1030 | /* Nothing found means we drop the port as its probably not there */ |
1031 | ||
1032 | ret = -ENODEV; | |
1033 | ata_link_for_each_dev(dev, &ap->link) { | |
1034 | if (!ata_dev_absent(dev)) { | |
1035 | legacy_host[probe->slot] = host; | |
1036 | ld->platform_dev = pdev; | |
1037 | return 0; | |
1038 | } | |
1039 | } | |
669a5db4 JG |
1040 | fail: |
1041 | platform_device_unregister(pdev); | |
669a5db4 JG |
1042 | return ret; |
1043 | } | |
1044 | ||
1045 | /** | |
1046 | * legacy_check_special_cases - ATA special cases | |
1047 | * @p: PCI device to check | |
1048 | * @master: set this if we find an ATA master | |
1049 | * @master: set this if we find an ATA secondary | |
1050 | * | |
defc9cd8 AC |
1051 | * A small number of vendors implemented early PCI ATA interfaces |
1052 | * on bridge logic without the ATA interface being PCI visible. | |
1053 | * Where we have a matching PCI driver we must skip the relevant | |
1054 | * device here. If we don't know about it then the legacy driver | |
1055 | * is the right driver anyway. | |
669a5db4 JG |
1056 | */ |
1057 | ||
b8325487 | 1058 | static void __init legacy_check_special_cases(struct pci_dev *p, int *primary, |
defc9cd8 | 1059 | int *secondary) |
669a5db4 JG |
1060 | { |
1061 | /* Cyrix CS5510 pre SFF MWDMA ATA on the bridge */ | |
1062 | if (p->vendor == 0x1078 && p->device == 0x0000) { | |
1063 | *primary = *secondary = 1; | |
1064 | return; | |
1065 | } | |
1066 | /* Cyrix CS5520 pre SFF MWDMA ATA on the bridge */ | |
1067 | if (p->vendor == 0x1078 && p->device == 0x0002) { | |
1068 | *primary = *secondary = 1; | |
1069 | return; | |
1070 | } | |
1071 | /* Intel MPIIX - PIO ATA on non PCI side of bridge */ | |
1072 | if (p->vendor == 0x8086 && p->device == 0x1234) { | |
1073 | u16 r; | |
1074 | pci_read_config_word(p, 0x6C, &r); | |
defc9cd8 AC |
1075 | if (r & 0x8000) { |
1076 | /* ATA port enabled */ | |
669a5db4 JG |
1077 | if (r & 0x4000) |
1078 | *secondary = 1; | |
1079 | else | |
1080 | *primary = 1; | |
1081 | } | |
1082 | return; | |
1083 | } | |
1084 | } | |
1085 | ||
defc9cd8 AC |
1086 | static __init void probe_opti_vlb(void) |
1087 | { | |
1088 | /* If an OPTI 82C46X is present find out where the channels are */ | |
1089 | static const char *optis[4] = { | |
1090 | "3/463MV", "5MV", | |
1091 | "5MVA", "5MVB" | |
1092 | }; | |
1093 | u8 chans = 1; | |
1094 | u8 ctrl = (opti_syscfg(0x30) & 0xC0) >> 6; | |
1095 | ||
1096 | opti82c46x = 3; /* Assume master and slave first */ | |
1097 | printk(KERN_INFO DRV_NAME ": Opti 82C46%s chipset support.\n", | |
1098 | optis[ctrl]); | |
1099 | if (ctrl == 3) | |
1100 | chans = (opti_syscfg(0x3F) & 0x20) ? 2 : 1; | |
1101 | ctrl = opti_syscfg(0xAC); | |
1102 | /* Check enabled and this port is the 465MV port. On the | |
1103 | MVB we may have two channels */ | |
1104 | if (ctrl & 8) { | |
1105 | if (chans == 2) { | |
1106 | legacy_probe_add(0x1F0, 14, OPTI46X, 0); | |
1107 | legacy_probe_add(0x170, 15, OPTI46X, 0); | |
1108 | } | |
1109 | if (ctrl & 4) | |
1110 | legacy_probe_add(0x170, 15, OPTI46X, 0); | |
1111 | else | |
1112 | legacy_probe_add(0x1F0, 14, OPTI46X, 0); | |
1113 | } else | |
1114 | legacy_probe_add(0x1F0, 14, OPTI46X, 0); | |
1115 | } | |
1116 | ||
1117 | static __init void qdi65_identify_port(u8 r, u8 res, unsigned long port) | |
1118 | { | |
1119 | static const unsigned long ide_port[2] = { 0x170, 0x1F0 }; | |
1120 | /* Check card type */ | |
1121 | if ((r & 0xF0) == 0xC0) { | |
1122 | /* QD6500: single channel */ | |
b8325487 | 1123 | if (r & 8) |
defc9cd8 | 1124 | /* Disabled ? */ |
defc9cd8 | 1125 | return; |
defc9cd8 AC |
1126 | legacy_probe_add(ide_port[r & 0x01], 14 + (r & 0x01), |
1127 | QDI6500, port); | |
1128 | } | |
1129 | if (((r & 0xF0) == 0xA0) || (r & 0xF0) == 0x50) { | |
1130 | /* QD6580: dual channel */ | |
1131 | if (!request_region(port + 2 , 2, "pata_qdi")) { | |
1132 | release_region(port, 2); | |
1133 | return; | |
1134 | } | |
1135 | res = inb(port + 3); | |
1136 | /* Single channel mode ? */ | |
1137 | if (res & 1) | |
1138 | legacy_probe_add(ide_port[r & 0x01], 14 + (r & 0x01), | |
1139 | QDI6580, port); | |
1140 | else { /* Dual channel mode */ | |
1141 | legacy_probe_add(0x1F0, 14, QDI6580DP, port); | |
1142 | /* port + 0x02, r & 0x04 */ | |
1143 | legacy_probe_add(0x170, 15, QDI6580DP, port + 2); | |
1144 | } | |
b8325487 | 1145 | release_region(port + 2, 2); |
defc9cd8 AC |
1146 | } |
1147 | } | |
1148 | ||
1149 | static __init void probe_qdi_vlb(void) | |
1150 | { | |
1151 | unsigned long flags; | |
1152 | static const unsigned long qd_port[2] = { 0x30, 0xB0 }; | |
1153 | int i; | |
1154 | ||
1155 | /* | |
1156 | * Check each possible QD65xx base address | |
1157 | */ | |
1158 | ||
1159 | for (i = 0; i < 2; i++) { | |
1160 | unsigned long port = qd_port[i]; | |
1161 | u8 r, res; | |
1162 | ||
1163 | ||
1164 | if (request_region(port, 2, "pata_qdi")) { | |
1165 | /* Check for a card */ | |
1166 | local_irq_save(flags); | |
1167 | /* I have no h/w that needs this delay but it | |
1168 | is present in the historic code */ | |
1169 | r = inb(port); | |
1170 | udelay(1); | |
1171 | outb(0x19, port); | |
1172 | udelay(1); | |
1173 | res = inb(port); | |
1174 | udelay(1); | |
1175 | outb(r, port); | |
1176 | udelay(1); | |
1177 | local_irq_restore(flags); | |
1178 | ||
1179 | /* Fail */ | |
1180 | if (res == 0x19) { | |
1181 | release_region(port, 2); | |
1182 | continue; | |
1183 | } | |
1184 | /* Passes the presence test */ | |
1185 | r = inb(port + 1); | |
1186 | udelay(1); | |
1187 | /* Check port agrees with port set */ | |
b8325487 AC |
1188 | if ((r & 2) >> 1 == i) |
1189 | qdi65_identify_port(r, res, port); | |
1190 | release_region(port, 2); | |
defc9cd8 AC |
1191 | } |
1192 | } | |
1193 | } | |
669a5db4 JG |
1194 | |
1195 | /** | |
1196 | * legacy_init - attach legacy interfaces | |
1197 | * | |
1198 | * Attach legacy IDE interfaces by scanning the usual IRQ/port suspects. | |
1199 | * Right now we do not scan the ide0 and ide1 address but should do so | |
1200 | * for non PCI systems or systems with no PCI IDE legacy mode devices. | |
1201 | * If you fix that note there are special cases to consider like VLB | |
1202 | * drivers and CS5510/20. | |
1203 | */ | |
1204 | ||
1205 | static __init int legacy_init(void) | |
1206 | { | |
1207 | int i; | |
1208 | int ct = 0; | |
1209 | int primary = 0; | |
1210 | int secondary = 0; | |
defc9cd8 AC |
1211 | int pci_present = 0; |
1212 | struct legacy_probe *pl = &probe_list[0]; | |
1213 | int slot = 0; | |
669a5db4 JG |
1214 | |
1215 | struct pci_dev *p = NULL; | |
1216 | ||
1217 | for_each_pci_dev(p) { | |
1218 | int r; | |
defc9cd8 AC |
1219 | /* Check for any overlap of the system ATA mappings. Native |
1220 | mode controllers stuck on these addresses or some devices | |
1221 | in 'raid' mode won't be found by the storage class test */ | |
669a5db4 JG |
1222 | for (r = 0; r < 6; r++) { |
1223 | if (pci_resource_start(p, r) == 0x1f0) | |
1224 | primary = 1; | |
1225 | if (pci_resource_start(p, r) == 0x170) | |
1226 | secondary = 1; | |
1227 | } | |
1228 | /* Check for special cases */ | |
1229 | legacy_check_special_cases(p, &primary, &secondary); | |
1230 | ||
defc9cd8 AC |
1231 | /* If PCI bus is present then don't probe for tertiary |
1232 | legacy ports */ | |
1233 | pci_present = 1; | |
669a5db4 JG |
1234 | } |
1235 | ||
b8325487 AC |
1236 | if (winbond == 1) |
1237 | winbond = 0x130; /* Default port, alt is 1B0 */ | |
1238 | ||
defc9cd8 AC |
1239 | if (primary == 0 || all) |
1240 | legacy_probe_add(0x1F0, 14, UNKNOWN, 0); | |
1241 | if (secondary == 0 || all) | |
1242 | legacy_probe_add(0x170, 15, UNKNOWN, 0); | |
1243 | ||
1244 | if (probe_all || !pci_present) { | |
1245 | /* ISA/VLB extra ports */ | |
1246 | legacy_probe_add(0x1E8, 11, UNKNOWN, 0); | |
1247 | legacy_probe_add(0x168, 10, UNKNOWN, 0); | |
1248 | legacy_probe_add(0x1E0, 8, UNKNOWN, 0); | |
1249 | legacy_probe_add(0x160, 12, UNKNOWN, 0); | |
669a5db4 JG |
1250 | } |
1251 | ||
defc9cd8 AC |
1252 | if (opti82c46x) |
1253 | probe_opti_vlb(); | |
1254 | if (qdi) | |
1255 | probe_qdi_vlb(); | |
1256 | ||
defc9cd8 AC |
1257 | for (i = 0; i < NR_HOST; i++, pl++) { |
1258 | if (pl->port == 0) | |
669a5db4 | 1259 | continue; |
defc9cd8 AC |
1260 | if (pl->type == UNKNOWN) |
1261 | pl->type = probe_chip_type(pl); | |
1262 | pl->slot = slot++; | |
1263 | if (legacy_init_one(pl) == 0) | |
669a5db4 JG |
1264 | ct++; |
1265 | } | |
1266 | if (ct != 0) | |
1267 | return 0; | |
1268 | return -ENODEV; | |
1269 | } | |
1270 | ||
1271 | static __exit void legacy_exit(void) | |
1272 | { | |
1273 | int i; | |
1274 | ||
1275 | for (i = 0; i < nr_legacy_host; i++) { | |
1276 | struct legacy_data *ld = &legacy_data[i]; | |
24dc5f33 | 1277 | ata_host_detach(legacy_host[i]); |
669a5db4 | 1278 | platform_device_unregister(ld->platform_dev); |
669a5db4 JG |
1279 | } |
1280 | } | |
1281 | ||
1282 | MODULE_AUTHOR("Alan Cox"); | |
1283 | MODULE_DESCRIPTION("low-level driver for legacy ATA"); | |
1284 | MODULE_LICENSE("GPL"); | |
1285 | MODULE_VERSION(DRV_VERSION); | |
1286 | ||
1287 | module_param(probe_all, int, 0); | |
1288 | module_param(autospeed, int, 0); | |
1289 | module_param(ht6560a, int, 0); | |
1290 | module_param(ht6560b, int, 0); | |
1291 | module_param(opti82c611a, int, 0); | |
1292 | module_param(opti82c46x, int, 0); | |
defc9cd8 | 1293 | module_param(qdi, int, 0); |
669a5db4 | 1294 | module_param(pio_mask, int, 0); |
f834e49f | 1295 | module_param(iordy_mask, int, 0); |
669a5db4 JG |
1296 | |
1297 | module_init(legacy_init); | |
1298 | module_exit(legacy_exit); |