[deliverable/linux.git] / drivers / ata / pata_pdc202xx_old.c

/*
 * pata_pdc202xx_old.c 	- Promise PDC202xx PATA for new ATA layer
 *			  (C) 2005 Red Hat Inc
 *			  Alan Cox <alan@redhat.com>
 *
 * Based in part on linux/drivers/ide/pci/pdc202xx_old.c
 *
 * First cut with LBA48/ATAPI
 *
 * TODO:
 *	Channel interlock/reset on both required ?
 */

#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/pci.h>
#include <linux/init.h>
#include <linux/blkdev.h>
#include <linux/delay.h>
#include <scsi/scsi_host.h>
#include <linux/libata.h>

#define DRV_NAME "pata_pdc202xx_old"
#define DRV_VERSION "0.3.0"

/**
 *	pdc2024x_pre_reset		-	probe begin
 *	@ap: ATA port
 *
 *	Set up cable type and use generic probe init
 */

static int pdc2024x_pre_reset(struct ata_port *ap)
{
	ap->cbl = ATA_CBL_PATA40;
	return ata_std_prereset(ap);
}


static void pdc2024x_error_handler(struct ata_port *ap)
{
	ata_bmdma_drive_eh(ap, pdc2024x_pre_reset, ata_std_softreset, NULL, ata_std_postreset);
}


static int pdc2026x_pre_reset(struct ata_port *ap)
{
	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	u16 cis;

	pci_read_config_word(pdev, 0x50, &cis);
	if (cis & (1 << (10 + ap->port_no)))
		ap->cbl = ATA_CBL_PATA80;
	else
		ap->cbl = ATA_CBL_PATA40;

	return ata_std_prereset(ap);
}

static void pdc2026x_error_handler(struct ata_port *ap)
{
	ata_bmdma_drive_eh(ap, pdc2026x_pre_reset, ata_std_softreset, NULL, ata_std_postreset);
}

/**
 *	pdc202xx_configure_piomode	-	set chip PIO timing
 *	@ap: ATA interface
 *	@adev: ATA device
 *	@pio: PIO mode
 *
 *	Called to do the PIO mode setup. Our timing registers are shared
 *	so a configure_dmamode call will undo any work we do here and vice
 *	versa
 */

static void pdc202xx_configure_piomode(struct ata_port *ap, struct ata_device *adev, int pio)
{
	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	int port = 0x60 + 4 * ap->port_no + 2 * adev->devno;
	static u16 pio_timing[5] = {
		0x0913, 0x050C , 0x0308, 0x0206, 0x0104
	};
	u8 r_ap, r_bp;

	pci_read_config_byte(pdev, port, &r_ap);
	pci_read_config_byte(pdev, port + 1, &r_bp);
	r_ap &= ~0x3F;	/* Preserve ERRDY_EN, SYNC_IN */
	r_bp &= ~0x07;
	r_ap |= (pio_timing[pio] >> 8);
	r_bp |= (pio_timing[pio] & 0xFF);

	if (ata_pio_need_iordy(adev))
		r_ap |= 0x20;	/* IORDY enable */
	if (adev->class == ATA_DEV_ATA)
		r_ap |= 0x10;	/* FIFO enable */
	pci_write_config_byte(pdev, port, r_ap);
	pci_write_config_byte(pdev, port + 1, r_bp);
}

/**
 *	pdc202xx_set_piomode	-	set initial PIO mode data
 *	@ap: ATA interface
 *	@adev: ATA device
 *
 *	Called to do the PIO mode setup. Our timing registers are shared
 *	but we want to set the PIO timing by default.
 */

static void pdc202xx_set_piomode(struct ata_port *ap, struct ata_device *adev)
{
	pdc202xx_configure_piomode(ap, adev, adev->pio_mode - XFER_PIO_0);
}

/**
 *	pdc202xx_configure_dmamode	-	set DMA mode in chip
 *	@ap: ATA interface
 *	@adev: ATA device
 *
 *	Load DMA cycle times into the chip ready for a DMA transfer
 *	to occur.
 */

static void pdc202xx_set_dmamode(struct ata_port *ap, struct ata_device *adev)
{
	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	int port = 0x60 + 4 * ap->port_no + 2 * adev->devno;
	static u8 udma_timing[6][2] = {
		{ 0x60, 0x03 },	/* 33 Mhz Clock */
		{ 0x40, 0x02 },
		{ 0x20, 0x01 },
		{ 0x40, 0x02 },	/* 66 Mhz Clock */
		{ 0x20, 0x01 },
		{ 0x20, 0x01 }
	};
	u8 r_bp, r_cp;

	pci_read_config_byte(pdev, port + 1, &r_bp);
	pci_read_config_byte(pdev, port + 2, &r_cp);

	r_bp &= ~0xF0;
	r_cp &= ~0x0F;

	if (adev->dma_mode >= XFER_UDMA_0) {
		int speed = adev->dma_mode - XFER_UDMA_0;
		r_bp |= udma_timing[speed][0];
		r_cp |= udma_timing[speed][1];

	} else {
		int speed = adev->dma_mode - XFER_MW_DMA_0;
		r_bp |= 0x60;
		r_cp |= (5 - speed);
	}
	pci_write_config_byte(pdev, port + 1, r_bp);
	pci_write_config_byte(pdev, port + 2, r_cp);

}

/**
 *	pdc2026x_bmdma_start		-	DMA engine begin
 *	@qc: ATA command
 *
 *	In UDMA3 or higher we have to clock switch for the duration of the
 *	DMA transfer sequence.
 */

static void pdc2026x_bmdma_start(struct ata_queued_cmd *qc)
{
	struct ata_port *ap = qc->ap;
	struct ata_device *adev = qc->dev;
	struct ata_taskfile *tf = &qc->tf;
	int sel66 = ap->port_no ? 0x08: 0x02;

	void __iomem *master = ap->host->ports[0]->ioaddr.bmdma_addr;
	void __iomem *clock = master + 0x11;
	void __iomem *atapi_reg = master + 0x20 + (4 * ap->port_no);

	u32 len;

	/* Check we keep host level locking here */
	if (adev->dma_mode >= XFER_UDMA_2)
		iowrite8(ioread8(clock) | sel66, clock);
	else
		iowrite8(ioread8(clock) & ~sel66, clock);

	/* The DMA clocks may have been trashed by a reset. FIXME: make conditional
	   and move to qc_issue ? */
	pdc202xx_set_dmamode(ap, qc->dev);

	/* Cases the state machine will not complete correctly without help */
	if ((tf->flags & ATA_TFLAG_LBA48) ||  tf->protocol == ATA_PROT_ATAPI_DMA)
	{
		len = qc->nbytes;

		if (tf->flags & ATA_TFLAG_WRITE)
			len |= 0x06000000;
		else
			len |= 0x05000000;

		iowrite32(len, atapi_reg);
	}

	/* Activate DMA */
	ata_bmdma_start(qc);
}

/**
 *	pdc2026x_bmdma_end		-	DMA engine stop
 *	@qc: ATA command
 *
 *	After a DMA completes we need to put the clock back to 33MHz for
 *	PIO timings.
 */

static void pdc2026x_bmdma_stop(struct ata_queued_cmd *qc)
{
	struct ata_port *ap = qc->ap;
	struct ata_device *adev = qc->dev;
	struct ata_taskfile *tf = &qc->tf;

	int sel66 = ap->port_no ? 0x08: 0x02;
	/* The clock bits are in the same register for both channels */
	void __iomem *master = ap->host->ports[0]->ioaddr.bmdma_addr;
	void __iomem *clock = master + 0x11;
	void __iomem *atapi_reg = master + 0x20 + (4 * ap->port_no);

	/* Cases the state machine will not complete correctly */
	if (tf->protocol == ATA_PROT_ATAPI_DMA || ( tf->flags & ATA_TFLAG_LBA48)) {
		iowrite32(0, atapi_reg);
		iowrite8(ioread8(clock) & ~sel66, clock);
	}
	/* Check we keep host level locking here */
	/* Flip back to 33Mhz for PIO */
	if (adev->dma_mode >= XFER_UDMA_2)
		iowrite8(ioread8(clock) & ~sel66, clock);

	ata_bmdma_stop(qc);
}

/**
 *	pdc2026x_dev_config	-	device setup hook
 *	@ap: ATA port
 *	@adev: newly found device
 *
 *	Perform chip specific early setup. We need to lock the transfer
 *	sizes to 8bit to avoid making the state engine on the 2026x cards
 *	barf.
 */

static void pdc2026x_dev_config(struct ata_port *ap, struct ata_device *adev)
{
	adev->max_sectors = 256;
}

static struct scsi_host_template pdc202xx_sht = {
	.module			= THIS_MODULE,
	.name			= DRV_NAME,
	.ioctl			= ata_scsi_ioctl,
	.queuecommand		= ata_scsi_queuecmd,
	.can_queue		= ATA_DEF_QUEUE,
	.this_id		= ATA_SHT_THIS_ID,
	.sg_tablesize		= LIBATA_MAX_PRD,
	.cmd_per_lun		= ATA_SHT_CMD_PER_LUN,
	.emulated		= ATA_SHT_EMULATED,
	.use_clustering		= ATA_SHT_USE_CLUSTERING,
	.proc_name		= DRV_NAME,
	.dma_boundary		= ATA_DMA_BOUNDARY,
	.slave_configure	= ata_scsi_slave_config,
	.slave_destroy		= ata_scsi_slave_destroy,
	.bios_param		= ata_std_bios_param,
	.resume			= ata_scsi_device_resume,
	.suspend		= ata_scsi_device_suspend,
};

static struct ata_port_operations pdc2024x_port_ops = {
	.port_disable	= ata_port_disable,
	.set_piomode	= pdc202xx_set_piomode,
	.set_dmamode	= pdc202xx_set_dmamode,
	.mode_filter	= ata_pci_default_filter,
	.tf_load	= ata_tf_load,
	.tf_read	= ata_tf_read,
	.check_status 	= ata_check_status,
	.exec_command	= ata_exec_command,
	.dev_select 	= ata_std_dev_select,

	.freeze		= ata_bmdma_freeze,
	.thaw		= ata_bmdma_thaw,
	.error_handler	= pdc2024x_error_handler,
	.post_internal_cmd = ata_bmdma_post_internal_cmd,

	.bmdma_setup 	= ata_bmdma_setup,
	.bmdma_start 	= ata_bmdma_start,
	.bmdma_stop	= ata_bmdma_stop,
	.bmdma_status 	= ata_bmdma_status,

	.qc_prep 	= ata_qc_prep,
	.qc_issue	= ata_qc_issue_prot,
	.data_xfer	= ata_data_xfer,

	.irq_handler	= ata_interrupt,
	.irq_clear	= ata_bmdma_irq_clear,
	.irq_on		= ata_irq_on,
	.irq_ack	= ata_irq_ack,

	.port_start	= ata_port_start,
};

static struct ata_port_operations pdc2026x_port_ops = {
	.port_disable	= ata_port_disable,
	.set_piomode	= pdc202xx_set_piomode,
	.set_dmamode	= pdc202xx_set_dmamode,
	.mode_filter	= ata_pci_default_filter,
	.tf_load	= ata_tf_load,
	.tf_read	= ata_tf_read,
	.check_status 	= ata_check_status,
	.exec_command	= ata_exec_command,
	.dev_select 	= ata_std_dev_select,
	.dev_config	= pdc2026x_dev_config,

	.freeze		= ata_bmdma_freeze,
	.thaw		= ata_bmdma_thaw,
	.error_handler	= pdc2026x_error_handler,
	.post_internal_cmd = ata_bmdma_post_internal_cmd,

	.bmdma_setup 	= ata_bmdma_setup,
	.bmdma_start 	= pdc2026x_bmdma_start,
	.bmdma_stop	= pdc2026x_bmdma_stop,
	.bmdma_status 	= ata_bmdma_status,

	.qc_prep 	= ata_qc_prep,
	.qc_issue	= ata_qc_issue_prot,
	.data_xfer	= ata_data_xfer,

	.irq_handler	= ata_interrupt,
	.irq_clear	= ata_bmdma_irq_clear,
	.irq_on		= ata_irq_on,
	.irq_ack	= ata_irq_ack,

	.port_start	= ata_port_start,
};

static int pdc202xx_init_one(struct pci_dev *dev, const struct pci_device_id *id)
{
	static struct ata_port_info info[3] = {
		{
			.sht = &pdc202xx_sht,
			.flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
			.pio_mask = 0x1f,
			.mwdma_mask = 0x07,
			.udma_mask = ATA_UDMA2,
			.port_ops = &pdc2024x_port_ops
		},
		{
			.sht = &pdc202xx_sht,
			.flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
			.pio_mask = 0x1f,
			.mwdma_mask = 0x07,
			.udma_mask = ATA_UDMA4,
			.port_ops = &pdc2026x_port_ops
		},
		{
			.sht = &pdc202xx_sht,
			.flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
			.pio_mask = 0x1f,
			.mwdma_mask = 0x07,
			.udma_mask = ATA_UDMA5,
			.port_ops = &pdc2026x_port_ops
		}

	};
	static struct ata_port_info *port_info[2];

	port_info[0] = port_info[1] = &info[id->driver_data];

	if (dev->device == PCI_DEVICE_ID_PROMISE_20265) {
		struct pci_dev *bridge = dev->bus->self;
		/* Don't grab anything behind a Promise I2O RAID */
		if (bridge && bridge->vendor == PCI_VENDOR_ID_INTEL) {
			if( bridge->device == PCI_DEVICE_ID_INTEL_I960)
				return -ENODEV;
			if( bridge->device == PCI_DEVICE_ID_INTEL_I960RM)
				return -ENODEV;
		}
	}
	return ata_pci_init_one(dev, port_info, 2);
}

static const struct pci_device_id pdc202xx[] = {
	{ PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20246), 0 },
	{ PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20262), 1 },
	{ PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20263), 1 },
	{ PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20265), 2 },
	{ PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20267), 2 },

	{ },
};

static struct pci_driver pdc202xx_pci_driver = {
	.name 		= DRV_NAME,
	.id_table	= pdc202xx,
	.probe 		= pdc202xx_init_one,
	.remove		= ata_pci_remove_one,
	.suspend	= ata_pci_device_suspend,
	.resume		= ata_pci_device_resume,
};

static int __init pdc202xx_init(void)
{
	return pci_register_driver(&pdc202xx_pci_driver);
}

static void __exit pdc202xx_exit(void)
{
	pci_unregister_driver(&pdc202xx_pci_driver);
}

MODULE_AUTHOR("Alan Cox");
MODULE_DESCRIPTION("low-level driver for Promise 2024x and 20262-20267");
MODULE_LICENSE("GPL");
MODULE_DEVICE_TABLE(pci, pdc202xx);
MODULE_VERSION(DRV_VERSION);

module_init(pdc202xx_init);
module_exit(pdc202xx_exit);
Commit	Line	Data
669a5db4 JG	1	/*
	2	* pata_pdc202xx_old.c - Promise PDC202xx PATA for new ATA layer
	3	* (C) 2005 Red Hat Inc
	4	* Alan Cox <alan@redhat.com>
	5	*
	6	* Based in part on linux/drivers/ide/pci/pdc202xx_old.c
	7	*
	8	* First cut with LBA48/ATAPI
	9	*
	10	* TODO:
	11	* Channel interlock/reset on both required ?
	12	*/
85cd7251	13
669a5db4 JG	14	#include <linux/kernel.h>
	15	#include <linux/module.h>
	16	#include <linux/pci.h>
	17	#include <linux/init.h>
	18	#include <linux/blkdev.h>
	19	#include <linux/delay.h>
	20	#include <scsi/scsi_host.h>
	21	#include <linux/libata.h>
	22
	23	#define DRV_NAME "pata_pdc202xx_old"
cb48cab7	24	#define DRV_VERSION "0.3.0"
669a5db4 JG	25
	26	/**
	27	* pdc2024x_pre_reset - probe begin
	28	* @ap: ATA port
	29	*
	30	* Set up cable type and use generic probe init
	31	*/
85cd7251	32
669a5db4 JG	33	static int pdc2024x_pre_reset(struct ata_port *ap)
	34	{
	35	ap->cbl = ATA_CBL_PATA40;
	36	return ata_std_prereset(ap);
	37	}
	38
	39
	40	static void pdc2024x_error_handler(struct ata_port *ap)
	41	{
	42	ata_bmdma_drive_eh(ap, pdc2024x_pre_reset, ata_std_softreset, NULL, ata_std_postreset);
	43	}
	44
	45
	46	static int pdc2026x_pre_reset(struct ata_port *ap)
	47	{
	48	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	49	u16 cis;
85cd7251	50
669a5db4 JG	51	pci_read_config_word(pdev, 0x50, &cis);
	52	if (cis & (1 << (10 + ap->port_no)))
	53	ap->cbl = ATA_CBL_PATA80;
	54	else
	55	ap->cbl = ATA_CBL_PATA40;
	56
	57	return ata_std_prereset(ap);
	58	}
	59
	60	static void pdc2026x_error_handler(struct ata_port *ap)
	61	{
	62	ata_bmdma_drive_eh(ap, pdc2026x_pre_reset, ata_std_softreset, NULL, ata_std_postreset);
	63	}
	64
	65	/**
ada406c8	66	* pdc202xx_configure_piomode - set chip PIO timing
669a5db4 JG	67	* @ap: ATA interface
	68	* @adev: ATA device
	69	* @pio: PIO mode
	70	*
	71	* Called to do the PIO mode setup. Our timing registers are shared
	72	* so a configure_dmamode call will undo any work we do here and vice
	73	* versa
	74	*/
85cd7251	75
ada406c8	76	static void pdc202xx_configure_piomode(struct ata_port ap, struct ata_device adev, int pio)
669a5db4 JG	77	{
	78	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	79	int port = 0x60 + 4 * ap->port_no + 2 * adev->devno;
	80	static u16 pio_timing[5] = {
	81	0x0913, 0x050C , 0x0308, 0x0206, 0x0104
	82	};
	83	u8 r_ap, r_bp;
	84
	85	pci_read_config_byte(pdev, port, &r_ap);
	86	pci_read_config_byte(pdev, port + 1, &r_bp);
	87	r_ap &= ~0x3F; /* Preserve ERRDY_EN, SYNC_IN */
	88	r_bp &= ~0x07;
	89	r_ap \|= (pio_timing[pio] >> 8);
	90	r_bp \|= (pio_timing[pio] & 0xFF);
85cd7251	91
669a5db4 JG	92	if (ata_pio_need_iordy(adev))
	93	r_ap \|= 0x20; /* IORDY enable */
	94	if (adev->class == ATA_DEV_ATA)
	95	r_ap \|= 0x10; /* FIFO enable */
	96	pci_write_config_byte(pdev, port, r_ap);
	97	pci_write_config_byte(pdev, port + 1, r_bp);
	98	}
	99
	100	/**
ada406c8	101	* pdc202xx_set_piomode - set initial PIO mode data
669a5db4 JG	102	* @ap: ATA interface
	103	* @adev: ATA device
	104	*
	105	* Called to do the PIO mode setup. Our timing registers are shared
	106	* but we want to set the PIO timing by default.
	107	*/
85cd7251	108
ada406c8	109	static void pdc202xx_set_piomode(struct ata_port ap, struct ata_device adev)
669a5db4	110	{
ada406c8	111	pdc202xx_configure_piomode(ap, adev, adev->pio_mode - XFER_PIO_0);
669a5db4 JG	112	}
	113
	114	/**
ada406c8	115	* pdc202xx_configure_dmamode - set DMA mode in chip
669a5db4 JG	116	* @ap: ATA interface
	117	* @adev: ATA device
	118	*
	119	* Load DMA cycle times into the chip ready for a DMA transfer
	120	* to occur.
	121	*/
85cd7251	122
ada406c8	123	static void pdc202xx_set_dmamode(struct ata_port ap, struct ata_device adev)
669a5db4 JG	124	{
	125	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	126	int port = 0x60 + 4 * ap->port_no + 2 * adev->devno;
	127	static u8 udma_timing[6][2] = {
	128	{ 0x60, 0x03 }, /* 33 Mhz Clock */
	129	{ 0x40, 0x02 },
	130	{ 0x20, 0x01 },
	131	{ 0x40, 0x02 }, /* 66 Mhz Clock */
	132	{ 0x20, 0x01 },
85cd7251	133	{ 0x20, 0x01 }
669a5db4 JG	134	};
669a5db4 JG	135	u8 r_bp, r_cp;
85cd7251	136
669a5db4 JG	137	pci_read_config_byte(pdev, port + 1, &r_bp);
669a5db4 JG	138	pci_read_config_byte(pdev, port + 2, &r_cp);
85cd7251	139
669a5db4 JG	140	r_bp &= ~0xF0;
669a5db4 JG	141	r_cp &= ~0x0F;
85cd7251	142
669a5db4 JG	143	if (adev->dma_mode >= XFER_UDMA_0) {
	144	int speed = adev->dma_mode - XFER_UDMA_0;
	145	r_bp \|= udma_timing[speed][0];
	146	r_cp \|= udma_timing[speed][1];
85cd7251	147
669a5db4 JG	148	} else {
	149	int speed = adev->dma_mode - XFER_MW_DMA_0;
	150	r_bp \|= 0x60;
	151	r_cp \|= (5 - speed);
	152	}
	153	pci_write_config_byte(pdev, port + 1, r_bp);
	154	pci_write_config_byte(pdev, port + 2, r_cp);
85cd7251	155
669a5db4 JG	156	}
	157
	158	/**
	159	* pdc2026x_bmdma_start - DMA engine begin
	160	* @qc: ATA command
	161	*
	162	* In UDMA3 or higher we have to clock switch for the duration of the
	163	* DMA transfer sequence.
	164	*/
85cd7251	165
669a5db4 JG	166	static void pdc2026x_bmdma_start(struct ata_queued_cmd *qc)
	167	{
	168	struct ata_port *ap = qc->ap;
	169	struct ata_device *adev = qc->dev;
	170	struct ata_taskfile *tf = &qc->tf;
	171	int sel66 = ap->port_no ? 0x08: 0x02;
	172
0d5ff566 TH	173	void __iomem *master = ap->host->ports[0]->ioaddr.bmdma_addr;
	174	void __iomem *clock = master + 0x11;
	175	void __iomem atapi_reg = master + 0x20 + (4 ap->port_no);
85cd7251	176
669a5db4	177	u32 len;
85cd7251	178
669a5db4 JG	179	/* Check we keep host level locking here */
669a5db4 JG	180	if (adev->dma_mode >= XFER_UDMA_2)
0d5ff566	181	iowrite8(ioread8(clock) \| sel66, clock);
669a5db4	182	else
0d5ff566	183	iowrite8(ioread8(clock) & ~sel66, clock);
669a5db4	184
85cd7251	185	/* The DMA clocks may have been trashed by a reset. FIXME: make conditional
669a5db4	186	and move to qc_issue ? */
ada406c8	187	pdc202xx_set_dmamode(ap, qc->dev);
669a5db4 JG	188
	189	/* Cases the state machine will not complete correctly without help */
	190	if ((tf->flags & ATA_TFLAG_LBA48) \|\| tf->protocol == ATA_PROT_ATAPI_DMA)
	191	{
726f0785	192	len = qc->nbytes;
85cd7251	193
669a5db4 JG	194	if (tf->flags & ATA_TFLAG_WRITE)
	195	len \|= 0x06000000;
	196	else
	197	len \|= 0x05000000;
85cd7251	198
0d5ff566	199	iowrite32(len, atapi_reg);
669a5db4	200	}
85cd7251 JG	201
85cd7251 JG	202	/* Activate DMA */
669a5db4 JG	203	ata_bmdma_start(qc);
	204	}
	205
	206	/**
	207	* pdc2026x_bmdma_end - DMA engine stop
	208	* @qc: ATA command
	209	*
	210	* After a DMA completes we need to put the clock back to 33MHz for
	211	* PIO timings.
	212	*/
85cd7251	213
669a5db4 JG	214	static void pdc2026x_bmdma_stop(struct ata_queued_cmd *qc)
	215	{
	216	struct ata_port *ap = qc->ap;
	217	struct ata_device *adev = qc->dev;
	218	struct ata_taskfile *tf = &qc->tf;
85cd7251	219
669a5db4 JG	220	int sel66 = ap->port_no ? 0x08: 0x02;
669a5db4 JG	221	/* The clock bits are in the same register for both channels */
0d5ff566 TH	222	void __iomem *master = ap->host->ports[0]->ioaddr.bmdma_addr;
	223	void __iomem *clock = master + 0x11;
	224	void __iomem atapi_reg = master + 0x20 + (4 ap->port_no);
85cd7251	225
669a5db4 JG	226	/* Cases the state machine will not complete correctly */
669a5db4 JG	227	if (tf->protocol == ATA_PROT_ATAPI_DMA \|\| ( tf->flags & ATA_TFLAG_LBA48)) {
0d5ff566 TH	228	iowrite32(0, atapi_reg);
0d5ff566 TH	229	iowrite8(ioread8(clock) & ~sel66, clock);
669a5db4 JG	230	}
	231	/* Check we keep host level locking here */
	232	/* Flip back to 33Mhz for PIO */
	233	if (adev->dma_mode >= XFER_UDMA_2)
0d5ff566	234	iowrite8(ioread8(clock) & ~sel66, clock);
669a5db4 JG	235
	236	ata_bmdma_stop(qc);
	237	}
	238
	239	/**
	240	* pdc2026x_dev_config - device setup hook
	241	* @ap: ATA port
	242	* @adev: newly found device
	243	*
	244	* Perform chip specific early setup. We need to lock the transfer
	245	* sizes to 8bit to avoid making the state engine on the 2026x cards
	246	* barf.
	247	*/
85cd7251	248
669a5db4 JG	249	static void pdc2026x_dev_config(struct ata_port ap, struct ata_device adev)
	250	{
	251	adev->max_sectors = 256;
	252	}
	253
ada406c8	254	static struct scsi_host_template pdc202xx_sht = {
669a5db4 JG	255	.module = THIS_MODULE,
	256	.name = DRV_NAME,
	257	.ioctl = ata_scsi_ioctl,
	258	.queuecommand = ata_scsi_queuecmd,
	259	.can_queue = ATA_DEF_QUEUE,
	260	.this_id = ATA_SHT_THIS_ID,
	261	.sg_tablesize = LIBATA_MAX_PRD,
669a5db4 JG	262	.cmd_per_lun = ATA_SHT_CMD_PER_LUN,
	263	.emulated = ATA_SHT_EMULATED,
	264	.use_clustering = ATA_SHT_USE_CLUSTERING,
	265	.proc_name = DRV_NAME,
	266	.dma_boundary = ATA_DMA_BOUNDARY,
	267	.slave_configure = ata_scsi_slave_config,
afdfe899	268	.slave_destroy = ata_scsi_slave_destroy,
669a5db4	269	.bios_param = ata_std_bios_param,
62d64ae0 A	270	.resume = ata_scsi_device_resume,
62d64ae0 A	271	.suspend = ata_scsi_device_suspend,
669a5db4 JG	272	};
	273
	274	static struct ata_port_operations pdc2024x_port_ops = {
	275	.port_disable = ata_port_disable,
ada406c8 AC	276	.set_piomode = pdc202xx_set_piomode,
ada406c8 AC	277	.set_dmamode = pdc202xx_set_dmamode,
669a5db4 JG	278	.mode_filter = ata_pci_default_filter,
	279	.tf_load = ata_tf_load,
	280	.tf_read = ata_tf_read,
	281	.check_status = ata_check_status,
	282	.exec_command = ata_exec_command,
	283	.dev_select = ata_std_dev_select,
	284
	285	.freeze = ata_bmdma_freeze,
	286	.thaw = ata_bmdma_thaw,
	287	.error_handler = pdc2024x_error_handler,
	288	.post_internal_cmd = ata_bmdma_post_internal_cmd,
	289
	290	.bmdma_setup = ata_bmdma_setup,
	291	.bmdma_start = ata_bmdma_start,
	292	.bmdma_stop = ata_bmdma_stop,
	293	.bmdma_status = ata_bmdma_status,
	294
	295	.qc_prep = ata_qc_prep,
	296	.qc_issue = ata_qc_issue_prot,
0d5ff566	297	.data_xfer = ata_data_xfer,
669a5db4 JG	298
	299	.irq_handler = ata_interrupt,
	300	.irq_clear = ata_bmdma_irq_clear,
246ce3b6 AI	301	.irq_on = ata_irq_on,
246ce3b6 AI	302	.irq_ack = ata_irq_ack,
85cd7251	303
669a5db4	304	.port_start = ata_port_start,
85cd7251	305	};
669a5db4 JG	306
	307	static struct ata_port_operations pdc2026x_port_ops = {
	308	.port_disable = ata_port_disable,
ada406c8 AC	309	.set_piomode = pdc202xx_set_piomode,
ada406c8 AC	310	.set_dmamode = pdc202xx_set_dmamode,
669a5db4 JG	311	.mode_filter = ata_pci_default_filter,
	312	.tf_load = ata_tf_load,
	313	.tf_read = ata_tf_read,
	314	.check_status = ata_check_status,
	315	.exec_command = ata_exec_command,
	316	.dev_select = ata_std_dev_select,
	317	.dev_config = pdc2026x_dev_config,
	318
	319	.freeze = ata_bmdma_freeze,
	320	.thaw = ata_bmdma_thaw,
	321	.error_handler = pdc2026x_error_handler,
	322	.post_internal_cmd = ata_bmdma_post_internal_cmd,
	323
	324	.bmdma_setup = ata_bmdma_setup,
	325	.bmdma_start = pdc2026x_bmdma_start,
	326	.bmdma_stop = pdc2026x_bmdma_stop,
	327	.bmdma_status = ata_bmdma_status,
	328
	329	.qc_prep = ata_qc_prep,
	330	.qc_issue = ata_qc_issue_prot,
0d5ff566	331	.data_xfer = ata_data_xfer,
669a5db4 JG	332
	333	.irq_handler = ata_interrupt,
	334	.irq_clear = ata_bmdma_irq_clear,
246ce3b6 AI	335	.irq_on = ata_irq_on,
246ce3b6 AI	336	.irq_ack = ata_irq_ack,
85cd7251	337
669a5db4	338	.port_start = ata_port_start,
85cd7251	339	};
669a5db4	340
ada406c8	341	static int pdc202xx_init_one(struct pci_dev dev, const struct pci_device_id id)
669a5db4 JG	342	{
	343	static struct ata_port_info info[3] = {
	344	{
ada406c8	345	.sht = &pdc202xx_sht,
669a5db4 JG	346	.flags = ATA_FLAG_SLAVE_POSS \| ATA_FLAG_SRST,
	347	.pio_mask = 0x1f,
	348	.mwdma_mask = 0x07,
	349	.udma_mask = ATA_UDMA2,
	350	.port_ops = &pdc2024x_port_ops
85cd7251	351	},
669a5db4	352	{
ada406c8	353	.sht = &pdc202xx_sht,
669a5db4 JG	354	.flags = ATA_FLAG_SLAVE_POSS \| ATA_FLAG_SRST,
	355	.pio_mask = 0x1f,
	356	.mwdma_mask = 0x07,
	357	.udma_mask = ATA_UDMA4,
	358	.port_ops = &pdc2026x_port_ops
	359	},
	360	{
ada406c8	361	.sht = &pdc202xx_sht,
669a5db4 JG	362	.flags = ATA_FLAG_SLAVE_POSS \| ATA_FLAG_SRST,
	363	.pio_mask = 0x1f,
	364	.mwdma_mask = 0x07,
	365	.udma_mask = ATA_UDMA5,
	366	.port_ops = &pdc2026x_port_ops
	367	}
85cd7251	368
669a5db4 JG	369	};
	370	static struct ata_port_info *port_info[2];
	371
	372	port_info[0] = port_info[1] = &info[id->driver_data];
85cd7251	373
669a5db4 JG	374	if (dev->device == PCI_DEVICE_ID_PROMISE_20265) {
	375	struct pci_dev *bridge = dev->bus->self;
	376	/* Don't grab anything behind a Promise I2O RAID */
	377	if (bridge && bridge->vendor == PCI_VENDOR_ID_INTEL) {
	378	if( bridge->device == PCI_DEVICE_ID_INTEL_I960)
	379	return -ENODEV;
	380	if( bridge->device == PCI_DEVICE_ID_INTEL_I960RM)
	381	return -ENODEV;
	382	}
	383	}
	384	return ata_pci_init_one(dev, port_info, 2);
	385	}
	386
ada406c8	387	static const struct pci_device_id pdc202xx[] = {
2d2744fc JG	388	{ PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20246), 0 },
	389	{ PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20262), 1 },
	390	{ PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20263), 1 },
	391	{ PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20265), 2 },
	392	{ PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20267), 2 },
	393
	394	{ },
669a5db4 JG	395	};
669a5db4 JG	396
ada406c8	397	static struct pci_driver pdc202xx_pci_driver = {
2d2744fc	398	.name = DRV_NAME,
ada406c8 AC	399	.id_table = pdc202xx,
ada406c8 AC	400	.probe = pdc202xx_init_one,
62d64ae0 A	401	.remove = ata_pci_remove_one,
	402	.suspend = ata_pci_device_suspend,
	403	.resume = ata_pci_device_resume,
669a5db4 JG	404	};
669a5db4 JG	405
ada406c8	406	static int __init pdc202xx_init(void)
669a5db4	407	{
ada406c8	408	return pci_register_driver(&pdc202xx_pci_driver);
669a5db4 JG	409	}
669a5db4 JG	410
ada406c8	411	static void __exit pdc202xx_exit(void)
669a5db4	412	{
ada406c8	413	pci_unregister_driver(&pdc202xx_pci_driver);
669a5db4 JG	414	}
669a5db4 JG	415
669a5db4 JG	416	MODULE_AUTHOR("Alan Cox");
	417	MODULE_DESCRIPTION("low-level driver for Promise 2024x and 20262-20267");
	418	MODULE_LICENSE("GPL");
ada406c8	419	MODULE_DEVICE_TABLE(pci, pdc202xx);
669a5db4 JG	420	MODULE_VERSION(DRV_VERSION);
669a5db4 JG	421
ada406c8 AC	422	module_init(pdc202xx_init);
ada406c8 AC	423	module_exit(pdc202xx_exit);