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[libata] sata_mv: add TODO list
[deliverable/linux.git] / drivers / ata / pata_scc.c
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a619f981
AI		 1/*
2 * Support for IDE interfaces on Celleb platform
3 *
4 * (C) Copyright 2006 TOSHIBA CORPORATION
5 *
6 * This code is based on drivers/ata/ata_piix.c:
7 * Copyright 2003-2005 Red Hat Inc
8 * Copyright 2003-2005 Jeff Garzik
9 * Copyright (C) 1998-1999 Andrzej Krzysztofowicz, Author and Maintainer
10 * Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org>
11 * Copyright (C) 2003 Red Hat Inc <alan@redhat.com>
12 *
13 * and drivers/ata/ahci.c:
14 * Copyright 2004-2005 Red Hat, Inc.
15 *
16 * and drivers/ata/libata-core.c:
17 * Copyright 2003-2004 Red Hat, Inc. All rights reserved.
18 * Copyright 2003-2004 Jeff Garzik
19 *
20 * This program is free software; you can redistribute it and/or modify
21 * it under the terms of the GNU General Public License as published by
22 * the Free Software Foundation; either version 2 of the License, or
23 * (at your option) any later version.
24 *
25 * This program is distributed in the hope that it will be useful,
26 * but WITHOUT ANY WARRANTY; without even the implied warranty of
27 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
28 * GNU General Public License for more details.
29 *
30 * You should have received a copy of the GNU General Public License along
31 * with this program; if not, write to the Free Software Foundation, Inc.,
32 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
33 */
34
35#include <linux/kernel.h>
36#include <linux/module.h>
37#include <linux/pci.h>
38#include <linux/init.h>
39#include <linux/blkdev.h>
40#include <linux/delay.h>
41#include <linux/device.h>
42#include <scsi/scsi_host.h>
43#include <linux/libata.h>
44
45#define DRV_NAME "pata_scc"
8bc3fc47 46#define DRV_VERSION "0.2"
a619f981
AI		 47
48#define PCI_DEVICE_ID_TOSHIBA_SCC_ATA 0x01b4
49
50/* PCI BARs */
51#define SCC_CTRL_BAR 0
52#define SCC_BMID_BAR 1
53
54/* offset of CTRL registers */
55#define SCC_CTL_PIOSHT 0x000
56#define SCC_CTL_PIOCT 0x004
57#define SCC_CTL_MDMACT 0x008
58#define SCC_CTL_MCRCST 0x00C
59#define SCC_CTL_SDMACT 0x010
60#define SCC_CTL_SCRCST 0x014
61#define SCC_CTL_UDENVT 0x018
62#define SCC_CTL_TDVHSEL 0x020
63#define SCC_CTL_MODEREG 0x024
64#define SCC_CTL_ECMODE 0xF00
65#define SCC_CTL_MAEA0 0xF50
66#define SCC_CTL_MAEC0 0xF54
67#define SCC_CTL_CCKCTRL 0xFF0
68
69/* offset of BMID registers */
70#define SCC_DMA_CMD 0x000
71#define SCC_DMA_STATUS 0x004
72#define SCC_DMA_TABLE_OFS 0x008
73#define SCC_DMA_INTMASK 0x010
74#define SCC_DMA_INTST 0x014
75#define SCC_DMA_PTERADD 0x018
76#define SCC_REG_CMD_ADDR 0x020
77#define SCC_REG_DATA 0x000
78#define SCC_REG_ERR 0x004
79#define SCC_REG_FEATURE 0x004
80#define SCC_REG_NSECT 0x008
81#define SCC_REG_LBAL 0x00C
82#define SCC_REG_LBAM 0x010
83#define SCC_REG_LBAH 0x014
84#define SCC_REG_DEVICE 0x018
85#define SCC_REG_STATUS 0x01C
86#define SCC_REG_CMD 0x01C
87#define SCC_REG_ALTSTATUS 0x020
88
89/* register value */
90#define TDVHSEL_MASTER 0x00000001
91#define TDVHSEL_SLAVE 0x00000004
92
93#define MODE_JCUSFEN 0x00000080
94
95#define ECMODE_VALUE 0x01
96
97#define CCKCTRL_ATARESET 0x00040000
98#define CCKCTRL_BUFCNT 0x00020000
99#define CCKCTRL_CRST 0x00010000
100#define CCKCTRL_OCLKEN 0x00000100
101#define CCKCTRL_ATACLKOEN 0x00000002
102#define CCKCTRL_LCLKEN 0x00000001
103
104#define QCHCD_IOS_SS 0x00000001
105
106#define QCHSD_STPDIAG 0x00020000
107
108#define INTMASK_MSK 0xD1000012
109#define INTSTS_SERROR 0x80000000
110#define INTSTS_PRERR 0x40000000
111#define INTSTS_RERR 0x10000000
112#define INTSTS_ICERR 0x01000000
113#define INTSTS_BMSINT 0x00000010
114#define INTSTS_BMHE 0x00000008
115#define INTSTS_IOIRQS 0x00000004
116#define INTSTS_INTRQ 0x00000002
117#define INTSTS_ACTEINT 0x00000001
118
119
120/* PIO transfer mode table */
121/* JCHST */
122static const unsigned long JCHSTtbl[2][7] = {
123 {0x0E, 0x05, 0x02, 0x03, 0x02, 0x00, 0x00}, /* 100MHz */
124 {0x13, 0x07, 0x04, 0x04, 0x03, 0x00, 0x00} /* 133MHz */
125};
126
127/* JCHHT */
128static const unsigned long JCHHTtbl[2][7] = {
129 {0x0E, 0x02, 0x02, 0x02, 0x02, 0x00, 0x00}, /* 100MHz */
130 {0x13, 0x03, 0x03, 0x03, 0x03, 0x00, 0x00} /* 133MHz */
131};
132
133/* JCHCT */
134static const unsigned long JCHCTtbl[2][7] = {
135 {0x1D, 0x1D, 0x1C, 0x0B, 0x06, 0x00, 0x00}, /* 100MHz */
136 {0x27, 0x26, 0x26, 0x0E, 0x09, 0x00, 0x00} /* 133MHz */
137};
138
139/* DMA transfer mode table */
140/* JCHDCTM/JCHDCTS */
141static const unsigned long JCHDCTxtbl[2][7] = {
142 {0x0A, 0x06, 0x04, 0x03, 0x01, 0x00, 0x00}, /* 100MHz */
143 {0x0E, 0x09, 0x06, 0x04, 0x02, 0x01, 0x00} /* 133MHz */
144};
145
146/* JCSTWTM/JCSTWTS */
147static const unsigned long JCSTWTxtbl[2][7] = {
148 {0x06, 0x04, 0x03, 0x02, 0x02, 0x02, 0x00}, /* 100MHz */
149 {0x09, 0x06, 0x04, 0x02, 0x02, 0x02, 0x02} /* 133MHz */
150};
151
152/* JCTSS */
153static const unsigned long JCTSStbl[2][7] = {
154 {0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x00}, /* 100MHz */
155 {0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05} /* 133MHz */
156};
157
158/* JCENVT */
159static const unsigned long JCENVTtbl[2][7] = {
160 {0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x00}, /* 100MHz */
161 {0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02} /* 133MHz */
162};
163
164/* JCACTSELS/JCACTSELM */
165static const unsigned long JCACTSELtbl[2][7] = {
166 {0x00, 0x00, 0x00, 0x00, 0x01, 0x01, 0x00}, /* 100MHz */
167 {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01} /* 133MHz */
168};
169
170static const struct pci_device_id scc_pci_tbl[] = {
171 {PCI_VENDOR_ID_TOSHIBA_2, PCI_DEVICE_ID_TOSHIBA_SCC_ATA,
172 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
173 { } /* terminate list */
174};
175
176/**
177 * scc_set_piomode - Initialize host controller PATA PIO timings
178 * @ap: Port whose timings we are configuring
179 * @adev: um
180 *
181 * Set PIO mode for device.
182 *
183 * LOCKING:
184 * None (inherited from caller).
185 */
186
187static void scc_set_piomode (struct ata_port *ap, struct ata_device *adev)
188{
189 unsigned int pio = adev->pio_mode - XFER_PIO_0;
190 void __iomem *ctrl_base = ap->host->iomap[SCC_CTRL_BAR];
191 void __iomem *cckctrl_port = ctrl_base + SCC_CTL_CCKCTRL;
192 void __iomem *piosht_port = ctrl_base + SCC_CTL_PIOSHT;
193 void __iomem *pioct_port = ctrl_base + SCC_CTL_PIOCT;
194 unsigned long reg;
195 int offset;
196
197 reg = in_be32(cckctrl_port);
198 if (reg & CCKCTRL_ATACLKOEN)
199 offset = 1; /* 133MHz */
200 else
201 offset = 0; /* 100MHz */
202
203 reg = JCHSTtbl[offset][pio] << 16 | JCHHTtbl[offset][pio];
204 out_be32(piosht_port, reg);
205 reg = JCHCTtbl[offset][pio];
206 out_be32(pioct_port, reg);
207}
208
209/**
210 * scc_set_dmamode - Initialize host controller PATA DMA timings
211 * @ap: Port whose timings we are configuring
212 * @adev: um
213 * @udma: udma mode, 0 - 6
214 *
215 * Set UDMA mode for device.
216 *
217 * LOCKING:
218 * None (inherited from caller).
219 */
220
221static void scc_set_dmamode (struct ata_port *ap, struct ata_device *adev)
222{
223 unsigned int udma = adev->dma_mode;
224 unsigned int is_slave = (adev->devno != 0);
225 u8 speed = udma;
226 void __iomem *ctrl_base = ap->host->iomap[SCC_CTRL_BAR];
227 void __iomem *cckctrl_port = ctrl_base + SCC_CTL_CCKCTRL;
228 void __iomem *mdmact_port = ctrl_base + SCC_CTL_MDMACT;
229 void __iomem *mcrcst_port = ctrl_base + SCC_CTL_MCRCST;
230 void __iomem *sdmact_port = ctrl_base + SCC_CTL_SDMACT;
231 void __iomem *scrcst_port = ctrl_base + SCC_CTL_SCRCST;
232 void __iomem *udenvt_port = ctrl_base + SCC_CTL_UDENVT;
233 void __iomem *tdvhsel_port = ctrl_base + SCC_CTL_TDVHSEL;
234 int offset, idx;
235
a84471fe 236 if (in_be32(cckctrl_port) & CCKCTRL_ATACLKOEN)
a619f981
AI		 237 offset = 1; /* 133MHz */
238 else
239 offset = 0; /* 100MHz */
240
241 if (speed >= XFER_UDMA_0)
242 idx = speed - XFER_UDMA_0;
243 else
244 return;
245
246 if (is_slave) {
247 out_be32(sdmact_port, JCHDCTxtbl[offset][idx]);
248 out_be32(scrcst_port, JCSTWTxtbl[offset][idx]);
249 out_be32(tdvhsel_port,
250 (in_be32(tdvhsel_port) & ~TDVHSEL_SLAVE) | (JCACTSELtbl[offset][idx] << 2));
251 } else {
252 out_be32(mdmact_port, JCHDCTxtbl[offset][idx]);
253 out_be32(mcrcst_port, JCSTWTxtbl[offset][idx]);
254 out_be32(tdvhsel_port,
255 (in_be32(tdvhsel_port) & ~TDVHSEL_MASTER) | JCACTSELtbl[offset][idx]);
256 }
257 out_be32(udenvt_port,
258 JCTSStbl[offset][idx] << 16 | JCENVTtbl[offset][idx]);
259}
260
261/**
262 * scc_tf_load - send taskfile registers to host controller
263 * @ap: Port to which output is sent
264 * @tf: ATA taskfile register set
265 *
266 * Note: Original code is ata_tf_load().
267 */
268
269static void scc_tf_load (struct ata_port *ap, const struct ata_taskfile *tf)
270{
271 struct ata_ioports *ioaddr = &ap->ioaddr;
272 unsigned int is_addr = tf->flags & ATA_TFLAG_ISADDR;
273
274 if (tf->ctl != ap->last_ctl) {
275 out_be32(ioaddr->ctl_addr, tf->ctl);
276 ap->last_ctl = tf->ctl;
277 ata_wait_idle(ap);
278 }
279
280 if (is_addr && (tf->flags & ATA_TFLAG_LBA48)) {
281 out_be32(ioaddr->feature_addr, tf->hob_feature);
282 out_be32(ioaddr->nsect_addr, tf->hob_nsect);
283 out_be32(ioaddr->lbal_addr, tf->hob_lbal);
284 out_be32(ioaddr->lbam_addr, tf->hob_lbam);
285 out_be32(ioaddr->lbah_addr, tf->hob_lbah);
286 VPRINTK("hob: feat 0x%X nsect 0x%X, lba 0x%X 0x%X 0x%X\n",
287 tf->hob_feature,
288 tf->hob_nsect,
289 tf->hob_lbal,
290 tf->hob_lbam,
291 tf->hob_lbah);
292 }
293
294 if (is_addr) {
295 out_be32(ioaddr->feature_addr, tf->feature);
296 out_be32(ioaddr->nsect_addr, tf->nsect);
297 out_be32(ioaddr->lbal_addr, tf->lbal);
298 out_be32(ioaddr->lbam_addr, tf->lbam);
299 out_be32(ioaddr->lbah_addr, tf->lbah);
300 VPRINTK("feat 0x%X nsect 0x%X lba 0x%X 0x%X 0x%X\n",
301 tf->feature,
302 tf->nsect,
303 tf->lbal,
304 tf->lbam,
305 tf->lbah);
306 }
307
308 if (tf->flags & ATA_TFLAG_DEVICE) {
309 out_be32(ioaddr->device_addr, tf->device);
310 VPRINTK("device 0x%X\n", tf->device);
311 }
312
313 ata_wait_idle(ap);
314}
315
316/**
317 * scc_check_status - Read device status reg & clear interrupt
318 * @ap: port where the device is
319 *
320 * Note: Original code is ata_check_status().
321 */
322
323static u8 scc_check_status (struct ata_port *ap)
324{
325 return in_be32(ap->ioaddr.status_addr);
326}
327
328/**
329 * scc_tf_read - input device's ATA taskfile shadow registers
330 * @ap: Port from which input is read
331 * @tf: ATA taskfile register set for storing input
332 *
333 * Note: Original code is ata_tf_read().
334 */
335
336static void scc_tf_read (struct ata_port *ap, struct ata_taskfile *tf)
337{
338 struct ata_ioports *ioaddr = &ap->ioaddr;
339
340 tf->command = scc_check_status(ap);
341 tf->feature = in_be32(ioaddr->error_addr);
342 tf->nsect = in_be32(ioaddr->nsect_addr);
343 tf->lbal = in_be32(ioaddr->lbal_addr);
344 tf->lbam = in_be32(ioaddr->lbam_addr);
345 tf->lbah = in_be32(ioaddr->lbah_addr);
346 tf->device = in_be32(ioaddr->device_addr);
347
348 if (tf->flags & ATA_TFLAG_LBA48) {
349 out_be32(ioaddr->ctl_addr, tf->ctl | ATA_HOB);
350 tf->hob_feature = in_be32(ioaddr->error_addr);
351 tf->hob_nsect = in_be32(ioaddr->nsect_addr);
352 tf->hob_lbal = in_be32(ioaddr->lbal_addr);
353 tf->hob_lbam = in_be32(ioaddr->lbam_addr);
354 tf->hob_lbah = in_be32(ioaddr->lbah_addr);
355 }
356}
357
358/**
359 * scc_exec_command - issue ATA command to host controller
360 * @ap: port to which command is being issued
361 * @tf: ATA taskfile register set
362 *
363 * Note: Original code is ata_exec_command().
364 */
365
366static void scc_exec_command (struct ata_port *ap,
367 const struct ata_taskfile *tf)
368{
878d4fed 369 DPRINTK("ata%u: cmd 0x%X\n", ap->print_id, tf->command);
a619f981
AI		 370
371 out_be32(ap->ioaddr.command_addr, tf->command);
372 ata_pause(ap);
373}
374
375/**
376 * scc_check_altstatus - Read device alternate status reg
377 * @ap: port where the device is
378 */
379
380static u8 scc_check_altstatus (struct ata_port *ap)
381{
382 return in_be32(ap->ioaddr.altstatus_addr);
383}
384
385/**
386 * scc_std_dev_select - Select device 0/1 on ATA bus
387 * @ap: ATA channel to manipulate
388 * @device: ATA device (numbered from zero) to select
389 *
390 * Note: Original code is ata_std_dev_select().
391 */
392
393static void scc_std_dev_select (struct ata_port *ap, unsigned int device)
394{
395 u8 tmp;
396
397 if (device == 0)
398 tmp = ATA_DEVICE_OBS;
399 else
400 tmp = ATA_DEVICE_OBS | ATA_DEV1;
401
402 out_be32(ap->ioaddr.device_addr, tmp);
403 ata_pause(ap);
404}
405
406/**
407 * scc_bmdma_setup - Set up PCI IDE BMDMA transaction
408 * @qc: Info associated with this ATA transaction.
409 *
410 * Note: Original code is ata_bmdma_setup().
411 */
412
413static void scc_bmdma_setup (struct ata_queued_cmd *qc)
414{
415 struct ata_port *ap = qc->ap;
416 unsigned int rw = (qc->tf.flags & ATA_TFLAG_WRITE);
417 u8 dmactl;
418 void __iomem *mmio = ap->ioaddr.bmdma_addr;
419
420 /* load PRD table addr */
421 out_be32(mmio + SCC_DMA_TABLE_OFS, ap->prd_dma);
422
423 /* specify data direction, triple-check start bit is clear */
424 dmactl = in_be32(mmio + SCC_DMA_CMD);
425 dmactl &= ~(ATA_DMA_WR | ATA_DMA_START);
426 if (!rw)
427 dmactl |= ATA_DMA_WR;
428 out_be32(mmio + SCC_DMA_CMD, dmactl);
429
430 /* issue r/w command */
431 ap->ops->exec_command(ap, &qc->tf);
432}
433
434/**
435 * scc_bmdma_start - Start a PCI IDE BMDMA transaction
436 * @qc: Info associated with this ATA transaction.
437 *
438 * Note: Original code is ata_bmdma_start().
439 */
440
441static void scc_bmdma_start (struct ata_queued_cmd *qc)
442{
443 struct ata_port *ap = qc->ap;
444 u8 dmactl;
445 void __iomem *mmio = ap->ioaddr.bmdma_addr;
446
447 /* start host DMA transaction */
448 dmactl = in_be32(mmio + SCC_DMA_CMD);
449 out_be32(mmio + SCC_DMA_CMD, dmactl | ATA_DMA_START);
450}
451
452/**
453 * scc_devchk - PATA device presence detection
454 * @ap: ATA channel to examine
455 * @device: Device to examine (starting at zero)
456 *
457 * Note: Original code is ata_devchk().
458 */
459
460static unsigned int scc_devchk (struct ata_port *ap,
461 unsigned int device)
462{
463 struct ata_ioports *ioaddr = &ap->ioaddr;
464 u8 nsect, lbal;
465
466 ap->ops->dev_select(ap, device);
467
468 out_be32(ioaddr->nsect_addr, 0x55);
469 out_be32(ioaddr->lbal_addr, 0xaa);
470
471 out_be32(ioaddr->nsect_addr, 0xaa);
472 out_be32(ioaddr->lbal_addr, 0x55);
473
474 out_be32(ioaddr->nsect_addr, 0x55);
475 out_be32(ioaddr->lbal_addr, 0xaa);
476
477 nsect = in_be32(ioaddr->nsect_addr);
478 lbal = in_be32(ioaddr->lbal_addr);
479
480 if ((nsect == 0x55) && (lbal == 0xaa))
481 return 1; /* we found a device */
482
483 return 0; /* nothing found */
484}
485
486/**
487 * scc_bus_post_reset - PATA device post reset
488 *
489 * Note: Original code is ata_bus_post_reset().
490 */
491
492static void scc_bus_post_reset (struct ata_port *ap, unsigned int devmask)
493{
494 struct ata_ioports *ioaddr = &ap->ioaddr;
495 unsigned int dev0 = devmask & (1 << 0);
496 unsigned int dev1 = devmask & (1 << 1);
497 unsigned long timeout;
498
499 /* if device 0 was found in ata_devchk, wait for its
500 * BSY bit to clear
501 */
502 if (dev0)
503 ata_busy_sleep(ap, ATA_TMOUT_BOOT_QUICK, ATA_TMOUT_BOOT);
504
505 /* if device 1 was found in ata_devchk, wait for
506 * register access, then wait for BSY to clear
507 */
508 timeout = jiffies + ATA_TMOUT_BOOT;
509 while (dev1) {
510 u8 nsect, lbal;
511
512 ap->ops->dev_select(ap, 1);
513 nsect = in_be32(ioaddr->nsect_addr);
514 lbal = in_be32(ioaddr->lbal_addr);
515 if ((nsect == 1) && (lbal == 1))
516 break;
517 if (time_after(jiffies, timeout)) {
518 dev1 = 0;
519 break;
520 }
521 msleep(50); /* give drive a breather */
522 }
523 if (dev1)
524 ata_busy_sleep(ap, ATA_TMOUT_BOOT_QUICK, ATA_TMOUT_BOOT);
525
526 /* is all this really necessary? */
527 ap->ops->dev_select(ap, 0);
528 if (dev1)
529 ap->ops->dev_select(ap, 1);
530 if (dev0)
531 ap->ops->dev_select(ap, 0);
532}
533
534/**
535 * scc_bus_softreset - PATA device software reset
536 *
537 * Note: Original code is ata_bus_softreset().
538 */
539
540static unsigned int scc_bus_softreset (struct ata_port *ap,
541 unsigned int devmask)
542{
543 struct ata_ioports *ioaddr = &ap->ioaddr;
544
878d4fed 545 DPRINTK("ata%u: bus reset via SRST\n", ap->print_id);
a619f981
AI		 546
547 /* software reset. causes dev0 to be selected */
548 out_be32(ioaddr->ctl_addr, ap->ctl);
549 udelay(20);
550 out_be32(ioaddr->ctl_addr, ap->ctl | ATA_SRST);
551 udelay(20);
552 out_be32(ioaddr->ctl_addr, ap->ctl);
553
554 /* spec mandates ">= 2ms" before checking status.
555 * We wait 150ms, because that was the magic delay used for
556 * ATAPI devices in Hale Landis's ATADRVR, for the period of time
557 * between when the ATA command register is written, and then
558 * status is checked. Because waiting for "a while" before
559 * checking status is fine, post SRST, we perform this magic
560 * delay here as well.
561 *
562 * Old drivers/ide uses the 2mS rule and then waits for ready
563 */
564 msleep(150);
565
566 /* Before we perform post reset processing we want to see if
567 * the bus shows 0xFF because the odd clown forgets the D7
568 * pulldown resistor.
569 */
570 if (scc_check_status(ap) == 0xFF)
571 return 0;
572
573 scc_bus_post_reset(ap, devmask);
574
575 return 0;
576}
577
578/**
579 * scc_std_softreset - reset host port via ATA SRST
580 * @ap: port to reset
581 * @classes: resulting classes of attached devices
582 *
583 * Note: Original code is ata_std_softreset().
584 */
585
586static int scc_std_softreset (struct ata_port *ap, unsigned int *classes)
587{
588 unsigned int slave_possible = ap->flags & ATA_FLAG_SLAVE_POSS;
589 unsigned int devmask = 0, err_mask;
590 u8 err;
591
592 DPRINTK("ENTER\n");
593
594 if (ata_port_offline(ap)) {
595 classes[0] = ATA_DEV_NONE;
596 goto out;
597 }
598
599 /* determine if device 0/1 are present */
600 if (scc_devchk(ap, 0))
601 devmask |= (1 << 0);
602 if (slave_possible && scc_devchk(ap, 1))
603 devmask |= (1 << 1);
604
605 /* select device 0 again */
606 ap->ops->dev_select(ap, 0);
607
608 /* issue bus reset */
609 DPRINTK("about to softreset, devmask=%x\n", devmask);
610 err_mask = scc_bus_softreset(ap, devmask);
611 if (err_mask) {
612 ata_port_printk(ap, KERN_ERR, "SRST failed (err_mask=0x%x)\n",
613 err_mask);
614 return -EIO;
615 }
616
617 /* determine by signature whether we have ATA or ATAPI devices */
618 classes[0] = ata_dev_try_classify(ap, 0, &err);
619 if (slave_possible && err != 0x81)
620 classes[1] = ata_dev_try_classify(ap, 1, &err);
621
622 out:
623 DPRINTK("EXIT, classes[0]=%u [1]=%u\n", classes[0], classes[1]);
624 return 0;
625}
626
627/**
628 * scc_bmdma_stop - Stop PCI IDE BMDMA transfer
629 * @qc: Command we are ending DMA for
630 */
631
632static void scc_bmdma_stop (struct ata_queued_cmd *qc)
633{
634 struct ata_port *ap = qc->ap;
635 void __iomem *ctrl_base = ap->host->iomap[SCC_CTRL_BAR];
636 void __iomem *bmid_base = ap->host->iomap[SCC_BMID_BAR];
637 u32 reg;
638
639 while (1) {
640 reg = in_be32(bmid_base + SCC_DMA_INTST);
641
642 if (reg & INTSTS_SERROR) {
643 printk(KERN_WARNING "%s: SERROR\n", DRV_NAME);
644 out_be32(bmid_base + SCC_DMA_INTST, INTSTS_SERROR|INTSTS_BMSINT);
645 out_be32(bmid_base + SCC_DMA_CMD,
646 in_be32(bmid_base + SCC_DMA_CMD) & ~ATA_DMA_START);
647 continue;
648 }
649
650 if (reg & INTSTS_PRERR) {
651 u32 maea0, maec0;
652 maea0 = in_be32(ctrl_base + SCC_CTL_MAEA0);
653 maec0 = in_be32(ctrl_base + SCC_CTL_MAEC0);
654 printk(KERN_WARNING "%s: PRERR [addr:%x cmd:%x]\n", DRV_NAME, maea0, maec0);
655 out_be32(bmid_base + SCC_DMA_INTST, INTSTS_PRERR|INTSTS_BMSINT);
656 out_be32(bmid_base + SCC_DMA_CMD,
657 in_be32(bmid_base + SCC_DMA_CMD) & ~ATA_DMA_START);
658 continue;
659 }
660
661 if (reg & INTSTS_RERR) {
662 printk(KERN_WARNING "%s: Response Error\n", DRV_NAME);
663 out_be32(bmid_base + SCC_DMA_INTST, INTSTS_RERR|INTSTS_BMSINT);
664 out_be32(bmid_base + SCC_DMA_CMD,
665 in_be32(bmid_base + SCC_DMA_CMD) & ~ATA_DMA_START);
666 continue;
667 }
668
669 if (reg & INTSTS_ICERR) {
670 out_be32(bmid_base + SCC_DMA_CMD,
671 in_be32(bmid_base + SCC_DMA_CMD) & ~ATA_DMA_START);
672 printk(KERN_WARNING "%s: Illegal Configuration\n", DRV_NAME);
673 out_be32(bmid_base + SCC_DMA_INTST, INTSTS_ICERR|INTSTS_BMSINT);
674 continue;
675 }
676
677 if (reg & INTSTS_BMSINT) {
678 unsigned int classes;
679 printk(KERN_WARNING "%s: Internal Bus Error\n", DRV_NAME);
680 out_be32(bmid_base + SCC_DMA_INTST, INTSTS_BMSINT);
681 /* TBD: SW reset */
682 scc_std_softreset(ap, &classes);
683 continue;
684 }
685
686 if (reg & INTSTS_BMHE) {
687 out_be32(bmid_base + SCC_DMA_INTST, INTSTS_BMHE);
688 continue;
689 }
690
691 if (reg & INTSTS_ACTEINT) {
692 out_be32(bmid_base + SCC_DMA_INTST, INTSTS_ACTEINT);
693 continue;
694 }
695
696 if (reg & INTSTS_IOIRQS) {
697 out_be32(bmid_base + SCC_DMA_INTST, INTSTS_IOIRQS);
698 continue;
699 }
700 break;
701 }
702
703 /* clear start/stop bit */
704 out_be32(bmid_base + SCC_DMA_CMD,
705 in_be32(bmid_base + SCC_DMA_CMD) & ~ATA_DMA_START);
706
707 /* one-PIO-cycle guaranteed wait, per spec, for HDMA1:0 transition */
708 ata_altstatus(ap); /* dummy read */
709}
710
711/**
712 * scc_bmdma_status - Read PCI IDE BMDMA status
713 * @ap: Port associated with this ATA transaction.
714 */
715
716static u8 scc_bmdma_status (struct ata_port *ap)
717{
718 u8 host_stat;
719 void __iomem *mmio = ap->ioaddr.bmdma_addr;
720
721 host_stat = in_be32(mmio + SCC_DMA_STATUS);
722
a84471fe 723 /* Workaround for PTERADD: emulate DMA_INTR when
a619f981
AI		 724 * - IDE_STATUS[ERR] = 1
725 * - INT_STATUS[INTRQ] = 1
726 * - DMA_STATUS[IORACTA] = 1
727 */
728 if (!(host_stat & ATA_DMA_INTR)) {
729 u32 int_status = in_be32(mmio + SCC_DMA_INTST);
730 if (ata_altstatus(ap) & ATA_ERR &&
731 int_status & INTSTS_INTRQ &&
732 host_stat & ATA_DMA_ACTIVE)
733 host_stat |= ATA_DMA_INTR;
734 }
735
736 return host_stat;
737}
738
739/**
740 * scc_data_xfer - Transfer data by PIO
741 * @adev: device for this I/O
742 * @buf: data buffer
743 * @buflen: buffer length
744 * @write_data: read/write
745 *
746 * Note: Original code is ata_data_xfer().
747 */
748
749static void scc_data_xfer (struct ata_device *adev, unsigned char *buf,
750 unsigned int buflen, int write_data)
751{
752 struct ata_port *ap = adev->ap;
753 unsigned int words = buflen >> 1;
754 unsigned int i;
755 u16 *buf16 = (u16 *) buf;
756 void __iomem *mmio = ap->ioaddr.data_addr;
757
758 /* Transfer multiple of 2 bytes */
759 if (write_data) {
760 for (i = 0; i < words; i++)
761 out_be32(mmio, cpu_to_le16(buf16[i]));
762 } else {
763 for (i = 0; i < words; i++)
764 buf16[i] = le16_to_cpu(in_be32(mmio));
765 }
766
767 /* Transfer trailing 1 byte, if any. */
768 if (unlikely(buflen & 0x01)) {
769 u16 align_buf[1] = { 0 };
770 unsigned char *trailing_buf = buf + buflen - 1;
771
772 if (write_data) {
773 memcpy(align_buf, trailing_buf, 1);
774 out_be32(mmio, cpu_to_le16(align_buf[0]));
775 } else {
776 align_buf[0] = le16_to_cpu(in_be32(mmio));
777 memcpy(trailing_buf, align_buf, 1);
778 }
779 }
780}
781
782/**
783 * scc_irq_on - Enable interrupts on a port.
784 * @ap: Port on which interrupts are enabled.
785 *
786 * Note: Original code is ata_irq_on().
787 */
788
789static u8 scc_irq_on (struct ata_port *ap)
790{
791 struct ata_ioports *ioaddr = &ap->ioaddr;
792 u8 tmp;
793
794 ap->ctl &= ~ATA_NIEN;
795 ap->last_ctl = ap->ctl;
796
797 out_be32(ioaddr->ctl_addr, ap->ctl);
798 tmp = ata_wait_idle(ap);
799
800 ap->ops->irq_clear(ap);
801
802 return tmp;
803}
804
805/**
806 * scc_irq_ack - Acknowledge a device interrupt.
807 * @ap: Port on which interrupts are enabled.
808 *
809 * Note: Original code is ata_irq_ack().
810 */
811
812static u8 scc_irq_ack (struct ata_port *ap, unsigned int chk_drq)
813{
814 unsigned int bits = chk_drq ? ATA_BUSY | ATA_DRQ : ATA_BUSY;
815 u8 host_stat, post_stat, status;
816
817 status = ata_busy_wait(ap, bits, 1000);
818 if (status & bits)
819 if (ata_msg_err(ap))
820 printk(KERN_ERR "abnormal status 0x%X\n", status);
821
822 /* get controller status; clear intr, err bits */
823 host_stat = in_be32(ap->ioaddr.bmdma_addr + SCC_DMA_STATUS);
824 out_be32(ap->ioaddr.bmdma_addr + SCC_DMA_STATUS,
825 host_stat | ATA_DMA_INTR | ATA_DMA_ERR);
826
827 post_stat = in_be32(ap->ioaddr.bmdma_addr + SCC_DMA_STATUS);
828
829 if (ata_msg_intr(ap))
830 printk(KERN_INFO "%s: irq ack: host_stat 0x%X, new host_stat 0x%X, drv_stat 0x%X\n",
831 __FUNCTION__,
832 host_stat, post_stat, status);
833
834 return status;
835}
836
837/**
838 * scc_bmdma_freeze - Freeze BMDMA controller port
839 * @ap: port to freeze
840 *
841 * Note: Original code is ata_bmdma_freeze().
842 */
843
844static void scc_bmdma_freeze (struct ata_port *ap)
845{
846 struct ata_ioports *ioaddr = &ap->ioaddr;
847
848 ap->ctl |= ATA_NIEN;
849 ap->last_ctl = ap->ctl;
850
851 out_be32(ioaddr->ctl_addr, ap->ctl);
852
853 /* Under certain circumstances, some controllers raise IRQ on
854 * ATA_NIEN manipulation. Also, many controllers fail to mask
855 * previously pending IRQ on ATA_NIEN assertion. Clear it.
856 */
857 ata_chk_status(ap);
858
859 ap->ops->irq_clear(ap);
860}
861
862/**
863 * scc_pata_prereset - prepare for reset
864 * @ap: ATA port to be reset
865 */
866
d1c68fa6 867static int scc_pata_prereset (struct ata_port *ap, unsigned long deadline)
a619f981
AI		 868{
869 ap->cbl = ATA_CBL_PATA80;
d1c68fa6 870 return ata_std_prereset(ap, deadline);
a619f981
AI		 871}
872
873/**
874 * scc_std_postreset - standard postreset callback
875 * @ap: the target ata_port
876 * @classes: classes of attached devices
877 *
878 * Note: Original code is ata_std_postreset().
879 */
880
881static void scc_std_postreset (struct ata_port *ap, unsigned int *classes)
882{
883 DPRINTK("ENTER\n");
884
885 /* re-enable interrupts */
886 if (!ap->ops->error_handler)
887 ap->ops->irq_on(ap);
888
889 /* is double-select really necessary? */
890 if (classes[0] != ATA_DEV_NONE)
891 ap->ops->dev_select(ap, 1);
892 if (classes[1] != ATA_DEV_NONE)
893 ap->ops->dev_select(ap, 0);
894
895 /* bail out if no device is present */
896 if (classes[0] == ATA_DEV_NONE && classes[1] == ATA_DEV_NONE) {
897 DPRINTK("EXIT, no device\n");
898 return;
899 }
900
901 /* set up device control */
902 if (ap->ioaddr.ctl_addr)
903 out_be32(ap->ioaddr.ctl_addr, ap->ctl);
904
905 DPRINTK("EXIT\n");
906}
907
908/**
909 * scc_error_handler - Stock error handler for BMDMA controller
910 * @ap: port to handle error for
911 */
912
913static void scc_error_handler (struct ata_port *ap)
914{
915 ata_bmdma_drive_eh(ap, scc_pata_prereset, scc_std_softreset, NULL,
916 scc_std_postreset);
917}
918
919/**
920 * scc_bmdma_irq_clear - Clear PCI IDE BMDMA interrupt.
921 * @ap: Port associated with this ATA transaction.
922 *
923 * Note: Original code is ata_bmdma_irq_clear().
924 */
925
926static void scc_bmdma_irq_clear (struct ata_port *ap)
927{
928 void __iomem *mmio = ap->ioaddr.bmdma_addr;
929
930 if (!mmio)
931 return;
932
933 out_be32(mmio + SCC_DMA_STATUS, in_be32(mmio + SCC_DMA_STATUS));
934}
935
936/**
937 * scc_port_start - Set port up for dma.
938 * @ap: Port to initialize
939 *
940 * Allocate space for PRD table using ata_port_start().
941 * Set PRD table address for PTERADD. (PRD Transfer End Read)
942 */
943
944static int scc_port_start (struct ata_port *ap)
945{
946 void __iomem *mmio = ap->ioaddr.bmdma_addr;
947 int rc;
948
949 rc = ata_port_start(ap);
950 if (rc)
951 return rc;
952
953 out_be32(mmio + SCC_DMA_PTERADD, ap->prd_dma);
954 return 0;
955}
956
957/**
958 * scc_port_stop - Undo scc_port_start()
959 * @ap: Port to shut down
960 *
961 * Reset PTERADD.
962 */
963
964static void scc_port_stop (struct ata_port *ap)
965{
966 void __iomem *mmio = ap->ioaddr.bmdma_addr;
967
968 out_be32(mmio + SCC_DMA_PTERADD, 0);
969}
970
971static struct scsi_host_template scc_sht = {
972 .module = THIS_MODULE,
973 .name = DRV_NAME,
974 .ioctl = ata_scsi_ioctl,
975 .queuecommand = ata_scsi_queuecmd,
976 .can_queue = ATA_DEF_QUEUE,
977 .this_id = ATA_SHT_THIS_ID,
978 .sg_tablesize = LIBATA_MAX_PRD,
979 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
980 .emulated = ATA_SHT_EMULATED,
981 .use_clustering = ATA_SHT_USE_CLUSTERING,
982 .proc_name = DRV_NAME,
983 .dma_boundary = ATA_DMA_BOUNDARY,
984 .slave_configure = ata_scsi_slave_config,
985 .slave_destroy = ata_scsi_slave_destroy,
986 .bios_param = ata_std_bios_param,
a619f981
AI		 987};
988
989static const struct ata_port_operations scc_pata_ops = {
990 .port_disable = ata_port_disable,
991 .set_piomode = scc_set_piomode,
992 .set_dmamode = scc_set_dmamode,
993 .mode_filter = ata_pci_default_filter,
994
995 .tf_load = scc_tf_load,
996 .tf_read = scc_tf_read,
997 .exec_command = scc_exec_command,
998 .check_status = scc_check_status,
999 .check_altstatus = scc_check_altstatus,
1000 .dev_select = scc_std_dev_select,
1001
1002 .bmdma_setup = scc_bmdma_setup,
1003 .bmdma_start = scc_bmdma_start,
1004 .bmdma_stop = scc_bmdma_stop,
1005 .bmdma_status = scc_bmdma_status,
1006 .data_xfer = scc_data_xfer,
1007
1008 .qc_prep = ata_qc_prep,
1009 .qc_issue = ata_qc_issue_prot,
1010
1011 .freeze = scc_bmdma_freeze,
1012 .error_handler = scc_error_handler,
1013 .post_internal_cmd = scc_bmdma_stop,
1014
a619f981
AI		 1015 .irq_clear = scc_bmdma_irq_clear,
1016 .irq_on = scc_irq_on,
1017 .irq_ack = scc_irq_ack,
1018
1019 .port_start = scc_port_start,
1020 .port_stop = scc_port_stop,
1021};
1022
1023static struct ata_port_info scc_port_info[] = {
1024 {
a619f981
AI		 1025 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_MMIO | ATA_FLAG_NO_LEGACY,
1026 .pio_mask = 0x1f, /* pio0-4 */
1027 .mwdma_mask = 0x00,
1028 .udma_mask = ATA_UDMA6,
1029 .port_ops = &scc_pata_ops,
1030 },
1031};
1032
1033/**
1034 * scc_reset_controller - initialize SCC PATA controller.
1035 */
1036
5d728824 1037static int scc_reset_controller(struct ata_host *host)
a619f981 1038{
5d728824
TH		 1039 void __iomem *ctrl_base = host->iomap[SCC_CTRL_BAR];
1040 void __iomem *bmid_base = host->iomap[SCC_BMID_BAR];
a619f981
AI		 1041 void __iomem *cckctrl_port = ctrl_base + SCC_CTL_CCKCTRL;
1042 void __iomem *mode_port = ctrl_base + SCC_CTL_MODEREG;
1043 void __iomem *ecmode_port = ctrl_base + SCC_CTL_ECMODE;
1044 void __iomem *intmask_port = bmid_base + SCC_DMA_INTMASK;
1045 void __iomem *dmastatus_port = bmid_base + SCC_DMA_STATUS;
1046 u32 reg = 0;
1047
1048 out_be32(cckctrl_port, reg);
1049 reg |= CCKCTRL_ATACLKOEN;
1050 out_be32(cckctrl_port, reg);
1051 reg |= CCKCTRL_LCLKEN | CCKCTRL_OCLKEN;
1052 out_be32(cckctrl_port, reg);
1053 reg |= CCKCTRL_CRST;
1054 out_be32(cckctrl_port, reg);
1055
1056 for (;;) {
1057 reg = in_be32(cckctrl_port);
1058 if (reg & CCKCTRL_CRST)
1059 break;
1060 udelay(5000);
1061 }
1062
1063 reg |= CCKCTRL_ATARESET;
1064 out_be32(cckctrl_port, reg);
1065 out_be32(ecmode_port, ECMODE_VALUE);
1066 out_be32(mode_port, MODE_JCUSFEN);
1067 out_be32(intmask_port, INTMASK_MSK);
1068
1069 if (in_be32(dmastatus_port) & QCHSD_STPDIAG) {
1070 printk(KERN_WARNING "%s: failed to detect 80c cable. (PDIAG# is high)\n", DRV_NAME);
1071 return -EIO;
1072 }
1073
1074 return 0;
1075}
1076
1077/**
1078 * scc_setup_ports - initialize ioaddr with SCC PATA port offsets.
1079 * @ioaddr: IO address structure to be initialized
1080 * @base: base address of BMID region
1081 */
1082
1083static void scc_setup_ports (struct ata_ioports *ioaddr, void __iomem *base)
1084{
1085 ioaddr->cmd_addr = base + SCC_REG_CMD_ADDR;
1086 ioaddr->altstatus_addr = ioaddr->cmd_addr + SCC_REG_ALTSTATUS;
1087 ioaddr->ctl_addr = ioaddr->cmd_addr + SCC_REG_ALTSTATUS;
1088 ioaddr->bmdma_addr = base;
1089 ioaddr->data_addr = ioaddr->cmd_addr + SCC_REG_DATA;
1090 ioaddr->error_addr = ioaddr->cmd_addr + SCC_REG_ERR;
1091 ioaddr->feature_addr = ioaddr->cmd_addr + SCC_REG_FEATURE;
1092 ioaddr->nsect_addr = ioaddr->cmd_addr + SCC_REG_NSECT;
1093 ioaddr->lbal_addr = ioaddr->cmd_addr + SCC_REG_LBAL;
1094 ioaddr->lbam_addr = ioaddr->cmd_addr + SCC_REG_LBAM;
1095 ioaddr->lbah_addr = ioaddr->cmd_addr + SCC_REG_LBAH;
1096 ioaddr->device_addr = ioaddr->cmd_addr + SCC_REG_DEVICE;
1097 ioaddr->status_addr = ioaddr->cmd_addr + SCC_REG_STATUS;
1098 ioaddr->command_addr = ioaddr->cmd_addr + SCC_REG_CMD;
1099}
1100
5d728824 1101static int scc_host_init(struct ata_host *host)
a619f981 1102{
5d728824 1103 struct pci_dev *pdev = to_pci_dev(host->dev);
a619f981
AI		 1104 int rc;
1105
5d728824 1106 rc = scc_reset_controller(host);
a619f981
AI		 1107 if (rc)
1108 return rc;
1109
a619f981
AI		 1110 rc = pci_set_dma_mask(pdev, ATA_DMA_MASK);
1111 if (rc)
1112 return rc;
1113 rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK);
1114 if (rc)
1115 return rc;
1116
5d728824 1117 scc_setup_ports(&host->ports[0]->ioaddr, host->iomap[SCC_BMID_BAR]);
a619f981
AI		 1118
1119 pci_set_master(pdev);
1120
1121 return 0;
1122}
1123
1124/**
1125 * scc_init_one - Register SCC PATA device with kernel services
1126 * @pdev: PCI device to register
1127 * @ent: Entry in scc_pci_tbl matching with @pdev
1128 *
1129 * LOCKING:
1130 * Inherited from PCI layer (may sleep).
1131 *
1132 * RETURNS:
1133 * Zero on success, or -ERRNO value.
1134 */
1135
1136static int scc_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
1137{
1138 static int printed_version;
1139 unsigned int board_idx = (unsigned int) ent->driver_data;
5d728824 1140 const struct ata_port_info *ppi[] = { &scc_port_info[board_idx], NULL };
0397bad5 1141 struct ata_host *host;
a619f981
AI		 1142 int rc;
1143
1144 if (!printed_version++)
1145 dev_printk(KERN_DEBUG, &pdev->dev,
1146 "version " DRV_VERSION "\n");
1147
0397bad5 1148 host = ata_host_alloc_pinfo(&pdev->dev, ppi, 1);
5d728824
TH		 1149 if (!host)
1150 return -ENOMEM;
1151
a619f981
AI		 1152 rc = pcim_enable_device(pdev);
1153 if (rc)
1154 return rc;
1155
1156 rc = pcim_iomap_regions(pdev, (1 << SCC_CTRL_BAR) | (1 << SCC_BMID_BAR), DRV_NAME);
1157 if (rc == -EBUSY)
1158 pcim_pin_device(pdev);
1159 if (rc)
1160 return rc;
5d728824 1161 host->iomap = pcim_iomap_table(pdev);
a619f981 1162
5d728824 1163 rc = scc_host_init(host);
a619f981
AI		 1164 if (rc)
1165 return rc;
1166
5d728824
TH		 1167 return ata_host_activate(host, pdev->irq, ata_interrupt, IRQF_SHARED,
1168 &scc_sht);
a619f981
AI		 1169}
1170
1171static struct pci_driver scc_pci_driver = {
1172 .name = DRV_NAME,
1173 .id_table = scc_pci_tbl,
1174 .probe = scc_init_one,
1175 .remove = ata_pci_remove_one,
1176#ifdef CONFIG_PM
1177 .suspend = ata_pci_device_suspend,
1178 .resume = ata_pci_device_resume,
1179#endif
1180};
1181
1182static int __init scc_init (void)
1183{
1184 int rc;
1185
1186 DPRINTK("pci_register_driver\n");
1187 rc = pci_register_driver(&scc_pci_driver);
1188 if (rc)
1189 return rc;
1190
1191 DPRINTK("done\n");
1192 return 0;
1193}
1194
1195static void __exit scc_exit (void)
1196{
1197 pci_unregister_driver(&scc_pci_driver);
1198}
1199
1200module_init(scc_init);
1201module_exit(scc_exit);
1202
1203MODULE_AUTHOR("Toshiba corp");
1204MODULE_DESCRIPTION("SCSI low-level driver for Toshiba SCC PATA controller");
1205MODULE_LICENSE("GPL");
1206MODULE_DEVICE_TABLE(pci, scc_pci_tbl);
1207MODULE_VERSION(DRV_VERSION);
Linux kernel - Deliverables
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