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[deliverable/linux.git] / drivers / ata / pata_scc.c
CommitLineData
a619f981
AI		 1/*
2 * Support for IDE interfaces on Celleb platform
3 *
4 * (C) Copyright 2006 TOSHIBA CORPORATION
5 *
6 * This code is based on drivers/ata/ata_piix.c:
7 * Copyright 2003-2005 Red Hat Inc
8 * Copyright 2003-2005 Jeff Garzik
9 * Copyright (C) 1998-1999 Andrzej Krzysztofowicz, Author and Maintainer
10 * Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org>
ab771630 11 * Copyright (C) 2003 Red Hat Inc
a619f981
AI		 12 *
13 * and drivers/ata/ahci.c:
14 * Copyright 2004-2005 Red Hat, Inc.
15 *
16 * and drivers/ata/libata-core.c:
17 * Copyright 2003-2004 Red Hat, Inc. All rights reserved.
18 * Copyright 2003-2004 Jeff Garzik
19 *
20 * This program is free software; you can redistribute it and/or modify
21 * it under the terms of the GNU General Public License as published by
22 * the Free Software Foundation; either version 2 of the License, or
23 * (at your option) any later version.
24 *
25 * This program is distributed in the hope that it will be useful,
26 * but WITHOUT ANY WARRANTY; without even the implied warranty of
27 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
28 * GNU General Public License for more details.
29 *
30 * You should have received a copy of the GNU General Public License along
31 * with this program; if not, write to the Free Software Foundation, Inc.,
32 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
33 */
34
35#include <linux/kernel.h>
36#include <linux/module.h>
37#include <linux/pci.h>
38#include <linux/init.h>
39#include <linux/blkdev.h>
40#include <linux/delay.h>
41#include <linux/device.h>
42#include <scsi/scsi_host.h>
43#include <linux/libata.h>
44
45#define DRV_NAME "pata_scc"
2a3103ce 46#define DRV_VERSION "0.3"
a619f981
AI		 47
48#define PCI_DEVICE_ID_TOSHIBA_SCC_ATA 0x01b4
49
50/* PCI BARs */
51#define SCC_CTRL_BAR 0
52#define SCC_BMID_BAR 1
53
54/* offset of CTRL registers */
55#define SCC_CTL_PIOSHT 0x000
56#define SCC_CTL_PIOCT 0x004
57#define SCC_CTL_MDMACT 0x008
58#define SCC_CTL_MCRCST 0x00C
59#define SCC_CTL_SDMACT 0x010
60#define SCC_CTL_SCRCST 0x014
61#define SCC_CTL_UDENVT 0x018
62#define SCC_CTL_TDVHSEL 0x020
63#define SCC_CTL_MODEREG 0x024
64#define SCC_CTL_ECMODE 0xF00
65#define SCC_CTL_MAEA0 0xF50
66#define SCC_CTL_MAEC0 0xF54
67#define SCC_CTL_CCKCTRL 0xFF0
68
69/* offset of BMID registers */
70#define SCC_DMA_CMD 0x000
71#define SCC_DMA_STATUS 0x004
72#define SCC_DMA_TABLE_OFS 0x008
73#define SCC_DMA_INTMASK 0x010
74#define SCC_DMA_INTST 0x014
75#define SCC_DMA_PTERADD 0x018
76#define SCC_REG_CMD_ADDR 0x020
77#define SCC_REG_DATA 0x000
78#define SCC_REG_ERR 0x004
79#define SCC_REG_FEATURE 0x004
80#define SCC_REG_NSECT 0x008
81#define SCC_REG_LBAL 0x00C
82#define SCC_REG_LBAM 0x010
83#define SCC_REG_LBAH 0x014
84#define SCC_REG_DEVICE 0x018
85#define SCC_REG_STATUS 0x01C
86#define SCC_REG_CMD 0x01C
87#define SCC_REG_ALTSTATUS 0x020
88
89/* register value */
90#define TDVHSEL_MASTER 0x00000001
91#define TDVHSEL_SLAVE 0x00000004
92
93#define MODE_JCUSFEN 0x00000080
94
95#define ECMODE_VALUE 0x01
96
97#define CCKCTRL_ATARESET 0x00040000
98#define CCKCTRL_BUFCNT 0x00020000
99#define CCKCTRL_CRST 0x00010000
100#define CCKCTRL_OCLKEN 0x00000100
101#define CCKCTRL_ATACLKOEN 0x00000002
102#define CCKCTRL_LCLKEN 0x00000001
103
104#define QCHCD_IOS_SS 0x00000001
105
106#define QCHSD_STPDIAG 0x00020000
107
108#define INTMASK_MSK 0xD1000012
109#define INTSTS_SERROR 0x80000000
110#define INTSTS_PRERR 0x40000000
111#define INTSTS_RERR 0x10000000
112#define INTSTS_ICERR 0x01000000
113#define INTSTS_BMSINT 0x00000010
114#define INTSTS_BMHE 0x00000008
115#define INTSTS_IOIRQS 0x00000004
116#define INTSTS_INTRQ 0x00000002
117#define INTSTS_ACTEINT 0x00000001
118
119
120/* PIO transfer mode table */
121/* JCHST */
122static const unsigned long JCHSTtbl[2][7] = {
123 {0x0E, 0x05, 0x02, 0x03, 0x02, 0x00, 0x00}, /* 100MHz */
124 {0x13, 0x07, 0x04, 0x04, 0x03, 0x00, 0x00} /* 133MHz */
125};
126
127/* JCHHT */
128static const unsigned long JCHHTtbl[2][7] = {
129 {0x0E, 0x02, 0x02, 0x02, 0x02, 0x00, 0x00}, /* 100MHz */
130 {0x13, 0x03, 0x03, 0x03, 0x03, 0x00, 0x00} /* 133MHz */
131};
132
133/* JCHCT */
134static const unsigned long JCHCTtbl[2][7] = {
135 {0x1D, 0x1D, 0x1C, 0x0B, 0x06, 0x00, 0x00}, /* 100MHz */
136 {0x27, 0x26, 0x26, 0x0E, 0x09, 0x00, 0x00} /* 133MHz */
137};
138
139/* DMA transfer mode table */
140/* JCHDCTM/JCHDCTS */
141static const unsigned long JCHDCTxtbl[2][7] = {
142 {0x0A, 0x06, 0x04, 0x03, 0x01, 0x00, 0x00}, /* 100MHz */
143 {0x0E, 0x09, 0x06, 0x04, 0x02, 0x01, 0x00} /* 133MHz */
144};
145
146/* JCSTWTM/JCSTWTS */
147static const unsigned long JCSTWTxtbl[2][7] = {
148 {0x06, 0x04, 0x03, 0x02, 0x02, 0x02, 0x00}, /* 100MHz */
149 {0x09, 0x06, 0x04, 0x02, 0x02, 0x02, 0x02} /* 133MHz */
150};
151
152/* JCTSS */
153static const unsigned long JCTSStbl[2][7] = {
154 {0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x00}, /* 100MHz */
155 {0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05} /* 133MHz */
156};
157
158/* JCENVT */
159static const unsigned long JCENVTtbl[2][7] = {
160 {0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x00}, /* 100MHz */
161 {0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02} /* 133MHz */
162};
163
164/* JCACTSELS/JCACTSELM */
165static const unsigned long JCACTSELtbl[2][7] = {
166 {0x00, 0x00, 0x00, 0x00, 0x01, 0x01, 0x00}, /* 100MHz */
167 {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01} /* 133MHz */
168};
169
170static const struct pci_device_id scc_pci_tbl[] = {
171 {PCI_VENDOR_ID_TOSHIBA_2, PCI_DEVICE_ID_TOSHIBA_SCC_ATA,
172 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
173 { } /* terminate list */
174};
175
176/**
177 * scc_set_piomode - Initialize host controller PATA PIO timings
178 * @ap: Port whose timings we are configuring
179 * @adev: um
180 *
181 * Set PIO mode for device.
182 *
183 * LOCKING:
184 * None (inherited from caller).
185 */
186
187static void scc_set_piomode (struct ata_port *ap, struct ata_device *adev)
188{
189 unsigned int pio = adev->pio_mode - XFER_PIO_0;
190 void __iomem *ctrl_base = ap->host->iomap[SCC_CTRL_BAR];
191 void __iomem *cckctrl_port = ctrl_base + SCC_CTL_CCKCTRL;
192 void __iomem *piosht_port = ctrl_base + SCC_CTL_PIOSHT;
193 void __iomem *pioct_port = ctrl_base + SCC_CTL_PIOCT;
194 unsigned long reg;
195 int offset;
196
197 reg = in_be32(cckctrl_port);
198 if (reg & CCKCTRL_ATACLKOEN)
199 offset = 1; /* 133MHz */
200 else
201 offset = 0; /* 100MHz */
202
203 reg = JCHSTtbl[offset][pio] << 16 | JCHHTtbl[offset][pio];
204 out_be32(piosht_port, reg);
205 reg = JCHCTtbl[offset][pio];
206 out_be32(pioct_port, reg);
207}
208
209/**
210 * scc_set_dmamode - Initialize host controller PATA DMA timings
211 * @ap: Port whose timings we are configuring
212 * @adev: um
213 * @udma: udma mode, 0 - 6
214 *
215 * Set UDMA mode for device.
216 *
217 * LOCKING:
218 * None (inherited from caller).
219 */
220
221static void scc_set_dmamode (struct ata_port *ap, struct ata_device *adev)
222{
223 unsigned int udma = adev->dma_mode;
224 unsigned int is_slave = (adev->devno != 0);
225 u8 speed = udma;
226 void __iomem *ctrl_base = ap->host->iomap[SCC_CTRL_BAR];
227 void __iomem *cckctrl_port = ctrl_base + SCC_CTL_CCKCTRL;
228 void __iomem *mdmact_port = ctrl_base + SCC_CTL_MDMACT;
229 void __iomem *mcrcst_port = ctrl_base + SCC_CTL_MCRCST;
230 void __iomem *sdmact_port = ctrl_base + SCC_CTL_SDMACT;
231 void __iomem *scrcst_port = ctrl_base + SCC_CTL_SCRCST;
232 void __iomem *udenvt_port = ctrl_base + SCC_CTL_UDENVT;
233 void __iomem *tdvhsel_port = ctrl_base + SCC_CTL_TDVHSEL;
234 int offset, idx;
235
a84471fe 236 if (in_be32(cckctrl_port) & CCKCTRL_ATACLKOEN)
a619f981
AI		 237 offset = 1; /* 133MHz */
238 else
239 offset = 0; /* 100MHz */
240
241 if (speed >= XFER_UDMA_0)
242 idx = speed - XFER_UDMA_0;
243 else
244 return;
245
246 if (is_slave) {
247 out_be32(sdmact_port, JCHDCTxtbl[offset][idx]);
248 out_be32(scrcst_port, JCSTWTxtbl[offset][idx]);
249 out_be32(tdvhsel_port,
250 (in_be32(tdvhsel_port) & ~TDVHSEL_SLAVE) | (JCACTSELtbl[offset][idx] << 2));
251 } else {
252 out_be32(mdmact_port, JCHDCTxtbl[offset][idx]);
253 out_be32(mcrcst_port, JCSTWTxtbl[offset][idx]);
254 out_be32(tdvhsel_port,
255 (in_be32(tdvhsel_port) & ~TDVHSEL_MASTER) | JCACTSELtbl[offset][idx]);
256 }
257 out_be32(udenvt_port,
258 JCTSStbl[offset][idx] << 16 | JCENVTtbl[offset][idx]);
259}
260
dcd03447
AI		 261unsigned long scc_mode_filter(struct ata_device *adev, unsigned long mask)
262{
263 /* errata A308 workaround: limit ATAPI UDMA mode to UDMA4 */
264 if (adev->class == ATA_DEV_ATAPI &&
265 (mask & (0xE0 << ATA_SHIFT_UDMA))) {
266 printk(KERN_INFO "%s: limit ATAPI UDMA to UDMA4\n", DRV_NAME);
267 mask &= ~(0xE0 << ATA_SHIFT_UDMA);
268 }
9363c382 269 return ata_bmdma_mode_filter(adev, mask);
dcd03447
AI		 270}
271
a619f981
AI		 272/**
273 * scc_tf_load - send taskfile registers to host controller
274 * @ap: Port to which output is sent
275 * @tf: ATA taskfile register set
276 *
9363c382 277 * Note: Original code is ata_sff_tf_load().
a619f981
AI		 278 */
279
280static void scc_tf_load (struct ata_port *ap, const struct ata_taskfile *tf)
281{
282 struct ata_ioports *ioaddr = &ap->ioaddr;
283 unsigned int is_addr = tf->flags & ATA_TFLAG_ISADDR;
284
285 if (tf->ctl != ap->last_ctl) {
286 out_be32(ioaddr->ctl_addr, tf->ctl);
287 ap->last_ctl = tf->ctl;
288 ata_wait_idle(ap);
289 }
290
291 if (is_addr && (tf->flags & ATA_TFLAG_LBA48)) {
292 out_be32(ioaddr->feature_addr, tf->hob_feature);
293 out_be32(ioaddr->nsect_addr, tf->hob_nsect);
294 out_be32(ioaddr->lbal_addr, tf->hob_lbal);
295 out_be32(ioaddr->lbam_addr, tf->hob_lbam);
296 out_be32(ioaddr->lbah_addr, tf->hob_lbah);
297 VPRINTK("hob: feat 0x%X nsect 0x%X, lba 0x%X 0x%X 0x%X\n",
298 tf->hob_feature,
299 tf->hob_nsect,
300 tf->hob_lbal,
301 tf->hob_lbam,
302 tf->hob_lbah);
303 }
304
305 if (is_addr) {
306 out_be32(ioaddr->feature_addr, tf->feature);
307 out_be32(ioaddr->nsect_addr, tf->nsect);
308 out_be32(ioaddr->lbal_addr, tf->lbal);
309 out_be32(ioaddr->lbam_addr, tf->lbam);
310 out_be32(ioaddr->lbah_addr, tf->lbah);
311 VPRINTK("feat 0x%X nsect 0x%X lba 0x%X 0x%X 0x%X\n",
312 tf->feature,
313 tf->nsect,
314 tf->lbal,
315 tf->lbam,
316 tf->lbah);
317 }
318
319 if (tf->flags & ATA_TFLAG_DEVICE) {
320 out_be32(ioaddr->device_addr, tf->device);
321 VPRINTK("device 0x%X\n", tf->device);
322 }
323
324 ata_wait_idle(ap);
325}
326
327/**
328 * scc_check_status - Read device status reg & clear interrupt
329 * @ap: port where the device is
330 *
331 * Note: Original code is ata_check_status().
332 */
333
334static u8 scc_check_status (struct ata_port *ap)
335{
336 return in_be32(ap->ioaddr.status_addr);
337}
338
339/**
340 * scc_tf_read - input device's ATA taskfile shadow registers
341 * @ap: Port from which input is read
342 * @tf: ATA taskfile register set for storing input
343 *
9363c382 344 * Note: Original code is ata_sff_tf_read().
a619f981
AI		 345 */
346
347static void scc_tf_read (struct ata_port *ap, struct ata_taskfile *tf)
348{
349 struct ata_ioports *ioaddr = &ap->ioaddr;
350
351 tf->command = scc_check_status(ap);
352 tf->feature = in_be32(ioaddr->error_addr);
353 tf->nsect = in_be32(ioaddr->nsect_addr);
354 tf->lbal = in_be32(ioaddr->lbal_addr);
355 tf->lbam = in_be32(ioaddr->lbam_addr);
356 tf->lbah = in_be32(ioaddr->lbah_addr);
357 tf->device = in_be32(ioaddr->device_addr);
358
359 if (tf->flags & ATA_TFLAG_LBA48) {
360 out_be32(ioaddr->ctl_addr, tf->ctl | ATA_HOB);
361 tf->hob_feature = in_be32(ioaddr->error_addr);
362 tf->hob_nsect = in_be32(ioaddr->nsect_addr);
363 tf->hob_lbal = in_be32(ioaddr->lbal_addr);
364 tf->hob_lbam = in_be32(ioaddr->lbam_addr);
365 tf->hob_lbah = in_be32(ioaddr->lbah_addr);
fe36cb53
PV		 366 out_be32(ioaddr->ctl_addr, tf->ctl);
367 ap->last_ctl = tf->ctl;
a619f981
AI		 368 }
369}
370
371/**
372 * scc_exec_command - issue ATA command to host controller
373 * @ap: port to which command is being issued
374 * @tf: ATA taskfile register set
375 *
9363c382 376 * Note: Original code is ata_sff_exec_command().
a619f981
AI		 377 */
378
379static void scc_exec_command (struct ata_port *ap,
380 const struct ata_taskfile *tf)
381{
878d4fed 382 DPRINTK("ata%u: cmd 0x%X\n", ap->print_id, tf->command);
a619f981
AI		 383
384 out_be32(ap->ioaddr.command_addr, tf->command);
9363c382 385 ata_sff_pause(ap);
a619f981
AI		 386}
387
388/**
389 * scc_check_altstatus - Read device alternate status reg
390 * @ap: port where the device is
391 */
392
393static u8 scc_check_altstatus (struct ata_port *ap)
394{
395 return in_be32(ap->ioaddr.altstatus_addr);
396}
397
398/**
9363c382 399 * scc_dev_select - Select device 0/1 on ATA bus
a619f981
AI		 400 * @ap: ATA channel to manipulate
401 * @device: ATA device (numbered from zero) to select
402 *
9363c382 403 * Note: Original code is ata_sff_dev_select().
a619f981
AI		 404 */
405
9363c382 406static void scc_dev_select (struct ata_port *ap, unsigned int device)
a619f981
AI		 407{
408 u8 tmp;
409
410 if (device == 0)
411 tmp = ATA_DEVICE_OBS;
412 else
413 tmp = ATA_DEVICE_OBS | ATA_DEV1;
414
415 out_be32(ap->ioaddr.device_addr, tmp);
9363c382 416 ata_sff_pause(ap);
a619f981
AI		 417}
418
419/**
420 * scc_bmdma_setup - Set up PCI IDE BMDMA transaction
421 * @qc: Info associated with this ATA transaction.
422 *
423 * Note: Original code is ata_bmdma_setup().
424 */
425
426static void scc_bmdma_setup (struct ata_queued_cmd *qc)
427{
428 struct ata_port *ap = qc->ap;
429 unsigned int rw = (qc->tf.flags & ATA_TFLAG_WRITE);
430 u8 dmactl;
431 void __iomem *mmio = ap->ioaddr.bmdma_addr;
432
433 /* load PRD table addr */
434 out_be32(mmio + SCC_DMA_TABLE_OFS, ap->prd_dma);
435
436 /* specify data direction, triple-check start bit is clear */
437 dmactl = in_be32(mmio + SCC_DMA_CMD);
438 dmactl &= ~(ATA_DMA_WR | ATA_DMA_START);
439 if (!rw)
440 dmactl |= ATA_DMA_WR;
441 out_be32(mmio + SCC_DMA_CMD, dmactl);
442
443 /* issue r/w command */
5682ed33 444 ap->ops->sff_exec_command(ap, &qc->tf);
a619f981
AI		 445}
446
447/**
448 * scc_bmdma_start - Start a PCI IDE BMDMA transaction
449 * @qc: Info associated with this ATA transaction.
450 *
451 * Note: Original code is ata_bmdma_start().
452 */
453
454static void scc_bmdma_start (struct ata_queued_cmd *qc)
455{
456 struct ata_port *ap = qc->ap;
457 u8 dmactl;
458 void __iomem *mmio = ap->ioaddr.bmdma_addr;
459
460 /* start host DMA transaction */
461 dmactl = in_be32(mmio + SCC_DMA_CMD);
462 out_be32(mmio + SCC_DMA_CMD, dmactl | ATA_DMA_START);
463}
464
465/**
466 * scc_devchk - PATA device presence detection
467 * @ap: ATA channel to examine
468 * @device: Device to examine (starting at zero)
469 *
470 * Note: Original code is ata_devchk().
471 */
472
473static unsigned int scc_devchk (struct ata_port *ap,
474 unsigned int device)
475{
476 struct ata_ioports *ioaddr = &ap->ioaddr;
477 u8 nsect, lbal;
478
5682ed33 479 ap->ops->sff_dev_select(ap, device);
a619f981
AI		 480
481 out_be32(ioaddr->nsect_addr, 0x55);
482 out_be32(ioaddr->lbal_addr, 0xaa);
483
484 out_be32(ioaddr->nsect_addr, 0xaa);
485 out_be32(ioaddr->lbal_addr, 0x55);
486
487 out_be32(ioaddr->nsect_addr, 0x55);
488 out_be32(ioaddr->lbal_addr, 0xaa);
489
490 nsect = in_be32(ioaddr->nsect_addr);
491 lbal = in_be32(ioaddr->lbal_addr);
492
493 if ((nsect == 0x55) && (lbal == 0xaa))
494 return 1; /* we found a device */
495
496 return 0; /* nothing found */
497}
498
499/**
705e76be 500 * scc_wait_after_reset - wait for devices to become ready after reset
a619f981 501 *
705e76be 502 * Note: Original code is ata_sff_wait_after_reset
a619f981
AI		 503 */
504
705e76be
TH		 505int scc_wait_after_reset(struct ata_link *link, unsigned int devmask,
506 unsigned long deadline)
a619f981 507{
705e76be 508 struct ata_port *ap = link->ap;
a619f981
AI		 509 struct ata_ioports *ioaddr = &ap->ioaddr;
510 unsigned int dev0 = devmask & (1 << 0);
511 unsigned int dev1 = devmask & (1 << 1);
705e76be
TH		 512 int rc, ret = 0;
513
514 /* Spec mandates ">= 2ms" before checking status. We wait
515 * 150ms, because that was the magic delay used for ATAPI
516 * devices in Hale Landis's ATADRVR, for the period of time
517 * between when the ATA command register is written, and then
518 * status is checked. Because waiting for "a while" before
519 * checking status is fine, post SRST, we perform this magic
520 * delay here as well.
521 *
522 * Old drivers/ide uses the 2mS rule and then waits for ready.
523 */
524 msleep(150);
a619f981 525
705e76be
TH		 526 /* always check readiness of the master device */
527 rc = ata_sff_wait_ready(link, deadline);
528 /* -ENODEV means the odd clown forgot the D7 pulldown resistor
529 * and TF status is 0xff, bail out on it too.
a619f981 530 */
705e76be
TH		 531 if (rc)
532 return rc;
a619f981 533
705e76be
TH		 534 /* if device 1 was found in ata_devchk, wait for register
535 * access briefly, then wait for BSY to clear.
a619f981 536 */
705e76be
TH		 537 if (dev1) {
538 int i;
a619f981 539
5682ed33 540 ap->ops->sff_dev_select(ap, 1);
705e76be
TH		 541
542 /* Wait for register access. Some ATAPI devices fail
543 * to set nsect/lbal after reset, so don't waste too
544 * much time on it. We're gonna wait for !BSY anyway.
545 */
546 for (i = 0; i < 2; i++) {
547 u8 nsect, lbal;
548
549 nsect = in_be32(ioaddr->nsect_addr);
550 lbal = in_be32(ioaddr->lbal_addr);
551 if ((nsect == 1) && (lbal == 1))
552 break;
553 msleep(50); /* give drive a breather */
554 }
555
556 rc = ata_sff_wait_ready(link, deadline);
557 if (rc) {
558 if (rc != -ENODEV)
559 return rc;
560 ret = rc;
561 }
7e068376 562 }
a619f981
AI		 563
564 /* is all this really necessary? */
5682ed33 565 ap->ops->sff_dev_select(ap, 0);
a619f981 566 if (dev1)
5682ed33 567 ap->ops->sff_dev_select(ap, 1);
a619f981 568 if (dev0)
5682ed33 569 ap->ops->sff_dev_select(ap, 0);
7e068376 570
705e76be 571 return ret;
a619f981
AI		 572}
573
574/**
575 * scc_bus_softreset - PATA device software reset
576 *
577 * Note: Original code is ata_bus_softreset().
578 */
579
7e068376
TB		 580static unsigned int scc_bus_softreset(struct ata_port *ap, unsigned int devmask,
581 unsigned long deadline)
a619f981
AI		 582{
583 struct ata_ioports *ioaddr = &ap->ioaddr;
584
878d4fed 585 DPRINTK("ata%u: bus reset via SRST\n", ap->print_id);
a619f981
AI		 586
587 /* software reset. causes dev0 to be selected */
588 out_be32(ioaddr->ctl_addr, ap->ctl);
589 udelay(20);
590 out_be32(ioaddr->ctl_addr, ap->ctl | ATA_SRST);
591 udelay(20);
592 out_be32(ioaddr->ctl_addr, ap->ctl);
593
e50e3ce5 594 scc_wait_after_reset(&ap->link, devmask, deadline);
a619f981
AI		 595
596 return 0;
597}
598
599/**
9363c382 600 * scc_softreset - reset host port via ATA SRST
a619f981
AI		 601 * @ap: port to reset
602 * @classes: resulting classes of attached devices
7e068376 603 * @deadline: deadline jiffies for the operation
a619f981 604 *
9363c382 605 * Note: Original code is ata_sff_softreset().
a619f981
AI		 606 */
607
9363c382
TH		 608static int scc_softreset(struct ata_link *link, unsigned int *classes,
609 unsigned long deadline)
a619f981 610{
b90fe23b 611 struct ata_port *ap = link->ap;
a619f981
AI		 612 unsigned int slave_possible = ap->flags & ATA_FLAG_SLAVE_POSS;
613 unsigned int devmask = 0, err_mask;
614 u8 err;
615
616 DPRINTK("ENTER\n");
617
a619f981
AI		 618 /* determine if device 0/1 are present */
619 if (scc_devchk(ap, 0))
620 devmask |= (1 << 0);
621 if (slave_possible && scc_devchk(ap, 1))
622 devmask |= (1 << 1);
623
624 /* select device 0 again */
5682ed33 625 ap->ops->sff_dev_select(ap, 0);
a619f981
AI		 626
627 /* issue bus reset */
628 DPRINTK("about to softreset, devmask=%x\n", devmask);
7e068376 629 err_mask = scc_bus_softreset(ap, devmask, deadline);
a619f981
AI		 630 if (err_mask) {
631 ata_port_printk(ap, KERN_ERR, "SRST failed (err_mask=0x%x)\n",
632 err_mask);
633 return -EIO;
634 }
635
636 /* determine by signature whether we have ATA or ATAPI devices */
9363c382 637 classes[0] = ata_sff_dev_classify(&ap->link.device[0],
3f19859e 638 devmask & (1 << 0), &err);
a619f981 639 if (slave_possible && err != 0x81)
9363c382 640 classes[1] = ata_sff_dev_classify(&ap->link.device[1],
3f19859e 641 devmask & (1 << 1), &err);
a619f981 642
a619f981
AI		 643 DPRINTK("EXIT, classes[0]=%u [1]=%u\n", classes[0], classes[1]);
644 return 0;
645}
646
647/**
648 * scc_bmdma_stop - Stop PCI IDE BMDMA transfer
649 * @qc: Command we are ending DMA for
650 */
651
652static void scc_bmdma_stop (struct ata_queued_cmd *qc)
653{
654 struct ata_port *ap = qc->ap;
655 void __iomem *ctrl_base = ap->host->iomap[SCC_CTRL_BAR];
656 void __iomem *bmid_base = ap->host->iomap[SCC_BMID_BAR];
657 u32 reg;
658
659 while (1) {
660 reg = in_be32(bmid_base + SCC_DMA_INTST);
661
662 if (reg & INTSTS_SERROR) {
663 printk(KERN_WARNING "%s: SERROR\n", DRV_NAME);
664 out_be32(bmid_base + SCC_DMA_INTST, INTSTS_SERROR|INTSTS_BMSINT);
665 out_be32(bmid_base + SCC_DMA_CMD,
666 in_be32(bmid_base + SCC_DMA_CMD) & ~ATA_DMA_START);
667 continue;
668 }
669
670 if (reg & INTSTS_PRERR) {
671 u32 maea0, maec0;
672 maea0 = in_be32(ctrl_base + SCC_CTL_MAEA0);
673 maec0 = in_be32(ctrl_base + SCC_CTL_MAEC0);
674 printk(KERN_WARNING "%s: PRERR [addr:%x cmd:%x]\n", DRV_NAME, maea0, maec0);
675 out_be32(bmid_base + SCC_DMA_INTST, INTSTS_PRERR|INTSTS_BMSINT);
676 out_be32(bmid_base + SCC_DMA_CMD,
677 in_be32(bmid_base + SCC_DMA_CMD) & ~ATA_DMA_START);
678 continue;
679 }
680
681 if (reg & INTSTS_RERR) {
682 printk(KERN_WARNING "%s: Response Error\n", DRV_NAME);
683 out_be32(bmid_base + SCC_DMA_INTST, INTSTS_RERR|INTSTS_BMSINT);
684 out_be32(bmid_base + SCC_DMA_CMD,
685 in_be32(bmid_base + SCC_DMA_CMD) & ~ATA_DMA_START);
686 continue;
687 }
688
689 if (reg & INTSTS_ICERR) {
690 out_be32(bmid_base + SCC_DMA_CMD,
691 in_be32(bmid_base + SCC_DMA_CMD) & ~ATA_DMA_START);
692 printk(KERN_WARNING "%s: Illegal Configuration\n", DRV_NAME);
693 out_be32(bmid_base + SCC_DMA_INTST, INTSTS_ICERR|INTSTS_BMSINT);
694 continue;
695 }
696
697 if (reg & INTSTS_BMSINT) {
698 unsigned int classes;
341c2c95 699 unsigned long deadline = ata_deadline(jiffies, ATA_TMOUT_BOOT);
a619f981
AI		 700 printk(KERN_WARNING "%s: Internal Bus Error\n", DRV_NAME);
701 out_be32(bmid_base + SCC_DMA_INTST, INTSTS_BMSINT);
702 /* TBD: SW reset */
9363c382 703 scc_softreset(&ap->link, &classes, deadline);
a619f981
AI		 704 continue;
705 }
706
707 if (reg & INTSTS_BMHE) {
708 out_be32(bmid_base + SCC_DMA_INTST, INTSTS_BMHE);
709 continue;
710 }
711
712 if (reg & INTSTS_ACTEINT) {
713 out_be32(bmid_base + SCC_DMA_INTST, INTSTS_ACTEINT);
714 continue;
715 }
716
717 if (reg & INTSTS_IOIRQS) {
718 out_be32(bmid_base + SCC_DMA_INTST, INTSTS_IOIRQS);
719 continue;
720 }
721 break;
722 }
723
724 /* clear start/stop bit */
725 out_be32(bmid_base + SCC_DMA_CMD,
726 in_be32(bmid_base + SCC_DMA_CMD) & ~ATA_DMA_START);
727
728 /* one-PIO-cycle guaranteed wait, per spec, for HDMA1:0 transition */
a57c1bad 729 ata_sff_dma_pause(ap); /* dummy read */
a619f981
AI		 730}
731
732/**
733 * scc_bmdma_status - Read PCI IDE BMDMA status
734 * @ap: Port associated with this ATA transaction.
735 */
736
737static u8 scc_bmdma_status (struct ata_port *ap)
738{
a619f981 739 void __iomem *mmio = ap->ioaddr.bmdma_addr;
fae57d34
AI		 740 u8 host_stat = in_be32(mmio + SCC_DMA_STATUS);
741 u32 int_status = in_be32(mmio + SCC_DMA_INTST);
b90fe23b 742 struct ata_queued_cmd *qc = ata_qc_from_tag(ap, ap->link.active_tag);
fae57d34
AI		 743 static int retry = 0;
744
745 /* return if IOS_SS is cleared */
746 if (!(in_be32(mmio + SCC_DMA_CMD) & ATA_DMA_START))
747 return host_stat;
748
749 /* errata A252,A308 workaround: Step4 */
a57c1bad
AC		 750 if ((scc_check_altstatus(ap) & ATA_ERR)
751 && (int_status & INTSTS_INTRQ))
fae57d34
AI		 752 return (host_stat | ATA_DMA_INTR);
753
754 /* errata A308 workaround Step5 */
755 if (int_status & INTSTS_IOIRQS) {
756 host_stat |= ATA_DMA_INTR;
757
758 /* We don't check ATAPI DMA because it is limited to UDMA4 */
759 if ((qc->tf.protocol == ATA_PROT_DMA &&
760 qc->dev->xfer_mode > XFER_UDMA_4)) {
761 if (!(int_status & INTSTS_ACTEINT)) {
dcd03447
AI		 762 printk(KERN_WARNING "ata%u: operation failed (transfer data loss)\n",
763 ap->print_id);
fae57d34
AI		 764 host_stat |= ATA_DMA_ERR;
765 if (retry++)
dcd03447 766 ap->udma_mask &= ~(1 << qc->dev->xfer_mode);
fae57d34
AI		 767 } else
768 retry = 0;
769 }
a619f981
AI		 770 }
771
772 return host_stat;
773}
774
775/**
776 * scc_data_xfer - Transfer data by PIO
55dba312 777 * @dev: device for this I/O
a619f981
AI		 778 * @buf: data buffer
779 * @buflen: buffer length
55dba312 780 * @rw: read/write
a619f981 781 *
9363c382 782 * Note: Original code is ata_sff_data_xfer().
a619f981
AI		 783 */
784
55dba312
TH		 785static unsigned int scc_data_xfer (struct ata_device *dev, unsigned char *buf,
786 unsigned int buflen, int rw)
a619f981 787{
55dba312 788 struct ata_port *ap = dev->link->ap;
a619f981
AI		 789 unsigned int words = buflen >> 1;
790 unsigned int i;
826cd156 791 __le16 *buf16 = (__le16 *) buf;
a619f981
AI		 792 void __iomem *mmio = ap->ioaddr.data_addr;
793
794 /* Transfer multiple of 2 bytes */
55dba312 795 if (rw == READ)
a619f981 796 for (i = 0; i < words; i++)
826cd156 797 buf16[i] = cpu_to_le16(in_be32(mmio));
55dba312
TH		 798 else
799 for (i = 0; i < words; i++)
826cd156 800 out_be32(mmio, le16_to_cpu(buf16[i]));
a619f981
AI		 801
802 /* Transfer trailing 1 byte, if any. */
803 if (unlikely(buflen & 0x01)) {
826cd156 804 __le16 align_buf[1] = { 0 };
a619f981
AI		 805 unsigned char *trailing_buf = buf + buflen - 1;
806
55dba312 807 if (rw == READ) {
826cd156 808 align_buf[0] = cpu_to_le16(in_be32(mmio));
a619f981 809 memcpy(trailing_buf, align_buf, 1);
55dba312
TH		 810 } else {
811 memcpy(align_buf, trailing_buf, 1);
826cd156 812 out_be32(mmio, le16_to_cpu(align_buf[0]));
a619f981 813 }
55dba312 814 words++;
a619f981 815 }
55dba312
TH		 816
817 return words << 1;
a619f981
AI		 818}
819
820/**
821 * scc_irq_on - Enable interrupts on a port.
822 * @ap: Port on which interrupts are enabled.
823 *
9363c382 824 * Note: Original code is ata_sff_irq_on().
a619f981
AI		 825 */
826
827static u8 scc_irq_on (struct ata_port *ap)
828{
829 struct ata_ioports *ioaddr = &ap->ioaddr;
830 u8 tmp;
831
832 ap->ctl &= ~ATA_NIEN;
833 ap->last_ctl = ap->ctl;
834
835 out_be32(ioaddr->ctl_addr, ap->ctl);
836 tmp = ata_wait_idle(ap);
837
5682ed33 838 ap->ops->sff_irq_clear(ap);
a619f981
AI		 839
840 return tmp;
841}
842
a619f981 843/**
9363c382 844 * scc_freeze - Freeze BMDMA controller port
a619f981
AI		 845 * @ap: port to freeze
846 *
9363c382 847 * Note: Original code is ata_sff_freeze().
a619f981
AI		 848 */
849
9363c382 850static void scc_freeze (struct ata_port *ap)
a619f981
AI		 851{
852 struct ata_ioports *ioaddr = &ap->ioaddr;
853
854 ap->ctl |= ATA_NIEN;
855 ap->last_ctl = ap->ctl;
856
857 out_be32(ioaddr->ctl_addr, ap->ctl);
858
859 /* Under certain circumstances, some controllers raise IRQ on
860 * ATA_NIEN manipulation. Also, many controllers fail to mask
861 * previously pending IRQ on ATA_NIEN assertion. Clear it.
862 */
5682ed33 863 ap->ops->sff_check_status(ap);
a619f981 864
5682ed33 865 ap->ops->sff_irq_clear(ap);
a619f981
AI		 866}
867
868/**
869 * scc_pata_prereset - prepare for reset
870 * @ap: ATA port to be reset
7e068376 871 * @deadline: deadline jiffies for the operation
a619f981
AI		 872 */
873
b90fe23b 874static int scc_pata_prereset(struct ata_link *link, unsigned long deadline)
a619f981 875{
b90fe23b 876 link->ap->cbl = ATA_CBL_PATA80;
9363c382 877 return ata_sff_prereset(link, deadline);
a619f981
AI		 878}
879
880/**
9363c382 881 * scc_postreset - standard postreset callback
a619f981
AI		 882 * @ap: the target ata_port
883 * @classes: classes of attached devices
884 *
9363c382 885 * Note: Original code is ata_sff_postreset().
a619f981
AI		 886 */
887
9363c382 888static void scc_postreset(struct ata_link *link, unsigned int *classes)
a619f981 889{
b90fe23b
SS		 890 struct ata_port *ap = link->ap;
891
a619f981
AI		 892 DPRINTK("ENTER\n");
893
a619f981
AI		 894 /* is double-select really necessary? */
895 if (classes[0] != ATA_DEV_NONE)
5682ed33 896 ap->ops->sff_dev_select(ap, 1);
a619f981 897 if (classes[1] != ATA_DEV_NONE)
5682ed33 898 ap->ops->sff_dev_select(ap, 0);
a619f981
AI		 899
900 /* bail out if no device is present */
901 if (classes[0] == ATA_DEV_NONE && classes[1] == ATA_DEV_NONE) {
902 DPRINTK("EXIT, no device\n");
903 return;
904 }
905
906 /* set up device control */
907 if (ap->ioaddr.ctl_addr)
908 out_be32(ap->ioaddr.ctl_addr, ap->ctl);
909
910 DPRINTK("EXIT\n");
911}
912
a619f981 913/**
9363c382 914 * scc_irq_clear - Clear PCI IDE BMDMA interrupt.
a619f981
AI		 915 * @ap: Port associated with this ATA transaction.
916 *
9363c382 917 * Note: Original code is ata_sff_irq_clear().
a619f981
AI		 918 */
919
9363c382 920static void scc_irq_clear (struct ata_port *ap)
a619f981
AI		 921{
922 void __iomem *mmio = ap->ioaddr.bmdma_addr;
923
924 if (!mmio)
925 return;
926
927 out_be32(mmio + SCC_DMA_STATUS, in_be32(mmio + SCC_DMA_STATUS));
928}
929
930/**
931 * scc_port_start - Set port up for dma.
932 * @ap: Port to initialize
933 *
934 * Allocate space for PRD table using ata_port_start().
935 * Set PRD table address for PTERADD. (PRD Transfer End Read)
936 */
937
938static int scc_port_start (struct ata_port *ap)
939{
940 void __iomem *mmio = ap->ioaddr.bmdma_addr;
941 int rc;
942
943 rc = ata_port_start(ap);
944 if (rc)
945 return rc;
946
947 out_be32(mmio + SCC_DMA_PTERADD, ap->prd_dma);
948 return 0;
949}
950
951/**
952 * scc_port_stop - Undo scc_port_start()
953 * @ap: Port to shut down
954 *
955 * Reset PTERADD.
956 */
957
958static void scc_port_stop (struct ata_port *ap)
959{
960 void __iomem *mmio = ap->ioaddr.bmdma_addr;
961
962 out_be32(mmio + SCC_DMA_PTERADD, 0);
963}
964
965static struct scsi_host_template scc_sht = {
68d1d07b 966 ATA_BMDMA_SHT(DRV_NAME),
a619f981
AI		 967};
968
c1796d98 969static struct ata_port_operations scc_pata_ops = {
029cfd6b
TH		 970 .inherits = &ata_bmdma_port_ops,
971
a619f981
AI		 972 .set_piomode = scc_set_piomode,
973 .set_dmamode = scc_set_dmamode,
dcd03447 974 .mode_filter = scc_mode_filter,
a619f981 975
5682ed33
TH		 976 .sff_tf_load = scc_tf_load,
977 .sff_tf_read = scc_tf_read,
978 .sff_exec_command = scc_exec_command,
979 .sff_check_status = scc_check_status,
980 .sff_check_altstatus = scc_check_altstatus,
981 .sff_dev_select = scc_dev_select,
a619f981
AI		 982
983 .bmdma_setup = scc_bmdma_setup,
984 .bmdma_start = scc_bmdma_start,
985 .bmdma_stop = scc_bmdma_stop,
986 .bmdma_status = scc_bmdma_status,
5682ed33 987 .sff_data_xfer = scc_data_xfer,
a619f981 988
9363c382 989 .freeze = scc_freeze,
a1efdaba 990 .prereset = scc_pata_prereset,
9363c382
TH		 991 .softreset = scc_softreset,
992 .postreset = scc_postreset,
a619f981
AI		 993 .post_internal_cmd = scc_bmdma_stop,
994
5682ed33
TH		 995 .sff_irq_clear = scc_irq_clear,
996 .sff_irq_on = scc_irq_on,
a619f981
AI		 997
998 .port_start = scc_port_start,
999 .port_stop = scc_port_stop,
1000};
1001
1002static struct ata_port_info scc_port_info[] = {
1003 {
a619f981
AI		 1004 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_MMIO | ATA_FLAG_NO_LEGACY,
1005 .pio_mask = 0x1f, /* pio0-4 */
1006 .mwdma_mask = 0x00,
1007 .udma_mask = ATA_UDMA6,
1008 .port_ops = &scc_pata_ops,
1009 },
1010};
1011
1012/**
1013 * scc_reset_controller - initialize SCC PATA controller.
1014 */
1015
5d728824 1016static int scc_reset_controller(struct ata_host *host)
a619f981 1017{
5d728824
TH		 1018 void __iomem *ctrl_base = host->iomap[SCC_CTRL_BAR];
1019 void __iomem *bmid_base = host->iomap[SCC_BMID_BAR];
a619f981
AI		 1020 void __iomem *cckctrl_port = ctrl_base + SCC_CTL_CCKCTRL;
1021 void __iomem *mode_port = ctrl_base + SCC_CTL_MODEREG;
1022 void __iomem *ecmode_port = ctrl_base + SCC_CTL_ECMODE;
1023 void __iomem *intmask_port = bmid_base + SCC_DMA_INTMASK;
1024 void __iomem *dmastatus_port = bmid_base + SCC_DMA_STATUS;
1025 u32 reg = 0;
1026
1027 out_be32(cckctrl_port, reg);
1028 reg |= CCKCTRL_ATACLKOEN;
1029 out_be32(cckctrl_port, reg);
1030 reg |= CCKCTRL_LCLKEN | CCKCTRL_OCLKEN;
1031 out_be32(cckctrl_port, reg);
1032 reg |= CCKCTRL_CRST;
1033 out_be32(cckctrl_port, reg);
1034
1035 for (;;) {
1036 reg = in_be32(cckctrl_port);
1037 if (reg & CCKCTRL_CRST)
1038 break;
1039 udelay(5000);
1040 }
1041
1042 reg |= CCKCTRL_ATARESET;
1043 out_be32(cckctrl_port, reg);
1044 out_be32(ecmode_port, ECMODE_VALUE);
1045 out_be32(mode_port, MODE_JCUSFEN);
1046 out_be32(intmask_port, INTMASK_MSK);
1047
1048 if (in_be32(dmastatus_port) & QCHSD_STPDIAG) {
1049 printk(KERN_WARNING "%s: failed to detect 80c cable. (PDIAG# is high)\n", DRV_NAME);
1050 return -EIO;
1051 }
1052
1053 return 0;
1054}
1055
1056/**
1057 * scc_setup_ports - initialize ioaddr with SCC PATA port offsets.
1058 * @ioaddr: IO address structure to be initialized
1059 * @base: base address of BMID region
1060 */
1061
1062static void scc_setup_ports (struct ata_ioports *ioaddr, void __iomem *base)
1063{
1064 ioaddr->cmd_addr = base + SCC_REG_CMD_ADDR;
1065 ioaddr->altstatus_addr = ioaddr->cmd_addr + SCC_REG_ALTSTATUS;
1066 ioaddr->ctl_addr = ioaddr->cmd_addr + SCC_REG_ALTSTATUS;
1067 ioaddr->bmdma_addr = base;
1068 ioaddr->data_addr = ioaddr->cmd_addr + SCC_REG_DATA;
1069 ioaddr->error_addr = ioaddr->cmd_addr + SCC_REG_ERR;
1070 ioaddr->feature_addr = ioaddr->cmd_addr + SCC_REG_FEATURE;
1071 ioaddr->nsect_addr = ioaddr->cmd_addr + SCC_REG_NSECT;
1072 ioaddr->lbal_addr = ioaddr->cmd_addr + SCC_REG_LBAL;
1073 ioaddr->lbam_addr = ioaddr->cmd_addr + SCC_REG_LBAM;
1074 ioaddr->lbah_addr = ioaddr->cmd_addr + SCC_REG_LBAH;
1075 ioaddr->device_addr = ioaddr->cmd_addr + SCC_REG_DEVICE;
1076 ioaddr->status_addr = ioaddr->cmd_addr + SCC_REG_STATUS;
1077 ioaddr->command_addr = ioaddr->cmd_addr + SCC_REG_CMD;
1078}
1079
5d728824 1080static int scc_host_init(struct ata_host *host)
a619f981 1081{
5d728824 1082 struct pci_dev *pdev = to_pci_dev(host->dev);
a619f981
AI		 1083 int rc;
1084
5d728824 1085 rc = scc_reset_controller(host);
a619f981
AI		 1086 if (rc)
1087 return rc;
1088
a619f981
AI		 1089 rc = pci_set_dma_mask(pdev, ATA_DMA_MASK);
1090 if (rc)
1091 return rc;
1092 rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK);
1093 if (rc)
1094 return rc;
1095
5d728824 1096 scc_setup_ports(&host->ports[0]->ioaddr, host->iomap[SCC_BMID_BAR]);
a619f981
AI		 1097
1098 pci_set_master(pdev);
1099
1100 return 0;
1101}
1102
1103/**
1104 * scc_init_one - Register SCC PATA device with kernel services
1105 * @pdev: PCI device to register
1106 * @ent: Entry in scc_pci_tbl matching with @pdev
1107 *
1108 * LOCKING:
1109 * Inherited from PCI layer (may sleep).
1110 *
1111 * RETURNS:
1112 * Zero on success, or -ERRNO value.
1113 */
1114
1115static int scc_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
1116{
1117 static int printed_version;
1118 unsigned int board_idx = (unsigned int) ent->driver_data;
5d728824 1119 const struct ata_port_info *ppi[] = { &scc_port_info[board_idx], NULL };
0397bad5 1120 struct ata_host *host;
a619f981
AI		 1121 int rc;
1122
1123 if (!printed_version++)
1124 dev_printk(KERN_DEBUG, &pdev->dev,
1125 "version " DRV_VERSION "\n");
1126
0397bad5 1127 host = ata_host_alloc_pinfo(&pdev->dev, ppi, 1);
5d728824
TH		 1128 if (!host)
1129 return -ENOMEM;
1130
a619f981
AI		 1131 rc = pcim_enable_device(pdev);
1132 if (rc)
1133 return rc;
1134
1135 rc = pcim_iomap_regions(pdev, (1 << SCC_CTRL_BAR) | (1 << SCC_BMID_BAR), DRV_NAME);
1136 if (rc == -EBUSY)
1137 pcim_pin_device(pdev);
1138 if (rc)
1139 return rc;
5d728824 1140 host->iomap = pcim_iomap_table(pdev);
a619f981 1141
cbcdd875
TH		 1142 ata_port_pbar_desc(host->ports[0], SCC_CTRL_BAR, -1, "ctrl");
1143 ata_port_pbar_desc(host->ports[0], SCC_BMID_BAR, -1, "bmid");
1144
5d728824 1145 rc = scc_host_init(host);
a619f981
AI		 1146 if (rc)
1147 return rc;
1148
9363c382
TH		 1149 return ata_host_activate(host, pdev->irq, ata_sff_interrupt,
1150 IRQF_SHARED, &scc_sht);
a619f981
AI		 1151}
1152
1153static struct pci_driver scc_pci_driver = {
1154 .name = DRV_NAME,
1155 .id_table = scc_pci_tbl,
1156 .probe = scc_init_one,
1157 .remove = ata_pci_remove_one,
1158#ifdef CONFIG_PM
1159 .suspend = ata_pci_device_suspend,
1160 .resume = ata_pci_device_resume,
1161#endif
1162};
1163
1164static int __init scc_init (void)
1165{
1166 int rc;
1167
1168 DPRINTK("pci_register_driver\n");
1169 rc = pci_register_driver(&scc_pci_driver);
1170 if (rc)
1171 return rc;
1172
1173 DPRINTK("done\n");
1174 return 0;
1175}
1176
1177static void __exit scc_exit (void)
1178{
1179 pci_unregister_driver(&scc_pci_driver);
1180}
1181
1182module_init(scc_init);
1183module_exit(scc_exit);
1184
1185MODULE_AUTHOR("Toshiba corp");
1186MODULE_DESCRIPTION("SCSI low-level driver for Toshiba SCC PATA controller");
1187MODULE_LICENSE("GPL");
1188MODULE_DEVICE_TABLE(pci, scc_pci_tbl);
1189MODULE_VERSION(DRV_VERSION);
Linux kernel - Deliverables
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