[deliverable/linux.git] / drivers / ata / pata_serverworks.c

/*
 * pata_serverworks.c 	- Serverworks PATA for new ATA layer
 *			  (C) 2005 Red Hat Inc
 *			  Alan Cox <alan@redhat.com>
 *
 * based upon
 *
 * serverworks.c
 *
 * Copyright (C) 1998-2000 Michel Aubry
 * Copyright (C) 1998-2000 Andrzej Krzysztofowicz
 * Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org>
 * Portions copyright (c) 2001 Sun Microsystems
 *
 *
 * RCC/ServerWorks IDE driver for Linux
 *
 *   OSB4: `Open South Bridge' IDE Interface (fn 1)
 *         supports UDMA mode 2 (33 MB/s)
 *
 *   CSB5: `Champion South Bridge' IDE Interface (fn 1)
 *         all revisions support UDMA mode 4 (66 MB/s)
 *         revision A2.0 and up support UDMA mode 5 (100 MB/s)
 *
 *         *** The CSB5 does not provide ANY register ***
 *         *** to detect 80-conductor cable presence. ***
 *
 *   CSB6: `Champion South Bridge' IDE Interface (optional: third channel)
 *
 * Documentation:
 *	Available under NDA only. Errata info very hard to get.
 */

#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/pci.h>
#include <linux/init.h>
#include <linux/blkdev.h>
#include <linux/delay.h>
#include <scsi/scsi_host.h>
#include <linux/libata.h>

#define DRV_NAME "pata_serverworks"
#define DRV_VERSION "0.4.1"

#define SVWKS_CSB5_REVISION_NEW	0x92 /* min PCI_REVISION_ID for UDMA5 (A2.0) */
#define SVWKS_CSB6_REVISION	0xa0 /* min PCI_REVISION_ID for UDMA4 (A1.0) */

/* Seagate Barracuda ATA IV Family drives in UDMA mode 5
 * can overrun their FIFOs when used with the CSB5 */

static const char *csb_bad_ata100[] = {
	"ST320011A",
	"ST340016A",
	"ST360021A",
	"ST380021A",
	NULL
};

/**
 *	dell_cable	-	Dell serverworks cable detection
 *	@ap: ATA port to do cable detect
 *
 *	Dell hide the 40/80 pin select for their interfaces in the top two
 *	bits of the subsystem ID.
 */

static int dell_cable(struct ata_port *ap) {
	struct pci_dev *pdev = to_pci_dev(ap->host->dev);

	if (pdev->subsystem_device & (1 << (ap->port_no + 14)))
		return ATA_CBL_PATA80;
	return ATA_CBL_PATA40;
}

/**
 *	sun_cable	-	Sun Cobalt 'Alpine' cable detection
 *	@ap: ATA port to do cable select
 *
 *	Cobalt CSB5 IDE hides the 40/80pin in the top two bits of the
 *	subsystem ID the same as dell. We could use one function but we may
 *	need to extend the Dell one in future
 */

static int sun_cable(struct ata_port *ap) {
	struct pci_dev *pdev = to_pci_dev(ap->host->dev);

	if (pdev->subsystem_device & (1 << (ap->port_no + 14)))
		return ATA_CBL_PATA80;
	return ATA_CBL_PATA40;
}

/**
 *	osb4_cable	-	OSB4 cable detect
 *	@ap: ATA port to check
 *
 *	The OSB4 isn't UDMA66 capable so this is easy
 */

static int osb4_cable(struct ata_port *ap) {
	return ATA_CBL_PATA40;
}

/**
 *	csb4_cable	-	CSB5/6 cable detect
 *	@ap: ATA port to check
 *
 *	Serverworks default arrangement is to use the drive side detection
 *	only.
 */

static int csb_cable(struct ata_port *ap) {
	return ATA_CBL_PATA80;
}

struct sv_cable_table {
	int device;
	int subvendor;
	int (*cable_detect)(struct ata_port *ap);
};

/*
 *	Note that we don't copy the old serverworks code because the old
 *	code contains obvious mistakes
 */

static struct sv_cable_table cable_detect[] = {
	{ PCI_DEVICE_ID_SERVERWORKS_CSB5IDE, PCI_VENDOR_ID_DELL, dell_cable },
	{ PCI_DEVICE_ID_SERVERWORKS_CSB6IDE, PCI_VENDOR_ID_DELL, dell_cable },
	{ PCI_DEVICE_ID_SERVERWORKS_CSB5IDE, PCI_VENDOR_ID_SUN,  sun_cable },
	{ PCI_DEVICE_ID_SERVERWORKS_OSB4IDE, PCI_ANY_ID, osb4_cable },
	{ PCI_DEVICE_ID_SERVERWORKS_CSB5IDE, PCI_ANY_ID, csb_cable },
	{ PCI_DEVICE_ID_SERVERWORKS_CSB6IDE, PCI_ANY_ID, csb_cable },
	{ PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2, PCI_ANY_ID, csb_cable },
	{ PCI_DEVICE_ID_SERVERWORKS_HT1000IDE, PCI_ANY_ID, csb_cable },
	{ }
};

/**
 *	serverworks_cable_detect	-	cable detection
 *	@ap: ATA port
 *	@deadline: deadline jiffies for the operation
 *
 *	Perform cable detection according to the device and subvendor
 *	identifications
 */

static int serverworks_cable_detect(struct ata_port *ap)
{
	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	struct sv_cable_table *cb = cable_detect;

	while(cb->device) {
		if (cb->device == pdev->device &&
		    (cb->subvendor == pdev->subsystem_vendor ||
		      cb->subvendor == PCI_ANY_ID)) {
			return cb->cable_detect(ap);
		}
		cb++;
	}

	BUG();
	return -1;	/* kill compiler warning */
}

/**
 *	serverworks_is_csb	-	Check for CSB or OSB
 *	@pdev: PCI device to check
 *
 *	Returns true if the device being checked is known to be a CSB
 *	series device.
 */

static u8 serverworks_is_csb(struct pci_dev *pdev)
{
	switch (pdev->device) {
		case PCI_DEVICE_ID_SERVERWORKS_CSB5IDE:
		case PCI_DEVICE_ID_SERVERWORKS_CSB6IDE:
		case PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2:
		case PCI_DEVICE_ID_SERVERWORKS_HT1000IDE:
			return 1;
		default:
			break;
	}
	return 0;
}

/**
 *	serverworks_osb4_filter	-	mode selection filter
 *	@adev: ATA device
 *	@mask: Mask of proposed modes
 *
 *	Filter the offered modes for the device to apply controller
 *	specific rules. OSB4 requires no UDMA for disks due to a FIFO
 *	bug we hit.
 */

static unsigned long serverworks_osb4_filter(struct ata_device *adev, unsigned long mask)
{
	if (adev->class == ATA_DEV_ATA)
		mask &= ~ATA_MASK_UDMA;
	return ata_pci_default_filter(adev, mask);
}


/**
 *	serverworks_csb_filter	-	mode selection filter
 *	@adev: ATA device
 *	@mask: Mask of proposed modes
 *
 *	Check the blacklist and disable UDMA5 if matched
 */

static unsigned long serverworks_csb_filter(struct ata_device *adev, unsigned long mask)
{
	const char *p;
	char model_num[ATA_ID_PROD_LEN + 1];
	int i;

	/* Disk, UDMA */
	if (adev->class != ATA_DEV_ATA)
		return ata_pci_default_filter(adev, mask);

	/* Actually do need to check */
	ata_id_c_string(adev->id, model_num, ATA_ID_PROD, sizeof(model_num));

	for (i = 0; (p = csb_bad_ata100[i]) != NULL; i++) {
		if (!strcmp(p, model_num))
			mask &= ~(0x1F << ATA_SHIFT_UDMA);
	}
	return ata_pci_default_filter(adev, mask);
}


/**
 *	serverworks_set_piomode	-	set initial PIO mode data
 *	@ap: ATA interface
 *	@adev: ATA device
 *
 *	Program the OSB4/CSB5 timing registers for PIO. The PIO register
 *	load is done as a simple lookup.
 */
static void serverworks_set_piomode(struct ata_port *ap, struct ata_device *adev)
{
	static const u8 pio_mode[] = { 0x5d, 0x47, 0x34, 0x22, 0x20 };
	int offset = 1 + (2 * ap->port_no) - adev->devno;
	int devbits = (2 * ap->port_no + adev->devno) * 4;
	u16 csb5_pio;
	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	int pio = adev->pio_mode - XFER_PIO_0;

	pci_write_config_byte(pdev, 0x40 + offset, pio_mode[pio]);

	/* The OSB4 just requires the timing but the CSB series want the
	   mode number as well */
	if (serverworks_is_csb(pdev)) {
		pci_read_config_word(pdev, 0x4A, &csb5_pio);
		csb5_pio &= ~(0x0F << devbits);
		pci_write_config_byte(pdev, 0x4A, csb5_pio | (pio << devbits));
	}
}

/**
 *	serverworks_set_dmamode	-	set initial DMA mode data
 *	@ap: ATA interface
 *	@adev: ATA device
 *
 *	Program the MWDMA/UDMA modes for the serverworks OSB4/CSB5
 *	chipset. The MWDMA mode values are pulled from a lookup table
 *	while the chipset uses mode number for UDMA.
 */

static void serverworks_set_dmamode(struct ata_port *ap, struct ata_device *adev)
{
	static const u8 dma_mode[] = { 0x77, 0x21, 0x20 };
	int offset = 1 + 2 * ap->port_no - adev->devno;
	int devbits = (2 * ap->port_no + adev->devno);
	u8 ultra;
	u8 ultra_cfg;
	struct pci_dev *pdev = to_pci_dev(ap->host->dev);

	pci_read_config_byte(pdev, 0x54, &ultra_cfg);

	if (adev->dma_mode >= XFER_UDMA_0) {
		pci_write_config_byte(pdev, 0x44 + offset,  0x20);

		pci_read_config_byte(pdev, 0x56 + ap->port_no, &ultra);
		ultra &= ~(0x0F << (ap->port_no * 4));
		ultra |= (adev->dma_mode - XFER_UDMA_0)
					<< (ap->port_no * 4);
		pci_write_config_byte(pdev, 0x56 + ap->port_no, ultra);

		ultra_cfg |=  (1 << devbits);
	} else {
		pci_write_config_byte(pdev, 0x44 + offset,
			dma_mode[adev->dma_mode - XFER_MW_DMA_0]);
		ultra_cfg &= ~(1 << devbits);
	}
	pci_write_config_byte(pdev, 0x54, ultra_cfg);
}

static struct scsi_host_template serverworks_sht = {
	.module			= THIS_MODULE,
	.name			= DRV_NAME,
	.ioctl			= ata_scsi_ioctl,
	.queuecommand		= ata_scsi_queuecmd,
	.can_queue		= ATA_DEF_QUEUE,
	.this_id		= ATA_SHT_THIS_ID,
	.sg_tablesize		= LIBATA_MAX_PRD,
	.cmd_per_lun		= ATA_SHT_CMD_PER_LUN,
	.emulated		= ATA_SHT_EMULATED,
	.use_clustering		= ATA_SHT_USE_CLUSTERING,
	.proc_name		= DRV_NAME,
	.dma_boundary		= ATA_DMA_BOUNDARY,
	.slave_configure	= ata_scsi_slave_config,
	.slave_destroy		= ata_scsi_slave_destroy,
	.bios_param		= ata_std_bios_param,
};

static struct ata_port_operations serverworks_osb4_port_ops = {
	.port_disable	= ata_port_disable,
	.set_piomode	= serverworks_set_piomode,
	.set_dmamode	= serverworks_set_dmamode,
	.mode_filter	= serverworks_osb4_filter,

	.tf_load	= ata_tf_load,
	.tf_read	= ata_tf_read,
	.check_status 	= ata_check_status,
	.exec_command	= ata_exec_command,
	.dev_select 	= ata_std_dev_select,

	.freeze		= ata_bmdma_freeze,
	.thaw		= ata_bmdma_thaw,
	.error_handler	= ata_bmdma_error_handler,
	.post_internal_cmd = ata_bmdma_post_internal_cmd,
	.cable_detect	= serverworks_cable_detect,

	.bmdma_setup 	= ata_bmdma_setup,
	.bmdma_start 	= ata_bmdma_start,
	.bmdma_stop	= ata_bmdma_stop,
	.bmdma_status 	= ata_bmdma_status,

	.qc_prep 	= ata_qc_prep,
	.qc_issue	= ata_qc_issue_prot,

	.data_xfer	= ata_data_xfer,

	.irq_handler	= ata_interrupt,
	.irq_clear	= ata_bmdma_irq_clear,
	.irq_on		= ata_irq_on,
	.irq_ack	= ata_irq_ack,

	.port_start	= ata_port_start,
};

static struct ata_port_operations serverworks_csb_port_ops = {
	.port_disable	= ata_port_disable,
	.set_piomode	= serverworks_set_piomode,
	.set_dmamode	= serverworks_set_dmamode,
	.mode_filter	= serverworks_csb_filter,

	.tf_load	= ata_tf_load,
	.tf_read	= ata_tf_read,
	.check_status 	= ata_check_status,
	.exec_command	= ata_exec_command,
	.dev_select 	= ata_std_dev_select,

	.freeze		= ata_bmdma_freeze,
	.thaw		= ata_bmdma_thaw,
	.error_handler	= ata_bmdma_error_handler,
	.post_internal_cmd = ata_bmdma_post_internal_cmd,
	.cable_detect	= serverworks_cable_detect,

	.bmdma_setup 	= ata_bmdma_setup,
	.bmdma_start 	= ata_bmdma_start,
	.bmdma_stop	= ata_bmdma_stop,
	.bmdma_status 	= ata_bmdma_status,

	.qc_prep 	= ata_qc_prep,
	.qc_issue	= ata_qc_issue_prot,

	.data_xfer	= ata_data_xfer,

	.irq_handler	= ata_interrupt,
	.irq_clear	= ata_bmdma_irq_clear,
	.irq_on		= ata_irq_on,
	.irq_ack	= ata_irq_ack,

	.port_start	= ata_port_start,
};

static int serverworks_fixup_osb4(struct pci_dev *pdev)
{
	u32 reg;
	struct pci_dev *isa_dev = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
		  PCI_DEVICE_ID_SERVERWORKS_OSB4, NULL);
	if (isa_dev) {
		pci_read_config_dword(isa_dev, 0x64, &reg);
		reg &= ~0x00002000; /* disable 600ns interrupt mask */
		if (!(reg & 0x00004000))
			printk(KERN_DEBUG DRV_NAME ": UDMA not BIOS enabled.\n");
		reg |=  0x00004000; /* enable UDMA/33 support */
		pci_write_config_dword(isa_dev, 0x64, reg);
		pci_dev_put(isa_dev);
		return 0;
	}
	printk(KERN_WARNING "ata_serverworks: Unable to find bridge.\n");
	return -ENODEV;
}

static int serverworks_fixup_csb(struct pci_dev *pdev)
{
	u8 rev;
	u8 btr;

	pci_read_config_byte(pdev, PCI_REVISION_ID, &rev);

	/* Third Channel Test */
	if (!(PCI_FUNC(pdev->devfn) & 1)) {
		struct pci_dev * findev = NULL;
		u32 reg4c = 0;
		findev = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
			PCI_DEVICE_ID_SERVERWORKS_CSB5, NULL);
		if (findev) {
			pci_read_config_dword(findev, 0x4C, &reg4c);
			reg4c &= ~0x000007FF;
			reg4c |=  0x00000040;
			reg4c |=  0x00000020;
			pci_write_config_dword(findev, 0x4C, reg4c);
			pci_dev_put(findev);
		}
	} else {
		struct pci_dev * findev = NULL;
		u8 reg41 = 0;

		findev = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
				PCI_DEVICE_ID_SERVERWORKS_CSB6, NULL);
		if (findev) {
			pci_read_config_byte(findev, 0x41, &reg41);
			reg41 &= ~0x40;
			pci_write_config_byte(findev, 0x41, reg41);
			pci_dev_put(findev);
		}
	}
	/* setup the UDMA Control register
	 *
	 * 1. clear bit 6 to enable DMA
	 * 2. enable DMA modes with bits 0-1
	 * 	00 : legacy
	 * 	01 : udma2
	 * 	10 : udma2/udma4
	 * 	11 : udma2/udma4/udma5
	 */
	pci_read_config_byte(pdev, 0x5A, &btr);
	btr &= ~0x40;
	if (!(PCI_FUNC(pdev->devfn) & 1))
		btr |= 0x2;
	else
		btr |= (rev >= SVWKS_CSB5_REVISION_NEW) ? 0x3 : 0x2;
	pci_write_config_byte(pdev, 0x5A, btr);

	return btr;
}

static void serverworks_fixup_ht1000(struct pci_dev *pdev)
{
	u8 btr;
	/* Setup HT1000 SouthBridge Controller - Single Channel Only */
	pci_read_config_byte(pdev, 0x5A, &btr);
	btr &= ~0x40;
	btr |= 0x3;
	pci_write_config_byte(pdev, 0x5A, btr);
}


static int serverworks_init_one(struct pci_dev *pdev, const struct pci_device_id *id)
{
	static const struct ata_port_info info[4] = {
		{ /* OSB4 */
			.sht = &serverworks_sht,
			.flags = ATA_FLAG_SLAVE_POSS,
			.pio_mask = 0x1f,
			.mwdma_mask = 0x07,
			.udma_mask = 0x07,
			.port_ops = &serverworks_osb4_port_ops
		}, { /* OSB4 no UDMA */
			.sht = &serverworks_sht,
			.flags = ATA_FLAG_SLAVE_POSS,
			.pio_mask = 0x1f,
			.mwdma_mask = 0x07,
			.udma_mask = 0x00,
			.port_ops = &serverworks_osb4_port_ops
		}, { /* CSB5 */
			.sht = &serverworks_sht,
			.flags = ATA_FLAG_SLAVE_POSS,
			.pio_mask = 0x1f,
			.mwdma_mask = 0x07,
			.udma_mask = ATA_UDMA4,
			.port_ops = &serverworks_csb_port_ops
		}, { /* CSB5 - later revisions*/
			.sht = &serverworks_sht,
			.flags = ATA_FLAG_SLAVE_POSS,
			.pio_mask = 0x1f,
			.mwdma_mask = 0x07,
			.udma_mask = ATA_UDMA5,
			.port_ops = &serverworks_csb_port_ops
		}
	};
	const struct ata_port_info *ppi[] = { &info[id->driver_data], NULL };

	/* Force master latency timer to 64 PCI clocks */
	pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0x40);

	/* OSB4 : South Bridge and IDE */
	if (pdev->device == PCI_DEVICE_ID_SERVERWORKS_OSB4IDE) {
		/* Select non UDMA capable OSB4 if we can't do fixups */
		if ( serverworks_fixup_osb4(pdev) < 0)
			ppi[0] = &info[1];
	}
	/* setup CSB5/CSB6 : South Bridge and IDE option RAID */
	else if ((pdev->device == PCI_DEVICE_ID_SERVERWORKS_CSB5IDE) ||
		 (pdev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE) ||
		 (pdev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2)) {

		 /* If the returned btr is the newer revision then
		    select the right info block */
		 if (serverworks_fixup_csb(pdev) == 3)
		 	ppi[0] = &info[3];

		/* Is this the 3rd channel CSB6 IDE ? */
		if (pdev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2)
			ppi[1] = &ata_dummy_port_info;
	}
	/* setup HT1000E */
	else if (pdev->device == PCI_DEVICE_ID_SERVERWORKS_HT1000IDE)
		serverworks_fixup_ht1000(pdev);

	if (pdev->device == PCI_DEVICE_ID_SERVERWORKS_CSB5IDE)
		ata_pci_clear_simplex(pdev);

	return ata_pci_init_one(pdev, ppi);
}

#ifdef CONFIG_PM
static int serverworks_reinit_one(struct pci_dev *pdev)
{
	/* Force master latency timer to 64 PCI clocks */
	pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0x40);

	switch (pdev->device)
	{
		case PCI_DEVICE_ID_SERVERWORKS_OSB4IDE:
			serverworks_fixup_osb4(pdev);
			break;
		case PCI_DEVICE_ID_SERVERWORKS_CSB5IDE:
			ata_pci_clear_simplex(pdev);
			/* fall through */
		case PCI_DEVICE_ID_SERVERWORKS_CSB6IDE:
		case PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2:
			serverworks_fixup_csb(pdev);
			break;
		case PCI_DEVICE_ID_SERVERWORKS_HT1000IDE:
			serverworks_fixup_ht1000(pdev);
			break;
	}
	return ata_pci_device_resume(pdev);
}
#endif

static const struct pci_device_id serverworks[] = {
	{ PCI_VDEVICE(SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_OSB4IDE), 0},
	{ PCI_VDEVICE(SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB5IDE), 2},
	{ PCI_VDEVICE(SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB6IDE), 2},
	{ PCI_VDEVICE(SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2), 2},
	{ PCI_VDEVICE(SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT1000IDE), 2},

	{ },
};

static struct pci_driver serverworks_pci_driver = {
	.name 		= DRV_NAME,
	.id_table	= serverworks,
	.probe 		= serverworks_init_one,
	.remove		= ata_pci_remove_one,
#ifdef CONFIG_PM
	.suspend	= ata_pci_device_suspend,
	.resume		= serverworks_reinit_one,
#endif
};

static int __init serverworks_init(void)
{
	return pci_register_driver(&serverworks_pci_driver);
}

static void __exit serverworks_exit(void)
{
	pci_unregister_driver(&serverworks_pci_driver);
}

MODULE_AUTHOR("Alan Cox");
MODULE_DESCRIPTION("low-level driver for Serverworks OSB4/CSB5/CSB6");
MODULE_LICENSE("GPL");
MODULE_DEVICE_TABLE(pci, serverworks);
MODULE_VERSION(DRV_VERSION);

module_init(serverworks_init);
module_exit(serverworks_exit);
Commit	Line	Data
669a5db4	1	/*
a0fcdc02	2	* pata_serverworks.c - Serverworks PATA for new ATA layer
669a5db4 JG	3	* (C) 2005 Red Hat Inc
	4	* Alan Cox <alan@redhat.com>
	5	*
	6	* based upon
	7	*
	8	* serverworks.c
85cd7251	9	*
669a5db4 JG	10	* Copyright (C) 1998-2000 Michel Aubry
	11	* Copyright (C) 1998-2000 Andrzej Krzysztofowicz
	12	* Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org>
	13	* Portions copyright (c) 2001 Sun Microsystems
	14	*
	15	*
	16	* RCC/ServerWorks IDE driver for Linux
	17	*
	18	* OSB4: `Open South Bridge' IDE Interface (fn 1)
	19	* supports UDMA mode 2 (33 MB/s)
	20	*
	21	* CSB5: `Champion South Bridge' IDE Interface (fn 1)
	22	* all revisions support UDMA mode 4 (66 MB/s)
	23	* revision A2.0 and up support UDMA mode 5 (100 MB/s)
	24	*
	25	* * The CSB5 does not provide ANY register *
	26	* * to detect 80-conductor cable presence. *
	27	*
	28	* CSB6: `Champion South Bridge' IDE Interface (optional: third channel)
	29	*
	30	* Documentation:
	31	* Available under NDA only. Errata info very hard to get.
	32	*/
	33
	34	#include <linux/kernel.h>
	35	#include <linux/module.h>
	36	#include <linux/pci.h>
	37	#include <linux/init.h>
	38	#include <linux/blkdev.h>
	39	#include <linux/delay.h>
	40	#include <scsi/scsi_host.h>
	41	#include <linux/libata.h>
	42
	43	#define DRV_NAME "pata_serverworks"
8bc3fc47	44	#define DRV_VERSION "0.4.1"
669a5db4 JG	45
	46	#define SVWKS_CSB5_REVISION_NEW 0x92 /* min PCI_REVISION_ID for UDMA5 (A2.0) */
	47	#define SVWKS_CSB6_REVISION 0xa0 /* min PCI_REVISION_ID for UDMA4 (A1.0) */
	48
	49	/* Seagate Barracuda ATA IV Family drives in UDMA mode 5
	50	* can overrun their FIFOs when used with the CSB5 */
	51
	52	static const char *csb_bad_ata100[] = {
	53	"ST320011A",
	54	"ST340016A",
	55	"ST360021A",
	56	"ST380021A",
	57	NULL
	58	};
	59
	60	/**
	61	* dell_cable - Dell serverworks cable detection
	62	* @ap: ATA port to do cable detect
	63	*
	64	* Dell hide the 40/80 pin select for their interfaces in the top two
85cd7251	65	* bits of the subsystem ID.
669a5db4	66	*/
85cd7251	67
669a5db4 JG	68	static int dell_cable(struct ata_port *ap) {
669a5db4 JG	69	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
85cd7251	70
669a5db4 JG	71	if (pdev->subsystem_device & (1 << (ap->port_no + 14)))
	72	return ATA_CBL_PATA80;
	73	return ATA_CBL_PATA40;
	74	}
	75
	76	/**
	77	* sun_cable - Sun Cobalt 'Alpine' cable detection
	78	* @ap: ATA port to do cable select
	79	*
	80	* Cobalt CSB5 IDE hides the 40/80pin in the top two bits of the
	81	* subsystem ID the same as dell. We could use one function but we may
	82	* need to extend the Dell one in future
	83	*/
85cd7251	84
669a5db4 JG	85	static int sun_cable(struct ata_port *ap) {
669a5db4 JG	86	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
85cd7251	87
669a5db4 JG	88	if (pdev->subsystem_device & (1 << (ap->port_no + 14)))
	89	return ATA_CBL_PATA80;
	90	return ATA_CBL_PATA40;
	91	}
	92
	93	/**
	94	* osb4_cable - OSB4 cable detect
	95	* @ap: ATA port to check
	96	*
	97	* The OSB4 isn't UDMA66 capable so this is easy
	98	*/
	99
	100	static int osb4_cable(struct ata_port *ap) {
	101	return ATA_CBL_PATA40;
	102	}
	103
	104	/**
	105	* csb4_cable - CSB5/6 cable detect
	106	* @ap: ATA port to check
	107	*
	108	* Serverworks default arrangement is to use the drive side detection
	109	* only.
	110	*/
	111
	112	static int csb_cable(struct ata_port *ap) {
	113	return ATA_CBL_PATA80;
	114	}
	115
	116	struct sv_cable_table {
	117	int device;
	118	int subvendor;
	119	int (cable_detect)(struct ata_port ap);
	120	};
	121
	122	/*
	123	* Note that we don't copy the old serverworks code because the old
	124	* code contains obvious mistakes
	125	*/
85cd7251	126
669a5db4 JG	127	static struct sv_cable_table cable_detect[] = {
	128	{ PCI_DEVICE_ID_SERVERWORKS_CSB5IDE, PCI_VENDOR_ID_DELL, dell_cable },
	129	{ PCI_DEVICE_ID_SERVERWORKS_CSB6IDE, PCI_VENDOR_ID_DELL, dell_cable },
	130	{ PCI_DEVICE_ID_SERVERWORKS_CSB5IDE, PCI_VENDOR_ID_SUN, sun_cable },
68d0d7ab	131	{ PCI_DEVICE_ID_SERVERWORKS_OSB4IDE, PCI_ANY_ID, osb4_cable },
669a5db4 JG	132	{ PCI_DEVICE_ID_SERVERWORKS_CSB5IDE, PCI_ANY_ID, csb_cable },
	133	{ PCI_DEVICE_ID_SERVERWORKS_CSB6IDE, PCI_ANY_ID, csb_cable },
	134	{ PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2, PCI_ANY_ID, csb_cable },
	135	{ PCI_DEVICE_ID_SERVERWORKS_HT1000IDE, PCI_ANY_ID, csb_cable },
	136	{ }
	137	};
	138
	139	/**
a0fcdc02	140	* serverworks_cable_detect - cable detection
669a5db4	141	* @ap: ATA port
d4b2bab4	142	* @deadline: deadline jiffies for the operation
669a5db4	143	*
85cd7251	144	* Perform cable detection according to the device and subvendor
669a5db4 JG	145	* identifications
669a5db4 JG	146	*/
85cd7251	147
d4b2bab4 TH	148	static int serverworks_cable_detect(struct ata_port *ap)
d4b2bab4 TH	149	{
669a5db4 JG	150	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	151	struct sv_cable_table *cb = cable_detect;
	152
	153	while(cb->device) {
85cd7251	154	if (cb->device == pdev->device &&
669a5db4 JG	155	(cb->subvendor == pdev->subsystem_vendor \|\|
669a5db4 JG	156	cb->subvendor == PCI_ANY_ID)) {
a0fcdc02	157	return cb->cable_detect(ap);
669a5db4 JG	158	}
	159	cb++;
	160	}
	161
	162	BUG();
	163	return -1; /* kill compiler warning */
	164	}
	165
669a5db4 JG	166	/**
	167	* serverworks_is_csb - Check for CSB or OSB
	168	* @pdev: PCI device to check
	169	*
	170	* Returns true if the device being checked is known to be a CSB
	171	* series device.
	172	*/
85cd7251	173
669a5db4 JG	174	static u8 serverworks_is_csb(struct pci_dev *pdev)
	175	{
	176	switch (pdev->device) {
	177	case PCI_DEVICE_ID_SERVERWORKS_CSB5IDE:
	178	case PCI_DEVICE_ID_SERVERWORKS_CSB6IDE:
	179	case PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2:
	180	case PCI_DEVICE_ID_SERVERWORKS_HT1000IDE:
	181	return 1;
	182	default:
	183	break;
	184	}
	185	return 0;
	186	}
	187
	188	/**
	189	* serverworks_osb4_filter - mode selection filter
669a5db4	190	* @adev: ATA device
a76b62ca	191	* @mask: Mask of proposed modes
669a5db4 JG	192	*
	193	* Filter the offered modes for the device to apply controller
	194	* specific rules. OSB4 requires no UDMA for disks due to a FIFO
	195	* bug we hit.
	196	*/
85cd7251	197
a76b62ca	198	static unsigned long serverworks_osb4_filter(struct ata_device *adev, unsigned long mask)
669a5db4 JG	199	{
	200	if (adev->class == ATA_DEV_ATA)
	201	mask &= ~ATA_MASK_UDMA;
a76b62ca	202	return ata_pci_default_filter(adev, mask);
669a5db4 JG	203	}
	204
	205
	206	/**
	207	* serverworks_csb_filter - mode selection filter
669a5db4	208	* @adev: ATA device
a76b62ca	209	* @mask: Mask of proposed modes
669a5db4 JG	210	*
	211	* Check the blacklist and disable UDMA5 if matched
	212	*/
	213
a76b62ca	214	static unsigned long serverworks_csb_filter(struct ata_device *adev, unsigned long mask)
669a5db4 JG	215	{
669a5db4 JG	216	const char *p;
8bfa79fc TH	217	char model_num[ATA_ID_PROD_LEN + 1];
8bfa79fc TH	218	int i;
669a5db4	219
85cd7251	220	/* Disk, UDMA */
669a5db4	221	if (adev->class != ATA_DEV_ATA)
a76b62ca	222	return ata_pci_default_filter(adev, mask);
669a5db4 JG	223
669a5db4 JG	224	/* Actually do need to check */
8bfa79fc	225	ata_id_c_string(adev->id, model_num, ATA_ID_PROD, sizeof(model_num));
85cd7251	226
8bfa79fc TH	227	for (i = 0; (p = csb_bad_ata100[i]) != NULL; i++) {
8bfa79fc TH	228	if (!strcmp(p, model_num))
669a5db4 JG	229	mask &= ~(0x1F << ATA_SHIFT_UDMA);
669a5db4 JG	230	}
a76b62ca	231	return ata_pci_default_filter(adev, mask);
669a5db4 JG	232	}
	233
	234
	235	/**
	236	* serverworks_set_piomode - set initial PIO mode data
	237	* @ap: ATA interface
	238	* @adev: ATA device
	239	*
	240	* Program the OSB4/CSB5 timing registers for PIO. The PIO register
	241	* load is done as a simple lookup.
	242	*/
	243	static void serverworks_set_piomode(struct ata_port ap, struct ata_device adev)
	244	{
	245	static const u8 pio_mode[] = { 0x5d, 0x47, 0x34, 0x22, 0x20 };
	246	int offset = 1 + (2 * ap->port_no) - adev->devno;
	247	int devbits = (2 * ap->port_no + adev->devno) * 4;
	248	u16 csb5_pio;
	249	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	250	int pio = adev->pio_mode - XFER_PIO_0;
	251
	252	pci_write_config_byte(pdev, 0x40 + offset, pio_mode[pio]);
85cd7251	253
669a5db4 JG	254	/* The OSB4 just requires the timing but the CSB series want the
	255	mode number as well */
	256	if (serverworks_is_csb(pdev)) {
	257	pci_read_config_word(pdev, 0x4A, &csb5_pio);
	258	csb5_pio &= ~(0x0F << devbits);
	259	pci_write_config_byte(pdev, 0x4A, csb5_pio \| (pio << devbits));
	260	}
	261	}
	262
	263	/**
	264	* serverworks_set_dmamode - set initial DMA mode data
	265	* @ap: ATA interface
	266	* @adev: ATA device
	267	*
	268	* Program the MWDMA/UDMA modes for the serverworks OSB4/CSB5
	269	* chipset. The MWDMA mode values are pulled from a lookup table
	270	* while the chipset uses mode number for UDMA.
	271	*/
	272
	273	static void serverworks_set_dmamode(struct ata_port ap, struct ata_device adev)
	274	{
	275	static const u8 dma_mode[] = { 0x77, 0x21, 0x20 };
	276	int offset = 1 + 2 * ap->port_no - adev->devno;
	277	int devbits = (2 * ap->port_no + adev->devno);
	278	u8 ultra;
	279	u8 ultra_cfg;
	280	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	281
	282	pci_read_config_byte(pdev, 0x54, &ultra_cfg);
	283
	284	if (adev->dma_mode >= XFER_UDMA_0) {
	285	pci_write_config_byte(pdev, 0x44 + offset, 0x20);
	286
	287	pci_read_config_byte(pdev, 0x56 + ap->port_no, &ultra);
	288	ultra &= ~(0x0F << (ap->port_no * 4));
	289	ultra \|= (adev->dma_mode - XFER_UDMA_0)
	290	<< (ap->port_no * 4);
	291	pci_write_config_byte(pdev, 0x56 + ap->port_no, ultra);
	292
	293	ultra_cfg \|= (1 << devbits);
	294	} else {
85cd7251	295	pci_write_config_byte(pdev, 0x44 + offset,
669a5db4 JG	296	dma_mode[adev->dma_mode - XFER_MW_DMA_0]);
	297	ultra_cfg &= ~(1 << devbits);
	298	}
	299	pci_write_config_byte(pdev, 0x54, ultra_cfg);
	300	}
	301
	302	static struct scsi_host_template serverworks_sht = {
	303	.module = THIS_MODULE,
	304	.name = DRV_NAME,
	305	.ioctl = ata_scsi_ioctl,
	306	.queuecommand = ata_scsi_queuecmd,
	307	.can_queue = ATA_DEF_QUEUE,
	308	.this_id = ATA_SHT_THIS_ID,
	309	.sg_tablesize = LIBATA_MAX_PRD,
669a5db4 JG	310	.cmd_per_lun = ATA_SHT_CMD_PER_LUN,
	311	.emulated = ATA_SHT_EMULATED,
	312	.use_clustering = ATA_SHT_USE_CLUSTERING,
	313	.proc_name = DRV_NAME,
	314	.dma_boundary = ATA_DMA_BOUNDARY,
	315	.slave_configure = ata_scsi_slave_config,
afdfe899	316	.slave_destroy = ata_scsi_slave_destroy,
669a5db4 JG	317	.bios_param = ata_std_bios_param,
	318	};
	319
	320	static struct ata_port_operations serverworks_osb4_port_ops = {
	321	.port_disable = ata_port_disable,
	322	.set_piomode = serverworks_set_piomode,
	323	.set_dmamode = serverworks_set_dmamode,
	324	.mode_filter = serverworks_osb4_filter,
85cd7251	325
669a5db4 JG	326	.tf_load = ata_tf_load,
	327	.tf_read = ata_tf_read,
	328	.check_status = ata_check_status,
	329	.exec_command = ata_exec_command,
	330	.dev_select = ata_std_dev_select,
	331
	332	.freeze = ata_bmdma_freeze,
	333	.thaw = ata_bmdma_thaw,
a0fcdc02	334	.error_handler = ata_bmdma_error_handler,
669a5db4	335	.post_internal_cmd = ata_bmdma_post_internal_cmd,
a0fcdc02	336	.cable_detect = serverworks_cable_detect,
669a5db4 JG	337
	338	.bmdma_setup = ata_bmdma_setup,
	339	.bmdma_start = ata_bmdma_start,
	340	.bmdma_stop = ata_bmdma_stop,
	341	.bmdma_status = ata_bmdma_status,
	342
	343	.qc_prep = ata_qc_prep,
	344	.qc_issue = ata_qc_issue_prot,
bda30288	345
0d5ff566	346	.data_xfer = ata_data_xfer,
85cd7251	347
669a5db4	348	.irq_handler = ata_interrupt,
efbf3f14	349	.irq_clear = ata_bmdma_irq_clear,
246ce3b6 AI	350	.irq_on = ata_irq_on,
246ce3b6 AI	351	.irq_ack = ata_irq_ack,
efbf3f14	352
669a5db4	353	.port_start = ata_port_start,
85cd7251	354	};
669a5db4 JG	355
	356	static struct ata_port_operations serverworks_csb_port_ops = {
	357	.port_disable = ata_port_disable,
	358	.set_piomode = serverworks_set_piomode,
	359	.set_dmamode = serverworks_set_dmamode,
	360	.mode_filter = serverworks_csb_filter,
85cd7251	361
669a5db4 JG	362	.tf_load = ata_tf_load,
	363	.tf_read = ata_tf_read,
	364	.check_status = ata_check_status,
	365	.exec_command = ata_exec_command,
	366	.dev_select = ata_std_dev_select,
	367
	368	.freeze = ata_bmdma_freeze,
	369	.thaw = ata_bmdma_thaw,
a0fcdc02	370	.error_handler = ata_bmdma_error_handler,
669a5db4	371	.post_internal_cmd = ata_bmdma_post_internal_cmd,
a0fcdc02	372	.cable_detect = serverworks_cable_detect,
669a5db4 JG	373
	374	.bmdma_setup = ata_bmdma_setup,
	375	.bmdma_start = ata_bmdma_start,
	376	.bmdma_stop = ata_bmdma_stop,
	377	.bmdma_status = ata_bmdma_status,
	378
	379	.qc_prep = ata_qc_prep,
	380	.qc_issue = ata_qc_issue_prot,
bda30288	381
0d5ff566	382	.data_xfer = ata_data_xfer,
85cd7251	383
669a5db4	384	.irq_handler = ata_interrupt,
efbf3f14	385	.irq_clear = ata_bmdma_irq_clear,
246ce3b6 AI	386	.irq_on = ata_irq_on,
246ce3b6 AI	387	.irq_ack = ata_irq_ack,
efbf3f14	388
669a5db4	389	.port_start = ata_port_start,
85cd7251	390	};
669a5db4 JG	391
	392	static int serverworks_fixup_osb4(struct pci_dev *pdev)
	393	{
	394	u32 reg;
	395	struct pci_dev *isa_dev = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
	396	PCI_DEVICE_ID_SERVERWORKS_OSB4, NULL);
	397	if (isa_dev) {
	398	pci_read_config_dword(isa_dev, 0x64, &reg);
	399	reg &= ~0x00002000; /* disable 600ns interrupt mask */
	400	if (!(reg & 0x00004000))
	401	printk(KERN_DEBUG DRV_NAME ": UDMA not BIOS enabled.\n");
	402	reg \|= 0x00004000; /* enable UDMA/33 support */
	403	pci_write_config_dword(isa_dev, 0x64, reg);
	404	pci_dev_put(isa_dev);
	405	return 0;
	406	}
	407	printk(KERN_WARNING "ata_serverworks: Unable to find bridge.\n");
	408	return -ENODEV;
	409	}
	410
	411	static int serverworks_fixup_csb(struct pci_dev *pdev)
	412	{
	413	u8 rev;
	414	u8 btr;
85cd7251	415
669a5db4 JG	416	pci_read_config_byte(pdev, PCI_REVISION_ID, &rev);
	417
	418	/* Third Channel Test */
	419	if (!(PCI_FUNC(pdev->devfn) & 1)) {
	420	struct pci_dev * findev = NULL;
	421	u32 reg4c = 0;
	422	findev = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
	423	PCI_DEVICE_ID_SERVERWORKS_CSB5, NULL);
	424	if (findev) {
	425	pci_read_config_dword(findev, 0x4C, &reg4c);
	426	reg4c &= ~0x000007FF;
	427	reg4c \|= 0x00000040;
	428	reg4c \|= 0x00000020;
	429	pci_write_config_dword(findev, 0x4C, reg4c);
	430	pci_dev_put(findev);
	431	}
	432	} else {
	433	struct pci_dev * findev = NULL;
	434	u8 reg41 = 0;
	435
	436	findev = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
	437	PCI_DEVICE_ID_SERVERWORKS_CSB6, NULL);
	438	if (findev) {
	439	pci_read_config_byte(findev, 0x41, &reg41);
	440	reg41 &= ~0x40;
	441	pci_write_config_byte(findev, 0x41, reg41);
	442	pci_dev_put(findev);
	443	}
	444	}
	445	/* setup the UDMA Control register
	446	*
	447	* 1. clear bit 6 to enable DMA
	448	* 2. enable DMA modes with bits 0-1
	449	* 00 : legacy
	450	* 01 : udma2
	451	* 10 : udma2/udma4
	452	* 11 : udma2/udma4/udma5
	453	*/
	454	pci_read_config_byte(pdev, 0x5A, &btr);
	455	btr &= ~0x40;
	456	if (!(PCI_FUNC(pdev->devfn) & 1))
	457	btr \|= 0x2;
	458	else
	459	btr \|= (rev >= SVWKS_CSB5_REVISION_NEW) ? 0x3 : 0x2;
	460	pci_write_config_byte(pdev, 0x5A, btr);
85cd7251	461
669a5db4 JG	462	return btr;
	463	}
	464
	465	static void serverworks_fixup_ht1000(struct pci_dev *pdev)
	466	{
	467	u8 btr;
	468	/* Setup HT1000 SouthBridge Controller - Single Channel Only */
	469	pci_read_config_byte(pdev, 0x5A, &btr);
	470	btr &= ~0x40;
	471	btr \|= 0x3;
	472	pci_write_config_byte(pdev, 0x5A, btr);
	473	}
	474
	475
	476	static int serverworks_init_one(struct pci_dev pdev, const struct pci_device_id id)
	477	{
1626aeb8	478	static const struct ata_port_info info[4] = {
669a5db4 JG	479	{ /* OSB4 */
669a5db4 JG	480	.sht = &serverworks_sht,
1d2808fd	481	.flags = ATA_FLAG_SLAVE_POSS,
669a5db4 JG	482	.pio_mask = 0x1f,
	483	.mwdma_mask = 0x07,
	484	.udma_mask = 0x07,
	485	.port_ops = &serverworks_osb4_port_ops
	486	}, { /* OSB4 no UDMA */
	487	.sht = &serverworks_sht,
1d2808fd	488	.flags = ATA_FLAG_SLAVE_POSS,
669a5db4 JG	489	.pio_mask = 0x1f,
	490	.mwdma_mask = 0x07,
	491	.udma_mask = 0x00,
	492	.port_ops = &serverworks_osb4_port_ops
	493	}, { /* CSB5 */
	494	.sht = &serverworks_sht,
1d2808fd	495	.flags = ATA_FLAG_SLAVE_POSS,
669a5db4 JG	496	.pio_mask = 0x1f,
669a5db4 JG	497	.mwdma_mask = 0x07,
bf6263a8	498	.udma_mask = ATA_UDMA4,
669a5db4 JG	499	.port_ops = &serverworks_csb_port_ops
	500	}, { /* CSB5 - later revisions*/
	501	.sht = &serverworks_sht,
1d2808fd	502	.flags = ATA_FLAG_SLAVE_POSS,
669a5db4 JG	503	.pio_mask = 0x1f,
669a5db4 JG	504	.mwdma_mask = 0x07,
bf6263a8	505	.udma_mask = ATA_UDMA5,
669a5db4 JG	506	.port_ops = &serverworks_csb_port_ops
	507	}
	508	};
1626aeb8	509	const struct ata_port_info *ppi[] = { &info[id->driver_data], NULL };
85cd7251	510
669a5db4 JG	511	/* Force master latency timer to 64 PCI clocks */
	512	pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0x40);
	513
	514	/* OSB4 : South Bridge and IDE */
	515	if (pdev->device == PCI_DEVICE_ID_SERVERWORKS_OSB4IDE) {
	516	/* Select non UDMA capable OSB4 if we can't do fixups */
	517	if ( serverworks_fixup_osb4(pdev) < 0)
1626aeb8	518	ppi[0] = &info[1];
669a5db4 JG	519	}
	520	/* setup CSB5/CSB6 : South Bridge and IDE option RAID */
	521	else if ((pdev->device == PCI_DEVICE_ID_SERVERWORKS_CSB5IDE) \|\|
	522	(pdev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE) \|\|
	523	(pdev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2)) {
85cd7251	524
669a5db4 JG	525	/* If the returned btr is the newer revision then
	526	select the right info block */
	527	if (serverworks_fixup_csb(pdev) == 3)
1626aeb8	528	ppi[0] = &info[3];
85cd7251	529
669a5db4 JG	530	/* Is this the 3rd channel CSB6 IDE ? */
669a5db4 JG	531	if (pdev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2)
1626aeb8	532	ppi[1] = &ata_dummy_port_info;
669a5db4 JG	533	}
	534	/* setup HT1000E */
	535	else if (pdev->device == PCI_DEVICE_ID_SERVERWORKS_HT1000IDE)
	536	serverworks_fixup_ht1000(pdev);
85cd7251	537
669a5db4 JG	538	if (pdev->device == PCI_DEVICE_ID_SERVERWORKS_CSB5IDE)
669a5db4 JG	539	ata_pci_clear_simplex(pdev);
85cd7251	540
1626aeb8	541	return ata_pci_init_one(pdev, ppi);
669a5db4 JG	542	}
669a5db4 JG	543
438ac6d5	544	#ifdef CONFIG_PM
38e0d56e A	545	static int serverworks_reinit_one(struct pci_dev *pdev)
	546	{
	547	/* Force master latency timer to 64 PCI clocks */
	548	pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0x40);
f20b16ff	549
38e0d56e A	550	switch (pdev->device)
	551	{
	552	case PCI_DEVICE_ID_SERVERWORKS_OSB4IDE:
	553	serverworks_fixup_osb4(pdev);
	554	break;
	555	case PCI_DEVICE_ID_SERVERWORKS_CSB5IDE:
	556	ata_pci_clear_simplex(pdev);
	557	/* fall through */
	558	case PCI_DEVICE_ID_SERVERWORKS_CSB6IDE:
	559	case PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2:
	560	serverworks_fixup_csb(pdev);
	561	break;
	562	case PCI_DEVICE_ID_SERVERWORKS_HT1000IDE:
	563	serverworks_fixup_ht1000(pdev);
	564	break;
	565	}
	566	return ata_pci_device_resume(pdev);
	567	}
438ac6d5	568	#endif
38e0d56e	569
2d2744fc JG	570	static const struct pci_device_id serverworks[] = {
	571	{ PCI_VDEVICE(SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_OSB4IDE), 0},
	572	{ PCI_VDEVICE(SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB5IDE), 2},
	573	{ PCI_VDEVICE(SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB6IDE), 2},
	574	{ PCI_VDEVICE(SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2), 2},
	575	{ PCI_VDEVICE(SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT1000IDE), 2},
	576
	577	{ },
669a5db4 JG	578	};
	579
	580	static struct pci_driver serverworks_pci_driver = {
	581	.name = DRV_NAME,
	582	.id_table = serverworks,
	583	.probe = serverworks_init_one,
38e0d56e	584	.remove = ata_pci_remove_one,
438ac6d5	585	#ifdef CONFIG_PM
38e0d56e A	586	.suspend = ata_pci_device_suspend,
38e0d56e A	587	.resume = serverworks_reinit_one,
438ac6d5	588	#endif
669a5db4 JG	589	};
	590
	591	static int __init serverworks_init(void)
	592	{
	593	return pci_register_driver(&serverworks_pci_driver);
	594	}
	595
669a5db4 JG	596	static void __exit serverworks_exit(void)
	597	{
	598	pci_unregister_driver(&serverworks_pci_driver);
	599	}
	600
669a5db4 JG	601	MODULE_AUTHOR("Alan Cox");
	602	MODULE_DESCRIPTION("low-level driver for Serverworks OSB4/CSB5/CSB6");
	603	MODULE_LICENSE("GPL");
	604	MODULE_DEVICE_TABLE(pci, serverworks);
	605	MODULE_VERSION(DRV_VERSION);
	606
	607	module_init(serverworks_init);
	608	module_exit(serverworks_exit);