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669a5db4 JG |
1 | /* |
2 | * pata_sis.c - SiS ATA driver | |
3 | * | |
4 | * (C) 2005 Red Hat <alan@redhat.com> | |
5 | * | |
6 | * Based upon linux/drivers/ide/pci/sis5513.c | |
7 | * Copyright (C) 1999-2000 Andre Hedrick <andre@linux-ide.org> | |
8 | * Copyright (C) 2002 Lionel Bouton <Lionel.Bouton@inet6.fr>, Maintainer | |
9 | * Copyright (C) 2003 Vojtech Pavlik <vojtech@suse.cz> | |
10 | * SiS Taiwan : for direct support and hardware. | |
11 | * Daniela Engert : for initial ATA100 advices and numerous others. | |
12 | * John Fremlin, Manfred Spraul, Dave Morgan, Peter Kjellerstedt : | |
13 | * for checking code correctness, providing patches. | |
14 | * Original tests and design on the SiS620 chipset. | |
15 | * ATA100 tests and design on the SiS735 chipset. | |
16 | * ATA16/33 support from specs | |
17 | * ATA133 support for SiS961/962 by L.C. Chang <lcchang@sis.com.tw> | |
18 | * | |
19 | * | |
20 | * TODO | |
21 | * Check MWDMA on drives that don't support MWDMA speed pio cycles ? | |
22 | * More Testing | |
23 | */ | |
24 | ||
25 | #include <linux/kernel.h> | |
26 | #include <linux/module.h> | |
27 | #include <linux/pci.h> | |
28 | #include <linux/init.h> | |
29 | #include <linux/blkdev.h> | |
30 | #include <linux/delay.h> | |
31 | #include <linux/device.h> | |
32 | #include <scsi/scsi_host.h> | |
33 | #include <linux/libata.h> | |
34 | #include <linux/ata.h> | |
35 | ||
36 | #define DRV_NAME "pata_sis" | |
37 | #define DRV_VERSION "0.4.2" | |
38 | ||
39 | struct sis_chipset { | |
40 | u16 device; /* PCI host ID */ | |
41 | struct ata_port_info *info; /* Info block */ | |
42 | /* Probably add family, cable detect type etc here to clean | |
43 | up code later */ | |
44 | }; | |
45 | ||
46 | /** | |
47 | * sis_port_base - return PCI configuration base for dev | |
48 | * @adev: device | |
49 | * | |
50 | * Returns the base of the PCI configuration registers for this port | |
51 | * number. | |
52 | */ | |
53 | ||
54 | static int sis_port_base(struct ata_device *adev) | |
55 | { | |
56 | return 0x40 + (4 * adev->ap->port_no) + (2 * adev->devno); | |
57 | } | |
58 | ||
59 | /** | |
60 | * sis_133_pre_reset - check for 40/80 pin | |
61 | * @ap: Port | |
62 | * | |
63 | * Perform cable detection for the later UDMA133 capable | |
64 | * SiS chipset. | |
65 | */ | |
66 | ||
67 | static int sis_133_pre_reset(struct ata_port *ap) | |
68 | { | |
69 | static const struct pci_bits sis_enable_bits[] = { | |
70 | { 0x4aU, 1U, 0x02UL, 0x02UL }, /* port 0 */ | |
71 | { 0x4aU, 1U, 0x04UL, 0x04UL }, /* port 1 */ | |
72 | }; | |
73 | ||
74 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); | |
75 | u16 tmp; | |
76 | ||
77 | if (!pci_test_config_bits(pdev, &sis_enable_bits[ap->port_no])) { | |
78 | ata_port_disable(ap); | |
79 | printk(KERN_INFO "ata%u: port disabled. ignoring.\n", ap->id); | |
80 | return 0; | |
81 | } | |
82 | /* The top bit of this register is the cable detect bit */ | |
83 | pci_read_config_word(pdev, 0x50 + 2 * ap->port_no, &tmp); | |
84 | if (tmp & 0x8000) | |
85 | ap->cbl = ATA_CBL_PATA40; | |
86 | else | |
87 | ap->cbl = ATA_CBL_PATA80; | |
88 | ||
89 | return ata_std_prereset(ap); | |
90 | } | |
91 | ||
92 | /** | |
93 | * sis_error_handler - Probe specified port on PATA host controller | |
94 | * @ap: Port to probe | |
95 | * | |
96 | * LOCKING: | |
97 | * None (inherited from caller). | |
98 | */ | |
99 | ||
100 | static void sis_133_error_handler(struct ata_port *ap) | |
101 | { | |
102 | ata_bmdma_drive_eh(ap, sis_133_pre_reset, ata_std_softreset, NULL, ata_std_postreset); | |
103 | } | |
104 | ||
105 | ||
106 | /** | |
107 | * sis_66_pre_reset - check for 40/80 pin | |
108 | * @ap: Port | |
109 | * | |
110 | * Perform cable detection on the UDMA66, UDMA100 and early UDMA133 | |
111 | * SiS IDE controllers. | |
112 | */ | |
113 | ||
114 | static int sis_66_pre_reset(struct ata_port *ap) | |
115 | { | |
116 | static const struct pci_bits sis_enable_bits[] = { | |
117 | { 0x4aU, 1U, 0x02UL, 0x02UL }, /* port 0 */ | |
118 | { 0x4aU, 1U, 0x04UL, 0x04UL }, /* port 1 */ | |
119 | }; | |
120 | ||
121 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); | |
122 | u8 tmp; | |
123 | ||
124 | if (!pci_test_config_bits(pdev, &sis_enable_bits[ap->port_no])) { | |
125 | ata_port_disable(ap); | |
126 | printk(KERN_INFO "ata%u: port disabled. ignoring.\n", ap->id); | |
127 | return 0; | |
128 | } | |
129 | /* Older chips keep cable detect in bits 4/5 of reg 0x48 */ | |
130 | pci_read_config_byte(pdev, 0x48, &tmp); | |
131 | tmp >>= ap->port_no; | |
132 | if (tmp & 0x10) | |
133 | ap->cbl = ATA_CBL_PATA40; | |
134 | else | |
135 | ap->cbl = ATA_CBL_PATA80; | |
136 | ||
137 | return ata_std_prereset(ap); | |
138 | } | |
139 | ||
140 | /** | |
141 | * sis_66_error_handler - Probe specified port on PATA host controller | |
142 | * @ap: Port to probe | |
143 | * @classes: | |
144 | * | |
145 | * LOCKING: | |
146 | * None (inherited from caller). | |
147 | */ | |
148 | ||
149 | static void sis_66_error_handler(struct ata_port *ap) | |
150 | { | |
151 | ata_bmdma_drive_eh(ap, sis_66_pre_reset, ata_std_softreset, NULL, ata_std_postreset); | |
152 | } | |
153 | ||
154 | /** | |
155 | * sis_old_pre_reset - probe begin | |
156 | * @ap: ATA port | |
157 | * | |
158 | * Set up cable type and use generic probe init | |
159 | */ | |
160 | ||
161 | static int sis_old_pre_reset(struct ata_port *ap) | |
162 | { | |
163 | static const struct pci_bits sis_enable_bits[] = { | |
164 | { 0x4aU, 1U, 0x02UL, 0x02UL }, /* port 0 */ | |
165 | { 0x4aU, 1U, 0x04UL, 0x04UL }, /* port 1 */ | |
166 | }; | |
167 | ||
168 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); | |
169 | ||
170 | if (!pci_test_config_bits(pdev, &sis_enable_bits[ap->port_no])) { | |
171 | ata_port_disable(ap); | |
172 | printk(KERN_INFO "ata%u: port disabled. ignoring.\n", ap->id); | |
173 | return 0; | |
174 | } | |
175 | ap->cbl = ATA_CBL_PATA40; | |
176 | return ata_std_prereset(ap); | |
177 | } | |
178 | ||
179 | ||
180 | /** | |
181 | * sis_old_error_handler - Probe specified port on PATA host controller | |
182 | * @ap: Port to probe | |
183 | * | |
184 | * LOCKING: | |
185 | * None (inherited from caller). | |
186 | */ | |
187 | ||
188 | static void sis_old_error_handler(struct ata_port *ap) | |
189 | { | |
190 | ata_bmdma_drive_eh(ap, sis_old_pre_reset, ata_std_softreset, NULL, ata_std_postreset); | |
191 | } | |
192 | ||
193 | /** | |
194 | * sis_set_fifo - Set RWP fifo bits for this device | |
195 | * @ap: Port | |
196 | * @adev: Device | |
197 | * | |
198 | * SIS chipsets implement prefetch/postwrite bits for each device | |
199 | * on both channels. This functionality is not ATAPI compatible and | |
200 | * must be configured according to the class of device present | |
201 | */ | |
202 | ||
203 | static void sis_set_fifo(struct ata_port *ap, struct ata_device *adev) | |
204 | { | |
205 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); | |
206 | u8 fifoctrl; | |
207 | u8 mask = 0x11; | |
208 | ||
209 | mask <<= (2 * ap->port_no); | |
210 | mask <<= adev->devno; | |
211 | ||
212 | /* This holds various bits including the FIFO control */ | |
213 | pci_read_config_byte(pdev, 0x4B, &fifoctrl); | |
214 | fifoctrl &= ~mask; | |
215 | ||
216 | /* Enable for ATA (disk) only */ | |
217 | if (adev->class == ATA_DEV_ATA) | |
218 | fifoctrl |= mask; | |
219 | pci_write_config_byte(pdev, 0x4B, fifoctrl); | |
220 | } | |
221 | ||
222 | /** | |
223 | * sis_old_set_piomode - Initialize host controller PATA PIO timings | |
224 | * @ap: Port whose timings we are configuring | |
225 | * @adev: Device we are configuring for. | |
226 | * | |
227 | * Set PIO mode for device, in host controller PCI config space. This | |
228 | * function handles PIO set up for all chips that are pre ATA100 and | |
229 | * also early ATA100 devices. | |
230 | * | |
231 | * LOCKING: | |
232 | * None (inherited from caller). | |
233 | */ | |
234 | ||
235 | static void sis_old_set_piomode (struct ata_port *ap, struct ata_device *adev) | |
236 | { | |
237 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); | |
238 | int port = sis_port_base(adev); | |
239 | u8 t1, t2; | |
240 | int speed = adev->pio_mode - XFER_PIO_0; | |
241 | ||
242 | const u8 active[] = { 0x00, 0x07, 0x04, 0x03, 0x01 }; | |
243 | const u8 recovery[] = { 0x00, 0x06, 0x04, 0x03, 0x03 }; | |
244 | ||
245 | sis_set_fifo(ap, adev); | |
246 | ||
247 | pci_read_config_byte(pdev, port, &t1); | |
248 | pci_read_config_byte(pdev, port + 1, &t2); | |
249 | ||
250 | t1 &= ~0x0F; /* Clear active/recovery timings */ | |
251 | t2 &= ~0x07; | |
252 | ||
253 | t1 |= active[speed]; | |
254 | t2 |= recovery[speed]; | |
255 | ||
256 | pci_write_config_byte(pdev, port, t1); | |
257 | pci_write_config_byte(pdev, port + 1, t2); | |
258 | } | |
259 | ||
260 | /** | |
261 | * sis_100_set_pioode - Initialize host controller PATA PIO timings | |
262 | * @ap: Port whose timings we are configuring | |
263 | * @adev: Device we are configuring for. | |
264 | * | |
265 | * Set PIO mode for device, in host controller PCI config space. This | |
266 | * function handles PIO set up for ATA100 devices and early ATA133. | |
267 | * | |
268 | * LOCKING: | |
269 | * None (inherited from caller). | |
270 | */ | |
271 | ||
272 | static void sis_100_set_piomode (struct ata_port *ap, struct ata_device *adev) | |
273 | { | |
274 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); | |
275 | int port = sis_port_base(adev); | |
276 | int speed = adev->pio_mode - XFER_PIO_0; | |
277 | ||
278 | const u8 actrec[] = { 0x00, 0x67, 0x44, 0x33, 0x31 }; | |
279 | ||
280 | sis_set_fifo(ap, adev); | |
281 | ||
282 | pci_write_config_byte(pdev, port, actrec[speed]); | |
283 | } | |
284 | ||
285 | /** | |
286 | * sis_133_set_pioode - Initialize host controller PATA PIO timings | |
287 | * @ap: Port whose timings we are configuring | |
288 | * @adev: Device we are configuring for. | |
289 | * | |
290 | * Set PIO mode for device, in host controller PCI config space. This | |
291 | * function handles PIO set up for the later ATA133 devices. | |
292 | * | |
293 | * LOCKING: | |
294 | * None (inherited from caller). | |
295 | */ | |
296 | ||
297 | static void sis_133_set_piomode (struct ata_port *ap, struct ata_device *adev) | |
298 | { | |
299 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); | |
300 | int port = 0x40; | |
301 | u32 t1; | |
302 | u32 reg54; | |
303 | int speed = adev->pio_mode - XFER_PIO_0; | |
304 | ||
305 | const u32 timing133[] = { | |
306 | 0x28269000, /* Recovery << 24 | Act << 16 | Ini << 12 */ | |
307 | 0x0C266000, | |
308 | 0x04263000, | |
309 | 0x0C0A3000, | |
310 | 0x05093000 | |
311 | }; | |
312 | const u32 timing100[] = { | |
313 | 0x1E1C6000, /* Recovery << 24 | Act << 16 | Ini << 12 */ | |
314 | 0x091C4000, | |
315 | 0x031C2000, | |
316 | 0x09072000, | |
317 | 0x04062000 | |
318 | }; | |
319 | ||
320 | sis_set_fifo(ap, adev); | |
321 | ||
322 | /* If bit 14 is set then the registers are mapped at 0x70 not 0x40 */ | |
323 | pci_read_config_dword(pdev, 0x54, ®54); | |
324 | if (reg54 & 0x40000000) | |
325 | port = 0x70; | |
326 | port += 8 * ap->port_no + 4 * adev->devno; | |
327 | ||
328 | pci_read_config_dword(pdev, port, &t1); | |
329 | t1 &= 0xC0C00FFF; /* Mask out timing */ | |
330 | ||
331 | if (t1 & 0x08) /* 100 or 133 ? */ | |
332 | t1 |= timing133[speed]; | |
333 | else | |
334 | t1 |= timing100[speed]; | |
335 | pci_write_config_byte(pdev, port, t1); | |
336 | } | |
337 | ||
338 | /** | |
339 | * sis_old_set_dmamode - Initialize host controller PATA DMA timings | |
340 | * @ap: Port whose timings we are configuring | |
341 | * @adev: Device to program | |
342 | * | |
343 | * Set UDMA/MWDMA mode for device, in host controller PCI config space. | |
344 | * Handles pre UDMA and UDMA33 devices. Supports MWDMA as well unlike | |
345 | * the old ide/pci driver. | |
346 | * | |
347 | * LOCKING: | |
348 | * None (inherited from caller). | |
349 | */ | |
350 | ||
351 | static void sis_old_set_dmamode (struct ata_port *ap, struct ata_device *adev) | |
352 | { | |
353 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); | |
354 | int speed = adev->dma_mode - XFER_MW_DMA_0; | |
355 | int drive_pci = sis_port_base(adev); | |
356 | u16 timing; | |
357 | ||
358 | const u16 mwdma_bits[] = { 0x707, 0x202, 0x202 }; | |
359 | const u16 udma_bits[] = { 0xE000, 0xC000, 0xA000 }; | |
360 | ||
361 | pci_read_config_word(pdev, drive_pci, &timing); | |
362 | ||
363 | if (adev->dma_mode < XFER_UDMA_0) { | |
364 | /* bits 3-0 hold recovery timing bits 8-10 active timing and | |
365 | the higer bits are dependant on the device */ | |
366 | timing &= ~ 0x870F; | |
367 | timing |= mwdma_bits[speed]; | |
368 | pci_write_config_word(pdev, drive_pci, timing); | |
369 | } else { | |
370 | /* Bit 15 is UDMA on/off, bit 13-14 are cycle time */ | |
371 | speed = adev->dma_mode - XFER_UDMA_0; | |
372 | timing &= ~0x6000; | |
373 | timing |= udma_bits[speed]; | |
374 | } | |
375 | } | |
376 | ||
377 | /** | |
378 | * sis_66_set_dmamode - Initialize host controller PATA DMA timings | |
379 | * @ap: Port whose timings we are configuring | |
380 | * @adev: Device to program | |
381 | * | |
382 | * Set UDMA/MWDMA mode for device, in host controller PCI config space. | |
383 | * Handles UDMA66 and early UDMA100 devices. Supports MWDMA as well unlike | |
384 | * the old ide/pci driver. | |
385 | * | |
386 | * LOCKING: | |
387 | * None (inherited from caller). | |
388 | */ | |
389 | ||
390 | static void sis_66_set_dmamode (struct ata_port *ap, struct ata_device *adev) | |
391 | { | |
392 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); | |
393 | int speed = adev->dma_mode - XFER_MW_DMA_0; | |
394 | int drive_pci = sis_port_base(adev); | |
395 | u16 timing; | |
396 | ||
397 | const u16 mwdma_bits[] = { 0x707, 0x202, 0x202 }; | |
398 | const u16 udma_bits[] = { 0xF000, 0xD000, 0xB000, 0xA000, 0x9000}; | |
399 | ||
400 | pci_read_config_word(pdev, drive_pci, &timing); | |
401 | ||
402 | if (adev->dma_mode < XFER_UDMA_0) { | |
403 | /* bits 3-0 hold recovery timing bits 8-10 active timing and | |
404 | the higer bits are dependant on the device, bit 15 udma */ | |
405 | timing &= ~ 0x870F; | |
406 | timing |= mwdma_bits[speed]; | |
407 | } else { | |
408 | /* Bit 15 is UDMA on/off, bit 12-14 are cycle time */ | |
409 | speed = adev->dma_mode - XFER_UDMA_0; | |
410 | timing &= ~0x6000; | |
411 | timing |= udma_bits[speed]; | |
412 | } | |
413 | pci_write_config_word(pdev, drive_pci, timing); | |
414 | } | |
415 | ||
416 | /** | |
417 | * sis_100_set_dmamode - Initialize host controller PATA DMA timings | |
418 | * @ap: Port whose timings we are configuring | |
419 | * @adev: Device to program | |
420 | * | |
421 | * Set UDMA/MWDMA mode for device, in host controller PCI config space. | |
422 | * Handles UDMA66 and early UDMA100 devices. | |
423 | * | |
424 | * LOCKING: | |
425 | * None (inherited from caller). | |
426 | */ | |
427 | ||
428 | static void sis_100_set_dmamode (struct ata_port *ap, struct ata_device *adev) | |
429 | { | |
430 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); | |
431 | int speed = adev->dma_mode - XFER_MW_DMA_0; | |
432 | int drive_pci = sis_port_base(adev); | |
433 | u16 timing; | |
434 | ||
435 | const u16 udma_bits[] = { 0x8B00, 0x8700, 0x8500, 0x8300, 0x8200, 0x8100}; | |
436 | ||
437 | pci_read_config_word(pdev, drive_pci, &timing); | |
438 | ||
439 | if (adev->dma_mode < XFER_UDMA_0) { | |
440 | /* NOT SUPPORTED YET: NEED DATA SHEET. DITTO IN OLD DRIVER */ | |
441 | } else { | |
442 | /* Bit 15 is UDMA on/off, bit 12-14 are cycle time */ | |
443 | speed = adev->dma_mode - XFER_UDMA_0; | |
444 | timing &= ~0x0F00; | |
445 | timing |= udma_bits[speed]; | |
446 | } | |
447 | pci_write_config_word(pdev, drive_pci, timing); | |
448 | } | |
449 | ||
450 | /** | |
451 | * sis_133_early_set_dmamode - Initialize host controller PATA DMA timings | |
452 | * @ap: Port whose timings we are configuring | |
453 | * @adev: Device to program | |
454 | * | |
455 | * Set UDMA/MWDMA mode for device, in host controller PCI config space. | |
456 | * Handles early SiS 961 bridges. Supports MWDMA as well unlike | |
457 | * the old ide/pci driver. | |
458 | * | |
459 | * LOCKING: | |
460 | * None (inherited from caller). | |
461 | */ | |
462 | ||
463 | static void sis_133_early_set_dmamode (struct ata_port *ap, struct ata_device *adev) | |
464 | { | |
465 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); | |
466 | int speed = adev->dma_mode - XFER_MW_DMA_0; | |
467 | int drive_pci = sis_port_base(adev); | |
468 | u16 timing; | |
469 | ||
470 | const u16 udma_bits[] = { 0x8F00, 0x8A00, 0x8700, 0x8500, 0x8300, 0x8200, 0x8100}; | |
471 | ||
472 | pci_read_config_word(pdev, drive_pci, &timing); | |
473 | ||
474 | if (adev->dma_mode < XFER_UDMA_0) { | |
475 | /* NOT SUPPORTED YET: NEED DATA SHEET. DITTO IN OLD DRIVER */ | |
476 | } else { | |
477 | /* Bit 15 is UDMA on/off, bit 12-14 are cycle time */ | |
478 | speed = adev->dma_mode - XFER_UDMA_0; | |
479 | timing &= ~0x0F00; | |
480 | timing |= udma_bits[speed]; | |
481 | } | |
482 | pci_write_config_word(pdev, drive_pci, timing); | |
483 | } | |
484 | ||
485 | /** | |
486 | * sis_133_set_dmamode - Initialize host controller PATA DMA timings | |
487 | * @ap: Port whose timings we are configuring | |
488 | * @adev: Device to program | |
489 | * | |
490 | * Set UDMA/MWDMA mode for device, in host controller PCI config space. | |
491 | * Handles early SiS 961 bridges. Supports MWDMA as well unlike | |
492 | * the old ide/pci driver. | |
493 | * | |
494 | * LOCKING: | |
495 | * None (inherited from caller). | |
496 | */ | |
497 | ||
498 | static void sis_133_set_dmamode (struct ata_port *ap, struct ata_device *adev) | |
499 | { | |
500 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); | |
501 | int speed = adev->dma_mode - XFER_MW_DMA_0; | |
502 | int port = 0x40; | |
503 | u32 t1; | |
504 | u32 reg54; | |
505 | ||
506 | /* bits 4- cycle time 8 - cvs time */ | |
507 | const u32 timing_u100[] = { 0x6B0, 0x470, 0x350, 0x140, 0x120, 0x110, 0x000 }; | |
508 | const u32 timing_u133[] = { 0x9F0, 0x6A0, 0x470, 0x250, 0x230, 0x220, 0x210 }; | |
509 | ||
510 | /* If bit 14 is set then the registers are mapped at 0x70 not 0x40 */ | |
511 | pci_read_config_dword(pdev, 0x54, ®54); | |
512 | if (reg54 & 0x40000000) | |
513 | port = 0x70; | |
514 | port += (8 * ap->port_no) + (4 * adev->devno); | |
515 | ||
516 | pci_read_config_dword(pdev, port, &t1); | |
517 | ||
518 | if (adev->dma_mode < XFER_UDMA_0) { | |
519 | t1 &= ~0x00000004; | |
520 | /* FIXME: need data sheet to add MWDMA here. Also lacking on | |
521 | ide/pci driver */ | |
522 | } else { | |
523 | speed = adev->dma_mode - XFER_UDMA_0; | |
524 | /* if & 8 no UDMA133 - need info for ... */ | |
525 | t1 &= ~0x00000FF0; | |
526 | t1 |= 0x00000004; | |
527 | if (t1 & 0x08) | |
528 | t1 |= timing_u133[speed]; | |
529 | else | |
530 | t1 |= timing_u100[speed]; | |
531 | } | |
532 | pci_write_config_dword(pdev, port, t1); | |
533 | } | |
534 | ||
535 | static struct scsi_host_template sis_sht = { | |
536 | .module = THIS_MODULE, | |
537 | .name = DRV_NAME, | |
538 | .ioctl = ata_scsi_ioctl, | |
539 | .queuecommand = ata_scsi_queuecmd, | |
540 | .can_queue = ATA_DEF_QUEUE, | |
541 | .this_id = ATA_SHT_THIS_ID, | |
542 | .sg_tablesize = LIBATA_MAX_PRD, | |
543 | .max_sectors = ATA_MAX_SECTORS, | |
544 | .cmd_per_lun = ATA_SHT_CMD_PER_LUN, | |
545 | .emulated = ATA_SHT_EMULATED, | |
546 | .use_clustering = ATA_SHT_USE_CLUSTERING, | |
547 | .proc_name = DRV_NAME, | |
548 | .dma_boundary = ATA_DMA_BOUNDARY, | |
549 | .slave_configure = ata_scsi_slave_config, | |
550 | .bios_param = ata_std_bios_param, | |
551 | }; | |
552 | ||
553 | static const struct ata_port_operations sis_133_ops = { | |
554 | .port_disable = ata_port_disable, | |
555 | .set_piomode = sis_133_set_piomode, | |
556 | .set_dmamode = sis_133_set_dmamode, | |
557 | .mode_filter = ata_pci_default_filter, | |
558 | ||
559 | .tf_load = ata_tf_load, | |
560 | .tf_read = ata_tf_read, | |
561 | .check_status = ata_check_status, | |
562 | .exec_command = ata_exec_command, | |
563 | .dev_select = ata_std_dev_select, | |
564 | ||
565 | .freeze = ata_bmdma_freeze, | |
566 | .thaw = ata_bmdma_thaw, | |
567 | .error_handler = sis_133_error_handler, | |
568 | .post_internal_cmd = ata_bmdma_post_internal_cmd, | |
569 | ||
570 | .bmdma_setup = ata_bmdma_setup, | |
571 | .bmdma_start = ata_bmdma_start, | |
572 | .bmdma_stop = ata_bmdma_stop, | |
573 | .bmdma_status = ata_bmdma_status, | |
574 | .qc_prep = ata_qc_prep, | |
575 | .qc_issue = ata_qc_issue_prot, | |
576 | .data_xfer = ata_pio_data_xfer, | |
577 | ||
578 | .eng_timeout = ata_eng_timeout, | |
579 | ||
580 | .irq_handler = ata_interrupt, | |
581 | .irq_clear = ata_bmdma_irq_clear, | |
582 | ||
583 | .port_start = ata_port_start, | |
584 | .port_stop = ata_port_stop, | |
585 | .host_stop = ata_host_stop, | |
586 | }; | |
587 | ||
588 | static const struct ata_port_operations sis_133_early_ops = { | |
589 | .port_disable = ata_port_disable, | |
590 | .set_piomode = sis_100_set_piomode, | |
591 | .set_dmamode = sis_133_early_set_dmamode, | |
592 | .mode_filter = ata_pci_default_filter, | |
593 | ||
594 | .tf_load = ata_tf_load, | |
595 | .tf_read = ata_tf_read, | |
596 | .check_status = ata_check_status, | |
597 | .exec_command = ata_exec_command, | |
598 | .dev_select = ata_std_dev_select, | |
599 | ||
600 | .freeze = ata_bmdma_freeze, | |
601 | .thaw = ata_bmdma_thaw, | |
602 | .error_handler = sis_66_error_handler, | |
603 | .post_internal_cmd = ata_bmdma_post_internal_cmd, | |
604 | ||
605 | .bmdma_setup = ata_bmdma_setup, | |
606 | .bmdma_start = ata_bmdma_start, | |
607 | .bmdma_stop = ata_bmdma_stop, | |
608 | .bmdma_status = ata_bmdma_status, | |
609 | .qc_prep = ata_qc_prep, | |
610 | .qc_issue = ata_qc_issue_prot, | |
611 | .data_xfer = ata_pio_data_xfer, | |
612 | ||
613 | .eng_timeout = ata_eng_timeout, | |
614 | ||
615 | .irq_handler = ata_interrupt, | |
616 | .irq_clear = ata_bmdma_irq_clear, | |
617 | ||
618 | .port_start = ata_port_start, | |
619 | .port_stop = ata_port_stop, | |
620 | .host_stop = ata_host_stop, | |
621 | }; | |
622 | ||
623 | static const struct ata_port_operations sis_100_ops = { | |
624 | .port_disable = ata_port_disable, | |
625 | .set_piomode = sis_100_set_piomode, | |
626 | .set_dmamode = sis_100_set_dmamode, | |
627 | .mode_filter = ata_pci_default_filter, | |
628 | ||
629 | .tf_load = ata_tf_load, | |
630 | .tf_read = ata_tf_read, | |
631 | .check_status = ata_check_status, | |
632 | .exec_command = ata_exec_command, | |
633 | .dev_select = ata_std_dev_select, | |
634 | ||
635 | .freeze = ata_bmdma_freeze, | |
636 | .thaw = ata_bmdma_thaw, | |
637 | .error_handler = sis_66_error_handler, | |
638 | .post_internal_cmd = ata_bmdma_post_internal_cmd, | |
639 | ||
640 | ||
641 | .bmdma_setup = ata_bmdma_setup, | |
642 | .bmdma_start = ata_bmdma_start, | |
643 | .bmdma_stop = ata_bmdma_stop, | |
644 | .bmdma_status = ata_bmdma_status, | |
645 | .qc_prep = ata_qc_prep, | |
646 | .qc_issue = ata_qc_issue_prot, | |
647 | .data_xfer = ata_pio_data_xfer, | |
648 | ||
649 | .eng_timeout = ata_eng_timeout, | |
650 | ||
651 | .irq_handler = ata_interrupt, | |
652 | .irq_clear = ata_bmdma_irq_clear, | |
653 | ||
654 | .port_start = ata_port_start, | |
655 | .port_stop = ata_port_stop, | |
656 | .host_stop = ata_host_stop, | |
657 | }; | |
658 | ||
659 | static const struct ata_port_operations sis_66_ops = { | |
660 | .port_disable = ata_port_disable, | |
661 | .set_piomode = sis_old_set_piomode, | |
662 | .set_dmamode = sis_66_set_dmamode, | |
663 | .mode_filter = ata_pci_default_filter, | |
664 | ||
665 | .tf_load = ata_tf_load, | |
666 | .tf_read = ata_tf_read, | |
667 | .check_status = ata_check_status, | |
668 | .exec_command = ata_exec_command, | |
669 | .dev_select = ata_std_dev_select, | |
670 | ||
671 | .freeze = ata_bmdma_freeze, | |
672 | .thaw = ata_bmdma_thaw, | |
673 | .error_handler = sis_66_error_handler, | |
674 | .post_internal_cmd = ata_bmdma_post_internal_cmd, | |
675 | ||
676 | .bmdma_setup = ata_bmdma_setup, | |
677 | .bmdma_start = ata_bmdma_start, | |
678 | .bmdma_stop = ata_bmdma_stop, | |
679 | .bmdma_status = ata_bmdma_status, | |
680 | .qc_prep = ata_qc_prep, | |
681 | .qc_issue = ata_qc_issue_prot, | |
682 | .data_xfer = ata_pio_data_xfer, | |
683 | ||
684 | .eng_timeout = ata_eng_timeout, | |
685 | ||
686 | .irq_handler = ata_interrupt, | |
687 | .irq_clear = ata_bmdma_irq_clear, | |
688 | ||
689 | .port_start = ata_port_start, | |
690 | .port_stop = ata_port_stop, | |
691 | .host_stop = ata_host_stop, | |
692 | }; | |
693 | ||
694 | static const struct ata_port_operations sis_old_ops = { | |
695 | .port_disable = ata_port_disable, | |
696 | .set_piomode = sis_old_set_piomode, | |
697 | .set_dmamode = sis_old_set_dmamode, | |
698 | .mode_filter = ata_pci_default_filter, | |
699 | ||
700 | .tf_load = ata_tf_load, | |
701 | .tf_read = ata_tf_read, | |
702 | .check_status = ata_check_status, | |
703 | .exec_command = ata_exec_command, | |
704 | .dev_select = ata_std_dev_select, | |
705 | ||
706 | .freeze = ata_bmdma_freeze, | |
707 | .thaw = ata_bmdma_thaw, | |
708 | .error_handler = sis_old_error_handler, | |
709 | .post_internal_cmd = ata_bmdma_post_internal_cmd, | |
710 | ||
711 | .bmdma_setup = ata_bmdma_setup, | |
712 | .bmdma_start = ata_bmdma_start, | |
713 | .bmdma_stop = ata_bmdma_stop, | |
714 | .bmdma_status = ata_bmdma_status, | |
715 | .qc_prep = ata_qc_prep, | |
716 | .qc_issue = ata_qc_issue_prot, | |
717 | .data_xfer = ata_pio_data_xfer, | |
718 | ||
719 | .eng_timeout = ata_eng_timeout, | |
720 | ||
721 | .irq_handler = ata_interrupt, | |
722 | .irq_clear = ata_bmdma_irq_clear, | |
723 | ||
724 | .port_start = ata_port_start, | |
725 | .port_stop = ata_port_stop, | |
726 | .host_stop = ata_host_stop, | |
727 | }; | |
728 | ||
729 | static struct ata_port_info sis_info = { | |
730 | .sht = &sis_sht, | |
731 | .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST, | |
732 | .pio_mask = 0x1f, /* pio0-4 */ | |
733 | .mwdma_mask = 0x07, | |
734 | .udma_mask = 0, | |
735 | .port_ops = &sis_old_ops, | |
736 | }; | |
737 | static struct ata_port_info sis_info33 = { | |
738 | .sht = &sis_sht, | |
739 | .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST, | |
740 | .pio_mask = 0x1f, /* pio0-4 */ | |
741 | .mwdma_mask = 0x07, | |
742 | .udma_mask = ATA_UDMA2, /* UDMA 33 */ | |
743 | .port_ops = &sis_old_ops, | |
744 | }; | |
745 | static struct ata_port_info sis_info66 = { | |
746 | .sht = &sis_sht, | |
747 | .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST, | |
748 | .pio_mask = 0x1f, /* pio0-4 */ | |
749 | .udma_mask = ATA_UDMA4, /* UDMA 66 */ | |
750 | .port_ops = &sis_66_ops, | |
751 | }; | |
752 | static struct ata_port_info sis_info100 = { | |
753 | .sht = &sis_sht, | |
754 | .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST, | |
755 | .pio_mask = 0x1f, /* pio0-4 */ | |
756 | .udma_mask = ATA_UDMA5, | |
757 | .port_ops = &sis_100_ops, | |
758 | }; | |
759 | static struct ata_port_info sis_info100_early = { | |
760 | .sht = &sis_sht, | |
761 | .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST, | |
762 | .udma_mask = ATA_UDMA5, | |
763 | .pio_mask = 0x1f, /* pio0-4 */ | |
764 | .port_ops = &sis_66_ops, | |
765 | }; | |
766 | static struct ata_port_info sis_info133 = { | |
767 | .sht = &sis_sht, | |
768 | .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST, | |
769 | .pio_mask = 0x1f, /* pio0-4 */ | |
770 | .udma_mask = ATA_UDMA6, | |
771 | .port_ops = &sis_133_ops, | |
772 | }; | |
773 | static struct ata_port_info sis_info133_early = { | |
774 | .sht = &sis_sht, | |
775 | .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST, | |
776 | .pio_mask = 0x1f, /* pio0-4 */ | |
777 | .udma_mask = ATA_UDMA6, | |
778 | .port_ops = &sis_133_early_ops, | |
779 | }; | |
780 | ||
781 | ||
782 | static void sis_fixup(struct pci_dev *pdev, struct sis_chipset *sis) | |
783 | { | |
784 | u16 regw; | |
785 | u8 reg; | |
786 | ||
787 | if (sis->info == &sis_info133) { | |
788 | pci_read_config_word(pdev, 0x50, ®w); | |
789 | if (regw & 0x08) | |
790 | pci_write_config_word(pdev, 0x50, regw & ~0x08); | |
791 | pci_read_config_word(pdev, 0x52, ®w); | |
792 | if (regw & 0x08) | |
793 | pci_write_config_word(pdev, 0x52, regw & ~0x08); | |
794 | return; | |
795 | } | |
796 | ||
797 | if (sis->info == &sis_info133_early || sis->info == &sis_info100) { | |
798 | /* Fix up latency */ | |
799 | pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0x80); | |
800 | /* Set compatibility bit */ | |
801 | pci_read_config_byte(pdev, 0x49, ®); | |
802 | if (!(reg & 0x01)) | |
803 | pci_write_config_byte(pdev, 0x49, reg | 0x01); | |
804 | return; | |
805 | } | |
806 | ||
807 | if (sis->info == &sis_info66 || sis->info == &sis_info100_early) { | |
808 | /* Fix up latency */ | |
809 | pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0x80); | |
810 | /* Set compatibility bit */ | |
811 | pci_read_config_byte(pdev, 0x52, ®); | |
812 | if (!(reg & 0x04)) | |
813 | pci_write_config_byte(pdev, 0x52, reg | 0x04); | |
814 | return; | |
815 | } | |
816 | ||
817 | if (sis->info == &sis_info33) { | |
818 | pci_read_config_byte(pdev, PCI_CLASS_PROG, ®); | |
819 | if (( reg & 0x0F ) != 0x00) | |
820 | pci_write_config_byte(pdev, PCI_CLASS_PROG, reg & 0xF0); | |
821 | /* Fall through to ATA16 fixup below */ | |
822 | } | |
823 | ||
824 | if (sis->info == &sis_info || sis->info == &sis_info33) { | |
825 | /* force per drive recovery and active timings | |
826 | needed on ATA_33 and below chips */ | |
827 | pci_read_config_byte(pdev, 0x52, ®); | |
828 | if (!(reg & 0x08)) | |
829 | pci_write_config_byte(pdev, 0x52, reg|0x08); | |
830 | return; | |
831 | } | |
832 | ||
833 | BUG(); | |
834 | } | |
835 | ||
836 | /** | |
837 | * sis_init_one - Register SiS ATA PCI device with kernel services | |
838 | * @pdev: PCI device to register | |
839 | * @ent: Entry in sis_pci_tbl matching with @pdev | |
840 | * | |
841 | * Called from kernel PCI layer. We probe for combined mode (sigh), | |
842 | * and then hand over control to libata, for it to do the rest. | |
843 | * | |
844 | * LOCKING: | |
845 | * Inherited from PCI layer (may sleep). | |
846 | * | |
847 | * RETURNS: | |
848 | * Zero on success, or -ERRNO value. | |
849 | */ | |
850 | ||
851 | static int sis_init_one (struct pci_dev *pdev, const struct pci_device_id *ent) | |
852 | { | |
853 | static int printed_version; | |
854 | static struct ata_port_info *port_info[2]; | |
855 | struct ata_port_info *port; | |
856 | struct pci_dev *host = NULL; | |
857 | struct sis_chipset *chipset = NULL; | |
858 | ||
859 | static struct sis_chipset sis_chipsets[] = { | |
860 | { 0x0745, &sis_info100 }, | |
861 | { 0x0735, &sis_info100 }, | |
862 | { 0x0733, &sis_info100 }, | |
863 | { 0x0635, &sis_info100 }, | |
864 | { 0x0633, &sis_info100 }, | |
865 | ||
866 | { 0x0730, &sis_info100_early }, /* 100 with ATA 66 layout */ | |
867 | { 0x0550, &sis_info100_early }, /* 100 with ATA 66 layout */ | |
868 | ||
869 | { 0x0640, &sis_info66 }, | |
870 | { 0x0630, &sis_info66 }, | |
871 | { 0x0620, &sis_info66 }, | |
872 | { 0x0540, &sis_info66 }, | |
873 | { 0x0530, &sis_info66 }, | |
874 | ||
875 | { 0x5600, &sis_info33 }, | |
876 | { 0x5598, &sis_info33 }, | |
877 | { 0x5597, &sis_info33 }, | |
878 | { 0x5591, &sis_info33 }, | |
879 | { 0x5582, &sis_info33 }, | |
880 | { 0x5581, &sis_info33 }, | |
881 | ||
882 | { 0x5596, &sis_info }, | |
883 | { 0x5571, &sis_info }, | |
884 | { 0x5517, &sis_info }, | |
885 | { 0x5511, &sis_info }, | |
886 | ||
887 | {0} | |
888 | }; | |
889 | static struct sis_chipset sis133_early = { | |
890 | 0x0, &sis_info133_early | |
891 | }; | |
892 | static struct sis_chipset sis133 = { | |
893 | 0x0, &sis_info133 | |
894 | }; | |
895 | static struct sis_chipset sis100_early = { | |
896 | 0x0, &sis_info100_early | |
897 | }; | |
898 | static struct sis_chipset sis100 = { | |
899 | 0x0, &sis_info100 | |
900 | }; | |
901 | ||
902 | if (!printed_version++) | |
903 | dev_printk(KERN_DEBUG, &pdev->dev, | |
904 | "version " DRV_VERSION "\n"); | |
905 | ||
906 | /* We have to find the bridge first */ | |
907 | ||
908 | for (chipset = &sis_chipsets[0]; chipset->device; chipset++) { | |
909 | host = pci_get_device(PCI_VENDOR_ID_SI, chipset->device, NULL); | |
910 | if (host != NULL) { | |
911 | if (chipset->device == 0x630) { /* SIS630 */ | |
912 | u8 host_rev; | |
913 | pci_read_config_byte(host, PCI_REVISION_ID, &host_rev); | |
914 | if (host_rev >= 0x30) /* 630 ET */ | |
915 | chipset = &sis100_early; | |
916 | } | |
917 | break; | |
918 | } | |
919 | } | |
920 | ||
921 | /* Look for concealed bridges */ | |
922 | if (host == NULL) { | |
923 | /* Second check */ | |
924 | u32 idemisc; | |
925 | u16 trueid; | |
926 | ||
927 | /* Disable ID masking and register remapping then | |
928 | see what the real ID is */ | |
929 | ||
930 | pci_read_config_dword(pdev, 0x54, &idemisc); | |
931 | pci_write_config_dword(pdev, 0x54, idemisc & 0x7fffffff); | |
932 | pci_read_config_word(pdev, PCI_DEVICE_ID, &trueid); | |
933 | pci_write_config_dword(pdev, 0x54, idemisc); | |
934 | ||
935 | switch(trueid) { | |
936 | case 0x5518: /* SIS 962/963 */ | |
937 | chipset = &sis133; | |
938 | if ((idemisc & 0x40000000) == 0) { | |
939 | pci_write_config_dword(pdev, 0x54, idemisc | 0x40000000); | |
940 | printk(KERN_INFO "SIS5513: Switching to 5513 register mapping\n"); | |
941 | } | |
942 | break; | |
943 | case 0x0180: /* SIS 965/965L */ | |
944 | chipset = &sis133; | |
945 | break; | |
946 | case 0x1180: /* SIS 966/966L */ | |
947 | chipset = &sis133; | |
948 | break; | |
949 | } | |
950 | } | |
951 | ||
952 | /* Further check */ | |
953 | if (chipset == NULL) { | |
954 | struct pci_dev *lpc_bridge; | |
955 | u16 trueid; | |
956 | u8 prefctl; | |
957 | u8 idecfg; | |
958 | u8 sbrev; | |
959 | ||
960 | /* Try the second unmasking technique */ | |
961 | pci_read_config_byte(pdev, 0x4a, &idecfg); | |
962 | pci_write_config_byte(pdev, 0x4a, idecfg | 0x10); | |
963 | pci_read_config_word(pdev, PCI_DEVICE_ID, &trueid); | |
964 | pci_write_config_byte(pdev, 0x4a, idecfg); | |
965 | ||
966 | switch(trueid) { | |
967 | case 0x5517: | |
968 | lpc_bridge = pci_get_slot(pdev->bus, 0x10); /* Bus 0 Dev 2 Fn 0 */ | |
969 | if (lpc_bridge == NULL) | |
970 | break; | |
971 | pci_read_config_byte(lpc_bridge, PCI_REVISION_ID, &sbrev); | |
972 | pci_read_config_byte(pdev, 0x49, &prefctl); | |
973 | pci_dev_put(lpc_bridge); | |
974 | ||
975 | if (sbrev == 0x10 && (prefctl & 0x80)) { | |
976 | chipset = &sis133_early; | |
977 | break; | |
978 | } | |
979 | chipset = &sis100; | |
980 | break; | |
981 | } | |
982 | } | |
983 | pci_dev_put(host); | |
984 | ||
985 | /* No chipset info, no support */ | |
986 | if (chipset == NULL) | |
987 | return -ENODEV; | |
988 | ||
989 | port = chipset->info; | |
990 | port->private_data = chipset; | |
991 | ||
992 | sis_fixup(pdev, chipset); | |
993 | ||
994 | port_info[0] = port_info[1] = port; | |
995 | return ata_pci_init_one(pdev, port_info, 2); | |
996 | } | |
997 | ||
998 | static const struct pci_device_id sis_pci_tbl[] = { | |
999 | { PCI_DEVICE(PCI_VENDOR_ID_SI, 0x5513), }, /* SiS 5513 */ | |
1000 | { PCI_DEVICE(PCI_VENDOR_ID_SI, 0x5518), }, /* SiS 5518 */ | |
1001 | { } | |
1002 | }; | |
1003 | ||
1004 | static struct pci_driver sis_pci_driver = { | |
1005 | .name = DRV_NAME, | |
1006 | .id_table = sis_pci_tbl, | |
1007 | .probe = sis_init_one, | |
1008 | .remove = ata_pci_remove_one, | |
1009 | }; | |
1010 | ||
1011 | static int __init sis_init(void) | |
1012 | { | |
1013 | return pci_register_driver(&sis_pci_driver); | |
1014 | } | |
1015 | ||
1016 | static void __exit sis_exit(void) | |
1017 | { | |
1018 | pci_unregister_driver(&sis_pci_driver); | |
1019 | } | |
1020 | ||
1021 | ||
1022 | module_init(sis_init); | |
1023 | module_exit(sis_exit); | |
1024 | ||
1025 | MODULE_AUTHOR("Alan Cox"); | |
1026 | MODULE_DESCRIPTION("SCSI low-level driver for SiS ATA"); | |
1027 | MODULE_LICENSE("GPL"); | |
1028 | MODULE_DEVICE_TABLE(pci, sis_pci_tbl); | |
1029 | MODULE_VERSION(DRV_VERSION); | |
1030 |