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669a5db4 JG |
1 | /* |
2 | * pata_sl82c105.c - SL82C105 PATA for new ATA layer | |
3 | * (C) 2005 Red Hat Inc | |
4 | * Alan Cox <alan@redhat.com> | |
5 | * | |
6 | * Based in part on linux/drivers/ide/pci/sl82c105.c | |
7 | * SL82C105/Winbond 553 IDE driver | |
8 | * | |
9 | * and in part on the documentation and errata sheet | |
16728da9 A |
10 | * |
11 | * | |
12 | * Note: The controller like many controllers has shared timings for | |
13 | * PIO and DMA. We thus flip to the DMA timings in dma_start and flip back | |
14 | * in the dma_stop function. Thus we actually don't need a set_dmamode | |
15 | * method as the PIO method is always called and will set the right PIO | |
16 | * timing parameters. | |
669a5db4 | 17 | */ |
85cd7251 | 18 | |
669a5db4 JG |
19 | #include <linux/kernel.h> |
20 | #include <linux/module.h> | |
21 | #include <linux/pci.h> | |
22 | #include <linux/init.h> | |
23 | #include <linux/blkdev.h> | |
24 | #include <linux/delay.h> | |
25 | #include <scsi/scsi_host.h> | |
26 | #include <linux/libata.h> | |
27 | ||
28 | #define DRV_NAME "pata_sl82c105" | |
cb48cab7 | 29 | #define DRV_VERSION "0.3.0" |
669a5db4 JG |
30 | |
31 | enum { | |
32 | /* | |
33 | * SL82C105 PCI config register 0x40 bits. | |
34 | */ | |
35 | CTRL_IDE_IRQB = (1 << 30), | |
36 | CTRL_IDE_IRQA = (1 << 28), | |
37 | CTRL_LEGIRQ = (1 << 11), | |
38 | CTRL_P1F16 = (1 << 5), | |
39 | CTRL_P1EN = (1 << 4), | |
40 | CTRL_P0F16 = (1 << 1), | |
41 | CTRL_P0EN = (1 << 0) | |
42 | }; | |
43 | ||
44 | /** | |
45 | * sl82c105_pre_reset - probe begin | |
46 | * @ap: ATA port | |
d4b2bab4 | 47 | * @deadline: deadline jiffies for the operation |
669a5db4 JG |
48 | * |
49 | * Set up cable type and use generic probe init | |
50 | */ | |
85cd7251 | 51 | |
d4b2bab4 | 52 | static int sl82c105_pre_reset(struct ata_port *ap, unsigned long deadline) |
669a5db4 JG |
53 | { |
54 | static const struct pci_bits sl82c105_enable_bits[] = { | |
55 | { 0x40, 1, 0x01, 0x01 }, | |
56 | { 0x40, 1, 0x10, 0x10 } | |
57 | }; | |
58 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); | |
59 | ||
c961922b AC |
60 | if (ap->port_no && !pci_test_config_bits(pdev, &sl82c105_enable_bits[ap->port_no])) |
61 | return -ENOENT; | |
d4b2bab4 | 62 | return ata_std_prereset(ap, deadline); |
669a5db4 JG |
63 | } |
64 | ||
65 | ||
66 | static void sl82c105_error_handler(struct ata_port *ap) | |
67 | { | |
68 | ata_bmdma_drive_eh(ap, sl82c105_pre_reset, ata_std_softreset, NULL, ata_std_postreset); | |
69 | } | |
70 | ||
71 | ||
72 | /** | |
73 | * sl82c105_configure_piomode - set chip PIO timing | |
74 | * @ap: ATA interface | |
75 | * @adev: ATA device | |
76 | * @pio: PIO mode | |
77 | * | |
78 | * Called to do the PIO mode setup. Our timing registers are shared | |
79 | * so a configure_dmamode call will undo any work we do here and vice | |
80 | * versa | |
81 | */ | |
85cd7251 | 82 | |
669a5db4 JG |
83 | static void sl82c105_configure_piomode(struct ata_port *ap, struct ata_device *adev, int pio) |
84 | { | |
85 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); | |
86 | static u16 pio_timing[5] = { | |
87 | 0x50D, 0x407, 0x304, 0x242, 0x240 | |
88 | }; | |
89 | u16 dummy; | |
90 | int timing = 0x44 + (8 * ap->port_no) + (4 * adev->devno); | |
85cd7251 | 91 | |
669a5db4 JG |
92 | pci_write_config_word(pdev, timing, pio_timing[pio]); |
93 | /* Can we lose this oddity of the old driver */ | |
94 | pci_read_config_word(pdev, timing, &dummy); | |
95 | } | |
96 | ||
97 | /** | |
98 | * sl82c105_set_piomode - set initial PIO mode data | |
99 | * @ap: ATA interface | |
100 | * @adev: ATA device | |
101 | * | |
102 | * Called to do the PIO mode setup. Our timing registers are shared | |
103 | * but we want to set the PIO timing by default. | |
104 | */ | |
85cd7251 | 105 | |
669a5db4 JG |
106 | static void sl82c105_set_piomode(struct ata_port *ap, struct ata_device *adev) |
107 | { | |
108 | sl82c105_configure_piomode(ap, adev, adev->pio_mode - XFER_PIO_0); | |
109 | } | |
110 | ||
111 | /** | |
112 | * sl82c105_configure_dmamode - set DMA mode in chip | |
113 | * @ap: ATA interface | |
114 | * @adev: ATA device | |
115 | * | |
116 | * Load DMA cycle times into the chip ready for a DMA transfer | |
117 | * to occur. | |
118 | */ | |
85cd7251 | 119 | |
669a5db4 JG |
120 | static void sl82c105_configure_dmamode(struct ata_port *ap, struct ata_device *adev) |
121 | { | |
122 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); | |
123 | static u16 dma_timing[3] = { | |
124 | 0x707, 0x201, 0x200 | |
125 | }; | |
126 | u16 dummy; | |
127 | int timing = 0x44 + (8 * ap->port_no) + (4 * adev->devno); | |
128 | int dma = adev->dma_mode - XFER_MW_DMA_0; | |
85cd7251 | 129 | |
669a5db4 JG |
130 | pci_write_config_word(pdev, timing, dma_timing[dma]); |
131 | /* Can we lose this oddity of the old driver */ | |
132 | pci_read_config_word(pdev, timing, &dummy); | |
133 | } | |
134 | ||
669a5db4 JG |
135 | /** |
136 | * sl82c105_reset_engine - Reset the DMA engine | |
137 | * @ap: ATA interface | |
138 | * | |
139 | * The sl82c105 has some serious problems with the DMA engine | |
85cd7251 | 140 | * when transfers don't run as expected or ATAPI is used. The |
669a5db4 JG |
141 | * recommended fix is to reset the engine each use using a chip |
142 | * test register. | |
143 | */ | |
85cd7251 | 144 | |
669a5db4 JG |
145 | static void sl82c105_reset_engine(struct ata_port *ap) |
146 | { | |
147 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); | |
148 | u16 val; | |
85cd7251 | 149 | |
669a5db4 JG |
150 | pci_read_config_word(pdev, 0x7E, &val); |
151 | pci_write_config_word(pdev, 0x7E, val | 4); | |
152 | pci_write_config_word(pdev, 0x7E, val & ~4); | |
153 | } | |
154 | ||
155 | /** | |
156 | * sl82c105_bmdma_start - DMA engine begin | |
157 | * @qc: ATA command | |
158 | * | |
159 | * Reset the DMA engine each use as recommended by the errata | |
85cd7251 | 160 | * document. |
669a5db4 JG |
161 | * |
162 | * FIXME: if we switch clock at BMDMA start/end we might get better | |
163 | * PIO performance on DMA capable devices. | |
164 | */ | |
85cd7251 | 165 | |
669a5db4 JG |
166 | static void sl82c105_bmdma_start(struct ata_queued_cmd *qc) |
167 | { | |
168 | struct ata_port *ap = qc->ap; | |
169 | ||
8361cd79 | 170 | udelay(100); |
669a5db4 | 171 | sl82c105_reset_engine(ap); |
8361cd79 | 172 | udelay(100); |
85cd7251 | 173 | |
669a5db4 JG |
174 | /* Set the clocks for DMA */ |
175 | sl82c105_configure_dmamode(ap, qc->dev); | |
85cd7251 | 176 | /* Activate DMA */ |
669a5db4 JG |
177 | ata_bmdma_start(qc); |
178 | } | |
179 | ||
180 | /** | |
181 | * sl82c105_bmdma_end - DMA engine stop | |
182 | * @qc: ATA command | |
183 | * | |
184 | * Reset the DMA engine each use as recommended by the errata | |
185 | * document. | |
186 | * | |
187 | * This function is also called to turn off DMA when a timeout occurs | |
188 | * during DMA operation. In both cases we need to reset the engine, | |
189 | * so no actual eng_timeout handler is required. | |
190 | * | |
191 | * We assume bmdma_stop is always called if bmdma_start as called. If | |
192 | * not then we may need to wrap qc_issue. | |
193 | */ | |
85cd7251 | 194 | |
669a5db4 JG |
195 | static void sl82c105_bmdma_stop(struct ata_queued_cmd *qc) |
196 | { | |
197 | struct ata_port *ap = qc->ap; | |
198 | ||
199 | ata_bmdma_stop(qc); | |
200 | sl82c105_reset_engine(ap); | |
8361cd79 | 201 | udelay(100); |
85cd7251 | 202 | |
669a5db4 JG |
203 | /* This will redo the initial setup of the DMA device to matching |
204 | PIO timings */ | |
16728da9 | 205 | sl82c105_set_piomode(ap, qc->dev); |
669a5db4 JG |
206 | } |
207 | ||
208 | static struct scsi_host_template sl82c105_sht = { | |
209 | .module = THIS_MODULE, | |
210 | .name = DRV_NAME, | |
211 | .ioctl = ata_scsi_ioctl, | |
212 | .queuecommand = ata_scsi_queuecmd, | |
213 | .can_queue = ATA_DEF_QUEUE, | |
214 | .this_id = ATA_SHT_THIS_ID, | |
215 | .sg_tablesize = LIBATA_MAX_PRD, | |
669a5db4 JG |
216 | .cmd_per_lun = ATA_SHT_CMD_PER_LUN, |
217 | .emulated = ATA_SHT_EMULATED, | |
218 | .use_clustering = ATA_SHT_USE_CLUSTERING, | |
219 | .proc_name = DRV_NAME, | |
220 | .dma_boundary = ATA_DMA_BOUNDARY, | |
221 | .slave_configure = ata_scsi_slave_config, | |
afdfe899 | 222 | .slave_destroy = ata_scsi_slave_destroy, |
669a5db4 JG |
223 | .bios_param = ata_std_bios_param, |
224 | }; | |
225 | ||
226 | static struct ata_port_operations sl82c105_port_ops = { | |
227 | .port_disable = ata_port_disable, | |
228 | .set_piomode = sl82c105_set_piomode, | |
669a5db4 JG |
229 | .mode_filter = ata_pci_default_filter, |
230 | ||
231 | .tf_load = ata_tf_load, | |
232 | .tf_read = ata_tf_read, | |
233 | .check_status = ata_check_status, | |
234 | .exec_command = ata_exec_command, | |
235 | .dev_select = ata_std_dev_select, | |
236 | ||
bf7551c4 JG |
237 | .freeze = ata_bmdma_freeze, |
238 | .thaw = ata_bmdma_thaw, | |
669a5db4 | 239 | .error_handler = sl82c105_error_handler, |
bf7551c4 | 240 | .post_internal_cmd = ata_bmdma_post_internal_cmd, |
c45a6328 | 241 | .cable_detect = ata_cable_40wire, |
669a5db4 JG |
242 | |
243 | .bmdma_setup = ata_bmdma_setup, | |
244 | .bmdma_start = sl82c105_bmdma_start, | |
245 | .bmdma_stop = sl82c105_bmdma_stop, | |
246 | .bmdma_status = ata_bmdma_status, | |
247 | ||
248 | .qc_prep = ata_qc_prep, | |
249 | .qc_issue = ata_qc_issue_prot, | |
bda30288 | 250 | |
0d5ff566 | 251 | .data_xfer = ata_data_xfer, |
669a5db4 JG |
252 | |
253 | .irq_handler = ata_interrupt, | |
254 | .irq_clear = ata_bmdma_irq_clear, | |
246ce3b6 AI |
255 | .irq_on = ata_irq_on, |
256 | .irq_ack = ata_irq_ack, | |
85cd7251 | 257 | |
669a5db4 | 258 | .port_start = ata_port_start, |
85cd7251 | 259 | }; |
669a5db4 JG |
260 | |
261 | /** | |
262 | * sl82c105_bridge_revision - find bridge version | |
263 | * @pdev: PCI device for the ATA function | |
264 | * | |
265 | * Locates the PCI bridge associated with the ATA function and | |
266 | * providing it is a Winbond 553 reports the revision. If it cannot | |
267 | * find a revision or the right device it returns -1 | |
268 | */ | |
85cd7251 | 269 | |
669a5db4 JG |
270 | static int sl82c105_bridge_revision(struct pci_dev *pdev) |
271 | { | |
272 | struct pci_dev *bridge; | |
273 | u8 rev; | |
274 | ||
275 | /* | |
276 | * The bridge should be part of the same device, but function 0. | |
277 | */ | |
278 | bridge = pci_get_slot(pdev->bus, | |
279 | PCI_DEVFN(PCI_SLOT(pdev->devfn), 0)); | |
280 | if (!bridge) | |
281 | return -1; | |
282 | ||
283 | /* | |
284 | * Make sure it is a Winbond 553 and is an ISA bridge. | |
285 | */ | |
286 | if (bridge->vendor != PCI_VENDOR_ID_WINBOND || | |
287 | bridge->device != PCI_DEVICE_ID_WINBOND_83C553 || | |
288 | bridge->class >> 8 != PCI_CLASS_BRIDGE_ISA) { | |
289 | pci_dev_put(bridge); | |
290 | return -1; | |
291 | } | |
292 | /* | |
293 | * We need to find function 0's revision, not function 1 | |
294 | */ | |
295 | pci_read_config_byte(bridge, PCI_REVISION_ID, &rev); | |
296 | ||
297 | pci_dev_put(bridge); | |
298 | return rev; | |
299 | } | |
300 | ||
85cd7251 | 301 | |
669a5db4 JG |
302 | static int sl82c105_init_one(struct pci_dev *dev, const struct pci_device_id *id) |
303 | { | |
1626aeb8 | 304 | static const struct ata_port_info info_dma = { |
669a5db4 JG |
305 | .sht = &sl82c105_sht, |
306 | .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST, | |
307 | .pio_mask = 0x1f, | |
308 | .mwdma_mask = 0x07, | |
309 | .port_ops = &sl82c105_port_ops | |
310 | }; | |
1626aeb8 | 311 | static const struct ata_port_info info_early = { |
669a5db4 JG |
312 | .sht = &sl82c105_sht, |
313 | .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST, | |
314 | .pio_mask = 0x1f, | |
315 | .port_ops = &sl82c105_port_ops | |
316 | }; | |
1626aeb8 TH |
317 | /* for now use only the first port */ |
318 | const struct ata_port_info *ppi[] = { &info_early, | |
319 | &ata_dummy_port_info }; | |
669a5db4 JG |
320 | u32 val; |
321 | int rev; | |
322 | ||
323 | rev = sl82c105_bridge_revision(dev); | |
85cd7251 | 324 | |
669a5db4 JG |
325 | if (rev == -1) |
326 | dev_printk(KERN_WARNING, &dev->dev, "pata_sl82c105: Unable to find bridge, disabling DMA.\n"); | |
327 | else if (rev <= 5) | |
328 | dev_printk(KERN_WARNING, &dev->dev, "pata_sl82c105: Early bridge revision, no DMA available.\n"); | |
1626aeb8 TH |
329 | else |
330 | ppi[0] = &info_dma; | |
85cd7251 | 331 | |
669a5db4 JG |
332 | pci_read_config_dword(dev, 0x40, &val); |
333 | val |= CTRL_P0EN | CTRL_P0F16 | CTRL_P1F16; | |
334 | pci_write_config_dword(dev, 0x40, val); | |
335 | ||
1626aeb8 | 336 | return ata_pci_init_one(dev, ppi); |
669a5db4 JG |
337 | } |
338 | ||
2d2744fc JG |
339 | static const struct pci_device_id sl82c105[] = { |
340 | { PCI_VDEVICE(WINBOND, PCI_DEVICE_ID_WINBOND_82C105), }, | |
341 | ||
342 | { }, | |
669a5db4 JG |
343 | }; |
344 | ||
345 | static struct pci_driver sl82c105_pci_driver = { | |
346 | .name = DRV_NAME, | |
347 | .id_table = sl82c105, | |
348 | .probe = sl82c105_init_one, | |
349 | .remove = ata_pci_remove_one | |
350 | }; | |
351 | ||
352 | static int __init sl82c105_init(void) | |
353 | { | |
354 | return pci_register_driver(&sl82c105_pci_driver); | |
355 | } | |
356 | ||
669a5db4 JG |
357 | static void __exit sl82c105_exit(void) |
358 | { | |
359 | pci_unregister_driver(&sl82c105_pci_driver); | |
360 | } | |
361 | ||
669a5db4 JG |
362 | MODULE_AUTHOR("Alan Cox"); |
363 | MODULE_DESCRIPTION("low-level driver for Sl82c105"); | |
364 | MODULE_LICENSE("GPL"); | |
365 | MODULE_DEVICE_TABLE(pci, sl82c105); | |
366 | MODULE_VERSION(DRV_VERSION); | |
367 | ||
368 | module_init(sl82c105_init); | |
369 | module_exit(sl82c105_exit); |