Commit | Line | Data |
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669a5db4 JG |
1 | /* |
2 | * pata_sl82c105.c - SL82C105 PATA for new ATA layer | |
3 | * (C) 2005 Red Hat Inc | |
4 | * Alan Cox <alan@redhat.com> | |
5 | * | |
6 | * Based in part on linux/drivers/ide/pci/sl82c105.c | |
7 | * SL82C105/Winbond 553 IDE driver | |
8 | * | |
9 | * and in part on the documentation and errata sheet | |
16728da9 A |
10 | * |
11 | * | |
12 | * Note: The controller like many controllers has shared timings for | |
13 | * PIO and DMA. We thus flip to the DMA timings in dma_start and flip back | |
14 | * in the dma_stop function. Thus we actually don't need a set_dmamode | |
15 | * method as the PIO method is always called and will set the right PIO | |
16 | * timing parameters. | |
669a5db4 | 17 | */ |
85cd7251 | 18 | |
669a5db4 JG |
19 | #include <linux/kernel.h> |
20 | #include <linux/module.h> | |
21 | #include <linux/pci.h> | |
22 | #include <linux/init.h> | |
23 | #include <linux/blkdev.h> | |
24 | #include <linux/delay.h> | |
25 | #include <scsi/scsi_host.h> | |
26 | #include <linux/libata.h> | |
27 | ||
28 | #define DRV_NAME "pata_sl82c105" | |
92ba5d02 | 29 | #define DRV_VERSION "0.3.3" |
669a5db4 JG |
30 | |
31 | enum { | |
32 | /* | |
33 | * SL82C105 PCI config register 0x40 bits. | |
34 | */ | |
35 | CTRL_IDE_IRQB = (1 << 30), | |
36 | CTRL_IDE_IRQA = (1 << 28), | |
37 | CTRL_LEGIRQ = (1 << 11), | |
38 | CTRL_P1F16 = (1 << 5), | |
39 | CTRL_P1EN = (1 << 4), | |
40 | CTRL_P0F16 = (1 << 1), | |
41 | CTRL_P0EN = (1 << 0) | |
42 | }; | |
43 | ||
44 | /** | |
45 | * sl82c105_pre_reset - probe begin | |
cc0680a5 | 46 | * @link: ATA link |
d4b2bab4 | 47 | * @deadline: deadline jiffies for the operation |
669a5db4 JG |
48 | * |
49 | * Set up cable type and use generic probe init | |
50 | */ | |
85cd7251 | 51 | |
cc0680a5 | 52 | static int sl82c105_pre_reset(struct ata_link *link, unsigned long deadline) |
669a5db4 JG |
53 | { |
54 | static const struct pci_bits sl82c105_enable_bits[] = { | |
55 | { 0x40, 1, 0x01, 0x01 }, | |
56 | { 0x40, 1, 0x10, 0x10 } | |
57 | }; | |
cc0680a5 | 58 | struct ata_port *ap = link->ap; |
669a5db4 JG |
59 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); |
60 | ||
c961922b AC |
61 | if (ap->port_no && !pci_test_config_bits(pdev, &sl82c105_enable_bits[ap->port_no])) |
62 | return -ENOENT; | |
cc0680a5 | 63 | return ata_std_prereset(link, deadline); |
669a5db4 JG |
64 | } |
65 | ||
66 | ||
67 | static void sl82c105_error_handler(struct ata_port *ap) | |
68 | { | |
69 | ata_bmdma_drive_eh(ap, sl82c105_pre_reset, ata_std_softreset, NULL, ata_std_postreset); | |
70 | } | |
71 | ||
72 | ||
73 | /** | |
74 | * sl82c105_configure_piomode - set chip PIO timing | |
75 | * @ap: ATA interface | |
76 | * @adev: ATA device | |
77 | * @pio: PIO mode | |
78 | * | |
79 | * Called to do the PIO mode setup. Our timing registers are shared | |
80 | * so a configure_dmamode call will undo any work we do here and vice | |
81 | * versa | |
82 | */ | |
85cd7251 | 83 | |
669a5db4 JG |
84 | static void sl82c105_configure_piomode(struct ata_port *ap, struct ata_device *adev, int pio) |
85 | { | |
86 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); | |
87 | static u16 pio_timing[5] = { | |
88 | 0x50D, 0x407, 0x304, 0x242, 0x240 | |
89 | }; | |
90 | u16 dummy; | |
91 | int timing = 0x44 + (8 * ap->port_no) + (4 * adev->devno); | |
85cd7251 | 92 | |
669a5db4 JG |
93 | pci_write_config_word(pdev, timing, pio_timing[pio]); |
94 | /* Can we lose this oddity of the old driver */ | |
95 | pci_read_config_word(pdev, timing, &dummy); | |
96 | } | |
97 | ||
98 | /** | |
99 | * sl82c105_set_piomode - set initial PIO mode data | |
100 | * @ap: ATA interface | |
101 | * @adev: ATA device | |
102 | * | |
103 | * Called to do the PIO mode setup. Our timing registers are shared | |
104 | * but we want to set the PIO timing by default. | |
105 | */ | |
85cd7251 | 106 | |
669a5db4 JG |
107 | static void sl82c105_set_piomode(struct ata_port *ap, struct ata_device *adev) |
108 | { | |
109 | sl82c105_configure_piomode(ap, adev, adev->pio_mode - XFER_PIO_0); | |
110 | } | |
111 | ||
112 | /** | |
113 | * sl82c105_configure_dmamode - set DMA mode in chip | |
114 | * @ap: ATA interface | |
115 | * @adev: ATA device | |
116 | * | |
117 | * Load DMA cycle times into the chip ready for a DMA transfer | |
118 | * to occur. | |
119 | */ | |
85cd7251 | 120 | |
669a5db4 JG |
121 | static void sl82c105_configure_dmamode(struct ata_port *ap, struct ata_device *adev) |
122 | { | |
123 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); | |
124 | static u16 dma_timing[3] = { | |
125 | 0x707, 0x201, 0x200 | |
126 | }; | |
127 | u16 dummy; | |
128 | int timing = 0x44 + (8 * ap->port_no) + (4 * adev->devno); | |
129 | int dma = adev->dma_mode - XFER_MW_DMA_0; | |
85cd7251 | 130 | |
669a5db4 JG |
131 | pci_write_config_word(pdev, timing, dma_timing[dma]); |
132 | /* Can we lose this oddity of the old driver */ | |
133 | pci_read_config_word(pdev, timing, &dummy); | |
134 | } | |
135 | ||
669a5db4 JG |
136 | /** |
137 | * sl82c105_reset_engine - Reset the DMA engine | |
138 | * @ap: ATA interface | |
139 | * | |
140 | * The sl82c105 has some serious problems with the DMA engine | |
85cd7251 | 141 | * when transfers don't run as expected or ATAPI is used. The |
669a5db4 JG |
142 | * recommended fix is to reset the engine each use using a chip |
143 | * test register. | |
144 | */ | |
85cd7251 | 145 | |
669a5db4 JG |
146 | static void sl82c105_reset_engine(struct ata_port *ap) |
147 | { | |
148 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); | |
149 | u16 val; | |
85cd7251 | 150 | |
669a5db4 JG |
151 | pci_read_config_word(pdev, 0x7E, &val); |
152 | pci_write_config_word(pdev, 0x7E, val | 4); | |
153 | pci_write_config_word(pdev, 0x7E, val & ~4); | |
154 | } | |
155 | ||
156 | /** | |
157 | * sl82c105_bmdma_start - DMA engine begin | |
158 | * @qc: ATA command | |
159 | * | |
160 | * Reset the DMA engine each use as recommended by the errata | |
85cd7251 | 161 | * document. |
669a5db4 JG |
162 | * |
163 | * FIXME: if we switch clock at BMDMA start/end we might get better | |
164 | * PIO performance on DMA capable devices. | |
165 | */ | |
85cd7251 | 166 | |
669a5db4 JG |
167 | static void sl82c105_bmdma_start(struct ata_queued_cmd *qc) |
168 | { | |
169 | struct ata_port *ap = qc->ap; | |
170 | ||
8361cd79 | 171 | udelay(100); |
669a5db4 | 172 | sl82c105_reset_engine(ap); |
8361cd79 | 173 | udelay(100); |
85cd7251 | 174 | |
669a5db4 JG |
175 | /* Set the clocks for DMA */ |
176 | sl82c105_configure_dmamode(ap, qc->dev); | |
85cd7251 | 177 | /* Activate DMA */ |
669a5db4 JG |
178 | ata_bmdma_start(qc); |
179 | } | |
180 | ||
181 | /** | |
182 | * sl82c105_bmdma_end - DMA engine stop | |
183 | * @qc: ATA command | |
184 | * | |
185 | * Reset the DMA engine each use as recommended by the errata | |
186 | * document. | |
187 | * | |
188 | * This function is also called to turn off DMA when a timeout occurs | |
189 | * during DMA operation. In both cases we need to reset the engine, | |
190 | * so no actual eng_timeout handler is required. | |
191 | * | |
192 | * We assume bmdma_stop is always called if bmdma_start as called. If | |
193 | * not then we may need to wrap qc_issue. | |
194 | */ | |
85cd7251 | 195 | |
669a5db4 JG |
196 | static void sl82c105_bmdma_stop(struct ata_queued_cmd *qc) |
197 | { | |
198 | struct ata_port *ap = qc->ap; | |
199 | ||
200 | ata_bmdma_stop(qc); | |
201 | sl82c105_reset_engine(ap); | |
8361cd79 | 202 | udelay(100); |
85cd7251 | 203 | |
669a5db4 JG |
204 | /* This will redo the initial setup of the DMA device to matching |
205 | PIO timings */ | |
16728da9 | 206 | sl82c105_set_piomode(ap, qc->dev); |
669a5db4 JG |
207 | } |
208 | ||
92ba5d02 AC |
209 | /** |
210 | * sl82c105_qc_defer - implement serialization | |
211 | * @qc: command | |
212 | * | |
213 | * We must issue one command per host not per channel because | |
214 | * of the reset bug. | |
215 | * | |
216 | * Q: is the scsi host lock sufficient ? | |
217 | */ | |
218 | ||
219 | static int sl82c105_qc_defer(struct ata_queued_cmd *qc) | |
220 | { | |
221 | struct ata_host *host = qc->ap->host; | |
222 | struct ata_port *alt = host->ports[1 ^ qc->ap->port_no]; | |
223 | int rc; | |
224 | ||
225 | /* First apply the usual rules */ | |
226 | rc = ata_std_qc_defer(qc); | |
227 | if (rc != 0) | |
228 | return rc; | |
229 | ||
230 | /* Now apply serialization rules. Only allow a command if the | |
231 | other channel state machine is idle */ | |
232 | if (alt && alt->qc_active) | |
233 | return ATA_DEFER_PORT; | |
234 | return 0; | |
235 | } | |
236 | ||
669a5db4 JG |
237 | static struct scsi_host_template sl82c105_sht = { |
238 | .module = THIS_MODULE, | |
239 | .name = DRV_NAME, | |
240 | .ioctl = ata_scsi_ioctl, | |
241 | .queuecommand = ata_scsi_queuecmd, | |
242 | .can_queue = ATA_DEF_QUEUE, | |
243 | .this_id = ATA_SHT_THIS_ID, | |
244 | .sg_tablesize = LIBATA_MAX_PRD, | |
669a5db4 JG |
245 | .cmd_per_lun = ATA_SHT_CMD_PER_LUN, |
246 | .emulated = ATA_SHT_EMULATED, | |
247 | .use_clustering = ATA_SHT_USE_CLUSTERING, | |
248 | .proc_name = DRV_NAME, | |
249 | .dma_boundary = ATA_DMA_BOUNDARY, | |
250 | .slave_configure = ata_scsi_slave_config, | |
afdfe899 | 251 | .slave_destroy = ata_scsi_slave_destroy, |
669a5db4 JG |
252 | .bios_param = ata_std_bios_param, |
253 | }; | |
254 | ||
255 | static struct ata_port_operations sl82c105_port_ops = { | |
669a5db4 | 256 | .set_piomode = sl82c105_set_piomode, |
669a5db4 JG |
257 | .mode_filter = ata_pci_default_filter, |
258 | ||
259 | .tf_load = ata_tf_load, | |
260 | .tf_read = ata_tf_read, | |
261 | .check_status = ata_check_status, | |
262 | .exec_command = ata_exec_command, | |
263 | .dev_select = ata_std_dev_select, | |
264 | ||
bf7551c4 JG |
265 | .freeze = ata_bmdma_freeze, |
266 | .thaw = ata_bmdma_thaw, | |
669a5db4 | 267 | .error_handler = sl82c105_error_handler, |
bf7551c4 | 268 | .post_internal_cmd = ata_bmdma_post_internal_cmd, |
c45a6328 | 269 | .cable_detect = ata_cable_40wire, |
669a5db4 JG |
270 | |
271 | .bmdma_setup = ata_bmdma_setup, | |
272 | .bmdma_start = sl82c105_bmdma_start, | |
273 | .bmdma_stop = sl82c105_bmdma_stop, | |
274 | .bmdma_status = ata_bmdma_status, | |
275 | ||
92ba5d02 | 276 | .qc_defer = sl82c105_qc_defer, |
669a5db4 JG |
277 | .qc_prep = ata_qc_prep, |
278 | .qc_issue = ata_qc_issue_prot, | |
bda30288 | 279 | |
0d5ff566 | 280 | .data_xfer = ata_data_xfer, |
669a5db4 JG |
281 | |
282 | .irq_handler = ata_interrupt, | |
283 | .irq_clear = ata_bmdma_irq_clear, | |
246ce3b6 | 284 | .irq_on = ata_irq_on, |
85cd7251 | 285 | |
81ad1837 | 286 | .port_start = ata_sff_port_start, |
85cd7251 | 287 | }; |
669a5db4 JG |
288 | |
289 | /** | |
290 | * sl82c105_bridge_revision - find bridge version | |
291 | * @pdev: PCI device for the ATA function | |
292 | * | |
293 | * Locates the PCI bridge associated with the ATA function and | |
294 | * providing it is a Winbond 553 reports the revision. If it cannot | |
295 | * find a revision or the right device it returns -1 | |
296 | */ | |
85cd7251 | 297 | |
669a5db4 JG |
298 | static int sl82c105_bridge_revision(struct pci_dev *pdev) |
299 | { | |
300 | struct pci_dev *bridge; | |
669a5db4 JG |
301 | |
302 | /* | |
303 | * The bridge should be part of the same device, but function 0. | |
304 | */ | |
305 | bridge = pci_get_slot(pdev->bus, | |
306 | PCI_DEVFN(PCI_SLOT(pdev->devfn), 0)); | |
307 | if (!bridge) | |
308 | return -1; | |
309 | ||
310 | /* | |
311 | * Make sure it is a Winbond 553 and is an ISA bridge. | |
312 | */ | |
313 | if (bridge->vendor != PCI_VENDOR_ID_WINBOND || | |
314 | bridge->device != PCI_DEVICE_ID_WINBOND_83C553 || | |
315 | bridge->class >> 8 != PCI_CLASS_BRIDGE_ISA) { | |
316 | pci_dev_put(bridge); | |
317 | return -1; | |
318 | } | |
319 | /* | |
320 | * We need to find function 0's revision, not function 1 | |
321 | */ | |
669a5db4 | 322 | pci_dev_put(bridge); |
44c10138 | 323 | return bridge->revision; |
669a5db4 JG |
324 | } |
325 | ||
85cd7251 | 326 | |
669a5db4 JG |
327 | static int sl82c105_init_one(struct pci_dev *dev, const struct pci_device_id *id) |
328 | { | |
1626aeb8 | 329 | static const struct ata_port_info info_dma = { |
669a5db4 | 330 | .sht = &sl82c105_sht, |
1d2808fd | 331 | .flags = ATA_FLAG_SLAVE_POSS, |
669a5db4 JG |
332 | .pio_mask = 0x1f, |
333 | .mwdma_mask = 0x07, | |
334 | .port_ops = &sl82c105_port_ops | |
335 | }; | |
1626aeb8 | 336 | static const struct ata_port_info info_early = { |
669a5db4 | 337 | .sht = &sl82c105_sht, |
1d2808fd | 338 | .flags = ATA_FLAG_SLAVE_POSS, |
669a5db4 JG |
339 | .pio_mask = 0x1f, |
340 | .port_ops = &sl82c105_port_ops | |
341 | }; | |
1626aeb8 TH |
342 | /* for now use only the first port */ |
343 | const struct ata_port_info *ppi[] = { &info_early, | |
92ba5d02 | 344 | NULL }; |
669a5db4 JG |
345 | u32 val; |
346 | int rev; | |
f08048e9 TH |
347 | int rc; |
348 | ||
349 | rc = pcim_enable_device(dev); | |
350 | if (rc) | |
351 | return rc; | |
669a5db4 JG |
352 | |
353 | rev = sl82c105_bridge_revision(dev); | |
85cd7251 | 354 | |
669a5db4 JG |
355 | if (rev == -1) |
356 | dev_printk(KERN_WARNING, &dev->dev, "pata_sl82c105: Unable to find bridge, disabling DMA.\n"); | |
357 | else if (rev <= 5) | |
358 | dev_printk(KERN_WARNING, &dev->dev, "pata_sl82c105: Early bridge revision, no DMA available.\n"); | |
1626aeb8 TH |
359 | else |
360 | ppi[0] = &info_dma; | |
85cd7251 | 361 | |
669a5db4 JG |
362 | pci_read_config_dword(dev, 0x40, &val); |
363 | val |= CTRL_P0EN | CTRL_P0F16 | CTRL_P1F16; | |
364 | pci_write_config_dword(dev, 0x40, val); | |
365 | ||
1626aeb8 | 366 | return ata_pci_init_one(dev, ppi); |
669a5db4 JG |
367 | } |
368 | ||
2d2744fc JG |
369 | static const struct pci_device_id sl82c105[] = { |
370 | { PCI_VDEVICE(WINBOND, PCI_DEVICE_ID_WINBOND_82C105), }, | |
371 | ||
372 | { }, | |
669a5db4 JG |
373 | }; |
374 | ||
375 | static struct pci_driver sl82c105_pci_driver = { | |
376 | .name = DRV_NAME, | |
377 | .id_table = sl82c105, | |
378 | .probe = sl82c105_init_one, | |
379 | .remove = ata_pci_remove_one | |
380 | }; | |
381 | ||
382 | static int __init sl82c105_init(void) | |
383 | { | |
384 | return pci_register_driver(&sl82c105_pci_driver); | |
385 | } | |
386 | ||
669a5db4 JG |
387 | static void __exit sl82c105_exit(void) |
388 | { | |
389 | pci_unregister_driver(&sl82c105_pci_driver); | |
390 | } | |
391 | ||
669a5db4 JG |
392 | MODULE_AUTHOR("Alan Cox"); |
393 | MODULE_DESCRIPTION("low-level driver for Sl82c105"); | |
394 | MODULE_LICENSE("GPL"); | |
395 | MODULE_DEVICE_TABLE(pci, sl82c105); | |
396 | MODULE_VERSION(DRV_VERSION); | |
397 | ||
398 | module_init(sl82c105_init); | |
399 | module_exit(sl82c105_exit); |