Commit | Line | Data |
---|---|---|
669a5db4 JG |
1 | /* |
2 | * pata_via.c - VIA PATA for new ATA layer | |
3 | * (C) 2005-2006 Red Hat Inc | |
669a5db4 JG |
4 | * |
5 | * Documentation | |
6 | * Most chipset documentation available under NDA only | |
7 | * | |
8 | * VIA version guide | |
9 | * VIA VT82C561 - early design, uses ata_generic currently | |
10 | * VIA VT82C576 - MWDMA, 33Mhz | |
11 | * VIA VT82C586 - MWDMA, 33Mhz | |
12 | * VIA VT82C586a - Added UDMA to 33Mhz | |
13 | * VIA VT82C586b - UDMA33 | |
14 | * VIA VT82C596a - Nonfunctional UDMA66 | |
15 | * VIA VT82C596b - Working UDMA66 | |
16 | * VIA VT82C686 - Nonfunctional UDMA66 | |
17 | * VIA VT82C686a - Working UDMA66 | |
18 | * VIA VT82C686b - Updated to UDMA100 | |
19 | * VIA VT8231 - UDMA100 | |
20 | * VIA VT8233 - UDMA100 | |
21 | * VIA VT8233a - UDMA133 | |
22 | * VIA VT8233c - UDMA100 | |
23 | * VIA VT8235 - UDMA133 | |
24 | * VIA VT8237 - UDMA133 | |
460f5318 | 25 | * VIA VT8237A - UDMA133 |
05c39e50 | 26 | * VIA VT8237S - UDMA133 |
75f609d2 | 27 | * VIA VT8251 - UDMA133 |
669a5db4 JG |
28 | * |
29 | * Most registers remain compatible across chips. Others start reserved | |
30 | * and acquire sensible semantics if set to 1 (eg cable detect). A few | |
31 | * exceptions exist, notably around the FIFO settings. | |
32 | * | |
33 | * One additional quirk of the VIA design is that like ALi they use few | |
34 | * PCI IDs for a lot of chips. | |
35 | * | |
36 | * Based heavily on: | |
37 | * | |
38 | * Version 3.38 | |
39 | * | |
40 | * VIA IDE driver for Linux. Supported southbridges: | |
41 | * | |
42 | * vt82c576, vt82c586, vt82c586a, vt82c586b, vt82c596a, vt82c596b, | |
43 | * vt82c686, vt82c686a, vt82c686b, vt8231, vt8233, vt8233c, vt8233a, | |
44 | * vt8235, vt8237 | |
45 | * | |
46 | * Copyright (c) 2000-2002 Vojtech Pavlik | |
47 | * | |
48 | * Based on the work of: | |
49 | * Michel Aubry | |
50 | * Jeff Garzik | |
51 | * Andre Hedrick | |
52 | ||
53 | */ | |
54 | ||
55 | #include <linux/kernel.h> | |
56 | #include <linux/module.h> | |
57 | #include <linux/pci.h> | |
58 | #include <linux/init.h> | |
59 | #include <linux/blkdev.h> | |
60 | #include <linux/delay.h> | |
61 | #include <scsi/scsi_host.h> | |
62 | #include <linux/libata.h> | |
cf5792d2 | 63 | #include <linux/dmi.h> |
669a5db4 JG |
64 | |
65 | #define DRV_NAME "pata_via" | |
b4746ed7 | 66 | #define DRV_VERSION "0.3.4" |
669a5db4 | 67 | |
669a5db4 | 68 | enum { |
460f5318 BZ |
69 | VIA_BAD_PREQ = 0x01, /* Crashes if PREQ# till DDACK# set */ |
70 | VIA_BAD_CLK66 = 0x02, /* 66 MHz clock doesn't work correctly */ | |
71 | VIA_SET_FIFO = 0x04, /* Needs to have FIFO split set */ | |
72 | VIA_NO_UNMASK = 0x08, /* Doesn't work with IRQ unmasking on */ | |
73 | VIA_BAD_ID = 0x10, /* Has wrong vendor ID (0x1107) */ | |
74 | VIA_BAD_AST = 0x20, /* Don't touch Address Setup Timing */ | |
75 | VIA_NO_ENABLES = 0x40, /* Has no enablebits */ | |
76 | VIA_SATA_PATA = 0x80, /* SATA/PATA combined configuration */ | |
669a5db4 JG |
77 | }; |
78 | ||
e4d866cd J |
79 | enum { |
80 | VIA_IDFLAG_SINGLE = (1 << 0), /* single channel controller) */ | |
81 | }; | |
82 | ||
669a5db4 JG |
83 | /* |
84 | * VIA SouthBridge chips. | |
85 | */ | |
86 | ||
87 | static const struct via_isa_bridge { | |
88 | const char *name; | |
89 | u16 id; | |
90 | u8 rev_min; | |
91 | u8 rev_max; | |
460f5318 BZ |
92 | u8 udma_mask; |
93 | u8 flags; | |
669a5db4 | 94 | } via_isa_bridges[] = { |
460f5318 BZ |
95 | { "vx855", PCI_DEVICE_ID_VIA_VX855, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST | VIA_SATA_PATA }, |
96 | { "vx800", PCI_DEVICE_ID_VIA_VX800, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST | VIA_SATA_PATA }, | |
97 | { "vt8261", PCI_DEVICE_ID_VIA_8261, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST }, | |
98 | { "vt8237s", PCI_DEVICE_ID_VIA_8237S, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST }, | |
99 | { "vt8251", PCI_DEVICE_ID_VIA_8251, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST }, | |
100 | { "cx700", PCI_DEVICE_ID_VIA_CX700, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST | VIA_SATA_PATA }, | |
101 | { "vt6410", PCI_DEVICE_ID_VIA_6410, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST | VIA_NO_ENABLES }, | |
102 | { "vt6415", PCI_DEVICE_ID_VIA_6415, 0x00, 0xff, ATA_UDMA6, VIA_BAD_AST | VIA_NO_ENABLES }, | |
103 | { "vt8237a", PCI_DEVICE_ID_VIA_8237A, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST }, | |
104 | { "vt8237", PCI_DEVICE_ID_VIA_8237, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST }, | |
105 | { "vt8235", PCI_DEVICE_ID_VIA_8235, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST }, | |
106 | { "vt8233a", PCI_DEVICE_ID_VIA_8233A, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST }, | |
107 | { "vt8233c", PCI_DEVICE_ID_VIA_8233C_0, 0x00, 0x2f, ATA_UDMA5, }, | |
108 | { "vt8233", PCI_DEVICE_ID_VIA_8233_0, 0x00, 0x2f, ATA_UDMA5, }, | |
109 | { "vt8231", PCI_DEVICE_ID_VIA_8231, 0x00, 0x2f, ATA_UDMA5, }, | |
110 | { "vt82c686b", PCI_DEVICE_ID_VIA_82C686, 0x40, 0x4f, ATA_UDMA5, }, | |
111 | { "vt82c686a", PCI_DEVICE_ID_VIA_82C686, 0x10, 0x2f, ATA_UDMA4, }, | |
112 | { "vt82c686", PCI_DEVICE_ID_VIA_82C686, 0x00, 0x0f, ATA_UDMA2, VIA_BAD_CLK66 }, | |
113 | { "vt82c596b", PCI_DEVICE_ID_VIA_82C596, 0x10, 0x2f, ATA_UDMA4, }, | |
114 | { "vt82c596a", PCI_DEVICE_ID_VIA_82C596, 0x00, 0x0f, ATA_UDMA2, VIA_BAD_CLK66 }, | |
115 | { "vt82c586b", PCI_DEVICE_ID_VIA_82C586_0, 0x47, 0x4f, ATA_UDMA2, VIA_SET_FIFO }, | |
116 | { "vt82c586b", PCI_DEVICE_ID_VIA_82C586_0, 0x40, 0x46, ATA_UDMA2, VIA_SET_FIFO | VIA_BAD_PREQ }, | |
117 | { "vt82c586b", PCI_DEVICE_ID_VIA_82C586_0, 0x30, 0x3f, ATA_UDMA2, VIA_SET_FIFO }, | |
118 | { "vt82c586a", PCI_DEVICE_ID_VIA_82C586_0, 0x20, 0x2f, ATA_UDMA2, VIA_SET_FIFO }, | |
119 | { "vt82c586", PCI_DEVICE_ID_VIA_82C586_0, 0x00, 0x0f, 0x00, VIA_SET_FIFO }, | |
120 | { "vt82c576", PCI_DEVICE_ID_VIA_82C576, 0x00, 0x2f, 0x00, VIA_SET_FIFO | VIA_NO_UNMASK }, | |
121 | { "vt82c576", PCI_DEVICE_ID_VIA_82C576, 0x00, 0x2f, 0x00, VIA_SET_FIFO | VIA_NO_UNMASK | VIA_BAD_ID }, | |
122 | { "vtxxxx", PCI_DEVICE_ID_VIA_ANON, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST }, | |
669a5db4 JG |
123 | { NULL } |
124 | }; | |
125 | ||
b4746ed7 AC |
126 | struct via_port { |
127 | u8 cached_device; | |
128 | }; | |
cf5792d2 AC |
129 | |
130 | /* | |
131 | * Cable special cases | |
132 | */ | |
133 | ||
1855256c | 134 | static const struct dmi_system_id cable_dmi_table[] = { |
cf5792d2 AC |
135 | { |
136 | .ident = "Acer Ferrari 3400", | |
137 | .matches = { | |
138 | DMI_MATCH(DMI_BOARD_VENDOR, "Acer,Inc."), | |
139 | DMI_MATCH(DMI_BOARD_NAME, "Ferrari 3400"), | |
140 | }, | |
141 | }, | |
142 | { } | |
143 | }; | |
144 | ||
145 | static int via_cable_override(struct pci_dev *pdev) | |
146 | { | |
147 | /* Systems by DMI */ | |
148 | if (dmi_check_system(cable_dmi_table)) | |
149 | return 1; | |
9edbdbea AC |
150 | /* Arima W730-K8/Targa Visionary 811/... */ |
151 | if (pdev->subsystem_vendor == 0x161F && pdev->subsystem_device == 0x2032) | |
152 | return 1; | |
cf5792d2 AC |
153 | return 0; |
154 | } | |
155 | ||
156 | ||
669a5db4 JG |
157 | /** |
158 | * via_cable_detect - cable detection | |
159 | * @ap: ATA port | |
160 | * | |
161 | * Perform cable detection. Actually for the VIA case the BIOS | |
162 | * already did this for us. We read the values provided by the | |
163 | * BIOS. If you are using an 8235 in a non-PC configuration you | |
164 | * may need to update this code. | |
165 | * | |
166 | * Hotplug also impacts on this. | |
167 | */ | |
168 | ||
169 | static int via_cable_detect(struct ata_port *ap) { | |
97cb81c3 | 170 | const struct via_isa_bridge *config = ap->host->private_data; |
669a5db4 JG |
171 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); |
172 | u32 ata66; | |
173 | ||
cf5792d2 AC |
174 | if (via_cable_override(pdev)) |
175 | return ATA_CBL_PATA40_SHORT; | |
176 | ||
7585eb1b TH |
177 | if ((config->flags & VIA_SATA_PATA) && ap->port_no == 0) |
178 | return ATA_CBL_SATA; | |
179 | ||
97cb81c3 | 180 | /* Early chips are 40 wire */ |
460f5318 | 181 | if (config->udma_mask < ATA_UDMA4) |
97cb81c3 AC |
182 | return ATA_CBL_PATA40; |
183 | /* UDMA 66 chips have only drive side logic */ | |
460f5318 | 184 | else if (config->udma_mask < ATA_UDMA5) |
97cb81c3 AC |
185 | return ATA_CBL_PATA_UNK; |
186 | /* UDMA 100 or later */ | |
669a5db4 JG |
187 | pci_read_config_dword(pdev, 0x50, &ata66); |
188 | /* Check both the drive cable reporting bits, we might not have | |
189 | two drives */ | |
190 | if (ata66 & (0x10100000 >> (16 * ap->port_no))) | |
191 | return ATA_CBL_PATA80; | |
7d73a363 | 192 | /* Check with ACPI so we can spot BIOS reported SATA bridges */ |
021ee9a6 TH |
193 | if (ata_acpi_init_gtm(ap) && |
194 | ata_acpi_cbl_80wire(ap, ata_acpi_init_gtm(ap))) | |
7d73a363 | 195 | return ATA_CBL_PATA80; |
97cb81c3 | 196 | return ATA_CBL_PATA40; |
669a5db4 JG |
197 | } |
198 | ||
cc0680a5 | 199 | static int via_pre_reset(struct ata_link *link, unsigned long deadline) |
669a5db4 | 200 | { |
cc0680a5 | 201 | struct ata_port *ap = link->ap; |
669a5db4 JG |
202 | const struct via_isa_bridge *config = ap->host->private_data; |
203 | ||
204 | if (!(config->flags & VIA_NO_ENABLES)) { | |
205 | static const struct pci_bits via_enable_bits[] = { | |
206 | { 0x40, 1, 0x02, 0x02 }, | |
207 | { 0x40, 1, 0x01, 0x01 } | |
208 | }; | |
669a5db4 | 209 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); |
c961922b AC |
210 | if (!pci_test_config_bits(pdev, &via_enable_bits[ap->port_no])) |
211 | return -ENOENT; | |
669a5db4 | 212 | } |
d4b2bab4 | 213 | |
9363c382 | 214 | return ata_sff_prereset(link, deadline); |
669a5db4 JG |
215 | } |
216 | ||
217 | ||
669a5db4 | 218 | /** |
f777582f | 219 | * via_do_set_mode - set transfer mode data |
669a5db4 JG |
220 | * @ap: ATA interface |
221 | * @adev: ATA device | |
222 | * @mode: ATA mode being programmed | |
669a5db4 JG |
223 | * @set_ast: Set to program address setup |
224 | * @udma_type: UDMA mode/format of registers | |
225 | * | |
226 | * Program the VIA registers for DMA and PIO modes. Uses the ata timing | |
227 | * support in order to compute modes. | |
228 | * | |
229 | * FIXME: Hotplug will require we serialize multiple mode changes | |
230 | * on the two channels. | |
231 | */ | |
232 | ||
460f5318 BZ |
233 | static void via_do_set_mode(struct ata_port *ap, struct ata_device *adev, |
234 | int mode, int set_ast, int udma_type) | |
669a5db4 JG |
235 | { |
236 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); | |
237 | struct ata_device *peer = ata_dev_pair(adev); | |
238 | struct ata_timing t, p; | |
460f5318 | 239 | static int via_clock = 33333; /* Bus clock in kHZ */ |
669a5db4 | 240 | unsigned long T = 1000000000 / via_clock; |
460f5318 | 241 | unsigned long UT = T; |
669a5db4 JG |
242 | int ut; |
243 | int offset = 3 - (2*ap->port_no) - adev->devno; | |
244 | ||
460f5318 BZ |
245 | switch (udma_type) { |
246 | case ATA_UDMA4: | |
247 | UT = T / 2; break; | |
248 | case ATA_UDMA5: | |
249 | UT = T / 3; break; | |
250 | case ATA_UDMA6: | |
251 | UT = T / 4; break; | |
252 | } | |
253 | ||
669a5db4 JG |
254 | /* Calculate the timing values we require */ |
255 | ata_timing_compute(adev, mode, &t, T, UT); | |
256 | ||
257 | /* We share 8bit timing so we must merge the constraints */ | |
258 | if (peer) { | |
259 | if (peer->pio_mode) { | |
260 | ata_timing_compute(peer, peer->pio_mode, &p, T, UT); | |
261 | ata_timing_merge(&p, &t, &t, ATA_TIMING_8BIT); | |
262 | } | |
263 | } | |
264 | ||
265 | /* Address setup is programmable but breaks on UDMA133 setups */ | |
266 | if (set_ast) { | |
267 | u8 setup; /* 2 bits per drive */ | |
268 | int shift = 2 * offset; | |
269 | ||
270 | pci_read_config_byte(pdev, 0x4C, &setup); | |
271 | setup &= ~(3 << shift); | |
f777582f | 272 | setup |= (clamp_val(t.setup, 1, 4) - 1) << shift; |
669a5db4 JG |
273 | pci_write_config_byte(pdev, 0x4C, setup); |
274 | } | |
275 | ||
276 | /* Load the PIO mode bits */ | |
277 | pci_write_config_byte(pdev, 0x4F - ap->port_no, | |
07633b5d | 278 | ((clamp_val(t.act8b, 1, 16) - 1) << 4) | (clamp_val(t.rec8b, 1, 16) - 1)); |
669a5db4 | 279 | pci_write_config_byte(pdev, 0x48 + offset, |
07633b5d | 280 | ((clamp_val(t.active, 1, 16) - 1) << 4) | (clamp_val(t.recover, 1, 16) - 1)); |
669a5db4 JG |
281 | |
282 | /* Load the UDMA bits according to type */ | |
460f5318 BZ |
283 | switch (udma_type) { |
284 | case ATA_UDMA2: | |
285 | default: | |
286 | ut = t.udma ? (0xe0 | (clamp_val(t.udma, 2, 5) - 2)) : 0x03; | |
287 | break; | |
288 | case ATA_UDMA4: | |
289 | ut = t.udma ? (0xe8 | (clamp_val(t.udma, 2, 9) - 2)) : 0x0f; | |
290 | break; | |
291 | case ATA_UDMA5: | |
292 | ut = t.udma ? (0xe0 | (clamp_val(t.udma, 2, 9) - 2)) : 0x07; | |
293 | break; | |
294 | case ATA_UDMA6: | |
295 | ut = t.udma ? (0xe0 | (clamp_val(t.udma, 2, 9) - 2)) : 0x07; | |
296 | break; | |
669a5db4 | 297 | } |
08ebd43d | 298 | |
669a5db4 | 299 | /* Set UDMA unless device is not UDMA capable */ |
c4d8a200 BZ |
300 | if (udma_type) { |
301 | u8 udma_etc; | |
08ebd43d | 302 | |
c4d8a200 | 303 | pci_read_config_byte(pdev, 0x50 + offset, &udma_etc); |
08ebd43d | 304 | |
c4d8a200 BZ |
305 | /* clear transfer mode bit */ |
306 | udma_etc &= ~0x20; | |
307 | ||
308 | if (t.udma) { | |
309 | /* preserve 80-wire cable detection bit */ | |
310 | udma_etc &= 0x10; | |
311 | udma_etc |= ut; | |
312 | } | |
313 | ||
314 | pci_write_config_byte(pdev, 0x50 + offset, udma_etc); | |
08ebd43d | 315 | } |
669a5db4 JG |
316 | } |
317 | ||
318 | static void via_set_piomode(struct ata_port *ap, struct ata_device *adev) | |
319 | { | |
320 | const struct via_isa_bridge *config = ap->host->private_data; | |
321 | int set_ast = (config->flags & VIA_BAD_AST) ? 0 : 1; | |
669a5db4 | 322 | |
460f5318 | 323 | via_do_set_mode(ap, adev, adev->pio_mode, set_ast, config->udma_mask); |
669a5db4 JG |
324 | } |
325 | ||
326 | static void via_set_dmamode(struct ata_port *ap, struct ata_device *adev) | |
327 | { | |
328 | const struct via_isa_bridge *config = ap->host->private_data; | |
329 | int set_ast = (config->flags & VIA_BAD_AST) ? 0 : 1; | |
669a5db4 | 330 | |
460f5318 | 331 | via_do_set_mode(ap, adev, adev->dma_mode, set_ast, config->udma_mask); |
669a5db4 JG |
332 | } |
333 | ||
10734fc8 AC |
334 | /** |
335 | * via_mode_filter - filter buggy device/mode pairs | |
336 | * @dev: ATA device | |
337 | * @mask: Mode bitmask | |
338 | * | |
339 | * We need to apply some minimal filtering for old controllers and at least | |
340 | * one breed of Transcend SSD. Return the updated mask. | |
341 | */ | |
342 | ||
343 | static unsigned long via_mode_filter(struct ata_device *dev, unsigned long mask) | |
344 | { | |
345 | struct ata_host *host = dev->link->ap->host; | |
346 | const struct via_isa_bridge *config = host->private_data; | |
347 | unsigned char model_num[ATA_ID_PROD_LEN + 1]; | |
348 | ||
349 | if (config->id == PCI_DEVICE_ID_VIA_82C586_0) { | |
350 | ata_id_c_string(dev->id, model_num, ATA_ID_PROD, sizeof(model_num)); | |
351 | if (strcmp(model_num, "TS64GSSD25-M") == 0) { | |
352 | ata_dev_printk(dev, KERN_WARNING, | |
353 | "disabling UDMA mode due to reported lockups with this device.\n"); | |
354 | mask &= ~ ATA_MASK_UDMA; | |
355 | } | |
356 | } | |
357 | return ata_bmdma_mode_filter(dev, mask); | |
358 | } | |
359 | ||
bfce5e01 | 360 | /** |
ff04715b | 361 | * via_tf_load - send taskfile registers to host controller |
bfce5e01 J |
362 | * @ap: Port to which output is sent |
363 | * @tf: ATA taskfile register set | |
364 | * | |
365 | * Outputs ATA taskfile to standard ATA host controller. | |
366 | * | |
367 | * Note: This is to fix the internal bug of via chipsets, which | |
ff04715b TH |
368 | * will reset the device register after changing the IEN bit on |
369 | * ctl register | |
bfce5e01 | 370 | */ |
ff04715b | 371 | static void via_tf_load(struct ata_port *ap, const struct ata_taskfile *tf) |
bfce5e01 | 372 | { |
b4746ed7 AC |
373 | struct ata_ioports *ioaddr = &ap->ioaddr; |
374 | struct via_port *vp = ap->private_data; | |
375 | unsigned int is_addr = tf->flags & ATA_TFLAG_ISADDR; | |
376 | int newctl = 0; | |
377 | ||
378 | if (tf->ctl != ap->last_ctl) { | |
379 | iowrite8(tf->ctl, ioaddr->ctl_addr); | |
380 | ap->last_ctl = tf->ctl; | |
381 | ata_wait_idle(ap); | |
382 | newctl = 1; | |
383 | } | |
384 | ||
385 | if (tf->flags & ATA_TFLAG_DEVICE) { | |
386 | iowrite8(tf->device, ioaddr->device_addr); | |
387 | vp->cached_device = tf->device; | |
388 | } else if (newctl) | |
389 | iowrite8(vp->cached_device, ioaddr->device_addr); | |
390 | ||
391 | if (is_addr && (tf->flags & ATA_TFLAG_LBA48)) { | |
392 | WARN_ON_ONCE(!ioaddr->ctl_addr); | |
393 | iowrite8(tf->hob_feature, ioaddr->feature_addr); | |
394 | iowrite8(tf->hob_nsect, ioaddr->nsect_addr); | |
395 | iowrite8(tf->hob_lbal, ioaddr->lbal_addr); | |
396 | iowrite8(tf->hob_lbam, ioaddr->lbam_addr); | |
397 | iowrite8(tf->hob_lbah, ioaddr->lbah_addr); | |
398 | VPRINTK("hob: feat 0x%X nsect 0x%X, lba 0x%X 0x%X 0x%X\n", | |
399 | tf->hob_feature, | |
400 | tf->hob_nsect, | |
401 | tf->hob_lbal, | |
402 | tf->hob_lbam, | |
403 | tf->hob_lbah); | |
404 | } | |
bfce5e01 | 405 | |
b4746ed7 AC |
406 | if (is_addr) { |
407 | iowrite8(tf->feature, ioaddr->feature_addr); | |
408 | iowrite8(tf->nsect, ioaddr->nsect_addr); | |
409 | iowrite8(tf->lbal, ioaddr->lbal_addr); | |
410 | iowrite8(tf->lbam, ioaddr->lbam_addr); | |
411 | iowrite8(tf->lbah, ioaddr->lbah_addr); | |
412 | VPRINTK("feat 0x%X nsect 0x%X lba 0x%X 0x%X 0x%X\n", | |
413 | tf->feature, | |
414 | tf->nsect, | |
415 | tf->lbal, | |
416 | tf->lbam, | |
417 | tf->lbah); | |
bfce5e01 | 418 | } |
b4746ed7 AC |
419 | |
420 | ata_wait_idle(ap); | |
421 | } | |
422 | ||
423 | static int via_port_start(struct ata_port *ap) | |
424 | { | |
425 | struct via_port *vp; | |
426 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); | |
427 | ||
428 | int ret = ata_sff_port_start(ap); | |
429 | if (ret < 0) | |
430 | return ret; | |
431 | ||
432 | vp = devm_kzalloc(&pdev->dev, sizeof(struct via_port), GFP_KERNEL); | |
433 | if (vp == NULL) | |
434 | return -ENOMEM; | |
435 | ap->private_data = vp; | |
436 | return 0; | |
bfce5e01 J |
437 | } |
438 | ||
669a5db4 | 439 | static struct scsi_host_template via_sht = { |
68d1d07b | 440 | ATA_BMDMA_SHT(DRV_NAME), |
669a5db4 JG |
441 | }; |
442 | ||
443 | static struct ata_port_operations via_port_ops = { | |
029cfd6b TH |
444 | .inherits = &ata_bmdma_port_ops, |
445 | .cable_detect = via_cable_detect, | |
669a5db4 JG |
446 | .set_piomode = via_set_piomode, |
447 | .set_dmamode = via_set_dmamode, | |
a1efdaba | 448 | .prereset = via_pre_reset, |
ff04715b | 449 | .sff_tf_load = via_tf_load, |
b4746ed7 | 450 | .port_start = via_port_start, |
10734fc8 | 451 | .mode_filter = via_mode_filter, |
669a5db4 JG |
452 | }; |
453 | ||
454 | static struct ata_port_operations via_port_ops_noirq = { | |
029cfd6b | 455 | .inherits = &via_port_ops, |
5682ed33 | 456 | .sff_data_xfer = ata_sff_data_xfer_noirq, |
669a5db4 JG |
457 | }; |
458 | ||
627d2d32 A |
459 | /** |
460 | * via_config_fifo - set up the FIFO | |
461 | * @pdev: PCI device | |
462 | * @flags: configuration flags | |
463 | * | |
3a4fa0a2 | 464 | * Set the FIFO properties for this device if necessary. Used both on |
627d2d32 A |
465 | * set up and on and the resume path |
466 | */ | |
467 | ||
468 | static void via_config_fifo(struct pci_dev *pdev, unsigned int flags) | |
469 | { | |
470 | u8 enable; | |
f20b16ff | 471 | |
627d2d32 A |
472 | /* 0x40 low bits indicate enabled channels */ |
473 | pci_read_config_byte(pdev, 0x40 , &enable); | |
474 | enable &= 3; | |
f20b16ff | 475 | |
627d2d32 | 476 | if (flags & VIA_SET_FIFO) { |
73720861 | 477 | static const u8 fifo_setting[4] = {0x00, 0x60, 0x00, 0x20}; |
627d2d32 A |
478 | u8 fifo; |
479 | ||
480 | pci_read_config_byte(pdev, 0x43, &fifo); | |
481 | ||
482 | /* Clear PREQ# until DDACK# for errata */ | |
483 | if (flags & VIA_BAD_PREQ) | |
484 | fifo &= 0x7F; | |
485 | else | |
486 | fifo &= 0x9f; | |
487 | /* Turn on FIFO for enabled channels */ | |
488 | fifo |= fifo_setting[enable]; | |
489 | pci_write_config_byte(pdev, 0x43, fifo); | |
490 | } | |
491 | } | |
492 | ||
669a5db4 JG |
493 | /** |
494 | * via_init_one - discovery callback | |
627d2d32 | 495 | * @pdev: PCI device |
669a5db4 JG |
496 | * @id: PCI table info |
497 | * | |
498 | * A VIA IDE interface has been discovered. Figure out what revision | |
499 | * and perform configuration work before handing it to the ATA layer | |
500 | */ | |
501 | ||
502 | static int via_init_one(struct pci_dev *pdev, const struct pci_device_id *id) | |
503 | { | |
504 | /* Early VIA without UDMA support */ | |
1626aeb8 | 505 | static const struct ata_port_info via_mwdma_info = { |
464cf177 | 506 | .flags = ATA_FLAG_SLAVE_POSS, |
14bdef98 EIB |
507 | .pio_mask = ATA_PIO4, |
508 | .mwdma_mask = ATA_MWDMA2, | |
669a5db4 JG |
509 | .port_ops = &via_port_ops |
510 | }; | |
511 | /* Ditto with IRQ masking required */ | |
1626aeb8 | 512 | static const struct ata_port_info via_mwdma_info_borked = { |
464cf177 | 513 | .flags = ATA_FLAG_SLAVE_POSS, |
14bdef98 EIB |
514 | .pio_mask = ATA_PIO4, |
515 | .mwdma_mask = ATA_MWDMA2, | |
669a5db4 JG |
516 | .port_ops = &via_port_ops_noirq, |
517 | }; | |
518 | /* VIA UDMA 33 devices (and borked 66) */ | |
1626aeb8 | 519 | static const struct ata_port_info via_udma33_info = { |
464cf177 | 520 | .flags = ATA_FLAG_SLAVE_POSS, |
14bdef98 EIB |
521 | .pio_mask = ATA_PIO4, |
522 | .mwdma_mask = ATA_MWDMA2, | |
bf6263a8 | 523 | .udma_mask = ATA_UDMA2, |
669a5db4 JG |
524 | .port_ops = &via_port_ops |
525 | }; | |
526 | /* VIA UDMA 66 devices */ | |
1626aeb8 | 527 | static const struct ata_port_info via_udma66_info = { |
464cf177 | 528 | .flags = ATA_FLAG_SLAVE_POSS, |
14bdef98 EIB |
529 | .pio_mask = ATA_PIO4, |
530 | .mwdma_mask = ATA_MWDMA2, | |
bf6263a8 | 531 | .udma_mask = ATA_UDMA4, |
669a5db4 JG |
532 | .port_ops = &via_port_ops |
533 | }; | |
534 | /* VIA UDMA 100 devices */ | |
1626aeb8 | 535 | static const struct ata_port_info via_udma100_info = { |
464cf177 | 536 | .flags = ATA_FLAG_SLAVE_POSS, |
14bdef98 EIB |
537 | .pio_mask = ATA_PIO4, |
538 | .mwdma_mask = ATA_MWDMA2, | |
bf6263a8 | 539 | .udma_mask = ATA_UDMA5, |
669a5db4 JG |
540 | .port_ops = &via_port_ops |
541 | }; | |
542 | /* UDMA133 with bad AST (All current 133) */ | |
1626aeb8 | 543 | static const struct ata_port_info via_udma133_info = { |
464cf177 | 544 | .flags = ATA_FLAG_SLAVE_POSS, |
14bdef98 EIB |
545 | .pio_mask = ATA_PIO4, |
546 | .mwdma_mask = ATA_MWDMA2, | |
bf6263a8 | 547 | .udma_mask = ATA_UDMA6, /* FIXME: should check north bridge */ |
669a5db4 JG |
548 | .port_ops = &via_port_ops |
549 | }; | |
887125e3 | 550 | const struct ata_port_info *ppi[] = { NULL, NULL }; |
7095e3eb | 551 | struct pci_dev *isa; |
669a5db4 JG |
552 | const struct via_isa_bridge *config; |
553 | static int printed_version; | |
669a5db4 JG |
554 | u8 enable; |
555 | u32 timing; | |
e4d866cd | 556 | unsigned long flags = id->driver_data; |
f08048e9 | 557 | int rc; |
669a5db4 JG |
558 | |
559 | if (!printed_version++) | |
560 | dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n"); | |
561 | ||
f08048e9 TH |
562 | rc = pcim_enable_device(pdev); |
563 | if (rc) | |
564 | return rc; | |
565 | ||
e4d866cd J |
566 | if (flags & VIA_IDFLAG_SINGLE) |
567 | ppi[1] = &ata_dummy_port_info; | |
568 | ||
669a5db4 JG |
569 | /* To find out how the IDE will behave and what features we |
570 | actually have to look at the bridge not the IDE controller */ | |
e4d866cd J |
571 | for (config = via_isa_bridges; config->id != PCI_DEVICE_ID_VIA_ANON; |
572 | config++) | |
669a5db4 JG |
573 | if ((isa = pci_get_device(PCI_VENDOR_ID_VIA + |
574 | !!(config->flags & VIA_BAD_ID), | |
575 | config->id, NULL))) { | |
7095e3eb JS |
576 | u8 rev = isa->revision; |
577 | pci_dev_put(isa); | |
669a5db4 | 578 | |
7095e3eb | 579 | if (rev >= config->rev_min && rev <= config->rev_max) |
669a5db4 | 580 | break; |
669a5db4 JG |
581 | } |
582 | ||
11f6400e AC |
583 | if (!(config->flags & VIA_NO_ENABLES)) { |
584 | /* 0x40 low bits indicate enabled channels */ | |
585 | pci_read_config_byte(pdev, 0x40 , &enable); | |
586 | enable &= 3; | |
587 | if (enable == 0) | |
588 | return -ENODEV; | |
669a5db4 JG |
589 | } |
590 | ||
591 | /* Initialise the FIFO for the enabled channels. */ | |
627d2d32 | 592 | via_config_fifo(pdev, config->flags); |
f20b16ff | 593 | |
669a5db4 | 594 | /* Clock set up */ |
460f5318 BZ |
595 | switch (config->udma_mask) { |
596 | case 0x00: | |
597 | if (config->flags & VIA_NO_UNMASK) | |
598 | ppi[0] = &via_mwdma_info_borked; | |
599 | else | |
600 | ppi[0] = &via_mwdma_info; | |
601 | break; | |
602 | case ATA_UDMA2: | |
603 | ppi[0] = &via_udma33_info; | |
604 | break; | |
605 | case ATA_UDMA4: | |
606 | ppi[0] = &via_udma66_info; | |
607 | break; | |
608 | case ATA_UDMA5: | |
609 | ppi[0] = &via_udma100_info; | |
610 | break; | |
611 | case ATA_UDMA6: | |
612 | ppi[0] = &via_udma133_info; | |
613 | break; | |
614 | default: | |
615 | WARN_ON(1); | |
616 | return -ENODEV; | |
617 | } | |
669a5db4 JG |
618 | |
619 | if (config->flags & VIA_BAD_CLK66) { | |
620 | /* Disable the 66MHz clock on problem devices */ | |
621 | pci_read_config_dword(pdev, 0x50, &timing); | |
622 | timing &= ~0x80008; | |
623 | pci_write_config_dword(pdev, 0x50, timing); | |
624 | } | |
625 | ||
626 | /* We have established the device type, now fire it up */ | |
16ea0fc9 | 627 | return ata_pci_sff_init_one(pdev, ppi, &via_sht, (void *)config, 0); |
669a5db4 JG |
628 | } |
629 | ||
438ac6d5 | 630 | #ifdef CONFIG_PM |
627d2d32 A |
631 | /** |
632 | * via_reinit_one - reinit after resume | |
633 | * @pdev; PCI device | |
634 | * | |
635 | * Called when the VIA PATA device is resumed. We must then | |
636 | * reconfigure the fifo and other setup we may have altered. In | |
637 | * addition the kernel needs to have the resume methods on PCI | |
638 | * quirk supported. | |
639 | */ | |
640 | ||
641 | static int via_reinit_one(struct pci_dev *pdev) | |
642 | { | |
643 | u32 timing; | |
644 | struct ata_host *host = dev_get_drvdata(&pdev->dev); | |
645 | const struct via_isa_bridge *config = host->private_data; | |
f08048e9 TH |
646 | int rc; |
647 | ||
648 | rc = ata_pci_device_do_resume(pdev); | |
649 | if (rc) | |
650 | return rc; | |
f20b16ff | 651 | |
627d2d32 A |
652 | via_config_fifo(pdev, config->flags); |
653 | ||
460f5318 | 654 | if (config->udma_mask == ATA_UDMA4) { |
627d2d32 A |
655 | /* The 66 MHz devices require we enable the clock */ |
656 | pci_read_config_dword(pdev, 0x50, &timing); | |
657 | timing |= 0x80008; | |
658 | pci_write_config_dword(pdev, 0x50, timing); | |
659 | } | |
660 | if (config->flags & VIA_BAD_CLK66) { | |
661 | /* Disable the 66MHz clock on problem devices */ | |
662 | pci_read_config_dword(pdev, 0x50, &timing); | |
663 | timing &= ~0x80008; | |
664 | pci_write_config_dword(pdev, 0x50, timing); | |
665 | } | |
f08048e9 TH |
666 | |
667 | ata_host_resume(host); | |
668 | return 0; | |
627d2d32 | 669 | } |
438ac6d5 | 670 | #endif |
627d2d32 | 671 | |
669a5db4 | 672 | static const struct pci_device_id via[] = { |
5955c7a2 | 673 | { PCI_VDEVICE(VIA, 0x0415), }, |
52df0ee0 JG |
674 | { PCI_VDEVICE(VIA, 0x0571), }, |
675 | { PCI_VDEVICE(VIA, 0x0581), }, | |
676 | { PCI_VDEVICE(VIA, 0x1571), }, | |
677 | { PCI_VDEVICE(VIA, 0x3164), }, | |
678 | { PCI_VDEVICE(VIA, 0x5324), }, | |
e4d866cd | 679 | { PCI_VDEVICE(VIA, 0xC409), VIA_IDFLAG_SINGLE }, |
2d2744fc JG |
680 | |
681 | { }, | |
669a5db4 JG |
682 | }; |
683 | ||
684 | static struct pci_driver via_pci_driver = { | |
2d2744fc | 685 | .name = DRV_NAME, |
669a5db4 JG |
686 | .id_table = via, |
687 | .probe = via_init_one, | |
627d2d32 | 688 | .remove = ata_pci_remove_one, |
438ac6d5 | 689 | #ifdef CONFIG_PM |
627d2d32 A |
690 | .suspend = ata_pci_device_suspend, |
691 | .resume = via_reinit_one, | |
438ac6d5 | 692 | #endif |
669a5db4 JG |
693 | }; |
694 | ||
695 | static int __init via_init(void) | |
696 | { | |
697 | return pci_register_driver(&via_pci_driver); | |
698 | } | |
699 | ||
669a5db4 JG |
700 | static void __exit via_exit(void) |
701 | { | |
702 | pci_unregister_driver(&via_pci_driver); | |
703 | } | |
704 | ||
669a5db4 JG |
705 | MODULE_AUTHOR("Alan Cox"); |
706 | MODULE_DESCRIPTION("low-level driver for VIA PATA"); | |
707 | MODULE_LICENSE("GPL"); | |
708 | MODULE_DEVICE_TABLE(pci, via); | |
709 | MODULE_VERSION(DRV_VERSION); | |
710 | ||
711 | module_init(via_init); | |
712 | module_exit(via_exit); |